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Viewing changes to arch/arm/mach-omap2/gpmc.c

  • Committer: Bazaar Package Importer
  • Author(s): John Rigby, Upstream Fixes, Andy Green, John Rigby
  • Date: 2011-04-14 12:16:06 UTC
  • Revision ID: james.westby@ubuntu.com-20110414121606-b77podkyqgr2oix7
Tags: 2.6.38-1002.3
https://launchpad.net/bugs/745737
https://launchpad.net/bugs/747639
https://launchpad.net/bugs/752900
https://launchpad.net/bugs/745737
https://launchpad.net/bugs/732842
https://launchpad.net/bugs/732912
[ Upstream Fixes ]

* MUSB: shutdown: Make sure block is awake before doing shutdown
  - LP: #745737
* Fixed gpio polarity of gpio USB-phy reset.
  - LP: #747639

[ Andy Green ]

* LINARO: SAUCE: disable CONFIG_OMAP_RESET_CLOCKS
  - LP: #752900

[ John Rigby ]

* Rebase to new upstreams:
  Linux v2.6.38.1
  linaro-linux-2.6.38-upstream-29Mar2011
  Ubuntu-2.6.38-7.35
* SAUCE: OMAP4: clock: wait for module to become accessible on
  a clk enable
  - LP: #745737
* Rebase to new upstreams:
  Linux v2.6.38.2
  linaro-linux-2.6.38-upstream-5Apr2011
  Ubuntu-2.6.38-8.41
  - LP: #732842
* Update configs for device tree, dvfs and lttng
* LINARO: add building of dtb's
* LINARO: SAUCE: Disable lowest operating freqs on omap34xx
  - LP: #732912

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Lines of Context:
arch/arm/mach-omap2/gpmc.c
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 */
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#undef DEBUG
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/err.h>
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <linux/module.h>
 
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#include <linux/interrupt.h>
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#include <asm/mach-types.h>
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#include <plat/gpmc.h>
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#define GPMC_CHUNK_SHIFT        24              /* 16 MB */
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#define GPMC_SECTION_SHIFT      28              /* 128 MB */
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#define PREFETCH_FIFOTHRESHOLD  (0x40 << 8)
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#define CS_NUM_SHIFT            24
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#define ENABLE_PREFETCH         (0x1 << 7)
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#define DMA_MPU_MODE            2
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static struct clk *gpmc_l3_clk;
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static irqreturn_t gpmc_handle_irq(int irq, void *dev);
 
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static void gpmc_write_reg(int idx, u32 val)
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{
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        __raw_writel(val, gpmc_base + idx);
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        u32 regval = 0;
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        switch (cmd) {
 
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        case GPMC_ENABLE_IRQ:
 
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                gpmc_write_reg(GPMC_IRQENABLE, wval);
 
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                break;
 
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        case GPMC_SET_IRQ_STATUS:
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                gpmc_write_reg(GPMC_IRQSTATUS, wval);
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                break;
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/**
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 * gpmc_prefetch_enable - configures and starts prefetch transfer
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 * @cs: cs (chip select) number
 
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 * @fifo_th: fifo threshold to be used for read/ write
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 * @dma_mode: dma mode enable (1) or disable (0)
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 * @u32_count: number of bytes to be transferred
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 * @is_write: prefetch read(0) or write post(1) mode
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 */
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int gpmc_prefetch_enable(int cs, int dma_mode,
 
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int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
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                                unsigned int u32_count, int is_write)
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{
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        if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) {
 
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        if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) {
 
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                pr_err("gpmc: fifo threshold is not supported\n");
 
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                return -1;
 
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        } else if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) {
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                /* Set the amount of bytes to be prefetched */
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                gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count);
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                 * enable the engine. Set which cs is has requested for.
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                 */
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                gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs << CS_NUM_SHIFT) |
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                                        PREFETCH_FIFOTHRESHOLD |
 
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                                        PREFETCH_FIFOTHRESHOLD(fifo_th) |
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                                        ENABLE_PREFETCH |
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                                        (dma_mode << DMA_MPU_MODE) |
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                                        (0x1 & is_write)));
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        }
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}
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void __init gpmc_init(void)
 
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static int __init gpmc_init(void)
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{
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        u32 l;
 
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        u32 l, irq;
 
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        int cs, ret = -EINVAL;
 
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        int gpmc_irq;
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        char *ck = NULL;
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        if (cpu_is_omap24xx()) {
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                        l = OMAP2420_GPMC_BASE;
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                else
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                        l = OMAP34XX_GPMC_BASE;
 
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                gpmc_irq = INT_34XX_GPMC_IRQ;
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        } else if (cpu_is_omap34xx()) {
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                ck = "gpmc_fck";
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                l = OMAP34XX_GPMC_BASE;
 
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                gpmc_irq = INT_34XX_GPMC_IRQ;
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        } else if (cpu_is_omap44xx()) {
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                ck = "gpmc_ck";
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                l = OMAP44XX_GPMC_BASE;
 
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                gpmc_irq = OMAP44XX_IRQ_GPMC;
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        }
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        if (WARN_ON(!ck))
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                return;
 
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                return ret;
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        gpmc_l3_clk = clk_get(NULL, ck);
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        if (IS_ERR(gpmc_l3_clk)) {
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        l |= (0x02 << 3) | (1 << 0);
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        gpmc_write_reg(GPMC_SYSCONFIG, l);
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        gpmc_mem_init();
 
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        /* initalize the irq_chained */
 
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        irq = OMAP_GPMC_IRQ_BASE;
 
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        for (cs = 0; cs < GPMC_CS_NUM; cs++) {
 
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                set_irq_chip_and_handler(irq, &dummy_irq_chip,
 
747
                                                handle_simple_irq);
 
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                set_irq_flags(irq, IRQF_VALID);
 
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                irq++;
 
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        }
 
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        ret = request_irq(gpmc_irq,
 
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                        gpmc_handle_irq, IRQF_SHARED, "gpmc", gpmc_base);
 
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        if (ret)
 
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                pr_err("gpmc: irq-%d could not claim: err %d\n",
 
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                                                gpmc_irq, ret);
 
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        return ret;
 
758
}
 
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postcore_initcall(gpmc_init);
 
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static irqreturn_t gpmc_handle_irq(int irq, void *dev)
 
762
{
 
763
        u8 cs;
 
764
 
 
765
        /* check cs to invoke the irq */
 
766
        cs = ((gpmc_read_reg(GPMC_PREFETCH_CONFIG1)) >> CS_NUM_SHIFT) & 0x7;
 
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        if (OMAP_GPMC_IRQ_BASE+cs <= OMAP_GPMC_IRQ_END)
 
768
                generic_handle_irq(OMAP_GPMC_IRQ_BASE+cs);
 
769
 
 
770
        return IRQ_HANDLED;
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}
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#ifdef CONFIG_ARCH_OMAP3