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Viewing changes to drivers/video/omap2/dss/hdmi.h

  • Committer: Bazaar Package Importer
  • Author(s): John Rigby, Upstream Fixes, Andy Green, John Rigby
  • Date: 2011-04-14 12:16:06 UTC
  • Revision ID: james.westby@ubuntu.com-20110414121606-b77podkyqgr2oix7
Tags: 2.6.38-1002.3
https://launchpad.net/bugs/745737
https://launchpad.net/bugs/747639
https://launchpad.net/bugs/752900
https://launchpad.net/bugs/745737
https://launchpad.net/bugs/732842
https://launchpad.net/bugs/732912
[ Upstream Fixes ]

* MUSB: shutdown: Make sure block is awake before doing shutdown
  - LP: #745737
* Fixed gpio polarity of gpio USB-phy reset.
  - LP: #747639

[ Andy Green ]

* LINARO: SAUCE: disable CONFIG_OMAP_RESET_CLOCKS
  - LP: #752900

[ John Rigby ]

* Rebase to new upstreams:
  Linux v2.6.38.1
  linaro-linux-2.6.38-upstream-29Mar2011
  Ubuntu-2.6.38-7.35
* SAUCE: OMAP4: clock: wait for module to become accessible on
  a clk enable
  - LP: #745737
* Rebase to new upstreams:
  Linux v2.6.38.2
  linaro-linux-2.6.38-upstream-5Apr2011
  Ubuntu-2.6.38-8.41
  - LP: #732842
* Update configs for device tree, dvfs and lttng
* LINARO: add building of dtb's
* LINARO: SAUCE: Disable lowest operating freqs on omap34xx
  - LP: #732912

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Lines of Context:
drivers/video/omap2/dss/hdmi.h
 
1
/*
 
2
 * hdmi.h
 
3
 *
 
4
 * HDMI driver definition for TI OMAP4 processors.
 
5
 *
 
6
 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
 
7
 *
 
8
 * This program is free software; you can redistribute it and/or modify it
 
9
 * under the terms of the GNU General Public License version 2 as published by
 
10
 * the Free Software Foundation.
 
11
 *
 
12
 * This program is distributed in the hope that it will be useful, but WITHOUT
 
13
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 
14
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 
15
 * more details.
 
16
 *
 
17
 * You should have received a copy of the GNU General Public License along with
 
18
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 
19
 */
 
20
 
 
21
#ifndef _OMAP4_DSS_HDMI_H_
 
22
#define _OMAP4_DSS_HDMI_H_
 
23
 
 
24
#include <linux/string.h>
 
25
#include <plat/display.h>
 
26
 
 
27
#define HDMI_WP         0x0
 
28
#define HDMI_CORE_SYS           0x400
 
29
#define HDMI_CORE_AV            0x900
 
30
#define HDMI_PLLCTRL            0x200
 
31
#define HDMI_PHY                0x300
 
32
 
 
33
struct hdmi_reg { u16 idx; };
 
34
 
 
35
#define HDMI_REG(idx)                   ((const struct hdmi_reg) { idx })
 
36
 
 
37
/* HDMI Wrapper */
 
38
#define HDMI_WP_REG(idx)                        HDMI_REG(HDMI_WP + idx)
 
39
 
 
40
#define HDMI_WP_REVISION                        HDMI_WP_REG(0x0)
 
41
#define HDMI_WP_SYSCONFIG                       HDMI_WP_REG(0x10)
 
42
#define HDMI_WP_IRQSTATUS_RAW                   HDMI_WP_REG(0x24)
 
43
#define HDMI_WP_IRQSTATUS                       HDMI_WP_REG(0x28)
 
44
#define HDMI_WP_PWR_CTRL                        HDMI_WP_REG(0x40)
 
45
#define HDMI_WP_IRQENABLE_SET                   HDMI_WP_REG(0x2C)
 
46
#define HDMI_WP_VIDEO_CFG                       HDMI_WP_REG(0x50)
 
47
#define HDMI_WP_VIDEO_SIZE                      HDMI_WP_REG(0x60)
 
48
#define HDMI_WP_VIDEO_TIMING_H                  HDMI_WP_REG(0x68)
 
49
#define HDMI_WP_VIDEO_TIMING_V                  HDMI_WP_REG(0x6C)
 
50
#define HDMI_WP_WP_CLK                          HDMI_WP_REG(0x70)
 
51
 
 
52
/* HDMI IP Core System */
 
53
#define HDMI_CORE_SYS_REG(idx)                  HDMI_REG(HDMI_CORE_SYS + idx)
 
54
 
 
55
#define HDMI_CORE_SYS_VND_IDL                   HDMI_CORE_SYS_REG(0x0)
 
56
#define HDMI_CORE_SYS_DEV_IDL                   HDMI_CORE_SYS_REG(0x8)
 
57
#define HDMI_CORE_SYS_DEV_IDH                   HDMI_CORE_SYS_REG(0xC)
 
58
#define HDMI_CORE_SYS_DEV_REV                   HDMI_CORE_SYS_REG(0x10)
 
59
#define HDMI_CORE_SYS_SRST                      HDMI_CORE_SYS_REG(0x14)
 
60
#define HDMI_CORE_CTRL1                 HDMI_CORE_SYS_REG(0x20)
 
61
#define HDMI_CORE_SYS_SYS_STAT                  HDMI_CORE_SYS_REG(0x24)
 
62
#define HDMI_CORE_SYS_VID_ACEN                  HDMI_CORE_SYS_REG(0x124)
 
63
#define HDMI_CORE_SYS_VID_MODE                  HDMI_CORE_SYS_REG(0x128)
 
64
#define HDMI_CORE_SYS_INTR_STATE                HDMI_CORE_SYS_REG(0x1C0)
 
65
#define HDMI_CORE_SYS_INTR1                     HDMI_CORE_SYS_REG(0x1C4)
 
66
#define HDMI_CORE_SYS_INTR2                     HDMI_CORE_SYS_REG(0x1C8)
 
67
#define HDMI_CORE_SYS_INTR3                     HDMI_CORE_SYS_REG(0x1CC)
 
68
#define HDMI_CORE_SYS_INTR4                     HDMI_CORE_SYS_REG(0x1D0)
 
69
#define HDMI_CORE_SYS_UMASK1                    HDMI_CORE_SYS_REG(0x1D4)
 
70
#define HDMI_CORE_SYS_TMDS_CTRL         HDMI_CORE_SYS_REG(0x208)
 
71
#define HDMI_CORE_SYS_DE_DLY                    HDMI_CORE_SYS_REG(0xC8)
 
72
#define HDMI_CORE_SYS_DE_CTRL                   HDMI_CORE_SYS_REG(0xCC)
 
73
#define HDMI_CORE_SYS_DE_TOP                    HDMI_CORE_SYS_REG(0xD0)
 
74
#define HDMI_CORE_SYS_DE_CNTL                   HDMI_CORE_SYS_REG(0xD8)
 
75
#define HDMI_CORE_SYS_DE_CNTH                   HDMI_CORE_SYS_REG(0xDC)
 
76
#define HDMI_CORE_SYS_DE_LINL                   HDMI_CORE_SYS_REG(0xE0)
 
77
#define HDMI_CORE_SYS_DE_LINH_1         HDMI_CORE_SYS_REG(0xE4)
 
78
#define HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC 0x1
 
79
#define HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC 0x1
 
80
#define HDMI_CORE_CTRL1_BSEL_24BITBUS           0x1
 
81
#define HDMI_CORE_CTRL1_EDGE_RISINGEDGE 0x1
 
82
 
 
83
/* HDMI DDC E-DID */
 
84
#define HDMI_CORE_DDC_CMD                       HDMI_CORE_SYS_REG(0x3CC)
 
85
#define HDMI_CORE_DDC_STATUS                    HDMI_CORE_SYS_REG(0x3C8)
 
86
#define HDMI_CORE_DDC_ADDR                      HDMI_CORE_SYS_REG(0x3B4)
 
87
#define HDMI_CORE_DDC_OFFSET                    HDMI_CORE_SYS_REG(0x3BC)
 
88
#define HDMI_CORE_DDC_COUNT1                    HDMI_CORE_SYS_REG(0x3C0)
 
89
#define HDMI_CORE_DDC_COUNT2                    HDMI_CORE_SYS_REG(0x3C4)
 
90
#define HDMI_CORE_DDC_DATA                      HDMI_CORE_SYS_REG(0x3D0)
 
91
#define HDMI_CORE_DDC_SEGM                      HDMI_CORE_SYS_REG(0x3B8)
 
92
 
 
93
/* HDMI IP Core Audio Video */
 
94
#define HDMI_CORE_AV_REG(idx)                   HDMI_REG(HDMI_CORE_AV + idx)
 
95
 
 
96
#define HDMI_CORE_AV_HDMI_CTRL                  HDMI_CORE_AV_REG(0xBC)
 
97
#define HDMI_CORE_AV_DPD                        HDMI_CORE_AV_REG(0xF4)
 
98
#define HDMI_CORE_AV_PB_CTRL1                   HDMI_CORE_AV_REG(0xF8)
 
99
#define HDMI_CORE_AV_PB_CTRL2                   HDMI_CORE_AV_REG(0xFC)
 
100
#define HDMI_CORE_AV_AVI_TYPE                   HDMI_CORE_AV_REG(0x100)
 
101
#define HDMI_CORE_AV_AVI_VERS                   HDMI_CORE_AV_REG(0x104)
 
102
#define HDMI_CORE_AV_AVI_LEN                    HDMI_CORE_AV_REG(0x108)
 
103
#define HDMI_CORE_AV_AVI_CHSUM                  HDMI_CORE_AV_REG(0x10C)
 
104
#define HDMI_CORE_AV_AVI_DBYTE(n)               HDMI_CORE_AV_REG(n * 4 + 0x110)
 
105
#define HDMI_CORE_AV_AVI_DBYTE_NELEMS           HDMI_CORE_AV_REG(15)
 
106
#define HDMI_CORE_AV_SPD_DBYTE                  HDMI_CORE_AV_REG(0x190)
 
107
#define HDMI_CORE_AV_SPD_DBYTE_NELEMS           HDMI_CORE_AV_REG(27)
 
108
#define HDMI_CORE_AV_MPEG_DBYTE         HDMI_CORE_AV_REG(0x290)
 
109
#define HDMI_CORE_AV_MPEG_DBYTE_NELEMS          HDMI_CORE_AV_REG(27)
 
110
#define HDMI_CORE_AV_GEN_DBYTE                  HDMI_CORE_AV_REG(0x300)
 
111
#define HDMI_CORE_AV_GEN_DBYTE_NELEMS           HDMI_CORE_AV_REG(31)
 
112
#define HDMI_CORE_AV_GEN2_DBYTE         HDMI_CORE_AV_REG(0x380)
 
113
#define HDMI_CORE_AV_GEN2_DBYTE_NELEMS          HDMI_CORE_AV_REG(31)
 
114
#define HDMI_CORE_AV_ACR_CTRL                   HDMI_CORE_AV_REG(0x4)
 
115
#define HDMI_CORE_AV_FREQ_SVAL                  HDMI_CORE_AV_REG(0x8)
 
116
#define HDMI_CORE_AV_N_SVAL1                    HDMI_CORE_AV_REG(0xC)
 
117
#define HDMI_CORE_AV_N_SVAL2                    HDMI_CORE_AV_REG(0x10)
 
118
#define HDMI_CORE_AV_N_SVAL3                    HDMI_CORE_AV_REG(0x14)
 
119
#define HDMI_CORE_AV_CTS_SVAL1                  HDMI_CORE_AV_REG(0x18)
 
120
#define HDMI_CORE_AV_CTS_SVAL2                  HDMI_CORE_AV_REG(0x1C)
 
121
#define HDMI_CORE_AV_CTS_SVAL3                  HDMI_CORE_AV_REG(0x20)
 
122
#define HDMI_CORE_AV_CTS_HVAL1                  HDMI_CORE_AV_REG(0x24)
 
123
#define HDMI_CORE_AV_CTS_HVAL2                  HDMI_CORE_AV_REG(0x28)
 
124
#define HDMI_CORE_AV_CTS_HVAL3                  HDMI_CORE_AV_REG(0x2C)
 
125
#define HDMI_CORE_AV_AUD_MODE                   HDMI_CORE_AV_REG(0x50)
 
126
#define HDMI_CORE_AV_SPDIF_CTRL         HDMI_CORE_AV_REG(0x54)
 
127
#define HDMI_CORE_AV_HW_SPDIF_FS                HDMI_CORE_AV_REG(0x60)
 
128
#define HDMI_CORE_AV_SWAP_I2S                   HDMI_CORE_AV_REG(0x64)
 
129
#define HDMI_CORE_AV_SPDIF_ERTH         HDMI_CORE_AV_REG(0x6C)
 
130
#define HDMI_CORE_AV_I2S_IN_MAP         HDMI_CORE_AV_REG(0x70)
 
131
#define HDMI_CORE_AV_I2S_IN_CTRL                HDMI_CORE_AV_REG(0x74)
 
132
#define HDMI_CORE_AV_I2S_CHST0                  HDMI_CORE_AV_REG(0x78)
 
133
#define HDMI_CORE_AV_I2S_CHST1                  HDMI_CORE_AV_REG(0x7C)
 
134
#define HDMI_CORE_AV_I2S_CHST2                  HDMI_CORE_AV_REG(0x80)
 
135
#define HDMI_CORE_AV_I2S_CHST4                  HDMI_CORE_AV_REG(0x84)
 
136
#define HDMI_CORE_AV_I2S_CHST5                  HDMI_CORE_AV_REG(0x88)
 
137
#define HDMI_CORE_AV_ASRC                       HDMI_CORE_AV_REG(0x8C)
 
138
#define HDMI_CORE_AV_I2S_IN_LEN         HDMI_CORE_AV_REG(0x90)
 
139
#define HDMI_CORE_AV_HDMI_CTRL                  HDMI_CORE_AV_REG(0xBC)
 
140
#define HDMI_CORE_AV_AUDO_TXSTAT                HDMI_CORE_AV_REG(0xC0)
 
141
#define HDMI_CORE_AV_AUD_PAR_BUSCLK_1           HDMI_CORE_AV_REG(0xCC)
 
142
#define HDMI_CORE_AV_AUD_PAR_BUSCLK_2           HDMI_CORE_AV_REG(0xD0)
 
143
#define HDMI_CORE_AV_AUD_PAR_BUSCLK_3           HDMI_CORE_AV_REG(0xD4)
 
144
#define HDMI_CORE_AV_TEST_TXCTRL                HDMI_CORE_AV_REG(0xF0)
 
145
#define HDMI_CORE_AV_DPD                        HDMI_CORE_AV_REG(0xF4)
 
146
#define HDMI_CORE_AV_PB_CTRL1                   HDMI_CORE_AV_REG(0xF8)
 
147
#define HDMI_CORE_AV_PB_CTRL2                   HDMI_CORE_AV_REG(0xFC)
 
148
#define HDMI_CORE_AV_AVI_TYPE                   HDMI_CORE_AV_REG(0x100)
 
149
#define HDMI_CORE_AV_AVI_VERS                   HDMI_CORE_AV_REG(0x104)
 
150
#define HDMI_CORE_AV_AVI_LEN                    HDMI_CORE_AV_REG(0x108)
 
151
#define HDMI_CORE_AV_AVI_CHSUM                  HDMI_CORE_AV_REG(0x10C)
 
152
#define HDMI_CORE_AV_SPD_TYPE                   HDMI_CORE_AV_REG(0x180)
 
153
#define HDMI_CORE_AV_SPD_VERS                   HDMI_CORE_AV_REG(0x184)
 
154
#define HDMI_CORE_AV_SPD_LEN                    HDMI_CORE_AV_REG(0x188)
 
155
#define HDMI_CORE_AV_SPD_CHSUM                  HDMI_CORE_AV_REG(0x18C)
 
156
#define HDMI_CORE_AV_MPEG_TYPE                  HDMI_CORE_AV_REG(0x280)
 
157
#define HDMI_CORE_AV_MPEG_VERS                  HDMI_CORE_AV_REG(0x284)
 
158
#define HDMI_CORE_AV_MPEG_LEN                   HDMI_CORE_AV_REG(0x288)
 
159
#define HDMI_CORE_AV_MPEG_CHSUM         HDMI_CORE_AV_REG(0x28C)
 
160
#define HDMI_CORE_AV_CP_BYTE1                   HDMI_CORE_AV_REG(0x37C)
 
161
#define HDMI_CORE_AV_CEC_ADDR_ID                HDMI_CORE_AV_REG(0x3FC)
 
162
#define HDMI_CORE_AV_SPD_DBYTE_ELSIZE           0x4
 
163
#define HDMI_CORE_AV_GEN2_DBYTE_ELSIZE          0x4
 
164
#define HDMI_CORE_AV_MPEG_DBYTE_ELSIZE          0x4
 
165
#define HDMI_CORE_AV_GEN_DBYTE_ELSIZE           0x4
 
166
 
 
167
/* PLL */
 
168
#define HDMI_PLL_REG(idx)                       HDMI_REG(HDMI_PLLCTRL + idx)
 
169
 
 
170
#define PLLCTRL_PLL_CONTROL                     HDMI_PLL_REG(0x0)
 
171
#define PLLCTRL_PLL_STATUS                      HDMI_PLL_REG(0x4)
 
172
#define PLLCTRL_PLL_GO                          HDMI_PLL_REG(0x8)
 
173
#define PLLCTRL_CFG1                            HDMI_PLL_REG(0xC)
 
174
#define PLLCTRL_CFG2                            HDMI_PLL_REG(0x10)
 
175
#define PLLCTRL_CFG3                            HDMI_PLL_REG(0x14)
 
176
#define PLLCTRL_CFG4                            HDMI_PLL_REG(0x20)
 
177
 
 
178
/* HDMI PHY */
 
179
#define HDMI_PHY_REG(idx)                       HDMI_REG(HDMI_PHY + idx)
 
180
 
 
181
#define HDMI_TXPHY_TX_CTRL                      HDMI_PHY_REG(0x0)
 
182
#define HDMI_TXPHY_DIGITAL_CTRL         HDMI_PHY_REG(0x4)
 
183
#define HDMI_TXPHY_POWER_CTRL                   HDMI_PHY_REG(0x8)
 
184
#define HDMI_TXPHY_PAD_CFG_CTRL         HDMI_PHY_REG(0xC)
 
185
 
 
186
/* HDMI EDID Length  */
 
187
#define HDMI_EDID_MAX_LENGTH                    256
 
188
#define EDID_TIMING_DESCRIPTOR_SIZE             0x12
 
189
#define EDID_DESCRIPTOR_BLOCK0_ADDRESS          0x36
 
190
#define EDID_DESCRIPTOR_BLOCK1_ADDRESS          0x80
 
191
#define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR      4
 
192
#define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR      4
 
193
 
 
194
#define OMAP_HDMI_TIMINGS_NB                    34
 
195
 
 
196
#define REG_FLD_MOD(idx, val, start, end) \
 
197
        hdmi_write_reg(idx, FLD_MOD(hdmi_read_reg(idx), val, start, end))
 
198
#define REG_GET(idx, start, end) \
 
199
        FLD_GET(hdmi_read_reg(idx), start, end)
 
200
 
 
201
/* HDMI timing structure */
 
202
struct hdmi_timings {
 
203
        struct omap_video_timings timings;
 
204
        int vsync_pol;
 
205
        int hsync_pol;
 
206
};
 
207
 
 
208
enum hdmi_phy_pwr {
 
209
        HDMI_PHYPWRCMD_OFF = 0,
 
210
        HDMI_PHYPWRCMD_LDOON = 1,
 
211
        HDMI_PHYPWRCMD_TXON = 2
 
212
};
 
213
 
 
214
enum hdmi_pll_pwr {
 
215
        HDMI_PLLPWRCMD_ALLOFF = 0,
 
216
        HDMI_PLLPWRCMD_PLLONLY = 1,
 
217
        HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2,
 
218
        HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3
 
219
};
 
220
 
 
221
enum hdmi_clk_refsel {
 
222
        HDMI_REFSEL_PCLK = 0,
 
223
        HDMI_REFSEL_REF1 = 1,
 
224
        HDMI_REFSEL_REF2 = 2,
 
225
        HDMI_REFSEL_SYSCLK = 3
 
226
};
 
227
 
 
228
enum hdmi_core_inputbus_width {
 
229
        HDMI_INPUT_8BIT = 0,
 
230
        HDMI_INPUT_10BIT = 1,
 
231
        HDMI_INPUT_12BIT = 2
 
232
};
 
233
 
 
234
enum hdmi_core_dither_trunc {
 
235
        HDMI_OUTPUTTRUNCATION_8BIT = 0,
 
236
        HDMI_OUTPUTTRUNCATION_10BIT = 1,
 
237
        HDMI_OUTPUTTRUNCATION_12BIT = 2,
 
238
        HDMI_OUTPUTDITHER_8BIT = 3,
 
239
        HDMI_OUTPUTDITHER_10BIT = 4,
 
240
        HDMI_OUTPUTDITHER_12BIT = 5
 
241
};
 
242
 
 
243
enum hdmi_core_deepcolor_ed {
 
244
        HDMI_DEEPCOLORPACKECTDISABLE = 0,
 
245
        HDMI_DEEPCOLORPACKECTENABLE = 1
 
246
};
 
247
 
 
248
enum hdmi_core_packet_mode {
 
249
        HDMI_PACKETMODERESERVEDVALUE = 0,
 
250
        HDMI_PACKETMODE24BITPERPIXEL = 4,
 
251
        HDMI_PACKETMODE30BITPERPIXEL = 5,
 
252
        HDMI_PACKETMODE36BITPERPIXEL = 6,
 
253
        HDMI_PACKETMODE48BITPERPIXEL = 7
 
254
};
 
255
 
 
256
enum hdmi_core_hdmi_dvi {
 
257
        HDMI_DVI = 0,
 
258
        HDMI_HDMI = 1
 
259
};
 
260
 
 
261
enum hdmi_core_tclkselclkmult {
 
262
        HDMI_FPLL05IDCK = 0,
 
263
        HDMI_FPLL10IDCK = 1,
 
264
        HDMI_FPLL20IDCK = 2,
 
265
        HDMI_FPLL40IDCK = 3
 
266
};
 
267
 
 
268
enum hdmi_core_packet_ctrl {
 
269
        HDMI_PACKETENABLE = 1,
 
270
        HDMI_PACKETDISABLE = 0,
 
271
        HDMI_PACKETREPEATON = 1,
 
272
        HDMI_PACKETREPEATOFF = 0
 
273
};
 
274
 
 
275
/* INFOFRAME_AVI_ definitions */
 
276
enum hdmi_core_infoframe {
 
277
        HDMI_INFOFRAME_AVI_DB1Y_RGB = 0,
 
278
        HDMI_INFOFRAME_AVI_DB1Y_YUV422 = 1,
 
279
        HDMI_INFOFRAME_AVI_DB1Y_YUV444 = 2,
 
280
        HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF = 0,
 
281
        HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_ON =  1,
 
282
        HDMI_INFOFRAME_AVI_DB1B_NO = 0,
 
283
        HDMI_INFOFRAME_AVI_DB1B_VERT = 1,
 
284
        HDMI_INFOFRAME_AVI_DB1B_HORI = 2,
 
285
        HDMI_INFOFRAME_AVI_DB1B_VERTHORI = 3,
 
286
        HDMI_INFOFRAME_AVI_DB1S_0 = 0,
 
287
        HDMI_INFOFRAME_AVI_DB1S_1 = 1,
 
288
        HDMI_INFOFRAME_AVI_DB1S_2 = 2,
 
289
        HDMI_INFOFRAME_AVI_DB2C_NO = 0,
 
290
        HDMI_INFOFRAME_AVI_DB2C_ITU601 = 1,
 
291
        HDMI_INFOFRAME_AVI_DB2C_ITU709 = 2,
 
292
        HDMI_INFOFRAME_AVI_DB2C_EC_EXTENDED = 3,
 
293
        HDMI_INFOFRAME_AVI_DB2M_NO = 0,
 
294
        HDMI_INFOFRAME_AVI_DB2M_43 = 1,
 
295
        HDMI_INFOFRAME_AVI_DB2M_169 = 2,
 
296
        HDMI_INFOFRAME_AVI_DB2R_SAME = 8,
 
297
        HDMI_INFOFRAME_AVI_DB2R_43 = 9,
 
298
        HDMI_INFOFRAME_AVI_DB2R_169 = 10,
 
299
        HDMI_INFOFRAME_AVI_DB2R_149 = 11,
 
300
        HDMI_INFOFRAME_AVI_DB3ITC_NO = 0,
 
301
        HDMI_INFOFRAME_AVI_DB3ITC_YES = 1,
 
302
        HDMI_INFOFRAME_AVI_DB3EC_XVYUV601 = 0,
 
303
        HDMI_INFOFRAME_AVI_DB3EC_XVYUV709 = 1,
 
304
        HDMI_INFOFRAME_AVI_DB3Q_DEFAULT = 0,
 
305
        HDMI_INFOFRAME_AVI_DB3Q_LR = 1,
 
306
        HDMI_INFOFRAME_AVI_DB3Q_FR = 2,
 
307
        HDMI_INFOFRAME_AVI_DB3SC_NO = 0,
 
308
        HDMI_INFOFRAME_AVI_DB3SC_HORI = 1,
 
309
        HDMI_INFOFRAME_AVI_DB3SC_VERT = 2,
 
310
        HDMI_INFOFRAME_AVI_DB3SC_HORIVERT = 3,
 
311
        HDMI_INFOFRAME_AVI_DB5PR_NO = 0,
 
312
        HDMI_INFOFRAME_AVI_DB5PR_2 = 1,
 
313
        HDMI_INFOFRAME_AVI_DB5PR_3 = 2,
 
314
        HDMI_INFOFRAME_AVI_DB5PR_4 = 3,
 
315
        HDMI_INFOFRAME_AVI_DB5PR_5 = 4,
 
316
        HDMI_INFOFRAME_AVI_DB5PR_6 = 5,
 
317
        HDMI_INFOFRAME_AVI_DB5PR_7 = 6,
 
318
        HDMI_INFOFRAME_AVI_DB5PR_8 = 7,
 
319
        HDMI_INFOFRAME_AVI_DB5PR_9 = 8,
 
320
        HDMI_INFOFRAME_AVI_DB5PR_10 = 9
 
321
};
 
322
 
 
323
enum hdmi_packing_mode {
 
324
        HDMI_PACK_10b_RGB_YUV444 = 0,
 
325
        HDMI_PACK_24b_RGB_YUV444_YUV422 = 1,
 
326
        HDMI_PACK_20b_YUV422 = 2,
 
327
        HDMI_PACK_ALREADYPACKED = 7
 
328
};
 
329
 
 
330
struct hdmi_core_video_config {
 
331
        enum hdmi_core_inputbus_width   ip_bus_width;
 
332
        enum hdmi_core_dither_trunc     op_dither_truc;
 
333
        enum hdmi_core_deepcolor_ed     deep_color_pkt;
 
334
        enum hdmi_core_packet_mode      pkt_mode;
 
335
        enum hdmi_core_hdmi_dvi         hdmi_dvi;
 
336
        enum hdmi_core_tclkselclkmult   tclk_sel_clkmult;
 
337
};
 
338
 
 
339
/*
 
340
 * Refer to section 8.2 in HDMI 1.3 specification for
 
341
 * details about infoframe databytes
 
342
 */
 
343
struct hdmi_core_infoframe_avi {
 
344
        u8      db1_format;
 
345
                /* Y0, Y1 rgb,yCbCr */
 
346
        u8      db1_active_info;
 
347
                /* A0  Active information Present */
 
348
        u8      db1_bar_info_dv;
 
349
                /* B0, B1 Bar info data valid */
 
350
        u8      db1_scan_info;
 
351
                /* S0, S1 scan information */
 
352
        u8      db2_colorimetry;
 
353
                /* C0, C1 colorimetry */
 
354
        u8      db2_aspect_ratio;
 
355
                /* M0, M1 Aspect ratio (4:3, 16:9) */
 
356
        u8      db2_active_fmt_ar;
 
357
                /* R0...R3 Active format aspect ratio */
 
358
        u8      db3_itc;
 
359
                /* ITC IT content. */
 
360
        u8      db3_ec;
 
361
                /* EC0, EC1, EC2 Extended colorimetry */
 
362
        u8      db3_q_range;
 
363
                /* Q1, Q0 Quantization range */
 
364
        u8      db3_nup_scaling;
 
365
                /* SC1, SC0 Non-uniform picture scaling */
 
366
        u8      db4_videocode;
 
367
                /* VIC0..6 Video format identification */
 
368
        u8      db5_pixel_repeat;
 
369
                /* PR0..PR3 Pixel repetition factor */
 
370
        u16     db6_7_line_eoftop;
 
371
                /* Line number end of top bar */
 
372
        u16     db8_9_line_sofbottom;
 
373
                /* Line number start of bottom bar */
 
374
        u16     db10_11_pixel_eofleft;
 
375
                /* Pixel number end of left bar */
 
376
        u16     db12_13_pixel_sofright;
 
377
                /* Pixel number start of right bar */
 
378
};
 
379
 
 
380
struct hdmi_core_packet_enable_repeat {
 
381
        u32     audio_pkt;
 
382
        u32     audio_pkt_repeat;
 
383
        u32     avi_infoframe;
 
384
        u32     avi_infoframe_repeat;
 
385
        u32     gen_cntrl_pkt;
 
386
        u32     gen_cntrl_pkt_repeat;
 
387
        u32     generic_pkt;
 
388
        u32     generic_pkt_repeat;
 
389
};
 
390
 
 
391
struct hdmi_video_format {
 
392
        enum hdmi_packing_mode  packing_mode;
 
393
        u32                     y_res;  /* Line per panel */
 
394
        u32                     x_res;  /* pixel per line */
 
395
};
 
396
 
 
397
struct hdmi_video_interface {
 
398
        int     vsp;    /* Vsync polarity */
 
399
        int     hsp;    /* Hsync polarity */
 
400
        int     interlacing;
 
401
        int     tm;     /* Timing mode */
 
402
};
 
403
 
 
404
struct hdmi_cm {
 
405
        int     code;
 
406
        int     mode;
 
407
};
 
408
 
 
409
struct hdmi_config {
 
410
        struct hdmi_timings timings;
 
411
        u16     interlace;
 
412
        struct hdmi_cm cm;
 
413
};
 
414
 
 
415
#endif