2
* OMAP2/3 Display Subsystem.
4
* Copyright (C) 2008,2009 Nokia Corporation
5
* Original OMAP2 support written by Andrzej Zaborowski <andrew@openedhand.com>
6
* Enhancements and OMAP3 support written by Juha Riihimäki
8
* This program is free software; you can redistribute it and/or
9
* modify it under the terms of the GNU General Public License as
10
* published by the Free Software Foundation; either version 2 or
11
* (at your option) any later version of the License.
13
* This program is distributed in the hope that it will be useful,
14
* but WITHOUT ANY WARRANTY; without even the implied warranty of
15
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16
* GNU General Public License for more details.
18
* You should have received a copy of the GNU General Public License along
19
* with this program; if not, see <http://www.gnu.org/licenses/>.
23
#include "ui/console.h"
26
//#define OMAP_DSS_DEBUG
27
#define OMAP_DSS_DEBUG_DISPC
28
#define OMAP_DSS_DEBUG_DISS
29
#define OMAP_DSS_DEBUG_DSI
30
#define OMAP_DSS_DEBUG_RFBI
31
//#define OMAP_DSS_DEBUG_VENC
34
#define TRACE(fmt,...) fprintf(stderr, "%s@%d: " fmt "\n", __FUNCTION__, \
35
__LINE__, ##__VA_ARGS__)
36
#define LAYERNAME(n) ((!(n)) ? "GFX" : ((n)==1) ? "VID1" : "VID2")
37
#ifdef OMAP_DSS_DEBUG_DISPC
38
#define TRACEDISPC(fmt,...) TRACE(fmt, ##__VA_ARGS__)
40
#define TRACEDISPC(...)
42
#ifdef OMAP_DSS_DEBUG_DISS
43
#define TRACEDISS(fmt,...) TRACE(fmt, ##__VA_ARGS__)
45
#define TRACEDISS(...)
47
#ifdef OMAP_DSS_DEBUG_DSI
48
#define TRACEDSI(fmt,...) TRACE(fmt, ##__VA_ARGS__)
52
#ifdef OMAP_DSS_DEBUG_RFBI
53
#define TRACERFBI(fmt,...) TRACE(fmt, ##__VA_ARGS__)
55
#define TRACERFBI(...)
57
#ifdef OMAP_DSS_DEBUG_VENC
58
#define TRACEVENC(fmt,...) TRACE(fmt, ##__VA_ARGS__)
60
#define TRACEVENC(...)
64
#define TRACEDISPC(...)
65
#define TRACEDISS(...)
67
#define TRACERFBI(...)
68
#define TRACEVENC(...)
73
#define OMAP_RO_REG(...)
74
#define OMAP_RO_REGV(...)
75
#define OMAP_BAD_REG(...)
76
#define OMAP_BAD_REGV(...)
79
#define OMAP_DSI_RX_FIFO_SIZE 32
81
struct omap_dss_plane_s {
93
hwaddr addr[3]; /* BA0, BA1, TABLE_BA */
103
/* following used for planes 1 and 2 only (VID1 and VID2) */
105
uint32_t fir_coef_h[8];
106
uint32_t fir_coef_hv[8];
107
uint32_t fir_coef_v[8];
108
uint32_t conv_coef[5];
109
uint32_t picture_size;
113
struct omap_dss_panel_s {
121
struct omap_dss_plane_s gfx;
122
struct omap_dss_plane_s vid1;
123
struct omap_dss_plane_s vid2;
124
uint32_t *gfx_palette;
125
uint32_t gfx_palette_size;
131
MemoryRegion iomem_diss1, iomem_disc1, iomem_rfbi1, iomem_venc1, iomem_im3;
132
MemoryRegion iomem_dsi;
139
uint32_t sdi_control;
140
uint32_t pll_control;
143
struct omap_dss_panel_s dig, lcd;
146
QEMUTimer *lcdframer;
161
uint32_t global_alpha;
166
struct omap_dss_plane_s plane[3]; /* GFX, VID1, VID2 */
182
const struct rfbi_chip_s *chip[2];
188
/* protocol engine registers */
193
uint32_t complexio_cfg1;
194
uint32_t complexio_cfg2;
195
uint32_t complexio_irqst;
196
uint32_t complexio_irqen;
208
uint32_t stopclk_timing;
209
uint32_t tx_fifo_vc_size;
210
uint32_t rx_fifo_vc_size;
220
uint32_t rx_fifo[OMAP_DSI_RX_FIFO_SIZE];
228
/* pll controller registers */
229
uint32_t pll_control;
231
uint32_t pll_config1;
232
uint32_t pll_config2;
236
#include "ui/pixel_ops.h"
237
#include "framebuffer.h"
239
#include "omap_dss_drawfn.h"
241
#include "omap_dss_drawfn.h"
243
#include "omap_dss_drawfn.h"
245
#include "omap_dss_drawfn.h"
247
#include "omap_dss_drawfn.h"
250
static drawfn omap_dss_linefn(const DeviceState *dev, int format, int bpp)
253
case 8: return omap_dss_drawfn_8[format];
254
case 15: return omap_dss_drawfn_15[format];
255
case 16: return omap_dss_drawfn_16[format];
256
case 24: return omap_dss_drawfn_24[format];
257
case 32: return omap_dss_drawfn_32[format];
259
hw_error("%s: unsupported host display color depth: %d\n",
266
/* Bytes(!) per pixel */
267
static const int omap_lcd_Bpp[0x10] = {
268
0, /* 0x0: BITMAP1 (CLUT) */
269
0, /* 0x1: BITMAP2 (CLUT) */
270
0, /* 0x2: BITMAP4 (CLUT) */
271
1, /* 0x3: BITMAP8 (CLUT) */
272
2, /* 0x4: RGB12 (unpacked 16-bit container)*/
275
0, /* 0x7: reserved */
276
4, /* 0x8: RGB24 (unpacked in 32-bit container) */
277
3, /* 0x9: RGB24 (packed in 24-bit container) */
278
2, /* 0xa: YUV2 422 */
279
2, /* 0xb: UYVY 422 */
282
4, /* 0xe: RGBx32 (24-bit RGB aligned on MSB of the 32-bit container) */
283
0, /* 0xf: reserved */
286
static void omap_dss_interrupt_update(struct omap_dss_s *s)
289
(s->dsi.irqst & s->dsi.irqen)
290
| (s->dsi.complexio_irqst & s->dsi.complexio_irqen)
291
| (s->dsi.vc[0].irqst & s->dsi.vc[0].irqen)
292
| (s->dsi.vc[1].irqst & s->dsi.vc[1].irqen)
293
| (s->dsi.vc[2].irqst & s->dsi.vc[2].irqen)
294
| (s->dsi.vc[3].irqst & s->dsi.vc[3].irqen)
295
| (s->dispc.irqst & s->dispc.irqen));
298
static void omap_dss_framedone(void *opaque)
300
struct omap_dss_s *s = (struct omap_dss_s *)opaque;
301
if (s->dispc.control & 3) { /* DIGITALENABLE | LCDENABLE */
302
if ((s->dispc.control & (1 << 11))) { /* STALLMODE */
303
s->dispc.control &= ~1; /* LCDENABLE */
304
if ((s->rfbi.control & 1)) { /* ENABLE */
308
if (s->dispc.lcdframer) {
309
qemu_del_timer(s->dispc.lcdframer);
312
if (s->dispc.lcdframer) {
313
qemu_mod_timer(s->dispc.lcdframer,
314
qemu_get_clock_ns(vm_clock)
315
+ get_ticks_per_sec() / 10);
318
s->dispc.irqst |= 1 | 2; /* FRAMEDONE | VSYNC */
319
omap_dss_interrupt_update(s);
323
static void omap_dsi_te_trigger(DeviceState *dev, int vc)
325
struct omap_dss_s *s = FROM_SYSBUS(struct omap_dss_s,
326
SYS_BUS_DEVICE(dev));
327
if ((s->dsi.ctrl & 1) && /* IF_EN */
328
(s->dsi.vc[vc].ctrl & 1)) { /* VC_EN */
329
s->dsi.irqst |= 1 << 16; /* TE_TRIGGER_IRQ */
330
omap_dss_interrupt_update(s);
334
static void omap_rfbi_transfer_stop(struct omap_dss_s *s)
339
/* TODO: in non-Bypass mode we probably need to just deassert the DRQ. */
342
s->rfbi.control &= ~0x10; /* ITE */
345
static void omap_rfbi_transfer_start(struct omap_dss_s *s)
351
static void *bounce_buffer;
352
static hwaddr bounce_len;
354
if (!s->rfbi.enable || s->rfbi.busy)
357
if (s->rfbi.control & (1 << 1)) { /* BYPASS */
358
/* TODO: in non-Bypass mode we probably need to just assert the
359
* DRQ and wait for DMA to write the pixels. */
360
hw_error("%s: Bypass mode unimplemented", __FUNCTION__);
363
if (!(s->dispc.control & (1 << 11))) /* STALLMODE */
368
len = s->rfbi.pixels * 2;
370
data_addr = s->dispc.plane[0].addr[0];
371
data = cpu_physical_memory_map(data_addr, &len, 0);
372
if (data && len != s->rfbi.pixels * 2) {
373
cpu_physical_memory_unmap(data, len, 0, 0);
375
len = s->rfbi.pixels * 2;
378
if (len > bounce_len) {
379
bounce_buffer = g_realloc(bounce_buffer, len);
381
data = bounce_buffer;
382
cpu_physical_memory_read(data_addr, data, len);
385
/* TODO: negative values */
386
pitch = s->dispc.plane[0].nx + (s->dispc.plane[0].rowinc - 1) / 2;
388
if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0])
389
s->rfbi.chip[0]->block(s->rfbi.chip[0]->opaque, 1, data, len, pitch);
390
if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1])
391
s->rfbi.chip[1]->block(s->rfbi.chip[1]->opaque, 1, data, len, pitch);
393
if (data != bounce_buffer) {
394
cpu_physical_memory_unmap(data, len, 0, len);
397
omap_rfbi_transfer_stop(s);
399
omap_dss_framedone(s);
402
static void omap_dsi_transfer_start(struct omap_dss_s *s, int ch)
404
if (((s->dispc.control >> 11) & 1) && /* STALLMODE */
405
(s->dsi.ctrl & 1) && /* IF_EN */
406
(s->dsi.vc[ch].ctrl & 1) && /* VC_EN */
407
(s->dsi.vc[ch].te >> 30) & 3) { /* TE_START | TE_EN */
408
TRACEDSI("start TE data transfer on channel %d for %d bytes",
409
ch, s->dsi.vc[ch].te & 0xffffff);
410
TRACEDSI("vc%d irqenable=0x%08x", ch, s->dsi.vc[ch].irqen);
411
TRACEDSI("dsi irqenable=0x%08x", s->dsi.irqen);
412
TRACEDSI("dispc irqenable=0x%08x", s->dispc.irqen);
413
int tx_dma = (s->dsi.vc[ch].ctrl >> 21) & 7; /* DMA_TX_REQ_NB */
415
qemu_irq_raise(s->dsi.drq[tx_dma]);
417
const int format = (s->dispc.plane[0].attr >> 1) & 0xf;
418
const int col_pitch = omap_lcd_Bpp[format] +
419
(s->dispc.plane[0].colinc - 1);
420
const int row_pitch = (s->dispc.plane[0].nx * col_pitch) +
421
(s->dispc.plane[0].rowinc - 1);
422
hwaddr len = row_pitch * s->dispc.plane[0].ny;
423
void *data = cpu_physical_memory_map(s->dispc.plane[0].addr[0],
425
if (!data || len != row_pitch * s->dispc.plane[0].ny) {
426
fprintf(stderr, "%s: unable to map contiguous frame buffer\n",
429
dsi_blt(s->dsi.host, ch, data, s->dispc.plane[0].nx,
430
s->dispc.plane[0].ny, col_pitch, row_pitch, format);
433
cpu_physical_memory_unmap(data, len, 0, 0);
435
s->dsi.vc[ch].te = 0; /* transfer complete */
436
omap_dss_framedone(s);
441
static void omap_dss_panel_layer_update(DisplayState *ds, MemoryRegion *mr,
442
uint32_t panel_width,
443
uint32_t panel_height,
445
int *posy, int *endy,
446
uint32_t width, uint32_t height,
452
if (!(attrib & 1)) { /* layer disabled? */
455
uint32_t format = (attrib >> 1) & 0xf;
456
if ((attrib & 0x600)) { /* GFXENDIANNESS | GFXNIBBLEMODE */
457
hw_error("%s: unsupported layer attributes (0x%08x)\n",
458
__FUNCTION__, attrib);
460
drawfn line_fn = omap_dss_linefn(NULL, format, ds_get_bits_per_pixel(ds));
462
hw_error("%s: unsupported omap dss color format: %d\n",
463
__FUNCTION__, format);
466
fprintf(stderr, "%s@%d: non-zero layer x-coordinate (%d), "
467
"not currently supported -> using zero\n", __FUNCTION__,
472
uint32_t copy_width = (posx + width) > panel_width
473
? (panel_width - posx) : width;
474
uint32_t copy_height = ((*posy) + height) > panel_height
475
? (panel_height - (*posy)) : height;
476
uint32_t linesize = ds_get_linesize(ds);
477
framebuffer_update_display(ds, mr, addr, copy_width, copy_height,
479
? (width >> (3 - format))
480
: (width * omap_lcd_Bpp[format]),
481
linesize, linesize / ds_get_width(ds),
482
full_update, line_fn, palette,
486
static void omap_dss_panel_update_display(struct omap_dss_panel_s *s,
487
MemoryRegion *mr, int lcd)
490
if (s->shadow.width != ds_get_width(s->ds)
491
|| s->shadow.height != ds_get_height(s->ds)) {
492
qemu_console_resize(s->ds, s->shadow.width, s->shadow.height);
494
if ((s->shadow.gfx.attr >> 12) & 0x3) { /* GFXROTATION */
495
hw_error("%s: GFX rotation is not supported", __FUNCTION__);
499
/* TODO: draw background color */
502
if ((lcd && !(s->shadow.gfx.attr & 0x100)) ||
503
(!lcd && (s->shadow.gfx.attr & 0x100))) {
504
if (s->shadow.gfx_palette && s->shadow.gfx_palette_size) {
505
cpu_physical_memory_read(s->shadow.gfx.addr[2],
506
(uint8_t *)s->shadow.gfx_palette,
507
s->shadow.gfx_palette_size
510
first_row = s->shadow.gfx.posy;
511
omap_dss_panel_layer_update(s->ds, mr,
512
s->shadow.width, s->shadow.height,
513
s->shadow.gfx.posx, &first_row, &last_row,
514
s->shadow.gfx.nx, s->shadow.gfx.ny,
515
s->shadow.gfx.attr, s->shadow.gfx.addr[0],
516
s->shadow.gfx_palette, s->invalidate);
518
/* TODO: draw VID1 & VID2 layers */
521
if (first_row >= 0) {
522
dpy_gfx_update(s->ds, 0, first_row, s->shadow.width,
523
last_row - first_row + 1);
527
static void omap_lcd_panel_update_display(void *opaque)
529
struct omap_dss_s *s = opaque;
531
|| !(s->lcd.shadow.control & 1) /* LCDENABLE */
532
|| (s->lcd.shadow.control & (1 << 11))) { /* STALLMODE */
535
omap_dss_panel_update_display(&s->lcd, sysbus_address_space(&s->busdev), 1);
536
omap_dss_framedone(s);
539
static void omap_lcd_panel_invalidate_display(void *opaque)
541
struct omap_dss_s *s = opaque;
542
s->lcd.invalidate = 1;
545
static void omap_dig_panel_update_display(void *opaque)
547
struct omap_dss_s *s = opaque;
548
if (!s->dig.ds || !(s->dig.shadow.control & 2)) { /* DIGITALENABLE */
551
omap_dss_panel_update_display(&s->dig, sysbus_address_space(&s->busdev), 0);
552
omap_dss_framedone(s);
555
static void omap_dig_panel_invalidate_display(void *opaque)
557
struct omap_dss_s *s = opaque;
558
s->dig.invalidate = 1;
561
static void omap_dss_panel_go(struct omap_dss_s *s,
562
struct omap_dss_panel_s *p,
567
p->shadow.control = s->dispc.control;
568
p->shadow.width = (size & 0x7ff) + 1;
569
p->shadow.height = ((size >> 16) & 0x7ff) + 1;
570
p->shadow.gfx = s->dispc.plane[0];
571
p->shadow.vid1 = s->dispc.plane[1];
572
p->shadow.vid2 = s->dispc.plane[2];
574
switch ((p->shadow.gfx.attr >> 1) & 0x0f) {
575
case 0: new_size = 2; break;
576
case 1: new_size = 4; break;
577
case 2: new_size = 16; break;
578
case 3: new_size = 256; break;
581
if (new_size != p->shadow.gfx_palette_size) {
582
if (p->shadow.gfx_palette) {
583
g_free(p->shadow.gfx_palette);
584
p->shadow.gfx_palette = NULL;
587
p->shadow.gfx_palette = g_malloc(new_size * sizeof(uint32_t));
589
p->shadow.gfx_palette_size = new_size;
594
static void omap_dss_panel_reset(void *opaque)
596
struct omap_dss_panel_s *s = opaque;
598
s->shadow.control = 0;
599
memset(&s->shadow.gfx, 0, sizeof(s->shadow.gfx));
600
memset(&s->shadow.vid1, 0, sizeof(s->shadow.vid1));
601
memset(&s->shadow.vid2, 0, sizeof(s->shadow.vid2));
602
if (s->shadow.gfx_palette) {
603
g_free(s->shadow.gfx_palette);
604
s->shadow.gfx_palette = NULL;
605
s->shadow.gfx_palette_size = 0;
610
static void omap_dsi_reset(struct omap_dss_s *s)
614
s->dsi.sysconfig = 0x11;
618
s->dsi.complexio_cfg1 = 0x20000000;
619
s->dsi.complexio_cfg2 = 0;
620
s->dsi.complexio_irqst = 0;
621
s->dsi.complexio_irqen = 0;
623
s->dsi.timing1 = 0x7fff7fff;
624
s->dsi.timing2 = 0x7fff7fff;
625
s->dsi.vm_timing1 = 0;
626
s->dsi.vm_timing2 = 0;
627
s->dsi.vm_timing3 = 0;
628
s->dsi.vm_timing4 = 0;
629
s->dsi.vm_timing5 = 0;
630
s->dsi.vm_timing6 = 0;
631
s->dsi.vm_timing7 = 0;
632
s->dsi.clk_timing = 0x0101;
633
s->dsi.stopclk_timing = 0x80;
634
s->dsi.tx_fifo_vc_size = 0;
635
s->dsi.rx_fifo_vc_size = 0;
636
for (i = 0; i < 4; i++) {
637
s->dsi.vc[i].ctrl = 0;
639
s->dsi.vc[i].lp_header = 0;
640
s->dsi.vc[i].lp_payload = 0;
641
s->dsi.vc[i].lp_counter = 0;
642
s->dsi.vc[i].sp_header = 0;
643
s->dsi.vc[i].irqst = 0;
644
s->dsi.vc[i].irqen = 0;
645
s->dsi.vc[i].rx_fifo_pos = 0;
646
s->dsi.vc[i].rx_fifo_len = 0;
648
if (s->mpu_model < omap3630) {
649
s->dsi.phy_cfg0 = 0x1a3c1a28;
650
s->dsi.phy_cfg1 = 0x420a1875;
651
s->dsi.phy_cfg2 = 0xb800001b;
653
s->dsi.phy_cfg0 = 0x1e481d3a;
654
s->dsi.phy_cfg1 = 0x420a1a6a;
655
s->dsi.phy_cfg2 = 0xb800001a;
657
s->dsi.pll_control = 0;
659
s->dsi.pll_config1 = 0;
660
s->dsi.pll_config2 = 0;
661
omap_dss_interrupt_update(s);
664
static void omap_rfbi_reset(struct omap_dss_s *s)
666
s->rfbi.idlemode = 0;
670
s->rfbi.skiplines = 0;
672
s->rfbi.config[0] = 0x00310000;
673
s->rfbi.config[1] = 0x00310000;
688
static void omap_dss_reset(DeviceState *dev)
692
struct omap_dss_s *s = FROM_SYSBUS(struct omap_dss_s,
693
SYS_BUS_DEVICE(dev));
694
s->autoidle = 0x10; /* was 0 for OMAP2 but bit4 must be set for OMAP3 */
696
if (s->mpu_model == omap3430) {
699
s->dss_status = 0x81; /* bit 7 is not present prior to OMAP3 */
700
} else { /* omap2, omap3630 */
701
s->dss_status = 0x01;
704
s->dispc.idlemode = 0;
707
s->dispc.control = 0;
709
s->dispc.capable = 0x161;
710
s->dispc.timing[0] = 0;
711
s->dispc.timing[1] = 0;
712
s->dispc.timing[2] = 0;
713
s->dispc.timing[3] = 0x00010002;
717
s->dispc.trans[0] = 0;
718
s->dispc.trans[1] = 0;
719
s->dispc.size_dig = 0;
720
s->dispc.size_lcd = 0;
721
s->dispc.global_alpha = 0;
722
s->dispc.cpr_coef_r = 0;
723
s->dispc.cpr_coef_g = 0;
724
s->dispc.cpr_coef_b = 0;
726
for (i = 0; i < 3; i++) {
727
s->dispc.plane[i].enable = 0;
728
s->dispc.plane[i].bpp = 0;
729
s->dispc.plane[i].addr[0] = 0;
730
s->dispc.plane[i].addr[1] = 0;
731
s->dispc.plane[i].addr[2] = 0;
732
s->dispc.plane[i].posx = 0;
733
s->dispc.plane[i].posy = 0;
734
s->dispc.plane[i].nx = 1;
735
s->dispc.plane[i].ny = 1;
736
s->dispc.plane[i].attr = 0;
737
s->dispc.plane[i].tresh = (s->dispc.rev < 0x30) ? 0 : 0x03ff03c0;
738
s->dispc.plane[i].rowinc = 1;
739
s->dispc.plane[i].colinc = 1;
740
s->dispc.plane[i].wininc = 0;
741
s->dispc.plane[i].preload = 0x100;
742
s->dispc.plane[i].fir = 0;
743
s->dispc.plane[i].picture_size = 0;
744
s->dispc.plane[i].accu[0] = 0;
745
s->dispc.plane[i].accu[1] = 0;
746
for (j = 0; j < 5; j++)
747
s->dispc.plane[i].conv_coef[j] = 0;
748
for (j = 0; j < 8; j++) {
749
s->dispc.plane[i].fir_coef_h[j] = 0;
750
s->dispc.plane[i].fir_coef_hv[j] = 0;
751
s->dispc.plane[i].fir_coef_v[j] = 0;
757
omap_dss_panel_reset(&s->lcd);
758
omap_dss_panel_reset(&s->dig);
759
omap_dss_interrupt_update(s);
762
static uint64_t omap_diss_read(void *opaque, hwaddr addr,
765
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
769
return omap_badwidth_read32(opaque, addr);
773
case 0x00: /* DSS_REVISIONNUMBER */
774
TRACEDISS("DSS_REVISIONNUMBER: 0x20");
777
case 0x10: /* DSS_SYSCONFIG */
778
TRACEDISS("DSS_SYSCONFIG: 0x%08x", s->autoidle);
781
case 0x14: /* DSS_SYSSTATUS */
782
TRACEDISS("DSS_SYSSTATUS: 0x1");
783
return 1; /* RESETDONE */
785
case 0x18: /* DSS_IRQSTATUS */
786
x = (s->dispc.irqst & s->dispc.irqen) ? 1 : 0;
787
if ((s->dsi.irqst & s->dsi.irqen)
788
| (s->dsi.complexio_irqst & s->dsi.complexio_irqen)
789
| (s->dsi.vc[0].irqst & s->dsi.vc[0].irqen)
790
| (s->dsi.vc[1].irqst & s->dsi.vc[1].irqen)
791
| (s->dsi.vc[2].irqst & s->dsi.vc[2].irqen)
792
| (s->dsi.vc[3].irqst & s->dsi.vc[3].irqen))
794
TRACEDISS("DSS_IRQSTATUS: 0x%08x", x);
797
case 0x40: /* DSS_CONTROL */
798
TRACEDISS("DSS_CONTROL: 0x%08x", s->control);
801
case 0x44: /* DSS_SDI_CONTROL */
802
if (s->mpu_model == omap3430) {
803
TRACEDISS("DSS_SDI_CONTROL: 0x%08x", s->sdi_control);
804
return s->sdi_control;
808
case 0x48: /* DSS_PLL_CONTROL */
809
if (s->mpu_model == omap3430) {
810
TRACEDISS("DSS_PLL_CONTROL: 0x%08x", s->pll_control);
811
return s->pll_control;
815
case 0x50: /* DSS_PSA_LCD_REG_1 */
816
case 0x54: /* DSS_PSA_LCD_REG_2 */
817
case 0x58: /* DSS_PSA_VIDEO_REG */
818
if (s->mpu_model < omap3430) {
819
TRACEDISS("DSS_PSA_xxx: 0");
820
/* TODO: fake some values according to s->control bits */
827
if (s->mpu_model < omap3430) {
828
TRACEDISS("DSS_STATUS: 0x%08x", x);
830
if (s->mpu_model == omap3430) {
831
s->dss_status &= ~(1 << 6); /* SDI_PLL_BUSYFLAG */
832
TRACEDISS("DSS_SDI_STATUS: 0x%08x", x);
833
} else { /* omap3630 */
834
TRACEDISS("DSS_CLK_STATUS: 0x%08x", x);
845
static void omap_diss_write(void *opaque, hwaddr addr,
846
uint64_t value, unsigned size)
848
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
851
return omap_badwidth_write32(opaque, addr, value);
855
case 0x00: /* DSS_REVISIONNUMBER */
856
case 0x14: /* DSS_SYSSTATUS */
857
case 0x18: /* DSS_IRQSTATUS */
858
case 0x50: /* DSS_PSA_LCD_REG_1 */
859
case 0x54: /* DSS_PSA_LCD_REG_2 */
860
case 0x58: /* DSS_PSA_VIDEO_REG */
861
case 0x5c: /* DSS_STATUS */
863
/*OMAP_RO_REGV(addr, value);*/
866
case 0x10: /* DSS_SYSCONFIG */
867
TRACEDISS("DSS_SYSCONFIG = 0x%08x", value);
868
if (value & 2) { /* SOFTRESET */
869
omap_dss_reset(&s->busdev.qdev);
871
if (s->mpu_model < omap3430) {
879
case 0x40: /* DSS_CONTROL */
880
TRACEDISS("DSS_CONTROL = 0x%08x", value);
881
if (s->mpu_model < omap3430) {
887
s->dss_status &= ~0x3;
888
s->dss_status |= 1 + (s->control & 1);
891
case 0x44: /* DSS_SDI_CONTROL */
892
if (s->mpu_model == omap3430) {
893
TRACEDISS("DSS_SDI_CONTROL = 0x%08x", value);
894
s->sdi_control = value & 0x000ff80f;
896
OMAP_BAD_REGV(addr, value);
900
case 0x48: /* DSS_PLL_CONTROL */
901
if (s->mpu_model == omap3430) {
902
TRACEDISS("DSS_PLL_CONTROL = 0x%08x", value);
903
if (value & (1 << 18)) { /* SDI_PLL_SYSRESET */
904
s->dss_status |= 1 << 2; /* SDI_PLL_RESETDONE */
906
s->dss_status &= ~(1 << 2); /* SDI_PLL_RESETDONE */
908
if (value & (1 << 28)) { /* SDI_PLL_GOBIT */
909
s->dss_status |= 1 << 6; /* SDI_PLL_BUSYFLAG */
910
s->dss_status &= ~(1 << 5); /* SDI_PLL_LOCK */
912
if (s->pll_control & (1 << 28)) { /* SDI_PLL_GOBIT */
913
s->dss_status &= ~(1 << 6); /* SDI_PLL_BUSYFLAG */
914
s->dss_status |= 1 << 5; /* SDI_PLL_LOCK */
917
s->pll_control = value;
919
OMAP_BAD_REGV(addr, value);
924
OMAP_BAD_REGV(addr, value);
929
static const MemoryRegionOps omap_diss_ops = {
930
.read = omap_diss_read,
931
.write = omap_diss_write,
932
.endianness = DEVICE_NATIVE_ENDIAN,
935
static uint64_t omap_disc_read(void *opaque, hwaddr addr,
938
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
942
return omap_badwidth_read32(opaque, addr);
946
case 0x000: /* DISPC_REVISION */
947
TRACEDISPC("DISPC_REVISION: 0x%08x", s->dispc.rev);
949
case 0x010: /* DISPC_SYSCONFIG */
950
TRACEDISPC("DISPC_SYSCONFIG: 0x%08x", s->dispc.idlemode);
951
return s->dispc.idlemode;
952
case 0x014: /* DISPC_SYSSTATUS */
953
TRACEDISPC("DISPC_SYSSTATUS: 1");
954
return 1; /* RESETDONE */
955
case 0x018: /* DISPC_IRQSTATUS */
956
TRACEDISPC("DISPC_IRQSTATUS: 0x%08x", s->dispc.irqst);
957
return s->dispc.irqst;
958
case 0x01c: /* DISPC_IRQENABLE */
959
TRACEDISPC("DISPC_IRQENABLE: 0x%08x", s->dispc.irqen);
960
return s->dispc.irqen;
961
case 0x040: /* DISPC_CONTROL */
962
TRACEDISPC("DISPC_CONTROL: 0x%08x", s->dispc.control);
963
return s->dispc.control;
964
case 0x044: /* DISPC_CONFIG */
965
TRACEDISPC("DISPC_CONFIG: 0x%08x", s->dispc.config);
966
return s->dispc.config;
967
case 0x048: /* DISPC_CAPABLE */
968
TRACEDISPC("DISPC_CAPABLE: 0x%08x", s->dispc.capable);
969
return s->dispc.capable;
970
case 0x04c: /* DISPC_DEFAULT_COLOR0 */
971
TRACEDISPC("DISPC_DEFAULT_COLOR0: 0x%08x", s->dispc.bg[0]);
972
return s->dispc.bg[0];
973
case 0x050: /* DISPC_DEFAULT_COLOR1 */
974
TRACEDISPC("DISPC_DEFAULT_COLOR0: 0x%08x", s->dispc.bg[1]);
975
return s->dispc.bg[1];
976
case 0x054: /* DISPC_TRANS_COLOR0 */
977
TRACEDISPC("DISPC_TRANS_COLOR0: 0x%08x", s->dispc.trans[0]);
978
return s->dispc.trans[0];
979
case 0x058: /* DISPC_TRANS_COLOR1 */
980
TRACEDISPC("DISPC_TRANS_COLOR0: 0x%08x", s->dispc.trans[1]);
981
return s->dispc.trans[1];
982
case 0x05c: /* DISPC_LINE_STATUS */
983
TRACEDISPC("DISPC_LINE_STATUS: 0x7ff");
985
case 0x060: /* DISPC_LINE_NUMBER */
986
TRACEDISPC("DISPC_LINE_NUMBER: 0x%08x", s->dispc.line);
987
return s->dispc.line;
988
case 0x064: /* DISPC_TIMING_H */
989
TRACEDISPC("DISPC_TIMING_H: 0x%08x", s->dispc.timing[0]);
990
return s->dispc.timing[0];
991
case 0x068: /* DISPC_TIMING_V */
992
TRACEDISPC("DISPC_TIMING_H: 0x%08x", s->dispc.timing[1]);
993
return s->dispc.timing[1];
994
case 0x06c: /* DISPC_POL_FREQ */
995
TRACEDISPC("DISPC_POL_FREQ: 0x%08x", s->dispc.timing[2]);
996
return s->dispc.timing[2];
997
case 0x070: /* DISPC_DIVISOR */
998
TRACEDISPC("DISPC_DIVISOR: 0x%08x", s->dispc.timing[3]);
999
return s->dispc.timing[3];
1000
case 0x074: /* DISPC_GLOBAL_ALPHA */
1001
TRACEDISPC("DISPC_GLOBAL_ALPHA: 0x%08x", s->dispc.global_alpha);
1002
return s->dispc.global_alpha;
1003
case 0x078: /* DISPC_SIZE_DIG */
1004
TRACEDISPC("DISPC_SIZE_DIG: 0x%08x", s->dispc.size_dig);
1005
return s->dispc.size_dig;
1006
case 0x07c: /* DISPC_SIZE_LCD */
1007
TRACEDISPC("DISPC_SIZE_LCD: 0x%08x", s->dispc.size_lcd);
1008
return s->dispc.size_lcd;
1009
case 0x14c: /* DISPC_VID2_BA0 */
1011
case 0x0bc: /* DISPC_VID1_BA0 */
1013
case 0x080: /* DISPC_GFX_BA0 */
1014
TRACEDISPC("DISPC_%s_BA0: " OMAP_FMT_plx, LAYERNAME(n),
1015
s->dispc.plane[n].addr[0]);
1016
return s->dispc.plane[n].addr[0];
1017
case 0x150: /* DISPC_VID2_BA1 */
1019
case 0x0c0: /* DISPC_VID1_BA1 */
1021
case 0x084: /* DISPC_GFX_BA1 */
1022
TRACEDISPC("DISPC_%s_BA1: " OMAP_FMT_plx, LAYERNAME(n),
1023
s->dispc.plane[n].addr[1]);
1024
return s->dispc.plane[n].addr[1];
1025
case 0x154: /* DISPC_VID2_POSITION */
1027
case 0x0c4: /* DISPC_VID1_POSITION */
1029
case 0x088: /* DISPC_GFX_POSITION */
1030
TRACEDISPC("DISPC_%s_POSITION: 0x%08x", LAYERNAME(n),
1031
(s->dispc.plane[n].posy << 16) | s->dispc.plane[n].posx);
1032
return (s->dispc.plane[n].posy << 16) | s->dispc.plane[n].posx;
1033
case 0x158: /* DISPC_VID2_SIZE */
1035
case 0x0c8: /* DISPC_VID1_SIZE */
1037
case 0x08c: /* DISPC_GFX_SIZE */
1038
TRACEDISPC("DISPC_%s_SIZE: 0x%08x", LAYERNAME(n),
1039
((s->dispc.plane[n].ny - 1) << 16)
1040
| (s->dispc.plane[n].nx - 1));
1041
return ((s->dispc.plane[n].ny - 1) << 16) | (s->dispc.plane[n].nx - 1);
1042
case 0x15c: /* DISPC_VID2_ATTRIBUTES */
1044
case 0x0cc: /* DISPC_VID1_ATTRIBUTES */
1046
case 0x0a0: /* DISPC_GFX_ATTRIBUTES */
1047
TRACEDISPC("DISPC_%s_ATTRIBUTES: 0x%08x", LAYERNAME(n),
1048
s->dispc.plane[n].attr);
1049
return s->dispc.plane[n].attr;
1050
case 0x160: /* DISPC_VID2_FIFO_THRESHOLD */
1052
case 0x0d0: /* DISPC_VID1_FIFO_THRESHOLD */
1054
case 0x0a4: /* DISPC_GFX_FIFO_TRESHOLD */
1055
TRACEDISPC("DISPC_%s_THRESHOLD: 0x%08x", LAYERNAME(n),
1056
s->dispc.plane[n].tresh);
1057
return s->dispc.plane[n].tresh;
1058
case 0x164: /* DISPC_VID2_FIFO_SIZE_STATUS */
1060
case 0x0d4: /* DISPC_VID1_FIFO_SIZE_STATUS */
1062
case 0x0a8: /* DISPC_GFX_FIFO_SIZE_STATUS */
1063
TRACEDISPC("DISPC_%s_FIFO_SIZE_STATUS: 0x%08x", LAYERNAME(n),
1064
s->dispc.rev < 0x30 ? 256 : 1024);
1065
return s->dispc.rev < 0x30 ? 256 : 1024;
1066
case 0x168: /* DISPC_VID2_ROW_INC */
1068
case 0x0d8: /* DISPC_VID1_ROW_INC */
1070
case 0x0ac: /* DISPC_GFX_ROW_INC */
1071
TRACEDISPC("DISPC_%s_ROW_INC: 0x%08x", LAYERNAME(n),
1072
s->dispc.plane[n].rowinc);
1073
return s->dispc.plane[n].rowinc;
1074
case 0x16c: /* DISPC_VID2_PIXEL_INC */
1076
case 0x0dc: /* DISPC_VID1_PIXEL_INC */
1078
case 0x0b0: /* DISPC_GFX_PIXEL_INC */
1079
TRACEDISPC("DISPC_%s_PIXEL_INC: 0x%08x", LAYERNAME(n),
1080
s->dispc.plane[n].colinc);
1081
return s->dispc.plane[n].colinc;
1082
case 0x0b4: /* DISPC_GFX_WINDOW_SKIP */
1083
TRACEDISPC("DISPC_GFX_WINDOW_SKIP: 0x%08x", s->dispc.plane[0].wininc);
1084
return s->dispc.plane[0].wininc;
1085
case 0x0b8: /* DISPC_GFX_TABLE_BA */
1086
TRACEDISPC("DISPC_GFX_TABLE_BA: " OMAP_FMT_plx,
1087
s->dispc.plane[0].addr[2]);
1088
return s->dispc.plane[0].addr[2];
1089
case 0x170: /* DISPC_VID2_FIR */
1091
case 0x0e0: /* DISPC_VID1_FIR */
1093
TRACEDISPC("DISPC_%s_FIR: 0x%08x", LAYERNAME(n),
1094
s->dispc.plane[n].fir);
1095
return s->dispc.plane[n].fir;
1096
case 0x174: /* DISPC_VID2_PICTURE_SIZE */
1098
case 0x0e4: /* DISPC_VID1_PICTURE_SIZE */
1100
TRACEDISPC("DISPC_%s_PICTURE_SIZE: 0x%08x", LAYERNAME(n),
1101
s->dispc.plane[n].picture_size);
1102
return s->dispc.plane[n].picture_size;
1103
case 0x178: /* DISPC_VID2_ACCU0 */
1104
case 0x17c: /* DISPC_VID2_ACCU1 */
1106
case 0x0e8: /* DISPC_VID1_ACCU0 */
1107
case 0x0ec: /* DISPC_VID1_ACCU1 */
1109
TRACEDISPC("DISPC_%s_ACCU%d: 0x%08x", LAYERNAME(n),
1110
(int)((addr >> 1) & 1),
1111
s->dispc.plane[n].accu[(addr >> 1 ) & 1]);
1112
return s->dispc.plane[n].accu[(addr >> 1) & 1];
1113
case 0x180 ... 0x1bc: /* DISPC_VID2_FIR_COEF */
1115
case 0x0f0 ... 0x12c: /* DISPC_VID1_FIR_COEF */
1118
TRACEDISPC("DISPC_%s_FIR_COEF_HV%d: 0x%08x", LAYERNAME(n),
1119
(int)((addr - ((n > 1) ? 0x180 : 0xf0)) / 8),
1120
s->dispc.plane[n].fir_coef_hv[
1121
(addr - ((n > 1) ? 0x180 : 0xf0)) / 8]);
1122
return s->dispc.plane[n].fir_coef_hv[
1123
(addr - ((n > 1) ? 0x180 : 0xf0)) / 8];
1125
TRACEDISPC("DISPC_%s_FIR_COEF_H%d: 0x%08x", LAYERNAME(n),
1126
(int)((addr - ((n > 1) ? 0x180 : 0xf0)) / 8),
1127
s->dispc.plane[n].fir_coef_h[
1128
(addr - ((n > 1) ? 0x180 : 0xf0)) / 8]);
1129
return s->dispc.plane[n].fir_coef_h[
1130
(addr - ((n > 1) ? 0x180 : 0xf0)) / 8];
1131
case 0x1c0 ... 0x1d0: /* DISPC_VID2_CONV_COEFi */
1133
case 0x130 ... 0x140: /* DISPC_VID1_CONV_COEFi */
1135
TRACEDISPC("DISPC_%s_CONV_COEF%d: 0x%08x", LAYERNAME(n),
1136
(int)((addr - ((n > 1) ? 0x1c0 : 0x130)) / 4),
1137
s->dispc.plane[n].conv_coef[
1138
(addr - ((n > 1) ? 0x1c0 : 0x130)) / 4]);
1139
return s->dispc.plane[n].conv_coef[
1140
(addr - ((n > 1) ? 0x1c0 : 0x130)) / 4];
1141
case 0x1d4: /* DISPC_DATA_CYCLE1 */
1142
case 0x1d8: /* DISPC_DATA_CYCLE2 */
1143
case 0x1dc: /* DISPC_DATA_CYCLE3 */
1144
TRACEDISPC("DISPC_DATA_CYCLE%d: 0", (int)((addr - 0x1d4) / 4));
1146
case 0x200 ... 0x21c: /* DISPC_VID2_FIR_COEF_Vi */
1148
case 0x1e0 ... 0x1fc: /* DISPC_VID1_FIR_COEF_Vi */
1150
TRACEDISPC("DISPC_%s_FIR_COEF_V%d: 0x%08x", LAYERNAME(n),
1151
(int)((addr & 0x01f) / 4),
1152
s->dispc.plane[n].fir_coef_v[(addr & 0x01f) / 4]);
1153
return s->dispc.plane[n].fir_coef_v[(addr & 0x01f) / 4];
1154
case 0x220: /* DISPC_CPR_COEF_R */
1155
TRACEDISPC("DISPC_CPR_COEF_R: 0x%08x", s->dispc.cpr_coef_r);
1156
return s->dispc.cpr_coef_r;
1157
case 0x224: /* DISPC_CPR_COEF_G */
1158
TRACEDISPC("DISPC_CPR_COEF_G: 0x%08x", s->dispc.cpr_coef_g);
1159
return s->dispc.cpr_coef_g;
1160
case 0x228: /* DISPC_CPR_COEF_B */
1161
TRACEDISPC("DISPC_CPR_COEF_B: 0x%08x", s->dispc.cpr_coef_b);
1162
return s->dispc.cpr_coef_b;
1163
case 0x234: /* DISPC_VID2_PRELOAD */
1165
case 0x230: /* DISPC_VID1_PRELOAD */
1167
case 0x22c: /* DISPC_GFX_PRELOAD */
1168
TRACEDISPC("DISPC_%s_PRELOAD: 0x%08x", LAYERNAME(n),
1169
s->dispc.plane[n].preload);
1170
return s->dispc.plane[n].preload;
1178
static void omap_disc_write(void *opaque, hwaddr addr,
1179
uint64_t value, unsigned size)
1181
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
1185
return omap_badwidth_write32(opaque, addr, value);
1189
case 0x000: /* DISPC_REVISION */
1190
case 0x014: /* DISPC_SYSSTATUS */
1191
case 0x05c: /* DISPC_LINE_STATUS */
1192
case 0x0a8: /* DISPC_GFX_FIFO_SIZE_STATUS */
1193
/* quietly ignore */
1194
/*OMAP_RO_REGV(addr, value);*/
1196
case 0x010: /* DISPC_SYSCONFIG */
1197
TRACEDISPC("DISPC_SYSCONFIG = 0x%08x", value);
1198
if (value & 2) { /* SOFTRESET */
1199
omap_dss_reset(&s->busdev.qdev);
1201
s->dispc.idlemode = value & ((s->dispc.rev < 0x30) ? 0x301b : 0x331f);
1203
case 0x018: /* DISPC_IRQSTATUS */
1204
TRACEDISPC("DISPC_IRQSTATUS = 0x%08x", value);
1205
s->dispc.irqst &= ~value;
1206
omap_dss_interrupt_update(s);
1208
case 0x01c: /* DISPC_IRQENABLE */
1209
TRACEDISPC("DISPC_IRQENABLE = 0x%08x", value);
1210
s->dispc.irqen = value & ((s->dispc.rev < 0x30) ? 0xffff : 0x1ffff);
1211
omap_dss_interrupt_update(s);
1213
case 0x040: /* DISPC_CONTROL */
1214
TRACEDISPC("DISPC_CONTROL = 0x%08x", value);
1215
n = s->dispc.control; /* cache old value */
1216
/* always clear GODIGITAL and GOLCD to signal completed shadowing */
1217
if (s->dispc.rev < 0x30) {
1218
s->dispc.control = value & 0x07ff9f9f;
1220
s->dispc.control = (value & 0xffff9b9f)
1221
| (s->dispc.control & 0x6000);
1223
if (value & (1 << 12)) /* OVERLAY_OPTIMIZATION */
1224
if (!((s->dispc.plane[1].attr | s->dispc.plane[2].attr) & 1)) {
1225
TRACEDISPC("Overlay Optimization when no overlay "
1226
"region effectively exists leads to "
1227
"unpredictable behaviour!");
1229
if ((value & 0x21)) { /* GOLCD | LCDENABLE */
1230
omap_dss_panel_go(s, &s->lcd, s->dispc.size_lcd);
1232
if ((value & 0x42)) { /* GODIGITAL | DIGITALENABLE */
1233
omap_dss_panel_go(s, &s->dig, s->dispc.size_dig);
1235
if (value & 1) { /* LCDENABLE */
1236
if ((value & (1 << 11))) { /* STALLMODE */
1237
if ((s->rfbi.control & 0x11) && /* ITE | ENABLE */
1238
!(s->rfbi.config[0] & s->rfbi.config[1] & 0xc)) { /* TRIGGERMODE */
1239
omap_rfbi_transfer_start(s);
1241
if (s->dsi.ctrl & 1) { /* IF_EN */
1243
for (ch = 0; ch < 4; ch++) {
1244
if ((s->dsi.vc[ch].ctrl & 1) && /* VC_EN */
1245
(s->dsi.vc[ch].te >> 30) & 3) { /* TE_START | TE_EN */
1246
omap_dsi_transfer_start(s, ch);
1250
} else if (s->dispc.lcdframer) {
1251
qemu_mod_timer(s->dispc.lcdframer,
1252
qemu_get_clock_ns(vm_clock)
1253
+ get_ticks_per_sec() / 10);
1255
} else if (n & 1) { /* enable -> disable, signal wip frame done */
1256
s->dispc.control |= 1;
1257
omap_dss_framedone(s);
1258
s->dispc.control &= ~1;
1261
case 0x044: /* DISPC_CONFIG */
1262
TRACEDISPC("DISPC_CONFIG = 0x%08x", value);
1263
s->dispc.config = value & 0x3fff;
1265
* bits 2:1 (LOADMODE) reset to 0 after set to 1 and palette loaded
1266
* bits 2:1 (LOADMODE) reset to 2 after set to 3 and palette loaded
1269
case 0x048: /* DISPC_CAPABLE */
1270
TRACEDISPC("DISPC_CAPABLE = 0x%08x", value);
1271
s->dispc.capable = value & 0x3ff;
1273
case 0x04c: /* DISPC_DEFAULT_COLOR0 */
1274
TRACEDISPC("DISPC_DEFAULT_COLOR0 = 0x%08x", value);
1275
s->dispc.bg[0] = value & 0xffffff;
1277
case 0x050: /* DISPC_DEFAULT_COLOR1 */
1278
TRACEDISPC("DISPC_DEFAULT_COLOR1 = 0x%08x", value);
1279
s->dispc.bg[1] = value & 0xffffff;
1281
case 0x054: /* DISPC_TRANS_COLOR0 */
1282
TRACEDISPC("DISPC_TRANS_COLOR0 = 0x%08x", value);
1283
s->dispc.trans[0] = value & 0xffffff;
1285
case 0x058: /* DISPC_TRANS_COLOR1 */
1286
TRACEDISPC("DISPC_TRANS_COLOR1 = 0x%08x", value);
1287
s->dispc.trans[1] = value & 0xffffff;
1289
case 0x060: /* DISPC_LINE_NUMBER */
1290
TRACEDISPC("DISPC_LINE_NUMBER = 0x%08x", value);
1291
s->dispc.line = value & 0x7ff;
1293
case 0x064: /* DISPC_TIMING_H */
1294
TRACEDISPC("DISPC_TIMING_H = 0x%08x", value);
1295
s->dispc.timing[0] = value & 0x0ff0ff3f;
1297
case 0x068: /* DISPC_TIMING_V */
1298
TRACEDISPC("DISPC_TIMING_V = 0x%08x", value);
1299
s->dispc.timing[1] = value & 0x0ff0ff3f;
1301
case 0x06c: /* DISPC_POL_FREQ */
1302
TRACEDISPC("DISPC_POL_FREQ = 0x%08x", value);
1303
s->dispc.timing[2] = value & 0x0003ffff;
1305
case 0x070: /* DISPC_DIVISOR */
1306
TRACEDISPC("DISPC_DIVISOR = 0x%08x", value);
1307
s->dispc.timing[3] = value & 0x00ff00ff;
1309
case 0x074: /* DISPC_GLOBAL_ALPHA */
1310
TRACEDISPC("DISPC_GLOBAL_ALPHA = 0x%08x", value);
1311
s->dispc.global_alpha = value & 0x00ff00ff;
1313
case 0x078: /* DISPC_SIZE_DIG */
1314
TRACEDISPC("DISPC_SIZE_DIG = 0x%08x (%dx%d)",
1315
value, (value & 0x7ff) + 1, ((value >> 16) & 0x7ff) + 1);
1316
s->dispc.size_dig = value;
1318
case 0x07c: /* DISPC_SIZE_LCD */
1319
TRACEDISPC("DISPC_SIZE_LCD = 0x%08x (%dx%d)",
1320
value, (value & 0x7ff) + 1, ((value >> 16) & 0x7ff) + 1);
1321
s->dispc.size_lcd = value;
1323
case 0x14c: /* DISPC_VID2_BA0 */
1325
case 0x0bc: /* DISPC_VID1_BA0 */
1327
case 0x080: /* DISPC_GFX_BA0 */
1328
TRACEDISPC("DISPC_%s_BA0 = 0x%08x", LAYERNAME(n), value);
1329
s->dispc.plane[n].addr[0] = (hwaddr) value;
1331
case 0x150: /* DISPC_VID2_BA1 */
1333
case 0x0c0: /* DISPC_VID1_BA1 */
1335
case 0x084: /* DISPC_GFX_BA1 */
1336
TRACEDISPC("DISPC_%s_BA1 = 0x%08x", LAYERNAME(n), value);
1337
s->dispc.plane[n].addr[1] = (hwaddr) value;
1339
case 0x154: /* DISPC_VID2_POSITION */
1341
case 0x0c4: /* DISPC_VID1_POSITION */
1343
case 0x088: /* DISPC_GFX_POSITION */
1344
s->dispc.plane[n].posx = ((value >> 0) & 0x7ff); /* GFXPOSX */
1345
s->dispc.plane[n].posy = ((value >> 16) & 0x7ff); /* GFXPOSY */
1346
TRACEDISPC("DISPC_%s_POSITION = 0x%08x (%d,%d)", LAYERNAME(n),
1347
value, s->dispc.plane[n].posx, s->dispc.plane[n].posy);
1349
case 0x158: /* DISPC_VID2_SIZE */
1351
case 0x0c8: /* DISPC_VID1_SIZE */
1353
case 0x08c: /* DISPC_GFX_SIZE */
1354
s->dispc.plane[n].nx = ((value >> 0) & 0x7ff) + 1; /* GFXSIZEX */
1355
s->dispc.plane[n].ny = ((value >> 16) & 0x7ff) + 1; /* GFXSIZEY */
1356
TRACEDISPC("DISPC_%s_SIZE = 0x%08x (%dx%d)", LAYERNAME(n),
1357
value, s->dispc.plane[n].nx, s->dispc.plane[n].ny);
1359
case 0x0a0: /* DISPC_GFX_ATTRIBUTES */
1360
TRACEDISPC("DISPC_GFX_ATTRIBUTES = 0x%08x", value);
1361
if (s->mpu_model < omap3630) {
1364
value &= 0x1000ffff;
1366
s->dispc.plane[0].attr = value;
1367
if (value & (3 << 9)) {
1368
hw_error("%s: Big-endian pixel format not supported",
1371
s->dispc.plane[0].enable = value & 1;
1372
s->dispc.plane[0].bpp = (value >> 1) & 0xf;
1373
s->dispc.plane[0].rotation_flag = (value >> 12) & 0x3;
1374
s->dispc.plane[0].gfx_format = (value >> 1) & 0xf;
1375
s->dispc.plane[0].gfx_channel = (value >> 8) & 0x1;
1377
case 0x160: /* DISPC_VID2_FIFO_TRESHOLD */
1379
case 0x0d0: /* DISPC_VID1_FIFO_TRESHOLD */
1381
case 0x0a4: /* DISPC_GFX_FIFO_THRESHOLD */
1382
TRACEDISPC("DISPC_%s_FIFO_THRESHOLD = 0x%08x", LAYERNAME(n), value);
1383
s->dispc.plane[n].tresh = value & ((s->dispc.rev < 0x30)
1384
? 0x01ff01ff : 0x0fff0fff);
1386
case 0x168: /* DISPC_VID2_ROW_INC */
1388
case 0x0d8: /* DISPC_VID1_ROW_INC */
1390
case 0x0ac: /* DISPC_GFX_ROW_INC */
1391
TRACEDISPC("DISPC_%s_ROW_INC = 0x%08x", LAYERNAME(n), value);
1392
s->dispc.plane[n].rowinc = value;
1394
case 0x16c: /* DISPC_VID2_PIXEL_INC */
1396
case 0x0dc: /* DISPC_VID1_PIXEL_INC */
1398
case 0x0b0: /* DISPC_GFX_PIXEL_INC */
1399
TRACEDISPC("DISPC_%s_PIXEL_INC = 0x%08x", LAYERNAME(n), value);
1400
s->dispc.plane[n].colinc = value;
1402
case 0x0b4: /* DISPC_GFX_WINDOW_SKIP */
1403
TRACEDISPC("DISPC_GFX_WINDOW_SKIP = 0x%08x", value);
1404
s->dispc.plane[0].wininc = value;
1406
case 0x0b8: /* DISPC_GFX_TABLE_BA */
1407
TRACEDISPC("DISPC_GFX_TABLE_BA = 0x%08x", value);
1408
s->dispc.plane[0].addr[2] = (hwaddr) value;
1410
case 0x15c: /* DISPC_VID2_ATTRIBUTES */
1412
case 0x0cc: /* DISPC_VID1_ATTRIBUTES */
1414
TRACEDISPC("DISPC_%s_ATTRIBUTES = 0x%08x", LAYERNAME(n), value);
1415
if (s->mpu_model < omap3630) {
1416
value &= 0x01ffffff;
1418
value &= 0x11ffffff;
1420
s->dispc.plane[n].attr = value;
1422
case 0x170: /* DISPC_VID2_FIR */
1424
case 0x0e0: /* DISPC_VID1_FIR */
1426
TRACEDISPC("DISPC_%s_FIR = 0x%08x", LAYERNAME(n), value);
1427
s->dispc.plane[n].fir = value & 0x1fff1fff;
1429
case 0x174: /* DISPC_VID2_PICTURE_SIZE */
1431
case 0x0e4: /* DISPC_VID1_PICTURE_SIZE */
1433
TRACEDISPC("DISPC_%s_PICTURE_SIZE = 0x%08x", LAYERNAME(n), value);
1434
s->dispc.plane[n].picture_size = value & 0x07ff07ff;
1436
case 0x178: /* DISPC_VID2_ACCU0 */
1437
case 0x17c: /* DISPC_VID2_ACCU1 */
1439
case 0x0e8: /* DISPC_VID1_ACCU0 */
1440
case 0x0ec: /* DISPC_VID1_ACCU1 */
1442
TRACEDISPC("DISPC_%s_ACCU%d = 0x%08x", LAYERNAME(n),
1443
(int)((addr >> 1) & 1), value);
1444
s->dispc.plane[n].accu[(addr >> 1) & 1] = value & 0x03ff03ff;
1446
case 0x180 ... 0x1bc: /* DISPC_VID2_FIR_COEF */
1448
case 0x0f0 ... 0x12c: /* DISPC_VID1_FIR_COEF */
1451
TRACEDISPC("DISPC_%s_FIR_COEF_HV%d = 0x%08x", LAYERNAME(n),
1452
(int)((addr - ((n > 1) ? 0x180 : 0xf0)) / 8), value);
1453
s->dispc.plane[n].fir_coef_hv[(addr - ((n > 1) ? 0x180 : 0xf0)) / 8] = value;
1455
TRACEDISPC("DISPC_%s_FIR_COEF_H%d = 0x%08x", LAYERNAME(n),
1456
(int)((addr - ((n > 1) ? 0x180 : 0xf0)) / 8), value);
1457
s->dispc.plane[n].fir_coef_h[(addr - ((n > 1) ? 0x180 : 0xf0)) / 8] = value;
1460
case 0x1c0 ... 0x1d0: /* DISPC_VID2_CONV_COEFi */
1462
case 0x130 ... 0x140: /* DISPC_VID1_CONV_COEFi */
1464
TRACEDISPC("DISPC_%s_CONV_COEF%d = 0x%08x", LAYERNAME(n),
1465
(int)((addr - ((n > 1) ? 0x1c0 : 0x130)) / 4), value);
1466
s->dispc.plane[n].conv_coef[(addr - ((n > 1) ? 0x1c0 : 0x130)) / 4] = value;
1468
case 0x1d4: /* DISPC_DATA_CYCLE1 */
1469
case 0x1d8: /* DISPC_DATA_CYCLE2 */
1470
case 0x1dc: /* DISPC_DATA_CYCLE3 */
1471
TRACEDISPC("DISPC_DATA_CYCLE%d = 0x%08x (ignored)",
1472
(int)((addr - 0x1d4) / 4), value);
1474
case 0x200 ... 0x21c: /* DISPC_VID2_FIR_COEF_Vi */
1476
case 0x1e0 ... 0x1fc: /* DISPC_VID1_FIR_COEF_Vi */
1478
TRACEDISPC("DISPC_%s_FIR_COEF_V%d = 0x%08x", LAYERNAME(n),
1479
(int)((addr & 0x01f) / 4), value);
1480
s->dispc.plane[n].fir_coef_v[(addr & 0x01f) / 4] = value & 0x0000ffff;
1482
case 0x220: /* DISPC_CPR_COEF_R */
1483
TRACEDISPC("DISPC_CPR_COEF_R = 0x%08x", value);
1484
s->dispc.cpr_coef_r = value & 0xffbffbff;
1486
case 0x224: /* DISPC_CPR_COEF_G */
1487
TRACEDISPC("DISPC_CPR_COEF_G = 0x%08x", value);
1488
s->dispc.cpr_coef_g = value & 0xffbffbff;
1490
case 0x228: /* DISPC_CPR_COEF_B */
1491
TRACEDISPC("DISPC_CPR_COEF_B = 0x%08x", value);
1492
s->dispc.cpr_coef_b = value & 0xffbffbff;
1494
case 0x234: /* DISPC_VID2_PRELOAD */
1496
case 0x230: /* DISPC_VID1_PRELOAD */
1498
case 0x22c: /* DISPC_GFX_PRELOAD */
1499
TRACEDISPC("DISPC_%s_PRELOAD = 0x%08x", LAYERNAME(n), value);
1500
s->dispc.plane[n].preload = value & 0x0fff;
1503
OMAP_BAD_REGV(addr, value);
1508
static const MemoryRegionOps omap_disc_ops = {
1509
.read = omap_disc_read,
1510
.write = omap_disc_write,
1511
.endianness = DEVICE_NATIVE_ENDIAN,
1514
static uint64_t omap_rfbi_read(void *opaque, hwaddr addr,
1517
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
1520
return omap_badwidth_read32(opaque, addr);
1524
case 0x00: /* RFBI_REVISION */
1525
TRACERFBI("RFBI_REVISION: 0x10");
1528
case 0x10: /* RFBI_SYSCONFIG */
1529
TRACERFBI("RFBI_SYSCONFIG: 0x%08x", s->rfbi.idlemode);
1530
return s->rfbi.idlemode;
1532
case 0x14: /* RFBI_SYSSTATUS */
1533
TRACERFBI("RFBI_SYSSTATUS: 0x%08x", 1 | (s->rfbi.busy << 8));
1534
return 1 | (s->rfbi.busy << 8); /* RESETDONE */
1536
case 0x40: /* RFBI_CONTROL */
1537
TRACERFBI("RFBI_CONTROL: 0x%08x", s->rfbi.control);
1538
return s->rfbi.control;
1540
case 0x44: /* RFBI_PIXELCNT */
1541
TRACERFBI("RFBI_PIXELCNT: 0x%08x", s->rfbi.pixels);
1542
return s->rfbi.pixels;
1544
case 0x48: /* RFBI_LINE_NUMBER */
1545
TRACERFBI("RFBI_LINE_NUMBER: 0x%08x", s->rfbi.skiplines);
1546
return s->rfbi.skiplines;
1548
case 0x58: /* RFBI_READ */
1549
case 0x5c: /* RFBI_STATUS */
1550
TRACERFBI("RFBI_READ/STATUS: 0x%08x", s->rfbi.rxbuf);
1551
return s->rfbi.rxbuf;
1553
case 0x60: /* RFBI_CONFIG0 */
1554
TRACERFBI("RFBI_CONFIG0: 0x%08x", s->rfbi.config[0]);
1555
return s->rfbi.config[0];
1556
case 0x64: /* RFBI_ONOFF_TIME0 */
1557
TRACERFBI("RFBI_ONOFF_TIME0: 0x%08x", s->rfbi.time[0]);
1558
return s->rfbi.time[0];
1559
case 0x68: /* RFBI_CYCLE_TIME0 */
1560
TRACERFBI("RFBI_CYCLE_TIME0: 0x%08x", s->rfbi.time[1]);
1561
return s->rfbi.time[1];
1562
case 0x6c: /* RFBI_DATA_CYCLE1_0 */
1563
TRACERFBI("RFBI_DATA_CYCLE1_0: 0x%08x", s->rfbi.data[0]);
1564
return s->rfbi.data[0];
1565
case 0x70: /* RFBI_DATA_CYCLE2_0 */
1566
TRACERFBI("RFBI_DATA_CYCLE2_0: 0x%08x", s->rfbi.data[1]);
1567
return s->rfbi.data[1];
1568
case 0x74: /* RFBI_DATA_CYCLE3_0 */
1569
TRACERFBI("RFBI_DATA_CYCLE3_0: 0x%08x", s->rfbi.data[2]);
1570
return s->rfbi.data[2];
1572
case 0x78: /* RFBI_CONFIG1 */
1573
TRACERFBI("RFBI_CONFIG1: 0x%08x", s->rfbi.config[1]);
1574
return s->rfbi.config[1];
1575
case 0x7c: /* RFBI_ONOFF_TIME1 */
1576
TRACERFBI("RFBI_ONOFF_TIME1: 0x%08x", s->rfbi.time[2]);
1577
return s->rfbi.time[2];
1578
case 0x80: /* RFBI_CYCLE_TIME1 */
1579
TRACERFBI("RFBI_CYCLE_TIME1: 0x%08x", s->rfbi.time[3]);
1580
return s->rfbi.time[3];
1581
case 0x84: /* RFBI_DATA_CYCLE1_1 */
1582
TRACERFBI("RFBI_DATA_CYCLE1_1: 0x%08x", s->rfbi.data[3]);
1583
return s->rfbi.data[3];
1584
case 0x88: /* RFBI_DATA_CYCLE2_1 */
1585
TRACERFBI("RFBI_DATA_CYCLE2_1: 0x%08x", s->rfbi.data[4]);
1586
return s->rfbi.data[4];
1587
case 0x8c: /* RFBI_DATA_CYCLE3_1 */
1588
TRACERFBI("RFBI_DATA_CYCLE3_1: 0x%08x", s->rfbi.data[5]);
1589
return s->rfbi.data[5];
1591
case 0x90: /* RFBI_VSYNC_WIDTH */
1592
TRACERFBI("RFBI_VSYNC_WIDTH: 0x%08x", s->rfbi.vsync);
1593
return s->rfbi.vsync;
1594
case 0x94: /* RFBI_HSYNC_WIDTH */
1595
TRACERFBI("RFBI_HSYNC_WIDTH: 0x%08x", s->rfbi.hsync);
1596
return s->rfbi.hsync;
1602
static void omap_rfbi_write(void *opaque, hwaddr addr,
1603
uint64_t value, unsigned size)
1605
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
1608
return omap_badwidth_write32(opaque, addr, value);
1612
case 0x10: /* RFBI_SYSCONFIG */
1613
TRACERFBI("RFBI_SYSCONFIG = 0x%08x", value);
1614
if (value & 2) /* SOFTRESET */
1616
s->rfbi.idlemode = value & 0x19;
1619
case 0x40: /* RFBI_CONTROL */
1620
TRACERFBI("RFBI_CONTROL = 0x%08x", value);
1621
if (s->dispc.rev < 0x30)
1622
s->rfbi.control = value & 0x1f;
1624
s->rfbi.control = value & 0x1ff;
1625
s->rfbi.enable = value & 1;
1626
if ((s->dispc.control & 1) && /* LCDENABLE */
1627
(value & 0x10) && /* ITE */
1628
!(s->rfbi.config[0] & s->rfbi.config[1] & 0xc)) /* TRIGGERMODE */
1629
omap_rfbi_transfer_start(s);
1632
case 0x44: /* RFBI_PIXELCNT */
1633
TRACERFBI("RFBI_PIXELCNT = 0x%08x", value);
1634
s->rfbi.pixels = value;
1637
case 0x48: /* RFBI_LINE_NUMBER */
1638
TRACERFBI("RFBI_LINE_NUMBER = 0x%08x", value);
1639
s->rfbi.skiplines = value & 0x7ff;
1642
case 0x4c: /* RFBI_CMD */
1643
TRACERFBI("RFBI_CMD = 0x%08x", value);
1644
if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0])
1645
s->rfbi.chip[0]->write(s->rfbi.chip[0]->opaque, 0, value & 0xffff);
1646
if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1])
1647
s->rfbi.chip[1]->write(s->rfbi.chip[1]->opaque, 0, value & 0xffff);
1649
case 0x50: /* RFBI_PARAM */
1650
TRACERFBI("RFBI_PARAM = 0x%08x", value);
1651
if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0])
1652
s->rfbi.chip[0]->write(s->rfbi.chip[0]->opaque, 1, value & 0xffff);
1653
if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1])
1654
s->rfbi.chip[1]->write(s->rfbi.chip[1]->opaque, 1, value & 0xffff);
1656
case 0x54: /* RFBI_DATA */
1657
TRACERFBI("RFBI_DATA = 0x%08x", value);
1658
/* TODO: take into account the format set up in s->rfbi.config[?] and
1659
* s->rfbi.data[?], but special-case the most usual scenario so that
1660
* speed doesn't suffer. */
1661
if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0]) {
1662
s->rfbi.chip[0]->write(s->rfbi.chip[0]->opaque, 1, value & 0xffff);
1663
s->rfbi.chip[0]->write(s->rfbi.chip[0]->opaque, 1, value >> 16);
1665
if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1]) {
1666
s->rfbi.chip[1]->write(s->rfbi.chip[1]->opaque, 1, value & 0xffff);
1667
s->rfbi.chip[1]->write(s->rfbi.chip[1]->opaque, 1, value >> 16);
1669
if (!-- s->rfbi.pixels)
1670
omap_rfbi_transfer_stop(s);
1672
case 0x58: /* RFBI_READ */
1673
TRACERFBI("RFBI_READ = 0x%08x", value);
1674
if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0])
1675
s->rfbi.rxbuf = s->rfbi.chip[0]->read(s->rfbi.chip[0]->opaque, 1);
1676
else if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1])
1677
s->rfbi.rxbuf = s->rfbi.chip[1]->read(s->rfbi.chip[1]->opaque, 1);
1678
if (!-- s->rfbi.pixels)
1679
omap_rfbi_transfer_stop(s);
1682
case 0x5c: /* RFBI_STATUS */
1683
TRACERFBI("RFBI_STATUS = 0x%08x", value);
1684
if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0])
1685
s->rfbi.rxbuf = s->rfbi.chip[0]->read(s->rfbi.chip[0]->opaque, 0);
1686
else if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1])
1687
s->rfbi.rxbuf = s->rfbi.chip[1]->read(s->rfbi.chip[1]->opaque, 0);
1688
if (!-- s->rfbi.pixels)
1689
omap_rfbi_transfer_stop(s);
1692
case 0x60: /* RFBI_CONFIG0 */
1693
TRACERFBI("RFBI_CONFIG0 = 0x%08x", value);
1694
s->rfbi.config[0] = value & 0x003f1fff;
1697
case 0x64: /* RFBI_ONOFF_TIME0 */
1698
TRACERFBI("RFBI_ONOFF_TIME0 = 0x%08x", value);
1699
s->rfbi.time[0] = value & 0x3fffffff;
1701
case 0x68: /* RFBI_CYCLE_TIME0 */
1702
TRACERFBI("RFBI_CYCLE_TIME0 = 0x%08x", value);
1703
s->rfbi.time[1] = value & 0x0fffffff;
1705
case 0x6c: /* RFBI_DATA_CYCLE1_0 */
1706
TRACERFBI("RFBI_DATA_CYCLE1_0 = 0x%08x", value);
1707
s->rfbi.data[0] = value & 0x0f1f0f1f;
1709
case 0x70: /* RFBI_DATA_CYCLE2_0 */
1710
TRACERFBI("RFBI_DATA_CYCLE2_0 = 0x%08x", value);
1711
s->rfbi.data[1] = value & 0x0f1f0f1f;
1713
case 0x74: /* RFBI_DATA_CYCLE3_0 */
1714
TRACERFBI("RFBI_DATA_CYCLE3_0 = 0x%08x", value);
1715
s->rfbi.data[2] = value & 0x0f1f0f1f;
1717
case 0x78: /* RFBI_CONFIG1 */
1718
TRACERFBI("RFBI_CONFIG1 = 0x%08x", value);
1719
s->rfbi.config[1] = value & 0x003f1fff;
1722
case 0x7c: /* RFBI_ONOFF_TIME1 */
1723
TRACERFBI("RFBI_ONOFF_TIME1 = 0x%08x", value);
1724
s->rfbi.time[2] = value & 0x3fffffff;
1726
case 0x80: /* RFBI_CYCLE_TIME1 */
1727
TRACERFBI("RFBI_CYCLE_TIME1 = 0x%08x", value);
1728
s->rfbi.time[3] = value & 0x0fffffff;
1730
case 0x84: /* RFBI_DATA_CYCLE1_1 */
1731
TRACERFBI("RFBI_DATA_CYCLE1_1 = 0x%08x", value);
1732
s->rfbi.data[3] = value & 0x0f1f0f1f;
1734
case 0x88: /* RFBI_DATA_CYCLE2_1 */
1735
TRACERFBI("RFBI_DATA_CYCLE2_1 = 0x%08x", value);
1736
s->rfbi.data[4] = value & 0x0f1f0f1f;
1738
case 0x8c: /* RFBI_DATA_CYCLE3_1 */
1739
TRACERFBI("RFBI_DATA_CYCLE3_1 = 0x%08x", value);
1740
s->rfbi.data[5] = value & 0x0f1f0f1f;
1743
case 0x90: /* RFBI_VSYNC_WIDTH */
1744
TRACERFBI("RFBI_VSYNC_WIDTH = 0x%08x", value);
1745
s->rfbi.vsync = value & 0xffff;
1747
case 0x94: /* RFBI_HSYNC_WIDTH */
1748
TRACERFBI("RFBI_HSYNC_WIDTH = 0x%08x", value);
1749
s->rfbi.hsync = value & 0xffff;
1753
OMAP_BAD_REGV(addr, value);
1758
static const MemoryRegionOps omap_rfbi_ops = {
1759
.read = omap_rfbi_read,
1760
.write = omap_rfbi_write,
1761
.endianness = DEVICE_NATIVE_ENDIAN,
1764
static uint64_t omap_venc_read(void *opaque, hwaddr addr,
1768
return omap_badwidth_read32(opaque, addr);
1772
case 0x00: /* REV_ID */
1774
case 0x04: /* STATUS */
1775
case 0x08: /* F_CONTROL */
1776
case 0x10: /* VIDOUT_CTRL */
1777
case 0x14: /* SYNC_CTRL */
1778
case 0x1c: /* LLEN */
1779
case 0x20: /* FLENS */
1780
case 0x24: /* HFLTR_CTRL */
1781
case 0x28: /* CC_CARR_WSS_CARR */
1782
case 0x2c: /* C_PHASE */
1783
case 0x30: /* GAIN_U */
1784
case 0x34: /* GAIN_V */
1785
case 0x38: /* GAIN_Y */
1786
case 0x3c: /* BLACK_LEVEL */
1787
case 0x40: /* BLANK_LEVEL */
1788
case 0x44: /* X_COLOR */
1789
case 0x48: /* M_CONTROL */
1790
case 0x4c: /* BSTAMP_WSS_DATA */
1791
case 0x50: /* S_CARR */
1792
case 0x54: /* LINE21 */
1793
case 0x58: /* LN_SEL */
1794
case 0x5c: /* L21__WC_CTL */
1795
case 0x60: /* HTRIGGER_VTRIGGER */
1796
case 0x64: /* SAVID__EAVID */
1797
case 0x68: /* FLEN__FAL */
1798
case 0x6c: /* LAL__PHASE_RESET */
1799
case 0x70: /* HS_INT_START_STOP_X */
1800
case 0x74: /* HS_EXT_START_STOP_X */
1801
case 0x78: /* VS_INT_START_X */
1802
case 0x7c: /* VS_INT_STOP_X__VS_INT_START_Y */
1803
case 0x80: /* VS_INT_STOP_Y__VS_INT_START_X */
1804
case 0x84: /* VS_EXT_STOP_X__VS_EXT_START_Y */
1805
case 0x88: /* VS_EXT_STOP_Y */
1806
case 0x90: /* AVID_START_STOP_X */
1807
case 0x94: /* AVID_START_STOP_Y */
1808
case 0xa0: /* FID_INT_START_X__FID_INT_START_Y */
1809
case 0xa4: /* FID_INT_OFFSET_Y__FID_EXT_START_X */
1810
case 0xa8: /* FID_EXT_START_Y__FID_EXT_OFFSET_Y */
1811
case 0xb0: /* TVDETGP_INT_START_STOP_X */
1812
case 0xb4: /* TVDETGP_INT_START_STOP_Y */
1813
case 0xb8: /* GEN_CTRL */
1814
case 0xc4: /* DAC_TST__DAC_A */
1815
case 0xc8: /* DAC_B__DAC_C */
1824
static void omap_venc_write(void *opaque, hwaddr addr,
1825
uint64_t value, unsigned size)
1828
return omap_badwidth_write32(opaque, addr, size);
1832
case 0x00: /* REV_ID */
1833
case 0x04: /* STATUS */
1834
/* read-only, ignore */
1836
case 0x08: /* F_CONTROL */
1837
case 0x10: /* VIDOUT_CTRL */
1838
case 0x14: /* SYNC_CTRL */
1839
case 0x1c: /* LLEN */
1840
case 0x20: /* FLENS */
1841
case 0x24: /* HFLTR_CTRL */
1842
case 0x28: /* CC_CARR_WSS_CARR */
1843
case 0x2c: /* C_PHASE */
1844
case 0x30: /* GAIN_U */
1845
case 0x34: /* GAIN_V */
1846
case 0x38: /* GAIN_Y */
1847
case 0x3c: /* BLACK_LEVEL */
1848
case 0x40: /* BLANK_LEVEL */
1849
case 0x44: /* X_COLOR */
1850
case 0x48: /* M_CONTROL */
1851
case 0x4c: /* BSTAMP_WSS_DATA */
1852
case 0x50: /* S_CARR */
1853
case 0x54: /* LINE21 */
1854
case 0x58: /* LN_SEL */
1855
case 0x5c: /* L21__WC_CTL */
1856
case 0x60: /* HTRIGGER_VTRIGGER */
1857
case 0x64: /* SAVID__EAVID */
1858
case 0x68: /* FLEN__FAL */
1859
case 0x6c: /* LAL__PHASE_RESET */
1860
case 0x70: /* HS_INT_START_STOP_X */
1861
case 0x74: /* HS_EXT_START_STOP_X */
1862
case 0x78: /* VS_INT_START_X */
1863
case 0x7c: /* VS_INT_STOP_X__VS_INT_START_Y */
1864
case 0x80: /* VS_INT_STOP_Y__VS_INT_START_X */
1865
case 0x84: /* VS_EXT_STOP_X__VS_EXT_START_Y */
1866
case 0x88: /* VS_EXT_STOP_Y */
1867
case 0x90: /* AVID_START_STOP_X */
1868
case 0x94: /* AVID_START_STOP_Y */
1869
case 0xa0: /* FID_INT_START_X__FID_INT_START_Y */
1870
case 0xa4: /* FID_INT_OFFSET_Y__FID_EXT_START_X */
1871
case 0xa8: /* FID_EXT_START_Y__FID_EXT_OFFSET_Y */
1872
case 0xb0: /* TVDETGP_INT_START_STOP_X */
1873
case 0xb4: /* TVDETGP_INT_START_STOP_Y */
1874
case 0xb8: /* GEN_CTRL */
1875
case 0xc4: /* DAC_TST__DAC_A */
1876
case 0xc8: /* DAC_B__DAC_C */
1879
OMAP_BAD_REGV(addr, value);
1884
static const MemoryRegionOps omap_venc_ops = {
1885
.read = omap_venc_read,
1886
.write = omap_venc_write,
1887
.endianness = DEVICE_NATIVE_ENDIAN,
1890
static uint64_t omap_im3_read(void *opaque, hwaddr addr,
1894
return omap_badwidth_read32(opaque, addr);
1898
case 0x0a8: /* SBIMERRLOGA */
1899
case 0x0b0: /* SBIMERRLOG */
1900
case 0x190: /* SBIMSTATE */
1901
case 0x198: /* SBTMSTATE_L */
1902
case 0x19c: /* SBTMSTATE_H */
1903
case 0x1a8: /* SBIMCONFIG_L */
1904
case 0x1ac: /* SBIMCONFIG_H */
1905
case 0x1f8: /* SBID_L */
1906
case 0x1fc: /* SBID_H */
1916
static void omap_im3_write(void *opaque, hwaddr addr,
1917
uint64_t value, unsigned size)
1920
return omap_badwidth_write32(opaque, addr, value);
1924
case 0x0b0: /* SBIMERRLOG */
1925
case 0x190: /* SBIMSTATE */
1926
case 0x198: /* SBTMSTATE_L */
1927
case 0x19c: /* SBTMSTATE_H */
1928
case 0x1a8: /* SBIMCONFIG_L */
1929
case 0x1ac: /* SBIMCONFIG_H */
1933
OMAP_BAD_REGV(addr, value);
1938
static const MemoryRegionOps omap_im3_ops = {
1939
.read = omap_im3_read,
1940
.write = omap_im3_write,
1941
.endianness = DEVICE_NATIVE_ENDIAN,
1944
static void omap_dsi_push_rx_fifo(struct omap_dss_s *s, int ch, uint32_t value)
1948
if (s->dsi.vc[ch].rx_fifo_len < OMAP_DSI_RX_FIFO_SIZE) {
1949
p = s->dsi.vc[ch].rx_fifo_pos + s->dsi.vc[ch].rx_fifo_len;
1950
if (p >= OMAP_DSI_RX_FIFO_SIZE)
1951
p -= OMAP_DSI_RX_FIFO_SIZE;
1952
s->dsi.vc[ch].rx_fifo[p] = value;
1953
s->dsi.vc[ch].rx_fifo_len++;
1955
TRACEDSI("vc%d rx fifo overflow!", ch);
1959
static uint32_t omap_dsi_pull_rx_fifo(struct omap_dss_s *s, int ch)
1963
if (!s->dsi.vc[ch].rx_fifo_len) {
1964
TRACEDSI("vc%d rx fifo underflow!", ch);
1966
v = s->dsi.vc[ch].rx_fifo[s->dsi.vc[ch].rx_fifo_pos++];
1967
s->dsi.vc[ch].rx_fifo_len--;
1968
if (s->dsi.vc[ch].rx_fifo_pos >= OMAP_DSI_RX_FIFO_SIZE)
1969
s->dsi.vc[ch].rx_fifo_pos = 0;
1975
static uint32_t omap_dsi_read(void *opaque, hwaddr addr)
1977
struct omap_dss_s *s = (struct omap_dss_s *)opaque;
1981
case 0x000: /* DSI_REVISION */
1982
TRACEDSI("DSI_REVISION = 0x10");
1984
case 0x010: /* DSI_SYSCONFIG */
1985
TRACEDSI("DSI_SYSCONFIG = 0x%04x", s->dsi.sysconfig);
1986
return s->dsi.sysconfig;
1987
case 0x014: /* DSI_SYSSTATUS */
1988
TRACEDSI("DSI_SYSSTATUS = 0x01");
1989
return 1; /* RESET_DONE */
1990
case 0x018: /* DSI_IRQSTATUS */
1991
TRACEDSI("DSI_IRQSTATUS = 0x%08x", s->dsi.irqst);
1992
return s->dsi.irqst;
1993
case 0x01c: /* DSI_IRQENABLE */
1994
TRACEDSI("DSI_IRQENABLE = 0x%08x", s->dsi.irqen);
1995
return s->dsi.irqen;
1996
case 0x040: /* DSI_CTRL */
1997
TRACEDSI("DSI_CTRL = 0x%08x", s->dsi.ctrl);
1999
case 0x048: /* DSI_COMPLEXIO_CFG1 */
2000
TRACEDSI("DSI_COMPLEXIO_CFG1 = 0x%08x", s->dsi.complexio_cfg1);
2001
return s->dsi.complexio_cfg1;
2002
case 0x04c: /* DSI_COMPLEXIO_IRQSTATUS */
2003
TRACEDSI("DSI_COMPLEXIO_IRQSTATUS = 0x%08x", s->dsi.complexio_irqst);
2004
return s->dsi.complexio_irqst;
2005
case 0x050: /* DSI_COMPLEXIO_IRQENABLE */
2006
TRACEDSI("DSI_COMPLEXIO_IRQENABLE = 0x%08x", s->dsi.complexio_irqen);
2007
return s->dsi.complexio_irqen;
2008
case 0x054: /* DSI_CLK_CTRL */
2009
TRACEDSI("DSI_CLK_CTRL = 0x%08x", s->dsi.clk_ctrl);
2010
return s->dsi.clk_ctrl;
2011
case 0x058: /* DSI_TIMING1 */
2012
TRACEDSI("DSI_TIMING1 = 0x%08x", s->dsi.timing1);
2013
return s->dsi.timing1;
2014
case 0x05c: /* DSI_TIMING2 */
2015
TRACEDSI("DSI_TIMING2 = 0x%08x", s->dsi.timing2);
2016
return s->dsi.timing2;
2017
case 0x060: /* DSI_VM_TIMING1 */
2018
TRACEDSI("DSI_VM_TIMING1 = 0x%08x", s->dsi.vm_timing1);
2019
return s->dsi.vm_timing1;
2020
case 0x064: /* DSI_VM_TIMING2 */
2021
TRACEDSI("DSI_VM_TIMING2 = 0x%08x", s->dsi.vm_timing2);
2022
return s->dsi.vm_timing2;
2023
case 0x068: /* DSI_VM_TIMING3 */
2024
TRACEDSI("DSI_VM_TIMING3 = 0x%08x", s->dsi.vm_timing3);
2025
return s->dsi.vm_timing3;
2026
case 0x06c: /* DSI_CLK_TIMING */
2027
TRACEDSI("DSI_CLK_TIMING = 0x%08x", s->dsi.clk_timing);
2028
return s->dsi.clk_timing;
2029
case 0x070: /* DSI_TX_FIFO_VC_SIZE */
2030
TRACEDSI("DSI_TX_FIFO_VC_SIZE = 0x%08x", s->dsi.tx_fifo_vc_size);
2031
return s->dsi.tx_fifo_vc_size;
2032
case 0x074: /* DSI_RX_FIFO_VC_SIZE */
2033
TRACEDSI("DSI_RX_FIFO_VC_SIZE = 0x%08x", s->dsi.rx_fifo_vc_size);
2034
return s->dsi.rx_fifo_vc_size;
2035
case 0x078: /* DSI_COMPLEXIO_CFG_2 */
2036
TRACEDSI("DSI_COMPLEXIO_CFG_2 = 0x%08x", s->dsi.complexio_cfg2);
2037
return s->dsi.complexio_cfg2;
2038
case 0x07c: /* DSI_RX_FIFO_VC_FULLNESS */
2039
TRACEDSI("DSI_RX_FIFO_VC_FULLNESS = 0x00");
2041
case 0x080: /* DSI_VM_TIMING4 */
2042
TRACEDSI("DSI_VM_TIMING4 = 0x%08x", s->dsi.vm_timing4);
2043
return s->dsi.vm_timing4;
2044
case 0x084: /* DSI_TX_FIFO_VC_EMPTINESS */
2045
TRACEDSI("DSI_TX_FIFO_VC_EMPTINESS = 0x7f7f7f7f");
2047
case 0x088: /* DSI_VM_TIMING5 */
2048
TRACEDSI("DSI_VM_TIMING5 = 0x%08x", s->dsi.vm_timing5);
2049
return s->dsi.vm_timing5;
2050
case 0x08c: /* DSI_VM_TIMING6 */
2051
TRACEDSI("DSI_VM_TIMING6 = 0x%08x", s->dsi.vm_timing6);
2052
return s->dsi.vm_timing6;
2053
case 0x090: /* DSI_VM_TIMING7 */
2054
TRACEDSI("DSI_VM_TIMING7 = 0x%08x", s->dsi.vm_timing7);
2055
return s->dsi.vm_timing7;
2056
case 0x094: /* DSI_STOPCLK_TIMING */
2057
TRACEDSI("DSI_STOPCLK_TIMING = 0x%08x", s->dsi.stopclk_timing);
2058
return s->dsi.stopclk_timing;
2059
case 0x100 ... 0x17c: /* DSI_VCx_xxx */
2060
x = (addr >> 5) & 3;
2061
switch (addr & 0x1f) {
2062
case 0x00: /* DSI_VCx_CTRL */
2063
TRACEDSI("DSI_VC%d_CTRL = 0x%08x", x, s->dsi.vc[x].ctrl);
2064
return s->dsi.vc[x].ctrl;
2065
case 0x04: /* DSI_VCx_TE */
2066
TRACEDSI("DSI_VC%d_TE = 0x%08x", x, s->dsi.vc[x].te);
2067
return s->dsi.vc[x].te;
2068
case 0x08: /* DSI_VCx_LONG_PACKET_HEADER */
2070
TRACEDSI("DSI_VC%d_LONG_PACKET_HEADER = 0", x);
2072
case 0x0c: /* DSI_VCx_LONG_PACKET_PAYLOAD */
2074
TRACEDSI("DSI_VC%d_LONG_PACKET_PAYLOAD = 0", x);
2076
case 0x10: /* DSI_VCx_SHORT_PACKET_HEADER */
2077
if (s->dsi.vc[x].ctrl & (1 << 20)) { /* RX_FIFO_NOT_EMPTY */
2078
y = omap_dsi_pull_rx_fifo(s, x);
2079
TRACEDSI("DSI_VC%d_SHORT_PACKET_HEADER = 0x%08x", x, y);
2080
if (!s->dsi.vc[x].rx_fifo_len)
2081
s->dsi.vc[x].ctrl &= ~(1 << 20); /* RX_FIFO_NOT_EMPTY */
2084
TRACEDSI("vc%d rx fifo underflow!", x);
2086
case 0x18: /* DSI_VCx_IRQSTATUS */
2087
TRACEDSI("DSI_VC%d_IRQSTATUS = 0x%08x", x, s->dsi.vc[x].irqst);
2088
return s->dsi.vc[x].irqst;
2089
case 0x1c: /* DSI_VCx_IRQENABLE */
2090
TRACEDSI("DSI_VC%d_IRQENABLE = 0x%08x", x, s->dsi.vc[x].irqen);
2091
return s->dsi.vc[x].irqen;
2096
case 0x200: /* DSI_PHY_CFG0 */
2097
TRACEDSI("DSI_PHY_CFG0 = 0x%08x", s->dsi.phy_cfg0);
2098
return s->dsi.phy_cfg0;
2099
case 0x204: /* DSI_PHY_CFG1 */
2100
TRACEDSI("DSI_PHY_CFG1 = 0x%08x", s->dsi.phy_cfg1);
2101
return s->dsi.phy_cfg1;
2102
case 0x208: /* DSI_PHY_CFG2 */
2103
TRACEDSI("DSI_PHY_CFG2 = 0x%08x", s->dsi.phy_cfg2);
2104
return s->dsi.phy_cfg2;
2105
case 0x214: /* DSI_PHY_CFG5 */
2106
TRACEDSI("DSI_PHY_CFG5 = 0xfc000000");
2107
return 0xfc000000; /* all resets done */
2108
case 0x300: /* DSI_PLL_CONTROL */
2109
TRACEDSI("DSI_PLL_CONTROL = 0x%08x", s->dsi.pll_control);
2110
return s->dsi.pll_control;
2111
case 0x304: /* DSI_PLL_STATUS */
2112
x = 1; /* DSI_PLLCTRL_RESET_DONE */
2113
if ((s->dsi.clk_ctrl >> 28) & 3) { /* DSI PLL control powered? */
2114
if (((s->dsi.pll_config1 >> 1) & 0x7f) && /* DSI_PLL_REGN */
2115
((s->dsi.pll_config1 >> 8) & 0x7ff)) { /* DSI_PLL_REGM */
2116
x |= 2; /* DSI_PLL_LOCK */
2119
if ((s->dsi.pll_config2 >> 20) & 1) /* DSI_HSDIVBYPASS */
2120
x |= (1 << 9); /* DSI_BYPASSACKZ */
2121
if ((s->dsi.pll_config2 >> 18) & 1) /* DSI_PROTO_CLOCK_EN */
2122
x |= (1 << 8); /* DSIPROTO_CLOCK_ACK */
2123
if ((s->dsi.pll_config2 >> 16) & 1) /* DSS_CLOCK_EN */
2124
x |= (1 << 7); /* DSS_CLOCK_ACK */
2125
if (!((s->dsi.pll_config2 >> 13) & 1)) /* DSI_PLL_REFEN */
2126
x |= (1 << 3); /* DSI_PLL_LOSSREF */
2127
TRACEDSI("DSI_PLL_STATUS = 0x%08x", x);
2129
case 0x308: /* DSI_PLL_GO */
2130
TRACEDSI("DSI_PLL_GO = 0x%08x", s->dsi.pll_go);
2131
return s->dsi.pll_go;
2132
case 0x30c: /* DSI_PLL_CONFIGURATION1 */
2133
TRACEDSI("DSI_PLL_CONFIGURATION1 = 0x%08x", s->dsi.pll_config1);
2134
return s->dsi.pll_config1;
2135
case 0x310: /* DSI_PLL_CONFIGURATION2 */
2136
TRACEDSI("DSI_PLL_CONFIGURATION2 = 0x%08x", s->dsi.pll_config2);
2137
return s->dsi.pll_config2;
2145
static void omap_dsi_txdone(struct omap_dss_s *s, int ch, int bta)
2148
s->dsi.vc[ch].irqst |= 0x20; /* BTA_IRQ */
2149
if (s->dsi.vc[ch].rx_fifo_len)
2150
s->dsi.vc[ch].ctrl |= 1 << 20; /* RX_FIFO_NOT_EMPTY */
2152
s->dsi.vc[ch].irqst |= 0x04; /* PACKET_SENT_IRQ */
2154
s->dsi.irqst |= 1 << ch; /* VIRTUAL_CHANNELx_IRQ */
2155
omap_dss_interrupt_update(s);
2158
static void omap_dsi_short_write(struct omap_dss_s *s, int ch)
2160
uint32_t data = s->dsi.vc[ch].sp_header;
2162
if (((data >> 6) & 0x03) != ch) {
2163
TRACEDSI("error - vc%d != %d", ch, (data >> 6) & 0x03);
2165
data = dsi_short_write(s->dsi.host, data);
2166
/* responses cannot be all-zero so it is safe to use that
2167
* as a no-reply value */
2169
omap_dsi_push_rx_fifo(s, ch, data);
2171
omap_dsi_txdone(s, ch, (s->dsi.vc[ch].ctrl & 0x04)); /* BTA_SHORT_EN */
2175
static void omap_dsi_long_write(struct omap_dss_s *s, int ch)
2177
uint32_t hdr = s->dsi.vc[ch].lp_header;
2179
/* TODO: implement packet footer sending (16bit checksum).
2180
* Currently none is sent and receiver is supposed to not expect one */
2181
if (((hdr >> 6) & 0x03) != ch) {
2182
TRACEDSI("error - vc%d != %d", ch, (hdr >> 6) & 0x03);
2184
dsi_long_write(s->dsi.host, hdr, s->dsi.vc[ch].lp_payload,
2185
s->dsi.vc[ch].lp_counter);
2186
if ((s->dsi.vc[ch].te >> 30) & 3) { /* TE_START | TE_EN */
2187
/* TODO: do we really need to implement something for this?
2188
* Should writes decrease the TE_SIZE counter, for example?
2189
* For now, the TE transfers are completed immediately */
2191
if (s->dsi.vc[ch].lp_counter > 0)
2192
s->dsi.vc[ch].lp_counter -= 4;
2193
if (s->dsi.vc[ch].lp_counter <= 0)
2194
omap_dsi_txdone(s, ch, (s->dsi.vc[ch].ctrl & 0x08)); /* BTA_LONG_EN */
2199
static void omap_dsi_write(void *opaque, hwaddr addr,
2202
struct omap_dss_s *s = (struct omap_dss_s *)opaque;
2206
case 0x000: /* DSI_REVISION */
2207
case 0x014: /* DSI_SYSSTATUS */
2208
case 0x07c: /* DSI_RX_FIFO_VC_FULLNESS */
2209
case 0x084: /* DSI_RX_FIFO_VC_EMPTINESS */
2210
case 0x214: /* DSI_PHY_CFG5 */
2211
case 0x304: /* DSI_PLL_STATUS */
2212
/* read-only, ignore */
2214
case 0x010: /* DSI_SYSCONFIG */
2215
TRACEDSI("DSI_SYSCONFIG = 0x%08x", value);
2216
if (value & 2) /* SOFT_RESET */
2219
s->dsi.sysconfig = value;
2221
case 0x018: /* DSI_IRQSTATUS */
2222
TRACEDSI("DSI_IRQSTATUS = 0x%08x", value);
2223
s->dsi.irqst &= ~(value & 0x1fc3b0);
2224
omap_dss_interrupt_update(s);
2226
case 0x01c: /* DSI_IRQENABLE */
2227
TRACEDSI("DSI_IRQENABLE = 0x%08x", value);
2228
s->dsi.irqen = value & 0x1fc3b0;
2229
omap_dss_interrupt_update(s);
2231
case 0x040: /* DSI_CTRL */
2232
TRACEDSI("DSI_CTRL = 0x%08x", value);
2233
s->dsi.ctrl = value & 0x7ffffff;
2235
case 0x048: /* DSI_COMPLEXIO_CFG_1 */
2236
TRACEDSI("DSI_COMPLEXIO_CFG1 = 0x%08x", value);
2237
value |= 1 << 29; /* RESET_DONE */
2238
value |= 1 << 21; /* LDO_POWER_GOOD_STATE */
2239
value &= ~(1 << 30); /* GOBIT */
2240
/* copy PWR_CMD directly to PWR_STATUS */
2241
value &= ~(3 << 25);
2242
value |= (value >> 2) & (3 << 25);
2243
/* TODO: notify screen refresh control about PWR_STATUS */
2244
s->dsi.complexio_cfg1 = value;
2246
case 0x04c: /* DSI_COMPLEXIO_IRQSTATUS */
2247
TRACEDSI("DSI_COMPLEXIO_IRQSTATUS = 0x%08x", value);
2248
s->dsi.complexio_irqst &= ~(value & 0xc3f39ce7);
2249
if (s->dsi.complexio_irqst & s->dsi.complexio_irqen)
2250
s->dsi.irqst |= (1 << 10); /* COMPLEXIO_ERR_IRQ */
2252
s->dsi.irqst &= ~(1 << 10); /* COMPLEXIO_ERR_IRQ */
2253
omap_dss_interrupt_update(s);
2255
case 0x050: /* DSI_COMPLEXIO_IRQENABLE */
2256
TRACEDSI("DSI_COMPLEXIO_IRQENABLE = 0x%08x", value);
2257
s->dsi.complexio_irqen = value & 0xc3f39ce7;
2258
omap_dss_interrupt_update(s);
2260
case 0x054: /* DSI_CLK_CTRL */
2261
TRACEDSI("DSI_CLK_CTRL = 0x%08x", value);
2262
value &= 0xc03fffff;
2263
/* copy PLL_PWR_CMD directly to PLL_PWR_STATUS */
2264
value |= (value >> 2) & (3 << 28);
2265
s->dsi.clk_ctrl = value;
2267
case 0x058: /* DSI_TIMING1 */
2268
TRACEDSI("DSI_TIMING1 = 0x%08x", value);
2269
value &= ~(1 << 15); /* deassert ForceTxStopMode signal */
2270
s->dsi.timing1 = value;
2272
case 0x05c: /* DSI_TIMING2 */
2273
TRACEDSI("DSI_TIMING2 = 0x%08x", value);
2274
s->dsi.timing2 = value;
2276
case 0x060: /* DSI_VM_TIMING1 */
2277
TRACEDSI("DSI_VM_TIMING1 = 0x%08x", value);
2278
s->dsi.vm_timing1 = value;
2280
case 0x064: /* DSI_VM_TIMING2 */
2281
TRACEDSI("DSI_VM_TIMING2 = 0x%08x", value);
2282
s->dsi.vm_timing2 = value & 0x0fffffff;
2284
case 0x068: /* DSI_VM_TIMING3 */
2285
TRACEDSI("DSI_VM_TIMING3 = 0x%08x", value);
2286
s->dsi.vm_timing3 = value;
2288
case 0x06c: /* DSI_CLK_TIMING */
2289
TRACEDSI("DSI_CLK_TIMING = 0x%08x", value);
2290
s->dsi.clk_timing = value & 0xffff;
2292
case 0x070: /* DSI_TX_FIFO_VC_SIZE */
2293
TRACEDSI("DSI_TX_FIFO_VC_SIZE = 0x%08x", value);
2294
s->dsi.tx_fifo_vc_size = value & 0xf7f7f7f7;
2296
case 0x074: /* DSI_RX_FIFO_VC_SIZE */
2297
TRACEDSI("DSI_RX_FIFO_VC_SIZE = 0x%08x", value);
2298
s->dsi.rx_fifo_vc_size = value & 0xf7f7f7f7;
2300
case 0x078: /* DSI_COMPLEXIO_CFG_2 */
2301
TRACEDSI("DSI_COMPLEXIO_CFG_2 = 0x%08x", value);
2302
s->dsi.complexio_cfg2 = (value & 0xfffcffff)
2303
| (s->dsi.complexio_cfg2 & (3 << 16));
2305
case 0x080: /* DSI_VM_TIMING4 */
2306
TRACEDSI("DSI_VM_TIMING4 = 0x%08x", value);
2307
s->dsi.vm_timing4 = value;
2309
case 0x088: /* DSI_VM_TIMING5 */
2310
TRACEDSI("DSI_VM_TIMING5 = 0x%08x", value);
2311
s->dsi.vm_timing5 = value;
2313
case 0x08c: /* DSI_VM_TIMING6 */
2314
TRACEDSI("DSI_VM_TIMING6 = 0x%08x", value);
2315
s->dsi.vm_timing6 = value;
2317
case 0x090: /* DSI_VM_TIMING7 */
2318
TRACEDSI("DSI_VM_TIMING7 = 0x%08x", value);
2319
s->dsi.vm_timing7 = value;
2321
case 0x094: /* DSI_STOPCLK_TIMING */
2322
TRACEDSI("DSI_STOPCLK_TIMING = 0x%08x", value);
2323
s->dsi.stopclk_timing = value & 0xff;
2325
case 0x100 ... 0x17c: /* DSI_VCx_xxx */
2326
x = (addr >> 5) & 3;
2327
switch (addr & 0x1f) {
2328
case 0x00: /* DSI_VCx_CTRL */
2329
TRACEDSI("DSI_VC%d_CTRL = 0x%08x", x, value);
2330
if (((value >> 27) & 7) != 4) /* DMA_RX_REQ_NB */
2331
hw_error("%s: RX DMA mode not implemented", __FUNCTION__);
2332
if (((value >> 21) & 7) != 4) /* DMA_TX_REQ_NB */
2333
hw_error("%s: TX DMA mode not implemented", __FUNCTION__);
2334
if (value & 1) { /* VC_EN */
2335
s->dsi.vc[x].ctrl &= ~0x40; /* BTA_EN */
2336
s->dsi.vc[x].ctrl |= 0x8001; /* VC_BUSY | VC_EN */
2338
/* clear VC_BUSY and VC_EN, assign writable bits */
2339
s->dsi.vc[x].ctrl = (s->dsi.vc[x].ctrl & 0x114020) |
2340
(value & 0x3fee039f);
2342
if (value & 0x40) /* BTA_EN */
2343
omap_dsi_txdone(s, x, 1);
2345
case 0x04: /* DSI_VCx_TE */
2346
TRACEDSI("DSI_VC%d_TE = 0x%08x", x, value);
2347
value &= 0xc0ffffff;
2348
/* according to the OMAP3 TRM the TE_EN bit in this
2349
* register is protected by VCx_CTRL VC_EN bit but
2350
* let's forget that */
2351
s->dsi.vc[x].te = value;
2352
if (s->dispc.control & 1) /* LCDENABLE */
2353
omap_dsi_transfer_start(s, x);
2355
case 0x08: /* DSI_VCx_LONG_PACKET_HEADER */
2356
TRACEDSI("DSI_VC%d_LONG_PACKET_HEADER id=0x%02x, len=0x%04x, ecc=0x%02x",
2357
x, value & 0xff, (value >> 8) & 0xffff, (value >> 24) & 0xff);
2358
s->dsi.vc[x].lp_header = value;
2359
s->dsi.vc[x].lp_counter = (value >> 8) & 0xffff;
2361
case 0x0c: /* DSI_VCx_LONG_PACKET_PAYLOAD */
2362
TRACEDSI("DSI_VC%d_LONG_PACKET_PAYLOAD = 0x%08x", x, value);
2363
s->dsi.vc[x].lp_payload = value;
2364
if ((s->dsi.vc[x].te >> 30) & 3) { /* TE_START | TE_EN */
2365
int tx_dma = (s->dsi.vc[x].ctrl >> 21) & 7; /* DMA_TX_REQ_NB */
2367
qemu_irq_lower(s->dsi.drq[tx_dma]);
2369
omap_dsi_long_write(s, x);
2371
case 0x10: /* DSI_VCx_SHORT_PACKET_HEADER */
2372
TRACEDSI("DSI_VC%d_SHORT_PACKET_HEADER = 0x%08x", x, value);
2373
s->dsi.vc[x].sp_header = value;
2374
omap_dsi_short_write(s, x);
2376
case 0x18: /* DSI_VCx_IRQSTATUS */
2377
TRACEDSI("DSI_VC%d_IRQSTATUS = 0x%08x", x, value);
2378
s->dsi.vc[x].irqst &= ~(value & 0x1ff);
2379
if (s->dsi.vc[x].irqst & s->dsi.vc[x].irqen)
2380
s->dsi.irqst |= 1 << x; /* VIRTUAL_CHANNELx_IRQ */
2382
s->dsi.irqst &= ~(1 << x); /* VIRTUAL_CHANNELx_IRQ */
2383
omap_dss_interrupt_update(s);
2385
case 0x1c: /* DSI_VCx_IRQENABLE */
2386
TRACEDSI("DSI_VC%d_IRQENABLE = 0x%08x", x, value);
2387
s->dsi.vc[x].irqen = value & 0x1ff;
2388
omap_dss_interrupt_update(s);
2391
OMAP_BAD_REGV(addr, value);
2395
case 0x200: /* DSI_PHY_CFG0 */
2396
TRACEDSI("DSI_PHY_CFG0 = 0x%08x", value);
2397
s->dsi.phy_cfg0 = value;
2399
case 0x204: /* DSI_PHY_CFG1 */
2400
TRACEDSI("DSI_PHY_CFG1 = 0x%08x", value);
2401
s->dsi.phy_cfg1 = value;
2403
case 0x208: /* DSI_PHY_CFG2 */
2404
TRACEDSI("DSI_PHY_CFG2 = 0x%08x", value);
2405
if (s->mpu_model >= omap3630) {
2406
value &= 0xff0000ff;
2408
s->dsi.phy_cfg2 = value;
2410
case 0x300: /* DSI_PLL_CONTROL */
2411
TRACEDSI("DSI_PLL_CONTROL = 0x%08x", value);
2412
s->dsi.pll_control = value & 0x1f;
2414
case 0x308: /* DSI_PLL_GO */
2415
TRACEDSI("DSI_PLL_GO = 0x%08x", value);
2416
/* TODO: check if we need to update something here */
2417
value &= ~1; /* mark it done */
2418
s->dsi.pll_go = value & 1;
2420
case 0x30c: /* DSI_PLL_CONFIGURATION1 */
2421
TRACEDSI("DSI_PLL_CONFIGURATION1 = 0x%08x", value);
2422
s->dsi.pll_config1 = value & 0x7ffffff;
2424
case 0x310: /* DSI_PLL_CONFIGURATION2 */
2425
TRACEDSI("DSI_PLL_CONFIGURATION2 = 0x%08x", value);
2426
if (s->mpu_model < omap3630) {
2431
s->dsi.pll_config2 = value;
2434
OMAP_BAD_REGV(addr, value);
2439
static const MemoryRegionOps omap_dsi_ops = {
2442
omap_badwidth_read32,
2443
omap_badwidth_read32,
2447
omap_badwidth_write32,
2448
omap_badwidth_write32,
2452
.endianness = DEVICE_NATIVE_ENDIAN,
2455
static int omap_dss_init(SysBusDevice *dev)
2457
struct omap_dss_s *s = FROM_SYSBUS(struct omap_dss_s, dev);
2458
sysbus_init_irq(dev, &s->irq);
2459
sysbus_init_irq(dev, &s->drq); /* linetrigger */
2461
memory_region_init_io(&s->iomem_diss1, &omap_diss_ops, s,
2462
"omap.diss1", 0x400);
2463
memory_region_init_io(&s->iomem_disc1, &omap_disc_ops, s,
2464
"omap.disc1", 0x400);
2465
memory_region_init_io(&s->iomem_rfbi1, &omap_rfbi_ops, s,
2466
"omap.rfbi1", 0x400);
2467
memory_region_init_io(&s->iomem_venc1, &omap_venc_ops, s,
2468
"omap.venc1", 0x400);
2469
sysbus_init_mmio(dev, &s->iomem_diss1);
2470
sysbus_init_mmio(dev, &s->iomem_disc1);
2471
sysbus_init_mmio(dev, &s->iomem_rfbi1);
2472
sysbus_init_mmio(dev, &s->iomem_venc1);
2474
if (s->mpu_model < omap2410) {
2475
hw_error("%s: unsupported cpu type\n", __FUNCTION__);
2476
} else if (s->mpu_model < omap3430) {
2477
s->dispc.rev = 0x20;
2478
memory_region_init_io(&s->iomem_im3, &omap_im3_ops, s,
2479
"omap.im3", 0x1000);
2480
sysbus_init_mmio(dev, &s->iomem_im3);
2482
s->dispc.rev = 0x30;
2483
s->dispc.lcdframer = qemu_new_timer_ns(vm_clock, omap_dss_framedone, s);
2484
s->dsi.host = dsi_init_host(&dev->qdev, "omap3_dsi",
2485
omap_dsi_te_trigger,
2487
memory_region_init_io(&s->iomem_dsi, &omap_dsi_ops, s,
2489
sysbus_init_mmio(dev, &s->iomem_dsi);
2490
sysbus_init_irq(dev, &s->dsi.drq[0]);
2491
sysbus_init_irq(dev, &s->dsi.drq[1]);
2492
sysbus_init_irq(dev, &s->dsi.drq[2]);
2493
sysbus_init_irq(dev, &s->dsi.drq[3]);
2498
static Property omap_dss_properties[] = {
2499
DEFINE_PROP_INT32("mpu_model", struct omap_dss_s, mpu_model, 0),
2500
DEFINE_PROP_END_OF_LIST()
2503
static void omap_dss_class_init(ObjectClass *klass, void *data)
2505
DeviceClass *dc = DEVICE_CLASS(klass);
2506
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
2507
k->init = omap_dss_init;
2508
dc->reset = omap_dss_reset;
2509
dc->props = omap_dss_properties;
2512
static TypeInfo omap_dss_info = {
2514
.parent = TYPE_SYS_BUS_DEVICE,
2515
.instance_size = sizeof(struct omap_dss_s),
2516
.class_init = omap_dss_class_init,
2519
static void omap_dss_register_types(void)
2521
type_register_static(&omap_dss_info);
2524
void omap_rfbi_attach(DeviceState *dev, int cs,
2525
const struct rfbi_chip_s *chip)
2527
struct omap_dss_s *s = FROM_SYSBUS(struct omap_dss_s,
2528
SYS_BUS_DEVICE(dev));
2529
if (cs < 0 || cs > 1) {
2530
hw_error("%s: wrong CS %i\n", __FUNCTION__, cs);
2532
if (s->rfbi.chip[cs]) {
2533
TRACERFBI("warning - replacing previously attached "
2534
"RFBI chip on CS%d", cs);
2536
s->rfbi.chip[cs] = chip;
2539
DSIHost *omap_dsi_host(DeviceState *dev)
2541
return FROM_SYSBUS(struct omap_dss_s,
2542
SYS_BUS_DEVICE(dev))->dsi.host;
2545
void omap_lcd_panel_attach(DeviceState *dev)
2547
struct omap_dss_s *s = FROM_SYSBUS(struct omap_dss_s,
2548
SYS_BUS_DEVICE(dev));
2549
if (!s->lcd.attached) {
2550
s->lcd.attached = 1;
2551
s->lcd.invalidate = 1;
2552
s->lcd.ds = graphic_console_init(omap_lcd_panel_update_display,
2553
omap_lcd_panel_invalidate_display,
2558
void omap_digital_panel_attach(DeviceState *dev)
2560
struct omap_dss_s *s = FROM_SYSBUS(struct omap_dss_s,
2561
SYS_BUS_DEVICE(dev));
2562
if (!s->dig.attached) {
2563
s->dig.attached = 1;
2564
s->dig.invalidate = 1;
2565
s->dig.ds = graphic_console_init(omap_dig_panel_update_display,
2566
omap_dig_panel_invalidate_display,
2571
type_init(omap_dss_register_types)