1
//===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3
// The LLVM Compiler Infrastructure
5
// This file is distributed under the University of Illinois Open Source
6
// License. See LICENSE.TXT for details.
8
//===----------------------------------------------------------------------===//
10
// This file implements integer type expansion and promotion for LegalizeTypes.
11
// Promotion is the act of changing a computation in an illegal type into a
12
// computation in a larger type. For example, implementing i8 arithmetic in an
13
// i32 register (often needed on powerpc).
14
// Expansion is the act of changing a computation in an illegal type into a
15
// computation in two identical registers of a smaller type. For example,
16
// implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19
//===----------------------------------------------------------------------===//
21
#include "LegalizeTypes.h"
22
#include "llvm/CodeGen/PseudoSourceValue.h"
23
#include "llvm/Support/ErrorHandling.h"
24
#include "llvm/Support/raw_ostream.h"
27
//===----------------------------------------------------------------------===//
28
// Integer Result Promotion
29
//===----------------------------------------------------------------------===//
31
/// PromoteIntegerResult - This method is called when a result of a node is
32
/// found to be in need of promotion to a larger type. At this point, the node
33
/// may also have invalid operands or may have other results that need
34
/// expansion, we just know that (at least) one result needs promotion.
35
void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
36
DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG); dbgs() << "\n");
37
SDValue Res = SDValue();
39
// See if the target wants to custom expand this node.
40
if (CustomLowerNode(N, N->getValueType(ResNo), true))
43
switch (N->getOpcode()) {
46
dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
47
N->dump(&DAG); dbgs() << "\n";
49
llvm_unreachable("Do not know how to promote this operator!");
50
case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
51
case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
52
case ISD::BIT_CONVERT: Res = PromoteIntRes_BIT_CONVERT(N); break;
53
case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
54
case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
55
case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
56
case ISD::CONVERT_RNDSAT:
57
Res = PromoteIntRes_CONVERT_RNDSAT(N); break;
58
case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
59
case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
60
case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
61
case ISD::EXTRACT_VECTOR_ELT:
62
Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
63
case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
64
case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
65
case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
66
case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
67
case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
68
case ISD::SIGN_EXTEND_INREG:
69
Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
70
case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
71
case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
72
case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
73
case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
74
case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
76
case ISD::SIGN_EXTEND:
77
case ISD::ZERO_EXTEND:
78
case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
81
case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
88
case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
91
case ISD::SREM: Res = PromoteIntRes_SDIV(N); break;
94
case ISD::UREM: Res = PromoteIntRes_UDIV(N); break;
97
case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
99
case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
101
case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
103
case ISD::ATOMIC_LOAD_ADD:
104
case ISD::ATOMIC_LOAD_SUB:
105
case ISD::ATOMIC_LOAD_AND:
106
case ISD::ATOMIC_LOAD_OR:
107
case ISD::ATOMIC_LOAD_XOR:
108
case ISD::ATOMIC_LOAD_NAND:
109
case ISD::ATOMIC_LOAD_MIN:
110
case ISD::ATOMIC_LOAD_MAX:
111
case ISD::ATOMIC_LOAD_UMIN:
112
case ISD::ATOMIC_LOAD_UMAX:
113
case ISD::ATOMIC_SWAP:
114
Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
116
case ISD::ATOMIC_CMP_SWAP:
117
Res = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break;
120
// If the result is null then the sub-method took care of registering it.
122
SetPromotedInteger(SDValue(N, ResNo), Res);
125
SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
126
// Sign-extend the new bits, and continue the assertion.
127
SDValue Op = SExtPromotedInteger(N->getOperand(0));
128
return DAG.getNode(ISD::AssertSext, N->getDebugLoc(),
129
Op.getValueType(), Op, N->getOperand(1));
132
SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
133
// Zero the new bits, and continue the assertion.
134
SDValue Op = ZExtPromotedInteger(N->getOperand(0));
135
return DAG.getNode(ISD::AssertZext, N->getDebugLoc(),
136
Op.getValueType(), Op, N->getOperand(1));
139
SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
140
SDValue Op2 = GetPromotedInteger(N->getOperand(2));
141
SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
143
N->getChain(), N->getBasePtr(),
144
Op2, N->getSrcValue(), N->getAlignment());
145
// Legalized the chain result - switch anything that used the old chain to
147
ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
151
SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) {
152
SDValue Op2 = GetPromotedInteger(N->getOperand(2));
153
SDValue Op3 = GetPromotedInteger(N->getOperand(3));
154
SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
155
N->getMemoryVT(), N->getChain(), N->getBasePtr(),
156
Op2, Op3, N->getSrcValue(), N->getAlignment());
157
// Legalized the chain result - switch anything that used the old chain to
159
ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
163
SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) {
164
SDValue InOp = N->getOperand(0);
165
EVT InVT = InOp.getValueType();
166
EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
167
EVT OutVT = N->getValueType(0);
168
EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
169
DebugLoc dl = N->getDebugLoc();
171
switch (getTypeAction(InVT)) {
173
assert(false && "Unknown type action!");
178
if (NOutVT.bitsEq(NInVT))
179
// The input promotes to the same size. Convert the promoted value.
180
return DAG.getNode(ISD::BIT_CONVERT, dl,
181
NOutVT, GetPromotedInteger(InOp));
184
// Promote the integer operand by hand.
185
return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
189
case ScalarizeVector:
190
// Convert the element to an integer and promote it by hand.
191
return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
192
BitConvertToInteger(GetScalarizedVector(InOp)));
194
// For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split
195
// pieces of the input into integers and reassemble in the final type.
197
GetSplitVector(N->getOperand(0), Lo, Hi);
198
Lo = BitConvertToInteger(Lo);
199
Hi = BitConvertToInteger(Hi);
201
if (TLI.isBigEndian())
204
InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
205
EVT::getIntegerVT(*DAG.getContext(), NOutVT.getSizeInBits()),
206
JoinIntegers(Lo, Hi));
207
return DAG.getNode(ISD::BIT_CONVERT, dl, NOutVT, InOp);
210
if (OutVT.bitsEq(NInVT))
211
// The input is widened to the same size. Convert to the widened value.
212
return DAG.getNode(ISD::BIT_CONVERT, dl, OutVT, GetWidenedVector(InOp));
215
return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
216
CreateStackStoreLoad(InOp, OutVT));
219
SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
220
SDValue Op = GetPromotedInteger(N->getOperand(0));
221
EVT OVT = N->getValueType(0);
222
EVT NVT = Op.getValueType();
223
DebugLoc dl = N->getDebugLoc();
225
unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
226
return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
227
DAG.getConstant(DiffBits, TLI.getPointerTy()));
230
SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
231
// The pair element type may be legal, or may not promote to the same type as
232
// the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
233
return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(),
234
TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)),
235
JoinIntegers(N->getOperand(0), N->getOperand(1)));
238
SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
239
EVT VT = N->getValueType(0);
240
// FIXME there is no actual debug info here
241
DebugLoc dl = N->getDebugLoc();
242
// Zero extend things like i1, sign extend everything else. It shouldn't
243
// matter in theory which one we pick, but this tends to give better code?
244
unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
245
SDValue Result = DAG.getNode(Opc, dl, TLI.getTypeToTransformTo(*DAG.getContext(), VT),
247
assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
251
SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
252
ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
253
assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
254
CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
255
CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
256
"can only promote integers");
257
EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
258
return DAG.getConvertRndSat(OutVT, N->getDebugLoc(), N->getOperand(0),
259
N->getOperand(1), N->getOperand(2),
260
N->getOperand(3), N->getOperand(4), CvtCode);
263
SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
264
// Zero extend to the promoted type and do the count there.
265
SDValue Op = ZExtPromotedInteger(N->getOperand(0));
266
DebugLoc dl = N->getDebugLoc();
267
EVT OVT = N->getValueType(0);
268
EVT NVT = Op.getValueType();
269
Op = DAG.getNode(ISD::CTLZ, dl, NVT, Op);
270
// Subtract off the extra leading bits in the bigger type.
271
return DAG.getNode(ISD::SUB, dl, NVT, Op,
272
DAG.getConstant(NVT.getSizeInBits() -
273
OVT.getSizeInBits(), NVT));
276
SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
277
// Zero extend to the promoted type and do the count there.
278
SDValue Op = ZExtPromotedInteger(N->getOperand(0));
279
return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), Op.getValueType(), Op);
282
SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
283
SDValue Op = GetPromotedInteger(N->getOperand(0));
284
EVT OVT = N->getValueType(0);
285
EVT NVT = Op.getValueType();
286
DebugLoc dl = N->getDebugLoc();
287
// The count is the same in the promoted type except if the original
288
// value was zero. This can be handled by setting the bit just off
289
// the top of the original type.
290
APInt TopBit(NVT.getSizeInBits(), 0);
291
TopBit.set(OVT.getSizeInBits());
292
Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT));
293
return DAG.getNode(ISD::CTTZ, dl, NVT, Op);
296
SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
297
DebugLoc dl = N->getDebugLoc();
298
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
299
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0),
303
SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
304
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
305
unsigned NewOpc = N->getOpcode();
306
DebugLoc dl = N->getDebugLoc();
308
// If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
309
// not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
310
// and SINT conversions are Custom, there is no way to tell which is preferable.
311
// We choose SINT because that's the right thing on PPC.)
312
if (N->getOpcode() == ISD::FP_TO_UINT &&
313
!TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
314
TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
315
NewOpc = ISD::FP_TO_SINT;
317
SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
319
// Assert that the converted value fits in the original type. If it doesn't
320
// (eg: because the value being converted is too big), then the result of the
321
// original operation was undefined anyway, so the assert is still correct.
322
return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
323
ISD::AssertZext : ISD::AssertSext, dl,
324
NVT, Res, DAG.getValueType(N->getValueType(0)));
327
SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
328
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
329
DebugLoc dl = N->getDebugLoc();
331
if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) {
332
SDValue Res = GetPromotedInteger(N->getOperand(0));
333
assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
335
// If the result and operand types are the same after promotion, simplify
336
// to an in-register extension.
337
if (NVT == Res.getValueType()) {
338
// The high bits are not guaranteed to be anything. Insert an extend.
339
if (N->getOpcode() == ISD::SIGN_EXTEND)
340
return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
341
DAG.getValueType(N->getOperand(0).getValueType()));
342
if (N->getOpcode() == ISD::ZERO_EXTEND)
343
return DAG.getZeroExtendInReg(Res, dl, N->getOperand(0).getValueType());
344
assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
349
// Otherwise, just extend the original operand all the way to the larger type.
350
return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
353
SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
354
assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
355
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
356
ISD::LoadExtType ExtType =
357
ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
358
DebugLoc dl = N->getDebugLoc();
359
SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
360
N->getSrcValue(), N->getSrcValueOffset(),
361
N->getMemoryVT(), N->isVolatile(),
362
N->isNonTemporal(), N->getAlignment());
364
// Legalized the chain result - switch anything that used the old chain to
366
ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
370
/// Promote the overflow flag of an overflowing arithmetic node.
371
SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
372
// Simply change the return type of the boolean result.
373
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
374
EVT ValueVTs[] = { N->getValueType(0), NVT };
375
SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
376
SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(),
377
DAG.getVTList(ValueVTs, 2), Ops, 2);
379
// Modified the sum result - switch anything that used the old sum to use
381
ReplaceValueWith(SDValue(N, 0), Res);
383
return SDValue(Res.getNode(), 1);
386
SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
388
return PromoteIntRes_Overflow(N);
390
// The operation overflowed iff the result in the larger type is not the
391
// sign extension of its truncation to the original type.
392
SDValue LHS = SExtPromotedInteger(N->getOperand(0));
393
SDValue RHS = SExtPromotedInteger(N->getOperand(1));
394
EVT OVT = N->getOperand(0).getValueType();
395
EVT NVT = LHS.getValueType();
396
DebugLoc dl = N->getDebugLoc();
398
// Do the arithmetic in the larger type.
399
unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
400
SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
402
// Calculate the overflow flag: sign extend the arithmetic result from
403
// the original type.
404
SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
405
DAG.getValueType(OVT));
406
// Overflowed if and only if this is not equal to Res.
407
Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
409
// Use the calculated overflow everywhere.
410
ReplaceValueWith(SDValue(N, 1), Ofl);
415
SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
416
// Sign extend the input.
417
SDValue LHS = SExtPromotedInteger(N->getOperand(0));
418
SDValue RHS = SExtPromotedInteger(N->getOperand(1));
419
return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
420
LHS.getValueType(), LHS, RHS);
423
SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
424
SDValue LHS = GetPromotedInteger(N->getOperand(1));
425
SDValue RHS = GetPromotedInteger(N->getOperand(2));
426
return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
427
LHS.getValueType(), N->getOperand(0),LHS,RHS);
430
SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
431
SDValue LHS = GetPromotedInteger(N->getOperand(2));
432
SDValue RHS = GetPromotedInteger(N->getOperand(3));
433
return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(),
434
LHS.getValueType(), N->getOperand(0),
435
N->getOperand(1), LHS, RHS, N->getOperand(4));
438
SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
439
EVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType());
440
assert(isTypeLegal(SVT) && "Illegal SetCC type!");
441
DebugLoc dl = N->getDebugLoc();
443
// Get the SETCC result using the canonical SETCC type.
444
SDValue SetCC = DAG.getNode(ISD::SETCC, dl, SVT, N->getOperand(0),
445
N->getOperand(1), N->getOperand(2));
447
// Convert to the expected type.
448
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
449
assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
450
return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
453
SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
454
return DAG.getNode(ISD::SHL, N->getDebugLoc(),
455
TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)),
456
GetPromotedInteger(N->getOperand(0)), N->getOperand(1));
459
SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
460
SDValue Op = GetPromotedInteger(N->getOperand(0));
461
return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(),
462
Op.getValueType(), Op, N->getOperand(1));
465
SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
466
// The input may have strange things in the top bits of the registers, but
467
// these operations don't care. They may have weird bits going out, but
468
// that too is okay if they are integer operations.
469
SDValue LHS = GetPromotedInteger(N->getOperand(0));
470
SDValue RHS = GetPromotedInteger(N->getOperand(1));
471
return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
472
LHS.getValueType(), LHS, RHS);
475
SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
476
// The input value must be properly sign extended.
477
SDValue Res = SExtPromotedInteger(N->getOperand(0));
478
return DAG.getNode(ISD::SRA, N->getDebugLoc(),
479
Res.getValueType(), Res, N->getOperand(1));
482
SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
483
// The input value must be properly zero extended.
484
EVT VT = N->getValueType(0);
485
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
486
SDValue Res = ZExtPromotedInteger(N->getOperand(0));
487
return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1));
490
SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
491
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
494
switch (getTypeAction(N->getOperand(0).getValueType())) {
495
default: llvm_unreachable("Unknown type action!");
498
Res = N->getOperand(0);
501
Res = GetPromotedInteger(N->getOperand(0));
505
// Truncate to NVT instead of VT
506
return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Res);
509
SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
511
return PromoteIntRes_Overflow(N);
513
// The operation overflowed iff the result in the larger type is not the
514
// zero extension of its truncation to the original type.
515
SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
516
SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
517
EVT OVT = N->getOperand(0).getValueType();
518
EVT NVT = LHS.getValueType();
519
DebugLoc dl = N->getDebugLoc();
521
// Do the arithmetic in the larger type.
522
unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
523
SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
525
// Calculate the overflow flag: zero extend the arithmetic result from
526
// the original type.
527
SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
528
// Overflowed if and only if this is not equal to Res.
529
Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
531
// Use the calculated overflow everywhere.
532
ReplaceValueWith(SDValue(N, 1), Ofl);
537
SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
538
// Zero extend the input.
539
SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
540
SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
541
return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
542
LHS.getValueType(), LHS, RHS);
545
SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
546
return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)));
549
SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
550
SDValue Chain = N->getOperand(0); // Get the chain.
551
SDValue Ptr = N->getOperand(1); // Get the pointer.
552
EVT VT = N->getValueType(0);
553
DebugLoc dl = N->getDebugLoc();
555
EVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
556
unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
557
// The argument is passed as NumRegs registers of type RegVT.
559
SmallVector<SDValue, 8> Parts(NumRegs);
560
for (unsigned i = 0; i < NumRegs; ++i) {
561
Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2));
562
Chain = Parts[i].getValue(1);
565
// Handle endianness of the load.
566
if (TLI.isBigEndian())
567
std::reverse(Parts.begin(), Parts.end());
569
// Assemble the parts in the promoted type.
570
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
571
SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
572
for (unsigned i = 1; i < NumRegs; ++i) {
573
SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
574
// Shift it to the right position and "or" it in.
575
Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
576
DAG.getConstant(i * RegVT.getSizeInBits(),
577
TLI.getPointerTy()));
578
Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
581
// Modified the chain result - switch anything that used the old chain to
583
ReplaceValueWith(SDValue(N, 1), Chain);
588
SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
589
assert(ResNo == 1 && "Only boolean result promotion currently supported!");
590
return PromoteIntRes_Overflow(N);
593
//===----------------------------------------------------------------------===//
594
// Integer Operand Promotion
595
//===----------------------------------------------------------------------===//
597
/// PromoteIntegerOperand - This method is called when the specified operand of
598
/// the specified node is found to need promotion. At this point, all of the
599
/// result types of the node are known to be legal, but other operands of the
600
/// node may need promotion or expansion as well as the specified one.
601
bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
602
DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG); dbgs() << "\n");
603
SDValue Res = SDValue();
605
if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
608
switch (N->getOpcode()) {
611
dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
612
N->dump(&DAG); dbgs() << "\n";
614
llvm_unreachable("Do not know how to promote this operator's operand!");
616
case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
617
case ISD::BIT_CONVERT: Res = PromoteIntOp_BIT_CONVERT(N); break;
618
case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
619
case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
620
case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
621
case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
622
case ISD::CONVERT_RNDSAT:
623
Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
624
case ISD::INSERT_VECTOR_ELT:
625
Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
626
case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break;
627
case ISD::SCALAR_TO_VECTOR:
628
Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
629
case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
630
case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
631
case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
632
case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
633
case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
634
case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
636
case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
637
case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
638
case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
644
case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
647
// If the result is null, the sub-method took care of registering results etc.
648
if (!Res.getNode()) return false;
650
// If the result is N, the sub-method updated N in place. Tell the legalizer
652
if (Res.getNode() == N)
655
assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
656
"Invalid operand expansion");
658
ReplaceValueWith(SDValue(N, 0), Res);
662
/// PromoteSetCCOperands - Promote the operands of a comparison. This code is
663
/// shared among BR_CC, SELECT_CC, and SETCC handlers.
664
void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
665
ISD::CondCode CCCode) {
666
// We have to insert explicit sign or zero extends. Note that we could
667
// insert sign extends for ALL conditions, but zero extend is cheaper on
668
// many machines (an AND instead of two shifts), so prefer it.
670
default: llvm_unreachable("Unknown integer comparison!");
677
// ALL of these operations will work if we either sign or zero extend
678
// the operands (including the unsigned comparisons!). Zero extend is
679
// usually a simpler/cheaper operation, so prefer it.
680
NewLHS = ZExtPromotedInteger(NewLHS);
681
NewRHS = ZExtPromotedInteger(NewRHS);
687
NewLHS = SExtPromotedInteger(NewLHS);
688
NewRHS = SExtPromotedInteger(NewRHS);
693
SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
694
SDValue Op = GetPromotedInteger(N->getOperand(0));
695
return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op);
698
SDValue DAGTypeLegalizer::PromoteIntOp_BIT_CONVERT(SDNode *N) {
699
// This should only occur in unusual situations like bitcasting to an
700
// x86_fp80, so just turn it into a store+load
701
return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
704
SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
705
assert(OpNo == 2 && "Don't know how to promote this operand!");
707
SDValue LHS = N->getOperand(2);
708
SDValue RHS = N->getOperand(3);
709
PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
711
// The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
713
return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
714
N->getOperand(1), LHS, RHS, N->getOperand(4));
717
SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
718
assert(OpNo == 1 && "only know how to promote condition");
720
// Promote all the way up to the canonical SetCC type.
721
EVT SVT = TLI.getSetCCResultType(MVT::Other);
722
SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT);
724
// The chain (Op#0) and basic block destination (Op#2) are always legal types.
725
return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Cond,
729
SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
730
// Since the result type is legal, the operands must promote to it.
731
EVT OVT = N->getOperand(0).getValueType();
732
SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
733
SDValue Hi = GetPromotedInteger(N->getOperand(1));
734
assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
735
DebugLoc dl = N->getDebugLoc();
737
Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
738
DAG.getConstant(OVT.getSizeInBits(), TLI.getPointerTy()));
739
return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
742
SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
743
// The vector type is legal but the element type is not. This implies
744
// that the vector is a power-of-two in length and that the element
745
// type does not have a strange size (eg: it is not i1).
746
EVT VecVT = N->getValueType(0);
747
unsigned NumElts = VecVT.getVectorNumElements();
748
assert(!(NumElts & 1) && "Legal vector of one illegal element?");
750
// Promote the inserted value. The type does not need to match the
751
// vector element type. Check that any extra bits introduced will be
753
assert(N->getOperand(0).getValueType().getSizeInBits() >=
754
N->getValueType(0).getVectorElementType().getSizeInBits() &&
755
"Type of inserted value narrower than vector element type!");
757
SmallVector<SDValue, 16> NewOps;
758
for (unsigned i = 0; i < NumElts; ++i)
759
NewOps.push_back(GetPromotedInteger(N->getOperand(i)));
761
return DAG.UpdateNodeOperands(SDValue(N, 0), &NewOps[0], NumElts);
764
SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
765
ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
766
assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
767
CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
768
CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
769
"can only promote integer arguments");
770
SDValue InOp = GetPromotedInteger(N->getOperand(0));
771
return DAG.getConvertRndSat(N->getValueType(0), N->getDebugLoc(), InOp,
772
N->getOperand(1), N->getOperand(2),
773
N->getOperand(3), N->getOperand(4), CvtCode);
776
SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
779
// Promote the inserted value. This is valid because the type does not
780
// have to match the vector element type.
782
// Check that any extra bits introduced will be truncated away.
783
assert(N->getOperand(1).getValueType().getSizeInBits() >=
784
N->getValueType(0).getVectorElementType().getSizeInBits() &&
785
"Type of inserted value narrower than vector element type!");
786
return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
787
GetPromotedInteger(N->getOperand(1)),
791
assert(OpNo == 2 && "Different operand and result vector types?");
793
// Promote the index.
794
SDValue Idx = ZExtPromotedInteger(N->getOperand(2));
795
return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
796
N->getOperand(1), Idx);
799
SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
801
DebugLoc dl = N->getDebugLoc();
802
NewOps[0] = N->getOperand(0);
803
for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
804
SDValue Flag = GetPromotedInteger(N->getOperand(i));
805
NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, MVT::i1);
807
return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps,
808
array_lengthof(NewOps));
811
SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) {
812
// Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
813
// the operand in place.
814
return DAG.UpdateNodeOperands(SDValue(N, 0),
815
GetPromotedInteger(N->getOperand(0)));
818
SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
819
assert(OpNo == 0 && "Only know how to promote condition");
821
// Promote all the way up to the canonical SetCC type.
822
EVT SVT = TLI.getSetCCResultType(N->getOperand(1).getValueType());
823
SDValue Cond = PromoteTargetBoolean(N->getOperand(0), SVT);
825
return DAG.UpdateNodeOperands(SDValue(N, 0), Cond,
826
N->getOperand(1), N->getOperand(2));
829
SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
830
assert(OpNo == 0 && "Don't know how to promote this operand!");
832
SDValue LHS = N->getOperand(0);
833
SDValue RHS = N->getOperand(1);
834
PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
836
// The CC (#4) and the possible return values (#2 and #3) have legal types.
837
return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2),
838
N->getOperand(3), N->getOperand(4));
841
SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
842
assert(OpNo == 0 && "Don't know how to promote this operand!");
844
SDValue LHS = N->getOperand(0);
845
SDValue RHS = N->getOperand(1);
846
PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
848
// The CC (#2) is always legal.
849
return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2));
852
SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
853
return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
854
ZExtPromotedInteger(N->getOperand(1)));
857
SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
858
SDValue Op = GetPromotedInteger(N->getOperand(0));
859
DebugLoc dl = N->getDebugLoc();
860
Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
861
return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
862
Op, DAG.getValueType(N->getOperand(0).getValueType()));
865
SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
866
return DAG.UpdateNodeOperands(SDValue(N, 0),
867
SExtPromotedInteger(N->getOperand(0)));
870
SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
871
assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
872
SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
873
int SVOffset = N->getSrcValueOffset();
874
unsigned Alignment = N->getAlignment();
875
bool isVolatile = N->isVolatile();
876
bool isNonTemporal = N->isNonTemporal();
877
DebugLoc dl = N->getDebugLoc();
879
SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
881
// Truncate the value and store the result.
882
return DAG.getTruncStore(Ch, dl, Val, Ptr, N->getSrcValue(),
883
SVOffset, N->getMemoryVT(),
884
isVolatile, isNonTemporal, Alignment);
887
SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
888
SDValue Op = GetPromotedInteger(N->getOperand(0));
889
return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), Op);
892
SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
893
return DAG.UpdateNodeOperands(SDValue(N, 0),
894
ZExtPromotedInteger(N->getOperand(0)));
897
SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
898
DebugLoc dl = N->getDebugLoc();
899
SDValue Op = GetPromotedInteger(N->getOperand(0));
900
Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
901
return DAG.getZeroExtendInReg(Op, dl, N->getOperand(0).getValueType());
905
//===----------------------------------------------------------------------===//
906
// Integer Result Expansion
907
//===----------------------------------------------------------------------===//
909
/// ExpandIntegerResult - This method is called when the specified result of the
910
/// specified node is found to need expansion. At this point, the node may also
911
/// have invalid operands or may have other results that need promotion, we just
912
/// know that (at least) one result needs expansion.
913
void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
914
DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG); dbgs() << "\n");
918
// See if the target wants to custom expand this node.
919
if (CustomLowerNode(N, N->getValueType(ResNo), true))
922
switch (N->getOpcode()) {
925
dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
926
N->dump(&DAG); dbgs() << "\n";
928
llvm_unreachable("Do not know how to expand the result of this operator!");
930
case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
931
case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
932
case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
933
case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
935
case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break;
936
case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
937
case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
938
case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
939
case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
941
case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
942
case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
943
case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
944
case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
945
case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
946
case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
947
case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
948
case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
949
case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
950
case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
951
case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
952
case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
953
case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
954
case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
955
case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
956
case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
957
case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
958
case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
959
case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
960
case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
964
case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
967
case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
970
case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
973
case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
977
case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
980
// If Lo/Hi is null, the sub-method took care of registering results etc.
982
SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
985
/// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
986
/// and the shift amount is a constant 'Amt'. Expand the operation.
987
void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
988
SDValue &Lo, SDValue &Hi) {
989
DebugLoc dl = N->getDebugLoc();
990
// Expand the incoming operand to be shifted, so that we have its parts
992
GetExpandedInteger(N->getOperand(0), InL, InH);
994
EVT NVT = InL.getValueType();
995
unsigned VTBits = N->getValueType(0).getSizeInBits();
996
unsigned NVTBits = NVT.getSizeInBits();
997
EVT ShTy = N->getOperand(1).getValueType();
999
if (N->getOpcode() == ISD::SHL) {
1001
Lo = Hi = DAG.getConstant(0, NVT);
1002
} else if (Amt > NVTBits) {
1003
Lo = DAG.getConstant(0, NVT);
1004
Hi = DAG.getNode(ISD::SHL, dl,
1005
NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy));
1006
} else if (Amt == NVTBits) {
1007
Lo = DAG.getConstant(0, NVT);
1009
} else if (Amt == 1 &&
1010
TLI.isOperationLegalOrCustom(ISD::ADDC,
1011
TLI.getTypeToExpandTo(*DAG.getContext(), NVT))) {
1012
// Emit this X << 1 as X+X.
1013
SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
1014
SDValue LoOps[2] = { InL, InL };
1015
Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1016
SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1017
Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1019
Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, DAG.getConstant(Amt, ShTy));
1020
Hi = DAG.getNode(ISD::OR, dl, NVT,
1021
DAG.getNode(ISD::SHL, dl, NVT, InH,
1022
DAG.getConstant(Amt, ShTy)),
1023
DAG.getNode(ISD::SRL, dl, NVT, InL,
1024
DAG.getConstant(NVTBits-Amt, ShTy)));
1029
if (N->getOpcode() == ISD::SRL) {
1031
Lo = DAG.getConstant(0, NVT);
1032
Hi = DAG.getConstant(0, NVT);
1033
} else if (Amt > NVTBits) {
1034
Lo = DAG.getNode(ISD::SRL, dl,
1035
NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
1036
Hi = DAG.getConstant(0, NVT);
1037
} else if (Amt == NVTBits) {
1039
Hi = DAG.getConstant(0, NVT);
1041
Lo = DAG.getNode(ISD::OR, dl, NVT,
1042
DAG.getNode(ISD::SRL, dl, NVT, InL,
1043
DAG.getConstant(Amt, ShTy)),
1044
DAG.getNode(ISD::SHL, dl, NVT, InH,
1045
DAG.getConstant(NVTBits-Amt, ShTy)));
1046
Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, DAG.getConstant(Amt, ShTy));
1051
assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1053
Hi = Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
1054
DAG.getConstant(NVTBits-1, ShTy));
1055
} else if (Amt > NVTBits) {
1056
Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
1057
DAG.getConstant(Amt-NVTBits, ShTy));
1058
Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
1059
DAG.getConstant(NVTBits-1, ShTy));
1060
} else if (Amt == NVTBits) {
1062
Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
1063
DAG.getConstant(NVTBits-1, ShTy));
1065
Lo = DAG.getNode(ISD::OR, dl, NVT,
1066
DAG.getNode(ISD::SRL, dl, NVT, InL,
1067
DAG.getConstant(Amt, ShTy)),
1068
DAG.getNode(ISD::SHL, dl, NVT, InH,
1069
DAG.getConstant(NVTBits-Amt, ShTy)));
1070
Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(Amt, ShTy));
1074
/// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1075
/// this shift based on knowledge of the high bit of the shift amount. If we
1076
/// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1078
bool DAGTypeLegalizer::
1079
ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1080
SDValue Amt = N->getOperand(1);
1081
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1082
EVT ShTy = Amt.getValueType();
1083
unsigned ShBits = ShTy.getScalarType().getSizeInBits();
1084
unsigned NVTBits = NVT.getScalarType().getSizeInBits();
1085
assert(isPowerOf2_32(NVTBits) &&
1086
"Expanded integer type size not a power of two!");
1087
DebugLoc dl = N->getDebugLoc();
1089
APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1090
APInt KnownZero, KnownOne;
1091
DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne);
1093
// If we don't know anything about the high bits, exit.
1094
if (((KnownZero|KnownOne) & HighBitMask) == 0)
1097
// Get the incoming operand to be shifted.
1099
GetExpandedInteger(N->getOperand(0), InL, InH);
1101
// If we know that any of the high bits of the shift amount are one, then we
1102
// can do this as a couple of simple shifts.
1103
if (KnownOne.intersects(HighBitMask)) {
1104
// Mask out the high bit, which we know is set.
1105
Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
1106
DAG.getConstant(~HighBitMask, ShTy));
1108
switch (N->getOpcode()) {
1109
default: llvm_unreachable("Unknown shift");
1111
Lo = DAG.getConstant(0, NVT); // Low part is zero.
1112
Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1115
Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1116
Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1119
Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1120
DAG.getConstant(NVTBits-1, ShTy));
1121
Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1127
// FIXME: This code is broken for shifts with a zero amount!
1128
// If we know that all of the high bits of the shift amount are zero, then we
1129
// can do this as a couple of simple shifts.
1130
if ((KnownZero & HighBitMask) == HighBitMask) {
1132
SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy,
1133
DAG.getConstant(NVTBits, ShTy),
1136
switch (N->getOpcode()) {
1137
default: llvm_unreachable("Unknown shift");
1138
case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1140
case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1143
Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt);
1144
Hi = DAG.getNode(ISD::OR, NVT,
1145
DAG.getNode(Op1, NVT, InH, Amt),
1146
DAG.getNode(Op2, NVT, InL, Amt2));
1154
/// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
1156
bool DAGTypeLegalizer::
1157
ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1158
SDValue Amt = N->getOperand(1);
1159
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1160
EVT ShTy = Amt.getValueType();
1161
unsigned NVTBits = NVT.getSizeInBits();
1162
assert(isPowerOf2_32(NVTBits) &&
1163
"Expanded integer type size not a power of two!");
1164
DebugLoc dl = N->getDebugLoc();
1166
// Get the incoming operand to be shifted.
1168
GetExpandedInteger(N->getOperand(0), InL, InH);
1170
SDValue NVBitsNode = DAG.getConstant(NVTBits, ShTy);
1171
SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode);
1172
SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
1173
SDValue isShort = DAG.getSetCC(dl, TLI.getSetCCResultType(ShTy),
1174
Amt, NVBitsNode, ISD::SETULT);
1176
SDValue LoS, HiS, LoL, HiL;
1177
switch (N->getOpcode()) {
1178
default: llvm_unreachable("Unknown shift");
1180
// Short: ShAmt < NVTBits
1181
LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
1182
HiS = DAG.getNode(ISD::OR, dl, NVT,
1183
DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
1184
// FIXME: If Amt is zero, the following shift generates an undefined result
1185
// on some architectures.
1186
DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack));
1188
// Long: ShAmt >= NVTBits
1189
LoL = DAG.getConstant(0, NVT); // Lo part is zero.
1190
HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part.
1192
Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1193
Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1196
// Short: ShAmt < NVTBits
1197
HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
1198
LoS = DAG.getNode(ISD::OR, dl, NVT,
1199
DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1200
// FIXME: If Amt is zero, the following shift generates an undefined result
1201
// on some architectures.
1202
DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1204
// Long: ShAmt >= NVTBits
1205
HiL = DAG.getConstant(0, NVT); // Hi part is zero.
1206
LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1208
Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1209
Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1212
// Short: ShAmt < NVTBits
1213
HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
1214
LoS = DAG.getNode(ISD::OR, dl, NVT,
1215
DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1216
// FIXME: If Amt is zero, the following shift generates an undefined result
1217
// on some architectures.
1218
DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1220
// Long: ShAmt >= NVTBits
1221
HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part.
1222
DAG.getConstant(NVTBits-1, ShTy));
1223
LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1225
Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1226
Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1233
void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1234
SDValue &Lo, SDValue &Hi) {
1235
DebugLoc dl = N->getDebugLoc();
1236
// Expand the subcomponents.
1237
SDValue LHSL, LHSH, RHSL, RHSH;
1238
GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1239
GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1241
EVT NVT = LHSL.getValueType();
1242
SDValue LoOps[2] = { LHSL, RHSL };
1243
SDValue HiOps[3] = { LHSH, RHSH };
1245
// Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1246
// them. TODO: Teach operation legalization how to expand unsupported
1247
// ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1248
// a carry of type MVT::Flag, but there doesn't seem to be any way to
1249
// generate a value of this type in the expanded code sequence.
1251
TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1252
ISD::ADDC : ISD::SUBC,
1253
TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
1256
SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
1257
if (N->getOpcode() == ISD::ADD) {
1258
Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1259
HiOps[2] = Lo.getValue(1);
1260
Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1262
Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1263
HiOps[2] = Lo.getValue(1);
1264
Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1267
if (N->getOpcode() == ISD::ADD) {
1268
Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2);
1269
Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2);
1270
SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[0],
1272
SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1,
1273
DAG.getConstant(1, NVT),
1274
DAG.getConstant(0, NVT));
1275
SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[1],
1277
SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2,
1278
DAG.getConstant(1, NVT), Carry1);
1279
Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
1281
Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2);
1282
Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2);
1284
DAG.getSetCC(dl, TLI.getSetCCResultType(LoOps[0].getValueType()),
1285
LoOps[0], LoOps[1], ISD::SETULT);
1286
SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp,
1287
DAG.getConstant(1, NVT),
1288
DAG.getConstant(0, NVT));
1289
Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
1294
void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1295
SDValue &Lo, SDValue &Hi) {
1296
// Expand the subcomponents.
1297
SDValue LHSL, LHSH, RHSL, RHSH;
1298
DebugLoc dl = N->getDebugLoc();
1299
GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1300
GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1301
SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1302
SDValue LoOps[2] = { LHSL, RHSL };
1303
SDValue HiOps[3] = { LHSH, RHSH };
1305
if (N->getOpcode() == ISD::ADDC) {
1306
Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1307
HiOps[2] = Lo.getValue(1);
1308
Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1310
Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1311
HiOps[2] = Lo.getValue(1);
1312
Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1315
// Legalized the flag result - switch anything that used the old flag to
1317
ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1320
void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1321
SDValue &Lo, SDValue &Hi) {
1322
// Expand the subcomponents.
1323
SDValue LHSL, LHSH, RHSL, RHSH;
1324
DebugLoc dl = N->getDebugLoc();
1325
GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1326
GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1327
SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1328
SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1329
SDValue HiOps[3] = { LHSH, RHSH };
1331
Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps, 3);
1332
HiOps[2] = Lo.getValue(1);
1333
Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3);
1335
// Legalized the flag result - switch anything that used the old flag to
1337
ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1340
void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1341
SDValue &Lo, SDValue &Hi) {
1342
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1343
DebugLoc dl = N->getDebugLoc();
1344
SDValue Op = N->getOperand(0);
1345
if (Op.getValueType().bitsLE(NVT)) {
1346
// The low part is any extension of the input (which degenerates to a copy).
1347
Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
1348
Hi = DAG.getUNDEF(NVT); // The high part is undefined.
1350
// For example, extension of an i48 to an i64. The operand type necessarily
1351
// promotes to the result type, so will end up being expanded too.
1352
assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1353
"Only know how to promote this result!");
1354
SDValue Res = GetPromotedInteger(Op);
1355
assert(Res.getValueType() == N->getValueType(0) &&
1356
"Operand over promoted?");
1357
// Split the promoted operand. This will simplify when it is expanded.
1358
SplitInteger(Res, Lo, Hi);
1362
void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1363
SDValue &Lo, SDValue &Hi) {
1364
DebugLoc dl = N->getDebugLoc();
1365
GetExpandedInteger(N->getOperand(0), Lo, Hi);
1366
EVT NVT = Lo.getValueType();
1367
EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1368
unsigned NVTBits = NVT.getSizeInBits();
1369
unsigned EVTBits = EVT.getSizeInBits();
1371
if (NVTBits < EVTBits) {
1372
Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
1373
DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), EVTBits - NVTBits)));
1375
Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
1376
// The high part replicates the sign bit of Lo, make it explicit.
1377
Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1378
DAG.getConstant(NVTBits-1, TLI.getPointerTy()));
1382
void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1383
SDValue &Lo, SDValue &Hi) {
1384
DebugLoc dl = N->getDebugLoc();
1385
GetExpandedInteger(N->getOperand(0), Lo, Hi);
1386
EVT NVT = Lo.getValueType();
1387
EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1388
unsigned NVTBits = NVT.getSizeInBits();
1389
unsigned EVTBits = EVT.getSizeInBits();
1391
if (NVTBits < EVTBits) {
1392
Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
1393
DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), EVTBits - NVTBits)));
1395
Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
1396
// The high part must be zero, make it explicit.
1397
Hi = DAG.getConstant(0, NVT);
1401
void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1402
SDValue &Lo, SDValue &Hi) {
1403
DebugLoc dl = N->getDebugLoc();
1404
GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1405
Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
1406
Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
1409
void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1410
SDValue &Lo, SDValue &Hi) {
1411
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1412
unsigned NBitWidth = NVT.getSizeInBits();
1413
const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue();
1414
Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT);
1415
Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT);
1418
void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1419
SDValue &Lo, SDValue &Hi) {
1420
DebugLoc dl = N->getDebugLoc();
1421
// ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1422
GetExpandedInteger(N->getOperand(0), Lo, Hi);
1423
EVT NVT = Lo.getValueType();
1425
SDValue HiNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Hi,
1426
DAG.getConstant(0, NVT), ISD::SETNE);
1428
SDValue LoLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Lo);
1429
SDValue HiLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Hi);
1431
Lo = DAG.getNode(ISD::SELECT, dl, NVT, HiNotZero, HiLZ,
1432
DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
1433
DAG.getConstant(NVT.getSizeInBits(), NVT)));
1434
Hi = DAG.getConstant(0, NVT);
1437
void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1438
SDValue &Lo, SDValue &Hi) {
1439
DebugLoc dl = N->getDebugLoc();
1440
// ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1441
GetExpandedInteger(N->getOperand(0), Lo, Hi);
1442
EVT NVT = Lo.getValueType();
1443
Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
1444
DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
1445
Hi = DAG.getConstant(0, NVT);
1448
void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1449
SDValue &Lo, SDValue &Hi) {
1450
DebugLoc dl = N->getDebugLoc();
1451
// cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1452
GetExpandedInteger(N->getOperand(0), Lo, Hi);
1453
EVT NVT = Lo.getValueType();
1455
SDValue LoNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo,
1456
DAG.getConstant(0, NVT), ISD::SETNE);
1458
SDValue LoLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo);
1459
SDValue HiLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Hi);
1461
Lo = DAG.getNode(ISD::SELECT, dl, NVT, LoNotZero, LoLZ,
1462
DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
1463
DAG.getConstant(NVT.getSizeInBits(), NVT)));
1464
Hi = DAG.getConstant(0, NVT);
1467
void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1469
DebugLoc dl = N->getDebugLoc();
1470
EVT VT = N->getValueType(0);
1471
SDValue Op = N->getOperand(0);
1472
RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1473
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1474
SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*irrelevant*/, dl), Lo, Hi);
1477
void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1479
DebugLoc dl = N->getDebugLoc();
1480
EVT VT = N->getValueType(0);
1481
SDValue Op = N->getOperand(0);
1482
RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1483
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1484
SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*irrelevant*/, dl), Lo, Hi);
1487
void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1488
SDValue &Lo, SDValue &Hi) {
1489
if (ISD::isNormalLoad(N)) {
1490
ExpandRes_NormalLoad(N, Lo, Hi);
1494
assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1496
EVT VT = N->getValueType(0);
1497
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1498
SDValue Ch = N->getChain();
1499
SDValue Ptr = N->getBasePtr();
1500
ISD::LoadExtType ExtType = N->getExtensionType();
1501
int SVOffset = N->getSrcValueOffset();
1502
unsigned Alignment = N->getAlignment();
1503
bool isVolatile = N->isVolatile();
1504
bool isNonTemporal = N->isNonTemporal();
1505
DebugLoc dl = N->getDebugLoc();
1507
assert(NVT.isByteSized() && "Expanded type not byte sized!");
1509
if (N->getMemoryVT().bitsLE(NVT)) {
1510
EVT MemVT = N->getMemoryVT();
1512
Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1513
MemVT, isVolatile, isNonTemporal, Alignment);
1515
// Remember the chain.
1516
Ch = Lo.getValue(1);
1518
if (ExtType == ISD::SEXTLOAD) {
1519
// The high part is obtained by SRA'ing all but one of the bits of the
1521
unsigned LoSize = Lo.getValueType().getSizeInBits();
1522
Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1523
DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1524
} else if (ExtType == ISD::ZEXTLOAD) {
1525
// The high part is just a zero.
1526
Hi = DAG.getConstant(0, NVT);
1528
assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1529
// The high part is undefined.
1530
Hi = DAG.getUNDEF(NVT);
1532
} else if (TLI.isLittleEndian()) {
1533
// Little-endian - low bits are at low addresses.
1534
Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getSrcValue(), SVOffset,
1535
isVolatile, isNonTemporal, Alignment);
1537
unsigned ExcessBits =
1538
N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1539
EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
1541
// Increment the pointer to the other half.
1542
unsigned IncrementSize = NVT.getSizeInBits()/8;
1543
Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1544
DAG.getIntPtrConstant(IncrementSize));
1545
Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(),
1546
SVOffset+IncrementSize, NEVT,
1547
isVolatile, isNonTemporal,
1548
MinAlign(Alignment, IncrementSize));
1550
// Build a factor node to remember that this load is independent of the
1552
Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1555
// Big-endian - high bits are at low addresses. Favor aligned loads at
1556
// the cost of some bit-fiddling.
1557
EVT MemVT = N->getMemoryVT();
1558
unsigned EBytes = MemVT.getStoreSize();
1559
unsigned IncrementSize = NVT.getSizeInBits()/8;
1560
unsigned ExcessBits = (EBytes - IncrementSize)*8;
1562
// Load both the high bits and maybe some of the low bits.
1563
Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1564
EVT::getIntegerVT(*DAG.getContext(),
1565
MemVT.getSizeInBits() - ExcessBits),
1566
isVolatile, isNonTemporal, Alignment);
1568
// Increment the pointer to the other half.
1569
Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1570
DAG.getIntPtrConstant(IncrementSize));
1571
// Load the rest of the low bits.
1572
Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr, N->getSrcValue(),
1573
SVOffset+IncrementSize,
1574
EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
1575
isVolatile, isNonTemporal,
1576
MinAlign(Alignment, IncrementSize));
1578
// Build a factor node to remember that this load is independent of the
1580
Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1583
if (ExcessBits < NVT.getSizeInBits()) {
1584
// Transfer low bits from the bottom of Hi to the top of Lo.
1585
Lo = DAG.getNode(ISD::OR, dl, NVT, Lo,
1586
DAG.getNode(ISD::SHL, dl, NVT, Hi,
1587
DAG.getConstant(ExcessBits,
1588
TLI.getPointerTy())));
1589
// Move high bits to the right position in Hi.
1590
Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl,
1592
DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1593
TLI.getPointerTy()));
1597
// Legalized the chain result - switch anything that used the old chain to
1599
ReplaceValueWith(SDValue(N, 1), Ch);
1602
void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
1603
SDValue &Lo, SDValue &Hi) {
1604
DebugLoc dl = N->getDebugLoc();
1605
SDValue LL, LH, RL, RH;
1606
GetExpandedInteger(N->getOperand(0), LL, LH);
1607
GetExpandedInteger(N->getOperand(1), RL, RH);
1608
Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
1609
Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
1612
void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
1613
SDValue &Lo, SDValue &Hi) {
1614
EVT VT = N->getValueType(0);
1615
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1616
DebugLoc dl = N->getDebugLoc();
1618
bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
1619
bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT);
1620
bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT);
1621
bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT);
1622
if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
1623
SDValue LL, LH, RL, RH;
1624
GetExpandedInteger(N->getOperand(0), LL, LH);
1625
GetExpandedInteger(N->getOperand(1), RL, RH);
1626
unsigned OuterBitSize = VT.getSizeInBits();
1627
unsigned InnerBitSize = NVT.getSizeInBits();
1628
unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
1629
unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
1631
APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
1632
if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
1633
DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
1634
// The inputs are both zero-extended.
1636
// We can emit a umul_lohi.
1637
Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1638
Hi = SDValue(Lo.getNode(), 1);
1642
// We can emit a mulhu+mul.
1643
Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1644
Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1648
if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
1649
// The input values are both sign-extended.
1651
// We can emit a smul_lohi.
1652
Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1653
Hi = SDValue(Lo.getNode(), 1);
1657
// We can emit a mulhs+mul.
1658
Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1659
Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL);
1664
// Lo,Hi = umul LHS, RHS.
1665
SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
1666
DAG.getVTList(NVT, NVT), LL, RL);
1668
Hi = UMulLOHI.getValue(1);
1669
RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1670
LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1671
Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1672
Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1676
Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1677
Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1678
RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1679
LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1680
Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1681
Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1686
// If nothing else, we can make a libcall.
1687
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1689
LC = RTLIB::MUL_I16;
1690
else if (VT == MVT::i32)
1691
LC = RTLIB::MUL_I32;
1692
else if (VT == MVT::i64)
1693
LC = RTLIB::MUL_I64;
1694
else if (VT == MVT::i128)
1695
LC = RTLIB::MUL_I128;
1696
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
1698
SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1699
SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*irrelevant*/, dl), Lo, Hi);
1702
void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
1703
SDValue &Lo, SDValue &Hi) {
1704
EVT VT = N->getValueType(0);
1705
DebugLoc dl = N->getDebugLoc();
1707
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1709
LC = RTLIB::SDIV_I16;
1710
else if (VT == MVT::i32)
1711
LC = RTLIB::SDIV_I32;
1712
else if (VT == MVT::i64)
1713
LC = RTLIB::SDIV_I64;
1714
else if (VT == MVT::i128)
1715
LC = RTLIB::SDIV_I128;
1716
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1718
SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1719
SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
1722
void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
1723
SDValue &Lo, SDValue &Hi) {
1724
EVT VT = N->getValueType(0);
1725
DebugLoc dl = N->getDebugLoc();
1727
// If we can emit an efficient shift operation, do so now. Check to see if
1728
// the RHS is a constant.
1729
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1730
return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi);
1732
// If we can determine that the high bit of the shift is zero or one, even if
1733
// the low bits are variable, emit this shift in an optimized form.
1734
if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
1737
// If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
1739
if (N->getOpcode() == ISD::SHL) {
1740
PartsOpc = ISD::SHL_PARTS;
1741
} else if (N->getOpcode() == ISD::SRL) {
1742
PartsOpc = ISD::SRL_PARTS;
1744
assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1745
PartsOpc = ISD::SRA_PARTS;
1748
// Next check to see if the target supports this SHL_PARTS operation or if it
1749
// will custom expand it.
1750
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1751
TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
1752
if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
1753
Action == TargetLowering::Custom) {
1754
// Expand the subcomponents.
1756
GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1758
SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) };
1759
EVT VT = LHSL.getValueType();
1760
Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops, 3);
1761
Hi = Lo.getValue(1);
1765
// Otherwise, emit a libcall.
1766
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1768
if (N->getOpcode() == ISD::SHL) {
1769
isSigned = false; /*sign irrelevant*/
1771
LC = RTLIB::SHL_I16;
1772
else if (VT == MVT::i32)
1773
LC = RTLIB::SHL_I32;
1774
else if (VT == MVT::i64)
1775
LC = RTLIB::SHL_I64;
1776
else if (VT == MVT::i128)
1777
LC = RTLIB::SHL_I128;
1778
} else if (N->getOpcode() == ISD::SRL) {
1781
LC = RTLIB::SRL_I16;
1782
else if (VT == MVT::i32)
1783
LC = RTLIB::SRL_I32;
1784
else if (VT == MVT::i64)
1785
LC = RTLIB::SRL_I64;
1786
else if (VT == MVT::i128)
1787
LC = RTLIB::SRL_I128;
1789
assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1792
LC = RTLIB::SRA_I16;
1793
else if (VT == MVT::i32)
1794
LC = RTLIB::SRA_I32;
1795
else if (VT == MVT::i64)
1796
LC = RTLIB::SRA_I64;
1797
else if (VT == MVT::i128)
1798
LC = RTLIB::SRA_I128;
1801
if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
1802
SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1803
SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned, dl), Lo, Hi);
1807
if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
1808
llvm_unreachable("Unsupported shift!");
1811
void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
1812
SDValue &Lo, SDValue &Hi) {
1813
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1814
DebugLoc dl = N->getDebugLoc();
1815
SDValue Op = N->getOperand(0);
1816
if (Op.getValueType().bitsLE(NVT)) {
1817
// The low part is sign extension of the input (degenerates to a copy).
1818
Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
1819
// The high part is obtained by SRA'ing all but one of the bits of low part.
1820
unsigned LoSize = NVT.getSizeInBits();
1821
Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1822
DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1824
// For example, extension of an i48 to an i64. The operand type necessarily
1825
// promotes to the result type, so will end up being expanded too.
1826
assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1827
"Only know how to promote this result!");
1828
SDValue Res = GetPromotedInteger(Op);
1829
assert(Res.getValueType() == N->getValueType(0) &&
1830
"Operand over promoted?");
1831
// Split the promoted operand. This will simplify when it is expanded.
1832
SplitInteger(Res, Lo, Hi);
1833
unsigned ExcessBits =
1834
Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1835
Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
1836
DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), ExcessBits)));
1840
void DAGTypeLegalizer::
1841
ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
1842
DebugLoc dl = N->getDebugLoc();
1843
GetExpandedInteger(N->getOperand(0), Lo, Hi);
1844
EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1846
if (EVT.bitsLE(Lo.getValueType())) {
1847
// sext_inreg the low part if needed.
1848
Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
1851
// The high part gets the sign extension from the lo-part. This handles
1852
// things like sextinreg V:i64 from i8.
1853
Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
1854
DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
1855
TLI.getPointerTy()));
1857
// For example, extension of an i48 to an i64. Leave the low part alone,
1858
// sext_inreg the high part.
1859
unsigned ExcessBits =
1860
EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
1861
Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
1862
DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), ExcessBits)));
1866
void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
1867
SDValue &Lo, SDValue &Hi) {
1868
EVT VT = N->getValueType(0);
1869
DebugLoc dl = N->getDebugLoc();
1871
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1873
LC = RTLIB::SREM_I16;
1874
else if (VT == MVT::i32)
1875
LC = RTLIB::SREM_I32;
1876
else if (VT == MVT::i64)
1877
LC = RTLIB::SREM_I64;
1878
else if (VT == MVT::i128)
1879
LC = RTLIB::SREM_I128;
1880
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1882
SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1883
SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
1886
void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
1887
SDValue &Lo, SDValue &Hi) {
1888
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1889
DebugLoc dl = N->getDebugLoc();
1890
Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
1891
Hi = DAG.getNode(ISD::SRL, dl,
1892
N->getOperand(0).getValueType(), N->getOperand(0),
1893
DAG.getConstant(NVT.getSizeInBits(), TLI.getPointerTy()));
1894
Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
1897
void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
1898
SDValue &Lo, SDValue &Hi) {
1899
EVT VT = N->getValueType(0);
1900
DebugLoc dl = N->getDebugLoc();
1902
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1904
LC = RTLIB::UDIV_I16;
1905
else if (VT == MVT::i32)
1906
LC = RTLIB::UDIV_I32;
1907
else if (VT == MVT::i64)
1908
LC = RTLIB::UDIV_I64;
1909
else if (VT == MVT::i128)
1910
LC = RTLIB::UDIV_I128;
1911
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
1913
SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1914
SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
1917
void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
1918
SDValue &Lo, SDValue &Hi) {
1919
EVT VT = N->getValueType(0);
1920
DebugLoc dl = N->getDebugLoc();
1922
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1924
LC = RTLIB::UREM_I16;
1925
else if (VT == MVT::i32)
1926
LC = RTLIB::UREM_I32;
1927
else if (VT == MVT::i64)
1928
LC = RTLIB::UREM_I64;
1929
else if (VT == MVT::i128)
1930
LC = RTLIB::UREM_I128;
1931
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
1933
SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1934
SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
1937
void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
1938
SDValue &Lo, SDValue &Hi) {
1939
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1940
DebugLoc dl = N->getDebugLoc();
1941
SDValue Op = N->getOperand(0);
1942
if (Op.getValueType().bitsLE(NVT)) {
1943
// The low part is zero extension of the input (degenerates to a copy).
1944
Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
1945
Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
1947
// For example, extension of an i48 to an i64. The operand type necessarily
1948
// promotes to the result type, so will end up being expanded too.
1949
assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1950
"Only know how to promote this result!");
1951
SDValue Res = GetPromotedInteger(Op);
1952
assert(Res.getValueType() == N->getValueType(0) &&
1953
"Operand over promoted?");
1954
// Split the promoted operand. This will simplify when it is expanded.
1955
SplitInteger(Res, Lo, Hi);
1956
unsigned ExcessBits =
1957
Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1958
Hi = DAG.getZeroExtendInReg(Hi, dl, EVT::getIntegerVT(*DAG.getContext(), ExcessBits));
1963
//===----------------------------------------------------------------------===//
1964
// Integer Operand Expansion
1965
//===----------------------------------------------------------------------===//
1967
/// ExpandIntegerOperand - This method is called when the specified operand of
1968
/// the specified node is found to need expansion. At this point, all of the
1969
/// result types of the node are known to be legal, but other operands of the
1970
/// node may need promotion or expansion as well as the specified one.
1971
bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
1972
DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG); dbgs() << "\n");
1973
SDValue Res = SDValue();
1975
if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
1978
switch (N->getOpcode()) {
1981
dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": ";
1982
N->dump(&DAG); dbgs() << "\n";
1984
llvm_unreachable("Do not know how to expand this operator's operand!");
1986
case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break;
1987
case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
1988
case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
1989
case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
1990
case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
1991
case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
1992
case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
1993
case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
1994
case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
1995
case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
1996
case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
1997
case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
2003
case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
2004
case ISD::RETURNADDR:
2005
case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
2008
// If the result is null, the sub-method took care of registering results etc.
2009
if (!Res.getNode()) return false;
2011
// If the result is N, the sub-method updated N in place. Tell the legalizer
2013
if (Res.getNode() == N)
2016
assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2017
"Invalid operand expansion");
2019
ReplaceValueWith(SDValue(N, 0), Res);
2023
/// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
2024
/// is shared among BR_CC, SELECT_CC, and SETCC handlers.
2025
void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
2027
ISD::CondCode &CCCode,
2029
SDValue LHSLo, LHSHi, RHSLo, RHSHi;
2030
GetExpandedInteger(NewLHS, LHSLo, LHSHi);
2031
GetExpandedInteger(NewRHS, RHSLo, RHSHi);
2033
if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
2034
if (RHSLo == RHSHi) {
2035
if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
2036
if (RHSCST->isAllOnesValue()) {
2037
// Equality comparison to -1.
2038
NewLHS = DAG.getNode(ISD::AND, dl,
2039
LHSLo.getValueType(), LHSLo, LHSHi);
2046
NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
2047
NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
2048
NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
2049
NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2053
// If this is a comparison of the sign bit, just look at the top part.
2055
if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
2056
if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
2057
(CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
2063
// FIXME: This generated code sucks.
2064
ISD::CondCode LowCC;
2066
default: llvm_unreachable("Unknown integer setcc!");
2068
case ISD::SETULT: LowCC = ISD::SETULT; break;
2070
case ISD::SETUGT: LowCC = ISD::SETUGT; break;
2072
case ISD::SETULE: LowCC = ISD::SETULE; break;
2074
case ISD::SETUGE: LowCC = ISD::SETUGE; break;
2077
// Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
2078
// Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
2079
// dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2081
// NOTE: on targets without efficient SELECT of bools, we can always use
2082
// this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
2083
TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, true, NULL);
2085
Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
2086
LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
2087
if (!Tmp1.getNode())
2088
Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
2089
LHSLo, RHSLo, LowCC);
2090
Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2091
LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
2092
if (!Tmp2.getNode())
2093
Tmp2 = DAG.getNode(ISD::SETCC, dl,
2094
TLI.getSetCCResultType(LHSHi.getValueType()),
2095
LHSHi, RHSHi, DAG.getCondCode(CCCode));
2097
ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
2098
ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
2099
if ((Tmp1C && Tmp1C->isNullValue()) ||
2100
(Tmp2C && Tmp2C->isNullValue() &&
2101
(CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2102
CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2103
(Tmp2C && Tmp2C->getAPIntValue() == 1 &&
2104
(CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2105
CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2106
// low part is known false, returns high part.
2107
// For LE / GE, if high part is known false, ignore the low part.
2108
// For LT / GT, if high part is known true, ignore the low part.
2114
NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2115
LHSHi, RHSHi, ISD::SETEQ, false,
2116
DagCombineInfo, dl);
2117
if (!NewLHS.getNode())
2118
NewLHS = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
2119
LHSHi, RHSHi, ISD::SETEQ);
2120
NewLHS = DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(),
2121
NewLHS, Tmp1, Tmp2);
2125
SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
2126
SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
2127
ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2128
IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2130
// If ExpandSetCCOperands returned a scalar, we need to compare the result
2131
// against zero to select between true and false values.
2132
if (NewRHS.getNode() == 0) {
2133
NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2134
CCCode = ISD::SETNE;
2137
// Update N to have the operands specified.
2138
return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
2139
DAG.getCondCode(CCCode), NewLHS, NewRHS,
2143
SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
2144
SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2145
ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2146
IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2148
// If ExpandSetCCOperands returned a scalar, we need to compare the result
2149
// against zero to select between true and false values.
2150
if (NewRHS.getNode() == 0) {
2151
NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2152
CCCode = ISD::SETNE;
2155
// Update N to have the operands specified.
2156
return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
2157
N->getOperand(2), N->getOperand(3),
2158
DAG.getCondCode(CCCode));
2161
SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2162
SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2163
ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2164
IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2166
// If ExpandSetCCOperands returned a scalar, use it.
2167
if (NewRHS.getNode() == 0) {
2168
assert(NewLHS.getValueType() == N->getValueType(0) &&
2169
"Unexpected setcc expansion!");
2173
// Otherwise, update N to have the operands specified.
2174
return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
2175
DAG.getCondCode(CCCode));
2178
SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
2179
// The value being shifted is legal, but the shift amount is too big.
2180
// It follows that either the result of the shift is undefined, or the
2181
// upper half of the shift amount is zero. Just use the lower half.
2183
GetExpandedInteger(N->getOperand(1), Lo, Hi);
2184
return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Lo);
2187
SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
2188
// The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
2189
// surely makes pretty nice problems on 8/16 bit targets. Just truncate this
2190
// constant to valid type.
2192
GetExpandedInteger(N->getOperand(0), Lo, Hi);
2193
return DAG.UpdateNodeOperands(SDValue(N, 0), Lo);
2196
SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2197
SDValue Op = N->getOperand(0);
2198
EVT DstVT = N->getValueType(0);
2199
RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
2200
assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2201
"Don't know how to expand this SINT_TO_FP!");
2202
return MakeLibCall(LC, DstVT, &Op, 1, true, N->getDebugLoc());
2205
SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2206
if (ISD::isNormalStore(N))
2207
return ExpandOp_NormalStore(N, OpNo);
2209
assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2210
assert(OpNo == 1 && "Can only expand the stored value so far");
2212
EVT VT = N->getOperand(1).getValueType();
2213
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2214
SDValue Ch = N->getChain();
2215
SDValue Ptr = N->getBasePtr();
2216
int SVOffset = N->getSrcValueOffset();
2217
unsigned Alignment = N->getAlignment();
2218
bool isVolatile = N->isVolatile();
2219
bool isNonTemporal = N->isNonTemporal();
2220
DebugLoc dl = N->getDebugLoc();
2223
assert(NVT.isByteSized() && "Expanded type not byte sized!");
2225
if (N->getMemoryVT().bitsLE(NVT)) {
2226
GetExpandedInteger(N->getValue(), Lo, Hi);
2227
return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset,
2228
N->getMemoryVT(), isVolatile, isNonTemporal,
2230
} else if (TLI.isLittleEndian()) {
2231
// Little-endian - low bits are at low addresses.
2232
GetExpandedInteger(N->getValue(), Lo, Hi);
2234
Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset,
2235
isVolatile, isNonTemporal, Alignment);
2237
unsigned ExcessBits =
2238
N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2239
EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
2241
// Increment the pointer to the other half.
2242
unsigned IncrementSize = NVT.getSizeInBits()/8;
2243
Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2244
DAG.getIntPtrConstant(IncrementSize));
2245
Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(),
2246
SVOffset+IncrementSize, NEVT,
2247
isVolatile, isNonTemporal,
2248
MinAlign(Alignment, IncrementSize));
2249
return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2251
// Big-endian - high bits are at low addresses. Favor aligned stores at
2252
// the cost of some bit-fiddling.
2253
GetExpandedInteger(N->getValue(), Lo, Hi);
2255
EVT ExtVT = N->getMemoryVT();
2256
unsigned EBytes = ExtVT.getStoreSize();
2257
unsigned IncrementSize = NVT.getSizeInBits()/8;
2258
unsigned ExcessBits = (EBytes - IncrementSize)*8;
2259
EVT HiVT = EVT::getIntegerVT(*DAG.getContext(), ExtVT.getSizeInBits() - ExcessBits);
2261
if (ExcessBits < NVT.getSizeInBits()) {
2262
// Transfer high bits from the top of Lo to the bottom of Hi.
2263
Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
2264
DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
2265
TLI.getPointerTy()));
2266
Hi = DAG.getNode(ISD::OR, dl, NVT, Hi,
2267
DAG.getNode(ISD::SRL, dl, NVT, Lo,
2268
DAG.getConstant(ExcessBits,
2269
TLI.getPointerTy())));
2272
// Store both the high bits and maybe some of the low bits.
2273
Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(),
2274
SVOffset, HiVT, isVolatile, isNonTemporal,
2277
// Increment the pointer to the other half.
2278
Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2279
DAG.getIntPtrConstant(IncrementSize));
2280
// Store the lowest ExcessBits bits in the second half.
2281
Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(),
2282
SVOffset+IncrementSize,
2283
EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
2284
isVolatile, isNonTemporal,
2285
MinAlign(Alignment, IncrementSize));
2286
return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2290
SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
2292
GetExpandedInteger(N->getOperand(0), InL, InH);
2293
// Just truncate the low part of the source.
2294
return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), InL);
2297
SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2298
SDValue Op = N->getOperand(0);
2299
EVT SrcVT = Op.getValueType();
2300
EVT DstVT = N->getValueType(0);
2301
DebugLoc dl = N->getDebugLoc();
2303
if (TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2304
// Do a signed conversion then adjust the result.
2305
SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
2306
SignedConv = TLI.LowerOperation(SignedConv, DAG);
2308
// The result of the signed conversion needs adjusting if the 'sign bit' of
2309
// the incoming integer was set. To handle this, we dynamically test to see
2310
// if it is set, and, if so, add a fudge factor.
2312
const uint64_t F32TwoE32 = 0x4F800000ULL;
2313
const uint64_t F32TwoE64 = 0x5F800000ULL;
2314
const uint64_t F32TwoE128 = 0x7F800000ULL;
2317
if (SrcVT == MVT::i32)
2318
FF = APInt(32, F32TwoE32);
2319
else if (SrcVT == MVT::i64)
2320
FF = APInt(32, F32TwoE64);
2321
else if (SrcVT == MVT::i128)
2322
FF = APInt(32, F32TwoE128);
2324
assert(false && "Unsupported UINT_TO_FP!");
2326
// Check whether the sign bit is set.
2328
GetExpandedInteger(Op, Lo, Hi);
2329
SDValue SignSet = DAG.getSetCC(dl,
2330
TLI.getSetCCResultType(Hi.getValueType()),
2331
Hi, DAG.getConstant(0, Hi.getValueType()),
2334
// Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2335
SDValue FudgePtr = DAG.getConstantPool(
2336
ConstantInt::get(*DAG.getContext(), FF.zext(64)),
2337
TLI.getPointerTy());
2339
// Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2340
SDValue Zero = DAG.getIntPtrConstant(0);
2341
SDValue Four = DAG.getIntPtrConstant(4);
2342
if (TLI.isBigEndian()) std::swap(Zero, Four);
2343
SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
2345
unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
2346
FudgePtr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), FudgePtr, Offset);
2347
Alignment = std::min(Alignment, 4u);
2349
// Load the value out, extending it from f32 to the destination float type.
2350
// FIXME: Avoid the extend by constructing the right constant pool?
2351
SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(),
2352
FudgePtr, NULL, 0, MVT::f32,
2353
false, false, Alignment);
2354
return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
2357
// Otherwise, use a libcall.
2358
RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
2359
assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2360
"Don't know how to expand this UINT_TO_FP!");
2361
return MakeLibCall(LC, DstVT, &Op, 1, true, dl);
added
removed
libclamav/c++/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
