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//====- X86InstrMMX.td - Describe the X86 Instruction Set --*- tablegen -*-===//
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// The LLVM Compiler Infrastructure
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//===----------------------------------------------------------------------===//
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// This file describes the X86 MMX instruction set, defining the instructions,
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// and properties of the instructions which are needed for code generation,
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// machine code emission, and analysis.
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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let Constraints = "$src1 = $dst" in {
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// MMXI_binop_rm - Simple MMX binary operator.
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multiclass MMXI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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ValueType OpVT, bit Commutable = 0> {
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def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
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(ins VR64:$src1, VR64:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst, (OpVT (OpNode VR64:$src1, VR64:$src2)))]> {
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let isCommutable = Commutable;
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def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
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(ins VR64:$src1, i64mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst, (OpVT (OpNode VR64:$src1,
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(load_mmx addr:$src2)))))]>;
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multiclass MMXI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
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def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
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(ins VR64:$src1, VR64:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]> {
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let isCommutable = Commutable;
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def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
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(ins VR64:$src1, i64mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst, (IntId VR64:$src1,
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(bitconvert (load_mmx addr:$src2))))]>;
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// MMXI_binop_rm_v1i64 - Simple MMX binary operator whose type is v1i64.
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// FIXME: we could eliminate this and use MMXI_binop_rm instead if tblgen knew
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// to collapse (bitconvert VT to VT) into its operand.
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multiclass MMXI_binop_rm_v1i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
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def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
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(ins VR64:$src1, VR64:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst, (v1i64 (OpNode VR64:$src1, VR64:$src2)))]> {
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let isCommutable = Commutable;
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def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
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(ins VR64:$src1, i64mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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(OpNode VR64:$src1,(load_mmx addr:$src2)))]>;
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multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
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string OpcodeStr, Intrinsic IntId,
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def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
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(ins VR64:$src1, VR64:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>;
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def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
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(ins VR64:$src1, i64mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst, (IntId VR64:$src1,
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(bitconvert (load_mmx addr:$src2))))]>;
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def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst),
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(ins VR64:$src1, i32i8imm:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst, (IntId2 VR64:$src1, (i32 imm:$src2)))]>;
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//===----------------------------------------------------------------------===//
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// MMX EMMS & FEMMS Instructions
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//===----------------------------------------------------------------------===//
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def MMX_EMMS : MMXI<0x77, RawFrm, (outs), (ins), "emms",
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[(int_x86_mmx_emms)]>;
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def MMX_FEMMS : MMXI<0x0E, RawFrm, (outs), (ins), "femms",
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[(int_x86_mmx_femms)]>;
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//===----------------------------------------------------------------------===//
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// MMX Scalar Instructions
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//===----------------------------------------------------------------------===//
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// Data Transfer Instructions
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def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
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"movd\t{$src, $dst|$dst, $src}",
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(v2i32 (scalar_to_vector GR32:$src)))]>;
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let canFoldAsLoad = 1, isReMaterializable = 1 in
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def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src),
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"movd\t{$src, $dst|$dst, $src}",
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(v2i32 (scalar_to_vector (loadi32 addr:$src))))]>;
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def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR64:$src),
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"movd\t{$src, $dst|$dst, $src}", []>;
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def MMX_MOVD64grr : MMXI<0x7E, MRMDestReg, (outs), (ins GR32:$dst, VR64:$src),
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"movd\t{$src, $dst|$dst, $src}", []>;
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def MMX_MOVQ64gmr : MMXRI<0x7E, MRMDestMem, (outs),
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(ins i64mem:$dst, VR64:$src),
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"movq\t{$src, $dst|$dst, $src}", []>;
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let neverHasSideEffects = 1 in
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def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
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"movd\t{$src, $dst|$dst, $src}",
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let neverHasSideEffects = 1 in
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// These are 64 bit moves, but since the OS X assembler doesn't
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// recognize a register-register movq, we write them as
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def MMX_MOVD64from64rr : MMXRI<0x7E, MRMDestReg,
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(outs GR64:$dst), (ins VR64:$src),
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"movd\t{$src, $dst|$dst, $src}", []>;
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def MMX_MOVD64rrv164 : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
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"movd\t{$src, $dst|$dst, $src}",
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(v1i64 (scalar_to_vector GR64:$src)))]>;
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let neverHasSideEffects = 1 in
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def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
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"movq\t{$src, $dst|$dst, $src}", []>;
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let canFoldAsLoad = 1, isReMaterializable = 1 in
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def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
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"movq\t{$src, $dst|$dst, $src}",
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[(set VR64:$dst, (load_mmx addr:$src))]>;
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def MMX_MOVQ64mr : MMXI<0x7F, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
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"movq\t{$src, $dst|$dst, $src}",
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[(store (v1i64 VR64:$src), addr:$dst)]>;
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def MMX_MOVDQ2Qrr : SDIi8<0xD6, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
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"movdq2q\t{$src, $dst|$dst, $src}",
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(i64 (vector_extract (v2i64 VR128:$src),
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def MMX_MOVQ2DQrr : SSDIi8<0xD6, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
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"movq2dq\t{$src, $dst|$dst, $src}",
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(v2i64 (scalar_to_vector (i64 (bitconvert VR64:$src))))))]>;
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let neverHasSideEffects = 1 in
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def MMX_MOVQ2FR64rr: SSDIi8<0xD6, MRMSrcReg, (outs FR64:$dst), (ins VR64:$src),
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"movq2dq\t{$src, $dst|$dst, $src}", []>;
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def MMX_MOVNTQmr : MMXI<0xE7, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
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"movntq\t{$src, $dst|$dst, $src}",
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[(int_x86_mmx_movnt_dq addr:$dst, VR64:$src)]>;
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let AddedComplexity = 15 in
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// movd to MMX register zero-extends
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def MMX_MOVZDI2PDIrr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
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"movd\t{$src, $dst|$dst, $src}",
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(v2i32 (X86vzmovl (v2i32 (scalar_to_vector GR32:$src)))))]>;
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let AddedComplexity = 20 in
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def MMX_MOVZDI2PDIrm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst),
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"movd\t{$src, $dst|$dst, $src}",
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(v2i32 (X86vzmovl (v2i32
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(scalar_to_vector (loadi32 addr:$src))))))]>;
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// Arithmetic Instructions
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defm MMX_PADDB : MMXI_binop_rm<0xFC, "paddb", add, v8i8, 1>;
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defm MMX_PADDW : MMXI_binop_rm<0xFD, "paddw", add, v4i16, 1>;
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defm MMX_PADDD : MMXI_binop_rm<0xFE, "paddd", add, v2i32, 1>;
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defm MMX_PADDQ : MMXI_binop_rm<0xD4, "paddq", add, v1i64, 1>;
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defm MMX_PADDSB : MMXI_binop_rm_int<0xEC, "paddsb" , int_x86_mmx_padds_b, 1>;
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defm MMX_PADDSW : MMXI_binop_rm_int<0xED, "paddsw" , int_x86_mmx_padds_w, 1>;
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defm MMX_PADDUSB : MMXI_binop_rm_int<0xDC, "paddusb", int_x86_mmx_paddus_b, 1>;
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defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w, 1>;
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defm MMX_PSUBB : MMXI_binop_rm<0xF8, "psubb", sub, v8i8>;
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defm MMX_PSUBW : MMXI_binop_rm<0xF9, "psubw", sub, v4i16>;
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defm MMX_PSUBD : MMXI_binop_rm<0xFA, "psubd", sub, v2i32>;
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defm MMX_PSUBQ : MMXI_binop_rm<0xFB, "psubq", sub, v1i64>;
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defm MMX_PSUBSB : MMXI_binop_rm_int<0xE8, "psubsb" , int_x86_mmx_psubs_b>;
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defm MMX_PSUBSW : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w>;
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defm MMX_PSUBUSB : MMXI_binop_rm_int<0xD8, "psubusb", int_x86_mmx_psubus_b>;
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defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD9, "psubusw", int_x86_mmx_psubus_w>;
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defm MMX_PMULLW : MMXI_binop_rm<0xD5, "pmullw", mul, v4i16, 1>;
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defm MMX_PMULHW : MMXI_binop_rm_int<0xE5, "pmulhw", int_x86_mmx_pmulh_w, 1>;
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defm MMX_PMULHUW : MMXI_binop_rm_int<0xE4, "pmulhuw", int_x86_mmx_pmulhu_w, 1>;
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defm MMX_PMULUDQ : MMXI_binop_rm_int<0xF4, "pmuludq", int_x86_mmx_pmulu_dq, 1>;
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defm MMX_PMADDWD : MMXI_binop_rm_int<0xF5, "pmaddwd", int_x86_mmx_pmadd_wd, 1>;
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defm MMX_PAVGB : MMXI_binop_rm_int<0xE0, "pavgb", int_x86_mmx_pavg_b, 1>;
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defm MMX_PAVGW : MMXI_binop_rm_int<0xE3, "pavgw", int_x86_mmx_pavg_w, 1>;
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defm MMX_PMINUB : MMXI_binop_rm_int<0xDA, "pminub", int_x86_mmx_pminu_b, 1>;
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defm MMX_PMINSW : MMXI_binop_rm_int<0xEA, "pminsw", int_x86_mmx_pmins_w, 1>;
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defm MMX_PMAXUB : MMXI_binop_rm_int<0xDE, "pmaxub", int_x86_mmx_pmaxu_b, 1>;
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defm MMX_PMAXSW : MMXI_binop_rm_int<0xEE, "pmaxsw", int_x86_mmx_pmaxs_w, 1>;
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defm MMX_PSADBW : MMXI_binop_rm_int<0xF6, "psadbw", int_x86_mmx_psad_bw, 1>;
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// Logical Instructions
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defm MMX_PAND : MMXI_binop_rm_v1i64<0xDB, "pand", and, 1>;
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defm MMX_POR : MMXI_binop_rm_v1i64<0xEB, "por" , or, 1>;
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defm MMX_PXOR : MMXI_binop_rm_v1i64<0xEF, "pxor", xor, 1>;
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let Constraints = "$src1 = $dst" in {
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def MMX_PANDNrr : MMXI<0xDF, MRMSrcReg,
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(outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
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"pandn\t{$src2, $dst|$dst, $src2}",
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[(set VR64:$dst, (v1i64 (and (vnot VR64:$src1),
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def MMX_PANDNrm : MMXI<0xDF, MRMSrcMem,
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(outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
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"pandn\t{$src2, $dst|$dst, $src2}",
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[(set VR64:$dst, (v1i64 (and (vnot VR64:$src1),
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(load addr:$src2))))]>;
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// Shift Instructions
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defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
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int_x86_mmx_psrl_w, int_x86_mmx_psrli_w>;
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defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
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int_x86_mmx_psrl_d, int_x86_mmx_psrli_d>;
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defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
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int_x86_mmx_psrl_q, int_x86_mmx_psrli_q>;
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defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
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int_x86_mmx_psll_w, int_x86_mmx_pslli_w>;
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defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
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int_x86_mmx_psll_d, int_x86_mmx_pslli_d>;
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defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
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int_x86_mmx_psll_q, int_x86_mmx_pslli_q>;
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defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
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int_x86_mmx_psra_w, int_x86_mmx_psrai_w>;
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defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
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int_x86_mmx_psra_d, int_x86_mmx_psrai_d>;
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// Shift up / down and insert zero's.
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def : Pat<(v1i64 (X86vshl VR64:$src, (i8 imm:$amt))),
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(v1i64 (MMX_PSLLQri VR64:$src, imm:$amt))>;
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def : Pat<(v1i64 (X86vshr VR64:$src, (i8 imm:$amt))),
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(v1i64 (MMX_PSRLQri VR64:$src, imm:$amt))>;
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// Comparison Instructions
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defm MMX_PCMPEQB : MMXI_binop_rm_int<0x74, "pcmpeqb", int_x86_mmx_pcmpeq_b>;
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defm MMX_PCMPEQW : MMXI_binop_rm_int<0x75, "pcmpeqw", int_x86_mmx_pcmpeq_w>;
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defm MMX_PCMPEQD : MMXI_binop_rm_int<0x76, "pcmpeqd", int_x86_mmx_pcmpeq_d>;
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defm MMX_PCMPGTB : MMXI_binop_rm_int<0x64, "pcmpgtb", int_x86_mmx_pcmpgt_b>;
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defm MMX_PCMPGTW : MMXI_binop_rm_int<0x65, "pcmpgtw", int_x86_mmx_pcmpgt_w>;
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defm MMX_PCMPGTD : MMXI_binop_rm_int<0x66, "pcmpgtd", int_x86_mmx_pcmpgt_d>;
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// Conversion Instructions
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// -- Unpack Instructions
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let Constraints = "$src1 = $dst" in {
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// Unpack High Packed Data Instructions
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def MMX_PUNPCKHBWrr : MMXI<0x68, MRMSrcReg,
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(outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
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"punpckhbw\t{$src2, $dst|$dst, $src2}",
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(v8i8 (mmx_unpckh VR64:$src1, VR64:$src2)))]>;
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def MMX_PUNPCKHBWrm : MMXI<0x68, MRMSrcMem,
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(outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
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"punpckhbw\t{$src2, $dst|$dst, $src2}",
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(v8i8 (mmx_unpckh VR64:$src1,
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(bc_v8i8 (load_mmx addr:$src2)))))]>;
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def MMX_PUNPCKHWDrr : MMXI<0x69, MRMSrcReg,
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(outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
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"punpckhwd\t{$src2, $dst|$dst, $src2}",
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(v4i16 (mmx_unpckh VR64:$src1, VR64:$src2)))]>;
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def MMX_PUNPCKHWDrm : MMXI<0x69, MRMSrcMem,
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(outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
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"punpckhwd\t{$src2, $dst|$dst, $src2}",
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(v4i16 (mmx_unpckh VR64:$src1,
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(bc_v4i16 (load_mmx addr:$src2)))))]>;
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def MMX_PUNPCKHDQrr : MMXI<0x6A, MRMSrcReg,
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(outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
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"punpckhdq\t{$src2, $dst|$dst, $src2}",
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(v2i32 (mmx_unpckh VR64:$src1, VR64:$src2)))]>;
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def MMX_PUNPCKHDQrm : MMXI<0x6A, MRMSrcMem,
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(outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
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"punpckhdq\t{$src2, $dst|$dst, $src2}",
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(v2i32 (mmx_unpckh VR64:$src1,
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(bc_v2i32 (load_mmx addr:$src2)))))]>;
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// Unpack Low Packed Data Instructions
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def MMX_PUNPCKLBWrr : MMXI<0x60, MRMSrcReg,
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(outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
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"punpcklbw\t{$src2, $dst|$dst, $src2}",
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(v8i8 (mmx_unpckl VR64:$src1, VR64:$src2)))]>;
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def MMX_PUNPCKLBWrm : MMXI<0x60, MRMSrcMem,
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(outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
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"punpcklbw\t{$src2, $dst|$dst, $src2}",
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(v8i8 (mmx_unpckl VR64:$src1,
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(bc_v8i8 (load_mmx addr:$src2)))))]>;
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def MMX_PUNPCKLWDrr : MMXI<0x61, MRMSrcReg,
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(outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
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"punpcklwd\t{$src2, $dst|$dst, $src2}",
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(v4i16 (mmx_unpckl VR64:$src1, VR64:$src2)))]>;
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def MMX_PUNPCKLWDrm : MMXI<0x61, MRMSrcMem,
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(outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
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"punpcklwd\t{$src2, $dst|$dst, $src2}",
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(v4i16 (mmx_unpckl VR64:$src1,
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(bc_v4i16 (load_mmx addr:$src2)))))]>;
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def MMX_PUNPCKLDQrr : MMXI<0x62, MRMSrcReg,
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(outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
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"punpckldq\t{$src2, $dst|$dst, $src2}",
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(v2i32 (mmx_unpckl VR64:$src1, VR64:$src2)))]>;
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def MMX_PUNPCKLDQrm : MMXI<0x62, MRMSrcMem,
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(outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
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"punpckldq\t{$src2, $dst|$dst, $src2}",
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(v2i32 (mmx_unpckl VR64:$src1,
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(bc_v2i32 (load_mmx addr:$src2)))))]>;
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// -- Pack Instructions
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defm MMX_PACKSSWB : MMXI_binop_rm_int<0x63, "packsswb", int_x86_mmx_packsswb>;
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defm MMX_PACKSSDW : MMXI_binop_rm_int<0x6B, "packssdw", int_x86_mmx_packssdw>;
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defm MMX_PACKUSWB : MMXI_binop_rm_int<0x67, "packuswb", int_x86_mmx_packuswb>;
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// -- Shuffle Instructions
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def MMX_PSHUFWri : MMXIi8<0x70, MRMSrcReg,
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(outs VR64:$dst), (ins VR64:$src1, i8imm:$src2),
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"pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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(v4i16 (mmx_pshufw:$src2 VR64:$src1, (undef))))]>;
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def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem,
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(outs VR64:$dst), (ins i64mem:$src1, i8imm:$src2),
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"pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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(mmx_pshufw:$src2 (bc_v4i16 (load_mmx addr:$src1)),
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// -- Conversion Instructions
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let neverHasSideEffects = 1 in {
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def MMX_CVTPD2PIrr : MMX2I<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
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"cvtpd2pi\t{$src, $dst|$dst, $src}", []>;
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def MMX_CVTPD2PIrm : MMX2I<0x2D, MRMSrcMem, (outs VR64:$dst),
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"cvtpd2pi\t{$src, $dst|$dst, $src}", []>;
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def MMX_CVTPI2PDrr : MMX2I<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
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"cvtpi2pd\t{$src, $dst|$dst, $src}", []>;
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def MMX_CVTPI2PDrm : MMX2I<0x2A, MRMSrcMem, (outs VR128:$dst),
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"cvtpi2pd\t{$src, $dst|$dst, $src}", []>;
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def MMX_CVTPI2PSrr : MMXI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
401
"cvtpi2ps\t{$src, $dst|$dst, $src}", []>;
403
def MMX_CVTPI2PSrm : MMXI<0x2A, MRMSrcMem, (outs VR128:$dst),
405
"cvtpi2ps\t{$src, $dst|$dst, $src}", []>;
407
def MMX_CVTPS2PIrr : MMXI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
408
"cvtps2pi\t{$src, $dst|$dst, $src}", []>;
410
def MMX_CVTPS2PIrm : MMXI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
411
"cvtps2pi\t{$src, $dst|$dst, $src}", []>;
413
def MMX_CVTTPD2PIrr : MMX2I<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
414
"cvttpd2pi\t{$src, $dst|$dst, $src}", []>;
416
def MMX_CVTTPD2PIrm : MMX2I<0x2C, MRMSrcMem, (outs VR64:$dst),
418
"cvttpd2pi\t{$src, $dst|$dst, $src}", []>;
420
def MMX_CVTTPS2PIrr : MMXI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
421
"cvttps2pi\t{$src, $dst|$dst, $src}", []>;
423
def MMX_CVTTPS2PIrm : MMXI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
424
"cvttps2pi\t{$src, $dst|$dst, $src}", []>;
425
} // end neverHasSideEffects
429
def MMX_X86pinsrw : SDNode<"X86ISD::MMX_PINSRW",
430
SDTypeProfile<1, 3, [SDTCisVT<0, v4i16>, SDTCisSameAs<0,1>,
431
SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
434
def MMX_PEXTRWri : MMXIi8<0xC5, MRMSrcReg,
435
(outs GR32:$dst), (ins VR64:$src1, i16i8imm:$src2),
436
"pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
437
[(set GR32:$dst, (X86pextrw (v4i16 VR64:$src1),
438
(iPTR imm:$src2)))]>;
439
let Constraints = "$src1 = $dst" in {
440
def MMX_PINSRWrri : MMXIi8<0xC4, MRMSrcReg,
442
(ins VR64:$src1, GR32:$src2,i16i8imm:$src3),
443
"pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
444
[(set VR64:$dst, (v4i16 (MMX_X86pinsrw (v4i16 VR64:$src1),
445
GR32:$src2,(iPTR imm:$src3))))]>;
446
def MMX_PINSRWrmi : MMXIi8<0xC4, MRMSrcMem,
448
(ins VR64:$src1, i16mem:$src2, i16i8imm:$src3),
449
"pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
451
(v4i16 (MMX_X86pinsrw (v4i16 VR64:$src1),
452
(i32 (anyext (loadi16 addr:$src2))),
453
(iPTR imm:$src3))))]>;
456
// MMX to XMM for vector types
457
def MMX_X86movq2dq : SDNode<"X86ISD::MOVQ2DQ", SDTypeProfile<1, 1,
458
[SDTCisVT<0, v2i64>, SDTCisVT<1, v1i64>]>>;
460
def : Pat<(v2i64 (MMX_X86movq2dq VR64:$src)),
461
(v2i64 (MMX_MOVQ2DQrr VR64:$src))>;
463
def : Pat<(v2i64 (MMX_X86movq2dq (load_mmx addr:$src))),
464
(v2i64 (MOVQI2PQIrm addr:$src))>;
466
def : Pat<(v2i64 (MMX_X86movq2dq (v1i64 (bitconvert
467
(v2i32 (scalar_to_vector (loadi32 addr:$src))))))),
468
(v2i64 (MOVDI2PDIrm addr:$src))>;
471
def MMX_PMOVMSKBrr : MMXI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR64:$src),
472
"pmovmskb\t{$src, $dst|$dst, $src}",
473
[(set GR32:$dst, (int_x86_mmx_pmovmskb VR64:$src))]>;
477
def MMX_MASKMOVQ : MMXI<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask),
478
"maskmovq\t{$mask, $src|$src, $mask}",
479
[(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, EDI)]>;
481
def MMX_MASKMOVQ64: MMXI64<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask),
482
"maskmovq\t{$mask, $src|$src, $mask}",
483
[(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, RDI)]>;
485
//===----------------------------------------------------------------------===//
486
// Alias Instructions
487
//===----------------------------------------------------------------------===//
489
// Alias instructions that map zero vector to pxor.
490
let isReMaterializable = 1, isCodeGenOnly = 1 in {
491
// FIXME: Change encoding to pseudo.
492
def MMX_V_SET0 : MMXI<0xEF, MRMInitReg, (outs VR64:$dst), (ins), "",
493
[(set VR64:$dst, (v2i32 immAllZerosV))]>;
494
def MMX_V_SETALLONES : MMXI<0x76, MRMInitReg, (outs VR64:$dst), (ins), "",
495
[(set VR64:$dst, (v2i32 immAllOnesV))]>;
498
let Predicates = [HasMMX] in {
499
def : Pat<(v1i64 immAllZerosV), (MMX_V_SET0)>;
500
def : Pat<(v4i16 immAllZerosV), (MMX_V_SET0)>;
501
def : Pat<(v8i8 immAllZerosV), (MMX_V_SET0)>;
504
//===----------------------------------------------------------------------===//
505
// Non-Instruction Patterns
506
//===----------------------------------------------------------------------===//
508
// Store 64-bit integer vector values.
509
def : Pat<(store (v8i8 VR64:$src), addr:$dst),
510
(MMX_MOVQ64mr addr:$dst, VR64:$src)>;
511
def : Pat<(store (v4i16 VR64:$src), addr:$dst),
512
(MMX_MOVQ64mr addr:$dst, VR64:$src)>;
513
def : Pat<(store (v2i32 VR64:$src), addr:$dst),
514
(MMX_MOVQ64mr addr:$dst, VR64:$src)>;
515
def : Pat<(store (v2f32 VR64:$src), addr:$dst),
516
(MMX_MOVQ64mr addr:$dst, VR64:$src)>;
517
def : Pat<(store (v1i64 VR64:$src), addr:$dst),
518
(MMX_MOVQ64mr addr:$dst, VR64:$src)>;
521
def : Pat<(v8i8 (bitconvert (v1i64 VR64:$src))), (v8i8 VR64:$src)>;
522
def : Pat<(v8i8 (bitconvert (v2i32 VR64:$src))), (v8i8 VR64:$src)>;
523
def : Pat<(v8i8 (bitconvert (v2f32 VR64:$src))), (v8i8 VR64:$src)>;
524
def : Pat<(v8i8 (bitconvert (v4i16 VR64:$src))), (v8i8 VR64:$src)>;
525
def : Pat<(v4i16 (bitconvert (v1i64 VR64:$src))), (v4i16 VR64:$src)>;
526
def : Pat<(v4i16 (bitconvert (v2i32 VR64:$src))), (v4i16 VR64:$src)>;
527
def : Pat<(v4i16 (bitconvert (v2f32 VR64:$src))), (v4i16 VR64:$src)>;
528
def : Pat<(v4i16 (bitconvert (v8i8 VR64:$src))), (v4i16 VR64:$src)>;
529
def : Pat<(v2i32 (bitconvert (v1i64 VR64:$src))), (v2i32 VR64:$src)>;
530
def : Pat<(v2i32 (bitconvert (v2f32 VR64:$src))), (v2i32 VR64:$src)>;
531
def : Pat<(v2i32 (bitconvert (v4i16 VR64:$src))), (v2i32 VR64:$src)>;
532
def : Pat<(v2i32 (bitconvert (v8i8 VR64:$src))), (v2i32 VR64:$src)>;
533
def : Pat<(v2f32 (bitconvert (v1i64 VR64:$src))), (v2f32 VR64:$src)>;
534
def : Pat<(v2f32 (bitconvert (v2i32 VR64:$src))), (v2f32 VR64:$src)>;
535
def : Pat<(v2f32 (bitconvert (v4i16 VR64:$src))), (v2f32 VR64:$src)>;
536
def : Pat<(v2f32 (bitconvert (v8i8 VR64:$src))), (v2f32 VR64:$src)>;
537
def : Pat<(v1i64 (bitconvert (v2i32 VR64:$src))), (v1i64 VR64:$src)>;
538
def : Pat<(v1i64 (bitconvert (v2f32 VR64:$src))), (v1i64 VR64:$src)>;
539
def : Pat<(v1i64 (bitconvert (v4i16 VR64:$src))), (v1i64 VR64:$src)>;
540
def : Pat<(v1i64 (bitconvert (v8i8 VR64:$src))), (v1i64 VR64:$src)>;
542
// 64-bit bit convert.
543
def : Pat<(v1i64 (bitconvert (i64 GR64:$src))),
544
(MMX_MOVD64to64rr GR64:$src)>;
545
def : Pat<(v2i32 (bitconvert (i64 GR64:$src))),
546
(MMX_MOVD64to64rr GR64:$src)>;
547
def : Pat<(v2f32 (bitconvert (i64 GR64:$src))),
548
(MMX_MOVD64to64rr GR64:$src)>;
549
def : Pat<(v4i16 (bitconvert (i64 GR64:$src))),
550
(MMX_MOVD64to64rr GR64:$src)>;
551
def : Pat<(v8i8 (bitconvert (i64 GR64:$src))),
552
(MMX_MOVD64to64rr GR64:$src)>;
553
def : Pat<(i64 (bitconvert (v1i64 VR64:$src))),
554
(MMX_MOVD64from64rr VR64:$src)>;
555
def : Pat<(i64 (bitconvert (v2i32 VR64:$src))),
556
(MMX_MOVD64from64rr VR64:$src)>;
557
def : Pat<(i64 (bitconvert (v2f32 VR64:$src))),
558
(MMX_MOVD64from64rr VR64:$src)>;
559
def : Pat<(i64 (bitconvert (v4i16 VR64:$src))),
560
(MMX_MOVD64from64rr VR64:$src)>;
561
def : Pat<(i64 (bitconvert (v8i8 VR64:$src))),
562
(MMX_MOVD64from64rr VR64:$src)>;
563
def : Pat<(f64 (bitconvert (v1i64 VR64:$src))),
564
(MMX_MOVQ2FR64rr VR64:$src)>;
565
def : Pat<(f64 (bitconvert (v2i32 VR64:$src))),
566
(MMX_MOVQ2FR64rr VR64:$src)>;
567
def : Pat<(f64 (bitconvert (v4i16 VR64:$src))),
568
(MMX_MOVQ2FR64rr VR64:$src)>;
569
def : Pat<(f64 (bitconvert (v8i8 VR64:$src))),
570
(MMX_MOVQ2FR64rr VR64:$src)>;
572
let AddedComplexity = 20 in {
573
def : Pat<(v2i32 (X86vzmovl (bc_v2i32 (load_mmx addr:$src)))),
574
(MMX_MOVZDI2PDIrm addr:$src)>;
578
let AddedComplexity = 15 in {
579
def : Pat<(v2i32 (X86vzmovl VR64:$src)),
580
(MMX_PUNPCKLDQrr VR64:$src, (MMX_V_SET0))>;
583
// Patterns to perform canonical versions of vector shuffling.
584
let AddedComplexity = 10 in {
585
def : Pat<(v8i8 (mmx_unpckl_undef VR64:$src, (undef))),
586
(MMX_PUNPCKLBWrr VR64:$src, VR64:$src)>;
587
def : Pat<(v4i16 (mmx_unpckl_undef VR64:$src, (undef))),
588
(MMX_PUNPCKLWDrr VR64:$src, VR64:$src)>;
589
def : Pat<(v2i32 (mmx_unpckl_undef VR64:$src, (undef))),
590
(MMX_PUNPCKLDQrr VR64:$src, VR64:$src)>;
593
let AddedComplexity = 10 in {
594
def : Pat<(v8i8 (mmx_unpckh_undef VR64:$src, (undef))),
595
(MMX_PUNPCKHBWrr VR64:$src, VR64:$src)>;
596
def : Pat<(v4i16 (mmx_unpckh_undef VR64:$src, (undef))),
597
(MMX_PUNPCKHWDrr VR64:$src, VR64:$src)>;
598
def : Pat<(v2i32 (mmx_unpckh_undef VR64:$src, (undef))),
599
(MMX_PUNPCKHDQrr VR64:$src, VR64:$src)>;
602
// Some special case PANDN patterns.
603
// FIXME: Get rid of these.
604
def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v2i32 immAllOnesV))),
606
(MMX_PANDNrr VR64:$src1, VR64:$src2)>;
607
def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v4i16 immAllOnesV_bc))),
609
(MMX_PANDNrr VR64:$src1, VR64:$src2)>;
610
def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v8i8 immAllOnesV_bc))),
612
(MMX_PANDNrr VR64:$src1, VR64:$src2)>;
614
def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v2i32 immAllOnesV))),
616
(MMX_PANDNrm VR64:$src1, addr:$src2)>;
617
def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v4i16 immAllOnesV_bc))),
619
(MMX_PANDNrm VR64:$src1, addr:$src2)>;
620
def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v8i8 immAllOnesV_bc))),
622
(MMX_PANDNrm VR64:$src1, addr:$src2)>;
624
// Move MMX to lower 64-bit of XMM
625
def : Pat<(v2i64 (scalar_to_vector (i64 (bitconvert (v8i8 VR64:$src))))),
626
(v2i64 (MMX_MOVQ2DQrr VR64:$src))>;
627
def : Pat<(v2i64 (scalar_to_vector (i64 (bitconvert (v4i16 VR64:$src))))),
628
(v2i64 (MMX_MOVQ2DQrr VR64:$src))>;
629
def : Pat<(v2i64 (scalar_to_vector (i64 (bitconvert (v2i32 VR64:$src))))),
630
(v2i64 (MMX_MOVQ2DQrr VR64:$src))>;
631
def : Pat<(v2i64 (scalar_to_vector (i64 (bitconvert (v1i64 VR64:$src))))),
632
(v2i64 (MMX_MOVQ2DQrr VR64:$src))>;
634
// Move lower 64-bit of XMM to MMX.
635
def : Pat<(v2i32 (bitconvert (i64 (vector_extract (v2i64 VR128:$src),
637
(v2i32 (MMX_MOVDQ2Qrr VR128:$src))>;
638
def : Pat<(v4i16 (bitconvert (i64 (vector_extract (v2i64 VR128:$src),
640
(v4i16 (MMX_MOVDQ2Qrr VR128:$src))>;
641
def : Pat<(v8i8 (bitconvert (i64 (vector_extract (v2i64 VR128:$src),
643
(v8i8 (MMX_MOVDQ2Qrr VR128:$src))>;
645
// Patterns for vector comparisons
646
def : Pat<(v8i8 (X86pcmpeqb VR64:$src1, VR64:$src2)),
647
(MMX_PCMPEQBrr VR64:$src1, VR64:$src2)>;
648
def : Pat<(v8i8 (X86pcmpeqb VR64:$src1, (bitconvert (load_mmx addr:$src2)))),
649
(MMX_PCMPEQBrm VR64:$src1, addr:$src2)>;
650
def : Pat<(v4i16 (X86pcmpeqw VR64:$src1, VR64:$src2)),
651
(MMX_PCMPEQWrr VR64:$src1, VR64:$src2)>;
652
def : Pat<(v4i16 (X86pcmpeqw VR64:$src1, (bitconvert (load_mmx addr:$src2)))),
653
(MMX_PCMPEQWrm VR64:$src1, addr:$src2)>;
654
def : Pat<(v2i32 (X86pcmpeqd VR64:$src1, VR64:$src2)),
655
(MMX_PCMPEQDrr VR64:$src1, VR64:$src2)>;
656
def : Pat<(v2i32 (X86pcmpeqd VR64:$src1, (bitconvert (load_mmx addr:$src2)))),
657
(MMX_PCMPEQDrm VR64:$src1, addr:$src2)>;
659
def : Pat<(v8i8 (X86pcmpgtb VR64:$src1, VR64:$src2)),
660
(MMX_PCMPGTBrr VR64:$src1, VR64:$src2)>;
661
def : Pat<(v8i8 (X86pcmpgtb VR64:$src1, (bitconvert (load_mmx addr:$src2)))),
662
(MMX_PCMPGTBrm VR64:$src1, addr:$src2)>;
663
def : Pat<(v4i16 (X86pcmpgtw VR64:$src1, VR64:$src2)),
664
(MMX_PCMPGTWrr VR64:$src1, VR64:$src2)>;
665
def : Pat<(v4i16 (X86pcmpgtw VR64:$src1, (bitconvert (load_mmx addr:$src2)))),
666
(MMX_PCMPGTWrm VR64:$src1, addr:$src2)>;
667
def : Pat<(v2i32 (X86pcmpgtd VR64:$src1, VR64:$src2)),
668
(MMX_PCMPGTDrr VR64:$src1, VR64:$src2)>;
669
def : Pat<(v2i32 (X86pcmpgtd VR64:$src1, (bitconvert (load_mmx addr:$src2)))),
670
(MMX_PCMPGTDrm VR64:$src1, addr:$src2)>;
672
// CMOV* - Used to implement the SELECT DAG operation. Expanded after
673
// instruction selection into a branch sequence.
674
let Uses = [EFLAGS], usesCustomInserter = 1 in {
675
def CMOV_V1I64 : I<0, Pseudo,
676
(outs VR64:$dst), (ins VR64:$t, VR64:$f, i8imm:$cond),
677
"#CMOV_V1I64 PSEUDO!",
679
(v1i64 (X86cmov VR64:$t, VR64:$f, imm:$cond,