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//===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
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// The LLVM Compiler Infrastructure
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//===----------------------------------------------------------------------===//
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// This tablegen backend is responsible for emitting a description of a target
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// register file for a code generator. It uses instances of the Register,
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// RegisterAliases, and RegisterClass classes to gather this information.
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//===----------------------------------------------------------------------===//
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#include "RegisterInfoEmitter.h"
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#include "CodeGenTarget.h"
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#include "CodeGenRegisters.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/ADT/STLExtras.h"
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// runEnums - Print out enum values for all of the registers.
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void RegisterInfoEmitter::runEnums(raw_ostream &OS) {
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const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
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std::string Namespace = Registers[0].TheDef->getValueAsString("Namespace");
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EmitSourceFileHeader("Target Register Enum Values", OS);
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OS << "namespace llvm {\n\n";
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if (!Namespace.empty())
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OS << "namespace " << Namespace << " {\n";
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OS << " enum {\n NoRegister,\n";
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for (unsigned i = 0, e = Registers.size(); i != e; ++i)
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OS << " " << Registers[i].getName() << ", \t// " << i+1 << "\n";
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OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
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if (!Namespace.empty())
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OS << "} // End llvm namespace \n";
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void RegisterInfoEmitter::runHeader(raw_ostream &OS) {
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EmitSourceFileHeader("Register Information Header Fragment", OS);
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const std::string &TargetName = Target.getName();
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std::string ClassName = TargetName + "GenRegisterInfo";
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OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n";
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OS << "#include <string>\n\n";
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OS << "namespace llvm {\n\n";
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OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
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<< " explicit " << ClassName
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<< "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
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<< " virtual int getDwarfRegNumFull(unsigned RegNum, "
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<< "unsigned Flavour) const;\n"
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<< " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n"
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<< " virtual bool needsStackRealignment(const MachineFunction &) const\n"
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<< " { return false; }\n"
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<< " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n"
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<< " unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;\n"
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const std::vector<CodeGenRegisterClass> &RegisterClasses =
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Target.getRegisterClasses();
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if (!RegisterClasses.empty()) {
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OS << "namespace " << RegisterClasses[0].Namespace
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<< " { // Register classes\n";
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for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
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OS << " " << RegisterClasses[i].getName() << "RegClassID";
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for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
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const std::string &Name = RegisterClasses[i].getName();
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// Output the register class definition.
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OS << " struct " << Name << "Class : public TargetRegisterClass {\n"
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<< " " << Name << "Class();\n"
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<< RegisterClasses[i].MethodProtos << " };\n";
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// Output the extern for the instance.
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OS << " extern " << Name << "Class\t" << Name << "RegClass;\n";
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// Output the extern for the pointer to the instance (should remove).
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OS << " static TargetRegisterClass * const "<< Name <<"RegisterClass = &"
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<< Name << "RegClass;\n";
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OS << "} // end of namespace " << TargetName << "\n\n";
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OS << "} // End llvm namespace \n";
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bool isSubRegisterClass(const CodeGenRegisterClass &RC,
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std::set<Record*> &RegSet) {
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for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
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Record *Reg = RC.Elements[i];
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if (!RegSet.count(Reg))
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static void addSuperReg(Record *R, Record *S,
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std::map<Record*, std::set<Record*>, LessRecord> &SubRegs,
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std::map<Record*, std::set<Record*>, LessRecord> &SuperRegs,
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std::map<Record*, std::set<Record*>, LessRecord> &Aliases) {
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errs() << "Error: recursive sub-register relationship between"
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<< " register " << getQualifiedName(R)
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<< " and its sub-registers?\n";
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if (!SuperRegs[R].insert(S).second)
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SubRegs[S].insert(R);
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Aliases[R].insert(S);
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Aliases[S].insert(R);
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if (SuperRegs.count(S))
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for (std::set<Record*>::iterator I = SuperRegs[S].begin(),
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E = SuperRegs[S].end(); I != E; ++I)
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addSuperReg(R, *I, SubRegs, SuperRegs, Aliases);
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static void addSubSuperReg(Record *R, Record *S,
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std::map<Record*, std::set<Record*>, LessRecord> &SubRegs,
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std::map<Record*, std::set<Record*>, LessRecord> &SuperRegs,
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std::map<Record*, std::set<Record*>, LessRecord> &Aliases) {
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errs() << "Error: recursive sub-register relationship between"
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<< " register " << getQualifiedName(R)
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<< " and its sub-registers?\n";
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if (!SubRegs[R].insert(S).second)
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addSuperReg(S, R, SubRegs, SuperRegs, Aliases);
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Aliases[R].insert(S);
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Aliases[S].insert(R);
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if (SubRegs.count(S))
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for (std::set<Record*>::iterator I = SubRegs[S].begin(),
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E = SubRegs[S].end(); I != E; ++I)
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addSubSuperReg(R, *I, SubRegs, SuperRegs, Aliases);
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class RegisterSorter {
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std::map<Record*, std::set<Record*>, LessRecord> &RegisterSubRegs;
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RegisterSorter(std::map<Record*, std::set<Record*>, LessRecord> &RS)
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: RegisterSubRegs(RS) {}
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bool operator()(Record *RegA, Record *RegB) {
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// B is sub-register of A.
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return RegisterSubRegs.count(RegA) && RegisterSubRegs[RegA].count(RegB);
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// RegisterInfoEmitter::run - Main register file description emitter.
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void RegisterInfoEmitter::run(raw_ostream &OS) {
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CodeGenTarget Target;
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EmitSourceFileHeader("Register Information Source Fragment", OS);
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OS << "namespace llvm {\n\n";
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// Start out by emitting each of the register classes... to do this, we build
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// a set of registers which belong to a register class, this is to ensure that
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// each register is only in a single register class.
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const std::vector<CodeGenRegisterClass> &RegisterClasses =
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Target.getRegisterClasses();
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// Loop over all of the register classes... emitting each one.
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OS << "namespace { // Register classes...\n";
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// RegClassesBelongedTo - Keep track of which register classes each reg
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std::multimap<Record*, const CodeGenRegisterClass*> RegClassesBelongedTo;
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// Emit the register enum value arrays for each RegisterClass
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for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
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const CodeGenRegisterClass &RC = RegisterClasses[rc];
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// Give the register class a legal C name if it's anonymous.
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std::string Name = RC.TheDef->getName();
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// Emit the register list now.
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OS << " // " << Name << " Register Class...\n"
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<< " static const unsigned " << Name
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for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
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Record *Reg = RC.Elements[i];
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OS << getQualifiedName(Reg) << ", ";
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// Keep track of which regclasses this register is in.
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RegClassesBelongedTo.insert(std::make_pair(Reg, &RC));
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// Emit the ValueType arrays for each RegisterClass
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for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
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const CodeGenRegisterClass &RC = RegisterClasses[rc];
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// Give the register class a legal C name if it's anonymous.
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std::string Name = RC.TheDef->getName() + "VTs";
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// Emit the register list now.
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<< " Register Class Value Types...\n"
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<< " static const EVT " << Name
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for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
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OS << getEnumName(RC.VTs[i]) << ", ";
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OS << "MVT::Other\n };\n\n";
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OS << "} // end anonymous namespace\n\n";
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// Now that all of the structs have been emitted, emit the instances.
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if (!RegisterClasses.empty()) {
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OS << "namespace " << RegisterClasses[0].Namespace
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<< " { // Register class instances\n";
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for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
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OS << " " << RegisterClasses[i].getName() << "Class\t"
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<< RegisterClasses[i].getName() << "RegClass;\n";
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std::map<unsigned, std::set<unsigned> > SuperClassMap;
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std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
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// Emit the sub-register classes for each RegisterClass
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for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
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const CodeGenRegisterClass &RC = RegisterClasses[rc];
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// Give the register class a legal C name if it's anonymous.
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std::string Name = RC.TheDef->getName();
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<< " Sub-register Classes...\n"
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<< " static const TargetRegisterClass* const "
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<< Name << "SubRegClasses[] = {\n ";
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for (unsigned subrc = 0, subrcMax = RC.SubRegClasses.size();
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subrc != subrcMax; ++subrc) {
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unsigned rc2 = 0, e2 = RegisterClasses.size();
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for (; rc2 != e2; ++rc2) {
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const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
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if (RC.SubRegClasses[subrc]->getName() == RC2.getName()) {
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OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
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std::map<unsigned, std::set<unsigned> >::iterator SCMI =
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SuperRegClassMap.find(rc2);
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if (SCMI == SuperRegClassMap.end()) {
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SuperRegClassMap.insert(std::make_pair(rc2,
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std::set<unsigned>()));
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SCMI = SuperRegClassMap.find(rc2);
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SCMI->second.insert(rc);
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throw "Register Class member '" +
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RC.SubRegClasses[subrc]->getName() +
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"' is not a valid RegisterClass!";
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OS << (!Empty ? ", " : "") << "NULL";
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// Emit the super-register classes for each RegisterClass
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for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
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const CodeGenRegisterClass &RC = RegisterClasses[rc];
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// Give the register class a legal C name if it's anonymous.
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std::string Name = RC.TheDef->getName();
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<< " Super-register Classes...\n"
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<< " static const TargetRegisterClass* const "
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<< Name << "SuperRegClasses[] = {\n ";
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std::map<unsigned, std::set<unsigned> >::iterator I =
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SuperRegClassMap.find(rc);
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if (I != SuperRegClassMap.end()) {
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for (std::set<unsigned>::iterator II = I->second.begin(),
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EE = I->second.end(); II != EE; ++II) {
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const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
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OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
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OS << (!Empty ? ", " : "") << "NULL";
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// Emit the sub-classes array for each RegisterClass
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for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
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const CodeGenRegisterClass &RC = RegisterClasses[rc];
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// Give the register class a legal C name if it's anonymous.
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std::string Name = RC.TheDef->getName();
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std::set<Record*> RegSet;
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for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
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Record *Reg = RC.Elements[i];
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<< " Register Class sub-classes...\n"
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<< " static const TargetRegisterClass* const "
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<< Name << "Subclasses[] = {\n ";
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for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
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const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
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// RC2 is a sub-class of RC if it is a valid replacement for any
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// instruction operand where an RC register is required. It must satisfy
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// 1. All RC2 registers are also in RC.
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// 2. The RC2 spill size must not be smaller that the RC spill size.
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// 3. RC2 spill alignment must be compatible with RC.
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// Sub-classes are used to determine if a virtual register can be used
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// as an instruction operand, or if it must be copied first.
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if (rc == rc2 || RC2.Elements.size() > RC.Elements.size() ||
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(RC.SpillAlignment && RC2.SpillAlignment % RC.SpillAlignment) ||
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RC.SpillSize > RC2.SpillSize || !isSubRegisterClass(RC2, RegSet))
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if (!Empty) OS << ", ";
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OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
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std::map<unsigned, std::set<unsigned> >::iterator SCMI =
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SuperClassMap.find(rc2);
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if (SCMI == SuperClassMap.end()) {
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SuperClassMap.insert(std::make_pair(rc2, std::set<unsigned>()));
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SCMI = SuperClassMap.find(rc2);
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SCMI->second.insert(rc);
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OS << (!Empty ? ", " : "") << "NULL";
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for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
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const CodeGenRegisterClass &RC = RegisterClasses[rc];
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// Give the register class a legal C name if it's anonymous.
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std::string Name = RC.TheDef->getName();
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<< " Register Class super-classes...\n"
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<< " static const TargetRegisterClass* const "
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<< Name << "Superclasses[] = {\n ";
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std::map<unsigned, std::set<unsigned> >::iterator I =
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SuperClassMap.find(rc);
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if (I != SuperClassMap.end()) {
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for (std::set<unsigned>::iterator II = I->second.begin(),
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EE = I->second.end(); II != EE; ++II) {
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const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
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if (!Empty) OS << ", ";
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OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
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OS << (!Empty ? ", " : "") << "NULL";
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for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
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const CodeGenRegisterClass &RC = RegisterClasses[i];
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OS << RC.MethodBodies << "\n";
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OS << RC.getName() << "Class::" << RC.getName()
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<< "Class() : TargetRegisterClass("
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<< RC.getName() + "RegClassID" << ", "
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<< '\"' << RC.getName() << "\", "
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<< RC.getName() + "VTs" << ", "
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<< RC.getName() + "Subclasses" << ", "
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<< RC.getName() + "Superclasses" << ", "
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<< RC.getName() + "SubRegClasses" << ", "
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<< RC.getName() + "SuperRegClasses" << ", "
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<< RC.SpillSize/8 << ", "
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<< RC.SpillAlignment/8 << ", "
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<< RC.CopyCost << ", "
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<< RC.getName() << ", " << RC.getName() << " + " << RC.Elements.size()
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OS << "\nnamespace {\n";
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OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
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for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
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OS << " &" << getQualifiedName(RegisterClasses[i].TheDef)
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// Emit register sub-registers / super-registers, aliases...
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std::map<Record*, std::set<Record*>, LessRecord> RegisterSubRegs;
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std::map<Record*, std::set<Record*>, LessRecord> RegisterSuperRegs;
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std::map<Record*, std::set<Record*>, LessRecord> RegisterAliases;
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std::map<Record*, std::vector<std::pair<int, Record*> > > SubRegVectors;
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typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
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DwarfRegNumsMapTy DwarfRegNums;
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const std::vector<CodeGenRegister> &Regs = Target.getRegisters();
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for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
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Record *R = Regs[i].TheDef;
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std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("Aliases");
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// Add information that R aliases all of the elements in the list... and
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// that everything in the list aliases R.
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for (unsigned j = 0, e = LI.size(); j != e; ++j) {
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if (RegisterAliases[R].count(Reg))
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errs() << "Warning: register alias between " << getQualifiedName(R)
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<< " and " << getQualifiedName(Reg)
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<< " specified multiple times!\n";
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RegisterAliases[R].insert(Reg);
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if (RegisterAliases[Reg].count(R))
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errs() << "Warning: register alias between " << getQualifiedName(R)
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<< " and " << getQualifiedName(Reg)
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<< " specified multiple times!\n";
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RegisterAliases[Reg].insert(R);
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// Process sub-register sets.
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for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
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Record *R = Regs[i].TheDef;
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std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("SubRegs");
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// Process sub-register set and add aliases information.
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for (unsigned j = 0, e = LI.size(); j != e; ++j) {
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Record *SubReg = LI[j];
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if (RegisterSubRegs[R].count(SubReg))
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errs() << "Warning: register " << getQualifiedName(SubReg)
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<< " specified as a sub-register of " << getQualifiedName(R)
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<< " multiple times!\n";
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addSubSuperReg(R, SubReg, RegisterSubRegs, RegisterSuperRegs,
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// Print the SubregHashTable, a simple quadratically probed
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// hash table for determining if a register is a subregister
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// of another register.
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unsigned NumSubRegs = 0;
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std::map<Record*, unsigned> RegNo;
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for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
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RegNo[Regs[i].TheDef] = i;
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NumSubRegs += RegisterSubRegs[Regs[i].TheDef].size();
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unsigned SubregHashTableSize = 2 * NextPowerOf2(2 * NumSubRegs);
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unsigned* SubregHashTable = new unsigned[2 * SubregHashTableSize];
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std::fill(SubregHashTable, SubregHashTable + 2 * SubregHashTableSize, ~0U);
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unsigned hashMisses = 0;
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for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
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Record* R = Regs[i].TheDef;
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for (std::set<Record*>::iterator I = RegisterSubRegs[R].begin(),
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E = RegisterSubRegs[R].end(); I != E; ++I) {
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// We have to increase the indices of both registers by one when
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// computing the hash because, in the generated code, there
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// will be an extra empty slot at register 0.
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size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (SubregHashTableSize-1);
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unsigned ProbeAmt = 2;
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while (SubregHashTable[index*2] != ~0U &&
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SubregHashTable[index*2+1] != ~0U) {
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index = (index + ProbeAmt) & (SubregHashTableSize-1);
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SubregHashTable[index*2] = i;
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SubregHashTable[index*2+1] = RegNo[RJ];
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OS << "\n\n // Number of hash collisions: " << hashMisses << "\n";
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if (SubregHashTableSize) {
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std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace");
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OS << " const unsigned SubregHashTable[] = { ";
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for (unsigned i = 0; i < SubregHashTableSize - 1; ++i) {
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// Insert spaces for nice formatting.
532
if (SubregHashTable[2*i] != ~0U) {
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OS << getQualifiedName(Regs[SubregHashTable[2*i]].TheDef) << ", "
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<< getQualifiedName(Regs[SubregHashTable[2*i+1]].TheDef) << ", \n";
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OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n";
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unsigned Idx = SubregHashTableSize*2-2;
541
if (SubregHashTable[Idx] != ~0U) {
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<< getQualifiedName(Regs[SubregHashTable[Idx]].TheDef) << ", "
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<< getQualifiedName(Regs[SubregHashTable[Idx+1]].TheDef) << " };\n";
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OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n";
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OS << " const unsigned SubregHashTableSize = "
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<< SubregHashTableSize << ";\n";
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OS << " const unsigned SubregHashTable[] = { ~0U, ~0U };\n"
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<< " const unsigned SubregHashTableSize = 1;\n";
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delete [] SubregHashTable;
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// Print the SuperregHashTable, a simple quadratically probed
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// hash table for determining if a register is a super-register
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// of another register.
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unsigned NumSupRegs = 0;
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for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
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RegNo[Regs[i].TheDef] = i;
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NumSupRegs += RegisterSuperRegs[Regs[i].TheDef].size();
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unsigned SuperregHashTableSize = 2 * NextPowerOf2(2 * NumSupRegs);
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unsigned* SuperregHashTable = new unsigned[2 * SuperregHashTableSize];
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std::fill(SuperregHashTable, SuperregHashTable + 2 * SuperregHashTableSize, ~0U);
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for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
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Record* R = Regs[i].TheDef;
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for (std::set<Record*>::iterator I = RegisterSuperRegs[R].begin(),
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E = RegisterSuperRegs[R].end(); I != E; ++I) {
580
// We have to increase the indices of both registers by one when
581
// computing the hash because, in the generated code, there
582
// will be an extra empty slot at register 0.
583
size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (SuperregHashTableSize-1);
584
unsigned ProbeAmt = 2;
585
while (SuperregHashTable[index*2] != ~0U &&
586
SuperregHashTable[index*2+1] != ~0U) {
587
index = (index + ProbeAmt) & (SuperregHashTableSize-1);
593
SuperregHashTable[index*2] = i;
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SuperregHashTable[index*2+1] = RegNo[RJ];
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OS << "\n\n // Number of hash collisions: " << hashMisses << "\n";
600
if (SuperregHashTableSize) {
601
std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace");
603
OS << " const unsigned SuperregHashTable[] = { ";
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for (unsigned i = 0; i < SuperregHashTableSize - 1; ++i) {
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// Insert spaces for nice formatting.
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if (SuperregHashTable[2*i] != ~0U) {
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OS << getQualifiedName(Regs[SuperregHashTable[2*i]].TheDef) << ", "
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<< getQualifiedName(Regs[SuperregHashTable[2*i+1]].TheDef) << ", \n";
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OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n";
617
unsigned Idx = SuperregHashTableSize*2-2;
618
if (SuperregHashTable[Idx] != ~0U) {
620
<< getQualifiedName(Regs[SuperregHashTable[Idx]].TheDef) << ", "
621
<< getQualifiedName(Regs[SuperregHashTable[Idx+1]].TheDef) << " };\n";
623
OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n";
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OS << " const unsigned SuperregHashTableSize = "
627
<< SuperregHashTableSize << ";\n";
629
OS << " const unsigned SuperregHashTable[] = { ~0U, ~0U };\n"
630
<< " const unsigned SuperregHashTableSize = 1;\n";
633
delete [] SuperregHashTable;
636
// Print the AliasHashTable, a simple quadratically probed
637
// hash table for determining if a register aliases another register.
638
unsigned NumAliases = 0;
640
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
641
RegNo[Regs[i].TheDef] = i;
642
NumAliases += RegisterAliases[Regs[i].TheDef].size();
645
unsigned AliasesHashTableSize = 2 * NextPowerOf2(2 * NumAliases);
646
unsigned* AliasesHashTable = new unsigned[2 * AliasesHashTableSize];
647
std::fill(AliasesHashTable, AliasesHashTable + 2 * AliasesHashTableSize, ~0U);
651
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
652
Record* R = Regs[i].TheDef;
653
for (std::set<Record*>::iterator I = RegisterAliases[R].begin(),
654
E = RegisterAliases[R].end(); I != E; ++I) {
656
// We have to increase the indices of both registers by one when
657
// computing the hash because, in the generated code, there
658
// will be an extra empty slot at register 0.
659
size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (AliasesHashTableSize-1);
660
unsigned ProbeAmt = 2;
661
while (AliasesHashTable[index*2] != ~0U &&
662
AliasesHashTable[index*2+1] != ~0U) {
663
index = (index + ProbeAmt) & (AliasesHashTableSize-1);
669
AliasesHashTable[index*2] = i;
670
AliasesHashTable[index*2+1] = RegNo[RJ];
674
OS << "\n\n // Number of hash collisions: " << hashMisses << "\n";
676
if (AliasesHashTableSize) {
677
std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace");
679
OS << " const unsigned AliasesHashTable[] = { ";
680
for (unsigned i = 0; i < AliasesHashTableSize - 1; ++i) {
682
// Insert spaces for nice formatting.
685
if (AliasesHashTable[2*i] != ~0U) {
686
OS << getQualifiedName(Regs[AliasesHashTable[2*i]].TheDef) << ", "
687
<< getQualifiedName(Regs[AliasesHashTable[2*i+1]].TheDef) << ", \n";
689
OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n";
693
unsigned Idx = AliasesHashTableSize*2-2;
694
if (AliasesHashTable[Idx] != ~0U) {
696
<< getQualifiedName(Regs[AliasesHashTable[Idx]].TheDef) << ", "
697
<< getQualifiedName(Regs[AliasesHashTable[Idx+1]].TheDef) << " };\n";
699
OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n";
702
OS << " const unsigned AliasesHashTableSize = "
703
<< AliasesHashTableSize << ";\n";
705
OS << " const unsigned AliasesHashTable[] = { ~0U, ~0U };\n"
706
<< " const unsigned AliasesHashTableSize = 1;\n";
709
delete [] AliasesHashTable;
711
if (!RegisterAliases.empty())
712
OS << "\n\n // Register Alias Sets...\n";
714
// Emit the empty alias list
715
OS << " const unsigned Empty_AliasSet[] = { 0 };\n";
716
// Loop over all of the registers which have aliases, emitting the alias list
718
for (std::map<Record*, std::set<Record*>, LessRecord >::iterator
719
I = RegisterAliases.begin(), E = RegisterAliases.end(); I != E; ++I) {
720
OS << " const unsigned " << I->first->getName() << "_AliasSet[] = { ";
721
for (std::set<Record*>::iterator ASI = I->second.begin(),
722
E = I->second.end(); ASI != E; ++ASI)
723
OS << getQualifiedName(*ASI) << ", ";
727
if (!RegisterSubRegs.empty())
728
OS << "\n\n // Register Sub-registers Sets...\n";
730
// Emit the empty sub-registers list
731
OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
732
// Loop over all of the registers which have sub-registers, emitting the
733
// sub-registers list to memory.
734
for (std::map<Record*, std::set<Record*>, LessRecord>::iterator
735
I = RegisterSubRegs.begin(), E = RegisterSubRegs.end(); I != E; ++I) {
736
OS << " const unsigned " << I->first->getName() << "_SubRegsSet[] = { ";
737
std::vector<Record*> SubRegsVector;
738
for (std::set<Record*>::iterator ASI = I->second.begin(),
739
E = I->second.end(); ASI != E; ++ASI)
740
SubRegsVector.push_back(*ASI);
741
RegisterSorter RS(RegisterSubRegs);
742
std::stable_sort(SubRegsVector.begin(), SubRegsVector.end(), RS);
743
for (unsigned i = 0, e = SubRegsVector.size(); i != e; ++i)
744
OS << getQualifiedName(SubRegsVector[i]) << ", ";
748
if (!RegisterSuperRegs.empty())
749
OS << "\n\n // Register Super-registers Sets...\n";
751
// Emit the empty super-registers list
752
OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
753
// Loop over all of the registers which have super-registers, emitting the
754
// super-registers list to memory.
755
for (std::map<Record*, std::set<Record*>, LessRecord >::iterator
756
I = RegisterSuperRegs.begin(), E = RegisterSuperRegs.end(); I != E; ++I) {
757
OS << " const unsigned " << I->first->getName() << "_SuperRegsSet[] = { ";
759
std::vector<Record*> SuperRegsVector;
760
for (std::set<Record*>::iterator ASI = I->second.begin(),
761
E = I->second.end(); ASI != E; ++ASI)
762
SuperRegsVector.push_back(*ASI);
763
RegisterSorter RS(RegisterSubRegs);
764
std::stable_sort(SuperRegsVector.begin(), SuperRegsVector.end(), RS);
765
for (unsigned i = 0, e = SuperRegsVector.size(); i != e; ++i)
766
OS << getQualifiedName(SuperRegsVector[i]) << ", ";
770
OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n";
771
OS << " { \"NOREG\",\t0,\t0,\t0 },\n";
773
// Now that register alias and sub-registers sets have been emitted, emit the
774
// register descriptors now.
775
const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
776
for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
777
const CodeGenRegister &Reg = Registers[i];
779
OS << Reg.getName() << "\",\t";
780
if (RegisterAliases.count(Reg.TheDef))
781
OS << Reg.getName() << "_AliasSet,\t";
783
OS << "Empty_AliasSet,\t";
784
if (RegisterSubRegs.count(Reg.TheDef))
785
OS << Reg.getName() << "_SubRegsSet,\t";
787
OS << "Empty_SubRegsSet,\t";
788
if (RegisterSuperRegs.count(Reg.TheDef))
789
OS << Reg.getName() << "_SuperRegsSet },\n";
791
OS << "Empty_SuperRegsSet },\n";
793
OS << " };\n"; // End of register descriptors...
794
OS << "}\n\n"; // End of anonymous namespace...
796
std::string ClassName = Target.getName() + "GenRegisterInfo";
798
// Calculate the mapping of subregister+index pairs to physical registers.
799
std::vector<Record*> SubRegs = Records.getAllDerivedDefinitions("SubRegSet");
800
for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) {
801
int subRegIndex = SubRegs[i]->getValueAsInt("index");
802
std::vector<Record*> From = SubRegs[i]->getValueAsListOfDefs("From");
803
std::vector<Record*> To = SubRegs[i]->getValueAsListOfDefs("To");
805
if (From.size() != To.size()) {
806
errs() << "Error: register list and sub-register list not of equal length"
807
<< " in SubRegSet\n";
811
// For each entry in from/to vectors, insert the to register at index
812
for (unsigned ii = 0, ee = From.size(); ii != ee; ++ii)
813
SubRegVectors[From[ii]].push_back(std::make_pair(subRegIndex, To[ii]));
816
// Emit the subregister + index mapping function based on the information
818
OS << "unsigned " << ClassName
819
<< "::getSubReg(unsigned RegNo, unsigned Index) const {\n"
820
<< " switch (RegNo) {\n"
821
<< " default:\n return 0;\n";
822
for (std::map<Record*, std::vector<std::pair<int, Record*> > >::iterator
823
I = SubRegVectors.begin(), E = SubRegVectors.end(); I != E; ++I) {
824
OS << " case " << getQualifiedName(I->first) << ":\n";
825
OS << " switch (Index) {\n";
826
OS << " default: return 0;\n";
827
for (unsigned i = 0, e = I->second.size(); i != e; ++i)
828
OS << " case " << (I->second)[i].first << ": return "
829
<< getQualifiedName((I->second)[i].second) << ";\n";
830
OS << " };\n" << " break;\n";
833
OS << " return 0;\n";
836
OS << "unsigned " << ClassName
837
<< "::getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const {\n"
838
<< " switch (RegNo) {\n"
839
<< " default:\n return 0;\n";
840
for (std::map<Record*, std::vector<std::pair<int, Record*> > >::iterator
841
I = SubRegVectors.begin(), E = SubRegVectors.end(); I != E; ++I) {
842
OS << " case " << getQualifiedName(I->first) << ":\n";
843
for (unsigned i = 0, e = I->second.size(); i != e; ++i)
844
OS << " if (SubRegNo == "
845
<< getQualifiedName((I->second)[i].second)
846
<< ") return " << (I->second)[i].first << ";\n";
847
OS << " return 0;\n";
850
OS << " return 0;\n";
853
// Emit the constructor of the class...
854
OS << ClassName << "::" << ClassName
855
<< "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
856
<< " : TargetRegisterInfo(RegisterDescriptors, " << Registers.size()+1
857
<< ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n "
858
<< " CallFrameSetupOpcode, CallFrameDestroyOpcode,\n"
859
<< " SubregHashTable, SubregHashTableSize,\n"
860
<< " SuperregHashTable, SuperregHashTableSize,\n"
861
<< " AliasesHashTable, AliasesHashTableSize) {\n"
864
// Collect all information about dwarf register numbers
866
// First, just pull all provided information to the map
867
unsigned maxLength = 0;
868
for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
869
Record *Reg = Registers[i].TheDef;
870
std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
871
maxLength = std::max((size_t)maxLength, RegNums.size());
872
if (DwarfRegNums.count(Reg))
873
errs() << "Warning: DWARF numbers for register " << getQualifiedName(Reg)
874
<< "specified multiple times\n";
875
DwarfRegNums[Reg] = RegNums;
878
// Now we know maximal length of number list. Append -1's, where needed
879
for (DwarfRegNumsMapTy::iterator
880
I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
881
for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
882
I->second.push_back(-1);
884
// Emit information about the dwarf register numbers.
885
OS << "int " << ClassName << "::getDwarfRegNumFull(unsigned RegNum, "
886
<< "unsigned Flavour) const {\n"
887
<< " switch (Flavour) {\n"
889
<< " assert(0 && \"Unknown DWARF flavour\");\n"
892
for (unsigned i = 0, e = maxLength; i != e; ++i) {
893
OS << " case " << i << ":\n"
894
<< " switch (RegNum) {\n"
896
<< " assert(0 && \"Invalid RegNum\");\n"
899
// Sort by name to get a stable order.
902
for (DwarfRegNumsMapTy::iterator
903
I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
904
int RegNo = I->second[i];
906
OS << " case " << getQualifiedName(I->first) << ":\n"
907
<< " return " << RegNo << ";\n";
909
OS << " case " << getQualifiedName(I->first) << ":\n"
910
<< " assert(0 && \"Invalid register for this mode\");\n"
918
OS << "} // End llvm namespace \n";