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//===- AsmWriterEmitter.cpp - Generate an assembly writer -----------------===//
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// The LLVM Compiler Infrastructure
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//===----------------------------------------------------------------------===//
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// This tablegen backend is emits an assembly printer for the current target.
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// Note that this is currently fairly skeletal, but will grow over time.
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//===----------------------------------------------------------------------===//
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#include "AsmWriterEmitter.h"
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#include "AsmWriterInst.h"
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#include "CodeGenTarget.h"
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#include "StringToOffsetTable.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MathExtras.h"
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static void PrintCases(std::vector<std::pair<std::string,
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AsmWriterOperand> > &OpsToPrint, raw_ostream &O) {
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O << " case " << OpsToPrint.back().first << ": ";
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AsmWriterOperand TheOp = OpsToPrint.back().second;
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OpsToPrint.pop_back();
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// Check to see if any other operands are identical in this list, and if so,
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// emit a case label for them.
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for (unsigned i = OpsToPrint.size(); i != 0; --i)
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if (OpsToPrint[i-1].second == TheOp) {
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O << "\n case " << OpsToPrint[i-1].first << ": ";
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OpsToPrint.erase(OpsToPrint.begin()+i-1);
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// Finally, emit the code.
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/// EmitInstructions - Emit the last instruction in the vector and any other
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/// instructions that are suitably similar to it.
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static void EmitInstructions(std::vector<AsmWriterInst> &Insts,
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AsmWriterInst FirstInst = Insts.back();
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std::vector<AsmWriterInst> SimilarInsts;
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unsigned DifferingOperand = ~0;
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for (unsigned i = Insts.size(); i != 0; --i) {
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unsigned DiffOp = Insts[i-1].MatchesAllButOneOp(FirstInst);
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if (DifferingOperand == ~0U) // First match!
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DifferingOperand = DiffOp;
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// If this differs in the same operand as the rest of the instructions in
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// this class, move it to the SimilarInsts list.
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if (DifferingOperand == DiffOp || DiffOp == ~0U) {
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SimilarInsts.push_back(Insts[i-1]);
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Insts.erase(Insts.begin()+i-1);
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O << " case " << FirstInst.CGI->Namespace << "::"
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<< FirstInst.CGI->TheDef->getName() << ":\n";
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for (unsigned i = 0, e = SimilarInsts.size(); i != e; ++i)
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O << " case " << SimilarInsts[i].CGI->Namespace << "::"
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<< SimilarInsts[i].CGI->TheDef->getName() << ":\n";
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for (unsigned i = 0, e = FirstInst.Operands.size(); i != e; ++i) {
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if (i != DifferingOperand) {
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// If the operand is the same for all instructions, just print it.
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O << " " << FirstInst.Operands[i].getCode();
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// If this is the operand that varies between all of the instructions,
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// emit a switch for just this operand now.
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O << " switch (MI->getOpcode()) {\n";
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std::vector<std::pair<std::string, AsmWriterOperand> > OpsToPrint;
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OpsToPrint.push_back(std::make_pair(FirstInst.CGI->Namespace + "::" +
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FirstInst.CGI->TheDef->getName(),
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FirstInst.Operands[i]));
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for (unsigned si = 0, e = SimilarInsts.size(); si != e; ++si) {
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AsmWriterInst &AWI = SimilarInsts[si];
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OpsToPrint.push_back(std::make_pair(AWI.CGI->Namespace+"::"+
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AWI.CGI->TheDef->getName(),
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std::reverse(OpsToPrint.begin(), OpsToPrint.end());
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while (!OpsToPrint.empty())
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PrintCases(OpsToPrint, O);
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void AsmWriterEmitter::
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FindUniqueOperandCommands(std::vector<std::string> &UniqueOperandCommands,
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std::vector<unsigned> &InstIdxs,
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std::vector<unsigned> &InstOpsUsed) const {
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InstIdxs.assign(NumberedInstructions.size(), ~0U);
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// This vector parallels UniqueOperandCommands, keeping track of which
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// instructions each case are used for. It is a comma separated string of
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std::vector<std::string> InstrsForCase;
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InstrsForCase.resize(UniqueOperandCommands.size());
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InstOpsUsed.assign(UniqueOperandCommands.size(), 0);
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for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
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const AsmWriterInst *Inst = getAsmWriterInstByID(i);
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if (Inst == 0) continue; // PHI, INLINEASM, DBG_LABEL, etc.
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if (Inst->Operands.empty())
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continue; // Instruction already done.
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Command = " " + Inst->Operands[0].getCode() + "\n";
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// Check to see if we already have 'Command' in UniqueOperandCommands.
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bool FoundIt = false;
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for (unsigned idx = 0, e = UniqueOperandCommands.size(); idx != e; ++idx)
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if (UniqueOperandCommands[idx] == Command) {
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InstrsForCase[idx] += ", ";
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InstrsForCase[idx] += Inst->CGI->TheDef->getName();
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InstIdxs[i] = UniqueOperandCommands.size();
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UniqueOperandCommands.push_back(Command);
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InstrsForCase.push_back(Inst->CGI->TheDef->getName());
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// This command matches one operand so far.
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InstOpsUsed.push_back(1);
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// For each entry of UniqueOperandCommands, there is a set of instructions
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// that uses it. If the next command of all instructions in the set are
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// identical, fold it into the command.
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for (unsigned CommandIdx = 0, e = UniqueOperandCommands.size();
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CommandIdx != e; ++CommandIdx) {
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for (unsigned Op = 1; ; ++Op) {
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// Scan for the first instruction in the set.
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std::vector<unsigned>::iterator NIT =
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std::find(InstIdxs.begin(), InstIdxs.end(), CommandIdx);
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if (NIT == InstIdxs.end()) break; // No commonality.
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// If this instruction has no more operands, we isn't anything to merge
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// into this command.
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const AsmWriterInst *FirstInst =
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getAsmWriterInstByID(NIT-InstIdxs.begin());
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if (!FirstInst || FirstInst->Operands.size() == Op)
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// Otherwise, scan to see if all of the other instructions in this command
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// set share the operand.
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// Keep track of the maximum, number of operands or any
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// instruction we see in the group.
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size_t MaxSize = FirstInst->Operands.size();
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for (NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx);
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NIT != InstIdxs.end();
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NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx)) {
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// Okay, found another instruction in this command set. If the operand
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// matches, we're ok, otherwise bail out.
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const AsmWriterInst *OtherInst =
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getAsmWriterInstByID(NIT-InstIdxs.begin());
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OtherInst->Operands.size() > FirstInst->Operands.size())
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MaxSize = std::max(MaxSize, OtherInst->Operands.size());
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if (!OtherInst || OtherInst->Operands.size() == Op ||
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OtherInst->Operands[Op] != FirstInst->Operands[Op]) {
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// Okay, everything in this command set has the same next operand. Add it
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// to UniqueOperandCommands and remember that it was consumed.
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std::string Command = " " + FirstInst->Operands[Op].getCode() + "\n";
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UniqueOperandCommands[CommandIdx] += Command;
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InstOpsUsed[CommandIdx]++;
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// Prepend some of the instructions each case is used for onto the case val.
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for (unsigned i = 0, e = InstrsForCase.size(); i != e; ++i) {
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std::string Instrs = InstrsForCase[i];
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if (Instrs.size() > 70) {
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Instrs.erase(Instrs.begin()+70, Instrs.end());
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UniqueOperandCommands[i] = " // " + Instrs + "\n" +
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UniqueOperandCommands[i];
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static void UnescapeString(std::string &Str) {
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for (unsigned i = 0; i != Str.size(); ++i) {
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if (Str[i] == '\\' && i != Str.size()-1) {
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default: continue; // Don't execute the code after the switch.
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case 'a': Str[i] = '\a'; break;
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case 'b': Str[i] = '\b'; break;
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case 'e': Str[i] = 27; break;
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case 'f': Str[i] = '\f'; break;
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case 'n': Str[i] = '\n'; break;
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case 'r': Str[i] = '\r'; break;
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case 't': Str[i] = '\t'; break;
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case 'v': Str[i] = '\v'; break;
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case '"': Str[i] = '\"'; break;
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case '\'': Str[i] = '\''; break;
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case '\\': Str[i] = '\\'; break;
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// Nuke the second character.
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Str.erase(Str.begin()+i+1);
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/// EmitPrintInstruction - Generate the code for the "printInstruction" method
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void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) {
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CodeGenTarget Target;
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Record *AsmWriter = Target.getAsmWriter();
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std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
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"/// printInstruction - This method is automatically generated by tablegen\n"
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"/// from the instruction set description.\n"
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"void " << Target.getName() << ClassName
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<< "::printInstruction(const MachineInstr *MI) {\n";
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std::vector<AsmWriterInst> Instructions;
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for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
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E = Target.inst_end(); I != E; ++I)
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if (!I->second.AsmString.empty() &&
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I->second.TheDef->getName() != "PHI")
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Instructions.push_back(
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AsmWriterInst(I->second,
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AsmWriter->getValueAsInt("Variant"),
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AsmWriter->getValueAsInt("FirstOperandColumn"),
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AsmWriter->getValueAsInt("OperandSpacing")));
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// Get the instruction numbering.
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Target.getInstructionsByEnumValue(NumberedInstructions);
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// Compute the CodeGenInstruction -> AsmWriterInst mapping. Note that not
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// all machine instructions are necessarily being printed, so there may be
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// target instructions not in this map.
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for (unsigned i = 0, e = Instructions.size(); i != e; ++i)
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CGIAWIMap.insert(std::make_pair(Instructions[i].CGI, &Instructions[i]));
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// Build an aggregate string, and build a table of offsets into it.
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StringToOffsetTable StringTable;
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/// OpcodeInfo - This encodes the index of the string to use for the first
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/// chunk of the output as well as indices used for operand printing.
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std::vector<unsigned> OpcodeInfo;
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unsigned MaxStringIdx = 0;
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for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
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AsmWriterInst *AWI = CGIAWIMap[NumberedInstructions[i]];
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// Something not handled by the asmwriter printer.
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} else if (AWI->Operands[0].OperandType !=
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AsmWriterOperand::isLiteralTextOperand ||
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AWI->Operands[0].Str.empty()) {
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// Something handled by the asmwriter printer, but with no leading string.
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Idx = StringTable.GetOrAddStringOffset("");
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std::string Str = AWI->Operands[0].Str;
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Idx = StringTable.GetOrAddStringOffset(Str);
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MaxStringIdx = std::max(MaxStringIdx, Idx);
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// Nuke the string from the operand list. It is now handled!
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AWI->Operands.erase(AWI->Operands.begin());
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// Bias offset by one since we want 0 as a sentinel.
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OpcodeInfo.push_back(Idx+1);
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// Figure out how many bits we used for the string index.
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unsigned AsmStrBits = Log2_32_Ceil(MaxStringIdx+2);
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// To reduce code size, we compactify common instructions into a few bits
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// in the opcode-indexed table.
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unsigned BitsLeft = 32-AsmStrBits;
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std::vector<std::vector<std::string> > TableDrivenOperandPrinters;
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std::vector<std::string> UniqueOperandCommands;
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std::vector<unsigned> InstIdxs;
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std::vector<unsigned> NumInstOpsHandled;
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FindUniqueOperandCommands(UniqueOperandCommands, InstIdxs,
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// If we ran out of operands to print, we're done.
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if (UniqueOperandCommands.empty()) break;
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// Compute the number of bits we need to represent these cases, this is
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// ceil(log2(numentries)).
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unsigned NumBits = Log2_32_Ceil(UniqueOperandCommands.size());
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// If we don't have enough bits for this operand, don't include it.
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if (NumBits > BitsLeft) {
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DEBUG(errs() << "Not enough bits to densely encode " << NumBits
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// Otherwise, we can include this in the initial lookup table. Add it in.
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for (unsigned i = 0, e = InstIdxs.size(); i != e; ++i)
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if (InstIdxs[i] != ~0U)
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OpcodeInfo[i] |= InstIdxs[i] << (BitsLeft+AsmStrBits);
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// Remove the info about this operand.
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for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
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if (AsmWriterInst *Inst = getAsmWriterInstByID(i))
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if (!Inst->Operands.empty()) {
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unsigned NumOps = NumInstOpsHandled[InstIdxs[i]];
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assert(NumOps <= Inst->Operands.size() &&
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"Can't remove this many ops!");
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Inst->Operands.erase(Inst->Operands.begin(),
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Inst->Operands.begin()+NumOps);
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// Remember the handlers for this set of operands.
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TableDrivenOperandPrinters.push_back(UniqueOperandCommands);
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O<<" static const unsigned OpInfo[] = {\n";
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for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
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O << " " << OpcodeInfo[i] << "U,\t// "
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<< NumberedInstructions[i]->TheDef->getName() << "\n";
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// Add a dummy entry so the array init doesn't end with a comma.
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// Emit the string itself.
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O << " const char *AsmStrs = \n";
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StringTable.EmitString(O);
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O << " O << \"\\t\";\n\n";
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O << " // Emit the opcode for the instruction.\n"
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<< " unsigned Bits = OpInfo[MI->getOpcode()];\n"
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<< " assert(Bits != 0 && \"Cannot print this instruction.\");\n"
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<< " O << AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << ")-1;\n\n";
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// Output the table driven operand information.
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BitsLeft = 32-AsmStrBits;
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for (unsigned i = 0, e = TableDrivenOperandPrinters.size(); i != e; ++i) {
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std::vector<std::string> &Commands = TableDrivenOperandPrinters[i];
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// Compute the number of bits we need to represent these cases, this is
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// ceil(log2(numentries)).
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unsigned NumBits = Log2_32_Ceil(Commands.size());
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assert(NumBits <= BitsLeft && "consistency error");
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// Emit code to extract this field from Bits.
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O << "\n // Fragment " << i << " encoded into " << NumBits
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<< " bits for " << Commands.size() << " unique commands.\n";
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if (Commands.size() == 2) {
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// Emit two possibilitys with if/else.
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O << " if ((Bits >> " << (BitsLeft+AsmStrBits) << ") & "
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<< ((1 << NumBits)-1) << ") {\n"
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O << " switch ((Bits >> " << (BitsLeft+AsmStrBits) << ") & "
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<< ((1 << NumBits)-1) << ") {\n"
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<< " default: // unreachable.\n";
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// Print out all the cases.
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for (unsigned i = 0, e = Commands.size(); i != e; ++i) {
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O << " case " << i << ":\n";
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// Okay, delete instructions with no operand info left.
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for (unsigned i = 0, e = Instructions.size(); i != e; ++i) {
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// Entire instruction has been emitted?
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AsmWriterInst &Inst = Instructions[i];
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if (Inst.Operands.empty()) {
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Instructions.erase(Instructions.begin()+i);
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// Because this is a vector, we want to emit from the end. Reverse all of the
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// elements in the vector.
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std::reverse(Instructions.begin(), Instructions.end());
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// Now that we've emitted all of the operand info that fit into 32 bits, emit
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// information for those instructions that are left. This is a less dense
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// encoding, but we expect the main 32-bit table to handle the majority of
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if (!Instructions.empty()) {
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// Find the opcode # of inline asm.
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O << " switch (MI->getOpcode()) {\n";
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while (!Instructions.empty())
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EmitInstructions(Instructions, O);
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void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) {
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CodeGenTarget Target;
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Record *AsmWriter = Target.getAsmWriter();
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std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
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const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
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StringToOffsetTable StringTable;
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"\n\n/// getRegisterName - This method is automatically generated by tblgen\n"
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"/// from the register set description. This returns the assembler name\n"
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"/// for the specified register.\n"
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"const char *" << Target.getName() << ClassName
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<< "::getRegisterName(unsigned RegNo) {\n"
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<< " assert(RegNo && RegNo < " << (Registers.size()+1)
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<< " && \"Invalid register number!\");\n"
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<< " static const unsigned RegAsmOffset[] = {";
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for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
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const CodeGenRegister &Reg = Registers[i];
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std::string AsmName = Reg.TheDef->getValueAsString("AsmName");
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AsmName = Reg.getName();
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O << StringTable.GetOrAddStringOffset(AsmName) << ", ";
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O << " const char *AsmStrs =\n";
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StringTable.EmitString(O);
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O << " return AsmStrs+RegAsmOffset[RegNo-1];\n"
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void AsmWriterEmitter::EmitGetInstructionName(raw_ostream &O) {
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CodeGenTarget Target;
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Record *AsmWriter = Target.getAsmWriter();
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std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
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std::vector<const CodeGenInstruction*> NumberedInstructions;
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Target.getInstructionsByEnumValue(NumberedInstructions);
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StringToOffsetTable StringTable;
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"\n\n#ifdef GET_INSTRUCTION_NAME\n"
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"#undef GET_INSTRUCTION_NAME\n\n"
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"/// getInstructionName: This method is automatically generated by tblgen\n"
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"/// from the instruction set description. This returns the enum name of the\n"
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"/// specified instruction.\n"
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"const char *" << Target.getName() << ClassName
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<< "::getInstructionName(unsigned Opcode) {\n"
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<< " assert(Opcode < " << NumberedInstructions.size()
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<< " && \"Invalid instruction number!\");\n"
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<< " static const unsigned InstAsmOffset[] = {";
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for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
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const CodeGenInstruction &Inst = *NumberedInstructions[i];
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std::string AsmName = Inst.TheDef->getName();
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O << StringTable.GetOrAddStringOffset(AsmName) << ", ";
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O << " const char *Strs =\n";
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StringTable.EmitString(O);
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O << " return Strs+InstAsmOffset[Opcode];\n"
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void AsmWriterEmitter::run(raw_ostream &O) {
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EmitSourceFileHeader("Assembly Writer Source Fragment", O);
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EmitPrintInstruction(O);
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EmitGetRegisterName(O);
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EmitGetInstructionName(O);