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Viewing changes to board/freescale/mpc8572ds/mpc8572ds.c

  • Committer: Bazaar Package Importer
  • Author(s): Oliver Grawert
  • Date: 2010-01-20 15:41:26 UTC
  • mfrom: (1.1.2 upstream)
  • Revision ID: james.westby@ubuntu.com-20100120154126-7bha1jeyjegu7xm5
Tags: 2009.08+really2009.01-0ubuntu1
* revert to the 2009.01 upstream version, 2009.08 has still to 
  many work in progress items in the freescale patchset (MMC and NIC
  dont work at all)
* add the latest patchset from freescale for 2009.01
* add 1002_enable_hush_shell_and_ext2.patch to enable hush shell and ext2 
* add 1003_fix_board_revision_numbers to make sure babbage 2.5 boards have 
  revision 51120 and babbage 3.0 boards have revision 51130 properly set in 
  their cpuinfo

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board/freescale/mpc8572ds/mpc8572ds.c
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#include <asm/mmu.h>
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#include <asm/cache.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_pci.h>
 
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#include <asm/immap_fsl_pci.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/io.h>
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#include <miiphy.h>
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int checkboard (void)
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{
45
 
        u8 vboot;
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        u8 *pixis_base = (u8 *)PIXIS_BASE;
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        puts ("Board: MPC8572DS ");
49
 
#ifdef CONFIG_PHYS_64BIT
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        puts ("(36-bit addrmap) ");
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#endif
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        printf ("Sys ID: 0x%02x, "
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                "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
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                in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
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                in_8(pixis_base + PIXIS_PVER));
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57
 
        vboot = in_8(pixis_base + PIXIS_VBOOT);
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        switch ((vboot & PIXIS_VBOOT_LBMAP) >> 6) {
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                case PIXIS_VBOOT_LBMAP_NOR0:
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                        puts ("vBank: 0\n");
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                        break;
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                case PIXIS_VBOOT_LBMAP_PJET:
63
 
                        puts ("Promjet\n");
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                        break;
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                case PIXIS_VBOOT_LBMAP_NAND:
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                        puts ("NAND\n");
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                        break;
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                case PIXIS_VBOOT_LBMAP_NOR1:
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                        puts ("vBank: 1\n");
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                        break;
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        }
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        printf ("Board: MPC8572DS, System ID: 0x%02x, "
 
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                "System Version: 0x%02x, FPGA Version: 0x%02x\n",
 
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                in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
 
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                in8(PIXIS_BASE + PIXIS_PVER));
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        return 0;
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}
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static struct pci_controller pcie3_hose;
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#endif
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extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
 
139
extern void fsl_pci_init(struct pci_controller *hose);
 
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int first_free_busno=0;
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#ifdef CONFIG_PCI
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void pci_init_board(void)
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                        /* outbound memory */
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                        pci_set_region(r++,
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                                        CONFIG_SYS_PCIE3_MEM_BUS,
 
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                                        CONFIG_SYS_PCIE3_MEM_BASE,
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                                        CONFIG_SYS_PCIE3_MEM_PHYS,
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                                        CONFIG_SYS_PCIE3_MEM_SIZE,
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                                        PCI_REGION_MEM);
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                        /* outbound io */
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                        pci_set_region(r++,
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                                        CONFIG_SYS_PCIE3_IO_BUS,
 
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                                        CONFIG_SYS_PCIE3_IO_BASE,
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                                        CONFIG_SYS_PCIE3_IO_PHYS,
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                                        CONFIG_SYS_PCIE3_IO_SIZE,
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                                        PCI_REGION_IO);
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                        pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0 ),
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                                        PCI_BASE_ADDRESS_1, &temp32);
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                        if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
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                                void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
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                                                                temp32, 4, 0);
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                                debug(" uli1572 read to %p\n", p);
243
 
                                in_be32(p);
 
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                        if (temp32 >= CONFIG_SYS_PCIE3_MEM_PHYS) {
 
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                                debug(" uli1572 read to %x\n", temp32);
 
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                                in_be32((unsigned *)temp32);
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                        }
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                } else {
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                        printf ("    PCIE3: disabled\n");
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                        /* outbound memory */
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                        pci_set_region(r++,
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                                        CONFIG_SYS_PCIE2_MEM_BUS,
 
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                                        CONFIG_SYS_PCIE2_MEM_BASE,
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                                        CONFIG_SYS_PCIE2_MEM_PHYS,
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                                        CONFIG_SYS_PCIE2_MEM_SIZE,
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                                        PCI_REGION_MEM);
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                        /* outbound io */
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                        pci_set_region(r++,
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                                        CONFIG_SYS_PCIE2_IO_BUS,
 
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                                        CONFIG_SYS_PCIE2_IO_BASE,
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                                        CONFIG_SYS_PCIE2_IO_PHYS,
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                                        CONFIG_SYS_PCIE2_IO_SIZE,
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                                        PCI_REGION_IO);
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                        /* outbound memory */
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                        pci_set_region(r++,
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                                        CONFIG_SYS_PCIE1_MEM_BUS,
 
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                                        CONFIG_SYS_PCIE1_MEM_BASE,
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                                        CONFIG_SYS_PCIE1_MEM_PHYS,
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                                        CONFIG_SYS_PCIE1_MEM_SIZE,
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                                        PCI_REGION_MEM);
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                        /* outbound io */
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                        pci_set_region(r++,
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                                        CONFIG_SYS_PCIE1_IO_BUS,
 
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                                        CONFIG_SYS_PCIE1_IO_BASE,
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                                        CONFIG_SYS_PCIE1_IO_PHYS,
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                                        CONFIG_SYS_PCIE1_IO_SIZE,
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                                        PCI_REGION_IO);
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        /* invalidate existing TLB entry for flash + promjet */
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        disable_tlb(flash_esel);
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384
 
        set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,       /* tlb, epn, rpn */
 
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        set_tlb(1, flashbase, flashbase,                /* tlb, epn, rpn */
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                        MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
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                        0, flash_esel, BOOKE_PAGESZ_256M, 1);   /* ts, esel, tsize, iprot */
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unsigned long get_board_sys_clk(ulong dummy)
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{
435
 
        u8 *pixis_base = (u8 *)PIXIS_BASE;
436
 
 
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        return ics307_clk_freq (
438
 
                        in_8(pixis_base + PIXIS_VSYSCLK0),
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                        in_8(pixis_base + PIXIS_VSYSCLK1),
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                        in_8(pixis_base + PIXIS_VSYSCLK2)
 
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                        in8(PIXIS_BASE + PIXIS_VSYSCLK0),
 
414
                        in8(PIXIS_BASE + PIXIS_VSYSCLK1),
 
415
                        in8(PIXIS_BASE + PIXIS_VSYSCLK2)
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                        );
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}
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unsigned long get_board_ddr_clk(ulong dummy)
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{
446
 
        u8 *pixis_base = (u8 *)PIXIS_BASE;
447
 
 
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        return ics307_clk_freq (
449
 
                        in_8(pixis_base + PIXIS_VDDRCLK0),
450
 
                        in_8(pixis_base + PIXIS_VDDRCLK1),
451
 
                        in_8(pixis_base + PIXIS_VDDRCLK2)
 
422
                        in8(PIXIS_BASE + PIXIS_VDDRCLK0),
 
423
                        in8(PIXIS_BASE + PIXIS_VDDRCLK1),
 
424
                        in8(PIXIS_BASE + PIXIS_VDDRCLK2)
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                        );
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}
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#else
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{
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        u8 i;
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        ulong val = 0;
459
 
        u8 *pixis_base = (u8 *)PIXIS_BASE;
460
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461
 
        i = in_8(pixis_base + PIXIS_SPD);
 
433
        i = in8(PIXIS_BASE + PIXIS_SPD);
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        i &= 0x07;
463
435
 
464
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        switch (i) {
495
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{
496
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        u8 i;
497
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        ulong val = 0;
498
 
        u8 *pixis_base = (u8 *)PIXIS_BASE;
499
470
 
500
 
        i = in_8(pixis_base + PIXIS_SPD);
 
471
        i = in8(PIXIS_BASE + PIXIS_SPD);
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        i &= 0x38;
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        i >>= 3;
503
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                return 0;
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        }
571
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572
 
#ifdef CONFIG_FSL_SGMII_RISER
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        fsl_sgmii_riser_init(tsec_info, num);
574
 
#endif
575
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576
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        tsec_eth_init(bis, tsec_info, num);
577
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580
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#endif
581
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582
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#if defined(CONFIG_OF_BOARD_SETUP)
 
552
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
 
553
                        struct pci_controller *hose);
 
554
 
583
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void ft_board_setup(void *blob, bd_t *bd)
584
556
{
585
 
        phys_addr_t base;
586
 
        phys_size_t size;
 
557
        ulong base, size;
587
558
 
588
559
        ft_cpu_setup(blob, bd);
589
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601
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#ifdef CONFIG_PCIE1
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        ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
603
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#endif
604
 
#ifdef CONFIG_FSL_SGMII_RISER
605
 
        fsl_sgmii_riser_fdt_fixup(blob);
606
 
#endif
607
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}
608
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#endif
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