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50
get_sys_info (&sysinfo);
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printf ("Board: Freescale MPC8540EVAL Board\n");
53
printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor[0] / 1000000);
53
printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
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54
printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
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55
printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
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56
if((CONFIG_SYS_LBC_LCRR & 0x0f) == 2 || (CONFIG_SYS_LBC_LCRR & 0x0f) == 4 \
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138
/* Initialize all of memory for ECC, then
139
139
* enable errors */
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volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
142
dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);
144
for (*p = 0; p < (uint *)(8 * 1024); p++) {
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if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
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*p = (unsigned int)0xdeadbeef;
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if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
151
dma_xfer((uint *)0x2000,0x2000,(uint *)0);
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dma_xfer((uint *)0x4000,0x4000,(uint *)0);
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dma_xfer((uint *)0x8000,0x8000,(uint *)0);
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dma_xfer((uint *)0x10000,0x10000,(uint *)0);
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dma_xfer((uint *)0x20000,0x20000,(uint *)0);
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dma_xfer((uint *)0x40000,0x40000,(uint *)0);
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dma_xfer((uint *)0x80000,0x80000,(uint *)0);
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dma_xfer((uint *)0x100000,0x100000,(uint *)0);
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dma_xfer((uint *)0x200000,0x200000,(uint *)0);
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dma_xfer((uint *)0x400000,0x400000,(uint *)0);
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for (i = 1; i < dram_size / 0x800000; i++) {
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dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
144
175
/* Enable errors for ECC */
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176
ddr->err_disable = 0x00000000;