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Viewing changes to include/configs/M54451EVB.h

  • Committer: Bazaar Package Importer
  • Author(s): Oliver Grawert
  • Date: 2010-01-20 15:41:26 UTC
  • mfrom: (1.1.2 upstream)
  • Revision ID: james.westby@ubuntu.com-20100120154126-7bha1jeyjegu7xm5
Tags: 2009.08+really2009.01-0ubuntu1
* revert to the 2009.01 upstream version, 2009.08 has still to 
  many work in progress items in the freescale patchset (MMC and NIC
  dont work at all)
* add the latest patchset from freescale for 2009.01
* add 1002_enable_hush_shell_and_ext2.patch to enable hush shell and ext2 
* add 1003_fix_board_revision_numbers to make sure babbage 2.5 boards have 
  revision 51120 and babbage 3.0 boards have revision 51130 properly set in 
  their cpuinfo

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Lines of Context:
include/configs/M54451EVB.h
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#define CONFIG_CMD_MISC
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_NFS
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_REGINFO
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#define CONFIG_CMD_SPI
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#       define MCFFEC_TOUT_LOOP 50000
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#       define CONFIG_BOOTDELAY 1       /* autoboot after 5 seconds */
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#       define CONFIG_BOOTARGS          "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:2M(kernel)ro,-(jffs2)"
 
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#       define CONFIG_BOOTARGS          "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
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#       define CONFIG_ETHADDR           00:e0:0c:bc:e5:60
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#       define CONFIG_ETHPRIME          "FEC0"
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#       define CONFIG_IPADDR            192.162.1.2
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#define CONFIG_SYS_I2C_SPEED            80000   /* I2C speed and slave address  */
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#define CONFIG_SYS_I2C_SLAVE            0x7F
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#define CONFIG_SYS_I2C_OFFSET           0x58000
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#define CONFIG_SYS_IMMR                 CONFIG_SYS_MBAR
 
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#define CONFIG_SYS_IMMR         CONFIG_SYS_MBAR
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/* DSPI and Serial Flash */
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#define CONFIG_CF_SPI
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#define CONFIG_CF_DSPI
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#define CONFIG_SERIAL_FLASH
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#define CONFIG_HARD_SPI
 
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#define CONFIG_SYS_SER_FLASH_BASE       0x01000000
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#define CONFIG_SYS_SBFHDR_SIZE          0x7
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#ifdef CONFIG_CMD_SPI
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#       define CONFIG_SPI_FLASH
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#       define CONFIG_SPI_FLASH_STMICRO
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#       define CONFIG_SYS_DSPI_CTAR0    (DSPI_CTAR_TRSZ(7) | \
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                                         DSPI_CTAR_PCSSCK_1CLK | \
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                                         DSPI_CTAR_PASC(0) | \
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                                         DSPI_CTAR_PDT(0) | \
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                                         DSPI_CTAR_CSSCK(0) | \
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                                         DSPI_CTAR_ASC(0) | \
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                                         DSPI_CTAR_DT(1))
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#       define CONFIG_SYS_DSPI_CTAR1    (CONFIG_SYS_DSPI_CTAR0)
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#       define CONFIG_SYS_DSPI_CTAR2    (CONFIG_SYS_DSPI_CTAR0)
 
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#       define CONFIG_SYS_DSPI_DCTAR0           (DSPI_DCTAR_TRSZ(7) | \
 
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                                         DSPI_DCTAR_CPOL | \
 
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                                         DSPI_DCTAR_CPHA | \
 
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                                         DSPI_DCTAR_PCSSCK_1CLK | \
 
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                                         DSPI_DCTAR_PASC(0) | \
 
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                                         DSPI_DCTAR_PDT(0) | \
 
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                                         DSPI_DCTAR_CSSCK(0) | \
 
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                                         DSPI_DCTAR_ASC(0) | \
 
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                                         DSPI_DCTAR_PBR(0) | \
 
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                                         DSPI_DCTAR_DT(1) | \
 
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                                         DSPI_DCTAR_BR(1))
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#endif
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/* Input, PCI, Flexbus, and VCO */
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#define CONFIG_EXTRA_CLOCK
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#define CONFIG_PRAM                     2048    /* 2048 KB */
 
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#define CONFIG_PRAM             2048    /* 2048 KB */
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#define CONFIG_SYS_PROMPT               "-> "
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#define CONFIG_SYS_LONGHELP             /* undef to save memory */
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#define CONFIG_SYS_HZ                   1000
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#define CONFIG_SYS_MBAR                 0xFC000000
 
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#define CONFIG_SYS_MBAR         0xFC000000
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/*
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 * Low Level Configuration Settings
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/* Configuration for environment
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 * Environment is embedded in u-boot in the second sector of the flash
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 */
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#if defined(CONFIG_SYS_STMICRO_BOOT)
 
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#if defined(CONFIG_CF_SBF)
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#       define CONFIG_ENV_IS_IN_SPI_FLASH       1
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#       define CONFIG_ENV_SPI_CS                1
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#       define CONFIG_ENV_OFFSET                0x20000
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#       define CONFIG_ENV_SECT_SIZE     0x10000
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#else
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#       define CONFIG_ENV_IS_IN_FLASH   1
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#       define CONFIG_ENV_ADDR          (CONFIG_SYS_FLASH_BASE + 0x8000)
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#       define CONFIG_ENV_SIZE          0x2000
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#       define CONFIG_ENV_SECT_SIZE     0x8000
 
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#       define CONFIG_ENV_ADDR          (CONFIG_SYS_FLASH_BASE + 0x4000)
 
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#       define CONFIG_ENV_SECT_SIZE     0x2000
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#endif
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#undef CONFIG_ENV_OVERWRITE
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#undef CONFIG_ENV_IS_EMBEDDED
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/* FLASH organization */
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#define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 
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/*-----------------------------------------------------------------------
 
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 * FLASH organization
 
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 */
 
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#ifdef CONFIG_SYS_STMICRO_BOOT
 
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#       define CONFIG_SYS_FLASH_BASE            CONFIG_SYS_SER_FLASH_BASE
 
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#       define CONFIG_SYS_FLASH0_BASE           CONFIG_SYS_SER_FLASH_BASE
 
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#       define CONFIG_SYS_FLASH1_BASE           CONFIG_SYS_CS0_BASE
 
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#endif
 
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#ifdef CONFIG_SYS_SPANSION_BOOT
 
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#       define CONFIG_SYS_FLASH_BASE            CONFIG_SYS_CS0_BASE
 
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#       define CONFIG_SYS_FLASH0_BASE           CONFIG_SYS_CS0_BASE
 
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#       define CONFIG_SYS_FLASH1_BASE           CONFIG_SYS_SER_FLASH_BASE
 
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#endif
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#define CONFIG_SYS_FLASH_CFI
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#ifdef CONFIG_SYS_FLASH_CFI
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#       define CONFIG_FLASH_CFI_DRIVER  1
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#       define CONFIG_SYS_FLASH_USE_BUFFER_WRITE        1
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#       define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
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#       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
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#       define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
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 * This is setting for JFFS2 support in u-boot.
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 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
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 */
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#ifdef CONFIG_CMD_JFFS2
 
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#ifdef CONFIG_SYS_SPANSION_BOOT
 
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#       define CONFIG_JFFS2_DEV         "nor0"
 
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#       define CONFIG_JFFS2_PART_SIZE   0x01000000
 
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#       define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
 
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#endif
 
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#ifdef CONFIG_SYS_STMICRO_BOOT
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#       define CONFIG_JFFS2_DEV         "nor0"
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#       define CONFIG_JFFS2_PART_SIZE   0x01000000
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#       define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
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#endif
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/* Cache Configuration */
 
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/*-----------------------------------------------------------------------
 
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 * Cache Configuration
 
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 */
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#define CONFIG_SYS_CACHELINE_SIZE               16
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/*-----------------------------------------------------------------------
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 * Memory bank definitions
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 */
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/*
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 * CS0 - NOR Flash 16MB
 
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 * CS0 - NOR Flash 8MB
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 * CS1 - Available
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 * CS2 - Available
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 * CS3 - Available
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 * CS5 - Available
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 */
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 /* Flash */
 
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 /* SPANSION Flash */
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#define CONFIG_SYS_CS0_BASE             0x00000000
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#define CONFIG_SYS_CS0_MASK             0x00FF0001
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#define CONFIG_SYS_CS0_CTRL             0x00004D80
 
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#define CONFIG_SYS_CS0_MASK             0x007F0001
 
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#define CONFIG_SYS_CS0_CTRL             0x00001180
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#define CONFIG_SYS_SPANSION_BASE        CONFIG_SYS_CS0_BASE
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