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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
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#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
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#define CONFIG_SYS_MC_PUP_VAL 0x00000000
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#define CONFIG_SYS_MC_PUER_VAL 0x00000000
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#define CONFIG_SYS_MC_ASR_VAL 0x00000000
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#define CONFIG_SYS_MC_AASR_VAL 0x00000000
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#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
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#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NAND
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#define CONFIG_NAND_LEGACY
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
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#define SECTORSIZE 512
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#define ADDR_COLUMN 1
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#define ADDR_COLUMN_PAGE 3
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#define NAND_ChipID_UNKNOWN 0x00
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#define NAND_MAX_FLOORS 1
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#define NAND_MAX_CHIPS 1
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#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */
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#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */
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#include <asm/arch/AT91RM9200.h> /* needed for port definitions */
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#define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0)
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#define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0)
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#define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2))
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#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0)
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#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0)
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#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
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#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
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/* the following are NOP's in our implementation */
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#define NAND_CTL_CLRALE(nandptr)
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#define NAND_CTL_SETALE(nandptr)
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#define NAND_CTL_CLRCLE(nandptr)
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#define NAND_CTL_SETCLE(nandptr)
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM 0x20000000