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* Copyright 2003,2004,2008 Free Software Foundation, Inc.
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* This file is part of GNU Radio
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* GNU Radio is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3, or (at your option)
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* GNU Radio is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License
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* along with GNU Radio; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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#include "usrp_basic.h"
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#include "usrp_prims.h"
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#include "usrp_interfaces.h"
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#include "fpga_regs_common.h"
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#include "fpga_regs_standard.h"
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#include "db_boards.h"
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using namespace ad9862;
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#define NELEM(x) (sizeof (x) / sizeof (x[0]))
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// These set the buffer size used for each end point using the fast
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// usb interface. The kernel ends up locking down this much memory.
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static const int FUSB_BUFFER_SIZE = fusb_sysconfig::default_buffer_size();
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static const int FUSB_BLOCK_SIZE = fusb_sysconfig::max_block_size();
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static const int FUSB_NBLOCKS = FUSB_BUFFER_SIZE / FUSB_BLOCK_SIZE;
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static const double POLLING_INTERVAL = 0.1; // seconds
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////////////////////////////////////////////////////////////////
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static struct usb_dev_handle *
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open_rx_interface (struct usb_device *dev)
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struct usb_dev_handle *udh = usrp_open_rx_interface (dev);
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fprintf (stderr, "usrp_basic_rx: can't open rx interface\n");
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static struct usb_dev_handle *
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open_tx_interface (struct usb_device *dev)
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struct usb_dev_handle *udh = usrp_open_tx_interface (dev);
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fprintf (stderr, "usrp_basic_tx: can't open tx interface\n");
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//////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////
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// These settings give us:
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// CLKOUT1 = CLKIN = 64 MHz
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// CLKOUT2 = CLKIN = 64 MHz
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// ADC is clocked at 64 MHz
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// DAC is clocked at 128 MHz
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static unsigned char common_regs[] = {
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REG_DLL, (DLL_DISABLE_INTERNAL_XTAL_OSC
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REG_CLKOUT, CLKOUT2_EQ_DLL_OVER_2,
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REG_AUX_ADC_CLK, AUX_ADC_CLK_CLK_OVER_4
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usrp_basic::usrp_basic (int which_board,
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struct usb_dev_handle *
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open_interface (struct usb_device *dev),
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const std::string fpga_filename,
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const std::string firmware_filename)
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d_usb_data_rate (16000000), // SWAG, see below
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d_bytes_per_poll ((int) (POLLING_INTERVAL * d_usb_data_rate)),
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d_verbose (false), d_fpga_master_clock_freq(64000000), d_db(2)
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* SWAG: Scientific Wild Ass Guess.
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* d_usb_data_rate is used only to determine how often to poll for over- and under-runs.
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* We defualt it to 1/2 of our best case. Classes derived from usrp_basic (e.g.,
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* usrp_standard_tx and usrp_standard_rx) call set_usb_data_rate() to tell us the
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* actual rate. This doesn't change our throughput, that's determined by the signal
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* processing code in the FPGA (which we know nothing about), and the system limits
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* determined by libusb, fusb_*, and the underlying drivers.
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memset (d_fpga_shadows, 0, sizeof (d_fpga_shadows));
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usrp_one_time_init ();
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if (!usrp_load_standard_bits (which_board, false, fpga_filename, firmware_filename))
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throw std::runtime_error ("usrp_basic/usrp_load_standard_bits");
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struct usb_device *dev = usrp_find_device (which_board);
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fprintf (stderr, "usrp_basic: can't find usrp[%d]\n", which_board);
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throw std::runtime_error ("usrp_basic/usrp_find_device");
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if (!(usrp_usrp_p(dev) && usrp_hw_rev(dev) >= 1)){
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fprintf (stderr, "usrp_basic: sorry, this code only works with USRP revs >= 1\n");
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throw std::runtime_error ("usrp_basic/bad_rev");
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if ((d_udh = open_interface (dev)) == 0)
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throw std::runtime_error ("usrp_basic/open_interface");
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// initialize registers that are common to rx and tx
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if (!usrp_9862_write_many_all (d_udh, common_regs, sizeof (common_regs))){
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fprintf (stderr, "usrp_basic: failed to init common AD9862 regs\n");
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throw std::runtime_error ("usrp_basic/init_9862");
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_write_fpga_reg (FR_MODE, 0); // ensure we're in normal mode
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_write_fpga_reg (FR_DEBUG_EN, 0); // disable debug outputs
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usrp_basic::shutdown_daughterboards()
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// nuke d'boards before we close down USB in ~usrp_basic
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// shutdown() will do any board shutdown while the USRP can still
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for(size_t i = 0; i < d_db.size(); i++)
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for(size_t j = 0; j < d_db[i].size(); j++)
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d_db[i][j]->shutdown();
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usrp_basic::~usrp_basic ()
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// shutdown_daughterboards(); // call from ~usrp_basic_{tx,rx}
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d_db.resize(0); // forget db shared ptrs
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usrp_basic::init_db(usrp_basic_sptr u)
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throw std::invalid_argument("u is not this");
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d_db[0] = instantiate_dbs(d_dbid[0], u, 0);
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d_db[1] = instantiate_dbs(d_dbid[1], u, 1);
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std::vector<db_base_sptr>
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usrp_basic::db(int which_side)
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which_side &= 0x1; // clamp it to avoid any reporting any errors
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return d_db[which_side];
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usrp_basic::is_valid(const usrp_subdev_spec &ss)
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if (ss.side < 0 || ss.side > 1)
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if (ss.subdev < 0 || ss.subdev >= d_db[ss.side].size())
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usrp_basic::selected_subdev(const usrp_subdev_spec &ss)
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throw std::invalid_argument("invalid subdev_spec");
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return d_db[ss.side][ss.subdev];
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usrp_basic::set_usb_data_rate (int usb_data_rate)
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d_usb_data_rate = usb_data_rate;
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d_bytes_per_poll = (int) (usb_data_rate * POLLING_INTERVAL);
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usrp_basic::_write_aux_dac (int slot, int which_dac, int value)
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return usrp_write_aux_dac (d_udh, slot, which_dac, value);
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usrp_basic::_read_aux_adc (int slot, int which_adc, int *value)
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return usrp_read_aux_adc (d_udh, slot, which_adc, value);
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usrp_basic::_read_aux_adc (int slot, int which_adc)
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if (!_read_aux_adc (slot, which_adc, &value))
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usrp_basic::write_eeprom (int i2c_addr, int eeprom_offset, const std::string buf)
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return usrp_eeprom_write (d_udh, i2c_addr, eeprom_offset, buf.data (), buf.size ());
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usrp_basic::read_eeprom (int i2c_addr, int eeprom_offset, int len)
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if (!usrp_eeprom_read (d_udh, i2c_addr, eeprom_offset, buf, len))
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return std::string (buf, len);
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usrp_basic::write_i2c (int i2c_addr, const std::string buf)
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return usrp_i2c_write (d_udh, i2c_addr, buf.data (), buf.size ());
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usrp_basic::read_i2c (int i2c_addr, int len)
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if (!usrp_i2c_read (d_udh, i2c_addr, buf, len))
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return std::string (buf, len);
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usrp_basic::serial_number()
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return usrp_serial_number(d_udh);
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// ----------------------------------------------------------------
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usrp_basic::set_adc_offset (int which_adc, int offset)
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if (which_adc < 0 || which_adc > 3)
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return _write_fpga_reg (FR_ADC_OFFSET_0 + which_adc, offset);
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usrp_basic::set_dac_offset (int which_dac, int offset, int offset_pin)
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if (which_dac < 0 || which_dac > 3)
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int which_codec = which_dac >> 1;
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int tx_a = (which_dac & 0x1) == 0;
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int lo = ((offset & 0x3) << 6) | (offset_pin & 0x1);
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int hi = (offset >> 2);
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ok = _write_9862 (which_codec, REG_TX_A_OFFSET_LO, lo);
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ok &= _write_9862 (which_codec, REG_TX_A_OFFSET_HI, hi);
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ok = _write_9862 (which_codec, REG_TX_B_OFFSET_LO, lo);
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ok &= _write_9862 (which_codec, REG_TX_B_OFFSET_HI, hi);
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usrp_basic::set_adc_buffer_bypass (int which_adc, bool bypass)
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if (which_adc < 0 || which_adc > 3)
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int codec = which_adc >> 1;
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int reg = (which_adc & 1) == 0 ? REG_RX_A : REG_RX_B;
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unsigned char cur_rx;
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unsigned char cur_pwr_dn;
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// If the input buffer is bypassed, we need to power it down too.
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bool ok = _read_9862 (codec, reg, &cur_rx);
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ok &= _read_9862 (codec, REG_RX_PWR_DN, &cur_pwr_dn);
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cur_rx |= RX_X_BYPASS_INPUT_BUFFER;
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cur_pwr_dn |= ((which_adc & 1) == 0) ? RX_PWR_DN_BUF_A : RX_PWR_DN_BUF_B;
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cur_rx &= ~RX_X_BYPASS_INPUT_BUFFER;
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cur_pwr_dn &= ~(((which_adc & 1) == 0) ? RX_PWR_DN_BUF_A : RX_PWR_DN_BUF_B);
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ok &= _write_9862 (codec, reg, cur_rx);
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ok &= _write_9862 (codec, REG_RX_PWR_DN, cur_pwr_dn);
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usrp_basic::set_dc_offset_cl_enable(int bits, int mask)
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return _write_fpga_reg(FR_DC_OFFSET_CL_EN,
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(d_fpga_shadows[FR_DC_OFFSET_CL_EN] & ~mask) | (bits & mask));
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// ----------------------------------------------------------------
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usrp_basic::_write_fpga_reg (int regno, int value)
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fprintf (stdout, "_write_fpga_reg(%3d, 0x%08x)\n", regno, value);
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if (regno >= 0 && regno < MAX_REGS)
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d_fpga_shadows[regno] = value;
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return usrp_write_fpga_reg (d_udh, regno, value);
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usrp_basic::_write_fpga_reg_masked (int regno, int value, int mask)
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//Only use this for registers who actually use a mask in the verilog firmware, like FR_RX_MASTER_SLAVE
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//value is a 16 bits value and mask is a 16 bits mask
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fprintf (stdout, "_write_fpga_reg_masked(%3d, 0x%04x,0x%04x)\n", regno, value, mask);
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if (regno >= 0 && regno < MAX_REGS)
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d_fpga_shadows[regno] = value;
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return usrp_write_fpga_reg (d_udh, regno, (value & 0xffff) | ((mask & 0xffff)<<16));
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usrp_basic::_read_fpga_reg (int regno, int *value)
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return usrp_read_fpga_reg (d_udh, regno, value);
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usrp_basic::_read_fpga_reg (int regno)
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if (!_read_fpga_reg (regno, &value))
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usrp_basic::_write_9862 (int which_codec, int regno, unsigned char value)
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// FIXME really want to enable logging in usrp_prims:usrp_9862_write
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fprintf(stdout, "_write_9862(codec = %d, regno = %2d, val = 0x%02x)\n", which_codec, regno, value);
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return usrp_9862_write (d_udh, which_codec, regno, value);
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usrp_basic::_read_9862 (int which_codec, int regno, unsigned char *value) const
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return usrp_9862_read (d_udh, which_codec, regno, value);
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usrp_basic::_read_9862 (int which_codec, int regno) const
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if (!_read_9862 (which_codec, regno, &value))
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usrp_basic::_write_spi (int optional_header, int enables, int format, std::string buf)
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return usrp_spi_write (d_udh, optional_header, enables, format,
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buf.data(), buf.size());
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usrp_basic::_read_spi (int optional_header, int enables, int format, int len)
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if (!usrp_spi_read (d_udh, optional_header, enables, format, buf, len))
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return std::string (buf, len);
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usrp_basic::_set_led (int which_led, bool on)
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return usrp_set_led (d_udh, which_led, on);
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usrp_basic::write_atr_tx_delay(int value)
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return _write_fpga_reg(FR_ATR_TX_DELAY, value);
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usrp_basic::write_atr_rx_delay(int value)
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return _write_fpga_reg(FR_ATR_RX_DELAY, value);
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* ----------------------------------------------------------------
498
* Routines to access and control daughterboard specific i/o
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* ----------------------------------------------------------------
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slot_id_to_oe_reg (int slot_id)
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static int reg[4] = { FR_OE_0, FR_OE_1, FR_OE_2, FR_OE_3 };
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assert (0 <= slot_id && slot_id < 4);
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slot_id_to_io_reg (int slot_id)
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static int reg[4] = { FR_IO_0, FR_IO_1, FR_IO_2, FR_IO_3 };
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assert (0 <= slot_id && slot_id < 4);
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slot_id_to_refclk_reg(int slot_id)
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static int reg[4] = { FR_TX_A_REFCLK, FR_RX_A_REFCLK, FR_TX_B_REFCLK, FR_RX_B_REFCLK };
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assert (0 <= slot_id && slot_id < 4);
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slot_id_to_atr_mask_reg(int slot_id)
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static int reg[4] = { FR_ATR_MASK_0, FR_ATR_MASK_1, FR_ATR_MASK_2, FR_ATR_MASK_3 };
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assert (0 <= slot_id && slot_id < 4);
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slot_id_to_atr_txval_reg(int slot_id)
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static int reg[4] = { FR_ATR_TXVAL_0, FR_ATR_TXVAL_1, FR_ATR_TXVAL_2, FR_ATR_TXVAL_3 };
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assert (0 <= slot_id && slot_id < 4);
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slot_id_to_atr_rxval_reg(int slot_id)
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static int reg[4] = { FR_ATR_RXVAL_0, FR_ATR_RXVAL_1, FR_ATR_RXVAL_2, FR_ATR_RXVAL_3 };
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assert (0 <= slot_id && slot_id < 4);
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to_slot(txrx_t txrx, int which_side)
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return ((which_side & 0x1) << 1) | ((txrx & 0x1) == C_RX);
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usrp_basic::common_set_pga(txrx_t txrx, int which_amp, double gain)
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if (which_amp < 0 || which_amp > 3)
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gain = std::min(common_pga_max(txrx),
566
std::max(common_pga_min(txrx), gain));
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int codec = which_amp >> 1;
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int int_gain = (int) rint((gain - common_pga_min(txrx)) / common_pga_db_per_step(txrx));
571
if (txrx == C_TX){ // 0 and 1 are same, as are 2 and 3
572
return _write_9862(codec, REG_TX_PGA, int_gain);
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int reg = (which_amp & 1) == 0 ? REG_RX_A : REG_RX_B;
577
// read current value to get input buffer bypass flag.
578
unsigned char cur_rx;
579
if (!_read_9862(codec, reg, &cur_rx))
582
cur_rx = (cur_rx & RX_X_BYPASS_INPUT_BUFFER) | (int_gain & 0x7f);
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return _write_9862(codec, reg, cur_rx);
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usrp_basic::common_pga(txrx_t txrx, int which_amp) const
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if (which_amp < 0 || which_amp > 3)
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int codec = which_amp >> 1;
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bool ok = _read_9862 (codec, REG_TX_PGA, &v);
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return (pga_db_per_step() * v) + pga_min();
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int codec = which_amp >> 1;
604
int reg = (which_amp & 1) == 0 ? REG_RX_A : REG_RX_B;
606
bool ok = _read_9862 (codec, reg, &v);
610
return (pga_db_per_step() * (v & 0x1f)) + pga_min();
615
usrp_basic::common_pga_min(txrx_t txrx) const
624
usrp_basic::common_pga_max(txrx_t txrx) const
633
usrp_basic::common_pga_db_per_step(txrx_t txrx) const
642
usrp_basic::_common_write_oe(txrx_t txrx, int which_side, int value, int mask)
644
if (! (0 <= which_side && which_side <= 1))
647
return _write_fpga_reg(slot_id_to_oe_reg(to_slot(txrx, which_side)),
648
(mask << 16) | (value & 0xffff));
652
usrp_basic::common_write_io(txrx_t txrx, int which_side, int value, int mask)
654
if (! (0 <= which_side && which_side <= 1))
657
return _write_fpga_reg(slot_id_to_io_reg(to_slot(txrx, which_side)),
658
(mask << 16) | (value & 0xffff));
662
usrp_basic::common_read_io(txrx_t txrx, int which_side, int *value)
664
if (! (0 <= which_side && which_side <= 1))
668
int reg = which_side + 1; // FIXME, *very* magic number (fix in serial_io.v)
669
bool ok = _read_fpga_reg(reg, &t);
674
*value = t & 0xffff; // FIXME, more magic
678
*value = (t >> 16) & 0xffff; // FIXME, more magic
684
usrp_basic::common_read_io(txrx_t txrx, int which_side)
687
if (!common_read_io(txrx, which_side, &value))
693
usrp_basic::common_write_refclk(txrx_t txrx, int which_side, int value)
695
if (! (0 <= which_side && which_side <= 1))
698
return _write_fpga_reg(slot_id_to_refclk_reg(to_slot(txrx, which_side)),
703
usrp_basic::common_write_atr_mask(txrx_t txrx, int which_side, int value)
705
if (! (0 <= which_side && which_side <= 1))
708
return _write_fpga_reg(slot_id_to_atr_mask_reg(to_slot(txrx, which_side)),
713
usrp_basic::common_write_atr_txval(txrx_t txrx, int which_side, int value)
715
if (! (0 <= which_side && which_side <= 1))
718
return _write_fpga_reg(slot_id_to_atr_txval_reg(to_slot(txrx, which_side)),
723
usrp_basic::common_write_atr_rxval(txrx_t txrx, int which_side, int value)
725
if (! (0 <= which_side && which_side <= 1))
728
return _write_fpga_reg(slot_id_to_atr_rxval_reg(to_slot(txrx, which_side)),
733
usrp_basic::common_write_aux_dac(txrx_t txrx, int which_side, int which_dac, int value)
735
return _write_aux_dac(to_slot(txrx, which_side), which_dac, value);
739
usrp_basic::common_read_aux_adc(txrx_t txrx, int which_side, int which_adc, int *value)
741
return _read_aux_adc(to_slot(txrx, which_side), which_adc, value);
745
usrp_basic::common_read_aux_adc(txrx_t txrx, int which_side, int which_adc)
747
return _read_aux_adc(to_slot(txrx, which_side), which_adc);
751
////////////////////////////////////////////////////////////////
755
////////////////////////////////////////////////////////////////
757
static unsigned char rx_init_regs[] = {
759
REG_RX_A, 0, // minimum gain = 0x00 (max gain = 0x14)
760
REG_RX_B, 0, // minimum gain = 0x00 (max gain = 0x14)
761
REG_RX_MISC, (RX_MISC_HS_DUTY_CYCLE | RX_MISC_CLK_DUTY),
762
REG_RX_IF, (RX_IF_USE_CLKOUT1
764
REG_RX_DIGITAL, (RX_DIGITAL_2_CHAN)
768
usrp_basic_rx::usrp_basic_rx (int which_board, int fusb_block_size, int fusb_nblocks,
769
const std::string fpga_filename,
770
const std::string firmware_filename
772
: usrp_basic (which_board, open_rx_interface, fpga_filename, firmware_filename),
773
d_devhandle (0), d_ephandle (0),
774
d_bytes_seen (0), d_first_read (true),
777
// initialize rx specific registers
779
if (!usrp_9862_write_many_all (d_udh, rx_init_regs, sizeof (rx_init_regs))){
780
fprintf (stderr, "usrp_basic_rx: failed to init AD9862 RX regs\n");
781
throw std::runtime_error ("usrp_basic_rx/init_9862");
785
// FIXME power down 2nd codec rx path
786
usrp_9862_write (d_udh, 1, REG_RX_PWR_DN, 0x1); // power down everything
789
// Reset the rx path and leave it disabled.
790
set_rx_enable (false);
791
usrp_set_fpga_rx_reset (d_udh, true);
792
usrp_set_fpga_rx_reset (d_udh, false);
794
set_fpga_rx_sample_rate_divisor (2); // usually correct
796
set_dc_offset_cl_enable(0xf, 0xf); // enable DC offset removal control loops
798
probe_rx_slots (false);
800
//d_db[0] = instantiate_dbs(d_dbid[0], this, 0);
801
//d_db[1] = instantiate_dbs(d_dbid[1], this, 1);
803
// check fusb buffering parameters
805
if (fusb_block_size < 0 || fusb_block_size > FUSB_BLOCK_SIZE)
806
throw std::out_of_range ("usrp_basic_rx: invalid fusb_block_size");
808
if (fusb_nblocks < 0)
809
throw std::out_of_range ("usrp_basic_rx: invalid fusb_nblocks");
811
if (fusb_block_size == 0)
812
fusb_block_size = fusb_sysconfig::default_block_size();
814
if (fusb_nblocks == 0)
815
fusb_nblocks = std::max (1, FUSB_BUFFER_SIZE / fusb_block_size);
817
d_devhandle = fusb_sysconfig::make_devhandle (d_udh);
818
d_ephandle = d_devhandle->make_ephandle (USRP_RX_ENDPOINT, true,
819
fusb_block_size, fusb_nblocks);
821
write_atr_mask(0, 0); // zero Rx A Auto Transmit/Receive regs
822
write_atr_txval(0, 0);
823
write_atr_rxval(0, 0);
824
write_atr_mask(1, 0); // zero Rx B Auto Transmit/Receive regs
825
write_atr_txval(1, 0);
826
write_atr_rxval(1, 0);
829
static unsigned char rx_fini_regs[] = {
830
REG_RX_PWR_DN, 0x1 // power down everything
833
usrp_basic_rx::~usrp_basic_rx ()
835
if (!set_rx_enable (false)){
836
fprintf (stderr, "usrp_basic_rx: set_fpga_rx_enable failed\n");
844
if (!usrp_9862_write_many_all (d_udh, rx_fini_regs, sizeof (rx_fini_regs))){
845
fprintf (stderr, "usrp_basic_rx: failed to fini AD9862 RX regs\n");
848
shutdown_daughterboards();
853
usrp_basic_rx::start ()
855
if (!usrp_basic::start ()) // invoke parent's method
858
// fire off reads before asserting rx_enable
860
if (!d_ephandle->start ()){
861
fprintf (stderr, "usrp_basic_rx: failed to start end point streaming");
866
if (!set_rx_enable (true)){
867
fprintf (stderr, "usrp_basic_rx: set_rx_enable failed\n");
876
usrp_basic_rx::stop ()
878
bool ok = usrp_basic::stop();
880
if (!set_rx_enable(false)){
881
fprintf (stderr, "usrp_basic_rx: set_rx_enable(false) failed\n");
886
if (!d_ephandle->stop()){
887
fprintf (stderr, "usrp_basic_rx: failed to stop end point streaming");
896
usrp_basic_rx::make (int which_board, int fusb_block_size, int fusb_nblocks,
897
const std::string fpga_filename,
898
const std::string firmware_filename)
900
usrp_basic_rx *u = 0;
903
u = new usrp_basic_rx (which_board, fusb_block_size, fusb_nblocks,
904
fpga_filename, firmware_filename);
916
usrp_basic_rx::set_fpga_rx_sample_rate_divisor (unsigned int div)
918
return _write_fpga_reg (FR_RX_SAMPLE_RATE_DIV, div - 1);
923
* \brief read data from the D/A's via the FPGA.
924
* \p len must be a multiple of 512 bytes.
926
* \returns the number of bytes read, or -1 on error.
928
* If overrun is non-NULL it will be set true iff an RX overrun is detected.
931
usrp_basic_rx::read (void *buf, int len, bool *overrun)
938
if (len < 0 || (len % 512) != 0){
939
fprintf (stderr, "usrp_basic_rx::read: invalid length = %d\n", len);
943
r = d_ephandle->read (buf, len);
948
* In many cases, the FPGA reports an rx overrun right after we
949
* enable the Rx path. If this is our first read, check for the
950
* overrun to clear the condition, then ignore the result.
952
if (0 && d_first_read){ // FIXME
953
d_first_read = false;
955
usrp_check_rx_overrun (d_udh, &bogus_overrun);
958
if (overrun != 0 && d_bytes_seen >= d_bytes_per_poll){
960
if (!usrp_check_rx_overrun (d_udh, overrun)){
961
fprintf (stderr, "usrp_basic_rx: usrp_check_rx_overrun failed\n");
970
usrp_basic_rx::set_rx_enable (bool on)
973
return usrp_set_fpga_rx_enable (d_udh, on);
976
// conditional disable, return prev state
978
usrp_basic_rx::disable_rx ()
980
bool enabled = rx_enable ();
982
set_rx_enable (false);
988
usrp_basic_rx::restore_rx (bool on)
990
if (on != rx_enable ())
995
usrp_basic_rx::probe_rx_slots (bool verbose)
997
struct usrp_dboard_eeprom eeprom;
998
static int slot_id_map[2] = { SLOT_RX_A, SLOT_RX_B };
999
static const char *slot_name[2] = { "RX d'board A", "RX d'board B" };
1001
for (int i = 0; i < 2; i++){
1002
int slot_id = slot_id_map [i];
1003
const char *msg = 0;
1004
usrp_dbeeprom_status_t s = usrp_read_dboard_eeprom (d_udh, slot_id, &eeprom);
1008
d_dbid[i] = eeprom.id;
1009
msg = usrp_dbid_to_string (eeprom.id).c_str ();
1010
set_adc_offset (2*i+0, eeprom.offset[0]);
1011
set_adc_offset (2*i+1, eeprom.offset[1]);
1012
_write_fpga_reg (slot_id_to_oe_reg(slot_id), (0xffff << 16) | eeprom.oe);
1013
_write_fpga_reg (slot_id_to_io_reg(slot_id), (0xffff << 16) | 0x0000);
1016
case UDBE_NO_EEPROM:
1019
_write_fpga_reg (slot_id_to_oe_reg(slot_id), (0xffff << 16) | 0x0000);
1020
_write_fpga_reg (slot_id_to_io_reg(slot_id), (0xffff << 16) | 0x0000);
1023
case UDBE_INVALID_EEPROM:
1025
msg = "Invalid EEPROM contents";
1026
_write_fpga_reg (slot_id_to_oe_reg(slot_id), (0xffff << 16) | 0x0000);
1027
_write_fpga_reg (slot_id_to_io_reg(slot_id), (0xffff << 16) | 0x0000);
1037
fprintf (stderr, "%s: %s\n", slot_name[i], msg);
1043
usrp_basic_rx::set_pga (int which_amp, double gain)
1045
return common_set_pga(C_RX, which_amp, gain);
1049
usrp_basic_rx::pga(int which_amp) const
1051
return common_pga(C_RX, which_amp);
1055
usrp_basic_rx::pga_min() const
1057
return common_pga_min(C_RX);
1061
usrp_basic_rx::pga_max() const
1063
return common_pga_max(C_RX);
1067
usrp_basic_rx::pga_db_per_step() const
1069
return common_pga_db_per_step(C_RX);
1073
usrp_basic_rx::_write_oe (int which_side, int value, int mask)
1075
return _common_write_oe(C_RX, which_side, value, mask);
1079
usrp_basic_rx::write_io (int which_side, int value, int mask)
1081
return common_write_io(C_RX, which_side, value, mask);
1085
usrp_basic_rx::read_io (int which_side, int *value)
1087
return common_read_io(C_RX, which_side, value);
1091
usrp_basic_rx::read_io (int which_side)
1093
return common_read_io(C_RX, which_side);
1097
usrp_basic_rx::write_refclk(int which_side, int value)
1099
return common_write_refclk(C_RX, which_side, value);
1103
usrp_basic_rx::write_atr_mask(int which_side, int value)
1105
return common_write_atr_mask(C_RX, which_side, value);
1109
usrp_basic_rx::write_atr_txval(int which_side, int value)
1111
return common_write_atr_txval(C_RX, which_side, value);
1115
usrp_basic_rx::write_atr_rxval(int which_side, int value)
1117
return common_write_atr_rxval(C_RX, which_side, value);
1121
usrp_basic_rx::write_aux_dac (int which_side, int which_dac, int value)
1123
return common_write_aux_dac(C_RX, which_side, which_dac, value);
1127
usrp_basic_rx::read_aux_adc (int which_side, int which_adc, int *value)
1129
return common_read_aux_adc(C_RX, which_side, which_adc, value);
1133
usrp_basic_rx::read_aux_adc (int which_side, int which_adc)
1135
return common_read_aux_adc(C_RX, which_side, which_adc);
1139
usrp_basic_rx::block_size () const { return d_ephandle->block_size(); }
1141
////////////////////////////////////////////////////////////////
1145
////////////////////////////////////////////////////////////////
1149
// DAC input rate 64 MHz interleaved for a total input rate of 128 MHz
1150
// DAC input is latched on rising edge of CLKOUT2
1153
// coarse modulator disabled
1156
static unsigned char tx_init_regs[] = {
1158
REG_TX_A_OFFSET_LO, 0,
1159
REG_TX_A_OFFSET_HI, 0,
1160
REG_TX_B_OFFSET_LO, 0,
1161
REG_TX_B_OFFSET_HI, 0,
1162
REG_TX_A_GAIN, (TX_X_GAIN_COARSE_FULL | 0),
1163
REG_TX_B_GAIN, (TX_X_GAIN_COARSE_FULL | 0),
1164
REG_TX_PGA, 0xff, // maximum gain (0 dB)
1166
REG_TX_IF, (TX_IF_USE_CLKOUT1
1170
| TX_IF_INTERLEAVED),
1171
REG_TX_DIGITAL, (TX_DIGITAL_2_DATA_PATHS
1172
| TX_DIGITAL_INTERPOLATE_4X),
1173
REG_TX_MODULATOR, (TX_MODULATOR_DISABLE_NCO
1174
| TX_MODULATOR_COARSE_MODULATION_NONE),
1175
REG_TX_NCO_FTW_7_0, 0,
1176
REG_TX_NCO_FTW_15_8, 0,
1177
REG_TX_NCO_FTW_23_16, 0
1180
usrp_basic_tx::usrp_basic_tx (int which_board, int fusb_block_size, int fusb_nblocks,
1181
const std::string fpga_filename,
1182
const std::string firmware_filename)
1183
: usrp_basic (which_board, open_tx_interface, fpga_filename, firmware_filename),
1184
d_devhandle (0), d_ephandle (0),
1185
d_bytes_seen (0), d_first_write (true),
1188
if (!usrp_9862_write_many_all (d_udh, tx_init_regs, sizeof (tx_init_regs))){
1189
fprintf (stderr, "usrp_basic_tx: failed to init AD9862 TX regs\n");
1190
throw std::runtime_error ("usrp_basic_tx/init_9862");
1194
// FIXME power down 2nd codec tx path
1195
usrp_9862_write (d_udh, 1, REG_TX_PWR_DN,
1196
(TX_PWR_DN_TX_DIGITAL
1197
| TX_PWR_DN_TX_ANALOG_BOTH));
1200
// Reset the tx path and leave it disabled.
1201
set_tx_enable (false);
1202
usrp_set_fpga_tx_reset (d_udh, true);
1203
usrp_set_fpga_tx_reset (d_udh, false);
1205
set_fpga_tx_sample_rate_divisor (4); // we're using interp x4
1207
probe_tx_slots (false);
1209
//d_db[0] = instantiate_dbs(d_dbid[0], this, 0);
1210
//d_db[1] = instantiate_dbs(d_dbid[1], this, 1);
1212
// check fusb buffering parameters
1214
if (fusb_block_size < 0 || fusb_block_size > FUSB_BLOCK_SIZE)
1215
throw std::out_of_range ("usrp_basic_rx: invalid fusb_block_size");
1217
if (fusb_nblocks < 0)
1218
throw std::out_of_range ("usrp_basic_rx: invalid fusb_nblocks");
1220
if (fusb_block_size == 0)
1221
fusb_block_size = FUSB_BLOCK_SIZE;
1223
if (fusb_nblocks == 0)
1224
fusb_nblocks = std::max (1, FUSB_BUFFER_SIZE / fusb_block_size);
1226
d_devhandle = fusb_sysconfig::make_devhandle (d_udh);
1227
d_ephandle = d_devhandle->make_ephandle (USRP_TX_ENDPOINT, false,
1228
fusb_block_size, fusb_nblocks);
1230
write_atr_mask(0, 0); // zero Tx A Auto Transmit/Receive regs
1231
write_atr_txval(0, 0);
1232
write_atr_rxval(0, 0);
1233
write_atr_mask(1, 0); // zero Tx B Auto Transmit/Receive regs
1234
write_atr_txval(1, 0);
1235
write_atr_rxval(1, 0);
1239
static unsigned char tx_fini_regs[] = {
1240
REG_TX_PWR_DN, (TX_PWR_DN_TX_DIGITAL
1241
| TX_PWR_DN_TX_ANALOG_BOTH),
1242
REG_TX_MODULATOR, (TX_MODULATOR_DISABLE_NCO
1243
| TX_MODULATOR_COARSE_MODULATION_NONE)
1246
usrp_basic_tx::~usrp_basic_tx ()
1248
d_ephandle->stop ();
1252
if (!usrp_9862_write_many_all (d_udh, tx_fini_regs, sizeof (tx_fini_regs))){
1253
fprintf (stderr, "usrp_basic_tx: failed to fini AD9862 TX regs\n");
1256
shutdown_daughterboards();
1260
usrp_basic_tx::start ()
1262
if (!usrp_basic::start ())
1265
if (!set_tx_enable (true)){
1266
fprintf (stderr, "usrp_basic_tx: set_tx_enable failed\n");
1271
if (!d_ephandle->start ()){
1272
fprintf (stderr, "usrp_basic_tx: failed to start end point streaming");
1281
usrp_basic_tx::stop ()
1283
bool ok = usrp_basic::stop ();
1285
if (!d_ephandle->stop ()){
1286
fprintf (stderr, "usrp_basic_tx: failed to stop end point streaming");
1291
if (!set_tx_enable (false)){
1292
fprintf (stderr, "usrp_basic_tx: set_tx_enable(false) failed\n");
1301
usrp_basic_tx::make (int which_board, int fusb_block_size, int fusb_nblocks,
1302
const std::string fpga_filename,
1303
const std::string firmware_filename)
1305
usrp_basic_tx *u = 0;
1308
u = new usrp_basic_tx (which_board, fusb_block_size, fusb_nblocks,
1309
fpga_filename, firmware_filename);
1321
usrp_basic_tx::set_fpga_tx_sample_rate_divisor (unsigned int div)
1323
return _write_fpga_reg (FR_TX_SAMPLE_RATE_DIV, div - 1);
1327
* \brief Write data to the A/D's via the FPGA.
1329
* \p len must be a multiple of 512 bytes.
1330
* \returns number of bytes written or -1 on error.
1332
* if \p underrun is non-NULL, it will be set to true iff
1333
* a transmit underrun condition is detected.
1336
usrp_basic_tx::write (const void *buf, int len, bool *underrun)
1343
if (len < 0 || (len % 512) != 0){
1344
fprintf (stderr, "usrp_basic_tx::write: invalid length = %d\n", len);
1348
r = d_ephandle->write (buf, len);
1353
* In many cases, the FPGA reports an tx underrun right after we
1354
* enable the Tx path. If this is our first write, check for the
1355
* underrun to clear the condition, then ignore the result.
1357
if (d_first_write && d_bytes_seen >= 4 * FUSB_BLOCK_SIZE){
1358
d_first_write = false;
1359
bool bogus_underrun;
1360
usrp_check_tx_underrun (d_udh, &bogus_underrun);
1363
if (underrun != 0 && d_bytes_seen >= d_bytes_per_poll){
1365
if (!usrp_check_tx_underrun (d_udh, underrun)){
1366
fprintf (stderr, "usrp_basic_tx: usrp_check_tx_underrun failed\n");
1375
usrp_basic_tx::wait_for_completion ()
1377
d_ephandle->wait_for_completion ();
1381
usrp_basic_tx::set_tx_enable (bool on)
1384
// fprintf (stderr, "set_tx_enable %d\n", on);
1385
return usrp_set_fpga_tx_enable (d_udh, on);
1388
// conditional disable, return prev state
1390
usrp_basic_tx::disable_tx ()
1392
bool enabled = tx_enable ();
1394
set_tx_enable (false);
1400
usrp_basic_tx::restore_tx (bool on)
1402
if (on != tx_enable ())
1407
usrp_basic_tx::probe_tx_slots (bool verbose)
1409
struct usrp_dboard_eeprom eeprom;
1410
static int slot_id_map[2] = { SLOT_TX_A, SLOT_TX_B };
1411
static const char *slot_name[2] = { "TX d'board A", "TX d'board B" };
1413
for (int i = 0; i < 2; i++){
1414
int slot_id = slot_id_map [i];
1415
const char *msg = 0;
1416
usrp_dbeeprom_status_t s = usrp_read_dboard_eeprom (d_udh, slot_id, &eeprom);
1420
d_dbid[i] = eeprom.id;
1421
msg = usrp_dbid_to_string (eeprom.id).c_str ();
1422
// FIXME, figure out interpretation of dc offset for TX d'boards
1423
// offset = (eeprom.offset[1] << 16) | (eeprom.offset[0] & 0xffff);
1424
_write_fpga_reg (slot_id_to_oe_reg(slot_id), (0xffff << 16) | eeprom.oe);
1425
_write_fpga_reg (slot_id_to_io_reg(slot_id), (0xffff << 16) | 0x0000);
1428
case UDBE_NO_EEPROM:
1431
_write_fpga_reg (slot_id_to_oe_reg(slot_id), (0xffff << 16) | 0x0000);
1432
_write_fpga_reg (slot_id_to_io_reg(slot_id), (0xffff << 16) | 0x0000);
1435
case UDBE_INVALID_EEPROM:
1437
msg = "Invalid EEPROM contents";
1438
_write_fpga_reg (slot_id_to_oe_reg(slot_id), (0xffff << 16) | 0x0000);
1439
_write_fpga_reg (slot_id_to_io_reg(slot_id), (0xffff << 16) | 0x0000);
1449
fprintf (stderr, "%s: %s\n", slot_name[i], msg);
1455
usrp_basic_tx::set_pga (int which_amp, double gain)
1457
return common_set_pga(C_TX, which_amp, gain);
1461
usrp_basic_tx::pga (int which_amp) const
1463
return common_pga(C_TX, which_amp);
1467
usrp_basic_tx::pga_min() const
1469
return common_pga_min(C_TX);
1473
usrp_basic_tx::pga_max() const
1475
return common_pga_max(C_TX);
1479
usrp_basic_tx::pga_db_per_step() const
1481
return common_pga_db_per_step(C_TX);
1485
usrp_basic_tx::_write_oe (int which_side, int value, int mask)
1487
return _common_write_oe(C_TX, which_side, value, mask);
1491
usrp_basic_tx::write_io (int which_side, int value, int mask)
1493
return common_write_io(C_TX, which_side, value, mask);
1497
usrp_basic_tx::read_io (int which_side, int *value)
1499
return common_read_io(C_TX, which_side, value);
1503
usrp_basic_tx::read_io (int which_side)
1505
return common_read_io(C_TX, which_side);
1509
usrp_basic_tx::write_refclk(int which_side, int value)
1511
return common_write_refclk(C_TX, which_side, value);
1515
usrp_basic_tx::write_atr_mask(int which_side, int value)
1517
return common_write_atr_mask(C_TX, which_side, value);
1521
usrp_basic_tx::write_atr_txval(int which_side, int value)
1523
return common_write_atr_txval(C_TX, which_side, value);
1527
usrp_basic_tx::write_atr_rxval(int which_side, int value)
1529
return common_write_atr_rxval(C_TX, which_side, value);
1533
usrp_basic_tx::write_aux_dac (int which_side, int which_dac, int value)
1535
return common_write_aux_dac(C_TX, which_side, which_dac, value);
1539
usrp_basic_tx::read_aux_adc (int which_side, int which_adc, int *value)
1541
return common_read_aux_adc(C_TX, which_side, which_adc, value);
1545
usrp_basic_tx::read_aux_adc (int which_side, int which_adc)
1547
return common_read_aux_adc(C_TX, which_side, which_adc);
1551
usrp_basic_tx::block_size () const { return d_ephandle->block_size(); }
added
removed
usrp/host/lib/legacy/usrp_basic.cc
