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* Copyright 2003,2004,2008 Free Software Foundation, Inc.
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* This file is part of GNU Radio
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* GNU Radio is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3, or (at your option)
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* GNU Radio is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License
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* along with GNU Radio; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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* ----------------------------------------------------------------------
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* Mid level interface to the Universal Software Radio Peripheral (Rev 1)
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* These classes implement the basic functionality for talking to the
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* USRP. They try to be as independent of the signal processing code
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* in FPGA as possible. They implement access to the low level
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* peripherals on the board, provide a common way for reading and
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* writing registers in the FPGA, and provide the high speed interface
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* to streaming data across the USB.
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* It is expected that subclasses will be derived that provide
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* access to the functionality to a particular FPGA configuration.
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* ----------------------------------------------------------------------
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#ifndef INCLUDED_USRP_BASIC_H
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#define INCLUDED_USRP_BASIC_H
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#include <usrp_slots.h>
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#include <boost/utility.hpp>
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#include <usrp_subdev_spec.h>
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struct usb_dev_handle;
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* \brief abstract base class for usrp operations
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class usrp_basic : boost::noncopyable
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void shutdown_daughterboards();
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struct usb_dev_handle *d_udh;
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int d_usb_data_rate; // bytes/sec
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int d_bytes_per_poll; // how often to poll for overruns
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long d_fpga_master_clock_freq;
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static const int MAX_REGS = 128;
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unsigned int d_fpga_shadows[MAX_REGS];
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int d_dbid[2]; // daughterboard ID's (side A, side B)
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* Shared pointers to subclasses of db_base.
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* The outer vector is of length 2 (0 = side A, 1 = side B). The
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* inner vectors are of length 1, 2 or 3 depending on the number of
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* subdevices implemented by the daugherboard. At this time, only
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* the Basic Rx and LF Rx implement more than 1 subdevice.
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std::vector< std::vector<db_base_sptr> > d_db;
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//! One time call, made only only from usrp_standard_*::make after shared_ptr is created.
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void init_db(usrp_basic_sptr u);
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usrp_basic (int which_board,
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struct usb_dev_handle *open_interface (struct usb_device *dev),
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const std::string fpga_filename = "",
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const std::string firmware_filename = "");
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* \brief advise usrp_basic of usb data rate (bytes/sec)
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* N.B., this doesn't tweak any hardware. Derived classes
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* should call this to inform us of the data rate whenever it's
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* first set or if it changes.
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* \param usb_data_rate bytes/sec
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void set_usb_data_rate (int usb_data_rate);
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* \brief Write auxiliary digital to analog converter.
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* \param slot Which Tx or Rx slot to write.
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* N.B., SLOT_TX_A and SLOT_RX_A share the same AUX DAC's.
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* SLOT_TX_B and SLOT_RX_B share the same AUX DAC's.
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* \param which_dac [0,3] RX slots must use only 0 and 1. TX slots must use only 2 and 3.
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* \param value [0,4095]
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* \returns true iff successful
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bool _write_aux_dac (int slot, int which_dac, int value);
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* \brief Read auxiliary analog to digital converter.
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* \param slot 2-bit slot number. E.g., SLOT_TX_A
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* \param which_adc [0,1]
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* \param value return 12-bit value [0,4095]
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* \returns true iff successful
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bool _read_aux_adc (int slot, int which_adc, int *value);
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* \brief Read auxiliary analog to digital converter.
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* \param slot 2-bit slot number. E.g., SLOT_TX_A
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* \param which_adc [0,1]
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* \returns value in the range [0,4095] if successful, else READ_FAILED.
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int _read_aux_adc (int slot, int which_adc);
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virtual ~usrp_basic ();
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* Return a vector of vectors that contain shared pointers
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* to the daughterboard instance(s) associated with the specified side.
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* It is an error to use the returned objects after the usrp_basic
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* object has been destroyed.
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std::vector<std::vector<db_base_sptr> > db() const { return d_db; }
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* Return a vector of size >= 1 that contains shared pointers
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* to the daughterboard instance(s) associated with the specified side.
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* \param which_side [0,1] which daughterboard
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* It is an error to use the returned objects after the usrp_basic
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* object has been destroyed.
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std::vector<db_base_sptr> db(int which_side);
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* \brief is the subdev_spec valid?
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bool is_valid(const usrp_subdev_spec &ss);
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* \brief given a subdev_spec, return the corresponding daughterboard object.
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* \throws std::invalid_ argument if ss is invalid.
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* \param ss specifies the side and subdevice
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db_base_sptr selected_subdev(const usrp_subdev_spec &ss);
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* \brief return frequency of master oscillator on USRP
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long fpga_master_clock_freq () const { return d_fpga_master_clock_freq; }
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* Tell API that the master oscillator on the USRP is operating at a non-standard
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* fixed frequency. This is only needed for custom USRP hardware modified to
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* operate at a different frequency from the default factory configuration. This
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* function must be called prior to any other API function.
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* \param master_clock USRP2 FPGA master clock frequency in Hz (10..64 MHz)
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void set_fpga_master_clock_freq (long master_clock) { d_fpga_master_clock_freq = master_clock; }
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* \returns usb data rate in bytes/sec
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int usb_data_rate () const { return d_usb_data_rate; }
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void set_verbose (bool on) { d_verbose = on; }
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//! magic value used on alternate register read interfaces
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static const int READ_FAILED = -99999;
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* \brief Write EEPROM on motherboard or any daughterboard.
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* \param i2c_addr I2C bus address of EEPROM
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* \param eeprom_offset byte offset in EEPROM to begin writing
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* \param buf the data to write
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* \returns true iff sucessful
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bool write_eeprom (int i2c_addr, int eeprom_offset, const std::string buf);
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* \brief Read EEPROM on motherboard or any daughterboard.
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* \param i2c_addr I2C bus address of EEPROM
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* \param eeprom_offset byte offset in EEPROM to begin reading
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* \param len number of bytes to read
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* \returns the data read if successful, else a zero length string.
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std::string read_eeprom (int i2c_addr, int eeprom_offset, int len);
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* \brief Write to I2C peripheral
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* \param i2c_addr I2C bus address (7-bits)
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* \param buf the data to write
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* \returns true iff successful
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* Writes are limited to a maximum of of 64 bytes.
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bool write_i2c (int i2c_addr, const std::string buf);
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* \brief Read from I2C peripheral
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* \param i2c_addr I2C bus address (7-bits)
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* \param len number of bytes to read
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* \returns the data read if successful, else a zero length string.
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* Reads are limited to a maximum of 64 bytes.
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std::string read_i2c (int i2c_addr, int len);
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* \brief Set ADC offset correction
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* \param which_adc which ADC[0,3]: 0 = RX_A I, 1 = RX_A Q...
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* \param offset 16-bit value to subtract from raw ADC input.
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bool set_adc_offset (int which_adc, int offset);
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* \brief Set DAC offset correction
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* \param which_dac which DAC[0,3]: 0 = TX_A I, 1 = TX_A Q...
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* \param offset 10-bit offset value (ambiguous format: See AD9862 datasheet).
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* \param offset_pin 1-bit value. If 0 offset applied to -ve differential pin;
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* If 1 offset applied to +ve differential pin.
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bool set_dac_offset (int which_dac, int offset, int offset_pin);
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* \brief Control ADC input buffer
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* \param which_adc which ADC[0,3]
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* \param bypass if non-zero, bypass input buffer and connect input
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* directly to switched cap SHA input of RxPGA.
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bool set_adc_buffer_bypass (int which_adc, bool bypass);
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* \brief Enable/disable automatic DC offset removal control loop in FPGA
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* \param bits which control loops to enable
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* \param mask which \p bits to pay attention to
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* If the corresponding bit is set, enable the automatic DC
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* offset correction control loop.
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* The 4 low bits are significant:
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* By default the control loop is enabled on all ADC's.
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bool set_dc_offset_cl_enable(int bits, int mask);
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* \brief return the usrp's serial number.
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* \returns non-zero length string iff successful.
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std::string serial_number();
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* \brief Return daughterboard ID for given side [0,1].
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* \param which_side [0,1] which daughterboard
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* \return daughterboard id >= 0 if successful
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* \return -1 if no daugherboard
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* \return -2 if invalid EEPROM on daughterboard
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virtual int daughterboard_id (int which_side) const = 0;
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* \brief Clock ticks to delay rising of T/R signal
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* \sa write_atr_mask, write_atr_txval, write_atr_rxval
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bool write_atr_tx_delay(int value);
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* \brief Clock ticks to delay falling edge of T/R signal
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* \sa write_atr_mask, write_atr_txval, write_atr_rxval
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bool write_atr_rx_delay(int value);
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// ================================================================
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// Routines to access and control daughterboard specific i/o
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// Those with a common_ prefix access either the Tx or Rx side depending
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// on the txrx parameter. Those without the common_ prefix are virtual
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// and are overriden in usrp_basic_rx and usrp_basic_tx to access the
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// the Rx or Tx sides automatically. We provide the common_ versions
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// for those daughterboards such as the WBX and XCVR2450 that share
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// h/w resources (such as the LO) between the Tx and Rx sides.
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// ----------------------------------------------------------------
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// BEGIN common_ daughterboard control functions
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* \brief Set Programmable Gain Amplifier(PGA)
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* \param txrx Tx or Rx?
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* \param which_amp which amp [0,3]
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* \param gain_in_db gain value(linear in dB)
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* gain is rounded to closest setting supported by hardware.
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* \returns true iff sucessful.
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* \sa pga_min(), pga_max(), pga_db_per_step()
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bool common_set_pga(txrx_t txrx, int which_amp, double gain_in_db);
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* \brief Return programmable gain amplifier gain setting in dB.
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* \param txrx Tx or Rx?
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* \param which_amp which amp [0,3]
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double common_pga(txrx_t txrx, int which_amp) const;
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* \brief Return minimum legal PGA gain in dB.
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* \param txrx Tx or Rx?
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double common_pga_min(txrx_t txrx) const;
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* \brief Return maximum legal PGA gain in dB.
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* \param txrx Tx or Rx?
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double common_pga_max(txrx_t txrx) const;
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* \brief Return hardware step size of PGA(linear in dB).
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* \param txrx Tx or Rx?
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double common_pga_db_per_step(txrx_t txrx) const;
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* \brief Write direction register(output enables) for pins that go to daughterboard.
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* \param txrx Tx or Rx?
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* \param which_side [0,1] which size
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* \param value value to write into register
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* \param mask which bits of value to write into reg
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* Each d'board has 16-bits of general purpose i/o.
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* Setting the bit makes it an output from the FPGA to the d'board.
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* This register is initialized based on a value stored in the
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* d'board EEPROM. In general, you shouldn't be using this routine
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* without a very good reason. Using this method incorrectly will
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* kill your USRP motherboard and/or daughterboard.
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bool _common_write_oe(txrx_t txrx, int which_side, int value, int mask);
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* \brief Write daughterboard i/o pin value
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* \param txrx Tx or Rx?
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* \param which_side [0,1] which d'board
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* \param value value to write into register
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* \param mask which bits of value to write into reg
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bool common_write_io(txrx_t txrx, int which_side, int value, int mask);
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* \brief Read daughterboard i/o pin value
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* \param txrx Tx or Rx?
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* \param which_side [0,1] which d'board
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* \param value output
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bool common_read_io(txrx_t txrx, int which_side, int *value);
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* \brief Read daughterboard i/o pin value
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* \param txrx Tx or Rx?
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* \param which_side [0,1] which d'board
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* \returns register value if successful, else READ_FAILED
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int common_read_io(txrx_t txrx, int which_side);
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* \brief Write daughterboard refclk config register
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* \param txrx Tx or Rx?
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* \param which_side [0,1] which d'board
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* \param value value to write into register, see below
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* Control whether a reference clock is sent to the daughterboards,
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* and what frequency. The refclk is sent on d'board i/o pin 0.
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* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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* +-----------------------------------------------+-+------------+
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* | Reserved (Must be zero) |E| DIVISOR |
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* +-----------------------------------------------+-+------------+
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* Bit 7 -- 1 turns on refclk, 0 allows IO use
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* Bits 6:0 Divider value
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bool common_write_refclk(txrx_t txrx, int which_side, int value);
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* \brief Automatic Transmit/Receive switching
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* If automatic transmit/receive (ATR) switching is enabled in the
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* FR_ATR_CTL register, the presence or absence of data in the FPGA
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* transmit fifo selects between two sets of values for each of the 4
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* banks of daughterboard i/o pins.
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* Each daughterboard slot has 3 16-bit registers associated with it:
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* FR_ATR_MASK_*, FR_ATR_TXVAL_* and FR_ATR_RXVAL_*
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* FR_ATR_MASK_{0,1,2,3}:
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* These registers determine which of the daugherboard i/o pins are
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* affected by ATR switching. If a bit in the mask is set, the
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* corresponding i/o bit is controlled by ATR, else it's output
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* value comes from the normal i/o pin output register:
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* FR_ATR_TXVAL_{0,1,2,3}:
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* FR_ATR_RXVAL_{0,1,2,3}:
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* If the Tx fifo contains data, then the bits from TXVAL that are
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* selected by MASK are output. Otherwise, the bits from RXVAL that
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* are selected by MASK are output.
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bool common_write_atr_mask(txrx_t txrx, int which_side, int value);
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bool common_write_atr_txval(txrx_t txrx, int which_side, int value);
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bool common_write_atr_rxval(txrx_t txrx, int which_side, int value);
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* \brief Write auxiliary digital to analog converter.
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* \param txrx Tx or Rx?
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* \param which_side [0,1] which d'board
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* N.B., SLOT_TX_A and SLOT_RX_A share the same AUX DAC's.
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* SLOT_TX_B and SLOT_RX_B share the same AUX DAC's.
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* \param which_dac [2,3] TX slots must use only 2 and 3.
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* \param value [0,4095]
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* \returns true iff successful
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bool common_write_aux_dac(txrx_t txrx, int which_side, int which_dac, int value);
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* \brief Read auxiliary analog to digital converter.
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* \param txrx Tx or Rx?
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* \param which_side [0,1] which d'board
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* \param which_adc [0,1]
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* \param value return 12-bit value [0,4095]
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* \returns true iff successful
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bool common_read_aux_adc(txrx_t txrx, int which_side, int which_adc, int *value);
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* \brief Read auxiliary analog to digital converter.
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* \param txrx Tx or Rx?
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* \param which_side [0,1] which d'board
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* \param which_adc [0,1]
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* \returns value in the range [0,4095] if successful, else READ_FAILED.
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int common_read_aux_adc(txrx_t txrx, int which_side, int which_adc);
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// END common_ daughterboard control functions
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// ----------------------------------------------------------------
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// BEGIN virtual daughterboard control functions
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* \brief Set Programmable Gain Amplifier (PGA)
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* \param which_amp which amp [0,3]
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* \param gain_in_db gain value (linear in dB)
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* gain is rounded to closest setting supported by hardware.
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* \returns true iff sucessful.
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* \sa pga_min(), pga_max(), pga_db_per_step()
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virtual bool set_pga (int which_amp, double gain_in_db) = 0;
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* \brief Return programmable gain amplifier gain setting in dB.
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* \param which_amp which amp [0,3]
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virtual double pga (int which_amp) const = 0;
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* \brief Return minimum legal PGA gain in dB.
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virtual double pga_min () const = 0;
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* \brief Return maximum legal PGA gain in dB.
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virtual double pga_max () const = 0;
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* \brief Return hardware step size of PGA (linear in dB).
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virtual double pga_db_per_step () const = 0;
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* \brief Write direction register (output enables) for pins that go to daughterboard.
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* \param which_side [0,1] which size
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* \param value value to write into register
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* \param mask which bits of value to write into reg
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* Each d'board has 16-bits of general purpose i/o.
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* Setting the bit makes it an output from the FPGA to the d'board.
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* This register is initialized based on a value stored in the
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* d'board EEPROM. In general, you shouldn't be using this routine
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* without a very good reason. Using this method incorrectly will
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* kill your USRP motherboard and/or daughterboard.
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virtual bool _write_oe (int which_side, int value, int mask) = 0;
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* \brief Write daughterboard i/o pin value
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* \param which_side [0,1] which d'board
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* \param value value to write into register
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* \param mask which bits of value to write into reg
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virtual bool write_io (int which_side, int value, int mask) = 0;
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* \brief Read daughterboard i/o pin value
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* \param which_side [0,1] which d'board
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* \param value output
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virtual bool read_io (int which_side, int *value) = 0;
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* \brief Read daughterboard i/o pin value
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* \param which_side [0,1] which d'board
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* \returns register value if successful, else READ_FAILED
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virtual int read_io (int which_side) = 0;
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* \brief Write daughterboard refclk config register
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* \param which_side [0,1] which d'board
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* \param value value to write into register, see below
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* Control whether a reference clock is sent to the daughterboards,
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* and what frequency. The refclk is sent on d'board i/o pin 0.
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* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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* +-----------------------------------------------+-+------------+
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* | Reserved (Must be zero) |E| DIVISOR |
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* +-----------------------------------------------+-+------------+
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* Bit 7 -- 1 turns on refclk, 0 allows IO use
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* Bits 6:0 Divider value
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virtual bool write_refclk(int which_side, int value) = 0;
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virtual bool write_atr_mask(int which_side, int value) = 0;
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virtual bool write_atr_txval(int which_side, int value) = 0;
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virtual bool write_atr_rxval(int which_side, int value) = 0;
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* \brief Write auxiliary digital to analog converter.
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* \param which_side [0,1] which d'board
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* N.B., SLOT_TX_A and SLOT_RX_A share the same AUX DAC's.
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* SLOT_TX_B and SLOT_RX_B share the same AUX DAC's.
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* \param which_dac [2,3] TX slots must use only 2 and 3.
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* \param value [0,4095]
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* \returns true iff successful
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virtual bool write_aux_dac (int which_side, int which_dac, int value) = 0;
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* \brief Read auxiliary analog to digital converter.
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* \param which_side [0,1] which d'board
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* \param which_adc [0,1]
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* \param value return 12-bit value [0,4095]
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* \returns true iff successful
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virtual bool read_aux_adc (int which_side, int which_adc, int *value) = 0;
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* \brief Read auxiliary analog to digital converter.
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* \param which_side [0,1] which d'board
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* \param which_adc [0,1]
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* \returns value in the range [0,4095] if successful, else READ_FAILED.
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virtual int read_aux_adc (int which_side, int which_adc) = 0;
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* \brief returns current fusb block size
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virtual int block_size() const = 0;
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* \brief returns A/D or D/A converter rate in Hz
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virtual long converter_rate() const = 0;
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// END virtual daughterboard control functions
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// ----------------------------------------------------------------
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// Low level implementation routines.
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// You probably shouldn't be using these...
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bool _set_led (int which_led, bool on);
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* \brief Write FPGA register.
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* \param regno 7-bit register number
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* \param value 32-bit value
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* \returns true iff successful
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bool _write_fpga_reg (int regno, int value); //< 7-bit regno, 32-bit value
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* \brief Read FPGA register.
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* \param regno 7-bit register number
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* \param value 32-bit value
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* \returns true iff successful
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bool _read_fpga_reg (int regno, int *value); //< 7-bit regno, 32-bit value
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* \brief Read FPGA register.
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* \param regno 7-bit register number
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* \returns register value if successful, else READ_FAILED
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int _read_fpga_reg (int regno);
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* \brief Write FPGA register with mask.
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* \param regno 7-bit register number
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* \param value 16-bit value
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* \param mask 16-bit value
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* \returns true if successful
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* Only use this for registers who actually implement a mask in the verilog firmware, like FR_RX_MASTER_SLAVE
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bool _write_fpga_reg_masked (int regno, int value, int mask);
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* \brief Write AD9862 register.
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* \param which_codec 0 or 1
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* \param regno 6-bit register number
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* \param value 8-bit value
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* \returns true iff successful
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bool _write_9862 (int which_codec, int regno, unsigned char value);
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* \brief Read AD9862 register.
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* \param which_codec 0 or 1
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* \param regno 6-bit register number
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* \param value 8-bit value
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* \returns true iff successful
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bool _read_9862 (int which_codec, int regno, unsigned char *value) const;
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* \brief Read AD9862 register.
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* \param which_codec 0 or 1
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* \param regno 6-bit register number
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* \returns register value if successful, else READ_FAILED
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int _read_9862 (int which_codec, int regno) const;
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* \brief Write data to SPI bus peripheral.
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* \param optional_header 0,1 or 2 bytes to write before buf.
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* \param enables bitmask of peripherals to write. See usrp_spi_defs.h
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* \param format transaction format. See usrp_spi_defs.h SPI_FMT_*
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* \param buf the data to write
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* \returns true iff successful
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* Writes are limited to a maximum of 64 bytes.
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* If \p format specifies that optional_header bytes are present, they are
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* written to the peripheral immediately prior to writing \p buf.
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bool _write_spi (int optional_header, int enables, int format, std::string buf);
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* \brief Read data from SPI bus peripheral.
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* \param optional_header 0,1 or 2 bytes to write before buf.
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* \param enables bitmask of peripheral to read. See usrp_spi_defs.h
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* \param format transaction format. See usrp_spi_defs.h SPI_FMT_*
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* \param len number of bytes to read. Must be in [0,64].
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* \returns the data read if sucessful, else a zero length string.
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* Reads are limited to a maximum of 64 bytes.
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* If \p format specifies that optional_header bytes are present, they
748
* are written to the peripheral first. Then \p len bytes are read from
749
* the peripheral and returned.
751
std::string _read_spi (int optional_header, int enables, int format, int len);
754
* \brief Start data transfers.
755
* Called in base class to derived class order.
760
* \brief Stop data transfers.
761
* Called in base class to derived class order.
767
* \brief class for accessing the receive side of the USRP
770
class usrp_basic_rx : public usrp_basic
773
fusb_devhandle *d_devhandle;
774
fusb_ephandle *d_ephandle;
775
int d_bytes_seen; // how many bytes we've seen
781
* \param which_board Which USRP board on usb (not particularly useful; use 0)
782
* \param fusb_block_size fast usb xfer block size. Must be a multiple of 512.
783
* Use zero for a reasonable default.
784
* \param fusb_nblocks number of fast usb URBs to allocate. Use zero for a reasonable default.
785
* \param fpga_filename name of the rbf file to load
786
* \param firmware_filename name of ihx file to load
788
usrp_basic_rx (int which_board,
789
int fusb_block_size=0,
791
const std::string fpga_filename = "",
792
const std::string firmware_filename = ""
793
); // throws if trouble
795
bool set_rx_enable (bool on);
796
bool rx_enable () const { return d_rx_enable; }
798
bool disable_rx (); // conditional disable, return prev state
799
void restore_rx (bool on); // conditional set
801
void probe_rx_slots (bool verbose);
807
* \brief invokes constructor, returns instance or 0 if trouble
809
* \param which_board Which USRP board on usb (not particularly useful; use 0)
810
* \param fusb_block_size fast usb xfer block size. Must be a multiple of 512.
811
* Use zero for a reasonable default.
812
* \param fusb_nblocks number of fast usb URBs to allocate. Use zero for a reasonable default.
813
* \param fpga_filename name of file that contains image to load into FPGA
814
* \param firmware_filename name of file that contains image to load into FX2
816
static usrp_basic_rx *make (int which_board,
817
int fusb_block_size=0,
819
const std::string fpga_filename = "",
820
const std::string firmware_filename = ""
824
* \brief tell the fpga the rate rx samples are coming from the A/D's
826
* div = fpga_master_clock_freq () / sample_rate
828
* sample_rate is determined by a myriad of registers
829
* in the 9862. That's why you have to tell us, so
830
* we can tell the fpga.
832
bool set_fpga_rx_sample_rate_divisor (unsigned int div);
835
* \brief read data from the D/A's via the FPGA.
836
* \p len must be a multiple of 512 bytes.
838
* \returns the number of bytes read, or -1 on error.
840
* If overrun is non-NULL it will be set true iff an RX overrun is detected.
842
int read (void *buf, int len, bool *overrun);
845
//! sampling rate of A/D converter
846
virtual long converter_rate() const { return fpga_master_clock_freq(); } // 64M
847
long adc_rate() const { return converter_rate(); }
848
int daughterboard_id (int which_side) const { return d_dbid[which_side & 0x1]; }
850
bool set_pga (int which_amp, double gain_in_db);
851
double pga (int which_amp) const;
852
double pga_min () const;
853
double pga_max () const;
854
double pga_db_per_step () const;
856
bool _write_oe (int which_side, int value, int mask);
857
bool write_io (int which_side, int value, int mask);
858
bool read_io (int which_side, int *value);
859
int read_io (int which_side);
860
bool write_refclk(int which_side, int value);
861
bool write_atr_mask(int which_side, int value);
862
bool write_atr_txval(int which_side, int value);
863
bool write_atr_rxval(int which_side, int value);
865
bool write_aux_dac (int which_side, int which_dac, int value);
866
bool read_aux_adc (int which_side, int which_adc, int *value);
867
int read_aux_adc (int which_side, int which_adc);
869
int block_size() const;
871
// called in base class to derived class order
877
* \brief class for accessing the transmit side of the USRP
880
class usrp_basic_tx : public usrp_basic
883
fusb_devhandle *d_devhandle;
884
fusb_ephandle *d_ephandle;
885
int d_bytes_seen; // how many bytes we've seen
891
* \param which_board Which USRP board on usb (not particularly useful; use 0)
892
* \param fusb_block_size fast usb xfer block size. Must be a multiple of 512.
893
* Use zero for a reasonable default.
894
* \param fusb_nblocks number of fast usb URBs to allocate. Use zero for a reasonable default.
895
* \param fpga_filename name of file that contains image to load into FPGA
896
* \param firmware_filename name of file that contains image to load into FX2
898
usrp_basic_tx (int which_board,
899
int fusb_block_size=0,
901
const std::string fpga_filename = "",
902
const std::string firmware_filename = ""
903
); // throws if trouble
905
bool set_tx_enable (bool on);
906
bool tx_enable () const { return d_tx_enable; }
908
bool disable_tx (); // conditional disable, return prev state
909
void restore_tx (bool on); // conditional set
911
void probe_tx_slots (bool verbose);
918
* \brief invokes constructor, returns instance or 0 if trouble
920
* \param which_board Which USRP board on usb (not particularly useful; use 0)
921
* \param fusb_block_size fast usb xfer block size. Must be a multiple of 512.
922
* Use zero for a reasonable default.
923
* \param fusb_nblocks number of fast usb URBs to allocate. Use zero for a reasonable default.
924
* \param fpga_filename name of file that contains image to load into FPGA
925
* \param firmware_filename name of file that contains image to load into FX2
927
static usrp_basic_tx *make (int which_board, int fusb_block_size=0, int fusb_nblocks=0,
928
const std::string fpga_filename = "",
929
const std::string firmware_filename = ""
933
* \brief tell the fpga the rate tx samples are going to the D/A's
935
* div = fpga_master_clock_freq () * 2
937
* sample_rate is determined by a myriad of registers
938
* in the 9862. That's why you have to tell us, so
939
* we can tell the fpga.
941
bool set_fpga_tx_sample_rate_divisor (unsigned int div);
944
* \brief Write data to the A/D's via the FPGA.
946
* \p len must be a multiple of 512 bytes.
947
* \returns number of bytes written or -1 on error.
949
* if \p underrun is non-NULL, it will be set to true iff
950
* a transmit underrun condition is detected.
952
int write (const void *buf, int len, bool *underrun);
955
* Block until all outstanding writes have completed.
956
* This is typically used to assist with benchmarking
958
void wait_for_completion ();
960
//! sampling rate of D/A converter
961
virtual long converter_rate() const { return fpga_master_clock_freq () * 2; } // 128M
962
long dac_rate() const { return converter_rate(); }
963
int daughterboard_id (int which_side) const { return d_dbid[which_side & 0x1]; }
965
bool set_pga (int which_amp, double gain_in_db);
966
double pga (int which_amp) const;
967
double pga_min () const;
968
double pga_max () const;
969
double pga_db_per_step () const;
971
bool _write_oe (int which_side, int value, int mask);
972
bool write_io (int which_side, int value, int mask);
973
bool read_io (int which_side, int *value);
974
int read_io (int which_side);
975
bool write_refclk(int which_side, int value);
976
bool write_atr_mask(int which_side, int value);
977
bool write_atr_txval(int which_side, int value);
978
bool write_atr_rxval(int which_side, int value);
980
bool write_aux_dac (int which_side, int which_dac, int value);
981
bool read_aux_adc (int which_side, int which_adc, int *value);
982
int read_aux_adc (int which_side, int which_adc);
984
int block_size() const;
986
// called in base class to derived class order
added
removed
usrp/host/lib/legacy/usrp_basic.h
