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* Copyright 2007,2008 Free Software Foundation, Inc.
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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#include "memory_map.h"
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#include "buffer_pool.h"
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#include "usrp2_eth_packet.h"
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#include "app_common_v2.h"
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#include "memcpy_wa.h"
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#define FW_SETS_SEQNO 1 // define to 0 or 1 (FIXME must be 1 for now)
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static int fw_seqno; // used when f/w is filling in sequence numbers
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* Full duplex Tx and Rx between ethernet and DSP pipelines
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* Buffer 1 is used by the cpu to send frames to the host.
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* Buffers 2 and 3 are used to double-buffer the DSP Rx to eth flow
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* Buffers 4 and 5 are used to double-buffer the eth to DSP Tx eth flow
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//#define CPU_RX_BUF 0 // eth -> cpu
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#define DSP_RX_BUF_0 2 // dsp rx -> eth (double buffer)
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#define DSP_RX_BUF_1 3 // dsp rx -> eth
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#define DSP_TX_BUF_0 4 // eth -> dsp tx (double buffer)
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#define DSP_TX_BUF_1 5 // eth -> dsp tx
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* ================================================================
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* configure DSP TX double buffering state machine (eth -> dsp)
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* ================================================================
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// 4 lines of ethernet hdr + 1 line transport hdr + 2 lines (word0 + timestamp)
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// DSP Tx reads word0 (flags) + timestamp followed by samples
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#define DSP_TX_FIRST_LINE ((sizeof(u2_eth_hdr_t) + sizeof(u2_transport_hdr_t))/4)
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// Receive from ethernet
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buf_cmd_args_t dsp_tx_recv_args = {
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buf_cmd_args_t dsp_tx_send_args = {
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DSP_TX_FIRST_LINE, // starts just past transport header
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0 // filled in from last_line register
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dbsm_t dsp_tx_sm; // the state machine
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* ================================================================
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* configure DSP RX double buffering state machine (dsp -> eth)
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* ================================================================
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// 4 lines of ethernet hdr + 1 line transport hdr + 1 line (word0)
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// DSP Rx writes timestamp followed by nlines_per_frame of samples
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#define DSP_RX_FIRST_LINE ((sizeof(u2_eth_hdr_t) + sizeof(u2_transport_hdr_t))/4 + 1)
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buf_cmd_args_t dsp_rx_recv_args = {
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buf_cmd_args_t dsp_rx_send_args = {
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0, // starts with ethernet header in line 0
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0, // filled in from list_line register
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dbsm_t dsp_rx_sm; // the state machine
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// The mac address of the host we're sending to.
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u2_mac_addr_t host_mac_addr;
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// variables for streaming mode
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static bool streaming_p = false;
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static unsigned int streaming_items_per_frame = 0;
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static int streaming_frame_count = 0;
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#define FRAMES_PER_CMD 1000
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bool is_streaming(void){ return streaming_p; }
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// ----------------------------------------------------------------
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restart_streaming(void)
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dsp_rx_regs->clear_state = 1; // reset
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streaming_frame_count = FRAMES_PER_CMD;
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dsp_rx_regs->rx_command =
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MK_RX_CMD(FRAMES_PER_CMD * streaming_items_per_frame,
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streaming_items_per_frame,
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1, 1); // set "chain" bit
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// kick off the state machine
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dbsm_start(&dsp_rx_sm);
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dsp_rx_regs->rx_time = 0; // enqueue first of two commands
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// make sure this one and the rest have the "now" and "chain" bits set.
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dsp_rx_regs->rx_command =
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MK_RX_CMD(FRAMES_PER_CMD * streaming_items_per_frame,
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streaming_items_per_frame,
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dsp_rx_regs->rx_time = 0; // enqueue second command
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start_rx_streaming_cmd(const u2_mac_addr_t *host, op_start_rx_streaming_t *p)
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host_mac_addr = *host; // remember who we're sending to
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* Construct ethernet header and word0 and preload into two buffers
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memset(&pkt, 0, sizeof(pkt));
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pkt.ehdr.dst = *host;
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pkt.ehdr.ethertype = U2_ETHERTYPE;
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u2p_set_word0(&pkt.fixed, 0, 0);
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// DSP RX will fill in timestamp
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memcpy_wa(buffer_ram(DSP_RX_BUF_0), &pkt, sizeof(pkt));
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memcpy_wa(buffer_ram(DSP_RX_BUF_1), &pkt, sizeof(pkt));
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streaming_items_per_frame = p->items_per_frame;
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dsp_rx_regs->clear_state = 1; // flush cmd queue
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bp_clear_buf(DSP_RX_BUF_0);
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bp_clear_buf(DSP_RX_BUF_1);
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dsp_tx_regs->clear_state = 1;
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bp_clear_buf(DSP_TX_BUF_0);
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bp_clear_buf(DSP_TX_BUF_1);
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// setup some defaults
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dsp_tx_regs->freq = 0;
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dsp_tx_regs->scale_iq = (tx_scale << 16) | tx_scale;
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dsp_tx_regs->interp_rate = interp;
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* Debugging ONLY. This will be handled by the tx_protocol_engine.
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* This is called when the DSP Rx chain has filled in a packet.
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* We set and increment the seqno, then return false, indicating
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* that we didn't handle the packet. A bit of a kludge
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* but it should work.
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fw_sets_seqno_inspector(dbsm_t *sm, int buf_this) // returns false
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uint32_t *p = buffer_ram(buf_this);
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uint32_t seqno = fw_seqno++;
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// KLUDGE all kinds of nasty magic numbers and embedded knowledge
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t = (t & 0xffff00ff) | ((seqno & 0xff) << 8);
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// queue up another rx command when required
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if (streaming_p && --streaming_frame_count == 0){
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streaming_frame_count = FRAMES_PER_CMD;
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dsp_rx_regs->rx_time = 0;
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return false; // we didn't handle the packet
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buffer_irq_handler(unsigned irq)
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uint32_t status = buffer_pool_status->status;
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dbsm_process_status(&dsp_tx_sm, status);
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dbsm_process_status(&dsp_rx_sm, status);
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print_mac_addr(ethernet_mac_addr()->addr);
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ethernet_register_link_changed_callback(link_changed_callback);
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// make bit 15 of Tx gpio's be a s/w output
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hal_gpio_set_sel(GPIO_TX_BANK, 15, 's');
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hal_gpio_set_ddr(GPIO_TX_BANK, 0x8000, 0x8000);
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output_regs->debug_mux_ctrl = 1;
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hal_gpio_set_sels(GPIO_TX_BANK, "1111111111111111");
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hal_gpio_set_sels(GPIO_RX_BANK, "1111111111111111");
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hal_gpio_set_ddr(GPIO_TX_BANK, 0xffff, 0xffff);
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hal_gpio_set_ddr(GPIO_RX_BANK, 0xffff, 0xffff);
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// initialize double buffering state machine for ethernet -> DSP Tx
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dbsm_init(&dsp_tx_sm, DSP_TX_BUF_0,
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&dsp_tx_recv_args, &dsp_tx_send_args,
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// initialize double buffering state machine for DSP RX -> Ethernet
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dbsm_init(&dsp_rx_sm, DSP_RX_BUF_0,
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&dsp_rx_recv_args, &dsp_rx_send_args,
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fw_sets_seqno_inspector);
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dbsm_init(&dsp_rx_sm, DSP_RX_BUF_0,
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&dsp_rx_recv_args, &dsp_rx_send_args,
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// tell app_common that this dbsm could be sending to the ethernet
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ac_could_be_sending_to_eth = &dsp_rx_sm;
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// program tx registers
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// kick off the state machine
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dbsm_start(&dsp_tx_sm);
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// hal_gpio_write(GPIO_TX_BANK, which, 0x8000);
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buffer_irq_handler(0);
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int pending = pic_regs->pending; // poll for under or overrun
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if (pending & PIC_UNDERRUN_INT){
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dbsm_handle_tx_underrun(&dsp_tx_sm);
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pic_regs->pending = PIC_UNDERRUN_INT; // clear interrupt
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if (pending & PIC_OVERRUN_INT){
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dbsm_handle_rx_overrun(&dsp_rx_sm);
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pic_regs->pending = PIC_OVERRUN_INT; // clear pending interrupt
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// FIXME Figure out how to handle this robustly.
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// Any buffers that are emptying should be allowed to drain...
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// restart_streaming();
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// FIXME report error
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// FIXME report error
added
removed
usrp2/firmware/apps/txrx.c
