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  • Committer: Bazaar Package Importer
  • Author(s): Uwe Hermann
  • Date: 2009-11-25 12:20:04 UTC
  • mfrom: (1.2.5 upstream)
  • Revision ID: james.westby@ubuntu.com-20091125122004-4cnrzqw7v9qu064n
Tags: 0.3.1-1
http://bugs.debian.org/554598
http://bugs.debian.org/537740
http://bugs.debian.org/555553
* New upstream release (Closes: #554598, #537740).
* Add sh4 (instead of sh) to the list of architectures (Closes: #555553).
* Standards-Version: 3.8.3 (no changes required).
* debian/watch: Add file.
* debian/docs: Updates, some files were removed, some added.

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src/target/arm926ejs.c
2
2
 *   Copyright (C) 2007 by Dominic Rath                                    *
3
3
 *   Dominic.Rath@gmx.de                                                   *
4
4
 *                                                                         *
 
5
 *   Copyright (C) 2007,2008,2009 by Øyvind Harboe                         *
 
6
 *   oyvind.harboe@zylin.com                                               *
 
7
 *                                                                         *
5
8
 *   This program is free software; you can redistribute it and/or modify  *
6
9
 *   it under the terms of the GNU General Public License as published by  *
7
10
 *   the Free Software Foundation; either version 2 of the License, or     *
30
33
#define _DEBUG_INSTRUCTION_EXECUTION_
31
34
#endif
32
35
 
33
 
/* cli handling */
34
 
int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
35
 
int arm926ejs_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
36
 
int arm926ejs_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
37
 
int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
38
 
int arm926ejs_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
39
 
int arm926ejs_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
40
 
 
41
 
int arm926ejs_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
42
 
int arm926ejs_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
43
 
 
44
 
/* forward declarations */
45
 
int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp);
46
 
int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
47
 
int arm926ejs_quit(void);
48
 
int arm926ejs_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
49
 
 
50
 
static int arm926ejs_virt2phys(struct target_s *target, uint32_t virtual, uint32_t *physical);
51
 
static int arm926ejs_mmu(struct target_s *target, int *enabled);
52
 
 
53
 
target_type_t arm926ejs_target =
54
 
{
55
 
        .name = "arm926ejs",
56
 
 
57
 
        .poll = arm7_9_poll,
58
 
        .arch_state = arm926ejs_arch_state,
59
 
 
60
 
        .target_request_data = arm7_9_target_request_data,
61
 
 
62
 
        .halt = arm7_9_halt,
63
 
        .resume = arm7_9_resume,
64
 
        .step = arm7_9_step,
65
 
 
66
 
        .assert_reset = arm7_9_assert_reset,
67
 
        .deassert_reset = arm7_9_deassert_reset,
68
 
        .soft_reset_halt = arm926ejs_soft_reset_halt,
69
 
 
70
 
        .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
71
 
 
72
 
        .read_memory = arm7_9_read_memory,
73
 
        .write_memory = arm926ejs_write_memory,
74
 
        .bulk_write_memory = arm7_9_bulk_write_memory,
75
 
        .checksum_memory = arm7_9_checksum_memory,
76
 
        .blank_check_memory = arm7_9_blank_check_memory,
77
 
 
78
 
        .run_algorithm = armv4_5_run_algorithm,
79
 
 
80
 
        .add_breakpoint = arm7_9_add_breakpoint,
81
 
        .remove_breakpoint = arm7_9_remove_breakpoint,
82
 
        .add_watchpoint = arm7_9_add_watchpoint,
83
 
        .remove_watchpoint = arm7_9_remove_watchpoint,
84
 
 
85
 
        .register_commands = arm926ejs_register_commands,
86
 
        .target_create = arm926ejs_target_create,
87
 
        .init_target = arm926ejs_init_target,
88
 
        .examine = arm9tdmi_examine,
89
 
        .quit = arm926ejs_quit,
90
 
        .virt2phys = arm926ejs_virt2phys,
91
 
        .mmu = arm926ejs_mmu
92
 
};
93
 
 
94
 
int arm926ejs_catch_broken_irscan(uint8_t *captured, void *priv, scan_field_t *field)
 
36
static int arm926ejs_catch_broken_irscan(uint8_t *captured, void *priv,
 
37
                scan_field_t *field)
95
38
{
96
39
        /* FIX!!!! this code should be reenabled. For now it does not check
97
40
         * the queue...*/
115
58
 
116
59
#define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0))
117
60
 
118
 
int arm926ejs_cp15_read(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
 
61
static int arm926ejs_cp15_read(target_t *target, uint32_t op1, uint32_t op2,
 
62
                uint32_t CRn, uint32_t CRm, uint32_t *value)
119
63
{
120
64
        int retval = ERROR_OK;
121
65
        armv4_5_common_t *armv4_5 = target->arch_info;
174
118
                {
175
119
                        return retval;
176
120
                }
177
 
                
 
121
 
178
122
                if (buf_get_u32(&access, 0, 1) == 1)
179
123
                {
180
124
                        break;
181
125
                }
182
 
                
 
126
 
183
127
                /* 10ms timeout */
184
128
                if ((timeval_ms()-then)>10)
185
129
                {
197
141
        return ERROR_OK;
198
142
}
199
143
 
200
 
int arm926ejs_cp15_write(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
 
144
static int arm926ejs_mrc(target_t *target, int cpnum, uint32_t op1,
 
145
                uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
 
146
{
 
147
        if (cpnum != 15) {
 
148
                LOG_ERROR("Only cp15 is supported");
 
149
                return ERROR_FAIL;
 
150
        }
 
151
        return arm926ejs_cp15_read(target, op1, op2, CRn, CRm, value);
 
152
}
 
153
 
 
154
static int arm926ejs_cp15_write(target_t *target, uint32_t op1, uint32_t op2,
 
155
                uint32_t CRn, uint32_t CRm, uint32_t value)
201
156
{
202
157
        int retval = ERROR_OK;
203
158
        armv4_5_common_t *armv4_5 = target->arch_info;
277
232
        return ERROR_OK;
278
233
}
279
234
 
280
 
int arm926ejs_examine_debug_reason(target_t *target)
 
235
static int arm926ejs_mcr(target_t *target, int cpnum, uint32_t op1,
 
236
                uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
 
237
{
 
238
        if (cpnum != 15) {
 
239
                LOG_ERROR("Only cp15 is supported");
 
240
                return ERROR_FAIL;
 
241
        }
 
242
        return arm926ejs_cp15_write(target, op1, op2, CRn, CRm, value);
 
243
}
 
244
 
 
245
static int arm926ejs_examine_debug_reason(target_t *target)
281
246
{
282
247
        armv4_5_common_t *armv4_5 = target->arch_info;
283
248
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
294
259
 
295
260
        switch (debug_reason)
296
261
        {
297
 
                /* case 0:  no debug entry */
 
262
                case 0:
 
263
                        LOG_DEBUG("no *NEW* debug entry (?missed one?)");
 
264
                        /* ... since last restart or debug reset ... */
 
265
                        target->debug_reason = DBG_REASON_DBGRQ;
 
266
                        break;
298
267
                case 1:
299
268
                        LOG_DEBUG("breakpoint from EICE unit 0");
300
269
                        target->debug_reason = DBG_REASON_BREAKPOINT;
377
346
        return ERROR_OK;
378
347
}
379
348
 
380
 
uint32_t arm926ejs_get_ttb(target_t *target)
 
349
static uint32_t arm926ejs_get_ttb(target_t *target)
381
350
{
382
351
        armv4_5_common_t *armv4_5 = target->arch_info;
383
352
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
392
361
        return ttb;
393
362
}
394
363
 
395
 
void arm926ejs_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
 
364
static void arm926ejs_disable_mmu_caches(target_t *target, int mmu,
 
365
                int d_u_cache, int i_cache)
396
366
{
397
367
        armv4_5_common_t *armv4_5 = target->arch_info;
398
368
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
443
413
        arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
444
414
}
445
415
 
446
 
void arm926ejs_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
 
416
static void arm926ejs_enable_mmu_caches(target_t *target, int mmu,
 
417
                int d_u_cache, int i_cache)
447
418
{
448
419
        armv4_5_common_t *armv4_5 = target->arch_info;
449
420
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
467
438
        arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
468
439
}
469
440
 
470
 
void arm926ejs_post_debug_entry(target_t *target)
 
441
static void arm926ejs_post_debug_entry(target_t *target)
471
442
{
472
443
        armv4_5_common_t *armv4_5 = target->arch_info;
473
444
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
509
480
        arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
510
481
}
511
482
 
512
 
void arm926ejs_pre_restore_context(target_t *target)
 
483
static void arm926ejs_pre_restore_context(target_t *target)
513
484
{
514
485
        armv4_5_common_t *armv4_5 = target->arch_info;
515
486
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
530
501
        arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
531
502
}
532
503
 
533
 
int arm926ejs_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm926ejs_common_t **arm926ejs_p)
 
504
static int arm926ejs_get_arch_pointers(target_t *target,
 
505
                armv4_5_common_t **armv4_5_p,
 
506
                arm7_9_common_t **arm7_9_p,
 
507
                arm9tdmi_common_t **arm9tdmi_p,
 
508
                arm926ejs_common_t **arm926ejs_p)
534
509
{
535
510
        armv4_5_common_t *armv4_5 = target->arch_info;
536
511
        arm7_9_common_t *arm7_9;
669
644
        return target_call_event_callbacks(target, TARGET_EVENT_HALTED);
670
645
}
671
646
 
672
 
int arm926ejs_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 
647
int arm926ejs_write_memory(struct target_s *target, uint32_t address,
 
648
                uint32_t size, uint32_t count, uint8_t *buffer)
673
649
{
674
650
        int retval;
675
651
        armv4_5_common_t *armv4_5 = target->arch_info;
677
653
        arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
678
654
        arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
679
655
 
680
 
        if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
681
 
                return retval;
 
656
        /* FIX!!!! this should be cleaned up and made much more general. The
 
657
         * plan is to write up and test on arm926ejs specifically and
 
658
         * then generalize and clean up afterwards. */
 
659
        if (arm926ejs->armv4_5_mmu.mmu_enabled && (count == 1) && ((size==2) || (size==4)))
 
660
        {
 
661
                /* special case the handling of single word writes to bypass MMU
 
662
                 * to allow implementation of breakpoints in memory marked read only
 
663
                 * by MMU */
 
664
                if (arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
 
665
                {
 
666
                        /* flush and invalidate data cache
 
667
                         *
 
668
                         * MCR p15,0,p,c7,c10,1 - clean cache line using virtual address
 
669
                         *
 
670
                         */
 
671
                        retval = arm926ejs->write_cp15(target, 0, 1, 7, 10, address&~0x3);
 
672
                        if (retval != ERROR_OK)
 
673
                                return retval;
 
674
                }
 
675
 
 
676
                uint32_t pa;
 
677
                retval = target->type->virt2phys(target, address, &pa);
 
678
                if (retval != ERROR_OK)
 
679
                        return retval;
 
680
 
 
681
                /* write directly to physical memory bypassing any read only MMU bits, etc. */
 
682
                retval = armv4_5_mmu_write_physical(target, &arm926ejs->armv4_5_mmu, pa, size, count, buffer);
 
683
                if (retval != ERROR_OK)
 
684
                        return retval;
 
685
        } else
 
686
        {
 
687
                if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
 
688
                        return retval;
 
689
        }
682
690
 
683
691
        /* If ICache is enabled, we have to invalidate affected ICache lines
684
692
         * the DCache is forced to write-through, so we don't have to clean it here
700
708
        return retval;
701
709
}
702
710
 
703
 
int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 
711
static int arm926ejs_write_phys_memory(struct target_s *target,
 
712
                uint32_t address, uint32_t size,
 
713
                uint32_t count, uint8_t *buffer)
 
714
{
 
715
        armv4_5_common_t *armv4_5 = target->arch_info;
 
716
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 
717
        arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 
718
        arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 
719
 
 
720
        return armv4_5_mmu_write_physical(target, &arm926ejs->armv4_5_mmu, address, size, count, buffer);
 
721
}
 
722
 
 
723
static int arm926ejs_read_phys_memory(struct target_s *target,
 
724
                uint32_t address, uint32_t size,
 
725
                uint32_t count, uint8_t *buffer)
 
726
{
 
727
        armv4_5_common_t *armv4_5 = target->arch_info;
 
728
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 
729
        arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 
730
        arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 
731
 
 
732
        return armv4_5_mmu_read_physical(target, &arm926ejs->armv4_5_mmu, address, size, count, buffer);
 
733
}
 
734
 
 
735
static int arm926ejs_init_target(struct command_context_s *cmd_ctx,
 
736
                struct target_s *target)
704
737
{
705
738
        arm9tdmi_init_target(cmd_ctx, target);
706
739
 
707
740
        return ERROR_OK;
708
741
}
709
742
 
710
 
int arm926ejs_quit(void)
 
743
static int arm926ejs_quit(void)
711
744
{
712
745
        return ERROR_OK;
713
746
}
714
747
 
715
 
int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, jtag_tap_t *tap)
 
748
int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs,
 
749
                jtag_tap_t *tap)
716
750
{
717
751
        arm9tdmi_common_t *arm9tdmi = &arm926ejs->arm9tdmi_common;
718
752
        arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
749
783
        return ERROR_OK;
750
784
}
751
785
 
752
 
int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp)
 
786
static int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp)
753
787
{
754
788
        arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t));
755
789
 
758
792
        return ERROR_OK;
759
793
}
760
794
 
761
 
int arm926ejs_register_commands(struct command_context_s *cmd_ctx)
762
 
{
763
 
        int retval;
764
 
        command_t *arm926ejs_cmd;
765
 
 
766
 
 
767
 
        retval = arm9tdmi_register_commands(cmd_ctx);
768
 
 
769
 
        arm926ejs_cmd = register_command(cmd_ctx, NULL, "arm926ejs", NULL, COMMAND_ANY, "arm926ejs specific commands");
770
 
 
771
 
        register_command(cmd_ctx, arm926ejs_cmd, "cp15", arm926ejs_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode_1> <opcode_2> <CRn> <CRm> [value]");
772
 
 
773
 
        register_command(cmd_ctx, arm926ejs_cmd, "cache_info", arm926ejs_handle_cache_info_command, COMMAND_EXEC, "display information about target caches");
774
 
        register_command(cmd_ctx, arm926ejs_cmd, "virt2phys", arm926ejs_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");
775
 
 
776
 
        register_command(cmd_ctx, arm926ejs_cmd, "mdw_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
777
 
        register_command(cmd_ctx, arm926ejs_cmd, "mdh_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
778
 
        register_command(cmd_ctx, arm926ejs_cmd, "mdb_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
779
 
 
780
 
        register_command(cmd_ctx, arm926ejs_cmd, "mww_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
781
 
        register_command(cmd_ctx, arm926ejs_cmd, "mwh_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
782
 
        register_command(cmd_ctx, arm926ejs_cmd, "mwb_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
783
 
 
784
 
        return retval;
785
 
}
786
 
 
787
 
int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 
795
static int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx,
 
796
                char *cmd, char **args, int argc)
788
797
{
789
798
        int retval;
790
799
        target_t *target = get_current_target(cmd_ctx);
849
858
        return ERROR_OK;
850
859
}
851
860
 
852
 
int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 
861
static int
 
862
arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx,
 
863
                char *cmd, char **args, int argc)
853
864
{
854
865
        target_t *target = get_current_target(cmd_ctx);
855
866
        armv4_5_common_t *armv4_5;
866
877
        return armv4_5_handle_cache_info_command(cmd_ctx, &arm926ejs->armv4_5_mmu.armv4_5_cache);
867
878
}
868
879
 
869
 
int arm926ejs_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
870
 
{
871
 
        target_t *target = get_current_target(cmd_ctx);
872
 
        armv4_5_common_t *armv4_5;
873
 
        arm7_9_common_t *arm7_9;
874
 
        arm9tdmi_common_t *arm9tdmi;
875
 
        arm926ejs_common_t *arm926ejs;
876
 
        arm_jtag_t *jtag_info;
877
 
 
878
 
        if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
879
 
        {
880
 
                command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
881
 
                return ERROR_OK;
882
 
        }
883
 
 
884
 
        jtag_info = &arm7_9->jtag_info;
885
 
 
886
 
        if (target->state != TARGET_HALTED)
887
 
        {
888
 
                command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
889
 
                return ERROR_OK;
890
 
        }
891
 
 
892
 
        return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
893
 
}
894
 
 
895
 
int arm926ejs_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
896
 
{
897
 
        target_t *target = get_current_target(cmd_ctx);
898
 
        armv4_5_common_t *armv4_5;
899
 
        arm7_9_common_t *arm7_9;
900
 
        arm9tdmi_common_t *arm9tdmi;
901
 
        arm926ejs_common_t *arm926ejs;
902
 
        arm_jtag_t *jtag_info;
903
 
 
904
 
        if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
905
 
        {
906
 
                command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
907
 
                return ERROR_OK;
908
 
        }
909
 
 
910
 
        jtag_info = &arm7_9->jtag_info;
911
 
 
912
 
        if (target->state != TARGET_HALTED)
913
 
        {
914
 
                command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
915
 
                return ERROR_OK;
916
 
        }
917
 
 
918
 
        return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
919
 
}
920
 
 
921
 
int arm926ejs_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
922
 
{
923
 
        target_t *target = get_current_target(cmd_ctx);
924
 
        armv4_5_common_t *armv4_5;
925
 
        arm7_9_common_t *arm7_9;
926
 
        arm9tdmi_common_t *arm9tdmi;
927
 
        arm926ejs_common_t *arm926ejs;
928
 
        arm_jtag_t *jtag_info;
929
 
 
930
 
        if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
931
 
        {
932
 
                command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
933
 
                return ERROR_OK;
934
 
        }
935
 
 
936
 
        jtag_info = &arm7_9->jtag_info;
937
 
 
938
 
        if (target->state != TARGET_HALTED)
939
 
        {
940
 
                command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
941
 
                return ERROR_OK;
942
 
        }
943
 
 
944
 
        return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
945
 
}
946
 
 
947
880
static int arm926ejs_virt2phys(struct target_s *target, uint32_t virtual, uint32_t *physical)
948
881
{
949
882
        int retval;
973
906
static int arm926ejs_mmu(struct target_s *target, int *enabled)
974
907
{
975
908
        armv4_5_common_t *armv4_5 = target->arch_info;
976
 
        arm926ejs_common_t *arm926ejs = armv4_5->arch_info;
 
909
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 
910
        arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 
911
        arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
977
912
 
978
913
        if (target->state != TARGET_HALTED)
979
914
        {
983
918
        *enabled = arm926ejs->armv4_5_mmu.mmu_enabled;
984
919
        return ERROR_OK;
985
920
}
 
921
 
 
922
int arm926ejs_register_commands(struct command_context_s *cmd_ctx)
 
923
{
 
924
        int retval;
 
925
        command_t *arm926ejs_cmd;
 
926
 
 
927
        retval = arm9tdmi_register_commands(cmd_ctx);
 
928
 
 
929
        arm926ejs_cmd = register_command(cmd_ctx, NULL, "arm926ejs",
 
930
                NULL, COMMAND_ANY,
 
931
                "arm926ejs specific commands");
 
932
 
 
933
        register_command(cmd_ctx, arm926ejs_cmd, "cp15",
 
934
                arm926ejs_handle_cp15_command, COMMAND_EXEC,
 
935
                "display/modify cp15 register "
 
936
                "<opcode_1> <opcode_2> <CRn> <CRm> [value]");
 
937
 
 
938
        register_command(cmd_ctx, arm926ejs_cmd, "cache_info",
 
939
                arm926ejs_handle_cache_info_command, COMMAND_EXEC,
 
940
                "display information about target caches");
 
941
 
 
942
        return retval;
 
943
}
 
944
 
 
945
target_type_t arm926ejs_target =
 
946
{
 
947
        .name = "arm926ejs",
 
948
 
 
949
        .poll = arm7_9_poll,
 
950
        .arch_state = arm926ejs_arch_state,
 
951
 
 
952
        .target_request_data = arm7_9_target_request_data,
 
953
 
 
954
        .halt = arm7_9_halt,
 
955
        .resume = arm7_9_resume,
 
956
        .step = arm7_9_step,
 
957
 
 
958
        .assert_reset = arm7_9_assert_reset,
 
959
        .deassert_reset = arm7_9_deassert_reset,
 
960
        .soft_reset_halt = arm926ejs_soft_reset_halt,
 
961
 
 
962
        .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
 
963
 
 
964
        .read_memory = arm7_9_read_memory,
 
965
        .write_memory = arm926ejs_write_memory,
 
966
        .bulk_write_memory = arm7_9_bulk_write_memory,
 
967
        .checksum_memory = arm7_9_checksum_memory,
 
968
        .blank_check_memory = arm7_9_blank_check_memory,
 
969
 
 
970
        .run_algorithm = armv4_5_run_algorithm,
 
971
 
 
972
        .add_breakpoint = arm7_9_add_breakpoint,
 
973
        .remove_breakpoint = arm7_9_remove_breakpoint,
 
974
        .add_watchpoint = arm7_9_add_watchpoint,
 
975
        .remove_watchpoint = arm7_9_remove_watchpoint,
 
976
 
 
977
        .register_commands = arm926ejs_register_commands,
 
978
        .target_create = arm926ejs_target_create,
 
979
        .init_target = arm926ejs_init_target,
 
980
        .examine = arm9tdmi_examine,
 
981
        .quit = arm926ejs_quit,
 
982
        .virt2phys = arm926ejs_virt2phys,
 
983
        .mmu = arm926ejs_mmu,
 
984
 
 
985
        .read_phys_memory = arm926ejs_read_phys_memory,
 
986
        .write_phys_memory = arm926ejs_write_phys_memory,
 
987
        .mrc = arm926ejs_mrc,
 
988
        .mcr = arm926ejs_mcr,
 
989
};
 
990