35
35
-expected-id $_JRC_TAPID
37
37
# GDB target: Cortex-A8, using DAP
39
# FIXME when we have A8 support, use it. A8 != M3 ...
40
target create omap3.cpu cortex_m3 -chain-position $_CHIPNAME.dap
42
# FIXME much of this should be in reset event handlers
43
proc omap3_dbginit { } {
47
jtag tapenable omap3530.dap
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# 0xd401.1000 - Cortex-A8
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# 0xd401.9000 - TPIU (traceport)
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# 0xd401.d000 - DAPCTL
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omap3.cpu mww 0x54011FB0 0xC5ACCE55
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omap3.cpu mdw 0x54011314
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omap3.cpu mdw 0x54011314
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# omap3.cpu mdw 0x54011080
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omap3.cpu mww 0x5401d030 0x00002000
38
set _TARGETNAME $_CHIPNAME.cpu
39
target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap
43
# the reset sequence is event-driven
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# and kind of finicky...
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# some TCK tycles are required to activate the DEBUG power domain
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jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
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# have the DAP "always" be active
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jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
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proc omap3_dbginit {target} {
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# General Cortex A8 debug initialisation
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# Enable DBGU signal for OMAP353x
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$target mww 0x5401d030 0x00002000
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# be absolutely certain the JTAG clock will work with the worst-case
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# 16.8MHz/2 = 8.4MHz core clock, even before a bootloader kicks in.
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# OK to speed up *after* PLL and clock tree setup.
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$_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 }
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# REVISIT This assumes that SRST is unavailable, so we must assert reset
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# ourselves using PRM_RSTCTRL. RST_GS (2) is a warm reset, like ICEpick
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# would issue. RST_DPLL3 (4) is a cold reset.
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set PRM_RSTCTRL 0x48307250
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$_TARGETNAME configure -event reset-assert-pre "$_TARGETNAME mww $PRM_RSTCTRL 2"
71
$_TARGETNAME configure -event reset-assert-post "omap3_dbginit $_TARGETNAME"