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  • Committer: Bazaar Package Importer
  • Author(s): Uwe Hermann
  • Date: 2009-11-25 12:20:04 UTC
  • mfrom: (1.2.5 upstream)
  • Revision ID: james.westby@ubuntu.com-20091125122004-4cnrzqw7v9qu064n
Tags: 0.3.1-1
http://bugs.debian.org/554598
http://bugs.debian.org/537740
http://bugs.debian.org/555553
* New upstream release (Closes: #554598, #537740).
* Add sh4 (instead of sh) to the list of architectures (Closes: #555553).
* Standards-Version: 3.8.3 (no changes required).
* debian/watch: Add file.
* debian/docs: Updates, some files were removed, some added.

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src/target/embeddedice.c
2
2
 *   Copyright (C) 2005 by Dominic Rath                                    *
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3
 *   Dominic.Rath@gmx.de                                                   *
4
4
 *                                                                         *
5
 
 *   Copyright (C) 2007,2008 �yvind Harboe                                 *
 
5
 *   Copyright (C) 2007,2008,2009 Øyvind Harboe                            *
6
6
 *   oyvind.harboe@zylin.com                                               *
7
7
 *                                                                         *
8
8
 *   Copyright (C) 2008 by Spencer Oliver                                  *
29
29
 
30
30
#include "embeddedice.h"
31
31
 
 
32
#define ARRAY_SIZE(x)   ((int)(sizeof(x)/sizeof((x)[0])))
32
33
 
33
34
#if 0
34
35
static bitfield_desc_t embeddedice_comms_ctrl_bitfield_desc[] =
40
41
};
41
42
#endif
42
43
 
43
 
static int embeddedice_reg_arch_info[] =
44
 
{
45
 
        0x0, 0x1, 0x4, 0x5,
46
 
        0x8, 0x9, 0xa, 0xb, 0xc, 0xd,
47
 
        0x10, 0x11, 0x12, 0x13, 0x14, 0x15,
48
 
        0x2
49
 
};
50
 
 
51
 
static char* embeddedice_reg_list[] =
52
 
{
53
 
        "debug_ctrl",
54
 
        "debug_status",
55
 
 
56
 
        "comms_ctrl",
57
 
        "comms_data",
58
 
 
59
 
        "watch 0 addr value",
60
 
        "watch 0 addr mask",
61
 
        "watch 0 data value",
62
 
        "watch 0 data mask",
63
 
        "watch 0 control value",
64
 
        "watch 0 control mask",
65
 
 
66
 
        "watch 1 addr value",
67
 
        "watch 1 addr mask",
68
 
        "watch 1 data value",
69
 
        "watch 1 data mask",
70
 
        "watch 1 control value",
71
 
        "watch 1 control mask",
72
 
 
73
 
        "vector catch"
74
 
};
 
44
/*
 
45
 * From:  ARM9E-S TRM, DDI 0165, table C-4 (and similar, for other cores)
 
46
 */
 
47
static const struct {
 
48
        char            *name;
 
49
        unsigned short  addr;
 
50
        unsigned short  width;
 
51
} eice_regs[] = {
 
52
        [EICE_DBG_CTRL] = {
 
53
                .name =         "debug_ctrl",
 
54
                .addr =         0,
 
55
                /* width is assigned based on EICE version */
 
56
        },
 
57
        [EICE_DBG_STAT] = {
 
58
                .name =         "debug_status",
 
59
                .addr =         1,
 
60
                /* width is assigned based on EICE version */
 
61
        },
 
62
        [EICE_COMMS_CTRL] = {
 
63
                .name =         "comms_ctrl",
 
64
                .addr =         4,
 
65
                .width =        6,
 
66
        },
 
67
        [EICE_COMMS_DATA] = {
 
68
                .name =         "comms_data",
 
69
                .addr =         5,
 
70
                .width =        32,
 
71
        },
 
72
        [EICE_W0_ADDR_VALUE] = {
 
73
                .name =         "watch_0_addr_value",
 
74
                .addr =         8,
 
75
                .width =        32,
 
76
        },
 
77
        [EICE_W0_ADDR_MASK] = {
 
78
                .name =         "watch_0_addr_mask",
 
79
                .addr =         9,
 
80
                .width =        32,
 
81
        },
 
82
        [EICE_W0_DATA_VALUE ] = {
 
83
                .name =         "watch_0_data_value",
 
84
                .addr =         10,
 
85
                .width =        32,
 
86
        },
 
87
        [EICE_W0_DATA_MASK] = {
 
88
                .name =         "watch_0_data_mask",
 
89
                .addr =         11,
 
90
                .width =        32,
 
91
        },
 
92
        [EICE_W0_CONTROL_VALUE] = {
 
93
                .name =         "watch_0_control_value",
 
94
                .addr =         12,
 
95
                .width =        9,
 
96
        },
 
97
        [EICE_W0_CONTROL_MASK] = {
 
98
                .name =         "watch_0_control_mask",
 
99
                .addr =         13,
 
100
                .width =        8,
 
101
        },
 
102
        [EICE_W1_ADDR_VALUE] = {
 
103
                .name =         "watch_1_addr_value",
 
104
                .addr =         16,
 
105
                .width =        32,
 
106
        },
 
107
        [EICE_W1_ADDR_MASK] = {
 
108
                .name =         "watch_1_addr_mask",
 
109
                .addr =         17,
 
110
                .width =        32,
 
111
        },
 
112
        [EICE_W1_DATA_VALUE] = {
 
113
                .name =         "watch_1_data_value",
 
114
                .addr =         18,
 
115
                .width =        32,
 
116
        },
 
117
        [EICE_W1_DATA_MASK] = {
 
118
                .name =         "watch_1_data_mask",
 
119
                .addr =         19,
 
120
                .width =        32,
 
121
        },
 
122
        [EICE_W1_CONTROL_VALUE] = {
 
123
                .name =         "watch_1_control_value",
 
124
                .addr =         20,
 
125
                .width =        9,
 
126
        },
 
127
        [EICE_W1_CONTROL_MASK] = {
 
128
                .name =         "watch_1_control_mask",
 
129
                .addr =         21,
 
130
                .width =        8,
 
131
        },
 
132
        /* vector_catch isn't always present */
 
133
        [EICE_VEC_CATCH] = {
 
134
                .name =         "vector_catch",
 
135
                .addr =         2,
 
136
                .width =        8,
 
137
        },
 
138
};
 
139
 
75
140
 
76
141
static int embeddedice_reg_arch_type = -1;
77
142
 
84
149
        reg_t *reg_list = NULL;
85
150
        embeddedice_reg_t *arch_info = NULL;
86
151
        arm_jtag_t *jtag_info = &arm7_9->jtag_info;
87
 
        int num_regs;
 
152
        int num_regs = ARRAY_SIZE(eice_regs);
88
153
        int i;
89
154
        int eice_version = 0;
90
155
 
91
156
        /* register a register arch-type for EmbeddedICE registers only once */
92
157
        if (embeddedice_reg_arch_type == -1)
93
 
                embeddedice_reg_arch_type = register_reg_arch_type(embeddedice_get_reg, embeddedice_set_reg_w_exec);
 
158
                embeddedice_reg_arch_type = register_reg_arch_type(
 
159
                                embeddedice_get_reg, embeddedice_set_reg_w_exec);
94
160
 
95
 
        if (arm7_9->has_vector_catch)
96
 
                num_regs = 17;
97
 
        else
98
 
                num_regs = 16;
 
161
        /* vector_catch isn't always present */
 
162
        if (!arm7_9->has_vector_catch)
 
163
                num_regs--;
99
164
 
100
165
        /* the actual registers are kept in two arrays */
101
166
        reg_list = calloc(num_regs, sizeof(reg_t));
110
175
        /* set up registers */
111
176
        for (i = 0; i < num_regs; i++)
112
177
        {
113
 
                reg_list[i].name = embeddedice_reg_list[i];
114
 
                reg_list[i].size = 32;
 
178
                reg_list[i].name = eice_regs[i].name;
 
179
                reg_list[i].size = eice_regs[i].width;
115
180
                reg_list[i].dirty = 0;
116
181
                reg_list[i].valid = 0;
117
182
                reg_list[i].bitfield_desc = NULL;
119
184
                reg_list[i].value = calloc(1, 4);
120
185
                reg_list[i].arch_info = &arch_info[i];
121
186
                reg_list[i].arch_type = embeddedice_reg_arch_type;
122
 
                arch_info[i].addr = embeddedice_reg_arch_info[i];
 
187
                arch_info[i].addr = eice_regs[i].addr;
123
188
                arch_info[i].jtag_info = jtag_info;
124
189
        }
125
190
 
132
197
                        free(reg_list[i].value);
133
198
                }
134
199
                free(reg_list);
 
200
                free(reg_cache);
135
201
                free(arch_info);
136
202
                return NULL;
137
203
        }
138
204
 
139
205
        eice_version = buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 28, 4);
 
206
        LOG_INFO("Embedded ICE version %d", eice_version);
140
207
 
141
208
        switch (eice_version)
142
209
        {
143
210
                case 1:
 
211
                        /* ARM7TDMI r3, ARM7TDMI-S r3
 
212
                         *
 
213
                         * REVISIT docs say ARM7TDMI-S r4 uses version 1 but
 
214
                         * that it has 6-bit CTRL and 5-bit STAT... doc bug?
 
215
                         * ARM7TDMI r4 docs say EICE v4.
 
216
                         */
144
217
                        reg_list[EICE_DBG_CTRL].size = 3;
145
218
                        reg_list[EICE_DBG_STAT].size = 5;
146
219
                        break;
147
220
                case 2:
 
221
                        /* ARM9TDMI */
148
222
                        reg_list[EICE_DBG_CTRL].size = 4;
149
223
                        reg_list[EICE_DBG_STAT].size = 5;
150
224
                        arm7_9->has_single_step = 1;
151
225
                        break;
152
226
                case 3:
153
 
                        LOG_ERROR("EmbeddedICE version 3 detected, EmbeddedICE handling might be broken");
 
227
                        LOG_ERROR("EmbeddedICE v%d handling might be broken",
 
228
                                        eice_version);
154
229
                        reg_list[EICE_DBG_CTRL].size = 6;
155
230
                        reg_list[EICE_DBG_STAT].size = 5;
156
231
                        arm7_9->has_single_step = 1;
157
232
                        arm7_9->has_monitor_mode = 1;
158
233
                        break;
159
234
                case 4:
 
235
                        /* ARM7TDMI r4 */
160
236
                        reg_list[EICE_DBG_CTRL].size = 6;
161
237
                        reg_list[EICE_DBG_STAT].size = 5;
162
238
                        arm7_9->has_monitor_mode = 1;
163
239
                        break;
164
240
                case 5:
 
241
                        /* ARM9E-S rev 1 */
165
242
                        reg_list[EICE_DBG_CTRL].size = 6;
166
243
                        reg_list[EICE_DBG_STAT].size = 5;
167
244
                        arm7_9->has_single_step = 1;
168
245
                        arm7_9->has_monitor_mode = 1;
169
246
                        break;
170
247
                case 6:
 
248
                        /* ARM7EJ-S, ARM9E-S rev 2, ARM9EJ-S */
171
249
                        reg_list[EICE_DBG_CTRL].size = 6;
172
250
                        reg_list[EICE_DBG_STAT].size = 10;
 
251
                        /* DBG_STAT has MOE bits */
173
252
                        arm7_9->has_monitor_mode = 1;
174
253
                        break;
175
254
                case 7:
176
 
                        LOG_WARNING("EmbeddedICE version 7 detected, EmbeddedICE handling might be broken");
 
255
                        LOG_ERROR("EmbeddedICE v%d handling might be broken",
 
256
                                        eice_version);
177
257
                        reg_list[EICE_DBG_CTRL].size = 6;
178
258
                        reg_list[EICE_DBG_STAT].size = 5;
179
259
                        arm7_9->has_monitor_mode = 1;
184
264
                         * in some unusual bits.  Let feroceon.c validate it
185
265
                         * and do the appropriate setup itself.
186
266
                         */
187
 
                        if (strcmp(target_get_name(target), "feroceon") == 0)
 
267
                        if (strcmp(target_get_name(target), "feroceon") == 0 ||
 
268
                            strcmp(target_get_name(target), "dragonite") == 0)
188
269
                                break;
189
270
                        LOG_ERROR("unknown EmbeddedICE version (comms ctrl: 0x%8.8" PRIx32 ")", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
190
271
        }
276
357
         * EICE_COMMS_DATA would read the register twice
277
358
         * reading the control register is safe
278
359
         */
279
 
        buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
 
360
        buf_set_u32(fields[1].out_value, 0, 5, eice_regs[EICE_COMMS_CTRL].addr);
280
361
 
281
362
        jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
282
363
 
305
386
        fields[1].tap = jtag_info->tap;
306
387
        fields[1].num_bits = 5;
307
388
        fields[1].out_value = field1_out;
308
 
        buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);
 
389
        buf_set_u32(fields[1].out_value, 0, 5, eice_regs[EICE_COMMS_DATA].addr);
309
390
        fields[1].in_value = NULL;
310
391
 
311
392
        fields[2].tap = jtag_info->tap;
322
403
                 * to avoid reading additional data from the DCC data reg
323
404
                 */
324
405
                if (size == 1)
325
 
                        buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
 
406
                        buf_set_u32(fields[1].out_value, 0, 5,
 
407
                                        eice_regs[EICE_COMMS_CTRL].addr);
326
408
 
327
409
                fields[0].in_value = (uint8_t *)data;
328
410
                jtag_add_dr_scan(3, fields, jtag_get_end_state());
407
489
        fields[1].tap = jtag_info->tap;
408
490
        fields[1].num_bits = 5;
409
491
        fields[1].out_value = field1_out;
410
 
        buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);
 
492
        buf_set_u32(fields[1].out_value, 0, 5, eice_regs[EICE_COMMS_DATA].addr);
411
493
        fields[1].in_value = NULL;
412
494
 
413
495
        fields[2].tap = jtag_info->tap;
462
544
        fields[1].tap = jtag_info->tap;
463
545
        fields[1].num_bits = 5;
464
546
        fields[1].out_value = field1_out;
465
 
        buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
 
547
        buf_set_u32(fields[1].out_value, 0, 5, eice_regs[EICE_COMMS_DATA].addr);
466
548
        fields[1].in_value = NULL;
467
549
 
468
550
        fields[2].tap = jtag_info->tap;