1
/****************************************************************************
2
* Copyright (c) 2006 by Michael Fischer. All rights reserved.
4
* Redistribution and use in source and binary forms, with or without
5
* modification, are permitted provided that the following conditions
8
* 1. Redistributions of source code must retain the above copyright
9
* notice, this list of conditions and the following disclaimer.
10
* 2. Redistributions in binary form must reproduce the above copyright
11
* notice, this list of conditions and the following disclaimer in the
12
* documentation and/or other materials provided with the distribution.
13
* 3. Neither the name of the author nor the names of its contributors may
14
* be used to endorse or promote products derived from this software
15
* without specific prior written permission.
17
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
20
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21
* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
22
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
23
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
24
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
25
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
27
* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30
****************************************************************************
34
* 04.03.06 mifi First Version
35
* This version based on an example from Ethernut and
36
* "ARM Cross Development with Eclipse" from James P. Lynch
37
****************************************************************************/
40
* Some defines for the program status registers
42
ARM_MODE_USER = 0x10 /* Normal User Mode */
43
ARM_MODE_FIQ = 0x11 /* FIQ Fast Interrupts Mode */
44
ARM_MODE_IRQ = 0x12 /* IRQ Standard Interrupts Mode */
45
ARM_MODE_SVC = 0x13 /* Supervisor Interrupts Mode */
46
ARM_MODE_ABORT = 0x17 /* Abort Processing memory Faults Mode */
47
ARM_MODE_UNDEF = 0x1B /* Undefined Instructions Mode */
48
ARM_MODE_SYS = 0x1F /* System Running in Priviledged Operating Mode */
51
I_BIT = 0x80 /* disable IRQ when I bit is set */
52
F_BIT = 0x40 /* disable IRQ when I bit is set */
55
* Register Base Address
57
PRCCU_BASE = 0xA0000000
67
.section .vectors,"ax"
70
/****************************************************************************/
71
/* Vector table and reset entry */
72
/****************************************************************************/
74
ldr pc, ResetAddr /* Reset */
75
ldr pc, UndefAddr /* Undefined instruction */
76
ldr pc, SWIAddr /* Software interrupt */
77
ldr pc, PAbortAddr /* Prefetch abort */
78
ldr pc, DAbortAddr /* Data abort */
79
ldr pc, ReservedAddr /* Reserved */
80
ldr pc, IRQAddr /* IRQ interrupt */
81
ldr pc, FIQAddr /* FIQ interrupt */
84
ResetAddr: .word ResetHandler
85
UndefAddr: .word UndefHandler
86
SWIAddr: .word SWIHandler
87
PAbortAddr: .word PAbortHandler
88
DAbortAddr: .word DAbortHandler
90
IRQAddr: .word IRQHandler
91
FIQAddr: .word FIQHandler
102
/****************************************************************************/
104
/****************************************************************************/
107
* Wait for the oscillator is stable
119
* Setup STR71X, for more information about the register
120
* take a look in the STR71x Microcontroller Reference Manual.
122
* Reference is made to: Rev. 6 March 2005
124
* 1. Map internal RAM to address 0
125
* In this case, we are running always in the RAM
126
* this make no sence. But if we are in flash, we
127
* can copy the interrupt vectors into the ram and
128
* switch to RAM mode.
130
* 2. Setup the PLL, the eval board HITEX STR7 is equipped
131
* with an external 16MHz oscillator. We want:
133
* RCLK: 32MHz = (CLK2 * 16) / 4
141
* 1. Map RAM to the boot memory 0x00000000
145
str r1, [r0, #PCU_BOOTCR]
152
/* Set the prescaling factor for APB and APB1 group */
154
ldr r1, =0x0000 /* no prescaling PCLKx = RCLK */
155
str r1, [r0, #PCU_PDIVR]
157
/* Set the prescaling factor for the Main System Clock MCLK */
159
ldr r1, =0x0000 /* no prescaling MCLK = RCLK
160
str r1, [r0, #PCU_MDIVR]
162
/* Configure the PLL1 ( * 16 , / 4 ) */
165
str r1, [r0, #RCCU_PLL1CR]
167
/* Check if the PLL is locked */
169
ldr r1, [r0, #RCCU_CFR]
173
/* Select PLL1_Output as RCLK clock */
176
str r1, [r0, #RCCU_CFR]
184
* Setup a stack for each mode
186
msr CPSR_c, #ARM_MODE_UNDEF | I_BIT | F_BIT /* Undefined Instruction Mode */
187
ldr sp, =__stack_und_end
189
msr CPSR_c, #ARM_MODE_ABORT | I_BIT | F_BIT /* Abort Mode */
190
ldr sp, =__stack_abt_end
192
msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT /* FIQ Mode */
193
ldr sp, =__stack_fiq_end
195
msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT /* IRQ Mode */
196
ldr sp, =__stack_irq_end
198
msr CPSR_c, #ARM_MODE_SVC | I_BIT | F_BIT /* Supervisor Mode */
199
ldr sp, =__stack_svc_end
218
bic r0, r0, #I_BIT | F_BIT /* Enable FIQ and IRQ interrupt */
221
mov r0, #0 /* No arguments */
222
mov r1, #0 /* No arguments */
225
bx r2 /* And jump... */
234
/****************************************************************************/
235
/* Default interrupt handler */
236
/****************************************************************************/
257
.weak UndefHandler, PAbortHandler, DAbortHandler
258
.weak IRQHandler, FIQHandler
added
removed
testing/examples/STR710JtagSpeed/src/crt.s
