~ubuntu-branches/debian/sid/gcc-4.8/sid : revision 78

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# DP: Implements D CPU version conditions.

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This implements the following versions:

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* D_HardFloat

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* D_SoftFloat

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for all supported architectures. And these where appropriate:

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* ARM

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** ARM_Thumb

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** ARM_HardFloat

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** ARM_SoftFloat

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** ARM_SoftFP

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* AArch64

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* Alpha

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** Alpha_SoftFloat

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** Alpha_HardFloat

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* X86

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* X86_64

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** D_X32

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* IA64

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* MIPS32

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* MIPS64

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** MIPS_O32

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** MIPS_O64

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** MIPS_N32

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** MIPS_N64

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** MIPS_EABI

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** MIPS_HardFloat

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** MIPS_SoftFloat

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* HPPA

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* HPPA64

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* PPC

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* PPC64

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** PPC_HardFloat

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** PPC_SoftFloat

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* S390

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* S390X

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* SH

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* SH64

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* SPARC

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* SPARC64

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* SPARC_V8Plus

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** SPARC_HardFloat

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** SPARC_SoftFloat

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--- a/src/gcc/config/aarch64/aarch64.h

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+++ b/src/gcc/config/aarch64/aarch64.h

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@@ -51,6 +51,14 @@

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\

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} while (0)

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+/* Target CPU builtins for D. */

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+#define TARGET_CPU_D_BUILTINS() \

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+ do \

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+ { \

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+ builtin_define ("AArch64"); \

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+ builtin_define ("D_HardFloat"); \

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+ } while (0)

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+

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/* Target machine storage layout. */

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--- a/src/gcc/config/alpha/alpha.h

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+++ b/src/gcc/config/alpha/alpha.h

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@@ -72,6 +72,23 @@ along with GCC; see the file COPYING3.

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SUBTARGET_LANGUAGE_CPP_BUILTINS(); \

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} while (0)

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+/* Target CPU builtins for D. */

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+#define TARGET_CPU_D_BUILTINS() \

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+ do \

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+ { \

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+ builtin_define ("Alpha"); \

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+ if (TARGET_SOFT_FP) \

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+ { \

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+ builtin_define ("D_SoftFloat"); \

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+ builtin_define ("Alpha_SoftFloat"); \

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+ } \

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+ else \

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+ { \

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+ builtin_define ("D_HardFloat"); \

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+ builtin_define ("Alpha_HardFloat"); \

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+ } \

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+} while (0)

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+

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#ifndef SUBTARGET_LANGUAGE_CPP_BUILTINS

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#define SUBTARGET_LANGUAGE_CPP_BUILTINS() \

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do \

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--- a/src/gcc/config/arm/arm.h

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+++ b/src/gcc/config/arm/arm.h

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@@ -158,6 +158,31 @@ extern char arm_arch_name[];

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builtin_define ("__ARM_ARCH_EXT_IDIV__"); \

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} while (0)

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+/* Target CPU builtins for D. */

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+#define TARGET_CPU_D_BUILTINS() \

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+ do \

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+ { \

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+ builtin_define ("ARM"); \

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+ \

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+ if (TARGET_THUMB || TARGET_THUMB2) \

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+ builtin_define ("ARM_Thumb"); \

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+ \

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+ if (TARGET_HARD_FLOAT_ABI) \

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+ builtin_define ("ARM_HardFloat"); \

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+ else \

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+ { \

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+ if(TARGET_SOFT_FLOAT) \

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+ builtin_define ("ARM_SoftFloat"); \

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+ else if(TARGET_HARD_FLOAT) \

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+ builtin_define ("ARM_SoftFP"); \

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+ } \

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+ \

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+ if(TARGET_SOFT_FLOAT) \

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+ builtin_define ("D_SoftFloat"); \

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+ else if(TARGET_HARD_FLOAT) \

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+ builtin_define ("D_HardFloat"); \

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+ } while (0)

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+

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#include "config/arm/arm-opts.h"

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enum target_cpus

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--- a/src/gcc/config/i386/i386.h

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+++ b/src/gcc/config/i386/i386.h

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@@ -588,6 +588,24 @@ extern const char *host_detect_local_cpu

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/* Target CPU builtins. */

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#define TARGET_CPU_CPP_BUILTINS() ix86_target_macros ()

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+/* Target CPU builtins for D. */

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+#define TARGET_CPU_D_BUILTINS() \

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+ do { \

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+ if (TARGET_64BIT) \

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+ { \

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+ builtin_define("X86_64"); \

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+ if (TARGET_X32) \

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+ builtin_define("D_X32"); \

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+ } \

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+ else \

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+ builtin_define("X86"); \

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+ \

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+ if (TARGET_80387) \

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+ builtin_define("D_HardFloat"); \

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+ else \

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+ builtin_define("D_SoftFloat"); \

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+ } while (0)

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+

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/* Target Pragmas. */

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#define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas ()

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--- a/src/gcc/config/ia64/ia64.h

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+++ b/src/gcc/config/ia64/ia64.h

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@@ -40,6 +40,13 @@ do { \

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builtin_define("__BIG_ENDIAN__"); \

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} while (0)

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+/* Target CPU builtins for D. */

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+#define TARGET_CPU_D_BUILTINS() \

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+do { \

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+ builtin_define ("IA64"); \

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+ builtin_define ("D_HardFloat"); \

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+} while (0)

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+

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#ifndef SUBTARGET_EXTRA_SPECS

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#define SUBTARGET_EXTRA_SPECS

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#endif

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--- a/src/gcc/config/mips/mips.h

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+++ b/src/gcc/config/mips/mips.h

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@@ -551,6 +551,54 @@ struct mips_cpu_info {

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} \

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while (0)

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+/* Target CPU builtins for D. */

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+#define TARGET_CPU_D_BUILTINS() \

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+ do \

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+ { \

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+ if (TARGET_64BIT) \

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+ builtin_define("MIPS64"); \

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+ else \

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+ builtin_define("MIPS32"); \

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+ \

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+ switch (mips_abi) \

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+ { \

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+ case ABI_32: \

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+ builtin_define("MIPS_O32"); \

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+ break; \

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+ \

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+ case ABI_O64: \

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+ builtin_define("MIPS_O64"); \

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+ break; \

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+ \

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+ case ABI_N32: \

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+ builtin_define("MIPS_N32"); \

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+ break; \

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+ \

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+ case ABI_64: \

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+ builtin_define("MIPS_N64"); \

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+ break; \

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+ \

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+ case ABI_EABI: \

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+ builtin_define("MIPS_EABI"); \

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+ break; \

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+ \

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+ default: \

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+ gcc_unreachable(); \

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+ } \

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+ \

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+ if (TARGET_HARD_FLOAT_ABI) \

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+ { \

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+ builtin_define("MIPS_HardFloat"); \

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+ builtin_define("D_HardFloat"); \

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+ } \

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+ else if (TARGET_SOFT_FLOAT_ABI) \

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+ { \

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+ builtin_define("MIPS_SoftFloat"); \

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+ builtin_define("D_SoftFloat"); \

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+ } \

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+ } \

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+ while (0)

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+

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/* Default target_flags if no switches are specified */

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#ifndef TARGET_DEFAULT

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--- a/src/gcc/config/pa/pa.h

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+++ b/src/gcc/config/pa/pa.h

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@@ -185,6 +185,20 @@ do { \

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builtin_define("_PA_RISC1_0"); \

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} while (0)

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+/* Target CPU builtins for D. */

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+#define TARGET_CPU_D_BUILTINS() \

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+do { \

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+ if(TARGET_64BIT) \

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+ builtin_define("HPPA64"); \

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+ else \

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+ builtin_define("HPPA"); \

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+ \

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+ if(TARGET_SOFT_FLOAT) \

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+ builtin_define ("D_SoftFloat"); \

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+ else \

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+ builtin_define ("D_HardFloat"); \

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+} while (0)

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+

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/* An old set of OS defines for various BSD-like systems. */

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#define TARGET_OS_CPP_BUILTINS() \

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do \

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--- a/src/gcc/config/rs6000/rs6000.h

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+++ b/src/gcc/config/rs6000/rs6000.h

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@@ -613,6 +613,28 @@ extern unsigned char rs6000_recip_bits[]

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#define TARGET_CPU_CPP_BUILTINS() \

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rs6000_cpu_cpp_builtins (pfile)

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+/* Target CPU builtins for D. */

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+#define TARGET_CPU_D_BUILTINS() \

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+ do \

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+ { \

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+ if (TARGET_64BIT) \

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+ builtin_define ("PPC64"); \

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+ else \

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+ builtin_define ("PPC"); \

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+ \

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+ if (TARGET_HARD_FLOAT) \

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+ { \

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+ builtin_define ("PPC_HardFloat"); \

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+ builtin_define ("D_HardFloat"); \

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+ } \

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+ else if (TARGET_SOFT_FLOAT) \

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+ { \

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+ builtin_define ("PPC_SoftFloat"); \

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+ builtin_define ("D_SoftFloat"); \

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+ } \

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+ } \

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+ while (0)

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+

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/* This is used by rs6000_cpu_cpp_builtins to indicate the byte order

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we're compiling for. Some configurations may need to override it. */

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#define RS6000_CPU_CPP_ENDIAN_BUILTINS() \

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--- a/src/gcc/config/s390/s390.h

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+++ b/src/gcc/config/s390/s390.h

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@@ -108,6 +108,22 @@ enum processor_flags

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} \

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while (0)

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+/* Target CPU builtins for D. */

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+#define TARGET_CPU_D_BUILTINS() \

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+ do \

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+ { \

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+ if (TARGET_64BIT) \

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+ builtin_define ("S390X"); \

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+ else \

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+ builtin_define ("S390"); \

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+ \

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+ if(TARGET_SOFT_FLOAT) \

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+ builtin_define ("D_SoftFloat"); \

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+ else if(TARGET_HARD_FLOAT) \

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+ builtin_define ("D_HardFloat"); \

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+ } \

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+ while (0)

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+

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#ifdef DEFAULT_TARGET_64BIT

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#define TARGET_DEFAULT (MASK_64BIT | MASK_ZARCH | MASK_HARD_DFP)

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#else

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--- a/src/gcc/config/sh/sh.h

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+++ b/src/gcc/config/sh/sh.h

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@@ -31,6 +31,22 @@ extern int code_for_indirect_jump_scratc

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#define TARGET_CPU_CPP_BUILTINS() sh_cpu_cpp_builtins (pfile)

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+/* Target CPU builtins for D. */

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+#define TARGET_CPU_D_BUILTINS() \

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+ do \

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+ { \

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+ if (TARGET_SHMEDIA64) \

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+ builtin_define ("SH64"); \

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+ else \

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+ builtin_define ("SH"); \

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+ \

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+ if (TARGET_FPU_ANY) \

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+ builtin_define ("D_HardFloat"); \

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+ else \

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+ builtin_define ("D_SoftFloat"); \

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+ } \

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+ while (0)

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+

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/* Value should be nonzero if functions must have frame pointers.

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Zero means the frame pointer need not be set up (and parms may be accessed

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via the stack pointer) in functions that seem suitable. */

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--- a/src/gcc/config/sparc/sparc.h

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+++ b/src/gcc/config/sparc/sparc.h

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@@ -27,6 +27,31 @@ along with GCC; see the file COPYING3.

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#define TARGET_CPU_CPP_BUILTINS() sparc_target_macros ()

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+/* Target CPU builtins for D. */

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+#define TARGET_CPU_D_BUILTINS() \

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+do \

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+ { \

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+ if (TARGET_64BIT) \

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+ builtin_define ("SPARC64"); \

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+ else \

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+ builtin_define ("SPARC"); \

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+ \

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+ if(TARGET_V8PLUS) \

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+ builtin_define ("SPARC_V8Plus"); \

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+ \

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+ if(TARGET_FPU) \

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+ { \

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+ builtin_define ("D_HardFloat"); \

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+ builtin_define ("SPARC_HardFloat"); \

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+ } \

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+ else \

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+ { \

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+ builtin_define ("D_SoftFloat"); \

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+ builtin_define ("SPARC_SoftFloat"); \

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+ } \

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+ } \

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+ while (0)

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+

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/* Specify this in a cover file to provide bi-architecture (32/64) support. */

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/* #define SPARC_BI_ARCH */

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