1
# DP: Changes for the Linaro 4.8-2014.03 release (documentation).
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Index: b/src/gcc/doc/extend.texi
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===================================================================
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--- a/src/gcc/doc/extend.texi
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+++ b/src/gcc/doc/extend.texi
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* Alpha Built-in Functions::
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* ARM iWMMXt Built-in Functions::
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* ARM NEON Intrinsics::
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+* ARM ACLE Intrinsics::
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* AVR Built-in Functions::
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* Blackfin Built-in Functions::
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* FR-V Built-in Functions::
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@@ -9046,6 +9047,14 @@
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@include arm-neon-intrinsics.texi
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+@node ARM ACLE Intrinsics
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+@subsection ARM ACLE Intrinsics
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+These built-in intrinsics for the ARMv8-A CRC32 extension are available when
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+the @option{-march=armv8-a+crc} switch is used:
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+@include arm-acle-intrinsics.texi
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@node AVR Built-in Functions
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@subsection AVR Built-in Functions
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Index: b/src/gcc/doc/arm-acle-intrinsics.texi
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===================================================================
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+++ b/src/gcc/doc/arm-acle-intrinsics.texi
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+@c Copyright (C) 2013-2014 Free Software Foundation, Inc.
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+@c This is part of the GCC manual.
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+@c For copying conditions, see the file gcc.texi.
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+@subsubsection CRC32 intrinsics
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+@item uint32_t __crc32b (uint32_t, uint8_t)
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+@*@emph{Form of expected instruction(s):} @code{crc32b @var{r0}, @var{r0}, @var{r0}}
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+@item uint32_t __crc32h (uint32_t, uint16_t)
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+@*@emph{Form of expected instruction(s):} @code{crc32h @var{r0}, @var{r0}, @var{r0}}
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+@item uint32_t __crc32w (uint32_t, uint32_t)
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+@*@emph{Form of expected instruction(s):} @code{crc32w @var{r0}, @var{r0}, @var{r0}}
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+@item uint32_t __crc32d (uint32_t, uint64_t)
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+@*@emph{Form of expected instruction(s):} Two @code{crc32w @var{r0}, @var{r0}, @var{r0}}
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+instructions for AArch32. One @code{crc32w @var{w0}, @var{w0}, @var{x0}} instruction for
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+@item uint32_t __crc32cb (uint32_t, uint8_t)
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+@*@emph{Form of expected instruction(s):} @code{crc32cb @var{r0}, @var{r0}, @var{r0}}
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+@item uint32_t __crc32ch (uint32_t, uint16_t)
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+@*@emph{Form of expected instruction(s):} @code{crc32ch @var{r0}, @var{r0}, @var{r0}}
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+@item uint32_t __crc32cw (uint32_t, uint32_t)
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+@*@emph{Form of expected instruction(s):} @code{crc32cw @var{r0}, @var{r0}, @var{r0}}
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+@item uint32_t __crc32cd (uint32_t, uint64_t)
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+@*@emph{Form of expected instruction(s):} Two @code{crc32cw @var{r0}, @var{r0}, @var{r0}}
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+instructions for AArch32. One @code{crc32cw @var{w0}, @var{w0}, @var{x0}} instruction for
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Index: b/src/gcc/doc/tm.texi
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===================================================================
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--- a/src/gcc/doc/tm.texi
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+++ b/src/gcc/doc/tm.texi
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@@ -10926,8 +10926,16 @@
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@samp{TARGET_INIT_BUILTINS}. @var{fndecl} is the declaration of the
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built-in function. @var{n_args} is the number of arguments passed to
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the function; the arguments themselves are pointed to by @var{argp}.
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-The result is another tree containing a simplified expression for the
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-call's result. If @var{ignore} is true the value will be ignored.
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+The result is another tree, valid for both GIMPLE and GENERIC,
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+containing a simplified expression for the call's result. If
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+@var{ignore} is true the value will be ignored.
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+@deftypefn {Target Hook} bool TARGET_GIMPLE_FOLD_BUILTIN (gimple_stmt_iterator *@var{gsi})
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+Fold a call to a machine specific built-in function that was set up
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+by @samp{TARGET_INIT_BUILTINS}. @var{gsi} points to the gimple
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+statement holding the function call. Returns true if any change
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+was made to the GIMPLE stream.
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@deftypefn {Target Hook} int TARGET_COMPARE_VERSION_PRIORITY (tree @var{decl1}, tree @var{decl2})
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Index: b/src/gcc/doc/tm.texi.in
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===================================================================
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--- a/src/gcc/doc/tm.texi.in
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+++ b/src/gcc/doc/tm.texi.in
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@@ -10772,10 +10772,13 @@
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@samp{TARGET_INIT_BUILTINS}. @var{fndecl} is the declaration of the
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built-in function. @var{n_args} is the number of arguments passed to
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the function; the arguments themselves are pointed to by @var{argp}.
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-The result is another tree containing a simplified expression for the
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-call's result. If @var{ignore} is true the value will be ignored.
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+The result is another tree, valid for both GIMPLE and GENERIC,
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+containing a simplified expression for the call's result. If
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+@var{ignore} is true the value will be ignored.
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+@hook TARGET_GIMPLE_FOLD_BUILTIN
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@hook TARGET_COMPARE_VERSION_PRIORITY
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This hook is used to compare the target attributes in two functions to
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determine which function's features get higher priority. This is used
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Index: b/src/gcc/doc/invoke.texi
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===================================================================
135
--- a/src/gcc/doc/invoke.texi
136
+++ b/src/gcc/doc/invoke.texi
138
-ftree-parallelize-loops=@var{n} -ftree-pre -ftree-partial-pre -ftree-pta @gol
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-ftree-reassoc -ftree-sink -ftree-slsr -ftree-sra @gol
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-ftree-switch-conversion -ftree-tail-merge @gol
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--ftree-ter -ftree-vect-loop-version -ftree-vectorize -ftree-vrp @gol
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+-ftree-ter -ftree-vectorize -ftree-vrp @gol
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-funit-at-a-time -funroll-all-loops -funroll-loops @gol
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-funsafe-loop-optimizations -funsafe-math-optimizations -funswitch-loops @gol
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-fvariable-expansion-in-unroller -fvect-cost-model -fvpt -fweb @gol
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-mtp=@var{name} -mtls-dialect=@var{dialect} @gol
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-mword-relocations @gol
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-mfix-cortex-m3-ldrd @gol
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+-munaligned-access @gol
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+-mneon-for-64bits @gol
156
@gccoptlist{-mmcu=@var{mcu} -maccumulate-args -mbranch-cost=@var{cost} @gol
157
@@ -6590,7 +6592,7 @@
158
@option{-Os} disables the following optimization flags:
159
@gccoptlist{-falign-functions -falign-jumps -falign-loops @gol
160
-falign-labels -freorder-blocks -freorder-blocks-and-partition @gol
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--fprefetch-loop-arrays -ftree-vect-loop-version}
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+-fprefetch-loop-arrays}
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@@ -7831,19 +7833,20 @@
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Perform basic block vectorization on trees. This flag is enabled by default at
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@option{-O3} and when @option{-ftree-vectorize} is enabled.
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-@item -ftree-vect-loop-version
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-@opindex ftree-vect-loop-version
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-Perform loop versioning when doing loop vectorization on trees. When a loop
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-appears to be vectorizable except that data alignment or data dependence cannot
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-be determined at compile time, then vectorized and non-vectorized versions of
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-the loop are generated along with run-time checks for alignment or dependence
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-to control which version is executed. This option is enabled by default
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-except at level @option{-Os} where it is disabled.
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-@item -fvect-cost-model
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+@item -fvect-cost-model=@var{model}
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@opindex fvect-cost-model
182
-Enable cost model for vectorization. This option is enabled by default at
184
+Alter the cost model used for vectorization. The @var{model} argument
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+should be one of @code{unlimited}, @code{dynamic} or @code{cheap}.
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+With the @code{unlimited} model the vectorized code-path is assumed
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+to be profitable while with the @code{dynamic} model a runtime check
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+will guard the vectorized code-path to enable it only for iteration
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+counts that will likely execute faster than when executing the original
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+scalar loop. The @code{cheap} model will disable vectorization of
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+loops where doing so would be cost prohibitive for example due to
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+required runtime checks for data dependence or alignment but otherwise
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+is equal to the @code{dynamic} model.
194
+The default cost model depends on other optimization flags and is
195
+either @code{dynamic} or @code{cheap}.
199
@@ -9239,13 +9242,15 @@
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@item vect-max-version-for-alignment-checks
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The maximum number of run-time checks that can be performed when
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-doing loop versioning for alignment in the vectorizer. See option
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-@option{-ftree-vect-loop-version} for more information.
205
+doing loop versioning for alignment in the vectorizer.
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@item vect-max-version-for-alias-checks
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The maximum number of run-time checks that can be performed when
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-doing loop versioning for alias in the vectorizer. See option
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-@option{-ftree-vect-loop-version} for more information.
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+doing loop versioning for alias in the vectorizer.
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+@item vect-max-peeling-for-alignment
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+The maximum number of loop peels to enhance access alignment
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+for vectorizer. Value -1 means 'no limit'.
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@item max-iterations-to-track
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The maximum number of iterations of a loop the brute-force algorithm
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@@ -10966,6 +10971,8 @@
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+Enable CRC extension.
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Enable Crypto extension. This implies Advanced SIMD is enabled.
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@@ -11263,8 +11270,8 @@
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@samp{arm1136j-s}, @samp{arm1136jf-s}, @samp{mpcore}, @samp{mpcorenovfp},
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@samp{arm1156t2-s}, @samp{arm1156t2f-s}, @samp{arm1176jz-s}, @samp{arm1176jzf-s},
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@samp{cortex-a5}, @samp{cortex-a7}, @samp{cortex-a8}, @samp{cortex-a9},
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-@samp{cortex-a15}, @samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-r5},
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-@samp{cortex-m4}, @samp{cortex-m3},
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+@samp{cortex-a15}, @samp{cortex-a53}, @samp{cortex-r4}, @samp{cortex-r4f},
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+@samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-m4}, @samp{cortex-m3},
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@samp{cortex-m0plus},
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@@ -11317,9 +11324,12 @@
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@samp{armv6}, @samp{armv6j},
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@samp{armv6t2}, @samp{armv6z}, @samp{armv6zk}, @samp{armv6-m},
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@samp{armv7}, @samp{armv7-a}, @samp{armv7-r}, @samp{armv7-m},
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+@samp{armv8-a}, @samp{armv8-a+crc},
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@samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}.
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+@option{-march=armv8-a+crc} enables code generation for the ARMv8-A
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+architecture together with the optional CRC32 extensions.
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@option{-march=native} causes the compiler to auto-detect the architecture
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of the build computer. At present, this feature is only supported on
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Linux, and not all architectures are recognized. If the auto-detect is
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@@ -11527,6 +11537,17 @@
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preprocessor symbol @code{__ARM_FEATURE_UNALIGNED} will also be
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+@item -mneon-for-64bits
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+@opindex mneon-for-64bits
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+Enables using Neon to handle scalar 64-bits operations. This is
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+disabled by default since the cost of moving data from core registers
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+@opindex mrestrict-it
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+Restricts generation of IT blocks to conform to the rules of ARMv8.
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+IT blocks can only contain a single 16-bit instruction from a select
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+set of instructions. This option is on by default for ARMv8 Thumb mode.
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Index: b/src/gcc/doc/arm-neon-intrinsics.texi
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===================================================================
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--- a/src/gcc/doc/arm-neon-intrinsics.texi
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+++ b/src/gcc/doc/arm-neon-intrinsics.texi
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@@ -4079,6 +4079,12 @@
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@subsubsection Vector shift right and insert
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+@item poly64x1_t vsri_n_p64 (poly64x1_t, poly64x1_t, const int)
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+@*@emph{Form of expected instruction(s):} @code{vsri.64 @var{d0}, @var{d0}, #@var{0}}
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@item uint32x2_t vsri_n_u32 (uint32x2_t, uint32x2_t, const int)
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@*@emph{Form of expected instruction(s):} @code{vsri.32 @var{d0}, @var{d0}, #@var{0}}
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@@ -4139,6 +4145,12 @@
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+@item poly64x2_t vsriq_n_p64 (poly64x2_t, poly64x2_t, const int)
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+@*@emph{Form of expected instruction(s):} @code{vsri.64 @var{q0}, @var{q0}, #@var{0}}
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@item uint32x4_t vsriq_n_u32 (uint32x4_t, uint32x4_t, const int)
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@*@emph{Form of expected instruction(s):} @code{vsri.32 @var{q0}, @var{q0}, #@var{0}}
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@@ -4203,6 +4215,12 @@
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@subsubsection Vector shift left and insert
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+@item poly64x1_t vsli_n_p64 (poly64x1_t, poly64x1_t, const int)
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+@*@emph{Form of expected instruction(s):} @code{vsli.64 @var{d0}, @var{d0}, #@var{0}}
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@item uint32x2_t vsli_n_u32 (uint32x2_t, uint32x2_t, const int)
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@*@emph{Form of expected instruction(s):} @code{vsli.32 @var{d0}, @var{d0}, #@var{0}}
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@@ -4263,6 +4281,12 @@
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+@item poly64x2_t vsliq_n_p64 (poly64x2_t, poly64x2_t, const int)
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+@*@emph{Form of expected instruction(s):} @code{vsli.64 @var{q0}, @var{q0}, #@var{0}}
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@item uint32x4_t vsliq_n_u32 (uint32x4_t, uint32x4_t, const int)
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@*@emph{Form of expected instruction(s):} @code{vsli.32 @var{q0}, @var{q0}, #@var{0}}
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@@ -5071,6 +5095,11 @@
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@subsubsection Create vector from literal bit pattern
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+@item poly64x1_t vcreate_p64 (uint64_t)
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@item uint32x2_t vcreate_u32 (uint64_t)
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@@ -5184,6 +5213,11 @@
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+@item poly64x1_t vdup_n_p64 (poly64_t)
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@item uint64x1_t vdup_n_u64 (uint64_t)
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@@ -5194,6 +5228,11 @@
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+@item poly64x2_t vdupq_n_p64 (poly64_t)
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@item uint32x4_t vdupq_n_u32 (uint32_t)
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@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
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@@ -5440,6 +5479,11 @@
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+@item poly64x1_t vdup_lane_p64 (poly64x1_t, const int)
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@item uint64x1_t vdup_lane_u64 (uint64x1_t, const int)
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@@ -5504,6 +5548,11 @@
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+@item poly64x2_t vdupq_lane_p64 (poly64x1_t, const int)
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@item uint64x2_t vdupq_lane_u64 (uint64x1_t, const int)
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@@ -5518,6 +5567,11 @@
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@subsubsection Combining vectors
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+@item poly64x2_t vcombine_p64 (poly64x1_t, poly64x1_t)
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@item uint32x4_t vcombine_u32 (uint32x2_t, uint32x2_t)
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@@ -5577,6 +5631,11 @@
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@subsubsection Splitting vectors
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+@item poly64x1_t vget_high_p64 (poly64x2_t)
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@item uint32x2_t vget_high_u32 (uint32x4_t)
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@@ -5686,6 +5745,11 @@
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+@item poly64x1_t vget_low_p64 (poly64x2_t)
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@item uint64x1_t vget_low_u64 (uint64x2_t)
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@@ -5748,6 +5812,18 @@
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+@item float16x4_t vcvt_f16_f32 (float32x4_t)
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+@*@emph{Form of expected instruction(s):} @code{vcvt.f16.f32 @var{d0}, @var{q0}}
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+@item float32x4_t vcvt_f32_f16 (float16x4_t)
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+@*@emph{Form of expected instruction(s):} @code{vcvt.f32.f16 @var{q0}, @var{d0}}
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@item float32x2_t vcvt_n_f32_u32 (uint32x2_t, const int)
440
@*@emph{Form of expected instruction(s):} @code{vcvt.f32.u32 @var{d0}, @var{d0}, #@var{0}}
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@@ -6806,6 +6882,12 @@
443
@subsubsection Vector extract
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+@item poly64x1_t vext_p64 (poly64x1_t, poly64x1_t, const int)
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+@*@emph{Form of expected instruction(s):} @code{vext.64 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
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@item uint32x2_t vext_u32 (uint32x2_t, uint32x2_t, const int)
453
@*@emph{Form of expected instruction(s):} @code{vext.32 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
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@@ -6872,6 +6954,12 @@
459
+@item poly64x2_t vextq_p64 (poly64x2_t, poly64x2_t, const int)
460
+@*@emph{Form of expected instruction(s):} @code{vext.64 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
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@item uint32x4_t vextq_u32 (uint32x4_t, uint32x4_t, const int)
466
@*@emph{Form of expected instruction(s):} @code{vext.32 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
468
@@ -7162,6 +7250,12 @@
469
@subsubsection Bit selection
472
+@item poly64x1_t vbsl_p64 (uint64x1_t, poly64x1_t, poly64x1_t)
473
+@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
478
@item uint32x2_t vbsl_u32 (uint32x2_t, uint32x2_t, uint32x2_t)
479
@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
481
@@ -7228,6 +7322,12 @@
485
+@item poly64x2_t vbslq_p64 (uint64x2_t, poly64x2_t, poly64x2_t)
486
+@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
491
@item uint32x4_t vbslq_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
492
@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
494
@@ -7634,6 +7734,12 @@
495
@subsubsection Element/structure loads, VLD1 variants
498
+@item poly64x1_t vld1_p64 (const poly64_t *)
499
+@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
504
@item uint32x2_t vld1_u32 (const uint32_t *)
505
@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}@}, [@var{r0}]}
507
@@ -7700,6 +7806,12 @@
511
+@item poly64x2_t vld1q_p64 (const poly64_t *)
512
+@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
517
@item uint32x4_t vld1q_u32 (const uint32_t *)
518
@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
520
@@ -7820,6 +7932,12 @@
524
+@item poly64x1_t vld1_lane_p64 (const poly64_t *, poly64x1_t, const int)
525
+@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
530
@item uint64x1_t vld1_lane_u64 (const uint64_t *, uint64x1_t, const int)
531
@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
533
@@ -7886,6 +8004,12 @@
537
+@item poly64x2_t vld1q_lane_p64 (const poly64_t *, poly64x2_t, const int)
538
+@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
543
@item uint64x2_t vld1q_lane_u64 (const uint64_t *, uint64x2_t, const int)
544
@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
546
@@ -7952,6 +8076,12 @@
550
+@item poly64x1_t vld1_dup_p64 (const poly64_t *)
551
+@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
556
@item uint64x1_t vld1_dup_u64 (const uint64_t *)
557
@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
559
@@ -8018,6 +8148,12 @@
563
+@item poly64x2_t vld1q_dup_p64 (const poly64_t *)
564
+@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
569
@item uint64x2_t vld1q_dup_u64 (const uint64_t *)
570
@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
572
@@ -8034,6 +8170,12 @@
573
@subsubsection Element/structure stores, VST1 variants
576
+@item void vst1_p64 (poly64_t *, poly64x1_t)
577
+@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
582
@item void vst1_u32 (uint32_t *, uint32x2_t)
583
@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}@}, [@var{r0}]}
585
@@ -8100,6 +8242,12 @@
589
+@item void vst1q_p64 (poly64_t *, poly64x2_t)
590
+@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
595
@item void vst1q_u32 (uint32_t *, uint32x4_t)
596
@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
598
@@ -8220,6 +8368,12 @@
602
+@item void vst1_lane_p64 (poly64_t *, poly64x1_t, const int)
603
+@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
608
@item void vst1_lane_s64 (int64_t *, int64x1_t, const int)
609
@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
611
@@ -8286,6 +8440,12 @@
615
+@item void vst1q_lane_p64 (poly64_t *, poly64x2_t, const int)
616
+@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
621
@item void vst1q_lane_s64 (int64_t *, int64x2_t, const int)
622
@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
624
@@ -8356,6 +8516,12 @@
628
+@item poly64x1x2_t vld2_p64 (const poly64_t *)
629
+@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
634
@item uint64x1x2_t vld2_u64 (const uint64_t *)
635
@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
637
@@ -8566,6 +8732,12 @@
641
+@item poly64x1x2_t vld2_dup_p64 (const poly64_t *)
642
+@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
647
@item uint64x1x2_t vld2_dup_u64 (const uint64_t *)
648
@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
650
@@ -8636,6 +8808,12 @@
654
+@item void vst2_p64 (poly64_t *, poly64x1x2_t)
655
+@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
660
@item void vst2_u64 (uint64_t *, uint64x1x2_t)
661
@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
663
@@ -8850,6 +9028,12 @@
667
+@item poly64x1x3_t vld3_p64 (const poly64_t *)
668
+@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
673
@item uint64x1x3_t vld3_u64 (const uint64_t *)
674
@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
676
@@ -9060,6 +9244,12 @@
680
+@item poly64x1x3_t vld3_dup_p64 (const poly64_t *)
681
+@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
686
@item uint64x1x3_t vld3_dup_u64 (const uint64_t *)
687
@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
689
@@ -9130,6 +9320,12 @@
693
+@item void vst3_p64 (poly64_t *, poly64x1x3_t)
694
+@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
699
@item void vst3_u64 (uint64_t *, uint64x1x3_t)
700
@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
702
@@ -9344,6 +9540,12 @@
706
+@item poly64x1x4_t vld4_p64 (const poly64_t *)
707
+@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
712
@item uint64x1x4_t vld4_u64 (const uint64_t *)
713
@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
715
@@ -9554,6 +9756,12 @@
719
+@item poly64x1x4_t vld4_dup_p64 (const poly64_t *)
720
+@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
725
@item uint64x1x4_t vld4_dup_u64 (const uint64_t *)
726
@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
728
@@ -9624,6 +9832,12 @@
732
+@item void vst4_p64 (poly64_t *, poly64x1x4_t)
733
+@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
738
@item void vst4_u64 (uint64_t *, uint64x1x4_t)
739
@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
741
@@ -10274,27 +10488,27 @@
742
@subsubsection Reinterpret casts
745
-@item poly8x8_t vreinterpret_p8_u32 (uint32x2_t)
746
+@item poly8x8_t vreinterpret_p8_p16 (poly16x4_t)
751
-@item poly8x8_t vreinterpret_p8_u16 (uint16x4_t)
752
+@item poly8x8_t vreinterpret_p8_f32 (float32x2_t)
757
-@item poly8x8_t vreinterpret_p8_u8 (uint8x8_t)
758
+@item poly8x8_t vreinterpret_p8_p64 (poly64x1_t)
763
-@item poly8x8_t vreinterpret_p8_s32 (int32x2_t)
764
+@item poly8x8_t vreinterpret_p8_s64 (int64x1_t)
769
-@item poly8x8_t vreinterpret_p8_s16 (int16x4_t)
770
+@item poly8x8_t vreinterpret_p8_u64 (uint64x1_t)
774
@@ -10304,967 +10518,1292 @@
778
-@item poly8x8_t vreinterpret_p8_u64 (uint64x1_t)
779
+@item poly8x8_t vreinterpret_p8_s16 (int16x4_t)
784
-@item poly8x8_t vreinterpret_p8_s64 (int64x1_t)
785
+@item poly8x8_t vreinterpret_p8_s32 (int32x2_t)
790
-@item poly8x8_t vreinterpret_p8_f32 (float32x2_t)
791
+@item poly8x8_t vreinterpret_p8_u8 (uint8x8_t)
796
-@item poly8x8_t vreinterpret_p8_p16 (poly16x4_t)
797
+@item poly8x8_t vreinterpret_p8_u16 (uint16x4_t)
802
-@item poly8x16_t vreinterpretq_p8_u32 (uint32x4_t)
803
+@item poly8x8_t vreinterpret_p8_u32 (uint32x2_t)
808
-@item poly8x16_t vreinterpretq_p8_u16 (uint16x8_t)
809
+@item poly16x4_t vreinterpret_p16_p8 (poly8x8_t)
814
-@item poly8x16_t vreinterpretq_p8_u8 (uint8x16_t)
815
+@item poly16x4_t vreinterpret_p16_f32 (float32x2_t)
820
-@item poly8x16_t vreinterpretq_p8_s32 (int32x4_t)
821
+@item poly16x4_t vreinterpret_p16_p64 (poly64x1_t)
826
-@item poly8x16_t vreinterpretq_p8_s16 (int16x8_t)
827
+@item poly16x4_t vreinterpret_p16_s64 (int64x1_t)
832
-@item poly8x16_t vreinterpretq_p8_s8 (int8x16_t)
833
+@item poly16x4_t vreinterpret_p16_u64 (uint64x1_t)
838
-@item poly8x16_t vreinterpretq_p8_u64 (uint64x2_t)
839
+@item poly16x4_t vreinterpret_p16_s8 (int8x8_t)
844
-@item poly8x16_t vreinterpretq_p8_s64 (int64x2_t)
845
+@item poly16x4_t vreinterpret_p16_s16 (int16x4_t)
850
-@item poly8x16_t vreinterpretq_p8_f32 (float32x4_t)
851
+@item poly16x4_t vreinterpret_p16_s32 (int32x2_t)
856
-@item poly8x16_t vreinterpretq_p8_p16 (poly16x8_t)
857
+@item poly16x4_t vreinterpret_p16_u8 (uint8x8_t)
862
-@item poly16x4_t vreinterpret_p16_u32 (uint32x2_t)
863
+@item poly16x4_t vreinterpret_p16_u16 (uint16x4_t)
868
-@item poly16x4_t vreinterpret_p16_u16 (uint16x4_t)
869
+@item poly16x4_t vreinterpret_p16_u32 (uint32x2_t)
874
-@item poly16x4_t vreinterpret_p16_u8 (uint8x8_t)
875
+@item float32x2_t vreinterpret_f32_p8 (poly8x8_t)
880
-@item poly16x4_t vreinterpret_p16_s32 (int32x2_t)
881
+@item float32x2_t vreinterpret_f32_p16 (poly16x4_t)
886
-@item poly16x4_t vreinterpret_p16_s16 (int16x4_t)
887
+@item float32x2_t vreinterpret_f32_p64 (poly64x1_t)
892
-@item poly16x4_t vreinterpret_p16_s8 (int8x8_t)
893
+@item float32x2_t vreinterpret_f32_s64 (int64x1_t)
898
-@item poly16x4_t vreinterpret_p16_u64 (uint64x1_t)
899
+@item float32x2_t vreinterpret_f32_u64 (uint64x1_t)
904
-@item poly16x4_t vreinterpret_p16_s64 (int64x1_t)
905
+@item float32x2_t vreinterpret_f32_s8 (int8x8_t)
910
-@item poly16x4_t vreinterpret_p16_f32 (float32x2_t)
911
+@item float32x2_t vreinterpret_f32_s16 (int16x4_t)
916
-@item poly16x4_t vreinterpret_p16_p8 (poly8x8_t)
917
+@item float32x2_t vreinterpret_f32_s32 (int32x2_t)
922
-@item poly16x8_t vreinterpretq_p16_u32 (uint32x4_t)
923
+@item float32x2_t vreinterpret_f32_u8 (uint8x8_t)
928
-@item poly16x8_t vreinterpretq_p16_u16 (uint16x8_t)
929
+@item float32x2_t vreinterpret_f32_u16 (uint16x4_t)
934
-@item poly16x8_t vreinterpretq_p16_u8 (uint8x16_t)
935
+@item float32x2_t vreinterpret_f32_u32 (uint32x2_t)
940
-@item poly16x8_t vreinterpretq_p16_s32 (int32x4_t)
941
+@item poly64x1_t vreinterpret_p64_p8 (poly8x8_t)
946
-@item poly16x8_t vreinterpretq_p16_s16 (int16x8_t)
947
+@item poly64x1_t vreinterpret_p64_p16 (poly16x4_t)
952
-@item poly16x8_t vreinterpretq_p16_s8 (int8x16_t)
953
+@item poly64x1_t vreinterpret_p64_f32 (float32x2_t)
958
-@item poly16x8_t vreinterpretq_p16_u64 (uint64x2_t)
959
+@item poly64x1_t vreinterpret_p64_s64 (int64x1_t)
964
-@item poly16x8_t vreinterpretq_p16_s64 (int64x2_t)
965
+@item poly64x1_t vreinterpret_p64_u64 (uint64x1_t)
970
-@item poly16x8_t vreinterpretq_p16_f32 (float32x4_t)
971
+@item poly64x1_t vreinterpret_p64_s8 (int8x8_t)
976
-@item poly16x8_t vreinterpretq_p16_p8 (poly8x16_t)
977
+@item poly64x1_t vreinterpret_p64_s16 (int16x4_t)
982
-@item float32x2_t vreinterpret_f32_u32 (uint32x2_t)
983
+@item poly64x1_t vreinterpret_p64_s32 (int32x2_t)
988
-@item float32x2_t vreinterpret_f32_u16 (uint16x4_t)
989
+@item poly64x1_t vreinterpret_p64_u8 (uint8x8_t)
994
-@item float32x2_t vreinterpret_f32_u8 (uint8x8_t)
995
+@item poly64x1_t vreinterpret_p64_u16 (uint16x4_t)
1000
-@item float32x2_t vreinterpret_f32_s32 (int32x2_t)
1001
+@item poly64x1_t vreinterpret_p64_u32 (uint32x2_t)
1006
-@item float32x2_t vreinterpret_f32_s16 (int16x4_t)
1007
+@item int64x1_t vreinterpret_s64_p8 (poly8x8_t)
1012
-@item float32x2_t vreinterpret_f32_s8 (int8x8_t)
1013
+@item int64x1_t vreinterpret_s64_p16 (poly16x4_t)
1018
-@item float32x2_t vreinterpret_f32_u64 (uint64x1_t)
1019
+@item int64x1_t vreinterpret_s64_f32 (float32x2_t)
1024
-@item float32x2_t vreinterpret_f32_s64 (int64x1_t)
1025
+@item int64x1_t vreinterpret_s64_p64 (poly64x1_t)
1030
-@item float32x2_t vreinterpret_f32_p16 (poly16x4_t)
1031
+@item int64x1_t vreinterpret_s64_u64 (uint64x1_t)
1036
-@item float32x2_t vreinterpret_f32_p8 (poly8x8_t)
1037
+@item int64x1_t vreinterpret_s64_s8 (int8x8_t)
1042
-@item float32x4_t vreinterpretq_f32_u32 (uint32x4_t)
1043
+@item int64x1_t vreinterpret_s64_s16 (int16x4_t)
1048
-@item float32x4_t vreinterpretq_f32_u16 (uint16x8_t)
1049
+@item int64x1_t vreinterpret_s64_s32 (int32x2_t)
1054
-@item float32x4_t vreinterpretq_f32_u8 (uint8x16_t)
1055
+@item int64x1_t vreinterpret_s64_u8 (uint8x8_t)
1060
-@item float32x4_t vreinterpretq_f32_s32 (int32x4_t)
1061
+@item int64x1_t vreinterpret_s64_u16 (uint16x4_t)
1066
-@item float32x4_t vreinterpretq_f32_s16 (int16x8_t)
1067
+@item int64x1_t vreinterpret_s64_u32 (uint32x2_t)
1072
-@item float32x4_t vreinterpretq_f32_s8 (int8x16_t)
1073
+@item uint64x1_t vreinterpret_u64_p8 (poly8x8_t)
1078
-@item float32x4_t vreinterpretq_f32_u64 (uint64x2_t)
1079
+@item uint64x1_t vreinterpret_u64_p16 (poly16x4_t)
1084
-@item float32x4_t vreinterpretq_f32_s64 (int64x2_t)
1085
+@item uint64x1_t vreinterpret_u64_f32 (float32x2_t)
1090
-@item float32x4_t vreinterpretq_f32_p16 (poly16x8_t)
1091
+@item uint64x1_t vreinterpret_u64_p64 (poly64x1_t)
1096
-@item float32x4_t vreinterpretq_f32_p8 (poly8x16_t)
1097
+@item uint64x1_t vreinterpret_u64_s64 (int64x1_t)
1102
-@item int64x1_t vreinterpret_s64_u32 (uint32x2_t)
1103
+@item uint64x1_t vreinterpret_u64_s8 (int8x8_t)
1108
-@item int64x1_t vreinterpret_s64_u16 (uint16x4_t)
1109
+@item uint64x1_t vreinterpret_u64_s16 (int16x4_t)
1114
-@item int64x1_t vreinterpret_s64_u8 (uint8x8_t)
1115
+@item uint64x1_t vreinterpret_u64_s32 (int32x2_t)
1120
-@item int64x1_t vreinterpret_s64_s32 (int32x2_t)
1121
+@item uint64x1_t vreinterpret_u64_u8 (uint8x8_t)
1126
-@item int64x1_t vreinterpret_s64_s16 (int16x4_t)
1127
+@item uint64x1_t vreinterpret_u64_u16 (uint16x4_t)
1132
-@item int64x1_t vreinterpret_s64_s8 (int8x8_t)
1133
+@item uint64x1_t vreinterpret_u64_u32 (uint32x2_t)
1138
-@item int64x1_t vreinterpret_s64_u64 (uint64x1_t)
1139
+@item int8x8_t vreinterpret_s8_p8 (poly8x8_t)
1144
-@item int64x1_t vreinterpret_s64_f32 (float32x2_t)
1145
+@item int8x8_t vreinterpret_s8_p16 (poly16x4_t)
1150
-@item int64x1_t vreinterpret_s64_p16 (poly16x4_t)
1151
+@item int8x8_t vreinterpret_s8_f32 (float32x2_t)
1156
-@item int64x1_t vreinterpret_s64_p8 (poly8x8_t)
1157
+@item int8x8_t vreinterpret_s8_p64 (poly64x1_t)
1162
-@item int64x2_t vreinterpretq_s64_u32 (uint32x4_t)
1163
+@item int8x8_t vreinterpret_s8_s64 (int64x1_t)
1168
-@item int64x2_t vreinterpretq_s64_u16 (uint16x8_t)
1169
+@item int8x8_t vreinterpret_s8_u64 (uint64x1_t)
1174
-@item int64x2_t vreinterpretq_s64_u8 (uint8x16_t)
1175
+@item int8x8_t vreinterpret_s8_s16 (int16x4_t)
1180
-@item int64x2_t vreinterpretq_s64_s32 (int32x4_t)
1181
+@item int8x8_t vreinterpret_s8_s32 (int32x2_t)
1186
-@item int64x2_t vreinterpretq_s64_s16 (int16x8_t)
1187
+@item int8x8_t vreinterpret_s8_u8 (uint8x8_t)
1192
-@item int64x2_t vreinterpretq_s64_s8 (int8x16_t)
1193
+@item int8x8_t vreinterpret_s8_u16 (uint16x4_t)
1198
-@item int64x2_t vreinterpretq_s64_u64 (uint64x2_t)
1199
+@item int8x8_t vreinterpret_s8_u32 (uint32x2_t)
1204
-@item int64x2_t vreinterpretq_s64_f32 (float32x4_t)
1205
+@item int16x4_t vreinterpret_s16_p8 (poly8x8_t)
1210
-@item int64x2_t vreinterpretq_s64_p16 (poly16x8_t)
1211
+@item int16x4_t vreinterpret_s16_p16 (poly16x4_t)
1216
-@item int64x2_t vreinterpretq_s64_p8 (poly8x16_t)
1217
+@item int16x4_t vreinterpret_s16_f32 (float32x2_t)
1222
-@item uint64x1_t vreinterpret_u64_u32 (uint32x2_t)
1223
+@item int16x4_t vreinterpret_s16_p64 (poly64x1_t)
1228
-@item uint64x1_t vreinterpret_u64_u16 (uint16x4_t)
1229
+@item int16x4_t vreinterpret_s16_s64 (int64x1_t)
1234
-@item uint64x1_t vreinterpret_u64_u8 (uint8x8_t)
1235
+@item int16x4_t vreinterpret_s16_u64 (uint64x1_t)
1240
-@item uint64x1_t vreinterpret_u64_s32 (int32x2_t)
1241
+@item int16x4_t vreinterpret_s16_s8 (int8x8_t)
1246
-@item uint64x1_t vreinterpret_u64_s16 (int16x4_t)
1247
+@item int16x4_t vreinterpret_s16_s32 (int32x2_t)
1252
-@item uint64x1_t vreinterpret_u64_s8 (int8x8_t)
1253
+@item int16x4_t vreinterpret_s16_u8 (uint8x8_t)
1258
-@item uint64x1_t vreinterpret_u64_s64 (int64x1_t)
1259
+@item int16x4_t vreinterpret_s16_u16 (uint16x4_t)
1264
-@item uint64x1_t vreinterpret_u64_f32 (float32x2_t)
1265
+@item int16x4_t vreinterpret_s16_u32 (uint32x2_t)
1270
-@item uint64x1_t vreinterpret_u64_p16 (poly16x4_t)
1271
+@item int32x2_t vreinterpret_s32_p8 (poly8x8_t)
1276
-@item uint64x1_t vreinterpret_u64_p8 (poly8x8_t)
1277
+@item int32x2_t vreinterpret_s32_p16 (poly16x4_t)
1282
-@item uint64x2_t vreinterpretq_u64_u32 (uint32x4_t)
1283
+@item int32x2_t vreinterpret_s32_f32 (float32x2_t)
1288
-@item uint64x2_t vreinterpretq_u64_u16 (uint16x8_t)
1289
+@item int32x2_t vreinterpret_s32_p64 (poly64x1_t)
1294
-@item uint64x2_t vreinterpretq_u64_u8 (uint8x16_t)
1295
+@item int32x2_t vreinterpret_s32_s64 (int64x1_t)
1300
-@item uint64x2_t vreinterpretq_u64_s32 (int32x4_t)
1301
+@item int32x2_t vreinterpret_s32_u64 (uint64x1_t)
1306
-@item uint64x2_t vreinterpretq_u64_s16 (int16x8_t)
1307
+@item int32x2_t vreinterpret_s32_s8 (int8x8_t)
1312
-@item uint64x2_t vreinterpretq_u64_s8 (int8x16_t)
1313
+@item int32x2_t vreinterpret_s32_s16 (int16x4_t)
1318
-@item uint64x2_t vreinterpretq_u64_s64 (int64x2_t)
1319
+@item int32x2_t vreinterpret_s32_u8 (uint8x8_t)
1324
-@item uint64x2_t vreinterpretq_u64_f32 (float32x4_t)
1325
+@item int32x2_t vreinterpret_s32_u16 (uint16x4_t)
1330
-@item uint64x2_t vreinterpretq_u64_p16 (poly16x8_t)
1331
+@item int32x2_t vreinterpret_s32_u32 (uint32x2_t)
1336
-@item uint64x2_t vreinterpretq_u64_p8 (poly8x16_t)
1337
+@item uint8x8_t vreinterpret_u8_p8 (poly8x8_t)
1342
-@item int8x8_t vreinterpret_s8_u32 (uint32x2_t)
1343
+@item uint8x8_t vreinterpret_u8_p16 (poly16x4_t)
1348
-@item int8x8_t vreinterpret_s8_u16 (uint16x4_t)
1349
+@item uint8x8_t vreinterpret_u8_f32 (float32x2_t)
1354
-@item int8x8_t vreinterpret_s8_u8 (uint8x8_t)
1355
+@item uint8x8_t vreinterpret_u8_p64 (poly64x1_t)
1360
-@item int8x8_t vreinterpret_s8_s32 (int32x2_t)
1361
+@item uint8x8_t vreinterpret_u8_s64 (int64x1_t)
1366
-@item int8x8_t vreinterpret_s8_s16 (int16x4_t)
1367
+@item uint8x8_t vreinterpret_u8_u64 (uint64x1_t)
1372
-@item int8x8_t vreinterpret_s8_u64 (uint64x1_t)
1373
+@item uint8x8_t vreinterpret_u8_s8 (int8x8_t)
1378
-@item int8x8_t vreinterpret_s8_s64 (int64x1_t)
1379
+@item uint8x8_t vreinterpret_u8_s16 (int16x4_t)
1384
-@item int8x8_t vreinterpret_s8_f32 (float32x2_t)
1385
+@item uint8x8_t vreinterpret_u8_s32 (int32x2_t)
1390
-@item int8x8_t vreinterpret_s8_p16 (poly16x4_t)
1391
+@item uint8x8_t vreinterpret_u8_u16 (uint16x4_t)
1396
-@item int8x8_t vreinterpret_s8_p8 (poly8x8_t)
1397
+@item uint8x8_t vreinterpret_u8_u32 (uint32x2_t)
1402
-@item int8x16_t vreinterpretq_s8_u32 (uint32x4_t)
1403
+@item uint16x4_t vreinterpret_u16_p8 (poly8x8_t)
1408
-@item int8x16_t vreinterpretq_s8_u16 (uint16x8_t)
1409
+@item uint16x4_t vreinterpret_u16_p16 (poly16x4_t)
1414
-@item int8x16_t vreinterpretq_s8_u8 (uint8x16_t)
1415
+@item uint16x4_t vreinterpret_u16_f32 (float32x2_t)
1420
-@item int8x16_t vreinterpretq_s8_s32 (int32x4_t)
1421
+@item uint16x4_t vreinterpret_u16_p64 (poly64x1_t)
1426
-@item int8x16_t vreinterpretq_s8_s16 (int16x8_t)
1427
+@item uint16x4_t vreinterpret_u16_s64 (int64x1_t)
1432
-@item int8x16_t vreinterpretq_s8_u64 (uint64x2_t)
1433
+@item uint16x4_t vreinterpret_u16_u64 (uint64x1_t)
1438
-@item int8x16_t vreinterpretq_s8_s64 (int64x2_t)
1439
+@item uint16x4_t vreinterpret_u16_s8 (int8x8_t)
1444
-@item int8x16_t vreinterpretq_s8_f32 (float32x4_t)
1445
+@item uint16x4_t vreinterpret_u16_s16 (int16x4_t)
1450
-@item int8x16_t vreinterpretq_s8_p16 (poly16x8_t)
1451
+@item uint16x4_t vreinterpret_u16_s32 (int32x2_t)
1456
-@item int8x16_t vreinterpretq_s8_p8 (poly8x16_t)
1457
+@item uint16x4_t vreinterpret_u16_u8 (uint8x8_t)
1462
-@item int16x4_t vreinterpret_s16_u32 (uint32x2_t)
1463
+@item uint16x4_t vreinterpret_u16_u32 (uint32x2_t)
1468
-@item int16x4_t vreinterpret_s16_u16 (uint16x4_t)
1469
+@item uint32x2_t vreinterpret_u32_p8 (poly8x8_t)
1474
-@item int16x4_t vreinterpret_s16_u8 (uint8x8_t)
1475
+@item uint32x2_t vreinterpret_u32_p16 (poly16x4_t)
1480
-@item int16x4_t vreinterpret_s16_s32 (int32x2_t)
1481
+@item uint32x2_t vreinterpret_u32_f32 (float32x2_t)
1486
-@item int16x4_t vreinterpret_s16_s8 (int8x8_t)
1487
+@item uint32x2_t vreinterpret_u32_p64 (poly64x1_t)
1492
-@item int16x4_t vreinterpret_s16_u64 (uint64x1_t)
1493
+@item uint32x2_t vreinterpret_u32_s64 (int64x1_t)
1498
-@item int16x4_t vreinterpret_s16_s64 (int64x1_t)
1499
+@item uint32x2_t vreinterpret_u32_u64 (uint64x1_t)
1504
-@item int16x4_t vreinterpret_s16_f32 (float32x2_t)
1505
+@item uint32x2_t vreinterpret_u32_s8 (int8x8_t)
1510
-@item int16x4_t vreinterpret_s16_p16 (poly16x4_t)
1511
+@item uint32x2_t vreinterpret_u32_s16 (int16x4_t)
1516
-@item int16x4_t vreinterpret_s16_p8 (poly8x8_t)
1517
+@item uint32x2_t vreinterpret_u32_s32 (int32x2_t)
1522
-@item int16x8_t vreinterpretq_s16_u32 (uint32x4_t)
1523
+@item uint32x2_t vreinterpret_u32_u8 (uint8x8_t)
1528
-@item int16x8_t vreinterpretq_s16_u16 (uint16x8_t)
1529
+@item uint32x2_t vreinterpret_u32_u16 (uint16x4_t)
1534
-@item int16x8_t vreinterpretq_s16_u8 (uint8x16_t)
1535
+@item poly8x16_t vreinterpretq_p8_p16 (poly16x8_t)
1540
-@item int16x8_t vreinterpretq_s16_s32 (int32x4_t)
1541
+@item poly8x16_t vreinterpretq_p8_f32 (float32x4_t)
1546
-@item int16x8_t vreinterpretq_s16_s8 (int8x16_t)
1547
+@item poly8x16_t vreinterpretq_p8_p64 (poly64x2_t)
1552
-@item int16x8_t vreinterpretq_s16_u64 (uint64x2_t)
1553
+@item poly8x16_t vreinterpretq_p8_p128 (poly128_t)
1558
-@item int16x8_t vreinterpretq_s16_s64 (int64x2_t)
1559
+@item poly8x16_t vreinterpretq_p8_s64 (int64x2_t)
1564
-@item int16x8_t vreinterpretq_s16_f32 (float32x4_t)
1565
+@item poly8x16_t vreinterpretq_p8_u64 (uint64x2_t)
1570
-@item int16x8_t vreinterpretq_s16_p16 (poly16x8_t)
1571
+@item poly8x16_t vreinterpretq_p8_s8 (int8x16_t)
1576
-@item int16x8_t vreinterpretq_s16_p8 (poly8x16_t)
1577
+@item poly8x16_t vreinterpretq_p8_s16 (int16x8_t)
1582
-@item int32x2_t vreinterpret_s32_u32 (uint32x2_t)
1583
+@item poly8x16_t vreinterpretq_p8_s32 (int32x4_t)
1588
-@item int32x2_t vreinterpret_s32_u16 (uint16x4_t)
1589
+@item poly8x16_t vreinterpretq_p8_u8 (uint8x16_t)
1594
-@item int32x2_t vreinterpret_s32_u8 (uint8x8_t)
1595
+@item poly8x16_t vreinterpretq_p8_u16 (uint16x8_t)
1600
-@item int32x2_t vreinterpret_s32_s16 (int16x4_t)
1601
+@item poly8x16_t vreinterpretq_p8_u32 (uint32x4_t)
1606
-@item int32x2_t vreinterpret_s32_s8 (int8x8_t)
1607
+@item poly16x8_t vreinterpretq_p16_p8 (poly8x16_t)
1612
-@item int32x2_t vreinterpret_s32_u64 (uint64x1_t)
1613
+@item poly16x8_t vreinterpretq_p16_f32 (float32x4_t)
1618
-@item int32x2_t vreinterpret_s32_s64 (int64x1_t)
1619
+@item poly16x8_t vreinterpretq_p16_p64 (poly64x2_t)
1624
-@item int32x2_t vreinterpret_s32_f32 (float32x2_t)
1625
+@item poly16x8_t vreinterpretq_p16_p128 (poly128_t)
1630
-@item int32x2_t vreinterpret_s32_p16 (poly16x4_t)
1631
+@item poly16x8_t vreinterpretq_p16_s64 (int64x2_t)
1636
-@item int32x2_t vreinterpret_s32_p8 (poly8x8_t)
1637
+@item poly16x8_t vreinterpretq_p16_u64 (uint64x2_t)
1642
-@item int32x4_t vreinterpretq_s32_u32 (uint32x4_t)
1643
+@item poly16x8_t vreinterpretq_p16_s8 (int8x16_t)
1648
-@item int32x4_t vreinterpretq_s32_u16 (uint16x8_t)
1649
+@item poly16x8_t vreinterpretq_p16_s16 (int16x8_t)
1654
-@item int32x4_t vreinterpretq_s32_u8 (uint8x16_t)
1655
+@item poly16x8_t vreinterpretq_p16_s32 (int32x4_t)
1660
-@item int32x4_t vreinterpretq_s32_s16 (int16x8_t)
1661
+@item poly16x8_t vreinterpretq_p16_u8 (uint8x16_t)
1666
-@item int32x4_t vreinterpretq_s32_s8 (int8x16_t)
1667
+@item poly16x8_t vreinterpretq_p16_u16 (uint16x8_t)
1672
-@item int32x4_t vreinterpretq_s32_u64 (uint64x2_t)
1673
+@item poly16x8_t vreinterpretq_p16_u32 (uint32x4_t)
1678
-@item int32x4_t vreinterpretq_s32_s64 (int64x2_t)
1679
+@item float32x4_t vreinterpretq_f32_p8 (poly8x16_t)
1684
-@item int32x4_t vreinterpretq_s32_f32 (float32x4_t)
1685
+@item float32x4_t vreinterpretq_f32_p16 (poly16x8_t)
1690
-@item int32x4_t vreinterpretq_s32_p16 (poly16x8_t)
1691
+@item float32x4_t vreinterpretq_f32_p64 (poly64x2_t)
1696
-@item int32x4_t vreinterpretq_s32_p8 (poly8x16_t)
1697
+@item float32x4_t vreinterpretq_f32_p128 (poly128_t)
1702
-@item uint8x8_t vreinterpret_u8_u32 (uint32x2_t)
1703
+@item float32x4_t vreinterpretq_f32_s64 (int64x2_t)
1708
-@item uint8x8_t vreinterpret_u8_u16 (uint16x4_t)
1709
+@item float32x4_t vreinterpretq_f32_u64 (uint64x2_t)
1714
-@item uint8x8_t vreinterpret_u8_s32 (int32x2_t)
1715
+@item float32x4_t vreinterpretq_f32_s8 (int8x16_t)
1720
-@item uint8x8_t vreinterpret_u8_s16 (int16x4_t)
1721
+@item float32x4_t vreinterpretq_f32_s16 (int16x8_t)
1726
-@item uint8x8_t vreinterpret_u8_s8 (int8x8_t)
1727
+@item float32x4_t vreinterpretq_f32_s32 (int32x4_t)
1732
-@item uint8x8_t vreinterpret_u8_u64 (uint64x1_t)
1733
+@item float32x4_t vreinterpretq_f32_u8 (uint8x16_t)
1738
-@item uint8x8_t vreinterpret_u8_s64 (int64x1_t)
1739
+@item float32x4_t vreinterpretq_f32_u16 (uint16x8_t)
1744
-@item uint8x8_t vreinterpret_u8_f32 (float32x2_t)
1745
+@item float32x4_t vreinterpretq_f32_u32 (uint32x4_t)
1750
-@item uint8x8_t vreinterpret_u8_p16 (poly16x4_t)
1751
+@item poly64x2_t vreinterpretq_p64_p8 (poly8x16_t)
1756
-@item uint8x8_t vreinterpret_u8_p8 (poly8x8_t)
1757
+@item poly64x2_t vreinterpretq_p64_p16 (poly16x8_t)
1762
-@item uint8x16_t vreinterpretq_u8_u32 (uint32x4_t)
1763
+@item poly64x2_t vreinterpretq_p64_f32 (float32x4_t)
1768
-@item uint8x16_t vreinterpretq_u8_u16 (uint16x8_t)
1769
+@item poly64x2_t vreinterpretq_p64_p128 (poly128_t)
1774
-@item uint8x16_t vreinterpretq_u8_s32 (int32x4_t)
1775
+@item poly64x2_t vreinterpretq_p64_s64 (int64x2_t)
1780
-@item uint8x16_t vreinterpretq_u8_s16 (int16x8_t)
1781
+@item poly64x2_t vreinterpretq_p64_u64 (uint64x2_t)
1786
-@item uint8x16_t vreinterpretq_u8_s8 (int8x16_t)
1787
+@item poly64x2_t vreinterpretq_p64_s8 (int8x16_t)
1792
-@item uint8x16_t vreinterpretq_u8_u64 (uint64x2_t)
1793
+@item poly64x2_t vreinterpretq_p64_s16 (int16x8_t)
1798
-@item uint8x16_t vreinterpretq_u8_s64 (int64x2_t)
1799
+@item poly64x2_t vreinterpretq_p64_s32 (int32x4_t)
1804
-@item uint8x16_t vreinterpretq_u8_f32 (float32x4_t)
1805
+@item poly64x2_t vreinterpretq_p64_u8 (uint8x16_t)
1810
-@item uint8x16_t vreinterpretq_u8_p16 (poly16x8_t)
1811
+@item poly64x2_t vreinterpretq_p64_u16 (uint16x8_t)
1816
-@item uint8x16_t vreinterpretq_u8_p8 (poly8x16_t)
1817
+@item poly64x2_t vreinterpretq_p64_u32 (uint32x4_t)
1822
-@item uint16x4_t vreinterpret_u16_u32 (uint32x2_t)
1823
+@item poly128_t vreinterpretq_p128_p8 (poly8x16_t)
1828
-@item uint16x4_t vreinterpret_u16_u8 (uint8x8_t)
1829
+@item poly128_t vreinterpretq_p128_p16 (poly16x8_t)
1834
-@item uint16x4_t vreinterpret_u16_s32 (int32x2_t)
1835
+@item poly128_t vreinterpretq_p128_f32 (float32x4_t)
1840
-@item uint16x4_t vreinterpret_u16_s16 (int16x4_t)
1841
+@item poly128_t vreinterpretq_p128_p64 (poly64x2_t)
1846
-@item uint16x4_t vreinterpret_u16_s8 (int8x8_t)
1847
+@item poly128_t vreinterpretq_p128_s64 (int64x2_t)
1852
-@item uint16x4_t vreinterpret_u16_u64 (uint64x1_t)
1853
+@item poly128_t vreinterpretq_p128_u64 (uint64x2_t)
1858
-@item uint16x4_t vreinterpret_u16_s64 (int64x1_t)
1859
+@item poly128_t vreinterpretq_p128_s8 (int8x16_t)
1864
-@item uint16x4_t vreinterpret_u16_f32 (float32x2_t)
1865
+@item poly128_t vreinterpretq_p128_s16 (int16x8_t)
1870
-@item uint16x4_t vreinterpret_u16_p16 (poly16x4_t)
1871
+@item poly128_t vreinterpretq_p128_s32 (int32x4_t)
1876
-@item uint16x4_t vreinterpret_u16_p8 (poly8x8_t)
1877
+@item poly128_t vreinterpretq_p128_u8 (uint8x16_t)
1882
-@item uint16x8_t vreinterpretq_u16_u32 (uint32x4_t)
1883
+@item poly128_t vreinterpretq_p128_u16 (uint16x8_t)
1888
-@item uint16x8_t vreinterpretq_u16_u8 (uint8x16_t)
1889
+@item poly128_t vreinterpretq_p128_u32 (uint32x4_t)
1894
-@item uint16x8_t vreinterpretq_u16_s32 (int32x4_t)
1895
+@item int64x2_t vreinterpretq_s64_p8 (poly8x16_t)
1900
-@item uint16x8_t vreinterpretq_u16_s16 (int16x8_t)
1901
+@item int64x2_t vreinterpretq_s64_p16 (poly16x8_t)
1906
-@item uint16x8_t vreinterpretq_u16_s8 (int8x16_t)
1907
+@item int64x2_t vreinterpretq_s64_f32 (float32x4_t)
1912
-@item uint16x8_t vreinterpretq_u16_u64 (uint64x2_t)
1913
+@item int64x2_t vreinterpretq_s64_p64 (poly64x2_t)
1918
-@item uint16x8_t vreinterpretq_u16_s64 (int64x2_t)
1919
+@item int64x2_t vreinterpretq_s64_p128 (poly128_t)
1924
-@item uint16x8_t vreinterpretq_u16_f32 (float32x4_t)
1925
+@item int64x2_t vreinterpretq_s64_u64 (uint64x2_t)
1930
-@item uint16x8_t vreinterpretq_u16_p16 (poly16x8_t)
1931
+@item int64x2_t vreinterpretq_s64_s8 (int8x16_t)
1936
+@item int64x2_t vreinterpretq_s64_s16 (int16x8_t)
1941
+@item int64x2_t vreinterpretq_s64_s32 (int32x4_t)
1946
+@item int64x2_t vreinterpretq_s64_u8 (uint8x16_t)
1951
+@item int64x2_t vreinterpretq_s64_u16 (uint16x8_t)
1956
+@item int64x2_t vreinterpretq_s64_u32 (uint32x4_t)
1961
+@item uint64x2_t vreinterpretq_u64_p8 (poly8x16_t)
1966
+@item uint64x2_t vreinterpretq_u64_p16 (poly16x8_t)
1971
+@item uint64x2_t vreinterpretq_u64_f32 (float32x4_t)
1976
+@item uint64x2_t vreinterpretq_u64_p64 (poly64x2_t)
1981
+@item uint64x2_t vreinterpretq_u64_p128 (poly128_t)
1986
+@item uint64x2_t vreinterpretq_u64_s64 (int64x2_t)
1991
+@item uint64x2_t vreinterpretq_u64_s8 (int8x16_t)
1996
+@item uint64x2_t vreinterpretq_u64_s16 (int16x8_t)
2001
+@item uint64x2_t vreinterpretq_u64_s32 (int32x4_t)
2006
+@item uint64x2_t vreinterpretq_u64_u8 (uint8x16_t)
2011
+@item uint64x2_t vreinterpretq_u64_u16 (uint16x8_t)
2016
+@item uint64x2_t vreinterpretq_u64_u32 (uint32x4_t)
2021
+@item int8x16_t vreinterpretq_s8_p8 (poly8x16_t)
2026
+@item int8x16_t vreinterpretq_s8_p16 (poly16x8_t)
2031
+@item int8x16_t vreinterpretq_s8_f32 (float32x4_t)
2036
+@item int8x16_t vreinterpretq_s8_p64 (poly64x2_t)
2041
+@item int8x16_t vreinterpretq_s8_p128 (poly128_t)
2046
+@item int8x16_t vreinterpretq_s8_s64 (int64x2_t)
2051
+@item int8x16_t vreinterpretq_s8_u64 (uint64x2_t)
2056
+@item int8x16_t vreinterpretq_s8_s16 (int16x8_t)
2061
+@item int8x16_t vreinterpretq_s8_s32 (int32x4_t)
2066
+@item int8x16_t vreinterpretq_s8_u8 (uint8x16_t)
2071
+@item int8x16_t vreinterpretq_s8_u16 (uint16x8_t)
2076
+@item int8x16_t vreinterpretq_s8_u32 (uint32x4_t)
2081
+@item int16x8_t vreinterpretq_s16_p8 (poly8x16_t)
2086
+@item int16x8_t vreinterpretq_s16_p16 (poly16x8_t)
2091
+@item int16x8_t vreinterpretq_s16_f32 (float32x4_t)
2096
+@item int16x8_t vreinterpretq_s16_p64 (poly64x2_t)
2101
+@item int16x8_t vreinterpretq_s16_p128 (poly128_t)
2106
+@item int16x8_t vreinterpretq_s16_s64 (int64x2_t)
2111
+@item int16x8_t vreinterpretq_s16_u64 (uint64x2_t)
2116
+@item int16x8_t vreinterpretq_s16_s8 (int8x16_t)
2121
+@item int16x8_t vreinterpretq_s16_s32 (int32x4_t)
2126
+@item int16x8_t vreinterpretq_s16_u8 (uint8x16_t)
2131
+@item int16x8_t vreinterpretq_s16_u16 (uint16x8_t)
2136
+@item int16x8_t vreinterpretq_s16_u32 (uint32x4_t)
2141
+@item int32x4_t vreinterpretq_s32_p8 (poly8x16_t)
2146
+@item int32x4_t vreinterpretq_s32_p16 (poly16x8_t)
2151
+@item int32x4_t vreinterpretq_s32_f32 (float32x4_t)
2156
+@item int32x4_t vreinterpretq_s32_p64 (poly64x2_t)
2161
+@item int32x4_t vreinterpretq_s32_p128 (poly128_t)
2166
+@item int32x4_t vreinterpretq_s32_s64 (int64x2_t)
2171
+@item int32x4_t vreinterpretq_s32_u64 (uint64x2_t)
2176
+@item int32x4_t vreinterpretq_s32_s8 (int8x16_t)
2181
+@item int32x4_t vreinterpretq_s32_s16 (int16x8_t)
2186
+@item int32x4_t vreinterpretq_s32_u8 (uint8x16_t)
2191
+@item int32x4_t vreinterpretq_s32_u16 (uint16x8_t)
2196
+@item int32x4_t vreinterpretq_s32_u32 (uint32x4_t)
2201
+@item uint8x16_t vreinterpretq_u8_p8 (poly8x16_t)
2206
+@item uint8x16_t vreinterpretq_u8_p16 (poly16x8_t)
2211
+@item uint8x16_t vreinterpretq_u8_f32 (float32x4_t)
2216
+@item uint8x16_t vreinterpretq_u8_p64 (poly64x2_t)
2221
+@item uint8x16_t vreinterpretq_u8_p128 (poly128_t)
2226
+@item uint8x16_t vreinterpretq_u8_s64 (int64x2_t)
2231
+@item uint8x16_t vreinterpretq_u8_u64 (uint64x2_t)
2236
+@item uint8x16_t vreinterpretq_u8_s8 (int8x16_t)
2241
+@item uint8x16_t vreinterpretq_u8_s16 (int16x8_t)
2246
+@item uint8x16_t vreinterpretq_u8_s32 (int32x4_t)
2251
+@item uint8x16_t vreinterpretq_u8_u16 (uint16x8_t)
2256
+@item uint8x16_t vreinterpretq_u8_u32 (uint32x4_t)
2260
@@ -11274,82 +11813,82 @@
2264
-@item uint32x2_t vreinterpret_u32_u16 (uint16x4_t)
2265
+@item uint16x8_t vreinterpretq_u16_p16 (poly16x8_t)
2270
-@item uint32x2_t vreinterpret_u32_u8 (uint8x8_t)
2271
+@item uint16x8_t vreinterpretq_u16_f32 (float32x4_t)
2276
-@item uint32x2_t vreinterpret_u32_s32 (int32x2_t)
2277
+@item uint16x8_t vreinterpretq_u16_p64 (poly64x2_t)
2282
-@item uint32x2_t vreinterpret_u32_s16 (int16x4_t)
2283
+@item uint16x8_t vreinterpretq_u16_p128 (poly128_t)
2288
-@item uint32x2_t vreinterpret_u32_s8 (int8x8_t)
2289
+@item uint16x8_t vreinterpretq_u16_s64 (int64x2_t)
2294
-@item uint32x2_t vreinterpret_u32_u64 (uint64x1_t)
2295
+@item uint16x8_t vreinterpretq_u16_u64 (uint64x2_t)
2300
-@item uint32x2_t vreinterpret_u32_s64 (int64x1_t)
2301
+@item uint16x8_t vreinterpretq_u16_s8 (int8x16_t)
2306
-@item uint32x2_t vreinterpret_u32_f32 (float32x2_t)
2307
+@item uint16x8_t vreinterpretq_u16_s16 (int16x8_t)
2312
-@item uint32x2_t vreinterpret_u32_p16 (poly16x4_t)
2313
+@item uint16x8_t vreinterpretq_u16_s32 (int32x4_t)
2318
-@item uint32x2_t vreinterpret_u32_p8 (poly8x8_t)
2319
+@item uint16x8_t vreinterpretq_u16_u8 (uint8x16_t)
2324
-@item uint32x4_t vreinterpretq_u32_u16 (uint16x8_t)
2325
+@item uint16x8_t vreinterpretq_u16_u32 (uint32x4_t)
2330
-@item uint32x4_t vreinterpretq_u32_u8 (uint8x16_t)
2331
+@item uint32x4_t vreinterpretq_u32_p8 (poly8x16_t)
2336
-@item uint32x4_t vreinterpretq_u32_s32 (int32x4_t)
2337
+@item uint32x4_t vreinterpretq_u32_p16 (poly16x8_t)
2342
-@item uint32x4_t vreinterpretq_u32_s16 (int16x8_t)
2343
+@item uint32x4_t vreinterpretq_u32_f32 (float32x4_t)
2348
-@item uint32x4_t vreinterpretq_u32_s8 (int8x16_t)
2349
+@item uint32x4_t vreinterpretq_u32_p64 (poly64x2_t)
2354
-@item uint32x4_t vreinterpretq_u32_u64 (uint64x2_t)
2355
+@item uint32x4_t vreinterpretq_u32_p128 (poly128_t)
2359
@@ -11359,19 +11898,111 @@
2363
-@item uint32x4_t vreinterpretq_u32_f32 (float32x4_t)
2364
+@item uint32x4_t vreinterpretq_u32_u64 (uint64x2_t)
2369
-@item uint32x4_t vreinterpretq_u32_p16 (poly16x8_t)
2370
+@item uint32x4_t vreinterpretq_u32_s8 (int8x16_t)
2375
-@item uint32x4_t vreinterpretq_u32_p8 (poly8x16_t)
2376
+@item uint32x4_t vreinterpretq_u32_s16 (int16x8_t)
2381
+@item uint32x4_t vreinterpretq_u32_s32 (int32x4_t)
2386
+@item uint32x4_t vreinterpretq_u32_u8 (uint8x16_t)
2391
+@item uint32x4_t vreinterpretq_u32_u16 (uint16x8_t)
2399
+@item poly128_t vldrq_p128(poly128_t const *)
2403
+@item void vstrq_p128(poly128_t *, poly128_t)
2407
+@item uint64x1_t vceq_p64 (poly64x1_t, poly64x1_t)
2411
+@item uint64x1_t vtst_p64 (poly64x1_t, poly64x1_t)
2415
+@item uint32_t vsha1h_u32 (uint32_t)
2416
+@*@emph{Form of expected instruction(s):} @code{sha1h.32 @var{q0}, @var{q1}}
2420
+@item uint32x4_t vsha1cq_u32 (uint32x4_t, uint32_t, uint32x4_t)
2421
+@*@emph{Form of expected instruction(s):} @code{sha1c.32 @var{q0}, @var{q1}, @var{q2}}
2425
+@item uint32x4_t vsha1pq_u32 (uint32x4_t, uint32_t, uint32x4_t)
2426
+@*@emph{Form of expected instruction(s):} @code{sha1p.32 @var{q0}, @var{q1}, @var{q2}}
2430
+@item uint32x4_t vsha1mq_u32 (uint32x4_t, uint32_t, uint32x4_t)
2431
+@*@emph{Form of expected instruction(s):} @code{sha1m.32 @var{q0}, @var{q1}, @var{q2}}
2435
+@item uint32x4_t vsha1su0q_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
2436
+@*@emph{Form of expected instruction(s):} @code{sha1su0.32 @var{q0}, @var{q1}, @var{q2}}
2440
+@item uint32x4_t vsha1su1q_u32 (uint32x4_t, uint32x4_t)
2441
+@*@emph{Form of expected instruction(s):} @code{sha1su1.32 @var{q0}, @var{q1}, @var{q2}}
2445
+@item uint32x4_t vsha256hq_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
2446
+@*@emph{Form of expected instruction(s):} @code{sha256h.32 @var{q0}, @var{q1}, @var{q2}}
2450
+@item uint32x4_t vsha256h2q_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
2451
+@*@emph{Form of expected instruction(s):} @code{sha256h2.32 @var{q0}, @var{q1}, @var{q2}}
2455
+@item uint32x4_t vsha256su0q_u32 (uint32x4_t, uint32x4_t)
2456
+@*@emph{Form of expected instruction(s):} @code{sha256su0.32 @var{q0}, @var{q1}}
2460
+@item uint32x4_t vsha256su1q_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
2461
+@*@emph{Form of expected instruction(s):} @code{sha256su1.32 @var{q0}, @var{q1}, @var{q2}}
2465
+@item poly128_t vmull_p64 (poly64_t a, poly64_t b)
2466
+@*@emph{Form of expected instruction(s):} @code{vmull.p64 @var{q0}, @var{d1}, @var{d2}}
2470
+@item poly128_t vmull_high_p64 (poly64x2_t a, poly64x2_t b)
2471
+@*@emph{Form of expected instruction(s):} @code{vmull.p64 @var{q0}, @var{d1}, @var{d2}}
2474
Index: b/src/gcc/doc/md.texi
2475
===================================================================
2476
--- a/src/gcc/doc/md.texi
2477
+++ b/src/gcc/doc/md.texi
2478
@@ -1711,9 +1711,6 @@
2480
Integer constant zero
2483
-An absolute symbolic address
2486
The high part (bits 12 and upwards) of the pc-relative address of a symbol
2487
within 4GB of the instruction
2488
@@ -8828,7 +8825,8 @@
2490
[@var{predicate-pattern}]
2492
- "@var{output-template}")
2493
+ "@var{output-template}"
2494
+ "@var{optional-insn-attribues}")
2497
@var{predicate-pattern} is the condition that must be true for the
2498
@@ -8849,6 +8847,13 @@
2499
@code{current_insn_predicate} that will contain the entire predicate
2500
if the current insn is predicated, and will otherwise be @code{NULL}.
2502
+@var{optional-insn-attributes} is an optional vector of attributes that gets
2503
+appended to the insn attributes of the produced cond_exec rtx. It can
2504
+be used to add some distinguishing attribute to cond_exec rtxs produced
2505
+that way. An example usage would be to use this attribute in conjunction
2506
+with attributes on the main pattern to disable particular alternatives under
2507
+certain conditions.
2509
When @code{define_cond_exec} is used, an implicit reference to
2510
the @code{predicable} instruction attribute is made.
2511
@xref{Insn Attributes}. This attribute must be a boolean (i.e.@: have
added
removed
.svn/pristine/8f/8fa0ce7fb69fd341a9d32e5c2acd446672f78d95.svn-base
