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# DP: Changes for the Linaro 4.8-2013.12 release (documentation).
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--- a/src/gcc/doc/tm.texi
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+++ b/src/gcc/doc/tm.texi
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@@ -10926,10 +10926,18 @@
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@samp{TARGET_INIT_BUILTINS}. @var{fndecl} is the declaration of the
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built-in function. @var{n_args} is the number of arguments passed to
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the function; the arguments themselves are pointed to by @var{argp}.
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-The result is another tree containing a simplified expression for the
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-call's result. If @var{ignore} is true the value will be ignored.
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+The result is another tree, valid for both GIMPLE and GENERIC,
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+containing a simplified expression for the call's result. If
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+@var{ignore} is true the value will be ignored.
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+@deftypefn {Target Hook} bool TARGET_GIMPLE_FOLD_BUILTIN (gimple_stmt_iterator *@var{gsi})
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+Fold a call to a machine specific built-in function that was set up
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+by @samp{TARGET_INIT_BUILTINS}. @var{gsi} points to the gimple
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+statement holding the function call. Returns true if any change
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+was made to the GIMPLE stream.
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@deftypefn {Target Hook} int TARGET_COMPARE_VERSION_PRIORITY (tree @var{decl1}, tree @var{decl2})
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This hook is used to compare the target attributes in two functions to
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determine which function's features get higher priority. This is used
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--- a/src/gcc/doc/tm.texi.in
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+++ b/src/gcc/doc/tm.texi.in
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@@ -10772,10 +10772,13 @@
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@samp{TARGET_INIT_BUILTINS}. @var{fndecl} is the declaration of the
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built-in function. @var{n_args} is the number of arguments passed to
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the function; the arguments themselves are pointed to by @var{argp}.
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-The result is another tree containing a simplified expression for the
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-call's result. If @var{ignore} is true the value will be ignored.
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+The result is another tree, valid for both GIMPLE and GENERIC,
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+containing a simplified expression for the call's result. If
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+@var{ignore} is true the value will be ignored.
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+@hook TARGET_GIMPLE_FOLD_BUILTIN
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@hook TARGET_COMPARE_VERSION_PRIORITY
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This hook is used to compare the target attributes in two functions to
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determine which function's features get higher priority. This is used
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--- a/src/gcc/doc/invoke.texi
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+++ b/src/gcc/doc/invoke.texi
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-mtp=@var{name} -mtls-dialect=@var{dialect} @gol
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-mword-relocations @gol
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-mfix-cortex-m3-ldrd @gol
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+-munaligned-access @gol
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+-mneon-for-64bits @gol
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@gccoptlist{-mmcu=@var{mcu} -maccumulate-args -mbranch-cost=@var{cost} @gol
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@@ -10966,6 +10968,8 @@
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+Enable CRC extension.
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Enable Crypto extension. This implies Advanced SIMD is enabled.
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@@ -11263,8 +11267,8 @@
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@samp{arm1136j-s}, @samp{arm1136jf-s}, @samp{mpcore}, @samp{mpcorenovfp},
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@samp{arm1156t2-s}, @samp{arm1156t2f-s}, @samp{arm1176jz-s}, @samp{arm1176jzf-s},
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@samp{cortex-a5}, @samp{cortex-a7}, @samp{cortex-a8}, @samp{cortex-a9},
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-@samp{cortex-a15}, @samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-r5},
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-@samp{cortex-m4}, @samp{cortex-m3},
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+@samp{cortex-a15}, @samp{cortex-a53}, @samp{cortex-r4}, @samp{cortex-r4f},
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+@samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-m4}, @samp{cortex-m3},
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@@ -11530,6 +11534,17 @@
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preprocessor symbol @code{__ARM_FEATURE_UNALIGNED} will also be
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+@item -mneon-for-64bits
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+@opindex mneon-for-64bits
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+Enables using Neon to handle scalar 64-bits operations. This is
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+disabled by default since the cost of moving data from core registers
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+@opindex mrestrict-it
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+Restricts generation of IT blocks to conform to the rules of ARMv8.
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+IT blocks can only contain a single 16-bit instruction from a select
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+set of instructions. This option is on by default for ARMv8 Thumb mode.
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--- a/src/gcc/doc/arm-neon-intrinsics.texi
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+++ b/src/gcc/doc/arm-neon-intrinsics.texi
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@@ -5748,6 +5748,18 @@
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+@item float16x4_t vcvt_f16_f32 (float32x4_t)
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+@*@emph{Form of expected instruction(s):} @code{vcvt.f16.f32 @var{d0}, @var{q0}}
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+@item float32x4_t vcvt_f32_f16 (float16x4_t)
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+@*@emph{Form of expected instruction(s):} @code{vcvt.f32.f16 @var{q0}, @var{d0}}
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@item float32x2_t vcvt_n_f32_u32 (uint32x2_t, const int)
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@*@emph{Form of expected instruction(s):} @code{vcvt.f32.u32 @var{d0}, @var{d0}, #@var{0}}
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--- a/src/gcc/doc/md.texi
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+++ b/src/gcc/doc/md.texi
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@@ -1711,9 +1711,6 @@
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Integer constant zero
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-An absolute symbolic address
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The high part (bits 12 and upwards) of the pc-relative address of a symbol
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within 4GB of the instruction
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@@ -8828,7 +8825,8 @@
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[@var{predicate-pattern}]
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- "@var{output-template}")
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+ "@var{output-template}"
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+ "@var{optional-insn-attribues}")
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@var{predicate-pattern} is the condition that must be true for the
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@@ -8849,6 +8847,13 @@
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@code{current_insn_predicate} that will contain the entire predicate
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if the current insn is predicated, and will otherwise be @code{NULL}.
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+@var{optional-insn-attributes} is an optional vector of attributes that gets
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+appended to the insn attributes of the produced cond_exec rtx. It can
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+be used to add some distinguishing attribute to cond_exec rtxs produced
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+that way. An example usage would be to use this attribute in conjunction
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+with attributes on the main pattern to disable particular alternatives under
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When @code{define_cond_exec} is used, an implicit reference to
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the @code{predicable} instruction attribute is made.
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@xref{Insn Attributes}. This attribute must be a boolean (i.e.@: have