~ubuntu-branches/debian/sid/gcc-4.8/sid : revision 78

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# DP: updates from the 4.8 branch upto 20140508 (r210209).

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last_updated()

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{

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cat > ${dir}LAST_UPDATED <<EOF

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Thu May 8 13:38:43 CEST 2014

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Thu May 8 11:38:43 UTC 2014 (revision 210209)

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EOF

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}

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LANG=C svn diff svn://gcc.gnu.org/svn/gcc/tags/gcc_4_8_2_release svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch \

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| sed -r 's,^--- (\S+)\t(\S+)(.*)$,--- a/src/\1\t\2,;s,^\+\+\+ (\S+)\t(\S+)(.*)$,+++ b/src/\1\t\2,' \

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| awk '/^Index:.*\.(class|texi)/ {skip=1; next} /^Index:/ { skip=0 } skip==0'

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Index: libitm/configure

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===================================================================

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--- a/src/libitm/configure (.../tags/gcc_4_8_2_release)

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+++ b/src/libitm/configure (.../branches/gcc-4_8-branch)

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@@ -7270,7 +7270,7 @@

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rm -rf conftest*

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;;

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-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \

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+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \

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s390*-*linux*|s390*-*tpf*|sparc*-*linux*)

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# Find out which ABI we are using.

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echo 'int i;' > conftest.$ac_ext

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@@ -7295,7 +7295,10 @@

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;;

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esac

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;;

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- ppc64-*linux*|powerpc64-*linux*)

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+ powerpc64le-*linux*)

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+ LD="${LD-ld} -m elf32lppclinux"

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+ ;;

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+ powerpc64-*linux*)

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LD="${LD-ld} -m elf32ppclinux"

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;;

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s390x-*linux*)

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@@ -7314,7 +7317,10 @@

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x86_64-*linux*)

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LD="${LD-ld} -m elf_x86_64"

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;;

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- ppc*-*linux*|powerpc*-*linux*)

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+ powerpcle-*linux*)

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+ LD="${LD-ld} -m elf64lppc"

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+ ;;

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+ powerpc-*linux*)

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LD="${LD-ld} -m elf64ppc"

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;;

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s390*-*linux*|s390*-*tpf*)

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@@ -11779,7 +11785,7 @@

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lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

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lt_status=$lt_dlunknown

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cat > conftest.$ac_ext <<_LT_EOF

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-#line 11782 "configure"

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+#line 11788 "configure"

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#include "confdefs.h"

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#if HAVE_DLFCN_H

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@@ -11885,7 +11891,7 @@

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lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

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lt_status=$lt_dlunknown

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cat > conftest.$ac_ext <<_LT_EOF

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-#line 11888 "configure"

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+#line 11894 "configure"

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#include "confdefs.h"

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#if HAVE_DLFCN_H

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@@ -17362,6 +17368,43 @@

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fi

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;;

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+esac

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+

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+case "${target_cpu}" in

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+powerpc*)

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+ { $as_echo "$as_me:${as_lineno-$LINENO}: checking if the assembler supports HTM" >&5

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+$as_echo_n "checking if the assembler supports HTM... " >&6; }

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+if test "${libitm_cv_as_htm+set}" = set; then :

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+ $as_echo_n "(cached) " >&6

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+else

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+

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+ cat confdefs.h - <<_ACEOF >conftest.$ac_ext

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+/* end confdefs.h. */

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+

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+int

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+main ()

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+{

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+asm("tbegin. 0; tend. 0");

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+ ;

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+ return 0;

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+}

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+_ACEOF

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+if ac_fn_c_try_compile "$LINENO"; then :

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+ libitm_cv_as_htm=yes

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+else

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+ libitm_cv_as_htm=no

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+fi

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+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext

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+

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+fi

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+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $libitm_cv_as_htm" >&5

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+$as_echo "$libitm_cv_as_htm" >&6; }

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+ if test x$libitm_cv_as_htm = xyes; then

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+

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+$as_echo "#define HAVE_AS_HTM 1" >>confdefs.h

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+

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+ fi

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+ ;;

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s390*)

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{ $as_echo "$as_me:${as_lineno-$LINENO}: checking if the assembler supports HTM" >&5

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$as_echo_n "checking if the assembler supports HTM... " >&6; }

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@@ -17399,7 +17442,6 @@

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fi

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;;

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esac

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-LIBITM_CHECK_AS_HTM

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{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether weak refs work like ELF" >&5

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Index: libitm/configure.tgt

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===================================================================

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--- a/src/libitm/configure.tgt (.../tags/gcc_4_8_2_release)

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+++ b/src/libitm/configure.tgt (.../branches/gcc-4_8-branch)

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@@ -47,7 +47,10 @@

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# work out any special compilation flags as necessary.

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case "${target_cpu}" in

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alpha*) ARCH=alpha ;;

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- rs6000 | powerpc*) ARCH=powerpc ;;

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+ rs6000 | powerpc*)

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+ XCFLAGS="${XCFLAGS} -mhtm"

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+ ARCH=powerpc

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+ ;;

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arm*) ARCH=arm ;;

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138

Index: libitm/ChangeLog

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===================================================================

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--- a/src/libitm/ChangeLog (.../tags/gcc_4_8_2_release)

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+++ b/src/libitm/ChangeLog (.../branches/gcc-4_8-branch)

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@@ -1,3 +1,62 @@

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+2014-04-14 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>

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+

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+ * acinclude.m4: Move s390* case from RTM to HTM check.

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+ * configure: Regenerate.

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+

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+2014-04-09 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>

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+

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+ * config/generic/asmcfi.h: Also check for

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+ __GCC_HAVE_DWARF2_CFI_ASM.

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+

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+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

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+

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+ Backport from mainline r204808:

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+

157

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

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+

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+ * config/powerpc/sjlj.S [__powerpc64__ && _CALL_ELF == 2]:

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+ (FUNC): Define ELFv2 variant.

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+ (END): Likewise.

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+ (HIDDEN): Likewise.

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+ (CALL): Likewise.

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+ (BASE): Likewise.

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+ (LR_SAVE): Likewise.

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+

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+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

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+

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+ Power8 HTM Support

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+ Backport from mainline

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+ * acinclude.m4 (LIBITM_CHECK_AS_HTM): New.

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+ * configure: Rebuild.

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+ * configure.tgt (target_cpu): Add -mhtm to XCFLAGS.

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+ * config/powerpc/target.h: Include sys/auxv.h and htmintrin.h.

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+ (USE_HTM_FASTPATH): Define.

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+ (_TBEGIN_STARTED, _TBEGIN_INDETERMINATE, _TBEGIN_PERSISTENT)

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+ (_HTM_RETRIES) New macros.

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+ (htm_abort, htm_abort_should_retry, htm_available, htm_begin, htm_init)

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+ (htm_begin_success, htm_commit, htm_transaction_active): New functions.

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+

181

+2014-03-26 Jakub Jelinek <jakub@redhat.com>

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+

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+ * config/linux/futex_bits.h: Include errno.h.

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+ (sys_futex0): If syscall returns -1, return -errno rather than

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+ -1.

186

+

187

+2014-03-03 Peter Bergner <bergner@vnet.ibm.com>

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+

189

+ Backport from mainline

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+ 2013-06-20 Torvald Riegel <triegel@redhat.com>

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+

192

+ * query.cc (_ITM_inTransaction): Abort when using the HTM fastpath.

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+ (_ITM_getTransactionId): Same.

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+ * config/x86/target.h (htm_transaction_active): New.

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+

196

+ 2013-06-20 Torvald Riegel <triegel@redhat.com>

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+

198

+ PR libitm/57643

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+ * beginend.cc (gtm_thread::begin_transaction): Handle reentrancy in

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+ the HTM fastpath.

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+

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2013-10-16 Release Manager

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204

* GCC 4.8.2 released.

205

@@ -8,13 +67,12 @@

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2013-08-02 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>

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208

* configure.tgt: Add -msoft-float to XCFLAGS.

209

-

210

211

2013-08-14 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>

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213

* config/s390/sjlj.S: Add file missing from last commit.

214

* config/s390/target.h: Likewise.

215

-

216

+

217

2013-08-02 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>

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219

Backports from mainline:

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Index: libitm/query.cc

221

===================================================================

222

--- a/src/libitm/query.cc (.../tags/gcc_4_8_2_release)

223

+++ b/src/libitm/query.cc (.../branches/gcc-4_8-branch)

224

@@ -43,6 +43,15 @@

225

_ITM_howExecuting ITM_REGPARM

226

_ITM_inTransaction (void)

227

{

228

+#if defined(USE_HTM_FASTPATH)

229

+ // If we use the HTM fastpath, we cannot reliably detect whether we are

230

+ // in a transaction because this function can be called outside of

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+ // a transaction and thus we can't deduce this by looking at just the serial

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+ // lock. This function isn't used in practice currently, so the easiest

233

+ // way to handle it is to just abort.

234

+ if (htm_fastpath && htm_transaction_active())

235

+ htm_abort();

236

+#endif

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struct gtm_thread *tx = gtm_thr();

238

if (tx && (tx->nesting > 0))

239

{

240

@@ -58,6 +67,11 @@

241

_ITM_transactionId_t ITM_REGPARM

242

_ITM_getTransactionId (void)

243

{

244

+#if defined(USE_HTM_FASTPATH)

245

+ // See ITM_inTransaction.

246

+ if (htm_fastpath && htm_transaction_active())

247

+ htm_abort();

248

+#endif

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struct gtm_thread *tx = gtm_thr();

250

return (tx && (tx->nesting > 0)) ? tx->id : _ITM_noTransactionId;

251

}

252

Index: libitm/beginend.cc

253

===================================================================

254

--- a/src/libitm/beginend.cc (.../tags/gcc_4_8_2_release)

255

+++ b/src/libitm/beginend.cc (.../branches/gcc-4_8-branch)

256

@@ -197,6 +197,8 @@

257

// We are executing a transaction now.

258

// Monitor the writer flag in the serial-mode lock, and abort

259

// if there is an active or waiting serial-mode transaction.

260

+ // Note that this can also happen due to an enclosing

261

+ // serial-mode transaction; we handle this case below.

262

if (unlikely(serial_lock.is_write_locked()))

263

htm_abort();

264

else

265

@@ -219,6 +221,14 @@

266

tx = new gtm_thread();

267

set_gtm_thr(tx);

268

}

269

+ // Check whether there is an enclosing serial-mode transaction;

270

+ // if so, we just continue as a nested transaction and don't

271

+ // try to use the HTM fastpath. This case can happen when an

272

+ // outermost relaxed transaction calls unsafe code that starts

273

+ // a transaction.

274

+ if (tx->nesting > 0)

275

+ break;

276

+ // Another thread is running a serial-mode transaction. Wait.

277

serial_lock.read_lock(tx);

278

serial_lock.read_unlock(tx);

279

// TODO We should probably reset the retry count t here, unless

280

Index: libitm/config/linux/futex_bits.h

281

===================================================================

282

--- a/src/libitm/config/linux/futex_bits.h (.../tags/gcc_4_8_2_release)

283

+++ b/src/libitm/config/linux/futex_bits.h (.../branches/gcc-4_8-branch)

284

@@ -31,9 +31,13 @@

285

286

#include <unistd.h>

287

#include <sys/syscall.h>

288

+#include <errno.h>

289

290

static inline long

291

sys_futex0 (std::atomic<int> *addr, long op, long val)

292

{

293

- return syscall (SYS_futex, (int*) addr, op, val, 0);

294

+ long res = syscall (SYS_futex, (int*) addr, op, val, 0);

295

+ if (__builtin_expect (res == -1, 0))

296

+ return -errno;

297

+ return res;

298

}

299

Index: libitm/config/powerpc/sjlj.S

300

===================================================================

301

--- a/src/libitm/config/powerpc/sjlj.S (.../tags/gcc_4_8_2_release)

302

+++ b/src/libitm/config/powerpc/sjlj.S (.../branches/gcc-4_8-branch)

303

@@ -26,8 +26,27 @@

304

305

#include "asmcfi.h"

306

307

-#if defined(__powerpc64__) && defined(__ELF__)

308

+#if defined(__powerpc64__) && _CALL_ELF == 2

309

.macro FUNC name

310

+ .globl \name

311

+ .type \name, @function

312

+\name:

313

+0: addis 2,12,(.TOC.-0b)@ha

314

+ addi 2,2,(.TOC.-0b)@l

315

+ .localentry \name, . - \name

316

+.endm

317

+.macro END name

318

+ .size \name, . - \name

319

+.endm

320

+.macro HIDDEN name

321

+ .hidden \name

322

+.endm

323

+.macro CALL name

324

+ bl \name

325

+ nop

326

+.endm

327

+#elif defined(__powerpc64__) && defined(__ELF__)

328

+.macro FUNC name

329

.globl \name, .\name

330

.section ".opd","aw"

331

.align 3

332

@@ -117,6 +136,9 @@

333

#if defined(_CALL_AIXDESC)

334

# define BASE 6*WS

335

# define LR_SAVE 2*WS

336

+#elif _CALL_ELF == 2

337

+# define BASE 6*WS

338

+# define LR_SAVE 2*WS

339

#elif defined(_CALL_SYSV)

340

# define BASE 2*WS

341

# define LR_SAVE 1*WS

342

Index: libitm/config/powerpc/target.h

343

===================================================================

344

--- a/src/libitm/config/powerpc/target.h (.../tags/gcc_4_8_2_release)

345

+++ b/src/libitm/config/powerpc/target.h (.../branches/gcc-4_8-branch)

346

@@ -22,6 +22,10 @@

347

see the files COPYING3 and COPYING.RUNTIME respectively. If not, see

348

<http://www.gnu.org/licenses/>. */

349

350

+#ifdef HAVE_SYS_AUXV_H

351

+#include <sys/auxv.h>

352

+#endif

353

+

354

namespace GTM HIDDEN {

355

356

typedef int v128 __attribute__((vector_size(16), may_alias, aligned(16)));

357

@@ -55,4 +59,82 @@

358

__asm volatile ("" : : : "memory");

359

}

360

361

+// Use HTM if it is supported by the system.

362

+// See gtm_thread::begin_transaction for how these functions are used.

363

+#if defined (__linux__) \

364

+ && defined (HAVE_AS_HTM) \

365

+ && defined (HAVE_GETAUXVAL) \

366

+ && defined (AT_HWCAP2) \

367

+ && defined (PPC_FEATURE2_HAS_HTM)

368

+

369

+#include <htmintrin.h>

370

+

371

+#define USE_HTM_FASTPATH

372

+

373

+#define _TBEGIN_STARTED 0

374

+#define _TBEGIN_INDETERMINATE 1

375

+#define _TBEGIN_PERSISTENT 2

376

+

377

+/* Number of retries for transient failures. */

378

+#define _HTM_RETRIES 10

379

+

380

+static inline bool

381

+htm_available (void)

382

+{

383

+ return (getauxval (AT_HWCAP2) & PPC_FEATURE2_HAS_HTM) ? true : false;

384

+}

385

+

386

+static inline uint32_t

387

+htm_init (void)

388

+{

389

+ // Maximum number of times we try to execute a transaction

390

+ // as a HW transaction.

391

+ return htm_available () ? _HTM_RETRIES : 0;

392

+}

393

+

394

+static inline uint32_t

395

+htm_begin (void)

396

+{

397

+ if (__builtin_expect (__builtin_tbegin (0), 1))

398

+ return _TBEGIN_STARTED;

399

+

400

+ if (_TEXASRU_FAILURE_PERSISTENT (__builtin_get_texasru ()))

401

+ return _TBEGIN_PERSISTENT;

402

+

403

+ return _TBEGIN_INDETERMINATE;

404

+}

405

+

406

+static inline bool

407

+htm_begin_success (uint32_t begin_ret)

408

+{

409

+ return begin_ret == _TBEGIN_STARTED;

410

+}

411

+

412

+static inline void

413

+htm_commit (void)

414

+{

415

+ __builtin_tend (0);

416

+}

417

+

418

+static inline void

419

+htm_abort (void)

420

+{

421

+ __builtin_tabort (0);

422

+}

423

+

424

+static inline bool

425

+htm_abort_should_retry (uint32_t begin_ret)

426

+{

427

+ return begin_ret != _TBEGIN_PERSISTENT;

428

+}

429

+

430

+/* Returns true iff a hardware transaction is currently being executed. */

431

+static inline bool

432

+htm_transaction_active (void)

433

+{

434

+ return (_HTM_STATE (__builtin_ttest ()) == _HTM_TRANSACTIONAL);

435

+}

436

+

437

+#endif

438

+

439

} // namespace GTM

440

Index: libitm/config/x86/target.h

441

===================================================================

442

--- a/src/libitm/config/x86/target.h (.../tags/gcc_4_8_2_release)

443

+++ b/src/libitm/config/x86/target.h (.../branches/gcc-4_8-branch)

444

@@ -125,6 +125,13 @@

445

{

446

return begin_ret & _XABORT_RETRY;

447

}

448

+

449

+/* Returns true iff a hardware transaction is currently being executed. */

450

+static inline bool

451

+htm_transaction_active ()

452

+{

453

+ return _xtest() != 0;

454

+}

455

#endif

456

457

458

Index: libitm/config/generic/asmcfi.h

459

===================================================================

460

--- a/src/libitm/config/generic/asmcfi.h (.../tags/gcc_4_8_2_release)

461

+++ b/src/libitm/config/generic/asmcfi.h (.../branches/gcc-4_8-branch)

462

@@ -24,7 +24,7 @@

463

464

#include "config.h"

465

466

-#ifdef HAVE_AS_CFI_PSEUDO_OP

467

+#if defined(HAVE_AS_CFI_PSEUDO_OP) && defined(__GCC_HAVE_DWARF2_CFI_ASM)

468

469

#define cfi_startproc .cfi_startproc

470

#define cfi_endproc .cfi_endproc

471

@@ -50,4 +50,4 @@

472

#define cfi_restore(r)

473

#define cfi_undefined(r)

474

475

-#endif /* HAVE_AS_CFI_PSEUDO_OP */

476

+#endif /* HAVE_AS_CFI_PSEUDO_OP && __GCC_HAVE_DWARF2_CFI_ASM */

477

Index: libitm/acinclude.m4

478

===================================================================

479

--- a/src/libitm/acinclude.m4 (.../tags/gcc_4_8_2_release)

480

+++ b/src/libitm/acinclude.m4 (.../branches/gcc-4_8-branch)

481

@@ -121,12 +121,26 @@

482

AC_DEFINE(HAVE_AS_RTM, 1, [Define to 1 if the assembler supports RTM.])

483

fi

484

;;

485

+esac])

486

+

487

+dnl Check if as supports HTM instructions.

488

+AC_DEFUN([LIBITM_CHECK_AS_HTM], [

489

+case "${target_cpu}" in

490

+powerpc*)

491

+ AC_CACHE_CHECK([if the assembler supports HTM], libitm_cv_as_htm, [

492

+ AC_TRY_COMPILE([], [asm("tbegin. 0; tend. 0");],

493

+ [libitm_cv_as_htm=yes], [libitm_cv_as_htm=no])

494

+ ])

495

+ if test x$libitm_cv_as_htm = xyes; then

496

+ AC_DEFINE(HAVE_AS_HTM, 1, [Define to 1 if the assembler supports HTM.])

497

+ fi

498

+ ;;

499

s390*)

500

AC_CACHE_CHECK([if the assembler supports HTM], libitm_cv_as_htm, [

501

save_CFLAGS="$CFLAGS"

502

CFLAGS="$CFLAGS -march=zEC12"

503

AC_TRY_COMPILE([], [asm("tbegin 0,0; tend");],

504

- [libitm_cv_as_htm=yes], [libitm_cv_as_htm=no])

505

+ [libitm_cv_as_htm=yes], [libitm_cv_as_htm=no])

506

CFLAGS="$save_CFLAGS"])

507

if test x$libitm_cv_as_htm = xyes; then

508

AC_DEFINE(HAVE_AS_HTM, 1, [Define to 1 if the assembler supports HTM.])

509

Index: libtool.m4

510

===================================================================

511

--- a/src/libtool.m4 (.../tags/gcc_4_8_2_release)

512

+++ b/src/libtool.m4 (.../branches/gcc-4_8-branch)

513

@@ -1220,7 +1220,7 @@

514

rm -rf conftest*

515

;;

516

517

-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \

518

+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \

519

s390*-*linux*|s390*-*tpf*|sparc*-*linux*)

520

# Find out which ABI we are using.

521

echo 'int i;' > conftest.$ac_ext

522

@@ -1241,7 +1241,10 @@

523

;;

524

esac

525

;;

526

- ppc64-*linux*|powerpc64-*linux*)

527

+ powerpc64le-*linux*)

528

+ LD="${LD-ld} -m elf32lppclinux"

529

+ ;;

530

+ powerpc64-*linux*)

531

LD="${LD-ld} -m elf32ppclinux"

532

;;

533

s390x-*linux*)

534

@@ -1260,7 +1263,10 @@

535

x86_64-*linux*)

536

LD="${LD-ld} -m elf_x86_64"

537

;;

538

- ppc*-*linux*|powerpc*-*linux*)

539

+ powerpcle-*linux*)

540

+ LD="${LD-ld} -m elf64lppc"

541

+ ;;

542

+ powerpc-*linux*)

543

LD="${LD-ld} -m elf64ppc"

544

;;

545

s390*-*linux*|s390*-*tpf*)

546

Index: libgomp/configure

547

===================================================================

548

--- a/src/libgomp/configure (.../tags/gcc_4_8_2_release)

549

+++ b/src/libgomp/configure (.../branches/gcc-4_8-branch)

550

@@ -6580,7 +6580,7 @@

551

rm -rf conftest*

552

;;

553

554

-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \

555

+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \

556

s390*-*linux*|s390*-*tpf*|sparc*-*linux*)

557

# Find out which ABI we are using.

558

echo 'int i;' > conftest.$ac_ext

559

@@ -6605,7 +6605,10 @@

560

;;

561

esac

562

;;

563

- ppc64-*linux*|powerpc64-*linux*)

564

+ powerpc64le-*linux*)

565

+ LD="${LD-ld} -m elf32lppclinux"

566

+ ;;

567

+ powerpc64-*linux*)

568

LD="${LD-ld} -m elf32ppclinux"

569

;;

570

s390x-*linux*)

571

@@ -6624,7 +6627,10 @@

572

x86_64-*linux*)

573

LD="${LD-ld} -m elf_x86_64"

574

;;

575

- ppc*-*linux*|powerpc*-*linux*)

576

+ powerpcle-*linux*)

577

+ LD="${LD-ld} -m elf64lppc"

578

+ ;;

579

+ powerpc-*linux*)

580

LD="${LD-ld} -m elf64ppc"

581

;;

582

s390*-*linux*|s390*-*tpf*)

583

@@ -11088,7 +11094,7 @@

584

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

585

lt_status=$lt_dlunknown

586

cat > conftest.$ac_ext <<_LT_EOF

587

-#line 11091 "configure"

588

+#line 11097 "configure"

589

#include "confdefs.h"

590

591

#if HAVE_DLFCN_H

592

@@ -11194,7 +11200,7 @@

593

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

594

lt_status=$lt_dlunknown

595

cat > conftest.$ac_ext <<_LT_EOF

596

-#line 11197 "configure"

597

+#line 11203 "configure"

598

#include "confdefs.h"

599

600

#if HAVE_DLFCN_H

601

Index: libgomp/ChangeLog

602

===================================================================

603

--- a/src/libgomp/ChangeLog (.../tags/gcc_4_8_2_release)

604

+++ b/src/libgomp/ChangeLog (.../branches/gcc-4_8-branch)

605

@@ -1,3 +1,21 @@

606

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

607

+

608

+ Backport from mainline

609

+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

610

+

611

+ * configure: Regenerate.

612

+

613

+2014-04-02 Richard Henderson <rth@redhat.com>

614

+

615

+ * config/linux/futex.h (futex_wait): Get error value from errno.

616

+ (futex_wake): Likewise.

617

+

618

+2013-12-12 Jakub Jelinek <jakub@redhat.com>

619

+

620

+ PR libgomp/59467

621

+ * testsuite/libgomp.fortran/crayptr2.f90: Add private (d) clause to

622

+ !$omp parallel.

623

+

624

2013-10-16 Release Manager

625

626

* GCC 4.8.2 released.

627

Index: libgomp/testsuite/libgomp.fortran/crayptr2.f90

628

===================================================================

629

--- a/src/libgomp/testsuite/libgomp.fortran/crayptr2.f90 (.../tags/gcc_4_8_2_release)

630

+++ b/src/libgomp/testsuite/libgomp.fortran/crayptr2.f90 (.../branches/gcc-4_8-branch)

631

@@ -12,7 +12,7 @@

632

b = 2

633

c = 3

634

l = .false.

635

-!$omp parallel num_threads (3) reduction (.or.:l)

636

+!$omp parallel num_threads (3) reduction (.or.:l) private (d)

637

if (omp_get_thread_num () .eq. 0) then

638

ip = loc (a)

639

elseif (omp_get_thread_num () .eq. 1) then

640

Index: libgomp/config/linux/futex.h

641

===================================================================

642

--- a/src/libgomp/config/linux/futex.h (.../tags/gcc_4_8_2_release)

643

+++ b/src/libgomp/config/linux/futex.h (.../branches/gcc-4_8-branch)

644

@@ -41,8 +41,8 @@

645

static inline void

646

futex_wait (int *addr, int val)

647

{

648

- long err = syscall (SYS_futex, addr, gomp_futex_wait, val, NULL);

649

- if (__builtin_expect (err == -ENOSYS, 0))

650

+ int err = syscall (SYS_futex, addr, gomp_futex_wait, val, NULL);

651

+ if (__builtin_expect (err < 0 && errno == ENOSYS, 0))

652

{

653

gomp_futex_wait &= ~FUTEX_PRIVATE_FLAG;

654

gomp_futex_wake &= ~FUTEX_PRIVATE_FLAG;

655

@@ -53,8 +53,8 @@

656

static inline void

657

futex_wake (int *addr, int count)

658

{

659

- long err = syscall (SYS_futex, addr, gomp_futex_wake, count);

660

- if (__builtin_expect (err == -ENOSYS, 0))

661

+ int err = syscall (SYS_futex, addr, gomp_futex_wake, count);

662

+ if (__builtin_expect (err < 0 && errno == ENOSYS, 0))

663

{

664

gomp_futex_wait &= ~FUTEX_PRIVATE_FLAG;

665

gomp_futex_wake &= ~FUTEX_PRIVATE_FLAG;

666

Index: libquadmath/configure

667

===================================================================

668

--- a/src/libquadmath/configure (.../tags/gcc_4_8_2_release)

669

+++ b/src/libquadmath/configure (.../branches/gcc-4_8-branch)

670

@@ -6248,7 +6248,7 @@

671

rm -rf conftest*

672

;;

673

674

-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \

675

+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \

676

s390*-*linux*|s390*-*tpf*|sparc*-*linux*)

677

# Find out which ABI we are using.

678

echo 'int i;' > conftest.$ac_ext

679

@@ -6273,7 +6273,10 @@

680

;;

681

esac

682

;;

683

- ppc64-*linux*|powerpc64-*linux*)

684

+ powerpc64le-*linux*)

685

+ LD="${LD-ld} -m elf32lppclinux"

686

+ ;;

687

+ powerpc64-*linux*)

688

LD="${LD-ld} -m elf32ppclinux"

689

;;

690

s390x-*linux*)

691

@@ -6292,7 +6295,10 @@

692

x86_64-*linux*)

693

LD="${LD-ld} -m elf_x86_64"

694

;;

695

- ppc*-*linux*|powerpc*-*linux*)

696

+ powerpcle-*linux*)

697

+ LD="${LD-ld} -m elf64lppc"

698

+ ;;

699

+ powerpc-*linux*)

700

LD="${LD-ld} -m elf64ppc"

701

;;

702

s390*-*linux*|s390*-*tpf*)

703

@@ -10521,7 +10527,7 @@

704

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

705

lt_status=$lt_dlunknown

706

cat > conftest.$ac_ext <<_LT_EOF

707

-#line 10524 "configure"

708

+#line 10530 "configure"

709

#include "confdefs.h"

710

711

#if HAVE_DLFCN_H

712

@@ -10627,7 +10633,7 @@

713

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

714

lt_status=$lt_dlunknown

715

cat > conftest.$ac_ext <<_LT_EOF

716

-#line 10630 "configure"

717

+#line 10636 "configure"

718

#include "confdefs.h"

719

720

#if HAVE_DLFCN_H

721

Index: libquadmath/ChangeLog

722

===================================================================

723

--- a/src/libquadmath/ChangeLog (.../tags/gcc_4_8_2_release)

724

+++ b/src/libquadmath/ChangeLog (.../branches/gcc-4_8-branch)

725

@@ -1,3 +1,10 @@

726

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

727

+

728

+ Backport from mainline

729

+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

730

+

731

+ * configure: Regenerate.

732

+

733

2013-10-16 Release Manager

734

735

* GCC 4.8.2 released.

736

Index: libsanitizer/configure

737

===================================================================

738

--- a/src/libsanitizer/configure (.../tags/gcc_4_8_2_release)

739

+++ b/src/libsanitizer/configure (.../branches/gcc-4_8-branch)

740

@@ -6604,7 +6604,7 @@

741

rm -rf conftest*

742

;;

743

744

-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \

745

+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \

746

s390*-*linux*|s390*-*tpf*|sparc*-*linux*)

747

# Find out which ABI we are using.

748

echo 'int i;' > conftest.$ac_ext

749

@@ -6629,7 +6629,10 @@

750

;;

751

esac

752

;;

753

- ppc64-*linux*|powerpc64-*linux*)

754

+ powerpc64le-*linux*)

755

+ LD="${LD-ld} -m elf32lppclinux"

756

+ ;;

757

+ powerpc64-*linux*)

758

LD="${LD-ld} -m elf32ppclinux"

759

;;

760

s390x-*linux*)

761

@@ -6648,7 +6651,10 @@

762

x86_64-*linux*)

763

LD="${LD-ld} -m elf_x86_64"

764

;;

765

- ppc*-*linux*|powerpc*-*linux*)

766

+ powerpcle-*linux*)

767

+ LD="${LD-ld} -m elf64lppc"

768

+ ;;

769

+ powerpc-*linux*)

770

LD="${LD-ld} -m elf64ppc"

771

;;

772

s390*-*linux*|s390*-*tpf*)

773

@@ -11111,7 +11117,7 @@

774

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

775

lt_status=$lt_dlunknown

776

cat > conftest.$ac_ext <<_LT_EOF

777

-#line 11114 "configure"

778

+#line 11120 "configure"

779

#include "confdefs.h"

780

781

#if HAVE_DLFCN_H

782

@@ -11217,7 +11223,7 @@

783

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

784

lt_status=$lt_dlunknown

785

cat > conftest.$ac_ext <<_LT_EOF

786

-#line 11220 "configure"

787

+#line 11226 "configure"

788

#include "confdefs.h"

789

790

#if HAVE_DLFCN_H

791

Index: libsanitizer/ChangeLog

792

===================================================================

793

--- a/src/libsanitizer/ChangeLog (.../tags/gcc_4_8_2_release)

794

+++ b/src/libsanitizer/ChangeLog (.../branches/gcc-4_8-branch)

795

@@ -1,3 +1,17 @@

796

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

797

+

798

+ Backport from mainline r208290

799

+ 2014-03-03 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

800

+

801

+ * configure.tgt: Unsupported for little endian PowerPC for now.

802

+

803

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

804

+

805

+ Backport from mainline

806

+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

807

+

808

+ * configure: Regenerate.

809

+

810

2013-10-16 Release Manager

811

812

* GCC 4.8.2 released.

813

Index: libsanitizer/configure.tgt

814

===================================================================

815

--- a/src/libsanitizer/configure.tgt (.../tags/gcc_4_8_2_release)

816

+++ b/src/libsanitizer/configure.tgt (.../branches/gcc-4_8-branch)

817

@@ -25,6 +25,9 @@

818

TSAN_SUPPORTED=yes

819

fi

820

;;

821

+ powerpc*le-*-linux*)

822

+ UNSUPPORTED=1

823

+ ;;

824

powerpc*-*-linux*)

825

;;

826

sparc*-*-linux*)

827

Index: zlib/configure

828

===================================================================

829

--- a/src/zlib/configure (.../tags/gcc_4_8_2_release)

830

+++ b/src/zlib/configure (.../branches/gcc-4_8-branch)

831

@@ -5853,7 +5853,7 @@

832

rm -rf conftest*

833

;;

834

835

-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \

836

+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \

837

s390*-*linux*|s390*-*tpf*|sparc*-*linux*)

838

# Find out which ABI we are using.

839

echo 'int i;' > conftest.$ac_ext

840

@@ -5878,7 +5878,10 @@

841

;;

842

esac

843

;;

844

- ppc64-*linux*|powerpc64-*linux*)

845

+ powerpc64le-*linux*)

846

+ LD="${LD-ld} -m elf32lppclinux"

847

+ ;;

848

+ powerpc64-*linux*)

849

LD="${LD-ld} -m elf32ppclinux"

850

;;

851

s390x-*linux*)

852

@@ -5897,7 +5900,10 @@

853

x86_64-*linux*)

854

LD="${LD-ld} -m elf_x86_64"

855

;;

856

- ppc*-*linux*|powerpc*-*linux*)

857

+ powerpcle-*linux*)

858

+ LD="${LD-ld} -m elf64lppc"

859

+ ;;

860

+ powerpc-*linux*)

861

LD="${LD-ld} -m elf64ppc"

862

;;

863

s390*-*linux*|s390*-*tpf*)

864

@@ -10394,7 +10400,7 @@

865

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

866

lt_status=$lt_dlunknown

867

cat > conftest.$ac_ext <<_LT_EOF

868

-#line 10397 "configure"

869

+#line 10403 "configure"

870

#include "confdefs.h"

871

872

#if HAVE_DLFCN_H

873

@@ -10500,7 +10506,7 @@

874

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

875

lt_status=$lt_dlunknown

876

cat > conftest.$ac_ext <<_LT_EOF

877

-#line 10503 "configure"

878

+#line 10509 "configure"

879

#include "confdefs.h"

880

881

#if HAVE_DLFCN_H

882

Index: zlib/ChangeLog

883

===================================================================

884

--- a/src/zlib/ChangeLog (.../tags/gcc_4_8_2_release)

885

+++ b/src/zlib/ChangeLog (.../branches/gcc-4_8-branch)

886

@@ -1,3 +1,10 @@

887

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

888

+

889

+ Backport from mainline

890

+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

891

+

892

+ * configure: Regenerate.

893

+

894

2013-10-16 Release Manager

895

896

* GCC 4.8.2 released.

897

Index: libstdc++-v3/configure

898

===================================================================

899

--- a/src/libstdc++-v3/configure (.../tags/gcc_4_8_2_release)

900

+++ b/src/libstdc++-v3/configure (.../branches/gcc-4_8-branch)

901

@@ -7111,7 +7111,7 @@

902

rm -rf conftest*

903

;;

904

905

-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \

906

+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \

907

s390*-*linux*|s390*-*tpf*|sparc*-*linux*)

908

# Find out which ABI we are using.

909

echo 'int i;' > conftest.$ac_ext

910

@@ -7136,7 +7136,10 @@

911

;;

912

esac

913

;;

914

- ppc64-*linux*|powerpc64-*linux*)

915

+ powerpc64le-*linux*)

916

+ LD="${LD-ld} -m elf32lppclinux"

917

+ ;;

918

+ powerpc64-*linux*)

919

LD="${LD-ld} -m elf32ppclinux"

920

;;

921

s390x-*linux*)

922

@@ -7155,7 +7158,10 @@

923

x86_64-*linux*)

924

LD="${LD-ld} -m elf_x86_64"

925

;;

926

- ppc*-*linux*|powerpc*-*linux*)

927

+ powerpcle-*linux*)

928

+ LD="${LD-ld} -m elf64lppc"

929

+ ;;

930

+ powerpc-*linux*)

931

LD="${LD-ld} -m elf64ppc"

932

;;

933

s390*-*linux*|s390*-*tpf*)

934

@@ -11513,7 +11519,7 @@

935

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

936

lt_status=$lt_dlunknown

937

cat > conftest.$ac_ext <<_LT_EOF

938

-#line 11516 "configure"

939

+#line 11522 "configure"

940

#include "confdefs.h"

941

942

#if HAVE_DLFCN_H

943

@@ -11619,7 +11625,7 @@

944

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

945

lt_status=$lt_dlunknown

946

cat > conftest.$ac_ext <<_LT_EOF

947

-#line 11622 "configure"

948

+#line 11628 "configure"

949

#include "confdefs.h"

950

951

#if HAVE_DLFCN_H

952

@@ -15033,7 +15039,7 @@

953

#

954

# Fake what AC_TRY_COMPILE does. XXX Look at redoing this new-style.

955

cat > conftest.$ac_ext << EOF

956

-#line 15036 "configure"

957

+#line 15042 "configure"

958

struct S { ~S(); };

959

void bar();

960

void foo()

961

@@ -15383,7 +15389,7 @@

962

# Fake what AC_TRY_COMPILE does.

963

964

cat > conftest.$ac_ext << EOF

965

-#line 15386 "configure"

966

+#line 15392 "configure"

967

int main()

968

{

969

typedef bool atomic_type;

970

@@ -15418,7 +15424,7 @@

971

rm -f conftest*

972

973

cat > conftest.$ac_ext << EOF

974

-#line 15421 "configure"

975

+#line 15427 "configure"

976

int main()

977

{

978

typedef short atomic_type;

979

@@ -15453,7 +15459,7 @@

980

rm -f conftest*

981

982

cat > conftest.$ac_ext << EOF

983

-#line 15456 "configure"

984

+#line 15462 "configure"

985

int main()

986

{

987

// NB: _Atomic_word not necessarily int.

988

@@ -15489,7 +15495,7 @@

989

rm -f conftest*

990

991

cat > conftest.$ac_ext << EOF

992

-#line 15492 "configure"

993

+#line 15498 "configure"

994

int main()

995

{

996

typedef long long atomic_type;

997

@@ -15568,7 +15574,7 @@

998

# unnecessary for this test.

999

1000

cat > conftest.$ac_ext << EOF

1001

-#line 15571 "configure"

1002

+#line 15577 "configure"

1003

int main()

1004

{

1005

_Decimal32 d1;

1006

@@ -15610,7 +15616,7 @@

1007

# unnecessary for this test.

1008

1009

cat > conftest.$ac_ext << EOF

1010

-#line 15613 "configure"

1011

+#line 15619 "configure"

1012

template<typename T1, typename T2>

1013

struct same

1014

{ typedef T2 type; };

1015

@@ -15644,7 +15650,7 @@

1016

rm -f conftest*

1017

1018

cat > conftest.$ac_ext << EOF

1019

-#line 15647 "configure"

1020

+#line 15653 "configure"

1021

template<typename T1, typename T2>

1022

struct same

1023

{ typedef T2 type; };

1024

@@ -71573,7 +71579,7 @@

1025

fi

1026

1027

# For libtool versioning info, format is CURRENT:REVISION:AGE

1028

-libtool_VERSION=6:18:0

1029

+libtool_VERSION=6:19:0

1030

1031

# Everything parsed; figure out what files and settings to use.

1032

case $enable_symvers in

1033

Index: libstdc++-v3/scripts/extract_symvers.in

1034

===================================================================

1035

--- a/src/libstdc++-v3/scripts/extract_symvers.in (.../tags/gcc_4_8_2_release)

1036

+++ b/src/libstdc++-v3/scripts/extract_symvers.in (.../branches/gcc-4_8-branch)

1037

@@ -53,6 +53,7 @@

1038

# present on Solaris.

1039

${readelf} ${lib} |\

1040

sed -e 's/ \[<other>: [A-Fa-f0-9]*\] //' -e '/\.dynsym/,/^$/p;d' |\

1041

+ sed -e 's/ \[<localentry>: [0-9]*\] //' |\

1042

egrep -v ' (LOCAL|UND) ' |\

1043

1044

sed -e 's/ <processor specific>: / <processor_specific>:_/g' |\

1045

Index: libstdc++-v3/src/c++11/thread.cc

1046

===================================================================

1047

--- a/src/libstdc++-v3/src/c++11/thread.cc (.../tags/gcc_4_8_2_release)

1048

+++ b/src/libstdc++-v3/src/c++11/thread.cc (.../branches/gcc-4_8-branch)

1049

@@ -183,7 +183,7 @@

1050

::usleep(__us);

1051

}

1052

# else

1053

- ::sleep(__s.count() + (__ns >= 1000000));

1054

+ ::sleep(__s.count() + (__ns.count() >= 1000000));

1055

# endif

1056

#elif defined(_GLIBCXX_HAVE_WIN32_SLEEP)

1057

unsigned long ms = __ns.count() / 1000000;

1058

Index: libstdc++-v3/doc/xml/manual/abi.xml

1059

===================================================================

1060

--- a/src/libstdc++-v3/doc/xml/manual/abi.xml (.../tags/gcc_4_8_2_release)

1061

+++ b/src/libstdc++-v3/doc/xml/manual/abi.xml (.../branches/gcc-4_8-branch)

1062

@@ -203,6 +203,7 @@

1063

1064

1065

1066

+ <listitem><para>GCC 4.8.0: GCC_4.8.0</para></listitem>

1067

</itemizedlist>

1068

</listitem>

1069

1070

@@ -261,6 +262,7 @@

1071

<listitem><para>GCC 4.6.1: libstdc++.so.6.0.16</para></listitem>

1072

<listitem><para>GCC 4.7.0: libstdc++.so.6.0.17</para></listitem>

1073

<listitem><para>GCC 4.8.0: libstdc++.so.6.0.18</para></listitem>

1074

+ <listitem><para>GCC 4.8.3: libstdc++.so.6.0.19</para></listitem>

1075

</itemizedlist>

1076

<para>

1077

Note 1: Error should be libstdc++.so.3.0.3.

1078

@@ -324,6 +326,7 @@

1079

<listitem><para>GCC 4.6.1: GLIBCXX_3.4.16, CXXABI_1.3.5</para></listitem>

1080

<listitem><para>GCC 4.7.0: GLIBCXX_3.4.17, CXXABI_1.3.6</para></listitem>

1081

<listitem><para>GCC 4.8.0: GLIBCXX_3.4.18, CXXABI_1.3.7</para></listitem>

1082

+ <listitem><para>GCC 4.8.3: GLIBCXX_3.4.19, CXXABI_1.3.7</para></listitem>

1083

</itemizedlist>

1084

</listitem>

1085

1086

Index: libstdc++-v3/doc/xml/manual/status_cxx2011.xml

1087

===================================================================

1088

--- a/src/libstdc++-v3/doc/xml/manual/status_cxx2011.xml (.../tags/gcc_4_8_2_release)

1089

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1090

@@ -877,10 +877,11 @@

1091

1092

</row>

1093

<row>

1094

+ <?dbhtml bgcolor="#B0B0B0" ?>

1095

1096

<entry>Other transformations</entry>

1097

- <entry>Y</entry>

1098

- <entry/>

1099

+ <entry>Partial</entry>

1100

+ <entry>Missing <code>aligned_union</code>.</entry>

1101

</row>

1102

<row>

1103

1104

Index: libstdc++-v3/doc/xml/manual/spine.xml

1105

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1106

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1107

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1108

@@ -20,6 +20,7 @@

1109

1110

1111

1112

+ <year>2013</year>

1113

1114

1115

</holder>

1116

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1117

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1123

\ No newline at end of file

1124

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title></title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="index.html" title="The GNU C++ Library" /><link rel="up" href="index.html" title="The GNU C++ Library" /><link rel="prev" href="manual/backwards.html" title="Backwards Compatibility" /><link rel="next" href="api.html" title="The GNU C++ Library API Reference" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center"></th></tr><tr><td width="20%" align="left"><a accesskey="p" href="manual/backwards.html">Prev</a> </td><th width="60%" align="center"> </th><td width="20%" align="right"> <a accesskey="n" href="api.html">Next</a></td></tr></table><hr /></div><div class="book"><div class="titlepage"><hr /></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="article"><a href="api.html">The GNU C++ Library API Reference</a></span></dt></dl></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="manual/backwards.html">Prev</a> </td><td width="20%" align="center"> </td><td width="40%" align="right"> <a accesskey="n" href="api.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">Backwards Compatibility </td><td width="20%" align="center"><a accesskey="h" href="index.html">Home</a></td><td width="40%" align="right" valign="top"> The GNU C++ Library API Reference</td></tr></table></div></body></html>

1125

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1127

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1130

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1131

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1133

\ No newline at end of file

1134

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title></title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="index.html" title="The GNU C++ Library" /><link rel="up" href="index.html" title="The GNU C++ Library" /><link rel="prev" href="api.html" title="The GNU C++ Library API Reference" /><link rel="next" href="faq.html" title="Frequently Asked Questions" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center"></th></tr><tr><td width="20%" align="left"><a accesskey="p" href="api.html">Prev</a> </td><th width="60%" align="center"> </th><td width="20%" align="right"> <a accesskey="n" href="faq.html">Next</a></td></tr></table><hr /></div><div class="book"><div class="titlepage"><hr /></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="article"><a href="faq.html">Frequently Asked Questions</a></span></dt></dl></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="api.html">Prev</a> </td><td width="20%" align="center"> </td><td width="40%" align="right"> <a accesskey="n" href="faq.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">The GNU C++ Library API Reference </td><td width="20%" align="center"><a accesskey="h" href="index.html">Home</a></td><td width="40%" align="right" valign="top"> Frequently Asked Questions</td></tr></table></div></body></html>

1135

\ No newline at end of file

1136

Index: libstdc++-v3/doc/html/faq.html

1137

===================================================================

1138

--- a/src/libstdc++-v3/doc/html/faq.html (.../tags/gcc_4_8_2_release)

1139

+++ b/src/libstdc++-v3/doc/html/faq.html (.../branches/gcc-4_8-branch)

1140

@@ -1,9 +1,9 @@

1141

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

1142

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Frequently Asked Questions</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="index.html" title="The GNU C++ Library" /><link rel="up" href="bk03.html" title="" /><link rel="prev" href="bk03.html" title="" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Frequently Asked Questions</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="bk03.html">Prev</a> </td><th width="60%" align="center"></th><td width="20%" align="right"> </td></tr></table><hr /></div><div class="article"><div class="titlepage"><div><div><h1 class="title"><a id="faq"></a>Frequently Asked Questions</h1></div><div><p class="copyright">Copyright ©

1143

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Frequently Asked Questions</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="index.html" title="The GNU C++ Library" /><link rel="up" href="bk03.html" title="" /><link rel="prev" href="bk03.html" title="" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Frequently Asked Questions</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="bk03.html">Prev</a> </td><th width="60%" align="center"></th><td width="20%" align="right"> </td></tr></table><hr /></div><div class="article"><div class="titlepage"><div><div><h1 class="title"><a id="faq"></a>Frequently Asked Questions</h1></div><div><p class="copyright">Copyright ©

1144

2008, 2010

1145

1146

1147

- </p></div></div><hr /></div><div class="qandaset"><a id="idp1581728"></a><dl><dt></dt><dd><dl><dt>1.1. <a href="faq.html#faq.what">

1148

+ </p></div></div><hr /></div><div class="qandaset"><a id="idm270011560848"></a><dl><dt></dt><dd><dl><dt>1.1. <a href="faq.html#faq.what">

1149

What is libstdc++?

1150

</a></dt><dt>1.2. <a href="faq.html#faq.why">

1151

Why should I use libstdc++?

1152

Index: libstdc++-v3/doc/html/index.html

1153

===================================================================

1154

--- a/src/libstdc++-v3/doc/html/index.html (.../tags/gcc_4_8_2_release)

1155

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1156

@@ -1,5 +1,5 @@

1157

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

1158

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>The GNU C++ Library</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="description" content="Short Contents Copyright (C) 2008-2013 FSF Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, with no Front-Cover Texts, and with no Back-Cover Texts. This is the top level of the libstdc++ documentation set. The documentation is divided into the following three sections. Manual Frequently Asked Questions API and Source Documentation" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="index.html" title="The GNU C++ Library" /><link rel="next" href="manual/index.html" title="The GNU C++ Library Manual" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">The GNU C++ Library</th></tr><tr><td width="20%" align="left"> </td><th width="60%" align="center"> </th><td width="20%" align="right"> <a accesskey="n" href="manual/index.html">Next</a></td></tr></table><hr /></div><div class="set" lang="en" xml:lang="en"><div class="titlepage"><div><div><h1 class="title"><a id="set-index"></a>The GNU C++ Library</h1></div><div><div class="abstract"><a id="contents"></a><p class="title"><strong>Short Contents</strong></p><p>

1159

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>The GNU C++ Library</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="description" content="Short Contents Copyright (C) 2008-2013 FSF Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, with no Front-Cover Texts, and with no Back-Cover Texts. This is the top level of the libstdc++ documentation set. The documentation is divided into the following three sections. Manual Frequently Asked Questions API and Source Documentation" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="index.html" title="The GNU C++ Library" /><link rel="next" href="manual/index.html" title="The GNU C++ Library Manual" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">The GNU C++ Library</th></tr><tr><td width="20%" align="left"> </td><th width="60%" align="center"> </th><td width="20%" align="right"> <a accesskey="n" href="manual/index.html">Next</a></td></tr></table><hr /></div><div class="set" lang="en" xml:lang="en"><div class="titlepage"><div><div><h1 class="title"><a id="set-index"></a>The GNU C++ Library</h1></div><div><div class="abstract"><a id="contents"></a><p class="title"><strong>Short Contents</strong></p><p>

1160

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<a class="link" href="http://www.fsf.org/" target="_top">FSF

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1165

<a class="link" href="api.html" title="The GNU C++ Library API Reference">API and Source Documentation</a>

1166

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1167

- </p></div></div></div><hr /></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="book"><a href="manual/index.html">The GNU C++ Library Manual</a></span></dt><dd><dl><dt><span class="part"><a href="manual/intro.html">I.

1168

+ </p></div></div></div><hr /></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="book"><a href="manual/index.html">The GNU C++ Library Manual</a></span></dt><dd><dl><dt><span class="part"><a href="manual/intro.html">I.

1169

Introduction

1170

1171

</a></span></dt><dd><dl><dt><span class="chapter"><a href="manual/status.html">1. Status</a></span></dt><dd><dl><dt><span class="section"><a href="manual/status.html#manual.intro.status.iso">Implementation Status</a></span></dt><dd><dl><dt><span class="section"><a href="manual/status.html#status.iso.1998">C++ 1998/2003</a></span></dt><dd><dl><dt><span class="section"><a href="manual/status.html#iso.1998.status">Implementation Status</a></span></dt><dt><span class="section"><a href="manual/status.html#iso.1998.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="manual/status.html#status.iso.2011">C++ 2011</a></span></dt><dd><dl><dt><span class="section"><a href="manual/status.html#iso.2011.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="manual/status.html#status.iso.tr1">C++ TR1</a></span></dt><dd><dl><dt><span class="section"><a href="manual/status.html#iso.tr1.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="manual/status.html#status.iso.tr24733">C++ TR 24733</a></span></dt></dl></dd><dt><span class="section"><a href="manual/license.html">License</a></span></dt><dd><dl><dt><span class="section"><a href="manual/license.html#manual.intro.status.license.gpl">The Code: GPL</a></span></dt><dt><span class="section"><a href="manual/license.html#manual.intro.status.license.fdl">The Documentation: GPL, FDL</a></span></dt></dl></dd><dt><span class="section"><a href="manual/bugs.html">Bugs</a></span></dt><dd><dl><dt><span class="section"><a href="manual/bugs.html#manual.intro.status.bugs.impl">Implementation Bugs</a></span></dt><dt><span class="section"><a href="manual/bugs.html#manual.intro.status.bugs.iso">Standard Bugs</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="manual/setup.html">2. Setup</a></span></dt><dd><dl><dt><span class="section"><a href="manual/setup.html#manual.intro.setup.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="manual/configure.html">Configure</a></span></dt><dt><span class="section"><a href="manual/make.html">Make</a></span></dt></dl></dd><dt><span class="chapter"><a href="manual/using.html">3. Using</a></span></dt><dd><dl><dt><span class="section"><a href="manual/using.html#manual.intro.using.flags">Command Options</a></span></dt><dt><span class="section"><a href="manual/using_headers.html">Headers</a></span></dt><dd><dl><dt><span class="section"><a href="manual/using_headers.html#manual.intro.using.headers.all">Header Files</a></span></dt><dt><span class="section"><a href="manual/using_headers.html#manual.intro.using.headers.mixing">Mixing Headers</a></span></dt><dt><span class="section"><a href="manual/using_headers.html#manual.intro.using.headers.cheaders">The C Headers and <code class="code">namespace std</code></a></span></dt><dt><span class="section"><a href="manual/using_headers.html#manual.intro.using.headers.pre">Precompiled Headers</a></span></dt></dl></dd><dt><span class="section"><a href="manual/using_macros.html">Macros</a></span></dt><dt><span class="section"><a href="manual/using_namespaces.html">Namespaces</a></span></dt><dd><dl><dt><span class="section"><a href="manual/using_namespaces.html#manual.intro.using.namespaces.all">Available Namespaces</a></span></dt><dt><span class="section"><a href="manual/using_namespaces.html#manual.intro.using.namespaces.std">namespace std</a></span></dt><dt><span class="section"><a href="manual/using_namespaces.html#manual.intro.using.namespaces.comp">Using Namespace Composition</a></span></dt></dl></dd><dt><span class="section"><a href="manual/using_dynamic_or_shared.html">Linking</a></span></dt><dd><dl><dt><span class="section"><a href="manual/using_dynamic_or_shared.html#manual.intro.using.linkage.freestanding">Almost Nothing</a></span></dt><dt><span class="section"><a href="manual/using_dynamic_or_shared.html#manual.intro.using.linkage.dynamic">Finding Dynamic or Shared Libraries</a></span></dt></dl></dd><dt><span class="section"><a href="manual/using_concurrency.html">Concurrency</a></span></dt><dd><dl><dt><span class="section"><a href="manual/using_concurrency.html#manual.intro.using.concurrency.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="manual/using_concurrency.html#manual.intro.using.concurrency.thread_safety">Thread Safety</a></span></dt><dt><span class="section"><a href="manual/using_concurrency.html#manual.intro.using.concurrency.atomics">Atomics</a></span></dt><dt><span class="section"><a href="manual/using_concurrency.html#manual.intro.using.concurrency.io">IO</a></span></dt><dd><dl><dt><span class="section"><a href="manual/using_concurrency.html#concurrency.io.structure">Structure</a></span></dt><dt><span class="section"><a href="manual/using_concurrency.html#concurrency.io.defaults">Defaults</a></span></dt><dt><span class="section"><a href="manual/using_concurrency.html#concurrency.io.future">Future</a></span></dt><dt><span class="section"><a href="manual/using_concurrency.html#concurrency.io.alt">Alternatives</a></span></dt></dl></dd><dt><span class="section"><a href="manual/using_concurrency.html#manual.intro.using.concurrency.containers">Containers</a></span></dt></dl></dd><dt><span class="section"><a href="manual/using_exceptions.html">Exceptions</a></span></dt><dd><dl><dt><span class="section"><a href="manual/using_exceptions.html#intro.using.exception.safety">Exception Safety</a></span></dt><dt><span class="section"><a href="manual/using_exceptions.html#intro.using.exception.propagating">Exception Neutrality</a></span></dt><dt><span class="section"><a href="manual/using_exceptions.html#intro.using.exception.no">Doing without</a></span></dt><dt><span class="section"><a href="manual/using_exceptions.html#intro.using.exception.compat">Compatibility</a></span></dt><dd><dl><dt><span class="section"><a href="manual/using_exceptions.html#using.exception.compat.c">With <code class="literal">C</code></a></span></dt><dt><span class="section"><a href="manual/using_exceptions.html#using.exception.compat.posix">With <code class="literal">POSIX</code> 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Support

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Iterators

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Standard Contents

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Iterators

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- <a id="idp16156992" class="indexterm"></a>

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-</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="iterators.html#std.iterators.predefined">Predefined</a></span></dt><dd><dl><dt><span class="section"><a href="iterators.html#iterators.predefined.vs_pointers">Iterators vs. Pointers</a></span></dt><dt><span class="section"><a href="iterators.html#iterators.predefined.end">One Past the End</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.iterators.predefined"></a>Predefined</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="iterators.predefined.vs_pointers"></a>Iterators vs. Pointers</h3></div></div></div><p>

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+ <a id="idm269999374096" class="indexterm"></a>

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+</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="iterators.html#std.iterators.predefined">Predefined</a></span></dt><dd><dl><dt><span class="section"><a href="iterators.html#iterators.predefined.vs_pointers">Iterators vs. Pointers</a></span></dt><dt><span class="section"><a href="iterators.html#iterators.predefined.end">One Past the End</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.iterators.predefined"></a>Predefined</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="iterators.predefined.vs_pointers"></a>Iterators vs. Pointers</h3></div></div></div><p>

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The following

1239

FAQ <a class="link" href="../faq.html#faq.iterator_as_pod" title="7.1.">entry</a> points out that

1240

iterators are not implemented as pointers. They are a generalization

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1249

Let's start by describing how the data on a freelist is laid out in memory.

1250

This is the first two blocks in freelist for thread id 3 in bin 3 (8 bytes):

1251

</p><pre class="programlisting">

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Extensions

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</p><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="allocator.mt.intro"></a>Intro</h2></div></div></div><p>

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The mt allocator [hereinafter referred to simply as "the allocator"]

1277

is a fixed size (power of two) allocator that was initially

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Configure</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, configure, options" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="setup.html" title="Chapter 2. Setup" /><link rel="prev" href="setup.html" title="Chapter 2. Setup" /><link rel="next" href="make.html" title="Make" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Configure</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="setup.html">Prev</a> </td><th width="60%" align="center">Chapter 2. Setup</th><td width="20%" align="right"> <a accesskey="n" href="make.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.setup.configure"></a>Configure</h2></div></div></div><p>

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When configuring libstdc++, you'll have to configure the entire

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<span class="emphasis"><em>gccsrcdir</em></span> directory. Consider using the

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toplevel gcc configuration option

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Index: libstdc++-v3/doc/html/manual/status.html

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===================================================================

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>

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-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 1. Status</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="intro.html" title="Part I. Introduction" /><link rel="prev" href="intro.html" title="Part I. Introduction" /><link rel="next" href="license.html" title="License" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 1. Status</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="intro.html">Prev</a> </td><th width="60%" align="center">Part I.

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 1. Status</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="intro.html" title="Part I. Introduction" /><link rel="prev" href="intro.html" title="Part I. Introduction" /><link rel="next" href="license.html" title="License" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 1. Status</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="intro.html">Prev</a> </td><th width="60%" align="center">Part I.

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Introduction

1309

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-</th><td width="20%" align="right"> <a accesskey="n" href="license.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.intro.status"></a>Chapter 1. Status</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="status.html#manual.intro.status.iso">Implementation Status</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#status.iso.1998">C++ 1998/2003</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.1998.status">Implementation Status</a></span></dt><dt><span class="section"><a href="status.html#iso.1998.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.2011">C++ 2011</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.2011.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.tr1">C++ TR1</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.tr1.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.tr24733">C++ TR 24733</a></span></dt></dl></dd><dt><span class="section"><a href="license.html">License</a></span></dt><dd><dl><dt><span class="section"><a href="license.html#manual.intro.status.license.gpl">The Code: GPL</a></span></dt><dt><span class="section"><a href="license.html#manual.intro.status.license.fdl">The Documentation: GPL, FDL</a></span></dt></dl></dd><dt><span class="section"><a href="bugs.html">Bugs</a></span></dt><dd><dl><dt><span class="section"><a href="bugs.html#manual.intro.status.bugs.impl">Implementation Bugs</a></span></dt><dt><span class="section"><a href="bugs.html#manual.intro.status.bugs.iso">Standard Bugs</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.status.iso"></a>Implementation Status</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="status.iso.1998"></a>C++ 1998/2003</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="iso.1998.status"></a>Implementation Status</h4></div></div></div><p>

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+</th><td width="20%" align="right"> <a accesskey="n" href="license.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.intro.status"></a>Chapter 1. Status</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="status.html#manual.intro.status.iso">Implementation Status</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#status.iso.1998">C++ 1998/2003</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.1998.status">Implementation Status</a></span></dt><dt><span class="section"><a href="status.html#iso.1998.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.2011">C++ 2011</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.2011.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.tr1">C++ TR1</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.tr1.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.tr24733">C++ TR 24733</a></span></dt></dl></dd><dt><span class="section"><a href="license.html">License</a></span></dt><dd><dl><dt><span class="section"><a href="license.html#manual.intro.status.license.gpl">The Code: GPL</a></span></dt><dt><span class="section"><a href="license.html#manual.intro.status.license.fdl">The Documentation: GPL, FDL</a></span></dt></dl></dd><dt><span class="section"><a href="bugs.html">Bugs</a></span></dt><dd><dl><dt><span class="section"><a href="bugs.html#manual.intro.status.bugs.impl">Implementation Bugs</a></span></dt><dt><span class="section"><a href="bugs.html#manual.intro.status.bugs.iso">Standard Bugs</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.status.iso"></a>Implementation Status</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="status.iso.1998"></a>C++ 1998/2003</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="iso.1998.status"></a>Implementation Status</h4></div></div></div><p>

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This status table is based on the table of contents of ISO/IEC 14882:2003.

1313

</p><p>

1314

This page describes the C++ support in mainline GCC SVN, not in any

1315

particular release.

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-</p><div class="table"><a id="idp452240"></a><p class="title"><strong>Table 1.1. C++ 1998/2003 Implementation Status</strong></p><div class="table-contents"><table summary="C++ 1998/2003 Implementation Status" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Section</th><th align="left">Description</th><th align="left">Status</th><th align="left">Comments</th></tr></thead><tbody><tr><td align="left">

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+</p><div class="table"><a id="idm270008034928"></a><p class="title"><strong>Table 1.1. C++ 1998/2003 Implementation Status</strong></p><div class="table-contents"><table summary="C++ 1998/2003 Implementation Status" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Section</th><th align="left">Description</th><th align="left">Status</th><th align="left">Comments</th></tr></thead><tbody><tr><td align="left">

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</td><td colspan="3" align="left">

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<span class="emphasis"><em>Language support</em></span>

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</p><p>

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This page describes the C++11 support in mainline GCC SVN, not in any

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-</p><div class="table"><a id="idp8670848"></a><p class="title"><strong>Table 1.2. C++ 2011 Implementation Status</strong></p><div class="table-contents"><table summary="C++ 2011 Implementation Status" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Section</th><th align="left">Description</th><th align="left">Status</th><th align="left">Comments</th></tr></thead><tbody><tr><td align="left">

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+</p><div class="table"><a id="idm270007982624"></a><p class="title"><strong>Table 1.2. C++ 2011 Implementation Status</strong></p><div class="table-contents"><table summary="C++ 2011 Implementation Status" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Section</th><th align="left">Description</th><th align="left">Status</th><th align="left">Comments</th></tr></thead><tbody><tr><td align="left">

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</td><td colspan="3" align="left">

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<span class="emphasis"><em>Language support</em></span>

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@@ -183,7 +183,7 @@

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is_trivially_copy_constructible, is_trivially_move_constructible,

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is_trivially_assignable, is_trivially_default_assignable,

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is_trivially_copy_assignable, is_trivially_move_assignable

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- </td></tr><tr><td align="left">20.9.5</td><td align="left">Type property queries</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.9.6</td><td align="left">Relationships between types</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.9.7</td><td align="left">Transformations between types</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.9.7.1</td><td align="left">Const-volatile modifications</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.9.7.2</td><td align="left">Reference modifications</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.9.7.3</td><td align="left">Sign modifications</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.9.7.4</td><td align="left">Array modifications</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.9.7.5</td><td align="left">Pointer modifications</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.9.7.6</td><td align="left">Other transformations</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.10</td><td align="left">Compile-time rational arithmetic</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.10.1</td><td align="left">In general</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.10.2</td><td align="left">Header <code class="code"><ratio></code> synopsis</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.10.3</td><td align="left">Class template <code class="code">ratio</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.10.4</td><td align="left">Arithmetic on <code class="code">ratio</code>s</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.10.5</td><td align="left">Comparison of <code class="code">ratio</code>s</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.10.6</td><td align="left">SI types for <code class="code">ratio</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11</td><td align="left">Time utilities</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.11.3</td><td align="left">Clock requirements</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11.4</td><td align="left">Time-related traits</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.11.4.1</td><td align="left"><code class="code">treat_as_floating_point</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11.4.2</td><td align="left"><code class="code">duration_values</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11.4.3</td><td align="left">Specializations of <code class="code">common_type</code></td><td align="left">Y</td><td align="left"> </td></tr><tr bgcolor="#B0B0B0"><td align="left">20.11.5</td><td align="left">Class template <code class="code">duration</code></td><td align="left">Partial</td><td align="left">Missing constexpr for non-member arithmetic operations</td></tr><tr><td align="left">20.11.6</td><td align="left">Class template <code class="code">time_point</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11.7</td><td align="left">Clocks</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.11.7.1</td><td align="left">Class <code class="code">system_clock</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11.7.2</td><td align="left">Class <code class="code">steady_clock</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11.7.3</td><td align="left">Class <code class="code">high_resolution_clock</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11.8</td><td align="left">Date and time functions</td><td align="left">Y</td><td align="left"> </td></tr><tr bgcolor="#B0B0B0"><td align="left">20.12</td><td align="left">Scoped allocator adaptor</td><td align="left">Partial</td><td align="left"> </td></tr><tr><td align="left">20.12.1</td><td align="left">Header <code class="code"><scoped_allocator></code> synopsis</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.12.2</td><td align="left">Scoped allocator adaptor member types</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.12.3</td><td align="left">Scoped allocator adaptor constructors</td><td align="left">Y</td><td align="left"> </td></tr><tr bgcolor="#B0B0B0"><td align="left">20.12.4</td><td align="left">Scoped allocator adaptor members</td><td align="left">Partial</td><td align="left">OUTERMOST is not recursive.</td></tr><tr><td align="left">20.12.5</td><td align="left">Scoped allocator operators</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.13</td><td align="left">Class <code class="code">type_index</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">

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+ </td></tr><tr><td align="left">20.9.5</td><td align="left">Type property queries</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.9.6</td><td align="left">Relationships between types</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.9.7</td><td align="left">Transformations between types</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.9.7.1</td><td align="left">Const-volatile modifications</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.9.7.2</td><td align="left">Reference modifications</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.9.7.3</td><td align="left">Sign modifications</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.9.7.4</td><td align="left">Array modifications</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.9.7.5</td><td align="left">Pointer modifications</td><td align="left">Y</td><td align="left"> </td></tr><tr bgcolor="#B0B0B0"><td align="left">20.9.7.6</td><td align="left">Other transformations</td><td align="left">Partial</td><td align="left">Missing <code class="code">aligned_union</code>.</td></tr><tr><td align="left">20.10</td><td align="left">Compile-time rational arithmetic</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.10.1</td><td align="left">In general</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.10.2</td><td align="left">Header <code class="code"><ratio></code> synopsis</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.10.3</td><td align="left">Class template <code class="code">ratio</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.10.4</td><td align="left">Arithmetic on <code class="code">ratio</code>s</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.10.5</td><td align="left">Comparison of <code class="code">ratio</code>s</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.10.6</td><td align="left">SI types for <code class="code">ratio</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11</td><td align="left">Time utilities</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.11.3</td><td align="left">Clock requirements</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11.4</td><td align="left">Time-related traits</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.11.4.1</td><td align="left"><code class="code">treat_as_floating_point</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11.4.2</td><td align="left"><code class="code">duration_values</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11.4.3</td><td align="left">Specializations of <code class="code">common_type</code></td><td align="left">Y</td><td align="left"> </td></tr><tr bgcolor="#B0B0B0"><td align="left">20.11.5</td><td align="left">Class template <code class="code">duration</code></td><td align="left">Partial</td><td align="left">Missing constexpr for non-member arithmetic operations</td></tr><tr><td align="left">20.11.6</td><td align="left">Class template <code class="code">time_point</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11.7</td><td align="left">Clocks</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.11.7.1</td><td align="left">Class <code class="code">system_clock</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11.7.2</td><td align="left">Class <code class="code">steady_clock</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11.7.3</td><td align="left">Class <code class="code">high_resolution_clock</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11.8</td><td align="left">Date and time functions</td><td align="left">Y</td><td align="left"> </td></tr><tr bgcolor="#B0B0B0"><td align="left">20.12</td><td align="left">Scoped allocator adaptor</td><td align="left">Partial</td><td align="left"> </td></tr><tr><td align="left">20.12.1</td><td align="left">Header <code class="code"><scoped_allocator></code> synopsis</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.12.2</td><td align="left">Scoped allocator adaptor member types</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.12.3</td><td align="left">Scoped allocator adaptor constructors</td><td align="left">Y</td><td align="left"> </td></tr><tr bgcolor="#B0B0B0"><td align="left">20.12.4</td><td align="left">Scoped allocator adaptor members</td><td align="left">Partial</td><td align="left">OUTERMOST is not recursive.</td></tr><tr><td align="left">20.12.5</td><td align="left">Scoped allocator operators</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.13</td><td align="left">Class <code class="code">type_index</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">

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</td><td colspan="3" align="left">

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<span class="emphasis"><em>Strings</em></span>

1339

@@ -302,7 +302,7 @@

1340

</p><p>

1341

This page describes the TR1 support in mainline GCC SVN, not in any particular

1342

release.

1343

-</p><div class="table"><a id="idp7483200"></a><p class="title"><strong>Table 1.3. C++ TR1 Implementation Status</strong></p><div class="table-contents"><table summary="C++ TR1 Implementation Status" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Section</th><th align="left">Description</th><th align="left">Status</th><th align="left">Comments</th></tr></thead><tbody><tr><td align="left"><span class="emphasis"><em>2</em></span></td><td colspan="3" align="left"><span class="emphasis"><em>General Utilities</em></span></td></tr><tr><td align="left">2.1</td><td align="left">Reference wrappers</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">2.1.1</td><td align="left">Additions to header <code class="code"><functional></code> synopsis</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.1.2</td><td align="left">Class template <code class="code">reference_wrapper</code></td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">2.1.2.1</td><td align="left"><code class="code">reference_wrapper</code> construct/copy/destroy</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.1.2.2</td><td align="left"><code class="code">reference_wrapper</code> assignment</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.1.2.3</td><td align="left"><code class="code">reference_wrapper</code> access</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.1.2.4</td><td align="left"><code class="code">reference_wrapper</code> invocation</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.1.2.5</td><td align="left"><code class="code">reference_wrapper</code> helper functions</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.2</td><td align="left">Smart pointers</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">2.2.1</td><td align="left">Additions to header <code class="code"><memory></code> synopsis</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.2.2</td><td align="left">Class <code class="code">bad_weak_ptr</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.2.3</td><td align="left">Class template <code class="code">shared_ptr</code></td><td align="left"> </td><td align="left">

1344

+</p><div class="table"><a id="idm270006687472"></a><p class="title"><strong>Table 1.3. C++ TR1 Implementation Status</strong></p><div class="table-contents"><table summary="C++ TR1 Implementation Status" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Section</th><th align="left">Description</th><th align="left">Status</th><th align="left">Comments</th></tr></thead><tbody><tr><td align="left"><span class="emphasis"><em>2</em></span></td><td colspan="3" align="left"><span class="emphasis"><em>General Utilities</em></span></td></tr><tr><td align="left">2.1</td><td align="left">Reference wrappers</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">2.1.1</td><td align="left">Additions to header <code class="code"><functional></code> synopsis</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.1.2</td><td align="left">Class template <code class="code">reference_wrapper</code></td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">2.1.2.1</td><td align="left"><code class="code">reference_wrapper</code> construct/copy/destroy</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.1.2.2</td><td align="left"><code class="code">reference_wrapper</code> assignment</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.1.2.3</td><td align="left"><code class="code">reference_wrapper</code> access</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.1.2.4</td><td align="left"><code class="code">reference_wrapper</code> invocation</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.1.2.5</td><td align="left"><code class="code">reference_wrapper</code> helper functions</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.2</td><td align="left">Smart pointers</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">2.2.1</td><td align="left">Additions to header <code class="code"><memory></code> synopsis</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.2.2</td><td align="left">Class <code class="code">bad_weak_ptr</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.2.3</td><td align="left">Class template <code class="code">shared_ptr</code></td><td align="left"> </td><td align="left">

1345

<p>

1346

Uses code from

1347

<a class="link" href="http://www.boost.org/libs/smart_ptr/shared_ptr.htm" target="_top">boost::shared_ptr</a>.

1348

@@ -323,7 +323,7 @@

1349

</p><p>

1350

This page describes the TR 24733 support in mainline GCC SVN, not in any

1351

particular release.

1352

-</p><div class="table"><a id="idp12559072"></a><p class="title"><strong>Table 1.4. C++ TR 24733 Implementation Status</strong></p><div class="table-contents"><table summary="C++ TR 24733 Implementation Status" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Section</th><th align="left">Description</th><th align="left">Status</th><th align="left">Comments</th></tr></thead><tbody><tr><td align="left">

1353

+</p><div class="table"><a id="idm270002960368"></a><p class="title"><strong>Table 1.4. C++ TR 24733 Implementation Status</strong></p><div class="table-contents"><table summary="C++ TR 24733 Implementation Status" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Section</th><th align="left">Description</th><th align="left">Status</th><th align="left">Comments</th></tr></thead><tbody><tr><td align="left">

1354

1355

</td><td colspan="3" align="left">

1356

<span class="emphasis"><em>Introduction</em></span>

1357

Index: libstdc++-v3/doc/html/manual/profile_mode_devel.html

1358

===================================================================

1359

--- a/src/libstdc++-v3/doc/html/manual/profile_mode_devel.html (.../tags/gcc_4_8_2_release)

1360

+++ b/src/libstdc++-v3/doc/html/manual/profile_mode_devel.html (.../branches/gcc-4_8-branch)

1361

@@ -1,5 +1,5 @@

1362

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

1363

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Developer Information</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="prev" href="profile_mode_impl.html" title="Implementation Issues" /><link rel="next" href="profile_mode_diagnostics.html" title="Diagnostics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Developer Information</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="profile_mode_impl.html">Prev</a> </td><th width="60%" align="center">Chapter 19. Profile Mode</th><td width="20%" align="right"> <a accesskey="n" href="profile_mode_diagnostics.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.developer"></a>Developer Information</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.ext.profile_mode.developer.bigpic"></a>Big Picture</h3></div></div></div><p>The profile mode headers are included with

1364

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Developer Information</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="prev" href="profile_mode_impl.html" title="Implementation Issues" /><link rel="next" href="profile_mode_diagnostics.html" title="Diagnostics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Developer Information</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="profile_mode_impl.html">Prev</a> </td><th width="60%" align="center">Chapter 19. Profile Mode</th><td width="20%" align="right"> <a accesskey="n" href="profile_mode_diagnostics.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.developer"></a>Developer Information</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.ext.profile_mode.developer.bigpic"></a>Big Picture</h3></div></div></div><p>The profile mode headers are included with

1365

<code class="code">-D_GLIBCXX_PROFILE</code> through preprocessor directives in

1366

<code class="code">include/std/*</code>.

1367

</p><p>Instrumented implementations are provided in

1368

Index: libstdc++-v3/doc/html/manual/debug_mode_design.html

1369

===================================================================

1370

--- a/src/libstdc++-v3/doc/html/manual/debug_mode_design.html (.../tags/gcc_4_8_2_release)

1371

+++ b/src/libstdc++-v3/doc/html/manual/debug_mode_design.html (.../branches/gcc-4_8-branch)

1372

@@ -1,5 +1,5 @@

1373

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

1374

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="C++, library, debug" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="debug_mode.html" title="Chapter 17. Debug Mode" /><link rel="prev" href="debug_mode_using.html" title="Using" /><link rel="next" href="parallel_mode.html" title="Chapter 18. Parallel Mode" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="debug_mode_using.html">Prev</a> </td><th width="60%" align="center">Chapter 17. Debug Mode</th><td width="20%" align="right"> <a accesskey="n" href="parallel_mode.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.debug_mode.design"></a>Design</h2></div></div></div><p>

1375

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, debug" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="debug_mode.html" title="Chapter 17. Debug Mode" /><link rel="prev" href="debug_mode_using.html" title="Using" /><link rel="next" href="parallel_mode.html" title="Chapter 18. Parallel Mode" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="debug_mode_using.html">Prev</a> </td><th width="60%" align="center">Chapter 17. Debug Mode</th><td width="20%" align="right"> <a accesskey="n" href="parallel_mode.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.debug_mode.design"></a>Design</h2></div></div></div><p>

1376

</p><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="debug_mode.design.goals"></a>Goals</h3></div></div></div><p>

1377

</p><p> The libstdc++ debug mode replaces unsafe (but efficient) standard

1378

containers and iterators with semantically equivalent safe standard

1379

@@ -391,7 +391,7 @@

1380

</p><p> There are several existing implementations of debug modes for C++

1381

standard library implementations, although none of them directly

1382

supports debugging for programs using libstdc++. The existing

1383

- implementations include:</p><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p><a class="link" href="http://www.mathcs.sjsu.edu/faculty/horstman/safestl.html" target="_top">SafeSTL</a>:

1384

+ implementations include:</p><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p><a class="link" href="http://www.cs.sjsu.edu/faculty/horstman/safestl.html" target="_top">SafeSTL</a>:

1385

SafeSTL was the original debugging version of the Standard Template

1386

Library (STL), implemented by Cay S. Horstmann on top of the

1387

Hewlett-Packard STL. Though it inspired much work in this area, it

1388

Index: libstdc++-v3/doc/html/manual/policy_data_structures_design.html

1389

===================================================================

1390

--- a/src/libstdc++-v3/doc/html/manual/policy_data_structures_design.html (.../tags/gcc_4_8_2_release)

1391

+++ b/src/libstdc++-v3/doc/html/manual/policy_data_structures_design.html (.../branches/gcc-4_8-branch)

1392

@@ -1,5 +1,5 @@

1393

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

1394

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, policy, container, data, structure, associated, tree, trie, hash, metaprogramming" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="policy_data_structures.html" title="Chapter 22. Policy-Based Data Structures" /><link rel="prev" href="policy_data_structures_using.html" title="Using" /><link rel="next" href="policy_based_data_structures_test.html" title="Testing" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="policy_data_structures_using.html">Prev</a> </td><th width="60%" align="center">Chapter 22. Policy-Based Data Structures</th><td width="20%" align="right"> <a accesskey="n" href="policy_based_data_structures_test.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="containers.pbds.design"></a>Design</h2></div></div></div><p></p><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="pbds.design.concepts"></a>Concepts</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="pbds.design.concepts.null_type"></a>Null Policy Classes</h4></div></div></div><p>

1395

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, policy, container, data, structure, associated, tree, trie, hash, metaprogramming" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="policy_data_structures.html" title="Chapter 22. Policy-Based Data Structures" /><link rel="prev" href="policy_data_structures_using.html" title="Using" /><link rel="next" href="policy_based_data_structures_test.html" title="Testing" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="policy_data_structures_using.html">Prev</a> </td><th width="60%" align="center">Chapter 22. Policy-Based Data Structures</th><td width="20%" align="right"> <a accesskey="n" href="policy_based_data_structures_test.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="containers.pbds.design"></a>Design</h2></div></div></div><p></p><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="pbds.design.concepts"></a>Concepts</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="pbds.design.concepts.null_type"></a>Null Policy Classes</h4></div></div></div><p>

1396

Associative containers are typically parametrized by various

1397

policies. For example, a hash-based associative container is

1398

parametrized by a hash-functor, transforming each key into an

1399

@@ -170,7 +170,7 @@

1400

naturally; collision-chaining hash tables (label B) store

1401

equivalent-key values in the same bucket, the bucket can be

1402

arranged so that equivalent-key values are consecutive.

1403

- </p><div class="figure"><a id="idp18000448"></a><p class="title"><strong>Figure 22.8. Non-unique Mapping Standard Containers</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_embedded_lists_1.png" align="middle" alt="Non-unique Mapping Standard Containers" /></div></div></div><br class="figure-break" /><p>

1404

+ </p><div class="figure"><a id="idm269997530416"></a><p class="title"><strong>Figure 22.8. Non-unique Mapping Standard Containers</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_embedded_lists_1.png" align="middle" alt="Non-unique Mapping Standard Containers" /></div></div></div><br class="figure-break" /><p>

1405

Put differently, the standards' non-unique mapping

1406

associative-containers are associative containers that map

1407

primary keys to linked lists that are embedded into the

1408

@@ -252,7 +252,7 @@

1409

first graphic above. Labels A and B, respectively. Each shaded

1410

box represents some size-type or secondary

1411

associative-container.

1412

- </p><div class="figure"><a id="idp18023952"></a><p class="title"><strong>Figure 22.10. Non-unique Mapping Containers</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_embedded_lists_3.png" align="middle" alt="Non-unique Mapping Containers" /></div></div></div><br class="figure-break" /><p>

1413

+ </p><div class="figure"><a id="idm269997506912"></a><p class="title"><strong>Figure 22.10. Non-unique Mapping Containers</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_embedded_lists_3.png" align="middle" alt="Non-unique Mapping Containers" /></div></div></div><br class="figure-break" /><p>

1414

In the first example above, then, one would use an associative

1415

container mapping each user to an associative container which

1416

maps each application id to a start time (see

1417

@@ -305,7 +305,7 @@

1418

shows invariants for order-preserving containers: point-type

1419

iterators are synonymous with range-type iterators.

1420

Orthogonally, <span class="emphasis"><em>C</em></span>shows invariants for "set"

1421

- containers: iterators are synonymous with const iterators.</p><div class="figure"><a id="idp18043824"></a><p class="title"><strong>Figure 22.11. Point Iterator Hierarchy</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_point_iterator_hierarchy.png" align="middle" alt="Point Iterator Hierarchy" /></div></div></div><br class="figure-break" /><p>Note that point-type iterators in self-organizing containers

1422

+ containers: iterators are synonymous with const iterators.</p><div class="figure"><a id="idm269997487104"></a><p class="title"><strong>Figure 22.11. Point Iterator Hierarchy</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_point_iterator_hierarchy.png" align="middle" alt="Point Iterator Hierarchy" /></div></div></div><br class="figure-break" /><p>Note that point-type iterators in self-organizing containers

1423

(hash-based associative containers) lack movement

1424

operators, such as <code class="literal">operator++</code> - in fact, this

1425

is the reason why this library differentiates from the standard C++ librarys

1426

@@ -344,7 +344,7 @@

1427

to the question of whether point-type iterators and range-type

1428

iterators are valid. The graphic below shows tags corresponding to

1429

different types of invalidation guarantees.

1430

- </p><div class="figure"><a id="idp18057168"></a><p class="title"><strong>Figure 22.12. Invalidation Guarantee Tags Hierarchy</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_invalidation_tag_hierarchy.png" align="middle" alt="Invalidation Guarantee Tags Hierarchy" /></div></div></div><br class="figure-break" /><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p>

1431

+ </p><div class="figure"><a id="idm269997473760"></a><p class="title"><strong>Figure 22.12. Invalidation Guarantee Tags Hierarchy</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_invalidation_tag_hierarchy.png" align="middle" alt="Invalidation Guarantee Tags Hierarchy" /></div></div></div><br class="figure-break" /><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p>

1432

<code class="classname">basic_invalidation_guarantee</code>

1433

corresponds to a basic guarantee that a point-type iterator,

1434

a found pointer, or a found reference, remains valid as long

1435

@@ -428,7 +428,7 @@

1436

</p><p>

1437

This library contains a container tag hierarchy corresponding to the

1438

diagram below.

1439

- </p><div class="figure"><a id="idp18087392"></a><p class="title"><strong>Figure 22.13. Container Tag Hierarchy</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_container_tag_hierarchy.png" align="middle" alt="Container Tag Hierarchy" /></div></div></div><br class="figure-break" /><p>

1440

+ </p><div class="figure"><a id="idm269997443664"></a><p class="title"><strong>Figure 22.13. Container Tag Hierarchy</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_container_tag_hierarchy.png" align="middle" alt="Container Tag Hierarchy" /></div></div></div><br class="figure-break" /><p>

1441

Given any container <span class="type">Cntnr</span>, the tag of

1442

the underlying data structure can be found via <code class="literal">typename

1443

Cntnr::container_category</code>.

1444

@@ -487,7 +487,7 @@

1445

collision-chaining container, except for the following.</p><div class="orderedlist"><ol class="orderedlist" type="1"><li class="listitem"><p><code class="classname">Comb_Probe_Fn</code> describes how to transform a probe

1446

sequence into a sequence of positions within the table.</p></li><li class="listitem"><p><code class="classname">Probe_Fn</code> describes a probe sequence policy.</p></li></ol></div><p>Some of the default template values depend on the values of

1447

other parameters, and are explained below.</p></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="container.hash.details"></a>Details</h5></div></div></div><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="container.hash.details.hash_policies"></a>Hash Policies</h6></div></div></div><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="details.hash_policies.general"></a>General</h6></div></div></div><p>Following is an explanation of some functions which hashing

1448

- involves. The graphic below illustrates the discussion.</p><div class="figure"><a id="idp18127536"></a><p class="title"><strong>Figure 22.14. Hash functions, ranged-hash functions, and

1449

+ involves. The graphic below illustrates the discussion.</p><div class="figure"><a id="idm269997403584"></a><p class="title"><strong>Figure 22.14. Hash functions, ranged-hash functions, and

1450

range-hashing functions</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_hash_ranged_hash_range_hashing_fns.png" align="middle" alt="Hash functions, ranged-hash functions, and range-hashing functions" /></div></div></div><br class="figure-break" /><p>Let U be a domain (e.g., the integers, or the

1451

strings of 3 characters). A hash-table algorithm needs to map

1452

elements of U "uniformly" into the range [0,..., m -

1453

@@ -504,7 +504,7 @@

1454

Z<sub>+</sub>,</p><p>which maps a non-negative hash value, and a non-negative

1455

range upper-bound into a non-negative integral in the range

1456

between 0 (inclusive) and the range upper bound (exclusive),

1457

- i.e., for any r in Z<sub>+</sub>,</p><p>0 ≤ g(r, m) ≤ m - 1</p><p>The resulting ranged-hash function, is</p><div class="equation"><a id="idp18141344"></a><p class="title"><strong>Equation 22.1. Ranged Hash Function</strong></p><div class="equation-contents"><span class="mathphrase">

1458

+ i.e., for any r in Z<sub>+</sub>,</p><p>0 ≤ g(r, m) ≤ m - 1</p><p>The resulting ranged-hash function, is</p><div class="equation"><a id="idm269997389776"></a><p class="title"><strong>Equation 22.1. Ranged Hash Function</strong></p><div class="equation-contents"><span class="mathphrase">

1459

f(u , m) = g(h(u), m)

1460

</span></div></div><br class="equation-break" /><p>From the above, it is obvious that given g and

1461

h, f can always be composed (however the converse

1462

@@ -524,7 +524,7 @@

1463

transforming the sequence of hash values into a sequence of

1464

positions.</p></div><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="details.hash_policies.range"></a>Range Hashing</h6></div></div></div><p>Some common choices for range-hashing functions are the

1465

division, multiplication, and middle-square methods (<a class="xref" href="policy_data_structures.html#biblio.knuth98sorting" title="The Art of Computer Programming - Sorting and Searching">[biblio.knuth98sorting]</a>), defined

1466

- as</p><div class="equation"><a id="idp18147232"></a><p class="title"><strong>Equation 22.2. Range-Hashing, Division Method</strong></p><div class="equation-contents"><span class="mathphrase">

1467

+ as</p><div class="equation"><a id="idm269997383888"></a><p class="title"><strong>Equation 22.2. Range-Hashing, Division Method</strong></p><div class="equation-contents"><span class="mathphrase">

1468

g(r, m) = r mod m

1469

</span></div></div><br class="equation-break" /><p>g(r, m) = ⌈ u/v ( a r mod v ) ⌉</p><p>and</p><p>g(r, m) = ⌈ u/v ( r<sup>2</sup> mod v ) ⌉</p><p>respectively, for some positive integrals u and

1470

v (typically powers of 2), and some a. Each of

1471

@@ -535,9 +535,9 @@

1472

implement using the low

1473

level % (modulo) operation (for any m), or the

1474

low level & (bit-mask) operation (for the case where

1475

- m is a power of 2), i.e.,</p><div class="equation"><a id="idp18151744"></a><p class="title"><strong>Equation 22.3. Division via Prime Modulo</strong></p><div class="equation-contents"><span class="mathphrase">

1476

+ m is a power of 2), i.e.,</p><div class="equation"><a id="idm269997379376"></a><p class="title"><strong>Equation 22.3. Division via Prime Modulo</strong></p><div class="equation-contents"><span class="mathphrase">

1477

g(r, m) = r % m

1478

- </span></div></div><br class="equation-break" /><p>and</p><div class="equation"><a id="idp18153568"></a><p class="title"><strong>Equation 22.4. Division via Bit Mask</strong></p><div class="equation-contents"><span class="mathphrase">

1479

+ </span></div></div><br class="equation-break" /><p>and</p><div class="equation"><a id="idm269997377552"></a><p class="title"><strong>Equation 22.4. Division via Bit Mask</strong></p><div class="equation-contents"><span class="mathphrase">

1480

g(r, m) = r & m - 1, (with m =

1481

2<sup>k</sup> for some k)

1482

</span></div></div><br class="equation-break" /><p>respectively.</p><p>The % (modulo) implementation has the advantage that for

1483

@@ -563,7 +563,7 @@

1484

s = [ s<sub>0</sub>,..., s<sub>t - 1</sub>]

1485

</p><p>be a string of t characters, each of which is from

1486

domain S. Consider the following ranged-hash

1487

- function:</p><div class="equation"><a id="idp18163200"></a><p class="title"><strong>Equation 22.5.

1488

+ function:</p><div class="equation"><a id="idm269997367984"></a><p class="title"><strong>Equation 22.5.

1489

A Standard String Hash Function

1490

</strong></p><div class="equation-contents"><span class="mathphrase">

1491

f<sub>1</sub>(s, m) = ∑ <sub>i =

1492

@@ -575,7 +575,7 @@

1493

of a long DNA sequence (and so S = {'A', 'C', 'G',

1494

'T'}). In this case, scanning the entire string might be

1495

prohibitively expensive. A possible alternative might be to use

1496

- only the first k characters of the string, where</p><p>|S|<sup>k</sup> ≥ m ,</p><p>i.e., using the hash function</p><div class="equation"><a id="idp18169344"></a><p class="title"><strong>Equation 22.6.

1497

+ only the first k characters of the string, where</p><p>|S|<sup>k</sup> ≥ m ,</p><p>i.e., using the hash function</p><div class="equation"><a id="idm269997361840"></a><p class="title"><strong>Equation 22.6.

1498

Only k String DNA Hash

1499

</strong></p><div class="equation-contents"><span class="mathphrase">

1500

f<sub>2</sub>(s, m) = ∑ <sub>i

1501

@@ -606,12 +606,12 @@

1502

the container transforms the key into a non-negative integral

1503

using the hash functor (points B and C), and transforms the

1504

result into a position using the combining functor (points D

1505

- and E).</p><div class="figure"><a id="idp18191968"></a><p class="title"><strong>Figure 22.15. Insert hash sequence diagram</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_hash_range_hashing_seq_diagram.png" align="middle" alt="Insert hash sequence diagram" /></div></div></div><br class="figure-break" /><p>If <code class="classname">cc_hash_table</code>'s

1506

+ and E).</p><div class="figure"><a id="idm269997339216"></a><p class="title"><strong>Figure 22.15. Insert hash sequence diagram</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_hash_range_hashing_seq_diagram.png" align="middle" alt="Insert hash sequence diagram" /></div></div></div><br class="figure-break" /><p>If <code class="classname">cc_hash_table</code>'s

1507

hash-functor, <code class="classname">Hash_Fn</code> is instantiated by <code class="classname">null_type</code> , then <code class="classname">Comb_Hash_Fn</code> is taken to be

1508

a ranged-hash function. The graphic below shows an <code class="function">insert</code> sequence

1509

diagram. The user inserts an element (point A), the container

1510

transforms the key into a position using the combining functor

1511

- (points B and C).</p><div class="figure"><a id="idp18199024"></a><p class="title"><strong>Figure 22.16. Insert hash sequence diagram with a null policy</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_hash_range_hashing_seq_diagram2.png" align="middle" alt="Insert hash sequence diagram with a null policy" /></div></div></div><br class="figure-break" /></div><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="hash_policies.implementation.probe"></a>

1512

+ (points B and C).</p><div class="figure"><a id="idm269997332160"></a><p class="title"><strong>Figure 22.16. Insert hash sequence diagram with a null policy</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_hash_range_hashing_seq_diagram2.png" align="middle" alt="Insert hash sequence diagram with a null policy" /></div></div></div><br class="figure-break" /></div><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="hash_policies.implementation.probe"></a>

1513

Probing tables

1514

</h6></div></div></div><p><code class="classname">gp_hash_table</code> is parametrized by

1515

<code class="classname">Hash_Fn</code>, <code class="classname">Probe_Fn</code>,

1516

@@ -634,7 +634,7 @@

1517

a linear probe and a quadratic probe function,

1518

respectively.</p></li></ol></div><p>

1519

The graphic below shows the relationships.

1520

- </p><div class="figure"><a id="idp18215840"></a><p class="title"><strong>Figure 22.17. Hash policy class diagram</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_hash_policy_cd.png" align="middle" alt="Hash policy class diagram" /></div></div></div><br class="figure-break" /></div></div></div><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="container.hash.details.resize_policies"></a>Resize Policies</h6></div></div></div><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="resize_policies.general"></a>General</h6></div></div></div><p>Hash-tables, as opposed to trees, do not naturally grow or

1521

+ </p><div class="figure"><a id="idm269997315408"></a><p class="title"><strong>Figure 22.17. Hash policy class diagram</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_hash_policy_cd.png" align="middle" alt="Hash policy class diagram" /></div></div></div><br class="figure-break" /></div></div></div><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="container.hash.details.resize_policies"></a>Resize Policies</h6></div></div></div><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="resize_policies.general"></a>General</h6></div></div></div><p>Hash-tables, as opposed to trees, do not naturally grow or

1522

shrink. It is necessary to specify policies to determine how

1523

and when a hash table should change its size. Usually, resize

1524

policies can be decomposed into orthogonal policies:</p><div class="orderedlist"><ol class="orderedlist" type="1"><li class="listitem"><p>A size policy indicating how a hash table

1525

@@ -667,10 +667,10 @@

1526

and some load factor be denoted by Α. We would like to

1527

calculate the minimal length of k, such that if there were Α

1528

m elements in the hash table, a probe sequence of length k would

1529

- be found with probability at most 1/m.</p><div class="figure"><a id="idp18234944"></a><p class="title"><strong>Figure 22.18. Balls and bins</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_balls_and_bins.png" align="middle" alt="Balls and bins" /></div></div></div><br class="figure-break" /><p>Denote the probability that a probe sequence of length

1530

+ be found with probability at most 1/m.</p><div class="figure"><a id="idm269997296368"></a><p class="title"><strong>Figure 22.18. Balls and bins</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_balls_and_bins.png" align="middle" alt="Balls and bins" /></div></div></div><br class="figure-break" /><p>Denote the probability that a probe sequence of length

1531

k appears in bin i by p<sub>i</sub>, the

1532

length of the probe sequence of bin i by

1533

- l<sub>i</sub>, and assume uniform distribution. Then</p><div class="equation"><a id="idp18240448"></a><p class="title"><strong>Equation 22.7.

1534

+ l<sub>i</sub>, and assume uniform distribution. Then</p><div class="equation"><a id="idm269997290864"></a><p class="title"><strong>Equation 22.7.

1535

Probability of Probe Sequence of Length k

1536

</strong></p><div class="equation-contents"><span class="mathphrase">

1537

p<sub>1</sub> =

1538

@@ -684,7 +684,7 @@

1539

l<sub>i</sub> are negatively-dependent

1540

(<a class="xref" href="policy_data_structures.html#biblio.dubhashi98neg" title="Balls and bins: A study in negative dependence">[biblio.dubhashi98neg]</a>)

1541

. Let

1542

- I(.) denote the indicator function. Then</p><div class="equation"><a id="idp18247216"></a><p class="title"><strong>Equation 22.8.

1543

+ I(.) denote the indicator function. Then</p><div class="equation"><a id="idm269997284096"></a><p class="title"><strong>Equation 22.8.

1544

Probability Probe Sequence in Some Bin

1545

</strong></p><div class="equation-contents"><span class="mathphrase">

1546

P( exists<sub>i</sub> l<sub>i</sub> ≥ k ) =

1547

@@ -723,7 +723,7 @@

1548

a resize is needed, and if so, what is the new size (points D

1549

to G); following the resize, it notifies the policy that a

1550

resize has completed (point H); finally, the element is

1551

- inserted, and the policy notified (point I).</p><div class="figure"><a id="idp18265728"></a><p class="title"><strong>Figure 22.19. Insert resize sequence diagram</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_insert_resize_sequence_diagram1.png" align="middle" alt="Insert resize sequence diagram" /></div></div></div><br class="figure-break" /><p>In practice, a resize policy can be usually orthogonally

1552

+ inserted, and the policy notified (point I).</p><div class="figure"><a id="idm269997265648"></a><p class="title"><strong>Figure 22.19. Insert resize sequence diagram</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_insert_resize_sequence_diagram1.png" align="middle" alt="Insert resize sequence diagram" /></div></div></div><br class="figure-break" /><p>In practice, a resize policy can be usually orthogonally

1553

decomposed to a size policy and a trigger policy. Consequently,

1554

the library contains a single class for instantiating a resize

1555

policy: <code class="classname">hash_standard_resize_policy</code>

1556

@@ -732,8 +732,8 @@

1557

both, and acts as a standard delegate (<a class="xref" href="policy_data_structures.html#biblio.gof" title="Design Patterns - Elements of Reusable Object-Oriented Software">[biblio.gof]</a>)

1558

to these policies.</p><p>The two graphics immediately below show sequence diagrams

1559

illustrating the interaction between the standard resize policy

1560

- and its trigger and size policies, respectively.</p><div class="figure"><a id="idp18273504"></a><p class="title"><strong>Figure 22.20. Standard resize policy trigger sequence

1561

- diagram</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_insert_resize_sequence_diagram2.png" align="middle" alt="Standard resize policy trigger sequence diagram" /></div></div></div><br class="figure-break" /><div class="figure"><a id="idp18277664"></a><p class="title"><strong>Figure 22.21. Standard resize policy size sequence

1562

+ and its trigger and size policies, respectively.</p><div class="figure"><a id="idm269997257872"></a><p class="title"><strong>Figure 22.20. Standard resize policy trigger sequence

1563

+ diagram</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_insert_resize_sequence_diagram2.png" align="middle" alt="Standard resize policy trigger sequence diagram" /></div></div></div><br class="figure-break" /><div class="figure"><a id="idm269997253712"></a><p class="title"><strong>Figure 22.21. Standard resize policy size sequence

1564

diagram</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_insert_resize_sequence_diagram3.png" align="middle" alt="Standard resize policy size sequence diagram" /></div></div></div><br class="figure-break" /></div><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="resize_policies.impl.predefined"></a>Predefined Policies</h6></div></div></div><p>The library includes the following

1565

instantiations of size and trigger policies:</p><div class="orderedlist"><ol class="orderedlist" type="1"><li class="listitem"><p><code class="classname">hash_load_check_resize_trigger</code>

1566

implements a load check trigger policy.</p></li><li class="listitem"><p><code class="classname">cc_hash_max_collision_check_resize_trigger</code>

1567

@@ -876,7 +876,7 @@

1568

each node, and maintains node invariants (see <a class="xref" href="policy_data_structures.html#biblio.clrs2001" title="Introduction to Algorithms, 2nd edition">[biblio.clrs2001]</a>.) The first stores in

1569

each node the size of the sub-tree rooted at the node; the

1570

second stores at each node the maximal endpoint of the

1571

- intervals at the sub-tree rooted at the node.</p><div class="figure"><a id="idp18355696"></a><p class="title"><strong>Figure 22.22. Tree node invariants</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_tree_node_invariants.png" align="middle" alt="Tree node invariants" /></div></div></div><br class="figure-break" /><p>Supporting such trees is difficult for a number of

1572

+ intervals at the sub-tree rooted at the node.</p><div class="figure"><a id="idm269997175616"></a><p class="title"><strong>Figure 22.22. Tree node invariants</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_tree_node_invariants.png" align="middle" alt="Tree node invariants" /></div></div></div><br class="figure-break" /><p>Supporting such trees is difficult for a number of

1573

reasons:</p><div class="orderedlist"><ol class="orderedlist" type="1"><li class="listitem"><p>There must be a way to specify what a node's metadata

1574

should be (if any).</p></li><li class="listitem"><p>Various operations can invalidate node

1575

invariants. The graphic below shows how a right rotation,

1576

@@ -890,7 +890,7 @@

1577

metadata.</p></li><li class="listitem"><p>It is not feasible to know in advance which methods trees

1578

can support. Besides the usual <code class="classname">find</code> method, the

1579

first tree can support a <code class="classname">find_by_order</code> method, while

1580

- the second can support an <code class="classname">overlaps</code> method.</p></li></ol></div><div class="figure"><a id="idp18365136"></a><p class="title"><strong>Figure 22.23. Tree node invalidation</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_tree_node_invalidations.png" align="middle" alt="Tree node invalidation" /></div></div></div><br class="figure-break" /><p>These problems are solved by a combination of two means:

1581

+ the second can support an <code class="classname">overlaps</code> method.</p></li></ol></div><div class="figure"><a id="idm269997166176"></a><p class="title"><strong>Figure 22.23. Tree node invalidation</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_tree_node_invalidations.png" align="middle" alt="Tree node invalidation" /></div></div></div><br class="figure-break" /><p>These problems are solved by a combination of two means:

1582

node iterators, and template-template node updater

1583

parameters.</p><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="container.tree.node.iterators"></a>Node Iterators</h6></div></div></div><p>Each tree-based container defines two additional iterator

1584

types, <code class="classname">const_node_iterator</code>

1585

@@ -919,7 +919,7 @@

1586

<code class="classname">node_update</code> class, and publicly subclasses

1587

<code class="classname">node_update</code>. The graphic below shows this

1588

scheme, as well as some predefined policies (which are explained

1589

- below).</p><div class="figure"><a id="idp18378304"></a><p class="title"><strong>Figure 22.24. A tree and its update policy</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_tree_node_updator_policy_cd.png" align="middle" alt="A tree and its update policy" /></div></div></div><br class="figure-break" /><p><code class="classname">node_update</code> (an instantiation of

1590

+ below).</p><div class="figure"><a id="idm269997153072"></a><p class="title"><strong>Figure 22.24. A tree and its update policy</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_tree_node_updator_policy_cd.png" align="middle" alt="A tree and its update policy" /></div></div></div><br class="figure-break" /><p><code class="classname">node_update</code> (an instantiation of

1591

<code class="classname">Node_Update</code>) must define <code class="classname">metadata_type</code> as

1592

the type of metadata it requires. For order statistics,

1593

e.g., <code class="classname">metadata_type</code> might be <code class="classname">size_t</code>.

1594

@@ -938,7 +938,7 @@

1595

<code class="classname">nd_it</code>. For example, say node x in the

1596

graphic below label A has an invalid invariant, but its' children,

1597

y and z have valid invariants. After the invocation, all three

1598

- nodes should have valid invariants, as in label B.</p><div class="figure"><a id="idp18389968"></a><p class="title"><strong>Figure 22.25. Restoring node invariants</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_restoring_node_invariants.png" align="middle" alt="Restoring node invariants" /></div></div></div><br class="figure-break" /><p>When a tree operation might invalidate some node invariant,

1599

+ nodes should have valid invariants, as in label B.</p><div class="figure"><a id="idm269997141408"></a><p class="title"><strong>Figure 22.25. Restoring node invariants</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_restoring_node_invariants.png" align="middle" alt="Restoring node invariants" /></div></div></div><br class="figure-break" /><p>When a tree operation might invalidate some node invariant,

1600

it invokes this method in its <code class="classname">node_update</code> base to

1601

restore the invariant. For example, the graphic below shows

1602

an <code class="function">insert</code> operation (point A); the tree performs some

1603

@@ -946,7 +946,7 @@

1604

C, and D). (It is well known that any <code class="function">insert</code>,

1605

<code class="function">erase</code>, <code class="function">split</code> or <code class="function">join</code>, can restore

1606

all node invariants by a small number of node invariant updates (<a class="xref" href="policy_data_structures.html#biblio.clrs2001" title="Introduction to Algorithms, 2nd edition">[biblio.clrs2001]</a>)

1607

- .</p><div class="figure"><a id="idp18398144"></a><p class="title"><strong>Figure 22.26. Insert update sequence</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_update_seq_diagram.png" align="middle" alt="Insert update sequence" /></div></div></div><br class="figure-break" /><p>To complete the description of the scheme, three questions

1608

+ .</p><div class="figure"><a id="idm269997133232"></a><p class="title"><strong>Figure 22.26. Insert update sequence</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_update_seq_diagram.png" align="middle" alt="Insert update sequence" /></div></div></div><br class="figure-break" /><p>To complete the description of the scheme, three questions

1609

need to be answered:</p><div class="orderedlist"><ol class="orderedlist" type="1"><li class="listitem"><p>How can a tree which supports order statistics define a

1610

method such as <code class="classname">find_by_order</code>?</p></li><li class="listitem"><p>How can the node updater base access methods of the

1611

tree?</p></li><li class="listitem"><p>How can the following cyclic dependency be resolved?

1612

@@ -988,7 +988,7 @@

1613

node's metadata (this is halting reducible). In the graphic

1614

below, assume the shaded node is inserted. The tree would have

1615

to traverse the useless path shown to the root, applying

1616

- redundant updates all the way.</p></li></ol></div><div class="figure"><a id="idp18420400"></a><p class="title"><strong>Figure 22.27. Useless update path</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_rationale_null_node_updator.png" align="middle" alt="Useless update path" /></div></div></div><br class="figure-break" /><p>A null policy class, <code class="classname">null_node_update</code>

1617

+ redundant updates all the way.</p></li></ol></div><div class="figure"><a id="idm269997110976"></a><p class="title"><strong>Figure 22.27. Useless update path</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_rationale_null_node_updator.png" align="middle" alt="Useless update path" /></div></div></div><br class="figure-break" /><p>A null policy class, <code class="classname">null_node_update</code>

1618

solves both these problems. The tree detects that node

1619

invariants are irrelevant, and defines all accordingly.</p></div></div><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="container.tree.details.split"></a>Split and Join</h6></div></div></div><p>Tree-based containers support split and join methods.

1620

It is possible to split a tree so that it passes

1621

@@ -1071,7 +1071,7 @@

1622

sub-tree with leafs "a" and "as". The maximal common prefix is

1623

"a". The internal node contains, consequently, to const

1624

iterators, one pointing to <code class="varname">'a'</code>, and the other to

1625

- <code class="varname">'s'</code>.</p><div class="figure"><a id="idp18465088"></a><p class="title"><strong>Figure 22.28. A PATRICIA trie</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_pat_trie.png" align="middle" alt="A PATRICIA trie" /></div></div></div><br class="figure-break" /></div><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="container.trie.details.node"></a>Node Invariants</h6></div></div></div><p>Trie-based containers support node invariants, as do

1626

+ <code class="varname">'s'</code>.</p><div class="figure"><a id="idm269997066288"></a><p class="title"><strong>Figure 22.28. A PATRICIA trie</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_pat_trie.png" align="middle" alt="A PATRICIA trie" /></div></div></div><br class="figure-break" /></div><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="container.trie.details.node"></a>Node Invariants</h6></div></div></div><p>Trie-based containers support node invariants, as do

1627

tree-based containers. There are two minor

1628

differences, though, which, unfortunately, thwart sharing them

1629

sharing the same node-updating policies:</p><div class="orderedlist"><ol class="orderedlist" type="1"><li class="listitem"><p>A trie's <code class="classname">Node_Update</code> template-template

1630

@@ -1080,7 +1080,7 @@

1631

parametrized by <code class="classname">Cmp_Fn</code>.</p></li><li class="listitem"><p>Tree-based containers store values in all nodes, while

1632

trie-based containers (at least in this implementation) store

1633

values in leafs.</p></li></ol></div><p>The graphic below shows the scheme, as well as some predefined

1634

- policies (which are explained below).</p><div class="figure"><a id="idp18475584"></a><p class="title"><strong>Figure 22.29. A trie and its update policy</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_trie_node_updator_policy_cd.png" align="middle" alt="A trie and its update policy" /></div></div></div><br class="figure-break" /><p>This library offers the following pre-defined trie node

1635

+ policies (which are explained below).</p><div class="figure"><a id="idm269997055856"></a><p class="title"><strong>Figure 22.29. A trie and its update policy</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_trie_node_updator_policy_cd.png" align="middle" alt="A trie and its update policy" /></div></div></div><br class="figure-break" /><p>This library offers the following pre-defined trie node

1636

updating policies:</p><div class="orderedlist"><ol class="orderedlist" type="1"><li class="listitem"><p>

1637

<code class="classname">trie_order_statistics_node_update</code>

1638

supports order statistics.

1639

@@ -1128,7 +1128,7 @@

1640

simple list of integer keys. If we search for the integer 6, we

1641

are paying an overhead: the link with key 6 is only the fifth

1642

link; if it were the first link, it could be accessed

1643

- faster.</p><div class="figure"><a id="idp18506160"></a><p class="title"><strong>Figure 22.30. A simple list</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_simple_list.png" align="middle" alt="A simple list" /></div></div></div><br class="figure-break" /><p>List-update algorithms reorder lists as elements are

1644

+ faster.</p><div class="figure"><a id="idm269997025344"></a><p class="title"><strong>Figure 22.30. A simple list</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_simple_list.png" align="middle" alt="A simple list" /></div></div></div><br class="figure-break" /><p>List-update algorithms reorder lists as elements are

1645

accessed. They try to determine, by the access history, which

1646

keys to move to the front of the list. Some of these algorithms

1647

require adding some metadata alongside each entry.</p><p>For example, in the graphic below label A shows the counter

1648

@@ -1138,7 +1138,7 @@

1649

predetermined value, say 10, as shown in label C, the count is set

1650

to 0 and the node is moved to the front of the list, as in label

1651

D.

1652

- </p><div class="figure"><a id="idp18511744"></a><p class="title"><strong>Figure 22.31. The counter algorithm</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_list_update.png" align="middle" alt="The counter algorithm" /></div></div></div><br class="figure-break" /></div><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="container.list.details.policies"></a>Policies</h6></div></div></div><p>this library allows instantiating lists with policies

1653

+ </p><div class="figure"><a id="idm269997019760"></a><p class="title"><strong>Figure 22.31. The counter algorithm</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_list_update.png" align="middle" alt="The counter algorithm" /></div></div></div><br class="figure-break" /></div><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="container.list.details.policies"></a>Policies</h6></div></div></div><p>this library allows instantiating lists with policies

1654

implementing any algorithm moving nodes to the front of the

1655

list (policies implementing algorithms interchanging nodes are

1656

unsupported).</p><p>Associative containers based on lists are parametrized by a

1657

@@ -1310,7 +1310,7 @@

1658

sequence; the second uses a tree (or forest of trees), which is

1659

typically less structured than an associative container's tree;

1660

the third simply uses an associative container. These are

1661

- shown in the graphic below, in labels A1 and A2, label B, and label C.</p><div class="figure"><a id="idp18575568"></a><p class="title"><strong>Figure 22.32. Underlying Priority-Queue Data-Structures.</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_priority_queue_different_underlying_dss.png" align="middle" alt="Underlying Priority-Queue Data-Structures." /></div></div></div><br class="figure-break" /><p>Roughly speaking, any value that is both pushed and popped

1662

+ shown in the graphic below, in labels A1 and A2, label B, and label C.</p><div class="figure"><a id="idm269996955920"></a><p class="title"><strong>Figure 22.32. Underlying Priority-Queue Data-Structures.</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_priority_queue_different_underlying_dss.png" align="middle" alt="Underlying Priority-Queue Data-Structures." /></div></div></div><br class="figure-break" /><p>Roughly speaking, any value that is both pushed and popped

1663

from a priority queue must incur a logarithmic expense (in the

1664

amortized sense). Any priority queue implementation that would

1665

avoid this, would violate known bounds on comparison-based

1666

@@ -1390,7 +1390,7 @@

1667

container <code class="classname">Cntnr</code>, the tag of the underlying

1668

data structure can be found via <code class="classname">typename

1669

Cntnr::container_category</code>; this is one of the possible tags shown in the graphic below.

1670

- </p><div class="figure"><a id="idp18610544"></a><p class="title"><strong>Figure 22.33. Priority-Queue Data-Structure Tags.</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_priority_queue_tag_hierarchy.png" align="middle" alt="Priority-Queue Data-Structure Tags." /></div></div></div><br class="figure-break" /><p>Additionally, a traits mechanism can be used to query a

1671

+ </p><div class="figure"><a id="idm269996920880"></a><p class="title"><strong>Figure 22.33. Priority-Queue Data-Structure Tags.</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_priority_queue_tag_hierarchy.png" align="middle" alt="Priority-Queue Data-Structure Tags." /></div></div></div><br class="figure-break" /><p>Additionally, a traits mechanism can be used to query a

1672

container type for its attributes. Given any container

1673

<code class="classname">Cntnr</code>, then </p><pre class="programlisting">__gnu_pbds::container_traits<Cntnr></pre><p>

1674

is a traits class identifying the properties of the

1675

Index: libstdc++-v3/doc/html/manual/using.html

1676

===================================================================

1677

--- a/src/libstdc++-v3/doc/html/manual/using.html (.../tags/gcc_4_8_2_release)

1678

+++ b/src/libstdc++-v3/doc/html/manual/using.html (.../branches/gcc-4_8-branch)

1679

@@ -1,8 +1,8 @@

1680

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

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-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 3. Using</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="intro.html" title="Part I. Introduction" /><link rel="prev" href="make.html" title="Make" /><link rel="next" href="using_headers.html" title="Headers" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 3. Using</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="make.html">Prev</a> </td><th width="60%" align="center">Part I.

1682

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 3. Using</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="intro.html" title="Part I. Introduction" /><link rel="prev" href="make.html" title="Make" /><link rel="next" href="using_headers.html" title="Headers" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 3. Using</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="make.html">Prev</a> </td><th width="60%" align="center">Part I.

1683

Introduction

1684

1685

-</th><td width="20%" align="right"> <a accesskey="n" href="using_headers.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.intro.using"></a>Chapter 3. Using</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="using.html#manual.intro.using.flags">Command Options</a></span></dt><dt><span class="section"><a href="using_headers.html">Headers</a></span></dt><dd><dl><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.all">Header Files</a></span></dt><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.mixing">Mixing Headers</a></span></dt><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.cheaders">The C Headers and <code class="code">namespace std</code></a></span></dt><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.pre">Precompiled Headers</a></span></dt></dl></dd><dt><span class="section"><a href="using_macros.html">Macros</a></span></dt><dt><span class="section"><a href="using_namespaces.html">Namespaces</a></span></dt><dd><dl><dt><span class="section"><a href="using_namespaces.html#manual.intro.using.namespaces.all">Available Namespaces</a></span></dt><dt><span class="section"><a href="using_namespaces.html#manual.intro.using.namespaces.std">namespace std</a></span></dt><dt><span class="section"><a href="using_namespaces.html#manual.intro.using.namespaces.comp">Using Namespace Composition</a></span></dt></dl></dd><dt><span class="section"><a href="using_dynamic_or_shared.html">Linking</a></span></dt><dd><dl><dt><span class="section"><a href="using_dynamic_or_shared.html#manual.intro.using.linkage.freestanding">Almost Nothing</a></span></dt><dt><span class="section"><a href="using_dynamic_or_shared.html#manual.intro.using.linkage.dynamic">Finding Dynamic or Shared Libraries</a></span></dt></dl></dd><dt><span class="section"><a href="using_concurrency.html">Concurrency</a></span></dt><dd><dl><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.thread_safety">Thread Safety</a></span></dt><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.atomics">Atomics</a></span></dt><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.io">IO</a></span></dt><dd><dl><dt><span class="section"><a href="using_concurrency.html#concurrency.io.structure">Structure</a></span></dt><dt><span class="section"><a href="using_concurrency.html#concurrency.io.defaults">Defaults</a></span></dt><dt><span class="section"><a href="using_concurrency.html#concurrency.io.future">Future</a></span></dt><dt><span class="section"><a href="using_concurrency.html#concurrency.io.alt">Alternatives</a></span></dt></dl></dd><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.containers">Containers</a></span></dt></dl></dd><dt><span class="section"><a href="using_exceptions.html">Exceptions</a></span></dt><dd><dl><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.safety">Exception Safety</a></span></dt><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.propagating">Exception Neutrality</a></span></dt><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.no">Doing without</a></span></dt><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.compat">Compatibility</a></span></dt><dd><dl><dt><span class="section"><a href="using_exceptions.html#using.exception.compat.c">With <code class="literal">C</code></a></span></dt><dt><span class="section"><a href="using_exceptions.html#using.exception.compat.posix">With <code class="literal">POSIX</code> thread cancellation</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="debug.html">Debugging Support</a></span></dt><dd><dl><dt><span class="section"><a href="debug.html#debug.compiler">Using <span class="command"><strong>g++</strong></span></a></span></dt><dt><span class="section"><a href="debug.html#debug.req">Debug Versions of Library Binary Files</a></span></dt><dt><span class="section"><a href="debug.html#debug.memory">Memory Leak Hunting</a></span></dt><dt><span class="section"><a href="debug.html#debug.races">Data Race Hunting</a></span></dt><dt><span class="section"><a href="debug.html#debug.gdb">Using <span class="command"><strong>gdb</strong></span></a></span></dt><dt><span class="section"><a href="debug.html#debug.exceptions">Tracking uncaught exceptions</a></span></dt><dt><span class="section"><a href="debug.html#debug.debug_mode">Debug Mode</a></span></dt><dt><span class="section"><a href="debug.html#debug.compile_time_checks">Compile Time Checking</a></span></dt><dt><span class="section"><a href="debug.html#debug.profile_mode">Profile-based Performance Analysis</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.flags"></a>Command Options</h2></div></div></div><p>

1686

+</th><td width="20%" align="right"> <a accesskey="n" href="using_headers.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.intro.using"></a>Chapter 3. Using</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="using.html#manual.intro.using.flags">Command Options</a></span></dt><dt><span class="section"><a href="using_headers.html">Headers</a></span></dt><dd><dl><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.all">Header Files</a></span></dt><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.mixing">Mixing Headers</a></span></dt><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.cheaders">The C Headers and <code class="code">namespace std</code></a></span></dt><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.pre">Precompiled Headers</a></span></dt></dl></dd><dt><span class="section"><a href="using_macros.html">Macros</a></span></dt><dt><span class="section"><a href="using_namespaces.html">Namespaces</a></span></dt><dd><dl><dt><span class="section"><a href="using_namespaces.html#manual.intro.using.namespaces.all">Available Namespaces</a></span></dt><dt><span class="section"><a href="using_namespaces.html#manual.intro.using.namespaces.std">namespace std</a></span></dt><dt><span class="section"><a href="using_namespaces.html#manual.intro.using.namespaces.comp">Using Namespace Composition</a></span></dt></dl></dd><dt><span class="section"><a href="using_dynamic_or_shared.html">Linking</a></span></dt><dd><dl><dt><span class="section"><a href="using_dynamic_or_shared.html#manual.intro.using.linkage.freestanding">Almost Nothing</a></span></dt><dt><span class="section"><a href="using_dynamic_or_shared.html#manual.intro.using.linkage.dynamic">Finding Dynamic or Shared Libraries</a></span></dt></dl></dd><dt><span class="section"><a href="using_concurrency.html">Concurrency</a></span></dt><dd><dl><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.thread_safety">Thread Safety</a></span></dt><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.atomics">Atomics</a></span></dt><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.io">IO</a></span></dt><dd><dl><dt><span class="section"><a href="using_concurrency.html#concurrency.io.structure">Structure</a></span></dt><dt><span class="section"><a href="using_concurrency.html#concurrency.io.defaults">Defaults</a></span></dt><dt><span class="section"><a href="using_concurrency.html#concurrency.io.future">Future</a></span></dt><dt><span class="section"><a href="using_concurrency.html#concurrency.io.alt">Alternatives</a></span></dt></dl></dd><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.containers">Containers</a></span></dt></dl></dd><dt><span class="section"><a href="using_exceptions.html">Exceptions</a></span></dt><dd><dl><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.safety">Exception Safety</a></span></dt><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.propagating">Exception Neutrality</a></span></dt><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.no">Doing without</a></span></dt><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.compat">Compatibility</a></span></dt><dd><dl><dt><span class="section"><a href="using_exceptions.html#using.exception.compat.c">With <code class="literal">C</code></a></span></dt><dt><span class="section"><a href="using_exceptions.html#using.exception.compat.posix">With <code class="literal">POSIX</code> thread cancellation</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="debug.html">Debugging Support</a></span></dt><dd><dl><dt><span class="section"><a href="debug.html#debug.compiler">Using <span class="command"><strong>g++</strong></span></a></span></dt><dt><span class="section"><a href="debug.html#debug.req">Debug Versions of Library Binary Files</a></span></dt><dt><span class="section"><a href="debug.html#debug.memory">Memory Leak Hunting</a></span></dt><dt><span class="section"><a href="debug.html#debug.races">Data Race Hunting</a></span></dt><dt><span class="section"><a href="debug.html#debug.gdb">Using <span class="command"><strong>gdb</strong></span></a></span></dt><dt><span class="section"><a href="debug.html#debug.exceptions">Tracking uncaught exceptions</a></span></dt><dt><span class="section"><a href="debug.html#debug.debug_mode">Debug Mode</a></span></dt><dt><span class="section"><a href="debug.html#debug.compile_time_checks">Compile Time Checking</a></span></dt><dt><span class="section"><a href="debug.html#debug.profile_mode">Profile-based Performance Analysis</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.flags"></a>Command Options</h2></div></div></div><p>

1687

The set of features available in the GNU C++ library is shaped

1688

by

1689

several <a class="link" href="http://gcc.gnu.org/onlinedocs/gcc-4.3.2/gcc/Invoking-GCC.html" target="_top">GCC

1690

@@ -10,5 +10,5 @@

1691

enumerated and detailed in the table below.

1692

</p><p>

1693

By default, <span class="command"><strong>g++</strong></span> is equivalent to <span class="command"><strong>g++ -std=gnu++98</strong></span>. The standard library also defaults to this dialect.

1694

- </p><div class="table"><a id="idp13051936"></a><p class="title"><strong>Table 3.1. C++ Command Options</strong></p><div class="table-contents"><table summary="C++ Command Options" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><thead><tr><th align="left">Option Flags</th><th align="left">Description</th></tr></thead><tbody><tr><td align="left"><code class="literal">-std=c++98</code></td><td align="left">Use the 1998 ISO C++ standard plus amendments.</td></tr><tr><td align="left"><code class="literal">-std=gnu++98</code></td><td align="left">As directly above, with GNU extensions.</td></tr><tr><td align="left"><code class="literal">-std=c++11</code></td><td align="left">Use the 2011 ISO C++ standard.</td></tr><tr><td align="left"><code class="literal">-std=gnu++11</code></td><td align="left">As directly above, with GNU extensions.</td></tr><tr><td align="left"><code class="literal">-fexceptions</code></td><td align="left">See <a class="link" href="using_exceptions.html#intro.using.exception.no" title="Doing without">exception-free dialect</a></td></tr><tr><td align="left"><code class="literal">-frtti</code></td><td align="left">As above, but RTTI-free dialect.</td></tr><tr><td align="left"><code class="literal">-pthread</code> or <code class="literal">-pthreads</code></td><td align="left">For ISO C++11 <thread>, <future>,

1695

+ </p><div class="table"><a id="idm270002481088"></a><p class="title"><strong>Table 3.1. C++ Command Options</strong></p><div class="table-contents"><table summary="C++ Command Options" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><thead><tr><th align="left">Option Flags</th><th align="left">Description</th></tr></thead><tbody><tr><td align="left"><code class="literal">-std=c++98</code></td><td align="left">Use the 1998 ISO C++ standard plus amendments.</td></tr><tr><td align="left"><code class="literal">-std=gnu++98</code></td><td align="left">As directly above, with GNU extensions.</td></tr><tr><td align="left"><code class="literal">-std=c++11</code></td><td align="left">Use the 2011 ISO C++ standard.</td></tr><tr><td align="left"><code class="literal">-std=gnu++11</code></td><td align="left">As directly above, with GNU extensions.</td></tr><tr><td align="left"><code class="literal">-fexceptions</code></td><td align="left">See <a class="link" href="using_exceptions.html#intro.using.exception.no" title="Doing without">exception-free dialect</a></td></tr><tr><td align="left"><code class="literal">-frtti</code></td><td align="left">As above, but RTTI-free dialect.</td></tr><tr><td align="left"><code class="literal">-pthread</code> or <code class="literal">-pthreads</code></td><td align="left">For ISO C++11 <thread>, <future>,

1696

<mutex>, or <condition_variable>.</td></tr><tr><td align="left"><code class="literal">-fopenmp</code></td><td align="left">For <a class="link" href="parallel_mode.html" title="Chapter 18. Parallel Mode">parallel</a> mode.</td></tr></tbody></table></div></div><br class="table-break" /></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="make.html">Prev</a> </td><td width="20%" align="center"><a accesskey="u" href="intro.html">Up</a></td><td width="40%" align="right"> <a accesskey="n" href="using_headers.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">Make </td><td width="20%" align="center"><a accesskey="h" href="../index.html">Home</a></td><td width="40%" align="right" valign="top"> Headers</td></tr></table></div></body></html>

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Implementation Issues</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="prev" href="profile_mode_cost_model.html" title="Empirical Cost Model" /><link rel="next" href="profile_mode_devel.html" title="Developer Information" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Implementation Issues</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="profile_mode_cost_model.html">Prev</a> </td><th width="60%" align="center">Chapter 19. Profile Mode</th><td width="20%" align="right"> <a accesskey="n" href="profile_mode_devel.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.implementation"></a>Implementation Issues</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.ext.profile_mode.implementation.stack"></a>Stack Traces</h3></div></div></div><p>

1706

Accurate stack traces are needed during profiling since we group events by

1707

call context and dynamic instance. Without accurate traces, diagnostics

1708

may be hard to interpret. For instance, when giving advice to the user

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 23. HP/SGI Extensions</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III. Extensions" /><link rel="prev" href="policy_data_structures_ack.html" title="Acknowledgments" /><link rel="next" href="ext_sgi.html" title="Deprecated" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 23. HP/SGI Extensions</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="policy_data_structures_ack.html">Prev</a> </td><th width="60%" align="center">Part III.

1717

Extensions

1718

1719

-</th><td width="20%" align="right"> <a accesskey="n" href="ext_sgi.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.containers"></a>Chapter 23. HP/SGI Extensions</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="ext_containers.html#manual.ext.containers.sgi">Backwards Compatibility</a></span></dt><dt><span class="section"><a href="ext_sgi.html">Deprecated</a></span></dt></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.containers.sgi"></a>Backwards Compatibility</h2></div></div></div><p>A few extensions and nods to backwards-compatibility have

1720

+</th><td width="20%" align="right"> <a accesskey="n" href="ext_sgi.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.containers"></a>Chapter 23. HP/SGI Extensions</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="ext_containers.html#manual.ext.containers.sgi">Backwards Compatibility</a></span></dt><dt><span class="section"><a href="ext_sgi.html">Deprecated</a></span></dt></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.containers.sgi"></a>Backwards Compatibility</h2></div></div></div><p>A few extensions and nods to backwards-compatibility have

1721

been made with containers. Those dealing with older SGI-style

1722

allocators are dealt with elsewhere. The remaining ones all deal

1723

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1728

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1729

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

1730

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Use</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="ext_concurrency.html" title="Chapter 30. Concurrency" /><link rel="prev" href="ext_concurrency_impl.html" title="Implementation" /><link rel="next" href="appendix.html" title="Part IV. Appendices" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Use</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_concurrency_impl.html">Prev</a> </td><th width="60%" align="center">Chapter 30. Concurrency</th><td width="20%" align="right"> <a accesskey="n" href="appendix.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.concurrency.use"></a>Use</h2></div></div></div><p>Typical usage of the last two constructs is demonstrated as follows:

1731

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Use</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="ext_concurrency.html" title="Chapter 30. Concurrency" /><link rel="prev" href="ext_concurrency_impl.html" title="Implementation" /><link rel="next" href="appendix.html" title="Part IV. Appendices" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Use</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_concurrency_impl.html">Prev</a> </td><th width="60%" align="center">Chapter 30. Concurrency</th><td width="20%" align="right"> <a accesskey="n" href="appendix.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.concurrency.use"></a>Use</h2></div></div></div><p>Typical usage of the last two constructs is demonstrated as follows:

1732

</p><pre class="programlisting">

1733

#include <ext/concurrence.h>

1734

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 28. Input and Output</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III. Extensions" /><link rel="prev" href="ext_iterators.html" title="Chapter 27. Iterators" /><link rel="next" href="ext_demangling.html" title="Chapter 29. Demangling" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 28. Input and Output</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_iterators.html">Prev</a> </td><th width="60%" align="center">Part III.

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Extensions

1744

1745

-</th><td width="20%" align="right"> <a accesskey="n" href="ext_demangling.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.io"></a>Chapter 28. Input and Output</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="ext_io.html#manual.ext.io.filebuf_derived">Derived filebufs</a></span></dt></dl></div><p>

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+</th><td width="20%" align="right"> <a accesskey="n" href="ext_demangling.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.io"></a>Chapter 28. Input and Output</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="ext_io.html#manual.ext.io.filebuf_derived">Derived filebufs</a></span></dt></dl></div><p>

1747

Extensions allowing <code class="code">filebuf</code>s to be constructed from

1748

"C" types like FILE*s and file descriptors.

1749

</p><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.io.filebuf_derived"></a>Derived filebufs</h2></div></div></div><p>The v2 library included non-standard extensions to construct

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Termination</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="support.html" title="Chapter 4. Support" /><link rel="prev" href="dynamic_memory.html" title="Dynamic Memory" /><link rel="next" href="diagnostics.html" title="Chapter 5. Diagnostics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Termination</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="dynamic_memory.html">Prev</a> </td><th width="60%" align="center">Chapter 4.

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Support

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Macros</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_headers.html" title="Headers" /><link rel="next" href="using_namespaces.html" title="Namespaces" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Macros</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_headers.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="using_namespaces.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.macros"></a>Macros</h2></div></div></div><p>

1769

All library macros begin with <code class="code">_GLIBCXX_</code>.

1770

</p><p>

1771

Furthermore, all pre-processor macros, switches, and

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Concurrency

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Standard Contents

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</th><td width="20%" align="right"> <a accesskey="n" href="extensions.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="std.concurrency"></a>Chapter 15.

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Concurrency

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-</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="concurrency.html#std.concurrency.api">API Reference</a></span></dt></dl></div><p>

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+</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="concurrency.html#std.concurrency.api">API Reference</a></span></dt></dl></div><p>

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Facilities for concurrent operation, and control thereof.

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</p><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.concurrency.api"></a>API Reference</h2></div></div></div><p>

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All items are declared in one of four standard header files.

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 24. Utilities</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III. Extensions" /><link rel="prev" href="ext_sgi.html" title="Deprecated" /><link rel="next" href="ext_algorithms.html" title="Chapter 25. Algorithms" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 24. Utilities</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_sgi.html">Prev</a> </td><th width="60%" align="center">Part III.

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Extensions

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</th><td width="20%" align="right"> <a accesskey="n" href="ext_algorithms.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.util"></a>Chapter 24. Utilities</h2></div></div></div><p>

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Extensions

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-</th><td width="20%" align="right"> <a accesskey="n" href="policy_data_structures_using.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.containers.pbds"></a>Chapter 22. Policy-Based Data Structures</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="policy_data_structures.html#pbds.intro">Intro</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.issues">Performance Issues</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.issues.associative">Associative</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.issues.priority_queue">Priority Que</a></span></dt></dl></dd><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.motivation">Goals</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.motivation.associative">Associative</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#motivation.associative.policy">Policy Choices</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.associative.underlying">Underlying Data Structures</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.associative.iterators">Iterators</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.associative.functions">Functional</a></span></dt></dl></dd><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.motivation.priority_queue">Priority Queues</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#motivation.priority_queue.policy">Policy Choices</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.priority_queue.underlying">Underlying Data Structures</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.priority_queue.binary_heap">Binary Heaps</a></span></dt></dl></dd></dl></dd></dl></dd><dt><span class="section"><a href="policy_data_structures_using.html">Using</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.organization">Organization</a></span></dt><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.tutorial">Tutorial</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.tutorial.basic">Basic Use</a></span></dt><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.tutorial.configuring">

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+</th><td width="20%" align="right"> <a accesskey="n" href="policy_data_structures_using.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.containers.pbds"></a>Chapter 22. Policy-Based Data Structures</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="policy_data_structures.html#pbds.intro">Intro</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.issues">Performance Issues</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.issues.associative">Associative</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.issues.priority_queue">Priority Que</a></span></dt></dl></dd><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.motivation">Goals</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.motivation.associative">Associative</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#motivation.associative.policy">Policy Choices</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.associative.underlying">Underlying Data Structures</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.associative.iterators">Iterators</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.associative.functions">Functional</a></span></dt></dl></dd><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.motivation.priority_queue">Priority Queues</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#motivation.priority_queue.policy">Policy Choices</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.priority_queue.underlying">Underlying Data Structures</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.priority_queue.binary_heap">Binary Heaps</a></span></dt></dl></dd></dl></dd></dl></dd><dt><span class="section"><a href="policy_data_structures_using.html">Using</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.organization">Organization</a></span></dt><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.tutorial">Tutorial</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.tutorial.basic">Basic Use</a></span></dt><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.tutorial.configuring">

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Configuring via Template Parameters

1818

</a></span></dt><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.tutorial.traits">

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Querying Container Attributes

1820

@@ -248,7 +248,7 @@

1821

these invariants, one must supply some policy that is aware

1822

of these changes. Without this, it would be better to use a

1823

linked list (in itself very efficient for these purposes).

1824

- </p></li></ol></div><div class="figure"><a id="idp17613296"></a><p class="title"><strong>Figure 22.1. Node Invariants</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_node_invariants.png" align="middle" alt="Node Invariants" /></div></div></div><br class="figure-break" /></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="motivation.associative.underlying"></a>Underlying Data Structures</h5></div></div></div><p>

1825

+ </p></li></ol></div><div class="figure"><a id="idm269997917584"></a><p class="title"><strong>Figure 22.1. Node Invariants</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_node_invariants.png" align="middle" alt="Node Invariants" /></div></div></div><br class="figure-break" /></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="motivation.associative.underlying"></a>Underlying Data Structures</h5></div></div></div><p>

1826

The standard C++ library contains associative containers based on

1827

red-black trees and collision-chaining hash tables. These are

1828

very useful, but they are not ideal for all types of

1829

@@ -256,7 +256,7 @@

1830

</p><p>

1831

The figure below shows the different underlying data structures

1832

currently supported in this library.

1833

- </p><div class="figure"><a id="idp17619952"></a><p class="title"><strong>Figure 22.2. Underlying Associative Data Structures</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_different_underlying_dss_1.png" align="middle" alt="Underlying Associative Data Structures" /></div></div></div><br class="figure-break" /><p>

1834

+ </p><div class="figure"><a id="idm269997910864"></a><p class="title"><strong>Figure 22.2. Underlying Associative Data Structures</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_different_underlying_dss_1.png" align="middle" alt="Underlying Associative Data Structures" /></div></div></div><br class="figure-break" /><p>

1835

A shows a collision-chaining hash-table, B shows a probing

1836

hash-table, C shows a red-black tree, D shows a splay tree, E shows

1837

a tree based on an ordered vector(implicit in the order of the

1838

@@ -375,7 +375,7 @@

1839

no guarantee that the elements traversed will coincide with the

1840

<span class="emphasis"><em>logical</em></span> elements between 1 and 5, as in

1841

label B.

1842

- </p><div class="figure"><a id="idp17651648"></a><p class="title"><strong>Figure 22.3. Range Iteration in Different Data Structures</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_point_iterators_range_ops_1.png" align="middle" alt="Node Invariants" /></div></div></div><br class="figure-break" /><p>

1843

+ </p><div class="figure"><a id="idm269997879168"></a><p class="title"><strong>Figure 22.3. Range Iteration in Different Data Structures</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_point_iterators_range_ops_1.png" align="middle" alt="Node Invariants" /></div></div></div><br class="figure-break" /><p>

1844

In our opinion, this problem is not caused just because

1845

red-black trees are order preserving while

1846

collision-chaining hash tables are (generally) not - it

1847

@@ -426,7 +426,7 @@

1848

list, as in the graphic below, label B. Here the iterators are as

1849

light as can be, but the hash-table's operations are more

1850

complicated.

1851

- </p><div class="figure"><a id="idp17666528"></a><p class="title"><strong>Figure 22.4. Point Iteration in Hash Data Structures</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_point_iterators_range_ops_2.png" align="middle" alt="Point Iteration in Hash Data Structures" /></div></div></div><br class="figure-break" /><p>

1852

+ </p><div class="figure"><a id="idm269997864256"></a><p class="title"><strong>Figure 22.4. Point Iteration in Hash Data Structures</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_point_iterators_range_ops_2.png" align="middle" alt="Point Iteration in Hash Data Structures" /></div></div></div><br class="figure-break" /><p>

1853

It should be noted that containers based on collision-chaining

1854

hash-tables are not the only ones with this type of behavior;

1855

many other self-organizing data structures display it as well.

1856

@@ -442,7 +442,7 @@

1857

container. The graphic below shows three cases: A1 and A2 show

1858

a red-black tree; B1 and B2 show a probing hash-table; C1 and C2

1859

show a collision-chaining hash table.

1860

- </p><div class="figure"><a id="idp17675840"></a><p class="title"><strong>Figure 22.5. Effect of erase in different underlying data structures</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_invalidation_guarantee_erase.png" align="middle" alt="Effect of erase in different underlying data structures" /></div></div></div><br class="figure-break" /><div class="orderedlist"><ol class="orderedlist" type="1"><li class="listitem"><p>

1861

+ </p><div class="figure"><a id="idm269997855056"></a><p class="title"><strong>Figure 22.5. Effect of erase in different underlying data structures</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_invalidation_guarantee_erase.png" align="middle" alt="Effect of erase in different underlying data structures" /></div></div></div><br class="figure-break" /><div class="orderedlist"><ol class="orderedlist" type="1"><li class="listitem"><p>

1862

Erasing 5 from A1 yields A2. Clearly, an iterator to 3 can

1863

be de-referenced and incremented. The sequence of iterators

1864

changed, but in a way that is well-defined by the interface.

1865

@@ -678,7 +678,7 @@

1866

typically less structured than an associative container's tree;

1867

the third simply uses an associative container. These are

1868

shown in the figure below with labels A1 and A2, B, and C.

1869

- </p><div class="figure"><a id="idp17743424"></a><p class="title"><strong>Figure 22.6. Underlying Priority Queue Data Structures</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_different_underlying_dss_2.png" align="middle" alt="Underlying Priority Queue Data Structures" /></div></div></div><br class="figure-break" /><p>

1870

+ </p><div class="figure"><a id="idm269997787392"></a><p class="title"><strong>Figure 22.6. Underlying Priority Queue Data Structures</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_different_underlying_dss_2.png" align="middle" alt="Underlying Priority Queue Data Structures" /></div></div></div><br class="figure-break" /><p>

1871

No single implementation can completely replace any of the

1872

others. Some have better <code class="function">push</code>

1873

and <code class="function">pop</code> amortized performance, some have

1874

@@ -1098,7 +1098,7 @@

1875

</span>. </span><span class="publisher"><span class="publishername">

1876

Proceedings of International Conference on Very Large Data Bases

1877

. </span></span></p></div><div class="biblioentry"><a id="biblio.maverik_lowerbounds"></a><p>[biblio.maverik_lowerbounds] <span class="title"><em>

1878

- <a class="link" href="http://magic.aladdin.cs.cmu.edu/2005/08/01/deamortization-part-2-binomial-heaps" target="_top">

1879

+ <a class="link" href="http://magic.aladdin.cs.cmu.edu/2005/08/01/deamortization-part-2-binomial-heaps/" target="_top">

1880

Deamortization - Part 2: Binomial Heaps

1881

</a>

1882

</em>. </span><span class="date">

1883

@@ -1190,7 +1190,7 @@

1884

</span>. </span><span class="publisher"><span class="publishername">

1885

Addison-Wesley Publishing Company

1886

. </span></span></p></div><div class="biblioentry"><a id="biblio.nelson96stlpq"></a><p>[biblio.nelson96stlpq] <span class="title"><em>

1887

- <a class="link" href="http://www.dogma.net/markn/articles/pq_stl/priority.htm" target="_top">Priority Queues and the STL

1888

+ <a class="link" href="http://marknelson.us/1996/01/01/priority-queues/" target="_top">Priority Queues and the STL

1889

</a>

1890

</em>. </span><span class="date">

1891

January 1996

1892

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-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 27. Iterators</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III. Extensions" /><link rel="prev" href="ext_numerics.html" title="Chapter 26. Numerics" /><link rel="next" href="ext_io.html" title="Chapter 28. Input and Output" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 27. Iterators</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_numerics.html">Prev</a> </td><th width="60%" align="center">Part III.

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 27. Iterators</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III. Extensions" /><link rel="prev" href="ext_numerics.html" title="Chapter 26. Numerics" /><link rel="next" href="ext_io.html" title="Chapter 28. Input and Output" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 27. Iterators</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_numerics.html">Prev</a> </td><th width="60%" align="center">Part III.

1900

Extensions

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1902

</th><td width="20%" align="right"> <a accesskey="n" href="ext_io.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.iterators"></a>Chapter 27. Iterators</h2></div></div></div><p>24.3.2 describes <code class="code">struct iterator</code>, which didn't exist in the

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>

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-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Implementation</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, allocator" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="bitmap_allocator.html" title="Chapter 21. The bitmap_allocator" /><link rel="prev" href="bitmap_allocator.html" title="Chapter 21. The bitmap_allocator" /><link rel="next" href="policy_data_structures.html" title="Chapter 22. Policy-Based Data Structures" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Implementation</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="bitmap_allocator.html">Prev</a> </td><th width="60%" align="center">Chapter 21. The bitmap_allocator</th><td width="20%" align="right"> <a accesskey="n" href="policy_data_structures.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="allocator.bitmap.impl"></a>Implementation</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="bitmap.impl.free_list_store"></a>Free List Store</h3></div></div></div><p>

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The Free List Store (referred to as FLS for the remaining part of this

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document) is the Global memory pool that is shared by all instances of

1913

the bitmapped allocator instantiated for any type. This maintains a

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1915

</p><p>

1916

Consider a block of size 64 ints. In memory, it would look like this:

1917

(assume a 32-bit system where, size_t is a 32-bit entity).

1918

- </p><div class="table"><a id="idp17500848"></a><p class="title"><strong>Table 21.1. Bitmap Allocator Memory Map</strong></p><div class="table-contents"><table summary="Bitmap Allocator Memory Map" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left">268</td><td align="left">0</td><td align="left">4294967295</td><td align="left">4294967295</td><td align="left">Data -> Space for 64 ints</td></tr></tbody></table></div></div><br class="table-break" /><p>

1919

+ </p><div class="table"><a id="idm269998030352"></a><p class="title"><strong>Table 21.1. Bitmap Allocator Memory Map</strong></p><div class="table-contents"><table summary="Bitmap Allocator Memory Map" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left">268</td><td align="left">0</td><td align="left">4294967295</td><td align="left">4294967295</td><td align="left">Data -> Space for 64 ints</td></tr></tbody></table></div></div><br class="table-break" /><p>

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The first Column(268) represents the size of the Block in bytes as

1921

seen by the Bitmap Allocator. Internally, a global free list is

1922

used to keep track of the free blocks used and given back by the

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Appendix A. Contributing</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix.html" title="Part IV. Appendices" /><link rel="prev" href="appendix.html" title="Part IV. Appendices" /><link rel="next" href="source_organization.html" title="Directory Layout and Source Conventions" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Appendix A.

1931

Contributing

1932

1933

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Appendices

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</th><td width="20%" align="right"> <a accesskey="n" href="source_organization.html">Next</a></td></tr></table><hr /></div><div class="appendix"><div class="titlepage"><div><div><h1 class="title"><a id="appendix.contrib"></a>

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Contributing

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-</h1></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="appendix_contributing.html#contrib.list">Contributor Checklist</a></span></dt><dd><dl><dt><span class="section"><a href="appendix_contributing.html#list.reading">Reading</a></span></dt><dt><span class="section"><a href="appendix_contributing.html#list.copyright">Assignment</a></span></dt><dt><span class="section"><a href="appendix_contributing.html#list.getting">Getting Sources</a></span></dt><dt><span class="section"><a href="appendix_contributing.html#list.patches">Submitting Patches</a></span></dt></dl></dd><dt><span class="section"><a href="source_organization.html">Directory Layout and Source Conventions</a></span></dt><dt><span class="section"><a href="source_code_style.html">Coding Style</a></span></dt><dd><dl><dt><span class="section"><a href="source_code_style.html#coding_style.bad_identifiers">Bad Identifiers</a></span></dt><dt><span class="section"><a href="source_code_style.html#coding_style.example">By Example</a></span></dt></dl></dd><dt><span class="section"><a href="source_design_notes.html">Design Notes</a></span></dt></dl></div><p>

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+ <a id="idm269993657472" class="indexterm"></a>

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+</h1></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="appendix_contributing.html#contrib.list">Contributor Checklist</a></span></dt><dd><dl><dt><span class="section"><a href="appendix_contributing.html#list.reading">Reading</a></span></dt><dt><span class="section"><a href="appendix_contributing.html#list.copyright">Assignment</a></span></dt><dt><span class="section"><a href="appendix_contributing.html#list.getting">Getting Sources</a></span></dt><dt><span class="section"><a href="appendix_contributing.html#list.patches">Submitting Patches</a></span></dt></dl></dd><dt><span class="section"><a href="source_organization.html">Directory Layout and Source Conventions</a></span></dt><dt><span class="section"><a href="source_code_style.html">Coding Style</a></span></dt><dd><dl><dt><span class="section"><a href="source_code_style.html#coding_style.bad_identifiers">Bad Identifiers</a></span></dt><dt><span class="section"><a href="source_code_style.html#coding_style.example">By Example</a></span></dt></dl></dd><dt><span class="section"><a href="source_design_notes.html">Design Notes</a></span></dt></dl></div><p>

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The GNU C++ Library follows an open development model. Active

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contributors are assigned maintainer-ship responsibility, and given

1944

write access to the source repository. First time contributors

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@@ -36,7 +36,7 @@

1946

for this group is quite useful.

1947

</p></li><li class="listitem"><p>

1948

Peruse

1949

- the <a class="link" href="http://www.gnu.org/prep/standards" target="_top">GNU

1950

+ the <a class="link" href="http://www.gnu.org/prep/standards/" target="_top">GNU

1951

Coding Standards</a>, and chuckle when you hit the part

1952

about <span class="quote">“<span class="quote">Using Languages Other Than C</span>”</span>.

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</p></li><li class="listitem"><p>

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Testing</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, parallel" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="parallel_mode.html" title="Chapter 18. Parallel Mode" /><link rel="prev" href="parallel_mode_design.html" title="Design" /><link rel="next" href="profile_mode.html" title="Chapter 19. Profile Mode" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Testing</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="parallel_mode_design.html">Prev</a> </td><th width="60%" align="center">Chapter 18. Parallel Mode</th><td width="20%" align="right"> <a accesskey="n" href="profile_mode.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.parallel_mode.test"></a>Testing</h2></div></div></div><p>

1962

Both the normal conformance and regression tests and the

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supplemental performance tests work.

1964

</p><p>

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 19. Profile Mode</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III. Extensions" /><link rel="prev" href="parallel_mode_test.html" title="Testing" /><link rel="next" href="profile_mode_design.html" title="Design" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 19. Profile Mode</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="parallel_mode_test.html">Prev</a> </td><th width="60%" align="center">Part III.

1973

Extensions

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1975

-</th><td width="20%" align="right"> <a accesskey="n" href="profile_mode_design.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.profile_mode"></a>Chapter 19. Profile Mode</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="profile_mode.html#manual.ext.profile_mode.intro">Intro</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode.html#manual.ext.profile_mode.using">Using the Profile Mode</a></span></dt><dt><span class="section"><a href="profile_mode.html#manual.ext.profile_mode.tuning">Tuning the Profile Mode</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_design.html">Design</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.wrapper">Wrapper Model</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.instrumentation">Instrumentation</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.rtlib">Run Time Behavior</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.analysis">Analysis and Diagnostics</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.cost-model">Cost Model</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.reports">Reports</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.testing">Testing</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_api.html">Extensions for Custom Containers</a></span></dt><dt><span class="section"><a href="profile_mode_cost_model.html">Empirical Cost Model</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html">Implementation Issues</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.stack">Stack Traces</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.symbols">Symbolization of Instruction Addresses</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.concurrency">Concurrency</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.stdlib-in-proflib">Using the Standard Library in the Instrumentation Implementation</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.malloc-hooks">Malloc Hooks</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.construction-destruction">Construction and Destruction of Global Objects</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_devel.html">Developer Information</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_devel.html#manual.ext.profile_mode.developer.bigpic">Big Picture</a></span></dt><dt><span class="section"><a href="profile_mode_devel.html#manual.ext.profile_mode.developer.howto">How To Add A Diagnostic</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html">Diagnostics</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.template">Diagnostic Template</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.containers">Containers</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.hashtable_too_small">Hashtable Too Small</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.hashtable_too_large">Hashtable Too Large</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.inefficient_hash">Inefficient Hash</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.vector_too_small">Vector Too Small</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.vector_too_large">Vector Too Large</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.vector_to_hashtable">Vector to Hashtable</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.hashtable_to_vector">Hashtable to Vector</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.vector_to_list">Vector to List</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.list_to_vector">List to Vector</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.list_to_slist">List to Forward List (Slist)</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.assoc_ord_to_unord">Ordered to Unordered Associative Container</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.algorithms">Algorithms</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.algorithms.sort">Sort Algorithm Performance</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.locality">Data Locality</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.locality.sw_prefetch">Need Software Prefetch</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.locality.linked">Linked Structure Locality</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.mthread">Multithreaded Data Access</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.mthread.ddtest">Data Dependence Violations at Container Level</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.mthread.false_share">False Sharing</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.statistics">Statistics</a></span></dt></dl></dd><dt><span class="bibliography"><a href="profile_mode.html#profile_mode.biblio">Bibliography</a></span></dt></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.intro"></a>Intro</h2></div></div></div><p>

1976

+</th><td width="20%" align="right"> <a accesskey="n" href="profile_mode_design.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.profile_mode"></a>Chapter 19. Profile Mode</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="profile_mode.html#manual.ext.profile_mode.intro">Intro</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode.html#manual.ext.profile_mode.using">Using the Profile Mode</a></span></dt><dt><span class="section"><a href="profile_mode.html#manual.ext.profile_mode.tuning">Tuning the Profile Mode</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_design.html">Design</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.wrapper">Wrapper Model</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.instrumentation">Instrumentation</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.rtlib">Run Time Behavior</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.analysis">Analysis and Diagnostics</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.cost-model">Cost Model</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.reports">Reports</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.testing">Testing</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_api.html">Extensions for Custom Containers</a></span></dt><dt><span class="section"><a href="profile_mode_cost_model.html">Empirical Cost Model</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html">Implementation Issues</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.stack">Stack Traces</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.symbols">Symbolization of Instruction Addresses</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.concurrency">Concurrency</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.stdlib-in-proflib">Using the Standard Library in the Instrumentation Implementation</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.malloc-hooks">Malloc Hooks</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.construction-destruction">Construction and Destruction of Global Objects</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_devel.html">Developer Information</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_devel.html#manual.ext.profile_mode.developer.bigpic">Big Picture</a></span></dt><dt><span class="section"><a href="profile_mode_devel.html#manual.ext.profile_mode.developer.howto">How To Add A Diagnostic</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html">Diagnostics</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.template">Diagnostic Template</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.containers">Containers</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.hashtable_too_small">Hashtable Too Small</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.hashtable_too_large">Hashtable Too Large</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.inefficient_hash">Inefficient Hash</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.vector_too_small">Vector Too Small</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.vector_too_large">Vector Too Large</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.vector_to_hashtable">Vector to Hashtable</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.hashtable_to_vector">Hashtable to Vector</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.vector_to_list">Vector to List</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.list_to_vector">List to Vector</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.list_to_slist">List to Forward List (Slist)</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.assoc_ord_to_unord">Ordered to Unordered Associative Container</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.algorithms">Algorithms</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.algorithms.sort">Sort Algorithm Performance</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.locality">Data Locality</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.locality.sw_prefetch">Need Software Prefetch</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.locality.linked">Linked Structure Locality</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.mthread">Multithreaded Data Access</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.mthread.ddtest">Data Dependence Violations at Container Level</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.mthread.false_share">False Sharing</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.statistics">Statistics</a></span></dt></dl></dd><dt><span class="bibliography"><a href="profile_mode.html#profile_mode.biblio">Bibliography</a></span></dt></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.intro"></a>Intro</h2></div></div></div><p>

1977

<span class="emphasis"><em>Goal: </em></span>Give performance improvement advice based on

1978

recognition of suboptimal usage patterns of the standard library.

1979

</p><p>

1980

@@ -137,7 +137,7 @@

1981

call context.

1982

(Environment variable not supported.)

1983

</p></li></ul></div><p>

1984

- </p></div></div><div class="bibliography"><div class="titlepage"><div><div><h2 class="title"><a id="profile_mode.biblio"></a>Bibliography</h2></div></div></div><div class="biblioentry"><a id="idp17395456"></a><p><span class="citetitle"><em class="citetitle">

1985

+ </p></div></div><div class="bibliography"><div class="titlepage"><div><div><h2 class="title"><a id="profile_mode.biblio"></a>Bibliography</h2></div></div></div><div class="biblioentry"><a id="idm269998135936"></a><p><span class="citetitle"><em class="citetitle">

1986

Perflint: A Context Sensitive Performance Advisor for C++ Programs

1987

</em>. </span><span class="author"><span class="firstname">Lixia</span> <span class="surname">Liu</span>. </span><span class="author"><span class="firstname">Silvius</span> <span class="surname">Rus</span>. </span><span class="copyright">Copyright © 2009 . </span><span class="publisher"><span class="publishername">

1988

Proceedings of the 2009 International Symposium on Code Generation

1989

Index: libstdc++-v3/doc/html/manual/stringstreams.html

1990

===================================================================

1991

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1994

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

1995

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Memory Based Streams</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="io.html" title="Chapter 13. Input and Output" /><link rel="prev" href="streambufs.html" title="Stream Buffers" /><link rel="next" href="fstreams.html" title="File Based Streams" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Memory Based Streams</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="streambufs.html">Prev</a> </td><th width="60%" align="center">Chapter 13.

1996

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Memory Based Streams</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="io.html" title="Chapter 13. Input and Output" /><link rel="prev" href="streambufs.html" title="Stream Buffers" /><link rel="next" href="fstreams.html" title="File Based Streams" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Memory Based Streams</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="streambufs.html">Prev</a> </td><th width="60%" align="center">Chapter 13.

1997

Input and Output

1998

1999

</th><td width="20%" align="right"> <a accesskey="n" href="fstreams.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.io.memstreams"></a>Memory Based Streams</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="std.io.memstreams.compat"></a>Compatibility With strstream</h3></div></div></div><p>

2000

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2001

===================================================================

2002

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>

2006

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Traits</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="utilities.html" title="Chapter 6. Utilities" /><link rel="prev" href="memory.html" title="Memory" /><link rel="next" href="strings.html" title="Chapter 7. Strings" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Traits</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="memory.html">Prev</a> </td><th width="60%" align="center">Chapter 6.

2007

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Traits</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="utilities.html" title="Chapter 6. Utilities" /><link rel="prev" href="memory.html" title="Memory" /><link rel="next" href="strings.html" title="Chapter 7. Strings" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Traits</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="memory.html">Prev</a> </td><th width="60%" align="center">Chapter 6.

2008

Utilities

2009

2010

</th><td width="20%" align="right"> <a accesskey="n" href="strings.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.util.traits"></a>Traits</h2></div></div></div><p>

2011

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2012

===================================================================

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2014

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2015

@@ -1,10 +1,9 @@

2016

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

2017

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Acknowledgments</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, policy, container, data, structure, associated, tree, trie, hash, metaprogramming" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="policy_data_structures.html" title="Chapter 22. Policy-Based Data Structures" /><link rel="prev" href="policy_based_data_structures_test.html" title="Testing" /><link rel="next" href="ext_containers.html" title="Chapter 23. HP/SGI Extensions" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Acknowledgments</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="policy_based_data_structures_test.html">Prev</a> </td><th width="60%" align="center">Chapter 22. Policy-Based Data Structures</th><td width="20%" align="right"> <a accesskey="n" href="ext_containers.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="pbds.ack"></a>Acknowledgments</h2></div></div></div><p>

2018

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Acknowledgments</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, policy, container, data, structure, associated, tree, trie, hash, metaprogramming" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="policy_data_structures.html" title="Chapter 22. Policy-Based Data Structures" /><link rel="prev" href="policy_based_data_structures_test.html" title="Testing" /><link rel="next" href="ext_containers.html" title="Chapter 23. HP/SGI Extensions" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Acknowledgments</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="policy_based_data_structures_test.html">Prev</a> </td><th width="60%" align="center">Chapter 22. Policy-Based Data Structures</th><td width="20%" align="right"> <a accesskey="n" href="ext_containers.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="pbds.ack"></a>Acknowledgments</h2></div></div></div><p>

2019

Written by Ami Tavory and Vladimir Dreizin (IBM Haifa Research

2020

Laboratories), and Benjamin Kosnik (Red Hat).

2021

</p><p>

2022

- This library was partially written at

2023

- <a class="link" href="http://www.haifa.il.ibm.com/" target="_top">IBM's Haifa Research Labs</a>.

2024

+ This library was partially written at IBM's Haifa Research Labs.

2025

It is based heavily on policy-based design and uses many useful

2026

techniques from Modern C++ Design: Generic Programming and Design

2027

Patterns Applied by Andrei Alexandrescu.

2028

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2030

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2033

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

2034

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Associative</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="containers.html" title="Chapter 9. Containers" /><link rel="prev" href="containers.html" title="Chapter 9. Containers" /><link rel="next" href="unordered_associative.html" title="Unordered Associative" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Associative</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="containers.html">Prev</a> </td><th width="60%" align="center">Chapter 9.

2035

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Associative</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="containers.html" title="Chapter 9. Containers" /><link rel="prev" href="containers.html" title="Chapter 9. Containers" /><link rel="next" href="unordered_associative.html" title="Unordered Associative" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Associative</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="containers.html">Prev</a> </td><th width="60%" align="center">Chapter 9.

2036

Containers

2037

2038

</th><td width="20%" align="right"> <a accesskey="n" href="unordered_associative.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.containers.associative"></a>Associative</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="containers.associative.insert_hints"></a>Insertion Hints</h3></div></div></div><p>

2039

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Extensions

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contains all the higher-level

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the concurrence layer consists largely of types. All types are defined within <code class="code">namespace __gnu_cxx</code>.

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Support

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Standard Contents

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This part deals with the functions called and objects created

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Extensions

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+</th><td width="20%" align="right"> <a accesskey="n" href="bitmap_allocator_impl.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.allocator.bitmap"></a>Chapter 21. The bitmap_allocator</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="bitmap_allocator.html#allocator.bitmap.design">Design</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.free_list_store">Free List Store</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.super_block">Super Block</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.super_block_data">Super Block Data Layout</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.max_wasted">Maximum Wasted Percentage</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.allocate"><code class="function">allocate</code></a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.deallocate"><code class="function">deallocate</code></a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.questions">Questions</a></span></dt><dd><dl><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.question.1">1</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.question.2">2</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.question.3">3</a></span></dt></dl></dd><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.locality">Locality</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.grow_policy">Overhead and Grow Policy</a></span></dt></dl></dd></dl></div><p>

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</p><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="allocator.bitmap.design"></a>Design</h2></div></div></div><p>

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As this name suggests, this allocator uses a bit-map to keep track

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and one for the documentation.

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Numerics

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Standard Contents

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+</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="numerics.html#std.numerics.complex">Complex</a></span></dt><dd><dl><dt><span class="section"><a href="numerics.html#numerics.complex.processing">complex Processing</a></span></dt></dl></dd><dt><span class="section"><a href="generalized_numeric_operations.html">Generalized Operations</a></span></dt><dt><span class="section"><a href="numerics_and_c.html">Interacting with C</a></span></dt><dd><dl><dt><span class="section"><a href="numerics_and_c.html#numerics.c.array">Numerics vs. Arrays</a></span></dt><dt><span class="section"><a href="numerics_and_c.html#numerics.c.c99">C99</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.numerics.complex"></a>Complex</h2></div></div></div><p>

2121

</p><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="numerics.complex.processing"></a>complex Processing</h3></div></div></div><p>

2122

</p><p>Using <code class="code">complex<></code> becomes even more comple- er, sorry,

2123

<span class="emphasis"><em>complicated</em></span>, with the not-quite-gratuitously-incompatible

2124

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2125

===================================================================

2126

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2127

+++ b/src/libstdc++-v3/doc/html/manual/using_exceptions.html (.../branches/gcc-4_8-branch)

2128

@@ -1,5 +1,5 @@

2129

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

2130

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Exceptions</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="C++, exception, error, exception neutrality, exception safety, exception propagation, -fno-exceptions" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_concurrency.html" title="Concurrency" /><link rel="next" href="debug.html" title="Debugging Support" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Exceptions</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_concurrency.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="debug.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.exceptions"></a>Exceptions</h2></div></div></div><p>

2131

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Exceptions</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, exception, error, exception neutrality, exception safety, exception propagation, -fno-exceptions" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_concurrency.html" title="Concurrency" /><link rel="next" href="debug.html" title="Debugging Support" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Exceptions</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_concurrency.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="debug.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.exceptions"></a>Exceptions</h2></div></div></div><p>

2132

The C++ language provides language support for stack unwinding

2133

with <code class="literal">try</code> and <code class="literal">catch</code> blocks and

2134

the <code class="literal">throw</code> keyword.

2135

@@ -265,7 +265,7 @@

2136

}

2137

catch(...)

2138

{ this->_M_setstate(ios_base::badbit); }

2139

-</pre></div></div><div class="bibliography"><div class="titlepage"><div><div><h3 class="title"><a id="using.exceptions.biblio"></a>Bibliography</h3></div></div></div><div class="biblioentry"><a id="idp13644000"></a><p><span class="title"><em>

2140

+</pre></div></div><div class="bibliography"><div class="titlepage"><div><div><h3 class="title"><a id="using.exceptions.biblio"></a>Bibliography</h3></div></div></div><div class="biblioentry"><a id="idm270001889024"></a><p><span class="title"><em>

2141

2142

System Interface Definitions, Issue 7 (IEEE Std. 1003.1-2008)

2143

</a>

2144

@@ -274,39 +274,39 @@

2145

2146

The Open Group/The Institute of Electrical and Electronics

2147

Engineers, Inc.

2148

- . </span></p></div><div class="biblioentry"><a id="idp13647696"></a><p><span class="title"><em>

2149

+ . </span></p></div><div class="biblioentry"><a id="idm270001885328"></a><p><span class="title"><em>

2150

2151

Error and Exception Handling

2152

</a>

2153

</em>. </span><span class="author"><span class="firstname">David</span> <span class="surname">Abrahams </span>. </span><span class="publisher"><span class="publishername">

2154

Boost

2155

- . </span></span></p></div><div class="biblioentry"><a id="idp13651392"></a><p><span class="title"><em>

2156

+ . </span></span></p></div><div class="biblioentry"><a id="idm270001881632"></a><p><span class="title"><em>

2157

2158

Exception-Safety in Generic Components

2159

</a>

2160

</em>. </span><span class="author"><span class="firstname">David</span> <span class="surname">Abrahams</span>. </span><span class="publisher"><span class="publishername">

2161

Boost

2162

- . </span></span></p></div><div class="biblioentry"><a id="idp13655104"></a><p><span class="title"><em>

2163

+ . </span></span></p></div><div class="biblioentry"><a id="idm270001877920"></a><p><span class="title"><em>

2164

2165

Standard Library Exception Policy

2166

</a>

2167

</em>. </span><span class="author"><span class="firstname">Matt</span> <span class="surname">Austern</span>. </span><span class="publisher"><span class="publishername">

2168

WG21 N1077

2169

- . </span></span></p></div><div class="biblioentry"><a id="idp13658816"></a><p><span class="title"><em>

2170

+ . </span></span></p></div><div class="biblioentry"><a id="idm270001874208"></a><p><span class="title"><em>

2171

2172

ia64 c++ abi exception handling

2173

</a>

2174

</em>. </span><span class="author"><span class="firstname">Richard</span> <span class="surname">Henderson</span>. </span><span class="publisher"><span class="publishername">

2175

GNU

2176

- . </span></span></p></div><div class="biblioentry"><a id="idp13662512"></a><p><span class="title"><em>

2177

+ . </span></span></p></div><div class="biblioentry"><a id="idm270001870512"></a><p><span class="title"><em>

2178

2179

Appendix E: Standard-Library Exception Safety

2180

</a>

2181

- </em>. </span><span class="author"><span class="firstname">Bjarne</span> <span class="surname">Stroustrup</span>. </span></p></div><div class="biblioentry"><a id="idp13665328"></a><p><span class="citetitle"><em class="citetitle">

2182

+ </em>. </span><span class="author"><span class="firstname">Bjarne</span> <span class="surname">Stroustrup</span>. </span></p></div><div class="biblioentry"><a id="idm270001867696"></a><p><span class="citetitle"><em class="citetitle">

2183

Exceptional C++

2184

</em>. </span><span class="pagenums">

2185

Exception-Safety Issues and Techniques

2186

- . </span><span class="author"><span class="firstname">Herb</span> <span class="surname">Sutter</span>. </span></p></div><div class="biblioentry"><a id="idp13667712"></a><p><span class="title"><em>

2187

+ . </span><span class="author"><span class="firstname">Herb</span> <span class="surname">Sutter</span>. </span></p></div><div class="biblioentry"><a id="idm270001865312"></a><p><span class="title"><em>

2188

2189

GCC Bug 25191: exception_defines.h #defines try/catch

2190

</a>

2191

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2192

===================================================================

2193

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2194

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2195

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2196

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

2197

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Testing</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, policy, container, data, structure, associated, tree, trie, hash, metaprogramming" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="policy_data_structures.html" title="Chapter 22. Policy-Based Data Structures" /><link rel="prev" href="policy_data_structures_design.html" title="Design" /><link rel="next" href="policy_data_structures_ack.html" title="Acknowledgments" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Testing</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="policy_data_structures_design.html">Prev</a> </td><th width="60%" align="center">Chapter 22. Policy-Based Data Structures</th><td width="20%" align="right"> <a accesskey="n" href="policy_data_structures_ack.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="pbds.test"></a>Testing</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="pbds.test.regression"></a>Regression</h3></div></div></div><p>The library contains a single comprehensive regression test.

2198

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Testing</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, policy, container, data, structure, associated, tree, trie, hash, metaprogramming" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="policy_data_structures.html" title="Chapter 22. Policy-Based Data Structures" /><link rel="prev" href="policy_data_structures_design.html" title="Design" /><link rel="next" href="policy_data_structures_ack.html" title="Acknowledgments" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Testing</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="policy_data_structures_design.html">Prev</a> </td><th width="60%" align="center">Chapter 22. Policy-Based Data Structures</th><td width="20%" align="right"> <a accesskey="n" href="policy_data_structures_ack.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="pbds.test"></a>Testing</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="pbds.test.regression"></a>Regression</h3></div></div></div><p>The library contains a single comprehensive regression test.

2199

For a given container type in this library, the test creates

2200

an object of the container type and an object of the

2201

corresponding standard type (e.g., <code class="classname">std::set</code>). It

2202

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2203

===================================================================

2204

--- a/src/libstdc++-v3/doc/html/manual/parallel_mode_design.html (.../tags/gcc_4_8_2_release)

2205

+++ b/src/libstdc++-v3/doc/html/manual/parallel_mode_design.html (.../branches/gcc-4_8-branch)

2206

@@ -1,5 +1,5 @@

2207

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

2208

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="C++, library, parallel" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="parallel_mode.html" title="Chapter 18. Parallel Mode" /><link rel="prev" href="parallel_mode_using.html" title="Using" /><link rel="next" href="parallel_mode_test.html" title="Testing" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="parallel_mode_using.html">Prev</a> </td><th width="60%" align="center">Chapter 18. Parallel Mode</th><td width="20%" align="right"> <a accesskey="n" href="parallel_mode_test.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.parallel_mode.design"></a>Design</h2></div></div></div><p>

2209

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, parallel" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="parallel_mode.html" title="Chapter 18. Parallel Mode" /><link rel="prev" href="parallel_mode_using.html" title="Using" /><link rel="next" href="parallel_mode_test.html" title="Testing" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="parallel_mode_using.html">Prev</a> </td><th width="60%" align="center">Chapter 18. Parallel Mode</th><td width="20%" align="right"> <a accesskey="n" href="parallel_mode_test.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.parallel_mode.design"></a>Design</h2></div></div></div><p>

2210

</p><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="parallel_mode.design.intro"></a>Interface Basics</h3></div></div></div><p>

2211

All parallel algorithms are intended to have signatures that are

2212

equivalent to the ISO C++ algorithms replaced. For instance, the

2213

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2214

===================================================================

2215

--- a/src/libstdc++-v3/doc/html/manual/abi.html (.../tags/gcc_4_8_2_release)

2216

+++ b/src/libstdc++-v3/doc/html/manual/abi.html (.../branches/gcc-4_8-branch)

2217

@@ -1,5 +1,5 @@

2218

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

2219

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>ABI Policy and Guidelines</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="C++, ABI, version, dynamic, shared, compatibility" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B. Porting and Maintenance" /><link rel="prev" href="test.html" title="Test" /><link rel="next" href="api.html" title="API Evolution and Deprecation History" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">ABI Policy and Guidelines</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="test.html">Prev</a> </td><th width="60%" align="center">Appendix B.

2220

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>ABI Policy and Guidelines</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, ABI, version, dynamic, shared, compatibility" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B. Porting and Maintenance" /><link rel="prev" href="test.html" title="Test" /><link rel="next" href="api.html" title="API Evolution and Deprecation History" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">ABI Policy and Guidelines</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="test.html">Prev</a> </td><th width="60%" align="center">Appendix B.

2221

Porting and Maintenance

2222

2223

</th><td width="20%" align="right"> <a accesskey="n" href="api.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="appendix.porting.abi"></a>ABI Policy and Guidelines</h2></div></div></div><p>

2224

@@ -493,39 +493,39 @@

2225

2226

C++ ABI Summary

2227

</a>

2228

- </em>. </span></p></div><div class="biblioentry"><a id="idp22945936"></a><p><span class="title"><em>

2229

+ </em>. </span></p></div><div class="biblioentry"><a id="idm269992586624"></a><p><span class="title"><em>

2230

2231

Intel Compilers for Linux Compatibility with the GNU Compilers

2232

</a>

2233

- </em>. </span></p></div><div class="biblioentry"><a id="idp22947792"></a><p><span class="title"><em>

2234

+ </em>. </span></p></div><div class="biblioentry"><a id="idm269992584768"></a><p><span class="title"><em>

2235

2236

Linker and Libraries Guide (document 819-0690)

2237

</a>

2238

- </em>. </span></p></div><div class="biblioentry"><a id="idp22949632"></a><p><span class="title"><em>

2239

+ </em>. </span></p></div><div class="biblioentry"><a id="idm269992582928"></a><p><span class="title"><em>

2240

2241

Sun Studio 11: C++ Migration Guide (document 819-3689)

2242

</a>

2243

- </em>. </span></p></div><div class="biblioentry"><a id="idp22951488"></a><p><span class="title"><em>

2244

+ </em>. </span></p></div><div class="biblioentry"><a id="idm269992581072"></a><p><span class="title"><em>

2245

2246

How to Write Shared Libraries

2247

</a>

2248

- </em>. </span><span class="author"><span class="firstname">Ulrich</span> <span class="surname">Drepper</span>. </span></p></div><div class="biblioentry"><a id="idp22954928"></a><p><span class="title"><em>

2249

+ </em>. </span><span class="author"><span class="firstname">Ulrich</span> <span class="surname">Drepper</span>. </span></p></div><div class="biblioentry"><a id="idm269992577632"></a><p><span class="title"><em>

2250

2251

C++ ABI for the ARM Architecture

2252

</a>

2253

- </em>. </span></p></div><div class="biblioentry"><a id="idp22956736"></a><p><span class="title"><em>

2254

+ </em>. </span></p></div><div class="biblioentry"><a id="idm269992575824"></a><p><span class="title"><em>

2255

2256

Dynamic Shared Objects: Survey and Issues

2257

</a>

2258

</em>. </span><span class="subtitle">

2259

ISO C++ J16/06-0046

2260

- . </span><span class="author"><span class="firstname">Benjamin</span> <span class="surname">Kosnik</span>. </span></p></div><div class="biblioentry"><a id="idp22960032"></a><p><span class="title"><em>

2261

+ . </span><span class="author"><span class="firstname">Benjamin</span> <span class="surname">Kosnik</span>. </span></p></div><div class="biblioentry"><a id="idm269992572528"></a><p><span class="title"><em>

2262

2263

Versioning With Namespaces

2264

</a>

2265

</em>. </span><span class="subtitle">

2266

ISO C++ J16/06-0083

2267

- . </span><span class="author"><span class="firstname">Benjamin</span> <span class="surname">Kosnik</span>. </span></p></div><div class="biblioentry"><a id="idp22963312"></a><p><span class="title"><em>

2268

+ . </span><span class="author"><span class="firstname">Benjamin</span> <span class="surname">Kosnik</span>. </span></p></div><div class="biblioentry"><a id="idm269992569248"></a><p><span class="title"><em>

2269

2270

Binary Compatibility of Shared Libraries Implemented in C++

2271

on GNU/Linux Systems

2272

Index: libstdc++-v3/doc/html/manual/intro.html

2273

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2274

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2275

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2276

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2277

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

2278

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-</h1></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="chapter"><a href="status.html">1. Status</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#manual.intro.status.iso">Implementation Status</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#status.iso.1998">C++ 1998/2003</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.1998.status">Implementation Status</a></span></dt><dt><span class="section"><a href="status.html#iso.1998.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.2011">C++ 2011</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.2011.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.tr1">C++ TR1</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.tr1.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.tr24733">C++ TR 24733</a></span></dt></dl></dd><dt><span class="section"><a href="license.html">License</a></span></dt><dd><dl><dt><span class="section"><a href="license.html#manual.intro.status.license.gpl">The Code: GPL</a></span></dt><dt><span class="section"><a href="license.html#manual.intro.status.license.fdl">The Documentation: GPL, FDL</a></span></dt></dl></dd><dt><span class="section"><a href="bugs.html">Bugs</a></span></dt><dd><dl><dt><span class="section"><a href="bugs.html#manual.intro.status.bugs.impl">Implementation Bugs</a></span></dt><dt><span class="section"><a href="bugs.html#manual.intro.status.bugs.iso">Standard Bugs</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="setup.html">2. Setup</a></span></dt><dd><dl><dt><span class="section"><a href="setup.html#manual.intro.setup.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="configure.html">Configure</a></span></dt><dt><span class="section"><a href="make.html">Make</a></span></dt></dl></dd><dt><span class="chapter"><a href="using.html">3. Using</a></span></dt><dd><dl><dt><span class="section"><a href="using.html#manual.intro.using.flags">Command Options</a></span></dt><dt><span class="section"><a href="using_headers.html">Headers</a></span></dt><dd><dl><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.all">Header Files</a></span></dt><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.mixing">Mixing Headers</a></span></dt><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.cheaders">The C Headers and <code class="code">namespace std</code></a></span></dt><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.pre">Precompiled Headers</a></span></dt></dl></dd><dt><span class="section"><a href="using_macros.html">Macros</a></span></dt><dt><span class="section"><a href="using_namespaces.html">Namespaces</a></span></dt><dd><dl><dt><span class="section"><a href="using_namespaces.html#manual.intro.using.namespaces.all">Available Namespaces</a></span></dt><dt><span class="section"><a href="using_namespaces.html#manual.intro.using.namespaces.std">namespace std</a></span></dt><dt><span class="section"><a href="using_namespaces.html#manual.intro.using.namespaces.comp">Using Namespace Composition</a></span></dt></dl></dd><dt><span class="section"><a href="using_dynamic_or_shared.html">Linking</a></span></dt><dd><dl><dt><span class="section"><a href="using_dynamic_or_shared.html#manual.intro.using.linkage.freestanding">Almost Nothing</a></span></dt><dt><span class="section"><a href="using_dynamic_or_shared.html#manual.intro.using.linkage.dynamic">Finding Dynamic or Shared Libraries</a></span></dt></dl></dd><dt><span class="section"><a href="using_concurrency.html">Concurrency</a></span></dt><dd><dl><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.thread_safety">Thread Safety</a></span></dt><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.atomics">Atomics</a></span></dt><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.io">IO</a></span></dt><dd><dl><dt><span class="section"><a href="using_concurrency.html#concurrency.io.structure">Structure</a></span></dt><dt><span class="section"><a href="using_concurrency.html#concurrency.io.defaults">Defaults</a></span></dt><dt><span class="section"><a href="using_concurrency.html#concurrency.io.future">Future</a></span></dt><dt><span class="section"><a href="using_concurrency.html#concurrency.io.alt">Alternatives</a></span></dt></dl></dd><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.containers">Containers</a></span></dt></dl></dd><dt><span class="section"><a href="using_exceptions.html">Exceptions</a></span></dt><dd><dl><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.safety">Exception Safety</a></span></dt><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.propagating">Exception Neutrality</a></span></dt><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.no">Doing without</a></span></dt><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.compat">Compatibility</a></span></dt><dd><dl><dt><span class="section"><a href="using_exceptions.html#using.exception.compat.c">With <code class="literal">C</code></a></span></dt><dt><span class="section"><a href="using_exceptions.html#using.exception.compat.posix">With <code class="literal">POSIX</code> thread cancellation</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="debug.html">Debugging Support</a></span></dt><dd><dl><dt><span class="section"><a href="debug.html#debug.compiler">Using <span class="command"><strong>g++</strong></span></a></span></dt><dt><span class="section"><a href="debug.html#debug.req">Debug Versions of Library Binary Files</a></span></dt><dt><span class="section"><a href="debug.html#debug.memory">Memory Leak Hunting</a></span></dt><dt><span class="section"><a href="debug.html#debug.races">Data Race Hunting</a></span></dt><dt><span class="section"><a href="debug.html#debug.gdb">Using <span class="command"><strong>gdb</strong></span></a></span></dt><dt><span class="section"><a href="debug.html#debug.exceptions">Tracking uncaught exceptions</a></span></dt><dt><span class="section"><a href="debug.html#debug.debug_mode">Debug Mode</a></span></dt><dt><span class="section"><a href="debug.html#debug.compile_time_checks">Compile Time Checking</a></span></dt><dt><span class="section"><a href="debug.html#debug.profile_mode">Profile-based Performance Analysis</a></span></dt></dl></dd></dl></dd></dl></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="index.html">Prev</a> </td><td width="20%" align="center"><a accesskey="u" href="index.html">Up</a></td><td width="40%" align="right"> <a accesskey="n" href="status.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">The GNU C++ Library Manual </td><td width="20%" align="center"><a accesskey="h" href="../index.html">Home</a></td><td width="40%" align="right" valign="top"> Chapter 1. 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Status</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#manual.intro.status.iso">Implementation Status</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#status.iso.1998">C++ 1998/2003</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.1998.status">Implementation Status</a></span></dt><dt><span class="section"><a href="status.html#iso.1998.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.2011">C++ 2011</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.2011.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.tr1">C++ TR1</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.tr1.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.tr24733">C++ TR 24733</a></span></dt></dl></dd><dt><span class="section"><a href="license.html">License</a></span></dt><dd><dl><dt><span class="section"><a href="license.html#manual.intro.status.license.gpl">The Code: GPL</a></span></dt><dt><span class="section"><a href="license.html#manual.intro.status.license.fdl">The Documentation: GPL, FDL</a></span></dt></dl></dd><dt><span class="section"><a href="bugs.html">Bugs</a></span></dt><dd><dl><dt><span class="section"><a href="bugs.html#manual.intro.status.bugs.impl">Implementation Bugs</a></span></dt><dt><span class="section"><a href="bugs.html#manual.intro.status.bugs.iso">Standard Bugs</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="setup.html">2. Setup</a></span></dt><dd><dl><dt><span class="section"><a href="setup.html#manual.intro.setup.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="configure.html">Configure</a></span></dt><dt><span class="section"><a href="make.html">Make</a></span></dt></dl></dd><dt><span class="chapter"><a href="using.html">3. Using</a></span></dt><dd><dl><dt><span class="section"><a href="using.html#manual.intro.using.flags">Command Options</a></span></dt><dt><span class="section"><a href="using_headers.html">Headers</a></span></dt><dd><dl><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.all">Header Files</a></span></dt><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.mixing">Mixing Headers</a></span></dt><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.cheaders">The C Headers and <code class="code">namespace std</code></a></span></dt><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.pre">Precompiled Headers</a></span></dt></dl></dd><dt><span class="section"><a href="using_macros.html">Macros</a></span></dt><dt><span class="section"><a href="using_namespaces.html">Namespaces</a></span></dt><dd><dl><dt><span class="section"><a href="using_namespaces.html#manual.intro.using.namespaces.all">Available Namespaces</a></span></dt><dt><span class="section"><a href="using_namespaces.html#manual.intro.using.namespaces.std">namespace std</a></span></dt><dt><span class="section"><a href="using_namespaces.html#manual.intro.using.namespaces.comp">Using Namespace Composition</a></span></dt></dl></dd><dt><span class="section"><a href="using_dynamic_or_shared.html">Linking</a></span></dt><dd><dl><dt><span class="section"><a href="using_dynamic_or_shared.html#manual.intro.using.linkage.freestanding">Almost Nothing</a></span></dt><dt><span class="section"><a href="using_dynamic_or_shared.html#manual.intro.using.linkage.dynamic">Finding Dynamic or Shared Libraries</a></span></dt></dl></dd><dt><span class="section"><a href="using_concurrency.html">Concurrency</a></span></dt><dd><dl><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.thread_safety">Thread Safety</a></span></dt><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.atomics">Atomics</a></span></dt><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.io">IO</a></span></dt><dd><dl><dt><span class="section"><a href="using_concurrency.html#concurrency.io.structure">Structure</a></span></dt><dt><span class="section"><a href="using_concurrency.html#concurrency.io.defaults">Defaults</a></span></dt><dt><span class="section"><a href="using_concurrency.html#concurrency.io.future">Future</a></span></dt><dt><span class="section"><a href="using_concurrency.html#concurrency.io.alt">Alternatives</a></span></dt></dl></dd><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.containers">Containers</a></span></dt></dl></dd><dt><span class="section"><a href="using_exceptions.html">Exceptions</a></span></dt><dd><dl><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.safety">Exception Safety</a></span></dt><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.propagating">Exception Neutrality</a></span></dt><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.no">Doing without</a></span></dt><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.compat">Compatibility</a></span></dt><dd><dl><dt><span class="section"><a href="using_exceptions.html#using.exception.compat.c">With <code class="literal">C</code></a></span></dt><dt><span class="section"><a href="using_exceptions.html#using.exception.compat.posix">With <code class="literal">POSIX</code> thread cancellation</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="debug.html">Debugging Support</a></span></dt><dd><dl><dt><span class="section"><a href="debug.html#debug.compiler">Using <span class="command"><strong>g++</strong></span></a></span></dt><dt><span class="section"><a href="debug.html#debug.req">Debug Versions of Library Binary Files</a></span></dt><dt><span class="section"><a href="debug.html#debug.memory">Memory Leak Hunting</a></span></dt><dt><span class="section"><a href="debug.html#debug.races">Data Race Hunting</a></span></dt><dt><span class="section"><a href="debug.html#debug.gdb">Using <span class="command"><strong>gdb</strong></span></a></span></dt><dt><span class="section"><a href="debug.html#debug.exceptions">Tracking uncaught exceptions</a></span></dt><dt><span class="section"><a href="debug.html#debug.debug_mode">Debug Mode</a></span></dt><dt><span class="section"><a href="debug.html#debug.compile_time_checks">Compile Time Checking</a></span></dt><dt><span class="section"><a href="debug.html#debug.profile_mode">Profile-based Performance Analysis</a></span></dt></dl></dd></dl></dd></dl></div></div><div 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Facilities for atomic operations.

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-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Porting to New Hardware or Operating Systems</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, internals" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B. Porting and Maintenance" /><link rel="prev" href="documentation_hacking.html" title="Writing and Generating Documentation" /><link rel="next" href="test.html" title="Test" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Porting to New Hardware or Operating Systems</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="documentation_hacking.html">Prev</a> </td><th width="60%" align="center">Appendix B.

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Porting to New Hardware or Operating Systems</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, internals" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B. Porting and Maintenance" /><link rel="prev" href="documentation_hacking.html" title="Writing and Generating Documentation" /><link rel="next" href="test.html" title="Test" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Porting to New Hardware or Operating Systems</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="documentation_hacking.html">Prev</a> </td><th width="60%" align="center">Appendix B.

2331

Porting and Maintenance

2332

2333

</th><td width="20%" align="right"> <a accesskey="n" href="test.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="appendix.porting.internals"></a>Porting to New Hardware or Operating Systems</h2></div></div></div><p>

2334

Index: libstdc++-v3/doc/html/manual/policy_data_structures_using.html

2335

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2336

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>

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-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Using</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, policy, container, data, structure, associated, tree, trie, hash, metaprogramming" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="policy_data_structures.html" title="Chapter 22. Policy-Based Data Structures" /><link rel="prev" href="policy_data_structures.html" title="Chapter 22. Policy-Based Data Structures" /><link rel="next" href="policy_data_structures_design.html" title="Design" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Using</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="policy_data_structures.html">Prev</a> </td><th width="60%" align="center">Chapter 22. Policy-Based Data Structures</th><td width="20%" align="right"> <a accesskey="n" href="policy_data_structures_design.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="containers.pbds.using"></a>Using</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="pbds.using.prereq"></a>Prerequisites</h3></div></div></div><p>The library contains only header files, and does not require any

2341

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Using</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, policy, container, data, structure, associated, tree, trie, hash, metaprogramming" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="policy_data_structures.html" title="Chapter 22. Policy-Based Data Structures" /><link rel="prev" href="policy_data_structures.html" title="Chapter 22. Policy-Based Data Structures" /><link rel="next" href="policy_data_structures_design.html" title="Design" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Using</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="policy_data_structures.html">Prev</a> </td><th width="60%" align="center">Chapter 22. Policy-Based Data Structures</th><td width="20%" align="right"> <a accesskey="n" href="policy_data_structures_design.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="containers.pbds.using"></a>Using</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="pbds.using.prereq"></a>Prerequisites</h3></div></div></div><p>The library contains only header files, and does not require any

2342

other libraries except the standard C++ library . All classes are

2343

defined in namespace <code class="code">__gnu_pbds</code>. The library internally

2344

uses macros beginning with <code class="code">PB_DS</code>, but

2345

@@ -61,7 +61,7 @@

2346

In addition, there are the following diagnostics classes,

2347

used to report errors specific to this library's data

2348

structures.

2349

- </p><div class="figure"><a id="idp17806128"></a><p class="title"><strong>Figure 22.7. Exception Hierarchy</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_exception_hierarchy.png" align="middle" alt="Exception Hierarchy" /></div></div></div><br class="figure-break" /></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="pbds.using.tutorial"></a>Tutorial</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="pbds.using.tutorial.basic"></a>Basic Use</h4></div></div></div><p>

2350

+ </p><div class="figure"><a id="idm269997724688"></a><p class="title"><strong>Figure 22.7. Exception Hierarchy</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_exception_hierarchy.png" align="middle" alt="Exception Hierarchy" /></div></div></div><br class="figure-break" /></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="pbds.using.tutorial"></a>Tutorial</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="pbds.using.tutorial.basic"></a>Basic Use</h4></div></div></div><p>

2351

For the most part, the policy-based containers containers in

2352

namespace <code class="literal">__gnu_pbds</code> have the same interface as

2353

the equivalent containers in the standard C++ library, except for

2354

Index: libstdc++-v3/doc/html/manual/bugs.html

2355

===================================================================

2356

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2357

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2358

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2359

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

2360

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Bugs</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="status.html" title="Chapter 1. Status" /><link rel="prev" href="license.html" title="License" /><link rel="next" href="setup.html" title="Chapter 2. Setup" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Bugs</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="license.html">Prev</a> </td><th width="60%" align="center">Chapter 1. Status</th><td width="20%" align="right"> <a accesskey="n" href="setup.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.status.bugs"></a>Bugs</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.intro.status.bugs.impl"></a>Implementation Bugs</h3></div></div></div><p>

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Bugs</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="status.html" title="Chapter 1. Status" /><link rel="prev" href="license.html" title="License" /><link rel="next" href="setup.html" title="Chapter 2. Setup" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Bugs</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="license.html">Prev</a> </td><th width="60%" align="center">Chapter 1. Status</th><td width="20%" align="right"> <a accesskey="n" href="setup.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.status.bugs"></a>Bugs</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.intro.status.bugs.impl"></a>Implementation Bugs</h3></div></div></div><p>

2362

Information on known bugs, details on efforts to fix them, and

2363

fixed bugs are all available as part of the <a class="link" href="http://gcc.gnu.org/bugs/" target="_top">GCC bug tracking system</a>,

2364

with the category set to <code class="literal">libstdc++</code>.

2365

Index: libstdc++-v3/doc/html/manual/parallel_mode_using.html

2366

===================================================================

2367

--- a/src/libstdc++-v3/doc/html/manual/parallel_mode_using.html (.../tags/gcc_4_8_2_release)

2368

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2369

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2370

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

2371

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Using</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="C++, library, parallel" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="parallel_mode.html" title="Chapter 18. Parallel Mode" /><link rel="prev" href="parallel_mode_semantics.html" title="Semantics" /><link rel="next" href="parallel_mode_design.html" title="Design" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Using</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="parallel_mode_semantics.html">Prev</a> </td><th width="60%" align="center">Chapter 18. Parallel Mode</th><td width="20%" align="right"> <a accesskey="n" href="parallel_mode_design.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.parallel_mode.using"></a>Using</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="parallel_mode.using.prereq_flags"></a>Prerequisite Compiler Flags</h3></div></div></div><p>

2372

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Using</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, parallel" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="parallel_mode.html" title="Chapter 18. Parallel Mode" /><link rel="prev" href="parallel_mode_semantics.html" title="Semantics" /><link rel="next" href="parallel_mode_design.html" title="Design" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Using</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="parallel_mode_semantics.html">Prev</a> </td><th width="60%" align="center">Chapter 18. Parallel Mode</th><td width="20%" align="right"> <a accesskey="n" href="parallel_mode_design.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.parallel_mode.using"></a>Using</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="parallel_mode.using.prereq_flags"></a>Prerequisite Compiler Flags</h3></div></div></div><p>

2373

Any use of parallel functionality requires additional compiler

2374

and runtime support, in particular support for OpenMP. Adding this support is

2375

not difficult: just compile your application with the compiler

2376

@@ -62,4 +62,4 @@

2377

flags for atomic operations.)

2378

</p><p> The following table provides the names and headers of all the

2379

parallel algorithms that can be used in a similar manner:

2380

-</p><div class="table"><a id="idp16725920"></a><p class="title"><strong>Table 18.1. Parallel Algorithms</strong></p><div class="table-contents"><table summary="Parallel Algorithms" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Algorithm</th><th align="left">Header</th><th align="left">Parallel algorithm</th><th align="left">Parallel header</th></tr></thead><tbody><tr><td align="left"><code class="function">std::accumulate</code></td><td align="left"><code class="filename">numeric</code></td><td align="left"><code class="function">__gnu_parallel::accumulate</code></td><td align="left"><code class="filename">parallel/numeric</code></td></tr><tr><td align="left"><code class="function">std::adjacent_difference</code></td><td align="left"><code class="filename">numeric</code></td><td align="left"><code class="function">__gnu_parallel::adjacent_difference</code></td><td align="left"><code class="filename">parallel/numeric</code></td></tr><tr><td align="left"><code class="function">std::inner_product</code></td><td align="left"><code class="filename">numeric</code></td><td align="left"><code class="function">__gnu_parallel::inner_product</code></td><td align="left"><code class="filename">parallel/numeric</code></td></tr><tr><td align="left"><code class="function">std::partial_sum</code></td><td align="left"><code class="filename">numeric</code></td><td align="left"><code class="function">__gnu_parallel::partial_sum</code></td><td align="left"><code class="filename">parallel/numeric</code></td></tr><tr><td align="left"><code class="function">std::adjacent_find</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::adjacent_find</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::count</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::count</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::count_if</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::count_if</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::equal</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::equal</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::find</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::find</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::find_if</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::find_if</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::find_first_of</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::find_first_of</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::for_each</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::for_each</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::generate</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::generate</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::generate_n</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::generate_n</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::lexicographical_compare</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::lexicographical_compare</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::mismatch</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::mismatch</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::search</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::search</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::search_n</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::search_n</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::transform</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::transform</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::replace</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::replace</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::replace_if</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::replace_if</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::max_element</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::max_element</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::merge</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::merge</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::min_element</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::min_element</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::nth_element</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::nth_element</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::partial_sort</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::partial_sort</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::partition</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::partition</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::random_shuffle</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::random_shuffle</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::set_union</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::set_union</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::set_intersection</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::set_intersection</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::set_symmetric_difference</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::set_symmetric_difference</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::set_difference</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::set_difference</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::sort</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::sort</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::stable_sort</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::stable_sort</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::unique_copy</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::unique_copy</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr></tbody></table></div></div><br class="table-break" /></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="parallel_mode_semantics.html">Prev</a> </td><td width="20%" align="center"><a accesskey="u" href="parallel_mode.html">Up</a></td><td width="40%" align="right"> <a accesskey="n" href="parallel_mode_design.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">Semantics </td><td width="20%" align="center"><a accesskey="h" href="../index.html">Home</a></td><td width="40%" align="right" valign="top"> Design</td></tr></table></div></body></html>

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+</p><div class="table"><a id="idm269998805216"></a><p class="title"><strong>Table 18.1. Parallel Algorithms</strong></p><div class="table-contents"><table summary="Parallel Algorithms" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Algorithm</th><th align="left">Header</th><th align="left">Parallel algorithm</th><th align="left">Parallel header</th></tr></thead><tbody><tr><td align="left"><code class="function">std::accumulate</code></td><td align="left"><code class="filename">numeric</code></td><td align="left"><code class="function">__gnu_parallel::accumulate</code></td><td align="left"><code class="filename">parallel/numeric</code></td></tr><tr><td align="left"><code class="function">std::adjacent_difference</code></td><td align="left"><code class="filename">numeric</code></td><td align="left"><code class="function">__gnu_parallel::adjacent_difference</code></td><td align="left"><code class="filename">parallel/numeric</code></td></tr><tr><td align="left"><code class="function">std::inner_product</code></td><td align="left"><code class="filename">numeric</code></td><td align="left"><code class="function">__gnu_parallel::inner_product</code></td><td align="left"><code class="filename">parallel/numeric</code></td></tr><tr><td align="left"><code class="function">std::partial_sum</code></td><td align="left"><code class="filename">numeric</code></td><td align="left"><code class="function">__gnu_parallel::partial_sum</code></td><td align="left"><code class="filename">parallel/numeric</code></td></tr><tr><td align="left"><code class="function">std::adjacent_find</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::adjacent_find</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::count</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::count</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::count_if</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::count_if</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::equal</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::equal</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::find</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::find</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::find_if</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::find_if</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::find_first_of</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::find_first_of</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::for_each</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::for_each</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::generate</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::generate</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::generate_n</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::generate_n</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::lexicographical_compare</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::lexicographical_compare</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::mismatch</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::mismatch</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::search</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::search</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::search_n</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::search_n</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::transform</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::transform</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::replace</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::replace</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::replace_if</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::replace_if</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::max_element</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::max_element</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::merge</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::merge</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::min_element</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::min_element</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::nth_element</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::nth_element</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::partial_sort</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::partial_sort</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::partition</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::partition</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::random_shuffle</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::random_shuffle</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::set_union</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::set_union</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::set_intersection</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::set_intersection</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::set_symmetric_difference</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::set_symmetric_difference</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::set_difference</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::set_difference</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::sort</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::sort</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::stable_sort</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::stable_sort</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::unique_copy</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::unique_copy</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr></tbody></table></div></div><br class="table-break" /></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="parallel_mode_semantics.html">Prev</a> </td><td width="20%" align="center"><a accesskey="u" href="parallel_mode.html">Up</a></td><td width="40%" align="right"> <a accesskey="n" href="parallel_mode_design.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">Semantics </td><td width="20%" align="center"><a accesskey="h" href="../index.html">Home</a></td><td width="40%" align="right" valign="top"> Design</td></tr></table></div></body></html>

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+</a></span></dt><dd><dl><dt><span class="section"><a href="utilities.html#std.util.functors">Functors</a></span></dt><dt><span class="section"><a href="pairs.html">Pairs</a></span></dt><dt><span class="section"><a href="memory.html">Memory</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#std.util.memory.allocator">Allocators</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#allocator.req">Requirements</a></span></dt><dt><span class="section"><a href="memory.html#allocator.design_issues">Design Issues</a></span></dt><dt><span class="section"><a href="memory.html#allocator.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idm270001611968">Interface Design</a></span></dt><dt><span class="section"><a href="memory.html#idm270001608416">Selecting Default Allocation Policy</a></span></dt><dt><span class="section"><a href="memory.html#idm270001595120">Disabling Memory Caching</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#allocator.using">Using a Specific Allocator</a></span></dt><dt><span class="section"><a href="memory.html#allocator.custom">Custom Allocators</a></span></dt><dt><span class="section"><a href="memory.html#allocator.ext">Extension Allocators</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#std.util.memory.auto_ptr">auto_ptr</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#auto_ptr.limitations">Limitations</a></span></dt><dt><span class="section"><a href="memory.html#auto_ptr.using">Use in Containers</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#std.util.memory.shared_ptr">shared_ptr</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#shared_ptr.req">Requirements</a></span></dt><dt><span class="section"><a href="memory.html#shared_ptr.design_issues">Design Issues</a></span></dt><dt><span class="section"><a href="memory.html#shared_ptr.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idm270000019344">Class Hierarchy</a></span></dt><dt><span class="section"><a href="memory.html#idm269999996832">Thread Safety</a></span></dt><dt><span class="section"><a href="memory.html#idm269999989536">Selecting Lock Policy</a></span></dt><dt><span class="section"><a href="memory.html#idm269999974912">Related functions and classes</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#shared_ptr.using">Use</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idm269999958496">Examples</a></span></dt><dt><span class="section"><a href="memory.html#idm269999954912">Unresolved Issues</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#shared_ptr.ack">Acknowledgments</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="traits.html">Traits</a></span></dt></dl></dd><dt><span class="chapter"><a href="strings.html">7.

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</a></span></dt><dd><dl><dt><span class="section"><a href="strings.html#std.strings.string">String Classes</a></span></dt><dd><dl><dt><span class="section"><a href="strings.html#strings.string.simple">Simple Transformations</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.case">Case Sensitivity</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.character_types">Arbitrary Character Types</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.token">Tokenizing</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.shrink">Shrink to Fit</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.Cstring">CString (MFC)</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="localization.html">8.

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Localization

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-</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#std.localization.locales">Locales</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#std.localization.locales.locale">locale</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#locales.locale.req">Requirements</a></span></dt><dt><span class="section"><a href="localization.html#locales.locale.design">Design</a></span></dt><dt><span class="section"><a href="localization.html#locales.locale.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#locale.impl.c">Interacting with "C" locales</a></span></dt></dl></dd><dt><span class="section"><a href="localization.html#locales.locale.future">Future</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="facets.html">Facets</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#std.localization.facet.ctype">ctype</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.ctype.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#idp15778336">Specializations</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.ctype.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#std.localization.facet.codecvt">codecvt</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.codecvt.req">Requirements</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.design">Design</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#codecvt.design.wchar_t_size"><span class="type">wchar_t</span> Size</a></span></dt><dt><span class="section"><a href="facets.html#codecvt.design.unicode">Support for Unicode</a></span></dt><dt><span class="section"><a href="facets.html#codecvt.design.issues">Other Issues</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.codecvt.impl">Implementation</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.use">Use</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#manual.localization.facet.messages">messages</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.messages.req">Requirements</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.design">Design</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#messages.impl.models">Models</a></span></dt><dt><span class="section"><a href="facets.html#messages.impl.gnu">The GNU Model</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.messages.use">Use</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.future">Future</a></span></dt></dl></dd></dl></dd></dl></dd><dt><span class="chapter"><a href="containers.html">9.

2434

+</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#std.localization.locales">Locales</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#std.localization.locales.locale">locale</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#locales.locale.req">Requirements</a></span></dt><dt><span class="section"><a href="localization.html#locales.locale.design">Design</a></span></dt><dt><span class="section"><a href="localization.html#locales.locale.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#locale.impl.c">Interacting with "C" locales</a></span></dt></dl></dd><dt><span class="section"><a href="localization.html#locales.locale.future">Future</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="facets.html">Facets</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#std.localization.facet.ctype">ctype</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.ctype.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#idm269999753024">Specializations</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.ctype.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#std.localization.facet.codecvt">codecvt</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.codecvt.req">Requirements</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.design">Design</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#codecvt.design.wchar_t_size"><span class="type">wchar_t</span> Size</a></span></dt><dt><span class="section"><a href="facets.html#codecvt.design.unicode">Support for Unicode</a></span></dt><dt><span class="section"><a href="facets.html#codecvt.design.issues">Other Issues</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.codecvt.impl">Implementation</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.use">Use</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#manual.localization.facet.messages">messages</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.messages.req">Requirements</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.design">Design</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#messages.impl.models">Models</a></span></dt><dt><span class="section"><a href="facets.html#messages.impl.gnu">The GNU Model</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.messages.use">Use</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.future">Future</a></span></dt></dl></dd></dl></dd></dl></dd><dt><span class="chapter"><a href="containers.html">9.

2435

Containers

2436

2437

</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#std.containers.sequences">Sequences</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#containers.sequences.list">list</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#sequences.list.size">list::size() is O(n)</a></span></dt></dl></dd><dt><span class="section"><a href="containers.html#containers.sequences.vector">vector</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#sequences.vector.management">Space Overhead Management</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="associative.html">Associative</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#containers.associative.insert_hints">Insertion Hints</a></span></dt><dt><span class="section"><a href="associative.html#containers.associative.bitset">bitset</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#associative.bitset.size_variable">Size Variable</a></span></dt><dt><span class="section"><a href="associative.html#associative.bitset.type_string">Type String</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="unordered_associative.html">Unordered Associative</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.hash">Hash Code</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.cache">Hash Code Caching Policy</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="containers_and_c.html">Interacting with C</a></span></dt><dd><dl><dt><span class="section"><a href="containers_and_c.html#containers.c.vs_array">Containers vs. Arrays</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="iterators.html">10.

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2439

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2440

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2441

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2442

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2443

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

2444

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Part IV. Appendices</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="index.html" title="The GNU C++ Library Manual" /><link rel="prev" href="ext_concurrency_use.html" title="Use" /><link rel="next" href="appendix_contributing.html" title="Appendix A. Contributing" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Part IV.

2445

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Part IV. Appendices</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="index.html" title="The GNU C++ Library Manual" /><link rel="prev" href="ext_concurrency_use.html" title="Use" /><link rel="next" href="appendix_contributing.html" title="Appendix A. Contributing" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Part IV.

2446

Appendices

2447

</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_concurrency_use.html">Prev</a> </td><th width="60%" align="center">The GNU C++ Library Manual</th><td width="20%" align="right"> <a accesskey="n" href="appendix_contributing.html">Next</a></td></tr></table><hr /></div><div class="part"><div class="titlepage"><div><div><h1 class="title"><a id="appendix"></a>Part IV.

2448

Appendices

2449

-</h1></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="appendix"><a href="appendix_contributing.html">A.

2450

+</h1></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="appendix"><a href="appendix_contributing.html">A.

2451

Contributing

2452

2453

</a></span></dt><dd><dl><dt><span class="section"><a href="appendix_contributing.html#contrib.list">Contributor Checklist</a></span></dt><dd><dl><dt><span class="section"><a href="appendix_contributing.html#list.reading">Reading</a></span></dt><dt><span class="section"><a href="appendix_contributing.html#list.copyright">Assignment</a></span></dt><dt><span class="section"><a href="appendix_contributing.html#list.getting">Getting Sources</a></span></dt><dt><span class="section"><a href="appendix_contributing.html#list.patches">Submitting Patches</a></span></dt></dl></dd><dt><span class="section"><a href="source_organization.html">Directory Layout and Source Conventions</a></span></dt><dt><span class="section"><a href="source_code_style.html">Coding Style</a></span></dt><dd><dl><dt><span class="section"><a href="source_code_style.html#coding_style.bad_identifiers">Bad Identifiers</a></span></dt><dt><span class="section"><a href="source_code_style.html#coding_style.example">By Example</a></span></dt></dl></dd><dt><span class="section"><a href="source_design_notes.html">Design Notes</a></span></dt></dl></dd><dt><span class="appendix"><a href="appendix_porting.html">B.

2454

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2455

===================================================================

2456

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2457

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2458

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2459

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

2460

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Memory</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="utilities.html" title="Chapter 6. Utilities" /><link rel="prev" href="pairs.html" title="Pairs" /><link rel="next" href="traits.html" title="Traits" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Memory</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="pairs.html">Prev</a> </td><th width="60%" align="center">Chapter 6.

2461

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Memory</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="utilities.html" title="Chapter 6. Utilities" /><link rel="prev" href="pairs.html" title="Pairs" /><link rel="next" href="traits.html" title="Traits" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Memory</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="pairs.html">Prev</a> </td><th width="60%" align="center">Chapter 6.

2462

Utilities

2463

2464

</th><td width="20%" align="right"> <a accesskey="n" href="traits.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.util.memory"></a>Memory</h2></div></div></div><p>

2465

@@ -92,7 +92,7 @@

2466

or loading and unloading shared objects in memory. As such, using

2467

caching allocators on systems that do not support

2468

<code class="function">abi::__cxa_atexit</code> is not recommended.

2469

- </p></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="allocator.impl"></a>Implementation</h4></div></div></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idp13920976"></a>Interface Design</h5></div></div></div><p>

2470

+ </p></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="allocator.impl"></a>Implementation</h4></div></div></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idm270001611968"></a>Interface Design</h5></div></div></div><p>

2471

The only allocator interface that

2472

is supported is the standard C++ interface. As such, all STL

2473

containers have been adjusted, and all external allocators have

2474

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2475

</p><p>

2476

The base class that <code class="classname">allocator</code> is derived from

2477

may not be user-configurable.

2478

-</p></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idp13924528"></a>Selecting Default Allocation Policy</h5></div></div></div><p>

2479

+</p></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idm270001608416"></a>Selecting Default Allocation Policy</h5></div></div></div><p>

2480

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2481

maximum utility, without excessively penalizing some behavior. In

2482

fact, it's difficult just deciding which typical actions to measure

2483

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2484

The current default choice for

2485

<code class="classname">allocator</code> is

2486

<code class="classname">__gnu_cxx::new_allocator</code>.

2487

- </p></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idp13937824"></a>Disabling Memory Caching</h5></div></div></div><p>

2488

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2489

In use, <code class="classname">allocator</code> may allocate and

2490

deallocate using implementation-specific strategies and

2491

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2492

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2493

of the used and unused memory locations. It has its own

2494

<a class="link" href="bitmap_allocator.html" title="Chapter 21. The bitmap_allocator">chapter</a>

2495

in the documentation.

2496

- </p></li></ol></div></div><div class="bibliography"><div class="titlepage"><div><div><h4 class="title"><a id="allocator.biblio"></a>Bibliography</h4></div></div></div><div class="biblioentry"><a id="idp13992848"></a><p><span class="citetitle"><em class="citetitle">

2497

+ </p></li></ol></div></div><div class="bibliography"><div class="titlepage"><div><div><h4 class="title"><a id="allocator.biblio"></a>Bibliography</h4></div></div></div><div class="biblioentry"><a id="idm270000084224"></a><p><span class="citetitle"><em class="citetitle">

2498

ISO/IEC 14882:1998 Programming languages - C++

2499

</em>. </span>

2500

isoc++_1998

2501

- <span class="pagenums">20.4 Memory. </span></p></div><div class="biblioentry"><a id="idp13994688"></a><p><span class="title"><em>

2502

- <a class="link" href="http://www.drdobbs.com/cpp/184403759" target="_top">

2503

+ <span class="pagenums">20.4 Memory. </span></p></div><div class="biblioentry"><a id="idm270000082384"></a><p><span class="title"><em>

2504

+ <a class="link" href="http://www.drdobbs.com/the-standard-librarian-what-are-allocato/184403759" target="_top">

2505

The Standard Librarian: What Are Allocators Good For?

2506

</a>

2507

</em>. </span><span class="author"><span class="firstname">Matt</span> <span class="surname">Austern</span>. </span><span class="publisher"><span class="publishername">

2508

C/C++ Users Journal

2509

- . </span></span></p></div><div class="biblioentry"><a id="idp13998416"></a><p><span class="title"><em>

2510

+ . </span></span></p></div><div class="biblioentry"><a id="idm270000078608"></a><p><span class="title"><em>

2511

2512

The Hoard Memory Allocator

2513

</a>

2514

- </em>. </span><span class="author"><span class="firstname">Emery</span> <span class="surname">Berger</span>. </span></p></div><div class="biblioentry"><a id="idp14001184"></a><p><span class="title"><em>

2515

+ </em>. </span><span class="author"><span class="firstname">Emery</span> <span class="surname">Berger</span>. </span></p></div><div class="biblioentry"><a id="idm270000075840"></a><p><span class="title"><em>

2516

2517

Reconsidering Custom Memory Allocation

2518

</a>

2519

- </em>. </span><span class="author"><span class="firstname">Emery</span> <span class="surname">Berger</span>. </span><span class="author"><span class="firstname">Ben</span> <span class="surname">Zorn</span>. </span><span class="author"><span class="firstname">Kathryn</span> <span class="surname">McKinley</span>. </span><span class="copyright">Copyright © 2002 OOPSLA. </span></p></div><div class="biblioentry"><a id="idp14007344"></a><p><span class="title"><em>

2520

+ </em>. </span><span class="author"><span class="firstname">Emery</span> <span class="surname">Berger</span>. </span><span class="author"><span class="firstname">Ben</span> <span class="surname">Zorn</span>. </span><span class="author"><span class="firstname">Kathryn</span> <span class="surname">McKinley</span>. </span><span class="copyright">Copyright © 2002 OOPSLA. </span></p></div><div class="biblioentry"><a id="idm270000069680"></a><p><span class="title"><em>

2521

2522

Allocator Types

2523

</a>

2524

</em>. </span><span class="author"><span class="firstname">Klaus</span> <span class="surname">Kreft</span>. </span><span class="author"><span class="firstname">Angelika</span> <span class="surname">Langer</span>. </span><span class="publisher"><span class="publishername">

2525

C/C++ Users Journal

2526

- . </span></span></p></div><div class="biblioentry"><a id="idp14012080"></a><p><span class="citetitle"><em class="citetitle">The C++ Programming Language</em>. </span><span class="author"><span class="firstname">Bjarne</span> <span class="surname">Stroustrup</span>. </span><span class="copyright">Copyright © 2000 . </span><span class="pagenums">19.4 Allocators. </span><span class="publisher"><span class="publishername">

2527

+ . </span></span></p></div><div class="biblioentry"><a id="idm270000064944"></a><p><span class="citetitle"><em class="citetitle">The C++ Programming Language</em>. </span><span class="author"><span class="firstname">Bjarne</span> <span class="surname">Stroustrup</span>. </span><span class="copyright">Copyright © 2000 . </span><span class="pagenums">19.4 Allocators. </span><span class="publisher"><span class="publishername">

2528

Addison Wesley

2529

- . </span></span></p></div><div class="biblioentry"><a id="idp14016512"></a><p><span class="citetitle"><em class="citetitle">Yalloc: A Recycling C++ Allocator</em>. </span><span class="author"><span class="firstname">Felix</span> <span class="surname">Yen</span>. </span></p></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="std.util.memory.auto_ptr"></a>auto_ptr</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="auto_ptr.limitations"></a>Limitations</h4></div></div></div><p>Explaining all of the fun and delicious things that can

2530

+ . </span></span></p></div><div class="biblioentry"><a id="idm270000060512"></a><p><span class="citetitle"><em class="citetitle">Yalloc: A Recycling C++ Allocator</em>. </span><span class="author"><span class="firstname">Felix</span> <span class="surname">Yen</span>. </span></p></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="std.util.memory.auto_ptr"></a>auto_ptr</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="auto_ptr.limitations"></a>Limitations</h4></div></div></div><p>Explaining all of the fun and delicious things that can

2531

happen with misuse of the <code class="classname">auto_ptr</code> class

2532

template (called <acronym class="acronym">AP</acronym> here) would take some

2533

time. Suffice it to say that the use of <acronym class="acronym">AP</acronym>

2534

@@ -445,7 +445,7 @@

2535

Derived classes override those functions to destroy resources in a context

2536

where the correct dynamic type is known. This is an application of the

2537

technique known as type erasure.

2538

- </p></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="shared_ptr.impl"></a>Implementation</h4></div></div></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idp15512272"></a>Class Hierarchy</h5></div></div></div><p>

2539

+ </p></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="shared_ptr.impl"></a>Implementation</h4></div></div></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idm270000019344"></a>Class Hierarchy</h5></div></div></div><p>

2540

A <code class="classname">shared_ptr<T></code> contains a pointer of

2541

type <span class="type">T*</span> and an object of type

2542

<code class="classname">__shared_count</code>. The shared_count contains a

2543

@@ -492,9 +492,9 @@

2544

aliasing constructor, make_shared & allocate_shared. Additionally,

2545

the constructors taking <code class="classname">auto_ptr</code> parameters are

2546

deprecated in C++11 mode.

2547

- </p></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idp15534784"></a>Thread Safety</h5></div></div></div><p>

2548

+ </p></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idm269999996832"></a>Thread Safety</h5></div></div></div><p>

2549

The

2550

-<a class="link" href="http://boost.org/libs/smart_ptr/shared_ptr.htm#ThreadSafety" target="_top">Thread

2551

+<a class="link" href="http://www.boost.org/libs/smart_ptr/shared_ptr.htm#ThreadSafety" target="_top">Thread

2552

Safety</a> section of the Boost shared_ptr documentation says "shared_ptr

2553

objects offer the same level of thread safety as built-in types."

2554

The implementation must ensure that concurrent updates to separate shared_ptr

2555

@@ -537,7 +537,7 @@

2556

shared_ptr in libstdc++ the compiler and library are fixed, which

2557

makes things much simpler: we have an atomic CAS or we don't, see Lock

2558

Policy below for details.

2559

-</p></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idp15542080"></a>Selecting Lock Policy</h5></div></div></div><p>

2560

+</p></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idm269999989536"></a>Selecting Lock Policy</h5></div></div></div><p>

2561

</p><p>

2562

There is a single <code class="classname">_Sp_counted_base</code> class,

2563

which is a template parameterized on the enum

2564

@@ -578,7 +578,7 @@

2565

<code class="filename">ext/atomicity.h</code>, which detect if the program

2566

is multi-threaded. If only one thread of execution exists in

2567

the program then less expensive non-atomic operations are used.

2568

- </p></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idp15556704"></a>Related functions and classes</h5></div></div></div><div class="variablelist"><dl class="variablelist"><dt><span class="term"><code class="code">dynamic_pointer_cast</code>, <code class="code">static_pointer_cast</code>,

2569

+ </p></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idm269999974912"></a>Related functions and classes</h5></div></div></div><div class="variablelist"><dl class="variablelist"><dt><span class="term"><code class="code">dynamic_pointer_cast</code>, <code class="code">static_pointer_cast</code>,

2570

<code class="code">const_pointer_cast</code></span></dt><dd><p>

2571

As noted in N2351, these functions can be implemented non-intrusively using

2572

the alias constructor. However the aliasing constructor is only available

2573

@@ -611,13 +611,13 @@

2574

As well as the extra constructors, this implementation also needs some

2575

members of _Sp_counted_deleter to be protected where they could otherwise

2576

be private.

2577

- </p></dd></dl></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="shared_ptr.using"></a>Use</h4></div></div></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idp15573056"></a>Examples</h5></div></div></div><p>

2578

+ </p></dd></dl></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="shared_ptr.using"></a>Use</h4></div></div></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idm269999958496"></a>Examples</h5></div></div></div><p>

2579

Examples of use can be found in the testsuite, under

2580

<code class="filename">testsuite/tr1/2_general_utilities/shared_ptr</code>,

2581

<code class="filename">testsuite/20_util/shared_ptr</code>

2582

and

2583

<code class="filename">testsuite/20_util/weak_ptr</code>.

2584

- </p></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idp15576640"></a>Unresolved Issues</h5></div></div></div><p>

2585

+ </p></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idm269999954912"></a>Unresolved Issues</h5></div></div></div><p>

2586

The <span class="emphasis"><em><code class="classname">shared_ptr</code> atomic access</em></span>

2587

clause in the C++11 standard is not implemented in GCC.

2588

</p><p>

2589

@@ -658,25 +658,25 @@

2590

code to work with, Peter Dimov in particular for his help and

2591

invaluable advice on thread safety. Phillip Jordan and Paolo

2592

Carlini for the lock policy implementation.

2593

- </p></div><div class="bibliography"><div class="titlepage"><div><div><h4 class="title"><a id="shared_ptr.biblio"></a>Bibliography</h4></div></div></div><div class="biblioentry"><a id="idp15587936"></a><p><span class="title"><em>

2594

+ </p></div><div class="bibliography"><div class="titlepage"><div><div><h4 class="title"><a id="shared_ptr.biblio"></a>Bibliography</h4></div></div></div><div class="biblioentry"><a id="idm269999943680"></a><p><span class="title"><em>

2595

2596

Improving shared_ptr for C++0x, Revision 2

2597

</a>

2598

</em>. </span><span class="subtitle">

2599

N2351

2600

- . </span></p></div><div class="biblioentry"><a id="idp15590224"></a><p><span class="title"><em>

2601

+ . </span></p></div><div class="biblioentry"><a id="idm269999941392"></a><p><span class="title"><em>

2602

2603

C++ Standard Library Active Issues List

2604

</a>

2605

</em>. </span><span class="subtitle">

2606

N2456

2607

- . </span></p></div><div class="biblioentry"><a id="idp15592512"></a><p><span class="title"><em>

2608

+ . </span></p></div><div class="biblioentry"><a id="idm269999939104"></a><p><span class="title"><em>

2609

2610

Working Draft, Standard for Programming Language C++

2611

</a>

2612

</em>. </span><span class="subtitle">

2613

N2461

2614

- . </span></p></div><div class="biblioentry"><a id="idp15594816"></a><p><span class="title"><em>

2615

+ . </span></p></div><div class="biblioentry"><a id="idm269999936800"></a><p><span class="title"><em>

2616

2617

Boost C++ Libraries documentation, shared_ptr

2618

</a>

2619

Index: libstdc++-v3/doc/html/manual/api.html

2620

===================================================================

2621

--- a/src/libstdc++-v3/doc/html/manual/api.html (.../tags/gcc_4_8_2_release)

2622

+++ b/src/libstdc++-v3/doc/html/manual/api.html (.../branches/gcc-4_8-branch)

2623

@@ -1,5 +1,5 @@

2624

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

2625

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>API Evolution and Deprecation History</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, api, evolution, deprecation, history" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B. Porting and Maintenance" /><link rel="prev" href="abi.html" title="ABI Policy and Guidelines" /><link rel="next" href="backwards.html" title="Backwards Compatibility" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">API Evolution and Deprecation History</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="abi.html">Prev</a> </td><th width="60%" align="center">Appendix B.

2626

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>API Evolution and Deprecation History</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, api, evolution, deprecation, history" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B. Porting and Maintenance" /><link rel="prev" href="abi.html" title="ABI Policy and Guidelines" /><link rel="next" href="backwards.html" title="Backwards Compatibility" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">API Evolution and Deprecation History</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="abi.html">Prev</a> </td><th width="60%" align="center">Appendix B.

2627

Porting and Maintenance

2628

2629

</th><td width="20%" align="right"> <a accesskey="n" href="backwards.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="appendix.porting.api"></a>API Evolution and Deprecation History</h2></div></div></div><p>

2630

@@ -77,11 +77,11 @@

2631

<span class="type">__alloc</span> to select an underlying allocator that

2632

satisfied memory allocation requests. The selection of this

2633

underlying allocator was not user-configurable.

2634

- </p><div class="table"><a id="idp23030528"></a><p class="title"><strong>Table B.6. Extension Allocators</strong></p><div class="table-contents"><table summary="Extension Allocators" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Allocator (3.4)</th><th align="left">Header (3.4)</th><th align="left">Allocator (3.[0-3])</th><th align="left">Header (3.[0-3])</th></tr></thead><tbody><tr><td align="left"><code class="classname">__gnu_cxx::new_allocator<T></code></td><td align="left"><code class="filename">ext/new_allocator.h</code></td><td align="left"><code class="classname">std::__new_alloc</code></td><td align="left"><code class="filename">memory</code></td></tr><tr><td align="left"><code class="classname">__gnu_cxx::malloc_allocator<T></code></td><td align="left"><code class="filename">ext/malloc_allocator.h</code></td><td align="left"><code class="classname">std::__malloc_alloc_template<int></code></td><td align="left"><code class="filename">memory</code></td></tr><tr><td align="left"><code class="classname">__gnu_cxx::debug_allocator<T></code></td><td align="left"><code class="filename">ext/debug_allocator.h</code></td><td align="left"><code class="classname">std::debug_alloc<T></code></td><td align="left"><code class="filename">memory</code></td></tr><tr><td align="left"><code class="classname">__gnu_cxx::__pool_alloc<T></code></td><td align="left"><code class="filename">ext/pool_allocator.h</code></td><td align="left"><code class="classname">std::__default_alloc_template<bool,int></code></td><td align="left"><code class="filename">memory</code></td></tr><tr><td align="left"><code class="classname">__gnu_cxx::__mt_alloc<T></code></td><td align="left"><code class="filename">ext/mt_allocator.h</code></td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left"><code class="classname">__gnu_cxx::bitmap_allocator<T></code></td><td align="left"><code class="filename">ext/bitmap_allocator.h</code></td><td align="left"> </td><td align="left"> </td></tr></tbody></table></div></div><br class="table-break" /><p> Releases after gcc-3.4 have continued to add to the collection

2635

+ </p><div class="table"><a id="idm269992502096"></a><p class="title"><strong>Table B.6. Extension Allocators</strong></p><div class="table-contents"><table summary="Extension Allocators" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Allocator (3.4)</th><th align="left">Header (3.4)</th><th align="left">Allocator (3.[0-3])</th><th align="left">Header (3.[0-3])</th></tr></thead><tbody><tr><td align="left"><code class="classname">__gnu_cxx::new_allocator<T></code></td><td align="left"><code class="filename">ext/new_allocator.h</code></td><td align="left"><code class="classname">std::__new_alloc</code></td><td align="left"><code class="filename">memory</code></td></tr><tr><td align="left"><code class="classname">__gnu_cxx::malloc_allocator<T></code></td><td align="left"><code class="filename">ext/malloc_allocator.h</code></td><td align="left"><code class="classname">std::__malloc_alloc_template<int></code></td><td align="left"><code class="filename">memory</code></td></tr><tr><td align="left"><code class="classname">__gnu_cxx::debug_allocator<T></code></td><td align="left"><code class="filename">ext/debug_allocator.h</code></td><td align="left"><code class="classname">std::debug_alloc<T></code></td><td align="left"><code class="filename">memory</code></td></tr><tr><td align="left"><code class="classname">__gnu_cxx::__pool_alloc<T></code></td><td align="left"><code class="filename">ext/pool_allocator.h</code></td><td align="left"><code class="classname">std::__default_alloc_template<bool,int></code></td><td align="left"><code class="filename">memory</code></td></tr><tr><td align="left"><code class="classname">__gnu_cxx::__mt_alloc<T></code></td><td align="left"><code class="filename">ext/mt_allocator.h</code></td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left"><code class="classname">__gnu_cxx::bitmap_allocator<T></code></td><td align="left"><code class="filename">ext/bitmap_allocator.h</code></td><td align="left"> </td><td align="left"> </td></tr></tbody></table></div></div><br class="table-break" /><p> Releases after gcc-3.4 have continued to add to the collection

2636

of available allocators. All of these new allocators are

2637

standard-style. The following table includes details, along with

2638

the first released version of GCC that included the extension allocator.

2639

- </p><div class="table"><a id="idp23058160"></a><p class="title"><strong>Table B.7. Extension Allocators Continued</strong></p><div class="table-contents"><table summary="Extension Allocators Continued" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left">Allocator</th><th align="left">Include</th><th align="left">Version</th></tr></thead><tbody><tr><td align="left"><code class="classname">__gnu_cxx::array_allocator<T></code></td><td align="left"><code class="filename">ext/array_allocator.h</code></td><td align="left">4.0.0</td></tr><tr><td align="left"><code class="classname">__gnu_cxx::throw_allocator<T></code></td><td align="left"><code class="filename">ext/throw_allocator.h</code></td><td align="left">4.2.0</td></tr></tbody></table></div></div><br class="table-break" /><p>

2640

+ </p><div class="table"><a id="idm269992474464"></a><p class="title"><strong>Table B.7. Extension Allocators Continued</strong></p><div class="table-contents"><table summary="Extension Allocators Continued" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left">Allocator</th><th align="left">Include</th><th align="left">Version</th></tr></thead><tbody><tr><td align="left"><code class="classname">__gnu_cxx::array_allocator<T></code></td><td align="left"><code class="filename">ext/array_allocator.h</code></td><td align="left">4.0.0</td></tr><tr><td align="left"><code class="classname">__gnu_cxx::throw_allocator<T></code></td><td align="left"><code class="filename">ext/throw_allocator.h</code></td><td align="left">4.2.0</td></tr></tbody></table></div></div><br class="table-break" /><p>

2641

Debug mode first appears.

2642

</p><p>

2643

Precompiled header support <acronym class="acronym">PCH</acronym> support.

2644

Index: libstdc++-v3/doc/html/manual/source_organization.html

2645

===================================================================

2646

--- a/src/libstdc++-v3/doc/html/manual/source_organization.html (.../tags/gcc_4_8_2_release)

2647

+++ b/src/libstdc++-v3/doc/html/manual/source_organization.html (.../branches/gcc-4_8-branch)

2648

@@ -1,5 +1,5 @@

2649

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

2650

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Directory Layout and Source Conventions</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_contributing.html" title="Appendix A. Contributing" /><link rel="prev" href="appendix_contributing.html" title="Appendix A. Contributing" /><link rel="next" href="source_code_style.html" title="Coding Style" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Directory Layout and Source Conventions</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="appendix_contributing.html">Prev</a> </td><th width="60%" align="center">Appendix A.

2651

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Directory Layout and Source Conventions</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_contributing.html" title="Appendix A. Contributing" /><link rel="prev" href="appendix_contributing.html" title="Appendix A. Contributing" /><link rel="next" href="source_code_style.html" title="Coding Style" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Directory Layout and Source Conventions</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="appendix_contributing.html">Prev</a> </td><th width="60%" align="center">Appendix A.

2652

Contributing

2653

2654

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2655

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2656

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2660

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

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2662

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>File Based Streams</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="io.html" title="Chapter 13. Input and Output" /><link rel="prev" href="stringstreams.html" title="Memory Based Streams" /><link rel="next" href="io_and_c.html" title="Interacting with C" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">File Based Streams</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="stringstreams.html">Prev</a> </td><th width="60%" align="center">Chapter 13.

2663

Input and Output

2664

2665

</th><td width="20%" align="right"> <a accesskey="n" href="io_and_c.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.io.filestreams"></a>File Based Streams</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="std.io.filestreams.copying_a_file"></a>Copying a File</h3></div></div></div><p>

2666

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2667

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2668

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2670

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2671

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2672

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2673

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 29. Demangling</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III. Extensions" /><link rel="prev" href="ext_io.html" title="Chapter 28. Input and Output" /><link rel="next" href="ext_concurrency.html" title="Chapter 30. Concurrency" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 29. Demangling</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_io.html">Prev</a> </td><th width="60%" align="center">Part III.

2674

Extensions

2675

2676

</th><td width="20%" align="right"> <a accesskey="n" href="ext_concurrency.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.demangle"></a>Chapter 29. Demangling</h2></div></div></div><p>

2677

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2678

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2679

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2681

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2682

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

2683

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title></title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III. Extensions" /><link rel="prev" href="extensions.html" title="Part III. Extensions" /><link rel="next" href="ext_compile_checks.html" title="Chapter 16. Compile Time Checks" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center"></th></tr><tr><td width="20%" align="left"><a accesskey="p" href="extensions.html">Prev</a> </td><th width="60%" align="center">Part III.

2684

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title></title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III. Extensions" /><link rel="prev" href="extensions.html" title="Part III. Extensions" /><link rel="next" href="ext_compile_checks.html" title="Chapter 16. Compile Time Checks" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center"></th></tr><tr><td width="20%" align="left"><a accesskey="p" href="extensions.html">Prev</a> </td><th width="60%" align="center">Part III.

2685

Extensions

2686

2687

-</th><td width="20%" align="right"> <a accesskey="n" href="ext_compile_checks.html">Next</a></td></tr></table><hr /></div><div class="preface"><div class="titlepage"><div><div><h1 class="title"><a id="idp16425920"></a></h1></div></div></div><p>

2688

+</th><td width="20%" align="right"> <a accesskey="n" href="ext_compile_checks.html">Next</a></td></tr></table><hr /></div><div class="preface"><div class="titlepage"><div><div><h1 class="title"><a id="idm269999105296"></a></h1></div></div></div><p>

2689

Here we will make an attempt at describing the non-Standard

2690

extensions to the library. Some of these are from older versions of

2691

standard library components, namely SGI's STL, and some of these are

2692

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2693

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2694

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2695

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2696

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2697

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2698

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2699

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Concept Checking</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="diagnostics.html" title="Chapter 5. Diagnostics" /><link rel="prev" href="diagnostics.html" title="Chapter 5. Diagnostics" /><link rel="next" href="utilities.html" title="Chapter 6. Utilities" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Concept Checking</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="diagnostics.html">Prev</a> </td><th width="60%" align="center">Chapter 5.

2700

Diagnostics

2701

2702

</th><td width="20%" align="right"> <a accesskey="n" href="utilities.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.diagnostics.concept_checking"></a>Concept Checking</h2></div></div></div><p>

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2704

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2705

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2707

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2708

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2709

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2710

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Multiple Thread Example</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, allocator" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="mt_allocator.html" title="Chapter 20. The mt_allocator" /><link rel="prev" href="mt_allocator_ex_single.html" title="Single Thread Example" /><link rel="next" href="bitmap_allocator.html" title="Chapter 21. The bitmap_allocator" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Multiple Thread Example</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="mt_allocator_ex_single.html">Prev</a> </td><th width="60%" align="center">Chapter 20. The mt_allocator</th><td width="20%" align="right"> <a accesskey="n" href="bitmap_allocator.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="allocator.mt.example_multi"></a>Multiple Thread Example</h2></div></div></div><p>

2711

In the ST example we never used the thread_id variable present in each block.

2712

Let's start by explaining the purpose of this in a MT application.

2713

</p><p>

2714

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2715

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2716

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2717

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2718

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2719

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2721

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 16. Compile Time Checks</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III. Extensions" /><link rel="prev" href="ext_preface.html" title="" /><link rel="next" href="debug_mode.html" title="Chapter 17. Debug Mode" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 16. Compile Time Checks</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_preface.html">Prev</a> </td><th width="60%" align="center">Part III.

2722

Extensions

2723

2724

</th><td width="20%" align="right"> <a accesskey="n" href="debug_mode.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.compile_checks"></a>Chapter 16. Compile Time Checks</h2></div></div></div><p>

2725

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2726

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2727

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2732

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2733

Strings

2734

2735

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2736

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2737

Standard Contents

2738

</th><td width="20%" align="right"> <a accesskey="n" href="localization.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="std.strings"></a>Chapter 7.

2739

Strings

2740

- <a id="idp15603440" class="indexterm"></a>

2741

-</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="strings.html#std.strings.string">String Classes</a></span></dt><dd><dl><dt><span class="section"><a href="strings.html#strings.string.simple">Simple Transformations</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.case">Case Sensitivity</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.character_types">Arbitrary Character Types</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.token">Tokenizing</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.shrink">Shrink to Fit</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.Cstring">CString (MFC)</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.strings.string"></a>String Classes</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="strings.string.simple"></a>Simple Transformations</h3></div></div></div><p>

2742

+ <a id="idm269999928112" class="indexterm"></a>

2743

+</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="strings.html#std.strings.string">String Classes</a></span></dt><dd><dl><dt><span class="section"><a href="strings.html#strings.string.simple">Simple Transformations</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.case">Case Sensitivity</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.character_types">Arbitrary Character Types</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.token">Tokenizing</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.shrink">Shrink to Fit</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.Cstring">CString (MFC)</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.strings.string"></a>String Classes</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="strings.string.simple"></a>Simple Transformations</h3></div></div></div><p>

2744

Here are Standard, simple, and portable ways to perform common

2745

transformations on a <code class="code">string</code> instance, such as

2746

"convert to all upper case." The word transformations

2747

Index: libstdc++-v3/doc/html/manual/containers_and_c.html

2748

===================================================================

2749

--- a/src/libstdc++-v3/doc/html/manual/containers_and_c.html (.../tags/gcc_4_8_2_release)

2750

+++ b/src/libstdc++-v3/doc/html/manual/containers_and_c.html (.../branches/gcc-4_8-branch)

2751

@@ -1,5 +1,5 @@

2752

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

2753

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Interacting with C</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="containers.html" title="Chapter 9. Containers" /><link rel="prev" href="unordered_associative.html" title="Unordered Associative" /><link rel="next" href="iterators.html" title="Chapter 10. Iterators" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Interacting with C</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="unordered_associative.html">Prev</a> </td><th width="60%" align="center">Chapter 9.

2754

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Interacting with C</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="containers.html" title="Chapter 9. Containers" /><link rel="prev" href="unordered_associative.html" title="Unordered Associative" /><link rel="next" href="iterators.html" title="Chapter 10. Iterators" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Interacting with C</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="unordered_associative.html">Prev</a> </td><th width="60%" align="center">Chapter 9.

2755

Containers

2756

2757

</th><td width="20%" align="right"> <a accesskey="n" href="iterators.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.containers.c"></a>Interacting with C</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="containers.c.vs_array"></a>Containers vs. Arrays</h3></div></div></div><p>

2758

Index: libstdc++-v3/doc/html/manual/profile_mode_diagnostics.html

2759

===================================================================

2760

--- a/src/libstdc++-v3/doc/html/manual/profile_mode_diagnostics.html (.../tags/gcc_4_8_2_release)

2761

+++ b/src/libstdc++-v3/doc/html/manual/profile_mode_diagnostics.html (.../branches/gcc-4_8-branch)

2762

@@ -1,5 +1,5 @@

2763

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

2764

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Diagnostics</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="prev" href="profile_mode_devel.html" title="Developer Information" /><link rel="next" href="mt_allocator.html" title="Chapter 20. The mt_allocator" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Diagnostics</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="profile_mode_devel.html">Prev</a> </td><th width="60%" align="center">Chapter 19. Profile Mode</th><td width="20%" align="right"> <a accesskey="n" href="mt_allocator.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.diagnostics"></a>Diagnostics</h2></div></div></div><p>

2765

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Diagnostics</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="prev" href="profile_mode_devel.html" title="Developer Information" /><link rel="next" href="mt_allocator.html" title="Chapter 20. The mt_allocator" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Diagnostics</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="profile_mode_devel.html">Prev</a> </td><th width="60%" align="center">Chapter 19. Profile Mode</th><td width="20%" align="right"> <a accesskey="n" href="mt_allocator.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.diagnostics"></a>Diagnostics</h2></div></div></div><p>

2766

The table below presents all the diagnostics we intend to implement.

2767

Each diagnostic has a corresponding compile time switch

2768

<code class="code">-D_GLIBCXX_PROFILE_<diagnostic></code>.

2769

@@ -17,7 +17,7 @@

2770

A high accuracy means that the diagnostic is unlikely to be wrong.

2771

These grades are not perfect. They are just meant to guide users with

2772

specific needs or time budgets.

2773

- </p><div class="table"><a id="idp17088912"></a><p class="title"><strong>Table 19.2. Profile Diagnostics</strong></p><div class="table-contents"><table summary="Profile Diagnostics" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /><col align="left" class="c6" /><col align="left" class="c7" /></colgroup><thead><tr><th align="left">Group</th><th align="left">Flag</th><th align="left">Benefit</th><th align="left">Cost</th><th align="left">Freq.</th><th align="left">Implemented</th><td class="auto-generated"> </td></tr></thead><tbody><tr><td align="left"><a class="link" href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.containers" title="Containers">

2774

+ </p><div class="table"><a id="idm269998442544"></a><p class="title"><strong>Table 19.2. Profile Diagnostics</strong></p><div class="table-contents"><table summary="Profile Diagnostics" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /><col align="left" class="c6" /><col align="left" class="c7" /></colgroup><thead><tr><th align="left">Group</th><th align="left">Flag</th><th align="left">Benefit</th><th align="left">Cost</th><th align="left">Freq.</th><th align="left">Implemented</th><td class="auto-generated"> </td></tr></thead><tbody><tr><td align="left"><a class="link" href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.containers" title="Containers">

2775

CONTAINERS</a></td><td align="left"><a class="link" href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.hashtable_too_small" title="Hashtable Too Small">

2776

HASHTABLE_TOO_SMALL</a></td><td align="left">10</td><td align="left">1</td><td align="left"> </td><td align="left">10</td><td align="left">yes</td></tr><tr><td align="left"> </td><td align="left"><a class="link" href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.hashtable_too_large" title="Hashtable Too Large">

2777

HASHTABLE_TOO_LARGE</a></td><td align="left">5</td><td align="left">1</td><td align="left"> </td><td align="left">10</td><td align="left">yes</td></tr><tr><td align="left"> </td><td align="left"><a class="link" href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.inefficient_hash" title="Inefficient Hash">

2778

@@ -374,7 +374,7 @@

2779

Quick Sort for a particular call context.

2780

</p></li><li class="listitem"><p><span class="emphasis"><em>Fundamentals:</em></span>

2781

See papers:

2782

- <a class="link" href="http://portal.acm.org/citation.cfm?doid=1065944.1065981" target="_top">

2783

+ <a class="link" href="https://dl.acm.org/citation.cfm?doid=1065944.1065981" target="_top">

2784

A framework for adaptive algorithm selection in STAPL</a> and

2785

2786

Optimizing Sorting with Machine Learning Algorithms</a>.

2787

@@ -500,7 +500,7 @@

2788

Keep a shadow for each container. Record iterator dereferences and

2789

container member accesses. Issue advice for elements referenced by

2790

multiple threads.

2791

- See paper: <a class="link" href="http://portal.acm.org/citation.cfm?id=207110.207148" target="_top">

2792

+ See paper: <a class="link" href="https://dl.acm.org/citation.cfm?id=207110.207148" target="_top">

2793

The LRPD test: speculative run-time parallelization of loops with

2794

privatization and reduction parallelization</a>.

2795

</p></li><li class="listitem"><p><span class="emphasis"><em>Cost model:</em></span>

2796

Index: libstdc++-v3/doc/html/manual/ext_concurrency_impl.html

2797

===================================================================

2798

--- a/src/libstdc++-v3/doc/html/manual/ext_concurrency_impl.html (.../tags/gcc_4_8_2_release)

2799

+++ b/src/libstdc++-v3/doc/html/manual/ext_concurrency_impl.html (.../branches/gcc-4_8-branch)

2800

@@ -1,5 +1,5 @@

2801

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

2802

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Implementation</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="ext_concurrency.html" title="Chapter 30. Concurrency" /><link rel="prev" href="ext_concurrency.html" title="Chapter 30. Concurrency" /><link rel="next" href="ext_concurrency_use.html" title="Use" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Implementation</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_concurrency.html">Prev</a> </td><th width="60%" align="center">Chapter 30. Concurrency</th><td width="20%" align="right"> <a accesskey="n" href="ext_concurrency_use.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.concurrency.impl"></a>Implementation</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.ext.concurrency.impl.atomic_fallbacks"></a>Using Builtin Atomic Functions</h3></div></div></div><p>The functions for atomic operations described above are either

2803

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Implementation</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="ext_concurrency.html" title="Chapter 30. Concurrency" /><link rel="prev" href="ext_concurrency.html" title="Chapter 30. Concurrency" /><link rel="next" href="ext_concurrency_use.html" title="Use" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Implementation</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_concurrency.html">Prev</a> </td><th width="60%" align="center">Chapter 30. Concurrency</th><td width="20%" align="right"> <a accesskey="n" href="ext_concurrency_use.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.concurrency.impl"></a>Implementation</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.ext.concurrency.impl.atomic_fallbacks"></a>Using Builtin Atomic Functions</h3></div></div></div><p>The functions for atomic operations described above are either

2804

implemented via compiler intrinsics (if the underlying host is

2805

capable) or by library fallbacks.</p><p>Compiler intrinsics (builtins) are always preferred. However, as

2806

the compiler builtins for atomics are not universally implemented,

2807

Index: libstdc++-v3/doc/html/manual/io_and_c.html

2808

===================================================================

2809

--- a/src/libstdc++-v3/doc/html/manual/io_and_c.html (.../tags/gcc_4_8_2_release)

2810

+++ b/src/libstdc++-v3/doc/html/manual/io_and_c.html (.../branches/gcc-4_8-branch)

2811

@@ -1,5 +1,5 @@

2812

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

2813

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Interacting with C</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="io.html" title="Chapter 13. Input and Output" /><link rel="prev" href="fstreams.html" title="File Based Streams" /><link rel="next" href="atomics.html" title="Chapter 14. Atomics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Interacting with C</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="fstreams.html">Prev</a> </td><th width="60%" align="center">Chapter 13.

2814

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Interacting with C</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="io.html" title="Chapter 13. Input and Output" /><link rel="prev" href="fstreams.html" title="File Based Streams" /><link rel="next" href="atomics.html" title="Chapter 14. Atomics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Interacting with C</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="fstreams.html">Prev</a> </td><th width="60%" align="center">Chapter 13.

2815

Input and Output

2816

2817

</th><td width="20%" align="right"> <a accesskey="n" href="atomics.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.io.c"></a>Interacting with C</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="std.io.c.FILE"></a>Using FILE* and file descriptors</h3></div></div></div><p>

2818

Index: libstdc++-v3/doc/html/manual/documentation_hacking.html

2819

===================================================================

2820

--- a/src/libstdc++-v3/doc/html/manual/documentation_hacking.html (.../tags/gcc_4_8_2_release)

2821

+++ b/src/libstdc++-v3/doc/html/manual/documentation_hacking.html (.../branches/gcc-4_8-branch)

2822

@@ -1,5 +1,5 @@

2823

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

2824

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Writing and Generating Documentation</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, documentation, style, docbook, doxygen" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B. Porting and Maintenance" /><link rel="prev" href="appendix_porting.html" title="Appendix B. Porting and Maintenance" /><link rel="next" href="internals.html" title="Porting to New Hardware or Operating Systems" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Writing and Generating Documentation</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="appendix_porting.html">Prev</a> </td><th width="60%" align="center">Appendix B.

2825

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Writing and Generating Documentation</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, documentation, style, docbook, doxygen" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B. Porting and Maintenance" /><link rel="prev" href="appendix_porting.html" title="Appendix B. Porting and Maintenance" /><link rel="next" href="internals.html" title="Porting to New Hardware or Operating Systems" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Writing and Generating Documentation</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="appendix_porting.html">Prev</a> </td><th width="60%" align="center">Appendix B.

2826

Porting and Maintenance

2827

2828

</th><td width="20%" align="right"> <a accesskey="n" href="internals.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="appendix.porting.doc"></a>Writing and Generating Documentation</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="doc.intro"></a>Introduction</h3></div></div></div><p>

2829

@@ -112,7 +112,7 @@

2830

supported, and are always aliased to dummy rules. These

2831

unsupported formats are: <span class="emphasis"><em>info</em></span>,

2832

<span class="emphasis"><em>ps</em></span>, and <span class="emphasis"><em>dvi</em></span>.

2833

- </p></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="doc.doxygen"></a>Doxygen</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="doxygen.prereq"></a>Prerequisites</h4></div></div></div><div class="table"><a id="idp22162432"></a><p class="title"><strong>Table B.1. Doxygen Prerequisites</strong></p><div class="table-contents"><table summary="Doxygen Prerequisites" border="1"><colgroup><col align="center" class="c1" /><col align="center" class="c2" /><col align="center" class="c3" /></colgroup><thead><tr><th align="center">Tool</th><th align="center">Version</th><th align="center">Required By</th></tr></thead><tbody><tr><td align="center">coreutils</td><td align="center">8.5</td><td align="center">all</td></tr><tr><td align="center">bash</td><td align="center">4.1</td><td align="center">all</td></tr><tr><td align="center">doxygen</td><td align="center">1.7.6.1</td><td align="center">all</td></tr><tr><td align="center">graphviz</td><td align="center">2.26</td><td align="center">graphical hierarchies</td></tr><tr><td align="center">pdflatex</td><td align="center">2007-59</td><td align="center">pdf output</td></tr></tbody></table></div></div><br class="table-break" /><p>

2834

+ </p></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="doc.doxygen"></a>Doxygen</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="doxygen.prereq"></a>Prerequisites</h4></div></div></div><div class="table"><a id="idm269993370272"></a><p class="title"><strong>Table B.1. Doxygen Prerequisites</strong></p><div class="table-contents"><table summary="Doxygen Prerequisites" border="1"><colgroup><col align="center" class="c1" /><col align="center" class="c2" /><col align="center" class="c3" /></colgroup><thead><tr><th align="center">Tool</th><th align="center">Version</th><th align="center">Required By</th></tr></thead><tbody><tr><td align="center">coreutils</td><td align="center">8.5</td><td align="center">all</td></tr><tr><td align="center">bash</td><td align="center">4.1</td><td align="center">all</td></tr><tr><td align="center">doxygen</td><td align="center">1.7.6.1</td><td align="center">all</td></tr><tr><td align="center">graphviz</td><td align="center">2.26</td><td align="center">graphical hierarchies</td></tr><tr><td align="center">pdflatex</td><td align="center">2007-59</td><td align="center">pdf output</td></tr></tbody></table></div></div><br class="table-break" /><p>

2835

Prerequisite tools are Bash 2.0 or later,

2836

<a class="link" href="http://www.doxygen.org/" target="_top">Doxygen</a>, and

2837

the <a class="link" href="http://www.gnu.org/software/coreutils/" target="_top">GNU

2838

@@ -232,9 +232,8 @@

2839

member functions.

2840

</p><p>

2841

Some commentary to accompany

2842

- the first list in the <a class="link" href="http://www.stack.nl/~dimitri/doxygen/docblocks.html" target="_top">Special

2843

- Documentation Blocks</a> section of

2844

- the Doxygen manual:

2845

+ the first list in the <a class="link" href="http://www.stack.nl/~dimitri/doxygen/manual/docblocks.html" target="_top">Special

2846

+ Documentation Blocks</a> section of the Doxygen manual:

2847

</p><div class="orderedlist"><ol class="orderedlist" type="1"><li class="listitem"><p>For longer comments, use the Javadoc style...</p></li><li class="listitem"><p>

2848

...not the Qt style. The intermediate *'s are preferred.

2849

</p></li><li class="listitem"><p>

2850

@@ -310,7 +309,7 @@

2851

writing Doxygen comments. Single and double quotes, and

2852

separators in filenames are two common trouble spots. When in

2853

doubt, consult the following table.

2854

- </p><div class="table"><a id="idp22238096"></a><p class="title"><strong>Table B.2. HTML to Doxygen Markup Comparison</strong></p><div class="table-contents"><table summary="HTML to Doxygen Markup Comparison" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><thead><tr><th align="left">HTML</th><th align="left">Doxygen</th></tr></thead><tbody><tr><td align="left">\</td><td align="left">\\</td></tr><tr><td align="left">"</td><td align="left">\"</td></tr><tr><td align="left">'</td><td align="left">\'</td></tr><tr><td align="left"><i></td><td align="left">@a word</td></tr><tr><td align="left"><b></td><td align="left">@b word</td></tr><tr><td align="left"><code></td><td align="left">@c word</td></tr><tr><td align="left"><em></td><td align="left">@a word</td></tr><tr><td align="left"><em></td><td align="left"><em>two words or more</em></td></tr></tbody></table></div></div><br class="table-break" /></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="doc.docbook"></a>Docbook</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="docbook.prereq"></a>Prerequisites</h4></div></div></div><div class="table"><a id="idp22257536"></a><p class="title"><strong>Table B.3. Docbook Prerequisites</strong></p><div class="table-contents"><table summary="Docbook Prerequisites" border="1"><colgroup><col align="center" class="c1" /><col align="center" class="c2" /><col align="center" class="c3" /></colgroup><thead><tr><th align="center">Tool</th><th align="center">Version</th><th align="center">Required By</th></tr></thead><tbody><tr><td align="center">docbook5-style-xsl</td><td align="center">1.76.1</td><td align="center">all</td></tr><tr><td align="center">xsltproc</td><td align="center">1.1.26</td><td align="center">all</td></tr><tr><td align="center">xmllint</td><td align="center">2.7.7</td><td align="center">validation</td></tr><tr><td align="center">dblatex</td><td align="center">0.3</td><td align="center">pdf output</td></tr><tr><td align="center">pdflatex</td><td align="center">2007-59</td><td align="center">pdf output</td></tr><tr><td align="center">docbook2X</td><td align="center">0.8.8</td><td align="center">info output</td></tr><tr><td align="center">epub3 stylesheets</td><td align="center">b3</td><td align="center">epub output</td></tr></tbody></table></div></div><br class="table-break" /><p>

2855

+ </p><div class="table"><a id="idm269993294592"></a><p class="title"><strong>Table B.2. HTML to Doxygen Markup Comparison</strong></p><div class="table-contents"><table summary="HTML to Doxygen Markup Comparison" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><thead><tr><th align="left">HTML</th><th align="left">Doxygen</th></tr></thead><tbody><tr><td align="left">\</td><td align="left">\\</td></tr><tr><td align="left">"</td><td align="left">\"</td></tr><tr><td align="left">'</td><td align="left">\'</td></tr><tr><td align="left"><i></td><td align="left">@a word</td></tr><tr><td align="left"><b></td><td align="left">@b word</td></tr><tr><td align="left"><code></td><td align="left">@c word</td></tr><tr><td align="left"><em></td><td align="left">@a word</td></tr><tr><td align="left"><em></td><td align="left"><em>two words or more</em></td></tr></tbody></table></div></div><br class="table-break" /></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="doc.docbook"></a>Docbook</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="docbook.prereq"></a>Prerequisites</h4></div></div></div><div class="table"><a id="idm269993275152"></a><p class="title"><strong>Table B.3. Docbook Prerequisites</strong></p><div class="table-contents"><table summary="Docbook Prerequisites" border="1"><colgroup><col align="center" class="c1" /><col align="center" class="c2" /><col align="center" class="c3" /></colgroup><thead><tr><th align="center">Tool</th><th align="center">Version</th><th align="center">Required By</th></tr></thead><tbody><tr><td align="center">docbook5-style-xsl</td><td align="center">1.76.1</td><td align="center">all</td></tr><tr><td align="center">xsltproc</td><td align="center">1.1.26</td><td align="center">all</td></tr><tr><td align="center">xmllint</td><td align="center">2.7.7</td><td align="center">validation</td></tr><tr><td align="center">dblatex</td><td align="center">0.3</td><td align="center">pdf output</td></tr><tr><td align="center">pdflatex</td><td align="center">2007-59</td><td align="center">pdf output</td></tr><tr><td align="center">docbook2X</td><td align="center">0.8.8</td><td align="center">info output</td></tr><tr><td align="center">epub3 stylesheets</td><td align="center">b3</td><td align="center">epub output</td></tr></tbody></table></div></div><br class="table-break" /><p>

2856

Editing the DocBook sources requires an XML editor. Many

2857

exist: some notable options

2858

include <span class="command"><strong>emacs</strong></span>, <span class="application">Kate</span>,

2859

@@ -520,11 +519,11 @@

2860

<a class="link" href="http://www.docbook.org/tdg/en/html/part2.html" target="_top">online</a>.

2861

An incomplete reference for HTML to Docbook conversion is

2862

detailed in the table below.

2863

- </p><div class="table"><a id="idp22335040"></a><p class="title"><strong>Table B.4. HTML to Docbook XML Markup Comparison</strong></p><div class="table-contents"><table summary="HTML to Docbook XML Markup Comparison" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><thead><tr><th align="left">HTML</th><th align="left">Docbook</th></tr></thead><tbody><tr><td align="left"><p></td><td align="left"><para></td></tr><tr><td align="left"><pre></td><td align="left"><computeroutput>, <programlisting>,

2864

+ </p><div class="table"><a id="idm269993197520"></a><p class="title"><strong>Table B.4. HTML to Docbook XML Markup Comparison</strong></p><div class="table-contents"><table summary="HTML to Docbook XML Markup Comparison" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><thead><tr><th align="left">HTML</th><th align="left">Docbook</th></tr></thead><tbody><tr><td align="left"><p></td><td align="left"><para></td></tr><tr><td align="left"><pre></td><td align="left"><computeroutput>, <programlisting>,

2865

2866

And examples of detailed markup for which there are no real HTML

2867

equivalents are listed in the table below.

2868

-</p><div class="table"><a id="idp22359184"></a><p class="title"><strong>Table B.5. Docbook XML Element Use</strong></p><div class="table-contents"><table summary="Docbook XML Element Use" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><thead><tr><th align="left">Element</th><th align="left">Use</th></tr></thead><tbody><tr><td align="left"><structname></td><td align="left"><structname>char_traits</structname></td></tr><tr><td align="left"><classname></td><td align="left"><classname>string</classname></td></tr><tr><td align="left"><function></td><td align="left">

2869

+</p><div class="table"><a id="idm269993173376"></a><p class="title"><strong>Table B.5. Docbook XML Element Use</strong></p><div class="table-contents"><table summary="Docbook XML Element Use" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><thead><tr><th align="left">Element</th><th align="left">Use</th></tr></thead><tbody><tr><td align="left"><structname></td><td align="left"><structname>char_traits</structname></td></tr><tr><td align="left"><classname></td><td align="left"><classname>string</classname></td></tr><tr><td align="left"><function></td><td align="left">

2870

<p><function>clear()</function></p>

2871

<p><function>fs.clear()</function></p>

2872

</td></tr><tr><td align="left"><type></td><td align="left"><type>long long</type></td></tr><tr><td align="left"><varname></td><td align="left"><varname>fs</varname></td></tr><tr><td align="left"><literal></td><td align="left">

2873

Index: libstdc++-v3/doc/html/manual/extensions.html

2874

===================================================================

2875

--- a/src/libstdc++-v3/doc/html/manual/extensions.html (.../tags/gcc_4_8_2_release)

2876

+++ b/src/libstdc++-v3/doc/html/manual/extensions.html (.../branches/gcc-4_8-branch)

2877

@@ -1,11 +1,11 @@

2878

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

2879

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Part III. Extensions</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="index.html" title="The GNU C++ Library Manual" /><link rel="prev" href="io_and_c.html" title="Interacting with C" /><link rel="next" href="ext_preface.html" title="" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Part III.

2880

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Part III. Extensions</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="index.html" title="The GNU C++ Library Manual" /><link rel="prev" href="io_and_c.html" title="Interacting with C" /><link rel="next" href="ext_preface.html" title="" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Part III.

2881

Extensions

2882

2883

</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="io_and_c.html">Prev</a> </td><th width="60%" align="center">The GNU C++ Library Manual</th><td width="20%" align="right"> <a accesskey="n" href="ext_preface.html">Next</a></td></tr></table><hr /></div><div class="part"><div class="titlepage"><div><div><h1 class="title"><a id="manual.ext"></a>Part III.

2884

Extensions

2885

- <a id="idp16423680" class="indexterm"></a>

2886

-</h1></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="preface"><a href="ext_preface.html"></a></span></dt><dt><span class="chapter"><a href="ext_compile_checks.html">16. Compile Time Checks</a></span></dt><dt><span class="chapter"><a href="debug_mode.html">17. Debug Mode</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode.html#manual.ext.debug_mode.intro">Intro</a></span></dt><dt><span class="section"><a href="debug_mode_semantics.html">Semantics</a></span></dt><dt><span class="section"><a href="debug_mode_using.html">Using</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_using.html#debug_mode.using.mode">Using the Debug Mode</a></span></dt><dt><span class="section"><a href="debug_mode_using.html#debug_mode.using.specific">Using a Specific Debug Container</a></span></dt></dl></dd><dt><span class="section"><a href="debug_mode_design.html">Design</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.goals">Goals</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods">Methods</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.wrappers">The Wrapper Model</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.safe_iter">Safe Iterators</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.safe_seq">Safe Sequences (Containers)</a></span></dt></dl></dd><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.precond">Precondition Checking</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.coexistence">Release- and debug-mode coexistence</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#methods.coexistence.compile">Compile-time coexistence of release- and debug-mode components</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#methods.coexistence.link">Link- and run-time coexistence of release- and

2887

+ <a id="idm269999107536" class="indexterm"></a>

2888

+</h1></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="preface"><a href="ext_preface.html"></a></span></dt><dt><span class="chapter"><a href="ext_compile_checks.html">16. Compile Time Checks</a></span></dt><dt><span class="chapter"><a href="debug_mode.html">17. Debug Mode</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode.html#manual.ext.debug_mode.intro">Intro</a></span></dt><dt><span class="section"><a href="debug_mode_semantics.html">Semantics</a></span></dt><dt><span class="section"><a href="debug_mode_using.html">Using</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_using.html#debug_mode.using.mode">Using the Debug Mode</a></span></dt><dt><span class="section"><a href="debug_mode_using.html#debug_mode.using.specific">Using a Specific Debug Container</a></span></dt></dl></dd><dt><span class="section"><a href="debug_mode_design.html">Design</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.goals">Goals</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods">Methods</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.wrappers">The Wrapper Model</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.safe_iter">Safe Iterators</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.safe_seq">Safe Sequences (Containers)</a></span></dt></dl></dd><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.precond">Precondition Checking</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.coexistence">Release- and debug-mode coexistence</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#methods.coexistence.compile">Compile-time coexistence of release- and debug-mode components</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#methods.coexistence.link">Link- and run-time coexistence of release- and

2889

debug-mode components</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#methods.coexistence.alt">Alternatives for Coexistence</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.other">Other Implementations</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="parallel_mode.html">18. Parallel Mode</a></span></dt><dd><dl><dt><span class="section"><a href="parallel_mode.html#manual.ext.parallel_mode.intro">Intro</a></span></dt><dt><span class="section"><a href="parallel_mode_semantics.html">Semantics</a></span></dt><dt><span class="section"><a href="parallel_mode_using.html">Using</a></span></dt><dd><dl><dt><span class="section"><a href="parallel_mode_using.html#parallel_mode.using.prereq_flags">Prerequisite Compiler Flags</a></span></dt><dt><span class="section"><a href="parallel_mode_using.html#parallel_mode.using.parallel_mode">Using Parallel Mode</a></span></dt><dt><span class="section"><a href="parallel_mode_using.html#parallel_mode.using.specific">Using Specific Parallel Components</a></span></dt></dl></dd><dt><span class="section"><a href="parallel_mode_design.html">Design</a></span></dt><dd><dl><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.intro">Interface Basics</a></span></dt><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.tuning">Configuration and Tuning</a></span></dt><dd><dl><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.tuning.omp">Setting up the OpenMP Environment</a></span></dt><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.tuning.compile">Compile Time Switches</a></span></dt><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.tuning.settings">Run Time Settings and Defaults</a></span></dt></dl></dd><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.impl">Implementation Namespaces</a></span></dt></dl></dd><dt><span class="section"><a href="parallel_mode_test.html">Testing</a></span></dt><dt><span class="bibliography"><a href="parallel_mode.html#parallel_mode.biblio">Bibliography</a></span></dt></dl></dd><dt><span class="chapter"><a href="profile_mode.html">19. Profile Mode</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode.html#manual.ext.profile_mode.intro">Intro</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode.html#manual.ext.profile_mode.using">Using the Profile Mode</a></span></dt><dt><span class="section"><a href="profile_mode.html#manual.ext.profile_mode.tuning">Tuning the Profile Mode</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_design.html">Design</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.wrapper">Wrapper Model</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.instrumentation">Instrumentation</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.rtlib">Run Time Behavior</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.analysis">Analysis and Diagnostics</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.cost-model">Cost Model</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.reports">Reports</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.testing">Testing</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_api.html">Extensions for Custom Containers</a></span></dt><dt><span class="section"><a href="profile_mode_cost_model.html">Empirical Cost Model</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html">Implementation Issues</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.stack">Stack Traces</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.symbols">Symbolization of Instruction Addresses</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.concurrency">Concurrency</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.stdlib-in-proflib">Using the Standard Library in the Instrumentation Implementation</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.malloc-hooks">Malloc Hooks</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.construction-destruction">Construction and Destruction of Global Objects</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_devel.html">Developer Information</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_devel.html#manual.ext.profile_mode.developer.bigpic">Big Picture</a></span></dt><dt><span class="section"><a href="profile_mode_devel.html#manual.ext.profile_mode.developer.howto">How To Add A Diagnostic</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html">Diagnostics</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.template">Diagnostic Template</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.containers">Containers</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.hashtable_too_small">Hashtable Too Small</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.hashtable_too_large">Hashtable Too Large</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.inefficient_hash">Inefficient Hash</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.vector_too_small">Vector Too Small</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.vector_too_large">Vector Too Large</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.vector_to_hashtable">Vector to Hashtable</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.hashtable_to_vector">Hashtable to Vector</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.vector_to_list">Vector to List</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.list_to_vector">List to Vector</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.list_to_slist">List to Forward List (Slist)</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.assoc_ord_to_unord">Ordered to Unordered Associative Container</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.algorithms">Algorithms</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.algorithms.sort">Sort Algorithm Performance</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.locality">Data Locality</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.locality.sw_prefetch">Need Software Prefetch</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.locality.linked">Linked Structure Locality</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.mthread">Multithreaded Data Access</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.mthread.ddtest">Data Dependence Violations at Container Level</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.mthread.false_share">False Sharing</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.statistics">Statistics</a></span></dt></dl></dd><dt><span class="bibliography"><a href="profile_mode.html#profile_mode.biblio">Bibliography</a></span></dt></dl></dd><dt><span class="chapter"><a href="mt_allocator.html">20. The mt_allocator</a></span></dt><dd><dl><dt><span class="section"><a href="mt_allocator.html#allocator.mt.intro">Intro</a></span></dt><dt><span class="section"><a href="mt_allocator_design.html">Design Issues</a></span></dt><dd><dl><dt><span class="section"><a href="mt_allocator_design.html#allocator.mt.overview">Overview</a></span></dt></dl></dd><dt><span class="section"><a href="mt_allocator_impl.html">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="mt_allocator_impl.html#allocator.mt.tune">Tunable Parameters</a></span></dt><dt><span class="section"><a href="mt_allocator_impl.html#allocator.mt.init">Initialization</a></span></dt><dt><span class="section"><a href="mt_allocator_impl.html#allocator.mt.deallocation">Deallocation Notes</a></span></dt></dl></dd><dt><span class="section"><a href="mt_allocator_ex_single.html">Single Thread Example</a></span></dt><dt><span class="section"><a href="mt_allocator_ex_multi.html">Multiple Thread Example</a></span></dt></dl></dd><dt><span class="chapter"><a href="bitmap_allocator.html">21. The bitmap_allocator</a></span></dt><dd><dl><dt><span class="section"><a href="bitmap_allocator.html#allocator.bitmap.design">Design</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.free_list_store">Free List Store</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.super_block">Super Block</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.super_block_data">Super Block Data Layout</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.max_wasted">Maximum Wasted Percentage</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.allocate"><code class="function">allocate</code></a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.deallocate"><code class="function">deallocate</code></a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.questions">Questions</a></span></dt><dd><dl><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.question.1">1</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.question.2">2</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.question.3">3</a></span></dt></dl></dd><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.locality">Locality</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.grow_policy">Overhead and Grow Policy</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="policy_data_structures.html">22. Policy-Based Data Structures</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#pbds.intro">Intro</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.issues">Performance Issues</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.issues.associative">Associative</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.issues.priority_queue">Priority Que</a></span></dt></dl></dd><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.motivation">Goals</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.motivation.associative">Associative</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#motivation.associative.policy">Policy Choices</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.associative.underlying">Underlying Data Structures</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.associative.iterators">Iterators</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.associative.functions">Functional</a></span></dt></dl></dd><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.motivation.priority_queue">Priority Queues</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#motivation.priority_queue.policy">Policy Choices</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.priority_queue.underlying">Underlying Data Structures</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.priority_queue.binary_heap">Binary Heaps</a></span></dt></dl></dd></dl></dd></dl></dd><dt><span class="section"><a href="policy_data_structures_using.html">Using</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.organization">Organization</a></span></dt><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.tutorial">Tutorial</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.tutorial.basic">Basic Use</a></span></dt><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.tutorial.configuring">

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Configuring via Template Parameters

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</a></span></dt><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.tutorial.traits">

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>

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-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Using</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="C++, library, debug" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="debug_mode.html" title="Chapter 17. Debug Mode" /><link rel="prev" href="debug_mode_semantics.html" title="Semantics" /><link rel="next" href="debug_mode_design.html" title="Design" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Using</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="debug_mode_semantics.html">Prev</a> </td><th width="60%" align="center">Chapter 17. Debug Mode</th><td width="20%" align="right"> <a accesskey="n" href="debug_mode_design.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.debug_mode.using"></a>Using</h2></div></div></div><p>

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Using</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, debug" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="debug_mode.html" title="Chapter 17. Debug Mode" /><link rel="prev" href="debug_mode_semantics.html" title="Semantics" /><link rel="next" href="debug_mode_design.html" title="Design" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Using</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="debug_mode_semantics.html">Prev</a> </td><th width="60%" align="center">Chapter 17. Debug Mode</th><td width="20%" align="right"> <a accesskey="n" href="debug_mode_design.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.debug_mode.using"></a>Using</h2></div></div></div><p>

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</p><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="debug_mode.using.mode"></a>Using the Debug Mode</h3></div></div></div><p>To use the libstdc++ debug mode, compile your application with the

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compiler flag <code class="code">-D_GLIBCXX_DEBUG</code>. Note that this flag

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changes the sizes and behavior of standard class templates such

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@@ -18,6 +18,6 @@

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mode or with debug mode. The

2905

following table provides the names and headers of the debugging

2906

containers:

2907

-</p><div class="table"><a id="idp16490400"></a><p class="title"><strong>Table 17.1. Debugging Containers</strong></p><div class="table-contents"><table summary="Debugging Containers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Container</th><th align="left">Header</th><th align="left">Debug container</th><th align="left">Debug header</th></tr></thead><tbody><tr><td align="left"><code class="classname">std::bitset</code></td><td align="left"><code class="filename">bitset</code></td><td align="left"><code class="classname">__gnu_debug::bitset</code></td><td align="left"><code class="filename"><debug/bitset></code></td></tr><tr><td align="left"><code class="classname">std::deque</code></td><td align="left"><code class="filename">deque</code></td><td align="left"><code class="classname">__gnu_debug::deque</code></td><td align="left"><code class="filename"><debug/deque></code></td></tr><tr><td align="left"><code class="classname">std::list</code></td><td align="left"><code class="filename">list</code></td><td align="left"><code class="classname">__gnu_debug::list</code></td><td align="left"><code class="filename"><debug/list></code></td></tr><tr><td align="left"><code class="classname">std::map</code></td><td align="left"><code class="filename">map</code></td><td align="left"><code class="classname">__gnu_debug::map</code></td><td align="left"><code class="filename"><debug/map></code></td></tr><tr><td align="left"><code class="classname">std::multimap</code></td><td align="left"><code class="filename">map</code></td><td align="left"><code class="classname">__gnu_debug::multimap</code></td><td align="left"><code class="filename"><debug/map></code></td></tr><tr><td align="left"><code class="classname">std::multiset</code></td><td align="left"><code class="filename">set</code></td><td align="left"><code class="classname">__gnu_debug::multiset</code></td><td align="left"><code class="filename"><debug/set></code></td></tr><tr><td align="left"><code class="classname">std::set</code></td><td align="left"><code class="filename">set</code></td><td align="left"><code class="classname">__gnu_debug::set</code></td><td align="left"><code class="filename"><debug/set></code></td></tr><tr><td align="left"><code class="classname">std::string</code></td><td align="left"><code class="filename">string</code></td><td align="left"><code class="classname">__gnu_debug::string</code></td><td align="left"><code class="filename"><debug/string></code></td></tr><tr><td align="left"><code class="classname">std::wstring</code></td><td align="left"><code class="filename">string</code></td><td align="left"><code class="classname">__gnu_debug::wstring</code></td><td align="left"><code class="filename"><debug/string></code></td></tr><tr><td align="left"><code class="classname">std::basic_string</code></td><td align="left"><code class="filename">string</code></td><td align="left"><code class="classname">__gnu_debug::basic_string</code></td><td align="left"><code class="filename"><debug/string></code></td></tr><tr><td align="left"><code class="classname">std::vector</code></td><td align="left"><code class="filename">vector</code></td><td align="left"><code class="classname">__gnu_debug::vector</code></td><td align="left"><code class="filename"><debug/vector></code></td></tr></tbody></table></div></div><br class="table-break" /><p>In addition, when compiling in C++11 mode, these additional

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+</p><div class="table"><a id="idm269999040896"></a><p class="title"><strong>Table 17.1. Debugging Containers</strong></p><div class="table-contents"><table summary="Debugging Containers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Container</th><th align="left">Header</th><th align="left">Debug container</th><th align="left">Debug header</th></tr></thead><tbody><tr><td align="left"><code class="classname">std::bitset</code></td><td align="left"><code class="filename">bitset</code></td><td align="left"><code class="classname">__gnu_debug::bitset</code></td><td align="left"><code class="filename"><debug/bitset></code></td></tr><tr><td align="left"><code class="classname">std::deque</code></td><td align="left"><code class="filename">deque</code></td><td align="left"><code class="classname">__gnu_debug::deque</code></td><td align="left"><code class="filename"><debug/deque></code></td></tr><tr><td align="left"><code class="classname">std::list</code></td><td align="left"><code class="filename">list</code></td><td align="left"><code class="classname">__gnu_debug::list</code></td><td align="left"><code class="filename"><debug/list></code></td></tr><tr><td align="left"><code class="classname">std::map</code></td><td align="left"><code class="filename">map</code></td><td align="left"><code class="classname">__gnu_debug::map</code></td><td align="left"><code class="filename"><debug/map></code></td></tr><tr><td align="left"><code class="classname">std::multimap</code></td><td align="left"><code class="filename">map</code></td><td align="left"><code class="classname">__gnu_debug::multimap</code></td><td align="left"><code class="filename"><debug/map></code></td></tr><tr><td align="left"><code class="classname">std::multiset</code></td><td align="left"><code class="filename">set</code></td><td align="left"><code class="classname">__gnu_debug::multiset</code></td><td align="left"><code class="filename"><debug/set></code></td></tr><tr><td align="left"><code class="classname">std::set</code></td><td align="left"><code class="filename">set</code></td><td align="left"><code class="classname">__gnu_debug::set</code></td><td align="left"><code class="filename"><debug/set></code></td></tr><tr><td align="left"><code class="classname">std::string</code></td><td align="left"><code class="filename">string</code></td><td align="left"><code class="classname">__gnu_debug::string</code></td><td align="left"><code class="filename"><debug/string></code></td></tr><tr><td align="left"><code class="classname">std::wstring</code></td><td align="left"><code class="filename">string</code></td><td align="left"><code class="classname">__gnu_debug::wstring</code></td><td align="left"><code class="filename"><debug/string></code></td></tr><tr><td align="left"><code class="classname">std::basic_string</code></td><td align="left"><code class="filename">string</code></td><td align="left"><code class="classname">__gnu_debug::basic_string</code></td><td align="left"><code class="filename"><debug/string></code></td></tr><tr><td align="left"><code class="classname">std::vector</code></td><td align="left"><code class="filename">vector</code></td><td align="left"><code class="classname">__gnu_debug::vector</code></td><td align="left"><code class="filename"><debug/vector></code></td></tr></tbody></table></div></div><br class="table-break" /><p>In addition, when compiling in C++11 mode, these additional

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containers have additional debug capability.

2910

-</p><div class="table"><a id="idp16535296"></a><p class="title"><strong>Table 17.2. Debugging Containers C++11</strong></p><div class="table-contents"><table summary="Debugging Containers C++11" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Container</th><th align="left">Header</th><th align="left">Debug container</th><th align="left">Debug header</th></tr></thead><tbody><tr><td align="left"><code class="classname">std::unordered_map</code></td><td align="left"><code class="filename">unordered_map</code></td><td align="left"><code class="classname">__gnu_debug::unordered_map</code></td><td align="left"><code class="filename"><debug/unordered_map></code></td></tr><tr><td align="left"><code class="classname">std::unordered_multimap</code></td><td align="left"><code class="filename">unordered_map</code></td><td align="left"><code class="classname">__gnu_debug::unordered_multimap</code></td><td align="left"><code class="filename"><debug/unordered_map></code></td></tr><tr><td align="left"><code class="classname">std::unordered_set</code></td><td align="left"><code class="filename">unordered_set</code></td><td align="left"><code class="classname">__gnu_debug::unordered_set</code></td><td align="left"><code class="filename"><debug/unordered_set></code></td></tr><tr><td align="left"><code class="classname">std::unordered_multiset</code></td><td align="left"><code class="filename">unordered_set</code></td><td align="left"><code class="classname">__gnu_debug::unordered_multiset</code></td><td align="left"><code class="filename"><debug/unordered_set></code></td></tr></tbody></table></div></div><br class="table-break" /></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="debug_mode_semantics.html">Prev</a> </td><td width="20%" align="center"><a accesskey="u" href="debug_mode.html">Up</a></td><td width="40%" align="right"> <a accesskey="n" href="debug_mode_design.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">Semantics </td><td width="20%" align="center"><a accesskey="h" href="../index.html">Home</a></td><td width="40%" align="right" valign="top"> Design</td></tr></table></div></body></html>

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\ No newline at end of file

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+</p><div class="table"><a id="idm269998996000"></a><p class="title"><strong>Table 17.2. Debugging Containers C++11</strong></p><div class="table-contents"><table summary="Debugging Containers C++11" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Container</th><th align="left">Header</th><th align="left">Debug container</th><th align="left">Debug header</th></tr></thead><tbody><tr><td align="left"><code class="classname">std::unordered_map</code></td><td align="left"><code class="filename">unordered_map</code></td><td align="left"><code class="classname">__gnu_debug::unordered_map</code></td><td align="left"><code class="filename"><debug/unordered_map></code></td></tr><tr><td align="left"><code class="classname">std::unordered_multimap</code></td><td align="left"><code class="filename">unordered_map</code></td><td align="left"><code class="classname">__gnu_debug::unordered_multimap</code></td><td align="left"><code class="filename"><debug/unordered_map></code></td></tr><tr><td align="left"><code class="classname">std::unordered_set</code></td><td align="left"><code class="filename">unordered_set</code></td><td align="left"><code class="classname">__gnu_debug::unordered_set</code></td><td align="left"><code class="filename"><debug/unordered_set></code></td></tr><tr><td align="left"><code class="classname">std::unordered_multiset</code></td><td align="left"><code class="filename">unordered_set</code></td><td align="left"><code class="classname">__gnu_debug::unordered_multiset</code></td><td align="left"><code class="filename"><debug/unordered_set></code></td></tr></tbody></table></div></div><br class="table-break" /></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="debug_mode_semantics.html">Prev</a> </td><td width="20%" align="center"><a accesskey="u" href="debug_mode.html">Up</a></td><td width="40%" align="right"> <a accesskey="n" href="debug_mode_design.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">Semantics </td><td width="20%" align="center"><a accesskey="h" href="../index.html">Home</a></td><td width="40%" align="right" valign="top"> Design</td></tr></table></div></body></html>

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>

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-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 18. Parallel Mode</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="C++, library, parallel" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III. Extensions" /><link rel="prev" href="debug_mode_design.html" title="Design" /><link rel="next" href="parallel_mode_semantics.html" title="Semantics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 18. Parallel Mode</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="debug_mode_design.html">Prev</a> </td><th width="60%" align="center">Part III.

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 18. Parallel Mode</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, parallel" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III. Extensions" /><link rel="prev" href="debug_mode_design.html" title="Design" /><link rel="next" href="parallel_mode_semantics.html" title="Semantics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 18. Parallel Mode</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="debug_mode_design.html">Prev</a> </td><th width="60%" align="center">Part III.

2922

Extensions

2923

2924

-</th><td width="20%" align="right"> <a accesskey="n" href="parallel_mode_semantics.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.parallel_mode"></a>Chapter 18. Parallel Mode</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="parallel_mode.html#manual.ext.parallel_mode.intro">Intro</a></span></dt><dt><span class="section"><a href="parallel_mode_semantics.html">Semantics</a></span></dt><dt><span class="section"><a href="parallel_mode_using.html">Using</a></span></dt><dd><dl><dt><span class="section"><a href="parallel_mode_using.html#parallel_mode.using.prereq_flags">Prerequisite Compiler Flags</a></span></dt><dt><span class="section"><a href="parallel_mode_using.html#parallel_mode.using.parallel_mode">Using Parallel Mode</a></span></dt><dt><span class="section"><a href="parallel_mode_using.html#parallel_mode.using.specific">Using Specific Parallel Components</a></span></dt></dl></dd><dt><span class="section"><a href="parallel_mode_design.html">Design</a></span></dt><dd><dl><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.intro">Interface Basics</a></span></dt><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.tuning">Configuration and Tuning</a></span></dt><dd><dl><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.tuning.omp">Setting up the OpenMP Environment</a></span></dt><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.tuning.compile">Compile Time Switches</a></span></dt><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.tuning.settings">Run Time Settings and Defaults</a></span></dt></dl></dd><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.impl">Implementation Namespaces</a></span></dt></dl></dd><dt><span class="section"><a href="parallel_mode_test.html">Testing</a></span></dt><dt><span class="bibliography"><a href="parallel_mode.html#parallel_mode.biblio">Bibliography</a></span></dt></dl></div><p> The libstdc++ parallel mode is an experimental parallel

2925

+</th><td width="20%" align="right"> <a accesskey="n" href="parallel_mode_semantics.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.parallel_mode"></a>Chapter 18. Parallel Mode</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="parallel_mode.html#manual.ext.parallel_mode.intro">Intro</a></span></dt><dt><span class="section"><a href="parallel_mode_semantics.html">Semantics</a></span></dt><dt><span class="section"><a href="parallel_mode_using.html">Using</a></span></dt><dd><dl><dt><span class="section"><a href="parallel_mode_using.html#parallel_mode.using.prereq_flags">Prerequisite Compiler Flags</a></span></dt><dt><span class="section"><a href="parallel_mode_using.html#parallel_mode.using.parallel_mode">Using Parallel Mode</a></span></dt><dt><span class="section"><a href="parallel_mode_using.html#parallel_mode.using.specific">Using Specific Parallel Components</a></span></dt></dl></dd><dt><span class="section"><a href="parallel_mode_design.html">Design</a></span></dt><dd><dl><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.intro">Interface Basics</a></span></dt><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.tuning">Configuration and Tuning</a></span></dt><dd><dl><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.tuning.omp">Setting up the OpenMP Environment</a></span></dt><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.tuning.compile">Compile Time Switches</a></span></dt><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.tuning.settings">Run Time Settings and Defaults</a></span></dt></dl></dd><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.impl">Implementation Namespaces</a></span></dt></dl></dd><dt><span class="section"><a href="parallel_mode_test.html">Testing</a></span></dt><dt><span class="bibliography"><a href="parallel_mode.html#parallel_mode.biblio">Bibliography</a></span></dt></dl></div><p> The libstdc++ parallel mode is an experimental parallel

2926

implementation of many algorithms the C++ Standard Library.

2927

</p><p>

2928

Several of the standard algorithms, for instance

2929

@@ -12,11 +12,11 @@

2930

specific compiler flag.

2931

</p><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.parallel_mode.intro"></a>Intro</h2></div></div></div><p>The following library components in the include

2932

<code class="filename">numeric</code> are included in the parallel mode:</p><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p><code class="function">std::accumulate</code></p></li><li class="listitem"><p><code class="function">std::adjacent_difference</code></p></li><li class="listitem"><p><code class="function">std::inner_product</code></p></li><li class="listitem"><p><code class="function">std::partial_sum</code></p></li></ul></div><p>The following library components in the include

2933

-<code class="filename">algorithm</code> are included in the parallel mode:</p><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p><code class="function">std::adjacent_find</code></p></li><li class="listitem"><p><code class="function">std::count</code></p></li><li class="listitem"><p><code class="function">std::count_if</code></p></li><li class="listitem"><p><code class="function">std::equal</code></p></li><li class="listitem"><p><code class="function">std::find</code></p></li><li class="listitem"><p><code class="function">std::find_if</code></p></li><li class="listitem"><p><code class="function">std::find_first_of</code></p></li><li class="listitem"><p><code class="function">std::for_each</code></p></li><li class="listitem"><p><code class="function">std::generate</code></p></li><li class="listitem"><p><code class="function">std::generate_n</code></p></li><li class="listitem"><p><code class="function">std::lexicographical_compare</code></p></li><li class="listitem"><p><code class="function">std::mismatch</code></p></li><li class="listitem"><p><code class="function">std::search</code></p></li><li class="listitem"><p><code class="function">std::search_n</code></p></li><li class="listitem"><p><code class="function">std::transform</code></p></li><li class="listitem"><p><code class="function">std::replace</code></p></li><li class="listitem"><p><code class="function">std::replace_if</code></p></li><li class="listitem"><p><code class="function">std::max_element</code></p></li><li class="listitem"><p><code class="function">std::merge</code></p></li><li class="listitem"><p><code class="function">std::min_element</code></p></li><li class="listitem"><p><code class="function">std::nth_element</code></p></li><li class="listitem"><p><code class="function">std::partial_sort</code></p></li><li class="listitem"><p><code class="function">std::partition</code></p></li><li class="listitem"><p><code class="function">std::random_shuffle</code></p></li><li class="listitem"><p><code class="function">std::set_union</code></p></li><li class="listitem"><p><code class="function">std::set_intersection</code></p></li><li class="listitem"><p><code class="function">std::set_symmetric_difference</code></p></li><li class="listitem"><p><code class="function">std::set_difference</code></p></li><li class="listitem"><p><code class="function">std::sort</code></p></li><li class="listitem"><p><code class="function">std::stable_sort</code></p></li><li class="listitem"><p><code class="function">std::unique_copy</code></p></li></ul></div></div><div class="bibliography"><div class="titlepage"><div><div><h2 class="title"><a id="parallel_mode.biblio"></a>Bibliography</h2></div></div></div><div class="biblioentry"><a id="idp16926864"></a><p><span class="citetitle"><em class="citetitle">

2934

+<code class="filename">algorithm</code> are included in the parallel mode:</p><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p><code class="function">std::adjacent_find</code></p></li><li class="listitem"><p><code class="function">std::count</code></p></li><li class="listitem"><p><code class="function">std::count_if</code></p></li><li class="listitem"><p><code class="function">std::equal</code></p></li><li class="listitem"><p><code class="function">std::find</code></p></li><li class="listitem"><p><code class="function">std::find_if</code></p></li><li class="listitem"><p><code class="function">std::find_first_of</code></p></li><li class="listitem"><p><code class="function">std::for_each</code></p></li><li class="listitem"><p><code class="function">std::generate</code></p></li><li class="listitem"><p><code class="function">std::generate_n</code></p></li><li class="listitem"><p><code class="function">std::lexicographical_compare</code></p></li><li class="listitem"><p><code class="function">std::mismatch</code></p></li><li class="listitem"><p><code class="function">std::search</code></p></li><li class="listitem"><p><code class="function">std::search_n</code></p></li><li class="listitem"><p><code class="function">std::transform</code></p></li><li class="listitem"><p><code class="function">std::replace</code></p></li><li class="listitem"><p><code class="function">std::replace_if</code></p></li><li class="listitem"><p><code class="function">std::max_element</code></p></li><li class="listitem"><p><code class="function">std::merge</code></p></li><li class="listitem"><p><code class="function">std::min_element</code></p></li><li class="listitem"><p><code class="function">std::nth_element</code></p></li><li class="listitem"><p><code class="function">std::partial_sort</code></p></li><li class="listitem"><p><code class="function">std::partition</code></p></li><li class="listitem"><p><code class="function">std::random_shuffle</code></p></li><li class="listitem"><p><code class="function">std::set_union</code></p></li><li class="listitem"><p><code class="function">std::set_intersection</code></p></li><li class="listitem"><p><code class="function">std::set_symmetric_difference</code></p></li><li class="listitem"><p><code class="function">std::set_difference</code></p></li><li class="listitem"><p><code class="function">std::sort</code></p></li><li class="listitem"><p><code class="function">std::stable_sort</code></p></li><li class="listitem"><p><code class="function">std::unique_copy</code></p></li></ul></div></div><div class="bibliography"><div class="titlepage"><div><div><h2 class="title"><a id="parallel_mode.biblio"></a>Bibliography</h2></div></div></div><div class="biblioentry"><a id="idm269998604464"></a><p><span class="citetitle"><em class="citetitle">

2935

Parallelization of Bulk Operations for STL Dictionaries

2936

</em>. </span><span class="author"><span class="firstname">Johannes</span> <span class="surname">Singler</span>. </span><span class="author"><span class="firstname">Leonor</span> <span class="surname">Frias</span>. </span><span class="copyright">Copyright © 2007 . </span><span class="publisher"><span class="publishername">

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Workshop on Highly Parallel Processing on a Chip (HPPC) 2007. (LNCS)

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- . </span></span></p></div><div class="biblioentry"><a id="idp16931936"></a><p><span class="citetitle"><em class="citetitle">

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+ . </span></span></p></div><div class="biblioentry"><a id="idm269998599392"></a><p><span class="citetitle"><em class="citetitle">

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The Multi-Core Standard Template Library

2941

</em>. </span><span class="author"><span class="firstname">Johannes</span> <span class="surname">Singler</span>. </span><span class="author"><span class="firstname">Peter</span> <span class="surname">Sanders</span>. </span><span class="author"><span class="firstname">Felix</span> <span class="surname">Putze</span>. </span><span class="copyright">Copyright © 2007 . </span><span class="publisher"><span class="publishername">

2942

Euro-Par 2007: Parallel Processing. (LNCS 4641)

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>

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-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Semantics</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="C++, library, debug" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="debug_mode.html" title="Chapter 17. Debug Mode" /><link rel="prev" href="debug_mode.html" title="Chapter 17. Debug Mode" /><link rel="next" href="debug_mode_using.html" title="Using" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Semantics</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="debug_mode.html">Prev</a> </td><th width="60%" align="center">Chapter 17. Debug Mode</th><td width="20%" align="right"> <a accesskey="n" href="debug_mode_using.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.debug_mode.semantics"></a>Semantics</h2></div></div></div><p>

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Semantics</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, debug" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="debug_mode.html" title="Chapter 17. Debug Mode" /><link rel="prev" href="debug_mode.html" title="Chapter 17. Debug Mode" /><link rel="next" href="debug_mode_using.html" title="Using" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Semantics</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="debug_mode.html">Prev</a> </td><th width="60%" align="center">Chapter 17. Debug Mode</th><td width="20%" align="right"> <a accesskey="n" href="debug_mode_using.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.debug_mode.semantics"></a>Semantics</h2></div></div></div><p>

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</p><p>A program that uses the C++ standard library correctly

2952

will maintain the same semantics under debug mode as it had with

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the normal (release) library. All functional and exception-handling

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>

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-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 2. Setup</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="intro.html" title="Part I. Introduction" /><link rel="prev" href="bugs.html" title="Bugs" /><link rel="next" href="configure.html" title="Configure" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 2. Setup</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="bugs.html">Prev</a> </td><th width="60%" align="center">Part I.

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 2. Setup</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="intro.html" title="Part I. Introduction" /><link rel="prev" href="bugs.html" title="Bugs" /><link rel="next" href="configure.html" title="Configure" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 2. Setup</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="bugs.html">Prev</a> </td><th width="60%" align="center">Part I.

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Introduction

2963

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-</th><td width="20%" align="right"> <a accesskey="n" href="configure.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.intro.setup"></a>Chapter 2. Setup</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="setup.html#manual.intro.setup.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="configure.html">Configure</a></span></dt><dt><span class="section"><a href="make.html">Make</a></span></dt></dl></div><p>To transform libstdc++ sources into installed include files

2965

+</th><td width="20%" align="right"> <a accesskey="n" href="configure.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.intro.setup"></a>Chapter 2. Setup</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="setup.html#manual.intro.setup.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="configure.html">Configure</a></span></dt><dt><span class="section"><a href="make.html">Make</a></span></dt></dl></div><p>To transform libstdc++ sources into installed include files

2966

and properly built binaries useful for linking to other software is

2967

a multi-step process. Steps include getting the sources,

2968

configuring and building the sources, testing, and installation.

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===================================================================

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>

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-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Backwards Compatibility</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, backwards" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B. Porting and Maintenance" /><link rel="prev" href="api.html" title="API Evolution and Deprecation History" /><link rel="next" href="appendix_free.html" title="Appendix C. Free Software Needs Free Documentation" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Backwards Compatibility</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="api.html">Prev</a> </td><th width="60%" align="center">Appendix B.

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Backwards Compatibility</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, backwards" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B. Porting and Maintenance" /><link rel="prev" href="api.html" title="API Evolution and Deprecation History" /><link rel="next" href="appendix_free.html" title="Appendix C. Free Software Needs Free Documentation" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Backwards Compatibility</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="api.html">Prev</a> </td><th width="60%" align="center">Appendix B.

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Porting and Maintenance

2978

2979

</th><td width="20%" align="right"> <a accesskey="n" href="appendix_free.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.appendix.porting.backwards"></a>Backwards Compatibility</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="backwards.first"></a>First</h3></div></div></div><p>The first generation GNU C++ library was called libg++. It was a

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This is a change in behavior from older versions. Now, most

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<span class="type">iterator_type</span> typedefs in container classes are POD

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objects, not <span class="type">value_type</span> pointers.

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-</p></div></div><div class="bibliography"><div class="titlepage"><div><div><h3 class="title"><a id="backwards.biblio"></a>Bibliography</h3></div></div></div><div class="biblioentry"><a id="idp23415104"></a><p><span class="title"><em>

2985

+</p></div></div><div class="bibliography"><div class="titlepage"><div><div><h3 class="title"><a id="backwards.biblio"></a>Bibliography</h3></div></div></div><div class="biblioentry"><a id="idm269992117648"></a><p><span class="title"><em>

2986

2987

Migrating to GCC 4.1

2988

</a>

2989

- </em>. </span><span class="author"><span class="firstname">Dan</span> <span class="surname">Kegel</span>. </span></p></div><div class="biblioentry"><a id="idp23417888"></a><p><span class="title"><em>

2990

+ </em>. </span><span class="author"><span class="firstname">Dan</span> <span class="surname">Kegel</span>. </span></p></div><div class="biblioentry"><a id="idm269992114864"></a><p><span class="title"><em>

2991

2992

Building the Whole Debian Archive with GCC 4.1: A Summary

2993

</a>

2994

- </em>. </span><span class="author"><span class="firstname">Martin</span> <span class="surname">Michlmayr</span>. </span></p></div><div class="biblioentry"><a id="idp23420736"></a><p><span class="title"><em>

2995

+ </em>. </span><span class="author"><span class="firstname">Martin</span> <span class="surname">Michlmayr</span>. </span></p></div><div class="biblioentry"><a id="idm269992112016"></a><p><span class="title"><em>

2996

2997

Migration guide for GCC-3.2

2998

</a>

2999

Index: libstdc++-v3/doc/html/manual/source_design_notes.html

3000

===================================================================

3001

--- a/src/libstdc++-v3/doc/html/manual/source_design_notes.html (.../tags/gcc_4_8_2_release)

3002

+++ b/src/libstdc++-v3/doc/html/manual/source_design_notes.html (.../branches/gcc-4_8-branch)

3003

@@ -1,5 +1,5 @@

3004

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

3005

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design Notes</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_contributing.html" title="Appendix A. Contributing" /><link rel="prev" href="source_code_style.html" title="Coding Style" /><link rel="next" href="appendix_porting.html" title="Appendix B. Porting and Maintenance" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design Notes</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="source_code_style.html">Prev</a> </td><th width="60%" align="center">Appendix A.

3006

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design Notes</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_contributing.html" title="Appendix A. Contributing" /><link rel="prev" href="source_code_style.html" title="Coding Style" /><link rel="next" href="appendix_porting.html" title="Appendix B. Porting and Maintenance" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design Notes</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="source_code_style.html">Prev</a> </td><th width="60%" align="center">Appendix A.

3007

Contributing

3008

3009

</th><td width="20%" align="right"> <a accesskey="n" href="appendix_porting.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="contrib.design_notes"></a>Design Notes</h2></div></div></div><p>

3010

Index: libstdc++-v3/doc/html/manual/ext_sgi.html

3011

===================================================================

3012

--- a/src/libstdc++-v3/doc/html/manual/ext_sgi.html (.../tags/gcc_4_8_2_release)

3013

+++ b/src/libstdc++-v3/doc/html/manual/ext_sgi.html (.../branches/gcc-4_8-branch)

3014

@@ -1,5 +1,5 @@

3015

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

3016

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Deprecated</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="ext_containers.html" title="Chapter 23. HP/SGI Extensions" /><link rel="prev" href="ext_containers.html" title="Chapter 23. HP/SGI Extensions" /><link rel="next" href="ext_utilities.html" title="Chapter 24. Utilities" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Deprecated</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_containers.html">Prev</a> </td><th width="60%" align="center">Chapter 23. HP/SGI Extensions</th><td width="20%" align="right"> <a accesskey="n" href="ext_utilities.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.containers.deprecated_sgi"></a>Deprecated</h2></div></div></div><p>

3017

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Deprecated</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="ext_containers.html" title="Chapter 23. HP/SGI Extensions" /><link rel="prev" href="ext_containers.html" title="Chapter 23. HP/SGI Extensions" /><link rel="next" href="ext_utilities.html" title="Chapter 24. Utilities" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Deprecated</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_containers.html">Prev</a> </td><th width="60%" align="center">Chapter 23. HP/SGI Extensions</th><td width="20%" align="right"> <a accesskey="n" href="ext_utilities.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.containers.deprecated_sgi"></a>Deprecated</h2></div></div></div><p>

3018

The SGI hashing classes <code class="classname">hash_set</code> and

3019

<code class="classname">hash_set</code> have been deprecated by the

3020

unordered_set, unordered_multiset, unordered_map,

3021

Index: libstdc++-v3/doc/html/manual/facets.html

3022

===================================================================

3023

--- a/src/libstdc++-v3/doc/html/manual/facets.html (.../tags/gcc_4_8_2_release)

3024

+++ b/src/libstdc++-v3/doc/html/manual/facets.html (.../branches/gcc-4_8-branch)

3025

@@ -1,8 +1,8 @@

3026

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

3027

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Facets</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="localization.html" title="Chapter 8. Localization" /><link rel="prev" href="localization.html" title="Chapter 8. Localization" /><link rel="next" href="containers.html" title="Chapter 9. Containers" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Facets</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="localization.html">Prev</a> </td><th width="60%" align="center">Chapter 8.

3028

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Facets</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="localization.html" title="Chapter 8. Localization" /><link rel="prev" href="localization.html" title="Chapter 8. Localization" /><link rel="next" href="containers.html" title="Chapter 9. Containers" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Facets</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="localization.html">Prev</a> </td><th width="60%" align="center">Chapter 8.

3029

Localization

3030

3031

-</th><td width="20%" align="right"> <a accesskey="n" href="containers.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.localization.facet"></a>Facets</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="std.localization.facet.ctype"></a>ctype</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="facet.ctype.impl"></a>Implementation</h4></div></div></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idp15778336"></a>Specializations</h5></div></div></div><p>

3032

+</th><td width="20%" align="right"> <a accesskey="n" href="containers.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.localization.facet"></a>Facets</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="std.localization.facet.ctype"></a>ctype</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="facet.ctype.impl"></a>Implementation</h4></div></div></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idm269999753024"></a>Specializations</h5></div></div></div><p>

3033

For the required specialization codecvt<wchar_t, char, mbstate_t> ,

3034

conversions are made between the internal character set (always UCS4

3035

on GNU/Linux) and whatever the currently selected locale for the

3036

@@ -49,24 +49,24 @@

3037

</p></li><li class="listitem"><p>

3038

Rename abstract base class. See if just smash-overriding is a

3039

better approach. Clarify, add sanity to naming.

3040

- </p></li></ul></div></div><div class="bibliography"><div class="titlepage"><div><div><h4 class="title"><a id="facet.ctype.biblio"></a>Bibliography</h4></div></div></div><div class="biblioentry"><a id="idp15793392"></a><p><span class="citetitle"><em class="citetitle">

3041

+ </p></li></ul></div></div><div class="bibliography"><div class="titlepage"><div><div><h4 class="title"><a id="facet.ctype.biblio"></a>Bibliography</h4></div></div></div><div class="biblioentry"><a id="idm269999738032"></a><p><span class="citetitle"><em class="citetitle">

3042

The GNU C Library

3043

- </em>. </span><span class="author"><span class="firstname">Roland</span> <span class="surname">McGrath</span>. </span><span class="author"><span class="firstname">Ulrich</span> <span class="surname">Drepper</span>. </span><span class="copyright">Copyright © 2007 FSF. </span><span class="pagenums">Chapters 6 Character Set Handling and 7 Locales and Internationalization. </span></p></div><div class="biblioentry"><a id="idp15798144"></a><p><span class="citetitle"><em class="citetitle">

3044

+ </em>. </span><span class="author"><span class="firstname">Roland</span> <span class="surname">McGrath</span>. </span><span class="author"><span class="firstname">Ulrich</span> <span class="surname">Drepper</span>. </span><span class="copyright">Copyright © 2007 FSF. </span><span class="pagenums">Chapters 6 Character Set Handling and 7 Locales and Internationalization. </span></p></div><div class="biblioentry"><a id="idm269999733280"></a><p><span class="citetitle"><em class="citetitle">

3045

Correspondence

3046

- </em>. </span><span class="author"><span class="firstname">Ulrich</span> <span class="surname">Drepper</span>. </span><span class="copyright">Copyright © 2002 . </span></p></div><div class="biblioentry"><a id="idp15801232"></a><p><span class="citetitle"><em class="citetitle">

3047

+ </em>. </span><span class="author"><span class="firstname">Ulrich</span> <span class="surname">Drepper</span>. </span><span class="copyright">Copyright © 2002 . </span></p></div><div class="biblioentry"><a id="idm269999730192"></a><p><span class="citetitle"><em class="citetitle">

3048

ISO/IEC 14882:1998 Programming languages - C++

3049

3050

3051

ISO/IEC 9899:1999 Programming languages - C

3052

3053

3054

3055

The Open Group Base Specifications, Issue 6 (IEEE Std. 1003.1-2004)

3056

</a>

3057

3058

- The Open Group/The Institute of Electrical and Electronics Engineers, Inc.. </span></p></div><div class="biblioentry"><a id="idp15809040"></a><p><span class="citetitle"><em class="citetitle">

3059

+ The Open Group/The Institute of Electrical and Electronics Engineers, Inc.. </span></p></div><div class="biblioentry"><a id="idm269999722384"></a><p><span class="citetitle"><em class="citetitle">

3060

The C++ Programming Language, Special Edition

3061

</em>. </span><span class="author"><span class="firstname">Bjarne</span> <span class="surname">Stroustrup</span>. </span><span class="copyright">Copyright © 2000 Addison Wesley, Inc.. </span><span class="pagenums">Appendix D. </span><span class="publisher"><span class="publishername">

3062

Addison Wesley

3063

- . </span></span></p></div><div class="biblioentry"><a id="idp15813664"></a><p><span class="citetitle"><em class="citetitle">

3064

+ . </span></span></p></div><div class="biblioentry"><a id="idm269999717760"></a><p><span class="citetitle"><em class="citetitle">

3065

Standard C++ IOStreams and Locales

3066

</em>. </span><span class="subtitle">

3067

Advanced Programmer's Guide and Reference

3068

@@ -409,17 +409,17 @@

3069

</p></li><li class="listitem"><p>

3070

wchar_t/char internal buffers and conversions between

3071

internal/external buffers?

3072

- </p></li></ul></div></li></ul></div></div><div class="bibliography"><div class="titlepage"><div><div><h4 class="title"><a id="facet.codecvt.biblio"></a>Bibliography</h4></div></div></div><div class="biblioentry"><a id="idp15891136"></a><p><span class="citetitle"><em class="citetitle">

3073

+ </p></li></ul></div></li></ul></div></div><div class="bibliography"><div class="titlepage"><div><div><h4 class="title"><a id="facet.codecvt.biblio"></a>Bibliography</h4></div></div></div><div class="biblioentry"><a id="idm269999640080"></a><p><span class="citetitle"><em class="citetitle">

3074

The GNU C Library

3075

</em>. </span><span class="author"><span class="firstname">Roland</span> <span class="surname">McGrath</span>. </span><span class="author"><span class="firstname">Ulrich</span> <span class="surname">Drepper</span>. </span><span class="copyright">Copyright © 2007 FSF. </span><span class="pagenums">

3076

Chapters 6 Character Set Handling and 7 Locales and Internationalization

3077

- . </span></p></div><div class="biblioentry"><a id="idp15895888"></a><p><span class="citetitle"><em class="citetitle">

3078

+ . </span></p></div><div class="biblioentry"><a id="idm269999635328"></a><p><span class="citetitle"><em class="citetitle">

3079

Correspondence

3080

- </em>. </span><span class="author"><span class="firstname">Ulrich</span> <span class="surname">Drepper</span>. </span><span class="copyright">Copyright © 2002 . </span></p></div><div class="biblioentry"><a id="idp15898976"></a><p><span class="citetitle"><em class="citetitle">

3081

+ </em>. </span><span class="author"><span class="firstname">Ulrich</span> <span class="surname">Drepper</span>. </span><span class="copyright">Copyright © 2002 . </span></p></div><div class="biblioentry"><a id="idm269999632240"></a><p><span class="citetitle"><em class="citetitle">

3082

ISO/IEC 14882:1998 Programming languages - C++

3083

3084

3085

ISO/IEC 9899:1999 Programming languages - C

3086

3087

3088

3089

System Interface Definitions, Issue 7 (IEEE Std. 1003.1-2008)

3090

</a>

3091

@@ -426,25 +426,25 @@

3092

3093

The Open Group/The Institute of Electrical and Electronics

3094

Engineers, Inc.

3095

- . </span></p></div><div class="biblioentry"><a id="idp15906768"></a><p><span class="citetitle"><em class="citetitle">

3096

+ . </span></p></div><div class="biblioentry"><a id="idm269999624448"></a><p><span class="citetitle"><em class="citetitle">

3097

The C++ Programming Language, Special Edition

3098

</em>. </span><span class="author"><span class="firstname">Bjarne</span> <span class="surname">Stroustrup</span>. </span><span class="copyright">Copyright © 2000 Addison Wesley, Inc.. </span><span class="pagenums">Appendix D. </span><span class="publisher"><span class="publishername">

3099

Addison Wesley

3100

- . </span></span></p></div><div class="biblioentry"><a id="idp15911392"></a><p><span class="citetitle"><em class="citetitle">

3101

+ . </span></span></p></div><div class="biblioentry"><a id="idm269999619824"></a><p><span class="citetitle"><em class="citetitle">

3102

Standard C++ IOStreams and Locales

3103

</em>. </span><span class="subtitle">

3104

Advanced Programmer's Guide and Reference

3105

. </span><span class="author"><span class="firstname">Angelika</span> <span class="surname">Langer</span>. </span><span class="author"><span class="firstname">Klaus</span> <span class="surname">Kreft</span>. </span><span class="copyright">Copyright © 2000 Addison Wesley Longman, Inc.. </span><span class="publisher"><span class="publishername">

3106

Addison Wesley Longman

3107

- . </span></span></p></div><div class="biblioentry"><a id="idp15917056"></a><p><span class="title"><em>

3108

+ . </span></span></p></div><div class="biblioentry"><a id="idm269999614160"></a><p><span class="title"><em>

3109

3110

A brief description of Normative Addendum 1

3111

</a>

3112

- </em>. </span><span class="author"><span class="firstname">Clive</span> <span class="surname">Feather</span>. </span><span class="pagenums">Extended Character Sets. </span></p></div><div class="biblioentry"><a id="idp15920304"></a><p><span class="title"><em>

3113

+ </em>. </span><span class="author"><span class="firstname">Clive</span> <span class="surname">Feather</span>. </span><span class="pagenums">Extended Character Sets. </span></p></div><div class="biblioentry"><a id="idm269999610912"></a><p><span class="title"><em>

3114

3115

The Unicode HOWTO

3116

</a>

3117

- </em>. </span><span class="author"><span class="firstname">Bruno</span> <span class="surname">Haible</span>. </span></p></div><div class="biblioentry"><a id="idp15923088"></a><p><span class="title"><em>

3118

+ </em>. </span><span class="author"><span class="firstname">Bruno</span> <span class="surname">Haible</span>. </span></p></div><div class="biblioentry"><a id="idm269999608128"></a><p><span class="title"><em>

3119

3120

UTF-8 and Unicode FAQ for Unix/Linux

3121

</a>

3122

@@ -690,16 +690,16 @@

3123

model. As of this writing, it is unknown how to query to see

3124

if a specified message catalog exists using the gettext

3125

package.

3126

- </p></li></ul></div></div><div class="bibliography"><div class="titlepage"><div><div><h4 class="title"><a id="facet.messages.biblio"></a>Bibliography</h4></div></div></div><div class="biblioentry"><a id="idp16003632"></a><p><span class="citetitle"><em class="citetitle">

3127

+ </p></li></ul></div></div><div class="bibliography"><div class="titlepage"><div><div><h4 class="title"><a id="facet.messages.biblio"></a>Bibliography</h4></div></div></div><div class="biblioentry"><a id="idm269999527584"></a><p><span class="citetitle"><em class="citetitle">

3128

The GNU C Library

3129

</em>. </span><span class="author"><span class="firstname">Roland</span> <span class="surname">McGrath</span>. </span><span class="author"><span class="firstname">Ulrich</span> <span class="surname">Drepper</span>. </span><span class="copyright">Copyright © 2007 FSF. </span><span class="pagenums">Chapters 6 Character Set Handling, and 7 Locales and Internationalization

3130

- . </span></p></div><div class="biblioentry"><a id="idp16008384"></a><p><span class="citetitle"><em class="citetitle">

3131

+ . </span></p></div><div class="biblioentry"><a id="idm269999522832"></a><p><span class="citetitle"><em class="citetitle">

3132

Correspondence

3133

- </em>. </span><span class="author"><span class="firstname">Ulrich</span> <span class="surname">Drepper</span>. </span><span class="copyright">Copyright © 2002 . </span></p></div><div class="biblioentry"><a id="idp16011472"></a><p><span class="citetitle"><em class="citetitle">

3134

+ </em>. </span><span class="author"><span class="firstname">Ulrich</span> <span class="surname">Drepper</span>. </span><span class="copyright">Copyright © 2002 . </span></p></div><div class="biblioentry"><a id="idm269999519744"></a><p><span class="citetitle"><em class="citetitle">

3135

ISO/IEC 14882:1998 Programming languages - C++

3136

3137

3138

ISO/IEC 9899:1999 Programming languages - C

3139

3140

3141

3142

System Interface Definitions, Issue 7 (IEEE Std. 1003.1-2008)

3143

</a>

3144

@@ -706,23 +706,23 @@

3145

3146

The Open Group/The Institute of Electrical and Electronics

3147

Engineers, Inc.

3148

- . </span></p></div><div class="biblioentry"><a id="idp16019264"></a><p><span class="citetitle"><em class="citetitle">

3149

+ . </span></p></div><div class="biblioentry"><a id="idm269999511952"></a><p><span class="citetitle"><em class="citetitle">

3150

The C++ Programming Language, Special Edition

3151

</em>. </span><span class="author"><span class="firstname">Bjarne</span> <span class="surname">Stroustrup</span>. </span><span class="copyright">Copyright © 2000 Addison Wesley, Inc.. </span><span class="pagenums">Appendix D. </span><span class="publisher"><span class="publishername">

3152

Addison Wesley

3153

- . </span></span></p></div><div class="biblioentry"><a id="idp16023888"></a><p><span class="citetitle"><em class="citetitle">

3154

+ . </span></span></p></div><div class="biblioentry"><a id="idm269999507328"></a><p><span class="citetitle"><em class="citetitle">

3155

Standard C++ IOStreams and Locales

3156

</em>. </span><span class="subtitle">

3157

Advanced Programmer's Guide and Reference

3158

. </span><span class="author"><span class="firstname">Angelika</span> <span class="surname">Langer</span>. </span><span class="author"><span class="firstname">Klaus</span> <span class="surname">Kreft</span>. </span><span class="copyright">Copyright © 2000 Addison Wesley Longman, Inc.. </span><span class="publisher"><span class="publishername">

3159

Addison Wesley Longman

3160

- . </span></span></p></div><div class="biblioentry"><a id="idp16029552"></a><p><span class="title"><em>

3161

- <a class="link" href="http://java.sun.com/reference/api/index.html" target="_top">

3162

+ . </span></span></p></div><div class="biblioentry"><a id="idm269999501664"></a><p><span class="title"><em>

3163

+ <a class="link" href="http://www.oracle.com/technetwork/java/api/index.html" target="_top">

3164

API Specifications, Java Platform

3165

</a>

3166

</em>. </span><span class="pagenums">java.util.Properties, java.text.MessageFormat,

3167

java.util.Locale, java.util.ResourceBundle

3168

- . </span></p></div><div class="biblioentry"><a id="idp16031888"></a><p><span class="title"><em>

3169

+ . </span></p></div><div class="biblioentry"><a id="idm269999499328"></a><p><span class="title"><em>

3170

3171

GNU gettext tools, version 0.10.38, Native Language Support

3172

Library and Tools.

3173

Index: libstdc++-v3/doc/html/manual/diagnostics.html

3174

===================================================================

3175

--- a/src/libstdc++-v3/doc/html/manual/diagnostics.html (.../tags/gcc_4_8_2_release)

3176

+++ b/src/libstdc++-v3/doc/html/manual/diagnostics.html (.../branches/gcc-4_8-branch)

3177

@@ -1,5 +1,5 @@

3178

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

3179

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 5. Diagnostics</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II. Standard Contents" /><link rel="prev" href="termination.html" title="Termination" /><link rel="next" href="concept_checking.html" title="Concept Checking" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 5.

3180

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 5. Diagnostics</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II. Standard Contents" /><link rel="prev" href="termination.html" title="Termination" /><link rel="next" href="concept_checking.html" title="Concept Checking" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 5.

3181

Diagnostics

3182

3183

</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="termination.html">Prev</a> </td><th width="60%" align="center">Part II.

3184

@@ -6,8 +6,8 @@

3185

Standard Contents

3186

</th><td width="20%" align="right"> <a accesskey="n" href="concept_checking.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="std.diagnostics"></a>Chapter 5.

3187

Diagnostics

3188

- <a id="idp13835248" class="indexterm"></a>

3189

-</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="diagnostics.html#std.diagnostics.exceptions">Exceptions</a></span></dt><dd><dl><dt><span class="section"><a href="diagnostics.html#std.diagnostics.exceptions.api">API Reference</a></span></dt><dt><span class="section"><a href="diagnostics.html#std.diagnostics.exceptions.data">Adding Data to <code class="classname">exception</code></a></span></dt></dl></dd><dt><span class="section"><a href="concept_checking.html">Concept Checking</a></span></dt></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.diagnostics.exceptions"></a>Exceptions</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="std.diagnostics.exceptions.api"></a>API Reference</h3></div></div></div><p>

3190

+ <a id="idm270001697504" class="indexterm"></a>

3191

+</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="diagnostics.html#std.diagnostics.exceptions">Exceptions</a></span></dt><dd><dl><dt><span class="section"><a href="diagnostics.html#std.diagnostics.exceptions.api">API Reference</a></span></dt><dt><span class="section"><a href="diagnostics.html#std.diagnostics.exceptions.data">Adding Data to <code class="classname">exception</code></a></span></dt></dl></dd><dt><span class="section"><a href="concept_checking.html">Concept Checking</a></span></dt></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.diagnostics.exceptions"></a>Exceptions</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="std.diagnostics.exceptions.api"></a>API Reference</h3></div></div></div><p>

3192

All exception objects are defined in one of the standard header

3193

files: <code class="filename">exception</code>,

3194

<code class="filename">stdexcept</code>, <code class="filename">new</code>, and

3195

Index: libstdc++-v3/doc/html/manual/mt_allocator_design.html

3196

===================================================================

3197

--- a/src/libstdc++-v3/doc/html/manual/mt_allocator_design.html (.../tags/gcc_4_8_2_release)

3198

+++ b/src/libstdc++-v3/doc/html/manual/mt_allocator_design.html (.../branches/gcc-4_8-branch)

3199

@@ -1,5 +1,5 @@

3200

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

3201

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design Issues</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, allocator" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="mt_allocator.html" title="Chapter 20. The mt_allocator" /><link rel="prev" href="mt_allocator.html" title="Chapter 20. The mt_allocator" /><link rel="next" href="mt_allocator_impl.html" title="Implementation" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design Issues</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="mt_allocator.html">Prev</a> </td><th width="60%" align="center">Chapter 20. The mt_allocator</th><td width="20%" align="right"> <a accesskey="n" href="mt_allocator_impl.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="allocator.mt.design_issues"></a>Design Issues</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="allocator.mt.overview"></a>Overview</h3></div></div></div><p> There are three general components to the allocator: a datum

3202

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design Issues</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, allocator" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="mt_allocator.html" title="Chapter 20. The mt_allocator" /><link rel="prev" href="mt_allocator.html" title="Chapter 20. The mt_allocator" /><link rel="next" href="mt_allocator_impl.html" title="Implementation" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design Issues</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="mt_allocator.html">Prev</a> </td><th width="60%" align="center">Chapter 20. The mt_allocator</th><td width="20%" align="right"> <a accesskey="n" href="mt_allocator_impl.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="allocator.mt.design_issues"></a>Design Issues</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="allocator.mt.overview"></a>Overview</h3></div></div></div><p> There are three general components to the allocator: a datum

3203

describing the characteristics of the memory pool, a policy class

3204

containing this pool that links instantiation types to common or

3205

individual pools, and a class inheriting from the policy class that is

3206

Index: libstdc++-v3/doc/html/manual/appendix_free.html

3207

===================================================================

3208

--- a/src/libstdc++-v3/doc/html/manual/appendix_free.html (.../tags/gcc_4_8_2_release)

3209

+++ b/src/libstdc++-v3/doc/html/manual/appendix_free.html (.../branches/gcc-4_8-branch)

3210

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3211

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

3212

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Appendix C. Free Software Needs Free Documentation</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix.html" title="Part IV. Appendices" /><link rel="prev" href="backwards.html" title="Backwards Compatibility" /><link rel="next" href="appendix_gpl.html" title="Appendix D. GNU General Public License version 3" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Appendix C.

3213

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Appendix C. Free Software Needs Free Documentation</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix.html" title="Part IV. Appendices" /><link rel="prev" href="backwards.html" title="Backwards Compatibility" /><link rel="next" href="appendix_gpl.html" title="Appendix D. GNU General Public License version 3" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Appendix C.

3214

Free Software Needs Free Documentation

3215

3216

</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="backwards.html">Prev</a> </td><th width="60%" align="center">Part IV.

3217

@@ -6,7 +6,7 @@

3218

Appendices

3219

</th><td width="20%" align="right"> <a accesskey="n" href="appendix_gpl.html">Next</a></td></tr></table><hr /></div><div class="appendix"><div class="titlepage"><div><div><h1 class="title"><a id="appendix.free"></a>

3220

Free Software Needs Free Documentation

3221

- <a id="idp23426192" class="indexterm"></a>

3222

+ <a id="idm269992106560" class="indexterm"></a>

3223

</h1></div></div></div><p>

3224

The biggest deficiency in free operating systems is not in the

3225

software--it is the lack of good free manuals that we can include in

3226

Index: libstdc++-v3/doc/html/manual/algorithms.html

3227

===================================================================

3228

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3229

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3230

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3231

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

3232

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3233

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 11. Algorithms</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library, algorithm" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II. Standard Contents" /><link rel="prev" href="iterators.html" title="Chapter 10. Iterators" /><link rel="next" href="numerics.html" title="Chapter 12. Numerics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 11.

3234

Algorithms

3235

3236

</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="iterators.html">Prev</a> </td><th width="60%" align="center">Part II.

3237

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3238

Standard Contents

3239

</th><td width="20%" align="right"> <a accesskey="n" href="numerics.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="std.algorithms"></a>Chapter 11.

3240

Algorithms

3241

- <a id="idp16191968" class="indexterm"></a>

3242

-</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="algorithms.html#std.algorithms.mutating">Mutating</a></span></dt><dd><dl><dt><span class="section"><a href="algorithms.html#algorithms.mutating.swap"><code class="function">swap</code></a></span></dt><dd><dl><dt><span class="section"><a href="algorithms.html#algorithms.swap.specializations">Specializations</a></span></dt></dl></dd></dl></dd></dl></div><p>

3243

+ <a id="idm269999339120" class="indexterm"></a>

3244

+</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="algorithms.html#std.algorithms.mutating">Mutating</a></span></dt><dd><dl><dt><span class="section"><a href="algorithms.html#algorithms.mutating.swap"><code class="function">swap</code></a></span></dt><dd><dl><dt><span class="section"><a href="algorithms.html#algorithms.swap.specializations">Specializations</a></span></dt></dl></dd></dl></dd></dl></div><p>

3245

The neatest accomplishment of the algorithms section is that all the

3246

work is done via iterators, not containers directly. This means two

3247

important things:

3248

Index: libstdc++-v3/doc/html/manual/appendix_porting.html

3249

===================================================================

3250

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3251

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3252

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3253

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

3254

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3255

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Appendix B. Porting and Maintenance</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix.html" title="Part IV. Appendices" /><link rel="prev" href="source_design_notes.html" title="Design Notes" /><link rel="next" href="documentation_hacking.html" title="Writing and Generating Documentation" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Appendix B.

3256

Porting and Maintenance

3257

3258

</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="source_design_notes.html">Prev</a> </td><th width="60%" align="center">Part IV.

3259

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3260

Appendices

3261

</th><td width="20%" align="right"> <a accesskey="n" href="documentation_hacking.html">Next</a></td></tr></table><hr /></div><div class="appendix"><div class="titlepage"><div><div><h1 class="title"><a id="appendix.porting"></a>

3262

Porting and Maintenance

3263

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3264

-</h1></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="appendix_porting.html#appendix.porting.build_hacking">Configure and Build Hacking</a></span></dt><dd><dl><dt><span class="section"><a href="appendix_porting.html#build_hacking.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="appendix_porting.html#build_hacking.overview">Overview</a></span></dt><dd><dl><dt><span class="section"><a href="appendix_porting.html#build_hacking.overview.basic">General Process</a></span></dt><dt><span class="section"><a href="appendix_porting.html#build_hacking.overview.map">What Comes from Where</a></span></dt></dl></dd><dt><span class="section"><a href="appendix_porting.html#build_hacking.configure">Configure</a></span></dt><dd><dl><dt><span class="section"><a href="appendix_porting.html#build_hacking.configure.scripts">Storing Information in non-AC files (like configure.host)</a></span></dt><dt><span class="section"><a href="appendix_porting.html#build_hacking.configure.conventions">Coding and Commenting Conventions</a></span></dt><dt><span class="section"><a href="appendix_porting.html#build_hacking.configure.acinclude">The acinclude.m4 layout</a></span></dt><dt><span class="section"><a href="appendix_porting.html#build_hacking.configure.enable"><code class="constant">GLIBCXX_ENABLE</code>, the <code class="literal">--enable</code> maker</a></span></dt></dl></dd><dt><span class="section"><a href="appendix_porting.html#build_hacking.make">Make</a></span></dt></dl></dd><dt><span class="section"><a href="documentation_hacking.html">Writing and Generating Documentation</a></span></dt><dd><dl><dt><span class="section"><a href="documentation_hacking.html#doc.intro">Introduction</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#doc.generation">Generating Documentation</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#doc.doxygen">Doxygen</a></span></dt><dd><dl><dt><span class="section"><a href="documentation_hacking.html#doxygen.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#doxygen.rules">Generating the Doxygen Files</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#doxygen.debug">Debugging Generation</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#doxygen.markup">Markup</a></span></dt></dl></dd><dt><span class="section"><a href="documentation_hacking.html#doc.docbook">Docbook</a></span></dt><dd><dl><dt><span class="section"><a href="documentation_hacking.html#docbook.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#docbook.rules">Generating the DocBook Files</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#docbook.debug">Debugging Generation</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#docbook.validation">Editing and Validation</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#docbook.examples">File Organization and Basics</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#docbook.markup">Markup By Example</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="internals.html">Porting to New Hardware or Operating Systems</a></span></dt><dd><dl><dt><span class="section"><a href="internals.html#internals.os">Operating System</a></span></dt><dt><span class="section"><a href="internals.html#internals.cpu">CPU</a></span></dt><dt><span class="section"><a href="internals.html#internals.char_types">Character Types</a></span></dt><dt><span class="section"><a href="internals.html#internals.thread_safety">Thread Safety</a></span></dt><dt><span class="section"><a href="internals.html#internals.numeric_limits">Numeric Limits</a></span></dt><dt><span class="section"><a href="internals.html#internals.libtool">Libtool</a></span></dt></dl></dd><dt><span class="section"><a href="test.html">Test</a></span></dt><dd><dl><dt><span class="section"><a href="test.html#test.organization">Organization</a></span></dt><dd><dl><dt><span class="section"><a href="test.html#test.organization.layout">Directory Layout</a></span></dt><dt><span class="section"><a href="test.html#test.organization.naming">Naming Conventions</a></span></dt></dl></dd><dt><span class="section"><a href="test.html#test.run">Running the Testsuite</a></span></dt><dd><dl><dt><span class="section"><a href="test.html#test.run.basic">Basic</a></span></dt><dt><span class="section"><a href="test.html#test.run.variations">Variations</a></span></dt><dt><span class="section"><a href="test.html#test.run.permutations">Permutations</a></span></dt></dl></dd><dt><span class="section"><a href="test.html#test.new_tests">Writing a new test case</a></span></dt><dt><span class="section"><a href="test.html#test.harness">Test Harness and Utilities</a></span></dt><dd><dl><dt><span class="section"><a href="test.html#test.harness.dejagnu">Dejagnu Harness Details</a></span></dt><dt><span class="section"><a href="test.html#test.harness.utils">Utilities</a></span></dt></dl></dd><dt><span class="section"><a href="test.html#test.special">Special Topics</a></span></dt><dd><dl><dt><span class="section"><a href="test.html#test.exception.safety">

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+ <a id="idm269993523968" class="indexterm"></a>

3266

+</h1></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="appendix_porting.html#appendix.porting.build_hacking">Configure and Build Hacking</a></span></dt><dd><dl><dt><span class="section"><a href="appendix_porting.html#build_hacking.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="appendix_porting.html#build_hacking.overview">Overview</a></span></dt><dd><dl><dt><span class="section"><a href="appendix_porting.html#build_hacking.overview.basic">General Process</a></span></dt><dt><span class="section"><a href="appendix_porting.html#build_hacking.overview.map">What Comes from Where</a></span></dt></dl></dd><dt><span class="section"><a href="appendix_porting.html#build_hacking.configure">Configure</a></span></dt><dd><dl><dt><span class="section"><a href="appendix_porting.html#build_hacking.configure.scripts">Storing Information in non-AC files (like configure.host)</a></span></dt><dt><span class="section"><a href="appendix_porting.html#build_hacking.configure.conventions">Coding and Commenting Conventions</a></span></dt><dt><span class="section"><a href="appendix_porting.html#build_hacking.configure.acinclude">The acinclude.m4 layout</a></span></dt><dt><span class="section"><a href="appendix_porting.html#build_hacking.configure.enable"><code class="constant">GLIBCXX_ENABLE</code>, the <code class="literal">--enable</code> maker</a></span></dt></dl></dd><dt><span class="section"><a href="appendix_porting.html#build_hacking.make">Make</a></span></dt></dl></dd><dt><span class="section"><a href="documentation_hacking.html">Writing and Generating Documentation</a></span></dt><dd><dl><dt><span class="section"><a href="documentation_hacking.html#doc.intro">Introduction</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#doc.generation">Generating Documentation</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#doc.doxygen">Doxygen</a></span></dt><dd><dl><dt><span class="section"><a href="documentation_hacking.html#doxygen.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#doxygen.rules">Generating the Doxygen Files</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#doxygen.debug">Debugging Generation</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#doxygen.markup">Markup</a></span></dt></dl></dd><dt><span class="section"><a href="documentation_hacking.html#doc.docbook">Docbook</a></span></dt><dd><dl><dt><span class="section"><a href="documentation_hacking.html#docbook.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#docbook.rules">Generating the DocBook Files</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#docbook.debug">Debugging Generation</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#docbook.validation">Editing and Validation</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#docbook.examples">File Organization and Basics</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#docbook.markup">Markup By Example</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="internals.html">Porting to New Hardware or Operating Systems</a></span></dt><dd><dl><dt><span class="section"><a href="internals.html#internals.os">Operating System</a></span></dt><dt><span class="section"><a href="internals.html#internals.cpu">CPU</a></span></dt><dt><span class="section"><a href="internals.html#internals.char_types">Character Types</a></span></dt><dt><span class="section"><a href="internals.html#internals.thread_safety">Thread Safety</a></span></dt><dt><span class="section"><a href="internals.html#internals.numeric_limits">Numeric Limits</a></span></dt><dt><span class="section"><a href="internals.html#internals.libtool">Libtool</a></span></dt></dl></dd><dt><span class="section"><a href="test.html">Test</a></span></dt><dd><dl><dt><span class="section"><a href="test.html#test.organization">Organization</a></span></dt><dd><dl><dt><span class="section"><a href="test.html#test.organization.layout">Directory Layout</a></span></dt><dt><span class="section"><a href="test.html#test.organization.naming">Naming Conventions</a></span></dt></dl></dd><dt><span class="section"><a href="test.html#test.run">Running the Testsuite</a></span></dt><dd><dl><dt><span class="section"><a href="test.html#test.run.basic">Basic</a></span></dt><dt><span class="section"><a href="test.html#test.run.variations">Variations</a></span></dt><dt><span class="section"><a href="test.html#test.run.permutations">Permutations</a></span></dt></dl></dd><dt><span class="section"><a href="test.html#test.new_tests">Writing a new test case</a></span></dt><dt><span class="section"><a href="test.html#test.harness">Test Harness and Utilities</a></span></dt><dd><dl><dt><span class="section"><a href="test.html#test.harness.dejagnu">Dejagnu Harness Details</a></span></dt><dt><span class="section"><a href="test.html#test.harness.utils">Utilities</a></span></dt></dl></dd><dt><span class="section"><a href="test.html#test.special">Special Topics</a></span></dt><dd><dl><dt><span class="section"><a href="test.html#test.exception.safety">

3267

Qualifying Exception Safety Guarantees

3268

3269

</a></span></dt><dd><dl><dt><span class="section"><a href="test.html#test.exception.safety.overview">Overview</a></span></dt><dt><span class="section"><a href="test.html#test.exception.safety.status">

3270

@@ -61,7 +61,7 @@

3271

in the build directory starts the build process. The <code class="literal">all</code> target comes from the <code class="filename">Makefile</code> file, which is generated via <span class="command"><strong>configure</strong></span> from the <code class="filename">Makefile.in</code> file, which is in turn generated (via

3272

<span class="command"><strong>automake</strong></span>) from the file

3273

<code class="filename">Makefile.am</code>.

3274

-</p></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="build_hacking.overview.map"></a>What Comes from Where</h4></div></div></div><div class="figure"><a id="idp22035648"></a><p class="title"><strong>Figure B.1. Configure and Build File Dependencies</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/confdeps.png" align="middle" alt="Dependency Graph for Configure and Build Files" /></div></div></div><br class="figure-break" /><p>

3275

+</p></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="build_hacking.overview.map"></a>What Comes from Where</h4></div></div></div><div class="figure"><a id="idm269993497120"></a><p class="title"><strong>Figure B.1. Configure and Build File Dependencies</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/confdeps.png" align="middle" alt="Dependency Graph for Configure and Build Files" /></div></div></div><br class="figure-break" /><p>

3276

Regenerate all generated files by using the command

3277

<code class="code">autoreconf</code> at the top level of the libstdc++ source

3278

directory.

3279

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3280

===================================================================

3281

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3282

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3283

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3284

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

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-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Empirical Cost Model</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="prev" href="profile_mode_api.html" title="Extensions for Custom Containers" /><link rel="next" href="profile_mode_impl.html" title="Implementation Issues" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Empirical Cost Model</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="profile_mode_api.html">Prev</a> </td><th width="60%" align="center">Chapter 19. Profile Mode</th><td width="20%" align="right"> <a accesskey="n" href="profile_mode_impl.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.cost_model"></a>Empirical Cost Model</h2></div></div></div><p>

3286

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Empirical Cost Model</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="prev" href="profile_mode_api.html" title="Extensions for Custom Containers" /><link rel="next" href="profile_mode_impl.html" title="Implementation Issues" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Empirical Cost Model</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="profile_mode_api.html">Prev</a> </td><th width="60%" align="center">Chapter 19. Profile Mode</th><td width="20%" align="right"> <a accesskey="n" href="profile_mode_impl.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.cost_model"></a>Empirical Cost Model</h2></div></div></div><p>

3287

Currently, the cost model uses formulas with predefined relative weights

3288

for alternative containers or container implementations. For instance,

3289

iterating through a vector is X times faster than iterating through a list.

3290

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3291

===================================================================

3292

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3293

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3294

@@ -1,5 +1,5 @@

3295

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

3296

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Make</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="setup.html" title="Chapter 2. Setup" /><link rel="prev" href="configure.html" title="Configure" /><link rel="next" href="using.html" title="Chapter 3. Using" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Make</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="configure.html">Prev</a> </td><th width="60%" align="center">Chapter 2. Setup</th><td width="20%" align="right"> <a accesskey="n" href="using.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.setup.make"></a>Make</h2></div></div></div><p>If you have never done this before, you should read the basic

3297

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Make</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="setup.html" title="Chapter 2. Setup" /><link rel="prev" href="configure.html" title="Configure" /><link rel="next" href="using.html" title="Chapter 3. Using" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Make</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="configure.html">Prev</a> </td><th width="60%" align="center">Chapter 2. Setup</th><td width="20%" align="right"> <a accesskey="n" href="using.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.setup.make"></a>Make</h2></div></div></div><p>If you have never done this before, you should read the basic

3298

<a class="link" href="http://gcc.gnu.org/install/" target="_top">GCC Installation

3299

Instructions</a> first. Read <span class="emphasis"><em>all of them</em></span>.

3300

<span class="emphasis"><em>Twice.</em></span>

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3303

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>

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-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Pairs</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="utilities.html" title="Chapter 6. Utilities" /><link rel="prev" href="utilities.html" title="Chapter 6. Utilities" /><link rel="next" href="memory.html" title="Memory" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Pairs</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="utilities.html">Prev</a> </td><th width="60%" align="center">Chapter 6.

3308

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Pairs</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="utilities.html" title="Chapter 6. Utilities" /><link rel="prev" href="utilities.html" title="Chapter 6. Utilities" /><link rel="next" href="memory.html" title="Memory" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Pairs</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="utilities.html">Prev</a> </td><th width="60%" align="center">Chapter 6.

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Utilities

3310

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</th><td width="20%" align="right"> <a accesskey="n" href="memory.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.util.pairs"></a>Pairs</h2></div></div></div><p>The <code class="code">pair<T1,T2></code> is a simple and handy way to

3312

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===================================================================

3314

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>

3318

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Test</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, test, testsuite, performance, conformance, ABI, exception safety" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B. Porting and Maintenance" /><link rel="prev" href="internals.html" title="Porting to New Hardware or Operating Systems" /><link rel="next" href="abi.html" title="ABI Policy and Guidelines" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Test</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="internals.html">Prev</a> </td><th width="60%" align="center">Appendix B.

3319

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Test</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, test, testsuite, performance, conformance, ABI, exception safety" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B. Porting and Maintenance" /><link rel="prev" href="internals.html" title="Porting to New Hardware or Operating Systems" /><link rel="next" href="abi.html" title="ABI Policy and Guidelines" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Test</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="internals.html">Prev</a> </td><th width="60%" align="center">Appendix B.

3320

Porting and Maintenance

3321

3322

</th><td width="20%" align="right"> <a accesskey="n" href="abi.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.setup.test"></a>Test</h2></div></div></div><p>

3323

@@ -492,7 +492,7 @@

3324

reporting functions including:

3325

</p><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: circle; "><li class="listitem"><p>time_counter</p></li><li class="listitem"><p>resource_counter</p></li><li class="listitem"><p>report_performance</p></li></ul></div></li></ul></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="test.special"></a>Special Topics</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="test.exception.safety"></a>

3326

Qualifying Exception Safety Guarantees

3327

- <a id="idp22628992" class="indexterm"></a>

3328

+ <a id="idm269992903504" class="indexterm"></a>

3329

</h4></div></div></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="test.exception.safety.overview"></a>Overview</h5></div></div></div><p>

3330

Testing is composed of running a particular test sequence,

3331

and looking at what happens to the surrounding code when

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===================================================================

3334

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>

3338

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Linking</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_namespaces.html" title="Namespaces" /><link rel="next" href="using_concurrency.html" title="Concurrency" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Linking</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_namespaces.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="using_concurrency.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.linkage"></a>Linking</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.intro.using.linkage.freestanding"></a>Almost Nothing</h3></div></div></div><p>

3339

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Linking</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_namespaces.html" title="Namespaces" /><link rel="next" href="using_concurrency.html" title="Concurrency" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Linking</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_namespaces.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="using_concurrency.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.linkage"></a>Linking</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.intro.using.linkage.freestanding"></a>Almost Nothing</h3></div></div></div><p>

3340

Or as close as it gets: freestanding. This is a minimal

3341

configuration, with only partial support for the standard

3342

library. Assume only the following header files can be used:

3343

Index: libstdc++-v3/doc/html/manual/using_headers.html

3344

===================================================================

3345

--- a/src/libstdc++-v3/doc/html/manual/using_headers.html (.../tags/gcc_4_8_2_release)

3346

+++ b/src/libstdc++-v3/doc/html/manual/using_headers.html (.../branches/gcc-4_8-branch)

3347

@@ -1,5 +1,5 @@

3348

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

3349

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Headers</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using.html" title="Chapter 3. Using" /><link rel="next" href="using_macros.html" title="Macros" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Headers</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="using_macros.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.headers"></a>Headers</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.intro.using.headers.all"></a>Header Files</h3></div></div></div><p>

3350

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Headers</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using.html" title="Chapter 3. Using" /><link rel="next" href="using_macros.html" title="Macros" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Headers</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="using_macros.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.headers"></a>Headers</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.intro.using.headers.all"></a>Header Files</h3></div></div></div><p>

3351

The C++ standard specifies the entire set of header files that

3352

must be available to all hosted implementations. Actually, the

3353

word "files" is a misnomer, since the contents of the

3354

@@ -18,19 +18,19 @@

3355

the 1998 standard as updated for 2003, and the current 2011 standard.

3356

</p><p>

3357

C++98/03 include files. These are available in the default compilation mode, i.e. <code class="code">-std=c++98</code> or <code class="code">-std=gnu++98</code>.

3358

- </p><div class="table"><a id="idp13079360"></a><p class="title"><strong>Table 3.2. C++ 1998 Library Headers</strong></p><div class="table-contents"><table summary="C++ 1998 Library Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="filename">bitset</code></td><td align="left"><code class="filename">complex</code></td><td align="left"><code class="filename">deque</code></td><td align="left"><code class="filename">exception</code></td></tr><tr><td align="left"><code class="filename">fstream</code></td><td align="left"><code class="filename">functional</code></td><td align="left"><code class="filename">iomanip</code></td><td align="left"><code class="filename">ios</code></td><td align="left"><code class="filename">iosfwd</code></td></tr><tr><td align="left"><code class="filename">iostream</code></td><td align="left"><code class="filename">istream</code></td><td align="left"><code class="filename">iterator</code></td><td align="left"><code class="filename">limits</code></td><td align="left"><code class="filename">list</code></td></tr><tr><td align="left"><code class="filename">locale</code></td><td align="left"><code class="filename">map</code></td><td align="left"><code class="filename">memory</code></td><td align="left"><code class="filename">new</code></td><td align="left"><code class="filename">numeric</code></td></tr><tr><td align="left"><code class="filename">ostream</code></td><td align="left"><code class="filename">queue</code></td><td align="left"><code class="filename">set</code></td><td align="left"><code class="filename">sstream</code></td><td align="left"><code class="filename">stack</code></td></tr><tr><td align="left"><code class="filename">stdexcept</code></td><td align="left"><code class="filename">streambuf</code></td><td align="left"><code class="filename">string</code></td><td align="left"><code class="filename">utility</code></td><td align="left"><code class="filename">typeinfo</code></td></tr><tr><td align="left"><code class="filename">valarray</code></td><td align="left"><code class="filename">vector</code></td><td class="auto-generated"> </td><td class="auto-generated"> </td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="idp13115840"></a><p class="title"><strong>Table 3.3. C++ 1998 Library Headers for C Library Facilities</strong></p><div class="table-contents"><table summary="C++ 1998 Library Headers for C Library Facilities" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">cassert</code></td><td align="left"><code class="filename">cerrno</code></td><td align="left"><code class="filename">cctype</code></td><td align="left"><code class="filename">cfloat</code></td><td align="left"><code class="filename">ciso646</code></td></tr><tr><td align="left"><code class="filename">climits</code></td><td align="left"><code class="filename">clocale</code></td><td align="left"><code class="filename">cmath</code></td><td align="left"><code class="filename">csetjmp</code></td><td align="left"><code class="filename">csignal</code></td></tr><tr><td align="left"><code class="filename">cstdarg</code></td><td align="left"><code class="filename">cstddef</code></td><td align="left"><code class="filename">cstdio</code></td><td align="left"><code class="filename">cstdlib</code></td><td align="left"><code class="filename">cstring</code></td></tr><tr><td align="left"><code class="filename">ctime</code></td><td align="left"><code class="filename">cwchar</code></td><td align="left"><code class="filename">cwctype</code></td><td class="auto-generated"> </td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p>

3359

+ </p><div class="table"><a id="idm270002453792"></a><p class="title"><strong>Table 3.2. C++ 1998 Library Headers</strong></p><div class="table-contents"><table summary="C++ 1998 Library Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="filename">bitset</code></td><td align="left"><code class="filename">complex</code></td><td align="left"><code class="filename">deque</code></td><td align="left"><code class="filename">exception</code></td></tr><tr><td align="left"><code class="filename">fstream</code></td><td align="left"><code class="filename">functional</code></td><td align="left"><code class="filename">iomanip</code></td><td align="left"><code class="filename">ios</code></td><td align="left"><code class="filename">iosfwd</code></td></tr><tr><td align="left"><code class="filename">iostream</code></td><td align="left"><code class="filename">istream</code></td><td align="left"><code class="filename">iterator</code></td><td align="left"><code class="filename">limits</code></td><td align="left"><code class="filename">list</code></td></tr><tr><td align="left"><code class="filename">locale</code></td><td align="left"><code class="filename">map</code></td><td align="left"><code class="filename">memory</code></td><td align="left"><code class="filename">new</code></td><td align="left"><code class="filename">numeric</code></td></tr><tr><td align="left"><code class="filename">ostream</code></td><td align="left"><code class="filename">queue</code></td><td align="left"><code class="filename">set</code></td><td align="left"><code class="filename">sstream</code></td><td align="left"><code class="filename">stack</code></td></tr><tr><td align="left"><code class="filename">stdexcept</code></td><td align="left"><code class="filename">streambuf</code></td><td align="left"><code class="filename">string</code></td><td align="left"><code class="filename">utility</code></td><td align="left"><code class="filename">typeinfo</code></td></tr><tr><td align="left"><code class="filename">valarray</code></td><td align="left"><code class="filename">vector</code></td><td class="auto-generated"> </td><td class="auto-generated"> </td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="idm270002417312"></a><p class="title"><strong>Table 3.3. C++ 1998 Library Headers for C Library Facilities</strong></p><div class="table-contents"><table summary="C++ 1998 Library Headers for C Library Facilities" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">cassert</code></td><td align="left"><code class="filename">cerrno</code></td><td align="left"><code class="filename">cctype</code></td><td align="left"><code class="filename">cfloat</code></td><td align="left"><code class="filename">ciso646</code></td></tr><tr><td align="left"><code class="filename">climits</code></td><td align="left"><code class="filename">clocale</code></td><td align="left"><code class="filename">cmath</code></td><td align="left"><code class="filename">csetjmp</code></td><td align="left"><code class="filename">csignal</code></td></tr><tr><td align="left"><code class="filename">cstdarg</code></td><td align="left"><code class="filename">cstddef</code></td><td align="left"><code class="filename">cstdio</code></td><td align="left"><code class="filename">cstdlib</code></td><td align="left"><code class="filename">cstring</code></td></tr><tr><td align="left"><code class="filename">ctime</code></td><td align="left"><code class="filename">cwchar</code></td><td align="left"><code class="filename">cwctype</code></td><td class="auto-generated"> </td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p>

3360

C++11 include files. These are only available in C++11 compilation

3361

mode, i.e. <code class="literal">-std=c++11</code> or <code class="literal">-std=gnu++11</code>.

3362

-</p><p></p><div class="table"><a id="idp13140576"></a><p class="title"><strong>Table 3.4. C++ 2011 Library Headers</strong></p><div class="table-contents"><table summary="C++ 2011 Library Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="filename">array</code></td><td align="left"><code class="filename">bitset</code></td><td align="left"><code class="filename">chrono</code></td><td align="left"><code class="filename">complex</code></td></tr><tr><td align="left"><code class="filename">condition_variable</code></td><td align="left"><code class="filename">deque</code></td><td align="left"><code class="filename">exception</code></td><td align="left"><code class="filename">forward_list</code></td><td align="left"><code class="filename">fstream</code></td></tr><tr><td align="left"><code class="filename">functional</code></td><td align="left"><code class="filename">future</code></td><td align="left"><code class="filename">initalizer_list</code></td><td align="left"><code class="filename">iomanip</code></td><td align="left"><code class="filename">ios</code></td></tr><tr><td align="left"><code class="filename">iosfwd</code></td><td align="left"><code class="filename">iostream</code></td><td align="left"><code class="filename">istream</code></td><td align="left"><code class="filename">iterator</code></td><td align="left"><code class="filename">limits</code></td></tr><tr><td align="left"><code class="filename">list</code></td><td align="left"><code class="filename">locale</code></td><td align="left"><code class="filename">map</code></td><td align="left"><code class="filename">memory</code></td><td align="left"><code class="filename">mutex</code></td></tr><tr><td align="left"><code class="filename">new</code></td><td align="left"><code class="filename">numeric</code></td><td align="left"><code class="filename">ostream</code></td><td align="left"><code class="filename">queue</code></td><td align="left"><code class="filename">random</code></td></tr><tr><td align="left"><code class="filename">ratio</code></td><td align="left"><code class="filename">regex</code></td><td align="left"><code class="filename">set</code></td><td align="left"><code class="filename">sstream</code></td><td align="left"><code class="filename">stack</code></td></tr><tr><td align="left"><code class="filename">stdexcept</code></td><td align="left"><code class="filename">streambuf</code></td><td align="left"><code class="filename">string</code></td><td align="left"><code class="filename">system_error</code></td><td align="left"><code class="filename">thread</code></td></tr><tr><td align="left"><code class="filename">tuple</code></td><td align="left"><code class="filename">type_traits</code></td><td align="left"><code class="filename">typeinfo</code></td><td align="left"><code class="filename">unordered_map</code></td><td align="left"><code class="filename">unordered_set</code></td></tr><tr><td align="left"><code class="filename">utility</code></td><td align="left"><code class="filename">valarray</code></td><td align="left"><code class="filename">vector</code></td><td class="auto-generated"> </td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="idp13192016"></a><p class="title"><strong>Table 3.5. C++ 2011 Library Headers for C Library Facilities</strong></p><div class="table-contents"><table summary="C++ 2011 Library Headers for C Library Facilities" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">cassert</code></td><td align="left"><code class="filename">ccomplex</code></td><td align="left"><code class="filename">cctype</code></td><td align="left"><code class="filename">cerrno</code></td><td align="left"><code class="filename">cfenv</code></td></tr><tr><td align="left"><code class="filename">cfloat</code></td><td align="left"><code class="filename">cinttypes</code></td><td align="left"><code class="filename">ciso646</code></td><td align="left"><code class="filename">climits</code></td><td align="left"><code class="filename">clocale</code></td></tr><tr><td align="left"><code class="filename">cmath</code></td><td align="left"><code class="filename">csetjmp</code></td><td align="left"><code class="filename">csignal</code></td><td align="left"><code class="filename">cstdarg</code></td><td align="left"><code class="filename">cstdbool</code></td></tr><tr><td align="left"><code class="filename">cstddef</code></td><td align="left"><code class="filename">cstdint</code></td><td align="left"><code class="filename">cstdlib</code></td><td align="left"><code class="filename">cstdio</code></td><td align="left"><code class="filename">cstring</code></td></tr><tr><td align="left"><code class="filename">ctgmath</code></td><td align="left"><code class="filename">ctime</code></td><td align="left"><code class="filename">cuchar</code></td><td align="left"><code class="filename">cwchar</code></td><td align="left"><code class="filename">cwctype</code></td></tr></tbody></table></div></div><br class="table-break" /><p>

3363

+</p><p></p><div class="table"><a id="idm270002392576"></a><p class="title"><strong>Table 3.4. C++ 2011 Library Headers</strong></p><div class="table-contents"><table summary="C++ 2011 Library Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="filename">array</code></td><td align="left"><code class="filename">bitset</code></td><td align="left"><code class="filename">chrono</code></td><td align="left"><code class="filename">complex</code></td></tr><tr><td align="left"><code class="filename">condition_variable</code></td><td align="left"><code class="filename">deque</code></td><td align="left"><code class="filename">exception</code></td><td align="left"><code class="filename">forward_list</code></td><td align="left"><code class="filename">fstream</code></td></tr><tr><td align="left"><code class="filename">functional</code></td><td align="left"><code class="filename">future</code></td><td align="left"><code class="filename">initalizer_list</code></td><td align="left"><code class="filename">iomanip</code></td><td align="left"><code class="filename">ios</code></td></tr><tr><td align="left"><code class="filename">iosfwd</code></td><td align="left"><code class="filename">iostream</code></td><td align="left"><code class="filename">istream</code></td><td align="left"><code class="filename">iterator</code></td><td align="left"><code class="filename">limits</code></td></tr><tr><td align="left"><code class="filename">list</code></td><td align="left"><code class="filename">locale</code></td><td align="left"><code class="filename">map</code></td><td align="left"><code class="filename">memory</code></td><td align="left"><code class="filename">mutex</code></td></tr><tr><td align="left"><code class="filename">new</code></td><td align="left"><code class="filename">numeric</code></td><td align="left"><code class="filename">ostream</code></td><td align="left"><code class="filename">queue</code></td><td align="left"><code class="filename">random</code></td></tr><tr><td align="left"><code class="filename">ratio</code></td><td align="left"><code class="filename">regex</code></td><td align="left"><code class="filename">set</code></td><td align="left"><code class="filename">sstream</code></td><td align="left"><code class="filename">stack</code></td></tr><tr><td align="left"><code class="filename">stdexcept</code></td><td align="left"><code class="filename">streambuf</code></td><td align="left"><code class="filename">string</code></td><td align="left"><code class="filename">system_error</code></td><td align="left"><code class="filename">thread</code></td></tr><tr><td align="left"><code class="filename">tuple</code></td><td align="left"><code class="filename">type_traits</code></td><td align="left"><code class="filename">typeinfo</code></td><td align="left"><code class="filename">unordered_map</code></td><td align="left"><code class="filename">unordered_set</code></td></tr><tr><td align="left"><code class="filename">utility</code></td><td align="left"><code class="filename">valarray</code></td><td align="left"><code class="filename">vector</code></td><td class="auto-generated"> </td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="idm270002341136"></a><p class="title"><strong>Table 3.5. C++ 2011 Library Headers for C Library Facilities</strong></p><div class="table-contents"><table summary="C++ 2011 Library Headers for C Library Facilities" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">cassert</code></td><td align="left"><code class="filename">ccomplex</code></td><td align="left"><code class="filename">cctype</code></td><td align="left"><code class="filename">cerrno</code></td><td align="left"><code class="filename">cfenv</code></td></tr><tr><td align="left"><code class="filename">cfloat</code></td><td align="left"><code class="filename">cinttypes</code></td><td align="left"><code class="filename">ciso646</code></td><td align="left"><code class="filename">climits</code></td><td align="left"><code class="filename">clocale</code></td></tr><tr><td align="left"><code class="filename">cmath</code></td><td align="left"><code class="filename">csetjmp</code></td><td align="left"><code class="filename">csignal</code></td><td align="left"><code class="filename">cstdarg</code></td><td align="left"><code class="filename">cstdbool</code></td></tr><tr><td align="left"><code class="filename">cstddef</code></td><td align="left"><code class="filename">cstdint</code></td><td align="left"><code class="filename">cstdlib</code></td><td align="left"><code class="filename">cstdio</code></td><td align="left"><code class="filename">cstring</code></td></tr><tr><td align="left"><code class="filename">ctgmath</code></td><td align="left"><code class="filename">ctime</code></td><td align="left"><code class="filename">cuchar</code></td><td align="left"><code class="filename">cwchar</code></td><td align="left"><code class="filename">cwctype</code></td></tr></tbody></table></div></div><br class="table-break" /><p>

3364

In addition, TR1 includes as:

3365

-</p><div class="table"><a id="idp13221904"></a><p class="title"><strong>Table 3.6. C++ TR 1 Library Headers</strong></p><div class="table-contents"><table summary="C++ TR 1 Library Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">tr1/array</code></td><td align="left"><code class="filename">tr1/complex</code></td><td align="left"><code class="filename">tr1/memory</code></td><td align="left"><code class="filename">tr1/functional</code></td><td align="left"><code class="filename">tr1/random</code></td></tr><tr><td align="left"><code class="filename">tr1/regex</code></td><td align="left"><code class="filename">tr1/tuple</code></td><td align="left"><code class="filename">tr1/type_traits</code></td><td align="left"><code class="filename">tr1/unordered_map</code></td><td align="left"><code class="filename">tr1/unordered_set</code></td></tr><tr><td align="left"><code class="filename">tr1/utility</code></td><td class="auto-generated"> </td><td class="auto-generated"> </td><td class="auto-generated"> </td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="idp13238832"></a><p class="title"><strong>Table 3.7. C++ TR 1 Library Headers for C Library Facilities</strong></p><div class="table-contents"><table summary="C++ TR 1 Library Headers for C Library Facilities" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">tr1/ccomplex</code></td><td align="left"><code class="filename">tr1/cfenv</code></td><td align="left"><code class="filename">tr1/cfloat</code></td><td align="left"><code class="filename">tr1/cmath</code></td><td align="left"><code class="filename">tr1/cinttypes</code></td></tr><tr><td align="left"><code class="filename">tr1/climits</code></td><td align="left"><code class="filename">tr1/cstdarg</code></td><td align="left"><code class="filename">tr1/cstdbool</code></td><td align="left"><code class="filename">tr1/cstdint</code></td><td align="left"><code class="filename">tr1/cstdio</code></td></tr><tr><td align="left"><code class="filename">tr1/cstdlib</code></td><td align="left"><code class="filename">tr1/ctgmath</code></td><td align="left"><code class="filename">tr1/ctime</code></td><td align="left"><code class="filename">tr1/cwchar</code></td><td align="left"><code class="filename">tr1/cwctype</code></td></tr></tbody></table></div></div><br class="table-break" /><p>Decimal floating-point arithmetic is available if the C++

3366

+</p><div class="table"><a id="idm270002311248"></a><p class="title"><strong>Table 3.6. C++ TR 1 Library Headers</strong></p><div class="table-contents"><table summary="C++ TR 1 Library Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">tr1/array</code></td><td align="left"><code class="filename">tr1/complex</code></td><td align="left"><code class="filename">tr1/memory</code></td><td align="left"><code class="filename">tr1/functional</code></td><td align="left"><code class="filename">tr1/random</code></td></tr><tr><td align="left"><code class="filename">tr1/regex</code></td><td align="left"><code class="filename">tr1/tuple</code></td><td align="left"><code class="filename">tr1/type_traits</code></td><td align="left"><code class="filename">tr1/unordered_map</code></td><td align="left"><code class="filename">tr1/unordered_set</code></td></tr><tr><td align="left"><code class="filename">tr1/utility</code></td><td class="auto-generated"> </td><td class="auto-generated"> </td><td class="auto-generated"> </td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="idm270002294320"></a><p class="title"><strong>Table 3.7. C++ TR 1 Library Headers for C Library Facilities</strong></p><div class="table-contents"><table summary="C++ TR 1 Library Headers for C Library Facilities" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">tr1/ccomplex</code></td><td align="left"><code class="filename">tr1/cfenv</code></td><td align="left"><code class="filename">tr1/cfloat</code></td><td align="left"><code class="filename">tr1/cmath</code></td><td align="left"><code class="filename">tr1/cinttypes</code></td></tr><tr><td align="left"><code class="filename">tr1/climits</code></td><td align="left"><code class="filename">tr1/cstdarg</code></td><td align="left"><code class="filename">tr1/cstdbool</code></td><td align="left"><code class="filename">tr1/cstdint</code></td><td align="left"><code class="filename">tr1/cstdio</code></td></tr><tr><td align="left"><code class="filename">tr1/cstdlib</code></td><td align="left"><code class="filename">tr1/ctgmath</code></td><td align="left"><code class="filename">tr1/ctime</code></td><td align="left"><code class="filename">tr1/cwchar</code></td><td align="left"><code class="filename">tr1/cwctype</code></td></tr></tbody></table></div></div><br class="table-break" /><p>Decimal floating-point arithmetic is available if the C++

3367

compiler supports scalar decimal floating-point types defined via

3368

<code class="code">__attribute__((mode(SD|DD|LD)))</code>.

3369

-</p><div class="table"><a id="idp13259904"></a><p class="title"><strong>Table 3.8. C++ TR 24733 Decimal Floating-Point Header</strong></p><div class="table-contents"><table summary="C++ TR 24733 Decimal Floating-Point Header" border="1"><colgroup><col align="left" class="c1" /></colgroup><tbody><tr><td align="left"><code class="filename">decimal/decimal</code></td></tr></tbody></table></div></div><br class="table-break" /><p>

3370

+</p><div class="table"><a id="idm270002273248"></a><p class="title"><strong>Table 3.8. C++ TR 24733 Decimal Floating-Point Header</strong></p><div class="table-contents"><table summary="C++ TR 24733 Decimal Floating-Point Header" border="1"><colgroup><col align="left" class="c1" /></colgroup><tbody><tr><td align="left"><code class="filename">decimal/decimal</code></td></tr></tbody></table></div></div><br class="table-break" /><p>

3371

Also included are files for the C++ ABI interface:

3372

-</p><div class="table"><a id="idp13265424"></a><p class="title"><strong>Table 3.9. C++ ABI Headers</strong></p><div class="table-contents"><table summary="C++ ABI Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><tbody><tr><td align="left"><code class="filename">cxxabi.h</code></td><td align="left"><code class="filename">cxxabi_forced.h</code></td></tr></tbody></table></div></div><br class="table-break" /><p>

3373

+</p><div class="table"><a id="idm270002267728"></a><p class="title"><strong>Table 3.9. C++ ABI Headers</strong></p><div class="table-contents"><table summary="C++ ABI Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><tbody><tr><td align="left"><code class="filename">cxxabi.h</code></td><td align="left"><code class="filename">cxxabi_forced.h</code></td></tr></tbody></table></div></div><br class="table-break" /><p>

3374

And a large variety of extensions.

3375

-</p><div class="table"><a id="idp13271824"></a><p class="title"><strong>Table 3.10. Extension Headers</strong></p><div class="table-contents"><table summary="Extension Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">ext/algorithm</code></td><td align="left"><code class="filename">ext/atomicity.h</code></td><td align="left"><code class="filename">ext/array_allocator.h</code></td><td align="left"><code class="filename">ext/bitmap_allocator.h</code></td><td align="left"><code class="filename">ext/cast.h</code></td></tr><tr><td align="left"><code class="filename">ext/codecvt_specializations.h</code></td><td align="left"><code class="filename">ext/concurrence.h</code></td><td align="left"><code class="filename">ext/debug_allocator.h</code></td><td align="left"><code class="filename">ext/enc_filebuf.h</code></td><td align="left"><code class="filename">ext/extptr_allocator.h</code></td></tr><tr><td align="left"><code class="filename">ext/functional</code></td><td align="left"><code class="filename">ext/iterator</code></td><td align="left"><code class="filename">ext/malloc_allocator.h</code></td><td align="left"><code class="filename">ext/memory</code></td><td align="left"><code class="filename">ext/mt_allocator.h</code></td></tr><tr><td align="left"><code class="filename">ext/new_allocator.h</code></td><td align="left"><code class="filename">ext/numeric</code></td><td align="left"><code class="filename">ext/numeric_traits.h</code></td><td align="left"><code class="filename">ext/pb_ds/assoc_container.h</code></td><td align="left"><code class="filename">ext/pb_ds/priority_queue.h</code></td></tr><tr><td align="left"><code class="filename">ext/pod_char_traits.h</code></td><td align="left"><code class="filename">ext/pool_allocator.h</code></td><td align="left"><code class="filename">ext/rb_tree</code></td><td align="left"><code class="filename">ext/rope</code></td><td align="left"><code class="filename">ext/slist</code></td></tr><tr><td align="left"><code class="filename">ext/stdio_filebuf.h</code></td><td align="left"><code class="filename">ext/stdio_sync_filebuf.h</code></td><td align="left"><code class="filename">ext/throw_allocator.h</code></td><td align="left"><code class="filename">ext/typelist.h</code></td><td align="left"><code class="filename">ext/type_traits.h</code></td></tr><tr><td align="left"><code class="filename">ext/vstring.h</code></td><td class="auto-generated"> </td><td class="auto-generated"> </td><td class="auto-generated"> </td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="idp13307552"></a><p class="title"><strong>Table 3.11. Extension Debug Headers</strong></p><div class="table-contents"><table summary="Extension Debug Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">debug/bitset</code></td><td align="left"><code class="filename">debug/deque</code></td><td align="left"><code class="filename">debug/list</code></td><td align="left"><code class="filename">debug/map</code></td><td align="left"><code class="filename">debug/set</code></td></tr><tr><td align="left"><code class="filename">debug/string</code></td><td align="left"><code class="filename">debug/unordered_map</code></td><td align="left"><code class="filename">debug/unordered_set</code></td><td align="left"><code class="filename">debug/vector</code></td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="idp13322320"></a><p class="title"><strong>Table 3.12. Extension Profile Headers</strong></p><div class="table-contents"><table summary="Extension Profile Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><tbody><tr><td align="left"><code class="filename">profile/bitset</code></td><td align="left"><code class="filename">profile/deque</code></td><td align="left"><code class="filename">profile/list</code></td><td align="left"><code class="filename">profile/map</code></td></tr><tr><td align="left"><code class="filename">profile/set</code></td><td align="left"><code class="filename">profile/unordered_map</code></td><td align="left"><code class="filename">profile/unordered_set</code></td><td align="left"><code class="filename">profile/vector</code></td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="idp13335696"></a><p class="title"><strong>Table 3.13. Extension Parallel Headers</strong></p><div class="table-contents"><table summary="Extension Parallel Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><tbody><tr><td align="left"><code class="filename">parallel/algorithm</code></td><td align="left"><code class="filename">parallel/numeric</code></td></tr></tbody></table></div></div><br class="table-break" /></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.intro.using.headers.mixing"></a>Mixing Headers</h3></div></div></div><p> A few simple rules.

3376

+</p><div class="table"><a id="idm270002261328"></a><p class="title"><strong>Table 3.10. Extension Headers</strong></p><div class="table-contents"><table summary="Extension Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">ext/algorithm</code></td><td align="left"><code class="filename">ext/atomicity.h</code></td><td align="left"><code class="filename">ext/array_allocator.h</code></td><td align="left"><code class="filename">ext/bitmap_allocator.h</code></td><td align="left"><code class="filename">ext/cast.h</code></td></tr><tr><td align="left"><code class="filename">ext/codecvt_specializations.h</code></td><td align="left"><code class="filename">ext/concurrence.h</code></td><td align="left"><code class="filename">ext/debug_allocator.h</code></td><td align="left"><code class="filename">ext/enc_filebuf.h</code></td><td align="left"><code class="filename">ext/extptr_allocator.h</code></td></tr><tr><td align="left"><code class="filename">ext/functional</code></td><td align="left"><code class="filename">ext/iterator</code></td><td align="left"><code class="filename">ext/malloc_allocator.h</code></td><td align="left"><code class="filename">ext/memory</code></td><td align="left"><code class="filename">ext/mt_allocator.h</code></td></tr><tr><td align="left"><code class="filename">ext/new_allocator.h</code></td><td align="left"><code class="filename">ext/numeric</code></td><td align="left"><code class="filename">ext/numeric_traits.h</code></td><td align="left"><code class="filename">ext/pb_ds/assoc_container.h</code></td><td align="left"><code class="filename">ext/pb_ds/priority_queue.h</code></td></tr><tr><td align="left"><code class="filename">ext/pod_char_traits.h</code></td><td align="left"><code class="filename">ext/pool_allocator.h</code></td><td align="left"><code class="filename">ext/rb_tree</code></td><td align="left"><code class="filename">ext/rope</code></td><td align="left"><code class="filename">ext/slist</code></td></tr><tr><td align="left"><code class="filename">ext/stdio_filebuf.h</code></td><td align="left"><code class="filename">ext/stdio_sync_filebuf.h</code></td><td align="left"><code class="filename">ext/throw_allocator.h</code></td><td align="left"><code class="filename">ext/typelist.h</code></td><td align="left"><code class="filename">ext/type_traits.h</code></td></tr><tr><td align="left"><code class="filename">ext/vstring.h</code></td><td class="auto-generated"> </td><td class="auto-generated"> </td><td class="auto-generated"> </td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="idm270002225600"></a><p class="title"><strong>Table 3.11. Extension Debug Headers</strong></p><div class="table-contents"><table summary="Extension Debug Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">debug/bitset</code></td><td align="left"><code class="filename">debug/deque</code></td><td align="left"><code class="filename">debug/list</code></td><td align="left"><code class="filename">debug/map</code></td><td align="left"><code class="filename">debug/set</code></td></tr><tr><td align="left"><code class="filename">debug/string</code></td><td align="left"><code class="filename">debug/unordered_map</code></td><td align="left"><code class="filename">debug/unordered_set</code></td><td align="left"><code class="filename">debug/vector</code></td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="idm270002210832"></a><p class="title"><strong>Table 3.12. Extension Profile Headers</strong></p><div class="table-contents"><table summary="Extension Profile Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><tbody><tr><td align="left"><code class="filename">profile/bitset</code></td><td align="left"><code class="filename">profile/deque</code></td><td align="left"><code class="filename">profile/list</code></td><td align="left"><code class="filename">profile/map</code></td></tr><tr><td align="left"><code class="filename">profile/set</code></td><td align="left"><code class="filename">profile/unordered_map</code></td><td align="left"><code class="filename">profile/unordered_set</code></td><td align="left"><code class="filename">profile/vector</code></td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="idm270002197456"></a><p class="title"><strong>Table 3.13. Extension Parallel Headers</strong></p><div class="table-contents"><table summary="Extension Parallel Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><tbody><tr><td align="left"><code class="filename">parallel/algorithm</code></td><td align="left"><code class="filename">parallel/numeric</code></td></tr></tbody></table></div></div><br class="table-break" /></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.intro.using.headers.mixing"></a>Mixing Headers</h3></div></div></div><p> A few simple rules.

3377

</p><p>First, mixing different dialects of the standard headers is not

3378

possible. It's an all-or-nothing affair. Thus, code like

3379

</p><pre class="programlisting">

3380

Index: libstdc++-v3/doc/html/manual/using_namespaces.html

3381

===================================================================

3382

--- a/src/libstdc++-v3/doc/html/manual/using_namespaces.html (.../tags/gcc_4_8_2_release)

3383

+++ b/src/libstdc++-v3/doc/html/manual/using_namespaces.html (.../branches/gcc-4_8-branch)

3384

@@ -1,5 +1,5 @@

3385

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

3386

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Namespaces</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_macros.html" title="Macros" /><link rel="next" href="using_dynamic_or_shared.html" title="Linking" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Namespaces</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_macros.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="using_dynamic_or_shared.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.namespaces"></a>Namespaces</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.intro.using.namespaces.all"></a>Available Namespaces</h3></div></div></div><p> There are three main namespaces.

3387

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Namespaces</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_macros.html" title="Macros" /><link rel="next" href="using_dynamic_or_shared.html" title="Linking" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Namespaces</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_macros.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="using_dynamic_or_shared.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.namespaces"></a>Namespaces</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.intro.using.namespaces.all"></a>Available Namespaces</h3></div></div></div><p> There are three main namespaces.

3388

</p><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p>std</p><p>The ISO C++ standards specify that "all library entities are defined

3389

within namespace std." This includes namespaces nested

3390

within <code class="code">namespace std</code>, such as <code class="code">namespace

3391

Index: libstdc++-v3/doc/html/manual/debug.html

3392

===================================================================

3393

--- a/src/libstdc++-v3/doc/html/manual/debug.html (.../tags/gcc_4_8_2_release)

3394

+++ b/src/libstdc++-v3/doc/html/manual/debug.html (.../branches/gcc-4_8-branch)

3395

@@ -1,5 +1,5 @@

3396

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

3397

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Debugging Support</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="C++, debug" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_exceptions.html" title="Exceptions" /><link rel="next" href="std_contents.html" title="Part II. Standard Contents" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Debugging Support</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_exceptions.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="std_contents.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.debug"></a>Debugging Support</h2></div></div></div><p>

3398

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Debugging Support</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, debug" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_exceptions.html" title="Exceptions" /><link rel="next" href="std_contents.html" title="Part II. Standard Contents" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Debugging Support</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_exceptions.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="std_contents.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.debug"></a>Debugging Support</h2></div></div></div><p>

3399

There are numerous things that can be done to improve the ease with

3400

which C++ binaries are debugged when using the GNU tool chain. Here

3401

are some of them.

3402

@@ -161,7 +161,7 @@

3403

DRD</a>,

3404

3405

Helgrind</a>, and

3406

- <a class="link" href="http://code.google.com/p/data-race-test" target="_top">

3407

+ <a class="link" href="http://code.google.com/p/data-race-test/" target="_top">

3408

ThreadSanitizer</a>.

3409

</p><p>

3410

With DRD, Helgrind and ThreadSanitizer you will need to define

3411

Index: libstdc++-v3/doc/html/manual/localization.html

3412

===================================================================

3413

--- a/src/libstdc++-v3/doc/html/manual/localization.html (.../tags/gcc_4_8_2_release)

3414

+++ b/src/libstdc++-v3/doc/html/manual/localization.html (.../branches/gcc-4_8-branch)

3415

@@ -1,5 +1,5 @@

3416

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

3417

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 8. Localization</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II. Standard Contents" /><link rel="prev" href="strings.html" title="Chapter 7. Strings" /><link rel="next" href="facets.html" title="Facets" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 8.

3418

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 8. Localization</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II. Standard Contents" /><link rel="prev" href="strings.html" title="Chapter 7. Strings" /><link rel="next" href="facets.html" title="Facets" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 8.

3419

Localization

3420

3421

</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="strings.html">Prev</a> </td><th width="60%" align="center">Part II.

3422

@@ -6,8 +6,8 @@

3423

Standard Contents

3424

</th><td width="20%" align="right"> <a accesskey="n" href="facets.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="std.localization"></a>Chapter 8.

3425

Localization

3426

- <a id="idp15701088" class="indexterm"></a>

3427

-</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="localization.html#std.localization.locales">Locales</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#std.localization.locales.locale">locale</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#locales.locale.req">Requirements</a></span></dt><dt><span class="section"><a href="localization.html#locales.locale.design">Design</a></span></dt><dt><span class="section"><a href="localization.html#locales.locale.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#locale.impl.c">Interacting with "C" locales</a></span></dt></dl></dd><dt><span class="section"><a href="localization.html#locales.locale.future">Future</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="facets.html">Facets</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#std.localization.facet.ctype">ctype</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.ctype.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#idp15778336">Specializations</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.ctype.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#std.localization.facet.codecvt">codecvt</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.codecvt.req">Requirements</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.design">Design</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#codecvt.design.wchar_t_size"><span class="type">wchar_t</span> Size</a></span></dt><dt><span class="section"><a href="facets.html#codecvt.design.unicode">Support for Unicode</a></span></dt><dt><span class="section"><a href="facets.html#codecvt.design.issues">Other Issues</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.codecvt.impl">Implementation</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.use">Use</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#manual.localization.facet.messages">messages</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.messages.req">Requirements</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.design">Design</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#messages.impl.models">Models</a></span></dt><dt><span class="section"><a href="facets.html#messages.impl.gnu">The GNU Model</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.messages.use">Use</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.future">Future</a></span></dt></dl></dd></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.localization.locales"></a>Locales</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="std.localization.locales.locale"></a>locale</h3></div></div></div><p>

3428

+ <a id="idm269999830208" class="indexterm"></a>

3429

+</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="localization.html#std.localization.locales">Locales</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#std.localization.locales.locale">locale</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#locales.locale.req">Requirements</a></span></dt><dt><span class="section"><a href="localization.html#locales.locale.design">Design</a></span></dt><dt><span class="section"><a href="localization.html#locales.locale.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#locale.impl.c">Interacting with "C" locales</a></span></dt></dl></dd><dt><span class="section"><a href="localization.html#locales.locale.future">Future</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="facets.html">Facets</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#std.localization.facet.ctype">ctype</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.ctype.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#idm269999753024">Specializations</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.ctype.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#std.localization.facet.codecvt">codecvt</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.codecvt.req">Requirements</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.design">Design</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#codecvt.design.wchar_t_size"><span class="type">wchar_t</span> Size</a></span></dt><dt><span class="section"><a href="facets.html#codecvt.design.unicode">Support for Unicode</a></span></dt><dt><span class="section"><a href="facets.html#codecvt.design.issues">Other Issues</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.codecvt.impl">Implementation</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.use">Use</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#manual.localization.facet.messages">messages</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.messages.req">Requirements</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.design">Design</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#messages.impl.models">Models</a></span></dt><dt><span class="section"><a href="facets.html#messages.impl.gnu">The GNU Model</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.messages.use">Use</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.future">Future</a></span></dt></dl></dd></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.localization.locales"></a>Locales</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="std.localization.locales.locale"></a>locale</h3></div></div></div><p>

3430

Describes the basic locale object, including nested

3431

classes id, facet, and the reference-counted implementation object,

3432

class _Impl.

3433

@@ -402,18 +402,18 @@

3434

What should non-required facet instantiations do? If the

3435

generic implementation is provided, then how to end-users

3436

provide specializations?

3437

- </p></li></ul></div></div><div class="bibliography"><div class="titlepage"><div><div><h4 class="title"><a id="locales.locale.biblio"></a>Bibliography</h4></div></div></div><div class="biblioentry"><a id="idp15744064"></a><p><span class="citetitle"><em class="citetitle">

3438

+ </p></li></ul></div></div><div class="bibliography"><div class="titlepage"><div><div><h4 class="title"><a id="locales.locale.biblio"></a>Bibliography</h4></div></div></div><div class="biblioentry"><a id="idm269999787232"></a><p><span class="citetitle"><em class="citetitle">

3439

The GNU C Library

3440

</em>. </span><span class="author"><span class="firstname">Roland</span> <span class="surname">McGrath</span>. </span><span class="author"><span class="firstname">Ulrich</span> <span class="surname">Drepper</span>. </span><span class="copyright">Copyright © 2007 FSF. </span><span class="pagenums">

3441

Chapters 6 Character Set Handling and 7 Locales and

3442

Internationalization

3443

- . </span></p></div><div class="biblioentry"><a id="idp15748832"></a><p><span class="citetitle"><em class="citetitle">

3444

+ . </span></p></div><div class="biblioentry"><a id="idm269999782464"></a><p><span class="citetitle"><em class="citetitle">

3445

Correspondence

3446

- </em>. </span><span class="author"><span class="firstname">Ulrich</span> <span class="surname">Drepper</span>. </span><span class="copyright">Copyright © 2002 . </span></p></div><div class="biblioentry"><a id="idp15751920"></a><p><span class="citetitle"><em class="citetitle">

3447

+ </em>. </span><span class="author"><span class="firstname">Ulrich</span> <span class="surname">Drepper</span>. </span><span class="copyright">Copyright © 2002 . </span></p></div><div class="biblioentry"><a id="idm269999779376"></a><p><span class="citetitle"><em class="citetitle">

3448

ISO/IEC 14882:1998 Programming languages - C++

3449

3450

3451

ISO/IEC 9899:1999 Programming languages - C

3452

3453

3454

3455

System Interface Definitions, Issue 7 (IEEE Std. 1003.1-2008)

3456

</a>

3457

@@ -420,11 +420,11 @@

3458

3459

The Open Group/The Institute of Electrical and Electronics

3460

Engineers, Inc.

3461

- . </span></p></div><div class="biblioentry"><a id="idp15759712"></a><p><span class="citetitle"><em class="citetitle">

3462

+ . </span></p></div><div class="biblioentry"><a id="idm269999771584"></a><p><span class="citetitle"><em class="citetitle">

3463

The C++ Programming Language, Special Edition

3464

</em>. </span><span class="author"><span class="firstname">Bjarne</span> <span class="surname">Stroustrup</span>. </span><span class="copyright">Copyright © 2000 Addison Wesley, Inc.. </span><span class="pagenums">Appendix D. </span><span class="publisher"><span class="publishername">

3465

Addison Wesley

3466

- . </span></span></p></div><div class="biblioentry"><a id="idp15764336"></a><p><span class="citetitle"><em class="citetitle">

3467

+ . </span></span></p></div><div class="biblioentry"><a id="idm269999766960"></a><p><span class="citetitle"><em class="citetitle">

3468

Standard C++ IOStreams and Locales

3469

</em>. </span><span class="subtitle">

3470

Advanced Programmer's Guide and Reference

3471

Index: libstdc++-v3/doc/html/manual/ext_algorithms.html

3472

===================================================================

3473

--- a/src/libstdc++-v3/doc/html/manual/ext_algorithms.html (.../tags/gcc_4_8_2_release)

3474

+++ b/src/libstdc++-v3/doc/html/manual/ext_algorithms.html (.../branches/gcc-4_8-branch)

3475

@@ -1,5 +1,5 @@

3476

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

3477

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 25. Algorithms</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III. Extensions" /><link rel="prev" href="ext_utilities.html" title="Chapter 24. Utilities" /><link rel="next" href="ext_numerics.html" title="Chapter 26. Numerics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 25. Algorithms</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_utilities.html">Prev</a> </td><th width="60%" align="center">Part III.

3478

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 25. Algorithms</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III. Extensions" /><link rel="prev" href="ext_utilities.html" title="Chapter 24. Utilities" /><link rel="next" href="ext_numerics.html" title="Chapter 26. Numerics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 25. Algorithms</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_utilities.html">Prev</a> </td><th width="60%" align="center">Part III.

3479

Extensions

3480

3481

</th><td width="20%" align="right"> <a accesskey="n" href="ext_numerics.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.algorithms"></a>Chapter 25. Algorithms</h2></div></div></div><p>25.1.6 (count, count_if) is extended with two more versions of count

3482

Index: libstdc++-v3/doc/html/manual/debug_mode.html

3483

===================================================================

3484

--- a/src/libstdc++-v3/doc/html/manual/debug_mode.html (.../tags/gcc_4_8_2_release)

3485

+++ b/src/libstdc++-v3/doc/html/manual/debug_mode.html (.../branches/gcc-4_8-branch)

3486

@@ -1,8 +1,8 @@

3487

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

3488

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 17. Debug Mode</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="C++, library, debug" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III. Extensions" /><link rel="prev" href="ext_compile_checks.html" title="Chapter 16. Compile Time Checks" /><link rel="next" href="debug_mode_semantics.html" title="Semantics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 17. Debug Mode</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_compile_checks.html">Prev</a> </td><th width="60%" align="center">Part III.

3489

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 17. Debug Mode</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, debug" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III. Extensions" /><link rel="prev" href="ext_compile_checks.html" title="Chapter 16. Compile Time Checks" /><link rel="next" href="debug_mode_semantics.html" title="Semantics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 17. Debug Mode</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_compile_checks.html">Prev</a> </td><th width="60%" align="center">Part III.

3490

Extensions

3491

3492

-</th><td width="20%" align="right"> <a accesskey="n" href="debug_mode_semantics.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.debug_mode"></a>Chapter 17. Debug Mode</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="debug_mode.html#manual.ext.debug_mode.intro">Intro</a></span></dt><dt><span class="section"><a href="debug_mode_semantics.html">Semantics</a></span></dt><dt><span class="section"><a href="debug_mode_using.html">Using</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_using.html#debug_mode.using.mode">Using the Debug Mode</a></span></dt><dt><span class="section"><a href="debug_mode_using.html#debug_mode.using.specific">Using a Specific Debug Container</a></span></dt></dl></dd><dt><span class="section"><a href="debug_mode_design.html">Design</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.goals">Goals</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods">Methods</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.wrappers">The Wrapper Model</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.safe_iter">Safe Iterators</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.safe_seq">Safe Sequences (Containers)</a></span></dt></dl></dd><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.precond">Precondition Checking</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.coexistence">Release- and debug-mode coexistence</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#methods.coexistence.compile">Compile-time coexistence of release- and debug-mode components</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#methods.coexistence.link">Link- and run-time coexistence of release- and

3493

+</th><td width="20%" align="right"> <a accesskey="n" href="debug_mode_semantics.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.debug_mode"></a>Chapter 17. Debug Mode</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="debug_mode.html#manual.ext.debug_mode.intro">Intro</a></span></dt><dt><span class="section"><a href="debug_mode_semantics.html">Semantics</a></span></dt><dt><span class="section"><a href="debug_mode_using.html">Using</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_using.html#debug_mode.using.mode">Using the Debug Mode</a></span></dt><dt><span class="section"><a href="debug_mode_using.html#debug_mode.using.specific">Using a Specific Debug Container</a></span></dt></dl></dd><dt><span class="section"><a href="debug_mode_design.html">Design</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.goals">Goals</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods">Methods</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.wrappers">The Wrapper Model</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.safe_iter">Safe Iterators</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.safe_seq">Safe Sequences (Containers)</a></span></dt></dl></dd><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.precond">Precondition Checking</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.coexistence">Release- and debug-mode coexistence</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#methods.coexistence.compile">Compile-time coexistence of release- and debug-mode components</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#methods.coexistence.link">Link- and run-time coexistence of release- and

3494

debug-mode components</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#methods.coexistence.alt">Alternatives for Coexistence</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.other">Other Implementations</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.debug_mode.intro"></a>Intro</h2></div></div></div><p>

3495

By default, libstdc++ is built with efficiency in mind, and

3496

therefore performs little or no error checking that is not

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3499

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3500

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3501

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3502

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

3503

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="prev" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="next" href="profile_mode_api.html" title="Extensions for Custom Containers" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="profile_mode.html">Prev</a> </td><th width="60%" align="center">Chapter 19. Profile Mode</th><td width="20%" align="right"> <a accesskey="n" href="profile_mode_api.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.design"></a>Design</h2></div></div></div><p>

3504

-</p><div class="table"><a id="idp16981200"></a><p class="title"><strong>Table 19.1. Profile Code Location</strong></p><div class="table-contents"><table summary="Profile Code Location" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><thead><tr><th align="left">Code Location</th><th align="left">Use</th></tr></thead><tbody><tr><td align="left"><code class="code">libstdc++-v3/include/std/*</code></td><td align="left">Preprocessor code to redirect to profile extension headers.</td></tr><tr><td align="left"><code class="code">libstdc++-v3/include/profile/*</code></td><td align="left">Profile extension public headers (map, vector, ...).</td></tr><tr><td align="left"><code class="code">libstdc++-v3/include/profile/impl/*</code></td><td align="left">Profile extension internals. Implementation files are

3505

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="prev" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="next" href="profile_mode_api.html" title="Extensions for Custom Containers" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="profile_mode.html">Prev</a> </td><th width="60%" align="center">Chapter 19. Profile Mode</th><td width="20%" align="right"> <a accesskey="n" href="profile_mode_api.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.design"></a>Design</h2></div></div></div><p>

3506

+</p><div class="table"><a id="idm269998550064"></a><p class="title"><strong>Table 19.1. Profile Code Location</strong></p><div class="table-contents"><table summary="Profile Code Location" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><thead><tr><th align="left">Code Location</th><th align="left">Use</th></tr></thead><tbody><tr><td align="left"><code class="code">libstdc++-v3/include/std/*</code></td><td align="left">Preprocessor code to redirect to profile extension headers.</td></tr><tr><td align="left"><code class="code">libstdc++-v3/include/profile/*</code></td><td align="left">Profile extension public headers (map, vector, ...).</td></tr><tr><td align="left"><code class="code">libstdc++-v3/include/profile/impl/*</code></td><td align="left">Profile extension internals. Implementation files are

3507

only included from <code class="code">impl/profiler.h</code>, which is the only

3508

file included from the public headers.</td></tr></tbody></table></div></div><br class="table-break" /><p>

3509

</p><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.ext.profile_mode.design.wrapper"></a>Wrapper Model</h3></div></div></div><p>

3510

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3511

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3512

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3513

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3514

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3515

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

3516

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Concurrency</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_dynamic_or_shared.html" title="Linking" /><link rel="next" href="using_exceptions.html" title="Exceptions" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Concurrency</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_dynamic_or_shared.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="using_exceptions.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.concurrency"></a>Concurrency</h2></div></div></div><p>This section discusses issues surrounding the proper compilation

3517

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Concurrency</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_dynamic_or_shared.html" title="Linking" /><link rel="next" href="using_exceptions.html" title="Exceptions" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Concurrency</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_dynamic_or_shared.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="using_exceptions.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.concurrency"></a>Concurrency</h2></div></div></div><p>This section discusses issues surrounding the proper compilation

3518

of multithreaded applications which use the Standard C++

3519

library. This information is GCC-specific since the C++

3520

standard does not address matters of multithreaded applications.

3521

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3522

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3523

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3526

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-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Implementation</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, allocator" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="mt_allocator.html" title="Chapter 20. The mt_allocator" /><link rel="prev" href="mt_allocator_design.html" title="Design Issues" /><link rel="next" href="mt_allocator_ex_single.html" title="Single Thread Example" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Implementation</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="mt_allocator_design.html">Prev</a> </td><th width="60%" align="center">Chapter 20. The mt_allocator</th><td width="20%" align="right"> <a accesskey="n" href="mt_allocator_ex_single.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="allocator.mt.impl"></a>Implementation</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="allocator.mt.tune"></a>Tunable Parameters</h3></div></div></div><p>Certain allocation parameters can be modified, or tuned. There

3528

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Implementation</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, allocator" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="mt_allocator.html" title="Chapter 20. The mt_allocator" /><link rel="prev" href="mt_allocator_design.html" title="Design Issues" /><link rel="next" href="mt_allocator_ex_single.html" title="Single Thread Example" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Implementation</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="mt_allocator_design.html">Prev</a> </td><th width="60%" align="center">Chapter 20. The mt_allocator</th><td width="20%" align="right"> <a accesskey="n" href="mt_allocator_ex_single.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="allocator.mt.impl"></a>Implementation</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="allocator.mt.tune"></a>Tunable Parameters</h3></div></div></div><p>Certain allocation parameters can be modified, or tuned. There

3529

exists a nested <code class="code">struct __pool_base::_Tune</code> that contains all

3530

these parameters, which include settings for

3531

</p><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p>Alignment</p></li><li class="listitem"><p>Maximum bytes before calling <code class="code">::operator new</code> directly</p></li><li class="listitem"><p>Minimum bytes</p></li><li class="listitem"><p>Size of underlying global allocations</p></li><li class="listitem"><p>Maximum number of supported threads</p></li><li class="listitem"><p>Migration of deallocations to the global free list</p></li><li class="listitem"><p>Shunt for global <code class="code">new</code> and <code class="code">delete</code></p></li></ul></div><p>Adjusting parameters for a given instance of an allocator can only

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>

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-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Appendix E. GNU Free Documentation License</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix.html" title="Part IV. Appendices" /><link rel="prev" href="appendix_gpl.html" title="Appendix D. GNU General Public License version 3" /><link rel="next" href="../bk02.html" title="" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Appendix E. GNU Free Documentation License</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="appendix_gpl.html">Prev</a> </td><th width="60%" align="center">Part IV.

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Appendix E. GNU Free Documentation License</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix.html" title="Part IV. Appendices" /><link rel="prev" href="appendix_gpl.html" title="Appendix D. GNU General Public License version 3" /><link rel="next" href="../bk02.html" title="" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Appendix E. GNU Free Documentation License</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="appendix_gpl.html">Prev</a> </td><th width="60%" align="center">Part IV.

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Appendices

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</th><td width="20%" align="right"> <a accesskey="n" href="../bk02.html">Next</a></td></tr></table><hr /></div><div class="appendix"><div class="titlepage"><div><div><h1 class="title"><a id="appendix.gfdl-1.3"></a>GNU Free Documentation License</h1></div></div></div><p>Version 1.3, 3 November 2008</p><p>

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3545

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 9. Containers</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II. Standard Contents" /><link rel="prev" href="facets.html" title="Facets" /><link rel="next" href="associative.html" title="Associative" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 9.

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Containers

3552

3553

</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="facets.html">Prev</a> </td><th width="60%" align="center">Part II.

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Standard Contents

3556

</th><td width="20%" align="right"> <a accesskey="n" href="associative.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="std.containers"></a>Chapter 9.

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Containers

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- <a id="idp16037808" class="indexterm"></a>

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-</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="containers.html#std.containers.sequences">Sequences</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#containers.sequences.list">list</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#sequences.list.size">list::size() is O(n)</a></span></dt></dl></dd><dt><span class="section"><a href="containers.html#containers.sequences.vector">vector</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#sequences.vector.management">Space Overhead Management</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="associative.html">Associative</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#containers.associative.insert_hints">Insertion Hints</a></span></dt><dt><span class="section"><a href="associative.html#containers.associative.bitset">bitset</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#associative.bitset.size_variable">Size Variable</a></span></dt><dt><span class="section"><a href="associative.html#associative.bitset.type_string">Type String</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="unordered_associative.html">Unordered Associative</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.hash">Hash Code</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.cache">Hash Code Caching Policy</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="containers_and_c.html">Interacting with C</a></span></dt><dd><dl><dt><span class="section"><a href="containers_and_c.html#containers.c.vs_array">Containers vs. Arrays</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.containers.sequences"></a>Sequences</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="containers.sequences.list"></a>list</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="sequences.list.size"></a>list::size() is O(n)</h4></div></div></div><p>

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+ <a id="idm269999493408" class="indexterm"></a>

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+</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="containers.html#std.containers.sequences">Sequences</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#containers.sequences.list">list</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#sequences.list.size">list::size() is O(n)</a></span></dt></dl></dd><dt><span class="section"><a href="containers.html#containers.sequences.vector">vector</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#sequences.vector.management">Space Overhead Management</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="associative.html">Associative</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#containers.associative.insert_hints">Insertion Hints</a></span></dt><dt><span class="section"><a href="associative.html#containers.associative.bitset">bitset</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#associative.bitset.size_variable">Size Variable</a></span></dt><dt><span class="section"><a href="associative.html#associative.bitset.type_string">Type String</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="unordered_associative.html">Unordered Associative</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.hash">Hash Code</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.cache">Hash Code Caching Policy</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="containers_and_c.html">Interacting with C</a></span></dt><dd><dl><dt><span class="section"><a href="containers_and_c.html#containers.c.vs_array">Containers vs. Arrays</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.containers.sequences"></a>Sequences</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="containers.sequences.list"></a>list</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="sequences.list.size"></a>list::size() is O(n)</h4></div></div></div><p>

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Yes it is, and that's okay. This is a decision that we preserved

3563

when we imported SGI's STL implementation. The following is

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quoted from <a class="link" href="http://www.sgi.com/tech/stl/FAQ.html" target="_top">their FAQ</a>:

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Index: libstdc++-v3/doc/html/manual/io.html

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>

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-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 13. Input and Output</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II. Standard Contents" /><link rel="prev" href="numerics_and_c.html" title="Interacting with C" /><link rel="next" href="streambufs.html" title="Stream Buffers" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 13.

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 13. Input and Output</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II. Standard Contents" /><link rel="prev" href="numerics_and_c.html" title="Interacting with C" /><link rel="next" href="streambufs.html" title="Stream Buffers" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 13.

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Input and Output

3574

3575

</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="numerics_and_c.html">Prev</a> </td><th width="60%" align="center">Part II.

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@@ -6,8 +6,8 @@

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Standard Contents

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</th><td width="20%" align="right"> <a accesskey="n" href="streambufs.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="std.io"></a>Chapter 13.

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Input and Output

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- <a id="idp16257600" class="indexterm"></a>

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-</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="io.html#std.io.objects">Iostream Objects</a></span></dt><dt><span class="section"><a href="streambufs.html">Stream Buffers</a></span></dt><dd><dl><dt><span class="section"><a href="streambufs.html#io.streambuf.derived">Derived streambuf Classes</a></span></dt><dt><span class="section"><a href="streambufs.html#io.streambuf.buffering">Buffering</a></span></dt></dl></dd><dt><span class="section"><a href="stringstreams.html">Memory Based Streams</a></span></dt><dd><dl><dt><span class="section"><a href="stringstreams.html#std.io.memstreams.compat">Compatibility With strstream</a></span></dt></dl></dd><dt><span class="section"><a href="fstreams.html">File Based Streams</a></span></dt><dd><dl><dt><span class="section"><a href="fstreams.html#std.io.filestreams.copying_a_file">Copying a File</a></span></dt><dt><span class="section"><a href="fstreams.html#std.io.filestreams.binary">Binary Input and Output</a></span></dt></dl></dd><dt><span class="section"><a href="io_and_c.html">Interacting with C</a></span></dt><dd><dl><dt><span class="section"><a href="io_and_c.html#std.io.c.FILE">Using FILE* and file descriptors</a></span></dt><dt><span class="section"><a href="io_and_c.html#std.io.c.sync">Performance</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.io.objects"></a>Iostream Objects</h2></div></div></div><p>To minimize the time you have to wait on the compiler, it's good to

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+ <a id="idm269999273616" class="indexterm"></a>

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+</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="io.html#std.io.objects">Iostream Objects</a></span></dt><dt><span class="section"><a href="streambufs.html">Stream Buffers</a></span></dt><dd><dl><dt><span class="section"><a href="streambufs.html#io.streambuf.derived">Derived streambuf Classes</a></span></dt><dt><span class="section"><a href="streambufs.html#io.streambuf.buffering">Buffering</a></span></dt></dl></dd><dt><span class="section"><a href="stringstreams.html">Memory Based Streams</a></span></dt><dd><dl><dt><span class="section"><a href="stringstreams.html#std.io.memstreams.compat">Compatibility With strstream</a></span></dt></dl></dd><dt><span class="section"><a href="fstreams.html">File Based Streams</a></span></dt><dd><dl><dt><span class="section"><a href="fstreams.html#std.io.filestreams.copying_a_file">Copying a File</a></span></dt><dt><span class="section"><a href="fstreams.html#std.io.filestreams.binary">Binary Input and Output</a></span></dt></dl></dd><dt><span class="section"><a href="io_and_c.html">Interacting with C</a></span></dt><dd><dl><dt><span class="section"><a href="io_and_c.html#std.io.c.FILE">Using FILE* and file descriptors</a></span></dt><dt><span class="section"><a href="io_and_c.html#std.io.c.sync">Performance</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.io.objects"></a>Iostream Objects</h2></div></div></div><p>To minimize the time you have to wait on the compiler, it's good to

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only include the headers you really need. Many people simply include

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<iostream> when they don't need to -- and that can <span class="emphasis"><em>penalize

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your runtime as well.</em></span> Here are some tips on which header to use

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Index: libstdc++-v3/doc/html/manual/index.html

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===================================================================

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>

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-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>The GNU C++ Library Manual</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="../index.html" title="The GNU C++ Library" /><link rel="prev" href="../index.html" title="The GNU C++ Library" /><link rel="next" href="intro.html" title="Part I. Introduction" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">The GNU C++ Library Manual</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="../index.html">Prev</a> </td><th width="60%" align="center"> </th><td width="20%" align="right"> <a accesskey="n" href="intro.html">Next</a></td></tr></table><hr /></div><div class="book"><div class="titlepage"><div><div><h1 class="title"><a id="manual"></a>The GNU C++ Library Manual</h1></div><div><div class="authorgroup"><div class="author"><h3 class="author"><span class="firstname"></span> <span class="surname"></span></h3></div><div class="author"><h3 class="author"><span class="firstname">Paolo</span> <span class="surname">Carlini</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Phil</span> <span class="surname">Edwards</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Doug</span> <span class="surname">Gregor</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Benjamin</span> <span class="surname">Kosnik</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Dhruv</span> <span class="surname">Matani</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Jason</span> <span class="surname">Merrill</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Mark</span> <span class="surname">Mitchell</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Nathan</span> <span class="surname">Myers</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Felix</span> <span class="surname">Natter</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Stefan</span> <span class="surname">Olsson</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Silvius</span> <span class="surname">Rus</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Johannes</span> <span class="surname">Singler</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Ami</span> <span class="surname">Tavory</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Jonathan</span> <span class="surname">Wakely</span></h3></div></div></div><div><p class="copyright">Copyright © 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>The GNU C++ Library Manual</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="../index.html" title="The GNU C++ Library" /><link rel="prev" href="../index.html" title="The GNU C++ Library" /><link rel="next" href="intro.html" title="Part I. Introduction" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">The GNU C++ Library Manual</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="../index.html">Prev</a> </td><th width="60%" align="center"> </th><td width="20%" align="right"> <a accesskey="n" href="intro.html">Next</a></td></tr></table><hr /></div><div class="book"><div class="titlepage"><div><div><h1 class="title"><a id="manual"></a>The GNU C++ Library Manual</h1></div><div><div class="authorgroup"><div class="author"><h3 class="author"><span class="firstname"></span> <span class="surname"></span></h3></div><div class="author"><h3 class="author"><span class="firstname">Paolo</span> <span class="surname">Carlini</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Phil</span> <span class="surname">Edwards</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Doug</span> <span class="surname">Gregor</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Benjamin</span> <span class="surname">Kosnik</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Dhruv</span> <span class="surname">Matani</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Jason</span> <span class="surname">Merrill</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Mark</span> <span class="surname">Mitchell</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Nathan</span> <span class="surname">Myers</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Felix</span> <span class="surname">Natter</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Stefan</span> <span class="surname">Olsson</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Silvius</span> <span class="surname">Rus</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Johannes</span> <span class="surname">Singler</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Ami</span> <span class="surname">Tavory</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Jonathan</span> <span class="surname">Wakely</span></h3></div></div></div><div><p class="copyright">Copyright © 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013

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- </p></div></div><hr /></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="part"><a href="intro.html">I.

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+ </p></div></div><hr /></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="part"><a href="intro.html">I.

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Introduction

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</a></span></dt><dd><dl><dt><span class="chapter"><a href="status.html">1. Status</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#manual.intro.status.iso">Implementation Status</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#status.iso.1998">C++ 1998/2003</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.1998.status">Implementation Status</a></span></dt><dt><span class="section"><a href="status.html#iso.1998.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.2011">C++ 2011</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.2011.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.tr1">C++ TR1</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.tr1.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.tr24733">C++ TR 24733</a></span></dt></dl></dd><dt><span class="section"><a href="license.html">License</a></span></dt><dd><dl><dt><span class="section"><a href="license.html#manual.intro.status.license.gpl">The Code: GPL</a></span></dt><dt><span class="section"><a href="license.html#manual.intro.status.license.fdl">The Documentation: GPL, FDL</a></span></dt></dl></dd><dt><span class="section"><a href="bugs.html">Bugs</a></span></dt><dd><dl><dt><span class="section"><a href="bugs.html#manual.intro.status.bugs.impl">Implementation Bugs</a></span></dt><dt><span class="section"><a href="bugs.html#manual.intro.status.bugs.iso">Standard Bugs</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="setup.html">2. Setup</a></span></dt><dd><dl><dt><span class="section"><a href="setup.html#manual.intro.setup.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="configure.html">Configure</a></span></dt><dt><span class="section"><a href="make.html">Make</a></span></dt></dl></dd><dt><span class="chapter"><a href="using.html">3. Using</a></span></dt><dd><dl><dt><span class="section"><a href="using.html#manual.intro.using.flags">Command Options</a></span></dt><dt><span class="section"><a href="using_headers.html">Headers</a></span></dt><dd><dl><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.all">Header Files</a></span></dt><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.mixing">Mixing Headers</a></span></dt><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.cheaders">The C Headers and <code class="code">namespace std</code></a></span></dt><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.pre">Precompiled Headers</a></span></dt></dl></dd><dt><span class="section"><a href="using_macros.html">Macros</a></span></dt><dt><span class="section"><a href="using_namespaces.html">Namespaces</a></span></dt><dd><dl><dt><span class="section"><a href="using_namespaces.html#manual.intro.using.namespaces.all">Available Namespaces</a></span></dt><dt><span class="section"><a href="using_namespaces.html#manual.intro.using.namespaces.std">namespace std</a></span></dt><dt><span class="section"><a href="using_namespaces.html#manual.intro.using.namespaces.comp">Using Namespace Composition</a></span></dt></dl></dd><dt><span class="section"><a href="using_dynamic_or_shared.html">Linking</a></span></dt><dd><dl><dt><span class="section"><a href="using_dynamic_or_shared.html#manual.intro.using.linkage.freestanding">Almost Nothing</a></span></dt><dt><span class="section"><a href="using_dynamic_or_shared.html#manual.intro.using.linkage.dynamic">Finding Dynamic or Shared Libraries</a></span></dt></dl></dd><dt><span class="section"><a href="using_concurrency.html">Concurrency</a></span></dt><dd><dl><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.thread_safety">Thread Safety</a></span></dt><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.atomics">Atomics</a></span></dt><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.io">IO</a></span></dt><dd><dl><dt><span class="section"><a href="using_concurrency.html#concurrency.io.structure">Structure</a></span></dt><dt><span class="section"><a href="using_concurrency.html#concurrency.io.defaults">Defaults</a></span></dt><dt><span class="section"><a href="using_concurrency.html#concurrency.io.future">Future</a></span></dt><dt><span class="section"><a href="using_concurrency.html#concurrency.io.alt">Alternatives</a></span></dt></dl></dd><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.containers">Containers</a></span></dt></dl></dd><dt><span class="section"><a href="using_exceptions.html">Exceptions</a></span></dt><dd><dl><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.safety">Exception Safety</a></span></dt><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.propagating">Exception Neutrality</a></span></dt><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.no">Doing without</a></span></dt><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.compat">Compatibility</a></span></dt><dd><dl><dt><span class="section"><a href="using_exceptions.html#using.exception.compat.c">With <code class="literal">C</code></a></span></dt><dt><span class="section"><a href="using_exceptions.html#using.exception.compat.posix">With <code class="literal">POSIX</code> thread cancellation</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="debug.html">Debugging Support</a></span></dt><dd><dl><dt><span class="section"><a href="debug.html#debug.compiler">Using <span class="command"><strong>g++</strong></span></a></span></dt><dt><span class="section"><a href="debug.html#debug.req">Debug Versions of Library Binary Files</a></span></dt><dt><span class="section"><a href="debug.html#debug.memory">Memory Leak Hunting</a></span></dt><dt><span class="section"><a href="debug.html#debug.races">Data Race Hunting</a></span></dt><dt><span class="section"><a href="debug.html#debug.gdb">Using <span class="command"><strong>gdb</strong></span></a></span></dt><dt><span class="section"><a href="debug.html#debug.exceptions">Tracking uncaught exceptions</a></span></dt><dt><span class="section"><a href="debug.html#debug.debug_mode">Debug Mode</a></span></dt><dt><span class="section"><a href="debug.html#debug.compile_time_checks">Compile Time Checking</a></span></dt><dt><span class="section"><a href="debug.html#debug.profile_mode">Profile-based Performance Analysis</a></span></dt></dl></dd></dl></dd></dl></dd><dt><span class="part"><a href="std_contents.html">II.

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</a></span></dt><dd><dl><dt><span class="section"><a href="diagnostics.html#std.diagnostics.exceptions">Exceptions</a></span></dt><dd><dl><dt><span class="section"><a href="diagnostics.html#std.diagnostics.exceptions.api">API Reference</a></span></dt><dt><span class="section"><a href="diagnostics.html#std.diagnostics.exceptions.data">Adding Data to <code class="classname">exception</code></a></span></dt></dl></dd><dt><span class="section"><a href="concept_checking.html">Concept Checking</a></span></dt></dl></dd><dt><span class="chapter"><a href="utilities.html">6.

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Utilities

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-</a></span></dt><dd><dl><dt><span class="section"><a href="utilities.html#std.util.functors">Functors</a></span></dt><dt><span class="section"><a href="pairs.html">Pairs</a></span></dt><dt><span class="section"><a href="memory.html">Memory</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#std.util.memory.allocator">Allocators</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#allocator.req">Requirements</a></span></dt><dt><span class="section"><a href="memory.html#allocator.design_issues">Design Issues</a></span></dt><dt><span class="section"><a href="memory.html#allocator.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idp13920976">Interface Design</a></span></dt><dt><span class="section"><a href="memory.html#idp13924528">Selecting Default Allocation Policy</a></span></dt><dt><span class="section"><a href="memory.html#idp13937824">Disabling Memory Caching</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#allocator.using">Using a Specific Allocator</a></span></dt><dt><span class="section"><a href="memory.html#allocator.custom">Custom Allocators</a></span></dt><dt><span class="section"><a href="memory.html#allocator.ext">Extension Allocators</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#std.util.memory.auto_ptr">auto_ptr</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#auto_ptr.limitations">Limitations</a></span></dt><dt><span class="section"><a href="memory.html#auto_ptr.using">Use in Containers</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#std.util.memory.shared_ptr">shared_ptr</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#shared_ptr.req">Requirements</a></span></dt><dt><span class="section"><a href="memory.html#shared_ptr.design_issues">Design Issues</a></span></dt><dt><span class="section"><a href="memory.html#shared_ptr.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idp15512272">Class Hierarchy</a></span></dt><dt><span class="section"><a href="memory.html#idp15534784">Thread Safety</a></span></dt><dt><span class="section"><a href="memory.html#idp15542080">Selecting Lock Policy</a></span></dt><dt><span class="section"><a href="memory.html#idp15556704">Related functions and classes</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#shared_ptr.using">Use</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idp15573056">Examples</a></span></dt><dt><span class="section"><a href="memory.html#idp15576640">Unresolved Issues</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#shared_ptr.ack">Acknowledgments</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="traits.html">Traits</a></span></dt></dl></dd><dt><span class="chapter"><a href="strings.html">7.

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+</a></span></dt><dd><dl><dt><span class="section"><a href="utilities.html#std.util.functors">Functors</a></span></dt><dt><span class="section"><a href="pairs.html">Pairs</a></span></dt><dt><span class="section"><a href="memory.html">Memory</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#std.util.memory.allocator">Allocators</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#allocator.req">Requirements</a></span></dt><dt><span class="section"><a href="memory.html#allocator.design_issues">Design Issues</a></span></dt><dt><span class="section"><a href="memory.html#allocator.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idm270001611968">Interface Design</a></span></dt><dt><span class="section"><a href="memory.html#idm270001608416">Selecting Default Allocation Policy</a></span></dt><dt><span class="section"><a href="memory.html#idm270001595120">Disabling Memory Caching</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#allocator.using">Using a Specific Allocator</a></span></dt><dt><span class="section"><a href="memory.html#allocator.custom">Custom Allocators</a></span></dt><dt><span class="section"><a href="memory.html#allocator.ext">Extension Allocators</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#std.util.memory.auto_ptr">auto_ptr</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#auto_ptr.limitations">Limitations</a></span></dt><dt><span class="section"><a href="memory.html#auto_ptr.using">Use in Containers</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#std.util.memory.shared_ptr">shared_ptr</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#shared_ptr.req">Requirements</a></span></dt><dt><span class="section"><a href="memory.html#shared_ptr.design_issues">Design Issues</a></span></dt><dt><span class="section"><a href="memory.html#shared_ptr.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idm270000019344">Class Hierarchy</a></span></dt><dt><span class="section"><a href="memory.html#idm269999996832">Thread Safety</a></span></dt><dt><span class="section"><a href="memory.html#idm269999989536">Selecting Lock Policy</a></span></dt><dt><span class="section"><a href="memory.html#idm269999974912">Related functions and classes</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#shared_ptr.using">Use</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idm269999958496">Examples</a></span></dt><dt><span class="section"><a href="memory.html#idm269999954912">Unresolved Issues</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#shared_ptr.ack">Acknowledgments</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="traits.html">Traits</a></span></dt></dl></dd><dt><span class="chapter"><a href="strings.html">7.

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Strings

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</a></span></dt><dd><dl><dt><span class="section"><a href="strings.html#std.strings.string">String Classes</a></span></dt><dd><dl><dt><span class="section"><a href="strings.html#strings.string.simple">Simple Transformations</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.case">Case Sensitivity</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.character_types">Arbitrary Character Types</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.token">Tokenizing</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.shrink">Shrink to Fit</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.Cstring">CString (MFC)</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="localization.html">8.

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-</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#std.localization.locales">Locales</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#std.localization.locales.locale">locale</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#locales.locale.req">Requirements</a></span></dt><dt><span class="section"><a href="localization.html#locales.locale.design">Design</a></span></dt><dt><span class="section"><a href="localization.html#locales.locale.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#locale.impl.c">Interacting with "C" locales</a></span></dt></dl></dd><dt><span class="section"><a href="localization.html#locales.locale.future">Future</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="facets.html">Facets</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#std.localization.facet.ctype">ctype</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.ctype.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#idp15778336">Specializations</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.ctype.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#std.localization.facet.codecvt">codecvt</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.codecvt.req">Requirements</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.design">Design</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#codecvt.design.wchar_t_size"><span class="type">wchar_t</span> Size</a></span></dt><dt><span class="section"><a href="facets.html#codecvt.design.unicode">Support for Unicode</a></span></dt><dt><span class="section"><a href="facets.html#codecvt.design.issues">Other Issues</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.codecvt.impl">Implementation</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.use">Use</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#manual.localization.facet.messages">messages</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.messages.req">Requirements</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.design">Design</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#messages.impl.models">Models</a></span></dt><dt><span class="section"><a href="facets.html#messages.impl.gnu">The GNU Model</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.messages.use">Use</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.future">Future</a></span></dt></dl></dd></dl></dd></dl></dd><dt><span class="chapter"><a href="containers.html">9.

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+</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#std.localization.locales">Locales</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#std.localization.locales.locale">locale</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#locales.locale.req">Requirements</a></span></dt><dt><span class="section"><a href="localization.html#locales.locale.design">Design</a></span></dt><dt><span class="section"><a href="localization.html#locales.locale.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#locale.impl.c">Interacting with "C" locales</a></span></dt></dl></dd><dt><span class="section"><a href="localization.html#locales.locale.future">Future</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="facets.html">Facets</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#std.localization.facet.ctype">ctype</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.ctype.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#idm269999753024">Specializations</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.ctype.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#std.localization.facet.codecvt">codecvt</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.codecvt.req">Requirements</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.design">Design</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#codecvt.design.wchar_t_size"><span class="type">wchar_t</span> Size</a></span></dt><dt><span class="section"><a href="facets.html#codecvt.design.unicode">Support for Unicode</a></span></dt><dt><span class="section"><a href="facets.html#codecvt.design.issues">Other Issues</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.codecvt.impl">Implementation</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.use">Use</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#manual.localization.facet.messages">messages</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.messages.req">Requirements</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.design">Design</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#messages.impl.models">Models</a></span></dt><dt><span class="section"><a href="facets.html#messages.impl.gnu">The GNU Model</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.messages.use">Use</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.future">Future</a></span></dt></dl></dd></dl></dd></dl></dd><dt><span class="chapter"><a href="containers.html">9.

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</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#std.containers.sequences">Sequences</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#containers.sequences.list">list</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#sequences.list.size">list::size() is O(n)</a></span></dt></dl></dd><dt><span class="section"><a href="containers.html#containers.sequences.vector">vector</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#sequences.vector.management">Space Overhead Management</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="associative.html">Associative</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#containers.associative.insert_hints">Insertion Hints</a></span></dt><dt><span class="section"><a href="associative.html#containers.associative.bitset">bitset</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#associative.bitset.size_variable">Size Variable</a></span></dt><dt><span class="section"><a href="associative.html#associative.bitset.type_string">Type String</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="unordered_associative.html">Unordered Associative</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.hash">Hash Code</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.cache">Hash Code Caching Policy</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="containers_and_c.html">Interacting with C</a></span></dt><dd><dl><dt><span class="section"><a href="containers_and_c.html#containers.c.vs_array">Containers vs. Arrays</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="iterators.html">10.

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</a></span></dt><dt><span class="appendix"><a href="appendix_gpl.html">D.

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<acronym class="acronym">GNU</acronym> General Public License version 3

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- </a></span></dt><dt><span class="appendix"><a href="appendix_gfdl.html">E. GNU Free Documentation License</a></span></dt></dl></dd></dl></div><div class="list-of-figures"><p><strong>List of Figures</strong></p><dl><dt>22.1. <a href="policy_data_structures.html#idp17613296">Node Invariants</a></dt><dt>22.2. <a href="policy_data_structures.html#idp17619952">Underlying Associative Data Structures</a></dt><dt>22.3. <a href="policy_data_structures.html#idp17651648">Range Iteration in Different Data Structures</a></dt><dt>22.4. <a href="policy_data_structures.html#idp17666528">Point Iteration in Hash Data Structures</a></dt><dt>22.5. <a href="policy_data_structures.html#idp17675840">Effect of erase in different underlying data structures</a></dt><dt>22.6. <a href="policy_data_structures.html#idp17743424">Underlying Priority Queue Data Structures</a></dt><dt>22.7. <a href="policy_data_structures_using.html#idp17806128">Exception Hierarchy</a></dt><dt>22.8. <a href="policy_data_structures_design.html#idp18000448">Non-unique Mapping Standard Containers</a></dt><dt>22.9. <a href="policy_data_structures_design.html#fig.pbds_embedded_lists_2">

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+ </a></span></dt><dt><span class="appendix"><a href="appendix_gfdl.html">E. GNU Free Documentation License</a></span></dt></dl></dd></dl></div><div class="list-of-figures"><p><strong>List of Figures</strong></p><dl><dt>22.1. <a href="policy_data_structures.html#idm269997917584">Node Invariants</a></dt><dt>22.2. <a href="policy_data_structures.html#idm269997910864">Underlying Associative Data Structures</a></dt><dt>22.3. <a href="policy_data_structures.html#idm269997879168">Range Iteration in Different Data Structures</a></dt><dt>22.4. <a href="policy_data_structures.html#idm269997864256">Point Iteration in Hash Data Structures</a></dt><dt>22.5. <a href="policy_data_structures.html#idm269997855056">Effect of erase in different underlying data structures</a></dt><dt>22.6. <a href="policy_data_structures.html#idm269997787392">Underlying Priority Queue Data Structures</a></dt><dt>22.7. <a href="policy_data_structures_using.html#idm269997724688">Exception Hierarchy</a></dt><dt>22.8. <a href="policy_data_structures_design.html#idm269997530416">Non-unique Mapping Standard Containers</a></dt><dt>22.9. <a href="policy_data_structures_design.html#fig.pbds_embedded_lists_2">

3623

Effect of embedded lists in

3624

<code class="classname">std::multimap</code>

3625

- </a></dt><dt>22.10. <a href="policy_data_structures_design.html#idp18023952">Non-unique Mapping Containers</a></dt><dt>22.11. <a href="policy_data_structures_design.html#idp18043824">Point Iterator Hierarchy</a></dt><dt>22.12. <a href="policy_data_structures_design.html#idp18057168">Invalidation Guarantee Tags Hierarchy</a></dt><dt>22.13. <a href="policy_data_structures_design.html#idp18087392">Container Tag Hierarchy</a></dt><dt>22.14. <a href="policy_data_structures_design.html#idp18127536">Hash functions, ranged-hash functions, and

3626

- range-hashing functions</a></dt><dt>22.15. <a href="policy_data_structures_design.html#idp18191968">Insert hash sequence diagram</a></dt><dt>22.16. <a href="policy_data_structures_design.html#idp18199024">Insert hash sequence diagram with a null policy</a></dt><dt>22.17. <a href="policy_data_structures_design.html#idp18215840">Hash policy class diagram</a></dt><dt>22.18. <a href="policy_data_structures_design.html#idp18234944">Balls and bins</a></dt><dt>22.19. <a href="policy_data_structures_design.html#idp18265728">Insert resize sequence diagram</a></dt><dt>22.20. <a href="policy_data_structures_design.html#idp18273504">Standard resize policy trigger sequence

3627

- diagram</a></dt><dt>22.21. <a href="policy_data_structures_design.html#idp18277664">Standard resize policy size sequence

3628

- diagram</a></dt><dt>22.22. <a href="policy_data_structures_design.html#idp18355696">Tree node invariants</a></dt><dt>22.23. <a href="policy_data_structures_design.html#idp18365136">Tree node invalidation</a></dt><dt>22.24. <a href="policy_data_structures_design.html#idp18378304">A tree and its update policy</a></dt><dt>22.25. <a href="policy_data_structures_design.html#idp18389968">Restoring node invariants</a></dt><dt>22.26. <a href="policy_data_structures_design.html#idp18398144">Insert update sequence</a></dt><dt>22.27. <a href="policy_data_structures_design.html#idp18420400">Useless update path</a></dt><dt>22.28. <a href="policy_data_structures_design.html#idp18465088">A PATRICIA trie</a></dt><dt>22.29. <a href="policy_data_structures_design.html#idp18475584">A trie and its update policy</a></dt><dt>22.30. <a href="policy_data_structures_design.html#idp18506160">A simple list</a></dt><dt>22.31. <a href="policy_data_structures_design.html#idp18511744">The counter algorithm</a></dt><dt>22.32. <a href="policy_data_structures_design.html#idp18575568">Underlying Priority-Queue Data-Structures.</a></dt><dt>22.33. <a href="policy_data_structures_design.html#idp18610544">Priority-Queue Data-Structure Tags.</a></dt><dt>B.1. <a href="appendix_porting.html#idp22035648">Configure and Build File Dependencies</a></dt></dl></div><div class="list-of-tables"><p><strong>List of Tables</strong></p><dl><dt>1.1. <a href="status.html#idp452240">C++ 1998/2003 Implementation Status</a></dt><dt>1.2. <a href="status.html#idp8670848">C++ 2011 Implementation Status</a></dt><dt>1.3. <a href="status.html#idp7483200">C++ TR1 Implementation Status</a></dt><dt>1.4. <a href="status.html#idp12559072">C++ TR 24733 Implementation Status</a></dt><dt>3.1. <a href="using.html#idp13051936">C++ Command Options</a></dt><dt>3.2. <a href="using_headers.html#idp13079360">C++ 1998 Library Headers</a></dt><dt>3.3. <a href="using_headers.html#idp13115840">C++ 1998 Library Headers for C Library Facilities</a></dt><dt>3.4. <a href="using_headers.html#idp13140576">C++ 2011 Library Headers</a></dt><dt>3.5. <a href="using_headers.html#idp13192016">C++ 2011 Library Headers for C Library Facilities</a></dt><dt>3.6. <a href="using_headers.html#idp13221904">C++ TR 1 Library Headers</a></dt><dt>3.7. <a href="using_headers.html#idp13238832">C++ TR 1 Library Headers for C Library Facilities</a></dt><dt>3.8. <a href="using_headers.html#idp13259904">C++ TR 24733 Decimal Floating-Point Header</a></dt><dt>3.9. <a href="using_headers.html#idp13265424">C++ ABI Headers</a></dt><dt>3.10. <a href="using_headers.html#idp13271824">Extension Headers</a></dt><dt>3.11. <a href="using_headers.html#idp13307552">Extension Debug Headers</a></dt><dt>3.12. <a href="using_headers.html#idp13322320">Extension Profile Headers</a></dt><dt>3.13. <a href="using_headers.html#idp13335696">Extension Parallel Headers</a></dt><dt>17.1. <a href="debug_mode_using.html#idp16490400">Debugging Containers</a></dt><dt>17.2. <a href="debug_mode_using.html#idp16535296">Debugging Containers C++11</a></dt><dt>18.1. <a href="parallel_mode_using.html#idp16725920">Parallel Algorithms</a></dt><dt>19.1. <a href="profile_mode_design.html#idp16981200">Profile Code Location</a></dt><dt>19.2. <a href="profile_mode_diagnostics.html#idp17088912">Profile Diagnostics</a></dt><dt>21.1. <a href="bitmap_allocator_impl.html#idp17500848">Bitmap Allocator Memory Map</a></dt><dt>B.1. <a href="documentation_hacking.html#idp22162432">Doxygen Prerequisites</a></dt><dt>B.2. <a href="documentation_hacking.html#idp22238096">HTML to Doxygen Markup Comparison</a></dt><dt>B.3. <a href="documentation_hacking.html#idp22257536">Docbook Prerequisites</a></dt><dt>B.4. <a href="documentation_hacking.html#idp22335040">HTML to Docbook XML Markup Comparison</a></dt><dt>B.5. <a href="documentation_hacking.html#idp22359184">Docbook XML Element Use</a></dt><dt>B.6. <a href="api.html#idp23030528">Extension Allocators</a></dt><dt>B.7. <a href="api.html#idp23058160">Extension Allocators Continued</a></dt></dl></div><div class="list-of-equations"><p><strong>List of Equations</strong></p><dl><dt>22.1. <a href="policy_data_structures_design.html#idp18141344">Ranged Hash Function</a></dt><dt>22.2. <a href="policy_data_structures_design.html#idp18147232">Range-Hashing, Division Method</a></dt><dt>22.3. <a href="policy_data_structures_design.html#idp18151744">Division via Prime Modulo</a></dt><dt>22.4. <a href="policy_data_structures_design.html#idp18153568">Division via Bit Mask</a></dt><dt>22.5. <a href="policy_data_structures_design.html#idp18163200">

3629

+ </a></dt><dt>22.10. <a href="policy_data_structures_design.html#idm269997506912">Non-unique Mapping Containers</a></dt><dt>22.11. <a href="policy_data_structures_design.html#idm269997487104">Point Iterator Hierarchy</a></dt><dt>22.12. <a href="policy_data_structures_design.html#idm269997473760">Invalidation Guarantee Tags Hierarchy</a></dt><dt>22.13. <a href="policy_data_structures_design.html#idm269997443664">Container Tag Hierarchy</a></dt><dt>22.14. <a href="policy_data_structures_design.html#idm269997403584">Hash functions, ranged-hash functions, and

3630

+ range-hashing functions</a></dt><dt>22.15. <a href="policy_data_structures_design.html#idm269997339216">Insert hash sequence diagram</a></dt><dt>22.16. <a href="policy_data_structures_design.html#idm269997332160">Insert hash sequence diagram with a null policy</a></dt><dt>22.17. <a href="policy_data_structures_design.html#idm269997315408">Hash policy class diagram</a></dt><dt>22.18. <a href="policy_data_structures_design.html#idm269997296368">Balls and bins</a></dt><dt>22.19. <a href="policy_data_structures_design.html#idm269997265648">Insert resize sequence diagram</a></dt><dt>22.20. <a href="policy_data_structures_design.html#idm269997257872">Standard resize policy trigger sequence

3631

+ diagram</a></dt><dt>22.21. <a href="policy_data_structures_design.html#idm269997253712">Standard resize policy size sequence

3632

+ diagram</a></dt><dt>22.22. <a href="policy_data_structures_design.html#idm269997175616">Tree node invariants</a></dt><dt>22.23. <a href="policy_data_structures_design.html#idm269997166176">Tree node invalidation</a></dt><dt>22.24. <a href="policy_data_structures_design.html#idm269997153072">A tree and its update policy</a></dt><dt>22.25. <a href="policy_data_structures_design.html#idm269997141408">Restoring node invariants</a></dt><dt>22.26. <a href="policy_data_structures_design.html#idm269997133232">Insert update sequence</a></dt><dt>22.27. <a href="policy_data_structures_design.html#idm269997110976">Useless update path</a></dt><dt>22.28. <a href="policy_data_structures_design.html#idm269997066288">A PATRICIA trie</a></dt><dt>22.29. <a href="policy_data_structures_design.html#idm269997055856">A trie and its update policy</a></dt><dt>22.30. <a href="policy_data_structures_design.html#idm269997025344">A simple list</a></dt><dt>22.31. <a href="policy_data_structures_design.html#idm269997019760">The counter algorithm</a></dt><dt>22.32. <a href="policy_data_structures_design.html#idm269996955920">Underlying Priority-Queue Data-Structures.</a></dt><dt>22.33. <a href="policy_data_structures_design.html#idm269996920880">Priority-Queue Data-Structure Tags.</a></dt><dt>B.1. <a href="appendix_porting.html#idm269993497120">Configure and Build File Dependencies</a></dt></dl></div><div class="list-of-tables"><p><strong>List of Tables</strong></p><dl><dt>1.1. <a href="status.html#idm270008034928">C++ 1998/2003 Implementation Status</a></dt><dt>1.2. <a href="status.html#idm270007982624">C++ 2011 Implementation Status</a></dt><dt>1.3. <a href="status.html#idm270006687472">C++ TR1 Implementation Status</a></dt><dt>1.4. <a href="status.html#idm270002960368">C++ TR 24733 Implementation Status</a></dt><dt>3.1. <a href="using.html#idm270002481088">C++ Command Options</a></dt><dt>3.2. <a href="using_headers.html#idm270002453792">C++ 1998 Library Headers</a></dt><dt>3.3. <a href="using_headers.html#idm270002417312">C++ 1998 Library Headers for C Library Facilities</a></dt><dt>3.4. <a href="using_headers.html#idm270002392576">C++ 2011 Library Headers</a></dt><dt>3.5. <a href="using_headers.html#idm270002341136">C++ 2011 Library Headers for C Library Facilities</a></dt><dt>3.6. <a href="using_headers.html#idm270002311248">C++ TR 1 Library Headers</a></dt><dt>3.7. <a href="using_headers.html#idm270002294320">C++ TR 1 Library Headers for C Library Facilities</a></dt><dt>3.8. <a href="using_headers.html#idm270002273248">C++ TR 24733 Decimal Floating-Point Header</a></dt><dt>3.9. <a href="using_headers.html#idm270002267728">C++ ABI Headers</a></dt><dt>3.10. <a href="using_headers.html#idm270002261328">Extension Headers</a></dt><dt>3.11. <a href="using_headers.html#idm270002225600">Extension Debug Headers</a></dt><dt>3.12. <a href="using_headers.html#idm270002210832">Extension Profile Headers</a></dt><dt>3.13. <a href="using_headers.html#idm270002197456">Extension Parallel Headers</a></dt><dt>17.1. <a href="debug_mode_using.html#idm269999040896">Debugging Containers</a></dt><dt>17.2. <a href="debug_mode_using.html#idm269998996000">Debugging Containers C++11</a></dt><dt>18.1. <a href="parallel_mode_using.html#idm269998805216">Parallel Algorithms</a></dt><dt>19.1. <a href="profile_mode_design.html#idm269998550064">Profile Code Location</a></dt><dt>19.2. <a href="profile_mode_diagnostics.html#idm269998442544">Profile Diagnostics</a></dt><dt>21.1. <a href="bitmap_allocator_impl.html#idm269998030352">Bitmap Allocator Memory Map</a></dt><dt>B.1. <a href="documentation_hacking.html#idm269993370272">Doxygen Prerequisites</a></dt><dt>B.2. <a href="documentation_hacking.html#idm269993294592">HTML to Doxygen Markup Comparison</a></dt><dt>B.3. <a href="documentation_hacking.html#idm269993275152">Docbook Prerequisites</a></dt><dt>B.4. <a href="documentation_hacking.html#idm269993197520">HTML to Docbook XML Markup Comparison</a></dt><dt>B.5. <a href="documentation_hacking.html#idm269993173376">Docbook XML Element Use</a></dt><dt>B.6. <a href="api.html#idm269992502096">Extension Allocators</a></dt><dt>B.7. <a href="api.html#idm269992474464">Extension Allocators Continued</a></dt></dl></div><div class="list-of-equations"><p><strong>List of Equations</strong></p><dl><dt>22.1. <a href="policy_data_structures_design.html#idm269997389776">Ranged Hash Function</a></dt><dt>22.2. <a href="policy_data_structures_design.html#idm269997383888">Range-Hashing, Division Method</a></dt><dt>22.3. <a href="policy_data_structures_design.html#idm269997379376">Division via Prime Modulo</a></dt><dt>22.4. <a href="policy_data_structures_design.html#idm269997377552">Division via Bit Mask</a></dt><dt>22.5. <a href="policy_data_structures_design.html#idm269997367984">

3633

A Standard String Hash Function

3634

- </a></dt><dt>22.6. <a href="policy_data_structures_design.html#idp18169344">

3635

+ </a></dt><dt>22.6. <a href="policy_data_structures_design.html#idm269997361840">

3636

Only k String DNA Hash

3637

- </a></dt><dt>22.7. <a href="policy_data_structures_design.html#idp18240448">

3638

+ </a></dt><dt>22.7. <a href="policy_data_structures_design.html#idm269997290864">

3639

Probability of Probe Sequence of Length k

3640

- </a></dt><dt>22.8. <a href="policy_data_structures_design.html#idp18247216">

3641

+ </a></dt><dt>22.8. <a href="policy_data_structures_design.html#idm269997284096">

3642

Probability Probe Sequence in Some Bin

3643

</a></dt></dl></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="../index.html">Prev</a> </td><td width="20%" align="center"> </td><td width="40%" align="right"> <a accesskey="n" href="intro.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">The GNU C++ Library </td><td width="20%" align="center"><a accesskey="h" href="../index.html">Home</a></td><td width="40%" align="right" valign="top"> Part I.

3644

Introduction

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>

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-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Interacting with C</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="numerics.html" title="Chapter 12. Numerics" /><link rel="prev" href="generalized_numeric_operations.html" title="Generalized Operations" /><link rel="next" href="io.html" title="Chapter 13. Input and Output" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Interacting with C</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="generalized_numeric_operations.html">Prev</a> </td><th width="60%" align="center">Chapter 12.

3652

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Interacting with C</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="numerics.html" title="Chapter 12. Numerics" /><link rel="prev" href="generalized_numeric_operations.html" title="Generalized Operations" /><link rel="next" href="io.html" title="Chapter 13. Input and Output" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Interacting with C</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="generalized_numeric_operations.html">Prev</a> </td><th width="60%" align="center">Chapter 12.

3653

Numerics

3654

3655

</th><td width="20%" align="right"> <a accesskey="n" href="io.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.numerics.c"></a>Interacting with C</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="numerics.c.array"></a>Numerics vs. Arrays</h3></div></div></div><p>One of the major reasons why FORTRAN can chew through numbers so well

3656

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3657

===================================================================

3658

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3661

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

3662

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Appendix D. GNU General Public License version 3</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix.html" title="Part IV. Appendices" /><link rel="prev" href="appendix_free.html" title="Appendix C. Free Software Needs Free Documentation" /><link rel="next" href="appendix_gfdl.html" title="Appendix E. GNU Free Documentation License" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Appendix D.

3663

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Appendix D. GNU General Public License version 3</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix.html" title="Part IV. Appendices" /><link rel="prev" href="appendix_free.html" title="Appendix C. Free Software Needs Free Documentation" /><link rel="next" href="appendix_gfdl.html" title="Appendix E. GNU Free Documentation License" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Appendix D.

3664

<acronym class="acronym">GNU</acronym> General Public License version 3

3665

</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="appendix_free.html">Prev</a> </td><th width="60%" align="center">Part IV.

3666

Appendices

3667

@@ -77,7 +77,7 @@

3668

</p><p>

3669

The precise terms and conditions for copying, distribution and modification

3670

follow.

3671

- </p><h2><a id="idp23466384"></a>

3672

+ </p><h2><a id="idm269992066368"></a>

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TERMS AND CONDITIONS

3674

</h2><h2><a id="gpl-3-definitions"></a>

3675

0. Definitions.

3676

@@ -618,7 +618,7 @@

3677

waiver of all civil liability in connection with the Program, unless a

3678

warranty or assumption of liability accompanies a copy of the Program in

3679

return for a fee.

3680

- </p><h2><a id="idp23565184"></a>

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+ </p><h2><a id="idm269991967568"></a>

3682

END OF TERMS AND CONDITIONS

3683

</h2><h2><a id="HowToApply"></a>

3684

How to Apply These Terms to Your New Programs

3685

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3686

===================================================================

3687

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>

3691

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Coding Style</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_contributing.html" title="Appendix A. Contributing" /><link rel="prev" href="source_organization.html" title="Directory Layout and Source Conventions" /><link rel="next" href="source_design_notes.html" title="Design Notes" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Coding Style</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="source_organization.html">Prev</a> </td><th width="60%" align="center">Appendix A.

3692

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Coding Style</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_contributing.html" title="Appendix A. Contributing" /><link rel="prev" href="source_organization.html" title="Directory Layout and Source Conventions" /><link rel="next" href="source_design_notes.html" title="Design Notes" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Coding Style</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="source_organization.html">Prev</a> </td><th width="60%" align="center">Appendix A.

3693

Contributing

3694

3695

</th><td width="20%" align="right"> <a accesskey="n" href="source_design_notes.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="contrib.coding_style"></a>Coding Style</h2></div></div></div><p>

3696

Index: libstdc++-v3/doc/html/manual/streambufs.html

3697

===================================================================

3698

--- a/src/libstdc++-v3/doc/html/manual/streambufs.html (.../tags/gcc_4_8_2_release)

3699

+++ b/src/libstdc++-v3/doc/html/manual/streambufs.html (.../branches/gcc-4_8-branch)

3700

@@ -1,5 +1,5 @@

3701

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

3702

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Stream Buffers</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="io.html" title="Chapter 13. Input and Output" /><link rel="prev" href="io.html" title="Chapter 13. Input and Output" /><link rel="next" href="stringstreams.html" title="Memory Based Streams" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Stream Buffers</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="io.html">Prev</a> </td><th width="60%" align="center">Chapter 13.

3703

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Stream Buffers</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="io.html" title="Chapter 13. Input and Output" /><link rel="prev" href="io.html" title="Chapter 13. Input and Output" /><link rel="next" href="stringstreams.html" title="Memory Based Streams" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Stream Buffers</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="io.html">Prev</a> </td><th width="60%" align="center">Chapter 13.

3704

Input and Output

3705

3706

</th><td width="20%" align="right"> <a accesskey="n" href="stringstreams.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.io.streambufs"></a>Stream Buffers</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="io.streambuf.derived"></a>Derived streambuf Classes</h3></div></div></div><p>

3707

Index: libstdc++-v3/doc/html/manual/utilities.html

3708

===================================================================

3709

--- a/src/libstdc++-v3/doc/html/manual/utilities.html (.../tags/gcc_4_8_2_release)

3710

+++ b/src/libstdc++-v3/doc/html/manual/utilities.html (.../branches/gcc-4_8-branch)

3711

@@ -1,5 +1,5 @@

3712

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

3713

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 6. Utilities</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II. Standard Contents" /><link rel="prev" href="concept_checking.html" title="Concept Checking" /><link rel="next" href="pairs.html" title="Pairs" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 6.

3714

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 6. Utilities</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II. Standard Contents" /><link rel="prev" href="concept_checking.html" title="Concept Checking" /><link rel="next" href="pairs.html" title="Pairs" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 6.

3715

Utilities

3716

3717

</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="concept_checking.html">Prev</a> </td><th width="60%" align="center">Part II.

3718

@@ -6,8 +6,8 @@

3719

Standard Contents

3720

</th><td width="20%" align="right"> <a accesskey="n" href="pairs.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="std.util"></a>Chapter 6.

3721

Utilities

3722

- <a id="idp13862416" class="indexterm"></a>

3723

-</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="utilities.html#std.util.functors">Functors</a></span></dt><dt><span class="section"><a href="pairs.html">Pairs</a></span></dt><dt><span class="section"><a href="memory.html">Memory</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#std.util.memory.allocator">Allocators</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#allocator.req">Requirements</a></span></dt><dt><span class="section"><a href="memory.html#allocator.design_issues">Design Issues</a></span></dt><dt><span class="section"><a href="memory.html#allocator.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idp13920976">Interface Design</a></span></dt><dt><span class="section"><a href="memory.html#idp13924528">Selecting Default Allocation Policy</a></span></dt><dt><span class="section"><a href="memory.html#idp13937824">Disabling Memory Caching</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#allocator.using">Using a Specific Allocator</a></span></dt><dt><span class="section"><a href="memory.html#allocator.custom">Custom Allocators</a></span></dt><dt><span class="section"><a href="memory.html#allocator.ext">Extension Allocators</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#std.util.memory.auto_ptr">auto_ptr</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#auto_ptr.limitations">Limitations</a></span></dt><dt><span class="section"><a href="memory.html#auto_ptr.using">Use in Containers</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#std.util.memory.shared_ptr">shared_ptr</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#shared_ptr.req">Requirements</a></span></dt><dt><span class="section"><a href="memory.html#shared_ptr.design_issues">Design Issues</a></span></dt><dt><span class="section"><a href="memory.html#shared_ptr.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idp15512272">Class Hierarchy</a></span></dt><dt><span class="section"><a href="memory.html#idp15534784">Thread Safety</a></span></dt><dt><span class="section"><a href="memory.html#idp15542080">Selecting Lock Policy</a></span></dt><dt><span class="section"><a href="memory.html#idp15556704">Related functions and classes</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#shared_ptr.using">Use</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idp15573056">Examples</a></span></dt><dt><span class="section"><a href="memory.html#idp15576640">Unresolved Issues</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#shared_ptr.ack">Acknowledgments</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="traits.html">Traits</a></span></dt></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.util.functors"></a>Functors</h2></div></div></div><p>If you don't know what functors are, you're not alone. Many people

3724

+ <a id="idm270001670464" class="indexterm"></a>

3725

+</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="utilities.html#std.util.functors">Functors</a></span></dt><dt><span class="section"><a href="pairs.html">Pairs</a></span></dt><dt><span class="section"><a href="memory.html">Memory</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#std.util.memory.allocator">Allocators</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#allocator.req">Requirements</a></span></dt><dt><span class="section"><a href="memory.html#allocator.design_issues">Design Issues</a></span></dt><dt><span class="section"><a href="memory.html#allocator.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idm270001611968">Interface Design</a></span></dt><dt><span class="section"><a href="memory.html#idm270001608416">Selecting Default Allocation Policy</a></span></dt><dt><span class="section"><a href="memory.html#idm270001595120">Disabling Memory Caching</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#allocator.using">Using a Specific Allocator</a></span></dt><dt><span class="section"><a href="memory.html#allocator.custom">Custom Allocators</a></span></dt><dt><span class="section"><a href="memory.html#allocator.ext">Extension Allocators</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#std.util.memory.auto_ptr">auto_ptr</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#auto_ptr.limitations">Limitations</a></span></dt><dt><span class="section"><a href="memory.html#auto_ptr.using">Use in Containers</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#std.util.memory.shared_ptr">shared_ptr</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#shared_ptr.req">Requirements</a></span></dt><dt><span class="section"><a href="memory.html#shared_ptr.design_issues">Design Issues</a></span></dt><dt><span class="section"><a href="memory.html#shared_ptr.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idm270000019344">Class Hierarchy</a></span></dt><dt><span class="section"><a href="memory.html#idm269999996832">Thread Safety</a></span></dt><dt><span class="section"><a href="memory.html#idm269999989536">Selecting Lock Policy</a></span></dt><dt><span class="section"><a href="memory.html#idm269999974912">Related functions and classes</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#shared_ptr.using">Use</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idm269999958496">Examples</a></span></dt><dt><span class="section"><a href="memory.html#idm269999954912">Unresolved Issues</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#shared_ptr.ack">Acknowledgments</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="traits.html">Traits</a></span></dt></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.util.functors"></a>Functors</h2></div></div></div><p>If you don't know what functors are, you're not alone. Many people

3726

get slightly the wrong idea. In the interest of not reinventing

3727

the wheel, we will refer you to the introduction to the functor

3728

concept written by SGI as part of their STL, in

3729

Index: libstdc++-v3/include/debug/functions.h

3730

===================================================================

3731

--- a/src/libstdc++-v3/include/debug/functions.h (.../tags/gcc_4_8_2_release)

3732

+++ b/src/libstdc++-v3/include/debug/functions.h (.../branches/gcc-4_8-branch)

3733

@@ -345,11 +345,13 @@

3734

return __check_sorted_set_aux(__first, __last, __pred, _SameType());

3735

}

3736

3737

+ // _GLIBCXX_RESOLVE_LIB_DEFECTS

3738

+ // 270. Binary search requirements overly strict

3739

+ // Determine if a sequence is partitioned w.r.t. this element.

3740

template<typename _ForwardIterator, typename _Tp>

3741

inline bool

3742

- __check_partitioned_lower_aux(_ForwardIterator __first,

3743

- _ForwardIterator __last, const _Tp& __value,

3744

- std::forward_iterator_tag)

3745

+ __check_partitioned_lower(_ForwardIterator __first,

3746

+ _ForwardIterator __last, const _Tp& __value)

3747

{

3748

while (__first != __last && *__first < __value)

3749

++__first;

3750

@@ -362,38 +364,11 @@

3751

return __first == __last;

3752

}

3753

3754

- // For performance reason, as the iterator range has been validated, check on

3755

- // random access safe iterators is done using the base iterator.

3756

- template<typename _Iterator, typename _Sequence, typename _Tp>

3757

- inline bool

3758

- __check_partitioned_lower_aux(

3759

- const _Safe_iterator<_Iterator, _Sequence>& __first,

3760

- const _Safe_iterator<_Iterator, _Sequence>& __last,

3761

- const _Tp& __value,

3762

- std::random_access_iterator_tag __tag)

3763

- {

3764

- return __check_partitioned_lower_aux(__first.base(), __last.base(),

3765

- __value, __tag);

3766

- }

3767

-

3768

- // _GLIBCXX_RESOLVE_LIB_DEFECTS

3769

- // 270. Binary search requirements overly strict

3770

- // Determine if a sequence is partitioned w.r.t. this element.

3771

template<typename _ForwardIterator, typename _Tp>

3772

inline bool

3773

- __check_partitioned_lower(_ForwardIterator __first,

3774

+ __check_partitioned_upper(_ForwardIterator __first,

3775

_ForwardIterator __last, const _Tp& __value)

3776

{

3777

- return __check_partitioned_lower_aux(__first, __last, __value,

3778

- std::__iterator_category(__first));

3779

- }

3780

-

3781

- template<typename _ForwardIterator, typename _Tp>

3782

- inline bool

3783

- __check_partitioned_upper_aux(_ForwardIterator __first,

3784

- _ForwardIterator __last, const _Tp& __value,

3785

- std::forward_iterator_tag)

3786

- {

3787

while (__first != __last && !(__value < *__first))

3788

++__first;

3789

if (__first != __last)

3790

@@ -405,35 +380,12 @@

3791

return __first == __last;

3792

}

3793

3794

- // For performance reason, as the iterator range has been validated, check on

3795

- // random access safe iterators is done using the base iterator.

3796

- template<typename _Iterator, typename _Sequence, typename _Tp>

3797

- inline bool

3798

- __check_partitioned_upper_aux(

3799

- const _Safe_iterator<_Iterator, _Sequence>& __first,

3800

- const _Safe_iterator<_Iterator, _Sequence>& __last,

3801

- const _Tp& __value,

3802

- std::random_access_iterator_tag __tag)

3803

- {

3804

- return __check_partitioned_upper_aux(__first.base(), __last.base(),

3805

- __value, __tag);

3806

- }

3807

-

3808

- template<typename _ForwardIterator, typename _Tp>

3809

- inline bool

3810

- __check_partitioned_upper(_ForwardIterator __first,

3811

- _ForwardIterator __last, const _Tp& __value)

3812

- {

3813

- return __check_partitioned_upper_aux(__first, __last, __value,

3814

- std::__iterator_category(__first));

3815

- }

3816

-

3817

+ // Determine if a sequence is partitioned w.r.t. this element.

3818

template<typename _ForwardIterator, typename _Tp, typename _Pred>

3819

inline bool

3820

- __check_partitioned_lower_aux(_ForwardIterator __first,

3821

- _ForwardIterator __last, const _Tp& __value,

3822

- _Pred __pred,

3823

- std::forward_iterator_tag)

3824

+ __check_partitioned_lower(_ForwardIterator __first,

3825

+ _ForwardIterator __last, const _Tp& __value,

3826

+ _Pred __pred)

3827

{

3828

while (__first != __last && bool(__pred(*__first, __value)))

3829

++__first;

3830

@@ -446,39 +398,12 @@

3831

return __first == __last;

3832

}

3833

3834

- // For performance reason, as the iterator range has been validated, check on

3835

- // random access safe iterators is done using the base iterator.

3836

- template<typename _Iterator, typename _Sequence,

3837

- typename _Tp, typename _Pred>

3838

- inline bool

3839

- __check_partitioned_lower_aux(

3840

- const _Safe_iterator<_Iterator, _Sequence>& __first,

3841

- const _Safe_iterator<_Iterator, _Sequence>& __last,

3842

- const _Tp& __value, _Pred __pred,

3843

- std::random_access_iterator_tag __tag)

3844

- {

3845

- return __check_partitioned_lower_aux(__first.base(), __last.base(),

3846

- __value, __pred, __tag);

3847

- }

3848

-

3849

- // Determine if a sequence is partitioned w.r.t. this element.

3850

template<typename _ForwardIterator, typename _Tp, typename _Pred>

3851

inline bool

3852

- __check_partitioned_lower(_ForwardIterator __first,

3853

+ __check_partitioned_upper(_ForwardIterator __first,

3854

_ForwardIterator __last, const _Tp& __value,

3855

_Pred __pred)

3856

{

3857

- return __check_partitioned_lower_aux(__first, __last, __value, __pred,

3858

- std::__iterator_category(__first));

3859

- }

3860

-

3861

- template<typename _ForwardIterator, typename _Tp, typename _Pred>

3862

- inline bool

3863

- __check_partitioned_upper_aux(_ForwardIterator __first,

3864

- _ForwardIterator __last, const _Tp& __value,

3865

- _Pred __pred,

3866

- std::forward_iterator_tag)

3867

- {

3868

while (__first != __last && !bool(__pred(__value, *__first)))

3869

++__first;

3870

if (__first != __last)

3871

@@ -490,31 +415,6 @@

3872

return __first == __last;

3873

}

3874

3875

- // For performance reason, as the iterator range has been validated, check on

3876

- // random access safe iterators is done using the base iterator.

3877

- template<typename _Iterator, typename _Sequence,

3878

- typename _Tp, typename _Pred>

3879

- inline bool

3880

- __check_partitioned_upper_aux(

3881

- const _Safe_iterator<_Iterator, _Sequence>& __first,

3882

- const _Safe_iterator<_Iterator, _Sequence>& __last,

3883

- const _Tp& __value, _Pred __pred,

3884

- std::random_access_iterator_tag __tag)

3885

- {

3886

- return __check_partitioned_upper_aux(__first.base(), __last.base(),

3887

- __value, __pred, __tag);

3888

- }

3889

-

3890

- template<typename _ForwardIterator, typename _Tp, typename _Pred>

3891

- inline bool

3892

- __check_partitioned_upper(_ForwardIterator __first,

3893

- _ForwardIterator __last, const _Tp& __value,

3894

- _Pred __pred)

3895

- {

3896

- return __check_partitioned_upper_aux(__first, __last, __value, __pred,

3897

- std::__iterator_category(__first));

3898

- }

3899

-

3900

// Helper struct to detect random access safe iterators.

3901

template<typename _Iterator>

3902

struct __is_safe_random_iterator

3903

Index: libstdc++-v3/include/debug/safe_unordered_base.h

3904

===================================================================

3905

--- a/src/libstdc++-v3/include/debug/safe_unordered_base.h (.../tags/gcc_4_8_2_release)

3906

+++ b/src/libstdc++-v3/include/debug/safe_unordered_base.h (.../branches/gcc-4_8-branch)

3907

@@ -133,9 +133,19 @@

3908

protected:

3909

// Initialize with a version number of 1 and no iterators

3910

_Safe_unordered_container_base()

3911

- : _M_local_iterators(0), _M_const_local_iterators(0)

3912

+ : _M_local_iterators(nullptr), _M_const_local_iterators(nullptr)

3913

{ }

3914

3915

+ // Initialize with a version number of 1 and no iterators

3916

+ _Safe_unordered_container_base(const _Safe_unordered_container_base&)

3917

+ noexcept

3918

+ : _Safe_unordered_container_base() { }

3919

+

3920

+ _Safe_unordered_container_base(_Safe_unordered_container_base&& __x)

3921

+ noexcept

3922

+ : _Safe_unordered_container_base()

3923

+ { this->_M_swap(__x); }

3924

+

3925

/** Notify all iterators that reference this container that the

3926

container is being destroyed. */

3927

~_Safe_unordered_container_base()

3928

Index: libstdc++-v3/include/debug/macros.h

3929

===================================================================

3930

--- a/src/libstdc++-v3/include/debug/macros.h (.../tags/gcc_4_8_2_release)

3931

+++ b/src/libstdc++-v3/include/debug/macros.h (.../branches/gcc-4_8-branch)

3932

@@ -261,8 +261,9 @@

3933

w.r.t. the value _Value. */

3934

#define __glibcxx_check_partitioned_lower(_First,_Last,_Value) \

3935

__glibcxx_check_valid_range(_First,_Last); \

3936

-_GLIBCXX_DEBUG_VERIFY(__gnu_debug::__check_partitioned_lower(_First, _Last, \

3937

- _Value), \

3938

+_GLIBCXX_DEBUG_VERIFY(__gnu_debug::__check_partitioned_lower( \

3939

+ __gnu_debug::__base(_First), \

3940

+ __gnu_debug::__base(_Last), _Value), \

3941

_M_message(__gnu_debug::__msg_unpartitioned) \

3942

._M_iterator(_First, #_First) \

3943

._M_iterator(_Last, #_Last) \

3944

@@ -270,8 +271,9 @@

3945

3946

#define __glibcxx_check_partitioned_upper(_First,_Last,_Value) \

3947

__glibcxx_check_valid_range(_First,_Last); \

3948

-_GLIBCXX_DEBUG_VERIFY(__gnu_debug::__check_partitioned_upper(_First, _Last, \

3949

- _Value), \

3950

+_GLIBCXX_DEBUG_VERIFY(__gnu_debug::__check_partitioned_upper( \

3951

+ __gnu_debug::__base(_First), \

3952

+ __gnu_debug::__base(_Last), _Value), \

3953

_M_message(__gnu_debug::__msg_unpartitioned) \

3954

._M_iterator(_First, #_First) \

3955

._M_iterator(_Last, #_Last) \

3956

@@ -281,8 +283,9 @@

3957

w.r.t. the value _Value and predicate _Pred. */

3958

#define __glibcxx_check_partitioned_lower_pred(_First,_Last,_Value,_Pred) \

3959

__glibcxx_check_valid_range(_First,_Last); \

3960

-_GLIBCXX_DEBUG_VERIFY(__gnu_debug::__check_partitioned_lower(_First, _Last, \

3961

- _Value, _Pred), \

3962

+_GLIBCXX_DEBUG_VERIFY(__gnu_debug::__check_partitioned_lower( \

3963

+ __gnu_debug::__base(_First), \

3964

+ __gnu_debug::__base(_Last), _Value, _Pred), \

3965

_M_message(__gnu_debug::__msg_unpartitioned_pred) \

3966

._M_iterator(_First, #_First) \

3967

._M_iterator(_Last, #_Last) \

3968

@@ -293,8 +296,9 @@

3969

w.r.t. the value _Value and predicate _Pred. */

3970

#define __glibcxx_check_partitioned_upper_pred(_First,_Last,_Value,_Pred) \

3971

__glibcxx_check_valid_range(_First,_Last); \

3972

-_GLIBCXX_DEBUG_VERIFY(__gnu_debug::__check_partitioned_upper(_First, _Last, \

3973

- _Value, _Pred), \

3974

+_GLIBCXX_DEBUG_VERIFY(__gnu_debug::__check_partitioned_upper( \

3975

+ __gnu_debug::__base(_First), \

3976

+ __gnu_debug::__base(_Last), _Value, _Pred), \

3977

_M_message(__gnu_debug::__msg_unpartitioned_pred) \

3978

._M_iterator(_First, #_First) \

3979

._M_iterator(_Last, #_Last) \

3980

Index: libstdc++-v3/include/std/tuple

3981

===================================================================

3982

--- a/src/libstdc++-v3/include/std/tuple (.../tags/gcc_4_8_2_release)

3983

+++ b/src/libstdc++-v3/include/std/tuple (.../branches/gcc-4_8-branch)

3984

@@ -755,7 +755,7 @@

3985

typename tuple_element<__i, tuple<_Elements...>>::type

3986

>::type

3987

get(tuple<_Elements...>& __t) noexcept

3988

- { return __get_helper<__i>(__t); }

3989

+ { return std::__get_helper<__i>(__t); }

3990

3991

template<std::size_t __i, typename... _Elements>

3992

constexpr typename __add_c_ref<

3993

@@ -762,7 +762,7 @@

3994

typename tuple_element<__i, tuple<_Elements...>>::type

3995

>::type

3996

get(const tuple<_Elements...>& __t) noexcept

3997

- { return __get_helper<__i>(__t); }

3998

+ { return std::__get_helper<__i>(__t); }

3999

4000

template<std::size_t __i, typename... _Elements>

4001

constexpr typename __add_r_ref<

4002

Index: libstdc++-v3/include/std/future

4003

===================================================================

4004

--- a/src/libstdc++-v3/include/std/future (.../tags/gcc_4_8_2_release)

4005

+++ b/src/libstdc++-v3/include/std/future (.../branches/gcc-4_8-branch)

4006

@@ -1261,9 +1261,11 @@

4007

struct __future_base::_Task_state<_Fn, _Alloc, _Res(_Args...)> final

4008

: __future_base::_Task_state_base<_Res(_Args...)>

4009

{

4010

- _Task_state(_Fn&& __fn, const _Alloc& __a)

4011

- : _Task_state_base<_Res(_Args...)>(__a), _M_impl(std::move(__fn), __a)

4012

- { }

4013

+ template<typename _Fn2>

4014

+ _Task_state(_Fn2&& __fn, const _Alloc& __a)

4015

+ : _Task_state_base<_Res(_Args...)>(__a),

4016

+ _M_impl(std::forward<_Fn2>(__fn), __a)

4017

+ { }

4018

4019

private:

4020

virtual void

4021

@@ -1292,19 +1294,21 @@

4022

4023

struct _Impl : _Alloc

4024

{

4025

- _Impl(_Fn&& __fn, const _Alloc& __a)

4026

- : _Alloc(__a), _M_fn(std::move(__fn)) { }

4027

+ template<typename _Fn2>

4028

+ _Impl(_Fn2&& __fn, const _Alloc& __a)

4029

+ : _Alloc(__a), _M_fn(std::forward<_Fn2>(__fn)) { }

4030

_Fn _M_fn;

4031

} _M_impl;

4032

};

4033

4034

- template<typename _Signature, typename _Fn, typename _Alloc>

4035

- static shared_ptr<__future_base::_Task_state_base<_Signature>>

4036

- __create_task_state(_Fn&& __fn, const _Alloc& __a)

4037

- {

4038

- typedef __future_base::_Task_state<_Fn, _Alloc, _Signature> _State;

4039

- return std::allocate_shared<_State>(__a, std::move(__fn), __a);

4040

- }

4041

+ template<typename _Signature, typename _Fn, typename _Alloc>

4042

+ static shared_ptr<__future_base::_Task_state_base<_Signature>>

4043

+ __create_task_state(_Fn&& __fn, const _Alloc& __a)

4044

+ {

4045

+ typedef typename decay<_Fn>::type _Fn2;

4046

+ typedef __future_base::_Task_state<_Fn2, _Alloc, _Signature> _State;

4047

+ return std::allocate_shared<_State>(__a, std::forward<_Fn>(__fn), __a);

4048

+ }

4049

4050

template<typename _Fn, typename _Alloc, typename _Res, typename... _Args>

4051

shared_ptr<__future_base::_Task_state_base<_Res(_Args...)>>

4052

@@ -1344,7 +1348,8 @@

4053

__constrain_pkgdtask<packaged_task, _Fn>::__type>

4054

explicit

4055

packaged_task(_Fn&& __fn)

4056

- : packaged_task(allocator_arg, std::allocator<int>(), std::move(__fn))

4057

+ : packaged_task(allocator_arg, std::allocator<int>(),

4058

+ std::forward<_Fn>(__fn))

4059

{ }

4060

4061

// _GLIBCXX_RESOLVE_LIB_DEFECTS

4062

Index: libstdc++-v3/include/std/functional

4063

===================================================================

4064

--- a/src/libstdc++-v3/include/std/functional (.../tags/gcc_4_8_2_release)

4065

+++ b/src/libstdc++-v3/include/std/functional (.../branches/gcc-4_8-branch)

4066

@@ -2181,8 +2181,15 @@

4067

using _Invoke = decltype(__callable_functor(std::declval<_Functor&>())

4068

(std::declval<_ArgTypes>()...) );

4069

4070

+ // Used so the return type convertibility checks aren't done when

4071

+ // performing overload resolution for copy construction/assignment.

4072

+ template<typename _Tp>

4073

+ using _NotSelf = __not_<is_same<_Tp, function>>;

4074

+

4075

template<typename _Functor>

4076

- using _Callable = __check_func_return_type<_Invoke<_Functor>, _Res>;

4077

+ using _Callable

4078

+ = __and_<_NotSelf<_Functor>,

4079

+ __check_func_return_type<_Invoke<_Functor>, _Res>>;

4080

4081

template<typename _Cond, typename _Tp>

4082

using _Requires = typename enable_if<_Cond::value, _Tp>::type;

4083

@@ -2323,7 +2330,7 @@

4084

* reference_wrapper<F>, this function will not throw.

4085

*/

4086

template<typename _Functor>

4087

- _Requires<_Callable<_Functor>, function&>

4088

+ _Requires<_Callable<typename decay<_Functor>::type>, function&>

4089

operator=(_Functor&& __f)

4090

{

4091

function(std::forward<_Functor>(__f)).swap(*this);

4092

Index: libstdc++-v3/include/bits/atomic_base.h

4093

===================================================================

4094

--- a/src/libstdc++-v3/include/bits/atomic_base.h (.../tags/gcc_4_8_2_release)

4095

+++ b/src/libstdc++-v3/include/bits/atomic_base.h (.../branches/gcc-4_8-branch)

4096

@@ -764,11 +764,11 @@

4097

4098

bool

4099

is_lock_free() const noexcept

4100

- { return __atomic_is_lock_free(_M_type_size(1), nullptr); }

4101

+ { return __atomic_is_lock_free(sizeof(__pointer_type), nullptr); }

4102

4103

bool

4104

is_lock_free() const volatile noexcept

4105

- { return __atomic_is_lock_free(_M_type_size(1), nullptr); }

4106

+ { return __atomic_is_lock_free(sizeof(__pointer_type), nullptr); }

4107

4108

void

4109

store(__pointer_type __p,

4110

Index: libstdc++-v3/include/bits/stl_vector.h

4111

===================================================================

4112

--- a/src/libstdc++-v3/include/bits/stl_vector.h (.../tags/gcc_4_8_2_release)

4113

+++ b/src/libstdc++-v3/include/bits/stl_vector.h (.../branches/gcc-4_8-branch)

4114

@@ -1361,7 +1361,8 @@

4115

void

4116

_M_move_assign(vector&& __x, std::true_type) noexcept

4117

{

4118

- const vector __tmp(std::move(*this));

4119

+ vector __tmp(get_allocator());

4120

+ this->_M_impl._M_swap_data(__tmp._M_impl);

4121

this->_M_impl._M_swap_data(__x._M_impl);

4122

if (_Alloc_traits::_S_propagate_on_move_assign())

4123

std::__alloc_on_move(_M_get_Tp_allocator(),

4124

Index: libstdc++-v3/include/bits/stl_algo.h

4125

===================================================================

4126

--- a/src/libstdc++-v3/include/bits/stl_algo.h (.../tags/gcc_4_8_2_release)

4127

+++ b/src/libstdc++-v3/include/bits/stl_algo.h (.../branches/gcc-4_8-branch)

4128

@@ -2279,7 +2279,7 @@

4129

_RandomAccessIterator __last)

4130

{

4131

_RandomAccessIterator __mid = __first + (__last - __first) / 2;

4132

- std::__move_median_to_first(__first, __first + 1, __mid, (__last - 2));

4133

+ std::__move_median_to_first(__first, __first + 1, __mid, __last - 1);

4134

return std::__unguarded_partition(__first + 1, __last, *__first);

4135

}

4136

4137

@@ -2291,7 +2291,7 @@

4138

_RandomAccessIterator __last, _Compare __comp)

4139

{

4140

_RandomAccessIterator __mid = __first + (__last - __first) / 2;

4141

- std::__move_median_to_first(__first, __first + 1, __mid, (__last - 2),

4142

+ std::__move_median_to_first(__first, __first + 1, __mid, __last - 1,

4143

__comp);

4144

return std::__unguarded_partition(__first + 1, __last, *__first, __comp);

4145

}

4146

Index: libstdc++-v3/include/bits/shared_ptr_base.h

4147

===================================================================

4148

--- a/src/libstdc++-v3/include/bits/shared_ptr_base.h (.../tags/gcc_4_8_2_release)

4149

+++ b/src/libstdc++-v3/include/bits/shared_ptr_base.h (.../branches/gcc-4_8-branch)

4150

@@ -233,7 +233,7 @@

4151

_M_add_ref_lock()

4152

{

4153

// Perform lock-free add-if-not-zero operation.

4154

- _Atomic_word __count = _M_use_count;

4155

+ _Atomic_word __count = _M_get_use_count();

4156

do

4157

{

4158

if (__count == 0)

4159

@@ -391,7 +391,7 @@

4160

public:

4161

template<typename... _Args>

4162

_Sp_counted_ptr_inplace(_Alloc __a, _Args&&... __args)

4163

- : _M_impl(__a), _M_storage()

4164

+ : _M_impl(__a)

4165

{

4166

_M_impl._M_ptr = static_cast<_Tp*>(static_cast<void*>(&_M_storage));

4167

// _GLIBCXX_RESOLVE_LIB_DEFECTS

4168

@@ -819,7 +819,7 @@

4169

: _M_ptr(__r.get()), _M_refcount()

4170

{

4171

__glibcxx_function_requires(_ConvertibleConcept<_Tp1*, _Tp*>)

4172

- auto __tmp = std::__addressof(*__r.get());

4173

+ auto __tmp = __r.get();

4174

_M_refcount = __shared_count<_Lp>(std::move(__r));

4175

__enable_shared_from_this_helper(_M_refcount, __tmp, __tmp);

4176

}

4177

Index: libstdc++-v3/include/c_global/cstdio

4178

===================================================================

4179

--- a/src/libstdc++-v3/include/c_global/cstdio (.../tags/gcc_4_8_2_release)

4180

+++ b/src/libstdc++-v3/include/c_global/cstdio (.../branches/gcc-4_8-branch)

4181

@@ -69,6 +69,7 @@

4182

#undef ftell

4183

#undef fwrite

4184

#undef getc

4185

+#undef getchar

4186

#undef gets

4187

#undef perror

4188

#undef printf

4189

Index: libstdc++-v3/ChangeLog

4190

===================================================================

4191

--- a/src/libstdc++-v3/ChangeLog (.../tags/gcc_4_8_2_release)

4192

+++ b/src/libstdc++-v3/ChangeLog (.../branches/gcc-4_8-branch)

4193

@@ -1,3 +1,188 @@

4194

+2014-05-06 Jonathan Wakely <jwakely@redhat.com>

4195

+

4196

+ Backport from mainline

4197

+ 2014-04-15 Jonathan Wakely <jwakely@redhat.com>

4198

+

4199

+ PR libstdc++/60594

4200

+ * include/std/functional (function::_Callable): Exclude own type

4201

+ from the callable checks.

4202

+ * testsuite/20_util/function/60594.cc: New.

4203

+

4204

+2014-04-27 Jonathan Wakely <jwakely@redhat.com>

4205

+

4206

+ PR libstdc++/60497

4207

+ * include/std/tuple (get): Qualify calls to prevent ADL.

4208

+ * testsuite/20_util/tuple/60497.cc: New.

4209

+

4210

+2012-04-05 Dominique d'Humieres <dominiq@lps.ens.fr>

4211

+ Jack Howarth <howarth@bromo.med.uc.edu>

4212

+

4213

+ PR target/54407

4214

+ * 30_threads/condition_variable/54185.cc: Skip for darwin < 11.

4215

+

4216

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

4217

+

4218

+ Backport from mainline

4219

+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

4220

+

4221

+ * configure: Regenerate.

4222

+

4223

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

4224

+

4225

+ Backport from mainline r204808:

4226

+

4227

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

4228

+

4229

+ * scripts/extract_symvers.in: Ignore <localentry: > fields

4230

+ in readelf --symbols output.

4231

+

4232

+2014-03-26 Jonathan Wakely <jwakely@redhat.com>

4233

+

4234

+ PR libstdc++/59548

4235

+ * include/debug/safe_unordered_base.h (_Safe_unordered_container_base):

4236

+ Define copy and move constructors that handle iterators correctly.

4237

+ * testsuite/23_containers/unordered_map/59548.cc: New.

4238

+

4239

+2014-03-25 Jonathan Wakely <jwakely@redhat.com>

4240

+

4241

+ PR libstdc++/60658

4242

+ * include/bits/atomic_base.h (__atomic_base<_PTp*>::is_lock_free()):

4243

+ Use sizeof pointer type not the element type.

4244

+ * testsuite/29_atomics/atomic/60658.cc: New.

4245

+

4246

+2014-03-18 Jonathan Wakely <jwakely@redhat.com>

4247

+

4248

+ PR libstdc++/60564

4249

+ * include/std/future (__future_base::_Task_state<>): Change

4250

+ constructors to template functions using perfect forwarding.

4251

+ (__create_task_state): Use decayed type as stored task.

4252

+ (packaged_task::packaged_task(_Fn&&)): Forward instead of moving.

4253

+ * testsuite/30_threads/packaged_task/60564.cc: New.

4254

+

4255

+2014-03-12 Roland McGrath <mcgrathr@google.com>

4256

+ Mark Seaborn <mseaborn@google.com>

4257

+

4258

+ PR libstdc++/59392

4259

+ * libsupc++/eh_call.cc (__cxa_call_unexpected): Call __do_catch with

4260

+ the address of a null pointer, not with a null pointer to pointer.

4261

+ Copy comment for this case from eh_personality.cc:__cxa_call_unexpected.

4262

+ * testsuite/18_support/bad_exception/59392.cc: New file.

4263

+

4264

+2014-03-11 Jonathan Wakely <jwakely@redhat.com>

4265

+

4266

+ Backport from mainline.

4267

+ 2014-01-09 Jonathan Wakely <jwakely@redhat.com>

4268

+

4269

+ PR libstdc++/59680

4270

+ * src/c++11/thread.cc (__sleep_for): Fix call to ::sleep.

4271

+

4272

+2014-03-11 Jonathan Wakely <jwakely@redhat.com>

4273

+

4274

+ Backport from mainline.

4275

+ 2014-01-27 Jonathan Wakely <jwakely@redhat.com>

4276

+

4277

+ PR libstdc++/59215

4278

+ * include/bits/shared_ptr_base.h

4279

+ (_Sp_counted_base<_S_atomic>::_M_add_ref_lock()): Use relaxed atomic

4280

+ load.

4281

+

4282

+2014-03-11 Jonathan Wakely <jwakely@redhat.com>

4283

+

4284

+ Backport from mainline.

4285

+

4286

+ 2014-01-09 Jonathan Wakely <jwakely@redhat.com>

4287

+

4288

+ PR libstdc++/59738

4289

+ * include/bits/stl_vector.h (vector<>::_M_move_assign): Restore

4290

+ support for non-Movable types.

4291

+

4292

+ 2014-01-08 François Dumont <fdumont@gcc.gnu.org>

4293

+

4294

+ * include/bits/stl_vector.h (std::vector<>::_M_move_assign): Pass

4295

+ *this allocator instance when building temporary vector instance

4296

+ so that *this allocator does not get moved.

4297

+ * testsuite/23_containers/vector/allocator/move.cc (test01): Add

4298

+ check on a vector iterator.

4299

+ * testsuite/23_containers/vector/allocator/move_assign.cc

4300

+ (test02): Likewise.

4301

+ (test03): New, test with a non-propagating allocator.

4302

+

4303

+ 2013-11-15 Jonathan Wakely <jwakely.gcc@gmail.com>

4304

+

4305

+ * testsuite/23_containers/vector/allocator/move.cc: New

4306

+

4307

+2014-01-27 Jason Merrill <jason@redhat.com>

4308

+

4309

+ Core DR 475

4310

+ PR c++/41174

4311

+ PR c++/59224

4312

+ * libsupc++/eh_throw.cc (__cxa_throw): Set uncaughtExceptions.

4313

+ * libsupc++/eh_alloc.cc (__cxa_allocate_dependent_exception)

4314

+ (__cxa_allocate_exception): Don't set it here.

4315

+

4316

+2013-12-15 H.J. Lu <hongjiu.lu@intel.com>

4317

+

4318

+ * config/abi/post/x86_64-linux-gnu/x32/baseline_symbols.txt: Update.

4319

+

4320

+2013-11-22 Jonathan Wakely <jwakely.gcc@gmail.com>

4321

+

4322

+ * acinclude.m4 (libtool_VERSION): Bump.

4323

+ * configure: Regenerate.

4324

+ * doc/xml/manual/abi.xml: Update version information.

4325

+

4326

+2013-11-05 Jonathan Wakely <jwakely.gcc@gmail.com>

4327

+

4328

+ * doc/xml/manual/status_cxx2011.xml: Document aligned_union as

4329

+ missing.

4330

+

4331

+ * doc/xml/manual/spine.xml: Update copyright years.

4332

+ * doc/html/*: Regenerate.

4333

+

4334

+2013-11-01 Paolo Carlini <paolo.carlini@oracle.com>

4335

+

4336

+ PR libstdc++/58952

4337

+ * include/c_global/cstdio: Undef getchar.

4338

+

4339

+2013-10-31 Jonathan Wakely <jwakely.gcc@gmail.com>

4340

+

4341

+ * testsuite/20_util/shared_ptr/cons/58839.cc: Do not use

4342

+ default_delete<void>.

4343

+

4344

+2013-10-30 Chris Studholme <cvs@cs.utoronto.ca>

4345

+

4346

+ PR libstdc++/58912

4347

+ * include/bits/shared_ptr_base.h (_Sp_counted_ptr_inplace): Remove

4348

+ unnecessary initialization of storage buffer.

4349

+

4350

+2013-10-29 Jonathan Wakely <jwakely.gcc@gmail.com>

4351

+

4352

+ PR libstdc++/58839

4353

+ * include/bits/shared_ptr_base.h

4354

+ (__shared_ptr<T>::__shared_ptr(unique_ptr<U,D>&&)): Do not dereference

4355

+ pointer.

4356

+ * testsuite/20_util/shared_ptr/cons/58839.cc: New.

4357

+

4358

+2013-10-20 Chris Jefferson <chris@bubblescope.net>

4359

+ Paolo Carlini <paolo.carlini@oracle.com>

4360

+

4361

+ PR libstdc++/58800

4362

+ * include/bits/stl_algo.h (__unguarded_partition_pivot): Change

4363

+ __last - 2 to __last - 1.

4364

+ * testsuite/25_algorithms/nth_element/58800.cc: New

4365

+

4366

+2013-10-16 François Dumont <fdumont@gcc.gnu.org>

4367

+

4368

+ PR libstdc++/58191

4369

+ * include/debug/macros.h (__glibcxx_check_partitioned_lower): Add

4370

+ __gnu_debug::__base calls on iterators passed to internal debug

4371

+ check.

4372

+ (__glibcxx_check_partitioned_lower_pred): Likewise.

4373

+ (__glibcxx_check_partitioned_upper): Likewise.

4374

+ (__glibcxx_check_partitioned_upper_pred): Likewise.

4375

+ * include/debug/functions.h (__check_partitioned_lower):

4376

+ Remove code to detect safe iterators.

4377

+ (__check_partitioned_upper): Likewise.

4378

+

4379

2013-10-16 Release Manager

4380

4381

* GCC 4.8.2 released.

4382

Index: libstdc++-v3/libsupc++/eh_call.cc

4383

===================================================================

4384

--- a/src/libstdc++-v3/libsupc++/eh_call.cc (.../tags/gcc_4_8_2_release)

4385

+++ b/src/libstdc++-v3/libsupc++/eh_call.cc (.../branches/gcc-4_8-branch)

4386

@@ -104,14 +104,14 @@

4387

} end_catch_protect_obj;

4388

4389

4390

- __try

4391

- {

4392

+ __try

4393

+ {

4394

if (foreign_exception)

4395

std::unexpected();

4396

else

4397

__unexpected(unexpectedHandler);

4398

}

4399

- __catch(...)

4400

+ __catch(...)

4401

{

4402

/* See if the new exception matches the rtti list. */

4403

if (foreign_exception)

4404

@@ -140,15 +140,19 @@

4405

&new_ptr) != ctm_failed)

4406

__throw_exception_again;

4407

4408

- if (catch_type->__do_catch(&bad_exc, 0, 1))

4409

+ // If the exception spec allows std::bad_exception, throw that.

4410

+ // We don't have a thrown object to compare against, but since

4411

+ // bad_exception doesn't have virtual bases, that's OK; just pass NULL.

4412

+ void* obj = NULL;

4413

+ if (catch_type->__do_catch(&bad_exc, &obj, 1))

4414

bad_exception_allowed = true;

4415

}

4416

4417

// If the exception spec allows std::bad_exception, throw that.

4418

-#ifdef __EXCEPTIONS

4419

+#ifdef __EXCEPTIONS

4420

if (bad_exception_allowed)

4421

throw std::bad_exception();

4422

-#endif

4423

+#endif

4424

4425

// Otherwise, die.

4426

__terminate(terminateHandler);

4427

Index: libstdc++-v3/libsupc++/eh_alloc.cc

4428

===================================================================

4429

--- a/src/libstdc++-v3/libsupc++/eh_alloc.cc (.../tags/gcc_4_8_2_release)

4430

+++ b/src/libstdc++-v3/libsupc++/eh_alloc.cc (.../branches/gcc-4_8-branch)

4431

@@ -129,12 +129,6 @@

4432

std::terminate ();

4433

}

4434

4435

- // We have an uncaught exception as soon as we allocate memory. This

4436

- // yields uncaught_exception() true during the copy-constructor that

4437

- // initializes the exception object. See Issue 475.

4438

- __cxa_eh_globals *globals = __cxa_get_globals ();

4439

- globals->uncaughtExceptions += 1;

4440

-

4441

memset (ret, 0, sizeof (__cxa_refcounted_exception));

4442

4443

return (void *)((char *)ret + sizeof (__cxa_refcounted_exception));

4444

@@ -191,12 +185,6 @@

4445

std::terminate ();

4446

}

4447

4448

- // We have an uncaught exception as soon as we allocate memory. This

4449

- // yields uncaught_exception() true during the copy-constructor that

4450

- // initializes the exception object. See Issue 475.

4451

- __cxa_eh_globals *globals = __cxa_get_globals ();

4452

- globals->uncaughtExceptions += 1;

4453

-

4454

memset (ret, 0, sizeof (__cxa_dependent_exception));

4455

4456

return ret;

4457

Index: libstdc++-v3/libsupc++/eh_throw.cc

4458

===================================================================

4459

--- a/src/libstdc++-v3/libsupc++/eh_throw.cc (.../tags/gcc_4_8_2_release)

4460

+++ b/src/libstdc++-v3/libsupc++/eh_throw.cc (.../branches/gcc-4_8-branch)

4461

@@ -62,6 +62,9 @@

4462

{

4463

PROBE2 (throw, obj, tinfo);

4464

4465

+ __cxa_eh_globals *globals = __cxa_get_globals ();

4466

+ globals->uncaughtExceptions += 1;

4467

+

4468

// Definitely a primary.

4469

__cxa_refcounted_exception *header

4470

= __get_refcounted_exception_header_from_obj (obj);

4471

Index: libstdc++-v3/testsuite/25_algorithms/nth_element/58800.cc

4472

===================================================================

4473

--- a/src/libstdc++-v3/testsuite/25_algorithms/nth_element/58800.cc (.../tags/gcc_4_8_2_release)

4474

+++ b/src/libstdc++-v3/testsuite/25_algorithms/nth_element/58800.cc (.../branches/gcc-4_8-branch)

4475

@@ -0,0 +1,52 @@

4476

4477

+//

4478

+// This file is part of the GNU ISO C++ Library. This library is free

4479

+// software; you can redistribute it and/or modify it under the

4480

+// terms of the GNU General Public License as published by the

4481

+// Free Software Foundation; either version 3, or (at your option)

4482

+// any later version.

4483

+

4484

+// This library is distributed in the hope that it will be useful,

4485

+// but WITHOUT ANY WARRANTY; without even the implied warranty of

4486

+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

4487

+// GNU General Public License for more details.

4488

+

4489

+// You should have received a copy of the GNU General Public License along

4490

+// with this library; see the file COPYING3. If not see

4491

+// <http://www.gnu.org/licenses/>.

4492

+

4493

+// 25.3.2 [lib.alg.nth.element]

4494

+

4495

+// { dg-options "-std=gnu++11" }

4496

+

4497

+#include <algorithm>

4498

+#include <testsuite_hooks.h>

4499

+#include <testsuite_iterators.h>

4500

+

4501

+using __gnu_test::test_container;

4502

+using __gnu_test::random_access_iterator_wrapper;

4503

+

4504

+typedef test_container<int, random_access_iterator_wrapper> Container;

4505

+

4506

+void test01()

4507

+{

4508

+ std::vector<int> v = {

4509

+ 207089,

4510

+ 202585,

4511

+ 180067,

4512

+ 157549,

4513

+ 211592,

4514

+ 216096,

4515

+ 207089

4516

+ };

4517

+

4518

+ Container con(v.data(), v.data() + 7);

4519

+

4520

+ std::nth_element(con.begin(), con.begin() + 3, con.end());

4521

+}

4522

+

4523

+int main()

4524

+{

4525

+ test01();

4526

+ return 0;

4527

+}

4528

Index: libstdc++-v3/testsuite/18_support/bad_exception/59392.cc

4529

===================================================================

4530

--- a/src/libstdc++-v3/testsuite/18_support/bad_exception/59392.cc (.../tags/gcc_4_8_2_release)

4531

+++ b/src/libstdc++-v3/testsuite/18_support/bad_exception/59392.cc (.../branches/gcc-4_8-branch)

4532

@@ -0,0 +1,51 @@

4533

4534

+//

4535

+// This file is part of the GNU ISO C++ Library. This library is free

4536

+// software; you can redistribute it and/or modify it under the

4537

+// terms of the GNU General Public License as published by the

4538

+// Free Software Foundation; either version 3, or (at your option)

4539

+// any later version.

4540

+

4541

+// This library is distributed in the hope that it will be useful,

4542

+// but WITHOUT ANY WARRANTY; without even the implied warranty of

4543

+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

4544

+// GNU General Public License for more details.

4545

+

4546

+// You should have received a copy of the GNU General Public License along

4547

+// with this library; see the file COPYING3. If not see

4548

+// <http://www.gnu.org/licenses/>.

4549

+

4550

+#include <exception>

4551

+#include <cstdlib>

4552

+

4553

+class expected {};

4554

+class unexpected {};

4555

+class from_handler {};

4556

+

4557

+static void func_with_exception_spec() throw(expected)

4558

+{

4559

+ throw unexpected();

4560

+}

4561

+

4562

+static void unexpected_handler()

4563

+{

4564

+ throw from_handler();

4565

+}

4566

+

4567

+static void terminate_handler()

4568

+{

4569

+ exit(0);

4570

+}

4571

+

4572

+// libstdc++/59392

4573

+int main()

4574

+{

4575

+ std::set_unexpected(unexpected_handler);

4576

+ std::set_terminate(terminate_handler);

4577

+ try {

4578

+ func_with_exception_spec();

4579

+ } catch (expected&) {

4580

+ abort();

4581

+ }

4582

+ abort();

4583

+}

4584

4585

Property changes on: libstdc++-v3/testsuite/18_support/bad_exception/59392.cc

4586

___________________________________________________________________

4587

Added: svn:eol-style

4588

## -0,0 +1 ##

4589

+LF

4590

\ No newline at end of property

4591

Index: libstdc++-v3/testsuite/30_threads/packaged_task/60564.cc

4592

===================================================================

4593

--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/60564.cc (.../tags/gcc_4_8_2_release)

4594

+++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/60564.cc (.../branches/gcc-4_8-branch)

4595

@@ -0,0 +1,51 @@

4596

+// { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-gnu* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } }

4597

+// { dg-options " -std=gnu++11 -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-gnu* powerpc-ibm-aix* } }

4598

+// { dg-options " -std=gnu++11 -pthreads" { target *-*-solaris* } }

4599

+// { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-darwin* } }

4600

+// { dg-require-cstdint "" }

4601

+// { dg-require-gthreads "" }

4602

+// { dg-require-atomic-builtins "" }

4603

+

4604

4605

+//

4606

+// This file is part of the GNU ISO C++ Library. This library is free

4607

+// software; you can redistribute it and/or modify it under the

4608

+// terms of the GNU General Public License as published by the

4609

+// Free Software Foundation; either version 3, or (at your option)

4610

+// any later version.

4611

+

4612

+// This library is distributed in the hope that it will be useful,

4613

+// but WITHOUT ANY WARRANTY; without even the implied warranty of

4614

+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

4615

+// GNU General Public License for more details.

4616

+

4617

+// You should have received a copy of the GNU General Public License along

4618

+// with this library; see the file COPYING3. If not see

4619

+// <http://www.gnu.org/licenses/>.

4620

+

4621

+

4622

+#include <future>

4623

+#include <testsuite_hooks.h>

4624

+

4625

+struct X

4626

+{

4627

+ X() = default;

4628

+ X(const X&) = default;

4629

+ X(X&& x) { x.moved = true; }

4630

+

4631

+ void operator()() const { }

4632

+

4633

+ bool moved = false;

4634

+};

4635

+

4636

+void test01()

4637

+{

4638

+ X x;

4639

+ std::packaged_task<void()> p(x);

4640

+ VERIFY( !x.moved );

4641

+}

4642

+

4643

+int main()

4644

+{

4645

+ test01();

4646

+}

4647

Index: libstdc++-v3/testsuite/30_threads/condition_variable/54185.cc

4648

===================================================================

4649

--- a/src/libstdc++-v3/testsuite/30_threads/condition_variable/54185.cc (.../tags/gcc_4_8_2_release)

4650

+++ b/src/libstdc++-v3/testsuite/30_threads/condition_variable/54185.cc (.../branches/gcc-4_8-branch)

4651

@@ -1,11 +1,11 @@

4652

-// { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } }

4653

-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } }

4654

+// { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-gnu* *-*-solaris* *-*-cygwin *-*-darwin1[1-9]* powerpc-ibm-aix* } }

4655

+// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-gnu* powerpc-ibm-aix* } }

4656

// { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } }

4657

// { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } }

4658

// { dg-require-cstdint "" }

4659

// { dg-require-gthreads "" }

4660

4661

4662

4663

//

4664

// This file is part of the GNU ISO C++ Library. This library is free

4665

// software; you can redistribute it and/or modify it under the

4666

Index: libstdc++-v3/testsuite/29_atomics/atomic/60658.cc

4667

===================================================================

4668

--- a/src/libstdc++-v3/testsuite/29_atomics/atomic/60658.cc (.../tags/gcc_4_8_2_release)

4669

+++ b/src/libstdc++-v3/testsuite/29_atomics/atomic/60658.cc (.../branches/gcc-4_8-branch)

4670

@@ -0,0 +1,43 @@

4671

+// { dg-require-atomic-builtins "" }

4672

+// { dg-options "-std=gnu++11" }

4673

+

4674

4675

+//

4676

+// This file is part of the GNU ISO C++ Library. This library is free

4677

+// software; you can redistribute it and/or modify it under the

4678

+// terms of the GNU General Public License as published by the

4679

+// Free Software Foundation; either version 3, or (at your option)

4680

+// any later version.

4681

+

4682

+// This library is distributed in the hope that it will be useful,

4683

+// but WITHOUT ANY WARRANTY; without even the implied warranty of

4684

+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

4685

+// GNU General Public License for more details.

4686

+

4687

+// You should have received a copy of the GNU General Public License along

4688

+// with this library; see the file COPYING3. If not see

4689

+// <http://www.gnu.org/licenses/>.

4690

+

4691

+#include <atomic>

4692

+#include <testsuite_hooks.h>

4693

+

4694

+// libstdc++/60658

4695

+

4696

+struct Foo {

4697

+ char buf[1];

4698

+};

4699

+

4700

+struct Bar {

4701

+ char buf[100];

4702

+};

4703

+

4704

+int

4705

+main ()

4706

+{

4707

+ bool test __attribute__((unused)) = true;

4708

+

4709

+ std::atomic<Foo*> a;

4710

+ std::atomic<Bar*> b;

4711

+

4712

+ VERIFY (a.is_lock_free() == b.is_lock_free());

4713

+}

4714

Index: libstdc++-v3/testsuite/23_containers/unordered_map/59548.cc

4715

===================================================================

4716

--- a/src/libstdc++-v3/testsuite/23_containers/unordered_map/59548.cc (.../tags/gcc_4_8_2_release)

4717

+++ b/src/libstdc++-v3/testsuite/23_containers/unordered_map/59548.cc (.../branches/gcc-4_8-branch)

4718

@@ -0,0 +1,34 @@

4719

+// { dg-options "-std=gnu++11" }

4720

+// { dg-do compile }

4721

+// { dg-require-debug-mode "" }

4722

+

4723

4724

+//

4725

+// This file is part of the GNU ISO C++ Library. This library is free

4726

+// software; you can redistribute it and/or modify it under the

4727

+// terms of the GNU General Public License as published by the

4728

+// Free Software Foundation; either version 3, or (at your option)

4729

+// any later version.

4730

+

4731

+// This library is distributed in the hope that it will be useful,

4732

+// but WITHOUT ANY WARRANTY; without even the implied warranty of

4733

+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

4734

+// GNU General Public License for more details.

4735

+

4736

+// You should have received a copy of the GNU General Public License along

4737

+// with this library; see the file COPYING3. If not see

4738

+// <http://www.gnu.org/licenses/>.

4739

+

4740

+// libstdc++/59548

4741

+

4742

+#include <unordered_map>

4743

+

4744

+int main()

4745

+{

4746

+ std::unordered_map<int,int> foo{ {0,1} };

4747

+ auto i = foo.begin();

4748

+ {

4749

+ auto bar = foo;

4750

+ }

4751

+ return i->first;

4752

+}

4753

Index: libstdc++-v3/testsuite/23_containers/vector/allocator/move.cc

4754

===================================================================

4755

--- a/src/libstdc++-v3/testsuite/23_containers/vector/allocator/move.cc (.../tags/gcc_4_8_2_release)

4756

+++ b/src/libstdc++-v3/testsuite/23_containers/vector/allocator/move.cc (.../branches/gcc-4_8-branch)

4757

@@ -0,0 +1,59 @@

4758

4759

+//

4760

+// This file is part of the GNU ISO C++ Library. This library is free

4761

+// software; you can redistribute it and/or modify it under the

4762

+// terms of the GNU General Public License as published by the

4763

+// Free Software Foundation; either version 3, or (at your option)

4764

+// any later version.

4765

+

4766

+// This library is distributed in the hope that it will be useful,

4767

+// but WITHOUT ANY WARRANTY; without even the implied warranty of

4768

+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

4769

+// GNU General Public License for more details.

4770

+

4771

+// You should have received a copy of the GNU General Public License along

4772

+// with this library; see the file COPYING3. If not see

4773

+// <http://www.gnu.org/licenses/>.

4774

+

4775

+// { dg-options "-std=gnu++11" }

4776

+

4777

+#include <vector>

4778

+#include <testsuite_hooks.h>

4779

+#include <testsuite_allocator.h>

4780

+

4781

+struct T { int i; };

4782

+

4783

+using __gnu_test::uneq_allocator;

4784

+

4785

+void test01()

4786

+{

4787

+ bool test __attribute__((unused)) = true;

4788

+ typedef uneq_allocator<T> alloc_type;

4789

+ typedef std::vector<T, alloc_type> test_type;

4790

+ test_type v1(alloc_type(1));

4791

+ v1 = { T() };

4792

+ auto it = v1.begin();

4793

+ test_type v2(std::move(v1));

4794

+ VERIFY(1 == v1.get_allocator().get_personality());

4795

+ VERIFY(1 == v2.get_allocator().get_personality());

4796

+ VERIFY( it == v2.begin() );

4797

+}

4798

+

4799

+void test02()

4800

+{

4801

+ bool test __attribute__((unused)) = true;

4802

+ typedef uneq_allocator<T> alloc_type;

4803

+ typedef std::vector<T, alloc_type> test_type;

4804

+ test_type v1(alloc_type(1));

4805

+ v1 = { T() };

4806

+ test_type v2(std::move(v1), alloc_type(2));

4807

+ VERIFY(1 == v1.get_allocator().get_personality());

4808

+ VERIFY(2 == v2.get_allocator().get_personality());

4809

+}

4810

+

4811

+int main()

4812

+{

4813

+ test01();

4814

+ test02();

4815

+ return 0;

4816

+}

4817

Index: libstdc++-v3/testsuite/23_containers/vector/allocator/move_assign.cc

4818

===================================================================

4819

--- a/src/libstdc++-v3/testsuite/23_containers/vector/allocator/move_assign.cc (.../tags/gcc_4_8_2_release)

4820

+++ b/src/libstdc++-v3/testsuite/23_containers/vector/allocator/move_assign.cc (.../branches/gcc-4_8-branch)

4821

@@ -46,16 +46,35 @@

4822

typedef std::vector<T, alloc_type> test_type;

4823

test_type v1(alloc_type(1));

4824

v1.push_back(T());

4825

+ auto it = v1.begin();

4826

test_type v2(alloc_type(2));

4827

+ v2.push_back(T());

4828

v2 = std::move(v1);

4829

- v2.push_back(T());

4830

+ VERIFY( it == v2.begin() );

4831

VERIFY(0 == v1.get_allocator().get_personality());

4832

VERIFY(1 == v2.get_allocator().get_personality());

4833

}

4834

4835

+void test03()

4836

+{

4837

+ bool test __attribute__((unused)) = true;

4838

+ typedef propagating_allocator<T, false> alloc_type;

4839

+ typedef std::vector<T, alloc_type> test_type;

4840

+ test_type v1(alloc_type(1));

4841

+ v1.push_back(T());

4842

+ auto it = v1.begin();

4843

+ test_type v2(alloc_type(1));

4844

+ v2.push_back(T());

4845

+ v2 = std::move(v1);

4846

+ VERIFY( it == v2.begin() );

4847

+ VERIFY(1 == v1.get_allocator().get_personality());

4848

+ VERIFY(1 == v2.get_allocator().get_personality());

4849

+}

4850

+

4851

int main()

4852

{

4853

test01();

4854

test02();

4855

+ test03();

4856

return 0;

4857

}

4858

Index: libstdc++-v3/testsuite/20_util/tuple/60497.cc

4859

===================================================================

4860

--- a/src/libstdc++-v3/testsuite/20_util/tuple/60497.cc (.../tags/gcc_4_8_2_release)

4861

+++ b/src/libstdc++-v3/testsuite/20_util/tuple/60497.cc (.../branches/gcc-4_8-branch)

4862

@@ -0,0 +1,35 @@

4863

+// { dg-options "-std=gnu++11" }

4864

+// { dg-do compile }

4865

+

4866

4867

+//

4868

+// This file is part of the GNU ISO C++ Library. This library is free

4869

+// software; you can redistribute it and/or modify it under the

4870

+// terms of the GNU General Public License as published by the

4871

+// Free Software Foundation; either version 3, or (at your option)

4872

+// any later version.

4873

+

4874

+// This library is distributed in the hope that it will be useful,

4875

+// but WITHOUT ANY WARRANTY; without even the implied warranty of

4876

+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

4877

+// GNU General Public License for more details.

4878

+

4879

+// You should have received a copy of the GNU General Public License along

4880

+// with this library; see the file COPYING3. If not see

4881

+// <http://www.gnu.org/licenses/>.

4882

+

4883

+// libstdc++/60497

4884

+

4885

+#include <tuple>

4886

+

4887

+struct A;

4888

+template<typename T> struct B { T t; };

4889

+

4890

+using element_type = B<A>*;

4891

+using tuple_type = std::tuple<element_type>;

4892

+

4893

+tuple_type t;

4894

+const tuple_type ct;

4895

+

4896

+auto a = std::get<0>(t);

4897

+auto b = std::get<0>(ct);

4898

Index: libstdc++-v3/testsuite/20_util/shared_ptr/cons/58839.cc

4899

===================================================================

4900

--- a/src/libstdc++-v3/testsuite/20_util/shared_ptr/cons/58839.cc (.../tags/gcc_4_8_2_release)

4901

+++ b/src/libstdc++-v3/testsuite/20_util/shared_ptr/cons/58839.cc (.../branches/gcc-4_8-branch)

4902

@@ -0,0 +1,33 @@

4903

+// { dg-options "-std=gnu++11" }

4904

+// { dg-do compile }

4905

+

4906

4907

+//

4908

+// This file is part of the GNU ISO C++ Library. This library is free

4909

+// software; you can redistribute it and/or modify it under the

4910

+// terms of the GNU General Public License as published by the

4911

+// Free Software Foundation; either version 3, or (at your option)

4912

+// any later version.

4913

+

4914

+// This library is distributed in the hope that it will be useful,

4915

+// but WITHOUT ANY WARRANTY; without even the implied warranty of

4916

+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

4917

+// GNU General Public License for more details.

4918

+

4919

+// You should have received a copy of the GNU General Public License along

4920

+// with this library; see the file COPYING3. If not see

4921

+// <http://www.gnu.org/licenses/>.

4922

+

4923

+#include <memory>

4924

+

4925

+// libstdc++/58839

4926

+

4927

+struct D {

4928

+ void operator()(void*) const noexcept { }

4929

+};

4930

+

4931

+void test01()

4932

+{

4933

+ std::unique_ptr<void, D> y;

4934

+ std::shared_ptr<void> x = std::move(y);

4935

+}

4936

Index: libstdc++-v3/testsuite/20_util/function/60594.cc

4937

===================================================================

4938

--- a/src/libstdc++-v3/testsuite/20_util/function/60594.cc (.../tags/gcc_4_8_2_release)

4939

+++ b/src/libstdc++-v3/testsuite/20_util/function/60594.cc (.../branches/gcc-4_8-branch)

4940

@@ -0,0 +1,36 @@

4941

+// { dg-options "-std=gnu++11" }

4942

+// { dg-do compile }

4943

+

4944

4945

+//

4946

+// This file is part of the GNU ISO C++ Library. This library is free

4947

+// software; you can redistribute it and/or modify it under the

4948

+// terms of the GNU General Public License as published by the

4949

+// Free Software Foundation; either version 3, or (at your option)

4950

+// any later version.

4951

+//

4952

+// This library is distributed in the hope that it will be useful,

4953

+// but WITHOUT ANY WARRANTY; without even the implied warranty of

4954

+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

4955

+// GNU General Public License for more details.

4956

+//

4957

+// You should have received a copy of the GNU General Public License along

4958

+// with this library; see the file COPYING3. If not see

4959

+// <http://www.gnu.org/licenses/>.

4960

+

4961

+// libstdc++/60594

4962

+

4963

+#include <functional>

4964

+#include <type_traits>

4965

+struct bar;

4966

+using F = std::function<bar()>;

4967

+// check for copy constructible and assignable while 'bar' is incomplete

4968

+constexpr int c = std::is_copy_constructible<F>::value;

4969

+constexpr int a = std::is_copy_assignable<F>::value;

4970

+struct bar { };

4971

+bar func();

4972

+void test()

4973

+{

4974

+ F g{ &func };

4975

+ g = func;

4976

+}

4977

Index: libstdc++-v3/testsuite/20_util/bind/57899.cc

4978

===================================================================

4979

--- a/src/libstdc++-v3/testsuite/20_util/bind/57899.cc (.../tags/gcc_4_8_2_release)

4980

+++ b/src/libstdc++-v3/testsuite/20_util/bind/57899.cc (.../branches/gcc-4_8-branch)

4981

@@ -0,0 +1,48 @@

4982

4983

+//

4984

+// This file is part of the GNU ISO C++ Library. This library is free

4985

+// software; you can redistribute it and/or modify it under the

4986

+// terms of the GNU General Public License as published by the

4987

+// Free Software Foundation; either version 3, or (at your option)

4988

+// any later version.

4989

+

4990

+// This library is distributed in the hope that it will be useful,

4991

+// but WITHOUT ANY WARRANTY; without even the implied warranty of

4992

+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

4993

+// GNU General Public License for more details.

4994

+

4995

+// You should have received a copy of the GNU General Public License along

4996

+// with this library; see the file COPYING3. If not see

4997

+// <http://www.gnu.org/licenses/>.

4998

+

4999

+// 20.7.11 Function template bind

5000

+

5001

+// PR c++/57899

5002

+// { dg-do compile }

5003

+// { dg-options -std=c++11 }

5004

+

5005

+#include <functional>

5006

+using std::bind;

5007

+using std::placeholders::_1;

5008

+

5009

+struct S { int i; };

5010

+

5011

+struct P { S s; };

5012

+

5013

+struct get_s

5014

+{

5015

+ const S& operator()(const P& p) const { return p.s; }

5016

+} gs;

5017

+

5018

+int gi(const S& s) { return s.i; }

5019

+

5020

+bool cmp(int, int) { return true; }

5021

+

5022

+int main()

5023

+{

5024

+ P p{};

5025

+ auto f1 = bind(gs, _1);

5026

+ auto f2 = bind(gi, f1);

5027

+ auto f3 = bind(cmp, f2, 5);

5028

+ f3(p);

5029

+}

5030

Index: libstdc++-v3/config/abi/post/x86_64-linux-gnu/x32/baseline_symbols.txt

5031

===================================================================

5032

--- a/src/libstdc++-v3/config/abi/post/x86_64-linux-gnu/x32/baseline_symbols.txt (.../tags/gcc_4_8_2_release)

5033

+++ b/src/libstdc++-v3/config/abi/post/x86_64-linux-gnu/x32/baseline_symbols.txt (.../branches/gcc-4_8-branch)

5034

@@ -403,6 +403,7 @@

5035

FUNC:_ZNKSt15basic_streambufIwSt11char_traitsIwEE6getlocEv@@GLIBCXX_3.4

5036

FUNC:_ZNKSt15basic_stringbufIcSt11char_traitsIcESaIcEE3strEv@@GLIBCXX_3.4

5037

FUNC:_ZNKSt15basic_stringbufIwSt11char_traitsIwESaIwEE3strEv@@GLIBCXX_3.4

5038

+FUNC:_ZNKSt17bad_function_call4whatEv@@GLIBCXX_3.4.18

5039

FUNC:_ZNKSt18basic_stringstreamIcSt11char_traitsIcESaIcEE3strEv@@GLIBCXX_3.4

5040

FUNC:_ZNKSt18basic_stringstreamIcSt11char_traitsIcESaIcEE5rdbufEv@@GLIBCXX_3.4

5041

FUNC:_ZNKSt18basic_stringstreamIwSt11char_traitsIwESaIwEE3strEv@@GLIBCXX_3.4

5042

@@ -590,6 +591,8 @@

5043

FUNC:_ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES3_RSt8ios_basewm@@GLIBCXX_3.4

5044

FUNC:_ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES3_RSt8ios_basewx@@GLIBCXX_3.4

5045

FUNC:_ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES3_RSt8ios_basewy@@GLIBCXX_3.4

5046

+FUNC:_ZNKSt8__detail20_Prime_rehash_policy11_M_next_bktEj@@GLIBCXX_3.4.18

5047

+FUNC:_ZNKSt8__detail20_Prime_rehash_policy14_M_need_rehashEjjj@@GLIBCXX_3.4.18

5048

FUNC:_ZNKSt8bad_cast4whatEv@@GLIBCXX_3.4.9

5049

FUNC:_ZNKSt8ios_base7failure4whatEv@@GLIBCXX_3.4

5050

FUNC:_ZNKSt8messagesIcE18_M_convert_to_charERKSs@@GLIBCXX_3.4

5051

@@ -1207,6 +1210,7 @@

5052

FUNC:_ZNSt11regex_errorD0Ev@@GLIBCXX_3.4.15

5053

FUNC:_ZNSt11regex_errorD1Ev@@GLIBCXX_3.4.15

5054

FUNC:_ZNSt11regex_errorD2Ev@@GLIBCXX_3.4.15

5055

+FUNC:_ZNSt11this_thread11__sleep_forENSt6chrono8durationIxSt5ratioILx1ELx1EEEENS1_IxS2_ILx1ELx1000000000EEEE@@GLIBCXX_3.4.18

5056

FUNC:_ZNSt12__basic_fileIcE2fdEv@@GLIBCXX_3.4

5057

FUNC:_ZNSt12__basic_fileIcE4fileEv@@GLIBCXX_3.4.1

5058

FUNC:_ZNSt12__basic_fileIcE4openEPKcSt13_Ios_Openmodei@@GLIBCXX_3.4

5059

@@ -1485,6 +1489,11 @@

5060

FUNC:_ZNSt13basic_ostreamIwSt11char_traitsIwEElsEt@@GLIBCXX_3.4

5061

FUNC:_ZNSt13basic_ostreamIwSt11char_traitsIwEElsEx@@GLIBCXX_3.4

5062

FUNC:_ZNSt13basic_ostreamIwSt11char_traitsIwEElsEy@@GLIBCXX_3.4

5063

+FUNC:_ZNSt13random_device14_M_init_pretr1ERKSs@@GLIBCXX_3.4.18

5064

+FUNC:_ZNSt13random_device16_M_getval_pretr1Ev@@GLIBCXX_3.4.18

5065

+FUNC:_ZNSt13random_device7_M_finiEv@@GLIBCXX_3.4.18

5066

+FUNC:_ZNSt13random_device7_M_initERKSs@@GLIBCXX_3.4.18

5067

+FUNC:_ZNSt13random_device9_M_getvalEv@@GLIBCXX_3.4.18

5068

FUNC:_ZNSt13runtime_errorC1ERKSs@@GLIBCXX_3.4

5069

FUNC:_ZNSt13runtime_errorC2ERKSs@@GLIBCXX_3.4

5070

FUNC:_ZNSt13runtime_errorD0Ev@@GLIBCXX_3.4

5071

@@ -1929,6 +1938,8 @@

5072

FUNC:_ZNSt6__norm15_List_node_base8transferEPS0_S1_@@GLIBCXX_3.4.9

5073

FUNC:_ZNSt6__norm15_List_node_base9_M_unhookEv@@GLIBCXX_3.4.14

5074

FUNC:_ZNSt6chrono12system_clock3nowEv@@GLIBCXX_3.4.11

5075

+FUNC:_ZNSt6chrono3_V212steady_clock3nowEv@@GLIBCXX_3.4.19

5076

+FUNC:_ZNSt6chrono3_V212system_clock3nowEv@@GLIBCXX_3.4.19

5077

FUNC:_ZNSt6gslice8_IndexerC1EjRKSt8valarrayIjES4_@@GLIBCXX_3.4

5078

FUNC:_ZNSt6gslice8_IndexerC2EjRKSt8valarrayIjES4_@@GLIBCXX_3.4

5079

FUNC:_ZNSt6locale11_M_coalesceERKS_S1_i@@GLIBCXX_3.4

5080

@@ -2467,6 +2478,7 @@

5081

FUNC:__cxa_guard_release@@CXXABI_1.3

5082

FUNC:__cxa_pure_virtual@@CXXABI_1.3

5083

FUNC:__cxa_rethrow@@CXXABI_1.3

5084

+FUNC:__cxa_thread_atexit@@CXXABI_1.3.7

5085

FUNC:__cxa_throw@@CXXABI_1.3

5086

FUNC:__cxa_tm_cleanup@@CXXABI_TM_1

5087

FUNC:__cxa_vec_cctor@@CXXABI_1.3

5088

@@ -2491,6 +2503,7 @@

5089

OBJECT:0:CXXABI_1.3.4

5090

OBJECT:0:CXXABI_1.3.5

5091

OBJECT:0:CXXABI_1.3.6

5092

+OBJECT:0:CXXABI_1.3.7

5093

OBJECT:0:CXXABI_TM_1

5094

OBJECT:0:GLIBCXX_3.4

5095

OBJECT:0:GLIBCXX_3.4.1

5096

@@ -2502,6 +2515,8 @@

5097

OBJECT:0:GLIBCXX_3.4.15

5098

OBJECT:0:GLIBCXX_3.4.16

5099

OBJECT:0:GLIBCXX_3.4.17

5100

+OBJECT:0:GLIBCXX_3.4.18

5101

+OBJECT:0:GLIBCXX_3.4.19

5102

OBJECT:0:GLIBCXX_3.4.2

5103

OBJECT:0:GLIBCXX_3.4.3

5104

OBJECT:0:GLIBCXX_3.4.4

5105

@@ -3033,6 +3048,8 @@

5106

OBJECT:1:_ZNSt21__numeric_limits_base9is_moduloE@@GLIBCXX_3.4

5107

OBJECT:1:_ZNSt21__numeric_limits_base9is_signedE@@GLIBCXX_3.4

5108

OBJECT:1:_ZNSt6chrono12system_clock12is_monotonicE@@GLIBCXX_3.4.11

5109

+OBJECT:1:_ZNSt6chrono3_V212steady_clock9is_steadyE@@GLIBCXX_3.4.19

5110

+OBJECT:1:_ZNSt6chrono3_V212system_clock9is_steadyE@@GLIBCXX_3.4.19

5111

OBJECT:1:_ZSt10adopt_lock@@GLIBCXX_3.4.11

5112

OBJECT:1:_ZSt10defer_lock@@GLIBCXX_3.4.11

5113

OBJECT:1:_ZSt11try_to_lock@@GLIBCXX_3.4.11

5114

Index: libstdc++-v3/acinclude.m4

5115

===================================================================

5116

--- a/src/libstdc++-v3/acinclude.m4 (.../tags/gcc_4_8_2_release)

5117

+++ b/src/libstdc++-v3/acinclude.m4 (.../branches/gcc-4_8-branch)

5118

@@ -3266,7 +3266,7 @@

5119

fi

5120

5121

# For libtool versioning info, format is CURRENT:REVISION:AGE

5122

-libtool_VERSION=6:18:0

5123

+libtool_VERSION=6:19:0

5124

5125

# Everything parsed; figure out what files and settings to use.

5126

case $enable_symvers in

5127

Index: libmudflap/configure

5128

===================================================================

5129

--- a/src/libmudflap/configure (.../tags/gcc_4_8_2_release)

5130

+++ b/src/libmudflap/configure (.../branches/gcc-4_8-branch)

5131

@@ -6377,7 +6377,7 @@

5132

rm -rf conftest*

5133

;;

5134

5135

-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \

5136

+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \

5137

s390*-*linux*|s390*-*tpf*|sparc*-*linux*)

5138

# Find out which ABI we are using.

5139

echo 'int i;' > conftest.$ac_ext

5140

@@ -6402,7 +6402,10 @@

5141

;;

5142

esac

5143

;;

5144

- ppc64-*linux*|powerpc64-*linux*)

5145

+ powerpc64le-*linux*)

5146

+ LD="${LD-ld} -m elf32lppclinux"

5147

+ ;;

5148

+ powerpc64-*linux*)

5149

LD="${LD-ld} -m elf32ppclinux"

5150

;;

5151

s390x-*linux*)

5152

@@ -6421,7 +6424,10 @@

5153

x86_64-*linux*)

5154

LD="${LD-ld} -m elf_x86_64"

5155

;;

5156

- ppc*-*linux*|powerpc*-*linux*)

5157

+ powerpcle-*linux*)

5158

+ LD="${LD-ld} -m elf64lppc"

5159

+ ;;

5160

+ powerpc-*linux*)

5161

LD="${LD-ld} -m elf64ppc"

5162

;;

5163

s390*-*linux*|s390*-*tpf*)

5164

@@ -10615,7 +10621,7 @@

5165

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

5166

lt_status=$lt_dlunknown

5167

cat > conftest.$ac_ext <<_LT_EOF

5168

-#line 10618 "configure"

5169

+#line 10624 "configure"

5170

#include "confdefs.h"

5171

5172

#if HAVE_DLFCN_H

5173

@@ -10721,7 +10727,7 @@

5174

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

5175

lt_status=$lt_dlunknown

5176

cat > conftest.$ac_ext <<_LT_EOF

5177

-#line 10724 "configure"

5178

+#line 10730 "configure"

5179

#include "confdefs.h"

5180

5181

#if HAVE_DLFCN_H

5182

Index: libmudflap/ChangeLog

5183

===================================================================

5184

--- a/src/libmudflap/ChangeLog (.../tags/gcc_4_8_2_release)

5185

+++ b/src/libmudflap/ChangeLog (.../branches/gcc-4_8-branch)

5186

@@ -1,3 +1,10 @@

5187

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

5188

+

5189

+ Backport from mainline

5190

+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

5191

+

5192

+ * configure: Regenerate.

5193

+

5194

2013-10-16 Release Manager

5195

5196

* GCC 4.8.2 released.

5197

Index: boehm-gc/include/private/gcconfig.h

5198

===================================================================

5199

--- a/src/boehm-gc/include/private/gcconfig.h (.../tags/gcc_4_8_2_release)

5200

+++ b/src/boehm-gc/include/private/gcconfig.h (.../branches/gcc-4_8-branch)

5201

@@ -837,7 +837,15 @@

5202

# define NO_PTHREAD_TRYLOCK

5203

# endif

5204

# ifdef FREEBSD

5205

+# if defined(__powerpc64__)

5206

+# define ALIGNMENT 8

5207

+# define CPP_WORDSZ 64

5208

+# ifndef HBLKSIZE

5209

+# define HBLKSIZE 4096

5210

+# endif

5211

+# else

5212

# define ALIGNMENT 4

5213

+# endif

5214

# define OS_TYPE "FREEBSD"

5215

# ifndef GC_FREEBSD_THREADS

5216

# define MPROTECT_VDB

5217

Index: boehm-gc/ChangeLog

5218

===================================================================

5219

--- a/src/boehm-gc/ChangeLog (.../tags/gcc_4_8_2_release)

5220

+++ b/src/boehm-gc/ChangeLog (.../branches/gcc-4_8-branch)

5221

@@ -1,3 +1,15 @@

5222

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

5223

+

5224

+ Backport from mainline

5225

+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

5226

+

5227

+ * configure: Regenerate.

5228

+

5229

+2013-12-29 Andreas Tobler <andreast@gcc.gnu.org>

5230

+

5231

+ Merge from trunk:

5232

+ * include/private/gcconfig.h: Add FreeBSD powerpc64 defines.

5233

+

5234

2013-10-16 Release Manager

5235

5236

* GCC 4.8.2 released.

5237

Index: boehm-gc/configure

5238

===================================================================

5239

--- a/src/boehm-gc/configure (.../tags/gcc_4_8_2_release)

5240

+++ b/src/boehm-gc/configure (.../branches/gcc-4_8-branch)

5241

@@ -6770,7 +6770,7 @@

5242

rm -rf conftest*

5243

;;

5244

5245

-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \

5246

+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \

5247

s390*-*linux*|s390*-*tpf*|sparc*-*linux*)

5248

# Find out which ABI we are using.

5249

echo 'int i;' > conftest.$ac_ext

5250

@@ -6795,7 +6795,10 @@

5251

;;

5252

esac

5253

;;

5254

- ppc64-*linux*|powerpc64-*linux*)

5255

+ powerpc64le-*linux*)

5256

+ LD="${LD-ld} -m elf32lppclinux"

5257

+ ;;

5258

+ powerpc64-*linux*)

5259

LD="${LD-ld} -m elf32ppclinux"

5260

;;

5261

s390x-*linux*)

5262

@@ -6814,7 +6817,10 @@

5263

x86_64-*linux*)

5264

LD="${LD-ld} -m elf_x86_64"

5265

;;

5266

- ppc*-*linux*|powerpc*-*linux*)

5267

+ powerpcle-*linux*)

5268

+ LD="${LD-ld} -m elf64lppc"

5269

+ ;;

5270

+ powerpc-*linux*)

5271

LD="${LD-ld} -m elf64ppc"

5272

;;

5273

s390*-*linux*|s390*-*tpf*)

5274

@@ -11312,7 +11318,7 @@

5275

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

5276

lt_status=$lt_dlunknown

5277

cat > conftest.$ac_ext <<_LT_EOF

5278

-#line 11315 "configure"

5279

+#line 11321 "configure"

5280

#include "confdefs.h"

5281

5282

#if HAVE_DLFCN_H

5283

@@ -11418,7 +11424,7 @@

5284

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

5285

lt_status=$lt_dlunknown

5286

cat > conftest.$ac_ext <<_LT_EOF

5287

-#line 11421 "configure"

5288

+#line 11427 "configure"

5289

#include "confdefs.h"

5290

5291

#if HAVE_DLFCN_H

5292

Index: ChangeLog

5293

===================================================================

5294

--- a/src/ChangeLog (.../tags/gcc_4_8_2_release)

5295

+++ b/src/ChangeLog (.../branches/gcc-4_8-branch)

5296

@@ -1,3 +1,21 @@

5297

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

5298

+

5299

+ Backport from mainline

5300

+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

5301

+

5302

+ * libtool.m4: Update to mainline version.

5303

+ * configure: Regenerate.

5304

+

5305

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

5306

+

5307

+ Backport from mainline r203071:

5308

+

5309

+ 2013-10-01 Joern Rennecke <joern.rennecke@embecosm.com>

5310

+

5311

+ Import from savannah.gnu.org:

5312

+ * config.guess: Update to 2013-06-10 version.

5313

+ * config.sub: Update to 2013-10-01 version.

5314

+

5315

2013-10-16 Release Manager

5316

5317

* GCC 4.8.2 released.

5318

Index: lto-plugin/configure

5319

===================================================================

5320

--- a/src/lto-plugin/configure (.../tags/gcc_4_8_2_release)

5321

+++ b/src/lto-plugin/configure (.../branches/gcc-4_8-branch)

5322

@@ -6044,7 +6044,7 @@

5323

rm -rf conftest*

5324

;;

5325

5326

-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \

5327

+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \

5328

s390*-*linux*|s390*-*tpf*|sparc*-*linux*)

5329

# Find out which ABI we are using.

5330

echo 'int i;' > conftest.$ac_ext

5331

@@ -6069,7 +6069,10 @@

5332

;;

5333

esac

5334

;;

5335

- ppc64-*linux*|powerpc64-*linux*)

5336

+ powerpc64le-*linux*)

5337

+ LD="${LD-ld} -m elf32lppclinux"

5338

+ ;;

5339

+ powerpc64-*linux*)

5340

LD="${LD-ld} -m elf32ppclinux"

5341

;;

5342

s390x-*linux*)

5343

@@ -6088,7 +6091,10 @@

5344

x86_64-*linux*)

5345

LD="${LD-ld} -m elf_x86_64"

5346

;;

5347

- ppc*-*linux*|powerpc*-*linux*)

5348

+ powerpcle-*linux*)

5349

+ LD="${LD-ld} -m elf64lppc"

5350

+ ;;

5351

+ powerpc-*linux*)

5352

LD="${LD-ld} -m elf64ppc"

5353

;;

5354

s390*-*linux*|s390*-*tpf*)

5355

@@ -10552,7 +10558,7 @@

5356

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

5357

lt_status=$lt_dlunknown

5358

cat > conftest.$ac_ext <<_LT_EOF

5359

-#line 10555 "configure"

5360

+#line 10561 "configure"

5361

#include "confdefs.h"

5362

5363

#if HAVE_DLFCN_H

5364

@@ -10658,7 +10664,7 @@

5365

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

5366

lt_status=$lt_dlunknown

5367

cat > conftest.$ac_ext <<_LT_EOF

5368

-#line 10661 "configure"

5369

+#line 10667 "configure"

5370

#include "confdefs.h"

5371

5372

#if HAVE_DLFCN_H

5373

Index: lto-plugin/ChangeLog

5374

===================================================================

5375

--- a/src/lto-plugin/ChangeLog (.../tags/gcc_4_8_2_release)

5376

+++ b/src/lto-plugin/ChangeLog (.../branches/gcc-4_8-branch)

5377

@@ -1,3 +1,10 @@

5378

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

5379

+

5380

+ Backport from mainline

5381

+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

5382

+

5383

+ * configure: Regenerate.

5384

+

5385

2013-10-16 Release Manager

5386

5387

* GCC 4.8.2 released.

5388

Index: contrib/ChangeLog

5389

===================================================================

5390

--- a/src/contrib/ChangeLog (.../tags/gcc_4_8_2_release)

5391

+++ b/src/contrib/ChangeLog (.../branches/gcc-4_8-branch)

5392

@@ -1,3 +1,7 @@

5393

+2013-10-21 Mike Stump <mikestump@comcast.net>

5394

+

5395

+ * gcc_update (configure): Update to handle svn 1.8.1.

5396

+

5397

2013-10-16 Release Manager

5398

5399

* GCC 4.8.2 released.

5400

Index: contrib/gcc_update

5401

===================================================================

5402

--- a/src/contrib/gcc_update (.../tags/gcc_4_8_2_release)

5403

+++ b/src/contrib/gcc_update (.../branches/gcc-4_8-branch)

5404

@@ -382,7 +382,7 @@

5405

fi

5406

5407

revision=`$GCC_SVN info | awk '/Revision:/ { print $2 }'`

5408

- branch=`$GCC_SVN info | sed -ne "/URL:/ {

5409

+ branch=`$GCC_SVN info | sed -ne "/^URL:/ {

5410

s,.*/trunk,trunk,

5411

s,.*/branches/,,

5412

s,.*/tags/,,

5413

Index: libatomic/configure

5414

===================================================================

5415

--- a/src/libatomic/configure (.../tags/gcc_4_8_2_release)

5416

+++ b/src/libatomic/configure (.../branches/gcc-4_8-branch)

5417

@@ -6505,7 +6505,7 @@

5418

rm -rf conftest*

5419

;;

5420

5421

-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \

5422

+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \

5423

s390*-*linux*|s390*-*tpf*|sparc*-*linux*)

5424

# Find out which ABI we are using.

5425

echo 'int i;' > conftest.$ac_ext

5426

@@ -6530,7 +6530,10 @@

5427

;;

5428

esac

5429

;;

5430

- ppc64-*linux*|powerpc64-*linux*)

5431

+ powerpc64le-*linux*)

5432

+ LD="${LD-ld} -m elf32lppclinux"

5433

+ ;;

5434

+ powerpc64-*linux*)

5435

LD="${LD-ld} -m elf32ppclinux"

5436

;;

5437

s390x-*linux*)

5438

@@ -6549,7 +6552,10 @@

5439

x86_64-*linux*)

5440

LD="${LD-ld} -m elf_x86_64"

5441

;;

5442

- ppc*-*linux*|powerpc*-*linux*)

5443

+ powerpcle-*linux*)

5444

+ LD="${LD-ld} -m elf64lppc"

5445

+ ;;

5446

+ powerpc-*linux*)

5447

LD="${LD-ld} -m elf64ppc"

5448

;;

5449

s390*-*linux*|s390*-*tpf*)

5450

@@ -11013,7 +11019,7 @@

5451

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

5452

lt_status=$lt_dlunknown

5453

cat > conftest.$ac_ext <<_LT_EOF

5454

-#line 11016 "configure"

5455

+#line 11022 "configure"

5456

#include "confdefs.h"

5457

5458

#if HAVE_DLFCN_H

5459

@@ -11119,7 +11125,7 @@

5460

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

5461

lt_status=$lt_dlunknown

5462

cat > conftest.$ac_ext <<_LT_EOF

5463

-#line 11122 "configure"

5464

+#line 11128 "configure"

5465

#include "confdefs.h"

5466

5467

#if HAVE_DLFCN_H

5468

Index: libatomic/cas_n.c

5469

===================================================================

5470

--- a/src/libatomic/cas_n.c (.../tags/gcc_4_8_2_release)

5471

+++ b/src/libatomic/cas_n.c (.../branches/gcc-4_8-branch)

5472

@@ -51,10 +51,9 @@

5473

#if !DONE && N <= WORDSIZE && defined(atomic_compare_exchange_w)

5474

bool

5475

SIZE(libat_compare_exchange) (UTYPE *mptr, UTYPE *eptr, UTYPE newval,

5476

- int smodel, int fmodel UNUSED)

5477

+ int smodel, int fmodel)

5478

{

5479

UWORD mask, shift, weval, woldval, wnewval, t, *wptr;

5480

- bool ret = false;

5481

5482

pre_barrier (smodel);

5483

5484

@@ -82,12 +81,13 @@

5485

}

5486

while (!atomic_compare_exchange_w (wptr, &woldval, t, true,

5487

__ATOMIC_RELAXED, __ATOMIC_RELAXED));

5488

- ret = true;

5489

+ post_barrier (smodel);

5490

+ return true;

5491

+

5492

failure:

5493

*eptr = woldval >> shift;

5494

-

5495

- post_barrier (smodel);

5496

- return ret;

5497

+ post_barrier (fmodel);

5498

+ return false;

5499

}

5500

5501

#define DONE 1

5502

@@ -102,18 +102,17 @@

5503

{

5504

UTYPE oldval;

5505

UWORD magic;

5506

- bool ret = false;

5507

+ bool ret;

5508

5509

pre_seq_barrier (smodel);

5510

magic = protect_start (mptr);

5511

5512

oldval = *mptr;

5513

- if (oldval == *eptr)

5514

- {

5515

- *mptr = newval;

5516

- ret = true;

5517

- }

5518

- *eptr = oldval;

5519

+ ret = (oldval == *eptr);

5520

+ if (ret)

5521

+ *mptr = newval;

5522

+ else

5523

+ *eptr = oldval;

5524

5525

protect_end (mptr, magic);

5526

post_seq_barrier (smodel);

5527

Index: libatomic/ChangeLog

5528

===================================================================

5529

--- a/src/libatomic/ChangeLog (.../tags/gcc_4_8_2_release)

5530

+++ b/src/libatomic/ChangeLog (.../branches/gcc-4_8-branch)

5531

@@ -1,3 +1,16 @@

5532

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

5533

+

5534

+ Backport from mainline

5535

+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

5536

+

5537

+ * configure: Regenerate.

5538

+

5539

+2014-02-20 Richard Henderson <rth@redhat.com>

5540

+

5541

+ PR c++/60272

5542

+ * cas_n.c (libat_compare_exchange): Conditionalize on failure

5543

+ the store back to EPTR.

5544

+

5545

2013-10-16 Release Manager

5546

5547

* GCC 4.8.2 released.

5548

Index: libbacktrace/configure

5549

===================================================================

5550

--- a/src/libbacktrace/configure (.../tags/gcc_4_8_2_release)

5551

+++ b/src/libbacktrace/configure (.../branches/gcc-4_8-branch)

5552

@@ -6842,7 +6842,7 @@

5553

rm -rf conftest*

5554

;;

5555

5556

-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \

5557

+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \

5558

s390*-*linux*|s390*-*tpf*|sparc*-*linux*)

5559

# Find out which ABI we are using.

5560

echo 'int i;' > conftest.$ac_ext

5561

@@ -6867,7 +6867,10 @@

5562

;;

5563

esac

5564

;;

5565

- ppc64-*linux*|powerpc64-*linux*)

5566

+ powerpc64le-*linux*)

5567

+ LD="${LD-ld} -m elf32lppclinux"

5568

+ ;;

5569

+ powerpc64-*linux*)

5570

LD="${LD-ld} -m elf32ppclinux"

5571

;;

5572

s390x-*linux*)

5573

@@ -6886,7 +6889,10 @@

5574

x86_64-*linux*)

5575

LD="${LD-ld} -m elf_x86_64"

5576

;;

5577

- ppc*-*linux*|powerpc*-*linux*)

5578

+ powerpcle-*linux*)

5579

+ LD="${LD-ld} -m elf64lppc"

5580

+ ;;

5581

+ powerpc-*linux*)

5582

LD="${LD-ld} -m elf64ppc"

5583

;;

5584

s390*-*linux*|s390*-*tpf*)

5585

@@ -11081,7 +11087,7 @@

5586

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

5587

lt_status=$lt_dlunknown

5588

cat > conftest.$ac_ext <<_LT_EOF

5589

-#line 11084 "configure"

5590

+#line 11090 "configure"

5591

#include "confdefs.h"

5592

5593

#if HAVE_DLFCN_H

5594

@@ -11187,7 +11193,7 @@

5595

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

5596

lt_status=$lt_dlunknown

5597

cat > conftest.$ac_ext <<_LT_EOF

5598

-#line 11190 "configure"

5599

+#line 11196 "configure"

5600

#include "confdefs.h"

5601

5602

#if HAVE_DLFCN_H

5603

@@ -11667,12 +11673,13 @@

5604

return 0;

5605

}

5606

_ACEOF

5607

-if ac_fn_c_try_compile "$LINENO"; then :

5608

+if ac_fn_c_try_link "$LINENO"; then :

5609

have_unwind_getipinfo=yes

5610

else

5611

have_unwind_getipinfo=no

5612

fi

5613

-rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext

5614

+rm -f core conftest.err conftest.$ac_objext \

5615

+ conftest$ac_exeext conftest.$ac_ext

5616

CFLAGS="$ac_save_CFLAGS"

5617

{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $have_unwind_getipinfo" >&5

5618

$as_echo "$have_unwind_getipinfo" >&6; }

5619

Index: libbacktrace/Makefile.in

5620

===================================================================

5621

--- a/src/libbacktrace/Makefile.in (.../tags/gcc_4_8_2_release)

5622

+++ b/src/libbacktrace/Makefile.in (.../branches/gcc-4_8-branch)

5623

@@ -16,7 +16,7 @@

5624

@SET_MAKE@

5625

5626

# Makefile.am -- Backtrace Makefile.

5627

5628

5629

5630

# Redistribution and use in source and binary forms, with or without

5631

# modification, are permitted provided that the following conditions are

5632

Index: libbacktrace/dwarf.c

5633

===================================================================

5634

--- a/src/libbacktrace/dwarf.c (.../tags/gcc_4_8_2_release)

5635

+++ b/src/libbacktrace/dwarf.c (.../branches/gcc-4_8-branch)

5636

@@ -2507,7 +2507,6 @@

5637

if (pfvec->count == 0)

5638

return;

5639

5640

- addrs = (struct function_addrs *) pfvec->vec.base;

5641

addrs_count = pfvec->count;

5642

5643

if (fvec == NULL)

5644

@@ -2514,12 +2513,17 @@

5645

{

5646

if (!backtrace_vector_release (state, &lvec.vec, error_callback, data))

5647

return;

5648

+ addrs = (struct function_addrs *) pfvec->vec.base;

5649

}

5650

else

5651

{

5652

/* Finish this list of addresses, but leave the remaining space in

5653

the vector available for the next function unit. */

5654

- backtrace_vector_finish (state, &fvec->vec);

5655

+ addrs = ((struct function_addrs *)

5656

+ backtrace_vector_finish (state, &fvec->vec,

5657

+ error_callback, data));

5658

+ if (addrs == NULL)

5659

+ return;

5660

fvec->count = 0;

5661

}

5662

5663

Index: libbacktrace/ChangeLog

5664

===================================================================

5665

--- a/src/libbacktrace/ChangeLog (.../tags/gcc_4_8_2_release)

5666

+++ b/src/libbacktrace/ChangeLog (.../branches/gcc-4_8-branch)

5667

@@ -1,3 +1,35 @@

5668

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

5669

+

5670

+ Backport from mainline

5671

+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

5672

+

5673

+ * configure: Regenerate.

5674

+

5675

+2014-02-07 Misty De Meo <misty@brew.sh>

5676

+

5677

+ PR target/58710

5678

+ * configure.ac: Use AC_LINK_IFELSE in check for

5679

+ _Unwind_GetIPInfo.

5680

+ * configure: Regenerate.

5681

+

5682

+2013-12-05 Ian Lance Taylor <iant@google.com>

5683

+

5684

+ * alloc.c (backtrace_vector_finish): Add error_callback and data

5685

+ parameters. Call backtrace_vector_release. Return address base.

5686

+ * mmap.c (backtrace_vector_finish): Add error_callback and data

5687

+ parameters. Return address base.

5688

+ * dwarf.c (read_function_info): Get new address base from

5689

+ backtrace_vector_finish.

5690

+ * internal.h (backtrace_vector_finish): Update declaration.

5691

+

5692

+2013-11-30 Ian Lance Taylor <iant@google.com>

5693

+

5694

+ Backport from mainline:

5695

+ 2013-10-17 Ian Lance Taylor <iant@google.com>

5696

+

5697

+ * elf.c (elf_add): Don't get the wrong offsets if a debug section

5698

+ is missing.

5699

+

5700

2013-10-16 Release Manager

5701

5702

* GCC 4.8.2 released.

5703

Index: libbacktrace/elf.c

5704

===================================================================

5705

--- a/src/libbacktrace/elf.c (.../tags/gcc_4_8_2_release)

5706

+++ b/src/libbacktrace/elf.c (.../branches/gcc-4_8-branch)

5707

@@ -725,6 +725,8 @@

5708

{

5709

off_t end;

5710

5711

+ if (sections[i].size == 0)

5712

+ continue;

5713

if (min_offset == 0 || sections[i].offset < min_offset)

5714

min_offset = sections[i].offset;

5715

end = sections[i].offset + sections[i].size;

5716

@@ -751,8 +753,13 @@

5717

descriptor = -1;

5718

5719

for (i = 0; i < (int) DEBUG_MAX; ++i)

5720

- sections[i].data = ((const unsigned char *) debug_view.data

5721

- + (sections[i].offset - min_offset));

5722

+ {

5723

+ if (sections[i].size == 0)

5724

+ sections[i].data = NULL;

5725

+ else

5726

+ sections[i].data = ((const unsigned char *) debug_view.data

5727

+ + (sections[i].offset - min_offset));

5728

+ }

5729

5730

if (!backtrace_dwarf_add (state, base_address,

5731

sections[DEBUG_INFO].data,

5732

Index: libbacktrace/internal.h

5733

===================================================================

5734

--- a/src/libbacktrace/internal.h (.../tags/gcc_4_8_2_release)

5735

+++ b/src/libbacktrace/internal.h (.../branches/gcc-4_8-branch)

5736

@@ -192,13 +192,17 @@

5737

struct backtrace_vector *vec);

5738

5739

/* Finish the current allocation on VEC. Prepare to start a new

5740

- allocation. The finished allocation will never be freed. */

5741

+ allocation. The finished allocation will never be freed. Returns

5742

+ a pointer to the base of the finished entries, or NULL on

5743

+ failure. */

5744

5745

-extern void backtrace_vector_finish (struct backtrace_state *state,

5746

- struct backtrace_vector *vec);

5747

+extern void* backtrace_vector_finish (struct backtrace_state *state,

5748

+ struct backtrace_vector *vec,

5749

+ backtrace_error_callback error_callback,

5750

+ void *data);

5751

5752

-/* Release any extra space allocated for VEC. Returns 1 on success, 0

5753

- on failure. */

5754

+/* Release any extra space allocated for VEC. This may change

5755

+ VEC->base. Returns 1 on success, 0 on failure. */

5756

5757

extern int backtrace_vector_release (struct backtrace_state *state,

5758

struct backtrace_vector *vec,

5759

Index: libbacktrace/configure.ac

5760

===================================================================

5761

--- a/src/libbacktrace/configure.ac (.../tags/gcc_4_8_2_release)

5762

+++ b/src/libbacktrace/configure.ac (.../branches/gcc-4_8-branch)

5763

@@ -144,7 +144,7 @@

5764

ac_save_CFFLAGS="$CFLAGS"

5765

CFLAGS="$CFLAGS -Werror-implicit-function-declaration"

5766

AC_MSG_CHECKING([for _Unwind_GetIPInfo])

5767

- AC_COMPILE_IFELSE(

5768

+ AC_LINK_IFELSE(

5769

[AC_LANG_PROGRAM(

5770

[#include "unwind.h"

5771

struct _Unwind_Context *context;

5772

Index: libbacktrace/alloc.c

5773

===================================================================

5774

--- a/src/libbacktrace/alloc.c (.../tags/gcc_4_8_2_release)

5775

+++ b/src/libbacktrace/alloc.c (.../branches/gcc-4_8-branch)

5776

@@ -113,12 +113,24 @@

5777

5778

/* Finish the current allocation on VEC. */

5779

5780

-void

5781

-backtrace_vector_finish (struct backtrace_state *state ATTRIBUTE_UNUSED,

5782

- struct backtrace_vector *vec)

5783

+void *

5784

+backtrace_vector_finish (struct backtrace_state *state,

5785

+ struct backtrace_vector *vec,

5786

+ backtrace_error_callback error_callback,

5787

+ void *data)

5788

{

5789

- vec->base = (char *) vec->base + vec->size;

5790

+ void *ret;

5791

+

5792

+ /* With this allocator we call realloc in backtrace_vector_grow,

5793

+ which means we can't easily reuse the memory here. So just

5794

+ release it. */

5795

+ if (!backtrace_vector_release (state, vec, error_callback, data))

5796

+ return NULL;

5797

+ ret = vec->base;

5798

+ vec->base = NULL;

5799

vec->size = 0;

5800

+ vec->alc = 0;

5801

+ return ret;

5802

}

5803

5804

/* Release any extra space allocated for VEC. */

5805

Index: libbacktrace/mmap.c

5806

===================================================================

5807

--- a/src/libbacktrace/mmap.c (.../tags/gcc_4_8_2_release)

5808

+++ b/src/libbacktrace/mmap.c (.../branches/gcc-4_8-branch)

5809

@@ -230,12 +230,19 @@

5810

5811

/* Finish the current allocation on VEC. */

5812

5813

-void

5814

-backtrace_vector_finish (struct backtrace_state *state ATTRIBUTE_UNUSED,

5815

- struct backtrace_vector *vec)

5816

+void *

5817

+backtrace_vector_finish (

5818

+ struct backtrace_state *state ATTRIBUTE_UNUSED,

5819

+ struct backtrace_vector *vec,

5820

+ backtrace_error_callback error_callback ATTRIBUTE_UNUSED,

5821

+ void *data ATTRIBUTE_UNUSED)

5822

{

5823

+ void *ret;

5824

+

5825

+ ret = vec->base;

5826

vec->base = (char *) vec->base + vec->size;

5827

vec->size = 0;

5828

+ return ret;

5829

}

5830

5831

/* Release any extra space allocated for VEC. */

5832

Index: libjava/libltdl/configure

5833

===================================================================

5834

--- a/src/libjava/libltdl/configure (.../tags/gcc_4_8_2_release)

5835

+++ b/src/libjava/libltdl/configure (.../branches/gcc-4_8-branch)

5836

@@ -4806,7 +4806,7 @@

5837

rm -rf conftest*

5838

;;

5839

5840

-x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*|s390*-*linux*|sparc*-*linux*)

5841

+x86_64-*linux*|powerpc*-*linux*|s390*-*linux*|sparc*-*linux*)

5842

# Find out which ABI we are using.

5843

echo 'int i;' > conftest.$ac_ext

5844

if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } >&5

5845

@@ -4820,7 +4820,10 @@

5846

x86_64-*linux*)

5847

LD="${LD-ld} -m elf_i386"

5848

;;

5849

- ppc64-*linux*|powerpc64-*linux*)

5850

+ powerpc64le-*linux*)

5851

+ LD="${LD-ld} -m elf32lppclinux"

5852

+ ;;

5853

+ powerpc64-*linux*)

5854

LD="${LD-ld} -m elf32ppclinux"

5855

;;

5856

s390x-*linux*)

5857

@@ -4836,7 +4839,10 @@

5858

x86_64-*linux*)

5859

LD="${LD-ld} -m elf_x86_64"

5860

;;

5861

- ppc*-*linux*|powerpc*-*linux*)

5862

+ powerpcle-*linux*)

5863

+ LD="${LD-ld} -m elf64lppc"

5864

+ ;;

5865

+ powerpc-*linux*)

5866

LD="${LD-ld} -m elf64ppc"

5867

;;

5868

s390*-*linux*)

5869

@@ -6456,11 +6462,11 @@

5870

-e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \

5871

-e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \

5872

-e 's:$: $lt_compiler_flag:'`

5873

- (eval echo "\"\$as_me:6459: $lt_compile\"" >&5)

5874

+ (eval echo "\"\$as_me:6465: $lt_compile\"" >&5)

5875

(eval "$lt_compile" 2>conftest.err)

5876

ac_status=$?

5877

cat conftest.err >&5

5878

- echo "$as_me:6463: \$? = $ac_status" >&5

5879

+ echo "$as_me:6469: \$? = $ac_status" >&5

5880

if (exit $ac_status) && test -s "$ac_outfile"; then

5881

# The compiler can only warn and ignore the option if not recognized

5882

# So say no if there are warnings other than the usual output.

5883

@@ -6718,11 +6724,11 @@

5884

-e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \

5885

-e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \

5886

-e 's:$: $lt_compiler_flag:'`

5887

- (eval echo "\"\$as_me:6721: $lt_compile\"" >&5)

5888

+ (eval echo "\"\$as_me:6727: $lt_compile\"" >&5)

5889

(eval "$lt_compile" 2>conftest.err)

5890

ac_status=$?

5891

cat conftest.err >&5

5892

- echo "$as_me:6725: \$? = $ac_status" >&5

5893

+ echo "$as_me:6731: \$? = $ac_status" >&5

5894

if (exit $ac_status) && test -s "$ac_outfile"; then

5895

# The compiler can only warn and ignore the option if not recognized

5896

# So say no if there are warnings other than the usual output.

5897

@@ -6780,11 +6786,11 @@

5898

-e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \

5899

-e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \

5900

-e 's:$: $lt_compiler_flag:'`

5901

- (eval echo "\"\$as_me:6783: $lt_compile\"" >&5)

5902

+ (eval echo "\"\$as_me:6789: $lt_compile\"" >&5)

5903

(eval "$lt_compile" 2>out/conftest.err)

5904

ac_status=$?

5905

cat out/conftest.err >&5

5906

- echo "$as_me:6787: \$? = $ac_status" >&5

5907

+ echo "$as_me:6793: \$? = $ac_status" >&5

5908

if (exit $ac_status) && test -s out/conftest2.$ac_objext

5909

then

5910

# The compiler can only warn and ignore the option if not recognized

5911

@@ -8099,7 +8105,7 @@

5912

libsuff=

5913

case "$host_cpu" in

5914

x86_64*|s390x*|powerpc64*)

5915

- echo '#line 8102 "configure"' > conftest.$ac_ext

5916

+ echo '#line 8108 "configure"' > conftest.$ac_ext

5917

if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } >&5

5918

(eval $ac_compile) 2>&5

5919

ac_status=$?

5920

@@ -8652,7 +8658,7 @@

5921

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

5922

lt_status=$lt_dlunknown

5923

cat > conftest.$ac_ext <<EOF

5924

-#line 8655 "configure"

5925

+#line 8661 "configure"

5926

#include "confdefs.h"

5927

5928

#if HAVE_DLFCN_H

5929

@@ -8750,7 +8756,7 @@

5930

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

5931

lt_status=$lt_dlunknown

5932

cat > conftest.$ac_ext <<EOF

5933

-#line 8753 "configure"

5934

+#line 8759 "configure"

5935

#include "confdefs.h"

5936

5937

#if HAVE_DLFCN_H

5938

@@ -10591,7 +10597,7 @@

5939

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

5940

lt_status=$lt_dlunknown

5941

cat > conftest.$ac_ext <<EOF

5942

-#line 10594 "configure"

5943

+#line 10600 "configure"

5944

#include "confdefs.h"

5945

5946

#if HAVE_DLFCN_H

5947

Index: libjava/libltdl/ChangeLog

5948

===================================================================

5949

--- a/src/libjava/libltdl/ChangeLog (.../tags/gcc_4_8_2_release)

5950

+++ b/src/libjava/libltdl/ChangeLog (.../branches/gcc-4_8-branch)

5951

@@ -1,3 +1,11 @@

5952

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

5953

+

5954

+ Backport from mainline

5955

+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

5956

+

5957

+ * acinclude.m4: Update to mainline version.

5958

+ * configure: Regenerate.

5959

+

5960

2013-10-16 Release Manager

5961

5962

* GCC 4.8.2 released.

5963

Index: libjava/libltdl/acinclude.m4

5964

===================================================================

5965

--- a/src/libjava/libltdl/acinclude.m4 (.../tags/gcc_4_8_2_release)

5966

+++ b/src/libjava/libltdl/acinclude.m4 (.../branches/gcc-4_8-branch)

5967

@@ -519,7 +519,7 @@

5968

rm -rf conftest*

5969

;;

5970

5971

-x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*|s390*-*linux*|sparc*-*linux*)

5972

+x86_64-*linux*|powerpc*-*linux*|s390*-*linux*|sparc*-*linux*)

5973

# Find out which ABI we are using.

5974

echo 'int i;' > conftest.$ac_ext

5975

if AC_TRY_EVAL(ac_compile); then

5976

@@ -529,7 +529,10 @@

5977

x86_64-*linux*)

5978

LD="${LD-ld} -m elf_i386"

5979

;;

5980

- ppc64-*linux*|powerpc64-*linux*)

5981

+ powerpc64le-*linux*)

5982

+ LD="${LD-ld} -m elf32lppclinux"

5983

+ ;;

5984

+ powerpc64-*linux*)

5985

LD="${LD-ld} -m elf32ppclinux"

5986

;;

5987

s390x-*linux*)

5988

@@ -545,7 +548,10 @@

5989

x86_64-*linux*)

5990

LD="${LD-ld} -m elf_x86_64"

5991

;;

5992

- ppc*-*linux*|powerpc*-*linux*)

5993

+ powerpcle-*linux*)

5994

+ LD="${LD-ld} -m elf64lppc"

5995

+ ;;

5996

+ powerpc-*linux*)

5997

LD="${LD-ld} -m elf64ppc"

5998

;;

5999

s390*-*linux*)

6000

Index: libjava/classpath/ChangeLog

6001

===================================================================

6002

--- a/src/libjava/classpath/ChangeLog (.../tags/gcc_4_8_2_release)

6003

+++ b/src/libjava/classpath/ChangeLog (.../branches/gcc-4_8-branch)

6004

@@ -1,3 +1,10 @@

6005

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

6006

+

6007

+ Backport from mainline

6008

+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

6009

+

6010

+ * configure: Regenerate.

6011

+

6012

2013-10-16 Release Manager

6013

6014

* GCC 4.8.2 released.

6015

Index: libjava/classpath/configure

6016

===================================================================

6017

--- a/src/libjava/classpath/configure (.../tags/gcc_4_8_2_release)

6018

+++ b/src/libjava/classpath/configure (.../branches/gcc-4_8-branch)

6019

@@ -7577,7 +7577,7 @@

6020

rm -rf conftest*

6021

;;

6022

6023

-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \

6024

+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \

6025

s390*-*linux*|s390*-*tpf*|sparc*-*linux*)

6026

# Find out which ABI we are using.

6027

echo 'int i;' > conftest.$ac_ext

6028

@@ -7602,7 +7602,10 @@

6029

;;

6030

esac

6031

;;

6032

- ppc64-*linux*|powerpc64-*linux*)

6033

+ powerpc64le-*linux*)

6034

+ LD="${LD-ld} -m elf32lppclinux"

6035

+ ;;

6036

+ powerpc64-*linux*)

6037

LD="${LD-ld} -m elf32ppclinux"

6038

;;

6039

s390x-*linux*)

6040

@@ -7621,7 +7624,10 @@

6041

x86_64-*linux*)

6042

LD="${LD-ld} -m elf_x86_64"

6043

;;

6044

- ppc*-*linux*|powerpc*-*linux*)

6045

+ powerpcle-*linux*)

6046

+ LD="${LD-ld} -m elf64lppc"

6047

+ ;;

6048

+ powerpc-*linux*)

6049

LD="${LD-ld} -m elf64ppc"

6050

;;

6051

s390*-*linux*|s390*-*tpf*)

6052

@@ -11820,7 +11826,7 @@

6053

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

6054

lt_status=$lt_dlunknown

6055

cat > conftest.$ac_ext <<_LT_EOF

6056

-#line 11823 "configure"

6057

+#line 11829 "configure"

6058

#include "confdefs.h"

6059

6060

#if HAVE_DLFCN_H

6061

@@ -11926,7 +11932,7 @@

6062

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

6063

lt_status=$lt_dlunknown

6064

cat > conftest.$ac_ext <<_LT_EOF

6065

-#line 11929 "configure"

6066

+#line 11935 "configure"

6067

#include "confdefs.h"

6068

6069

#if HAVE_DLFCN_H

6070

@@ -25300,7 +25306,7 @@

6071

JAVA_TEST=Object.java

6072

CLASS_TEST=Object.class

6073

cat << \EOF > $JAVA_TEST

6074

-/* #line 25303 "configure" */

6075

+/* #line 25309 "configure" */

6076

package java.lang;

6077

6078

public class Object

6079

@@ -25393,7 +25399,7 @@

6080

if uudecode$EXEEXT Test.uue; then

6081

ac_cv_prog_uudecode_base64=yes

6082

else

6083

- echo "configure: 25396: uudecode had trouble decoding base 64 file 'Test.uue'" >&5

6084

+ echo "configure: 25402: uudecode had trouble decoding base 64 file 'Test.uue'" >&5

6085

echo "configure: failed file was:" >&5

6086

cat Test.uue >&5

6087

ac_cv_prog_uudecode_base64=no

6088

@@ -25421,7 +25427,7 @@

6089

CLASS_TEST=Test.class

6090

TEST=Test

6091

cat << \EOF > $JAVA_TEST

6092

-/* [#]line 25424 "configure" */

6093

+/* [#]line 25430 "configure" */

6094

public class Test {

6095

public static void main (String args[]) {

6096

System.exit (0);

6097

@@ -25629,7 +25635,7 @@

6098

JAVA_TEST=Test.java

6099

CLASS_TEST=Test.class

6100

cat << \EOF > $JAVA_TEST

6101

- /* #line 25632 "configure" */

6102

+ /* #line 25638 "configure" */

6103

public class Test

6104

{

6105

public static void main(String args)

6106

Index: libjava/classpath/native/jni/gtk-peer/gnu_java_awt_peer_gtk_GdkFontPeer.c

6107

===================================================================

6108

--- a/src/libjava/classpath/native/jni/gtk-peer/gnu_java_awt_peer_gtk_GdkFontPeer.c (.../tags/gcc_4_8_2_release)

6109

+++ b/src/libjava/classpath/native/jni/gtk-peer/gnu_java_awt_peer_gtk_GdkFontPeer.c (.../branches/gcc-4_8-branch)

6110

@@ -39,10 +39,11 @@

6111

#include <pango/pango.h>

6112

#include <pango/pangoft2.h>

6113

#include <pango/pangofc-font.h>

6114

-#include <freetype/ftglyph.h>

6115

-#include <freetype/ftoutln.h>

6116

-#include <freetype/fttypes.h>

6117

-#include <freetype/tttables.h>

6118

+#include <ft2build.h>

6119

+#include FT_GLYPH_H

6120

+#include FT_OUTLINE_H

6121

+#include FT_TYPES_H

6122

+#include FT_TRUETYPE_TABLES_H

6123

#include "gdkfont.h"

6124

#include "gtkpeer.h"

6125

#include "gnu_java_awt_peer_gtk_GdkFontPeer.h"

6126

Index: libjava/classpath/native/jni/gtk-peer/gnu_java_awt_peer_gtk_FreetypeGlyphVector.c

6127

===================================================================

6128

--- a/src/libjava/classpath/native/jni/gtk-peer/gnu_java_awt_peer_gtk_FreetypeGlyphVector.c (.../tags/gcc_4_8_2_release)

6129

+++ b/src/libjava/classpath/native/jni/gtk-peer/gnu_java_awt_peer_gtk_FreetypeGlyphVector.c (.../branches/gcc-4_8-branch)

6130

@@ -42,8 +42,9 @@

6131

#include <pango/pango.h>

6132

#include <pango/pangoft2.h>

6133

#include <pango/pangofc-font.h>

6134

-#include <freetype/ftglyph.h>

6135

-#include <freetype/ftoutln.h>

6136

+#include <ft2build.h>

6137

+#include FT_GLYPH_H

6138

+#include FT_OUTLINE_H

6139

#include "jcl.h"

6140

#include "gdkfont.h"

6141

#include "gnu_java_awt_peer_gtk_FreetypeGlyphVector.h"

6142

Index: libjava/classpath/ChangeLog.gcj

6143

===================================================================

6144

--- a/src/libjava/classpath/ChangeLog.gcj (.../tags/gcc_4_8_2_release)

6145

+++ b/src/libjava/classpath/ChangeLog.gcj (.../branches/gcc-4_8-branch)

6146

@@ -1,3 +1,9 @@

6147

+2013-11-29 Matthias Klose <doko@ubuntu.com>

6148

+

6149

+ * native/jni/gtk-peer/gnu_java_awt_peer_gtk_FreetypeGlyphVector.c,

6150

+ native/jni/gtk-peer/gnu_java_awt_peer_gtk_GdkFontPeer.c:

6151

+ Fix freetype includes.

6152

+

6153

2013-03-22 Jakub Jelinek <jakub@redhat.com>

6154

6155

PR other/43620

6156

Index: libjava/classpath

6157

===================================================================

6158

--- a/src/libjava/classpath (.../tags/gcc_4_8_2_release)

6159

+++ b/src/libjava/classpath (.../branches/gcc-4_8-branch)

6160

6161

Property changes on: libjava/classpath

6162

___________________________________________________________________

6163

Modified: svn:mergeinfo

6164

Merged /trunk/libjava/classpath:r206395

6165

Index: libjava/ChangeLog

6166

===================================================================

6167

--- a/src/libjava/ChangeLog (.../tags/gcc_4_8_2_release)

6168

+++ b/src/libjava/ChangeLog (.../branches/gcc-4_8-branch)

6169

@@ -1,3 +1,23 @@

6170

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

6171

+

6172

+ Backport from mainline

6173

+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

6174

+

6175

+ * configure: Regenerate.

6176

+

6177

+2014-04-01 Dominique d'Humieres <dominiq@lps.ens.fr>

6178

+

6179

+ Backport from mainline

6180

+ 2014-02-20 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>

6181

+

6182

+ PR libgcj/55637

6183

+ * testsuite/libjava.lang/sourcelocation.xfail: New file.

6184

+

6185

+2014-03-11 Uros Bizjak <ubizjak@gmail.com>

6186

+

6187

+ * java/lang/natObject.cc (_Jv_MonitorEnter): Add missing parenthesis

6188

+ around comparison with (address | LOCKED) in JvAssert.

6189

+

6190

2013-10-16 Release Manager

6191

6192

* GCC 4.8.2 released.

6193

Index: libjava/testsuite/libjava.lang/sourcelocation.xfail

6194

===================================================================

6195

--- a/src/libjava/testsuite/libjava.lang/sourcelocation.xfail (.../tags/gcc_4_8_2_release)

6196

+++ b/src/libjava/testsuite/libjava.lang/sourcelocation.xfail (.../branches/gcc-4_8-branch)

6197

@@ -0,0 +1 @@

6198

+xfail-output

6199

Index: libjava/configure

6200

===================================================================

6201

--- a/src/libjava/configure (.../tags/gcc_4_8_2_release)

6202

+++ b/src/libjava/configure (.../branches/gcc-4_8-branch)

6203

@@ -8842,7 +8842,7 @@

6204

rm -rf conftest*

6205

;;

6206

6207

-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \

6208

+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \

6209

s390*-*linux*|s390*-*tpf*|sparc*-*linux*)

6210

# Find out which ABI we are using.

6211

echo 'int i;' > conftest.$ac_ext

6212

@@ -8867,7 +8867,10 @@

6213

;;

6214

esac

6215

;;

6216

- ppc64-*linux*|powerpc64-*linux*)

6217

+ powerpc64le-*linux*)

6218

+ LD="${LD-ld} -m elf32lppclinux"

6219

+ ;;

6220

+ powerpc64-*linux*)

6221

LD="${LD-ld} -m elf32ppclinux"

6222

;;

6223

s390x-*linux*)

6224

@@ -8886,7 +8889,10 @@

6225

x86_64-*linux*)

6226

LD="${LD-ld} -m elf_x86_64"

6227

;;

6228

- ppc*-*linux*|powerpc*-*linux*)

6229

+ powerpcle-*linux*)

6230

+ LD="${LD-ld} -m elf64lppc"

6231

+ ;;

6232

+ powerpc-*linux*)

6233

LD="${LD-ld} -m elf64ppc"

6234

;;

6235

s390*-*linux*|s390*-*tpf*)

6236

@@ -13382,7 +13388,7 @@

6237

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

6238

lt_status=$lt_dlunknown

6239

cat > conftest.$ac_ext <<_LT_EOF

6240

-#line 13385 "configure"

6241

+#line 13391 "configure"

6242

#include "confdefs.h"

6243

6244

#if HAVE_DLFCN_H

6245

@@ -13488,7 +13494,7 @@

6246

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

6247

lt_status=$lt_dlunknown

6248

cat > conftest.$ac_ext <<_LT_EOF

6249

-#line 13491 "configure"

6250

+#line 13497 "configure"

6251

#include "confdefs.h"

6252

6253

#if HAVE_DLFCN_H

6254

@@ -19483,7 +19489,7 @@

6255

enableval=$enable_sjlj_exceptions; :

6256

else

6257

cat > conftest.$ac_ext << EOF

6258

-#line 19486 "configure"

6259

+#line 19492 "configure"

6260

struct S { ~S(); };

6261

void bar();

6262

void foo()

6263

Index: libjava/java/lang/natObject.cc

6264

===================================================================

6265

--- a/src/libjava/java/lang/natObject.cc (.../tags/gcc_4_8_2_release)

6266

+++ b/src/libjava/java/lang/natObject.cc (.../branches/gcc-4_8-branch)

6267

@@ -929,7 +929,7 @@

6268

// only be held by other threads waiting for conversion, and

6269

// they, like us, drop it quickly without blocking.

6270

_Jv_MutexLock(&(hl->si.mutex));

6271

- JvAssert(he -> address == address | LOCKED );

6272

+ JvAssert(he -> address == (address | LOCKED));

6273

release_set(&(he -> address), (address | REQUEST_CONVERSION | HEAVY));

6274

// release lock on he

6275

LOG(REQ_CONV, (address | REQUEST_CONVERSION | HEAVY), self);

6276

@@ -961,7 +961,7 @@

6277

}

6278

obj_addr_t was_heavy = (address & HEAVY);

6279

if ((address & LOCKED) ||

6280

- !compare_and_swap(&(he -> address), address, (address | LOCKED )))

6281

+ !compare_and_swap(&(he -> address), address, address | LOCKED ))

6282

{

6283

wait_unlocked(he);

6284

goto retry;

6285

Index: gnattools/configure

6286

===================================================================

6287

--- a/src/gnattools/configure (.../tags/gcc_4_8_2_release)

6288

+++ b/src/gnattools/configure (.../branches/gcc-4_8-branch)

6289

@@ -2029,66 +2029,59 @@

6290

# Per-target case statement

6291

# -------------------------

6292

case "${target}" in

6293

- alpha*-dec-vx*) # Unlike all other Vxworks

6294

+ *-*-aix*)

6295

+ TOOLS_TARGET_PAIRS="\

6296

+ mlib-tgt-specific.adb<mlib-tgt-specific-aix.adb \

6297

+ indepsw.adb<indepsw-aix.adb"

6298

;;

6299

- m68k*-wrs-vx* \

6300

- | powerpc*-wrs-vxworks \

6301

- | sparc*-wrs-vx* \

6302

- | *86-wrs-vxworks \

6303

- | mips*-wrs-vx*)

6304

- TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-vxworks.adb"

6305

+ *-*-darwin*)

6306

+ TOOLS_TARGET_PAIRS="\

6307

+ mlib-tgt-specific.adb<mlib-tgt-specific-darwin.adb \

6308

+ indepsw.adb<indepsw-darwin.adb"

6309

;;

6310

- sparc-sun-solaris*)

6311

- TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-solaris.adb"

6312

+ *-*-freebsd*)

6313

+ TOOLS_TARGET_PAIRS="\

6314

+ mlib-tgt-specific.adb<mlib-tgt-specific-linux.adb \

6315

+ indepsw.adb<indepsw-gnu.adb"

6316

;;

6317

- *86-*-solaris2* | x86_64-*-solaris2.1[0-9]*)

6318

- TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-solaris.adb"

6319

- ;;

6320

- *86-*-linux* \

6321

- | powerpc*-*-linux* \

6322

- | *ia64-*-linux* \

6323

- | alpha*-*-linux* \

6324

- | sparc*-*-linux* \

6325

- | hppa*-*-linux* \

6326

- | *x86_64-*-linux*)

6327

+ *-*-linux*)

6328

TOOLS_TARGET_PAIRS="\

6329

mlib-tgt-specific.adb<mlib-tgt-specific-linux.adb \

6330

indepsw.adb<indepsw-gnu.adb"

6331

;;

6332

- s390*-*-linux*)

6333

- TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-linux.adb"

6334

+ *-*-lynxos*)

6335

+ TOOLS_TARGET_PAIRS="\

6336

+ mlib-tgt-specific.adb<mlib-tgt-specific-lynxos.adb \

6337

+ indepsw.adb<indepsw-gnu.adb"

6338

;;

6339

- *86-*-freebsd*)

6340

+ *-*-solaris*)

6341

+ TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-solaris.adb"

6342

+ ;;

6343

+ *-*-vxworks*)

6344

TOOLS_TARGET_PAIRS="\

6345

- mlib-tgt-specific.adb<mlib-tgt-specific-linux.adb \

6346

+ mlib-tgt-specific.adb<mlib-tgt-specific-vxworks.adb \

6347

indepsw.adb<indepsw-gnu.adb"

6348

;;

6349

- hppa*-hp-hpux10*) # Unlike hpux11

6350

+ hppa*-hp-hpux10*)

6351

;;

6352

hppa*-hp-hpux11*)

6353

TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-hpux.adb"

6354

;;

6355

- *-ibm-aix*)

6356

- TOOLS_TARGET_PAIRS="\

6357

- mlib-tgt-specific.adb<mlib-tgt-specific-aix.adb \

6358

- indepsw.adb<indepsw-aix.adb"

6359

+ ia64-hp-hpux11*)

6360

+ TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-ia64-hpux.adb"

6361

;;

6362

- alpha*-dec-vms* | alpha*-dec-openvms* | alpha*-dec-vms* \

6363

- | alpha*-hp-vms* | alpha*-hp-openvms* | alpha*-hp-vms*)

6364

+ alpha*-*-vms* | alpha*-*-openvms*)

6365

TOOLS_TARGET_PAIRS="\

6366

mlib-tgt-specific.adb<mlib-tgt-specific-vms-alpha.adb \

6367

symbols.adb<symbols-vms.adb \

6368

symbols-processing.adb<symbols-processing-vms-alpha.adb"

6369

-

6370

EXTRA_GNATTOOLS='../../gnatlbr$(exeext) ../../gnatsym$(exeext)'

6371

;;

6372

- ia64*-dec-vms* | ia64*-dec-openvms* | ia64*-dec-vms* \

6373

- | ia64*-hp-vms* | ia64*-hp-openvms* | ia64*-hp-vms*)

6374

+ ia64-*-vms* | ia64-*-openvms*)

6375

TOOLS_TARGET_PAIRS="\

6376

mlib-tgt-specific.adb<mlib-tgt-specific-vms-ia64.adb \

6377

symbols.adb<symbols-vms.adb \

6378

symbols-processing.adb<symbols-processing-vms-ia64.adb"

6379

-

6380

EXTRA_GNATTOOLS='../../gnatlbr$(exeext) ../../gnatsym$(exeext)'

6381

;;

6382

*-*-cygwin32* | *-*-mingw32* | *-*-pe)

6383

@@ -2097,14 +2090,6 @@

6384

indepsw.adb<indepsw-mingw.adb"

6385

EXTRA_GNATTOOLS='../../gnatdll$(exeext)'

6386

;;

6387

- *-*-darwin*)

6388

- TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-darwin.adb"

6389

- ;;

6390

- *-*-lynxos)

6391

- TOOLS_TARGET_PAIRS="\

6392

- mlib-tgt-specific.adb<mlib-tgt-specific-lynxos.adb \

6393

- indepsw.adb<indepsw-gnu.adb"

6394

- ;;

6395

esac

6396

6397

# From user or toplevel makefile.

6398

Index: gnattools/Makefile.in

6399

===================================================================

6400

--- a/src/gnattools/Makefile.in (.../tags/gcc_4_8_2_release)

6401

+++ b/src/gnattools/Makefile.in (.../branches/gcc-4_8-branch)

6402

@@ -24,6 +24,8 @@

6403

libdir = @libdir@

6404

build = @build@

6405

target = @target@

6406

+host = @host@

6407

+host_alias = @host_alias@

6408

prefix = @prefix@

6409

INSTALL = @INSTALL@

6410

INSTALL_DATA = @INSTALL_DATA@

6411

@@ -84,6 +86,7 @@

6412

TOOLS_FLAGS_TO_PASS_RE= \

6413

"CC=../../xgcc -B../../" \

6414

"CFLAGS=$(CFLAGS)" \

6415

+ "LDFLAGS=$(LDFLAGS)" \

6416

"ADAFLAGS=$(ADAFLAGS)" \

6417

"ADA_CFLAGS=$(ADA_CFLAGS)" \

6418

"INCLUDES=$(INCLUDES_FOR_SUBDIR)" \

6419

@@ -97,6 +100,22 @@

6420

"TOOLSCASE=cross"

6421

6422

# Variables for gnattools, cross

6423

+ifeq ($(build), $(host))

6424

+ GNATMAKE_FOR_HOST=gnatmake

6425

+ GNATLINK_FOR_HOST=gnatlink

6426

+ GNATBIND_FOR_HOST=gnatbind

6427

+ GNATLS_FOR_HOST=gnatls

6428

+else

6429

+ GNATMAKE_FOR_HOST=$(host_alias)-gnatmake

6430

+ GNATLINK_FOR_HOST=$(host_alias)-gnatlink

6431

+ GNATBIND_FOR_HOST=$(host_alias)-gnatbind

6432

+ GNATLS_FOR_HOST=$(host_alias)-gnatls

6433

+endif

6434

+

6435

+# Put the host RTS dir first in the PATH to hide the default runtime

6436

+# files that are among the sources

6437

+RTS_DIR:=$(strip $(subst \,/,$(shell $(GNATLS_FOR_HOST) -v | grep adalib )))

6438

+

6439

TOOLS_FLAGS_TO_PASS_CROSS= \

6440

"CC=$(CC)" \

6441

"CFLAGS=$(CFLAGS) $(WARN_CFLAGS)" \

6442

@@ -108,9 +127,9 @@

6443

"exeext=$(exeext)" \

6444

"fsrcdir=$(fsrcdir)" \

6445

"srcdir=$(fsrcdir)" \

6446

- "GNATMAKE=gnatmake" \

6447

- "GNATLINK=gnatlink" \

6448

- "GNATBIND=gnatbind" \

6449

+ "GNATMAKE=$(GNATMAKE_FOR_HOST)" \

6450

+ "GNATLINK=$(GNATLINK_FOR_HOST)" \

6451

+ "GNATBIND=$(GNATBIND_FOR_HOST)" \

6452

"TOOLSCASE=cross" \

6453

"LIBGNAT="

6454

6455

@@ -179,11 +198,6 @@

6456

$(MAKE) -C $(GCC_DIR)/ada/tools -f ../Makefile \

6457

$(TOOLS_FLAGS_TO_PASS_NATIVE) common-tools

6458

6459

-# For cross builds of gnattools,

6460

-# put the host RTS dir first in the PATH to hide the default runtime

6461

-# files that are among the sources

6462

-# FIXME: This should be done in configure.

6463

-RTS_DIR:=$(strip $(subst \,/,$(shell gnatls -v | grep adalib )))

6464

gnattools-cross: $(GCC_DIR)/stamp-tools

6465

# gnattools1-re

6466

$(MAKE) -C $(GCC_DIR)/ada/tools -f ../Makefile \

6467

Index: gnattools/configure.ac

6468

===================================================================

6469

--- a/src/gnattools/configure.ac (.../tags/gcc_4_8_2_release)

6470

+++ b/src/gnattools/configure.ac (.../branches/gcc-4_8-branch)

6471

@@ -69,66 +69,59 @@

6472

# Per-target case statement

6473

# -------------------------

6474

case "${target}" in

6475

- alpha*-dec-vx*) # Unlike all other Vxworks

6476

+ *-*-aix*)

6477

+ TOOLS_TARGET_PAIRS="\

6478

+ mlib-tgt-specific.adb<mlib-tgt-specific-aix.adb \

6479

+ indepsw.adb<indepsw-aix.adb"

6480

;;

6481

- m68k*-wrs-vx* \

6482

- | powerpc*-wrs-vxworks \

6483

- | sparc*-wrs-vx* \

6484

- | *86-wrs-vxworks \

6485

- | mips*-wrs-vx*)

6486

- TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-vxworks.adb"

6487

+ *-*-darwin*)

6488

+ TOOLS_TARGET_PAIRS="\

6489

+ mlib-tgt-specific.adb<mlib-tgt-specific-darwin.adb \

6490

+ indepsw.adb<indepsw-darwin.adb"

6491

;;

6492

- sparc-sun-solaris*)

6493

- TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-solaris.adb"

6494

+ *-*-freebsd*)

6495

+ TOOLS_TARGET_PAIRS="\

6496

+ mlib-tgt-specific.adb<mlib-tgt-specific-linux.adb \

6497

+ indepsw.adb<indepsw-gnu.adb"

6498

;;

6499

- *86-*-solaris2* | x86_64-*-solaris2.1[[0-9]]*)

6500

- TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-solaris.adb"

6501

- ;;

6502

- *86-*-linux* \

6503

- | powerpc*-*-linux* \

6504

- | *ia64-*-linux* \

6505

- | alpha*-*-linux* \

6506

- | sparc*-*-linux* \

6507

- | hppa*-*-linux* \

6508

- | *x86_64-*-linux*)

6509

+ *-*-linux*)

6510

TOOLS_TARGET_PAIRS="\

6511

mlib-tgt-specific.adb<mlib-tgt-specific-linux.adb \

6512

indepsw.adb<indepsw-gnu.adb"

6513

;;

6514

- s390*-*-linux*)

6515

- TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-linux.adb"

6516

+ *-*-lynxos*)

6517

+ TOOLS_TARGET_PAIRS="\

6518

+ mlib-tgt-specific.adb<mlib-tgt-specific-lynxos.adb \

6519

+ indepsw.adb<indepsw-gnu.adb"

6520

;;

6521

- *86-*-freebsd*)

6522

+ *-*-solaris*)

6523

+ TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-solaris.adb"

6524

+ ;;

6525

+ *-*-vxworks*)

6526

TOOLS_TARGET_PAIRS="\

6527

- mlib-tgt-specific.adb<mlib-tgt-specific-linux.adb \

6528

+ mlib-tgt-specific.adb<mlib-tgt-specific-vxworks.adb \

6529

indepsw.adb<indepsw-gnu.adb"

6530

;;

6531

- hppa*-hp-hpux10*) # Unlike hpux11

6532

+ hppa*-hp-hpux10*)

6533

;;

6534

hppa*-hp-hpux11*)

6535

TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-hpux.adb"

6536

;;

6537

- *-ibm-aix*)

6538

- TOOLS_TARGET_PAIRS="\

6539

- mlib-tgt-specific.adb<mlib-tgt-specific-aix.adb \

6540

- indepsw.adb<indepsw-aix.adb"

6541

+ ia64-hp-hpux11*)

6542

+ TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-ia64-hpux.adb"

6543

;;

6544

- alpha*-dec-vms* | alpha*-dec-openvms* | alpha*-dec-vms* \

6545

- | alpha*-hp-vms* | alpha*-hp-openvms* | alpha*-hp-vms*)

6546

+ alpha*-*-vms* | alpha*-*-openvms*)

6547

TOOLS_TARGET_PAIRS="\

6548

mlib-tgt-specific.adb<mlib-tgt-specific-vms-alpha.adb \

6549

symbols.adb<symbols-vms.adb \

6550

symbols-processing.adb<symbols-processing-vms-alpha.adb"

6551

-

6552

EXTRA_GNATTOOLS='../../gnatlbr$(exeext) ../../gnatsym$(exeext)'

6553

;;

6554

- ia64*-dec-vms* | ia64*-dec-openvms* | ia64*-dec-vms* \

6555

- | ia64*-hp-vms* | ia64*-hp-openvms* | ia64*-hp-vms*)

6556

+ ia64-*-vms* | ia64-*-openvms*)

6557

TOOLS_TARGET_PAIRS="\

6558

mlib-tgt-specific.adb<mlib-tgt-specific-vms-ia64.adb \

6559

symbols.adb<symbols-vms.adb \

6560

symbols-processing.adb<symbols-processing-vms-ia64.adb"

6561

-

6562

EXTRA_GNATTOOLS='../../gnatlbr$(exeext) ../../gnatsym$(exeext)'

6563

;;

6564

*-*-cygwin32* | *-*-mingw32* | *-*-pe)

6565

@@ -137,14 +130,6 @@

6566

indepsw.adb<indepsw-mingw.adb"

6567

EXTRA_GNATTOOLS='../../gnatdll$(exeext)'

6568

;;

6569

- *-*-darwin*)

6570

- TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-darwin.adb"

6571

- ;;

6572

- *-*-lynxos)

6573

- TOOLS_TARGET_PAIRS="\

6574

- mlib-tgt-specific.adb<mlib-tgt-specific-lynxos.adb \

6575

- indepsw.adb<indepsw-gnu.adb"

6576

- ;;

6577

esac

6578

6579

# From user or toplevel makefile.

6580

Index: gnattools/ChangeLog

6581

===================================================================

6582

--- a/src/gnattools/ChangeLog (.../tags/gcc_4_8_2_release)

6583

+++ b/src/gnattools/ChangeLog (.../branches/gcc-4_8-branch)

6584

@@ -1,3 +1,23 @@

6585

+2013-12-12 Eric Botcazou <ebotcazou@adacore.com>

6586

+ Iain Sandoe <iain@codesourcery.com>

6587

+

6588

+ PR ada/55946

6589

+ * Makefile.in (host): Define.

6590

+ (host_alias): Likewise.

6591

+ (TOOLS_FLAGS_TO_PASS_RE): Add LDFLAGS.

6592

+ (GNATMAKE_FOR_HOST): Define.

6593

+ (GNATLINK_FOR_HOST): Likewise.

6594

+ (GNATBIND_FOR_HOST): Likewise.

6595

+ (GNATLS_FOR_HOST): Likewise.

6596

+ (RTS_DIR): Move around and use GNATLS_FOR_HOST.

6597

+ (TOOLS_FLAGS_TO_PASS_CROSS): Use the other *_HOST variables.

6598

+

6599

+2013-12-04 Eric Botcazou <ebotcazou@adacore.com>

6600

+

6601

+ PR ada/59382

6602

+ * configure.ac (target parameterization): Rewrite.

6603

+ * configure: Regenerate.

6604

+

6605

2013-10-16 Release Manager

6606

6607

* GCC 4.8.2 released.

6608

Index: maintainer-scripts/ChangeLog

6609

===================================================================

6610

--- a/src/maintainer-scripts/ChangeLog (.../tags/gcc_4_8_2_release)

6611

+++ b/src/maintainer-scripts/ChangeLog (.../branches/gcc-4_8-branch)

6612

@@ -1,3 +1,9 @@

6613

+2014-02-01 Dmitry Gorbachev <d.g.gorbachev@gmail.com>

6614

+

6615

+ PR other/56653

6616

+ * gcc_release: Avoid printing empty line to generated MD5SUMS files.

6617

+ Bump copyright year.

6618

+

6619

2013-10-16 Release Manager

6620

6621

* GCC 4.8.2 released.

6622

Index: maintainer-scripts/gcc_release

6623

===================================================================

6624

--- a/src/maintainer-scripts/gcc_release (.../tags/gcc_4_8_2_release)

6625

+++ b/src/maintainer-scripts/gcc_release (.../branches/gcc-4_8-branch)

6626

@@ -9,7 +9,7 @@

6627

# Contents:

6628

# Script to create a GCC release.

6629

#

6630

6631

6632

#

6633

# This file is part of GCC.

6634

#

6635

@@ -213,7 +213,7 @@

6636

#

6637

# Suggested usage:

6638

# md5sum -c MD5SUMS | grep -v \"OK$\"

6639

-" > MD5SUMS

6640

+#" > MD5SUMS

6641

6642

find . -type f |

6643

sed -e 's:^\./::' -e '/MD5SUMS/d' |

6644

Index: libgcc/config.host

6645

===================================================================

6646

--- a/src/libgcc/config.host (.../tags/gcc_4_8_2_release)

6647

+++ b/src/libgcc/config.host (.../branches/gcc-4_8-branch)

6648

@@ -331,10 +331,10 @@

6649

;;

6650

arm*-*-uclinux*) # ARM ucLinux

6651

tmake_file="${tmake_file} t-fixedpoint-gnu-prefix"

6652

+ tmake_file="$tmake_file arm/t-arm arm/t-elf t-softfp-sfdf t-softfp-excl arm/t-softfp t-softfp"

6653

tmake_file="${tmake_file} arm/t-bpabi"

6654

tm_file="$tm_file arm/bpabi-lib.h"

6655

unwind_header=config/arm/unwind-arm.h

6656

- tmake_file="$tmake_file arm/t-arm arm/t-elf t-softfp-sfdf t-softfp-excl arm/t-softfp t-softfp"

6657

extra_parts="$extra_parts crti.o crtn.o"

6658

;;

6659

arm*-*-eabi* | arm*-*-symbianelf* | arm*-*-rtems*)

6660

@@ -718,6 +718,10 @@

6661

tmake_file="${tmake_file} microblaze/t-microblaze t-fdpbit"

6662

extra_parts="$extra_parts crtbeginS.o crtendS.o crtbeginT.o crti.o crtn.o"

6663

;;

6664

+microblaze*-*-rtems*)

6665

+ tmake_file="${tmake_file} microblaze/t-microblaze t-fdpbit"

6666

+ extra_parts="$extra_parts crtbeginS.o crtendS.o crtbeginT.o crti.o crtn.o"

6667

+ ;;

6668

mips*-*-netbsd*) # NetBSD/mips, either endian.

6669

;;

6670

mips*-*-linux*) # Linux MIPS, either endian.

6671

@@ -1081,7 +1085,7 @@

6672

md_unwind_header=tilepro/linux-unwind.h

6673

;;

6674

v850*-*-*)

6675

- tmake_file="v850/t-v850 t-fdpbit"

6676

+ tmake_file="${tmake_file} v850/t-v850 t-fdpbit"

6677

;;

6678

vax-*-linux*)

6679

tmake_file="$tmake_file vax/t-linux"

6680

@@ -1098,7 +1102,7 @@

6681

extra_parts="$extra_parts crti.o crtn.o"

6682

;;

6683

xtensa*-*-linux*)

6684

- tmake_file="$tmake_file xtensa/t-xtensa xtensa/t-linux"

6685

+ tmake_file="$tmake_file xtensa/t-xtensa xtensa/t-linux t-slibgcc-libgcc"

6686

md_unwind_header=xtensa/linux-unwind.h

6687

;;

6688

am33_2.0-*-linux*)

6689

Index: libgcc/ChangeLog

6690

===================================================================

6691

--- a/src/libgcc/ChangeLog (.../tags/gcc_4_8_2_release)

6692

+++ b/src/libgcc/ChangeLog (.../branches/gcc-4_8-branch)

6693

@@ -1,3 +1,206 @@

6694

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

6695

+

6696

+ Backport from mainline r204808:

6697

+

6698

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

6699

+ Alan Modra <amodra@gmail.com>

6700

+

6701

+ * config/rs6000/linux-unwind.h (TOC_SAVE_SLOT): Define.

6702

+ (frob_update_context): Use it.

6703

+

6704

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

6705

+ Alan Modra <amodra@gmail.com>

6706

+

6707

+ * config/rs6000/tramp.S [__powerpc64__ && _CALL_ELF == 2]:

6708

+ (trampoline_initial): Provide ELFv2 variant.

6709

+ (__trampoline_setup): Likewise.

6710

+

6711

+ * config/rs6000/linux-unwind.h (frob_update_context): Do not

6712

+ check for AIX indirect function call sequence if _CALL_ELF == 2.

6713

+

6714

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

6715

+ Alan Modra <amodra@gmail.com>

6716

+

6717

+ * config/rs6000/linux-unwind.h (get_regs): Do not support

6718

+ old kernel versions if _CALL_ELF == 2.

6719

+ (frob_update_context): Do not support PLT stub variants only

6720

+ generated by old linkers if _CALL_ELF == 2.

6721

+

6722

+ Backport from mainline r204800:

6723

+

6724

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

6725

+ Alan Modra <amodra@gmail.com>

6726

+

6727

+ * config/rs6000/linux-unwind.h (ppc_fallback_frame_state): Correct

6728

+ location of CR save area for 64-bit little-endian systems.

6729

+

6730

+2014-03-20 Joel Sherrill <joel.sherrill@oarcorp.com>

6731

+

6732

+ * config.host (v850*-*-*): Add to tmake_file instead of resetting it.

6733

+

6734

+2014-02-28 Joey Ye <joey.ye@arm.com>

6735

+

6736

+ Backport from mainline r208229

6737

+ 2014-02-28 Joey Ye <joey.ye@arm.com>

6738

+

6739

+ PR libgcc/60166

6740

+ * config/arm/sfp-machine.h (_FP_NANFRAC_H,

6741

+ _FP_NANFRAC_S, _FP_NANFRAC_D, _FP_NANFRAC_Q):

6742

+ Set to zero.

6743

+

6744

+2014-02-18 Kai Tietz <ktietz@redhat.com>

6745

+ Jonathan Schleifer <js@webkeks.org>

6746

+

6747

+ PR objc/56870

6748

+ * unwind-seh.c (_GCC_specific_handler): Pass proper

6749

+ value to unwind-handler.

6750

+

6751

+2014-01-25 Walter Lee <walt@tilera.com>

6752

+

6753

+ Backport from mainline

6754

+ 2014-01-25 Walter Lee <walt@tilera.com>

6755

+

6756

+ * config/tilepro/atomic.c (pre_atomic_barrier): Mark inline.

6757

+ (post_atomic_barrier): Ditto.

6758

+ (__fetch_and_do): New macro.

6759

+ (__atomic_fetch_and_do): Use __fetch_and_do.

6760

+ (__sync_fetch_and_do): New macro.

6761

+ (__sync_fetch_and_add_4): New function.

6762

+ (__sync_fetch_and_sub_4): New function.

6763

+ (__sync_fetch_and_or_4): New function.

6764

+ (__sync_fetch_and_and_4): New function.

6765

+ (__sync_fetch_and_xor_4): New function.

6766

+ (__sync_fetch_and_nand_4): New function.

6767

+ (__sync_fetch_and_add_8): New function.

6768

+ (__sync_fetch_and_sub_8): New function.

6769

+ (__sync_fetch_and_or_8): New function.

6770

+ (__sync_fetch_and_and_8): New function.

6771

+ (__sync_fetch_and_xor_8): New function.

6772

+ (__sync_fetch_and_nand_8): New function.

6773

+ (__do_and_fetch): New macro.

6774

+ (__atomic_do_and_fetch): Use __do_and_fetch.

6775

+ (__sync_do_and_fetch): New macro.

6776

+ (__sync_add_and_fetch_4): New function.

6777

+ (__sync_sub_and_fetch_4): New function.

6778

+ (__sync_or_and_fetch_4): New function.

6779

+ (__sync_and_and_fetch_4): New function.

6780

+ (__sync_xor_and_fetch_4): New function.

6781

+ (__sync_nand_and_fetch_4): New function.

6782

+ (__sync_add_and_fetch_8): New function.

6783

+ (__sync_sub_and_fetch_8): New function.

6784

+ (__sync_or_and_fetch_8): New function.

6785

+ (__sync_and_and_fetch_8): New function.

6786

+ (__sync_xor_and_fetch_8): New function.

6787

+ (__sync_nand_and_fetch_8): New function.

6788

+ (__sync_exchange_methods): New macro.

6789

+ (__sync_val_compare_and_swap_4): New function.

6790

+ (__sync_bool_compare_and_swap_4): New function.

6791

+ (__sync_lock_test_and_test_4): New function.

6792

+ (__sync_val_compare_and_swap_8): New function.

6793

+ (__sync_bool_compare_and_swap_8): New function.

6794

+ (__sync_lock_test_and_test_8): New function.

6795

+ (__subword_cmpxchg_body): New macro.

6796

+ (__atomic_compare_exchange_1): Use __subword_cmpxchg_body.

6797

+ (__atomic_compare_exchange_2): Ditto.

6798

+ (__sync_subword_cmpxchg): New macro.

6799

+ (__sync_val_compare_and_swap_1): New function.

6800

+ (__sync_bool_compare_and_swap_1): New function.

6801

+ (__sync_val_compare_and_swap_2): New function.

6802

+ (__sync_bool_compare_and_swap_2): New function.

6803

+ (__atomic_subword): Rename to ...

6804

+ (__subword): ... New name.

6805

+ (__atomic_subword_fetch): Use __subword.

6806

+ (__sync_subword_fetch): New macro.

6807

+ (__sync_fetch_and_add_1): New function.

6808

+ (__sync_fetch_and_sub_1): New function.

6809

+ (__sync_fetch_and_or_1): New function.

6810

+ (__sync_fetch_and_and_1): New function.

6811

+ (__sync_fetch_and_xor_1): New function.

6812

+ (__sync_fetch_and_nand_1): New function.

6813

+ (__sync_fetch_and_add_2): New function.

6814

+ (__sync_fetch_and_sub_2): New function.

6815

+ (__sync_fetch_and_or_2): New function.

6816

+ (__sync_fetch_and_and_2): New function.

6817

+ (__sync_fetch_and_xor_2): New function.

6818

+ (__sync_fetch_and_nand_2): New function.

6819

+ (__sync_add_and_fetch_1): New function.

6820

+ (__sync_sub_and_fetch_1): New function.

6821

+ (__sync_or_and_fetch_1): New function.

6822

+ (__sync_and_and_fetch_1): New function.

6823

+ (__sync_xor_and_fetch_1): New function.

6824

+ (__sync_nand_and_fetch_1): New function.

6825

+ (__sync_add_and_fetch_2): New function.

6826

+ (__sync_sub_and_fetch_2): New function.

6827

+ (__sync_or_and_fetch_2): New function.

6828

+ (__sync_and_and_fetch_2): New function.

6829

+ (__sync_xor_and_fetch_2): New function.

6830

+ (__sync_nand_and_fetch_2): New function.

6831

+ (__atomic_subword_lock): Use __subword.

6832

+ (__sync_subword_lock): New macro.

6833

+ (__sync_lock_test_and_set_1): New function.

6834

+ (__sync_lock_test_and_set_2): New function.

6835

+

6836

+2014-01-25 Walter Lee <walt@tilera.com>

6837

+

6838

+ Backport from mainline

6839

+ 2014-01-25 Walter Lee <walt@tilera.com>

6840

+

6841

+ * config/tilepro/atomic.c (BIT_OFFSET): Define.

6842

+ (__atomic_subword_cmpxchg): Use BIT_OFFSET.

6843

+ (__atomic_subword): Ditto.

6844

+

6845

+2014-01-25 Walter Lee <walt@tilera.com>

6846

+

6847

+ Backport from mainline

6848

+ 2014-01-25 Walter Lee <walt@tilera.com>

6849

+

6850

+ * config/tilepro/atomic.c (__atomic_do_and_fetch): Add

6851

+ a prefix op argument.

6852

+ (__atomic_nand_fetch_4): Add prefix op.

6853

+ (__atomic_nand_fetch_8): Ditto.

6854

+

6855

+2014-01-21 Baruch Siach <barch@tkos.co.il>

6856

+

6857

+ * config.host (tmake_file): add t-slibgcc-libgcc for xtensa*-*-linux*.

6858

+

6859

+2014-01-03 Joseph Myers <joseph@codesourcery.com>

6860

+

6861

+ * config/rs6000/ibm-ldouble.c (__gcc_qdiv): Scale up arguments in

6862

+ case of small numerator and finite nonzero result.

6863

+

6864

+2013-12-12 Zhenqiang Chen <zhenqiang.chen@arm.com>

6865

+

6866

+ Backport from trunk r205917.

6867

+ 2013-12-12 Zhenqiang Chen <zhenqiang.chen@arm.com>

6868

+ * config.host (arm*-*-uclinux*): Move t-arm before t-bpabi.

6869

+

6870

+2013-12-10 Uros Bizjak <ubizjak@gmail.com>

6871

+

6872

+ * config/i386/sfp-exceptions.c (__sfp_handle_exceptions): Emit SSE

6873

+ instructions when __SSE_MATH__ is defined.

6874

+

6875

+2013-12-06 Ralf Corsépius <ralf.corsepius@rtems.org>

6876

+

6877

+ * config.host (microblaze-*-rtems*): New.

6878

+

6879

+2013-11-10 Kai Tietz <ktietz@redhat.com>

6880

+

6881

+ Back-merged from trunk

6882

+ * config/i386/cygming-crtbegin.c (__gcc_register_frame):

6883

+ Increment load-count on use of LIBGCC_SONAME DLL.

6884

+ (hmod_libgcc): New static variable to hold handle of

6885

+ LIBGCC_SONAME DLL.

6886

+ (__gcc_deregister_frame): Decrement load-count of

6887

+ LIBGCC_SONAME DLL.

6888

+

6889

+2013-11-07 Uros Bizjak <ubizjak@gmail.com>

6890

+

6891

+ * config/i386/sfp-exceptions.c (__sfp_handle_exceptions): Handle

6892

+ FP_EX_DENORM. Store result to volatile location after SSE division

6893

+ to close interrupt window. Remove unneeded fwait after x87

6894

+ division since interrupt window will be closed by emitted fstp.

6895

+ Rewrite FP_EX_INEXACT handling.

6896

+

6897

2013-10-16 Release Manager

6898

6899

* GCC 4.8.2 released.

6900

@@ -151,7 +354,7 @@

6901

* config/mips/crtn.S (fini, init): New labels.

6902

6903

2012-02-19 Edgar E. Iglesias <edgar.iglesias@gmail.com>

6904

- * config/microblaze/modsi3.S (modsi3): Fix case with 0x80000000

6905

+ * config/microblaze/modsi3.S (modsi3): Fix case with 0x80000000

6906

as dividend.

6907

6908

2013-02-16 Alan Modra <amodra@gmail.com>

6909

Index: libgcc/config/i386/sfp-exceptions.c

6910

===================================================================

6911

--- a/src/libgcc/config/i386/sfp-exceptions.c (.../tags/gcc_4_8_2_release)

6912

+++ b/src/libgcc/config/i386/sfp-exceptions.c (.../branches/gcc-4_8-branch)

6913

@@ -47,21 +47,33 @@

6914

if (_fex & FP_EX_INVALID)

6915

{

6916

float f = 0.0f;

6917

-#ifdef __x86_64__

6918

+#ifdef __SSE_MATH__

6919

+ volatile float r __attribute__ ((unused));

6920

asm volatile ("%vdivss\t{%0, %d0|%d0, %0}" : "+x" (f));

6921

+ r = f; /* Needed to trigger exception. */

6922

#else

6923

asm volatile ("fdiv\t{%y0, %0|%0, %y0}" : "+t" (f));

6924

- asm volatile ("fwait");

6925

+ /* No need for fwait, exception is triggered by emitted fstp. */

6926

#endif

6927

}

6928

+ if (_fex & FP_EX_DENORM)

6929

+ {

6930

+ struct fenv temp;

6931

+ asm volatile ("fnstenv\t%0" : "=m" (temp));

6932

+ temp.__status_word |= FP_EX_DENORM;

6933

+ asm volatile ("fldenv\t%0" : : "m" (temp));

6934

+ asm volatile ("fwait");

6935

+ }

6936

if (_fex & FP_EX_DIVZERO)

6937

{

6938

float f = 1.0f, g = 0.0f;

6939

-#ifdef __x86_64__

6940

+#ifdef __SSE_MATH__

6941

+ volatile float r __attribute__ ((unused));

6942

asm volatile ("%vdivss\t{%1, %d0|%d0, %1}" : "+x" (f) : "xm" (g));

6943

+ r = f; /* Needed to trigger exception. */

6944

#else

6945

asm volatile ("fdivs\t%1" : "+t" (f) : "m" (g));

6946

- asm volatile ("fwait");

6947

+ /* No need for fwait, exception is triggered by emitted fstp. */

6948

#endif

6949

}

6950

if (_fex & FP_EX_OVERFLOW)

6951

@@ -82,11 +94,15 @@

6952

}

6953

if (_fex & FP_EX_INEXACT)

6954

{

6955

- struct fenv temp;

6956

- asm volatile ("fnstenv\t%0" : "=m" (temp));

6957

- temp.__status_word |= FP_EX_INEXACT;

6958

- asm volatile ("fldenv\t%0" : : "m" (temp));

6959

- asm volatile ("fwait");

6960

+ float f = 1.0f, g = 3.0f;

6961

+#ifdef __SSE_MATH__

6962

+ volatile float r __attribute__ ((unused));

6963

+ asm volatile ("%vdivss\t{%1, %d0|%d0, %1}" : "+x" (f) : "xm" (g));

6964

+ r = f; /* Needed to trigger exception. */

6965

+#else

6966

+ asm volatile ("fdivs\t%1" : "+t" (f) : "m" (g));

6967

+ /* No need for fwait, exception is triggered by emitted fstp. */

6968

+#endif

6969

}

6970

};

6971

#endif

6972

Index: libgcc/config/i386/cygming-crtbegin.c

6973

===================================================================

6974

--- a/src/libgcc/config/i386/cygming-crtbegin.c (.../tags/gcc_4_8_2_release)

6975

+++ b/src/libgcc/config/i386/cygming-crtbegin.c (.../branches/gcc-4_8-branch)

6976

@@ -69,6 +69,9 @@

6977

= { };

6978

6979

static struct object obj;

6980

+

6981

+/* Handle of libgcc's DLL reference. */

6982

+HANDLE hmod_libgcc;

6983

#endif

6984

6985

#if TARGET_USE_JCR_SECTION

6986

@@ -93,9 +96,14 @@

6987

6988

void (*register_frame_fn) (const void *, struct object *);

6989

HANDLE h = GetModuleHandle (LIBGCC_SONAME);

6990

+

6991

if (h)

6992

- register_frame_fn = (void (*) (const void *, struct object *))

6993

- GetProcAddress (h, "__register_frame_info");

6994

+ {

6995

+ /* Increasing the load-count of LIBGCC_SONAME DLL. */

6996

+ hmod_libgcc = LoadLibrary (LIBGCC_SONAME);

6997

+ register_frame_fn = (void (*) (const void *, struct object *))

6998

+ GetProcAddress (h, "__register_frame_info");

6999

+ }

7000

else

7001

register_frame_fn = __register_frame_info;

7002

if (register_frame_fn)

7003

@@ -132,5 +140,7 @@

7004

deregister_frame_fn = __deregister_frame_info;

7005

if (deregister_frame_fn)

7006

deregister_frame_fn (__EH_FRAME_BEGIN__);

7007

+ if (hmod_libgcc)

7008

+ FreeLibrary (hmod_libgcc);

7009

#endif

7010

}

7011

Index: libgcc/config/rs6000/tramp.S

7012

===================================================================

7013

--- a/src/libgcc/config/rs6000/tramp.S (.../tags/gcc_4_8_2_release)

7014

+++ b/src/libgcc/config/rs6000/tramp.S (.../branches/gcc-4_8-branch)

7015

@@ -116,4 +116,70 @@

7016

7017

#endif

7018

7019

+#elif _CALL_ELF == 2

7020

+ .type trampoline_initial,@object

7021

+ .align 3

7022

+trampoline_initial:

7023

+ ld r11,.Lchain(r12)

7024

+ ld r12,.Lfunc(r12)

7025

+ mtctr r12

7026

+ bctr

7027

+.Lfunc = .-trampoline_initial

7028

+ .quad 0 /* will be replaced with function address */

7029

+.Lchain = .-trampoline_initial

7030

+ .quad 0 /* will be replaced with static chain */

7031

+

7032

+trampoline_size = .-trampoline_initial

7033

+ .size trampoline_initial,trampoline_size

7034

+

7035

+

7036

+/* R3 = stack address to store trampoline */

7037

+/* R4 = length of trampoline area */

7038

+/* R5 = function address */

7039

+/* R6 = static chain */

7040

+

7041

+ .pushsection ".toc","aw"

7042

+.LC0:

7043

+ .quad trampoline_initial-8

7044

+ .popsection

7045

+

7046

+FUNC_START(__trampoline_setup)

7047

+ addis 7,2,.LC0@toc@ha

7048

+ ld 7,.LC0@toc@l(7) /* trampoline address -8 */

7049

+

7050

+ li r8,trampoline_size /* verify that the trampoline is big enough */

7051

+ cmpw cr1,r8,r4

7052

+ srwi r4,r4,3 /* # doublewords to move */

7053

+ addi r9,r3,-8 /* adjust pointer for stdu */

7054

+ mtctr r4

7055

+ blt cr1,.Labort

7056

+

7057

+ /* Copy the instructions to the stack */

7058

+.Lmove:

7059

+ ldu r10,8(r7)

7060

+ stdu r10,8(r9)

7061

+ bdnz .Lmove

7062

+

7063

+ /* Store correct function and static chain */

7064

+ std r5,.Lfunc(r3)

7065

+ std r6,.Lchain(r3)

7066

+

7067

+ /* Now flush both caches */

7068

+ mtctr r4

7069

+.Lcache:

7070

+ icbi 0,r3

7071

+ dcbf 0,r3

7072

+ addi r3,r3,8

7073

+ bdnz .Lcache

7074

+

7075

+ /* Finally synchronize things & return */

7076

+ sync

7077

+ isync

7078

+ blr

7079

+

7080

+.Labort:

7081

+ bl JUMP_TARGET(abort)

7082

+ nop

7083

+FUNC_END(__trampoline_setup)

7084

+

7085

#endif

7086

Index: libgcc/config/rs6000/linux-unwind.h

7087

===================================================================

7088

--- a/src/libgcc/config/rs6000/linux-unwind.h (.../tags/gcc_4_8_2_release)

7089

+++ b/src/libgcc/config/rs6000/linux-unwind.h (.../branches/gcc-4_8-branch)

7090

@@ -24,9 +24,19 @@

7091

7092

#define R_LR 65

7093

#define R_CR2 70

7094

+#define R_CR3 71

7095

+#define R_CR4 72

7096

#define R_VR0 77

7097

#define R_VRSAVE 109

7098

7099

+#ifdef __powerpc64__

7100

+#if _CALL_ELF == 2

7101

+#define TOC_SAVE_SLOT 24

7102

+#else

7103

+#define TOC_SAVE_SLOT 40

7104

+#endif

7105

+#endif

7106

+

7107

struct gcc_vregs

7108

{

7109

__attribute__ ((vector_size (16))) int vr[32];

7110

@@ -107,6 +117,8 @@

7111

}

7112

else if (pc[1] == 0x380000AC)

7113

{

7114

+#if _CALL_ELF != 2

7115

+ /* These old kernel versions never supported ELFv2. */

7116

/* This works for 2.4 kernels, but not for 2.6 kernels with vdso

7117

because pc isn't pointing into the stack. Can be removed when

7118

no one is running 2.4.19 or 2.4.20, the first two ppc64

7119

@@ -121,6 +133,7 @@

7120

if ((long) frame24->puc != -21 * 8)

7121

return frame24->puc->regs;

7122

else

7123

+#endif

7124

{

7125

/* This works for 2.4.21 and later kernels. */

7126

struct rt_sigframe {

7127

@@ -185,6 +198,7 @@

7128

{

7129

struct gcc_regs *regs = get_regs (context);

7130

struct gcc_vregs *vregs;

7131

+ long cr_offset;

7132

long new_cfa;

7133

int i;

7134

7135

@@ -206,11 +220,21 @@

7136

fs->regs.reg[i].loc.offset = (long) &regs->gpr[i] - new_cfa;

7137

}

7138

7139

+ /* The CR is saved in the low 32 bits of regs->ccr. */

7140

+ cr_offset = (long) &regs->ccr - new_cfa;

7141

+#ifndef __LITTLE_ENDIAN__

7142

+ cr_offset += sizeof (long) - 4;

7143

+#endif

7144

+ /* In the ELFv1 ABI, CR2 stands in for the whole CR. */

7145

fs->regs.reg[R_CR2].how = REG_SAVED_OFFSET;

7146

- /* CR? regs are always 32-bit and PPC is big-endian, so in 64-bit

7147

- libgcc loc.offset needs to point to the low 32 bits of regs->ccr. */

7148

- fs->regs.reg[R_CR2].loc.offset = (long) &regs->ccr - new_cfa

7149

- + sizeof (long) - 4;

7150

+ fs->regs.reg[R_CR2].loc.offset = cr_offset;

7151

+#if _CALL_ELF == 2

7152

+ /* In the ELFv2 ABI, every CR field has a separate CFI entry. */

7153

+ fs->regs.reg[R_CR3].how = REG_SAVED_OFFSET;

7154

+ fs->regs.reg[R_CR3].loc.offset = cr_offset;

7155

+ fs->regs.reg[R_CR4].how = REG_SAVED_OFFSET;

7156

+ fs->regs.reg[R_CR4].loc.offset = cr_offset;

7157

+#endif

7158

7159

fs->regs.reg[R_LR].how = REG_SAVED_OFFSET;

7160

fs->regs.reg[R_LR].loc.offset = (long) &regs->link - new_cfa;

7161

@@ -294,9 +318,13 @@

7162

figure out if it was saved. The big problem here is that the

7163

code that does the save/restore is generated by the linker, so

7164

we have no good way to determine at compile time what to do. */

7165

- if (pc[0] == 0xF8410028

7166

+ if (pc[0] == 0xF8410000 + TOC_SAVE_SLOT

7167

+#if _CALL_ELF != 2

7168

+ /* The ELFv2 linker never generates the old PLT stub form. */

7169

|| ((pc[0] & 0xFFFF0000) == 0x3D820000

7170

- && pc[1] == 0xF8410028))

7171

+ && pc[1] == 0xF8410000 + TOC_SAVE_SLOT)

7172

+#endif

7173

+ )

7174

{

7175

/* We are in a plt call stub or r2 adjusting long branch stub,

7176

before r2 has been saved. Keep REG_UNSAVED. */

7177

@@ -305,10 +333,12 @@

7178

{

7179

unsigned int *insn

7180

= (unsigned int *) _Unwind_GetGR (context, R_LR);

7181

- if (insn && *insn == 0xE8410028)

7182

- _Unwind_SetGRPtr (context, 2, context->cfa + 40);

7183

+ if (insn && *insn == 0xE8410000 + TOC_SAVE_SLOT)

7184

+ _Unwind_SetGRPtr (context, 2, context->cfa + TOC_SAVE_SLOT);

7185

+#if _CALL_ELF != 2

7186

+ /* ELFv2 does not use this function pointer call sequence. */

7187

else if (pc[0] == 0x4E800421

7188

- && pc[1] == 0xE8410028)

7189

+ && pc[1] == 0xE8410000 + TOC_SAVE_SLOT)

7190

{

7191

/* We are at the bctrl instruction in a call via function

7192

pointer. gcc always emits the load of the new R2 just

7193

@@ -315,8 +345,9 @@

7194

before the bctrl so this is the first and only place

7195

we need to use the stored R2. */

7196

_Unwind_Word sp = _Unwind_GetGR (context, 1);

7197

- _Unwind_SetGRPtr (context, 2, (void *)(sp + 40));

7198

+ _Unwind_SetGRPtr (context, 2, (void *)(sp + TOC_SAVE_SLOT));

7199

}

7200

+#endif

7201

}

7202

}

7203

#endif

7204

Index: libgcc/config/rs6000/ibm-ldouble.c

7205

===================================================================

7206

--- a/src/libgcc/config/rs6000/ibm-ldouble.c (.../tags/gcc_4_8_2_release)

7207

+++ b/src/libgcc/config/rs6000/ibm-ldouble.c (.../branches/gcc-4_8-branch)

7208

@@ -188,7 +188,16 @@

7209

|| nonfinite (t))

7210

return t;

7211

7212

- /* Finite nonzero result requires corrections to the highest order term. */

7213

+ /* Finite nonzero result requires corrections to the highest order

7214

+ term. These corrections require the low part of c * t to be

7215

+ exactly represented in double. */

7216

+ if (fabs (a) <= 0x1p-969)

7217

+ {

7218

+ a *= 0x1p106;

7219

+ b *= 0x1p106;

7220

+ c *= 0x1p106;

7221

+ d *= 0x1p106;

7222

+ }

7223

7224

s = c * t; /* (s,sigma) = c*t exactly. */

7225

w = -(-b + d * t); /* Written to get fnmsub for speed, but not

7226

Index: libgcc/config/tilepro/atomic.c

7227

===================================================================

7228

--- a/src/libgcc/config/tilepro/atomic.c (.../tags/gcc_4_8_2_release)

7229

+++ b/src/libgcc/config/tilepro/atomic.c (.../branches/gcc-4_8-branch)

7230

@@ -28,7 +28,7 @@

7231

/* This code should be inlined by the compiler, but for now support

7232

it as out-of-line methods in libgcc. */

7233

7234

-static void

7235

+static inline void

7236

pre_atomic_barrier (int model)

7237

{

7238

switch ((enum memmodel) model)

7239

@@ -44,7 +44,7 @@

7240

return;

7241

}

7242

7243

-static void

7244

+static inline void

7245

post_atomic_barrier (int model)

7246

{

7247

switch ((enum memmodel) model)

7248

@@ -62,16 +62,21 @@

7249

7250

#define __unused __attribute__((unused))

7251

7252

-#define __atomic_fetch_and_do(type, size, opname) \

7253

-type \

7254

-__atomic_fetch_##opname##_##size(type* p, type i, int model) \

7255

+#define __fetch_and_do(proto, type, size, opname, top, bottom) \

7256

+proto \

7257

{ \

7258

- pre_atomic_barrier(model); \

7259

+ top; \

7260

type rv = arch_atomic_##opname(p, i); \

7261

- post_atomic_barrier(model); \

7262

+ bottom; \

7263

return rv; \

7264

}

7265

7266

+#define __atomic_fetch_and_do(type, size, opname) \

7267

+ __fetch_and_do(type __atomic_fetch_##opname##_##size(type* p, type i, int model), \

7268

+ type, size, opname, \

7269

+ pre_atomic_barrier(model), \

7270

+ post_atomic_barrier(model)) \

7271

+

7272

__atomic_fetch_and_do (int, 4, add)

7273

__atomic_fetch_and_do (int, 4, sub)

7274

__atomic_fetch_and_do (int, 4, or)

7275

@@ -84,27 +89,73 @@

7276

__atomic_fetch_and_do (long long, 8, and)

7277

__atomic_fetch_and_do (long long, 8, xor)

7278

__atomic_fetch_and_do (long long, 8, nand)

7279

-#define __atomic_do_and_fetch(type, size, opname, op) \

7280

-type \

7281

-__atomic_##opname##_fetch_##size(type* p, type i, int model) \

7282

-{ \

7283

- pre_atomic_barrier(model); \

7284

- type rv = arch_atomic_##opname(p, i) op i; \

7285

- post_atomic_barrier(model); \

7286

- return rv; \

7287

+

7288

+#define __sync_fetch_and_do(type, size, opname) \

7289

+ __fetch_and_do(type __sync_fetch_and_##opname##_##size(type* p, type i), \

7290

+ type, size, opname, \

7291

+ arch_atomic_write_barrier(), \

7292

+ arch_atomic_read_barrier())

7293

+

7294

+__sync_fetch_and_do (int, 4, add)

7295

+__sync_fetch_and_do (int, 4, sub)

7296

+__sync_fetch_and_do (int, 4, or)

7297

+__sync_fetch_and_do (int, 4, and)

7298

+__sync_fetch_and_do (int, 4, xor)

7299

+__sync_fetch_and_do (int, 4, nand)

7300

+__sync_fetch_and_do (long long, 8, add)

7301

+__sync_fetch_and_do (long long, 8, sub)

7302

+__sync_fetch_and_do (long long, 8, or)

7303

+__sync_fetch_and_do (long long, 8, and)

7304

+__sync_fetch_and_do (long long, 8, xor)

7305

+__sync_fetch_and_do (long long, 8, nand)

7306

+

7307

+#define __do_and_fetch(proto, type, size, opname, op, op2, top, bottom) \

7308

+proto \

7309

+{ \

7310

+ top; \

7311

+ type rv = op2 (arch_atomic_##opname(p, i) op i); \

7312

+ bottom; \

7313

+ return rv; \

7314

}

7315

-__atomic_do_and_fetch (int, 4, add, +)

7316

-__atomic_do_and_fetch (int, 4, sub, -)

7317

-__atomic_do_and_fetch (int, 4, or, |)

7318

-__atomic_do_and_fetch (int, 4, and, &)

7319

-__atomic_do_and_fetch (int, 4, xor, |)

7320

-__atomic_do_and_fetch (int, 4, nand, &)

7321

-__atomic_do_and_fetch (long long, 8, add, +)

7322

-__atomic_do_and_fetch (long long, 8, sub, -)

7323

-__atomic_do_and_fetch (long long, 8, or, |)

7324

-__atomic_do_and_fetch (long long, 8, and, &)

7325

-__atomic_do_and_fetch (long long, 8, xor, |)

7326

-__atomic_do_and_fetch (long long, 8, nand, &)

7327

+

7328

+#define __atomic_do_and_fetch(type, size, opname, op, op2) \

7329

+ __do_and_fetch(type __atomic_##opname##_fetch_##size(type* p, type i, int model), \

7330

+ type, size, opname, op, op2, \

7331

+ pre_atomic_barrier(model), \

7332

+ post_atomic_barrier(model)) \

7333

+

7334

+__atomic_do_and_fetch (int, 4, add, +, )

7335

+__atomic_do_and_fetch (int, 4, sub, -, )

7336

+__atomic_do_and_fetch (int, 4, or, |, )

7337

+__atomic_do_and_fetch (int, 4, and, &, )

7338

+__atomic_do_and_fetch (int, 4, xor, |, )

7339

+__atomic_do_and_fetch (int, 4, nand, &, ~)

7340

+__atomic_do_and_fetch (long long, 8, add, +, )

7341

+__atomic_do_and_fetch (long long, 8, sub, -, )

7342

+__atomic_do_and_fetch (long long, 8, or, |, )

7343

+__atomic_do_and_fetch (long long, 8, and, &, )

7344

+__atomic_do_and_fetch (long long, 8, xor, |, )

7345

+__atomic_do_and_fetch (long long, 8, nand, &, ~)

7346

+

7347

+#define __sync_do_and_fetch(type, size, opname, op, op2) \

7348

+ __do_and_fetch(type __sync_##opname##_and_fetch_##size(type* p, type i), \

7349

+ type, size, opname, op, op2, \

7350

+ arch_atomic_write_barrier(), \

7351

+ arch_atomic_read_barrier()) \

7352

+

7353

+__sync_do_and_fetch (int, 4, add, +, )

7354

+__sync_do_and_fetch (int, 4, sub, -, )

7355

+__sync_do_and_fetch (int, 4, or, |, )

7356

+__sync_do_and_fetch (int, 4, and, &, )

7357

+__sync_do_and_fetch (int, 4, xor, |, )

7358

+__sync_do_and_fetch (int, 4, nand, &, ~)

7359

+__sync_do_and_fetch (long long, 8, add, +, )

7360

+__sync_do_and_fetch (long long, 8, sub, -, )

7361

+__sync_do_and_fetch (long long, 8, or, |, )

7362

+__sync_do_and_fetch (long long, 8, and, &, )

7363

+__sync_do_and_fetch (long long, 8, xor, |, )

7364

+__sync_do_and_fetch (long long, 8, nand, &, ~)

7365

+

7366

#define __atomic_exchange_methods(type, size) \

7367

bool \

7368

__atomic_compare_exchange_##size(volatile type* ptr, type* oldvalp, \

7369

@@ -128,49 +179,117 @@

7370

post_atomic_barrier(model); \

7371

return retval; \

7372

}

7373

+

7374

__atomic_exchange_methods (int, 4)

7375

__atomic_exchange_methods (long long, 8)

7376

7377

+#define __sync_exchange_methods(type, size) \

7378

+type \

7379

+__sync_val_compare_and_swap_##size(type* ptr, type oldval, type newval) \

7380

+{ \

7381

+ arch_atomic_write_barrier(); \

7382

+ type retval = arch_atomic_val_compare_and_exchange(ptr, oldval, newval); \

7383

+ arch_atomic_read_barrier(); \

7384

+ return retval; \

7385

+} \

7386

+ \

7387

+bool \

7388

+__sync_bool_compare_and_swap_##size(type* ptr, type oldval, type newval) \

7389

+{ \

7390

+ arch_atomic_write_barrier(); \

7391

+ bool retval = arch_atomic_bool_compare_and_exchange(ptr, oldval, newval); \

7392

+ arch_atomic_read_barrier(); \

7393

+ return retval; \

7394

+} \

7395

+ \

7396

+type \

7397

+__sync_lock_test_and_set_##size(type* ptr, type val) \

7398

+{ \

7399

+ type retval = arch_atomic_exchange(ptr, val); \

7400

+ arch_atomic_acquire_barrier_value(retval); \

7401

+ return retval; \

7402

+}

7403

+

7404

+__sync_exchange_methods (int, 4)

7405

+__sync_exchange_methods (long long, 8)

7406

+

7407

+#ifdef __LITTLE_ENDIAN__

7408

+#define BIT_OFFSET(n, type) ((n) * 8)

7409

+#else

7410

+#define BIT_OFFSET(n, type) ((4 - sizeof(type) - (n)) * 8)

7411

+#endif

7412

+

7413

/* Subword methods require the same approach for both TILEPro and

7414

TILE-Gx. We load the background data for the word, insert the

7415

desired subword piece, then compare-and-exchange it into place. */

7416

#define u8 unsigned char

7417

#define u16 unsigned short

7418

+

7419

+#define __subword_cmpxchg_body(type, size, ptr, guess, val) \

7420

+ ({ \

7421

+ unsigned int *p = (unsigned int *)((unsigned long)ptr & ~3UL); \

7422

+ const int shift = BIT_OFFSET((unsigned long)ptr & 3UL, type); \

7423

+ const unsigned int valmask = (1 << (sizeof(type) * 8)) - 1; \

7424

+ const unsigned int bgmask = ~(valmask << shift); \

7425

+ unsigned int oldword = *p; \

7426

+ type oldval = (oldword >> shift) & valmask; \

7427

+ if (__builtin_expect((oldval == guess), 1)) { \

7428

+ unsigned int word = (oldword & bgmask) | ((val & valmask) << shift); \

7429

+ oldword = arch_atomic_val_compare_and_exchange(p, oldword, word); \

7430

+ oldval = (oldword >> shift) & valmask; \

7431

+ } \

7432

+ oldval; \

7433

+ }) \

7434

+

7435

#define __atomic_subword_cmpxchg(type, size) \

7436

\

7437

bool \

7438

-__atomic_compare_exchange_##size(volatile type* ptr, type* guess, \

7439

+__atomic_compare_exchange_##size(volatile type* ptr, type* guess_ptr, \

7440

type val, bool weak __unused, int models, \

7441

int modelf __unused) \

7442

{ \

7443

pre_atomic_barrier(models); \

7444

- unsigned int *p = (unsigned int *)((unsigned long)ptr & ~3UL); \

7445

- const int shift = ((unsigned long)ptr & 3UL) * 8; \

7446

- const unsigned int valmask = (1 << (sizeof(type) * 8)) - 1; \

7447

- const unsigned int bgmask = ~(valmask << shift); \

7448

- unsigned int oldword = *p; \

7449

- type oldval = (oldword >> shift) & valmask; \

7450

- if (__builtin_expect((oldval == *guess), 1)) { \

7451

- unsigned int word = (oldword & bgmask) | ((val & valmask) << shift); \

7452

- oldword = arch_atomic_val_compare_and_exchange(p, oldword, word); \

7453

- oldval = (oldword >> shift) & valmask; \

7454

- } \

7455

+ type guess = *guess_ptr; \

7456

+ type oldval = __subword_cmpxchg_body(type, size, ptr, guess, val); \

7457

post_atomic_barrier(models); \

7458

- bool success = (oldval == *guess); \

7459

- *guess = oldval; \

7460

+ bool success = (oldval == guess); \

7461

+ *guess_ptr = oldval; \

7462

return success; \

7463

}

7464

+

7465

__atomic_subword_cmpxchg (u8, 1)

7466

__atomic_subword_cmpxchg (u16, 2)

7467

+

7468

+#define __sync_subword_cmpxchg(type, size) \

7469

+ \

7470

+type \

7471

+__sync_val_compare_and_swap_##size(type* ptr, type guess, type val) \

7472

+{ \

7473

+ arch_atomic_write_barrier(); \

7474

+ type oldval = __subword_cmpxchg_body(type, size, ptr, guess, val); \

7475

+ arch_atomic_read_barrier(); \

7476

+ return oldval; \

7477

+} \

7478

+ \

7479

+bool \

7480

+__sync_bool_compare_and_swap_##size(type* ptr, type guess, type val) \

7481

+{ \

7482

+ type oldval = __sync_val_compare_and_swap_##size(ptr, guess, val); \

7483

+ return oldval == guess; \

7484

+}

7485

+

7486

+__sync_subword_cmpxchg (u8, 1)

7487

+__sync_subword_cmpxchg (u16, 2)

7488

+

7489

/* For the atomic-update subword methods, we use the same approach as

7490

above, but we retry until we succeed if the compare-and-exchange

7491

fails. */

7492

-#define __atomic_subword(type, proto, top, expr, bottom) \

7493

+#define __subword(type, proto, top, expr, bottom) \

7494

proto \

7495

{ \

7496

top \

7497

unsigned int *p = (unsigned int *)((unsigned long)ptr & ~3UL); \

7498

- const int shift = ((unsigned long)ptr & 3UL) * 8; \

7499

+ const int shift = BIT_OFFSET((unsigned long)ptr & 3UL, type); \

7500

const unsigned int valmask = (1 << (sizeof(type) * 8)) - 1; \

7501

const unsigned int bgmask = ~(valmask << shift); \

7502

unsigned int oldword, xword = *p; \

7503

@@ -184,12 +303,14 @@

7504

} while (__builtin_expect(xword != oldword, 0)); \

7505

bottom \

7506

}

7507

+

7508

#define __atomic_subword_fetch(type, funcname, expr, retval) \

7509

- __atomic_subword(type, \

7510

- type __atomic_ ## funcname(volatile type *ptr, type i, int model), \

7511

- pre_atomic_barrier(model);, \

7512

- expr, \

7513

- post_atomic_barrier(model); return retval;)

7514

+ __subword(type, \

7515

+ type __atomic_ ## funcname(volatile type *ptr, type i, int model), \

7516

+ pre_atomic_barrier(model);, \

7517

+ expr, \

7518

+ post_atomic_barrier(model); return retval;)

7519

+

7520

__atomic_subword_fetch (u8, fetch_add_1, oldval + i, oldval)

7521

__atomic_subword_fetch (u8, fetch_sub_1, oldval - i, oldval)

7522

__atomic_subword_fetch (u8, fetch_or_1, oldval | i, oldval)

7523

@@ -196,6 +317,7 @@

7524

__atomic_subword_fetch (u8, fetch_and_1, oldval & i, oldval)

7525

__atomic_subword_fetch (u8, fetch_xor_1, oldval ^ i, oldval)

7526

__atomic_subword_fetch (u8, fetch_nand_1, ~(oldval & i), oldval)

7527

+

7528

__atomic_subword_fetch (u16, fetch_add_2, oldval + i, oldval)

7529

__atomic_subword_fetch (u16, fetch_sub_2, oldval - i, oldval)

7530

__atomic_subword_fetch (u16, fetch_or_2, oldval | i, oldval)

7531

@@ -202,6 +324,7 @@

7532

__atomic_subword_fetch (u16, fetch_and_2, oldval & i, oldval)

7533

__atomic_subword_fetch (u16, fetch_xor_2, oldval ^ i, oldval)

7534

__atomic_subword_fetch (u16, fetch_nand_2, ~(oldval & i), oldval)

7535

+

7536

__atomic_subword_fetch (u8, add_fetch_1, oldval + i, val)

7537

__atomic_subword_fetch (u8, sub_fetch_1, oldval - i, val)

7538

__atomic_subword_fetch (u8, or_fetch_1, oldval | i, val)

7539

@@ -208,6 +331,7 @@

7540

__atomic_subword_fetch (u8, and_fetch_1, oldval & i, val)

7541

__atomic_subword_fetch (u8, xor_fetch_1, oldval ^ i, val)

7542

__atomic_subword_fetch (u8, nand_fetch_1, ~(oldval & i), val)

7543

+

7544

__atomic_subword_fetch (u16, add_fetch_2, oldval + i, val)

7545

__atomic_subword_fetch (u16, sub_fetch_2, oldval - i, val)

7546

__atomic_subword_fetch (u16, or_fetch_2, oldval | i, val)

7547

@@ -214,12 +338,58 @@

7548

__atomic_subword_fetch (u16, and_fetch_2, oldval & i, val)

7549

__atomic_subword_fetch (u16, xor_fetch_2, oldval ^ i, val)

7550

__atomic_subword_fetch (u16, nand_fetch_2, ~(oldval & i), val)

7551

+

7552

+#define __sync_subword_fetch(type, funcname, expr, retval) \

7553

+ __subword(type, \

7554

+ type __sync_ ## funcname(type *ptr, type i), \

7555

+ arch_atomic_read_barrier();, \

7556

+ expr, \

7557

+ arch_atomic_write_barrier(); return retval;)

7558

+

7559

+__sync_subword_fetch (u8, fetch_and_add_1, oldval + i, oldval)

7560

+__sync_subword_fetch (u8, fetch_and_sub_1, oldval - i, oldval)

7561

+__sync_subword_fetch (u8, fetch_and_or_1, oldval | i, oldval)

7562

+__sync_subword_fetch (u8, fetch_and_and_1, oldval & i, oldval)

7563

+__sync_subword_fetch (u8, fetch_and_xor_1, oldval ^ i, oldval)

7564

+__sync_subword_fetch (u8, fetch_and_nand_1, ~(oldval & i), oldval)

7565

+

7566

+__sync_subword_fetch (u16, fetch_and_add_2, oldval + i, oldval)

7567

+__sync_subword_fetch (u16, fetch_and_sub_2, oldval - i, oldval)

7568

+__sync_subword_fetch (u16, fetch_and_or_2, oldval | i, oldval)

7569

+__sync_subword_fetch (u16, fetch_and_and_2, oldval & i, oldval)

7570

+__sync_subword_fetch (u16, fetch_and_xor_2, oldval ^ i, oldval)

7571

+__sync_subword_fetch (u16, fetch_and_nand_2, ~(oldval & i), oldval)

7572

+

7573

+__sync_subword_fetch (u8, add_and_fetch_1, oldval + i, val)

7574

+__sync_subword_fetch (u8, sub_and_fetch_1, oldval - i, val)

7575

+__sync_subword_fetch (u8, or_and_fetch_1, oldval | i, val)

7576

+__sync_subword_fetch (u8, and_and_fetch_1, oldval & i, val)

7577

+__sync_subword_fetch (u8, xor_and_fetch_1, oldval ^ i, val)

7578

+__sync_subword_fetch (u8, nand_and_fetch_1, ~(oldval & i), val)

7579

+

7580

+__sync_subword_fetch (u16, add_and_fetch_2, oldval + i, val)

7581

+__sync_subword_fetch (u16, sub_and_fetch_2, oldval - i, val)

7582

+__sync_subword_fetch (u16, or_and_fetch_2, oldval | i, val)

7583

+__sync_subword_fetch (u16, and_and_fetch_2, oldval & i, val)

7584

+__sync_subword_fetch (u16, xor_and_fetch_2, oldval ^ i, val)

7585

+__sync_subword_fetch (u16, nand_and_fetch_2, ~(oldval & i), val)

7586

+

7587

#define __atomic_subword_lock(type, size) \

7588

- \

7589

-__atomic_subword(type, \

7590

- type __atomic_exchange_##size(volatile type* ptr, type nval, int model), \

7591

- pre_atomic_barrier(model);, \

7592

- nval, \

7593

- post_atomic_barrier(model); return oldval;)

7594

+ __subword(type, \

7595

+ type __atomic_exchange_##size(volatile type* ptr, type nval, int model), \

7596

+ pre_atomic_barrier(model);, \

7597

+ nval, \

7598

+ post_atomic_barrier(model); return oldval;)

7599

+

7600

__atomic_subword_lock (u8, 1)

7601

__atomic_subword_lock (u16, 2)

7602

+

7603

+#define __sync_subword_lock(type, size) \

7604

+ __subword(type, \

7605

+ type __sync_lock_test_and_set_##size(type* ptr, type nval), \

7606

+ , \

7607

+ nval, \

7608

+ arch_atomic_acquire_barrier_value(oldval); return oldval;)

7609

+

7610

+__sync_subword_lock (u8, 1)

7611

+__sync_subword_lock (u16, 2)

7612

Index: libgcc/config/arm/sfp-machine.h

7613

===================================================================

7614

--- a/src/libgcc/config/arm/sfp-machine.h (.../tags/gcc_4_8_2_release)

7615

+++ b/src/libgcc/config/arm/sfp-machine.h (.../branches/gcc-4_8-branch)

7616

@@ -19,10 +19,12 @@

7617

#define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_2_udiv(D,R,X,Y)

7618

#define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_4_udiv(Q,R,X,Y)

7619

7620

-#define _FP_NANFRAC_H ((_FP_QNANBIT_H << 1) - 1)

7621

-#define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1)

7622

-#define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1), -1

7623

-#define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1, -1, -1

7624

+/* According to RTABI, QNAN is only with the most significant bit of the

7625

+ significand set, and all other significand bits zero. */

7626

+#define _FP_NANFRAC_H 0

7627

+#define _FP_NANFRAC_S 0

7628

+#define _FP_NANFRAC_D 0, 0

7629

+#define _FP_NANFRAC_Q 0, 0, 0, 0

7630

#define _FP_NANSIGN_H 0

7631

#define _FP_NANSIGN_S 0

7632

#define _FP_NANSIGN_D 0

7633

Index: libgcc/unwind-seh.c

7634

===================================================================

7635

--- a/src/libgcc/unwind-seh.c (.../tags/gcc_4_8_2_release)

7636

+++ b/src/libgcc/unwind-seh.c (.../branches/gcc-4_8-branch)

7637

@@ -313,8 +313,9 @@

7638

ms_exc->ExceptionInformation[3] = gcc_context.reg[1];

7639

7640

/* Begin phase 2. Perform the unwinding. */

7641

- RtlUnwindEx (this_frame, gcc_context.ra, ms_exc, gcc_exc,

7642

- ms_orig_context, ms_disp->HistoryTable);

7643

+ RtlUnwindEx (this_frame, gcc_context.ra, ms_exc,

7644

+ (PVOID)gcc_context.reg[0], ms_orig_context,

7645

+ ms_disp->HistoryTable);

7646

}

7647

7648

/* In _Unwind_RaiseException we return _URC_FATAL_PHASE1_ERROR. */

7649

Index: config.guess

7650

===================================================================

7651

--- a/src/config.guess (.../tags/gcc_4_8_2_release)

7652

+++ b/src/config.guess (.../branches/gcc-4_8-branch)

7653

@@ -1,10 +1,8 @@

7654

#! /bin/sh

7655

# Attempt to guess a canonical system name.

7656

7657

-# 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,

7658

-# 2011, 2012, 2013 Free Software Foundation, Inc.

7659

7660

7661

-timestamp='2012-12-30'

7662

+timestamp='2013-06-10'

7663

7664

# This file is free software; you can redistribute it and/or modify it

7665

# under the terms of the GNU General Public License as published by

7666

@@ -52,9 +50,7 @@

7667

GNU config.guess ($timestamp)

7668

7669

Originally written by Per Bothner.

7670

7671

-2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011,

7672

-2012, 2013 Free Software Foundation, Inc.

7673

7674

7675

This is free software; see the source for copying conditions. There is NO

7676

warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE."

7677

@@ -136,6 +132,27 @@

7678

UNAME_SYSTEM=`(uname -s) 2>/dev/null` || UNAME_SYSTEM=unknown

7679

UNAME_VERSION=`(uname -v) 2>/dev/null` || UNAME_VERSION=unknown

7680

7681

+case "${UNAME_SYSTEM}" in

7682

+Linux|GNU|GNU/*)

7683

+ # If the system lacks a compiler, then just pick glibc.

7684

+ # We could probably try harder.

7685

+ LIBC=gnu

7686

+

7687

+ eval $set_cc_for_build

7688

+ cat <<-EOF > $dummy.c

7689

+ #include <features.h>

7690

+ #if defined(__UCLIBC__)

7691

+ LIBC=uclibc

7692

+ #elif defined(__dietlibc__)

7693

+ LIBC=dietlibc

7694

+ #else

7695

+ LIBC=gnu

7696

+ #endif

7697

+ EOF

7698

+ eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep '^LIBC'`

7699

+ ;;

7700

+esac

7701

+

7702

# Note: order is significant - the case branches are not exclusive.

7703

7704

case "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" in

7705

@@ -857,21 +874,21 @@

7706

exit ;;

7707

*:GNU:*:*)

7708

# the GNU system

7709

- echo `echo ${UNAME_MACHINE}|sed -e 's,[-/].*$,,'`-unknown-gnu`echo ${UNAME_RELEASE}|sed -e 's,/.*$,,'`

7710

+ echo `echo ${UNAME_MACHINE}|sed -e 's,[-/].*$,,'`-unknown-${LIBC}`echo ${UNAME_RELEASE}|sed -e 's,/.*$,,'`

7711

exit ;;

7712

*:GNU/*:*:*)

7713

# other systems with GNU libc and userland

7714

- echo ${UNAME_MACHINE}-unknown-`echo ${UNAME_SYSTEM} | sed 's,^[^/]*/,,' | tr '[A-Z]' '[a-z]'``echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'`-gnu

7715

+ echo ${UNAME_MACHINE}-unknown-`echo ${UNAME_SYSTEM} | sed 's,^[^/]*/,,' | tr '[A-Z]' '[a-z]'``echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'`-${LIBC}

7716

exit ;;

7717

i*86:Minix:*:*)

7718

echo ${UNAME_MACHINE}-pc-minix

7719

exit ;;

7720

aarch64:Linux:*:*)

7721

- echo ${UNAME_MACHINE}-unknown-linux-gnu

7722

+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}

7723

exit ;;

7724

aarch64_be:Linux:*:*)

7725

UNAME_MACHINE=aarch64_be

7726

- echo ${UNAME_MACHINE}-unknown-linux-gnu

7727

+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}

7728

exit ;;

7729

alpha:Linux:*:*)

7730

case `sed -n '/^cpu model/s/^.*: $.*$/\1/p' < /proc/cpuinfo` in

7731

@@ -884,59 +901,54 @@

7732

EV68*) UNAME_MACHINE=alphaev68 ;;

7733

esac

7734

objdump --private-headers /bin/sh | grep -q ld.so.1

7735

- if test "$?" = 0 ; then LIBC="libc1" ; else LIBC="" ; fi

7736

- echo ${UNAME_MACHINE}-unknown-linux-gnu${LIBC}

7737

+ if test "$?" = 0 ; then LIBC="gnulibc1" ; fi

7738

+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}

7739

exit ;;

7740

+ arc:Linux:*:* | arceb:Linux:*:*)

7741

+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}

7742

+ exit ;;

7743

arm*:Linux:*:*)

7744

eval $set_cc_for_build

7745

if echo __ARM_EABI__ | $CC_FOR_BUILD -E - 2>/dev/null \

7746

| grep -q __ARM_EABI__

7747

then

7748

- echo ${UNAME_MACHINE}-unknown-linux-gnu

7749

+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}

7750

else

7751

if echo __ARM_PCS_VFP | $CC_FOR_BUILD -E - 2>/dev/null \

7752

| grep -q __ARM_PCS_VFP

7753

then

7754

- echo ${UNAME_MACHINE}-unknown-linux-gnueabi

7755

+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}eabi

7756

else

7757

- echo ${UNAME_MACHINE}-unknown-linux-gnueabihf

7758

+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}eabihf

7759

fi

7760

fi

7761

exit ;;

7762

avr32*:Linux:*:*)

7763

- echo ${UNAME_MACHINE}-unknown-linux-gnu

7764

+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}

7765

exit ;;

7766

cris:Linux:*:*)

7767

- echo ${UNAME_MACHINE}-axis-linux-gnu

7768

+ echo ${UNAME_MACHINE}-axis-linux-${LIBC}

7769

exit ;;

7770

crisv32:Linux:*:*)

7771

- echo ${UNAME_MACHINE}-axis-linux-gnu

7772

+ echo ${UNAME_MACHINE}-axis-linux-${LIBC}

7773

exit ;;

7774

frv:Linux:*:*)

7775

- echo ${UNAME_MACHINE}-unknown-linux-gnu

7776

+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}

7777

exit ;;

7778

hexagon:Linux:*:*)

7779

- echo ${UNAME_MACHINE}-unknown-linux-gnu

7780

+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}

7781

exit ;;

7782

i*86:Linux:*:*)

7783

- LIBC=gnu

7784

- eval $set_cc_for_build

7785

- sed 's/^ //' << EOF >$dummy.c

7786

- #ifdef __dietlibc__

7787

- LIBC=dietlibc

7788

- #endif

7789

-EOF

7790

- eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep '^LIBC'`

7791

- echo "${UNAME_MACHINE}-pc-linux-${LIBC}"

7792

+ echo ${UNAME_MACHINE}-pc-linux-${LIBC}

7793

exit ;;

7794

ia64:Linux:*:*)

7795

- echo ${UNAME_MACHINE}-unknown-linux-gnu

7796

+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}

7797

exit ;;

7798

m32r*:Linux:*:*)

7799

- echo ${UNAME_MACHINE}-unknown-linux-gnu

7800

+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}

7801

exit ;;

7802

m68*:Linux:*:*)

7803

- echo ${UNAME_MACHINE}-unknown-linux-gnu

7804

+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}

7805

exit ;;

7806

mips:Linux:*:* | mips64:Linux:*:*)

7807

eval $set_cc_for_build

7808

@@ -955,54 +967,63 @@

7809

#endif

7810

EOF

7811

eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep '^CPU'`

7812

- test x"${CPU}" != x && { echo "${CPU}-unknown-linux-gnu"; exit; }

7813

+ test x"${CPU}" != x && { echo "${CPU}-unknown-linux-${LIBC}"; exit; }

7814

;;

7815

+ or1k:Linux:*:*)

7816

+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}

7817

+ exit ;;

7818

or32:Linux:*:*)

7819

- echo ${UNAME_MACHINE}-unknown-linux-gnu

7820

+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}

7821

exit ;;

7822

padre:Linux:*:*)

7823

- echo sparc-unknown-linux-gnu

7824

+ echo sparc-unknown-linux-${LIBC}

7825

exit ;;

7826

parisc64:Linux:*:* | hppa64:Linux:*:*)

7827

- echo hppa64-unknown-linux-gnu

7828

+ echo hppa64-unknown-linux-${LIBC}

7829

exit ;;

7830

parisc:Linux:*:* | hppa:Linux:*:*)

7831

# Look for CPU level

7832

case `grep '^cpu[^a-z]*:' /proc/cpuinfo 2>/dev/null | cut -d' ' -f2` in

7833

- PA7*) echo hppa1.1-unknown-linux-gnu ;;

7834

- PA8*) echo hppa2.0-unknown-linux-gnu ;;

7835

- *) echo hppa-unknown-linux-gnu ;;

7836

+ PA7*) echo hppa1.1-unknown-linux-${LIBC} ;;

7837

+ PA8*) echo hppa2.0-unknown-linux-${LIBC} ;;

7838

+ *) echo hppa-unknown-linux-${LIBC} ;;

7839

esac

7840

exit ;;

7841

ppc64:Linux:*:*)

7842

- echo powerpc64-unknown-linux-gnu

7843

+ echo powerpc64-unknown-linux-${LIBC}

7844

exit ;;

7845

ppc:Linux:*:*)

7846

- echo powerpc-unknown-linux-gnu

7847

+ echo powerpc-unknown-linux-${LIBC}

7848

exit ;;

7849

+ ppc64le:Linux:*:*)

7850

+ echo powerpc64le-unknown-linux-${LIBC}

7851

+ exit ;;

7852

+ ppcle:Linux:*:*)

7853

+ echo powerpcle-unknown-linux-${LIBC}

7854

+ exit ;;

7855

s390:Linux:*:* | s390x:Linux:*:*)

7856

- echo ${UNAME_MACHINE}-ibm-linux

7857

+ echo ${UNAME_MACHINE}-ibm-linux-${LIBC}

7858

exit ;;

7859

sh64*:Linux:*:*)

7860

- echo ${UNAME_MACHINE}-unknown-linux-gnu

7861

+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}

7862

exit ;;

7863

sh*:Linux:*:*)

7864

- echo ${UNAME_MACHINE}-unknown-linux-gnu

7865

+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}

7866

exit ;;

7867

sparc:Linux:*:* | sparc64:Linux:*:*)

7868

- echo ${UNAME_MACHINE}-unknown-linux-gnu

7869

+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}

7870

exit ;;

7871

tile*:Linux:*:*)

7872

- echo ${UNAME_MACHINE}-unknown-linux-gnu

7873

+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}

7874

exit ;;

7875

vax:Linux:*:*)

7876

- echo ${UNAME_MACHINE}-dec-linux-gnu

7877

+ echo ${UNAME_MACHINE}-dec-linux-${LIBC}

7878

exit ;;

7879

x86_64:Linux:*:*)

7880

- echo ${UNAME_MACHINE}-unknown-linux-gnu

7881

+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}

7882

exit ;;

7883

xtensa*:Linux:*:*)

7884

- echo ${UNAME_MACHINE}-unknown-linux-gnu

7885

+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}

7886

exit ;;

7887

i*86:DYNIX/ptx:4*:*)

7888

# ptx 4.0 does uname -s correctly, with DYNIX/ptx in there.

7889

@@ -1235,19 +1256,21 @@

7890

exit ;;

7891

*:Darwin:*:*)

7892

UNAME_PROCESSOR=`uname -p` || UNAME_PROCESSOR=unknown

7893

- case $UNAME_PROCESSOR in

7894

- i386)

7895

- eval $set_cc_for_build

7896

- if [ "$CC_FOR_BUILD" != 'no_compiler_found' ]; then

7897

- if (echo '#ifdef __LP64__'; echo IS_64BIT_ARCH; echo '#endif') | \

7898

- (CCOPTS= $CC_FOR_BUILD -E - 2>/dev/null) | \

7899

- grep IS_64BIT_ARCH >/dev/null

7900

- then

7901

- UNAME_PROCESSOR="x86_64"

7902

- fi

7903

- fi ;;

7904

- unknown) UNAME_PROCESSOR=powerpc ;;

7905

- esac

7906

+ eval $set_cc_for_build

7907

+ if test "$UNAME_PROCESSOR" = unknown ; then

7908

+ UNAME_PROCESSOR=powerpc

7909

+ fi

7910

+ if [ "$CC_FOR_BUILD" != 'no_compiler_found' ]; then

7911

+ if (echo '#ifdef __LP64__'; echo IS_64BIT_ARCH; echo '#endif') | \

7912

+ (CCOPTS= $CC_FOR_BUILD -E - 2>/dev/null) | \

7913

+ grep IS_64BIT_ARCH >/dev/null

7914

+ then

7915

+ case $UNAME_PROCESSOR in

7916

+ i386) UNAME_PROCESSOR=x86_64 ;;

7917

+ powerpc) UNAME_PROCESSOR=powerpc64 ;;

7918

+ esac

7919

+ fi

7920

+ fi

7921

echo ${UNAME_PROCESSOR}-apple-darwin${UNAME_RELEASE}

7922

exit ;;

7923

*:procnto*:*:* | *:QNX:[0123456789]*:*)

7924

Index: gcc/tree-vrp.c

7925

===================================================================

7926

--- a/src/gcc/tree-vrp.c (.../tags/gcc_4_8_2_release)

7927

+++ b/src/gcc/tree-vrp.c (.../branches/gcc-4_8-branch)

7928

@@ -5271,9 +5271,13 @@

7929

}

7930

else if (CONVERT_EXPR_CODE_P (gimple_assign_rhs_code (op_def)))

7931

{

7932

- /* Recurse through the type conversion. */

7933

- retval |= register_edge_assert_for_1 (gimple_assign_rhs1 (op_def),

7934

- code, e, bsi);

7935

+ /* Recurse through the type conversion, unless it is a narrowing

7936

+ conversion or conversion from non-integral type. */

7937

+ tree rhs = gimple_assign_rhs1 (op_def);

7938

+ if (INTEGRAL_TYPE_P (TREE_TYPE (rhs))

7939

+ && (TYPE_PRECISION (TREE_TYPE (rhs))

7940

+ <= TYPE_PRECISION (TREE_TYPE (op))))

7941

+ retval |= register_edge_assert_for_1 (rhs, code, e, bsi);

7942

}

7943

7944

return retval;

7945

@@ -7453,7 +7457,8 @@

7946

}

7947

else if ((operand_less_p (vr1min, *vr0max) == 1

7948

|| operand_equal_p (vr1min, *vr0max, 0))

7949

- && operand_less_p (*vr0min, vr1min) == 1)

7950

+ && operand_less_p (*vr0min, vr1min) == 1

7951

+ && operand_less_p (*vr0max, vr1max) == 1)

7952

{

7953

/* [ ( ] ) or [ ]( ) */

7954

if (*vr0type == VR_RANGE

7955

@@ -7487,7 +7492,8 @@

7956

}

7957

else if ((operand_less_p (*vr0min, vr1max) == 1

7958

|| operand_equal_p (*vr0min, vr1max, 0))

7959

- && operand_less_p (vr1min, *vr0min) == 1)

7960

+ && operand_less_p (vr1min, *vr0min) == 1

7961

+ && operand_less_p (vr1max, *vr0max) == 1)

7962

{

7963

/* ( [ ) ] or ( )[ ] */

7964

if (*vr0type == VR_RANGE

7965

Index: gcc/loop-unswitch.c

7966

===================================================================

7967

--- a/src/gcc/loop-unswitch.c (.../tags/gcc_4_8_2_release)

7968

+++ b/src/gcc/loop-unswitch.c (.../branches/gcc-4_8-branch)

7969

@@ -191,6 +191,7 @@

7970

if (!test)

7971

return NULL_RTX;

7972

7973

+ mode = VOIDmode;

7974

for (i = 0; i < 2; i++)

7975

{

7976

op[i] = XEXP (test, i);

7977

@@ -205,11 +206,15 @@

7978

return NULL_RTX;

7979

7980

op[i] = get_iv_value (&iv, const0_rtx);

7981

+ if (iv.extend != IV_UNKNOWN_EXTEND

7982

+ && iv.mode != iv.extend_mode)

7983

+ op[i] = lowpart_subreg (iv.mode, op[i], iv.extend_mode);

7984

+ if (mode == VOIDmode)

7985

+ mode = iv.mode;

7986

+ else

7987

+ gcc_assert (mode == iv.mode);

7988

}

7989

7990

- mode = GET_MODE (op[0]);

7991

- if (mode == VOIDmode)

7992

- mode = GET_MODE (op[1]);

7993

if (GET_MODE_CLASS (mode) == MODE_CC)

7994

{

7995

if (at != BB_END (bb))

7996

Index: gcc/tree-ssa-loop-im.c

7997

===================================================================

7998

--- a/src/gcc/tree-ssa-loop-im.c (.../tags/gcc_4_8_2_release)

7999

+++ b/src/gcc/tree-ssa-loop-im.c (.../branches/gcc-4_8-branch)

8000

@@ -1190,6 +1190,67 @@

8001

fini_walk_dominator_tree (&walk_data);

8002

}

8003

8004

+/* Return true if CODE is an operation that when operating on signed

8005

+ integer types involves undefined behavior on overflow and the

8006

+ operation can be expressed with unsigned arithmetic. */

8007

+

8008

+static bool

8009

+arith_code_with_undefined_signed_overflow (tree_code code)

8010

+{

8011

+ switch (code)

8012

+ {

8013

+ case PLUS_EXPR:

8014

+ case MINUS_EXPR:

8015

+ case MULT_EXPR:

8016

+ case NEGATE_EXPR:

8017

+ case POINTER_PLUS_EXPR:

8018

+ return true;

8019

+ default:

8020

+ return false;

8021

+ }

8022

+}

8023

+

8024

+/* Rewrite STMT, an assignment with a signed integer or pointer arithmetic

8025

+ operation that can be transformed to unsigned arithmetic by converting

8026

+ its operand, carrying out the operation in the corresponding unsigned

8027

+ type and converting the result back to the original type.

8028

+

8029

+ Returns a sequence of statements that replace STMT and also contain

8030

+ a modified form of STMT itself. */

8031

+

8032

+static gimple_seq

8033

+rewrite_to_defined_overflow (gimple stmt)

8034

+{

8035

+ if (dump_file && (dump_flags & TDF_DETAILS))

8036

+ {

8037

+ fprintf (dump_file, "rewriting stmt with undefined signed "

8038

+ "overflow ");

8039

+ print_gimple_stmt (dump_file, stmt, 0, TDF_SLIM);

8040

+ }

8041

+

8042

+ tree lhs = gimple_assign_lhs (stmt);

8043

+ tree type = unsigned_type_for (TREE_TYPE (lhs));

8044

+ gimple_seq stmts = NULL;

8045

+ for (unsigned i = 1; i < gimple_num_ops (stmt); ++i)

8046

+ {

8047

+ gimple_seq stmts2 = NULL;

8048

+ gimple_set_op (stmt, i,

8049

+ force_gimple_operand (fold_convert (type,

8050

+ gimple_op (stmt, i)),

8051

+ &stmts2, true, NULL_TREE));

8052

+ gimple_seq_add_seq (&stmts, stmts2);

8053

+ }

8054

+ gimple_assign_set_lhs (stmt, make_ssa_name (type, stmt));

8055

+ if (gimple_assign_rhs_code (stmt) == POINTER_PLUS_EXPR)

8056

+ gimple_assign_set_rhs_code (stmt, PLUS_EXPR);

8057

+ gimple_seq_add_stmt (&stmts, stmt);

8058

+ gimple cvt = gimple_build_assign_with_ops

8059

+ (NOP_EXPR, lhs, gimple_assign_lhs (stmt), NULL_TREE);

8060

+ gimple_seq_add_stmt (&stmts, cvt);

8061

+

8062

+ return stmts;

8063

+}

8064

+

8065

/* Hoist the statements in basic block BB out of the loops prescribed by

8066

data stored in LIM_DATA structures associated with each statement. Callback

8067

for walk_dominator_tree. */

8068

@@ -1321,7 +1382,21 @@

8069

}

8070

}

8071

gsi_remove (&bsi, false);

8072

- gsi_insert_on_edge (e, stmt);

8073

+ /* In case this is a stmt that is not unconditionally executed

8074

+ when the target loop header is executed and the stmt may

8075

+ invoke undefined integer or pointer overflow rewrite it to

8076

+ unsigned arithmetic. */

8077

+ if (is_gimple_assign (stmt)

8078

+ && INTEGRAL_TYPE_P (TREE_TYPE (gimple_assign_lhs (stmt)))

8079

+ && TYPE_OVERFLOW_UNDEFINED (TREE_TYPE (gimple_assign_lhs (stmt)))

8080

+ && arith_code_with_undefined_signed_overflow

8081

+ (gimple_assign_rhs_code (stmt))

8082

+ && (!ALWAYS_EXECUTED_IN (bb)

8083

+ || !(ALWAYS_EXECUTED_IN (bb) == level

8084

+ || flow_loop_nested_p (ALWAYS_EXECUTED_IN (bb), level))))

8085

+ gsi_insert_seq_on_edge (e, rewrite_to_defined_overflow (stmt));

8086

+ else

8087

+ gsi_insert_on_edge (e, stmt);

8088

}

8089

}

8090

8091

@@ -1992,6 +2067,7 @@

8092

gimple_stmt_iterator gsi;

8093

gimple stmt;

8094

struct prev_flag_edges *prev_edges = (struct prev_flag_edges *) ex->aux;

8095

+ bool irr = ex->flags & EDGE_IRREDUCIBLE_LOOP;

8096

8097

/* ?? Insert store after previous store if applicable. See note

8098

below. */

8099

@@ -2006,8 +2082,9 @@

8100

old_dest = ex->dest;

8101

new_bb = split_edge (ex);

8102

then_bb = create_empty_bb (new_bb);

8103

- if (current_loops && new_bb->loop_father)

8104

- add_bb_to_loop (then_bb, new_bb->loop_father);

8105

+ if (irr)

8106

+ then_bb->flags = BB_IRREDUCIBLE_LOOP;

8107

+ add_bb_to_loop (then_bb, new_bb->loop_father);

8108

8109

gsi = gsi_start_bb (new_bb);

8110

stmt = gimple_build_cond (NE_EXPR, flag, boolean_false_node,

8111

@@ -2019,9 +2096,12 @@

8112

stmt = gimple_build_assign (unshare_expr (mem), tmp_var);

8113

gsi_insert_after (&gsi, stmt, GSI_CONTINUE_LINKING);

8114

8115

- make_edge (new_bb, then_bb, EDGE_TRUE_VALUE);

8116

- make_edge (new_bb, old_dest, EDGE_FALSE_VALUE);

8117

- then_old_edge = make_edge (then_bb, old_dest, EDGE_FALLTHRU);

8118

+ make_edge (new_bb, then_bb,

8119

+ EDGE_TRUE_VALUE | (irr ? EDGE_IRREDUCIBLE_LOOP : 0));

8120

+ make_edge (new_bb, old_dest,

8121

+ EDGE_FALSE_VALUE | (irr ? EDGE_IRREDUCIBLE_LOOP : 0));

8122

+ then_old_edge = make_edge (then_bb, old_dest,

8123

+ EDGE_FALLTHRU | (irr ? EDGE_IRREDUCIBLE_LOOP : 0));

8124

8125

set_immediate_dominator (CDI_DOMINATORS, then_bb, new_bb);

8126

8127

Index: gcc/tree-ssa-tail-merge.c

8128

===================================================================

8129

--- a/src/gcc/tree-ssa-tail-merge.c (.../tags/gcc_4_8_2_release)

8130

+++ b/src/gcc/tree-ssa-tail-merge.c (.../branches/gcc-4_8-branch)

8131

@@ -297,7 +297,8 @@

8132

tree val;

8133

def_operand_p def_p;

8134

8135

- if (gimple_has_side_effects (stmt))

8136

+ if (gimple_has_side_effects (stmt)

8137

+ || gimple_vdef (stmt) != NULL_TREE)

8138

return false;

8139

8140

def_p = SINGLE_SSA_DEF_OPERAND (stmt, SSA_OP_DEF);

8141

Index: gcc/cgraphbuild.c

8142

===================================================================

8143

--- a/src/gcc/cgraphbuild.c (.../tags/gcc_4_8_2_release)

8144

+++ b/src/gcc/cgraphbuild.c (.../branches/gcc-4_8-branch)

8145

@@ -73,7 +73,7 @@

8146

decl = get_base_var (*tp);

8147

if (TREE_CODE (decl) == FUNCTION_DECL)

8148

{

8149

- struct cgraph_node *node = cgraph_get_create_node (decl);

8150

+ struct cgraph_node *node = cgraph_get_create_real_symbol_node (decl);

8151

if (!ctx->only_vars)

8152

cgraph_mark_address_taken_node (node);

8153

ipa_record_reference ((symtab_node)ctx->varpool_node,

8154

@@ -143,7 +143,7 @@

8155

{

8156

struct cgraph_node *per_node;

8157

8158

- per_node = cgraph_get_create_node (DECL_FUNCTION_PERSONALITY (node->symbol.decl));

8159

+ per_node = cgraph_get_create_real_symbol_node (DECL_FUNCTION_PERSONALITY (node->symbol.decl));

8160

ipa_record_reference ((symtab_node)node, (symtab_node)per_node, IPA_REF_ADDR, NULL);

8161

cgraph_mark_address_taken_node (per_node);

8162

}

8163

@@ -218,12 +218,12 @@

8164

/* Mark address taken in STMT. */

8165

8166

static bool

8167

-mark_address (gimple stmt, tree addr, void *data)

8168

+mark_address (gimple stmt, tree addr, tree, void *data)

8169

{

8170

addr = get_base_address (addr);

8171

if (TREE_CODE (addr) == FUNCTION_DECL)

8172

{

8173

- struct cgraph_node *node = cgraph_get_create_node (addr);

8174

+ struct cgraph_node *node = cgraph_get_create_real_symbol_node (addr);

8175

cgraph_mark_address_taken_node (node);

8176

ipa_record_reference ((symtab_node)data,

8177

(symtab_node)node,

8178

@@ -245,7 +245,7 @@

8179

/* Mark load of T. */

8180

8181

static bool

8182

-mark_load (gimple stmt, tree t, void *data)

8183

+mark_load (gimple stmt, tree t, tree, void *data)

8184

{

8185

t = get_base_address (t);

8186

if (t && TREE_CODE (t) == FUNCTION_DECL)

8187

@@ -252,7 +252,7 @@

8188

{

8189

/* ??? This can happen on platforms with descriptors when these are

8190

directly manipulated in the code. Pretend that it's an address. */

8191

- struct cgraph_node *node = cgraph_get_create_node (t);

8192

+ struct cgraph_node *node = cgraph_get_create_real_symbol_node (t);

8193

cgraph_mark_address_taken_node (node);

8194

ipa_record_reference ((symtab_node)data,

8195

(symtab_node)node,

8196

@@ -273,7 +273,7 @@

8197

/* Mark store of T. */

8198

8199

static bool

8200

-mark_store (gimple stmt, tree t, void *data)

8201

+mark_store (gimple stmt, tree t, tree, void *data)

8202

{

8203

t = get_base_address (t);

8204

if (t && TREE_CODE (t) == VAR_DECL

8205

@@ -330,7 +330,7 @@

8206

{

8207

tree fn = gimple_omp_parallel_child_fn (stmt);

8208

ipa_record_reference ((symtab_node)node,

8209

- (symtab_node)cgraph_get_create_node (fn),

8210

+ (symtab_node)cgraph_get_create_real_symbol_node (fn),

8211

IPA_REF_ADDR, stmt);

8212

}

8213

if (gimple_code (stmt) == GIMPLE_OMP_TASK)

8214

@@ -338,12 +338,12 @@

8215

tree fn = gimple_omp_task_child_fn (stmt);

8216

if (fn)

8217

ipa_record_reference ((symtab_node)node,

8218

- (symtab_node) cgraph_get_create_node (fn),

8219

+ (symtab_node) cgraph_get_create_real_symbol_node (fn),

8220

IPA_REF_ADDR, stmt);

8221

fn = gimple_omp_task_copy_fn (stmt);

8222

if (fn)

8223

ipa_record_reference ((symtab_node)node,

8224

- (symtab_node)cgraph_get_create_node (fn),

8225

+ (symtab_node)cgraph_get_create_real_symbol_node (fn),

8226

IPA_REF_ADDR, stmt);

8227

}

8228

}

8229

Index: gcc/tree-ssa-uninit.c

8230

===================================================================

8231

--- a/src/gcc/tree-ssa-uninit.c (.../tags/gcc_4_8_2_release)

8232

+++ b/src/gcc/tree-ssa-uninit.c (.../branches/gcc-4_8-branch)

8233

@@ -36,6 +36,7 @@

8234

#include "hashtab.h"

8235

#include "tree-pass.h"

8236

#include "diagnostic-core.h"

8237

+#include "params.h"

8238

8239

/* This implements the pass that does predicate aware warning on uses of

8240

possibly uninitialized variables. The pass first collects the set of

8241

@@ -246,8 +247,8 @@

8242

8243

/* Computes the control dependence chains (paths of edges)

8244

for DEP_BB up to the dominating basic block BB (the head node of a

8245

- chain should be dominated by it). CD_CHAINS is pointer to a

8246

- dynamic array holding the result chains. CUR_CD_CHAIN is the current

8247

+ chain should be dominated by it). CD_CHAINS is pointer to an

8248

+ array holding the result chains. CUR_CD_CHAIN is the current

8249

chain being computed. *NUM_CHAINS is total number of chains. The

8250

function returns true if the information is successfully computed,

8251

return false if there is no control dependence or not computed. */

8252

@@ -256,7 +257,8 @@

8253

compute_control_dep_chain (basic_block bb, basic_block dep_bb,

8254

vec<edge> *cd_chains,

8255

size_t *num_chains,

8256

- vec<edge> *cur_cd_chain)

8257

+ vec<edge> *cur_cd_chain,

8258

+ int *num_calls)

8259

{

8260

edge_iterator ei;

8261

edge e;

8262

@@ -267,6 +269,10 @@

8263

if (EDGE_COUNT (bb->succs) < 2)

8264

return false;

8265

8266

+ if (*num_calls > PARAM_VALUE (PARAM_UNINIT_CONTROL_DEP_ATTEMPTS))

8267

+ return false;

8268

+ ++*num_calls;

8269

+

8270

/* Could use a set instead. */

8271

cur_chain_len = cur_cd_chain->length ();

8272

if (cur_chain_len > MAX_CHAIN_LEN)

8273

@@ -306,7 +312,7 @@

8274

8275

/* Now check if DEP_BB is indirectly control dependent on BB. */

8276

if (compute_control_dep_chain (cd_bb, dep_bb, cd_chains,

8277

- num_chains, cur_cd_chain))

8278

+ num_chains, cur_cd_chain, num_calls))

8279

{

8280

found_cd_chain = true;

8281

break;

8282

@@ -438,14 +444,12 @@

8283

basic_block use_bb)

8284

{

8285

size_t num_chains = 0, i;

8286

- vec<edge> *dep_chains = 0;

8287

+ int num_calls = 0;

8288

+ vec<edge> dep_chains[MAX_NUM_CHAINS];

8289

vec<edge> cur_chain = vNULL;

8290

bool has_valid_pred = false;

8291

basic_block cd_root = 0;

8292

8293

- typedef vec<edge> vec_edge_heap;

8294

- dep_chains = XCNEWVEC (vec_edge_heap, MAX_NUM_CHAINS);

8295

-

8296

/* First find the closest bb that is control equivalent to PHI_BB

8297

that also dominates USE_BB. */

8298

cd_root = phi_bb;

8299

@@ -458,20 +462,16 @@

8300

break;

8301

}

8302

8303

- compute_control_dep_chain (cd_root, use_bb,

8304

- dep_chains, &num_chains,

8305

- &cur_chain);

8306

+ compute_control_dep_chain (cd_root, use_bb, dep_chains, &num_chains,

8307

+ &cur_chain, &num_calls);

8308

8309

has_valid_pred

8310

- = convert_control_dep_chain_into_preds (dep_chains,

8311

- num_chains,

8312

- preds,

8313

- num_preds);

8314

+ = convert_control_dep_chain_into_preds (dep_chains, num_chains, preds,

8315

+ num_preds);

8316

/* Free individual chain */

8317

cur_chain.release ();

8318

for (i = 0; i < num_chains; i++)

8319

dep_chains[i].release ();

8320

- free (dep_chains);

8321

return has_valid_pred;

8322

}

8323

8324

@@ -539,7 +539,7 @@

8325

size_t *num_preds, gimple phi)

8326

{

8327

size_t num_chains = 0, i, n;

8328

- vec<edge> *dep_chains = 0;

8329

+ vec<edge> dep_chains[MAX_NUM_CHAINS];

8330

vec<edge> cur_chain = vNULL;

8331

vec<edge> def_edges = vNULL;

8332

bool has_valid_pred = false;

8333

@@ -546,9 +546,6 @@

8334

basic_block phi_bb, cd_root = 0;

8335

struct pointer_set_t *visited_phis;

8336

8337

- typedef vec<edge> vec_edge_heap;

8338

- dep_chains = XCNEWVEC (vec_edge_heap, MAX_NUM_CHAINS);

8339

-

8340

phi_bb = gimple_bb (phi);

8341

/* First find the closest dominating bb to be

8342

the control dependence root */

8343

@@ -567,38 +564,33 @@

8344

for (i = 0; i < n; i++)

8345

{

8346

size_t prev_nc, j;

8347

+ int num_calls = 0;

8348

edge opnd_edge;

8349

8350

opnd_edge = def_edges[i];

8351

prev_nc = num_chains;

8352

- compute_control_dep_chain (cd_root, opnd_edge->src,

8353

- dep_chains, &num_chains,

8354

- &cur_chain);

8355

- /* Free individual chain */

8356

- cur_chain.release ();

8357

+ compute_control_dep_chain (cd_root, opnd_edge->src, dep_chains,

8358

+ &num_chains, &cur_chain, &num_calls);

8359

8360

/* Now update the newly added chains with

8361

the phi operand edge: */

8362

if (EDGE_COUNT (opnd_edge->src->succs) > 1)

8363

{

8364

- if (prev_nc == num_chains

8365

- && num_chains < MAX_NUM_CHAINS)

8366

- num_chains++;

8367

+ if (prev_nc == num_chains && num_chains < MAX_NUM_CHAINS)

8368

+ dep_chains[num_chains++] = vNULL;

8369

for (j = prev_nc; j < num_chains; j++)

8370

- {

8371

- dep_chains[j].safe_push (opnd_edge);

8372

- }

8373

+ dep_chains[j].safe_push (opnd_edge);

8374

}

8375

}

8376

8377

+ /* Free individual chain */

8378

+ cur_chain.release ();

8379

+

8380

has_valid_pred

8381

- = convert_control_dep_chain_into_preds (dep_chains,

8382

- num_chains,

8383

- preds,

8384

- num_preds);

8385

+ = convert_control_dep_chain_into_preds (dep_chains, num_chains, preds,

8386

+ num_preds);

8387

for (i = 0; i < num_chains; i++)

8388

dep_chains[i].release ();

8389

- free (dep_chains);

8390

return has_valid_pred;

8391

}

8392

8393

Index: gcc/tree-ssa-loop-niter.c

8394

===================================================================

8395

--- a/src/gcc/tree-ssa-loop-niter.c (.../tags/gcc_4_8_2_release)

8396

+++ b/src/gcc/tree-ssa-loop-niter.c (.../branches/gcc-4_8-branch)

8397

@@ -2075,7 +2075,8 @@

8398

return NULL;

8399

}

8400

8401

- if (gimple_code (stmt) != GIMPLE_ASSIGN)

8402

+ if (gimple_code (stmt) != GIMPLE_ASSIGN

8403

+ || gimple_assign_rhs_class (stmt) == GIMPLE_TERNARY_RHS)

8404

return NULL;

8405

8406

code = gimple_assign_rhs_code (stmt);

8407

@@ -2143,7 +2144,7 @@

8408

{

8409

gimple stmt;

8410

8411

- gcc_assert (is_gimple_min_invariant (base));

8412

+ gcc_checking_assert (is_gimple_min_invariant (base));

8413

8414

if (!x)

8415

return base;

8416

@@ -2152,7 +2153,7 @@

8417

if (gimple_code (stmt) == GIMPLE_PHI)

8418

return base;

8419

8420

- gcc_assert (is_gimple_assign (stmt));

8421

+ gcc_checking_assert (is_gimple_assign (stmt));

8422

8423

/* STMT must be either an assignment of a single SSA name or an

8424

expression involving an SSA name and a constant. Try to fold that

8425

Index: gcc/c-family/c.opt

8426

===================================================================

8427

--- a/src/gcc/c-family/c.opt (.../tags/gcc_4_8_2_release)

8428

+++ b/src/gcc/c-family/c.opt (.../branches/gcc-4_8-branch)

8429

@@ -933,7 +933,7 @@

8430

Recognize GNU-defined keywords

8431

8432

fgnu-runtime

8433

-ObjC ObjC++ Report RejectNegative Var(flag_next_runtime,0) Init(NEXT_OBJC_RUNTIME)

8434

+ObjC ObjC++ LTO Report RejectNegative Var(flag_next_runtime,0) Init(NEXT_OBJC_RUNTIME)

8435

Generate code for GNU runtime environment

8436

8437

fgnu89-inline

8438

@@ -1007,7 +1007,7 @@

8439

C++ ObjC++ Ignore Warn(switch %qs is no longer supported)

8440

8441

fnext-runtime

8442

-ObjC ObjC++ Report RejectNegative Var(flag_next_runtime)

8443

+ObjC ObjC++ LTO Report RejectNegative Var(flag_next_runtime)

8444

Generate code for NeXT (Apple Mac OS X) runtime environment

8445

8446

fnil-receivers

8447

@@ -1025,7 +1025,7 @@

8448

Treat a throw() exception specification as noexcept to improve code size

8449

8450

fobjc-abi-version=

8451

-ObjC ObjC++ Joined Report RejectNegative UInteger Var(flag_objc_abi)

8452

+ObjC ObjC++ LTO Joined Report RejectNegative UInteger Var(flag_objc_abi)

8453

Specify which ABI to use for Objective-C family code and meta-data generation.

8454

8455

; Generate special '- .cxx_construct' and '- .cxx_destruct' methods

8456

@@ -1045,7 +1045,7 @@

8457

Enable Objective-C exception and synchronization syntax

8458

8459

fobjc-gc

8460

-ObjC ObjC++ Var(flag_objc_gc)

8461

+ObjC ObjC++ LTO Var(flag_objc_gc)

8462

Enable garbage collection (GC) in Objective-C/Objective-C++ programs

8463

8464

fobjc-nilcheck

8465

@@ -1105,7 +1105,7 @@

8466

-fno-pretty-templates Do not pretty-print template specializations as the template signature followed by the arguments

8467

8468

freplace-objc-classes

8469

-ObjC ObjC++ Var(flag_replace_objc_classes)

8470

+ObjC ObjC++ LTO Var(flag_replace_objc_classes)

8471

Used in Fix-and-Continue mode to indicate that object files may be swapped in at runtime

8472

8473

frepo

8474

Index: gcc/c-family/c-opts.c

8475

===================================================================

8476

--- a/src/gcc/c-family/c-opts.c (.../tags/gcc_4_8_2_release)

8477

+++ b/src/gcc/c-family/c-opts.c (.../branches/gcc-4_8-branch)

8478

@@ -840,6 +840,12 @@

8479

if (flag_objc_exceptions && !flag_objc_sjlj_exceptions)

8480

flag_exceptions = 1;

8481

8482

+ /* If -ffreestanding, -fno-hosted or -fno-builtin then disable

8483

+ pattern recognition. */

8484

+ if (!global_options_set.x_flag_tree_loop_distribute_patterns

8485

+ && flag_no_builtin)

8486

+ flag_tree_loop_distribute_patterns = 0;

8487

+

8488

/* -Woverlength-strings is off by default, but is enabled by -Wpedantic.

8489

It is never enabled in C++, as the minimum limit is not normative

8490

in that standard. */

8491

@@ -1258,17 +1264,18 @@

8492

{

8493

size_t i;

8494

8495

- {

8496

- /* Make sure all of the builtins about to be declared have

8497

- BUILTINS_LOCATION has their source_location. */

8498

- source_location builtins_loc = BUILTINS_LOCATION;

8499

- cpp_force_token_locations (parse_in, &builtins_loc);

8500

+ cb_file_change (parse_in,

8501

+ linemap_add (line_table, LC_RENAME, 0,

8502

+ _("<built-in>"), 0));

8503

+ /* Make sure all of the builtins about to be declared have

8504

+ BUILTINS_LOCATION has their source_location. */

8505

+ source_location builtins_loc = BUILTINS_LOCATION;

8506

+ cpp_force_token_locations (parse_in, &builtins_loc);

8507

8508

- cpp_init_builtins (parse_in, flag_hosted);

8509

- c_cpp_builtins (parse_in);

8510

+ cpp_init_builtins (parse_in, flag_hosted);

8511

+ c_cpp_builtins (parse_in);

8512

8513

- cpp_stop_forcing_token_locations (parse_in);

8514

- }

8515

+ cpp_stop_forcing_token_locations (parse_in);

8516

8517

/* We're about to send user input to cpplib, so make it warn for

8518

things that we previously (when we sent it internal definitions)

8519

Index: gcc/c-family/ChangeLog

8520

===================================================================

8521

--- a/src/gcc/c-family/ChangeLog (.../tags/gcc_4_8_2_release)

8522

+++ b/src/gcc/c-family/ChangeLog (.../branches/gcc-4_8-branch)

8523

@@ -1,3 +1,78 @@

8524

+2014-05-06 Richard Biener <rguenther@suse.de>

8525

+

8526

+ * c-opts.c (c_common_post_options): For -freestanding,

8527

+ -fno-hosted and -fno-builtin disable pattern recognition

8528

+ if not enabled explicitely.

8529

+

8530

+2014-04-10 Jakub Jelinek <jakub@redhat.com>

8531

+

8532

+ Backport from mainline

8533

+ 2014-03-28 Jakub Jelinek <jakub@redhat.com>

8534

+

8535

+ PR c++/60689

8536

+ * c-common.c (add_atomic_size_parameter): When creating new

8537

+ params vector, push the size argument first.

8538

+

8539

+ 2014-03-22 Jakub Jelinek <jakub@redhat.com>

8540

+

8541

+ PR debug/60603

8542

+ * c-opts.c (c_finish_options): Restore cb_file_change call to

8543

+ <built-in>.

8544

+

8545

+ 2014-03-13 Jakub Jelinek <jakub@redhat.com>

8546

+

8547

+ PR middle-end/36282

8548

+ * c-pragma.c (apply_pragma_weak): Only look at

8549

+ TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)) if

8550

+ DECL_ASSEMBLER_NAME_SET_P (decl).

8551

+ (maybe_apply_pending_pragma_weaks): Exit early if

8552

+ vec_safe_is_empty (pending_weaks) rather than only when

8553

+ !pending_weaks.

8554

+ (maybe_apply_pragma_weak): Likewise. If !DECL_ASSEMBLER_NAME_SET_P,

8555

+ set assembler name back to NULL afterwards.

8556

+

8557

+2014-04-07 Dominique d'Humieres <dominiq@lps.ens.fr>

8558

+

8559

+ Backport from mainline

8560

+ 2013-09-14 Iain Sandoe <iains@gcc.gnu.org>

8561

+

8562

+ PR target/48094

8563

+ * c.opt (fgnu-runtime, fnext-runtime, fobjc-abi-version,

8564

+ fobjc-gc, freplace-objc-classes): Accept for LTO.

8565

+

8566

+2014-03-06 Jakub Jelinek <jakub@redhat.com>

8567

+

8568

+ Backport from mainline

8569

+ 2014-02-19 Jakub Jelinek <jakub@redhat.com>

8570

+

8571

+ PR c/37743

8572

+ * c-common.c (c_common_nodes_and_builtins): When initializing

8573

+ c_uint{16,32,64}_type_node, also set corresponding

8574

+ uint{16,32,64}_type_node to the same value.

8575

+

8576

+ 2014-02-12 Jakub Jelinek <jakub@redhat.com>

8577

+

8578

+ PR c/60101

8579

+ * c-common.c (merge_tlist): If copy is true, call new_tlist,

8580

+ if false, add ADD itself, rather than vice versa.

8581

+ (verify_tree): For COND_EXPR, don't call merge_tlist with non-zero

8582

+ copy. For SAVE_EXPR, only call merge_tlist once.

8583

+

8584

+2013-11-29 Jakub Jelinek <jakub@redhat.com>

8585

+

8586

+ PR c/59280

8587

+ * c-common.c (get_priority): If TREE_VALUE (args) is IDENTIFIER_NODE,

8588

+ goto invalid. If it is error_mark_node, don't issue further

8589

+ diagnostics.

8590

+

8591

+2013-11-04 Marek Polacek <polacek@redhat.com>

8592

+

8593

+ Backport from mainline

8594

+ 2013-11-04 Marek Polacek <polacek@redhat.com>

8595

+

8596

+ PR c++/58979

8597

+ * c-common.c (invalid_indirection_error): Handle RO_ARROW_STAR case.

8598

+

8599

2013-10-16 Release Manager

8600

8601

* GCC 4.8.2 released.

8602

Index: gcc/c-family/c-common.c

8603

===================================================================

8604

--- a/src/gcc/c-family/c-common.c (.../tags/gcc_4_8_2_release)

8605

+++ b/src/gcc/c-family/c-common.c (.../branches/gcc-4_8-branch)

8606

@@ -2894,7 +2894,7 @@

8607

}

8608

if (!found)

8609

{

8610

- *end = copy ? add : new_tlist (NULL, add->expr, add->writer);

8611

+ *end = copy ? new_tlist (NULL, add->expr, add->writer) : add;

8612

end = &(*end)->next;

8613

*end = 0;

8614

}

8615

@@ -3052,7 +3052,7 @@

8616

verify_tree (TREE_OPERAND (x, 0), &tmp_before, &tmp_list2, NULL_TREE);

8617

warn_for_collisions (tmp_list2);

8618

merge_tlist (pbefore_sp, tmp_before, 0);

8619

- merge_tlist (pbefore_sp, tmp_list2, 1);

8620

+ merge_tlist (pbefore_sp, tmp_list2, 0);

8621

8622

tmp_list3 = tmp_nosp = 0;

8623

verify_tree (TREE_OPERAND (x, 1), &tmp_list3, &tmp_nosp, NULL_TREE);

8624

@@ -3156,12 +3156,7 @@

8625

warn_for_collisions (tmp_nosp);

8626

8627

tmp_list3 = 0;

8628

- while (tmp_nosp)

8629

- {

8630

- struct tlist *t = tmp_nosp;

8631

- tmp_nosp = t->next;

8632

- merge_tlist (&tmp_list3, t, 0);

8633

- }

8634

+ merge_tlist (&tmp_list3, tmp_nosp, 0);

8635

t->cache_before_sp = tmp_before;

8636

t->cache_after_sp = tmp_list3;

8637

}

8638

@@ -5511,13 +5506,13 @@

8639

uint8_type_node =

8640

TREE_TYPE (identifier_global_value (c_get_ident (UINT8_TYPE)));

8641

if (UINT16_TYPE)

8642

- c_uint16_type_node =

8643

+ c_uint16_type_node = uint16_type_node =

8644

TREE_TYPE (identifier_global_value (c_get_ident (UINT16_TYPE)));

8645

if (UINT32_TYPE)

8646

- c_uint32_type_node =

8647

+ c_uint32_type_node = uint32_type_node =

8648

TREE_TYPE (identifier_global_value (c_get_ident (UINT32_TYPE)));

8649

if (UINT64_TYPE)

8650

- c_uint64_type_node =

8651

+ c_uint64_type_node = uint64_type_node =

8652

TREE_TYPE (identifier_global_value (c_get_ident (UINT64_TYPE)));

8653

if (INT_LEAST8_TYPE)

8654

int_least8_type_node =

8655

@@ -6917,6 +6912,10 @@

8656

}

8657

8658

arg = TREE_VALUE (args);

8659

+ if (TREE_CODE (arg) == IDENTIFIER_NODE)

8660

+ goto invalid;

8661

+ if (arg == error_mark_node)

8662

+ return DEFAULT_INIT_PRIORITY;

8663

arg = default_conversion (arg);

8664

if (!host_integerp (arg, /*pos=*/0)

8665

|| !INTEGRAL_TYPE_P (TREE_TYPE (arg)))

8666

@@ -9763,6 +9762,11 @@

8667

"invalid type argument of %<->%> (have %qT)",

8668

type);

8669

break;

8670

+ case RO_ARROW_STAR:

8671

+ error_at (loc,

8672

+ "invalid type argument of %<->*%> (have %qT)",

8673

+ type);

8674

+ break;

8675

case RO_IMPLICIT_CONVERSION:

8676

error_at (loc,

8677

"invalid type argument of implicit conversion (have %qT)",

8678

@@ -10198,6 +10202,7 @@

8679

8680

len = params->length ();

8681

vec_alloc (v, len + 1);

8682

+ v->quick_push (build_int_cst (size_type_node, n));

8683

for (z = 0; z < len; z++)

8684

v->quick_push ((*params)[z]);

8685

f = build_function_call_vec (loc, function, v, NULL);

8686

Index: gcc/c-family/c-pragma.c

8687

===================================================================

8688

--- a/src/gcc/c-family/c-pragma.c (.../tags/gcc_4_8_2_release)

8689

+++ b/src/gcc/c-family/c-pragma.c (.../branches/gcc-4_8-branch)

8690

@@ -259,6 +259,7 @@

8691

8692

if (SUPPORTS_WEAK && DECL_EXTERNAL (decl) && TREE_USED (decl)

8693

&& !DECL_WEAK (decl) /* Don't complain about a redundant #pragma. */

8694

+ && DECL_ASSEMBLER_NAME_SET_P (decl)

8695

&& TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))

8696

warning (OPT_Wpragmas, "applying #pragma weak %q+D after first use "

8697

"results in unspecified behavior", decl);

8698

@@ -276,7 +277,7 @@

8699

/* Avoid asking for DECL_ASSEMBLER_NAME when it's not needed. */

8700

8701

/* No weak symbols pending, take the short-cut. */

8702

- if (!pending_weaks)

8703

+ if (vec_safe_is_empty (pending_weaks))

8704

return;

8705

/* If it's not visible outside this file, it doesn't matter whether

8706

it's weak. */

8707

@@ -288,7 +289,13 @@

8708

if (TREE_CODE (decl) != FUNCTION_DECL && TREE_CODE (decl) != VAR_DECL)

8709

return;

8710

8711

- id = DECL_ASSEMBLER_NAME (decl);

8712

+ if (DECL_ASSEMBLER_NAME_SET_P (decl))

8713

+ id = DECL_ASSEMBLER_NAME (decl);

8714

+ else

8715

+ {

8716

+ id = DECL_ASSEMBLER_NAME (decl);

8717

+ SET_DECL_ASSEMBLER_NAME (decl, NULL_TREE);

8718

+ }

8719

8720

FOR_EACH_VEC_ELT (*pending_weaks, i, pe)

8721

if (id == pe->name)

8722

@@ -309,7 +316,7 @@

8723

pending_weak *pe;

8724

symtab_node target;

8725

8726

- if (!pending_weaks)

8727

+ if (vec_safe_is_empty (pending_weaks))

8728

return;

8729

8730

FOR_EACH_VEC_ELT (*pending_weaks, i, pe)

8731

Index: gcc/c/c-typeck.c

8732

===================================================================

8733

--- a/src/gcc/c/c-typeck.c (.../tags/gcc_4_8_2_release)

8734

+++ b/src/gcc/c/c-typeck.c (.../branches/gcc-4_8-branch)

8735

@@ -2666,7 +2666,7 @@

8736

vec_alloc (v, list_length (params));

8737

for (; params; params = TREE_CHAIN (params))

8738

v->quick_push (TREE_VALUE (params));

8739

- ret = build_function_call_vec (loc, function, v, NULL);

8740

+ ret = c_build_function_call_vec (loc, function, v, NULL);

8741

vec_free (v);

8742

return ret;

8743

}

8744

@@ -2705,14 +2705,6 @@

8745

/* Convert anything with function type to a pointer-to-function. */

8746

if (TREE_CODE (function) == FUNCTION_DECL)

8747

{

8748

- /* Implement type-directed function overloading for builtins.

8749

- resolve_overloaded_builtin and targetm.resolve_overloaded_builtin

8750

- handle all the type checking. The result is a complete expression

8751

- that implements this function call. */

8752

- tem = resolve_overloaded_builtin (loc, function, params);

8753

- if (tem)

8754

- return tem;

8755

-

8756

name = DECL_NAME (function);

8757

8758

if (flag_tm)

8759

@@ -2863,6 +2855,30 @@

8760

}

8761

return require_complete_type (result);

8762

}

8763

+

8764

+/* Like build_function_call_vec, but call also resolve_overloaded_builtin. */

8765

+

8766

+tree

8767

+c_build_function_call_vec (location_t loc, tree function,

8768

+ vec<tree, va_gc> *params,

8769

+ vec<tree, va_gc> *origtypes)

8770

+{

8771

+ /* Strip NON_LVALUE_EXPRs, etc., since we aren't using as an lvalue. */

8772

+ STRIP_TYPE_NOPS (function);

8773

+

8774

+ /* Convert anything with function type to a pointer-to-function. */

8775

+ if (TREE_CODE (function) == FUNCTION_DECL)

8776

+ {

8777

+ /* Implement type-directed function overloading for builtins.

8778

+ resolve_overloaded_builtin and targetm.resolve_overloaded_builtin

8779

+ handle all the type checking. The result is a complete expression

8780

+ that implements this function call. */

8781

+ tree tem = resolve_overloaded_builtin (loc, function, params);

8782

+ if (tem)

8783

+ return tem;

8784

+ }

8785

+ return build_function_call_vec (loc, function, params, origtypes);

8786

+}

8787

8788

/* Convert the argument expressions in the vector VALUES

8789

to the types in the list TYPELIST.

8790

@@ -3629,7 +3645,8 @@

8791

/* Report invalid types. */

8792

8793

if (typecode != POINTER_TYPE && typecode != FIXED_POINT_TYPE

8794

- && typecode != INTEGER_TYPE && typecode != REAL_TYPE)

8795

+ && typecode != INTEGER_TYPE && typecode != REAL_TYPE

8796

+ && typecode != VECTOR_TYPE)

8797

{

8798

if (code == PREINCREMENT_EXPR || code == POSTINCREMENT_EXPR)

8799

error_at (location, "wrong type argument to increment");

8800

@@ -3694,7 +3711,9 @@

8801

}

8802

else

8803

{

8804

- inc = integer_one_node;

8805

+ inc = (TREE_CODE (argtype) == VECTOR_TYPE

8806

+ ? build_one_cst (argtype)

8807

+ : integer_one_node);

8808

inc = convert (argtype, inc);

8809

}

8810

8811

@@ -4331,8 +4350,10 @@

8812

{

8813

if (int_operands)

8814

{

8815

- op1 = remove_c_maybe_const_expr (op1);

8816

- op2 = remove_c_maybe_const_expr (op2);

8817

+ /* Use c_fully_fold here, since C_MAYBE_CONST_EXPR might be

8818

+ nested inside of the expression. */

8819

+ op1 = c_fully_fold (op1, false, NULL);

8820

+ op2 = c_fully_fold (op2, false, NULL);

8821

}

8822

ret = build3 (COND_EXPR, result_type, ifexp, op1, op2);

8823

if (int_operands)

8824

@@ -10618,7 +10639,8 @@

8825

"%qE has invalid type for %<reduction%>", t);

8826

remove = true;

8827

}

8828

- else if (FLOAT_TYPE_P (TREE_TYPE (t)))

8829

+ else if (FLOAT_TYPE_P (TREE_TYPE (t))

8830

+ || TREE_CODE (TREE_TYPE (t)) == COMPLEX_TYPE)

8831

{

8832

enum tree_code r_code = OMP_CLAUSE_REDUCTION_CODE (c);

8833

const char *r_name = NULL;

8834

@@ -10628,8 +10650,14 @@

8835

case PLUS_EXPR:

8836

case MULT_EXPR:

8837

case MINUS_EXPR:

8838

+ break;

8839

case MIN_EXPR:

8840

+ if (TREE_CODE (TREE_TYPE (t)) == COMPLEX_TYPE)

8841

+ r_name = "min";

8842

+ break;

8843

case MAX_EXPR:

8844

+ if (TREE_CODE (TREE_TYPE (t)) == COMPLEX_TYPE)

8845

+ r_name = "max";

8846

break;

8847

case BIT_AND_EXPR:

8848

r_name = "&";

8849

@@ -10641,10 +10669,12 @@

8850

r_name = "|";

8851

break;

8852

case TRUTH_ANDIF_EXPR:

8853

- r_name = "&&";

8854

+ if (FLOAT_TYPE_P (TREE_TYPE (t)))

8855

+ r_name = "&&";

8856

break;

8857

case TRUTH_ORIF_EXPR:

8858

- r_name = "||";

8859

+ if (FLOAT_TYPE_P (TREE_TYPE (t)))

8860

+ r_name = "||";

8861

break;

8862

default:

8863

gcc_unreachable ();

8864

Index: gcc/c/c-tree.h

8865

===================================================================

8866

--- a/src/gcc/c/c-tree.h (.../tags/gcc_4_8_2_release)

8867

+++ b/src/gcc/c/c-tree.h (.../branches/gcc-4_8-branch)

8868

@@ -640,6 +640,8 @@

8869

extern tree c_finish_omp_clauses (tree);

8870

extern tree c_build_va_arg (location_t, tree, tree);

8871

extern tree c_finish_transaction (location_t, tree, int);

8872

+extern tree c_build_function_call_vec (location_t, tree, vec<tree, va_gc> *,

8873

+ vec<tree, va_gc> *);

8874

8875

/* Set to 0 at beginning of a function definition, set to 1 if

8876

a return statement that specifies a return value is seen. */

8877

Index: gcc/c/ChangeLog

8878

===================================================================

8879

--- a/src/gcc/c/ChangeLog (.../tags/gcc_4_8_2_release)

8880

+++ b/src/gcc/c/ChangeLog (.../branches/gcc-4_8-branch)

8881

@@ -1,3 +1,49 @@

8882

+2014-04-10 Jakub Jelinek <jakub@redhat.com>

8883

+

8884

+ Backport from mainline

8885

+ 2014-03-28 Jakub Jelinek <jakub@redhat.com>

8886

+

8887

+ PR c++/60689

8888

+ * c-tree.h (c_build_function_call_vec): New prototype.

8889

+ * c-typeck.c (build_function_call_vec): Don't call

8890

+ resolve_overloaded_builtin here.

8891

+ (c_build_function_call_vec): New wrapper function around

8892

+ build_function_call_vec. Call resolve_overloaded_builtin here.

8893

+ (convert_lvalue_to_rvalue, build_function_call, build_atomic_assign):

8894

+ Call c_build_function_call_vec instead of build_function_call_vec.

8895

+ * c-parser.c (c_parser_postfix_expression_after_primary): Likewise.

8896

+ * c-decl.c (finish_decl): Likewise.

8897

+

8898

+2014-01-23 Jakub Jelinek <jakub@redhat.com>

8899

+

8900

+ PR middle-end/58809

8901

+ * c-typeck.c (c_finish_omp_clause): Reject MIN_EXPR, MAX_EXPR,

8902

+ BIT_AND_EXPR, BIT_IOR_EXPR and BIT_XOR_EXPR on COMPLEX_TYPEs.

8903

+

8904

+2014-01-22 Marek Polacek <polacek@redhat.com>

8905

+

8906

+ Backport from mainline

8907

+ 2014-01-22 Marek Polacek <polacek@redhat.com>

8908

+

8909

+ PR c/59891

8910

+ * c-typeck.c (build_conditional_expr): Call c_fully_fold instead

8911

+ of remove_c_maybe_const_expr on op1 and op2.

8912

+

8913

+2013-12-03 Marek Polacek <polacek@redhat.com>

8914

+

8915

+ Backport from mainline

8916

+ 2013-12-03 Marek Polacek <polacek@redhat.com>

8917

+

8918

+ PR c/59351

8919

+ * c-decl.c (build_compound_literal): Allow compound literals with

8920

+ empty initial value.

8921

+

8922

+2013-11-27 Tom de Vries <tom@codesourcery.com>

8923

+ Marc Glisse <marc.glisse@inria.fr>

8924

+

8925

+ PR c++/59032

8926

+ * c-typeck.c (build_unary_op): Allow vector increment and decrement.

8927

+

8928

2013-10-16 Release Manager

8929

8930

* GCC 4.8.2 released.

8931

Index: gcc/c/c-decl.c

8932

===================================================================

8933

--- a/src/gcc/c/c-decl.c (.../tags/gcc_4_8_2_release)

8934

+++ b/src/gcc/c/c-decl.c (.../branches/gcc-4_8-branch)

8935

@@ -4507,8 +4507,8 @@

8936

cleanup = build_unary_op (input_location, ADDR_EXPR, decl, 0);

8937

vec_alloc (v, 1);

8938

v->quick_push (cleanup);

8939

- cleanup = build_function_call_vec (DECL_SOURCE_LOCATION (decl),

8940

- cleanup_decl, v, NULL);

8941

+ cleanup = c_build_function_call_vec (DECL_SOURCE_LOCATION (decl),

8942

+ cleanup_decl, v, NULL);

8943

vec_free (v);

8944

8945

/* Don't warn about decl unused; the cleanup uses it. */

8946

@@ -4632,7 +4632,9 @@

8947

{

8948

int failure = complete_array_type (&TREE_TYPE (decl),

8949

DECL_INITIAL (decl), true);

8950

- gcc_assert (!failure);

8951

+ /* If complete_array_type returns 3, it means that the

8952

+ initial value of the compound literal is empty. Allow it. */

8953

+ gcc_assert (failure == 0 || failure == 3);

8954

8955

type = TREE_TYPE (decl);

8956

TREE_TYPE (DECL_INITIAL (decl)) = type;

8957

Index: gcc/c/c-parser.c

8958

===================================================================

8959

--- a/src/gcc/c/c-parser.c (.../tags/gcc_4_8_2_release)

8960

+++ b/src/gcc/c/c-parser.c (.../branches/gcc-4_8-branch)

8961

@@ -6904,8 +6904,8 @@

8962

sizeof_ptr_memacc_comptypes);

8963

/* FIXME diagnostics: Ideally we want the FUNCNAME, not the

8964

"(" after the FUNCNAME, which is what we have now. */

8965

- expr.value = build_function_call_vec (op_loc, expr.value, exprlist,

8966

- origtypes);

8967

+ expr.value = c_build_function_call_vec (op_loc, expr.value, exprlist,

8968

+ origtypes);

8969

expr.original_code = ERROR_MARK;

8970

if (TREE_CODE (expr.value) == INTEGER_CST

8971

&& TREE_CODE (orig_expr.value) == FUNCTION_DECL

8972

Index: gcc/cgraph.c

8973

===================================================================

8974

--- a/src/gcc/cgraph.c (.../tags/gcc_4_8_2_release)

8975

+++ b/src/gcc/cgraph.c (.../branches/gcc-4_8-branch)

8976

@@ -2596,4 +2596,47 @@

8977

FOR_EACH_FUNCTION (node)

8978

verify_cgraph_node (node);

8979

}

8980

+

8981

+/* Create external decl node for DECL.

8982

+ The difference i nbetween cgraph_get_create_node and

8983

+ cgraph_get_create_real_symbol_node is that cgraph_get_create_node

8984

+ may return inline clone, while cgraph_get_create_real_symbol_node

8985

+ will create a new node in this case.

8986

+ FIXME: This function should be removed once clones are put out of decl

8987

+ hash. */

8988

+

8989

+struct cgraph_node *

8990

+cgraph_get_create_real_symbol_node (tree decl)

8991

+{

8992

+ struct cgraph_node *first_clone = cgraph_get_node (decl);

8993

+ struct cgraph_node *node;

8994

+ /* create symbol table node. even if inline clone exists, we can not take

8995

+ it as a target of non-inlined call. */

8996

+ node = cgraph_get_node (decl);

8997

+ if (node && !node->global.inlined_to)

8998

+ return node;

8999

+

9000

+ node = cgraph_create_node (decl);

9001

+

9002

+ /* ok, we previously inlined the function, then removed the offline copy and

9003

+ now we want it back for external call. this can happen when devirtualizing

9004

+ while inlining function called once that happens after extern inlined and

9005

+ virtuals are already removed. in this case introduce the external node

9006

+ and make it available for call. */

9007

+ if (first_clone)

9008

+ {

9009

+ first_clone->clone_of = node;

9010

+ node->clones = first_clone;

9011

+ symtab_prevail_in_asm_name_hash ((symtab_node) node);

9012

+ symtab_insert_node_to_hashtable ((symtab_node) node);

9013

+ if (dump_file)

9014

+ fprintf (dump_file, "Introduced new external node "

9015

+ "(%s/%i) and turned into root of the clone tree.\n",

9016

+ xstrdup (cgraph_node_name (node)), node->uid);

9017

+ }

9018

+ else if (dump_file)

9019

+ fprintf (dump_file, "Introduced new external node "

9020

+ "(%s/%i).\n", xstrdup (cgraph_node_name (node)), node->uid);

9021

+ return node;

9022

+}

9023

#include "gt-cgraph.h"

9024

Index: gcc/cgraph.h

9025

===================================================================

9026

--- a/src/gcc/cgraph.h (.../tags/gcc_4_8_2_release)

9027

+++ b/src/gcc/cgraph.h (.../branches/gcc-4_8-branch)

9028

@@ -575,6 +575,7 @@

9029

struct cgraph_node * cgraph_create_node (tree);

9030

struct cgraph_node * cgraph_create_empty_node (void);

9031

struct cgraph_node * cgraph_get_create_node (tree);

9032

+struct cgraph_node * cgraph_get_create_real_symbol_node (tree);

9033

struct cgraph_node * cgraph_same_body_alias (struct cgraph_node *, tree, tree);

9034

struct cgraph_node * cgraph_add_thunk (struct cgraph_node *, tree, tree, bool, HOST_WIDE_INT,

9035

HOST_WIDE_INT, tree, tree);

9036

Index: gcc/optabs.c

9037

===================================================================

9038

--- a/src/gcc/optabs.c (.../tags/gcc_4_8_2_release)

9039

+++ b/src/gcc/optabs.c (.../branches/gcc-4_8-branch)

9040

@@ -3376,7 +3376,8 @@

9041

{

9042

rtx temp;

9043

9044

- if (! flag_trapv)

9045

+ if (GET_MODE_CLASS (mode) != MODE_INT

9046

+ || ! flag_trapv)

9047

result_unsignedp = 1;

9048

9049

/* First try to do it with a special abs instruction. */

9050

@@ -3399,7 +3400,8 @@

9051

{

9052

rtx last = get_last_insn ();

9053

9054

- temp = expand_unop (mode, neg_optab, op0, NULL_RTX, 0);

9055

+ temp = expand_unop (mode, result_unsignedp ? neg_optab : negv_optab,

9056

+ op0, NULL_RTX, 0);

9057

if (temp != 0)

9058

temp = expand_binop (mode, smax_optab, op0, temp, target, 0,

9059

OPTAB_WIDEN);

9060

@@ -3441,7 +3443,8 @@

9061

{

9062

rtx temp, op1;

9063

9064

- if (! flag_trapv)

9065

+ if (GET_MODE_CLASS (mode) != MODE_INT

9066

+ || ! flag_trapv)

9067

result_unsignedp = 1;

9068

9069

temp = expand_abs_nojump (mode, op0, target, result_unsignedp);

9070

@@ -4558,8 +4561,11 @@

9071

if (!COMPARISON_P (comparison))

9072

return NULL_RTX;

9073

9074

+ /* State variables we need to save and restore if cmove can't be used. */

9075

+ int save_pending_stack_adjust = pending_stack_adjust;

9076

+ int save_stack_pointer_delta = stack_pointer_delta;

9077

+ last = get_last_insn ();

9078

do_pending_stack_adjust ();

9079

- last = get_last_insn ();

9080

prepare_cmp_insn (XEXP (comparison, 0), XEXP (comparison, 1),

9081

GET_CODE (comparison), NULL_RTX, unsignedp, OPTAB_WIDEN,

9082

&comparison, &cmode);

9083

@@ -4579,6 +4585,8 @@

9084

}

9085

}

9086

delete_insns_since (last);

9087

+ pending_stack_adjust = save_pending_stack_adjust;

9088

+ stack_pointer_delta = save_stack_pointer_delta;

9089

return NULL_RTX;

9090

}

9091

9092

@@ -6233,7 +6241,7 @@

9093

9094

/* If the optabs changed, record it. */

9095

if (memcmp (tmp_optabs, this_target_optabs, sizeof (struct target_optabs)))

9096

- TREE_OPTIMIZATION_OPTABS (optnode) = (unsigned char *) tmp_optabs;

9097

+ TREE_OPTIMIZATION_OPTABS (optnode) = tmp_optabs;

9098

else

9099

{

9100

TREE_OPTIMIZATION_OPTABS (optnode) = NULL;

9101

@@ -7035,8 +7043,7 @@

9102

9103

create_output_operand (&ops[0], target, mode);

9104

create_fixed_operand (&ops[1], mem);

9105

- /* VAL may have been promoted to a wider mode. Shrink it if so. */

9106

- create_convert_operand_to (&ops[2], val, mode, true);

9107

+ create_input_operand (&ops[2], val, mode);

9108

create_integer_operand (&ops[3], model);

9109

if (maybe_expand_insn (icode, 4, ops))

9110

return ops[0].value;

9111

@@ -7075,8 +7082,7 @@

9112

struct expand_operand ops[3];

9113

create_output_operand (&ops[0], target, mode);

9114

create_fixed_operand (&ops[1], mem);

9115

- /* VAL may have been promoted to a wider mode. Shrink it if so. */

9116

- create_convert_operand_to (&ops[2], val, mode, true);

9117

+ create_input_operand (&ops[2], val, mode);

9118

if (maybe_expand_insn (icode, 3, ops))

9119

return ops[0].value;

9120

}

9121

@@ -7118,8 +7124,6 @@

9122

{

9123

if (!target || !register_operand (target, mode))

9124

target = gen_reg_rtx (mode);

9125

- if (GET_MODE (val) != VOIDmode && GET_MODE (val) != mode)

9126

- val = convert_modes (mode, GET_MODE (val), val, 1);

9127

if (expand_compare_and_swap_loop (mem, target, val, NULL_RTX))

9128

return target;

9129

}

9130

@@ -7331,8 +7335,8 @@

9131

create_output_operand (&ops[0], target_bool, bool_mode);

9132

create_output_operand (&ops[1], target_oval, mode);

9133

create_fixed_operand (&ops[2], mem);

9134

- create_convert_operand_to (&ops[3], expected, mode, true);

9135

- create_convert_operand_to (&ops[4], desired, mode, true);

9136

+ create_input_operand (&ops[3], expected, mode);

9137

+ create_input_operand (&ops[4], desired, mode);

9138

create_integer_operand (&ops[5], is_weak);

9139

create_integer_operand (&ops[6], succ_model);

9140

create_integer_operand (&ops[7], fail_model);

9141

@@ -7353,8 +7357,8 @@

9142

9143

create_output_operand (&ops[0], target_oval, mode);

9144

create_fixed_operand (&ops[1], mem);

9145

- create_convert_operand_to (&ops[2], expected, mode, true);

9146

- create_convert_operand_to (&ops[3], desired, mode, true);

9147

+ create_input_operand (&ops[2], expected, mode);

9148

+ create_input_operand (&ops[3], desired, mode);

9149

if (!maybe_expand_insn (icode, 4, ops))

9150

return false;

9151

9152

Index: gcc/DATESTAMP

9153

===================================================================

9154

--- a/src/gcc/DATESTAMP (.../tags/gcc_4_8_2_release)

9155

+++ b/src/gcc/DATESTAMP (.../branches/gcc-4_8-branch)

9156

@@ -1 +1 @@

9157

-20131016

9158

+20140508

9159

Index: gcc/value-prof.c

9160

===================================================================

9161

--- a/src/gcc/value-prof.c (.../tags/gcc_4_8_2_release)

9162

+++ b/src/gcc/value-prof.c (.../branches/gcc-4_8-branch)

9163

@@ -1270,8 +1270,7 @@

9164

9165

/* Build an EH edge for the direct call if necessary. */

9166

lp_nr = lookup_stmt_eh_lp (icall_stmt);

9167

- if (lp_nr != 0

9168

- && stmt_could_throw_p (dcall_stmt))

9169

+ if (lp_nr > 0 && stmt_could_throw_p (dcall_stmt))

9170

{

9171

edge e_eh, e;

9172

edge_iterator ei;

9173

Index: gcc/tree.c

9174

===================================================================

9175

--- a/src/gcc/tree.c (.../tags/gcc_4_8_2_release)

9176

+++ b/src/gcc/tree.c (.../branches/gcc-4_8-branch)

9177

@@ -1619,6 +1619,60 @@

9178

}

9179

}

9180

9181

+/* Return an integer of type TYPE containing all 1's in as much precision as

9182

+ it contains, or a complex or vector whose subparts are such integers. */

9183

+

9184

+tree

9185

+build_all_ones_cst (tree type)

9186

+{

9187

+ if (TREE_CODE (type) == COMPLEX_TYPE)

9188

+ {

9189

+ tree scalar = build_all_ones_cst (TREE_TYPE (type));

9190

+ return build_complex (type, scalar, scalar);

9191

+ }

9192

+ else

9193

+ return build_minus_one_cst (type);

9194

+}

9195

+

9196

+/* Return a constant of arithmetic type TYPE which is the

9197

+ opposite of the multiplicative identity of the set TYPE. */

9198

+

9199

+tree

9200

+build_minus_one_cst (tree type)

9201

+{

9202

+ switch (TREE_CODE (type))

9203

+ {

9204

+ case INTEGER_TYPE: case ENUMERAL_TYPE: case BOOLEAN_TYPE:

9205

+ case POINTER_TYPE: case REFERENCE_TYPE:

9206

+ case OFFSET_TYPE:

9207

+ return build_int_cst (type, -1);

9208

+

9209

+ case REAL_TYPE:

9210

+ return build_real (type, dconstm1);

9211

+

9212

+ case FIXED_POINT_TYPE:

9213

+ /* We can only generate 1 for accum types. */

9214

+ gcc_assert (ALL_SCALAR_ACCUM_MODE_P (TYPE_MODE (type)));

9215

+ return build_fixed (type, fixed_from_double_int (double_int_minus_one,

9216

+ TYPE_MODE (type)));

9217

+

9218

+ case VECTOR_TYPE:

9219

+ {

9220

+ tree scalar = build_minus_one_cst (TREE_TYPE (type));

9221

+

9222

+ return build_vector_from_val (type, scalar);

9223

+ }

9224

+

9225

+ case COMPLEX_TYPE:

9226

+ return build_complex (type,

9227

+ build_minus_one_cst (TREE_TYPE (type)),

9228

+ build_zero_cst (TREE_TYPE (type)));

9229

+

9230

+ default:

9231

+ gcc_unreachable ();

9232

+ }

9233

+}

9234

+

9235

/* Build 0 constant of type TYPE. This is used by constructor folding

9236

and thus the constant should be represented in memory by

9237

zero(es). */

9238

Index: gcc/tree.h

9239

===================================================================

9240

--- a/src/gcc/tree.h (.../tags/gcc_4_8_2_release)

9241

+++ b/src/gcc/tree.h (.../branches/gcc-4_8-branch)

9242

@@ -3589,7 +3589,7 @@

9243

9244

/* Target optabs for this set of optimization options. This is of

9245

type `struct target_optabs *'. */

9246

- unsigned char *GTY ((atomic)) optabs;

9247

+ void *GTY ((atomic)) optabs;

9248

9249

/* The value of this_target_optabs against which the optabs above were

9250

generated. */

9251

@@ -4760,6 +4760,8 @@

9252

extern tree build_real_from_int_cst (tree, const_tree);

9253

extern tree build_complex (tree, tree, tree);

9254

extern tree build_one_cst (tree);

9255

+extern tree build_minus_one_cst (tree);

9256

+extern tree build_all_ones_cst (tree);

9257

extern tree build_zero_cst (tree);

9258

extern tree build_string (int, const char *);

9259

extern tree build_tree_list_stat (tree, tree MEM_STAT_DECL);

9260

@@ -5854,6 +5856,7 @@

9261

extern tree fold_builtin_fputs (location_t, tree, tree, bool, bool, tree);

9262

extern tree fold_builtin_strcpy (location_t, tree, tree, tree, tree);

9263

extern tree fold_builtin_strncpy (location_t, tree, tree, tree, tree, tree);

9264

+extern tree fold_builtin_strcat (location_t, tree, tree, tree);

9265

extern tree fold_builtin_memory_chk (location_t, tree, tree, tree, tree, tree, tree, bool,

9266

enum built_in_function);

9267

extern tree fold_builtin_stxcpy_chk (location_t, tree, tree, tree, tree, tree, bool,

9268

@@ -6545,4 +6548,18 @@

9269

&& builtin_info.implicit_p[uns_fncode]);

9270

}

9271

9272

+/* Return pointer to optimization flags of FNDECL. */

9273

+static inline struct cl_optimization *

9274

+opts_for_fn (const_tree fndecl)

9275

+{

9276

+ tree fn_opts = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);

9277

+ if (fn_opts == NULL_TREE)

9278

+ fn_opts = optimization_default_node;

9279

+ return TREE_OPTIMIZATION (fn_opts);

9280

+}

9281

+

9282

+/* opt flag for function FNDECL, e.g. opts_for_fn (fndecl, optimize) is

9283

+ the optimization level of function fndecl. */

9284

+#define opt_for_fn(fndecl, opt) (opts_for_fn (fndecl)->x_##opt)

9285

+

9286

#endif /* GCC_TREE_H */

9287

Index: gcc/ipa-cp.c

9288

===================================================================

9289

--- a/src/gcc/ipa-cp.c (.../tags/gcc_4_8_2_release)

9290

+++ b/src/gcc/ipa-cp.c (.../branches/gcc-4_8-branch)

9291

@@ -444,6 +444,9 @@

9292

reason = "not a tree_versionable_function";

9293

else if (cgraph_function_body_availability (node) <= AVAIL_OVERWRITABLE)

9294

reason = "insufficient body availability";

9295

+ else if (!opt_for_fn (node->symbol.decl, optimize)

9296

+ || !opt_for_fn (node->symbol.decl, flag_ipa_cp))

9297

+ reason = "non-optimized function";

9298

9299

if (reason && dump_file && !node->alias && !node->thunk.thunk_p)

9300

fprintf (dump_file, "Function %s/%i is not versionable, reason: %s.\n",

9301

@@ -1455,22 +1458,21 @@

9302

args_count = ipa_get_cs_argument_count (args);

9303

parms_count = ipa_get_param_count (callee_info);

9304

9305

- /* If this call goes through a thunk we must not propagate to the first (0th)

9306

- parameter. However, we might need to uncover a thunk from below a series

9307

- of aliases first. */

9308

+ /* If this call goes through a thunk we should not propagate because we

9309

+ cannot redirect edges to thunks. However, we might need to uncover a

9310

+ thunk from below a series of aliases first. */

9311

alias_or_thunk = cs->callee;

9312

while (alias_or_thunk->alias)

9313

alias_or_thunk = cgraph_alias_aliased_node (alias_or_thunk);

9314

if (alias_or_thunk->thunk.thunk_p)

9315

{

9316

- ret |= set_all_contains_variable (ipa_get_parm_lattices (callee_info,

9317

- 0));

9318

- i = 1;

9319

+ for (i = 0; i < parms_count; i++)

9320

+ ret |= set_all_contains_variable (ipa_get_parm_lattices (callee_info,

9321

+ i));

9322

+ return ret;

9323

}

9324

- else

9325

- i = 0;

9326

9327

- for (; (i < args_count) && (i < parms_count); i++)

9328

+ for (i = 0; (i < args_count) && (i < parms_count); i++)

9329

{

9330

struct ipa_jump_func *jump_func = ipa_get_ith_jump_func (args, i);

9331

struct ipcp_param_lattices *dest_plats;

9332

@@ -3119,6 +3121,7 @@

9333

struct cgraph_node *node)

9334

{

9335

struct ipa_node_params *orig_caller_info = IPA_NODE_REF (cs->caller);

9336

+ struct ipa_node_params *orig_node_info;

9337

struct ipa_agg_replacement_value *aggval;

9338

int i, ec, count;

9339

9340

@@ -3133,6 +3136,7 @@

9341

if (aggval->index >= ec)

9342

return false;

9343

9344

+ orig_node_info = IPA_NODE_REF (IPA_NODE_REF (node)->ipcp_orig_node);

9345

if (orig_caller_info->ipcp_orig_node)

9346

orig_caller_info = IPA_NODE_REF (orig_caller_info->ipcp_orig_node);

9347

9348

@@ -3150,7 +3154,7 @@

9349

if (!interesting)

9350

continue;

9351

9352

- plats = ipa_get_parm_lattices (orig_caller_info, aggval->index);

9353

+ plats = ipa_get_parm_lattices (orig_node_info, aggval->index);

9354

if (plats->aggs_bottom)

9355

return false;

9356

9357

Index: gcc/rtlanal.c

9358

===================================================================

9359

--- a/src/gcc/rtlanal.c (.../tags/gcc_4_8_2_release)

9360

+++ b/src/gcc/rtlanal.c (.../branches/gcc-4_8-branch)

9361

@@ -224,10 +224,10 @@

9362

return 0;

9363

}

9364

9365

-/* Return nonzero if the use of X as an address in a MEM can cause a trap.

9366

- MODE is the mode of the MEM (not that of X) and UNALIGNED_MEMS controls

9367

- whether nonzero is returned for unaligned memory accesses on strict

9368

- alignment machines. */

9369

+/* Return nonzero if the use of X+OFFSET as an address in a MEM with SIZE

9370

+ bytes can cause a trap. MODE is the mode of the MEM (not that of X) and

9371

+ UNALIGNED_MEMS controls whether nonzero is returned for unaligned memory

9372

+ references on strict alignment machines. */

9373

9374

static int

9375

rtx_addr_can_trap_p_1 (const_rtx x, HOST_WIDE_INT offset, HOST_WIDE_INT size,

9376

@@ -235,11 +235,12 @@

9377

{

9378

enum rtx_code code = GET_CODE (x);

9379

9380

- if (STRICT_ALIGNMENT

9381

- && unaligned_mems

9382

- && GET_MODE_SIZE (mode) != 0)

9383

+ /* The offset must be a multiple of the mode size if we are considering

9384

+ unaligned memory references on strict alignment machines. */

9385

+ if (STRICT_ALIGNMENT && unaligned_mems && GET_MODE_SIZE (mode) != 0)

9386

{

9387

HOST_WIDE_INT actual_offset = offset;

9388

+

9389

#ifdef SPARC_STACK_BOUNDARY_HACK

9390

/* ??? The SPARC port may claim a STACK_BOUNDARY higher than

9391

the real alignment of %sp. However, when it does this, the

9392

@@ -298,8 +299,27 @@

9393

return 0;

9394

9395

case REG:

9396

- /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */

9397

- if (x == frame_pointer_rtx || x == hard_frame_pointer_rtx

9398

+ /* Stack references are assumed not to trap, but we need to deal with

9399

+ nonsensical offsets. */

9400

+ if (x == frame_pointer_rtx)

9401

+ {

9402

+ HOST_WIDE_INT adj_offset = offset - STARTING_FRAME_OFFSET;

9403

+ if (size == 0)

9404

+ size = GET_MODE_SIZE (mode);

9405

+ if (FRAME_GROWS_DOWNWARD)

9406

+ {

9407

+ if (adj_offset < frame_offset || adj_offset + size - 1 >= 0)

9408

+ return 1;

9409

+ }

9410

+ else

9411

+ {

9412

+ if (adj_offset < 0 || adj_offset + size - 1 >= frame_offset)

9413

+ return 1;

9414

+ }

9415

+ return 0;

9416

+ }

9417

+ /* ??? Need to add a similar guard for nonsensical offsets. */

9418

+ if (x == hard_frame_pointer_rtx

9419

|| x == stack_pointer_rtx

9420

/* The arg pointer varies if it is not a fixed register. */

9421

|| (x == arg_pointer_rtx && fixed_regs[ARG_POINTER_REGNUM]))

9422

@@ -320,9 +340,7 @@

9423

if (XEXP (x, 0) == pic_offset_table_rtx && CONSTANT_P (XEXP (x, 1)))

9424

return 0;

9425

9426

- /* - or it is an address that can't trap plus a constant integer,

9427

- with the proper remainder modulo the mode size if we are

9428

- considering unaligned memory references. */

9429

+ /* - or it is an address that can't trap plus a constant integer. */

9430

if (CONST_INT_P (XEXP (x, 1))

9431

&& !rtx_addr_can_trap_p_1 (XEXP (x, 0), offset + INTVAL (XEXP (x, 1)),

9432

size, mode, unaligned_mems))

9433

Index: gcc/configure

9434

===================================================================

9435

--- a/src/gcc/configure (.../tags/gcc_4_8_2_release)

9436

+++ b/src/gcc/configure (.../branches/gcc-4_8-branch)

9437

@@ -11202,13 +11202,16 @@

9438

/* | A-Za-z:\\/* ) realsrcdir=${srcdir};;

9439

*) realsrcdir=../${srcdir};;

9440

esac

9441

- saved_CFLAGS="${CFLAGS}"

9442

+ # Clearing GMPINC is necessary to prevent host headers being

9443

+ # used by the build compiler. Defining GENERATOR_FILE stops

9444

+ # system.h from including gmp.h.

9445

CC="${CC_FOR_BUILD}" CFLAGS="${CFLAGS_FOR_BUILD}" \

9446

- LDFLAGS="${LDFLAGS_FOR_BUILD}" \

9447

+ CXX="${CXX_FOR_BUILD}" CXXFLAGS="${CXXFLAGS_FOR_BUILD}" \

9448

+ LD="${LD_FOR_BUILD}" LDFLAGS="${LDFLAGS_FOR_BUILD}" \

9449

+ GMPINC="" CPPFLAGS="${CPPFLAGS} -DGENERATOR_FILE" \

9450

${realsrcdir}/configure \

9451

--enable-languages=${enable_languages-all} \

9452

--target=$target_alias --host=$build_alias --build=$build_alias

9453

- CFLAGS="${saved_CFLAGS}"

9454

9455

# We just finished tests for the build machine, so rename

9456

# the file auto-build.h in the gcc directory.

9457

@@ -11703,6 +11706,7 @@

9458

if test x$build != x$host || test "x$coverage_flags" != x

9459

then

9460

BUILD_CFLAGS='$(INTERNAL_CFLAGS) $(T_CFLAGS) $(CFLAGS_FOR_BUILD)'

9461

+ BUILD_CXXFLAGS='$(INTERNAL_CFLAGS) $(T_CFLAGS) $(CXXFLAGS_FOR_BUILD)'

9462

BUILD_LDFLAGS='$(LDFLAGS_FOR_BUILD)'

9463

fi

9464

9465

@@ -13590,7 +13594,7 @@

9466

rm -rf conftest*

9467

;;

9468

9469

-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \

9470

+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \

9471

s390*-*linux*|s390*-*tpf*|sparc*-*linux*)

9472

# Find out which ABI we are using.

9473

echo 'int i;' > conftest.$ac_ext

9474

@@ -13615,7 +13619,10 @@

9475

;;

9476

esac

9477

;;

9478

- ppc64-*linux*|powerpc64-*linux*)

9479

+ powerpc64le-*linux*)

9480

+ LD="${LD-ld} -m elf32lppclinux"

9481

+ ;;

9482

+ powerpc64-*linux*)

9483

LD="${LD-ld} -m elf32ppclinux"

9484

;;

9485

s390x-*linux*)

9486

@@ -13634,7 +13641,10 @@

9487

x86_64-*linux*)

9488

LD="${LD-ld} -m elf_x86_64"

9489

;;

9490

- ppc*-*linux*|powerpc*-*linux*)

9491

+ powerpcle-*linux*)

9492

+ LD="${LD-ld} -m elf64lppc"

9493

+ ;;

9494

+ powerpc-*linux*)

9495

LD="${LD-ld} -m elf64ppc"

9496

;;

9497

s390*-*linux*|s390*-*tpf*)

9498

@@ -17828,7 +17838,7 @@

9499

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

9500

lt_status=$lt_dlunknown

9501

cat > conftest.$ac_ext <<_LT_EOF

9502

-#line 17831 "configure"

9503

+#line 17841 "configure"

9504

#include "confdefs.h"

9505

9506

#if HAVE_DLFCN_H

9507

@@ -17934,7 +17944,7 @@

9508

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

9509

lt_status=$lt_dlunknown

9510

cat > conftest.$ac_ext <<_LT_EOF

9511

-#line 17937 "configure"

9512

+#line 17947 "configure"

9513

#include "confdefs.h"

9514

9515

#if HAVE_DLFCN_H

9516

@@ -24263,6 +24273,43 @@

9517

$as_echo "#define HAVE_AS_SPARC4 1" >>confdefs.h

9518

9519

fi

9520

+

9521

+ { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for LEON instructions" >&5

9522

+$as_echo_n "checking assembler for LEON instructions... " >&6; }

9523

+if test "${gcc_cv_as_sparc_leon+set}" = set; then :

9524

+ $as_echo_n "(cached) " >&6

9525

+else

9526

+ gcc_cv_as_sparc_leon=no

9527

+ if test x$gcc_cv_as != x; then

9528

+ $as_echo '.text

9529

+ .register %g2, #scratch

9530

+ .register %g3, #scratch

9531

+ .align 4

9532

+ smac %g2, %g3, %g1

9533

+ umac %g2, %g3, %g1

9534

+ casa [%g2] 0xb, %g3, %g1' > conftest.s

9535

+ if { ac_try='$gcc_cv_as $gcc_cv_as_flags -Aleon -o conftest.o conftest.s >&5'

9536

+ { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5

9537

+ (eval $ac_try) 2>&5

9538

+ ac_status=$?

9539

+ $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5

9540

+ test $ac_status = 0; }; }

9541

+ then

9542

+ gcc_cv_as_sparc_leon=yes

9543

+ else

9544

+ echo "configure: failed program was" >&5

9545

+ cat conftest.s >&5

9546

+ fi

9547

+ rm -f conftest.o conftest.s

9548

+ fi

9549

+fi

9550

+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_sparc_leon" >&5

9551

+$as_echo "$gcc_cv_as_sparc_leon" >&6; }

9552

+if test $gcc_cv_as_sparc_leon = yes; then

9553

+

9554

+$as_echo "#define HAVE_AS_LEON 1" >>confdefs.h

9555

+

9556

+fi

9557

;;

9558

9559

i[34567]86-*-* | x86_64-*-*)

9560

@@ -24745,6 +24792,10 @@

9561

9562

# These two are used unconditionally by i386.[ch]; it is to be defined

9563

# to 1 if the feature is present, 0 otherwise.

9564

+ as_ix86_gotoff_in_data_opt=

9565

+ if test x$gas = xyes; then

9566

+ as_ix86_gotoff_in_data_opt="--32"

9567

+ fi

9568

{ $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for GOTOFF in data" >&5

9569

$as_echo_n "checking assembler for GOTOFF in data... " >&6; }

9570

if test "${gcc_cv_as_ix86_gotoff_in_data+set}" = set; then :

9571

@@ -24761,7 +24812,7 @@

9572

nop

9573

.data

9574

.long .L0@GOTOFF' > conftest.s

9575

- if { ac_try='$gcc_cv_as $gcc_cv_as_flags -o conftest.o conftest.s >&5'

9576

+ if { ac_try='$gcc_cv_as $gcc_cv_as_flags $as_ix86_gotoff_in_data_opt -o conftest.o conftest.s >&5'

9577

{ { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5

9578

(eval $ac_try) 2>&5

9579

ac_status=$?

9580

@@ -24822,6 +24873,37 @@

9581

9582

fi

9583

9584

+ { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for ud2 mnemonic" >&5

9585

+$as_echo_n "checking assembler for ud2 mnemonic... " >&6; }

9586

+if test "${gcc_cv_as_ix86_ud2+set}" = set; then :

9587

+ $as_echo_n "(cached) " >&6

9588

+else

9589

+ gcc_cv_as_ix86_ud2=no

9590

+ if test x$gcc_cv_as != x; then

9591

+ $as_echo 'ud2' > conftest.s

9592

+ if { ac_try='$gcc_cv_as $gcc_cv_as_flags -o conftest.o conftest.s >&5'

9593

+ { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5

9594

+ (eval $ac_try) 2>&5

9595

+ ac_status=$?

9596

+ $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5

9597

+ test $ac_status = 0; }; }

9598

+ then

9599

+ gcc_cv_as_ix86_ud2=yes

9600

+ else

9601

+ echo "configure: failed program was" >&5

9602

+ cat conftest.s >&5

9603

+ fi

9604

+ rm -f conftest.o conftest.s

9605

+ fi

9606

+fi

9607

+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_ix86_ud2" >&5

9608

+$as_echo "$gcc_cv_as_ix86_ud2" >&6; }

9609

+if test $gcc_cv_as_ix86_ud2 = yes; then

9610

+

9611

+$as_echo "#define HAVE_AS_IX86_UD2 1" >>confdefs.h

9612

+

9613

+fi

9614

+

9615

{ $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for R_386_TLS_GD_PLT reloc" >&5

9616

$as_echo_n "checking assembler for R_386_TLS_GD_PLT reloc... " >&6; }

9617

if test "${gcc_cv_as_ix86_tlsgdplt+set}" = set; then :

9618

@@ -27239,8 +27321,8 @@

9619

$as_echo_n "checking for exported symbols... " >&6; }

9620

if test "x$export_sym_check" != x; then

9621

echo "int main() {return 0;} int foobar() {return 0;}" > conftest.c

9622

- ${CC} ${CFLAGS} ${LDFLAGS} conftest.c -o conftest > /dev/null 2>&1

9623

- if $export_sym_check conftest | grep foobar > /dev/null; then

9624

+ ${CC} ${CFLAGS} ${LDFLAGS} conftest.c -o conftest$ac_exeext > /dev/null 2>&1

9625

+ if $export_sym_check conftest$ac_exeext | grep -q foobar > /dev/null; then

9626

: # No need to use a flag

9627

{ $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5

9628

$as_echo "yes" >&6; }

9629

@@ -27249,8 +27331,8 @@

9630

$as_echo "yes" >&6; }

9631

{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for -rdynamic" >&5

9632

$as_echo_n "checking for -rdynamic... " >&6; }

9633

- ${CC} ${CFLAGS} ${LDFLAGS} -rdynamic conftest.c -o conftest > /dev/null 2>&1

9634

- if $export_sym_check conftest | grep foobar > /dev/null; then

9635

+ ${CC} ${CFLAGS} ${LDFLAGS} -rdynamic conftest.c -o conftest$ac_exeext > /dev/null 2>&1

9636

+ if $export_sym_check conftest$ac_exeext | grep -q foobar > /dev/null; then

9637

plugin_rdynamic=yes

9638

pluginlibs="-rdynamic"

9639

else

9640

Index: gcc/builtins.c

9641

===================================================================

9642

--- a/src/gcc/builtins.c (.../tags/gcc_4_8_2_release)

9643

+++ b/src/gcc/builtins.c (.../branches/gcc-4_8-branch)

9644

@@ -180,7 +180,6 @@

9645

static tree fold_builtin_strpbrk (location_t, tree, tree, tree);

9646

static tree fold_builtin_strstr (location_t, tree, tree, tree);

9647

static tree fold_builtin_strrchr (location_t, tree, tree, tree);

9648

-static tree fold_builtin_strcat (location_t, tree, tree);

9649

static tree fold_builtin_strncat (location_t, tree, tree, tree);

9650

static tree fold_builtin_strspn (location_t, tree, tree);

9651

static tree fold_builtin_strcspn (location_t, tree, tree);

9652

@@ -1958,6 +1957,7 @@

9653

tree fndecl = get_callee_fndecl (exp);

9654

enum machine_mode mode;

9655

bool errno_set = false;

9656

+ bool try_widening = false;

9657

tree arg;

9658

9659

if (!validate_arglist (exp, REAL_TYPE, VOID_TYPE))

9660

@@ -1969,6 +1969,7 @@

9661

{

9662

CASE_FLT_FN (BUILT_IN_SQRT):

9663

errno_set = ! tree_expr_nonnegative_p (arg);

9664

+ try_widening = true;

9665

builtin_optab = sqrt_optab;

9666

break;

9667

CASE_FLT_FN (BUILT_IN_EXP):

9668

@@ -2025,8 +2026,10 @@

9669

if (! flag_errno_math || ! HONOR_NANS (mode))

9670

errno_set = false;

9671

9672

- /* Before working hard, check whether the instruction is available. */

9673

- if (optab_handler (builtin_optab, mode) != CODE_FOR_nothing

9674

+ /* Before working hard, check whether the instruction is available, but try

9675

+ to widen the mode for specific operations. */

9676

+ if ((optab_handler (builtin_optab, mode) != CODE_FOR_nothing

9677

+ || (try_widening && !excess_precision_type (TREE_TYPE (exp))))

9678

&& (!errno_set || !optimize_insn_for_size_p ()))

9679

{

9680

rtx result = gen_reg_rtx (mode);

9681

@@ -5347,7 +5350,7 @@

9682

expand_builtin_atomic_compare_exchange (enum machine_mode mode, tree exp,

9683

rtx target)

9684

{

9685

- rtx expect, desired, mem, oldval;

9686

+ rtx expect, desired, mem, oldval, label;

9687

enum memmodel success, failure;

9688

tree weak;

9689

bool is_weak;

9690

@@ -5385,14 +5388,26 @@

9691

if (host_integerp (weak, 0) && tree_low_cst (weak, 0) != 0)

9692

is_weak = true;

9693

9694

- oldval = expect;

9695

- if (!expand_atomic_compare_and_swap ((target == const0_rtx ? NULL : &target),

9696

- &oldval, mem, oldval, desired,

9697

+ if (target == const0_rtx)

9698

+ target = NULL;

9699

+

9700

+ /* Lest the rtl backend create a race condition with an imporoper store

9701

+ to memory, always create a new pseudo for OLDVAL. */

9702

+ oldval = NULL;

9703

+

9704

+ if (!expand_atomic_compare_and_swap (&target, &oldval, mem, expect, desired,

9705

is_weak, success, failure))

9706

return NULL_RTX;

9707

9708

- if (oldval != expect)

9709

- emit_move_insn (expect, oldval);

9710

+ /* Conditionally store back to EXPECT, lest we create a race condition

9711

+ with an improper store to memory. */

9712

+ /* ??? With a rearrangement of atomics at the gimple level, we can handle

9713

+ the normal case where EXPECT is totally private, i.e. a register. At

9714

+ which point the store can be unconditional. */

9715

+ label = gen_label_rtx ();

9716

+ emit_cmp_and_jump_insns (target, const0_rtx, NE, NULL, VOIDmode, 1, label);

9717

+ emit_move_insn (expect, oldval);

9718

+ emit_label (label);

9719

9720

return target;

9721

}

9722

@@ -5846,6 +5861,9 @@

9723

switch (fcode)

9724

{

9725

CASE_FLT_FN (BUILT_IN_FABS):

9726

+ case BUILT_IN_FABSD32:

9727

+ case BUILT_IN_FABSD64:

9728

+ case BUILT_IN_FABSD128:

9729

target = expand_builtin_fabs (exp, target, subtarget);

9730

if (target)

9731

return target;

9732

@@ -10298,6 +10316,9 @@

9733

return fold_builtin_strlen (loc, type, arg0);

9734

9735

CASE_FLT_FN (BUILT_IN_FABS):

9736

+ case BUILT_IN_FABSD32:

9737

+ case BUILT_IN_FABSD64:

9738

+ case BUILT_IN_FABSD128:

9739

return fold_builtin_fabs (loc, arg0, type);

9740

9741

case BUILT_IN_ABS:

9742

@@ -10766,7 +10787,7 @@

9743

return fold_builtin_strstr (loc, arg0, arg1, type);

9744

9745

case BUILT_IN_STRCAT:

9746

- return fold_builtin_strcat (loc, arg0, arg1);

9747

+ return fold_builtin_strcat (loc, arg0, arg1, NULL_TREE);

9748

9749

case BUILT_IN_STRSPN:

9750

return fold_builtin_strspn (loc, arg0, arg1);

9751

@@ -11809,8 +11830,9 @@

9752

COMPOUND_EXPR in the chain will contain the tree for the simplified

9753

form of the builtin function call. */

9754

9755

-static tree

9756

-fold_builtin_strcat (location_t loc ATTRIBUTE_UNUSED, tree dst, tree src)

9757

+tree

9758

+fold_builtin_strcat (location_t loc ATTRIBUTE_UNUSED, tree dst, tree src,

9759

+ tree len)

9760

{

9761

if (!validate_arg (dst, POINTER_TYPE)

9762

|| !validate_arg (src, POINTER_TYPE))

9763

@@ -11828,22 +11850,17 @@

9764

/* See if we can store by pieces into (dst + strlen(dst)). */

9765

tree newdst, call;

9766

tree strlen_fn = builtin_decl_implicit (BUILT_IN_STRLEN);

9767

- tree strcpy_fn = builtin_decl_implicit (BUILT_IN_STRCPY);

9768

+ tree memcpy_fn = builtin_decl_implicit (BUILT_IN_MEMCPY);

9769

9770

- if (!strlen_fn || !strcpy_fn)

9771

+ if (!strlen_fn || !memcpy_fn)

9772

return NULL_TREE;

9773

9774

- /* If we don't have a movstr we don't want to emit an strcpy

9775

- call. We have to do that if the length of the source string

9776

- isn't computable (in that case we can use memcpy probably

9777

- later expanding to a sequence of mov instructions). If we

9778

- have movstr instructions we can emit strcpy calls. */

9779

- if (!HAVE_movstr)

9780

- {

9781

- tree len = c_strlen (src, 1);

9782

- if (! len || TREE_SIDE_EFFECTS (len))

9783

- return NULL_TREE;

9784

- }

9785

+ /* If the length of the source string isn't computable don't

9786

+ split strcat into strlen and memcpy. */

9787

+ if (! len)

9788

+ len = c_strlen (src, 1);

9789

+ if (! len || TREE_SIDE_EFFECTS (len))

9790

+ return NULL_TREE;

9791

9792

/* Stabilize the argument list. */

9793

dst = builtin_save_expr (dst);

9794

@@ -11855,7 +11872,11 @@

9795

newdst = fold_build_pointer_plus_loc (loc, dst, newdst);

9796

newdst = builtin_save_expr (newdst);

9797

9798

- call = build_call_expr_loc (loc, strcpy_fn, 2, newdst, src);

9799

+ len = fold_convert_loc (loc, size_type_node, len);

9800

+ len = size_binop_loc (loc, PLUS_EXPR, len,

9801

+ build_int_cst (size_type_node, 1));

9802

+

9803

+ call = build_call_expr_loc (loc, memcpy_fn, 3, newdst, src, len);

9804

return build2 (COMPOUND_EXPR, TREE_TYPE (dst), call, dst);

9805

}

9806

return NULL_TREE;

9807

Index: gcc/gcc.c

9808

===================================================================

9809

--- a/src/gcc/gcc.c (.../tags/gcc_4_8_2_release)

9810

+++ b/src/gcc/gcc.c (.../branches/gcc-4_8-branch)

9811

@@ -5441,7 +5441,7 @@

9812

const char *save_suffix_subst;

9813

9814

int save_growing_size;

9815

- void *save_growing_value;

9816

+ void *save_growing_value = NULL;

9817

9818

sf = lookup_spec_function (func);

9819

if (sf == NULL)

9820

Index: gcc/fold-const.c

9821

===================================================================

9822

--- a/src/gcc/fold-const.c (.../tags/gcc_4_8_2_release)

9823

+++ b/src/gcc/fold-const.c (.../branches/gcc-4_8-branch)

9824

@@ -461,8 +461,6 @@

9825

9826

case TRUNC_DIV_EXPR:

9827

case ROUND_DIV_EXPR:

9828

- case FLOOR_DIV_EXPR:

9829

- case CEIL_DIV_EXPR:

9830

case EXACT_DIV_EXPR:

9831

/* In general we can't negate A / B, because if A is INT_MIN and

9832

B is 1, we may turn this into INT_MIN / -1 which is undefined

9833

@@ -644,8 +642,6 @@

9834

9835

case TRUNC_DIV_EXPR:

9836

case ROUND_DIV_EXPR:

9837

- case FLOOR_DIV_EXPR:

9838

- case CEIL_DIV_EXPR:

9839

case EXACT_DIV_EXPR:

9840

/* In general we can't negate A / B, because if A is INT_MIN and

9841

B is 1, we may turn this into INT_MIN / -1 which is undefined

9842

@@ -2664,10 +2660,11 @@

9843

case COMPONENT_REF:

9844

/* Handle operand 2 the same as for ARRAY_REF. Operand 0

9845

may be NULL when we're called to compare MEM_EXPRs. */

9846

- if (!OP_SAME_WITH_NULL (0))

9847

+ if (!OP_SAME_WITH_NULL (0)

9848

+ || !OP_SAME (1))

9849

return 0;

9850

flags &= ~OEP_CONSTANT_ADDRESS_OF;

9851

- return OP_SAME (1) && OP_SAME_WITH_NULL (2);

9852

+ return OP_SAME_WITH_NULL (2);

9853

9854

case BIT_FIELD_REF:

9855

if (!OP_SAME (0))

9856

@@ -4920,12 +4917,16 @@

9857

int in0_p, in1_p, in_p;

9858

tree low0, low1, low, high0, high1, high;

9859

bool strict_overflow_p = false;

9860

- tree lhs = make_range (op0, &in0_p, &low0, &high0, &strict_overflow_p);

9861

- tree rhs = make_range (op1, &in1_p, &low1, &high1, &strict_overflow_p);

9862

- tree tem;

9863

+ tree tem, lhs, rhs;

9864

const char * const warnmsg = G_("assuming signed overflow does not occur "

9865

"when simplifying range test");

9866

9867

+ if (!INTEGRAL_TYPE_P (type))

9868

+ return 0;

9869

+

9870

+ lhs = make_range (op0, &in0_p, &low0, &high0, &strict_overflow_p);

9871

+ rhs = make_range (op1, &in1_p, &low1, &high1, &strict_overflow_p);

9872

+

9873

/* If this is an OR operation, invert both sides; we will invert

9874

again at the end. */

9875

if (or_op)

9876

@@ -10927,6 +10928,13 @@

9877

fold_build2_loc (loc, MULT_EXPR, type,

9878

build_int_cst (type, 2) , arg1));

9879

9880

+ /* ((T) (X /[ex] C)) * C cancels out if the conversion is

9881

+ sign-changing only. */

9882

+ if (TREE_CODE (arg1) == INTEGER_CST

9883

+ && TREE_CODE (arg0) == EXACT_DIV_EXPR

9884

+ && operand_equal_p (arg1, TREE_OPERAND (arg0, 1), 0))

9885

+ return fold_convert_loc (loc, type, TREE_OPERAND (arg0, 0));

9886

+

9887

strict_overflow_p = false;

9888

if (TREE_CODE (arg1) == INTEGER_CST

9889

&& 0 != (tem = extract_muldiv (op0, arg1, code, NULL_TREE,

9890

@@ -16587,7 +16595,7 @@

9891

unsigned HOST_WIDE_INT indexi = offset * BITS_PER_UNIT;

9892

tree index = bitsize_int (indexi);

9893

9894

- if (offset/part_widthi <= TYPE_VECTOR_SUBPARTS (op00type))

9895

+ if (offset / part_widthi < TYPE_VECTOR_SUBPARTS (op00type))

9896

return fold_build3_loc (loc,

9897

BIT_FIELD_REF, type, op00,

9898

part_width, index);

9899

Index: gcc/objc/ChangeLog

9900

===================================================================

9901

--- a/src/gcc/objc/ChangeLog (.../tags/gcc_4_8_2_release)

9902

+++ b/src/gcc/objc/ChangeLog (.../branches/gcc-4_8-branch)

9903

@@ -1,3 +1,14 @@

9904

+2014-04-07 Dominique d'Humieres <dominiq@lps.ens.fr>

9905

+

9906

+ Backport from mainline

9907

+ 2013-09-14 Iain Sandoe <iains@gcc.gnu.org>

9908

+

9909

+ PR target/48094

9910

+ * objc-next-runtime-abi-01.c (generate_objc_image_info): Remove.

9911

+ (objc_generate_v1_next_metadata): Remove generation of ImageInfo.

9912

+ * objc-next-runtime-abi-02.c (generate_v2_objc_image_info): Remove.

9913

+ (objc_generate_v2_next_metadata): Remove generation of ImageInfo.

9914

+

9915

2013-10-16 Release Manager

9916

9917

* GCC 4.8.2 released.

9918

Index: gcc/objc/objc-next-runtime-abi-01.c

9919

===================================================================

9920

--- a/src/gcc/objc/objc-next-runtime-abi-01.c (.../tags/gcc_4_8_2_release)

9921

+++ b/src/gcc/objc/objc-next-runtime-abi-01.c (.../branches/gcc-4_8-branch)

9922

@@ -2332,37 +2332,7 @@

9923

return;

9924

}

9925

9926

-

9927

-/* The Fix-and-Continue functionality available in Mac OS X 10.3 and

9928

- later requires that ObjC translation units participating in F&C be

9929

- specially marked. The following routine accomplishes this. */

9930

-

9931

-/* static int _OBJC_IMAGE_INFO[2] = { 0, 1 }; */

9932

-

9933

static void

9934

-generate_objc_image_info (void)

9935

-{

9936

- tree decl;

9937

- int flags

9938

- = ((flag_replace_objc_classes && imp_count ? 1 : 0)

9939

- | (flag_objc_gc ? 2 : 0));

9940

- vec<constructor_elt, va_gc> *v = NULL;

9941

- tree array_type;

9942

-

9943

- array_type = build_sized_array_type (integer_type_node, 2);

9944

-

9945

- decl = start_var_decl (array_type, "_OBJC_ImageInfo");

9946

-

9947

- CONSTRUCTOR_APPEND_ELT (v, NULL_TREE, integer_zero_node);

9948

- CONSTRUCTOR_APPEND_ELT (v, NULL_TREE, build_int_cst (integer_type_node, flags));

9949

- /* The runtime wants this and refers to it in a manner hidden from the compiler.

9950

- So we must force the output. */

9951

- DECL_PRESERVE_P (decl) = 1;

9952

- OBJCMETA (decl, objc_meta, meta_info);

9953

- finish_var_decl (decl, objc_build_constructor (TREE_TYPE (decl), v));

9954

-}

9955

-

9956

-static void

9957

objc_generate_v1_next_metadata (void)

9958

{

9959

struct imp_entry *impent;

9960

@@ -2412,9 +2382,6 @@

9961

attr = build_tree_list (objc_meta, meta_modules);

9962

build_module_descriptor (vers, attr);

9963

9964

- /* This conveys information on GC usage and zero-link. */

9965

- generate_objc_image_info ();

9966

-

9967

/* Dump the class references. This forces the appropriate classes

9968

to be linked into the executable image, preserving unix archive

9969

semantics. */

9970

Index: gcc/objc/objc-next-runtime-abi-02.c

9971

===================================================================

9972

--- a/src/gcc/objc/objc-next-runtime-abi-02.c (.../tags/gcc_4_8_2_release)

9973

+++ b/src/gcc/objc/objc-next-runtime-abi-02.c (.../branches/gcc-4_8-branch)

9974

@@ -3329,32 +3329,7 @@

9975

finish_var_decl (ref->decl, ref->offset);

9976

}

9977

9978

-/* static int _OBJC_IMAGE_INFO[2] = { 0, 16 | flags }; */

9979

-

9980

static void

9981

-generate_v2_objc_image_info (void)

9982

-{

9983

- tree decl, array_type;

9984

- vec<constructor_elt, va_gc> *v = NULL;

9985

- int flags =

9986

- ((flag_replace_objc_classes && imp_count ? 1 : 0)

9987

- | (flag_objc_gc ? 2 : 0));

9988

-

9989

- flags |= 16;

9990

-

9991

- array_type = build_sized_array_type (integer_type_node, 2);

9992

-

9993

- decl = start_var_decl (array_type, "_OBJC_ImageInfo");

9994

-

9995

- CONSTRUCTOR_APPEND_ELT (v, NULL_TREE, integer_zero_node);

9996

- CONSTRUCTOR_APPEND_ELT (v, NULL_TREE, build_int_cst (integer_type_node, flags));

9997

- /* The Runtime wants this. */

9998

- DECL_PRESERVE_P (decl) = 1;

9999

- OBJCMETA (decl, objc_meta, meta_info);

10000

- finish_var_decl (decl, objc_build_constructor (TREE_TYPE (decl), v));

10001

-}

10002

-

10003

-static void

10004

objc_generate_v2_next_metadata (void)

10005

{

10006

struct imp_entry *impent;

10007

@@ -3405,9 +3380,6 @@

10008

build_v2_address_table (nonlazy_category_list, "_OBJC_NonLazyCategoryList$",

10009

meta_label_nonlazy_categorylist);

10010

10011

- /* This conveys information on GC usage and zero-link. */

10012

- generate_v2_objc_image_info ();

10013

-

10014

/* Generate catch objects for eh, if any are needed. */

10015

build_v2_eh_catch_objects ();

10016

10017

Index: gcc/reorg.c

10018

===================================================================

10019

--- a/src/gcc/reorg.c (.../tags/gcc_4_8_2_release)

10020

+++ b/src/gcc/reorg.c (.../branches/gcc-4_8-branch)

10021

@@ -1105,6 +1105,7 @@

10022

int used_annul = 0;

10023

int i;

10024

struct resources cc_set;

10025

+ bool *redundant;

10026

10027

/* We can't do anything if there are more delay slots in SEQ than we

10028

can handle, or if we don't know that it will be a taken branch.

10029

@@ -1145,6 +1146,7 @@

10030

return delay_list;

10031

#endif

10032

10033

+ redundant = XALLOCAVEC (bool, XVECLEN (seq, 0));

10034

for (i = 1; i < XVECLEN (seq, 0); i++)

10035

{

10036

rtx trial = XVECEXP (seq, 0, i);

10037

@@ -1166,7 +1168,8 @@

10038

10039

/* If this insn was already done (usually in a previous delay slot),

10040

pretend we put it in our delay slot. */

10041

- if (redundant_insn (trial, insn, new_delay_list))

10042

+ redundant[i] = redundant_insn (trial, insn, new_delay_list);

10043

+ if (redundant[i])

10044

continue;

10045

10046

/* We will end up re-vectoring this branch, so compute flags

10047

@@ -1199,6 +1202,12 @@

10048

return delay_list;

10049

}

10050

10051

+ /* Record the effect of the instructions that were redundant and which

10052

+ we therefore decided not to copy. */

10053

+ for (i = 1; i < XVECLEN (seq, 0); i++)

10054

+ if (redundant[i])

10055

+ update_block (XVECEXP (seq, 0, i), insn);

10056

+

10057

/* Show the place to which we will be branching. */

10058

*pnew_thread = first_active_target_insn (JUMP_LABEL (XVECEXP (seq, 0, 0)));

10059

10060

@@ -1262,6 +1271,7 @@

10061

/* If this insn was already done, we don't need it. */

10062

if (redundant_insn (trial, insn, delay_list))

10063

{

10064

+ update_block (trial, insn);

10065

delete_from_delay_slot (trial);

10066

continue;

10067

}

10068

@@ -3266,6 +3276,7 @@

10069

to reprocess this insn. */

10070

if (redundant_insn (XVECEXP (pat, 0, 1), delay_insn, 0))

10071

{

10072

+ update_block (XVECEXP (pat, 0, 1), insn);

10073

delete_from_delay_slot (XVECEXP (pat, 0, 1));

10074

next = prev_active_insn (next);

10075

continue;

10076

@@ -3385,6 +3396,7 @@

10077

&& redirect_with_delay_slots_safe_p (delay_insn, target_label,

10078

insn))

10079

{

10080

+ update_block (XVECEXP (PATTERN (trial), 0, 1), insn);

10081

reorg_redirect_jump (delay_insn, target_label);

10082

next = insn;

10083

continue;

10084

Index: gcc/tree-ssa-sccvn.c

10085

===================================================================

10086

--- a/src/gcc/tree-ssa-sccvn.c (.../tags/gcc_4_8_2_release)

10087

+++ b/src/gcc/tree-ssa-sccvn.c (.../branches/gcc-4_8-branch)

10088

@@ -660,7 +660,7 @@

10089

}

10090

10091

/* For non-calls, store the information that makes up the address. */

10092

-

10093

+ tree orig = ref;

10094

while (ref)

10095

{

10096

vn_reference_op_s temp;

10097

@@ -711,7 +711,15 @@

10098

.arshift (BITS_PER_UNIT == 8

10099

? 3 : exact_log2 (BITS_PER_UNIT),

10100

HOST_BITS_PER_DOUBLE_INT);

10101

- if (off.fits_shwi ())

10102

+ if (off.fits_shwi ()

10103

+ /* Probibit value-numbering zero offset components

10104

+ of addresses the same before the pass folding

10105

+ __builtin_object_size had a chance to run

10106

+ (checking cfun->after_inlining does the

10107

+ trick here). */

10108

+ && (TREE_CODE (orig) != ADDR_EXPR

10109

+ || !off.is_zero ()

10110

+ || cfun->after_inlining))

10111

temp.off = off.low;

10112

}

10113

}

10114

Index: gcc/ChangeLog

10115

===================================================================

10116

--- a/src/gcc/ChangeLog (.../tags/gcc_4_8_2_release)

10117

+++ b/src/gcc/ChangeLog (.../branches/gcc-4_8-branch)

10118

@@ -1,3 +1,5367 @@

10119

+2014-05-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com>

10120

+

10121

+ * config.gcc (aarch64*-*-*): Use ISA flags from aarch64-arches.def.

10122

+ Do not define target_cpu_default2 to generic.

10123

+

10124

+2014-05-06 Richard Biener <rguenther@suse.de>

10125

+

10126

+ Backport from mainline

10127

+ 2014-04-14 Richard Biener <rguenther@suse.de>

10128

+

10129

+ PR middle-end/55022

10130

+ * fold-const.c (negate_expr_p): Don't negate directional rounding

10131

+ division.

10132

+ (fold_negate_expr): Likewise.

10133

+

10134

+2014-05-06 Richard Biener <rguenther@suse.de>

10135

+

10136

+ Backport from mainline

10137

+ 2014-04-17 Richard Biener <rguenther@suse.de>

10138

+

10139

+ PR middle-end/60849

10140

+ * tree-ssa-propagate.c (valid_gimple_rhs_p): Only allow effective

10141

+ boolean results for comparisons.

10142

+

10143

+ 2014-04-07 Richard Biener <rguenther@suse.de>

10144

+

10145

+ PR tree-optimization/60766

10146

+ * tree-ssa-loop-ivopts.c (cand_value_at): Compute in an

10147

+ unsigned type.

10148

+ (may_eliminate_iv): Convert cand_value_at result to desired

10149

+ type.

10150

+

10151

+ 2014-04-23 Richard Biener <rguenther@suse.de>

10152

+

10153

+ PR tree-optimization/60903

10154

+ * tree-ssa-loop-im.c (execute_sm_if_changed): Properly apply

10155

+ IRREDUCIBLE_LOOP loop flags to newly created BBs and edges.

10156

+

10157

+2014-05-05 Richard Biener <rguenther@suse.de>

10158

+

10159

+ Backport from mainline

10160

+ 2014-04-23 Richard Biener <rguenther@suse.de>

10161

+

10162

+ PR middle-end/60895

10163

+ * tree-inline.c (declare_return_variable): Use mark_addressable.

10164

+

10165

+ 2014-04-07 Richard Biener <rguenther@suse.de>

10166

+

10167

+ PR middle-end/60750

10168

+ * tree-ssa-operands.c (maybe_add_call_vops): Also add VDEFs

10169

+ for noreturn calls.

10170

+ * tree-cfgcleanup.c (fixup_noreturn_call): Do not remove VDEFs.

10171

+

10172

+ 2014-04-14 Richard Biener <rguenther@suse.de>

10173

+

10174

+ PR tree-optimization/59817

10175

+ PR tree-optimization/60453

10176

+ * graphite-scop-detection.c (graphite_can_represent_scev): Complete

10177

+ recursion to catch all CHRECs in the scalar evolution and restrict

10178

+ the predicate for the remains appropriately.

10179

+

10180

+ 2014-04-17 Richard Biener <rguenther@suse.de>

10181

+

10182

+ PR tree-optimization/60836

10183

+ * tree-vect-loop.c (vect_create_epilog_for_reduction): Force

10184

+ initial PHI args to be gimple values.

10185

+

10186

+2014-05-05 Jakub Jelinek <jakub@redhat.com>

10187

+

10188

+ Backported from mainline

10189

+ 2014-04-25 Jakub Jelinek <jakub@redhat.com>

10190

+

10191

+ PR tree-optimization/60960

10192

+ * tree-vect-generic.c (expand_vector_operation): Only call

10193

+ expand_vector_divmod if type's mode satisfies VECTOR_MODE_P.

10194

+

10195

+2014-05-04 Peter Bergner <bergner@vnet.ibm.com>

10196

+

10197

+ * config/rs6000/rs6000.h (RS6000_BTM_HARD_FLOAT): New define.

10198

+ (RS6000_BTM_COMMON): Add RS6000_BTM_HARD_FLOAT.

10199

+ (TARGET_EXTRA_BUILTINS): Add TARGET_HARD_FLOAT.

10200

+ * config/rs6000/rs6000-builtin.def (BU_MISC_1):

10201

+ Use RS6000_BTM_HARD_FLOAT.

10202

+ (BU_MISC_2): Likewise.

10203

+ * config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Handle

10204

+ RS6000_BTM_HARD_FLOAT.

10205

+ (rs6000_option_override_internal): Enforce -mhard-float if -mhard-dfp

10206

+ is explicitly used.

10207

+ (rs6000_invalid_builtin): Add hard floating builtin support.

10208

+ (rs6000_expand_builtin): Relax the gcc_assert to allow the new

10209

+ hard float builtins.

10210

+ (rs6000_builtin_mask_names): Add RS6000_BTM_HARD_FLOAT.

10211

+

10212

+2014-05-03 Joey Ye <joey.ye@arm.com>

10213

+

10214

+ Backport from mainline r209463

10215

+ 2014-04-17 Joey Ye <joey.ye@arm.com>

10216

+

10217

+ * opts.c (OPT_fif_conversion, OPT_fif_conversion2): Disable for Og.

10218

+

10219

+2014-05-03 Oleg Endo <olegendo@gcc.gnu.org>

10220

+

10221

+ Back port from mainline

10222

+ PR target/61026

10223

+ * config/sh/sh.c: Include stdlib headers before everything else.

10224

+

10225

+2014-05-02 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10226

+

10227

+ PR tree-optimization/60930

10228

+ * gimple-ssa-strength-reduction.c (create_mul_imm_cand): Reject

10229

+ creating a multiply candidate by folding two constant

10230

+ multiplicands when the result overflows.

10231

+

10232

+2014-05-02 Kyrylo Tkachov <kyrylo.tkachov@arm.com>

10233

+

10234

+ * config/aarch64/aarch64.h (TARGET_SIMD): Take AARCH64_ISA_SIMD

10235

+ into account.

10236

+ (TARGET_FLOAT): Take AARCH64_ISA_FP into account.

10237

+

10238

+2014-04-30 Michael Meissner <meissner@linux.vnet.ibm.com>

10239

+

10240

+ Back port from mainline

10241

+ 2014-04-24 Michael Meissner <meissner@linux.vnet.ibm.com>

10242

+

10243

+ * doc/extend.texi (PowerPC Built-in Functions): Document new

10244

+ powerpc extended divide, bcd, pack/unpack 128-bit, builtin

10245

+ functions.

10246

+ (PowerPC AltiVec/VSX Built-in Functions): Likewise.

10247

+

10248

+ * config/rs6000/predicates.md (const_0_to_3_operand): New

10249

+ predicate to match 0..3 integer constants.

10250

+

10251

+ * config/rs6000/rs6000-builtin.def (BU_DFP_MISC_1): Add new macros

10252

+ to support adding miscellaneous builtin functions.

10253

+ (BU_DFP_MISC_2): Likewise.

10254

+ (BU_P7_MISC_1): Likewise.

10255

+ (BU_P7_MISC_2): Likewise.

10256

+ (BU_P8V_MISC_3): Likewise.

10257

+ (BU_MISC_1): Likewise.

10258

+ (BU_MISC_2): Likewise.

10259

+ (DIVWE): Add extended divide builtin functions.

10260

+ (DIVWEO): Likewise.

10261

+ (DIVWEU): Likewise.

10262

+ (DIVWEUO): Likewise.

10263

+ (DIVDE): Likewise.

10264

+ (DIVDEO): Likewise.

10265

+ (DIVDEU): Likewise.

10266

+ (DIVDEUO): Likewise.

10267

+ (DXEX): Add decimal floating-point builtin functions.

10268

+ (DXEXQ): Likewise.

10269

+ (DDEDPD): Likewise.

10270

+ (DDEDPDQ): Likewise.

10271

+ (DENBCD): Likewise.

10272

+ (DENBCDQ): Likewise.

10273

+ (DIEX): Likewise.

10274

+ (DIEXQ): Likewise.

10275

+ (DSCLI): Likewise.

10276

+ (DSCLIQ): Likewise.

10277

+ (DSCRI): Likewise.

10278

+ (DSCRIQ): Likewise.

10279

+ (CDTBCD): Add new BCD builtin functions.

10280

+ (CBCDTD): Likewise.

10281

+ (ADDG6S): Likewise.

10282

+ (BCDADD): Likewise.

10283

+ (BCDADD_LT): Likewise.

10284

+ (BCDADD_EQ): Likewise.

10285

+ (BCDADD_GT): Likewise.

10286

+ (BCDADD_OV): Likewise.

10287

+ (BCDSUB): Likewise.

10288

+ (BCDSUB_LT): Likewise.

10289

+ (BCDSUB_EQ): Likewise.

10290

+ (BCDSUB_GT): Likewise.

10291

+ (BCDSUB_OV): Likewise.

10292

+ (PACK_TD): Add new pack/unpack 128-bit type builtin functions.

10293

+ (UNPACK_TD): Likewise.

10294

+ (PACK_TF): Likewise.

10295

+ (UNPACK_TF): Likewise.

10296

+ (UNPACK_TF_0): Likewise.

10297

+ (UNPACK_TF_1): Likewise.

10298

+ (PACK_V1TI): Likewise.

10299

+ (UNPACK_V1TI): Likewise.

10300

+

10301

+ * config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Add

10302

+ support for decimal floating point builtin functions.

10303

+ (rs6000_expand_ternop_builtin): Add checks for the new builtin

10304

+ functions that take constant arguments.

10305

+ (rs6000_invalid_builtin): Add decimal floating point builtin

10306

+ support.

10307

+ (rs6000_init_builtins): Setup long double, _Decimal64, and

10308

+ _Decimal128 types for new builtin functions.

10309

+ (builtin_function_type): Set the unsigned flags appropriately for

10310

+ the new builtin functions.

10311

+ (rs6000_opt_masks): Add support for decimal floating point builtin

10312

+ functions.

10313

+

10314

+ * config/rs6000/rs6000.h (RS6000_BTM_DFP): Add support for decimal

10315

+ floating point builtin functions.

10316

+ (RS6000_BTM_COMMON): Likewise.

10317

+ (RS6000_BTI_long_double): Likewise.

10318

+ (RS6000_BTI_dfloat64): Likewise.

10319

+ (RS6000_BTI_dfloat128): Likewise.

10320

+ (long_double_type_internal_node): Likewise.

10321

+ (dfloat64_type_internal_node): Likewise.

10322

+ (dfloat128_type_internal_node): Likewise.

10323

+

10324

+ * config/rs6000/altivec.h (UNSPEC_BCDADD): Add support for ISA

10325

+ 2.07 bcd arithmetic instructions.

10326

+ (UNSPEC_BCDSUB): Likewise.

10327

+ (UNSPEC_BCD_OVERFLOW): Likewise.

10328

+ (UNSPEC_BCD_ADD_SUB): Likewise.

10329

+ (bcd_add_sub): Likewise.

10330

+ (BCD_TEST): Likewise.

10331

+ (bcd<bcd_add_sub>): Likewise.

10332

+ (bcd<bcd_add_sub>_test): Likewise.

10333

+ (bcd<bcd_add_sub>_test2): Likewise.

10334

+ (bcd<bcd_add_sub>_<code>): Likewise.

10335

+ (peephole2 for combined bcd ops): Likewise.

10336

+

10337

+ * config/rs6000/dfp.md (UNSPEC_DDEDPD): Add support for new

10338

+ decimal floating point builtin functions.

10339

+ (UNSPEC_DENBCD): Likewise.

10340

+ (UNSPEC_DXEX): Likewise.

10341

+ (UNSPEC_DIEX): Likewise.

10342

+ (UNSPEC_DSCLI): Likewise.

10343

+ (UNSPEC_DSCRI): Likewise.

10344

+ (D64_D128): Likewise.

10345

+ (dfp_suffix): Likewise.

10346

+ (dfp_ddedpd_<mode>): Likewise.

10347

+ (dfp_denbcd_<mode>): Likewise.

10348

+ (dfp_dxex_<mode>): Likewise.

10349

+ (dfp_diex_<mode>): Likewise.

10350

+ (dfp_dscli_<mode>): Likewise.

10351

+ (dfp_dscri_<mode>): Likewise.

10352

+

10353

+ * config/rs6000/rs6000.md (UNSPEC_ADDG6S): Add support for new BCD

10354

+ builtin functions.

10355

+ (UNSPEC_CDTBCD): Likewise.

10356

+ (UNSPEC_CBCDTD): Likewise.

10357

+ (UNSPEC_DIVE): Add support for new extended divide builtin

10358

+ functions.

10359

+ (UNSPEC_DIVEO): Likewise.

10360

+ (UNSPEC_DIVEU): Likewise.

10361

+ (UNSPEC_DIVEUO): Likewise.

10362

+ (UNSPEC_UNPACK_128BIT): Add support for new builtin functions to

10363

+ pack/unpack 128-bit types.

10364

+ (UNSPEC_PACK_128BIT): Likewise.

10365

+ (idiv_ldiv): New mode attribute to set the 32/64-bit divide type.

10366

+ (udiv<mode>3): Use idiv_ldiv mode attribute.

10367

+ (div<mode>3): Likewise.

10368

+ (addg6s): Add new BCD builtin functions.

10369

+ (cdtbcd): Likewise.

10370

+ (cbcdtd): Likewise.

10371

+ (UNSPEC_DIV_EXTEND): Add support for new extended divide

10372

+ instructions.

10373

+ (div_extend): Likewise.

10374

+ (div<div_extend>_<mode>"): Likewise.

10375

+ (FP128_64): Add support for new builtin functions to pack/unpack

10376

+ 128-bit types.

10377

+ (unpack<mode>): Likewise.

10378

+ (unpacktf_0): Likewise.

10379

+ (unpacktf_1): Likewise.

10380

+ (unpack<mode>_dm): Likewise.

10381

+ (unpack<mode>_nodm): Likewise.

10382

+ (pack<mode>): Likewise.

10383

+ (unpackv1ti): Likewise.

10384

+ (packv1ti): Likewise.

10385

+

10386

+2014-04-29 Pat Haugen <pthaugen@us.ibm.com>

10387

+

10388

+ Backport from mainline

10389

+ 2014-04-17 Pat Haugen <pthaugen@us.ibm.com>

10390

+

10391

+ * config/rs6000/rs6000.md (addti3, subti3): New.

10392

+

10393

+2014-04-28 Pat Haugen <pthaugen@us.ibm.com>

10394

+

10395

+ Backport from mainline

10396

+ 2014-04-28 Pat Haugen <pthaugen@us.ibm.com>

10397

+

10398

+ * config/rs6000/sync.md (AINT mode_iterator): Move definition.

10399

+ (loadsync_<mode>): Change mode.

10400

+ (load_quadpti, store_quadpti): New.

10401

+ (atomic_load<mode>, atomic_store<mode>): Add support for TI mode.

10402

+ * config/rs6000/rs6000.md (unspec enum): Add UNSPEC_LSQ.

10403

+

10404

+2014-04-28 Eric Botcazou <ebotcazou@adacore.com>

10405

+

10406

+ * configure.ac: Tweak GAS check for LEON instructions on SPARC.

10407

+ * configure: Regenerate.

10408

+ * config/sparc/sparc.opt (muser-mode): New option.

10409

+ * config/sparc/sync.md (atomic_compare_and_swap<mode>_1): Do not enable

10410

+ for LEON3.

10411

+ (atomic_compare_and_swap_leon3_1): New instruction for LEON3.

10412

+ * doc/invoke.texi (SPARC options): Document -muser-mode.

10413

+

10414

+2014-04-25 Eric Botcazou <ebotcazou@adacore.com>

10415

+

10416

+ PR target/60941

10417

+ * config/sparc/sparc.md (ashlsi3_extend): Delete.

10418

+

10419

+2014-04-22 Michael Meissner <meissner@linux.vnet.ibm.com>

10420

+

10421

+ Back port from main line:

10422

+ 2014-03-27 Michael Meissner <meissner@linux.vnet.ibm.com>

10423

+

10424

+ * config/rs6000/rs6000-builtins.def (VBPERMQ): Add vbpermq builtin

10425

+ for ISA 2.07.

10426

+

10427

+ * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add

10428

+ vbpermq builtins.

10429

+

10430

+ * config/rs6000/altivec.md (UNSPEC_VBPERMQ): Add support for the

10431

+ vbpermq instruction.

10432

+ (altivec_vbpermq): Likewise.

10433

+

10434

+ PR target/60672

10435

+ * config/rs6000/altivec.h (vec_xxsldwi): Add missing define to

10436

+ enable use of xxsldwi and xxpermdi builtin functions.

10437

+ (vec_xxpermdi): Likewise.

10438

+

10439

+ * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions):

10440

+ Document use of vec_xxsldwi and vec_xxpermdi builtins.

10441

+

10442

+2014-04-23 Uros Bizjak <ubizjak@gmail.com>

10443

+

10444

+ Backport from mainline

10445

+ 2014-04-21 Uros Bizjak <ubizjak@gmail.com>

10446

+

10447

+ PR target/60909

10448

+ * config/i386/i386.c (ix86_expand_builtin)

10449

+ <case IX86_BUILTIN_RDRAND{16,32,64}_STEP>: Use temporary

10450

+ register for target RTX.

10451

+ <case IX86_BUILTIN_RDSEED{16,32,64}_STEP>: Ditto.

10452

+

10453

+2014-04-23 Richard Biener <rguenther@suse.de>

10454

+

10455

+ Backport from mainline

10456

+ 2014-04-02 Richard Biener <rguenther@suse.de>

10457

+

10458

+ PR middle-end/60729

10459

+ * optabs.c (expand_abs_nojump): Honor flag_trapv only for

10460

+ MODE_INTs. Properly use negv_optab.

10461

+ (expand_abs): Likewise.

10462

+

10463

+ 2014-04-03 Richard Biener <rguenther@suse.de>

10464

+

10465

+ PR tree-optimization/60740

10466

+ * graphite-scop-detection.c (stmt_simple_for_scop_p): Iterate

10467

+ over all GIMPLE_COND operands.

10468

+

10469

+2014-04-23 Richard Biener <rguenther@suse.de>

10470

+

10471

+ PR middle-end/60635

10472

+ * gimplify.c (gimple_regimplify_operands): Update the

10473

+ re-gimplifed stmt.

10474

+

10475

+2014-04-21 Michael Meissner <meissner@linux.vnet.ibm.com>

10476

+

10477

+ Back port from the trunk, subversion id 209546.

10478

+

10479

+ 2014-04-21 Michael Meissner <meissner@linux.vnet.ibm.com>

10480

+

10481

+ PR target/60735

10482

+ * config/rs6000/rs6000.md (mov<mode>_softfloat32, FMOVE64 case):

10483

+ If mode is DDmode and TARGET_E500_DOUBLE allow move.

10484

+

10485

+ * config/rs6000/rs6000.c (rs6000_debug_reg_global): Print some

10486

+ more debug information for E500 if -mdebug=reg.

10487

+

10488

+2014-04-18 Richard Henderson <rth@redhat.com>

10489

+

10490

+ * config/aarch64/aarch64.c (aarch64_register_move_cost): Pass a mode

10491

+ to GET_MODE_SIZE, not a reg_class_t.

10492

+

10493

+2014-04-17 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10494

+

10495

+ * config/rs6000/vsx.md (vsx_xxmrghw_<mode>): Adjust for

10496

+ little-endian.

10497

+ (vsx_xxmrglw_<mode>): Likewise.

10498

+

10499

+2014-04-15 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10500

+

10501

+ PR target/60839

10502

+ Revert the following patch

10503

+

10504

+ 2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10505

+

10506

+ Back port mainline subversion id 209025.

10507

+ 2014-04-02 Michael Meissner <meissner@linux.vnet.ibm.com>

10508

+

10509

+ PR target/60735

10510

+ * config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): If we have

10511

+ software floating point or no floating point registers, do not

10512

+ allow any type in the FPRs. Eliminate a test for SPE SIMD types

10513

+ in GPRs that occurs after we tested for GPRs that would never be

10514

+ true.

10515

+

10516

+ * config/rs6000/rs6000.md (mov<mode>_softfloat32, FMOVE64):

10517

+ Rewrite tests to use TARGET_DOUBLE_FLOAT and TARGET_E500_DOUBLE,

10518

+ since the FMOVE64 type is DFmode/DDmode. If TARGET_E500_DOUBLE,

10519

+ specifically allow DDmode, since that does not use the SPE SIMD

10520

+ instructions.

10521

+

10522

+2014-04-10 Vladimir Makarov <vmakarov@redhat.com>

10523

+

10524

+ PR rtl-optimization/60769

10525

+ * lra-constraints.c (simplify_operand_subreg): Force reload of

10526

+ paradoxical subreg if it is not in the class contents.

10527

+

10528

+2014-04-10 Jakub Jelinek <jakub@redhat.com>

10529

+

10530

+ Backport from mainline

10531

+ 2014-03-12 Jakub Jelinek <jakub@redhat.com>

10532

+ Marc Glisse <marc.glisse@inria.fr>

10533

+

10534

+ PR tree-optimization/60502

10535

+ * tree-ssa-reassoc.c (eliminate_not_pairs): Use build_all_ones_cst

10536

+ instead of build_low_bits_mask.

10537

+

10538

+ 2013-06-13 Marc Glisse <marc.glisse@inria.fr>

10539

+

10540

+ * tree.c (build_all_ones_cst): New function.

10541

+ * tree.h (build_all_ones_cst): Declare it.

10542

+

10543

+ 2013-05-10 Marc Glisse <marc.glisse@inria.fr>

10544

+

10545

+ * tree.c (build_minus_one_cst): New function.

10546

+ * tree.h (build_minus_one_cst): Declare new function.

10547

+

10548

+2014-04-10 Jakub Jelinek <jakub@redhat.com>

10549

+

10550

+ Backport from mainline

10551

+ 2014-03-28 Jakub Jelinek <jakub@redhat.com>

10552

+

10553

+ PR target/60693

10554

+ * config/i386/i386.c (ix86_copy_addr_to_reg): Call copy_addr_to_reg

10555

+ also if addr has VOIDmode.

10556

+

10557

+ 2014-03-17 Jakub Jelinek <jakub@redhat.com>

10558

+

10559

+ PR target/60516

10560

+ * config/i386/i386.c (ix86_expand_epilogue): Adjust REG_CFA_ADJUST_CFA

10561

+ note creation for the 2010-08-31 changes.

10562

+

10563

+ 2014-03-06 Jakub Jelinek <jakub@redhat.com>

10564

+ Meador Inge <meadori@codesourcery.com>

10565

+

10566

+ PR target/58595

10567

+ * config/arm/arm.c (arm_tls_symbol_p): Remove.

10568

+ (arm_legitimize_address): Call legitimize_tls_address for any

10569

+ arm_tls_referenced_p expression, handle constant addend. Call it

10570

+ before testing for !TARGET_ARM.

10571

+ (thumb_legitimize_address): Don't handle arm_tls_symbol_p here.

10572

+

10573

+2014-04-09 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10574

+

10575

+ Backport from mainline r208750

10576

+ 2014-03-21 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10577

+

10578

+ * config/rs6000/rs6000.c (rs6000_expand_vector_set): Generate a

10579

+ pattern for vector nor instead of subtract from splat(-1).

10580

+ (altivec_expand_vec_perm_const_le): Likewise.

10581

+

10582

+ Backport from mainline r209235

10583

+ 2014-04-08 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10584

+

10585

+ * config/rs6000/rs6000.c (rs6000_expand_vector_set): Use vnand

10586

+ instead of vnor to exploit possible fusion opportunity in the

10587

+ future.

10588

+ (altivec_expand_vec_perm_const_le): Likewise.

10589

+

10590

+2014-04-09 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10591

+

10592

+ Revert following patch

10593

+ 2014-04-08 Pat Haugen <pthaugen@us.ibm.com>

10594

+

10595

+ Backport from mainline

10596

+ 2014-04-08 Pat Haugen <pthaugen@us.ibm.com>

10597

+

10598

+ * config/rs6000/sync.md (AINT mode_iterator): Move definition.

10599

+ (loadsync_<mode>): Change mode.

10600

+ (load_quadpti, store_quadpti): New.

10601

+ (atomic_load<mode>, atomic_store<mode>): Add support for TI mode.

10602

+ * config/rs6000/rs6000.md (unspec enum): Add UNSPEC_LSQ.

10603

+

10604

+2014-04-09 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10605

+

10606

+ Backport from mainline r202642

10607

+ 2013-09-17 Alan Modra <amodra@gmail.com>

10608

+

10609

+ PR target/57589

10610

+ * config/rs6000/driver-rs6000.c (elf_platform): Revert 2013-06-11

10611

+ patch (r199972).

10612

+

10613

+2014-04-08 Pat Haugen <pthaugen@us.ibm.com>

10614

+

10615

+ Backport from mainline

10616

+ 2014-04-08 Pat Haugen <pthaugen@us.ibm.com>

10617

+

10618

+ * config/rs6000/sync.md (AINT mode_iterator): Move definition.

10619

+ (loadsync_<mode>): Change mode.

10620

+ (load_quadpti, store_quadpti): New.

10621

+ (atomic_load<mode>, atomic_store<mode>): Add support for TI mode.

10622

+ * config/rs6000/rs6000.md (unspec enum): Add UNSPEC_LSQ.

10623

+

10624

+2014-04-07 Martin Jambor <mjambor@suse.cz>

10625

+

10626

+ PR ipa/60640

10627

+ * ipa-cp.c (propagate_constants_accross_call): Do not propagate

10628

+ accross thunks.

10629

+

10630

+2014-04-07 Dominique d'Humieres <dominiq@lps.ens.fr>

10631

+

10632

+ Backport from mainline

10633

+ 2013-09-14 Iain Sandoe <iains@gcc.gnu.org>

10634

+

10635

+ PR target/48094

10636

+ * config/darwin.c (darwin_objc2_section): Note if ObjC Metadata

10637

+ is seen.

10638

+ (darwin_objc1_section): Likewise.

10639

+ (darwin_file_end): Emit Image Info section when required.

10640

+

10641

+2014-04-05 Alan Modra <amodra@gmail.com>

10642

+

10643

+ Apply from mainline

10644

+ 2014-01-28 Alan Modra <amodra@gmail.com>

10645

+ * Makefile.in (BUILD_CPPFLAGS): Do not use ALL_CPPFLAGS.

10646

+ * configure.ac <recursive call for build != host>: Define

10647

+ GENERATOR_FILE. Comment. Use CXX_FOR_BUILD, CXXFLAGS_FOR_BUILD

10648

+ and LD_FOR_BUILD too.

10649

+ * configure: Regenerate.

10650

+

10651

+2014-04-04 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

10652

+

10653

+ Backport from mainline r208895:

10654

+ 2014-03-28 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

10655

+

10656

+ * config/rs6000/rs6000.c (fusion_gpr_load_p): Refuse optimization

10657

+ if it would clobber the stack pointer, even temporarily.

10658

+

10659

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10660

+

10661

+ Back port from main line:

10662

+ 2014-04-01 Michael Meissner <meissner@linux.vnet.ibm.com>

10663

+

10664

+ * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions):

10665

+ Document vec_vgbbd.

10666

+

10667

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10668

+

10669

+ Back port mainline subversion id 209025.

10670

+ 2014-04-02 Michael Meissner <meissner@linux.vnet.ibm.com>

10671

+

10672

+ PR target/60735

10673

+ * config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): If we have

10674

+ software floating point or no floating point registers, do not

10675

+ allow any type in the FPRs. Eliminate a test for SPE SIMD types

10676

+ in GPRs that occurs after we tested for GPRs that would never be

10677

+ true.

10678

+

10679

+ * config/rs6000/rs6000.md (mov<mode>_softfloat32, FMOVE64):

10680

+ Rewrite tests to use TARGET_DOUBLE_FLOAT and TARGET_E500_DOUBLE,

10681

+ since the FMOVE64 type is DFmode/DDmode. If TARGET_E500_DOUBLE,

10682

+ specifically allow DDmode, since that does not use the SPE SIMD

10683

+ instructions.

10684

+

10685

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10686

+

10687

+ Backport from mainline r205308

10688

+ 2013-11-23 David Edelsohn <dje.gcc@gmail.com>

10689

+

10690

+ * config/rs6000/rs6000.c (IN_NAMED_SECTION): New macro.

10691

+ (rs6000_xcoff_select_section): Place decls with stricter alignment

10692

+ into named sections.

10693

+ (rs6000_xcoff_unique_section): Allow unique sections for

10694

+ uninitialized data with strict alignment.

10695

+

10696

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10697

+

10698

+ Backport from mainline

10699

+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

10700

+

10701

+ * gcc/configure: Regenerate.

10702

+

10703

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10704

+

10705

+ Back port from trunk

10706

+ 2013-04-25 Alan Modra <amodra@gmail.com>

10707

+

10708

+ PR target/57052

10709

+ * config/rs6000/rs6000.md (rotlsi3_internal7): Rename to

10710

+ rotlsi3_internal7le and condition on !BYTES_BIG_ENDIAN.

10711

+ (rotlsi3_internal8be): New BYTES_BIG_ENDIAN insn.

10712

+ Repeat for many other rotate/shift and mask patterns using subregs.

10713

+ Name lshiftrt insns.

10714

+ (ashrdisi3_noppc64): Rename to ashrdisi3_noppc64be and condition

10715

+ on WORDS_BIG_ENDIAN.

10716

+

10717

+ 2013-06-07 Alan Modra <amodra@gmail.com>

10718

+

10719

+ * config/rs6000/rs6000.c (rs6000_option_override_internal): Don't

10720

+ override user -mfp-in-toc.

10721

+ (offsettable_ok_by_alignment): Consider just the current access

10722

+ rather than the whole object, unless BLKmode. Handle

10723

+ CONSTANT_POOL_ADDRESS_P constants that lack a decl too.

10724

+ (use_toc_relative_ref): Allow CONSTANT_POOL_ADDRESS_P constants

10725

+ for -mcmodel=medium.

10726

+ * config/rs6000/linux64.h (SUBSUBTARGET_OVERRIDE_OPTIONS): Don't

10727

+ override user -mfp-in-toc or -msum-in-toc. Default to

10728

+ -mno-fp-in-toc for -mcmodel=medium.

10729

+

10730

+ 2013-06-18 Alan Modra <amodra@gmail.com>

10731

+

10732

+ * config/rs6000/rs6000.h (enum data_align): New.

10733

+ (LOCAL_ALIGNMENT, DATA_ALIGNMENT): Use rs6000_data_alignment.

10734

+ (DATA_ABI_ALIGNMENT): Define.

10735

+ (CONSTANT_ALIGNMENT): Correct comment.

10736

+ * config/rs6000/rs6000-protos.h (rs6000_data_alignment): Declare.

10737

+ * config/rs6000/rs6000.c (rs6000_data_alignment): New function.

10738

+

10739

+ 2013-07-11 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

10740

+

10741

+ * config/rs6000/rs6000.md (""*tls_gd_low<TLSmode:tls_abi_suffix>"):

10742

+ Require GOT register as additional operand in UNSPEC.

10743

+ ("*tls_ld_low<TLSmode:tls_abi_suffix>"): Likewise.

10744

+ ("*tls_got_dtprel_low<TLSmode:tls_abi_suffix>"): Likewise.

10745

+ ("*tls_got_tprel_low<TLSmode:tls_abi_suffix>"): Likewise.

10746

+ ("*tls_gd<TLSmode:tls_abi_suffix>"): Update splitter.

10747

+ ("*tls_ld<TLSmode:tls_abi_suffix>"): Likewise.

10748

+ ("tls_got_dtprel_<TLSmode:tls_abi_suffix>"): Likewise.

10749

+ ("tls_got_tprel_<TLSmode:tls_abi_suffix>"): Likewise.

10750

+

10751

+ 2014-01-23 Pat Haugen <pthaugen@us.ibm.com>

10752

+

10753

+ * config/rs6000/rs6000.c (rs6000_option_override_internal): Don't

10754

+ force flag_ira_loop_pressure if set via command line.

10755

+

10756

+ 2014-02-06 Alan Modra <amodra@gmail.com>

10757

+

10758

+ PR target/60032

10759

+ * config/rs6000/rs6000.c (rs6000_secondary_memory_needed_mode): Only

10760

+ change SDmode to DDmode when lra_in_progress.

10761

+

10762

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10763

+

10764

+ V1TImode Support

10765

+ Back port from trunk

10766

+ 2014-03-12 Michael Meissner <meissner@linux.vnet.ibm.com>

10767

+

10768

+ * config/rs6000/vector.md (VEC_L): Add V1TI mode to vector types.

10769

+ (VEC_M): Likewise.

10770

+ (VEC_N): Likewise.

10771

+ (VEC_R): Likewise.

10772

+ (VEC_base): Likewise.

10773

+ (mov<MODE>, VEC_M modes): If we are loading TImode into VSX

10774

+ registers, we need to swap double words in little endian mode.

10775

+

10776

+ * config/rs6000/rs6000-modes.def (V1TImode): Add new vector mode

10777

+ to be a container mode for 128-bit integer operations added in ISA

10778

+ 2.07. Unlike TImode and PTImode, the preferred register set is

10779

+ the Altivec/VMX registers for the 128-bit operations.

10780

+

10781

+ * config/rs6000/rs6000-protos.h (rs6000_move_128bit_ok_p): Add

10782

+ declarations.

10783

+ (rs6000_split_128bit_ok_p): Likewise.

10784

+

10785

+ * config/rs6000/rs6000-builtin.def (BU_P8V_AV_3): Add new support

10786

+ macros for creating ISA 2.07 normal and overloaded builtin

10787

+ functions with 3 arguments.

10788

+ (BU_P8V_OVERLOAD_3): Likewise.

10789

+ (VPERM_1T): Add support for V1TImode in 128-bit vector operations

10790

+ for use as overloaded functions.

10791

+ (VPERM_1TI_UNS): Likewise.

10792

+ (VSEL_1TI): Likewise.

10793

+ (VSEL_1TI_UNS): Likewise.

10794

+ (ST_INTERNAL_1ti): Likewise.

10795

+ (LD_INTERNAL_1ti): Likewise.

10796

+ (XXSEL_1TI): Likewise.

10797

+ (XXSEL_1TI_UNS): Likewise.

10798

+ (VPERM_1TI): Likewise.

10799

+ (VPERM_1TI_UNS): Likewise.

10800

+ (XXPERMDI_1TI): Likewise.

10801

+ (SET_1TI): Likewise.

10802

+ (LXVD2X_V1TI): Likewise.

10803

+ (STXVD2X_V1TI): Likewise.

10804

+ (VEC_INIT_V1TI): Likewise.

10805

+ (VEC_SET_V1TI): Likewise.

10806

+ (VEC_EXT_V1TI): Likewise.

10807

+ (EQV_V1TI): Likewise.

10808

+ (NAND_V1TI): Likewise.

10809

+ (ORC_V1TI): Likewise.

10810

+ (VADDCUQ): Add support for 128-bit integer arithmetic instructions

10811

+ added in ISA 2.07. Add both normal 'altivec' builtins, and the

10812

+ overloaded builtin.

10813

+ (VADDUQM): Likewise.

10814

+ (VSUBCUQ): Likewise.

10815

+ (VADDEUQM): Likewise.

10816

+ (VADDECUQ): Likewise.

10817

+ (VSUBEUQM): Likewise.

10818

+ (VSUBECUQ): Likewise.

10819

+

10820

+ * config/rs6000/rs6000-c.c (__int128_type): New static to hold

10821

+ __int128_t and __uint128_t types.

10822

+ (__uint128_type): Likewise.

10823

+ (altivec_categorize_keyword): Add support for vector __int128_t,

10824

+ vector __uint128_t, vector __int128, and vector unsigned __int128

10825

+ as a container type for TImode operations that need to be done in

10826

+ VSX/Altivec registers.

10827

+ (rs6000_macro_to_expand): Likewise.

10828

+ (altivec_overloaded_builtins): Add ISA 2.07 overloaded functions

10829

+ to support 128-bit integer instructions vaddcuq, vadduqm,

10830

+ vaddecuq, vaddeuqm, vsubcuq, vsubuqm, vsubecuq, vsubeuqm.

10831

+ (altivec_resolve_overloaded_builtin): Add support for V1TImode.

10832

+

10833

+ * config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): Add support

10834

+ for V1TImode, and set up preferences to use VSX/Altivec

10835

+ registers. Setup VSX reload handlers.

10836

+ (rs6000_debug_reg_global): Likewise.

10837

+ (rs6000_init_hard_regno_mode_ok): Likewise.

10838

+ (rs6000_preferred_simd_mode): Likewise.

10839

+ (vspltis_constant): Do not allow V1TImode as easy altivec

10840

+ constants.

10841

+ (easy_altivec_constant): Likewise.

10842

+ (output_vec_const_move): Likewise.

10843

+ (rs6000_expand_vector_set): Convert V1TImode set and extract to

10844

+ simple move.

10845

+ (rs6000_expand_vector_extract): Likewise.

10846

+ (reg_offset_addressing_ok_p): Setup V1TImode to use VSX reg+reg

10847

+ addressing.

10848

+ (rs6000_const_vec): Add support for V1TImode.

10849

+ (rs6000_emit_le_vsx_load): Swap double words when loading or

10850

+ storing TImode/V1TImode.

10851

+ (rs6000_emit_le_vsx_store): Likewise.

10852

+ (rs6000_emit_le_vsx_move): Likewise.

10853

+ (rs6000_emit_move): Add support for V1TImode.

10854

+ (altivec_expand_ld_builtin): Likewise.

10855

+ (altivec_expand_st_builtin): Likewise.

10856

+ (altivec_expand_vec_init_builtin): Likewise.

10857

+ (altivec_expand_builtin): Likewise.

10858

+ (rs6000_init_builtins): Add support for V1TImode type. Add

10859

+ support for ISA 2.07 128-bit integer builtins. Define type names

10860

+ for the VSX/Altivec vector types.

10861

+ (altivec_init_builtins): Add support for overloaded vector

10862

+ functions with V1TImode type.

10863

+ (rs6000_preferred_reload_class): Prefer Altivec registers for

10864

+ V1TImode.

10865

+ (rs6000_move_128bit_ok_p): Move 128-bit move/split validation to

10866

+ external function.

10867

+ (rs6000_split_128bit_ok_p): Likewise.

10868

+ (rs6000_handle_altivec_attribute): Create V1TImode from vector

10869

+ __int128_t and vector __uint128_t.

10870

+

10871

+ * config/rs6000/vsx.md (VSX_L): Add V1TImode to vector iterators

10872

+ and mode attributes.

10873

+ (VSX_M): Likewise.

10874

+ (VSX_M2): Likewise.

10875

+ (VSm): Likewise.

10876

+ (VSs): Likewise.

10877

+ (VSr): Likewise.

10878

+ (VSv): Likewise.

10879

+ (VS_scalar): Likewise.

10880

+ (VS_double): Likewise.

10881

+ (vsx_set_v1ti): New builtin function to create V1TImode from

10882

+ TImode.

10883

+

10884

+ * config/rs6000/rs6000.h (TARGET_VADDUQM): New macro to say

10885

+ whether we support the ISA 2.07 128-bit integer arithmetic

10886

+ instructions.

10887

+ (ALTIVEC_OR_VSX_VECTOR_MODE): Add V1TImode.

10888

+ (enum rs6000_builtin_type_index): Add fields to hold V1TImode

10889

+ and TImode types for use with the builtin functions.

10890

+ (V1TI_type_node): Likewise.

10891

+ (unsigned_V1TI_type_node): Likewise.

10892

+ (intTI_type_internal_node): Likewise.

10893

+ (uintTI_type_internal_node): Likewise.

10894

+

10895

+ * config/rs6000/altivec.md (UNSPEC_VADDCUQ): New unspecs for ISA

10896

+ 2.07 128-bit builtin functions.

10897

+ (UNSPEC_VADDEUQM): Likewise.

10898

+ (UNSPEC_VADDECUQ): Likewise.

10899

+ (UNSPEC_VSUBCUQ): Likewise.

10900

+ (UNSPEC_VSUBEUQM): Likewise.

10901

+ (UNSPEC_VSUBECUQ): Likewise.

10902

+ (VM): Add V1TImode to vector mode iterators.

10903

+ (VM2): Likewise.

10904

+ (VI_unit): Likewise.

10905

+ (altivec_vadduqm): Add ISA 2.07 128-bit binary builtins.

10906

+ (altivec_vaddcuq): Likewise.

10907

+ (altivec_vsubuqm): Likewise.

10908

+ (altivec_vsubcuq): Likewise.

10909

+ (altivec_vaddeuqm): Likewise.

10910

+ (altivec_vaddecuq): Likewise.

10911

+ (altivec_vsubeuqm): Likewise.

10912

+ (altivec_vsubecuq): Likewise.

10913

+

10914

+ * config/rs6000/rs6000.md (FMOVE128_GPR): Add V1TImode to vector

10915

+ mode iterators.

10916

+ (BOOL_128): Likewise.

10917

+ (BOOL_REGS_OUTPUT): Likewise.

10918

+ (BOOL_REGS_OP1): Likewise.

10919

+ (BOOL_REGS_OP2): Likewise.

10920

+ (BOOL_REGS_UNARY): Likewise.

10921

+ (BOOL_REGS_AND_CR0): Likewise.

10922

+

10923

+ * config/rs6000/altivec.h (vec_vaddcuq): Add support for ISA 2.07

10924

+ 128-bit integer builtin support.

10925

+ (vec_vadduqm): Likewise.

10926

+ (vec_vaddecuq): Likewise.

10927

+ (vec_vaddeuqm): Likewise.

10928

+ (vec_vsubecuq): Likewise.

10929

+ (vec_vsubeuqm): Likewise.

10930

+ (vec_vsubcuq): Likewise.

10931

+ (vec_vsubuqm): Likewise.

10932

+

10933

+ * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions):

10934

+ Document vec_vaddcuq, vec_vadduqm, vec_vaddecuq, vec_vaddeuqm,

10935

+ vec_subecuq, vec_subeuqm, vec_vsubcuq, vec_vsubeqm builtins adding

10936

+ 128-bit integer add/subtract to ISA 2.07.

10937

+

10938

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10939

+

10940

+ Apply mainline r207798

10941

+ 2014-02-26 Alan Modra <amodra@gmail.com>

10942

+ PR target/58675

10943

+ PR target/57935

10944

+ * config/rs6000/rs6000.c (rs6000_secondary_reload_inner): Use

10945

+ find_replacement on parts of insn rtl that might be reloaded.

10946

+

10947

+ Backport from mainline r208287

10948

+ 2014-03-03 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10949

+

10950

+ * config/rs6000/rs6000.c (rs6000_preferred_reload_class): Disallow

10951

+ reload of PLUS rtx's outside of GENERAL_REGS or BASE_REGS; relax

10952

+ constraint on constants to permit them being loaded into

10953

+ GENERAL_REGS or BASE_REGS.

10954

+

10955

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10956

+

10957

+ Backport from mainline r207699.

10958

+ 2014-02-11 Michael Meissner <meissner@linux.vnet.ibm.com>

10959

+

10960

+ PR target/60137

10961

+ * config/rs6000/rs6000.md (128-bit GPR splitter): Add a splitter

10962

+ for VSX/Altivec vectors that land in GPR registers.

10963

+

10964

+ Backport from mainline r207808.

10965

+ 2014-02-15 Michael Meissner <meissner@linux.vnet.ibm.com>

10966

+

10967

+ PR target/60203

10968

+ * config/rs6000/rs6000.md (rreg): Add TFmode, TDmode constraints.

10969

+ (mov<mode>_internal, TFmode/TDmode): Split TFmode/TDmode moves

10970

+ into 64-bit and 32-bit moves. On 64-bit moves, add support for

10971

+ using direct move instructions on ISA 2.07. Also adjust

10972

+ instruction length for 64-bit.

10973

+ (mov<mode>_64bit, TFmode/TDmode): Likewise.

10974

+ (mov<mode>_32bit, TFmode/TDmode): Likewise.

10975

+

10976

+ Backport from mainline r207868.

10977

+ 2014-02-18 Michael Meissner <meissner@linux.vnet.ibm.com>

10978

+

10979

+ PR target/60203

10980

+ * config/rs6000/rs6000.md (mov<mode>_64bit, TF/TDmode moves):

10981

+ Split 64-bit moves into 2 patterns. Do not allow the use of

10982

+ direct move for TDmode in little endian, since the decimal value

10983

+ has little endian bytes within a word, but the 64-bit pieces are

10984

+ ordered in a big endian fashion, and normal subreg's of TDmode are

10985

+ not allowed.

10986

+ (mov<mode>_64bit_dm): Likewise.

10987

+ (movtd_64bit_nodm): Likewise.

10988

+

10989

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10990

+

10991

+ Backport from mainline r207658

10992

+ 2014-02-06 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

10993

+

10994

+ * config/rs6000/sysv4.h (ENDIAN_SELECT): Do not attempt to enforce

10995

+ big-endian mode for -mcall-aixdesc, -mcall-freebsd, -mcall-netbsd,

10996

+ -mcall-openbsd, or -mcall-linux.

10997

+ (CC1_ENDIAN_BIG_SPEC): Remove.

10998

+ (CC1_ENDIAN_LITTLE_SPEC): Remove.

10999

+ (CC1_ENDIAN_DEFAULT_SPEC): Remove.

11000

+ (CC1_SPEC): Remove (always empty) %cc1_endian_... spec.

11001

+ (SUBTARGET_EXTRA_SPECS): Remove %cc1_endian_big, %cc1_endian_little,

11002

+ and %cc1_endian_default.

11003

+ * config/rs6000/sysv4le.h (CC1_ENDIAN_DEFAULT_SPEC): Remove.

11004

+

11005

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11006

+

11007

+ Little Endian Vector API Support

11008

+ Backport from mainline r206443

11009

+ 2014-01-08 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11010

+

11011

+ * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Remove

11012

+ two duplicate entries.

11013

+

11014

+ Backport from mainline r206494

11015

+ 2014-01-09 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11016

+

11017

+ * doc/invoke.texi: Add -maltivec={be,le} options, and document

11018

+ default element-order behavior for -maltivec.

11019

+ * config/rs6000/rs6000.opt: Add -maltivec={be,le} options.

11020

+ * config/rs6000/rs6000.c (rs6000_option_override_internal): Ensure

11021

+ that -maltivec={le,be} implies -maltivec; disallow -maltivec=le

11022

+ when targeting big endian, at least for now.

11023

+ * config/rs6000/rs6000.h: Add #define of VECTOR_ELT_ORDER_BIG.

11024

+

11025

+ Backport from mainline r206541

11026

+ 2014-01-10 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11027

+

11028

+ * config/rs6000/rs6000-builtin.def: Fix pasto for VPKSDUS.

11029

+

11030

+ Backport from mainline r206590

11031

+ 2014-01-13 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11032

+

11033

+ * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin):

11034

+ Implement -maltivec=be for vec_insert and vec_extract.

11035

+

11036

+ Backport from mainline r206641

11037

+ 2014-01-15 Bill Schmidt <wschmidt@vnet.linux.ibm.com>

11038

+

11039

+ * config/rs6000/altivec.md (mulv8hi3): Explicitly generate vmulesh

11040

+ and vmulosh rather than call gen_vec_widen_smult_*.

11041

+ (vec_widen_umult_even_v16qi): Test VECTOR_ELT_ORDER_BIG rather

11042

+ than BYTES_BIG_ENDIAN to determine use of even or odd instruction.

11043

+ (vec_widen_smult_even_v16qi): Likewise.

11044

+ (vec_widen_umult_even_v8hi): Likewise.

11045

+ (vec_widen_smult_even_v8hi): Likewise.

11046

+ (vec_widen_umult_odd_v16qi): Likewise.

11047

+ (vec_widen_smult_odd_v16qi): Likewise.

11048

+ (vec_widen_umult_odd_v8hi): Likewise.

11049

+ (vec_widen_smult_odd_v8hi): Likewise.

11050

+ (vec_widen_umult_hi_v16qi): Explicitly generate vmuleub and

11051

+ vmuloub rather than call gen_vec_widen_umult_*.

11052

+ (vec_widen_umult_lo_v16qi): Likewise.

11053

+ (vec_widen_smult_hi_v16qi): Explicitly generate vmulesb and

11054

+ vmulosb rather than call gen_vec_widen_smult_*.

11055

+ (vec_widen_smult_lo_v16qi): Likewise.

11056

+ (vec_widen_umult_hi_v8hi): Explicitly generate vmuleuh and vmulouh

11057

+ rather than call gen_vec_widen_umult_*.

11058

+ (vec_widen_umult_lo_v8hi): Likewise.

11059

+ (vec_widen_smult_hi_v8hi): Explicitly gnerate vmulesh and vmulosh

11060

+ rather than call gen_vec_widen_smult_*.

11061

+ (vec_widen_smult_lo_v8hi): Likewise.

11062

+

11063

+ Backport from mainline r207062

11064

+ 2014-01-24 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11065

+

11066

+ * config/rs6000/rs6000.c (rs6000_expand_vec_perm_const_1): Remove

11067

+ correction for little endian...

11068

+ * config/rs6000/vsx.md (vsx_xxpermdi2_<mode>_1): ...and move it to

11069

+ here.

11070

+

11071

+ Backport from mainline r207262

11072

+ 2014-01-29 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11073

+

11074

+ * config/rs6000/rs6000.c (altivec_expand_vec_perm_const): Use

11075

+ CODE_FOR_altivec_vmrg*_direct rather than CODE_FOR_altivec_vmrg*.

11076

+ * config/rs6000/vsx.md (vsx_mergel_<mode>): Adjust for

11077

+ -maltivec=be with LE targets.

11078

+ (vsx_mergeh_<mode>): Likewise.

11079

+ * config/rs6000/altivec.md (UNSPEC_VMRG[HL]_DIRECT): New

11080

+ unspecs.

11081

+ (mulv8hi3): Use gen_altivec_vmrg[hl]w_direct.

11082

+ (altivec_vmrghb): Replace with define_expand and new

11083

+ *altivec_vmrghb_internal insn; adjust for -maltivec=be with LE

11084

+ targets.

11085

+ (altivec_vmrghb_direct): New define_insn.

11086

+ (altivec_vmrghh): Replace with define_expand and new

11087

+ *altivec_vmrghh_internal insn; adjust for -maltivec=be with LE

11088

+ targets.

11089

+ (altivec_vmrghh_direct): New define_insn.

11090

+ (altivec_vmrghw): Replace with define_expand and new

11091

+ *altivec_vmrghw_internal insn; adjust for -maltivec=be with LE

11092

+ targets.

11093

+ (altivec_vmrghw_direct): New define_insn.

11094

+ (*altivec_vmrghsf): Adjust for endianness.

11095

+ (altivec_vmrglb): Replace with define_expand and new

11096

+ *altivec_vmrglb_internal insn; adjust for -maltivec=be with LE

11097

+ targets.

11098

+ (altivec_vmrglb_direct): New define_insn.

11099

+ (altivec_vmrglh): Replace with define_expand and new

11100

+ *altivec_vmrglh_internal insn; adjust for -maltivec=be with LE

11101

+ targets.

11102

+ (altivec_vmrglh_direct): New define_insn.

11103

+ (altivec_vmrglw): Replace with define_expand and new

11104

+ *altivec_vmrglw_internal insn; adjust for -maltivec=be with LE

11105

+ targets.

11106

+ (altivec_vmrglw_direct): New define_insn.

11107

+ (*altivec_vmrglsf): Adjust for endianness.

11108

+ (vec_widen_umult_hi_v16qi): Use gen_altivec_vmrghh_direct.

11109

+ (vec_widen_umult_lo_v16qi): Use gen_altivec_vmrglh_direct.

11110

+ (vec_widen_smult_hi_v16qi): Use gen_altivec_vmrghh_direct.

11111

+ (vec_widen_smult_lo_v16qi): Use gen_altivec_vmrglh_direct.

11112

+ (vec_widen_umult_hi_v8hi): Use gen_altivec_vmrghw_direct.

11113

+ (vec_widen_umult_lo_v8hi): Use gen_altivec_vmrglw_direct.

11114

+ (vec_widen_smult_hi_v8hi): Use gen_altivec_vmrghw_direct.

11115

+ (vec_widen_smult_lo_v8hi): Use gen_altivec_vmrglw_direct.

11116

+

11117

+ Backport from mainline r207318

11118

+ 2014-01-30 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11119

+

11120

+ * gcc/config/rs6000/rs6000.c (rs6000_expand_vector_init): Use

11121

+ gen_vsx_xxspltw_v4sf_direct instead of gen_vsx_xxspltw_v4sf;

11122

+ remove element index adjustment for endian (now handled in vsx.md

11123

+ and altivec.md).

11124

+ (altivec_expand_vec_perm_const): Use

11125

+ gen_altivec_vsplt[bhw]_direct instead of gen_altivec_vsplt[bhw].

11126

+ * gcc/config/rs6000/vsx.md (UNSPEC_VSX_XXSPLTW): New unspec.

11127

+ (vsx_xxspltw_<mode>): Adjust element index for little endian.

11128

+ * gcc/config/rs6000/altivec.md (altivec_vspltb): Divide into a

11129

+ define_expand and a new define_insn *altivec_vspltb_internal;

11130

+ adjust for -maltivec=be on a little endian target.

11131

+ (altivec_vspltb_direct): New.

11132

+ (altivec_vsplth): Divide into a define_expand and a new

11133

+ define_insn *altivec_vsplth_internal; adjust for -maltivec=be on a

11134

+ little endian target.

11135

+ (altivec_vsplth_direct): New.

11136

+ (altivec_vspltw): Divide into a define_expand and a new

11137

+ define_insn *altivec_vspltw_internal; adjust for -maltivec=be on a

11138

+ little endian target.

11139

+ (altivec_vspltw_direct): New.

11140

+ (altivec_vspltsf): Divide into a define_expand and a new

11141

+ define_insn *altivec_vspltsf_internal; adjust for -maltivec=be on

11142

+ a little endian target.

11143

+

11144

+ Backport from mainline r207326

11145

+ 2014-01-30 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11146

+

11147

+ * config/rs6000/rs6000.c (rs6000_expand_vector_init): Remove

11148

+ unused variable "field".

11149

+ * config/rs6000/vsx.md (vsx_mergel_<mode>): Add missing DONE.

11150

+ (vsx_mergeh_<mode>): Likewise.

11151

+ * config/rs6000/altivec.md (altivec_vmrghb): Likewise.

11152

+ (altivec_vmrghh): Likewise.

11153

+ (altivec_vmrghw): Likewise.

11154

+ (altivec_vmrglb): Likewise.

11155

+ (altivec_vmrglh): Likewise.

11156

+ (altivec_vmrglw): Likewise.

11157

+ (altivec_vspltb): Add missing uses.

11158

+ (altivec_vsplth): Likewise.

11159

+ (altivec_vspltw): Likewise.

11160

+ (altivec_vspltsf): Likewise.

11161

+

11162

+ Backport from mainline r207414

11163

+ 2014-02-02 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11164

+

11165

+ * config/rs6000/altivec.md (UNSPEC_VSUMSWS_DIRECT): New unspec.

11166

+ (altivec_vsumsws): Add handling for -maltivec=be with a little

11167

+ endian target.

11168

+ (altivec_vsumsws_direct): New.

11169

+ (reduc_splus_<mode>): Call gen_altivec_vsumsws_direct instead of

11170

+ gen_altivec_vsumsws.

11171

+

11172

+ Backport from mainline r207415

11173

+ 2014-02-02 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11174

+

11175

+ * config/rs6000/rs6000.c (altivec_expand_vec_perm_le): Generalize

11176

+ for vector types other than V16QImode.

11177

+ * config/rs6000/altivec.md (altivec_vperm_<mode>): Change to a

11178

+ define_expand, and call altivec_expand_vec_perm_le when producing

11179

+ code with little endian element order.

11180

+ (*altivec_vperm_<mode>_internal): New insn having previous

11181

+ behavior of altivec_vperm_<mode>.

11182

+ (altivec_vperm_<mode>_uns): Change to a define_expand, and call

11183

+ altivec_expand_vec_perm_le when producing code with little endian

11184

+ element order.

11185

+ (*altivec_vperm_<mode>_uns_internal): New insn having previous

11186

+ behavior of altivec_vperm_<mode>_uns.

11187

+

11188

+ Backport from mainline r207520

11189

+ 2014-02-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11190

+

11191

+ * altivec.md (UNSPEC_VPACK_UNS_UNS_MOD_DIRECT): New unspec.

11192

+ (UNSPEC_VUNPACK_HI_SIGN_DIRECT): Likewise.

11193

+ (UNSPEC_VUNPACK_LO_SIGN_DIRECT): Likewise.

11194

+ (mulv8hi3): Use gen_altivec_vpkuwum_direct instead of

11195

+ gen_altivec_vpkuwum.

11196

+ (altivec_vpkpx): Test for VECTOR_ELT_ORDER_BIG instead of for

11197

+ BYTES_BIG_ENDIAN.

11198

+ (altivec_vpks<VI_char>ss): Likewise.

11199

+ (altivec_vpks<VI_char>us): Likewise.

11200

+ (altivec_vpku<VI_char>us): Likewise.

11201

+ (altivec_vpku<VI_char>um): Likewise.

11202

+ (altivec_vpku<VI_char>um_direct): New (copy of

11203

+ altivec_vpku<VI_char>um that still relies on BYTES_BIG_ENDIAN, for

11204

+ internal use).

11205

+ (altivec_vupkhs<VU_char>): Emit vupkls* instead of vupkhs* when

11206

+ target is little endian and -maltivec=be is not specified.

11207

+ (*altivec_vupkhs<VU_char>_direct): New (copy of

11208

+ altivec_vupkhs<VU_char> that always emits vupkhs*, for internal

11209

+ use).

11210

+ (altivec_vupkls<VU_char>): Emit vupkhs* instead of vupkls* when

11211

+ target is little endian and -maltivec=be is not specified.

11212

+ (*altivec_vupkls<VU_char>_direct): New (copy of

11213

+ altivec_vupkls<VU_char> that always emits vupkls*, for internal

11214

+ use).

11215

+ (altivec_vupkhpx): Emit vupklpx instead of vupkhpx when target is

11216

+ little endian and -maltivec=be is not specified.

11217

+ (altivec_vupklpx): Emit vupkhpx instead of vupklpx when target is

11218

+ little endian and -maltivec=be is not specified.

11219

+

11220

+ Backport from mainline r207521

11221

+ 2014-02-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11222

+

11223

+ * config/rs6000/altivec.md (altivec_vsum2sws): Adjust code

11224

+ generation for -maltivec=be.

11225

+ (altivec_vsumsws): Simplify redundant test.

11226

+

11227

+ Backport from mainline r207525

11228

+ 2014-02-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11229

+

11230

+ * config/rs6000/rs6000.c (altivec_expand_vec_perm_const): Change

11231

+ CODE_FOR_altivec_vpku[hw]um to

11232

+ CODE_FOR_altivec_vpku[hw]um_direct.

11233

+ * config/rs6000/altivec.md (vec_unpacks_hi_<VP_small_lc>): Change

11234

+ UNSPEC_VUNPACK_HI_SIGN to UNSPEC_VUNPACK_HI_SIGN_DIRECT.

11235

+ (vec_unpacks_lo_<VP_small_lc>): Change UNSPEC_VUNPACK_LO_SIGN to

11236

+ UNSPEC_VUNPACK_LO_SIGN_DIRECT.

11237

+

11238

+ Backport from mainline r207814.

11239

+ 2014-02-16 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11240

+

11241

+ * config/rs6000/vsx.md (vsx_xxpermdi_<mode>): Handle little

11242

+ endian targets.

11243

+

11244

+ Backport from mainline r207815.

11245

+ 2014-02-16 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11246

+

11247

+ * config/rs6000/altivec.md (p8_vmrgew): Handle little endian

11248

+ targets.

11249

+ (p8_vmrgow): Likewise.

11250

+

11251

+ Backport from mainline r207919.

11252

+ 2014-02-19 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11253

+

11254

+ * config/rs6000/rs6000.c (vspltis_constant): Fix most significant

11255

+ bit of zero.

11256

+

11257

+ Backport from mainline 208019

11258

+ 2014-02-21 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11259

+

11260

+ * config/rs6000/altivec.md (altivec_lvxl): Rename as

11261

+ *altivec_lvxl_<mode>_internal and use VM2 iterator instead of

11262

+ V4SI.

11263

+ (altivec_lvxl_<mode>): New define_expand incorporating

11264

+ -maltivec=be semantics where needed.

11265

+ (altivec_lvx): Rename as *altivec_lvx_<mode>_internal.

11266

+ (altivec_lvx_<mode>): New define_expand incorporating -maltivec=be

11267

+ semantics where needed.

11268

+ (altivec_stvx): Rename as *altivec_stvx_<mode>_internal.

11269

+ (altivec_stvx_<mode>): New define_expand incorporating

11270

+ -maltivec=be semantics where needed.

11271

+ (altivec_stvxl): Rename as *altivec_stvxl_<mode>_internal and use

11272

+ VM2 iterator instead of V4SI.

11273

+ (altivec_stvxl_<mode>): New define_expand incorporating

11274

+ -maltivec=be semantics where needed.

11275

+ * config/rs6000/rs6000-builtin.def: Add new built-in definitions

11276

+ LVXL_V2DF, LVXL_V2DI, LVXL_V4SF, LVXL_V4SI, LVXL_V8HI, LVXL_V16QI,

11277

+ LVX_V2DF, LVX_V2DI, LVX_V4SF, LVX_V4SI, LVX_V8HI, LVX_V16QI,

11278

+ STVX_V2DF, STVX_V2DI, STVX_V4SF, STVX_V4SI, STVX_V8HI, STVX_V16QI,

11279

+ STVXL_V2DF, STVXL_V2DI, STVXL_V4SF, STVXL_V4SI, STVXL_V8HI,

11280

+ STVXL_V16QI.

11281

+ * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Replace

11282

+ ALTIVEC_BUILTIN_LVX with ALTIVEC_BUILTIN_LVX_<MODE> throughout;

11283

+ similarly for ALTIVEC_BUILTIN_LVXL, ALTIVEC_BUILTIN_STVX, and

11284

+ ALTIVEC_BUILTIN_STVXL.

11285

+ * config/rs6000/rs6000-protos.h (altivec_expand_lvx_be): New

11286

+ prototype.

11287

+ (altivec_expand_stvx_be): Likewise.

11288

+ * config/rs6000/rs6000.c (swap_selector_for_mode): New function.

11289

+ (altivec_expand_lvx_be): Likewise.

11290

+ (altivec_expand_stvx_be): Likewise.

11291

+ (altivec_expand_builtin): Add cases for

11292

+ ALTIVEC_BUILTIN_STVX_<MODE>, ALTIVEC_BUILTIN_STVXL_<MODE>,

11293

+ ALTIVEC_BUILTIN_LVXL_<MODE>, and ALTIVEC_BUILTIN_LVX_<MODE>.

11294

+ (altivec_init_builtins): Add definitions for

11295

+ __builtin_altivec_lvxl_<mode>, __builtin_altivec_lvx_<mode>,

11296

+ __builtin_altivec_stvx_<mode>, and

11297

+ __builtin_altivec_stvxl_<mode>.

11298

+

11299

+ Backport from mainline 208021

11300

+ 2014-02-21 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11301

+

11302

+ * config/rs6000/altivec.md (altivec_vsumsws): Replace second

11303

+ vspltw with vsldoi.

11304

+ (reduc_uplus_v16qi): Use gen_altivec_vsumsws_direct instead of

11305

+ gen_altivec_vsumsws.

11306

+

11307

+ Backport from mainline 208049

11308

+ 2014-02-23 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11309

+

11310

+ * config/rs6000/altivec.md (altivec_lve<VI_char>x): Replace

11311

+ define_insn with define_expand and new define_insn

11312

+ *altivec_lve<VI_char>x_internal.

11313

+ (altivec_stve<VI_char>x): Replace define_insn with define_expand

11314

+ and new define_insn *altivec_stve<VI_char>x_internal.

11315

+ * config/rs6000/rs6000-protos.h (altivec_expand_stvex_be): New

11316

+ prototype.

11317

+ * config/rs6000/rs6000.c (altivec_expand_lvx_be): Document use by

11318

+ lve*x built-ins.

11319

+ (altivec_expand_stvex_be): New function.

11320

+

11321

+ Backport from mainline

11322

+ 2014-02-23 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11323

+ * config/rs6000/rs6000.c (rs6000_emit_le_vsx_move): Relax assert

11324

+ to permit subregs.

11325

+

11326

+ Backport from mainline

11327

+ 2014-02-25 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11328

+ * config/rs6000/vector.md (*vector_unordered<mode>): Change split

11329

+ to use canonical form for nor<mode>3.

11330

+

11331

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11332

+

11333

+ Backport from mainline

11334

+ 2014-02-04 Michael Meissner <meissner@linux.vnet.ibm.com>

11335

+

11336

+ * config/rs6000/rs6000.opt (-mlra): Add switch to enable the LRA

11337

+ register allocator.

11338

+

11339

+ * config/rs6000/rs6000.c (TARGET_LRA_P): Add support for -mlra to

11340

+ enable the LRA register allocator. Back port the changes from the

11341

+ trunk to enable LRA.

11342

+ (rs6000_legitimate_offset_address_p): Likewise.

11343

+ (legitimate_lo_sum_address_p): Likewise.

11344

+ (use_toc_relative_ref): Likewise.

11345

+ (rs6000_legitimate_address_p): Likewise.

11346

+ (rs6000_emit_move): Likewise.

11347

+ (rs6000_secondary_memory_needed_mode): Likewise.

11348

+ (rs6000_alloc_sdmode_stack_slot): Likewise.

11349

+ (rs6000_lra_p): Likewise.

11350

+

11351

+ * config/rs6000/sync.md (load_lockedti): Copy TI/PTI variables by

11352

+ 64-bit parts to force the register allocator to allocate even/odd

11353

+ register pairs for the quad word atomic instructions.

11354

+ (store_conditionalti): Likewise.

11355

+

11356

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11357

+

11358

+ Back port from mainline

11359

+ 2014-01-23 Michael Meissner <meissner@linux.vnet.ibm.com>

11360

+

11361

+ PR target/59909

11362

+ * doc/invoke.texi (RS/6000 and PowerPC Options): Document

11363

+ -mquad-memory-atomic. Update -mquad-memory documentation to say

11364

+ it is only used for non-atomic loads/stores.

11365

+

11366

+ * config/rs6000/predicates.md (quad_int_reg_operand): Allow either

11367

+ -mquad-memory or -mquad-memory-atomic switches.

11368

+

11369

+ * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Add

11370

+ -mquad-memory-atomic to ISA 2.07 support.

11371

+

11372

+ * config/rs6000/rs6000.opt (-mquad-memory-atomic): Add new switch

11373

+ to separate support of normal quad word memory operations (ldq,

11374

+ stq) from the atomic quad word memory operations.

11375

+

11376

+ * config/rs6000/rs6000.c (rs6000_option_override_internal): Add

11377

+ support to separate non-atomic quad word operations from atomic

11378

+ quad word operations. Disable non-atomic quad word operations in

11379

+ little endian mode so that we don't have to swap words after the

11380

+ load and before the store.

11381

+ (quad_load_store_p): Add comment about atomic quad word support.

11382

+ (rs6000_opt_masks): Add -mquad-memory-atomic to the list of

11383

+ options printed with -mdebug=reg.

11384

+

11385

+ * config/rs6000/rs6000.h (TARGET_SYNC_TI): Use

11386

+ -mquad-memory-atomic as the test for whether we have quad word

11387

+ atomic instructions.

11388

+ (TARGET_SYNC_HI_QI): If either -mquad-memory-atomic,

11389

+ -mquad-memory, or -mp8-vector are used, allow byte/half-word

11390

+ atomic operations.

11391

+

11392

+ * config/rs6000/sync.md (load_lockedti): Insure that the address

11393

+ is a proper indexed or indirect address for the lqarx instruction.

11394

+ On little endian systems, swap the hi/lo registers after the lqarx

11395

+ instruction.

11396

+ (load_lockedpti): Use indexed_or_indirect_operand predicate to

11397

+ insure the address is valid for the lqarx instruction.

11398

+ (store_conditionalti): Insure that the address is a proper indexed

11399

+ or indirect address for the stqcrx. instruction. On little endian

11400

+ systems, swap the hi/lo registers before doing the stqcrx.

11401

+ instruction.

11402

+ (store_conditionalpti): Use indexed_or_indirect_operand predicate to

11403

+ insure the address is valid for the stqcrx. instruction.

11404

+

11405

+ * gcc/config/rs6000/rs6000-c.c (rs6000_target_modify_macros):

11406

+ Define __QUAD_MEMORY__ and __QUAD_MEMORY_ATOMIC__ based on what

11407

+ type of quad memory support is available.

11408

+

11409

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11410

+

11411

+ Apply mainline r202190, powerpc64le multilibs and multiarch dir

11412

+ 2013-09-03 Alan Modra <amodra@gmail.com>

11413

+

11414

+ * config.gcc (powerpc*-*-linux*): Add support for little-endian

11415

+ multilibs to big-endian target and vice versa.

11416

+ * config/rs6000/t-linux64: Use := assignment on all vars.

11417

+ (MULTILIB_EXTRA_OPTS): Remove fPIC.

11418

+ (MULTILIB_OSDIRNAMES): Specify using mapping from multilib_options.

11419

+ * config/rs6000/t-linux64le: New file.

11420

+ * config/rs6000/t-linux64bele: New file.

11421

+ * config/rs6000/t-linux64lebe: New file.

11422

+

11423

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11424

+

11425

+ Back port from mainline

11426

+ 2014-01-16 Michael Meissner <meissner@linux.vnet.ibm.com>

11427

+

11428

+ PR target/59844

11429

+ * config/rs6000/rs6000.md (reload_vsx_from_gprsf): Add little

11430

+ endian support, remove tests for WORDS_BIG_ENDIAN.

11431

+ (p8_mfvsrd_3_<mode>): Likewise.

11432

+ (reload_gpr_from_vsx<mode>): Likewise.

11433

+ (reload_gpr_from_vsxsf): Likewise.

11434

+ (p8_mfvsrd_4_disf): Likewise.

11435

+

11436

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11437

+

11438

+ Backport from mainline

11439

+ 2013-04-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11440

+

11441

+ PR target/56843

11442

+ * config/rs6000/rs6000.c (rs6000_emit_swdiv_high_precision): Remove.

11443

+ (rs6000_emit_swdiv_low_precision): Remove.

11444

+ (rs6000_emit_swdiv): Rewrite to handle between one and four

11445

+ iterations of Newton-Raphson generally; modify required number of

11446

+ iterations for some cases.

11447

+ * config/rs6000/rs6000.h (RS6000_RECIP_HIGH_PRECISION_P): Remove.

11448

+

11449

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11450

+

11451

+ Backport from mainline

11452

+ 2013-08-19 Peter Bergner <bergner@vnet.ibm.com>

11453

+ Jakub Jelinek <jakub@redhat.com>

11454

+

11455

+ * builtins.def (BUILT_IN_FABSD32): New DFP ABS builtin.

11456

+ (BUILT_IN_FABSD64): Likewise.

11457

+ (BUILT_IN_FABSD128): Likewise.

11458

+ * builtins.c (expand_builtin): Add support for

11459

+ new DFP ABS builtins.

11460

+ (fold_builtin_1): Likewise.

11461

+ * config/rs6000/dfp.md

11462

+ (*abstd2_fpr): Handle non-overlapping destination

11463

+ and source operands.

11464

+ (*nabstd2_fpr): Likewise.

11465

+

11466

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11467

+

11468

+ Apply mainline r205060.

11469

+ 2013-11-20 Alan Modra <amodra@gmail.com>

11470

+ * config/rs6000/sysv4.h (CC1_ENDIAN_LITTLE_SPEC): Define as empty.

11471

+ * config/rs6000/rs6000.c (rs6000_option_override_internal): Default

11472

+ to strict alignment on older processors when little-endian.

11473

+ * config/rs6000/linux64.h (PROCESSOR_DEFAULT64): Default to power8

11474

+ for ELFv2.

11475

+

11476

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11477

+

11478

+ POWER ELFv2 ABI Support

11479

+ Backport from mainline r204842:

11480

+

11481

+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

11482

+

11483

+ * doc/invoke.texi (-mabi=elfv1, -mabi=elfv2): Document.

11484

+

11485

+ Backport from mainline r204809:

11486

+

11487

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

11488

+

11489

+ * config/rs6000/sysv4le.h (LINUX64_DEFAULT_ABI_ELFv2): Define.

11490

+

11491

+ Backport from mainline r204808:

11492

+

11493

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

11494

+ Alan Modra <amodra@gmail.com>

11495

+

11496

+ * config/rs6000/rs6000.h (RS6000_SAVE_AREA): Handle ABI_ELFv2.

11497

+ (RS6000_SAVE_TOC): Remove.

11498

+ (RS6000_TOC_SAVE_SLOT): New macro.

11499

+ * config/rs6000/rs6000.c (rs6000_parm_offset): New function.

11500

+ (rs6000_parm_start): Use it.

11501

+ (rs6000_function_arg_advance_1): Likewise.

11502

+ (rs6000_emit_prologue): Use RS6000_TOC_SAVE_SLOT.

11503

+ (rs6000_emit_epilogue): Likewise.

11504

+ (rs6000_call_aix): Likewise.

11505

+ (rs6000_output_function_prologue): Do not save/restore r11

11506

+ around calling _mcount for ABI_ELFv2.

11507

+

11508

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

11509

+ Alan Modra <amodra@gmail.com>

11510

+

11511

+ * config/rs6000/rs6000-protos.h (rs6000_reg_parm_stack_space):

11512

+ Add prototype.

11513

+ * config/rs6000/rs6000.h (RS6000_REG_SAVE): Remove.

11514

+ (REG_PARM_STACK_SPACE): Call rs6000_reg_parm_stack_space.

11515

+ * config/rs6000/rs6000.c (rs6000_parm_needs_stack): New function.

11516

+ (rs6000_function_parms_need_stack): Likewise.

11517

+ (rs6000_reg_parm_stack_space): Likewise.

11518

+ (rs6000_function_arg): Do not replace BLKmode by Pmode when

11519

+ returning a register argument.

11520

+

11521

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

11522

+ Michael Gschwind <mkg@us.ibm.com>

11523

+

11524

+ * config/rs6000/rs6000.h (FP_ARG_MAX_RETURN): New macro.

11525

+ (ALTIVEC_ARG_MAX_RETURN): Likewise.

11526

+ (FUNCTION_VALUE_REGNO_P): Use them.

11527

+ * config/rs6000/rs6000.c (TARGET_RETURN_IN_MSB): Define.

11528

+ (rs6000_return_in_msb): New function.

11529

+ (rs6000_return_in_memory): Handle ELFv2 homogeneous aggregates.

11530

+ Handle aggregates of up to 16 bytes for ELFv2.

11531

+ (rs6000_function_value): Handle ELFv2 homogeneous aggregates.

11532

+

11533

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

11534

+ Michael Gschwind <mkg@us.ibm.com>

11535

+

11536

+ * config/rs6000/rs6000.h (AGGR_ARG_NUM_REG): Define.

11537

+ * config/rs6000/rs6000.c (rs6000_aggregate_candidate): New function.

11538

+ (rs6000_discover_homogeneous_aggregate): Likewise.

11539

+ (rs6000_function_arg_boundary): Handle homogeneous aggregates.

11540

+ (rs6000_function_arg_advance_1): Likewise.

11541

+ (rs6000_function_arg): Likewise.

11542

+ (rs6000_arg_partial_bytes): Likewise.

11543

+ (rs6000_psave_function_arg): Handle BLKmode arguments.

11544

+

11545

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

11546

+ Michael Gschwind <mkg@us.ibm.com>

11547

+

11548

+ * config/rs6000/rs6000.h (AGGR_ARG_NUM_REG): Define.

11549

+ * config/rs6000/rs6000.c (rs6000_aggregate_candidate): New function.

11550

+ (rs6000_discover_homogeneous_aggregate): Likewise.

11551

+ (rs6000_function_arg_boundary): Handle homogeneous aggregates.

11552

+ (rs6000_function_arg_advance_1): Likewise.

11553

+ (rs6000_function_arg): Likewise.

11554

+ (rs6000_arg_partial_bytes): Likewise.

11555

+ (rs6000_psave_function_arg): Handle BLKmode arguments.

11556

+

11557

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

11558

+

11559

+ * config/rs6000/rs6000.c (machine_function): New member

11560

+ r2_setup_needed.

11561

+ (rs6000_emit_prologue): Set r2_setup_needed if necessary.

11562

+ (rs6000_output_mi_thunk): Set r2_setup_needed.

11563

+ (rs6000_output_function_prologue): Output global entry point

11564

+ prologue and local entry point marker if needed for ABI_ELFv2.

11565

+ Output -mprofile-kernel code here.

11566

+ (output_function_profiler): Do not output -mprofile-kernel

11567

+ code here; moved to rs6000_output_function_prologue.

11568

+ (rs6000_file_start): Output ".abiversion 2" for ABI_ELFv2.

11569

+

11570

+ (rs6000_emit_move): Do not handle dot symbols for ABI_ELFv2.

11571

+ (rs6000_output_function_entry): Likewise.

11572

+ (rs6000_assemble_integer): Likewise.

11573

+ (rs6000_elf_encode_section_info): Likewise.

11574

+ (rs6000_elf_declare_function_name): Do not create dot symbols

11575

+ or .opd section for ABI_ELFv2.

11576

+

11577

+ (rs6000_trampoline_size): Update for ABI_ELFv2 trampolines.

11578

+ (rs6000_trampoline_init): Likewise.

11579

+ (rs6000_elf_file_end): Call file_end_indicate_exec_stack

11580

+ for ABI_ELFv2.

11581

+

11582

+ (rs6000_call_aix): Handle ELFv2 indirect calls. Do not check

11583

+ for function descriptors in ABI_ELFv2.

11584

+

11585

+ * config/rs6000/rs6000.md ("*call_indirect_aix<mode>"): Support

11586

+ on ABI_AIX only, not ABI_ELFv2.

11587

+ ("*call_value_indirect_aix<mode>"): Likewise.

11588

+ ("*call_indirect_elfv2<mode>"): New pattern.

11589

+ ("*call_value_indirect_elfv2<mode>"): Likewise.

11590

+

11591

+ * config/rs6000/predicates.md ("symbol_ref_operand"): Do not

11592

+ check for function descriptors in ABI_ELFv2.

11593

+ ("current_file_function_operand"): Likewise.

11594

+

11595

+ * config/rs6000/ppc-asm.h [__powerpc64__ && _CALL_ELF == 2]:

11596

+ (toc): Undefine.

11597

+ (FUNC_NAME): Define ELFv2 variant.

11598

+ (JUMP_TARGET): Likewise.

11599

+ (FUNC_START): Likewise.

11600

+ (HIDDEN_FUNC): Likewise.

11601

+ (FUNC_END): Likeiwse.

11602

+

11603

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

11604

+

11605

+ * config.gcc [powerpc*-*-* | rs6000-*-*]: Support --with-abi=elfv1

11606

+ and --with-abi=elfv2.

11607

+ * config/rs6000/option-defaults.h (OPTION_DEFAULT_SPECS): Add "abi".

11608

+ * config/rs6000/rs6000.opt (mabi=elfv1): New option.

11609

+ (mabi=elfv2): Likewise.

11610

+ * config/rs6000/rs6000-opts.h (enum rs6000_abi): Add ABI_ELFv2.

11611

+ * config/rs6000/linux64.h (DEFAULT_ABI): Do not hard-code to AIX_ABI

11612

+ if !RS6000_BI_ARCH.

11613

+ (ELFv2_ABI_CHECK): New macro.

11614

+ (SUBSUBTARGET_OVERRIDE_OPTIONS): Use it to decide whether to set

11615

+ rs6000_current_abi to ABI_AIX or ABI_ELFv2.

11616

+ (GLIBC_DYNAMIC_LINKER64): Support ELFv2 ld.so version.

11617

+ * config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): Predefine

11618

+ _CALL_ELF and __STRUCT_PARM_ALIGN__ if appropriate.

11619

+

11620

+ * config/rs6000/rs6000.c (rs6000_debug_reg_global): Handle ABI_ELFv2.

11621

+ (debug_stack_info): Likewise.

11622

+ (rs6000_file_start): Treat ABI_ELFv2 the same as ABI_AIX.

11623

+ (rs6000_legitimize_tls_address): Likewise.

11624

+ (rs6000_conditional_register_usage): Likewise.

11625

+ (rs6000_emit_move): Likewise.

11626

+ (init_cumulative_args): Likewise.

11627

+ (rs6000_function_arg_advance_1): Likewise.

11628

+ (rs6000_function_arg): Likewise.

11629

+ (rs6000_arg_partial_bytes): Likewise.

11630

+ (rs6000_output_function_entry): Likewise.

11631

+ (rs6000_assemble_integer): Likewise.

11632

+ (rs6000_savres_strategy): Likewise.

11633

+ (rs6000_stack_info): Likewise.

11634

+ (rs6000_function_ok_for_sibcall): Likewise.

11635

+ (rs6000_emit_load_toc_table): Likewise.

11636

+ (rs6000_savres_routine_name): Likewise.

11637

+ (ptr_regno_for_savres): Likewise.

11638

+ (rs6000_emit_prologue): Likewise.

11639

+ (rs6000_emit_epilogue): Likewise.

11640

+ (rs6000_output_function_epilogue): Likewise.

11641

+ (output_profile_hook): Likewise.

11642

+ (output_function_profiler): Likewise.

11643

+ (rs6000_trampoline_size): Likewise.

11644

+ (rs6000_trampoline_init): Likewise.

11645

+ (rs6000_elf_output_toc_section_asm_op): Likewise.

11646

+ (rs6000_elf_encode_section_info): Likewise.

11647

+ (rs6000_elf_reloc_rw_mask): Likewise.

11648

+ (rs6000_elf_declare_function_name): Likewise.

11649

+ (rs6000_function_arg_boundary): Treat ABI_ELFv2 the same as ABI_AIX,

11650

+ except that rs6000_compat_align_parm is always assumed false.

11651

+ (rs6000_gimplify_va_arg): Likewise.

11652

+ (rs6000_call_aix): Update comment.

11653

+ (rs6000_sibcall_aix): Likewise.

11654

+ * config/rs6000/rs6000.md ("tls_gd_aix<TLSmode:tls_abi_suffix>"):

11655

+ Treat ABI_ELFv2 the same as ABI_AIX.

11656

+ ("*tls_gd_call_aix<TLSmode:tls_abi_suffix>"): Likewise.

11657

+ ("tls_ld_aix<TLSmode:tls_abi_suffix>"): Likewise.

11658

+ ("*tls_ld_call_aix<TLSmode:tls_abi_suffix>"): Likewise.

11659

+ ("load_toc_aix_si"): Likewise.

11660

+ ("load_toc_aix_di"): Likewise.

11661

+ ("call"): Likewise.

11662

+ ("call_value"): Likewise.

11663

+ ("*call_local_aix<mode>"): Likewise.

11664

+ ("*call_value_local_aix<mode>"): Likewise.

11665

+ ("*call_nonlocal_aix<mode>"): Likewise.

11666

+ ("*call_value_nonlocal_aix<mode>"): Likewise.

11667

+ ("*call_indirect_aix<mode>"): Likewise.

11668

+ ("*call_value_indirect_aix<mode>"): Likewise.

11669

+ ("sibcall"): Likewise.

11670

+ ("sibcall_value"): Likewise.

11671

+ ("*sibcall_aix<mode>"): Likewise.

11672

+ ("*sibcall_value_aix<mode>"): Likewise.

11673

+ * config/rs6000/predicates.md ("symbol_ref_operand"): Likewise.

11674

+ ("current_file_function_operand"): Likewise.

11675

+

11676

+ Backport from mainline r204807:

11677

+

11678

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

11679

+

11680

+ * config/rs6000/rs6000.c (rs6000_arg_partial_bytes): Simplify logic

11681

+ by making use of the fact that for vector / floating point arguments

11682

+ passed both in VRs/FPRs and in the fixed parameter area, the partial

11683

+ bytes mechanism is in fact not used.

11684

+

11685

+ Backport from mainline r204806:

11686

+

11687

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

11688

+

11689

+ * config/rs6000/rs6000.c (rs6000_psave_function_arg): New function.

11690

+ (rs6000_finish_function_arg): Likewise.

11691

+ (rs6000_function_arg): Use rs6000_psave_function_arg and

11692

+ rs6000_finish_function_arg to handle both vector and floating

11693

+ point arguments that are also passed in GPRs / the stack.

11694

+

11695

+ Backport from mainline r204805:

11696

+

11697

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

11698

+

11699

+ * config/rs6000/rs6000.c (USE_FP_FOR_ARG_P): Remove TYPE argument.

11700

+ (USE_ALTIVEC_FOR_ARG_P): Likewise.

11701

+ (rs6000_darwin64_record_arg_advance_recurse): Update uses.

11702

+ (rs6000_function_arg_advance_1):Likewise.

11703

+ (rs6000_darwin64_record_arg_recurse): Likewise.

11704

+ (rs6000_function_arg): Likewise.

11705

+ (rs6000_arg_partial_bytes): Likewise.

11706

+

11707

+ Backport from mainline r204804:

11708

+

11709

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

11710

+

11711

+ * config/rs6000/rs6000.c (rs6000_option_override_internal): Replace

11712

+ "DEFAULT_ABI != ABI_AIX" test by testing for ABI_V4 or ABI_DARWIN.

11713

+ (rs6000_savres_strategy): Likewise.

11714

+ (rs6000_return_addr): Likewise.

11715

+ (rs6000_emit_load_toc_table): Replace "DEFAULT_ABI != ABI_AIX" by

11716

+ testing for ABI_V4 (since ABI_DARWIN is impossible here).

11717

+ (rs6000_emit_prologue): Likewise.

11718

+ (legitimate_lo_sum_address_p): Simplify DEFAULT_ABI test.

11719

+ (rs6000_elf_declare_function_name): Remove duplicated test.

11720

+ * config/rs6000/rs6000.md ("load_toc_v4_PIC_1"): Explicitly test

11721

+ for ABI_V4 (instead of "DEFAULT_ABI != ABI_AIX" test).

11722

+ ("load_toc_v4_PIC_1_normal"): Likewise.

11723

+ ("load_toc_v4_PIC_1_476"): Likewise.

11724

+ ("load_toc_v4_PIC_1b"): Likewise.

11725

+ ("load_toc_v4_PIC_1b_normal"): Likewise.

11726

+ ("load_toc_v4_PIC_1b_476"): Likewise.

11727

+ ("load_toc_v4_PIC_2"): Likewise.

11728

+ ("load_toc_v4_PIC_3b"): Likewise.

11729

+ ("load_toc_v4_PIC_3c"): Likewise.

11730

+ * config/rs6000/rs6000.h (RS6000_REG_SAVE): Simplify DEFAULT_ABI test.

11731

+ (RS6000_SAVE_AREA): Likewise.

11732

+ (FP_ARG_MAX_REG): Likewise.

11733

+ (RETURN_ADDRESS_OFFSET): Likewise.

11734

+ * config/rs6000/sysv.h (TARGET_TOC): Test for ABI_V4 instead

11735

+ of ABI_AIX.

11736

+ (SUBTARGET_OVERRIDE_OPTIONS): Likewise.

11737

+ (MINIMAL_TOC_SECTION_ASM_OP): Likewise.

11738

+

11739

+ Backport from mainline r204803:

11740

+

11741

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

11742

+

11743

+ * config/rs6000/rs6000.c (rs6000_call_indirect_aix): Rename to ...

11744

+ (rs6000_call_aix): ... this. Handle both direct and indirect calls.

11745

+ Create call insn directly instead of via various gen_... routines.

11746

+ Mention special registers used by the call in CALL_INSN_FUNCTION_USAGE.

11747

+ (rs6000_sibcall_aix): New function.

11748

+ * config/rs6000/rs6000.md (TOC_SAVE_OFFSET_32BIT): Remove.

11749

+ (TOC_SAVE_OFFSET_64BIT): Likewise.

11750

+ (AIX_FUNC_DESC_TOC_32BIT): Likewise.

11751

+ (AIX_FUNC_DESC_TOC_64BIT): Likewise.

11752

+ (AIX_FUNC_DESC_SC_32BIT): Likewise.

11753

+ (AIX_FUNC_DESC_SC_64BIT): Likewise.

11754

+ ("call" expander): Call rs6000_call_aix.

11755

+ ("call_value" expander): Likewise.

11756

+ ("call_indirect_aix<ptrsize>"): Replace this pattern ...

11757

+ ("call_indirect_aix<ptrsize>_nor11"): ... and this pattern ...

11758

+ ("*call_indirect_aix<mode>"): ... by this insn pattern.

11759

+ ("call_value_indirect_aix<ptrsize>"): Replace this pattern ...

11760

+ ("call_value_indirect_aix<ptrsize>_nor11"): ... and this pattern ...

11761

+ ("*call_value_indirect_aix<mode>"): ... by this insn pattern.

11762

+ ("*call_nonlocal_aix32", "*call_nonlocal_aix64"): Replace by ...

11763

+ ("*call_nonlocal_aix<mode>"): ... this pattern.

11764

+ ("*call_value_nonlocal_aix32", "*call_value_nonlocal_aix64"): Replace

11765

+ ("*call_value_nonlocal_aix<mode>"): ... by this pattern.

11766

+ ("*call_local_aix<mode>"): New insn pattern.

11767

+ ("*call_value_local_aix<mode>"): Likewise.

11768

+ ("sibcall" expander): Call rs6000_sibcall_aix.

11769

+ ("sibcall_value" expander): Likewise. Move earlier in file.

11770

+ ("*sibcall_nonlocal_aix<mode>"): Replace by ...

11771

+ ("*sibcall_aix<mode>"): ... this pattern.

11772

+ ("*sibcall_value_nonlocal_aix<mode>"): Replace by ...

11773

+ ("*sibcall_value_aix<mode>"): ... this pattern.

11774

+ * config/rs6000/rs6000-protos.h (rs6000_call_indirect_aix): Remove.

11775

+ (rs6000_call_aix): Add prototype.

11776

+ (rs6000_sibcall_aix): Likewise.

11777

+

11778

+ Backport from mainline r204799:

11779

+

11780

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

11781

+

11782

+ * config/rs6000/rs6000.c (rs6000_emit_prologue): Do not place a

11783

+ RTX_FRAME_RELATED_P marker on the UNSPEC_MOVESI_FROM_CR insn.

11784

+ Instead, add USEs of all modified call-saved CR fields to the

11785

+ insn storing the result to the stack slot, and provide an

11786

+ appropriate REG_FRAME_RELATED_EXPR for that insn.

11787

+ * config/rs6000/rs6000.md ("*crsave"): New insn pattern.

11788

+ * config/rs6000/predicates.md ("crsave_operation"): New predicate.

11789

+

11790

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11791

+

11792

+ ELFv2 ABI Call Support

11793

+ Backport from mainline r204798:

11794

+

11795

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

11796

+ Alan Modra <amodra@gmail.com>

11797

+

11798

+ * function.c (assign_parms): Use all.reg_parm_stack_space instead

11799

+ of re-evaluating REG_PARM_STACK_SPACE target macro.

11800

+ (locate_and_pad_parm): New parameter REG_PARM_STACK_SPACE. Use it

11801

+ instead of evaluating target macro REG_PARM_STACK_SPACE every time.

11802

+ (assign_parm_find_entry_rtl): Update call.

11803

+ * calls.c (initialize_argument_information): Update call.

11804

+ (emit_library_call_value_1): Likewise.

11805

+ * expr.h (locate_and_pad_parm): Update prototype.

11806

+

11807

+ Backport from mainline r204797:

11808

+

11809

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

11810

+

11811

+ * calls.c (store_unaligned_arguments_into_pseudos): Skip PARALLEL

11812

+ arguments.

11813

+

11814

+ Backport from mainline r197003:

11815

+

11816

+ 2013-03-23 Eric Botcazou <ebotcazou@adacore.com>

11817

+

11818

+ * calls.c (expand_call): Add missing guard to code handling return

11819

+ of non-BLKmode structures in MSB.

11820

+ * function.c (expand_function_end): Likewise.

11821

+

11822

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11823

+

11824

+ Backport from mainline r201750.

11825

+ Note: Default setting of -mcompat-align-parm inverted!

11826

+

11827

+ 2013-08-14 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11828

+

11829

+ PR target/57949

11830

+ * doc/invoke.texi: Add documentation of mcompat-align-parm

11831

+ option.

11832

+ * config/rs6000/rs6000.opt: Add mcompat-align-parm option.

11833

+ * config/rs6000/rs6000.c (rs6000_function_arg_boundary): For AIX

11834

+ and Linux, correct BLKmode alignment when 128-bit alignment is

11835

+ required and compatibility flag is not set.

11836

+ (rs6000_gimplify_va_arg): For AIX and Linux, honor specified

11837

+ alignment for zero-size arguments when compatibility flag is not

11838

+ set.

11839

+

11840

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11841

+

11842

+ Little Endian Vector Support

11843

+ Backport from mainline r205333

11844

+ 2013-11-24 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11845

+

11846

+ * config/rs6000/rs6000.c (rs6000_expand_vec_perm_const_1): Correct

11847

+ for little endian.

11848

+

11849

+ Backport from mainline r205241

11850

+ 2013-11-21 Bill Schmidt <wschmidt@vnet.ibm.com>

11851

+

11852

+ * config/rs6000/vector.md (vec_pack_trunc_v2df): Revert previous

11853

+ little endian change.

11854

+ (vec_pack_sfix_trunc_v2df): Likewise.

11855

+ (vec_pack_ufix_trunc_v2df): Likewise.

11856

+ * config/rs6000/rs6000.c (rs6000_expand_interleave): Correct

11857

+ double checking of endianness.

11858

+

11859

+ Backport from mainline r205146

11860

+ 2013-11-20 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11861

+

11862

+ * config/rs6000/vsx.md (vsx_set_<mode>): Adjust for little endian.

11863

+ (vsx_extract_<mode>): Likewise.

11864

+ (*vsx_extract_<mode>_one_le): New LE variant on

11865

+ *vsx_extract_<mode>_zero.

11866

+ (vsx_extract_v4sf): Adjust for little endian.

11867

+

11868

+ Backport from mainline r205080

11869

+ 2013-11-19 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11870

+

11871

+ * config/rs6000/rs6000.c (altivec_expand_vec_perm_const): Adjust

11872

+ V16QI vector splat case for little endian.

11873

+

11874

+ Backport from mainline r205045:

11875

+

11876

+ 2013-11-19 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

11877

+

11878

+ * config/rs6000/vector.md ("mov<mode>"): Do not call

11879

+ rs6000_emit_le_vsx_move to move into or out of GPRs.

11880

+ * config/rs6000/rs6000.c (rs6000_emit_le_vsx_move): Assert

11881

+ source and destination are not GPR hard regs.

11882

+

11883

+ Backport from mainline r204920

11884

+ 2011-11-17 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11885

+

11886

+ * config/rs6000/rs6000.c (rs6000_frame_related): Add split_reg

11887

+ parameter and use it in REG_FRAME_RELATED_EXPR note.

11888

+ (emit_frame_save): Call rs6000_frame_related with extra NULL_RTX

11889

+ parameter.

11890

+ (rs6000_emit_prologue): Likewise, but for little endian VSX

11891

+ stores, pass the source register of the store instead.

11892

+

11893

+ Backport from mainline r204862

11894

+ 2013-11-15 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11895

+

11896

+ * config/rs6000/altivec.md (UNSPEC_VPERM_X, UNSPEC_VPERM_UNS_X):

11897

+ Remove.

11898

+ (altivec_vperm_<mode>): Revert earlier little endian change.

11899

+ (*altivec_vperm_<mode>_internal): Remove.

11900

+ (altivec_vperm_<mode>_uns): Revert earlier little endian change.

11901

+ (*altivec_vperm_<mode>_uns_internal): Remove.

11902

+ * config/rs6000/vector.md (vec_realign_load_<mode>): Revise

11903

+ commentary.

11904

+

11905

+ Backport from mainline r204441

11906

+ 2013-11-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11907

+

11908

+ * config/rs6000/rs6000.c (rs6000_option_override_internal):

11909

+ Remove restriction against use of VSX instructions when generating

11910

+ code for little endian mode.

11911

+

11912

+ Backport from mainline r204440

11913

+ 2013-11-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11914

+

11915

+ * config/rs6000/altivec.md (mulv4si3): Ensure we generate vmulouh

11916

+ for both big and little endian.

11917

+ (mulv8hi3): Swap input operands for merge high and merge low

11918

+ instructions for little endian.

11919

+

11920

+ Backport from mainline r204439

11921

+ 2013-11-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11922

+

11923

+ * config/rs6000/altivec.md (vec_widen_umult_even_v16qi): Change

11924

+ define_insn to define_expand that uses even patterns for big

11925

+ endian and odd patterns for little endian.

11926

+ (vec_widen_smult_even_v16qi): Likewise.

11927

+ (vec_widen_umult_even_v8hi): Likewise.

11928

+ (vec_widen_smult_even_v8hi): Likewise.

11929

+ (vec_widen_umult_odd_v16qi): Likewise.

11930

+ (vec_widen_smult_odd_v16qi): Likewise.

11931

+ (vec_widen_umult_odd_v8hi): Likewise.

11932

+ (vec_widen_smult_odd_v8hi): Likewise.

11933

+ (altivec_vmuleub): New define_insn.

11934

+ (altivec_vmuloub): Likewise.

11935

+ (altivec_vmulesb): Likewise.

11936

+ (altivec_vmulosb): Likewise.

11937

+ (altivec_vmuleuh): Likewise.

11938

+ (altivec_vmulouh): Likewise.

11939

+ (altivec_vmulesh): Likewise.

11940

+ (altivec_vmulosh): Likewise.

11941

+

11942

+ Backport from mainline r204395

11943

+ 2013-11-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11944

+

11945

+ * config/rs6000/vector.md (vec_pack_sfix_trunc_v2df): Adjust for

11946

+ little endian.

11947

+ (vec_pack_ufix_trunc_v2df): Likewise.

11948

+

11949

+ Backport from mainline r204363

11950

+ 2013-11-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11951

+

11952

+ * config/rs6000/altivec.md (vec_widen_umult_hi_v16qi): Swap

11953

+ arguments to merge instruction for little endian.

11954

+ (vec_widen_umult_lo_v16qi): Likewise.

11955

+ (vec_widen_smult_hi_v16qi): Likewise.

11956

+ (vec_widen_smult_lo_v16qi): Likewise.

11957

+ (vec_widen_umult_hi_v8hi): Likewise.

11958

+ (vec_widen_umult_lo_v8hi): Likewise.

11959

+ (vec_widen_smult_hi_v8hi): Likewise.

11960

+ (vec_widen_smult_lo_v8hi): Likewise.

11961

+

11962

+ Backport from mainline r204350

11963

+ 2013-11-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11964

+

11965

+ * config/rs6000/vsx.md (*vsx_le_perm_store_<mode> for VSX_D):

11966

+ Replace the define_insn_and_split with a define_insn and two

11967

+ define_splits, with the split after reload re-permuting the source

11968

+ register to its original value.

11969

+ (*vsx_le_perm_store_<mode> for VSX_W): Likewise.

11970

+ (*vsx_le_perm_store_v8hi): Likewise.

11971

+ (*vsx_le_perm_store_v16qi): Likewise.

11972

+

11973

+ Backport from mainline r204321

11974

+ 2013-11-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11975

+

11976

+ * config/rs6000/vector.md (vec_pack_trunc_v2df): Adjust for

11977

+ little endian.

11978

+

11979

+ Backport from mainline r204321

11980

+ 2013-11-02 Bill Schmidt <wschmidt@vnet.linux.ibm.com>

11981

+

11982

+ * config/rs6000/rs6000.c (rs6000_expand_vector_set): Adjust for

11983

+ little endian.

11984

+

11985

+ Backport from mainline r203980

11986

+ 2013-10-23 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11987

+

11988

+ * config/rs6000/altivec.md (mulv8hi3): Adjust for little endian.

11989

+

11990

+ Backport from mainline r203930

11991

+ 2013-10-22 Bill Schmidt <wschmidt@vnet.ibm.com>

11992

+

11993

+ * config/rs6000/rs6000.c (altivec_expand_vec_perm_const): Reverse

11994

+ meaning of merge-high and merge-low masks for little endian; avoid

11995

+ use of vector-pack masks for little endian for mismatched modes.

11996

+

11997

+ Backport from mainline r203877

11998

+ 2013-10-20 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11999

+

12000

+ * config/rs6000/altivec.md (vec_unpacku_hi_v16qi): Adjust for

12001

+ little endian.

12002

+ (vec_unpacku_hi_v8hi): Likewise.

12003

+ (vec_unpacku_lo_v16qi): Likewise.

12004

+ (vec_unpacku_lo_v8hi): Likewise.

12005

+

12006

+ Backport from mainline r203863

12007

+ 2013-10-19 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

12008

+

12009

+ * config/rs6000/rs6000.c (vspltis_constant): Make sure we check

12010

+ all elements for both endian flavors.

12011

+

12012

+ Backport from mainline r203714

12013

+ 2013-10-16 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

12014

+

12015

+ * gcc/config/rs6000/vector.md (vec_unpacks_hi_v4sf): Correct for

12016

+ endianness.

12017

+ (vec_unpacks_lo_v4sf): Likewise.

12018

+ (vec_unpacks_float_hi_v4si): Likewise.

12019

+ (vec_unpacks_float_lo_v4si): Likewise.

12020

+ (vec_unpacku_float_hi_v4si): Likewise.

12021

+ (vec_unpacku_float_lo_v4si): Likewise.

12022

+

12023

+ Backport from mainline r203713

12024

+ 2013-10-16 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

12025

+

12026

+ * config/rs6000/vsx.md (vsx_concat_<mode>): Adjust output for LE.

12027

+ (vsx_concat_v2sf): Likewise.

12028

+

12029

+ Backport from mainline r203458

12030

+ 2013-10-11 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

12031

+

12032

+ * config/rs6000/vsx.md (*vsx_le_perm_load_v2di): Generalize to

12033

+ handle vector float as well.

12034

+ (*vsx_le_perm_load_v4si): Likewise.

12035

+ (*vsx_le_perm_store_v2di): Likewise.

12036

+ (*vsx_le_perm_store_v4si): Likewise.

12037

+

12038

+ Backport from mainline r203457

12039

+ 2013-10-11 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

12040

+

12041

+ * config/rs6000/vector.md (vec_realign_load<mode>): Generate vperm

12042

+ directly to circumvent subtract from splat{31} workaround.

12043

+ * config/rs6000/rs6000-protos.h (altivec_expand_vec_perm_le): New

12044

+ prototype.

12045

+ * config/rs6000/rs6000.c (altivec_expand_vec_perm_le): New.

12046

+ * config/rs6000/altivec.md (define_c_enum "unspec"): Add

12047

+ UNSPEC_VPERM_X and UNSPEC_VPERM_UNS_X.

12048

+ (altivec_vperm_<mode>): Convert to define_insn_and_split to

12049

+ separate big and little endian logic.

12050

+ (*altivec_vperm_<mode>_internal): New define_insn.

12051

+ (altivec_vperm_<mode>_uns): Convert to define_insn_and_split to

12052

+ separate big and little endian logic.

12053

+ (*altivec_vperm_<mode>_uns_internal): New define_insn.

12054

+ (vec_permv16qi): Add little endian logic.

12055

+

12056

+ Backport from mainline r203247

12057

+ 2013-10-07 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

12058

+

12059

+ * config/rs6000/rs6000.c (altivec_expand_vec_perm_const_le): New.

12060

+ (altivec_expand_vec_perm_const): Call it.

12061

+

12062

+ Backport from mainline r203246

12063

+ 2013-10-07 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

12064

+

12065

+ * config/rs6000/vector.md (mov<mode>): Emit permuted move

12066

+ sequences for LE VSX loads and stores at expand time.

12067

+ * config/rs6000/rs6000-protos.h (rs6000_emit_le_vsx_move): New

12068

+ prototype.

12069

+ * config/rs6000/rs6000.c (rs6000_const_vec): New.

12070

+ (rs6000_gen_le_vsx_permute): New.

12071

+ (rs6000_gen_le_vsx_load): New.

12072

+ (rs6000_gen_le_vsx_store): New.

12073

+ (rs6000_gen_le_vsx_move): New.

12074

+ * config/rs6000/vsx.md (*vsx_le_perm_load_v2di): New.

12075

+ (*vsx_le_perm_load_v4si): New.

12076

+ (*vsx_le_perm_load_v8hi): New.

12077

+ (*vsx_le_perm_load_v16qi): New.

12078

+ (*vsx_le_perm_store_v2di): New.

12079

+ (*vsx_le_perm_store_v4si): New.

12080

+ (*vsx_le_perm_store_v8hi): New.

12081

+ (*vsx_le_perm_store_v16qi): New.

12082

+ (*vsx_xxpermdi2_le_<mode>): New.

12083

+ (*vsx_xxpermdi4_le_<mode>): New.

12084

+ (*vsx_xxpermdi8_le_V8HI): New.

12085

+ (*vsx_xxpermdi16_le_V16QI): New.

12086

+ (*vsx_lxvd2x2_le_<mode>): New.

12087

+ (*vsx_lxvd2x4_le_<mode>): New.

12088

+ (*vsx_lxvd2x8_le_V8HI): New.

12089

+ (*vsx_lxvd2x16_le_V16QI): New.

12090

+ (*vsx_stxvd2x2_le_<mode>): New.

12091

+ (*vsx_stxvd2x4_le_<mode>): New.

12092

+ (*vsx_stxvd2x8_le_V8HI): New.

12093

+ (*vsx_stxvd2x16_le_V16QI): New.

12094

+

12095

+ Backport from mainline r201235

12096

+ 2013-07-24 Bill Schmidt <wschmidt@linux.ibm.com>

12097

+ Anton Blanchard <anton@au1.ibm.com>

12098

+

12099

+ * config/rs6000/altivec.md (altivec_vpkpx): Handle little endian.

12100

+ (altivec_vpks<VI_char>ss): Likewise.

12101

+ (altivec_vpks<VI_char>us): Likewise.

12102

+ (altivec_vpku<VI_char>us): Likewise.

12103

+ (altivec_vpku<VI_char>um): Likewise.

12104

+

12105

+ Backport from mainline r201208

12106

+ 2013-07-24 Bill Schmidt <wschmidt@vnet.linux.ibm.com>

12107

+ Anton Blanchard <anton@au1.ibm.com>

12108

+

12109

+ * config/rs6000/vector.md (vec_realign_load_<mode>): Reorder input

12110

+ operands to vperm for little endian.

12111

+ * config/rs6000/rs6000.c (rs6000_expand_builtin): Use lvsr instead

12112

+ of lvsl to create the control mask for a vperm for little endian.

12113

+

12114

+ Backport from mainline r201195

12115

+ 2013-07-23 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

12116

+ Anton Blanchard <anton@au1.ibm.com>

12117

+

12118

+ * config/rs6000/rs6000.c (altivec_expand_vec_perm_const): Reverse

12119

+ two operands for little-endian.

12120

+

12121

+ Backport from mainline r201193

12122

+ 2013-07-23 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

12123

+ Anton Blanchard <anton@au1.ibm.com>

12124

+

12125

+ * config/rs6000/rs6000.c (altivec_expand_vec_perm_const): Correct

12126

+ selection of field for vector splat in little endian mode.

12127

+

12128

+ Backport from mainline r201149

12129

+ 2013-07-22 Bill Schmidt <wschmidt@vnet.linux.ibm.com>

12130

+ Anton Blanchard <anton@au1.ibm.com>

12131

+

12132

+ * config/rs6000/rs6000.c (rs6000_expand_vector_init): Fix

12133

+ endianness when selecting field to splat.

12134

+

12135

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

12136

+

12137

+ Backport from mainline r205123:

12138

+

12139

+ 2013-11-20 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

12140

+

12141

+ * config/rs6000/rs6000.c (rs6000_cannot_change_mode_class): Do not

12142

+ allow subregs of TDmode in FPRs of smaller size in little-endian.

12143

+ (rs6000_split_multireg_move): When splitting an access to TDmode

12144

+ in FPRs, do not use simplify_gen_subreg.

12145

+

12146

+ Backport from mainline r204927:

12147

+

12148

+ 2013-11-17 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

12149

+

12150

+ * config/rs6000/rs6000.c (rs6000_emit_move): Use low word of

12151

+ sdmode_stack_slot also in little-endian mode.

12152

+

12153

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

12154

+

12155

+ Power8 HTM Support

12156

+ Backport from mainline

12157

+ 2013-12-03 Peter Bergner <bergner@vnet.ibm.com>

12158

+

12159

+ * config/rs6000/htmintrin.h (_TEXASR_INSTRUCTION_FETCH_CONFLICT): Fix

12160

+ typo in macro name.

12161

+ (_TEXASRU_INSTRUCTION_FETCH_CONFLICT): Likewise.

12162

+

12163

+ Backport from mainline r205233.

12164

+ 2013-11-21 Peter Bergner <bergner@vnet.ibm.com>

12165

+

12166

+ * doc/extend.texi: Document htm builtins.

12167

+

12168

+ Backport from mainline

12169

+ 2013-07-17 Iain Sandoe <iain@codesourcery.com>

12170

+

12171

+ * config/rs6000/darwin.h (REGISTER_NAMES): Add HTM registers.

12172

+

12173

+ Backport from mainline

12174

+ 2013-07-16 Peter Bergner <bergner@vnet.ibm.com>

12175

+

12176

+ * config/rs6000/rs6000.c (rs6000_option_override_internal): Do not

12177

+ enable extra ISA flags with TARGET_HTM.

12178

+

12179

+ 2013-07-16 Jakub Jelinek <jakub@redhat.com>

12180

+ Peter Bergner <bergner@vnet.ibm.com>

12181

+

12182

+ * config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTERS): Mention HTM

12183

+ registers in the comment.

12184

+ (DWARF_FRAME_REGISTERS): Subtract also the 3 HTM registers.

12185

+ (DWARF_REG_TO_UNWIND_COLUMN): Use DWARF_FRAME_REGISTERS

12186

+ rather than FIRST_PSEUDO_REGISTERS.

12187

+

12188

+ * config.gcc (powerpc*-*-*): Install htmintrin.h and htmxlintrin.h.

12189

+ * config/rs6000/t-rs6000 (MD_INCLUDES): Add htm.md.

12190

+ * config/rs6000/rs6000.opt: Add -mhtm option.

12191

+ * config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add OPTION_MASK_HTM.

12192

+ (ISA_2_7_MASKS_SERVER): Add OPTION_MASK_HTM.

12193

+ * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Define

12194

+ __HTM__ if the HTM instructions are available.

12195

+ * config/rs6000/predicates.md (u3bit_cint_operand, u10bit_cint_operand)

12196

+ (htm_spr_reg_operand): New define_predicates.

12197

+ * config/rs6000/rs6000.md (define_attr "type"): Add htm.

12198

+ (TFHAR_REGNO, TFIAR_REGNO, TEXASR_REGNO): New define_constants.

12199

+ Include htm.md.

12200

+ * config/rs6000/rs6000-builtin.def (BU_HTM_0, BU_HTM_1, BU_HTM_2)

12201

+ (BU_HTM_3, BU_HTM_SPR0, BU_HTM_SPR1): Add support macros for defining

12202

+ HTM builtin functions.

12203

+ * config/rs6000/rs6000.c (RS6000_BUILTIN_H): New macro.

12204

+ (rs6000_reg_names, alt_reg_names): Add HTM SPR register names.

12205

+ (rs6000_init_hard_regno_mode_ok): Add support for HTM instructions.

12206

+ (rs6000_builtin_mask_calculate): Likewise.

12207

+ (rs6000_option_override_internal): Likewise.

12208

+ (bdesc_htm): Add new HTM builtin support.

12209

+ (htm_spr_num): New function.

12210

+ (htm_spr_regno): Likewise.

12211

+ (rs6000_htm_spr_icode): Likewise.

12212

+ (htm_expand_builtin): Likewise.

12213

+ (htm_init_builtins): Likewise.

12214

+ (rs6000_expand_builtin): Add support for HTM builtin functions.

12215

+ (rs6000_init_builtins): Likewise.

12216

+ (rs6000_invalid_builtin, rs6000_opt_mask): Add support for -mhtm option.

12217

+ * config/rs6000/rs6000.h (ASM_CPU_SPEC): Add support for -mhtm.

12218

+ (TARGET_HTM, MASK_HTM): Define macros.

12219

+ (FIRST_PSEUDO_REGISTER): Adjust for new HTM SPR registers.

12220

+ (FIXED_REGISTERS): Likewise.

12221

+ (CALL_USED_REGISTERS): Likewise.

12222

+ (CALL_REALLY_USED_REGISTERS): Likewise.

12223

+ (REG_ALLOC_ORDER): Likewise.

12224

+ (enum reg_class): Likewise.

12225

+ (REG_CLASS_NAMES): Likewise.

12226

+ (REG_CLASS_CONTENTS): Likewise.

12227

+ (REGISTER_NAMES): Likewise.

12228

+ (ADDITIONAL_REGISTER_NAMES): Likewise.

12229

+ (RS6000_BTC_SPR, RS6000_BTC_VOID, RS6000_BTC_32BIT, RS6000_BTC_64BIT)

12230

+ (RS6000_BTC_MISC_MASK, RS6000_BTM_HTM): New macros.

12231

+ (RS6000_BTM_COMMON): Add RS6000_BTM_HTM.

12232

+ * config/rs6000/htm.md: New file.

12233

+ * config/rs6000/htmintrin.h: New file.

12234

+ * config/rs6000/htmxlintrin.h: New file.

12235

+

12236

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

12237

+

12238

+ Power8 Base Support

12239

+ Apply mainline

12240

+ 2013-11-23 Alan Modra <amodra@gmail.com>

12241

+ * config/rs6000/vsx.md (fusion peepholes): Disable when !TARGET_VSX.

12242

+

12243

+ Backport from mainline

12244

+ 2013-11-12 Michael Meissner <meissner@linux.vnet.ibm.com>

12245

+

12246

+ PR target/59054

12247

+ * config/rs6000/rs6000.md (movdi_internal32): Eliminate

12248

+ constraints that would allow DImode into the traditional Altivec

12249

+ registers, but cause undesirable code generation when loading 0 as

12250

+ a constant.

12251

+ (movdi_internal64): Likewise.

12252

+ (cmp<mode>_fpr): Do not use %x for CR register output.

12253

+ (extendsfdf2_fpr): Fix constraints when -mallow-upper-df and

12254

+ -mallow-upper-sf debug switches are used.

12255

+

12256

+ Backport from mainline

12257

+ 2013-10-17 Michael Meissner <meissner@linux.vnet.ibm.com>

12258

+

12259

+ * config/rs6000/rs6000.c (enum rs6000_reload_reg_type): Add new

12260

+ fields to the reg_addr array that describes the valid addressing

12261

+ mode for any register, general purpose registers, floating point

12262

+ registers, and Altivec registers.

12263

+ (FIRST_RELOAD_REG_CLASS): Likewise.

12264

+ (LAST_RELOAD_REG_CLASS): Likewise.

12265

+ (struct reload_reg_map_type): Likewise.

12266

+ (reload_reg_map_type): Likewise.

12267

+ (RELOAD_REG_VALID): Likewise.

12268

+ (RELOAD_REG_MULTIPLE): Likewise.

12269

+ (RELOAD_REG_INDEXED): Likewise.

12270

+ (RELOAD_REG_OFFSET): Likewise.

12271

+ (RELOAD_REG_PRE_INCDEC): Likewise.

12272

+ (RELOAD_REG_PRE_MODIFY): Likewise.

12273

+ (reg_addr): Likewise.

12274

+ (mode_supports_pre_incdec_p): New helper functions to say whether

12275

+ a given mode supports PRE_INC, PRE_DEC, and PRE_MODIFY.

12276

+ (mode_supports_pre_modify_p): Likewise.

12277

+ (rs6000_debug_vector_unit): Rearrange the -mdebug=reg output to

12278

+ print the valid address mode bits for each mode.

12279

+ (rs6000_debug_print_mode): Likewise.

12280

+ (rs6000_debug_reg_global): Likewise.

12281

+ (rs6000_setup_reg_addr_masks): New function to set up the address

12282

+ mask bits for each type.

12283

+ (rs6000_init_hard_regno_mode_ok): Use memset to clear arrays.

12284

+ Call rs6000_setup_reg_addr_masks to set up the address mask bits.

12285

+ (rs6000_legitimate_address_p): Use mode_supports_pre_incdec_p and

12286

+ mode_supports_pre_modify_p to determine if PRE_INC, PRE_DEC, and

12287

+ PRE_MODIFY are supported.

12288

+ (rs6000_output_move_128bit): Change to use {src,dest}_vmx_p for altivec

12289

+ registers, instead of {src,dest}_av_p.

12290

+ (rs6000_print_options_internal): Tweak the debug output slightly.

12291

+

12292

+ Backport from mainline

12293

+ 2013-10-03 Michael Meissner <meissner@linux.vnet.ibm.com>

12294

+

12295

+ * config/rs6000/rs6000-builtin.def (XSRDPIM): Use floatdf2,

12296

+ ceildf2, btruncdf2, instead of vsx_* name.

12297

+

12298

+ * config/rs6000/vsx.md (vsx_add<mode>3): Change arithmetic

12299

+ iterators to only do V2DF and V4SF here. Move the DF code to

12300

+ rs6000.md where it is combined with SF mode. Replace <VSv> with

12301

+ just 'v' since only vector operations are handled with these insns

12302

+ after moving the DF support to rs6000.md.

12303

+ (vsx_sub<mode>3): Likewise.

12304

+ (vsx_mul<mode>3): Likewise.

12305

+ (vsx_div<mode>3): Likewise.

12306

+ (vsx_fre<mode>2): Likewise.

12307

+ (vsx_neg<mode>2): Likewise.

12308

+ (vsx_abs<mode>2): Likewise.

12309

+ (vsx_nabs<mode>2): Likewise.

12310

+ (vsx_smax<mode>3): Likewise.

12311

+ (vsx_smin<mode>3): Likewise.

12312

+ (vsx_sqrt<mode>2): Likewise.

12313

+ (vsx_rsqrte<mode>2): Likewise.

12314

+ (vsx_fms<mode>4): Likewise.

12315

+ (vsx_nfma<mode>4): Likewise.

12316

+ (vsx_copysign<mode>3): Likewise.

12317

+ (vsx_btrunc<mode>2): Likewise.

12318

+ (vsx_floor<mode>2): Likewise.

12319

+ (vsx_ceil<mode>2): Likewise.

12320

+ (vsx_smaxsf3): Delete scalar ops that were moved to rs6000.md.

12321

+ (vsx_sminsf3): Likewise.

12322

+ (vsx_fmadf4): Likewise.

12323

+ (vsx_fmsdf4): Likewise.

12324

+ (vsx_nfmadf4): Likewise.

12325

+ (vsx_nfmsdf4): Likewise.

12326

+ (vsx_cmpdf_internal1): Likewise.

12327

+

12328

+ * config/rs6000/rs6000.h (TARGET_SF_SPE): Define macros to make it

12329

+ simpler to select whether a target has SPE or traditional floating

12330

+ point support in iterators.

12331

+ (TARGET_DF_SPE): Likewise.

12332

+ (TARGET_SF_FPR): Likewise.

12333

+ (TARGET_DF_FPR): Likewise.

12334

+ (TARGET_SF_INSN): Macros to say whether floating point support

12335

+ exists for a given operation for expanders.

12336

+ (TARGET_DF_INSN): Likewise.

12337

+

12338

+ * config/rs6000/rs6000.c (Ftrad): New mode attributes to allow

12339

+ combining of SF/DF mode operations, using both traditional and VSX

12340

+ registers.

12341

+ (Fvsx): Likewise.

12342

+ (Ff): Likewise.

12343

+ (Fv): Likewise.

12344

+ (Fs): Likewise.

12345

+ (Ffre): Likewise.

12346

+ (FFRE): Likewise.

12347

+ (abs<mode>2): Combine SF/DF modes using traditional floating point

12348

+ instructions. Add support for using the upper DF registers with

12349

+ VSX support, and SF registers with power8-vector support. Update

12350

+ expanders for operations supported by both the SPE and traditional

12351

+ floating point units.

12352

+ (abs<mode>2_fpr): Likewise.

12353

+ (nabs<mode>2): Likewise.

12354

+ (nabs<mode>2_fpr): Likewise.

12355

+ (neg<mode>2): Likewise.

12356

+ (neg<mode>2_fpr): Likewise.

12357

+ (add<mode>3): Likewise.

12358

+ (add<mode>3_fpr): Likewise.

12359

+ (sub<mode>3): Likewise.

12360

+ (sub<mode>3_fpr): Likewise.

12361

+ (mul<mode>3): Likewise.

12362

+ (mul<mode>3_fpr): Likewise.

12363

+ (div<mode>3): Likewise.

12364

+ (div<mode>3_fpr): Likewise.

12365

+ (sqrt<mode>3): Likewise.

12366

+ (sqrt<mode>3_fpr): Likewise.

12367

+ (fre<Fs>): Likewise.

12368

+ (rsqrt<mode>2): Likewise.

12369

+ (cmp<mode>_fpr): Likewise.

12370

+ (smax<mode>3): Likewise.

12371

+ (smin<mode>3): Likewise.

12372

+ (smax<mode>3_vsx): Likewise.

12373

+ (smin<mode>3_vsx): Likewise.

12374

+ (negsf2): Delete SF operations that are merged with DF.

12375

+ (abssf2): Likewise.

12376

+ (addsf3): Likewise.

12377

+ (subsf3): Likewise.

12378

+ (mulsf3): Likewise.

12379

+ (divsf3): Likewise.

12380

+ (fres): Likewise.

12381

+ (fmasf4_fpr): Likewise.

12382

+ (fmssf4_fpr): Likewise.

12383

+ (nfmasf4_fpr): Likewise.

12384

+ (nfmssf4_fpr): Likewise.

12385

+ (sqrtsf2): Likewise.

12386

+ (rsqrtsf_internal1): Likewise.

12387

+ (smaxsf3): Likewise.

12388

+ (sminsf3): Likewise.

12389

+ (cmpsf_internal1): Likewise.

12390

+ (copysign<mode>3_fcpsgn): Add VSX/power8-vector support.

12391

+ (negdf2): Delete DF operations that are merged with SF.

12392

+ (absdf2): Likewise.

12393

+ (nabsdf2): Likewise.

12394

+ (adddf3): Likewise.

12395

+ (subdf3): Likewise.

12396

+ (muldf3): Likewise.

12397

+ (divdf3): Likewise.

12398

+ (fred): Likewise.

12399

+ (rsqrtdf_internal1): Likewise.

12400

+ (fmadf4_fpr): Likewise.

12401

+ (fmsdf4_fpr): Likewise.

12402

+ (nfmadf4_fpr): Likewise.

12403

+ (nfmsdf4_fpr): Likewise.

12404

+ (sqrtdf2): Likewise.

12405

+ (smaxdf3): Likewise.

12406

+ (smindf3): Likewise.

12407

+ (cmpdf_internal1): Likewise.

12408

+ (lrint<mode>di2): Use TARGET_<MODE>_FPR macro.

12409

+ (btrunc<mode>2): Delete separate expander, and combine with the

12410

+ insn and add VSX instruction support. Use TARGET_<MODE>_FPR.

12411

+ (btrunc<mode>2_fpr): Likewise.

12412

+ (ceil<mode>2): Likewise.

12413

+ (ceil<mode>2_fpr): Likewise.

12414

+ (floor<mode>2): Likewise.

12415

+ (floor<mode>2_fpr): Likewise.

12416

+ (fma<mode>4_fpr): Combine SF and DF fused multiply/add support.

12417

+ Add support for using the upper registers with VSX and

12418

+ power8-vector. Move insns to be closer to the define_expands. On

12419

+ VSX systems, prefer the traditional form of FMA over the VSX

12420

+ version, since the traditional form allows the target not to

12421

+ overlap with the inputs.

12422

+ (fms<mode>4_fpr): Likewise.

12423

+ (nfma<mode>4_fpr): Likewise.

12424

+ (nfms<mode>4_fpr): Likewise.

12425

+

12426

+ Backport from mainline

12427

+ 2013-09-27 Michael Meissner <meissner@linux.vnet.ibm.com>

12428

+

12429

+ * config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): Allow

12430

+ DFmode, DImode, and SFmode in the upper VSX registers based on the

12431

+ -mupper-regs-{df,sf} flags. Fix wu constraint to be ALTIVEC_REGS

12432

+ if -mpower8-vector. Combine -mvsx-timode handling with the rest

12433

+ of the VSX register handling.

12434

+

12435

+ * config/rs6000/rs6000.md (f32_lv): Use %x0 for VSX regsters.

12436

+ (f32_sv): Likewise.

12437

+ (zero_extendsidi2_lfiwzx): Add support for loading into the

12438

+ Altivec registers with -mpower8-vector. Use wu/wv constraints to

12439

+ only do VSX memory options on Altivec registers.

12440

+ (extendsidi2_lfiwax): Likewise.

12441

+ (extendsfdf2_fpr): Likewise.

12442

+ (mov<mode>_hardfloat, SF/SD modes): Likewise.

12443

+ (mov<mode>_hardfloat32, DF/DD modes): Likewise.

12444

+ (mov<mode>_hardfloat64, DF/DD modes): Likewise.

12445

+ (movdi_internal64): Likewise.

12446

+

12447

+ Backport from mainline

12448

+ 2013-09-23 Michael Meissner <meissner@linux.vnet.ibm.com>

12449

+

12450

+ * config/rs6000/rs6000.c (rs6000_vector_reload): Delete, combine

12451

+ reload helper function arrays into a single array reg_addr.

12452

+ (reload_fpr_gpr): Likewise.

12453

+ (reload_gpr_vsx): Likewise.

12454

+ (reload_vsx_gpr): Likewise.

12455

+ (struct rs6000_reg_addr): Likewise.

12456

+ (reg_addr): Likewise.

12457

+ (rs6000_debug_reg_global): Change rs6000_vector_reload,

12458

+ reload_fpr_gpr, reload_gpr_vsx, reload_vsx_gpr uses to reg_addr.

12459

+ (rs6000_init_hard_regno_mode_ok): Likewise.

12460

+ (rs6000_secondary_reload_direct_move): Likewise.

12461

+ (rs6000_secondary_reload): Likewise.

12462

+

12463

+ * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Add new

12464

+ constraints: wu, ww, and wy. Repurpose wv constraint added during

12465

+ power8 changes. Put wg constraint in alphabetical order.

12466

+

12467

+ * config/rs6000/rs6000.opt (-mvsx-scalar-float): New debug switch

12468

+ for future work to add ISA 2.07 VSX single precision support.

12469

+ (-mvsx-scalar-double): Change default from -1 to 1, update

12470

+ documentation comment.

12471

+ (-mvsx-scalar-memory): Rename debug switch to -mupper-regs-df.

12472

+ (-mupper-regs-df): New debug switch to control whether DF values

12473

+ can go in the traditional Altivec registers.

12474

+ (-mupper-regs-sf): New debug switch to control whether SF values

12475

+ can go in the traditional Altivec registers.

12476

+

12477

+ * config/rs6000/rs6000.c (rs6000_debug_reg_global): Print wu, ww,

12478

+ and wy constraints.

12479

+ (rs6000_init_hard_regno_mode_ok): Use ssize_t instead of int for

12480

+ loop variables. Rename -mvsx-scalar-memory to -mupper-regs-df.

12481

+ Add new constraints, wu/ww/wy. Repurpose wv constraint.

12482

+ (rs6000_debug_legitimate_address_p): Print if we are running

12483

+ before, during, or after reload.

12484

+ (rs6000_secondary_reload): Add a comment.

12485

+ (rs6000_opt_masks): Add -mupper-regs-df, -mupper-regs-sf.

12486

+

12487

+ * config/rs6000/constraints.md (wa constraint): Sort w<x>

12488

+ constraints. Update documentation string.

12489

+ (wd constraint): Likewise.

12490

+ (wf constraint): Likewise.

12491

+ (wg constraint): Likewise.

12492

+ (wn constraint): Likewise.

12493

+ (ws constraint): Likewise.

12494

+ (wt constraint): Likewise.

12495

+ (wx constraint): Likewise.

12496

+ (wz constraint): Likewise.

12497

+ (wu constraint): New constraint for ISA 2.07 SFmode scalar

12498

+ instructions.

12499

+ (ww constraint): Likewise.

12500

+ (wy constraint): Likewise.

12501

+ (wv constraint): Repurpose ISA 2.07 constraint that did not use in

12502

+ the previous submissions.

12503

+ * doc/md.texi (PowerPC and IBM RS6000): Likewise.

12504

+

12505

+ Backport from mainline

12506

+ 2013-10-17 Michael Meissner <meissner@linux.vnet.ibm.com>

12507

+

12508

+ PR target/58673

12509

+ * config/rs6000/rs6000.c (rs6000_legitimate_address_p): Only

12510

+ restrict TImode addresses to single indirect registers if both

12511

+ -mquad-memory and -mvsx-timode are used.

12512

+ (rs6000_output_move_128bit): Use quad_load_store_p to determine if

12513

+ we should emit load/store quad. Remove using %y for quad memory

12514

+ addresses.

12515

+

12516

+ * config/rs6000/rs6000.md (mov<mode>_ppc64, TI/PTImode): Add

12517

+ constraints to allow load/store quad on machines where TImode is

12518

+ not allowed in VSX registers. Use 'n' instead of 'F' constraint

12519

+ for TImode to load integer constants.

12520

+

12521

+ Backport from mainline

12522

+ 2013-10-02 Michael Meissner <meissner@linux.vnet.ibm.com>

12523

+

12524

+ PR target/58587

12525

+ * config/rs6000/rs6000-cpus.def (ISA_2_6_MASKS_SERVER): Turn off

12526

+ setting -mvsx-timode by default until the underlying problem is

12527

+ fixed.

12528

+ (RS6000_CPU, power7 defaults): Likewise.

12529

+

12530

+ Backport from trunk

12531

+ 2013-08-16 Michael Meissner <meissner@linux.vnet.ibm.com>

12532

+

12533

+ PR target/58160

12534

+ * config/rs6000/predicates.md (fusion_gpr_mem_load): Allow the

12535

+ memory rtx to contain ZERO_EXTEND and SIGN_EXTEND.

12536

+

12537

+ * config/rs6000/rs6000-protos.h (fusion_gpr_load_p): Pass operands

12538

+ array instead of each individual operand as a separate argument.

12539

+ (emit_fusion_gpr_load): Likewise.

12540

+ (expand_fusion_gpr_load): Add new function declaration.

12541

+

12542

+ * config/rs6000/rs6000.c (fusion_gpr_load_p): Change the calling

12543

+ signature to have the operands passed as an array, instead of as

12544

+ separate arguments. Allow ZERO_EXTEND to be in the memory

12545

+ address, and also SIGN_EXTEND if -mpower8-fusion-sign. Do not

12546

+ depend on the register live/dead flags when peepholes are run.

12547

+ (expand_fusion_gpr_load): New function to be called from the

12548

+ peephole2 pass, to change the register that addis sets to be the

12549

+ target register.

12550

+ (emit_fusion_gpr_load): Change the calling signature to have the

12551

+ operands passed as an array, instead of as separate arguments.

12552

+ Allow ZERO_EXTEND to be in the memory address, and also

12553

+ SIGN_EXTEND if -mpower8-fusion-sign.

12554

+

12555

+ * config/rs6000/rs6000.md (UNSPEC_FUSION_GPR): Delete unused

12556

+ unspec enumeration.

12557

+ (power8 fusion peephole/peephole2): Rework the fusion peepholes to

12558

+ adjust the register addis loads up in the peephole2 pass. Do not

12559

+ depend on the register live/dead state when the peephole pass is

12560

+ done.

12561

+

12562

+ Backport from trunk

12563

+ 2013-07-23 Michael Meissner <meissner@linux.vnet.ibm.com>

12564

+

12565

+ * config/rs6000/vector.md (xor<mode>3): Move 128-bit boolean

12566

+ expanders to rs6000.md.

12567

+ (ior<mode>3): Likewise.

12568

+ (and<mode>3): Likewise.

12569

+ (one_cmpl<mode>2): Likewise.

12570

+ (nor<mode>3): Likewise.

12571

+ (andc<mode>3): Likewise.

12572

+ (eqv<mode>3): Likewise.

12573

+ (nand<mode>3): Likewise.

12574

+ (orc<mode>3): Likewise.

12575

+

12576

+ * config/rs6000/rs6000-protos.h (rs6000_split_logical): New

12577

+ declaration.

12578

+

12579

+ * config/rs6000/rs6000.c (rs6000_split_logical_inner): Add support

12580

+ to split multi-word logical operations.

12581

+ (rs6000_split_logical_di): Likewise.

12582

+ (rs6000_split_logical): Likewise.

12583

+

12584

+ * config/rs6000/vsx.md (VSX_L2): Delete, no longer used.

12585

+ (vsx_and<mode>3_32bit): Move 128-bit logical insns to rs6000.md,

12586

+ and allow TImode operations in 32-bit.

12587

+ (vsx_and<mode>3_64bit): Likewise.

12588

+ (vsx_ior<mode>3_32bit): Likewise.

12589

+ (vsx_ior<mode>3_64bit): Likewise.

12590

+ (vsx_xor<mode>3_32bit): Likewise.

12591

+ (vsx_xor<mode>3_64bit): Likewise.

12592

+ (vsx_one_cmpl<mode>2_32bit): Likewise.

12593

+ (vsx_one_cmpl<mode>2_64bit): Likewise.

12594

+ (vsx_nor<mode>3_32bit): Likewise.

12595

+ (vsx_nor<mode>3_64bit): Likewise.

12596

+ (vsx_andc<mode>3_32bit): Likewise.

12597

+ (vsx_andc<mode>3_64bit): Likewise.

12598

+ (vsx_eqv<mode>3_32bit): Likewise.

12599

+ (vsx_eqv<mode>3_64bit): Likewise.

12600

+ (vsx_nand<mode>3_32bit): Likewise.

12601

+ (vsx_nand<mode>3_64bit): Likewise.

12602

+ (vsx_orc<mode>3_32bit): Likewise.

12603

+ (vsx_orc<mode>3_64bit): Likewise.

12604

+

12605

+ * config/rs6000/rs6000.h (VLOGICAL_REGNO_P): Always allow vector

12606

+ logical types in GPRs.

12607

+

12608

+ * config/rs6000/altivec.md (altivec_and<mode>3): Move 128-bit

12609

+ logical insns to rs6000.md, and allow TImode operations in

12610

+ 32-bit.

12611

+ (altivec_ior<mode>3): Likewise.

12612

+ (altivec_xor<mode>3): Likewise.

12613

+ (altivec_one_cmpl<mode>2): Likewise.

12614

+ (altivec_nor<mode>3): Likewise.

12615

+ (altivec_andc<mode>3): Likewise.

12616

+

12617

+ * config/rs6000/rs6000.md (BOOL_128): New mode iterators and mode

12618

+ attributes for moving the 128-bit logical operations into

12619

+ rs6000.md.

12620

+ (BOOL_REGS_OUTPUT): Likewise.

12621

+ (BOOL_REGS_OP1): Likewise.

12622

+ (BOOL_REGS_OP2): Likewise.

12623

+ (BOOL_REGS_UNARY): Likewise.

12624

+ (BOOL_REGS_AND_CR0): Likewise.

12625

+ (one_cmpl<mode>2): Add support for DI logical operations on

12626

+ 32-bit, splitting the operations to 32-bit.

12627

+ (anddi3): Likewise.

12628

+ (iordi3): Likewise.

12629

+ (xordi3): Likewise.

12630

+ (and<mode>3, 128-bit types): Rewrite 2013-06-06 logical operator

12631

+ changes to combine the 32/64-bit code, allow logical operations on

12632

+ TI mode in 32-bit, and to use similar match_operator patterns like

12633

+ scalar mode uses. Combine the Altivec and VSX code for logical

12634

+ operations, and move it here.

12635

+ (ior<mode>3, 128-bit types): Likewise.

12636

+ (xor<mode>3, 128-bit types): Likewise.

12637

+ (one_cmpl<mode>3, 128-bit types): Likewise.

12638

+ (nor<mode>3, 128-bit types): Likewise.

12639

+ (andc<mode>3, 128-bit types): Likewise.

12640

+ (eqv<mode>3, 128-bit types): Likewise.

12641

+ (nand<mode>3, 128-bit types): Likewise.

12642

+ (orc<mode>3, 128-bit types): Likewise.

12643

+ (and<mode>3_internal): Likewise.

12644

+ (bool<mode>3_internal): Likewise.

12645

+ (boolc<mode>3_internal1): Likewise.

12646

+ (boolc<mode>3_internal2): Likewise.

12647

+ (boolcc<mode>3_internal1): Likewise.

12648

+ (boolcc<mode>3_internal2): Likewise.

12649

+ (eqv<mode>3_internal1): Likewise.

12650

+ (eqv<mode>3_internal2): Likewise.

12651

+ (one_cmpl1<mode>3_internal): Likewise.

12652

+

12653

+ Back port from mainline:

12654

+ 2013-06-06 Michael Meissner <meissner@linux.vnet.ibm.com>

12655

+ Pat Haugen <pthaugen@us.ibm.com>

12656

+ Peter Bergner <bergner@vnet.ibm.com>

12657

+

12658

+ * lib/target-supports.exp (check_p8vector_hw_available) Add power8

12659

+ support.

12660

+ (check_effective_target_powerpc_p8vector_ok): Likewise.

12661

+ (is-effective-target): Likewise.

12662

+ (check_vect_support_and_set_flags): Likewise.

12663

+

12664

+ Backport from mainline

12665

+ 2013-07-31 Michael Meissner <meissner@linux.vnet.ibm.com>

12666

+

12667

+ * config/rs6000/predicates.md (fusion_gpr_addis): New predicates

12668

+ to support power8 load fusion.

12669

+ (fusion_gpr_mem_load): Likewise.

12670

+

12671

+ * config/rs6000/rs6000-modes.def (PTImode): Update a comment.

12672

+

12673

+ * config/rs6000/rs6000-protos.h (fusion_gpr_load_p): New

12674

+ declarations for power8 load fusion.

12675

+ (emit_fusion_gpr_load): Likewise.

12676

+

12677

+ * config/rs6000/rs6000.c (rs6000_option_override_internal): If

12678

+ tuning for power8, turn on fusion mode by default. Turn on sign

12679

+ extending fusion mode if normal fusion mode is on, and we are at

12680

+ -O2 or -O3.

12681

+ (fusion_gpr_load_p): New function, return true if we can fuse an

12682

+ addis instruction with a dependent load to a GPR.

12683

+ (emit_fusion_gpr_load): Emit the instructions for power8 load

12684

+ fusion to GPRs.

12685

+

12686

+ * config/rs6000/vsx.md (VSX_M2): New iterator for fusion

12687

+ peepholes.

12688

+ (VSX load fusion peepholes): New peepholes to fuse together an

12689

+ addi instruction with a VSX load instruction.

12690

+

12691

+ * config/rs6000/rs6000.md (GPR load fusion peepholes): New

12692

+ peepholes to fuse an addis instruction with a load to a GPR base

12693

+ register. If we are supporting sign extending fusions, convert

12694

+ sign extending loads to zero extending loads and add an explicit

12695

+ sign extension.

12696

+

12697

+ Backport from mainline

12698

+ 2013-07-18 Pat Haugen <pthaugen@us.ibm.com>

12699

+

12700

+ * config/rs6000/rs6000.c (rs6000_option_override_internal): Adjust flag

12701

+ interaction for new Power8 flags and VSX.

12702

+

12703

+ Back port from the trunk

12704

+ 2013-06-28 Michael Meissner <meissner@linux.vnet.ibm.com>

12705

+

12706

+ PR target/57744

12707

+ * config/rs6000/rs6000.h (MODES_TIEABLE_P): Do not allow PTImode

12708

+ to tie with any other modes. Eliminate Altivec vector mode tests,

12709

+ since these are a subset of ALTIVEC or VSX vector modes. Simplify

12710

+ code, to return 0 if testing MODE2 for a condition, if we've

12711

+ already tested MODE1 for the same condition.

12712

+

12713

+ Backport from mainline

12714

+ 2013-06-28 Pat Haugen <pthaugen@us.ibm.com>

12715

+

12716

+ * config/rs6000/rs6000.md (define_insn ""): Fix insn type.

12717

+

12718

+ Back port from the trunk

12719

+ 2013-06-26 Michael Meissner <meissner@linux.vnet.ibm.com>

12720

+ Pat Haugen <pthaugen@us.ibm.com>

12721

+ Peter Bergner <bergner@vnet.ibm.com>

12722

+

12723

+ * config/rs6000/power8.md: New.

12724

+ * config/rs6000/rs6000-cpus.def (RS6000_CPU table): Adjust processor

12725

+ setting for power8 entry.

12726

+ * config/rs6000/t-rs6000 (MD_INCLUDES): Add power8.md.

12727

+ * config/rs6000/rs6000.c (is_microcoded_insn, is_cracked_insn): Adjust

12728

+ test for Power4/Power5 only.

12729

+ (insn_must_be_first_in_group, insn_must_be_last_in_group): Add Power8

12730

+ support.

12731

+ (force_new_group): Adjust comment.

12732

+ * config/rs6000/rs6000.md: Include power8.md.

12733

+

12734

+ Back port from the trunk

12735

+ 2013-06-14 Michael Meissner <meissner@linux.vnet.ibm.com>

12736

+

12737

+ PR target/57615

12738

+ * config/rs6000/rs6000.md (mov<mode>_ppc64): Call

12739

+ rs6000_output_move_128bit to handle emitting quad memory

12740

+ operations. Set attribute length to 8 bytes.

12741

+

12742

+ Back port from the trunk

12743

+ 2013-06-13 Michael Meissner <meissner@linux.vnet.ibm.com>

12744

+

12745

+ * config/rs6000/rs6000.c (rs6000_option_override_internal): Move

12746

+ test for clearing quad memory on 32-bit later.

12747

+

12748

+ Back port from the trunk

12749

+

12750

+ 2013-06-12 Michael Meissner <meissner@linux.vnet.ibm.com>

12751

+ Pat Haugen <pthaugen@us.ibm.com>

12752

+ Peter Bergner <bergner@vnet.ibm.com>

12753

+

12754

+ * config/rs6000/rs6000.c (emit_load_locked): Add support for

12755

+ power8 byte, half-word, and quad-word atomic instructions.

12756

+ (emit_store_conditional): Likewise.

12757

+ (rs6000_expand_atomic_compare_and_swap): Likewise.

12758

+ (rs6000_expand_atomic_op): Likewise.

12759

+

12760

+ * config/rs6000/sync.md (larx): Add new modes for power8.

12761

+ (stcx): Likewise.

12762

+ (AINT): New mode iterator to include TImode as well as normal

12763

+ integer modes on power8.

12764

+ (fetchop_pred): Use int_reg_operand instead of gpc_reg_operand so

12765

+ that VSX registers are not considered. Use AINT mode iterator

12766

+ instead of INT1 to allow inclusion of quad word atomic operations

12767

+ on power8.

12768

+ (load_locked<mode>): Likewise.

12769

+ (store_conditional<mode>): Likewise.

12770

+ (atomic_compare_and_swap<mode>): Likewise.

12771

+ (atomic_exchange<mode>): Likewise.

12772

+ (atomic_nand<mode>): Likewise.

12773

+ (atomic_fetch_<fetchop_name><mode>): Likewise.

12774

+ (atomic_nand_fetch<mode>): Likewise.

12775

+ (mem_thread_fence): Use gen_loadsync_<mode> instead of enumerating

12776

+ each type.

12777

+ (ATOMIC): On power8, add QImode, HImode modes.

12778

+ (load_locked<QHI:mode>_si): Varients of load_locked for QI/HI

12779

+ modes that promote to SImode.

12780

+ (load_lockedti): Convert TImode arguments to PTImode, so that we

12781

+ get a guaranteed even/odd register pair.

12782

+ (load_lockedpti): Likewise.

12783

+ (store_conditionalti): Likewise.

12784

+ (store_conditionalpti): Likewise.

12785

+

12786

+ * config/rs6000/rs6000.md (QHI): New mode iterator for power8

12787

+ atomic load/store instructions.

12788

+ (HSI): Likewise.

12789

+

12790

+ Back port from the trunk

12791

+

12792

+ 2013-06-10 Michael Meissner <meissner@linux.vnet.ibm.com>

12793

+ Pat Haugen <pthaugen@us.ibm.com>

12794

+ Peter Bergner <bergner@vnet.ibm.com>

12795

+

12796

+ * config/rs6000/vector.md (GPR move splitter): Do not split moves

12797

+ of vectors in GPRS if they are direct moves or quad word load or

12798

+ store moves.

12799

+

12800

+ * config/rs6000/rs6000-protos.h (rs6000_output_move_128bit): Add

12801

+ declaration.

12802

+ (direct_move_p): Likewise.

12803

+ (quad_load_store_p): Likewise.

12804

+

12805

+ * config/rs6000/rs6000.c (enum rs6000_reg_type): Simplify register

12806

+ classes into bins based on the physical register type.

12807

+ (reg_class_to_reg_type): Likewise.

12808

+ (IS_STD_REG_TYPE): Likewise.

12809

+ (IS_FP_VECT_REG_TYPE): Likewise.

12810

+ (reload_fpr_gpr): Arrays to determine what insn to use if we can

12811

+ use direct move instructions.

12812

+ (reload_gpr_vsx): Likewise.

12813

+ (reload_vsx_gpr): Likewise.

12814

+ (rs6000_init_hard_regno_mode_ok): Precalculate the register type

12815

+ information that is a simplification of register classes. Also

12816

+ precalculate direct move reload helpers.

12817

+ (direct_move_p): New function to return true if the operation can

12818

+ be done as a direct move instruciton.

12819

+ (quad_load_store_p): New function to return true if the operation

12820

+ is a quad memory operation.

12821

+ (rs6000_legitimize_address): If quad memory, only allow register

12822

+ indirect for TImode addresses.

12823

+ (rs6000_legitimate_address_p): Likewise.

12824

+ (enum reload_reg_type): Delete, replace with rs6000_reg_type.

12825

+ (rs6000_reload_register_type): Likewise.

12826

+ (register_to_reg_type): Return register type.

12827

+ (rs6000_secondary_reload_simple_move): New helper function for

12828

+ secondary reload and secondary memory needed to identify anything

12829

+ that is a simple move, and does not need reloading.

12830

+ (rs6000_secondary_reload_direct_move): New helper function for

12831

+ secondary reload to identify cases that can be done with several

12832

+ instructions via the direct move instructions.

12833

+ (rs6000_secondary_reload_move): New helper function for secondary

12834

+ reload to identify moves between register types that can be done.

12835

+ (rs6000_secondary_reload): Add support for quad memory operations

12836

+ and for direct move.

12837

+ (rs6000_secondary_memory_needed): Likewise.

12838

+ (rs6000_debug_secondary_memory_needed): Change argument names.

12839

+ (rs6000_output_move_128bit): New function to return the move to

12840

+ use for 128-bit moves, including knowing about the various

12841

+ limitations of quad memory operations.

12842

+

12843

+ * config/rs6000/vsx.md (vsx_mov<mode>): Add support for quad

12844

+ memory operations. call rs6000_output_move_128bit for the actual

12845

+ instruciton(s) to generate.

12846

+ (vsx_movti_64bit): Likewise.

12847

+

12848

+ * config/rs6000/rs6000.md (UNSPEC_P8V_FMRGOW): New unspec values.

12849

+ (UNSPEC_P8V_MTVSRWZ): Likewise.

12850

+ (UNSPEC_P8V_RELOAD_FROM_GPR): Likewise.

12851

+ (UNSPEC_P8V_MTVSRD): Likewise.

12852

+ (UNSPEC_P8V_XXPERMDI): Likewise.

12853

+ (UNSPEC_P8V_RELOAD_FROM_VSX): Likewise.

12854

+ (UNSPEC_FUSION_GPR): Likewise.

12855

+ (FMOVE128_GPR): New iterator for direct move.

12856

+ (f32_lv): New mode attribute for load/store of SFmode/SDmode

12857

+ values.

12858

+ (f32_sv): Likewise.

12859

+ (f32_dm): Likewise.

12860

+ (zero_extend<mode>di2_internal1): Add support for power8 32-bit

12861

+ loads and direct move instructions.

12862

+ (zero_extendsidi2_lfiwzx): Likewise.

12863

+ (extendsidi2_lfiwax): Likewise.

12864

+ (extendsidi2_nocell): Likewise.

12865

+ (floatsi<mode>2_lfiwax): Likewise.

12866

+ (lfiwax): Likewise.

12867

+ (floatunssi<mode>2_lfiwzx): Likewise.

12868

+ (lfiwzx): Likewise.

12869

+ (fix_trunc<mode>_stfiwx): Likewise.

12870

+ (fixuns_trunc<mode>_stfiwx): Likewise.

12871

+ (mov<mode>_hardfloat, 32-bit floating point): Likewise.

12872

+ (mov<move>_hardfloat64, 64-bit floating point): Likewise.

12873

+ (parity<mode>2_cmpb): Set length/type attr.

12874

+ (unnamed shift right patterns, mov<mode>_internal2): Change type attr

12875

+ for 'mr.' to fast_compare.

12876

+ (bpermd_<mode>): Change type attr to popcnt.

12877

+ (p8_fmrgow_<mode>): New insns for power8 direct move support.

12878

+ (p8_mtvsrwz_1): Likewise.

12879

+ (p8_mtvsrwz_2): Likewise.

12880

+ (reload_fpr_from_gpr<mode>): Likewise.

12881

+ (p8_mtvsrd_1): Likewise.

12882

+ (p8_mtvsrd_2): Likewise.

12883

+ (p8_xxpermdi_<mode>): Likewise.

12884

+ (reload_vsx_from_gpr<mode>): Likewise.

12885

+ (reload_vsx_from_gprsf): Likewise.

12886

+ (p8_mfvsrd_3_<mode>): LIkewise.

12887

+ (reload_gpr_from_vsx<mode>): Likewise.

12888

+ (reload_gpr_from_vsxsf): Likewise.

12889

+ (p8_mfvsrd_4_disf): Likewise.

12890

+ (multi-word GPR splits): Do not split direct moves or quad memory

12891

+ operations.

12892

+

12893

+ Backport from the trunk

12894

+

12895

+ 2013-06-06 Michael Meissner <meissner@linux.vnet.ibm.com>

12896

+ Pat Haugen <pthaugen@us.ibm.com>

12897

+ Peter Bergner <bergner@vnet.ibm.com>

12898

+

12899

+ * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions):

12900

+ Document new power8 builtins.

12901

+

12902

+ * config/rs6000/vector.md (and<mode>3): Add a clobber/scratch of a

12903

+ condition code register, to allow 128-bit logical operations to be

12904

+ done in the VSX or GPR registers.

12905

+ (nor<mode>3): Use the canonical form for nor.

12906

+ (eqv<mode>3): Add expanders for power8 xxleqv, xxlnand, xxlorc,

12907

+ vclz*, and vpopcnt* vector instructions.

12908

+ (nand<mode>3): Likewise.

12909

+ (orc<mode>3): Likewise.

12910

+ (clz<mode>2): LIkewise.

12911

+ (popcount<mode>2): Likewise.

12912

+

12913

+ * config/rs6000/predicates.md (int_reg_operand): Rework tests so

12914

+ that only the GPRs are recognized.

12915

+

12916

+ * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add

12917

+ support for new power8 builtins.

12918

+

12919

+ * config/rs6000/rs6000-builtin.def (xscvspdpn): Add new power8

12920

+ builtin functions.

12921

+ (xscvdpspn): Likewise.

12922

+ (vclz): Likewise.

12923

+ (vclzb): Likewise.

12924

+ (vclzh): Likewise.

12925

+ (vclzw): Likewise.

12926

+ (vclzd): Likewise.

12927

+ (vpopcnt): Likewise.

12928

+ (vpopcntb): Likewise.

12929

+ (vpopcnth): Likewise.

12930

+ (vpopcntw): Likewise.

12931

+ (vpopcntd): Likewise.

12932

+ (vgbbd): Likewise.

12933

+ (vmrgew): Likewise.

12934

+ (vmrgow): Likewise.

12935

+ (eqv): Likewise.

12936

+ (eqv_v16qi3): Likewise.

12937

+ (eqv_v8hi3): Likewise.

12938

+ (eqv_v4si3): Likewise.

12939

+ (eqv_v2di3): Likewise.

12940

+ (eqv_v4sf3): Likewise.

12941

+ (eqv_v2df3): Likewise.

12942

+ (nand): Likewise.

12943

+ (nand_v16qi3): Likewise.

12944

+ (nand_v8hi3): Likewise.

12945

+ (nand_v4si3): Likewise.

12946

+ (nand_v2di3): Likewise.

12947

+ (nand_v4sf3): Likewise.

12948

+ (nand_v2df3): Likewise.

12949

+ (orc): Likewise.

12950

+ (orc_v16qi3): Likewise.

12951

+ (orc_v8hi3): Likewise.

12952

+ (orc_v4si3): Likewise.

12953

+ (orc_v2di3): Likewise.

12954

+ (orc_v4sf3): Likewise.

12955

+ (orc_v2df3): Likewise.

12956

+

12957

+ * config/rs6000/rs6000.c (rs6000_option_override_internal): Only

12958

+ allow power8 quad mode in 64-bit.

12959

+ (rs6000_builtin_vectorized_function): Add support to vectorize

12960

+ ISA 2.07 count leading zeros, population count builtins.

12961

+ (rs6000_expand_vector_init): On ISA 2.07 use xscvdpspn to form

12962

+ V4SF vectors instead of xscvdpsp to avoid IEEE related traps.

12963

+ (builtin_function_type): Add vgbbd builtin function which takes an

12964

+ unsigned argument.

12965

+ (altivec_expand_vec_perm_const): Add support for new power8 merge

12966

+ instructions.

12967

+

12968

+ * config/rs6000/vsx.md (VSX_L2): New iterator for 128-bit types,

12969

+ that does not include TImdoe for use with 32-bit.

12970

+ (UNSPEC_VSX_CVSPDPN): Support for power8 xscvdpspn and xscvspdpn

12971

+ instructions.

12972

+ (UNSPEC_VSX_CVDPSPN): Likewise.

12973

+ (vsx_xscvdpspn): Likewise.

12974

+ (vsx_xscvspdpn): Likewise.

12975

+ (vsx_xscvdpspn_scalar): Likewise.

12976

+ (vsx_xscvspdpn_directmove): Likewise.

12977

+ (vsx_and<mode>3): Split logical operations into 32-bit and

12978

+ 64-bit. Add support to do logical operations on TImode as well as

12979

+ VSX vector types. Allow logical operations to be done in either

12980

+ VSX registers or in general purpose registers in 64-bit mode. Add

12981

+ splitters if GPRs were used. For AND, add clobber of CCmode to

12982

+ allow use of ANDI on GPRs. Rewrite nor to use the canonical RTL

12983

+ encoding.

12984

+ (vsx_and<mode>3_32bit): Likewise.

12985

+ (vsx_and<mode>3_64bit): Likewise.

12986

+ (vsx_ior<mode>3): Likewise.

12987

+ (vsx_ior<mode>3_32bit): Likewise.

12988

+ (vsx_ior<mode>3_64bit): Likewise.

12989

+ (vsx_xor<mode>3): Likewise.

12990

+ (vsx_xor<mode>3_32bit): Likewise.

12991

+ (vsx_xor<mode>3_64bit): Likewise.

12992

+ (vsx_one_cmpl<mode>2): Likewise.

12993

+ (vsx_one_cmpl<mode>2_32bit): Likewise.

12994

+ (vsx_one_cmpl<mode>2_64bit): Likewise.

12995

+ (vsx_nor<mode>3): Likewise.

12996

+ (vsx_nor<mode>3_32bit): Likewise.

12997

+ (vsx_nor<mode>3_64bit): Likewise.

12998

+ (vsx_andc<mode>3): Likewise.

12999

+ (vsx_andc<mode>3_32bit): Likewise.

13000

+ (vsx_andc<mode>3_64bit): Likewise.

13001

+ (vsx_eqv<mode>3_32bit): Add support for power8 xxleqv, xxlnand,

13002

+ and xxlorc instructions.

13003

+ (vsx_eqv<mode>3_64bit): Likewise.

13004

+ (vsx_nand<mode>3_32bit): Likewise.

13005

+ (vsx_nand<mode>3_64bit): Likewise.

13006

+ (vsx_orc<mode>3_32bit): Likewise.

13007

+ (vsx_orc<mode>3_64bit): Likewise.

13008

+

13009

+ * config/rs6000/rs6000.h (VLOGICAL_REGNO_P): Update comment.

13010

+

13011

+ * config/rs6000/altivec.md (UNSPEC_VGBBD): Add power8 vgbbd

13012

+ instruction.

13013

+ (p8_vmrgew): Add power8 vmrgew and vmrgow instructions.

13014

+ (p8_vmrgow): Likewise.

13015

+ (altivec_and<mode>3): Add clobber of CCmode to allow AND using

13016

+ GPRs to be split under VSX.

13017

+ (p8v_clz<mode>2): Add power8 count leading zero support.

13018

+ (p8v_popcount<mode>2): Add power8 population count support.

13019

+ (p8v_vgbbd): Add power8 gather bits by bytes by doubleword

13020

+ support.

13021

+

13022

+ * config/rs6000/rs6000.md (eqv<mode>3): Add support for powerp eqv

13023

+ instruction.

13024

+

13025

+ * config/rs6000/altivec.h (vec_eqv): Add defines to export power8

13026

+ builtin functions.

13027

+ (vec_nand): Likewise.

13028

+ (vec_vclz): Likewise.

13029

+ (vec_vclzb): Likewise.

13030

+ (vec_vclzd): Likewise.

13031

+ (vec_vclzh): Likewise.

13032

+ (vec_vclzw): Likewise.

13033

+ (vec_vgbbd): Likewise.

13034

+ (vec_vmrgew): Likewise.

13035

+ (vec_vmrgow): Likewise.

13036

+ (vec_vpopcnt): Likewise.

13037

+ (vec_vpopcntb): Likewise.

13038

+ (vec_vpopcntd): Likewise.

13039

+ (vec_vpopcnth): Likewise.

13040

+ (vec_vpopcntw): Likewise.

13041

+

13042

+ Backport from trunk

13043

+

13044

+ 2013-05-29 Michael Meissner <meissner@linux.vnet.ibm.com>

13045

+ Pat Haugen <pthaugen@us.ibm.com>

13046

+ Peter Bergner <bergner@vnet.ibm.com>

13047

+

13048

+ * config/rs6000/vector.md (VEC_I): Add support for new power8 V2DI

13049

+ instructions.

13050

+ (VEC_A): Likewise.

13051

+ (VEC_C): Likewise.

13052

+ (vrotl<mode>3): Likewise.

13053

+ (vashl<mode>3): Likewise.

13054

+ (vlshr<mode>3): Likewise.

13055

+ (vashr<mode>3): Likewise.

13056

+

13057

+ * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add

13058

+ support for power8 V2DI builtins.

13059

+

13060

+ * config/rs6000/rs6000-builtin.def (abs_v2di): Add support for

13061

+ power8 V2DI builtins.

13062

+ (vupkhsw): Likewise.

13063

+ (vupklsw): Likewise.

13064

+ (vaddudm): Likewise.

13065

+ (vminsd): Likewise.

13066

+ (vmaxsd): Likewise.

13067

+ (vminud): Likewise.

13068

+ (vmaxud): Likewise.

13069

+ (vpkudum): Likewise.

13070

+ (vpksdss): Likewise.

13071

+ (vpkudus): Likewise.

13072

+ (vpksdus): Likewise.

13073

+ (vrld): Likewise.

13074

+ (vsld): Likewise.

13075

+ (vsrd): Likewise.

13076

+ (vsrad): Likewise.

13077

+ (vsubudm): Likewise.

13078

+ (vcmpequd): Likewise.

13079

+ (vcmpgtsd): Likewise.

13080

+ (vcmpgtud): Likewise.

13081

+ (vcmpequd_p): Likewise.

13082

+ (vcmpgtsd_p): Likewise.

13083

+ (vcmpgtud_p): Likewise.

13084

+ (vupkhsw): Likewise.

13085

+ (vupklsw): Likewise.

13086

+ (vaddudm): Likewise.

13087

+ (vmaxsd): Likewise.

13088

+ (vmaxud): Likewise.

13089

+ (vminsd): Likewise.

13090

+ (vminud): Likewise.

13091

+ (vpksdss): Likewise.

13092

+ (vpksdus): Likewise.

13093

+ (vpkudum): Likewise.

13094

+ (vpkudus): Likewise.

13095

+ (vrld): Likewise.

13096

+ (vsld): Likewise.

13097

+ (vsrad): Likewise.

13098

+ (vsrd): Likewise.

13099

+ (vsubudm): Likewise.

13100

+

13101

+ * config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Add

13102

+ support for power8 V2DI instructions.

13103

+

13104

+ * config/rs6000/altivec.md (UNSPEC_VPKUHUM): Add support for

13105

+ power8 V2DI instructions. Combine pack and unpack insns to use an

13106

+ iterator for each mode. Check whether a particular mode supports

13107

+ Altivec instructions instead of just checking TARGET_ALTIVEC.

13108

+ (UNSPEC_VPKUWUM): Likewise.

13109

+ (UNSPEC_VPKSHSS): Likewise.

13110

+ (UNSPEC_VPKSWSS): Likewise.

13111

+ (UNSPEC_VPKUHUS): Likewise.

13112

+ (UNSPEC_VPKSHUS): Likewise.

13113

+ (UNSPEC_VPKUWUS): Likewise.

13114

+ (UNSPEC_VPKSWUS): Likewise.

13115

+ (UNSPEC_VPACK_SIGN_SIGN_SAT): Likewise.

13116

+ (UNSPEC_VPACK_SIGN_UNS_SAT): Likewise.

13117

+ (UNSPEC_VPACK_UNS_UNS_SAT): Likewise.

13118

+ (UNSPEC_VPACK_UNS_UNS_MOD): Likewise.

13119

+ (UNSPEC_VUPKHSB): Likewise.

13120

+ (UNSPEC_VUNPACK_HI_SIGN): Likewise.

13121

+ (UNSPEC_VUNPACK_LO_SIGN): Likewise.

13122

+ (UNSPEC_VUPKHSH): Likewise.

13123

+ (UNSPEC_VUPKLSB): Likewise.

13124

+ (UNSPEC_VUPKLSH): Likewise.

13125

+ (VI2): Likewise.

13126

+ (VI_char): Likewise.

13127

+ (VI_scalar): Likewise.

13128

+ (VI_unit): Likewise.

13129

+ (VP): Likewise.

13130

+ (VP_small): Likewise.

13131

+ (VP_small_lc): Likewise.

13132

+ (VU_char): Likewise.

13133

+ (add<mode>3): Likewise.

13134

+ (altivec_vaddcuw): Likewise.

13135

+ (altivec_vaddu<VI_char>s): Likewise.

13136

+ (altivec_vadds<VI_char>s): Likewise.

13137

+ (sub<mode>3): Likewise.

13138

+ (altivec_vsubcuw): Likewise.

13139

+ (altivec_vsubu<VI_char>s): Likewise.

13140

+ (altivec_vsubs<VI_char>s): Likewise.

13141

+ (altivec_vavgs<VI_char>): Likewise.

13142

+ (altivec_vcmpbfp): Likewise.

13143

+ (altivec_eq<mode>): Likewise.

13144

+ (altivec_gt<mode>): Likewise.

13145

+ (altivec_gtu<mode>): Likewise.

13146

+ (umax<mode>3): Likewise.

13147

+ (smax<mode>3): Likewise.

13148

+ (umin<mode>3): Likewise.

13149

+ (smin<mode>3): Likewise.

13150

+ (altivec_vpkuhum): Likewise.

13151

+ (altivec_vpkuwum): Likewise.

13152

+ (altivec_vpkshss): Likewise.

13153

+ (altivec_vpkswss): Likewise.

13154

+ (altivec_vpkuhus): Likewise.

13155

+ (altivec_vpkshus): Likewise.

13156

+ (altivec_vpkuwus): Likewise.

13157

+ (altivec_vpkswus): Likewise.

13158

+ (altivec_vpks<VI_char>ss): Likewise.

13159

+ (altivec_vpks<VI_char>us): Likewise.

13160

+ (altivec_vpku<VI_char>us): Likewise.

13161

+ (altivec_vpku<VI_char>um): Likewise.

13162

+ (altivec_vrl<VI_char>): Likewise.

13163

+ (altivec_vsl<VI_char>): Likewise.

13164

+ (altivec_vsr<VI_char>): Likewise.

13165

+ (altivec_vsra<VI_char>): Likewise.

13166

+ (altivec_vsldoi_<mode>): Likewise.

13167

+ (altivec_vupkhsb): Likewise.

13168

+ (altivec_vupkhs<VU_char>): Likewise.

13169

+ (altivec_vupkls<VU_char>): Likewise.

13170

+ (altivec_vupkhsh): Likewise.

13171

+ (altivec_vupklsb): Likewise.

13172

+ (altivec_vupklsh): Likewise.

13173

+ (altivec_vcmpequ<VI_char>_p): Likewise.

13174

+ (altivec_vcmpgts<VI_char>_p): Likewise.

13175

+ (altivec_vcmpgtu<VI_char>_p): Likewise.

13176

+ (abs<mode>2): Likewise.

13177

+ (vec_unpacks_hi_v16qi): Likewise.

13178

+ (vec_unpacks_hi_v8hi): Likewise.

13179

+ (vec_unpacks_lo_v16qi): Likewise.

13180

+ (vec_unpacks_hi_<VP_small_lc>): Likewise.

13181

+ (vec_unpacks_lo_v8hi): Likewise.

13182

+ (vec_unpacks_lo_<VP_small_lc>): Likewise.

13183

+ (vec_pack_trunc_v8h): Likewise.

13184

+ (vec_pack_trunc_v4si): Likewise.

13185

+ (vec_pack_trunc_<mode>): Likewise.

13186

+

13187

+ * config/rs6000/altivec.h (vec_vaddudm): Add defines for power8

13188

+ V2DI builtins.

13189

+ (vec_vmaxsd): Likewise.

13190

+ (vec_vmaxud): Likewise.

13191

+ (vec_vminsd): Likewise.

13192

+ (vec_vminud): Likewise.

13193

+ (vec_vpksdss): Likewise.

13194

+ (vec_vpksdus): Likewise.

13195

+ (vec_vpkudum): Likewise.

13196

+ (vec_vpkudus): Likewise.

13197

+ (vec_vrld): Likewise.

13198

+ (vec_vsld): Likewise.

13199

+ (vec_vsrad): Likewise.

13200

+ (vec_vsrd): Likewise.

13201

+ (vec_vsubudm): Likewise.

13202

+ (vec_vupkhsw): Likewise.

13203

+ (vec_vupklsw): Likewise.

13204

+

13205

+ 2013-05-22 Michael Meissner <meissner@linux.vnet.ibm.com>

13206

+ Pat Haugen <pthaugen@us.ibm.com>

13207

+ Peter Bergner <bergner@vnet.ibm.com>

13208

+

13209

+ * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions): Add

13210

+ documentation for the power8 crypto builtins.

13211

+

13212

+ * config/rs6000/t-rs6000 (MD_INCLUDES): Add crypto.md.

13213

+

13214

+ * config/rs6000/rs6000-builtin.def (BU_P8V_AV_1): Add support

13215

+ macros for defining power8 builtin functions.

13216

+ (BU_P8V_AV_2): Likewise.

13217

+ (BU_P8V_AV_P): Likewise.

13218

+ (BU_P8V_VSX_1): Likewise.

13219

+ (BU_P8V_OVERLOAD_1): Likewise.

13220

+ (BU_P8V_OVERLOAD_2): Likewise.

13221

+ (BU_CRYPTO_1): Likewise.

13222

+ (BU_CRYPTO_2): Likewise.

13223

+ (BU_CRYPTO_3): Likewise.

13224

+ (BU_CRYPTO_OVERLOAD_1): Likewise.

13225

+ (BU_CRYPTO_OVERLOAD_2): Likewise.

13226

+ (XSCVSPDP): Fix typo, point to the correct instruction.

13227

+ (VCIPHER): Add power8 crypto builtins.

13228

+ (VCIPHERLAST): Likewise.

13229

+ (VNCIPHER): Likewise.

13230

+ (VNCIPHERLAST): Likewise.

13231

+ (VPMSUMB): Likewise.

13232

+ (VPMSUMH): Likewise.

13233

+ (VPMSUMW): Likewise.

13234

+ (VPERMXOR_V2DI): Likewise.

13235

+ (VPERMXOR_V4SI: Likewise.

13236

+ (VPERMXOR_V8HI: Likewise.

13237

+ (VPERMXOR_V16QI: Likewise.

13238

+ (VSHASIGMAW): Likewise.

13239

+ (VSHASIGMAD): Likewise.

13240

+ (VPMSUM): Likewise.

13241

+ (VPERMXOR): Likewise.

13242

+ (VSHASIGMA): Likewise.

13243

+

13244

+ * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Define

13245

+ __CRYPTO__ if the crypto instructions are available.

13246

+ (altivec_overloaded_builtins): Add support for overloaded power8

13247

+ builtins.

13248

+

13249

+ * config/rs6000/rs6000.c (rs6000_expand_ternop_builtin): Add

13250

+ support for power8 crypto builtins.

13251

+ (builtin_function_type): Likewise.

13252

+ (altivec_init_builtins): Add support for builtins that take vector

13253

+ long long (V2DI) arguments.

13254

+

13255

+ * config/rs6000/crypto.md: New file, define power8 crypto

13256

+ instructions.

13257

+

13258

+ 2013-05-22 Michael Meissner <meissner@linux.vnet.ibm.com>

13259

+ Pat Haugen <pthaugen@us.ibm.com>

13260

+ Peter Bergner <bergner@vnet.ibm.com>

13261

+

13262

+ * doc/invoke.texi (Option Summary): Add power8 options.

13263

+ (RS/6000 and PowerPC Options): Likewise.

13264

+

13265

+ * doc/md.texi (PowerPC and IBM RS6000 constraints): Update to use

13266

+ constraints.md instead of rs6000.h. Reorder w* constraints. Add

13267

+ wm, wn, wr documentation.

13268

+

13269

+ * gcc/config/rs6000/constraints.md (wm): New constraint for VSX

13270

+ registers if direct move instructions are enabled.

13271

+ (wn): New constraint for no registers.

13272

+ (wq): New constraint for quad word even GPR registers.

13273

+ (wr): New constraint if 64-bit instructions are enabled.

13274

+ (wv): New constraint if power8 vector instructions are enabled.

13275

+ (wQ): New constraint for quad word memory locations.

13276

+

13277

+ * gcc/config/rs6000/predicates.md (const_0_to_15_operand): New

13278

+ constraint for 0..15 for crypto instructions.

13279

+ (gpc_reg_operand): If VSX allow registers in VSX registers as well

13280

+ as GPR and floating point registers.

13281

+ (int_reg_operand): New predicate to match only GPR registers.

13282

+ (base_reg_operand): New predicate to match base registers.

13283

+ (quad_int_reg_operand): New predicate to match even GPR registers

13284

+ for quad memory operations.

13285

+ (vsx_reg_or_cint_operand): New predicate to allow vector logical

13286

+ operations in both GPR and VSX registers.

13287

+ (quad_memory_operand): New predicate for quad memory operations.

13288

+ (reg_or_indexed_operand): New predicate for direct move support.

13289

+

13290

+ * gcc/config/rs6000/rs6000-cpus.def (ISA_2_5_MASKS_EMBEDDED):

13291

+ Inherit from ISA_2_4_MASKS, not ISA_2_2_MASKS.

13292

+ (ISA_2_7_MASKS_SERVER): New mask for ISA 2.07 (i.e. power8).

13293

+ (POWERPC_MASKS): Add power8 options.

13294

+ (power8 cpu): Use ISA_2_7_MASKS_SERVER instead of specifying the

13295

+ various options.

13296

+

13297

+ * gcc/config/rs6000/rs6000-c.c (rs6000_target_modify_macros):

13298

+ Define _ARCH_PWR8 and __POWER8_VECTOR__ for power8.

13299

+

13300

+ * gcc/config/rs6000/rs6000.opt (-mvsx-timode): Add documentation.

13301

+ (-mpower8-fusion): New power8 options.

13302

+ (-mpower8-fusion-sign): Likewise.

13303

+ (-mpower8-vector): Likewise.

13304

+ (-mcrypto): Likewise.

13305

+ (-mdirect-move): Likewise.

13306

+ (-mquad-memory): Likewise.

13307

+

13308

+ * gcc/config/rs6000/rs6000.c (power8_cost): Initial definition for

13309

+ power8.

13310

+ (rs6000_hard_regno_mode_ok): Make PTImode only match even GPR

13311

+ registers.

13312

+ (rs6000_debug_reg_print): Print the base register class if

13313

+ -mdebug=reg.

13314

+ (rs6000_debug_vector_unit): Add p8_vector.

13315

+ (rs6000_debug_reg_global): If -mdebug=reg, print power8 constraint

13316

+ definitions. Also print fusion state.

13317

+ (rs6000_init_hard_regno_mode_ok): Set up power8 constraints.

13318

+ (rs6000_builtin_mask_calculate): Add power8 builtin support.

13319

+ (rs6000_option_override_internal): Add support for power8.

13320

+ (rs6000_common_init_builtins): Add debugging for skipped builtins

13321

+ if -mdebug=builtin.

13322

+ (rs6000_adjust_cost): Add power8 support.

13323

+ (rs6000_issue_rate): Likewise.

13324

+ (insn_must_be_first_in_group): Likewise.

13325

+ (insn_must_be_last_in_group): Likewise.

13326

+ (force_new_group): Likewise.

13327

+ (rs6000_register_move_cost): Likewise.

13328

+ (rs6000_opt_masks): Likewise.

13329

+

13330

+ * config/rs6000/rs6000.h (ASM_CPU_POWER8_SPEC): If we don't have a

13331

+ power8 capable assembler, default to power7 options.

13332

+ (TARGET_DIRECT_MOVE): Likewise.

13333

+ (TARGET_CRYPTO): Likewise.

13334

+ (TARGET_P8_VECTOR): Likewise.

13335

+ (VECTOR_UNIT_P8_VECTOR_P): Define power8 vector support.

13336

+ (VECTOR_UNIT_VSX_OR_P8_VECTOR_P): Likewise.

13337

+ (VECTOR_MEM_P8_VECTOR_P): Likewise.

13338

+ (VECTOR_MEM_VSX_OR_P8_VECTOR_P): Likewise.

13339

+ (VECTOR_MEM_ALTIVEC_OR_VSX_P): Likewise.

13340

+ (TARGET_XSCVDPSPN): Likewise.

13341

+ (TARGET_XSCVSPDPN): Likewsie.

13342

+ (TARGET_SYNC_HI_QI): Likewise.

13343

+ (TARGET_SYNC_TI): Likewise.

13344

+ (MASK_CRYPTO): Likewise.

13345

+ (MASK_DIRECT_MOVE): Likewise.

13346

+ (MASK_P8_FUSION): Likewise.

13347

+ (MASK_P8_VECTOR): Likewise.

13348

+ (REG_ALLOC_ORDER): Move fr13 to be lower in priority so that the

13349

+ TFmode temporary used by some of the direct move instructions to

13350

+ get two FP temporary registers does not force creation of a stack

13351

+ frame.

13352

+ (VLOGICAL_REGNO_P): Allow vector logical operations in GPRs.

13353

+ (MODES_TIEABLE_P): Move the VSX tests above the Altivec tests so

13354

+ that any VSX registers are tieable, even if they are also an

13355

+ Altivec vector mode.

13356

+ (r6000_reg_class_enum): Add wm, wr, wv constraints.

13357

+ (RS6000_BTM_P8_VECTOR): Power8 builtin support.

13358

+ (RS6000_BTM_CRYPTO): Likewise.

13359

+ (RS6000_BTM_COMMON): Likewise.

13360

+

13361

+ * config/rs6000/rs6000.md (cpu attribute): Add power8.

13362

+ * config/rs6000/rs6000-opts.h (PROCESSOR_POWER8): Likewise.

13363

+ (enum rs6000_vector): Add power8 vector support.

13364

+

13365

+

13366

+ Backport from mainline

13367

+ 2013-03-20 Pat Haugen <pthaugen@us.ibm.com>

13368

+

13369

+ * config/rs6000/predicates.md (indexed_address, update_address_mem

13370

+ update_indexed_address_mem): New predicates.

13371

+ * config/rs6000/vsx.md (vsx_extract_<mode>_zero): Set correct "type"

13372

+ attribute for load/store instructions.

13373

+ * config/rs6000/dfp.md (movsd_store): Likewise.

13374

+ (movsd_load): Likewise.

13375

+ * config/rs6000/rs6000.md (zero_extend<mode>di2_internal1): Likewise.

13376

+ (unnamed HI->DI extend define_insn): Likewise.

13377

+ (unnamed SI->DI extend define_insn): Likewise.

13378

+ (unnamed QI->SI extend define_insn): Likewise.

13379

+ (unnamed QI->HI extend define_insn): Likewise.

13380

+ (unnamed HI->SI extend define_insn): Likewise.

13381

+ (unnamed HI->SI extend define_insn): Likewise.

13382

+ (extendsfdf2_fpr): Likewise.

13383

+ (movsi_internal1): Likewise.

13384

+ (movsi_internal1_single): Likewise.

13385

+ (movhi_internal): Likewise.

13386

+ (movqi_internal): Likewise.

13387

+ (movcc_internal1): Correct mnemonic for stw insn. Set correct "type"

13388

+ attribute for load/store instructions.

13389

+ (mov<mode>_hardfloat): Set correct "type" attribute for load/store

13390

+ instructions.

13391

+ (mov<mode>_softfloat): Likewise.

13392

+ (mov<mode>_hardfloat32): Likewise.

13393

+ (mov<mode>_hardfloat64): Likewise.

13394

+ (mov<mode>_softfloat64): Likewise.

13395

+ (movdi_internal32): Likewise.

13396

+ (movdi_internal64): Likewise.

13397

+ (probe_stack_<mode>): Likewise.

13398

+

13399

+ Backport from mainline

13400

+ 2013-03-20 Michael Meissner <meissner@linux.vnet.ibm.com>

13401

+

13402

+ * config/rs6000/vector.md (VEC_R): Add 32-bit integer, binary

13403

+ floating point, and decimal floating point to reload iterator.

13404

+

13405

+ * config/rs6000/constraints.md (wl constraint): New constraints to

13406

+ return FLOAT_REGS if certain options are used to reduce the number

13407

+ of separate patterns that exist in the file.

13408

+ (wx constraint): Likewise.

13409

+ (wz constraint): Likewise.

13410

+

13411

+ * config/rs6000/rs6000.c (rs6000_debug_reg_global): If

13412

+ -mdebug=reg, print wg, wl, wx, and wz constraints.

13413

+ (rs6000_init_hard_regno_mode_ok): Initialize new constraints.

13414

+ Initialize the reload functions for 64-bit binary/decimal floating

13415

+ point types.

13416

+ (reg_offset_addressing_ok_p): If we are on a power7 or later, use

13417

+ LFIWZX and STFIWX to load/store 32-bit decimal types, and don't

13418

+ create the buffer on the stack to overcome not having a 32-bit

13419

+ load and store.

13420

+ (rs6000_emit_move): Likewise.

13421

+ (rs6000_secondary_memory_needed_rtx): Likewise.

13422

+ (rs6000_alloc_sdmode_stack_slot): Likewise.

13423

+ (rs6000_preferred_reload_class): On VSX, we can create SFmode 0.0f

13424

+ via xxlxor, just like DFmode 0.0.

13425

+

13426

+ * config/rs6000/rs6000.h (TARGET_NO_SDMODE_STACK): New macro)

13427

+ (define as 1 if we are running on a power7 or newer.

13428

+ (enum r6000_reg_class_enum): Add new constraints.

13429

+

13430

+ * config/rs6000/dfp.md (movsd): Delete, combine with binary

13431

+ floating point moves in rs6000.md. Combine power6x (mfpgpr) moves

13432

+ with other moves by using conditional constraits (wg). Use LFIWZX

13433

+ and STFIWX for loading SDmode on power7. Use xxlxor to create

13434

+ 0.0f.

13435

+ (movsd splitter): Likewise.

13436

+ (movsd_hardfloat): Likewise.

13437

+ (movsd_softfloat): Likewise.

13438

+

13439

+ * config/rs6000/rs6000.md (FMOVE32): New iterators to combine

13440

+ binary and decimal floating point moves.

13441

+ (fmove_ok): New attributes to combine binary and decimal floating

13442

+ point moves, and to combine power6x (mfpgpr) moves along normal

13443

+ floating moves.

13444

+ (real_value_to_target): Likewise.

13445

+ (f32_lr): Likewise.

13446

+ (f32_lm): Likewise.

13447

+ (f32_li): Likewise.

13448

+ (f32_sr): Likewise.

13449

+ (f32_sm): Likewise.

13450

+ (f32_si): Likewise.

13451

+ (movsf): Combine binary and decimal floating point moves. Combine

13452

+ power6x (mfpgpr) moves with other moves by using conditional

13453

+ constraits (wg). Use LFIWZX and STFIWX for loading SDmode on

13454

+ power7.

13455

+ (mov<mode> for SFmode/SDmode); Likewise.

13456

+ (SFmode/SDmode splitters): Likewise.

13457

+ (movsf_hardfloat): Likewise.

13458

+ (mov<mode>_hardfloat for SFmode/SDmode): Likewise.

13459

+ (movsf_softfloat): Likewise.

13460

+ (mov<mode>_softfloat for SFmode/SDmode): Likewise.

13461

+

13462

+ * doc/md.texi (PowerPC and IBM RS6000 constraints): Document wl)

13463

+ (wx and wz constraints.

13464

+

13465

+ * config/rs6000/constraints.md (wg constraint): New constraint to

13466

+ return FLOAT_REGS if -mmfpgpr (power6x) was used.

13467

+

13468

+ * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Add wg

13469

+ constraint.

13470

+

13471

+ * config/rs6000/rs6000.c (rs6000_debug_reg_global): If

13472

+ -mdebug=reg, print wg, wl, wx, and wz constraints.

13473

+ (rs6000_init_hard_regno_mode_ok): Initialize new constraints.

13474

+ Initialize the reload functions for 64-bit binary/decimal floating

13475

+ point types.

13476

+ (reg_offset_addressing_ok_p): If we are on a power7 or later, use

13477

+ LFIWZX and STFIWX to load/store 32-bit decimal types, and don't

13478

+ create the buffer on the stack to overcome not having a 32-bit

13479

+ load and store.

13480

+ (rs6000_emit_move): Likewise.

13481

+ (rs6000_secondary_memory_needed_rtx): Likewise.

13482

+ (rs6000_alloc_sdmode_stack_slot): Likewise.

13483

+ (rs6000_preferred_reload_class): On VSX, we can create SFmode 0.0f

13484

+ via xxlxor, just like DFmode 0.0.

13485

+

13486

+

13487

+ * config/rs6000/dfp.md (movdd): Delete, combine with binary

13488

+ floating point moves in rs6000.md. Combine power6x (mfpgpr) moves

13489

+ with other moves by using conditional constraits (wg). Use LFIWZX

13490

+ and STFIWX for loading SDmode on power7.

13491

+ (movdd splitters): Likewise.

13492

+ (movdd_hardfloat32): Likewise.

13493

+ (movdd_softfloat32): Likewise.

13494

+ (movdd_hardfloat64_mfpgpr): Likewise.

13495

+ (movdd_hardfloat64): Likewise.

13496

+ (movdd_softfloat64): Likewise.

13497

+

13498

+ * config/rs6000/rs6000.md (FMOVE64): New iterators to combine

13499

+ 64-bit binary and decimal floating point moves.

13500

+ (FMOVE64X): Likewise.

13501

+ (movdf): Combine 64-bit binary and decimal floating point moves.

13502

+ Combine power6x (mfpgpr) moves with other moves by using

13503

+ conditional constraits (wg).

13504

+ (mov<mode> for DFmode/DDmode): Likewise.

13505

+ (DFmode/DDmode splitters): Likewise.

13506

+ (movdf_hardfloat32): Likewise.

13507

+ (mov<mode>_hardfloat32 for DFmode/DDmode): Likewise.

13508

+ (movdf_softfloat32): Likewise.

13509

+ (movdf_hardfloat64_mfpgpr): Likewise.

13510

+ (movdf_hardfloat64): Likewise.

13511

+ (mov<mode>_hardfloat64 for DFmode/DDmode): Likewise.

13512

+ (movdf_softfloat64): Likewise.

13513

+ (mov<mode>_softfloat64 for DFmode/DDmode): Likewise.

13514

+ (reload_<mode>_load): Move to later in the file so they aren't in

13515

+ the middle of the floating point move insns.

13516

+ (reload_<mode>_store): Likewise.

13517

+

13518

+ * doc/md.texi (PowerPC and IBM RS6000 constraints): Document wg

13519

+ constraint.

13520

+

13521

+ * config/rs6000/rs6000.c (rs6000_debug_reg_global): Print out wg

13522

+ constraint if -mdebug=reg.

13523

+ (rs6000_initi_hard_regno_mode_ok): Enable wg constraint if

13524

+ -mfpgpr. Enable using dd reload support if needed.

13525

+

13526

+ * config/rs6000/dfp.md (movtd): Delete, combine with 128-bit

13527

+ binary and decimal floating point moves in rs6000.md.

13528

+ (movtd_internal): Likewise.

13529

+

13530

+ * config/rs6000/rs6000.md (FMOVE128): Combine 128-bit binary and

13531

+ decimal floating point moves.

13532

+ (movtf): Likewise.

13533

+ (movtf_internal): Likewise.

13534

+ (mov<mode>_internal, TDmode/TFmode): Likewise.

13535

+ (movtf_softfloat): Likewise.

13536

+ (mov<mode>_softfloat, TDmode/TFmode): Likewise.

13537

+

13538

+ * config/rs6000/rs6000.md (movdi_mfpgpr): Delete, combine with

13539

+ movdi_internal64, using wg constraint for move direct operations.

13540

+ (movdi_internal64): Likewise.

13541

+

13542

+ * config/rs6000/rs6000.c (rs6000_debug_reg_global): Print

13543

+ MODES_TIEABLE_P for selected modes. Print the numerical value of

13544

+ the various virtual registers. Use GPR/FPR first/last values)

13545

+ (instead of hard coding the register numbers. Print which modes

13546

+ have reload functions registered.

13547

+ (rs6000_option_override_internal): If -mdebug=reg, trace the

13548

+ options settings before/after setting cpu, target and subtarget

13549

+ settings.

13550

+ (rs6000_secondary_reload_trace): Improve the RTL dump for

13551

+ -mdebug=addr and for secondary reload failures in

13552

+ rs6000_secondary_reload_inner.

13553

+ (rs6000_secondary_reload_fail): Likewise.

13554

+ (rs6000_secondary_reload_inner): Likewise.

13555

+

13556

+ * config/rs6000/rs6000.md (FIRST_GPR_REGNO): Add convenience

13557

+ macros for first/last GPR and FPR registers.

13558

+ (LAST_GPR_REGNO): Likewise.

13559

+ (FIRST_FPR_REGNO): Likewise.

13560

+ (LAST_FPR_REGNO): Likewise.

13561

+

13562

+ * config/rs6000/vector.md (mul<mode>3): Use the combined macro

13563

+ VECTOR_UNIT_ALTIVEC_OR_VSX_P instead of separate calls to

13564

+ VECTOR_UNIT_ALTIVEC_P and VECTOR_UNIT_VSX_P.

13565

+ (vcond<mode><mode>): Likewise.

13566

+ (vcondu<mode><mode>): Likewise.

13567

+ (vector_gtu<mode>): Likewise.

13568

+ (vector_gte<mode>): Likewise.

13569

+ (xor<mode>3): Don't allow logical operations on TImode in 32-bit

13570

+ to prevent the compiler from converting DImode operations to

13571

+ TImode.

13572

+ (ior<mode>3): Likewise.

13573

+ (and<mode>3): Likewise.

13574

+ (one_cmpl<mode>2): Likewise.

13575

+ (nor<mode>3): Likewise.

13576

+ (andc<mode>3): Likewise.

13577

+

13578

+ * config/rs6000/constraints.md (wt constraint): New constraint

13579

+ that returns VSX_REGS if TImode is allowed in VSX registers.

13580

+

13581

+ * config/rs6000/predicates.md (easy_fp_constant): 0.0f is an easy

13582

+ constant under VSX.

13583

+

13584

+ * config/rs6000/rs6000-modes.def (PTImode): Define, PTImode is

13585

+ similar to TImode, but it is restricted to being in the GPRs.

13586

+

13587

+ * config/rs6000/rs6000.opt (-mvsx-timode): New switch to allow

13588

+ TImode to occupy a single VSX register.

13589

+

13590

+ * config/rs6000/rs6000-cpus.def (ISA_2_6_MASKS_SERVER): Default to

13591

+ -mvsx-timode for power7/power8.

13592

+ (power7 cpu): Likewise.

13593

+ (power8 cpu): Likewise.

13594

+

13595

+ * config/rs6000/rs6000.c (rs6000_hard_regno_nregs_internal): Make

13596

+ sure that TFmode/TDmode take up two registers if they are ever

13597

+ allowed in the upper VSX registers.

13598

+ (rs6000_hard_regno_mode_ok): If -mvsx-timode, allow TImode in VSX

13599

+ registers.

13600

+ (rs6000_init_hard_regno_mode_ok): Likewise.

13601

+ (rs6000_debug_reg_global): Add debugging for PTImode and wt

13602

+ constraint. Print if LRA is turned on.

13603

+ (rs6000_option_override_internal): Give an error if -mvsx-timode

13604

+ and VSX is not enabled.

13605

+ (invalid_e500_subreg): Handle PTImode, restricting it to GPRs. If

13606

+ -mvsx-timode, restrict TImode to reg+reg addressing, and PTImode

13607

+ to reg+offset addressing. Use PTImode when checking offset

13608

+ addresses for validity.

13609

+ (reg_offset_addressing_ok_p): Likewise.

13610

+ (rs6000_legitimate_offset_address_p): Likewise.

13611

+ (rs6000_legitimize_address): Likewise.

13612

+ (rs6000_legitimize_reload_address): Likewise.

13613

+ (rs6000_legitimate_address_p): Likewise.

13614

+ (rs6000_eliminate_indexed_memrefs): Likewise.

13615

+ (rs6000_emit_move): Likewise.

13616

+ (rs6000_secondary_reload): Likewise.

13617

+ (rs6000_secondary_reload_inner): Handle PTImode. Allow 64-bit

13618

+ reloads to fpr registers to continue to use reg+offset addressing)

13619

+ (but 64-bit reloads to altivec registers need reg+reg addressing.

13620

+ Drop test for PRE_MODIFY, since VSX loads/stores no longer support

13621

+ it. Treat LO_SUM like a PLUS operation.

13622

+ (rs6000_secondary_reload_class): If type is 64-bit, prefer to use

13623

+ FLOAT_REGS instead of VSX_RGS to allow use of reg+offset

13624

+ addressing.

13625

+ (rs6000_cannot_change_mode_class): Do not allow TImode in VSX

13626

+ registers to share a register with a smaller sized type, since VSX

13627

+ puts scalars in the upper 64-bits.

13628

+ (print_operand): Add support for PTImode.

13629

+ (rs6000_register_move_cost): Use VECTOR_MEM_VSX_P instead of

13630

+ VECTOR_UNIT_VSX_P to catch types that can be loaded in VSX

13631

+ registers, but don't have arithmetic support.

13632

+ (rs6000_memory_move_cost): Add test for VSX.

13633

+ (rs6000_opt_masks): Add -mvsx-timode.

13634

+

13635

+ * config/rs6000/vsx.md (VSm): Change to use 64-bit aligned moves

13636

+ for TImode.

13637

+ (VSs): Likewise.

13638

+ (VSr): Use wt constraint for TImode.

13639

+ (VSv): Drop TImode support.

13640

+ (vsx_movti): Delete, replace with versions for 32-bit and 64-bit.

13641

+ (vsx_movti_64bit): Likewise.

13642

+ (vsx_movti_32bit): Likewise.

13643

+ (vec_store_<mode>): Use VSX iterator instead of vector iterator.

13644

+ (vsx_and<mode>3): Delete use of '?' constraint on inputs, just put

13645

+ one '?' on the appropriate output constraint. Do not allow TImode

13646

+ logical operations on 32-bit systems.

13647

+ (vsx_ior<mode>3): Likewise.

13648

+ (vsx_xor<mode>3): Likewise.

13649

+ (vsx_one_cmpl<mode>2): Likewise.

13650

+ (vsx_nor<mode>3): Likewise.

13651

+ (vsx_andc<mode>3): Likewise.

13652

+ (vsx_concat_<mode>): Likewise.

13653

+ (vsx_xxpermdi_<mode>): Fix thinko for non V2DF/V2DI modes.

13654

+

13655

+ * config/rs6000/rs6000.h (MASK_VSX_TIMODE): Map from

13656

+ OPTION_MASK_VSX_TIMODE.

13657

+ (enum rs6000_reg_class_enum): Add RS6000_CONSTRAINT_wt.

13658

+ (STACK_SAVEAREA_MODE): Use PTImode instead of TImode.

13659

+

13660

+ * config/rs6000/rs6000.md (INT mode attribute): Add PTImode.

13661

+ (TI2 iterator): New iterator for TImode, PTImode.

13662

+ (wd mode attribute): Add values for vector types.

13663

+ (movti_string): Replace TI move operations with operations for

13664

+ TImode and PTImode. Add support for TImode being allowed in VSX

13665

+ registers.

13666

+ (mov<mode>_string, TImode/PTImode): Likewise.

13667

+ (movti_ppc64): Likewise.

13668

+ (mov<mode>_ppc64, TImode/PTImode): Likewise.

13669

+ (TI mode splitters): Likewise.

13670

+

13671

+ * doc/md.texi (PowerPC and IBM RS6000 constraints): Document wt

13672

+ constraint.

13673

+

13674

+2014-04-04 Richard Biener <rguenther@suse.de>

13675

+

13676

+ * tree-ssanames.c (make_ssa_name_fn): Fix assert.

13677

+

13678

+2014-04-02 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>

13679

+

13680

+ * config/s390/s390.c (s390_expand_insv): Use GET_MODE_BITSIZE.

13681

+

13682

+2014-04-01 Richard Biener <rguenther@suse.de>

13683

+

13684

+ * gimple.h (struct gimple_statement_base): Align subcode to

13685

+ 16 bits.

13686

+

13687

+2014-04-01 Sebastian Huber <sebastian.huber@embedded-brains.de>

13688

+

13689

+ * doc/invoke.texi (mapp-regs): Clarify.

13690

+

13691

+2014-03-31 H.J. Lu <hongjiu.lu@intel.com>

13692

+

13693

+ PR rtl-optimization/60700

13694

+ Backport from mainline

13695

+ 2013-07-30 Zhenqiang Chen <zhenqiang.chen@linaro.org>

13696

+

13697

+ PR rtl-optimization/57637

13698

+ * function.c (move_insn_for_shrink_wrap): Also check the

13699

+ GEN set of the LIVE problem for the liveness analysis

13700

+ if it exists, otherwise give up.

13701

+

13702

+2014-03-30 Kaz Kojima <kkojima@gcc.gnu.org>

13703

+

13704

+ Backport from mainline

13705

+ 2014-03-19 Kaz Kojima <kkojima@gcc.gnu.org>

13706

+

13707

+ PR target/60039

13708

+ * config/sh/sh.md (udivsi3_i1): Clobber R1 register.

13709

+

13710

+2014-03-26 Martin Jambor <mjambor@suse.cz>

13711

+

13712

+ PR ipa/60419

13713

+ * ipa.c (symtab_remove_unreachable_nodes): Clear thunk and

13714

+ alias flags of nodes in the border.

13715

+

13716

+2014-03-26 Eric Botcazou <ebotcazou@adacore.com>

13717

+

13718

+ PR rtl-optimization/60452

13719

+ * rtlanal.c (rtx_addr_can_trap_p_1): Fix head comment.

13720

+ <case REG>: Return 1 for invalid offsets from the frame pointer.

13721

+

13722

+2014-03-24 Richard Biener <rguenther@suse.de>

13723

+

13724

+ PR tree-optimization/60429

13725

+ * tree-ssa-structalias.c (get_constraint_for_ptr_offset): Remove

13726

+ duplicated line.

13727

+

13728

+2014-03-23 Eric Botcazou <ebotcazou@adacore.com>

13729

+

13730

+ PR rtl-optimization/60601

13731

+ * bb-reorder.c (fix_up_fall_thru_edges): Test EDGE_FALLTHRU everywhere.

13732

+

13733

+ * gcc.c (eval_spec_function): Initialize save_growing_value.

13734

+

13735

+2014-03-20 Jakub Jelinek <jakub@redhat.com>

13736

+

13737

+ PR target/60568

13738

+ * config/i386/i386.c (x86_output_mi_thunk): Surround UNSPEC_GOT

13739

+ into CONST, put pic register as first operand of PLUS. Use

13740

+ gen_const_mem for both 32-bit and 64-bit PIC got loads.

13741

+

13742

+2014-03-20 Eric Botcazou <ebotcazou@adacore.com>

13743

+

13744

+ * config/sparc/sparc.c (sparc_do_work_around_errata): Implement work

13745

+ around for store forwarding issue in the FPU on the UT699.

13746

+ * config/sparc/sparc.md (in_branch_delay): Return false for single FP

13747

+ loads and operations if -mfix-ut699 is specified.

13748

+ (divtf3_hq): Tweak attribute.

13749

+ (sqrttf2_hq): Likewise.

13750

+

13751

+2014-03-18 Kai Tietz <ktietz@redhat.com>

13752

+

13753

+ PR rtl-optimization/56356

13754

+ * sdbout.c (sdbout_parms): Verify that parms'

13755

+ incoming argument is valid.

13756

+ (sdbout_reg_parms): Likewise.

13757

+

13758

+2014-03-18 Eric Botcazou <ebotcazou@adacore.com>

13759

+

13760

+ * config/sparc/sparc.c (sparc_do_work_around_errata): Speed up and use

13761

+ proper constant for the store mode.

13762

+

13763

+2014-03-17 Mikael Pettersson <mikpelinux@gmail.com>

13764

+ Committed by Bill Schmidt <wschmidt@linux.vnet.ibm.com>

13765

+

13766

+ Backport from mainline:

13767

+

13768

+ 2013-06-20 Joern Rennecke <joern.rennecke@embecosm.com>

13769

+

13770

+ PR rtl-optimization/57425

13771

+ PR rtl-optimization/57569

13772

+ * alias.c (write_dependence_p): Remove parameters mem_mode and

13773

+ canon_mem_addr. Add parameters x_mode, x_addr and x_canonicalized.

13774

+ Changed all callers.

13775

+ (canon_anti_dependence): Get comments and semantics in sync.

13776

+ Add parameter mem_canonicalized. Changed all callers.

13777

+ * rtl.h (canon_anti_dependence): Update prototype.

13778

+

13779

+ 2013-06-16 Joern Rennecke <joern.rennecke@embecosm.com>

13780

+

13781

+ PR rtl-optimization/57425

13782

+ PR rtl-optimization/57569

13783

+ * alias.c (write_dependence_p): Add new parameters mem_mode,

13784

+ canon_mem_addr and mem_canonicalized. Change type of writep to bool.

13785

+ Changed all callers.

13786

+ (canon_anti_dependence): New function.

13787

+ * cse.c (check_dependence): Use canon_anti_dependence.

13788

+ * cselib.c (cselib_invalidate_mem): Likewise.

13789

+ * rtl.h (canon_anti_dependence): Declare.

13790

+

13791

+2014-03-17 Richard Biener <rguenther@suse.de>

13792

+

13793

+ Backport from mainline

13794

+ 2014-03-11 Richard Biener <rguenther@suse.de>

13795

+

13796

+ PR tree-optimization/60429

13797

+ PR tree-optimization/60485

13798

+ * tree-ssa-structalias.c (set_union_with_increment): Properly

13799

+ take into account all fields that overlap the shifted vars.

13800

+ (do_sd_constraint): Likewise.

13801

+ (do_ds_constraint): Likewise.

13802

+ (get_constraint_for_ptr_offset): Likewise.

13803

+

13804

+2014-03-15 Eric Botcazou <ebotcazou@adacore.com>

13805

+

13806

+ * config/sparc/sparc-protos.h (tls_call_delay): Delete.

13807

+ (eligible_for_call_delay): New prototype.

13808

+ * config/sparc/sparc.c (tls_call_delay): Rename into...

13809

+ (eligible_for_call_delay): ...this. Return false if the instruction

13810

+ cannot be put in the delay slot of a branch.

13811

+ (eligible_for_restore_insn): Simplify.

13812

+ (eligible_for_return_delay): Return false if the instruction cannot be

13813

+ put in the delay slot of a branch and simplify.

13814

+ (eligible_for_sibcall_delay): Return false if the instruction cannot be

13815

+ put in the delay slot of a branch.

13816

+ * config/sparc/sparc.md (fix_ut699): New attribute.

13817

+ (tls_call_delay): Delete.

13818

+ (in_call_delay): Reimplement.

13819

+ (eligible_for_sibcall_delay): Rename into...

13820

+ (in_sibcall_delay): ...this.

13821

+ (eligible_for_return_delay): Rename into...

13822

+ (in_return_delay): ...this.

13823

+ (in_branch_delay): Reimplement.

13824

+ (in_uncond_branch_delay): Delete.

13825

+ (in_annul_branch_delay): Delete.

13826

+

13827

+2014-03-14 Georg-Johann Lay <avr@gjlay.de>

13828

+

13829

+ Backport from 2014-03-14 trunk r208562.

13830

+

13831

+ PR target/59396

13832

+ * config/avr/avr.c (avr_set_current_function): Pass function name

13833

+ through default_strip_name_encoding before sanity checking instead

13834

+ of skipping the first char of the assembler name.

13835

+

13836

+2014-03-13 Georg-Johann Lay <avr@gjlay.de>

13837

+

13838

+ Backport from 2014-03-13 trunk r208532.

13839

+

13840

+ PR target/60486

13841

+ * config/avr/avr.c (avr_out_plus): Swap cc_plus and cc_minus in

13842

+ calls of avr_out_plus_1.

13843

+

13844

+2014-03-13 Joey Ye <joey.ye@arm.com>

13845

+

13846

+ Backport from mainline

13847

+ 2014-03-12 Thomas Preud'homme <thomas.preudhomme@arm.com>

13848

+

13849

+ PR tree-optimization/60454

13850

+ * tree-ssa-math-opts.c (find_bswap_1): Fix bswap detection.

13851

+

13852

+2014-03-06 Matthias Klose <doko@ubuntu.com>

13853

+

13854

+ * Makefile.in (s-mlib): Only pass MULTIARCH_DIRNAME if

13855

+ MULTILIB_OSDIRNAMES is not defined.

13856

+

13857

+2014-03-06 Jakub Jelinek <jakub@redhat.com>

13858

+

13859

+ PR tree-optimization/60276

13860

+ * tree-vect-data-refs.c (vect_analyze_data_ref_dependence): Avoid

13861

+ a -Wsign-compare warning.

13862

+

13863

+ * Makefile.in (tree-ssa-uninit.o): Depend on $(PARAMS_H).

13864

+

13865

+ Backport from mainline

13866

+ 2014-02-21 Jakub Jelinek <jakub@redhat.com>

13867

+

13868

+ PR tree-optimization/56490

13869

+ * params.def (PARAM_UNINIT_CONTROL_DEP_ATTEMPTS): New param.

13870

+ * tree-ssa-uninit.c: Include params.h.

13871

+ (compute_control_dep_chain): Add num_calls argument, return false

13872

+ if it exceed PARAM_UNINIT_CONTROL_DEP_ATTEMPTS param, pass

13873

+ num_calls to recursive call.

13874

+ (find_predicates): Change dep_chain into normal array, add num_calls

13875

+ variable and adjust compute_control_dep_chain caller.

13876

+ (find_def_preds): Likewise.

13877

+

13878

+ 2014-02-13 Jakub Jelinek <jakub@redhat.com>

13879

+

13880

+ PR target/43546

13881

+ * expr.c (compress_float_constant): If x is a hard register,

13882

+ extend into a pseudo and then move to x.

13883

+

13884

+ 2014-02-11 Richard Henderson <rth@redhat.com>

13885

+ Jakub Jelinek <jakub@redhat.com>

13886

+

13887

+ PR debug/59776

13888

+ * tree-sra.c (load_assign_lhs_subreplacements): Add VIEW_CONVERT_EXPR

13889

+ around drhs if type conversion to lacc->type is not useless.

13890

+

13891

+ 2014-02-08 Jakub Jelinek <jakub@redhat.com>

13892

+

13893

+ PR ipa/60026

13894

+ * ipa-cp.c (determine_versionability): Fail at -O0

13895

+ or __attribute__((optimize (0))) or -fno-ipa-cp functions.

13896

+ * tree-sra.c (ipa_sra_preliminary_function_checks): Similarly.

13897

+

13898

+ 2014-02-06 Jakub Jelinek <jakub@redhat.com>

13899

+

13900

+ PR target/60062

13901

+ * tree.h (opts_for_fn): New inline function.

13902

+ (opt_for_fn): Define.

13903

+ * config/i386/i386.c (ix86_function_regparm): Use

13904

+ opt_for_fn (decl, optimize) instead of optimize.

13905

+

13906

+ 2014-02-05 Jakub Jelinek <jakub@redhat.com>

13907

+

13908

+ PR middle-end/57499

13909

+ * tree-eh.c (cleanup_empty_eh): Bail out on totally empty

13910

+ bb with no successors.

13911

+

13912

+2014-03-04 Richard Biener <rguenther@suse.de>

13913

+

13914

+ PR tree-optimization/60382

13915

+ * tree-vect-loop.c (vect_is_simple_reduction_1): Do not consider

13916

+ dead PHIs a reduction.

13917

+

13918

+2014-02-25 Richard Biener <rguenther@suse.de>

13919

+

13920

+ Backport from mainline

13921

+ 2014-02-21 Richard Biener <rguenther@suse.de>

13922

+

13923

+ PR tree-optimization/60276

13924

+ * tree-vectorizer.h (struct _stmt_vec_info): Add min_neg_dist field.

13925

+ (STMT_VINFO_MIN_NEG_DIST): New macro.

13926

+ * tree-vect-data-refs.c (vect_analyze_data_ref_dependence): Record

13927

+ STMT_VINFO_MIN_NEG_DIST.

13928

+ * tree-vect-stmts.c (vectorizable_load): Verify if assumptions

13929

+ made for negative dependence distances still hold.

13930

+

13931

+2014-02-25 Richard Biener <rguenther@suse.de>

13932

+

13933

+ Backport from mainline

13934

+ 2014-02-21 Richard Biener <rguenther@suse.de>

13935

+

13936

+ PR middle-end/60291

13937

+ * tree-ssa-live.c (mark_all_vars_used_1): Do not walk

13938

+ DECL_INITIAL for globals not in the current function context.

13939

+

13940

+ 2014-02-20 Richard Biener <rguenther@suse.de>

13941

+

13942

+ PR middle-end/60221

13943

+ * tree-eh.c (execute_cleanup_eh_1): Also cleanup empty EH

13944

+ regions at -O0.

13945

+

13946

+ 2014-02-14 Richard Biener <rguenther@suse.de>

13947

+

13948

+ PR tree-optimization/60183

13949

+ * tree-ssa-phiprop.c (propagate_with_phi): Avoid speculating

13950

+ loads.

13951

+ (tree_ssa_phiprop): Calculate and free post-dominators.

13952

+

13953

+2014-02-25 Kyrylo Tkachov <kyrylo.tkachov@arm.com>

13954

+

13955

+ PR target/55426

13956

+ * config/arm/arm.h (CANNOT_CHANGE_MODE_CLASS): Allow 128 to 64-bit

13957

+ conversions.

13958

+

13959

+2014-02-24 John David Anglin <danglin@gcc.gnu.org>

13960

+

13961

+ * config/pa/pa.c (pa_output_move_double): Don't valididate when

13962

+ adjusting offsetable addresses.

13963

+

13964

+2014-02-23 David Holsgrove <david.holsgrove@xilinx.com>

13965

+

13966

+ * config/microblaze/microblaze.md: Correct ashrsi_reg / lshrsi_reg names

13967

+

13968

+2014-02-23 Edgar E. Iglesias <edgar.iglesias@xilinx.com>

13969

+

13970

+ * config/microblaze/microblaze.h: Remove SECONDARY_MEMORY_NEEDED

13971

+ definition.

13972

+

13973

+2014-02-23 David Holsgrove <david.holsgrove@xilinx.com>

13974

+

13975

+ * /config/microblaze/microblaze.c: Add microblaze_asm_output_mi_thunk

13976

+ and define TARGET_ASM_OUTPUT_MI_THUNK and

13977

+ TARGET_ASM_CAN_OUTPUT_MI_THUNK.

13978

+

13979

+2014-02-23 David Holsgrove <david.holsgrove@xilinx.com>

13980

+

13981

+ * config/microblaze/predicates.md: Add cmp_op predicate.

13982

+ * config/microblaze/microblaze.md: Add branch_compare instruction

13983

+ which uses cmp_op predicate and emits cmp insn before branch.

13984

+ * config/microblaze/microblaze.c (microblaze_emit_compare): Rename

13985

+ to microblaze_expand_conditional_branch and consolidate logic.

13986

+ (microblaze_expand_conditional_branch): emit branch_compare

13987

+ insn instead of handling cmp op separate from branch insn.

13988

+

13989

+2014-02-21 Martin Jambor <mjambor@suse.cz>

13990

+

13991

+ PR ipa/55260

13992

+ * ipa-cp.c (cgraph_edge_brings_all_agg_vals_for_node): Uce correct

13993

+ info when checking whether lattices are bottom.

13994

+

13995

+2014-02-21 Jakub Jelinek <jakub@redhat.com>

13996

+

13997

+ * config/i386/i386.c (ix86_expand_vec_perm): Use V8SImode

13998

+ mode for mask of V8SFmode permutation.

13999

+

14000

+2014-02-20 Richard Henderson <rth@redhat.com>

14001

+

14002

+ PR c++/60272

14003

+ * builtins.c (expand_builtin_atomic_compare_exchange): Conditionalize

14004

+ on failure the store back into EXPECT. Always make a new pseudo for

14005

+ OLDVAL.

14006

+

14007

+2014-02-20 Jakub Jelinek <jakub@redhat.com>

14008

+

14009

+ PR target/57896

14010

+ * config/i386/i386.c (expand_vec_perm_interleave2): Don't call

14011

+ gen_reg_rtx if d->testing_p.

14012

+ (expand_vec_perm_pshufb2, expand_vec_perm_even_odd_1,

14013

+ expand_vec_perm_broadcast_1): Return early if d->testing_p and

14014

+ we will certainly return true.

14015

+

14016

+2014-02-20 Richard Biener <rguenther@suse.de>

14017

+

14018

+ * tree-cfg.c (replace_uses_by): Mark altered BBs before

14019

+ doing the substitution.

14020

+

14021

+2014-02-19 H.J. Lu <hongjiu.lu@intel.com>

14022

+

14023

+ Backport from mainline

14024

+ 2014-02-19 H.J. Lu <hongjiu.lu@intel.com>

14025

+

14026

+ PR target/60207

14027

+ * config/i386/i386.c (construct_container): Remove TFmode check

14028

+ for X86_64_INTEGER_CLASS.

14029

+

14030

+2014-02-19 Uros Bizjak <ubizjak@gmail.com>

14031

+

14032

+ Backport from mainline

14033

+ 2014-02-19 Uros Bizjak <ubizjak@gmail.com>

14034

+

14035

+ PR target/59794

14036

+ * config/i386/i386.c (type_natural_mode): Warn for ABI changes

14037

+ only when -Wpsabi is enabled.

14038

+

14039

+2014-02-19 Terry Guo <terry.guo@arm.com>

14040

+

14041

+ Backport from mainline

14042

+ 2014-02-08 Terry Guo <terry.guo@arm.com>

14043

+

14044

+ * doc/invoke.texi: Document ARM -march=armv7e-m.

14045

+

14046

+2014-02-18 Kai Tietz <ktietz@redhat.com>

14047

+

14048

+ Backport from mainline

14049

+ 2014-02-18 Kai Tietz <ktietz@redhat.com>

14050

+

14051

+ PR target/60193

14052

+ * config/i386/i386.c (ix86_expand_prologue): Use

14053

+ rax register as displacement for restoring %r10, %rax.

14054

+ Additional fix wrong offset for restoring both-registers.

14055

+

14056

+2014-02-18 Eric Botcazou <ebotcazou@adacore.com>

14057

+

14058

+ * ipa-prop.c (compute_complex_ancestor_jump_func): Replace overzealous

14059

+ assertion with conditional return.

14060

+

14061

+2014-02-18 Jakub Jelinek <jakub@redhat.com>

14062

+ Uros Bizjak <ubizjak@gmail.com>

14063

+

14064

+ PR driver/60233

14065

+ * config/i386/driver-i386.c (host_detect_local_cpu): If

14066

+ YMM state is not saved by the OS, also clear has_f16c. Move

14067

+ CPUID 0x80000001 handling before YMM state saving checking.

14068

+

14069

+2014-02-14 Roland McGrath <mcgrathr@google.com>

14070

+

14071

+ * configure.ac (HAVE_AS_IX86_UD2): New test for 'ud2' mnemonic.

14072

+ * configure: Regenerated.

14073

+ * config.in: Regenerated.

14074

+ * config/i386/i386.md (trap) [HAVE_AS_IX86_UD2]: Use the mnemonic

14075

+ instead of ASM_SHORT.

14076

+

14077

+2014-02-13 Uros Bizjak <ubizjak@gmail.com>

14078

+

14079

+ Backport from mainline

14080

+ 2014-02-13 Uros Bizjak <ubizjak@gmail.com>

14081

+

14082

+ * config/i386/sse.md (xop_vmfrcz<mode>2): Generate const0 in

14083

+ operands[2], not operands[3].

14084

+

14085

+2014-02-13 Dominik Vogt <vogt@linux.vnet.ibm.com>

14086

+

14087

+ * config/s390/s390.c (s390_asm_output_function_label): Fix crash

14088

+ caused by bad second argument to warning_at() with -mhotpatch and

14089

+ nested functions (e.g. with gfortran).

14090

+

14091

+2014-02-12 H.J. Lu <hongjiu.lu@intel.com>

14092

+

14093

+ Backport from mainline

14094

+ 2014-02-12 H.J. Lu <hongjiu.lu@intel.com>

14095

+ Uros Bizjak <ubizjak@gmail.com>

14096

+

14097

+ PR target/60151

14098

+ * configure.ac (HAVE_AS_GOTOFF_IN_DATA): Pass --32 to GNU assembler.

14099

+

14100

+2014-02-12 Eric Botcazou <ebotcazou@adacore.com>

14101

+

14102

+ PR rtl-optimization/60116

14103

+ * combine.c (try_combine): Also remove dangling REG_DEAD notes on the

14104

+ other_insn once the combination has been validated.

14105

+

14106

+2014-02-10 Nagaraju Mekala <nagaraju.mekala@xilinx.com>

14107

+

14108

+ * config/microblaze/microblaze.md: Add movsi4_rev insn pattern.

14109

+ * config/microblaze/predicates.md: Add reg_or_mem_operand predicate.

14110

+

14111

+2014-02-10 Nagaraju Mekala <nagaraju.mekala@xilinx.com>

14112

+

14113

+ * config/microblaze/microblaze.c: Extend mcpu version format

14114

+

14115

+2014-02-10 David Holsgrove <david.holsgrove@xilinx.com>

14116

+

14117

+ * config/microblaze/microblaze.h: Define SIZE_TYPE and PTRDIFF_TYPE.

14118

+

14119

+2014-02-10 Richard Biener <rguenther@suse.de>

14120

+

14121

+ Backport from mainline

14122

+ 2014-01-30 Richard Biener <rguenther@suse.de>

14123

+

14124

+ PR tree-optimization/59903

14125

+ * tree-vect-loop.c (vect_transform_loop): Guard multiple-types

14126

+ check properly.

14127

+

14128

+ 2014-02-10 Richard Biener <rguenther@suse.de>

14129

+

14130

+ PR tree-optimization/60115

14131

+ * tree-eh.c (tree_could_trap_p): Unify TARGET_MEM_REF and

14132

+ MEM_REF handling. Properly verify that the accesses are not

14133

+ out of the objects bound.

14134

+

14135

+2014-02-05 James Greenhalgh <james.greenhalgh@arm.com>

14136

+

14137

+ Backport from mainline.

14138

+ 2014-02-05 James Greenhalgh <james.greenhalgh@arm.com>

14139

+

14140

+ PR target/59718

14141

+ * doc/invoke.texi (-march): Clarify documentation for ARM.

14142

+ (-mtune): Likewise.

14143

+ (-mcpu): Likewise.

14144

+

14145

+2014-02-04 John David Anglin <danglin@gcc.gnu.org>

14146

+

14147

+ PR target/59777

14148

+ * config/pa/pa.c (legitimize_tls_address): Return original address

14149

+ if not passed a SYMBOL_REF rtx.

14150

+ (hppa_legitimize_address): Call legitimize_tls_address for all TLS

14151

+ addresses.

14152

+ (pa_emit_move_sequence): Simplify TLS source operands.

14153

+ (pa_legitimate_constant_p): Reject all TLS constants.

14154

+ * config/pa/pa.h (PA_SYMBOL_REF_TLS_P): Correct comment.

14155

+ (CONSTANT_ADDRESS_P): Reject TLS CONST addresses.

14156

+

14157

+2014-02-04 Uros Bizjak <ubizjak@gmail.com>

14158

+

14159

+ Backport from mainline

14160

+ 2014-02-02 Uros Bizjak <ubizjak@gmail.com>

14161

+

14162

+ PR target/60017

14163

+ * config/i386/i386.c (classify_argument): Fix handling of bit_offset

14164

+ when calculating size of integer atomic types.

14165

+

14166

+2014-02-02 Uros Bizjak <ubizjak@gmail.com>

14167

+

14168

+ Backport from mainline

14169

+ 2014-01-30 Jakub Jelinek <jakub@redhat.com>

14170

+

14171

+ * config/i386/f16cintrin.h (_cvtsh_ss): Avoid -Wnarrowing warning.

14172

+

14173

+2014-01-31 Richard Henderson <rth@redhat.com>

14174

+

14175

+ PR middle-end/60004

14176

+ * tree-eh.c (lower_try_finally_switch): Delay lowering finally block

14177

+ until after else_eh is processed.

14178

+

14179

+2014-01-30 David Holsgrove <david.holsgrove@xilinx.com>

14180

+

14181

+ Backport from mainline

14182

+ * config/microblaze/microblaze.md(cstoresf4, cbranchsf4): Replace

14183

+ comparison_operator with ordered_comparison_operator.

14184

+

14185

+2014-01-25 Walter Lee <walt@tilera.com>

14186

+

14187

+ Backport from mainline

14188

+ 2014-01-25 Walter Lee <walt@tilera.com>

14189

+

14190

+ * config/tilegx/sync.md (atomic_fetch_sub): Fix negation and

14191

+ avoid clobbering a live register.

14192

+

14193

+2014-01-25 Walter Lee <walt@tilera.com>

14194

+

14195

+ Backport from mainline

14196

+ 2014-01-25 Walter Lee <walt@tilera.com>

14197

+

14198

+ * config/tilegx/tilegx-c.c (tilegx_cpu_cpp_builtins):

14199

+ Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_{1,2}.

14200

+ * config/tilegx/tilepro-c.c (tilepro_cpu_cpp_builtins):

14201

+ Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_{1,2,4,8}.

14202

+

14203

+2014-01-25 Walter Lee <walt@tilera.com>

14204

+

14205

+ Backport from mainline

14206

+ 2014-01-25 Walter Lee <walt@tilera.com>

14207

+

14208

+ * config/tilegx/tilegx.c (tilegx_gen_bundles): Delete barrier

14209

+ insns before bundling.

14210

+ * config/tilegx/tilegx.md (tile_network_barrier): Update comment.

14211

+

14212

+2014-01-25 Walter Lee <walt@tilera.com>

14213

+

14214

+ Backport from mainline

14215

+ 2014-01-25 Walter Lee <walt@tilera.com>

14216

+

14217

+ * config/tilegx/tilegx.c (tilegx_expand_builtin): Set

14218

+ PREFETCH_SCHEDULE_BARRIER_P to true for prefetches.

14219

+ * config/tilepro/tilepro.c (tilepro_expand_builtin): Ditto.

14220

+

14221

+2014-01-25 Walter Lee <walt@tilera.com>

14222

+

14223

+ Backport from mainline

14224

+ 2014-01-25 Walter Lee <walt@tilera.com>

14225

+

14226

+ * config/tilepro/tilepro.md (ctzdi2): Use register_operand

14227

+ predicate.

14228

+ (clzdi2): Ditto.

14229

+ (ffsdi2): Ditto.

14230

+

14231

+2014-01-25 Walter Lee <walt@tilera.com>

14232

+

14233

+ Backport from mainline

14234

+ 2014-01-25 Walter Lee <walt@tilera.com>

14235

+

14236

+ * config/tilegx/tilegx.c (tilegx_expand_to_rtl_hook): New.

14237

+ (TARGET_EXPAND_TO_RTL_HOOK): Define.

14238

+

14239

+2014-01-24 H.J. Lu <hongjiu.lu@intel.com>

14240

+

14241

+ Backport from mainline

14242

+ 2014-01-23 H.J. Lu <hongjiu.lu@intel.com>

14243

+

14244

+ PR target/59929

14245

+ * config/i386/i386.md (pushsf splitter): Get stack adjustment

14246

+ from push operand if code of push isn't PRE_DEC.

14247

+

14248

+2014-01-23 David Holsgrove <david.holsgrove@xilinx.com>

14249

+

14250

+ Backport from mainline.

14251

+ * config/microblaze/microblaze.md: Add trap insn and attribute

14252

+

14253

+2014-01-23 Marek Polacek <polacek@redhat.com>

14254

+

14255

+ Backport from mainline

14256

+ 2013-10-21 Marek Polacek <polacek@redhat.com>

14257

+

14258

+ PR middle-end/58809

14259

+ * fold-const.c (fold_range_test): Return 0 if the type is not

14260

+ an integral type.

14261

+

14262

+2014-01-22 David Holsgrove <david.holsgrove@xilinx.com>

14263

+

14264

+ * config/microblaze/microblaze.md: Correct bswaphi2 insn.

14265

+

14266

+2014-01-22 Uros Bizjak <ubizjak@gmail.com>

14267

+

14268

+ Backport from mainline

14269

+ 2014-01-20 Uros Bizjak <ubizjak@gmail.com>

14270

+

14271

+ * config/i386/i386.c (ix86_avoid_lea_for_addr): Return false

14272

+ for SImode_address_operand operands, having only a REG argument.

14273

+

14274

+ 2014-01-20 Jakub Jelinek <jakub@redhat.com>

14275

+

14276

+ PR target/59880

14277

+ * config/i386/i386.c (ix86_avoid_lea_for_addr): Return false

14278

+ if operands[1] is a REG or ZERO_EXTEND of a REG.

14279

+

14280

+ 2014-01-18 Uros Bizjak <ubizjak@gmail.com>

14281

+ H.J. Lu <hongjiu.lu@intel.com>

14282

+

14283

+ PR target/59379

14284

+ * config/i386/i386.md (*lea<mode>): Zero-extend return register

14285

+ to DImode for zero-extended addresses.

14286

+

14287

+2014-01-21 Andrew Pinski <apinski@cavium.com>

14288

+ Steve Ellcey <sellcey@mips.com>

14289

+

14290

+ PR target/59462

14291

+ * config/mips/mips.c (mips_print_operand): Check operand mode instead

14292

+ of operator mode.

14293

+

14294

+2014-01-21 Andrey Belevantsev <abel@ispras.ru>

14295

+

14296

+ Backport from mainline

14297

+ 2013-12-23 Andrey Belevantsev <abel@ispras.ru>

14298

+

14299

+ PR rtl-optimization/57422

14300

+ * sel-sched.c (mark_unavailable_hard_regs): Fix typo when calling

14301

+ add_to_hard_reg_set.

14302

+

14303

+2014-01-20 Jakub Jelinek <jakub@redhat.com>

14304

+

14305

+ PR middle-end/59860

14306

+ * tree.h (fold_builtin_strcat): New prototype.

14307

+ * builtins.c (fold_builtin_strcat): No longer static. Add len

14308

+ argument, if non-NULL, don't call c_strlen. Optimize

14309

+ directly into __builtin_memcpy instead of __builtin_strcpy.

14310

+ (fold_builtin_2): Adjust fold_builtin_strcat caller.

14311

+ * gimple-fold.c (gimple_fold_builtin): Handle BUILT_IN_STRCAT.

14312

+

14313

+2014-01-20 Richard Biener <rguenther@suse.de>

14314

+

14315

+ PR middle-end/59860

14316

+ * builtins.c (fold_builtin_strcat): Remove case better handled

14317

+ by tree-ssa-strlen.c.

14318

+

14319

+2014-01-19 John David Anglin <danglin@gcc.gnu.org>

14320

+

14321

+ * config/pa/pa.c (pa_attr_length_millicode_call): Correct length of

14322

+ long non-pic millicode calls.

14323

+

14324

+2014-01-17 John David Anglin <danglin@gcc.gnu.org>

14325

+

14326

+ * config/pa/pa.c (pa_attr_length_indirect_call): Don't output a short

14327

+ call to $$dyncall when TARGET_LONG_CALLS is true.

14328

+

14329

+2014-01-17 H.J. Lu <hongjiu.lu@intel.com>

14330

+

14331

+ Backport from mainline

14332

+ 2014-01-14 H.J. Lu <hongjiu.lu@intel.com>

14333

+

14334

+ PR target/59794

14335

+ * config/i386/i386.c (type_natural_mode): Add a bool parameter

14336

+ to indicate if type is used for function return value. Warn

14337

+ ABI change if the vector mode isn't available for function

14338

+ return value.

14339

+ (ix86_function_arg_advance): Pass false to type_natural_mode.

14340

+ (ix86_function_arg): Likewise.

14341

+ (ix86_gimplify_va_arg): Likewise.

14342

+ (function_arg_32): Don't warn ABI change.

14343

+ (ix86_function_value): Pass true to type_natural_mode.

14344

+ (ix86_return_in_memory): Likewise.

14345

+ (ix86_struct_value_rtx): Removed.

14346

+ (TARGET_STRUCT_VALUE_RTX): Likewise.

14347

+

14348

+2014-01-17 Charles Baylis <charles.baylis@linaro.org>

14349

+

14350

+ Backport from mainline

14351

+ 2013-12-19 Charles Baylis <charles.baylis@linaro.org>

14352

+

14353

+ PR target/59142

14354

+ * config/arm/arm-ldmstm.ml: Use low_register_operand for Thumb

14355

+ patterns.

14356

+ * config/arm/ldmstm.md: Regenerate.

14357

+

14358

+ 2013-12-19 Charles Baylis <charles.baylis@linaro.org>

14359

+

14360

+ PR target/59142

14361

+ * config/arm/predicates.md (arm_hard_general_register_operand):

14362

+ New predicate.

14363

+ (arm_hard_register_operand): Remove.

14364

+ * config/arm/arm-ldmstm.ml: Use arm_hard_general_register_operand

14365

+ for all patterns.

14366

+ * config/arm/ldmstm.md: Regenerate.

14367

+

14368

+ 2013-12-19 Charles Baylis <charles.baylis@linaro.org>

14369

+

14370

+ PR target/59142

14371

+ * config/arm/predicates.md (vfp_hard_register_operand): New predicate.

14372

+ * config/arm/arm.md (vfp_pop_multiple_with_writeback): Use

14373

+ vfp_hard_register_operand.

14374

+

14375

+2014-01-17 Kugan Vivekanandarajah <kuganv@linaro.org>

14376

+

14377

+ Backport from mainline

14378

+ 2014-01-15 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org>

14379

+ Kugan Vivekanandarajah <kuganv@linaro.org>

14380

+

14381

+ PR target/59695

14382

+ * config/aarch64/aarch64.c (aarch64_build_constant): Fix incorrect

14383

+ truncation.

14384

+

14385

+2014-01-17 Terry Guo <terry.guo@arm.com>

14386

+

14387

+ PR target/59826

14388

+ * config/arm/arm.md (prefetch): Set insn type attribute to load1.

14389

+

14390

+2014-01-16 Jakub Jelinek <jakub@redhat.com>

14391

+

14392

+ PR target/59839

14393

+ * config/i386/i386.c (ix86_expand_builtin): If target doesn't

14394

+ satisfy operand 0 predicate for gathers, use a new pseudo as

14395

+ subtarget.

14396

+

14397

+2014-01-16 Richard Henderson <rth@redhat.com>

14398

+

14399

+ PR debug/54694

14400

+ * reginfo.c (global_regs_decl): Globalize.

14401

+ * rtl.h (global_regs_decl): Declare.

14402

+ * ira.c (do_reload): Diagnose frame_pointer_needed and it

14403

+ reserved via global_regs.

14404

+

14405

+2014-01-16 Peter Bergner <bergner@vnet.ibm.com>

14406

+

14407

+ Backport from mainline

14408

+ 2014-01-15 Uros Bizjak <ubizjak@gmail.com>

14409

+

14410

+ * config/i386/i386.c (ix86_hard_regno_mode_ok): Use

14411

+ VALID_AVX256_REG_OR_OI_MODE.

14412

+

14413

+ 2013-09-05 Peter Bergner <bergner@vnet.ibm.com>

14414

+

14415

+ PR target/58139

14416

+ * reginfo.c (choose_hard_reg_mode): Scan through all mode classes

14417

+ looking for widest mode.

14418

+

14419

+2014-01-16 Marek Polacek <polacek@redhat.com>

14420

+

14421

+ Backported from mainline

14422

+ 2014-01-16 Marek Polacek <polacek@redhat.com>

14423

+

14424

+ PR middle-end/59827

14425

+ * gimple-low.c (gimple_check_call_args): Don't use DECL_ARG_TYPE if

14426

+ it is error_mark_node.

14427

+

14428

+2014-01-15 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>

14429

+

14430

+ PR target/59803

14431

+ * config/s390/s390.c (s390_preferred_reload_class): Don't return

14432

+ ADDR_REGS for invalid symrefs in non-PIC code.

14433

+

14434

+2014-01-14 Uros Bizjak <ubizjak@gmail.com>

14435

+

14436

+ Revert:

14437

+ 2014-01-08 Uros Bizjak <ubizjak@gmail.com>

14438

+

14439

+ * config/i386/i386.c (ix86_data_alignment): Calculate max_align

14440

+ from prefetch_block tune setting.

14441

+

14442

+2014-01-13 Jakub Jelinek <jakub@redhat.com>

14443

+

14444

+ Backported from mainline

14445

+ 2014-01-10 Jakub Jelinek <jakub@redhat.com>

14446

+

14447

+ PR tree-optimization/59745

14448

+ * tree-predcom.c (tree_predictive_commoning_loop): Call

14449

+ free_affine_expand_cache if giving up because components is NULL.

14450

+

14451

+2014-01-10 Yufeng Zhang <yufeng.zhang@arm.com>

14452

+

14453

+ * config/arm/arm.c (arm_expand_neon_args): Call expand_expr

14454

+ with EXPAND_MEMORY for NEON_ARG_MEMORY; check if the returned

14455

+ rtx is const0_rtx or not.

14456

+

14457

+2014-01-10 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>

14458

+

14459

+ * config/s390/s390.c (s390_expand_tbegin): Remove jump over CC

14460

+ extraction in good case.

14461

+

14462

+2014-01-10 Huacai Chen <chenhc@lemote.com>

14463

+

14464

+ * config/mips/driver-native.c (host_detect_local_cpu): Handle new

14465

+ kernel strings for Loongson-2E/2F/3A.

14466

+

14467

+2014-01-10 Richard Biener <rguenther@suse.de>

14468

+

14469

+ PR tree-optimization/59715

14470

+ * tree-flow.h (split_critical_edges): Declare.

14471

+ * tree-cfg.c (split_critical_edges): Export.

14472

+ * tree-ssa-sink.c (execute_sink_code): Split critical edges.

14473

+

14474

+2014-01-09 Richard Sandiford <rdsandiford@googlemail.com>

14475

+

14476

+ * config/mips/mips.h (ISA_HAS_WSBH): Define.

14477

+ * config/mips/mips.md (UNSPEC_WSBH, UNSPEC_DSBH, UNSPEC_DSHD): New

14478

+ constants.

14479

+ (bswaphi2, bswapsi2, bswapdi2, wsbh, dsbh, dshd): New patterns.

14480

+

14481

+2014-01-09 Richard Sandiford <rdsandiford@googlemail.com>

14482

+

14483

+ PR rtl-optimization/59137

14484

+ * reorg.c (steal_delay_list_from_target): Call update_block for

14485

+ elided insns.

14486

+ (steal_delay_list_from_fallthrough, relax_delay_slots): Likewise.

14487

+

14488

+2014-01-09 Richard Sandiford <rdsandiford@googlemail.com>

14489

+

14490

+ Revert:

14491

+ 2012-10-07 Richard Sandiford <rdsandiford@googlemail.com>

14492

+

14493

+ * config/mips/mips.c (mips_truncated_op_cost): New function.

14494

+ (mips_rtx_costs): Adjust test for BADDU.

14495

+ * config/mips/mips.md (*baddu_di<mode>): Push truncates to operands.

14496

+

14497

+ 2012-10-02 Richard Sandiford <rdsandiford@googlemail.com>

14498

+

14499

+ * config/mips/mips.md (*baddu_si_eb, *baddu_si_el): Merge into...

14500

+ (*baddu_si): ...this new pattern.

14501

+

14502

+2014-01-09 Richard Biener <rguenther@suse.de>

14503

+

14504

+ Backport from mainline

14505

+ 2013-11-18 Richard Biener <rguenther@suse.de>

14506

+

14507

+ PR tree-optimization/59125

14508

+ PR tree-optimization/54570

14509

+ * tree-ssa-sccvn.c (copy_reference_ops_from_ref): When inlining

14510

+ is not complete do not treat component-references with offset zero

14511

+ but different fields as equal.

14512

+ * tree-object-size.c: Include tree-phinodes.h and ssa-iterators.h.

14513

+ (compute_object_sizes): Apply TLC. Propagate the constant

14514

+ results into all uses and fold their stmts.

14515

+ * passes.def (pass_all_optimizations): Move pass_object_sizes

14516

+ after the first pass_forwprop and before pass_fre.

14517

+

14518

+ 2013-12-03 Jakub Jelinek <jakub@redhat.com>

14519

+

14520

+ PR tree-optimization/59362

14521

+ * tree-object-size.c (object_sizes): Change into array of

14522

+ vec<unsigned HOST_WIDE_INT>.

14523

+ (compute_builtin_object_size): Check computed bitmap for

14524

+ non-NULL instead of object_sizes. Call safe_grow on object_sizes

14525

+ vector if new SSA_NAMEs appeared.

14526

+ (init_object_sizes): Check computed bitmap for non-NULL.

14527

+ Call safe_grow on object_sizes elements instead of initializing

14528

+ it with XNEWVEC.

14529

+ (fini_object_sizes): Call release on object_sizes elements, don't

14530

+ set it to NULL.

14531

+

14532

+2014-01-09 Richard Earnshaw <rearnsha@arm.com>

14533

+

14534

+ PR rtl-optimization/54300

14535

+ * regcprop.c (copyprop_hardreg_forward_1): Ensure any unused

14536

+ outputs in a single-set are killed from the value chains.

14537

+

14538

+2014-01-09 Jakub Jelinek <jakub@redhat.com>

14539

+

14540

+ PR rtl-optimization/59724

14541

+ * ifcvt.c (cond_exec_process_if_block): Don't call

14542

+ flow_find_head_matching_sequence with 0 longest_match.

14543

+ * cfgcleanup.c (flow_find_head_matching_sequence): Count even

14544

+ non-active insns if !stop_after.

14545

+ (try_head_merge_bb): Revert 2014-01-07 changes.

14546

+

14547

+2014-01-09 Hans-Peter Nilsson <hp@axis.com>

14548

+

14549

+ Backport from mainline

14550

+ 2013-12-23 Hans-Peter Nilsson <hp@axis.com>

14551

+

14552

+ PR middle-end/59584

14553

+ * config/cris/predicates.md (cris_nonsp_register_operand):

14554

+ New define_predicate.

14555

+ * config/cris/cris.md: Replace register_operand with

14556

+ cris_nonsp_register_operand for destinations in all

14557

+ define_splits where a register is set more than once.

14558

+

14559

+2014-01-08 H.J. Lu <hongjiu.lu@intel.com>

14560

+

14561

+ Backport from mainline

14562

+ 2013-12-25 H.J. Lu <hongjiu.lu@intel.com>

14563

+

14564

+ PR target/59587

14565

+ * config/i386/i386.c (struct ptt): Add a field for processor name.

14566

+ (processor_target_table): Sync with processor_type. Add

14567

+ processor names.

14568

+ (cpu_names): Removed.

14569

+ (ix86_option_override_internal): Default x_ix86_tune_string

14570

+ to processor_target_table[TARGET_CPU_DEFAULT].name.

14571

+ (ix86_function_specific_print): Assert arch and tune <

14572

+ PROCESSOR_max. Use processor_target_table to print arch and

14573

+ tune names.

14574

+ * config/i386/i386.h (TARGET_CPU_DEFAULT): Default to

14575

+ PROCESSOR_GENERIC32.

14576

+ (target_cpu_default): Removed.

14577

+ (processor_type): Reordered.

14578

+

14579

+2014-01-08 Uros Bizjak <ubizjak@gmail.com>

14580

+

14581

+ Backport from mainline

14582

+ 2014-01-05 Uros Bizjak <ubizjak@gmail.com>

14583

+

14584

+ * config/i386/i386.c (ix86_data_alignment): Calculate max_align

14585

+ from prefetch_block tune setting.

14586

+ (nocona_cost): Correct size of prefetch block to 64.

14587

+

14588

+2014-01-08 Martin Jambor <mjambor@suse.cz>

14589

+

14590

+ PR ipa/59610

14591

+ * ipa-prop.c (ipa_compute_jump_functions): Bail out if not optimizing.

14592

+ (parm_preserved_before_stmt_p): Assume modification present when not

14593

+ optimizing.

14594

+

14595

+2014-01-07 John David Anglin <danglin@gcc.gnu.org>

14596

+

14597

+ PR target/59652

14598

+ * config/pa/pa.c (pa_legitimate_address_p): Return false before reload

14599

+ for 14-bit register offsets when INT14_OK_STRICT is false.

14600

+

14601

+2014-01-07 Roland Stigge <stigge@antcom.de>

14602

+ Michael Meissner <meissner@linux.vnet.ibm.com>

14603

+

14604

+ PR 57386/target

14605

+ * config/rs6000/rs6000.c (rs6000_legitimate_offset_address_p):

14606

+ Only check TFmode for SPE constants. Don't check TImode or TDmode.

14607

+

14608

+2014-01-07 Jakub Jelinek <jakub@redhat.com>

14609

+

14610

+ PR rtl-optimization/58668

14611

+ * cfgcleanup.c (flow_find_cross_jump): Don't count

14612

+ any jumps if dir_p is NULL. Remove p1 variable and make USE/CLOBBER

14613

+ check consistent with other places.

14614

+ (flow_find_head_matching_sequence): Don't count USE or CLOBBER insns.

14615

+ (try_head_merge_bb): Adjust for the flow_find_head_matching_sequence

14616

+ counting change.

14617

+ * ifcvt.c (count_bb_insns): Don't count USE or CLOBBER insns.

14618

+

14619

+2014-01-07 Mike Stump <mikestump@comcast.net>

14620

+ Jakub Jelinek <jakub@redhat.com>

14621

+

14622

+ PR pch/59436

14623

+ * tree.h (struct tree_optimization_option): Change optabs

14624

+ type from unsigned char * to void *.

14625

+ * optabs.c (init_tree_optimization_optabs): Adjust

14626

+ TREE_OPTIMIZATION_OPTABS initialization.

14627

+

14628

+2014-01-07 Jakub Jelinek <jakub@redhat.com>

14629

+

14630

+ Backported from mainline

14631

+ 2013-12-16 Jakub Jelinek <jakub@redhat.com>

14632

+

14633

+ PR middle-end/58956

14634

+ PR middle-end/59470

14635

+ * gimple.h (walk_stmt_load_store_addr_fn): New typedef.

14636

+ (walk_stmt_load_store_addr_ops, walk_stmt_load_store_ops): Use it

14637

+ for callback params.

14638

+ * gimple.c (walk_stmt_load_store_ops): Likewise.

14639

+ (walk_stmt_load_store_addr_ops): Likewise. Adjust all callback

14640

+ calls to supply the gimple operand containing the base tree

14641

+ as an extra argument.

14642

+ * tree-ssa-ter.c (find_ssaname, find_ssaname_in_store): New helper

14643

+ functions.

14644

+ (find_replaceable_in_bb): For calls or GIMPLE_ASM, only set

14645

+ same_root_var if USE is used somewhere in the stores of the stmt.

14646

+ * ipa-prop.c (visit_ref_for_mod_analysis): Remove name of the stmt

14647

+ argument and ATTRIBUTE_UNUSED, add another unnamed tree argument.

14648

+ * ipa-pure-const.c (check_load, check_store, check_ipa_load,

14649

+ check_ipa_store): Likewise.

14650

+ * gimple.c (gimple_ior_addresses_taken_1): Likewise.

14651

+ * ipa-split.c (test_nonssa_use, mark_nonssa_use): Likewise.

14652

+ (verify_non_ssa_vars, visit_bb): Adjust their callers.

14653

+ * cfgexpand.c (add_scope_conflicts_1): Use

14654

+ walk_stmt_load_store_addr_fn type for visit variable.

14655

+ (visit_op, visit_conflict): Remove name of the stmt

14656

+ argument and ATTRIBUTE_UNUSED, add another unnamed tree argument.

14657

+ * tree-sra.c (asm_visit_addr): Likewise. Remove name of the data

14658

+ argument and ATTRIBUTE_UNUSED.

14659

+ * cgraphbuild.c (mark_address, mark_load, mark_store): Add another

14660

+ unnamed tree argument.

14661

+

14662

+2014-01-03 Andreas Schwab <schwab@linux-m68k.org>

14663

+

14664

+ * config/m68k/m68k.c (handle_move_double): Handle pushes with

14665

+ overlapping registers also for registers other than the stack

14666

+ pointer.

14667

+

14668

+2014-01-03 Jakub Jelinek <jakub@redhat.com>

14669

+

14670

+ PR target/59625

14671

+ * config/i386/i386.c (ix86_avoid_jump_mispredicts): Don't consider

14672

+ asm goto as jump.

14673

+

14674

+2014-01-01 Jakub Jelinek <jakub@redhat.com>

14675

+

14676

+ PR rtl-optimization/59647

14677

+ * cse.c (cse_process_notes_1): Don't substitute negative VOIDmode

14678

+ new_rtx into UNSIGNED_FLOAT rtxes.

14679

+

14680

+2013-12-28 Eric Botcazou <ebotcazou@adacore.com>

14681

+

14682

+ * doc/invoke.texi (output file options): Document -fada-spec-parent.

14683

+

14684

+2013-12-26 Uros Bizjak <ubizjak@gmail.com>

14685

+

14686

+ * config/i386/driver-i386.c (decode_caches_intel): Add missing entries.

14687

+

14688

+2013-12-20 Jakub Jelinek <jakub@redhat.com>

14689

+

14690

+ PR c++/59255

14691

+ Backported from mainline

14692

+ 2013-08-19 Dehao Chen <dehao@google.com>

14693

+

14694

+ * value-prof.c (gimple_ic): Fix the bug of adding EH edge.

14695

+

14696

+2013-12-19 James Greenhalgh <james.greenhalgh@arm.com>

14697

+

14698

+ Backport from Mainline.

14699

+ 2013-05-01 James Greenhalgh <james.greenhalgh@arm.com>

14700

+

14701

+ * config/aarch64/aarch64-simd-builtins.def (cmhs): Rename to...

14702

+ (cmgeu): ...This.

14703

+ (cmhi): Rename to...

14704

+ (cmgtu): ...This.

14705

+ * config/aarch64/aarch64-simd.md

14706

+ (simd_mode): Add SF.

14707

+ (aarch64_vcond_internal): Use new names for unsigned comparison insns.

14708

+ (aarch64_cm<optab><mode>): Rewrite to not use UNSPECs.

14709

+ * config/aarch64/aarch64.md (*cstore<mode>_neg): Rename to...

14710

+ (cstore<mode>_neg): ...This.

14711

+ * config/aarch64/iterators.md

14712

+ (VALLF): new.

14713

+ (unspec): Remove UNSPEC_CM<EQ, LE, LT, GE, GT, HS, HI, TST>.

14714

+ (COMPARISONS): New.

14715

+ (UCOMPARISONS): Likewise.

14716

+ (optab): Add missing comparisons.

14717

+ (n_optab): New.

14718

+ (cmp_1): Likewise.

14719

+ (cmp_2): Likewise.

14720

+ (CMP): Likewise.

14721

+ (cmp): Remove.

14722

+ (VCMP_S): Likewise.

14723

+ (VCMP_U): Likewise.

14724

+ (V_cmp_result): Add DF, SF modes.

14725

+ (v_cmp_result): Likewise.

14726

+ (v): Likewise.

14727

+ (vmtype): Likewise.

14728

+ * config/aarch64/predicates.md (aarch64_reg_or_fp_zero): New.

14729

+

14730

+ Partial Backport from mainline.

14731

+ 2013-05-01 James Greenhalgh <james.greenhalgh@arm.com>

14732

+

14733

+ * config/aarch64/arm_neon.h

14734

+ (vc<eq, lt, le, gt, ge, tst><qsd>_<u><8,16,32,64>): Remap

14735

+ to builtins or C as appropriate.

14736

+

14737

+2013-12-19 Dominik Vogt <vogt@linux.vnet.ibm.com>

14738

+ Andreas Krebbel <Andreas.Krebbel@de.ibm.com>

14739

+

14740

+ Backport from mainline

14741

+ 2013-12-19 Dominik Vogt <vogt@linux.vnet.ibm.com>

14742

+ * config/s390/s390.c (s390_hotpatch_trampoline_halfwords_default): New

14743

+ constant

14744

+ (s390_hotpatch_trampoline_halfwords_max): New constant

14745

+ (s390_hotpatch_trampoline_halfwords): New static variable

14746

+ (get_hotpatch_attribute): New function

14747

+ (s390_handle_hotpatch_attribute): New function

14748

+ (s390_attribute_table): New target specific attribute table to implement

14749

+ the hotpatch attribute

14750

+ (s390_option_override): Parse hotpatch options

14751

+ (s390_function_num_hotpatch_trampoline_halfwords): New function

14752

+ (s390_can_inline_p): Implement target hook to

14753

+ suppress hotpatching for explicitly inlined functions

14754

+ (s390_asm_output_function_label): Generate hotpatch prologue

14755

+ (TARGET_ATTRIBUTE_TABLE): Define to implement target attribute table

14756

+ (TARGET_CAN_INLINE_P): Define to implement target hook

14757

+ * config/s390/s390.opt (mhotpatch): New options -mhotpatch, -mhotpatch=

14758

+ * config/s390/s390-protos.h (s390_asm_output_function_label): Add

14759

+ prototype

14760

+ * config/s390/s390.h (ASM_OUTPUT_FUNCTION_LABEL): Target specific

14761

+ function label generation for hotpatching

14762

+ (FUNCTION_BOUNDARY): Align functions to eight bytes

14763

+ * doc/extend.texi: Document hotpatch attribute

14764

+ * doc/invoke.texi: Document -mhotpatch option

14765

+

14766

+2013-12-18 Eric Botcazou <ebotcazou@adacore.com>

14767

+

14768

+ * config/arm/arm.c (arm_expand_epilogue_apcs_frame): Fix thinko.

14769

+

14770

+2013-12-12 Vladimir Makarov <vmakarov@redhat.com>

14771

+

14772

+ PR middle-end/59470

14773

+ * lra-coalesce.c (lra_coalesce): Invalidate inheritance pseudo

14774

+ values if necessary.

14775

+

14776

+2013-12-12 Jakub Jelinek <jakub@redhat.com>

14777

+

14778

+ PR libgomp/59467

14779

+ * gimplify.c (omp_check_private): Add copyprivate argument, if it

14780

+ is true, don't check omp_privatize_by_reference.

14781

+ (gimplify_scan_omp_clauses): For OMP_CLAUSE_COPYPRIVATE verify

14782

+ decl is private in outer context. Adjust omp_check_private caller.

14783

+

14784

+2013-12-10 Eric Botcazou <ebotcazou@adacore.com>

14785

+

14786

+ PR rtl-optimization/58295

14787

+ * simplify-rtx.c (simplify_truncation): Restrict the distribution for

14788

+ WORD_REGISTER_OPERATIONS targets.

14789

+

14790

+2013-12-10 Kai Tietz <ktietz@redhat.com>

14791

+

14792

+ PR target/56807

14793

+ * config/i386/i386.c (ix86_expand_prologue): Address saved

14794

+ registers stack-relative, not via frame-pointer.

14795

+

14796

+2013-12-09 Alan Modra <amodra@gmail.com>

14797

+

14798

+ Apply from mainline

14799

+ 2013-12-05 Alan Modra <amodra@gmail.com>

14800

+ * configure.ac (BUILD_CXXFLAGS) Don't use ALL_CXXFLAGS for

14801

+ build != host.

14802

+ <recursive call for build != host>: Clear GMPINC. Don't bother

14803

+ saving CFLAGS.

14804

+ * configure: Regenerate.

14805

+

14806

+2013-12-08 Uros Bizjak <ubizjak@gmail.com>

14807

+

14808

+ Backport from mainline

14809

+ 2013-12-06 Uros Bizjak <ubizjak@gmail.com>

14810

+

14811

+ PR target/59405

14812

+ * config/i386/i386.c (type_natural_mode): Properly handle

14813

+ size 8 for !TARGET_64BIT.

14814

+

14815

+2013-12-07 Ralf Corsépius <ralf.corsepius@rtems.org>

14816

+

14817

+ * config.gcc (microblaze*-*-rtems*): Add TARGET_BIG_ENDIAN_DEFAULT.

14818

+

14819

+2013-12-06 Jakub Jelinek <jakub@redhat.com>

14820

+

14821

+ PR tree-optimization/59388

14822

+ * tree-ssa-reassoc.c (update_range_test): If op == range->exp,

14823

+ gimplify tem after stmt rather than before it.

14824

+

14825

+2013-12-06 Oleg Endo <olegendo@gcc.gnu.org>

14826

+

14827

+ Backport from mainline

14828

+ 2013-11-26 Oleg Endo <olegendo@gcc.gnu.org>

14829

+

14830

+ PR target/58314

14831

+ PR target/50751

14832

+ * config/sh/sh.c (max_mov_insn_displacement, disp_addr_displacement):

14833

+ Prefix function names with 'sh_'. Make them non-static.

14834

+ * config/sh/sh-protos.h (sh_disp_addr_displacement,

14835

+ sh_max_mov_insn_displacement): Add declarations.

14836

+ * config/sh/constraints.md (Q): Reject QImode.

14837

+ (Sdd): Use match_code "mem".

14838

+ (Snd): Fix erroneous matching of non-memory operands.

14839

+ * config/sh/predicates.md (short_displacement_mem_operand): New

14840

+ predicate.

14841

+ (general_movsrc_operand): Disallow PC relative QImode loads.

14842

+ * config/sh/sh.md (*mov<mode>_reg_reg): Remove it.

14843

+ (*movqi, *movhi): Merge both insns into...

14844

+ (*mov<mode>): ... this new insn. Replace generic 'm' constraints with

14845

+ 'Snd' and 'Sdd' constraints. Calculate insn length dynamically based

14846

+ on the operand types.

14847

+

14848

+2013-12-06 Richard Biener <rguenther@suse.de>

14849

+

14850

+ Backport from mainline

14851

+ 2013-11-29 Richard Biener <rguenther@suse.de>

14852

+

14853

+ PR tree-optimization/59334

14854

+ * tree-ssa-dce.c (eliminate_unnecessary_stmts): Fix bug

14855

+ in previous commit.

14856

+

14857

+ 2013-11-28 Richard Biener <rguenther@suse.de>

14858

+

14859

+ PR tree-optimization/59330

14860

+ * tree-ssa-dce.c (eliminate_unnecessary_stmts): Simplify

14861

+ and fix delayed marking of free calls not necessary.

14862

+

14863

+2013-12-06 Richard Biener <rguenther@suse.de>

14864

+

14865

+ Backport from mainline

14866

+ 2013-11-27 Richard Biener <rguenther@suse.de>

14867

+

14868

+ PR tree-optimization/59288

14869

+ * tree-vect-loop.c (get_initial_def_for_induction): Do not

14870

+ re-analyze the PHI but use STMT_VINFO_LOOP_PHI_EVOLUTION_PART.

14871

+

14872

+ 2013-11-19 Richard Biener <rguenther@suse.de>

14873

+

14874

+ PR tree-optimization/59164

14875

+ * tree-vect-loop.c (vect_analyze_loop_operations): Adjust

14876

+ check whether we can create an epilogue loop to reflect the

14877

+ cases where we create one.

14878

+

14879

+ 2013-09-05 Richard Biener <rguenther@suse.de>

14880

+

14881

+ PR tree-optimization/58137

14882

+ * tree-vect-stmts.c (get_vectype_for_scalar_type_and_size):

14883

+ Do not create vectors of pointers.

14884

+ * tree-vect-loop.c (get_initial_def_for_induction): Use proper

14885

+ types for the components of the vector initializer.

14886

+ * tree-cfg.c (verify_gimple_assign_binary): Remove special-casing

14887

+ allowing pointer vectors with PLUS_EXPR/MINUS_EXPR.

14888

+

14889

+2013-12-06 Oleg Endo <olegendo@gcc.gnu.org>

14890

+

14891

+ PR target/51244

14892

+ PR target/59343

14893

+ * config/sh/sh.md (*cbranch_t): Check that there are no labels between

14894

+ the s1 insn and the testing insn. Remove REG_DEAD note from s1 insn.

14895

+

14896

+2013-12-05 Richard Biener <rguenther@suse.de>

14897

+

14898

+ Backport from mainline

14899

+ 2013-11-19 Richard Biener <rguenther@suse.de>

14900

+

14901

+ PR middle-end/58956

14902

+ * tree-ssa-ter.c (find_replaceable_in_bb): Avoid forwarding

14903

+ loads into stmts that may clobber it.

14904

+

14905

+2013-12-04 Jakub Jelinek <jakub@redhat.com>

14906

+

14907

+ PR rtl-optimization/58726

14908

+ * combine.c (force_to_mode): Fix comment typo. Don't destructively

14909

+ modify x for ROTATE, ROTATERT and IF_THEN_ELSE.

14910

+

14911

+2013-12-04 Jakub Jelinek <jakub@redhat.com>

14912

+ Uros Bizjak <ubizjak@gmail.com>

14913

+

14914

+ PR target/59163

14915

+ * config/i386/i386.c (ix86_legitimate_combined_insn): If for

14916

+ !TARGET_AVX there is misaligned MEM operand with vector mode

14917

+ and get_attr_ssememalign is 0, return false.

14918

+ (ix86_expand_special_args_builtin): Add get_pointer_alignment

14919

+ computed alignment and for non-temporal loads/stores also

14920

+ at least GET_MODE_ALIGNMENT as MEM_ALIGN.

14921

+ * config/i386/sse.md

14922

+ (<sse>_loadu<ssemodesuffix><avxsizesuffix>,

14923

+ <sse>_storeu<ssemodesuffix><avxsizesuffix>,

14924

+ <sse2>_loaddqu<avxsizesuffix>,

14925

+ <sse2>_storedqu<avxsizesuffix>, <sse3>_lddqu<avxsizesuffix>,

14926

+ sse_vmrcpv4sf2, sse_vmrsqrtv4sf2, sse2_cvtdq2pd, sse_movhlps,

14927

+ sse_movlhps, sse_storehps, sse_loadhps, sse_loadlps,

14928

+ *vec_interleave_highv2df, *vec_interleave_lowv2df,

14929

+ *vec_extractv2df_1_sse, sse2_loadhpd, sse2_loadlpd, sse2_movsd,

14930

+ sse4_1_<code>v8qiv8hi2, sse4_1_<code>v4qiv4si2,

14931

+ sse4_1_<code>v4hiv4si2, sse4_1_<code>v2qiv2di2,

14932

+ sse4_1_<code>v2hiv2di2, sse4_1_<code>v2siv2di2, sse4_2_pcmpestr,

14933

+ *sse4_2_pcmpestr_unaligned, sse4_2_pcmpestri, sse4_2_pcmpestrm,

14934

+ sse4_2_pcmpestr_cconly, sse4_2_pcmpistr, *sse4_2_pcmpistr_unaligned,

14935

+ sse4_2_pcmpistri, sse4_2_pcmpistrm, sse4_2_pcmpistr_cconly): Add

14936

+ ssememalign attribute.

14937

+ * config/i386/i386.md (ssememalign): New define_attr.

14938

+

14939

+2013-12-03 Jakub Jelinek <jakub@redhat.com>

14940

+

14941

+ PR middle-end/59011

14942

+ * gimplify.c (nonlocal_vla_vars): New variable.

14943

+ (gimplify_var_or_parm_decl): Put VAR_DECLs for VLAs into

14944

+ nonlocal_vla_vars chain.

14945

+ (gimplify_body): Call declare_vars on nonlocal_vla_vars chain

14946

+ if outer_bind has DECL_INITIAL (current_function_decl) block.

14947

+

14948

+ PR target/58864

14949

+ * optabs.c (emit_conditional_move): Save and restore

14950

+ pending_stack_adjust and stack_pointer_delta if cmove can't be used.

14951

+

14952

+2013-12-02 Jakub Jelinek <jakub@redhat.com>

14953

+

14954

+ PR tree-optimization/59358

14955

+ * tree-vrp.c (union_ranges): To check for the partially

14956

+ overlapping ranges or adjacent ranges, also compare *vr0max

14957

+ with vr1max.

14958

+

14959

+2013-12-02 Richard Biener <rguenther@suse.de>

14960

+

14961

+ PR tree-optimization/59139

14962

+ * tree-ssa-loop-niter.c (chain_of_csts_start): Properly match

14963

+ code in get_val_for.

14964

+ (get_val_for): Use gcc_checking_asserts.

14965

+

14966

+2013-11-27 Tom de Vries <tom@codesourcery.com>

14967

+ Marc Glisse <marc.glisse@inria.fr>

14968

+

14969

+ PR middle-end/59037

14970

+ * fold-const.c (fold_indirect_ref_1): Don't create out-of-bounds

14971

+ BIT_FIELD_REF.

14972

+ * gimplify.c (gimple_fold_indirect_ref): Same.

14973

+

14974

+2013-12-01 Eric Botcazou <ebotcazou@adacore.com>

14975

+

14976

+ * config/i386/winnt.c (i386_pe_asm_named_section): Be prepared for an

14977

+ identifier node.

14978

+

14979

+2013-12-01 Bernd Edlinger <bernd.edlinger@hotmail.de>

14980

+

14981

+ * expr.c (emit_group_store): Fix off-by-one BITFIELD_END argument.

14982

+

14983

+2013-11-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com>

14984

+

14985

+ Backport from mainline

14986

+ 2013-11-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com>

14987

+

14988

+ * config/arm/iterators.md (vrint_conds): New int attribute.

14989

+ * config/arm/vfp.md (<vrint_pattern><SDF:mode>2): Set conds attribute.

14990

+ (smax<mode>3): Likewise.

14991

+ (smin<mode>3): Likewise.

14992

+

14993

+2013-11-28 Uros Bizjak <ubizjak@gmail.com>

14994

+

14995

+ Backport from mainline

14996

+ 2013-11-27 Uros Bizjak <ubizjak@gmail.com>

14997

+ Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>

14998

+

14999

+ PR target/56788

15000

+ * gcc.target/i386/xop-frczX.c: New test.

15001

+

15002

+2013-11-28 Terry Guo <terry.guo@arm.com>

15003

+

15004

+ Backport mainline r205391

15005

+ 2013-11-26 Terry Guo <terry.guo@arm.com>

15006

+

15007

+ * config/arm/arm.c (require_pic_register): Handle high pic base

15008

+ register for thumb-1.

15009

+ (arm_load_pic_register): Also initialize high pic base register.

15010

+ * doc/invoke.texi: Update documentation for option -mpic-register.

15011

+

15012

+2013-11-27 Jakub Jelinek <jakub@redhat.com>

15013

+

15014

+ Backported from mainline

15015

+ 2013-11-26 Jakub Jelinek <jakub@redhat.com>

15016

+

15017

+ PR tree-optimization/59014

15018

+ * tree-vrp.c (register_edge_assert_for_1): Don't look

15019

+ through conversions from non-integral types or through

15020

+ narrowing conversions.

15021

+

15022

+2013-11-27 Eric Botcazou <ebotcazou@adacore.com>

15023

+

15024

+ PR middle-end/59138

15025

+ * expr.c (emit_group_store): Don't write past the end of the structure.

15026

+ (store_bit_field): Fix formatting.

15027

+

15028

+2013-11-24 Sebastian Huber <sebastian.huber@embedded-brains.de>

15029

+

15030

+ Backport from mainline

15031

+ 2013-09-17 Sebastian Huber <sebastian.huber@embedded-brains.de>

15032

+

15033

+ * config/sparc/t-rtems: Add leon3 multilibs.

15034

+

15035

+2013-11-24 Sebastian Huber <sebastian.huber@embedded-brains.de>

15036

+

15037

+ Backport from mainline

15038

+ 2013-08-09 Eric Botcazou <ebotcazou@adacore.com>

15039

+

15040

+ * configure.ac: Add GAS check for LEON instructions on SPARC.

15041

+ * configure: Regenerate.

15042

+ * config.in: Likewise.

15043

+ * config.gcc (with_cpu): Remove sparc-leon*-* and deal with LEON in the

15044

+ sparc*-*-* block.

15045

+ * config/sparc/sparc.opt (LEON, LEON3): New masks.

15046

+ * config/sparc/sparc.h (ASM_CPU32_DEFAULT_SPEC): Set to AS_LEON_FLAG

15047

+ for LEON or LEON3.

15048

+ (ASM_CPU_SPEC): Pass AS_LEON_FLAG if -mcpu=leon or -mcpu=leon3.

15049

+ (AS_LEON_FLAG): New macro.

15050

+ * config/sparc/sparc.c (sparc_option_override): Set MASK_LEON for leon

15051

+ and MASK_LEON3 for leon3 and unset them if HAVE_AS_LEON is not defined.

15052

+ Deal with LEON and LEON3 for the memory model.

15053

+ * config/sparc/sync.md (atomic_compare_and_swap<mode>): Enable if LEON3

15054

+ (atomic_compare_and_swap<mode>_1): Likewise.

15055

+ (*atomic_compare_and_swap<mode>_1): Likewise.

15056

+

15057

+2013-11-24 Sebastian Huber <sebastian.huber@embedded-brains.de>

15058

+

15059

+ Backport from mainline

15060

+ 2013-07-23 Eric Botcazou <ebotcazou@adacore.com>

15061

+

15062

+ * doc/invoke.texi (SPARC Options): Document new leon3 processor value.

15063

+

15064

+2013-11-24 Sebastian Huber <sebastian.huber@embedded-brains.de>

15065

+

15066

+ Backport from mainline

15067

+ 2013-07-22 Eric Botcazou <ebotcazou@adacore.com>

15068

+

15069

+ * config.gcc (sparc*-*-*): Accept leon3 processor.

15070

+ (sparc-leon*-*): Merge with sparc*-*-* and add leon3 support.

15071

+ * doc/invoke.texi (SPARC Options): Adjust -mfix-ut699 entry.

15072

+ * config/sparc/sparc-opts.h (enum processor_type): Add PROCESSOR_LEON3.

15073

+ * config/sparc/sparc.opt (enum processor_type): Add leon3.

15074

+ (mfix-ut699): Adjust comment.

15075

+ * config/sparc/sparc.h (TARGET_CPU_leon3): New define.

15076

+ (CPP_CPU32_DEFAULT_SPEC): Add leon3 support.

15077

+ (CPP_CPU_SPEC): Likewise.

15078

+ (ASM_CPU_SPEC): Likewise.

15079

+ * config/sparc/sparc.c (leon3_cost): New constant.

15080

+ (sparc_option_override): Add leon3 support.

15081

+ (mem_ref): New function.

15082

+ (sparc_gate_work_around_errata): Return true if -mfix-ut699 is enabled.

15083

+ (sparc_do_work_around_errata): Look into the instruction in the delay

15084

+ slot and adjust accordingly. Add fix for the data cache nullify issues

15085

+ of the UT699. Change insertion position for the NOP.

15086

+ * config/sparc/leon.md (leon_fpalu, leon_fpmds, write_buf): Delete.

15087

+ (leon3_load): New reservation.

15088

+ (leon_store): Bump latency to 2.

15089

+ (grfpu): New automaton.

15090

+ (grfpu_alu): New unit.

15091

+ (grfpu_ds): Likewise.

15092

+ (leon_fp_alu): Adjust.

15093

+ (leon_fp_mult): Delete.

15094

+ (leon_fp_div): Split into leon_fp_divs and leon_fp_divd.

15095

+ (leon_fp_sqrt): Split into leon_fp_sqrts and leon_fp_sqrtd.

15096

+ * config/sparc/sparc.md (cpu): Add leon3.

15097

+ * config/sparc/sync.md (atomic_exchangesi): Disable if -mfix-ut699.

15098

+ (swapsi): Likewise.

15099

+ (atomic_test_and_set): Likewise.

15100

+ (ldstub): Likewise.

15101

+

15102

+2013-11-24 Sebastian Huber <sebastian.huber@embedded-brains.de>

15103

+

15104

+ Backport from mainline

15105

+ 2013-04-10 Steven Bosscher <steven@gcc.gnu.org>

15106

+

15107

+ * config/sparc/sparc.c: Include tree-pass.h.

15108

+ (TARGET_MACHINE_DEPENDENT_REORG): Do not redefine.

15109

+ (sparc_reorg): Rename to sparc_do_work_around_errata. Move to

15110

+ head of file. Change return type. Split off gate function.

15111

+ (sparc_gate_work_around_errata): New function.

15112

+ (pass_work_around_errata): New pass definition.

15113

+ (insert_pass_work_around_errata) New pass insert definition to

15114

+ insert pass_work_around_errata just after delayed-branch scheduling.

15115

+ (sparc_option_override): Insert the pass.

15116

+ * config/sparc/t-sparc (sparc.o): Add TREE_PASS_H dependence.

15117

+

15118

+2013-11-24 Sebastian Huber <sebastian.huber@embedded-brains.de>

15119

+

15120

+ Backport from mainline

15121

+ 2013-05-28 Eric Botcazou <ebotcazou@adacore.com>

15122

+

15123

+ * doc/invoke.texi (SPARC Options): Document -mfix-ut699.

15124

+ * builtins.c (expand_builtin_mathfn) <BUILT_IN_SQRT>: Try to widen the

15125

+ mode if the instruction isn't available in the original mode.

15126

+ * config/sparc/sparc.opt (mfix-ut699): New option.

15127

+ * config/sparc/sparc.md (muldf3_extend): Disable if -mfix-ut699.

15128

+ (divdf3): Turn into expander.

15129

+ (divdf3_nofix): New insn.

15130

+ (divdf3_fix): Likewise.

15131

+ (divsf3): Disable if -mfix-ut699.

15132

+ (sqrtdf2): Turn into expander.

15133

+ (sqrtdf2_nofix): New insn.

15134

+ (sqrtdf2_fix): Likewise.

15135

+ (sqrtsf2): Disable if -mfix-ut699.

15136

+

15137

+2013-11-22 Eric Botcazou <ebotcazou@adacore.com>

15138

+

15139

+ * print-rtl.c (print_rtx) <case MEM>: Output a space if no MEM_EXPR.

15140

+

15141

+2013-11-21 Zhenqiang Chen <zhenqiang.chen@linaro.org>

15142

+

15143

+ PR bootstrap/57683

15144

+ Backport from mainline: r197467 and r198999.

15145

+ 2013-04-03 Jeff Law <law@redhat.com>

15146

+

15147

+ * Makefile.in (lra-constraints.o): Depend on $(OPTABS_H).

15148

+ (lra-eliminations.o): Likewise.

15149

+

15150

+ 2013-05-16 Jeff Law <law@redhat.com>

15151

+

15152

+ * Makefile.in (tree-switch-conversion.o): Depend on $(OPTABS_H).

15153

+

15154

+2013-11-20 Eric Botcazou <ebotcazou@adacore.com>

15155

+

15156

+ PR target/59207

15157

+ * config/sparc/sparc.c (sparc_fold_builtin) <case CODE_FOR_pdist_vis>:

15158

+ Make sure neg2_ovf is set before being used.

15159

+

15160

+2013-11-20 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>

15161

+ Dominik Vogt <vogt@linux.vnet.ibm.com>

15162

+

15163

+ Backport from mainline

15164

+ * config/s390/s390.c (s390_canonicalize_comparison): Don't fold

15165

+ int comparisons with an out of range condition code.

15166

+ (s390_optimize_nonescaping_tx): Skip empty BBs.

15167

+ Generate the new tbegin RTX when removing the FPR clobbers (with

15168

+ two SETs).

15169

+ (s390_expand_tbegin): Fix the retry loop counter. Copy CC to the

15170

+ result before doing the retry calculations.

15171

+ (s390_init_builtins): Make tbegin "returns_twice" and tabort

15172

+ "noreturn".

15173

+ * config/s390/s390.md (UNSPECV_TBEGIN_TDB): New constant used for

15174

+ the TDB setting part of an tbegin.

15175

+ ("tbegin_1", "tbegin_nofloat_1"): Add a set for the TDB.

15176

+ ("tx_assist"): Set unused argument to an immediate zero instead of

15177

+ loading zero into a GPR and pass it as argument.

15178

+ * config/s390/htmxlintrin.h (__TM_simple_begin, __TM_begin):

15179

+ Remove inline and related attributes.

15180

+ (__TM_nesting_depth, __TM_is_user_abort, __TM_is_named_user_abort)

15181

+ (__TM_is_illegal, __TM_is_footprint_exceeded)

15182

+ (__TM_is_nested_too_deep, __TM_is_conflict): Fix format value

15183

+ check.

15184

+

15185

+2013-11-19 Uros Bizjak <ubizjak@gmail.com>

15186

+

15187

+ Backport from mainline

15188

+ 2013-11-18 Uros Bizjak <ubizjak@gmail.com>

15189

+

15190

+ * config/i386/i386.c (ix86_decompose_address): Use REG_P instead of

15191

+ ix86_address_subreg_operand. Move subreg checks to

15192

+ ix86_validate_address_register. Move address override check to

15193

+ ix86_legitimate_address_p.

15194

+ (ix86_validate_address_register): New function.

15195

+ (ix86_legitimate_address_p): Call ix86_validate_address_register

15196

+ to validate base and index registers. Add address override check

15197

+ from ix86_decompose_address.

15198

+ (ix86_decompose_address): Remove.

15199

+

15200

+ Backport from mainline

15201

+ 2013-11-17 Uros Bizjak <ubizjak@gmail.com>

15202

+

15203

+ PR target/59153

15204

+ * config/i386/i386.c (ix86_address_subreg_operand): Do not

15205

+ reject non-integer subregs.

15206

+ (ix86_decompose_address): Do not reject invalid CONST_INT RTXes.

15207

+ Move check for invalid x32 constant addresses ...

15208

+ (ix86_legitimate_address_p): ... here.

15209

+

15210

+2013-11-19 Richard Biener <rguenther@suse.de>

15211

+

15212

+ Backport from mainline

15213

+ 2013-11-07 Richard Biener <rguenther@suse.de>

15214

+

15215

+ * tree-dfa.c (get_ref_base_and_extent): Fix casting.

15216

+

15217

+2013-11-19 Richard Biener <rguenther@suse.de>

15218

+

15219

+ PR tree-optimization/57517

15220

+ * tree-predcom.c (combinable_refs_p): Verify the combination

15221

+ is always executed when the refs are.

15222

+

15223

+2013-11-19 Richard Biener <rguenther@suse.de>

15224

+

15225

+ Backport from mainline

15226

+ 2013-11-05 Richard Biener <rguenther@suse.de>

15227

+

15228

+ PR middle-end/58941

15229

+ * tree-dfa.c (get_ref_base_and_extent): Merge common code

15230

+ in MEM_REF and TARGET_MEM_REF handling. Make sure to

15231

+ process trailing array detection before diving into the

15232

+ view-converted object (and possibly apply some extra offset).

15233

+

15234

+2013-11-18 Richard Biener <rguenther@suse.de>

15235

+

15236

+ Backport from mainline

15237

+ 2013-10-21 Richard Biener <rguenther@suse.de>

15238

+

15239

+ PR tree-optimization/58794

15240

+ * fold-const.c (operand_equal_p): Compare FIELD_DECL operand

15241

+ of COMPONENT_REFs with OEP_CONSTANT_ADDRESS_OF left in place.

15242

+

15243

+ 2013-10-21 Richard Biener <rguenther@suse.de>

15244

+

15245

+ PR middle-end/58742

15246

+ * fold-const.c (fold_binary_loc): Fold ((T) (X /[ex] C)) * C

15247

+ to (T) X for sign-changing conversions (or no conversion).

15248

+

15249

+ 2013-11-06 Richard Biener <rguenther@suse.de>

15250

+

15251

+ PR tree-optimization/58653

15252

+ * tree-predcom.c (ref_at_iteration): Rewrite to generate

15253

+ a MEM_REF.

15254

+ (prepare_initializers_chain): Adjust.

15255

+

15256

+ PR tree-optimization/59047

15257

+ * tree-predcom.c (ref_at_iteration): Handle bitfield accesses

15258

+ properly.

15259

+

15260

+ 2013-10-15 Richard Biener <rguenther@suse.de>

15261

+

15262

+ PR tree-optimization/58143

15263

+ * tree-ssa-loop-im.c (arith_code_with_undefined_signed_overflow):

15264

+ New function.

15265

+ (rewrite_to_defined_overflow): Likewise.

15266

+ (move_computations_dom_walker::before_dom): Rewrite stmts

15267

+ with undefined signed overflow that are not always executed

15268

+ into unsigned arithmetic.

15269

+

15270

+2013-11-14 Uros Bizjak <ubizjak@gmail.com>

15271

+

15272

+ Backport from mainline

15273

+ 2013-11-10 Uros Bizjak <ubizjak@gmail.com>

15274

+

15275

+ * mode-switching.c (optimize_mode_switching): Mark block as

15276

+ nontransparent, if last_mode at block exit is different from no_mode.

15277

+

15278

+ Backport from mainline

15279

+ 2013-11-06 Uros Bizjak <ubizjak@gmail.com>

15280

+

15281

+ PR target/59021

15282

+ * config/i386/i386.c (ix86_avx_u128_mode_needed): Require

15283

+ AVX_U128_DIRTY mode for call_insn RTXes that use AVX256 registers.

15284

+ (ix86_avx_u128_mode_needed): Return AVX_U128_DIRTY mode for call_insn

15285

+ RTXes that return in AVX256 register.

15286

+

15287

+2013-11-14 Jakub Jelinek <jakub@redhat.com>

15288

+ Uros Bizjak <ubizjak@gmail.com>

15289

+

15290

+ PR target/59101

15291

+ * config/i386/i386.md (*anddi_2): Only allow CCZmode if

15292

+ operands[2] satisfies_constraint_Z that might have bit 31 set.

15293

+

15294

+2013-11-12 H.J. Lu <hongjiu.lu@intel.com>

15295

+

15296

+ Backported from mainline

15297

+ 2013-11-12 H.J. Lu <hongjiu.lu@intel.com>

15298

+

15299

+ PR target/59088

15300

+ * config/i386/i386.c (initial_ix86_tune_features): Set

15301

+ X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL and

15302

+ X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL for m_HASWELL.

15303

+

15304

+2013-11-11 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>

15305

+

15306

+ Backported from mainline

15307

+ 2013-10-30 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>

15308

+

15309

+ PR target/58854

15310

+ * config/arm/arm.c (arm_expand_epilogue_apcs_frame): Emit blockage

15311

+

15312

+2013-11-11 Jakub Jelinek <jakub@redhat.com>

15313

+

15314

+ Backported from mainline

15315

+ 2013-11-06 Jakub Jelinek <jakub@redhat.com>

15316

+

15317

+ PR middle-end/58970

15318

+ * expr.c (get_bit_range): Handle *offset == NULL_TREE.

15319

+ (expand_assignment): If *bitpos is negative, set *offset

15320

+ and adjust *bitpos, so that it is not negative.

15321

+

15322

+ 2013-11-05 Jakub Jelinek <jakub@redhat.com>

15323

+

15324

+ PR rtl-optimization/58997

15325

+ * loop-iv.c (iv_subreg): For IV_UNKNOWN_EXTEND, expect

15326

+ get_iv_value to be in iv->mode rather than iv->extend_mode.

15327

+ (iv_extend): Likewise. Otherwise, if iv->extend != extend,

15328

+ use lowpart_subreg on get_iv_value before calling simplify_gen_unary.

15329

+ * loop-unswitch.c (may_unswitch_on): Make sure op[i] is in the right

15330

+ mode.

15331

+

15332

+2013-11-10 Karlson2k <k2k@narod.ru>

15333

+ Kai Tietz <ktietz@redhat.com>

15334

+

15335

+ Merged from trunk

15336

+ PR plugins/52872

15337

+ * configure.ac: Adding for exported symbols check

15338

+ and for rdynamic-check executable-extension.

15339

+ * configure: Regenerated.

15340

+

15341

+2013-11-07 H.J. Lu <hongjiu.lu@intel.com>

15342

+

15343

+ PR target/59034

15344

+ * config/i386/i386.md (push peepholer/splitter): Use Pmode

15345

+ with stack_pointer_rtx.

15346

+

15347

+2013-11-05 Uros Bizjak <ubizjak@gmail.com>

15348

+

15349

+ * config/i386/t-rtems (MULTILIB_MATCHES): Fix option typos.

15350

+

15351

+2013-11-05 Jakub Jelinek <jakub@redhat.com>

15352

+

15353

+ PR tree-optimization/58984

15354

+ * ipa-prop.c (ipa_load_from_parm_agg_1): Add SIZE_P argument,

15355

+ set *SIZE_P if non-NULL on success.

15356

+ (ipa_load_from_parm_agg, ipa_analyze_indirect_call_uses): Adjust

15357

+ callers.

15358

+ (ipcp_transform_function): Likewise. Punt if size of access

15359

+ is different from TYPE_SIZE on v->value's type.

15360

+

15361

+2013-11-03 H.J. Lu <hongjiu.lu@intel.com>

15362

+

15363

+ Backport from mainline

15364

+ 2013-10-12 H.J. Lu <hongjiu.lu@intel.com>

15365

+

15366

+ PR target/58690

15367

+ * config/i386/i386.c (ix86_copy_addr_to_reg): New function.

15368

+ (ix86_expand_movmem): Replace copy_addr_to_reg with

15369

+ ix86_copy_addr_to_reg.

15370

+ (ix86_expand_setmem): Likewise.

15371

+

15372

+2013-10-29 Uros Bizjak <ubizjak@gmail.com>

15373

+

15374

+ Backport from mainline

15375

+ 2013-08-08 Richard Sandiford <rdsandiford@googlemail.com>

15376

+

15377

+ PR rtl-optimization/58079

15378

+ * combine.c (combine_simplify_rtx): Avoid using SUBST if

15379

+ simplify_comparison has widened a comparison with an integer.

15380

+

15381

+2013-10-29 Martin Jambor <mjambor@suse.cz>

15382

+

15383

+ PR middle-end/58789

15384

+ Backport from mainline

15385

+ 2013-05-09 Martin Jambor <mjambor@suse.cz>

15386

+

15387

+ PR lto/57084

15388

+ * gimple-fold.c (canonicalize_constructor_val): Call

15389

+ cgraph_get_create_real_symbol_node instead of cgraph_get_create_node.

15390

+

15391

+ Backport from mainline

15392

+ 2013-03-16 Jan Hubicka <jh@suse.cz>

15393

+

15394

+ * cgraph.h (cgraph_get_create_real_symbol_node): Declare.

15395

+ * cgraph.c (cgraph_get_create_real_symbol_node): New function.

15396

+ * cgrpahbuild.c: Use cgraph_get_create_real_symbol_node instead

15397

+ of cgraph_get_create_node.

15398

+ * ipa-prop.c (ipa_make_edge_direct_to_target): Likewise.

15399

+

15400

+2013-10-28 Tom de Vries <tom@codesourcery.com>

15401

+

15402

+ * cfgexpand.c (gimple_expand_cfg): Remove test for parm_birth_insn.

15403

+ Don't commit insertions after NOTE_INSN_FUNCTION_BEG.

15404

+

15405

+2013-10-26 Uros Bizjak <ubizjak@gmail.com>

15406

+

15407

+ Backport from mainline

15408

+ 2013-10-22 Uros Bizjak <ubizjak@gmail.com>

15409

+

15410

+ PR target/58779

15411

+ * config/i386/i386.c (put_condition_code) <case GTU, case LEU>:

15412

+ Remove CCCmode handling.

15413

+ <case LTU>: Return 'c' suffix for CCCmode.

15414

+ <case GEU>: Return 'nc' suffix for CCCmode.

15415

+ (ix86_cc_mode) <case GTU, case LEU>: Do not generate overflow checks.

15416

+ * config/i386/i386.md (*sub<mode>3_cconly_overflow): Remove.

15417

+ (*sub<mode>3_cc_overflow): Ditto.

15418

+ (*subsi3_zext_cc_overflow): Ditto.

15419

+

15420

+2013-10-26 Uros Bizjak <ubizjak@gmail.com>

15421

+

15422

+ Backport from mainline

15423

+ 2013-10-19 Uros Bizjak <ubizjak@gmail.com>

15424

+

15425

+ PR target/58792

15426

+ * config/i386/i386.c (ix86_function_value_regno): Add DX_REG,

15427

+ ST1_REG and XMM1_REG for 32bit and 64bit targets. Also add DI_REG

15428

+ and SI_REG for 64bit SYSV ABI targets.

15429

+

15430

+2013-08-25 Richard Henderson <rth@twiddle.net>

15431

+

15432

+ PR rtl/58542

15433

+ * optabs.c (maybe_emit_atomic_exchange): Use create_input_operand

15434

+ instead of create_convert_operand_to.

15435

+ (maybe_emit_sync_lock_test_and_set): Likewise.

15436

+ (expand_atomic_compare_and_swap): Likewise.

15437

+ (maybe_emit_compare_and_swap_exchange_loop): Don't convert_modes.

15438

+

15439

+2013-10-25 Eric Botcazou <ebotcazou@adacore.com>

15440

+

15441

+ PR rtl-optimization/58831

15442

+ * alias.c (init_alias_analysis): At the beginning of each iteration, set

15443

+ the reg_seen[N] bit if static_reg_base_value[N] is non-null.

15444

+

15445

+2013-10-25 Eric Botcazou <ebotcazou@adacore.com>

15446

+

15447

+ * recog.c (search_ofs): New static variable moved from...

15448

+ (peep2_find_free_register): ...here.

15449

+ (peephole2_optimize): Initialize it.

15450

+

15451

+2013-10-24 David Edelsohn <dje.gcc@gmail.com>

15452

+

15453

+ Backport from mainline

15454

+ 2013-10-23 David Edelsohn <dje.gcc@gmail.com>

15455

+

15456

+ PR target/58838

15457

+ * config/rs6000/rs6000.md (mulsi3_internal1 and splitter): Add

15458

+ TARGET_32BIT final condition.

15459

+ (mulsi3_internal2 and splitter): Same.

15460

+

15461

+2013-10-23 Tom de Vries <tom@codesourcery.com>

15462

+

15463

+ PR tree-optimization/58805

15464

+ * tree-ssa-tail-merge.c (stmt_local_def): Add gimple_vdef check.

15465

+

15466

+2013-10-23 Richard Biener <rguenther@suse.de>

15467

+

15468

+ Backport from mainline

15469

+ 2013-06-24 Richard Biener <rguenther@suse.de>

15470

+

15471

+ PR tree-optimization/57488

15472

+ * tree-ssa-pre.c (insert): Clear NEW sets before each iteration.

15473

+

15474

+2013-10-16 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>

15475

+

15476

+ Backport from mainline

15477

+ 2013-10-16 Ganesh Gopalasubramanian

15478

+ <Ganesh.Gopalasubramanian@amd.com>

15479

+

15480

+ * config/i386/i386.c (ix86_option_override_internal): Enable FMA4

15481

+ for AMD bdver3.

15482

+

15483

2013-10-16 Release Manager

15484

15485

* GCC 4.8.2 released.

15486

@@ -639,7 +6008,7 @@

15487

2013-07-31 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>

15488

15489

Backport from mainline

15490

- 2013-03-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>

15491

+ 2013-03-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>

15492

15493

* config/s390/s390.h (TARGET_FLT_EVAL_METHOD): Define.

15494

15495

Index: gcc/testsuite/gcc.target/arm/thumb1-pic-single-base.c

15496

===================================================================

15497

--- a/src/gcc/testsuite/gcc.target/arm/thumb1-pic-single-base.c (.../tags/gcc_4_8_2_release)

15498

+++ b/src/gcc/testsuite/gcc.target/arm/thumb1-pic-single-base.c (.../branches/gcc-4_8-branch)

15499

@@ -0,0 +1,11 @@

15500

+/* { dg-do compile } */

15501

+/* { dg-require-effective-target arm_thumb1_ok } */

15502

+/* { dg-options "-mthumb -fpic -msingle-pic-base" } */

15503

+

15504

+int g_test;

15505

+

15506

+int

15507

+foo (int par)

15508

+{

15509

+ g_test = par;

15510

+}

15511

Index: gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64-1.c

15512

===================================================================

15513

--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64-1.c (.../tags/gcc_4_8_2_release)

15514

+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64-1.c (.../branches/gcc-4_8-branch)

15515

@@ -0,0 +1,25 @@

15516

+/* Test the `vst1Q_laneu64' ARM Neon intrinsic. */

15517

+

15518

+/* Detect ICE in the case of unaligned memory address. */

15519

+

15520

+/* { dg-do compile } */

15521

+/* { dg-require-effective-target arm_neon_ok } */

15522

+/* { dg-add-options arm_neon } */

15523

+

15524

+#include "arm_neon.h"

15525

+

15526

+unsigned char dummy_store[1000];

15527

+

15528

+void

15529

+foo (char* addr)

15530

+{

15531

+ uint8x16_t vdata = vld1q_u8 (addr);

15532

+ vst1q_lane_u64 ((uint64_t*) &dummy_store, vreinterpretq_u64_u8 (vdata), 0);

15533

+}

15534

+

15535

+uint64_t

15536

+bar (uint64x2_t vdata)

15537

+{

15538

+ vdata = vld1q_lane_u64 ((uint64_t*) &dummy_store, vdata, 0);

15539

+ return vgetq_lane_u64 (vdata, 0);

15540

+}

15541

Index: gcc/testsuite/gcc.target/arm/thumb1-pic-high-reg.c

15542

===================================================================

15543

--- a/src/gcc/testsuite/gcc.target/arm/thumb1-pic-high-reg.c (.../tags/gcc_4_8_2_release)

15544

+++ b/src/gcc/testsuite/gcc.target/arm/thumb1-pic-high-reg.c (.../branches/gcc-4_8-branch)

15545

@@ -0,0 +1,11 @@

15546

+/* { dg-do compile } */

15547

+/* { dg-require-effective-target arm_thumb1_ok } */

15548

+/* { dg-options "-mthumb -fpic -mpic-register=9" } */

15549

+

15550

+int g_test;

15551

+

15552

+int

15553

+foo (int par)

15554

+{

15555

+ g_test = par;

15556

+}

15557

Index: gcc/testsuite/gcc.target/arm/require-pic-register-loc.c

15558

===================================================================

15559

--- a/src/gcc/testsuite/gcc.target/arm/require-pic-register-loc.c (.../tags/gcc_4_8_2_release)

15560

+++ b/src/gcc/testsuite/gcc.target/arm/require-pic-register-loc.c (.../branches/gcc-4_8-branch)

15561

@@ -0,0 +1,29 @@

15562

+/* { dg-do compile } */

15563

+/* { dg-options "-g -fPIC" } */

15564

+

15565

+void *v;

15566

+void a (void *x) { }

15567

+void b (void) { }

15568

+ /* line 7. */

15569

+int /* line 8. */

15570

+main (int argc) /* line 9. */

15571

+{ /* line 10. */

15572

+ if (argc == 12345) /* line 11. */

15573

+ {

15574

+ a (v);

15575

+ return 1;

15576

+ }

15577

+ b ();

15578

+

15579

+ return 0;

15580

+}

15581

+

15582

+/* { dg-final { scan-assembler-not "\.loc 1 7 0" } } */

15583

+/* { dg-final { scan-assembler-not "\.loc 1 8 0" } } */

15584

+/* { dg-final { scan-assembler-not "\.loc 1 9 0" } } */

15585

+

15586

+/* The loc at the start of the prologue. */

15587

+/* { dg-final { scan-assembler-times "\.loc 1 10 0" 1 } } */

15588

+

15589

+/* The loc at the end of the prologue, with the first user line. */

15590

+/* { dg-final { scan-assembler-times "\.loc 1 11 0" 1 } } */

15591

Index: gcc/testsuite/gcc.target/arm/vrinta-ce.c

15592

===================================================================

15593

--- a/src/gcc/testsuite/gcc.target/arm/vrinta-ce.c (.../tags/gcc_4_8_2_release)

15594

+++ b/src/gcc/testsuite/gcc.target/arm/vrinta-ce.c (.../branches/gcc-4_8-branch)

15595

@@ -0,0 +1,15 @@

15596

+/* { dg-do compile } */

15597

+/* { dg-require-effective-target arm_v8_vfp_ok } */

15598

+/* { dg-options "-O2 -marm -march=armv8-a" } */

15599

+/* { dg-add-options arm_v8_vfp } */

15600

+

15601

+double foo (double a)

15602

+{

15603

+ if (a > 3.0)

15604

+ return __builtin_round (a);

15605

+

15606

+ return 0.0;

15607

+}

15608

+

15609

+/* { dg-final { scan-assembler-times "vrinta.f64\td\[0-9\]+" 1 } } */

15610

+

15611

Index: gcc/testsuite/gcc.target/arm/pr54300.C

15612

===================================================================

15613

--- a/src/gcc/testsuite/gcc.target/arm/pr54300.C (.../tags/gcc_4_8_2_release)

15614

+++ b/src/gcc/testsuite/gcc.target/arm/pr54300.C (.../branches/gcc-4_8-branch)

15615

@@ -0,0 +1,61 @@

15616

+/* { dg-do run } */

15617

+/* { dg-require-effective-target arm_neon } */

15618

+/* { dg-options "-O2" } */

15619

+/* { dg-add-options arm_neon } */

15620

+

15621

+#include <arm_neon.h>

15622

+#include <stdlib.h>

15623

+

15624

+struct __attribute__ ((aligned(8))) _v16u8_ {

15625

+ uint8x16_t val;

15626

+ _v16u8_( const int16x8_t &src) { val = vreinterpretq_u8_s16(src); }

15627

+ operator int16x8_t () const { return vreinterpretq_s16_u8(val); }

15628

+};

15629

+typedef struct _v16u8_ v16u8;

15630

+

15631

+struct __attribute__ ((aligned(4))) _v8u8_ {

15632

+ uint8x8_t val;

15633

+ _v8u8_( const uint8x8_t &src) { val = src; }

15634

+ operator int16x4_t () const { return vreinterpret_s16_u8(val); }

15635

+};

15636

+typedef struct _v8u8_ v8u8;

15637

+

15638

+typedef v16u8 v8i16;

15639

+typedef int32x4_t v4i32;

15640

+typedef const short cv1i16;

15641

+typedef const unsigned char cv1u8;

15642

+typedef const v8i16 cv8i16;

15643

+

15644

+static inline __attribute__((always_inline)) v8u8 zero_64(){ return vdup_n_u8( 0 ); }

15645

+

15646

+static inline __attribute__((always_inline)) v8i16 loadlo_8i16( cv8i16* p ){

15647

+ return vcombine_s16( vld1_s16( (cv1i16 *)p ), zero_64() );

15648

+}

15649

+static inline __attribute__((always_inline)) v8i16 _loadlo_8i16( cv8i16* p, int offset ){

15650

+ return loadlo_8i16( (cv8i16*)(&((cv1u8*)p)[offset]) );

15651

+}

15652

+

15653

+void __attribute__((noinline))

15654

+test(unsigned short *_Inp, int32_t *_Out,

15655

+ unsigned int s1v, unsigned int dv0,

15656

+ unsigned int smask_v)

15657

+{

15658

+ int32x4_t c = vdupq_n_s32(0);

15659

+

15660

+ for(unsigned int sv=0 ; sv!=dv0 ; sv=(sv+s1v)&smask_v )

15661

+ {

15662

+ int32x4_t s;

15663

+ s = vmovl_s16( vget_low_s16( _loadlo_8i16( (cv8i16*) _Inp, sv ) ) );

15664

+ c = vaddq_s32( c, s );

15665

+ }

15666

+ vst1q_s32( _Out, c );

15667

+}

15668

+

15669

+main()

15670

+{

15671

+ unsigned short a[4] = {1, 2, 3, 4};

15672

+ int32_t b[4] = {0, 0, 0, 0};

15673

+ test(a, b, 1, 1, ~0);

15674

+ if (b[0] != 1 || b[1] != 2 || b[2] != 3 || b[3] != 4)

15675

+ abort();

15676

+}

15677

Index: gcc/testsuite/gcc.target/arm/pr59826.c

15678

===================================================================

15679

--- a/src/gcc/testsuite/gcc.target/arm/pr59826.c (.../tags/gcc_4_8_2_release)

15680

+++ b/src/gcc/testsuite/gcc.target/arm/pr59826.c (.../branches/gcc-4_8-branch)

15681

@@ -0,0 +1,35 @@

15682

+/* { dg-do compile } */

15683

+/* { dg-options "-mthumb -mcpu=cortex-m4 -fprefetch-loop-arrays -O2" } */

15684

+

15685

+typedef struct genxWriter_rec * genxWriter;

15686

+typedef unsigned char * utf8;

15687

+typedef const unsigned char * constUtf8;

15688

+

15689

+int genxScrubText(genxWriter w, constUtf8 in, utf8 out)

15690

+{

15691

+ int problems = 0;

15692

+ constUtf8 last = in;

15693

+

15694

+ while (*in)

15695

+ {

15696

+ int c = genxNextUnicodeChar(&in);

15697

+ if (c == -1)

15698

+ {

15699

+ problems++;

15700

+ last = in;

15701

+ continue;

15702

+ }

15703

+

15704

+ if (!isXMLChar(w, c))

15705

+ {

15706

+ problems++;

15707

+ last = in;

15708

+ continue;

15709

+ }

15710

+

15711

+ while (last < in)

15712

+ *out++ = *last++;

15713

+ }

15714

+ *out = 0;

15715

+ return problems;

15716

+}

15717

Index: gcc/testsuite/gcc.target/arm/pr57637.c

15718

===================================================================

15719

--- a/src/gcc/testsuite/gcc.target/arm/pr57637.c (.../tags/gcc_4_8_2_release)

15720

+++ b/src/gcc/testsuite/gcc.target/arm/pr57637.c (.../branches/gcc-4_8-branch)

15721

@@ -0,0 +1,206 @@

15722

+/* { dg-do run } */

15723

+/* { dg-options "-O2 -fno-inline" } */

15724

+

15725

+typedef struct _GtkCssStyleProperty GtkCssStyleProperty;

15726

+

15727

+struct _GtkCssStyleProperty

15728

+{

15729

+ int *initial_value;

15730

+ unsigned int id;

15731

+ unsigned int inherit :1;

15732

+ unsigned int animated :1;

15733

+ unsigned int affects_size :1;

15734

+ unsigned int affects_font :1;

15735

+

15736

+ int * parse_value;

15737

+ int * query_value;

15738

+ int * assign_value;

15739

+};

15740

+

15741

+void

15742

+g_assertion_message_expr (const char *domain,

15743

+ const char *file,

15744

+ int line,

15745

+ const char *func,

15746

+ const char *expr) __attribute__((__noreturn__));

15747

+

15748

+void

15749

+g_assertion_message_expr (const char *domain,

15750

+ const char *file,

15751

+ int line,

15752

+ const char *func,

15753

+ const char *expr)

15754

+{

15755

+ __builtin_abort ();

15756

+}

15757

+int

15758

+get_id (GtkCssStyleProperty *property)

15759

+{

15760

+ return 1;

15761

+}

15762

+int

15763

+_gtk_css_style_property_get_type ()

15764

+{

15765

+ return 1;

15766

+}

15767

+

15768

+GtkCssStyleProperty *

15769

+g_object_new (int object_type,

15770

+ const char *first_property_name,

15771

+ ...)

15772

+{

15773

+ return (GtkCssStyleProperty *) __builtin_malloc (sizeof (GtkCssStyleProperty));

15774

+}

15775

+

15776

+typedef enum {

15777

+ INHERIT = (1 << 0),

15778

+ ANIMATED = (1 << 1),

15779

+ RESIZE = (1 << 2),

15780

+ FONT = (1 << 3)

15781

+} GtkStylePropertyFlags;

15782

+

15783

+int t = 0;

15784

+void

15785

+gtk_css_style_property_register (const char * name,

15786

+ int expected_id,

15787

+ int value_type,

15788

+ int flags,

15789

+ int *parse_value,

15790

+ int *query_value,

15791

+ int *assign_value,

15792

+ int *initial_value)

15793

+{

15794

+ GtkCssStyleProperty *node;

15795

+

15796

+ do

15797

+ {

15798

+ if (__builtin_expect (__extension__ (

15799

+ {

15800

+ int _g_boolean_var_;

15801

+ if (initial_value != ((void *)0))

15802

+ _g_boolean_var_ = 1;

15803

+ else

15804

+ _g_boolean_var_ = 0;

15805

+ _g_boolean_var_;

15806

+ }),

15807

+ 1))

15808

+ ;

15809

+ else

15810

+ g_assertion_message_expr ("Gtk",

15811

+ "gtkcssstylepropertyimpl.c",

15812

+ 85,

15813

+ ((const char*) (__PRETTY_FUNCTION__)),

15814

+ "initial_value != NULL");

15815

+ } while (0);

15816

+

15817

+ do

15818

+ {

15819

+ if (__builtin_expect (__extension__ (

15820

+ {

15821

+ int _g_boolean_var_;

15822

+ if (parse_value != ((void *)0))

15823

+ _g_boolean_var_ = 1;

15824

+ else

15825

+ _g_boolean_var_ = 0;

15826

+ _g_boolean_var_;

15827

+ }),

15828

+ 1))

15829

+ ;

15830

+ else

15831

+ g_assertion_message_expr ("Gtk",

15832

+ "gtkcssstylepropertyimpl.c",

15833

+ 86,

15834

+ ((const char*) (__PRETTY_FUNCTION__)),

15835

+ "parse_value != NULL");

15836

+ } while (0);

15837

+

15838

+ do

15839

+ {

15840

+ if (__builtin_expect (__extension__ (

15841

+ {

15842

+ int _g_boolean_var_;

15843

+ if (value_type == ((int) ((1) << (2)))

15844

+ || query_value != ((void *)0))

15845

+ _g_boolean_var_ = 1;

15846

+ else

15847

+ _g_boolean_var_ = 0;

15848

+ _g_boolean_var_;

15849

+ }),

15850

+ 1))

15851

+ ;

15852

+ else

15853

+ g_assertion_message_expr ("Gtk",

15854

+ "gtkcssstylepropertyimpl.c",

15855

+ 87, ((const char*) (__PRETTY_FUNCTION__)),

15856

+ "value_type == NONE || query_value != NULL");

15857

+ } while (0);

15858

+

15859

+ /* FLAGS is changed in a cond_exec instruction with pr57637. */

15860

+ if (flags == 15)

15861

+ t = 15;

15862

+

15863

+ do

15864

+ {

15865

+ if (__builtin_expect (__extension__ (

15866

+ {

15867

+ int _g_boolean_var_;

15868

+ if (value_type == ((1) << (2))

15869

+ || assign_value != ((void *)0))

15870

+ _g_boolean_var_ = 1;

15871

+ else

15872

+ _g_boolean_var_ = 0;

15873

+ _g_boolean_var_;

15874

+ }),

15875

+ 1))

15876

+ ;

15877

+ else

15878

+ g_assertion_message_expr ("Gtk",

15879

+ "gtkcssstylepropertyimpl.c",

15880

+ 88, ((const char*) (__PRETTY_FUNCTION__)),

15881

+ "value_type == NONE || assign_value != NULL");

15882

+ } while (0);

15883

+

15884

+ node = g_object_new ((_gtk_css_style_property_get_type ()),

15885

+ "value-type", value_type,

15886

+ "affects-size", (flags & RESIZE) ? (0) : (!(0)),

15887

+ "affects-font", (flags & FONT) ? (!(0)) : (0),

15888

+ "animated", (flags & ANIMATED) ? (!(0)) : (0),

15889

+ "inherit", (flags & INHERIT) ? (!(0)) : (0),

15890

+ "initial-value", initial_value,

15891

+ "name", name,

15892

+ ((void *)0));

15893

+

15894

+ node->parse_value = parse_value;

15895

+ node->query_value = query_value;

15896

+ node->assign_value = assign_value;

15897

+

15898

+ do

15899

+ {

15900

+ if (__builtin_expect (__extension__ (

15901

+ {

15902

+ int _g_boolean_var_;

15903

+ if (get_id (node) == expected_id)

15904

+ _g_boolean_var_ = 1;

15905

+ else

15906

+ _g_boolean_var_ = 0;

15907

+ _g_boolean_var_;

15908

+ }),

15909

+ 1))

15910

+ ;

15911

+ else

15912

+ g_assertion_message_expr ("Gtk",

15913

+ "gtkcssstylepropertyimpl.c",

15914

+ 106,

15915

+ ((const char*) (__PRETTY_FUNCTION__)),

15916

+ "get_id (node) == expected_id");

15917

+ } while (0);

15918

+}

15919

+

15920

+int main ()

15921

+{

15922

+ gtk_css_style_property_register ("test", 1, 4, 15, &t, &t, &t, &t);

15923

+

15924

+ if (t != 15)

15925

+ __builtin_abort ();

15926

+ return 0;

15927

+}

15928

Index: gcc/testsuite/gcc.target/powerpc/ppc-target-2.c

15929

===================================================================

15930

--- a/src/gcc/testsuite/gcc.target/powerpc/ppc-target-2.c (.../tags/gcc_4_8_2_release)

15931

+++ b/src/gcc/testsuite/gcc.target/powerpc/ppc-target-2.c (.../branches/gcc-4_8-branch)

15932

@@ -5,8 +5,7 @@

15933

/* { dg-final { scan-assembler-times "fabs" 3 } } */

15934

/* { dg-final { scan-assembler-times "fnabs" 3 } } */

15935

/* { dg-final { scan-assembler-times "fsel" 3 } } */

15936

-/* { dg-final { scan-assembler-times "fcpsgn" 3 } } */

15937

-/* { dg-final { scan-assembler-times "xscpsgndp" 1 } } */

15938

+/* { dg-final { scan-assembler-times "fcpsgn\|xscpsgndp" 4 } } */

15939

15940

/* fabs/fnabs/fsel */

15941

double normal1 (double a, double b) { return __builtin_copysign (a, b); }

15942

Index: gcc/testsuite/gcc.target/powerpc/dfp-builtin-1.c

15943

===================================================================

15944

--- a/src/gcc/testsuite/gcc.target/powerpc/dfp-builtin-1.c (.../tags/gcc_4_8_2_release)

15945

+++ b/src/gcc/testsuite/gcc.target/powerpc/dfp-builtin-1.c (.../branches/gcc-4_8-branch)

15946

@@ -0,0 +1,88 @@

15947

+/* { dg-do compile { target { powerpc*-*-linux* } } } */

15948

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

15949

+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */

15950

+/* { dg-require-effective-target powerpc_vsx_ok } */

15951

+/* { dg-options "-mcpu=power7 -O2" } */

15952

+/* { dg-final { scan-assembler-times "ddedpd " 4 } } */

15953

+/* { dg-final { scan-assembler-times "denbcd " 2 } } */

15954

+/* { dg-final { scan-assembler-times "dxex " 1 } } */

15955

+/* { dg-final { scan-assembler-times "diex " 1 } } */

15956

+/* { dg-final { scan-assembler-times "dscli " 2 } } */

15957

+/* { dg-final { scan-assembler-times "dscri " 2 } } */

15958

+/* { dg-final { scan-assembler-not "bl __builtin" } } */

15959

+/* { dg-final { scan-assembler-not "dctqpq" } } */

15960

+/* { dg-final { scan-assembler-not "drdpq" } } */

15961

+/* { dg-final { scan-assembler-not "stfd" } } */

15962

+/* { dg-final { scan-assembler-not "lfd" } } */

15963

+

15964

+_Decimal64

15965

+do_dedpd_0 (_Decimal64 a)

15966

+{

15967

+ return __builtin_ddedpd (0, a);

15968

+}

15969

+

15970

+_Decimal64

15971

+do_dedpd_1 (_Decimal64 a)

15972

+{

15973

+ return __builtin_ddedpd (1, a);

15974

+}

15975

+

15976

+_Decimal64

15977

+do_dedpd_2 (_Decimal64 a)

15978

+{

15979

+ return __builtin_ddedpd (2, a);

15980

+}

15981

+

15982

+_Decimal64

15983

+do_dedpd_3 (_Decimal64 a)

15984

+{

15985

+ return __builtin_ddedpd (3, a);

15986

+}

15987

+

15988

+_Decimal64

15989

+do_enbcd_0 (_Decimal64 a)

15990

+{

15991

+ return __builtin_denbcd (0, a);

15992

+}

15993

+

15994

+_Decimal64

15995

+do_enbcd_1 (_Decimal64 a)

15996

+{

15997

+ return __builtin_denbcd (1, a);

15998

+}

15999

+

16000

+_Decimal64

16001

+do_xex (_Decimal64 a)

16002

+{

16003

+ return __builtin_dxex (a);

16004

+}

16005

+

16006

+_Decimal64

16007

+do_iex (_Decimal64 a, _Decimal64 b)

16008

+{

16009

+ return __builtin_diex (a, b);

16010

+}

16011

+

16012

+_Decimal64

16013

+do_scli_1 (_Decimal64 a)

16014

+{

16015

+ return __builtin_dscli (a, 1);

16016

+}

16017

+

16018

+_Decimal64

16019

+do_scli_10 (_Decimal64 a)

16020

+{

16021

+ return __builtin_dscli (a, 10);

16022

+}

16023

+

16024

+_Decimal64

16025

+do_scri_1 (_Decimal64 a)

16026

+{

16027

+ return __builtin_dscri (a, 1);

16028

+}

16029

+

16030

+_Decimal64

16031

+do_scri_10 (_Decimal64 a)

16032

+{

16033

+ return __builtin_dscri (a, 10);

16034

+}

16035

Index: gcc/testsuite/gcc.target/powerpc/p8vector-builtin-1.c

16036

===================================================================

16037

--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-1.c (.../tags/gcc_4_8_2_release)

16038

+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-1.c (.../branches/gcc-4_8-branch)

16039

@@ -0,0 +1,65 @@

16040

+/* { dg-do compile { target { powerpc*-*-* } } } */

16041

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

16042

+/* { dg-require-effective-target powerpc_p8vector_ok } */

16043

+/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model -fno-unroll-loops -fno-unroll-all-loops" } */

16044

+

16045

+#ifndef TYPE

16046

+#define TYPE long long

16047

+#endif

16048

+

16049

+#ifndef SIGN_TYPE

16050

+#define SIGN_TYPE signed TYPE

16051

+#endif

16052

+

16053

+#ifndef UNS_TYPE

16054

+#define UNS_TYPE unsigned TYPE

16055

+#endif

16056

+

16057

+typedef vector SIGN_TYPE v_sign;

16058

+typedef vector UNS_TYPE v_uns;

16059

+

16060

+v_sign sign_add (v_sign a, v_sign b)

16061

+{

16062

+ return a + b;

16063

+}

16064

+

16065

+v_sign sign_sub (v_sign a, v_sign b)

16066

+{

16067

+ return a - b;

16068

+}

16069

+

16070

+v_sign sign_shift_left (v_sign a, v_sign b)

16071

+{

16072

+ return a << b;

16073

+}

16074

+

16075

+v_sign sign_shift_right (v_sign a, v_sign b)

16076

+{

16077

+ return a >> b;

16078

+}

16079

+

16080

+v_uns uns_add (v_uns a, v_uns b)

16081

+{

16082

+ return a + b;

16083

+}

16084

+

16085

+v_uns uns_sub (v_uns a, v_uns b)

16086

+{

16087

+ return a - b;

16088

+}

16089

+

16090

+v_uns uns_shift_left (v_uns a, v_uns b)

16091

+{

16092

+ return a << b;

16093

+}

16094

+

16095

+v_uns uns_shift_right (v_uns a, v_uns b)

16096

+{

16097

+ return a >> b;

16098

+}

16099

+

16100

+/* { dg-final { scan-assembler-times "vaddudm" 2 } } */

16101

+/* { dg-final { scan-assembler-times "vsubudm" 2 } } */

16102

+/* { dg-final { scan-assembler-times "vsld" 2 } } */

16103

+/* { dg-final { scan-assembler-times "vsrad" 1 } } */

16104

+/* { dg-final { scan-assembler-times "vsrd" 1 } } */

16105

Index: gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-1.c

16106

===================================================================

16107

--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-1.c (.../tags/gcc_4_8_2_release)

16108

+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-1.c (.../branches/gcc-4_8-branch)

16109

@@ -0,0 +1,200 @@

16110

+/* { dg-do compile { target { powerpc*-*-* } } } */

16111

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

16112

+/* { dg-require-effective-target powerpc_p8vector_ok } */

16113

+/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model -fno-unroll-loops -fno-unroll-all-loops" } */

16114

+

16115

+#ifndef SIZE

16116

+#define SIZE 1024

16117

+#endif

16118

+

16119

+#ifndef ALIGN

16120

+#define ALIGN 32

16121

+#endif

16122

+

16123

+#ifndef TYPE

16124

+#define TYPE long long

16125

+#endif

16126

+

16127

+#ifndef SIGN_TYPE

16128

+#define SIGN_TYPE signed TYPE

16129

+#endif

16130

+

16131

+#ifndef UNS_TYPE

16132

+#define UNS_TYPE unsigned TYPE

16133

+#endif

16134

+

16135

+#define ALIGN_ATTR __attribute__((__aligned__(ALIGN)))

16136

+

16137

+SIGN_TYPE sa[SIZE] ALIGN_ATTR;

16138

+SIGN_TYPE sb[SIZE] ALIGN_ATTR;

16139

+SIGN_TYPE sc[SIZE] ALIGN_ATTR;

16140

+

16141

+UNS_TYPE ua[SIZE] ALIGN_ATTR;

16142

+UNS_TYPE ub[SIZE] ALIGN_ATTR;

16143

+UNS_TYPE uc[SIZE] ALIGN_ATTR;

16144

+

16145

+void

16146

+sign_add (void)

16147

+{

16148

+ unsigned long i;

16149

+

16150

+ for (i = 0; i < SIZE; i++)

16151

+ sa[i] = sb[i] + sc[i];

16152

+}

16153

+

16154

+void

16155

+sign_sub (void)

16156

+{

16157

+ unsigned long i;

16158

+

16159

+ for (i = 0; i < SIZE; i++)

16160

+ sa[i] = sb[i] - sc[i];

16161

+}

16162

+

16163

+void

16164

+sign_shift_left (void)

16165

+{

16166

+ unsigned long i;

16167

+

16168

+ for (i = 0; i < SIZE; i++)

16169

+ sa[i] = sb[i] << sc[i];

16170

+}

16171

+

16172

+void

16173

+sign_shift_right (void)

16174

+{

16175

+ unsigned long i;

16176

+

16177

+ for (i = 0; i < SIZE; i++)

16178

+ sa[i] = sb[i] >> sc[i];

16179

+}

16180

+

16181

+void

16182

+sign_max (void)

16183

+{

16184

+ unsigned long i;

16185

+

16186

+ for (i = 0; i < SIZE; i++)

16187

+ sa[i] = (sb[i] > sc[i]) ? sb[i] : sc[i];

16188

+}

16189

+

16190

+void

16191

+sign_min (void)

16192

+{

16193

+ unsigned long i;

16194

+

16195

+ for (i = 0; i < SIZE; i++)

16196

+ sa[i] = (sb[i] < sc[i]) ? sb[i] : sc[i];

16197

+}

16198

+

16199

+void

16200

+sign_abs (void)

16201

+{

16202

+ unsigned long i;

16203

+

16204

+ for (i = 0; i < SIZE; i++)

16205

+ sa[i] = (sb[i] < 0) ? -sb[i] : sb[i]; /* xor, vsubudm, vmaxsd. */

16206

+}

16207

+

16208

+void

16209

+sign_eq (SIGN_TYPE val1, SIGN_TYPE val2)

16210

+{

16211

+ unsigned long i;

16212

+

16213

+ for (i = 0; i < SIZE; i++)

16214

+ sa[i] = (sb[i] == sc[i]) ? val1 : val2;

16215

+}

16216

+

16217

+void

16218

+sign_lt (SIGN_TYPE val1, SIGN_TYPE val2)

16219

+{

16220

+ unsigned long i;

16221

+

16222

+ for (i = 0; i < SIZE; i++)

16223

+ sa[i] = (sb[i] < sc[i]) ? val1 : val2;

16224

+}

16225

+

16226

+void

16227

+uns_add (void)

16228

+{

16229

+ unsigned long i;

16230

+

16231

+ for (i = 0; i < SIZE; i++)

16232

+ ua[i] = ub[i] + uc[i];

16233

+}

16234

+

16235

+void

16236

+uns_sub (void)

16237

+{

16238

+ unsigned long i;

16239

+

16240

+ for (i = 0; i < SIZE; i++)

16241

+ ua[i] = ub[i] - uc[i];

16242

+}

16243

+

16244

+void

16245

+uns_shift_left (void)

16246

+{

16247

+ unsigned long i;

16248

+

16249

+ for (i = 0; i < SIZE; i++)

16250

+ ua[i] = ub[i] << uc[i];

16251

+}

16252

+

16253

+void

16254

+uns_shift_right (void)

16255

+{

16256

+ unsigned long i;

16257

+

16258

+ for (i = 0; i < SIZE; i++)

16259

+ ua[i] = ub[i] >> uc[i];

16260

+}

16261

+

16262

+void

16263

+uns_max (void)

16264

+{

16265

+ unsigned long i;

16266

+

16267

+ for (i = 0; i < SIZE; i++)

16268

+ ua[i] = (ub[i] > uc[i]) ? ub[i] : uc[i];

16269

+}

16270

+

16271

+void

16272

+uns_min (void)

16273

+{

16274

+ unsigned long i;

16275

+

16276

+ for (i = 0; i < SIZE; i++)

16277

+ ua[i] = (ub[i] < uc[i]) ? ub[i] : uc[i];

16278

+}

16279

+

16280

+void

16281

+uns_eq (UNS_TYPE val1, UNS_TYPE val2)

16282

+{

16283

+ unsigned long i;

16284

+

16285

+ for (i = 0; i < SIZE; i++)

16286

+ ua[i] = (ub[i] == uc[i]) ? val1 : val2;

16287

+}

16288

+

16289

+void

16290

+uns_lt (UNS_TYPE val1, UNS_TYPE val2)

16291

+{

16292

+ unsigned long i;

16293

+

16294

+ for (i = 0; i < SIZE; i++)

16295

+ ua[i] = (ub[i] < uc[i]) ? val1 : val2;

16296

+}

16297

+

16298

+/* { dg-final { scan-assembler-times "\[\t \]vaddudm\[\t \]" 2 } } */

16299

+/* { dg-final { scan-assembler-times "\[\t \]vsubudm\[\t \]" 3 } } */

16300

+/* { dg-final { scan-assembler-times "\[\t \]vmaxsd\[\t \]" 2 } } */

16301

+/* { dg-final { scan-assembler-times "\[\t \]vmaxud\[\t \]" 1 } } */

16302

+/* { dg-final { scan-assembler-times "\[\t \]vminsd\[\t \]" 1 } } */

16303

+/* { dg-final { scan-assembler-times "\[\t \]vminud\[\t \]" 1 } } */

16304

+/* { dg-final { scan-assembler-times "\[\t \]vsld\[\t \]" 2 } } */

16305

+/* { dg-final { scan-assembler-times "\[\t \]vsrad\[\t \]" 1 } } */

16306

+/* { dg-final { scan-assembler-times "\[\t \]vsrd\[\t \]" 1 } } */

16307

+/* { dg-final { scan-assembler-times "\[\t \]vcmpequd\[\t \]" 2 } } */

16308

+/* { dg-final { scan-assembler-times "\[\t \]vcmpgtsd\[\t \]" 1 } } */

16309

+/* { dg-final { scan-assembler-times "\[\t \]vcmpgtud\[\t \]" 1 } } */

16310

Index: gcc/testsuite/gcc.target/powerpc/pr57744.c

16311

===================================================================

16312

--- a/src/gcc/testsuite/gcc.target/powerpc/pr57744.c (.../tags/gcc_4_8_2_release)

16313

+++ b/src/gcc/testsuite/gcc.target/powerpc/pr57744.c (.../branches/gcc-4_8-branch)

16314

@@ -0,0 +1,39 @@

16315

+/* { dg-do run { target { powerpc*-*-* && lp64 } } } */

16316

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

16317

+/* { dg-require-effective-target powerpc_p8vector_ok } */

16318

+/* { dg-options "-mcpu=power8 -O3" } */

16319

+

16320

+void abort (void);

16321

+

16322

+typedef unsigned U_16 __attribute__((mode(TI)));

16323

+

16324

+extern int libat_compare_exchange_16 (U_16 *, U_16 *, U_16, int, int)

16325

+ __attribute__((__noinline__));

16326

+

16327

+/* PR 57744: lqarx/stqcx needs even/odd register pairs. The assembler will

16328

+ complain if the compiler gets an odd/even register pair. Create a function

16329

+ which has the 16 byte compare and exchange instructions, but don't actually

16330

+ execute it, so that we can detect these failures on older machines. */

16331

+

16332

+int

16333

+libat_compare_exchange_16 (U_16 *mptr, U_16 *eptr, U_16 newval,

16334

+ int smodel, int fmodel __attribute__((unused)))

16335

+{

16336

+ if (((smodel) == 0))

16337

+ return __atomic_compare_exchange_n (mptr, eptr, newval, 0, 0, 0);

16338

+ else if (((smodel) != 5))

16339

+ return __atomic_compare_exchange_n (mptr, eptr, newval, 0, 4, 0);

16340

+ else

16341

+ return __atomic_compare_exchange_n (mptr, eptr, newval, 0, 5, 0);

16342

+}

16343

+

16344

+U_16 a = 1, b = 1, c = -2;

16345

+volatile int do_test = 0;

16346

+

16347

+int main (void)

16348

+{

16349

+ if (do_test && !libat_compare_exchange_16 (&a, &b, c, 0, 0))

16350

+ abort ();

16351

+

16352

+ return 0;

16353

+}

16354

Index: gcc/testsuite/gcc.target/powerpc/recip-1.c

16355

===================================================================

16356

--- a/src/gcc/testsuite/gcc.target/powerpc/recip-1.c (.../tags/gcc_4_8_2_release)

16357

+++ b/src/gcc/testsuite/gcc.target/powerpc/recip-1.c (.../branches/gcc-4_8-branch)

16358

@@ -3,8 +3,8 @@

16359

/* { dg-options "-O2 -mrecip -ffast-math -mcpu=power6" } */

16360

/* { dg-final { scan-assembler-times "frsqrte" 2 } } */

16361

/* { dg-final { scan-assembler-times "fmsub" 2 } } */

16362

-/* { dg-final { scan-assembler-times "fmul" 8 } } */

16363

-/* { dg-final { scan-assembler-times "fnmsub" 4 } } */

16364

+/* { dg-final { scan-assembler-times "fmul" 6 } } */

16365

+/* { dg-final { scan-assembler-times "fnmsub" 3 } } */

16366

16367

double

16368

rsqrt_d (double a)

16369

Index: gcc/testsuite/gcc.target/powerpc/darwin-longlong.c

16370

===================================================================

16371

--- a/src/gcc/testsuite/gcc.target/powerpc/darwin-longlong.c (.../tags/gcc_4_8_2_release)

16372

+++ b/src/gcc/testsuite/gcc.target/powerpc/darwin-longlong.c (.../branches/gcc-4_8-branch)

16373

@@ -11,7 +11,11 @@

16374

int i[2];

16375

} ud;

16376

ud.ll = in;

16377

+#ifdef __LITTLE_ENDIAN__

16378

+ return ud.i[1];

16379

+#else

16380

return ud.i[0];

16381

+#endif

16382

}

16383

16384

int main()

16385

Index: gcc/testsuite/gcc.target/powerpc/bool2-p8.c

16386

===================================================================

16387

--- a/src/gcc/testsuite/gcc.target/powerpc/bool2-p8.c (.../tags/gcc_4_8_2_release)

16388

+++ b/src/gcc/testsuite/gcc.target/powerpc/bool2-p8.c (.../branches/gcc-4_8-branch)

16389

@@ -0,0 +1,32 @@

16390

+/* { dg-do compile { target { powerpc*-*-* } } } */

16391

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

16392

+/* { dg-require-effective-target powerpc_p8vector_ok } */

16393

+/* { dg-options "-O2 -mcpu=power8" } */

16394

+/* { dg-final { scan-assembler-not "\[ \t\]and " } } */

16395

+/* { dg-final { scan-assembler-not "\[ \t\]or " } } */

16396

+/* { dg-final { scan-assembler-not "\[ \t\]xor " } } */

16397

+/* { dg-final { scan-assembler-not "\[ \t\]nor " } } */

16398

+/* { dg-final { scan-assembler-not "\[ \t\]eqv " } } */

16399

+/* { dg-final { scan-assembler-not "\[ \t\]andc " } } */

16400

+/* { dg-final { scan-assembler-not "\[ \t\]orc " } } */

16401

+/* { dg-final { scan-assembler-not "\[ \t\]nand " } } */

16402

+/* { dg-final { scan-assembler-not "\[ \t\]vand " } } */

16403

+/* { dg-final { scan-assembler-not "\[ \t\]vandc " } } */

16404

+/* { dg-final { scan-assembler-not "\[ \t\]vor " } } */

16405

+/* { dg-final { scan-assembler-not "\[ \t\]vxor " } } */

16406

+/* { dg-final { scan-assembler-not "\[ \t\]vnor " } } */

16407

+/* { dg-final { scan-assembler "\[ \t\]xxland " } } */

16408

+/* { dg-final { scan-assembler "\[ \t\]xxlor " } } */

16409

+/* { dg-final { scan-assembler "\[ \t\]xxlxor " } } */

16410

+/* { dg-final { scan-assembler "\[ \t\]xxlnor " } } */

16411

+/* { dg-final { scan-assembler "\[ \t\]xxlandc " } } */

16412

+/* { dg-final { scan-assembler "\[ \t\]xxleqv " } } */

16413

+/* { dg-final { scan-assembler "\[ \t\]xxlorc " } } */

16414

+/* { dg-final { scan-assembler "\[ \t\]xxlnand " } } */

16415

+

16416

+#ifndef TYPE

16417

+typedef int v4si __attribute__ ((vector_size (16)));

16418

+#define TYPE v4si

16419

+#endif

16420

+

16421

+#include "bool2.h"

16422

Index: gcc/testsuite/gcc.target/powerpc/mmfpgpr.c

16423

===================================================================

16424

--- a/src/gcc/testsuite/gcc.target/powerpc/mmfpgpr.c (.../tags/gcc_4_8_2_release)

16425

+++ b/src/gcc/testsuite/gcc.target/powerpc/mmfpgpr.c (.../branches/gcc-4_8-branch)

16426

@@ -0,0 +1,22 @@

16427

+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */

16428

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

16429

+/* { dg-require-effective-target powerpc_vsx_ok } */

16430

+/* { dg-options "-O2 -mcpu=power6x -mmfpgpr" } */

16431

+/* { dg-final { scan-assembler "mffgpr" } } */

16432

+/* { dg-final { scan-assembler "mftgpr" } } */

16433

+

16434

+/* Test that we generate the instructions to move between the GPR and FPR

16435

+ registers under power6x. */

16436

+

16437

+extern long return_long (void);

16438

+extern double return_double (void);

16439

+

16440

+double return_double2 (void)

16441

+{

16442

+ return (double) return_long ();

16443

+}

16444

+

16445

+long return_long2 (void)

16446

+{

16447

+ return (long) return_double ();

16448

+}

16449

Index: gcc/testsuite/gcc.target/powerpc/pr60203.c

16450

===================================================================

16451

--- a/src/gcc/testsuite/gcc.target/powerpc/pr60203.c (.../tags/gcc_4_8_2_release)

16452

+++ b/src/gcc/testsuite/gcc.target/powerpc/pr60203.c (.../branches/gcc-4_8-branch)

16453

@@ -0,0 +1,40 @@

16454

+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */

16455

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

16456

+/* { dg-require-effective-target powerpc_p8vector_ok } */

16457

+/* { dg-options "-mcpu=power8 -O3" } */

16458

+

16459

+union u_ld { long double ld; double d[2]; };

16460

+

16461

+long double

16462

+pack (double a, double aa)

16463

+{

16464

+ union u_ld u;

16465

+ u.d[0] = a;

16466

+ u.d[1] = aa;

16467

+ return u.ld;

16468

+}

16469

+

16470

+double

16471

+unpack_0 (long double x)

16472

+{

16473

+ union u_ld u;

16474

+ u.ld = x;

16475

+ return u.d[0];

16476

+}

16477

+

16478

+double

16479

+unpack_1 (long double x)

16480

+{

16481

+ union u_ld u;

16482

+ u.ld = x;

16483

+ return u.d[1];

16484

+}

16485

+

16486

+/* { dg-final { scan-assembler-not "stfd" } } */

16487

+/* { dg-final { scan-assembler-not "lfd" } } */

16488

+/* { dg-final { scan-assembler-not "lxsdx" } } */

16489

+/* { dg-final { scan-assembler-not "stxsdx" } } */

16490

+/* { dg-final { scan-assembler-not "mfvsrd" } } */

16491

+/* { dg-final { scan-assembler-not "mtvsrd" } } */

16492

+

16493

+

16494

Index: gcc/testsuite/gcc.target/powerpc/direct-move-vint1.c

16495

===================================================================

16496

--- a/src/gcc/testsuite/gcc.target/powerpc/direct-move-vint1.c (.../tags/gcc_4_8_2_release)

16497

+++ b/src/gcc/testsuite/gcc.target/powerpc/direct-move-vint1.c (.../branches/gcc-4_8-branch)

16498

@@ -0,0 +1,14 @@

16499

+/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */

16500

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

16501

+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */

16502

+/* { dg-require-effective-target powerpc_p8vector_ok } */

16503

+/* { dg-options "-mcpu=power8 -O2" } */

16504

+/* { dg-final { scan-assembler "mtvsrd" } } */

16505

+/* { dg-final { scan-assembler "mfvsrd" } } */

16506

+

16507

+/* Check code generation for direct move for vector types. */

16508

+

16509

+#define TYPE vector int

16510

+#define VSX_REG_ATTR "wa"

16511

+

16512

+#include "direct-move.h"

16513

Index: gcc/testsuite/gcc.target/powerpc/bool2-av.c

16514

===================================================================

16515

--- a/src/gcc/testsuite/gcc.target/powerpc/bool2-av.c (.../tags/gcc_4_8_2_release)

16516

+++ b/src/gcc/testsuite/gcc.target/powerpc/bool2-av.c (.../branches/gcc-4_8-branch)

16517

@@ -0,0 +1,32 @@

16518

+/* { dg-do compile { target { powerpc*-*-* } } } */

16519

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

16520

+/* { dg-require-effective-target powerpc_altivec_ok } */

16521

+/* { dg-options "-O2 -mcpu=power6 -maltivec" } */

16522

+/* { dg-final { scan-assembler-not "\[ \t\]and " } } */

16523

+/* { dg-final { scan-assembler-not "\[ \t\]or " } } */

16524

+/* { dg-final { scan-assembler-not "\[ \t\]xor " } } */

16525

+/* { dg-final { scan-assembler-not "\[ \t\]nor " } } */

16526

+/* { dg-final { scan-assembler-not "\[ \t\]andc " } } */

16527

+/* { dg-final { scan-assembler-not "\[ \t\]eqv " } } */

16528

+/* { dg-final { scan-assembler-not "\[ \t\]orc " } } */

16529

+/* { dg-final { scan-assembler-not "\[ \t\]nand " } } */

16530

+/* { dg-final { scan-assembler "\[ \t\]vand " } } */

16531

+/* { dg-final { scan-assembler "\[ \t\]vandc " } } */

16532

+/* { dg-final { scan-assembler "\[ \t\]vor " } } */

16533

+/* { dg-final { scan-assembler "\[ \t\]vxor " } } */

16534

+/* { dg-final { scan-assembler "\[ \t\]vnor " } } */

16535

+/* { dg-final { scan-assembler-not "\[ \t\]xxland " } } */

16536

+/* { dg-final { scan-assembler-not "\[ \t\]xxlor " } } */

16537

+/* { dg-final { scan-assembler-not "\[ \t\]xxlxor " } } */

16538

+/* { dg-final { scan-assembler-not "\[ \t\]xxlnor " } } */

16539

+/* { dg-final { scan-assembler-not "\[ \t\]xxlandc " } } */

16540

+/* { dg-final { scan-assembler-not "\[ \t\]xxleqv " } } */

16541

+/* { dg-final { scan-assembler-not "\[ \t\]xxlorc " } } */

16542

+/* { dg-final { scan-assembler-not "\[ \t\]xxlnand " } } */

16543

+

16544

+#ifndef TYPE

16545

+typedef int v4si __attribute__ ((vector_size (16)));

16546

+#define TYPE v4si

16547

+#endif

16548

+

16549

+#include "bool2.h"

16550

Index: gcc/testsuite/gcc.target/powerpc/pr43154.c

16551

===================================================================

16552

--- a/src/gcc/testsuite/gcc.target/powerpc/pr43154.c (.../tags/gcc_4_8_2_release)

16553

+++ b/src/gcc/testsuite/gcc.target/powerpc/pr43154.c (.../branches/gcc-4_8-branch)

16554

@@ -1,5 +1,6 @@

16555

/* { dg-do compile { target { powerpc*-*-* } } } */

16556

/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

16557

+/* { dg-skip-if "" { powerpc*le-*-* } { "*" } { "" } } */

16558

/* { dg-require-effective-target powerpc_vsx_ok } */

16559

/* { dg-options "-O2 -mcpu=power7" } */

16560

16561

Index: gcc/testsuite/gcc.target/powerpc/pr59054.c

16562

===================================================================

16563

--- a/src/gcc/testsuite/gcc.target/powerpc/pr59054.c (.../tags/gcc_4_8_2_release)

16564

+++ b/src/gcc/testsuite/gcc.target/powerpc/pr59054.c (.../branches/gcc-4_8-branch)

16565

@@ -0,0 +1,9 @@

16566

+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */

16567

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

16568

+/* { dg-require-effective-target powerpc_vsx_ok } */

16569

+/* { dg-options "-mcpu=power7 -O0 -m64" } */

16570

+

16571

+long foo (void) { return 0; }

16572

+

16573

+/* { dg-final { scan-assembler-not "xxlor" } } */

16574

+/* { dg-final { scan-assembler-not "stfd" } } */

16575

Index: gcc/testsuite/gcc.target/powerpc/dfp-builtin-2.c

16576

===================================================================

16577

--- a/src/gcc/testsuite/gcc.target/powerpc/dfp-builtin-2.c (.../tags/gcc_4_8_2_release)

16578

+++ b/src/gcc/testsuite/gcc.target/powerpc/dfp-builtin-2.c (.../branches/gcc-4_8-branch)

16579

@@ -0,0 +1,88 @@

16580

+/* { dg-do compile { target { powerpc*-*-linux* } } } */

16581

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

16582

+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */

16583

+/* { dg-require-effective-target powerpc_vsx_ok } */

16584

+/* { dg-options "-mcpu=power7 -O2" } */

16585

+/* { dg-final { scan-assembler-times "ddedpdq " 4 } } */

16586

+/* { dg-final { scan-assembler-times "denbcdq " 2 } } */

16587

+/* { dg-final { scan-assembler-times "dxexq " 1 } } */

16588

+/* { dg-final { scan-assembler-times "diexq " 1 } } */

16589

+/* { dg-final { scan-assembler-times "dscliq " 2 } } */

16590

+/* { dg-final { scan-assembler-times "dscriq " 2 } } */

16591

+/* { dg-final { scan-assembler-not "bl __builtin" } } */

16592

+/* { dg-final { scan-assembler-not "dctqpq" } } */

16593

+/* { dg-final { scan-assembler-not "drdpq" } } */

16594

+/* { dg-final { scan-assembler-not "stfd" } } */

16595

+/* { dg-final { scan-assembler-not "lfd" } } */

16596

+

16597

+_Decimal128

16598

+do_dedpdq_0 (_Decimal128 a)

16599

+{

16600

+ return __builtin_ddedpdq (0, a);

16601

+}

16602

+

16603

+_Decimal128

16604

+do_dedpdq_1 (_Decimal128 a)

16605

+{

16606

+ return __builtin_ddedpdq (1, a);

16607

+}

16608

+

16609

+_Decimal128

16610

+do_dedpdq_2 (_Decimal128 a)

16611

+{

16612

+ return __builtin_ddedpdq (2, a);

16613

+}

16614

+

16615

+_Decimal128

16616

+do_dedpdq_3 (_Decimal128 a)

16617

+{

16618

+ return __builtin_ddedpdq (3, a);

16619

+}

16620

+

16621

+_Decimal128

16622

+do_enbcdq_0 (_Decimal128 a)

16623

+{

16624

+ return __builtin_denbcdq (0, a);

16625

+}

16626

+

16627

+_Decimal128

16628

+do_enbcdq_1 (_Decimal128 a)

16629

+{

16630

+ return __builtin_denbcdq (1, a);

16631

+}

16632

+

16633

+_Decimal128

16634

+do_xexq (_Decimal128 a)

16635

+{

16636

+ return __builtin_dxexq (a);

16637

+}

16638

+

16639

+_Decimal128

16640

+do_iexq (_Decimal128 a, _Decimal128 b)

16641

+{

16642

+ return __builtin_diexq (a, b);

16643

+}

16644

+

16645

+_Decimal128

16646

+do_scliq_1 (_Decimal128 a)

16647

+{

16648

+ return __builtin_dscliq (a, 1);

16649

+}

16650

+

16651

+_Decimal128

16652

+do_scliq_10 (_Decimal128 a)

16653

+{

16654

+ return __builtin_dscliq (a, 10);

16655

+}

16656

+

16657

+_Decimal128

16658

+do_scriq_1 (_Decimal128 a)

16659

+{

16660

+ return __builtin_dscriq (a, 1);

16661

+}

16662

+

16663

+_Decimal128

16664

+do_scriq_10 (_Decimal128 a)

16665

+{

16666

+ return __builtin_dscriq (a, 10);

16667

+}

16668

Index: gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c

16669

===================================================================

16670

--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c (.../tags/gcc_4_8_2_release)

16671

+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c (.../branches/gcc-4_8-branch)

16672

@@ -0,0 +1,204 @@

16673

+/* { dg-do compile { target { powerpc*-*-* } } } */

16674

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

16675

+/* { dg-require-effective-target powerpc_p8vector_ok } */

16676

+/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model -fno-unroll-loops -fno-unroll-all-loops" } */

16677

+

16678

+#include <altivec.h>

16679

+

16680

+typedef vector long long v_sign;

16681

+typedef vector unsigned long long v_uns;

16682

+typedef vector bool long long v_bool;

16683

+

16684

+v_sign sign_add_1 (v_sign a, v_sign b)

16685

+{

16686

+ return __builtin_altivec_vaddudm (a, b);

16687

+}

16688

+

16689

+v_sign sign_add_2 (v_sign a, v_sign b)

16690

+{

16691

+ return vec_add (a, b);

16692

+}

16693

+

16694

+v_sign sign_add_3 (v_sign a, v_sign b)

16695

+{

16696

+ return vec_vaddudm (a, b);

16697

+}

16698

+

16699

+v_sign sign_sub_1 (v_sign a, v_sign b)

16700

+{

16701

+ return __builtin_altivec_vsubudm (a, b);

16702

+}

16703

+

16704

+v_sign sign_sub_2 (v_sign a, v_sign b)

16705

+{

16706

+ return vec_sub (a, b);

16707

+}

16708

+

16709

+

16710

+v_sign sign_sub_3 (v_sign a, v_sign b)

16711

+{

16712

+ return vec_vsubudm (a, b);

16713

+}

16714

+

16715

+v_sign sign_min_1 (v_sign a, v_sign b)

16716

+{

16717

+ return __builtin_altivec_vminsd (a, b);

16718

+}

16719

+

16720

+v_sign sign_min_2 (v_sign a, v_sign b)

16721

+{

16722

+ return vec_min (a, b);

16723

+}

16724

+

16725

+v_sign sign_min_3 (v_sign a, v_sign b)

16726

+{

16727

+ return vec_vminsd (a, b);

16728

+}

16729

+

16730

+v_sign sign_max_1 (v_sign a, v_sign b)

16731

+{

16732

+ return __builtin_altivec_vmaxsd (a, b);

16733

+}

16734

+

16735

+v_sign sign_max_2 (v_sign a, v_sign b)

16736

+{

16737

+ return vec_max (a, b);

16738

+}

16739

+

16740

+v_sign sign_max_3 (v_sign a, v_sign b)

16741

+{

16742

+ return vec_vmaxsd (a, b);

16743

+}

16744

+

16745

+v_sign sign_abs (v_sign a)

16746

+{

16747

+ return vec_abs (a); /* xor, vsubudm, vmaxsd. */

16748

+}

16749

+

16750

+v_bool sign_eq (v_sign a, v_sign b)

16751

+{

16752

+ return vec_cmpeq (a, b);

16753

+}

16754

+

16755

+v_bool sign_lt (v_sign a, v_sign b)

16756

+{

16757

+ return vec_cmplt (a, b);

16758

+}

16759

+

16760

+v_uns uns_add_2 (v_uns a, v_uns b)

16761

+{

16762

+ return vec_add (a, b);

16763

+}

16764

+

16765

+v_uns uns_add_3 (v_uns a, v_uns b)

16766

+{

16767

+ return vec_vaddudm (a, b);

16768

+}

16769

+

16770

+v_uns uns_sub_2 (v_uns a, v_uns b)

16771

+{

16772

+ return vec_sub (a, b);

16773

+}

16774

+

16775

+v_uns uns_sub_3 (v_uns a, v_uns b)

16776

+{

16777

+ return vec_vsubudm (a, b);

16778

+}

16779

+

16780

+v_uns uns_min_2 (v_uns a, v_uns b)

16781

+{

16782

+ return vec_min (a, b);

16783

+}

16784

+

16785

+v_uns uns_min_3 (v_uns a, v_uns b)

16786

+{

16787

+ return vec_vminud (a, b);

16788

+}

16789

+

16790

+v_uns uns_max_2 (v_uns a, v_uns b)

16791

+{

16792

+ return vec_max (a, b);

16793

+}

16794

+

16795

+v_uns uns_max_3 (v_uns a, v_uns b)

16796

+{

16797

+ return vec_vmaxud (a, b);

16798

+}

16799

+

16800

+v_bool uns_eq (v_uns a, v_uns b)

16801

+{

16802

+ return vec_cmpeq (a, b);

16803

+}

16804

+

16805

+v_bool uns_lt (v_uns a, v_uns b)

16806

+{

16807

+ return vec_cmplt (a, b);

16808

+}

16809

+

16810

+v_sign sign_rl_1 (v_sign a, v_sign b)

16811

+{

16812

+ return __builtin_altivec_vrld (a, b);

16813

+}

16814

+

16815

+v_sign sign_rl_2 (v_sign a, v_uns b)

16816

+{

16817

+ return vec_rl (a, b);

16818

+}

16819

+

16820

+v_uns uns_rl_2 (v_uns a, v_uns b)

16821

+{

16822

+ return vec_rl (a, b);

16823

+}

16824

+

16825

+v_sign sign_sl_1 (v_sign a, v_sign b)

16826

+{

16827

+ return __builtin_altivec_vsld (a, b);

16828

+}

16829

+

16830

+v_sign sign_sl_2 (v_sign a, v_uns b)

16831

+{

16832

+ return vec_sl (a, b);

16833

+}

16834

+

16835

+v_sign sign_sl_3 (v_sign a, v_uns b)

16836

+{

16837

+ return vec_vsld (a, b);

16838

+}

16839

+

16840

+v_uns uns_sl_2 (v_uns a, v_uns b)

16841

+{

16842

+ return vec_sl (a, b);

16843

+}

16844

+

16845

+v_uns uns_sl_3 (v_uns a, v_uns b)

16846

+{

16847

+ return vec_vsld (a, b);

16848

+}

16849

+

16850

+v_sign sign_sra_1 (v_sign a, v_sign b)

16851

+{

16852

+ return __builtin_altivec_vsrad (a, b);

16853

+}

16854

+

16855

+v_sign sign_sra_2 (v_sign a, v_uns b)

16856

+{

16857

+ return vec_sra (a, b);

16858

+}

16859

+

16860

+v_sign sign_sra_3 (v_sign a, v_uns b)

16861

+{

16862

+ return vec_vsrad (a, b);

16863

+}

16864

+

16865

+/* { dg-final { scan-assembler-times "vaddudm" 5 } } */

16866

+/* { dg-final { scan-assembler-times "vsubudm" 6 } } */

16867

+/* { dg-final { scan-assembler-times "vmaxsd" 4 } } */

16868

+/* { dg-final { scan-assembler-times "vminsd" 3 } } */

16869

+/* { dg-final { scan-assembler-times "vmaxud" 2 } } */

16870

+/* { dg-final { scan-assembler-times "vminud" 2 } } */

16871

+/* { dg-final { scan-assembler-times "vcmpequd" 2 } } */

16872

+/* { dg-final { scan-assembler-times "vcmpgtsd" 1 } } */

16873

+/* { dg-final { scan-assembler-times "vcmpgtud" 1 } } */

16874

+/* { dg-final { scan-assembler-times "vrld" 3 } } */

16875

+/* { dg-final { scan-assembler-times "vsld" 5 } } */

16876

+/* { dg-final { scan-assembler-times "vsrad" 3 } } */

16877

Index: gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-2.c

16878

===================================================================

16879

--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-2.c (.../tags/gcc_4_8_2_release)

16880

+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-2.c (.../branches/gcc-4_8-branch)

16881

@@ -0,0 +1,30 @@

16882

+/* { dg-do compile { target { powerpc*-*-* } } } */

16883

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

16884

+/* { dg-require-effective-target powerpc_p8vector_ok } */

16885

+/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model" } */

16886

+

16887

+#include <stddef.h>

16888

+

16889

+#ifndef SIZE

16890

+#define SIZE 1024

16891

+#endif

16892

+

16893

+#ifndef ALIGN

16894

+#define ALIGN 32

16895

+#endif

16896

+

16897

+#define ALIGN_ATTR __attribute__((__aligned__(ALIGN)))

16898

+

16899

+long long sign_ll[SIZE] ALIGN_ATTR;

16900

+int sign_i [SIZE] ALIGN_ATTR;

16901

+

16902

+void copy_int_to_long_long (void)

16903

+{

16904

+ size_t i;

16905

+

16906

+ for (i = 0; i < SIZE; i++)

16907

+ sign_ll[i] = sign_i[i];

16908

+}

16909

+

16910

+/* { dg-final { scan-assembler "vupkhsw" } } */

16911

+/* { dg-final { scan-assembler "vupklsw" } } */

16912

Index: gcc/testsuite/gcc.target/powerpc/p8vector-vbpermq.c

16913

===================================================================

16914

--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-vbpermq.c (.../tags/gcc_4_8_2_release)

16915

+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-vbpermq.c (.../branches/gcc-4_8-branch)

16916

@@ -0,0 +1,27 @@

16917

+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */

16918

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

16919

+/* { dg-require-effective-target powerpc_p8vector_ok } */

16920

+/* { dg-options "-O3 -mcpu=power8" } */

16921

+/* { dg-final { scan-assembler "vbpermq" } } */

16922

+/* { dg-final { scan-assembler "mfvsrd" } } */

16923

+/* { dg-final { scan-assembler-not "stfd" } } */

16924

+/* { dg-final { scan-assembler-not "stxvd2x" } } */

16925

+

16926

+#include <altivec.h>

16927

+

16928

+#if __LITTLE_ENDIAN__

16929

+#define OFFSET 1

16930

+#else

16931

+#define OFFSET 0

16932

+#endif

16933

+

16934

+long foos (vector signed char a, vector signed char b)

16935

+{

16936

+ return vec_extract (vec_vbpermq (a, b), OFFSET);

16937

+}

16938

+

16939

+long foou (vector unsigned char a, vector unsigned char b)

16940

+{

16941

+ return vec_extract (vec_vbpermq (a, b), OFFSET);

16942

+}

16943

+

16944

Index: gcc/testsuite/gcc.target/powerpc/bcd-1.c

16945

===================================================================

16946

--- a/src/gcc/testsuite/gcc.target/powerpc/bcd-1.c (.../tags/gcc_4_8_2_release)

16947

+++ b/src/gcc/testsuite/gcc.target/powerpc/bcd-1.c (.../branches/gcc-4_8-branch)

16948

@@ -0,0 +1,27 @@

16949

+/* { dg-do compile { target { powerpc*-*-linux* } } } */

16950

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

16951

+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */

16952

+/* { dg-require-effective-target powerpc_vsx_ok } */

16953

+/* { dg-options "-mcpu=power7 -O2" } */

16954

+/* { dg-final { scan-assembler-times "cdtbcd " 1 } } */

16955

+/* { dg-final { scan-assembler-times "cbcdtd " 1 } } */

16956

+/* { dg-final { scan-assembler-times "addg6s " 1 } } */

16957

+/* { dg-final { scan-assembler-not "bl __builtin" } } */

16958

+

16959

+unsigned int

16960

+to_bcd (unsigned int a)

16961

+{

16962

+ return __builtin_cdtbcd (a);

16963

+}

16964

+

16965

+unsigned int

16966

+from_bcd (unsigned int a)

16967

+{

16968

+ return __builtin_cbcdtd (a);

16969

+}

16970

+

16971

+unsigned int

16972

+bcd_arith (unsigned int a, unsigned int b)

16973

+{

16974

+ return __builtin_addg6s (a, b);

16975

+}

16976

Index: gcc/testsuite/gcc.target/powerpc/pr60735.c

16977

===================================================================

16978

--- a/src/gcc/testsuite/gcc.target/powerpc/pr60735.c (.../tags/gcc_4_8_2_release)

16979

+++ b/src/gcc/testsuite/gcc.target/powerpc/pr60735.c (.../branches/gcc-4_8-branch)

16980

@@ -0,0 +1,11 @@

16981

+/* { dg-do compile } */

16982

+/* { dg-options "-mcpu=8548 -mspe -mabi=spe -O2" } */

16983

+/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */

16984

+

16985

+/* In PR60735, the type _Decimal64 generated an insn not found message. */

16986

+

16987

+void

16988

+pr60735 (_Decimal64 *p, _Decimal64 *q)

16989

+{

16990

+ *p = *q;

16991

+}

16992

Index: gcc/testsuite/gcc.target/powerpc/extend-divide-1.c

16993

===================================================================

16994

--- a/src/gcc/testsuite/gcc.target/powerpc/extend-divide-1.c (.../tags/gcc_4_8_2_release)

16995

+++ b/src/gcc/testsuite/gcc.target/powerpc/extend-divide-1.c (.../branches/gcc-4_8-branch)

16996

@@ -0,0 +1,34 @@

16997

+/* { dg-do compile { target { powerpc*-*-linux* } } } */

16998

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

16999

+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */

17000

+/* { dg-require-effective-target powerpc_vsx_ok } */

17001

+/* { dg-options "-mcpu=power7 -O2" } */

17002

+/* { dg-final { scan-assembler-times "divwe " 1 } } */

17003

+/* { dg-final { scan-assembler-times "divweo " 1 } } */

17004

+/* { dg-final { scan-assembler-times "divweu " 1 } } */

17005

+/* { dg-final { scan-assembler-times "divweuo " 1 } } */

17006

+/* { dg-final { scan-assembler-not "bl __builtin" } } */

17007

+

17008

+int

17009

+div_we (int a, int b)

17010

+{

17011

+ return __builtin_divwe (a, b);

17012

+}

17013

+

17014

+int

17015

+div_weo (int a, int b)

17016

+{

17017

+ return __builtin_divweo (a, b);

17018

+}

17019

+

17020

+unsigned int

17021

+div_weu (unsigned int a, unsigned int b)

17022

+{

17023

+ return __builtin_divweu (a, b);

17024

+}

17025

+

17026

+unsigned int

17027

+div_weuo (unsigned int a, unsigned int b)

17028

+{

17029

+ return __builtin_divweuo (a, b);

17030

+}

17031

Index: gcc/testsuite/gcc.target/powerpc/altivec-perm-3.c

17032

===================================================================

17033

--- a/src/gcc/testsuite/gcc.target/powerpc/altivec-perm-3.c (.../tags/gcc_4_8_2_release)

17034

+++ b/src/gcc/testsuite/gcc.target/powerpc/altivec-perm-3.c (.../branches/gcc-4_8-branch)

17035

@@ -0,0 +1,23 @@

17036

+/* { dg-do compile } */

17037

+/* { dg-require-effective-target powerpc_altivec_ok } */

17038

+/* { dg-skip-if "" { powerpc*le-*-* } { "*" } { "" } } */

17039

+/* { dg-options "-O -maltivec -mno-vsx" } */

17040

+

17041

+typedef unsigned char V __attribute__((vector_size(16)));

17042

+

17043

+V p2(V x, V y)

17044

+{

17045

+ return __builtin_shuffle(x, y,

17046

+ (V){ 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 });

17047

+

17048

+}

17049

+

17050

+V p4(V x, V y)

17051

+{

17052

+ return __builtin_shuffle(x, y,

17053

+ (V){ 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 });

17054

+}

17055

+

17056

+/* { dg-final { scan-assembler-not "vperm" } } */

17057

+/* { dg-final { scan-assembler "vpkuhum" } } */

17058

+/* { dg-final { scan-assembler "vpkuwum" } } */

17059

Index: gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c

17060

===================================================================

17061

--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c (.../tags/gcc_4_8_2_release)

17062

+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c (.../branches/gcc-4_8-branch)

17063

@@ -0,0 +1,85 @@

17064

+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */

17065

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

17066

+/* { dg-require-effective-target powerpc_p8vector_ok } */

17067

+/* { dg-options "-mcpu=power8 -O3 -mvsx-timode" } */

17068

+

17069

+#include <altivec.h>

17070

+

17071

+#ifndef TYPE

17072

+#define TYPE vector __int128_t

17073

+#endif

17074

+

17075

+TYPE

17076

+do_addcuq (TYPE p, TYPE q)

17077

+{

17078

+ return __builtin_vec_vaddcuq (p, q);

17079

+}

17080

+

17081

+TYPE

17082

+do_adduqm (TYPE p, TYPE q)

17083

+{

17084

+ return __builtin_vec_add (p, q);

17085

+}

17086

+

17087

+TYPE

17088

+do_addeuqm (TYPE p, TYPE q, TYPE r)

17089

+{

17090

+ return __builtin_vec_vaddeuqm (p, q, r);

17091

+}

17092

+

17093

+TYPE

17094

+do_addecuq (TYPE p, TYPE q, TYPE r)

17095

+{

17096

+ return __builtin_vec_vaddecuq (p, q, r);

17097

+}

17098

+

17099

+TYPE

17100

+do_subeuqm (TYPE p, TYPE q, TYPE r)

17101

+{

17102

+ return __builtin_vec_vsubeuqm (p, q, r);

17103

+}

17104

+

17105

+TYPE

17106

+do_subecuq (TYPE p, TYPE q, TYPE r)

17107

+{

17108

+ return __builtin_vec_vsubecuq (p, q, r);

17109

+}

17110

+

17111

+TYPE

17112

+do_subcuq (TYPE p, TYPE q)

17113

+{

17114

+ return __builtin_vec_vsubcuq (p, q);

17115

+}

17116

+

17117

+TYPE

17118

+do_subuqm (TYPE p, TYPE q)

17119

+{

17120

+ return __builtin_vec_vsubuqm (p, q);

17121

+}

17122

+

17123

+TYPE

17124

+do_zero (void)

17125

+{

17126

+ return (TYPE) { 0 };

17127

+}

17128

+

17129

+TYPE

17130

+do_minus_one (void)

17131

+{

17132

+ return (TYPE) { -1 };

17133

+}

17134

+

17135

+/* { dg-final { scan-assembler "vaddcuq" } } */

17136

+/* { dg-final { scan-assembler "vadduqm" } } */

17137

+/* { dg-final { scan-assembler "vaddecuq" } } */

17138

+/* { dg-final { scan-assembler "vaddeuqm" } } */

17139

+/* { dg-final { scan-assembler "vsubecuq" } } */

17140

+/* { dg-final { scan-assembler "vsubeuqm" } } */

17141

+/* { dg-final { scan-assembler "vsubcuq" } } */

17142

+/* { dg-final { scan-assembler "vsubuqm" } } */

17143

+/* { dg-final { scan-assembler-not "mtvsrd" } } */

17144

+/* { dg-final { scan-assembler-not "mfvsrd" } } */

17145

+/* { dg-final { scan-assembler-not "ori 2,2,0" } } */

17146

+/* { dg-final { scan-assembler-not "xxpermdi" } } */

17147

+/* { dg-final { scan-assembler-not "stxvd2x" } } */

17148

+/* { dg-final { scan-assembler-not "stxvw4x" } } */

17149

Index: gcc/testsuite/gcc.target/powerpc/pr58673-1.c

17150

===================================================================

17151

--- a/src/gcc/testsuite/gcc.target/powerpc/pr58673-1.c (.../tags/gcc_4_8_2_release)

17152

+++ b/src/gcc/testsuite/gcc.target/powerpc/pr58673-1.c (.../branches/gcc-4_8-branch)

17153

@@ -0,0 +1,78 @@

17154

+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */

17155

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

17156

+/* { dg-require-effective-target powerpc_p8vector_ok } */

17157

+/* { dg-options "-mcpu=power8 -m64 -O1" } */

17158

+

17159

+enum typecode

17160

+{

17161

+ QIcode, QUcode, HIcode, HUcode, SIcode, SUcode, DIcode, DUcode, SFcode,

17162

+ DFcode, XFcode, Pcode, Tcode, LAST_AND_UNUSED_TYPECODE

17163

+};

17164

+enum bytecode_opcode

17165

+{

17166

+ neverneverland, drop, duplicate, over, setstackSI, adjstackSI, constQI,

17167

+ constHI, constSI, constDI, constSF, constDF, constXF, constP, loadQI,

17168

+ loadHI, loadSI, loadDI, loadSF, loadDF, loadXF, loadP, storeQI, storeHI,

17169

+ storeSI, storeDI, storeSF, storeDF, storeXF, storeP, storeBLK, clearBLK,

17170

+ addconstPSI, newlocalSI, localP, argP, convertQIHI, convertHISI,

17171

+ convertSIDI, convertQISI, convertQUHU, convertHUSU, convertSUDU,

17172

+ convertQUSU, convertSFDF, convertDFXF, convertHIQI, convertSIHI,

17173

+ convertDISI, convertSIQI, convertSUQU, convertDFSF, convertXFDF,

17174

+ convertSISF, convertSIDF, convertSIXF, convertSUSF, convertSUDF,

17175

+ convertSUXF, convertDISF, convertDIDF, convertDIXF, convertDUSF,

17176

+ convertDUDF, convertDUXF, convertSFSI, convertDFSI, convertXFSI,

17177

+ convertSFSU, convertDFSU, convertXFSU, convertSFDI, convertDFDI,

17178

+ convertXFDI, convertSFDU, convertDFDU, convertXFDU, convertPSI,

17179

+ convertSIP, convertSIT, convertDIT, convertSFT, convertDFT, convertXFT,

17180

+ convertPT, zxloadBI, sxloadBI, sstoreBI, addSI, addDI, addSF, addDF,

17181

+ addXF, addPSI, subSI, subDI, subSF, subDF, subXF, subPP, mulSI, mulDI,

17182

+ mulSU, mulDU, mulSF, mulDF, mulXF, divSI, divDI, divSU, divDU, divSF,

17183

+ divDF, divXF, modSI, modDI, modSU, modDU, andSI, andDI, iorSI, iorDI,

17184

+ xorSI, xorDI, lshiftSI, lshiftSU, lshiftDI, lshiftDU, rshiftSI, rshiftSU,

17185

+ rshiftDI, rshiftDU, ltSI, ltSU, ltDI, ltDU, ltSF, ltDF, ltXF, ltP, leSI,

17186

+ leSU, leDI, leDU, leSF, leDF, leXF, leP, geSI, geSU, geDI, geDU, geSF,

17187

+ geDF, geXF, geP, gtSI, gtSU, gtDI, gtDU, gtSF, gtDF, gtXF, gtP, eqSI,

17188

+ eqDI, eqSF, eqDF, eqXF, eqP, neSI, neDI, neSF, neDF, neXF, neP, negSI,

17189

+ negDI, negSF, negDF, negXF, notSI, notDI, notT, predecQI, predecHI,

17190

+ predecSI, predecDI, predecP, predecSF, predecDF, predecXF, predecBI,

17191

+ preincQI, preincHI, preincSI, preincDI, preincP, preincSF, preincDF,

17192

+ preincXF, preincBI, postdecQI, postdecHI, postdecSI, postdecDI, postdecP,

17193

+ postdecSF, postdecDF, postdecXF, postdecBI, postincQI, postincHI,

17194

+ postincSI, postincDI, postincP, postincSF, postincDF, postincXF,

17195

+ postincBI, xjumpif, xjumpifnot, jump, jumpP, caseSI, caseSU, caseDI,

17196

+ caseDU, call, returnP, ret, linenote, LAST_AND_UNUSED_OPCODE

17197

+};

17198

+struct binary_operator

17199

+{

17200

+ enum bytecode_opcode opcode;

17201

+ enum typecode arg0;

17202

+};

17203

+static struct conversion_recipe

17204

+{

17205

+ unsigned char *opcodes;

17206

+ int cost;

17207

+}

17208

+conversion_recipe[((int) LAST_AND_UNUSED_TYPECODE)][((int)

17209

+ LAST_AND_UNUSED_TYPECODE)];

17210

+static struct conversion_recipe

17211

+deduce_conversion (from, to)

17212

+ enum typecode from, to;

17213

+{

17214

+ (conversion_recipe[(int) from][(int) to].

17215

+ opcodes ? 0 : (conversion_recipe[(int) from][(int) to] =

17216

+ deduce_conversion (from, to), 0));

17217

+}

17218

+

17219

+void

17220

+bc_expand_binary_operation (optab, resulttype, arg0, arg1)

17221

+ struct binary_operator optab[];

17222

+{

17223

+ int i, besti, cost, bestcost;

17224

+ enum typecode resultcode, arg0code;

17225

+ for (i = 0; optab[i].opcode != -1; ++i)

17226

+ {

17227

+ (conversion_recipe[(int) arg0code][(int) optab[i].arg0].

17228

+ opcodes ? 0 : (conversion_recipe[(int) arg0code][(int) optab[i].arg0] =

17229

+ deduce_conversion (arg0code, optab[i].arg0), 0));

17230

+ }

17231

+}

17232

Index: gcc/testsuite/gcc.target/powerpc/no-r11-1.c

17233

===================================================================

17234

--- a/src/gcc/testsuite/gcc.target/powerpc/no-r11-1.c (.../tags/gcc_4_8_2_release)

17235

+++ b/src/gcc/testsuite/gcc.target/powerpc/no-r11-1.c (.../branches/gcc-4_8-branch)

17236

@@ -1,5 +1,6 @@

17237

/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */

17238

/* { dg-skip-if "" { *-*-darwin* } { "*" } { "" } } */

17239

+/* { dg-skip-if "" { powerpc_elfv2 } { "*" } { "" } } */

17240

/* { dg-options "-O2 -mno-pointers-to-nested-functions" } */

17241

17242

int

17243

Index: gcc/testsuite/gcc.target/powerpc/p8vector-fp.c

17244

===================================================================

17245

--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-fp.c (.../tags/gcc_4_8_2_release)

17246

+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-fp.c (.../branches/gcc-4_8-branch)

17247

@@ -0,0 +1,139 @@

17248

+/* { dg-do compile { target { powerpc*-*-* } } } */

17249

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

17250

+/* { dg-require-effective-target powerpc_p8vector_ok } */

17251

+/* { dg-options "-mcpu=power8 -O2 -mupper-regs-df -mupper-regs-sf -fno-math-errno" } */

17252

+

17253

+float abs_sf (float *p)

17254

+{

17255

+ float f = *p;

17256

+ __asm__ ("# reg %x0" : "+v" (f));

17257

+ return __builtin_fabsf (f);

17258

+}

17259

+

17260

+float nabs_sf (float *p)

17261

+{

17262

+ float f = *p;

17263

+ __asm__ ("# reg %x0" : "+v" (f));

17264

+ return - __builtin_fabsf (f);

17265

+}

17266

+

17267

+float neg_sf (float *p)

17268

+{

17269

+ float f = *p;

17270

+ __asm__ ("# reg %x0" : "+v" (f));

17271

+ return - f;

17272

+}

17273

+

17274

+float add_sf (float *p, float *q)

17275

+{

17276

+ float f1 = *p;

17277

+ float f2 = *q;

17278

+ __asm__ ("# reg %x0, %x1" : "+v" (f1), "+v" (f2));

17279

+ return f1 + f2;

17280

+}

17281

+

17282

+float sub_sf (float *p, float *q)

17283

+{

17284

+ float f1 = *p;

17285

+ float f2 = *q;

17286

+ __asm__ ("# reg %x0, %x1" : "+v" (f1), "+v" (f2));

17287

+ return f1 - f2;

17288

+}

17289

+

17290

+float mul_sf (float *p, float *q)

17291

+{

17292

+ float f1 = *p;

17293

+ float f2 = *q;

17294

+ __asm__ ("# reg %x0, %x1" : "+v" (f1), "+v" (f2));

17295

+ return f1 * f2;

17296

+}

17297

+

17298

+float div_sf (float *p, float *q)

17299

+{

17300

+ float f1 = *p;

17301

+ float f2 = *q;

17302

+ __asm__ ("# reg %x0, %x1" : "+v" (f1), "+v" (f2));

17303

+ return f1 / f2;

17304

+}

17305

+

17306

+float sqrt_sf (float *p)

17307

+{

17308

+ float f = *p;

17309

+ __asm__ ("# reg %x0" : "+v" (f));

17310

+ return __builtin_sqrtf (f);

17311

+}

17312

+

17313

+

17314

+double abs_df (double *p)

17315

+{

17316

+ double d = *p;

17317

+ __asm__ ("# reg %x0" : "+v" (d));

17318

+ return __builtin_fabs (d);

17319

+}

17320

+

17321

+double nabs_df (double *p)

17322

+{

17323

+ double d = *p;

17324

+ __asm__ ("# reg %x0" : "+v" (d));

17325

+ return - __builtin_fabs (d);

17326

+}

17327

+

17328

+double neg_df (double *p)

17329

+{

17330

+ double d = *p;

17331

+ __asm__ ("# reg %x0" : "+v" (d));

17332

+ return - d;

17333

+}

17334

+

17335

+double add_df (double *p, double *q)

17336

+{

17337

+ double d1 = *p;

17338

+ double d2 = *q;

17339

+ __asm__ ("# reg %x0, %x1" : "+v" (d1), "+v" (d2));

17340

+ return d1 + d2;

17341

+}

17342

+

17343

+double sub_df (double *p, double *q)

17344

+{

17345

+ double d1 = *p;

17346

+ double d2 = *q;

17347

+ __asm__ ("# reg %x0, %x1" : "+v" (d1), "+v" (d2));

17348

+ return d1 - d2;

17349

+}

17350

+

17351

+double mul_df (double *p, double *q)

17352

+{

17353

+ double d1 = *p;

17354

+ double d2 = *q;

17355

+ __asm__ ("# reg %x0, %x1" : "+v" (d1), "+v" (d2));

17356

+ return d1 * d2;

17357

+}

17358

+

17359

+double div_df (double *p, double *q)

17360

+{

17361

+ double d1 = *p;

17362

+ double d2 = *q;

17363

+ __asm__ ("# reg %x0, %x1" : "+v" (d1), "+v" (d2));

17364

+ return d1 / d2;

17365

+}

17366

+

17367

+double sqrt_df (float *p)

17368

+{

17369

+ double d = *p;

17370

+ __asm__ ("# reg %x0" : "+v" (d));

17371

+ return __builtin_sqrt (d);

17372

+}

17373

+

17374

+/* { dg-final { scan-assembler "xsabsdp" } } */

17375

+/* { dg-final { scan-assembler "xsadddp" } } */

17376

+/* { dg-final { scan-assembler "xsaddsp" } } */

17377

+/* { dg-final { scan-assembler "xsdivdp" } } */

17378

+/* { dg-final { scan-assembler "xsdivsp" } } */

17379

+/* { dg-final { scan-assembler "xsmuldp" } } */

17380

+/* { dg-final { scan-assembler "xsmulsp" } } */

17381

+/* { dg-final { scan-assembler "xsnabsdp" } } */

17382

+/* { dg-final { scan-assembler "xsnegdp" } } */

17383

+/* { dg-final { scan-assembler "xssqrtdp" } } */

17384

+/* { dg-final { scan-assembler "xssqrtsp" } } */

17385

+/* { dg-final { scan-assembler "xssubdp" } } */

17386

+/* { dg-final { scan-assembler "xssubsp" } } */

17387

Index: gcc/testsuite/gcc.target/powerpc/direct-move-vint2.c

17388

===================================================================

17389

--- a/src/gcc/testsuite/gcc.target/powerpc/direct-move-vint2.c (.../tags/gcc_4_8_2_release)

17390

+++ b/src/gcc/testsuite/gcc.target/powerpc/direct-move-vint2.c (.../branches/gcc-4_8-branch)

17391

@@ -0,0 +1,13 @@

17392

+/* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */

17393

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

17394

+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */

17395

+/* { dg-require-effective-target p8vector_hw } */

17396

+/* { dg-options "-mcpu=power8 -O2" } */

17397

+

17398

+/* Check whether we get the right bits for direct move at runtime. */

17399

+

17400

+#define TYPE vector int

17401

+#define DO_MAIN

17402

+#define VSX_REG_ATTR "wa"

17403

+

17404

+#include "direct-move.h"

17405

Index: gcc/testsuite/gcc.target/powerpc/bool3-p7.c

17406

===================================================================

17407

--- a/src/gcc/testsuite/gcc.target/powerpc/bool3-p7.c (.../tags/gcc_4_8_2_release)

17408

+++ b/src/gcc/testsuite/gcc.target/powerpc/bool3-p7.c (.../branches/gcc-4_8-branch)

17409

@@ -0,0 +1,37 @@

17410

+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */

17411

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

17412

+/* { dg-require-effective-target powerpc_vsx_ok } */

17413

+/* { dg-options "-O2 -mcpu=power7" } */

17414

+/* { dg-final { scan-assembler "\[ \t\]and " } } */

17415

+/* { dg-final { scan-assembler "\[ \t\]or " } } */

17416

+/* { dg-final { scan-assembler "\[ \t\]xor " } } */

17417

+/* { dg-final { scan-assembler "\[ \t\]nor " } } */

17418

+/* { dg-final { scan-assembler "\[ \t\]andc " } } */

17419

+/* { dg-final { scan-assembler-not "\[ \t\]vand " } } */

17420

+/* { dg-final { scan-assembler-not "\[ \t\]vandc " } } */

17421

+/* { dg-final { scan-assembler-not "\[ \t\]vor " } } */

17422

+/* { dg-final { scan-assembler-not "\[ \t\]vxor " } } */

17423

+/* { dg-final { scan-assembler-not "\[ \t\]vnor " } } */

17424

+/* { dg-final { scan-assembler-not "\[ \t\]xxland " } } */

17425

+/* { dg-final { scan-assembler-not "\[ \t\]xxlor " } } */

17426

+/* { dg-final { scan-assembler-not "\[ \t\]xxlxor " } } */

17427

+/* { dg-final { scan-assembler-not "\[ \t\]xxlnor " } } */

17428

+/* { dg-final { scan-assembler-not "\[ \t\]xxlandc " } } */

17429

+/* { dg-final { scan-assembler-not "\[ \t\]xxleqv " } } */

17430

+/* { dg-final { scan-assembler-not "\[ \t\]xxlorc " } } */

17431

+/* { dg-final { scan-assembler-not "\[ \t\]xxlnand " } } */

17432

+

17433

+/* On power7, for 128-bit types, ORC/ANDC/EQV might not show up, since the

17434

+ vector unit doesn't support these, so the appropriate combine patterns may

17435

+ not be generated. */

17436

+

17437

+#ifndef TYPE

17438

+#ifdef _ARCH_PPC64

17439

+#define TYPE __int128_t

17440

+#else

17441

+typedef int v4si __attribute__ ((vector_size (16)));

17442

+#define TYPE v4si

17443

+#endif

17444

+#endif

17445

+

17446

+#include "bool3.h"

17447

Index: gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c

17448

===================================================================

17449

--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c (.../tags/gcc_4_8_2_release)

17450

+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c (.../branches/gcc-4_8-branch)

17451

@@ -0,0 +1,104 @@

17452

+/* { dg-do compile { target { powerpc*-*-* } } } */

17453

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

17454

+/* { dg-require-effective-target powerpc_p8vector_ok } */

17455

+/* { dg-options "-mcpu=power8 -O3 -ftree-vectorize -fvect-cost-model" } */

17456

+

17457

+#include <altivec.h>

17458

+

17459

+typedef vector long long vll_sign;

17460

+typedef vector unsigned long long vll_uns;

17461

+typedef vector bool long long vll_bool;

17462

+

17463

+typedef vector int vi_sign;

17464

+typedef vector unsigned int vi_uns;

17465

+typedef vector bool int vi_bool;

17466

+

17467

+typedef vector short vs_sign;

17468

+typedef vector unsigned short vs_uns;

17469

+typedef vector bool short vs_bool;

17470

+

17471

+typedef vector signed char vc_sign;

17472

+typedef vector unsigned char vc_uns;

17473

+typedef vector bool char vc_bool;

17474

+

17475

+

17476

+vi_sign vi_pack_1 (vll_sign a, vll_sign b)

17477

+{

17478

+ return __builtin_altivec_vpkudum (a, b);

17479

+}

17480

+

17481

+vi_sign vi_pack_2 (vll_sign a, vll_sign b)

17482

+{

17483

+ return vec_pack (a, b);

17484

+}

17485

+

17486

+vi_sign vi_pack_3 (vll_sign a, vll_sign b)

17487

+{

17488

+ return vec_vpkudum (a, b);

17489

+}

17490

+

17491

+vs_sign vs_pack_1 (vi_sign a, vi_sign b)

17492

+{

17493

+ return __builtin_altivec_vpkuwum (a, b);

17494

+}

17495

+

17496

+vs_sign vs_pack_2 (vi_sign a, vi_sign b)

17497

+{

17498

+ return vec_pack (a, b);

17499

+}

17500

+

17501

+vs_sign vs_pack_3 (vi_sign a, vi_sign b)

17502

+{

17503

+ return vec_vpkuwum (a, b);

17504

+}

17505

+

17506

+vc_sign vc_pack_1 (vs_sign a, vs_sign b)

17507

+{

17508

+ return __builtin_altivec_vpkuhum (a, b);

17509

+}

17510

+

17511

+vc_sign vc_pack_2 (vs_sign a, vs_sign b)

17512

+{

17513

+ return vec_pack (a, b);

17514

+}

17515

+

17516

+vc_sign vc_pack_3 (vs_sign a, vs_sign b)

17517

+{

17518

+ return vec_vpkuhum (a, b);

17519

+}

17520

+

17521

+vll_sign vll_unpack_hi_1 (vi_sign a)

17522

+{

17523

+ return __builtin_altivec_vupkhsw (a);

17524

+}

17525

+

17526

+vll_sign vll_unpack_hi_2 (vi_sign a)

17527

+{

17528

+ return vec_unpackh (a);

17529

+}

17530

+

17531

+vll_sign vll_unpack_hi_3 (vi_sign a)

17532

+{

17533

+ return __builtin_vec_vupkhsw (a);

17534

+}

17535

+

17536

+vll_sign vll_unpack_lo_1 (vi_sign a)

17537

+{

17538

+ return vec_vupklsw (a);

17539

+}

17540

+

17541

+vll_sign vll_unpack_lo_2 (vi_sign a)

17542

+{

17543

+ return vec_unpackl (a);

17544

+}

17545

+

17546

+vll_sign vll_unpack_lo_3 (vi_sign a)

17547

+{

17548

+ return vec_vupklsw (a);

17549

+}

17550

+

17551

+/* { dg-final { scan-assembler-times "vpkudum" 3 } } */

17552

+/* { dg-final { scan-assembler-times "vpkuwum" 3 } } */

17553

+/* { dg-final { scan-assembler-times "vpkuhum" 3 } } */

17554

+/* { dg-final { scan-assembler-times "vupklsw" 3 } } */

17555

+/* { dg-final { scan-assembler-times "vupkhsw" 3 } } */

17556

Index: gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-3.c

17557

===================================================================

17558

--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-3.c (.../tags/gcc_4_8_2_release)

17559

+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-3.c (.../branches/gcc-4_8-branch)

17560

@@ -0,0 +1,29 @@

17561

+/* { dg-do compile { target { powerpc*-*-* } } } */

17562

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

17563

+/* { dg-require-effective-target powerpc_p8vector_ok } */

17564

+/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model" } */

17565

+

17566

+#include <stddef.h>

17567

+

17568

+#ifndef SIZE

17569

+#define SIZE 1024

17570

+#endif

17571

+

17572

+#ifndef ALIGN

17573

+#define ALIGN 32

17574

+#endif

17575

+

17576

+#define ALIGN_ATTR __attribute__((__aligned__(ALIGN)))

17577

+

17578

+long long sign_ll[SIZE] ALIGN_ATTR;

17579

+int sign_i [SIZE] ALIGN_ATTR;

17580

+

17581

+void copy_long_long_to_int (void)

17582

+{

17583

+ size_t i;

17584

+

17585

+ for (i = 0; i < SIZE; i++)

17586

+ sign_i[i] = sign_ll[i];

17587

+}

17588

+

17589

+/* { dg-final { scan-assembler "vpkudum" } } */

17590

Index: gcc/testsuite/gcc.target/powerpc/direct-move.h

17591

===================================================================

17592

--- a/src/gcc/testsuite/gcc.target/powerpc/direct-move.h (.../tags/gcc_4_8_2_release)

17593

+++ b/src/gcc/testsuite/gcc.target/powerpc/direct-move.h (.../branches/gcc-4_8-branch)

17594

@@ -0,0 +1,188 @@

17595

+/* Test functions for direct move support. */

17596

+

17597

+#include <math.h>

17598

+extern void abort (void);

17599

+

17600

+#ifndef VSX_REG_ATTR

17601

+#define VSX_REG_ATTR "wa"

17602

+#endif

17603

+

17604

+void __attribute__((__noinline__))

17605

+copy (TYPE *a, TYPE *b)

17606

+{

17607

+ *b = *a;

17608

+}

17609

+

17610

+#ifndef NO_GPR

17611

+void __attribute__((__noinline__))

17612

+load_gpr (TYPE *a, TYPE *b)

17613

+{

17614

+ TYPE c = *a;

17615

+ __asm__ ("# gpr, reg = %0" : "+b" (c));

17616

+ *b = c;

17617

+}

17618

+#endif

17619

+

17620

+#ifndef NO_FPR

17621

+void __attribute__((__noinline__))

17622

+load_fpr (TYPE *a, TYPE *b)

17623

+{

17624

+ TYPE c = *a;

17625

+ __asm__ ("# fpr, reg = %0" : "+d" (c));

17626

+ *b = c;

17627

+}

17628

+#endif

17629

+

17630

+#ifndef NO_ALTIVEC

17631

+void __attribute__((__noinline__))

17632

+load_altivec (TYPE *a, TYPE *b)

17633

+{

17634

+ TYPE c = *a;

17635

+ __asm__ ("# altivec, reg = %0" : "+v" (c));

17636

+ *b = c;

17637

+}

17638

+#endif

17639

+

17640

+#ifndef NO_VSX

17641

+void __attribute__((__noinline__))

17642

+load_vsx (TYPE *a, TYPE *b)

17643

+{

17644

+ TYPE c = *a;

17645

+ __asm__ ("# vsx, reg = %x0" : "+" VSX_REG_ATTR (c));

17646

+ *b = c;

17647

+}

17648

+#endif

17649

+

17650

+#ifndef NO_GPR_TO_VSX

17651

+void __attribute__((__noinline__))

17652

+load_gpr_to_vsx (TYPE *a, TYPE *b)

17653

+{

17654

+ TYPE c = *a;

17655

+ TYPE d;

17656

+ __asm__ ("# gpr, reg = %0" : "+b" (c));

17657

+ d = c;

17658

+ __asm__ ("# vsx, reg = %x0" : "+" VSX_REG_ATTR (d));

17659

+ *b = d;

17660

+}

17661

+#endif

17662

+

17663

+#ifndef NO_VSX_TO_GPR

17664

+void __attribute__((__noinline__))

17665

+load_vsx_to_gpr (TYPE *a, TYPE *b)

17666

+{

17667

+ TYPE c = *a;

17668

+ TYPE d;

17669

+ __asm__ ("# vsx, reg = %x0" : "+" VSX_REG_ATTR (c));

17670

+ d = c;

17671

+ __asm__ ("# gpr, reg = %0" : "+b" (d));

17672

+ *b = d;

17673

+}

17674

+#endif

17675

+

17676

+#ifdef DO_MAIN

17677

+typedef void (fn_type (TYPE *, TYPE *));

17678

+

17679

+struct test_struct {

17680

+ fn_type *func;

17681

+ const char *name;

17682

+};

17683

+

17684

+const struct test_struct test_functions[] = {

17685

+ { copy, "copy" },

17686

+#ifndef NO_GPR

17687

+ { load_gpr, "load_gpr" },

17688

+#endif

17689

+#ifndef NO_FPR

17690

+ { load_fpr, "load_fpr" },

17691

+#endif

17692

+#ifndef NO_ALTIVEC

17693

+ { load_altivec, "load_altivec" },

17694

+#endif

17695

+#ifndef NO_VSX

17696

+ { load_vsx, "load_vsx" },

17697

+#endif

17698

+#ifndef NO_GPR_TO_VSX

17699

+ { load_gpr_to_vsx, "load_gpr_to_vsx" },

17700

+#endif

17701

+#ifndef NO_VSX_TO_GPR

17702

+ { load_vsx_to_gpr, "load_vsx_to_gpr" },

17703

+#endif

17704

+};

17705

+

17706

+/* Test a given value for each of the functions. */

17707

+void __attribute__((__noinline__))

17708

+test_value (TYPE a)

17709

+{

17710

+ long i;

17711

+

17712

+ for (i = 0; i < sizeof (test_functions) / sizeof (test_functions[0]); i++)

17713

+ {

17714

+ TYPE b;

17715

+

17716

+ test_functions[i].func (&a, &b);

17717

+ if (memcmp ((void *)&a, (void *)&b, sizeof (TYPE)) != 0)

17718

+ abort ();

17719

+ }

17720

+}

17721

+

17722

+/* Main program. */

17723

+int

17724

+main (void)

17725

+{

17726

+ long i,j;

17727

+ union {

17728

+ TYPE value;

17729

+ unsigned char bytes[sizeof (TYPE)];

17730

+ } u;

17731

+

17732

+#if IS_INT

17733

+ TYPE value = (TYPE)-5;

17734

+ for (i = 0; i < 12; i++)

17735

+ {

17736

+ test_value (value);

17737

+ value++;

17738

+ }

17739

+

17740

+ for (i = 0; i < 8*sizeof (TYPE); i++)

17741

+ test_value (((TYPE)1) << i);

17742

+

17743

+#elif IS_UNS

17744

+ TYPE value = (TYPE)0;

17745

+ for (i = 0; i < 10; i++)

17746

+ {

17747

+ test_value (value);

17748

+ test_value (~ value);

17749

+ value++;

17750

+ }

17751

+

17752

+ for (i = 0; i < 8*sizeof (TYPE); i++)

17753

+ test_value (((TYPE)1) << i);

17754

+

17755

+#elif IS_FLOAT

17756

+ TYPE value = (TYPE)-5;

17757

+ for (i = 0; i < 12; i++)

17758

+ {

17759

+ test_value (value);

17760

+ value++;

17761

+ }

17762

+

17763

+ test_value ((TYPE)3.1415926535);

17764

+ test_value ((TYPE)1.23456);

17765

+ test_value ((TYPE)(-0.0));

17766

+ test_value ((TYPE)NAN);

17767

+ test_value ((TYPE)+INFINITY);

17768

+ test_value ((TYPE)-INFINITY);

17769

+#else

17770

+

17771

+ for (j = 0; j < 10; j++)

17772

+ {

17773

+ for (i = 0; i < sizeof (TYPE); i++)

17774

+ u.bytes[i] = (unsigned char) (random () >> 4);

17775

+

17776

+ test_value (u.value);

17777

+ }

17778

+#endif

17779

+

17780

+ return 0;

17781

+}

17782

+#endif

17783

Index: gcc/testsuite/gcc.target/powerpc/sd-vsx.c

17784

===================================================================

17785

--- a/src/gcc/testsuite/gcc.target/powerpc/sd-vsx.c (.../tags/gcc_4_8_2_release)

17786

+++ b/src/gcc/testsuite/gcc.target/powerpc/sd-vsx.c (.../branches/gcc-4_8-branch)

17787

@@ -0,0 +1,20 @@

17788

+/* { dg-do compile { target { powerpc*-*-* } } } */

17789

+/* { dg-skip-if "" { powerpc*-*-darwin* powerpc-ibm-aix* } { "*" } { "" } } */

17790

+/* { dg-require-effective-target powerpc_vsx_ok } */

17791

+/* { dg-options "-O2 -mcpu=power7 -mhard-dfp" } */

17792

+/* { dg-final { scan-assembler-times "lfiwzx" 2 } } */

17793

+/* { dg-final { scan-assembler-times "stfiwx" 1 } } */

17794

+/* { dg-final { scan-assembler-not "lfd" } } */

17795

+/* { dg-final { scan-assembler-not "stfd" } } */

17796

+/* { dg-final { scan-assembler-times "dctdp" 2 } } */

17797

+/* { dg-final { scan-assembler-times "dadd" 1 } } */

17798

+/* { dg-final { scan-assembler-times "drsp" 1 } } */

17799

+

17800

+/* Test that power7 can directly load/store SDmode variables without using a

17801

+ bounce buffer. */

17802

+_Decimal32 a;

17803

+

17804

+void inc_dec32 (void)

17805

+{

17806

+ a += (_Decimal32) 1.0;

17807

+}

17808

Index: gcc/testsuite/gcc.target/powerpc/bcd-2.c

17809

===================================================================

17810

--- a/src/gcc/testsuite/gcc.target/powerpc/bcd-2.c (.../tags/gcc_4_8_2_release)

17811

+++ b/src/gcc/testsuite/gcc.target/powerpc/bcd-2.c (.../branches/gcc-4_8-branch)

17812

@@ -0,0 +1,44 @@

17813

+/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */

17814

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

17815

+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */

17816

+/* { dg-require-effective-target powerpc_p8vector_ok } */

17817

+/* { dg-options "-mcpu=power8 -O2" } */

17818

+/* { dg-final { scan-assembler-times "bcdadd\[.\] " 2 } } */

17819

+/* { dg-final { scan-assembler-times "bcdsub\[.\] " 2 } } */

17820

+/* { dg-final { scan-assembler-not "bl __builtin" } } */

17821

+/* { dg-final { scan-assembler-not "mtvsr" } } */

17822

+/* { dg-final { scan-assembler-not "mfvsr" } } */

17823

+/* { dg-final { scan-assembler-not "lvx" } } */

17824

+/* { dg-final { scan-assembler-not "lxvw4x" } } */

17825

+/* { dg-final { scan-assembler-not "lxvd2x" } } */

17826

+/* { dg-final { scan-assembler-not "stvx" } } */

17827

+/* { dg-final { scan-assembler-not "stxvw4x" } } */

17828

+/* { dg-final { scan-assembler-not "stxvd2x" } } */

17829

+

17830

+typedef __int128_t __attribute__((__vector_size__(16))) vector_128_t;

17831

+typedef __int128_t scalar_128_t;

17832

+typedef unsigned long long scalar_64_t;

17833

+

17834

+vector_128_t

17835

+do_add_0 (vector_128_t a, vector_128_t b)

17836

+{

17837

+ return __builtin_bcdadd (a, b, 0);

17838

+}

17839

+

17840

+vector_128_t

17841

+do_add_1 (vector_128_t a, vector_128_t b)

17842

+{

17843

+ return __builtin_bcdadd (a, b, 1);

17844

+}

17845

+

17846

+vector_128_t

17847

+do_sub_0 (vector_128_t a, vector_128_t b)

17848

+{

17849

+ return __builtin_bcdsub (a, b, 0);

17850

+}

17851

+

17852

+vector_128_t

17853

+do_sub_1 (vector_128_t a, vector_128_t b)

17854

+{

17855

+ return __builtin_bcdsub (a, b, 1);

17856

+}

17857

Index: gcc/testsuite/gcc.target/powerpc/extend-divide-2.c

17858

===================================================================

17859

--- a/src/gcc/testsuite/gcc.target/powerpc/extend-divide-2.c (.../tags/gcc_4_8_2_release)

17860

+++ b/src/gcc/testsuite/gcc.target/powerpc/extend-divide-2.c (.../branches/gcc-4_8-branch)

17861

@@ -0,0 +1,34 @@

17862

+/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */

17863

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

17864

+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */

17865

+/* { dg-require-effective-target powerpc_vsx_ok } */

17866

+/* { dg-options "-mcpu=power7 -O2" } */

17867

+/* { dg-final { scan-assembler-times "divde " 1 } } */

17868

+/* { dg-final { scan-assembler-times "divdeo " 1 } } */

17869

+/* { dg-final { scan-assembler-times "divdeu " 1 } } */

17870

+/* { dg-final { scan-assembler-times "divdeuo " 1 } } */

17871

+/* { dg-final { scan-assembler-not "bl __builtin" } } */

17872

+

17873

+long

17874

+div_de (long a, long b)

17875

+{

17876

+ return __builtin_divde (a, b);

17877

+}

17878

+

17879

+long

17880

+div_deo (long a, long b)

17881

+{

17882

+ return __builtin_divdeo (a, b);

17883

+}

17884

+

17885

+unsigned long

17886

+div_deu (unsigned long a, unsigned long b)

17887

+{

17888

+ return __builtin_divdeu (a, b);

17889

+}

17890

+

17891

+unsigned long

17892

+div_deuo (unsigned long a, unsigned long b)

17893

+{

17894

+ return __builtin_divdeuo (a, b);

17895

+}

17896

Index: gcc/testsuite/gcc.target/powerpc/p8vector-int128-2.c

17897

===================================================================

17898

--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-int128-2.c (.../tags/gcc_4_8_2_release)

17899

+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-int128-2.c (.../branches/gcc-4_8-branch)

17900

@@ -0,0 +1,177 @@

17901

+/* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */

17902

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

17903

+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */

17904

+/* { dg-require-effective-target p8vector_hw } */

17905

+/* { dg-options "-mcpu=power8 -O2" } */

17906

+

17907

+#include <stddef.h>

17908

+#include <stdlib.h>

17909

+#include <altivec.h>

17910

+

17911

+#ifdef DEBUG

17912

+#include <stdio.h>

17913

+#define UNUSED

17914

+

17915

+#ifdef __LITTLE_ENDIAN__

17916

+#define HI_WORD 1

17917

+#define LO_WORD 0

17918

+#else

17919

+#define HI_WORD 0

17920

+#define LO_WORD 1

17921

+#endif

17922

+

17923

+#else

17924

+#define UNUSED __attribute__((__unused__))

17925

+#endif

17926

+

17927

+#ifndef S_TYPE

17928

+#define S_TYPE __uint128_t

17929

+#endif

17930

+

17931

+#ifndef V_TYPE

17932

+#define V_TYPE vector S_TYPE

17933

+#endif

17934

+

17935

+static int compare (S_TYPE, V_TYPE, const char *, const char *)

17936

+ __attribute__((__noinline__));

17937

+

17938

+static int

17939

+compare (S_TYPE scalar,

17940

+ V_TYPE vect,

17941

+ const char *nl UNUSED,

17942

+ const char *which UNUSED)

17943

+{

17944

+ unsigned long scalar_lo = (unsigned long) scalar;

17945

+ unsigned long scalar_hi = (unsigned long) (scalar >> 64);

17946

+ unsigned long vect_lo;

17947

+ unsigned long vect_hi;

17948

+ vector long long tmp;

17949

+ int ret;

17950

+

17951

+ __asm__ ("mfvsrd %0,%x3\n\t"

17952

+ "xxpermdi %x2,%x3,%x3,3\n\t"

17953

+ "mfvsrd %1,%x2"

17954

+ : "=r" (vect_hi),

17955

+ "=r" (vect_lo),

17956

+ "=wa" (tmp)

17957

+ : "wa" (vect));

17958

+

17959

+ ret = (scalar_lo != vect_lo) || (scalar_hi != vect_hi);

17960

+

17961

+#ifdef DEBUG

17962

+ printf ("%s%s: 0x%.16lx %.16lx %s 0x%.16lx %.16lx\n",

17963

+ nl, which,

17964

+ scalar_hi, scalar_lo,

17965

+ (ret) ? "!=" : "==",

17966

+ vect_hi, vect_lo);

17967

+

17968

+ fflush (stdout);

17969

+#endif

17970

+

17971

+ return ret;

17972

+}

17973

+

17974

+static void convert_via_mem (V_TYPE *, S_TYPE *)

17975

+ __attribute__((__noinline__));

17976

+

17977

+static void

17978

+convert_via_mem (V_TYPE *v, S_TYPE *s)

17979

+{

17980

+ *v = (V_TYPE) { *s };

17981

+ __asm__ volatile ("nop"

17982

+ : "+m" (*s), "+m" (*v)

17983

+ :

17984

+ : "memory");

17985

+

17986

+}

17987

+

17988

+

17989

+/* Check if vadduqm returns the same values as normal 128-bit add. */

17990

+

17991

+/* Values to add together. */

17992

+const static struct {

17993

+ unsigned long hi_1;

17994

+ unsigned long lo_1;

17995

+ unsigned long hi_2;

17996

+ unsigned long lo_2;

17997

+} values[] = {

17998

+ { 0x0000000000000000UL, 0xfffffffffffffffeUL,

17999

+ 0x0000000000000000UL, 0x0000000000000002UL },

18000

+ { 0x0000000000000000UL, 0x0000000000000002UL,

18001

+ 0x0000000000000000UL, 0xfffffffffffffffeUL },

18002

+ { 0xffffffffffffffffUL, 0xfffffffffffffffeUL,

18003

+ 0x0000000000000000UL, 0x0000000000000002UL },

18004

+ { 0xfffffffffffffff2UL, 0xffffffffffffffffUL,

18005

+ 0x0000000000000002UL, 0x0000000000000000UL },

18006

+ { 0x7fffffffffffffffUL, 0xfffffffffffffffeUL,

18007

+ 0x0000000000000000UL, 0x0000000000000002UL },

18008

+ { 0x7ffffffffffffff2UL, 0xffffffffffffffffUL,

18009

+ 0x0000000000000002UL, 0x0000000000000000UL },

18010

+};

18011

+

18012

+int

18013

+main (void)

18014

+{

18015

+ int reg_errors = 0;

18016

+ int mem_errors = 0;

18017

+ size_t i;

18018

+ const char *nl = "";

18019

+

18020

+ for (i = 0; i < sizeof (values) / sizeof (values[0]); i++)

18021

+ {

18022

+ S_TYPE s_reg_res, s_reg_in1, s_reg_in2, s_mem_res, s_mem_in1, s_mem_in2;

18023

+ V_TYPE v_reg_res, v_reg_in1, v_reg_in2, v_mem_res, v_mem_in1, v_mem_in2;

18024

+

18025

+ s_reg_in1 = ((((S_TYPE)values[i].hi_1 << 64)) + ((S_TYPE)values[i].lo_1));

18026

+ reg_errors += compare (s_reg_in1, (V_TYPE) { s_reg_in1 }, nl, "reg, in1");

18027

+

18028

+ s_reg_in2 = ((((S_TYPE)values[i].hi_2 << 64)) + ((S_TYPE)values[i].lo_2));

18029

+ reg_errors += compare (s_reg_in2, (V_TYPE) { s_reg_in2 }, "", "reg, in2");

18030

+

18031

+ s_reg_res = s_reg_in1 + s_reg_in2;

18032

+

18033

+ v_reg_in1 = (V_TYPE) { s_reg_in1 };

18034

+ v_reg_in2 = (V_TYPE) { s_reg_in2 };

18035

+ v_reg_res = vec_vadduqm (v_reg_in1, v_reg_in2);

18036

+ reg_errors += compare (s_reg_res, v_reg_res, "", "reg, res");

18037

+

18038

+ s_mem_in1 = s_reg_in1;

18039

+ convert_via_mem (&v_mem_in1, &s_mem_in1);

18040

+ mem_errors += compare (s_mem_in1, (V_TYPE) { s_mem_in1 }, "\n", "mem, in1");

18041

+

18042

+ s_mem_in2 = s_reg_in2;

18043

+ convert_via_mem (&v_mem_in2, &s_mem_in2);

18044

+ mem_errors += compare (s_mem_in2, (V_TYPE) { s_mem_in2 }, "", "mem, in2");

18045

+

18046

+ s_mem_res = s_mem_in1 + s_mem_in2;

18047

+ v_mem_res = vec_vadduqm (v_mem_in1, v_mem_in2);

18048

+ mem_errors += compare (s_mem_res, v_mem_res, "", "mem, res");

18049

+

18050

+ nl = "\n";

18051

+ }

18052

+

18053

+#ifdef DEBUG

18054

+ putchar ('\n');

18055

+

18056

+ if (!reg_errors)

18057

+ fputs ("no errors found on register operations\n", stdout);

18058

+ else

18059

+ printf ("%d error%s found on register operations\n",

18060

+ reg_errors,

18061

+ (reg_errors == 1) ? "s" : "");

18062

+

18063

+ if (!mem_errors)

18064

+ fputs ("no errors found on memory operations\n", stdout);

18065

+ else

18066

+ printf ("%d error%s found on memory operations\n",

18067

+ mem_errors,

18068

+ (mem_errors == 1) ? "s" : "");

18069

+

18070

+ fflush (stdout);

18071

+#endif

18072

+

18073

+ if ((reg_errors + mem_errors) != 0)

18074

+ abort ();

18075

+

18076

+ return 0;

18077

+}

18078

Index: gcc/testsuite/gcc.target/powerpc/pr58673-2.c

18079

===================================================================

18080

--- a/src/gcc/testsuite/gcc.target/powerpc/pr58673-2.c (.../tags/gcc_4_8_2_release)

18081

+++ b/src/gcc/testsuite/gcc.target/powerpc/pr58673-2.c (.../branches/gcc-4_8-branch)

18082

@@ -0,0 +1,217 @@

18083

+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */

18084

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

18085

+/* { dg-require-effective-target powerpc_p8vector_ok } */

18086

+/* { dg-options "-mcpu=power8 -O3 -m64 -funroll-loops" } */

18087

+

18088

+#include <stddef.h>

18089

+#include <stdlib.h>

18090

+#include <math.h>

18091

+#include <string.h>

18092

+

18093

+typedef long unsigned int size_t;

18094

+typedef struct _IO_FILE FILE;

18095

+typedef float real;

18096

+typedef real rvec[3];

18097

+typedef real matrix[3][3];

18098

+typedef real tensor[3][3];

18099

+enum

18100

+{

18101

+ F_BONDS, F_G96BONDS, F_MORSE, F_CUBICBONDS, F_CONNBONDS, F_HARMONIC,

18102

+ F_ANGLES, F_G96ANGLES, F_PDIHS, F_RBDIHS, F_IDIHS, F_LJ14, F_COUL14, F_LJ,

18103

+ F_BHAM, F_LJLR, F_DISPCORR, F_SR, F_LR, F_WPOL, F_POSRES, F_DISRES,

18104

+ F_DISRESVIOL, F_ORIRES, F_ORIRESDEV, F_ANGRES, F_ANGRESZ, F_SHAKE,

18105

+ F_SHAKENC, F_SETTLE, F_DUMMY2, F_DUMMY3, F_DUMMY3FD, F_DUMMY3FAD,

18106

+ F_DUMMY3OUT, F_DUMMY4FD, F_EQM, F_EPOT, F_EKIN, F_ETOT, F_TEMP, F_PRES,

18107

+ F_DVDL, F_DVDLKIN, F_NRE

18108

+};

18109

+typedef union

18110

+{

18111

+ struct

18112

+ {

18113

+ }

18114

+ bham;

18115

+ struct

18116

+ {

18117

+ real rA, krA, rB, krB;

18118

+ }

18119

+ harmonic;

18120

+}

18121

+t_iparams;

18122

+typedef struct

18123

+{

18124

+ t_iparams *iparams;

18125

+}

18126

+t_idef;

18127

+typedef struct

18128

+{

18129

+}

18130

+t_inputrec;

18131

+typedef struct

18132

+{

18133

+}

18134

+t_commrec;

18135

+typedef struct

18136

+{

18137

+}

18138

+t_forcerec;

18139

+typedef struct

18140

+{

18141

+}

18142

+t_mdatoms;

18143

+typedef struct

18144

+{

18145

+}

18146

+t_filenm;

18147

+enum

18148

+{

18149

+ eoPres, eoEpot, eoVir, eoDist, eoMu, eoForce, eoFx, eoFy, eoFz, eoPx, eoPy,

18150

+ eoPz, eoPolarizability, eoDipole, eoObsNR, eoMemory =

18151

+ eoObsNR, eoInter, eoUseVirial, eoNR

18152

+};

18153

+extern char *eoNames[eoNR];

18154

+typedef struct

18155

+{

18156

+ int bPrint;

18157

+}

18158

+t_coupl_LJ;

18159

+typedef struct

18160

+{

18161

+ int eObs;

18162

+ t_iparams xi;

18163

+}

18164

+t_coupl_iparams;

18165

+typedef struct

18166

+{

18167

+ real act_value[eoObsNR];

18168

+ real av_value[eoObsNR];

18169

+ real ref_value[eoObsNR];

18170

+ int bObsUsed[eoObsNR];

18171

+ int nLJ, nBU, nQ, nIP;

18172

+ t_coupl_LJ *tcLJ;

18173

+}

18174

+t_coupl_rec;

18175

+static void

18176

+pr_ff (t_coupl_rec * tcr, real time, t_idef * idef, t_commrec * cr, int nfile,

18177

+ t_filenm fnm[])

18178

+{

18179

+ static FILE *prop;

18180

+ static FILE **out = ((void *) 0);

18181

+ static FILE **qq = ((void *) 0);

18182

+ static FILE **ip = ((void *) 0);

18183

+ char buf[256];

18184

+ char *leg[] = {

18185

+ "C12", "C6"

18186

+ };

18187

+ char **raleg;

18188

+ int i, j, index;

18189

+ if ((prop == ((void *) 0)) && (out == ((void *) 0)) && (qq == ((void *) 0))

18190

+ && (ip == ((void *) 0)))

18191

+ {

18192

+ for (i = j = 0; (i < eoObsNR); i++)

18193

+ {

18194

+ if (tcr->bObsUsed[i])

18195

+ {

18196

+ raleg[j++] =

18197

+ (__extension__

18198

+ (__builtin_constant_p (eoNames[i])

18199

+ && ((size_t) (const void *) ((eoNames[i]) + 1) -

18200

+ (size_t) (const void *) (eoNames[i]) ==

18201

+ 1) ? (((const char *) (eoNames[i]))[0] ==

18202

+ '\0' ? (char *) calloc ((size_t) 1,

18203

+ (size_t) 1) : (

18204

+ {

18205

+ size_t

18206

+ __len

18207

+ =

18208

+ strlen

18209

+ (eoNames

18210

+ [i])

18211

+ +

18212

+ 1;

18213

+ char

18214

+ *__retval

18215

+ =

18216

+ (char

18217

+ *)

18218

+ malloc

18219

+ (__len);

18220

+ __retval;}

18221

+ )): __strdup (eoNames[i])));

18222

+ raleg[j++] =

18223

+ (__extension__

18224

+ (__builtin_constant_p (buf)

18225

+ && ((size_t) (const void *) ((buf) + 1) -

18226

+ (size_t) (const void *) (buf) ==

18227

+ 1) ? (((const char *) (buf))[0] ==

18228

+ '\0' ? (char *) calloc ((size_t) 1,

18229

+ (size_t) 1) : (

18230

+ {

18231

+ size_t

18232

+ __len

18233

+ =

18234

+ strlen

18235

+ (buf)

18236

+ +

18237

+ 1;

18238

+ char

18239

+ *__retval

18240

+ =

18241

+ (char

18242

+ *)

18243

+ malloc

18244

+ (__len);

18245

+ __retval;}

18246

+ )): __strdup (buf)));

18247

+ }

18248

+ }

18249

+ if (tcr->nLJ)

18250

+ {

18251

+ for (i = 0; (i < tcr->nLJ); i++)

18252

+ {

18253

+ if (tcr->tcLJ[i].bPrint)

18254

+ {

18255

+ xvgr_legend (out[i], (sizeof (leg) / sizeof ((leg)[0])),

18256

+ leg);

18257

+ }

18258

+ }

18259

+ }

18260

+ }

18261

+}

18262

+

18263

+void

18264

+do_coupling (FILE * log, int nfile, t_filenm fnm[], t_coupl_rec * tcr, real t,

18265

+ int step, real ener[], t_forcerec * fr, t_inputrec * ir,

18266

+ int bMaster, t_mdatoms * md, t_idef * idef, real mu_aver,

18267

+ int nmols, t_commrec * cr, matrix box, tensor virial,

18268

+ tensor pres, rvec mu_tot, rvec x[], rvec f[], int bDoIt)

18269

+{

18270

+ int i, j, ati, atj, atnr2, type, ftype;

18271

+ real deviation[eoObsNR], prdev[eoObsNR], epot0, dist, rmsf;

18272

+ real ff6, ff12, ffa, ffb, ffc, ffq, factor, dt, mu_ind;

18273

+ int bTest, bPrint;

18274

+ t_coupl_iparams *tip;

18275

+ if (bPrint)

18276

+ {

18277

+ pr_ff (tcr, t, idef, cr, nfile, fnm);

18278

+ }

18279

+ for (i = 0; (i < eoObsNR); i++)

18280

+ {

18281

+ deviation[i] =

18282

+ calc_deviation (tcr->av_value[i], tcr->act_value[i],

18283

+ tcr->ref_value[i]);

18284

+ prdev[i] = tcr->ref_value[i] - tcr->act_value[i];

18285

+ }

18286

+ if (bPrint)

18287

+ pr_dev (tcr, t, prdev, cr, nfile, fnm);

18288

+ for (i = 0; (i < atnr2); i++)

18289

+ {

18290

+ factor = dt * deviation[tip->eObs];

18291

+ switch (ftype)

18292

+ {

18293

+ case F_BONDS:

18294

+ if (fabs (tip->xi.harmonic.krA) > 1.2e-38)

18295

+ idef->iparams[type].harmonic.krA *=

18296

+ (1 + factor / tip->xi.harmonic.krA);

18297

+ }

18298

+ }

18299

+}

18300

Index: gcc/testsuite/gcc.target/powerpc/atomic-p7.c

18301

===================================================================

18302

--- a/src/gcc/testsuite/gcc.target/powerpc/atomic-p7.c (.../tags/gcc_4_8_2_release)

18303

+++ b/src/gcc/testsuite/gcc.target/powerpc/atomic-p7.c (.../branches/gcc-4_8-branch)

18304

@@ -0,0 +1,207 @@

18305

+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */

18306

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

18307

+/* { dg-require-effective-target powerpc_vsx_ok } */

18308

+/* { dg-options "-mcpu=power7 -O2" } */

18309

+/* { dg-final { scan-assembler-not "lbarx" } } */

18310

+/* { dg-final { scan-assembler-not "lharx" } } */

18311

+/* { dg-final { scan-assembler-times "lwarx" 18 } } */

18312

+/* { dg-final { scan-assembler-times "ldarx" 6 } } */

18313

+/* { dg-final { scan-assembler-not "lqarx" } } */

18314

+/* { dg-final { scan-assembler-not "stbcx" } } */

18315

+/* { dg-final { scan-assembler-not "sthcx" } } */

18316

+/* { dg-final { scan-assembler-times "stwcx" 18 } } */

18317

+/* { dg-final { scan-assembler-times "stdcx" 6 } } */

18318

+/* { dg-final { scan-assembler-not "stqcx" } } */

18319

+/* { dg-final { scan-assembler-times "bl __atomic" 6 } } */

18320

+/* { dg-final { scan-assembler-times "isync" 12 } } */

18321

+/* { dg-final { scan-assembler-times "lwsync" 8 } } */

18322

+/* { dg-final { scan-assembler-not "mtvsrd" } } */

18323

+/* { dg-final { scan-assembler-not "mtvsrwa" } } */

18324

+/* { dg-final { scan-assembler-not "mtvsrwz" } } */

18325

+/* { dg-final { scan-assembler-not "mfvsrd" } } */

18326

+/* { dg-final { scan-assembler-not "mfvsrwz" } } */

18327

+

18328

+/* Test for the byte atomic operations on power8 using lbarx/stbcx. */

18329

+char

18330

+char_fetch_add_relaxed (char *ptr, int value)

18331

+{

18332

+ return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED);

18333

+}

18334

+

18335

+char

18336

+char_fetch_sub_consume (char *ptr, int value)

18337

+{

18338

+ return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME);

18339

+}

18340

+

18341

+char

18342

+char_fetch_and_acquire (char *ptr, int value)

18343

+{

18344

+ return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE);

18345

+}

18346

+

18347

+char

18348

+char_fetch_ior_release (char *ptr, int value)

18349

+{

18350

+ return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE);

18351

+}

18352

+

18353

+char

18354

+char_fetch_xor_acq_rel (char *ptr, int value)

18355

+{

18356

+ return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL);

18357

+}

18358

+

18359

+char

18360

+char_fetch_nand_seq_cst (char *ptr, int value)

18361

+{

18362

+ return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST);

18363

+}

18364

+

18365

+/* Test for the half word atomic operations on power8 using lharx/sthcx. */

18366

+short

18367

+short_fetch_add_relaxed (short *ptr, int value)

18368

+{

18369

+ return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED);

18370

+}

18371

+

18372

+short

18373

+short_fetch_sub_consume (short *ptr, int value)

18374

+{

18375

+ return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME);

18376

+}

18377

+

18378

+short

18379

+short_fetch_and_acquire (short *ptr, int value)

18380

+{

18381

+ return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE);

18382

+}

18383

+

18384

+short

18385

+short_fetch_ior_release (short *ptr, int value)

18386

+{

18387

+ return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE);

18388

+}

18389

+

18390

+short

18391

+short_fetch_xor_acq_rel (short *ptr, int value)

18392

+{

18393

+ return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL);

18394

+}

18395

+

18396

+short

18397

+short_fetch_nand_seq_cst (short *ptr, int value)

18398

+{

18399

+ return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST);

18400

+}

18401

+

18402

+/* Test for the word atomic operations on power8 using lwarx/stwcx. */

18403

+int

18404

+int_fetch_add_relaxed (int *ptr, int value)

18405

+{

18406

+ return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED);

18407

+}

18408

+

18409

+int

18410

+int_fetch_sub_consume (int *ptr, int value)

18411

+{

18412

+ return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME);

18413

+}

18414

+

18415

+int

18416

+int_fetch_and_acquire (int *ptr, int value)

18417

+{

18418

+ return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE);

18419

+}

18420

+

18421

+int

18422

+int_fetch_ior_release (int *ptr, int value)

18423

+{

18424

+ return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE);

18425

+}

18426

+

18427

+int

18428

+int_fetch_xor_acq_rel (int *ptr, int value)

18429

+{

18430

+ return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL);

18431

+}

18432

+

18433

+int

18434

+int_fetch_nand_seq_cst (int *ptr, int value)

18435

+{

18436

+ return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST);

18437

+}

18438

+

18439

+/* Test for the double word atomic operations on power8 using ldarx/stdcx. */

18440

+long

18441

+long_fetch_add_relaxed (long *ptr, long value)

18442

+{

18443

+ return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED);

18444

+}

18445

+

18446

+long

18447

+long_fetch_sub_consume (long *ptr, long value)

18448

+{

18449

+ return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME);

18450

+}

18451

+

18452

+long

18453

+long_fetch_and_acquire (long *ptr, long value)

18454

+{

18455

+ return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE);

18456

+}

18457

+

18458

+long

18459

+long_fetch_ior_release (long *ptr, long value)

18460

+{

18461

+ return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE);

18462

+}

18463

+

18464

+long

18465

+long_fetch_xor_acq_rel (long *ptr, long value)

18466

+{

18467

+ return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL);

18468

+}

18469

+

18470

+long

18471

+long_fetch_nand_seq_cst (long *ptr, long value)

18472

+{

18473

+ return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST);

18474

+}

18475

+

18476

+/* Test for the quad word atomic operations on power8 using ldarx/stdcx. */

18477

+__int128_t

18478

+quad_fetch_add_relaxed (__int128_t *ptr, __int128_t value)

18479

+{

18480

+ return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED);

18481

+}

18482

+

18483

+__int128_t

18484

+quad_fetch_sub_consume (__int128_t *ptr, __int128_t value)

18485

+{

18486

+ return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME);

18487

+}

18488

+

18489

+__int128_t

18490

+quad_fetch_and_acquire (__int128_t *ptr, __int128_t value)

18491

+{

18492

+ return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE);

18493

+}

18494

+

18495

+__int128_t

18496

+quad_fetch_ior_release (__int128_t *ptr, __int128_t value)

18497

+{

18498

+ return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE);

18499

+}

18500

+

18501

+__int128_t

18502

+quad_fetch_xor_acq_rel (__int128_t *ptr, __int128_t value)

18503

+{

18504

+ return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL);

18505

+}

18506

+

18507

+__int128_t

18508

+quad_fetch_nand_seq_cst (__int128_t *ptr, __int128_t value)

18509

+{

18510

+ return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST);

18511

+}

18512

Index: gcc/testsuite/gcc.target/powerpc/recip-3.c

18513

===================================================================

18514

--- a/src/gcc/testsuite/gcc.target/powerpc/recip-3.c (.../tags/gcc_4_8_2_release)

18515

+++ b/src/gcc/testsuite/gcc.target/powerpc/recip-3.c (.../branches/gcc-4_8-branch)

18516

@@ -1,14 +1,14 @@

18517

/* { dg-do compile { target { { powerpc*-*-* } && { ! powerpc*-apple-darwin* } } } } */

18518

/* { dg-require-effective-target powerpc_fprs } */

18519

/* { dg-options "-O2 -mrecip -ffast-math -mcpu=power7" } */

18520

-/* { dg-final { scan-assembler-times "xsrsqrtedp" 1 } } */

18521

+/* { dg-final { scan-assembler-times "xsrsqrtedp\|frsqrte\ " 1 } } */

18522

/* { dg-final { scan-assembler-times "xsmsub.dp\|fmsub\ " 1 } } */

18523

-/* { dg-final { scan-assembler-times "xsmuldp" 4 } } */

18524

+/* { dg-final { scan-assembler-times "xsmuldp\|fmul\ " 4 } } */

18525

/* { dg-final { scan-assembler-times "xsnmsub.dp\|fnmsub\ " 2 } } */

18526

-/* { dg-final { scan-assembler-times "frsqrtes" 1 } } */

18527

-/* { dg-final { scan-assembler-times "fmsubs" 1 } } */

18528

-/* { dg-final { scan-assembler-times "fmuls" 4 } } */

18529

-/* { dg-final { scan-assembler-times "fnmsubs" 2 } } */

18530

+/* { dg-final { scan-assembler-times "xsrsqrtesp\|frsqrtes" 1 } } */

18531

+/* { dg-final { scan-assembler-times "xsmsub.sp\|fmsubs" 1 } } */

18532

+/* { dg-final { scan-assembler-times "xsmulsp\|fmuls" 2 } } */

18533

+/* { dg-final { scan-assembler-times "xsnmsub.sp\|fnmsubs" 1 } } */

18534

18535

double

18536

rsqrt_d (double a)

18537

Index: gcc/testsuite/gcc.target/powerpc/timode_off.c

18538

===================================================================

18539

--- a/src/gcc/testsuite/gcc.target/powerpc/timode_off.c (.../tags/gcc_4_8_2_release)

18540

+++ b/src/gcc/testsuite/gcc.target/powerpc/timode_off.c (.../branches/gcc-4_8-branch)

18541

@@ -1,5 +1,5 @@

18542

/* { dg-do assemble { target { lp64 } } } */

18543

-/* { dg-options "-O2 -fno-align-functions -mtraceback=no -save-temps" } */

18544

+/* { dg-options "-O2 -fno-align-functions -mtraceback=no -save-temps -mcpu=power5" } */

18545

18546

typedef int TImode __attribute__ ((mode (TI)));

18547

18548

@@ -46,6 +46,12 @@

18549

TImode r20 (void *x) { return *(TImode *) (x + 32748); }

18550

18551

/* test should really be == 616, see pr54110 */

18552

+/* When TImode is allowed in VSX registers, the allowable address modes for

18553

+ TImode is just a single indirect address in order for the value to be loaded

18554

+ and store in either GPR or VSX registers. This affects the generated code,

18555

+ and it would cause this test to fail, when such an option is used. Fall

18556

+ back to power5 to test the code. */

18557

+

18558

/* { dg-final { object-size text <= 700 } } */

18559

/* { dg-final { scan-assembler-not "(st|l)fd" } } */

18560

/* { dg-final { cleanup-saved-temps "timode_off" } } */

18561

Index: gcc/testsuite/gcc.target/powerpc/no-r11-2.c

18562

===================================================================

18563

--- a/src/gcc/testsuite/gcc.target/powerpc/no-r11-2.c (.../tags/gcc_4_8_2_release)

18564

+++ b/src/gcc/testsuite/gcc.target/powerpc/no-r11-2.c (.../branches/gcc-4_8-branch)

18565

@@ -1,5 +1,6 @@

18566

/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */

18567

/* { dg-skip-if "" { *-*-darwin* } { "*" } { "" } } */

18568

+/* { dg-skip-if "" { powerpc_elfv2 } { "*" } { "" } } */

18569

/* { dg-options "-O2 -mpointers-to-nested-functions" } */

18570

18571

int

18572

Index: gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c

18573

===================================================================

18574

--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c (.../tags/gcc_4_8_2_release)

18575

+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c (.../branches/gcc-4_8-branch)

18576

@@ -0,0 +1,42 @@

18577

+/* { dg-do compile { target { powerpc*-*-* } } } */

18578

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

18579

+/* { dg-require-effective-target powerpc_p8vector_ok } */

18580

+/* { dg-options "-mcpu=power8 -O2 -mupper-regs-df -mupper-regs-sf" } */

18581

+

18582

+float load_sf (float *p)

18583

+{

18584

+ float f = *p;

18585

+ __asm__ ("# reg %x0" : "+v" (f));

18586

+ return f;

18587

+}

18588

+

18589

+double load_df (double *p)

18590

+{

18591

+ double d = *p;

18592

+ __asm__ ("# reg %x0" : "+v" (d));

18593

+ return d;

18594

+}

18595

+

18596

+double load_dfsf (float *p)

18597

+{

18598

+ double d = (double) *p;

18599

+ __asm__ ("# reg %x0" : "+v" (d));

18600

+ return d;

18601

+}

18602

+

18603

+void store_sf (float *p, float f)

18604

+{

18605

+ __asm__ ("# reg %x0" : "+v" (f));

18606

+ *p = f;

18607

+}

18608

+

18609

+void store_df (double *p, double d)

18610

+{

18611

+ __asm__ ("# reg %x0" : "+v" (d));

18612

+ *p = d;

18613

+}

18614

+

18615

+/* { dg-final { scan-assembler "lxsspx" } } */

18616

+/* { dg-final { scan-assembler "lxsdx" } } */

18617

+/* { dg-final { scan-assembler "stxsspx" } } */

18618

+/* { dg-final { scan-assembler "stxsdx" } } */

18619

Index: gcc/testsuite/gcc.target/powerpc/pack01.c

18620

===================================================================

18621

--- a/src/gcc/testsuite/gcc.target/powerpc/pack01.c (.../tags/gcc_4_8_2_release)

18622

+++ b/src/gcc/testsuite/gcc.target/powerpc/pack01.c (.../branches/gcc-4_8-branch)

18623

@@ -0,0 +1,91 @@

18624

+/* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */

18625

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

18626

+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */

18627

+/* { dg-require-effective-target p8vector_hw } */

18628

+/* { dg-options "-mcpu=power8 -O2" } */

18629

+

18630

+#include <stddef.h>

18631

+#include <stdlib.h>

18632

+#include <altivec.h>

18633

+

18634

+#ifdef DEBUG

18635

+#include <stdio.h>

18636

+#endif

18637

+

18638

+typedef __int128_t __attribute__((__vector_size__(16))) vector_128_t;

18639

+typedef __int128_t scalar_128_t;

18640

+typedef unsigned long long scalar_64_t;

18641

+

18642

+volatile scalar_64_t one = 1;

18643

+volatile scalar_64_t two = 2;

18644

+

18645

+int

18646

+main (void)

18647

+{

18648

+ scalar_128_t a = (((scalar_128_t)one) << 64) | ((scalar_128_t)two);

18649

+ vector_128_t v1 = (vector_128_t) { a };

18650

+ vector_128_t v2 = __builtin_pack_vector_int128 (one, two);

18651

+ scalar_64_t x0 = __builtin_unpack_vector_int128 (v1, 0);

18652

+ scalar_64_t x1 = __builtin_unpack_vector_int128 (v1, 1);

18653

+ vector_128_t v3 = __builtin_pack_vector_int128 (x0, x1);

18654

+

18655

+ size_t i;

18656

+ union {

18657

+ scalar_128_t i128;

18658

+ vector_128_t v128;

18659

+ scalar_64_t u64;

18660

+ unsigned char uc[sizeof (scalar_128_t)];

18661

+ char c[sizeof (scalar_128_t)];

18662

+ } u, u2;

18663

+

18664

+#ifdef DEBUG

18665

+ {

18666

+ printf ("a = 0x");

18667

+ u.i128 = a;

18668

+ for (i = 0; i < sizeof (scalar_128_t); i++)

18669

+ printf ("%.2x", u.uc[i]);

18670

+

18671

+ printf ("\nv1 = 0x");

18672

+ u.v128 = v1;

18673

+ for (i = 0; i < sizeof (scalar_128_t); i++)

18674

+ printf ("%.2x", u.uc[i]);

18675

+

18676

+ printf ("\nv2 = 0x");

18677

+ u.v128 = v2;

18678

+ for (i = 0; i < sizeof (scalar_128_t); i++)

18679

+ printf ("%.2x", u.uc[i]);

18680

+

18681

+ printf ("\nv3 = 0x");

18682

+ u.v128 = v3;

18683

+ for (i = 0; i < sizeof (scalar_128_t); i++)

18684

+ printf ("%.2x", u.uc[i]);

18685

+

18686

+ printf ("\nx0 = 0x");

18687

+ u.u64 = x0;

18688

+ for (i = 0; i < sizeof (scalar_64_t); i++)

18689

+ printf ("%.2x", u.uc[i]);

18690

+

18691

+ printf ("\nx1 = 0x");

18692

+ u.u64 = x1;

18693

+ for (i = 0; i < sizeof (scalar_64_t); i++)

18694

+ printf ("%.2x", u.uc[i]);

18695

+

18696

+ printf ("\n");

18697

+ }

18698

+#endif

18699

+

18700

+ u2.i128 = a;

18701

+ u.v128 = v1;

18702

+ if (memcmp (u.c, u2.c, sizeof (scalar_128_t)) != 0)

18703

+ abort ();

18704

+

18705

+ u.v128 = v2;

18706

+ if (memcmp (u.c, u2.c, sizeof (scalar_128_t)) != 0)

18707

+ abort ();

18708

+

18709

+ u.v128 = v3;

18710

+ if (memcmp (u.c, u2.c, sizeof (scalar_128_t)) != 0)

18711

+ abort ();

18712

+

18713

+ return 0;

18714

+}

18715

Index: gcc/testsuite/gcc.target/powerpc/bool3-p8.c

18716

===================================================================

18717

--- a/src/gcc/testsuite/gcc.target/powerpc/bool3-p8.c (.../tags/gcc_4_8_2_release)

18718

+++ b/src/gcc/testsuite/gcc.target/powerpc/bool3-p8.c (.../branches/gcc-4_8-branch)

18719

@@ -0,0 +1,36 @@

18720

+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */

18721

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

18722

+/* { dg-require-effective-target powerpc_p8vector_ok } */

18723

+/* { dg-options "-O2 -mcpu=power8" } */

18724

+/* { dg-final { scan-assembler "\[ \t\]and " } } */

18725

+/* { dg-final { scan-assembler "\[ \t\]or " } } */

18726

+/* { dg-final { scan-assembler "\[ \t\]xor " } } */

18727

+/* { dg-final { scan-assembler "\[ \t\]nor " } } */

18728

+/* { dg-final { scan-assembler "\[ \t\]andc " } } */

18729

+/* { dg-final { scan-assembler "\[ \t\]eqv " } } */

18730

+/* { dg-final { scan-assembler "\[ \t\]orc " } } */

18731

+/* { dg-final { scan-assembler "\[ \t\]nand " } } */

18732

+/* { dg-final { scan-assembler-not "\[ \t\]vand " } } */

18733

+/* { dg-final { scan-assembler-not "\[ \t\]vandc " } } */

18734

+/* { dg-final { scan-assembler-not "\[ \t\]vor " } } */

18735

+/* { dg-final { scan-assembler-not "\[ \t\]vxor " } } */

18736

+/* { dg-final { scan-assembler-not "\[ \t\]vnor " } } */

18737

+/* { dg-final { scan-assembler-not "\[ \t\]xxland " } } */

18738

+/* { dg-final { scan-assembler-not "\[ \t\]xxlor " } } */

18739

+/* { dg-final { scan-assembler-not "\[ \t\]xxlxor " } } */

18740

+/* { dg-final { scan-assembler-not "\[ \t\]xxlnor " } } */

18741

+/* { dg-final { scan-assembler-not "\[ \t\]xxlandc " } } */

18742

+/* { dg-final { scan-assembler-not "\[ \t\]xxleqv " } } */

18743

+/* { dg-final { scan-assembler-not "\[ \t\]xxlorc " } } */

18744

+/* { dg-final { scan-assembler-not "\[ \t\]xxlnand " } } */

18745

+

18746

+#ifndef TYPE

18747

+#ifdef _ARCH_PPC64

18748

+#define TYPE __int128_t

18749

+#else

18750

+typedef int v4si __attribute__ ((vector_size (16)));

18751

+#define TYPE v4si

18752

+#endif

18753

+#endif

18754

+

18755

+#include "bool3.h"

18756

Index: gcc/testsuite/gcc.target/powerpc/htm-xl-intrin-1.c

18757

===================================================================

18758

--- a/src/gcc/testsuite/gcc.target/powerpc/htm-xl-intrin-1.c (.../tags/gcc_4_8_2_release)

18759

+++ b/src/gcc/testsuite/gcc.target/powerpc/htm-xl-intrin-1.c (.../branches/gcc-4_8-branch)

18760

@@ -0,0 +1,32 @@

18761

+/* This checks the availability of the XL compiler intrinsics for

18762

+ transactional execution with the expected prototypes. */

18763

+

18764

+/* { dg-do compile { target { powerpc*-*-* } } } */

18765

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

18766

+/* { dg-require-effective-target powerpc_htm_ok } */

18767

+/* { dg-options "-O2 -mhtm" } */

18768

+

18769

+#include <htmxlintrin.h>

18770

+

18771

+void

18772

+foo (void *TM_buff, long *result, unsigned char *code)

18773

+{

18774

+ *result++ = __TM_simple_begin ();

18775

+ *result++ = __TM_begin (TM_buff);

18776

+ *result++ = __TM_end ();

18777

+ __TM_abort ();

18778

+ __TM_named_abort (*code);

18779

+ __TM_resume ();

18780

+ __TM_suspend ();

18781

+ *result++ = __TM_is_user_abort (TM_buff);

18782

+ *result++ = __TM_is_named_user_abort (TM_buff, code);

18783

+ *result++ = __TM_is_illegal (TM_buff);

18784

+ *result++ = __TM_is_footprint_exceeded (TM_buff);

18785

+ *result++ = __TM_nesting_depth (TM_buff);

18786

+ *result++ = __TM_is_nested_too_deep (TM_buff);

18787

+ *result++ = __TM_is_conflict (TM_buff);

18788

+ *result++ = __TM_is_failure_persistent (TM_buff);

18789

+ *result++ = __TM_failure_address (TM_buff);

18790

+ *result++ = __TM_failure_code (TM_buff);

18791

+}

18792

+

18793

Index: gcc/testsuite/gcc.target/powerpc/rs6000-ldouble-3.c

18794

===================================================================

18795

--- a/src/gcc/testsuite/gcc.target/powerpc/rs6000-ldouble-3.c (.../tags/gcc_4_8_2_release)

18796

+++ b/src/gcc/testsuite/gcc.target/powerpc/rs6000-ldouble-3.c (.../branches/gcc-4_8-branch)

18797

@@ -0,0 +1,21 @@

18798

+/* Test accuracy of long double division (glibc bug 15396). */

18799

+/* { dg-do run { target powerpc*-*-linux* powerpc*-*-darwin* powerpc*-*-aix* rs6000-*-* } } */

18800

+/* { dg-options "-mlong-double-128" } */

18801

+

18802

+extern void exit (int);

18803

+extern void abort (void);

18804

+

18805

+volatile long double a = 0x1p-1024L;

18806

+volatile long double b = 0x3p-53L;

18807

+volatile long double r;

18808

+volatile long double expected = 0x1.55555555555555555555555555p-973L;

18809

+

18810

+int

18811

+main (void)

18812

+{

18813

+ r = a / b;

18814

+ /* Allow error up to 2ulp. */

18815

+ if (__builtin_fabsl (r - expected) > 0x1p-1073L)

18816

+ abort ();

18817

+ exit (0);

18818

+}

18819

Index: gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c

18820

===================================================================

18821

--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c (.../tags/gcc_4_8_2_release)

18822

+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c (.../branches/gcc-4_8-branch)

18823

@@ -0,0 +1,249 @@

18824

+/* { dg-do compile { target { powerpc*-*-* } } } */

18825

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

18826

+/* { dg-require-effective-target powerpc_p8vector_ok } */

18827

+/* { dg-options "-mcpu=power8 -O3 -ftree-vectorize -fvect-cost-model" } */

18828

+

18829

+#include <altivec.h>

18830

+

18831

+typedef vector long long vll_sign;

18832

+typedef vector unsigned long long vll_uns;

18833

+typedef vector bool long long vll_bool;

18834

+

18835

+typedef vector int vi_sign;

18836

+typedef vector unsigned int vi_uns;

18837

+typedef vector bool int vi_bool;

18838

+

18839

+typedef vector short vs_sign;

18840

+typedef vector unsigned short vs_uns;

18841

+typedef vector bool short vs_bool;

18842

+

18843

+typedef vector signed char vc_sign;

18844

+typedef vector unsigned char vc_uns;

18845

+typedef vector bool char vc_bool;

18846

+

18847

+vll_sign vll_clz_1 (vll_sign a)

18848

+{

18849

+ return __builtin_altivec_vclzd (a);

18850

+}

18851

+

18852

+vll_sign vll_clz_2 (vll_sign a)

18853

+{

18854

+ return vec_vclz (a);

18855

+}

18856

+

18857

+vll_sign vll_clz_3 (vll_sign a)

18858

+{

18859

+ return vec_vclzd (a);

18860

+}

18861

+

18862

+vll_uns vll_clz_4 (vll_uns a)

18863

+{

18864

+ return vec_vclz (a);

18865

+}

18866

+

18867

+vll_uns vll_clz_5 (vll_uns a)

18868

+{

18869

+ return vec_vclzd (a);

18870

+}

18871

+

18872

+vi_sign vi_clz_1 (vi_sign a)

18873

+{

18874

+ return __builtin_altivec_vclzw (a);

18875

+}

18876

+

18877

+vi_sign vi_clz_2 (vi_sign a)

18878

+{

18879

+ return vec_vclz (a);

18880

+}

18881

+

18882

+vi_sign vi_clz_3 (vi_sign a)

18883

+{

18884

+ return vec_vclzw (a);

18885

+}

18886

+

18887

+vi_uns vi_clz_4 (vi_uns a)

18888

+{

18889

+ return vec_vclz (a);

18890

+}

18891

+

18892

+vi_uns vi_clz_5 (vi_uns a)

18893

+{

18894

+ return vec_vclzw (a);

18895

+}

18896

+

18897

+vs_sign vs_clz_1 (vs_sign a)

18898

+{

18899

+ return __builtin_altivec_vclzh (a);

18900

+}

18901

+

18902

+vs_sign vs_clz_2 (vs_sign a)

18903

+{

18904

+ return vec_vclz (a);

18905

+}

18906

+

18907

+vs_sign vs_clz_3 (vs_sign a)

18908

+{

18909

+ return vec_vclzh (a);

18910

+}

18911

+

18912

+vs_uns vs_clz_4 (vs_uns a)

18913

+{

18914

+ return vec_vclz (a);

18915

+}

18916

+

18917

+vs_uns vs_clz_5 (vs_uns a)

18918

+{

18919

+ return vec_vclzh (a);

18920

+}

18921

+

18922

+vc_sign vc_clz_1 (vc_sign a)

18923

+{

18924

+ return __builtin_altivec_vclzb (a);

18925

+}

18926

+

18927

+vc_sign vc_clz_2 (vc_sign a)

18928

+{

18929

+ return vec_vclz (a);

18930

+}

18931

+

18932

+vc_sign vc_clz_3 (vc_sign a)

18933

+{

18934

+ return vec_vclzb (a);

18935

+}

18936

+

18937

+vc_uns vc_clz_4 (vc_uns a)

18938

+{

18939

+ return vec_vclz (a);

18940

+}

18941

+

18942

+vc_uns vc_clz_5 (vc_uns a)

18943

+{

18944

+ return vec_vclzb (a);

18945

+}

18946

+

18947

+vll_sign vll_popcnt_1 (vll_sign a)

18948

+{

18949

+ return __builtin_altivec_vpopcntd (a);

18950

+}

18951

+

18952

+vll_sign vll_popcnt_2 (vll_sign a)

18953

+{

18954

+ return vec_vpopcnt (a);

18955

+}

18956

+

18957

+vll_sign vll_popcnt_3 (vll_sign a)

18958

+{

18959

+ return vec_vpopcntd (a);

18960

+}

18961

+

18962

+vll_uns vll_popcnt_4 (vll_uns a)

18963

+{

18964

+ return vec_vpopcnt (a);

18965

+}

18966

+

18967

+vll_uns vll_popcnt_5 (vll_uns a)

18968

+{

18969

+ return vec_vpopcntd (a);

18970

+}

18971

+

18972

+vi_sign vi_popcnt_1 (vi_sign a)

18973

+{

18974

+ return __builtin_altivec_vpopcntw (a);

18975

+}

18976

+

18977

+vi_sign vi_popcnt_2 (vi_sign a)

18978

+{

18979

+ return vec_vpopcnt (a);

18980

+}

18981

+

18982

+vi_sign vi_popcnt_3 (vi_sign a)

18983

+{

18984

+ return vec_vpopcntw (a);

18985

+}

18986

+

18987

+vi_uns vi_popcnt_4 (vi_uns a)

18988

+{

18989

+ return vec_vpopcnt (a);

18990

+}

18991

+

18992

+vi_uns vi_popcnt_5 (vi_uns a)

18993

+{

18994

+ return vec_vpopcntw (a);

18995

+}

18996

+

18997

+vs_sign vs_popcnt_1 (vs_sign a)

18998

+{

18999

+ return __builtin_altivec_vpopcnth (a);

19000

+}

19001

+

19002

+vs_sign vs_popcnt_2 (vs_sign a)

19003

+{

19004

+ return vec_vpopcnt (a);

19005

+}

19006

+

19007

+vs_sign vs_popcnt_3 (vs_sign a)

19008

+{

19009

+ return vec_vpopcnth (a);

19010

+}

19011

+

19012

+vs_uns vs_popcnt_4 (vs_uns a)

19013

+{

19014

+ return vec_vpopcnt (a);

19015

+}

19016

+

19017

+vs_uns vs_popcnt_5 (vs_uns a)

19018

+{

19019

+ return vec_vpopcnth (a);

19020

+}

19021

+

19022

+vc_sign vc_popcnt_1 (vc_sign a)

19023

+{

19024

+ return __builtin_altivec_vpopcntb (a);

19025

+}

19026

+

19027

+vc_sign vc_popcnt_2 (vc_sign a)

19028

+{

19029

+ return vec_vpopcnt (a);

19030

+}

19031

+

19032

+vc_sign vc_popcnt_3 (vc_sign a)

19033

+{

19034

+ return vec_vpopcntb (a);

19035

+}

19036

+

19037

+vc_uns vc_popcnt_4 (vc_uns a)

19038

+{

19039

+ return vec_vpopcnt (a);

19040

+}

19041

+

19042

+vc_uns vc_popcnt_5 (vc_uns a)

19043

+{

19044

+ return vec_vpopcntb (a);

19045

+}

19046

+

19047

+vc_uns vc_gbb_1 (vc_uns a)

19048

+{

19049

+ return __builtin_altivec_vgbbd (a);

19050

+}

19051

+

19052

+vc_sign vc_gbb_2 (vc_sign a)

19053

+{

19054

+ return vec_vgbbd (a);

19055

+}

19056

+

19057

+vc_uns vc_gbb_3 (vc_uns a)

19058

+{

19059

+ return vec_vgbbd (a);

19060

+}

19061

+

19062

+/* { dg-final { scan-assembler-times "vclzd" 5 } } */

19063

+/* { dg-final { scan-assembler-times "vclzw" 5 } } */

19064

+/* { dg-final { scan-assembler-times "vclzh" 5 } } */

19065

+/* { dg-final { scan-assembler-times "vclzb" 5 } } */

19066

+

19067

+/* { dg-final { scan-assembler-times "vpopcntd" 5 } } */

19068

+/* { dg-final { scan-assembler-times "vpopcntw" 5 } } */

19069

+/* { dg-final { scan-assembler-times "vpopcnth" 5 } } */

19070

+/* { dg-final { scan-assembler-times "vpopcntb" 5 } } */

19071

+

19072

+/* { dg-final { scan-assembler-times "vgbbd" 3 } } */

19073

Index: gcc/testsuite/gcc.target/powerpc/bool3-av.c

19074

===================================================================

19075

--- a/src/gcc/testsuite/gcc.target/powerpc/bool3-av.c (.../tags/gcc_4_8_2_release)

19076

+++ b/src/gcc/testsuite/gcc.target/powerpc/bool3-av.c (.../branches/gcc-4_8-branch)

19077

@@ -0,0 +1,37 @@

19078

+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */

19079

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

19080

+/* { dg-require-effective-target powerpc_altivec_ok } */

19081

+/* { dg-options "-O2 -mcpu=power6 -mabi=altivec -maltivec -mno-vsx" } */

19082

+/* { dg-final { scan-assembler "\[ \t\]and " } } */

19083

+/* { dg-final { scan-assembler "\[ \t\]or " } } */

19084

+/* { dg-final { scan-assembler "\[ \t\]xor " } } */

19085

+/* { dg-final { scan-assembler "\[ \t\]nor " } } */

19086

+/* { dg-final { scan-assembler "\[ \t\]andc " } } */

19087

+/* { dg-final { scan-assembler-not "\[ \t\]vand " } } */

19088

+/* { dg-final { scan-assembler-not "\[ \t\]vandc " } } */

19089

+/* { dg-final { scan-assembler-not "\[ \t\]vor " } } */

19090

+/* { dg-final { scan-assembler-not "\[ \t\]vxor " } } */

19091

+/* { dg-final { scan-assembler-not "\[ \t\]vnor " } } */

19092

+/* { dg-final { scan-assembler-not "\[ \t\]xxland " } } */

19093

+/* { dg-final { scan-assembler-not "\[ \t\]xxlor " } } */

19094

+/* { dg-final { scan-assembler-not "\[ \t\]xxlxor " } } */

19095

+/* { dg-final { scan-assembler-not "\[ \t\]xxlnor " } } */

19096

+/* { dg-final { scan-assembler-not "\[ \t\]xxlandc " } } */

19097

+/* { dg-final { scan-assembler-not "\[ \t\]xxleqv " } } */

19098

+/* { dg-final { scan-assembler-not "\[ \t\]xxlorc " } } */

19099

+/* { dg-final { scan-assembler-not "\[ \t\]xxlnand " } } */

19100

+

19101

+/* On altivec, for 128-bit types, ORC/ANDC/EQV might not show up, since the

19102

+ vector unit doesn't support these, so the appropriate combine patterns may

19103

+ not be generated. */

19104

+

19105

+#ifndef TYPE

19106

+#ifdef _ARCH_PPC64

19107

+#define TYPE __int128_t

19108

+#else

19109

+typedef int v4si __attribute__ ((vector_size (16)));

19110

+#define TYPE v4si

19111

+#endif

19112

+#endif

19113

+

19114

+#include "bool3.h"

19115

Index: gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-4.c

19116

===================================================================

19117

--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-4.c (.../tags/gcc_4_8_2_release)

19118

+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-4.c (.../branches/gcc-4_8-branch)

19119

@@ -0,0 +1,69 @@

19120

+/* { dg-do compile { target { powerpc*-*-* } } } */

19121

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

19122

+/* { dg-require-effective-target powerpc_p8vector_ok } */

19123

+/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model -fno-unroll-loops -fno-unroll-all-loops" } */

19124

+

19125

+#ifndef SIZE

19126

+#define SIZE 1024

19127

+#endif

19128

+

19129

+#ifndef ALIGN

19130

+#define ALIGN 32

19131

+#endif

19132

+

19133

+#define ALIGN_ATTR __attribute__((__aligned__(ALIGN)))

19134

+

19135

+#define DO_BUILTIN(PREFIX, TYPE, CLZ, POPCNT) \

19136

+TYPE PREFIX ## _a[SIZE] ALIGN_ATTR; \

19137

+TYPE PREFIX ## _b[SIZE] ALIGN_ATTR; \

19138

+ \

19139

+void \

19140

+PREFIX ## _clz (void) \

19141

+{ \

19142

+ unsigned long i; \

19143

+ \

19144

+ for (i = 0; i < SIZE; i++) \

19145

+ PREFIX ## _a[i] = CLZ (PREFIX ## _b[i]); \

19146

+} \

19147

+ \

19148

+void \

19149

+PREFIX ## _popcnt (void) \

19150

+{ \

19151

+ unsigned long i; \

19152

+ \

19153

+ for (i = 0; i < SIZE; i++) \

19154

+ PREFIX ## _a[i] = POPCNT (PREFIX ## _b[i]); \

19155

+}

19156

+

19157

+#if !defined(DO_LONG_LONG) && !defined(DO_LONG) && !defined(DO_INT) && !defined(DO_SHORT) && !defined(DO_CHAR)

19158

+#define DO_INT 1

19159

+#endif

19160

+

19161

+#if DO_LONG_LONG

19162

+/* At the moment, only int is auto vectorized. */

19163

+DO_BUILTIN (sll, long long, __builtin_clzll, __builtin_popcountll)

19164

+DO_BUILTIN (ull, unsigned long long, __builtin_clzll, __builtin_popcountll)

19165

+#endif

19166

+

19167

+#if defined(_ARCH_PPC64) && DO_LONG

19168

+DO_BUILTIN (sl, long, __builtin_clzl, __builtin_popcountl)

19169

+DO_BUILTIN (ul, unsigned long, __builtin_clzl, __builtin_popcountl)

19170

+#endif

19171

+

19172

+#if DO_INT

19173

+DO_BUILTIN (si, int, __builtin_clz, __builtin_popcount)

19174

+DO_BUILTIN (ui, unsigned int, __builtin_clz, __builtin_popcount)

19175

+#endif

19176

+

19177

+#if DO_SHORT

19178

+DO_BUILTIN (ss, short, __builtin_clz, __builtin_popcount)

19179

+DO_BUILTIN (us, unsigned short, __builtin_clz, __builtin_popcount)

19180

+#endif

19181

+

19182

+#if DO_CHAR

19183

+DO_BUILTIN (sc, signed char, __builtin_clz, __builtin_popcount)

19184

+DO_BUILTIN (uc, unsigned char, __builtin_clz, __builtin_popcount)

19185

+#endif

19186

+

19187

+/* { dg-final { scan-assembler-times "vclzw" 2 } } */

19188

+/* { dg-final { scan-assembler-times "vpopcntw" 2 } } */

19189

Index: gcc/testsuite/gcc.target/powerpc/bcd-3.c

19190

===================================================================

19191

--- a/src/gcc/testsuite/gcc.target/powerpc/bcd-3.c (.../tags/gcc_4_8_2_release)

19192

+++ b/src/gcc/testsuite/gcc.target/powerpc/bcd-3.c (.../branches/gcc-4_8-branch)

19193

@@ -0,0 +1,103 @@

19194

+/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */

19195

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

19196

+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */

19197

+/* { dg-require-effective-target powerpc_p8vector_ok } */

19198

+/* { dg-options "-mcpu=power8 -O2" } */

19199

+/* { dg-final { scan-assembler-times "bcdadd\[.\] " 4 } } */

19200

+/* { dg-final { scan-assembler-times "bcdsub\[.\] " 4 } } */

19201

+/* { dg-final { scan-assembler-not "bl __builtin" } } */

19202

+/* { dg-final { scan-assembler-not "mtvsr" } } */

19203

+/* { dg-final { scan-assembler-not "mfvsr" } } */

19204

+/* { dg-final { scan-assembler-not "lvx" } } */

19205

+/* { dg-final { scan-assembler-not "lxvw4x" } } */

19206

+/* { dg-final { scan-assembler-not "lxvd2x" } } */

19207

+/* { dg-final { scan-assembler-not "stvx" } } */

19208

+/* { dg-final { scan-assembler-not "stxvw4x" } } */

19209

+/* { dg-final { scan-assembler-not "stxvd2x" } } */

19210

+

19211

+typedef __int128_t __attribute__((__vector_size__(16))) vector_128_t;

19212

+typedef __int128_t scalar_128_t;

19213

+typedef unsigned long long scalar_64_t;

19214

+

19215

+/* Test whether the peephole works to allow folding a bcdadd, with a

19216

+ bcdadd_<test> into a single instruction. */

19217

+

19218

+vector_128_t

19219

+do_add_lt (vector_128_t a, vector_128_t b, int *p)

19220

+{

19221

+ vector_128_t ret = __builtin_bcdadd (a, b, 0);

19222

+ if (__builtin_bcdadd_lt (a, b, 0))

19223

+ *p = 1;

19224

+

19225

+ return ret;

19226

+}

19227

+

19228

+vector_128_t

19229

+do_add_eq (vector_128_t a, vector_128_t b, int *p)

19230

+{

19231

+ vector_128_t ret = __builtin_bcdadd (a, b, 0);

19232

+ if (__builtin_bcdadd_eq (a, b, 0))

19233

+ *p = 1;

19234

+

19235

+ return ret;

19236

+}

19237

+

19238

+vector_128_t

19239

+do_add_gt (vector_128_t a, vector_128_t b, int *p)

19240

+{

19241

+ vector_128_t ret = __builtin_bcdadd (a, b, 0);

19242

+ if (__builtin_bcdadd_gt (a, b, 0))

19243

+ *p = 1;

19244

+

19245

+ return ret;

19246

+}

19247

+

19248

+vector_128_t

19249

+do_add_ov (vector_128_t a, vector_128_t b, int *p)

19250

+{

19251

+ vector_128_t ret = __builtin_bcdadd (a, b, 0);

19252

+ if (__builtin_bcdadd_ov (a, b, 0))

19253

+ *p = 1;

19254

+

19255

+ return ret;

19256

+}

19257

+

19258

+vector_128_t

19259

+do_sub_lt (vector_128_t a, vector_128_t b, int *p)

19260

+{

19261

+ vector_128_t ret = __builtin_bcdsub (a, b, 0);

19262

+ if (__builtin_bcdsub_lt (a, b, 0))

19263

+ *p = 1;

19264

+

19265

+ return ret;

19266

+}

19267

+

19268

+vector_128_t

19269

+do_sub_eq (vector_128_t a, vector_128_t b, int *p)

19270

+{

19271

+ vector_128_t ret = __builtin_bcdsub (a, b, 0);

19272

+ if (__builtin_bcdsub_eq (a, b, 0))

19273

+ *p = 1;

19274

+

19275

+ return ret;

19276

+}

19277

+

19278

+vector_128_t

19279

+do_sub_gt (vector_128_t a, vector_128_t b, int *p)

19280

+{

19281

+ vector_128_t ret = __builtin_bcdsub (a, b, 0);

19282

+ if (__builtin_bcdsub_gt (a, b, 0))

19283

+ *p = 1;

19284

+

19285

+ return ret;

19286

+}

19287

+

19288

+vector_128_t

19289

+do_sub_ov (vector_128_t a, vector_128_t b, int *p)

19290

+{

19291

+ vector_128_t ret = __builtin_bcdsub (a, b, 0);

19292

+ if (__builtin_bcdsub_ov (a, b, 0))

19293

+ *p = 1;

19294

+

19295

+ return ret;

19296

+}

19297

Index: gcc/testsuite/gcc.target/powerpc/pr57949-1.c

19298

===================================================================

19299

--- a/src/gcc/testsuite/gcc.target/powerpc/pr57949-1.c (.../tags/gcc_4_8_2_release)

19300

+++ b/src/gcc/testsuite/gcc.target/powerpc/pr57949-1.c (.../branches/gcc-4_8-branch)

19301

@@ -0,0 +1,20 @@

19302

+/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */

19303

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

19304

+/* { dg-skip-if "" { powerpc_elfv2 } { "*" } { "" } } */

19305

+/* { dg-options "-O2 -mcpu=power7 -mno-compat-align-parm" } */

19306

+

19307

+/* Verify that vs is 16-byte aligned with -mcompat-align-parm. */

19308

+

19309

+typedef float v4sf __attribute__ ((vector_size (16)));

19310

+struct s { long m; v4sf v; };

19311

+long n;

19312

+v4sf ve;

19313

+

19314

+void pr57949 (long d1, long d2, long d3, long d4, long d5, long d6,

19315

+ long d7, long d8, long d9, struct s vs) {

19316

+ n = vs.m;

19317

+ ve = vs.v;

19318

+}

19319

+

19320

+/* { dg-final { scan-assembler "li \.\*,144" } } */

19321

+/* { dg-final { scan-assembler "ld \.\*,128\$1\$" } } */

19322

Index: gcc/testsuite/gcc.target/powerpc/atomic-p8.c

19323

===================================================================

19324

--- a/src/gcc/testsuite/gcc.target/powerpc/atomic-p8.c (.../tags/gcc_4_8_2_release)

19325

+++ b/src/gcc/testsuite/gcc.target/powerpc/atomic-p8.c (.../branches/gcc-4_8-branch)

19326

@@ -0,0 +1,237 @@

19327

+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */

19328

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

19329

+/* { dg-require-effective-target powerpc_p8vector_ok } */

19330

+/* { dg-options "-mcpu=power8 -O2" } */

19331

+/* { dg-final { scan-assembler-times "lbarx" 7 } } */

19332

+/* { dg-final { scan-assembler-times "lharx" 7 } } */

19333

+/* { dg-final { scan-assembler-times "lwarx" 7 } } */

19334

+/* { dg-final { scan-assembler-times "ldarx" 7 } } */

19335

+/* { dg-final { scan-assembler-times "lqarx" 7 } } */

19336

+/* { dg-final { scan-assembler-times "stbcx" 7 } } */

19337

+/* { dg-final { scan-assembler-times "sthcx" 7 } } */

19338

+/* { dg-final { scan-assembler-times "stwcx" 7 } } */

19339

+/* { dg-final { scan-assembler-times "stdcx" 7 } } */

19340

+/* { dg-final { scan-assembler-times "stqcx" 7 } } */

19341

+/* { dg-final { scan-assembler-not "bl __atomic" } } */

19342

+/* { dg-final { scan-assembler-times "isync" 20 } } */

19343

+/* { dg-final { scan-assembler-times "lwsync" 10 } } */

19344

+/* { dg-final { scan-assembler-not "mtvsrd" } } */

19345

+/* { dg-final { scan-assembler-not "mtvsrwa" } } */

19346

+/* { dg-final { scan-assembler-not "mtvsrwz" } } */

19347

+/* { dg-final { scan-assembler-not "mfvsrd" } } */

19348

+/* { dg-final { scan-assembler-not "mfvsrwz" } } */

19349

+

19350

+/* Test for the byte atomic operations on power8 using lbarx/stbcx. */

19351

+char

19352

+char_fetch_add_relaxed (char *ptr, int value)

19353

+{

19354

+ return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED);

19355

+}

19356

+

19357

+char

19358

+char_fetch_sub_consume (char *ptr, int value)

19359

+{

19360

+ return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME);

19361

+}

19362

+

19363

+char

19364

+char_fetch_and_acquire (char *ptr, int value)

19365

+{

19366

+ return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE);

19367

+}

19368

+

19369

+char

19370

+char_fetch_ior_release (char *ptr, int value)

19371

+{

19372

+ return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE);

19373

+}

19374

+

19375

+char

19376

+char_fetch_xor_acq_rel (char *ptr, int value)

19377

+{

19378

+ return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL);

19379

+}

19380

+

19381

+char

19382

+char_fetch_nand_seq_cst (char *ptr, int value)

19383

+{

19384

+ return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST);

19385

+}

19386

+

19387

+void

19388

+char_val_compare_and_swap (char *p, int i, int j, char *q)

19389

+{

19390

+ *q = __sync_val_compare_and_swap (p, i, j);

19391

+}

19392

+

19393

+/* Test for the half word atomic operations on power8 using lharx/sthcx. */

19394

+short

19395

+short_fetch_add_relaxed (short *ptr, int value)

19396

+{

19397

+ return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED);

19398

+}

19399

+

19400

+short

19401

+short_fetch_sub_consume (short *ptr, int value)

19402

+{

19403

+ return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME);

19404

+}

19405

+

19406

+short

19407

+short_fetch_and_acquire (short *ptr, int value)

19408

+{

19409

+ return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE);

19410

+}

19411

+

19412

+short

19413

+short_fetch_ior_release (short *ptr, int value)

19414

+{

19415

+ return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE);

19416

+}

19417

+

19418

+short

19419

+short_fetch_xor_acq_rel (short *ptr, int value)

19420

+{

19421

+ return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL);

19422

+}

19423

+

19424

+short

19425

+short_fetch_nand_seq_cst (short *ptr, int value)

19426

+{

19427

+ return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST);

19428

+}

19429

+

19430

+void

19431

+short_val_compare_and_swap (short *p, int i, int j, short *q)

19432

+{

19433

+ *q = __sync_val_compare_and_swap (p, i, j);

19434

+}

19435

+

19436

+/* Test for the word atomic operations on power8 using lwarx/stwcx. */

19437

+int

19438

+int_fetch_add_relaxed (int *ptr, int value)

19439

+{

19440

+ return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED);

19441

+}

19442

+

19443

+int

19444

+int_fetch_sub_consume (int *ptr, int value)

19445

+{

19446

+ return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME);

19447

+}

19448

+

19449

+int

19450

+int_fetch_and_acquire (int *ptr, int value)

19451

+{

19452

+ return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE);

19453

+}

19454

+

19455

+int

19456

+int_fetch_ior_release (int *ptr, int value)

19457

+{

19458

+ return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE);

19459

+}

19460

+

19461

+int

19462

+int_fetch_xor_acq_rel (int *ptr, int value)

19463

+{

19464

+ return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL);

19465

+}

19466

+

19467

+int

19468

+int_fetch_nand_seq_cst (int *ptr, int value)

19469

+{

19470

+ return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST);

19471

+}

19472

+

19473

+void

19474

+int_val_compare_and_swap (int *p, int i, int j, int *q)

19475

+{

19476

+ *q = __sync_val_compare_and_swap (p, i, j);

19477

+}

19478

+

19479

+/* Test for the double word atomic operations on power8 using ldarx/stdcx. */

19480

+long

19481

+long_fetch_add_relaxed (long *ptr, long value)

19482

+{

19483

+ return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED);

19484

+}

19485

+

19486

+long

19487

+long_fetch_sub_consume (long *ptr, long value)

19488

+{

19489

+ return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME);

19490

+}

19491

+

19492

+long

19493

+long_fetch_and_acquire (long *ptr, long value)

19494

+{

19495

+ return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE);

19496

+}

19497

+

19498

+long

19499

+long_fetch_ior_release (long *ptr, long value)

19500

+{

19501

+ return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE);

19502

+}

19503

+

19504

+long

19505

+long_fetch_xor_acq_rel (long *ptr, long value)

19506

+{

19507

+ return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL);

19508

+}

19509

+

19510

+long

19511

+long_fetch_nand_seq_cst (long *ptr, long value)

19512

+{

19513

+ return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST);

19514

+}

19515

+

19516

+void

19517

+long_val_compare_and_swap (long *p, long i, long j, long *q)

19518

+{

19519

+ *q = __sync_val_compare_and_swap (p, i, j);

19520

+}

19521

+

19522

+/* Test for the quad word atomic operations on power8 using ldarx/stdcx. */

19523

+__int128_t

19524

+quad_fetch_add_relaxed (__int128_t *ptr, __int128_t value)

19525

+{

19526

+ return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED);

19527

+}

19528

+

19529

+__int128_t

19530

+quad_fetch_sub_consume (__int128_t *ptr, __int128_t value)

19531

+{

19532

+ return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME);

19533

+}

19534

+

19535

+__int128_t

19536

+quad_fetch_and_acquire (__int128_t *ptr, __int128_t value)

19537

+{

19538

+ return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE);

19539

+}

19540

+

19541

+__int128_t

19542

+quad_fetch_ior_release (__int128_t *ptr, __int128_t value)

19543

+{

19544

+ return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE);

19545

+}

19546

+

19547

+__int128_t

19548

+quad_fetch_xor_acq_rel (__int128_t *ptr, __int128_t value)

19549

+{

19550

+ return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL);

19551

+}

19552

+

19553

+__int128_t

19554

+quad_fetch_nand_seq_cst (__int128_t *ptr, __int128_t value)

19555

+{

19556

+ return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST);

19557

+}

19558

+

19559

+void

19560

+quad_val_compare_and_swap (__int128_t *p, __int128_t i, __int128_t j, __int128_t *q)

19561

+{

19562

+ *q = __sync_val_compare_and_swap (p, i, j);

19563

+}

19564

Index: gcc/testsuite/gcc.target/powerpc/sd-pwr6.c

19565

===================================================================

19566

--- a/src/gcc/testsuite/gcc.target/powerpc/sd-pwr6.c (.../tags/gcc_4_8_2_release)

19567

+++ b/src/gcc/testsuite/gcc.target/powerpc/sd-pwr6.c (.../branches/gcc-4_8-branch)

19568

@@ -0,0 +1,19 @@

19569

+/* { dg-do compile { target { powerpc*-*-* } } } */

19570

+/* { dg-skip-if "" { powerpc*-*-darwin* powerpc-ibm-aix* } { "*" } { "" } } */

19571

+/* { dg-require-effective-target powerpc_vsx_ok } */

19572

+/* { dg-options "-O2 -mcpu=power6 -mhard-dfp" } */

19573

+/* { dg-final { scan-assembler-not "lfiwzx" } } */

19574

+/* { dg-final { scan-assembler-times "lfd" 2 } } */

19575

+/* { dg-final { scan-assembler-times "dctdp" 2 } } */

19576

+/* { dg-final { scan-assembler-times "dadd" 1 } } */

19577

+/* { dg-final { scan-assembler-times "drsp" 1 } } */

19578

+

19579

+/* Test that for power6 we need to use a bounce buffer on the stack to load

19580

+ SDmode variables because the power6 does not have a way to directly load

19581

+ 32-bit values from memory. */

19582

+_Decimal32 a;

19583

+

19584

+void inc_dec32 (void)

19585

+{

19586

+ a += (_Decimal32) 1.0;

19587

+}

19588

Index: gcc/testsuite/gcc.target/powerpc/recip-4.c

19589

===================================================================

19590

--- a/src/gcc/testsuite/gcc.target/powerpc/recip-4.c (.../tags/gcc_4_8_2_release)

19591

+++ b/src/gcc/testsuite/gcc.target/powerpc/recip-4.c (.../branches/gcc-4_8-branch)

19592

@@ -7,8 +7,8 @@

19593

/* { dg-final { scan-assembler-times "xvnmsub.dp" 2 } } */

19594

/* { dg-final { scan-assembler-times "xvrsqrtesp" 1 } } */

19595

/* { dg-final { scan-assembler-times "xvmsub.sp" 1 } } */

19596

-/* { dg-final { scan-assembler-times "xvmulsp" 4 } } */

19597

-/* { dg-final { scan-assembler-times "xvnmsub.sp" 2 } } */

19598

+/* { dg-final { scan-assembler-times "xvmulsp" 2 } } */

19599

+/* { dg-final { scan-assembler-times "xvnmsub.sp" 1 } } */

19600

19601

#define SIZE 1024

19602

19603

Index: gcc/testsuite/gcc.target/powerpc/no-r11-3.c

19604

===================================================================

19605

--- a/src/gcc/testsuite/gcc.target/powerpc/no-r11-3.c (.../tags/gcc_4_8_2_release)

19606

+++ b/src/gcc/testsuite/gcc.target/powerpc/no-r11-3.c (.../branches/gcc-4_8-branch)

19607

@@ -1,5 +1,6 @@

19608

/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */

19609

/* { dg-skip-if "" { *-*-darwin* } { "*" } { "" } } */

19610

+/* { dg-skip-if "" { powerpc_elfv2 } { "*" } { "" } } */

19611

/* { dg-options "-O2 -mno-pointers-to-nested-functions" } */

19612

19613

extern void ext_call (int (func) (void));

19614

Index: gcc/testsuite/gcc.target/powerpc/pack02.c

19615

===================================================================

19616

--- a/src/gcc/testsuite/gcc.target/powerpc/pack02.c (.../tags/gcc_4_8_2_release)

19617

+++ b/src/gcc/testsuite/gcc.target/powerpc/pack02.c (.../branches/gcc-4_8-branch)

19618

@@ -0,0 +1,95 @@

19619

+/* { dg-do run { target { powerpc*-*-linux* } } } */

19620

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

19621

+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */

19622

+/* { dg-require-effective-target powerpc_fprs } */

19623

+/* { dg-options "-O2 -mhard-float" } */

19624

+

19625

+#include <stddef.h>

19626

+#include <stdlib.h>

19627

+#include <math.h>

19628

+

19629

+#ifdef DEBUG

19630

+#include <stdio.h>

19631

+#endif

19632

+

19633

+int

19634

+main (void)

19635

+{

19636

+ double high = pow (2.0, 60);

19637

+ double low = 2.0;

19638

+ long double a = ((long double)high) + ((long double)low);

19639

+ double x0 = __builtin_unpack_longdouble (a, 0);

19640

+ double x1 = __builtin_unpack_longdouble (a, 1);

19641

+ long double b = __builtin_pack_longdouble (x0, x1);

19642

+

19643

+#ifdef DEBUG

19644

+ {

19645

+ size_t i;

19646

+ union {

19647

+ long double ld;

19648

+ double d;

19649

+ unsigned char uc[sizeof (long double)];

19650

+ char c[sizeof (long double)];

19651

+ } u;

19652

+

19653

+ printf ("a = 0x");

19654

+ u.ld = a;

19655

+ for (i = 0; i < sizeof (long double); i++)

19656

+ printf ("%.2x", u.uc[i]);

19657

+

19658

+ printf (", %Lg\n", a);

19659

+

19660

+ printf ("b = 0x");

19661

+ u.ld = b;

19662

+ for (i = 0; i < sizeof (long double); i++)

19663

+ printf ("%.2x", u.uc[i]);

19664

+

19665

+ printf (", %Lg\n", b);

19666

+

19667

+ printf ("hi = 0x");

19668

+ u.d = high;

19669

+ for (i = 0; i < sizeof (double); i++)

19670

+ printf ("%.2x", u.uc[i]);

19671

+

19672

+ printf (",%*s %g\n", (int)(2 * (sizeof (long double) - sizeof (double))), "", high);

19673

+

19674

+ printf ("lo = 0x");

19675

+ u.d = low;

19676

+ for (i = 0; i < sizeof (double); i++)

19677

+ printf ("%.2x", u.uc[i]);

19678

+

19679

+ printf (",%*s %g\n", (int)(2 * (sizeof (long double) - sizeof (double))), "", low);

19680

+

19681

+ printf ("x0 = 0x");

19682

+ u.d = x0;

19683

+ for (i = 0; i < sizeof (double); i++)

19684

+ printf ("%.2x", u.uc[i]);

19685

+

19686

+ printf (",%*s %g\n", (int)(2 * (sizeof (long double) - sizeof (double))), "", x0);

19687

+

19688

+ printf ("x1 = 0x");

19689

+ u.d = x1;

19690

+ for (i = 0; i < sizeof (double); i++)

19691

+ printf ("%.2x", u.uc[i]);

19692

+

19693

+ printf (",%*s %g\n", (int)(2 * (sizeof (long double) - sizeof (double))), "", x1);

19694

+ }

19695

+#endif

19696

+

19697

+ if (high != x0)

19698

+ abort ();

19699

+

19700

+ if (low != x1)

19701

+ abort ();

19702

+

19703

+ if (a != b)

19704

+ abort ();

19705

+

19706

+ if (x0 != high)

19707

+ abort ();

19708

+

19709

+ if (x1 != low)

19710

+ abort ();

19711

+

19712

+ return 0;

19713

+}

19714

Index: gcc/testsuite/gcc.target/powerpc/crypto-builtin-1.c

19715

===================================================================

19716

--- a/src/gcc/testsuite/gcc.target/powerpc/crypto-builtin-1.c (.../tags/gcc_4_8_2_release)

19717

+++ b/src/gcc/testsuite/gcc.target/powerpc/crypto-builtin-1.c (.../branches/gcc-4_8-branch)

19718

@@ -0,0 +1,130 @@

19719

+/* { dg-do compile { target { powerpc*-*-* } } } */

19720

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

19721

+/* { dg-require-effective-target powerpc_p8vector_ok } */

19722

+/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model -fno-unroll-loops -fno-unroll-all-loops" } */

19723

+

19724

+typedef vector unsigned long long crypto_t;

19725

+typedef vector unsigned long long v2di_t;

19726

+typedef vector unsigned int v4si_t;

19727

+typedef vector unsigned short v8hi_t;

19728

+typedef vector unsigned char v16qi_t;

19729

+

19730

+crypto_t crpyto1 (crypto_t a)

19731

+{

19732

+ return __builtin_crypto_vsbox (a);

19733

+}

19734

+

19735

+crypto_t crypto2 (crypto_t a, crypto_t b)

19736

+{

19737

+ return __builtin_crypto_vcipher (a, b);

19738

+}

19739

+

19740

+crypto_t crypto3 (crypto_t a, crypto_t b)

19741

+{

19742

+ return __builtin_crypto_vcipherlast (a, b);

19743

+}

19744

+

19745

+crypto_t crypto4 (crypto_t a, crypto_t b)

19746

+{

19747

+ return __builtin_crypto_vncipher (a, b);

19748

+}

19749

+

19750

+crypto_t crypto5 (crypto_t a, crypto_t b)

19751

+{

19752

+ return __builtin_crypto_vncipherlast (a, b);

19753

+}

19754

+

19755

+v16qi_t crypto6a (v16qi_t a, v16qi_t b, v16qi_t c)

19756

+{

19757

+ return __builtin_crypto_vpermxor (a, b, c);

19758

+}

19759

+

19760

+v8hi_t crypto6b (v8hi_t a, v8hi_t b, v8hi_t c)

19761

+{

19762

+ return __builtin_crypto_vpermxor (a, b, c);

19763

+}

19764

+

19765

+v4si_t crypto6c (v4si_t a, v4si_t b, v4si_t c)

19766

+{

19767

+ return __builtin_crypto_vpermxor (a, b, c);

19768

+}

19769

+

19770

+v2di_t crypto6d (v2di_t a, v2di_t b, v2di_t c)

19771

+{

19772

+ return __builtin_crypto_vpermxor (a, b, c);

19773

+}

19774

+

19775

+v16qi_t crypto7a (v16qi_t a, v16qi_t b)

19776

+{

19777

+ return __builtin_crypto_vpmsumb (a, b);

19778

+}

19779

+

19780

+v16qi_t crypto7b (v16qi_t a, v16qi_t b)

19781

+{

19782

+ return __builtin_crypto_vpmsum (a, b);

19783

+}

19784

+

19785

+v8hi_t crypto7c (v8hi_t a, v8hi_t b)

19786

+{

19787

+ return __builtin_crypto_vpmsumh (a, b);

19788

+}

19789

+

19790

+v8hi_t crypto7d (v8hi_t a, v8hi_t b)

19791

+{

19792

+ return __builtin_crypto_vpmsum (a, b);

19793

+}

19794

+

19795

+v4si_t crypto7e (v4si_t a, v4si_t b)

19796

+{

19797

+ return __builtin_crypto_vpmsumw (a, b);

19798

+}

19799

+

19800

+v4si_t crypto7f (v4si_t a, v4si_t b)

19801

+{

19802

+ return __builtin_crypto_vpmsum (a, b);

19803

+}

19804

+

19805

+v2di_t crypto7g (v2di_t a, v2di_t b)

19806

+{

19807

+ return __builtin_crypto_vpmsumd (a, b);

19808

+}

19809

+

19810

+v2di_t crypto7h (v2di_t a, v2di_t b)

19811

+{

19812

+ return __builtin_crypto_vpmsum (a, b);

19813

+}

19814

+

19815

+v2di_t crypto8a (v2di_t a)

19816

+{

19817

+ return __builtin_crypto_vshasigmad (a, 0, 8);

19818

+}

19819

+

19820

+v2di_t crypto8b (v2di_t a)

19821

+{

19822

+ return __builtin_crypto_vshasigma (a, 0, 8);

19823

+}

19824

+

19825

+v4si_t crypto8c (v4si_t a)

19826

+{

19827

+ return __builtin_crypto_vshasigmaw (a, 1, 15);

19828

+}

19829

+

19830

+v4si_t crypto8d (v4si_t a)

19831

+{

19832

+ return __builtin_crypto_vshasigma (a, 1, 15);

19833

+}

19834

+

19835

+/* Note space is used after the instruction so that vcipherlast does not match

19836

+ vcipher. */

19837

+/* { dg-final { scan-assembler-times "vcipher " 1 } } */

19838

+/* { dg-final { scan-assembler-times "vcipherlast " 1 } } */

19839

+/* { dg-final { scan-assembler-times "vncipher " 1 } } */

19840

+/* { dg-final { scan-assembler-times "vncipherlast " 1 } } */

19841

+/* { dg-final { scan-assembler-times "vpermxor " 4 } } */

19842

+/* { dg-final { scan-assembler-times "vpmsumb " 2 } } */

19843

+/* { dg-final { scan-assembler-times "vpmsumd " 2 } } */

19844

+/* { dg-final { scan-assembler-times "vpmsumh " 2 } } */

19845

+/* { dg-final { scan-assembler-times "vpmsumw " 2 } } */

19846

+/* { dg-final { scan-assembler-times "vsbox " 1 } } */

19847

+/* { dg-final { scan-assembler-times "vshasigmad " 2 } } */

19848

+/* { dg-final { scan-assembler-times "vshasigmaw " 2 } } */

19849

Index: gcc/testsuite/gcc.target/powerpc/pr42747.c

19850

===================================================================

19851

--- a/src/gcc/testsuite/gcc.target/powerpc/pr42747.c (.../tags/gcc_4_8_2_release)

19852

+++ b/src/gcc/testsuite/gcc.target/powerpc/pr42747.c (.../branches/gcc-4_8-branch)

19853

@@ -5,4 +5,4 @@

19854

19855

double foo (double x) { return __builtin_sqrt (x); }

19856

19857

-/* { dg-final { scan-assembler "xssqrtdp" } } */

19858

+/* { dg-final { scan-assembler "xssqrtdp\|fsqrt" } } */

19859

Index: gcc/testsuite/gcc.target/powerpc/dfp-dd-2.c

19860

===================================================================

19861

--- a/src/gcc/testsuite/gcc.target/powerpc/dfp-dd-2.c (.../tags/gcc_4_8_2_release)

19862

+++ b/src/gcc/testsuite/gcc.target/powerpc/dfp-dd-2.c (.../branches/gcc-4_8-branch)

19863

@@ -0,0 +1,26 @@

19864

+/* Test generation of DFP instructions for POWER6. */

19865

+/* { dg-do compile { target { powerpc*-*-linux* && powerpc_fprs } } } */

19866

+/* { dg-options "-std=gnu99 -O1 -mcpu=power6" } */

19867

+

19868

+/* { dg-final { scan-assembler-times "fneg" 1 } } */

19869

+/* { dg-final { scan-assembler-times "fabs" 1 } } */

19870

+/* { dg-final { scan-assembler-times "fnabs" 1 } } */

19871

+/* { dg-final { scan-assembler-times "fmr" 0 } } */

19872

+

19873

+_Decimal64

19874

+func1 (_Decimal64 a, _Decimal64 b)

19875

+{

19876

+ return -b;

19877

+}

19878

+

19879

+_Decimal64

19880

+func2 (_Decimal64 a, _Decimal64 b)

19881

+{

19882

+ return __builtin_fabsd64 (b);

19883

+}

19884

+

19885

+_Decimal64

19886

+func3 (_Decimal64 a, _Decimal64 b)

19887

+{

19888

+ return - __builtin_fabsd64 (b);

19889

+}

19890

Index: gcc/testsuite/gcc.target/powerpc/direct-move-float1.c

19891

===================================================================

19892

--- a/src/gcc/testsuite/gcc.target/powerpc/direct-move-float1.c (.../tags/gcc_4_8_2_release)

19893

+++ b/src/gcc/testsuite/gcc.target/powerpc/direct-move-float1.c (.../branches/gcc-4_8-branch)

19894

@@ -0,0 +1,18 @@

19895

+/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */

19896

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

19897

+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */

19898

+/* { dg-require-effective-target powerpc_p8vector_ok } */

19899

+/* { dg-options "-mcpu=power8 -O2" } */

19900

+/* { dg-final { scan-assembler "mtvsrd" } } */

19901

+/* { dg-final { scan-assembler "mfvsrd" } } */

19902

+/* { dg-final { scan-assembler "xscvdpspn" } } */

19903

+/* { dg-final { scan-assembler "xscvspdpn" } } */

19904

+

19905

+/* Check code generation for direct move for float types. */

19906

+

19907

+#define TYPE float

19908

+#define IS_FLOAT 1

19909

+#define NO_ALTIVEC 1

19910

+#define VSX_REG_ATTR "ww"

19911

+

19912

+#include "direct-move.h"

19913

Index: gcc/testsuite/gcc.target/powerpc/dfp-td-2.c

19914

===================================================================

19915

--- a/src/gcc/testsuite/gcc.target/powerpc/dfp-td-2.c (.../tags/gcc_4_8_2_release)

19916

+++ b/src/gcc/testsuite/gcc.target/powerpc/dfp-td-2.c (.../branches/gcc-4_8-branch)

19917

@@ -0,0 +1,29 @@

19918

+/* Test generation of DFP instructions for POWER6. */

19919

+/* { dg-do compile { target { powerpc*-*-linux* && powerpc_fprs } } } */

19920

+/* { dg-options "-std=gnu99 -O1 -mcpu=power6" } */

19921

+

19922

+/* { dg-final { scan-assembler-times "fneg" 1 } } */

19923

+/* { dg-final { scan-assembler-times "fabs" 1 } } */

19924

+/* { dg-final { scan-assembler-times "fnabs" 1 } } */

19925

+/* { dg-final { scan-assembler-times "fmr" 0 } } */

19926

+

19927

+/* These tests verify we only generate fneg, fabs and fnabs

19928

+ instructions and no fmr's since these are done in place. */

19929

+

19930

+_Decimal128

19931

+func1 (_Decimal128 a)

19932

+{

19933

+ return -a;

19934

+}

19935

+

19936

+_Decimal128

19937

+func2 (_Decimal128 a)

19938

+{

19939

+ return __builtin_fabsd128 (a);

19940

+}

19941

+

19942

+_Decimal128

19943

+func3 (_Decimal128 a)

19944

+{

19945

+ return - __builtin_fabsd128 (a);

19946

+}

19947

Index: gcc/testsuite/gcc.target/powerpc/p8vector-builtin-5.c

19948

===================================================================

19949

--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-5.c (.../tags/gcc_4_8_2_release)

19950

+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-5.c (.../branches/gcc-4_8-branch)

19951

@@ -0,0 +1,105 @@

19952

+/* { dg-do compile { target { powerpc*-*-* } } } */

19953

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

19954

+/* { dg-require-effective-target powerpc_p8vector_ok } */

19955

+/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model -fno-unroll-loops -fno-unroll-all-loops" } */

19956

+

19957

+#include <altivec.h>

19958

+

19959

+#ifndef SIZE

19960

+#define SIZE 1024

19961

+#endif

19962

+

19963

+#ifndef ALIGN

19964

+#define ALIGN 32

19965

+#endif

19966

+

19967

+#ifndef ATTR_ALIGN

19968

+#define ATTR_ALIGN __attribute__((__aligned__(ALIGN)))

19969

+#endif

19970

+

19971

+#define DOIT(TYPE, PREFIX) \

19972

+TYPE PREFIX ## _eqv_builtin (TYPE a, TYPE b) \

19973

+{ \

19974

+ return vec_eqv (a, b); \

19975

+} \

19976

+ \

19977

+TYPE PREFIX ## _eqv_arith (TYPE a, TYPE b) \

19978

+{ \

19979

+ return ~(a ^ b); \

19980

+} \

19981

+ \

19982

+TYPE PREFIX ## _nand_builtin (TYPE a, TYPE b) \

19983

+{ \

19984

+ return vec_nand (a, b); \

19985

+} \

19986

+ \

19987

+TYPE PREFIX ## _nand_arith1 (TYPE a, TYPE b) \

19988

+{ \

19989

+ return ~(a & b); \

19990

+} \

19991

+ \

19992

+TYPE PREFIX ## _nand_arith2 (TYPE a, TYPE b) \

19993

+{ \

19994

+ return (~a) | (~b); \

19995

+} \

19996

+ \

19997

+TYPE PREFIX ## _orc_builtin (TYPE a, TYPE b) \

19998

+{ \

19999

+ return vec_orc (a, b); \

20000

+} \

20001

+ \

20002

+TYPE PREFIX ## _orc_arith1 (TYPE a, TYPE b) \

20003

+{ \

20004

+ return (~ a) | b; \

20005

+} \

20006

+ \

20007

+TYPE PREFIX ## _orc_arith2 (TYPE a, TYPE b) \

20008

+{ \

20009

+ return a | (~ b); \

20010

+}

20011

+

20012

+#define DOIT_FLOAT(TYPE, PREFIX) \

20013

+TYPE PREFIX ## _eqv_builtin (TYPE a, TYPE b) \

20014

+{ \

20015

+ return vec_eqv (a, b); \

20016

+} \

20017

+ \

20018

+TYPE PREFIX ## _nand_builtin (TYPE a, TYPE b) \

20019

+{ \

20020

+ return vec_nand (a, b); \

20021

+} \

20022

+ \

20023

+TYPE PREFIX ## _orc_builtin (TYPE a, TYPE b) \

20024

+{ \

20025

+ return vec_orc (a, b); \

20026

+}

20027

+

20028

+typedef vector signed char sign_char_vec;

20029

+typedef vector short sign_short_vec;

20030

+typedef vector int sign_int_vec;

20031

+typedef vector long long sign_llong_vec;

20032

+

20033

+typedef vector unsigned char uns_char_vec;

20034

+typedef vector unsigned short uns_short_vec;

20035

+typedef vector unsigned int uns_int_vec;

20036

+typedef vector unsigned long long uns_llong_vec;

20037

+

20038

+typedef vector float float_vec;

20039

+typedef vector double double_vec;

20040

+

20041

+DOIT(sign_char_vec, sign_char)

20042

+DOIT(sign_short_vec, sign_short)

20043

+DOIT(sign_int_vec, sign_int)

20044

+DOIT(sign_llong_vec, sign_llong)

20045

+

20046

+DOIT(uns_char_vec, uns_char)

20047

+DOIT(uns_short_vec, uns_short)

20048

+DOIT(uns_int_vec, uns_int)

20049

+DOIT(uns_llong_vec, uns_llong)

20050

+

20051

+DOIT_FLOAT(float_vec, float)

20052

+DOIT_FLOAT(double_vec, double)

20053

+

20054

+/* { dg-final { scan-assembler-times "xxleqv" 18 } } */

20055

+/* { dg-final { scan-assembler-times "xxlnand" 26 } } */

20056

+/* { dg-final { scan-assembler-times "xxlorc" 26 } } */

20057

Index: gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-5.c

20058

===================================================================

20059

--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-5.c (.../tags/gcc_4_8_2_release)

20060

+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-5.c (.../branches/gcc-4_8-branch)

20061

@@ -0,0 +1,87 @@

20062

+/* { dg-do compile { target { powerpc*-*-* } } } */

20063

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

20064

+/* { dg-require-effective-target powerpc_p8vector_ok } */

20065

+/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model -fno-unroll-loops -fno-unroll-all-loops" } */

20066

+

20067

+#ifndef SIZE

20068

+#define SIZE 1024

20069

+#endif

20070

+

20071

+#ifndef ALIGN

20072

+#define ALIGN 32

20073

+#endif

20074

+

20075

+#ifndef ATTR_ALIGN

20076

+#define ATTR_ALIGN __attribute__((__aligned__(ALIGN)))

20077

+#endif

20078

+

20079

+#ifndef TYPE

20080

+#define TYPE unsigned int

20081

+#endif

20082

+

20083

+TYPE in1 [SIZE] ATTR_ALIGN;

20084

+TYPE in2 [SIZE] ATTR_ALIGN;

20085

+TYPE eqv [SIZE] ATTR_ALIGN;

20086

+TYPE nand1[SIZE] ATTR_ALIGN;

20087

+TYPE nand2[SIZE] ATTR_ALIGN;

20088

+TYPE orc1 [SIZE] ATTR_ALIGN;

20089

+TYPE orc2 [SIZE] ATTR_ALIGN;

20090

+

20091

+void

20092

+do_eqv (void)

20093

+{

20094

+ unsigned long i;

20095

+

20096

+ for (i = 0; i < SIZE; i++)

20097

+ {

20098

+ eqv[i] = ~(in1[i] ^ in2[i]);

20099

+ }

20100

+}

20101

+

20102

+void

20103

+do_nand1 (void)

20104

+{

20105

+ unsigned long i;

20106

+

20107

+ for (i = 0; i < SIZE; i++)

20108

+ {

20109

+ nand1[i] = ~(in1[i] & in2[i]);

20110

+ }

20111

+}

20112

+

20113

+void

20114

+do_nand2 (void)

20115

+{

20116

+ unsigned long i;

20117

+

20118

+ for (i = 0; i < SIZE; i++)

20119

+ {

20120

+ nand2[i] = (~in1[i]) | (~in2[i]);

20121

+ }

20122

+}

20123

+

20124

+void

20125

+do_orc1 (void)

20126

+{

20127

+ unsigned long i;

20128

+

20129

+ for (i = 0; i < SIZE; i++)

20130

+ {

20131

+ orc1[i] = (~in1[i]) | in2[i];

20132

+ }

20133

+}

20134

+

20135

+void

20136

+do_orc2 (void)

20137

+{

20138

+ unsigned long i;

20139

+

20140

+ for (i = 0; i < SIZE; i++)

20141

+ {

20142

+ orc1[i] = in1[i] | (~in2[i]);

20143

+ }

20144

+}

20145

+

20146

+/* { dg-final { scan-assembler-times "xxleqv" 1 } } */

20147

+/* { dg-final { scan-assembler-times "xxlnand" 2 } } */

20148

+/* { dg-final { scan-assembler-times "xxlorc" 2 } } */

20149

Index: gcc/testsuite/gcc.target/powerpc/pr57949-2.c

20150

===================================================================

20151

--- a/src/gcc/testsuite/gcc.target/powerpc/pr57949-2.c (.../tags/gcc_4_8_2_release)

20152

+++ b/src/gcc/testsuite/gcc.target/powerpc/pr57949-2.c (.../branches/gcc-4_8-branch)

20153

@@ -0,0 +1,20 @@

20154

+/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */

20155

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

20156

+/* { dg-skip-if "" { powerpc_elfv2 } { "*" } { "" } } */

20157

+/* { dg-options "-O2 -mcpu=power7" } */

20158

+

20159

+/* Verify that vs is not 16-byte aligned in the absence of -mno-compat-align-parm. */

20160

+

20161

+typedef float v4sf __attribute__ ((vector_size (16)));

20162

+struct s { long m; v4sf v; };

20163

+long n;

20164

+v4sf ve;

20165

+

20166

+void pr57949 (long d1, long d2, long d3, long d4, long d5, long d6,

20167

+ long d7, long d8, long d9, struct s vs) {

20168

+ n = vs.m;

20169

+ ve = vs.v;

20170

+}

20171

+

20172

+/* { dg-final { scan-assembler "ld .\*,136\$1\$" } } */

20173

+/* { dg-final { scan-assembler "ld .\*,120\$1\$" } } */

20174

Index: gcc/testsuite/gcc.target/powerpc/recip-5.c

20175

===================================================================

20176

--- a/src/gcc/testsuite/gcc.target/powerpc/recip-5.c (.../tags/gcc_4_8_2_release)

20177

+++ b/src/gcc/testsuite/gcc.target/powerpc/recip-5.c (.../branches/gcc-4_8-branch)

20178

@@ -4,8 +4,16 @@

20179

/* { dg-options "-O3 -ftree-vectorize -mrecip=all -ffast-math -mcpu=power7 -fno-unroll-loops" } */

20180

/* { dg-final { scan-assembler-times "xvredp" 4 } } */

20181

/* { dg-final { scan-assembler-times "xvresp" 5 } } */

20182

-/* { dg-final { scan-assembler-times "xsredp" 2 } } */

20183

-/* { dg-final { scan-assembler-times "fres" 2 } } */

20184

+/* { dg-final { scan-assembler-times "xsredp\|fre\ " 2 } } */

20185

+/* { dg-final { scan-assembler-times "xsresp\|fres" 2 } } */

20186

+/* { dg-final { scan-assembler-times "xsmulsp\|fmuls" 2 } } */

20187

+/* { dg-final { scan-assembler-times "xsnmsub.sp\|fnmsubs" 2 } } */

20188

+/* { dg-final { scan-assembler-times "xsmuldp\|fmul\ " 2 } } */

20189

+/* { dg-final { scan-assembler-times "xsnmsub.dp\|fnmsub\ " 4 } } */

20190

+/* { dg-final { scan-assembler-times "xvmulsp" 7 } } */

20191

+/* { dg-final { scan-assembler-times "xvnmsub.sp" 5 } } */

20192

+/* { dg-final { scan-assembler-times "xvmuldp" 6 } } */

20193

+/* { dg-final { scan-assembler-times "xvnmsub.dp" 8 } } */

20194

20195

#include <altivec.h>

20196

20197

Index: gcc/testsuite/gcc.target/powerpc/pack03.c

20198

===================================================================

20199

--- a/src/gcc/testsuite/gcc.target/powerpc/pack03.c (.../tags/gcc_4_8_2_release)

20200

+++ b/src/gcc/testsuite/gcc.target/powerpc/pack03.c (.../branches/gcc-4_8-branch)

20201

@@ -0,0 +1,88 @@

20202

+/* { dg-do run { target { powerpc*-*-linux* } } } */

20203

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

20204

+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */

20205

+/* { dg-require-effective-target dfprt } */

20206

+/* { dg-options "-O2 -mhard-dfp" } */

20207

+

20208

+#include <stddef.h>

20209

+#include <stdlib.h>

20210

+#include <math.h>

20211

+

20212

+#ifdef DEBUG

20213

+#include <stdio.h>

20214

+#endif

20215

+

20216

+int

20217

+main (void)

20218

+{

20219

+ _Decimal128 one = (_Decimal128)1.0;

20220

+ _Decimal128 two = (_Decimal128)2.0;

20221

+ _Decimal128 ten = (_Decimal128)10.0;

20222

+ _Decimal128 a = one;

20223

+ _Decimal128 b;

20224

+ _Decimal128 c;

20225

+ unsigned long long x0;

20226

+ unsigned long long x1;

20227

+ size_t i;

20228

+

20229

+ for (i = 0; i < 25; i++)

20230

+ a *= ten;

20231

+

20232

+ a += two;

20233

+

20234

+ x0 = __builtin_unpack_dec128 (a, 0);

20235

+ x1 = __builtin_unpack_dec128 (a, 1);

20236

+ b = __builtin_pack_dec128 (x0, x1);

20237

+ c = __builtin_dscliq (one, 25) + two;

20238

+

20239

+#ifdef DEBUG

20240

+ {

20241

+ union {

20242

+ _Decimal128 d;

20243

+ unsigned long long ull;

20244

+ unsigned char uc[sizeof (_Decimal128)];

20245

+ } u;

20246

+

20247

+ printf ("a = 0x");

20248

+ u.d = a;

20249

+ for (i = 0; i < sizeof (_Decimal128); i++)

20250

+ printf ("%.2x", u.uc[i]);

20251

+

20252

+ printf (", %Lg\n", (long double)a);

20253

+

20254

+ printf ("b = 0x");

20255

+ u.d = b;

20256

+ for (i = 0; i < sizeof (_Decimal128); i++)

20257

+ printf ("%.2x", u.uc[i]);

20258

+

20259

+ printf (", %Lg\n", (long double)b);

20260

+

20261

+ printf ("c = 0x");

20262

+ u.d = c;

20263

+ for (i = 0; i < sizeof (_Decimal128); i++)

20264

+ printf ("%.2x", u.uc[i]);

20265

+

20266

+ printf (", %Lg\n", (long double)c);

20267

+

20268

+ printf ("x0 = 0x");

20269

+ u.ull = x0;

20270

+ for (i = 0; i < sizeof (unsigned long long); i++)

20271

+ printf ("%.2x", u.uc[i]);

20272

+

20273

+ printf ("\nx1 = 0x");

20274

+ u.ull = x1;

20275

+ for (i = 0; i < sizeof (unsigned long long); i++)

20276

+ printf ("%.2x", u.uc[i]);

20277

+

20278

+ printf ("\n");

20279

+ }

20280

+#endif

20281

+

20282

+ if (a != b)

20283

+ abort ();

20284

+

20285

+ if (a != c)

20286

+ abort ();

20287

+

20288

+ return 0;

20289

+}

20290

Index: gcc/testsuite/gcc.target/powerpc/ppc64-abi-1.c

20291

===================================================================

20292

--- a/src/gcc/testsuite/gcc.target/powerpc/ppc64-abi-1.c (.../tags/gcc_4_8_2_release)

20293

+++ b/src/gcc/testsuite/gcc.target/powerpc/ppc64-abi-1.c (.../branches/gcc-4_8-branch)

20294

@@ -89,8 +89,10 @@

20295

long a1;

20296

long a2;

20297

long a3;

20298

+#if _CALL_ELF != 2

20299

long a4;

20300

long a5;

20301

+#endif

20302

parm_t slot[100];

20303

} stack_frame_t;

20304

20305

Index: gcc/testsuite/gcc.target/powerpc/direct-move-float2.c

20306

===================================================================

20307

--- a/src/gcc/testsuite/gcc.target/powerpc/direct-move-float2.c (.../tags/gcc_4_8_2_release)

20308

+++ b/src/gcc/testsuite/gcc.target/powerpc/direct-move-float2.c (.../branches/gcc-4_8-branch)

20309

@@ -0,0 +1,15 @@

20310

+/* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */

20311

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

20312

+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */

20313

+/* { dg-require-effective-target p8vector_hw } */

20314

+/* { dg-options "-mcpu=power8 -O2" } */

20315

+

20316

+/* Check whether we get the right bits for direct move at runtime. */

20317

+

20318

+#define TYPE float

20319

+#define IS_FLOAT 1

20320

+#define NO_ALTIVEC 1

20321

+#define DO_MAIN

20322

+#define VSX_REG_ATTR "ww"

20323

+

20324

+#include "direct-move.h"

20325

Index: gcc/testsuite/gcc.target/powerpc/direct-move-double1.c

20326

===================================================================

20327

--- a/src/gcc/testsuite/gcc.target/powerpc/direct-move-double1.c (.../tags/gcc_4_8_2_release)

20328

+++ b/src/gcc/testsuite/gcc.target/powerpc/direct-move-double1.c (.../branches/gcc-4_8-branch)

20329

@@ -0,0 +1,16 @@

20330

+/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */

20331

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

20332

+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */

20333

+/* { dg-require-effective-target powerpc_p8vector_ok } */

20334

+/* { dg-options "-mcpu=power8 -O2" } */

20335

+/* { dg-final { scan-assembler "mtvsrd" } } */

20336

+/* { dg-final { scan-assembler "mfvsrd" } } */

20337

+

20338

+/* Check code generation for direct move for double types. */

20339

+

20340

+#define TYPE double

20341

+#define IS_FLOAT 1

20342

+#define NO_ALTIVEC 1

20343

+#define VSX_REG_ATTR "ws"

20344

+

20345

+#include "direct-move.h"

20346

Index: gcc/testsuite/gcc.target/powerpc/dfp-td-3.c

20347

===================================================================

20348

--- a/src/gcc/testsuite/gcc.target/powerpc/dfp-td-3.c (.../tags/gcc_4_8_2_release)

20349

+++ b/src/gcc/testsuite/gcc.target/powerpc/dfp-td-3.c (.../branches/gcc-4_8-branch)

20350

@@ -0,0 +1,29 @@

20351

+/* Test generation of DFP instructions for POWER6. */

20352

+/* { dg-do compile { target { powerpc*-*-linux* && powerpc_fprs } } } */

20353

+/* { dg-options "-std=gnu99 -O1 -mcpu=power6" } */

20354

+

20355

+/* { dg-final { scan-assembler-times "fneg" 1 } } */

20356

+/* { dg-final { scan-assembler-times "fabs" 1 } } */

20357

+/* { dg-final { scan-assembler-times "fnabs" 1 } } */

20358

+/* { dg-final { scan-assembler-times "fmr" 3 } } */

20359

+

20360

+/* These tests verify we generate fneg, fabs and fnabs and

20361

+ associated fmr's since these are not done in place. */

20362

+

20363

+_Decimal128

20364

+func1 (_Decimal128 a, _Decimal128 b)

20365

+{

20366

+ return -b;

20367

+}

20368

+

20369

+_Decimal128

20370

+func2 (_Decimal128 a, _Decimal128 b)

20371

+{

20372

+ return __builtin_fabsd128 (b);

20373

+}

20374

+

20375

+_Decimal128

20376

+func3 (_Decimal128 a, _Decimal128 b)

20377

+{

20378

+ return - __builtin_fabsd128 (b);

20379

+}

20380

Index: gcc/testsuite/gcc.target/powerpc/p8vector-builtin-6.c

20381

===================================================================

20382

--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-6.c (.../tags/gcc_4_8_2_release)

20383

+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-6.c (.../branches/gcc-4_8-branch)

20384

@@ -0,0 +1,10 @@

20385

+/* { dg-do compile { target { powerpc*-*-* } } } */

20386

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

20387

+/* { dg-require-effective-target powerpc_p8vector_ok } */

20388

+/* { dg-options "-mcpu=power8 -O2" } */

20389

+

20390

+vector float dbl_to_float_p8 (double x) { return __builtin_vsx_xscvdpspn (x); }

20391

+double float_to_dbl_p8 (vector float x) { return __builtin_vsx_xscvspdpn (x); }

20392

+

20393

+/* { dg-final { scan-assembler "xscvdpspn" } } */

20394

+/* { dg-final { scan-assembler "xscvspdpn" } } */

20395

Index: gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c

20396

===================================================================

20397

--- a/src/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c (.../tags/gcc_4_8_2_release)

20398

+++ b/src/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c (.../branches/gcc-4_8-branch)

20399

@@ -16,9 +16,9 @@

20400

/* { dg-final { scan-assembler "xvrspiz" } } */

20401

/* { dg-final { scan-assembler "xsrdpi" } } */

20402

/* { dg-final { scan-assembler "xsrdpic" } } */

20403

-/* { dg-final { scan-assembler "xsrdpim" } } */

20404

-/* { dg-final { scan-assembler "xsrdpip" } } */

20405

-/* { dg-final { scan-assembler "xsrdpiz" } } */

20406

+/* { dg-final { scan-assembler "xsrdpim\|frim" } } */

20407

+/* { dg-final { scan-assembler "xsrdpip\|frip" } } */

20408

+/* { dg-final { scan-assembler "xsrdpiz\|friz" } } */

20409

/* { dg-final { scan-assembler "xsmaxdp" } } */

20410

/* { dg-final { scan-assembler "xsmindp" } } */

20411

/* { dg-final { scan-assembler "xxland" } } */

20412

Index: gcc/testsuite/gcc.target/powerpc/htm-builtin-1.c

20413

===================================================================

20414

--- a/src/gcc/testsuite/gcc.target/powerpc/htm-builtin-1.c (.../tags/gcc_4_8_2_release)

20415

+++ b/src/gcc/testsuite/gcc.target/powerpc/htm-builtin-1.c (.../branches/gcc-4_8-branch)

20416

@@ -0,0 +1,51 @@

20417

+/* { dg-do compile { target { powerpc*-*-* } } } */

20418

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

20419

+/* { dg-require-effective-target powerpc_htm_ok } */

20420

+/* { dg-options "-O2 -mhtm" } */

20421

+

20422

+/* { dg-final { scan-assembler-times "tbegin\\." 1 } } */

20423

+/* { dg-final { scan-assembler-times "tend\\." 2 } } */

20424

+/* { dg-final { scan-assembler-times "tabort\\." 2 } } */

20425

+/* { dg-final { scan-assembler-times "tabortdc\\." 1 } } */

20426

+/* { dg-final { scan-assembler-times "tabortdci\\." 1 } } */

20427

+/* { dg-final { scan-assembler-times "tabortwc\\." 1 } } */

20428

+/* { dg-final { scan-assembler-times "tabortwci\\." 2 } } */

20429

+/* { dg-final { scan-assembler-times "tcheck\\." 1 } } */

20430

+/* { dg-final { scan-assembler-times "trechkpt\\." 1 } } */

20431

+/* { dg-final { scan-assembler-times "treclaim\\." 1 } } */

20432

+/* { dg-final { scan-assembler-times "tsr\\." 3 } } */

20433

+/* { dg-final { scan-assembler-times "mfspr" 4 } } */

20434

+/* { dg-final { scan-assembler-times "mtspr" 4 } } */

20435

+

20436

+void use_builtins (long *p, char code, long *a, long *b)

20437

+{

20438

+ p[0] = __builtin_tbegin (0);

20439

+ p[1] = __builtin_tend (0);

20440

+ p[2] = __builtin_tendall ();

20441

+ p[3] = __builtin_tabort (0);

20442

+ p[4] = __builtin_tabort (code);

20443

+

20444

+ p[5] = __builtin_tabortdc (0xf, a[5], b[5]);

20445

+ p[6] = __builtin_tabortdci (0xf, a[6], 13);

20446

+ p[7] = __builtin_tabortwc (0xf, a[7], b[7]);

20447

+ p[8] = __builtin_tabortwci (0xf, a[8], 13);

20448

+

20449

+ p[9] = __builtin_tcheck (5);

20450

+ p[10] = __builtin_trechkpt ();

20451

+ p[11] = __builtin_treclaim (0);

20452

+ p[12] = __builtin_tresume ();

20453

+ p[13] = __builtin_tsuspend ();

20454

+ p[14] = __builtin_tsr (0);

20455

+ p[15] = __builtin_ttest (); /* This expands to a tabortwci. */

20456

+

20457

+

20458

+ p[16] = __builtin_get_texasr ();

20459

+ p[17] = __builtin_get_texasru ();

20460

+ p[18] = __builtin_get_tfhar ();

20461

+ p[19] = __builtin_get_tfiar ();

20462

+

20463

+ __builtin_set_texasr (a[20]);

20464

+ __builtin_set_texasru (a[21]);

20465

+ __builtin_set_tfhar (a[22]);

20466

+ __builtin_set_tfiar (a[23]);

20467

+}

20468

Index: gcc/testsuite/gcc.target/powerpc/bool.c

20469

===================================================================

20470

--- a/src/gcc/testsuite/gcc.target/powerpc/bool.c (.../tags/gcc_4_8_2_release)

20471

+++ b/src/gcc/testsuite/gcc.target/powerpc/bool.c (.../branches/gcc-4_8-branch)

20472

@@ -0,0 +1,14 @@

20473

+/* { dg-do compile { target { powerpc*-*-* } } } */

20474

+/* { dg-options "-O2" } */

20475

+/* { dg-final { scan-assembler "eqv" } } */

20476

+/* { dg-final { scan-assembler "nand" } } */

20477

+/* { dg-final { scan-assembler "nor" } } */

20478

+

20479

+#ifndef TYPE

20480

+#define TYPE unsigned long

20481

+#endif

20482

+

20483

+TYPE op1 (TYPE a, TYPE b) { return ~(a ^ b); } /* eqv */

20484

+TYPE op2 (TYPE a, TYPE b) { return ~(a & b); } /* nand */

20485

+TYPE op3 (TYPE a, TYPE b) { return ~(a | b); } /* nor */

20486

+

20487

Index: gcc/testsuite/gcc.target/powerpc/bool2-p5.c

20488

===================================================================

20489

--- a/src/gcc/testsuite/gcc.target/powerpc/bool2-p5.c (.../tags/gcc_4_8_2_release)

20490

+++ b/src/gcc/testsuite/gcc.target/powerpc/bool2-p5.c (.../branches/gcc-4_8-branch)

20491

@@ -0,0 +1,32 @@

20492

+/* { dg-do compile { target { powerpc*-*-* } } } */

20493

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

20494

+/* { dg-require-effective-target powerpc_altivec_ok } */

20495

+/* { dg-options "-O2 -mcpu=power5 -mabi=altivec -mno-altivec -mno-vsx" } */

20496

+/* { dg-final { scan-assembler "\[ \t\]and " } } */

20497

+/* { dg-final { scan-assembler "\[ \t\]or " } } */

20498

+/* { dg-final { scan-assembler "\[ \t\]xor " } } */

20499

+/* { dg-final { scan-assembler "\[ \t\]nor " } } */

20500

+/* { dg-final { scan-assembler "\[ \t\]andc " } } */

20501

+/* { dg-final { scan-assembler "\[ \t\]eqv " } } */

20502

+/* { dg-final { scan-assembler "\[ \t\]orc " } } */

20503

+/* { dg-final { scan-assembler "\[ \t\]nand " } } */

20504

+/* { dg-final { scan-assembler-not "\[ \t\]vand " } } */

20505

+/* { dg-final { scan-assembler-not "\[ \t\]vandc " } } */

20506

+/* { dg-final { scan-assembler-not "\[ \t\]vor " } } */

20507

+/* { dg-final { scan-assembler-not "\[ \t\]vxor " } } */

20508

+/* { dg-final { scan-assembler-not "\[ \t\]vnor " } } */

20509

+/* { dg-final { scan-assembler-not "\[ \t\]xxland " } } */

20510

+/* { dg-final { scan-assembler-not "\[ \t\]xxlor " } } */

20511

+/* { dg-final { scan-assembler-not "\[ \t\]xxlxor " } } */

20512

+/* { dg-final { scan-assembler-not "\[ \t\]xxlnor " } } */

20513

+/* { dg-final { scan-assembler-not "\[ \t\]xxlandc " } } */

20514

+/* { dg-final { scan-assembler-not "\[ \t\]xxleqv " } } */

20515

+/* { dg-final { scan-assembler-not "\[ \t\]xxlorc " } } */

20516

+/* { dg-final { scan-assembler-not "\[ \t\]xxlnand " } } */

20517

+

20518

+#ifndef TYPE

20519

+typedef int v4si __attribute__ ((vector_size (16)));

20520

+#define TYPE v4si

20521

+#endif

20522

+

20523

+#include "bool2.h"

20524

Index: gcc/testsuite/gcc.target/powerpc/fusion.c

20525

===================================================================

20526

--- a/src/gcc/testsuite/gcc.target/powerpc/fusion.c (.../tags/gcc_4_8_2_release)

20527

+++ b/src/gcc/testsuite/gcc.target/powerpc/fusion.c (.../branches/gcc-4_8-branch)

20528

@@ -0,0 +1,24 @@

20529

+/* { dg-do compile { target { powerpc*-*-* } } } */

20530

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

20531

+/* { dg-skip-if "" { powerpc*le-*-* } { "*" } { "" } } */

20532

+/* { dg-require-effective-target powerpc_p8vector_ok } */

20533

+/* { dg-options "-mcpu=power7 -mtune=power8 -O3" } */

20534

+

20535

+#define LARGE 0x12345

20536

+

20537

+int fusion_uchar (unsigned char *p){ return p[LARGE]; }

20538

+int fusion_schar (signed char *p){ return p[LARGE]; }

20539

+int fusion_ushort (unsigned short *p){ return p[LARGE]; }

20540

+int fusion_short (short *p){ return p[LARGE]; }

20541

+int fusion_int (int *p){ return p[LARGE]; }

20542

+unsigned fusion_uns (unsigned *p){ return p[LARGE]; }

20543

+

20544

+vector double fusion_vector (vector double *p) { return p[2]; }

20545

+

20546

+/* { dg-final { scan-assembler-times "gpr load fusion" 6 } } */

20547

+/* { dg-final { scan-assembler-times "vector load fusion" 1 } } */

20548

+/* { dg-final { scan-assembler-times "lbz" 2 } } */

20549

+/* { dg-final { scan-assembler-times "extsb" 1 } } */

20550

+/* { dg-final { scan-assembler-times "lhz" 2 } } */

20551

+/* { dg-final { scan-assembler-times "extsh" 1 } } */

20552

+/* { dg-final { scan-assembler-times "lwz" 2 } } */

20553

Index: gcc/testsuite/gcc.target/powerpc/ppc64-abi-2.c

20554

===================================================================

20555

--- a/src/gcc/testsuite/gcc.target/powerpc/ppc64-abi-2.c (.../tags/gcc_4_8_2_release)

20556

+++ b/src/gcc/testsuite/gcc.target/powerpc/ppc64-abi-2.c (.../branches/gcc-4_8-branch)

20557

@@ -107,8 +107,10 @@

20558

long a1;

20559

long a2;

20560

long a3;

20561

+#if _CALL_ELF != 2

20562

long a4;

20563

long a5;

20564

+#endif

20565

parm_t slot[100];

20566

} stack_frame_t;

20567

20568

@@ -119,6 +121,12 @@

20569

vector int v;

20570

} vector_int_t;

20571

20572

+#ifdef __LITTLE_ENDIAN__

20573

+#define MAKE_SLOT(x, y) ((long)x | ((long)y << 32))

20574

+#else

20575

+#define MAKE_SLOT(x, y) ((long)y | ((long)x << 32))

20576

+#endif

20577

+

20578

/* Paramter passing.

20579

s : gpr 3

20580

v : vpr 2

20581

@@ -226,8 +234,8 @@

20582

sp = __builtin_frame_address(0);

20583

sp = sp->backchain;

20584

20585

- if (sp->slot[2].l != 0x100000002ULL

20586

- || sp->slot[4].l != 0x500000006ULL)

20587

+ if (sp->slot[2].l != MAKE_SLOT (1, 2)

20588

+ || sp->slot[4].l != MAKE_SLOT (5, 6))

20589

abort();

20590

}

20591

20592

@@ -268,8 +276,8 @@

20593

sp = __builtin_frame_address(0);

20594

sp = sp->backchain;

20595

20596

- if (sp->slot[4].l != 0x100000002ULL

20597

- || sp->slot[6].l != 0x500000006ULL)

20598

+ if (sp->slot[4].l != MAKE_SLOT (1, 2)

20599

+ || sp->slot[6].l != MAKE_SLOT (5, 6))

20600

abort();

20601

}

20602

20603

@@ -296,8 +304,8 @@

20604

sp = __builtin_frame_address(0);

20605

sp = sp->backchain;

20606

20607

- if (sp->slot[4].l != 0x100000002ULL

20608

- || sp->slot[6].l != 0x500000006ULL)

20609

+ if (sp->slot[4].l != MAKE_SLOT (1, 2)

20610

+ || sp->slot[6].l != MAKE_SLOT (5, 6))

20611

abort();

20612

}

20613

20614

Index: gcc/testsuite/gcc.target/powerpc/direct-move-long1.c

20615

===================================================================

20616

--- a/src/gcc/testsuite/gcc.target/powerpc/direct-move-long1.c (.../tags/gcc_4_8_2_release)

20617

+++ b/src/gcc/testsuite/gcc.target/powerpc/direct-move-long1.c (.../branches/gcc-4_8-branch)

20618

@@ -0,0 +1,16 @@

20619

+/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */

20620

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

20621

+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */

20622

+/* { dg-require-effective-target powerpc_p8vector_ok } */

20623

+/* { dg-options "-mcpu=power8 -O2" } */

20624

+/* { dg-final { scan-assembler "mtvsrd" } } */

20625

+/* { dg-final { scan-assembler "mfvsrd" } } */

20626

+

20627

+/* Check code generation for direct move for long types. */

20628

+

20629

+#define TYPE long

20630

+#define IS_INT 1

20631

+#define NO_ALTIVEC 1

20632

+#define VSX_REG_ATTR "d"

20633

+

20634

+#include "direct-move.h"

20635

Index: gcc/testsuite/gcc.target/powerpc/direct-move-double2.c

20636

===================================================================

20637

--- a/src/gcc/testsuite/gcc.target/powerpc/direct-move-double2.c (.../tags/gcc_4_8_2_release)

20638

+++ b/src/gcc/testsuite/gcc.target/powerpc/direct-move-double2.c (.../branches/gcc-4_8-branch)

20639

@@ -0,0 +1,15 @@

20640

+/* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */

20641

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

20642

+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */

20643

+/* { dg-require-effective-target p8vector_hw } */

20644

+/* { dg-options "-mcpu=power8 -O2" } */

20645

+

20646

+/* Check whether we get the right bits for direct move at runtime. */

20647

+

20648

+#define TYPE double

20649

+#define IS_FLOAT 1

20650

+#define NO_ALTIVEC 1

20651

+#define DO_MAIN

20652

+#define VSX_REG_ATTR "ws"

20653

+

20654

+#include "direct-move.h"

20655

Index: gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c

20656

===================================================================

20657

--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c (.../tags/gcc_4_8_2_release)

20658

+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c (.../branches/gcc-4_8-branch)

20659

@@ -0,0 +1,32 @@

20660

+/* { dg-do compile { target { powerpc*-*-* } } } */

20661

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

20662

+/* { dg-require-effective-target powerpc_p8vector_ok } */

20663

+/* { dg-options "-mcpu=power8 -O2" } */

20664

+

20665

+#include <altivec.h>

20666

+

20667

+typedef vector int v_sign;

20668

+typedef vector unsigned int v_uns;

20669

+

20670

+v_sign even_sign (v_sign a, v_sign b)

20671

+{

20672

+ return vec_vmrgew (a, b);

20673

+}

20674

+

20675

+v_uns even_uns (v_uns a, v_uns b)

20676

+{

20677

+ return vec_vmrgew (a, b);

20678

+}

20679

+

20680

+v_sign odd_sign (v_sign a, v_sign b)

20681

+{

20682

+ return vec_vmrgow (a, b);

20683

+}

20684

+

20685

+v_uns odd_uns (v_uns a, v_uns b)

20686

+{

20687

+ return vec_vmrgow (a, b);

20688

+}

20689

+

20690

+/* { dg-final { scan-assembler-times "vmrgew" 2 } } */

20691

+/* { dg-final { scan-assembler-times "vmrgow" 2 } } */

20692

Index: gcc/testsuite/gcc.target/powerpc/bool2.h

20693

===================================================================

20694

--- a/src/gcc/testsuite/gcc.target/powerpc/bool2.h (.../tags/gcc_4_8_2_release)

20695

+++ b/src/gcc/testsuite/gcc.target/powerpc/bool2.h (.../branches/gcc-4_8-branch)

20696

@@ -0,0 +1,29 @@

20697

+/* Test various logical operations. */

20698

+

20699

+TYPE arg1 (TYPE p, TYPE q) { return p & q; } /* AND */

20700

+TYPE arg2 (TYPE p, TYPE q) { return p | q; } /* OR */

20701

+TYPE arg3 (TYPE p, TYPE q) { return p ^ q; } /* XOR */

20702

+TYPE arg4 (TYPE p) { return ~ p; } /* NOR */

20703

+TYPE arg5 (TYPE p, TYPE q) { return ~(p & q); } /* NAND */

20704

+TYPE arg6 (TYPE p, TYPE q) { return ~(p | q); } /* NOR */

20705

+TYPE arg7 (TYPE p, TYPE q) { return ~(p ^ q); } /* EQV */

20706

+TYPE arg8 (TYPE p, TYPE q) { return (~p) & q; } /* ANDC */

20707

+TYPE arg9 (TYPE p, TYPE q) { return (~p) | q; } /* ORC */

20708

+TYPE arg10(TYPE p, TYPE q) { return (~p) ^ q; } /* EQV */

20709

+TYPE arg11(TYPE p, TYPE q) { return p & (~q); } /* ANDC */

20710

+TYPE arg12(TYPE p, TYPE q) { return p | (~q); } /* ORC */

20711

+TYPE arg13(TYPE p, TYPE q) { return p ^ (~q); } /* EQV */

20712

+

20713

+void ptr1 (TYPE *p) { p[0] = p[1] & p[2]; } /* AND */

20714

+void ptr2 (TYPE *p) { p[0] = p[1] | p[2]; } /* OR */

20715

+void ptr3 (TYPE *p) { p[0] = p[1] ^ p[2]; } /* XOR */

20716

+void ptr4 (TYPE *p) { p[0] = ~p[1]; } /* NOR */

20717

+void ptr5 (TYPE *p) { p[0] = ~(p[1] & p[2]); } /* NAND */

20718

+void ptr6 (TYPE *p) { p[0] = ~(p[1] | p[2]); } /* NOR */

20719

+void ptr7 (TYPE *p) { p[0] = ~(p[1] ^ p[2]); } /* EQV */

20720

+void ptr8 (TYPE *p) { p[0] = ~(p[1]) & p[2]; } /* ANDC */

20721

+void ptr9 (TYPE *p) { p[0] = (~p[1]) | p[2]; } /* ORC */

20722

+void ptr10(TYPE *p) { p[0] = (~p[1]) ^ p[2]; } /* EQV */

20723

+void ptr11(TYPE *p) { p[0] = p[1] & (~p[2]); } /* ANDC */

20724

+void ptr12(TYPE *p) { p[0] = p[1] | (~p[2]); } /* ORC */

20725

+void ptr13(TYPE *p) { p[0] = p[1] ^ (~p[2]); } /* EQV */

20726

Index: gcc/testsuite/gcc.target/powerpc/pr48258-1.c

20727

===================================================================

20728

--- a/src/gcc/testsuite/gcc.target/powerpc/pr48258-1.c (.../tags/gcc_4_8_2_release)

20729

+++ b/src/gcc/testsuite/gcc.target/powerpc/pr48258-1.c (.../branches/gcc-4_8-branch)

20730

@@ -1,5 +1,6 @@

20731

/* { dg-do compile } */

20732

/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

20733

+/* { dg-skip-if "" { powerpc*le-*-* } { "*" } { "" } } */

20734

/* { dg-require-effective-target powerpc_vsx_ok } */

20735

/* { dg-options "-O3 -mcpu=power7 -mabi=altivec -ffast-math -fno-unroll-loops" } */

20736

/* { dg-final { scan-assembler-times "xvaddsp" 3 } } */

20737

Index: gcc/testsuite/gcc.target/powerpc/quad-atomic.c

20738

===================================================================

20739

--- a/src/gcc/testsuite/gcc.target/powerpc/quad-atomic.c (.../tags/gcc_4_8_2_release)

20740

+++ b/src/gcc/testsuite/gcc.target/powerpc/quad-atomic.c (.../branches/gcc-4_8-branch)

20741

@@ -0,0 +1,67 @@

20742

+/* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */

20743

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

20744

+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */

20745

+/* { dg-require-effective-target p8vector_hw } */

20746

+/* { dg-options "-mcpu=power8 -O2" } */

20747

+

20748

+/* Test whether we get the right bits for quad word atomic instructions. */

20749

+#include <stdlib.h>

20750

+

20751

+static __int128_t quad_fetch_and (__int128_t *, __int128_t value) __attribute__((__noinline__));

20752

+static __int128_t quad_fetch_or (__int128_t *, __int128_t value) __attribute__((__noinline__));

20753

+static __int128_t quad_fetch_add (__int128_t *, __int128_t value) __attribute__((__noinline__));

20754

+

20755

+static __int128_t

20756

+quad_fetch_and (__int128_t *ptr, __int128_t value)

20757

+{

20758

+ return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE);

20759

+}

20760

+

20761

+static __int128_t

20762

+quad_fetch_or (__int128_t *ptr, __int128_t value)

20763

+{

20764

+ return __atomic_fetch_or (ptr, value, __ATOMIC_ACQUIRE);

20765

+}

20766

+

20767

+static __int128_t

20768

+quad_fetch_add (__int128_t *ptr, __int128_t value)

20769

+{

20770

+ return __atomic_fetch_add (ptr, value, __ATOMIC_ACQUIRE);

20771

+}

20772

+

20773

+int

20774

+main (void)

20775

+{

20776

+ __int128_t result;

20777

+ __int128_t value;

20778

+ __int128_t and_input = ((((__int128_t) 0x1234567890abcdefULL) << 64) | ((__int128_t) 0xfedcba0987654321ULL));

20779

+ __int128_t and_value = ((((__int128_t) 0xfffffffffffffff0ULL) << 64) | ((__int128_t) 0xfffffffffffffff0ULL));

20780

+ __int128_t and_exp = ((((__int128_t) 0x1234567890abcde0ULL) << 64) | ((__int128_t) 0xfedcba0987654320ULL));

20781

+

20782

+ __int128_t or_input = ((((__int128_t) 0x1234567890abcdefULL) << 64) | ((__int128_t) 0xfedcba0987654321ULL));

20783

+ __int128_t or_value = ((((__int128_t) 0x0000000000000010ULL) << 64) | ((__int128_t) 0x000000000000000eULL));

20784

+ __int128_t or_exp = ((((__int128_t) 0x1234567890abcdffULL) << 64) | ((__int128_t) 0xfedcba098765432fULL));

20785

+

20786

+ __int128_t add_input = ((((__int128_t) 0x1234567890abcdefULL) << 64) | ((__int128_t) 0xfedcba0987654321ULL));

20787

+ __int128_t add_value = ((((__int128_t) 0x0000000001000000ULL) << 64) | ((__int128_t) 0x0000001000000000ULL));

20788

+ __int128_t add_exp = ((((__int128_t) 0x1234567891abcdefULL) << 64) | ((__int128_t) 0xfedcba1987654321ULL));

20789

+

20790

+

20791

+ value = and_input;

20792

+ result = quad_fetch_and (&value, and_value);

20793

+ if (result != and_input || value != and_exp)

20794

+ abort ();

20795

+

20796

+ value = or_input;

20797

+ result = quad_fetch_or (&value, or_value);

20798

+ if (result != or_input || value != or_exp)

20799

+ abort ();

20800

+

20801

+ value = add_input;

20802

+ result = quad_fetch_add (&value, add_value);

20803

+ if (result != add_input || value != add_exp)

20804

+ abort ();

20805

+

20806

+ return 0;

20807

+}

20808

+

20809

Index: gcc/testsuite/gcc.target/powerpc/ti_math1.c

20810

===================================================================

20811

--- a/src/gcc/testsuite/gcc.target/powerpc/ti_math1.c (.../tags/gcc_4_8_2_release)

20812

+++ b/src/gcc/testsuite/gcc.target/powerpc/ti_math1.c (.../branches/gcc-4_8-branch)

20813

@@ -0,0 +1,20 @@

20814

+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */

20815

+/* { dg-options "-O2" } */

20816

+/* { dg-final { scan-assembler-times "addc" 1 } } */

20817

+/* { dg-final { scan-assembler-times "adde" 1 } } */

20818

+/* { dg-final { scan-assembler-times "subfc" 1 } } */

20819

+/* { dg-final { scan-assembler-times "subfe" 1 } } */

20820

+/* { dg-final { scan-assembler-not "subf " } } */

20821

+

20822

+__int128

20823

+add_128 (__int128 *ptr, __int128 val)

20824

+{

20825

+ return (*ptr + val);

20826

+}

20827

+

20828

+__int128

20829

+sub_128 (__int128 *ptr, __int128 val)

20830

+{

20831

+ return (*ptr - val);

20832

+}

20833

+

20834

Index: gcc/testsuite/gcc.target/powerpc/atomic_load_store-p8.c

20835

===================================================================

20836

--- a/src/gcc/testsuite/gcc.target/powerpc/atomic_load_store-p8.c (.../tags/gcc_4_8_2_release)

20837

+++ b/src/gcc/testsuite/gcc.target/powerpc/atomic_load_store-p8.c (.../branches/gcc-4_8-branch)

20838

@@ -0,0 +1,22 @@

20839

+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */

20840

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

20841

+/* { dg-require-effective-target powerpc_p8vector_ok } */

20842

+/* { dg-options "-mcpu=power8 -O2" } */

20843

+/* { dg-final { scan-assembler-times "lq" 1 } } */

20844

+/* { dg-final { scan-assembler-times "stq" 1 } } */

20845

+/* { dg-final { scan-assembler-not "bl __atomic" } } */

20846

+/* { dg-final { scan-assembler-not "lqarx" } } */

20847

+/* { dg-final { scan-assembler-not "stqcx" } } */

20848

+

20849

+__int128

20850

+atomic_load_128_relaxed (__int128 *ptr)

20851

+{

20852

+ return __atomic_load_n (ptr, __ATOMIC_RELAXED);

20853

+}

20854

+

20855

+void

20856

+atomic_store_128_relaxed (__int128 *ptr, __int128 val)

20857

+{

20858

+ __atomic_store_n (ptr, val, __ATOMIC_RELAXED);

20859

+}

20860

+

20861

Index: gcc/testsuite/gcc.target/powerpc/ppc64-abi-dfp-1.c

20862

===================================================================

20863

--- a/src/gcc/testsuite/gcc.target/powerpc/ppc64-abi-dfp-1.c (.../tags/gcc_4_8_2_release)

20864

+++ b/src/gcc/testsuite/gcc.target/powerpc/ppc64-abi-dfp-1.c (.../branches/gcc-4_8-branch)

20865

@@ -33,15 +33,27 @@

20866

20867

20868

/* Wrapper to save the GPRs and FPRs and then jump to the real function. */

20869

+#if _CALL_ELF != 2

20870

+#define FUNC_START(NAME) \

20871

+ "\t.globl\t" NAME "\n\t" \

20872

+ ".section \".opd\",\"aw\"\n\t" \

20873

+ ".align 3\n" \

20874

+ NAME ":\n\t" \

20875

+ ".quad .L." NAME ",.TOC.@tocbase,0\n\t" \

20876

+ ".text\n\t" \

20877

+ ".type " NAME ", @function\n" \

20878

+ ".L." NAME ":\n\t"

20879

+#else

20880

+#define FUNC_START(NAME) \

20881

+ "\t.globl\t" NAME "\n\t" \

20882

+ ".text\n\t" \

20883

+ NAME ":\n" \

20884

+ "0:\taddis 2,12,(.TOC.-0b)@ha\n\t" \

20885

+ "addi 2,2,(.TOC.-0b)@l\n\t" \

20886

+ ".localentry " NAME ",.-" NAME "\n\t"

20887

+#endif

20888

#define WRAPPER(NAME) \

20889

-__asm__ ("\t.globl\t" #NAME "_asm\n\t" \

20890

- ".section \".opd\",\"aw\"\n\t" \

20891

- ".align 3\n" \

20892

- #NAME "_asm:\n\t" \

20893

- ".quad .L." #NAME "_asm,.TOC.@tocbase,0\n\t" \

20894

- ".text\n\t" \

20895

- ".type " #NAME "_asm, @function\n" \

20896

- ".L." #NAME "_asm:\n\t" \

20897

+__asm__ (FUNC_START (#NAME "_asm") \

20898

"ld 11,gparms@got(2)\n\t" \

20899

"std 3,0(11)\n\t" \

20900

"std 4,8(11)\n\t" \

20901

@@ -75,8 +87,10 @@

20902

long a1;

20903

long a2;

20904

long a3;

20905

+#if _CALL_ELF != 2

20906

long a4;

20907

long a5;

20908

+#endif

20909

unsigned long slot[100];

20910

} stack_frame_t;

20911

20912

Index: gcc/testsuite/gcc.target/powerpc/direct-move-long2.c

20913

===================================================================

20914

--- a/src/gcc/testsuite/gcc.target/powerpc/direct-move-long2.c (.../tags/gcc_4_8_2_release)

20915

+++ b/src/gcc/testsuite/gcc.target/powerpc/direct-move-long2.c (.../branches/gcc-4_8-branch)

20916

@@ -0,0 +1,15 @@

20917

+/* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */

20918

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

20919

+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */

20920

+/* { dg-require-effective-target p8vector_hw } */

20921

+/* { dg-options "-mcpu=power8 -O2" } */

20922

+

20923

+/* Check whether we get the right bits for direct move at runtime. */

20924

+

20925

+#define TYPE long

20926

+#define IS_INT 1

20927

+#define NO_ALTIVEC 1

20928

+#define DO_MAIN

20929

+#define VSX_REG_ATTR "d"

20930

+

20931

+#include "direct-move.h"

20932

Index: gcc/testsuite/gcc.target/powerpc/vsx-float0.c

20933

===================================================================

20934

--- a/src/gcc/testsuite/gcc.target/powerpc/vsx-float0.c (.../tags/gcc_4_8_2_release)

20935

+++ b/src/gcc/testsuite/gcc.target/powerpc/vsx-float0.c (.../branches/gcc-4_8-branch)

20936

@@ -0,0 +1,16 @@

20937

+/* { dg-do compile { target { powerpc*-*-* } } } */

20938

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

20939

+/* { dg-require-effective-target powerpc_vsx_ok } */

20940

+/* { dg-options "-O2 -mcpu=power7" } */

20941

+/* { dg-final { scan-assembler "xxlxor" } } */

20942

+

20943

+/* Test that we generate xxlor to clear a SFmode register. */

20944

+

20945

+float sum (float *p, unsigned long n)

20946

+{

20947

+ float sum = 0.0f; /* generate xxlxor instead of load */

20948

+ while (n-- > 0)

20949

+ sum += *p++;

20950

+

20951

+ return sum;

20952

+}

20953

Index: gcc/testsuite/gcc.target/powerpc/ppc-target-1.c

20954

===================================================================

20955

--- a/src/gcc/testsuite/gcc.target/powerpc/ppc-target-1.c (.../tags/gcc_4_8_2_release)

20956

+++ b/src/gcc/testsuite/gcc.target/powerpc/ppc-target-1.c (.../branches/gcc-4_8-branch)

20957

@@ -5,8 +5,7 @@

20958

/* { dg-final { scan-assembler-times "fabs" 3 } } */

20959

/* { dg-final { scan-assembler-times "fnabs" 3 } } */

20960

/* { dg-final { scan-assembler-times "fsel" 3 } } */

20961

-/* { dg-final { scan-assembler-times "fcpsgn" 3 } } */

20962

-/* { dg-final { scan-assembler-times "xscpsgndp" 1 } } */

20963

+/* { dg-final { scan-assembler-times "fcpsgn\|xscpsgndp" 4 } } */

20964

20965

double normal1 (double, double);

20966

double power5 (double, double) __attribute__((__target__("cpu=power5")));

20967

Index: gcc/testsuite/gcc.target/powerpc/pr60137.c

20968

===================================================================

20969

--- a/src/gcc/testsuite/gcc.target/powerpc/pr60137.c (.../tags/gcc_4_8_2_release)

20970

+++ b/src/gcc/testsuite/gcc.target/powerpc/pr60137.c (.../branches/gcc-4_8-branch)

20971

@@ -0,0 +1,17 @@

20972

+/* { dg-do compile { target { powerpc*-*-* } } } */

20973

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

20974

+/* { dg-require-effective-target powerpc_p8vector_ok } */

20975

+/* { dg-options "-mcpu=power8 -O3 -mno-vsx" } */

20976

+

20977

+/* target/60137, compiler got a 'could not split insn error'. */

20978

+

20979

+extern int target_flags;

20980

+extern char fixed_regs[53];

20981

+extern char call_used_regs[53];

20982

+

20983

+void init_reg_sets_1(void)

20984

+{

20985

+ int i;

20986

+ for (i = 0; i < 53; i++)

20987

+ fixed_regs[i] = call_used_regs[i] = (call_used_regs[i] &((target_flags & 0x02000000) ? 2 : 1)) != 0;

20988

+}

20989

Index: gcc/testsuite/gcc.target/powerpc/bool3.h

20990

===================================================================

20991

--- a/src/gcc/testsuite/gcc.target/powerpc/bool3.h (.../tags/gcc_4_8_2_release)

20992

+++ b/src/gcc/testsuite/gcc.target/powerpc/bool3.h (.../branches/gcc-4_8-branch)

20993

@@ -0,0 +1,186 @@

20994

+/* Test forcing 128-bit logical types into GPR registers. */

20995

+

20996

+#if defined(NO_ASM)

20997

+#define FORCE_REG1(X)

20998

+#define FORCE_REG2(X,Y)

20999

+

21000

+#else

21001

+#if defined(USE_ALTIVEC)

21002

+#define REG_CLASS "+v"

21003

+#define PRINT_REG1 "# altivec reg %0"

21004

+#define PRINT_REG2 "# altivec reg %0, %1"

21005

+

21006

+#elif defined(USE_FPR)

21007

+#define REG_CLASS "+d"

21008

+#define PRINT_REG1 "# fpr reg %0"

21009

+#define PRINT_REG2 "# fpr reg %0, %1"

21010

+

21011

+#elif defined(USE_VSX)

21012

+#define REG_CLASS "+wa"

21013

+#define PRINT_REG1 "# vsx reg %x0"

21014

+#define PRINT_REG2 "# vsx reg %x0, %x1"

21015

+

21016

+#else

21017

+#define REG_CLASS "+r"

21018

+#define PRINT_REG1 "# gpr reg %0"

21019

+#define PRINT_REG2 "# gpr reg %0, %1"

21020

+#endif

21021

+

21022

+#define FORCE_REG1(X) __asm__ (PRINT_REG1 : REG_CLASS (X))

21023

+#define FORCE_REG2(X,Y) __asm__ (PRINT_REG2 : REG_CLASS (X), REG_CLASS (Y))

21024

+#endif

21025

+

21026

+void ptr1 (TYPE *p)

21027

+{

21028

+ TYPE a = p[1];

21029

+ TYPE b = p[2];

21030

+ TYPE c;

21031

+

21032

+ FORCE_REG2 (a, b);

21033

+ c = a & b; /* AND */

21034

+ FORCE_REG1 (c);

21035

+ p[0] = c;

21036

+}

21037

+

21038

+void ptr2 (TYPE *p)

21039

+{

21040

+ TYPE a = p[1];

21041

+ TYPE b = p[2];

21042

+ TYPE c;

21043

+

21044

+ FORCE_REG2 (a, b);

21045

+ c = a | b; /* OR */

21046

+ FORCE_REG1 (c);

21047

+ p[0] = c;

21048

+}

21049

+

21050

+void ptr3 (TYPE *p)

21051

+{

21052

+ TYPE a = p[1];

21053

+ TYPE b = p[2];

21054

+ TYPE c;

21055

+

21056

+ FORCE_REG2 (a, b);

21057

+ c = a ^ b; /* XOR */

21058

+ FORCE_REG1 (c);

21059

+ p[0] = c;

21060

+}

21061

+

21062

+void ptr4 (TYPE *p)

21063

+{

21064

+ TYPE a = p[1];

21065

+ TYPE b;

21066

+

21067

+ FORCE_REG1 (a);

21068

+ b = ~a; /* NOR */

21069

+ FORCE_REG1 (b);

21070

+ p[0] = b;

21071

+}

21072

+

21073

+void ptr5 (TYPE *p)

21074

+{

21075

+ TYPE a = p[1];

21076

+ TYPE b = p[2];

21077

+ TYPE c;

21078

+

21079

+ FORCE_REG2 (a, b);

21080

+ c = ~(a & b); /* NAND */

21081

+ FORCE_REG1 (c);

21082

+ p[0] = c;

21083

+}

21084

+

21085

+void ptr6 (TYPE *p)

21086

+{

21087

+ TYPE a = p[1];

21088

+ TYPE b = p[2];

21089

+ TYPE c;

21090

+

21091

+ FORCE_REG2 (a, b);

21092

+ c = ~(a | b); /* AND */

21093

+ FORCE_REG1 (c);

21094

+ p[0] = c;

21095

+}

21096

+

21097

+void ptr7 (TYPE *p)

21098

+{

21099

+ TYPE a = p[1];

21100

+ TYPE b = p[2];

21101

+ TYPE c;

21102

+

21103

+ FORCE_REG2 (a, b);

21104

+ c = ~(a ^ b); /* EQV */

21105

+ FORCE_REG1 (c);

21106

+ p[0] = c;

21107

+}

21108

+

21109

+void ptr8 (TYPE *p)

21110

+{

21111

+ TYPE a = p[1];

21112

+ TYPE b = p[2];

21113

+ TYPE c;

21114

+

21115

+ FORCE_REG2 (a, b);

21116

+ c = (~a) & b; /* ANDC */

21117

+ FORCE_REG1 (c);

21118

+ p[0] = c;

21119

+}

21120

+

21121

+void ptr9 (TYPE *p)

21122

+{

21123

+ TYPE a = p[1];

21124

+ TYPE b = p[2];

21125

+ TYPE c;

21126

+

21127

+ FORCE_REG2 (a, b);

21128

+ c = (~a) | b; /* ORC */

21129

+ FORCE_REG1 (c);

21130

+ p[0] = c;

21131

+}

21132

+

21133

+void ptr10 (TYPE *p)

21134

+{

21135

+ TYPE a = p[1];

21136

+ TYPE b = p[2];

21137

+ TYPE c;

21138

+

21139

+ FORCE_REG2 (a, b);

21140

+ c = (~a) ^ b; /* EQV */

21141

+ FORCE_REG1 (c);

21142

+ p[0] = c;

21143

+}

21144

+

21145

+void ptr11 (TYPE *p)

21146

+{

21147

+ TYPE a = p[1];

21148

+ TYPE b = p[2];

21149

+ TYPE c;

21150

+

21151

+ FORCE_REG2 (a, b);

21152

+ c = a & (~b); /* ANDC */

21153

+ FORCE_REG1 (c);

21154

+ p[0] = c;

21155

+}

21156

+

21157

+void ptr12 (TYPE *p)

21158

+{

21159

+ TYPE a = p[1];

21160

+ TYPE b = p[2];

21161

+ TYPE c;

21162

+

21163

+ FORCE_REG2 (a, b);

21164

+ c = a | (~b); /* ORC */

21165

+ FORCE_REG1 (c);

21166

+ p[0] = c;

21167

+}

21168

+

21169

+void ptr13 (TYPE *p)

21170

+{

21171

+ TYPE a = p[1];

21172

+ TYPE b = p[2];

21173

+ TYPE c;

21174

+

21175

+ FORCE_REG2 (a, b);

21176

+ c = a ^ (~b); /* AND */

21177

+ FORCE_REG1 (c);

21178

+ p[0] = c;

21179

+}

21180

Index: gcc/testsuite/gcc.target/powerpc/altivec-perm-1.c

21181

===================================================================

21182

--- a/src/gcc/testsuite/gcc.target/powerpc/altivec-perm-1.c (.../tags/gcc_4_8_2_release)

21183

+++ b/src/gcc/testsuite/gcc.target/powerpc/altivec-perm-1.c (.../branches/gcc-4_8-branch)

21184

@@ -19,19 +19,6 @@

21185

return __builtin_shuffle(x, (V){ 4,5,6,7, 4,5,6,7, 4,5,6,7, 4,5,6,7, });

21186

}

21187

21188

-V p2(V x, V y)

21189

-{

21190

- return __builtin_shuffle(x, y,

21191

- (V){ 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 });

21192

-

21193

-}

21194

-

21195

-V p4(V x, V y)

21196

-{

21197

- return __builtin_shuffle(x, y,

21198

- (V){ 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 });

21199

-}

21200

-

21201

V h1(V x, V y)

21202

{

21203

return __builtin_shuffle(x, y,

21204

@@ -72,5 +59,3 @@

21205

/* { dg-final { scan-assembler "vspltb" } } */

21206

/* { dg-final { scan-assembler "vsplth" } } */

21207

/* { dg-final { scan-assembler "vspltw" } } */

21208

-/* { dg-final { scan-assembler "vpkuhum" } } */

21209

-/* { dg-final { scan-assembler "vpkuwum" } } */

21210

Index: gcc/testsuite/gcc.target/powerpc/bool2-p7.c

21211

===================================================================

21212

--- a/src/gcc/testsuite/gcc.target/powerpc/bool2-p7.c (.../tags/gcc_4_8_2_release)

21213

+++ b/src/gcc/testsuite/gcc.target/powerpc/bool2-p7.c (.../branches/gcc-4_8-branch)

21214

@@ -0,0 +1,31 @@

21215

+/* { dg-do compile { target { powerpc*-*-* } } } */

21216

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

21217

+/* { dg-require-effective-target powerpc_vsx_ok } */

21218

+/* { dg-options "-O2 -mcpu=power7" } */

21219

+/* { dg-final { scan-assembler-not "\[ \t\]and " } } */

21220

+/* { dg-final { scan-assembler-not "\[ \t\]or " } } */

21221

+/* { dg-final { scan-assembler-not "\[ \t\]xor " } } */

21222

+/* { dg-final { scan-assembler-not "\[ \t\]nor " } } */

21223

+/* { dg-final { scan-assembler-not "\[ \t\]eqv " } } */

21224

+/* { dg-final { scan-assembler-not "\[ \t\]andc " } } */

21225

+/* { dg-final { scan-assembler-not "\[ \t\]orc " } } */

21226

+/* { dg-final { scan-assembler-not "\[ \t\]nand " } } */

21227

+/* { dg-final { scan-assembler-not "\[ \t\]vand " } } */

21228

+/* { dg-final { scan-assembler-not "\[ \t\]vor " } } */

21229

+/* { dg-final { scan-assembler-not "\[ \t\]vxor " } } */

21230

+/* { dg-final { scan-assembler-not "\[ \t\]vnor " } } */

21231

+/* { dg-final { scan-assembler "\[ \t\]xxland " } } */

21232

+/* { dg-final { scan-assembler "\[ \t\]xxlor " } } */

21233

+/* { dg-final { scan-assembler "\[ \t\]xxlxor " } } */

21234

+/* { dg-final { scan-assembler "\[ \t\]xxlnor " } } */

21235

+/* { dg-final { scan-assembler "\[ \t\]xxlandc " } } */

21236

+/* { dg-final { scan-assembler-not "\[ \t\]xxleqv " } } */

21237

+/* { dg-final { scan-assembler-not "\[ \t\]xxlorc " } } */

21238

+/* { dg-final { scan-assembler-not "\[ \t\]xxlnand " } } */

21239

+

21240

+#ifndef TYPE

21241

+typedef int v4si __attribute__ ((vector_size (16)));

21242

+#define TYPE v4si

21243

+#endif

21244

+

21245

+#include "bool2.h"

21246

Index: gcc/testsuite/gcc.target/powerpc/ti_math2.c

21247

===================================================================

21248

--- a/src/gcc/testsuite/gcc.target/powerpc/ti_math2.c (.../tags/gcc_4_8_2_release)

21249

+++ b/src/gcc/testsuite/gcc.target/powerpc/ti_math2.c (.../branches/gcc-4_8-branch)

21250

@@ -0,0 +1,73 @@

21251

+/* { dg-do run { target { powerpc*-*-* && lp64 } } } */

21252

+/* { dg-options "-O2 -fno-inline" } */

21253

+

21254

+union U {

21255

+ __int128 i128;

21256

+ struct {

21257

+ long l1;

21258

+ long l2;

21259

+ } s;

21260

+};

21261

+

21262

+union U u1,u2;

21263

+

21264

+__int128

21265

+create_128 (long most_sig, long least_sig)

21266

+{

21267

+ union U u;

21268

+

21269

+#if __LITTLE_ENDIAN__

21270

+ u.s.l1 = least_sig;

21271

+ u.s.l2 = most_sig;

21272

+#else

21273

+ u.s.l1 = most_sig;

21274

+ u.s.l2 = least_sig;

21275

+#endif

21276

+ return u.i128;

21277

+}

21278

+

21279

+long most_sig (union U * u)

21280

+{

21281

+#if __LITTLE_ENDIAN__

21282

+ return (*u).s.l2;

21283

+#else

21284

+ return (*u).s.l1;

21285

+#endif

21286

+}

21287

+

21288

+long least_sig (union U * u)

21289

+{

21290

+#if __LITTLE_ENDIAN__

21291

+ return (*u).s.l1;

21292

+#else

21293

+ return (*u).s.l2;

21294

+#endif

21295

+}

21296

+

21297

+__int128

21298

+add_128 (__int128 *ptr, __int128 val)

21299

+{

21300

+ return (*ptr + val);

21301

+}

21302

+

21303

+__int128

21304

+sub_128 (__int128 *ptr, __int128 val)

21305

+{

21306

+ return (*ptr - val);

21307

+}

21308

+

21309

+int

21310

+main (void)

21311

+{

21312

+ /* Do a simple add/sub to make sure carry is happening between the dwords

21313

+ and that dwords are in correct endian order. */

21314

+ u1.i128 = create_128 (1, -1);

21315

+ u2.i128 = add_128 (&u1.i128, 1);

21316

+ if ((most_sig (&u2) != 2) || (least_sig (&u2) != 0))

21317

+ __builtin_abort ();

21318

+ u2.i128 = sub_128 (&u2.i128, 1);

21319

+ if ((most_sig (&u2) != 1) || (least_sig (&u2) != -1))

21320

+ __builtin_abort ();

21321

+ return 0;

21322

+}

21323

+

21324

Index: gcc/testsuite/gcc.target/microblaze/others/mem_reload.c

21325

===================================================================

21326

--- a/src/gcc/testsuite/gcc.target/microblaze/others/mem_reload.c (.../tags/gcc_4_8_2_release)

21327

+++ b/src/gcc/testsuite/gcc.target/microblaze/others/mem_reload.c (.../branches/gcc-4_8-branch)

21328

@@ -0,0 +1,74 @@

21329

+/* { dg-options "-O2 -fPIC" } */

21330

+

21331

+typedef struct test_struct

21332

+{

21333

+ unsigned long long h[8];

21334

+ unsigned long long Nl,Nh;

21335

+ union {

21336

+ unsigned long long d[16];

21337

+ unsigned char p[(16*8)];

21338

+ } u;

21339

+ unsigned int num,md_len;

21340

+} TEST_STRUCT;

21341

+

21342

+static const unsigned long long K512[12] = {

21343

+ 0x428a2f98d728ae22,0x7137449123ef65cd,

21344

+ 0xb5c0fbcfec4d3b2f,0xe9b5dba58189dbbc,

21345

+ 0x3956c25bf348b538,0x59f111f1b605d019,

21346

+ 0x923f82a4af194f9b,0xab1c5ed5da6d8118,

21347

+ 0xd807aa98a3030242,0x12835b0145706fbe,

21348

+ 0x243185be4ee4b28c,0x550c7dc3d5ffb4e2};

21349

+

21350

+#define ROTR(x,s) (((x)>>s) | (x)<<(64-s))

21351

+#define Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39))

21352

+#define Sigma1(x) (ROTR((x),14) ^ ROTR((x),18) ^ ROTR((x),41))

21353

+#define Ch(x,y,z) (((x) & (y)) ^ ((~(x)) & (z)))

21354

+#define Maj(x,y,z) (((x) & (y)) ^ ((x) & (z)) ^ ((y) & (z)))

21355

+

21356

+#define ROUND_00_15(i,a,b,c,d,e,f,g,h) do { \

21357

+ T1 += h + Sigma1(e) + Ch(e,f,g) + K512[i]; \

21358

+ h = Sigma0(a) + Maj(a,b,c); \

21359

+ d += T1; h += T1; } while (0)

21360

+

21361

+#define ROUND_16_80(i,a,b,c,d,e,f,g,h,X) do { \

21362

+ T1 = X[(i)&0x0f] += s0 + s1 + X[(i+9)&0x0f]; \

21363

+ ROUND_00_15(i,a,b,c,d,e,f,g,h); } while (0)

21364

+

21365

+static void testfunc1 (TEST_STRUCT *ctx, const void *in, unsigned int num)

21366

+{

21367

+ const unsigned long long *W=in;

21368

+ unsigned long long a,b,c,d,e,f,g,h,s0,s1,T1;

21369

+ unsigned long long X[16];

21370

+ int i;

21371

+

21372

+ while (num--) {

21373

+

21374

+ T1 = X[0] = W[0]; ROUND_00_15(0,a,b,c,d,e,f,g,h);

21375

+ T1 = X[1] = W[1]; ROUND_00_15(1,h,a,b,c,d,e,f,g);

21376

+ T1 = X[2] = W[2]; ROUND_00_15(2,g,h,a,b,c,d,e,f);

21377

+ T1 = X[3] = W[3]; ROUND_00_15(3,f,g,h,a,b,c,d,e);

21378

+ T1 = X[4] = W[4]; ROUND_00_15(4,e,f,g,h,a,b,c,d);

21379

+ T1 = X[5] = W[5]; ROUND_00_15(5,d,e,f,g,h,a,b,c);

21380

+ T1 = X[6] = W[6]; ROUND_00_15(6,c,d,e,f,g,h,a,b);

21381

+ T1 = X[7] = W[7]; ROUND_00_15(7,b,c,d,e,f,g,h,a);

21382

+ T1 = X[8] = W[8]; ROUND_00_15(8,a,b,c,d,e,f,g,h);

21383

+ T1 = X[9] = W[9]; ROUND_00_15(9,h,a,b,c,d,e,f,g);

21384

+

21385

+ for (i=16;i<80;i+=8)

21386

+ {

21387

+ ROUND_16_80(i+0,a,b,c,d,e,f,g,h,X);

21388

+ }

21389

+

21390

+ ctx->h[4] += e; ctx->h[5] += f; ctx->h[6] += g; ctx->h[7] += h;

21391

+ }

21392

+}

21393

+

21394

+int testfunc2 (TEST_STRUCT *c, const void *_data, unsigned int len)

21395

+{

21396

+ const unsigned char *data=(const unsigned char *)_data;

21397

+

21398

+ unsigned char *p=(unsigned char *)c->u.p;

21399

+

21400

+ testfunc1 (c,p,0);

21401

+ testfunc1 (c,data,len/sizeof(c->u));

21402

+}

21403

Index: gcc/testsuite/gcc.target/microblaze/others/builtin-trap.c

21404

===================================================================

21405

--- a/src/gcc/testsuite/gcc.target/microblaze/others/builtin-trap.c (.../tags/gcc_4_8_2_release)

21406

+++ b/src/gcc/testsuite/gcc.target/microblaze/others/builtin-trap.c (.../branches/gcc-4_8-branch)

21407

@@ -0,0 +1,8 @@

21408

+/* { dg-do compile } */

21409

+

21410

+void trap ()

21411

+{

21412

+ __builtin_trap ();

21413

+}

21414

+

21415

+/* { dg-final { scan-assembler "brki\tr0,-1" } } */

21416

\ No newline at end of file

21417

Index: gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c

21418

===================================================================

21419

--- a/src/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c (.../tags/gcc_4_8_2_release)

21420

+++ b/src/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c (.../branches/gcc-4_8-branch)

21421

@@ -0,0 +1,9 @@

21422

+/* { dg-options "-O3 -mcpu=v6.00.a -mhard-float" } */

21423

+

21424

+void float_func(float f1, float f2, float f3)

21425

+{

21426

+ /* { dg-final { scan-assembler "fcmp\.eq\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */

21427

+ /* { dg-final { scan-assembler "fcmp\.le\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */

21428

+ if(f1==f2 && f1<=f3)

21429

+ print ("f1 eq f2 && f1 le f3");

21430

+}

21431

Index: gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c

21432

===================================================================

21433

--- a/src/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c (.../tags/gcc_4_8_2_release)

21434

+++ b/src/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c (.../branches/gcc-4_8-branch)

21435

@@ -1,8 +1,14 @@

21436

/* { dg-do compile } */

21437

/* { dg-options "-O2" } */

21438

21439

-#include "../../../config/aarch64/arm_neon.h"

21440

+#include <arm_neon.h>

21441

21442

+/* Used to force a variable to a SIMD register. */

21443

+#define force_simd(V1) asm volatile ("mov %d0, %1.d[0]" \

21444

+ : "=w"(V1) \

21445

+ : "w"(V1) \

21446

+ : /* No clobbers */);

21447

+

21448

/* { dg-final { scan-assembler-times "\\tadd\\tx\[0-9\]+" 2 } } */

21449

21450

uint64x1_t

21451

@@ -31,7 +37,12 @@

21452

uint64x1_t

21453

test_vceqd_s64 (int64x1_t a, int64x1_t b)

21454

{

21455

- return vceqd_s64 (a, b);

21456

+ uint64x1_t res;

21457

+ force_simd (a);

21458

+ force_simd (b);

21459

+ res = vceqd_s64 (a, b);

21460

+ force_simd (res);

21461

+ return res;

21462

}

21463

21464

/* { dg-final { scan-assembler-times "\\tcmeq\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */

21465

@@ -39,7 +50,11 @@

21466

uint64x1_t

21467

test_vceqzd_s64 (int64x1_t a)

21468

{

21469

- return vceqzd_s64 (a);

21470

+ uint64x1_t res;

21471

+ force_simd (a);

21472

+ res = vceqzd_s64 (a);

21473

+ force_simd (res);

21474

+ return res;

21475

}

21476

21477

/* { dg-final { scan-assembler-times "\\tcmge\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 2 } } */

21478

@@ -47,21 +62,36 @@

21479

uint64x1_t

21480

test_vcged_s64 (int64x1_t a, int64x1_t b)

21481

{

21482

- return vcged_s64 (a, b);

21483

+ uint64x1_t res;

21484

+ force_simd (a);

21485

+ force_simd (b);

21486

+ res = vcged_s64 (a, b);

21487

+ force_simd (res);

21488

+ return res;

21489

}

21490

21491

uint64x1_t

21492

test_vcled_s64 (int64x1_t a, int64x1_t b)

21493

{

21494

- return vcled_s64 (a, b);

21495

+ uint64x1_t res;

21496

+ force_simd (a);

21497

+ force_simd (b);

21498

+ res = vcled_s64 (a, b);

21499

+ force_simd (res);

21500

+ return res;

21501

}

21502

21503

-/* { dg-final { scan-assembler-times "\\tcmge\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */

21504

+/* Idiom recognition will cause this testcase not to generate

21505

+ the expected cmge instruction, so do not check for it. */

21506

21507

uint64x1_t

21508

test_vcgezd_s64 (int64x1_t a)

21509

{

21510

- return vcgezd_s64 (a);

21511

+ uint64x1_t res;

21512

+ force_simd (a);

21513

+ res = vcgezd_s64 (a);

21514

+ force_simd (res);

21515

+ return res;

21516

}

21517

21518

/* { dg-final { scan-assembler-times "\\tcmhs\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */

21519

@@ -69,7 +99,12 @@

21520

uint64x1_t

21521

test_vcged_u64 (uint64x1_t a, uint64x1_t b)

21522

{

21523

- return vcged_u64 (a, b);

21524

+ uint64x1_t res;

21525

+ force_simd (a);

21526

+ force_simd (b);

21527

+ res = vcged_u64 (a, b);

21528

+ force_simd (res);

21529

+ return res;

21530

}

21531

21532

/* { dg-final { scan-assembler-times "\\tcmgt\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 2 } } */

21533

@@ -77,13 +112,23 @@

21534

uint64x1_t

21535

test_vcgtd_s64 (int64x1_t a, int64x1_t b)

21536

{

21537

- return vcgtd_s64 (a, b);

21538

+ uint64x1_t res;

21539

+ force_simd (a);

21540

+ force_simd (b);

21541

+ res = vcgtd_s64 (a, b);

21542

+ force_simd (res);

21543

+ return res;

21544

}

21545

21546

uint64x1_t

21547

test_vcltd_s64 (int64x1_t a, int64x1_t b)

21548

{

21549

- return vcltd_s64 (a, b);

21550

+ uint64x1_t res;

21551

+ force_simd (a);

21552

+ force_simd (b);

21553

+ res = vcltd_s64 (a, b);

21554

+ force_simd (res);

21555

+ return res;

21556

}

21557

21558

/* { dg-final { scan-assembler-times "\\tcmgt\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */

21559

@@ -91,7 +136,11 @@

21560

uint64x1_t

21561

test_vcgtzd_s64 (int64x1_t a)

21562

{

21563

- return vcgtzd_s64 (a);

21564

+ uint64x1_t res;

21565

+ force_simd (a);

21566

+ res = vcgtzd_s64 (a);

21567

+ force_simd (res);

21568

+ return res;

21569

}

21570

21571

/* { dg-final { scan-assembler-times "\\tcmhi\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */

21572

@@ -99,7 +148,12 @@

21573

uint64x1_t

21574

test_vcgtd_u64 (uint64x1_t a, uint64x1_t b)

21575

{

21576

- return vcgtd_u64 (a, b);

21577

+ uint64x1_t res;

21578

+ force_simd (a);

21579

+ force_simd (b);

21580

+ res = vcgtd_u64 (a, b);

21581

+ force_simd (res);

21582

+ return res;

21583

}

21584

21585

/* { dg-final { scan-assembler-times "\\tcmle\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */

21586

@@ -107,15 +161,24 @@

21587

uint64x1_t

21588

test_vclezd_s64 (int64x1_t a)

21589

{

21590

- return vclezd_s64 (a);

21591

+ uint64x1_t res;

21592

+ force_simd (a);

21593

+ res = vclezd_s64 (a);

21594

+ force_simd (res);

21595

+ return res;

21596

}

21597

21598

-/* { dg-final { scan-assembler-times "\\tcmlt\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */

21599

+/* Idiom recognition will cause this testcase not to generate

21600

+ the expected cmlt instruction, so do not check for it. */

21601

21602

uint64x1_t

21603

test_vcltzd_s64 (int64x1_t a)

21604

{

21605

- return vcltzd_s64 (a);

21606

+ uint64x1_t res;

21607

+ force_simd (a);

21608

+ res = vcltzd_s64 (a);

21609

+ force_simd (res);

21610

+ return res;

21611

}

21612

21613

/* { dg-final { scan-assembler-times "\\tdup\\tb\[0-9\]+, v\[0-9\]+\.b" 2 } } */

21614

@@ -179,13 +242,23 @@

21615

int64x1_t

21616

test_vtst_s64 (int64x1_t a, int64x1_t b)

21617

{

21618

- return vtstd_s64 (a, b);

21619

+ uint64x1_t res;

21620

+ force_simd (a);

21621

+ force_simd (b);

21622

+ res = vtstd_s64 (a, b);

21623

+ force_simd (res);

21624

+ return res;

21625

}

21626

21627

uint64x1_t

21628

test_vtst_u64 (uint64x1_t a, uint64x1_t b)

21629

{

21630

- return vtstd_u64 (a, b);

21631

+ uint64x1_t res;

21632

+ force_simd (a);

21633

+ force_simd (b);

21634

+ res = vtstd_s64 (a, b);

21635

+ force_simd (res);

21636

+ return res;

21637

}

21638

21639

/* { dg-final { scan-assembler-times "\\taddp\\td\[0-9\]+, v\[0-9\]+\.2d" 1 } } */

21640

@@ -722,8 +795,11 @@

21641

return vrshld_u64 (a, b);

21642

}

21643

21644

-/* { dg-final { scan-assembler-times "\\tasr\\tx\[0-9\]+" 1 } } */

21645

+/* Other intrinsics can generate an asr instruction (vcltzd, vcgezd),

21646

+ so we cannot check scan-assembler-times. */

21647

21648

+/* { dg-final { scan-assembler "\\tasr\\tx\[0-9\]+" } } */

21649

+

21650

int64x1_t

21651

test_vshrd_n_s64 (int64x1_t a)

21652

{

21653

Index: gcc/testsuite/gcc.target/i386/pr59405.c

21654

===================================================================

21655

--- a/src/gcc/testsuite/gcc.target/i386/pr59405.c (.../tags/gcc_4_8_2_release)

21656

+++ b/src/gcc/testsuite/gcc.target/i386/pr59405.c (.../branches/gcc-4_8-branch)

21657

@@ -0,0 +1,24 @@

21658

+/* { dg-do run } */

21659

+/* { dg-options "-mmmx -mfpmath=387" } */

21660

+

21661

+#include "mmx-check.h"

21662

+

21663

+#include <mmintrin.h>

21664

+

21665

+typedef float float32x2_t __attribute__ ((vector_size (8)));

21666

+

21667

+float

21668

+foo32x2_be (float32x2_t x)

21669

+{

21670

+ _mm_empty ();

21671

+ return x[1];

21672

+}

21673

+

21674

+static void

21675

+mmx_test (void)

21676

+{

21677

+ float32x2_t b = { 0.0f, 1.0f };

21678

+

21679

+ if (foo32x2_be (b) != 1.0f)

21680

+ abort ();

21681

+}

21682

Index: gcc/testsuite/gcc.target/i386/pr59794-5.c

21683

===================================================================

21684

--- a/src/gcc/testsuite/gcc.target/i386/pr59794-5.c (.../tags/gcc_4_8_2_release)

21685

+++ b/src/gcc/testsuite/gcc.target/i386/pr59794-5.c (.../branches/gcc-4_8-branch)

21686

@@ -0,0 +1,14 @@

21687

+/* PR target/59794 */

21688

+/* { dg-do compile { target { ia32 } } } */

21689

+/* { dg-options "-O2 -mno-sse" } */

21690

+/* { dg-skip-if "no SSE vector" { *-*-mingw* } } */

21691

+

21692

+typedef int __v4si __attribute__ ((__vector_size__ (16)));

21693

+

21694

+extern __v4si x;

21695

+

21696

+__v4si

21697

+foo (void)

21698

+{ /* { dg-warning "SSE vector return without SSE enabled changes the ABI" } */

21699

+ return x;

21700

+}

21701

Index: gcc/testsuite/gcc.target/i386/avx-vzeroupper-17.c

21702

===================================================================

21703

--- a/src/gcc/testsuite/gcc.target/i386/avx-vzeroupper-17.c (.../tags/gcc_4_8_2_release)

21704

+++ b/src/gcc/testsuite/gcc.target/i386/avx-vzeroupper-17.c (.../branches/gcc-4_8-branch)

21705

@@ -1,5 +1,5 @@

21706

/* { dg-do compile { target lp64 } } */

21707

-/* { dg-options "-O2 -mavx -mabi=ms -mtune=generic -dp" } */

21708

+/* { dg-options "-O2 -mavx -mabi=ms -maccumulate-outgoing-args -dp" } */

21709

21710

typedef float __m256 __attribute__ ((__vector_size__ (32), __may_alias__));

21711

21712

Index: gcc/testsuite/gcc.target/i386/pr54694.c

21713

===================================================================

21714

--- a/src/gcc/testsuite/gcc.target/i386/pr54694.c (.../tags/gcc_4_8_2_release)

21715

+++ b/src/gcc/testsuite/gcc.target/i386/pr54694.c (.../branches/gcc-4_8-branch)

21716

@@ -0,0 +1,11 @@

21717

+/* { dg-do compile } */

21718

+/* { dg-options "-O" } */

21719

+

21720

+register void *hfp __asm__("%ebp"); /* { dg-message "note: for" } */

21721

+

21722

+extern void g(void *);

21723

+

21724

+void f(int x) /* { dg-error "frame pointer required" } */

21725

+{

21726

+ g(__builtin_alloca(x));

21727

+}

21728

Index: gcc/testsuite/gcc.target/i386/pr59470.c

21729

===================================================================

21730

--- a/src/gcc/testsuite/gcc.target/i386/pr59470.c (.../tags/gcc_4_8_2_release)

21731

+++ b/src/gcc/testsuite/gcc.target/i386/pr59470.c (.../branches/gcc-4_8-branch)

21732

@@ -0,0 +1,17 @@

21733

+/* PR middle-end/58956 */

21734

+/* PR middle-end/59470 */

21735

+/* { dg-do run } */

21736

+/* { dg-options "-O2" } */

21737

+

21738

+int a, b, d[1024];

21739

+

21740

+int

21741

+main ()

21742

+{

21743

+ int c = a;

21744

+ asm ("{movl $6, (%2); movl $1, %0|mov dword ptr [%2], 6; mov %0, 1}"

21745

+ : "=r" (d[c]) : "rm" (b), "r" (&a) : "memory");

21746

+ if (d[0] != 1 || d[6] != 0)

21747

+ __builtin_abort ();

21748

+ return 0;

21749

+}

21750

Index: gcc/testsuite/gcc.target/i386/pr59034-1.c

21751

===================================================================

21752

--- a/src/gcc/testsuite/gcc.target/i386/pr59034-1.c (.../tags/gcc_4_8_2_release)

21753

+++ b/src/gcc/testsuite/gcc.target/i386/pr59034-1.c (.../branches/gcc-4_8-branch)

21754

@@ -0,0 +1,10 @@

21755

+/* { dg-do compile { target { ! { ia32 } } } } */

21756

+/* { dg-require-effective-target maybe_x32 } */

21757

+/* { dg-options "-O -mx32 -mtune=corei7 -maddress-mode=short" } */

21758

+

21759

+extern int foo(int, ...);

21760

+int bar(void) {

21761

+ long double l = 1.2345E6;

21762

+ foo(0, l);

21763

+ return 0;

21764

+}

21765

Index: gcc/testsuite/gcc.target/i386/pr58690.c

21766

===================================================================

21767

--- a/src/gcc/testsuite/gcc.target/i386/pr58690.c (.../tags/gcc_4_8_2_release)

21768

+++ b/src/gcc/testsuite/gcc.target/i386/pr58690.c (.../branches/gcc-4_8-branch)

21769

@@ -0,0 +1,14 @@

21770

+/* { dg-do compile { target { ! { ia32 } } } } */

21771

+/* { dg-require-effective-target maybe_x32 } */

21772

+/* { dg-options "-O2 -mx32 -maddress-mode=short" } */

21773

+

21774

+struct gomp_thread

21775

+{

21776

+ char foo[41];

21777

+};

21778

+extern __thread struct gomp_thread gomp_tls_data;

21779

+void

21780

+foo (void)

21781

+{

21782

+ __builtin_memset (&gomp_tls_data, '\0', sizeof (gomp_tls_data));

21783

+}

21784

Index: gcc/testsuite/gcc.target/i386/avx-vmovapd-256-2.c

21785

===================================================================

21786

--- a/src/gcc/testsuite/gcc.target/i386/avx-vmovapd-256-2.c (.../tags/gcc_4_8_2_release)

21787

+++ b/src/gcc/testsuite/gcc.target/i386/avx-vmovapd-256-2.c (.../branches/gcc-4_8-branch)

21788

@@ -15,7 +15,7 @@

21789

avx_test (void)

21790

{

21791

union256d u;

21792

- double e [4] __attribute__ ((aligned (8))) = {0.0};

21793

+ double e [4] __attribute__ ((aligned (32))) = {0.0};

21794

21795

u.x = _mm256_set_pd (39578.467285, 7856.342941, 85632.783567, 47563.234215);

21796

21797

Index: gcc/testsuite/gcc.target/i386/pr9771-1.c

21798

===================================================================

21799

--- a/src/gcc/testsuite/gcc.target/i386/pr9771-1.c (.../tags/gcc_4_8_2_release)

21800

+++ b/src/gcc/testsuite/gcc.target/i386/pr9771-1.c (.../branches/gcc-4_8-branch)

21801

@@ -45,7 +45,17 @@

21802

exit(0);

21803

}

21804

21805

-int main()

21806

+/* main usually performs dynamic realignment of the stack in case

21807

+ _start would fail to properly align the stack, but for dynamic

21808

+ stack realignment we need frame pointer which is incompatible

21809

+ with -ffixed-ebp and the global register var. So, cheat here

21810

+ and hide from the compiler that main is really main. */

21811

+#define ASMNAME(cname) ASMNAME2 (__USER_LABEL_PREFIX__, cname)

21812

+#define ASMNAME2(prefix, cname) STRING (prefix) cname

21813

+#define STRING(x) #x

21814

+int real_main() __asm (ASMNAME ("main"));

21815

+

21816

+int real_main()

21817

{

21818

test();

21819

return 0;

21820

Index: gcc/testsuite/gcc.target/i386/pr60700.c

21821

===================================================================

21822

--- a/src/gcc/testsuite/gcc.target/i386/pr60700.c (.../tags/gcc_4_8_2_release)

21823

+++ b/src/gcc/testsuite/gcc.target/i386/pr60700.c (.../branches/gcc-4_8-branch)

21824

@@ -0,0 +1,59 @@

21825

+/* PR rtl-optimization/60700 */

21826

+/* { dg-do run { target ia32 } } */

21827

+/* { dg-options "-O3 -march=i686" } */

21828

+

21829

+int

21830

+__attribute__((noinline))

21831

+foo (void)

21832

+{

21833

+ return 0;

21834

+}

21835

+

21836

+void *g = (void *)1;

21837

+

21838

+struct st {

21839

+ char data[36]; /* must be greater than 32. */

21840

+};

21841

+

21842

+int

21843

+__attribute__((noinline))

21844

+repro(struct st **out)

21845

+{

21846

+ int status = 0;

21847

+

21848

+ *out = 0;

21849

+

21850

+ status = foo();

21851

+ if (status != 0) {

21852

+ return status;

21853

+ }

21854

+

21855

+ if (0 == g) {

21856

+ status = 999;

21857

+ return status;

21858

+ }

21859

+

21860

+ *out = (struct st *)__builtin_malloc(sizeof(struct st));

21861

+ if (0 == *out) {

21862

+ status = 42;

21863

+ return status;

21864

+ }

21865

+

21866

+ __builtin_memset(*out, 0, sizeof(struct st));

21867

+

21868

+ return status;

21869

+}

21870

+

21871

+int

21872

+main ()

21873

+{

21874

+ struct st *p;

21875

+ int ret = repro (&p);

21876

+ unsigned int i;

21877

+

21878

+ for (i = 0; i < sizeof (p->data)/sizeof (p->data[0]); i++)

21879

+ if (p->data[i] != 0)

21880

+ __builtin_abort ();

21881

+

21882

+ return ret;

21883

+}

21884

Index: gcc/testsuite/gcc.target/i386/pr59794-2.c

21885

===================================================================

21886

--- a/src/gcc/testsuite/gcc.target/i386/pr59794-2.c (.../tags/gcc_4_8_2_release)

21887

+++ b/src/gcc/testsuite/gcc.target/i386/pr59794-2.c (.../branches/gcc-4_8-branch)

21888

@@ -0,0 +1,15 @@

21889

+/* PR target/59794 */

21890

+/* { dg-prune-output "ABI for passing parameters" } */

21891

+/* { dg-options "-O2 -mno-sse" } */

21892

+/* { dg-skip-if "no SSE vector" { *-*-mingw* } } */

21893

+

21894

+typedef double __v2df __attribute__ ((__vector_size__ (16)));

21895

+

21896

+extern __v2df x;

21897

+

21898

+extern void bar (__v2df);

21899

+void

21900

+foo (void)

21901

+{

21902

+ bar (x); /* { dg-message "warning: SSE vector argument without SSE enabled changes the ABI" } */

21903

+}

21904

Index: gcc/testsuite/gcc.target/i386/pr57003.c

21905

===================================================================

21906

--- a/src/gcc/testsuite/gcc.target/i386/pr57003.c (.../tags/gcc_4_8_2_release)

21907

+++ b/src/gcc/testsuite/gcc.target/i386/pr57003.c (.../branches/gcc-4_8-branch)

21908

@@ -1,6 +1,6 @@

21909

/* PR rtl-optimization/57003 */

21910

/* { dg-do run } */

21911

-/* { dg-options "-O2" } */

21912

+/* { dg-options "-O2 -maccumulate-outgoing-args" } */

21913

21914

#define N 2001

21915

unsigned short *b, *c, *d;

21916

Index: gcc/testsuite/gcc.target/i386/pr59929.c

21917

===================================================================

21918

--- a/src/gcc/testsuite/gcc.target/i386/pr59929.c (.../tags/gcc_4_8_2_release)

21919

+++ b/src/gcc/testsuite/gcc.target/i386/pr59929.c (.../branches/gcc-4_8-branch)

21920

@@ -0,0 +1,55 @@

21921

+/* { dg-do run } */

21922

+/* { dg-options "-O0 -mno-accumulate-outgoing-args" } */

21923

+/* { dg-options "-O0 -mno-accumulate-outgoing-args -mx32 -maddress-mode=short" { target x32 } } */

21924

+

21925

+void

21926

+__attribute__ ((noinline))

21927

+test (float x1, float x2, float x3, float x4, float x5, float x6,

21928

+ float x7, float x8, float x9, float x10, float x11, float x12,

21929

+ float x13, float x14, float x15, float x16)

21930

+{

21931

+ if (x1 != 91

21932

+ || x2 != 92

21933

+ || x3 != 93

21934

+ || x4 != 94

21935

+ || x5 != 95

21936

+ || x6 != 96

21937

+ || x7 != 97

21938

+ || x8 != 98

21939

+ || x9 != 99

21940

+ || x10 != 100

21941

+ || x11 != 101

21942

+ || x12 != 102

21943

+ || x13 != 103

21944

+ || x14 != 104

21945

+ || x15 != 105

21946

+ || x16 != 106)

21947

+ __builtin_abort ();

21948

+}

21949

+

21950

+float x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13,

21951

+ x14, x15, x16;

21952

+

21953

+int

21954

+main ()

21955

+{

21956

+ x1 = 91;

21957

+ x2 = 92;

21958

+ x3 = 93;

21959

+ x4 = 94;

21960

+ x5 = 95;

21961

+ x6 = 96;

21962

+ x7 = 97;

21963

+ x8 = 98;

21964

+ x9 = 99;

21965

+ x10 = 100;

21966

+ x11 = 101;

21967

+ x12 = 102;

21968

+ x13 = 103;

21969

+ x14 = 104;

21970

+ x15 = 105;

21971

+ x16 = 106;

21972

+ test (x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13,

21973

+ x14, x15, x16);

21974

+ return 0;

21975

+}

21976

Index: gcc/testsuite/gcc.target/i386/pr59794-6.c

21977

===================================================================

21978

--- a/src/gcc/testsuite/gcc.target/i386/pr59794-6.c (.../tags/gcc_4_8_2_release)

21979

+++ b/src/gcc/testsuite/gcc.target/i386/pr59794-6.c (.../branches/gcc-4_8-branch)

21980

@@ -0,0 +1,14 @@

21981

+/* PR target/59794 */

21982

+/* { dg-do compile { target { ! ia32 } } } */

21983

+/* { dg-options "-O2 -mno-sse" } */

21984

+/* { dg-skip-if "no SSE vector" { *-*-mingw* } } */

21985

+

21986

+typedef int __v4si __attribute__ ((__vector_size__ (16)));

21987

+

21988

+extern __v4si x;

21989

+

21990

+__v4si

21991

+foo (void)

21992

+{ /* { dg-error "SSE register return with SSE disabled" } */

21993

+ return x;

21994

+}

21995

Index: gcc/testsuite/gcc.target/i386/avx-vzeroupper-18.c

21996

===================================================================

21997

--- a/src/gcc/testsuite/gcc.target/i386/avx-vzeroupper-18.c (.../tags/gcc_4_8_2_release)

21998

+++ b/src/gcc/testsuite/gcc.target/i386/avx-vzeroupper-18.c (.../branches/gcc-4_8-branch)

21999

@@ -1,5 +1,5 @@

22000

/* { dg-do compile { target lp64 } } */

22001

-/* { dg-options "-O0 -mavx -mabi=ms -mtune=generic -dp" } */

22002

+/* { dg-options "-O0 -mavx -mabi=ms -maccumulate-outgoing-args -dp" } */

22003

22004

typedef float __m256 __attribute__ ((__vector_size__ (32), __may_alias__));

22005

22006

Index: gcc/testsuite/gcc.target/i386/sse2-movapd-1.c

22007

===================================================================

22008

--- a/src/gcc/testsuite/gcc.target/i386/sse2-movapd-1.c (.../tags/gcc_4_8_2_release)

22009

+++ b/src/gcc/testsuite/gcc.target/i386/sse2-movapd-1.c (.../branches/gcc-4_8-branch)

22010

@@ -25,7 +25,7 @@

22011

TEST (void)

22012

{

22013

union128d u;

22014

- double e[2] __attribute__ ((aligned (8))) = {2134.3343,1234.635654};

22015

+ double e[2] __attribute__ ((aligned (16))) = {2134.3343,1234.635654};

22016

22017

u.x = test (e);

22018

22019

Index: gcc/testsuite/gcc.target/i386/pr59021.c

22020

===================================================================

22021

--- a/src/gcc/testsuite/gcc.target/i386/pr59021.c (.../tags/gcc_4_8_2_release)

22022

+++ b/src/gcc/testsuite/gcc.target/i386/pr59021.c (.../branches/gcc-4_8-branch)

22023

@@ -0,0 +1,23 @@

22024

+/* { dg-do compile } */

22025

+/* { dg-options "-O2 -mavx -mvzeroupper" } */

22026

+

22027

+extern void abort (void);

22028

+

22029

+struct S {

22030

+ int i1;

22031

+ int i2;

22032

+ int i3;

22033

+};

22034

+

22035

+typedef double v4df __attribute__ ((vector_size (32)));

22036

+

22037

+extern int foo (v4df, int i1, int i2, int i3, int i4, int i5, struct S s);

22038

+

22039

+void bar (v4df v, struct S s)

22040

+{

22041

+ int r = foo (v, 1, 2, 3, 4, 5, s);

22042

+ if (r)

22043

+ abort ();

22044

+}

22045

+

22046

+/* { dg-final { scan-assembler-not "vzeroupper" } } */

22047

Index: gcc/testsuite/gcc.target/i386/pr59034-2.c

22048

===================================================================

22049

--- a/src/gcc/testsuite/gcc.target/i386/pr59034-2.c (.../tags/gcc_4_8_2_release)

22050

+++ b/src/gcc/testsuite/gcc.target/i386/pr59034-2.c (.../branches/gcc-4_8-branch)

22051

@@ -0,0 +1,10 @@

22052

+/* { dg-do compile { target { ! { ia32 } } } } */

22053

+/* { dg-require-effective-target maybe_x32 } */

22054

+/* { dg-options "-O -mx32 -mtune=corei7 -maddress-mode=long" } */

22055

+

22056

+extern int foo(int, ...);

22057

+int bar(void) {

22058

+ long double l = 1.2345E6;

22059

+ foo(0, l);

22060

+ return 0;

22061

+}

22062

Index: gcc/testsuite/gcc.target/i386/pr60693.c

22063

===================================================================

22064

--- a/src/gcc/testsuite/gcc.target/i386/pr60693.c (.../tags/gcc_4_8_2_release)

22065

+++ b/src/gcc/testsuite/gcc.target/i386/pr60693.c (.../branches/gcc-4_8-branch)

22066

@@ -0,0 +1,13 @@

22067

+/* PR target/60693 */

22068

+/* { dg-do compile } */

22069

+/* { dg-options "-O0" } */

22070

+

22071

+void bar (char *);

22072

+

22073

+void

22074

+foo (void)

22075

+{

22076

+ char buf[4096];

22077

+ __builtin_memcpy (buf, (void *) 0x8000, 4096);

22078

+ bar (buf);

22079

+}

22080

Index: gcc/testsuite/gcc.target/i386/pr59794-3.c

22081

===================================================================

22082

--- a/src/gcc/testsuite/gcc.target/i386/pr59794-3.c (.../tags/gcc_4_8_2_release)

22083

+++ b/src/gcc/testsuite/gcc.target/i386/pr59794-3.c (.../branches/gcc-4_8-branch)

22084

@@ -0,0 +1,15 @@

22085

+/* PR target/59794 */

22086

+/* { dg-prune-output "ABI for passing parameters" } */

22087

+/* { dg-options "-O2 -mno-avx" } */

22088

+/* { dg-skip-if "no AVX vector" { *-*-mingw* } } */

22089

+

22090

+typedef int __v8si __attribute__ ((__vector_size__ (32)));

22091

+

22092

+extern __v8si x;

22093

+

22094

+extern void bar (__v8si);

22095

+void

22096

+foo (void)

22097

+{

22098

+ bar (x); /* { dg-message "warning: AVX vector argument without AVX enabled changes the ABI" } */

22099

+}

22100

Index: gcc/testsuite/gcc.target/i386/pr59839.c

22101

===================================================================

22102

--- a/src/gcc/testsuite/gcc.target/i386/pr59839.c (.../tags/gcc_4_8_2_release)

22103

+++ b/src/gcc/testsuite/gcc.target/i386/pr59839.c (.../branches/gcc-4_8-branch)

22104

@@ -0,0 +1,12 @@

22105

+/* PR target/59839 */

22106

+/* { dg-do compile } */

22107

+/* { dg-options "-O0 -mavx2" } */

22108

+

22109

+#include <x86intrin.h>

22110

+

22111

+void

22112

+test (const float *x)

22113

+{

22114

+ __m256i i = _mm256_set1_epi32 (1);

22115

+ __m256 d = _mm256_i32gather_ps (x, i, 1);

22116

+}

22117

Index: gcc/testsuite/gcc.target/i386/pr60516.c

22118

===================================================================

22119

--- a/src/gcc/testsuite/gcc.target/i386/pr60516.c (.../tags/gcc_4_8_2_release)

22120

+++ b/src/gcc/testsuite/gcc.target/i386/pr60516.c (.../branches/gcc-4_8-branch)

22121

@@ -0,0 +1,20 @@

22122

+/* PR target/60516 */

22123

+/* { dg-do compile } */

22124

+/* { dg-options "-O2" } */

22125

+

22126

+struct S { char c[65536]; };

22127

+

22128

+__attribute__((ms_abi, thiscall)) void

22129

+foo (void *x, struct S y)

22130

+{

22131

+}

22132

+

22133

+__attribute__((ms_abi, fastcall)) void

22134

+bar (void *x, void *y, struct S z)

22135

+{

22136

+}

22137

+

22138

+__attribute__((ms_abi, stdcall)) void

22139

+baz (struct S x)

22140

+{

22141

+}

22142

Index: gcc/testsuite/gcc.target/i386/xop-frczX.c

22143

===================================================================

22144

--- a/src/gcc/testsuite/gcc.target/i386/xop-frczX.c (.../tags/gcc_4_8_2_release)

22145

+++ b/src/gcc/testsuite/gcc.target/i386/xop-frczX.c (.../branches/gcc-4_8-branch)

22146

@@ -0,0 +1,60 @@

22147

+/* { dg-do run } */

22148

+/* { dg-require-effective-target xop } */

22149

+/* { dg-options "-O2 -mxop" } */

22150

+

22151

+#include "xop-check.h"

22152

+

22153

+#include <x86intrin.h>

22154

+

22155

+void

22156

+check_mm_vmfrcz_sd (__m128d __A, __m128d __B)

22157

+{

22158

+ union128d a, b, c;

22159

+ double d[2];

22160

+

22161

+ a.x = __A;

22162

+ b.x = __B;

22163

+ c.x = _mm_frcz_sd (__A, __B);

22164

+ d[0] = b.a[0] - (int)b.a[0] ;

22165

+ d[1] = a.a[1];

22166

+ if (check_union128d (c, d))

22167

+ abort ();

22168

+}

22169

+

22170

+void

22171

+check_mm_vmfrcz_ss (__m128 __A, __m128 __B)

22172

+{

22173

+ union128 a, b, c;

22174

+ float f[4];

22175

+

22176

+ a.x = __A;

22177

+ b.x = __B;

22178

+ c.x = _mm_frcz_ss (__A, __B);

22179

+ f[0] = b.a[0] - (int)b.a[0] ;

22180

+ f[1] = a.a[1];

22181

+ f[2] = a.a[2];

22182

+ f[3] = a.a[3];

22183

+ if (check_union128 (c, f))

22184

+ abort ();

22185

+}

22186

+

22187

+static void

22188

+xop_test (void)

22189

+{

22190

+ union128 a, b;

22191

+ union128d c,d;

22192

+ int i;

22193

+

22194

+ for (i = 0; i < 4; i++)

22195

+ {

22196

+ a.a[i] = i + 3.5;

22197

+ b.a[i] = i + 7.9;

22198

+ }

22199

+ for (i = 0; i < 2; i++)

22200

+ {

22201

+ c.a[i] = i + 3.5;

22202

+ d.a[i] = i + 7.987654321;

22203

+ }

22204

+ check_mm_vmfrcz_ss (a.x, b.x);

22205

+ check_mm_vmfrcz_sd (c.x, d.x);

22206

+}

22207

Index: gcc/testsuite/gcc.target/i386/pr59794-7.c

22208

===================================================================

22209

--- a/src/gcc/testsuite/gcc.target/i386/pr59794-7.c (.../tags/gcc_4_8_2_release)

22210

+++ b/src/gcc/testsuite/gcc.target/i386/pr59794-7.c (.../branches/gcc-4_8-branch)

22211

@@ -0,0 +1,13 @@

22212

+/* PR target/59794 */

22213

+/* { dg-options "-O2 -mno-avx" } */

22214

+/* { dg-skip-if "no AVX vector" { *-*-mingw* } } */

22215

+

22216

+typedef int __v8si __attribute__ ((__vector_size__ (32)));

22217

+

22218

+extern __v8si x;

22219

+

22220

+__v8si

22221

+foo (void)

22222

+{ /* { dg-warning "AVX vector return without AVX enabled changes the ABI" } */

22223

+ return x;

22224

+}

22225

Index: gcc/testsuite/gcc.target/i386/pr59625.c

22226

===================================================================

22227

--- a/src/gcc/testsuite/gcc.target/i386/pr59625.c (.../tags/gcc_4_8_2_release)

22228

+++ b/src/gcc/testsuite/gcc.target/i386/pr59625.c (.../branches/gcc-4_8-branch)

22229

@@ -0,0 +1,36 @@

22230

+/* PR target/59625 */

22231

+/* { dg-do compile } */

22232

+/* { dg-options "-O2 -mtune=atom" } */

22233

+

22234

+int

22235

+foo (void)

22236

+{

22237

+ asm goto ("" : : : : lab);

22238

+ asm goto ("" : : : : lab);

22239

+ asm goto ("" : : : : lab);

22240

+ asm goto ("" : : : : lab);

22241

+ asm goto ("" : : : : lab);

22242

+ asm goto ("" : : : : lab);

22243

+ asm goto ("" : : : : lab);

22244

+ asm goto ("" : : : : lab);

22245

+ asm goto ("" : : : : lab);

22246

+ asm goto ("" : : : : lab);

22247

+ asm goto ("" : : : : lab);

22248

+ asm goto ("" : : : : lab);

22249

+ asm goto ("" : : : : lab);

22250

+ asm goto ("" : : : : lab);

22251

+ asm goto ("" : : : : lab);

22252

+ asm goto ("" : : : : lab);

22253

+ asm goto ("" : : : : lab);

22254

+ asm goto ("" : : : : lab);

22255

+ asm goto ("" : : : : lab);

22256

+ asm goto ("" : : : : lab);

22257

+ return 0;

22258

+lab:

22259

+ return 1;

22260

+}

22261

+

22262

+/* Verify we don't consider asm goto as a jump for four jumps limit

22263

+ optimization. asm goto doesn't have to contain a jump at all,

22264

+ the branching to labels can happen through different means. */

22265

+/* { dg-final { scan-assembler-not "(p2align\[^\n\r\]*\[\n\r]*\[^\n\r\]*){8}p2align" } } */

22266

Index: gcc/testsuite/gcc.target/i386/sse2-movapd-2.c

22267

===================================================================

22268

--- a/src/gcc/testsuite/gcc.target/i386/sse2-movapd-2.c (.../tags/gcc_4_8_2_release)

22269

+++ b/src/gcc/testsuite/gcc.target/i386/sse2-movapd-2.c (.../branches/gcc-4_8-branch)

22270

@@ -25,7 +25,7 @@

22271

TEST (void)

22272

{

22273

union128d u;

22274

- double e[2] __attribute__ ((aligned (8))) = {0.0};

22275

+ double e[2] __attribute__ ((aligned (16))) = {0.0};

22276

22277

u.x = _mm_set_pd (2134.3343,1234.635654);

22278

22279

Index: gcc/testsuite/gcc.target/i386/sse-5.c

22280

===================================================================

22281

--- a/src/gcc/testsuite/gcc.target/i386/sse-5.c (.../tags/gcc_4_8_2_release)

22282

+++ b/src/gcc/testsuite/gcc.target/i386/sse-5.c (.../branches/gcc-4_8-branch)

22283

@@ -1,6 +1,7 @@

22284

/* { dg-do compile } */

22285

/* { dg-require-effective-target ia32 } */

22286

-/* { dg-options "-Winline -Wno-psabi -O2 -mno-sse" } */

22287

+/* { dg-prune-output "ABI for passing parameters" } */

22288

+/* { dg-options "-Winline -O2 -mno-sse" } */

22289

22290

typedef double v2df __attribute__ ((vector_size (16)));

22291

v2df p;

22292

Index: gcc/testsuite/gcc.target/i386/pr39162.c

22293

===================================================================

22294

--- a/src/gcc/testsuite/gcc.target/i386/pr39162.c (.../tags/gcc_4_8_2_release)

22295

+++ b/src/gcc/testsuite/gcc.target/i386/pr39162.c (.../branches/gcc-4_8-branch)

22296

@@ -1,11 +1,14 @@

22297

/* { dg-do compile } */

22298

-/* { dg-options "-O2 -Wno-psabi -msse2 -mno-avx" } */

22299

+/* { dg-prune-output "ABI for passing parameters" } */

22300

+/* { dg-options "-O2 -msse2 -mno-avx" } */

22301

/* { dg-additional-options "-mabi=sysv" { target x86_64-*-mingw* } } */

22302

22303

typedef long long __m256i __attribute__ ((__vector_size__ (32), __may_alias__));

22304

22305

-__m256i

22306

+extern __m256i y;

22307

+

22308

+void

22309

bar (__m256i x) /* { dg-warning "AVX" "" } */

22310

{

22311

- return x;

22312

+ y = x;

22313

}

22314

Index: gcc/testsuite/gcc.target/i386/pr60909-1.c

22315

===================================================================

22316

--- a/src/gcc/testsuite/gcc.target/i386/pr60909-1.c (.../tags/gcc_4_8_2_release)

22317

+++ b/src/gcc/testsuite/gcc.target/i386/pr60909-1.c (.../branches/gcc-4_8-branch)

22318

@@ -0,0 +1,11 @@

22319

+/* { dg-do compile } */

22320

+/* { dg-options "-mrdrnd" } */

22321

+

22322

+extern void bar (int);

22323

+

22324

+void

22325

+foo (unsigned *u)

22326

+{

22327

+ int i = __builtin_ia32_rdrand32_step (u);

22328

+ bar (i);

22329

+}

22330

Index: gcc/testsuite/gcc.target/i386/pr58137.c

22331

===================================================================

22332

--- a/src/gcc/testsuite/gcc.target/i386/pr58137.c (.../tags/gcc_4_8_2_release)

22333

+++ b/src/gcc/testsuite/gcc.target/i386/pr58137.c (.../branches/gcc-4_8-branch)

22334

@@ -0,0 +1,33 @@

22335

+/* { dg-do compile } */

22336

+/* { dg-options "-O3 -mavx2" } */

22337

+

22338

+typedef unsigned int U32;

22339

+

22340

+struct sv {

22341

+ void* sv_any;

22342

+ U32 sv_refcnt;

22343

+ U32 sv_flags;

22344

+};

22345

+typedef struct sv SV;

22346

+

22347

+struct xrv {

22348

+ SV * xrv_rv;

22349

+};

22350

+typedef struct xrv XRV;

22351

+

22352

+extern XRV * PL_xrv_root;

22353

+

22354

+void

22355

+more_xrv (void)

22356

+{

22357

+ register XRV* xrv;

22358

+ register XRV* xrvend;

22359

+ xrv = PL_xrv_root;

22360

+ xrvend = &xrv[200 / sizeof (XRV) - 1];

22361

+ while (xrv < xrvend)

22362

+ {

22363

+ xrv->xrv_rv = (SV*)(xrv + 1);

22364

+ xrv++;

22365

+ }

22366

+ xrv->xrv_rv = 0;

22367

+}

22368

Index: gcc/testsuite/gcc.target/i386/pr59794-4.c

22369

===================================================================

22370

--- a/src/gcc/testsuite/gcc.target/i386/pr59794-4.c (.../tags/gcc_4_8_2_release)

22371

+++ b/src/gcc/testsuite/gcc.target/i386/pr59794-4.c (.../branches/gcc-4_8-branch)

22372

@@ -0,0 +1,14 @@

22373

+/* PR target/59794 */

22374

+/* { dg-do compile { target { ia32 } } } */

22375

+/* { dg-options "-O2 -mno-mmx" } */

22376

+/* { dg-skip-if "no MMX vector" { *-*-mingw* } } */

22377

+

22378

+typedef int __v2si __attribute__ ((__vector_size__ (8)));

22379

+

22380

+extern __v2si x;

22381

+

22382

+__v2si

22383

+foo (void)

22384

+{ /* { dg-warning "MMX vector return without MMX enabled changes the ABI" } */

22385

+ return x;

22386

+}

22387

Index: gcc/testsuite/gcc.target/i386/avx-vzeroupper-16.c

22388

===================================================================

22389

--- a/src/gcc/testsuite/gcc.target/i386/avx-vzeroupper-16.c (.../tags/gcc_4_8_2_release)

22390

+++ b/src/gcc/testsuite/gcc.target/i386/avx-vzeroupper-16.c (.../branches/gcc-4_8-branch)

22391

@@ -1,5 +1,5 @@

22392

/* { dg-do compile { target lp64 } } */

22393

-/* { dg-options "-O2 -mavx -mabi=ms -mtune=generic -dp" } */

22394

+/* { dg-options "-O2 -mavx -mabi=ms -maccumulate-outgoing-args -dp" } */

22395

22396

typedef float __m256 __attribute__ ((__vector_size__ (32), __may_alias__));

22397

22398

Index: gcc/testsuite/gcc.target/i386/pr30315.c

22399

===================================================================

22400

--- a/src/gcc/testsuite/gcc.target/i386/pr30315.c (.../tags/gcc_4_8_2_release)

22401

+++ b/src/gcc/testsuite/gcc.target/i386/pr30315.c (.../branches/gcc-4_8-branch)

22402

@@ -1,6 +1,6 @@

22403

/* { dg-do compile } */

22404

/* { dg-options "-O2" } */

22405

-/* { dg-final { scan-assembler-times "cmp" 4 } } */

22406

+/* { dg-final { scan-assembler-not "cmp" } } */

22407

22408

extern void abort (void);

22409

int c;

22410

@@ -34,39 +34,10 @@

22411

}

22412

#define PLUSCCONLY(T, t) PLUSCCONLY1(T, t, a) PLUSCCONLY1(T, t, b)

22413

22414

-#define MINUSCC(T, t) \

22415

-T minuscc##t (T a, T b) \

22416

-{ \

22417

- T difference = a - b; \

22418

- if (difference > a) \

22419

- abort (); \

22420

- return difference; \

22421

-}

22422

-

22423

-#define DECCC(T, t) \

22424

-T deccc##t (T a, T b) \

22425

-{ \

22426

- T difference = a - b; \

22427

- if (difference > a) \

22428

- c --; \

22429

- return difference; \

22430

-}

22431

-

22432

-#define MINUSCCONLY(T, t) \

22433

-void minuscconly##t (T a, T b) \

22434

-{ \

22435

- T difference = a - b; \

22436

- if (difference > a) \

22437

- abort (); \

22438

-}

22439

-

22440

#define TEST(T, t) \

22441

PLUSCC(T, t) \

22442

PLUSCCONLY(T, t) \

22443

- INCCC(T, t) \

22444

- MINUSCC(T, t) \

22445

- MINUSCCONLY(T, t) \

22446

- DECCC(T, t)

22447

+ INCCC(T, t)

22448

22449

TEST (unsigned long, l)

22450

TEST (unsigned int, i)

22451

@@ -84,14 +55,3 @@

22452

22453

PLUSCCZEXT(a)

22454

PLUSCCZEXT(b)

22455

-

22456

-#define MINUSCCZEXT \

22457

-unsigned long minuscczext (unsigned int a, unsigned int b) \

22458

-{ \

22459

- unsigned int difference = a - b; \

22460

- if (difference > a) \

22461

- abort (); \

22462

- return difference; \

22463

-}

22464

-

22465

-MINUSCCZEXT

22466

Index: gcc/testsuite/gcc.target/i386/pr43869.c

22467

===================================================================

22468

--- a/src/gcc/testsuite/gcc.target/i386/pr43869.c (.../tags/gcc_4_8_2_release)

22469

+++ b/src/gcc/testsuite/gcc.target/i386/pr43869.c (.../branches/gcc-4_8-branch)

22470

@@ -1,4 +1,5 @@

22471

/* { dg-do compile { target lp64 } } */

22472

+/* { dg-options "-maccumulate-outgoing-args" } */

22473

22474

int __attribute__((__noinline__))

22475

bugged(float f1, float f2, float f3, float f4,

22476

Index: gcc/testsuite/gcc.target/i386/pr43546.c

22477

===================================================================

22478

--- a/src/gcc/testsuite/gcc.target/i386/pr43546.c (.../tags/gcc_4_8_2_release)

22479

+++ b/src/gcc/testsuite/gcc.target/i386/pr43546.c (.../branches/gcc-4_8-branch)

22480

@@ -0,0 +1,12 @@

22481

+/* PR target/43546 */

22482

+/* { dg-do compile } */

22483

+/* { dg-options "-O1" } */

22484

+/* { dg-additional-options "-mpreferred-stack-boundary=2 -msseregparm -msse" { target ia32 } } */

22485

+

22486

+extern void bar (double);

22487

+

22488

+void

22489

+foo (void)

22490

+{

22491

+ bar (1.0);

22492

+}

22493

Index: gcc/testsuite/gcc.target/i386/pr43662.c

22494

===================================================================

22495

--- a/src/gcc/testsuite/gcc.target/i386/pr43662.c (.../tags/gcc_4_8_2_release)

22496

+++ b/src/gcc/testsuite/gcc.target/i386/pr43662.c (.../branches/gcc-4_8-branch)

22497

@@ -1,5 +1,5 @@

22498

/* { dg-do compile { target lp64 } } */

22499

-/* { dg-options "-O2" } */

22500

+/* { dg-options "-O2 -maccumulate-outgoing-args" } */

22501

22502

void __attribute__ ((ms_abi)) foo (void)

22503

{

22504

Index: gcc/testsuite/gcc.target/i386/avx-vmovapd-256-1.c

22505

===================================================================

22506

--- a/src/gcc/testsuite/gcc.target/i386/avx-vmovapd-256-1.c (.../tags/gcc_4_8_2_release)

22507

+++ b/src/gcc/testsuite/gcc.target/i386/avx-vmovapd-256-1.c (.../branches/gcc-4_8-branch)

22508

@@ -15,7 +15,7 @@

22509

avx_test (void)

22510

{

22511

union256d u;

22512

- double e [4] __attribute__ ((aligned (8))) = {41124.234,2344.2354,8653.65635,856.43576};

22513

+ double e [4] __attribute__ ((aligned (32))) = {41124.234,2344.2354,8653.65635,856.43576};

22514

22515

u.x = test (e);

22516

22517

Index: gcc/testsuite/gcc.target/i386/nest-1.c

22518

===================================================================

22519

--- a/src/gcc/testsuite/gcc.target/i386/nest-1.c (.../tags/gcc_4_8_2_release)

22520

+++ b/src/gcc/testsuite/gcc.target/i386/nest-1.c (.../branches/gcc-4_8-branch)

22521

@@ -0,0 +1,14 @@

22522

+/* { dg-do compile { target llp64 } } */

22523

+/* { dg-options "" } */

22524

+

22525

+void foo (int i)

22526

+{

22527

+ void nested (void)

22528

+ {

22529

+ char arr[(1U << 31) + 4U];

22530

+ arr[i] = 0;

22531

+ }

22532

+

22533

+ nested ();

22534

+}

22535

+

22536

Index: gcc/testsuite/gcc.target/i386/pr60909-2.c

22537

===================================================================

22538

--- a/src/gcc/testsuite/gcc.target/i386/pr60909-2.c (.../tags/gcc_4_8_2_release)

22539

+++ b/src/gcc/testsuite/gcc.target/i386/pr60909-2.c (.../branches/gcc-4_8-branch)

22540

@@ -0,0 +1,11 @@

22541

+/* { dg-do compile } */

22542

+/* { dg-options "-mrdseed" } */

22543

+

22544

+extern void bar (int);

22545

+

22546

+void

22547

+foo (unsigned *u)

22548

+{

22549

+ int i = __builtin_ia32_rdseed_si_step (u);

22550

+ bar (i);

22551

+}

22552

Index: gcc/testsuite/gcc.target/i386/pr59794-1.c

22553

===================================================================

22554

--- a/src/gcc/testsuite/gcc.target/i386/pr59794-1.c (.../tags/gcc_4_8_2_release)

22555

+++ b/src/gcc/testsuite/gcc.target/i386/pr59794-1.c (.../branches/gcc-4_8-branch)

22556

@@ -0,0 +1,15 @@

22557

+/* PR target/59794 */

22558

+/* { dg-do compile { target { ia32 } } } */

22559

+/* { dg-options "-O2 -mno-mmx" } */

22560

+/* { dg-skip-if "no MMX vector" { *-*-mingw* } } */

22561

+

22562

+typedef int __v2si __attribute__ ((__vector_size__ (8)));

22563

+

22564

+extern __v2si x;

22565

+

22566

+extern void bar (__v2si);

22567

+void

22568

+foo (void)

22569

+{

22570

+ bar (x); /* { dg-message "warning: MMX vector argument without MMX enabled changes the ABI" } */

22571

+}

22572

Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/pr38891.c

22573

===================================================================

22574

--- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/pr38891.c (.../tags/gcc_4_8_2_release)

22575

+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/pr38891.c (.../branches/gcc-4_8-branch)

22576

@@ -1,7 +1,7 @@

22577

/* Test for cross x86_64<->w64 abi standard calls.

22578

*/

22579

/* { dg-do compile } */

22580

-/* { dg-options "-mno-sse" } */

22581

+/* { dg-options "-mno-sse -maccumulate-outgoing-args" } */

22582

#include "callabi.h"

22583

22584

long double

22585

Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-1.c

22586

===================================================================

22587

--- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-1.c (.../tags/gcc_4_8_2_release)

22588

+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-1.c (.../branches/gcc-4_8-branch)

22589

@@ -2,7 +2,7 @@

22590

*/

22591

/* Origin: Kai Tietz <kai.tietz@onevision.com> */

22592

/* { dg-do run } */

22593

-/* { dg-options "-std=gnu99" } */

22594

+/* { dg-options "-std=gnu99 -maccumulate-outgoing-args" } */

22595

#include "callabi.h"

22596

22597

extern __SIZE_TYPE__ strlen (const char *);

22598

Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-2.c

22599

===================================================================

22600

--- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-2.c (.../tags/gcc_4_8_2_release)

22601

+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-2.c (.../branches/gcc-4_8-branch)

22602

@@ -2,7 +2,7 @@

22603

*/

22604

/* Origin: Kai Tietz <kai.tietz@onevision.com> */

22605

/* { dg-do run } */

22606

-/* { dg-options "-std=gnu99" } */

22607

+/* { dg-options "-std=gnu99 -maccumulate-outgoing-args" } */

22608

#include "callabi.h"

22609

22610

extern void abort (void);

22611

Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-3.c

22612

===================================================================

22613

--- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-3.c (.../tags/gcc_4_8_2_release)

22614

+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-3.c (.../branches/gcc-4_8-branch)

22615

@@ -2,7 +2,7 @@

22616

*/

22617

/* Origin: Kai Tietz <kai.tietz@onevision.com> */

22618

/* { dg-do run } */

22619

-/* { dg-options "-std=gnu99" } */

22620

+/* { dg-options "-std=gnu99 -maccumulate-outgoing-args" } */

22621

#include "callabi.h"

22622

22623

extern void abort (void);

22624

Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-4a.c

22625

===================================================================

22626

--- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-4a.c (.../tags/gcc_4_8_2_release)

22627

+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-4a.c (.../branches/gcc-4_8-branch)

22628

@@ -1,6 +1,6 @@

22629

/* Test for cross x86_64<->w64 abi va_list calls. */

22630

/* { dg-do run { target i?86-*-linux* x86_64-*-linux* } } */

22631

-/* { dg-options "-O2 -mabi=ms -std=gnu99 -fno-builtin" } */

22632

+/* { dg-options "-O2 -mabi=ms -std=gnu99 -fno-builtin -maccumulate-outgoing-args" } */

22633

/* { dg-additional-sources "vaarg-4b.c" } */

22634

22635

extern __SIZE_TYPE__ __attribute__ ((sysv_abi)) strlen (const char *);

22636

Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-5a.c

22637

===================================================================

22638

--- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-5a.c (.../tags/gcc_4_8_2_release)

22639

+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-5a.c (.../branches/gcc-4_8-branch)

22640

@@ -1,6 +1,6 @@

22641

/* Test for cross x86_64<->w64 abi va_list calls. */

22642

/* { dg-do run { target i?86-*-linux* x86_64-*-linux* } } */

22643

-/* { dg-options "-O2 -mabi=ms -std=gnu99 -fno-builtin" } */

22644

+/* { dg-options "-O2 -mabi=ms -std=gnu99 -fno-builtin -maccumulate-outgoing-args" } */

22645

/* { dg-additional-sources "vaarg-5b.c" } */

22646

22647

extern void __attribute__ ((sysv_abi)) abort (void);

22648

Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-4b.c

22649

===================================================================

22650

--- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-4b.c (.../tags/gcc_4_8_2_release)

22651

+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-4b.c (.../branches/gcc-4_8-branch)

22652

@@ -1,5 +1,5 @@

22653

/* Test for cross x86_64<->w64 abi va_list calls. */

22654

-/* { dg-options "-O2 -mabi=ms -std=gnu99 -fno-builtin" } */

22655

+/* { dg-options "-O2 -mabi=ms -std=gnu99 -fno-builtin -maccumulate-outgoing-args" } */

22656

22657

#include <stdarg.h>

22658

22659

Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-5b.c

22660

===================================================================

22661

--- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-5b.c (.../tags/gcc_4_8_2_release)

22662

+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-5b.c (.../branches/gcc-4_8-branch)

22663

@@ -1,5 +1,5 @@

22664

/* Test for cross x86_64<->w64 abi va_list calls. */

22665

-/* { dg-options "-O2 -mabi=ms -std=gnu99 -fno-builtin" } */

22666

+/* { dg-options "-O2 -mabi=ms -std=gnu99 -fno-builtin -maccumulate-outgoing-args" } */

22667

22668

#include <stdarg.h>

22669

22670

Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/leaf-1.c

22671

===================================================================

22672

--- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/leaf-1.c (.../tags/gcc_4_8_2_release)

22673

+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/leaf-1.c (.../branches/gcc-4_8-branch)

22674

@@ -1,5 +1,5 @@

22675

/* { dg-do compile } */

22676

-/* { dg-options "-O2 -mabi=sysv" } */

22677

+/* { dg-options "-O2 -mabi=sysv -maccumulate-outgoing-args" } */

22678

22679

__attribute__ ((ms_abi))

22680

int foo (void)

22681

Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/leaf-2.c

22682

===================================================================

22683

--- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/leaf-2.c (.../tags/gcc_4_8_2_release)

22684

+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/leaf-2.c (.../branches/gcc-4_8-branch)

22685

@@ -1,5 +1,5 @@

22686

/* { dg-do compile } */

22687

-/* { dg-options "-O2 -mabi=sysv" } */

22688

+/* { dg-options "-O2 -mabi=sysv -maccumulate-outgoing-args" } */

22689

22690

extern int glb1, gbl2, gbl3;

22691

22692

Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/func-1.c

22693

===================================================================

22694

--- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-1.c (.../tags/gcc_4_8_2_release)

22695

+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-1.c (.../branches/gcc-4_8-branch)

22696

@@ -2,7 +2,7 @@

22697

*/

22698

/* Origin: Kai Tietz <kai.tietz@onevision.com> */

22699

/* { dg-do run } */

22700

-/* { dg-options "-std=gnu99 -ffast-math" } */

22701

+/* { dg-options "-std=gnu99 -ffast-math -maccumulate-outgoing-args" } */

22702

#include "callabi.h"

22703

22704

extern void abort (void);

22705

Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect-2a.c

22706

===================================================================

22707

--- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect-2a.c (.../tags/gcc_4_8_2_release)

22708

+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect-2a.c (.../branches/gcc-4_8-branch)

22709

@@ -1,6 +1,6 @@

22710

/* Test for cross x86_64<->w64 abi standard calls via variable. */

22711

/* { dg-do run { target i?86-*-linux* x86_64-*-linux* } } */

22712

-/* { dg-options "-O2 -mabi=ms -std=gnu99 -ffast-math -fno-builtin" } */

22713

+/* { dg-options "-O2 -mabi=ms -std=gnu99 -ffast-math -fno-builtin -maccumulate-outgoing-args" } */

22714

/* { dg-additional-sources "func-indirect-2b.c" } */

22715

22716

extern void __attribute__ ((sysv_abi)) abort (void);

22717

Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect.c

22718

===================================================================

22719

--- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect.c (.../tags/gcc_4_8_2_release)

22720

+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect.c (.../branches/gcc-4_8-branch)

22721

@@ -2,7 +2,7 @@

22722

*/

22723

/* Origin: Kai Tietz <kai.tietz@onevision.com> */

22724

/* { dg-do run } */

22725

-/* { dg-options "-std=gnu99 -ffast-math" } */

22726

+/* { dg-options "-std=gnu99 -ffast-math -maccumulate-outgoing-args" } */

22727

#include "callabi.h"

22728

22729

extern void abort (void);

22730

Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/func-2a.c

22731

===================================================================

22732

--- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-2a.c (.../tags/gcc_4_8_2_release)

22733

+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-2a.c (.../branches/gcc-4_8-branch)

22734

@@ -1,6 +1,6 @@

22735

/* Test for cross x86_64<->w64 abi standard calls. */

22736

/* { dg-do run { target i?86-*-linux* x86_64-*-linux* } } */

22737

-/* { dg-options "-O2 -mabi=ms -std=gnu99 -ffast-math -fno-builtin" } */

22738

+/* { dg-options "-O2 -mabi=ms -std=gnu99 -ffast-math -fno-builtin -maccumulate-outgoing-args" } */

22739

/* { dg-additional-sources "func-2b.c" } */

22740

22741

extern void __attribute__ ((sysv_abi)) abort (void);

22742

Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect-2b.c

22743

===================================================================

22744

--- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect-2b.c (.../tags/gcc_4_8_2_release)

22745

+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect-2b.c (.../branches/gcc-4_8-branch)

22746

@@ -1,5 +1,5 @@

22747

/* Test for cross x86_64<->w64 abi standard calls via variable. */

22748

-/* { dg-options "-O2 -mabi=ms -std=gnu99 -ffast-math -fno-builtin" } */

22749

+/* { dg-options "-O2 -mabi=ms -std=gnu99 -ffast-math -fno-builtin -maccumulate-outgoing-args" } */

22750

22751

typedef int (*func)(void *, char *, char *, short, long long);

22752

22753

Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/func-2b.c

22754

===================================================================

22755

--- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-2b.c (.../tags/gcc_4_8_2_release)

22756

+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-2b.c (.../branches/gcc-4_8-branch)

22757

@@ -1,5 +1,5 @@

22758

/* Test for cross x86_64<->w64 abi standard calls. */

22759

-/* { dg-options "-mabi=ms -std=gnu99 -ffast-math -fno-builtin" } */

22760

+/* { dg-options "-mabi=ms -std=gnu99 -ffast-math -fno-builtin -maccumulate-outgoing-args" } */

22761

22762

long double func_cross (long double a, double b, float c, long d, int e,

22763

char f)

22764

Index: gcc/testsuite/gcc.target/s390/htm-xl-intrin-1.c

22765

===================================================================

22766

--- a/src/gcc/testsuite/gcc.target/s390/htm-xl-intrin-1.c (.../tags/gcc_4_8_2_release)

22767

+++ b/src/gcc/testsuite/gcc.target/s390/htm-xl-intrin-1.c (.../branches/gcc-4_8-branch)

22768

@@ -1,37 +0,0 @@

22769

-/* This checks the availability of the XL compiler intrinsics for

22770

- transactional execution with the expected prototypes. */

22771

-

22772

-/* { dg-do compile } */

22773

-/* { dg-options "-O3 -march=zEC12 -mzarch" } */

22774

-

22775

-#include <htmxlintrin.h>

22776

-

22777

-int a = 0;

22778

-unsigned long g;

22779

-

22780

-int

22781

-foo ()

22782

-{

22783

- struct __htm_tdb *tdb_struct;

22784

- void * const tdb = tdb_struct;

22785

- long result;

22786

- unsigned char code;

22787

-

22788

- result = __TM_simple_begin ();

22789

- result = __TM_begin (tdb);

22790

- result = __TM_end ();

22791

- __TM_abort ();

22792

- __TM_named_abort (42);

22793

- __TM_non_transactional_store (&g, 42);

22794

- result = __TM_nesting_depth (tdb);

22795

-

22796

- result = __TM_is_user_abort (tdb);

22797

- result = __TM_is_named_user_abort (tdb, &code);

22798

- result = __TM_is_illegal (tdb);

22799

- result = __TM_is_footprint_exceeded (tdb);

22800

- result = __TM_is_nested_too_deep (tdb);

22801

- result = __TM_is_conflict (tdb);

22802

- result = __TM_is_failure_persistent (result);

22803

- result = __TM_failure_address (tdb);

22804

- result = __TM_failure_code (tdb);

22805

-}

22806

Index: gcc/testsuite/gcc.target/s390/htm-1.c

22807

===================================================================

22808

--- a/src/gcc/testsuite/gcc.target/s390/htm-1.c (.../tags/gcc_4_8_2_release)

22809

+++ b/src/gcc/testsuite/gcc.target/s390/htm-1.c (.../branches/gcc-4_8-branch)

22810

@@ -1,73 +0,0 @@

22811

-/* This checks the availability of the low-level builtins introduced

22812

- for transactional execution. */

22813

-

22814

-/* { dg-do compile } */

22815

-/* { dg-options "-O3 -march=zEC12 -mzarch" } */

22816

-

22817

-#include <stdint.h>

22818

-#include <htmintrin.h>

22819

-

22820

-int global = 0;

22821

-uint64_t g;

22822

-struct __htm_tdb global_tdb;

22823

-

22824

-int

22825

-foo (struct __htm_tdb* tdb, int reg, int *mem, uint64_t *mem64)

22826

-{

22827

-

22828

- int cc;

22829

- int n;

22830

-

22831

- cc = __builtin_tbegin (0);

22832

- cc = __builtin_tbegin (tdb);

22833

- cc = __builtin_tbegin (&global_tdb);

22834

-

22835

- cc = __builtin_tbegin_nofloat (0);

22836

- cc = __builtin_tbegin_nofloat (&global_tdb);

22837

-

22838

- cc = __builtin_tbegin_retry (0, 42);

22839

- cc = __builtin_tbegin_retry (0, reg);

22840

- cc = __builtin_tbegin_retry (0, *mem);

22841

- cc = __builtin_tbegin_retry (0, global);

22842

- cc = __builtin_tbegin_retry (tdb, 42);

22843

- cc = __builtin_tbegin_retry (&global_tdb, 42);

22844

-

22845

- cc = __builtin_tbegin_retry_nofloat (0, 42);

22846

- cc = __builtin_tbegin_retry_nofloat (0, reg);

22847

- cc = __builtin_tbegin_retry_nofloat (0, *mem);

22848

- cc = __builtin_tbegin_retry_nofloat (0, global);

22849

- cc = __builtin_tbegin_retry_nofloat (&global_tdb, 42);

22850

-

22851

- __builtin_tbeginc ();

22852

-

22853

- n = __builtin_tx_nesting_depth();

22854

-

22855

- __builtin_non_tx_store(&g, 23);

22856

- __builtin_non_tx_store(mem64, 23);

22857

- __builtin_non_tx_store(&g, reg);

22858

- __builtin_non_tx_store(&g, *mem);

22859

- __builtin_non_tx_store(&g, global);

22860

-

22861

- __builtin_tabort (42 + 255);

22862

- __builtin_tabort (reg);

22863

- /* { dg-final { scan-assembler-times "tabort\t255" 1 } } */

22864

- __builtin_tabort (reg + 255);

22865

- __builtin_tabort (*mem);

22866

- __builtin_tabort (global);

22867

- /* Here global + 255 gets reloaded into a reg. Better would be to

22868

- just reload global or *mem and get the +255 for free as address

22869

- arithmetic. */

22870

- __builtin_tabort (*mem + 255);

22871

- __builtin_tabort (global + 255);

22872

-

22873

- __builtin_tend();

22874

-

22875

- __builtin_tx_assist (23);

22876

- __builtin_tx_assist (reg);

22877

- __builtin_tx_assist (*mem);

22878

- __builtin_tx_assist (global);

22879

-}

22880

-

22881

-/* Make sure the tdb NULL argument ends up as immediate value in the

22882

- instruction. */

22883

-/* { dg-final { scan-assembler-times "tbegin\t0," 10 } } */

22884

Index: gcc/testsuite/gcc.target/s390/htm-nofloat-2.c

22885

===================================================================

22886

--- a/src/gcc/testsuite/gcc.target/s390/htm-nofloat-2.c (.../tags/gcc_4_8_2_release)

22887

+++ b/src/gcc/testsuite/gcc.target/s390/htm-nofloat-2.c (.../branches/gcc-4_8-branch)

22888

@@ -1,55 +0,0 @@

22889

-/* { dg-do run } */

22890

-/* { dg-options "-O3 -mhtm -Wa,-march=zEC12,-mzarch --save-temps" } */

22891

-

22892

-/* __builtin_tbegin has to emit clobbers for all FPRs since the tbegin

22893

- instruction does not automatically preserves them. If the

22894

- transaction body is fully contained in a function the backend tries

22895

- after reload to get rid of the FPR save/restore operations

22896

- triggered by the clobbers. This testcase failed since the backend

22897

- was able to get rid of all FPR saves/restores and since these were

22898

- the only stack operations also of the entire stack space. So even

22899

- the save/restore of the stack pointer was omitted in the end.

22900

- However, since the frame layout has been fixed before, the prologue

22901

- still generated the stack pointer decrement making foo return with

22902

- a modified stack pointer. */

22903

-

22904

-void abort(void);

22905

-

22906

-void __attribute__((noinline))

22907

-foo (int a)

22908

-{

22909

- /* This is just to prevent the tbegin code from actually being

22910

- executed. That way the test may even run on machines prior to

22911

- zEC12. */

22912

- if (a == 42)

22913

- return;

22914

-

22915

- if (__builtin_tbegin (0) == 0)

22916

- __builtin_tend ();

22917

-}

22918

-

22919

-#ifdef __s390x__

22920

-#define GET_STACK_POINTER(SP) \

22921

- asm volatile ("stg %%r15, %0" : "=QRST" (SP));

22922

-#else

22923

-#define GET_STACK_POINTER(SP) \

22924

- asm volatile ("st %%r15, %0" : "=QR" (SP));

22925

-#endif

22926

-

22927

-int main(void)

22928

-{

22929

- unsigned long new_sp, old_sp;

22930

-

22931

- GET_STACK_POINTER (old_sp);

22932

- foo(42);

22933

- GET_STACK_POINTER (new_sp);

22934

-

22935

- if (old_sp != new_sp)

22936

- abort ();

22937

-

22938

- return 0;

22939

-}

22940

-

22941

-/* Make sure no FPR saves/restores are emitted. */

22942

-/* { dg-final { scan-assembler-not "\tstd\t" } } */

22943

-/* { dg-final { scan-assembler-not "\tld\t" } } */

22944

Index: gcc/testsuite/gcc.target/s390/hotpatch-compile-1.c

22945

===================================================================

22946

--- a/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-1.c (.../tags/gcc_4_8_2_release)

22947

+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-1.c (.../branches/gcc-4_8-branch)

22948

@@ -0,0 +1,27 @@

22949

+/* Functional tests for the function hotpatching feature. */

22950

+

22951

+/* { dg-do run } */

22952

+/* { dg-options "-O3 -mzarch -mhotpatch" } */

22953

+

22954

+#include <stdio.h>

22955

+

22956

+void hp1(void)

22957

+{

22958

+ printf("hello, world!\n");

22959

+}

22960

+

22961

+inline void hp2(void)

22962

+{

22963

+ printf("hello, world!\n");

22964

+}

22965

+

22966

+__attribute__ ((always_inline))

22967

+void hp3(void) /* { dg-warning "always_inline function might not be inlinable" } */

22968

+{

22969

+ printf("hello, world!\n");

22970

+} /* { dg-warning "function 'hp3' with the 'always_inline' attribute is not hotpatchable" } */

22971

+

22972

+int main (void)

22973

+{

22974

+ return 0;

22975

+}

22976

Index: gcc/testsuite/gcc.target/s390/hotpatch-compile-2.c

22977

===================================================================

22978

--- a/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-2.c (.../tags/gcc_4_8_2_release)

22979

+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-2.c (.../branches/gcc-4_8-branch)

22980

@@ -0,0 +1,27 @@

22981

+/* Functional tests for the function hotpatching feature. */

22982

+

22983

+/* { dg-do run } */

22984

+/* { dg-options "-O3 -mzarch -mhotpatch=0" } */

22985

+

22986

+#include <stdio.h>

22987

+

22988

+void hp1(void)

22989

+{

22990

+ printf("hello, world!\n");

22991

+}

22992

+

22993

+inline void hp2(void)

22994

+{

22995

+ printf("hello, world!\n");

22996

+}

22997

+

22998

+__attribute__ ((always_inline))

22999

+void hp3(void) /* { dg-warning "always_inline function might not be inlinable" } */

23000

+{

23001

+ printf("hello, world!\n");

23002

+} /* { dg-warning "function 'hp3' with the 'always_inline' attribute is not hotpatchable" } */

23003

+

23004

+int main (void)

23005

+{

23006

+ return 0;

23007

+}

23008

Index: gcc/testsuite/gcc.target/s390/hotpatch-compile-3.c

23009

===================================================================

23010

--- a/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-3.c (.../tags/gcc_4_8_2_release)

23011

+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-3.c (.../branches/gcc-4_8-branch)

23012

@@ -0,0 +1,27 @@

23013

+/* Functional tests for the function hotpatching feature. */

23014

+

23015

+/* { dg-do run } */

23016

+/* { dg-options "-O3 -mzarch -mhotpatch=1" } */

23017

+

23018

+#include <stdio.h>

23019

+

23020

+void hp1(void)

23021

+{

23022

+ printf("hello, world!\n");

23023

+}

23024

+

23025

+inline void hp2(void)

23026

+{

23027

+ printf("hello, world!\n");

23028

+}

23029

+

23030

+__attribute__ ((always_inline))

23031

+void hp3(void) /* { dg-warning "always_inline function might not be inlinable" } */

23032

+{

23033

+ printf("hello, world!\n");

23034

+} /* { dg-warning "function 'hp3' with the 'always_inline' attribute is not hotpatchable" } */

23035

+

23036

+int main (void)

23037

+{

23038

+ return 0;

23039

+}

23040

Index: gcc/testsuite/gcc.target/s390/hotpatch-compile-4.c

23041

===================================================================

23042

--- a/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-4.c (.../tags/gcc_4_8_2_release)

23043

+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-4.c (.../branches/gcc-4_8-branch)

23044

@@ -0,0 +1,11 @@

23045

+/* Functional tests for the function hotpatching feature. */

23046

+

23047

+/* { dg-do compile } */

23048

+/* { dg-options "-O3 -mzarch -mhotpatch=-1" } */

23049

+

23050

+int main (void)

23051

+{

23052

+ return 0;

23053

+}

23054

+

23055

+/* { dg-excess-errors "argument to '-mhotpatch=' should be a non-negative integer" } */

23056

Index: gcc/testsuite/gcc.target/s390/hotpatch-compile-5.c

23057

===================================================================

23058

--- a/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-5.c (.../tags/gcc_4_8_2_release)

23059

+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-5.c (.../branches/gcc-4_8-branch)

23060

@@ -0,0 +1,28 @@

23061

+/* Functional tests for the function hotpatching feature. */

23062

+

23063

+/* { dg-do compile } */

23064

+/* { dg-options "-O3 -mzarch -mhotpatch=1000000" } */

23065

+

23066

+#include <stdio.h>

23067

+

23068

+void hp1(void)

23069

+{

23070

+ printf("hello, world!\n");

23071

+}

23072

+

23073

+__attribute__ ((hotpatch(1000000)))

23074

+void hp2(void)

23075

+{

23076

+ printf("hello, world!\n");

23077

+}

23078

+

23079

+__attribute__ ((hotpatch(1000001)))

23080

+void hp3(void)

23081

+{ /* { dg-error "requested 'hotpatch' attribute is not a non-negative integer constant or too large .max. 1000000." } */

23082

+ printf("hello, world!\n");

23083

+}

23084

+

23085

+int main (void)

23086

+{

23087

+ return 0;

23088

+}

23089

Index: gcc/testsuite/gcc.target/s390/hotpatch-compile-6.c

23090

===================================================================

23091

--- a/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-6.c (.../tags/gcc_4_8_2_release)

23092

+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-6.c (.../branches/gcc-4_8-branch)

23093

@@ -0,0 +1,11 @@

23094

+/* Functional tests for the function hotpatching feature. */

23095

+

23096

+/* { dg-do compile } */

23097

+/* { dg-options "-O3 -mzarch -mhotpatch=1000001" } */

23098

+

23099

+int main (void)

23100

+{

23101

+ return 0;

23102

+}

23103

+

23104

+/* { dg-excess-errors "argument to '-mhotpatch=' is too large .max. 1000000." } */

23105

Index: gcc/testsuite/gcc.target/s390/htm-builtins-compile-1.c

23106

===================================================================

23107

--- a/src/gcc/testsuite/gcc.target/s390/htm-builtins-compile-1.c (.../tags/gcc_4_8_2_release)

23108

+++ b/src/gcc/testsuite/gcc.target/s390/htm-builtins-compile-1.c (.../branches/gcc-4_8-branch)

23109

@@ -0,0 +1,164 @@

23110

+/* This checks the availability of the low-level builtins introduced

23111

+ for transactional execution. */

23112

+

23113

+/* { dg-do compile } */

23114

+/* { dg-options "-O3 -march=zEC12 -mzarch" } */

23115

+

23116

+#include <stdint.h>

23117

+#include <htmintrin.h>

23118

+

23119

+int global = 0;

23120

+uint64_t g;

23121

+struct __htm_tdb global_tdb;

23122

+

23123

+int

23124

+foo (struct __htm_tdb* tdb, int reg, int *mem, uint64_t *mem64)

23125

+{

23126

+

23127

+ int cc;

23128

+ int n;

23129

+

23130

+ __builtin_tbegin ((void *)0);

23131

+ __builtin_tbegin ((void *)-99999);

23132

+ __builtin_tbegin ((void *)99999);

23133

+ while (__builtin_tbegin ((void *)0) != 0)

23134

+ {

23135

+ }

23136

+ cc = __builtin_tbegin ((void *)0x12345678);

23137

+ cc = __builtin_tbegin (tdb);

23138

+ cc = __builtin_tbegin (&global_tdb);

23139

+ cc = __builtin_tbegin ((void *)(long)(reg + 0x12345678));

23140

+ cc = __builtin_tbegin ((void *)(long)(reg));

23141

+

23142

+ __builtin_tbegin_nofloat ((void *)0);

23143

+ __builtin_tbegin_nofloat ((void *)-99999);

23144

+ __builtin_tbegin_nofloat ((void *)99999);

23145

+ cc = __builtin_tbegin_nofloat ((void *)0x12345678);

23146

+ cc = __builtin_tbegin_nofloat (tdb);

23147

+ cc = __builtin_tbegin_nofloat (&global_tdb);

23148

+ cc = __builtin_tbegin_nofloat ((void *)(long)(reg + 0x12345678));

23149

+ cc = __builtin_tbegin_nofloat ((void *)(long)(reg));

23150

+

23151

+ __builtin_tbegin_retry ((void *)0, 0);

23152

+ cc = __builtin_tbegin_retry ((void *)0, 1);

23153

+ cc = __builtin_tbegin_retry ((void *)0, -1);

23154

+ cc = __builtin_tbegin_retry ((void *)0, 42);

23155

+ cc = __builtin_tbegin_retry ((void *)0, reg);

23156

+ cc = __builtin_tbegin_retry ((void *)0, *mem);

23157

+ cc = __builtin_tbegin_retry ((void *)0, global);

23158

+ cc = __builtin_tbegin_retry (tdb, 42);

23159

+ cc = __builtin_tbegin_retry (&global_tdb, 42);

23160

+ cc = __builtin_tbegin_retry ((void *)0x12345678, global);

23161

+ cc = __builtin_tbegin_retry (

23162

+ (void *)(long) (reg + 0x12345678), global + 1);

23163

+ cc = __builtin_tbegin_retry (

23164

+ (void *)(long)(reg), global - 1);

23165

+

23166

+ __builtin_tbegin_retry_nofloat ((void *)0, 0);

23167

+ cc = __builtin_tbegin_retry_nofloat ((void *)0, 1);

23168

+ cc = __builtin_tbegin_retry_nofloat ((void *)0, -1);

23169

+ cc = __builtin_tbegin_retry_nofloat ((void *)0, 42);

23170

+ cc = __builtin_tbegin_retry_nofloat ((void *)0, reg);

23171

+ cc = __builtin_tbegin_retry_nofloat ((void *)0, *mem);

23172

+ cc = __builtin_tbegin_retry_nofloat ((void *)0, global);

23173

+ cc = __builtin_tbegin_retry_nofloat (tdb, 42);

23174

+ cc = __builtin_tbegin_retry_nofloat (&global_tdb, 42);

23175

+ cc = __builtin_tbegin_retry_nofloat ((void *)0x12345678, global);

23176

+ cc = __builtin_tbegin_retry_nofloat (

23177

+ (void *)(long) (reg + 0x12345678), global + 1);

23178

+ cc = __builtin_tbegin_retry_nofloat (

23179

+ (void *)(long)(reg), global - 1);

23180

+

23181

+ __builtin_tbeginc ();

23182

+

23183

+ __builtin_tx_nesting_depth ();

23184

+ n = __builtin_tx_nesting_depth ();

23185

+

23186

+ __builtin_non_tx_store (mem64, 0);

23187

+ {

23188

+ const uint64_t val_var = 0x1122334455667788;

23189

+

23190

+ __builtin_non_tx_store (mem64, val_var);

23191

+ }

23192

+ __builtin_non_tx_store (mem64, (uint64_t)reg);

23193

+ __builtin_non_tx_store (mem64, g);

23194

+ __builtin_non_tx_store ((uint64_t *)0, 0);

23195

+ __builtin_non_tx_store ((uint64_t *)0x12345678, 0);

23196

+ __builtin_non_tx_store (&g, 23);

23197

+ __builtin_non_tx_store (&g, reg);

23198

+ __builtin_non_tx_store (&g, *mem);

23199

+ __builtin_non_tx_store (&g, global);

23200

+

23201

+ __builtin_tend();

23202

+

23203

+ __builtin_tx_assist (0);

23204

+ __builtin_tx_assist (1);

23205

+ __builtin_tx_assist (reg);

23206

+ __builtin_tx_assist (*mem);

23207

+ __builtin_tx_assist (global);

23208

+}

23209

+

23210

+/* The taborts must go into separate function since they are

23211

+ "noreturn". */

23212

+

23213

+void

23214

+tabort1 ()

23215

+{

23216

+ __builtin_tabort (256);

23217

+}

23218

+

23219

+void

23220

+tabort2 (int reg)

23221

+{

23222

+ __builtin_tabort (reg);

23223

+}

23224

+

23225

+void

23226

+tabort3 (int reg)

23227

+{

23228

+ /* { dg-final { scan-assembler-times "tabort\t255" 1 } } */

23229

+ __builtin_tabort (reg + 255);

23230

+}

23231

+

23232

+void

23233

+tabort4 (int *mem)

23234

+{

23235

+ __builtin_tabort (*mem);

23236

+}

23237

+

23238

+void

23239

+tabort5 ()

23240

+{

23241

+ __builtin_tabort (global);

23242

+}

23243

+

23244

+void

23245

+tabort6 (int *mem)

23246

+{

23247

+ /* Here global + 255 gets reloaded into a reg. Better would be to

23248

+ just reload global or *mem and get the +255 for free as address

23249

+ arithmetic. */

23250

+ __builtin_tabort (*mem + 255);

23251

+}

23252

+

23253

+void

23254

+tabort7 ()

23255

+{

23256

+ __builtin_tabort (global + 255);

23257

+}

23258

+

23259

+void

23260

+tabort8 ()

23261

+{

23262

+ __builtin_tabort (-1);

23263

+}

23264

+

23265

+

23266

+/* Make sure the tdb NULL argument ends up as immediate value in the

23267

+ instruction. */

23268

+/* { dg-final { scan-assembler-times "tbegin\t0," 17 } } */

23269

+/* { dg-final { scan-assembler-times "tbegin\t" 41 } } */

23270

+/* Check number of occurences of certain instructions. */

23271

+/* { dg-final { scan-assembler-times "tbeginc\t" 1 } } */

23272

+/* { dg-final { scan-assembler-times "tabort\t" 8 } } */

23273

+/* { dg-final { scan-assembler "ppa\t" } } */

23274

Index: gcc/testsuite/gcc.target/s390/hotpatch-compile-7.c

23275

===================================================================

23276

--- a/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-7.c (.../tags/gcc_4_8_2_release)

23277

+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-7.c (.../branches/gcc-4_8-branch)

23278

@@ -0,0 +1,68 @@

23279

+/* Functional tests for the function hotpatching feature. */

23280

+

23281

+/* { dg-do run } */

23282

+/* { dg-options "-O3 -mzarch -mno-hotpatch" } */

23283

+

23284

+#include <stdio.h>

23285

+

23286

+__attribute__ ((hotpatch))

23287

+void hp1(void)

23288

+{

23289

+ printf("hello, world!\n");

23290

+}

23291

+

23292

+__attribute__ ((hotpatch))

23293

+inline void hp2(void)

23294

+{

23295

+ printf("hello, world!\n");

23296

+}

23297

+

23298

+__attribute__ ((hotpatch))

23299

+__attribute__ ((always_inline))

23300

+void hp3(void) /* { dg-warning "always_inline function might not be inlinable" } */

23301

+{

23302

+ printf("hello, world!\n");

23303

+} /* { dg-warning "function 'hp3' with the 'always_inline' attribute is not hotpatchable" } */

23304

+

23305

+__attribute__ ((hotpatch(0)))

23306

+void hp4(void)

23307

+{

23308

+ printf("hello, world!\n");

23309

+}

23310

+

23311

+__attribute__ ((hotpatch(0)))

23312

+inline void hp5(void)

23313

+{

23314

+ printf("hello, world!\n");

23315

+}

23316

+

23317

+__attribute__ ((hotpatch(0)))

23318

+__attribute__ ((always_inline))

23319

+void hp6(void) /* { dg-warning "always_inline function might not be inlinable" } */

23320

+{

23321

+ printf("hello, world!\n");

23322

+} /* { dg-warning "function 'hp6' with the 'always_inline' attribute is not hotpatchable" } */

23323

+

23324

+__attribute__ ((hotpatch(1)))

23325

+void hp7(void)

23326

+{

23327

+ printf("hello, world!\n");

23328

+}

23329

+

23330

+__attribute__ ((hotpatch(1)))

23331

+inline void hp8(void)

23332

+{

23333

+ printf("hello, world!\n");

23334

+}

23335

+

23336

+__attribute__ ((hotpatch(1)))

23337

+__attribute__ ((always_inline))

23338

+void hp9(void) /* { dg-warning "always_inline function might not be inlinable" } */

23339

+{

23340

+ printf("hello, world!\n");

23341

+} /* { dg-warning "function 'hp9' with the 'always_inline' attribute is not hotpatchable" } */

23342

+

23343

+int main (void)

23344

+{

23345

+ return 0;

23346

+}

23347

Index: gcc/testsuite/gcc.target/s390/htm-builtins-compile-2.c

23348

===================================================================

23349

--- a/src/gcc/testsuite/gcc.target/s390/htm-builtins-compile-2.c (.../tags/gcc_4_8_2_release)

23350

+++ b/src/gcc/testsuite/gcc.target/s390/htm-builtins-compile-2.c (.../branches/gcc-4_8-branch)

23351

@@ -0,0 +1,12 @@

23352

+/* { dg-do compile } */

23353

+/* { dg-options "-O3 -march=zEC12 -mzarch" } */

23354

+

23355

+void must_not_compile1 (void)

23356

+{

23357

+ __builtin_tabort (0); /* { dg-error "Invalid transaction abort code:" } */

23358

+}

23359

+

23360

+void must_not_compile2 (void)

23361

+{

23362

+ __builtin_tabort (255); /* { dg-error "Invalid transaction abort code:" } */

23363

+}

23364

Index: gcc/testsuite/gcc.target/s390/hotpatch-compile-8.c

23365

===================================================================

23366

--- a/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-8.c (.../tags/gcc_4_8_2_release)

23367

+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-8.c (.../branches/gcc-4_8-branch)

23368

@@ -0,0 +1,23 @@

23369

+/* Functional tests for the function hotpatching feature. */

23370

+

23371

+/* { dg-do run } */

23372

+/* { dg-options "-O3 -mzarch -mhotpatch" } */

23373

+

23374

+#include <stdio.h>

23375

+

23376

+int hp1(void)

23377

+{

23378

+ int nested1(void) /* { dg-warning "hotpatching is not compatible with nested functions" } */

23379

+ { return 1; }

23380

+

23381

+ __attribute__ ((hotpatch))

23382

+ int nested2(void) /* { dg-warning "hotpatching is not compatible with nested functions" } */

23383

+ { return 1; }

23384

+

23385

+ return nested1() - nested2();

23386

+}

23387

+

23388

+int main (void)

23389

+{

23390

+ return hp1();

23391

+}

23392

Index: gcc/testsuite/gcc.target/s390/htm-builtins-compile-3.c

23393

===================================================================

23394

--- a/src/gcc/testsuite/gcc.target/s390/htm-builtins-compile-3.c (.../tags/gcc_4_8_2_release)

23395

+++ b/src/gcc/testsuite/gcc.target/s390/htm-builtins-compile-3.c (.../branches/gcc-4_8-branch)

23396

@@ -0,0 +1,37 @@

23397

+/* This checks the availability of the XL compiler intrinsics for

23398

+ transactional execution with the expected prototypes. */

23399

+

23400

+/* { dg-do compile } */

23401

+/* { dg-options "-O3 -march=zEC12 -mzarch" } */

23402

+

23403

+#include <htmxlintrin.h>

23404

+

23405

+int a = 0;

23406

+unsigned long g;

23407

+

23408

+int

23409

+foo ()

23410

+{

23411

+ struct __htm_tdb *tdb_struct;

23412

+ void * const tdb = tdb_struct;

23413

+ long result;

23414

+ unsigned char code;

23415

+

23416

+ result = __TM_simple_begin ();

23417

+ result = __TM_begin (tdb);

23418

+ result = __TM_end ();

23419

+ __TM_abort ();

23420

+ __TM_named_abort (42);

23421

+ __TM_non_transactional_store (&g, 42);

23422

+ result = __TM_nesting_depth (tdb);

23423

+

23424

+ result = __TM_is_user_abort (tdb);

23425

+ result = __TM_is_named_user_abort (tdb, &code);

23426

+ result = __TM_is_illegal (tdb);

23427

+ result = __TM_is_footprint_exceeded (tdb);

23428

+ result = __TM_is_nested_too_deep (tdb);

23429

+ result = __TM_is_conflict (tdb);

23430

+ result = __TM_is_failure_persistent (result);

23431

+ result = __TM_failure_address (tdb);

23432

+ result = __TM_failure_code (tdb);

23433

+}

23434

Index: gcc/testsuite/gcc.target/s390/s390.exp

23435

===================================================================

23436

--- a/src/gcc/testsuite/gcc.target/s390/s390.exp (.../tags/gcc_4_8_2_release)

23437

+++ b/src/gcc/testsuite/gcc.target/s390/s390.exp (.../branches/gcc-4_8-branch)

23438

@@ -24,6 +24,19 @@

23439

# Load support procs.

23440

load_lib gcc-dg.exp

23441

23442

+# Return 1 if htm (etnd - extract nesting depth) instructions are

23443

+# understood by the assembler and can be executed.

23444

+proc check_effective_target_htm { } {

23445

+ if { ![check_runtime s390_check_htm [subst {

23446

+ int main (void)

23447

+ {

23448

+ unsigned int nd;

23449

+ asm ("etnd %0" : "=d" (nd));

23450

+ return nd;

23451

+ }

23452

+ }] "-march=zEC12 -mzarch" ] } { return 0 } else { return 1 }

23453

+}

23454

+

23455

# If a testcase doesn't have special options, use these.

23456

global DEFAULT_CFLAGS

23457

if ![info exists DEFAULT_CFLAGS] then {

23458

Index: gcc/testsuite/gcc.target/s390/htm-nofloat-1.c

23459

===================================================================

23460

--- a/src/gcc/testsuite/gcc.target/s390/htm-nofloat-1.c (.../tags/gcc_4_8_2_release)

23461

+++ b/src/gcc/testsuite/gcc.target/s390/htm-nofloat-1.c (.../branches/gcc-4_8-branch)

23462

@@ -1,12 +1,50 @@

23463

-/* { dg-do compile } */

23464

-/* { dg-options "-O3 -march=zEC12 -mzarch" } */

23465

+/* { dg-do run } */

23466

+/* { dg-require-effective-target htm } */

23467

+/* { dg-options "-O3 -march=zEC12 -mzarch --save-temps" } */

23468

23469

-int

23470

-foo ()

23471

+/* __builtin_tbegin has to emit clobbers for all FPRs since the tbegin

23472

+ instruction does not automatically preserves them. If the

23473

+ transaction body is fully contained in a function the backend tries

23474

+ after reload to get rid of the FPR save/restore operations

23475

+ triggered by the clobbers. This testcase failed since the backend

23476

+ was able to get rid of all FPR saves/restores and since these were

23477

+ the only stack operations also of the entire stack space. So even

23478

+ the save/restore of the stack pointer was omitted in the end.

23479

+ However, since the frame layout has been fixed before, the prologue

23480

+ still generated the stack pointer decrement making foo return with

23481

+ a modified stack pointer. */

23482

+

23483

+void abort(void);

23484

+

23485

+void __attribute__((noinline))

23486

+foo (int a)

23487

{

23488

- __builtin_tbegin_nofloat (0);

23489

- __builtin_tbegin_retry_nofloat (0, 42);

23490

+ if (__builtin_tbegin (0) == 0)

23491

+ __builtin_tend ();

23492

}

23493

+

23494

+#ifdef __s390x__

23495

+#define GET_STACK_POINTER(SP) \

23496

+ asm volatile ("stg %%r15, %0" : "=QRST" (SP));

23497

+#else

23498

+#define GET_STACK_POINTER(SP) \

23499

+ asm volatile ("st %%r15, %0" : "=QR" (SP));

23500

+#endif

23501

+

23502

+int main(void)

23503

+{

23504

+ unsigned long new_sp, old_sp;

23505

+

23506

+ GET_STACK_POINTER (old_sp);

23507

+ foo(42);

23508

+ GET_STACK_POINTER (new_sp);

23509

+

23510

+ if (old_sp != new_sp)

23511

+ abort ();

23512

+

23513

+ return 0;

23514

+}

23515

+

23516

/* Make sure no FPR saves/restores are emitted. */

23517

-/* { dg-final { scan-assembler-not "std" } } */

23518

-/* { dg-final { scan-assembler-not "ld" } } */

23519

+/* { dg-final { scan-assembler-not "\tstd\t" } } */

23520

+/* { dg-final { scan-assembler-not "\tld\t" } } */

23521

Index: gcc/testsuite/gcc.target/s390/hotpatch-1.c

23522

===================================================================

23523

--- a/src/gcc/testsuite/gcc.target/s390/hotpatch-1.c (.../tags/gcc_4_8_2_release)

23524

+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-1.c (.../branches/gcc-4_8-branch)

23525

@@ -0,0 +1,20 @@

23526

+/* Functional tests for the function hotpatching feature. */

23527

+

23528

+/* { dg-do run } */

23529

+/* { dg-options "-O3 -mzarch -mhotpatch --save-temps" } */

23530

+

23531

+#include <stdio.h>

23532

+

23533

+void hp1(void)

23534

+{

23535

+ printf("hello, world!\n");

23536

+}

23537

+

23538

+int main (void)

23539

+{

23540

+ return 0;

23541

+}

23542

+

23543

+/* Check number of occurences of certain instructions. */

23544

+/* { dg-final { scan-assembler-times "nopr\t%r7" 12 } } */

23545

+/* { dg-final { scan-assembler-times "nop\t0" 1 } } */

23546

Index: gcc/testsuite/gcc.target/s390/hotpatch-2.c

23547

===================================================================

23548

--- a/src/gcc/testsuite/gcc.target/s390/hotpatch-2.c (.../tags/gcc_4_8_2_release)

23549

+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-2.c (.../branches/gcc-4_8-branch)

23550

@@ -0,0 +1,20 @@

23551

+/* Functional tests for the function hotpatching feature. */

23552

+

23553

+/* { dg-do run } */

23554

+/* { dg-options "-O3 -mzarch -mhotpatch=1 --save-temps" } */

23555

+

23556

+#include <stdio.h>

23557

+

23558

+void hp1(void)

23559

+{

23560

+ printf("hello, world!\n");

23561

+}

23562

+

23563

+int main (void)

23564

+{

23565

+ return 0;

23566

+}

23567

+

23568

+/* Check number of occurences of certain instructions. */

23569

+/* { dg-final { scan-assembler-times "nopr\t%r7" 1 } } */

23570

+/* { dg-final { scan-assembler-times "nop\t0" 1 } } */

23571

Index: gcc/testsuite/gcc.target/s390/hotpatch-3.c

23572

===================================================================

23573

--- a/src/gcc/testsuite/gcc.target/s390/hotpatch-3.c (.../tags/gcc_4_8_2_release)

23574

+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-3.c (.../branches/gcc-4_8-branch)

23575

@@ -0,0 +1,20 @@

23576

+/* Functional tests for the function hotpatching feature. */

23577

+

23578

+/* { dg-do run } */

23579

+/* { dg-options "-O3 -mzarch -mhotpatch=0 --save-temps" } */

23580

+

23581

+#include <stdio.h>

23582

+

23583

+void hp1(void)

23584

+{

23585

+ printf("hello, world!\n");

23586

+}

23587

+

23588

+int main (void)

23589

+{

23590

+ return 0;

23591

+}

23592

+

23593

+/* Check number of occurences of certain instructions. */

23594

+/* { dg-final { scan-assembler-not "nopr\t%r7" } } */

23595

+/* { dg-final { scan-assembler-times "nop\t0" 1 } } */

23596

Index: gcc/testsuite/gcc.target/s390/hotpatch-4.c

23597

===================================================================

23598

--- a/src/gcc/testsuite/gcc.target/s390/hotpatch-4.c (.../tags/gcc_4_8_2_release)

23599

+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-4.c (.../branches/gcc-4_8-branch)

23600

@@ -0,0 +1,26 @@

23601

+/* Functional tests for the function hotpatching feature. */

23602

+

23603

+/* { dg-do run } */

23604

+/* { dg-options "-O3 -mzarch -mhotpatch --save-temps" } */

23605

+

23606

+#include <stdio.h>

23607

+

23608

+inline void hp1(void)

23609

+{

23610

+ printf("hello, world!\n");

23611

+}

23612

+

23613

+__attribute__ ((always_inline))

23614

+void hp2(void) /* { dg-warning "always_inline function might not be inlinable" } */

23615

+{

23616

+ printf("hello, world!\n");

23617

+} /* { dg-warning "function 'hp2' with the 'always_inline' attribute is not hotpatchable" } */

23618

+

23619

+int main (void)

23620

+{

23621

+ return 0;

23622

+}

23623

+

23624

+/* Check number of occurences of certain instructions. */

23625

+/* { dg-final { scan-assembler-not "nopr\t%r7" } } */

23626

+/* { dg-final { scan-assembler-not "nop\t0" } } */

23627

Index: gcc/testsuite/gcc.target/s390/hotpatch-5.c

23628

===================================================================

23629

--- a/src/gcc/testsuite/gcc.target/s390/hotpatch-5.c (.../tags/gcc_4_8_2_release)

23630

+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-5.c (.../branches/gcc-4_8-branch)

23631

@@ -0,0 +1,21 @@

23632

+/* Functional tests for the function hotpatching feature. */

23633

+

23634

+/* { dg-do run } */

23635

+/* { dg-options "-O3 -mzarch -mhotpatch --save-temps" } */

23636

+

23637

+#include <stdio.h>

23638

+

23639

+__attribute__ ((hotpatch))

23640

+void hp1(void)

23641

+{

23642

+ printf("hello, world!\n");

23643

+}

23644

+

23645

+int main (void)

23646

+{

23647

+ return 0;

23648

+}

23649

+

23650

+/* Check number of occurences of certain instructions. */

23651

+/* { dg-final { scan-assembler-times "nopr\t%r7" 12 } } */

23652

+/* { dg-final { scan-assembler-times "nop\t0" 1 } } */

23653

Index: gcc/testsuite/gcc.target/s390/htm-nofloat-compile-1.c

23654

===================================================================

23655

--- a/src/gcc/testsuite/gcc.target/s390/htm-nofloat-compile-1.c (.../tags/gcc_4_8_2_release)

23656

+++ b/src/gcc/testsuite/gcc.target/s390/htm-nofloat-compile-1.c (.../branches/gcc-4_8-branch)

23657

@@ -0,0 +1,12 @@

23658

+/* { dg-do compile } */

23659

+/* { dg-options "-O3 -march=zEC12 -mzarch" } */

23660

+

23661

+int

23662

+foo ()

23663

+{

23664

+ __builtin_tbegin_nofloat (0);

23665

+ __builtin_tbegin_retry_nofloat (0, 42);

23666

+}

23667

+/* Make sure no FPR saves/restores are emitted. */

23668

+/* { dg-final { scan-assembler-not "std" } } */

23669

+/* { dg-final { scan-assembler-not "ld" } } */

23670

Index: gcc/testsuite/gcc.target/s390/hotpatch-6.c

23671

===================================================================

23672

--- a/src/gcc/testsuite/gcc.target/s390/hotpatch-6.c (.../tags/gcc_4_8_2_release)

23673

+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-6.c (.../branches/gcc-4_8-branch)

23674

@@ -0,0 +1,21 @@

23675

+/* Functional tests for the function hotpatching feature. */

23676

+

23677

+/* { dg-do run } */

23678

+/* { dg-options "-O3 -mzarch -mhotpatch --save-temps" } */

23679

+

23680

+#include <stdio.h>

23681

+

23682

+__attribute__ ((hotpatch(1)))

23683

+void hp1(void)

23684

+{

23685

+ printf("hello, world!\n");

23686

+}

23687

+

23688

+int main (void)

23689

+{

23690

+ return 0;

23691

+}

23692

+

23693

+/* Check number of occurences of certain instructions. */

23694

+/* { dg-final { scan-assembler-times "nopr\t%r7" 1 } } */

23695

+/* { dg-final { scan-assembler-times "nop\t0" 1 } } */

23696

Index: gcc/testsuite/gcc.target/s390/htm-builtins-1.c

23697

===================================================================

23698

--- a/src/gcc/testsuite/gcc.target/s390/htm-builtins-1.c (.../tags/gcc_4_8_2_release)

23699

+++ b/src/gcc/testsuite/gcc.target/s390/htm-builtins-1.c (.../branches/gcc-4_8-branch)

23700

@@ -0,0 +1,1073 @@

23701

+/* Functional tests of the htm __builtin_... macros. */

23702

+

23703

+/* { dg-do run } */

23704

+/* { dg-require-effective-target htm } */

23705

+/* { dg-options "-O3 -march=zEC12 -mzarch" } */

23706

+

23707

+/* ---------------------------- included header files ---------------------- */

23708

+

23709

+#include <stdio.h>

23710

+#include <string.h>

23711

+#include <stdint.h>

23712

+#include <htmintrin.h>

23713

+

23714

+/* ---------------------------- local definitions -------------------------- */

23715

+

23716

+#define DEFAULT_MAX_REPETITIONS 5

23717

+#define DEFAULT_REQUIRED_QUORUM ((DEFAULT_MAX_REPETITIONS) - 1)

23718

+#define NUM_WARMUP_RUNS 10

23719

+

23720

+/* ---------------------------- local macros ------------------------------- */

23721

+

23722

+#define TEST_DF_REP(name) \

23723

+ { #name, name, DEFAULT_MAX_REPETITIONS, DEFAULT_REQUIRED_QUORUM }

23724

+#define TEST_NO_REP(name) { #name, name, 1, 1 }

23725

+

23726

+/* ---------------------------- local types -------------------------------- */

23727

+

23728

+typedef int (*test_func_t)(void);

23729

+

23730

+typedef struct

23731

+{

23732

+ const char *name;

23733

+ test_func_t test_func;

23734

+ int max_repetitions;

23735

+ int required_quorum;

23736

+} test_table_entry_t;

23737

+

23738

+/* ---------------------------- local variables ---------------------------- */

23739

+

23740

+__attribute__ ((aligned(256))) static struct __htm_tdb local_tdb256;

23741

+static struct __htm_tdb local_tdb;

23742

+static int do_dump_tdb = 0;

23743

+

23744

+/* ---------------------------- exported variables (globals) --------------- */

23745

+

23746

+__attribute__ ((aligned(256))) struct

23747

+{

23748

+ float float_1;

23749

+ float float_2;

23750

+ float float_3;

23751

+} global = { 1.0, 2.5, 0.0 };

23752

+

23753

+__attribute__ ((aligned(256))) struct

23754

+{

23755

+ volatile uint64_t c1;

23756

+ volatile uint64_t c2;

23757

+ volatile uint64_t c3;

23758

+} counters = { 0, 0, 0 };

23759

+

23760

+/* ---------------------------- local helper functions --------------------- */

23761

+

23762

+static void dump_tdb (struct __htm_tdb *tdb)

23763

+{

23764

+ unsigned char *p;

23765

+ int i;

23766

+ int j;

23767

+

23768

+ if (do_dump_tdb == 0)

23769

+ {

23770

+ return;

23771

+ }

23772

+ p = (unsigned char *)tdb;

23773

+ for (i = 0; i < 16; i++)

23774

+ {

23775

+ fprintf (stderr, "0x%02x ", i * 16);

23776

+ for (j = 0; j < 16; j++)

23777

+ {

23778

+ fprintf (stderr, "%02x", (int)p[i * 16 + j]);

23779

+ if (j < 15)

23780

+ {

23781

+ fprintf (stderr, " ");

23782

+ }

23783

+ if (j == 7)

23784

+ {

23785

+ fprintf (stderr, " ");

23786

+ }

23787

+ }

23788

+ fprintf (stderr, "\n");

23789

+ }

23790

+

23791

+ return;

23792

+}

23793

+

23794

+/* ---------------------------- local test functions ----------------------- */

23795

+

23796

+/* Check values of the constants defined in htmintrin.h. */

23797

+static int test_constants (void)

23798

+{

23799

+ if (_HTM_TBEGIN_STARTED != 0)

23800

+ {

23801

+ return 100 * _HTM_TBEGIN_STARTED + 1;

23802

+ }

23803

+ if (_HTM_TBEGIN_INDETERMINATE != 1)

23804

+ {

23805

+ return 100 * _HTM_TBEGIN_INDETERMINATE + 2;

23806

+ }

23807

+ if (_HTM_TBEGIN_TRANSIENT != 2)

23808

+ {

23809

+ return 100 * _HTM_TBEGIN_TRANSIENT + 3;

23810

+ }

23811

+ if (_HTM_TBEGIN_PERSISTENT != 3)

23812

+ {

23813

+ return 100 * _HTM_TBEGIN_PERSISTENT + 4;

23814

+ }

23815

+

23816

+ return 0;

23817

+}

23818

+

23819

+static int test_tbegin_ntstg_tend (void)

23820

+{

23821

+ int rc;

23822

+

23823

+ counters.c1 = 0;

23824

+ counters.c2 = 0;

23825

+ if ((rc = __builtin_tbegin ((void *)0)) == 0)

23826

+ {

23827

+ __builtin_non_tx_store ((uint64_t *)&counters.c1, 1);

23828

+ counters.c2 = 2;

23829

+ rc = __builtin_tend ();

23830

+ if (rc != 0)

23831

+ {

23832

+ return 100 * rc + 5;

23833

+ }

23834

+ if (counters.c1 != 1)

23835

+ {

23836

+ return 100 * counters.c1 + 2;

23837

+ }

23838

+ if (counters.c2 != 2)

23839

+ {

23840

+ return 100 * counters.c2 + 3;

23841

+ }

23842

+ }

23843

+ else

23844

+ {

23845

+ return 100 * rc + 4;

23846

+ }

23847

+

23848

+ return 0;

23849

+}

23850

+

23851

+static int test_tbegin_ntstg_tabort (void)

23852

+{

23853

+ float f;

23854

+

23855

+ counters.c1 = 0;

23856

+ counters.c2 = 0;

23857

+ f = 0;

23858

+ if (__builtin_tbegin ((void *)0) == 0)

23859

+ {

23860

+ __builtin_non_tx_store ((uint64_t *)&counters.c1, 1);

23861

+ counters.c2 = 2;

23862

+ f = 1;

23863

+ __builtin_tabort (256);

23864

+ return 1;

23865

+ }

23866

+ if (counters.c1 != 1)

23867

+ {

23868

+ return 100 * counters.c1 + 2;

23869

+ }

23870

+ if (counters.c2 != 0)

23871

+ {

23872

+ return 100 * counters.c2 + 3;

23873

+ }

23874

+ if (f != 0)

23875

+ {

23876

+ return 100 * f + 4;

23877

+ }

23878

+

23879

+ return 0;

23880

+}

23881

+

23882

+static int test_tbegin_nofloat (void)

23883

+{

23884

+ int rc;

23885

+

23886

+ counters.c1 = 0;

23887

+ counters.c2 = 0;

23888

+ if ((rc = __builtin_tbegin_nofloat ((void *)0)) == 0)

23889

+ {

23890

+ __builtin_non_tx_store ((uint64_t *)&counters.c1, 1);

23891

+ counters.c2 = 2;

23892

+ rc = __builtin_tend ();

23893

+ if (rc != 0)

23894

+ {

23895

+ return 100 * rc + 5;

23896

+ }

23897

+ if (counters.c1 != 1)

23898

+ {

23899

+ return 100 * counters.c1 + 2;

23900

+ }

23901

+ if (counters.c2 != 2)

23902

+ {

23903

+ return 100 * counters.c2 + 3;

23904

+ }

23905

+ }

23906

+ else

23907

+ {

23908

+ return 100 * rc + 4;

23909

+ }

23910

+

23911

+ return 0;

23912

+}

23913

+

23914

+static int test_tbegin_retry (void)

23915

+{

23916

+ int rc;

23917

+

23918

+ counters.c1 = 0;

23919

+ counters.c2 = 0;

23920

+ counters.c3 = 0;

23921

+ if ((rc = __builtin_tbegin_retry ((void *)0, 5)) == 0)

23922

+ {

23923

+ int do_abort;

23924

+

23925

+ do_abort = (counters.c1 == 0) ? 1 : 0;

23926

+ __builtin_non_tx_store (

23927

+ (uint64_t *)&counters.c1, counters.c1 + 1);

23928

+ if (do_abort == 1)

23929

+ {

23930

+ __builtin_tabort (256);

23931

+ }

23932

+ counters.c2 = counters.c2 + 10;

23933

+ __builtin_non_tx_store ((uint64_t *)&counters.c3, 3);

23934

+ rc = __builtin_tend ();

23935

+ if (rc != 0)

23936

+ {

23937

+ return 100 * rc + 5;

23938

+ }

23939

+ if (counters.c1 != 2)

23940

+ {

23941

+ return 100 * counters.c1 + 2;

23942

+ }

23943

+ if (counters.c2 != 10)

23944

+ {

23945

+ return 100 * counters.c2 + 3;

23946

+ }

23947

+ if (counters.c3 != 3)

23948

+ {

23949

+ return 100 * counters.c3 + 6;

23950

+ }

23951

+ }

23952

+ else

23953

+ {

23954

+ return 100 * rc + 4;

23955

+ }

23956

+

23957

+ return 0;

23958

+}

23959

+

23960

+static int test_tbegin_retry_nofloat (void)

23961

+{

23962

+ int rc;

23963

+

23964

+ counters.c1 = 0;

23965

+ counters.c2 = 0;

23966

+ counters.c3 = 0;

23967

+ if ((rc = __builtin_tbegin_retry_nofloat ((void *)0, 5)) == 0)

23968

+ {

23969

+ int do_abort;

23970

+

23971

+ do_abort = (counters.c1 == 0) ? 1 : 0;

23972

+ __builtin_non_tx_store (

23973

+ (uint64_t *)&counters.c1, counters.c1 + 1);

23974

+ if (do_abort == 1)

23975

+ {

23976

+ __builtin_tabort (256);

23977

+ }

23978

+ counters.c2 = counters.c2 + 10;

23979

+ __builtin_non_tx_store ((uint64_t *)&counters.c3, 3);

23980

+ rc = __builtin_tend ();

23981

+ if (rc != 0)

23982

+ {

23983

+ return 100 * rc + 5;

23984

+ }

23985

+ if (counters.c1 != 2)

23986

+ {

23987

+ return 100 * counters.c1 + 2;

23988

+ }

23989

+ if (counters.c2 != 10)

23990

+ {

23991

+ return 100 * counters.c2 + 3;

23992

+ }

23993

+ if (counters.c3 != 3)

23994

+ {

23995

+ return 100 * counters.c3 + 6;

23996

+ }

23997

+ }

23998

+ else

23999

+ {

24000

+ return 100 * rc + 4;

24001

+ }

24002

+

24003

+ return 0;

24004

+}

24005

+

24006

+static int test_tbegin_aborts (void)

24007

+{

24008

+ float f;

24009

+ int rc;

24010

+

24011

+ f = 77;

24012

+ if ((rc = __builtin_tbegin ((void *)0)) == 0)

24013

+ {

24014

+ f = 88;

24015

+ __builtin_tabort (256);

24016

+ return 2;

24017

+ }

24018

+ else if (rc != 2)

24019

+ {

24020

+ return 3;

24021

+ }

24022

+ if (f != 77)

24023

+ {

24024

+ return 4;

24025

+ }

24026

+ f = 66;

24027

+ if ((rc = __builtin_tbegin ((void *)0)) == 0)

24028

+ {

24029

+ f = 99;

24030

+ __builtin_tabort (257);

24031

+ return 5;

24032

+ }

24033

+ else if (rc != 3)

24034

+ {

24035

+ return 100 * rc + 6;

24036

+ }

24037

+ if (f != 66)

24038

+ {

24039

+ return 100 * f + 7;

24040

+ }

24041

+ if ((rc = __builtin_tbegin ((void *)0)) == 0)

24042

+ {

24043

+ global.float_3 = global.float_1 + global.float_2;

24044

+ rc = __builtin_tend ();

24045

+ if (rc != 0)

24046

+ {

24047

+ return 100 * rc + 8;

24048

+ }

24049

+ }

24050

+ else

24051

+ {

24052

+ return 100 * rc + 9;

24053

+ }

24054

+ if (global.float_3 != global.float_1 + global.float_2)

24055

+ {

24056

+ return 100 * rc + 10;

24057

+ }

24058

+

24059

+ return 0;

24060

+}

24061

+

24062

+static __attribute__((noinline)) void indirect_abort(int abort_code)

24063

+{

24064

+ __builtin_tabort (abort_code);

24065

+

24066

+ return;

24067

+}

24068

+

24069

+static int test_tbegin_indirect_aborts (void)

24070

+{

24071

+ float f;

24072

+ int rc;

24073

+

24074

+ f = 77;

24075

+ if ((rc = __builtin_tbegin ((void *)0)) == 0)

24076

+ {

24077

+ f = 88;

24078

+ indirect_abort(256);

24079

+ return 2;

24080

+ }

24081

+ else if (rc != 2)

24082

+ {

24083

+ return 100 * rc + 3;

24084

+ }

24085

+ if (f != 77)

24086

+ {

24087

+ return 100 * rc + 4;

24088

+ }

24089

+ f = 66;

24090

+ if ((rc = __builtin_tbegin ((void *)0)) == 0)

24091

+ {

24092

+ f = 99;

24093

+ indirect_abort(257);

24094

+ return 5;

24095

+ }

24096

+ else if (rc != 3)

24097

+ {

24098

+ return 100 * rc + 6;

24099

+ }

24100

+ if (f != 66)

24101

+ {

24102

+ return 100 * f + 7;

24103

+ }

24104

+

24105

+ return 0;

24106

+}

24107

+

24108

+static int test_tbegin_nofloat_aborts (void)

24109

+{

24110

+ int rc;

24111

+

24112

+ if ((rc = __builtin_tbegin_nofloat ((void *)0)) == 0)

24113

+ {

24114

+ __builtin_tabort (256);

24115

+ return 2;

24116

+ }

24117

+ if ((rc = __builtin_tbegin_nofloat ((void *)0)) == 0)

24118

+ {

24119

+ __builtin_tabort (257);

24120

+ return 1005;

24121

+ }

24122

+ else if (rc != 3)

24123

+ {

24124

+ return 1000 * rc + 6;

24125

+ }

24126

+

24127

+ return 0;

24128

+}

24129

+

24130

+static int test_tbegin_nofloat_indirect_aborts (void)

24131

+{

24132

+ int rc;

24133

+

24134

+ if ((rc = __builtin_tbegin_nofloat ((void *)0)) == 0)

24135

+ {

24136

+ indirect_abort (256);

24137

+ return 2;

24138

+ }

24139

+ if ((rc = __builtin_tbegin_nofloat ((void *)0)) == 0)

24140

+ {

24141

+ indirect_abort (257);

24142

+ return 1005;

24143

+ }

24144

+ else if (rc != 3)

24145

+ {

24146

+ return 1000 * rc + 6;

24147

+ }

24148

+

24149

+ return 0;

24150

+}

24151

+

24152

+static

24153

+int _test_tbegin_retry_aborts (int retries, uint64_t abort_code)

24154

+{

24155

+ int rc;

24156

+

24157

+ counters.c1 = 0;

24158

+ if ((rc = __builtin_tbegin_retry ((void *)0, retries)) == 0)

24159

+ {

24160

+ __builtin_non_tx_store ((uint64_t *)&counters.c1, counters.c1 + 1);

24161

+ __builtin_tabort (abort_code);

24162

+ return 2;

24163

+ }

24164

+ else

24165

+ {

24166

+ if ((abort_code & 1) == 0)

24167

+ {

24168

+ if (rc != 2)

24169

+ {

24170

+ return 100 * rc + 2003;

24171

+ }

24172

+ else if (counters.c1 != (uint64_t)retries + 1)

24173

+ {

24174

+ return 1000 * counters.c1 + 100 * retries + 4;

24175

+ }

24176

+ }

24177

+ else

24178

+ {

24179

+ if (rc != 3)

24180

+ {

24181

+ return 100 * rc + 3005;

24182

+ }

24183

+ else if (counters.c1 != 1)

24184

+ {

24185

+ return 1000 * counters.c1 + 100 * retries + 6;

24186

+ }

24187

+ }

24188

+ }

24189

+

24190

+ return 0;

24191

+}

24192

+

24193

+static int test_tbegin_retry_aborts (void)

24194

+{

24195

+ int rc;

24196

+ int retries;

24197

+

24198

+ for (retries = 1; retries <= 3; retries++)

24199

+ {

24200

+ rc = _test_tbegin_retry_aborts (retries, 256);

24201

+ if (rc != 0)

24202

+ {

24203

+ return 10000 + rc;

24204

+ }

24205

+ }

24206

+ for (retries = 1; retries <= 3; retries++)

24207

+ {

24208

+ rc = _test_tbegin_retry_aborts (retries, 257);

24209

+ if (rc != 0)

24210

+ {

24211

+ return 20000 + rc;

24212

+ }

24213

+ }

24214

+ if ((rc = __builtin_tbegin_retry ((void *)0, 5)) == 0)

24215

+ {

24216

+ global.float_3 = global.float_1 + global.float_2;

24217

+ rc = __builtin_tend ();

24218

+ if (rc != 0)

24219

+ {

24220

+ return 30000 + 100 * rc + 6;

24221

+ }

24222

+ }

24223

+ else

24224

+ {

24225

+ return 30000 + 100 * rc + 7;

24226

+ }

24227

+

24228

+ return 0;

24229

+}

24230

+

24231

+static int _test_tbegin_retry_nofloat_aborts (int retries, uint64_t abort_code)

24232

+{

24233

+ int rc;

24234

+

24235

+ counters.c1 = 0;

24236

+ if ((rc = __builtin_tbegin_retry_nofloat ((void *)0, retries)) == 0)

24237

+ {

24238

+ __builtin_non_tx_store ((uint64_t *)&counters.c1, counters.c1 + 1);

24239

+ __builtin_tabort (abort_code);

24240

+ return 2;

24241

+ }

24242

+ else

24243

+ {

24244

+ if ((abort_code & 1) == 0)

24245

+ {

24246

+ if (rc != 2)

24247

+ {

24248

+ return 100 * rc + 2003;

24249

+ }

24250

+ else if (counters.c1 != (uint64_t)retries + 1)

24251

+ {

24252

+ return 1000 * counters.c1 + 100 * retries + 4;

24253

+ }

24254

+ }

24255

+ else

24256

+ {

24257

+ if (rc != 3)

24258

+ {

24259

+ return 100 * rc + 3005;

24260

+ }

24261

+ else if (counters.c1 != 1)

24262

+ {

24263

+ return 1000 * counters.c1 + 100 * retries + 6;

24264

+ }

24265

+ }

24266

+ }

24267

+

24268

+ return 0;

24269

+}

24270

+

24271

+static int test_tbegin_retry_nofloat_aborts (void)

24272

+{

24273

+ int rc;

24274

+ int retries;

24275

+

24276

+ for (retries = 1; retries <= 3; retries++)

24277

+ {

24278

+ rc = _test_tbegin_retry_nofloat_aborts (retries, 256);

24279

+ if (rc != 0)

24280

+ {

24281

+ return 10 * retries + rc;

24282

+ }

24283

+ }

24284

+ for (retries = 1; retries <= 3; retries++)

24285

+ {

24286

+ rc = _test_tbegin_retry_nofloat_aborts (retries, 257);

24287

+ if (rc != 0)

24288

+ {

24289

+ return 10000 + 10 * retries + rc;

24290

+ }

24291

+ }

24292

+

24293

+ return 0;

24294

+}

24295

+

24296

+static int test_tbegin_tdb (void)

24297

+{

24298

+ int rc;

24299

+

24300

+ local_tdb.format = 0;

24301

+ if ((rc = __builtin_tbegin (&local_tdb)) == 0)

24302

+ {

24303

+ rc = __builtin_tend ();

24304

+ if (rc != 0)

24305

+ {

24306

+ return 100 * rc + 1;

24307

+ }

24308

+ if (local_tdb.format != 0)

24309

+ {

24310

+ dump_tdb (&local_tdb);

24311

+ return 100 * local_tdb.format + 2;

24312

+ }

24313

+ }

24314

+ else

24315

+ {

24316

+ return 100 * rc + 3;

24317

+ }

24318

+ local_tdb.format = 0;

24319

+ if ((rc = __builtin_tbegin (&local_tdb)) == 0)

24320

+ {

24321

+ __builtin_tabort (257);

24322

+ return 4;

24323

+ }

24324

+ else

24325

+ {

24326

+ if (rc != 3)

24327

+ {

24328

+ return 100 * rc + 5;

24329

+ }

24330

+ if (local_tdb.format != 1)

24331

+ {

24332

+ dump_tdb (&local_tdb);

24333

+ return 100 * local_tdb.format + 6;

24334

+ }

24335

+ }

24336

+ local_tdb256.format = 0;

24337

+ if ((rc = __builtin_tbegin (&local_tdb256)) == 0)

24338

+ {

24339

+ rc = __builtin_tend ();

24340

+ if (rc != 0)

24341

+ {

24342

+ return 1100 * rc + 1;

24343

+ }

24344

+ if (local_tdb256.format != 0)

24345

+ {

24346

+ dump_tdb (&local_tdb256);

24347

+ return 1100 * local_tdb256.format + 2;

24348

+ }

24349

+ }

24350

+ else

24351

+ {

24352

+ return 1100 * rc + 3;

24353

+ }

24354

+ local_tdb256.format = 0;

24355

+ if ((rc = __builtin_tbegin (&local_tdb256)) == 0)

24356

+ {

24357

+ __builtin_tabort (257);

24358

+ return 2004;

24359

+ }

24360

+ else

24361

+ {

24362

+ if (rc != 3)

24363

+ {

24364

+ return 2100 * rc + 5;

24365

+ }

24366

+ if (local_tdb256.format != 1)

24367

+ {

24368

+ dump_tdb (&local_tdb256);

24369

+ return 2100 * local_tdb256.format + 6;

24370

+ }

24371

+ }

24372

+

24373

+ return 0;

24374

+}

24375

+

24376

+static int test_tbegin_nofloat_tdb (void)

24377

+{

24378

+ int rc;

24379

+

24380

+ local_tdb.format = 0;

24381

+ if ((rc = __builtin_tbegin_nofloat (&local_tdb)) == 0)

24382

+ {

24383

+ rc = __builtin_tend ();

24384

+ if (rc != 0)

24385

+ {

24386

+ return 100 * rc + 1;

24387

+ }

24388

+ if (local_tdb.format != 0)

24389

+ {

24390

+ dump_tdb (&local_tdb);

24391

+ return 100 * local_tdb.format + 2;

24392

+ }

24393

+ }

24394

+ else

24395

+ {

24396

+ return 3;

24397

+ }

24398

+ local_tdb.format = 0;

24399

+ if ((rc = __builtin_tbegin_nofloat (&local_tdb)) == 0)

24400

+ {

24401

+ __builtin_tabort (257);

24402

+ return 4;

24403

+ }

24404

+ else

24405

+ {

24406

+ if (rc != 3)

24407

+ {

24408

+ return 100 * rc + 5;

24409

+ }

24410

+ if (local_tdb.format != 1)

24411

+ {

24412

+ dump_tdb (&local_tdb);

24413

+ return 100 * local_tdb.format + 6;

24414

+ }

24415

+ }

24416

+ local_tdb256.format = 0;

24417

+ if ((rc = __builtin_tbegin_nofloat (&local_tdb256)) == 0)

24418

+ {

24419

+ rc = __builtin_tend ();

24420

+ if (rc != 0)

24421

+ {

24422

+ return 1100 * rc + 1;

24423

+ }

24424

+ if (local_tdb256.format != 0)

24425

+ {

24426

+ dump_tdb (&local_tdb256);

24427

+ return 1100 * local_tdb256.format + 2;

24428

+ }

24429

+ }

24430

+ else

24431

+ {

24432

+ return 1003;

24433

+ }

24434

+ local_tdb256.format = 0;

24435

+ if ((rc = __builtin_tbegin_nofloat (&local_tdb256)) == 0)

24436

+ {

24437

+ __builtin_tabort (257);

24438

+ return 2004;

24439

+ }

24440

+ else

24441

+ {

24442

+ if (rc != 3)

24443

+ {

24444

+ return 2100 * rc + 5;

24445

+ }

24446

+ if (local_tdb256.format != 1)

24447

+ {

24448

+ dump_tdb (&local_tdb256);

24449

+ return 2100 * local_tdb256.format + 6;

24450

+ }

24451

+ }

24452

+

24453

+ return 0;

24454

+}

24455

+

24456

+static int test_tbegin_retry_tdb (void)

24457

+{

24458

+ int rc;

24459

+

24460

+ local_tdb256.format = 0;

24461

+ if ((rc = __builtin_tbegin_retry (&local_tdb256, 2)) == 0)

24462

+ {

24463

+ rc = __builtin_tend ();

24464

+ if (rc != 0)

24465

+ {

24466

+ return 1100 * rc + 1;

24467

+ }

24468

+ if (local_tdb256.format != 0)

24469

+ {

24470

+ dump_tdb (&local_tdb256);

24471

+ return 1100 * local_tdb256.format + 2;

24472

+ }

24473

+ }

24474

+ else

24475

+ {

24476

+ return 1003;

24477

+ }

24478

+ local_tdb256.format = 0;

24479

+ if ((rc = __builtin_tbegin_retry (&local_tdb256, 2)) == 0)

24480

+ {

24481

+ __builtin_tabort (257);

24482

+ return 2004;

24483

+ }

24484

+ else

24485

+ {

24486

+ if (rc != 3)

24487

+ {

24488

+ return 2100 * rc + 5;

24489

+ }

24490

+ if (local_tdb256.format != 1)

24491

+ {

24492

+ dump_tdb (&local_tdb256);

24493

+ return 2100 * local_tdb256.format + 6;

24494

+ }

24495

+ }

24496

+

24497

+ return 0;

24498

+}

24499

+

24500

+static int test_tbegin_retry_nofloat_tdb (void)

24501

+{

24502

+ int rc;

24503

+

24504

+ local_tdb.format = 0;

24505

+ if ((rc = __builtin_tbegin_retry_nofloat (&local_tdb, 2)) == 0)

24506

+ {

24507

+ rc = __builtin_tend ();

24508

+ if (rc != 0)

24509

+ {

24510

+ return 100 * rc + 1;

24511

+ }

24512

+ if (local_tdb.format != 0)

24513

+ {

24514

+ dump_tdb (&local_tdb);

24515

+ return 100 * local_tdb.format + 2;

24516

+ }

24517

+ }

24518

+ else

24519

+ {

24520

+ return 100 * rc + 3;

24521

+ }

24522

+ local_tdb.format = 0;

24523

+ if ((rc = __builtin_tbegin_retry_nofloat (&local_tdb, 2)) == 0)

24524

+ {

24525

+ __builtin_tabort (257);

24526

+ return 4;

24527

+ }

24528

+ else

24529

+ {

24530

+ if (rc != 3)

24531

+ {

24532

+ return 100 * rc + 5;

24533

+ }

24534

+ if (local_tdb.format != 1)

24535

+ {

24536

+ dump_tdb (&local_tdb);

24537

+ return 100 * local_tdb.format + 6;

24538

+ }

24539

+ }

24540

+ local_tdb256.format = 0;

24541

+ if ((rc = __builtin_tbegin_retry_nofloat (&local_tdb256, 2)) == 0)

24542

+ {

24543

+ rc = __builtin_tend ();

24544

+ if (rc != 0)

24545

+ {

24546

+ return 1100 * rc + 1;

24547

+ }

24548

+ if (local_tdb256.format != 0)

24549

+ {

24550

+ dump_tdb (&local_tdb256);

24551

+ return 1100 * local_tdb256.format + 2;

24552

+ }

24553

+ }

24554

+ else

24555

+ {

24556

+ return 1100 * rc + 3;

24557

+ }

24558

+ local_tdb256.format = 0;

24559

+ if ((rc = __builtin_tbegin_retry_nofloat (&local_tdb256, 2)) == 0)

24560

+ {

24561

+ __builtin_tabort (257);

24562

+ return 2004;

24563

+ }

24564

+ else

24565

+ {

24566

+ if (rc != 3)

24567

+ {

24568

+ return 2100 * rc + 5;

24569

+ }

24570

+ if (local_tdb256.format != 1)

24571

+ {

24572

+ dump_tdb (&local_tdb256);

24573

+ return 2100 * local_tdb256.format + 6;

24574

+ }

24575

+ }

24576

+

24577

+ return 0;

24578

+}

24579

+

24580

+static int test_etnd (void)

24581

+{

24582

+ int rc;

24583

+

24584

+ counters.c1 = 0;

24585

+ counters.c2 = 0;

24586

+ counters.c3 = 0;

24587

+ if ((rc = __builtin_tbegin ((void *)0)) == 0)

24588

+ {

24589

+ counters.c1 = __builtin_tx_nesting_depth ();

24590

+ if (__builtin_tbegin ((void *)0) == 0)

24591

+ {

24592

+ counters.c2 = __builtin_tx_nesting_depth ();

24593

+ if (__builtin_tbegin ((void *)0) == 0)

24594

+ {

24595

+ counters.c3 = __builtin_tx_nesting_depth ();

24596

+ __builtin_tend ();

24597

+ }

24598

+ __builtin_tend ();

24599

+ }

24600

+ __builtin_tend ();

24601

+ }

24602

+ else

24603

+ {

24604

+ return 100 * rc + 1;

24605

+ }

24606

+ if (counters.c1 != 1)

24607

+ {

24608

+ return 100 * counters.c1 + 2;

24609

+ }

24610

+ if (counters.c2 != 2)

24611

+ {

24612

+ return 100 * counters.c2 + 3;

24613

+ }

24614

+ if (counters.c3 != 3)

24615

+ {

24616

+ return 100 * counters.c3 + 4;

24617

+ }

24618

+

24619

+ return 0;

24620

+}

24621

+

24622

+static int test_tbeginc (void)

24623

+{

24624

+ int rc;

24625

+

24626

+ counters.c1 = 0;

24627

+ __builtin_tbeginc ();

24628

+ counters.c1 = 1;

24629

+ rc = __builtin_tend ();

24630

+ if (rc != 0)

24631

+ {

24632

+ return 10000 * rc + 1;

24633

+ }

24634

+ if (counters.c1 != 1)

24635

+ {

24636

+ return 100000 * counters.c1 + 3;

24637

+ }

24638

+

24639

+ return 0;

24640

+}

24641

+

24642

+/* ---------------------------- local testing framework functions ---------- */

24643

+

24644

+static int run_one_test (const test_table_entry_t *test_entry)

24645

+{

24646

+ int do_print_passes;

24647

+ int succeeded;

24648

+ int rc;

24649

+ int i;

24650

+

24651

+ /* Warmup run to get all necessary data and instruction pages into the page

24652

+ * tables. */

24653

+ {

24654

+ int run;

24655

+

24656

+ do_dump_tdb = 0;

24657

+ for (run = 0; run < NUM_WARMUP_RUNS; run++)

24658

+ {

24659

+ test_entry->test_func ();

24660

+ }

24661

+ do_dump_tdb = 1;

24662

+ }

24663

+ do_print_passes = (

24664

+ test_entry->required_quorum != 1 ||

24665

+ test_entry->max_repetitions != 1);

24666

+ printf ("RRR RUN %s\n", test_entry->name);

24667

+ if (do_print_passes == 1)

24668

+ {

24669

+ printf (

24670

+ " (requires %d successful out of %d runs)\n",

24671

+ test_entry->required_quorum,

24672

+ test_entry->max_repetitions);

24673

+ }

24674

+ succeeded = 0;

24675

+ rc = 0;

24676

+ for (rc = 0, i = 0; i < test_entry->max_repetitions; i++)

24677

+ {

24678

+ if (do_print_passes == 1)

24679

+ {

24680

+ if (i == 0)

24681

+ {

24682

+ printf (" ");

24683

+ }

24684

+ else

24685

+ {

24686

+ printf (",");

24687

+ }

24688

+ }

24689

+ rc = test_entry->test_func ();

24690

+ if (rc == 0)

24691

+ {

24692

+ if (do_print_passes == 1)

24693

+ {

24694

+ printf (" success");

24695

+ }

24696

+ succeeded++;

24697

+ if (succeeded >= test_entry->required_quorum)

24698

+ {

24699

+ break;

24700

+ }

24701

+ }

24702

+ else

24703

+ {

24704

+ printf (" failed (rc = %d)", rc);

24705

+ }

24706

+ }

24707

+ if (do_print_passes == 1 || rc != 0)

24708

+ {

24709

+ printf ("\n");

24710

+ }

24711

+ if (succeeded >= test_entry->required_quorum)

24712

+ {

24713

+ printf ("+++ OK %s\n", test_entry->name);

24714

+

24715

+ return 0;

24716

+ }

24717

+ else

24718

+ {

24719

+ printf ("--- FAIL %s\n", test_entry->name);

24720

+

24721

+ return (rc != 0) ? rc : -1;

24722

+ }

24723

+}

24724

+

24725

+static int run_all_tests (const test_table_entry_t *test_table)

24726

+{

24727

+ const test_table_entry_t *test;

24728

+ int rc;

24729

+

24730

+ for (

24731

+ rc = 0, test = &test_table[0];

24732

+ test->test_func != NULL && rc == 0; test++)

24733

+ {

24734

+ rc = run_one_test (test);

24735

+ }

24736

+

24737

+ return rc;

24738

+}

24739

+

24740

+/* ---------------------------- interface functions ------------------------ */

24741

+

24742

+int main (void)

24743

+{

24744

+ const test_table_entry_t test_table[] = {

24745

+ TEST_NO_REP (test_constants),

24746

+ TEST_DF_REP (test_tbegin_ntstg_tend),

24747

+ TEST_DF_REP (test_tbegin_ntstg_tabort),

24748

+ TEST_DF_REP (test_tbegin_nofloat),

24749

+ TEST_NO_REP (test_tbegin_retry),

24750

+ TEST_NO_REP (test_tbegin_retry_nofloat),

24751

+ TEST_DF_REP (test_tbegin_aborts),

24752

+ TEST_DF_REP (test_tbegin_indirect_aborts),

24753

+ TEST_DF_REP (test_tbegin_nofloat_aborts),

24754

+ TEST_DF_REP (test_tbegin_nofloat_indirect_aborts),

24755

+ TEST_NO_REP (test_tbegin_retry_aborts),

24756

+ TEST_NO_REP (test_tbegin_retry_nofloat_aborts),

24757

+ TEST_DF_REP (test_tbegin_tdb),

24758

+ TEST_DF_REP (test_tbegin_nofloat_tdb),

24759

+ TEST_NO_REP (test_tbegin_retry_tdb),

24760

+ TEST_NO_REP (test_tbegin_retry_nofloat_tdb),

24761

+ TEST_DF_REP (test_etnd),

24762

+ TEST_DF_REP (test_tbeginc),

24763

+ { (void *)0, 0, 0 }

24764

+ };

24765

+

24766

+ {

24767

+ int rc;

24768

+

24769

+ rc = run_all_tests (test_table);

24770

+

24771

+ return rc;

24772

+ }

24773

+}

24774

Index: gcc/testsuite/gcc.target/s390/hotpatch-7.c

24775

===================================================================

24776

--- a/src/gcc/testsuite/gcc.target/s390/hotpatch-7.c (.../tags/gcc_4_8_2_release)

24777

+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-7.c (.../branches/gcc-4_8-branch)

24778

@@ -0,0 +1,21 @@

24779

+/* Functional tests for the function hotpatching feature. */

24780

+

24781

+/* { dg-do run } */

24782

+/* { dg-options "-O3 -mzarch -mhotpatch --save-temps" } */

24783

+

24784

+#include <stdio.h>

24785

+

24786

+__attribute__ ((hotpatch(0)))

24787

+void hp1(void)

24788

+{

24789

+ printf("hello, world!\n");

24790

+}

24791

+

24792

+int main (void)

24793

+{

24794

+ return 0;

24795

+}

24796

+

24797

+/* Check number of occurences of certain instructions. */

24798

+/* { dg-final { scan-assembler-not "nopr\t%r7" } } */

24799

+/* { dg-final { scan-assembler-times "nop\t0" 1 } } */

24800

Index: gcc/testsuite/gcc.target/s390/htm-builtins-2.c

24801

===================================================================

24802

--- a/src/gcc/testsuite/gcc.target/s390/htm-builtins-2.c (.../tags/gcc_4_8_2_release)

24803

+++ b/src/gcc/testsuite/gcc.target/s390/htm-builtins-2.c (.../branches/gcc-4_8-branch)

24804

@@ -0,0 +1,682 @@

24805

+/* Functional tests of the htm __TM_... macros. */

24806

+

24807

+/* { dg-do run } */

24808

+/* { dg-require-effective-target htm } */

24809

+/* { dg-options "-O3 -march=zEC12 -mzarch" } */

24810

+

24811

+/* ---------------------------- included header files ---------------------- */

24812

+

24813

+#include <stdio.h>

24814

+#include <string.h>

24815

+#include <inttypes.h>

24816

+#include <htmxlintrin.h>

24817

+

24818

+/* ---------------------------- local definitions -------------------------- */

24819

+

24820

+#define DEFAULT_MAX_REPETITIONS 5

24821

+#define DEFAULT_REQUIRED_QUORUM ((DEFAULT_MAX_REPETITIONS) - 1)

24822

+#define DEFAULT_ABORT_ADDRESS (0x12345678u)

24823

+

24824

+/* ---------------------------- local macros ------------------------------- */

24825

+

24826

+#define TEST_DF_REP(name) \

24827

+ { #name, name, DEFAULT_MAX_REPETITIONS, DEFAULT_REQUIRED_QUORUM }

24828

+#define TEST_NO_REP(name) { #name, name, 1, 1 }

24829

+

24830

+/* ---------------------------- local types -------------------------------- */

24831

+

24832

+typedef int (*test_func_t)(void);

24833

+

24834

+typedef struct

24835

+{

24836

+ const char *name;

24837

+ test_func_t test_func;

24838

+ int max_repetitions;

24839

+ int required_quorum;

24840

+} test_table_entry_t;

24841

+

24842

+typedef enum

24843

+{

24844

+ ABORT_T_SYSTEM = 0,

24845

+ ABORT_T_USER = 1,

24846

+} abort_user_t;

24847

+

24848

+typedef enum

24849

+{

24850

+ ABORT_T_NONE = 0,

24851

+ ABORT_T_ILLEGAL,

24852

+ ABORT_T_FOOTPRINT_EXCEEDED,

24853

+ ABORT_T_NESTED_TOO_DEEP,

24854

+ ABORT_T_CONFLICT,

24855

+

24856

+ ABORT_T_INVALID_ABORT_CODE

24857

+} abort_t;

24858

+

24859

+/* ---------------------------- local variables ---------------------------- */

24860

+

24861

+__attribute__ ((aligned(256))) static struct __htm_tdb local_tdb256;

24862

+static struct __htm_tdb local_tdb;

24863

+

24864

+static abort_t const abort_classes[] =

24865

+{

24866

+ ABORT_T_INVALID_ABORT_CODE,

24867

+ ABORT_T_NONE,

24868

+ ABORT_T_NONE,

24869

+ ABORT_T_NONE,

24870

+

24871

+ ABORT_T_ILLEGAL,

24872

+ ABORT_T_NONE,

24873

+ ABORT_T_NONE,

24874

+ ABORT_T_FOOTPRINT_EXCEEDED,

24875

+

24876

+ ABORT_T_FOOTPRINT_EXCEEDED,

24877

+ ABORT_T_CONFLICT,

24878

+ ABORT_T_CONFLICT,

24879

+ ABORT_T_ILLEGAL,

24880

+

24881

+ ABORT_T_NONE,

24882

+ ABORT_T_NESTED_TOO_DEEP,

24883

+ ABORT_T_NONE,

24884

+ ABORT_T_NONE,

24885

+

24886

+ ABORT_T_NONE

24887

+};

24888

+

24889

+static size_t num_abort_classes = sizeof(abort_classes) / sizeof(abort_t);

24890

+

24891

+/* ---------------------------- exported variables (globals) --------------- */

24892

+

24893

+int global_int = 0;

24894

+uint64_t global_u64 = 0;

24895

+float global_float_1 = 1.0;

24896

+float global_float_2 = 2.5;

24897

+float global_float_3 = 0.0;

24898

+__attribute__ ((aligned(256))) struct

24899

+{

24900

+ volatile uint64_t c1;

24901

+ volatile uint64_t c2;

24902

+ volatile uint64_t c3;

24903

+} counters = { 0, 0, 0 };

24904

+

24905

+/* ---------------------------- local helper functions --------------------- */

24906

+

24907

+static void dump_tdb(struct __htm_tdb *tdb)

24908

+{

24909

+ unsigned char *p;

24910

+ int i;

24911

+ int j;

24912

+

24913

+ p = (unsigned char *)tdb;

24914

+ for (i = 0; i < 16; i++)

24915

+ {

24916

+ fprintf(stderr, "0x%02x ", i * 16);

24917

+ for (j = 0; j < 16; j++)

24918

+ {

24919

+ fprintf(stderr, "%02x", (int)p[i * 16 + j]);

24920

+ if (j < 15)

24921

+ {

24922

+ fprintf(stderr, " ");

24923

+ }

24924

+ if (j == 7)

24925

+ {

24926

+ fprintf(stderr, " ");

24927

+ }

24928

+ }

24929

+ fprintf(stderr, "\n");

24930

+ }

24931

+

24932

+ return;

24933

+}

24934

+

24935

+static void make_fake_tdb(struct __htm_tdb *tdb)

24936

+{

24937

+ memset(tdb, 0, sizeof(*tdb));

24938

+ tdb->format = 1;

24939

+ tdb->nesting_depth = 1;

24940

+ tdb->atia = DEFAULT_ABORT_ADDRESS;

24941

+ tdb->abort_code = 11;

24942

+

24943

+ return;

24944

+}

24945

+

24946

+static int check_abort_code_in_tdb(struct __htm_tdb *tdb, uint64_t abort_code)

24947

+{

24948

+ long expect_rc;

24949

+ long rc;

24950

+

24951

+ if (abort_code != 0)

24952

+ {

24953

+ long addr;

24954

+

24955

+ addr = __TM_failure_address(&local_tdb);

24956

+ if (addr != DEFAULT_ABORT_ADDRESS)

24957

+ {

24958

+ return 11;

24959

+ }

24960

+ }

24961

+ {

24962

+ long long tdb_abort_code;

24963

+

24964

+ tdb_abort_code = __TM_failure_code(tdb);

24965

+ if ((uint64_t)tdb_abort_code != abort_code)

24966

+ {

24967

+ fprintf(

24968

+ stderr, "tm_ac %" PRIu64 ", ac %" PRIu64

24969

+ ", tdb_ac %" PRIu64 "\n",

24970

+ (uint64_t)tdb_abort_code, abort_code,

24971

+ (uint64_t)tdb->abort_code);

24972

+ return 10;

24973

+ }

24974

+ }

24975

+ expect_rc = (abort_code >= 256) ? 1 : 0;

24976

+ rc = __TM_is_user_abort(tdb);

24977

+ if (rc != expect_rc)

24978

+ {

24979

+ fprintf(stderr, "rc %ld, expect_rc %ld\n", rc, expect_rc);

24980

+ return 1;

24981

+ }

24982

+ {

24983

+ unsigned char code;

24984

+

24985

+ code = 0xffu;

24986

+ rc = __TM_is_named_user_abort(tdb, &code);

24987

+ if (rc != expect_rc)

24988

+ {

24989

+ fprintf(

24990

+ stderr, "rc %ld, expect_rc %ld\n", rc,

24991

+ expect_rc);

24992

+ return 2;

24993

+ }

24994

+ if (expect_rc == 1 && code != abort_code - 256)

24995

+ {

24996

+ return 3;

24997

+ }

24998

+ }

24999

+ if (abort_code > (uint64_t)num_abort_classes)

25000

+ {

25001

+ abort_code = (uint64_t)num_abort_classes;

25002

+ }

25003

+ expect_rc = (abort_classes[abort_code] == ABORT_T_ILLEGAL) ? 1 : 0;

25004

+ rc = __TM_is_illegal(tdb);

25005

+ if (rc != expect_rc)

25006

+ {

25007

+ dump_tdb(tdb);

25008

+ fprintf(stderr, "rc %ld, expect_rc %ld\n", rc, expect_rc);

25009

+ return 4;

25010

+ }

25011

+ expect_rc =

25012

+ (abort_classes[abort_code] == ABORT_T_FOOTPRINT_EXCEEDED) ?

25013

+ 1 : 0;

25014

+ rc = __TM_is_footprint_exceeded(tdb);

25015

+ if (rc != expect_rc)

25016

+ {

25017

+ dump_tdb(tdb);

25018

+ fprintf(stderr, "rc %ld, expect_rc %ld\n", rc, expect_rc);

25019

+ return 5;

25020

+ }

25021

+ expect_rc =

25022

+ (abort_classes[abort_code] == ABORT_T_NESTED_TOO_DEEP) ? 1 : 0;

25023

+ rc = __TM_is_nested_too_deep(tdb);

25024

+ if (rc != expect_rc)

25025

+ {

25026

+ dump_tdb(tdb);

25027

+ fprintf(stderr, "rc %ld, expect_rc %ld\n", rc, expect_rc);

25028

+ return 6;

25029

+ }

25030

+ expect_rc = (abort_classes[abort_code] == ABORT_T_CONFLICT) ? 1 : 0;

25031

+ rc = __TM_is_conflict(tdb);

25032

+ if (rc != expect_rc)

25033

+ {

25034

+ dump_tdb(tdb);

25035

+ fprintf(stderr, "rc %ld, expect_rc %ld\n", rc, expect_rc);

25036

+ return 7;

25037

+ }

25038

+

25039

+ return 0;

25040

+}

25041

+

25042

+/* ---------------------------- local test functions ----------------------- */

25043

+

25044

+/* Not a test; make sure that the involved global cachelines are reserved for

25045

+ * writing. */

25046

+static int init_cache(void)

25047

+{

25048

+ make_fake_tdb(&local_tdb);

25049

+ make_fake_tdb(&local_tdb256);

25050

+ global_int = 0;

25051

+ global_u64 = 0;

25052

+ global_float_1 = 1.0;

25053

+ global_float_2 = 2.5;

25054

+ global_float_3 = 0.0;

25055

+ counters.c1 = 0;

25056

+ counters.c2 = 0;

25057

+ counters.c3 = 0;

25058

+

25059

+ return 0;

25060

+}

25061

+

25062

+static int test_abort_classification(void)

25063

+{

25064

+ int i;

25065

+

25066

+ make_fake_tdb(&local_tdb);

25067

+ for (i = 0; i <= 256; i++)

25068

+ {

25069

+ int rc;

25070

+

25071

+ local_tdb.abort_code = (uint64_t)i;

25072

+ rc = check_abort_code_in_tdb(&local_tdb, (uint64_t)i);

25073

+ if (rc != 0)

25074

+ {

25075

+ return 100 * i + rc;

25076

+ }

25077

+ }

25078

+

25079

+ return 0;

25080

+}

25081

+

25082

+static int test_cc_classification(void)

25083

+{

25084

+ long rc;

25085

+

25086

+ rc = __TM_is_failure_persistent(0);

25087

+ if (rc != 0)

25088

+ {

25089

+ return 1;

25090

+ }

25091

+ rc = __TM_is_failure_persistent(1);

25092

+ if (rc != 0)

25093

+ {

25094

+ return 2;

25095

+ }

25096

+ rc = __TM_is_failure_persistent(2);

25097

+ if (rc != 0)

25098

+ {

25099

+ return 3;

25100

+ }

25101

+ rc = __TM_is_failure_persistent(3);

25102

+ if (rc != 1)

25103

+ {

25104

+ return 4;

25105

+ }

25106

+

25107

+ return 0;

25108

+}

25109

+

25110

+static int test_tbegin_ntstg_tend(void)

25111

+{

25112

+ long rc;

25113

+

25114

+ counters.c1 = 0;

25115

+ counters.c2 = 0;

25116

+ if ((rc = __TM_simple_begin()) == 0)

25117

+ {

25118

+ __TM_non_transactional_store((uint64_t *)&counters.c1, 1);

25119

+ counters.c2 = 2;

25120

+ rc = __TM_end();

25121

+ if (rc != 0)

25122

+ {

25123

+ return 100 * rc + 5;

25124

+ }

25125

+ if (counters.c1 != 1)

25126

+ {

25127

+ return 100 * counters.c1 + 2;

25128

+ }

25129

+ if (counters.c2 != 2)

25130

+ {

25131

+ return 100 * counters.c2 + 3;

25132

+ }

25133

+ }

25134

+ else

25135

+ {

25136

+ return 100 * rc + 4;

25137

+ }

25138

+

25139

+ return 0;

25140

+}

25141

+

25142

+static int test_tbegin_ntstg_tabort(void)

25143

+{

25144

+ register float f;

25145

+

25146

+ counters.c1 = 0;

25147

+ counters.c2 = 0;

25148

+ f = 0;

25149

+ if (__TM_simple_begin() == 0)

25150

+ {

25151

+ __TM_non_transactional_store((uint64_t *)&counters.c1, 1);

25152

+ counters.c2 = 2;

25153

+ f = 1;

25154

+ __TM_named_abort(0);

25155

+ return 1;

25156

+ }

25157

+ if (counters.c1 != 1)

25158

+ {

25159

+ return 100 * counters.c1 + 2;

25160

+ }

25161

+ if (counters.c2 != 0)

25162

+ {

25163

+ return 100 * counters.c2 + 3;

25164

+ }

25165

+ if (f != 0)

25166

+ {

25167

+ return 100 * f + 4;

25168

+ }

25169

+

25170

+ return 0;

25171

+}

25172

+

25173

+static int test_tbegin_aborts(void)

25174

+{

25175

+ float f;

25176

+ long rc;

25177

+

25178

+ f = 77;

25179

+ if ((rc = __TM_simple_begin()) == 0)

25180

+ {

25181

+ f = 88;

25182

+ __TM_abort();

25183

+ return 2;

25184

+ }

25185

+ else if (rc != 2)

25186

+ {

25187

+ return 3;

25188

+ }

25189

+ if (f != 77)

25190

+ {

25191

+ return 4;

25192

+ }

25193

+ f = 66;

25194

+ if ((rc = __TM_simple_begin()) == 0)

25195

+ {

25196

+ f = 99;

25197

+ __TM_named_abort(3);

25198

+ return 5;

25199

+ }

25200

+ else if (rc != 3)

25201

+ {

25202

+ return 100 * rc + 6;

25203

+ }

25204

+ if (f != 66)

25205

+ {

25206

+ return 100 * f + 7;

25207

+ }

25208

+ if ((rc = __TM_simple_begin()) == 0)

25209

+ {

25210

+ global_float_3 = global_float_1 + global_float_2;

25211

+ rc = __TM_end();

25212

+ if (rc != 0)

25213

+ {

25214

+ return 100 * rc + 8;

25215

+ }

25216

+ }

25217

+ else

25218

+ {

25219

+ return 100 * rc + 9;

25220

+ }

25221

+ if (global_float_3 != global_float_1 + global_float_2)

25222

+ {

25223

+ return 100 * rc + 10;

25224

+ }

25225

+

25226

+ return 0;

25227

+}

25228

+

25229

+static int test_tbegin_tdb(void)

25230

+{

25231

+ long rc;

25232

+

25233

+ local_tdb.format = 0;

25234

+ if ((rc = __TM_begin(&local_tdb)) == 0)

25235

+ {

25236

+ rc = __TM_end();

25237

+ if (rc != 0)

25238

+ {

25239

+ return 100 * rc + 1;

25240

+ }

25241

+ if (local_tdb.format != 0)

25242

+ {

25243

+ dump_tdb(&local_tdb);

25244

+ return 100 * local_tdb.format + 2;

25245

+ }

25246

+ }

25247

+ else

25248

+ {

25249

+ return 100 * rc + 3;

25250

+ }

25251

+ local_tdb.format = 0;

25252

+ if ((rc = __TM_begin(&local_tdb)) == 0)

25253

+ {

25254

+ __TM_named_abort(1);

25255

+ return 4;

25256

+ }

25257

+ else

25258

+ {

25259

+ if (rc != 3)

25260

+ {

25261

+ return 100 * rc + 5;

25262

+ }

25263

+ if (local_tdb.format != 1)

25264

+ {

25265

+ dump_tdb(&local_tdb);

25266

+ return 100 * local_tdb.format + 6;

25267

+ }

25268

+ }

25269

+ local_tdb256.format = 0;

25270

+ if ((rc = __TM_begin(&local_tdb256)) == 0)

25271

+ {

25272

+ rc = __TM_end();

25273

+ if (rc != 0)

25274

+ {

25275

+ return 1100 * rc + 1;

25276

+ }

25277

+ if (local_tdb256.format != 0)

25278

+ {

25279

+ dump_tdb(&local_tdb256);

25280

+ return 1100 * local_tdb256.format + 2;

25281

+ }

25282

+ }

25283

+ else

25284

+ {

25285

+ return 1100 * rc + 3;

25286

+ }

25287

+#if 1 /*!!!does not work*/

25288

+ local_tdb256.format = 0;

25289

+ if ((rc = __TM_begin(&local_tdb256)) == 0)

25290

+ {

25291

+ __TM_named_abort(1);

25292

+ return 2004;

25293

+ }

25294

+ else

25295

+ {

25296

+ if (rc != 3)

25297

+ {

25298

+ return 2100 * rc + 5;

25299

+ }

25300

+ if (local_tdb256.format != 1)

25301

+ {

25302

+ dump_tdb(&local_tdb256);

25303

+ return 2100 * local_tdb256.format + 6;

25304

+ }

25305

+ }

25306

+#endif

25307

+

25308

+ return 0;

25309

+}

25310

+

25311

+static int test_etnd(void)

25312

+{

25313

+ long rc;

25314

+

25315

+ {

25316

+ long nd;

25317

+

25318

+ make_fake_tdb(&local_tdb);

25319

+ local_tdb.nesting_depth = 0;

25320

+ nd = __TM_nesting_depth(&local_tdb);

25321

+ if (nd != 0)

25322

+ {

25323

+ return 1;

25324

+ }

25325

+ local_tdb.nesting_depth = 7;

25326

+ nd = __TM_nesting_depth(&local_tdb);

25327

+ if (nd != 7)

25328

+ {

25329

+ return 7;

25330

+ }

25331

+ local_tdb.format = 0;

25332

+ nd = __TM_nesting_depth(&local_tdb);

25333

+ if (nd != 0)

25334

+ {

25335

+ return 2;

25336

+ }

25337

+ }

25338

+ counters.c1 = 0;

25339

+ counters.c1 = 0;

25340

+ counters.c2 = 0;

25341

+ counters.c3 = 0;

25342

+ if ((rc = __TM_simple_begin()) == 0)

25343

+ {

25344

+ counters.c1 = __TM_nesting_depth(0);

25345

+ if (__TM_simple_begin() == 0)

25346

+ {

25347

+ counters.c2 = __TM_nesting_depth(0);

25348

+ if (__TM_simple_begin() == 0)

25349

+ {

25350

+ counters.c3 = __TM_nesting_depth(0);

25351

+ __TM_end();

25352

+ }

25353

+ __TM_end();

25354

+ }

25355

+ __TM_end();

25356

+ }

25357

+ else

25358

+ {

25359

+ return 100 * rc + 1;

25360

+ }

25361

+ if (counters.c1 != 1)

25362

+ {

25363

+ return 100 * counters.c1 + 2;

25364

+ }

25365

+ if (counters.c2 != 2)

25366

+ {

25367

+ return 100 * counters.c2 + 3;

25368

+ }

25369

+ if (counters.c3 != 3)

25370

+ {

25371

+ return 100 * counters.c3 + 4;

25372

+ }

25373

+

25374

+ return 0;

25375

+}

25376

+

25377

+/* ---------------------------- local testing framework functions ---------- */

25378

+

25379

+static int run_one_test(const test_table_entry_t *test_entry)

25380

+{

25381

+ int do_print_passes;

25382

+ int succeeded;

25383

+ int rc;

25384

+ int i;

25385

+

25386

+ do_print_passes = (

25387

+ test_entry->required_quorum != 1 ||

25388

+ test_entry->max_repetitions != 1);

25389

+ printf("RRR RUN %s\n", test_entry->name);

25390

+ if (do_print_passes == 1)

25391

+ {

25392

+ printf(

25393

+ " (requires %d successful out of %d runs)\n",

25394

+ test_entry->required_quorum,

25395

+ test_entry->max_repetitions);

25396

+ }

25397

+ succeeded = 0;

25398

+ rc = 0;

25399

+ for (rc = 0, i = 0; i < test_entry->max_repetitions; i++)

25400

+ {

25401

+ if (do_print_passes == 1)

25402

+ {

25403

+ if (i == 0)

25404

+ {

25405

+ printf(" ");

25406

+ }

25407

+ else

25408

+ {

25409

+ printf(",");

25410

+ }

25411

+ }

25412

+ rc = test_entry->test_func();

25413

+ if (rc == 0)

25414

+ {

25415

+ if (do_print_passes == 1)

25416

+ {

25417

+ printf(" success");

25418

+ }

25419

+ succeeded++;

25420

+ if (succeeded >= test_entry->required_quorum)

25421

+ {

25422

+ break;

25423

+ }

25424

+ }

25425

+ else

25426

+ {

25427

+ printf(" failed (rc = %d)", rc);

25428

+ }

25429

+ }

25430

+ if (do_print_passes == 1 || rc != 0)

25431

+ {

25432

+ printf("\n");

25433

+ }

25434

+ if (succeeded >= test_entry->required_quorum)

25435

+ {

25436

+ printf("+++ OK %s\n", test_entry->name);

25437

+

25438

+ return 0;

25439

+ }

25440

+ else

25441

+ {

25442

+ printf("--- FAIL %s\n", test_entry->name);

25443

+

25444

+ return (rc != 0) ? rc : -1;

25445

+ }

25446

+}

25447

+

25448

+static int run_all_tests(const test_table_entry_t *test_table)

25449

+{

25450

+ const test_table_entry_t *test;

25451

+ int rc;

25452

+

25453

+ for (

25454

+ rc = 0, test = &test_table[0];

25455

+ test->test_func != NULL && rc == 0; test++)

25456

+ {

25457

+ rc = run_one_test(test);

25458

+ }

25459

+

25460

+ return rc;

25461

+}

25462

+

25463

+/* ---------------------------- interface functions ------------------------ */

25464

+

25465

+int main(void)

25466

+{

25467

+ const test_table_entry_t test_table[] = {

25468

+ TEST_NO_REP(init_cache),

25469

+ TEST_NO_REP(test_abort_classification),

25470

+ TEST_NO_REP(test_cc_classification),

25471

+ TEST_DF_REP(test_tbegin_ntstg_tend),

25472

+ TEST_DF_REP(test_tbegin_ntstg_tabort),

25473

+ TEST_DF_REP(test_tbegin_aborts),

25474

+ TEST_DF_REP(test_tbegin_tdb),

25475

+ TEST_DF_REP(test_etnd),

25476

+ { (void *)0, 0, 0 }

25477

+ };

25478

+

25479

+ {

25480

+ int rc;

25481

+

25482

+ rc = run_all_tests(test_table);

25483

+

25484

+ return rc;

25485

+ }

25486

+}

25487

Index: gcc/testsuite/gcc.target/s390/hotpatch-8.c

25488

===================================================================

25489

--- a/src/gcc/testsuite/gcc.target/s390/hotpatch-8.c (.../tags/gcc_4_8_2_release)

25490

+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-8.c (.../branches/gcc-4_8-branch)

25491

@@ -0,0 +1,28 @@

25492

+/* Functional tests for the function hotpatching feature. */

25493

+

25494

+/* { dg-do run } */

25495

+/* { dg-options "-O3 -mzarch -mhotpatch --save-temps" } */

25496

+

25497

+#include <stdio.h>

25498

+

25499

+__attribute__ ((hotpatch))

25500

+inline void hp1(void)

25501

+{

25502

+ printf("hello, world!\n");

25503

+}

25504

+

25505

+__attribute__ ((hotpatch))

25506

+__attribute__ ((always_inline))

25507

+void hp2(void) /* { dg-warning "always_inline function might not be inlinable" } */

25508

+{

25509

+ printf("hello, world!\n");

25510

+} /* { dg-warning "function 'hp2' with the 'always_inline' attribute is not hotpatchable" } */

25511

+

25512

+int main (void)

25513

+{

25514

+ return 0;

25515

+}

25516

+

25517

+/* Check number of occurences of certain instructions. */

25518

+/* { dg-final { scan-assembler-not "nopr\t%r7" } } */

25519

+/* { dg-final { scan-assembler-not "nop\t0" } } */

25520

Index: gcc/testsuite/gcc.target/s390/hotpatch-9.c

25521

===================================================================

25522

--- a/src/gcc/testsuite/gcc.target/s390/hotpatch-9.c (.../tags/gcc_4_8_2_release)

25523

+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-9.c (.../branches/gcc-4_8-branch)

25524

@@ -0,0 +1,21 @@

25525

+/* Functional tests for the function hotpatching feature. */

25526

+

25527

+/* { dg-do run } */

25528

+/* { dg-options "-O3 -mzarch -mhotpatch=1 --save-temps" } */

25529

+

25530

+#include <stdio.h>

25531

+

25532

+__attribute__ ((hotpatch(2)))

25533

+void hp1(void)

25534

+{

25535

+ printf("hello, world!\n");

25536

+}

25537

+

25538

+int main (void)

25539

+{

25540

+ return 0;

25541

+}

25542

+

25543

+/* Check number of occurences of certain instructions. */

25544

+/* { dg-final { scan-assembler-times "nopr\t%r7" 2 } } */

25545

+/* { dg-final { scan-assembler-times "nop\t0" 1 } } */

25546

Index: gcc/testsuite/gcc.target/s390/hotpatch-10.c

25547

===================================================================

25548

--- a/src/gcc/testsuite/gcc.target/s390/hotpatch-10.c (.../tags/gcc_4_8_2_release)

25549

+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-10.c (.../branches/gcc-4_8-branch)

25550

@@ -0,0 +1,21 @@

25551

+/* Functional tests for the function hotpatching feature. */

25552

+

25553

+/* { dg-do run } */

25554

+/* { dg-options "-O3 -mzarch -mno-hotpatch --save-temps" } */

25555

+

25556

+#include <stdio.h>

25557

+

25558

+__attribute__ ((hotpatch(2)))

25559

+void hp1(void)

25560

+{

25561

+ printf("hello, world!\n");

25562

+}

25563

+

25564

+int main (void)

25565

+{

25566

+ return 0;

25567

+}

25568

+

25569

+/* Check number of occurences of certain instructions. */

25570

+/* { dg-final { scan-assembler-times "nopr\t%r7" 2 } } */

25571

+/* { dg-final { scan-assembler-times "nop\t0" 1 } } */

25572

Index: gcc/testsuite/gcc.target/s390/hotpatch-11.c

25573

===================================================================

25574

--- a/src/gcc/testsuite/gcc.target/s390/hotpatch-11.c (.../tags/gcc_4_8_2_release)

25575

+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-11.c (.../branches/gcc-4_8-branch)

25576

@@ -0,0 +1,20 @@

25577

+/* Functional tests for the function hotpatching feature. */

25578

+

25579

+/* { dg-do run } */

25580

+/* { dg-options "-O3 -mzarch -mhotpatch -mno-hotpatch --save-temps" } */

25581

+

25582

+#include <stdio.h>

25583

+

25584

+void hp1(void)

25585

+{

25586

+ printf("hello, world!\n");

25587

+}

25588

+

25589

+int main (void)

25590

+{

25591

+ return 0;

25592

+}

25593

+

25594

+/* Check number of occurences of certain instructions. */

25595

+/* { dg-final { scan-assembler-not "nopr\t%r7" } } */

25596

+/* { dg-final { scan-assembler-not "nop\t0" } } */

25597

Index: gcc/testsuite/gcc.target/s390/hotpatch-12.c

25598

===================================================================

25599

--- a/src/gcc/testsuite/gcc.target/s390/hotpatch-12.c (.../tags/gcc_4_8_2_release)

25600

+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-12.c (.../branches/gcc-4_8-branch)

25601

@@ -0,0 +1,20 @@

25602

+/* Functional tests for the function hotpatching feature. */

25603

+

25604

+/* { dg-do run } */

25605

+/* { dg-options "-O3 -mzarch -mno-hotpatch -mhotpatch=1 --save-temps" } */

25606

+

25607

+#include <stdio.h>

25608

+

25609

+void hp1(void)

25610

+{

25611

+ printf("hello, world!\n");

25612

+}

25613

+

25614

+int main (void)

25615

+{

25616

+ return 0;

25617

+}

25618

+

25619

+/* Check number of occurences of certain instructions. */

25620

+/* { dg-final { scan-assembler-times "nopr\t%r7" 1 } } */

25621

+/* { dg-final { scan-assembler-times "nop\t0" 1 } } */

25622

Index: gcc/testsuite/gcc.target/mips/bswap-1.c

25623

===================================================================

25624

--- a/src/gcc/testsuite/gcc.target/mips/bswap-1.c (.../tags/gcc_4_8_2_release)

25625

+++ b/src/gcc/testsuite/gcc.target/mips/bswap-1.c (.../branches/gcc-4_8-branch)

25626

@@ -0,0 +1,10 @@

25627

+/* { dg-options "isa_rev>=2" } */

25628

+/* { dg-skip-if "bswap recognition needs expensive optimizations" { *-*-* } { "-O0" "-O1" } { "" } } */

25629

+

25630

+NOMIPS16 unsigned short

25631

+foo (unsigned short x)

25632

+{

25633

+ return ((x << 8) & 0xff00) | ((x >> 8) & 0xff);

25634

+}

25635

+

25636

+/* { dg-final { scan-assembler "\twsbh\t" } } */

25637

Index: gcc/testsuite/gcc.target/mips/bswap-2.c

25638

===================================================================

25639

--- a/src/gcc/testsuite/gcc.target/mips/bswap-2.c (.../tags/gcc_4_8_2_release)

25640

+++ b/src/gcc/testsuite/gcc.target/mips/bswap-2.c (.../branches/gcc-4_8-branch)

25641

@@ -0,0 +1,9 @@

25642

+/* { dg-options "isa_rev>=2" } */

25643

+

25644

+NOMIPS16 unsigned short

25645

+foo (unsigned short x)

25646

+{

25647

+ return __builtin_bswap16 (x);

25648

+}

25649

+

25650

+/* { dg-final { scan-assembler "\twsbh\t" } } */

25651

Index: gcc/testsuite/gcc.target/mips/pr59137.c

25652

===================================================================

25653

--- a/src/gcc/testsuite/gcc.target/mips/pr59137.c (.../tags/gcc_4_8_2_release)

25654

+++ b/src/gcc/testsuite/gcc.target/mips/pr59137.c (.../branches/gcc-4_8-branch)

25655

@@ -0,0 +1,34 @@

25656

+/* { dg-do run } */

25657

+/* { dg-options "-mno-plt" } */

25658

+

25659

+extern void abort (void);

25660

+

25661

+struct lispstruct

25662

+{

25663

+ int e;

25664

+ int t;

25665

+};

25666

+

25667

+struct lispstruct Cnil_body;

25668

+struct lispstruct Ct_body;

25669

+int nvalues;

25670

+

25671

+struct lispstruct * __attribute__ ((noinline))

25672

+fLlistp (struct lispstruct *x0)

25673

+{

25674

+ if (x0 == &Cnil_body

25675

+ || (((unsigned long) x0 >= 0x80000000) ? 0

25676

+ : (!x0->e ? (x0 != &Cnil_body) : x0->t)))

25677

+ x0 = &Ct_body;

25678

+ else

25679

+ x0 = &Cnil_body;

25680

+ nvalues = 1;

25681

+ return x0;

25682

+}

25683

+

25684

+int main ()

25685

+{

25686

+ if (fLlistp ((struct lispstruct *) 0xa0000001) != &Cnil_body)

25687

+ abort ();

25688

+ return 0;

25689

+}

25690

Index: gcc/testsuite/gcc.target/mips/bswap-3.c

25691

===================================================================

25692

--- a/src/gcc/testsuite/gcc.target/mips/bswap-3.c (.../tags/gcc_4_8_2_release)

25693

+++ b/src/gcc/testsuite/gcc.target/mips/bswap-3.c (.../branches/gcc-4_8-branch)

25694

@@ -0,0 +1,14 @@

25695

+/* { dg-options "isa_rev>=2" } */

25696

+/* { dg-skip-if "bswap recognition needs expensive optimizations" { *-*-* } { "-O0" "-O1" } { "" } } */

25697

+

25698

+NOMIPS16 unsigned int

25699

+foo (unsigned int x)

25700

+{

25701

+ return (((x << 24) & 0xff000000)

25702

+ | ((x << 8) & 0xff0000)

25703

+ | ((x >> 8) & 0xff00)

25704

+ | ((x >> 24) & 0xff));

25705

+}

25706

+

25707

+/* { dg-final { scan-assembler "\twsbh\t" } } */

25708

+/* { dg-final { scan-assembler "\tror\t" } } */

25709

Index: gcc/testsuite/gcc.target/mips/bswap-4.c

25710

===================================================================

25711

--- a/src/gcc/testsuite/gcc.target/mips/bswap-4.c (.../tags/gcc_4_8_2_release)

25712

+++ b/src/gcc/testsuite/gcc.target/mips/bswap-4.c (.../branches/gcc-4_8-branch)

25713

@@ -0,0 +1,10 @@

25714

+/* { dg-options "isa_rev>=2" } */

25715

+

25716

+NOMIPS16 unsigned int

25717

+foo (unsigned int x)

25718

+{

25719

+ return __builtin_bswap32 (x);

25720

+}

25721

+

25722

+/* { dg-final { scan-assembler "\twsbh\t" } } */

25723

+/* { dg-final { scan-assembler "\tror\t" } } */

25724

Index: gcc/testsuite/gcc.target/mips/bswap-5.c

25725

===================================================================

25726

--- a/src/gcc/testsuite/gcc.target/mips/bswap-5.c (.../tags/gcc_4_8_2_release)

25727

+++ b/src/gcc/testsuite/gcc.target/mips/bswap-5.c (.../branches/gcc-4_8-branch)

25728

@@ -0,0 +1,20 @@

25729

+/* { dg-options "isa_rev>=2 -mgp64" } */

25730

+/* { dg-skip-if "bswap recognition needs expensive optimizations" { *-*-* } { "-O0" "-O1" } { "" } } */

25731

+

25732

+typedef unsigned long long uint64_t;

25733

+

25734

+NOMIPS16 uint64_t

25735

+foo (uint64_t x)

25736

+{

25737

+ return (((x << 56) & 0xff00000000000000ull)

25738

+ | ((x << 40) & 0xff000000000000ull)

25739

+ | ((x << 24) & 0xff0000000000ull)

25740

+ | ((x << 8) & 0xff00000000ull)

25741

+ | ((x >> 8) & 0xff000000)

25742

+ | ((x >> 24) & 0xff0000)

25743

+ | ((x >> 40) & 0xff00)

25744

+ | ((x >> 56) & 0xff));

25745

+}

25746

+

25747

+/* { dg-final { scan-assembler "\tdsbh\t" } } */

25748

+/* { dg-final { scan-assembler "\tdshd\t" } } */

25749

Index: gcc/testsuite/gcc.target/mips/bswap-6.c

25750

===================================================================

25751

--- a/src/gcc/testsuite/gcc.target/mips/bswap-6.c (.../tags/gcc_4_8_2_release)

25752

+++ b/src/gcc/testsuite/gcc.target/mips/bswap-6.c (.../branches/gcc-4_8-branch)

25753

@@ -0,0 +1,12 @@

25754

+/* { dg-options "isa_rev>=2 -mgp64" } */

25755

+

25756

+typedef unsigned long long uint64_t;

25757

+

25758

+NOMIPS16 uint64_t

25759

+foo (uint64_t x)

25760

+{

25761

+ return __builtin_bswap64 (x);

25762

+}

25763

+

25764

+/* { dg-final { scan-assembler "\tdsbh\t" } } */

25765

+/* { dg-final { scan-assembler "\tdshd\t" } } */

25766

Index: gcc/testsuite/gcc.target/sh/pr51244-19.c

25767

===================================================================

25768

--- a/src/gcc/testsuite/gcc.target/sh/pr51244-19.c (.../tags/gcc_4_8_2_release)

25769

+++ b/src/gcc/testsuite/gcc.target/sh/pr51244-19.c (.../branches/gcc-4_8-branch)

25770

@@ -22,11 +22,16 @@

25771

unwanted sequences. Thus, if we see any movt insns, something is not

25772

working as expected. This test requires -O2 because the T bit stores

25773

in question will be eliminated in additional insn split passes after

25774

- reload. */

25775

+ reload.

25776

+

25777

+ Notice: When this test case was initially added, the T bit optimization

25778

+ was buggy and this test case resulted in wrong code. The movt

25779

+ instructions actually have to be present in this case to get

25780

+ correct code. */

25781

/* { dg-do compile { target "sh*-*-*" } } */

25782

/* { dg-options "-O2" } */

25783

/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */

25784

-/* { dg-final { scan-assembler-not "movt" } } */

25785

+/* { dg-final { scan-assembler "movt" } } */

25786

25787

struct request

25788

{

25789

Index: gcc/testsuite/gcc.target/sh/pr54089-3.c

25790

===================================================================

25791

--- a/src/gcc/testsuite/gcc.target/sh/pr54089-3.c (.../tags/gcc_4_8_2_release)

25792

+++ b/src/gcc/testsuite/gcc.target/sh/pr54089-3.c (.../branches/gcc-4_8-branch)

25793

@@ -5,7 +5,7 @@

25794

/* { dg-options "-O1" } */

25795

/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m1*" "-m2" "-m2e*" } } */

25796

/* { dg-final { scan-assembler-not "and" } } */

25797

-/* { dg-final { scan-assembler-not "31" } } */

25798

+/* { dg-final { scan-assembler-not "#31" } } */

25799

25800

int

25801

test00 (unsigned int a, int* b, int c, int* d, unsigned int e)

25802

Index: gcc/testsuite/go.test/go-test.exp

25803

===================================================================

25804

--- a/src/gcc/testsuite/go.test/go-test.exp (.../tags/gcc_4_8_2_release)

25805

+++ b/src/gcc/testsuite/go.test/go-test.exp (.../branches/gcc-4_8-branch)

25806

@@ -333,17 +333,16 @@

25807

}

25808

25809

if { ( [file tail $test] == "select2.go" \

25810

- || [file tail $test] == "stack.go" ) \

25811

+ || [file tail $test] == "stack.go" \

25812

+ || [file tail $test] == "peano.go" ) \

25813

&& ! [check_effective_target_split_stack] } {

25814

- # chan/select2.go fails on targets without split stack,

25815

- # because they allocate a large stack segment that blows

25816

- # out the memory calculations.

25817

+ # These tests fails on targets without split stack.

25818

untested $name

25819

continue

25820

}

25821

25822

- if { [file tail $test] == "rotate.go" } {

25823

- # This test produces a temporary file that takes too long

25824

+ if [string match "*go.test/test/rotate\[0123\].go" $test] {

25825

+ # These tests produces a temporary file that takes too long

25826

# to compile--5 minutes on my laptop without optimization.

25827

# When compiling without optimization it tests nothing

25828

# useful, since the point of the test is to see whether

25829

Index: gcc/testsuite/lib/target-supports.exp

25830

===================================================================

25831

--- a/src/gcc/testsuite/lib/target-supports.exp (.../tags/gcc_4_8_2_release)

25832

+++ b/src/gcc/testsuite/lib/target-supports.exp (.../branches/gcc-4_8-branch)

25833

@@ -1311,6 +1311,32 @@

25834

return 0

25835

}

25836

25837

+# Return 1 if the target supports executing power8 vector instructions, 0

25838

+# otherwise. Cache the result.

25839

+

25840

+proc check_p8vector_hw_available { } {

25841

+ return [check_cached_effective_target p8vector_hw_available {

25842

+ # Some simulators are known to not support VSX/power8 instructions.

25843

+ # For now, disable on Darwin

25844

+ if { [istarget powerpc-*-eabi] || [istarget powerpc*-*-eabispe] || [istarget *-*-darwin*]} {

25845

+ expr 0

25846

+ } else {

25847

+ set options "-mpower8-vector"

25848

+ check_runtime_nocache p8vector_hw_available {

25849

+ int main()

25850

+ {

25851

+ #ifdef __MACH__

25852

+ asm volatile ("xxlorc vs0,vs0,vs0");

25853

+ #else

25854

+ asm volatile ("xxlorc 0,0,0");

25855

+ #endif

25856

+ return 0;

25857

+ }

25858

+ } $options

25859

+ }

25860

+ }]

25861

+}

25862

+

25863

# Return 1 if the target supports executing VSX instructions, 0

25864

# otherwise. Cache the result.

25865

25866

@@ -2672,6 +2698,33 @@

25867

}

25868

}

25869

25870

+# Return 1 if this is a PowerPC target supporting -mpower8-vector

25871

+

25872

+proc check_effective_target_powerpc_p8vector_ok { } {

25873

+ if { ([istarget powerpc*-*-*]

25874

+ && ![istarget powerpc-*-linux*paired*])

25875

+ || [istarget rs6000-*-*] } {

25876

+ # AltiVec is not supported on AIX before 5.3.

25877

+ if { [istarget powerpc*-*-aix4*]

25878

+ || [istarget powerpc*-*-aix5.1*]

25879

+ || [istarget powerpc*-*-aix5.2*] } {

25880

+ return 0

25881

+ }

25882

+ return [check_no_compiler_messages powerpc_p8vector_ok object {

25883

+ int main (void) {

25884

+#ifdef __MACH__

25885

+ asm volatile ("xxlorc vs0,vs0,vs0");

25886

+#else

25887

+ asm volatile ("xxlorc 0,0,0");

25888

+#endif

25889

+ return 0;

25890

+ }

25891

+ } "-mpower8-vector"]

25892

+ } else {

25893

+ return 0

25894

+ }

25895

+}

25896

+

25897

# Return 1 if this is a PowerPC target supporting -mvsx

25898

25899

proc check_effective_target_powerpc_vsx_ok { } {

25900

@@ -2699,6 +2752,27 @@

25901

}

25902

}

25903

25904

+# Return 1 if this is a PowerPC target supporting -mhtm

25905

+

25906

+proc check_effective_target_powerpc_htm_ok { } {

25907

+ if { ([istarget powerpc*-*-*]

25908

+ && ![istarget powerpc-*-linux*paired*])

25909

+ || [istarget rs6000-*-*] } {

25910

+ # HTM is not supported on AIX yet.

25911

+ if { [istarget powerpc*-*-aix*] } {

25912

+ return 0

25913

+ }

25914

+ return [check_no_compiler_messages powerpc_htm_ok object {

25915

+ int main (void) {

25916

+ asm volatile ("tbegin. 0");

25917

+ return 0;

25918

+ }

25919

+ } "-mhtm"]

25920

+ } else {

25921

+ return 0

25922

+ }

25923

+}

25924

+

25925

# Return 1 if this is a PowerPC target supporting -mcpu=cell.

25926

25927

proc check_effective_target_powerpc_ppu_ok { } {

25928

@@ -2794,6 +2868,22 @@

25929

}

25930

}

25931

25932

+# Return 1 if this is a PowerPC target using the ELFv2 ABI.

25933

+

25934

+proc check_effective_target_powerpc_elfv2 { } {

25935

+ if { [istarget powerpc*-*-*] } {

25936

+ return [check_no_compiler_messages powerpc_elfv2 object {

25937

+ #if _CALL_ELF != 2

25938

+ #error not ELF v2 ABI

25939

+ #else

25940

+ int dummy;

25941

+ #endif

25942

+ }]

25943

+ } else {

25944

+ return 0

25945

+ }

25946

+}

25947

+

25948

# Return 1 if this is a SPU target with a toolchain that

25949

# supports automatic overlay generation.

25950

25951

@@ -4499,6 +4589,7 @@

25952

switch $arg {

25953

"vmx_hw" { set selected [check_vmx_hw_available] }

25954

"vsx_hw" { set selected [check_vsx_hw_available] }

25955

+ "p8vector_hw" { set selected [check_p8vector_hw_available] }

25956

"ppc_recip_hw" { set selected [check_ppc_recip_hw_available] }

25957

"named_sections" { set selected [check_named_sections_available] }

25958

"gc_sections" { set selected [check_gc_sections_available] }

25959

@@ -4520,6 +4611,7 @@

25960

switch $arg {

25961

"vmx_hw" { return 1 }

25962

"vsx_hw" { return 1 }

25963

+ "p8vector_hw" { return 1 }

25964

"ppc_recip_hw" { return 1 }

25965

"named_sections" { return 1 }

25966

"gc_sections" { return 1 }

25967

@@ -5077,7 +5169,9 @@

25968

}

25969

25970

lappend DEFAULT_VECTCFLAGS "-maltivec"

25971

- if [check_vsx_hw_available] {

25972

+ if [check_p8vector_hw_available] {

25973

+ lappend DEFAULT_VECTCFLAGS "-mpower8-vector" "-mno-allow-movmisalign"

25974

+ } elseif [check_vsx_hw_available] {

25975

lappend DEFAULT_VECTCFLAGS "-mvsx" "-mno-allow-movmisalign"

25976

}

25977

25978

Index: gcc/testsuite/gfortran.dg/shape_8.f90

25979

===================================================================

25980

--- a/src/gcc/testsuite/gfortran.dg/shape_8.f90 (.../tags/gcc_4_8_2_release)

25981

+++ b/src/gcc/testsuite/gfortran.dg/shape_8.f90 (.../branches/gcc-4_8-branch)

25982

@@ -0,0 +1,10 @@

25983

+! { dg-do compile }

25984

+!

25985

+! PR 60450: [4.7/4.8 Regression] ICE with SHAPE intrinsic

25986

+!

25987

+! Contributed by Dave Allured <dave.allured@noaa.gov>

25988

+

25989

+ real, allocatable :: x(:,:)

25990

+ allocate (x(3,2), source=99.)

25991

+ print *, shape (x / 10.0)

25992

+end

25993

Index: gcc/testsuite/gfortran.dg/proc_ptr_comp_38.f90

25994

===================================================================

25995

--- a/src/gcc/testsuite/gfortran.dg/proc_ptr_comp_38.f90 (.../tags/gcc_4_8_2_release)

25996

+++ b/src/gcc/testsuite/gfortran.dg/proc_ptr_comp_38.f90 (.../branches/gcc-4_8-branch)

25997

@@ -0,0 +1,12 @@

25998

+! { dg-do compile }

25999

+!

26000

+! PR fortran/58803

26001

+!

26002

+! Contributed by Vittorio Zecca

26003

+!

26004

+! Was before ICEing due to a double free

26005

+!

26006

+ type t

26007

+ procedure(real), pointer, nopass :: f1, f2

26008

+ end type

26009

+ end

26010

Index: gcc/testsuite/gfortran.dg/where_4.f90

26011

===================================================================

26012

--- a/src/gcc/testsuite/gfortran.dg/where_4.f90 (.../tags/gcc_4_8_2_release)

26013

+++ b/src/gcc/testsuite/gfortran.dg/where_4.f90 (.../branches/gcc-4_8-branch)

26014

@@ -0,0 +1,18 @@

26015

+! { dg-do compile }

26016

+! PR 60522 - this used to ICE.

26017

+! Original test case Roger Ferrer Ibanez

26018

+subroutine foo(a, b)

26019

+ implicit none

26020

+ integer, dimension(:), intent(inout) :: a

26021

+ integer, dimension(:), intent(in) :: b

26022

+

26023

+ where (b(:) > 0)

26024

+ where (b(:) > 100)

26025

+ a(lbound(a, 1):ubound(a, 1)) = b(lbound(b, 1):ubound(b, 1)) * b(lbound(b, 1):ubound(b, 1)) - 100

26026

+ elsewhere

26027

+ a(lbound(a, 1):ubound(a, 1)) = b(lbound(b, 1):ubound(b, 1)) * b(lbound(b, 1):ubound(b, 1))

26028

+ end where

26029

+ elsewhere

26030

+ a(lbound(a, 1):ubound(a, 1)) = - b(lbound(b, 1):ubound(b, 1)) * b(lbound(b, 1):ubound(b, 1))

26031

+ end where

26032

+end subroutine foo

26033

Index: gcc/testsuite/gfortran.dg/gomp/pr59467.f90

26034

===================================================================

26035

--- a/src/gcc/testsuite/gfortran.dg/gomp/pr59467.f90 (.../tags/gcc_4_8_2_release)

26036

+++ b/src/gcc/testsuite/gfortran.dg/gomp/pr59467.f90 (.../branches/gcc-4_8-branch)

26037

@@ -0,0 +1,24 @@

26038

+! PR libgomp/59467

26039

+! { dg-do compile }

26040

+! { dg-options "-fopenmp" }

26041

+ FUNCTION t()

26042

+ INTEGER :: a, b, t

26043

+ a = 0

26044

+ b = 0

26045

+ !$OMP PARALLEL REDUCTION(+:b)

26046

+ !$OMP SINGLE ! { dg-error "is not threadprivate or private in outer context" }

26047

+ !$OMP ATOMIC WRITE

26048

+ a = 6

26049

+ !$OMP END SINGLE COPYPRIVATE (a)

26050

+ b = a

26051

+ !$OMP END PARALLEL

26052

+ t = b

26053

+ b = 0

26054

+ !$OMP PARALLEL REDUCTION(+:b)

26055

+ !$OMP SINGLE

26056

+ !$OMP ATOMIC WRITE

26057

+ b = 6

26058

+ !$OMP END SINGLE COPYPRIVATE (b)

26059

+ !$OMP END PARALLEL

26060

+ t = t + b

26061

+ END FUNCTION

26062

Index: gcc/testsuite/gfortran.dg/allocate_class_3.f90

26063

===================================================================

26064

--- a/src/gcc/testsuite/gfortran.dg/allocate_class_3.f90 (.../tags/gcc_4_8_2_release)

26065

+++ b/src/gcc/testsuite/gfortran.dg/allocate_class_3.f90 (.../branches/gcc-4_8-branch)

26066

@@ -0,0 +1,107 @@

26067

+! { dg-do run }

26068

+! Tests the fix for PR59414, comment #3, in which the allocate

26069

+! expressions were not correctly being stripped to provide the

26070

+! vpointer as an lhs to the pointer assignment of the vptr from

26071

+! the SOURCE expression.

26072

+!

26073

+! Contributed by Antony Lewis <antony@cosmologist.info>

26074

+!

26075

+module ObjectLists

26076

+ implicit none

26077

+

26078

+ type :: t

26079

+ integer :: i

26080

+ end type

26081

+

26082

+ type Object_array_pointer

26083

+ class(t), pointer :: p(:)

26084

+ end type

26085

+

26086

+contains

26087

+

26088

+ subroutine AddArray1 (P, Pt)

26089

+ class(t) :: P(:)

26090

+ class(Object_array_pointer) :: Pt

26091

+

26092

+ select type (Pt)

26093

+ class is (Object_array_pointer)

26094

+ if (associated (Pt%P)) deallocate (Pt%P)

26095

+ allocate(Pt%P(1:SIZE(P)), source=P)

26096

+ end select

26097

+ end subroutine

26098

+

26099

+ subroutine AddArray2 (P, Pt)

26100

+ class(t) :: P(:)

26101

+ class(Object_array_pointer) :: Pt

26102

+

26103

+ select type (Pt)

26104

+ type is (Object_array_pointer)

26105

+ if (associated (Pt%P)) deallocate (Pt%P)

26106

+ allocate(Pt%P(1:SIZE(P)), source=P)

26107

+ end select

26108

+ end subroutine

26109

+

26110

+ subroutine AddArray3 (P, Pt)

26111

+ class(t) :: P

26112

+ class(Object_array_pointer) :: Pt

26113

+

26114

+ select type (Pt)

26115

+ class is (Object_array_pointer)

26116

+ if (associated (Pt%P)) deallocate (Pt%P)

26117

+ allocate(Pt%P(1:4), source=P)

26118

+ end select

26119

+ end subroutine

26120

+

26121

+ subroutine AddArray4 (P, Pt)

26122

+ type(t) :: P(:)

26123

+ class(Object_array_pointer) :: Pt

26124

+

26125

+ select type (Pt)

26126

+ class is (Object_array_pointer)

26127

+ if (associated (Pt%P)) deallocate (Pt%P)

26128

+ allocate(Pt%P(1:SIZE(P)), source=P)

26129

+ end select

26130

+ end subroutine

26131

+end module

26132

+

26133

+ use ObjectLists

26134

+ type(Object_array_pointer), pointer :: Pt

26135

+ class(t), pointer :: P(:)

26136

+

26137

+ allocate (P(2), source = [t(1),t(2)])

26138

+ allocate (Pt, source = Object_array_pointer(NULL()))

26139

+ call AddArray1 (P, Pt)

26140

+ select type (x => Pt%p)

26141

+ type is (t)

26142

+ if (any (x%i .ne. [1,2])) call abort

26143

+ end select

26144

+ deallocate (P)

26145

+ deallocate (pt)

26146

+

26147

+ allocate (P(3), source = [t(3),t(4),t(5)])

26148

+ allocate (Pt, source = Object_array_pointer(NULL()))

26149

+ call AddArray2 (P, Pt)

26150

+ select type (x => Pt%p)

26151

+ type is (t)

26152

+ if (any (x%i .ne. [3,4,5])) call abort

26153

+ end select

26154

+ deallocate (P)

26155

+ deallocate (pt)

26156

+

26157

+ allocate (Pt, source = Object_array_pointer(NULL()))

26158

+ call AddArray3 (t(6), Pt)

26159

+ select type (x => Pt%p)

26160

+ type is (t)

26161

+ if (any (x%i .ne. [6,6,6,6])) call abort

26162

+ end select

26163

+ deallocate (pt)

26164

+

26165

+ allocate (Pt, source = Object_array_pointer(NULL()))

26166

+ call AddArray4 ([t(7), t(8)], Pt)

26167

+ select type (x => Pt%p)

26168

+ type is (t)

26169

+ if (any (x%i .ne. [7,8])) call abort

26170

+ end select

26171

+ deallocate (pt)

26172

+ end

26173

+

26174

Index: gcc/testsuite/gfortran.dg/reshape_6.f90

26175

===================================================================

26176

--- a/src/gcc/testsuite/gfortran.dg/reshape_6.f90 (.../tags/gcc_4_8_2_release)

26177

+++ b/src/gcc/testsuite/gfortran.dg/reshape_6.f90 (.../branches/gcc-4_8-branch)

26178

@@ -0,0 +1,19 @@

26179

+! { dg-do compile }

26180

+! PR fortran/58989

26181

+!

26182

+program test

26183

+

26184

+ real(8), dimension(4,4) :: fluxes

26185

+ real(8), dimension(2,2,2,2) :: f

26186

+ integer, dimension(3) :: dmmy

26187

+ integer, parameter :: indx(4)=(/2,2,2,2/)

26188

+

26189

+ fluxes = 1

26190

+

26191

+ dmmy = (/2,2,2/)

26192

+

26193

+ f = reshape(fluxes,(/dmmy,2/)) ! Caused an ICE

26194

+ f = reshape(fluxes,(/2,2,2,2/)) ! Works as expected

26195

+ f = reshape(fluxes,indx) ! Works as expected

26196

+

26197

+end program test

26198

Index: gcc/testsuite/gfortran.dg/unresolved_fixup_2.f90

26199

===================================================================

26200

--- a/src/gcc/testsuite/gfortran.dg/unresolved_fixup_2.f90 (.../tags/gcc_4_8_2_release)

26201

+++ b/src/gcc/testsuite/gfortran.dg/unresolved_fixup_2.f90 (.../branches/gcc-4_8-branch)

26202

@@ -0,0 +1,36 @@

26203

+! { dg-do compile }

26204

+!

26205

+! PR fortran/58007

26206

+! Unresolved fiixup while loading a module.

26207

+!

26208

+! This tests that the specification expression A%MAX_DEGREE in module BSR is

26209

+! correctly loaded and resolved in program MAIN.

26210

+!

26211

+! Original testcase from Daniel Shapiro <shapero@uw.edu>

26212

+

26213

+module matrix

26214

+ type :: sparse_matrix

26215

+ integer :: max_degree

26216

+ end type

26217

+end module

26218

+

26219

+module bsr

26220

+ use matrix

26221

+

26222

+ type, extends(sparse_matrix) :: bsr_matrix

26223

+ end type

26224

+

26225

+ integer :: i1

26226

+ integer :: i2

26227

+ integer :: i3

26228

+contains

26229

+ function get_neighbors (A)

26230

+ type(bsr_matrix), intent(in) :: A

26231

+ integer :: get_neighbors(A%max_degree)

26232

+ end function

26233

+end module

26234

+

26235

+program main

26236

+ use matrix

26237

+ use bsr

26238

+end

26239

Index: gcc/testsuite/gfortran.dg/init_flag_12.f90

26240

===================================================================

26241

--- a/src/gcc/testsuite/gfortran.dg/init_flag_12.f90 (.../tags/gcc_4_8_2_release)

26242

+++ b/src/gcc/testsuite/gfortran.dg/init_flag_12.f90 (.../branches/gcc-4_8-branch)

26243

@@ -0,0 +1,13 @@

26244

+! { dg-do compile }

26245

+! { dg-options "-fno-automatic -finit-local-zero" }

26246

+!

26247

+! PR 55907: [4.7/4.8/4.9 Regression] ICE with -fno-automatic -finit-local-zero

26248

+!

26249

+! Contributed by J.R. Garcia <garcia.espinosa.jr@gmail.com>

26250

+

26251

+subroutine cchaine (i)

26252

+ implicit none

26253

+ integer :: i

26254

+ character(len=i) :: chaine

26255

+ write(*,*) chaine

26256

+end subroutine

26257

Index: gcc/testsuite/gfortran.dg/derived_external_function_1.f90

26258

===================================================================

26259

--- a/src/gcc/testsuite/gfortran.dg/derived_external_function_1.f90 (.../tags/gcc_4_8_2_release)

26260

+++ b/src/gcc/testsuite/gfortran.dg/derived_external_function_1.f90 (.../branches/gcc-4_8-branch)

26261

@@ -0,0 +1,27 @@

26262

+! { dg-do run }

26263

+!

26264

+! PR fortran/58771

26265

+!

26266

+! Contributed by Vittorio Secca <zeccav@gmail.com>

26267

+!

26268

+! ICEd on the write statement with f() because the derived type backend

26269

+! declaration not built.

26270

+!

26271

+module m

26272

+ type t

26273

+ integer(4) g

26274

+ end type

26275

+end

26276

+

26277

+type(t) function f() result(ff)

26278

+ use m

26279

+ ff%g = 42

26280

+end

26281

+

26282

+ use m

26283

+ character (20) :: line1, line2

26284

+ type(t) f

26285

+ write (line1, *) f()

26286

+ write (line2, *) 42_4

26287

+ if (line1 .ne. line2) call abort

26288

+end

26289

Index: gcc/testsuite/gfortran.dg/implicit_pure_4.f90

26290

===================================================================

26291

--- a/src/gcc/testsuite/gfortran.dg/implicit_pure_4.f90 (.../tags/gcc_4_8_2_release)

26292

+++ b/src/gcc/testsuite/gfortran.dg/implicit_pure_4.f90 (.../branches/gcc-4_8-branch)

26293

@@ -0,0 +1,22 @@

26294

+! { dg-do compile }

26295

+!

26296

+! PR fortran/60543

26297

+! PR fortran/60283

26298

+!

26299

+module m

26300

+contains

26301

+ REAL(8) FUNCTION random()

26302

+ CALL RANDOM_NUMBER(random)

26303

+ END FUNCTION random

26304

+ REAL(8) FUNCTION random2()

26305

+ block

26306

+ block

26307

+ block

26308

+ CALL RANDOM_NUMBER(random2)

26309

+ end block

26310

+ end block

26311

+ end block

26312

+ END FUNCTION random2

26313

+end module m

26314

+

26315

+! { dg-final { scan-module-absence "m" "IMPLICIT_PURE" } }

26316

Index: gcc/testsuite/gfortran.dg/null_6.f90

26317

===================================================================

26318

--- a/src/gcc/testsuite/gfortran.dg/null_6.f90 (.../tags/gcc_4_8_2_release)

26319

+++ b/src/gcc/testsuite/gfortran.dg/null_6.f90 (.../branches/gcc-4_8-branch)

26320

@@ -30,5 +30,5 @@

26321

26322

subroutine test_PR34547_3 ()

26323

integer, allocatable :: i(:)

26324

- print *, NULL(i)

26325

+ print *, NULL(i) ! { dg-error "Invalid context for NULL" }

26326

end subroutine test_PR34547_3

26327

Index: gcc/testsuite/gfortran.dg/fmt_en.f90

26328

===================================================================

26329

--- a/src/gcc/testsuite/gfortran.dg/fmt_en.f90 (.../tags/gcc_4_8_2_release)

26330

+++ b/src/gcc/testsuite/gfortran.dg/fmt_en.f90 (.../branches/gcc-4_8-branch)

26331

@@ -0,0 +1,186 @@

26332

+! { dg-do run { target fd_truncate } }

26333

+! PR60128 Invalid outputs with EN descriptors

26334

+! Test case provided by Walt Brainerd.

26335

+program pr60128

26336

+use ISO_FORTRAN_ENV

26337

+ implicit none

26338

+ integer, parameter :: j(size(real_kinds)+4)=[REAL_KINDS, [4, 4, 4, 4]]

26339

+ logical :: l_skip(4) = .false.

26340

+ integer :: i

26341

+ integer :: n_tst = 0, n_cnt = 0, n_skip = 0

26342

+ character(len=20) :: s, s1

26343

+

26344

+ open (unit = 10, file = 'fmt_en.res')

26345

+! Check that the default rounding mode is to nearest and to even on tie.

26346

+ do i=1,size(real_kinds)

26347

+ if (i == 1) then

26348

+ write(s, '(2F4.1,2F4.0)') real(-9.49999905,kind=j(1)), &

26349

+ real(9.49999905,kind=j(1)), &

26350

+ real(9.5,kind=j(1)), real(8.5,kind=j(1))

26351

+ write(s1, '(3PE10.3,2PE10.3)') real(987350.,kind=j(1)), &

26352

+ real(98765.0,kind=j(1))

26353

+ else if (i == 2) then

26354

+ write(s, '(2F4.1,2F4.0)') real(-9.49999905,kind=j(2)), &

26355

+ real(9.49999905,kind=j(2)), &

26356

+ real(9.5,kind=j(2)), real(8.5,kind=j(2))

26357

+ write(s1, '(3PE10.3,2PE10.3)') real(987350.,kind=j(2)), &

26358

+ real(98765.0,kind=j(2))

26359

+ else if (i == 3) then

26360

+ write(s, '(2F4.1,2F4.0)') real(-9.49999905,kind=j(3)), &

26361

+ real(9.49999905,kind=j(3)), &

26362

+ real(9.5,kind=j(3)), real(8.5,kind=j(3))

26363

+ write(s1, '(3PE10.3,2PE10.3)') real(987350.,kind=j(3)), &

26364

+ real(98765.0,kind=j(3))

26365

+ else if (i == 4) then

26366

+ write(s, '(2F4.1,2F4.0)') real(-9.49999905,kind=j(4)), &

26367

+ real(9.49999905,kind=j(4)), &

26368

+ real(9.5,kind=j(4)), real(8.5,kind=j(4))

26369

+ write(s1, '(3PE10.3,2PE10.3)') real(987350.,kind=j(4)), &

26370

+ real(98765.0,kind=j(4))

26371

+ end if

26372

+ if (s /= '-9.5 9.5 10. 8.' .or. s1 /= ' 987.4E+03 98.76E+03') then

26373

+ l_skip(i) = .true.

26374

+! print "('Unsupported rounding for real(',i0,')')", j(i)

26375

+ end if

26376

+ end do

26377

+

26378

+

26379

+! Original test.

26380

+ call checkfmt("(en15.2)", -.44444, " -444.44E-03")

26381

+

26382

+! Test for the bug in comment 6.

26383

+ call checkfmt("(en15.0)", 1.0, " 1.E+00")

26384

+ call checkfmt("(en15.0)", 1.00000012, " 1.E+00")

26385

+ call checkfmt("(en15.0)", 0.99999994, " 1.E+00")

26386

+ call checkfmt("(en15.0)", 10.0, " 10.E+00")

26387

+ call checkfmt("(en15.0)", 10.0000010, " 10.E+00")

26388

+ call checkfmt("(en15.0)", 9.99999905, " 10.E+00")

26389

+ call checkfmt("(en15.0)", 100.0, " 100.E+00")

26390

+ call checkfmt("(en15.0)", 100.000008, " 100.E+00")

26391

+ call checkfmt("(en15.0)", 99.9999924, " 100.E+00")

26392

+ call checkfmt("(en15.0)", 1000.0, " 1.E+03")

26393

+ call checkfmt("(en15.0)", 1000.00006, " 1.E+03")

26394

+ call checkfmt("(en15.0)", 999.999939, " 1.E+03")

26395

+ call checkfmt("(en15.0)", 9.5, " 10.E+00")

26396

+ call checkfmt("(en15.0)", 9.50000095, " 10.E+00")

26397

+ call checkfmt("(en15.0)", 9.49999905, " 9.E+00")

26398

+ call checkfmt("(en15.0)", 99.5, " 100.E+00")

26399

+ call checkfmt("(en15.0)", 99.5000076, " 100.E+00")

26400

+ call checkfmt("(en15.0)", 99.4999924, " 99.E+00")

26401

+ call checkfmt("(en15.0)", 999.5, " 1.E+03")

26402

+ call checkfmt("(en15.0)", 999.500061, " 1.E+03")

26403

+ call checkfmt("(en15.0)", 999.499939, " 999.E+00")

26404

+ call checkfmt("(en15.0)", 9500.0, " 10.E+03")

26405

+ call checkfmt("(en15.0)", 9500.00098, " 10.E+03")

26406

+ call checkfmt("(en15.0)", 9499.99902, " 9.E+03")

26407

+ call checkfmt("(en15.1)", 9950.0, " 10.0E+03")

26408

+ call checkfmt("(en15.2)", 9995.0, " 10.00E+03")

26409

+ call checkfmt("(en15.3)", 9999.5, " 10.000E+03")

26410

+ call checkfmt("(en15.1)", 9.5, " 9.5E+00")

26411

+ call checkfmt("(en15.1)", 9.50000095, " 9.5E+00")

26412

+ call checkfmt("(en15.1)", 9.49999905, " 9.5E+00")

26413

+ call checkfmt("(en15.1)", 0.099951, " 100.0E-03")

26414

+ call checkfmt("(en15.1)", 0.009951, " 10.0E-03")

26415

+ call checkfmt("(en15.1)", 0.000999951," 1.0E-03")

26416

+

26417

+ call checkfmt("(en15.0)", -1.0, " -1.E+00")

26418

+ call checkfmt("(en15.0)", -1.00000012, " -1.E+00")

26419

+ call checkfmt("(en15.0)", -0.99999994, " -1.E+00")

26420

+ call checkfmt("(en15.0)", -10.0, " -10.E+00")

26421

+ call checkfmt("(en15.0)", -10.0000010, " -10.E+00")

26422

+ call checkfmt("(en15.0)", -9.99999905, " -10.E+00")

26423

+ call checkfmt("(en15.0)", -100.0, " -100.E+00")

26424

+ call checkfmt("(en15.0)", -100.000008, " -100.E+00")

26425

+ call checkfmt("(en15.0)", -99.9999924, " -100.E+00")

26426

+ call checkfmt("(en15.0)", -1000.0, " -1.E+03")

26427

+ call checkfmt("(en15.0)", -1000.00006, " -1.E+03")

26428

+ call checkfmt("(en15.0)", -999.999939, " -1.E+03")

26429

+ call checkfmt("(en15.0)", -9.5, " -10.E+00")

26430

+ call checkfmt("(en15.0)", -9.50000095, " -10.E+00")

26431

+ call checkfmt("(en15.0)", -9.49999905, " -9.E+00")

26432

+ call checkfmt("(en15.0)", -99.5, " -100.E+00")

26433

+ call checkfmt("(en15.0)", -99.5000076, " -100.E+00")

26434

+ call checkfmt("(en15.0)", -99.4999924, " -99.E+00")

26435

+ call checkfmt("(en15.0)", -999.5, " -1.E+03")

26436

+ call checkfmt("(en15.0)", -999.500061, " -1.E+03")

26437

+ call checkfmt("(en15.0)", -999.499939, " -999.E+00")

26438

+ call checkfmt("(en15.0)", -9500.0, " -10.E+03")

26439

+ call checkfmt("(en15.0)", -9500.00098, " -10.E+03")

26440

+ call checkfmt("(en15.0)", -9499.99902, " -9.E+03")

26441

+ call checkfmt("(en15.1)", -9950.0, " -10.0E+03")

26442

+ call checkfmt("(en15.2)", -9995.0, " -10.00E+03")

26443

+ call checkfmt("(en15.3)", -9999.5, " -10.000E+03")

26444

+ call checkfmt("(en15.1)", -9.5, " -9.5E+00")

26445

+ call checkfmt("(en15.1)", -9.50000095, " -9.5E+00")

26446

+ call checkfmt("(en15.1)", -9.49999905, " -9.5E+00")

26447

+ call checkfmt("(en15.1)", -0.099951, " -100.0E-03")

26448

+ call checkfmt("(en15.1)", -0.009951, " -10.0E-03")

26449

+ call checkfmt("(en15.1)", -0.000999951," -1.0E-03")

26450

+

26451

+ call checkfmt("(en15.1)", 987350., " 987.4E+03")

26452

+ call checkfmt("(en15.2)", 98735., " 98.74E+03")

26453

+ call checkfmt("(en15.3)", 9873.5, " 9.874E+03")

26454

+ call checkfmt("(en15.1)", 987650., " 987.6E+03")

26455

+ call checkfmt("(en15.2)", 98765., " 98.76E+03")

26456

+ call checkfmt("(en15.3)", 9876.5, " 9.876E+03")

26457

+ call checkfmt("(en15.1)", 3.125E-02, " 31.2E-03")

26458

+ call checkfmt("(en15.1)", 9.375E-02, " 93.8E-03")

26459

+ call checkfmt("(en15.2)", 1.5625E-02, " 15.62E-03")

26460

+ call checkfmt("(en15.2)", 4.6875E-02, " 46.88E-03")

26461

+ call checkfmt("(en15.3)", 7.8125E-03, " 7.812E-03")

26462

+ call checkfmt("(en15.3)", 2.34375E-02, " 23.438E-03")

26463

+ call checkfmt("(en15.3)", 9.765625E-04," 976.562E-06")

26464

+ call checkfmt("(en15.6)", 2.9296875E-03," 2.929688E-03")

26465

+

26466

+ call checkfmt("(en15.1)", -987350., " -987.4E+03")

26467

+ call checkfmt("(en15.2)", -98735., " -98.74E+03")

26468

+ call checkfmt("(en15.3)", -9873.5, " -9.874E+03")

26469

+ call checkfmt("(en15.1)", -987650., " -987.6E+03")

26470

+ call checkfmt("(en15.2)", -98765., " -98.76E+03")

26471

+ call checkfmt("(en15.3)", -9876.5, " -9.876E+03")

26472

+ call checkfmt("(en15.1)", -3.125E-02, " -31.2E-03")

26473

+ call checkfmt("(en15.1)", -9.375E-02, " -93.8E-03")

26474

+ call checkfmt("(en15.2)", -1.5625E-02, " -15.62E-03")

26475

+ call checkfmt("(en15.2)", -4.6875E-02, " -46.88E-03")

26476

+ call checkfmt("(en15.3)", -7.8125E-03, " -7.812E-03")

26477

+ call checkfmt("(en15.3)", -2.34375E-02, " -23.438E-03")

26478

+ call checkfmt("(en15.3)", -9.765625E-04," -976.562E-06")

26479

+ call checkfmt("(en15.6)", -2.9296875E-03," -2.929688E-03")

26480

+

26481

+ ! print *, n_tst, n_cnt, n_skip

26482

+ if (n_cnt /= 0) call abort

26483

+ if (all(.not. l_skip)) write (10, *) "All kinds rounded to nearest"

26484

+ close (10)

26485

+

26486

+contains

26487

+ subroutine checkfmt(fmt, x, cmp)

26488

+ implicit none

26489

+ integer :: i

26490

+ character(len=*), intent(in) :: fmt

26491

+ real, intent(in) :: x

26492

+ character(len=*), intent(in) :: cmp

26493

+ do i=1,size(real_kinds)

26494

+ if (i == 1) then

26495

+ write(s, fmt) real(x,kind=j(1))

26496

+ else if (i == 2) then

26497

+ write(s, fmt) real(x,kind=j(2))

26498

+ else if (i == 3) then

26499

+ write(s, fmt) real(x,kind=j(3))

26500

+ else if (i == 4) then

26501

+ write(s, fmt) real(x,kind=j(4))

26502

+ end if

26503

+ n_tst = n_tst + 1

26504

+ if (s /= cmp) then

26505

+ if (l_skip(i)) then

26506

+ n_skip = n_skip + 1

26507

+ else

26508

+ print "(a,1x,a,' expected: ',1x,a)", fmt, s, cmp

26509

+ n_cnt = n_cnt + 1

26510

+ end if

26511

+ end if

26512

+ end do

26513

+

26514

+ end subroutine

26515

+end program

26516

+! { dg-final { scan-file fmt_en.res "All kinds rounded to nearest" { xfail { i?86-*-solaris2.9* hppa*-*-hpux* } } } }

26517

+! { dg-final { cleanup-saved-temps } }

26518

Index: gcc/testsuite/gfortran.dg/constructor_9.f90

26519

===================================================================

26520

--- a/src/gcc/testsuite/gfortran.dg/constructor_9.f90 (.../tags/gcc_4_8_2_release)

26521

+++ b/src/gcc/testsuite/gfortran.dg/constructor_9.f90 (.../branches/gcc-4_8-branch)

26522

@@ -0,0 +1,22 @@

26523

+! { dg-do compile }

26524

+! { dg-options "-Wall" }

26525

+!

26526

+! PR 58471: [4.8/4.9 Regression] ICE on invalid with missing type constructor and -Wall

26527

+!

26528

+! Contributed by Andrew Benson <abensonca@gmail.com>

26529

+

26530

+module cf

26531

+ implicit none

26532

+ type :: cfmde

26533

+ end type

26534

+ interface cfmde

26535

+ module procedure mdedc ! { dg-error "is neither function nor subroutine" }

26536

+ end interface

26537

+contains

26538

+ subroutine cfi()

26539

+ type(cfmde), pointer :: cfd

26540

+ cfd=cfmde() ! { dg-error "Can't convert" }

26541

+ end subroutine

26542

+end module

26543

+

26544

+! { dg-final { cleanup-modules "cf" } }

26545

Index: gcc/testsuite/gfortran.dg/round_3.f08

26546

===================================================================

26547

--- a/src/gcc/testsuite/gfortran.dg/round_3.f08 (.../tags/gcc_4_8_2_release)

26548

+++ b/src/gcc/testsuite/gfortran.dg/round_3.f08 (.../branches/gcc-4_8-branch)

26549

@@ -16,19 +16,44 @@

26550

call checkfmt("(RU,1P,G6.0E2)", 2.0, "2.E+00")

26551

call checkfmt("(RU,1P,G10.4E2)", 2.3456e5, "2.3456E+05")

26552

26553

- call checkfmt("(RU,F2.0)", 0.09, "1.") ! 0.

26554

+ call checkfmt("(RC,G10.2)", 99.5, " 0.10E+03") ! pr59774

26555

+ call checkfmt("(RC,G10.2)", 995., " 0.10E+04") ! pr59774

26556

+ call checkfmt("(RC,G10.3)", 999.5, " 0.100E+04") ! pr59774

26557

+ call checkfmt("(RC,G10.3)", 9995., " 0.100E+05") ! pr59774

26558

+ call checkfmt("(RU,G10.2)", .099, " 0.10 ") ! pr59774

26559

+ call checkfmt("(RC,G10.1)", .095, " 0.1 ") ! pr59774

26560

+ call checkfmt("(RU,G10.3)", .0999, " 0.100 ") ! pr59774

26561

+ call checkfmt("(RC,G10.2)", .0995, " 0.10 ") ! pr59774

26562

+

26563

+ call checkfmt("(RU,G9.3)", 891.1, " 892.") ! pr59836

26564

+ call checkfmt("(RD,G9.3)", -891.1, "-892.") ! pr59836

26565

+

26566

+ call checkfmt("(RU,F6.4)", 0.00006, "0.0001")! 0.

26567

+ call checkfmt("(RU,F5.3)", 0.0007, "0.001") ! 0.

26568

+ call checkfmt("(RU,F4.2)", 0.008, "0.01") ! 0.

26569

+ call checkfmt("(RU,F3.1)", 0.09, "0.1") ! 0.

26570

+

26571

+ call checkfmt("(RU,F2.0)", 0.09, "1.") ! 0.

26572

call checkfmt("(RD,F3.0)", -0.09, "-1.") ! -0.

26573

- call checkfmt("(RU,F2.0)", 2.0, "2.") ! 3.

26574

- call checkfmt("(RD,F3.0)", -2.0, "-2.") ! -3.

26575

- call checkfmt("(RU,F6.4)", 2.0, "2.0000") ! 2.0001

26576

- call checkfmt("(RD,F7.4)", -2.0, "-2.0000") ! -2.0001

26577

- call checkfmt("(RU,1P,E6.0E2)", 2.0, "2.E+00") ! 3.E+00

26578

+ call checkfmt("(RU,F2.0)", 0.9, "1.") ! pr59836

26579

+ call checkfmt("(RC,F2.0)", 0.4, "0.") ! pr59836

26580

+ call checkfmt("(RC,F2.0)", 0.5, "1.") ! pr59836

26581

+ call checkfmt("(RC,F2.0)", 0.6, "1.") ! pr59836

26582

+ call checkfmt("(RD,F3.0)", -0.9, "-1.") ! pr59836

26583

+ call checkfmt("(RC,F3.0)", -0.4, "-0.") ! pr59836

26584

+ call checkfmt("(RC,F3.0)", -0.5, "-1.") ! pr59836

26585

+ call checkfmt("(RC,F3.0)", -0.6, "-1.") ! pr59836

26586

+ call checkfmt("(RU,F2.0)", 2.0, "2.") ! 3.

26587

+ call checkfmt("(RD,F3.0)", -2.0, "-2.") ! -3.

26588

+ call checkfmt("(RU,F6.4)", 2.0, "2.0000") ! 2.0001

26589

+ call checkfmt("(RD,F7.4)", -2.0, "-2.0000") ! -2.0001

26590

+ call checkfmt("(RU,1P,E6.0E2)", 2.0, "2.E+00") ! 3.E+00

26591

call checkfmt("(RD,1P,E7.0E2)", -2.0, "-2.E+00") ! -3.E+00

26592

- call checkfmt("(RU,1P,E7.1E2)", 2.5, "2.5E+00") ! 2.6E+00

26593

+ call checkfmt("(RU,1P,E7.1E2)", 2.5, "2.5E+00") ! 2.6E+00

26594

call checkfmt("(RD,1P,E8.1E2)", -2.5, "-2.5E+00") ! -2.6E+00

26595

call checkfmt("(RU,1P,E10.4E2)", 2.5, "2.5000E+00") ! 2.5001E+00

26596

call checkfmt("(RD,1P,E11.4E2)", -2.5, "-2.5000E+00") ! -2.5001E+00

26597

- call checkfmt("(RU,1P,G6.0E2)", 2.0, "2.E+00") ! 3.E+00

26598

+ call checkfmt("(RU,1P,G6.0E2)", 2.0, "2.E+00") ! 3.E+00

26599

call checkfmt("(RD,1P,G7.0E2)", -2.0, "-2.E+00") ! -3.E+00

26600

call checkfmt("(RU,1P,G10.4E2)", 2.3456e5, "2.3456E+05") ! 2.3457E+05

26601

call checkfmt("(RD,1P,G11.4E2)", -2.3456e5, "-2.3456E+05") ! -2.3457E+05

26602

Index: gcc/testsuite/gfortran.dg/default_initialization_7.f90

26603

===================================================================

26604

--- a/src/gcc/testsuite/gfortran.dg/default_initialization_7.f90 (.../tags/gcc_4_8_2_release)

26605

+++ b/src/gcc/testsuite/gfortran.dg/default_initialization_7.f90 (.../branches/gcc-4_8-branch)

26606

@@ -0,0 +1,22 @@

26607

+! { dg-do compile }

26608

+!

26609

+! PR fortran/57033

26610

+! ICE on a structure constructor of an extended derived type whose parent

26611

+! type last component has a default initializer

26612

+!

26613

+! Contributed by Tilo Schwarz <tilo@tilo-schwarz.de>

26614

+

26615

+program ice

26616

+

26617

+type m

26618

+ integer i

26619

+ logical :: f = .false.

26620

+end type m

26621

+

26622

+type, extends(m) :: me

26623

+end type me

26624

+

26625

+type(me) meo

26626

+

26627

+meo = me(1) ! ICE

26628

+end program ice

26629

Index: gcc/testsuite/gfortran.dg/proc_ptr_46.f90

26630

===================================================================

26631

--- a/src/gcc/testsuite/gfortran.dg/proc_ptr_46.f90 (.../tags/gcc_4_8_2_release)

26632

+++ b/src/gcc/testsuite/gfortran.dg/proc_ptr_46.f90 (.../branches/gcc-4_8-branch)

26633

@@ -0,0 +1,14 @@

26634

+! { dg-do compile }

26635

+!

26636

+! PR fortran/49397

26637

+!

26638

+! Invalid per IR F08/0060 and F2008Corr2, C729

26639

+!

26640

+

26641

+! Print *,f() ! << Valid when uncommented

26642

+Contains

26643

+ Subroutine s

26644

+ Procedure(Real),Pointer :: p

26645

+ p => f ! { dg-error "Procedure pointer target 'f' at .1. must be either an intrinsic, host or use associated, referenced or have the EXTERNAL attribute" }

26646

+ End Subroutine

26647

+End

26648

Index: gcc/testsuite/gfortran.dg/pr52370.f90

26649

===================================================================

26650

--- a/src/gcc/testsuite/gfortran.dg/pr52370.f90 (.../tags/gcc_4_8_2_release)

26651

+++ b/src/gcc/testsuite/gfortran.dg/pr52370.f90 (.../branches/gcc-4_8-branch)

26652

@@ -0,0 +1,21 @@

26653

+! PR fortran/52370

26654

+! { dg-do compile }

26655

+! { dg-options "-O1 -Wall" }

26656

+

26657

+module pr52370

26658

+contains

26659

+ subroutine foo(a,b)

26660

+ real, intent(out) :: a

26661

+ real, dimension(:), optional, intent(out) :: b

26662

+ a=0.5

26663

+ if (present(b)) then

26664

+ b=1.0

26665

+ end if

26666

+ end subroutine foo

26667

+end module pr52370

26668

+

26669

+program prg52370

26670

+ use pr52370

26671

+ real :: a

26672

+ call foo(a)

26673

+end program prg52370

26674

Index: gcc/testsuite/gfortran.dg/graphite/pr59817.f

26675

===================================================================

26676

--- a/src/gcc/testsuite/gfortran.dg/graphite/pr59817.f (.../tags/gcc_4_8_2_release)

26677

+++ b/src/gcc/testsuite/gfortran.dg/graphite/pr59817.f (.../branches/gcc-4_8-branch)

26678

@@ -0,0 +1,14 @@

26679

+! { dg-do compile }

26680

+! { dg-options "-O2 -floop-interchange" }

26681

+ SUBROUTINE PREPD(ICAST,ICAS,ICASX,ICAS1,ICAS2,NDET,NM,III,IMP,

26682

+ * CASMIN)

26683

+ LOGICAL CASMIN

26684

+ DIMENSION ICAST(NDET,NM),IMP(NM)

26685

+ IF(CASMIN) THEN

26686

+ DO K=1,NDET

26687

+ DO L=1,NM

26688

+ IF(L.EQ.K-1) ICAST(K,L) = 1

26689

+ END DO

26690

+ END DO

26691

+ END IF

26692

+ END SUBROUTINE

26693

Index: gcc/testsuite/gfortran.dg/str_comp_optimize_1.f90

26694

===================================================================

26695

--- a/src/gcc/testsuite/gfortran.dg/str_comp_optimize_1.f90 (.../tags/gcc_4_8_2_release)

26696

+++ b/src/gcc/testsuite/gfortran.dg/str_comp_optimize_1.f90 (.../branches/gcc-4_8-branch)

26697

@@ -0,0 +1,22 @@

26698

+! { dg-do compile }

26699

+! { dg-options "-ffrontend-optimize" }

26700

+!

26701

+! PR fortran/60341

26702

+! An unguarded union access was wrongly enabling a frontend optimization on a

26703

+! string comparison, leading to an ICE.

26704

+!

26705

+! Original testcase from Steve Chapel <steve.chapel@a2pg.com>.

26706

+! Reduced by Steven G. Kargl <kargl@gcc.gnu.org>.

26707

+!

26708

+

26709

+ subroutine modelg(ncm)

26710

+ implicit none

26711

+ integer, parameter :: pc = 30, pm = pc - 1

26712

+ integer i

26713

+ character*4 catt(pm,2)

26714

+ integer ncm,iatt(pm,pc)

26715

+ do i=1,ncm

26716

+ if (catt(i,1)//catt(i,2).eq.'central') exit

26717

+ end do

26718

+ iatt(i,4)=1

26719

+ end

26720

Index: gcc/testsuite/gfortran.dg/list_read_12.f90

26721

===================================================================

26722

--- a/src/gcc/testsuite/gfortran.dg/list_read_12.f90 (.../tags/gcc_4_8_2_release)

26723

+++ b/src/gcc/testsuite/gfortran.dg/list_read_12.f90 (.../branches/gcc-4_8-branch)

26724

@@ -0,0 +1,11 @@

26725

+! { dg-do run }

26726

+! PR58324 Bogus end of file condition

26727

+integer :: i, ios

26728

+open(99, access='stream', form='unformatted')

26729

+write(99) "5 a"

26730

+close(99)

26731

+

26732

+open(99, access='sequential', form='formatted')

26733

+read(99, *, iostat=ios) i

26734

+if (ios /= 0) call abort

26735

+end

26736

Index: gcc/testsuite/gfortran.dg/generic_28.f90

26737

===================================================================

26738

--- a/src/gcc/testsuite/gfortran.dg/generic_28.f90 (.../tags/gcc_4_8_2_release)

26739

+++ b/src/gcc/testsuite/gfortran.dg/generic_28.f90 (.../branches/gcc-4_8-branch)

26740

@@ -0,0 +1,18 @@

26741

+! { dg-do compile }

26742

+!

26743

+! PR 58998: [4.8/4.9 Regression] Generic interface problem with gfortran

26744

+!

26745

+! Contributed by Paul van Delst

26746

+

26747

+ interface iargc

26748

+ procedure iargc_8

26749

+ end interface

26750

+

26751

+contains

26752

+

26753

+ integer(8) function iargc_8()

26754

+ integer(4) iargc

26755

+ iargc_8 = iargc()

26756

+ end function

26757

+

26758

+end

26759

Index: gcc/testsuite/gfortran.dg/unresolved_fixup_1.f90

26760

===================================================================

26761

--- a/src/gcc/testsuite/gfortran.dg/unresolved_fixup_1.f90 (.../tags/gcc_4_8_2_release)

26762

+++ b/src/gcc/testsuite/gfortran.dg/unresolved_fixup_1.f90 (.../branches/gcc-4_8-branch)

26763

@@ -0,0 +1,44 @@

26764

+! { dg-do compile }

26765

+!

26766

+! PR fortran/58007

26767

+! Unresolved fixup while loading a module.

26768

+!

26769

+! This tests that the specification expression A%MAX_DEGREE in module BSR is

26770

+! correctly loaded and resolved in program MAIN.

26771

+!

26772

+! Original testcase from Daniel Shapiro <shapero@uw.edu>

26773

+! Reduced by Tobias Burnus <burnus@net-b.de> and Janus Weil <janus@gcc.gnu.org>

26774

+

26775

+module matrix

26776

+ type :: sparse_matrix

26777

+ integer :: max_degree

26778

+ end type

26779

+contains

26780

+ subroutine init_interface (A)

26781

+ class(sparse_matrix), intent(in) :: A

26782

+ end subroutine

26783

+ real function get_value_interface()

26784

+ end function

26785

+end module

26786

+

26787

+module ellpack

26788

+ use matrix

26789

+end module

26790

+

26791

+module bsr

26792

+ use matrix

26793

+ type, extends(sparse_matrix) :: bsr_matrix

26794

+ contains

26795

+ procedure :: get_neighbors

26796

+ end type

26797

+contains

26798

+ function get_neighbors (A)

26799

+ class(bsr_matrix), intent(in) :: A

26800

+ integer :: get_neighbors(A%max_degree)

26801

+ end function

26802

+end module

26803

+

26804

+program main

26805

+ use ellpack

26806

+ use bsr

26807

+end

26808

Index: gcc/testsuite/gfortran.dg/lto/pr60635_1.c

26809

===================================================================

26810

--- a/src/gcc/testsuite/gfortran.dg/lto/pr60635_1.c (.../tags/gcc_4_8_2_release)

26811

+++ b/src/gcc/testsuite/gfortran.dg/lto/pr60635_1.c (.../branches/gcc-4_8-branch)

26812

@@ -0,0 +1,14 @@

26813

+#include <stdint.h>

26814

+#include <stdbool.h>

26815

+

26816

+static bool littleendian=true;

26817

+

26818

+uint16_t bigendc16(union{uint16_t * n;uint8_t* b;}x){

26819

+

26820

+ if (!littleendian) return *x.n;

26821

+

26822

+ uint16_t res = ((uint16_t)(x.b[1])<<0) |

26823

+ ((uint16_t)(x.b[0])<<8);

26824

+ return res;

26825

+}

26826

+

26827

Index: gcc/testsuite/gfortran.dg/lto/pr60635_0.f90

26828

===================================================================

26829

--- a/src/gcc/testsuite/gfortran.dg/lto/pr60635_0.f90 (.../tags/gcc_4_8_2_release)

26830

+++ b/src/gcc/testsuite/gfortran.dg/lto/pr60635_0.f90 (.../branches/gcc-4_8-branch)

26831

@@ -0,0 +1,16 @@

26832

+! { dg-lto-do link }

26833

+program test

26834

+ use iso_fortran_env

26835

+

26836

+ interface

26837

+ integer(int16) function bigendc16(x) bind(C)

26838

+ import

26839

+ integer(int16), intent(in) :: x

26840

+ end function

26841

+ end interface

26842

+

26843

+ integer(int16) :: x16 = 12345

26844

+ x16 = bigendc16(x16)

26845

+ print *,x16

26846

+end program

26847

+

26848

Index: gcc/testsuite/gfortran.dg/arrayio_13.f90

26849

===================================================================

26850

--- a/src/gcc/testsuite/gfortran.dg/arrayio_13.f90 (.../tags/gcc_4_8_2_release)

26851

+++ b/src/gcc/testsuite/gfortran.dg/arrayio_13.f90 (.../branches/gcc-4_8-branch)

26852

@@ -0,0 +1,14 @@

26853

+! { dg-do run }

26854

+! PR60810 Bogus end-of-file

26855

+program readstrlist

26856

+ character(len=80), dimension(2) :: ver

26857

+ integer :: a, b, c

26858

+ a = 1

26859

+ b = 2

26860

+ c = 3

26861

+ ver(1) = '285 383'

26862

+ ver(2) = '985'

26863

+ read( ver, *) a, b, c

26864

+ if (a /= 285 .or. b /= 383 .or. c /= 985) call abort

26865

+ !write ( *, *) a, b, c

26866

+end

26867

Index: gcc/testsuite/gfortran.dg/null_5.f90

26868

===================================================================

26869

--- a/src/gcc/testsuite/gfortran.dg/null_5.f90 (.../tags/gcc_4_8_2_release)

26870

+++ b/src/gcc/testsuite/gfortran.dg/null_5.f90 (.../branches/gcc-4_8-branch)

26871

@@ -34,7 +34,7 @@

26872

end subroutine test_PR34547_1

26873

26874

subroutine test_PR34547_2 ()

26875

- print *, null () ! { dg-error "in data transfer statement requires MOLD" }

26876

+ print *, null () ! { dg-error "Invalid context" }

26877

end subroutine test_PR34547_2

26878

26879

subroutine test_PR34547_3 ()

26880

Index: gcc/testsuite/gfortran.dg/proc_ptr_43.f90

26881

===================================================================

26882

--- a/src/gcc/testsuite/gfortran.dg/proc_ptr_43.f90 (.../tags/gcc_4_8_2_release)

26883

+++ b/src/gcc/testsuite/gfortran.dg/proc_ptr_43.f90 (.../branches/gcc-4_8-branch)

26884

@@ -0,0 +1,19 @@

26885

+! { dg-do compile }

26886

+!

26887

+! PR 58099: [4.8/4.9 Regression] [F03] over-zealous procedure-pointer error checking

26888

+!

26889

+! Contributed by Daniel Price <daniel.price@monash.edu>

26890

+

26891

+ implicit none

26892

+ procedure(real), pointer :: wfunc

26893

+

26894

+ wfunc => w_cubic

26895

+

26896

+contains

26897

+

26898

+ pure real function w_cubic(q2)

26899

+ real, intent(in) :: q2

26900

+ w_cubic = 0.

26901

+ end function

26902

+

26903

+end

26904

Index: gcc/testsuite/gfortran.dg/nan_7.f90

26905

===================================================================

26906

--- a/src/gcc/testsuite/gfortran.dg/nan_7.f90 (.../tags/gcc_4_8_2_release)

26907

+++ b/src/gcc/testsuite/gfortran.dg/nan_7.f90 (.../branches/gcc-4_8-branch)

26908

@@ -2,6 +2,7 @@

26909

! { dg-options "-fno-range-check" }

26910

! { dg-require-effective-target fortran_real_16 }

26911

! { dg-require-effective-target fortran_integer_16 }

26912

+! { dg-skip-if "" { "powerpc*le-*-*" } { "*" } { "" } }

26913

! PR47293 NAN not correctly read

26914

character(len=200) :: str

26915

real(16) :: r

26916

Index: gcc/testsuite/gfortran.dg/typebound_generic_15.f90

26917

===================================================================

26918

--- a/src/gcc/testsuite/gfortran.dg/typebound_generic_15.f90 (.../tags/gcc_4_8_2_release)

26919

+++ b/src/gcc/testsuite/gfortran.dg/typebound_generic_15.f90 (.../branches/gcc-4_8-branch)

26920

@@ -0,0 +1,18 @@

26921

+! { dg-do compile }

26922

+!

26923

+! PR 60231: [4.8/4.9 Regression] ICE on undefined generic

26924

+!

26925

+! Contributed by Antony Lewis <antony@cosmologist.info>

26926

+

26927

+module Objects

26928

+

26929

+ Type TObjectList

26930

+ contains

26931

+ procedure :: Add1 ! { dg-error "must be a module procedure" }

26932

+ procedure :: Add2 ! { dg-error "must be a module procedure" }

26933

+ generic :: Add => Add1, Add2 ! { dg-error "are ambiguous" }

26934

+ end Type

26935

+

26936

+end module

26937

+

26938

+! { dg-final { cleanup-modules "Objects" } }

26939

Index: gcc/testsuite/gfortran.dg/extends_15.f90

26940

===================================================================

26941

--- a/src/gcc/testsuite/gfortran.dg/extends_15.f90 (.../tags/gcc_4_8_2_release)

26942

+++ b/src/gcc/testsuite/gfortran.dg/extends_15.f90 (.../branches/gcc-4_8-branch)

26943

@@ -0,0 +1,16 @@

26944

+! { dg-do compile }

26945

+!

26946

+! PR 58355: [4.7/4.8/4.9 Regression] [F03] ICE with TYPE, EXTENDS before parent TYPE defined

26947

+!

26948

+! Contributed by Andrew Benson <abensonca@gmail.com>

26949

+

26950

+module ct

26951

+ public :: t1

26952

+

26953

+ type, extends(t1) :: t2 ! { dg-error "has not been previously defined" }

26954

+

26955

+ type :: t1

26956

+ end type

26957

+end

26958

+

26959

+! { dg-final { cleanup-modules "ct" } }

26960

Index: gcc/testsuite/gfortran.dg/optional_class_1.f90

26961

===================================================================

26962

--- a/src/gcc/testsuite/gfortran.dg/optional_class_1.f90 (.../tags/gcc_4_8_2_release)

26963

+++ b/src/gcc/testsuite/gfortran.dg/optional_class_1.f90 (.../branches/gcc-4_8-branch)

26964

@@ -0,0 +1,45 @@

26965

+! { dg-do run }

26966

+!

26967

+! PR fortran/57445

26968

+!

26969

+! Contributed by Tobias Burnus <burnus@gcc.gnu.org>

26970

+!

26971

+! Spurious assert was added at revision 192495

26972

+!

26973

+module m

26974

+ implicit none

26975

+ type t

26976

+ integer :: i

26977

+ end type t

26978

+contains

26979

+ subroutine opt(xa, xc, xaa, xca)

26980

+ type(t), allocatable, intent(out), optional :: xa

26981

+ class(t), allocatable, intent(out), optional :: xc

26982

+ type(t), allocatable, intent(out), optional :: xaa(:)

26983

+ class(t), allocatable, intent(out), optional :: xca(:)

26984

+ if (present (xca)) call foo_opt(xca=xca)

26985

+ end subroutine opt

26986

+ subroutine foo_opt(xa, xc, xaa, xca)

26987

+ type(t), allocatable, intent(out), optional :: xa

26988

+ class(t), allocatable, intent(out), optional :: xc

26989

+ type(t), allocatable, intent(out), optional :: xaa(:)

26990

+ class(t), allocatable, intent(out), optional :: xca(:)

26991

+ if (present (xca)) then

26992

+ if (allocated (xca)) deallocate (xca)

26993

+ allocate (xca(3), source = [t(9),t(99),t(999)])

26994

+ end if

26995

+ end subroutine foo_opt

26996

+end module m

26997

+ use m

26998

+ class(t), allocatable :: xca(:)

26999

+ allocate (xca(1), source = t(42))

27000

+ select type (xca)

27001

+ type is (t)

27002

+ if (any (xca%i .ne. [42])) call abort

27003

+ end select

27004

+ call opt (xca = xca)

27005

+ select type (xca)

27006

+ type is (t)

27007

+ if (any (xca%i .ne. [9,99,999])) call abort

27008

+ end select

27009

+end

27010

Index: gcc/testsuite/gfortran.dg/dynamic_dispatch_12.f90

27011

===================================================================

27012

--- a/src/gcc/testsuite/gfortran.dg/dynamic_dispatch_12.f90 (.../tags/gcc_4_8_2_release)

27013

+++ b/src/gcc/testsuite/gfortran.dg/dynamic_dispatch_12.f90 (.../branches/gcc-4_8-branch)

27014

@@ -0,0 +1,74 @@

27015

+! { dg-do run }

27016

+!

27017

+! PR 59654: [4.8/4.9 Regression] [OOP] Broken function table with complex OO use case

27018

+!

27019

+! Contributed by Thomas Clune <Thomas.L.Clune@nasa.gov>

27020

+

27021

+module TestResult_mod

27022

+ implicit none

27023

+

27024

+ type TestResult

27025

+ integer :: numRun = 0

27026

+ contains

27027

+ procedure :: run

27028

+ procedure, nopass :: getNumRun

27029

+ end type

27030

+

27031

+contains

27032

+

27033

+ subroutine run (this)

27034

+ class (TestResult) :: this

27035

+ this%numRun = this%numRun + 1

27036

+ end subroutine

27037

+

27038

+ subroutine getNumRun()

27039

+ end subroutine

27040

+

27041

+end module

27042

+

27043

+

27044

+module BaseTestRunner_mod

27045

+ implicit none

27046

+

27047

+ type :: BaseTestRunner

27048

+ contains

27049

+ procedure, nopass :: norun

27050

+ end type

27051

+

27052

+contains

27053

+

27054

+ function norun () result(result)

27055

+ use TestResult_mod, only: TestResult

27056

+ type (TestResult) :: result

27057

+ end function

27058

+

27059

+end module

27060

+

27061

+

27062

+module TestRunner_mod

27063

+ use BaseTestRunner_mod, only: BaseTestRunner

27064

+ implicit none

27065

+end module

27066

+

27067

+

27068

+program main

27069

+ use TestRunner_mod, only: BaseTestRunner

27070

+ use TestResult_mod, only: TestResult

27071

+ implicit none

27072

+

27073

+ type (TestResult) :: result

27074

+

27075

+ call runtest (result)

27076

+

27077

+contains

27078

+

27079

+ subroutine runtest (result)

27080

+ use TestResult_mod, only: TestResult

27081

+ class (TestResult) :: result

27082

+ call result%run()

27083

+ if (result%numRun /= 1) call abort()

27084

+ end subroutine

27085

+

27086

+end

27087

+

27088

+! { dg-final { cleanup-modules "TestResult_mod BaseTestRunner_mod TestRunner_mod" } }

27089

Index: gcc/testsuite/gfortran.dg/proc_ptr_45.f90

27090

===================================================================

27091

--- a/src/gcc/testsuite/gfortran.dg/proc_ptr_45.f90 (.../tags/gcc_4_8_2_release)

27092

+++ b/src/gcc/testsuite/gfortran.dg/proc_ptr_45.f90 (.../branches/gcc-4_8-branch)

27093

@@ -0,0 +1,24 @@

27094

+! { dg-do compile }

27095

+!

27096

+! PR fortran/49397

27097

+!

27098

+! Valid per IR F08/0060 and F2008Corr2, C729

27099

+!

27100

+Program m5

27101

+ Print *,f()

27102

+Contains

27103

+ Subroutine s

27104

+ Procedure(Real),Pointer :: p

27105

+ Print *,g()

27106

+ p => f ! (1)

27107

+ Print *,p()

27108

+ p => g ! (2)

27109

+ Print *,p()

27110

+ End Subroutine

27111

+End Program

27112

+Function f()

27113

+ f = 1

27114

+End Function

27115

+Function g()

27116

+ g = 2

27117

+End Function

27118

Index: gcc/testsuite/gfortran.dg/pr59700.f90

27119

===================================================================

27120

--- a/src/gcc/testsuite/gfortran.dg/pr59700.f90 (.../tags/gcc_4_8_2_release)

27121

+++ b/src/gcc/testsuite/gfortran.dg/pr59700.f90 (.../branches/gcc-4_8-branch)

27122

@@ -0,0 +1,40 @@

27123

+! { dg-do run }

27124

+! PR59700 Test case by Steve Kargl

27125

+program foo

27126

+

27127

+ implicit none

27128

+

27129

+ character(len=80) msg

27130

+ integer, parameter :: fd = 10

27131

+ integer i1, i2, i3, i4

27132

+ real x1, x2, x3, x4

27133

+ complex c1, c2

27134

+ logical a

27135

+

27136

+ open(unit=fd, status='scratch')

27137

+ write(fd, '(A)') '1 2 3.4 q'

27138

+

27139

+ rewind(fd)

27140

+ msg = 'ok'

27141

+ read(fd, *, err=10, iomsg=msg) i1, i2, i3, i4

27142

+10 if (msg /= 'Bad integer for item 3 in list input') call abort

27143

+ rewind(fd)

27144

+ msg = 'ok'

27145

+ read(fd, *, err=20, iomsg=msg) x1, x2, x3, x4

27146

+20 if (msg /= 'Bad real number in item 4 of list input') call abort

27147

+ rewind(fd)

27148

+ msg = 'ok'

27149

+ read(fd, *, err=30, iomsg=msg) i1, x2, x1, a

27150

+30 if (msg /= 'Bad logical value while reading item 4') call abort

27151

+ rewind(fd)

27152

+ read(fd, *, err=31, iomsg=msg) i1, x2, a, x1

27153

+31 if (msg /= 'Bad repeat count in item 3 of list input') call abort

27154

+ close(fd)

27155

+ open(unit=fd, status='scratch')

27156

+ write(fd, '(A)') '(1, 2) (3.4, q)'

27157

+ rewind(fd)

27158

+ msg = 'ok'

27159

+ read(fd, *, err=40, iomsg=msg) c1, c2

27160

+40 if (msg /= 'Bad floating point number for item 2') call abort

27161

+ close(fd)

27162

+end program foo

27163

Index: gcc/testsuite/gfortran.dg/ichar_3.f90

27164

===================================================================

27165

--- a/src/gcc/testsuite/gfortran.dg/ichar_3.f90 (.../tags/gcc_4_8_2_release)

27166

+++ b/src/gcc/testsuite/gfortran.dg/ichar_3.f90 (.../branches/gcc-4_8-branch)

27167

@@ -0,0 +1,13 @@

27168

+! { dg-do compile }

27169

+!

27170

+! PR fortran/59599

27171

+! The call to ichar was triggering an ICE.

27172

+!

27173

+! Original testcase from Fran Martinez Fadrique <fmartinez@gmv.com>

27174

+

27175

+character(1) cpk(2)

27176

+integer res(2)

27177

+cpk = 'a'

27178

+res = ichar( cpk, kind=1 )

27179

+print *, ichar( cpk, kind=1 )

27180

+end

27181

Index: gcc/testsuite/gfortran.dg/unlimited_polymorphic_15.f90

27182

===================================================================

27183

--- a/src/gcc/testsuite/gfortran.dg/unlimited_polymorphic_15.f90 (.../tags/gcc_4_8_2_release)

27184

+++ b/src/gcc/testsuite/gfortran.dg/unlimited_polymorphic_15.f90 (.../branches/gcc-4_8-branch)

27185

@@ -0,0 +1,17 @@

27186

+! { dg-do compile }

27187

+!

27188

+! PR 59493: [OOP] ICE: Segfault on Class(*) pointer association

27189

+!

27190

+! Contributed by Hossein Talebi <talebi.hossein@gmail.com>

27191

+

27192

+ implicit none

27193

+

27194

+ type ty_mytype1

27195

+ end type

27196

+

27197

+ class(ty_mytype1), allocatable, target:: cla1

27198

+ class(*), pointer :: ptr

27199

+

27200

+ ptr => cla1

27201

+

27202

+end

27203

Index: gcc/testsuite/gfortran.dg/fmt_g_1.f90

27204

===================================================================

27205

--- a/src/gcc/testsuite/gfortran.dg/fmt_g_1.f90 (.../tags/gcc_4_8_2_release)

27206

+++ b/src/gcc/testsuite/gfortran.dg/fmt_g_1.f90 (.../branches/gcc-4_8-branch)

27207

@@ -0,0 +1,11 @@

27208

+! { dg-do run }

27209

+! PR59771 Cleanup handling of Gw.0 and Gw.0Ee format

27210

+! Test case prepared by Dominique d'Humieres <dominiq@lps.ens.fr>

27211

+ PROGRAM FOO

27212

+ character(len=60) :: buffer, buffer1

27213

+

27214

+ write (buffer ,'(6(1X,1PG9.0e2))') 0.0, 0.04, 0.06, 0.4, 0.6, 243.0

27215

+ write (buffer1,'(6(1X,1PE9.0e2))') 0.0, 0.04, 0.06, 0.4, 0.6, 243.0

27216

+

27217

+ if (buffer /= buffer1) call abort

27218

+ end

27219

Index: gcc/testsuite/gfortran.dg/elemental_subroutine_9.f90

27220

===================================================================

27221

--- a/src/gcc/testsuite/gfortran.dg/elemental_subroutine_9.f90 (.../tags/gcc_4_8_2_release)

27222

+++ b/src/gcc/testsuite/gfortran.dg/elemental_subroutine_9.f90 (.../branches/gcc-4_8-branch)

27223

@@ -0,0 +1,39 @@

27224

+! { dg-do run }

27225

+!

27226

+! PR fortran/59906

27227

+!

27228

+! Contributed by H Anlauf <anlauf@gmx.de>

27229

+!

27230

+! Failed generate character scalar for scalarized loop for elemantal call.

27231

+!

27232

+program x

27233

+ implicit none

27234

+ call y('bbb')

27235

+contains

27236

+

27237

+ subroutine y(str)

27238

+ character(len=*), intent(in) :: str

27239

+ character(len=len_trim(str)) :: str_aux

27240

+ character(len=3) :: str3 = 'abc'

27241

+

27242

+ str_aux = str

27243

+

27244

+ ! Compiled but did not give correct result

27245

+ if (any (str_cmp((/'aaa','bbb'/), str) .neqv. [.FALSE.,.TRUE.])) call abort

27246

+

27247

+ ! Did not compile

27248

+ if (any (str_cmp((/'bbb', 'aaa'/), str_aux) .neqv. [.TRUE.,.FALSE.])) call abort

27249

+

27250

+ ! Verify patch

27251

+ if (any (str_cmp((/'bbb', 'aaa'/), str3) .neqv. [.FALSE.,.FALSE.])) call abort

27252

+ if (any (str_cmp((/'bbb', 'aaa'/), 'aaa') .neqv. [.FALSE.,.TRUE.])) call abort

27253

+

27254

+ end subroutine y

27255

+

27256

+ elemental logical function str_cmp(str1, str2)

27257

+ character(len=*), intent(in) :: str1

27258

+ character(len=*), intent(in) :: str2

27259

+ str_cmp = (str1 == str2)

27260

+ end function str_cmp

27261

+

27262

+end program x

27263

Index: gcc/testsuite/gcc.c-torture/execute/20140212-1.c

27264

===================================================================

27265

--- a/src/gcc/testsuite/gcc.c-torture/execute/20140212-1.c (.../tags/gcc_4_8_2_release)

27266

+++ b/src/gcc/testsuite/gcc.c-torture/execute/20140212-1.c (.../branches/gcc-4_8-branch)

27267

@@ -0,0 +1,37 @@

27268

+/* PR rtl-optimization/60116 */

27269

+/* Reported by Zhendong Su <su@cs.ucdavis.edu> */

27270

+

27271

+extern void abort (void);

27272

+

27273

+int a, b, c, d = 1, e, f = 1, h, i, k;

27274

+char g, j;

27275

+

27276

+void

27277

+fn1 (void)

27278

+{

27279

+ int l;

27280

+ e = 0;

27281

+ c = 0;

27282

+ for (;;)

27283

+ {

27284

+ k = a && b;

27285

+ j = k * 54;

27286

+ g = j * 147;

27287

+ l = ~g + (long long) e && 1;

27288

+ if (d)

27289

+ c = l;

27290

+ else

27291

+ h = i = l * 9UL;

27292

+ if (f)

27293

+ return;

27294

+ }

27295

+}

27296

+

27297

+int

27298

+main (void)

27299

+{

27300

+ fn1 ();

27301

+ if (c != 1)

27302

+ abort ();

27303

+ return 0;

27304

+}

27305

Index: gcc/testsuite/gcc.c-torture/execute/pr58984.c

27306

===================================================================

27307

--- a/src/gcc/testsuite/gcc.c-torture/execute/pr58984.c (.../tags/gcc_4_8_2_release)

27308

+++ b/src/gcc/testsuite/gcc.c-torture/execute/pr58984.c (.../branches/gcc-4_8-branch)

27309

@@ -0,0 +1,57 @@

27310

+/* PR tree-optimization/58984 */

27311

+

27312

+struct S { int f0 : 8; int : 6; int f1 : 5; };

27313

+struct T { char f0; int : 6; int f1 : 5; };

27314

+

27315

+int a, *c = &a, e, n, b, m;

27316

+

27317

+static int

27318

+foo (struct S p)

27319

+{

27320

+ const unsigned short *f[36];

27321

+ for (; e < 2; e++)

27322

+ {

27323

+ const unsigned short **i = &f[0];

27324

+ *c ^= 1;

27325

+ if (p.f1)

27326

+ {

27327

+ *i = 0;

27328

+ return b;

27329

+ }

27330

+ }

27331

+ return 0;

27332

+}

27333

+

27334

+static int

27335

+bar (struct T p)

27336

+{

27337

+ const unsigned short *f[36];

27338

+ for (; e < 2; e++)

27339

+ {

27340

+ const unsigned short **i = &f[0];

27341

+ *c ^= 1;

27342

+ if (p.f1)

27343

+ {

27344

+ *i = 0;

27345

+ return b;

27346

+ }

27347

+ }

27348

+ return 0;

27349

+}

27350

+

27351

+int

27352

+main ()

27353

+{

27354

+ struct S o = { 1, 1 };

27355

+ foo (o);

27356

+ m = n || o.f0;

27357

+ if (a != 1)

27358

+ __builtin_abort ();

27359

+ e = 0;

27360

+ struct T p = { 1, 1 };

27361

+ bar (p);

27362

+ m |= n || p.f0;

27363

+ if (a != 0)

27364

+ __builtin_abort ();

27365

+ return 0;

27366

+}

27367

Index: gcc/testsuite/gcc.c-torture/execute/pr60454.c

27368

===================================================================

27369

--- a/src/gcc/testsuite/gcc.c-torture/execute/pr60454.c (.../tags/gcc_4_8_2_release)

27370

+++ b/src/gcc/testsuite/gcc.c-torture/execute/pr60454.c (.../branches/gcc-4_8-branch)

27371

@@ -0,0 +1,31 @@

27372

+#ifdef __UINT32_TYPE__

27373

+typedef __UINT32_TYPE__ uint32_t;

27374

+#else

27375

+typedef unsigned uint32_t;

27376

+#endif

27377

+

27378

+#define __fake_const_swab32(x) ((uint32_t)( \

27379

+ (((uint32_t)(x) & (uint32_t)0x000000ffUL) << 24) | \

27380

+ (((uint32_t)(x) & (uint32_t)0x0000ff00UL) << 8) | \

27381

+ (((uint32_t)(x) & (uint32_t)0x000000ffUL) << 8) | \

27382

+ (((uint32_t)(x) & (uint32_t)0x0000ff00UL) ) | \

27383

+ (((uint32_t)(x) & (uint32_t)0xff000000UL) >> 24)))

27384

+

27385

+/* Previous version of bswap optimization would detect byte swap when none

27386

+ happen. This test aims at catching such wrong detection to avoid

27387

+ regressions. */

27388

+

27389

+__attribute__ ((noinline, noclone)) uint32_t

27390

+fake_swap32 (uint32_t in)

27391

+{

27392

+ return __fake_const_swab32 (in);

27393

+}

27394

+

27395

+int main(void)

27396

+{

27397

+ if (sizeof (uint32_t) * __CHAR_BIT__ != 32)

27398

+ return 0;

27399

+ if (fake_swap32 (0x12345678UL) != 0x78567E12UL)

27400

+ __builtin_abort ();

27401

+ return 0;

27402

+}

27403

Index: gcc/testsuite/gcc.c-torture/execute/pr60017.c

27404

===================================================================

27405

--- a/src/gcc/testsuite/gcc.c-torture/execute/pr60017.c (.../tags/gcc_4_8_2_release)

27406

+++ b/src/gcc/testsuite/gcc.c-torture/execute/pr60017.c (.../branches/gcc-4_8-branch)

27407

@@ -0,0 +1,33 @@

27408

+/* PR target/60017 */

27409

+

27410

+extern void abort (void);

27411

+

27412

+struct S0

27413

+{

27414

+ short m0;

27415

+ short m1;

27416

+};

27417

+

27418

+struct S1

27419

+{

27420

+ unsigned m0:1;

27421

+ char m1[2][2];

27422

+ struct S0 m2[2];

27423

+};

27424

+

27425

+struct S1 x = { 1, {{2, 3}, {4, 5}}, {{6, 7}, {8, 9}} };

27426

+

27427

+struct S1 func (void)

27428

+{

27429

+ return x;

27430

+}

27431

+

27432

+int main (void)

27433

+{

27434

+ struct S1 ret = func ();

27435

+

27436

+ if (ret.m2[1].m1 != 9)

27437

+ abort ();

27438

+

27439

+ return 0;

27440

+}

27441

Index: gcc/testsuite/gcc.c-torture/execute/20131127-1.c

27442

===================================================================

27443

--- a/src/gcc/testsuite/gcc.c-torture/execute/20131127-1.c (.../tags/gcc_4_8_2_release)

27444

+++ b/src/gcc/testsuite/gcc.c-torture/execute/20131127-1.c (.../branches/gcc-4_8-branch)

27445

@@ -0,0 +1,34 @@

27446

+/* PR middle-end/59138 */

27447

+/* Testcase by John Regehr <regehr@cs.utah.edu> */

27448

+

27449

+extern void abort (void);

27450

+

27451

+#pragma pack(1)

27452

+

27453

+struct S0 {

27454

+ int f0;

27455

+ int f1;

27456

+ int f2;

27457

+ short f3;

27458

+};

27459

+

27460

+short a = 1;

27461

+

27462

+struct S0 b = { 1 }, c, d, e;

27463

+

27464

+struct S0 fn1() { return c; }

27465

+

27466

+void fn2 (void)

27467

+{

27468

+ b = fn1 ();

27469

+ a = 0;

27470

+ d = e;

27471

+}

27472

+

27473

+int main (void)

27474

+{

27475

+ fn2 ();

27476

+ if (a != 0)

27477

+ abort ();

27478

+ return 0;

27479

+}

27480

Index: gcc/testsuite/gcc.c-torture/execute/pr59358.c

27481

===================================================================

27482

--- a/src/gcc/testsuite/gcc.c-torture/execute/pr59358.c (.../tags/gcc_4_8_2_release)

27483

+++ b/src/gcc/testsuite/gcc.c-torture/execute/pr59358.c (.../branches/gcc-4_8-branch)

27484

@@ -0,0 +1,44 @@

27485

+/* PR tree-optimization/59358 */

27486

+

27487

+__attribute__((noinline, noclone)) int

27488

+foo (int *x, int y)

27489

+{

27490

+ int z = *x;

27491

+ if (y > z && y <= 16)

27492

+ while (y > z)

27493

+ z *= 2;

27494

+ return z;

27495

+}

27496

+

27497

+int

27498

+main ()

27499

+{

27500

+ int i;

27501

+ for (i = 1; i < 17; i++)

27502

+ {

27503

+ int j = foo (&i, 16);

27504

+ int k;

27505

+ if (i >= 8 && i <= 15)

27506

+ k = 16 + (i - 8) * 2;

27507

+ else if (i >= 4 && i <= 7)

27508

+ k = 16 + (i - 4) * 4;

27509

+ else if (i == 3)

27510

+ k = 24;

27511

+ else

27512

+ k = 16;

27513

+ if (j != k)

27514

+ __builtin_abort ();

27515

+ j = foo (&i, 7);

27516

+ if (i >= 7)

27517

+ k = i;

27518

+ else if (i >= 4)

27519

+ k = 8 + (i - 4) * 2;

27520

+ else if (i == 3)

27521

+ k = 12;

27522

+ else

27523

+ k = 8;

27524

+ if (j != k)

27525

+ __builtin_abort ();

27526

+ }

27527

+ return 0;

27528

+}

27529

Index: gcc/testsuite/gcc.c-torture/execute/pr60062.c

27530

===================================================================

27531

--- a/src/gcc/testsuite/gcc.c-torture/execute/pr60062.c (.../tags/gcc_4_8_2_release)

27532

+++ b/src/gcc/testsuite/gcc.c-torture/execute/pr60062.c (.../branches/gcc-4_8-branch)

27533

@@ -0,0 +1,25 @@

27534

+/* PR target/60062 */

27535

+

27536

+int a;

27537

+

27538

+static void

27539

+foo (const char *p1, int p2)

27540

+{

27541

+ if (__builtin_strcmp (p1, "hello") != 0)

27542

+ __builtin_abort ();

27543

+}

27544

+

27545

+static void

27546

+bar (const char *p1)

27547

+{

27548

+ if (__builtin_strcmp (p1, "hello") != 0)

27549

+ __builtin_abort ();

27550

+}

27551

+

27552

+__attribute__((optimize (0))) int

27553

+main ()

27554

+{

27555

+ foo ("hello", a);

27556

+ bar ("hello");

27557

+ return 0;

27558

+}

27559

Index: gcc/testsuite/gcc.c-torture/execute/20140425-1.c

27560

===================================================================

27561

--- a/src/gcc/testsuite/gcc.c-torture/execute/20140425-1.c (.../tags/gcc_4_8_2_release)

27562

+++ b/src/gcc/testsuite/gcc.c-torture/execute/20140425-1.c (.../branches/gcc-4_8-branch)

27563

@@ -0,0 +1,23 @@

27564

+/* PR target/60941 */

27565

+/* Reported by Martin Husemann <martin@netbsd.org> */

27566

+

27567

+extern void abort (void);

27568

+

27569

+static void __attribute__((noinline))

27570

+set (unsigned long *l)

27571

+{

27572

+ *l = 31;

27573

+}

27574

+

27575

+int main (void)

27576

+{

27577

+ unsigned long l;

27578

+ int i;

27579

+

27580

+ set (&l);

27581

+ i = (int) l;

27582

+ l = (unsigned long)(2U << i);

27583

+ if (l != 0)

27584

+ abort ();

27585

+ return 0;

27586

+}

27587

Index: gcc/testsuite/gcc.c-torture/execute/pr59014-2.c

27588

===================================================================

27589

--- a/src/gcc/testsuite/gcc.c-torture/execute/pr59014-2.c (.../tags/gcc_4_8_2_release)

27590

+++ b/src/gcc/testsuite/gcc.c-torture/execute/pr59014-2.c (.../branches/gcc-4_8-branch)

27591

@@ -0,0 +1,23 @@

27592

+/* PR tree-optimization/59014 */

27593

+

27594

+__attribute__((noinline, noclone)) long long int

27595

+foo (long long int x, long long int y)

27596

+{

27597

+ if (((int) x | (int) y) != 0)

27598

+ return 6;

27599

+ return x + y;

27600

+}

27601

+

27602

+int

27603

+main ()

27604

+{

27605

+ if (sizeof (long long) == sizeof (int))

27606

+ return 0;

27607

+ int shift_half = sizeof (int) * __CHAR_BIT__ / 2;

27608

+ long long int x = (3LL << shift_half) << shift_half;

27609

+ long long int y = (5LL << shift_half) << shift_half;

27610

+ long long int z = foo (x, y);

27611

+ if (z != ((8LL << shift_half) << shift_half))

27612

+ __builtin_abort ();

27613

+ return 0;

27614

+}

27615

Index: gcc/testsuite/gcc.c-torture/execute/pr59101.c

27616

===================================================================

27617

--- a/src/gcc/testsuite/gcc.c-torture/execute/pr59101.c (.../tags/gcc_4_8_2_release)

27618

+++ b/src/gcc/testsuite/gcc.c-torture/execute/pr59101.c (.../branches/gcc-4_8-branch)

27619

@@ -0,0 +1,15 @@

27620

+/* PR target/59101 */

27621

+

27622

+__attribute__((noinline, noclone)) int

27623

+foo (int a)

27624

+{

27625

+ return (~a & 4102790424LL) > 0 | 6;

27626

+}

27627

+

27628

+int

27629

+main ()

27630

+{

27631

+ if (foo (0) != 7)

27632

+ __builtin_abort ();

27633

+ return 0;

27634

+}

27635

Index: gcc/testsuite/gcc.c-torture/execute/pr58831.c

27636

===================================================================

27637

--- a/src/gcc/testsuite/gcc.c-torture/execute/pr58831.c (.../tags/gcc_4_8_2_release)

27638

+++ b/src/gcc/testsuite/gcc.c-torture/execute/pr58831.c (.../branches/gcc-4_8-branch)

27639

@@ -0,0 +1,40 @@

27640

+#include <assert.h>

27641

+

27642

+int a, *b, c, d, f, **i, p, q, *r;

27643

+short o, j;

27644

+

27645

+static int __attribute__((noinline, noclone))

27646

+fn1 (int *p1, int **p2)

27647

+{

27648

+ int **e = &b;

27649

+ for (; p; p++)

27650

+ *p1 = 1;

27651

+ *e = *p2 = &d;

27652

+

27653

+ assert (r);

27654

+

27655

+ return c;

27656

+}

27657

+

27658

+static int ** __attribute__((noinline, noclone))

27659

+fn2 (void)

27660

+{

27661

+ for (f = 0; f != 42; f++)

27662

+ {

27663

+ int *g[3] = {0, 0, 0};

27664

+ for (o = 0; o; o--)

27665

+ for (; a > 1;)

27666

+ {

27667

+ int **h[1] = { &g[2] };

27668

+ }

27669

+ }

27670

+ return &r;

27671

+}

27672

+

27673

+int

27674

+main (void)

27675

+{

27676

+ i = fn2 ();

27677

+ fn1 (b, i);

27678

+ return 0;

27679

+}

27680

Index: gcc/testsuite/gcc.c-torture/execute/pr58726.c

27681

===================================================================

27682

--- a/src/gcc/testsuite/gcc.c-torture/execute/pr58726.c (.../tags/gcc_4_8_2_release)

27683

+++ b/src/gcc/testsuite/gcc.c-torture/execute/pr58726.c (.../branches/gcc-4_8-branch)

27684

@@ -0,0 +1,26 @@

27685

+/* PR rtl-optimization/58726 */

27686

+

27687

+int a, c;

27688

+union { int f1; int f2 : 1; } b;

27689

+

27690

+short

27691

+foo (short p)

27692

+{

27693

+ return p < 0 ? p : a;

27694

+}

27695

+

27696

+int

27697

+main ()

27698

+{

27699

+ if (sizeof (short) * __CHAR_BIT__ != 16

27700

+ || sizeof (int) * __CHAR_BIT__ != 32)

27701

+ return 0;

27702

+ b.f1 = 56374;

27703

+ unsigned short d;

27704

+ int e = b.f2;

27705

+ d = e == 0 ? b.f1 : 0;

27706

+ c = foo (d);

27707

+ if (c != (short) 56374)

27708

+ __builtin_abort ();

27709

+ return 0;

27710

+}

27711

Index: gcc/testsuite/gcc.c-torture/execute/pr59014.c

27712

===================================================================

27713

--- a/src/gcc/testsuite/gcc.c-torture/execute/pr59014.c (.../tags/gcc_4_8_2_release)

27714

+++ b/src/gcc/testsuite/gcc.c-torture/execute/pr59014.c (.../branches/gcc-4_8-branch)

27715

@@ -0,0 +1,25 @@

27716

+/* PR tree-optimization/59014 */

27717

+

27718

+int a = 2, b, c, d;

27719

+

27720

+int

27721

+foo ()

27722

+{

27723

+ for (;; c++)

27724

+ if ((b > 0) | (a & 1))

27725

+ ;

27726

+ else

27727

+ {

27728

+ d = a;

27729

+ return 0;

27730

+ }

27731

+}

27732

+

27733

+int

27734

+main ()

27735

+{

27736

+ foo ();

27737

+ if (d != 2)

27738

+ __builtin_abort ();

27739

+ return 0;

27740

+}

27741

Index: gcc/testsuite/gcc.c-torture/execute/pr60960.c

27742

===================================================================

27743

--- a/src/gcc/testsuite/gcc.c-torture/execute/pr60960.c (.../tags/gcc_4_8_2_release)

27744

+++ b/src/gcc/testsuite/gcc.c-torture/execute/pr60960.c (.../branches/gcc-4_8-branch)

27745

@@ -0,0 +1,38 @@

27746

+/* PR tree-optimization/60960 */

27747

+

27748

+typedef unsigned char v4qi __attribute__ ((vector_size (4)));

27749

+

27750

+__attribute__((noinline, noclone)) v4qi

27751

+f1 (v4qi v)

27752

+{

27753

+ return v / 2;

27754

+}

27755

+

27756

+__attribute__((noinline, noclone)) v4qi

27757

+f2 (v4qi v)

27758

+{

27759

+ return v / (v4qi) { 2, 2, 2, 2 };

27760

+}

27761

+

27762

+__attribute__((noinline, noclone)) v4qi

27763

+f3 (v4qi x, v4qi y)

27764

+{

27765

+ return x / y;

27766

+}

27767

+

27768

+int

27769

+main ()

27770

+{

27771

+ v4qi x = { 5, 5, 5, 5 };

27772

+ v4qi y = { 2, 2, 2, 2 };

27773

+ v4qi z = f1 (x);

27774

+ if (__builtin_memcmp (&y, &z, sizeof (y)) != 0)

27775

+ __builtin_abort ();

27776

+ z = f2 (x);

27777

+ if (__builtin_memcmp (&y, &z, sizeof (y)) != 0)

27778

+ __builtin_abort ();

27779

+ z = f3 (x, y);

27780

+ if (__builtin_memcmp (&y, &z, sizeof (y)) != 0)

27781

+ __builtin_abort ();

27782

+ return 0;

27783

+}

27784

Index: gcc/testsuite/gcc.c-torture/execute/pr60072.c

27785

===================================================================

27786

--- a/src/gcc/testsuite/gcc.c-torture/execute/pr60072.c (.../tags/gcc_4_8_2_release)

27787

+++ b/src/gcc/testsuite/gcc.c-torture/execute/pr60072.c (.../branches/gcc-4_8-branch)

27788

@@ -0,0 +1,16 @@

27789

+/* PR target/60072 */

27790

+

27791

+int c = 1;

27792

+

27793

+__attribute__ ((optimize (1)))

27794

+static int *foo (int *p)

27795

+{

27796

+ return p;

27797

+}

27798

+

27799

+int

27800

+main ()

27801

+{

27802

+ *foo (&c) = 2;

27803

+ return c - 2;

27804

+}

27805

Index: gcc/testsuite/gcc.c-torture/execute/20140326-1.c

27806

===================================================================

27807

--- a/src/gcc/testsuite/gcc.c-torture/execute/20140326-1.c (.../tags/gcc_4_8_2_release)

27808

+++ b/src/gcc/testsuite/gcc.c-torture/execute/20140326-1.c (.../branches/gcc-4_8-branch)

27809

@@ -0,0 +1,10 @@

27810

+int a;

27811

+

27812

+int

27813

+main (void)

27814

+{

27815

+ char e[2] = { 0, 0 }, f = 0;

27816

+ if (a == 131072)

27817

+ f = e[a];

27818

+ return f;

27819

+}

27820

Index: gcc/testsuite/gcc.c-torture/execute/pr59388.c

27821

===================================================================

27822

--- a/src/gcc/testsuite/gcc.c-torture/execute/pr59388.c (.../tags/gcc_4_8_2_release)

27823

+++ b/src/gcc/testsuite/gcc.c-torture/execute/pr59388.c (.../branches/gcc-4_8-branch)

27824

@@ -0,0 +1,11 @@

27825

+/* PR tree-optimization/59388 */

27826

+

27827

+int a;

27828

+struct S { unsigned int f:1; } b;

27829

+

27830

+int

27831

+main ()

27832

+{

27833

+ a = (0 < b.f) | b.f;

27834

+ return a;

27835

+}

27836

Index: gcc/testsuite/gcc.c-torture/compile/pr58970-1.c

27837

===================================================================

27838

--- a/src/gcc/testsuite/gcc.c-torture/compile/pr58970-1.c (.../tags/gcc_4_8_2_release)

27839

+++ b/src/gcc/testsuite/gcc.c-torture/compile/pr58970-1.c (.../branches/gcc-4_8-branch)

27840

@@ -0,0 +1,11 @@

27841

+/* PR middle-end/58970 */

27842

+

27843

+struct T { int b : 1; };

27844

+struct S { struct T t[1]; };

27845

+

27846

+void

27847

+foo (int x, struct S *s)

27848

+{

27849

+ if (x == -1)

27850

+ s->t[x].b = 0;

27851

+}

27852

Index: gcc/testsuite/gcc.c-torture/compile/pr59803.c

27853

===================================================================

27854

--- a/src/gcc/testsuite/gcc.c-torture/compile/pr59803.c (.../tags/gcc_4_8_2_release)

27855

+++ b/src/gcc/testsuite/gcc.c-torture/compile/pr59803.c (.../branches/gcc-4_8-branch)

27856

@@ -0,0 +1,27 @@

27857

+/* PR target/59803 */

27858

+

27859

+extern void baz (void) __attribute__ ((__noreturn__));

27860

+struct A { int g, h; };

27861

+extern struct A a;

27862

+struct B { unsigned char i, j, k, l, m; };

27863

+int c, d, e;

27864

+static int f;

27865

+

27866

+void

27867

+foo (void)

27868

+{

27869

+ f = 1;

27870

+}

27871

+

27872

+void

27873

+bar (struct B *x)

27874

+{

27875

+ x->i = e;

27876

+ x->k = c;

27877

+ x->l = d;

27878

+ x->j = a.h;

27879

+ x->m = f;

27880

+ if (x->i != e) baz ();

27881

+ if (x->k != c) baz ();

27882

+ if (x->j != a.h) baz ();

27883

+}

27884

Index: gcc/testsuite/gcc.c-torture/compile/pr58997.c

27885

===================================================================

27886

--- a/src/gcc/testsuite/gcc.c-torture/compile/pr58997.c (.../tags/gcc_4_8_2_release)

27887

+++ b/src/gcc/testsuite/gcc.c-torture/compile/pr58997.c (.../branches/gcc-4_8-branch)

27888

@@ -0,0 +1,19 @@

27889

+/* PR rtl-optimization/58997 */

27890

+

27891

+int a, b, c, e;

27892

+short d;

27893

+char h;

27894

+

27895

+void

27896

+foo ()

27897

+{

27898

+ while (b)

27899

+ {

27900

+ d = a ? c : 1 % a;

27901

+ c = d;

27902

+ h = d;

27903

+ if (!h)

27904

+ while (e)

27905

+ ;

27906

+ }

27907

+}

27908

Index: gcc/testsuite/gcc.c-torture/compile/pr60502.c

27909

===================================================================

27910

--- a/src/gcc/testsuite/gcc.c-torture/compile/pr60502.c (.../tags/gcc_4_8_2_release)

27911

+++ b/src/gcc/testsuite/gcc.c-torture/compile/pr60502.c (.../branches/gcc-4_8-branch)

27912

@@ -0,0 +1,18 @@

27913

+/* PR tree-optimization/60502 */

27914

+

27915

+typedef signed char v16i8 __attribute__ ((vector_size (16)));

27916

+typedef unsigned char v16u8 __attribute__ ((vector_size (16)));

27917

+

27918

+void

27919

+foo (v16i8 *x)

27920

+{

27921

+ v16i8 m1 = { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 };

27922

+ *x |= *x ^ m1;

27923

+}

27924

+

27925

+void

27926

+bar (v16u8 *x)

27927

+{

27928

+ v16u8 m1 = { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 };

27929

+ *x |= *x ^ m1;

27930

+}

27931

Index: gcc/testsuite/gcc.c-torture/compile/pr58970-2.c

27932

===================================================================

27933

--- a/src/gcc/testsuite/gcc.c-torture/compile/pr58970-2.c (.../tags/gcc_4_8_2_release)

27934

+++ b/src/gcc/testsuite/gcc.c-torture/compile/pr58970-2.c (.../branches/gcc-4_8-branch)

27935

@@ -0,0 +1,11 @@

27936

+/* PR middle-end/58970 */

27937

+

27938

+struct T { char a : 8; char b : 1; };

27939

+struct S { char x; struct T t[1]; };

27940

+

27941

+void

27942

+foo (int x, struct S *s)

27943

+{

27944

+ if (x == -1)

27945

+ s->t[x].b = 0;

27946

+}

27947

Index: gcc/testsuite/gcc.c-torture/compile/pr59362.c

27948

===================================================================

27949

--- a/src/gcc/testsuite/gcc.c-torture/compile/pr59362.c (.../tags/gcc_4_8_2_release)

27950

+++ b/src/gcc/testsuite/gcc.c-torture/compile/pr59362.c (.../branches/gcc-4_8-branch)

27951

@@ -0,0 +1,21 @@

27952

+/* PR tree-optimization/59362 */

27953

+

27954

+char *

27955

+foo (char *r, int s)

27956

+{

27957

+ r = __builtin___stpcpy_chk (r, "abc", __builtin_object_size (r, 1));

27958

+ if (s)

27959

+ r = __builtin___stpcpy_chk (r, "d", __builtin_object_size (r, 1));

27960

+ return r;

27961

+}

27962

+

27963

+char *a;

27964

+long int b;

27965

+

27966

+void

27967

+bar (void)

27968

+{

27969

+ b = __builtin_object_size (0, 0);

27970

+ a = __builtin___stpcpy_chk (0, "", b);

27971

+ b = __builtin_object_size (a, 0);

27972

+}

27973

Index: gcc/testsuite/gnat.dg/opt32.adb

27974

===================================================================

27975

--- a/src/gcc/testsuite/gnat.dg/opt32.adb (.../tags/gcc_4_8_2_release)

27976

+++ b/src/gcc/testsuite/gnat.dg/opt32.adb (.../branches/gcc-4_8-branch)

27977

@@ -0,0 +1,37 @@

27978

+-- { dg-do compile }

27979

+-- { dg-options "-O2" }

27980

+

27981

+with Ada.Containers; use Ada.Containers;

27982

+with Ada.Containers.Vectors;

27983

+

27984

+function Opt32 return Natural is

27985

+

27986

+ package My_Vectors

27987

+ is new Vectors (Index_Type => Natural, Element_Type => Integer);

27988

+ use My_Vectors;

27989

+

27990

+ V : Vector;

27991

+

27992

+ function Sign_Changes return Natural is

27993

+ Cur : Cursor := To_Cursor (V, 0);

27994

+ R : Natural := 0;

27995

+ Negative : Boolean;

27996

+ begin

27997

+ Negative := Element (Cur) < 0;

27998

+

27999

+ loop

28000

+ Cur := Next (Cur);

28001

+ exit when R > 100;

28002

+

28003

+ if (Element (Cur) < 0) /= Negative then

28004

+ Negative := not Negative;

28005

+ R := R + 1;

28006

+ end if;

28007

+ end loop;

28008

+

28009

+ return R;

28010

+ end;

28011

+

28012

+begin

28013

+ return Sign_Changes;

28014

+end;

28015

Index: gcc/testsuite/gcc.dg/pr58668.c

28016

===================================================================

28017

--- a/src/gcc/testsuite/gcc.dg/pr58668.c (.../tags/gcc_4_8_2_release)

28018

+++ b/src/gcc/testsuite/gcc.dg/pr58668.c (.../branches/gcc-4_8-branch)

28019

@@ -0,0 +1,25 @@

28020

+/* PR rtl-optimization/58668 */

28021

+/* { dg-do compile } */

28022

+/* { dg-options "-O2" } */

28023

+/* { dg-additional-options "-mthumb" { target { { arm*-*-* } && arm_thumb2_ok } } } */

28024

+

28025

+void *fn1 (void *);

28026

+void *fn2 (void *, const char *);

28027

+void fn3 (void *);

28028

+void fn4 (void *, int);

28029

+

28030

+void *

28031

+test (void *x)

28032

+{

28033

+ void *a, *b;

28034

+ if (!(a = fn1 (x)))

28035

+ return (void *) 0;

28036

+ if (!(b = fn2 (a, "w")))

28037

+ {

28038

+ fn3 (a);

28039

+ return (void *) 0;

28040

+ }

28041

+ fn3 (a);

28042

+ fn4 (b, 1);

28043

+ return b;

28044

+}

28045

Index: gcc/testsuite/gcc.dg/pr57518.c

28046

===================================================================

28047

--- a/src/gcc/testsuite/gcc.dg/pr57518.c (.../tags/gcc_4_8_2_release)

28048

+++ b/src/gcc/testsuite/gcc.dg/pr57518.c (.../branches/gcc-4_8-branch)

28049

@@ -1,8 +1,8 @@

28050

-/* PR rtl-optimization/57130 */

28051

+/* PR rtl-optimization/57518 */

28052

28053

/* { dg-do compile } */

28054

/* { dg-options "-O2 -fdump-rtl-ira" } */

28055

-/* { dg-final { scan-rtl-dump-not "REG_EQUIV.*mem.*\"ip\"" "ira" } } */

28056

+/* { dg-final { scan-rtl-dump-not "REG_EQUIV\[^\n\]*mem\[^\n\]*\"ip\".*subreg" "ira" } } */

28057

28058

char ip[10];

28059

int total;

28060

Index: gcc/testsuite/gcc.dg/builtin-object-size-14.c

28061

===================================================================

28062

--- a/src/gcc/testsuite/gcc.dg/builtin-object-size-14.c (.../tags/gcc_4_8_2_release)

28063

+++ b/src/gcc/testsuite/gcc.dg/builtin-object-size-14.c (.../branches/gcc-4_8-branch)

28064

@@ -0,0 +1,28 @@

28065

+/* { dg-do run } */

28066

+/* { dg-options "-O2" } */

28067

+

28068

+extern void abort (void);

28069

+extern char *strncpy(char *, const char *, __SIZE_TYPE__);

28070

+

28071

+union u {

28072

+ struct {

28073

+ char vi[8];

28074

+ char pi[16];

28075

+ };

28076

+ char all[8+16+4];

28077

+};

28078

+

28079

+void __attribute__((noinline,noclone))

28080

+f(union u *u)

28081

+{

28082

+ char vi[8+1];

28083

+ __builtin_strncpy(vi, u->vi, sizeof(u->vi));

28084

+ if (__builtin_object_size (u->all, 1) != -1)

28085

+ abort ();

28086

+}

28087

+int main()

28088

+{

28089

+ union u u;

28090

+ f (&u);

28091

+ return 0;

28092

+}

28093

Index: gcc/testsuite/gcc.dg/gomp/pr58809.c

28094

===================================================================

28095

--- a/src/gcc/testsuite/gcc.dg/gomp/pr58809.c (.../tags/gcc_4_8_2_release)

28096

+++ b/src/gcc/testsuite/gcc.dg/gomp/pr58809.c (.../branches/gcc-4_8-branch)

28097

@@ -0,0 +1,13 @@

28098

+/* PR middle-end/58809 */

28099

+/* { dg-do compile } */

28100

+/* { dg-options "-fopenmp -O" } */

28101

+

28102

+int i;

28103

+#pragma omp threadprivate (i)

28104

+

28105

+void foo()

28106

+{

28107

+ _Complex int j;

28108

+#pragma omp parallel copyin (i) reduction (&&:j)

28109

+ ;

28110

+}

28111

Index: gcc/testsuite/gcc.dg/20050922-1.c

28112

===================================================================

28113

--- a/src/gcc/testsuite/gcc.dg/20050922-1.c (.../tags/gcc_4_8_2_release)

28114

+++ b/src/gcc/testsuite/gcc.dg/20050922-1.c (.../branches/gcc-4_8-branch)

28115

@@ -4,7 +4,7 @@

28116

/* { dg-do run } */

28117

/* { dg-options "-O1 -std=c99" } */

28118

28119

-#include <stdlib.h>

28120

+extern void abort (void);

28121

28122

#if __INT_MAX__ == 2147483647

28123

typedef unsigned int uint32_t;

28124

Index: gcc/testsuite/gcc.dg/pr46309.c

28125

===================================================================

28126

--- a/src/gcc/testsuite/gcc.dg/pr46309.c (.../tags/gcc_4_8_2_release)

28127

+++ b/src/gcc/testsuite/gcc.dg/pr46309.c (.../branches/gcc-4_8-branch)

28128

@@ -1,5 +1,5 @@

28129

/* PR tree-optimization/46309 */

28130

-/* { dg-do compile } */

28131

+/* { dg-do compile { target { ! { cris*-*-* } } } } */

28132

/* { dg-options "-O2 -fdump-tree-reassoc-details" } */

28133

/* The transformation depends on BRANCH_COST being greater than 1

28134

(see the notes in the PR), so try to force that. */

28135

Index: gcc/testsuite/gcc.dg/pr60485-2.c

28136

===================================================================

28137

--- a/src/gcc/testsuite/gcc.dg/pr60485-2.c (.../tags/gcc_4_8_2_release)

28138

+++ b/src/gcc/testsuite/gcc.dg/pr60485-2.c (.../branches/gcc-4_8-branch)

28139

@@ -0,0 +1,38 @@

28140

+/* { dg-do run } */

28141

+/* { dg-options "-O2" } */

28142

+

28143

+extern void abort (void);

28144

+struct S {

28145

+ int *i[4];

28146

+ int *p1;

28147

+ int *p2;

28148

+ int *p3;

28149

+ int *p4;

28150

+ int **x;

28151

+};

28152

+int **b;

28153

+int main()

28154

+{

28155

+ int i = 1;

28156

+ struct S s;

28157

+ s.p3 = &i;

28158

+ int **p;

28159

+ if (b)

28160

+ p = b;

28161

+ else

28162

+ p = &s.i[2];

28163

+ p += 4;

28164

+ /* prevert fowrprop from creating an offsetted sd constraint and

28165

+ preserve the pointer offsetting constraint. */

28166

+ s.x = p;

28167

+ p = s.x;

28168

+ if (!b)

28169

+ {

28170

+ int *z = *p;

28171

+ /* z should point to i (and non-local/escaped). */

28172

+ *z = 0;

28173

+ }

28174

+ if (i != 0)

28175

+ abort ();

28176

+ return i;

28177

+}

28178

Index: gcc/testsuite/gcc.dg/atomic-store-6.c

28179

===================================================================

28180

--- a/src/gcc/testsuite/gcc.dg/atomic-store-6.c (.../tags/gcc_4_8_2_release)

28181

+++ b/src/gcc/testsuite/gcc.dg/atomic-store-6.c (.../branches/gcc-4_8-branch)

28182

@@ -0,0 +1,13 @@

28183

+/* { dg-do run } */

28184

+/* { dg-require-effective-target sync_int_128_runtime } */

28185

+/* { dg-options "-mcx16" { target { i?86-*-* x86_64-*-* } } } */

28186

+

28187

+__int128_t i;

28188

+

28189

+int main()

28190

+{

28191

+ __atomic_store_16(&i, -1, 0);

28192

+ if (i != -1)

28193

+ __builtin_abort();

28194

+ return 0;

28195

+}

28196

Index: gcc/testsuite/gcc.dg/guality/pr59776.c

28197

===================================================================

28198

--- a/src/gcc/testsuite/gcc.dg/guality/pr59776.c (.../tags/gcc_4_8_2_release)

28199

+++ b/src/gcc/testsuite/gcc.dg/guality/pr59776.c (.../branches/gcc-4_8-branch)

28200

@@ -0,0 +1,29 @@

28201

+/* PR debug/59776 */

28202

+/* { dg-do run } */

28203

+/* { dg-options "-g" } */

28204

+

28205

+#include "../nop.h"

28206

+

28207

+struct S { float f, g; };

28208

+

28209

+__attribute__((noinline, noclone)) void

28210

+foo (struct S *p)

28211

+{

28212

+ struct S s1, s2; /* { dg-final { gdb-test pr59776.c:17 "s1.f" "5.0" } } */

28213

+ s1 = *p; /* { dg-final { gdb-test pr59776.c:17 "s1.g" "6.0" } } */

28214

+ s2 = s1; /* { dg-final { gdb-test pr59776.c:17 "s2.f" "0.0" } } */

28215

+ *(int *) &s2.f = 0; /* { dg-final { gdb-test pr59776.c:17 "s2.g" "6.0" } } */

28216

+ asm volatile (NOP : : : "memory"); /* { dg-final { gdb-test pr59776.c:20 "s1.f" "5.0" } } */

28217

+ asm volatile (NOP : : : "memory"); /* { dg-final { gdb-test pr59776.c:20 "s1.g" "6.0" } } */

28218

+ s2 = s1; /* { dg-final { gdb-test pr59776.c:20 "s2.f" "5.0" } } */

28219

+ asm volatile (NOP : : : "memory"); /* { dg-final { gdb-test pr59776.c:20 "s2.g" "6.0" } } */

28220

+ asm volatile (NOP : : : "memory");

28221

+}

28222

+

28223

+int

28224

+main ()

28225

+{

28226

+ struct S x = { 5.0f, 6.0f };

28227

+ foo (&x);

28228

+ return 0;

28229

+}

28230

Index: gcc/testsuite/gcc.dg/attr-weakref-1.c

28231

===================================================================

28232

--- a/src/gcc/testsuite/gcc.dg/attr-weakref-1.c (.../tags/gcc_4_8_2_release)

28233

+++ b/src/gcc/testsuite/gcc.dg/attr-weakref-1.c (.../branches/gcc-4_8-branch)

28234

@@ -4,12 +4,14 @@

28235

// This test requires support for undefined weak symbols. This support

28236

// is not available on hppa*-*-hpux*. The test is skipped rather than

28237

// xfailed to suppress the warning that would otherwise arise.

28238

-// { dg-skip-if "" { "*-*-darwin*" "hppa*-*-hpux*" } "*" { "" } }

28239

+// { dg-skip-if "" { "hppa*-*-hpux*" } "*" { "" } }

28240

// For kernel modules and static RTPs, the loader treats undefined weak

28241

// symbols in the same way as undefined strong symbols. The test

28242

// therefore fails to load, so skip it.

28243

// { dg-skip-if "" { "*-*-vxworks*" && nonpic } "*" { "-non-static" } }

28244

// { dg-options "-O2" }

28245

+// { dg-additional-options "-Wl,-undefined,dynamic_lookup" { target *-*-darwin* } }

28246

+// { dg-additional-options "-Wl,-flat_namespace" { target *-*-darwin[89]* } }

28247

// { dg-additional-sources "attr-weakref-1a.c" }

28248

28249

28250

Index: gcc/testsuite/gcc.dg/pr59827.c

28251

===================================================================

28252

--- a/src/gcc/testsuite/gcc.dg/pr59827.c (.../tags/gcc_4_8_2_release)

28253

+++ b/src/gcc/testsuite/gcc.dg/pr59827.c (.../branches/gcc-4_8-branch)

28254

@@ -0,0 +1,15 @@

28255

+/* PR middle-end/59827 */

28256

+/* { dg-do compile } */

28257

+

28258

+int

28259

+foo (int p[2][]) /* { dg-error "array type has incomplete element type" } */

28260

+{

28261

+ return p[0][0];

28262

+}

28263

+

28264

+void

28265

+bar (void)

28266

+{

28267

+ int p[2][1];

28268

+ foo (p); /* { dg-error "type of formal parameter 1 is incomplete" } */

28269

+}

28270

Index: gcc/testsuite/gcc.dg/vmx/stl-be-order.c

28271

===================================================================

28272

--- a/src/gcc/testsuite/gcc.dg/vmx/stl-be-order.c (.../tags/gcc_4_8_2_release)

28273

+++ b/src/gcc/testsuite/gcc.dg/vmx/stl-be-order.c (.../branches/gcc-4_8-branch)

28274

@@ -0,0 +1,83 @@

28275

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */

28276

+

28277

+#include "harness.h"

28278

+

28279

+static unsigned char svuc[16] __attribute__ ((aligned (16)));

28280

+static signed char svsc[16] __attribute__ ((aligned (16)));

28281

+static unsigned char svbc[16] __attribute__ ((aligned (16)));

28282

+static unsigned short svus[8] __attribute__ ((aligned (16)));

28283

+static signed short svss[8] __attribute__ ((aligned (16)));

28284

+static unsigned short svbs[8] __attribute__ ((aligned (16)));

28285

+static unsigned short svp[8] __attribute__ ((aligned (16)));

28286

+static unsigned int svui[4] __attribute__ ((aligned (16)));

28287

+static signed int svsi[4] __attribute__ ((aligned (16)));

28288

+static unsigned int svbi[4] __attribute__ ((aligned (16)));

28289

+static float svf[4] __attribute__ ((aligned (16)));

28290

+

28291

+static void check_arrays ()

28292

+{

28293

+ unsigned int i;

28294

+ for (i = 0; i < 16; ++i)

28295

+ {

28296

+ check (svuc[i] == i, "svuc");

28297

+ check (svsc[i] == i - 8, "svsc");

28298

+ check (svbc[i] == ((i % 2) ? 0xff : 0), "svbc");

28299

+ }

28300

+ for (i = 0; i < 8; ++i)

28301

+ {

28302

+ check (svus[i] == i, "svus");

28303

+ check (svss[i] == i - 4, "svss");

28304

+ check (svbs[i] == ((i % 2) ? 0xffff : 0), "svbs");

28305

+ check (svp[i] == i, "svp");

28306

+ }

28307

+ for (i = 0; i < 4; ++i)

28308

+ {

28309

+ check (svui[i] == i, "svui");

28310

+ check (svsi[i] == i - 2, "svsi");

28311

+ check (svbi[i] == ((i % 2) ? 0xffffffff : 0), "svbi");

28312

+ check (svf[i] == i * 1.0f, "svf");

28313

+ }

28314

+}

28315

+

28316

+static void test ()

28317

+{

28318

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

28319

+ vector unsigned char vuc = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};

28320

+ vector signed char vsc = {7,6,5,4,3,2,1,0,-1,-2,-3,-4,-5,-6,-7,-8};

28321

+ vector bool char vbc = {255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0};

28322

+ vector unsigned short vus = {7,6,5,4,3,2,1,0};

28323

+ vector signed short vss = {3,2,1,0,-1,-2,-3,-4};

28324

+ vector bool short vbs = {65535,0,65535,0,65535,0,65535,0};

28325

+ vector pixel vp = {7,6,5,4,3,2,1,0};

28326

+ vector unsigned int vui = {3,2,1,0};

28327

+ vector signed int vsi = {1,0,-1,-2};

28328

+ vector bool int vbi = {0xffffffff,0,0xffffffff,0};

28329

+ vector float vf = {3.0,2.0,1.0,0.0};

28330

+#else

28331

+ vector unsigned char vuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

28332

+ vector signed char vsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};

28333

+ vector bool char vbc = {0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255};

28334

+ vector unsigned short vus = {0,1,2,3,4,5,6,7};

28335

+ vector signed short vss = {-4,-3,-2,-1,0,1,2,3};

28336

+ vector bool short vbs = {0,65535,0,65535,0,65535,0,65535};

28337

+ vector pixel vp = {0,1,2,3,4,5,6,7};

28338

+ vector unsigned int vui = {0,1,2,3};

28339

+ vector signed int vsi = {-2,-1,0,1};

28340

+ vector bool int vbi = {0,0xffffffff,0,0xffffffff};

28341

+ vector float vf = {0.0,1.0,2.0,3.0};

28342

+#endif

28343

+

28344

+ vec_stl (vuc, 0, (vector unsigned char *)svuc);

28345

+ vec_stl (vsc, 0, (vector signed char *)svsc);

28346

+ vec_stl (vbc, 0, (vector bool char *)svbc);

28347

+ vec_stl (vus, 0, (vector unsigned short *)svus);

28348

+ vec_stl (vss, 0, (vector signed short *)svss);

28349

+ vec_stl (vbs, 0, (vector bool short *)svbs);

28350

+ vec_stl (vp, 0, (vector pixel *)svp);

28351

+ vec_stl (vui, 0, (vector unsigned int *)svui);

28352

+ vec_stl (vsi, 0, (vector signed int *)svsi);

28353

+ vec_stl (vbi, 0, (vector bool int *)svbi);

28354

+ vec_stl (vf, 0, (vector float *)svf);

28355

+

28356

+ check_arrays ();

28357

+}

28358

Index: gcc/testsuite/gcc.dg/vmx/perm-be-order.c

28359

===================================================================

28360

--- a/src/gcc/testsuite/gcc.dg/vmx/perm-be-order.c (.../tags/gcc_4_8_2_release)

28361

+++ b/src/gcc/testsuite/gcc.dg/vmx/perm-be-order.c (.../branches/gcc-4_8-branch)

28362

@@ -0,0 +1,74 @@

28363

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */

28364

+

28365

+#include "harness.h"

28366

+

28367

+static void test()

28368

+{

28369

+ /* Input vectors. */

28370

+ vector unsigned char vuca = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

28371

+ vector unsigned char vucb = {16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31};

28372

+ vector signed char vsca = {-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1};

28373

+ vector signed char vscb = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

28374

+ vector unsigned short vusa = {0,1,2,3,4,5,6,7};

28375

+ vector unsigned short vusb = {8,9,10,11,12,13,14,15};

28376

+ vector signed short vssa = {-8,-7,-6,-5,-4,-3,-2,-1};

28377

+ vector signed short vssb = {0,1,2,3,4,5,6,7};

28378

+ vector unsigned int vuia = {0,1,2,3};

28379

+ vector unsigned int vuib = {4,5,6,7};

28380

+ vector signed int vsia = {-4,-3,-2,-1};

28381

+ vector signed int vsib = {0,1,2,3};

28382

+ vector float vfa = {-4.0,-3.0,-2.0,-1.0};

28383

+ vector float vfb = {0.0,1.0,2.0,3.0};

28384

+

28385

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

28386

+ vector unsigned char vucp = {15,16,14,17,13,18,12,19,11,20,10,21,9,22,8,23};

28387

+ vector unsigned char vscp = {15,16,14,17,13,18,12,19,11,20,10,21,9,22,8,23};

28388

+ vector unsigned char vusp = {15,14,17,16,13,12,19,18,11,10,21,20,9,8,23,22};

28389

+ vector unsigned char vssp = {15,14,17,16,13,12,19,18,11,10,21,20,9,8,23,22};

28390

+ vector unsigned char vuip = {15,14,13,12,19,18,17,16,11,10,9,8,23,22,21,20};

28391

+ vector unsigned char vsip = {15,14,13,12,19,18,17,16,11,10,9,8,23,22,21,20};

28392

+ vector unsigned char vfp = {15,14,13,12,19,18,17,16,11,10,9,8,23,22,21,20};

28393

+#else

28394

+ vector unsigned char vucp = {0,31,1,30,2,29,3,28,4,27,5,26,6,25,7,24};

28395

+ vector unsigned char vscp = {0,31,1,30,2,29,3,28,4,27,5,26,6,25,7,24};

28396

+ vector unsigned char vusp = {0,1,30,31,2,3,28,29,4,5,26,27,6,7,24,25};

28397

+ vector unsigned char vssp = {0,1,30,31,2,3,28,29,4,5,26,27,6,7,24,25};

28398

+ vector unsigned char vuip = {0,1,2,3,28,29,30,31,4,5,6,7,24,25,26,27};

28399

+ vector unsigned char vsip = {0,1,2,3,28,29,30,31,4,5,6,7,24,25,26,27};

28400

+ vector unsigned char vfp = {0,1,2,3,28,29,30,31,4,5,6,7,24,25,26,27};

28401

+#endif

28402

+

28403

+ /* Result vectors. */

28404

+ vector unsigned char vuc;

28405

+ vector signed char vsc;

28406

+ vector unsigned short vus;

28407

+ vector signed short vss;

28408

+ vector unsigned int vui;

28409

+ vector signed int vsi;

28410

+ vector float vf;

28411

+

28412

+ /* Expected result vectors. */

28413

+ vector unsigned char vucr = {0,31,1,30,2,29,3,28,4,27,5,26,6,25,7,24};

28414

+ vector signed char vscr = {-16,15,-15,14,-14,13,-13,12,-12,11,-11,10,-10,9,-9,8};

28415

+ vector unsigned short vusr = {0,15,1,14,2,13,3,12};

28416

+ vector signed short vssr = {-8,7,-7,6,-6,5,-5,4};

28417

+ vector unsigned int vuir = {0,7,1,6};

28418

+ vector signed int vsir = {-4,3,-3,2};

28419

+ vector float vfr = {-4.0,3.0,-3.0,2.0};

28420

+

28421

+ vuc = vec_perm (vuca, vucb, vucp);

28422

+ vsc = vec_perm (vsca, vscb, vscp);

28423

+ vus = vec_perm (vusa, vusb, vusp);

28424

+ vss = vec_perm (vssa, vssb, vssp);

28425

+ vui = vec_perm (vuia, vuib, vuip);

28426

+ vsi = vec_perm (vsia, vsib, vsip);

28427

+ vf = vec_perm (vfa, vfb, vfp );

28428

+

28429

+ check (vec_all_eq (vuc, vucr), "vuc");

28430

+ check (vec_all_eq (vsc, vscr), "vsc");

28431

+ check (vec_all_eq (vus, vusr), "vus");

28432

+ check (vec_all_eq (vss, vssr), "vss");

28433

+ check (vec_all_eq (vui, vuir), "vui");

28434

+ check (vec_all_eq (vsi, vsir), "vsi");

28435

+ check (vec_all_eq (vf, vfr), "vf" );

28436

+}

28437

Index: gcc/testsuite/gcc.dg/vmx/insert-be-order.c

28438

===================================================================

28439

--- a/src/gcc/testsuite/gcc.dg/vmx/insert-be-order.c (.../tags/gcc_4_8_2_release)

28440

+++ b/src/gcc/testsuite/gcc.dg/vmx/insert-be-order.c (.../branches/gcc-4_8-branch)

28441

@@ -0,0 +1,65 @@

28442

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */

28443

+

28444

+#include "harness.h"

28445

+

28446

+static void test()

28447

+{

28448

+ vector unsigned char va = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

28449

+ vector signed char vb = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};

28450

+ vector unsigned short vc = {0,1,2,3,4,5,6,7};

28451

+ vector signed short vd = {-4,-3,-2,-1,0,1,2,3};

28452

+ vector unsigned int ve = {0,1,2,3};

28453

+ vector signed int vf = {-2,-1,0,1};

28454

+ vector float vg = {-2.0f,-1.0f,0.0f,1.0f};

28455

+

28456

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

28457

+ check (vec_all_eq (vec_insert (16, va, 5),

28458

+ ((vector unsigned char)

28459

+ {0,1,2,3,4,5,6,7,8,9,16,11,12,13,14,15})),

28460

+ "vec_insert (va LE)");

28461

+ check (vec_all_eq (vec_insert (-16, vb, 0),

28462

+ ((vector signed char)

28463

+ {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,-16})),

28464

+ "vec_insert (vb LE)");

28465

+ check (vec_all_eq (vec_insert (16, vc, 7),

28466

+ ((vector unsigned short){16,1,2,3,4,5,6,7})),

28467

+ "vec_insert (vc LE)");

28468

+ check (vec_all_eq (vec_insert (-16, vd, 3),

28469

+ ((vector signed short){-4,-3,-2,-1,-16,1,2,3})),

28470

+ "vec_insert (vd LE)");

28471

+ check (vec_all_eq (vec_insert (16, ve, 2),

28472

+ ((vector unsigned int){0,16,2,3})),

28473

+ "vec_insert (ve LE)");

28474

+ check (vec_all_eq (vec_insert (-16, vf, 1),

28475

+ ((vector signed int){-2,-1,-16,1})),

28476

+ "vec_insert (vf LE)");

28477

+ check (vec_all_eq (vec_insert (-16.0f, vg, 0),

28478

+ ((vector float){-2.0f,-1.0f,0.0f,-16.0f})),

28479

+ "vec_insert (vg LE)");

28480

+#else

28481

+ check (vec_all_eq (vec_insert (16, va, 5),

28482

+ ((vector unsigned char)

28483

+ {0,1,2,3,4,16,6,7,8,9,10,11,12,13,14,15})),

28484

+ "vec_insert (va BE)");

28485

+ check (vec_all_eq (vec_insert (-16, vb, 0),

28486

+ ((vector signed char)

28487

+ {-16,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7})),

28488

+ "vec_insert (vb BE)");

28489

+ check (vec_all_eq (vec_insert (16, vc, 7),

28490

+ ((vector unsigned short){0,1,2,3,4,5,6,16})),

28491

+ "vec_insert (vc BE)");

28492

+ check (vec_all_eq (vec_insert (-16, vd, 3),

28493

+ ((vector signed short){-4,-3,-2,-16,0,1,2,3})),

28494

+ "vec_insert (vd BE)");

28495

+ check (vec_all_eq (vec_insert (16, ve, 2),

28496

+ ((vector unsigned int){0,1,16,3})),

28497

+ "vec_insert (ve BE)");

28498

+ check (vec_all_eq (vec_insert (-16, vf, 1),

28499

+ ((vector signed int){-2,-16,0,1})),

28500

+ "vec_insert (vf BE)");

28501

+ check (vec_all_eq (vec_insert (-16.0f, vg, 0),

28502

+ ((vector float){-16.0f,-1.0f,0.0f,1.0f})),

28503

+ "vec_insert (vg BE)");

28504

+#endif

28505

+}

28506

+

28507

Index: gcc/testsuite/gcc.dg/vmx/ldl.c

28508

===================================================================

28509

--- a/src/gcc/testsuite/gcc.dg/vmx/ldl.c (.../tags/gcc_4_8_2_release)

28510

+++ b/src/gcc/testsuite/gcc.dg/vmx/ldl.c (.../branches/gcc-4_8-branch)

28511

@@ -0,0 +1,91 @@

28512

+#include "harness.h"

28513

+

28514

+static unsigned char svuc[16] __attribute__ ((aligned (16)));

28515

+static signed char svsc[16] __attribute__ ((aligned (16)));

28516

+static unsigned char svbc[16] __attribute__ ((aligned (16)));

28517

+static unsigned short svus[8] __attribute__ ((aligned (16)));

28518

+static signed short svss[8] __attribute__ ((aligned (16)));

28519

+static unsigned short svbs[8] __attribute__ ((aligned (16)));

28520

+static unsigned short svp[8] __attribute__ ((aligned (16)));

28521

+static unsigned int svui[4] __attribute__ ((aligned (16)));

28522

+static signed int svsi[4] __attribute__ ((aligned (16)));

28523

+static unsigned int svbi[4] __attribute__ ((aligned (16)));

28524

+static float svf[4] __attribute__ ((aligned (16)));

28525

+

28526

+static void init ()

28527

+{

28528

+ unsigned int i;

28529

+ for (i = 0; i < 16; ++i)

28530

+ {

28531

+ svuc[i] = i;

28532

+ svsc[i] = i - 8;

28533

+ svbc[i] = (i % 2) ? 0xff : 0;

28534

+ }

28535

+ for (i = 0; i < 8; ++i)

28536

+ {

28537

+ svus[i] = i;

28538

+ svss[i] = i - 4;

28539

+ svbs[i] = (i % 2) ? 0xffff : 0;

28540

+ svp[i] = i;

28541

+ }

28542

+ for (i = 0; i < 4; ++i)

28543

+ {

28544

+ svui[i] = i;

28545

+ svsi[i] = i - 2;

28546

+ svbi[i] = (i % 2) ? 0xffffffff : 0;

28547

+ svf[i] = i * 1.0f;

28548

+ }

28549

+}

28550

+

28551

+static void test ()

28552

+{

28553

+ vector unsigned char evuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

28554

+ vector signed char evsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};

28555

+ vector bool char evbc = {0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255};

28556

+ vector unsigned short evus = {0,1,2,3,4,5,6,7};

28557

+ vector signed short evss = {-4,-3,-2,-1,0,1,2,3};

28558

+ vector bool short evbs = {0,65535,0,65535,0,65535,0,65535};

28559

+ vector pixel evp = {0,1,2,3,4,5,6,7};

28560

+ vector unsigned int evui = {0,1,2,3};

28561

+ vector signed int evsi = {-2,-1,0,1};

28562

+ vector bool int evbi = {0,0xffffffff,0,0xffffffff};

28563

+ vector float evf = {0.0,1.0,2.0,3.0};

28564

+

28565

+ vector unsigned char vuc;

28566

+ vector signed char vsc;

28567

+ vector bool char vbc;

28568

+ vector unsigned short vus;

28569

+ vector signed short vss;

28570

+ vector bool short vbs;

28571

+ vector pixel vp;

28572

+ vector unsigned int vui;

28573

+ vector signed int vsi;

28574

+ vector bool int vbi;

28575

+ vector float vf;

28576

+

28577

+ init ();

28578

+

28579

+ vuc = vec_ldl (0, (vector unsigned char *)svuc);

28580

+ vsc = vec_ldl (0, (vector signed char *)svsc);

28581

+ vbc = vec_ldl (0, (vector bool char *)svbc);

28582

+ vus = vec_ldl (0, (vector unsigned short *)svus);

28583

+ vss = vec_ldl (0, (vector signed short *)svss);

28584

+ vbs = vec_ldl (0, (vector bool short *)svbs);

28585

+ vp = vec_ldl (0, (vector pixel *)svp);

28586

+ vui = vec_ldl (0, (vector unsigned int *)svui);

28587

+ vsi = vec_ldl (0, (vector signed int *)svsi);

28588

+ vbi = vec_ldl (0, (vector bool int *)svbi);

28589

+ vf = vec_ldl (0, (vector float *)svf);

28590

+

28591

+ check (vec_all_eq (vuc, evuc), "vuc");

28592

+ check (vec_all_eq (vsc, evsc), "vsc");

28593

+ check (vec_all_eq (vbc, evbc), "vbc");

28594

+ check (vec_all_eq (vus, evus), "vus");

28595

+ check (vec_all_eq (vss, evss), "vss");

28596

+ check (vec_all_eq (vbs, evbs), "vbs");

28597

+ check (vec_all_eq (vp, evp ), "vp" );

28598

+ check (vec_all_eq (vui, evui), "vui");

28599

+ check (vec_all_eq (vsi, evsi), "vsi");

28600

+ check (vec_all_eq (vbi, evbi), "vbi");

28601

+ check (vec_all_eq (vf, evf ), "vf" );

28602

+}

28603

Index: gcc/testsuite/gcc.dg/vmx/stl-vsx-be-order.c

28604

===================================================================

28605

--- a/src/gcc/testsuite/gcc.dg/vmx/stl-vsx-be-order.c (.../tags/gcc_4_8_2_release)

28606

+++ b/src/gcc/testsuite/gcc.dg/vmx/stl-vsx-be-order.c (.../branches/gcc-4_8-branch)

28607

@@ -0,0 +1,34 @@

28608

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

28609

+/* { dg-require-effective-target powerpc_vsx_ok } */

28610

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mvsx" } */

28611

+

28612

+#include "harness.h"

28613

+

28614

+static unsigned long long svul[2] __attribute__ ((aligned (16)));

28615

+static double svd[2] __attribute__ ((aligned (16)));

28616

+

28617

+static void check_arrays ()

28618

+{

28619

+ unsigned int i;

28620

+ for (i = 0; i < 2; ++i)

28621

+ {

28622

+ check (svul[i] == i, "svul");

28623

+ check (svd[i] == i * 1.0, "svd");

28624

+ }

28625

+}

28626

+

28627

+static void test ()

28628

+{

28629

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

28630

+ vector unsigned long long vul = {1,0};

28631

+ vector double vd = {1.0,0.0};

28632

+#else

28633

+ vector unsigned long long vul = {0,1};

28634

+ vector double vd = {0.0,1.0};

28635

+#endif

28636

+

28637

+ vec_stl (vul, 0, (vector unsigned long long *)svul);

28638

+ vec_stl (vd, 0, (vector double *)svd);

28639

+

28640

+ check_arrays ();

28641

+}

28642

Index: gcc/testsuite/gcc.dg/vmx/vsums.c

28643

===================================================================

28644

--- a/src/gcc/testsuite/gcc.dg/vmx/vsums.c (.../tags/gcc_4_8_2_release)

28645

+++ b/src/gcc/testsuite/gcc.dg/vmx/vsums.c (.../branches/gcc-4_8-branch)

28646

@@ -0,0 +1,12 @@

28647

+#include "harness.h"

28648

+

28649

+static void test()

28650

+{

28651

+ vector signed int va = {-7,11,-13,17};

28652

+ vector signed int vb = {0,0,0,128};

28653

+ vector signed int evd = {0,0,0,136};

28654

+

28655

+ vector signed int vd = vec_sums (va, vb);

28656

+

28657

+ check (vec_all_eq (vd, evd), "sums");

28658

+}

28659

Index: gcc/testsuite/gcc.dg/vmx/insert-vsx-be-order.c

28660

===================================================================

28661

--- a/src/gcc/testsuite/gcc.dg/vmx/insert-vsx-be-order.c (.../tags/gcc_4_8_2_release)

28662

+++ b/src/gcc/testsuite/gcc.dg/vmx/insert-vsx-be-order.c (.../branches/gcc-4_8-branch)

28663

@@ -0,0 +1,34 @@

28664

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

28665

+/* { dg-require-effective-target powerpc_vsx_ok } */

28666

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mvsx" } */

28667

+

28668

+#include "harness.h"

28669

+

28670

+static int vec_long_long_eq (vector long long x, vector long long y)

28671

+{

28672

+ return (x[0] == y[0] && x[1] == y[1]);

28673

+}

28674

+

28675

+static int vec_dbl_eq (vector double x, vector double y)

28676

+{

28677

+ return (x[0] == y[0] && x[1] == y[1]);

28678

+}

28679

+

28680

+static void test()

28681

+{

28682

+ vector long long vl = {0, 1};

28683

+ vector double vd = {0.0, 1.0};

28684

+ vector long long vlr = vec_insert (2, vl, 0);

28685

+ vector double vdr = vec_insert (2.0, vd, 1);

28686

+

28687

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

28688

+ vector long long vler = {0, 2};

28689

+ vector double vder = {2.0, 1.0};

28690

+#else

28691

+ vector long long vler = {2, 1};

28692

+ vector double vder = {0.0, 2.0};

28693

+#endif

28694

+

28695

+ check (vec_long_long_eq (vlr, vler), "vl");

28696

+ check (vec_dbl_eq (vdr, vder), "vd");

28697

+}

28698

Index: gcc/testsuite/gcc.dg/vmx/unpack.c

28699

===================================================================

28700

--- a/src/gcc/testsuite/gcc.dg/vmx/unpack.c (.../tags/gcc_4_8_2_release)

28701

+++ b/src/gcc/testsuite/gcc.dg/vmx/unpack.c (.../branches/gcc-4_8-branch)

28702

@@ -0,0 +1,67 @@

28703

+#include "harness.h"

28704

+

28705

+#define BIG 4294967295

28706

+

28707

+static void test()

28708

+{

28709

+ /* Input vectors. */

28710

+ vector signed char vsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};

28711

+ vector bool char vbc = {0,255,255,0,0,0,255,0,255,0,0,255,255,255,0,255};

28712

+ vector pixel vp = {(0<<15) + (1<<10) + (2<<5) + 3,

28713

+ (1<<15) + (4<<10) + (5<<5) + 6,

28714

+ (0<<15) + (7<<10) + (8<<5) + 9,

28715

+ (1<<15) + (10<<10) + (11<<5) + 12,

28716

+ (1<<15) + (13<<10) + (14<<5) + 15,

28717

+ (0<<15) + (16<<10) + (17<<5) + 18,

28718

+ (1<<15) + (19<<10) + (20<<5) + 21,

28719

+ (0<<15) + (22<<10) + (23<<5) + 24};

28720

+ vector signed short vss = {-4,-3,-2,-1,0,1,2,3};

28721

+ vector bool short vbs = {0,65535,65535,0,0,0,65535,0};

28722

+

28723

+ /* Result vectors. */

28724

+ vector signed short vsch, vscl;

28725

+ vector bool short vbsh, vbsl;

28726

+ vector unsigned int vuih, vuil;

28727

+ vector signed int vsih, vsil;

28728

+ vector bool int vbih, vbil;

28729

+

28730

+ /* Expected result vectors. */

28731

+ vector signed short vschr = {-8,-7,-6,-5,-4,-3,-2,-1};

28732

+ vector signed short vsclr = {0,1,2,3,4,5,6,7};

28733

+ vector bool short vbshr = {0,65535,65535,0,0,0,65535,0};

28734

+ vector bool short vbslr = {65535,0,0,65535,65535,65535,0,65535};

28735

+ vector unsigned int vuihr = {(0<<24) + (1<<16) + (2<<8) + 3,

28736

+ (65535<<24) + (4<<16) + (5<<8) + 6,

28737

+ (0<<24) + (7<<16) + (8<<8) + 9,

28738

+ (65535<<24) + (10<<16) + (11<<8) + 12};

28739

+ vector unsigned int vuilr = {(65535<<24) + (13<<16) + (14<<8) + 15,

28740

+ (0<<24) + (16<<16) + (17<<8) + 18,

28741

+ (65535<<24) + (19<<16) + (20<<8) + 21,

28742

+ (0<<24) + (22<<16) + (23<<8) + 24};

28743

+ vector signed int vsihr = {-4,-3,-2,-1};

28744

+ vector signed int vsilr = {0,1,2,3};

28745

+ vector bool int vbihr = {0,BIG,BIG,0};

28746

+ vector bool int vbilr = {0,0,BIG,0};

28747

+

28748

+ vsch = vec_unpackh (vsc);

28749

+ vscl = vec_unpackl (vsc);

28750

+ vbsh = vec_unpackh (vbc);

28751

+ vbsl = vec_unpackl (vbc);

28752

+ vuih = vec_unpackh (vp);

28753

+ vuil = vec_unpackl (vp);

28754

+ vsih = vec_unpackh (vss);

28755

+ vsil = vec_unpackl (vss);

28756

+ vbih = vec_unpackh (vbs);

28757

+ vbil = vec_unpackl (vbs);

28758

+

28759

+ check (vec_all_eq (vsch, vschr), "vsch");

28760

+ check (vec_all_eq (vscl, vsclr), "vscl");

28761

+ check (vec_all_eq (vbsh, vbshr), "vbsh");

28762

+ check (vec_all_eq (vbsl, vbslr), "vbsl");

28763

+ check (vec_all_eq (vuih, vuihr), "vuih");

28764

+ check (vec_all_eq (vuil, vuilr), "vuil");

28765

+ check (vec_all_eq (vsih, vsihr), "vsih");

28766

+ check (vec_all_eq (vsil, vsilr), "vsil");

28767

+ check (vec_all_eq (vbih, vbihr), "vbih");

28768

+ check (vec_all_eq (vbil, vbilr), "vbil");

28769

+}

28770

Index: gcc/testsuite/gcc.dg/vmx/splat.c

28771

===================================================================

28772

--- a/src/gcc/testsuite/gcc.dg/vmx/splat.c (.../tags/gcc_4_8_2_release)

28773

+++ b/src/gcc/testsuite/gcc.dg/vmx/splat.c (.../branches/gcc-4_8-branch)

28774

@@ -0,0 +1,47 @@

28775

+#include "harness.h"

28776

+

28777

+static void test()

28778

+{

28779

+ /* Input vectors. */

28780

+ vector unsigned char vuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

28781

+ vector signed char vsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};

28782

+ vector unsigned short vus = {0,1,2,3,4,5,6,7};

28783

+ vector signed short vss = {-4,-3,-2,-1,0,1,2,3};

28784

+ vector unsigned int vui = {0,1,2,3};

28785

+ vector signed int vsi = {-2,-1,0,1};

28786

+ vector float vf = {-2.0,-1.0,0.0,1.0};

28787

+

28788

+ /* Result vectors. */

28789

+ vector unsigned char vucr;

28790

+ vector signed char vscr;

28791

+ vector unsigned short vusr;

28792

+ vector signed short vssr;

28793

+ vector unsigned int vuir;

28794

+ vector signed int vsir;

28795

+ vector float vfr;

28796

+

28797

+ /* Expected result vectors. */

28798

+ vector unsigned char vucer = {1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1};

28799

+ vector signed char vscer = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};

28800

+ vector unsigned short vuser = {7,7,7,7,7,7,7,7};

28801

+ vector signed short vsser = {-4,-4,-4,-4,-4,-4,-4,-4};

28802

+ vector unsigned int vuier = {2,2,2,2};

28803

+ vector signed int vsier = {1,1,1,1};

28804

+ vector float vfer = {-1.0,-1.0,-1.0,-1.0};

28805

+

28806

+ vucr = vec_splat (vuc, 1);

28807

+ vscr = vec_splat (vsc, 8);

28808

+ vusr = vec_splat (vus, 7);

28809

+ vssr = vec_splat (vss, 0);

28810

+ vuir = vec_splat (vui, 2);

28811

+ vsir = vec_splat (vsi, 3);

28812

+ vfr = vec_splat (vf, 1);

28813

+

28814

+ check (vec_all_eq (vucr, vucer), "vuc");

28815

+ check (vec_all_eq (vscr, vscer), "vsc");

28816

+ check (vec_all_eq (vusr, vuser), "vus");

28817

+ check (vec_all_eq (vssr, vsser), "vss");

28818

+ check (vec_all_eq (vuir, vuier), "vui");

28819

+ check (vec_all_eq (vsir, vsier), "vsi");

28820

+ check (vec_all_eq (vfr, vfer ), "vf");

28821

+}

28822

Index: gcc/testsuite/gcc.dg/vmx/ldl-vsx-be-order.c

28823

===================================================================

28824

--- a/src/gcc/testsuite/gcc.dg/vmx/ldl-vsx-be-order.c (.../tags/gcc_4_8_2_release)

28825

+++ b/src/gcc/testsuite/gcc.dg/vmx/ldl-vsx-be-order.c (.../branches/gcc-4_8-branch)

28826

@@ -0,0 +1,44 @@

28827

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

28828

+/* { dg-require-effective-target powerpc_vsx_ok } */

28829

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mvsx" } */

28830

+

28831

+#include "harness.h"

28832

+

28833

+static unsigned long long svul[2] __attribute__ ((aligned (16)));

28834

+static double svd[2] __attribute__ ((aligned (16)));

28835

+

28836

+static void init ()

28837

+{

28838

+ unsigned int i;

28839

+ for (i = 0; i < 2; ++i)

28840

+ {

28841

+ svul[i] = i;

28842

+ svd[i] = i * 1.0;

28843

+ }

28844

+}

28845

+

28846

+static void test ()

28847

+{

28848

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

28849

+ vector unsigned long long evul = {1,0};

28850

+ vector double evd = {1.0,0.0};

28851

+#else

28852

+ vector unsigned long long evul = {0,1};

28853

+ vector double evd = {0.0,1.0};

28854

+#endif

28855

+

28856

+ vector unsigned long long vul;

28857

+ vector double vd;

28858

+ unsigned i;

28859

+

28860

+ init ();

28861

+

28862

+ vul = vec_ldl (0, (vector unsigned long long *)svul);

28863

+ vd = vec_ldl (0, (vector double *)svd);

28864

+

28865

+ for (i = 0; i < 2; ++i)

28866

+ {

28867

+ check (vul[i] == evul[i], "vul");

28868

+ check (vd[i] == evd[i], "vd" );

28869

+ }

28870

+}

28871

Index: gcc/testsuite/gcc.dg/vmx/merge-be-order.c

28872

===================================================================

28873

--- a/src/gcc/testsuite/gcc.dg/vmx/merge-be-order.c (.../tags/gcc_4_8_2_release)

28874

+++ b/src/gcc/testsuite/gcc.dg/vmx/merge-be-order.c (.../branches/gcc-4_8-branch)

28875

@@ -0,0 +1,96 @@

28876

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */

28877

+

28878

+#include "harness.h"

28879

+

28880

+static void test()

28881

+{

28882

+ /* Input vectors. */

28883

+ vector unsigned char vuca = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

28884

+ vector unsigned char vucb

28885

+ = {16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31};

28886

+ vector signed char vsca

28887

+ = {-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1};

28888

+ vector signed char vscb = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

28889

+ vector unsigned short vusa = {0,1,2,3,4,5,6,7};

28890

+ vector unsigned short vusb = {8,9,10,11,12,13,14,15};

28891

+ vector signed short vssa = {-8,-7,-6,-5,-4,-3,-2,-1};

28892

+ vector signed short vssb = {0,1,2,3,4,5,6,7};

28893

+ vector unsigned int vuia = {0,1,2,3};

28894

+ vector unsigned int vuib = {4,5,6,7};

28895

+ vector signed int vsia = {-4,-3,-2,-1};

28896

+ vector signed int vsib = {0,1,2,3};

28897

+ vector float vfa = {-4.0,-3.0,-2.0,-1.0};

28898

+ vector float vfb = {0.0,1.0,2.0,3.0};

28899

+

28900

+ /* Result vectors. */

28901

+ vector unsigned char vuch, vucl;

28902

+ vector signed char vsch, vscl;

28903

+ vector unsigned short vush, vusl;

28904

+ vector signed short vssh, vssl;

28905

+ vector unsigned int vuih, vuil;

28906

+ vector signed int vsih, vsil;

28907

+ vector float vfh, vfl;

28908

+

28909

+ /* Expected result vectors. */

28910

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

28911

+ vector unsigned char vucrh = {24,8,25,9,26,10,27,11,28,12,29,13,30,14,31,15};

28912

+ vector unsigned char vucrl = {16,0,17,1,18,2,19,3,20,4,21,5,22,6,23,7};

28913

+ vector signed char vscrh = {8,-8,9,-7,10,-6,11,-5,12,-4,13,-3,14,-2,15,-1};

28914

+ vector signed char vscrl = {0,-16,1,-15,2,-14,3,-13,4,-12,5,-11,6,-10,7,-9};

28915

+ vector unsigned short vusrh = {12,4,13,5,14,6,15,7};

28916

+ vector unsigned short vusrl = {8,0,9,1,10,2,11,3};

28917

+ vector signed short vssrh = {4,-4,5,-3,6,-2,7,-1};

28918

+ vector signed short vssrl = {0,-8,1,-7,2,-6,3,-5};

28919

+ vector unsigned int vuirh = {6,2,7,3};

28920

+ vector unsigned int vuirl = {4,0,5,1};

28921

+ vector signed int vsirh = {2,-2,3,-1};

28922

+ vector signed int vsirl = {0,-4,1,-3};

28923

+ vector float vfrh = {2.0,-2.0,3.0,-1.0};

28924

+ vector float vfrl = {0.0,-4.0,1.0,-3.0};

28925

+#else

28926

+ vector unsigned char vucrh = {0,16,1,17,2,18,3,19,4,20,5,21,6,22,7,23};

28927

+ vector unsigned char vucrl = {8,24,9,25,10,26,11,27,12,28,13,29,14,30,15,31};

28928

+ vector signed char vscrh = {-16,0,-15,1,-14,2,-13,3,-12,4,-11,5,-10,6,-9,7};

28929

+ vector signed char vscrl = {-8,8,-7,9,-6,10,-5,11,-4,12,-3,13,-2,14,-1,15};

28930

+ vector unsigned short vusrh = {0,8,1,9,2,10,3,11};

28931

+ vector unsigned short vusrl = {4,12,5,13,6,14,7,15};

28932

+ vector signed short vssrh = {-8,0,-7,1,-6,2,-5,3};

28933

+ vector signed short vssrl = {-4,4,-3,5,-2,6,-1,7};

28934

+ vector unsigned int vuirh = {0,4,1,5};

28935

+ vector unsigned int vuirl = {2,6,3,7};

28936

+ vector signed int vsirh = {-4,0,-3,1};

28937

+ vector signed int vsirl = {-2,2,-1,3};

28938

+ vector float vfrh = {-4.0,0.0,-3.0,1.0};

28939

+ vector float vfrl = {-2.0,2.0,-1.0,3.0};

28940

+#endif

28941

+

28942

+ vuch = vec_mergeh (vuca, vucb);

28943

+ vucl = vec_mergel (vuca, vucb);

28944

+ vsch = vec_mergeh (vsca, vscb);

28945

+ vscl = vec_mergel (vsca, vscb);

28946

+ vush = vec_mergeh (vusa, vusb);

28947

+ vusl = vec_mergel (vusa, vusb);

28948

+ vssh = vec_mergeh (vssa, vssb);

28949

+ vssl = vec_mergel (vssa, vssb);

28950

+ vuih = vec_mergeh (vuia, vuib);

28951

+ vuil = vec_mergel (vuia, vuib);

28952

+ vsih = vec_mergeh (vsia, vsib);

28953

+ vsil = vec_mergel (vsia, vsib);

28954

+ vfh = vec_mergeh (vfa, vfb );

28955

+ vfl = vec_mergel (vfa, vfb );

28956

+

28957

+ check (vec_all_eq (vuch, vucrh), "vuch");

28958

+ check (vec_all_eq (vucl, vucrl), "vucl");

28959

+ check (vec_all_eq (vsch, vscrh), "vsch");

28960

+ check (vec_all_eq (vscl, vscrl), "vscl");

28961

+ check (vec_all_eq (vush, vusrh), "vush");

28962

+ check (vec_all_eq (vusl, vusrl), "vusl");

28963

+ check (vec_all_eq (vssh, vssrh), "vssh");

28964

+ check (vec_all_eq (vssl, vssrl), "vssl");

28965

+ check (vec_all_eq (vuih, vuirh), "vuih");

28966

+ check (vec_all_eq (vuil, vuirl), "vuil");

28967

+ check (vec_all_eq (vsih, vsirh), "vsih");

28968

+ check (vec_all_eq (vsil, vsirl), "vsil");

28969

+ check (vec_all_eq (vfh, vfrh), "vfh");

28970

+ check (vec_all_eq (vfl, vfrl), "vfl");

28971

+}

28972

Index: gcc/testsuite/gcc.dg/vmx/splat-vsx-be-order.c

28973

===================================================================

28974

--- a/src/gcc/testsuite/gcc.dg/vmx/splat-vsx-be-order.c (.../tags/gcc_4_8_2_release)

28975

+++ b/src/gcc/testsuite/gcc.dg/vmx/splat-vsx-be-order.c (.../branches/gcc-4_8-branch)

28976

@@ -0,0 +1,37 @@

28977

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

28978

+/* { dg-require-effective-target powerpc_vsx_ok } */

28979

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mvsx" } */

28980

+

28981

+#include "harness.h"

28982

+

28983

+static void test()

28984

+{

28985

+ /* Input vectors. */

28986

+ vector unsigned int vui = {0,1,2,3};

28987

+ vector signed int vsi = {-2,-1,0,1};

28988

+ vector float vf = {-2.0,-1.0,0.0,1.0};

28989

+

28990

+ /* Result vectors. */

28991

+ vector unsigned int vuir;

28992

+ vector signed int vsir;

28993

+ vector float vfr;

28994

+

28995

+ /* Expected result vectors. */

28996

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

28997

+ vector unsigned int vuier = {1,1,1,1};

28998

+ vector signed int vsier = {-2,-2,-2,-2};

28999

+ vector float vfer = {0.0,0.0,0.0,0.0};

29000

+#else

29001

+ vector unsigned int vuier = {2,2,2,2};

29002

+ vector signed int vsier = {1,1,1,1};

29003

+ vector float vfer = {-1.0,-1.0,-1.0,-1.0};

29004

+#endif

29005

+

29006

+ vuir = vec_splat (vui, 2);

29007

+ vsir = vec_splat (vsi, 3);

29008

+ vfr = vec_splat (vf, 1);

29009

+

29010

+ check (vec_all_eq (vuir, vuier), "vui");

29011

+ check (vec_all_eq (vsir, vsier), "vsi");

29012

+ check (vec_all_eq (vfr, vfer ), "vf");

29013

+}

29014

Index: gcc/testsuite/gcc.dg/vmx/merge.c

29015

===================================================================

29016

--- a/src/gcc/testsuite/gcc.dg/vmx/merge.c (.../tags/gcc_4_8_2_release)

29017

+++ b/src/gcc/testsuite/gcc.dg/vmx/merge.c (.../branches/gcc-4_8-branch)

29018

@@ -0,0 +1,77 @@

29019

+#include "harness.h"

29020

+

29021

+static void test()

29022

+{

29023

+ /* Input vectors. */

29024

+ vector unsigned char vuca = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

29025

+ vector unsigned char vucb

29026

+ = {16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31};

29027

+ vector signed char vsca

29028

+ = {-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1};

29029

+ vector signed char vscb = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

29030

+ vector unsigned short vusa = {0,1,2,3,4,5,6,7};

29031

+ vector unsigned short vusb = {8,9,10,11,12,13,14,15};

29032

+ vector signed short vssa = {-8,-7,-6,-5,-4,-3,-2,-1};

29033

+ vector signed short vssb = {0,1,2,3,4,5,6,7};

29034

+ vector unsigned int vuia = {0,1,2,3};

29035

+ vector unsigned int vuib = {4,5,6,7};

29036

+ vector signed int vsia = {-4,-3,-2,-1};

29037

+ vector signed int vsib = {0,1,2,3};

29038

+ vector float vfa = {-4.0,-3.0,-2.0,-1.0};

29039

+ vector float vfb = {0.0,1.0,2.0,3.0};

29040

+

29041

+ /* Result vectors. */

29042

+ vector unsigned char vuch, vucl;

29043

+ vector signed char vsch, vscl;

29044

+ vector unsigned short vush, vusl;

29045

+ vector signed short vssh, vssl;

29046

+ vector unsigned int vuih, vuil;

29047

+ vector signed int vsih, vsil;

29048

+ vector float vfh, vfl;

29049

+

29050

+ /* Expected result vectors. */

29051

+ vector unsigned char vucrh = {0,16,1,17,2,18,3,19,4,20,5,21,6,22,7,23};

29052

+ vector unsigned char vucrl = {8,24,9,25,10,26,11,27,12,28,13,29,14,30,15,31};

29053

+ vector signed char vscrh = {-16,0,-15,1,-14,2,-13,3,-12,4,-11,5,-10,6,-9,7};

29054

+ vector signed char vscrl = {-8,8,-7,9,-6,10,-5,11,-4,12,-3,13,-2,14,-1,15};

29055

+ vector unsigned short vusrh = {0,8,1,9,2,10,3,11};

29056

+ vector unsigned short vusrl = {4,12,5,13,6,14,7,15};

29057

+ vector signed short vssrh = {-8,0,-7,1,-6,2,-5,3};

29058

+ vector signed short vssrl = {-4,4,-3,5,-2,6,-1,7};

29059

+ vector unsigned int vuirh = {0,4,1,5};

29060

+ vector unsigned int vuirl = {2,6,3,7};

29061

+ vector signed int vsirh = {-4,0,-3,1};

29062

+ vector signed int vsirl = {-2,2,-1,3};

29063

+ vector float vfrh = {-4.0,0.0,-3.0,1.0};

29064

+ vector float vfrl = {-2.0,2.0,-1.0,3.0};

29065

+

29066

+ vuch = vec_mergeh (vuca, vucb);

29067

+ vucl = vec_mergel (vuca, vucb);

29068

+ vsch = vec_mergeh (vsca, vscb);

29069

+ vscl = vec_mergel (vsca, vscb);

29070

+ vush = vec_mergeh (vusa, vusb);

29071

+ vusl = vec_mergel (vusa, vusb);

29072

+ vssh = vec_mergeh (vssa, vssb);

29073

+ vssl = vec_mergel (vssa, vssb);

29074

+ vuih = vec_mergeh (vuia, vuib);

29075

+ vuil = vec_mergel (vuia, vuib);

29076

+ vsih = vec_mergeh (vsia, vsib);

29077

+ vsil = vec_mergel (vsia, vsib);

29078

+ vfh = vec_mergeh (vfa, vfb );

29079

+ vfl = vec_mergel (vfa, vfb );

29080

+

29081

+ check (vec_all_eq (vuch, vucrh), "vuch");

29082

+ check (vec_all_eq (vucl, vucrl), "vucl");

29083

+ check (vec_all_eq (vsch, vscrh), "vsch");

29084

+ check (vec_all_eq (vscl, vscrl), "vscl");

29085

+ check (vec_all_eq (vush, vusrh), "vush");

29086

+ check (vec_all_eq (vusl, vusrl), "vusl");

29087

+ check (vec_all_eq (vssh, vssrh), "vssh");

29088

+ check (vec_all_eq (vssl, vssrl), "vssl");

29089

+ check (vec_all_eq (vuih, vuirh), "vuih");

29090

+ check (vec_all_eq (vuil, vuirl), "vuil");

29091

+ check (vec_all_eq (vsih, vsirh), "vsih");

29092

+ check (vec_all_eq (vsil, vsirl), "vsil");

29093

+ check (vec_all_eq (vfh, vfrh), "vfh");

29094

+ check (vec_all_eq (vfl, vfrl), "vfl");

29095

+}

29096

Index: gcc/testsuite/gcc.dg/vmx/vec-set.c

29097

===================================================================

29098

--- a/src/gcc/testsuite/gcc.dg/vmx/vec-set.c (.../tags/gcc_4_8_2_release)

29099

+++ b/src/gcc/testsuite/gcc.dg/vmx/vec-set.c (.../branches/gcc-4_8-branch)

29100

@@ -0,0 +1,14 @@

29101

+#include "harness.h"

29102

+

29103

+vector short

29104

+vec_set (short m)

29105

+{

29106

+ return (vector short){m, 0, 0, 0, 0, 0, 0, 0};

29107

+}

29108

+

29109

+static void test()

29110

+{

29111

+ check (vec_all_eq (vec_set (7),

29112

+ ((vector short){7, 0, 0, 0, 0, 0, 0, 0})),

29113

+ "vec_set");

29114

+}

29115

Index: gcc/testsuite/gcc.dg/vmx/ld-vsx-be-order.c

29116

===================================================================

29117

--- a/src/gcc/testsuite/gcc.dg/vmx/ld-vsx-be-order.c (.../tags/gcc_4_8_2_release)

29118

+++ b/src/gcc/testsuite/gcc.dg/vmx/ld-vsx-be-order.c (.../branches/gcc-4_8-branch)

29119

@@ -0,0 +1,44 @@

29120

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

29121

+/* { dg-require-effective-target powerpc_vsx_ok } */

29122

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mvsx" } */

29123

+

29124

+#include "harness.h"

29125

+

29126

+static unsigned long long svul[2] __attribute__ ((aligned (16)));

29127

+static double svd[2] __attribute__ ((aligned (16)));

29128

+

29129

+static void init ()

29130

+{

29131

+ unsigned int i;

29132

+ for (i = 0; i < 2; ++i)

29133

+ {

29134

+ svul[i] = i;

29135

+ svd[i] = i * 1.0;

29136

+ }

29137

+}

29138

+

29139

+static void test ()

29140

+{

29141

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

29142

+ vector unsigned long long evul = {1,0};

29143

+ vector double evd = {1.0,0.0};

29144

+#else

29145

+ vector unsigned long long evul = {0,1};

29146

+ vector double evd = {0.0,1.0};

29147

+#endif

29148

+

29149

+ vector unsigned long long vul;

29150

+ vector double vd;

29151

+ unsigned i;

29152

+

29153

+ init ();

29154

+

29155

+ vul = vec_ld (0, (vector unsigned long long *)svul);

29156

+ vd = vec_ld (0, (vector double *)svd);

29157

+

29158

+ for (i = 0; i < 2; ++i)

29159

+ {

29160

+ check (vul[i] == evul[i], "vul");

29161

+ check (vd[i] == evd[i], "vd" );

29162

+ }

29163

+}

29164

Index: gcc/testsuite/gcc.dg/vmx/extract.c

29165

===================================================================

29166

--- a/src/gcc/testsuite/gcc.dg/vmx/extract.c (.../tags/gcc_4_8_2_release)

29167

+++ b/src/gcc/testsuite/gcc.dg/vmx/extract.c (.../branches/gcc-4_8-branch)

29168

@@ -0,0 +1,21 @@

29169

+#include "harness.h"

29170

+

29171

+static void test()

29172

+{

29173

+ vector unsigned char va = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

29174

+ vector signed char vb = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};

29175

+ vector unsigned short vc = {0,1,2,3,4,5,6,7};

29176

+ vector signed short vd = {-4,-3,-2,-1,0,1,2,3};

29177

+ vector unsigned int ve = {0,1,2,3};

29178

+ vector signed int vf = {-2,-1,0,1};

29179

+ vector float vg = {-2.0f,-1.0f,0.0f,1.0f};

29180

+

29181

+ check (vec_extract (va, 5) == 5, "vec_extract (va, 5)");

29182

+ check (vec_extract (vb, 0) == -8, "vec_extract (vb, 0)");

29183

+ check (vec_extract (vc, 7) == 7, "vec_extract (vc, 7)");

29184

+ check (vec_extract (vd, 3) == -1, "vec_extract (vd, 3)");

29185

+ check (vec_extract (ve, 2) == 2, "vec_extract (ve, 2)");

29186

+ check (vec_extract (vf, 1) == -1, "vec_extract (vf, 1)");

29187

+ check (vec_extract (vg, 0) == -2.0f, "vec_extract (vg, 0)");

29188

+}

29189

+

29190

Index: gcc/testsuite/gcc.dg/vmx/pack-be-order.c

29191

===================================================================

29192

--- a/src/gcc/testsuite/gcc.dg/vmx/pack-be-order.c (.../tags/gcc_4_8_2_release)

29193

+++ b/src/gcc/testsuite/gcc.dg/vmx/pack-be-order.c (.../branches/gcc-4_8-branch)

29194

@@ -0,0 +1,136 @@

29195

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */

29196

+

29197

+#include "harness.h"

29198

+

29199

+#define BIG 4294967295

29200

+

29201

+static void test()

29202

+{

29203

+ /* Input vectors. */

29204

+ vector unsigned short vusa = {0,1,2,3,4,5,6,7};

29205

+ vector unsigned short vusb = {8,9,10,11,12,13,14,15};

29206

+ vector signed short vssa = {-8,-7,-6,-5,-4,-3,-2,-1};

29207

+ vector signed short vssb = {0,1,2,3,4,5,6,7};

29208

+ vector bool short vbsa = {0,65535,65535,0,0,0,65535,0};

29209

+ vector bool short vbsb = {65535,0,0,65535,65535,65535,0,65535};

29210

+ vector unsigned int vuia = {0,1,2,3};

29211

+ vector unsigned int vuib = {4,5,6,7};

29212

+ vector signed int vsia = {-4,-3,-2,-1};

29213

+ vector signed int vsib = {0,1,2,3};

29214

+ vector bool int vbia = {0,BIG,BIG,BIG};

29215

+ vector bool int vbib = {BIG,0,0,0};

29216

+ vector unsigned int vipa = {(0<<24) + (2<<19) + (3<<11) + (4<<3),

29217

+ (1<<24) + (5<<19) + (6<<11) + (7<<3),

29218

+ (0<<24) + (8<<19) + (9<<11) + (10<<3),

29219

+ (1<<24) + (11<<19) + (12<<11) + (13<<3)};

29220

+ vector unsigned int vipb = {(1<<24) + (14<<19) + (15<<11) + (16<<3),

29221

+ (0<<24) + (17<<19) + (18<<11) + (19<<3),

29222

+ (1<<24) + (20<<19) + (21<<11) + (22<<3),

29223

+ (0<<24) + (23<<19) + (24<<11) + (25<<3)};

29224

+ vector unsigned short vusc = {0,256,1,257,2,258,3,259};

29225

+ vector unsigned short vusd = {4,260,5,261,6,262,7,263};

29226

+ vector signed short vssc = {-1,-128,0,127,-2,-129,1,128};

29227

+ vector signed short vssd = {-3,-130,2,129,-4,-131,3,130};

29228

+ vector unsigned int vuic = {0,65536,1,65537};

29229

+ vector unsigned int vuid = {2,65538,3,65539};

29230

+ vector signed int vsic = {-1,-32768,0,32767};

29231

+ vector signed int vsid = {-2,-32769,1,32768};

29232

+

29233

+ /* Result vectors. */

29234

+ vector unsigned char vucr;

29235

+ vector signed char vscr;

29236

+ vector bool char vbcr;

29237

+ vector unsigned short vusr;

29238

+ vector signed short vssr;

29239

+ vector bool short vbsr;

29240

+ vector pixel vpr;

29241

+ vector unsigned char vucsr;

29242

+ vector signed char vscsr;

29243

+ vector unsigned short vussr;

29244

+ vector signed short vsssr;

29245

+ vector unsigned char vucsur1, vucsur2;

29246

+ vector unsigned short vussur1, vussur2;

29247

+

29248

+ /* Expected result vectors. */

29249

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

29250

+ vector unsigned char vucer = {8,9,10,11,12,13,14,15,0,1,2,3,4,5,6,7};

29251

+ vector signed char vscer = {0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1};

29252

+ vector bool char vbcer = {255,0,0,255,255,255,0,255,0,255,255,0,0,0,255,0};

29253

+ vector unsigned short vuser = {4,5,6,7,0,1,2,3};

29254

+ vector signed short vsser = {0,1,2,3,-4,-3,-2,-1};

29255

+ vector bool short vbser = {65535,0,0,0,0,65535,65535,65535};

29256

+ vector pixel vper = {(1<<15) + (14<<10) + (15<<5) + 16,

29257

+ (0<<15) + (17<<10) + (18<<5) + 19,

29258

+ (1<<15) + (20<<10) + (21<<5) + 22,

29259

+ (0<<15) + (23<<10) + (24<<5) + 25,

29260

+ (0<<15) + (2<<10) + (3<<5) + 4,

29261

+ (1<<15) + (5<<10) + (6<<5) + 7,

29262

+ (0<<15) + (8<<10) + (9<<5) + 10,

29263

+ (1<<15) + (11<<10) + (12<<5) + 13};

29264

+ vector unsigned char vucser = {4,255,5,255,6,255,7,255,0,255,1,255,2,255,3,255};

29265

+ vector signed char vscser = {-3,-128,2,127,-4,-128,3,127,

29266

+ -1,-128,0,127,-2,-128,1,127};

29267

+ vector unsigned short vusser = {2,65535,3,65535,0,65535,1,65535};

29268

+ vector signed short vssser = {-2,-32768,1,32767,-1,-32768,0,32767};

29269

+ vector unsigned char vucsuer1 = {4,255,5,255,6,255,7,255,0,255,1,255,2,255,3,255};

29270

+ vector unsigned char vucsuer2 = {0,0,2,129,0,0,3,130,0,0,0,127,0,0,1,128};

29271

+ vector unsigned short vussuer1 = {2,65535,3,65535,0,65535,1,65535};

29272

+ vector unsigned short vussuer2 = {0,0,1,32768,0,0,0,32767};

29273

+#else

29274

+ vector unsigned char vucer = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

29275

+ vector signed char vscer = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};

29276

+ vector bool char vbcer = {0,255,255,0,0,0,255,0,255,0,0,255,255,255,0,255};

29277

+ vector unsigned short vuser = {0,1,2,3,4,5,6,7};

29278

+ vector signed short vsser = {-4,-3,-2,-1,0,1,2,3};

29279

+ vector bool short vbser = {0,65535,65535,65535,65535,0,0,0};

29280

+ vector pixel vper = {(0<<15) + (2<<10) + (3<<5) + 4,

29281

+ (1<<15) + (5<<10) + (6<<5) + 7,

29282

+ (0<<15) + (8<<10) + (9<<5) + 10,

29283

+ (1<<15) + (11<<10) + (12<<5) + 13,

29284

+ (1<<15) + (14<<10) + (15<<5) + 16,

29285

+ (0<<15) + (17<<10) + (18<<5) + 19,

29286

+ (1<<15) + (20<<10) + (21<<5) + 22,

29287

+ (0<<15) + (23<<10) + (24<<5) + 25};

29288

+ vector unsigned char vucser = {0,255,1,255,2,255,3,255,4,255,5,255,6,255,7,255};

29289

+ vector signed char vscser = {-1,-128,0,127,-2,-128,1,127,

29290

+ -3,-128,2,127,-4,-128,3,127};

29291

+ vector unsigned short vusser = {0,65535,1,65535,2,65535,3,65535};

29292

+ vector signed short vssser = {-1,-32768,0,32767,-2,-32768,1,32767};

29293

+ vector unsigned char vucsuer1 = {0,255,1,255,2,255,3,255,4,255,5,255,6,255,7,255};

29294

+ vector unsigned char vucsuer2 = {0,0,0,127,0,0,1,128,0,0,2,129,0,0,3,130};

29295

+ vector unsigned short vussuer1 = {0,65535,1,65535,2,65535,3,65535};

29296

+ vector unsigned short vussuer2 = {0,0,0,32767,0,0,1,32768};

29297

+#endif

29298

+

29299

+ vucr = vec_pack (vusa, vusb);

29300

+ vscr = vec_pack (vssa, vssb);

29301

+ vbcr = vec_pack (vbsa, vbsb);

29302

+ vusr = vec_pack (vuia, vuib);

29303

+ vssr = vec_pack (vsia, vsib);

29304

+ vbsr = vec_pack (vbia, vbib);

29305

+ vpr = vec_packpx (vipa, vipb);

29306

+ vucsr = vec_packs (vusc, vusd);

29307

+ vscsr = vec_packs (vssc, vssd);

29308

+ vussr = vec_packs (vuic, vuid);

29309

+ vsssr = vec_packs (vsic, vsid);

29310

+ vucsur1 = vec_packsu (vusc, vusd);

29311

+ vucsur2 = vec_packsu (vssc, vssd);

29312

+ vussur1 = vec_packsu (vuic, vuid);

29313

+ vussur2 = vec_packsu (vsic, vsid);

29314

+

29315

+ check (vec_all_eq (vucr, vucer), "vucr");

29316

+ check (vec_all_eq (vscr, vscer), "vscr");

29317

+ check (vec_all_eq (vbcr, vbcer), "vbcr");

29318

+ check (vec_all_eq (vusr, vuser), "vusr");

29319

+ check (vec_all_eq (vssr, vsser), "vssr");

29320

+ check (vec_all_eq (vbsr, vbser), "vbsr");

29321

+ check (vec_all_eq (vpr, vper ), "vpr" );

29322

+ check (vec_all_eq (vucsr, vucser), "vucsr");

29323

+ check (vec_all_eq (vscsr, vscser), "vscsr");

29324

+ check (vec_all_eq (vussr, vusser), "vussr");

29325

+ check (vec_all_eq (vsssr, vssser), "vsssr");

29326

+ check (vec_all_eq (vucsur1, vucsuer1), "vucsur1");

29327

+ check (vec_all_eq (vucsur2, vucsuer2), "vucsur2");

29328

+ check (vec_all_eq (vussur1, vussuer1), "vussur1");

29329

+ check (vec_all_eq (vussur2, vussuer2), "vussur2");

29330

+}

29331

Index: gcc/testsuite/gcc.dg/vmx/st-be-order.c

29332

===================================================================

29333

--- a/src/gcc/testsuite/gcc.dg/vmx/st-be-order.c (.../tags/gcc_4_8_2_release)

29334

+++ b/src/gcc/testsuite/gcc.dg/vmx/st-be-order.c (.../branches/gcc-4_8-branch)

29335

@@ -0,0 +1,83 @@

29336

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */

29337

+

29338

+#include "harness.h"

29339

+

29340

+static unsigned char svuc[16] __attribute__ ((aligned (16)));

29341

+static signed char svsc[16] __attribute__ ((aligned (16)));

29342

+static unsigned char svbc[16] __attribute__ ((aligned (16)));

29343

+static unsigned short svus[8] __attribute__ ((aligned (16)));

29344

+static signed short svss[8] __attribute__ ((aligned (16)));

29345

+static unsigned short svbs[8] __attribute__ ((aligned (16)));

29346

+static unsigned short svp[8] __attribute__ ((aligned (16)));

29347

+static unsigned int svui[4] __attribute__ ((aligned (16)));

29348

+static signed int svsi[4] __attribute__ ((aligned (16)));

29349

+static unsigned int svbi[4] __attribute__ ((aligned (16)));

29350

+static float svf[4] __attribute__ ((aligned (16)));

29351

+

29352

+static void check_arrays ()

29353

+{

29354

+ unsigned int i;

29355

+ for (i = 0; i < 16; ++i)

29356

+ {

29357

+ check (svuc[i] == i, "svuc");

29358

+ check (svsc[i] == i - 8, "svsc");

29359

+ check (svbc[i] == ((i % 2) ? 0xff : 0), "svbc");

29360

+ }

29361

+ for (i = 0; i < 8; ++i)

29362

+ {

29363

+ check (svus[i] == i, "svus");

29364

+ check (svss[i] == i - 4, "svss");

29365

+ check (svbs[i] == ((i % 2) ? 0xffff : 0), "svbs");

29366

+ check (svp[i] == i, "svp");

29367

+ }

29368

+ for (i = 0; i < 4; ++i)

29369

+ {

29370

+ check (svui[i] == i, "svui");

29371

+ check (svsi[i] == i - 2, "svsi");

29372

+ check (svbi[i] == ((i % 2) ? 0xffffffff : 0), "svbi");

29373

+ check (svf[i] == i * 1.0f, "svf");

29374

+ }

29375

+}

29376

+

29377

+static void test ()

29378

+{

29379

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

29380

+ vector unsigned char vuc = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};

29381

+ vector signed char vsc = {7,6,5,4,3,2,1,0,-1,-2,-3,-4,-5,-6,-7,-8};

29382

+ vector bool char vbc = {255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0};

29383

+ vector unsigned short vus = {7,6,5,4,3,2,1,0};

29384

+ vector signed short vss = {3,2,1,0,-1,-2,-3,-4};

29385

+ vector bool short vbs = {65535,0,65535,0,65535,0,65535,0};

29386

+ vector pixel vp = {7,6,5,4,3,2,1,0};

29387

+ vector unsigned int vui = {3,2,1,0};

29388

+ vector signed int vsi = {1,0,-1,-2};

29389

+ vector bool int vbi = {0xffffffff,0,0xffffffff,0};

29390

+ vector float vf = {3.0,2.0,1.0,0.0};

29391

+#else

29392

+ vector unsigned char vuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

29393

+ vector signed char vsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};

29394

+ vector bool char vbc = {0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255};

29395

+ vector unsigned short vus = {0,1,2,3,4,5,6,7};

29396

+ vector signed short vss = {-4,-3,-2,-1,0,1,2,3};

29397

+ vector bool short vbs = {0,65535,0,65535,0,65535,0,65535};

29398

+ vector pixel vp = {0,1,2,3,4,5,6,7};

29399

+ vector unsigned int vui = {0,1,2,3};

29400

+ vector signed int vsi = {-2,-1,0,1};

29401

+ vector bool int vbi = {0,0xffffffff,0,0xffffffff};

29402

+ vector float vf = {0.0,1.0,2.0,3.0};

29403

+#endif

29404

+

29405

+ vec_st (vuc, 0, (vector unsigned char *)svuc);

29406

+ vec_st (vsc, 0, (vector signed char *)svsc);

29407

+ vec_st (vbc, 0, (vector bool char *)svbc);

29408

+ vec_st (vus, 0, (vector unsigned short *)svus);

29409

+ vec_st (vss, 0, (vector signed short *)svss);

29410

+ vec_st (vbs, 0, (vector bool short *)svbs);

29411

+ vec_st (vp, 0, (vector pixel *)svp);

29412

+ vec_st (vui, 0, (vector unsigned int *)svui);

29413

+ vec_st (vsi, 0, (vector signed int *)svsi);

29414

+ vec_st (vbi, 0, (vector bool int *)svbi);

29415

+ vec_st (vf, 0, (vector float *)svf);

29416

+

29417

+ check_arrays ();

29418

+}

29419

Index: gcc/testsuite/gcc.dg/vmx/gcc-bug-i.c

29420

===================================================================

29421

--- a/src/gcc/testsuite/gcc.dg/vmx/gcc-bug-i.c (.../tags/gcc_4_8_2_release)

29422

+++ b/src/gcc/testsuite/gcc.dg/vmx/gcc-bug-i.c (.../branches/gcc-4_8-branch)

29423

@@ -13,6 +13,20 @@

29424

#define DO_INLINE __attribute__ ((always_inline))

29425

#define DONT_INLINE __attribute__ ((noinline))

29426

29427

+#ifdef __LITTLE_ENDIAN__

29428

+static inline DO_INLINE int inline_me(vector signed short data)

29429

+{

29430

+ union {vector signed short v; signed short s[8];} u;

29431

+ signed short x;

29432

+ unsigned char x1, x2;

29433

+

29434

+ u.v = data;

29435

+ x = u.s[7];

29436

+ x1 = (x >> 8) & 0xff;

29437

+ x2 = x & 0xff;

29438

+ return ((x2 << 8) | x1);

29439

+}

29440

+#else

29441

static inline DO_INLINE int inline_me(vector signed short data)

29442

{

29443

union {vector signed short v; signed short s[8];} u;

29444

@@ -19,6 +33,7 @@

29445

u.v = data;

29446

return u.s[7];

29447

}

29448

+#endif

29449

29450

static DONT_INLINE int foo(vector signed short data)

29451

{

29452

Index: gcc/testsuite/gcc.dg/vmx/eg-5.c

29453

===================================================================

29454

--- a/src/gcc/testsuite/gcc.dg/vmx/eg-5.c (.../tags/gcc_4_8_2_release)

29455

+++ b/src/gcc/testsuite/gcc.dg/vmx/eg-5.c (.../branches/gcc-4_8-branch)

29456

@@ -6,12 +6,10 @@

29457

{

29458

/* Set result to a vector of f32 0's */

29459

vector float result = ((vector float){0.,0.,0.,0.});

29460

-

29461

result = vec_madd (c0, vec_splat (v, 0), result);

29462

result = vec_madd (c1, vec_splat (v, 1), result);

29463

result = vec_madd (c2, vec_splat (v, 2), result);

29464

result = vec_madd (c3, vec_splat (v, 3), result);

29465

-

29466

return result;

29467

}

29468

29469

Index: gcc/testsuite/gcc.dg/vmx/st-vsx-be-order.c

29470

===================================================================

29471

--- a/src/gcc/testsuite/gcc.dg/vmx/st-vsx-be-order.c (.../tags/gcc_4_8_2_release)

29472

+++ b/src/gcc/testsuite/gcc.dg/vmx/st-vsx-be-order.c (.../branches/gcc-4_8-branch)

29473

@@ -0,0 +1,34 @@

29474

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

29475

+/* { dg-require-effective-target powerpc_vsx_ok } */

29476

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mvsx" } */

29477

+

29478

+#include "harness.h"

29479

+

29480

+static unsigned long long svul[2] __attribute__ ((aligned (16)));

29481

+static double svd[2] __attribute__ ((aligned (16)));

29482

+

29483

+static void check_arrays ()

29484

+{

29485

+ unsigned int i;

29486

+ for (i = 0; i < 2; ++i)

29487

+ {

29488

+ check (svul[i] == i, "svul");

29489

+ check (svd[i] == i * 1.0, "svd");

29490

+ }

29491

+}

29492

+

29493

+static void test ()

29494

+{

29495

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

29496

+ vector unsigned long long vul = {1,0};

29497

+ vector double vd = {1.0,0.0};

29498

+#else

29499

+ vector unsigned long long vul = {0,1};

29500

+ vector double vd = {0.0,1.0};

29501

+#endif

29502

+

29503

+ vec_st (vul, 0, (vector unsigned long long *)svul);

29504

+ vec_st (vd, 0, (vector double *)svd);

29505

+

29506

+ check_arrays ();

29507

+}

29508

Index: gcc/testsuite/gcc.dg/vmx/lde.c

29509

===================================================================

29510

--- a/src/gcc/testsuite/gcc.dg/vmx/lde.c (.../tags/gcc_4_8_2_release)

29511

+++ b/src/gcc/testsuite/gcc.dg/vmx/lde.c (.../branches/gcc-4_8-branch)

29512

@@ -0,0 +1,59 @@

29513

+#include "harness.h"

29514

+

29515

+static unsigned char svuc[16] __attribute__ ((aligned (16)));

29516

+static signed char svsc[16] __attribute__ ((aligned (16)));

29517

+static unsigned short svus[8] __attribute__ ((aligned (16)));

29518

+static signed short svss[8] __attribute__ ((aligned (16)));

29519

+static unsigned int svui[4] __attribute__ ((aligned (16)));

29520

+static signed int svsi[4] __attribute__ ((aligned (16)));

29521

+static float svf[4] __attribute__ ((aligned (16)));

29522

+

29523

+static void init ()

29524

+{

29525

+ unsigned int i;

29526

+ for (i = 0; i < 16; ++i)

29527

+ {

29528

+ svuc[i] = i;

29529

+ svsc[i] = i - 8;

29530

+ }

29531

+ for (i = 0; i < 8; ++i)

29532

+ {

29533

+ svus[i] = i;

29534

+ svss[i] = i - 4;

29535

+ }

29536

+ for (i = 0; i < 4; ++i)

29537

+ {

29538

+ svui[i] = i;

29539

+ svsi[i] = i - 2;

29540

+ svf[i] = i * 1.0f;

29541

+ }

29542

+}

29543

+

29544

+static void test ()

29545

+{

29546

+ vector unsigned char vuc;

29547

+ vector signed char vsc;

29548

+ vector unsigned short vus;

29549

+ vector signed short vss;

29550

+ vector unsigned int vui;

29551

+ vector signed int vsi;

29552

+ vector float vf;

29553

+

29554

+ init ();

29555

+

29556

+ vuc = vec_lde (9*1, (unsigned char *)svuc);

29557

+ vsc = vec_lde (14*1, (signed char *)svsc);

29558

+ vus = vec_lde (7*2, (unsigned short *)svus);

29559

+ vss = vec_lde (1*2, (signed short *)svss);

29560

+ vui = vec_lde (3*4, (unsigned int *)svui);

29561

+ vsi = vec_lde (2*4, (signed int *)svsi);

29562

+ vf = vec_lde (0*4, (float *)svf);

29563

+

29564

+ check (vec_extract (vuc, 9) == 9, "vuc");

29565

+ check (vec_extract (vsc, 14) == 6, "vsc");

29566

+ check (vec_extract (vus, 7) == 7, "vus");

29567

+ check (vec_extract (vss, 1) == -3, "vss");

29568

+ check (vec_extract (vui, 3) == 3, "vui");

29569

+ check (vec_extract (vsi, 2) == 0, "vsi");

29570

+ check (vec_extract (vf, 0) == 0.0, "vf");

29571

+}

29572

Index: gcc/testsuite/gcc.dg/vmx/pack.c

29573

===================================================================

29574

--- a/src/gcc/testsuite/gcc.dg/vmx/pack.c (.../tags/gcc_4_8_2_release)

29575

+++ b/src/gcc/testsuite/gcc.dg/vmx/pack.c (.../branches/gcc-4_8-branch)

29576

@@ -0,0 +1,108 @@

29577

+#include "harness.h"

29578

+

29579

+#define BIG 4294967295

29580

+

29581

+static void test()

29582

+{

29583

+ /* Input vectors. */

29584

+ vector unsigned short vusa = {0,1,2,3,4,5,6,7};

29585

+ vector unsigned short vusb = {8,9,10,11,12,13,14,15};

29586

+ vector signed short vssa = {-8,-7,-6,-5,-4,-3,-2,-1};

29587

+ vector signed short vssb = {0,1,2,3,4,5,6,7};

29588

+ vector bool short vbsa = {0,65535,65535,0,0,0,65535,0};

29589

+ vector bool short vbsb = {65535,0,0,65535,65535,65535,0,65535};

29590

+ vector unsigned int vuia = {0,1,2,3};

29591

+ vector unsigned int vuib = {4,5,6,7};

29592

+ vector signed int vsia = {-4,-3,-2,-1};

29593

+ vector signed int vsib = {0,1,2,3};

29594

+ vector bool int vbia = {0,BIG,BIG,BIG};

29595

+ vector bool int vbib = {BIG,0,0,0};

29596

+ vector unsigned int vipa = {(0<<24) + (2<<19) + (3<<11) + (4<<3),

29597

+ (1<<24) + (5<<19) + (6<<11) + (7<<3),

29598

+ (0<<24) + (8<<19) + (9<<11) + (10<<3),

29599

+ (1<<24) + (11<<19) + (12<<11) + (13<<3)};

29600

+ vector unsigned int vipb = {(1<<24) + (14<<19) + (15<<11) + (16<<3),

29601

+ (0<<24) + (17<<19) + (18<<11) + (19<<3),

29602

+ (1<<24) + (20<<19) + (21<<11) + (22<<3),

29603

+ (0<<24) + (23<<19) + (24<<11) + (25<<3)};

29604

+ vector unsigned short vusc = {0,256,1,257,2,258,3,259};

29605

+ vector unsigned short vusd = {4,260,5,261,6,262,7,263};

29606

+ vector signed short vssc = {-1,-128,0,127,-2,-129,1,128};

29607

+ vector signed short vssd = {-3,-130,2,129,-4,-131,3,130};

29608

+ vector unsigned int vuic = {0,65536,1,65537};

29609

+ vector unsigned int vuid = {2,65538,3,65539};

29610

+ vector signed int vsic = {-1,-32768,0,32767};

29611

+ vector signed int vsid = {-2,-32769,1,32768};

29612

+

29613

+ /* Result vectors. */

29614

+ vector unsigned char vucr;

29615

+ vector signed char vscr;

29616

+ vector bool char vbcr;

29617

+ vector unsigned short vusr;

29618

+ vector signed short vssr;

29619

+ vector bool short vbsr;

29620

+ vector pixel vpr;

29621

+ vector unsigned char vucsr;

29622

+ vector signed char vscsr;

29623

+ vector unsigned short vussr;

29624

+ vector signed short vsssr;

29625

+ vector unsigned char vucsur1, vucsur2;

29626

+ vector unsigned short vussur1, vussur2;

29627

+

29628

+ /* Expected result vectors. */

29629

+ vector unsigned char vucer = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

29630

+ vector signed char vscer = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};

29631

+ vector bool char vbcer = {0,255,255,0,0,0,255,0,255,0,0,255,255,255,0,255};

29632

+ vector unsigned short vuser = {0,1,2,3,4,5,6,7};

29633

+ vector signed short vsser = {-4,-3,-2,-1,0,1,2,3};

29634

+ vector bool short vbser = {0,65535,65535,65535,65535,0,0,0};

29635

+ vector pixel vper = {(0<<15) + (2<<10) + (3<<5) + 4,

29636

+ (1<<15) + (5<<10) + (6<<5) + 7,

29637

+ (0<<15) + (8<<10) + (9<<5) + 10,

29638

+ (1<<15) + (11<<10) + (12<<5) + 13,

29639

+ (1<<15) + (14<<10) + (15<<5) + 16,

29640

+ (0<<15) + (17<<10) + (18<<5) + 19,

29641

+ (1<<15) + (20<<10) + (21<<5) + 22,

29642

+ (0<<15) + (23<<10) + (24<<5) + 25};

29643

+ vector unsigned char vucser = {0,255,1,255,2,255,3,255,4,255,5,255,6,255,7,255};

29644

+ vector signed char vscser = {-1,-128,0,127,-2,-128,1,127,

29645

+ -3,-128,2,127,-4,-128,3,127};

29646

+ vector unsigned short vusser = {0,65535,1,65535,2,65535,3,65535};

29647

+ vector signed short vssser = {-1,-32768,0,32767,-2,-32768,1,32767};

29648

+ vector unsigned char vucsuer1 = {0,255,1,255,2,255,3,255,4,255,5,255,6,255,7,255};

29649

+ vector unsigned char vucsuer2 = {0,0,0,127,0,0,1,128,0,0,2,129,0,0,3,130};

29650

+ vector unsigned short vussuer1 = {0,65535,1,65535,2,65535,3,65535};

29651

+ vector unsigned short vussuer2 = {0,0,0,32767,0,0,1,32768};

29652

+

29653

+ vucr = vec_pack (vusa, vusb);

29654

+ vscr = vec_pack (vssa, vssb);

29655

+ vbcr = vec_pack (vbsa, vbsb);

29656

+ vusr = vec_pack (vuia, vuib);

29657

+ vssr = vec_pack (vsia, vsib);

29658

+ vbsr = vec_pack (vbia, vbib);

29659

+ vpr = vec_packpx (vipa, vipb);

29660

+ vucsr = vec_packs (vusc, vusd);

29661

+ vscsr = vec_packs (vssc, vssd);

29662

+ vussr = vec_packs (vuic, vuid);

29663

+ vsssr = vec_packs (vsic, vsid);

29664

+ vucsur1 = vec_packsu (vusc, vusd);

29665

+ vucsur2 = vec_packsu (vssc, vssd);

29666

+ vussur1 = vec_packsu (vuic, vuid);

29667

+ vussur2 = vec_packsu (vsic, vsid);

29668

+

29669

+ check (vec_all_eq (vucr, vucer), "vucr");

29670

+ check (vec_all_eq (vscr, vscer), "vscr");

29671

+ check (vec_all_eq (vbcr, vbcer), "vbcr");

29672

+ check (vec_all_eq (vusr, vuser), "vusr");

29673

+ check (vec_all_eq (vssr, vsser), "vssr");

29674

+ check (vec_all_eq (vbsr, vbser), "vbsr");

29675

+ check (vec_all_eq (vpr, vper ), "vpr" );

29676

+ check (vec_all_eq (vucsr, vucser), "vucsr");

29677

+ check (vec_all_eq (vscsr, vscser), "vscsr");

29678

+ check (vec_all_eq (vussr, vusser), "vussr");

29679

+ check (vec_all_eq (vsssr, vssser), "vsssr");

29680

+ check (vec_all_eq (vucsur1, vucsuer1), "vucsur1");

29681

+ check (vec_all_eq (vucsur2, vucsuer2), "vucsur2");

29682

+ check (vec_all_eq (vussur1, vussuer1), "vussur1");

29683

+ check (vec_all_eq (vussur2, vussuer2), "vussur2");

29684

+}

29685

Index: gcc/testsuite/gcc.dg/vmx/unpack-be-order.c

29686

===================================================================

29687

--- a/src/gcc/testsuite/gcc.dg/vmx/unpack-be-order.c (.../tags/gcc_4_8_2_release)

29688

+++ b/src/gcc/testsuite/gcc.dg/vmx/unpack-be-order.c (.../branches/gcc-4_8-branch)

29689

@@ -0,0 +1,88 @@

29690

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */

29691

+

29692

+#include "harness.h"

29693

+

29694

+#define BIG 4294967295

29695

+

29696

+static void test()

29697

+{

29698

+ /* Input vectors. */

29699

+ vector signed char vsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};

29700

+ vector bool char vbc = {0,255,255,0,0,0,255,0,255,0,0,255,255,255,0,255};

29701

+ vector pixel vp = {(0<<15) + (1<<10) + (2<<5) + 3,

29702

+ (1<<15) + (4<<10) + (5<<5) + 6,

29703

+ (0<<15) + (7<<10) + (8<<5) + 9,

29704

+ (1<<15) + (10<<10) + (11<<5) + 12,

29705

+ (1<<15) + (13<<10) + (14<<5) + 15,

29706

+ (0<<15) + (16<<10) + (17<<5) + 18,

29707

+ (1<<15) + (19<<10) + (20<<5) + 21,

29708

+ (0<<15) + (22<<10) + (23<<5) + 24};

29709

+ vector signed short vss = {-4,-3,-2,-1,0,1,2,3};

29710

+ vector bool short vbs = {0,65535,65535,0,0,0,65535,0};

29711

+

29712

+ /* Result vectors. */

29713

+ vector signed short vsch, vscl;

29714

+ vector bool short vbsh, vbsl;

29715

+ vector unsigned int vuih, vuil;

29716

+ vector signed int vsih, vsil;

29717

+ vector bool int vbih, vbil;

29718

+

29719

+ /* Expected result vectors. */

29720

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

29721

+ vector signed short vschr = {0,1,2,3,4,5,6,7};

29722

+ vector signed short vsclr = {-8,-7,-6,-5,-4,-3,-2,-1};

29723

+ vector bool short vbshr = {65535,0,0,65535,65535,65535,0,65535};

29724

+ vector bool short vbslr = {0,65535,65535,0,0,0,65535,0};

29725

+ vector unsigned int vuihr = {(65535<<24) + (13<<16) + (14<<8) + 15,

29726

+ (0<<24) + (16<<16) + (17<<8) + 18,

29727

+ (65535<<24) + (19<<16) + (20<<8) + 21,

29728

+ (0<<24) + (22<<16) + (23<<8) + 24};

29729

+ vector unsigned int vuilr = {(0<<24) + (1<<16) + (2<<8) + 3,

29730

+ (65535<<24) + (4<<16) + (5<<8) + 6,

29731

+ (0<<24) + (7<<16) + (8<<8) + 9,

29732

+ (65535<<24) + (10<<16) + (11<<8) + 12};

29733

+ vector signed int vsihr = {0,1,2,3};

29734

+ vector signed int vsilr = {-4,-3,-2,-1};

29735

+ vector bool int vbihr = {0,0,BIG,0};

29736

+ vector bool int vbilr = {0,BIG,BIG,0};

29737

+#else

29738

+ vector signed short vschr = {-8,-7,-6,-5,-4,-3,-2,-1};

29739

+ vector signed short vsclr = {0,1,2,3,4,5,6,7};

29740

+ vector bool short vbshr = {0,65535,65535,0,0,0,65535,0};

29741

+ vector bool short vbslr = {65535,0,0,65535,65535,65535,0,65535};

29742

+ vector unsigned int vuihr = {(0<<24) + (1<<16) + (2<<8) + 3,

29743

+ (65535<<24) + (4<<16) + (5<<8) + 6,

29744

+ (0<<24) + (7<<16) + (8<<8) + 9,

29745

+ (65535<<24) + (10<<16) + (11<<8) + 12};

29746

+ vector unsigned int vuilr = {(65535<<24) + (13<<16) + (14<<8) + 15,

29747

+ (0<<24) + (16<<16) + (17<<8) + 18,

29748

+ (65535<<24) + (19<<16) + (20<<8) + 21,

29749

+ (0<<24) + (22<<16) + (23<<8) + 24};

29750

+ vector signed int vsihr = {-4,-3,-2,-1};

29751

+ vector signed int vsilr = {0,1,2,3};

29752

+ vector bool int vbihr = {0,BIG,BIG,0};

29753

+ vector bool int vbilr = {0,0,BIG,0};

29754

+#endif

29755

+

29756

+ vsch = vec_unpackh (vsc);

29757

+ vscl = vec_unpackl (vsc);

29758

+ vbsh = vec_unpackh (vbc);

29759

+ vbsl = vec_unpackl (vbc);

29760

+ vuih = vec_unpackh (vp);

29761

+ vuil = vec_unpackl (vp);

29762

+ vsih = vec_unpackh (vss);

29763

+ vsil = vec_unpackl (vss);

29764

+ vbih = vec_unpackh (vbs);

29765

+ vbil = vec_unpackl (vbs);

29766

+

29767

+ check (vec_all_eq (vsch, vschr), "vsch");

29768

+ check (vec_all_eq (vscl, vsclr), "vscl");

29769

+ check (vec_all_eq (vbsh, vbshr), "vbsh");

29770

+ check (vec_all_eq (vbsl, vbslr), "vbsl");

29771

+ check (vec_all_eq (vuih, vuihr), "vuih");

29772

+ check (vec_all_eq (vuil, vuilr), "vuil");

29773

+ check (vec_all_eq (vsih, vsihr), "vsih");

29774

+ check (vec_all_eq (vsil, vsilr), "vsil");

29775

+ check (vec_all_eq (vbih, vbihr), "vbih");

29776

+ check (vec_all_eq (vbil, vbilr), "vbil");

29777

+}

29778

Index: gcc/testsuite/gcc.dg/vmx/st.c

29779

===================================================================

29780

--- a/src/gcc/testsuite/gcc.dg/vmx/st.c (.../tags/gcc_4_8_2_release)

29781

+++ b/src/gcc/testsuite/gcc.dg/vmx/st.c (.../branches/gcc-4_8-branch)

29782

@@ -0,0 +1,67 @@

29783

+#include "harness.h"

29784

+

29785

+static unsigned char svuc[16] __attribute__ ((aligned (16)));

29786

+static signed char svsc[16] __attribute__ ((aligned (16)));

29787

+static unsigned char svbc[16] __attribute__ ((aligned (16)));

29788

+static unsigned short svus[8] __attribute__ ((aligned (16)));

29789

+static signed short svss[8] __attribute__ ((aligned (16)));

29790

+static unsigned short svbs[8] __attribute__ ((aligned (16)));

29791

+static unsigned short svp[8] __attribute__ ((aligned (16)));

29792

+static unsigned int svui[4] __attribute__ ((aligned (16)));

29793

+static signed int svsi[4] __attribute__ ((aligned (16)));

29794

+static unsigned int svbi[4] __attribute__ ((aligned (16)));

29795

+static float svf[4] __attribute__ ((aligned (16)));

29796

+

29797

+static void check_arrays ()

29798

+{

29799

+ unsigned int i;

29800

+ for (i = 0; i < 16; ++i)

29801

+ {

29802

+ check (svuc[i] == i, "svuc");

29803

+ check (svsc[i] == i - 8, "svsc");

29804

+ check (svbc[i] == ((i % 2) ? 0xff : 0), "svbc");

29805

+ }

29806

+ for (i = 0; i < 8; ++i)

29807

+ {

29808

+ check (svus[i] == i, "svus");

29809

+ check (svss[i] == i - 4, "svss");

29810

+ check (svbs[i] == ((i % 2) ? 0xffff : 0), "svbs");

29811

+ check (svp[i] == i, "svp");

29812

+ }

29813

+ for (i = 0; i < 4; ++i)

29814

+ {

29815

+ check (svui[i] == i, "svui");

29816

+ check (svsi[i] == i - 2, "svsi");

29817

+ check (svbi[i] == ((i % 2) ? 0xffffffff : 0), "svbi");

29818

+ check (svf[i] == i * 1.0f, "svf");

29819

+ }

29820

+}

29821

+

29822

+static void test ()

29823

+{

29824

+ vector unsigned char vuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

29825

+ vector signed char vsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};

29826

+ vector bool char vbc = {0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255};

29827

+ vector unsigned short vus = {0,1,2,3,4,5,6,7};

29828

+ vector signed short vss = {-4,-3,-2,-1,0,1,2,3};

29829

+ vector bool short vbs = {0,65535,0,65535,0,65535,0,65535};

29830

+ vector pixel vp = {0,1,2,3,4,5,6,7};

29831

+ vector unsigned int vui = {0,1,2,3};

29832

+ vector signed int vsi = {-2,-1,0,1};

29833

+ vector bool int vbi = {0,0xffffffff,0,0xffffffff};

29834

+ vector float vf = {0.0,1.0,2.0,3.0};

29835

+

29836

+ vec_st (vuc, 0, (vector unsigned char *)svuc);

29837

+ vec_st (vsc, 0, (vector signed char *)svsc);

29838

+ vec_st (vbc, 0, (vector bool char *)svbc);

29839

+ vec_st (vus, 0, (vector unsigned short *)svus);

29840

+ vec_st (vss, 0, (vector signed short *)svss);

29841

+ vec_st (vbs, 0, (vector bool short *)svbs);

29842

+ vec_st (vp, 0, (vector pixel *)svp);

29843

+ vec_st (vui, 0, (vector unsigned int *)svui);

29844

+ vec_st (vsi, 0, (vector signed int *)svsi);

29845

+ vec_st (vbi, 0, (vector bool int *)svbi);

29846

+ vec_st (vf, 0, (vector float *)svf);

29847

+

29848

+ check_arrays ();

29849

+}

29850

Index: gcc/testsuite/gcc.dg/vmx/ste-be-order.c

29851

===================================================================

29852

--- a/src/gcc/testsuite/gcc.dg/vmx/ste-be-order.c (.../tags/gcc_4_8_2_release)

29853

+++ b/src/gcc/testsuite/gcc.dg/vmx/ste-be-order.c (.../branches/gcc-4_8-branch)

29854

@@ -0,0 +1,53 @@

29855

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */

29856

+

29857

+#include "harness.h"

29858

+

29859

+static unsigned char svuc[16] __attribute__ ((aligned (16)));

29860

+static signed char svsc[16] __attribute__ ((aligned (16)));

29861

+static unsigned short svus[8] __attribute__ ((aligned (16)));

29862

+static signed short svss[8] __attribute__ ((aligned (16)));

29863

+static unsigned int svui[4] __attribute__ ((aligned (16)));

29864

+static signed int svsi[4] __attribute__ ((aligned (16)));

29865

+static float svf[4] __attribute__ ((aligned (16)));

29866

+

29867

+static void check_arrays ()

29868

+{

29869

+ check (svuc[9] == 9, "svuc");

29870

+ check (svsc[14] == 6, "svsc");

29871

+ check (svus[7] == 7, "svus");

29872

+ check (svss[1] == -3, "svss");

29873

+ check (svui[3] == 3, "svui");

29874

+ check (svsi[2] == 0, "svsi");

29875

+ check (svf[0] == 0.0, "svf");

29876

+}

29877

+

29878

+static void test ()

29879

+{

29880

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

29881

+ vector unsigned char vuc = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};

29882

+ vector signed char vsc = {7,6,5,4,3,2,1,0,-1,-2,-3,-4,-5,-6,-7,-8};

29883

+ vector unsigned short vus = {7,6,5,4,3,2,1,0};

29884

+ vector signed short vss = {3,2,1,0,-1,-2,-3,-4};

29885

+ vector unsigned int vui = {3,2,1,0};

29886

+ vector signed int vsi = {1,0,-1,-2};

29887

+ vector float vf = {3.0,2.0,1.0,0.0};

29888

+#else

29889

+ vector unsigned char vuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

29890

+ vector signed char vsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};

29891

+ vector unsigned short vus = {0,1,2,3,4,5,6,7};

29892

+ vector signed short vss = {-4,-3,-2,-1,0,1,2,3};

29893

+ vector unsigned int vui = {0,1,2,3};

29894

+ vector signed int vsi = {-2,-1,0,1};

29895

+ vector float vf = {0.0,1.0,2.0,3.0};

29896

+#endif

29897

+

29898

+ vec_ste (vuc, 9*1, (unsigned char *)svuc);

29899

+ vec_ste (vsc, 14*1, (signed char *)svsc);

29900

+ vec_ste (vus, 7*2, (unsigned short *)svus);

29901

+ vec_ste (vss, 1*2, (signed short *)svss);

29902

+ vec_ste (vui, 3*4, (unsigned int *)svui);

29903

+ vec_ste (vsi, 2*4, (signed int *)svsi);

29904

+ vec_ste (vf, 0*4, (float *)svf);

29905

+

29906

+ check_arrays ();

29907

+}

29908

Index: gcc/testsuite/gcc.dg/vmx/insert.c

29909

===================================================================

29910

--- a/src/gcc/testsuite/gcc.dg/vmx/insert.c (.../tags/gcc_4_8_2_release)

29911

+++ b/src/gcc/testsuite/gcc.dg/vmx/insert.c (.../branches/gcc-4_8-branch)

29912

@@ -0,0 +1,37 @@

29913

+#include "harness.h"

29914

+

29915

+static void test()

29916

+{

29917

+ vector unsigned char va = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

29918

+ vector signed char vb = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};

29919

+ vector unsigned short vc = {0,1,2,3,4,5,6,7};

29920

+ vector signed short vd = {-4,-3,-2,-1,0,1,2,3};

29921

+ vector unsigned int ve = {0,1,2,3};

29922

+ vector signed int vf = {-2,-1,0,1};

29923

+ vector float vg = {-2.0f,-1.0f,0.0f,1.0f};

29924

+

29925

+ check (vec_all_eq (vec_insert (16, va, 5),

29926

+ ((vector unsigned char)

29927

+ {0,1,2,3,4,16,6,7,8,9,10,11,12,13,14,15})),

29928

+ "vec_insert (va)");

29929

+ check (vec_all_eq (vec_insert (-16, vb, 0),

29930

+ ((vector signed char)

29931

+ {-16,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7})),

29932

+ "vec_insert (vb)");

29933

+ check (vec_all_eq (vec_insert (16, vc, 7),

29934

+ ((vector unsigned short){0,1,2,3,4,5,6,16})),

29935

+ "vec_insert (vc)");

29936

+ check (vec_all_eq (vec_insert (-16, vd, 3),

29937

+ ((vector signed short){-4,-3,-2,-16,0,1,2,3})),

29938

+ "vec_insert (vd)");

29939

+ check (vec_all_eq (vec_insert (16, ve, 2),

29940

+ ((vector unsigned int){0,1,16,3})),

29941

+ "vec_insert (ve)");

29942

+ check (vec_all_eq (vec_insert (-16, vf, 1),

29943

+ ((vector signed int){-2,-16,0,1})),

29944

+ "vec_insert (vf)");

29945

+ check (vec_all_eq (vec_insert (-16.0f, vg, 0),

29946

+ ((vector float){-16.0f,-1.0f,0.0f,1.0f})),

29947

+ "vec_insert (vg)");

29948

+}

29949

+

29950

Index: gcc/testsuite/gcc.dg/vmx/ld-vsx.c

29951

===================================================================

29952

--- a/src/gcc/testsuite/gcc.dg/vmx/ld-vsx.c (.../tags/gcc_4_8_2_release)

29953

+++ b/src/gcc/testsuite/gcc.dg/vmx/ld-vsx.c (.../branches/gcc-4_8-branch)

29954

@@ -0,0 +1,39 @@

29955

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

29956

+/* { dg-require-effective-target powerpc_vsx_ok } */

29957

+/* { dg-options "-maltivec -mabi=altivec -std=gnu99 -mvsx" } */

29958

+

29959

+#include "harness.h"

29960

+

29961

+static unsigned long long svul[2] __attribute__ ((aligned (16)));

29962

+static double svd[2] __attribute__ ((aligned (16)));

29963

+

29964

+static void init ()

29965

+{

29966

+ unsigned int i;

29967

+ for (i = 0; i < 2; ++i)

29968

+ {

29969

+ svul[i] = i;

29970

+ svd[i] = i * 1.0;

29971

+ }

29972

+}

29973

+

29974

+static void test ()

29975

+{

29976

+ vector unsigned long long evul = {0,1};

29977

+ vector double evd = {0.0,1.0};

29978

+

29979

+ vector unsigned long long vul;

29980

+ vector double vd;

29981

+ unsigned i;

29982

+

29983

+ init ();

29984

+

29985

+ vul = vec_ld (0, (vector unsigned long long *)svul);

29986

+ vd = vec_ld (0, (vector double *)svd);

29987

+

29988

+ for (i = 0; i < 2; ++i)

29989

+ {

29990

+ check (vul[i] == evul[i], "vul");

29991

+ check (vd[i] == evd[i], "vd" );

29992

+ }

29993

+}

29994

Index: gcc/testsuite/gcc.dg/vmx/extract-vsx.c

29995

===================================================================

29996

--- a/src/gcc/testsuite/gcc.dg/vmx/extract-vsx.c (.../tags/gcc_4_8_2_release)

29997

+++ b/src/gcc/testsuite/gcc.dg/vmx/extract-vsx.c (.../branches/gcc-4_8-branch)

29998

@@ -0,0 +1,16 @@

29999

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

30000

+/* { dg-require-effective-target powerpc_vsx_ok } */

30001

+/* { dg-options "-maltivec -mabi=altivec -std=gnu99 -mvsx" } */

30002

+

30003

+#include "harness.h"

30004

+

30005

+static void test()

30006

+{

30007

+ vector long long vl = {0, 1};

30008

+ vector double vd = {0.0, 1.0};

30009

+

30010

+ check (vec_extract (vl, 0) == 0, "vec_extract, vl, 0");

30011

+ check (vec_extract (vd, 1) == 1.0, "vec_extract, vd, 1");

30012

+ check (vl[0] == 0, "[], vl, 0");

30013

+ check (vd[1] == 1.0, "[], vd, 0");

30014

+}

30015

Index: gcc/testsuite/gcc.dg/vmx/perm.c

30016

===================================================================

30017

--- a/src/gcc/testsuite/gcc.dg/vmx/perm.c (.../tags/gcc_4_8_2_release)

30018

+++ b/src/gcc/testsuite/gcc.dg/vmx/perm.c (.../branches/gcc-4_8-branch)

30019

@@ -0,0 +1,69 @@

30020

+#include "harness.h"

30021

+

30022

+static void test()

30023

+{

30024

+ /* Input vectors. */

30025

+ vector unsigned char vuca = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

30026

+ vector unsigned char vucb

30027

+ = {16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31};

30028

+ vector unsigned char vucp = {0,31,1,30,2,29,3,28,4,27,5,26,6,25,7,24};

30029

+

30030

+ vector signed char vsca

30031

+ = {-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1};

30032

+ vector signed char vscb = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

30033

+ vector unsigned char vscp = {0,31,1,30,2,29,3,28,4,27,5,26,6,25,7,24};

30034

+

30035

+ vector unsigned short vusa = {0,1,2,3,4,5,6,7};

30036

+ vector unsigned short vusb = {8,9,10,11,12,13,14,15};

30037

+ vector unsigned char vusp = {0,1,30,31,2,3,28,29,4,5,26,27,6,7,24,25};

30038

+

30039

+ vector signed short vssa = {-8,-7,-6,-5,-4,-3,-2,-1};

30040

+ vector signed short vssb = {0,1,2,3,4,5,6,7};

30041

+ vector unsigned char vssp = {0,1,30,31,2,3,28,29,4,5,26,27,6,7,24,25};

30042

+

30043

+ vector unsigned int vuia = {0,1,2,3};

30044

+ vector unsigned int vuib = {4,5,6,7};

30045

+ vector unsigned char vuip = {0,1,2,3,28,29,30,31,4,5,6,7,24,25,26,27};

30046

+

30047

+ vector signed int vsia = {-4,-3,-2,-1};

30048

+ vector signed int vsib = {0,1,2,3};

30049

+ vector unsigned char vsip = {0,1,2,3,28,29,30,31,4,5,6,7,24,25,26,27};

30050

+

30051

+ vector float vfa = {-4.0,-3.0,-2.0,-1.0};

30052

+ vector float vfb = {0.0,1.0,2.0,3.0};

30053

+ vector unsigned char vfp = {0,1,2,3,28,29,30,31,4,5,6,7,24,25,26,27};

30054

+

30055

+ /* Result vectors. */

30056

+ vector unsigned char vuc;

30057

+ vector signed char vsc;

30058

+ vector unsigned short vus;

30059

+ vector signed short vss;

30060

+ vector unsigned int vui;

30061

+ vector signed int vsi;

30062

+ vector float vf;

30063

+

30064

+ /* Expected result vectors. */

30065

+ vector unsigned char vucr = {0,31,1,30,2,29,3,28,4,27,5,26,6,25,7,24};

30066

+ vector signed char vscr = {-16,15,-15,14,-14,13,-13,12,-12,11,-11,10,-10,9,-9,8};

30067

+ vector unsigned short vusr = {0,15,1,14,2,13,3,12};

30068

+ vector signed short vssr = {-8,7,-7,6,-6,5,-5,4};

30069

+ vector unsigned int vuir = {0,7,1,6};

30070

+ vector signed int vsir = {-4,3,-3,2};

30071

+ vector float vfr = {-4.0,3.0,-3.0,2.0};

30072

+

30073

+ vuc = vec_perm (vuca, vucb, vucp);

30074

+ vsc = vec_perm (vsca, vscb, vscp);

30075

+ vus = vec_perm (vusa, vusb, vusp);

30076

+ vss = vec_perm (vssa, vssb, vssp);

30077

+ vui = vec_perm (vuia, vuib, vuip);

30078

+ vsi = vec_perm (vsia, vsib, vsip);

30079

+ vf = vec_perm (vfa, vfb, vfp );

30080

+

30081

+ check (vec_all_eq (vuc, vucr), "vuc");

30082

+ check (vec_all_eq (vsc, vscr), "vsc");

30083

+ check (vec_all_eq (vus, vusr), "vus");

30084

+ check (vec_all_eq (vss, vssr), "vss");

30085

+ check (vec_all_eq (vui, vuir), "vui");

30086

+ check (vec_all_eq (vsi, vsir), "vsi");

30087

+ check (vec_all_eq (vf, vfr), "vf" );

30088

+}

30089

Index: gcc/testsuite/gcc.dg/vmx/extract-be-order.c

30090

===================================================================

30091

--- a/src/gcc/testsuite/gcc.dg/vmx/extract-be-order.c (.../tags/gcc_4_8_2_release)

30092

+++ b/src/gcc/testsuite/gcc.dg/vmx/extract-be-order.c (.../branches/gcc-4_8-branch)

30093

@@ -0,0 +1,33 @@

30094

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */

30095

+

30096

+#include "harness.h"

30097

+

30098

+static void test()

30099

+{

30100

+ vector unsigned char va = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

30101

+ vector signed char vb = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};

30102

+ vector unsigned short vc = {0,1,2,3,4,5,6,7};

30103

+ vector signed short vd = {-4,-3,-2,-1,0,1,2,3};

30104

+ vector unsigned int ve = {0,1,2,3};

30105

+ vector signed int vf = {-2,-1,0,1};

30106

+ vector float vg = {-2.0f,-1.0f,0.0f,1.0f};

30107

+

30108

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

30109

+ check (vec_extract (va, 5) == 10, "vec_extract (va, 5)");

30110

+ check (vec_extract (vb, 0) == 7, "vec_extract (vb, 0)");

30111

+ check (vec_extract (vc, 7) == 0, "vec_extract (vc, 7)");

30112

+ check (vec_extract (vd, 3) == 0, "vec_extract (vd, 3)");

30113

+ check (vec_extract (ve, 2) == 1, "vec_extract (ve, 2)");

30114

+ check (vec_extract (vf, 1) == 0, "vec_extract (vf, 1)");

30115

+ check (vec_extract (vg, 0) == 1.0f, "vec_extract (vg, 0)");

30116

+#else

30117

+ check (vec_extract (va, 5) == 5, "vec_extract (va, 5)");

30118

+ check (vec_extract (vb, 0) == -8, "vec_extract (vb, 0)");

30119

+ check (vec_extract (vc, 7) == 7, "vec_extract (vc, 7)");

30120

+ check (vec_extract (vd, 3) == -1, "vec_extract (vd, 3)");

30121

+ check (vec_extract (ve, 2) == 2, "vec_extract (ve, 2)");

30122

+ check (vec_extract (vf, 1) == -1, "vec_extract (vf, 1)");

30123

+ check (vec_extract (vg, 0) == -2.0f, "vec_extract (vg, 0)");

30124

+#endif

30125

+}

30126

+

30127

Index: gcc/testsuite/gcc.dg/vmx/ldl-be-order.c

30128

===================================================================

30129

--- a/src/gcc/testsuite/gcc.dg/vmx/ldl-be-order.c (.../tags/gcc_4_8_2_release)

30130

+++ b/src/gcc/testsuite/gcc.dg/vmx/ldl-be-order.c (.../branches/gcc-4_8-branch)

30131

@@ -0,0 +1,107 @@

30132

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */

30133

+

30134

+#include "harness.h"

30135

+

30136

+static unsigned char svuc[16] __attribute__ ((aligned (16)));

30137

+static signed char svsc[16] __attribute__ ((aligned (16)));

30138

+static unsigned char svbc[16] __attribute__ ((aligned (16)));

30139

+static unsigned short svus[8] __attribute__ ((aligned (16)));

30140

+static signed short svss[8] __attribute__ ((aligned (16)));

30141

+static unsigned short svbs[8] __attribute__ ((aligned (16)));

30142

+static unsigned short svp[8] __attribute__ ((aligned (16)));

30143

+static unsigned int svui[4] __attribute__ ((aligned (16)));

30144

+static signed int svsi[4] __attribute__ ((aligned (16)));

30145

+static unsigned int svbi[4] __attribute__ ((aligned (16)));

30146

+static float svf[4] __attribute__ ((aligned (16)));

30147

+

30148

+static void init ()

30149

+{

30150

+ unsigned int i;

30151

+ for (i = 0; i < 16; ++i)

30152

+ {

30153

+ svuc[i] = i;

30154

+ svsc[i] = i - 8;

30155

+ svbc[i] = (i % 2) ? 0xff : 0;

30156

+ }

30157

+ for (i = 0; i < 8; ++i)

30158

+ {

30159

+ svus[i] = i;

30160

+ svss[i] = i - 4;

30161

+ svbs[i] = (i % 2) ? 0xffff : 0;

30162

+ svp[i] = i;

30163

+ }

30164

+ for (i = 0; i < 4; ++i)

30165

+ {

30166

+ svui[i] = i;

30167

+ svsi[i] = i - 2;

30168

+ svbi[i] = (i % 2) ? 0xffffffff : 0;

30169

+ svf[i] = i * 1.0f;

30170

+ }

30171

+}

30172

+

30173

+static void test ()

30174

+{

30175

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

30176

+ vector unsigned char evuc = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};

30177

+ vector signed char evsc = {7,6,5,4,3,2,1,0,-1,-2,-3,-4,-5,-6,-7,-8};

30178

+ vector bool char evbc = {255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0};

30179

+ vector unsigned short evus = {7,6,5,4,3,2,1,0};

30180

+ vector signed short evss = {3,2,1,0,-1,-2,-3,-4};

30181

+ vector bool short evbs = {65535,0,65535,0,65535,0,65535,0};

30182

+ vector pixel evp = {7,6,5,4,3,2,1,0};

30183

+ vector unsigned int evui = {3,2,1,0};

30184

+ vector signed int evsi = {1,0,-1,-2};

30185

+ vector bool int evbi = {0xffffffff,0,0xffffffff,0};

30186

+ vector float evf = {3.0,2.0,1.0,0.0};

30187

+#else

30188

+ vector unsigned char evuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

30189

+ vector signed char evsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};

30190

+ vector bool char evbc = {0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255};

30191

+ vector unsigned short evus = {0,1,2,3,4,5,6,7};

30192

+ vector signed short evss = {-4,-3,-2,-1,0,1,2,3};

30193

+ vector bool short evbs = {0,65535,0,65535,0,65535,0,65535};

30194

+ vector pixel evp = {0,1,2,3,4,5,6,7};

30195

+ vector unsigned int evui = {0,1,2,3};

30196

+ vector signed int evsi = {-2,-1,0,1};

30197

+ vector bool int evbi = {0,0xffffffff,0,0xffffffff};

30198

+ vector float evf = {0.0,1.0,2.0,3.0};

30199

+#endif

30200

+

30201

+ vector unsigned char vuc;

30202

+ vector signed char vsc;

30203

+ vector bool char vbc;

30204

+ vector unsigned short vus;

30205

+ vector signed short vss;

30206

+ vector bool short vbs;

30207

+ vector pixel vp;

30208

+ vector unsigned int vui;

30209

+ vector signed int vsi;

30210

+ vector bool int vbi;

30211

+ vector float vf;

30212

+

30213

+ init ();

30214

+

30215

+ vuc = vec_ldl (0, (vector unsigned char *)svuc);

30216

+ vsc = vec_ldl (0, (vector signed char *)svsc);

30217

+ vbc = vec_ldl (0, (vector bool char *)svbc);

30218

+ vus = vec_ldl (0, (vector unsigned short *)svus);

30219

+ vss = vec_ldl (0, (vector signed short *)svss);

30220

+ vbs = vec_ldl (0, (vector bool short *)svbs);

30221

+ vp = vec_ldl (0, (vector pixel *)svp);

30222

+ vui = vec_ldl (0, (vector unsigned int *)svui);

30223

+ vsi = vec_ldl (0, (vector signed int *)svsi);

30224

+ vbi = vec_ldl (0, (vector bool int *)svbi);

30225

+ vf = vec_ldl (0, (vector float *)svf);

30226

+

30227

+ check (vec_all_eq (vuc, evuc), "vuc");

30228

+ check (vec_all_eq (vsc, evsc), "vsc");

30229

+ check (vec_all_eq (vbc, evbc), "vbc");

30230

+ check (vec_all_eq (vus, evus), "vus");

30231

+ check (vec_all_eq (vss, evss), "vss");

30232

+ check (vec_all_eq (vbs, evbs), "vbs");

30233

+ check (vec_all_eq (vp, evp ), "vp" );

30234

+ check (vec_all_eq (vui, evui), "vui");

30235

+ check (vec_all_eq (vsi, evsi), "vsi");

30236

+ check (vec_all_eq (vbi, evbi), "vbi");

30237

+ check (vec_all_eq (vf, evf ), "vf" );

30238

+}

30239

Index: gcc/testsuite/gcc.dg/vmx/mult-even-odd.c

30240

===================================================================

30241

--- a/src/gcc/testsuite/gcc.dg/vmx/mult-even-odd.c (.../tags/gcc_4_8_2_release)

30242

+++ b/src/gcc/testsuite/gcc.dg/vmx/mult-even-odd.c (.../branches/gcc-4_8-branch)

30243

@@ -0,0 +1,43 @@

30244

+#include "harness.h"

30245

+

30246

+static void test()

30247

+{

30248

+ vector unsigned char vuca = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

30249

+ vector unsigned char vucb = {2,3,2,3,2,3,2,3,2,3,2,3,2,3,2,3};

30250

+ vector signed char vsca = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};

30251

+ vector signed char vscb = {2,-3,2,-3,2,-3,2,-3,2,-3,2,-3,2,-3,2,-3};

30252

+ vector unsigned short vusa = {0,1,2,3,4,5,6,7};

30253

+ vector unsigned short vusb = {2,3,2,3,2,3,2,3};

30254

+ vector signed short vssa = {-4,-3,-2,-1,0,1,2,3};

30255

+ vector signed short vssb = {2,-3,2,-3,2,-3,2,-3};

30256

+ vector unsigned short vuse, vuso;

30257

+ vector signed short vsse, vsso;

30258

+ vector unsigned int vuie, vuio;

30259

+ vector signed int vsie, vsio;

30260

+

30261

+ vuse = vec_mule (vuca, vucb);

30262

+ vuso = vec_mulo (vuca, vucb);

30263

+ vsse = vec_mule (vsca, vscb);

30264

+ vsso = vec_mulo (vsca, vscb);

30265

+ vuie = vec_mule (vusa, vusb);

30266

+ vuio = vec_mulo (vusa, vusb);

30267

+ vsie = vec_mule (vssa, vssb);

30268

+ vsio = vec_mulo (vssa, vssb);

30269

+

30270

+ check (vec_all_eq (vuse,

30271

+ ((vector unsigned short){0,4,8,12,16,20,24,28})),

30272

+ "vuse");

30273

+ check (vec_all_eq (vuso,

30274

+ ((vector unsigned short){3,9,15,21,27,33,39,45})),

30275

+ "vuso");

30276

+ check (vec_all_eq (vsse,

30277

+ ((vector signed short){-16,-12,-8,-4,0,4,8,12})),

30278

+ "vsse");

30279

+ check (vec_all_eq (vsso,

30280

+ ((vector signed short){21,15,9,3,-3,-9,-15,-21})),

30281

+ "vsso");

30282

+ check (vec_all_eq (vuie, ((vector unsigned int){0,4,8,12})), "vuie");

30283

+ check (vec_all_eq (vuio, ((vector unsigned int){3,9,15,21})), "vuio");

30284

+ check (vec_all_eq (vsie, ((vector signed int){-8,-4,0,4})), "vsie");

30285

+ check (vec_all_eq (vsio, ((vector signed int){9,3,-3,-9})), "vsio");

30286

+}

30287

Index: gcc/testsuite/gcc.dg/vmx/splat-be-order.c

30288

===================================================================

30289

--- a/src/gcc/testsuite/gcc.dg/vmx/splat-be-order.c (.../tags/gcc_4_8_2_release)

30290

+++ b/src/gcc/testsuite/gcc.dg/vmx/splat-be-order.c (.../branches/gcc-4_8-branch)

30291

@@ -0,0 +1,59 @@

30292

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */

30293

+

30294

+#include "harness.h"

30295

+

30296

+static void test()

30297

+{

30298

+ /* Input vectors. */

30299

+ vector unsigned char vuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

30300

+ vector signed char vsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};

30301

+ vector unsigned short vus = {0,1,2,3,4,5,6,7};

30302

+ vector signed short vss = {-4,-3,-2,-1,0,1,2,3};

30303

+ vector unsigned int vui = {0,1,2,3};

30304

+ vector signed int vsi = {-2,-1,0,1};

30305

+ vector float vf = {-2.0,-1.0,0.0,1.0};

30306

+

30307

+ /* Result vectors. */

30308

+ vector unsigned char vucr;

30309

+ vector signed char vscr;

30310

+ vector unsigned short vusr;

30311

+ vector signed short vssr;

30312

+ vector unsigned int vuir;

30313

+ vector signed int vsir;

30314

+ vector float vfr;

30315

+

30316

+ /* Expected result vectors. */

30317

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

30318

+ vector unsigned char vucer = {14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14};

30319

+ vector signed char vscer = {-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1};

30320

+ vector unsigned short vuser = {0,0,0,0,0,0,0,0};

30321

+ vector signed short vsser = {3,3,3,3,3,3,3,3};

30322

+ vector unsigned int vuier = {1,1,1,1};

30323

+ vector signed int vsier = {-2,-2,-2,-2};

30324

+ vector float vfer = {0.0,0.0,0.0,0.0};

30325

+#else

30326

+ vector unsigned char vucer = {1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1};

30327

+ vector signed char vscer = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};

30328

+ vector unsigned short vuser = {7,7,7,7,7,7,7,7};

30329

+ vector signed short vsser = {-4,-4,-4,-4,-4,-4,-4,-4};

30330

+ vector unsigned int vuier = {2,2,2,2};

30331

+ vector signed int vsier = {1,1,1,1};

30332

+ vector float vfer = {-1.0,-1.0,-1.0,-1.0};

30333

+#endif

30334

+

30335

+ vucr = vec_splat (vuc, 1);

30336

+ vscr = vec_splat (vsc, 8);

30337

+ vusr = vec_splat (vus, 7);

30338

+ vssr = vec_splat (vss, 0);

30339

+ vuir = vec_splat (vui, 2);

30340

+ vsir = vec_splat (vsi, 3);

30341

+ vfr = vec_splat (vf, 1);

30342

+

30343

+ check (vec_all_eq (vucr, vucer), "vuc");

30344

+ check (vec_all_eq (vscr, vscer), "vsc");

30345

+ check (vec_all_eq (vusr, vuser), "vus");

30346

+ check (vec_all_eq (vssr, vsser), "vss");

30347

+ check (vec_all_eq (vuir, vuier), "vui");

30348

+ check (vec_all_eq (vsir, vsier), "vsi");

30349

+ check (vec_all_eq (vfr, vfer ), "vf");

30350

+}

30351

Index: gcc/testsuite/gcc.dg/vmx/extract-vsx-be-order.c

30352

===================================================================

30353

--- a/src/gcc/testsuite/gcc.dg/vmx/extract-vsx-be-order.c (.../tags/gcc_4_8_2_release)

30354

+++ b/src/gcc/testsuite/gcc.dg/vmx/extract-vsx-be-order.c (.../branches/gcc-4_8-branch)

30355

@@ -0,0 +1,19 @@

30356

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

30357

+/* { dg-require-effective-target powerpc_vsx_ok } */

30358

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mvsx" } */

30359

+

30360

+#include "harness.h"

30361

+

30362

+static void test()

30363

+{

30364

+ vector long long vl = {0, 1};

30365

+ vector double vd = {0.0, 1.0};

30366

+

30367

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

30368

+ check (vec_extract (vl, 0) == 1, "vl, 0");

30369

+ check (vec_extract (vd, 1) == 0.0, "vd, 1");

30370

+#else

30371

+ check (vec_extract (vl, 0) == 0, "vl, 0");

30372

+ check (vec_extract (vd, 1) == 1.0, "vd, 1");

30373

+#endif

30374

+}

30375

Index: gcc/testsuite/gcc.dg/vmx/ld-be-order.c

30376

===================================================================

30377

--- a/src/gcc/testsuite/gcc.dg/vmx/ld-be-order.c (.../tags/gcc_4_8_2_release)

30378

+++ b/src/gcc/testsuite/gcc.dg/vmx/ld-be-order.c (.../branches/gcc-4_8-branch)

30379

@@ -0,0 +1,107 @@

30380

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */

30381

+

30382

+#include "harness.h"

30383

+

30384

+static unsigned char svuc[16] __attribute__ ((aligned (16)));

30385

+static signed char svsc[16] __attribute__ ((aligned (16)));

30386

+static unsigned char svbc[16] __attribute__ ((aligned (16)));

30387

+static unsigned short svus[8] __attribute__ ((aligned (16)));

30388

+static signed short svss[8] __attribute__ ((aligned (16)));

30389

+static unsigned short svbs[8] __attribute__ ((aligned (16)));

30390

+static unsigned short svp[8] __attribute__ ((aligned (16)));

30391

+static unsigned int svui[4] __attribute__ ((aligned (16)));

30392

+static signed int svsi[4] __attribute__ ((aligned (16)));

30393

+static unsigned int svbi[4] __attribute__ ((aligned (16)));

30394

+static float svf[4] __attribute__ ((aligned (16)));

30395

+

30396

+static void init ()

30397

+{

30398

+ unsigned int i;

30399

+ for (i = 0; i < 16; ++i)

30400

+ {

30401

+ svuc[i] = i;

30402

+ svsc[i] = i - 8;

30403

+ svbc[i] = (i % 2) ? 0xff : 0;

30404

+ }

30405

+ for (i = 0; i < 8; ++i)

30406

+ {

30407

+ svus[i] = i;

30408

+ svss[i] = i - 4;

30409

+ svbs[i] = (i % 2) ? 0xffff : 0;

30410

+ svp[i] = i;

30411

+ }

30412

+ for (i = 0; i < 4; ++i)

30413

+ {

30414

+ svui[i] = i;

30415

+ svsi[i] = i - 2;

30416

+ svbi[i] = (i % 2) ? 0xffffffff : 0;

30417

+ svf[i] = i * 1.0f;

30418

+ }

30419

+}

30420

+

30421

+static void test ()

30422

+{

30423

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

30424

+ vector unsigned char evuc = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};

30425

+ vector signed char evsc = {7,6,5,4,3,2,1,0,-1,-2,-3,-4,-5,-6,-7,-8};

30426

+ vector bool char evbc = {255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0};

30427

+ vector unsigned short evus = {7,6,5,4,3,2,1,0};

30428

+ vector signed short evss = {3,2,1,0,-1,-2,-3,-4};

30429

+ vector bool short evbs = {65535,0,65535,0,65535,0,65535,0};

30430

+ vector pixel evp = {7,6,5,4,3,2,1,0};

30431

+ vector unsigned int evui = {3,2,1,0};

30432

+ vector signed int evsi = {1,0,-1,-2};

30433

+ vector bool int evbi = {0xffffffff,0,0xffffffff,0};

30434

+ vector float evf = {3.0,2.0,1.0,0.0};

30435

+#else

30436

+ vector unsigned char evuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

30437

+ vector signed char evsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};

30438

+ vector bool char evbc = {0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255};

30439

+ vector unsigned short evus = {0,1,2,3,4,5,6,7};

30440

+ vector signed short evss = {-4,-3,-2,-1,0,1,2,3};

30441

+ vector bool short evbs = {0,65535,0,65535,0,65535,0,65535};

30442

+ vector pixel evp = {0,1,2,3,4,5,6,7};

30443

+ vector unsigned int evui = {0,1,2,3};

30444

+ vector signed int evsi = {-2,-1,0,1};

30445

+ vector bool int evbi = {0,0xffffffff,0,0xffffffff};

30446

+ vector float evf = {0.0,1.0,2.0,3.0};

30447

+#endif

30448

+

30449

+ vector unsigned char vuc;

30450

+ vector signed char vsc;

30451

+ vector bool char vbc;

30452

+ vector unsigned short vus;

30453

+ vector signed short vss;

30454

+ vector bool short vbs;

30455

+ vector pixel vp;

30456

+ vector unsigned int vui;

30457

+ vector signed int vsi;

30458

+ vector bool int vbi;

30459

+ vector float vf;

30460

+

30461

+ init ();

30462

+

30463

+ vuc = vec_ld (0, (vector unsigned char *)svuc);

30464

+ vsc = vec_ld (0, (vector signed char *)svsc);

30465

+ vbc = vec_ld (0, (vector bool char *)svbc);

30466

+ vus = vec_ld (0, (vector unsigned short *)svus);

30467

+ vss = vec_ld (0, (vector signed short *)svss);

30468

+ vbs = vec_ld (0, (vector bool short *)svbs);

30469

+ vp = vec_ld (0, (vector pixel *)svp);

30470

+ vui = vec_ld (0, (vector unsigned int *)svui);

30471

+ vsi = vec_ld (0, (vector signed int *)svsi);

30472

+ vbi = vec_ld (0, (vector bool int *)svbi);

30473

+ vf = vec_ld (0, (vector float *)svf);

30474

+

30475

+ check (vec_all_eq (vuc, evuc), "vuc");

30476

+ check (vec_all_eq (vsc, evsc), "vsc");

30477

+ check (vec_all_eq (vbc, evbc), "vbc");

30478

+ check (vec_all_eq (vus, evus), "vus");

30479

+ check (vec_all_eq (vss, evss), "vss");

30480

+ check (vec_all_eq (vbs, evbs), "vbs");

30481

+ check (vec_all_eq (vp, evp ), "vp" );

30482

+ check (vec_all_eq (vui, evui), "vui");

30483

+ check (vec_all_eq (vsi, evsi), "vsi");

30484

+ check (vec_all_eq (vbi, evbi), "vbi");

30485

+ check (vec_all_eq (vf, evf ), "vf" );

30486

+}

30487

Index: gcc/testsuite/gcc.dg/vmx/ld.c

30488

===================================================================

30489

--- a/src/gcc/testsuite/gcc.dg/vmx/ld.c (.../tags/gcc_4_8_2_release)

30490

+++ b/src/gcc/testsuite/gcc.dg/vmx/ld.c (.../branches/gcc-4_8-branch)

30491

@@ -0,0 +1,91 @@

30492

+#include "harness.h"

30493

+

30494

+static unsigned char svuc[16] __attribute__ ((aligned (16)));

30495

+static signed char svsc[16] __attribute__ ((aligned (16)));

30496

+static unsigned char svbc[16] __attribute__ ((aligned (16)));

30497

+static unsigned short svus[8] __attribute__ ((aligned (16)));

30498

+static signed short svss[8] __attribute__ ((aligned (16)));

30499

+static unsigned short svbs[8] __attribute__ ((aligned (16)));

30500

+static unsigned short svp[8] __attribute__ ((aligned (16)));

30501

+static unsigned int svui[4] __attribute__ ((aligned (16)));

30502

+static signed int svsi[4] __attribute__ ((aligned (16)));

30503

+static unsigned int svbi[4] __attribute__ ((aligned (16)));

30504

+static float svf[4] __attribute__ ((aligned (16)));

30505

+

30506

+static void init ()

30507

+{

30508

+ unsigned int i;

30509

+ for (i = 0; i < 16; ++i)

30510

+ {

30511

+ svuc[i] = i;

30512

+ svsc[i] = i - 8;

30513

+ svbc[i] = (i % 2) ? 0xff : 0;

30514

+ }

30515

+ for (i = 0; i < 8; ++i)

30516

+ {

30517

+ svus[i] = i;

30518

+ svss[i] = i - 4;

30519

+ svbs[i] = (i % 2) ? 0xffff : 0;

30520

+ svp[i] = i;

30521

+ }

30522

+ for (i = 0; i < 4; ++i)

30523

+ {

30524

+ svui[i] = i;

30525

+ svsi[i] = i - 2;

30526

+ svbi[i] = (i % 2) ? 0xffffffff : 0;

30527

+ svf[i] = i * 1.0f;

30528

+ }

30529

+}

30530

+

30531

+static void test ()

30532

+{

30533

+ vector unsigned char evuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

30534

+ vector signed char evsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};

30535

+ vector bool char evbc = {0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255};

30536

+ vector unsigned short evus = {0,1,2,3,4,5,6,7};

30537

+ vector signed short evss = {-4,-3,-2,-1,0,1,2,3};

30538

+ vector bool short evbs = {0,65535,0,65535,0,65535,0,65535};

30539

+ vector pixel evp = {0,1,2,3,4,5,6,7};

30540

+ vector unsigned int evui = {0,1,2,3};

30541

+ vector signed int evsi = {-2,-1,0,1};

30542

+ vector bool int evbi = {0,0xffffffff,0,0xffffffff};

30543

+ vector float evf = {0.0,1.0,2.0,3.0};

30544

+

30545

+ vector unsigned char vuc;

30546

+ vector signed char vsc;

30547

+ vector bool char vbc;

30548

+ vector unsigned short vus;

30549

+ vector signed short vss;

30550

+ vector bool short vbs;

30551

+ vector pixel vp;

30552

+ vector unsigned int vui;

30553

+ vector signed int vsi;

30554

+ vector bool int vbi;

30555

+ vector float vf;

30556

+

30557

+ init ();

30558

+

30559

+ vuc = vec_ld (0, (vector unsigned char *)svuc);

30560

+ vsc = vec_ld (0, (vector signed char *)svsc);

30561

+ vbc = vec_ld (0, (vector bool char *)svbc);

30562

+ vus = vec_ld (0, (vector unsigned short *)svus);

30563

+ vss = vec_ld (0, (vector signed short *)svss);

30564

+ vbs = vec_ld (0, (vector bool short *)svbs);

30565

+ vp = vec_ld (0, (vector pixel *)svp);

30566

+ vui = vec_ld (0, (vector unsigned int *)svui);

30567

+ vsi = vec_ld (0, (vector signed int *)svsi);

30568

+ vbi = vec_ld (0, (vector bool int *)svbi);

30569

+ vf = vec_ld (0, (vector float *)svf);

30570

+

30571

+ check (vec_all_eq (vuc, evuc), "vuc");

30572

+ check (vec_all_eq (vsc, evsc), "vsc");

30573

+ check (vec_all_eq (vbc, evbc), "vbc");

30574

+ check (vec_all_eq (vus, evus), "vus");

30575

+ check (vec_all_eq (vss, evss), "vss");

30576

+ check (vec_all_eq (vbs, evbs), "vbs");

30577

+ check (vec_all_eq (vp, evp ), "vp" );

30578

+ check (vec_all_eq (vui, evui), "vui");

30579

+ check (vec_all_eq (vsi, evsi), "vsi");

30580

+ check (vec_all_eq (vbi, evbi), "vbi");

30581

+ check (vec_all_eq (vf, evf ), "vf" );

30582

+}

30583

Index: gcc/testsuite/gcc.dg/vmx/sn7153.c

30584

===================================================================

30585

--- a/src/gcc/testsuite/gcc.dg/vmx/sn7153.c (.../tags/gcc_4_8_2_release)

30586

+++ b/src/gcc/testsuite/gcc.dg/vmx/sn7153.c (.../branches/gcc-4_8-branch)

30587

@@ -34,7 +34,11 @@

30588

30589

void validate_sat()

30590

{

30591

+#ifdef __LITTLE_ENDIAN__

30592

+ if (vec_any_ne(vec_splat(vec_mfvscr(), 0), ((vector unsigned short){1,1,1,1,1,1,1,1})))

30593

+#else

30594

if (vec_any_ne(vec_splat(vec_mfvscr(), 7), ((vector unsigned short){1,1,1,1,1,1,1,1})))

30595

+#endif

30596

{

30597

union {vector unsigned short v; unsigned short s[8];} u;

30598

u.v = vec_mfvscr();

30599

Index: gcc/testsuite/gcc.dg/vmx/stl.c

30600

===================================================================

30601

--- a/src/gcc/testsuite/gcc.dg/vmx/stl.c (.../tags/gcc_4_8_2_release)

30602

+++ b/src/gcc/testsuite/gcc.dg/vmx/stl.c (.../branches/gcc-4_8-branch)

30603

@@ -0,0 +1,67 @@

30604

+#include "harness.h"

30605

+

30606

+static unsigned char svuc[16] __attribute__ ((aligned (16)));

30607

+static signed char svsc[16] __attribute__ ((aligned (16)));

30608

+static unsigned char svbc[16] __attribute__ ((aligned (16)));

30609

+static unsigned short svus[8] __attribute__ ((aligned (16)));

30610

+static signed short svss[8] __attribute__ ((aligned (16)));

30611

+static unsigned short svbs[8] __attribute__ ((aligned (16)));

30612

+static unsigned short svp[8] __attribute__ ((aligned (16)));

30613

+static unsigned int svui[4] __attribute__ ((aligned (16)));

30614

+static signed int svsi[4] __attribute__ ((aligned (16)));

30615

+static unsigned int svbi[4] __attribute__ ((aligned (16)));

30616

+static float svf[4] __attribute__ ((aligned (16)));

30617

+

30618

+static void check_arrays ()

30619

+{

30620

+ unsigned int i;

30621

+ for (i = 0; i < 16; ++i)

30622

+ {

30623

+ check (svuc[i] == i, "svuc");

30624

+ check (svsc[i] == i - 8, "svsc");

30625

+ check (svbc[i] == ((i % 2) ? 0xff : 0), "svbc");

30626

+ }

30627

+ for (i = 0; i < 8; ++i)

30628

+ {

30629

+ check (svus[i] == i, "svus");

30630

+ check (svss[i] == i - 4, "svss");

30631

+ check (svbs[i] == ((i % 2) ? 0xffff : 0), "svbs");

30632

+ check (svp[i] == i, "svp");

30633

+ }

30634

+ for (i = 0; i < 4; ++i)

30635

+ {

30636

+ check (svui[i] == i, "svui");

30637

+ check (svsi[i] == i - 2, "svsi");

30638

+ check (svbi[i] == ((i % 2) ? 0xffffffff : 0), "svbi");

30639

+ check (svf[i] == i * 1.0f, "svf");

30640

+ }

30641

+}

30642

+

30643

+static void test ()

30644

+{

30645

+ vector unsigned char vuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

30646

+ vector signed char vsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};

30647

+ vector bool char vbc = {0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255};

30648

+ vector unsigned short vus = {0,1,2,3,4,5,6,7};

30649

+ vector signed short vss = {-4,-3,-2,-1,0,1,2,3};

30650

+ vector bool short vbs = {0,65535,0,65535,0,65535,0,65535};

30651

+ vector pixel vp = {0,1,2,3,4,5,6,7};

30652

+ vector unsigned int vui = {0,1,2,3};

30653

+ vector signed int vsi = {-2,-1,0,1};

30654

+ vector bool int vbi = {0,0xffffffff,0,0xffffffff};

30655

+ vector float vf = {0.0,1.0,2.0,3.0};

30656

+

30657

+ vec_stl (vuc, 0, (vector unsigned char *)svuc);

30658

+ vec_stl (vsc, 0, (vector signed char *)svsc);

30659

+ vec_stl (vbc, 0, (vector bool char *)svbc);

30660

+ vec_stl (vus, 0, (vector unsigned short *)svus);

30661

+ vec_stl (vss, 0, (vector signed short *)svss);

30662

+ vec_stl (vbs, 0, (vector bool short *)svbs);

30663

+ vec_stl (vp, 0, (vector pixel *)svp);

30664

+ vec_stl (vui, 0, (vector unsigned int *)svui);

30665

+ vec_stl (vsi, 0, (vector signed int *)svsi);

30666

+ vec_stl (vbi, 0, (vector bool int *)svbi);

30667

+ vec_stl (vf, 0, (vector float *)svf);

30668

+

30669

+ check_arrays ();

30670

+}

30671

Index: gcc/testsuite/gcc.dg/vmx/st-vsx.c

30672

===================================================================

30673

--- a/src/gcc/testsuite/gcc.dg/vmx/st-vsx.c (.../tags/gcc_4_8_2_release)

30674

+++ b/src/gcc/testsuite/gcc.dg/vmx/st-vsx.c (.../branches/gcc-4_8-branch)

30675

@@ -0,0 +1,29 @@

30676

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

30677

+/* { dg-require-effective-target powerpc_vsx_ok } */

30678

+/* { dg-options "-maltivec -mabi=altivec -std=gnu99 -mvsx" } */

30679

+

30680

+#include "harness.h"

30681

+

30682

+static unsigned long long svul[2] __attribute__ ((aligned (16)));

30683

+static double svd[2] __attribute__ ((aligned (16)));

30684

+

30685

+static void check_arrays ()

30686

+{

30687

+ unsigned int i;

30688

+ for (i = 0; i < 2; ++i)

30689

+ {

30690

+ check (svul[i] == i, "svul");

30691

+ check (svd[i] == i * 1.0, "svd");

30692

+ }

30693

+}

30694

+

30695

+static void test ()

30696

+{

30697

+ vector unsigned long long vul = {0,1};

30698

+ vector double vd = {0.0,1.0};

30699

+

30700

+ vec_st (vul, 0, (vector unsigned long long *)svul);

30701

+ vec_st (vd, 0, (vector double *)svd);

30702

+

30703

+ check_arrays ();

30704

+}

30705

Index: gcc/testsuite/gcc.dg/vmx/sum2s.c

30706

===================================================================

30707

--- a/src/gcc/testsuite/gcc.dg/vmx/sum2s.c (.../tags/gcc_4_8_2_release)

30708

+++ b/src/gcc/testsuite/gcc.dg/vmx/sum2s.c (.../branches/gcc-4_8-branch)

30709

@@ -0,0 +1,13 @@

30710

+#include "harness.h"

30711

+

30712

+static void test()

30713

+{

30714

+ vector signed int vsia = {-10,1,2,3};

30715

+ vector signed int vsib = {100,101,102,-103};

30716

+ vector signed int vsir;

30717

+ vector signed int vsier = {0,92,0,-98};

30718

+

30719

+ vsir = vec_sum2s (vsia, vsib);

30720

+

30721

+ check (vec_all_eq (vsir, vsier), "vsir");

30722

+}

30723

Index: gcc/testsuite/gcc.dg/vmx/merge-vsx-be-order.c

30724

===================================================================

30725

--- a/src/gcc/testsuite/gcc.dg/vmx/merge-vsx-be-order.c (.../tags/gcc_4_8_2_release)

30726

+++ b/src/gcc/testsuite/gcc.dg/vmx/merge-vsx-be-order.c (.../branches/gcc-4_8-branch)

30727

@@ -0,0 +1,84 @@

30728

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

30729

+/* { dg-require-effective-target powerpc_vsx_ok } */

30730

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mvsx" } */

30731

+

30732

+#include "harness.h"

30733

+

30734

+static int vec_long_long_eq (vector long long x, vector long long y)

30735

+{

30736

+ return (x[0] == y[0] && x[1] == y[1]);

30737

+}

30738

+

30739

+static int vec_double_eq (vector double x, vector double y)

30740

+{

30741

+ return (x[0] == y[0] && x[1] == y[1]);

30742

+}

30743

+

30744

+static void test()

30745

+{

30746

+ /* Input vectors. */

30747

+ vector long long vla = {-2,-1};

30748

+ vector long long vlb = {0,1};

30749

+ vector double vda = {-2.0,-1.0};

30750

+ vector double vdb = {0.0,1.0};

30751

+ vector unsigned int vuia = {0,1,2,3};

30752

+ vector unsigned int vuib = {4,5,6,7};

30753

+ vector signed int vsia = {-4,-3,-2,-1};

30754

+ vector signed int vsib = {0,1,2,3};

30755

+ vector float vfa = {-4.0,-3.0,-2.0,-1.0};

30756

+ vector float vfb = {0.0,1.0,2.0,3.0};

30757

+

30758

+ /* Result vectors. */

30759

+ vector long long vlh, vll;

30760

+ vector double vdh, vdl;

30761

+ vector unsigned int vuih, vuil;

30762

+ vector signed int vsih, vsil;

30763

+ vector float vfh, vfl;

30764

+

30765

+ /* Expected result vectors. */

30766

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

30767

+ vector long long vlrh = {1,-1};

30768

+ vector long long vlrl = {0,-2};

30769

+ vector double vdrh = {1.0,-1.0};

30770

+ vector double vdrl = {0.0,-2.0};

30771

+ vector unsigned int vuirh = {6,2,7,3};

30772

+ vector unsigned int vuirl = {4,0,5,1};

30773

+ vector signed int vsirh = {2,-2,3,-1};

30774

+ vector signed int vsirl = {0,-4,1,-3};

30775

+ vector float vfrh = {2.0,-2.0,3.0,-1.0};

30776

+ vector float vfrl = {0.0,-4.0,1.0,-3.0};

30777

+#else

30778

+ vector long long vlrh = {-2,0};

30779

+ vector long long vlrl = {-1,1};

30780

+ vector double vdrh = {-2.0,0.0};

30781

+ vector double vdrl = {-1.0,1.0};

30782

+ vector unsigned int vuirh = {0,4,1,5};

30783

+ vector unsigned int vuirl = {2,6,3,7};

30784

+ vector signed int vsirh = {-4,0,-3,1};

30785

+ vector signed int vsirl = {-2,2,-1,3};

30786

+ vector float vfrh = {-4.0,0.0,-3.0,1.0};

30787

+ vector float vfrl = {-2.0,2.0,-1.0,3.0};

30788

+#endif

30789

+

30790

+ vlh = vec_mergeh (vla, vlb);

30791

+ vll = vec_mergel (vla, vlb);

30792

+ vdh = vec_mergeh (vda, vdb);

30793

+ vdl = vec_mergel (vda, vdb);

30794

+ vuih = vec_mergeh (vuia, vuib);

30795

+ vuil = vec_mergel (vuia, vuib);

30796

+ vsih = vec_mergeh (vsia, vsib);

30797

+ vsil = vec_mergel (vsia, vsib);

30798

+ vfh = vec_mergeh (vfa, vfb );

30799

+ vfl = vec_mergel (vfa, vfb );

30800

+

30801

+ check (vec_long_long_eq (vlh, vlrh), "vlh");

30802

+ check (vec_long_long_eq (vll, vlrl), "vll");

30803

+ check (vec_double_eq (vdh, vdrh), "vdh" );

30804

+ check (vec_double_eq (vdl, vdrl), "vdl" );

30805

+ check (vec_all_eq (vuih, vuirh), "vuih");

30806

+ check (vec_all_eq (vuil, vuirl), "vuil");

30807

+ check (vec_all_eq (vsih, vsirh), "vsih");

30808

+ check (vec_all_eq (vsil, vsirl), "vsil");

30809

+ check (vec_all_eq (vfh, vfrh), "vfh");

30810

+ check (vec_all_eq (vfl, vfrl), "vfl");

30811

+}

30812

Index: gcc/testsuite/gcc.dg/vmx/mult-even-odd-be-order.c

30813

===================================================================

30814

--- a/src/gcc/testsuite/gcc.dg/vmx/mult-even-odd-be-order.c (.../tags/gcc_4_8_2_release)

30815

+++ b/src/gcc/testsuite/gcc.dg/vmx/mult-even-odd-be-order.c (.../branches/gcc-4_8-branch)

30816

@@ -0,0 +1,64 @@

30817

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */

30818

+

30819

+#include "harness.h"

30820

+

30821

+static void test()

30822

+{

30823

+ vector unsigned char vuca = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

30824

+ vector unsigned char vucb = {2,3,2,3,2,3,2,3,2,3,2,3,2,3,2,3};

30825

+ vector signed char vsca = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};

30826

+ vector signed char vscb = {2,-3,2,-3,2,-3,2,-3,2,-3,2,-3,2,-3,2,-3};

30827

+ vector unsigned short vusa = {0,1,2,3,4,5,6,7};

30828

+ vector unsigned short vusb = {2,3,2,3,2,3,2,3};

30829

+ vector signed short vssa = {-4,-3,-2,-1,0,1,2,3};

30830

+ vector signed short vssb = {2,-3,2,-3,2,-3,2,-3};

30831

+ vector unsigned short vuse, vuso;

30832

+ vector signed short vsse, vsso;

30833

+ vector unsigned int vuie, vuio;

30834

+ vector signed int vsie, vsio;

30835

+

30836

+ vuse = vec_mule (vuca, vucb);

30837

+ vuso = vec_mulo (vuca, vucb);

30838

+ vsse = vec_mule (vsca, vscb);

30839

+ vsso = vec_mulo (vsca, vscb);

30840

+ vuie = vec_mule (vusa, vusb);

30841

+ vuio = vec_mulo (vusa, vusb);

30842

+ vsie = vec_mule (vssa, vssb);

30843

+ vsio = vec_mulo (vssa, vssb);

30844

+

30845

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

30846

+ check (vec_all_eq (vuse,

30847

+ ((vector unsigned short){3,9,15,21,27,33,39,45})),

30848

+ "vuse");

30849

+ check (vec_all_eq (vuso,

30850

+ ((vector unsigned short){0,4,8,12,16,20,24,28})),

30851

+ "vuso");

30852

+ check (vec_all_eq (vsse,

30853

+ ((vector signed short){21,15,9,3,-3,-9,-15,-21})),

30854

+ "vsse");

30855

+ check (vec_all_eq (vsso,

30856

+ ((vector signed short){-16,-12,-8,-4,0,4,8,12})),

30857

+ "vsso");

30858

+ check (vec_all_eq (vuie, ((vector unsigned int){3,9,15,21})), "vuie");

30859

+ check (vec_all_eq (vuio, ((vector unsigned int){0,4,8,12})), "vuio");

30860

+ check (vec_all_eq (vsie, ((vector signed int){9,3,-3,-9})), "vsie");

30861

+ check (vec_all_eq (vsio, ((vector signed int){-8,-4,0,4})), "vsio");

30862

+#else

30863

+ check (vec_all_eq (vuse,

30864

+ ((vector unsigned short){0,4,8,12,16,20,24,28})),

30865

+ "vuse");

30866

+ check (vec_all_eq (vuso,

30867

+ ((vector unsigned short){3,9,15,21,27,33,39,45})),

30868

+ "vuso");

30869

+ check (vec_all_eq (vsse,

30870

+ ((vector signed short){-16,-12,-8,-4,0,4,8,12})),

30871

+ "vsse");

30872

+ check (vec_all_eq (vsso,

30873

+ ((vector signed short){21,15,9,3,-3,-9,-15,-21})),

30874

+ "vsso");

30875

+ check (vec_all_eq (vuie, ((vector unsigned int){0,4,8,12})), "vuie");

30876

+ check (vec_all_eq (vuio, ((vector unsigned int){3,9,15,21})), "vuio");

30877

+ check (vec_all_eq (vsie, ((vector signed int){-8,-4,0,4})), "vsie");

30878

+ check (vec_all_eq (vsio, ((vector signed int){9,3,-3,-9})), "vsio");

30879

+#endif

30880

+}

30881

Index: gcc/testsuite/gcc.dg/vmx/insert-vsx.c

30882

===================================================================

30883

--- a/src/gcc/testsuite/gcc.dg/vmx/insert-vsx.c (.../tags/gcc_4_8_2_release)

30884

+++ b/src/gcc/testsuite/gcc.dg/vmx/insert-vsx.c (.../branches/gcc-4_8-branch)

30885

@@ -0,0 +1,28 @@

30886

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

30887

+/* { dg-require-effective-target powerpc_vsx_ok } */

30888

+/* { dg-options "-maltivec -mabi=altivec -std=gnu99 -mvsx" } */

30889

+

30890

+#include "harness.h"

30891

+

30892

+static int vec_long_long_eq (vector long long x, vector long long y)

30893

+{

30894

+ return (x[0] == y[0] && x[1] == y[1]);

30895

+}

30896

+

30897

+static int vec_dbl_eq (vector double x, vector double y)

30898

+{

30899

+ return (x[0] == y[0] && x[1] == y[1]);

30900

+}

30901

+

30902

+static void test()

30903

+{

30904

+ vector long long vl = {0, 1};

30905

+ vector double vd = {0.0, 1.0};

30906

+ vector long long vlr = vec_insert (2, vl, 0);

30907

+ vector double vdr = vec_insert (2.0, vd, 1);

30908

+ vector long long vler = {2, 1};

30909

+ vector double vder = {0.0, 2.0};

30910

+

30911

+ check (vec_long_long_eq (vlr, vler), "vl");

30912

+ check (vec_dbl_eq (vdr, vder), "vd");

30913

+}

30914

Index: gcc/testsuite/gcc.dg/vmx/vsums-be-order.c

30915

===================================================================

30916

--- a/src/gcc/testsuite/gcc.dg/vmx/vsums-be-order.c (.../tags/gcc_4_8_2_release)

30917

+++ b/src/gcc/testsuite/gcc.dg/vmx/vsums-be-order.c (.../branches/gcc-4_8-branch)

30918

@@ -0,0 +1,20 @@

30919

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */

30920

+

30921

+#include "harness.h"

30922

+

30923

+static void test()

30924

+{

30925

+ vector signed int va = {-7,11,-13,17};

30926

+

30927

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

30928

+ vector signed int vb = {128,0,0,0};

30929

+ vector signed int evd = {136,0,0,0};

30930

+#else

30931

+ vector signed int vb = {0,0,0,128};

30932

+ vector signed int evd = {0,0,0,136};

30933

+#endif

30934

+

30935

+ vector signed int vd = vec_sums (va, vb);

30936

+

30937

+ check (vec_all_eq (vd, evd), "sums");

30938

+}

30939

Index: gcc/testsuite/gcc.dg/vmx/ldl-vsx.c

30940

===================================================================

30941

--- a/src/gcc/testsuite/gcc.dg/vmx/ldl-vsx.c (.../tags/gcc_4_8_2_release)

30942

+++ b/src/gcc/testsuite/gcc.dg/vmx/ldl-vsx.c (.../branches/gcc-4_8-branch)

30943

@@ -0,0 +1,39 @@

30944

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

30945

+/* { dg-require-effective-target powerpc_vsx_ok } */

30946

+/* { dg-options "-maltivec -mabi=altivec -std=gnu99 -mvsx" } */

30947

+

30948

+#include "harness.h"

30949

+

30950

+static unsigned long long svul[2] __attribute__ ((aligned (16)));

30951

+static double svd[2] __attribute__ ((aligned (16)));

30952

+

30953

+static void init ()

30954

+{

30955

+ unsigned int i;

30956

+ for (i = 0; i < 2; ++i)

30957

+ {

30958

+ svul[i] = i;

30959

+ svd[i] = i * 1.0;

30960

+ }

30961

+}

30962

+

30963

+static void test ()

30964

+{

30965

+ vector unsigned long long evul = {0,1};

30966

+ vector double evd = {0.0,1.0};

30967

+

30968

+ vector unsigned long long vul;

30969

+ vector double vd;

30970

+ unsigned i;

30971

+

30972

+ init ();

30973

+

30974

+ vul = vec_ldl (0, (vector unsigned long long *)svul);

30975

+ vd = vec_ldl (0, (vector double *)svd);

30976

+

30977

+ for (i = 0; i < 2; ++i)

30978

+ {

30979

+ check (vul[i] == evul[i], "vul");

30980

+ check (vd[i] == evd[i], "vd" );

30981

+ }

30982

+}

30983

Index: gcc/testsuite/gcc.dg/vmx/ste.c

30984

===================================================================

30985

--- a/src/gcc/testsuite/gcc.dg/vmx/ste.c (.../tags/gcc_4_8_2_release)

30986

+++ b/src/gcc/testsuite/gcc.dg/vmx/ste.c (.../branches/gcc-4_8-branch)

30987

@@ -0,0 +1,41 @@

30988

+#include "harness.h"

30989

+

30990

+static unsigned char svuc[16] __attribute__ ((aligned (16)));

30991

+static signed char svsc[16] __attribute__ ((aligned (16)));

30992

+static unsigned short svus[8] __attribute__ ((aligned (16)));

30993

+static signed short svss[8] __attribute__ ((aligned (16)));

30994

+static unsigned int svui[4] __attribute__ ((aligned (16)));

30995

+static signed int svsi[4] __attribute__ ((aligned (16)));

30996

+static float svf[4] __attribute__ ((aligned (16)));

30997

+

30998

+static void check_arrays ()

30999

+{

31000

+ check (svuc[9] == 9, "svuc");

31001

+ check (svsc[14] == 6, "svsc");

31002

+ check (svus[7] == 7, "svus");

31003

+ check (svss[1] == -3, "svss");

31004

+ check (svui[3] == 3, "svui");

31005

+ check (svsi[2] == 0, "svsi");

31006

+ check (svf[0] == 0.0, "svf");

31007

+}

31008

+

31009

+static void test ()

31010

+{

31011

+ vector unsigned char vuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

31012

+ vector signed char vsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};

31013

+ vector unsigned short vus = {0,1,2,3,4,5,6,7};

31014

+ vector signed short vss = {-4,-3,-2,-1,0,1,2,3};

31015

+ vector unsigned int vui = {0,1,2,3};

31016

+ vector signed int vsi = {-2,-1,0,1};

31017

+ vector float vf = {0.0,1.0,2.0,3.0};

31018

+

31019

+ vec_ste (vuc, 9*1, (unsigned char *)svuc);

31020

+ vec_ste (vsc, 14*1, (signed char *)svsc);

31021

+ vec_ste (vus, 7*2, (unsigned short *)svus);

31022

+ vec_ste (vss, 1*2, (signed short *)svss);

31023

+ vec_ste (vui, 3*4, (unsigned int *)svui);

31024

+ vec_ste (vsi, 2*4, (signed int *)svsi);

31025

+ vec_ste (vf, 0*4, (float *)svf);

31026

+

31027

+ check_arrays ();

31028

+}

31029

Index: gcc/testsuite/gcc.dg/vmx/lde-be-order.c

31030

===================================================================

31031

--- a/src/gcc/testsuite/gcc.dg/vmx/lde-be-order.c (.../tags/gcc_4_8_2_release)

31032

+++ b/src/gcc/testsuite/gcc.dg/vmx/lde-be-order.c (.../branches/gcc-4_8-branch)

31033

@@ -0,0 +1,73 @@

31034

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */

31035

+

31036

+#include "harness.h"

31037

+

31038

+static unsigned char svuc[16] __attribute__ ((aligned (16)));

31039

+static signed char svsc[16] __attribute__ ((aligned (16)));

31040

+static unsigned short svus[8] __attribute__ ((aligned (16)));

31041

+static signed short svss[8] __attribute__ ((aligned (16)));

31042

+static unsigned int svui[4] __attribute__ ((aligned (16)));

31043

+static signed int svsi[4] __attribute__ ((aligned (16)));

31044

+static float svf[4] __attribute__ ((aligned (16)));

31045

+

31046

+static void init ()

31047

+{

31048

+ int i;

31049

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

31050

+ for (i = 15; i >= 0; --i)

31051

+#else

31052

+ for (i = 0; i < 16; ++i)

31053

+#endif

31054

+ {

31055

+ svuc[i] = i;

31056

+ svsc[i] = i - 8;

31057

+ }

31058

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

31059

+ for (i = 7; i >= 0; --i)

31060

+#else

31061

+ for (i = 0; i < 8; ++i)

31062

+#endif

31063

+ {

31064

+ svus[i] = i;

31065

+ svss[i] = i - 4;

31066

+ }

31067

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

31068

+ for (i = 3; i >= 0; --i)

31069

+#else

31070

+ for (i = 0; i < 4; ++i)

31071

+#endif

31072

+ {

31073

+ svui[i] = i;

31074

+ svsi[i] = i - 2;

31075

+ svf[i] = i * 1.0f;

31076

+ }

31077

+}

31078

+

31079

+static void test ()

31080

+{

31081

+ vector unsigned char vuc;

31082

+ vector signed char vsc;

31083

+ vector unsigned short vus;

31084

+ vector signed short vss;

31085

+ vector unsigned int vui;

31086

+ vector signed int vsi;

31087

+ vector float vf;

31088

+

31089

+ init ();

31090

+

31091

+ vuc = vec_lde (9*1, (unsigned char *)svuc);

31092

+ vsc = vec_lde (14*1, (signed char *)svsc);

31093

+ vus = vec_lde (7*2, (unsigned short *)svus);

31094

+ vss = vec_lde (1*2, (signed short *)svss);

31095

+ vui = vec_lde (3*4, (unsigned int *)svui);

31096

+ vsi = vec_lde (2*4, (signed int *)svsi);

31097

+ vf = vec_lde (0*4, (float *)svf);

31098

+

31099

+ check (vec_extract (vuc, 9) == 9, "vuc");

31100

+ check (vec_extract (vsc, 14) == 6, "vsc");

31101

+ check (vec_extract (vus, 7) == 7, "vus");

31102

+ check (vec_extract (vss, 1) == -3, "vss");

31103

+ check (vec_extract (vui, 3) == 3, "vui");

31104

+ check (vec_extract (vsi, 2) == 0, "vsi");

31105

+ check (vec_extract (vf, 0) == 0.0, "vf");

31106

+}

31107

Index: gcc/testsuite/gcc.dg/vmx/splat-vsx.c

31108

===================================================================

31109

--- a/src/gcc/testsuite/gcc.dg/vmx/splat-vsx.c (.../tags/gcc_4_8_2_release)

31110

+++ b/src/gcc/testsuite/gcc.dg/vmx/splat-vsx.c (.../branches/gcc-4_8-branch)

31111

@@ -0,0 +1,31 @@

31112

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

31113

+/* { dg-require-effective-target powerpc_vsx_ok } */

31114

+/* { dg-options "-maltivec -mabi=altivec -std=gnu99 -mvsx" } */

31115

+

31116

+#include "harness.h"

31117

+

31118

+static void test()

31119

+{

31120

+ /* Input vectors. */

31121

+ vector unsigned int vui = {0,1,2,3};

31122

+ vector signed int vsi = {-2,-1,0,1};

31123

+ vector float vf = {-2.0,-1.0,0.0,1.0};

31124

+

31125

+ /* Result vectors. */

31126

+ vector unsigned int vuir;

31127

+ vector signed int vsir;

31128

+ vector float vfr;

31129

+

31130

+ /* Expected result vectors. */

31131

+ vector unsigned int vuier = {2,2,2,2};

31132

+ vector signed int vsier = {1,1,1,1};

31133

+ vector float vfer = {-1.0,-1.0,-1.0,-1.0};

31134

+

31135

+ vuir = vec_splat (vui, 2);

31136

+ vsir = vec_splat (vsi, 3);

31137

+ vfr = vec_splat (vf, 1);

31138

+

31139

+ check (vec_all_eq (vuir, vuier), "vui");

31140

+ check (vec_all_eq (vsir, vsier), "vsi");

31141

+ check (vec_all_eq (vfr, vfer ), "vf");

31142

+}

31143

Index: gcc/testsuite/gcc.dg/vmx/sum2s-be-order.c

31144

===================================================================

31145

--- a/src/gcc/testsuite/gcc.dg/vmx/sum2s-be-order.c (.../tags/gcc_4_8_2_release)

31146

+++ b/src/gcc/testsuite/gcc.dg/vmx/sum2s-be-order.c (.../branches/gcc-4_8-branch)

31147

@@ -0,0 +1,19 @@

31148

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */

31149

+

31150

+#include "harness.h"

31151

+

31152

+static void test()

31153

+{

31154

+ vector signed int vsia = {-10,1,2,3};

31155

+ vector signed int vsib = {100,101,102,-103};

31156

+ vector signed int vsir;

31157

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

31158

+ vector signed int vsier = {91,0,107,0};

31159

+#else

31160

+ vector signed int vsier = {0,92,0,-98};

31161

+#endif

31162

+

31163

+ vsir = vec_sum2s (vsia, vsib);

31164

+

31165

+ check (vec_all_eq (vsir, vsier), "vsir");

31166

+}

31167

Index: gcc/testsuite/gcc.dg/vmx/merge-vsx.c

31168

===================================================================

31169

--- a/src/gcc/testsuite/gcc.dg/vmx/merge-vsx.c (.../tags/gcc_4_8_2_release)

31170

+++ b/src/gcc/testsuite/gcc.dg/vmx/merge-vsx.c (.../branches/gcc-4_8-branch)

31171

@@ -0,0 +1,71 @@

31172

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

31173

+/* { dg-require-effective-target powerpc_vsx_ok } */

31174

+/* { dg-options "-maltivec -mabi=altivec -std=gnu99 -mvsx" } */

31175

+

31176

+#include "harness.h"

31177

+

31178

+static int vec_long_long_eq (vector long long x, vector long long y)

31179

+{

31180

+ return (x[0] == y[0] && x[1] == y[1]);

31181

+}

31182

+

31183

+static int vec_double_eq (vector double x, vector double y)

31184

+{

31185

+ return (x[0] == y[0] && x[1] == y[1]);

31186

+}

31187

+

31188

+static void test()

31189

+{

31190

+ /* Input vectors. */

31191

+ vector long long vla = {-2,-1};

31192

+ vector long long vlb = {0,1};

31193

+ vector double vda = {-2.0,-1.0};

31194

+ vector double vdb = {0.0,1.0};

31195

+ vector unsigned int vuia = {0,1,2,3};

31196

+ vector unsigned int vuib = {4,5,6,7};

31197

+ vector signed int vsia = {-4,-3,-2,-1};

31198

+ vector signed int vsib = {0,1,2,3};

31199

+ vector float vfa = {-4.0,-3.0,-2.0,-1.0};

31200

+ vector float vfb = {0.0,1.0,2.0,3.0};

31201

+

31202

+ /* Result vectors. */

31203

+ vector long long vlh, vll;

31204

+ vector double vdh, vdl;

31205

+ vector unsigned int vuih, vuil;

31206

+ vector signed int vsih, vsil;

31207

+ vector float vfh, vfl;

31208

+

31209

+ /* Expected result vectors. */

31210

+ vector long long vlrh = {-2,0};

31211

+ vector long long vlrl = {-1,1};

31212

+ vector double vdrh = {-2.0,0.0};

31213

+ vector double vdrl = {-1.0,1.0};

31214

+ vector unsigned int vuirh = {0,4,1,5};

31215

+ vector unsigned int vuirl = {2,6,3,7};

31216

+ vector signed int vsirh = {-4,0,-3,1};

31217

+ vector signed int vsirl = {-2,2,-1,3};

31218

+ vector float vfrh = {-4.0,0.0,-3.0,1.0};

31219

+ vector float vfrl = {-2.0,2.0,-1.0,3.0};

31220

+

31221

+ vlh = vec_mergeh (vla, vlb);

31222

+ vll = vec_mergel (vla, vlb);

31223

+ vdh = vec_mergeh (vda, vdb);

31224

+ vdl = vec_mergel (vda, vdb);

31225

+ vuih = vec_mergeh (vuia, vuib);

31226

+ vuil = vec_mergel (vuia, vuib);

31227

+ vsih = vec_mergeh (vsia, vsib);

31228

+ vsil = vec_mergel (vsia, vsib);

31229

+ vfh = vec_mergeh (vfa, vfb );

31230

+ vfl = vec_mergel (vfa, vfb );

31231

+

31232

+ check (vec_long_long_eq (vlh, vlrh), "vlh");

31233

+ check (vec_long_long_eq (vll, vlrl), "vll");

31234

+ check (vec_double_eq (vdh, vdrh), "vdh" );

31235

+ check (vec_double_eq (vdl, vdrl), "vdl" );

31236

+ check (vec_all_eq (vuih, vuirh), "vuih");

31237

+ check (vec_all_eq (vuil, vuirl), "vuil");

31238

+ check (vec_all_eq (vsih, vsirh), "vsih");

31239

+ check (vec_all_eq (vsil, vsirl), "vsil");

31240

+ check (vec_all_eq (vfh, vfrh), "vfh");

31241

+ check (vec_all_eq (vfl, vfrl), "vfl");

31242

+}

31243

Index: gcc/testsuite/gcc.dg/vmx/stl-vsx.c

31244

===================================================================

31245

--- a/src/gcc/testsuite/gcc.dg/vmx/stl-vsx.c (.../tags/gcc_4_8_2_release)

31246

+++ b/src/gcc/testsuite/gcc.dg/vmx/stl-vsx.c (.../branches/gcc-4_8-branch)

31247

@@ -0,0 +1,29 @@

31248

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

31249

+/* { dg-require-effective-target powerpc_vsx_ok } */

31250

+/* { dg-options "-maltivec -mabi=altivec -std=gnu99 -mvsx" } */

31251

+

31252

+#include "harness.h"

31253

+

31254

+static unsigned long long svul[2] __attribute__ ((aligned (16)));

31255

+static double svd[2] __attribute__ ((aligned (16)));

31256

+

31257

+static void check_arrays ()

31258

+{

31259

+ unsigned int i;

31260

+ for (i = 0; i < 2; ++i)

31261

+ {

31262

+ check (svul[i] == i, "svul");

31263

+ check (svd[i] == i * 1.0, "svd");

31264

+ }

31265

+}

31266

+

31267

+static void test ()

31268

+{

31269

+ vector unsigned long long vul = {0,1};

31270

+ vector double vd = {0.0,1.0};

31271

+

31272

+ vec_stl (vul, 0, (vector unsigned long long *)svul);

31273

+ vec_stl (vd, 0, (vector double *)svd);

31274

+

31275

+ check_arrays ();

31276

+}

31277

Index: gcc/testsuite/gcc.dg/strlenopt-4gf.c

31278

===================================================================

31279

--- a/src/gcc/testsuite/gcc.dg/strlenopt-4gf.c (.../tags/gcc_4_8_2_release)

31280

+++ b/src/gcc/testsuite/gcc.dg/strlenopt-4gf.c (.../branches/gcc-4_8-branch)

31281

@@ -7,13 +7,13 @@

31282

#include "strlenopt-4.c"

31283

31284

/* { dg-final { scan-tree-dump-times "strlen \\(" 1 "strlen" } } */

31285

-/* { dg-final { scan-tree-dump-times "__memcpy_chk \\(" 4 "strlen" } } */

31286

-/* { dg-final { scan-tree-dump-times "__strcpy_chk \\(" 1 "strlen" } } */

31287

+/* { dg-final { scan-tree-dump-times "__memcpy_chk \\(" 0 "strlen" } } */

31288

+/* { dg-final { scan-tree-dump-times "__strcpy_chk \\(" 0 "strlen" } } */

31289

/* { dg-final { scan-tree-dump-times "__strcat_chk \\(" 0 "strlen" } } */

31290

/* { dg-final { scan-tree-dump-times "strchr \\(" 0 "strlen" } } */

31291

-/* { dg-final { scan-tree-dump-times "__stpcpy_chk \\(" 5 "strlen" } } */

31292

-/* { dg-final { scan-tree-dump-times "memcpy \\(" 0 "strlen" } } */

31293

-/* { dg-final { scan-tree-dump-times "strcpy \\(" 0 "strlen" } } */

31294

+/* { dg-final { scan-tree-dump-times "__stpcpy_chk \\(" 0 "strlen" } } */

31295

+/* { dg-final { scan-tree-dump-times "memcpy \\(" 4 "strlen" } } */

31296

+/* { dg-final { scan-tree-dump-times "strcpy \\(" 1 "strlen" } } */

31297

/* { dg-final { scan-tree-dump-times "strcat \\(" 0 "strlen" } } */

31298

-/* { dg-final { scan-tree-dump-times "stpcpy \\(" 0 "strlen" } } */

31299

+/* { dg-final { scan-tree-dump-times "stpcpy \\(" 5 "strlen" } } */

31300

/* { dg-final { cleanup-tree-dump "strlen" } } */

31301

Index: gcc/testsuite/gcc.dg/pr59351.c

31302

===================================================================

31303

--- a/src/gcc/testsuite/gcc.dg/pr59351.c (.../tags/gcc_4_8_2_release)

31304

+++ b/src/gcc/testsuite/gcc.dg/pr59351.c (.../branches/gcc-4_8-branch)

31305

@@ -0,0 +1,8 @@

31306

+/* { dg-do compile } */

31307

+/* { dg-options "-std=c99 -Wpedantic" } */

31308

+

31309

+unsigned int

31310

+foo (void)

31311

+{

31312

+ return sizeof ((int[]) {}); /* { dg-warning "ISO C forbids empty initializer braces" } */

31313

+}

31314

Index: gcc/testsuite/gcc.dg/debug/dwarf2/dwarf2-macro2.c

31315

===================================================================

31316

--- a/src/gcc/testsuite/gcc.dg/debug/dwarf2/dwarf2-macro2.c (.../tags/gcc_4_8_2_release)

31317

+++ b/src/gcc/testsuite/gcc.dg/debug/dwarf2/dwarf2-macro2.c (.../branches/gcc-4_8-branch)

31318

@@ -0,0 +1,7 @@

31319

+/* Test to make sure the macro info includes the predefined macros with line number 0. */

31320

+/* { dg-do compile } */

31321

+/* { dg-options "-g3 -gdwarf-2 -dA -fverbose-asm" } */

31322

+/* { dg-final { scan-assembler "At line number 0" } } */

31323

+

31324

+#define FOO 1

31325

+int i;

31326

Index: gcc/testsuite/gcc.dg/Wstrict-aliasing-bogus-ref-all-2.c

31327

===================================================================

31328

--- a/src/gcc/testsuite/gcc.dg/Wstrict-aliasing-bogus-ref-all-2.c (.../tags/gcc_4_8_2_release)

31329

+++ b/src/gcc/testsuite/gcc.dg/Wstrict-aliasing-bogus-ref-all-2.c (.../branches/gcc-4_8-branch)

31330

@@ -1,6 +1,7 @@

31331

/* { dg-do compile } */

31332

/* { dg-options "-O2 -Wall" } */

31333

/* { dg-options "-O2 -Wall -mabi=altivec" { target { { powerpc*-*-linux* } && ilp32 } } } */

31334

+/* { dg-options "-O2 -Wall -msse2" { target { i?86-*-* x86_64-*-* } } } */

31335

31336

typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));

31337

31338

Index: gcc/testsuite/gcc.dg/builtin-object-size-8.c

31339

===================================================================

31340

--- a/src/gcc/testsuite/gcc.dg/builtin-object-size-8.c (.../tags/gcc_4_8_2_release)

31341

+++ b/src/gcc/testsuite/gcc.dg/builtin-object-size-8.c (.../branches/gcc-4_8-branch)

31342

@@ -1,4 +1,4 @@

31343

-/* { dg-do run { xfail *-*-* } } */

31344

+/* { dg-do run } */

31345

/* { dg-options "-O2" } */

31346

31347

typedef __SIZE_TYPE__ size_t;

31348

Index: gcc/testsuite/gcc.dg/20050922-2.c

31349

===================================================================

31350

--- a/src/gcc/testsuite/gcc.dg/20050922-2.c (.../tags/gcc_4_8_2_release)

31351

+++ b/src/gcc/testsuite/gcc.dg/20050922-2.c (.../branches/gcc-4_8-branch)

31352

@@ -4,7 +4,8 @@

31353

/* { dg-do run } */

31354

/* { dg-options "-O1 -std=c99" } */

31355

31356

-#include <stdlib.h>

31357

+extern void abort (void);

31358

+extern void exit (int);

31359

31360

#if __INT_MAX__ == 2147483647

31361

typedef unsigned int uint32_t;

31362

Index: gcc/testsuite/gcc.dg/graphite/pr55022.c

31363

===================================================================

31364

--- a/src/gcc/testsuite/gcc.dg/graphite/pr55022.c (.../tags/gcc_4_8_2_release)

31365

+++ b/src/gcc/testsuite/gcc.dg/graphite/pr55022.c (.../branches/gcc-4_8-branch)

31366

@@ -0,0 +1,27 @@

31367

+/* { dg-do run } */

31368

+/* { dg-options "-O2 -fgraphite-identity" } */

31369

+

31370

+extern void abort (void);

31371

+

31372

+void __attribute__((noinline,noclone))

31373

+f(int *limit, int minLen, int maxLen)

31374

+{

31375

+ int i;

31376

+

31377

+ for (i = minLen; i <= maxLen; i++) {

31378

+ limit[i] = i;

31379

+ }

31380

+}

31381

+

31382

+int main()

31383

+{

31384

+ int limit[256], i;

31385

+ f (limit, 0, 255);

31386

+ for (i = 0; i < 256; ++i)

31387

+ {

31388

+ if (limit[i] != i)

31389

+ abort ();

31390

+ __asm__ volatile ("" : : : "memory");

31391

+ }

31392

+ return 0;

31393

+}

31394

Index: gcc/testsuite/gcc.dg/graphite/pr59817-2.c

31395

===================================================================

31396

--- a/src/gcc/testsuite/gcc.dg/graphite/pr59817-2.c (.../tags/gcc_4_8_2_release)

31397

+++ b/src/gcc/testsuite/gcc.dg/graphite/pr59817-2.c (.../branches/gcc-4_8-branch)

31398

@@ -0,0 +1,15 @@

31399

+/* { dg-do compile } */

31400

+/* { dg-options "-O2 -floop-interchange" } */

31401

+

31402

+void

31403

+xl(void)

31404

+{

31405

+ static int j3;

31406

+ for (j3 = 0; j3 < 1; ++j3) {

31407

+ static int f2;

31408

+ static int w7;

31409

+ short int b5;

31410

+ int ok;

31411

+ f2 = (b5 += ok) ? (w7 = 0): (w7 ? 0 : (f2 = ok));

31412

+ }

31413

+}

31414

Index: gcc/testsuite/gcc.dg/graphite/pr60740.c

31415

===================================================================

31416

--- a/src/gcc/testsuite/gcc.dg/graphite/pr60740.c (.../tags/gcc_4_8_2_release)

31417

+++ b/src/gcc/testsuite/gcc.dg/graphite/pr60740.c (.../branches/gcc-4_8-branch)

31418

@@ -0,0 +1,16 @@

31419

+/* { dg-options "-O2 -floop-interchange" } */

31420

+

31421

+int **db6 = 0;

31422

+

31423

+void

31424

+k26(void)

31425

+{

31426

+ static int geb = 0;

31427

+ int *a22 = &geb;

31428

+ int **l30 = &a22;

31429

+ int *c4b;

31430

+ int ndf;

31431

+ for (ndf = 0; ndf <= 1; ++ndf)

31432

+ *c4b = (db6 == l30) && (*a22)--;

31433

+}

31434

+

31435

Index: gcc/testsuite/gcc.dg/graphite/pr59817-1.c

31436

===================================================================

31437

--- a/src/gcc/testsuite/gcc.dg/graphite/pr59817-1.c (.../tags/gcc_4_8_2_release)

31438

+++ b/src/gcc/testsuite/gcc.dg/graphite/pr59817-1.c (.../branches/gcc-4_8-branch)

31439

@@ -0,0 +1,16 @@

31440

+/* { dg-do compile } */

31441

+/* { dg-options "-O2 -floop-interchange" } */

31442

+

31443

+int kd;

31444

+

31445

+void

31446

+n2(void)

31447

+{

31448

+ static int so;

31449

+ static short int i5;

31450

+ int wj;

31451

+ int *il;

31452

+ int *nk = &so;

31453

+ for (wj = 0; wj < 2; ++wj)

31454

+ *nk = ((i5 += *il) || kd );

31455

+}

31456

Index: gcc/testsuite/gcc.dg/pr59860.c

31457

===================================================================

31458

--- a/src/gcc/testsuite/gcc.dg/pr59860.c (.../tags/gcc_4_8_2_release)

31459

+++ b/src/gcc/testsuite/gcc.dg/pr59860.c (.../branches/gcc-4_8-branch)

31460

@@ -0,0 +1,15 @@

31461

+/* { dg-do compile } */

31462

+/* { dg-options "-O" } */

31463

+

31464

+extern __inline __attribute__ ((__always_inline__)) __attribute__ ((__gnu_inline__)) __attribute__ ((__artificial__)) char * __attribute__ ((__nothrow__ , __leaf__))

31465

+strcat (char *__restrict __dest, const char *__restrict __src)

31466

+{

31467

+ return __builtin___strcat_chk (__dest, __src, __builtin_object_size (__dest, 2 > 1));

31468

+}

31469

+static char raw_decode;

31470

+void foo (char **argv, char *outfilename)

31471

+{

31472

+ if (**argv == 'r')

31473

+ raw_decode = 1;

31474

+ strcat (outfilename, raw_decode ? ".raw" : ".wav");

31475

+}

31476

Index: gcc/testsuite/gcc.dg/stack-usage-1.c

31477

===================================================================

31478

--- a/src/gcc/testsuite/gcc.dg/stack-usage-1.c (.../tags/gcc_4_8_2_release)

31479

+++ b/src/gcc/testsuite/gcc.dg/stack-usage-1.c (.../branches/gcc-4_8-branch)

31480

@@ -38,7 +38,11 @@

31481

# endif

31482

#elif defined (__powerpc64__) || defined (__ppc64__) || defined (__POWERPC64__) \

31483

|| defined (__PPC64__)

31484

-# define SIZE 180

31485

+# if _CALL_ELF == 2

31486

+# define SIZE 208

31487

+# else

31488

+# define SIZE 180

31489

+# endif

31490

#elif defined (__powerpc__) || defined (__PPC__) || defined (__ppc__) \

31491

|| defined (__POWERPC__) || defined (PPC) || defined (_IBMR2)

31492

# if defined (__ALTIVEC__)

31493

Index: gcc/testsuite/gcc.dg/pr59011.c

31494

===================================================================

31495

--- a/src/gcc/testsuite/gcc.dg/pr59011.c (.../tags/gcc_4_8_2_release)

31496

+++ b/src/gcc/testsuite/gcc.dg/pr59011.c (.../branches/gcc-4_8-branch)

31497

@@ -0,0 +1,22 @@

31498

+/* PR middle-end/59011 */

31499

+/* { dg-do compile } */

31500

+/* { dg-options "-std=gnu99" } */

31501

+

31502

+void

31503

+foo (int m)

31504

+{

31505

+ int a[m];

31506

+ void

31507

+ bar (void)

31508

+ {

31509

+ {

31510

+ int

31511

+ baz (void)

31512

+ {

31513

+ return a[0];

31514

+ }

31515

+ }

31516

+ a[0] = 42;

31517

+ }

31518

+ bar ();

31519

+}

31520

Index: gcc/testsuite/gcc.dg/pr58805.c

31521

===================================================================

31522

--- a/src/gcc/testsuite/gcc.dg/pr58805.c (.../tags/gcc_4_8_2_release)

31523

+++ b/src/gcc/testsuite/gcc.dg/pr58805.c (.../branches/gcc-4_8-branch)

31524

@@ -0,0 +1,24 @@

31525

+/* { dg-do compile } */

31526

+/* { dg-options "-O2 -ftree-tail-merge -fdump-tree-pre" } */

31527

+

31528

+/* Type that matches the 'p' constraint. */

31529

+#define TYPE void *

31530

+

31531

+static inline

31532

+void bar (TYPE *r)

31533

+{

31534

+ TYPE t;

31535

+ __asm__ ("" : "=&p" (t), "=p" (*r));

31536

+}

31537

+

31538

+void

31539

+foo (int n, TYPE *x, TYPE *y)

31540

+{

31541

+ if (n == 0)

31542

+ bar (x);

31543

+ else

31544

+ bar (y);

31545

+}

31546

+

31547

+/* { dg-final { scan-tree-dump-times "__asm__" 2 "pre"} } */

31548

+/* { dg-final { cleanup-tree-dump "pre" } } */

31549

Index: gcc/testsuite/gcc.dg/strlenopt-14gf.c

31550

===================================================================

31551

--- a/src/gcc/testsuite/gcc.dg/strlenopt-14gf.c (.../tags/gcc_4_8_2_release)

31552

+++ b/src/gcc/testsuite/gcc.dg/strlenopt-14gf.c (.../branches/gcc-4_8-branch)

31553

@@ -11,14 +11,14 @@

31554

memcpy. */

31555

/* { dg-final { scan-tree-dump-times "strlen \\(" 4 "strlen" } } */

31556

/* { dg-final { scan-tree-dump-times "__memcpy_chk \\(" 0 "strlen" } } */

31557

-/* { dg-final { scan-tree-dump-times "__mempcpy_chk \\(" 2 "strlen" } } */

31558

+/* { dg-final { scan-tree-dump-times "__mempcpy_chk \\(" 0 "strlen" } } */

31559

/* { dg-final { scan-tree-dump-times "__strcpy_chk \\(" 0 "strlen" } } */

31560

/* { dg-final { scan-tree-dump-times "__strcat_chk \\(" 0 "strlen" } } */

31561

/* { dg-final { scan-tree-dump-times "strchr \\(" 0 "strlen" } } */

31562

-/* { dg-final { scan-tree-dump-times "__stpcpy_chk \\(" 3 "strlen" } } */

31563

-/* { dg-final { scan-tree-dump-times "memcpy \\(" 0 "strlen" } } */

31564

-/* { dg-final { scan-tree-dump-times "mempcpy \\(" 0 "strlen" } } */

31565

+/* { dg-final { scan-tree-dump-times "__stpcpy_chk \\(" 0 "strlen" } } */

31566

+/* { dg-final { scan-tree-dump-times "memcpy \\(" 1 "strlen" } } */

31567

+/* { dg-final { scan-tree-dump-times "mempcpy \\(" 2 "strlen" } } */

31568

/* { dg-final { scan-tree-dump-times "strcpy \\(" 0 "strlen" } } */

31569

/* { dg-final { scan-tree-dump-times "strcat \\(" 0 "strlen" } } */

31570

-/* { dg-final { scan-tree-dump-times "stpcpy \\(" 0 "strlen" } } */

31571

+/* { dg-final { scan-tree-dump-times "stpcpy \\(" 2 "strlen" } } */

31572

/* { dg-final { cleanup-tree-dump "strlen" } } */

31573

Index: gcc/testsuite/gcc.dg/torture/pr57425-2.c

31574

===================================================================

31575

--- a/src/gcc/testsuite/gcc.dg/torture/pr57425-2.c (.../tags/gcc_4_8_2_release)

31576

+++ b/src/gcc/testsuite/gcc.dg/torture/pr57425-2.c (.../branches/gcc-4_8-branch)

31577

@@ -0,0 +1,31 @@

31578

+/* { dg-do run } */

31579

+

31580

+extern void abort (void) __attribute__((noreturn));

31581

+

31582

+int

31583

+main ()

31584

+{

31585

+ int sum = 0;

31586

+ {

31587

+ int a[20];

31588

+ int *c;

31589

+ c = a;

31590

+ asm ("": "=r" (c):"0" (c));

31591

+ *c = 0;

31592

+ asm ("": "=r" (c):"0" (c));

31593

+ sum += *c;

31594

+ }

31595

+ {

31596

+ long b[10];

31597

+ long *c;

31598

+ c = b;

31599

+ asm ("": "=r" (c):"0" (c));

31600

+ *c = 1;

31601

+ asm ("": "=r" (c):"0" (c));

31602

+ sum += *c;

31603

+ }

31604

+

31605

+ if (sum != 1)

31606

+ abort();

31607

+ return 0;

31608

+}

31609

Index: gcc/testsuite/gcc.dg/torture/pr57425-3.c

31610

===================================================================

31611

--- a/src/gcc/testsuite/gcc.dg/torture/pr57425-3.c (.../tags/gcc_4_8_2_release)

31612

+++ b/src/gcc/testsuite/gcc.dg/torture/pr57425-3.c (.../branches/gcc-4_8-branch)

31613

@@ -0,0 +1,31 @@

31614

+/* { dg-do run } */

31615

+

31616

+extern void abort (void) __attribute__((noreturn));

31617

+

31618

+int

31619

+main ()

31620

+{

31621

+ int sum = 0;

31622

+ {

31623

+ long a[20];

31624

+ long *c;

31625

+ c = a;

31626

+ asm ("": "=r" (c):"0" (c));

31627

+ *c = 0;

31628

+ asm ("": "=r" (c):"0" (c));

31629

+ sum += *c;

31630

+ }

31631

+ {

31632

+ long long b[10];

31633

+ long long *c;

31634

+ c = b;

31635

+ asm ("": "=r" (c):"0" (c));

31636

+ *c = 1;

31637

+ asm ("": "=r" (c):"0" (c));

31638

+ sum += *c;

31639

+ }

31640

+

31641

+ if (sum != 1)

31642

+ abort();

31643

+ return 0;

31644

+}

31645

Index: gcc/testsuite/gcc.dg/torture/pr59047.c

31646

===================================================================

31647

--- a/src/gcc/testsuite/gcc.dg/torture/pr59047.c (.../tags/gcc_4_8_2_release)

31648

+++ b/src/gcc/testsuite/gcc.dg/torture/pr59047.c (.../branches/gcc-4_8-branch)

31649

@@ -0,0 +1,39 @@

31650

+/* { dg-do run } */

31651

+

31652

+extern void abort (void);

31653

+

31654

+struct

31655

+{

31656

+ int f0;

31657

+ int f1:1;

31658

+ int f2:2;

31659

+} a = {0, 0, 1};

31660

+

31661

+int b, c, *d, e, f;

31662

+

31663

+int

31664

+fn1 ()

31665

+{

31666

+ for (; b < 1; ++b)

31667

+ {

31668

+ for (e = 0; e < 1; e = 1)

31669

+ {

31670

+ int **g = &d;

31671

+ *g = &c;

31672

+ }

31673

+ *d = 0;

31674

+ f = a.f1;

31675

+ if (f)

31676

+ return 0;

31677

+ }

31678

+ return 0;

31679

+}

31680

+

31681

+int

31682

+main ()

31683

+{

31684

+ fn1 ();

31685

+ if (b != 1)

31686

+ abort ();

31687

+ return 0;

31688

+}

31689

Index: gcc/testsuite/gcc.dg/torture/pr58956.c

31690

===================================================================

31691

--- a/src/gcc/testsuite/gcc.dg/torture/pr58956.c (.../tags/gcc_4_8_2_release)

31692

+++ b/src/gcc/testsuite/gcc.dg/torture/pr58956.c (.../branches/gcc-4_8-branch)

31693

@@ -0,0 +1,30 @@

31694

+/* { dg-do run } */

31695

+

31696

+extern void abort (void);

31697

+

31698

+struct S

31699

+{

31700

+ int f0;

31701

+} a = {1}, b, g, *c = &b, **f = &c;

31702

+

31703

+int *d, **e = &d, h;

31704

+

31705

+struct S

31706

+foo ()

31707

+{

31708

+ *e = &h;

31709

+ if (!d)

31710

+ __builtin_unreachable ();

31711

+ *f = &g;

31712

+ return a;

31713

+}

31714

+

31715

+int

31716

+main ()

31717

+{

31718

+ struct S *i = c;

31719

+ *i = foo ();

31720

+ if (b.f0 != 1)

31721

+ abort ();

31722

+ return 0;

31723

+}

31724

Index: gcc/testsuite/gcc.dg/torture/pr60183.c

31725

===================================================================

31726

--- a/src/gcc/testsuite/gcc.dg/torture/pr60183.c (.../tags/gcc_4_8_2_release)

31727

+++ b/src/gcc/testsuite/gcc.dg/torture/pr60183.c (.../branches/gcc-4_8-branch)

31728

@@ -0,0 +1,38 @@

31729

+/* { dg-do run } */

31730

+

31731

+/* Large so an out-of-bound read will crash. */

31732

+unsigned char c[0x30001] = { 1 };

31733

+int j = 2;

31734

+

31735

+static void

31736

+foo (unsigned long *x, unsigned char *y)

31737

+{

31738

+ int i;

31739

+ unsigned long w = x[0];

31740

+ for (i = 0; i < j; i++)

31741

+ {

31742

+ w += *y;

31743

+ y += 0x10000;

31744

+ w += *y;

31745

+ y += 0x10000;

31746

+ }

31747

+ x[1] = w;

31748

+}

31749

+

31750

+__attribute__ ((noinline, noclone)) void

31751

+bar (unsigned long *x)

31752

+{

31753

+ foo (x, c);

31754

+}

31755

+

31756

+int

31757

+main ()

31758

+{

31759

+ unsigned long a[2] = { 0, -1UL };

31760

+ asm volatile (""::"r" (c):"memory");

31761

+ c[0] = 0;

31762

+ bar (a);

31763

+ if (a[1] != 0)

31764

+ __builtin_abort ();

31765

+ return 0;

31766

+}

31767

Index: gcc/testsuite/gcc.dg/torture/pr57517.c

31768

===================================================================

31769

--- a/src/gcc/testsuite/gcc.dg/torture/pr57517.c (.../tags/gcc_4_8_2_release)

31770

+++ b/src/gcc/testsuite/gcc.dg/torture/pr57517.c (.../branches/gcc-4_8-branch)

31771

@@ -0,0 +1,16 @@

31772

+/* { dg-do compile } */

31773

+

31774

+int x[1024], y[1024], z[1024], w[1024];

31775

+void foo (void)

31776

+{

31777

+ int i;

31778

+ for (i = 1; i < 1024; ++i)

31779

+ {

31780

+ int a = x[i];

31781

+ int b = y[i];

31782

+ int c = x[i-1];

31783

+ int d = y[i-1];

31784

+ if (w[i])

31785

+ z[i] = (a + b) + (c + d);

31786

+ }

31787

+}

31788

Index: gcc/testsuite/gcc.dg/torture/pr59891.c

31789

===================================================================

31790

--- a/src/gcc/testsuite/gcc.dg/torture/pr59891.c (.../tags/gcc_4_8_2_release)

31791

+++ b/src/gcc/testsuite/gcc.dg/torture/pr59891.c (.../branches/gcc-4_8-branch)

31792

@@ -0,0 +1,9 @@

31793

+/* PR c/59891 */

31794

+

31795

+unsigned int a;

31796

+

31797

+int

31798

+main ()

31799

+{

31800

+ return (0 ? a : 0) ? : 0 % 0; /* { dg-warning "division by zero" } */

31801

+}

31802

Index: gcc/testsuite/gcc.dg/torture/pr59164.c

31803

===================================================================

31804

--- a/src/gcc/testsuite/gcc.dg/torture/pr59164.c (.../tags/gcc_4_8_2_release)

31805

+++ b/src/gcc/testsuite/gcc.dg/torture/pr59164.c (.../branches/gcc-4_8-branch)

31806

@@ -0,0 +1,21 @@

31807

+/* { dg-do compile } */

31808

+

31809

+int a, d, e;

31810

+long b[10];

31811

+int c[10][8];

31812

+

31813

+int fn1(p1)

31814

+{

31815

+ return 1 >> p1;

31816

+}

31817

+

31818

+void fn2(void)

31819

+{

31820

+ int f;

31821

+ for (a=1; a <= 4; a++)

31822

+ {

31823

+ f = fn1(0 < c[a][0]);

31824

+ if (f || d)

31825

+ e = b[a] = 1;

31826

+ }

31827

+}

31828

Index: gcc/testsuite/gcc.dg/torture/pr58779.c

31829

===================================================================

31830

--- a/src/gcc/testsuite/gcc.dg/torture/pr58779.c (.../tags/gcc_4_8_2_release)

31831

+++ b/src/gcc/testsuite/gcc.dg/torture/pr58779.c (.../branches/gcc-4_8-branch)

31832

@@ -0,0 +1,12 @@

31833

+/* { dg-do run } */

31834

+

31835

+int a, c;

31836

+

31837

+int main ()

31838

+{

31839

+ int e = -1;

31840

+ short d = (c <= 0) ^ e;

31841

+ if ((unsigned int) a - (a || d) <= (unsigned int) a)

31842

+ __builtin_abort ();

31843

+ return 0;

31844

+}

31845

Index: gcc/testsuite/gcc.dg/torture/pr59139.c

31846

===================================================================

31847

--- a/src/gcc/testsuite/gcc.dg/torture/pr59139.c (.../tags/gcc_4_8_2_release)

31848

+++ b/src/gcc/testsuite/gcc.dg/torture/pr59139.c (.../branches/gcc-4_8-branch)

31849

@@ -0,0 +1,20 @@

31850

+/* { dg-do compile } */

31851

+

31852

+int a, b, c, d, e;

31853

+int fn1(p1, p2) { return p2 == 0 ? p1 : 1 % p2; }

31854

+

31855

+void fn2()

31856

+{

31857

+ c = 0;

31858

+ for (;; c = (unsigned short)c)

31859

+ {

31860

+ b = 2;

31861

+ for (; b; b = a)

31862

+ {

31863

+ e = fn1(2, c && 1);

31864

+ d = c == 0 ? e : c;

31865

+ if (d)

31866

+ return;

31867

+ }

31868

+ }

31869

+}

31870

Index: gcc/testsuite/gcc.dg/torture/pr58079.c

31871

===================================================================

31872

--- a/src/gcc/testsuite/gcc.dg/torture/pr58079.c (.../tags/gcc_4_8_2_release)

31873

+++ b/src/gcc/testsuite/gcc.dg/torture/pr58079.c (.../branches/gcc-4_8-branch)

31874

@@ -0,0 +1,107 @@

31875

+/* { dg-options "-mlong-calls" { target mips*-*-* } } */

31876

+

31877

+typedef unsigned char u8;

31878

+typedef unsigned short u16;

31879

+typedef unsigned int __kernel_size_t;

31880

+typedef __kernel_size_t size_t;

31881

+struct list_head {

31882

+ struct list_head *next;

31883

+};

31884

+

31885

+struct dmx_ts_feed {

31886

+ int is_filtering;

31887

+};

31888

+struct dmx_section_feed {

31889

+ u16 secbufp;

31890

+ u16 seclen;

31891

+ u16 tsfeedp;

31892

+};

31893

+

31894

+typedef int (*dmx_ts_cb) (

31895

+ const u8 * buffer1,

31896

+ size_t buffer1_length,

31897

+ const u8 * buffer2,

31898

+ size_t buffer2_length

31899

+);

31900

+

31901

+struct dvb_demux_feed {

31902

+ union {

31903

+ struct dmx_ts_feed ts;

31904

+ struct dmx_section_feed sec;

31905

+ } feed;

31906

+ union {

31907

+ dmx_ts_cb ts;

31908

+ } cb;

31909

+ int type;

31910

+ u16 pid;

31911

+ int ts_type;

31912

+ struct list_head list_head;

31913

+};

31914

+

31915

+struct dvb_demux {

31916

+ int (*stop_feed)(struct dvb_demux_feed *feed);

31917

+ struct list_head feed_list;

31918

+};

31919

+

31920

+

31921

+static

31922

+inline

31923

+__attribute__((always_inline))

31924

+u8

31925

+payload(const u8 *tsp)

31926

+{

31927

+ if (tsp[3] & 0x20) {

31928

+ return 184 - 1 - tsp[4];

31929

+ }

31930

+ return 184;

31931

+}

31932

+

31933

+static

31934

+inline

31935

+__attribute__((always_inline))

31936

+int

31937

+dvb_dmx_swfilter_payload(struct dvb_demux_feed *feed, const u8 *buf)

31938

+{

31939

+ int count = payload(buf);

31940

+ int p;

31941

+ if (count == 0)

31942

+ return -1;

31943

+ return feed->cb.ts(&buf[p], count, ((void *)0), 0);

31944

+}

31945

+

31946

+static

31947

+inline

31948

+__attribute__((always_inline))

31949

+void

31950

+dvb_dmx_swfilter_packet_type(struct dvb_demux_feed *feed, const u8 *buf)

31951

+{

31952

+ switch (feed->type) {

31953

+ case 0:

31954

+ if (feed->ts_type & 1) {

31955

+ dvb_dmx_swfilter_payload(feed, buf);

31956

+ }

31957

+ if (dvb_dmx_swfilter_section_packet(feed, buf) < 0)

31958

+ feed->feed.sec.seclen = feed->feed.sec.secbufp = 0;

31959

+ }

31960

+}

31961

+

31962

+static

31963

+void

31964

+dvb_dmx_swfilter_packet(struct dvb_demux *demux, const u8 *buf)

31965

+{

31966

+ struct dvb_demux_feed *feed;

31967

+ int dvr_done = 0;

31968

+

31969

+ for (feed = ({ const typeof( ((typeof(*feed) *)0)->list_head ) *__mptr = ((&demux->feed_list)->next); (typeof(*feed) *)( (char *)__mptr - __builtin_offsetof(typeof(*feed),list_head) );}); __builtin_prefetch(feed->list_head.next), &feed->list_head != (&demux->feed_list); feed = ({ const typeof( ((typeof(*feed) *)0)->list_head ) *__mptr = (feed->list_head.next); (typeof(*feed) *)( (char *)__mptr - __builtin_offsetof(typeof(*feed),list_head) );})) {

31970

+ if (((((feed)->type == 0) && ((feed)->feed.ts.is_filtering) && (((feed)->ts_type & (1 | 8)) == 1))) && (dvr_done++))

31971

+ dvb_dmx_swfilter_packet_type(feed, buf);

31972

+ else if (feed->pid == 0x2000)

31973

+ feed->cb.ts(buf, 188, ((void *)0), 0);

31974

+ }

31975

+}

31976

+void dvb_dmx_swfilter_packets(struct dvb_demux *demux, const u8 *buf, size_t count)

31977

+{

31978

+ while (count--) {

31979

+ dvb_dmx_swfilter_packet(demux, buf);

31980

+ }

31981

+}

31982

Index: gcc/testsuite/gcc.dg/torture/pr60903.c

31983

===================================================================

31984

--- a/src/gcc/testsuite/gcc.dg/torture/pr60903.c (.../tags/gcc_4_8_2_release)

31985

+++ b/src/gcc/testsuite/gcc.dg/torture/pr60903.c (.../branches/gcc-4_8-branch)

31986

@@ -0,0 +1,22 @@

31987

+/* { dg-do compile } */

31988

+

31989

+extern int a, b, k, q;

31990

+

31991

+void

31992

+foo ()

31993

+{

31994

+ if (a)

31995

+ {

31996

+ while (q)

31997

+ {

31998

+ lbl:

31999

+ if (a)

32000

+ {

32001

+ a = 0;

32002

+ goto lbl;

32003

+ }

32004

+ }

32005

+ b = k;

32006

+ }

32007

+ goto lbl;

32008

+}

32009

Index: gcc/testsuite/gcc.dg/torture/pr58830.c

32010

===================================================================

32011

--- a/src/gcc/testsuite/gcc.dg/torture/pr58830.c (.../tags/gcc_4_8_2_release)

32012

+++ b/src/gcc/testsuite/gcc.dg/torture/pr58830.c (.../branches/gcc-4_8-branch)

32013

@@ -0,0 +1,42 @@

32014

+/* { dg-do run } */

32015

+/* { dg-additional-options "-ftree-pre -ftree-partial-pre" } */

32016

+

32017

+extern void abort (void);

32018

+

32019

+int b, c, d, f, g, h, i, j[6], *l = &b, *m, n, *o, r;

32020

+char k;

32021

+

32022

+static int

32023

+foo ()

32024

+{

32025

+ char *p = &k;

32026

+

32027

+ for (; d; d++)

32028

+ if (i)

32029

+ h = 0;

32030

+ else

32031

+ h = c || (r = 0);

32032

+

32033

+ for (f = 0; f < 2; f++)

32034

+ {

32035

+ unsigned int q;

32036

+ *l = 0;

32037

+ if (n)

32038

+ *m = g;

32039

+ if (g)

32040

+ o = 0;

32041

+ for (q = -8; q >= 5; q++)

32042

+ (*p)--;

32043

+ }

32044

+

32045

+ return 0;

32046

+}

32047

+

32048

+int

32049

+main ()

32050

+{

32051

+ foo ();

32052

+ if (j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[0]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]] ^ (k & 15)] != 0)

32053

+ abort ();

32054

+ return 0;

32055

+}

32056

Index: gcc/testsuite/gcc.dg/torture/pr60930.c

32057

===================================================================

32058

--- a/src/gcc/testsuite/gcc.dg/torture/pr60930.c (.../tags/gcc_4_8_2_release)

32059

+++ b/src/gcc/testsuite/gcc.dg/torture/pr60930.c (.../branches/gcc-4_8-branch)

32060

@@ -0,0 +1,22 @@

32061

+/* { dg-do run } */

32062

+

32063

+int x = 1;

32064

+

32065

+__attribute__((noinline, noclone)) void

32066

+foo (unsigned long long t)

32067

+{

32068

+ asm volatile ("" : : "r" (&t));

32069

+ if (t == 1)

32070

+ __builtin_abort ();

32071

+}

32072

+

32073

+int

32074

+main ()

32075

+{

32076

+#if __SIZEOF_LONG_LONG__ >= 8

32077

+ unsigned long long t = 0xffffffffffffffffULL * (0xffffffffUL * x);

32078

+ if (t != 0xffffffff00000001ULL)

32079

+ foo (t);;

32080

+#endif

32081

+ return 0;

32082

+}

32083

Index: gcc/testsuite/gcc.dg/torture/pr59715.c

32084

===================================================================

32085

--- a/src/gcc/testsuite/gcc.dg/torture/pr59715.c (.../tags/gcc_4_8_2_release)

32086

+++ b/src/gcc/testsuite/gcc.dg/torture/pr59715.c (.../branches/gcc-4_8-branch)

32087

@@ -0,0 +1,21 @@

32088

+/* { dg-do run } */

32089

+

32090

+extern void abort (void);

32091

+

32092

+int a = 2, b;

32093

+

32094

+int

32095

+main ()

32096

+{

32097

+ int c;

32098

+ if (!b)

32099

+ {

32100

+ b = a;

32101

+ c = a == 0 ? 1 : 1 % a;

32102

+ if (c)

32103

+ b = 0;

32104

+ }

32105

+ if (b != 0)

32106

+ abort ();

32107

+ return 0;

32108

+}

32109

Index: gcc/testsuite/gcc.dg/torture/pr60115.c

32110

===================================================================

32111

--- a/src/gcc/testsuite/gcc.dg/torture/pr60115.c (.../tags/gcc_4_8_2_release)

32112

+++ b/src/gcc/testsuite/gcc.dg/torture/pr60115.c (.../branches/gcc-4_8-branch)

32113

@@ -0,0 +1,14 @@

32114

+/* { dg-do run } */

32115

+

32116

+int a, b[2];

32117

+

32118

+int

32119

+main ()

32120

+{

32121

+lbl:

32122

+ for (; a; a--)

32123

+ if (b[10000])

32124

+ goto lbl;

32125

+

32126

+ return 0;

32127

+}

32128

Index: gcc/testsuite/gcc.dg/torture/pr59903.c

32129

===================================================================

32130

--- a/src/gcc/testsuite/gcc.dg/torture/pr59903.c (.../tags/gcc_4_8_2_release)

32131

+++ b/src/gcc/testsuite/gcc.dg/torture/pr59903.c (.../branches/gcc-4_8-branch)

32132

@@ -0,0 +1,56 @@

32133

+/* { dg-do compile } */

32134

+

32135

+int a, b, c, d, e, f, g, h, i[3], l, m, n, o, p, q, r;

32136

+

32137

+struct S0

32138

+{

32139

+ int f0;

32140

+ int f1;

32141

+ int f2;

32142

+ int f3;

32143

+} j;

32144

+

32145

+static int

32146

+fn1 (int p1)

32147

+{

32148

+ return p1 || ((p1 > 0) > (e << 1));

32149

+}

32150

+

32151

+static struct S0

32152

+fn2 (struct S0 p1)

32153

+{

32154

+ char s;

32155

+ struct S0 t = {0,0,0,0};

32156

+ int u = 2;

32157

+ for (;;)

32158

+ {

32159

+ if (i[0])

32160

+ break;

32161

+ for (m = 0; m < 4; m++)

32162

+ for (p1.f0 = 0; p1.f0 < 3; p1.f0++)

32163

+ {

32164

+ j = t;

32165

+ t.f3 = i[p1.f0];

32166

+ o = b || 1 >> b ? 0 : a < 0;

32167

+ q = 1 % d;

32168

+ if ((g < fn1 ((1 ^ (q & 1)) | n)) ^ u)

32169

+ j.f3 |= p % 2;

32170

+ s = j.f3 > 0 ? j.f3 : j.f3 << 1;

32171

+ r = l = s && p1.f1 * c;

32172

+ h = p1.f1;

32173

+ }

32174

+ }

32175

+ return p1;

32176

+}

32177

+

32178

+int

32179

+main ()

32180

+{

32181

+ for (;f;)

32182

+ {

32183

+ struct S0 v = {0,0,0,0};

32184

+ fn2 (v);

32185

+ j.f3 = 0;

32186

+ }

32187

+ return 0;

32188

+}

32189

Index: gcc/testsuite/gcc.dg/torture/pr58143-1.c

32190

===================================================================

32191

--- a/src/gcc/testsuite/gcc.dg/torture/pr58143-1.c (.../tags/gcc_4_8_2_release)

32192

+++ b/src/gcc/testsuite/gcc.dg/torture/pr58143-1.c (.../branches/gcc-4_8-branch)

32193

@@ -0,0 +1,51 @@

32194

+/* { dg-do run } */

32195

+/* { dg-additional-options "-fstrict-overflow" } */

32196

+

32197

+extern void abort (void);

32198

+

32199

+int a, b, c, d, e, f, g, h = 1, i;

32200

+

32201

+int foo (int p)

32202

+{

32203

+ return p < 0 && a < - __INT_MAX__ - 1 - p ? 0 : 1;

32204

+}

32205

+

32206

+int *bar ()

32207

+{

32208

+ int j;

32209

+ i = h ? 0 : 1 % h;

32210

+ for (j = 0; j < 1; j++)

32211

+ for (d = 0; d; d++)

32212

+ for (e = 1; e;)

32213

+ return 0;

32214

+ return 0;

32215

+}

32216

+

32217

+int baz ()

32218

+{

32219

+ for (; b >= 0; b--)

32220

+ for (c = 1; c >= 0; c--)

32221

+ {

32222

+ int *k = &c;

32223

+ for (;;)

32224

+ {

32225

+ for (f = 0; f < 1; f++)

32226

+ {

32227

+ g = foo (*k);

32228

+ bar ();

32229

+ }

32230

+ if (*k)

32231

+ break;

32232

+ return 0;

32233

+ }

32234

+ }

32235

+ return 0;

32236

+}

32237

+

32238

+int main ()

32239

+{

32240

+ baz ();

32241

+ if (b != 0)

32242

+ abort ();

32243

+ return 0;

32244

+}

32245

Index: gcc/testsuite/gcc.dg/torture/pr58143-2.c

32246

===================================================================

32247

--- a/src/gcc/testsuite/gcc.dg/torture/pr58143-2.c (.../tags/gcc_4_8_2_release)

32248

+++ b/src/gcc/testsuite/gcc.dg/torture/pr58143-2.c (.../branches/gcc-4_8-branch)

32249

@@ -0,0 +1,34 @@

32250

+/* { dg-do run } */

32251

+/* { dg-additional-options "-fstrict-overflow" } */

32252

+

32253

+int a, b, d, e, f, *g, h, i;

32254

+volatile int c;

32255

+

32256

+char foo (unsigned char p)

32257

+{

32258

+ return p + 1;

32259

+}

32260

+

32261

+int bar ()

32262

+{

32263

+ for (h = 0; h < 3; h = foo (h))

32264

+ {

32265

+ c;

32266

+ for (f = 0; f < 1; f++)

32267

+ {

32268

+ i = a && 0 < -__INT_MAX__ - h ? 0 : 1;

32269

+ if (e)

32270

+ for (; d;)

32271

+ b = 0;

32272

+ else

32273

+ g = 0;

32274

+ }

32275

+ }

32276

+ return 0;

32277

+}

32278

+

32279

+int main ()

32280

+{

32281

+ bar ();

32282

+ return 0;

32283

+}

32284

Index: gcc/testsuite/gcc.dg/torture/pr58941.c

32285

===================================================================

32286

--- a/src/gcc/testsuite/gcc.dg/torture/pr58941.c (.../tags/gcc_4_8_2_release)

32287

+++ b/src/gcc/testsuite/gcc.dg/torture/pr58941.c (.../branches/gcc-4_8-branch)

32288

@@ -0,0 +1,33 @@

32289

+/* { dg-do run } */

32290

+

32291

+extern void abort (void);

32292

+

32293

+typedef struct {

32294

+ int msgLength;

32295

+ unsigned char data[1000];

32296

+} SMsg;

32297

+

32298

+typedef struct {

32299

+ int dummy;

32300

+ int d[0];

32301

+} SData;

32302

+

32303

+int condition = 3;

32304

+

32305

+int main()

32306

+{

32307

+ SMsg msg;

32308

+ SData *pData = (SData*)(msg.data);

32309

+ unsigned int i = 0;

32310

+ for (i = 0; i < 1; i++)

32311

+ {

32312

+ pData->d[i] = 0;

32313

+ if(condition & 1)

32314

+ pData->d[i] |= 0x55;

32315

+ if(condition & 2)

32316

+ pData->d[i] |= 0xaa;

32317

+ }

32318

+ if (pData->d[0] != 0xff)

32319

+ abort ();

32320

+ return 0;

32321

+}

32322

Index: gcc/testsuite/gcc.dg/torture/pr57488.c

32323

===================================================================

32324

--- a/src/gcc/testsuite/gcc.dg/torture/pr57488.c (.../tags/gcc_4_8_2_release)

32325

+++ b/src/gcc/testsuite/gcc.dg/torture/pr57488.c (.../branches/gcc-4_8-branch)

32326

@@ -0,0 +1,58 @@

32327

+/* { dg-do run } */

32328

+

32329

+extern void abort (void);

32330

+

32331

+int i, j, *pj = &j, **ppj = &pj;

32332

+int x, *px = &x;

32333

+

32334

+short s, *ps = &s, k;

32335

+

32336

+unsigned short u, *pu = &u, **ppu = &pu;

32337

+

32338

+char c, *pc = &c;

32339

+

32340

+unsigned char v = 48;

32341

+

32342

+static int

32343

+bar (int p)

32344

+{

32345

+ p = k;

32346

+ *px = **ppu = i;

32347

+ *ppj = &p;

32348

+ if (**ppj)

32349

+ *pj = p;

32350

+ return p;

32351

+}

32352

+

32353

+void __attribute__((noinline))

32354

+foo ()

32355

+{

32356

+ for (; i <= 3; i++)

32357

+ for (; j; j--);

32358

+

32359

+ u ^= bar (*pj);

32360

+

32361

+ for (k = 1; k >= 0; k--)

32362

+ {

32363

+ int l;

32364

+ bar (0);

32365

+ for (l = 1; l < 5; l++)

32366

+ {

32367

+ int m;

32368

+ for (m = 6; m; m--)

32369

+ {

32370

+ v--;

32371

+ *ps = *pc;

32372

+ }

32373

+ }

32374

+ }

32375

+}

32376

+

32377

+int

32378

+main ()

32379

+{

32380

+ foo ();

32381

+ if (v != 0)

32382

+ abort ();

32383

+ return 0;

32384

+}

32385

Index: gcc/testsuite/gcc.dg/torture/pr57569.c

32386

===================================================================

32387

--- a/src/gcc/testsuite/gcc.dg/torture/pr57569.c (.../tags/gcc_4_8_2_release)

32388

+++ b/src/gcc/testsuite/gcc.dg/torture/pr57569.c (.../branches/gcc-4_8-branch)

32389

@@ -0,0 +1,37 @@

32390

+/* { dg-do run } */

32391

+

32392

+extern void abort (void) __attribute__((noreturn));

32393

+

32394

+struct S { int f0; } a;

32395

+

32396

+int b, e, *d = &b, f;

32397

+

32398

+void

32399

+fn1 ()

32400

+{

32401

+ int **g[9][6];

32402

+ int ***h = &g[6][3];

32403

+ for (; e < 9; e++) {

32404

+ f = 0;

32405

+ for (; f < 6; f++)

32406

+ g[e][f] = &d;

32407

+ }

32408

+ ***h = 0;

32409

+}

32410

+

32411

+void

32412

+fn2 ()

32413

+{

32414

+ fn1 ();

32415

+ struct S c[4][10] = {};

32416

+ a = c[3][9];

32417

+}

32418

+

32419

+int

32420

+main ()

32421

+{

32422

+ fn2 ();

32423

+ if (a.f0 != 0)

32424

+ abort ();

32425

+ return 0;

32426

+}

32427

Index: gcc/testsuite/gcc.dg/torture/pr58143-3.c

32428

===================================================================

32429

--- a/src/gcc/testsuite/gcc.dg/torture/pr58143-3.c (.../tags/gcc_4_8_2_release)

32430

+++ b/src/gcc/testsuite/gcc.dg/torture/pr58143-3.c (.../branches/gcc-4_8-branch)

32431

@@ -0,0 +1,18 @@

32432

+/* { dg-do run } */

32433

+/* { dg-additional-options "-fstrict-overflow" } */

32434

+

32435

+int a, b, c, d, e;

32436

+

32437

+int

32438

+main ()

32439

+{

32440

+ for (b = 4; b > -30; b--)

32441

+ for (; c;)

32442

+ for (;;)

32443

+ {

32444

+ e = a > __INT_MAX__ - b;

32445

+ if (d)

32446

+ break;

32447

+ }

32448

+ return 0;

32449

+}

32450

Index: gcc/testsuite/gcc.dg/torture/pr53922.c

32451

===================================================================

32452

--- a/src/gcc/testsuite/gcc.dg/torture/pr53922.c (.../tags/gcc_4_8_2_release)

32453

+++ b/src/gcc/testsuite/gcc.dg/torture/pr53922.c (.../branches/gcc-4_8-branch)

32454

@@ -3,6 +3,7 @@

32455

/* { dg-skip-if "No undefined" { *-*-mingw* } { "*" } { "" } } */

32456

/* { dg-skip-if "No undefined weak" { hppa*-*-hpux* && { ! lp64 } } { "*" } { "" } } */

32457

/* { dg-options "-Wl,-undefined,dynamic_lookup" { target *-*-darwin* } } */

32458

+/* { dg-additional-options "-Wl,-flat_namespace" { target *-*-darwin[89]* } } */

32459

32460

int x(int a)

32461

{

32462

Index: gcc/testsuite/gcc.dg/torture/pr57864.c

32463

===================================================================

32464

--- a/src/gcc/testsuite/gcc.dg/torture/pr57864.c (.../tags/gcc_4_8_2_release)

32465

+++ b/src/gcc/testsuite/gcc.dg/torture/pr57864.c (.../branches/gcc-4_8-branch)

32466

@@ -0,0 +1,37 @@

32467

+/* { dg-do compile } */

32468

+

32469

+union U {

32470

+ double val;

32471

+ union U *ptr;

32472

+};

32473

+

32474

+union U *d;

32475

+double a;

32476

+int b;

32477

+int c;

32478

+

32479

+static void fn1(union U *p1, int p2, _Bool p3)

32480

+{

32481

+ union U *e;

32482

+

32483

+ if (p2 == 0)

32484

+ a = ((union U*)((unsigned long)p1 & ~1))->val;

32485

+

32486

+ if (b) {

32487

+ e = p1;

32488

+ } else if (c) {

32489

+ e = ((union U*)((unsigned long)p1 & ~1))->ptr;

32490

+ d = e;

32491

+ } else {

32492

+ e = 0;

32493

+ d = ((union U*)0)->ptr;

32494

+ }

32495

+

32496

+ fn1 (e, 0, 0);

32497

+ fn1 (0, 0, p3);

32498

+}

32499

+

32500

+void fn2 (void)

32501

+{

32502

+ fn1 (0, 0, 0);

32503

+}

32504

Index: gcc/testsuite/gcc.dg/torture/pr59288.c

32505

===================================================================

32506

--- a/src/gcc/testsuite/gcc.dg/torture/pr59288.c (.../tags/gcc_4_8_2_release)

32507

+++ b/src/gcc/testsuite/gcc.dg/torture/pr59288.c (.../branches/gcc-4_8-branch)

32508

@@ -0,0 +1,9 @@

32509

+/* { dg-do compile } */

32510

+

32511

+void

32512

+baz (int *d)

32513

+{

32514

+ long int i, j, k;

32515

+ for (i = 0, j = 0, k = 0; i < 512; i = (int) i + 1, j = (int) j + 1, k = (int) k + 3)

32516

+ d[i] = j ^ (i * 3) ^ (2 * k + 2);

32517

+}

32518

Index: gcc/testsuite/gcc.dg/torture/pr60766.c

32519

===================================================================

32520

--- a/src/gcc/testsuite/gcc.dg/torture/pr60766.c (.../tags/gcc_4_8_2_release)

32521

+++ b/src/gcc/testsuite/gcc.dg/torture/pr60766.c (.../branches/gcc-4_8-branch)

32522

@@ -0,0 +1,15 @@

32523

+/* { dg-do run } */

32524

+

32525

+int m = 9;

32526

+

32527

+int main()

32528

+{

32529

+ int n, x;

32530

+

32531

+ n = m;

32532

+ for (x = 0; x <= n; x++)

32533

+ if (n == x + (x + 1) + (x + 2))

32534

+ return 0;

32535

+

32536

+ __builtin_abort();

32537

+}

32538

Index: gcc/testsuite/gcc.dg/torture/pr57425-1.c

32539

===================================================================

32540

--- a/src/gcc/testsuite/gcc.dg/torture/pr57425-1.c (.../tags/gcc_4_8_2_release)

32541

+++ b/src/gcc/testsuite/gcc.dg/torture/pr57425-1.c (.../branches/gcc-4_8-branch)

32542

@@ -0,0 +1,37 @@

32543

+/* { dg-do run } */

32544

+

32545

+extern void abort (void) __attribute__((noreturn));

32546

+

32547

+union setconflict

32548

+{

32549

+ int a[20];

32550

+ long b[10];

32551

+};

32552

+

32553

+int

32554

+main ()

32555

+{

32556

+ int sum = 0;

32557

+ {

32558

+ union setconflict a;

32559

+ int *c;

32560

+ c = a.a;

32561

+ asm ("": "=r" (c):"0" (c));

32562

+ *c = 0;

32563

+ asm ("": "=r" (c):"0" (c));

32564

+ sum += *c;

32565

+ }

32566

+ {

32567

+ union setconflict a;

32568

+ long *c;

32569

+ c = a.b;

32570

+ asm ("": "=r" (c):"0" (c));

32571

+ *c = 1;

32572

+ asm ("": "=r" (c):"0" (c));

32573

+ sum += *c;

32574

+ }

32575

+

32576

+ if (sum != 1)

32577

+ abort();

32578

+ return 0;

32579

+}

32580

Index: gcc/testsuite/gcc.dg/torture/pr59330.c

32581

===================================================================

32582

--- a/src/gcc/testsuite/gcc.dg/torture/pr59330.c (.../tags/gcc_4_8_2_release)

32583

+++ b/src/gcc/testsuite/gcc.dg/torture/pr59330.c (.../branches/gcc-4_8-branch)

32584

@@ -0,0 +1,17 @@

32585

+/* { dg-do run } */

32586

+

32587

+void free(void *ptr)

32588

+{

32589

+}

32590

+

32591

+void *foo(void)

32592

+{

32593

+ return 0;

32594

+}

32595

+

32596

+int main(void)

32597

+{

32598

+ void *p = foo();

32599

+ free(p);

32600

+ return 0;

32601

+}

32602

Index: gcc/testsuite/gcc.dg/tree-ssa/20040517-1.c

32603

===================================================================

32604

--- a/src/gcc/testsuite/gcc.dg/tree-ssa/20040517-1.c (.../tags/gcc_4_8_2_release)

32605

+++ b/src/gcc/testsuite/gcc.dg/tree-ssa/20040517-1.c (.../branches/gcc-4_8-branch)

32606

@@ -16,6 +16,7 @@

32607

/* We used to treat malloc functions like pure and const functions, but

32608

malloc functions may clobber global memory. Only the function result

32609

does not alias any other pointer.

32610

- Hence, we must have a VDEF for a before and after the call to foo(). */

32611

-/* { dg-final { scan-tree-dump-times "VDEF" 2 "alias"} } */

32612

+ Hence, we must have a VDEF for a before and after the call to foo().

32613

+ And one after the call to abort(). */

32614

+/* { dg-final { scan-tree-dump-times "VDEF" 3 "alias"} } */

32615

/* { dg-final { cleanup-tree-dump "alias" } } */

32616

Index: gcc/testsuite/gcc.dg/tree-ssa/predcom-6.c

32617

===================================================================

32618

--- a/src/gcc/testsuite/gcc.dg/tree-ssa/predcom-6.c (.../tags/gcc_4_8_2_release)

32619

+++ b/src/gcc/testsuite/gcc.dg/tree-ssa/predcom-6.c (.../branches/gcc-4_8-branch)

32620

@@ -0,0 +1,14 @@

32621

+/* { dg-do run } */

32622

+/* { dg-options "-O3" } */

32623

+

32624

+int a, c, e[5][2];

32625

+unsigned int d;

32626

+

32627

+int

32628

+main ()

32629

+{

32630

+ for (d = 0; d < 2; d++)

32631

+ if (a ? 0 : e[c + 3][d] & e[c + 4][d])

32632

+ break;

32633

+ return 0;

32634

+}

32635

Index: gcc/testsuite/gcc.dg/tree-ssa/predcom-7.c

32636

===================================================================

32637

--- a/src/gcc/testsuite/gcc.dg/tree-ssa/predcom-7.c (.../tags/gcc_4_8_2_release)

32638

+++ b/src/gcc/testsuite/gcc.dg/tree-ssa/predcom-7.c (.../branches/gcc-4_8-branch)

32639

@@ -0,0 +1,18 @@

32640

+/* { dg-do run } */

32641

+/* { dg-options "-O3 -fdump-tree-pcom-details" } */

32642

+

32643

+int b, f, d[5][2];

32644

+unsigned int c;

32645

+

32646

+int

32647

+main ()

32648

+{

32649

+ for (c = 0; c < 2; c++)

32650

+ if (d[b + 3][c] & d[b + 4][c])

32651

+ if (f)

32652

+ break;

32653

+ return 0;

32654

+}

32655

+

32656

+/* { dg-final { scan-tree-dump "Executing predictive commoning" "pcom" } } */

32657

+/* { dg-final { cleanup-tree-dump "pcom" } } */

32658

Index: gcc/testsuite/gcc.dg/tls/pr58595.c

32659

===================================================================

32660

--- a/src/gcc/testsuite/gcc.dg/tls/pr58595.c (.../tags/gcc_4_8_2_release)

32661

+++ b/src/gcc/testsuite/gcc.dg/tls/pr58595.c (.../branches/gcc-4_8-branch)

32662

@@ -0,0 +1,28 @@

32663

+/* PR target/58595 */

32664

+/* { dg-do run } */

32665

+/* { dg-options "-O2" } */

32666

+/* { dg-additional-options "-fpic" { target fpic } } */

32667

+/* { dg-require-effective-target tls } */

32668

+/* { dg-require-effective-target sync_int_long } */

32669

+

32670

+struct S { unsigned long a, b; };

32671

+__thread struct S s;

32672

+void bar (unsigned long *);

32673

+

32674

+__attribute__((noinline)) void

32675

+foo (void)

32676

+{

32677

+ int i;

32678

+ for (i = 0; i < 10; i++)

32679

+ __sync_fetch_and_add (&s.b, 1L);

32680

+}

32681

+

32682

+int

32683

+main ()

32684

+{

32685

+ s.b = 12;

32686

+ foo ();

32687

+ if (s.b != 22)

32688

+ __builtin_abort ();

32689

+ return 0;

32690

+}

32691

Index: gcc/testsuite/gcc.dg/strlenopt-4.c

32692

===================================================================

32693

--- a/src/gcc/testsuite/gcc.dg/strlenopt-4.c (.../tags/gcc_4_8_2_release)

32694

+++ b/src/gcc/testsuite/gcc.dg/strlenopt-4.c (.../branches/gcc-4_8-branch)

32695

@@ -66,16 +66,10 @@

32696

return 0;

32697

}

32698

32699

-/* For targets providing a movstr pattern strcat is already decomposed

32700

- into strlen + strcpy by fold_builtin_strcat. */

32701

-

32702

-/* { dg-final { scan-tree-dump-times "strlen \\(" 3 "strlen" { target { ! s390*-*-* } } } } */

32703

-/* { dg-final { scan-tree-dump-times "strlen \\(" 6 "strlen" { target s390*-*-* } } } */

32704

+/* { dg-final { scan-tree-dump-times "strlen \\(" 3 "strlen" } } */

32705

/* { dg-final { scan-tree-dump-times "memcpy \\(" 4 "strlen" } } */

32706

-/* { dg-final { scan-tree-dump-times "strcpy \\(" 3 "strlen" { target { ! s390*-*-* } } } } */

32707

-/* { dg-final { scan-tree-dump-times "strcpy \\(" 6 "strlen" { target s390*-*-* } } } */

32708

-/* { dg-final { scan-tree-dump-times "strcat \\(" 3 "strlen" { target { ! s390*-*-* } } } } */

32709

-/* { dg-final { scan-tree-dump-times "strcat \\(" 0 "strlen" { target s390*-*-* } } } */

32710

+/* { dg-final { scan-tree-dump-times "strcpy \\(" 3 "strlen" } } */

32711

+/* { dg-final { scan-tree-dump-times "strcat \\(" 3 "strlen" } } */

32712

/* { dg-final { scan-tree-dump-times "strchr \\(" 0 "strlen" } } */

32713

/* { dg-final { scan-tree-dump-times "stpcpy \\(" 0 "strlen" } } */

32714

/* { dg-final { cleanup-tree-dump "strlen" } } */

32715

Index: gcc/testsuite/gcc.dg/pr56824.c

32716

===================================================================

32717

--- a/src/gcc/testsuite/gcc.dg/pr56824.c (.../tags/gcc_4_8_2_release)

32718

+++ b/src/gcc/testsuite/gcc.dg/pr56824.c (.../branches/gcc-4_8-branch)

32719

@@ -0,0 +1,18 @@

32720

+/* PR preprocessor/56824 */

32721

+/* { dg-do compile } */

32722

+/* { dg-options "-Waggregate-return" } */

32723

+

32724

+struct S { int i; };

32725

+struct S foo (void);

32726

+

32727

+#pragma GCC diagnostic push

32728

+#pragma GCC diagnostic ignored "-Waggregate-return"

32729

+

32730

+int

32731

+main ()

32732

+{

32733

+ foo ();

32734

+ return 0;

32735

+}

32736

+

32737

+#pragma GCC diagnostic pop

32738

Index: gcc/testsuite/gcc.dg/ipa/pr55260.c

32739

===================================================================

32740

--- a/src/gcc/testsuite/gcc.dg/ipa/pr55260.c (.../tags/gcc_4_8_2_release)

32741

+++ b/src/gcc/testsuite/gcc.dg/ipa/pr55260.c (.../branches/gcc-4_8-branch)

32742

@@ -0,0 +1,38 @@

32743

+/* { dg-do compile } */

32744

+/* { dg-options "-O2 -fno-inline -fipa-cp-clone" } */

32745

+

32746

+typedef struct {

32747

+ int *ptr;

32748

+ int len;

32749

+} string;

32750

+typedef struct {

32751

+ string nantstr;

32752

+ int *nant;

32753

+} malv;

32754

+typedef struct {

32755

+ int *nor;

32756

+} list_heads;

32757

+int b;

32758

+list_heads *fn1(string, int *, unsigned);

32759

+void fn2(malv *p1, list_heads *p2, unsigned p3) {

32760

+ string a = p1->nantstr;

32761

+ fn1(a, p1->nant, p3);

32762

+}

32763

+

32764

+void fn3(unsigned p1) { fn2(0, 0, p1); }

32765

+

32766

+list_heads *fn1(string p1, int *p2, unsigned p3) {

32767

+ while (1) {

32768

+ if (p3)

32769

+ fn3(1);

32770

+ if (b)

32771

+ return 0;

32772

+ fn3(1);

32773

+ }

32774

+}

32775

+

32776

+void fn5() {

32777

+ list_heads c;

32778

+ c.nor = 0;

32779

+ fn2(0, &c, 1);

32780

+}

32781

Index: gcc/testsuite/gcc.dg/ipa/pr59610.c

32782

===================================================================

32783

--- a/src/gcc/testsuite/gcc.dg/ipa/pr59610.c (.../tags/gcc_4_8_2_release)

32784

+++ b/src/gcc/testsuite/gcc.dg/ipa/pr59610.c (.../branches/gcc-4_8-branch)

32785

@@ -0,0 +1,11 @@

32786

+/* { dg-do compile } */

32787

+/* { dg-options "-O2" } */

32788

+

32789

+struct A { int a; };

32790

+extern void *y;

32791

+

32792

+__attribute__((optimize (0))) void

32793

+foo (void *p, struct A x)

32794

+{

32795

+ foo (y, x);

32796

+}

32797

Index: gcc/testsuite/gcc.dg/pr60485-1.c

32798

===================================================================

32799

--- a/src/gcc/testsuite/gcc.dg/pr60485-1.c (.../tags/gcc_4_8_2_release)

32800

+++ b/src/gcc/testsuite/gcc.dg/pr60485-1.c (.../branches/gcc-4_8-branch)

32801

@@ -0,0 +1,29 @@

32802

+/* { dg-do run } */

32803

+/* { dg-options "-O2" } */

32804

+

32805

+extern void abort (void);

32806

+struct S {

32807

+ int *i[4];

32808

+ int *p1;

32809

+ int *p2;

32810

+ int *p3;

32811

+ int *p4;

32812

+};

32813

+int **b;

32814

+int main()

32815

+{

32816

+ int i = 1;

32817

+ struct S s;

32818

+ s.p3 = &i;

32819

+ int **p;

32820

+ if (b)

32821

+ p = b;

32822

+ else

32823

+ p = &s.i[2];

32824

+ p += 4;

32825

+ if (!b)

32826

+ **p = 0;

32827

+ if (i != 0)

32828

+ abort ();

32829

+ return i;

32830

+}

32831

Index: gcc/testsuite/gcc.dg/strlenopt-1f.c

32832

===================================================================

32833

--- a/src/gcc/testsuite/gcc.dg/strlenopt-1f.c (.../tags/gcc_4_8_2_release)

32834

+++ b/src/gcc/testsuite/gcc.dg/strlenopt-1f.c (.../branches/gcc-4_8-branch)

32835

@@ -6,13 +6,13 @@

32836

#include "strlenopt-1.c"

32837

32838

/* { dg-final { scan-tree-dump-times "strlen \\(" 2 "strlen" } } */

32839

-/* { dg-final { scan-tree-dump-times "__memcpy_chk \\(" 3 "strlen" } } */

32840

-/* { dg-final { scan-tree-dump-times "__strcpy_chk \\(" 1 "strlen" } } */

32841

+/* { dg-final { scan-tree-dump-times "__memcpy_chk \\(" 0 "strlen" } } */

32842

+/* { dg-final { scan-tree-dump-times "__strcpy_chk \\(" 0 "strlen" } } */

32843

/* { dg-final { scan-tree-dump-times "__strcat_chk \\(" 0 "strlen" } } */

32844

/* { dg-final { scan-tree-dump-times "strchr \\(" 0 "strlen" } } */

32845

/* { dg-final { scan-tree-dump-times "__stpcpy_chk \\(" 0 "strlen" } } */

32846

-/* { dg-final { scan-tree-dump-times "memcpy \\(" 0 "strlen" } } */

32847

-/* { dg-final { scan-tree-dump-times "strcpy \\(" 0 "strlen" } } */

32848

+/* { dg-final { scan-tree-dump-times "memcpy \\(" 3 "strlen" } } */

32849

+/* { dg-final { scan-tree-dump-times "strcpy \\(" 1 "strlen" } } */

32850

/* { dg-final { scan-tree-dump-times "strcat \\(" 0 "strlen" } } */

32851

/* { dg-final { scan-tree-dump-times "stpcpy \\(" 0 "strlen" } } */

32852

/* { dg-final { cleanup-tree-dump "strlen" } } */

32853

Index: gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-slp-34.c

32854

===================================================================

32855

--- a/src/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-slp-34.c (.../tags/gcc_4_8_2_release)

32856

+++ b/src/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-slp-34.c (.../branches/gcc-4_8-branch)

32857

@@ -1,4 +1,5 @@

32858

/* { dg-require-effective-target vect_int } */

32859

+/* { dg-skip-if "cost too high" { powerpc*le-*-* } { "*" } { "" } } */

32860

32861

#include <stdarg.h>

32862

#include "../../tree-vect.h"

32863

Index: gcc/testsuite/gcc.dg/vect/pr60382.c

32864

===================================================================

32865

--- a/src/gcc/testsuite/gcc.dg/vect/pr60382.c (.../tags/gcc_4_8_2_release)

32866

+++ b/src/gcc/testsuite/gcc.dg/vect/pr60382.c (.../branches/gcc-4_8-branch)

32867

@@ -0,0 +1,32 @@

32868

+#include "tree-vect.h"

32869

+

32870

+int a, b, c, e, f;

32871

+

32872

+void

32873

+foo ()

32874

+{

32875

+ for (b = 0; b < 3; b++)

32876

+ if (e)

32877

+ {

32878

+ for (c = 0; c < 4; c++)

32879

+ {

32880

+ if (b)

32881

+ continue;

32882

+ f = 1;

32883

+ for (a = 0; a < 2; a++)

32884

+ f |= 1;

32885

+ }

32886

+ for (;;)

32887

+ ;

32888

+ }

32889

+}

32890

+

32891

+int

32892

+main ()

32893

+{

32894

+ check_vect ();

32895

+ foo ();

32896

+ return 0;

32897

+}

32898

+

32899

+/* { dg-final { cleanup-tree-dump "vect" } } */

32900

Index: gcc/testsuite/gcc.dg/vect/pr60276.c

32901

===================================================================

32902

--- a/src/gcc/testsuite/gcc.dg/vect/pr60276.c (.../tags/gcc_4_8_2_release)

32903

+++ b/src/gcc/testsuite/gcc.dg/vect/pr60276.c (.../branches/gcc-4_8-branch)

32904

@@ -0,0 +1,52 @@

32905

+/* { dg-do run } */

32906

+

32907

+extern void abort (void);

32908

+

32909

+static void

32910

+foo (int *out, const int *lp, unsigned samples)

32911

+{

32912

+ int x, target;

32913

+ for (x = 0, target = 0; x < (int)samples; x += 2, target++)

32914

+ {

32915

+ out[x] = lp[target];

32916

+ out[x - 1] = out[x - 2] + out[x];

32917

+ }

32918

+}

32919

+

32920

+static void

32921

+foo_novec (int *out, const int *lp, unsigned samples)

32922

+{

32923

+ int x, target;

32924

+ for (x = 0, target = 0; x < (int)samples; x += 2, target++)

32925

+ {

32926

+ out[x] = lp[target];

32927

+ out[x - 1] = out[x - 2] + out[x];

32928

+ __asm__ volatile ("" : : : "memory");

32929

+ }

32930

+}

32931

+

32932

+int main(void)

32933

+{

32934

+ const int lp[25] = {

32935

+ 0, 2, 4, 6, 8,

32936

+ 10, 12, 14, 16,

32937

+ 18, 20, 22, 24,

32938

+ 26, 28, 30, 32,

32939

+ 34, 36, 38, 40,

32940

+ 42, 44, 46, 48,

32941

+ };

32942

+ int out[49] = {0};

32943

+ int out2[49] = {0};

32944

+ int s;

32945

+

32946

+ foo (out + 2, lp + 1, 48);

32947

+ foo_novec (out2 + 2, lp + 1, 48);

32948

+

32949

+ for (s = 0; s < 49; s++)

32950

+ if (out[s] != out2[s])

32951

+ abort ();

32952

+

32953

+ return 0;

32954

+}

32955

+

32956

+/* { dg-final { cleanup-tree-dump "vect" } } */

32957

Index: gcc/testsuite/gcc.dg/pr53060.c

32958

===================================================================

32959

--- a/src/gcc/testsuite/gcc.dg/pr53060.c (.../tags/gcc_4_8_2_release)

32960

+++ b/src/gcc/testsuite/gcc.dg/pr53060.c (.../branches/gcc-4_8-branch)

32961

@@ -25,3 +25,4 @@

32962

32963

/* Ignore a warning that is irrelevant to the purpose of this test. */

32964

/* { dg-prune-output ".*GCC vector returned by reference.*" } */

32965

+/* { dg-prune-output "changes the ABI" } */

32966

Index: gcc/testsuite/ChangeLog

32967

===================================================================

32968

--- a/src/gcc/testsuite/ChangeLog (.../tags/gcc_4_8_2_release)

32969

+++ b/src/gcc/testsuite/ChangeLog (.../branches/gcc-4_8-branch)

32970

@@ -1,3 +1,1827 @@

32971

+2014-05-07 Richard Biener <rguenther@suse.de>

32972

+

32973

+ PR tree-optimization/57864

32974

+ * gcc.dg/torture/pr57864.c: New testcase.

32975

+

32976

+2014-05-06 Richard Biener <rguenther@suse.de>

32977

+

32978

+ Backport from mainline

32979

+ 2014-04-14 Richard Biener <rguenther@suse.de>

32980

+

32981

+ PR middle-end/55022

32982

+ * gcc.dg/graphite/pr55022.c: New testcase.

32983

+

32984

+2014-05-06 Richard Biener <rguenther@suse.de>

32985

+

32986

+ Backport from mainline

32987

+ 2014-04-17 Richard Biener <rguenther@suse.de>

32988

+

32989

+ PR middle-end/60849

32990

+ * g++.dg/opt/pr60849.C: New testcase.

32991

+

32992

+ 2014-04-07 Richard Biener <rguenther@suse.de>

32993

+

32994

+ PR tree-optimization/60766

32995

+ * gcc.dg/torture/pr60766.c: New testcase.

32996

+

32997

+ 2014-04-23 Richard Biener <rguenther@suse.de>

32998

+

32999

+ PR tree-optimization/60903

33000

+ * gcc.dg/torture/pr60903.c: New testcase.

33001

+

33002

+2014-05-05 Richard Biener <rguenther@suse.de>

33003

+

33004

+ Backport from mainline

33005

+ 2014-04-23 Richard Biener <rguenther@suse.de>

33006

+

33007

+ PR middle-end/60895

33008

+ * g++.dg/torture/pr60895.C: New testcase.

33009

+

33010

+ 2014-04-07 Richard Biener <rguenther@suse.de>

33011

+

33012

+ PR middle-end/60750

33013

+ * g++.dg/torture/pr60750.C: New testcase.

33014

+ * gcc.dg/tree-ssa/20040517-1.c: Adjust.

33015

+

33016

+ 2014-04-14 Richard Biener <rguenther@suse.de>

33017

+

33018

+ PR tree-optimization/59817

33019

+ PR tree-optimization/60453

33020

+ * gfortran.dg/graphite/pr59817.f: New testcase.

33021

+ * gcc.dg/graphite/pr59817-1.c: Likewise.

33022

+ * gcc.dg/graphite/pr59817-2.c: Likewise.

33023

+

33024

+ 2014-04-17 Richard Biener <rguenther@suse.de>

33025

+

33026

+ PR tree-optimization/60836

33027

+ * g++.dg/vect/pr60836.cc: New testcase.

33028

+

33029

+2014-05-05 Jakub Jelinek <jakub@redhat.com>

33030

+

33031

+ Backported from mainline

33032

+ 2014-04-25 Jakub Jelinek <jakub@redhat.com>

33033

+

33034

+ PR tree-optimization/60960

33035

+ * gcc.c-torture/execute/pr60960.c: New test.

33036

+

33037

+2014-05-04 Peter Bergner <bergner@vnet.ibm.com>

33038

+

33039

+ * gcc.target/powerpc/pack02.c (dg-options): Add -mhard-float.

33040

+ (dg-require-effective-target): Change target to powerpc_fprs.

33041

+ * gcc.target/powerpc/pack03.c (dg-options): Add -mhard-dfp.

33042

+ (dg-require-effective-target): Change target to dfprt.

33043

+

33044

+2014-05-02 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33045

+

33046

+ PR tree-optimization/60930

33047

+ * gcc.dg/torture/pr60930.c: New test.

33048

+

33049

+2014-04-30 Michael Meissner <meissner@linux.vnet.ibm.com>

33050

+

33051

+ Back port from mainline

33052

+ 2014-04-24 Michael Meissner <meissner@linux.vnet.ibm.com>

33053

+

33054

+ * gcc.target/powerpc/pack01.c: New test to test the new pack and

33055

+ unpack builtin functionss for 128-bit types.

33056

+ * gcc.target/powerpc/pack02.c: Likewise.

33057

+ * gcc.target/powerpc/pack03.c: Likewise.

33058

+ * gcc.target/powerpc/extend-divide-1.c: New test to test extended

33059

+ divide builtin functionss.

33060

+ * gcc.target/powerpc/extend-divide-2.c: Likewise.

33061

+ * gcc.target/powerpc/bcd-1.c: New test for the new BCD builtin

33062

+ functions.

33063

+ * gcc.target/powerpc/bcd-2.c: Likewise.

33064

+ * gcc.target/powerpc/bcd-3.c: Likewise.

33065

+ * gcc.target/powerpc/dfp-builtin-1.c: New test for the new DFP

33066

+ builtin functionss.

33067

+ * gcc.target/powerpc/dfp-builtin-2.c: Likewise.

33068

+

33069

+2014-04-29 Pat Haugen <pthaugen@us.ibm.com>

33070

+

33071

+ Backport from mainline

33072

+ 2014-04-17 Pat Haugen <pthaugen@us.ibm.com>

33073

+

33074

+ * gcc.target/powerpc/ti_math1.c: New.

33075

+ * gcc.target/powerpc/ti_math2.c: New.

33076

+

33077

+2014-04-25 Eric Botcazou <ebotcazou@adacore.com>

33078

+

33079

+ * gcc.c-torture/execute/20140425-1.c: New test.

33080

+

33081

+2014-04-23 Michael Meissner <meissner@linux.vnet.ibm.com>

33082

+

33083

+ Back port from main line:

33084

+ 2014-03-27 Michael Meissner <meissner@linux.vnet.ibm.com>

33085

+

33086

+ * gcc.target/powerpc/p8vector-vbpermq.c: New test to test the

33087

+ vbpermq builtin.

33088

+

33089

+2014-04-23 Uros Bizjak <ubizjak@gmail.com>

33090

+

33091

+ Backport from mainline

33092

+ 2014-04-21 Uros Bizjak <ubizjak@gmail.com>

33093

+

33094

+ PR target/60909

33095

+ * gcc.target/i386/pr60909-1.c: New test.

33096

+ * gcc.target/i386/pr60909-2.c: Ditto.

33097

+

33098

+2014-04-23 Richard Biener <rguenther@suse.de>

33099

+

33100

+ Backport from mainline

33101

+ 2014-04-02 Richard Biener <rguenther@suse.de>

33102

+

33103

+ PR middle-end/60729

33104

+ * g++.dg/vect/pr60729.cc: New testcase.

33105

+

33106

+ 2014-04-03 Richard Biener <rguenther@suse.de>

33107

+

33108

+ PR tree-optimization/60740

33109

+ * gcc.dg/graphite/pr60740.c: New testcase.

33110

+

33111

+2014-04-23 Richard Biener <rguenther@suse.de>

33112

+

33113

+ PR middle-end/60635

33114

+ * gfortran.dg/lto/pr60635_0.f90: New testcase.

33115

+ * gfortran.dg/lto/pr60635_1.c: Likewise.

33116

+

33117

+2014-04-21 Michael Meissner <meissner@linux.vnet.ibm.com>

33118

+

33119

+ Back port from the trunk, subversion id 209546.

33120

+

33121

+ 2014-04-21 Michael Meissner <meissner@linux.vnet.ibm.com>

33122

+

33123

+ PR target/60735

33124

+ * gcc.target/powerpc/pr60735.c: New test. Insure _Decimal64 does

33125

+ not cause errors if -mspe.

33126

+

33127

+2014-04-17 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33128

+

33129

+ * gcc.dg/vmx/merge-vsx.c: Add V4SI and V4SF tests.

33130

+ * gcc.dg/vmx/merge-vsx-be-order.c: Likewise.

33131

+

33132

+2014-04-12 Jerry DeLisle <jvdelisle@gcc.gnu>

33133

+

33134

+ Backport from mainline

33135

+ PR libfortran/60810

33136

+ gfortran.dg/arrayio_13.f90: New test.

33137

+

33138

+2014-04-11 Hans-Peter Nilsson <hp@axis.com>

33139

+

33140

+ * gfortran.dg/fmt_en.f90: Gate test on effective_target

33141

+ fd_truncate.

33142

+

33143

+2014-04-11 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>

33144

+

33145

+ * gcc.target/s390/htm-nofloat-1.c: Rename to ...

33146

+ * gcc.target/s390/htm-nofloat-compile-1.c: ... this one.

33147

+ * gcc.target/s390/htm-nofloat-2.c: Add check for htm target and

33148

+ rename to ...

33149

+ * gcc.target/s390/htm-nofloat-1.c: ... this one.

33150

+ * gcc.target/s390/s390.exp: Make sure the assembler supports htm

33151

+ instructions as well.

33152

+

33153

+2014-04-11 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>

33154

+

33155

+ * gcc.target/s390/htm-builtins-compile-1.c: Replace long long with

33156

+ long.

33157

+

33158

+2014-04-11 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>

33159

+

33160

+ * gcc.target/s390/htm-builtins-compile-1.c: Remove htm check.

33161

+ * gcc.target/s390/htm-builtins-compile-2.c: Remove htm check.

33162

+

33163

+2014-04-10 Vladimir Makarov <vmakarov@redhat.com>

33164

+

33165

+ PR rtl-optimization/60769

33166

+ * g++.dg/pr60769.C: New.

33167

+

33168

+2014-04-10 Jakub Jelinek <jakub@redhat.com>

33169

+

33170

+ Backport from mainline

33171

+ 2014-03-12 Jakub Jelinek <jakub@redhat.com>

33172

+ Marc Glisse <marc.glisse@inria.fr>

33173

+

33174

+ PR tree-optimization/60502

33175

+ * gcc.c-torture/compile/pr60502.c: New test.

33176

+

33177

+ 2014-03-28 Jakub Jelinek <jakub@redhat.com>

33178

+

33179

+ PR target/60693

33180

+ * gcc.target/i386/pr60693.c: New test.

33181

+

33182

+ PR c++/60689

33183

+ * c-c++-common/pr60689.c: New test.

33184

+

33185

+ 2014-03-22 Jakub Jelinek <jakub@redhat.com>

33186

+

33187

+ PR debug/60603

33188

+ * gcc.dg/debug/dwarf2/dwarf2-macro2.c: New test.

33189

+

33190

+ 2014-03-17 Jakub Jelinek <jakub@redhat.com>

33191

+

33192

+ PR target/60516

33193

+ * gcc.target/i386/pr60516.c: New test.

33194

+

33195

+ 2014-03-13 Jakub Jelinek <jakub@redhat.com>

33196

+

33197

+ PR middle-end/36282

33198

+ * c-c++-common/pr36282-1.c: New test.

33199

+ * c-c++-common/pr36282-2.c: New test.

33200

+ * c-c++-common/pr36282-3.c: New test.

33201

+ * c-c++-common/pr36282-4.c: New test.

33202

+

33203

+ 2014-03-06 Jakub Jelinek <jakub@redhat.com>

33204

+

33205

+ PR target/58595

33206

+ * gcc.dg/tls/pr58595.c: New test.

33207

+

33208

+2014-04-07 Martin Jambor <mjambor@suse.cz>

33209

+

33210

+ PR ipa/60640

33211

+ * g++.dg/ipa/pr60640-1.C: New test.

33212

+ * g++.dg/ipa/pr60640-2.C: Likewise.

33213

+ * g++.dg/ipa/pr60640-3.C: Likewise.

33214

+

33215

+2014-04-06 Dominique d'Humieres <dominiq@lps.ens.fr>

33216

+ Iain Sandoe <iain@codesourcery.com>

33217

+

33218

+ PR target/54083

33219

+ * gcc.dg/attr-weakref-1.c: Allow the test on darwin with

33220

+ the additional options -Wl,-undefined,dynamic_lookup and

33221

+ -Wl,-flat_namespace

33222

+ * gcc.dg/torture/pr53922.c: Additional option

33223

+ -Wl,-flat_namespace for darwin[89].

33224

+

33225

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33226

+

33227

+ Backport from mainline

33228

+ 2013-04-05 David Edelsohn <dje.gcc@gmail.com>

33229

+

33230

+ * gcc.target/powerpc/sd-vsx.c: Skip on AIX.

33231

+ * gcc.target/powerpc/sd-pwr6.c: Same.

33232

+

33233

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33234

+

33235

+ Back port from trunk

33236

+ 2014-03-12 Michael Meissner <meissner@linux.vnet.ibm.com>

33237

+

33238

+ * gcc.target/powerpc/p8vector-int128-1.c: New test to test ISA

33239

+ 2.07 128-bit arithmetic.

33240

+ * gcc.target/powerpc/p8vector-int128-2.c: Likewise.

33241

+

33242

+ * gcc.target/powerpc/timode_off.c: Restrict cpu type to power5,

33243

+ due to when TImode is allowed in VSX registers, the allowable

33244

+ address modes for TImode is just a single indirect address in

33245

+ order for the value to be loaded and store in either GPR or VSX

33246

+ registers. This affects the generated code, and it would cause

33247

+ this test to fail, when such an option is used.

33248

+

33249

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33250

+

33251

+ Backport from mainline r207699.

33252

+ 2014-02-11 Michael Meissner <meissner@linux.vnet.ibm.com>

33253

+

33254

+ PR target/60137

33255

+ * gcc.target/powerpc/pr60137.c: New file.

33256

+

33257

+ Backport from mainline r207808.

33258

+ 2014-02-15 Michael Meissner <meissner@linux.vnet.ibm.com>

33259

+

33260

+ PR target/60203

33261

+ * gcc.target/powerpc/pr60203.c: New testsuite.

33262

+

33263

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33264

+

33265

+ Little Endian Vector API Support

33266

+ Backport from mainline r206590

33267

+ 2014-01-13 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33268

+

33269

+ * gcc.dg/vmx/insert.c: New.

33270

+ * gcc.dg/vmx/insert-be-order.c: New.

33271

+ * gcc.dg/vmx/extract.c: New.

33272

+ * gcc.dg/vmx/extract-be-order.c: New.

33273

+

33274

+ Backport from mainline r206641

33275

+ 2014-01-15 Bill Schmidt <wschmidt@vnet.linux.ibm.com>

33276

+

33277

+ * gcc.dg/vmx/mult-even-odd.c: New.

33278

+ * gcc.dg/vmx/mult-even-odd-be-order.c: New.

33279

+

33280

+ Backport from mainline r206926

33281

+ 2014-01-22 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33282

+

33283

+ * gcc.dg/vmx/insert-vsx-be-order.c: New.

33284

+ * gcc.dg/vmx/extract-vsx.c: New.

33285

+ * gcc.dg/vmx/extract-vsx-be-order.c: New.

33286

+ * gcc.dg/vmx/insert-vsx.c: New.

33287

+

33288

+ Backport from mainline r207262

33289

+ 2014-01-29 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33290

+

33291

+ * gcc.dg/vmx/merge-be-order.c: New.

33292

+ * gcc.dg/vmx/merge.c: New.

33293

+ * gcc.dg/vmx/merge-vsx-be-order.c: New.

33294

+ * gcc.dg/vmx/merge-vsx.c: New.

33295

+

33296

+ Backport from mainline r207318

33297

+ 2014-01-30 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33298

+

33299

+ * gcc.dg/vmx/splat.c: New.

33300

+ * gcc.dg/vmx/splat-vsx.c: New.

33301

+ * gcc.dg/vmx/splat-be-order.c: New.

33302

+ * gcc.dg/vmx/splat-vsx-be-order.c: New.

33303

+ * gcc.dg/vmx/eg-5.c: Remove special casing for little endian.

33304

+ * gcc.dg/vmx/sn7153.c: Add special casing for little endian.

33305

+

33306

+ Backport from mainline r207414

33307

+ 2014-02-02 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33308

+

33309

+ * gcc.dg/vmx/vsums.c: New.

33310

+ * gcc.dg/vmx/vsums-be-order.c: New.

33311

+

33312

+ Backport from mainline r207415

33313

+ 2014-02-02 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33314

+

33315

+ * gcc.dg/vmx/3b-15.c: Remove special handling for little endian.

33316

+ * gcc.dg/vmx/perm.c: New.

33317

+ * gcc.dg/vmx/perm-be-order.c: New.

33318

+

33319

+ Backport from mainline r207520

33320

+ 2014-02-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33321

+

33322

+ * gcc.dg/vmx/pack.c: New.

33323

+ * gcc.dg/vmx/pack-be-order.c: New.

33324

+ * gcc.dg/vmx/unpack.c: New.

33325

+ * gcc.dg/vmx/unpack-be-order.c: New.

33326

+

33327

+ Backport from mainline r207521

33328

+ 2014-02-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33329

+

33330

+ * gcc.dg/vmx/sum2s.c: New.

33331

+ * gcc.dg/vmx/sum2s-be-order.c: New.

33332

+

33333

+ Backport from mainline 208019

33334

+ 2014-02-21 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33335

+

33336

+ * gcc.dg/vmx/ld.c: New test.

33337

+ * gcc.dg/vmx/ld-be-order.c: New test.

33338

+ * gcc.dg/vmx/ld-vsx.c: New test.

33339

+ * gcc.dg/vmx/ld-vsx-be-order.c: New test.

33340

+ * gcc.dg/vmx/ldl.c: New test.

33341

+ * gcc.dg/vmx/ldl-be-order.c: New test.

33342

+ * gcc.dg/vmx/ldl-vsx.c: New test.

33343

+ * gcc.dg/vmx/ldl-vsx-be-order.c: New test.

33344

+ * gcc.dg/vmx/st.c: New test.

33345

+ * gcc.dg/vmx/st-be-order.c: New test.

33346

+ * gcc.dg/vmx/st-vsx.c: New test.

33347

+ * gcc.dg/vmx/st-vsx-be-order.c: New test.

33348

+ * gcc.dg/vmx/stl.c: New test.

33349

+ * gcc.dg/vmx/stl-be-order.c: New test.

33350

+ * gcc.dg/vmx/stl-vsx.c: New test.

33351

+ * gcc.dg/vmx/stl-vsx-be-order.c: New test.

33352

+

33353

+ Backport from mainline 208021

33354

+ 2014-02-21 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33355

+

33356

+ * gcc.dg/vmx/vsums.c: Check entire result vector.

33357

+ * gcc.dg/vmx/vsums-be-order.c: Likewise.

33358

+

33359

+ Backport from mainline 208049

33360

+ 2014-02-23 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33361

+

33362

+ * gcc.dg/vmx/lde.c: New test.

33363

+ * gcc.dg/vmx/lde-be-order.c: New test.

33364

+ * gcc.dg/vmx/ste.c: New test.

33365

+ * gcc.dg/vmx/ste-be-order.c: New test.

33366

+

33367

+ Backport from mainline 208120

33368

+ 2014-02-25 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33369

+

33370

+ * gcc.dg/vmx/ld-vsx.c: Don't use vec_all_eq.

33371

+ * gcc.dg/vmx/ld-vsx-be-order.c: Likewise.

33372

+ * gcc.dg/vmx/ldl-vsx.c: Likewise.

33373

+ * gcc.dg/vmx/ldl-vsx-be-order.c: Likewise.

33374

+ * gcc.dg/vmx/merge-vsx.c: Likewise.

33375

+ * gcc.dg/vmx/merge-vsx-be-order.c: Likewise.

33376

+

33377

+ Backport from mainline 208321

33378

+ 2014-03-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33379

+

33380

+ * gcc.dg/vmx/extract-vsx.c: Replace "vector long" with "vector

33381

+ long long" throughout.

33382

+ * gcc.dg/vmx/extract-vsx-be-order.c: Likewise.

33383

+ * gcc.dg/vmx/insert-vsx.c: Likewise.

33384

+ * gcc.dg/vmx/insert-vsx-be-order.c: Likewise.

33385

+ * gcc.dg/vmx/ld-vsx.c: Likewise.

33386

+ * gcc.dg/vmx/ld-vsx-be-order.c: Likewise.

33387

+ * gcc.dg/vmx/ldl-vsx.c: Likewise.

33388

+ * gcc.dg/vmx/ldl-vsx-be-order.c: Likewise.

33389

+ * gcc.dg/vmx/merge-vsx.c: Likewise.

33390

+ * gcc.dg/vmx/merge-vsx-be-order.c: Likewise.

33391

+ * gcc.dg/vmx/st-vsx.c: Likewise.

33392

+ * gcc.dg/vmx/st-vsx-be-order.c: Likewise.

33393

+ * gcc.dg/vmx/stl-vsx.c: Likewise.

33394

+ * gcc.dg/vmx/stl-vsx-be-order.c: Likewise.

33395

+

33396

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33397

+

33398

+ Back port from mainline

33399

+ 2014-01-23 Michael Meissner <meissner@linux.vnet.ibm.com>

33400

+

33401

+ PR target/59909

33402

+ * gcc.target/powerpc/quad-atomic.c: New file to test power8 quad

33403

+ word atomic functions at runtime.

33404

+

33405

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33406

+

33407

+ Backport from mainline

33408

+ 2013-10-23 Pat Haugen <pthaugen@us.ibm.com>

33409

+

33410

+ * gcc.target/powerpc/direct-move.h: Fix header for executable tests.

33411

+

33412

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33413

+

33414

+ Backport from mainline

33415

+ 2013-04-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33416

+

33417

+ PR target/56843

33418

+ * gcc.target/powerpc/recip-1.c: Modify expected output.

33419

+ * gcc.target/powerpc/recip-3.c: Likewise.

33420

+ * gcc.target/powerpc/recip-4.c: Likewise.

33421

+ * gcc.target/powerpc/recip-5.c: Add expected output for iterations.

33422

+

33423

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33424

+

33425

+ Backport from mainline

33426

+ 2013-08-19 Peter Bergner <bergner@vnet.ibm.com>

33427

+

33428

+ * gcc.target/powerpc/dfp-dd-2.c: New test.

33429

+ * gcc.target/powerpc/dfp-td-2.c: Likewise.

33430

+ * gcc.target/powerpc/dfp-td-3.c: Likewise.

33431

+

33432

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33433

+

33434

+ ELFv2 ABI Support

33435

+ Backport from mainline r204808:

33436

+

33437

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

33438

+

33439

+ * gcc.target/powerpc/ppc64-abi-1.c (stack_frame_t): Remove

33440

+ compiler and linker field if _CALL_ELF == 2.

33441

+ * gcc.target/powerpc/ppc64-abi-2.c (stack_frame_t): Likewise.

33442

+ * gcc.target/powerpc/ppc64-abi-dfp-1.c (stack_frame_t): Likewise.

33443

+ * gcc.dg/stack-usage-1.c (SIZE): Update value for _CALL_ELF == 2.

33444

+

33445

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

33446

+

33447

+ * gcc.target/powerpc/ppc64-abi-dfp-1.c (FUNC_START): New macro.

33448

+ (WRAPPER): Use it.

33449

+ * gcc.target/powerpc/no-r11-1.c: Skip on powerpc_elfv2.

33450

+ * gcc.target/powerpc/no-r11-2.c: Skip on powerpc_elfv2.

33451

+ * gcc.target/powerpc/no-r11-3.c: Skip on powerpc_elfv2.

33452

+

33453

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

33454

+

33455

+ * lib/target-supports.exp (check_effective_target_powerpc_elfv2):

33456

+ New function.

33457

+ * gcc.target/powerpc/pr57949-1.c: Disable for powerpc_elfv2.

33458

+ * gcc.target/powerpc/pr57949-2.c: Likewise.

33459

+

33460

+ Backport from mainline r204799:

33461

+

33462

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

33463

+

33464

+ * g++.dg/eh/ppc64-sighandle-cr.C: New test.

33465

+

33466

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33467

+

33468

+ Backport from mainline r201750.

33469

+ Note: Default setting of -mcompat-align-parm inverted!

33470

+

33471

+ 2013-08-14 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33472

+

33473

+ PR target/57949

33474

+ * gcc.target/powerpc/pr57949-1.c: New.

33475

+ * gcc.target/powerpc/pr57949-2.c: New.

33476

+

33477

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33478

+

33479

+ Little Endian Vector Support

33480

+ Backport from mainline r205638

33481

+ 2013-12-03 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33482

+

33483

+ * gcc.dg/vect/costmodel/ppc/costmodel-slp-34.c: Skip for little

33484

+ endian.

33485

+

33486

+ Backport from mainline r205146

33487

+ 2013-11-20 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33488

+

33489

+ * gcc.target/powerpc/pr48258-1.c: Skip for little endian.

33490

+

33491

+ Backport from mainline r204862

33492

+ 2013-11-15 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33493

+

33494

+ * gcc.dg/vmx/3b-15.c: Revise for little endian.

33495

+

33496

+ Backport from mainline r204321

33497

+ 2013-11-02 Bill Schmidt <wschmidt@vnet.linux.ibm.com>

33498

+

33499

+ * gcc.dg/vmx/vec-set.c: New.

33500

+

33501

+ Backport from mainline r204138

33502

+ 2013-10-28 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33503

+

33504

+ * gcc.dg/vmx/gcc-bug-i.c: Add little endian variant.

33505

+ * gcc.dg/vmx/eg-5.c: Likewise.

33506

+

33507

+ Backport from mainline r203930

33508

+ 2013-10-22 Bill Schmidt <wschmidt@vnet.ibm.com>

33509

+

33510

+ * gcc.target/powerpc/altivec-perm-1.c: Move the two vector pack

33511

+ tests into...

33512

+ * gcc.target/powerpc/altivec-perm-3.c: ...this new test, which is

33513

+ restricted to big-endian targets.

33514

+

33515

+ Backport from mainline r203246

33516

+ 2013-10-07 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33517

+

33518

+ * gcc.target/powerpc/pr43154.c: Skip for ppc64 little endian.

33519

+ * gcc.target/powerpc/fusion.c: Likewise.

33520

+

33521

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33522

+

33523

+ Backport from mainline

33524

+ 2013-11-27 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33525

+

33526

+ * gfortran.dg/nan_7.f90: Disable for little endian PowerPC.

33527

+

33528

+ Backport from mainline r205106:

33529

+

33530

+ 2013-11-20 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

33531

+

33532

+ * gcc.target/powerpc/darwin-longlong.c (msw): Make endian-safe.

33533

+

33534

+ Backport from mainline r205046:

33535

+

33536

+ 2013-11-19 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

33537

+

33538

+ * gcc.target/powerpc/ppc64-abi-2.c (MAKE_SLOT): New macro to

33539

+ construct parameter slot value in endian-independent way.

33540

+ (fcevv, fciievv, fcvevv): Use it.

33541

+

33542

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33543

+

33544

+ Power8 HTM Support

33545

+ Backport from mainline

33546

+ * lib/target-supports.exp (check_effective_target_powerpc_htm_ok): New

33547

+ function to test if HTM is available.

33548

+ * gcc.target/powerpc/htm-xl-intrin-1.c: New test.

33549

+ * gcc.target/powerpc/htm-builtin-1.c: New test.

33550

+

33551

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33552

+

33553

+ Power8 Base Support

33554

+ Backport from mainline

33555

+ 2013-11-22 Michael Meissner <meissner@linux.vnet.ibm.com>

33556

+

33557

+ PR target/59054

33558

+ * gcc.target/powerpc/direct-move.h (VSX_REG_ATTR): Allow test to

33559

+ specify an appropriate register class for VSX operations.

33560

+ (load_vsx): Use it.

33561

+ (load_gpr_to_vsx): Likewise.

33562

+ (load_vsx_to_gpr): Likewise.

33563

+ * gcc.target/powerpc/direct-move-vint1.c: Use an appropriate

33564

+ register class for VSX registers that the type can handle. Remove

33565

+ checks for explicit number of instructions generated, just check

33566

+ if the instruction is generated.

33567

+ * gcc.target/powerpc/direct-move-vint2.c: Likewise.

33568

+ * gcc.target/powerpc/direct-move-float1.c: Likewise.

33569

+ * gcc.target/powerpc/direct-move-float2.c: Likewise.

33570

+ * gcc.target/powerpc/direct-move-double1.c: Likewise.

33571

+ * gcc.target/powerpc/direct-move-double2.c: Likewise.

33572

+ * gcc.target/powerpc/direct-move-long1.c: Likewise.

33573

+ * gcc.target/powerpc/direct-move-long2.c: Likewise.

33574

+

33575

+ * gcc.target/powerpc/bool3-av.c: Limit to 64-bit mode for now.

33576

+ * gcc.target/powerpc/bool3-p7.c: Likewise.

33577

+ * gcc.target/powerpc/bool3-p8.c: Likewise.

33578

+

33579

+ * gcc.target/powerpc/p8vector-ldst.c: Just check that the

33580

+ appropriate instructions are generated, don't check the count.

33581

+

33582

+ 2013-11-12 Michael Meissner <meissner@linux.vnet.ibm.com>

33583

+

33584

+ PR target/59054

33585

+ * gcc.target/powerpc/pr59054.c: New test.

33586

+

33587

+ 2013-08-22 Michael Meissner <meissner@linux.vnet.ibm.com>

33588

+

33589

+ * gcc.target/powerpc/pr57744.c: Declare abort.

33590

+

33591

+ 2013-07-18 Pat Haugen <pthaugen@us.ibm.com>

33592

+

33593

+ * gcc.target/powerpc/pr57744.c: Fix typo.

33594

+

33595

+ Back port from mainline

33596

+ 2013-10-03 Michael Meissner <meissner@linux.vnet.ibm.com>

33597

+

33598

+ * gcc.target/powerpc/p8vector-fp.c: New test for floating point

33599

+ scalar operations when using -mupper-regs-sf and -mupper-regs-df.

33600

+ * gcc.target/powerpc/ppc-target-1.c: Update tests to allow either

33601

+ VSX scalar operations or the traditional floating point form of

33602

+ the instruction.

33603

+ * gcc.target/powerpc/ppc-target-2.c: Likewise.

33604

+ * gcc.target/powerpc/recip-3.c: Likewise.

33605

+ * gcc.target/powerpc/recip-5.c: Likewise.

33606

+ * gcc.target/powerpc/pr72747.c: Likewise.

33607

+ * gcc.target/powerpc/vsx-builtin-3.c: Likewise.

33608

+

33609

+ Back port from mainline

33610

+ 2013-09-27 Michael Meissner <meissner@linux.vnet.ibm.com>

33611

+

33612

+ * gcc.target/powerpc/p8vector-ldst.c: New test for -mupper-regs-sf

33613

+ and -mupper-regs-df.

33614

+

33615

+ Back port from mainline

33616

+ 2013-10-17 Michael Meissner <meissner@linux.vnet.ibm.com>

33617

+

33618

+ PR target/58673

33619

+ * gcc.target/powerpc/pr58673-1.c: New file to test whether

33620

+ -mquad-word + -mno-vsx-timode causes errors.

33621

+ * gcc.target/powerpc/pr58673-2.c: Likewise.

33622

+

33623

+

33624

+ Backport from trunk.

33625

+ 2013-07-23 Michael Meissner <meissner@linux.vnet.ibm.com>

33626

+

33627

+ * gcc.target/powerpc/bool2.h: New file, test the code generation

33628

+ of logical operations for power5, altivec, power7, and power8 systems.

33629

+ * gcc.target/powerpc/bool2-p5.c: Likewise.

33630

+ * gcc.target/powerpc/bool2-av.c: Likewise.

33631

+ * gcc.target/powerpc/bool2-p7.c: Likewise.

33632

+ * gcc.target/powerpc/bool2-p8.c: Likewise.

33633

+ * gcc.target/powerpc/bool3.h: Likewise.

33634

+ * gcc.target/powerpc/bool3-av.c: Likewise.

33635

+ * gcc.target/powerpc/bool2-p7.c: Likewise.

33636

+ * gcc.target/powerpc/bool2-p8.c: Likewise.

33637

+

33638

+ Backport from trunk.

33639

+ 2013-07-31 Michael Meissner <meissner@linux.vnet.ibm.com>

33640

+

33641

+ * gcc.target/powerpc/fusion.c: New file, test power8 fusion support.

33642

+

33643

+ Back port from the trunk

33644

+ 2013-06-28 Michael Meissner <meissner@linux.vnet.ibm.com>

33645

+

33646

+ PR target/57744

33647

+ * gcc.target/powerpc/pr57744.c: New test to make sure lqarx and

33648

+ stqcx. get even registers.

33649

+

33650

+ Back port from the trunk

33651

+

33652

+ 2013-06-12 Michael Meissner <meissner@linux.vnet.ibm.com>

33653

+ Pat Haugen <pthaugen@us.ibm.com>

33654

+ Peter Bergner <bergner@vnet.ibm.com>

33655

+

33656

+ * gcc.target/powerpc/atomic-p7.c: New file, add tests for atomic

33657

+ load/store instructions on power7, power8.

33658

+ * gcc.target/powerpc/atomic-p8.c: Likewise.

33659

+

33660

+ Back port from the trunk

33661

+

33662

+ 2013-06-10 Michael Meissner <meissner@linux.vnet.ibm.com>

33663

+ Pat Haugen <pthaugen@us.ibm.com>

33664

+ Peter Bergner <bergner@vnet.ibm.com>

33665

+

33666

+ * gcc.target/powerpc/direct-move-vint1.c: New tests for power8

33667

+ direct move instructions.

33668

+ * gcc.target/powerpc/direct-move-vint2.c: Likewise.

33669

+ * gcc.target/powerpc/direct-move.h: Likewise.

33670

+ * gcc.target/powerpc/direct-move-float1.c: Likewise.

33671

+ * gcc.target/powerpc/direct-move-float2.c: Likewise.

33672

+ * gcc.target/powerpc/direct-move-double1.c: Likewise.

33673

+ * gcc.target/powerpc/direct-move-double2.c: Likewise.

33674

+ * gcc.target/powerpc/direct-move-long1.c: Likewise.

33675

+ * gcc.target/powerpc/direct-move-long2.c: Likewise.

33676

+

33677

+ Backport from the trunk

33678

+

33679

+ 2013-06-06 Michael Meissner <meissner@linux.vnet.ibm.com>

33680

+ Pat Haugen <pthaugen@us.ibm.com>

33681

+ Peter Bergner <bergner@vnet.ibm.com>

33682

+

33683

+ * gcc.target/powerpc/p8vector-builtin-1.c: New test to test

33684

+ power8 builtin functions.

33685

+ * gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c: Likewise.

33686

+ * gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c: Likewise.

33687

+ * gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c: Likewise.

33688

+ * gcc/testsuite/gcc.target/powerpc/p8vector-builtin-5.c: Likewise.

33689

+ * gcc/testsuite/gcc.target/powerpc/p8vector-builtin-6.c: Likewise.

33690

+ * gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c: Likewise.

33691

+ * gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-1.c: New

33692

+ tests to test power8 auto-vectorization.

33693

+ * gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-2.c: Likewise.

33694

+ * gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-3.c: Likewise.

33695

+ * gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-4.c: Likewise.

33696

+ * gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-5.c: Likewise.

33697

+

33698

+ * gcc.target/powerpc/crypto-builtin-1.c: Use effective target

33699

+ powerpc_p8vector_ok instead of powerpc_vsx_ok.

33700

+

33701

+ * gcc.target/powerpc/bool.c: New file, add eqv, nand, nor tests.

33702

+

33703

+ * lib/target-supports.exp (check_p8vector_hw_available) Add power8

33704

+ support.

33705

+ (check_effective_target_powerpc_p8vector_ok): Likewise.

33706

+ (is-effective-target): Likewise.

33707

+ (check_vect_support_and_set_flags): Likewise.

33708

+

33709

+ Backport from trunk

33710

+

33711

+ 2013-05-22 Michael Meissner <meissner@linux.vnet.ibm.com>

33712

+ Pat Haugen <pthaugen@us.ibm.com>

33713

+ Peter Bergner <bergner@vnet.ibm.com>

33714

+

33715

+ * gcc.target/powerpc/crypto-builtin-1.c: New file, test for power8

33716

+ crypto builtins.

33717

+

33718

+ Backport from mainline

33719

+ 2013-03-20 Michael Meissner <meissner@linux.vnet.ibm.com>

33720

+

33721

+ * gcc.target/powerpc/mmfpgpr.c: New test.

33722

+ * gcc.target/powerpc/sd-vsx.c: Likewise.

33723

+ * gcc.target/powerpc/sd-pwr6.c: Likewise.

33724

+ * gcc.target/powerpc/vsx-float0.c: Likewise.

33725

+

33726

+2014-04-01 Dominique d'Humieres <dominiq@lps.ens.fr>

33727

+

33728

+ PR libfortran/60128

33729

+ * gfortran.dg/fmt_en.f90: Skip unsupported rounding tests.

33730

+ XFAIL for i?86-*-solaris2.9* and hppa*-*-hpux*.

33731

+

33732

+2014-03-31 H.J. Lu <hongjiu.lu@intel.com>

33733

+

33734

+ Backport from mainline

33735

+ 2014-03-31 H.J. Lu <hongjiu.lu@intel.com>

33736

+

33737

+ PR rtl-optimization/60700

33738

+ * gcc.target/i386/pr60700.c: New test.

33739

+

33740

+2014-03-28 H.J. Lu <hongjiu.lu@intel.com>

33741

+

33742

+ PR rtl-optimization/60700

33743

+ Backport from mainline

33744

+ 2013-07-30 Zhenqiang Chen <zhenqiang.chen@linaro.org>

33745

+

33746

+ * gcc.target/arm/pr57637.c: New testcase.

33747

+

33748

+2014-04-28 Thomas Koenig <tkoenig@gcc.gnu.org>

33749

+

33750

+ PR fortran/60522

33751

+ * gfortran.dg/where_4.f90: New test case.

33752

+

33753

+2014-03-26 Martin Jambor <mjambor@suse.cz>

33754

+

33755

+ PR ipa/60419

33756

+ * g++.dg/ipa/pr60419.C: New test.

33757

+

33758

+2014-03-26 Eric Botcazou <ebotcazou@adacore.com>

33759

+

33760

+ * gcc.c-torture/execute/20140326-1.c: New test.

33761

+

33762

+2014-03-20 Tobias Burnus <burnus@net-b.de>

33763

+

33764

+ PR fortran/60543

33765

+ PR fortran/60283

33766

+ * gfortran.dg/implicit_pure_4.f90: New.

33767

+

33768

+2014-03-17 Mikael Pettersson <mikpelinux@gmail.com>

33769

+ Committed by Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33770

+

33771

+ Backport from mainline:

33772

+

33773

+ 2013-06-16 Joern Rennecke <joern.rennecke@embecosm.com>

33774

+

33775

+ PR rtl-optimization/57425

33776

+ PR rtl-optimization/57569

33777

+ * gcc.dg/torture/pr57425-1.c, gcc.dg/torture/pr57425-2.c: New files.

33778

+ * gcc.dg/torture/pr57425-3.c, gcc.dg/torture/pr57569.c: Likewise.

33779

+

33780

+2014-03-17 Richard Biener <rguenther@suse.de>

33781

+

33782

+ Backport from mainline

33783

+ 2014-03-11 Richard Biener <rguenther@suse.de>

33784

+

33785

+ PR tree-optimization/60429

33786

+ PR tree-optimization/60485

33787

+ * gcc.dg/pr60485-1.c: New testcase.

33788

+ * gcc.dg/pr60485-2.c: Likewise.

33789

+

33790

+2014-03-15 Dominique d'Humieres <dominiq@lps.ens.fr>

33791

+

33792

+ Backport from mainline

33793

+ PR libfortran/60128

33794

+ * gfortran.dg/fmt_en.f90: New test.

33795

+

33796

+2014-03-15 Jerry DeLisle <jvdelisle@gcc.gnu>

33797

+

33798

+ Backport from mainline

33799

+ PR libfortran/58324

33800

+ * gfortran.dg/list_read_12.f90: New test.

33801

+

33802

+2014-03-13 Joey Ye <joey.ye@arm.com>

33803

+

33804

+ Backport from mainline

33805

+ 2014-03-12 Thomas Preud'homme <thomas.preudhomme@arm.com>

33806

+

33807

+ PR tree-optimization/60454

33808

+ * gcc.c-torture/execute/pr60454.c: New test.

33809

+

33810

+2014-03-08 Janus Weil <janus@gcc.gnu.org>

33811

+

33812

+ PR fortran/60450

33813

+ * gfortran.dg/shape_8.f90: New.

33814

+

33815

+2014-03-06 Jakub Jelinek <jakub@redhat.com>

33816

+

33817

+ Backport from mainline

33818

+ 2014-02-19 Jakub Jelinek <jakub@redhat.com>

33819

+

33820

+ PR c/37743

33821

+ * g++.dg/ext/builtin-bswap1.C: New test.

33822

+ * c-c++-common/pr37743.c: New test.

33823

+

33824

+ PR preprocessor/58844

33825

+ * c-c++-common/cpp/pr58844-1.c: New test.

33826

+ * c-c++-common/cpp/pr58844-2.c: New test.

33827

+

33828

+ 2014-02-13 Jakub Jelinek <jakub@redhat.com>

33829

+

33830

+ PR target/43546

33831

+ * gcc.target/i386/pr43546.c: New test.

33832

+

33833

+ 2014-02-12 Jakub Jelinek <jakub@redhat.com>

33834

+

33835

+ PR c/60101

33836

+ * c-c++-common/pr60101.c: New test.

33837

+

33838

+ 2014-02-11 Jakub Jelinek <jakub@redhat.com>

33839

+

33840

+ PR fortran/52370

33841

+ * gfortran.dg/pr52370.f90: New test.

33842

+

33843

+ PR debug/59776

33844

+ * gcc.dg/guality/pr59776.c: New test.

33845

+

33846

+ 2014-02-07 Jakub Jelinek <jakub@redhat.com>

33847

+

33848

+ PR preprocessor/56824

33849

+ * gcc.dg/pr56824.c: New test.

33850

+

33851

+ 2014-02-06 Jakub Jelinek <jakub@redhat.com>

33852

+

33853

+ PR target/60062

33854

+ * gcc.c-torture/execute/pr60062.c: New test.

33855

+ * gcc.c-torture/execute/pr60072.c: New test.

33856

+

33857

+ 2014-02-04 Jakub Jelinek <jakub@redhat.com>

33858

+

33859

+ PR ipa/60026

33860

+ * c-c++-common/torture/pr60026.c: New test.

33861

+

33862

+ 2014-02-05 Jakub Jelinek <jakub@redhat.com>

33863

+

33864

+ PR middle-end/57499

33865

+ * g++.dg/torture/pr57499.C: New test.

33866

+

33867

+ 2014-03-03 Jakub Jelinek <jakub@redhat.com>

33868

+

33869

+ PR preprocessor/60400

33870

+ * c-c++-common/cpp/pr60400.c: New test.

33871

+ * c-c++-common/cpp/pr60400-1.h: New file.

33872

+ * c-c++-common/cpp/pr60400-2.h: New file.

33873

+

33874

+2014-03-04 Richard Biener <rguenther@suse.de>

33875

+

33876

+ PR tree-optimization/60382

33877

+ * gcc.dg/vect/pr60382.c: New testcase.

33878

+

33879

+2014-03-02 Mikael Morin <mikael@gcc.gnu.org>

33880

+

33881

+ PR fortran/60341

33882

+ * gfortran.dg/str_comp_optimize_1.f90: New test.

33883

+

33884

+2014-02-25 Richard Biener <rguenther@suse.de>

33885

+

33886

+ Backport from mainline

33887

+ 2014-02-21 Richard Biener <rguenther@suse.de>

33888

+

33889

+ PR tree-optimization/60276

33890

+ * gcc.dg/vect/pr60276.c: New testcase.

33891

+

33892

+2014-02-25 Richard Biener <rguenther@suse.de>

33893

+

33894

+ Backport from mainline

33895

+ 2014-02-14 Richard Biener <rguenther@suse.de>

33896

+

33897

+ PR tree-optimization/60183

33898

+ * gcc.dg/torture/pr60183.c: New testcase.

33899

+

33900

+2014-02-24 Fabien Chêne <fabien@gcc.gnu.org>

33901

+

33902

+ PR c++/37140

33903

+ * g++.dg/template/using27.C: New.

33904

+ * g++.dg/template/using28.C: New.

33905

+ * g++.dg/template/using29.C: New.

33906

+

33907

+2014-02-23 David Holsgrove <david.holsgrove@xilinx.com>

33908

+

33909

+ * gcc/testsuite/gcc.target/microblaze/others/mem_reload.c: New test.

33910

+

33911

+2014-02-22 Mikael Morin <mikael@gcc.gnu.org>

33912

+

33913

+ PR fortran/59599

33914

+ * gfortran.dg/ichar_3.f90: New test.

33915

+

33916

+2014-02-21 Steven G. Kargl <kargl@gcc.gnu.org>

33917

+

33918

+ Backport from mainline

33919

+ PR fortran/59700

33920

+ * gfortran.dg/pr59700.f90: New test.

33921

+

33922

+2014-02-21 Martin Jambor <mjambor@suse.cz>

33923

+

33924

+ PR ipa/55260

33925

+ * gcc.dg/ipa/pr55260.c: New test.

33926

+

33927

+2014-02-19 Tobias Burnus <burnus@net-b.de>

33928

+

33929

+ PR fortran/49397

33930

+ * gfortran.dg/proc_ptr_45.f90: New.

33931

+ * gfortran.dg/proc_ptr_46.f90: New.

33932

+

33933

+2014-02-19 Uros Bizjak <ubizjak@gmail.com>

33934

+

33935

+ Backport from mainline

33936

+ 2014-02-19 Uros Bizjak <ubizjak@gmail.com>

33937

+

33938

+ PR target/59794

33939

+ * gcc.target/i386/pr39162.c: Add dg-prune-output.

33940

+ (dg-options): Remove -Wno-psabi.

33941

+ * gcc.target/i386/pr59794-2.c: Ditto.

33942

+ * gcc.target/i386/sse-5.c: Ditto.

33943

+

33944

+2014-02-19 Janus Weil <janus@gcc.gnu.org>

33945

+

33946

+ Backports from mainline:

33947

+ 2014-02-17 Janus Weil <janus@gcc.gnu.org>

33948

+

33949

+ PR fortran/55907

33950

+ * gfortran.dg/init_flag_12.f90: New.

33951

+

33952

+ 2014-02-18 Janus Weil <janus@gcc.gnu.org>

33953

+

33954

+ PR fortran/60231

33955

+ * gfortran.dg/typebound_generic_15.f90: New.

33956

+

33957

+2014-02-18 Kai Tietz <ktietz@redhat.com>

33958

+

33959

+ PR target/60193

33960

+ * gcc.target/i386/nest-1.c: New testcase.

33961

+

33962

+2014-02-18 Eric Botcazou <ebotcazou@adacore.com>

33963

+

33964

+ * gnat.dg/opt32.adb: New test.

33965

+

33966

+2014-02-15 Jerry DeLisle <jvdelisle@gcc.gnu>

33967

+ Dominique d'Humieres <dominiq@lps.ens.fr>

33968

+

33969

+ Backport from mainline

33970

+ PR libfortran/59771

33971

+ PR libfortran/59774

33972

+ PR libfortran/59836

33973

+ * gfortran.dg/fmt_g_1.f90: New test.

33974

+ * gfortran.dg/round_3.f08: New cases added.

33975

+

33976

+2014-02-13 Dominik Vogt <vogt@linux.vnet.ibm.com>

33977

+

33978

+ * gcc.target/s390/hotpatch-compile-8.c: New test.

33979

+

33980

+2014-02-12 Eric Botcazou <ebotcazou@adacore.com>

33981

+

33982

+ * gcc.c-torture/execute/20140212-1.c: New test.

33983

+

33984

+2014-02-10 Richard Biener <rguenther@suse.de>

33985

+

33986

+ Backport from mainline

33987

+ 2014-01-30 Richard Biener <rguenther@suse.de>

33988

+

33989

+ PR tree-optimization/59903

33990

+ * gcc.dg/torture/pr59903.c: New testcase.

33991

+

33992

+ 2014-02-10 Richard Biener <rguenther@suse.de>

33993

+

33994

+ PR tree-optimization/60115

33995

+ * gcc.dg/torture/pr60115.c: New testcase.

33996

+

33997

+2014-02-09 Janus Weil <janus@gcc.gnu.org>

33998

+

33999

+ Backport from mainline

34000

+ 2013-10-21 Tobias Burnus <burnus@net-b.de>

34001

+

34002

+ PR fortran/58803

34003

+ PR fortran/59395

34004

+ * gfortran.dg/proc_ptr_comp_38.f90: New.

34005

+

34006

+2014-02-08 Mikael Morin <mikael@gcc.gnu.org>

34007

+

34008

+ PR fortran/57033

34009

+ * gfortran.dg/default_initialization_7.f90: New test.

34010

+

34011

+2014-02-07 Paul Thomas <pault@gcc.gnu.org>

34012

+

34013

+ PR fortran/59906

34014

+ * gfortran.dg/elemental_subroutine_9.f90 : New test

34015

+

34016

+2014-02-04 Uros Bizjak <ubizjak@gmail.com>

34017

+

34018

+ Backport from mainline

34019

+ 2014-02-02 Uros Bizjak <ubizjak@gmail.com>

34020

+

34021

+ PR target/60017

34022

+ * gcc.c-torture/execute/pr60017.c: New test.

34023

+

34024

+2014-02-01 Paul Thomas <pault@gcc.gnu.org>

34025

+

34026

+ PR fortran/59414

34027

+ * gfortran.dg/allocate_class_3.f90 : New test

34028

+

34029

+2014-01-30 David Holsgrove <david.holsgrove@xilinx.com>

34030

+

34031

+ Backport from mainline.

34032

+ * gcc.target/microblaze/isa/fcmp4.c: New.

34033

+

34034

+2014-01-26 Mikael Morin <mikael@gcc.gnu.org>

34035

+

34036

+ PR fortran/58007

34037

+ * gfortran.dg/unresolved_fixup_1.f90: New test.

34038

+ * gfortran.dg/unresolved_fixup_2.f90: New test.

34039

+

34040

+2014-01-24 H.J. Lu <hongjiu.lu@intel.com>

34041

+

34042

+ Backport from mainline.

34043

+ 2014-01-23 H.J. Lu <hongjiu.lu@intel.com>

34044

+

34045

+ PR target/59929

34046

+ * gcc.target/i386/pr59929.c: New test.

34047

+

34048

+2014-01-24 Paolo Carlini <paolo.carlini@oracle.com>

34049

+

34050

+ PR c++/57524

34051

+ * g++.dg/ext/timevar2.C: New.

34052

+

34053

+2014-01-23 David Holsgrove <david.holsgrove@xilinx.com>

34054

+

34055

+ Backport from mainline.

34056

+ * gcc.target/microblaze/others/builtin-trap.c: New test.

34057

+

34058

+2014-01-23 Marek Polacek <polacek@redhat.com>

34059

+

34060

+ Backport from mainline

34061

+ 2013-10-21 Marek Polacek <polacek@redhat.com>

34062

+

34063

+ PR middle-end/58809

34064

+ * gcc.dg/gomp/pr58809.c: New test.

34065

+

34066

+2014-01-23 Jakub Jelinek <jakub@redhat.com>

34067

+

34068

+ PR middle-end/58809

34069

+ * c-c++-common/gomp/pr58809.c: New test.

34070

+

34071

+2014-01-22 Marek Polacek <polacek@redhat.com>

34072

+

34073

+ Backport from mainline

34074

+ 2014-01-22 Marek Polacek <polacek@redhat.com>

34075

+

34076

+ PR c/59891

34077

+ * gcc.dg/torture/pr59891.c: New test.

34078

+

34079

+2014-01-21 Jakub Jelinek <jakub@redhat.com>

34080

+

34081

+ PR middle-end/59860

34082

+ * gcc.dg/strlenopt-4.c: Expect the same counts on s390*-* as on all

34083

+ other targets.

34084

+

34085

+2014-01-20 Richard Biener <rguenther@suse.de>

34086

+

34087

+ PR middle-end/59860

34088

+ * gcc.dg/pr59860.c: New testcase.

34089

+

34090

+2014-01-20 Marek Polacek <polacek@redhat.com>

34091

+

34092

+ Backported from mainline

34093

+ 2014-01-17 Marek Polacek <polacek@redhat.com>

34094

+

34095

+ PR c++/59838

34096

+ * g++.dg/diagnostic/pr59838.C: New test.

34097

+

34098

+2014-01-19 Paul Thomas <pault@gcc.gnu.org>

34099

+

34100

+ Backport from mainline

34101

+ 2013-12-01 Paul Thomas <pault@gcc.gnu.org>

34102

+

34103

+ PR fortran/34547

34104

+ * gfortran.dg/null_5.f90 : Include new error.

34105

+ * gfortran.dg/null_6.f90 : Include new error.

34106

+

34107

+2014-01-17 H.J. Lu <hongjiu.lu@intel.com>

34108

+

34109

+ Backport from mainline

34110

+ 2014-01-15 H.J. Lu <hongjiu.lu@intel.com>

34111

+

34112

+ PR target/59794

34113

+ * c-c++-common/convert-vec-1.c: Also prune ABI change for

34114

+ Linux/x86.

34115

+ * g++.dg/cpp0x/constexpr-53094-2.C: Likewise.

34116

+ * g++.dg/ext/attribute-test-1.C: Likewise.

34117

+ * g++.dg/ext/attribute-test-2.C: Likewise.

34118

+ * g++.dg/ext/attribute-test-3.C: Likewise.

34119

+ * g++.dg/ext/attribute-test-4.C: Likewise.

34120

+ * g++.dg/torture/pr38565.C: Likewise.

34121

+ * gcc.dg/pr53060.c: Likewise.

34122

+ * c-c++-common/scal-to-vec2.c: Add -msse2 for x86.

34123

+ * c-c++-common/vector-compare-2.c: Likewise.

34124

+ * gcc.dg/Wstrict-aliasing-bogus-ref-all-2.c: Likewise.

34125

+ * g++.dg/conversion/simd1.C: Add -msse2 for x86. Adjust

34126

+ dg-message line number.

34127

+

34128

+2014-01-17 H.J. Lu <hongjiu.lu@intel.com>

34129

+

34130

+ Backport from mainline

34131

+ 2014-01-14 H.J. Lu <hongjiu.lu@intel.com>

34132

+

34133

+ PR target/59794

34134

+ * gcc.target/i386/pr39162.c (y): New __m256i variable.

34135

+ (bar): Change return type to void. Set y to x.

34136

+ * gcc.target/i386/pr59794-1.c: New testcase.

34137

+ * gcc.target/i386/pr59794-2.c: Likewise.

34138

+ * gcc.target/i386/pr59794-3.c: Likewise.

34139

+ * gcc.target/i386/pr59794-4.c: Likewise.

34140

+ * gcc.target/i386/pr59794-5.c: Likewise.

34141

+ * gcc.target/i386/pr59794-6.c: Likewise.

34142

+ * gcc.target/i386/pr59794-7.c: Likewise.

34143

+

34144

+2014-01-17 Matthias Klose <doko@ubuntu.com>

34145

+

34146

+ Backport from the trunk:

34147

+ 2014-01-09 Uros Bizjak <ubizjak@gmail.com>

34148

+ * go.test/go-test.exp (go-gc-tests): Don't run peano.go on systems

34149

+ which don't support -fsplit-stack. Skip rotate[0123].go tests.

34150

+

34151

+2014-01-15 Kugan Vivekanandarajah <kuganv@linaro.org>

34152

+

34153

+ Backport from mainline

34154

+ 2014-01-15 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org>

34155

+ Kugan Vivekanandarajah <kuganv@linaro.org>

34156

+

34157

+ PR target/59695

34158

+ * g++.dg/pr59695.C: New testcase.

34159

+

34160

+2014-01-17 Terry Guo <terry.guo@arm.com>

34161

+

34162

+ * gcc.target/arm/pr59826.c: New test.

34163

+

34164

+2014-01-16 Jakub Jelinek <jakub@redhat.com>

34165

+

34166

+ PR target/59839

34167

+ * gcc.target/i386/pr59839.c: New test.

34168

+

34169

+ PR debug/54694

34170

+ * gcc.target/i386/pr9771-1.c (main): Rename to...

34171

+ (real_main): ... this. Add __asm name "main".

34172

+ (ASMNAME, ASMNAME2, STRING): Define.

34173

+

34174

+2014-01-16 Marek Polacek <polacek@redhat.com>

34175

+

34176

+ Backported from mainline

34177

+ 2014-01-16 Marek Polacek <polacek@redhat.com>

34178

+

34179

+ PR middle-end/59827

34180

+ * gcc.dg/pr59827.c: New test.

34181

+

34182

+2014-01-15 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>

34183

+

34184

+ PR target/59803

34185

+ * gcc.c-torture/compile/pr59803.c: New testcase.

34186

+

34187

+2014-01-10 Yufeng Zhang <yufeng.zhang@arm.com>

34188

+

34189

+ * gcc.target/arm/neon/vst1Q_laneu64-1.c: New test.

34190

+

34191

+2014-01-10 Hans-Peter Nilsson <hp@axis.com>

34192

+

34193

+ * gcc.dg/pr46309.c: Disable for cris*-*-*.

34194

+

34195

+2014-01-10 Paolo Carlini <paolo.carlini@oracle.com>

34196

+

34197

+ PR c++/56060

34198

+ PR c++/59730

34199

+ * g++.dg/cpp0x/variadic144.C: New.

34200

+ * g++.dg/cpp0x/variadic145.C: Likewise.

34201

+

34202

+2014-01-10 Richard Biener <rguenther@suse.de>

34203

+

34204

+ PR tree-optimization/59715

34205

+ * gcc.dg/torture/pr59715.c: New testcase.

34206

+

34207

+2014-01-09 Richard Sandiford <rdsandiford@googlemail.com>

34208

+

34209

+ * gcc.target/mips/bswap-1.c, gcc.target/mips/bswap-2.c,

34210

+ gcc.target/mips/bswap-3.c, gcc.target/mips/bswap-4.c,

34211

+ gcc.target/mips/bswap-5.c, gcc.target/mips/bswap-6.c: New tests.

34212

+

34213

+2014-01-09 Richard Sandiford <rdsandiford@googlemail.com>

34214

+

34215

+ PR rtl-optimization/59137

34216

+ * gcc.target/mips/pr59137.c: New test.

34217

+

34218

+2014-01-09 Richard Biener <rguenther@suse.de>

34219

+

34220

+ Backport from mainline

34221

+ 2013-11-18 Richard Biener <rguenther@suse.de>

34222

+

34223

+ PR tree-optimization/59125

34224

+ PR tree-optimization/54570

34225

+ * gcc.dg/builtin-object-size-8.c: Un-xfail.

34226

+ * gcc.dg/builtin-object-size-14.c: New testcase.

34227

+ * gcc.dg/strlenopt-14gf.c: Adjust.

34228

+ * gcc.dg/strlenopt-1f.c: Likewise.

34229

+ * gcc.dg/strlenopt-4gf.c: Likewise.

34230

+

34231

+ 2013-12-03 Jakub Jelinek <jakub@redhat.com>

34232

+

34233

+ PR tree-optimization/59362

34234

+ * gcc.c-torture/compile/pr59362.c: New test.

34235

+

34236

+2014-01-09 Richard Earnshaw <rearnsha@arm.com>

34237

+

34238

+ PR rtl-optimization/54300

34239

+ * gcc.target/arm/pr54300.C: New test.

34240

+

34241

+2014-01-08 Martin Jambor <mjambor@suse.cz>

34242

+

34243

+ PR ipa/59610

34244

+ * gcc.dg/ipa/pr59610.c: New test.

34245

+

34246

+2014-01-07 Jakub Jelinek <jakub@redhat.com>

34247

+

34248

+ PR rtl-optimization/58668

34249

+ * gcc.dg/pr58668.c: New test.

34250

+

34251

+ Backported from mainline

34252

+ 2013-12-16 Jakub Jelinek <jakub@redhat.com>

34253

+

34254

+ PR middle-end/58956

34255

+ PR middle-end/59470

34256

+ * gcc.target/i386/pr59470.c: New test.

34257

+

34258

+2014-01-04 Janus Weil <janus@gcc.gnu.org>

34259

+

34260

+ Backport from mainline

34261

+ 2014-01-02 Janus Weil <janus@gcc.gnu.org>

34262

+

34263

+ PR fortran/59654

34264

+ * gfortran.dg/dynamic_dispatch_12.f90: New.

34265

+

34266

+2014-01-03 Joseph Myers <joseph@codesourcery.com>

34267

+

34268

+ * gcc.target/powerpc/rs6000-ldouble-3.c: New test.

34269

+

34270

+2014-01-03 Jakub Jelinek <jakub@redhat.com>

34271

+

34272

+ PR target/59625

34273

+ * gcc.target/i386/pr59625.c: New test.

34274

+

34275

+2014-01-01 Jakub Jelinek <jakub@redhat.com>

34276

+

34277

+ PR rtl-optimization/59647

34278

+ * g++.dg/opt/pr59647.C: New test.

34279

+

34280

+2013-12-31 Janus Weil <janus@gcc.gnu.org>

34281

+

34282

+ Backport from mainline

34283

+ 2013-12-30 Janus Weil <janus@gcc.gnu.org>

34284

+

34285

+ PR fortran/58998

34286

+ * gfortran.dg/generic_28.f90: New.

34287

+

34288

+2013-12-20 Jakub Jelinek <jakub@redhat.com>

34289

+

34290

+ PR c++/59255

34291

+ * g++.dg/tree-prof/pr59255.C: New test.

34292

+

34293

+2013-12-19 James Greenhalgh <james.greenhalgh@arm.com>

34294

+

34295

+ Backport from Mainline

34296

+ 2013-05-01 James Greenhalgh <james.greenhalgh@arm.com>

34297

+

34298

+ * gcc.target/aarch64/scalar_intrinsics.c (force_simd): New.

34299

+ (test_vceqd_s64): Force arguments to SIMD registers.

34300

+ (test_vceqzd_s64): Likewise.

34301

+ (test_vcged_s64): Likewise.

34302

+ (test_vcled_s64): Likewise.

34303

+ (test_vcgezd_s64): Likewise.

34304

+ (test_vcged_u64): Likewise.

34305

+ (test_vcgtd_s64): Likewise.

34306

+ (test_vcltd_s64): Likewise.

34307

+ (test_vcgtzd_s64): Likewise.

34308

+ (test_vcgtd_u64): Likewise.

34309

+ (test_vclezd_s64): Likewise.

34310

+ (test_vcltzd_s64): Likewise.

34311

+ (test_vtst_s64): Likewise.

34312

+ (test_vtst_u64): Likewise.

34313

+

34314

+2013-12-19 Dominik Vogt <vogt@linux.vnet.ibm.com>

34315

+ Andreas Krebbel <Andreas.Krebbel@de.ibm.com>

34316

+

34317

+ Backport from mainline

34318

+ 2013-12-19 Dominik Vogt <vogt@linux.vnet.ibm.com>

34319

+ * gcc/testsuite/gcc.target/s390/hotpatch-1.c: New test

34320

+ * gcc/testsuite/gcc.target/s390/hotpatch-2.c: New test

34321

+ * gcc/testsuite/gcc.target/s390/hotpatch-3.c: New test

34322

+ * gcc/testsuite/gcc.target/s390/hotpatch-4.c: New test

34323

+ * gcc/testsuite/gcc.target/s390/hotpatch-5.c: New test

34324

+ * gcc/testsuite/gcc.target/s390/hotpatch-6.c: New test

34325

+ * gcc/testsuite/gcc.target/s390/hotpatch-7.c: New test

34326

+ * gcc/testsuite/gcc.target/s390/hotpatch-8.c: New test

34327

+ * gcc/testsuite/gcc.target/s390/hotpatch-9.c: New test

34328

+ * gcc/testsuite/gcc.target/s390/hotpatch-10.c: New test

34329

+ * gcc/testsuite/gcc.target/s390/hotpatch-11.c: New test

34330

+ * gcc/testsuite/gcc.target/s390/hotpatch-12.c: New test

34331

+ * gcc/testsuite/gcc.target/s390/hotpatch-compile-1.c: New test

34332

+ * gcc/testsuite/gcc.target/s390/hotpatch-compile-2.c: New test

34333

+ * gcc/testsuite/gcc.target/s390/hotpatch-compile-3.c: New test

34334

+ * gcc/testsuite/gcc.target/s390/hotpatch-compile-4.c: New test

34335

+ * gcc/testsuite/gcc.target/s390/hotpatch-compile-5.c: New test

34336

+ * gcc/testsuite/gcc.target/s390/hotpatch-compile-6.c: New test

34337

+ * gcc/testsuite/gcc.target/s390/hotpatch-compile-7.c: New test

34338

+

34339

+2013-12-18 Janus Weil <janus@gcc.gnu.org>

34340

+

34341

+ Backport from mainline

34342

+ 2013-12-15 Janus Weil <janus@gcc.gnu.org>

34343

+

34344

+ PR fortran/59493

34345

+ * gfortran.dg/unlimited_polymorphic_15.f90: New.

34346

+

34347

+2013-12-15 Uros Bizjak <ubizjak@gmail.com>

34348

+

34349

+ PR testsuite/58630

34350

+ * gcc.target/i386/pr43662.c (dg-options):

34351

+ Add -maccumulate-outgoing-args.

34352

+ * gcc.target/i386/pr43869.c (dg-options): Ditto.

34353

+ * gcc.target/i386/pr57003.c (dg-options): Ditto.

34354

+ * gcc.target/i386/avx-vzeroupper-16.c (dg-options):

34355

+ Remove -mtune=generic and add -maccumulate-outgoing-args instead.

34356

+ * gcc.target/i386/avx-vzeroupper-17.c (dg-options): Ditto.

34357

+ * gcc.target/i386/avx-vzeroupper-18.c (dg-options): Ditto.

34358

+ * gcc.target/x86_64/abi/callabi/func-1.c (dg-options):

34359

+ Add -maccumulate-outgoing-args.

34360

+ * gcc.target/x86_64/abi/callabi/func-2a.c (dg-options): Ditto.

34361

+ * gcc.target/x86_64/abi/callabi/func-2b.c (dg-options): Ditto.

34362

+ * gcc.target/x86_64/abi/callabi/func-indirect.c (dg-options): Ditto.

34363

+ * gcc.target/x86_64/abi/callabi/func-indirect-2a.c (dg-options): Ditto.

34364

+ * gcc.target/x86_64/abi/callabi/func-indirect-2b.c (dg-options): Ditto.

34365

+ * gcc.target/x86_64/abi/callabi/leaf-1.c (dg-options): Ditto.

34366

+ * gcc.target/x86_64/abi/callabi/leaf-2.c (dg-options): Ditto.

34367

+ * gcc.target/x86_64/abi/callabi/pr38891.c (dg-options): Ditto.

34368

+ * gcc.target/x86_64/abi/callabi/vaarg-1.c (dg-options): Ditto.

34369

+ * gcc.target/x86_64/abi/callabi/vaarg-2.c (dg-options): Ditto.

34370

+ * gcc.target/x86_64/abi/callabi/vaarg-3.c (dg-options): Ditto.

34371

+ * gcc.target/x86_64/abi/callabi/vaarg-4a.c (dg-options): Ditto.

34372

+ * gcc.target/x86_64/abi/callabi/vaarg-4b.c (dg-options): Ditto.

34373

+ * gcc.target/x86_64/abi/callabi/vaarg-5a.c (dg-options): Ditto.

34374

+ * gcc.target/x86_64/abi/callabi/vaarg-5b.c (dg-options): Ditto.

34375

+

34376

+2013-12-12 Jakub Jelinek <jakub@redhat.com>

34377

+

34378

+ PR middle-end/59470

34379

+ * g++.dg/opt/pr59470.C: New test.

34380

+

34381

+ PR libgomp/59467

34382

+ * gfortran.dg/gomp/pr59467.f90: New test.

34383

+ * c-c++-common/gomp/pr59467.c: New test.

34384

+

34385

+2013-12-12 Uros Bizjak <ubizjak@gmail.com>

34386

+

34387

+ Backport from mainline

34388

+ 2013-12-12 Ryan Mansfield <rmansfield@qnx.com>

34389

+

34390

+ PR testsuite/59442

34391

+ * gcc.target/i386/sse2-movapd-1.c: Fix alignment attributes.

34392

+ * gcc.target/i386/sse2-movapd-2.c: Likewise.

34393

+ * gcc.target/i386/avx-vmovapd-256-1.c: Likewise.

34394

+ * gcc.target/i386/avx-vmovapd-256-2.c: Likewise.

34395

+

34396

+2013-12-08 Uros Bizjak <ubizjak@gmail.com>

34397

+

34398

+ Backport from mainline

34399

+ 2013-12-06 Uros Bizjak <ubizjak@gmail.com>

34400

+

34401

+ PR target/59405

34402

+ * gcc.target/i386/pr59405.c: New test.

34403

+

34404

+2013-12-06 Jakub Jelinek <jakub@redhat.com>

34405

+

34406

+ PR tree-optimization/59388

34407

+ * gcc.c-torture/execute/pr59388.c: New test.

34408

+

34409

+2013-12-06 Richard Biener <rguenther@suse.de>

34410

+

34411

+ Backport from mainline

34412

+ 2013-11-28 Richard Biener <rguenther@suse.de>

34413

+

34414

+ PR tree-optimization/59330

34415

+ * gcc.dg/torture/pr59330.c: New testcase.

34416

+

34417

+2013-12-06 Richard Biener <rguenther@suse.de>

34418

+

34419

+ Backport from mainline

34420

+ 2013-11-27 Richard Biener <rguenther@suse.de>

34421

+

34422

+ PR tree-optimization/59288

34423

+ * gcc.dg/torture/pr59288.c: New testcase.

34424

+

34425

+ 2013-11-19 Richard Biener <rguenther@suse.de>

34426

+

34427

+ PR tree-optimization/59164

34428

+ * gcc.dg/torture/pr59164.c: New testcase.

34429

+

34430

+ 2013-09-05 Richard Biener <rguenther@suse.de>

34431

+

34432

+ PR tree-optimization/58137

34433

+ * gcc.target/i386/pr58137.c: New testcase.

34434

+

34435

+2013-12-06 Oleg Endo <olegendo@gcc.gnu.org>

34436

+

34437

+ PR target/51244

34438

+ PR target/59343

34439

+ * gcc.target/sh/pr51244-19.c: Adjust test case.

34440

+

34441

+2013-12-05 Richard Biener <rguenther@suse.de>

34442

+

34443

+ Backport from mainline

34444

+ 2013-11-19 Richard Biener <rguenther@suse.de>

34445

+

34446

+ PR middle-end/58956

34447

+ * gcc.dg/torture/pr58956.c: New testcase.

34448

+

34449

+2013-12-04 Jakub Jelinek <jakub@redhat.com>

34450

+

34451

+ PR c++/59268

34452

+ * g++.dg/cpp0x/constexpr-template6.C: New test.

34453

+

34454

+ PR rtl-optimization/58726

34455

+ * gcc.c-torture/execute/pr58726.c: New test.

34456

+

34457

+ PR target/59163

34458

+ * g++.dg/torture/pr59163.C: New test.

34459

+

34460

+2013-12-03 Marek Polacek <polacek@redhat.com>

34461

+

34462

+ Backport from mainline

34463

+ 2013-12-03 Marek Polacek <polacek@redhat.com>

34464

+

34465

+ PR c/59351

34466

+ * gcc.dg/pr59351.c: New test.

34467

+

34468

+2013-12-03 Jakub Jelinek <jakub@redhat.com>

34469

+

34470

+ PR middle-end/59011

34471

+ * gcc.dg/pr59011.c: New test.

34472

+

34473

+ PR target/58864

34474

+ * g++.dg/opt/pr58864.C: New test.

34475

+

34476

+2013-12-02 Jakub Jelinek <jakub@redhat.com>

34477

+

34478

+ PR tree-optimization/59358

34479

+ * gcc.c-torture/execute/pr59358.c: New test.

34480

+

34481

+2013-12-02 Richard Biener <rguenther@suse.de>

34482

+

34483

+ PR tree-optimization/59139

34484

+ * gcc.dg/torture/pr59139.c: New testcase.

34485

+

34486

+2013-11-27 Tom de Vries <tom@codesourcery.com>

34487

+ Marc Glisse <marc.glisse@inria.fr>

34488

+

34489

+ PR c++/59032

34490

+ * c-c++-common/pr59032.c: New testcase.

34491

+

34492

+2013-11-27 Tom de Vries <tom@codesourcery.com>

34493

+ Marc Glisse <marc.glisse@inria.fr>

34494

+

34495

+ PR middle-end/59037

34496

+ * c-c++-common/pr59037.c: New testcase.

34497

+

34498

+2013-11-30 Paul Thomas <pault@gcc.gnu.org>

34499

+

34500

+ Backport from mainline

34501

+ 2013-11-04 Paul Thomas <pault@gcc.gnu.org>

34502

+

34503

+ PR fortran/57445

34504

+ * gfortran.dg/optional_class_1.f90 : New test

34505

+

34506

+2013-11-29 Jakub Jelinek <jakub@redhat.com>

34507

+

34508

+ PR c/59280

34509

+ * c-c++-common/pr59280.c: New test.

34510

+

34511

+2013-11-28 Jakub Jelinek <jakub@redhat.com>

34512

+

34513

+ PR c++/59297

34514

+ * g++.dg/gomp/pr59297.C: New test.

34515

+

34516

+2013-11-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com>

34517

+

34518

+ Backport from mainline

34519

+ 2013-11-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com>

34520

+

34521

+ * gcc.target/arm/vrinta-ce.c: New testcase.

34522

+

34523

+2013-11-28 Uros Bizjak <ubizjak@gmail.com>

34524

+

34525

+ Backport from mainline

34526

+ 2013-11-23 Uros Bizjak <ubizjak@gmail.com>

34527

+

34528

+ PR target/56788

34529

+ * config/i386/i386.c (bdesc_multi_arg) <IX86_BUILTIN_VFRCZSS>:

34530

+ Declare as MULTI_ARG_1_SF instruction.

34531

+ <IX86_BUILTIN_VFRCZSD>: Decleare as MULTI_ARG_1_DF instruction.

34532

+ * config/i386/sse.md (*xop_vmfrcz<mode>2): Rename

34533

+ from *xop_vmfrcz_<mode>.

34534

+ * config/i386/xopintrin.h (_mm_frcz_ss): Use __builtin_ia32_movss

34535

+ to merge scalar result with __A.

34536

+ (_mm_frcz_sd): Use __builtin_ia32_movsd to merge scalar

34537

+ result with __A.

34538

+

34539

+2013-11-28 Terry Guo <terry.guo@arm.com>

34540

+

34541

+ Backport mainline r205391

34542

+ 2013-11-26 Terry Guo <terry.guo@arm.com>

34543

+

34544

+ * gcc.target/arm/thumb1-pic-high-reg.c: New case.

34545

+ * gcc.target/arm/thumb1-pic-single-base.c: New case.

34546

+

34547

+2013-11-27 Jakub Jelinek <jakub@redhat.com>

34548

+

34549

+ Backported from mainline

34550

+ 2013-11-27 Jakub Jelinek <jakub@redhat.com>

34551

+

34552

+ PR tree-optimization/59014

34553

+ * gcc.c-torture/execute/pr59014-2.c: New test.

34554

+

34555

+ 2013-11-26 Jakub Jelinek <jakub@redhat.com>

34556

+

34557

+ PR tree-optimization/59014

34558

+ * gcc.c-torture/execute/pr59014.c: New test.

34559

+

34560

+2013-11-27 Eric Botcazou <ebotcazou@adacore.com>

34561

+

34562

+ * gcc.c-torture/execute/20131127-1.c: New test.

34563

+

34564

+2013-11-25 Vidya Praveen <vidyapraveen@arm.com>

34565

+

34566

+ Backport from mainline

34567

+ 2013-10-21 Vidya Praveen <vidyapraveen@arm.com>

34568

+

34569

+ * gcc.dg/20050922-1.c: Remove stdlib.h and declare abort().

34570

+ * gcc.dg/20050922-1.c: Remove stdlib.h and declare abort() and exit().

34571

+

34572

+2013-11-20 Dominik Vogt <vogt@linux.vnet.ibm.com>

34573

+

34574

+ Backport from mainline

34575

+ * gcc.target/s390/htm-1.c: Rename to ...

34576

+ * gcc/testsuite/gcc.target/s390/htm-builtins-compile-1.c: ... this

34577

+ one.

34578

+ * gcc.target/s390/htm-xl-intrin-1.c: Rename to ...

34579

+ * gcc.target/s390/htm-builtins-compile-3.c: ... this one.

34580

+ * gcc.target/s390/htm-builtins-compile-2.c: New testcase.

34581

+ * gcc.target/s390/htm-builtins-1.c: New testcase.

34582

+ * gcc.target/s390/htm-builtins-2.c: New testcase.

34583

+ * gcc.target/s390/s390.exp: Add check for htm machine.

34584

+

34585

+2013-11-19 Richard Biener <rguenther@suse.de>

34586

+

34587

+ PR tree-optimization/57517

34588

+ * gfortran.fortran-torture/compile/pr57517.f90: New testcase.

34589

+ * gcc.dg/torture/pr57517.c: Likewise.

34590

+

34591

+2013-11-19 Richard Biener <rguenther@suse.de>

34592

+

34593

+ Backport from mainline

34594

+ 2013-11-05 Richard Biener <rguenther@suse.de>

34595

+

34596

+ PR middle-end/58941

34597

+ * gcc.dg/torture/pr58941.c: New testcase.

34598

+

34599

+2013-11-18 Richard Biener <rguenther@suse.de>

34600

+

34601

+ Backport from mainline

34602

+ 2013-10-21 Richard Biener <rguenther@suse.de>

34603

+

34604

+ PR tree-optimization/58794

34605

+ * c-c++-common/torture/pr58794-1.c: New testcase.

34606

+ * c-c++-common/torture/pr58794-2.c: Likewise.

34607

+

34608

+ 2013-10-21 Richard Biener <rguenther@suse.de>

34609

+

34610

+ PR middle-end/58742

34611

+ * c-c++-common/fold-divmul-1.c: New testcase.

34612

+

34613

+ 2013-11-06 Richard Biener <rguenther@suse.de>

34614

+

34615

+ PR tree-optimization/58653

34616

+ * gcc.dg/tree-ssa/predcom-6.c: New testcase.

34617

+ * gcc.dg/tree-ssa/predcom-7.c: Likewise.

34618

+

34619

+ PR tree-optimization/59047

34620

+ * gcc.dg/torture/pr59047.c: New testcase.

34621

+

34622

+ 2013-10-15 Richard Biener <rguenther@suse.de>

34623

+

34624

+ PR tree-optimization/58143

34625

+ * gcc.dg/torture/pr58143-1.c: New testcase.

34626

+ * gcc.dg/torture/pr58143-2.c: Likewise.

34627

+ * gcc.dg/torture/pr58143-3.c: Likewise.

34628

+

34629

+2013-11-17 Janus Weil <janus@gcc.gnu.org>

34630

+

34631

+ Backport from mainline

34632

+ 2013-11-07 Janus Weil <janus@gcc.gnu.org>

34633

+

34634

+ PR fortran/58471

34635

+ * gfortran.dg/constructor_9.f90: New.

34636

+

34637

+2013-11-16 Janus Weil <janus@gcc.gnu.org>

34638

+

34639

+ Backport from mainline

34640

+ 2013-09-20 Janus Weil <janus@gcc.gnu.org>

34641

+

34642

+ PR fortran/58099

34643

+ * gfortran.dg/proc_ptr_43.f90: New.

34644

+

34645

+2013-11-16 Paul Thomas <pault@gcc.gnu.org>

34646

+

34647

+ PR fortran/58771

34648

+ * gfortran.dg/derived_external_function_1.f90 : New test

34649

+

34650

+2013-11-14 Uros Bizjak <ubizjak@gmail.com>

34651

+

34652

+ Backport from mainline

34653

+ 2013-11-06 Uros Bizjak <ubizjak@gmail.com>

34654

+

34655

+ PR target/59021

34656

+ * gcc.target/i386/pr59021.c: New test.

34657

+

34658

+2013-11-14 Jakub Jelinek <jakub@redhat.com>

34659

+

34660

+ PR target/59101

34661

+ * gcc.c-torture/execute/pr59101.c: New test.

34662

+

34663

+2013-11-11 Jakub Jelinek <jakub@redhat.com>

34664

+

34665

+ Backported from mainline

34666

+ 2013-11-06 Jakub Jelinek <jakub@redhat.com>

34667

+

34668

+ PR middle-end/58970

34669

+ * gcc.c-torture/compile/pr58970-1.c: New test.

34670

+ * gcc.c-torture/compile/pr58970-2.c: New test.

34671

+

34672

+ 2013-11-05 Jakub Jelinek <jakub@redhat.com>

34673

+

34674

+ PR rtl-optimization/58997

34675

+ * gcc.c-torture/compile/pr58997.c: New test.

34676

+

34677

+2013-11-10 Wei Mi <wmi@google.com>

34678

+

34679

+ * gcc.dg/pr57518.c: Backport regex fix from r200720.

34680

+

34681

+2013-11-07 H.J. Lu <hongjiu.lu@intel.com>

34682

+

34683

+ Backport from mainline

34684

+ 2013-11-07 H.J. Lu <hongjiu.lu@intel.com>

34685

+

34686

+ PR target/59034

34687

+ * gcc.target/i386/pr59034-1.c: New test.

34688

+ * gcc.target/i386/pr59034-2.c: Likewise.

34689

+

34690

+2013-11-06 Wei Mi <wmi@google.com>

34691

+

34692

+ PR regression/58985

34693

+ * gcc.dg/pr57518.c: Add subreg in regexp pattern.

34694

+

34695

+2013-11-05 Steven G. Kargl <kargl@gcc.gnu.org>

34696

+

34697

+ PR fortran/58989

34698

+ * gfortran.dg/reshape_6.f90: New test.

34699

+

34700

+2013-11-05 Jakub Jelinek <jakub@redhat.com>

34701

+

34702

+ PR tree-optimization/58984

34703

+ * gcc.c-torture/execute/pr58984.c: New test.

34704

+

34705

+2013-11-04 Marek Polacek <polacek@redhat.com>

34706

+

34707

+ Backport from mainline

34708

+ 2013-11-04 Marek Polacek <polacek@redhat.com>

34709

+

34710

+ PR c++/58979

34711

+ * g++.dg/diagnostic/pr58979.C: New test.

34712

+

34713

+2013-11-03 H.J. Lu <hongjiu.lu@intel.com>

34714

+

34715

+ Backport from mainline

34716

+ 2013-10-12 H.J. Lu <hongjiu.lu@intel.com>

34717

+

34718

+ PR target/58690

34719

+ * gcc.target/i386/pr58690.c: New test

34720

+

34721

+2013-11-02 Janus Weil <janus@gcc.gnu.org>

34722

+

34723

+ Backport from mainline

34724

+ 2013-09-23 Janus Weil <janus@gcc.gnu.org>

34725

+

34726

+ PR fortran/58355

34727

+ * gfortran.dg/extends_15.f90: New.

34728

+

34729

+2013-10-29 Uros Bizjak <ubizjak@gmail.com>

34730

+

34731

+ Backport from mainline

34732

+ 2013-08-08 Richard Sandiford <rdsandiford@googlemail.com>

34733

+

34734

+ PR rtl-optimization/58079

34735

+ * gcc.dg/torture/pr58079.c: New test.

34736

+

34737

+2013-10-28 Tom de Vries <tom@codesourcery.com>

34738

+

34739

+ * gcc.target/arm/require-pic-register-loc.c: New test.

34740

+

34741

+2013-10-26 Uros Bizjak <ubizjak@gmail.com>

34742

+

34743

+ Backport from mainline

34744

+ 2013-10-22 Uros Bizjak <ubizjak@gmail.com>

34745

+

34746

+ PR target/58779

34747

+ * gcc.target/i386/pr30315.c: Remove MINUSCC, DECCC, MINUSCCONLY

34748

+ and MINUSCCZEXT defines. Update scan-assembler dg directive.

34749

+ * gcc.dg/torture/pr58779.c: New test.

34750

+

34751

+2013-10-25 Richard Henderson <rth@redhat.com>

34752

+

34753

+ PR rtl/58542

34754

+ * gcc.dg/atomic-store-6.c: New.

34755

+

34756

+2013-10-25 Tom de Vries <tom@codesourcery.com>

34757

+

34758

+ PR c++/58282

34759

+ * g++.dg/tm/noexcept-6.C: New test.

34760

+

34761

+2013-10-25 Eric Botcazou <ebotcazou@adacore.com>

34762

+

34763

+ * gcc.c-torture/execute/pr58831.c: New test.

34764

+

34765

+2013-10-23 Tom de Vries <tom@codesourcery.com>

34766

+

34767

+ PR tree-optimization/58805

34768

+ * gcc.dg/pr58805.c: New test.

34769

+

34770

+2013-10-23 Richard Biener <rguenther@suse.de>

34771

+

34772

+ * gcc.dg/torture/pr58830.c: New testcase.

34773

+

34774

+ Backport from mainline

34775

+ 2013-06-24 Richard Biener <rguenther@suse.de>

34776

+

34777

+ PR tree-optimization/57488

34778

+ * gcc.dg/torture/pr57488.c: New testcase.

34779

+

34780

+2013-10-19 Oleg Endo <olegendo@gcc.gnu.org>

34781

+

34782

+ * gcc.target/sh/pr54089-3.c: Fix test for load of constant 31.

34783

+

34784

+2013-10-17 Paolo Carlini <paolo.carlini@oracle.com>

34785

+

34786

+ PR c++/58596

34787

+ * g++.dg/cpp0x/lambda/lambda-nsdmi5.C: New

34788

+

34789

+2013-10-16 Paolo Carlini <paolo.carlini@oracle.com>

34790

+

34791

+ PR c++/58633

34792

+ * g++.dg/cpp0x/decltype57.C: New.

34793

+ * g++.dg/cpp0x/enum18.C: Revert r174385 changes.

34794

+

34795

2013-10-16 Release Manager

34796

34797

* GCC 4.8.2 released.

34798

@@ -39,9 +1863,9 @@

34799

Backport from mainline

34800

2013-06-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>

34801

34802

- * gcc.target/s390/htm-1.c: New file.

34803

- * gcc.target/s390/htm-nofloat-1.c: New file.

34804

- * gcc.target/s390/htm-xl-intrin-1.c: New file.

34805

+ * gcc.target/s390/htm-1.c: New file.

34806

+ * gcc.target/s390/htm-nofloat-1.c: New file.

34807

+ * gcc.target/s390/htm-xl-intrin-1.c: New file.

34808

34809

2013-10-04 Tobias Burnus <burnus@net-b.de>

34810

34811

@@ -307,8 +2131,8 @@

34812

Backport from mainline

34813

2013-08-12 Perez Read <netfirewall@gmail.com>

34814

34815

- PR target/58132

34816

- * gcc.target/i386/movabs-1.c: New test.

34817

+ PR target/58132

34818

+ * gcc.target/i386/movabs-1.c: New test.

34819

34820

2013-08-11 Janus Weil <janus@gcc.gnu.org>

34821

34822

@@ -494,7 +2318,7 @@

34823

2013-06-19 Wei Mi <wmi@google.com>

34824

34825

PR rtl-optimization/57518

34826

- * testsuite/gcc.dg/pr57518.c: New test.

34827

+ * gcc.dg/pr57518.c: New test.

34828

34829

2013-06-11 Tobias Burnus <burnus@net-b.de>

34830

34831

@@ -623,8 +2447,8 @@

34832

34833

2013-05-09 Martin Jambor <mjambor@suse.cz>

34834

34835

- PR middle-end/56988

34836

- * gcc.dg/ipa/pr56988.c: New test.

34837

+ PR middle-end/56988

34838

+ * gcc.dg/ipa/pr56988.c: New test.

34839

34840

2013-05-08 Marc Glisse <marc.glisse@inria.fr>

34841

34842

@@ -701,7 +2525,7 @@

34843

2013-04-25 Marek Polacek <polacek@redhat.com>

34844

34845

PR tree-optimization/57066

34846

- * gcc.dg/torture/builtin-logb-1.c: Adjust testcase.

34847

+ * gcc.dg/torture/builtin-logb-1.c: Adjust testcase.

34848

34849

2013-05-02 Jakub Jelinek <jakub@redhat.com>

34850

34851

@@ -727,8 +2551,8 @@

34852

Backport from mainline

34853

2013-04-24 Vladimir Makarov <vmakarov@redhat.com>

34854

34855

- PR rtl-optimizations/57046

34856

- * gcc.target/i386/pr57046.c: New test.

34857

+ PR rtl-optimizations/57046

34858

+ * gcc.target/i386/pr57046.c: New test.

34859

34860

2013-05-02 Vladimir Makarov <vmakarov@redhat.com>

34861

34862

@@ -735,8 +2559,8 @@

34863

Backport from mainline

34864

2013-04-22 Vladimir Makarov <vmakarov@redhat.com>

34865

34866

- PR target/57018

34867

- * gcc.target/i386/pr57018.c: New test.

34868

+ PR target/57018

34869

+ * gcc.target/i386/pr57018.c: New test.

34870

34871

2013-05-02 Vladimir Makarov <vmakarov@redhat.com>

34872

34873

@@ -743,8 +2567,8 @@

34874

Backport from mainline

34875

2013-04-18 Jakub Jelinek <jakub@redhat.com>

34876

34877

- PR rtl-optimization/56999

34878

- * g++.dg/opt/pr56999.C: New test.

34879

+ PR rtl-optimization/56999

34880

+ * g++.dg/opt/pr56999.C: New test.

34881

34882

2013-05-02 Vladimir Makarov <vmakarov@redhat.com>

34883

34884

@@ -751,8 +2575,8 @@

34885

Backport from mainline

34886

2013-04-19 Vladimir Makarov <vmakarov@redhat.com>

34887

34888

- PR rtl-optimization/56847

34889

- * gcc.dg/pr56847.c: New test.

34890

+ PR rtl-optimization/56847

34891

+ * gcc.dg/pr56847.c: New test.

34892

34893

2013-05-02 Ian Bolton <ian.bolton@arm.com>

34894

34895

@@ -1102,7 +2926,7 @@

34896

2013-03-29 Tobias Burnus <burnus@net-b.de>

34897

34898

PR fortran/56737

34899

- * testsuite/gfortran.dg/fmt_cache_3.f90: New.

34900

+ * gfortran.dg/fmt_cache_3.f90: New.

34901

34902

2013-04-02 Richard Biener <rguenther@suse.de>

34903

34904

@@ -1636,7 +3460,7 @@

34905

2013-02-20 Jan Hubicka <jh@suse.cz>

34906

34907

PR tree-optimization/56265

34908

- * testsuite/g++.dg/ipa/devirt-11.C: New testcase.

34909

+ * g++.dg/ipa/devirt-11.C: New testcase.

34910

34911

2013-02-20 Richard Biener <rguenther@suse.de>

34912

34913

@@ -1823,11 +3647,9 @@

34914

34915

Avoid instrumenting duplicated memory access in the same basic block

34916

* c-c++-common/asan/no-redundant-instrumentation-1.c: New test.

34917

- * testsuite/c-c++-common/asan/no-redundant-instrumentation-2.c:

34918

- Likewise.

34919

- * testsuite/c-c++-common/asan/no-redundant-instrumentation-3.c:

34920

- Likewise.

34921

- * testsuite/c-c++-common/asan/inc.c: Likewise.

34922

+ * c-c++-common/asan/no-redundant-instrumentation-2.c: Likewise.

34923

+ * c-c++-common/asan/no-redundant-instrumentation-3.c: Likewise.

34924

+ * c-c++-common/asan/inc.c: Likewise.

34925

34926

2013-02-12 Vladimir Makarov <vmakarov@redhat.com>

34927

34928

Index: gcc/testsuite/gfortran.fortran-torture/compile/pr57517.f90

34929

===================================================================

34930

--- a/src/gcc/testsuite/gfortran.fortran-torture/compile/pr57517.f90 (.../tags/gcc_4_8_2_release)

34931

+++ b/src/gcc/testsuite/gfortran.fortran-torture/compile/pr57517.f90 (.../branches/gcc-4_8-branch)

34932

@@ -0,0 +1,13 @@

34933

+SUBROUTINE cal_helicity (uh, ph, phb, wavg, ims, ime, its, ite)

34934

+ INTEGER, INTENT( IN ) :: ims, ime, its, ite

34935

+ REAL, DIMENSION( ims:ime), INTENT( IN ) :: ph, phb, wavg

34936

+ REAL, DIMENSION( ims:ime), INTENT( INOUT ) :: uh

34937

+ INTEGER :: i

34938

+ REAL :: zu

34939

+ DO i = its, ite

34940

+ zu = (ph(i ) + phb(i)) + (ph(i-1) + phb(i-1))

34941

+ IF (wavg(i) .GT. 0) THEN

34942

+ uh(i) = uh(i) + zu

34943

+ ENDIF

34944

+ END DO

34945

+END SUBROUTINE cal_helicity

34946

Index: gcc/testsuite/g++.dg/ext/attribute-test-2.C

34947

===================================================================

34948

--- a/src/gcc/testsuite/g++.dg/ext/attribute-test-2.C (.../tags/gcc_4_8_2_release)

34949

+++ b/src/gcc/testsuite/g++.dg/ext/attribute-test-2.C (.../branches/gcc-4_8-branch)

34950

@@ -50,3 +50,4 @@

34951

34952

/* Ignore a warning that is irrelevant to the purpose of this test. */

34953

/* { dg-prune-output ".*GCC vector returned by reference.*" } */

34954

+/* { dg-prune-output "changes the ABI" } */

34955

Index: gcc/testsuite/g++.dg/ext/attribute-test-3.C

34956

===================================================================

34957

--- a/src/gcc/testsuite/g++.dg/ext/attribute-test-3.C (.../tags/gcc_4_8_2_release)

34958

+++ b/src/gcc/testsuite/g++.dg/ext/attribute-test-3.C (.../branches/gcc-4_8-branch)

34959

@@ -52,3 +52,4 @@

34960

34961

/* Ignore a warning that is irrelevant to the purpose of this test. */

34962

/* { dg-prune-output ".*GCC vector returned by reference.*" } */

34963

+/* { dg-prune-output "changes the ABI" } */

34964

Index: gcc/testsuite/g++.dg/ext/traits1.C

34965

===================================================================

34966

--- a/src/gcc/testsuite/g++.dg/ext/traits1.C (.../tags/gcc_4_8_2_release)

34967

+++ b/src/gcc/testsuite/g++.dg/ext/traits1.C (.../branches/gcc-4_8-branch)

34968

@@ -0,0 +1,4 @@

34969

+// PR c++/58504

34970

+

34971

+template<bool = __has_nothrow_assign(void)> struct A {};

34972

+A<> a;

34973

Index: gcc/testsuite/g++.dg/ext/attribute-test-4.C

34974

===================================================================

34975

--- a/src/gcc/testsuite/g++.dg/ext/attribute-test-4.C (.../tags/gcc_4_8_2_release)

34976

+++ b/src/gcc/testsuite/g++.dg/ext/attribute-test-4.C (.../branches/gcc-4_8-branch)

34977

@@ -49,3 +49,4 @@

34978

34979

/* Ignore a warning that is irrelevant to the purpose of this test. */

34980

/* { dg-prune-output ".*GCC vector returned by reference.*" } */

34981

+/* { dg-prune-output "changes the ABI" } */

34982

Index: gcc/testsuite/g++.dg/ext/stmtexpr15.C

34983

===================================================================

34984

--- a/src/gcc/testsuite/g++.dg/ext/stmtexpr15.C (.../tags/gcc_4_8_2_release)

34985

+++ b/src/gcc/testsuite/g++.dg/ext/stmtexpr15.C (.../branches/gcc-4_8-branch)

34986

@@ -0,0 +1,7 @@

34987

+// PR c++/59097

34988

+// { dg-options "" }

34989

+

34990

+void foo()

34991

+{

34992

+ int x[({ return; })]; // { dg-error "non-integral" }

34993

+}

34994

Index: gcc/testsuite/g++.dg/ext/vector25.C

34995

===================================================================

34996

--- a/src/gcc/testsuite/g++.dg/ext/vector25.C (.../tags/gcc_4_8_2_release)

34997

+++ b/src/gcc/testsuite/g++.dg/ext/vector25.C (.../branches/gcc-4_8-branch)

34998

@@ -0,0 +1,6 @@

34999

+volatile int i __attribute__((vector_size(8)));

35000

+

35001

+void foo()

35002

+{

35003

+ i += i;

35004

+}

35005

Index: gcc/testsuite/g++.dg/ext/builtin-bswap1.C

35006

===================================================================

35007

--- a/src/gcc/testsuite/g++.dg/ext/builtin-bswap1.C (.../tags/gcc_4_8_2_release)

35008

+++ b/src/gcc/testsuite/g++.dg/ext/builtin-bswap1.C (.../branches/gcc-4_8-branch)

35009

@@ -0,0 +1,22 @@

35010

+// PR c/37743

35011

+// { dg-do compile }

35012

+

35013

+#if defined(__UINT32_TYPE__) && defined(__INT32_TYPE__)

35014

+

35015

+void foo (__UINT32_TYPE__);

35016

+void foo (__INT32_TYPE__);

35017

+

35018

+void

35019

+bar (__UINT32_TYPE__ x)

35020

+{

35021

+ foo (__builtin_bswap32 (x));

35022

+}

35023

+

35024

+#else

35025

+

35026

+void

35027

+bar ()

35028

+{

35029

+}

35030

+

35031

+#endif

35032

Index: gcc/testsuite/g++.dg/ext/attrib48.C

35033

===================================================================

35034

--- a/src/gcc/testsuite/g++.dg/ext/attrib48.C (.../tags/gcc_4_8_2_release)

35035

+++ b/src/gcc/testsuite/g++.dg/ext/attrib48.C (.../branches/gcc-4_8-branch)

35036

@@ -0,0 +1,6 @@

35037

+// PR c++/54652

35038

+

35039

+typedef unsigned L __attribute__ ((aligned));

35040

+typedef unsigned L __attribute__ ((aligned));

35041

+

35042

+L l;

35043

Index: gcc/testsuite/g++.dg/ext/vector27.C

35044

===================================================================

35045

--- a/src/gcc/testsuite/g++.dg/ext/vector27.C (.../tags/gcc_4_8_2_release)

35046

+++ b/src/gcc/testsuite/g++.dg/ext/vector27.C (.../branches/gcc-4_8-branch)

35047

@@ -0,0 +1,7 @@

35048

+// PR c++/58845

35049

+

35050

+void foo()

35051

+{

35052

+ int v __attribute__((vector_size(8)));

35053

+ v = v || v; // { dg-bogus "" "" { xfail *-*-* } }

35054

+}

35055

Index: gcc/testsuite/g++.dg/ext/timevar2.C

35056

===================================================================

35057

--- a/src/gcc/testsuite/g++.dg/ext/timevar2.C (.../tags/gcc_4_8_2_release)

35058

+++ b/src/gcc/testsuite/g++.dg/ext/timevar2.C (.../branches/gcc-4_8-branch)

35059

@@ -0,0 +1,14 @@

35060

+// PR c++/57524

35061

+// { dg-options "-ftime-report" }

35062

+// { dg-prune-output "wall" }

35063

+// { dg-prune-output "times" }

35064

+// { dg-prune-output "TOTAL" }

35065

+// { dg-prune-output "checks" }

35066

+

35067

+namespace detail {

35068

+namespace indirect_traits {}

35069

+using namespace indirect_traits;

35070

+void fn1() {

35071

+using namespace detail;

35072

+}

35073

+}

35074

Index: gcc/testsuite/g++.dg/ext/attribute-test-1.C

35075

===================================================================

35076

--- a/src/gcc/testsuite/g++.dg/ext/attribute-test-1.C (.../tags/gcc_4_8_2_release)

35077

+++ b/src/gcc/testsuite/g++.dg/ext/attribute-test-1.C (.../branches/gcc-4_8-branch)

35078

@@ -36,3 +36,4 @@

35079

35080

/* Ignore a warning that is irrelevant to the purpose of this test. */

35081

/* { dg-prune-output ".*GCC vector returned by reference.*" } */

35082

+/* { dg-prune-output "changes the ABI" } */

35083

Index: gcc/testsuite/g++.dg/vect/pr60836.cc

35084

===================================================================

35085

--- a/src/gcc/testsuite/g++.dg/vect/pr60836.cc (.../tags/gcc_4_8_2_release)

35086

+++ b/src/gcc/testsuite/g++.dg/vect/pr60836.cc (.../branches/gcc-4_8-branch)

35087

@@ -0,0 +1,39 @@

35088

+// { dg-do compile }

35089

+

35090

+int a, b;

35091

+typedef double (*NormFunc) (const int &);

35092

+int &

35093

+max (int &p1, int &p2)

35094

+{

35095

+ if (p1 < p2)

35096

+ return p2;

35097

+ return p1;

35098

+}

35099

+

35100

+struct A

35101

+{

35102

+ int operator () (int p1, int p2)

35103

+ {

35104

+ return max (p1, p2);

35105

+ }

35106

+};

35107

+template < class, class > double

35108

+norm_ (const int &)

35109

+{

35110

+ char c, d;

35111

+ A e;

35112

+ for (; a; a++)

35113

+ {

35114

+ b = e (b, d);

35115

+ b = e (b, c);

35116

+ }

35117

+}

35118

+

35119

+void

35120

+norm ()

35121

+{

35122

+ static NormFunc f = norm_ < int, A >;

35123

+ f = 0;

35124

+}

35125

+

35126

+// { dg-final { cleanup-tree-dump "vect" } }

35127

Index: gcc/testsuite/g++.dg/vect/pr60729.cc

35128

===================================================================

35129

--- a/src/gcc/testsuite/g++.dg/vect/pr60729.cc (.../tags/gcc_4_8_2_release)

35130

+++ b/src/gcc/testsuite/g++.dg/vect/pr60729.cc (.../branches/gcc-4_8-branch)

35131

@@ -0,0 +1,10 @@

35132

+// { dg-do compile }

35133

+// { dg-additional-options "-ftrapv" }

35134

+

35135

+void doSomething(int dim, double *Y, double *A)

35136

+{

35137

+ for (int k=0; k<dim; k++)

35138

+ Y[k] += __builtin_fabs (A[k]);

35139

+}

35140

+

35141

+// { dg-final { cleanup-tree-dump "vect" } }

35142

Index: gcc/testsuite/g++.dg/opt/pr60849.C

35143

===================================================================

35144

--- a/src/gcc/testsuite/g++.dg/opt/pr60849.C (.../tags/gcc_4_8_2_release)

35145

+++ b/src/gcc/testsuite/g++.dg/opt/pr60849.C (.../branches/gcc-4_8-branch)

35146

@@ -0,0 +1,13 @@

35147

+// { dg-do compile }

35148

+// { dg-options "-O2" }

35149

+

35150

+int g;

35151

+

35152

+extern "C" int isnan ();

35153

+

35154

+void foo(float a) {

35155

+ int (*xx)(...);

35156

+ xx = isnan;

35157

+ if (xx(a))

35158

+ g++;

35159

+}

35160

Index: gcc/testsuite/g++.dg/opt/pr59647.C

35161

===================================================================

35162

--- a/src/gcc/testsuite/g++.dg/opt/pr59647.C (.../tags/gcc_4_8_2_release)

35163

+++ b/src/gcc/testsuite/g++.dg/opt/pr59647.C (.../branches/gcc-4_8-branch)

35164

@@ -0,0 +1,32 @@

35165

+// PR rtl-optimization/59647

35166

+// { dg-do compile }

35167

+// { dg-options "-O2 -fno-tree-vrp" }

35168

+// { dg-additional-options "-msse2 -mfpmath=sse" { target { { i?86-*-* x86_64-*-* } && ia32 } } }

35169

+

35170

+void f1 (int);

35171

+void f2 ();

35172

+double f3 (int);

35173

+

35174

+struct A

35175

+{

35176

+ int f4 () const

35177

+ {

35178

+ if (a == 0)

35179

+ return 1;

35180

+ return 0;

35181

+ }

35182

+ unsigned f5 ()

35183

+ {

35184

+ if (!f4 ())

35185

+ f2 ();

35186

+ return a;

35187

+ }

35188

+ int a;

35189

+};

35190

+

35191

+void

35192

+f6 (A *x)

35193

+{

35194

+ unsigned b = x->f5 ();

35195

+ f1 (b - 1 - f3 (x->f5 () - 1U));

35196

+}

35197

Index: gcc/testsuite/g++.dg/opt/pr59470.C

35198

===================================================================

35199

--- a/src/gcc/testsuite/g++.dg/opt/pr59470.C (.../tags/gcc_4_8_2_release)

35200

+++ b/src/gcc/testsuite/g++.dg/opt/pr59470.C (.../branches/gcc-4_8-branch)

35201

@@ -0,0 +1,188 @@

35202

+// PR middle-end/59470

35203

+// { dg-do run }

35204

+// { dg-options "-O2 -fstack-protector" }

35205

+// { dg-additional-options "-fPIC" { target fpic } }

35206

+// { dg-require-effective-target fstack_protector }

35207

+

35208

+struct A

35209

+{

35210

+ int a1;

35211

+ A () throw () : a1 (0) {}

35212

+};

35213

+

35214

+struct B

35215

+{

35216

+ unsigned int b1 () throw ();

35217

+};

35218

+

35219

+__attribute__((noinline, noclone)) unsigned int

35220

+B::b1 () throw ()

35221

+{

35222

+ asm volatile ("" : : : "memory");

35223

+ return 0;

35224

+}

35225

+

35226

+struct C

35227

+{

35228

+ const A **c1;

35229

+ void c2 (const A *, unsigned int);

35230

+};

35231

+

35232

+__attribute__((noinline, noclone)) void

35233

+C::c2 (const A *, unsigned int)

35234

+{

35235

+ asm volatile ("" : : : "memory");

35236

+}

35237

+

35238

+struct D

35239

+{

35240

+ C *d1;

35241

+};

35242

+

35243

+struct E

35244

+{

35245

+ int e1;

35246

+ int e2;

35247

+ D e3;

35248

+};

35249

+

35250

+struct F

35251

+{

35252

+ virtual int f1 (const char * s, int n);

35253

+};

35254

+

35255

+struct G

35256

+{

35257

+ F *g1;

35258

+ bool g2;

35259

+ G & g3 (const char * ws, int len)

35260

+ {

35261

+ if (__builtin_expect (!g2, true)

35262

+ && __builtin_expect (this->g1->f1 (ws, len) != len, false))

35263

+ g2 = true;

35264

+ return *this;

35265

+ }

35266

+};

35267

+

35268

+struct H : public A

35269

+{

35270

+ const char *h1;

35271

+ unsigned int h2;

35272

+ bool h3;

35273

+ const char *h4;

35274

+ char h5;

35275

+ char h6;

35276

+ char h7[31];

35277

+ bool h8;

35278

+ H () : h1 (0), h2 (0), h4 (0), h5 (0), h6 (0), h8 (false) {}

35279

+ void h9 (const D &) __attribute__((noinline, noclone));

35280

+};

35281

+

35282

+void

35283

+H::h9 (const D &)

35284

+{

35285

+ h3 = true;

35286

+ __builtin_memset (h7, 0, sizeof (h7));

35287

+ asm volatile ("" : : : "memory");

35288

+};

35289

+

35290

+B b;

35291

+

35292

+inline const H *

35293

+foo (const D &x)

35294

+{

35295

+ const unsigned int i = b.b1 ();

35296

+ const A **j = x.d1->c1;

35297

+ if (!j[i])

35298

+ {

35299

+ H *k = 0;

35300

+ try

35301

+ {

35302

+ k = new H;

35303

+ k->h9 (x);

35304

+ }

35305

+ catch (...)

35306

+ {

35307

+ }

35308

+ x.d1->c2 (k, i);

35309

+ }

35310

+ return static_cast <const H *>(j[i]);

35311

+}

35312

+

35313

+__attribute__((noinline, noclone)) int

35314

+bar (char *x, unsigned long v, const char *y, int z, bool w)

35315

+{

35316

+ asm volatile ("" : : "r" (x), "r" (v), "r" (y) : "memory");

35317

+ asm volatile ("" : : "r" (z), "r" (w) : "memory");

35318

+ return 8;

35319

+}

35320

+

35321

+__attribute__((noinline, noclone)) void

35322

+baz (void *z, const char *g, unsigned int h, char s, E &e, char *n, char *c, int &l)

35323

+{

35324

+ asm volatile ("" : : "r" (z), "r" (g), "r" (h) : "memory");

35325

+ asm volatile ("" : : "r" (s), "r" (&e), "r" (n) : "memory");

35326

+ asm volatile ("" : : "r" (c), "r" (&l) : "memory");

35327

+ if (n == c)

35328

+ __builtin_abort ();

35329

+ int i = 0;

35330

+ asm ("" : "+r" (i));

35331

+ if (i == 0)

35332

+ __builtin_exit (0);

35333

+}

35334

+

35335

+__attribute__((noinline, noclone)) G

35336

+test (void *z, G s, E &x, char, long v)

35337

+{

35338

+ const D &d = x.e3;

35339

+ const H *h = foo (d);

35340

+ const char *q = h->h7;

35341

+ const int f = x.e2;

35342

+ const int i = 5 * sizeof (long);

35343

+ char *c = static_cast <char *>(__builtin_alloca (i));

35344

+ const int b = f & 74;

35345

+ const bool e = (b != 64 && b != 8);

35346

+ const unsigned long u = ((v > 0 || !e) ? (unsigned long) v : -(unsigned long) v);

35347

+ int l = bar (c + i, u, q, f, e);

35348

+ c += i - l;

35349

+ if (h->h3)

35350

+ {

35351

+ char *c2 = static_cast <char *>(__builtin_alloca ((l + 1) * 2));

35352

+ baz (z, h->h1, h->h2, h->h6, x, c2 + 2, c, l);

35353

+ c = c2 + 2;

35354

+ }

35355

+ if (__builtin_expect (e, true))

35356

+ {

35357

+ }

35358

+ else if ((f & 4096) && v)

35359

+ {

35360

+ {

35361

+ const bool m = f & 176;

35362

+ *--c = q[m];

35363

+ *--c = q[1];

35364

+ }

35365

+ }

35366

+ const int w = x.e1;

35367

+ if (w > l)

35368

+ {

35369

+ char * c3 = static_cast <char *>(__builtin_alloca (w));

35370

+ c = c3;

35371

+ }

35372

+ return s.g3 (c, l);

35373

+}

35374

+

35375

+int

35376

+main ()

35377

+{

35378

+ H h;

35379

+ const A *j[1];

35380

+ C c;

35381

+ G g;

35382

+ E e;

35383

+ h.h9 (e.e3);

35384

+ j[0] = &h;

35385

+ c.c1 = j;

35386

+ e.e3.d1 = &c;

35387

+ test (0, g, e, 0, 0);

35388

+ __builtin_abort ();

35389

+}

35390

Index: gcc/testsuite/g++.dg/opt/pr58864.C

35391

===================================================================

35392

--- a/src/gcc/testsuite/g++.dg/opt/pr58864.C (.../tags/gcc_4_8_2_release)

35393

+++ b/src/gcc/testsuite/g++.dg/opt/pr58864.C (.../branches/gcc-4_8-branch)

35394

@@ -0,0 +1,21 @@

35395

+// PR target/58864

35396

+// { dg-do compile }

35397

+// { dg-options "-Os" }

35398

+// { dg-additional-options "-march=i686" { target { { i?86-*-* x86_64-*-* } && ia32 } } }

35399

+

35400

+struct A { A (); ~A (); };

35401

+struct B { B (); };

35402

+

35403

+float d, e;

35404

+

35405

+void

35406

+foo ()

35407

+{

35408

+ A a;

35409

+ float c = d;

35410

+ while (1)

35411

+ {

35412

+ B b;

35413

+ e = c ? -c : 0;

35414

+ }

35415

+}

35416

Index: gcc/testsuite/g++.dg/tree-prof/pr59255.C

35417

===================================================================

35418

--- a/src/gcc/testsuite/g++.dg/tree-prof/pr59255.C (.../tags/gcc_4_8_2_release)

35419

+++ b/src/gcc/testsuite/g++.dg/tree-prof/pr59255.C (.../branches/gcc-4_8-branch)

35420

@@ -0,0 +1,29 @@

35421

+// PR c++/59255

35422

+// { dg-options "-O2 -std=c++11" }

35423

+

35424

+struct S

35425

+{

35426

+ __attribute__((noinline, noclone)) ~S () noexcept (true)

35427

+ {

35428

+ if (fn)

35429

+ fn (1);

35430

+ }

35431

+ void (*fn) (int);

35432

+};

35433

+

35434

+__attribute__((noinline, noclone)) void

35435

+foo (int x)

35436

+{

35437

+ if (x != 1)

35438

+ throw 1;

35439

+}

35440

+

35441

+int

35442

+main ()

35443

+{

35444

+ for (int i = 0; i < 100; i++)

35445

+ {

35446

+ S s;

35447

+ s.fn = foo;

35448

+ }

35449

+}

35450

Index: gcc/testsuite/g++.dg/gomp/for-20.C

35451

===================================================================

35452

--- a/src/gcc/testsuite/g++.dg/gomp/for-20.C (.../tags/gcc_4_8_2_release)

35453

+++ b/src/gcc/testsuite/g++.dg/gomp/for-20.C (.../branches/gcc-4_8-branch)

35454

@@ -0,0 +1,16 @@

35455

+// PR c++/60146

35456

+// { dg-do compile }

35457

+// { dg-options -fopenmp }

35458

+

35459

+int foo() { return 0; }

35460

+

35461

+template<typename T> void bar()

35462

+{

35463

+#pragma omp parallel for

35464

+ for (T i = foo(); i < 8; ++i) {}

35465

+}

35466

+

35467

+void baz()

35468

+{

35469

+ bar<int>();

35470

+}

35471

Index: gcc/testsuite/g++.dg/gomp/pr59297.C

35472

===================================================================

35473

--- a/src/gcc/testsuite/g++.dg/gomp/pr59297.C (.../tags/gcc_4_8_2_release)

35474

+++ b/src/gcc/testsuite/g++.dg/gomp/pr59297.C (.../branches/gcc-4_8-branch)

35475

@@ -0,0 +1,25 @@

35476

+// PR c++/59297

35477

+// { dg-do compile }

35478

+// { dg-options "-fopenmp" }

35479

+

35480

+template <typename T>

35481

+struct A

35482

+{

35483

+ ~A ();

35484

+ const T &operator[] (int) const;

35485

+};

35486

+

35487

+struct B

35488

+{

35489

+ int &operator () (A <int>);

35490

+};

35491

+

35492

+void

35493

+foo (B &x, int &z)

35494

+{

35495

+ A<A<int> > y;

35496

+ #pragma omp atomic

35497

+ x (y[0]) += 1;

35498

+ #pragma omp atomic

35499

+ z += x(y[1]);

35500

+}

35501

Index: gcc/testsuite/g++.dg/diagnostic/pr59838.C

35502

===================================================================

35503

--- a/src/gcc/testsuite/g++.dg/diagnostic/pr59838.C (.../tags/gcc_4_8_2_release)

35504

+++ b/src/gcc/testsuite/g++.dg/diagnostic/pr59838.C (.../branches/gcc-4_8-branch)

35505

@@ -0,0 +1,4 @@

35506

+// PR c++/59838

35507

+// { dg-do compile }

35508

+

35509

+enum E { a, b = (E) a }; // { dg-error "conversion to incomplete type" }

35510

Index: gcc/testsuite/g++.dg/diagnostic/pedantic.C

35511

===================================================================

35512

--- a/src/gcc/testsuite/g++.dg/diagnostic/pedantic.C (.../tags/gcc_4_8_2_release)

35513

+++ b/src/gcc/testsuite/g++.dg/diagnostic/pedantic.C (.../branches/gcc-4_8-branch)

35514

@@ -0,0 +1,11 @@

35515

+// { dg-do compile }

35516

+// { dg-options "-pedantic" }

35517

+typedef void F(void);

35518

+

35519

+void foo()

35520

+{

35521

+ void* p = 0;

35522

+ F* f1 = reinterpret_cast<F*>(p); // { dg-warning "ISO" }

35523

+#pragma GCC diagnostic ignored "-pedantic"

35524

+ F* f2 = reinterpret_cast<F*>(p);

35525

+}

35526

Index: gcc/testsuite/g++.dg/diagnostic/pr58979.C

35527

===================================================================

35528

--- a/src/gcc/testsuite/g++.dg/diagnostic/pr58979.C (.../tags/gcc_4_8_2_release)

35529

+++ b/src/gcc/testsuite/g++.dg/diagnostic/pr58979.C (.../branches/gcc-4_8-branch)

35530

@@ -0,0 +1,4 @@

35531

+// PR c++/58979

35532

+// { dg-do compile }

35533

+

35534

+int i = 0->*0; // { dg-error "invalid type argument of" }

35535

Index: gcc/testsuite/g++.dg/conversion/simd1.C

35536

===================================================================

35537

--- a/src/gcc/testsuite/g++.dg/conversion/simd1.C (.../tags/gcc_4_8_2_release)

35538

+++ b/src/gcc/testsuite/g++.dg/conversion/simd1.C (.../branches/gcc-4_8-branch)

35539

@@ -1,4 +1,5 @@

35540

/* { dg-do compile } */

35541

+/* { dg-options "-msse2" { target { i?86-*-* x86_64-*-* } } } */

35542

35543

/* Test overload resolution of vector types.

35544

From Janis Johnson and Paolo Bonzini, based on PR/16882 */

35545

@@ -17,7 +18,7 @@

35546

void foo ()

35547

{

35548

vss = vld(i, vscp); /* { dg-error "no matching function for call" } */

35549

- // { dg-message "candidate" "candidate note" { target *-*-* } 19 }

35550

+ // { dg-message "candidate" "candidate note" { target *-*-* } 20 }

35551

vss = vld(i, vssp);

35552

vss = vld(i, cvssp);

35553

}

35554

Index: gcc/testsuite/g++.dg/tls/thread_local8.C

35555

===================================================================

35556

--- a/src/gcc/testsuite/g++.dg/tls/thread_local8.C (.../tags/gcc_4_8_2_release)

35557

+++ b/src/gcc/testsuite/g++.dg/tls/thread_local8.C (.../branches/gcc-4_8-branch)

35558

@@ -0,0 +1,12 @@

35559

+// PR c++/55800

35560

+// { dg-options "-std=c++11" }

35561

+// { dg-require-alias "" }

35562

+// { dg-require-effective-target tls }

35563

+// { dg-final { scan-assembler "_ZTH12foo_instance" { target tls_native } } }

35564

+

35565

+struct foo

35566

+{

35567

+ foo();

35568

+};

35569

+

35570

+thread_local foo foo_instance;

35571

Index: gcc/testsuite/g++.dg/tls/thread_local-ice2.C

35572

===================================================================

35573

--- a/src/gcc/testsuite/g++.dg/tls/thread_local-ice2.C (.../tags/gcc_4_8_2_release)

35574

+++ b/src/gcc/testsuite/g++.dg/tls/thread_local-ice2.C (.../branches/gcc-4_8-branch)

35575

@@ -0,0 +1,11 @@

35576

+// PR c++/58672

35577

+// { dg-options "-std=c++11" }

35578

+// { dg-require-effective-target tls }

35579

+

35580

+struct A

35581

+{

35582

+ A(int);

35583

+ i; // { dg-error "" }

35584

+};

35585

+

35586

+thread_local A a(0);

35587

Index: gcc/testsuite/g++.dg/pr60769.C

35588

===================================================================

35589

--- a/src/gcc/testsuite/g++.dg/pr60769.C (.../tags/gcc_4_8_2_release)

35590

+++ b/src/gcc/testsuite/g++.dg/pr60769.C (.../branches/gcc-4_8-branch)

35591

@@ -0,0 +1,43 @@

35592

+/* { dg-do compile } */

35593

+/* { dg-options "-O" } */

35594

+

35595

+template <class T> void fun(T);

35596

+struct B {};

35597

+struct R {

35598

+ int *x;

35599

+ B f;

35600

+};

35601

+R v(int &, R);

35602

+void rfun(R &);

35603

+struct A {

35604

+ void m_fn2(R p1) {

35605

+ R a = p1;

35606

+ rfun(p1);

35607

+ fun(this);

35608

+ fun(a);

35609

+ }

35610

+};

35611

+struct J {

35612

+ A ep;

35613

+ A ap;

35614

+ int c2a;

35615

+ void m_fn1(R &p2) {

35616

+ R d, e, b;

35617

+ v(c2a, p2);

35618

+ e = v(c2a, b);

35619

+ ap.m_fn2(e);

35620

+ v(c2a, p2);

35621

+ d = v(c2a, b);

35622

+ ep.m_fn2(d);

35623

+ }

35624

+};

35625

+struct N {

35626

+ int &p_;

35627

+ J cfo;

35628

+};

35629

+void fn3(N&n) {

35630

+ R h;

35631

+ n.cfo.m_fn1(h);

35632

+}

35633

+extern N &c;

35634

+void fn1() { fn3(c); }

35635

Index: gcc/testsuite/g++.dg/tm/pr60004.C

35636

===================================================================

35637

--- a/src/gcc/testsuite/g++.dg/tm/pr60004.C (.../tags/gcc_4_8_2_release)

35638

+++ b/src/gcc/testsuite/g++.dg/tm/pr60004.C (.../branches/gcc-4_8-branch)

35639

@@ -0,0 +1,10 @@

35640

+// { dg-do compile }

35641

+// { dg-options "-fgnu-tm" }

35642

+

35643

+int a;

35644

+int f() {

35645

+ __transaction_atomic {

35646

+ if (a == 5)

35647

+ return 1;

35648

+ }

35649

+}

35650

Index: gcc/testsuite/g++.dg/tm/noexcept-6.C

35651

===================================================================

35652

--- a/src/gcc/testsuite/g++.dg/tm/noexcept-6.C (.../tags/gcc_4_8_2_release)

35653

+++ b/src/gcc/testsuite/g++.dg/tm/noexcept-6.C (.../branches/gcc-4_8-branch)

35654

@@ -0,0 +1,23 @@

35655

+// { dg-do compile }

35656

+// { dg-options "-fno-exceptions -fgnu-tm -O -std=c++0x -fdump-tree-tmlower" }

35657

+

35658

+struct TrueFalse

35659

+{

35660

+ static constexpr bool v() { return true; }

35661

+};

35662

+

35663

+int global;

35664

+

35665

+template<typename T> int foo()

35666

+{

35667

+ return __transaction_atomic noexcept(T::v()) (global + 1);

35668

+}

35669

+

35670

+int f1()

35671

+{

35672

+ return foo<TrueFalse>();

35673

+}

35674

+

35675

+/* { dg-final { scan-tree-dump-times "eh_must_not_throw" 0 "tmlower" } } */

35676

+/* { dg-final { scan-tree-dump-times "__transaction_atomic" 1 "tmlower" } } */

35677

+/* { dg-final { cleanup-tree-dump "tmlower" } } */

35678

Index: gcc/testsuite/g++.dg/pr59695.C

35679

===================================================================

35680

--- a/src/gcc/testsuite/g++.dg/pr59695.C (.../tags/gcc_4_8_2_release)

35681

+++ b/src/gcc/testsuite/g++.dg/pr59695.C (.../branches/gcc-4_8-branch)

35682

@@ -0,0 +1,125 @@

35683

+

35684

+/* PR target/59695 */

35685

+/* { dg-do run } */

35686

+/* { dg-options "-O0" } */

35687

+

35688

+#define DEFINE_VIRTUALS_FNS(i) virtual void xxx##i () {} \

35689

+ virtual void foo1_##i () {}\

35690

+ virtual void foo2_##i () {}\

35691

+ virtual void foo3_##i () {}\

35692

+ virtual void foo4_##i () {}\

35693

+ virtual void foo5_##i () {}\

35694

+ virtual void foo6_##i () {}\

35695

+ virtual void foo7_##i () {}\

35696

+ virtual void foo8_##i () {}\

35697

+ virtual void foo9_##i () {}\

35698

+ virtual void foo10_##i () {}\

35699

+ virtual void foo11_##i () {}\

35700

+ virtual void foo12_##i () {}\

35701

+ virtual void foo13_##i () {}\

35702

+ virtual void foo14_##i () {}\

35703

+ virtual void foo15_##i () {}\

35704

+ virtual void foo16_##i () {}\

35705

+ virtual void foo17_##i () {}\

35706

+ virtual void foo18_##i () {}\

35707

+ virtual void foo19_##i () {}\

35708

+ virtual void foo20_##i () {}\

35709

+ virtual void foo21_##i () {}\

35710

+ virtual void foo22_##i () {}\

35711

+

35712

+class base_class_2

35713

+{

35714

+

35715

+public:

35716

+ /* Define lots of virtual functions */

35717

+ DEFINE_VIRTUALS_FNS (1)

35718

+ DEFINE_VIRTUALS_FNS (2)

35719

+ DEFINE_VIRTUALS_FNS (3)

35720

+ DEFINE_VIRTUALS_FNS (4)

35721

+ DEFINE_VIRTUALS_FNS (5)

35722

+ DEFINE_VIRTUALS_FNS (6)

35723

+ DEFINE_VIRTUALS_FNS (7)

35724

+ DEFINE_VIRTUALS_FNS (8)

35725

+ DEFINE_VIRTUALS_FNS (9)

35726

+ DEFINE_VIRTUALS_FNS (10)

35727

+ DEFINE_VIRTUALS_FNS (11)

35728

+ DEFINE_VIRTUALS_FNS (12)

35729

+ DEFINE_VIRTUALS_FNS (13)

35730

+ DEFINE_VIRTUALS_FNS (14)

35731

+ DEFINE_VIRTUALS_FNS (15)

35732

+ DEFINE_VIRTUALS_FNS (16)

35733

+ DEFINE_VIRTUALS_FNS (17)

35734

+ DEFINE_VIRTUALS_FNS (18)

35735

+ DEFINE_VIRTUALS_FNS (19)

35736

+ DEFINE_VIRTUALS_FNS (20)

35737

+

35738

+ base_class_2();

35739

+ virtual ~base_class_2 ();

35740

+};

35741

+

35742

+base_class_2::base_class_2()

35743

+{

35744

+}

35745

+

35746

+base_class_2::~base_class_2 ()

35747

+{

35748

+}

35749

+

35750

+class base_class_1

35751

+{

35752

+public:

35753

+ virtual ~base_class_1();

35754

+ base_class_1();

35755

+};

35756

+

35757

+base_class_1::base_class_1()

35758

+{

35759

+}

35760

+

35761

+base_class_1::~base_class_1()

35762

+{

35763

+}

35764

+

35765

+class base_Impl_class :

35766

+ virtual public base_class_2, public base_class_1

35767

+{

35768

+public:

35769

+ base_Impl_class ();

35770

+ virtual ~base_Impl_class ();

35771

+};

35772

+

35773

+base_Impl_class::base_Impl_class ()

35774

+{

35775

+}

35776

+

35777

+base_Impl_class::~base_Impl_class ()

35778

+{

35779

+}

35780

+

35781

+

35782

+class test_cls : public base_Impl_class

35783

+{

35784

+public:

35785

+ test_cls();

35786

+ virtual ~test_cls();

35787

+};

35788

+

35789

+test_cls::test_cls()

35790

+{

35791

+}

35792

+

35793

+test_cls::~test_cls()

35794

+{

35795

+}

35796

+

35797

+int main()

35798

+{

35799

+ test_cls *test = new test_cls;

35800

+ base_class_2 *p1 = test;

35801

+

35802

+ /* PR59695 destructor thunk offsets are not setup

35803

+ correctly resulting in crash. */

35804

+ delete p1;

35805

+ return 0;

35806

+}

35807

+

35808

Index: gcc/testsuite/g++.dg/cpp0x/initlist79.C

35809

===================================================================

35810

--- a/src/gcc/testsuite/g++.dg/cpp0x/initlist79.C (.../tags/gcc_4_8_2_release)

35811

+++ b/src/gcc/testsuite/g++.dg/cpp0x/initlist79.C (.../branches/gcc-4_8-branch)

35812

@@ -0,0 +1,8 @@

35813

+// PR c++/59646

35814

+// { dg-require-effective-target c++11 }

35815

+

35816

+#include <initializer_list>

35817

+

35818

+struct A {};

35819

+

35820

+std::initializer_list<volatile A> x = {{}};

35821

Index: gcc/testsuite/g++.dg/cpp0x/enum_base2.C

35822

===================================================================

35823

--- a/src/gcc/testsuite/g++.dg/cpp0x/enum_base2.C (.../tags/gcc_4_8_2_release)

35824

+++ b/src/gcc/testsuite/g++.dg/cpp0x/enum_base2.C (.../branches/gcc-4_8-branch)

35825

@@ -0,0 +1,9 @@

35826

+// PR c++/60187

35827

+// { dg-require-effective-target c++11 }

35828

+

35829

+template<typename... T> struct A

35830

+{

35831

+ enum E : T {}; // { dg-error "parameter pack" }

35832

+};

35833

+

35834

+A<int> a;

35835

Index: gcc/testsuite/g++.dg/cpp0x/lambda/lambda-nsdmi5.C

35836

===================================================================

35837

--- a/src/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-nsdmi5.C (.../tags/gcc_4_8_2_release)

35838

+++ b/src/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-nsdmi5.C (.../branches/gcc-4_8-branch)

35839

@@ -0,0 +1,7 @@

35840

+// PR c++/58596

35841

+// { dg-do compile { target c++11 } }

35842

+

35843

+struct A

35844

+{

35845

+ int i = [] { return decltype(i)(); }();

35846

+};

35847

Index: gcc/testsuite/g++.dg/cpp0x/variadic149.C

35848

===================================================================

35849

--- a/src/gcc/testsuite/g++.dg/cpp0x/variadic149.C (.../tags/gcc_4_8_2_release)

35850

+++ b/src/gcc/testsuite/g++.dg/cpp0x/variadic149.C (.../branches/gcc-4_8-branch)

35851

@@ -0,0 +1,11 @@

35852

+// PR c++/60248

35853

+// { dg-options "-std=c++11 -g -fabi-version=2" }

35854

+

35855

+template<int...> struct A {};

35856

+

35857

+template<> struct A<0>

35858

+{

35859

+ typedef enum { e } B;

35860

+};

35861

+

35862

+A<0> a;

35863

Index: gcc/testsuite/g++.dg/cpp0x/constexpr-53094-2.C

35864

===================================================================

35865

--- a/src/gcc/testsuite/g++.dg/cpp0x/constexpr-53094-2.C (.../tags/gcc_4_8_2_release)

35866

+++ b/src/gcc/testsuite/g++.dg/cpp0x/constexpr-53094-2.C (.../branches/gcc-4_8-branch)

35867

@@ -2,6 +2,7 @@

35868

// { dg-options "-std=gnu++11" }

35869

// Ignore warning on some powerpc-ibm-aix configurations.

35870

// { dg-prune-output "non-standard ABI extension" }

35871

+// { dg-prune-output "changes the ABI" }

35872

35873

typedef float __attribute__ ((vector_size (4 * sizeof (float)))) V4;

35874

constexpr V4 build (float x, float y, float z) { return (V4){ x, y, z, 0 };}

35875

Index: gcc/testsuite/g++.dg/cpp0x/defaulted48.C

35876

===================================================================

35877

--- a/src/gcc/testsuite/g++.dg/cpp0x/defaulted48.C (.../tags/gcc_4_8_2_release)

35878

+++ b/src/gcc/testsuite/g++.dg/cpp0x/defaulted48.C (.../branches/gcc-4_8-branch)

35879

@@ -0,0 +1,17 @@

35880

+// PR c++/60108

35881

+// { dg-require-effective-target c++11 }

35882

+

35883

+template<int> struct A

35884

+{

35885

+ virtual ~A();

35886

+};

35887

+

35888

+template<typename> struct B : A<0>, A<1>

35889

+{

35890

+ ~B() = default;

35891

+};

35892

+

35893

+struct C : B<bool>

35894

+{

35895

+ C() {}

35896

+};

35897

Index: gcc/testsuite/g++.dg/cpp0x/alias-decl-41.C

35898

===================================================================

35899

--- a/src/gcc/testsuite/g++.dg/cpp0x/alias-decl-41.C (.../tags/gcc_4_8_2_release)

35900

+++ b/src/gcc/testsuite/g++.dg/cpp0x/alias-decl-41.C (.../branches/gcc-4_8-branch)

35901

@@ -0,0 +1,18 @@

35902

+// PR c++/60182

35903

+// { dg-require-effective-target c++11 }

35904

+

35905

+class B {};

35906

+template <typename> using __allocator_base = B;

35907

+template <typename> class F : __allocator_base<int> {};

35908

+class C {};

35909

+template <typename, typename = F<int> > class G : C {};

35910

+template <typename> class D;

35911

+class A {

35912

+ using Container = G<D<char>>;

35913

+ A();

35914

+ A(D<char> const &);

35915

+ Container m_elements;

35916

+};

35917

+template <template <class, class> class C, class A = F<D<int>>>

35918

+void doSomething(C<D<char>, A> &);

35919

+A::A(D<char> const &) : A() { doSomething(m_elements); }

35920

Index: gcc/testsuite/g++.dg/cpp0x/nsdmi-union3.C

35921

===================================================================

35922

--- a/src/gcc/testsuite/g++.dg/cpp0x/nsdmi-union3.C (.../tags/gcc_4_8_2_release)

35923

+++ b/src/gcc/testsuite/g++.dg/cpp0x/nsdmi-union3.C (.../branches/gcc-4_8-branch)

35924

@@ -0,0 +1,10 @@

35925

+// PR c++/58965

35926

+// { dg-require-effective-target c++11 }

35927

+

35928

+void foo()

35929

+{

35930

+ static union

35931

+ {

35932

+ int i = i;

35933

+ };

35934

+}

35935

Index: gcc/testsuite/g++.dg/cpp0x/variadic144.C

35936

===================================================================

35937

--- a/src/gcc/testsuite/g++.dg/cpp0x/variadic144.C (.../tags/gcc_4_8_2_release)

35938

+++ b/src/gcc/testsuite/g++.dg/cpp0x/variadic144.C (.../branches/gcc-4_8-branch)

35939

@@ -0,0 +1,15 @@

35940

+// PR c++/56060

35941

+// { dg-do compile { target c++11 } }

35942

+

35943

+template<typename T> struct baz { };

35944

+template<typename T> T bar();

35945

+

35946

+template<typename T, typename ... U>

35947

+baz<decltype(bar<T>()(bar<U> ...))> // { dg-error "cannot be used" }

35948

+foo();

35949

+

35950

+int main()

35951

+{

35952

+ foo<int>(); // { dg-error "no matching" }

35953

+ return 0;

35954

+}

35955

Index: gcc/testsuite/g++.dg/cpp0x/enum18.C

35956

===================================================================

35957

--- a/src/gcc/testsuite/g++.dg/cpp0x/enum18.C (.../tags/gcc_4_8_2_release)

35958

+++ b/src/gcc/testsuite/g++.dg/cpp0x/enum18.C (.../branches/gcc-4_8-branch)

35959

@@ -4,5 +4,5 @@

35960

int main(void) {

35961

enum e {};

35962

e ev;

35963

- ev.e::~e_u(); // { dg-error "e_u. has not been declared" }

35964

+ ev.e::~e_u(); // { dg-error "" }

35965

}

35966

Index: gcc/testsuite/g++.dg/cpp0x/noexcept22.C

35967

===================================================================

35968

--- a/src/gcc/testsuite/g++.dg/cpp0x/noexcept22.C (.../tags/gcc_4_8_2_release)

35969

+++ b/src/gcc/testsuite/g++.dg/cpp0x/noexcept22.C (.../branches/gcc-4_8-branch)

35970

@@ -0,0 +1,21 @@

35971

+// PR c++/60046

35972

+// { dg-require-effective-target c++11 }

35973

+

35974

+constexpr bool foo () { return noexcept (true); }

35975

+template <typename T>

35976

+struct V

35977

+{

35978

+ void bar (V &) noexcept (foo ()) {}

35979

+};

35980

+template <typename T>

35981

+struct W : public V <int>

35982

+{

35983

+ void bar (W &x) { V <int>::bar (x); }

35984

+};

35985

+

35986

+int

35987

+main ()

35988

+{

35989

+ W <int> a, b;

35990

+ a.bar (b);

35991

+}

35992

Index: gcc/testsuite/g++.dg/cpp0x/initlist76.C

35993

===================================================================

35994

--- a/src/gcc/testsuite/g++.dg/cpp0x/initlist76.C (.../tags/gcc_4_8_2_release)

35995

+++ b/src/gcc/testsuite/g++.dg/cpp0x/initlist76.C (.../branches/gcc-4_8-branch)

35996

@@ -0,0 +1,5 @@

35997

+// PR c++/58812

35998

+// { dg-require-effective-target c++11 }

35999

+

36000

+int i;

36001

+int&& j{{ i }}; // { dg-error "too many braces" }

36002

Index: gcc/testsuite/g++.dg/cpp0x/access02.C

36003

===================================================================

36004

--- a/src/gcc/testsuite/g++.dg/cpp0x/access02.C (.../tags/gcc_4_8_2_release)

36005

+++ b/src/gcc/testsuite/g++.dg/cpp0x/access02.C (.../branches/gcc-4_8-branch)

36006

@@ -0,0 +1,39 @@

36007

+// PR c++/58954

36008

+// { dg-require-effective-target c++11 }

36009

+

36010

+template<class T>

36011

+T&& declval();

36012

+

36013

+template<class T>

36014

+struct foo_argument

36015

+{

36016

+ template<class Ret, class C, class Arg>

36017

+ static Arg test(Ret (C::*)(Arg));

36018

+

36019

+ typedef decltype(test(&T::template foo<>)) type;

36020

+};

36021

+

36022

+template<class T, class>

36023

+struct dependent { typedef T type; };

36024

+

36025

+template<class T>

36026

+struct base

36027

+{

36028

+ template<class Ignore = void>

36029

+ auto foo(int i) -> decltype(declval<

36030

+ typename dependent<T&, Ignore>::type

36031

+ >().foo_impl(i));

36032

+};

36033

+

36034

+struct derived : base<derived>

36035

+{

36036

+ friend struct base<derived>;

36037

+private:

36038

+ int foo_impl(int i);

36039

+};

36040

+

36041

+int main()

36042

+{

36043

+ foo_argument<derived>::type var = 0;

36044

+ return var;

36045

+}

36046

Index: gcc/testsuite/g++.dg/cpp0x/constexpr-template6.C

36047

===================================================================

36048

--- a/src/gcc/testsuite/g++.dg/cpp0x/constexpr-template6.C (.../tags/gcc_4_8_2_release)

36049

+++ b/src/gcc/testsuite/g++.dg/cpp0x/constexpr-template6.C (.../branches/gcc-4_8-branch)

36050

@@ -0,0 +1,20 @@

36051

+// PR c++/59268

36052

+// { dg-do compile }

36053

+// { dg-options "-std=c++11" }

36054

+

36055

+template <typename>

36056

+struct A

36057

+{

36058

+ constexpr A (int) {}

36059

+ virtual void foo ()

36060

+ {

36061

+ constexpr A<void> a (0);

36062

+ }

36063

+};

36064

+

36065

+void

36066

+bar ()

36067

+{

36068

+ A<int> a (3);

36069

+ a.foo ();

36070

+}

36071

Index: gcc/testsuite/g++.dg/cpp0x/initlist78.C

36072

===================================================================

36073

--- a/src/gcc/testsuite/g++.dg/cpp0x/initlist78.C (.../tags/gcc_4_8_2_release)

36074

+++ b/src/gcc/testsuite/g++.dg/cpp0x/initlist78.C (.../branches/gcc-4_8-branch)

36075

@@ -0,0 +1,12 @@

36076

+// PR c++/58639

36077

+// { dg-require-effective-target c++11 }

36078

+

36079

+struct node {

36080

+ node &parent;

36081

+};

36082

+

36083

+struct vector {

36084

+ node n;

36085

+};

36086

+

36087

+vector v({}); // { dg-error "" }

36088

Index: gcc/testsuite/g++.dg/cpp0x/variadic148.C

36089

===================================================================

36090

--- a/src/gcc/testsuite/g++.dg/cpp0x/variadic148.C (.../tags/gcc_4_8_2_release)

36091

+++ b/src/gcc/testsuite/g++.dg/cpp0x/variadic148.C (.../branches/gcc-4_8-branch)

36092

@@ -0,0 +1,6 @@

36093

+// PR c++/59989

36094

+// { dg-require-effective-target c++11 }

36095

+

36096

+template<typename T> struct X {};

36097

+template<template<typename...> class D, typename ...U> int test(D<U...>*);

36098

+int n = test<X, int>(0); // { dg-error "no match" }

36099

Index: gcc/testsuite/g++.dg/cpp0x/nsdmi9.C

36100

===================================================================

36101

--- a/src/gcc/testsuite/g++.dg/cpp0x/nsdmi9.C (.../tags/gcc_4_8_2_release)

36102

+++ b/src/gcc/testsuite/g++.dg/cpp0x/nsdmi9.C (.../branches/gcc-4_8-branch)

36103

@@ -0,0 +1,13 @@

36104

+// PR c++/58162

36105

+// { dg-require-effective-target c++11 }

36106

+

36107

+struct A {

36108

+ A();

36109

+ A(A&&);

36110

+};

36111

+

36112

+struct B {

36113

+ A const a = A();

36114

+};

36115

+

36116

+B b;

36117

Index: gcc/testsuite/g++.dg/cpp0x/deleted3.C

36118

===================================================================

36119

--- a/src/gcc/testsuite/g++.dg/cpp0x/deleted3.C (.../tags/gcc_4_8_2_release)

36120

+++ b/src/gcc/testsuite/g++.dg/cpp0x/deleted3.C (.../branches/gcc-4_8-branch)

36121

@@ -0,0 +1,11 @@

36122

+// PR c++/60216

36123

+// { dg-require-effective-target c++11 }

36124

+

36125

+struct A

36126

+{

36127

+ template<typename T> A(T) = delete;

36128

+};

36129

+

36130

+template<> A::A<int>(int) {}

36131

+

36132

+A a(0);

36133

Index: gcc/testsuite/g++.dg/cpp0x/variadic150.C

36134

===================================================================

36135

--- a/src/gcc/testsuite/g++.dg/cpp0x/variadic150.C (.../tags/gcc_4_8_2_release)

36136

+++ b/src/gcc/testsuite/g++.dg/cpp0x/variadic150.C (.../branches/gcc-4_8-branch)

36137

@@ -0,0 +1,9 @@

36138

+// PR c++/60219

36139

+// { dg-require-effective-target c++11 }

36140

+

36141

+template<typename..., int> void foo();

36142

+

36143

+void bar()

36144

+{

36145

+ foo<0>; // { dg-error "" }

36146

+}

36147

Index: gcc/testsuite/g++.dg/cpp0x/static_assert9.C

36148

===================================================================

36149

--- a/src/gcc/testsuite/g++.dg/cpp0x/static_assert9.C (.../tags/gcc_4_8_2_release)

36150

+++ b/src/gcc/testsuite/g++.dg/cpp0x/static_assert9.C (.../branches/gcc-4_8-branch)

36151

@@ -0,0 +1,7 @@

36152

+// PR c++/58837

36153

+// { dg-require-effective-target c++11 }

36154

+

36155

+void f();

36156

+static_assert(f, "");

36157

+struct A {};

36158

+static_assert(A::~A, ""); // { dg-error "non-static member function" }

36159

Index: gcc/testsuite/g++.dg/cpp0x/variadic145.C

36160

===================================================================

36161

--- a/src/gcc/testsuite/g++.dg/cpp0x/variadic145.C (.../tags/gcc_4_8_2_release)

36162

+++ b/src/gcc/testsuite/g++.dg/cpp0x/variadic145.C (.../branches/gcc-4_8-branch)

36163

@@ -0,0 +1,13 @@

36164

+// PR c++/59730

36165

+// { dg-do compile { target c++11 } }

36166

+

36167

+template <typename> void declval();

36168

+template <typename> void forward();

36169

+template <typename> class D;

36170

+template <typename _Functor, typename... _Bound_args>

36171

+class D <_Functor(_Bound_args...)> {

36172

+ template <typename... _Args, decltype(declval<_Functor>)>

36173

+ void operator()(...) {

36174

+ 0(forward<_Args>...);

36175

+ }

36176

+};

36177

Index: gcc/testsuite/g++.dg/cpp0x/decltype57.C

36178

===================================================================

36179

--- a/src/gcc/testsuite/g++.dg/cpp0x/decltype57.C (.../tags/gcc_4_8_2_release)

36180

+++ b/src/gcc/testsuite/g++.dg/cpp0x/decltype57.C (.../branches/gcc-4_8-branch)

36181

@@ -0,0 +1,8 @@

36182

+// PR c++/58633

36183

+// { dg-do compile { target c++11 } }

36184

+

36185

+void foo(int i)

36186

+{

36187

+ typedef int I;

36188

+ decltype(i.I::~I())* p;

36189

+}

36190

Index: gcc/testsuite/g++.dg/cpp0x/variadic147.C

36191

===================================================================

36192

--- a/src/gcc/testsuite/g++.dg/cpp0x/variadic147.C (.../tags/gcc_4_8_2_release)

36193

+++ b/src/gcc/testsuite/g++.dg/cpp0x/variadic147.C (.../branches/gcc-4_8-branch)

36194

@@ -0,0 +1,10 @@

36195

+// PR c++/58466

36196

+// { dg-require-effective-target c++11 }

36197

+

36198

+template<char, char...> struct A;

36199

+

36200

+template<typename> struct B;

36201

+

36202

+template<char... C> struct B<A<C...>> {};

36203

+

36204

+B<A<'X'>> b;

36205

Index: gcc/testsuite/g++.dg/eh/uncaught1.C

36206

===================================================================

36207

--- a/src/gcc/testsuite/g++.dg/eh/uncaught1.C (.../tags/gcc_4_8_2_release)

36208

+++ b/src/gcc/testsuite/g++.dg/eh/uncaught1.C (.../branches/gcc-4_8-branch)

36209

@@ -13,7 +13,7 @@

36210

36211

static Check const data[] = {

36212

{ 0, 0, false }, // construct [0]

36213

- { 1, 0, true }, // [1] = [0]

36214

+ { 1, 0, false }, // [1] = [0]

36215

{ 0, 0, true }, // destruct [0]

36216

{ 2, 1, true }, // [2] = [1]

36217

{ 2, 2, true }, // destruct [2]

36218

Index: gcc/testsuite/g++.dg/eh/ppc64-sighandle-cr.C

36219

===================================================================

36220

--- a/src/gcc/testsuite/g++.dg/eh/ppc64-sighandle-cr.C (.../tags/gcc_4_8_2_release)

36221

+++ b/src/gcc/testsuite/g++.dg/eh/ppc64-sighandle-cr.C (.../branches/gcc-4_8-branch)

36222

@@ -0,0 +1,54 @@

36223

+// { dg-do run { target { powerpc64*-*-linux* } } }

36224

+// { dg-options "-fexceptions -fnon-call-exceptions" }

36225

+

36226

+#include <signal.h>

36227

+#include <stdlib.h>

36228

+#include <fenv.h>

36229

+

36230

+#define SET_CR(R,V) __asm__ __volatile__ ("mtcrf %0,%1" : : "n" (1<<(7-R)), "r" (V<<(4*(7-R))) : "cr" #R)

36231

+#define GET_CR(R) ({ int tmp; __asm__ __volatile__ ("mfcr %0" : "=r" (tmp)); (tmp >> 4*(7-R)) & 15; })

36232

+

36233

+void sighandler (int signo, siginfo_t * si, void * uc)

36234

+{

36235

+ SET_CR(2, 3);

36236

+ SET_CR(3, 2);

36237

+ SET_CR(4, 1);

36238

+

36239

+ throw 0;

36240

+}

36241

+

36242

+float test (float a, float b) __attribute__ ((__noinline__));

36243

+float test (float a, float b)

36244

+{

36245

+ float x;

36246

+ asm ("mtcrf %1,%2" : "=f" (x) : "n" (1 << (7-3)), "r" (0), "0" (b) : "cr3");

36247

+ return a / x;

36248

+}

36249

+

36250

+int main ()

36251

+{

36252

+ struct sigaction sa;

36253

+ int status;

36254

+

36255

+ sa.sa_sigaction = sighandler;

36256

+ sa.sa_flags = SA_SIGINFO;

36257

+

36258

+ status = sigaction (SIGFPE, & sa, NULL);

36259

+

36260

+ feenableexcept (FE_DIVBYZERO);

36261

+

36262

+ SET_CR(2, 6);

36263

+ SET_CR(3, 9);

36264

+ SET_CR(4, 12);

36265

+

36266

+ try {

36267

+ test (1, 0);

36268

+ }

36269

+ catch (...) {

36270

+ return GET_CR(2) != 6 || GET_CR(3) != 9 || GET_CR(4) != 12;

36271

+ }

36272

+

36273

+ return 1;

36274

+}

36275

+

36276

+

36277

Index: gcc/testsuite/g++.dg/eh/uncaught4.C

36278

===================================================================

36279

--- a/src/gcc/testsuite/g++.dg/eh/uncaught4.C (.../tags/gcc_4_8_2_release)

36280

+++ b/src/gcc/testsuite/g++.dg/eh/uncaught4.C (.../branches/gcc-4_8-branch)

36281

@@ -0,0 +1,29 @@

36282

+// PR c++/41174

36283

+// { dg-do run }

36284

+

36285

+#include <exception>

36286

+

36287

+#define assert(E) if (!(E)) __builtin_abort();

36288

+

36289

+struct e {

36290

+ e()

36291

+ {

36292

+ assert( !std::uncaught_exception() );

36293

+ try {

36294

+ throw 1;

36295

+ } catch (int i) {

36296

+ assert( !std::uncaught_exception() );

36297

+ throw;

36298

+ }

36299

+ }

36300

+};

36301

+

36302

+int main()

36303

+{

36304

+ try {

36305

+ throw e();

36306

+ } catch (int i) {

36307

+ assert( !std::uncaught_exception() );

36308

+ }

36309

+ assert( !std::uncaught_exception() );

36310

+}

36311

Index: gcc/testsuite/g++.dg/inherit/virtual11.C

36312

===================================================================

36313

--- a/src/gcc/testsuite/g++.dg/inherit/virtual11.C (.../tags/gcc_4_8_2_release)

36314

+++ b/src/gcc/testsuite/g++.dg/inherit/virtual11.C (.../branches/gcc-4_8-branch)

36315

@@ -0,0 +1,17 @@

36316

+// PR c++/59031

36317

+// { dg-do compile }

36318

+// { dg-options "-fdump-tree-gimple " }

36319

+class B {

36320

+ public:

36321

+ virtual int add (int a, int b) {return a+ b;}

36322

+};

36323

+

36324

+class D : public B {

36325

+};

36326

+

36327

+int foo (int a, int b) {

36328

+ D d;

36329

+ return d.add(a, b);

36330

+}

36331

+// { dg-final { scan-tree-dump-not "OBJ_TYPE_REF" "gimple" } }

36332

+// { dg-final { cleanup-tree-dump "gimple" } }

36333

Index: gcc/testsuite/g++.dg/torture/pr38565.C

36334

===================================================================

36335

--- a/src/gcc/testsuite/g++.dg/torture/pr38565.C (.../tags/gcc_4_8_2_release)

36336

+++ b/src/gcc/testsuite/g++.dg/torture/pr38565.C (.../branches/gcc-4_8-branch)

36337

@@ -1,6 +1,7 @@

36338

// { dg-do compile }

36339

// Ignore warning on some powerpc-linux configurations.

36340

// { dg-prune-output "non-standard ABI extension" }

36341

+// { dg-prune-output "changes the ABI" }

36342

#define vector __attribute__((vector_size(16) ))

36343

vector unsigned int f(int a)

36344

{

36345

Index: gcc/testsuite/g++.dg/torture/pr57499.C

36346

===================================================================

36347

--- a/src/gcc/testsuite/g++.dg/torture/pr57499.C (.../tags/gcc_4_8_2_release)

36348

+++ b/src/gcc/testsuite/g++.dg/torture/pr57499.C (.../branches/gcc-4_8-branch)

36349

@@ -0,0 +1,14 @@

36350

+// PR middle-end/57499

36351

+// { dg-do compile }

36352

+

36353

+struct S

36354

+{

36355

+ ~S () __attribute__ ((noreturn)) {} // { dg-warning "function does return" }

36356

+};

36357

+

36358

+void

36359

+foo ()

36360

+{

36361

+ S s;

36362

+ throw 1;

36363

+}

36364

Index: gcc/testsuite/g++.dg/torture/pr60750.C

36365

===================================================================

36366

--- a/src/gcc/testsuite/g++.dg/torture/pr60750.C (.../tags/gcc_4_8_2_release)

36367

+++ b/src/gcc/testsuite/g++.dg/torture/pr60750.C (.../branches/gcc-4_8-branch)

36368

@@ -0,0 +1,21 @@

36369

+// { dg-do run }

36370

+// { dg-options "-std=c++11" }

36371

+

36372

+#include <string>

36373

+#include <stdexcept>

36374

+

36375

+const std::string err_prefix = "Problem: ";

36376

+void thrower (std::string msg)

36377

+{

36378

+ throw std::runtime_error(err_prefix + std::move(msg));

36379

+}

36380

+

36381

+int main(int argc, char **argv)

36382

+{

36383

+ try {

36384

+ std::string base = "hello";

36385

+ thrower(std::move(base));

36386

+ } catch (const std::runtime_error &e) {

36387

+ }

36388

+ return 0;

36389

+}

36390

Index: gcc/testsuite/g++.dg/torture/pr59163.C

36391

===================================================================

36392

--- a/src/gcc/testsuite/g++.dg/torture/pr59163.C (.../tags/gcc_4_8_2_release)

36393

+++ b/src/gcc/testsuite/g++.dg/torture/pr59163.C (.../branches/gcc-4_8-branch)

36394

@@ -0,0 +1,30 @@

36395

+// PR target/59163

36396

+// { dg-do run }

36397

+

36398

+struct A { float a[4]; };

36399

+struct B { int b; A a; };

36400

+

36401

+__attribute__((noinline, noclone)) void

36402

+bar (A &a)

36403

+{

36404

+ if (a.a[0] != 36.0f || a.a[1] != 42.0f || a.a[2] != 48.0f || a.a[3] != 54.0f)

36405

+ __builtin_abort ();

36406

+}

36407

+

36408

+__attribute__((noinline, noclone)) void

36409

+foo (A &a)

36410

+{

36411

+ int i;

36412

+ A c = a;

36413

+ for (i = 0; i < 4; i++)

36414

+ c.a[i] *= 6.0f;

36415

+ a = c;

36416

+ bar (a);

36417

+}

36418

+

36419

+int

36420

+main ()

36421

+{

36422

+ B b = { 5, { 6, 7, 8, 9 } };

36423

+ foo (b.a);

36424

+}

36425

Index: gcc/testsuite/g++.dg/torture/pr60895.C

36426

===================================================================

36427

--- a/src/gcc/testsuite/g++.dg/torture/pr60895.C (.../tags/gcc_4_8_2_release)

36428

+++ b/src/gcc/testsuite/g++.dg/torture/pr60895.C (.../branches/gcc-4_8-branch)

36429

@@ -0,0 +1,32 @@

36430

+// { dg-do compile }

36431

+

36432

+struct C

36433

+{

36434

+ double elems[3];

36435

+};

36436

+

36437

+C

36438

+foo ()

36439

+{

36440

+ C a;

36441

+ double *f = a.elems;

36442

+ int b;

36443

+ for (; b;)

36444

+ {

36445

+ *f = 0;

36446

+ ++f;

36447

+ }

36448

+ return a;

36449

+}

36450

+

36451

+struct J

36452

+{

36453

+ C c;

36454

+ __attribute__((always_inline)) J () : c (foo ()) {}

36455

+};

36456

+

36457

+void

36458

+bar ()

36459

+{

36460

+ J ();

36461

+}

36462

Index: gcc/testsuite/g++.dg/ipa/pr60640-1.C

36463

===================================================================

36464

--- a/src/gcc/testsuite/g++.dg/ipa/pr60640-1.C (.../tags/gcc_4_8_2_release)

36465

+++ b/src/gcc/testsuite/g++.dg/ipa/pr60640-1.C (.../branches/gcc-4_8-branch)

36466

@@ -0,0 +1,50 @@

36467

+// { dg-do compile }

36468

+// { dg-options "-O3" }

36469

+

36470

+class ASN1Object

36471

+{

36472

+public:

36473

+ virtual ~ASN1Object ();

36474

+};

36475

+class A

36476

+{

36477

+ virtual unsigned m_fn1 () const;

36478

+};

36479

+class B

36480

+{

36481

+public:

36482

+ ASN1Object Element;

36483

+ virtual unsigned m_fn1 (bool) const;

36484

+};

36485

+template <class BASE> class C : public BASE

36486

+{

36487

+};

36488

+

36489

+class D : ASN1Object, public B

36490

+{

36491

+};

36492

+class G : public D

36493

+{

36494

+ unsigned m_fn1 (bool) const {}

36495

+};

36496

+class F : A

36497

+{

36498

+public:

36499

+ F (A);

36500

+ unsigned m_fn1 () const

36501

+ {

36502

+ int a;

36503

+ a = m_fn2 ().m_fn1 (0);

36504

+ return a;

36505

+ }

36506

+ const B &m_fn2 () const { return m_groupParameters; }

36507

+ C<G> m_groupParameters;

36508

+};

36509

+template <class D> void BenchMarkKeyAgreement (int *, int *, int)

36510

+{

36511

+ A f;

36512

+ D d (f);

36513

+}

36514

+

36515

+void BenchmarkAll2 () { BenchMarkKeyAgreement<F>(0, 0, 0); }

36516

+

36517

Index: gcc/testsuite/g++.dg/ipa/pr60640-2.C

36518

===================================================================

36519

--- a/src/gcc/testsuite/g++.dg/ipa/pr60640-2.C (.../tags/gcc_4_8_2_release)

36520

+++ b/src/gcc/testsuite/g++.dg/ipa/pr60640-2.C (.../branches/gcc-4_8-branch)

36521

@@ -0,0 +1,15 @@

36522

+// { dg-do compile }

36523

+// { dg-options "-O3" }

36524

+

36525

+struct B { virtual unsigned f () const; };

36526

+struct C { virtual void f (); };

36527

+struct F { virtual unsigned f (bool) const; ~F (); };

36528

+struct J : C, F {};

36529

+struct G : J { unsigned f (bool) const { return 0; } };

36530

+struct H : B

36531

+{

36532

+ H (int);

36533

+ unsigned f () const { return ((const F &) h).f (0); }

36534

+ G h;

36535

+};

36536

+H h (0);

36537

Index: gcc/testsuite/g++.dg/ipa/pr60640-3.C

36538

===================================================================

36539

--- a/src/gcc/testsuite/g++.dg/ipa/pr60640-3.C (.../tags/gcc_4_8_2_release)

36540

+++ b/src/gcc/testsuite/g++.dg/ipa/pr60640-3.C (.../branches/gcc-4_8-branch)

36541

@@ -0,0 +1,81 @@

36542

+// { dg-do run }

36543

+// { dg-options "-O3" }

36544

+

36545

+struct Distraction

36546

+{

36547

+ char fc[8];

36548

+ virtual Distraction * return_self ()

36549

+ { return this; }

36550

+};

36551

+

36552

+namespace {

36553

+

36554

+struct A;

36555

+static A * __attribute__ ((noinline, noclone)) get_an_A ();

36556

+

36557

+static int go;

36558

+

36559

+struct A

36560

+{

36561

+ int fi;

36562

+

36563

+ A () : fi(777) {}

36564

+ A (int pi) : fi (pi) {}

36565

+ virtual A * foo (int p) = 0;

36566

+};

36567

+

36568

+struct B;

36569

+static B * __attribute__ ((noinline, noclone)) get_a_B ();

36570

+

36571

+struct B : public Distraction, A

36572

+{

36573

+ B () : Distraction(), A() { }

36574

+ B (int pi) : Distraction (), A (pi) {}

36575

+ virtual B * foo (int p)

36576

+ {

36577

+ int o = fi;

36578

+ for (int i = 0; i < p; i++)

36579

+ o += i + i * i;

36580

+ go = o;

36581

+

36582

+ return get_a_B ();

36583

+ }

36584

+};

36585

+

36586

+

36587

+struct B gb1 (1111), gb2 (2);

36588

+static B * __attribute__ ((noinline, noclone))

36589

+get_a_B ()

36590

+{

36591

+ return &gb1;

36592

+}

36593

+

36594

+static A * __attribute__ ((noinline, noclone))

36595

+get_an_A ()

36596

+{

36597

+ return &gb2;

36598

+}

36599

+

36600

+}

36601

+

36602

+static int __attribute__ ((noinline, noclone))

36603

+get_a_number ()

36604

+{

36605

+ return 5;

36606

+}

36607

+

36608

+extern "C" void abort (void);

36609

+

36610

+int main (int argc, char *argv[])

36611

+{

36612

+ for (int i = 0; i < get_a_number (); i++)

36613

+ {

36614

+ struct A *p = get_an_A ();

36615

+ struct A *r = p->foo (4);

36616

+ if (r->fi != 1111)

36617

+ abort ();

36618

+ if (go != 22)

36619

+ abort ();

36620

+ }

36621

+ return 0;

36622

+}

36623

Index: gcc/testsuite/g++.dg/ipa/pr60419.C

36624

===================================================================

36625

--- a/src/gcc/testsuite/g++.dg/ipa/pr60419.C (.../tags/gcc_4_8_2_release)

36626

+++ b/src/gcc/testsuite/g++.dg/ipa/pr60419.C (.../branches/gcc-4_8-branch)

36627

@@ -0,0 +1,80 @@

36628

+// PR middle-end/60419

36629

+// { dg-do compile }

36630

+// { dg-options "-O2" }

36631

+

36632

+struct C

36633

+{

36634

+};

36635

+

36636

+struct I : C

36637

+{

36638

+ I ();

36639

+};

36640

+

36641

+struct J

36642

+{

36643

+ void foo ();

36644

+ J ();

36645

+ virtual void foo (int &, int);

36646

+};

36647

+

36648

+template <class>

36649

+struct D

36650

+{

36651

+ virtual void foo (I &) const;

36652

+ void bar ()

36653

+ {

36654

+ I p;

36655

+ foo (p);

36656

+ }

36657

+};

36658

+

36659

+struct K : J, public D<int>

36660

+{

36661

+};

36662

+

36663

+struct F

36664

+{

36665

+ K *operator->();

36666

+};

36667

+

36668

+struct N : public K

36669

+{

36670

+ void foo (int &, int);

36671

+ I n;

36672

+ void foo (I &) const {}

36673

+};

36674

+

36675

+struct L : J

36676

+{

36677

+ F l;

36678

+};

36679

+

36680

+struct M : F

36681

+{

36682

+ L *operator->();

36683

+};

36684

+

36685

+struct G

36686

+{

36687

+ G ();

36688

+};

36689

+

36690

+M h;

36691

+

36692

+G::G ()

36693

+try

36694

+{

36695

+ N f;

36696

+ f.bar ();

36697

+ throw;

36698

+}

36699

+catch (int)

36700

+{

36701

+}

36702

+

36703

+void

36704

+baz ()

36705

+{

36706

+ h->l->bar ();

36707

+}

36708

Index: gcc/testsuite/g++.dg/template/ref7.C

36709

===================================================================

36710

--- a/src/gcc/testsuite/g++.dg/template/ref7.C (.../tags/gcc_4_8_2_release)

36711

+++ b/src/gcc/testsuite/g++.dg/template/ref7.C (.../branches/gcc-4_8-branch)

36712

@@ -0,0 +1,16 @@

36713

+// PR c++/60274

36714

+

36715

+typedef const char *const& ProtocolIdType;

36716

+

36717

+template <ProtocolIdType protocolId>

36718

+struct C {

36719

+ typedef int ProtocolVersion;

36720

+ struct D {

36721

+ ProtocolVersion GetProtocolVersion();

36722

+ };

36723

+};

36724

+template <ProtocolIdType protocolId>

36725

+typename C<protocolId>::ProtocolVersion C<protocolId>::D::GetProtocolVersion()

36726

+{

36727

+ return 1;

36728

+}

36729

Index: gcc/testsuite/g++.dg/template/using28.C

36730

===================================================================

36731

--- a/src/gcc/testsuite/g++.dg/template/using28.C (.../tags/gcc_4_8_2_release)

36732

+++ b/src/gcc/testsuite/g++.dg/template/using28.C (.../branches/gcc-4_8-branch)

36733

@@ -0,0 +1,17 @@

36734

+// PR c++/37140

36735

+

36736

+struct C

36737

+{

36738

+ static const int block_size = 1;

36739

+};

36740

+

36741

+template <typename T> struct A {

36742

+ typedef C type;

36743

+};

36744

+

36745

+template <typename T> struct B : public A<T> {

36746

+ using typename A<T>::type;

36747

+ static const int block_size = type::block_size;

36748

+};

36749

+

36750

+template class B<int>;

36751

Index: gcc/testsuite/g++.dg/template/shadow1.C

36752

===================================================================

36753

--- a/src/gcc/testsuite/g++.dg/template/shadow1.C (.../tags/gcc_4_8_2_release)

36754

+++ b/src/gcc/testsuite/g++.dg/template/shadow1.C (.../branches/gcc-4_8-branch)

36755

@@ -0,0 +1,4 @@

36756

+// PR c++/58632

36757

+

36758

+template<template<int I> class A> // { dg-message "shadows" }

36759

+class A {}; // { dg-error "declaration" }

36760

Index: gcc/testsuite/g++.dg/template/partial14.C

36761

===================================================================

36762

--- a/src/gcc/testsuite/g++.dg/template/partial14.C (.../tags/gcc_4_8_2_release)

36763

+++ b/src/gcc/testsuite/g++.dg/template/partial14.C (.../branches/gcc-4_8-branch)

36764

@@ -0,0 +1,16 @@

36765

+// PR c++/59044

36766

+

36767

+template <class T>

36768

+class C {

36769

+private:

36770

+ template <T a, T b>

36771

+ struct Implementation {};

36772

+public:

36773

+ typedef typename Implementation<0, 0>::Typedef Type;

36774

+};

36775

+

36776

+template <class T>

36777

+template <T b>

36778

+struct C<T>::Implementation<0, b> { typedef void Typedef; };

36779

+

36780

+template class C<unsigned>;

36781

Index: gcc/testsuite/g++.dg/template/using27.C

36782

===================================================================

36783

--- a/src/gcc/testsuite/g++.dg/template/using27.C (.../tags/gcc_4_8_2_release)

36784

+++ b/src/gcc/testsuite/g++.dg/template/using27.C (.../branches/gcc-4_8-branch)

36785

@@ -0,0 +1,33 @@

36786

+// PR c++/37140

36787

+

36788

+struct X

36789

+{

36790

+ typedef int nested_type;

36791

+};

36792

+

36793

+template <class T>

36794

+struct A

36795

+{

36796

+ typedef X type;

36797

+};

36798

+

36799

+template <class T>

36800

+struct B : A<T>

36801

+{

36802

+ using typename A<T>::type;

36803

+ typename type::nested_type x;

36804

+};

36805

+

36806

+template <class T>

36807

+struct C : B<T>

36808

+{

36809

+ using typename B<T>::type;

36810

+ typename type::nested_type y;

36811

+};

36812

+

36813

+struct D : C<int>

36814

+{

36815

+ using C<int>::type;

36816

+ type::nested_type z;

36817

+};

36818

+

36819

Index: gcc/testsuite/g++.dg/template/using29.C

36820

===================================================================

36821

--- a/src/gcc/testsuite/g++.dg/template/using29.C (.../tags/gcc_4_8_2_release)

36822

+++ b/src/gcc/testsuite/g++.dg/template/using29.C (.../branches/gcc-4_8-branch)

36823

@@ -0,0 +1,21 @@

36824

+// PR c++/58047

36825

+

36826

+template <int N>

36827

+struct print_arg { };

36828

+

36829

+struct const_holder {

36830

+ static const int CONSTANT = 42;

36831

+};

36832

+

36833

+template <typename T>

36834

+struct identity {

36835

+ typedef T type;

36836

+};

36837

+

36838

+template <class T>

36839

+struct test_case : public identity<T> {

36840

+ using typename identity<T>::type;

36841

+ print_arg<type::CONSTANT> printer;

36842

+};

36843

+

36844

+template struct test_case<const_holder>;

36845

Index: gcc/testsuite/g++.dg/template/partial15.C

36846

===================================================================

36847

--- a/src/gcc/testsuite/g++.dg/template/partial15.C (.../tags/gcc_4_8_2_release)

36848

+++ b/src/gcc/testsuite/g++.dg/template/partial15.C (.../branches/gcc-4_8-branch)

36849

@@ -0,0 +1,19 @@

36850

+// PR c++/57043

36851

+// { dg-do link }

36852

+

36853

+template<typename D> struct complex { };

36854

+

36855

+template<typename Tp>

36856

+complex<Tp>

36857

+pow(const complex<Tp>& x, const complex<Tp>& y) { return complex<Tp>(); }

36858

+

36859

+template<typename T, typename U>

36860

+struct promote_2 { typedef T type; };

36861

+

36862

+template<typename Tp, typename Up>

36863

+complex<typename promote_2<Tp, Up>::type>

36864

+pow(const complex<Tp>& x, const complex<Up>& y);

36865

+

36866

+complex<double> (*powcc)(const complex<double>&, const complex<double>&) = pow;

36867

+

36868

+int main() {}

36869

Index: gcc/testsuite/c-c++-common/cpp/pr60400-1.h

36870

===================================================================

36871

--- a/src/gcc/testsuite/c-c++-common/cpp/pr60400-1.h (.../tags/gcc_4_8_2_release)

36872

+++ b/src/gcc/testsuite/c-c++-common/cpp/pr60400-1.h (.../branches/gcc-4_8-branch)

36873

@@ -0,0 +1,3 @@

36874

+??=ifndef PR60400_1_H

36875

+??=define PR60400_1_H

36876

+??=endif

36877

Index: gcc/testsuite/c-c++-common/cpp/pr60400-2.h

36878

===================================================================

36879

--- a/src/gcc/testsuite/c-c++-common/cpp/pr60400-2.h (.../tags/gcc_4_8_2_release)

36880

+++ b/src/gcc/testsuite/c-c++-common/cpp/pr60400-2.h (.../branches/gcc-4_8-branch)

36881

@@ -0,0 +1,4 @@

36882

+??=ifndef PR60400_2_H

36883

+??=define PR60400_2_H

36884

+??=include "pr60400-1.h"

36885

+??=endif

36886

Index: gcc/testsuite/c-c++-common/cpp/pr60400.c

36887

===================================================================

36888

--- a/src/gcc/testsuite/c-c++-common/cpp/pr60400.c (.../tags/gcc_4_8_2_release)

36889

+++ b/src/gcc/testsuite/c-c++-common/cpp/pr60400.c (.../branches/gcc-4_8-branch)

36890

@@ -0,0 +1,13 @@

36891

+/* PR preprocessor/60400 */

36892

+/* { dg-do compile } */

36893

+/* { dg-options "-trigraphs -Wtrigraphs" } */

36894

+

36895

+??=include "pr60400-1.h"

36896

+??=include "pr60400-2.h"

36897

+

36898

+/* { dg-warning "trigraph" "" { target *-*-* } 1 } */

36899

+/* { dg-warning "trigraph" "" { target *-*-* } 2 } */

36900

+/* { dg-warning "trigraph" "" { target *-*-* } 3 } */

36901

+/* { dg-warning "trigraph" "" { target *-*-* } 4 } */

36902

+/* { dg-warning "trigraph" "" { target *-*-* } 5 } */

36903

+/* { dg-warning "trigraph" "" { target *-*-* } 6 } */

36904

Index: gcc/testsuite/c-c++-common/cpp/pr58844-1.c

36905

===================================================================

36906

--- a/src/gcc/testsuite/c-c++-common/cpp/pr58844-1.c (.../tags/gcc_4_8_2_release)

36907

+++ b/src/gcc/testsuite/c-c++-common/cpp/pr58844-1.c (.../branches/gcc-4_8-branch)

36908

@@ -0,0 +1,8 @@

36909

+/* PR preprocessor/58844 */

36910

+/* { dg-do compile } */

36911

+/* { dg-options "-ftrack-macro-expansion=0" } */

36912

+

36913

+#define A x######x

36914

+int A = 1;

36915

+#define A x######x /* { dg-message "previous definition" } */

36916

+#define A x##x /* { dg-warning "redefined" } */

36917

Index: gcc/testsuite/c-c++-common/cpp/pr58844-2.c

36918

===================================================================

36919

--- a/src/gcc/testsuite/c-c++-common/cpp/pr58844-2.c (.../tags/gcc_4_8_2_release)

36920

+++ b/src/gcc/testsuite/c-c++-common/cpp/pr58844-2.c (.../branches/gcc-4_8-branch)

36921

@@ -0,0 +1,8 @@

36922

+/* PR preprocessor/58844 */

36923

+/* { dg-do compile } */

36924

+/* { dg-options "-ftrack-macro-expansion=2" } */

36925

+

36926

+#define A x######x

36927

+int A = 1;

36928

+#define A x######x /* { dg-message "previous definition" } */

36929

+#define A x##x /* { dg-warning "redefined" } */

36930

Index: gcc/testsuite/c-c++-common/convert-vec-1.c

36931

===================================================================

36932

--- a/src/gcc/testsuite/c-c++-common/convert-vec-1.c (.../tags/gcc_4_8_2_release)

36933

+++ b/src/gcc/testsuite/c-c++-common/convert-vec-1.c (.../branches/gcc-4_8-branch)

36934

@@ -1,3 +1,4 @@

36935

/* { dg-do compile } */

36936

+/* { dg-prune-output "changes the ABI" } */

36937

typedef float v2sf __attribute__ ((vector_size (8)));

36938

v2sf sub (void) { return (v2sf) 0.0; } /* { dg-error "can't convert" } */

36939

Index: gcc/testsuite/c-c++-common/pr60101.c

36940

===================================================================

36941

--- a/src/gcc/testsuite/c-c++-common/pr60101.c (.../tags/gcc_4_8_2_release)

36942

+++ b/src/gcc/testsuite/c-c++-common/pr60101.c (.../branches/gcc-4_8-branch)

36943

@@ -0,0 +1,112 @@

36944

+/* PR c/60101 */

36945

+/* { dg-do compile } */

36946

+/* { dg-options "-O2 -Wall" } */

36947

+

36948

+extern int *a, b, *c, *d;

36949

+

36950

+void

36951

+foo (double _Complex *x, double _Complex *y, double _Complex *z, unsigned int l, int w)

36952

+{

36953

+ unsigned int e = (unsigned int) a[3];

36954

+ double _Complex (*v)[l][4][e][l][4] = (double _Complex (*)[l][4][e][l][4]) z;

36955

+ double _Complex (*f)[l][b][l] = (double _Complex (*)[l][b][l]) y;

36956

+ unsigned int g = c[0] * c[1] * c[2];

36957

+ unsigned int h = d[0] + c[0] * (d[1] + c[1] * d[2]);

36958

+ unsigned int i;

36959

+

36960

+ for (i = 0; i < e; i++)

36961

+ {

36962

+ int j = e * d[3] + i;

36963

+

36964

+ unsigned int n0, n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11;

36965

+ float _Complex s = 0.;

36966

+ unsigned int t = 0;

36967

+

36968

+ for (n0 = 0; n0 < l; n0++)

36969

+ for (n1 = 0; n1 < l; n1++)

36970

+ for (n2 = 0; n2 < l; n2++)

36971

+ for (n3 = 0; n3 < l; n3++)

36972

+ for (n4 = 0; n4 < l; n4++)

36973

+ for (n5 = 0; n5 < l; n5++)

36974

+ for (n6 = 0; n6 < l; n6++)

36975

+ for (n7 = 0; n7 < l; n7++)

36976

+ for (n8 = 0; n8 < l; n8++)

36977

+ for (n9 = 0; n9 < l; n9++)

36978

+ for (n10 = 0; n10 < l; n10++)

36979

+ for (n11 = 0; n11 < l; n11++)

36980

+ {

36981

+ if (t % g == h)

36982

+ s

36983

+ += f[n0][n4][j][n8] * f[n1][n5][j][n9] * ~(f[n2][n6][w][n10]) * ~(f[n3][n7][w][n11])

36984

+ * (+0.25 * v[0][n2][0][i][n9][1] * v[0][n3][0][i][n5][1] * v[0][n10][0][i][n4][1]

36985

+ * v[0][n7][1][i][n8][0] * v[0][n11][1][i][n1][0] * v[0][n6][1][i][n0][0]

36986

+ + 0.25 * v[0][n2][0][i][n9][1] * v[0][n3][0][i][n5][1] * v[0][n10][0][i][n4][1]

36987

+ * v[0][n11][1][i][n8][0] * v[0][n6][1][i][n1][0] * v[0][n7][1][i][n0][0]

36988

+ - 0.5 * v[0][n2][0][i][n9][1] * v[0][n3][0][i][n5][1] * v[0][n10][0][i][n4][1]

36989

+ * v[0][n11][1][i][n8][0] * v[0][n7][1][i][n1][0] * v[0][n6][1][i][n0][0]

36990

+ + 0.25 * v[0][n2][0][i][n9][1] * v[0][n10][0][i][n5][1] * v[0][n3][0][i][n4][1]

36991

+ * v[0][n7][1][i][n8][0] * v[0][n6][1][i][n1][0] * v[0][n11][1][i][n0][0]

36992

+ - 0.5 * v[0][n2][0][i][n9][1] * v[0][n10][0][i][n5][1] * v[0][n3][0][i][n4][1]

36993

+ * v[0][n11][1][i][n8][0] * v[0][n6][1][i][n1][0] * v[0][n7][1][i][n0][0]

36994

+ + 0.25 * v[0][n2][0][i][n9][1] * v[0][n10][0][i][n5][1] * v[0][n3][0][i][n4][1]

36995

+ * v[0][n11][1][i][n8][0] * v[0][n7][1][i][n1][0] * v[0][n6][1][i][n0][0]

36996

+ + 0.25 * v[0][n3][0][i][n9][1] * v[0][n2][0][i][n5][1] * v[0][n10][0][i][n4][1]

36997

+ * v[0][n6][1][i][n8][0] * v[0][n11][1][i][n1][0] * v[0][n7][1][i][n0][0]

36998

+ - 0.5 * v[0][n3][0][i][n9][1] * v[0][n2][0][i][n5][1] * v[0][n10][0][i][n4][1]

36999

+ * v[0][n11][1][i][n8][0] * v[0][n6][1][i][n1][0] * v[0][n7][1][i][n0][0]

37000

+ + 0.25 * v[0][n3][0][i][n9][1] * v[0][n2][0][i][n5][1] * v[0][n10][0][i][n4][1]

37001

+ * v[0][n11][1][i][n8][0] * v[0][n7][1][i][n1][0] * v[0][n6][1][i][n0][0]

37002

+ + 0.25 * v[0][n3][0][i][n9][1] * v[0][n10][0][i][n5][1] * v[0][n2][0][i][n4][1]

37003

+ * v[0][n6][1][i][n8][0] * v[0][n7][1][i][n1][0] * v[0][n11][1][i][n0][0]

37004

+ + 0.25 * v[0][n3][0][i][n9][1] * v[0][n10][0][i][n5][1] * v[0][n2][0][i][n4][1]

37005

+ * v[0][n11][1][i][n8][0] * v[0][n6][1][i][n1][0] * v[0][n7][1][i][n0][0]

37006

+ - 0.5 * v[0][n3][0][i][n9][1] * v[0][n10][0][i][n5][1] * v[0][n2][0][i][n4][1]

37007

+ * v[0][n11][1][i][n8][0] * v[0][n7][1][i][n1][0] * v[0][n6][1][i][n0][0]

37008

+ + 0.25 * v[0][n10][0][i][n9][1] * v[0][n2][0][i][n5][1] * v[0][n3][0][i][n4][1]

37009

+ * v[0][n6][1][i][n8][0] * v[0][n7][1][i][n1][0] * v[0][n11][1][i][n0][0]

37010

+ - 0.5 * v[0][n10][0][i][n9][1] * v[0][n2][0][i][n5][1] * v[0][n3][0][i][n4][1]

37011

+ * v[0][n6][1][i][n8][0] * v[0][n11][1][i][n1][0] * v[0][n7][1][i][n0][0]

37012

+ - 0.5 * v[0][n10][0][i][n9][1] * v[0][n2][0][i][n5][1] * v[0][n3][0][i][n4][1]

37013

+ * v[0][n7][1][i][n8][0] * v[0][n6][1][i][n1][0] * v[0][n11][1][i][n0][0]

37014

+ + 0.25 * v[0][n10][0][i][n9][1] * v[0][n2][0][i][n5][1] * v[0][n3][0][i][n4][1]

37015

+ * v[0][n7][1][i][n8][0] * v[0][n11][1][i][n1][0] * v[0][n6][1][i][n0][0]

37016

+ + 1. * v[0][n10][0][i][n9][1] * v[0][n2][0][i][n5][1] * v[0][n3][0][i][n4][1]

37017

+ * v[0][n11][1][i][n8][0] * v[0][n6][1][i][n1][0] * v[0][n7][1][i][n0][0]

37018

+ - 0.5 * v[0][n10][0][i][n9][1] * v[0][n2][0][i][n5][1] * v[0][n3][0][i][n4][1]

37019

+ * v[0][n11][1][i][n8][0] * v[0][n7][1][i][n1][0] * v[0][n6][1][i][n0][0]

37020

+ - 0.5 * v[0][n10][0][i][n9][1] * v[0][n3][0][i][n5][1] * v[0][n2][0][i][n4][1]

37021

+ * v[0][n6][1][i][n8][0] * v[0][n7][1][i][n1][0] * v[0][n11][1][i][n0][0]

37022

+ + 0.25 * v[0][n10][0][i][n9][1] * v[0][n3][0][i][n5][1] * v[0][n2][0][i][n4][1]

37023

+ * v[0][n6][1][i][n8][0] * v[0][n11][1][i][n1][0] * v[0][n7][1][i][n0][0]

37024

+ + 0.25 * v[0][n10][0][i][n9][1] * v[0][n3][0][i][n5][1] * v[0][n2][0][i][n4][1]

37025

+ * v[0][n7][1][i][n8][0] * v[0][n6][1][i][n1][0] * v[0][n11][1][i][n0][0]

37026

+ - 0.5 * v[0][n10][0][i][n9][1] * v[0][n3][0][i][n5][1] * v[0][n2][0][i][n4][1]

37027

+ * v[0][n7][1][i][n8][0] * v[0][n11][1][i][n1][0] * v[0][n6][1][i][n0][0]

37028

+ - 0.5 * v[0][n10][0][i][n9][1] * v[0][n3][0][i][n5][1] * v[0][n2][0][i][n4][1]

37029

+ * v[0][n11][1][i][n8][0] * v[0][n6][1][i][n1][0] * v[0][n7][1][i][n0][0]

37030

+ + 1. * v[0][n10][0][i][n9][1] * v[0][n3][0][i][n5][1] * v[0][n2][0][i][n4][1]

37031

+ * v[0][n11][1][i][n8][0] * v[0][n7][1][i][n1][0] * v[0][n6][1][i][n0][0]

37032

+ + 0.5 * v[0][n6][1][i][n4][1] * v[0][n2][0][i][n9][1] * v[0][n3][0][i][n5][1]

37033

+ * v[0][n7][1][i][n1][0] * v[0][n11][1][i][n0][0] * v[0][n10][0][i][n8][0]

37034

+ - 0.25 * v[0][n6][1][i][n4][1] * v[0][n2][0][i][n9][1] * v[0][n3][0][i][n5][1]

37035

+ * v[0][n11][1][i][n1][0] * v[0][n7][1][i][n0][0] * v[0][n10][0][i][n8][0]

37036

+ - 0.25 * v[0][n6][1][i][n4][1] * v[0][n2][0][i][n9][1] * v[0][n3][0][i][n5][1]

37037

+ * v[0][n7][1][i][n8][0] * v[0][n11][1][i][n0][0] * v[0][n10][0][i][n1][0]

37038

+ + 0.25 * v[0][n6][1][i][n4][1] * v[0][n2][0][i][n9][1] * v[0][n3][0][i][n5][1]

37039

+ * v[0][n7][1][i][n8][0] * v[0][n11][1][i][n1][0] * v[0][n10][0][i][n0][0]

37040

+ + 0.25 * v[0][n6][1][i][n4][1] * v[0][n2][0][i][n9][1] * v[0][n3][0][i][n5][1]

37041

+ * v[0][n11][1][i][n8][0] * v[0][n7][1][i][n0][0] * v[0][n10][0][i][n1][0]

37042

+ - 0.5 * v[0][n6][1][i][n4][1] * v[0][n2][0][i][n9][1] * v[0][n3][0][i][n5][1]

37043

+ * v[0][n11][1][i][n8][0] * v[0][n7][1][i][n1][0] * v[0][n10][0][i][n0][0]

37044

+ - 0.25 * v[0][n6][1][i][n4][1] * v[0][n2][0][i][n9][1] * v[0][n10][0][i][n5][1]

37045

+ * v[0][n7][1][i][n1][0] * v[0][n11][1][i][n0][0] * v[0][n3][0][i][n8][0]

37046

+ - 0.25 * v[0][n6][1][i][n4][1] * v[0][n2][0][i][n9][1] * v[0][n10][0][i][n5][1]

37047

+ * v[0][n7][1][i][n8][0] * v[0][n11][1][i][n0][0] * v[0][n3][0][i][n1][0]);

37048

+ t++;

37049

+ }

37050

+ int u = (j - w + b) % b;

37051

+ int q = (j >= w ? +1 : -1);

37052

+ int r = q;

37053

+ x[u] += r * s;

37054

+ }

37055

+}

37056

Index: gcc/testsuite/c-c++-common/pr36282-3.c

37057

===================================================================

37058

--- a/src/gcc/testsuite/c-c++-common/pr36282-3.c (.../tags/gcc_4_8_2_release)

37059

+++ b/src/gcc/testsuite/c-c++-common/pr36282-3.c (.../branches/gcc-4_8-branch)

37060

@@ -0,0 +1,13 @@

37061

+/* PR middle-end/36282 */

37062

+/* { dg-do compile } */

37063

+

37064

+void bar (void);

37065

+#pragma weak bar

37066

+

37067

+extern void *baz (void *dest, const void *src, __SIZE_TYPE__ n);

37068

+extern __typeof (baz) baz __asm("bazfn"); /* { dg-bogus "asm declaration ignored due to conflict with previous rename" } */

37069

+

37070

+void

37071

+foo (void)

37072

+{

37073

+}

37074

Index: gcc/testsuite/c-c++-common/pr59037.c

37075

===================================================================

37076

--- a/src/gcc/testsuite/c-c++-common/pr59037.c (.../tags/gcc_4_8_2_release)

37077

+++ b/src/gcc/testsuite/c-c++-common/pr59037.c (.../branches/gcc-4_8-branch)

37078

@@ -0,0 +1,12 @@

37079

+/* { dg-do compile } */

37080

+/* { dg-options "-O3" } */

37081

+

37082

+typedef int v4si __attribute__ ((vector_size (16)));

37083

+

37084

+int

37085

+main (int argc, char** argv)

37086

+{

37087

+ v4si x = {0,1,2,3};

37088

+ x = (v4si) {(x)[3], (x)[2], (x)[1], (x)[0]};

37089

+ return x[4];

37090

+}

37091

Index: gcc/testsuite/c-c++-common/pr59280.c

37092

===================================================================

37093

--- a/src/gcc/testsuite/c-c++-common/pr59280.c (.../tags/gcc_4_8_2_release)

37094

+++ b/src/gcc/testsuite/c-c++-common/pr59280.c (.../branches/gcc-4_8-branch)

37095

@@ -0,0 +1,4 @@

37096

+/* PR c/59280 */

37097

+/* { dg-do compile } */

37098

+

37099

+void bar (char *) __attribute__((constructor(foo))); /* { dg-error "constructor priorities must be integers|was not declared|constructor priorities are not supported" } */

37100

Index: gcc/testsuite/c-c++-common/pr37743.c

37101

===================================================================

37102

--- a/src/gcc/testsuite/c-c++-common/pr37743.c (.../tags/gcc_4_8_2_release)

37103

+++ b/src/gcc/testsuite/c-c++-common/pr37743.c (.../branches/gcc-4_8-branch)

37104

@@ -0,0 +1,13 @@

37105

+/* PR c/37743 */

37106

+/* This needs to be run only on targets where __UINT32_TYPE__ is defined

37107

+ to unsigned int. */

37108

+/* { dg-do compile { target *-*-linux-gnu* } } */

37109

+/* { dg-options "-Wformat" } */

37110

+

37111

+int foo (const char *, ...) __attribute__ ((format (printf, 1, 2)));

37112

+

37113

+void

37114

+bar (unsigned int x)

37115

+{

37116

+ foo ("%x", __builtin_bswap32 (x));

37117

+}

37118

Index: gcc/testsuite/c-c++-common/fold-divmul-1.c

37119

===================================================================

37120

--- a/src/gcc/testsuite/c-c++-common/fold-divmul-1.c (.../tags/gcc_4_8_2_release)

37121

+++ b/src/gcc/testsuite/c-c++-common/fold-divmul-1.c (.../branches/gcc-4_8-branch)

37122

@@ -0,0 +1,11 @@

37123

+/* { dg-do compile } */

37124

+/* { dg-options "-fdump-tree-original" } */

37125

+

37126

+int *

37127

+fx (int *b, int *e)

37128

+{

37129

+ return b + (e - b);

37130

+}

37131

+

37132

+/* { dg-final { scan-tree-dump-not "/\\\[ex\\\]" "original" } } */

37133

+/* { dg-final { cleanup-tree-dump "original" } } */

37134

Index: gcc/testsuite/c-c++-common/torture/pr58794-1.c

37135

===================================================================

37136

--- a/src/gcc/testsuite/c-c++-common/torture/pr58794-1.c (.../tags/gcc_4_8_2_release)

37137

+++ b/src/gcc/testsuite/c-c++-common/torture/pr58794-1.c (.../branches/gcc-4_8-branch)

37138

@@ -0,0 +1,29 @@

37139

+/* { dg-do compile } */

37140

+

37141

+struct S0

37142

+{

37143

+ int f;

37144

+};

37145

+

37146

+struct S1

37147

+{

37148

+ struct S0 f1;

37149

+ volatile int f2;

37150

+};

37151

+

37152

+struct S2

37153

+{

37154

+ struct S1 g;

37155

+} a, b;

37156

+

37157

+static int *c[1][2] = {{0, (int *)&a.g.f2}};

37158

+static int d;

37159

+

37160

+int

37161

+main ()

37162

+{

37163

+ for (d = 0; d < 1; d++)

37164

+ for (b.g.f1.f = 0; b.g.f1.f < 1; b.g.f1.f++)

37165

+ *c[b.g.f1.f][d + 1] = 0;

37166

+ return 0;

37167

+}

37168

Index: gcc/testsuite/c-c++-common/torture/pr58794-2.c

37169

===================================================================

37170

--- a/src/gcc/testsuite/c-c++-common/torture/pr58794-2.c (.../tags/gcc_4_8_2_release)

37171

+++ b/src/gcc/testsuite/c-c++-common/torture/pr58794-2.c (.../branches/gcc-4_8-branch)

37172

@@ -0,0 +1,21 @@

37173

+/* { dg-do compile } */

37174

+

37175

+struct S

37176

+{

37177

+ volatile int f;

37178

+} a;

37179

+

37180

+unsigned int b;

37181

+

37182

+static int *c[1][2] = {{0, (int *)&a.f}};

37183

+static unsigned int d;

37184

+

37185

+int

37186

+main ()

37187

+{

37188

+ for (; d < 1; d++)

37189

+ for (; b < 1; b++)

37190

+ *c[b][d + 1] = 0;

37191

+

37192

+ return 0;

37193

+}

37194

Index: gcc/testsuite/c-c++-common/torture/pr60026.c

37195

===================================================================

37196

--- a/src/gcc/testsuite/c-c++-common/torture/pr60026.c (.../tags/gcc_4_8_2_release)

37197

+++ b/src/gcc/testsuite/c-c++-common/torture/pr60026.c (.../branches/gcc-4_8-branch)

37198

@@ -0,0 +1,28 @@

37199

+/* PR ipa/60026 */

37200

+/* { dg-do compile } */

37201

+

37202

+struct S { int f; } a;

37203

+

37204

+__attribute__((optimize (0)))

37205

+struct S foo (int x, struct S y)

37206

+{

37207

+ int b = y.f;

37208

+ return a;

37209

+}

37210

+

37211

+void

37212

+bar ()

37213

+{

37214

+ while (a.f)

37215

+ {

37216

+ struct S c = {0};

37217

+ foo (0, c);

37218

+ }

37219

+}

37220

+

37221

+int

37222

+main ()

37223

+{

37224

+ bar ();

37225

+ return 0;

37226

+}

37227

Index: gcc/testsuite/c-c++-common/vector-compare-2.c

37228

===================================================================

37229

--- a/src/gcc/testsuite/c-c++-common/vector-compare-2.c (.../tags/gcc_4_8_2_release)

37230

+++ b/src/gcc/testsuite/c-c++-common/vector-compare-2.c (.../branches/gcc-4_8-branch)

37231

@@ -1,6 +1,7 @@

37232

/* { dg-do compile } */

37233

/* { dg-options "-fno-common" { target hppa*-*-hpux* } } */

37234

/* { dg-options "-mabi=altivec" { target { { powerpc*-*-linux* } && ilp32 } } } */

37235

+/* { dg-options "-msse2" { target { i?86-*-* x86_64-*-* } } } */

37236

/* Ignore warning on some powerpc-ibm-aix configurations. */

37237

/* { dg-prune-output "non-standard ABI extension" } */

37238

37239

Index: gcc/testsuite/c-c++-common/pr36282-4.c

37240

===================================================================

37241

--- a/src/gcc/testsuite/c-c++-common/pr36282-4.c (.../tags/gcc_4_8_2_release)

37242

+++ b/src/gcc/testsuite/c-c++-common/pr36282-4.c (.../branches/gcc-4_8-branch)

37243

@@ -0,0 +1,13 @@

37244

+/* PR middle-end/36282 */

37245

+/* { dg-do compile } */

37246

+

37247

+#pragma weak bar

37248

+void bar (void);

37249

+

37250

+extern void *baz (void *dest, const void *src, __SIZE_TYPE__ n);

37251

+extern __typeof (baz) baz __asm("bazfn"); /* { dg-bogus "asm declaration ignored due to conflict with previous rename" } */

37252

+

37253

+void

37254

+foo (void)

37255

+{

37256

+}

37257

Index: gcc/testsuite/c-c++-common/gomp/pr58809.c

37258

===================================================================

37259

--- a/src/gcc/testsuite/c-c++-common/gomp/pr58809.c (.../tags/gcc_4_8_2_release)

37260

+++ b/src/gcc/testsuite/c-c++-common/gomp/pr58809.c (.../branches/gcc-4_8-branch)

37261

@@ -0,0 +1,31 @@

37262

+/* PR middle-end/58809 */

37263

+/* { dg-do compile } */

37264

+/* { dg-options "-fopenmp" } */

37265

+

37266

+_Complex int j;

37267

+_Complex double d;

37268

+

37269

+void

37270

+foo (void)

37271

+{

37272

+ #pragma omp parallel reduction (&:j) /* { dg-error "has invalid type for" } */

37273

+ ;

37274

+ #pragma omp parallel reduction (|:j) /* { dg-error "has invalid type for" } */

37275

+ ;

37276

+ #pragma omp parallel reduction (^:j) /* { dg-error "has invalid type for" } */

37277

+ ;

37278

+ #pragma omp parallel reduction (min:j) /* { dg-error "has invalid type for" } */

37279

+ ;

37280

+ #pragma omp parallel reduction (max:j) /* { dg-error "has invalid type for" } */

37281

+ ;

37282

+ #pragma omp parallel reduction (&:d) /* { dg-error "has invalid type for" } */

37283

+ ;

37284

+ #pragma omp parallel reduction (|:d) /* { dg-error "has invalid type for" } */

37285

+ ;

37286

+ #pragma omp parallel reduction (^:d) /* { dg-error "has invalid type for" } */

37287

+ ;

37288

+ #pragma omp parallel reduction (min:d) /* { dg-error "has invalid type for" } */

37289

+ ;

37290

+ #pragma omp parallel reduction (max:d) /* { dg-error "has invalid type for" } */

37291

+ ;

37292

+}

37293

Index: gcc/testsuite/c-c++-common/gomp/pr59467.c

37294

===================================================================

37295

--- a/src/gcc/testsuite/c-c++-common/gomp/pr59467.c (.../tags/gcc_4_8_2_release)

37296

+++ b/src/gcc/testsuite/c-c++-common/gomp/pr59467.c (.../branches/gcc-4_8-branch)

37297

@@ -0,0 +1,68 @@

37298

+/* PR libgomp/59467 */

37299

+

37300

+int v;

37301

+

37302

+void

37303

+foo (void)

37304

+{

37305

+ int x = 0, y = 0;

37306

+ #pragma omp parallel

37307

+ {

37308

+ int z;

37309

+ #pragma omp single copyprivate (x) /* { dg-error "is not threadprivate or private in outer context" } */

37310

+ {

37311

+ #pragma omp atomic write

37312

+ x = 6;

37313

+ }

37314

+ #pragma omp atomic read

37315

+ z = x;

37316

+ #pragma omp atomic

37317

+ y += z;

37318

+ }

37319

+ #pragma omp parallel

37320

+ {

37321

+ int z;

37322

+ #pragma omp single copyprivate (v) /* { dg-error "is not threadprivate or private in outer context" } */

37323

+ {

37324

+ #pragma omp atomic write

37325

+ v = 6;

37326

+ }

37327

+ #pragma omp atomic read

37328

+ z = v;

37329

+ #pragma omp atomic

37330

+ y += z;

37331

+ }

37332

+ #pragma omp parallel private (x)

37333

+ {

37334

+ int z;

37335

+ #pragma omp single copyprivate (x)

37336

+ {

37337

+ #pragma omp atomic write

37338

+ x = 6;

37339

+ }

37340

+ #pragma omp atomic read

37341

+ z = x;

37342

+ #pragma omp atomic

37343

+ y += z;

37344

+ }

37345

+ x = 0;

37346

+ #pragma omp parallel reduction (+:x)

37347

+ {

37348

+ #pragma omp single copyprivate (x)

37349

+ {

37350

+ #pragma omp atomic write

37351

+ x = 6;

37352

+ }

37353

+ #pragma omp atomic

37354

+ y += x;

37355

+ }

37356

+ #pragma omp single copyprivate (x)

37357

+ {

37358

+ x = 7;

37359

+ }

37360

+ #pragma omp single copyprivate (v) /* { dg-error "is not threadprivate or private in outer context" } */

37361

+ {

37362

+ #pragma omp atomic write

37363

+ v = 6;

37364

+ }

37365

+}

37366

Index: gcc/testsuite/c-c++-common/pr36282-1.c

37367

===================================================================

37368

--- a/src/gcc/testsuite/c-c++-common/pr36282-1.c (.../tags/gcc_4_8_2_release)

37369

+++ b/src/gcc/testsuite/c-c++-common/pr36282-1.c (.../branches/gcc-4_8-branch)

37370

@@ -0,0 +1,12 @@

37371

+/* PR middle-end/36282 */

37372

+/* { dg-do compile } */

37373

+

37374

+#pragma weak bar

37375

+

37376

+extern void *baz (void *dest, const void *src, __SIZE_TYPE__ n);

37377

+extern __typeof (baz) baz __asm("bazfn"); /* { dg-bogus "asm declaration ignored due to conflict with previous rename" } */

37378

+

37379

+void

37380

+foo (void)

37381

+{

37382

+}

37383

Index: gcc/testsuite/c-c++-common/pr60689.c

37384

===================================================================

37385

--- a/src/gcc/testsuite/c-c++-common/pr60689.c (.../tags/gcc_4_8_2_release)

37386

+++ b/src/gcc/testsuite/c-c++-common/pr60689.c (.../branches/gcc-4_8-branch)

37387

@@ -0,0 +1,10 @@

37388

+/* PR c++/60689 */

37389

+/* { dg-do compile } */

37390

+

37391

+struct S { char x[9]; };

37392

+

37393

+void

37394

+foo (struct S *x, struct S *y, struct S *z)

37395

+{

37396

+ __atomic_exchange (x, y, z, __ATOMIC_SEQ_CST);

37397

+}

37398

Index: gcc/testsuite/c-c++-common/scal-to-vec2.c

37399

===================================================================

37400

--- a/src/gcc/testsuite/c-c++-common/scal-to-vec2.c (.../tags/gcc_4_8_2_release)

37401

+++ b/src/gcc/testsuite/c-c++-common/scal-to-vec2.c (.../branches/gcc-4_8-branch)

37402

@@ -1,6 +1,7 @@

37403

/* { dg-do compile } */

37404

/* { dg-options "-fno-common" { target hppa*-*-hpux* } } */

37405

/* { dg-options "-mabi=altivec" { target { { powerpc*-*-linux* } && ilp32 } } } */

37406

+/* { dg-options "-msse2" { target { i?86-*-* x86_64-*-* } } } */

37407

/* Ignore warning on some powerpc-ibm-aix configurations. */

37408

/* { dg-prune-output "non-standard ABI extension" } */

37409

37410

Index: gcc/testsuite/c-c++-common/pr59032.c

37411

===================================================================

37412

--- a/src/gcc/testsuite/c-c++-common/pr59032.c (.../tags/gcc_4_8_2_release)

37413

+++ b/src/gcc/testsuite/c-c++-common/pr59032.c (.../branches/gcc-4_8-branch)

37414

@@ -0,0 +1,30 @@

37415

+/* { dg-do compile } */

37416

+/* { dg-options "-O2" } */

37417

+

37418

+void

37419

+foo()

37420

+{

37421

+ float v __attribute__((vector_size(8)));

37422

+ v++;

37423

+}

37424

+

37425

+void

37426

+foo2 ()

37427

+{

37428

+ float v __attribute__((vector_size(8)));

37429

+ ++v;

37430

+}

37431

+

37432

+void

37433

+foo3 ()

37434

+{

37435

+ float v __attribute__((vector_size(8)));

37436

+ v--;

37437

+}

37438

+

37439

+void

37440

+foo4 ()

37441

+{

37442

+ float v __attribute__((vector_size(8)));

37443

+ --v;

37444

+}

37445

Index: gcc/testsuite/c-c++-common/pr36282-2.c

37446

===================================================================

37447

--- a/src/gcc/testsuite/c-c++-common/pr36282-2.c (.../tags/gcc_4_8_2_release)

37448

+++ b/src/gcc/testsuite/c-c++-common/pr36282-2.c (.../branches/gcc-4_8-branch)

37449

@@ -0,0 +1,10 @@

37450

+/* PR middle-end/36282 */

37451

+/* { dg-do compile } */

37452

+

37453

+extern void *baz (void *dest, const void *src, __SIZE_TYPE__ n);

37454

+extern __typeof (baz) baz __asm("bazfn"); /* { dg-bogus "asm declaration ignored due to conflict with previous rename" } */

37455

+

37456

+void

37457

+foo (void)

37458

+{

37459

+}

37460

Index: gcc/cp/typeck.c

37461

===================================================================

37462

--- a/src/gcc/cp/typeck.c (.../tags/gcc_4_8_2_release)

37463

+++ b/src/gcc/cp/typeck.c (.../branches/gcc-4_8-branch)

37464

@@ -4103,6 +4103,11 @@

37465

case TRUTH_ORIF_EXPR:

37466

case TRUTH_AND_EXPR:

37467

case TRUTH_OR_EXPR:

37468

+ if (TREE_CODE (type0) == VECTOR_TYPE || TREE_CODE (type1) == VECTOR_TYPE)

37469

+ {

37470

+ sorry ("logical operation on vector type");

37471

+ return error_mark_node;

37472

+ }

37473

result_type = boolean_type_node;

37474

break;

37475

37476

@@ -5010,7 +5015,10 @@

37477

cp_truthvalue_conversion (tree expr)

37478

{

37479

tree type = TREE_TYPE (expr);

37480

- if (TYPE_PTRDATAMEM_P (type))

37481

+ if (TYPE_PTRDATAMEM_P (type)

37482

+ /* Avoid ICE on invalid use of non-static member function. */

37483

+ || (TREE_CODE (expr) == FUNCTION_DECL

37484

+ && DECL_NONSTATIC_MEMBER_FUNCTION_P (expr)))

37485

return build_binary_op (EXPR_LOCATION (expr),

37486

NE_EXPR, expr, nullptr_node, 1);

37487

else if (TYPE_PTR_P (type) || TYPE_PTRMEMFUNC_P (type))

37488

@@ -5588,7 +5596,9 @@

37489

inc = cxx_sizeof_nowarn (TREE_TYPE (argtype));

37490

}

37491

else

37492

- inc = integer_one_node;

37493

+ inc = (TREE_CODE (argtype) == VECTOR_TYPE

37494

+ ? build_one_cst (argtype)

37495

+ : integer_one_node);

37496

37497

inc = cp_convert (argtype, inc, complain);

37498

37499

@@ -6639,7 +6649,7 @@

37500

where possible, and it is necessary in some cases. DR 195

37501

addresses this issue, but as of 2004/10/26 is still in

37502

drafting. */

37503

- warning (0, "ISO C++ forbids casting between pointer-to-function and pointer-to-object");

37504

+ warning (OPT_Wpedantic, "ISO C++ forbids casting between pointer-to-function and pointer-to-object");

37505

return fold_if_not_in_template (build_nop (type, expr));

37506

}

37507

else if (TREE_CODE (type) == VECTOR_TYPE)

37508

@@ -7194,8 +7204,7 @@

37509

side effect associated with any single compound assignment

37510

operator. -- end note ] */

37511

lhs = stabilize_reference (lhs);

37512

- if (TREE_SIDE_EFFECTS (rhs))

37513

- rhs = mark_rvalue_use (rhs);

37514

+ rhs = rvalue (rhs);

37515

rhs = stabilize_expr (rhs, &init);

37516

newrhs = cp_build_binary_op (input_location,

37517

modifycode, lhs, rhs,

37518

@@ -7611,7 +7620,7 @@

37519

/* Handle null pointer to member function conversions. */

37520

if (null_ptr_cst_p (pfn))

37521

{

37522

- pfn = build_c_cast (input_location, type, pfn);

37523

+ pfn = cp_build_c_cast (type, pfn, complain);

37524

return build_ptrmemfunc1 (to_type,

37525

integer_zero_node,

37526

pfn);

37527

Index: gcc/cp/decl.c

37528

===================================================================

37529

--- a/src/gcc/cp/decl.c (.../tags/gcc_4_8_2_release)

37530

+++ b/src/gcc/cp/decl.c (.../branches/gcc-4_8-branch)

37531

@@ -1867,9 +1867,9 @@

37532

/* Merge the data types specified in the two decls. */

37533

newtype = merge_types (TREE_TYPE (newdecl), TREE_TYPE (olddecl));

37534

37535

- /* If merge_types produces a non-typedef type, just use the old type. */

37536

- if (TREE_CODE (newdecl) == TYPE_DECL

37537

- && newtype == DECL_ORIGINAL_TYPE (newdecl))

37538

+ /* For typedefs use the old type, as the new type's DECL_NAME points

37539

+ at newdecl, which will be ggc_freed. */

37540

+ if (TREE_CODE (newdecl) == TYPE_DECL)

37541

newtype = oldtype;

37542

37543

if (TREE_CODE (newdecl) == VAR_DECL)

37544

@@ -8193,7 +8193,9 @@

37545

abi_1_itype = error_mark_node;

37546

}

37547

37548

- size = maybe_constant_value (size);

37549

+ if (INTEGRAL_OR_UNSCOPED_ENUMERATION_TYPE_P (type))

37550

+ size = maybe_constant_value (size);

37551

+

37552

if (!TREE_CONSTANT (size))

37553

size = osize;

37554

}

37555

@@ -11891,7 +11893,10 @@

37556

37557

if (decl

37558

&& (DECL_CLASS_TEMPLATE_P (decl)

37559

- || DECL_TEMPLATE_TEMPLATE_PARM_P (decl)))

37560

+ /* If scope is ts_current we're defining a class, so ignore a

37561

+ template template parameter. */

37562

+ || (scope != ts_current

37563

+ && DECL_TEMPLATE_TEMPLATE_PARM_P (decl))))

37564

decl = DECL_TEMPLATE_RESULT (decl);

37565

37566

if (decl && TREE_CODE (decl) == TYPE_DECL)

37567

Index: gcc/cp/except.c

37568

===================================================================

37569

--- a/src/gcc/cp/except.c (.../tags/gcc_4_8_2_release)

37570

+++ b/src/gcc/cp/except.c (.../branches/gcc-4_8-branch)

37571

@@ -380,6 +380,9 @@

37572

{

37573

tree type = body ? TREE_TYPE (body) : void_type_node;

37574

37575

+ if (!flag_exceptions)

37576

+ return body;

37577

+

37578

if (cond && !value_dependent_expression_p (cond))

37579

{

37580

cond = cxx_constant_value (cond);

37581

Index: gcc/cp/ChangeLog

37582

===================================================================

37583

--- a/src/gcc/cp/ChangeLog (.../tags/gcc_4_8_2_release)

37584

+++ b/src/gcc/cp/ChangeLog (.../branches/gcc-4_8-branch)

37585

@@ -1,3 +1,251 @@

37586

+2014-04-28 Daniel Gutson <daniel.gutson@tallertechnologies.com>

37587

+

37588

+ * typeck.c (build_reinterpret_cast_1): Pass proper argument to

37589

+ warn() in pedantic.

37590

+

37591

+2014-02-28 Jason Merrill <jason@redhat.com>

37592

+

37593

+ PR c++/58845

37594

+ * typeck.c (cp_build_binary_op): Sorry on vector&&vector.

37595

+

37596

+2014-02-26 Jason Merrill <jason@redhat.com>

37597

+

37598

+ PR c++/60182

37599

+ * pt.c (unify): Ignore alias templates when deducing a template

37600

+ template parameter.

37601

+

37602

+2014-02-24 Jason Merrill <jason@redhat.com>

37603

+

37604

+ PR c++/60146

37605

+ * pt.c (tsubst_omp_for_iterator): Don't let substitution of the

37606

+ DECL_EXPR initialize a non-class iterator.

37607

+

37608

+2014-02-24 Fabien Chêne <fabien@gcc.gnu.org>

37609

+ PR c++/37140

37610

+ * parser.c (cp_parser_nonclass_name): Call strip_using_decl and

37611

+ move the code handling dependent USING_DECLs...

37612

+ * name-lookup.c (strip_using_decl): ...Here.

37613

+

37614

+2014-02-21 Jason Merrill <jason@redhat.com>

37615

+

37616

+ PR c++/60108

37617

+ * semantics.c (expand_or_defer_fn_1): Check DECL_DEFAULTED_FN.

37618

+

37619

+ PR c++/60187

37620

+ * parser.c (cp_parser_enum_specifier): Call

37621

+ check_for_bare_parameter_packs.

37622

+

37623

+ PR c++/60216

37624

+ * pt.c (register_specialization): Copy DECL_DELETED_FN to clones.

37625

+

37626

+ PR c++/60219

37627

+ * pt.c (coerce_template_parms): Bail if argument packing fails.

37628

+

37629

+ PR c++/60248

37630

+ * mangle.c (mangle_decl): Don't make an alias for a TYPE_DECL.

37631

+

37632

+2014-02-20 Jason Merrill <jason@redhat.com>

37633

+

37634

+ PR c++/60274

37635

+ Revert:

37636

+ PR c++/58606

37637

+ * pt.c (template_parm_to_arg): Call convert_from_reference.

37638

+ (tsubst_template_arg): Don't strip reference refs.

37639

+

37640

+2014-02-20 Kai Tietz <ktietz@redhat.com>

37641

+

37642

+ PR c++/58873

37643

+ * parser.c (cp_parser_functional_cast): Treat NULL_TREE

37644

+ valued type argument as error_mark_node.

37645

+

37646

+ PR c++/58835

37647

+ * semantics.c (finish_fname): Handle error_mark_node.

37648

+

37649

+2014-02-19 Jason Merrill <jason@redhat.com>

37650

+

37651

+ PR c++/60046

37652

+ * pt.c (maybe_instantiate_noexcept): Don't instantiate exception

37653

+ spec from template context.

37654

+

37655

+2014-01-31 Jason Merrill <jason@redhat.com>

37656

+

37657

+ PR c++/58672

37658

+ * decl2.c (handle_tls_init): Handle null init fn.

37659

+

37660

+ PR c++/55800

37661

+ * decl2.c (get_tls_init_fn): Copy DECL_EXTERNAL from the variable.

37662

+

37663

+ PR c++/59646

37664

+ * call.c (convert_like_real) [ck_aggr]: Set TARGET_EXPR_LIST_INIT_P.

37665

+ [ck_list]: Check for error_mark_node.

37666

+

37667

+ PR c++/57043

37668

+ * pt.c (fn_type_unification): Don't do DEDUCE_EXACT check

37669

+ during partial ordering.

37670

+

37671

+2014-01-30 Jason Merrill <jason@redhat.com>

37672

+

37673

+ PR c++/57899

37674

+ * pt.c (instantiate_template_1): Save/restore local_specializations.

37675

+

37676

+2014-01-29 Jason Merrill <jason@redhat.com>

37677

+

37678

+ PR c++/59989

37679

+ * pt.c (expand_template_argument_pack): Correct

37680

+ non_default_args_count calculation.

37681

+

37682

+ PR c++/58466

37683

+ * pt.c (unify_pack_expansion): Call expand_template_argument_pack.

37684

+

37685

+2014-01-28 Jason Merrill <jason@redhat.com>

37686

+

37687

+ PR c++/58632

37688

+ * decl.c (lookup_and_check_tag): Ignore template parameters if

37689

+ scope == ts_current.

37690

+ * pt.c (check_template_shadow): Don't complain about the injected

37691

+ class name.

37692

+

37693

+2014-01-27 Jason Merrill <jason@redhat.com>

37694

+

37695

+ PR c++/54652

37696

+ * decl.c (duplicate_decls): Always use oldtype for TYPE_DECL.

37697

+

37698

+ PR c++/58504

37699

+ * pt.c (tsubst_copy_and_build) [TRAIT_EXPR]: Use tsubst for

37700

+ types.

37701

+

37702

+ PR c++/58606

37703

+ * pt.c (template_parm_to_arg): Call convert_from_reference.

37704

+ (tsubst_template_arg): Don't strip reference refs.

37705

+

37706

+ PR c++/58639

37707

+ * call.c (build_aggr_conv): Reject value-initialization of reference.

37708

+

37709

+ PR c++/58812

37710

+ * call.c (convert_like_real): Give helpful error about excess braces

37711

+ for reference binding, too.

37712

+

37713

+ PR c++/58814

37714

+ * typeck.c (cp_build_modify_expr): Make the RHS an rvalue before

37715

+ stabilizing.

37716

+

37717

+ PR c++/58837

37718

+ * typeck.c (cp_truthvalue_conversion): Use explicit comparison for

37719

+ FUNCTION_DECL.

37720

+

37721

+ PR c++/59097

37722

+ * decl.c (compute_array_index_type): Don't call

37723

+ maybe_constant_value for a non-integral expression.

37724

+

37725

+ PR c++/58965

37726

+ * mangle.c (write_guarded_var_name): Handle null DECL_NAME.

37727

+

37728

+2014-01-24 Paolo Carlini <paolo.carlini@oracle.com>

37729

+

37730

+ PR c++/57524

37731

+ * name-lookup.c (push_using_directive): Use timevar_cond_start.

37732

+

37733

+2014-01-23 Jakub Jelinek <jakub@redhat.com>

37734

+

37735

+ PR middle-end/58809

37736

+ * semantics.c (finish_omp_clauses): Reject MIN_EXPR, MAX_EXPR,

37737

+ BIT_AND_EXPR, BIT_IOR_EXPR and BIT_XOR_EXPR on COMPLEX_TYPEs.

37738

+

37739

+2014-01-20 Marek Polacek <polacek@redhat.com>

37740

+

37741

+ Backported from mainline

37742

+ 2014-01-17 Marek Polacek <polacek@redhat.com>

37743

+

37744

+ PR c++/59838

37745

+ * cvt.c (ocp_convert): Don't segfault on non-existing

37746

+ ENUM_UNDERLYING_TYPE.

37747

+

37748

+2014-01-10 Paolo Carlini <paolo.carlini@oracle.com>

37749

+

37750

+ PR c++/56060

37751

+ PR c++/59730

37752

+ * pt.c (type_dependent_expression_p): Handle EXPR_PACK_EXPANSION.

37753

+

37754

+2013-12-12 Jason Merrill <jason@redhat.com>

37755

+

37756

+ PR c++/58954

37757

+ * pt.c (resolve_overloaded_unification): Discard access checks.

37758

+

37759

+2013-12-05 Jason Merrill <jason@redhat.com>

37760

+

37761

+ PR c++/59044

37762

+ PR c++/59052

37763

+ * pt.c (most_specialized_class): Use the partially instantiated

37764

+ template for deduction. Drop the TMPL parameter.

37765

+

37766

+2013-12-04 Jakub Jelinek <jakub@redhat.com>

37767

+

37768

+ PR c++/59268

37769

+ * pt.c (tsubst_copy_and_build): Handle POINTER_PLUS_EXPR.

37770

+

37771

+2013-11-27 Tom de Vries <tom@codesourcery.com>

37772

+ Marc Glisse <marc.glisse@inria.fr>

37773

+

37774

+ PR c++/59032

37775

+ * typeck.c (cp_build_unary_op): Allow vector increment and decrement.

37776

+

37777

+2013-11-27 Tom de Vries <tom@codesourcery.com>

37778

+ Marc Glisse <marc.glisse@inria.fr>

37779

+

37780

+ PR middle-end/59037

37781

+ * semantics.c (cxx_fold_indirect_ref): Don't create out-of-bounds

37782

+ BIT_FIELD_REF.

37783

+

37784

+2013-11-28 Jakub Jelinek <jakub@redhat.com>

37785

+

37786

+ PR c++/59297

37787

+ * semantics.c (finish_omp_atomic): Call finish_expr_stmt

37788

+ rather than add_stmt.

37789

+

37790

+2013-11-23 Easwaran Raman <eraman@google.com>

37791

+

37792

+ PR c++/59031

37793

+ * call.c (build_new_method_call_1): Comnpare function context

37794

+ with BASELINK_BINFO type rather than instance type before

37795

+ marking the call with LOOKUP_NONVIRTUAL.

37796

+

37797

+2013-10-31 Jason Merrill <jason@redhat.com>

37798

+

37799

+ PR c++/58162

37800

+ * parser.c (cp_parser_late_parse_one_default_arg): Set

37801

+ TARGET_EXPR_DIRECT_INIT_P.

37802

+

37803

+2013-11-11 Paolo Carlini <paolo.carlini@oracle.com>

37804

+

37805

+ * cvt.c (cp_convert_to_pointer): Call build_ptrmemfunc before

37806

+ maybe_warn_zero_as_null_pointer_constant to avoid duplicate

37807

+ -Wzero-as-null-pointer-constant diagnostics.

37808

+

37809

+ * typeck.c (build_ptrmemfunc): Use cp_build_c_cast.

37810

+

37811

+2013-10-25 Tom de Vries <tom@codesourcery.com>

37812

+

37813

+ PR c++/58282

37814

+ * except.c (build_must_not_throw_expr): Handle

37815

+ flag_exceptions.

37816

+

37817

+2013-10-17 Paolo Carlini <paolo.carlini@oracle.com>

37818

+

37819

+ PR c++/58596

37820

+ * semantics.c (lambda_expr_this_capture): Handle NSDMIs in the

37821

+ cp_unevaluated_operand case.

37822

+

37823

+2013-10-16 Paolo Carlini <paolo.carlini@oracle.com>

37824

+

37825

+ PR c++/58633

37826

+ * parser.c (cp_parser_pseudo_destructor_name): Revert r174385 changes.

37827

+

37828

+2013-10-16 Jason Merrill <jason@redhat.com>

37829

+

37830

+ PR c++/57850

37831

+ * decl2.c (dump_tu): Split out from...

37832

+ (cp_write_global_declarations): ...here. Call it in PCH mode.

37833

+

37834

2013-10-16 Release Manager

37835

37836

* GCC 4.8.2 released.

37837

Index: gcc/cp/pt.c

37838

===================================================================

37839

--- a/src/gcc/cp/pt.c (.../tags/gcc_4_8_2_release)

37840

+++ b/src/gcc/cp/pt.c (.../branches/gcc-4_8-branch)

37841

@@ -170,7 +170,7 @@

37842

static tree tsubst_template_args (tree, tree, tsubst_flags_t, tree);

37843

static tree tsubst_template_parms (tree, tree, tsubst_flags_t);

37844

static void regenerate_decl_from_template (tree, tree);

37845

-static tree most_specialized_class (tree, tree, tsubst_flags_t);

37846

+static tree most_specialized_class (tree, tsubst_flags_t);

37847

static tree tsubst_aggr_type (tree, tree, tsubst_flags_t, tree, int);

37848

static tree tsubst_arg_types (tree, tree, tree, tsubst_flags_t, tree);

37849

static tree tsubst_function_type (tree, tree, tsubst_flags_t, tree);

37850

@@ -1419,6 +1419,8 @@

37851

= DECL_DECLARED_INLINE_P (fn);

37852

DECL_SOURCE_LOCATION (clone)

37853

= DECL_SOURCE_LOCATION (fn);

37854

+ DECL_DELETED_FN (clone)

37855

+ = DECL_DELETED_FN (fn);

37856

}

37857

check_specialization_namespace (tmpl);

37858

37859

@@ -3436,7 +3438,7 @@

37860

for (i = 0; i < num_packed; ++i, ++out_arg)

37861

TREE_VEC_ELT (result_args, out_arg) = TREE_VEC_ELT(packed, i);

37862

if (non_default_args_count > 0)

37863

- non_default_args_count += num_packed;

37864

+ non_default_args_count += num_packed - 1;

37865

}

37866

else

37867

{

37868

@@ -3491,6 +3493,11 @@

37869

|| TEMPLATE_PARMS_FOR_INLINE (current_template_parms))

37870

return true;

37871

37872

+ /* Don't complain about the injected class name, as we've already

37873

+ complained about the class itself. */

37874

+ if (DECL_SELF_REFERENCE_P (decl))

37875

+ return false;

37876

+

37877

error ("declaration of %q+#D", decl);

37878

error (" shadows template parm %q+#D", olddecl);

37879

return false;

37880

@@ -4261,7 +4268,7 @@

37881

if (COMPLETE_TYPE_P (inst_type)

37882

&& CLASSTYPE_IMPLICIT_INSTANTIATION (inst_type))

37883

{

37884

- tree spec = most_specialized_class (inst_type, maintmpl, tf_none);

37885

+ tree spec = most_specialized_class (inst_type, tf_none);

37886

if (spec && TREE_TYPE (spec) == type)

37887

permerror (input_location,

37888

"partial specialization of %qT after instantiation "

37889

@@ -6672,6 +6679,8 @@

37890

/* Store this argument. */

37891

if (arg == error_mark_node)

37892

lost++;

37893

+ if (lost)

37894

+ break;

37895

TREE_VEC_ELT (new_inner_args, parm_idx) = arg;

37896

37897

/* We are done with all of the arguments. */

37898

@@ -8572,7 +8581,7 @@

37899

37900

/* Determine what specialization of the original template to

37901

instantiate. */

37902

- t = most_specialized_class (type, templ, tf_warning_or_error);

37903

+ t = most_specialized_class (type, tf_warning_or_error);

37904

if (t == error_mark_node)

37905

{

37906

TYPE_BEING_DEFINED (type) = 1;

37907

@@ -12694,27 +12703,43 @@

37908

tsubst_expr ((NODE), args, complain, in_decl, \

37909

integral_constant_expression_p)

37910

tree decl, init, cond, incr;

37911

- bool init_decl;

37912

37913

init = TREE_VEC_ELT (OMP_FOR_INIT (t), i);

37914

gcc_assert (TREE_CODE (init) == MODIFY_EXPR);

37915

decl = TREE_OPERAND (init, 0);

37916

init = TREE_OPERAND (init, 1);

37917

- /* Do this before substituting into decl to handle 'auto'. */

37918

- init_decl = (init && TREE_CODE (init) == DECL_EXPR);

37919

- init = RECUR (init);

37920

- decl = RECUR (decl);

37921

- if (init_decl)

37922

+ tree decl_expr = NULL_TREE;

37923

+ if (init && TREE_CODE (init) == DECL_EXPR)

37924

{

37925

- gcc_assert (!processing_template_decl);

37926

- init = DECL_INITIAL (decl);

37927

- DECL_INITIAL (decl) = NULL_TREE;

37928

+ /* We need to jump through some hoops to handle declarations in the

37929

+ for-init-statement, since we might need to handle auto deduction,

37930

+ but we need to keep control of initialization. */

37931

+ decl_expr = init;

37932

+ init = DECL_INITIAL (DECL_EXPR_DECL (init));

37933

+ decl = tsubst_decl (decl, args, complain);

37934

}

37935

+ else

37936

+ decl = RECUR (decl);

37937

+ init = RECUR (init);

37938

37939

+ tree auto_node = type_uses_auto (TREE_TYPE (decl));

37940

+ if (auto_node && init)

37941

+ TREE_TYPE (decl)

37942

+ = do_auto_deduction (TREE_TYPE (decl), init, auto_node);

37943

+

37944

gcc_assert (!type_dependent_expression_p (decl));

37945

37946

if (!CLASS_TYPE_P (TREE_TYPE (decl)))

37947

{

37948

+ if (decl_expr)

37949

+ {

37950

+ /* Declare the variable, but don't let that initialize it. */

37951

+ tree init_sav = DECL_INITIAL (DECL_EXPR_DECL (decl_expr));

37952

+ DECL_INITIAL (DECL_EXPR_DECL (decl_expr)) = NULL_TREE;

37953

+ RECUR (decl_expr);

37954

+ DECL_INITIAL (DECL_EXPR_DECL (decl_expr)) = init_sav;

37955

+ }

37956

+

37957

cond = RECUR (TREE_VEC_ELT (OMP_FOR_COND (t), i));

37958

incr = TREE_VEC_ELT (OMP_FOR_INCR (t), i);

37959

if (TREE_CODE (incr) == MODIFY_EXPR)

37960

@@ -12731,8 +12756,14 @@

37961

return;

37962

}

37963

37964

- if (init && !init_decl)

37965

+ if (decl_expr)

37966

{

37967

+ /* Declare and initialize the variable. */

37968

+ RECUR (decl_expr);

37969

+ init = NULL_TREE;

37970

+ }

37971

+ else if (init)

37972

+ {

37973

tree c;

37974

for (c = *clauses; c ; c = OMP_CLAUSE_CHAIN (c))

37975

{

37976

@@ -13710,6 +13741,10 @@

37977

RETURN (r);

37978

}

37979

37980

+ case POINTER_PLUS_EXPR:

37981

+ return fold_build_pointer_plus (RECUR (TREE_OPERAND (t, 0)),

37982

+ RECUR (TREE_OPERAND (t, 1)));

37983

+

37984

case SCOPE_REF:

37985

RETURN (tsubst_qualified_id (t, args, complain, in_decl, /*done=*/true,

37986

/*address_p=*/false));

37987

@@ -14471,12 +14506,12 @@

37988

37989

case TRAIT_EXPR:

37990

{

37991

- tree type1 = tsubst_copy (TRAIT_EXPR_TYPE1 (t), args,

37992

- complain, in_decl);

37993

+ tree type1 = tsubst (TRAIT_EXPR_TYPE1 (t), args,

37994

+ complain, in_decl);

37995

37996

tree type2 = TRAIT_EXPR_TYPE2 (t);

37997

if (type2)

37998

- type2 = tsubst_copy (type2, args, complain, in_decl);

37999

+ type2 = tsubst (type2, args, complain, in_decl);

38000

38001

RETURN (finish_trait_expr (TRAIT_EXPR_KIND (t), type1, type2));

38002

}

38003

@@ -14778,6 +14813,8 @@

38004

/* Instantiation of the function happens in the context of the function

38005

template, not the context of the overload resolution we're doing. */

38006

push_to_top_level ();

38007

+ struct pointer_map_t *saved_local_specializations = local_specializations;

38008

+ local_specializations = NULL;

38009

/* If there are dependent arguments, e.g. because we're doing partial

38010

ordering, make sure processing_template_decl stays set. */

38011

if (uses_template_parms (targ_ptr))

38012

@@ -14793,6 +14830,7 @@

38013

targ_ptr, complain, gen_tmpl);

38014

if (DECL_CLASS_SCOPE_P (gen_tmpl))

38015

pop_nested_class ();

38016

+ local_specializations = saved_local_specializations;

38017

pop_from_top_level ();

38018

38019

if (fndecl == error_mark_node)

38020

@@ -15192,8 +15230,11 @@

38021

38022

/* If we're looking for an exact match, check that what we got

38023

is indeed an exact match. It might not be if some template

38024

- parameters are used in non-deduced contexts. */

38025

- if (strict == DEDUCE_EXACT)

38026

+ parameters are used in non-deduced contexts. But don't check

38027

+ for an exact match if we have dependent template arguments;

38028

+ in that case we're doing partial ordering, and we already know

38029

+ that we have two candidates that will provide the actual type. */

38030

+ if (strict == DEDUCE_EXACT && !any_dependent_template_arguments_p (targs))

38031

{

38032

tree substed = TREE_TYPE (decl);

38033

unsigned int i;

38034

@@ -15749,7 +15790,7 @@

38035

if (subargs != error_mark_node

38036

&& !any_dependent_template_arguments_p (subargs))

38037

{

38038

- elem = tsubst (TREE_TYPE (fn), subargs, tf_none, NULL_TREE);

38039

+ elem = TREE_TYPE (instantiate_template (fn, subargs, tf_none));

38040

if (try_one_overload (tparms, targs, tempargs, parm,

38041

elem, strict, sub_strict, addr_p, explain_p)

38042

&& (!goodfn || !same_type_p (goodfn, elem)))

38043

@@ -16207,6 +16248,9 @@

38044

tree pattern = PACK_EXPANSION_PATTERN (parm);

38045

tree pack, packs = NULL_TREE;

38046

int i, start = TREE_VEC_LENGTH (packed_parms) - 1;

38047

+

38048

+ packed_args = expand_template_argument_pack (packed_args);

38049

+

38050

int len = TREE_VEC_LENGTH (packed_args);

38051

38052

/* Determine the parameter packs we will be deducing from the

38053

@@ -16574,9 +16618,11 @@

38054

if (TREE_CODE (arg) != BOUND_TEMPLATE_TEMPLATE_PARM

38055

&& !CLASSTYPE_SPECIALIZATION_OF_PRIMARY_TEMPLATE_P (arg))

38056

return unify_template_deduction_failure (explain_p, parm, arg);

38057

-

38058

{

38059

tree parmvec = TYPE_TI_ARGS (parm);

38060

+ /* An alias template name is never deduced. */

38061

+ if (TYPE_ALIAS_P (arg))

38062

+ arg = strip_typedefs (arg);

38063

tree argvec = INNERMOST_TEMPLATE_ARGS (TYPE_TI_ARGS (arg));

38064

tree full_argvec = add_to_template_args (targs, argvec);

38065

tree parm_parms

38066

@@ -17553,7 +17599,7 @@

38067

return -1;

38068

}

38069

38070

-/* Determine which of two partial specializations of MAIN_TMPL is more

38071

+/* Determine which of two partial specializations of TMPL is more

38072

specialized.

38073

38074

PAT1 is a TREE_LIST whose TREE_TYPE is the _TYPE node corresponding

38075

@@ -17569,7 +17615,7 @@

38076

two templates is more specialized. */

38077

38078

static int

38079

-more_specialized_class (tree main_tmpl, tree pat1, tree pat2)

38080

+more_specialized_class (tree tmpl, tree pat1, tree pat2)

38081

{

38082

tree targs;

38083

tree tmpl1, tmpl2;

38084

@@ -17584,7 +17630,7 @@

38085

types in the arguments, and we need our dependency check functions

38086

to behave correctly. */

38087

++processing_template_decl;

38088

- targs = get_class_bindings (main_tmpl, TREE_VALUE (pat1),

38089

+ targs = get_class_bindings (tmpl, TREE_VALUE (pat1),

38090

CLASSTYPE_TI_ARGS (tmpl1),

38091

CLASSTYPE_TI_ARGS (tmpl2));

38092

if (targs)

38093

@@ -17593,7 +17639,7 @@

38094

any_deductions = true;

38095

}

38096

38097

- targs = get_class_bindings (main_tmpl, TREE_VALUE (pat2),

38098

+ targs = get_class_bindings (tmpl, TREE_VALUE (pat2),

38099

CLASSTYPE_TI_ARGS (tmpl2),

38100

CLASSTYPE_TI_ARGS (tmpl1));

38101

if (targs)

38102

@@ -17673,7 +17719,7 @@

38103

}

38104

38105

/* Return the innermost template arguments that, when applied to a partial

38106

- specialization of MAIN_TMPL whose innermost template parameters are

38107

+ specialization of TMPL whose innermost template parameters are

38108

TPARMS, and whose specialization arguments are SPEC_ARGS, yield the

38109

ARGS.

38110

38111

@@ -17688,7 +17734,7 @@

38112

is bound to `double'. */

38113

38114

static tree

38115

-get_class_bindings (tree main_tmpl, tree tparms, tree spec_args, tree args)

38116

+get_class_bindings (tree tmpl, tree tparms, tree spec_args, tree args)

38117

{

38118

int i, ntparms = TREE_VEC_LENGTH (tparms);

38119

tree deduced_args;

38120

@@ -17728,8 +17774,8 @@

38121

`T' is `A' but unify () does not check whether `typename T::X'

38122

is `int'. */

38123

spec_args = tsubst (spec_args, deduced_args, tf_none, NULL_TREE);

38124

- spec_args = coerce_template_parms (DECL_INNERMOST_TEMPLATE_PARMS (main_tmpl),

38125

- spec_args, main_tmpl,

38126

+ spec_args = coerce_template_parms (DECL_INNERMOST_TEMPLATE_PARMS (tmpl),

38127

+ spec_args, tmpl,

38128

tf_none, false, false);

38129

if (spec_args == error_mark_node

38130

/* We only need to check the innermost arguments; the other

38131

@@ -17877,8 +17923,8 @@

38132

}

38133

38134

/* Return the most specialized of the class template partial

38135

- specializations of TMPL which can produce TYPE, a specialization of

38136

- TMPL. The value returned is actually a TREE_LIST; the TREE_TYPE is

38137

+ specializations which can produce TYPE, a specialization of some class

38138

+ template. The value returned is actually a TREE_LIST; the TREE_TYPE is

38139

a _TYPE node corresponding to the partial specialization, while the

38140

TREE_PURPOSE is the set of template arguments that must be

38141

substituted into the TREE_TYPE in order to generate TYPE.

38142

@@ -17885,11 +17931,11 @@

38143

38144

If the choice of partial specialization is ambiguous, a diagnostic

38145

is issued, and the error_mark_node is returned. If there are no

38146

- partial specializations of TMPL matching TYPE, then NULL_TREE is

38147

- returned. */

38148

+ partial specializations matching TYPE, then NULL_TREE is

38149

+ returned, indicating that the primary template should be used. */

38150

38151

static tree

38152

-most_specialized_class (tree type, tree tmpl, tsubst_flags_t complain)

38153

+most_specialized_class (tree type, tsubst_flags_t complain)

38154

{

38155

tree list = NULL_TREE;

38156

tree t;

38157

@@ -17896,11 +17942,11 @@

38158

tree champ;

38159

int fate;

38160

bool ambiguous_p;

38161

- tree args;

38162

tree outer_args = NULL_TREE;

38163

38164

- tmpl = most_general_template (tmpl);

38165

- args = CLASSTYPE_TI_ARGS (type);

38166

+ tree tmpl = CLASSTYPE_TI_TEMPLATE (type);

38167

+ tree main_tmpl = most_general_template (tmpl);

38168

+ tree args = CLASSTYPE_TI_ARGS (type);

38169

38170

/* For determining which partial specialization to use, only the

38171

innermost args are interesting. */

38172

@@ -17910,7 +17956,7 @@

38173

args = INNERMOST_TEMPLATE_ARGS (args);

38174

}

38175

38176

- for (t = DECL_TEMPLATE_SPECIALIZATIONS (tmpl); t; t = TREE_CHAIN (t))

38177

+ for (t = DECL_TEMPLATE_SPECIALIZATIONS (main_tmpl); t; t = TREE_CHAIN (t))

38178

{

38179

tree partial_spec_args;

38180

tree spec_args;

38181

@@ -17944,8 +17990,7 @@

38182

38183

partial_spec_args =

38184

coerce_template_parms (DECL_INNERMOST_TEMPLATE_PARMS (tmpl),

38185

- add_to_template_args (outer_args,

38186

- partial_spec_args),

38187

+ partial_spec_args,

38188

tmpl, tf_none,

38189

/*require_all_args=*/true,

38190

/*use_default_args=*/true);

38191

@@ -18553,6 +18598,10 @@

38192

{

38193

tree fntype, spec, noex, clone;

38194

38195

+ /* Don't instantiate a noexcept-specification from template context. */

38196

+ if (processing_template_decl)

38197

+ return;

38198

+

38199

if (DECL_CLONED_FUNCTION_P (fn))

38200

fn = DECL_CLONED_FUNCTION (fn);

38201

fntype = TREE_TYPE (fn);

38202

@@ -19955,6 +20004,10 @@

38203

if (TREE_CODE (expression) == SCOPE_REF)

38204

return false;

38205

38206

+ /* Always dependent, on the number of arguments if nothing else. */

38207

+ if (TREE_CODE (expression) == EXPR_PACK_EXPANSION)

38208

+ return true;

38209

+

38210

if (BASELINK_P (expression))

38211

expression = BASELINK_FUNCTIONS (expression);

38212

38213

Index: gcc/cp/semantics.c

38214

===================================================================

38215

--- a/src/gcc/cp/semantics.c (.../tags/gcc_4_8_2_release)

38216

+++ b/src/gcc/cp/semantics.c (.../branches/gcc-4_8-branch)

38217

@@ -2501,7 +2501,8 @@

38218

tree decl;

38219

38220

decl = fname_decl (input_location, C_RID_CODE (id), id);

38221

- if (processing_template_decl && current_function_decl)

38222

+ if (processing_template_decl && current_function_decl

38223

+ && decl != error_mark_node)

38224

decl = DECL_NAME (decl);

38225

return decl;

38226

}

38227

@@ -3853,7 +3854,7 @@

38228

linkage of all functions, and as that causes writes to

38229

the data mapped in from the PCH file, it's advantageous

38230

to mark the functions at this point. */

38231

- if (!DECL_IMPLICIT_INSTANTIATION (fn))

38232

+ if (!DECL_IMPLICIT_INSTANTIATION (fn) || DECL_DEFAULTED_FN (fn))

38233

{

38234

/* This function must have external linkage, as

38235

otherwise DECL_INTERFACE_KNOWN would have been

38236

@@ -4291,7 +4292,8 @@

38237

error ("%qE has invalid type for %<reduction%>", t);

38238

remove = true;

38239

}

38240

- else if (FLOAT_TYPE_P (TREE_TYPE (t)))

38241

+ else if (FLOAT_TYPE_P (TREE_TYPE (t))

38242

+ || TREE_CODE (TREE_TYPE (t)) == COMPLEX_TYPE)

38243

{

38244

enum tree_code r_code = OMP_CLAUSE_REDUCTION_CODE (c);

38245

switch (r_code)

38246

@@ -4299,10 +4301,26 @@

38247

case PLUS_EXPR:

38248

case MULT_EXPR:

38249

case MINUS_EXPR:

38250

+ break;

38251

case MIN_EXPR:

38252

case MAX_EXPR:

38253

+ if (TREE_CODE (TREE_TYPE (t)) == COMPLEX_TYPE)

38254

+ r_code = ERROR_MARK;

38255

break;

38256

+ case BIT_AND_EXPR:

38257

+ case BIT_XOR_EXPR:

38258

+ case BIT_IOR_EXPR:

38259

default:

38260

+ r_code = ERROR_MARK;

38261

+ break;

38262

+ case TRUTH_ANDIF_EXPR:

38263

+ case TRUTH_ORIF_EXPR:

38264

+ if (FLOAT_TYPE_P (TREE_TYPE (t)))

38265

+ r_code = ERROR_MARK;

38266

+ break;

38267

+ }

38268

+ if (r_code == ERROR_MARK)

38269

+ {

38270

error ("%qE has invalid type for %<reduction(%s)%>",

38271

t, operator_name_info[r_code].name);

38272

remove = true;

38273

@@ -5059,7 +5077,7 @@

38274

}

38275

stmt = build2 (OMP_ATOMIC, void_type_node, integer_zero_node, stmt);

38276

}

38277

- add_stmt (stmt);

38278

+ finish_expr_stmt (stmt);

38279

}

38280

38281

void

38282

@@ -7543,7 +7561,7 @@

38283

unsigned HOST_WIDE_INT indexi = offset * BITS_PER_UNIT;

38284

tree index = bitsize_int (indexi);

38285

38286

- if (offset/part_widthi <= TYPE_VECTOR_SUBPARTS (op00type))

38287

+ if (offset / part_widthi < TYPE_VECTOR_SUBPARTS (op00type))

38288

return fold_build3_loc (loc,

38289

BIT_FIELD_REF, type, op00,

38290

part_width, index);

38291

@@ -9481,7 +9499,14 @@

38292

/* In unevaluated context this isn't an odr-use, so just return the

38293

nearest 'this'. */

38294

if (cp_unevaluated_operand)

38295

- return lookup_name (this_identifier);

38296

+ {

38297

+ /* In an NSDMI the fake 'this' pointer that we're using for

38298

+ parsing is in scope_chain. */

38299

+ if (LAMBDA_EXPR_EXTRA_SCOPE (lambda)

38300

+ && TREE_CODE (LAMBDA_EXPR_EXTRA_SCOPE (lambda)) == FIELD_DECL)

38301

+ return scope_chain->x_current_class_ptr;

38302

+ return lookup_name (this_identifier);

38303

+ }

38304

38305

/* Try to default capture 'this' if we can. */

38306

if (!this_capture

38307

Index: gcc/cp/decl2.c

38308

===================================================================

38309

--- a/src/gcc/cp/decl2.c (.../tags/gcc_4_8_2_release)

38310

+++ b/src/gcc/cp/decl2.c (.../branches/gcc-4_8-branch)

38311

@@ -2884,7 +2884,7 @@

38312

TREE_PUBLIC (fn) = TREE_PUBLIC (var);

38313

DECL_ARTIFICIAL (fn) = true;

38314

DECL_COMDAT (fn) = DECL_COMDAT (var);

38315

- DECL_EXTERNAL (fn) = true;

38316

+ DECL_EXTERNAL (fn) = DECL_EXTERNAL (var);

38317

if (DECL_ONE_ONLY (var))

38318

make_decl_one_only (fn, cxx_comdat_group (fn));

38319

if (TREE_PUBLIC (var))

38320

@@ -3946,6 +3946,8 @@

38321

if (TREE_PUBLIC (var))

38322

{

38323

tree single_init_fn = get_tls_init_fn (var);

38324

+ if (single_init_fn == NULL_TREE)

38325

+ continue;

38326

cgraph_node *alias

38327

= cgraph_same_body_alias (cgraph_get_create_node (fn),

38328

single_init_fn, fn);

38329

@@ -3960,6 +3962,22 @@

38330

expand_or_defer_fn (finish_function (0));

38331

}

38332

38333

+/* The entire file is now complete. If requested, dump everything

38334

+ to a file. */

38335

+

38336

+static void

38337

+dump_tu (void)

38338

+{

38339

+ int flags;

38340

+ FILE *stream = dump_begin (TDI_tu, &flags);

38341

+

38342

+ if (stream)

38343

+ {

38344

+ dump_node (global_namespace, flags & ~TDF_SLIM, stream);

38345

+ dump_end (TDI_tu, stream);

38346

+ }

38347

+}

38348

+

38349

/* This routine is called at the end of compilation.

38350

Its job is to create all the code needed to initialize and

38351

destroy the global aggregates. We do the destruction

38352

@@ -3990,6 +4008,7 @@

38353

if (pch_file)

38354

{

38355

c_common_write_pch ();

38356

+ dump_tu ();

38357

return;

38358

}

38359

38360

@@ -4359,17 +4378,8 @@

38361

38362

/* The entire file is now complete. If requested, dump everything

38363

to a file. */

38364

- {

38365

- int flags;

38366

- FILE *stream = dump_begin (TDI_tu, &flags);

38367

+ dump_tu ();

38368

38369

- if (stream)

38370

- {

38371

- dump_node (global_namespace, flags & ~TDF_SLIM, stream);

38372

- dump_end (TDI_tu, stream);

38373

- }

38374

- }

38375

-

38376

if (flag_detailed_statistics)

38377

{

38378

dump_tree_statistics ();

38379

Index: gcc/cp/parser.c

38380

===================================================================

38381

--- a/src/gcc/cp/parser.c (.../tags/gcc_4_8_2_release)

38382

+++ b/src/gcc/cp/parser.c (.../branches/gcc-4_8-branch)

38383

@@ -6421,10 +6421,6 @@

38384

/* Look for the `~'. */

38385

cp_parser_require (parser, CPP_COMPL, RT_COMPL);

38386

38387

- /* Once we see the ~, this has to be a pseudo-destructor. */

38388

- if (!processing_template_decl && !cp_parser_error_occurred (parser))

38389

- cp_parser_commit_to_tentative_parse (parser);

38390

-

38391

/* Look for the type-name again. We are not responsible for

38392

checking that it matches the first type-name. */

38393

*type = cp_parser_nonclass_name (parser);

38394

@@ -14168,25 +14164,7 @@

38395

/* Look up the type-name. */

38396

type_decl = cp_parser_lookup_name_simple (parser, identifier, token->location);

38397

38398

- if (TREE_CODE (type_decl) == USING_DECL)

38399

- {

38400

- if (!DECL_DEPENDENT_P (type_decl))

38401

- type_decl = strip_using_decl (type_decl);

38402

- else if (USING_DECL_TYPENAME_P (type_decl))

38403

- {

38404

- /* We have found a type introduced by a using

38405

- declaration at class scope that refers to a dependent

38406

- type.

38407

-

38408

- using typename :: [opt] nested-name-specifier unqualified-id ;

38409

- */

38410

- type_decl = make_typename_type (TREE_TYPE (type_decl),

38411

- DECL_NAME (type_decl),

38412

- typename_type, tf_error);

38413

- if (type_decl != error_mark_node)

38414

- type_decl = TYPE_NAME (type_decl);

38415

- }

38416

- }

38417

+ type_decl = strip_using_decl (type_decl);

38418

38419

if (TREE_CODE (type_decl) != TYPE_DECL

38420

&& (objc_is_id (identifier) || objc_is_class_name (identifier)))

38421

@@ -14742,7 +14720,8 @@

38422

{

38423

underlying_type = grokdeclarator (NULL, &type_specifiers, TYPENAME,

38424

/*initialized=*/0, NULL);

38425

- if (underlying_type == error_mark_node)

38426

+ if (underlying_type == error_mark_node

38427

+ || check_for_bare_parameter_packs (underlying_type))

38428

underlying_type = NULL_TREE;

38429

}

38430

}

38431

@@ -22209,6 +22188,9 @@

38432

tree cast;

38433

bool nonconst_p;

38434

38435

+ if (!type)

38436

+ type = error_mark_node;

38437

+

38438

if (cp_lexer_next_token_is (parser->lexer, CPP_OPEN_BRACE))

38439

{

38440

maybe_warn_cpp0x (CPP0X_INITIALIZER_LISTS);

38441

@@ -22576,6 +22558,9 @@

38442

&& CONSTRUCTOR_IS_DIRECT_INIT (parsed_arg))

38443

flags = LOOKUP_NORMAL;

38444

parsed_arg = digest_init_flags (TREE_TYPE (decl), parsed_arg, flags);

38445

+ if (TREE_CODE (parsed_arg) == TARGET_EXPR)

38446

+ /* This represents the whole initialization. */

38447

+ TARGET_EXPR_DIRECT_INIT_P (parsed_arg) = true;

38448

}

38449

}

38450

38451

Index: gcc/cp/call.c

38452

===================================================================

38453

--- a/src/gcc/cp/call.c (.../tags/gcc_4_8_2_release)

38454

+++ b/src/gcc/cp/call.c (.../branches/gcc-4_8-branch)

38455

@@ -892,6 +892,9 @@

38456

38457

if (i < CONSTRUCTOR_NELTS (ctor))

38458

val = CONSTRUCTOR_ELT (ctor, i)->value;

38459

+ else if (TREE_CODE (ftype) == REFERENCE_TYPE)

38460

+ /* Value-initialization of reference is ill-formed. */

38461

+ return NULL;

38462

else

38463

{

38464

if (empty_ctor == NULL_TREE)

38465

@@ -5806,9 +5809,11 @@

38466

&& convs->kind != ck_ambig

38467

&& (convs->kind != ck_ref_bind

38468

|| convs->user_conv_p)

38469

- && convs->kind != ck_rvalue

38470

+ && (convs->kind != ck_rvalue

38471

+ || SCALAR_TYPE_P (totype))

38472

&& convs->kind != ck_base)

38473

{

38474

+ bool complained = false;

38475

conversion *t = convs;

38476

38477

/* Give a helpful error if this is bad because of excess braces. */

38478

@@ -5816,7 +5821,14 @@

38479

&& SCALAR_TYPE_P (totype)

38480

&& CONSTRUCTOR_NELTS (expr) > 0

38481

&& BRACE_ENCLOSED_INITIALIZER_P (CONSTRUCTOR_ELT (expr, 0)->value))

38482

- permerror (loc, "too many braces around initializer for %qT", totype);

38483

+ {

38484

+ complained = true;

38485

+ permerror (loc, "too many braces around initializer "

38486

+ "for %qT", totype);

38487

+ while (BRACE_ENCLOSED_INITIALIZER_P (expr)

38488

+ && CONSTRUCTOR_NELTS (expr) == 1)

38489

+ expr = CONSTRUCTOR_ELT (expr, 0)->value;

38490

+ }

38491

38492

for (; t ; t = next_conversion (t))

38493

{

38494

@@ -5853,8 +5865,9 @@

38495

break;

38496

}

38497

38498

- permerror (loc, "invalid conversion from %qT to %qT",

38499

- TREE_TYPE (expr), totype);

38500

+ if (!complained)

38501

+ permerror (loc, "invalid conversion from %qT to %qT",

38502

+ TREE_TYPE (expr), totype);

38503

if (fn)

38504

permerror (DECL_SOURCE_LOCATION (fn),

38505

" initializing argument %P of %qD", argnum, fn);

38506

@@ -5999,6 +6012,8 @@

38507

to avoid the error about taking the address of a temporary. */

38508

array = cp_build_addr_expr (array, complain);

38509

array = cp_convert (build_pointer_type (elttype), array, complain);

38510

+ if (array == error_mark_node)

38511

+ return error_mark_node;

38512

38513

/* Build up the initializer_list object. */

38514

totype = complete_type (totype);

38515

@@ -6023,8 +6038,11 @@

38516

return fold_if_not_in_template (expr);

38517

}

38518

expr = reshape_init (totype, expr, complain);

38519

- return get_target_expr_sfinae (digest_init (totype, expr, complain),

38520

+ expr = get_target_expr_sfinae (digest_init (totype, expr, complain),

38521

complain);

38522

+ if (expr != error_mark_node)

38523

+ TARGET_EXPR_LIST_INIT_P (expr) = true;

38524

+ return expr;

38525

38526

default:

38527

break;

38528

@@ -7414,7 +7432,7 @@

38529

struct z_candidate *candidates = 0, *cand;

38530

tree explicit_targs = NULL_TREE;

38531

tree basetype = NULL_TREE;

38532

- tree access_binfo;

38533

+ tree access_binfo, binfo;

38534

tree optype;

38535

tree first_mem_arg = NULL_TREE;

38536

tree instance_ptr;

38537

@@ -7454,6 +7472,7 @@

38538

if (!conversion_path)

38539

conversion_path = BASELINK_BINFO (fns);

38540

access_binfo = BASELINK_ACCESS_BINFO (fns);

38541

+ binfo = BASELINK_BINFO (fns);

38542

optype = BASELINK_OPTYPE (fns);

38543

fns = BASELINK_FUNCTIONS (fns);

38544

if (TREE_CODE (fns) == TEMPLATE_ID_EXPR)

38545

@@ -7697,13 +7716,13 @@

38546

{

38547

/* Optimize away vtable lookup if we know that this

38548

function can't be overridden. We need to check if

38549

- the context and the instance type are the same,

38550

+ the context and the type where we found fn are the same,

38551

actually FN might be defined in a different class

38552

type because of a using-declaration. In this case, we

38553

do not want to perform a non-virtual call. */

38554

if (DECL_VINDEX (fn) && ! (flags & LOOKUP_NONVIRTUAL)

38555

&& same_type_ignoring_top_level_qualifiers_p

38556

- (DECL_CONTEXT (fn), TREE_TYPE (instance))

38557

+ (DECL_CONTEXT (fn), BINFO_TYPE (binfo))

38558

&& resolves_to_fixed_type_p (instance, 0))

38559

flags |= LOOKUP_NONVIRTUAL;

38560

if (explicit_targs)

38561

Index: gcc/cp/cvt.c

38562

===================================================================

38563

--- a/src/gcc/cp/cvt.c (.../tags/gcc_4_8_2_release)

38564

+++ b/src/gcc/cp/cvt.c (.../branches/gcc-4_8-branch)

38565

@@ -203,13 +203,13 @@

38566

38567

if (null_ptr_cst_p (expr))

38568

{

38569

- if (complain & tf_warning)

38570

- maybe_warn_zero_as_null_pointer_constant (expr, loc);

38571

-

38572

if (TYPE_PTRMEMFUNC_P (type))

38573

return build_ptrmemfunc (TYPE_PTRMEMFUNC_FN_TYPE (type), expr, 0,

38574

/*c_cast_p=*/false, complain);

38575

38576

+ if (complain & tf_warning)

38577

+ maybe_warn_zero_as_null_pointer_constant (expr, loc);

38578

+

38579

/* A NULL pointer-to-data-member is represented by -1, not by

38580

zero. */

38581

tree val = (TYPE_PTRDATAMEM_P (type)

38582

@@ -743,6 +743,7 @@

38583

unspecified. */

38584

if ((complain & tf_warning)

38585

&& TREE_CODE (e) == INTEGER_CST

38586

+ && ENUM_UNDERLYING_TYPE (type)

38587

&& !int_fits_type_p (e, ENUM_UNDERLYING_TYPE (type)))

38588

warning_at (loc, OPT_Wconversion,

38589

"the result of the conversion is unspecified because "

38590

Index: gcc/cp/mangle.c

38591

===================================================================

38592

--- a/src/gcc/cp/mangle.c (.../tags/gcc_4_8_2_release)

38593

+++ b/src/gcc/cp/mangle.c (.../branches/gcc-4_8-branch)

38594

@@ -3478,6 +3478,7 @@

38595

38596

if (G.need_abi_warning

38597

/* Don't do this for a fake symbol we aren't going to emit anyway. */

38598

+ && TREE_CODE (decl) != TYPE_DECL

38599

&& !DECL_MAYBE_IN_CHARGE_CONSTRUCTOR_P (decl)

38600

&& !DECL_MAYBE_IN_CHARGE_DESTRUCTOR_P (decl))

38601

{

38602

@@ -3773,7 +3774,8 @@

38603

static void

38604

write_guarded_var_name (const tree variable)

38605

{

38606

- if (strncmp (IDENTIFIER_POINTER (DECL_NAME (variable)), "_ZGR", 4) == 0)

38607

+ if (DECL_NAME (variable)

38608

+ && strncmp (IDENTIFIER_POINTER (DECL_NAME (variable)), "_ZGR", 4) == 0)

38609

/* The name of a guard variable for a reference temporary should refer

38610

to the reference, not the temporary. */

38611

write_string (IDENTIFIER_POINTER (DECL_NAME (variable)) + 4);

38612

Index: gcc/cp/cp-tree.h

38613

===================================================================

38614

--- a/src/gcc/cp/cp-tree.h (.../tags/gcc_4_8_2_release)

38615

+++ b/src/gcc/cp/cp-tree.h (.../branches/gcc-4_8-branch)

38616

@@ -344,7 +344,8 @@

38617

/* Returns true iff NODE is a BASELINK. */

38618

#define BASELINK_P(NODE) \

38619

(TREE_CODE (NODE) == BASELINK)

38620

-/* The BINFO indicating the base from which the BASELINK_FUNCTIONS came. */

38621

+/* The BINFO indicating the base in which lookup found the

38622

+ BASELINK_FUNCTIONS. */

38623

#define BASELINK_BINFO(NODE) \

38624

(((struct tree_baselink*) BASELINK_CHECK (NODE))->binfo)

38625

/* The functions referred to by the BASELINK; either a FUNCTION_DECL,

38626

Index: gcc/cp/name-lookup.c

38627

===================================================================

38628

--- a/src/gcc/cp/name-lookup.c (.../tags/gcc_4_8_2_release)

38629

+++ b/src/gcc/cp/name-lookup.c (.../branches/gcc-4_8-branch)

38630

@@ -394,7 +394,8 @@

38631

}

38632

}

38633

38634

-/* Strip non dependent using declarations. */

38635

+/* Strip non dependent using declarations. If DECL is dependent,

38636

+ surreptitiously create a typename_type and return it. */

38637

38638

tree

38639

strip_using_decl (tree decl)

38640

@@ -404,6 +405,23 @@

38641

38642

while (TREE_CODE (decl) == USING_DECL && !DECL_DEPENDENT_P (decl))

38643

decl = USING_DECL_DECLS (decl);

38644

+

38645

+ if (TREE_CODE (decl) == USING_DECL && DECL_DEPENDENT_P (decl)

38646

+ && USING_DECL_TYPENAME_P (decl))

38647

+ {

38648

+ /* We have found a type introduced by a using

38649

+ declaration at class scope that refers to a dependent

38650

+ type.

38651

+

38652

+ using typename :: [opt] nested-name-specifier unqualified-id ;

38653

+ */

38654

+ decl = make_typename_type (TREE_TYPE (decl),

38655

+ DECL_NAME (decl),

38656

+ typename_type, tf_error);

38657

+ if (decl != error_mark_node)

38658

+ decl = TYPE_NAME (decl);

38659

+ }

38660

+

38661

return decl;

38662

}

38663

38664

@@ -5605,9 +5623,9 @@

38665

push_using_directive (tree used)

38666

{

38667

tree ret;

38668

- timevar_start (TV_NAME_LOOKUP);

38669

+ bool subtime = timevar_cond_start (TV_NAME_LOOKUP);

38670

ret = push_using_directive_1 (used);

38671

- timevar_stop (TV_NAME_LOOKUP);

38672

+ timevar_cond_stop (TV_NAME_LOOKUP, subtime);

38673

return ret;

38674

}

38675

38676

Index: gcc/builtins.def

38677

===================================================================

38678

--- a/src/gcc/builtins.def (.../tags/gcc_4_8_2_release)

38679

+++ b/src/gcc/builtins.def (.../branches/gcc-4_8-branch)

38680

@@ -252,6 +252,9 @@

38681

DEF_LIB_BUILTIN (BUILT_IN_FABS, "fabs", BT_FN_DOUBLE_DOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST)

38682

DEF_C99_C90RES_BUILTIN (BUILT_IN_FABSF, "fabsf", BT_FN_FLOAT_FLOAT, ATTR_CONST_NOTHROW_LEAF_LIST)

38683

DEF_C99_C90RES_BUILTIN (BUILT_IN_FABSL, "fabsl", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST)

38684

+DEF_GCC_BUILTIN (BUILT_IN_FABSD32, "fabsd32", BT_FN_DFLOAT32_DFLOAT32, ATTR_CONST_NOTHROW_LEAF_LIST)

38685

+DEF_GCC_BUILTIN (BUILT_IN_FABSD64, "fabsd64", BT_FN_DFLOAT64_DFLOAT64, ATTR_CONST_NOTHROW_LEAF_LIST)

38686

+DEF_GCC_BUILTIN (BUILT_IN_FABSD128, "fabsd128", BT_FN_DFLOAT128_DFLOAT128, ATTR_CONST_NOTHROW_LEAF_LIST)

38687

DEF_C99_BUILTIN (BUILT_IN_FDIM, "fdim", BT_FN_DOUBLE_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO)

38688

DEF_C99_BUILTIN (BUILT_IN_FDIMF, "fdimf", BT_FN_FLOAT_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO)

38689

DEF_C99_BUILTIN (BUILT_IN_FDIML, "fdiml", BT_FN_LONGDOUBLE_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO)

38690

Index: gcc/tree-ssa-loop-ivopts.c

38691

===================================================================

38692

--- a/src/gcc/tree-ssa-loop-ivopts.c (.../tags/gcc_4_8_2_release)

38693

+++ b/src/gcc/tree-ssa-loop-ivopts.c (.../branches/gcc-4_8-branch)

38694

@@ -4236,8 +4236,10 @@

38695

tree steptype = type;

38696

if (POINTER_TYPE_P (type))

38697

steptype = sizetype;

38698

+ steptype = unsigned_type_for (type);

38699

38700

- tree_to_aff_combination (iv->step, steptype, &step);

38701

+ tree_to_aff_combination (iv->step, TREE_TYPE (iv->step), &step);

38702

+ aff_combination_convert (&step, steptype);

38703

tree_to_aff_combination (niter, TREE_TYPE (niter), &nit);

38704

aff_combination_convert (&nit, steptype);

38705

aff_combination_mult (&nit, &step, &delta);

38706

@@ -4245,6 +4247,8 @@

38707

aff_combination_add (&delta, &step);

38708

38709

tree_to_aff_combination (iv->base, type, val);

38710

+ if (!POINTER_TYPE_P (type))

38711

+ aff_combination_convert (val, steptype);

38712

aff_combination_add (val, &delta);

38713

}

38714

38715

@@ -4623,7 +4627,8 @@

38716

38717

cand_value_at (loop, cand, use->stmt, desc->niter, &bnd);

38718

38719

- *bound = aff_combination_to_tree (&bnd);

38720

+ *bound = fold_convert (TREE_TYPE (cand->iv->base),

38721

+ aff_combination_to_tree (&bnd));

38722

*comp = iv_elimination_compare (data, use);

38723

38724

/* It is unlikely that computing the number of iterations using division

38725

Index: gcc/mode-switching.c

38726

===================================================================

38727

--- a/src/gcc/mode-switching.c (.../tags/gcc_4_8_2_release)

38728

+++ b/src/gcc/mode-switching.c (.../branches/gcc-4_8-branch)

38729

@@ -568,12 +568,15 @@

38730

38731

info[bb->index].computing = last_mode;

38732

/* Check for blocks without ANY mode requirements.

38733

- N.B. because of MODE_AFTER, last_mode might still be different

38734

- from no_mode. */

38735

+ N.B. because of MODE_AFTER, last_mode might still

38736

+ be different from no_mode, in which case we need to

38737

+ mark the block as nontransparent. */

38738

if (!any_set_required)

38739

{

38740

ptr = new_seginfo (no_mode, BB_END (bb), bb->index, live_now);

38741

add_seginfo (info + bb->index, ptr);

38742

+ if (last_mode != no_mode)

38743

+ bitmap_clear_bit (transp[bb->index], j);

38744

}

38745

}

38746

#if defined (MODE_ENTRY) && defined (MODE_EXIT)

38747

Index: gcc/ipa-pure-const.c

38748

===================================================================

38749

--- a/src/gcc/ipa-pure-const.c (.../tags/gcc_4_8_2_release)

38750

+++ b/src/gcc/ipa-pure-const.c (.../branches/gcc-4_8-branch)

38751

@@ -588,7 +588,7 @@

38752

/* Wrapper around check_decl for loads in local more. */

38753

38754

static bool

38755

-check_load (gimple stmt ATTRIBUTE_UNUSED, tree op, void *data)

38756

+check_load (gimple, tree op, tree, void *data)

38757

{

38758

if (DECL_P (op))

38759

check_decl ((funct_state)data, op, false, false);

38760

@@ -600,7 +600,7 @@

38761

/* Wrapper around check_decl for stores in local more. */

38762

38763

static bool

38764

-check_store (gimple stmt ATTRIBUTE_UNUSED, tree op, void *data)

38765

+check_store (gimple, tree op, tree, void *data)

38766

{

38767

if (DECL_P (op))

38768

check_decl ((funct_state)data, op, true, false);

38769

@@ -612,7 +612,7 @@

38770

/* Wrapper around check_decl for loads in ipa mode. */

38771

38772

static bool

38773

-check_ipa_load (gimple stmt ATTRIBUTE_UNUSED, tree op, void *data)

38774

+check_ipa_load (gimple, tree op, tree, void *data)

38775

{

38776

if (DECL_P (op))

38777

check_decl ((funct_state)data, op, false, true);

38778

@@ -624,7 +624,7 @@

38779

/* Wrapper around check_decl for stores in ipa mode. */

38780

38781

static bool

38782

-check_ipa_store (gimple stmt ATTRIBUTE_UNUSED, tree op, void *data)

38783

+check_ipa_store (gimple, tree op, tree, void *data)

38784

{

38785

if (DECL_P (op))

38786

check_decl ((funct_state)data, op, true, true);

38787

Index: gcc/cse.c

38788

===================================================================

38789

--- a/src/gcc/cse.c (.../tags/gcc_4_8_2_release)

38790

+++ b/src/gcc/cse.c (.../branches/gcc-4_8-branch)

38791

@@ -1824,7 +1824,7 @@

38792

}

38793

}

38794

38795

-/* Function called for each rtx to check whether true dependence exist. */

38796

+/* Function called for each rtx to check whether an anti dependence exist. */

38797

struct check_dependence_data

38798

{

38799

enum machine_mode mode;

38800

@@ -1837,7 +1837,7 @@

38801

{

38802

struct check_dependence_data *d = (struct check_dependence_data *) data;

38803

if (*x && MEM_P (*x))

38804

- return canon_true_dependence (d->exp, d->mode, d->addr, *x, NULL_RTX);

38805

+ return canon_anti_dependence (*x, true, d->exp, d->mode, d->addr);

38806

else

38807

return 0;

38808

}

38809

@@ -6082,6 +6082,18 @@

38810

return x;

38811

}

38812

38813

+ case UNSIGNED_FLOAT:

38814

+ {

38815

+ rtx new_rtx = cse_process_notes (XEXP (x, 0), object, changed);

38816

+ /* We don't substitute negative VOIDmode constants into these rtx,

38817

+ since they would impede folding. */

38818

+ if (GET_MODE (new_rtx) != VOIDmode

38819

+ || (CONST_INT_P (new_rtx) && INTVAL (new_rtx) >= 0)

38820

+ || (CONST_DOUBLE_P (new_rtx) && CONST_DOUBLE_HIGH (new_rtx) >= 0))

38821

+ validate_change (object, &XEXP (x, 0), new_rtx, 0);

38822

+ return x;

38823

+ }

38824

+

38825

case REG:

38826

i = REG_QTY (REGNO (x));

38827

38828

Index: gcc/tree-ssa-math-opts.c

38829

===================================================================

38830

--- a/src/gcc/tree-ssa-math-opts.c (.../tags/gcc_4_8_2_release)

38831

+++ b/src/gcc/tree-ssa-math-opts.c (.../branches/gcc-4_8-branch)

38832

@@ -1718,7 +1718,9 @@

38833

38834

if (rhs_class == GIMPLE_BINARY_RHS)

38835

{

38836

+ int i;

38837

struct symbolic_number n1, n2;

38838

+ unsigned HOST_WIDEST_INT mask;

38839

tree source_expr2;

38840

38841

if (code != BIT_IOR_EXPR)

38842

@@ -1744,6 +1746,15 @@

38843

return NULL_TREE;

38844

38845

n->size = n1.size;

38846

+ for (i = 0, mask = 0xff; i < n->size; i++, mask <<= BITS_PER_UNIT)

38847

+ {

38848

+ unsigned HOST_WIDEST_INT masked1, masked2;

38849

+

38850

+ masked1 = n1.n & mask;

38851

+ masked2 = n2.n & mask;

38852

+ if (masked1 && masked2 && masked1 != masked2)

38853

+ return NULL_TREE;

38854

+ }

38855

n->n = n1.n | n2.n;

38856

38857

if (!verify_symbolic_number_p (n, stmt))

38858

Index: gcc/tree-ssa-propagate.c

38859

===================================================================

38860

--- a/src/gcc/tree-ssa-propagate.c (.../tags/gcc_4_8_2_release)

38861

+++ b/src/gcc/tree-ssa-propagate.c (.../branches/gcc-4_8-branch)

38862

@@ -556,8 +556,18 @@

38863

/* All constants are ok. */

38864

break;

38865

38866

+ case tcc_comparison:

38867

+ /* GENERIC allows comparisons with non-boolean types, reject

38868

+ those for GIMPLE. Let vector-typed comparisons pass - rules

38869

+ for GENERIC and GIMPLE are the same here. */

38870

+ if (!(INTEGRAL_TYPE_P (TREE_TYPE (expr))

38871

+ && (TREE_CODE (TREE_TYPE (expr)) == BOOLEAN_TYPE

38872

+ || TYPE_PRECISION (TREE_TYPE (expr)) == 1))

38873

+ && TREE_CODE (TREE_TYPE (expr)) != VECTOR_TYPE)

38874

+ return false;

38875

+

38876

+ /* Fallthru. */

38877

case tcc_binary:

38878

- case tcc_comparison:

38879

if (!is_gimple_val (TREE_OPERAND (expr, 0))

38880

|| !is_gimple_val (TREE_OPERAND (expr, 1)))

38881

return false;

38882

Index: gcc/sel-sched.c

38883

===================================================================

38884

--- a/src/gcc/sel-sched.c (.../tags/gcc_4_8_2_release)

38885

+++ b/src/gcc/sel-sched.c (.../branches/gcc-4_8-branch)

38886

@@ -1253,7 +1253,7 @@

38887

38888

if (!HARD_FRAME_POINTER_IS_FRAME_POINTER)

38889

add_to_hard_reg_set (&reg_rename_p->unavailable_hard_regs,

38890

- Pmode, HARD_FRAME_POINTER_IS_FRAME_POINTER);

38891

+ Pmode, HARD_FRAME_POINTER_REGNUM);

38892

}

38893

38894

#ifdef STACK_REGS

38895

Index: gcc/gimple-low.c

38896

===================================================================

38897

--- a/src/gcc/gimple-low.c (.../tags/gcc_4_8_2_release)

38898

+++ b/src/gcc/gimple-low.c (.../branches/gcc-4_8-branch)

38899

@@ -238,6 +238,7 @@

38900

break;

38901

arg = gimple_call_arg (stmt, i);

38902

if (p == error_mark_node

38903

+ || DECL_ARG_TYPE (p) == error_mark_node

38904

|| arg == error_mark_node

38905

|| (!types_compatible_p (DECL_ARG_TYPE (p), TREE_TYPE (arg))

38906

&& !fold_convertible_p (DECL_ARG_TYPE (p), arg)))

38907

Index: gcc/tree-ssa-sink.c

38908

===================================================================

38909

--- a/src/gcc/tree-ssa-sink.c (.../tags/gcc_4_8_2_release)

38910

+++ b/src/gcc/tree-ssa-sink.c (.../branches/gcc-4_8-branch)

38911

@@ -559,7 +559,7 @@

38912

execute_sink_code (void)

38913

{

38914

loop_optimizer_init (LOOPS_NORMAL);

38915

-

38916

+ split_critical_edges ();

38917

connect_infinite_loops_to_exit ();

38918

memset (&sink_stats, 0, sizeof (sink_stats));

38919

calculate_dominance_info (CDI_DOMINATORS);

38920

Index: gcc/config.in

38921

===================================================================

38922

--- a/src/gcc/config.in (.../tags/gcc_4_8_2_release)

38923

+++ b/src/gcc/config.in (.../branches/gcc-4_8-branch)

38924

@@ -363,6 +363,12 @@

38925

#endif

38926

38927

38928

+/* Define if your assembler supports the 'ud2' mnemonic. */

38929

+#ifndef USED_FOR_TARGET

38930

+#undef HAVE_AS_IX86_UD2

38931

+#endif

38932

+

38933

+

38934

/* Define if your assembler supports the lituse_jsrdirect relocation. */

38935

#ifndef USED_FOR_TARGET

38936

#undef HAVE_AS_JSRDIRECT_RELOCS

38937

@@ -375,6 +381,12 @@

38938

#endif

38939

38940

38941

+/* Define if your assembler supports LEON instructions. */

38942

+#ifndef USED_FOR_TARGET

38943

+#undef HAVE_AS_LEON

38944

+#endif

38945

+

38946

+

38947

/* Define if the assembler won't complain about a line such as # 0 "" 2. */

38948

#ifndef USED_FOR_TARGET

38949

#undef HAVE_AS_LINE_ZERO

38950

Index: gcc/ifcvt.c

38951

===================================================================

38952

--- a/src/gcc/ifcvt.c (.../tags/gcc_4_8_2_release)

38953

+++ b/src/gcc/ifcvt.c (.../branches/gcc-4_8-branch)

38954

@@ -115,7 +115,11 @@

38955

38956

while (1)

38957

{

38958

- if (CALL_P (insn) || NONJUMP_INSN_P (insn))

38959

+ if ((CALL_P (insn) || NONJUMP_INSN_P (insn))

38960

+ /* Don't count USE/CLOBBER insns, flow_find_cross_jump etc.

38961

+ don't count them either and we need consistency. */

38962

+ && GET_CODE (PATTERN (insn)) != USE

38963

+ && GET_CODE (PATTERN (insn)) != CLOBBER)

38964

count++;

38965

38966

if (insn == BB_END (bb))

38967

@@ -505,7 +509,10 @@

38968

n_insns -= 2 * n_matching;

38969

}

38970

38971

- if (then_start && else_start)

38972

+ if (then_start

38973

+ && else_start

38974

+ && then_n_insns > n_matching

38975

+ && else_n_insns > n_matching)

38976

{

38977

int longest_match = MIN (then_n_insns - n_matching,

38978

else_n_insns - n_matching);

38979

Index: gcc/expr.c

38980

===================================================================

38981

--- a/src/gcc/expr.c (.../tags/gcc_4_8_2_release)

38982

+++ b/src/gcc/expr.c (.../branches/gcc-4_8-branch)

38983

@@ -1994,12 +1994,14 @@

38984

HOST_WIDE_INT bytepos = INTVAL (XEXP (XVECEXP (src, 0, i), 1));

38985

enum machine_mode mode = GET_MODE (tmps[i]);

38986

unsigned int bytelen = GET_MODE_SIZE (mode);

38987

- unsigned int adj_bytelen = bytelen;

38988

+ unsigned int adj_bytelen;

38989

rtx dest = dst;

38990

38991

/* Handle trailing fragments that run over the size of the struct. */

38992

if (ssize >= 0 && bytepos + (HOST_WIDE_INT) bytelen > ssize)

38993

adj_bytelen = ssize - bytepos;

38994

+ else

38995

+ adj_bytelen = bytelen;

38996

38997

if (GET_CODE (dst) == CONCAT)

38998

{

38999

@@ -2040,6 +2042,7 @@

39000

}

39001

}

39002

39003

+ /* Handle trailing fragments that run over the size of the struct. */

39004

if (ssize >= 0 && bytepos + (HOST_WIDE_INT) bytelen > ssize)

39005

{

39006

/* store_bit_field always takes its value from the lsb.

39007

@@ -2057,16 +2060,22 @@

39008

tmps[i] = expand_shift (RSHIFT_EXPR, mode, tmps[i],

39009

shift, tmps[i], 0);

39010

}

39011

- bytelen = adj_bytelen;

39012

+

39013

+ /* Make sure not to write past the end of the struct. */

39014

+ store_bit_field (dest,

39015

+ adj_bytelen * BITS_PER_UNIT, bytepos * BITS_PER_UNIT,

39016

+ bytepos * BITS_PER_UNIT, ssize * BITS_PER_UNIT - 1,

39017

+ VOIDmode, tmps[i]);

39018

}

39019

39020

/* Optimize the access just a bit. */

39021

- if (MEM_P (dest)

39022

- && (! SLOW_UNALIGNED_ACCESS (mode, MEM_ALIGN (dest))

39023

- || MEM_ALIGN (dest) >= GET_MODE_ALIGNMENT (mode))

39024

- && bytepos * BITS_PER_UNIT % GET_MODE_ALIGNMENT (mode) == 0

39025

- && bytelen == GET_MODE_SIZE (mode))

39026

+ else if (MEM_P (dest)

39027

+ && (!SLOW_UNALIGNED_ACCESS (mode, MEM_ALIGN (dest))

39028

+ || MEM_ALIGN (dest) >= GET_MODE_ALIGNMENT (mode))

39029

+ && bytepos * BITS_PER_UNIT % GET_MODE_ALIGNMENT (mode) == 0

39030

+ && bytelen == GET_MODE_SIZE (mode))

39031

emit_move_insn (adjust_address (dest, mode, bytepos), tmps[i]);

39032

+

39033

else

39034

store_bit_field (dest, bytelen * BITS_PER_UNIT, bytepos * BITS_PER_UNIT,

39035

0, 0, mode, tmps[i]);

39036

@@ -3602,12 +3611,21 @@

39037

into a new pseudo. This constant may be used in different modes,

39038

and if not, combine will put things back together for us. */

39039

trunc_y = force_reg (srcmode, trunc_y);

39040

- emit_unop_insn (ic, x, trunc_y, UNKNOWN);

39041

+

39042

+ /* If x is a hard register, perform the extension into a pseudo,

39043

+ so that e.g. stack realignment code is aware of it. */

39044

+ rtx target = x;

39045

+ if (REG_P (x) && HARD_REGISTER_P (x))

39046

+ target = gen_reg_rtx (dstmode);

39047

+

39048

+ emit_unop_insn (ic, target, trunc_y, UNKNOWN);

39049

last_insn = get_last_insn ();

39050

39051

- if (REG_P (x))

39052

+ if (REG_P (target))

39053

set_unique_reg_note (last_insn, REG_EQUAL, y);

39054

39055

+ if (target != x)

39056

+ return emit_move_insn (x, target);

39057

return last_insn;

39058

}

39059

39060

@@ -4551,19 +4569,19 @@

39061

- tree_low_cst (DECL_FIELD_BIT_OFFSET (repr), 1));

39062

39063

/* If the adjustment is larger than bitpos, we would have a negative bit

39064

- position for the lower bound and this may wreak havoc later. This can

39065

- occur only if we have a non-null offset, so adjust offset and bitpos

39066

- to make the lower bound non-negative. */

39067

+ position for the lower bound and this may wreak havoc later. Adjust

39068

+ offset and bitpos to make the lower bound non-negative in that case. */

39069

if (bitoffset > *bitpos)

39070

{

39071

HOST_WIDE_INT adjust = bitoffset - *bitpos;

39072

-

39073

gcc_assert ((adjust % BITS_PER_UNIT) == 0);

39074

- gcc_assert (*offset != NULL_TREE);

39075

39076

*bitpos += adjust;

39077

- *offset

39078

- = size_binop (MINUS_EXPR, *offset, size_int (adjust / BITS_PER_UNIT));

39079

+ if (*offset == NULL_TREE)

39080

+ *offset = size_int (-adjust / BITS_PER_UNIT);

39081

+ else

39082

+ *offset

39083

+ = size_binop (MINUS_EXPR, *offset, size_int (adjust / BITS_PER_UNIT));

39084

*bitstart = 0;

39085

}

39086

else

39087

@@ -4668,8 +4686,7 @@

39088

expand_insn (icode, 2, ops);

39089

}

39090

else

39091

- store_bit_field (mem, GET_MODE_BITSIZE (mode),

39092

- 0, 0, 0, mode, reg);

39093

+ store_bit_field (mem, GET_MODE_BITSIZE (mode), 0, 0, 0, mode, reg);

39094

return;

39095

}

39096

39097

@@ -4698,6 +4715,15 @@

39098

tem = get_inner_reference (to, &bitsize, &bitpos, &offset, &mode1,

39099

&unsignedp, &volatilep, true);

39100

39101

+ /* Make sure bitpos is not negative, it can wreak havoc later. */

39102

+ if (bitpos < 0)

39103

+ {

39104

+ gcc_assert (offset == NULL_TREE);

39105

+ offset = size_int (bitpos >> (BITS_PER_UNIT == 8

39106

+ ? 3 : exact_log2 (BITS_PER_UNIT)));

39107

+ bitpos &= BITS_PER_UNIT - 1;

39108

+ }

39109

+

39110

if (TREE_CODE (to) == COMPONENT_REF

39111

&& DECL_BIT_FIELD_TYPE (TREE_OPERAND (to, 1)))

39112

get_bit_range (&bitregion_start, &bitregion_end, to, &bitpos, &offset);

39113

Index: gcc/expr.h

39114

===================================================================

39115

--- a/src/gcc/expr.h (.../tags/gcc_4_8_2_release)

39116

+++ b/src/gcc/expr.h (.../branches/gcc-4_8-branch)

39117

@@ -521,8 +521,8 @@

39118

rtx, int);

39119

#endif

39120

39121

-extern void locate_and_pad_parm (enum machine_mode, tree, int, int, tree,

39122

- struct args_size *,

39123

+extern void locate_and_pad_parm (enum machine_mode, tree, int, int, int,

39124

+ tree, struct args_size *,

39125

struct locate_and_pad_arg_data *);

39126

39127

/* Return the CODE_LABEL rtx for a LABEL_DECL, creating it if necessary. */

39128

Index: gcc/go/go-gcc.cc

39129

===================================================================

39130

--- a/src/gcc/go/go-gcc.cc (.../tags/gcc_4_8_2_release)

39131

+++ b/src/gcc/go/go-gcc.cc (.../branches/gcc-4_8-branch)

39132

@@ -232,6 +232,9 @@

39133

Bexpression*

39134

convert_expression(Btype* type, Bexpression* expr, Location);

39135

39136

+ Bexpression*

39137

+ function_code_expression(Bfunction*, Location);

39138

+

39139

// Statements.

39140

39141

Bstatement*

39142

@@ -334,6 +337,17 @@

39143

Bexpression*

39144

label_address(Blabel*, Location);

39145

39146

+ // Functions.

39147

+

39148

+ Bfunction*

39149

+ error_function()

39150

+ { return this->make_function(error_mark_node); }

39151

+

39152

+ Bfunction*

39153

+ function(Btype* fntype, const std::string& name, const std::string& asm_name,

39154

+ bool is_visible, bool is_declaration, bool is_inlinable,

39155

+ bool disable_split_stack, bool in_unique_section, Location);

39156

+

39157

private:

39158

// Make a Bexpression from a tree.

39159

Bexpression*

39160

@@ -350,6 +364,10 @@

39161

make_type(tree t)

39162

{ return new Btype(t); }

39163

39164

+ Bfunction*

39165

+ make_function(tree t)

39166

+ { return new Bfunction(t); }

39167

+

39168

Btype*

39169

fill_in_struct(Btype*, const std::vector<Btyped_identifier>&);

39170

39171

@@ -966,6 +984,19 @@

39172

return tree_to_expr(ret);

39173

}

39174

39175

+// Get the address of a function.

39176

+

39177

+Bexpression*

39178

+Gcc_backend::function_code_expression(Bfunction* bfunc, Location location)

39179

+{

39180

+ tree func = bfunc->get_tree();

39181

+ if (func == error_mark_node)

39182

+ return this->error_expression();

39183

+

39184

+ tree ret = build_fold_addr_expr_loc(location.gcc_location(), func);

39185

+ return this->make_expression(ret);

39186

+}

39187

+

39188

// An expression as a statement.

39189

39190

Bstatement*

39191

@@ -1724,6 +1755,56 @@

39192

return this->make_expression(ret);

39193

}

39194

39195

+// Declare or define a new function.

39196

+

39197

+Bfunction*

39198

+Gcc_backend::function(Btype* fntype, const std::string& name,

39199

+ const std::string& asm_name, bool is_visible,

39200

+ bool is_declaration, bool is_inlinable,

39201

+ bool disable_split_stack, bool in_unique_section,

39202

+ Location location)

39203

+{

39204

+ tree functype = fntype->get_tree();

39205

+ if (functype != error_mark_node)

39206

+ {

39207

+ gcc_assert(FUNCTION_POINTER_TYPE_P(functype));

39208

+ functype = TREE_TYPE(functype);

39209

+ }

39210

+ tree id = get_identifier_from_string(name);

39211

+ if (functype == error_mark_node || id == error_mark_node)

39212

+ return this->error_function();

39213

+

39214

+ tree decl = build_decl(location.gcc_location(), FUNCTION_DECL, id, functype);

39215

+ if (!asm_name.empty())

39216

+ SET_DECL_ASSEMBLER_NAME(decl, get_identifier_from_string(asm_name));

39217

+ if (is_visible)

39218

+ TREE_PUBLIC(decl) = 1;

39219

+ if (is_declaration)

39220

+ DECL_EXTERNAL(decl) = 1;

39221

+ else

39222

+ {

39223

+ tree restype = TREE_TYPE(functype);

39224

+ tree resdecl =

39225

+ build_decl(location.gcc_location(), RESULT_DECL, NULL_TREE, restype);

39226

+ DECL_ARTIFICIAL(resdecl) = 1;

39227

+ DECL_IGNORED_P(resdecl) = 1;

39228

+ DECL_CONTEXT(resdecl) = decl;

39229

+ DECL_RESULT(decl) = resdecl;

39230

+ }

39231

+ if (!is_inlinable)

39232

+ DECL_UNINLINABLE(decl) = 1;

39233

+ if (disable_split_stack)

39234

+ {

39235

+ tree attr = get_identifier("__no_split_stack__");

39236

+ DECL_ATTRIBUTES(decl) = tree_cons(attr, NULL_TREE, NULL_TREE);

39237

+ }

39238

+ if (in_unique_section)

39239

+ resolve_unique_section(decl, 0, 1);

39240

+

39241

+ go_preserve_from_gc(decl);

39242

+ return new Bfunction(decl);

39243

+}

39244

+

39245

// The single backend.

39246

39247

static Gcc_backend gcc_backend;

39248

@@ -1799,3 +1880,9 @@

39249

{

39250

return bv->get_tree();

39251

}

39252

+

39253

+tree

39254

+function_to_tree(Bfunction* bf)

39255

+{

39256

+ return bf->get_tree();

39257

+}

39258

Index: gcc/go/ChangeLog

39259

===================================================================

39260

--- a/src/gcc/go/ChangeLog (.../tags/gcc_4_8_2_release)

39261

+++ b/src/gcc/go/ChangeLog (.../branches/gcc-4_8-branch)

39262

@@ -1,3 +1,22 @@

39263

+2013-12-11 Ian Lance Taylor <iant@google.com>

39264

+

39265

+ * go-lang.c (go_langhook_post_options): Disable sibling calls by

39266

+ default.

39267

+

39268

+2013-10-16 Ian Lance Taylor <iant@google.com>

39269

+

39270

+ Bring in from mainline:

39271

+

39272

+ 2013-10-11 Chris Manghane <cmang@google.com>

39273

+ * go-gcc.cc (Gcc_backend::function_code_expression): New

39274

+ function.

39275

+

39276

+ 2013-10-10 Chris Manghane <cmang@google.com>

39277

+ * go-gcc.cc (Backend::error_function): New function.

39278

+ (Backend::function): New function.

39279

+ (Backend::make_function): New function.

39280

+ (function_to_tree): New function.

39281

+

39282

2013-10-16 Release Manager

39283

39284

* GCC 4.8.2 released.

39285

Index: gcc/go/go-lang.c

39286

===================================================================

39287

--- a/src/gcc/go/go-lang.c (.../tags/gcc_4_8_2_release)

39288

+++ b/src/gcc/go/go-lang.c (.../branches/gcc-4_8-branch)

39289

@@ -269,6 +269,10 @@

39290

if (flag_excess_precision_cmdline == EXCESS_PRECISION_DEFAULT)

39291

flag_excess_precision_cmdline = EXCESS_PRECISION_STANDARD;

39292

39293

+ /* Tail call optimizations can confuse uses of runtime.Callers. */

39294

+ if (!global_options_set.x_flag_optimize_sibling_calls)

39295

+ global_options.x_flag_optimize_sibling_calls = 0;

39296

+

39297

/* Returning false means that the backend should be used. */

39298

return false;

39299

}

39300

Index: gcc/go/gofrontend/gogo.cc

39301

===================================================================

39302

--- a/src/gcc/go/gofrontend/gogo.cc (.../tags/gcc_4_8_2_release)

39303

+++ b/src/gcc/go/gofrontend/gogo.cc (.../branches/gcc-4_8-branch)

39304

@@ -2822,7 +2822,10 @@

39305

if (orig_fntype->is_varargs())

39306

new_fntype->set_is_varargs();

39307

39308

- std::string name = orig_no->name() + "$recover";

39309

+ std::string name = orig_no->name();

39310

+ if (orig_fntype->is_method())

39311

+ name += "$" + orig_fntype->receiver()->type()->mangled_name(gogo);

39312

+ name += "$recover";

39313

Named_object *new_no = gogo->start_function(name, new_fntype, false,

39314

location);

39315

Function *new_func = new_no->func_value();

39316

@@ -2916,7 +2919,25 @@

39317

&& !orig_rec_no->var_value()->is_receiver());

39318

orig_rec_no->var_value()->set_is_receiver();

39319

39320

- const std::string& new_receiver_name(orig_fntype->receiver()->name());

39321

+ std::string new_receiver_name(orig_fntype->receiver()->name());

39322

+ if (new_receiver_name.empty())

39323

+ {

39324

+ // Find the receiver. It was named "r.NNN" in

39325

+ // Gogo::start_function.

39326

+ for (Bindings::const_definitions_iterator p =

39327

+ new_bindings->begin_definitions();

39328

+ p != new_bindings->end_definitions();

39329

+ ++p)

39330

+ {

39331

+ const std::string& pname((*p)->name());

39332

+ if (pname[0] == 'r' && pname[1] == '.')

39333

+ {

39334

+ new_receiver_name = pname;

39335

+ break;

39336

+ }

39337

+ }

39338

+ go_assert(!new_receiver_name.empty());

39339

+ }

39340

Named_object* new_rec_no = new_bindings->lookup_local(new_receiver_name);

39341

if (new_rec_no == NULL)

39342

go_assert(saw_errors());

39343

@@ -3320,7 +3341,8 @@

39344

closure_var_(NULL), block_(block), location_(location), labels_(),

39345

local_type_count_(0), descriptor_(NULL), fndecl_(NULL), defer_stack_(NULL),

39346

is_sink_(false), results_are_named_(false), nointerface_(false),

39347

- calls_recover_(false), is_recover_thunk_(false), has_recover_thunk_(false),

39348

+ is_unnamed_type_stub_method_(false), calls_recover_(false),

39349

+ is_recover_thunk_(false), has_recover_thunk_(false),

39350

in_unique_section_(false)

39351

{

39352

}

39353

@@ -3819,6 +3841,81 @@

39354

*presults = results;

39355

}

39356

39357

+// Get the backend representation.

39358

+

39359

+Bfunction*

39360

+Function::get_or_make_decl(Gogo* gogo, Named_object* no)

39361

+{

39362

+ if (this->fndecl_ == NULL)

39363

+ {

39364

+ std::string asm_name;

39365

+ bool is_visible = false;

39366

+ if (no->package() != NULL)

39367

+ ;

39368

+ else if (this->enclosing_ != NULL || Gogo::is_thunk(no))

39369

+ ;

39370

+ else if (Gogo::unpack_hidden_name(no->name()) == "init"

39371

+ && !this->type_->is_method())

39372

+ ;

39373

+ else if (Gogo::unpack_hidden_name(no->name()) == "main"

39374

+ && gogo->is_main_package())

39375

+ is_visible = true;

39376

+ // Methods have to be public even if they are hidden because

39377

+ // they can be pulled into type descriptors when using

39378

+ // anonymous fields.

39379

+ else if (!Gogo::is_hidden_name(no->name())

39380

+ || this->type_->is_method())

39381

+ {

39382

+ if (!this->is_unnamed_type_stub_method_)

39383

+ is_visible = true;

39384

+ std::string pkgpath = gogo->pkgpath_symbol();

39385

+ if (this->type_->is_method()

39386

+ && Gogo::is_hidden_name(no->name())

39387

+ && Gogo::hidden_name_pkgpath(no->name()) != gogo->pkgpath())

39388

+ {

39389

+ // This is a method we created for an unexported

39390

+ // method of an imported embedded type. We need to

39391

+ // use the pkgpath of the imported package to avoid

39392

+ // a possible name collision. See bug478 for a test

39393

+ // case.

39394

+ pkgpath = Gogo::hidden_name_pkgpath(no->name());

39395

+ pkgpath = Gogo::pkgpath_for_symbol(pkgpath);

39396

+ }

39397

+

39398

+ asm_name = pkgpath;

39399

+ asm_name.append(1, '.');

39400

+ asm_name.append(Gogo::unpack_hidden_name(no->name()));

39401

+ if (this->type_->is_method())

39402

+ {

39403

+ asm_name.append(1, '.');

39404

+ Type* rtype = this->type_->receiver()->type();

39405

+ asm_name.append(rtype->mangled_name(gogo));

39406

+ }

39407

+ }

39408

+

39409

+ // If a function calls the predeclared recover function, we

39410

+ // can't inline it, because recover behaves differently in a

39411

+ // function passed directly to defer. If this is a recover

39412

+ // thunk that we built to test whether a function can be

39413

+ // recovered, we can't inline it, because that will mess up

39414

+ // our return address comparison.

39415

+ bool is_inlinable = !(this->calls_recover_ || this->is_recover_thunk_);

39416

+

39417

+ // If this is a thunk created to call a function which calls

39418

+ // the predeclared recover function, we need to disable

39419

+ // stack splitting for the thunk.

39420

+ bool disable_split_stack = this->is_recover_thunk_;

39421

+

39422

+ Btype* functype = this->type_->get_backend_fntype(gogo);

39423

+ this->fndecl_ =

39424

+ gogo->backend()->function(functype, no->get_id(gogo), asm_name,

39425

+ is_visible, false, is_inlinable,

39426

+ disable_split_stack,

39427

+ this->in_unique_section_, this->location());

39428

+ }

39429

+ return this->fndecl_;

39430

+}

39431

+

39432

// Class Block.

39433

39434

Block::Block(Block* enclosing, Location location)

39435

@@ -5110,6 +5207,75 @@

39436

go_unreachable();

39437

}

39438

39439

+

39440

+// Return the external identifier for this object.

39441

+

39442

+std::string

39443

+Named_object::get_id(Gogo* gogo)

39444

+{

39445

+ go_assert(!this->is_variable() && !this->is_result_variable());

39446

+ std::string decl_name;

39447

+ if (this->is_function_declaration()

39448

+ && !this->func_declaration_value()->asm_name().empty())

39449

+ decl_name = this->func_declaration_value()->asm_name();

39450

+ else if (this->is_type()

39451

+ && Linemap::is_predeclared_location(this->type_value()->location()))

39452

+ {

39453

+ // We don't need the package name for builtin types.

39454

+ decl_name = Gogo::unpack_hidden_name(this->name_);

39455

+ }

39456

+ else

39457

+ {

39458

+ std::string package_name;

39459

+ if (this->package_ == NULL)

39460

+ package_name = gogo->package_name();

39461

+ else

39462

+ package_name = this->package_->package_name();

39463

+

39464

+ // Note that this will be misleading if this is an unexported

39465

+ // method generated for an embedded imported type. In that case

39466

+ // the unexported method should have the package name of the

39467

+ // package from which it is imported, but we are going to give

39468

+ // it our package name. Fixing this would require knowing the

39469

+ // package name, but we only know the package path. It might be

39470

+ // better to use package paths here anyhow. This doesn't affect

39471

+ // the assembler code, because we always set that name in

39472

+ // Function::get_or_make_decl anyhow. FIXME.

39473

+

39474

+ decl_name = package_name + '.' + Gogo::unpack_hidden_name(this->name_);

39475

+

39476

+ Function_type* fntype;

39477

+ if (this->is_function())

39478

+ fntype = this->func_value()->type();

39479

+ else if (this->is_function_declaration())

39480

+ fntype = this->func_declaration_value()->type();

39481

+ else

39482

+ fntype = NULL;

39483

+ if (fntype != NULL && fntype->is_method())

39484

+ {

39485

+ decl_name.push_back('.');

39486

+ decl_name.append(fntype->receiver()->type()->mangled_name(gogo));

39487

+ }

39488

+ }

39489

+ if (this->is_type())

39490

+ {

39491

+ unsigned int index;

39492

+ const Named_object* in_function = this->type_value()->in_function(&index);

39493

+ if (in_function != NULL)

39494

+ {

39495

+ decl_name += '$' + Gogo::unpack_hidden_name(in_function->name());

39496

+ if (index > 0)

39497

+ {

39498

+ char buf[30];

39499

+ snprintf(buf, sizeof buf, "%u", index);

39500

+ decl_name += '$';

39501

+ decl_name += buf;

39502

+ }

39503

+ }

39504

+ }

39505

+ return decl_name;

39506

+}

39507

+

39508

// Class Bindings.

39509

39510

Bindings::Bindings(Bindings* enclosing)

39511

Index: gcc/go/gofrontend/runtime.def

39512

===================================================================

39513

--- a/src/gcc/go/gofrontend/runtime.def (.../tags/gcc_4_8_2_release)

39514

+++ b/src/gcc/go/gofrontend/runtime.def (.../branches/gcc-4_8-branch)

39515

@@ -68,6 +68,12 @@

39516

P1(STRING), R1(SLICE))

39517

39518

39519

+// Complex division.

39520

+DEF_GO_RUNTIME(COMPLEX64_DIV, "__go_complex64_div",

39521

+ P2(COMPLEX64, COMPLEX64), R1(COMPLEX64))

39522

+DEF_GO_RUNTIME(COMPLEX128_DIV, "__go_complex128_div",

39523

+ P2(COMPLEX128, COMPLEX128), R1(COMPLEX128))

39524

+

39525

// Make a slice.

39526

DEF_GO_RUNTIME(MAKESLICE1, "__go_make_slice1", P2(TYPE, UINTPTR), R1(SLICE))

39527

DEF_GO_RUNTIME(MAKESLICE2, "__go_make_slice2", P3(TYPE, UINTPTR, UINTPTR),

39528

Index: gcc/go/gofrontend/gogo.h

39529

===================================================================

39530

--- a/src/gcc/go/gofrontend/gogo.h (.../tags/gcc_4_8_2_release)

39531

+++ b/src/gcc/go/gofrontend/gogo.h (.../branches/gcc-4_8-branch)

39532

@@ -48,6 +48,7 @@

39533

class Bblock;

39534

class Bvariable;

39535

class Blabel;

39536

+class Bfunction;

39537

39538

// This file declares the basic classes used to hold the internal

39539

// representation of Go which is built by the parser.

39540

@@ -952,6 +953,15 @@

39541

this->nointerface_ = true;

39542

}

39543

39544

+ // Record that this function is a stub method created for an unnamed

39545

+ // type.

39546

+ void

39547

+ set_is_unnamed_type_stub_method()

39548

+ {

39549

+ go_assert(this->is_method());

39550

+ this->is_unnamed_type_stub_method_ = true;

39551

+ }

39552

+

39553

// Add a new field to the closure variable.

39554

void

39555

add_closure_field(Named_object* var, Location loc)

39556

@@ -1089,17 +1099,13 @@

39557

this->descriptor_ = descriptor;

39558

}

39559

39560

- // Return the function's decl given an identifier.

39561

- tree

39562

- get_or_make_decl(Gogo*, Named_object*, tree id);

39563

+ // Return the backend representation.

39564

+ Bfunction*

39565

+ get_or_make_decl(Gogo*, Named_object*);

39566

39567

// Return the function's decl after it has been built.

39568

tree

39569

- get_decl() const

39570

- {

39571

- go_assert(this->fndecl_ != NULL);

39572

- return this->fndecl_;

39573

- }

39574

+ get_decl() const;

39575

39576

// Set the function decl to hold a tree of the function code.

39577

void

39578

@@ -1170,7 +1176,7 @@

39579

// The function descriptor, if any.

39580

Expression* descriptor_;

39581

// The function decl.

39582

- tree fndecl_;

39583

+ Bfunction* fndecl_;

39584

// The defer stack variable. A pointer to this variable is used to

39585

// distinguish the defer stack for one function from another. This

39586

// is NULL unless we actually need a defer stack.

39587

@@ -1181,6 +1187,9 @@

39588

bool results_are_named_ : 1;

39589

// True if this method should not be included in the type descriptor.

39590

bool nointerface_ : 1;

39591

+ // True if this function is a stub method created for an unnamed

39592

+ // type.

39593

+ bool is_unnamed_type_stub_method_ : 1;

39594

// True if this function calls the predeclared recover function.

39595

bool calls_recover_ : 1;

39596

// True if this a thunk built for a function which calls recover.

39597

@@ -1265,9 +1274,9 @@

39598

has_descriptor() const

39599

{ return this->descriptor_ != NULL; }

39600

39601

- // Return a decl for the function given an identifier.

39602

- tree

39603

- get_or_make_decl(Gogo*, Named_object*, tree id);

39604

+ // Return a backend representation.

39605

+ Bfunction*

39606

+ get_or_make_decl(Gogo*, Named_object*);

39607

39608

// If there is a descriptor, build it into the backend

39609

// representation.

39610

@@ -1290,7 +1299,7 @@

39611

// The function descriptor, if any.

39612

Expression* descriptor_;

39613

// The function decl if needed.

39614

- tree fndecl_;

39615

+ Bfunction* fndecl_;

39616

};

39617

39618

// A variable.

39619

@@ -2181,8 +2190,8 @@

39620

Bvariable*

39621

get_backend_variable(Gogo*, Named_object* function);

39622

39623

- // Return a tree for the external identifier for this object.

39624

- tree

39625

+ // Return the external identifier for this object.

39626

+ std::string

39627

get_id(Gogo*);

39628

39629

// Return a tree representing this object.

39630

Index: gcc/go/gofrontend/types.h

39631

===================================================================

39632

--- a/src/gcc/go/gofrontend/types.h (.../tags/gcc_4_8_2_release)

39633

+++ b/src/gcc/go/gofrontend/types.h (.../branches/gcc-4_8-branch)

39634

@@ -1138,6 +1138,13 @@

39635

Function_type* equal_fntype, Named_object** hash_fn,

39636

Named_object** equal_fn);

39637

39638

+ void

39639

+ write_named_hash(Gogo*, Named_type*, Function_type* hash_fntype,

39640

+ Function_type* equal_fntype);

39641

+

39642

+ void

39643

+ write_named_equal(Gogo*, Named_type*);

39644

+

39645

// Build a composite literal for the uncommon type information.

39646

Expression*

39647

uncommon_type_constructor(Gogo*, Type* uncommon_type,

39648

@@ -1717,7 +1724,8 @@

39649

Typed_identifier_list* results, Location location)

39650

: Type(TYPE_FUNCTION),

39651

receiver_(receiver), parameters_(parameters), results_(results),

39652

- location_(location), is_varargs_(false), is_builtin_(false)

39653

+ location_(location), is_varargs_(false), is_builtin_(false),

39654

+ fnbtype_(NULL)

39655

{ }

39656

39657

// Get the receiver.

39658

@@ -1789,6 +1797,12 @@

39659

Function_type*

39660

copy_with_receiver(Type*) const;

39661

39662

+ // Return a copy of this type with the receiver treated as the first

39663

+ // parameter. If WANT_POINTER_RECEIVER is true, the receiver is

39664

+ // forced to be a pointer.

39665

+ Function_type*

39666

+ copy_with_receiver_as_param(bool want_pointer_receiver) const;

39667

+

39668

// Return a copy of this type ignoring any receiver and using dummy

39669

// names for all parameters. This is used for thunks for method

39670

// values.

39671

@@ -1798,6 +1812,11 @@

39672

static Type*

39673

make_function_type_descriptor_type();

39674

39675

+ // Return the backend representation of this function type. This is used

39676

+ // as the real type of a backend function declaration or defintion.

39677

+ Btype*

39678

+ get_backend_fntype(Gogo*);

39679

+

39680

protected:

39681

int

39682

do_traverse(Traverse*);

39683

@@ -1851,6 +1870,9 @@

39684

// Whether this is a special builtin function which can not simply

39685

// be called. This is used for len, cap, etc.

39686

bool is_builtin_;

39687

+ // The backend representation of this type for backend function

39688

+ // declarations and definitions.

39689

+ Btype* fnbtype_;

39690

};

39691

39692

// The type of a pointer.

39693

@@ -1915,7 +1937,7 @@

39694

{

39695

public:

39696

explicit Struct_field(const Typed_identifier& typed_identifier)

39697

- : typed_identifier_(typed_identifier), tag_(NULL)

39698

+ : typed_identifier_(typed_identifier), tag_(NULL), is_imported_(false)

39699

{ }

39700

39701

// The field name.

39702

@@ -1926,6 +1948,10 @@

39703

bool

39704

is_field_name(const std::string& name) const;

39705

39706

+ // Return whether this struct field is an unexported field named NAME.

39707

+ bool

39708

+ is_unexported_field_name(Gogo*, const std::string& name) const;

39709

+

39710

// Return whether this struct field is an embedded built-in type.

39711

bool

39712

is_embedded_builtin(Gogo*) const;

39713

@@ -1963,6 +1989,11 @@

39714

set_tag(const std::string& tag)

39715

{ this->tag_ = new std::string(tag); }

39716

39717

+ // Record that this field is defined in an imported struct.

39718

+ void

39719

+ set_is_imported()

39720

+ { this->is_imported_ = true; }

39721

+

39722

// Set the type. This is only used in error cases.

39723

void

39724

set_type(Type* type)

39725

@@ -1973,6 +2004,8 @@

39726

Typed_identifier typed_identifier_;

39727

// The field tag. This is NULL if the field has no tag.

39728

std::string* tag_;

39729

+ // Whether this field is defined in an imported struct.

39730

+ bool is_imported_;

39731

};

39732

39733

// A list of struct fields.

39734

Index: gcc/go/gofrontend/parse.cc

39735

===================================================================

39736

--- a/src/gcc/go/gofrontend/parse.cc (.../tags/gcc_4_8_2_release)

39737

+++ b/src/gcc/go/gofrontend/parse.cc (.../branches/gcc-4_8-branch)

39738

@@ -744,6 +744,8 @@

39739

return NULL;

39740

39741

Parse::Names names;

39742

+ if (receiver != NULL)

39743

+ names[receiver->name()] = receiver;

39744

if (params != NULL)

39745

this->check_signature_names(params, &names);

39746

if (results != NULL)

39747

Index: gcc/go/gofrontend/import.h

39748

===================================================================

39749

--- a/src/gcc/go/gofrontend/import.h (.../tags/gcc_4_8_2_release)

39750

+++ b/src/gcc/go/gofrontend/import.h (.../branches/gcc-4_8-branch)

39751

@@ -149,6 +149,11 @@

39752

location() const

39753

{ return this->location_; }

39754

39755

+ // Return the package we are importing.

39756

+ Package*

39757

+ package() const

39758

+ { return this->package_; }

39759

+

39760

// Return the next character.

39761

int

39762

peek_char()

39763

Index: gcc/go/gofrontend/runtime.cc

39764

===================================================================

39765

--- a/src/gcc/go/gofrontend/runtime.cc (.../tags/gcc_4_8_2_release)

39766

+++ b/src/gcc/go/gofrontend/runtime.cc (.../branches/gcc-4_8-branch)

39767

@@ -42,6 +42,8 @@

39768

RFT_RUNE,

39769

// Go type float64, C type double.

39770

RFT_FLOAT64,

39771

+ // Go type complex64, C type __complex float.

39772

+ RFT_COMPLEX64,

39773

// Go type complex128, C type __complex double.

39774

RFT_COMPLEX128,

39775

// Go type string, C type struct __go_string.

39776

@@ -126,6 +128,10 @@

39777

t = Type::lookup_float_type("float64");

39778

break;

39779

39780

+ case RFT_COMPLEX64:

39781

+ t = Type::lookup_complex_type("complex64");

39782

+ break;

39783

+

39784

case RFT_COMPLEX128:

39785

t = Type::lookup_complex_type("complex128");

39786

break;

39787

@@ -216,6 +222,7 @@

39788

case RFT_UINTPTR:

39789

case RFT_RUNE:

39790

case RFT_FLOAT64:

39791

+ case RFT_COMPLEX64:

39792

case RFT_COMPLEX128:

39793

case RFT_STRING:

39794

case RFT_POINTER:

39795

Index: gcc/go/gofrontend/expressions.h

39796

===================================================================

39797

--- a/src/gcc/go/gofrontend/expressions.h (.../tags/gcc_4_8_2_release)

39798

+++ b/src/gcc/go/gofrontend/expressions.h (.../branches/gcc-4_8-branch)

39799

@@ -1514,8 +1514,8 @@

39800

closure()

39801

{ return this->closure_; }

39802

39803

- // Return a tree for the code for a function.

39804

- static tree

39805

+ // Return a backend expression for the code of a function.

39806

+ static Bexpression*

39807

get_code_pointer(Gogo*, Named_object* function, Location loc);

39808

39809

protected:

39810

Index: gcc/go/gofrontend/gogo-tree.cc

39811

===================================================================

39812

--- a/src/gcc/go/gofrontend/gogo-tree.cc (.../tags/gcc_4_8_2_release)

39813

+++ b/src/gcc/go/gofrontend/gogo-tree.cc (.../branches/gcc-4_8-branch)

39814

@@ -985,74 +985,6 @@

39815

delete[] vec;

39816

}

39817

39818

-// Get a tree for the identifier for a named object.

39819

-

39820

-tree

39821

-Named_object::get_id(Gogo* gogo)

39822

-{

39823

- go_assert(!this->is_variable() && !this->is_result_variable());

39824

- std::string decl_name;

39825

- if (this->is_function_declaration()

39826

- && !this->func_declaration_value()->asm_name().empty())

39827

- decl_name = this->func_declaration_value()->asm_name();

39828

- else if (this->is_type()

39829

- && Linemap::is_predeclared_location(this->type_value()->location()))

39830

- {

39831

- // We don't need the package name for builtin types.

39832

- decl_name = Gogo::unpack_hidden_name(this->name_);

39833

- }

39834

- else

39835

- {

39836

- std::string package_name;

39837

- if (this->package_ == NULL)

39838

- package_name = gogo->package_name();

39839

- else

39840

- package_name = this->package_->package_name();

39841

-

39842

- // Note that this will be misleading if this is an unexported

39843

- // method generated for an embedded imported type. In that case

39844

- // the unexported method should have the package name of the

39845

- // package from which it is imported, but we are going to give

39846

- // it our package name. Fixing this would require knowing the

39847

- // package name, but we only know the package path. It might be

39848

- // better to use package paths here anyhow. This doesn't affect

39849

- // the assembler code, because we always set that name in

39850

- // Function::get_or_make_decl anyhow. FIXME.

39851

-

39852

- decl_name = package_name + '.' + Gogo::unpack_hidden_name(this->name_);

39853

-

39854

- Function_type* fntype;

39855

- if (this->is_function())

39856

- fntype = this->func_value()->type();

39857

- else if (this->is_function_declaration())

39858

- fntype = this->func_declaration_value()->type();

39859

- else

39860

- fntype = NULL;

39861

- if (fntype != NULL && fntype->is_method())

39862

- {

39863

- decl_name.push_back('.');

39864

- decl_name.append(fntype->receiver()->type()->mangled_name(gogo));

39865

- }

39866

- }

39867

- if (this->is_type())

39868

- {

39869

- unsigned int index;

39870

- const Named_object* in_function = this->type_value()->in_function(&index);

39871

- if (in_function != NULL)

39872

- {

39873

- decl_name += '$' + Gogo::unpack_hidden_name(in_function->name());

39874

- if (index > 0)

39875

- {

39876

- char buf[30];

39877

- snprintf(buf, sizeof buf, "%u", index);

39878

- decl_name += '$';

39879

- decl_name += buf;

39880

- }

39881

- }

39882

- }

39883

- return get_identifier_from_string(decl_name);

39884

-}

39885

-

39886

// Get a tree for a named object.

39887

39888

tree

39889

@@ -1067,11 +999,6 @@

39890

return error_mark_node;

39891

}

39892

39893

- tree name;

39894

- if (this->classification_ == NAMED_OBJECT_TYPE)

39895

- name = NULL_TREE;

39896

- else

39897

- name = this->get_id(gogo);

39898

tree decl;

39899

switch (this->classification_)

39900

{

39901

@@ -1099,6 +1026,7 @@

39902

decl = error_mark_node;

39903

else if (INTEGRAL_TYPE_P(TREE_TYPE(expr_tree)))

39904

{

39905

+ tree name = get_identifier_from_string(this->get_id(gogo));

39906

decl = build_decl(named_constant->location().gcc_location(),

39907

CONST_DECL, name, TREE_TYPE(expr_tree));

39908

DECL_INITIAL(decl) = expr_tree;

39909

@@ -1161,7 +1089,7 @@

39910

case NAMED_OBJECT_FUNC:

39911

{

39912

Function* func = this->u_.func_value;

39913

- decl = func->get_or_make_decl(gogo, this, name);

39914

+ decl = function_to_tree(func->get_or_make_decl(gogo, this));

39915

if (decl != error_mark_node)

39916

{

39917

if (func->block() != NULL)

39918

@@ -1286,124 +1214,13 @@

39919

return block_tree;

39920

}

39921

39922

-// Get a tree for a function decl.

39923

+// Get the backend representation.

39924

39925

-tree

39926

-Function::get_or_make_decl(Gogo* gogo, Named_object* no, tree id)

39927

+Bfunction*

39928

+Function_declaration::get_or_make_decl(Gogo* gogo, Named_object* no)

39929

{

39930

- if (this->fndecl_ == NULL_TREE)

39931

+ if (this->fndecl_ == NULL)

39932

{

39933

- tree functype = type_to_tree(this->type_->get_backend(gogo));

39934

-

39935

- if (functype != error_mark_node)

39936

- {

39937

- // The type of a function comes back as a pointer to a

39938

- // struct whose first field is the function, but we want the

39939

- // real function type for a function declaration.

39940

- go_assert(POINTER_TYPE_P(functype)

39941

- && TREE_CODE(TREE_TYPE(functype)) == RECORD_TYPE);

39942

- functype = TREE_TYPE(TYPE_FIELDS(TREE_TYPE(functype)));

39943

- go_assert(FUNCTION_POINTER_TYPE_P(functype));

39944

- functype = TREE_TYPE(functype);

39945

- }

39946

-

39947

- if (functype == error_mark_node)

39948

- this->fndecl_ = error_mark_node;

39949

- else

39950

- {

39951

- tree decl = build_decl(this->location().gcc_location(), FUNCTION_DECL,

39952

- id, functype);

39953

-

39954

- this->fndecl_ = decl;

39955

-

39956

- if (no->package() != NULL)

39957

- ;

39958

- else if (this->enclosing_ != NULL || Gogo::is_thunk(no))

39959

- ;

39960

- else if (Gogo::unpack_hidden_name(no->name()) == "init"

39961

- && !this->type_->is_method())

39962

- ;

39963

- else if (Gogo::unpack_hidden_name(no->name()) == "main"

39964

- && gogo->is_main_package())

39965

- TREE_PUBLIC(decl) = 1;

39966

- // Methods have to be public even if they are hidden because

39967

- // they can be pulled into type descriptors when using

39968

- // anonymous fields.

39969

- else if (!Gogo::is_hidden_name(no->name())

39970

- || this->type_->is_method())

39971

- {

39972

- TREE_PUBLIC(decl) = 1;

39973

- std::string pkgpath = gogo->pkgpath_symbol();

39974

- if (this->type_->is_method()

39975

- && Gogo::is_hidden_name(no->name())

39976

- && Gogo::hidden_name_pkgpath(no->name()) != gogo->pkgpath())

39977

- {

39978

- // This is a method we created for an unexported

39979

- // method of an imported embedded type. We need to

39980

- // use the pkgpath of the imported package to avoid

39981

- // a possible name collision. See bug478 for a test

39982

- // case.

39983

- pkgpath = Gogo::hidden_name_pkgpath(no->name());

39984

- pkgpath = Gogo::pkgpath_for_symbol(pkgpath);

39985

- }

39986

-

39987

- std::string asm_name = pkgpath;

39988

- asm_name.append(1, '.');

39989

- asm_name.append(Gogo::unpack_hidden_name(no->name()));

39990

- if (this->type_->is_method())

39991

- {

39992

- asm_name.append(1, '.');

39993

- Type* rtype = this->type_->receiver()->type();

39994

- asm_name.append(rtype->mangled_name(gogo));

39995

- }

39996

- SET_DECL_ASSEMBLER_NAME(decl,

39997

- get_identifier_from_string(asm_name));

39998

- }

39999

-

40000

- // Why do we have to do this in the frontend?

40001

- tree restype = TREE_TYPE(functype);

40002

- tree resdecl =

40003

- build_decl(this->location().gcc_location(), RESULT_DECL, NULL_TREE,

40004

- restype);

40005

- DECL_ARTIFICIAL(resdecl) = 1;

40006

- DECL_IGNORED_P(resdecl) = 1;

40007

- DECL_CONTEXT(resdecl) = decl;

40008

- DECL_RESULT(decl) = resdecl;

40009

-

40010

- // If a function calls the predeclared recover function, we

40011

- // can't inline it, because recover behaves differently in a

40012

- // function passed directly to defer. If this is a recover

40013

- // thunk that we built to test whether a function can be

40014

- // recovered, we can't inline it, because that will mess up

40015

- // our return address comparison.

40016

- if (this->calls_recover_ || this->is_recover_thunk_)

40017

- DECL_UNINLINABLE(decl) = 1;

40018

-

40019

- // If this is a thunk created to call a function which calls

40020

- // the predeclared recover function, we need to disable

40021

- // stack splitting for the thunk.

40022

- if (this->is_recover_thunk_)

40023

- {

40024

- tree attr = get_identifier("__no_split_stack__");

40025

- DECL_ATTRIBUTES(decl) = tree_cons(attr, NULL_TREE, NULL_TREE);

40026

- }

40027

-

40028

- if (this->in_unique_section_)

40029

- resolve_unique_section (decl, 0, 1);

40030

-

40031

- go_preserve_from_gc(decl);

40032

- }

40033

- }

40034

- return this->fndecl_;

40035

-}

40036

-

40037

-// Get a tree for a function declaration.

40038

-

40039

-tree

40040

-Function_declaration::get_or_make_decl(Gogo* gogo, Named_object* no, tree id)

40041

-{

40042

- if (this->fndecl_ == NULL_TREE)

40043

- {

40044

// Let Go code use an asm declaration to pick up a builtin

40045

// function.

40046

if (!this->asm_name_.empty())

40047

@@ -1412,58 +1229,46 @@

40048

builtin_functions.find(this->asm_name_);

40049

if (p != builtin_functions.end())

40050

{

40051

- this->fndecl_ = p->second;

40052

+ this->fndecl_ = tree_to_function(p->second);

40053

return this->fndecl_;

40054

}

40055

}

40056

40057

- tree functype = type_to_tree(this->fntype_->get_backend(gogo));

40058

+ std::string asm_name;

40059

+ if (this->asm_name_.empty())

40060

+ {

40061

+ asm_name = (no->package() == NULL

40062

+ ? gogo->pkgpath_symbol()

40063

+ : no->package()->pkgpath_symbol());

40064

+ asm_name.append(1, '.');

40065

+ asm_name.append(Gogo::unpack_hidden_name(no->name()));

40066

+ if (this->fntype_->is_method())

40067

+ {

40068

+ asm_name.append(1, '.');

40069

+ Type* rtype = this->fntype_->receiver()->type();

40070

+ asm_name.append(rtype->mangled_name(gogo));

40071

+ }

40072

+ }

40073

40074

- if (functype != error_mark_node)

40075

- {

40076

- // The type of a function comes back as a pointer to a

40077

- // struct whose first field is the function, but we want the

40078

- // real function type for a function declaration.

40079

- go_assert(POINTER_TYPE_P(functype)

40080

- && TREE_CODE(TREE_TYPE(functype)) == RECORD_TYPE);

40081

- functype = TREE_TYPE(TYPE_FIELDS(TREE_TYPE(functype)));

40082

- go_assert(FUNCTION_POINTER_TYPE_P(functype));

40083

- functype = TREE_TYPE(functype);

40084

- }

40085

+ Btype* functype = this->fntype_->get_backend_fntype(gogo);

40086

+ this->fndecl_ =

40087

+ gogo->backend()->function(functype, no->get_id(gogo), asm_name,

40088

+ true, true, true, false, false,

40089

+ this->location());

40090

+ }

40091

40092

- tree decl;

40093

- if (functype == error_mark_node)

40094

- decl = error_mark_node;

40095

- else

40096

- {

40097

- decl = build_decl(this->location().gcc_location(), FUNCTION_DECL, id,

40098

- functype);

40099

- TREE_PUBLIC(decl) = 1;

40100

- DECL_EXTERNAL(decl) = 1;

40101

-

40102

- if (this->asm_name_.empty())

40103

- {

40104

- std::string asm_name = (no->package() == NULL

40105

- ? gogo->pkgpath_symbol()

40106

- : no->package()->pkgpath_symbol());

40107

- asm_name.append(1, '.');

40108

- asm_name.append(Gogo::unpack_hidden_name(no->name()));

40109

- if (this->fntype_->is_method())

40110

- {

40111

- asm_name.append(1, '.');

40112

- Type* rtype = this->fntype_->receiver()->type();

40113

- asm_name.append(rtype->mangled_name(gogo));

40114

- }

40115

- SET_DECL_ASSEMBLER_NAME(decl,

40116

- get_identifier_from_string(asm_name));

40117

- }

40118

- }

40119

- this->fndecl_ = decl;

40120

- go_preserve_from_gc(decl);

40121

- }

40122

return this->fndecl_;

40123

}

40124

40125

+// Return the function's decl after it has been built.

40126

+

40127

+tree

40128

+Function::get_decl() const

40129

+{

40130

+ go_assert(this->fndecl_ != NULL);

40131

+ return function_to_tree(this->fndecl_);

40132

+}

40133

+

40134

// We always pass the receiver to a method as a pointer. If the

40135

// receiver is actually declared as a non-pointer type, then we copy

40136

// the value into a local variable, so that it has the right type. In

40137

@@ -1558,7 +1363,7 @@

40138

void

40139

Function::build_tree(Gogo* gogo, Named_object* named_function)

40140

{

40141

- tree fndecl = this->fndecl_;

40142

+ tree fndecl = this->get_decl();

40143

go_assert(fndecl != NULL_TREE);

40144

40145

tree params = NULL_TREE;

40146

@@ -1796,7 +1601,7 @@

40147

set = NULL_TREE;

40148

else

40149

set = fold_build2_loc(end_loc.gcc_location(), MODIFY_EXPR, void_type_node,

40150

- DECL_RESULT(this->fndecl_), retval);

40151

+ DECL_RESULT(this->get_decl()), retval);

40152

tree ret_stmt = fold_build1_loc(end_loc.gcc_location(), RETURN_EXPR,

40153

void_type_node, set);

40154

append_to_statement_list(ret_stmt, &stmt_list);

40155

@@ -1851,7 +1656,7 @@

40156

retval = this->return_value(gogo, named_function, end_loc,

40157

&stmt_list);

40158

set = fold_build2_loc(end_loc.gcc_location(), MODIFY_EXPR, void_type_node,

40159

- DECL_RESULT(this->fndecl_), retval);

40160

+ DECL_RESULT(this->get_decl()), retval);

40161

ret_stmt = fold_build1_loc(end_loc.gcc_location(), RETURN_EXPR,

40162

void_type_node, set);

40163

40164

@@ -1869,7 +1674,7 @@

40165

*fini = stmt_list;

40166

}

40167

40168

-// Return the value to assign to DECL_RESULT(this->fndecl_). This may

40169

+// Return the value to assign to DECL_RESULT(this->get_decl()). This may

40170

// also add statements to STMT_LIST, which need to be executed before

40171

// the assignment. This is used for a return statement with no

40172

// explicit values.

40173

@@ -1902,7 +1707,7 @@

40174

}

40175

else

40176

{

40177

- tree rettype = TREE_TYPE(DECL_RESULT(this->fndecl_));

40178

+ tree rettype = TREE_TYPE(DECL_RESULT(this->get_decl()));

40179

retval = create_tmp_var(rettype, "RESULT");

40180

tree field = TYPE_FIELDS(rettype);

40181

int index = 0;

40182

@@ -2323,18 +2128,14 @@

40183

go_assert(m != NULL);

40184

40185

Named_object* no = m->named_object();

40186

-

40187

- tree fnid = no->get_id(this);

40188

-

40189

- tree fndecl;

40190

+ Bfunction* bf;

40191

if (no->is_function())

40192

- fndecl = no->func_value()->get_or_make_decl(this, no, fnid);

40193

+ bf = no->func_value()->get_or_make_decl(this, no);

40194

else if (no->is_function_declaration())

40195

- fndecl = no->func_declaration_value()->get_or_make_decl(this, no,

40196

- fnid);

40197

+ bf = no->func_declaration_value()->get_or_make_decl(this, no);

40198

else

40199

go_unreachable();

40200

- fndecl = build_fold_addr_expr(fndecl);

40201

+ tree fndecl = build_fold_addr_expr(function_to_tree(bf));

40202

40203

elt = pointers->quick_push(empty);

40204

elt->index = size_int(i);

40205

@@ -2353,10 +2154,11 @@

40206

TREE_CONSTANT(decl) = 1;

40207

DECL_INITIAL(decl) = constructor;

40208

40209

- // If the interface type has hidden methods, then this is the only

40210

- // definition of the table. Otherwise it is a comdat table which

40211

- // may be defined in multiple packages.

40212

- if (has_hidden_methods)

40213

+ // If the interface type has hidden methods, and the table is for a

40214

+ // named type, then this is the only definition of the table.

40215

+ // Otherwise it is a comdat table which may be defined in multiple

40216

+ // packages.

40217

+ if (has_hidden_methods && type->named_type() != NULL)

40218

TREE_PUBLIC(decl) = 1;

40219

else

40220

{

40221

Index: gcc/go/gofrontend/lex.cc

40222

===================================================================

40223

--- a/src/gcc/go/gofrontend/lex.cc (.../tags/gcc_4_8_2_release)

40224

+++ b/src/gcc/go/gofrontend/lex.cc (.../branches/gcc-4_8-branch)

40225

@@ -873,7 +873,28 @@

40226

&& (cc < 'a' || cc > 'z')

40227

&& cc != '_'

40228

&& (cc < '0' || cc > '9'))

40229

- break;

40230

+ {

40231

+ // Check for an invalid character here, as we get better

40232

+ // error behaviour if we swallow them as part of the

40233

+ // identifier we are building.

40234

+ if ((cc >= ' ' && cc < 0x7f)

40235

+ || cc == '\t'

40236

+ || cc == '\r'

40237

+ || cc == '\n')

40238

+ break;

40239

+

40240

+ this->lineoff_ = p - this->linebuf_;

40241

+ error_at(this->location(),

40242

+ "invalid character 0x%x in identifier",

40243

+ cc);

40244

+ if (!has_non_ascii_char)

40245

+ {

40246

+ buf.assign(pstart, p - pstart);

40247

+ has_non_ascii_char = true;

40248

+ }

40249

+ if (!Lex::is_invalid_identifier(buf))

40250

+ buf.append("$INVALID$");

40251

+ }

40252

++p;

40253

if (is_first)

40254

{

40255

Index: gcc/go/gofrontend/backend.h

40256

===================================================================

40257

--- a/src/gcc/go/gofrontend/backend.h (.../tags/gcc_4_8_2_release)

40258

+++ b/src/gcc/go/gofrontend/backend.h (.../branches/gcc-4_8-branch)

40259

@@ -23,7 +23,7 @@

40260

// The backend representation of a statement.

40261

class Bstatement;

40262

40263

-// The backend representation of a function definition.

40264

+// The backend representation of a function definition or declaration.

40265

class Bfunction;

40266

40267

// The backend representation of a block.

40268

@@ -266,6 +266,11 @@

40269

virtual Bexpression*

40270

convert_expression(Btype* type, Bexpression* expr, Location) = 0;

40271

40272

+ // Create an expression for the address of a function. This is used to

40273

+ // get the address of the code for a function.

40274

+ virtual Bexpression*

40275

+ function_code_expression(Bfunction*, Location) = 0;

40276

+

40277

// Statements.

40278

40279

// Create an error statement. This is used for cases which should

40280

@@ -498,6 +503,32 @@

40281

// recover.

40282

virtual Bexpression*

40283

label_address(Blabel*, Location) = 0;

40284

+

40285

+ // Functions.

40286

+

40287

+ // Create an error function. This is used for cases which should

40288

+ // not occur in a correct program, in order to keep the compilation

40289

+ // going without crashing.

40290

+ virtual Bfunction*

40291

+ error_function() = 0;

40292

+

40293

+ // Declare or define a function of FNTYPE.

40294

+ // NAME is the Go name of the function. ASM_NAME, if not the empty string, is

40295

+ // the name that should be used in the symbol table; this will be non-empty if

40296

+ // a magic extern comment is used.

40297

+ // IS_VISIBLE is true if this function should be visible outside of the

40298

+ // current compilation unit. IS_DECLARATION is true if this is a function

40299

+ // declaration rather than a definition; the function definition will be in

40300

+ // another compilation unit.

40301

+ // IS_INLINABLE is true if the function can be inlined.

40302

+ // DISABLE_SPLIT_STACK is true if this function may not split the stack; this

40303

+ // is used for the implementation of recover.

40304

+ // IN_UNIQUE_SECTION is true if this function should be put into a unique

40305

+ // location if possible; this is used for field tracking.

40306

+ virtual Bfunction*

40307

+ function(Btype* fntype, const std::string& name, const std::string& asm_name,

40308

+ bool is_visible, bool is_declaration, bool is_inlinable,

40309

+ bool disable_split_stack, bool in_unique_section, Location) = 0;

40310

};

40311

40312

// The backend interface has to define this function.

40313

@@ -517,5 +548,6 @@

40314

extern tree stat_to_tree(Bstatement*);

40315

extern tree block_to_tree(Bblock*);

40316

extern tree var_to_tree(Bvariable*);

40317

+extern tree function_to_tree(Bfunction*);

40318

40319

#endif // !defined(GO_BACKEND_H)

40320

Index: gcc/go/gofrontend/types.cc

40321

===================================================================

40322

--- a/src/gcc/go/gofrontend/types.cc (.../tags/gcc_4_8_2_release)

40323

+++ b/src/gcc/go/gofrontend/types.cc (.../branches/gcc-4_8-branch)

40324

@@ -1834,7 +1834,9 @@

40325

bloc);

40326

gogo->start_block(bloc);

40327

40328

- if (this->struct_type() != NULL)

40329

+ if (name != NULL && name->real_type()->named_type() != NULL)

40330

+ this->write_named_hash(gogo, name, hash_fntype, equal_fntype);

40331

+ else if (this->struct_type() != NULL)

40332

this->struct_type()->write_hash_function(gogo, name, hash_fntype,

40333

equal_fntype);

40334

else if (this->array_type() != NULL)

40335

@@ -1852,7 +1854,9 @@

40336

false, bloc);

40337

gogo->start_block(bloc);

40338

40339

- if (this->struct_type() != NULL)

40340

+ if (name != NULL && name->real_type()->named_type() != NULL)

40341

+ this->write_named_equal(gogo, name);

40342

+ else if (this->struct_type() != NULL)

40343

this->struct_type()->write_equal_function(gogo, name);

40344

else if (this->array_type() != NULL)

40345

this->array_type()->write_equal_function(gogo, name);

40346

@@ -1865,6 +1869,100 @@

40347

gogo->finish_function(bloc);

40348

}

40349

40350

+// Write a hash function that simply calls the hash function for a

40351

+// named type. This is used when one named type is defined as

40352

+// another. This ensures that this case works when the other named

40353

+// type is defined in another package and relies on calling hash

40354

+// functions defined only in that package.

40355

+

40356

+void

40357

+Type::write_named_hash(Gogo* gogo, Named_type* name,

40358

+ Function_type* hash_fntype, Function_type* equal_fntype)

40359

+{

40360

+ Location bloc = Linemap::predeclared_location();

40361

+

40362

+ Named_type* base_type = name->real_type()->named_type();

40363

+ go_assert(base_type != NULL);

40364

+

40365

+ // The pointer to the type we are going to hash. This is an

40366

+ // unsafe.Pointer.

40367

+ Named_object* key_arg = gogo->lookup("key", NULL);

40368

+ go_assert(key_arg != NULL);

40369

+

40370

+ // The size of the type we are going to hash.

40371

+ Named_object* keysz_arg = gogo->lookup("key_size", NULL);

40372

+ go_assert(keysz_arg != NULL);

40373

+

40374

+ Named_object* hash_fn;

40375

+ Named_object* equal_fn;

40376

+ name->real_type()->type_functions(gogo, base_type, hash_fntype, equal_fntype,

40377

+ &hash_fn, &equal_fn);

40378

+

40379

+ // Call the hash function for the base type.

40380

+ Expression* key_ref = Expression::make_var_reference(key_arg, bloc);

40381

+ Expression* keysz_ref = Expression::make_var_reference(keysz_arg, bloc);

40382

+ Expression_list* args = new Expression_list();

40383

+ args->push_back(key_ref);

40384

+ args->push_back(keysz_ref);

40385

+ Expression* func = Expression::make_func_reference(hash_fn, NULL, bloc);

40386

+ Expression* call = Expression::make_call(func, args, false, bloc);

40387

+

40388

+ // Return the hash of the base type.

40389

+ Expression_list* vals = new Expression_list();

40390

+ vals->push_back(call);

40391

+ Statement* s = Statement::make_return_statement(vals, bloc);

40392

+ gogo->add_statement(s);

40393

+}

40394

+

40395

+// Write an equality function that simply calls the equality function

40396

+// for a named type. This is used when one named type is defined as

40397

+// another. This ensures that this case works when the other named

40398

+// type is defined in another package and relies on calling equality

40399

+// functions defined only in that package.

40400

+

40401

+void

40402

+Type::write_named_equal(Gogo* gogo, Named_type* name)

40403

+{

40404

+ Location bloc = Linemap::predeclared_location();

40405

+

40406

+ // The pointers to the types we are going to compare. These have

40407

+ // type unsafe.Pointer.

40408

+ Named_object* key1_arg = gogo->lookup("key1", NULL);

40409

+ Named_object* key2_arg = gogo->lookup("key2", NULL);

40410

+ go_assert(key1_arg != NULL && key2_arg != NULL);

40411

+

40412

+ Named_type* base_type = name->real_type()->named_type();

40413

+ go_assert(base_type != NULL);

40414

+

40415

+ // Build temporaries with the base type.

40416

+ Type* pt = Type::make_pointer_type(base_type);

40417

+

40418

+ Expression* ref = Expression::make_var_reference(key1_arg, bloc);

40419

+ ref = Expression::make_cast(pt, ref, bloc);

40420

+ Temporary_statement* p1 = Statement::make_temporary(pt, ref, bloc);

40421

+ gogo->add_statement(p1);

40422

+

40423

+ ref = Expression::make_var_reference(key2_arg, bloc);

40424

+ ref = Expression::make_cast(pt, ref, bloc);

40425

+ Temporary_statement* p2 = Statement::make_temporary(pt, ref, bloc);

40426

+ gogo->add_statement(p2);

40427

+

40428

+ // Compare the values for equality.

40429

+ Expression* t1 = Expression::make_temporary_reference(p1, bloc);

40430

+ t1 = Expression::make_unary(OPERATOR_MULT, t1, bloc);

40431

+

40432

+ Expression* t2 = Expression::make_temporary_reference(p2, bloc);

40433

+ t2 = Expression::make_unary(OPERATOR_MULT, t2, bloc);

40434

+

40435

+ Expression* cond = Expression::make_binary(OPERATOR_EQEQ, t1, t2, bloc);

40436

+

40437

+ // Return the equality comparison.

40438

+ Expression_list* vals = new Expression_list();

40439

+ vals->push_back(cond);

40440

+ Statement* s = Statement::make_return_statement(vals, bloc);

40441

+ gogo->add_statement(s);

40442

+}

40443

+

40444

// Return a composite literal for the type descriptor for a plain type

40445

// of kind RUNTIME_TYPE_KIND named NAME.

40446

40447

@@ -2164,26 +2262,9 @@

40448

40449

++p;

40450

go_assert(p->is_field_name("typ"));

40451

- if (!only_value_methods && m->is_value_method())

40452

- {

40453

- // This is a value method on a pointer type. Change the type of

40454

- // the method to use a pointer receiver. The implementation

40455

- // always uses a pointer receiver anyhow.

40456

- Type* rtype = mtype->receiver()->type();

40457

- Type* prtype = Type::make_pointer_type(rtype);

40458

- Typed_identifier* receiver =

40459

- new Typed_identifier(mtype->receiver()->name(), prtype,

40460

- mtype->receiver()->location());

40461

- mtype = Type::make_function_type(receiver,

40462

- (mtype->parameters() == NULL

40463

- ? NULL

40464

- : mtype->parameters()->copy()),

40465

- (mtype->results() == NULL

40466

- ? NULL

40467

- : mtype->results()->copy()),

40468

- mtype->location());

40469

- }

40470

- vals->push_back(Expression::make_type_descriptor(mtype, bloc));

40471

+ bool want_pointer_receiver = !only_value_methods && m->is_value_method();

40472

+ nonmethod_type = mtype->copy_with_receiver_as_param(want_pointer_receiver);

40473

+ vals->push_back(Expression::make_type_descriptor(nonmethod_type, bloc));

40474

40475

++p;

40476

go_assert(p->is_field_name("tfn"));

40477

@@ -3383,6 +3464,68 @@

40478

// Get the backend representation for a function type.

40479

40480

Btype*

40481

+Function_type::get_backend_fntype(Gogo* gogo)

40482

+{

40483

+ if (this->fnbtype_ == NULL)

40484

+ {

40485

+ Backend::Btyped_identifier breceiver;

40486

+ if (this->receiver_ != NULL)

40487

+ {

40488

+ breceiver.name = Gogo::unpack_hidden_name(this->receiver_->name());

40489

+

40490

+ // We always pass the address of the receiver parameter, in

40491

+ // order to make interface calls work with unknown types.

40492

+ Type* rtype = this->receiver_->type();

40493

+ if (rtype->points_to() == NULL)

40494

+ rtype = Type::make_pointer_type(rtype);

40495

+ breceiver.btype = rtype->get_backend(gogo);

40496

+ breceiver.location = this->receiver_->location();

40497

+ }

40498

+

40499

+ std::vector<Backend::Btyped_identifier> bparameters;

40500

+ if (this->parameters_ != NULL)

40501

+ {

40502

+ bparameters.resize(this->parameters_->size());

40503

+ size_t i = 0;

40504

+ for (Typed_identifier_list::const_iterator p =

40505

+ this->parameters_->begin(); p != this->parameters_->end();

40506

+ ++p, ++i)

40507

+ {

40508

+ bparameters[i].name = Gogo::unpack_hidden_name(p->name());

40509

+ bparameters[i].btype = p->type()->get_backend(gogo);

40510

+ bparameters[i].location = p->location();

40511

+ }

40512

+ go_assert(i == bparameters.size());

40513

+ }

40514

+

40515

+ std::vector<Backend::Btyped_identifier> bresults;

40516

+ if (this->results_ != NULL)

40517

+ {

40518

+ bresults.resize(this->results_->size());

40519

+ size_t i = 0;

40520

+ for (Typed_identifier_list::const_iterator p =

40521

+ this->results_->begin(); p != this->results_->end();

40522

+ ++p, ++i)

40523

+ {

40524

+ bresults[i].name = Gogo::unpack_hidden_name(p->name());

40525

+ bresults[i].btype = p->type()->get_backend(gogo);

40526

+ bresults[i].location = p->location();

40527

+ }

40528

+ go_assert(i == bresults.size());

40529

+ }

40530

+

40531

+ this->fnbtype_ = gogo->backend()->function_type(breceiver, bparameters,

40532

+ bresults,

40533

+ this->location());

40534

+

40535

+ }

40536

+

40537

+ return this->fnbtype_;

40538

+}

40539

+

40540

+// Get the backend representation for a Go function type.

40541

+

40542

+Btype*

40543

Function_type::do_get_backend(Gogo* gogo)

40544

{

40545

// When we do anything with a function value other than call it, it

40546

@@ -3395,57 +3538,9 @@

40547

gogo->backend()->placeholder_struct_type("__go_descriptor", loc);

40548

Btype* ptr_struct_type = gogo->backend()->pointer_type(struct_type);

40549

40550

- Backend::Btyped_identifier breceiver;

40551

- if (this->receiver_ != NULL)

40552

- {

40553

- breceiver.name = Gogo::unpack_hidden_name(this->receiver_->name());

40554

-

40555

- // We always pass the address of the receiver parameter, in

40556

- // order to make interface calls work with unknown types.

40557

- Type* rtype = this->receiver_->type();

40558

- if (rtype->points_to() == NULL)

40559

- rtype = Type::make_pointer_type(rtype);

40560

- breceiver.btype = rtype->get_backend(gogo);

40561

- breceiver.location = this->receiver_->location();

40562

- }

40563

-

40564

- std::vector<Backend::Btyped_identifier> bparameters;

40565

- if (this->parameters_ != NULL)

40566

- {

40567

- bparameters.resize(this->parameters_->size());

40568

- size_t i = 0;

40569

- for (Typed_identifier_list::const_iterator p = this->parameters_->begin();

40570

- p != this->parameters_->end();

40571

- ++p, ++i)

40572

- {

40573

- bparameters[i].name = Gogo::unpack_hidden_name(p->name());

40574

- bparameters[i].btype = p->type()->get_backend(gogo);

40575

- bparameters[i].location = p->location();

40576

- }

40577

- go_assert(i == bparameters.size());

40578

- }

40579

-

40580

- std::vector<Backend::Btyped_identifier> bresults;

40581

- if (this->results_ != NULL)

40582

- {

40583

- bresults.resize(this->results_->size());

40584

- size_t i = 0;

40585

- for (Typed_identifier_list::const_iterator p = this->results_->begin();

40586

- p != this->results_->end();

40587

- ++p, ++i)

40588

- {

40589

- bresults[i].name = Gogo::unpack_hidden_name(p->name());

40590

- bresults[i].btype = p->type()->get_backend(gogo);

40591

- bresults[i].location = p->location();

40592

- }

40593

- go_assert(i == bresults.size());

40594

- }

40595

-

40596

- Btype* fntype = gogo->backend()->function_type(breceiver, bparameters,

40597

- bresults, loc);

40598

std::vector<Backend::Btyped_identifier> fields(1);

40599

fields[0].name = "code";

40600

- fields[0].btype = fntype;

40601

+ fields[0].btype = this->get_backend_fntype(gogo);

40602

fields[0].location = loc;

40603

if (!gogo->backend()->set_placeholder_struct_type(struct_type, fields))

40604

return gogo->backend()->error_type();

40605

@@ -3821,6 +3916,32 @@

40606

return ret;

40607

}

40608

40609

+// Make a copy of a function type with the receiver as the first

40610

+// parameter.

40611

+

40612

+Function_type*

40613

+Function_type::copy_with_receiver_as_param(bool want_pointer_receiver) const

40614

+{

40615

+ go_assert(this->is_method());

40616

+ Typed_identifier_list* new_params = new Typed_identifier_list();

40617

+ Type* rtype = this->receiver_->type();

40618

+ if (want_pointer_receiver)

40619

+ rtype = Type::make_pointer_type(rtype);

40620

+ Typed_identifier receiver(this->receiver_->name(), rtype,

40621

+ this->receiver_->location());

40622

+ new_params->push_back(receiver);

40623

+ const Typed_identifier_list* orig_params = this->parameters_;

40624

+ if (orig_params != NULL && !orig_params->empty())

40625

+ {

40626

+ for (Typed_identifier_list::const_iterator p = orig_params->begin();

40627

+ p != orig_params->end();

40628

+ ++p)

40629

+ new_params->push_back(*p);

40630

+ }

40631

+ return Type::make_function_type(NULL, new_params, this->results_,

40632

+ this->location_);

40633

+}

40634

+

40635

// Make a copy of a function type ignoring any receiver and adding a

40636

// closure parameter.

40637

40638

@@ -4195,7 +4316,8 @@

40639

40640

// This is a horrible hack caused by the fact that we don't pack

40641

// the names of builtin types. FIXME.

40642

- if (nt != NULL

40643

+ if (!this->is_imported_

40644

+ && nt != NULL

40645

&& nt->is_builtin()

40646

&& nt->name() == Gogo::unpack_hidden_name(name))

40647

return true;

40648

@@ -4204,6 +4326,36 @@

40649

}

40650

}

40651

40652

+// Return whether this field is an unexported field named NAME.

40653

+

40654

+bool

40655

+Struct_field::is_unexported_field_name(Gogo* gogo,

40656

+ const std::string& name) const

40657

+{

40658

+ const std::string& field_name(this->field_name());

40659

+ if (Gogo::is_hidden_name(field_name)

40660

+ && name == Gogo::unpack_hidden_name(field_name)

40661

+ && gogo->pack_hidden_name(name, false) != field_name)

40662

+ return true;

40663

+

40664

+ // Check for the name of a builtin type. This is like the test in

40665

+ // is_field_name, only there we return false if this->is_imported_,

40666

+ // and here we return true.

40667

+ if (this->is_imported_ && this->is_anonymous())

40668

+ {

40669

+ Type* t = this->typed_identifier_.type();

40670

+ if (t->points_to() != NULL)

40671

+ t = t->points_to();

40672

+ Named_type* nt = t->named_type();

40673

+ if (nt != NULL

40674

+ && nt->is_builtin()

40675

+ && nt->name() == Gogo::unpack_hidden_name(name))

40676

+ return true;

40677

+ }

40678

+

40679

+ return false;

40680

+}

40681

+

40682

// Return whether this field is an embedded built-in type.

40683

40684

bool

40685

@@ -4264,13 +4416,8 @@

40686

++p)

40687

{

40688

Type* t = p->type();

40689

- if (t->is_undefined())

40690

+ if (p->is_anonymous())

40691

{

40692

- error_at(p->location(), "struct field type is incomplete");

40693

- p->set_type(Type::make_error_type());

40694

- }

40695

- else if (p->is_anonymous())

40696

- {

40697

if (t->named_type() != NULL && t->points_to() != NULL)

40698

{

40699

error_at(p->location(), "embedded type may not be a pointer");

40700

@@ -4641,13 +4788,8 @@

40701

for (Struct_field_list::const_iterator pf = fields->begin();

40702

pf != fields->end();

40703

++pf)

40704

- {

40705

- const std::string& field_name(pf->field_name());

40706

- if (Gogo::is_hidden_name(field_name)

40707

- && name == Gogo::unpack_hidden_name(field_name)

40708

- && gogo->pack_hidden_name(name, false) != field_name)

40709

- return true;

40710

- }

40711

+ if (pf->is_unexported_field_name(gogo, name))

40712

+ return true;

40713

}

40714

return false;

40715

}

40716

@@ -5250,6 +5392,7 @@

40717

Type* ftype = imp->read_type();

40718

40719

Struct_field sf(Typed_identifier(name, ftype, imp->location()));

40720

+ sf.set_is_imported();

40721

40722

if (imp->peek_char() == ' ')

40723

{

40724

@@ -9022,6 +9165,8 @@

40725

fntype->is_varargs(), location);

40726

gogo->finish_function(fntype->location());

40727

40728

+ if (type->named_type() == NULL && stub->is_function())

40729

+ stub->func_value()->set_is_unnamed_type_stub_method();

40730

if (m->nointerface() && stub->is_function())

40731

stub->func_value()->set_nointerface();

40732

}

40733

@@ -9289,7 +9434,9 @@

40734

else

40735

{

40736

bool is_unexported;

40737

- if (!Gogo::is_hidden_name(name))

40738

+ // The test for 'a' and 'z' is to handle builtin names,

40739

+ // which are not hidden.

40740

+ if (!Gogo::is_hidden_name(name) && (name[0] < 'a' || name[0] > 'z'))

40741

is_unexported = false;

40742

else

40743

{

40744

Index: gcc/go/gofrontend/expressions.cc

40745

===================================================================

40746

--- a/src/gcc/go/gofrontend/expressions.cc (.../tags/gcc_4_8_2_release)

40747

+++ b/src/gcc/go/gofrontend/expressions.cc (.../branches/gcc-4_8-branch)

40748

@@ -1219,7 +1219,7 @@

40749

40750

// Get the tree for the code of a function expression.

40751

40752

-tree

40753

+Bexpression*

40754

Func_expression::get_code_pointer(Gogo* gogo, Named_object* no, Location loc)

40755

{

40756

Function_type* fntype;

40757

@@ -1237,25 +1237,18 @@

40758

error_at(loc,

40759

"invalid use of special builtin function %qs; must be called",

40760

no->message_name().c_str());

40761

- return error_mark_node;

40762

+ return gogo->backend()->error_expression();

40763

}

40764

40765

- tree id = no->get_id(gogo);

40766

- if (id == error_mark_node)

40767

- return error_mark_node;

40768

-

40769

- tree fndecl;

40770

+ Bfunction* fndecl;

40771

if (no->is_function())

40772

- fndecl = no->func_value()->get_or_make_decl(gogo, no, id);

40773

+ fndecl = no->func_value()->get_or_make_decl(gogo, no);

40774

else if (no->is_function_declaration())

40775

- fndecl = no->func_declaration_value()->get_or_make_decl(gogo, no, id);

40776

+ fndecl = no->func_declaration_value()->get_or_make_decl(gogo, no);

40777

else

40778

go_unreachable();

40779

40780

- if (fndecl == error_mark_node)

40781

- return error_mark_node;

40782

-

40783

- return build_fold_addr_expr_loc(loc.gcc_location(), fndecl);

40784

+ return gogo->backend()->function_code_expression(fndecl, loc);

40785

}

40786

40787

// Get the tree for a function expression. This is used when we take

40788

@@ -1492,8 +1485,10 @@

40789

tree

40790

Func_code_reference_expression::do_get_tree(Translate_context* context)

40791

{

40792

- return Func_expression::get_code_pointer(context->gogo(), this->function_,

40793

- this->location());

40794

+ Bexpression* ret =

40795

+ Func_expression::get_code_pointer(context->gogo(), this->function_,

40796

+ this->location());

40797

+ return expr_to_tree(ret);

40798

}

40799

40800

// Make a reference to the code of a function.

40801

@@ -3055,8 +3050,7 @@

40802

do_lower(Gogo*, Named_object*, Statement_inserter*, int);

40803

40804

bool

40805

- do_is_constant() const

40806

- { return this->expr_->is_constant(); }

40807

+ do_is_constant() const;

40808

40809

bool

40810

do_numeric_constant_value(Numeric_constant*) const;

40811

@@ -3198,6 +3192,27 @@

40812

return this;

40813

}

40814

40815

+// Return whether a type conversion is a constant.

40816

+

40817

+bool

40818

+Type_conversion_expression::do_is_constant() const

40819

+{

40820

+ if (!this->expr_->is_constant())

40821

+ return false;

40822

+

40823

+ // A conversion to a type that may not be used as a constant is not

40824

+ // a constant. For example, []byte(nil).

40825

+ Type* type = this->type_;

40826

+ if (type->integer_type() == NULL

40827

+ && type->float_type() == NULL

40828

+ && type->complex_type() == NULL

40829

+ && !type->is_boolean_type()

40830

+ && !type->is_string_type())

40831

+ return false;

40832

+

40833

+ return true;

40834

+}

40835

+

40836

// Return the constant numeric value if there is one.

40837

40838

bool

40839

@@ -5586,6 +5601,15 @@

40840

subcontext.type = NULL;

40841

}

40842

40843

+ if (this->op_ == OPERATOR_ANDAND || this->op_ == OPERATOR_OROR)

40844

+ {

40845

+ // For a logical operation, the context does not determine the

40846

+ // types of the operands. The operands must be some boolean

40847

+ // type but if the context has a boolean type they do not

40848

+ // inherit it. See http://golang.org/issue/3924.

40849

+ subcontext.type = NULL;

40850

+ }

40851

+

40852

// Set the context for the left hand operand.

40853

if (is_shift_op)

40854

{

40855

@@ -5967,6 +5991,43 @@

40856

right);

40857

}

40858

40859

+ // For complex division Go wants slightly different results than the

40860

+ // GCC library provides, so we have our own runtime routine.

40861

+ if (this->op_ == OPERATOR_DIV && this->left_->type()->complex_type() != NULL)

40862

+ {

40863

+ const char *name;

40864

+ tree *pdecl;

40865

+ Type* ctype;

40866

+ static tree complex64_div_decl;

40867

+ static tree complex128_div_decl;

40868

+ switch (this->left_->type()->complex_type()->bits())

40869

+ {

40870

+ case 64:

40871

+ name = "__go_complex64_div";

40872

+ pdecl = &complex64_div_decl;

40873

+ ctype = Type::lookup_complex_type("complex64");

40874

+ break;

40875

+ case 128:

40876

+ name = "__go_complex128_div";

40877

+ pdecl = &complex128_div_decl;

40878

+ ctype = Type::lookup_complex_type("complex128");

40879

+ break;

40880

+ default:

40881

+ go_unreachable();

40882

+ }

40883

+ Btype* cbtype = ctype->get_backend(gogo);

40884

+ tree ctype_tree = type_to_tree(cbtype);

40885

+ return Gogo::call_builtin(pdecl,

40886

+ this->location(),

40887

+ name,

40888

+ 2,

40889

+ ctype_tree,

40890

+ ctype_tree,

40891

+ fold_convert_loc(gccloc, ctype_tree, left),

40892

+ type,

40893

+ fold_convert_loc(gccloc, ctype_tree, right));

40894

+ }

40895

+

40896

tree compute_type = excess_precision_type(type);

40897

if (compute_type != NULL_TREE)

40898

{

40899

@@ -7191,6 +7252,15 @@

40900

if (this->code_ == BUILTIN_OFFSETOF)

40901

{

40902

Expression* arg = this->one_arg();

40903

+

40904

+ if (arg->bound_method_expression() != NULL

40905

+ || arg->interface_field_reference_expression() != NULL)

40906

+ {

40907

+ this->report_error(_("invalid use of method value as argument "

40908

+ "of Offsetof"));

40909

+ return this;

40910

+ }

40911

+

40912

Field_reference_expression* farg = arg->field_reference_expression();

40913

while (farg != NULL)

40914

{

40915

@@ -7200,7 +7270,8 @@

40916

// it must not be reached through pointer indirections.

40917

if (farg->expr()->deref() != farg->expr())

40918

{

40919

- this->report_error(_("argument of Offsetof implies indirection of an embedded field"));

40920

+ this->report_error(_("argument of Offsetof implies "

40921

+ "indirection of an embedded field"));

40922

return this;

40923

}

40924

// Go up until we reach the original base.

40925

@@ -7476,7 +7547,7 @@

40926

switch (nc.to_unsigned_long(&v))

40927

{

40928

case Numeric_constant::NC_UL_VALID:

40929

- return true;

40930

+ break;

40931

case Numeric_constant::NC_UL_NOTINT:

40932

error_at(e->location(), "non-integer %s argument to make",

40933

is_length ? "len" : "cap");

40934

@@ -7488,8 +7559,23 @@

40935

case Numeric_constant::NC_UL_BIG:

40936

// We don't want to give a compile-time error for a 64-bit

40937

// value on a 32-bit target.

40938

- return true;

40939

+ break;

40940

}

40941

+

40942

+ mpz_t val;

40943

+ if (!nc.to_int(&val))

40944

+ go_unreachable();

40945

+ int bits = mpz_sizeinbase(val, 2);

40946

+ mpz_clear(val);

40947

+ Type* int_type = Type::lookup_integer_type("int");

40948

+ if (bits >= int_type->integer_type()->bits())

40949

+ {

40950

+ error_at(e->location(), "%s argument too large for make",

40951

+ is_length ? "len" : "cap");

40952

+ return false;

40953

+ }

40954

+

40955

+ return true;

40956

}

40957

40958

if (e->type()->integer_type() != NULL)

40959

@@ -7595,6 +7681,8 @@

40960

bool

40961

Builtin_call_expression::do_is_constant() const

40962

{

40963

+ if (this->is_error_expression())

40964

+ return true;

40965

switch (this->code_)

40966

{

40967

case BUILTIN_LEN:

40968

@@ -9744,15 +9832,9 @@

40969

}

40970

40971

tree fntype_tree = type_to_tree(fntype->get_backend(gogo));

40972

- if (fntype_tree == error_mark_node)

40973

+ tree fnfield_type = type_to_tree(fntype->get_backend_fntype(gogo));

40974

+ if (fntype_tree == error_mark_node || fnfield_type == error_mark_node)

40975

return error_mark_node;

40976

- go_assert(POINTER_TYPE_P(fntype_tree));

40977

- if (TREE_TYPE(fntype_tree) == error_mark_node)

40978

- return error_mark_node;

40979

- go_assert(TREE_CODE(TREE_TYPE(fntype_tree)) == RECORD_TYPE);

40980

- tree fnfield_type = TREE_TYPE(TYPE_FIELDS(TREE_TYPE(fntype_tree)));

40981

- if (fnfield_type == error_mark_node)

40982

- return error_mark_node;

40983

go_assert(FUNCTION_POINTER_TYPE_P(fnfield_type));

40984

tree rettype = TREE_TYPE(TREE_TYPE(fnfield_type));

40985

if (rettype == error_mark_node)

40986

@@ -9763,7 +9845,7 @@

40987

if (func != NULL)

40988

{

40989

Named_object* no = func->named_object();

40990

- fn = Func_expression::get_code_pointer(gogo, no, location);

40991

+ fn = expr_to_tree(Func_expression::get_code_pointer(gogo, no, location));

40992

if (!has_closure)

40993

closure_tree = NULL_TREE;

40994

else

40995

@@ -10817,11 +10899,20 @@

40996

void

40997

String_index_expression::do_check_types(Gogo*)

40998

{

40999

- if (this->start_->type()->integer_type() == NULL)

41000

+ Numeric_constant nc;

41001

+ unsigned long v;

41002

+ if (this->start_->type()->integer_type() == NULL

41003

+ && !this->start_->type()->is_error()

41004

+ && (!this->start_->numeric_constant_value(&nc)

41005

+ || nc.to_unsigned_long(&v) == Numeric_constant::NC_UL_NOTINT))

41006

this->report_error(_("index must be integer"));

41007

if (this->end_ != NULL

41008

&& this->end_->type()->integer_type() == NULL

41009

- && !this->end_->is_nil_expression())

41010

+ && !this->end_->type()->is_error()

41011

+ && !this->end_->is_nil_expression()

41012

+ && !this->end_->is_error_expression()

41013

+ && (!this->end_->numeric_constant_value(&nc)

41014

+ || nc.to_unsigned_long(&v) == Numeric_constant::NC_UL_NOTINT))

41015

this->report_error(_("slice end must be integer"));

41016

41017

std::string sval;

41018

Index: gcc/opts.c

41019

===================================================================

41020

--- a/src/gcc/opts.c (.../tags/gcc_4_8_2_release)

41021

+++ b/src/gcc/opts.c (.../branches/gcc-4_8-branch)

41022

@@ -425,8 +425,8 @@

41023

{ OPT_LEVELS_1_PLUS, OPT_fguess_branch_probability, NULL, 1 },

41024

{ OPT_LEVELS_1_PLUS, OPT_fcprop_registers, NULL, 1 },

41025

{ OPT_LEVELS_1_PLUS, OPT_fforward_propagate, NULL, 1 },

41026

- { OPT_LEVELS_1_PLUS, OPT_fif_conversion, NULL, 1 },

41027

- { OPT_LEVELS_1_PLUS, OPT_fif_conversion2, NULL, 1 },

41028

+ { OPT_LEVELS_1_PLUS_NOT_DEBUG, OPT_fif_conversion, NULL, 1 },

41029

+ { OPT_LEVELS_1_PLUS_NOT_DEBUG, OPT_fif_conversion2, NULL, 1 },

41030

{ OPT_LEVELS_1_PLUS, OPT_fipa_pure_const, NULL, 1 },

41031

{ OPT_LEVELS_1_PLUS, OPT_fipa_reference, NULL, 1 },

41032

{ OPT_LEVELS_1_PLUS, OPT_fipa_profile, NULL, 1 },

41033

Index: gcc/recog.c

41034

===================================================================

41035

--- a/src/gcc/recog.c (.../tags/gcc_4_8_2_release)

41036

+++ b/src/gcc/recog.c (.../branches/gcc-4_8-branch)

41037

@@ -3061,6 +3061,9 @@

41038

return 1;

41039

}

41040

41041

+/* Regno offset to be used in the register search. */

41042

+static int search_ofs;

41043

+

41044

/* Try to find a hard register of mode MODE, matching the register class in

41045

CLASS_STR, which is available at the beginning of insn CURRENT_INSN and

41046

remains available until the end of LAST_INSN. LAST_INSN may be NULL_RTX,

41047

@@ -3076,7 +3079,6 @@

41048

peep2_find_free_register (int from, int to, const char *class_str,

41049

enum machine_mode mode, HARD_REG_SET *reg_set)

41050

{

41051

- static int search_ofs;

41052

enum reg_class cl;

41053

HARD_REG_SET live;

41054

df_ref *def_rec;

41055

@@ -3541,6 +3543,7 @@

41056

/* Initialize the regsets we're going to use. */

41057

for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)

41058

peep2_insn_data[i].live_before = BITMAP_ALLOC (&reg_obstack);

41059

+ search_ofs = 0;

41060

live = BITMAP_ALLOC (&reg_obstack);

41061

41062

FOR_EACH_BB_REVERSE (bb)

41063

Index: gcc/ada/system-linux-s390x.ads

41064

===================================================================

41065

--- a/src/gcc/ada/system-linux-s390x.ads (.../tags/gcc_4_8_2_release)

41066

+++ b/src/gcc/ada/system-linux-s390x.ads (.../branches/gcc-4_8-branch)

41067

@@ -7,7 +7,7 @@

41068

-- S p e c --

41069

-- (GNU-Linux/s390x Version) --

41070

-- --

41071

41072

41073

-- --

41074

-- This specification is derived from the Ada Reference Manual for use with --

41075

-- GNAT. The copyright notice above, and the license provisions that follow --

41076

@@ -35,9 +35,10 @@

41077

------------------------------------------------------------------------------

41078

41079

package System is

41080

-pragma Pure (System);

41081

--- Note that we take advantage of the implementation permission to

41082

--- make this unit Pure instead of Preelaborable, see RM 13.7(36)

41083

+ pragma Pure;

41084

+ -- Note that we take advantage of the implementation permission to make

41085

+ -- this unit Pure instead of Preelaborable; see RM 13.7.1(15). In Ada

41086

+ -- 2005, this is Pure in any case (AI-362).

41087

41088

type Name is (SYSTEM_NAME_GNAT);

41089

System_Name : constant Name := SYSTEM_NAME_GNAT;

41090

@@ -61,6 +62,7 @@

41091

-- Storage-related Declarations

41092

41093

type Address is private;

41094

+ pragma Preelaborable_Initialization (Address);

41095

Null_Address : constant Address;

41096

41097

Storage_Unit : constant := 8;

41098

Index: gcc/ada/system-linux-alpha.ads

41099

===================================================================

41100

--- a/src/gcc/ada/system-linux-alpha.ads (.../tags/gcc_4_8_2_release)

41101

+++ b/src/gcc/ada/system-linux-alpha.ads (.../branches/gcc-4_8-branch)

41102

@@ -7,7 +7,7 @@

41103

-- S p e c --

41104

-- (GNU-Linux/alpha Version) --

41105

-- --

41106

41107

41108

-- --

41109

-- This specification is derived from the Ada Reference Manual for use with --

41110

-- GNAT. The copyright notice above, and the license provisions that follow --

41111

@@ -35,9 +35,10 @@

41112

------------------------------------------------------------------------------

41113

41114

package System is

41115

-pragma Pure (System);

41116

--- Note that we take advantage of the implementation permission to

41117

--- make this unit Pure instead of Preelaborable, see RM 13.7(36)

41118

+ pragma Pure;

41119

+ -- Note that we take advantage of the implementation permission to make

41120

+ -- this unit Pure instead of Preelaborable; see RM 13.7.1(15). In Ada

41121

+ -- 2005, this is Pure in any case (AI-362).

41122

41123

type Name is (SYSTEM_NAME_GNAT);

41124

System_Name : constant Name := SYSTEM_NAME_GNAT;

41125

@@ -61,6 +62,7 @@

41126

-- Storage-related Declarations

41127

41128

type Address is private;

41129

+ pragma Preelaborable_Initialization (Address);

41130

Null_Address : constant Address;

41131

41132

Storage_Unit : constant := 8;

41133

Index: gcc/ada/system-vxworks-arm.ads

41134

===================================================================

41135

--- a/src/gcc/ada/system-vxworks-arm.ads (.../tags/gcc_4_8_2_release)

41136

+++ b/src/gcc/ada/system-vxworks-arm.ads (.../branches/gcc-4_8-branch)

41137

@@ -7,7 +7,7 @@

41138

-- S p e c --

41139

-- (VxWorks Version ARM) --

41140

-- --

41141

41142

41143

-- --

41144

-- This specification is derived from the Ada Reference Manual for use with --

41145

-- GNAT. The copyright notice above, and the license provisions that follow --

41146

@@ -35,10 +35,10 @@

41147

------------------------------------------------------------------------------

41148

41149

package System is

41150

-pragma Pure (System);

41151

--- Note that we take advantage of the implementation permission to make this

41152

--- unit Pure instead of Preelaborable; see RM 13.7.1(15). In Ada 2005, this is

41153

--- Pure in any case (AI-362).

41154

+ pragma Pure;

41155

+ -- Note that we take advantage of the implementation permission to make

41156

+ -- this unit Pure instead of Preelaborable; see RM 13.7.1(15). In Ada

41157

+ -- 2005, this is Pure in any case (AI-362).

41158

41159

type Name is (SYSTEM_NAME_GNAT);

41160

System_Name : constant Name := SYSTEM_NAME_GNAT;

41161

Index: gcc/ada/system-linux-s390.ads

41162

===================================================================

41163

--- a/src/gcc/ada/system-linux-s390.ads (.../tags/gcc_4_8_2_release)

41164

+++ b/src/gcc/ada/system-linux-s390.ads (.../branches/gcc-4_8-branch)

41165

@@ -7,7 +7,7 @@

41166

-- S p e c --

41167

-- (GNU-Linux/s390 Version) --

41168

-- --

41169

41170

41171

-- --

41172

-- This specification is derived from the Ada Reference Manual for use with --

41173

-- GNAT. The copyright notice above, and the license provisions that follow --

41174

@@ -35,9 +35,10 @@

41175

------------------------------------------------------------------------------

41176

41177

package System is

41178

-pragma Pure (System);

41179

--- Note that we take advantage of the implementation permission to

41180

--- make this unit Pure instead of Preelaborable, see RM 13.7(36)

41181

+ pragma Pure;

41182

+ -- Note that we take advantage of the implementation permission to make

41183

+ -- this unit Pure instead of Preelaborable; see RM 13.7.1(15). In Ada

41184

+ -- 2005, this is Pure in any case (AI-362).

41185

41186

type Name is (SYSTEM_NAME_GNAT);

41187

System_Name : constant Name := SYSTEM_NAME_GNAT;

41188

@@ -61,6 +62,7 @@

41189

-- Storage-related Declarations

41190

41191

type Address is private;

41192

+ pragma Preelaborable_Initialization (Address);

41193

Null_Address : constant Address;

41194

41195

Storage_Unit : constant := 8;

41196

Index: gcc/ada/indepsw-darwin.adb

41197

===================================================================

41198

--- a/src/gcc/ada/indepsw-darwin.adb (.../tags/gcc_4_8_2_release)

41199

+++ b/src/gcc/ada/indepsw-darwin.adb (.../branches/gcc-4_8-branch)

41200

@@ -0,0 +1,67 @@

41201

+------------------------------------------------------------------------------

41202

+-- --

41203

+-- GNAT COMPILER COMPONENTS --

41204

+-- --

41205

+-- I N D E P S W --

41206

+-- --

41207

+-- B o d y --

41208

+-- (Darwin version) --

41209

+-- --

41210

41211

+-- --

41212

+-- GNAT is free software; you can redistribute it and/or modify it under --

41213

+-- terms of the GNU General Public License as published by the Free Soft- --

41214

+-- ware Foundation; either version 3, or (at your option) any later ver- --

41215

+-- sion. GNAT is distributed in the hope that it will be useful, but WITH- --

41216

+-- OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY --

41217

+-- or FITNESS FOR A PARTICULAR PURPOSE. --

41218

+-- --

41219

+-- As a special exception under Section 7 of GPL version 3, you are granted --

41220

+-- additional permissions described in the GCC Runtime Library Exception, --

41221

+-- version 3.1, as published by the Free Software Foundation. --

41222

+-- --

41223

+-- You should have received a copy of the GNU General Public License and --

41224

+-- a copy of the GCC Runtime Library Exception along with this program; --

41225

+-- see the files COPYING3 and COPYING.RUNTIME respectively. If not, see --

41226

+-- <http://www.gnu.org/licenses/>. --

41227

+-- --

41228

+-- GNAT was originally developed by the GNAT team at New York University. --

41229

+-- Extensive contributions were provided by Ada Core Technologies Inc. --

41230

+-- --

41231

+------------------------------------------------------------------------------

41232

+

41233

+-- This is the Darwin version

41234

+

41235

+package body Indepsw is

41236

+

41237

+ Map_Switch : aliased constant String := "-Wl,-map,";

41238

+

41239

+ -------------

41240

+ -- Convert --

41241

+ -------------

41242

+

41243

+ procedure Convert

41244

+ (Switch : Switch_Kind;

41245

+ Argument : String;

41246

+ To : out String_List_Access)

41247

+ is

41248

+ begin

41249

+ case Switch is

41250

+ when Map_File =>

41251

+ To := new Argument_List'(1 => new String'(Map_Switch & Argument));

41252

+ end case;

41253

+ end Convert;

41254

+

41255

+ ------------------

41256

+ -- Is_Supported --

41257

+ ------------------

41258

+

41259

+ function Is_Supported (Switch : Switch_Kind) return Boolean is

41260

+ begin

41261

+ case Switch is

41262

+ when Map_File =>

41263

+ return True;

41264

+ end case;

41265

+ end Is_Supported;

41266

+

41267

+end Indepsw;

41268

Index: gcc/ada/system-linux-sparcv9.ads

41269

===================================================================

41270

--- a/src/gcc/ada/system-linux-sparcv9.ads (.../tags/gcc_4_8_2_release)

41271

+++ b/src/gcc/ada/system-linux-sparcv9.ads (.../branches/gcc-4_8-branch)

41272

@@ -7,7 +7,7 @@

41273

-- S p e c --

41274

-- (GNU/Linux-SPARCV9 Version) --

41275

-- --

41276

41277

41278

-- --

41279

-- This specification is derived from the Ada Reference Manual for use with --

41280

-- GNAT. The copyright notice above, and the license provisions that follow --

41281

@@ -35,9 +35,10 @@

41282

------------------------------------------------------------------------------

41283

41284

package System is

41285

-pragma Pure (System);

41286

--- Note that we take advantage of the implementation permission to

41287

--- make this unit Pure instead of Preelaborable, see RM 13.7(36)

41288

+ pragma Pure;

41289

+ -- Note that we take advantage of the implementation permission to make

41290

+ -- this unit Pure instead of Preelaborable; see RM 13.7.1(15). In Ada

41291

+ -- 2005, this is Pure in any case (AI-362).

41292

41293

type Name is (SYSTEM_NAME_GNAT);

41294

System_Name : constant Name := SYSTEM_NAME_GNAT;

41295

@@ -61,6 +62,7 @@

41296

-- Storage-related Declarations

41297

41298

type Address is private;

41299

+ pragma Preelaborable_Initialization (Address);

41300

Null_Address : constant Address;

41301

41302

Storage_Unit : constant := 8;

41303

Index: gcc/ada/ChangeLog

41304

===================================================================

41305

--- a/src/gcc/ada/ChangeLog (.../tags/gcc_4_8_2_release)

41306

+++ b/src/gcc/ada/ChangeLog (.../branches/gcc-4_8-branch)

41307

@@ -1,3 +1,60 @@

41308

+2014-03-30 Eric Botcazou <ebotcazou@adacore.com>

41309

+

41310

+ PR ada/60703

41311

+ * system-linux-alpha.ads: Adjust for Ada 2005.

41312

+ * system-linux-mips.ads: Likewise.

41313

+ * system-linux-mips64el.ads: Likewise.

41314

+ * system-linux-mipsel.ads: Likewise.

41315

+ * system-linux-s390.ads: Likewise.

41316

+ * system-linux-s390x.ads: Likewise.

41317

+ * system-linux-sparc.ads: Likewise.

41318

+ * system-linux-sparcv9.ads: Likewise.

41319

+ * system-rtems.ads: Likewise.

41320

+ * system-vxworks-arm.ads: Likewise.

41321

+

41322

+2014-03-13 Eric Botcazou <ebotcazou@adacore.com>

41323

+

41324

+ PR ada/51483

41325

+ * back_end.ads (Register_Type_Proc): Add 'precision' parameter.

41326

+ * cstand.adb (Register_Float_Type): Add 'precision' parameter and use

41327

+ it to set the RM size. Use directly 'size' for the Esize.

41328

+ * gcc-interface/gigi.h (enumerate_modes): Add integer parameter.

41329

+ * gcc-interface/misc.c (enumerate_modes): Likewise. Do not register

41330

+ types for vector modes, pass the size in addition to the precision.

41331

+

41332

+2014-01-12 Eric Botcazou <ebotcazou@adacore.com>

41333

+

41334

+ PR ada/59772

41335

+ * gcc-interface/cuintp.c (build_cst_from_int): Use 32-bit integer type

41336

+ as intermediate type.

41337

+ (UI_To_gnu): Likewise.

41338

+

41339

+2013-12-12 Eric Botcazou <ebotcazou@adacore.com>

41340

+ Iain Sandoe <iain@codesourcery.com>

41341

+

41342

+ PR ada/55946

41343

+ * gcc-interface/Make-lang.in (ada/doctools/xgnatugn): Use gnatmake.

41344

+ * gcc-interface/Makefile.in (GCC_LINK): Add LDFLAGS.

41345

+ (../../gnatmake): Remove LDFLAGS.

41346

+ (../../gnatlink): Likewise.

41347

+

41348

+2013-12-04 Eric Botcazou <ebotcazou@adacore.com>

41349

+

41350

+ PR ada/59382

41351

+ * indepsw-darwin.adb: New file.

41352

+

41353

+2013-10-19 Eric Botcazou <ebotcazou@adacore.com>

41354

+

41355

+ * gcc-interface/utils.c (scale_by_factor_of): New function.

41356

+ (rest_of_record_type_compilation): Use scale_by_factor_of in order to

41357

+ scale the original offset for both rounding cases; in the second case,

41358

+ take into accout the addend to compute the alignment. Tidy up.

41359

+

41360

+2013-10-19 Eric Botcazou <ebotcazou@adacore.com>

41361

+

41362

+ * gcc-interface/utils.c (gnat_set_type_context): New function.

41363

+ (gnat_pushdecl): Use it to set the context of the type.

41364

+

41365

2013-10-16 Release Manager

41366

41367

* GCC 4.8.2 released.

41368

Index: gcc/ada/cstand.adb

41369

===================================================================

41370

--- a/src/gcc/ada/cstand.adb (.../tags/gcc_4_8_2_release)

41371

+++ b/src/gcc/ada/cstand.adb (.../branches/gcc-4_8-branch)

41372

@@ -151,6 +151,7 @@

41373

Complex : Boolean; -- True iff type has real and imaginary parts

41374

Count : Natural; -- Number of elements in vector, 0 otherwise

41375

Float_Rep : Float_Rep_Kind; -- Representation used for fpt type

41376

+ Precision : Positive; -- Precision of representation in bits

41377

Size : Positive; -- Size of representation in bits

41378

Alignment : Natural); -- Required alignment in bits

41379

pragma Convention (C, Register_Float_Type);

41380

@@ -2014,6 +2015,7 @@

41381

Complex : Boolean;

41382

Count : Natural;

41383

Float_Rep : Float_Rep_Kind;

41384

+ Precision : Positive;

41385

Size : Positive;

41386

Alignment : Natural)

41387

is

41388

@@ -2063,14 +2065,25 @@

41389

41390

else

41391

Write_Str ("mod 2**");

41392

- Write_Int (Int (Size / Positive'Max (1, Count)));

41393

+ Write_Int (Int (Precision / Positive'Max (1, Count)));

41394

Write_Line (";");

41395

end if;

41396

41397

- Write_Str ("for " & T & "'Size use ");

41398

- Write_Int (Int (Size));

41399

- Write_Line (";");

41400

+ if Precision = Size then

41401

+ Write_Str ("for " & T (1 .. Last) & "'Size use ");

41402

+ Write_Int (Int (Size));

41403

+ Write_Line (";");

41404

41405

+ else

41406

+ Write_Str ("for " & T (1 .. Last) & "'Value_Size use ");

41407

+ Write_Int (Int (Precision));

41408

+ Write_Line (";");

41409

+

41410

+ Write_Str ("for " & T (1 .. Last) & "'Object_Size use ");

41411

+ Write_Int (Int (Size));

41412

+ Write_Line (";");

41413

+ end if;

41414

+

41415

Write_Str ("for " & T & "'Alignment use ");

41416

Write_Int (Int (Alignment / 8));

41417

Write_Line (";");

41418

@@ -2092,15 +2105,13 @@

41419

if Digs > 0 and then not Complex and then Count = 0 then

41420

declare

41421

Ent : constant Entity_Id := New_Standard_Entity;

41422

- Esize : constant Pos := Pos ((Size + Alignment - 1)

41423

- / Alignment * Alignment);

41424

begin

41425

Set_Defining_Identifier

41426

(New_Node (N_Full_Type_Declaration, Stloc), Ent);

41427

Make_Name (Ent, T (1 .. Last));

41428

Set_Scope (Ent, Standard_Standard);

41429

- Build_Float_Type (Ent, Esize, Float_Rep, Pos (Digs));

41430

- Set_RM_Size (Ent, UI_From_Int (Int (Size)));

41431

+ Build_Float_Type (Ent, Int (Size), Float_Rep, Pos (Digs));

41432

+ Set_RM_Size (Ent, UI_From_Int (Int (Precision)));

41433

Set_Alignment (Ent, UI_From_Int (Int (Alignment / 8)));

41434

41435

if No (Back_End_Float_Types) then

41436

Index: gcc/ada/back_end.ads

41437

===================================================================

41438

--- a/src/gcc/ada/back_end.ads (.../tags/gcc_4_8_2_release)

41439

+++ b/src/gcc/ada/back_end.ads (.../branches/gcc-4_8-branch)

41440

@@ -55,6 +55,7 @@

41441

Complex : Boolean; -- True iff type has real and imaginary parts

41442

Count : Natural; -- Number of elements in vector, 0 otherwise

41443

Float_Rep : Float_Rep_Kind; -- Representation used for fpt type

41444

+ Precision : Positive; -- Precision of representation in bits

41445

Size : Positive; -- Size of representation in bits

41446

Alignment : Natural); -- Required alignment in bits

41447

pragma Convention (C, Register_Type_Proc);

41448

Index: gcc/ada/system-linux-mipsel.ads

41449

===================================================================

41450

--- a/src/gcc/ada/system-linux-mipsel.ads (.../tags/gcc_4_8_2_release)

41451

+++ b/src/gcc/ada/system-linux-mipsel.ads (.../branches/gcc-4_8-branch)

41452

@@ -7,7 +7,7 @@

41453

-- S p e c --

41454

-- (GNU-Linux/MIPSEL Version) --

41455

-- --

41456

41457

41458

-- --

41459

-- This specification is derived from the Ada Reference Manual for use with --

41460

-- GNAT. The copyright notice above, and the license provisions that follow --

41461

@@ -62,6 +62,7 @@

41462

-- Storage-related Declarations

41463

41464

type Address is private;

41465

+ pragma Preelaborable_Initialization (Address);

41466

Null_Address : constant Address;

41467

41468

Storage_Unit : constant := 8;

41469

Index: gcc/ada/system-linux-mips.ads

41470

===================================================================

41471

--- a/src/gcc/ada/system-linux-mips.ads (.../tags/gcc_4_8_2_release)

41472

+++ b/src/gcc/ada/system-linux-mips.ads (.../branches/gcc-4_8-branch)

41473

@@ -7,7 +7,7 @@

41474

-- S p e c --

41475

-- (GNU-Linux/MIPS Version) --

41476

-- --

41477

41478

41479

-- --

41480

-- This specification is derived from the Ada Reference Manual for use with --

41481

-- GNAT. The copyright notice above, and the license provisions that follow --

41482

@@ -62,6 +62,7 @@

41483

-- Storage-related Declarations

41484

41485

type Address is private;

41486

+ pragma Preelaborable_Initialization (Address);

41487

Null_Address : constant Address;

41488

41489

Storage_Unit : constant := 8;

41490

Index: gcc/ada/system-linux-mips64el.ads

41491

===================================================================

41492

--- a/src/gcc/ada/system-linux-mips64el.ads (.../tags/gcc_4_8_2_release)

41493

+++ b/src/gcc/ada/system-linux-mips64el.ads (.../branches/gcc-4_8-branch)

41494

@@ -7,7 +7,7 @@

41495

-- S p e c --

41496

-- (GNU-Linux/MIPS64EL Version) --

41497

-- --

41498

41499

41500

-- --

41501

-- This specification is derived from the Ada Reference Manual for use with --

41502

-- GNAT. The copyright notice above, and the license provisions that follow --

41503

@@ -62,6 +62,7 @@

41504

-- Storage-related Declarations

41505

41506

type Address is private;

41507

+ pragma Preelaborable_Initialization (Address);

41508

Null_Address : constant Address;

41509

41510

Storage_Unit : constant := 8;

41511

Index: gcc/ada/gcc-interface/utils.c

41512

===================================================================

41513

--- a/src/gcc/ada/gcc-interface/utils.c (.../tags/gcc_4_8_2_release)

41514

+++ b/src/gcc/ada/gcc-interface/utils.c (.../branches/gcc-4_8-branch)

41515

@@ -232,6 +232,7 @@

41516

static tree split_plus (tree, tree *);

41517

static tree float_type_for_precision (int, enum machine_mode);

41518

static tree convert_to_fat_pointer (tree, tree);

41519

+static unsigned int scale_by_factor_of (tree, unsigned int);

41520

static bool potential_alignment_gap (tree, tree, tree);

41521

static void process_attributes (tree, struct attrib *);

41522

41523

@@ -532,6 +533,22 @@

41524

free_binding_level = level;

41525

}

41526

41527

+/* Set the context of TYPE and its parallel types (if any) to CONTEXT. */

41528

+

41529

+static void

41530

+gnat_set_type_context (tree type, tree context)

41531

+{

41532

+ tree decl = TYPE_STUB_DECL (type);

41533

+

41534

+ TYPE_CONTEXT (type) = context;

41535

+

41536

+ while (decl && DECL_PARALLEL_TYPE (decl))

41537

+ {

41538

+ TYPE_CONTEXT (DECL_PARALLEL_TYPE (decl)) = context;

41539

+ decl = TYPE_STUB_DECL (DECL_PARALLEL_TYPE (decl));

41540

+ }

41541

+}

41542

+

41543

/* Record DECL as belonging to the current lexical scope and use GNAT_NODE

41544

for location information and flag propagation. */

41545

41546

@@ -613,7 +630,7 @@

41547

if (TREE_CODE (t) == POINTER_TYPE)

41548

TYPE_NEXT_PTR_TO (t) = tt;

41549

TYPE_NAME (tt) = DECL_NAME (decl);

41550

- TYPE_CONTEXT (tt) = DECL_CONTEXT (decl);

41551

+ gnat_set_type_context (tt, DECL_CONTEXT (decl));

41552

TYPE_STUB_DECL (tt) = TYPE_STUB_DECL (t);

41553

DECL_ORIGINAL_TYPE (decl) = tt;

41554

}

41555

@@ -623,7 +640,7 @@

41556

/* We need a variant for the placeholder machinery to work. */

41557

tree tt = build_variant_type_copy (t);

41558

TYPE_NAME (tt) = decl;

41559

- TYPE_CONTEXT (tt) = DECL_CONTEXT (decl);

41560

+ gnat_set_type_context (tt, DECL_CONTEXT (decl));

41561

TREE_USED (tt) = TREE_USED (t);

41562

TREE_TYPE (decl) = tt;

41563

if (DECL_ORIGINAL_TYPE (TYPE_NAME (t)))

41564

@@ -645,7 +662,7 @@

41565

if (!(TYPE_NAME (t) && TREE_CODE (TYPE_NAME (t)) == TYPE_DECL))

41566

{

41567

TYPE_NAME (t) = decl;

41568

- TYPE_CONTEXT (t) = DECL_CONTEXT (decl);

41569

+ gnat_set_type_context (t, DECL_CONTEXT (decl));

41570

}

41571

}

41572

}

41573

@@ -1692,93 +1709,74 @@

41574

TYPE_SIZE_UNIT (new_record_type)

41575

= size_int (TYPE_ALIGN (record_type) / BITS_PER_UNIT);

41576

41577

- /* Now scan all the fields, replacing each field with a new

41578

- field corresponding to the new encoding. */

41579

+ /* Now scan all the fields, replacing each field with a new field

41580

+ corresponding to the new encoding. */

41581

for (old_field = TYPE_FIELDS (record_type); old_field;

41582

old_field = DECL_CHAIN (old_field))

41583

{

41584

tree field_type = TREE_TYPE (old_field);

41585

tree field_name = DECL_NAME (old_field);

41586

- tree new_field;

41587

tree curpos = bit_position (old_field);

41588

+ tree pos, new_field;

41589

bool var = false;

41590

unsigned int align = 0;

41591

- tree pos;

41592

41593

+ /* We're going to do some pattern matching below so remove as many

41594

+ conversions as possible. */

41595

+ curpos = remove_conversions (curpos, true);

41596

+

41597

/* See how the position was modified from the last position.

41598

41599

- There are two basic cases we support: a value was added

41600

- to the last position or the last position was rounded to

41601

- a boundary and they something was added. Check for the

41602

- first case first. If not, see if there is any evidence

41603

- of rounding. If so, round the last position and try

41604

- again.

41605

+ There are two basic cases we support: a value was added

41606

+ to the last position or the last position was rounded to

41607

+ a boundary and they something was added. Check for the

41608

+ first case first. If not, see if there is any evidence

41609

+ of rounding. If so, round the last position and retry.

41610

41611

- If this is a union, the position can be taken as zero. */

41612

-

41613

- /* Some computations depend on the shape of the position expression,

41614

- so strip conversions to make sure it's exposed. */

41615

- curpos = remove_conversions (curpos, true);

41616

-

41617

+ If this is a union, the position can be taken as zero. */

41618

if (TREE_CODE (new_record_type) == UNION_TYPE)

41619

- pos = bitsize_zero_node, align = 0;

41620

+ pos = bitsize_zero_node;

41621

else

41622

pos = compute_related_constant (curpos, last_pos);

41623

41624

- if (!pos && TREE_CODE (curpos) == MULT_EXPR

41625

+ if (!pos

41626

+ && TREE_CODE (curpos) == MULT_EXPR

41627

&& host_integerp (TREE_OPERAND (curpos, 1), 1))

41628

{

41629

tree offset = TREE_OPERAND (curpos, 0);

41630

align = tree_low_cst (TREE_OPERAND (curpos, 1), 1);

41631

-

41632

- /* An offset which is a bitwise AND with a mask increases the

41633

- alignment according to the number of trailing zeros. */

41634

- offset = remove_conversions (offset, true);

41635

- if (TREE_CODE (offset) == BIT_AND_EXPR

41636

- && TREE_CODE (TREE_OPERAND (offset, 1)) == INTEGER_CST)

41637

- {

41638

- unsigned HOST_WIDE_INT mask

41639

- = TREE_INT_CST_LOW (TREE_OPERAND (offset, 1));

41640

- unsigned int i;

41641

-

41642

- for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)

41643

- {

41644

- if (mask & 1)

41645

- break;

41646

- mask >>= 1;

41647

- align *= 2;

41648

- }

41649

- }

41650

-

41651

- pos = compute_related_constant (curpos,

41652

- round_up (last_pos, align));

41653

+ align = scale_by_factor_of (offset, align);

41654

+ last_pos = round_up (last_pos, align);

41655

+ pos = compute_related_constant (curpos, last_pos);

41656

}

41657

- else if (!pos && TREE_CODE (curpos) == PLUS_EXPR

41658

- && TREE_CODE (TREE_OPERAND (curpos, 1)) == INTEGER_CST

41659

+ else if (!pos

41660

+ && TREE_CODE (curpos) == PLUS_EXPR

41661

+ && host_integerp (TREE_OPERAND (curpos, 1), 1)

41662

&& TREE_CODE (TREE_OPERAND (curpos, 0)) == MULT_EXPR

41663

- && host_integerp (TREE_OPERAND

41664

- (TREE_OPERAND (curpos, 0), 1),

41665

- 1))

41666

+ && host_integerp

41667

+ (TREE_OPERAND (TREE_OPERAND (curpos, 0), 1), 1))

41668

{

41669

+ tree offset = TREE_OPERAND (TREE_OPERAND (curpos, 0), 0);

41670

+ unsigned HOST_WIDE_INT addend

41671

+ = tree_low_cst (TREE_OPERAND (curpos, 1), 1);

41672

align

41673

- = tree_low_cst

41674

- (TREE_OPERAND (TREE_OPERAND (curpos, 0), 1), 1);

41675

- pos = compute_related_constant (curpos,

41676

- round_up (last_pos, align));

41677

+ = tree_low_cst (TREE_OPERAND (TREE_OPERAND (curpos, 0), 1), 1);

41678

+ align = scale_by_factor_of (offset, align);

41679

+ align = MIN (align, addend & -addend);

41680

+ last_pos = round_up (last_pos, align);

41681

+ pos = compute_related_constant (curpos, last_pos);

41682

}

41683

- else if (potential_alignment_gap (prev_old_field, old_field,

41684

- pos))

41685

+ else if (potential_alignment_gap (prev_old_field, old_field, pos))

41686

{

41687

align = TYPE_ALIGN (field_type);

41688

- pos = compute_related_constant (curpos,

41689

- round_up (last_pos, align));

41690

+ last_pos = round_up (last_pos, align);

41691

+ pos = compute_related_constant (curpos, last_pos);

41692

}

41693

41694

/* If we can't compute a position, set it to zero.

41695

41696

- ??? We really should abort here, but it's too much work

41697

- to get this correct for all cases. */

41698

-

41699

+ ??? We really should abort here, but it's too much work

41700

+ to get this correct for all cases. */

41701

if (!pos)

41702

pos = bitsize_zero_node;

41703

41704

@@ -2553,6 +2551,32 @@

41705

return false;

41706

}

41707

41708

+/* Return VALUE scaled by the biggest power-of-2 factor of EXPR. */

41709

+

41710

+static unsigned int

41711

+scale_by_factor_of (tree expr, unsigned int value)

41712

+{

41713

+ expr = remove_conversions (expr, true);

41714

+

41715

+ /* An expression which is a bitwise AND with a mask has a power-of-2 factor

41716

+ corresponding to the number of trailing zeros of the mask. */

41717

+ if (TREE_CODE (expr) == BIT_AND_EXPR

41718

+ && TREE_CODE (TREE_OPERAND (expr, 1)) == INTEGER_CST)

41719

+ {

41720

+ unsigned HOST_WIDE_INT mask = TREE_INT_CST_LOW (TREE_OPERAND (expr, 1));

41721

+ unsigned int i = 0;

41722

+

41723

+ while ((mask & 1) == 0 && i < HOST_BITS_PER_WIDE_INT)

41724

+ {

41725

+ mask >>= 1;

41726

+ value *= 2;

41727

+ i++;

41728

+ }

41729

+ }

41730

+

41731

+ return value;

41732

+}

41733

+

41734

/* Given two consecutive field decls PREV_FIELD and CURR_FIELD, return true

41735

unless we can prove these 2 fields are laid out in such a way that no gap

41736

exist between the end of PREV_FIELD and the beginning of CURR_FIELD. OFFSET

41737

Index: gcc/ada/gcc-interface/Makefile.in

41738

===================================================================

41739

--- a/src/gcc/ada/gcc-interface/Makefile.in (.../tags/gcc_4_8_2_release)

41740

+++ b/src/gcc/ada/gcc-interface/Makefile.in (.../branches/gcc-4_8-branch)

41741

@@ -2397,7 +2397,7 @@

41742

"GNATLINK=$(GNATLINK)" \

41743

"GNATBIND=$(GNATBIND)"

41744

41745

-GCC_LINK=$(CC) $(GCC_LINK_FLAGS) $(ADA_INCLUDES)

41746

+GCC_LINK=$(CC) $(GCC_LINK_FLAGS) $(ADA_INCLUDES) $(LDFLAGS)

41747

41748

# Build directory for the tools. Let's copy the target-dependent

41749

# sources using the same mechanism as for gnatlib. The other sources are

41750

@@ -2519,12 +2519,10 @@

41751

41752

# Likewise for the tools

41753

../../gnatmake$(exeext): $(P) b_gnatm.o link.o targext.o $(GNATMAKE_OBJS)

41754

- $(GCC_LINK) $(ALL_CFLAGS) $(LDFLAGS) -o $@ b_gnatm.o $(GNATMAKE_OBJS) \

41755

- $(TOOLS_LIBS)

41756

+ +$(GCC_LINK) $(ALL_CFLAGS) -o $@ b_gnatm.o $(GNATMAKE_OBJS) $(TOOLS_LIBS)

41757

41758

../../gnatlink$(exeext): $(P) b_gnatl.o link.o targext.o $(GNATLINK_OBJS)

41759

- $(GCC_LINK) $(ALL_CFLAGS) $(LDFLAGS) -o $@ b_gnatl.o $(GNATLINK_OBJS) \

41760

- $(TOOLS_LIBS)

41761

+ +$(GCC_LINK) $(ALL_CFLAGS) -o $@ b_gnatl.o $(GNATLINK_OBJS) $(TOOLS_LIBS)

41762

41763

../stamp-gnatlib-$(RTSDIR):

41764

@if [ ! -f stamp-gnatlib-$(RTSDIR) ] ; \

41765

Index: gcc/ada/gcc-interface/cuintp.c

41766

===================================================================

41767

--- a/src/gcc/ada/gcc-interface/cuintp.c (.../tags/gcc_4_8_2_release)

41768

+++ b/src/gcc/ada/gcc-interface/cuintp.c (.../branches/gcc-4_8-branch)

41769

@@ -6,7 +6,7 @@

41770

* *

41771

* C Implementation File *

41772

* *

41773

41774

41775

* *

41776

* GNAT is free software; you can redistribute it and/or modify it under *

41777

* terms of the GNU General Public License as published by the Free Soft- *

41778

@@ -59,8 +59,8 @@

41779

static tree

41780

build_cst_from_int (tree type, HOST_WIDE_INT low)

41781

{

41782

- if (TREE_CODE (type) == REAL_TYPE)

41783

- return convert (type, build_int_cst (NULL_TREE, low));

41784

+ if (SCALAR_FLOAT_TYPE_P (type))

41785

+ return convert (type, build_int_cst (gnat_type_for_size (32, 0), low));

41786

else

41787

return build_int_cst_type (type, low);

41788

}

41789

@@ -99,20 +99,13 @@

41790

gcc_assert (Length > 0);

41791

41792

/* The computations we perform below always require a type at least as

41793

- large as an integer not to overflow. REAL types are always fine, but

41794

+ large as an integer not to overflow. FP types are always fine, but

41795

INTEGER or ENUMERAL types we are handed may be too short. We use a

41796

base integer type node for the computations in this case and will

41797

- convert the final result back to the incoming type later on.

41798

- The base integer precision must be superior than 16. */

41799

+ convert the final result back to the incoming type later on. */

41800

+ if (!SCALAR_FLOAT_TYPE_P (comp_type) && TYPE_PRECISION (comp_type) < 32)

41801

+ comp_type = gnat_type_for_size (32, 0);

41802

41803

- if (TREE_CODE (comp_type) != REAL_TYPE

41804

- && TYPE_PRECISION (comp_type)

41805

- < TYPE_PRECISION (long_integer_type_node))

41806

- {

41807

- comp_type = long_integer_type_node;

41808

- gcc_assert (TYPE_PRECISION (comp_type) > 16);

41809

- }

41810

-

41811

gnu_base = build_cst_from_int (comp_type, Base);

41812

41813

gnu_ret = build_cst_from_int (comp_type, First);

41814

Index: gcc/ada/gcc-interface/Make-lang.in

41815

===================================================================

41816

--- a/src/gcc/ada/gcc-interface/Make-lang.in (.../tags/gcc_4_8_2_release)

41817

+++ b/src/gcc/ada/gcc-interface/Make-lang.in (.../branches/gcc-4_8-branch)

41818

@@ -625,7 +625,7 @@

41819

ada/doctools/xgnatugn$(build_exeext): ada/xgnatugn.adb

41820

-$(MKDIR) ada/doctools

41821

$(CP) $^ ada/doctools

41822

- cd ada/doctools && $(GNATMAKE) -q xgnatugn

41823

+ cd ada/doctools && gnatmake -q xgnatugn

41824

41825

# Note that doc/gnat_ugn.texi and doc/projects.texi do not depend on

41826

# xgnatugn being built so we can distribute a pregenerated doc/gnat_ugn.info

41827

Index: gcc/ada/gcc-interface/gigi.h

41828

===================================================================

41829

--- a/src/gcc/ada/gcc-interface/gigi.h (.../tags/gcc_4_8_2_release)

41830

+++ b/src/gcc/ada/gcc-interface/gigi.h (.../branches/gcc-4_8-branch)

41831

@@ -1014,7 +1014,7 @@

41832

/* This function is called by the front-end to enumerate all the supported

41833

modes for the machine, as well as some predefined C types. */

41834

extern void enumerate_modes (void (*f) (const char *, int, int, int, int, int,

41835

- int));

41836

+ int, int));

41837

41838

#ifdef __cplusplus

41839

}

41840

Index: gcc/ada/gcc-interface/misc.c

41841

===================================================================

41842

--- a/src/gcc/ada/gcc-interface/misc.c (.../tags/gcc_4_8_2_release)

41843

+++ b/src/gcc/ada/gcc-interface/misc.c (.../branches/gcc-4_8-branch)

41844

@@ -648,7 +648,7 @@

41845

/* This function is called by the front-end to enumerate all the supported

41846

modes for the machine, as well as some predefined C types. F is a function

41847

which is called back with the parameters as listed below, first a string,

41848

- then six ints. The name is any arbitrary null-terminated string and has

41849

+ then seven ints. The name is any arbitrary null-terminated string and has

41850

no particular significance, except for the case of predefined C types, where

41851

it should be the name of the C type. For integer types, only signed types

41852

should be listed, unsigned versions are assumed. The order of types should

41853

@@ -664,11 +664,12 @@

41854

COMPLEX_P nonzero is this represents a complex mode

41855

COUNT count of number of items, nonzero for vector mode

41856

FLOAT_REP Float_Rep_Kind for FP, otherwise undefined

41857

- SIZE number of bits used to store data

41858

+ PRECISION number of bits used to store data

41859

+ SIZE number of bits occupied by the mode

41860

ALIGN number of bits to which mode is aligned. */

41861

41862

void

41863

-enumerate_modes (void (*f) (const char *, int, int, int, int, int, int))

41864

+enumerate_modes (void (*f) (const char *, int, int, int, int, int, int, int))

41865

{

41866

const tree c_types[]

41867

= { float_type_node, double_type_node, long_double_type_node };

41868

@@ -742,28 +743,26 @@

41869

41870

/* First register any C types for this mode that the front end

41871

may need to know about, unless the mode should be skipped. */

41872

-

41873

- if (!skip_p)

41874

+ if (!skip_p && !vector_p)

41875

for (nameloop = 0; nameloop < ARRAY_SIZE (c_types); nameloop++)

41876

{

41877

- tree typ = c_types[nameloop];

41878

- const char *nam = c_names[nameloop];

41879

+ tree type = c_types[nameloop];

41880

+ const char *name = c_names[nameloop];

41881

41882

- if (TYPE_MODE (typ) == i)

41883

+ if (TYPE_MODE (type) == i)

41884

{

41885

- f (nam, digs, complex_p,

41886

- vector_p ? GET_MODE_NUNITS (i) : 0, float_rep,

41887

- TYPE_PRECISION (typ), TYPE_ALIGN (typ));

41888

+ f (name, digs, complex_p, 0, float_rep, TYPE_PRECISION (type),

41889

+ TREE_INT_CST_LOW (TYPE_SIZE (type)), TYPE_ALIGN (type));

41890

skip_p = true;

41891

}

41892

}

41893

41894

/* If no predefined C types were found, register the mode itself. */

41895

-

41896

if (!skip_p)

41897

f (GET_MODE_NAME (i), digs, complex_p,

41898

vector_p ? GET_MODE_NUNITS (i) : 0, float_rep,

41899

- GET_MODE_PRECISION (i), GET_MODE_ALIGNMENT (i));

41900

+ GET_MODE_PRECISION (i), GET_MODE_BITSIZE (i),

41901

+ GET_MODE_ALIGNMENT (i));

41902

}

41903

}

41904

41905

Index: gcc/ada/system-linux-sparc.ads

41906

===================================================================

41907

--- a/src/gcc/ada/system-linux-sparc.ads (.../tags/gcc_4_8_2_release)

41908

+++ b/src/gcc/ada/system-linux-sparc.ads (.../branches/gcc-4_8-branch)

41909

@@ -7,7 +7,7 @@

41910

-- S p e c --

41911

-- (GNU/Linux-SPARC Version) --

41912

-- --

41913

41914

41915

-- --

41916

-- This specification is derived from the Ada Reference Manual for use with --

41917

-- GNAT. The copyright notice above, and the license provisions that follow --

41918

@@ -35,9 +35,10 @@

41919

------------------------------------------------------------------------------

41920

41921

package System is

41922

-pragma Pure (System);

41923

--- Note that we take advantage of the implementation permission to

41924

--- make this unit Pure instead of Preelaborable, see RM 13.7(36)

41925

+ pragma Pure;

41926

+ -- Note that we take advantage of the implementation permission to make

41927

+ -- this unit Pure instead of Preelaborable; see RM 13.7.1(15). In Ada

41928

+ -- 2005, this is Pure in any case (AI-362).

41929

41930

type Name is (SYSTEM_NAME_GNAT);

41931

System_Name : constant Name := SYSTEM_NAME_GNAT;

41932

@@ -61,6 +62,7 @@

41933

-- Storage-related Declarations

41934

41935

type Address is private;

41936

+ pragma Preelaborable_Initialization (Address);

41937

Null_Address : constant Address;

41938

41939

Storage_Unit : constant := 8;

41940

Index: gcc/ada/system-rtems.ads

41941

===================================================================

41942

--- a/src/gcc/ada/system-rtems.ads (.../tags/gcc_4_8_2_release)

41943

+++ b/src/gcc/ada/system-rtems.ads (.../branches/gcc-4_8-branch)

41944

@@ -7,7 +7,7 @@

41945

-- S p e c --

41946

-- (Compiler Version) --

41947

-- --

41948

41949

41950

-- --

41951

-- This specification is derived from the Ada Reference Manual for use with --

41952

-- GNAT. The copyright notice above, and the license provisions that follow --

41953

@@ -34,9 +34,8 @@

41954

-- --

41955

------------------------------------------------------------------------------

41956

41957

--- This version of System is a RTEMS version that is used in building

41958

--- the compiler. This is based as closely as possible on the generic

41959

--- version with the following exceptions:

41960

+-- This version is for RTEMS. It is based as closely as possible on the

41961

+-- generic version with the following exceptions:

41962

-- + priority definitions

41963

41964

package System is

41965

@@ -67,6 +66,7 @@

41966

-- Storage-related Declarations

41967

41968

type Address is private;

41969

+ pragma Preelaborable_Initialization (Address);

41970

Null_Address : constant Address;

41971

41972

Storage_Unit : constant := Standard'Storage_Unit;

41973

Index: gcc/gimple-ssa-strength-reduction.c

41974

===================================================================

41975

--- a/src/gcc/gimple-ssa-strength-reduction.c (.../tags/gcc_4_8_2_release)

41976

+++ b/src/gcc/gimple-ssa-strength-reduction.c (.../branches/gcc-4_8-branch)

41977

@@ -735,15 +735,18 @@

41978

X = Y * c

41979

============================

41980

X = (B + i') * (S * c) */

41981

- base = base_cand->base_expr;

41982

- index = base_cand->index;

41983

temp = tree_to_double_int (base_cand->stride)

41984

* tree_to_double_int (stride_in);

41985

- stride = double_int_to_tree (TREE_TYPE (stride_in), temp);

41986

- ctype = base_cand->cand_type;

41987

- if (has_single_use (base_in))

41988

- savings = (base_cand->dead_savings

41989

- + stmt_cost (base_cand->cand_stmt, speed));

41990

+ if (double_int_fits_to_tree_p (TREE_TYPE (stride_in), temp))

41991

+ {

41992

+ base = base_cand->base_expr;

41993

+ index = base_cand->index;

41994

+ stride = double_int_to_tree (TREE_TYPE (stride_in), temp);

41995

+ ctype = base_cand->cand_type;

41996

+ if (has_single_use (base_in))

41997

+ savings = (base_cand->dead_savings

41998

+ + stmt_cost (base_cand->cand_stmt, speed));

41999

+ }

42000

}

42001

else if (base_cand->kind == CAND_ADD

42002

&& operand_equal_p (base_cand->stride, integer_one_node, 0))

42003

Index: gcc/tree-eh.c

42004

===================================================================

42005

--- a/src/gcc/tree-eh.c (.../tags/gcc_4_8_2_release)

42006

+++ b/src/gcc/tree-eh.c (.../branches/gcc-4_8-branch)

42007

@@ -1357,9 +1357,6 @@

42008

x = gimple_seq_last_stmt (finally);

42009

finally_loc = x ? gimple_location (x) : tf_loc;

42010

42011

- /* Lower the finally block itself. */

42012

- lower_eh_constructs_1 (state, &finally);

42013

-

42014

/* Prepare for switch statement generation. */

42015

nlabels = tf->dest_array.length ();

42016

return_index = nlabels;

42017

@@ -1445,6 +1442,7 @@

42018

x = gimple_build_label (finally_label);

42019

gimple_seq_add_stmt (&tf->top_p_seq, x);

42020

42021

+ lower_eh_constructs_1 (state, &finally);

42022

gimple_seq_add_seq (&tf->top_p_seq, finally);

42023

42024

/* Redirect each incoming goto edge. */

42025

@@ -2502,12 +2500,6 @@

42026

restart:

42027

switch (code)

42028

{

42029

- case TARGET_MEM_REF:

42030

- if (TREE_CODE (TMR_BASE (expr)) == ADDR_EXPR

42031

- && !TMR_INDEX (expr) && !TMR_INDEX2 (expr))

42032

- return false;

42033

- return !TREE_THIS_NOTRAP (expr);

42034

-

42035

case COMPONENT_REF:

42036

case REALPART_EXPR:

42037

case IMAGPART_EXPR:

42038

@@ -2534,10 +2526,36 @@

42039

return false;

42040

return !in_array_bounds_p (expr);

42041

42042

+ case TARGET_MEM_REF:

42043

case MEM_REF:

42044

+ if (TREE_CODE (TREE_OPERAND (expr, 0)) == ADDR_EXPR

42045

+ && tree_could_trap_p (TREE_OPERAND (TREE_OPERAND (expr, 0), 0)))

42046

+ return true;

42047

+ if (TREE_THIS_NOTRAP (expr))

42048

+ return false;

42049

+ /* We cannot prove that the access is in-bounds when we have

42050

+ variable-index TARGET_MEM_REFs. */

42051

+ if (code == TARGET_MEM_REF

42052

+ && (TMR_INDEX (expr) || TMR_INDEX2 (expr)))

42053

+ return true;

42054

if (TREE_CODE (TREE_OPERAND (expr, 0)) == ADDR_EXPR)

42055

- return false;

42056

- /* Fallthru. */

42057

+ {

42058

+ tree base = TREE_OPERAND (TREE_OPERAND (expr, 0), 0);

42059

+ double_int off = mem_ref_offset (expr);

42060

+ if (off.is_negative ())

42061

+ return true;

42062

+ if (TREE_CODE (base) == STRING_CST)

42063

+ return double_int::from_uhwi (TREE_STRING_LENGTH (base)).ule (off);

42064

+ else if (DECL_SIZE_UNIT (base) == NULL_TREE

42065

+ || TREE_CODE (DECL_SIZE_UNIT (base)) != INTEGER_CST

42066

+ || tree_to_double_int (DECL_SIZE_UNIT (base)).ule (off))

42067

+ return true;

42068

+ /* Now we are sure the first byte of the access is inside

42069

+ the object. */

42070

+ return false;

42071

+ }

42072

+ return true;

42073

+

42074

case INDIRECT_REF:

42075

return !TREE_THIS_NOTRAP (expr);

42076

42077

@@ -4166,8 +4184,11 @@

42078

/* If the block is totally empty, look for more unsplitting cases. */

42079

if (gsi_end_p (gsi))

42080

{

42081

- /* For the degenerate case of an infinite loop bail out. */

42082

- if (infinite_empty_loop_p (e_out))

42083

+ /* For the degenerate case of an infinite loop bail out.

42084

+ If bb has no successors and is totally empty, which can happen e.g.

42085

+ because of incorrect noreturn attribute, bail out too. */

42086

+ if (e_out == NULL

42087

+ || infinite_empty_loop_p (e_out))

42088

return ret;

42089

42090

return ret | cleanup_empty_eh_unsplit (bb, e_out, lp);

42091

@@ -4304,11 +4325,12 @@

42092

remove_unreachable_handlers ();

42093

42094

/* Watch out for the region tree vanishing due to all unreachable. */

42095

- if (cfun->eh->region_tree && optimize)

42096

+ if (cfun->eh->region_tree)

42097

{

42098

bool changed = false;

42099

42100

- changed |= unsplit_all_eh ();

42101

+ if (optimize)

42102

+ changed |= unsplit_all_eh ();

42103

changed |= cleanup_all_empty_eh ();

42104

42105

if (changed)

42106

Index: gcc/fortran/interface.c

42107

===================================================================

42108

--- a/src/gcc/fortran/interface.c (.../tags/gcc_4_8_2_release)

42109

+++ b/src/gcc/fortran/interface.c (.../branches/gcc-4_8-branch)

42110

@@ -1245,7 +1245,8 @@

42111

return FAILURE;

42112

}

42113

42114

- if (r1->ts.u.cl->length)

42115

+ if (s1->ts.u.cl && s1->ts.u.cl->length

42116

+ && s2->ts.u.cl && s2->ts.u.cl->length)

42117

{

42118

int compval = gfc_dep_compare_expr (r1->ts.u.cl->length,

42119

r2->ts.u.cl->length);

42120

@@ -1367,8 +1368,8 @@

42121

if (s1->attr.function && s2->attr.function)

42122

{

42123

/* If both are functions, check result characteristics. */

42124

- if (check_result_characteristics (s1, s2, errmsg, err_len)

42125

- == FAILURE)

42126

+ if (check_result_characteristics (s1, s2, errmsg, err_len) == FAILURE

42127

+ || check_result_characteristics (s2, s1, errmsg, err_len) == FAILURE)

42128

return 0;

42129

}

42130

42131

Index: gcc/fortran/intrinsic.c

42132

===================================================================

42133

--- a/src/gcc/fortran/intrinsic.c (.../tags/gcc_4_8_2_release)

42134

+++ b/src/gcc/fortran/intrinsic.c (.../branches/gcc-4_8-branch)

42135

@@ -4229,7 +4229,7 @@

42136

c->resolved_sym->attr.elemental = isym->elemental;

42137

}

42138

42139

- if (gfc_pure (NULL) && !isym->pure)

42140

+ if (!isym->pure && gfc_pure (NULL))

42141

{

42142

gfc_error ("Subroutine call to intrinsic '%s' at %L is not PURE", name,

42143

&c->loc);

42144

@@ -4236,6 +4236,9 @@

42145

return MATCH_ERROR;

42146

}

42147

42148

+ if (!isym->pure)

42149

+ gfc_unset_implicit_pure (NULL);

42150

+

42151

c->resolved_sym->attr.noreturn = isym->noreturn;

42152

42153

return MATCH_YES;

42154

Index: gcc/fortran/trans-expr.c

42155

===================================================================

42156

--- a/src/gcc/fortran/trans-expr.c (.../tags/gcc_4_8_2_release)

42157

+++ b/src/gcc/fortran/trans-expr.c (.../branches/gcc-4_8-branch)

42158

@@ -355,7 +355,11 @@

42159

gfc_conv_expr_descriptor (parmse, e);

42160

42161

if (e->rank != class_ts.u.derived->components->as->rank)

42162

- class_array_data_assign (&block, ctree, parmse->expr, true);

42163

+ {

42164

+ gcc_assert (class_ts.u.derived->components->as->type

42165

+ == AS_ASSUMED_RANK);

42166

+ class_array_data_assign (&block, ctree, parmse->expr, false);

42167

+ }

42168

else

42169

{

42170

if (gfc_expr_attr (e).codimension)

42171

@@ -670,7 +674,6 @@

42172

gfc_add_modify (&parmse->post, vptr,

42173

fold_convert (TREE_TYPE (vptr), ctree));

42174

42175

- gcc_assert (!optional || (optional && !copyback));

42176

if (optional)

42177

{

42178

tree tmp2;

42179

@@ -6343,7 +6346,13 @@

42180

/* Returns a reference to the scalar evaluated outside the loop

42181

for this case. */

42182

gfc_conv_expr (se, expr);

42183

- se->expr = gfc_build_addr_expr (NULL_TREE, se->expr);

42184

+

42185

+ if (expr->ts.type == BT_CHARACTER

42186

+ && expr->expr_type != EXPR_FUNCTION)

42187

+ gfc_conv_string_parameter (se);

42188

+ else

42189

+ se->expr = gfc_build_addr_expr (NULL_TREE, se->expr);

42190

+

42191

return;

42192

}

42193

42194

Index: gcc/fortran/trans-array.c

42195

===================================================================

42196

--- a/src/gcc/fortran/trans-array.c (.../tags/gcc_4_8_2_release)

42197

+++ b/src/gcc/fortran/trans-array.c (.../branches/gcc-4_8-branch)

42198

@@ -1,5 +1,5 @@

42199

/* Array translation routines

42200

42201

42202

Contributed by Paul Brook <paul@nowt.org>

42203

and Steven Bosscher <s.bosscher@student.tudelft.nl>

42204

42205

@@ -2487,6 +2487,11 @@

42206

a reference to the value. */

42207

gfc_conv_expr (&se, expr);

42208

}

42209

+

42210

+ /* Ensure that a pointer to the string is stored. */

42211

+ if (expr->ts.type == BT_CHARACTER)

42212

+ gfc_conv_string_parameter (&se);

42213

+

42214

gfc_add_block_to_block (&outer_loop->pre, &se.pre);

42215

gfc_add_block_to_block (&outer_loop->post, &se.post);

42216

if (gfc_is_class_scalar_expr (expr))

42217

@@ -7940,6 +7945,7 @@

42218

tree size1;

42219

tree size2;

42220

tree array1;

42221

+ tree cond_null;

42222

tree cond;

42223

tree tmp;

42224

tree tmp2;

42225

@@ -8015,9 +8021,9 @@

42226

jump_label2 = gfc_build_label_decl (NULL_TREE);

42227

42228

/* Allocate if data is NULL. */

42229

- cond = fold_build2_loc (input_location, EQ_EXPR, boolean_type_node,

42230

+ cond_null = fold_build2_loc (input_location, EQ_EXPR, boolean_type_node,

42231

array1, build_int_cst (TREE_TYPE (array1), 0));

42232

- tmp = build3_v (COND_EXPR, cond,

42233

+ tmp = build3_v (COND_EXPR, cond_null,

42234

build1_v (GOTO_EXPR, jump_label1),

42235

build_empty_stmt (input_location));

42236

gfc_add_expr_to_block (&fblock, tmp);

42237

@@ -8069,13 +8075,25 @@

42238

tmp = build1_v (LABEL_EXPR, jump_label1);

42239

gfc_add_expr_to_block (&fblock, tmp);

42240

42241

- size1 = gfc_conv_descriptor_size (desc, expr1->rank);

42242

+ /* If the lhs has not been allocated, its bounds will not have been

42243

+ initialized and so its size is set to zero. */

42244

+ size1 = gfc_create_var (gfc_array_index_type, NULL);

42245

+ gfc_init_block (&alloc_block);

42246

+ gfc_add_modify (&alloc_block, size1, gfc_index_zero_node);

42247

+ gfc_init_block (&realloc_block);

42248

+ gfc_add_modify (&realloc_block, size1,

42249

+ gfc_conv_descriptor_size (desc, expr1->rank));

42250

+ tmp = build3_v (COND_EXPR, cond_null,

42251

+ gfc_finish_block (&alloc_block),

42252

+ gfc_finish_block (&realloc_block));

42253

+ gfc_add_expr_to_block (&fblock, tmp);

42254

42255

- /* Get the rhs size. Fix both sizes. */

42256

+ /* Get the rhs size and fix it. */

42257

if (expr2)

42258

desc2 = rss->info->data.array.descriptor;

42259

else

42260

desc2 = NULL_TREE;

42261

+

42262

size2 = gfc_index_one_node;

42263

for (n = 0; n < expr2->rank; n++)

42264

{

42265

@@ -8089,8 +8107,6 @@

42266

gfc_array_index_type,

42267

tmp, size2);

42268

}

42269

-

42270

- size1 = gfc_evaluate_now (size1, &fblock);

42271

size2 = gfc_evaluate_now (size2, &fblock);

42272

42273

cond = fold_build2_loc (input_location, NE_EXPR, boolean_type_node,

42274

Index: gcc/fortran/symbol.c

42275

===================================================================

42276

--- a/src/gcc/fortran/symbol.c (.../tags/gcc_4_8_2_release)

42277

+++ b/src/gcc/fortran/symbol.c (.../branches/gcc-4_8-branch)

42278

@@ -1110,8 +1110,8 @@

42279

return FAILURE;

42280

}

42281

42282

- if (s == SAVE_EXPLICIT && gfc_implicit_pure (NULL))

42283

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

42284

+ if (s == SAVE_EXPLICIT)

42285

+ gfc_unset_implicit_pure (NULL);

42286

42287

if (s == SAVE_EXPLICIT && attr->save == SAVE_EXPLICIT)

42288

{

42289

Index: gcc/fortran/class.c

42290

===================================================================

42291

--- a/src/gcc/fortran/class.c (.../tags/gcc_4_8_2_release)

42292

+++ b/src/gcc/fortran/class.c (.../branches/gcc-4_8-branch)

42293

@@ -2486,7 +2486,7 @@

42294

return NULL;

42295

42296

/* Sometimes the typespec is passed from a single call. */

42297

- if (ts->type == BT_DERIVED)

42298

+ if (ts->type == BT_DERIVED || ts->type == BT_CLASS)

42299

return gfc_find_derived_vtab (ts->u.derived);

42300

42301

/* Find the top-level namespace. */

42302

Index: gcc/fortran/decl.c

42303

===================================================================

42304

--- a/src/gcc/fortran/decl.c (.../tags/gcc_4_8_2_release)

42305

+++ b/src/gcc/fortran/decl.c (.../branches/gcc-4_8-branch)

42306

@@ -510,10 +510,8 @@

42307

free (newdata);

42308

return MATCH_ERROR;

42309

}

42310

+ gfc_unset_implicit_pure (gfc_current_ns->proc_name);

42311

42312

- if (gfc_implicit_pure (NULL))

42313

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

42314

-

42315

/* Mark the variable as having appeared in a data statement. */

42316

if (gfc_add_data (&sym->attr, sym->name, &sym->declared_at) == FAILURE)

42317

{

42318

@@ -571,10 +569,8 @@

42319

gfc_error ("DATA statement at %C is not allowed in a PURE procedure");

42320

return MATCH_ERROR;

42321

}

42322

+ gfc_unset_implicit_pure (gfc_current_ns->proc_name);

42323

42324

- if (gfc_implicit_pure (NULL))

42325

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

42326

-

42327

return MATCH_YES;

42328

42329

cleanup:

42330

@@ -1737,6 +1733,7 @@

42331

"a PURE procedure");

42332

return MATCH_ERROR;

42333

}

42334

+ gfc_unset_implicit_pure (gfc_current_ns->proc_name);

42335

42336

/* Match NULL() initialization. */

42337

m = gfc_match_null (init);

42338

@@ -2045,6 +2042,10 @@

42339

m = MATCH_ERROR;

42340

}

42341

42342

+ if (current_attr.flavor != FL_PARAMETER

42343

+ && gfc_state_stack->state != COMP_DERIVED)

42344

+ gfc_unset_implicit_pure (gfc_current_ns->proc_name);

42345

+

42346

if (m != MATCH_YES)

42347

goto cleanup;

42348

}

42349

@@ -5069,7 +5070,14 @@

42350

if (gfc_add_proc (&c->attr, name, NULL) == FAILURE)

42351

return MATCH_ERROR;

42352

42353

- c->tb = tb;

42354

+ if (num == 1)

42355

+ c->tb = tb;

42356

+ else

42357

+ {

42358

+ c->tb = XCNEW (gfc_typebound_proc);

42359

+ c->tb->where = gfc_current_locus;

42360

+ *c->tb = *tb;

42361

+ }

42362

42363

/* Set interface. */

42364

if (proc_if != NULL)

42365

@@ -7384,6 +7392,7 @@

42366

42367

42368

/* Check a derived type that is being extended. */

42369

+

42370

static gfc_symbol*

42371

check_extended_derived_type (char *name)

42372

{

42373

@@ -7395,14 +7404,15 @@

42374

return NULL;

42375

}

42376

42377

+ extended = gfc_find_dt_in_generic (extended);

42378

+

42379

+ /* F08:C428. */

42380

if (!extended)

42381

{

42382

- gfc_error ("No such symbol in TYPE definition at %C");

42383

+ gfc_error ("Symbol '%s' at %C has not been previously defined", name);

42384

return NULL;

42385

}

42386

42387

- extended = gfc_find_dt_in_generic (extended);

42388

-

42389

if (extended->attr.flavor != FL_DERIVED)

42390

{

42391

gfc_error ("'%s' in EXTENDS expression at %C is not a "

42392

Index: gcc/fortran/dump-parse-tree.c

42393

===================================================================

42394

--- a/src/gcc/fortran/dump-parse-tree.c (.../tags/gcc_4_8_2_release)

42395

+++ b/src/gcc/fortran/dump-parse-tree.c (.../branches/gcc-4_8-branch)

42396

@@ -110,7 +110,8 @@

42397

break;

42398

42399

case BT_CHARACTER:

42400

- show_expr (ts->u.cl->length);

42401

+ if (ts->u.cl)

42402

+ show_expr (ts->u.cl->length);

42403

fprintf(dumpfile, " %d", ts->kind);

42404

break;

42405

42406

Index: gcc/fortran/cpp.c

42407

===================================================================

42408

--- a/src/gcc/fortran/cpp.c (.../tags/gcc_4_8_2_release)

42409

+++ b/src/gcc/fortran/cpp.c (.../branches/gcc-4_8-branch)

42410

@@ -569,6 +569,7 @@

42411

if (gfc_option.flag_preprocessed)

42412

return;

42413

42414

+ cpp_change_file (cpp_in, LC_RENAME, _("<built-in>"));

42415

if (!gfc_cpp_option.no_predefined)

42416

{

42417

/* Make sure all of the builtins about to be declared have

42418

Index: gcc/fortran/gfortran.h

42419

===================================================================

42420

--- a/src/gcc/fortran/gfortran.h (.../tags/gcc_4_8_2_release)

42421

+++ b/src/gcc/fortran/gfortran.h (.../branches/gcc-4_8-branch)

42422

@@ -2830,6 +2830,7 @@

42423

int gfc_impure_variable (gfc_symbol *);

42424

int gfc_pure (gfc_symbol *);

42425

int gfc_implicit_pure (gfc_symbol *);

42426

+void gfc_unset_implicit_pure (gfc_symbol *);

42427

int gfc_elemental (gfc_symbol *);

42428

gfc_try gfc_resolve_iterator (gfc_iterator *, bool, bool);

42429

gfc_try find_forall_index (gfc_expr *, gfc_symbol *, int);

42430

Index: gcc/fortran/ChangeLog

42431

===================================================================

42432

--- a/src/gcc/fortran/ChangeLog (.../tags/gcc_4_8_2_release)

42433

+++ b/src/gcc/fortran/ChangeLog (.../branches/gcc-4_8-branch)

42434

@@ -1,3 +1,259 @@

42435

+2014-04-11 Janne Blomqvist <jb@gcc.gnu.org>

42436

+

42437

+ * intrinsic.texi (RANDOM_SEED): Improve example.

42438

+

42439

+2014-04-10 Jakub Jelinek <jakub@redhat.com>

42440

+

42441

+ Backport from mainline

42442

+ 2014-03-22 Jakub Jelinek <jakub@redhat.com>

42443

+

42444

+ PR debug/60603

42445

+ * cpp.c (gfc_cpp_init): Restore cb_change_file call to

42446

+ <built-in>.

42447

+

42448

+2014-03-29 Mikael Morin <mikael@gcc.gnu.org>

42449

+

42450

+ PR fortran/60677

42451

+ * trans-intrinsic.c (gfc_conv_intrinsic_ichar): Enlarge argument

42452

+ list buffer.

42453

+

42454

+2014-03-28 Mikael Morin <mikael@gcc.gnu.org>

42455

+ Tobias Burnus <burnus@net-b.de>

42456

+

42457

+ PR fortran/60576

42458

+ * trans-expr.c (gfc_conv_derived_to_class): Avoid

42459

+ generation of out-of-bounds range expr.

42460

+

42461

+2014-03-28 Thomas Koenig <tkoenig@gcc.gnu.org>

42462

+

42463

+ PR fortran/60522

42464

+ * frontend-passes.c (cfe_code): Do not walk subtrees

42465

+ for WHERE.

42466

+

42467

+2014-03-20 Tobias Burnus <burnus@net-b.de>

42468

+

42469

+ PR fortran/60543

42470

+ PR fortran/60283

42471

+ * gfortran.h (gfc_unset_implicit_pure): New prototype.

42472

+ * resolve.c (gfc_unset_implicit_pure): New.

42473

+ (resolve_structure_cons, resolve_function,

42474

+ pure_subroutine, resolve_ordinary_assign): Use it.

42475

+ * decl.c (match_old_style_init, gfc_match_data,

42476

+ match_pointer_init, variable_decl): Ditto.

42477

+ * expr.c (gfc_check_pointer_assign): Ditto.

42478

+ * intrinsic.c (gfc_intrinsic_sub_interface): Ditto.

42479

+ * io.c (match_vtag, gfc_match_open, gfc_match_close,

42480

+ match_filepos, gfc_match_inquire, gfc_match_print,

42481

+ gfc_match_wait, check_io_constraints): Ditto.

42482

+ * match.c (gfc_match_critical, gfc_match_stopcode,

42483

+ lock_unlock_statement, sync_statement, gfc_match_allocate,

42484

+ gfc_match_deallocate): Ditto.

42485

+ * parse.c (decode_omp_directive): Ditto.

42486

+ * symbol.c (gfc_add_save): Ditto.

42487

+

42488

+2014-03-08 Janus Weil <janus@gcc.gnu.org>

42489

+

42490

+ PR fortran/60450

42491

+ * simplify.c (gfc_simplify_shape): Only clear shape if it was really

42492

+ created successfully.

42493

+

42494

+2014-03-06 Jakub Jelinek <jakub@redhat.com>

42495

+

42496

+ Backport from mainline

42497

+ 2014-02-11 Jakub Jelinek <jakub@redhat.com>

42498

+

42499

+ PR fortran/52370

42500

+ * trans-decl.c (gfc_build_dummy_array_decl): Set TREE_NO_WARNING

42501

+ on decl if sym->attr.optional.

42502

+

42503

+2014-03-02 Mikael Morin <mikael@gcc.gnu.org>

42504

+

42505

+ PR fortran/60341

42506

+ * frontend-passes.c (optimize_comparison): Guard two union accesses

42507

+ with the corresponding tag checks.

42508

+

42509

+2014-02-22 Mikael Morin <mikael@gcc.gnu.org>

42510

+

42511

+ PR fortran/59599

42512

+ * trans-intrinsic.c (gfc_conv_intrinsic_ichar): Calculate the

42513

+ number of arguments.

42514

+

42515

+2014-02-19 Tobias Burnus <burnus@net-b.de>

42516

+

42517

+ PR fortran/49397

42518

+ * expr.c (gfc_check_pointer_assign): Add check for

42519

+ F2008Cor2, C729.

42520

+ * trans-decl.c (gfc_get_symbol_decl): Correctly generate

42521

+ external decl in a corner case.

42522

+

42523

+2014-02-19 Janus Weil <janus@gcc.gnu.org>

42524

+

42525

+ Backports from mainline:

42526

+ 2014-02-17 Janus Weil <janus@gcc.gnu.org>

42527

+

42528

+ PR fortran/55907

42529

+ * resolve.c (build_default_init_expr): Don't initialize character

42530

+ variable if -fno-automatic is given.

42531

+

42532

+ 2014-02-18 Janus Weil <janus@gcc.gnu.org>

42533

+

42534

+ PR fortran/60231

42535

+ * resolve.c (check_generic_tbp_ambiguity): Check for presence of dummy

42536

+ arguments to prevent ICE.

42537

+

42538

+2014-02-09 Janus Weil <janus@gcc.gnu.org>

42539

+

42540

+ Backport from mainline

42541

+ 2013-10-21 Tobias Burnus <burnus@net-b.de>

42542

+

42543

+ PR fortran/58803

42544

+ PR fortran/59395

42545

+ * decl.c (match_ppc_decl): Prevent later double free.

42546

+

42547

+2014-02-08 Mikael Morin <mikael@gcc.gnu.org>

42548

+

42549

+ PR fortran/57033

42550

+ * primary.c (gfc_convert_to_structure_constructor): Avoid null pointer

42551

+ dereference.

42552

+

42553

+2014-02-07 Paul Thomas <pault@gcc.gnu.org>

42554

+

42555

+ PR fortran/59906

42556

+ * trans-stmt.c (gfc_add_loop_ss_code): In the case of character

42557

+ SS_REFERENCE, use gfc_conv_string_parameter to ensure that a

42558

+ pointer to the string is stored.

42559

+ * trans-expr.c (gfc_conv_expr_reference): Likewise, use

42560

+ gfc_conv_string_parameter to ensure that a pointer to is passed

42561

+ to the elemental function.

42562

+

42563

+2014-02-01 Paul Thomas <pault@gcc.gnu.org>

42564

+

42565

+ PR fortran/59414

42566

+ * trans-stmt.c (gfc_trans_allocate): Before the pointer

42567

+ assignment to transfer the source _vptr to a class allocate

42568

+ expression, the final class reference should be exposed. The

42569

+ tail that includes the _data and array references is stored.

42570

+ This reduced expression is transferred to 'lhs' and the _vptr

42571

+ added. Then the tail is restored to the allocate expression.

42572

+

42573

+2014-01-26 Mikael Morin <mikael@gcc.gnu.org>

42574

+

42575

+ PR fortran/58007

42576

+ * module.c

42577

+ (fp2, find_pointer2): Remove.

42578

+ (mio_component_ref): Don't forcedfully set the containing derived type

42579

+ symbol for loading. Remove unused argument.

42580

+ (mio_ref): Update caller

42581

+ (skip_list): New argument nest_level. Initialize level with the new

42582

+ argument.

42583

+ (read_module): Add forced pointer components association for derived

42584

+ type symbols.

42585

+

42586

+2014-01-19 Paul Thomas <pault@gcc.gnu.org>

42587

+

42588

+ Backport from mainline

42589

+ 2013-12-01 Paul Thomas <pault@gcc.gnu.org>

42590

+

42591

+ PR fortran/58410

42592

+ * trans-array.c (gfc_alloc_allocatable_for_assignment): Do not

42593

+ use the array bounds of an unallocated array but set its size

42594

+ to zero instead.

42595

+

42596

+2014-01-19 Paul Thomas <pault@gcc.gnu.org>

42597

+

42598

+ Backport from mainline

42599

+ 2013-12-01 Paul Thomas <pault@gcc.gnu.org>

42600

+

42601

+ PR fortran/34547

42602

+ * resolve.c (resolve_transfer): EXPR_NULL is always in an

42603

+ invalid context in a transfer statement.

42604

+

42605

+2014-01-11 Janus Weil <janus@gcc.gnu.org>

42606

+

42607

+ Backport from mainline

42608

+ 2013-12-29 Janus Weil <janus@gcc.gnu.org>

42609

+

42610

+ PR fortran/59612

42611

+ PR fortran/57042

42612

+ * dump-parse-tree.c (show_typespec): Check for charlen.

42613

+ * invoke.texi: Fix documentation of -fdump-fortran-optimized and

42614

+ -fdump-parse-tree.

42615

+

42616

+2014-01-04 Janus Weil <janus@gcc.gnu.org>

42617

+

42618

+ Backport from mainline

42619

+ 2014-01-02 Janus Weil <janus@gcc.gnu.org>

42620

+

42621

+ PR fortran/59654

42622

+ * resolve.c (resolve_typebound_procedures): No need to create the vtab

42623

+ here.

42624

+

42625

+2013-12-31 Janus Weil <janus@gcc.gnu.org>

42626

+

42627

+ Backport from mainline

42628

+ 2013-12-30 Janus Weil <janus@gcc.gnu.org>

42629

+

42630

+ PR fortran/58998

42631

+ * resolve.c (resolve_symbol): Check that symbol is not only flavorless

42632

+ but also untyped.

42633

+

42634

+2013-12-18 Janus Weil <janus@gcc.gnu.org>

42635

+

42636

+ Backport from mainline

42637

+ 2013-12-15 Janus Weil <janus@gcc.gnu.org>

42638

+

42639

+ PR fortran/59493

42640

+ * class.c (gfc_find_intrinsic_vtab): Handle BT_CLASS.

42641

+

42642

+2013-11-30 Paul Thomas <pault@gcc.gnu.org>

42643

+

42644

+ Backport from mainline

42645

+ 2013-11-04 Paul Thomas <pault@gcc.gnu.org>

42646

+

42647

+ PR fortran/57445

42648

+ * trans-expr.c (gfc_conv_class_to_class): Remove spurious

42649

+ assert.

42650

+

42651

+2013-11-17 Janus Weil <janus@gcc.gnu.org>

42652

+

42653

+ Backport from mainline

42654

+ 2013-11-07 Janus Weil <janus@gcc.gnu.org>

42655

+

42656

+ PR fortran/58471

42657

+ * primary.c (gfc_expr_attr): Check for result symbol.

42658

+

42659

+2013-11-16 Janus Weil <janus@gcc.gnu.org>

42660

+

42661

+ Backport from mainline

42662

+ 2013-09-20 Janus Weil <janus@gcc.gnu.org>

42663

+

42664

+ PR fortran/58099

42665

+ * expr.c (gfc_check_pointer_assign): Remove second call to

42666

+ 'gfc_compare_interfaces' with swapped arguments.

42667

+ * interface.c (gfc_compare_interfaces): Symmetrize the call to

42668

+ 'check_result_characteristics' by calling it with swapped arguments.

42669

+

42670

+2013-11-16 Paul Thomas <pault@gcc.gnu.org>

42671

+

42672

+ PR fortran/58771

42673

+ * trans-io.c (transfer_expr): If the backend_decl for a derived

42674

+ type is missing, build it with gfc_typenode_for_spec.

42675

+

42676

+2013-11-05 Steven G. Kargl <kargl@gcc.gnu.org>

42677

+

42678

+ PR fortran/58989

42679

+ * check.c (gfc_check_reshape): ensure that shape is a constant

42680

+ expression.

42681

+

42682

+2013-11-02 Janus Weil <janus@gcc.gnu.org>

42683

+

42684

+ Backport from mainline

42685

+ 2013-09-23 Janus Weil <janus@gcc.gnu.org>

42686

+

42687

+ PR fortran/58355

42688

+ * decl.c (check_extended_derived_type): Prevent segfault, modify error

42689

+ message.

42690

+

42691

2013-10-16 Release Manager

42692

42693

* GCC 4.8.2 released.

42694

Index: gcc/fortran/trans-stmt.c

42695

===================================================================

42696

--- a/src/gcc/fortran/trans-stmt.c (.../tags/gcc_4_8_2_release)

42697

+++ b/src/gcc/fortran/trans-stmt.c (.../branches/gcc-4_8-branch)

42698

@@ -5104,10 +5104,49 @@

42699

{

42700

gfc_expr *lhs, *rhs;

42701

gfc_se lse;

42702

+ gfc_ref *ref, *class_ref, *tail;

42703

42704

+ /* Find the last class reference. */

42705

+ class_ref = NULL;

42706

+ for (ref = e->ref; ref; ref = ref->next)

42707

+ {

42708

+ if (ref->type == REF_COMPONENT

42709

+ && ref->u.c.component->ts.type == BT_CLASS)

42710

+ class_ref = ref;

42711

+

42712

+ if (ref->next == NULL)

42713

+ break;

42714

+ }

42715

+

42716

+ /* Remove and store all subsequent references after the

42717

+ CLASS reference. */

42718

+ if (class_ref)

42719

+ {

42720

+ tail = class_ref->next;

42721

+ class_ref->next = NULL;

42722

+ }

42723

+ else

42724

+ {

42725

+ tail = e->ref;

42726

+ e->ref = NULL;

42727

+ }

42728

+

42729

lhs = gfc_expr_to_initialize (e);

42730

gfc_add_vptr_component (lhs);

42731

42732

+ /* Remove the _vptr component and restore the original tail

42733

+ references. */

42734

+ if (class_ref)

42735

+ {

42736

+ gfc_free_ref_list (class_ref->next);

42737

+ class_ref->next = tail;

42738

+ }

42739

+ else

42740

+ {

42741

+ gfc_free_ref_list (e->ref);

42742

+ e->ref = tail;

42743

+ }

42744

+

42745

if (class_expr != NULL_TREE)

42746

{

42747

/* Polymorphic SOURCE: VPTR must be determined at run time. */

42748

Index: gcc/fortran/expr.c

42749

===================================================================

42750

--- a/src/gcc/fortran/expr.c (.../tags/gcc_4_8_2_release)

42751

+++ b/src/gcc/fortran/expr.c (.../branches/gcc-4_8-branch)

42752

@@ -3555,11 +3555,13 @@

42753

return FAILURE;

42754

}

42755

42756

- if (!gfc_compare_interfaces (s2, s1, name, 0, 1,

42757

- err, sizeof(err), NULL, NULL))

42758

+ /* Check F2008Cor2, C729. */

42759

+ if (!s2->attr.intrinsic && s2->attr.if_source == IFSRC_UNKNOWN

42760

+ && !s2->attr.external && !s2->attr.subroutine && !s2->attr.function)

42761

{

42762

- gfc_error ("Interface mismatch in procedure pointer assignment "

42763

- "at %L: %s", &rvalue->where, err);

42764

+ gfc_error ("Procedure pointer target '%s' at %L must be either an "

42765

+ "intrinsic, host or use associated, referenced or have "

42766

+ "the EXTERNAL attribute", s2->name, &rvalue->where);

42767

return FAILURE;

42768

}

42769

42770

@@ -3679,9 +3681,8 @@

42771

}

42772

42773

if (is_implicit_pure && gfc_impure_variable (rvalue->symtree->n.sym))

42774

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

42775

+ gfc_unset_implicit_pure (gfc_current_ns->proc_name);

42776

42777

-

42778

if (gfc_has_vector_index (rvalue))

42779

{

42780

gfc_error ("Pointer assignment with vector subscript "

42781

Index: gcc/fortran/module.c

42782

===================================================================

42783

--- a/src/gcc/fortran/module.c (.../tags/gcc_4_8_2_release)

42784

+++ b/src/gcc/fortran/module.c (.../branches/gcc-4_8-branch)

42785

@@ -386,37 +386,6 @@

42786

}

42787

42788

42789

-/* Recursive function to find a pointer within a tree by brute force. */

42790

-

42791

-static pointer_info *

42792

-fp2 (pointer_info *p, const void *target)

42793

-{

42794

- pointer_info *q;

42795

-

42796

- if (p == NULL)

42797

- return NULL;

42798

-

42799

- if (p->u.pointer == target)

42800

- return p;

42801

-

42802

- q = fp2 (p->left, target);

42803

- if (q != NULL)

42804

- return q;

42805

-

42806

- return fp2 (p->right, target);

42807

-}

42808

-

42809

-

42810

-/* During reading, find a pointer_info node from the pointer value.

42811

- This amounts to a brute-force search. */

42812

-

42813

-static pointer_info *

42814

-find_pointer2 (void *p)

42815

-{

42816

- return fp2 (pi_root, p);

42817

-}

42818

-

42819

-

42820

/* Resolve any fixups using a known pointer. */

42821

42822

static void

42823

@@ -2522,45 +2491,13 @@

42824

the namespace and is not loaded again. */

42825

42826

static void

42827

-mio_component_ref (gfc_component **cp, gfc_symbol *sym)

42828

+mio_component_ref (gfc_component **cp)

42829

{

42830

- char name[GFC_MAX_SYMBOL_LEN + 1];

42831

- gfc_component *q;

42832

pointer_info *p;

42833

42834

p = mio_pointer_ref (cp);

42835

if (p->type == P_UNKNOWN)

42836

p->type = P_COMPONENT;

42837

-

42838

- if (iomode == IO_OUTPUT)

42839

- mio_pool_string (&(*cp)->name);

42840

- else

42841

- {

42842

- mio_internal_string (name);

42843

-

42844

- if (sym && sym->attr.is_class)

42845

- sym = sym->components->ts.u.derived;

42846

-

42847

- /* It can happen that a component reference can be read before the

42848

- associated derived type symbol has been loaded. Return now and

42849

- wait for a later iteration of load_needed. */

42850

- if (sym == NULL)

42851

- return;

42852

-

42853

- if (sym->components != NULL && p->u.pointer == NULL)

42854

- {

42855

- /* Symbol already loaded, so search by name. */

42856

- q = gfc_find_component (sym, name, true, true);

42857

-

42858

- if (q)

42859

- associate_integer_pointer (p, q);

42860

- }

42861

-

42862

- /* Make sure this symbol will eventually be loaded. */

42863

- p = find_pointer2 (sym);

42864

- if (p->u.rsym.state == UNUSED)

42865

- p->u.rsym.state = NEEDED;

42866

- }

42867

}

42868

42869

42870

@@ -2917,7 +2854,7 @@

42871

42872

case REF_COMPONENT:

42873

mio_symbol_ref (&r->u.c.sym);

42874

- mio_component_ref (&r->u.c.component, r->u.c.sym);

42875

+ mio_component_ref (&r->u.c.component);

42876

break;

42877

42878

case REF_SUBSTRING:

42879

@@ -3772,7 +3709,9 @@

42880

42881

42882

/* Unlike most other routines, the address of the symbol node is already

42883

- fixed on input and the name/module has already been filled in. */

42884

+ fixed on input and the name/module has already been filled in.

42885

+ If you update the symbol format here, don't forget to update read_module

42886

+ as well (look for "seek to the symbol's component list"). */

42887

42888

static void

42889

mio_symbol (gfc_symbol *sym)

42890

@@ -3782,6 +3721,7 @@

42891

mio_lparen ();

42892

42893

mio_symbol_attribute (&sym->attr);

42894

+

42895

mio_typespec (&sym->ts);

42896

if (sym->ts.type == BT_CLASS)

42897

sym->attr.class_ok = 1;

42898

@@ -3812,7 +3752,6 @@

42899

42900

/* Note that components are always saved, even if they are supposed

42901

to be private. Component access is checked during searching. */

42902

-

42903

mio_component_list (&sym->components, sym->attr.vtype);

42904

42905

if (sym->components != NULL)

42906

@@ -3914,14 +3853,17 @@

42907

}

42908

42909

42910

-/* Skip a list between balanced left and right parens. */

42911

+/* Skip a list between balanced left and right parens.

42912

+ By setting NEST_LEVEL one assumes that a number of NEST_LEVEL opening parens

42913

+ have been already parsed by hand, and the remaining of the content is to be

42914

+ skipped here. The default value is 0 (balanced parens). */

42915

42916

static void

42917

-skip_list (void)

42918

+skip_list (int nest_level = 0)

42919

{

42920

int level;

42921

42922

- level = 0;

42923

+ level = nest_level;

42924

do

42925

{

42926

switch (parse_atom ())

42927

@@ -4555,7 +4497,6 @@

42928

info->u.rsym.ns = atom_int;

42929

42930

get_module_locus (&info->u.rsym.where);

42931

- skip_list ();

42932

42933

/* See if the symbol has already been loaded by a previous module.

42934

If so, we reference the existing symbol and prevent it from

42935

@@ -4566,11 +4507,57 @@

42936

42937

if (sym == NULL

42938

|| (sym->attr.flavor == FL_VARIABLE && info->u.rsym.ns !=1))

42939

- continue;

42940

+ {

42941

+ skip_list ();

42942

+ continue;

42943

+ }

42944

42945

info->u.rsym.state = USED;

42946

info->u.rsym.sym = sym;

42947

+ /* The current symbol has already been loaded, so we can avoid loading

42948

+ it again. However, if it is a derived type, some of its components

42949

+ can be used in expressions in the module. To avoid the module loading

42950

+ failing, we need to associate the module's component pointer indexes

42951

+ with the existing symbol's component pointers. */

42952

+ if (sym->attr.flavor == FL_DERIVED)

42953

+ {

42954

+ gfc_component *c;

42955

42956

+ /* First seek to the symbol's component list. */

42957

+ mio_lparen (); /* symbol opening. */

42958

+ skip_list (); /* skip symbol attribute. */

42959

+ skip_list (); /* typespec. */

42960

+ require_atom (ATOM_INTEGER); /* namespace ref. */

42961

+ require_atom (ATOM_INTEGER); /* common ref. */

42962

+ skip_list (); /* formal args. */

42963

+ /* no value. */

42964

+ skip_list (); /* array_spec. */

42965

+ require_atom (ATOM_INTEGER); /* result. */

42966

+ /* not a cray pointer. */

42967

+

42968

+ mio_lparen (); /* component list opening. */

42969

+ for (c = sym->components; c; c = c->next)

42970

+ {

42971

+ pointer_info *p;

42972

+ const char *comp_name;

42973

+ int n;

42974

+

42975

+ mio_lparen (); /* component opening. */

42976

+ mio_integer (&n);

42977

+ p = get_integer (n);

42978

+ if (p->u.pointer == NULL)

42979

+ associate_integer_pointer (p, c);

42980

+ mio_pool_string (&comp_name);

42981

+ gcc_assert (comp_name == c->name);

42982

+ skip_list (1); /* component end. */

42983

+ }

42984

+ mio_rparen (); /* component list closing. */

42985

+

42986

+ skip_list (1); /* symbol end. */

42987

+ }

42988

+ else

42989

+ skip_list ();

42990

+

42991

/* Some symbols do not have a namespace (eg. formal arguments),

42992

so the automatic "unique symtree" mechanism must be suppressed

42993

by marking them as referenced. */

42994

Index: gcc/fortran/io.c

42995

===================================================================

42996

--- a/src/gcc/fortran/io.c (.../tags/gcc_4_8_2_release)

42997

+++ b/src/gcc/fortran/io.c (.../branches/gcc-4_8-branch)

42998

@@ -1309,7 +1309,8 @@

42999

return MATCH_ERROR;

43000

}

43001

43002

- if (gfc_pure (NULL) && gfc_impure_variable (result->symtree->n.sym))

43003

+ bool impure = gfc_impure_variable (result->symtree->n.sym);

43004

+ if (impure && gfc_pure (NULL))

43005

{

43006

gfc_error ("Variable %s cannot be assigned in PURE procedure at %C",

43007

tag->name);

43008

@@ -1317,8 +1318,8 @@

43009

return MATCH_ERROR;

43010

}

43011

43012

- if (gfc_implicit_pure (NULL) && gfc_impure_variable (result->symtree->n.sym))

43013

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

43014

+ if (impure)

43015

+ gfc_unset_implicit_pure (NULL);

43016

43017

*v = result;

43018

return MATCH_YES;

43019

@@ -1838,8 +1839,7 @@

43020

goto cleanup;

43021

}

43022

43023

- if (gfc_implicit_pure (NULL))

43024

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

43025

+ gfc_unset_implicit_pure (NULL);

43026

43027

warn = (open->err || open->iostat) ? true : false;

43028

43029

@@ -2251,8 +2251,7 @@

43030

goto cleanup;

43031

}

43032

43033

- if (gfc_implicit_pure (NULL))

43034

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

43035

+ gfc_unset_implicit_pure (NULL);

43036

43037

warn = (close->iostat || close->err) ? true : false;

43038

43039

@@ -2419,8 +2418,7 @@

43040

goto cleanup;

43041

}

43042

43043

- if (gfc_implicit_pure (NULL))

43044

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

43045

+ gfc_unset_implicit_pure (NULL);

43046

43047

new_st.op = op;

43048

new_st.ext.filepos = fp;

43049

@@ -3276,9 +3274,8 @@

43050

"an internal file in a PURE procedure",

43051

io_kind_name (k));

43052

43053

- if (gfc_implicit_pure (NULL) && (k == M_READ || k == M_WRITE))

43054

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

43055

-

43056

+ if (k == M_READ || k == M_WRITE)

43057

+ gfc_unset_implicit_pure (NULL);

43058

}

43059

43060

if (k != M_READ)

43061

@@ -3809,8 +3806,7 @@

43062

return MATCH_ERROR;

43063

}

43064

43065

- if (gfc_implicit_pure (NULL))

43066

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

43067

+ gfc_unset_implicit_pure (NULL);

43068

43069

return MATCH_YES;

43070

}

43071

@@ -3969,8 +3965,7 @@

43072

return MATCH_ERROR;

43073

}

43074

43075

- if (gfc_implicit_pure (NULL))

43076

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

43077

+ gfc_unset_implicit_pure (NULL);

43078

43079

new_st.block = gfc_get_code ();

43080

new_st.block->op = EXEC_IOLENGTH;

43081

@@ -4023,8 +4018,7 @@

43082

goto cleanup;

43083

}

43084

43085

- if (gfc_implicit_pure (NULL))

43086

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

43087

+ gfc_unset_implicit_pure (NULL);

43088

43089

if (inquire->id != NULL && inquire->pending == NULL)

43090

{

43091

@@ -4212,8 +4206,7 @@

43092

goto cleanup;

43093

}

43094

43095

- if (gfc_implicit_pure (NULL))

43096

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

43097

+ gfc_unset_implicit_pure (NULL);

43098

43099

new_st.op = EXEC_WAIT;

43100

new_st.ext.wait = wait;

43101

Index: gcc/fortran/frontend-passes.c

43102

===================================================================

43103

--- a/src/gcc/fortran/frontend-passes.c (.../tags/gcc_4_8_2_release)

43104

+++ b/src/gcc/fortran/frontend-passes.c (.../branches/gcc-4_8-branch)

43105

@@ -623,12 +623,35 @@

43106

to insert statements as needed. */

43107

43108

static int

43109

-cfe_code (gfc_code **c, int *walk_subtrees ATTRIBUTE_UNUSED,

43110

- void *data ATTRIBUTE_UNUSED)

43111

+cfe_code (gfc_code **c, int *walk_subtrees, void *data ATTRIBUTE_UNUSED)

43112

{

43113

current_code = c;

43114

inserted_block = NULL;

43115

changed_statement = NULL;

43116

+

43117

+ /* Do not do anything inside a WHERE statement; scalar assignments, BLOCKs

43118

+ and allocation on assigment are prohibited inside WHERE, and finally

43119

+ masking an expression would lead to wrong-code when replacing

43120

+

43121

+ WHERE (a>0)

43122

+ b = sum(foo(a) + foo(a))

43123

+ END WHERE

43124

+

43125

+ with

43126

+

43127

+ WHERE (a > 0)

43128

+ tmp = foo(a)

43129

+ b = sum(tmp + tmp)

43130

+ END WHERE

43131

+*/

43132

+

43133

+ if ((*c)->op == EXEC_WHERE)

43134

+ {

43135

+ *walk_subtrees = 0;

43136

+ return 0;

43137

+ }

43138

+

43139

+

43140

return 0;

43141

}

43142

43143

@@ -1214,7 +1237,9 @@

43144

/* Replace A // B < A // C with B < C, and A // B < C // B

43145

with A < C. */

43146

if (op1->ts.type == BT_CHARACTER && op2->ts.type == BT_CHARACTER

43147

+ && op1->expr_type == EXPR_OP

43148

&& op1->value.op.op == INTRINSIC_CONCAT

43149

+ && op2->expr_type == EXPR_OP

43150

&& op2->value.op.op == INTRINSIC_CONCAT)

43151

{

43152

gfc_expr *op1_left = op1->value.op.op1;

43153

Index: gcc/fortran/resolve.c

43154

===================================================================

43155

--- a/src/gcc/fortran/resolve.c (.../tags/gcc_4_8_2_release)

43156

+++ b/src/gcc/fortran/resolve.c (.../branches/gcc-4_8-branch)

43157

@@ -1,5 +1,5 @@

43158

/* Perform type resolution on the various structures.

43159

43160

43161

Contributed by Andy Vaught

43162

43163

This file is part of GCC.

43164

@@ -1259,9 +1259,10 @@

43165

}

43166

43167

/* F2003, C1272 (3). */

43168

- if (gfc_pure (NULL) && cons->expr->expr_type == EXPR_VARIABLE

43169

- && (gfc_impure_variable (cons->expr->symtree->n.sym)

43170

- || gfc_is_coindexed (cons->expr)))

43171

+ bool impure = cons->expr->expr_type == EXPR_VARIABLE

43172

+ && (gfc_impure_variable (cons->expr->symtree->n.sym)

43173

+ || gfc_is_coindexed (cons->expr));

43174

+ if (impure && gfc_pure (NULL))

43175

{

43176

t = FAILURE;

43177

gfc_error ("Invalid expression in the structure constructor for "

43178

@@ -1269,12 +1270,8 @@

43179

comp->name, &cons->expr->where);

43180

}

43181

43182

- if (gfc_implicit_pure (NULL)

43183

- && cons->expr->expr_type == EXPR_VARIABLE

43184

- && (gfc_impure_variable (cons->expr->symtree->n.sym)

43185

- || gfc_is_coindexed (cons->expr)))

43186

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

43187

-

43188

+ if (impure)

43189

+ gfc_unset_implicit_pure (NULL);

43190

}

43191

43192

return t;

43193

@@ -3295,8 +3292,7 @@

43194

t = FAILURE;

43195

}

43196

43197

- if (gfc_implicit_pure (NULL))

43198

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

43199

+ gfc_unset_implicit_pure (NULL);

43200

}

43201

43202

/* Functions without the RECURSIVE attribution are not allowed to

43203

@@ -3361,8 +3357,7 @@

43204

gfc_error ("Subroutine call to '%s' at %L is not PURE", sym->name,

43205

&c->loc);

43206

43207

- if (gfc_implicit_pure (NULL))

43208

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

43209

+ gfc_unset_implicit_pure (NULL);

43210

}

43211

43212

43213

@@ -8705,10 +8700,11 @@

43214

&& exp->value.op.op == INTRINSIC_PARENTHESES)

43215

exp = exp->value.op.op1;

43216

43217

- if (exp && exp->expr_type == EXPR_NULL && exp->ts.type == BT_UNKNOWN)

43218

+ if (exp && exp->expr_type == EXPR_NULL

43219

+ && code->ext.dt)

43220

{

43221

- gfc_error ("NULL intrinsic at %L in data transfer statement requires "

43222

- "MOLD=", &exp->where);

43223

+ gfc_error ("Invalid context for NULL () intrinsic at %L",

43224

+ &exp->where);

43225

return;

43226

}

43227

43228

@@ -9612,7 +9608,7 @@

43229

if (lhs->expr_type == EXPR_VARIABLE

43230

&& lhs->symtree->n.sym != gfc_current_ns->proc_name

43231

&& lhs->symtree->n.sym->ns != gfc_current_ns)

43232

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

43233

+ gfc_unset_implicit_pure (NULL);

43234

43235

if (lhs->ts.type == BT_DERIVED

43236

&& lhs->expr_type == EXPR_VARIABLE

43237

@@ -9620,11 +9616,11 @@

43238

&& rhs->expr_type == EXPR_VARIABLE

43239

&& (gfc_impure_variable (rhs->symtree->n.sym)

43240

|| gfc_is_coindexed (rhs)))

43241

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

43242

+ gfc_unset_implicit_pure (NULL);

43243

43244

/* Fortran 2008, C1283. */

43245

if (gfc_is_coindexed (lhs))

43246

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

43247

+ gfc_unset_implicit_pure (NULL);

43248

}

43249

43250

/* F03:7.4.1.2. */

43251

@@ -11057,7 +11053,7 @@

43252

init_expr = NULL;

43253

}

43254

if (!init_expr && gfc_option.flag_init_character == GFC_INIT_CHARACTER_ON

43255

- && sym->ts.u.cl->length)

43256

+ && sym->ts.u.cl->length && gfc_option.flag_max_stack_var_size != 0)

43257

{

43258

gfc_actual_arglist *arg;

43259

init_expr = gfc_get_expr ();

43260

@@ -11877,6 +11873,7 @@

43261

{

43262

gfc_symbol *sym1, *sym2;

43263

const char *pass1, *pass2;

43264

+ gfc_formal_arglist *dummy_args;

43265

43266

gcc_assert (t1->specific && t2->specific);

43267

gcc_assert (!t1->specific->is_generic);

43268

@@ -11899,19 +11896,33 @@

43269

return FAILURE;

43270

}

43271

43272

- /* Compare the interfaces. */

43273

+ /* Determine PASS arguments. */

43274

if (t1->specific->nopass)

43275

pass1 = NULL;

43276

else if (t1->specific->pass_arg)

43277

pass1 = t1->specific->pass_arg;

43278

else

43279

- pass1 = gfc_sym_get_dummy_args (t1->specific->u.specific->n.sym)->sym->name;

43280

+ {

43281

+ dummy_args = gfc_sym_get_dummy_args (t1->specific->u.specific->n.sym);

43282

+ if (dummy_args)

43283

+ pass1 = dummy_args->sym->name;

43284

+ else

43285

+ pass1 = NULL;

43286

+ }

43287

if (t2->specific->nopass)

43288

pass2 = NULL;

43289

else if (t2->specific->pass_arg)

43290

pass2 = t2->specific->pass_arg;

43291

else

43292

- pass2 = gfc_sym_get_dummy_args (t2->specific->u.specific->n.sym)->sym->name;

43293

+ {

43294

+ dummy_args = gfc_sym_get_dummy_args (t2->specific->u.specific->n.sym);

43295

+ if (dummy_args)

43296

+ pass2 = dummy_args->sym->name;

43297

+ else

43298

+ pass2 = NULL;

43299

+ }

43300

+

43301

+ /* Compare the interfaces. */

43302

if (gfc_compare_interfaces (sym1, sym2, sym2->name, !t1->is_operator, 0,

43303

NULL, 0, pass1, pass2))

43304

{

43305

@@ -12425,9 +12436,6 @@

43306

resolve_bindings_derived = derived;

43307

resolve_bindings_result = SUCCESS;

43308

43309

- /* Make sure the vtab has been generated. */

43310

- gfc_find_derived_vtab (derived);

43311

-

43312

if (derived->f2k_derived->tb_sym_root)

43313

gfc_traverse_symtree (derived->f2k_derived->tb_sym_root,

43314

&resolve_typebound_procedure);

43315

@@ -13256,7 +13264,8 @@

43316

if (sym->attr.flavor == FL_UNKNOWN

43317

|| (sym->attr.flavor == FL_PROCEDURE && !sym->attr.intrinsic

43318

&& !sym->attr.generic && !sym->attr.external

43319

- && sym->attr.if_source == IFSRC_UNKNOWN))

43320

+ && sym->attr.if_source == IFSRC_UNKNOWN

43321

+ && sym->ts.type == BT_UNKNOWN))

43322

{

43323

43324

/* If we find that a flavorless symbol is an interface in one of the

43325

@@ -14376,6 +14385,33 @@

43326

}

43327

43328

43329

+void

43330

+gfc_unset_implicit_pure (gfc_symbol *sym)

43331

+{

43332

+ gfc_namespace *ns;

43333

+

43334

+ if (sym == NULL)

43335

+ {

43336

+ /* Check if the current procedure is implicit_pure. Walk up

43337

+ the procedure list until we find a procedure. */

43338

+ for (ns = gfc_current_ns; ns; ns = ns->parent)

43339

+ {

43340

+ sym = ns->proc_name;

43341

+ if (sym == NULL)

43342

+ return;

43343

+

43344

+ if (sym->attr.flavor == FL_PROCEDURE)

43345

+ break;

43346

+ }

43347

+ }

43348

+

43349

+ if (sym->attr.flavor == FL_PROCEDURE)

43350

+ sym->attr.implicit_pure = 0;

43351

+ else

43352

+ sym->attr.pure = 0;

43353

+}

43354

+

43355

+

43356

/* Test whether the current procedure is elemental or not. */

43357

43358

int

43359

Index: gcc/fortran/trans-io.c

43360

===================================================================

43361

--- a/src/gcc/fortran/trans-io.c (.../tags/gcc_4_8_2_release)

43362

+++ b/src/gcc/fortran/trans-io.c (.../branches/gcc-4_8-branch)

43363

@@ -243,16 +243,16 @@

43364

43365

/* The code to generate the error. */

43366

gfc_start_block (&block);

43367

-

43368

+

43369

arg1 = gfc_build_addr_expr (NULL_TREE, var);

43370

-

43371

+

43372

arg2 = build_int_cst (integer_type_node, error_code),

43373

-

43374

+

43375

asprintf (&message, "%s", _(msgid));

43376

arg3 = gfc_build_addr_expr (pchar_type_node,

43377

gfc_build_localized_cstring_const (message));

43378

free (message);

43379

-

43380

+

43381

tmp = build_call_expr_loc (input_location,

43382

gfor_fndecl_generate_error, 3, arg1, arg2, arg3);

43383

43384

@@ -521,7 +521,7 @@

43385

gfc_trans_io_runtime_check (cond, var, LIBERROR_BAD_UNIT,

43386

"Unit number in I/O statement too small",

43387

&se.pre);

43388

-

43389

+

43390

/* UNIT numbers should be less than the max. */

43391

val = gfc_conv_mpz_to_tree (gfc_integer_kinds[i].huge, 4);

43392

cond = fold_build2_loc (input_location, GT_EXPR, boolean_type_node,

43393

@@ -1000,7 +1000,7 @@

43394

if (p->convert)

43395

mask |= set_string (&block, &post_block, var, IOPARM_open_convert,

43396

p->convert);

43397

-

43398

+

43399

if (p->newunit)

43400

mask |= set_parameter_ref (&block, &post_block, var, IOPARM_open_newunit,

43401

p->newunit);

43402

@@ -1234,7 +1234,7 @@

43403

{

43404

mask |= set_parameter_ref (&block, &post_block, var, IOPARM_inquire_exist,

43405

p->exist);

43406

-

43407

+

43408

if (p->unit && !p->iostat)

43409

{

43410

p->iostat = create_dummy_iostat ();

43411

@@ -1322,7 +1322,7 @@

43412

if (p->pad)

43413

mask |= set_string (&block, &post_block, var, IOPARM_inquire_pad,

43414

p->pad);

43415

-

43416

+

43417

if (p->convert)

43418

mask |= set_string (&block, &post_block, var, IOPARM_inquire_convert,

43419

p->convert);

43420

@@ -1547,7 +1547,7 @@

43421

tree dtype;

43422

tree dt_parm_addr;

43423

tree decl = NULL_TREE;

43424

- int n_dim;

43425

+ int n_dim;

43426

int itype;

43427

int rank = 0;

43428

43429

@@ -2032,7 +2032,7 @@

43430

if (gfc_notification_std (GFC_STD_GNU) != SILENT)

43431

{

43432

gfc_error_now ("Derived type '%s' at %L has PRIVATE components",

43433

- ts->u.derived->name, code != NULL ? &(code->loc) :

43434

+ ts->u.derived->name, code != NULL ? &(code->loc) :

43435

&gfc_current_locus);

43436

return;

43437

}

43438

@@ -2041,7 +2041,7 @@

43439

ts->kind = ts->u.derived->ts.kind;

43440

ts->f90_type = ts->u.derived->ts.f90_type;

43441

}

43442

-

43443

+

43444

kind = ts->kind;

43445

function = NULL;

43446

arg2 = NULL;

43447

@@ -2123,7 +2123,7 @@

43448

function = iocall[IOCALL_X_CHARACTER_WIDE];

43449

else

43450

function = iocall[IOCALL_X_CHARACTER_WIDE_WRITE];

43451

-

43452

+

43453

tmp = gfc_build_addr_expr (NULL_TREE, dt_parm);

43454

tmp = build_call_expr_loc (input_location,

43455

function, 4, tmp, addr_expr, arg2, arg3);

43456

@@ -2158,6 +2158,12 @@

43457

expr = build_fold_indirect_ref_loc (input_location,

43458

expr);

43459

43460

+ /* Make sure that the derived type has been built. An external

43461

+ function, if only referenced in an io statement requires this

43462

+ check (see PR58771). */

43463

+ if (ts->u.derived->backend_decl == NULL_TREE)

43464

+ tmp = gfc_typenode_for_spec (ts);

43465

+

43466

for (c = ts->u.derived->components; c; c = c->next)

43467

{

43468

field = c->backend_decl;

43469

Index: gcc/fortran/trans-decl.c

43470

===================================================================

43471

--- a/src/gcc/fortran/trans-decl.c (.../tags/gcc_4_8_2_release)

43472

+++ b/src/gcc/fortran/trans-decl.c (.../branches/gcc-4_8-branch)

43473

@@ -1013,6 +1013,10 @@

43474

TREE_STATIC (decl) = 0;

43475

DECL_EXTERNAL (decl) = 0;

43476

43477

+ /* Avoid uninitialized warnings for optional dummy arguments. */

43478

+ if (sym->attr.optional)

43479

+ TREE_NO_WARNING (decl) = 1;

43480

+

43481

/* We should never get deferred shape arrays here. We used to because of

43482

frontend bugs. */

43483

gcc_assert (sym->as->type != AS_DEFERRED);

43484

@@ -1358,9 +1362,10 @@

43485

43486

if (sym->attr.flavor == FL_PROCEDURE)

43487

{

43488

- /* Catch function declarations. Only used for actual parameters,

43489

+ /* Catch functions. Only used for actual parameters,

43490

procedure pointers and procptr initialization targets. */

43491

- if (sym->attr.external || sym->attr.use_assoc || sym->attr.intrinsic)

43492

+ if (sym->attr.external || sym->attr.use_assoc || sym->attr.intrinsic

43493

+ || sym->attr.if_source != IFSRC_DECL)

43494

{

43495

decl = gfc_get_extern_function_decl (sym);

43496

gfc_set_decl_location (decl, &sym->declared_at);

43497

Index: gcc/fortran/match.c

43498

===================================================================

43499

--- a/src/gcc/fortran/match.c (.../tags/gcc_4_8_2_release)

43500

+++ b/src/gcc/fortran/match.c (.../branches/gcc-4_8-branch)

43501

@@ -1753,8 +1753,7 @@

43502

return MATCH_ERROR;

43503

}

43504

43505

- if (gfc_implicit_pure (NULL))

43506

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

43507

+ gfc_unset_implicit_pure (NULL);

43508

43509

if (gfc_notify_std (GFC_STD_F2008, "CRITICAL statement at %C")

43510

== FAILURE)

43511

@@ -2683,8 +2682,7 @@

43512

goto cleanup;

43513

}

43514

43515

- if (gfc_implicit_pure (NULL))

43516

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

43517

+ gfc_unset_implicit_pure (NULL);

43518

43519

if (st == ST_STOP && gfc_find_state (COMP_CRITICAL) == SUCCESS)

43520

{

43521

@@ -2824,8 +2822,7 @@

43522

return MATCH_ERROR;

43523

}

43524

43525

- if (gfc_implicit_pure (NULL))

43526

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

43527

+ gfc_unset_implicit_pure (NULL);

43528

43529

if (gfc_option.coarray == GFC_FCOARRAY_NONE)

43530

{

43531

@@ -3020,8 +3017,7 @@

43532

return MATCH_ERROR;

43533

}

43534

43535

- if (gfc_implicit_pure (NULL))

43536

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

43537

+ gfc_unset_implicit_pure (NULL);

43538

43539

if (gfc_notify_std (GFC_STD_F2008, "SYNC statement at %C")

43540

== FAILURE)

43541

@@ -3500,15 +3496,15 @@

43542

if (gfc_check_do_variable (tail->expr->symtree))

43543

goto cleanup;

43544

43545

- if (gfc_pure (NULL) && gfc_impure_variable (tail->expr->symtree->n.sym))

43546

+ bool impure = gfc_impure_variable (tail->expr->symtree->n.sym);

43547

+ if (impure && gfc_pure (NULL))

43548

{

43549

gfc_error ("Bad allocate-object at %C for a PURE procedure");

43550

goto cleanup;

43551

}

43552

43553

- if (gfc_implicit_pure (NULL)

43554

- && gfc_impure_variable (tail->expr->symtree->n.sym))

43555

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

43556

+ if (impure)

43557

+ gfc_unset_implicit_pure (NULL);

43558

43559

if (tail->expr->ts.deferred)

43560

{

43561

@@ -3890,14 +3886,15 @@

43562

43563

sym = tail->expr->symtree->n.sym;

43564

43565

- if (gfc_pure (NULL) && gfc_impure_variable (sym))

43566

+ bool impure = gfc_impure_variable (sym);

43567

+ if (impure && gfc_pure (NULL))

43568

{

43569

gfc_error ("Illegal allocate-object at %C for a PURE procedure");

43570

goto cleanup;

43571

}

43572

43573

- if (gfc_implicit_pure (NULL) && gfc_impure_variable (sym))

43574

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

43575

+ if (impure)

43576

+ gfc_unset_implicit_pure (NULL);

43577

43578

if (gfc_is_coarray (tail->expr)

43579

&& gfc_find_state (COMP_DO_CONCURRENT) == SUCCESS)

43580

Index: gcc/fortran/parse.c

43581

===================================================================

43582

--- a/src/gcc/fortran/parse.c (.../tags/gcc_4_8_2_release)

43583

+++ b/src/gcc/fortran/parse.c (.../branches/gcc-4_8-branch)

43584

@@ -550,8 +550,7 @@

43585

return ST_NONE;

43586

}

43587

43588

- if (gfc_implicit_pure (NULL))

43589

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

43590

+ gfc_unset_implicit_pure (NULL);

43591

43592

old_locus = gfc_current_locus;

43593

43594

Index: gcc/fortran/check.c

43595

===================================================================

43596

--- a/src/gcc/fortran/check.c (.../tags/gcc_4_8_2_release)

43597

+++ b/src/gcc/fortran/check.c (.../branches/gcc-4_8-branch)

43598

@@ -3208,7 +3208,7 @@

43599

"than %d elements", &shape->where, GFC_MAX_DIMENSIONS);

43600

return FAILURE;

43601

}

43602

- else if (shape->expr_type == EXPR_ARRAY)

43603

+ else if (shape->expr_type == EXPR_ARRAY && gfc_is_constant_expr (shape))

43604

{

43605

gfc_expr *e;

43606

int i, extent;

43607

Index: gcc/fortran/primary.c

43608

===================================================================

43609

--- a/src/gcc/fortran/primary.c (.../tags/gcc_4_8_2_release)

43610

+++ b/src/gcc/fortran/primary.c (.../branches/gcc-4_8-branch)

43611

@@ -2252,7 +2252,7 @@

43612

case EXPR_FUNCTION:

43613

gfc_clear_attr (&attr);

43614

43615

- if (e->value.function.esym != NULL)

43616

+ if (e->value.function.esym && e->value.function.esym->result)

43617

{

43618

gfc_symbol *sym = e->value.function.esym->result;

43619

attr = sym->attr;

43620

@@ -2540,7 +2540,8 @@

43621

if (parent && !comp)

43622

break;

43623

43624

- actual = actual->next;

43625

+ if (actual)

43626

+ actual = actual->next;

43627

}

43628

43629

if (build_actual_constructor (&comp_head, &ctor_head, sym) == FAILURE)

43630

Index: gcc/fortran/trans-intrinsic.c

43631

===================================================================

43632

--- a/src/gcc/fortran/trans-intrinsic.c (.../tags/gcc_4_8_2_release)

43633

+++ b/src/gcc/fortran/trans-intrinsic.c (.../branches/gcc-4_8-branch)

43634

@@ -4684,9 +4684,11 @@

43635

static void

43636

gfc_conv_intrinsic_ichar (gfc_se * se, gfc_expr * expr)

43637

{

43638

- tree args[2], type, pchartype;

43639

+ tree args[3], type, pchartype;

43640

+ int nargs;

43641

43642

- gfc_conv_intrinsic_function_args (se, expr, args, 2);

43643

+ nargs = gfc_intrinsic_argument_list_length (expr);

43644

+ gfc_conv_intrinsic_function_args (se, expr, args, nargs);

43645

gcc_assert (POINTER_TYPE_P (TREE_TYPE (args[1])));

43646

pchartype = gfc_get_pchar_type (expr->value.function.actual->expr->ts.kind);

43647

args[1] = fold_build1_loc (input_location, NOP_EXPR, pchartype, args[1]);

43648

Index: gcc/fortran/simplify.c

43649

===================================================================

43650

--- a/src/gcc/fortran/simplify.c (.../tags/gcc_4_8_2_release)

43651

+++ b/src/gcc/fortran/simplify.c (.../branches/gcc-4_8-branch)

43652

@@ -5528,7 +5528,7 @@

43653

if (e == &gfc_bad_expr || range_check (e, "SHAPE") == &gfc_bad_expr)

43654

{

43655

gfc_free_expr (result);

43656

- if (t)

43657

+ if (t == SUCCESS)

43658

gfc_clear_shape (shape, source->rank);

43659

return &gfc_bad_expr;

43660

}

43661

@@ -5536,7 +5536,7 @@

43662

gfc_constructor_append_expr (&result->value.constructor, e, NULL);

43663

}

43664

43665

- if (t)

43666

+ if (t == SUCCESS)

43667

gfc_clear_shape (shape, source->rank);

43668

43669

return result;

43670

Index: gcc/configure.ac

43671

===================================================================

43672

--- a/src/gcc/configure.ac (.../tags/gcc_4_8_2_release)

43673

+++ b/src/gcc/configure.ac (.../branches/gcc-4_8-branch)

43674

@@ -1516,13 +1516,16 @@

43675

/* | [A-Za-z]:[\\/]* ) realsrcdir=${srcdir};;

43676

*) realsrcdir=../${srcdir};;

43677

esac

43678

- saved_CFLAGS="${CFLAGS}"

43679

+ # Clearing GMPINC is necessary to prevent host headers being

43680

+ # used by the build compiler. Defining GENERATOR_FILE stops

43681

+ # system.h from including gmp.h.

43682

CC="${CC_FOR_BUILD}" CFLAGS="${CFLAGS_FOR_BUILD}" \

43683

- LDFLAGS="${LDFLAGS_FOR_BUILD}" \

43684

+ CXX="${CXX_FOR_BUILD}" CXXFLAGS="${CXXFLAGS_FOR_BUILD}" \

43685

+ LD="${LD_FOR_BUILD}" LDFLAGS="${LDFLAGS_FOR_BUILD}" \

43686

+ GMPINC="" CPPFLAGS="${CPPFLAGS} -DGENERATOR_FILE" \

43687

${realsrcdir}/configure \

43688

--enable-languages=${enable_languages-all} \

43689

--target=$target_alias --host=$build_alias --build=$build_alias

43690

- CFLAGS="${saved_CFLAGS}"

43691

43692

# We just finished tests for the build machine, so rename

43693

# the file auto-build.h in the gcc directory.

43694

@@ -1887,6 +1890,7 @@

43695

if test x$build != x$host || test "x$coverage_flags" != x

43696

then

43697

BUILD_CFLAGS='$(INTERNAL_CFLAGS) $(T_CFLAGS) $(CFLAGS_FOR_BUILD)'

43698

+ BUILD_CXXFLAGS='$(INTERNAL_CFLAGS) $(T_CFLAGS) $(CXXFLAGS_FOR_BUILD)'

43699

BUILD_LDFLAGS='$(LDFLAGS_FOR_BUILD)'

43700

fi

43701

43702

@@ -3611,6 +3615,19 @@

43703

kasumi_fi_xor %f46, %f48, %f50, %f52],,

43704

[AC_DEFINE(HAVE_AS_SPARC4, 1,

43705

[Define if your assembler supports SPARC4 instructions.])])

43706

+

43707

+ gcc_GAS_CHECK_FEATURE([LEON instructions],

43708

+ gcc_cv_as_sparc_leon,,

43709

+ [-Aleon],

43710

+ [.text

43711

+ .register %g2, #scratch

43712

+ .register %g3, #scratch

43713

+ .align 4

43714

+ smac %g2, %g3, %g1

43715

+ umac %g2, %g3, %g1

43716

+ casa [[%g2]] 0xb, %g3, %g1],,

43717

+ [AC_DEFINE(HAVE_AS_LEON, 1,

43718

+ [Define if your assembler supports LEON instructions.])])

43719

;;

43720

43721

changequote(,)dnl

43722

@@ -3749,8 +3766,13 @@

43723

43724

# These two are used unconditionally by i386.[ch]; it is to be defined

43725

# to 1 if the feature is present, 0 otherwise.

43726

+ as_ix86_gotoff_in_data_opt=

43727

+ if test x$gas = xyes; then

43728

+ as_ix86_gotoff_in_data_opt="--32"

43729

+ fi

43730

gcc_GAS_CHECK_FEATURE([GOTOFF in data],

43731

- gcc_cv_as_ix86_gotoff_in_data, [2,11,0],,

43732

+ gcc_cv_as_ix86_gotoff_in_data, [2,11,0],

43733

+ [$as_ix86_gotoff_in_data_opt],

43734

[ .text

43735

.L0:

43736

nop

43737

@@ -3772,6 +3794,12 @@

43738

[AC_DEFINE(HAVE_AS_IX86_REP_LOCK_PREFIX, 1,

43739

[Define if the assembler supports 'rep <insn>, lock <insn>'.])])

43740

43741

+ gcc_GAS_CHECK_FEATURE([ud2 mnemonic],

43742

+ gcc_cv_as_ix86_ud2,,,

43743

+ [ud2],,

43744

+ [AC_DEFINE(HAVE_AS_IX86_UD2, 1,

43745

+ [Define if your assembler supports the 'ud2' mnemonic.])])

43746

+

43747

gcc_GAS_CHECK_FEATURE([R_386_TLS_GD_PLT reloc],

43748

gcc_cv_as_ix86_tlsgdplt,,,

43749

[call tls_gd@tlsgdplt],

43750

@@ -5193,15 +5221,15 @@

43751

AC_MSG_CHECKING([for exported symbols])

43752

if test "x$export_sym_check" != x; then

43753

echo "int main() {return 0;} int foobar() {return 0;}" > conftest.c

43754

- ${CC} ${CFLAGS} ${LDFLAGS} conftest.c -o conftest > /dev/null 2>&1

43755

- if $export_sym_check conftest | grep foobar > /dev/null; then

43756

+ ${CC} ${CFLAGS} ${LDFLAGS} conftest.c -o conftest$ac_exeext > /dev/null 2>&1

43757

+ if $export_sym_check conftest$ac_exeext | grep -q foobar > /dev/null; then

43758

: # No need to use a flag

43759

AC_MSG_RESULT([yes])

43760

else

43761

AC_MSG_RESULT([yes])

43762

AC_MSG_CHECKING([for -rdynamic])

43763

- ${CC} ${CFLAGS} ${LDFLAGS} -rdynamic conftest.c -o conftest > /dev/null 2>&1

43764

- if $export_sym_check conftest | grep foobar > /dev/null; then

43765

+ ${CC} ${CFLAGS} ${LDFLAGS} -rdynamic conftest.c -o conftest$ac_exeext > /dev/null 2>&1

43766

+ if $export_sym_check conftest$ac_exeext | grep -q foobar > /dev/null; then

43767

plugin_rdynamic=yes

43768

pluginlibs="-rdynamic"

43769

else

43770

Index: gcc/function.c

43771

===================================================================

43772

--- a/src/gcc/function.c (.../tags/gcc_4_8_2_release)

43773

+++ b/src/gcc/function.c (.../branches/gcc-4_8-branch)

43774

@@ -2507,6 +2507,7 @@

43775

}

43776

43777

locate_and_pad_parm (data->promoted_mode, data->passed_type, in_regs,

43778

+ all->reg_parm_stack_space,

43779

entry_parm ? data->partial : 0, current_function_decl,

43780

&all->stack_args_size, &data->locate);

43781

43782

@@ -3485,11 +3486,7 @@

43783

/* Adjust function incoming argument size for alignment and

43784

minimum length. */

43785

43786

-#ifdef REG_PARM_STACK_SPACE

43787

- crtl->args.size = MAX (crtl->args.size,

43788

- REG_PARM_STACK_SPACE (fndecl));

43789

-#endif

43790

-

43791

+ crtl->args.size = MAX (crtl->args.size, all.reg_parm_stack_space);

43792

crtl->args.size = CEIL_ROUND (crtl->args.size,

43793

PARM_BOUNDARY / BITS_PER_UNIT);

43794

43795

@@ -3693,6 +3690,9 @@

43796

IN_REGS is nonzero if the argument will be passed in registers. It will

43797

never be set if REG_PARM_STACK_SPACE is not defined.

43798

43799

+ REG_PARM_STACK_SPACE is the number of bytes of stack space reserved

43800

+ for arguments which are passed in registers.

43801

+

43802

FNDECL is the function in which the argument was defined.

43803

43804

There are two types of rounding that are done. The first, controlled by

43805

@@ -3713,7 +3713,8 @@

43806

43807

void

43808

locate_and_pad_parm (enum machine_mode passed_mode, tree type, int in_regs,

43809

- int partial, tree fndecl ATTRIBUTE_UNUSED,

43810

+ int reg_parm_stack_space, int partial,

43811

+ tree fndecl ATTRIBUTE_UNUSED,

43812

struct args_size *initial_offset_ptr,

43813

struct locate_and_pad_arg_data *locate)

43814

{

43815

@@ -3720,12 +3721,8 @@

43816

tree sizetree;

43817

enum direction where_pad;

43818

unsigned int boundary, round_boundary;

43819

- int reg_parm_stack_space = 0;

43820

int part_size_in_regs;

43821

43822

-#ifdef REG_PARM_STACK_SPACE

43823

- reg_parm_stack_space = REG_PARM_STACK_SPACE (fndecl);

43824

-

43825

/* If we have found a stack parm before we reach the end of the

43826

area reserved for registers, skip that area. */

43827

if (! in_regs)

43828

@@ -3743,7 +3740,6 @@

43829

initial_offset_ptr->constant = reg_parm_stack_space;

43830

}

43831

}

43832

-#endif /* REG_PARM_STACK_SPACE */

43833

43834

part_size_in_regs = (reg_parm_stack_space == 0 ? partial : 0);

43835

43836

@@ -3806,11 +3802,7 @@

43837

43838

locate->slot_offset.constant += part_size_in_regs;

43839

43840

- if (!in_regs

43841

-#ifdef REG_PARM_STACK_SPACE

43842

- || REG_PARM_STACK_SPACE (fndecl) > 0

43843

-#endif

43844

- )

43845

+ if (!in_regs || reg_parm_stack_space > 0)

43846

pad_to_arg_alignment (&locate->slot_offset, boundary,

43847

&locate->alignment_pad);

43848

43849

@@ -3830,11 +3822,7 @@

43850

pad_below (&locate->offset, passed_mode, sizetree);

43851

43852

#else /* !ARGS_GROW_DOWNWARD */

43853

- if (!in_regs

43854

-#ifdef REG_PARM_STACK_SPACE

43855

- || REG_PARM_STACK_SPACE (fndecl) > 0

43856

-#endif

43857

- )

43858

+ if (!in_regs || reg_parm_stack_space > 0)

43859

pad_to_arg_alignment (initial_offset_ptr, boundary,

43860

&locate->alignment_pad);

43861

locate->slot_offset = *initial_offset_ptr;

43862

@@ -5093,6 +5081,7 @@

43863

amount. BLKmode results are handled using the group load/store

43864

machinery. */

43865

if (TYPE_MODE (TREE_TYPE (decl_result)) != BLKmode

43866

+ && REG_P (real_decl_rtl)

43867

&& targetm.calls.return_in_msb (TREE_TYPE (decl_result)))

43868

{

43869

emit_move_insn (gen_rtx_REG (GET_MODE (decl_rtl),

43870

@@ -5509,22 +5498,45 @@

43871

except for any part that overlaps SRC (next loop). */

43872

bb_uses = &DF_LR_BB_INFO (bb)->use;

43873

bb_defs = &DF_LR_BB_INFO (bb)->def;

43874

- for (i = dregno; i < end_dregno; i++)

43875

+ if (df_live)

43876

{

43877

- if (REGNO_REG_SET_P (bb_uses, i) || REGNO_REG_SET_P (bb_defs, i))

43878

- next_block = NULL;

43879

- CLEAR_REGNO_REG_SET (live_out, i);

43880

- CLEAR_REGNO_REG_SET (live_in, i);

43881

+ for (i = dregno; i < end_dregno; i++)

43882

+ {

43883

+ if (REGNO_REG_SET_P (bb_uses, i) || REGNO_REG_SET_P (bb_defs, i)

43884

+ || REGNO_REG_SET_P (&DF_LIVE_BB_INFO (bb)->gen, i))

43885

+ next_block = NULL;

43886

+ CLEAR_REGNO_REG_SET (live_out, i);

43887

+ CLEAR_REGNO_REG_SET (live_in, i);

43888

+ }

43889

+

43890

+ /* Check whether BB clobbers SRC. We need to add INSN to BB if so.

43891

+ Either way, SRC is now live on entry. */

43892

+ for (i = sregno; i < end_sregno; i++)

43893

+ {

43894

+ if (REGNO_REG_SET_P (bb_defs, i)

43895

+ || REGNO_REG_SET_P (&DF_LIVE_BB_INFO (bb)->gen, i))

43896

+ next_block = NULL;

43897

+ SET_REGNO_REG_SET (live_out, i);

43898

+ SET_REGNO_REG_SET (live_in, i);

43899

+ }

43900

}

43901

+ else

43902

+ {

43903

+ /* DF_LR_BB_INFO (bb)->def does not comprise the DF_REF_PARTIAL and

43904

+ DF_REF_CONDITIONAL defs. So if DF_LIVE doesn't exist, i.e.

43905

+ at -O1, just give up searching NEXT_BLOCK. */

43906

+ next_block = NULL;

43907

+ for (i = dregno; i < end_dregno; i++)

43908

+ {

43909

+ CLEAR_REGNO_REG_SET (live_out, i);

43910

+ CLEAR_REGNO_REG_SET (live_in, i);

43911

+ }

43912

43913

- /* Check whether BB clobbers SRC. We need to add INSN to BB if so.

43914

- Either way, SRC is now live on entry. */

43915

- for (i = sregno; i < end_sregno; i++)

43916

- {

43917

- if (REGNO_REG_SET_P (bb_defs, i))

43918

- next_block = NULL;

43919

- SET_REGNO_REG_SET (live_out, i);

43920

- SET_REGNO_REG_SET (live_in, i);

43921

+ for (i = sregno; i < end_sregno; i++)

43922

+ {

43923

+ SET_REGNO_REG_SET (live_out, i);

43924

+ SET_REGNO_REG_SET (live_in, i);

43925

+ }

43926

}

43927

43928

/* If we don't need to add the move to BB, look for a single

43929

Index: gcc/print-rtl.c

43930

===================================================================

43931

--- a/src/gcc/print-rtl.c (.../tags/gcc_4_8_2_release)

43932

+++ b/src/gcc/print-rtl.c (.../branches/gcc-4_8-branch)

43933

@@ -582,6 +582,8 @@

43934

43935

if (MEM_EXPR (in_rtx))

43936

print_mem_expr (outfile, MEM_EXPR (in_rtx));

43937

+ else

43938

+ fputc (' ', outfile);

43939

43940

if (MEM_OFFSET_KNOWN_P (in_rtx))

43941

fprintf (outfile, "+" HOST_WIDE_INT_PRINT_DEC, MEM_OFFSET (in_rtx));

43942

Index: gcc/tree-vectorizer.h

43943

===================================================================

43944

--- a/src/gcc/tree-vectorizer.h (.../tags/gcc_4_8_2_release)

43945

+++ b/src/gcc/tree-vectorizer.h (.../branches/gcc-4_8-branch)

43946

@@ -542,6 +542,10 @@

43947

is 1. */

43948

unsigned int gap;

43949

43950

+ /* The minimum negative dependence distance this stmt participates in

43951

+ or zero if none. */

43952

+ unsigned int min_neg_dist;

43953

+

43954

/* Not all stmts in the loop need to be vectorized. e.g, the increment

43955

of the loop induction variable and computation of array indexes. relevant

43956

indicates whether the stmt needs to be vectorized. */

43957

@@ -593,6 +597,7 @@

43958

#define STMT_VINFO_GROUP_READ_WRITE_DEPENDENCE(S) (S)->read_write_dep

43959

#define STMT_VINFO_GROUPED_ACCESS(S) ((S)->first_element != NULL && (S)->data_ref_info)

43960

#define STMT_VINFO_LOOP_PHI_EVOLUTION_PART(S) (S)->loop_phi_evolution_part

43961

+#define STMT_VINFO_MIN_NEG_DIST(S) (S)->min_neg_dist

43962

43963

#define GROUP_FIRST_ELEMENT(S) (S)->first_element

43964

#define GROUP_NEXT_ELEMENT(S) (S)->next_element

43965

Index: gcc/sdbout.c

43966

===================================================================

43967

--- a/src/gcc/sdbout.c (.../tags/gcc_4_8_2_release)

43968

+++ b/src/gcc/sdbout.c (.../branches/gcc-4_8-branch)

43969

@@ -1226,7 +1226,10 @@

43970

sdbout_parms (tree parms)

43971

{

43972

for (; parms; parms = TREE_CHAIN (parms))

43973

- if (DECL_NAME (parms))

43974

+ if (DECL_NAME (parms)

43975

+ && TREE_TYPE (parms) != error_mark_node

43976

+ && DECL_RTL_SET_P (parms)

43977

+ && DECL_INCOMING_RTL (parms))

43978

{

43979

int current_sym_value = 0;

43980

const char *name = IDENTIFIER_POINTER (DECL_NAME (parms));

43981

@@ -1358,7 +1361,10 @@

43982

sdbout_reg_parms (tree parms)

43983

{

43984

for (; parms; parms = TREE_CHAIN (parms))

43985

- if (DECL_NAME (parms))

43986

+ if (DECL_NAME (parms)

43987

+ && TREE_TYPE (parms) != error_mark_node

43988

+ && DECL_RTL_SET_P (parms)

43989

+ && DECL_INCOMING_RTL (parms))

43990

{

43991

const char *name = IDENTIFIER_POINTER (DECL_NAME (parms));

43992

43993

Index: gcc/ipa-split.c

43994

===================================================================

43995

--- a/src/gcc/ipa-split.c (.../tags/gcc_4_8_2_release)

43996

+++ b/src/gcc/ipa-split.c (.../branches/gcc-4_8-branch)

43997

@@ -136,7 +136,7 @@

43998

variable, check it if it is present in bitmap passed via DATA. */

43999

44000

static bool

44001

-test_nonssa_use (gimple stmt ATTRIBUTE_UNUSED, tree t, void *data)

44002

+test_nonssa_use (gimple, tree t, tree, void *data)

44003

{

44004

t = get_base_address (t);

44005

44006

@@ -229,7 +229,7 @@

44007

}

44008

if (gimple_code (stmt) == GIMPLE_LABEL

44009

&& test_nonssa_use (stmt, gimple_label_label (stmt),

44010

- non_ssa_vars))

44011

+ NULL_TREE, non_ssa_vars))

44012

{

44013

ok = false;

44014

goto done;

44015

@@ -258,7 +258,7 @@

44016

if (virtual_operand_p (gimple_phi_result (stmt)))

44017

continue;

44018

if (TREE_CODE (op) != SSA_NAME

44019

- && test_nonssa_use (stmt, op, non_ssa_vars))

44020

+ && test_nonssa_use (stmt, op, op, non_ssa_vars))

44021

{

44022

ok = false;

44023

goto done;

44024

@@ -670,7 +670,7 @@

44025

Return true when access to T prevents splitting the function. */

44026

44027

static bool

44028

-mark_nonssa_use (gimple stmt ATTRIBUTE_UNUSED, tree t, void *data)

44029

+mark_nonssa_use (gimple, tree t, tree, void *data)

44030

{

44031

t = get_base_address (t);

44032

44033

@@ -830,7 +830,7 @@

44034

if (TREE_CODE (op) == SSA_NAME)

44035

bitmap_set_bit (used_ssa_names, SSA_NAME_VERSION (op));

44036

else

44037

- can_split &= !mark_nonssa_use (stmt, op, non_ssa_vars);

44038

+ can_split &= !mark_nonssa_use (stmt, op, op, non_ssa_vars);

44039

}

44040

}

44041

return can_split;

44042

Index: gcc/alias.c

44043

===================================================================

44044

--- a/src/gcc/alias.c (.../tags/gcc_4_8_2_release)

44045

+++ b/src/gcc/alias.c (.../branches/gcc-4_8-branch)

44046

@@ -156,7 +156,9 @@

44047

static alias_set_entry get_alias_set_entry (alias_set_type);

44048

static bool nonoverlapping_component_refs_p (const_rtx, const_rtx);

44049

static tree decl_for_component_ref (tree);

44050

-static int write_dependence_p (const_rtx, const_rtx, int);

44051

+static int write_dependence_p (const_rtx,

44052

+ const_rtx, enum machine_mode, rtx,

44053

+ bool, bool, bool);

44054

44055

static void memory_modified_1 (rtx, const_rtx, void *);

44056

44057

@@ -2558,15 +2560,24 @@

44058

}

44059

44060

/* Returns nonzero if a write to X might alias a previous read from

44061

- (or, if WRITEP is nonzero, a write to) MEM. */

44062

+ (or, if WRITEP is true, a write to) MEM.

44063

+ If X_CANONCALIZED is true, then X_ADDR is the canonicalized address of X,

44064

+ and X_MODE the mode for that access.

44065

+ If MEM_CANONICALIZED is true, MEM is canonicalized. */

44066

44067

static int

44068

-write_dependence_p (const_rtx mem, const_rtx x, int writep)

44069

+write_dependence_p (const_rtx mem,

44070

+ const_rtx x, enum machine_mode x_mode, rtx x_addr,

44071

+ bool mem_canonicalized, bool x_canonicalized, bool writep)

44072

{

44073

- rtx x_addr, mem_addr;

44074

+ rtx mem_addr;

44075

rtx base;

44076

int ret;

44077

44078

+ gcc_checking_assert (x_canonicalized

44079

+ ? (x_addr != NULL_RTX && x_mode != VOIDmode)

44080

+ : (x_addr == NULL_RTX && x_mode == VOIDmode));

44081

+

44082

if (MEM_VOLATILE_P (x) && MEM_VOLATILE_P (mem))

44083

return 1;

44084

44085

@@ -2590,17 +2601,21 @@

44086

if (MEM_ADDR_SPACE (mem) != MEM_ADDR_SPACE (x))

44087

return 1;

44088

44089

- x_addr = XEXP (x, 0);

44090

mem_addr = XEXP (mem, 0);

44091

- if (!((GET_CODE (x_addr) == VALUE

44092

- && GET_CODE (mem_addr) != VALUE

44093

- && reg_mentioned_p (x_addr, mem_addr))

44094

- || (GET_CODE (x_addr) != VALUE

44095

- && GET_CODE (mem_addr) == VALUE

44096

- && reg_mentioned_p (mem_addr, x_addr))))

44097

+ if (!x_addr)

44098

{

44099

- x_addr = get_addr (x_addr);

44100

- mem_addr = get_addr (mem_addr);

44101

+ x_addr = XEXP (x, 0);

44102

+ if (!((GET_CODE (x_addr) == VALUE

44103

+ && GET_CODE (mem_addr) != VALUE

44104

+ && reg_mentioned_p (x_addr, mem_addr))

44105

+ || (GET_CODE (x_addr) != VALUE

44106

+ && GET_CODE (mem_addr) == VALUE

44107

+ && reg_mentioned_p (mem_addr, x_addr))))

44108

+ {

44109

+ x_addr = get_addr (x_addr);

44110

+ if (!mem_canonicalized)

44111

+ mem_addr = get_addr (mem_addr);

44112

+ }

44113

}

44114

44115

if (! writep)

44116

@@ -2616,11 +2631,16 @@

44117

GET_MODE (mem)))

44118

return 0;

44119

44120

- x_addr = canon_rtx (x_addr);

44121

- mem_addr = canon_rtx (mem_addr);

44122

+ if (!x_canonicalized)

44123

+ {

44124

+ x_addr = canon_rtx (x_addr);

44125

+ x_mode = GET_MODE (x);

44126

+ }

44127

+ if (!mem_canonicalized)

44128

+ mem_addr = canon_rtx (mem_addr);

44129

44130

if ((ret = memrefs_conflict_p (SIZE_FOR_MODE (mem), mem_addr,

44131

- SIZE_FOR_MODE (x), x_addr, 0)) != -1)

44132

+ GET_MODE_SIZE (x_mode), x_addr, 0)) != -1)

44133

return ret;

44134

44135

if (nonoverlapping_memrefs_p (x, mem, false))

44136

@@ -2634,15 +2654,33 @@

44137

int

44138

anti_dependence (const_rtx mem, const_rtx x)

44139

{

44140

- return write_dependence_p (mem, x, /*writep=*/0);

44141

+ return write_dependence_p (mem, x, VOIDmode, NULL_RTX,

44142

+ /*mem_canonicalized=*/false,

44143

+ /*x_canonicalized*/false, /*writep=*/false);

44144

}

44145

44146

+/* Likewise, but we already have a canonicalized MEM, and X_ADDR for X.

44147

+ Also, consider X in X_MODE (which might be from an enclosing

44148

+ STRICT_LOW_PART / ZERO_EXTRACT).

44149

+ If MEM_CANONICALIZED is true, MEM is canonicalized. */

44150

+

44151

+int

44152

+canon_anti_dependence (const_rtx mem, bool mem_canonicalized,

44153

+ const_rtx x, enum machine_mode x_mode, rtx x_addr)

44154

+{

44155

+ return write_dependence_p (mem, x, x_mode, x_addr,

44156

+ mem_canonicalized, /*x_canonicalized=*/true,

44157

+ /*writep=*/false);

44158

+}

44159

+

44160

/* Output dependence: X is written after store in MEM takes place. */

44161

44162

int

44163

output_dependence (const_rtx mem, const_rtx x)

44164

{

44165

- return write_dependence_p (mem, x, /*writep=*/1);

44166

+ return write_dependence_p (mem, x, VOIDmode, NULL_RTX,

44167

+ /*mem_canonicalized=*/false,

44168

+ /*x_canonicalized*/false, /*writep=*/true);

44169

}

44170

44171

44172

@@ -2871,17 +2909,14 @@

44173

/* Wipe the reg_seen array clean. */

44174

bitmap_clear (reg_seen);

44175

44176

- /* Mark all hard registers which may contain an address.

44177

- The stack, frame and argument pointers may contain an address.

44178

- An argument register which can hold a Pmode value may contain

44179

- an address even if it is not in BASE_REGS.

44180

+ /* Initialize the alias information for this pass. */

44181

+ for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)

44182

+ if (static_reg_base_value[i])

44183

+ {

44184

+ new_reg_base_value[i] = static_reg_base_value[i];

44185

+ bitmap_set_bit (reg_seen, i);

44186

+ }

44187

44188

- The address expression is VOIDmode for an argument and

44189

- Pmode for other registers. */

44190

-

44191

- memcpy (new_reg_base_value, static_reg_base_value,

44192

- FIRST_PSEUDO_REGISTER * sizeof (rtx));

44193

-

44194

/* Walk the insns adding values to the new_reg_base_value array. */

44195

for (i = 0; i < rpo_cnt; i++)

44196

{

44197

Index: gcc/tree-vect-loop.c

44198

===================================================================

44199

--- a/src/gcc/tree-vect-loop.c (.../tags/gcc_4_8_2_release)

44200

+++ b/src/gcc/tree-vect-loop.c (.../branches/gcc-4_8-branch)

44201

@@ -1537,7 +1537,7 @@

44202

44203

if (!LOOP_VINFO_NITERS_KNOWN_P (loop_vinfo)

44204

|| LOOP_VINFO_INT_NITERS (loop_vinfo) % vectorization_factor != 0

44205

- || LOOP_PEELING_FOR_ALIGNMENT (loop_vinfo))

44206

+ || LOOP_VINFO_PEELING_FOR_GAPS (loop_vinfo))

44207

{

44208

if (dump_enabled_p ())

44209

dump_printf_loc (MSG_NOTE, vect_location, "epilog loop required.");

44210

@@ -2097,6 +2097,12 @@

44211

|| (!check_reduction && flow_loop_nested_p (vect_loop, loop)));

44212

44213

name = PHI_RESULT (phi);

44214

+ /* ??? If there are no uses of the PHI result the inner loop reduction

44215

+ won't be detected as possibly double-reduction by vectorizable_reduction

44216

+ because that tries to walk the PHI arg from the preheader edge which

44217

+ can be constant. See PR60382. */

44218

+ if (has_zero_uses (name))

44219

+ return NULL;

44220

nloop_uses = 0;

44221

FOR_EACH_IMM_USE_FAST (use_p, imm_iter, name)

44222

{

44223

@@ -3115,7 +3121,6 @@

44224

stmt_vec_info stmt_vinfo = vinfo_for_stmt (iv_phi);

44225

loop_vec_info loop_vinfo = STMT_VINFO_LOOP_VINFO (stmt_vinfo);

44226

struct loop *loop = LOOP_VINFO_LOOP (loop_vinfo);

44227

- tree scalar_type;

44228

tree vectype;

44229

int nunits;

44230

edge pe = loop_preheader_edge (loop);

44231

@@ -3122,7 +3127,6 @@

44232

struct loop *iv_loop;

44233

basic_block new_bb;

44234

tree new_vec, vec_init, vec_step, t;

44235

- tree access_fn;

44236

tree new_var;

44237

tree new_name;

44238

gimple init_stmt, induction_phi, new_stmt;

44239

@@ -3130,7 +3134,6 @@

44240

tree init_expr, step_expr;

44241

int vf = LOOP_VINFO_VECT_FACTOR (loop_vinfo);

44242

int i;

44243

- bool ok;

44244

int ncopies;

44245

tree expr;

44246

stmt_vec_info phi_info = vinfo_for_stmt (iv_phi);

44247

@@ -3159,16 +3162,14 @@

44248

latch_e = loop_latch_edge (iv_loop);

44249

loop_arg = PHI_ARG_DEF_FROM_EDGE (iv_phi, latch_e);

44250

44251

- access_fn = analyze_scalar_evolution (iv_loop, PHI_RESULT (iv_phi));

44252

- gcc_assert (access_fn);

44253

- STRIP_NOPS (access_fn);

44254

- ok = vect_is_simple_iv_evolution (iv_loop->num, access_fn,

44255

- &init_expr, &step_expr);

44256

- gcc_assert (ok);

44257

+ step_expr = STMT_VINFO_LOOP_PHI_EVOLUTION_PART (phi_info);

44258

+ gcc_assert (step_expr != NULL_TREE);

44259

+

44260

pe = loop_preheader_edge (iv_loop);

44261

+ init_expr = PHI_ARG_DEF_FROM_EDGE (iv_phi,

44262

+ loop_preheader_edge (iv_loop));

44263

44264

- scalar_type = TREE_TYPE (init_expr);

44265

- vectype = get_vectype_for_scalar_type (scalar_type);

44266

+ vectype = get_vectype_for_scalar_type (TREE_TYPE (init_expr));

44267

resvectype = get_vectype_for_scalar_type (TREE_TYPE (PHI_RESULT (iv_phi)));

44268

gcc_assert (vectype);

44269

nunits = TYPE_VECTOR_SUBPARTS (vectype);

44270

@@ -3177,6 +3178,16 @@

44271

gcc_assert (phi_info);

44272

gcc_assert (ncopies >= 1);

44273

44274

+ /* Convert the step to the desired type. */

44275

+ step_expr = force_gimple_operand (fold_convert (TREE_TYPE (vectype),

44276

+ step_expr),

44277

+ &stmts, true, NULL_TREE);

44278

+ if (stmts)

44279

+ {

44280

+ new_bb = gsi_insert_seq_on_edge_immediate (pe, stmts);

44281

+ gcc_assert (!new_bb);

44282

+ }

44283

+

44284

/* Find the first insertion point in the BB. */

44285

si = gsi_after_labels (bb);

44286

44287

@@ -3186,9 +3197,7 @@

44288

/* iv_loop is nested in the loop to be vectorized. init_expr had already

44289

been created during vectorization of previous stmts. We obtain it

44290

from the STMT_VINFO_VEC_STMT of the defining stmt. */

44291

- tree iv_def = PHI_ARG_DEF_FROM_EDGE (iv_phi,

44292

- loop_preheader_edge (iv_loop));

44293

- vec_init = vect_get_vec_def_for_operand (iv_def, iv_phi, NULL);

44294

+ vec_init = vect_get_vec_def_for_operand (init_expr, iv_phi, NULL);

44295

/* If the initial value is not of proper type, convert it. */

44296

if (!useless_type_conversion_p (vectype, TREE_TYPE (vec_init)))

44297

{

44298

@@ -3211,8 +3220,11 @@

44299

44300

/* iv_loop is the loop to be vectorized. Create:

44301

vec_init = [X, X+S, X+2*S, X+3*S] (S = step_expr, X = init_expr) */

44302

- new_var = vect_get_new_vect_var (scalar_type, vect_scalar_var, "var_");

44303

- new_name = force_gimple_operand (init_expr, &stmts, false, new_var);

44304

+ new_var = vect_get_new_vect_var (TREE_TYPE (vectype),

44305

+ vect_scalar_var, "var_");

44306

+ new_name = force_gimple_operand (fold_convert (TREE_TYPE (vectype),

44307

+ init_expr),

44308

+ &stmts, false, new_var);

44309

if (stmts)

44310

{

44311

new_bb = gsi_insert_seq_on_edge_immediate (pe, stmts);

44312

@@ -3224,9 +3236,7 @@

44313

for (i = 1; i < nunits; i++)

44314

{

44315

/* Create: new_name_i = new_name + step_expr */

44316

- enum tree_code code = POINTER_TYPE_P (scalar_type)

44317

- ? POINTER_PLUS_EXPR : PLUS_EXPR;

44318

- init_stmt = gimple_build_assign_with_ops (code, new_var,

44319

+ init_stmt = gimple_build_assign_with_ops (PLUS_EXPR, new_var,

44320

new_name, step_expr);

44321

new_name = make_ssa_name (new_var, init_stmt);

44322

gimple_assign_set_lhs (init_stmt, new_name);

44323

@@ -3781,8 +3791,12 @@

44324

/* Set phi nodes arguments. */

44325

FOR_EACH_VEC_ELT (reduction_phis, i, phi)

44326

{

44327

- tree vec_init_def = vec_initial_defs[i];

44328

- tree def = vect_defs[i];

44329

+ tree vec_init_def, def;

44330

+ gimple_seq stmts;

44331

+ vec_init_def = force_gimple_operand (vec_initial_defs[i], &stmts,

44332

+ true, NULL_TREE);

44333

+ gsi_insert_seq_on_edge_immediate (loop_preheader_edge (loop), stmts);

44334

+ def = vect_defs[i];

44335

for (j = 0; j < ncopies; j++)

44336

{

44337

/* Set the loop-entry arg of the reduction-phi. */

44338

@@ -5564,8 +5578,9 @@

44339

&& !STMT_VINFO_LIVE_P (stmt_info))

44340

continue;

44341

44342

- if ((TYPE_VECTOR_SUBPARTS (STMT_VINFO_VECTYPE (stmt_info))

44343

- != (unsigned HOST_WIDE_INT) vectorization_factor)

44344

+ if (STMT_VINFO_VECTYPE (stmt_info)

44345

+ && (TYPE_VECTOR_SUBPARTS (STMT_VINFO_VECTYPE (stmt_info))

44346

+ != (unsigned HOST_WIDE_INT) vectorization_factor)

44347

&& dump_enabled_p ())

44348

dump_printf_loc (MSG_NOTE, vect_location, "multiple-types.");

44349

44350

Index: gcc/ipa.c

44351

===================================================================

44352

--- a/src/gcc/ipa.c (.../tags/gcc_4_8_2_release)

44353

+++ b/src/gcc/ipa.c (.../branches/gcc-4_8-branch)

44354

@@ -359,6 +359,8 @@

44355

{

44356

if (file)

44357

fprintf (file, " %s", cgraph_node_name (node));

44358

+ node->alias = false;

44359

+ node->thunk.thunk_p = false;

44360

cgraph_node_remove_callees (node);

44361

ipa_remove_all_references (&node->symbol.ref_list);

44362

changed = true;

44363

Index: gcc/lra-coalesce.c

44364

===================================================================

44365

--- a/src/gcc/lra-coalesce.c (.../tags/gcc_4_8_2_release)

44366

+++ b/src/gcc/lra-coalesce.c (.../branches/gcc-4_8-branch)

44367

@@ -221,9 +221,12 @@

44368

basic_block bb;

44369

rtx mv, set, insn, next, *sorted_moves;

44370

int i, mv_num, sregno, dregno;

44371

+ unsigned int regno;

44372

int coalesced_moves;

44373

int max_regno = max_reg_num ();

44374

bitmap_head involved_insns_bitmap;

44375

+ bitmap_head result_pseudo_vals_bitmap;

44376

+ bitmap_iterator bi;

44377

44378

timevar_push (TV_LRA_COALESCE);

44379

44380

@@ -318,6 +321,34 @@

44381

}

44382

}

44383

}

44384

+ /* If we have situation after inheritance pass:

44385

+

44386

+ r1 <- ... insn originally setting p1

44387

+ i1 <- r1 setting inheritance i1 from reload r1

44388

+ ...

44389

+ ... <- ... p2 ... dead p2

44390

+ ..

44391

+ p1 <- i1

44392

+ r2 <- i1

44393

+ ...<- ... r2 ...

44394

+

44395

+ And we are coalescing p1 and p2 using p1. In this case i1 and p1

44396

+ should have different values, otherwise they can get the same

44397

+ hard reg and this is wrong for insn using p2 before coalescing.

44398

+ So invalidate such inheritance pseudo values. */

44399

+ bitmap_initialize (&result_pseudo_vals_bitmap, &reg_obstack);

44400

+ EXECUTE_IF_SET_IN_BITMAP (&coalesced_pseudos_bitmap, 0, regno, bi)

44401

+ bitmap_set_bit (&result_pseudo_vals_bitmap,

44402

+ lra_reg_info[first_coalesced_pseudo[regno]].val);

44403

+ EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi)

44404

+ if (bitmap_bit_p (&result_pseudo_vals_bitmap, lra_reg_info[regno].val))

44405

+ {

44406

+ lra_set_regno_unique_value (regno);

44407

+ if (lra_dump_file != NULL)

44408

+ fprintf (lra_dump_file,

44409

+ " Make unique value for inheritance r%d\n", regno);

44410

+ }

44411

+ bitmap_clear (&result_pseudo_vals_bitmap);

44412

bitmap_clear (&used_pseudos_bitmap);

44413

bitmap_clear (&involved_insns_bitmap);

44414

bitmap_clear (&coalesced_pseudos_bitmap);

44415

Index: gcc/tree-vect-data-refs.c

44416

===================================================================

44417

--- a/src/gcc/tree-vect-data-refs.c (.../tags/gcc_4_8_2_release)

44418

+++ b/src/gcc/tree-vect-data-refs.c (.../branches/gcc-4_8-branch)

44419

@@ -739,6 +739,13 @@

44420

if (dump_enabled_p ())

44421

dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location,

44422

"dependence distance negative.");

44423

+ /* Record a negative dependence distance to later limit the

44424

+ amount of stmt copying / unrolling we can perform.

44425

+ Only need to handle read-after-write dependence. */

44426

+ if (DR_IS_READ (drb)

44427

+ && (STMT_VINFO_MIN_NEG_DIST (stmtinfo_b) == 0

44428

+ || STMT_VINFO_MIN_NEG_DIST (stmtinfo_b) > (unsigned)dist))

44429

+ STMT_VINFO_MIN_NEG_DIST (stmtinfo_b) = dist;

44430

continue;

44431

}

44432

44433

Index: gcc/gimplify.c

44434

===================================================================

44435

--- a/src/gcc/gimplify.c (.../tags/gcc_4_8_2_release)

44436

+++ b/src/gcc/gimplify.c (.../branches/gcc-4_8-branch)

44437

@@ -2060,6 +2060,9 @@

44438

/* Nonlocal VLAs seen in the current function. */

44439

static struct pointer_set_t *nonlocal_vlas;

44440

44441

+/* The VAR_DECLs created for nonlocal VLAs for debug info purposes. */

44442

+static tree nonlocal_vla_vars;

44443

+

44444

/* Gimplify a VAR_DECL or PARM_DECL. Return GS_OK if we expanded a

44445

DECL_VALUE_EXPR, and it's worth re-examining things. */

44446

44447

@@ -2106,14 +2109,13 @@

44448

ctx = ctx->outer_context;

44449

if (!ctx && !pointer_set_insert (nonlocal_vlas, decl))

44450

{

44451

- tree copy = copy_node (decl), block;

44452

+ tree copy = copy_node (decl);

44453

44454

lang_hooks.dup_lang_specific_decl (copy);

44455

SET_DECL_RTL (copy, 0);

44456

TREE_USED (copy) = 1;

44457

- block = DECL_INITIAL (current_function_decl);

44458

- DECL_CHAIN (copy) = BLOCK_VARS (block);

44459

- BLOCK_VARS (block) = copy;

44460

+ DECL_CHAIN (copy) = nonlocal_vla_vars;

44461

+ nonlocal_vla_vars = copy;

44462

SET_DECL_VALUE_EXPR (copy, unshare_expr (value_expr));

44463

DECL_HAS_VALUE_EXPR_P (copy) = 1;

44464

}

44465

@@ -4369,7 +4371,7 @@

44466

unsigned HOST_WIDE_INT indexi = offset * BITS_PER_UNIT;

44467

tree index = bitsize_int (indexi);

44468

if (offset / part_widthi

44469

- <= TYPE_VECTOR_SUBPARTS (TREE_TYPE (addrtype)))

44470

+ < TYPE_VECTOR_SUBPARTS (TREE_TYPE (addrtype)))

44471

return fold_build3 (BIT_FIELD_REF, type, TREE_OPERAND (addr, 0),

44472

part_width, index);

44473

}

44474

@@ -6131,7 +6133,7 @@

44475

region's REDUCTION clause. */

44476

44477

static bool

44478

-omp_check_private (struct gimplify_omp_ctx *ctx, tree decl)

44479

+omp_check_private (struct gimplify_omp_ctx *ctx, tree decl, bool copyprivate)

44480

{

44481

splay_tree_node n;

44482

44483

@@ -6140,8 +6142,11 @@

44484

ctx = ctx->outer_context;

44485

if (ctx == NULL)

44486

return !(is_global_var (decl)

44487

- /* References might be private, but might be shared too. */

44488

- || lang_hooks.decls.omp_privatize_by_reference (decl));

44489

+ /* References might be private, but might be shared too,

44490

+ when checking for copyprivate, assume they might be

44491

+ private, otherwise assume they might be shared. */

44492

+ || (!copyprivate

44493

+ && lang_hooks.decls.omp_privatize_by_reference (decl)));

44494

44495

n = splay_tree_lookup (ctx->variables, (splay_tree_key) decl);

44496

if (n != NULL)

44497

@@ -6267,12 +6272,36 @@

44498

remove = true;

44499

break;

44500

}

44501

+ if (OMP_CLAUSE_CODE (c) == OMP_CLAUSE_COPYPRIVATE

44502

+ && !remove

44503

+ && !omp_check_private (ctx, decl, true))

44504

+ {

44505

+ remove = true;

44506

+ if (is_global_var (decl))

44507

+ {

44508

+ if (DECL_THREAD_LOCAL_P (decl))

44509

+ remove = false;

44510

+ else if (DECL_HAS_VALUE_EXPR_P (decl))

44511

+ {

44512

+ tree value = get_base_address (DECL_VALUE_EXPR (decl));

44513

+

44514

+ if (value

44515

+ && DECL_P (value)

44516

+ && DECL_THREAD_LOCAL_P (value))

44517

+ remove = false;

44518

+ }

44519

+ }

44520

+ if (remove)

44521

+ error_at (OMP_CLAUSE_LOCATION (c),

44522

+ "copyprivate variable %qE is not threadprivate"

44523

+ " or private in outer context", DECL_NAME (decl));

44524

+ }

44525

do_notice:

44526

if (outer_ctx)

44527

omp_notice_variable (outer_ctx, decl, true);

44528

if (check_non_private

44529

&& region_type == ORT_WORKSHARE

44530

- && omp_check_private (ctx, decl))

44531

+ && omp_check_private (ctx, decl, false))

44532

{

44533

error ("%s variable %qE is private in outer context",

44534

check_non_private, DECL_NAME (decl));

44535

@@ -8261,6 +8290,21 @@

44536

44537

if (nonlocal_vlas)

44538

{

44539

+ if (nonlocal_vla_vars)

44540

+ {

44541

+ /* tree-nested.c may later on call declare_vars (..., true);

44542

+ which relies on BLOCK_VARS chain to be the tail of the

44543

+ gimple_bind_vars chain. Ensure we don't violate that

44544

+ assumption. */

44545

+ if (gimple_bind_block (outer_bind)

44546

+ == DECL_INITIAL (current_function_decl))

44547

+ declare_vars (nonlocal_vla_vars, outer_bind, true);

44548

+ else

44549

+ BLOCK_VARS (DECL_INITIAL (current_function_decl))

44550

+ = chainon (BLOCK_VARS (DECL_INITIAL (current_function_decl)),

44551

+ nonlocal_vla_vars);

44552

+ nonlocal_vla_vars = NULL_TREE;

44553

+ }

44554

pointer_set_destroy (nonlocal_vlas);

44555

nonlocal_vlas = NULL;

44556

}

44557

@@ -8588,6 +8632,8 @@

44558

gsi_insert_after (gsi_p, post_stmt, GSI_NEW_STMT);

44559

44560

pop_gimplify_context (NULL);

44561

+

44562

+ update_stmt (stmt);

44563

}

44564

44565

/* Expand EXPR to list of gimple statements STMTS. GIMPLE_TEST_F specifies

44566

Index: gcc/graphite-scop-detection.c

44567

===================================================================

44568

--- a/src/gcc/graphite-scop-detection.c (.../tags/gcc_4_8_2_release)

44569

+++ b/src/gcc/graphite-scop-detection.c (.../branches/gcc-4_8-branch)

44570

@@ -203,7 +203,14 @@

44571

44572

switch (TREE_CODE (scev))

44573

{

44574

+ case NEGATE_EXPR:

44575

+ case BIT_NOT_EXPR:

44576

+ CASE_CONVERT:

44577

+ case NON_LVALUE_EXPR:

44578

+ return graphite_can_represent_scev (TREE_OPERAND (scev, 0));

44579

+

44580

case PLUS_EXPR:

44581

+ case POINTER_PLUS_EXPR:

44582

case MINUS_EXPR:

44583

return graphite_can_represent_scev (TREE_OPERAND (scev, 0))

44584

&& graphite_can_represent_scev (TREE_OPERAND (scev, 1));

44585

@@ -225,6 +232,7 @@

44586

if (!evolution_function_right_is_integer_cst (scev)

44587

|| !graphite_can_represent_init (scev))

44588

return false;

44589

+ return graphite_can_represent_scev (CHREC_LEFT (scev));

44590

44591

default:

44592

break;

44593

@@ -231,7 +239,8 @@

44594

}

44595

44596

/* Only affine functions can be represented. */

44597

- if (!scev_is_linear_expression (scev))

44598

+ if (tree_contains_chrecs (scev, NULL)

44599

+ || !scev_is_linear_expression (scev))

44600

return false;

44601

44602

return true;

44603

@@ -330,13 +339,10 @@

44604

44605

case GIMPLE_COND:

44606

{

44607

- tree op;

44608

- ssa_op_iter op_iter;

44609

- enum tree_code code = gimple_cond_code (stmt);

44610

-

44611

/* We can handle all binary comparisons. Inequalities are

44612

also supported as they can be represented with union of

44613

polyhedra. */

44614

+ enum tree_code code = gimple_cond_code (stmt);

44615

if (!(code == LT_EXPR

44616

|| code == GT_EXPR

44617

|| code == LE_EXPR

44618

@@ -345,11 +351,14 @@

44619

|| code == NE_EXPR))

44620

return false;

44621

44622

- FOR_EACH_SSA_TREE_OPERAND (op, stmt, op_iter, SSA_OP_ALL_USES)

44623

- if (!graphite_can_represent_expr (scop_entry, loop, op)

44624

- /* We can not handle REAL_TYPE. Failed for pr39260. */

44625

- || TREE_CODE (TREE_TYPE (op)) == REAL_TYPE)

44626

- return false;

44627

+ for (unsigned i = 0; i < 2; ++i)

44628

+ {

44629

+ tree op = gimple_op (stmt, i);

44630

+ if (!graphite_can_represent_expr (scop_entry, loop, op)

44631

+ /* We can not handle REAL_TYPE. Failed for pr39260. */

44632

+ || TREE_CODE (TREE_TYPE (op)) == REAL_TYPE)

44633

+ return false;

44634

+ }

44635

44636

return true;

44637

}

44638

Index: gcc/lra-constraints.c

44639

===================================================================

44640

--- a/src/gcc/lra-constraints.c (.../tags/gcc_4_8_2_release)

44641

+++ b/src/gcc/lra-constraints.c (.../branches/gcc-4_8-branch)

44642

@@ -1156,6 +1156,8 @@

44643

enum machine_mode mode;

44644

rtx reg, new_reg;

44645

rtx operand = *curr_id->operand_loc[nop];

44646

+ enum reg_class regclass;

44647

+ enum op_type type;

44648

44649

before = after = NULL_RTX;

44650

44651

@@ -1164,6 +1166,7 @@

44652

44653

mode = GET_MODE (operand);

44654

reg = SUBREG_REG (operand);

44655

+ type = curr_static_id->operand[nop].type;

44656

/* If we change address for paradoxical subreg of memory, the

44657

address might violate the necessary alignment or the access might

44658

be slow. So take this into consideration. We should not worry

44659

@@ -1236,6 +1239,55 @@

44660

"Inserting subreg reload");

44661

return true;

44662

}

44663

+ /* Force a reload for a paradoxical subreg. For paradoxical subreg,

44664

+ IRA allocates hardreg to the inner pseudo reg according to its mode

44665

+ instead of the outermode, so the size of the hardreg may not be enough

44666

+ to contain the outermode operand, in that case we may need to insert

44667

+ reload for the reg. For the following two types of paradoxical subreg,

44668

+ we need to insert reload:

44669

+ 1. If the op_type is OP_IN, and the hardreg could not be paired with

44670

+ other hardreg to contain the outermode operand

44671

+ (checked by in_hard_reg_set_p), we need to insert the reload.

44672

+ 2. If the op_type is OP_OUT or OP_INOUT. */

44673

+ else if (REG_P (reg)

44674

+ && REGNO (reg) >= FIRST_PSEUDO_REGISTER

44675

+ && (hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0

44676

+ && (hard_regno_nregs[hard_regno][GET_MODE (reg)]

44677

+ < hard_regno_nregs[hard_regno][mode])

44678

+ && (regclass = lra_get_allocno_class (REGNO (reg)))

44679

+ && (type != OP_IN

44680

+ || !in_hard_reg_set_p (reg_class_contents[regclass],

44681

+ mode, hard_regno)))

44682

+ {

44683

+ /* The class will be defined later in curr_insn_transform. */

44684

+ enum reg_class rclass

44685

+ = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS);

44686

+ rtx subreg;

44687

+

44688

+ new_reg = lra_create_new_reg_with_unique_value (mode, reg, rclass,

44689

+ "paradoxical subreg");

44690

+ PUT_MODE (new_reg, mode);

44691

+ subreg = simplify_gen_subreg (GET_MODE (reg), new_reg, mode, 0);

44692

+ if (type != OP_OUT)

44693

+ {

44694

+ push_to_sequence (before);

44695

+ lra_emit_move (subreg, reg);

44696

+ before = get_insns ();

44697

+ end_sequence ();

44698

+ }

44699

+ if (type != OP_IN)

44700

+ {

44701

+ start_sequence ();

44702

+ lra_emit_move (reg, subreg);

44703

+ emit_insn (after);

44704

+ after = get_insns ();

44705

+ end_sequence ();

44706

+ }

44707

+ SUBREG_REG (operand) = new_reg;

44708

+ lra_process_new_insns (curr_insn, before, after,

44709

+ "Inserting paradoxical subreg reload");

44710

+ return true;

44711

+ }

44712

return false;

44713

}

44714

44715

Index: gcc/calls.c

44716

===================================================================

44717

--- a/src/gcc/calls.c (.../tags/gcc_4_8_2_release)

44718

+++ b/src/gcc/calls.c (.../branches/gcc-4_8-branch)

44719

@@ -983,6 +983,7 @@

44720

44721

for (i = 0; i < num_actuals; i++)

44722

if (args[i].reg != 0 && ! args[i].pass_on_stack

44723

+ && GET_CODE (args[i].reg) != PARALLEL

44724

&& args[i].mode == BLKmode

44725

&& MEM_P (args[i].value)

44726

&& (MEM_ALIGN (args[i].value)

44727

@@ -1327,6 +1328,7 @@

44728

#else

44729

args[i].reg != 0,

44730

#endif

44731

+ reg_parm_stack_space,

44732

args[i].pass_on_stack ? 0 : args[i].partial,

44733

fndecl, args_size, &args[i].locate);

44734

#ifdef BLOCK_REG_PADDING

44735

@@ -3171,7 +3173,9 @@

44736

group load/store machinery below. */

44737

if (!structure_value_addr

44738

&& !pcc_struct_value

44739

+ && TYPE_MODE (rettype) != VOIDmode

44740

&& TYPE_MODE (rettype) != BLKmode

44741

+ && REG_P (valreg)

44742

&& targetm.calls.return_in_msb (rettype))

44743

{

44744

if (shift_return_value (TYPE_MODE (rettype), false, valreg))

44745

@@ -3734,7 +3738,8 @@

44746

#else

44747

argvec[count].reg != 0,

44748

#endif

44749

- 0, NULL_TREE, &args_size, &argvec[count].locate);

44750

+ reg_parm_stack_space, 0,

44751

+ NULL_TREE, &args_size, &argvec[count].locate);

44752

44753

if (argvec[count].reg == 0 || argvec[count].partial != 0

44754

|| reg_parm_stack_space > 0)

44755

@@ -3821,7 +3826,7 @@

44756

#else

44757

argvec[count].reg != 0,

44758

#endif

44759

- argvec[count].partial,

44760

+ reg_parm_stack_space, argvec[count].partial,

44761

NULL_TREE, &args_size, &argvec[count].locate);

44762

args_size.constant += argvec[count].locate.size.constant;

44763

gcc_assert (!argvec[count].locate.size.var);

44764

Index: gcc/tree-dfa.c

44765

===================================================================

44766

--- a/src/gcc/tree-dfa.c (.../tags/gcc_4_8_2_release)

44767

+++ b/src/gcc/tree-dfa.c (.../branches/gcc-4_8-branch)

44768

@@ -386,7 +386,6 @@

44769

double_int bit_offset = double_int_zero;

44770

HOST_WIDE_INT hbit_offset;

44771

bool seen_variable_array_ref = false;

44772

- tree base_type;

44773

44774

/* First get the final access size from just the outermost expression. */

44775

if (TREE_CODE (exp) == COMPONENT_REF)

44776

@@ -417,8 +416,6 @@

44777

and find the ultimate containing object. */

44778

while (1)

44779

{

44780

- base_type = TREE_TYPE (exp);

44781

-

44782

switch (TREE_CODE (exp))

44783

{

44784

case BIT_FIELD_REF:

44785

@@ -543,7 +540,38 @@

44786

case VIEW_CONVERT_EXPR:

44787

break;

44788

44789

+ case TARGET_MEM_REF:

44790

+ /* Via the variable index or index2 we can reach the

44791

+ whole object. Still hand back the decl here. */

44792

+ if (TREE_CODE (TMR_BASE (exp)) == ADDR_EXPR

44793

+ && (TMR_INDEX (exp) || TMR_INDEX2 (exp)))

44794

+ {

44795

+ exp = TREE_OPERAND (TMR_BASE (exp), 0);

44796

+ bit_offset = double_int_zero;

44797

+ maxsize = -1;

44798

+ goto done;

44799

+ }

44800

+ /* Fallthru. */

44801

case MEM_REF:

44802

+ /* We need to deal with variable arrays ending structures such as

44803

+ struct { int length; int a[1]; } x; x.a[d]

44804

+ struct { struct { int a; int b; } a[1]; } x; x.a[d].a

44805

+ struct { struct { int a[1]; } a[1]; } x; x.a[0][d], x.a[d][0]

44806

+ struct { int len; union { int a[1]; struct X x; } u; } x; x.u.a[d]

44807

+ where we do not know maxsize for variable index accesses to

44808

+ the array. The simplest way to conservatively deal with this

44809

+ is to punt in the case that offset + maxsize reaches the

44810

+ base type boundary. This needs to include possible trailing

44811

+ padding that is there for alignment purposes. */

44812

+ if (seen_variable_array_ref

44813

+ && maxsize != -1

44814

+ && (!bit_offset.fits_shwi ()

44815

+ || !host_integerp (TYPE_SIZE (TREE_TYPE (exp)), 1)

44816

+ || (bit_offset.to_shwi () + maxsize

44817

+ == (HOST_WIDE_INT) TREE_INT_CST_LOW

44818

+ (TYPE_SIZE (TREE_TYPE (exp))))))

44819

+ maxsize = -1;

44820

+

44821

/* Hand back the decl for MEM[&decl, off]. */

44822

if (TREE_CODE (TREE_OPERAND (exp, 0)) == ADDR_EXPR)

44823

{

44824

@@ -565,37 +593,6 @@

44825

}

44826

goto done;

44827

44828

- case TARGET_MEM_REF:

44829

- /* Hand back the decl for MEM[&decl, off]. */

44830

- if (TREE_CODE (TMR_BASE (exp)) == ADDR_EXPR)

44831

- {

44832

- /* Via the variable index or index2 we can reach the

44833

- whole object. */

44834

- if (TMR_INDEX (exp) || TMR_INDEX2 (exp))

44835

- {

44836

- exp = TREE_OPERAND (TMR_BASE (exp), 0);

44837

- bit_offset = double_int_zero;

44838

- maxsize = -1;

44839

- goto done;

44840

- }

44841

- if (integer_zerop (TMR_OFFSET (exp)))

44842

- exp = TREE_OPERAND (TMR_BASE (exp), 0);

44843

- else

44844

- {

44845

- double_int off = mem_ref_offset (exp);

44846

- off = off.alshift (BITS_PER_UNIT == 8

44847

- ? 3 : exact_log2 (BITS_PER_UNIT),

44848

- HOST_BITS_PER_DOUBLE_INT);

44849

- off += bit_offset;

44850

- if (off.fits_shwi ())

44851

- {

44852

- bit_offset = off;

44853

- exp = TREE_OPERAND (TMR_BASE (exp), 0);

44854

- }

44855

- }

44856

- }

44857

- goto done;

44858

-

44859

default:

44860

goto done;

44861

}

44862

@@ -602,8 +599,18 @@

44863

44864

exp = TREE_OPERAND (exp, 0);

44865

}

44866

+

44867

+ /* We need to deal with variable arrays ending structures. */

44868

+ if (seen_variable_array_ref

44869

+ && maxsize != -1

44870

+ && (!bit_offset.fits_shwi ()

44871

+ || !host_integerp (TYPE_SIZE (TREE_TYPE (exp)), 1)

44872

+ || (bit_offset.to_shwi () + maxsize

44873

+ == (HOST_WIDE_INT)

44874

+ TREE_INT_CST_LOW (TYPE_SIZE (TREE_TYPE (exp))))))

44875

+ maxsize = -1;

44876

+

44877

done:

44878

-

44879

if (!bit_offset.fits_shwi ())

44880

{

44881

*poffset = 0;

44882

@@ -615,24 +622,6 @@

44883

44884

hbit_offset = bit_offset.to_shwi ();

44885

44886

- /* We need to deal with variable arrays ending structures such as

44887

- struct { int length; int a[1]; } x; x.a[d]

44888

- struct { struct { int a; int b; } a[1]; } x; x.a[d].a

44889

- struct { struct { int a[1]; } a[1]; } x; x.a[0][d], x.a[d][0]

44890

- struct { int len; union { int a[1]; struct X x; } u; } x; x.u.a[d]

44891

- where we do not know maxsize for variable index accesses to

44892

- the array. The simplest way to conservatively deal with this

44893

- is to punt in the case that offset + maxsize reaches the

44894

- base type boundary. This needs to include possible trailing padding

44895

- that is there for alignment purposes. */

44896

-

44897

- if (seen_variable_array_ref

44898

- && maxsize != -1

44899

- && (!host_integerp (TYPE_SIZE (base_type), 1)

44900

- || (hbit_offset + maxsize

44901

- == (signed) TREE_INT_CST_LOW (TYPE_SIZE (base_type)))))

44902

- maxsize = -1;

44903

-

44904

/* In case of a decl or constant base object we can do better. */

44905

44906

if (DECL_P (exp))

44907

Index: gcc/gimple-fold.c

44908

===================================================================

44909

--- a/src/gcc/gimple-fold.c (.../tags/gcc_4_8_2_release)

44910

+++ b/src/gcc/gimple-fold.c (.../branches/gcc-4_8-branch)

44911

@@ -178,7 +178,7 @@

44912

/* Make sure we create a cgraph node for functions we'll reference.

44913

They can be non-existent if the reference comes from an entry

44914

of an external vtable for example. */

44915

- cgraph_get_create_node (base);

44916

+ cgraph_get_create_real_symbol_node (base);

44917

}

44918

/* Fixup types in global initializers. */

44919

if (TREE_TYPE (TREE_TYPE (cval)) != TREE_TYPE (TREE_OPERAND (cval, 0)))

44920

@@ -866,6 +866,7 @@

44921

break;

44922

case BUILT_IN_STRCPY:

44923

case BUILT_IN_STRNCPY:

44924

+ case BUILT_IN_STRCAT:

44925

arg_idx = 1;

44926

type = 0;

44927

break;

44928

@@ -941,6 +942,13 @@

44929

val[1]);

44930

break;

44931

44932

+ case BUILT_IN_STRCAT:

44933

+ if (val[1] && is_gimple_val (val[1]) && nargs == 2)

44934

+ result = fold_builtin_strcat (loc, gimple_call_arg (stmt, 0),

44935

+ gimple_call_arg (stmt, 1),

44936

+ val[1]);

44937

+ break;

44938

+

44939

case BUILT_IN_FPUTS:

44940

if (nargs == 2)

44941

result = fold_builtin_fputs (loc, gimple_call_arg (stmt, 0),

44942

Index: gcc/cfgexpand.c

44943

===================================================================

44944

--- a/src/gcc/cfgexpand.c (.../tags/gcc_4_8_2_release)

44945

+++ b/src/gcc/cfgexpand.c (.../branches/gcc-4_8-branch)

44946

@@ -331,7 +331,7 @@

44947

enter its partition number into bitmap DATA. */

44948

44949

static bool

44950

-visit_op (gimple stmt ATTRIBUTE_UNUSED, tree op, void *data)

44951

+visit_op (gimple, tree op, tree, void *data)

44952

{

44953

bitmap active = (bitmap)data;

44954

op = get_base_address (op);

44955

@@ -351,7 +351,7 @@

44956

from bitmap DATA. */

44957

44958

static bool

44959

-visit_conflict (gimple stmt ATTRIBUTE_UNUSED, tree op, void *data)

44960

+visit_conflict (gimple, tree op, tree, void *data)

44961

{

44962

bitmap active = (bitmap)data;

44963

op = get_base_address (op);

44964

@@ -385,7 +385,7 @@

44965

edge e;

44966

edge_iterator ei;

44967

gimple_stmt_iterator gsi;

44968

- bool (*visit)(gimple, tree, void *);

44969

+ walk_stmt_load_store_addr_fn visit;

44970

44971

bitmap_clear (work);

44972

FOR_EACH_EDGE (e, ei, bb->preds)

44973

@@ -4707,14 +4707,18 @@

44974

if (e->insns.r)

44975

{

44976

rebuild_jump_labels_chain (e->insns.r);

44977

- /* Avoid putting insns before parm_birth_insn. */

44978

+ /* Put insns after parm birth, but before

44979

+ NOTE_INSNS_FUNCTION_BEG. */

44980

if (e->src == ENTRY_BLOCK_PTR

44981

- && single_succ_p (ENTRY_BLOCK_PTR)

44982

- && parm_birth_insn)

44983

+ && single_succ_p (ENTRY_BLOCK_PTR))

44984

{

44985

rtx insns = e->insns.r;

44986

e->insns.r = NULL_RTX;

44987

- emit_insn_after_noloc (insns, parm_birth_insn, e->dest);

44988

+ if (NOTE_P (parm_birth_insn)

44989

+ && NOTE_KIND (parm_birth_insn) == NOTE_INSN_FUNCTION_BEG)

44990

+ emit_insn_before_noloc (insns, parm_birth_insn, e->dest);

44991

+ else

44992

+ emit_insn_after_noloc (insns, parm_birth_insn, e->dest);

44993

}

44994

else

44995

commit_one_edge_insertion (e);

44996

Index: gcc/cselib.c

44997

===================================================================

44998

--- a/src/gcc/cselib.c (.../tags/gcc_4_8_2_release)

44999

+++ b/src/gcc/cselib.c (.../branches/gcc-4_8-branch)

45000

@@ -2260,8 +2260,8 @@

45001

continue;

45002

}

45003

if (num_mems < PARAM_VALUE (PARAM_MAX_CSELIB_MEMORY_LOCATIONS)

45004

- && ! canon_true_dependence (mem_rtx, GET_MODE (mem_rtx),

45005

- mem_addr, x, NULL_RTX))

45006

+ && ! canon_anti_dependence (x, false, mem_rtx,

45007

+ GET_MODE (mem_rtx), mem_addr))

45008

{

45009

has_mem = true;

45010

num_mems++;

45011

Index: gcc/tree-cfgcleanup.c

45012

===================================================================

45013

--- a/src/gcc/tree-cfgcleanup.c (.../tags/gcc_4_8_2_release)

45014

+++ b/src/gcc/tree-cfgcleanup.c (.../branches/gcc-4_8-branch)

45015

@@ -539,9 +539,6 @@

45016

update_stmt (stmt);

45017

changed = true;

45018

}

45019

- /* Similarly remove VDEF if there is any. */

45020

- else if (gimple_vdef (stmt))

45021

- update_stmt (stmt);

45022

return changed;

45023

}

45024

45025

Index: gcc/tree-ssa-pre.c

45026

===================================================================

45027

--- a/src/gcc/tree-ssa-pre.c (.../tags/gcc_4_8_2_release)

45028

+++ b/src/gcc/tree-ssa-pre.c (.../branches/gcc-4_8-branch)

45029

@@ -3664,6 +3664,12 @@

45030

if (dump_file && dump_flags & TDF_DETAILS)

45031

fprintf (dump_file, "Starting insert iteration %d\n", num_iterations);

45032

new_stuff = insert_aux (ENTRY_BLOCK_PTR);

45033

+

45034

+ /* Clear the NEW sets before the next iteration. We have already

45035

+ fully propagated its contents. */

45036

+ if (new_stuff)

45037

+ FOR_ALL_BB (bb)

45038

+ bitmap_set_free (NEW_SETS (bb));

45039

}

45040

statistics_histogram_event (cfun, "insert iterations", num_iterations);

45041

}

45042

Index: gcc/cfgcleanup.c

45043

===================================================================

45044

--- a/src/gcc/cfgcleanup.c (.../tags/gcc_4_8_2_release)

45045

+++ b/src/gcc/cfgcleanup.c (.../branches/gcc-4_8-branch)

45046

@@ -1293,7 +1293,6 @@

45047

{

45048

rtx i1, i2, last1, last2, afterlast1, afterlast2;

45049

int ninsns = 0;

45050

- rtx p1;

45051

enum replace_direction dir, last_dir, afterlast_dir;

45052

bool follow_fallthru, did_fallthru;

45053

45054

@@ -1321,8 +1320,9 @@

45055

|| (returnjump_p (i2) && !side_effects_p (PATTERN (i2))))

45056

{

45057

last2 = i2;

45058

- /* Count everything except for unconditional jump as insn. */

45059

- if (!simplejump_p (i2) && !returnjump_p (i2) && last1)

45060

+ /* Count everything except for unconditional jump as insn.

45061

+ Don't count any jumps if dir_p is NULL. */

45062

+ if (!simplejump_p (i2) && !returnjump_p (i2) && last1 && dir_p)

45063

ninsns++;

45064

i2 = PREV_INSN (i2);

45065

}

45066

@@ -1373,8 +1373,8 @@

45067

last1 = i1, last2 = i2;

45068

afterlast_dir = last_dir;

45069

last_dir = dir;

45070

- p1 = PATTERN (i1);

45071

- if (!(GET_CODE (p1) == USE || GET_CODE (p1) == CLOBBER))

45072

+ if (GET_CODE (PATTERN (i1)) != USE

45073

+ && GET_CODE (PATTERN (i1)) != CLOBBER)

45074

ninsns++;

45075

}

45076

45077

@@ -1420,7 +1420,8 @@

45078

/* Like flow_find_cross_jump, except start looking for a matching sequence from

45079

the head of the two blocks. Do not include jumps at the end.

45080

If STOP_AFTER is nonzero, stop after finding that many matching

45081

- instructions. */

45082

+ instructions. If STOP_AFTER is zero, count all INSN_P insns, if it is

45083

+ non-zero, only count active insns. */

45084

45085

int

45086

flow_find_head_matching_sequence (basic_block bb1, basic_block bb2, rtx *f1,

45087

@@ -1492,7 +1493,10 @@

45088

45089

beforelast1 = last1, beforelast2 = last2;

45090

last1 = i1, last2 = i2;

45091

- ninsns++;

45092

+ if (!stop_after

45093

+ || (GET_CODE (PATTERN (i1)) != USE

45094

+ && GET_CODE (PATTERN (i1)) != CLOBBER))

45095

+ ninsns++;

45096

}

45097

45098

if (i1 == BB_END (bb1) || i2 == BB_END (bb2)

45099

Index: gcc/simplify-rtx.c

45100

===================================================================

45101

--- a/src/gcc/simplify-rtx.c (.../tags/gcc_4_8_2_release)

45102

+++ b/src/gcc/simplify-rtx.c (.../branches/gcc-4_8-branch)

45103

@@ -639,11 +639,16 @@

45104

XEXP (op, 0), origmode);

45105

}

45106

45107

- /* Simplify (truncate:SI (op:DI (x:DI) (y:DI)))

45108

- to (op:SI (truncate:SI (x:DI)) (truncate:SI (x:DI))). */

45109

- if (GET_CODE (op) == PLUS

45110

- || GET_CODE (op) == MINUS

45111

- || GET_CODE (op) == MULT)

45112

+ /* If the machine can perform operations in the truncated mode, distribute

45113

+ the truncation, i.e. simplify (truncate:QI (op:SI (x:SI) (y:SI))) into

45114

+ (op:QI (truncate:QI (x:SI)) (truncate:QI (y:SI))). */

45115

+ if (1

45116

+#ifdef WORD_REGISTER_OPERATIONS

45117

+ && precision >= BITS_PER_WORD

45118

+#endif

45119

+ && (GET_CODE (op) == PLUS

45120

+ || GET_CODE (op) == MINUS

45121

+ || GET_CODE (op) == MULT))

45122

{

45123

rtx op0 = simplify_gen_unary (TRUNCATE, mode, XEXP (op, 0), op_mode);

45124

if (op0)

45125

Index: gcc/tree-ssa-live.c

45126

===================================================================

45127

--- a/src/gcc/tree-ssa-live.c (.../tags/gcc_4_8_2_release)

45128

+++ b/src/gcc/tree-ssa-live.c (.../branches/gcc-4_8-branch)

45129

@@ -394,7 +394,8 @@

45130

{

45131

/* When a global var becomes used for the first time also walk its

45132

initializer (non global ones don't have any). */

45133

- if (set_is_used (t) && is_global_var (t))

45134

+ if (set_is_used (t) && is_global_var (t)

45135

+ && DECL_CONTEXT (t) == current_function_decl)

45136

mark_all_vars_used (&DECL_INITIAL (t));

45137

}

45138

/* remove_unused_scope_block_p requires information about labels

45139

Index: gcc/tree-sra.c

45140

===================================================================

45141

--- a/src/gcc/tree-sra.c (.../tags/gcc_4_8_2_release)

45142

+++ b/src/gcc/tree-sra.c (.../branches/gcc-4_8-branch)

45143

@@ -1161,8 +1161,7 @@

45144

GIMPLE_ASM operands with memory constrains which cannot be scalarized. */

45145

45146

static bool

45147

-asm_visit_addr (gimple stmt ATTRIBUTE_UNUSED, tree op,

45148

- void *data ATTRIBUTE_UNUSED)

45149

+asm_visit_addr (gimple, tree op, tree, void *)

45150

{

45151

op = get_base_address (op);

45152

if (op

45153

@@ -2890,6 +2889,10 @@

45154

lacc);

45155

else

45156

drhs = NULL_TREE;

45157

+ if (drhs

45158

+ && !useless_type_conversion_p (lacc->type, TREE_TYPE (drhs)))

45159

+ drhs = fold_build1_loc (loc, VIEW_CONVERT_EXPR,

45160

+ lacc->type, drhs);

45161

ds = gimple_build_debug_bind (get_access_replacement (lacc),

45162

drhs, gsi_stmt (*old_gsi));

45163

gsi_insert_after (new_gsi, ds, GSI_NEW_STMT);

45164

@@ -4868,6 +4871,14 @@

45165

return false;

45166

}

45167

45168

+ if (!opt_for_fn (node->symbol.decl, optimize)

45169

+ || !opt_for_fn (node->symbol.decl, flag_ipa_sra))

45170

+ {

45171

+ if (dump_file)

45172

+ fprintf (dump_file, "Function not optimized.\n");

45173

+ return false;

45174

+ }

45175

+

45176

if (DECL_VIRTUAL_P (current_function_decl))

45177

{

45178

if (dump_file)

45179

Index: gcc/tree-predcom.c

45180

===================================================================

45181

--- a/src/gcc/tree-predcom.c (.../tags/gcc_4_8_2_release)

45182

+++ b/src/gcc/tree-predcom.c (.../branches/gcc-4_8-branch)

45183

@@ -1323,90 +1323,43 @@

45184

gsi_insert_after (&bsi, new_stmt, GSI_NEW_STMT);

45185

}

45186

45187

-/* Returns the reference to the address of REF in the ITER-th iteration of

45188

- LOOP, or NULL if we fail to determine it (ITER may be negative). We

45189

- try to preserve the original shape of the reference (not rewrite it

45190

- as an indirect ref to the address), to make tree_could_trap_p in

45191

- prepare_initializers_chain return false more often. */

45192

+/* Returns a memory reference to DR in the ITER-th iteration of

45193

+ the loop it was analyzed in. Append init stmts to STMTS. */

45194

45195

-static tree

45196

-ref_at_iteration (struct loop *loop, tree ref, int iter)

45197

+static tree

45198

+ref_at_iteration (data_reference_p dr, int iter, gimple_seq *stmts)

45199

{

45200

- tree idx, *idx_p, type, val, op0 = NULL_TREE, ret;

45201

- affine_iv iv;

45202

- bool ok;

45203

-

45204

- if (handled_component_p (ref))

45205

+ tree off = DR_OFFSET (dr);

45206

+ tree coff = DR_INIT (dr);

45207

+ if (iter == 0)

45208

+ ;

45209

+ else if (TREE_CODE (DR_STEP (dr)) == INTEGER_CST)

45210

+ coff = size_binop (PLUS_EXPR, coff,

45211

+ size_binop (MULT_EXPR, DR_STEP (dr), ssize_int (iter)));

45212

+ else

45213

+ off = size_binop (PLUS_EXPR, off,

45214

+ size_binop (MULT_EXPR, DR_STEP (dr), ssize_int (iter)));

45215

+ tree addr = fold_build_pointer_plus (DR_BASE_ADDRESS (dr), off);

45216

+ addr = force_gimple_operand_1 (addr, stmts, is_gimple_mem_ref_addr,

45217

+ NULL_TREE);

45218

+ tree alias_ptr = fold_convert (reference_alias_ptr_type (DR_REF (dr)), coff);

45219

+ /* While data-ref analysis punts on bit offsets it still handles

45220

+ bitfield accesses at byte boundaries. Cope with that. Note that

45221

+ we cannot simply re-apply the outer COMPONENT_REF because the

45222

+ byte-granular portion of it is already applied via DR_INIT and

45223

+ DR_OFFSET, so simply build a BIT_FIELD_REF knowing that the bits

45224

+ start at offset zero. */

45225

+ if (TREE_CODE (DR_REF (dr)) == COMPONENT_REF

45226

+ && DECL_BIT_FIELD (TREE_OPERAND (DR_REF (dr), 1)))

45227

{

45228

- op0 = ref_at_iteration (loop, TREE_OPERAND (ref, 0), iter);

45229

- if (!op0)

45230

- return NULL_TREE;

45231

+ tree field = TREE_OPERAND (DR_REF (dr), 1);

45232

+ return build3 (BIT_FIELD_REF, TREE_TYPE (DR_REF (dr)),

45233

+ build2 (MEM_REF, DECL_BIT_FIELD_TYPE (field),

45234

+ addr, alias_ptr),

45235

+ DECL_SIZE (field), bitsize_zero_node);

45236

}

45237

- else if (!INDIRECT_REF_P (ref)

45238

- && TREE_CODE (ref) != MEM_REF)

45239

- return unshare_expr (ref);

45240

-

45241

- if (TREE_CODE (ref) == MEM_REF)

45242

- {

45243

- ret = unshare_expr (ref);

45244

- idx = TREE_OPERAND (ref, 0);

45245

- idx_p = &TREE_OPERAND (ret, 0);

45246

- }

45247

- else if (TREE_CODE (ref) == COMPONENT_REF)

45248

- {

45249

- /* Check that the offset is loop invariant. */

45250

- if (TREE_OPERAND (ref, 2)

45251

- && !expr_invariant_in_loop_p (loop, TREE_OPERAND (ref, 2)))

45252

- return NULL_TREE;

45253

-

45254

- return build3 (COMPONENT_REF, TREE_TYPE (ref), op0,

45255

- unshare_expr (TREE_OPERAND (ref, 1)),

45256

- unshare_expr (TREE_OPERAND (ref, 2)));

45257

- }

45258

- else if (TREE_CODE (ref) == ARRAY_REF)

45259

- {

45260

- /* Check that the lower bound and the step are loop invariant. */

45261

- if (TREE_OPERAND (ref, 2)

45262

- && !expr_invariant_in_loop_p (loop, TREE_OPERAND (ref, 2)))

45263

- return NULL_TREE;

45264

- if (TREE_OPERAND (ref, 3)

45265

- && !expr_invariant_in_loop_p (loop, TREE_OPERAND (ref, 3)))

45266

- return NULL_TREE;

45267

-

45268

- ret = build4 (ARRAY_REF, TREE_TYPE (ref), op0, NULL_TREE,

45269

- unshare_expr (TREE_OPERAND (ref, 2)),

45270

- unshare_expr (TREE_OPERAND (ref, 3)));

45271

- idx = TREE_OPERAND (ref, 1);

45272

- idx_p = &TREE_OPERAND (ret, 1);

45273

- }

45274

else

45275

- return NULL_TREE;

45276

-

45277

- ok = simple_iv (loop, loop, idx, &iv, true);

45278

- if (!ok)

45279

- return NULL_TREE;

45280

- iv.base = expand_simple_operations (iv.base);

45281

- if (integer_zerop (iv.step))

45282

- *idx_p = unshare_expr (iv.base);

45283

- else

45284

- {

45285

- type = TREE_TYPE (iv.base);

45286

- if (POINTER_TYPE_P (type))

45287

- {

45288

- val = fold_build2 (MULT_EXPR, sizetype, iv.step,

45289

- size_int (iter));

45290

- val = fold_build_pointer_plus (iv.base, val);

45291

- }

45292

- else

45293

- {

45294

- val = fold_build2 (MULT_EXPR, type, iv.step,

45295

- build_int_cst_type (type, iter));

45296

- val = fold_build2 (PLUS_EXPR, type, iv.base, val);

45297

- }

45298

- *idx_p = unshare_expr (val);

45299

- }

45300

-

45301

- return ret;

45302

+ return fold_build2 (MEM_REF, TREE_TYPE (DR_REF (dr)), addr, alias_ptr);

45303

}

45304

45305

/* Get the initialization expression for the INDEX-th temporary variable

45306

@@ -2068,7 +2021,11 @@

45307

45308

stmt = find_common_use_stmt (&name1, &name2);

45309

45310

- if (!stmt)

45311

+ if (!stmt

45312

+ /* A simple post-dominance check - make sure the combination

45313

+ is executed under the same condition as the references. */

45314

+ || (gimple_bb (stmt) != gimple_bb (r1->stmt)

45315

+ && gimple_bb (stmt) != gimple_bb (r2->stmt)))

45316

return false;

45317

45318

acode = gimple_assign_rhs_code (stmt);

45319

@@ -2365,14 +2322,10 @@

45320

if (chain->inits[i] != NULL_TREE)

45321

continue;

45322

45323

- init = ref_at_iteration (loop, DR_REF (dr), (int) i - n);

45324

- if (!init)

45325

- return false;

45326

-

45327

+ init = ref_at_iteration (dr, (int) i - n, &stmts);

45328

if (!chain->all_always_accessed && tree_could_trap_p (init))

45329

return false;

45330

45331

- init = force_gimple_operand (init, &stmts, false, NULL_TREE);

45332

if (stmts)

45333

gsi_insert_seq_on_edge_immediate (entry, stmts);

45334

45335

@@ -2449,6 +2402,7 @@

45336

if (!components)

45337

{

45338

free_data_refs (datarefs);

45339

+ free_affine_expand_cache (&name_expansions);

45340

return false;

45341

}

45342

45343

Index: gcc/loop-iv.c

45344

===================================================================

45345

--- a/src/gcc/loop-iv.c (.../tags/gcc_4_8_2_release)

45346

+++ b/src/gcc/loop-iv.c (.../branches/gcc-4_8-branch)

45347

@@ -425,7 +425,9 @@

45348

&& !iv->first_special)

45349

{

45350

rtx val = get_iv_value (iv, const0_rtx);

45351

- val = lowpart_subreg (mode, val, iv->extend_mode);

45352

+ val = lowpart_subreg (mode, val,

45353

+ iv->extend == IV_UNKNOWN_EXTEND

45354

+ ? iv->mode : iv->extend_mode);

45355

45356

iv->base = val;

45357

iv->extend = IV_UNKNOWN_EXTEND;

45358

@@ -465,8 +467,14 @@

45359

&& !iv->first_special)

45360

{

45361

rtx val = get_iv_value (iv, const0_rtx);

45362

+ if (iv->extend_mode != iv->mode

45363

+ && iv->extend != IV_UNKNOWN_EXTEND

45364

+ && iv->extend != extend)

45365

+ val = lowpart_subreg (iv->mode, val, iv->extend_mode);

45366

val = simplify_gen_unary (iv_extend_to_rtx_code (extend), mode,

45367

- val, iv->extend_mode);

45368

+ val,

45369

+ iv->extend == extend

45370

+ ? iv->extend_mode : iv->mode);

45371

iv->base = val;

45372

iv->extend = IV_UNKNOWN_EXTEND;

45373

iv->mode = iv->extend_mode = mode;

45374

Index: gcc/ipa-prop.c

45375

===================================================================

45376

--- a/src/gcc/ipa-prop.c (.../tags/gcc_4_8_2_release)

45377

+++ b/src/gcc/ipa-prop.c (.../branches/gcc-4_8-branch)

45378

@@ -623,16 +623,22 @@

45379

if (parm_ainfo && parm_ainfo->parm_modified)

45380

return false;

45381

45382

- gcc_checking_assert (gimple_vuse (stmt) != NULL_TREE);

45383

- ao_ref_init (&refd, parm_load);

45384

- /* We can cache visited statements only when parm_ainfo is available and when

45385

- we are looking at a naked load of the whole parameter. */

45386

- if (!parm_ainfo || TREE_CODE (parm_load) != PARM_DECL)

45387

- visited_stmts = NULL;

45388

+ if (optimize)

45389

+ {

45390

+ gcc_checking_assert (gimple_vuse (stmt) != NULL_TREE);

45391

+ ao_ref_init (&refd, parm_load);

45392

+ /* We can cache visited statements only when parm_ainfo is available and

45393

+ when we are looking at a naked load of the whole parameter. */

45394

+ if (!parm_ainfo || TREE_CODE (parm_load) != PARM_DECL)

45395

+ visited_stmts = NULL;

45396

+ else

45397

+ visited_stmts = &parm_ainfo->parm_visited_statements;

45398

+ walk_aliased_vdefs (&refd, gimple_vuse (stmt), mark_modified, &modified,

45399

+ visited_stmts);

45400

+ }

45401

else

45402

- visited_stmts = &parm_ainfo->parm_visited_statements;

45403

- walk_aliased_vdefs (&refd, gimple_vuse (stmt), mark_modified, &modified,

45404

- visited_stmts);

45405

+ modified = true;

45406

+

45407

if (parm_ainfo && modified)

45408

parm_ainfo->parm_modified = true;

45409

return !modified;

45410

@@ -740,7 +746,7 @@

45411

ipa_load_from_parm_agg_1 (vec<ipa_param_descriptor_t> descriptors,

45412

struct param_analysis_info *parms_ainfo, gimple stmt,

45413

tree op, int *index_p, HOST_WIDE_INT *offset_p,

45414

- bool *by_ref_p)

45415

+ HOST_WIDE_INT *size_p, bool *by_ref_p)

45416

{

45417

int index;

45418

HOST_WIDE_INT size, max_size;

45419

@@ -758,6 +764,8 @@

45420

{

45421

*index_p = index;

45422

*by_ref_p = false;

45423

+ if (size_p)

45424

+ *size_p = size;

45425

return true;

45426

}

45427

return false;

45428

@@ -800,6 +808,8 @@

45429

{

45430

*index_p = index;

45431

*by_ref_p = true;

45432

+ if (size_p)

45433

+ *size_p = size;

45434

return true;

45435

}

45436

return false;

45437

@@ -814,7 +824,7 @@

45438

bool *by_ref_p)

45439

{

45440

return ipa_load_from_parm_agg_1 (info->descriptors, NULL, stmt, op, index_p,

45441

- offset_p, by_ref_p);

45442

+ offset_p, NULL, by_ref_p);

45443

}

45444

45445

/* Given that an actual argument is an SSA_NAME (given in NAME) and is a result

45446

@@ -1051,7 +1061,8 @@

45447

return;

45448

parm = TREE_OPERAND (expr, 0);

45449

index = ipa_get_param_decl_index (info, SSA_NAME_VAR (parm));

45450

- gcc_assert (index >= 0);

45451

+ if (index < 0)

45452

+ return;

45453

45454

cond_bb = single_pred (assign_bb);

45455

cond = last_stmt (cond_bb);

45456

@@ -1462,6 +1473,9 @@

45457

{

45458

struct cgraph_edge *cs;

45459

45460

+ if (!optimize)

45461

+ return;

45462

+

45463

for (cs = node->callees; cs; cs = cs->next_callee)

45464

{

45465

struct cgraph_node *callee = cgraph_function_or_thunk_node (cs->callee,

45466

@@ -1646,7 +1660,7 @@

45467

if (gimple_assign_single_p (def)

45468

&& ipa_load_from_parm_agg_1 (info->descriptors, parms_ainfo, def,

45469

gimple_assign_rhs1 (def), &index, &offset,

45470

- &by_ref))

45471

+ NULL, &by_ref))

45472

{

45473

struct cgraph_edge *cs = ipa_note_param_call (node, index, call);

45474

cs->indirect_info->offset = offset;

45475

@@ -1847,8 +1861,7 @@

45476

passed in DATA. */

45477

45478

static bool

45479

-visit_ref_for_mod_analysis (gimple stmt ATTRIBUTE_UNUSED,

45480

- tree op, void *data)

45481

+visit_ref_for_mod_analysis (gimple, tree op, tree, void *data)

45482

{

45483

struct ipa_node_params *info = (struct ipa_node_params *) data;

45484

45485

@@ -2126,7 +2139,6 @@

45486

we may create the first reference to the object in the unit. */

45487

if (!callee || callee->global.inlined_to)

45488

{

45489

- struct cgraph_node *first_clone = callee;

45490

45491

/* We are better to ensure we can refer to it.

45492

In the case of static functions we are out of luck, since we already

45493

@@ -2142,31 +2154,7 @@

45494

xstrdup (cgraph_node_name (ie->callee)), ie->callee->uid);

45495

return NULL;

45496

}

45497

-

45498

- /* Create symbol table node. Even if inline clone exists, we can not take

45499

- it as a target of non-inlined call. */

45500

- callee = cgraph_create_node (target);

45501

-

45502

- /* OK, we previously inlined the function, then removed the offline copy and

45503

- now we want it back for external call. This can happen when devirtualizing

45504

- while inlining function called once that happens after extern inlined and

45505

- virtuals are already removed. In this case introduce the external node

45506

- and make it available for call. */

45507

- if (first_clone)

45508

- {

45509

- first_clone->clone_of = callee;

45510

- callee->clones = first_clone;

45511

- symtab_prevail_in_asm_name_hash ((symtab_node)callee);

45512

- symtab_insert_node_to_hashtable ((symtab_node)callee);

45513

- if (dump_file)

45514

- fprintf (dump_file, "ipa-prop: Introduced new external node "

45515

- "(%s/%i) and turned into root of the clone tree.\n",

45516

- xstrdup (cgraph_node_name (callee)), callee->uid);

45517

- }

45518

- else if (dump_file)

45519

- fprintf (dump_file, "ipa-prop: Introduced new external node "

45520

- "(%s/%i).\n",

45521

- xstrdup (cgraph_node_name (callee)), callee->uid);

45522

+ callee = cgraph_get_create_real_symbol_node (target);

45523

}

45524

ipa_check_create_node_params ();

45525

45526

@@ -3902,7 +3890,7 @@

45527

struct ipa_agg_replacement_value *v;

45528

gimple stmt = gsi_stmt (gsi);

45529

tree rhs, val, t;

45530

- HOST_WIDE_INT offset;

45531

+ HOST_WIDE_INT offset, size;

45532

int index;

45533

bool by_ref, vce;

45534

45535

@@ -3929,13 +3917,15 @@

45536

continue;

45537

45538

if (!ipa_load_from_parm_agg_1 (descriptors, parms_ainfo, stmt,

45539

- rhs, &index, &offset, &by_ref))

45540

+ rhs, &index, &offset, &size, &by_ref))

45541

continue;

45542

for (v = aggval; v; v = v->next)

45543

if (v->index == index

45544

&& v->offset == offset)

45545

break;

45546

- if (!v || v->by_ref != by_ref)

45547

+ if (!v

45548

+ || v->by_ref != by_ref

45549

+ || tree_low_cst (TYPE_SIZE (TREE_TYPE (v->value)), 0) != size)

45550

continue;

45551

45552

gcc_checking_assert (is_gimple_ip_invariant (v->value));

45553

Index: gcc/tree-ssa-dce.c

45554

===================================================================

45555

--- a/src/gcc/tree-ssa-dce.c (.../tags/gcc_4_8_2_release)

45556

+++ b/src/gcc/tree-ssa-dce.c (.../branches/gcc-4_8-branch)

45557

@@ -1307,26 +1307,19 @@

45558

stats.total++;

45559

45560

/* We can mark a call to free as not necessary if the

45561

- defining statement of its argument is an allocation

45562

- function and that is not necessary itself. */

45563

- if (gimple_call_builtin_p (stmt, BUILT_IN_FREE))

45564

+ defining statement of its argument is not necessary

45565

+ (and thus is getting removed). */

45566

+ if (gimple_plf (stmt, STMT_NECESSARY)

45567

+ && gimple_call_builtin_p (stmt, BUILT_IN_FREE))

45568

{

45569

tree ptr = gimple_call_arg (stmt, 0);

45570

- tree callee2;

45571

- gimple def_stmt;

45572

- if (TREE_CODE (ptr) != SSA_NAME)

45573

- continue;

45574

- def_stmt = SSA_NAME_DEF_STMT (ptr);

45575

- if (!is_gimple_call (def_stmt)

45576

- || gimple_plf (def_stmt, STMT_NECESSARY))

45577

- continue;

45578

- callee2 = gimple_call_fndecl (def_stmt);

45579

- if (callee2 == NULL_TREE

45580

- || DECL_BUILT_IN_CLASS (callee2) != BUILT_IN_NORMAL

45581

- || (DECL_FUNCTION_CODE (callee2) != BUILT_IN_MALLOC

45582

- && DECL_FUNCTION_CODE (callee2) != BUILT_IN_CALLOC))

45583

- continue;

45584

- gimple_set_plf (stmt, STMT_NECESSARY, false);

45585

+ if (TREE_CODE (ptr) == SSA_NAME)

45586

+ {

45587

+ gimple def_stmt = SSA_NAME_DEF_STMT (ptr);

45588

+ if (!gimple_nop_p (def_stmt)

45589

+ && !gimple_plf (def_stmt, STMT_NECESSARY))

45590

+ gimple_set_plf (stmt, STMT_NECESSARY, false);

45591

+ }

45592

}

45593

45594

/* If GSI is not necessary then remove it. */

45595

Index: gcc/tree-ssa-ter.c

45596

===================================================================

45597

--- a/src/gcc/tree-ssa-ter.c (.../tags/gcc_4_8_2_release)

45598

+++ b/src/gcc/tree-ssa-ter.c (.../branches/gcc-4_8-branch)

45599

@@ -590,6 +590,30 @@

45600

}

45601

45602

45603

+/* Helper function for find_ssaname_in_stores. Called via walk_tree to

45604

+ find a SSA_NAME DATA somewhere in *TP. */

45605

+

45606

+static tree

45607

+find_ssaname (tree *tp, int *walk_subtrees, void *data)

45608

+{

45609

+ tree var = (tree) data;

45610

+ if (*tp == var)

45611

+ return var;

45612

+ else if (IS_TYPE_OR_DECL_P (*tp))

45613

+ *walk_subtrees = 0;

45614

+ return NULL_TREE;

45615

+}

45616

+

45617

+/* Helper function for find_replaceable_in_bb. Return true if SSA_NAME DATA

45618

+ is used somewhere in T, which is a store in the statement. Called via

45619

+ walk_stmt_load_store_addr_ops. */

45620

+

45621

+static bool

45622

+find_ssaname_in_store (gimple, tree, tree t, void *data)

45623

+{

45624

+ return walk_tree (&t, find_ssaname, data, NULL) != NULL_TREE;

45625

+}

45626

+

45627

/* This function processes basic block BB, and looks for variables which can

45628

be replaced by their expressions. Results are stored in the table TAB. */

45629

45630

@@ -643,8 +667,7 @@

45631

/* If the stmt does a memory store and the replacement

45632

is a load aliasing it avoid creating overlapping

45633

assignments which we cannot expand correctly. */

45634

- if (gimple_vdef (stmt)

45635

- && gimple_assign_single_p (stmt))

45636

+ if (gimple_vdef (stmt))

45637

{

45638

gimple def_stmt = SSA_NAME_DEF_STMT (use);

45639

while (is_gimple_assign (def_stmt)

45640

@@ -653,9 +676,29 @@

45641

= SSA_NAME_DEF_STMT (gimple_assign_rhs1 (def_stmt));

45642

if (gimple_vuse (def_stmt)

45643

&& gimple_assign_single_p (def_stmt)

45644

- && refs_may_alias_p (gimple_assign_lhs (stmt),

45645

- gimple_assign_rhs1 (def_stmt)))

45646

- same_root_var = true;

45647

+ && stmt_may_clobber_ref_p (stmt,

45648

+ gimple_assign_rhs1 (def_stmt)))

45649

+ {

45650

+ /* For calls, it is not a problem if USE is among

45651

+ call's arguments or say OBJ_TYPE_REF argument,

45652

+ all those necessarily need to be evaluated before

45653

+ the call that may clobber the memory. But if

45654

+ LHS of the call refers to USE, expansion might

45655

+ evaluate it after the call, prevent TER in that

45656

+ case.

45657

+ For inline asm, allow TER of loads into input

45658

+ arguments, but disallow TER for USEs that occur

45659

+ somewhere in outputs. */

45660

+ if (is_gimple_call (stmt)

45661

+ || gimple_code (stmt) == GIMPLE_ASM)

45662

+ {

45663

+ if (walk_stmt_load_store_ops (stmt, use, NULL,

45664

+ find_ssaname_in_store))

45665

+ same_root_var = true;

45666

+ }

45667

+ else

45668

+ same_root_var = true;

45669

+ }

45670

}

45671

45672

/* Mark expression as replaceable unless stmt is volatile, or the

45673

Index: gcc/ira.c

45674

===================================================================

45675

--- a/src/gcc/ira.c (.../tags/gcc_4_8_2_release)

45676

+++ b/src/gcc/ira.c (.../branches/gcc-4_8-branch)

45677

@@ -4742,6 +4742,18 @@

45678

if (need_dce && optimize)

45679

run_fast_dce ();

45680

45681

+ /* Diagnose uses of the hard frame pointer when it is used as a global

45682

+ register. Often we can get away with letting the user appropriate

45683

+ the frame pointer, but we should let them know when code generation

45684

+ makes that impossible. */

45685

+ if (global_regs[HARD_FRAME_POINTER_REGNUM] && frame_pointer_needed)

45686

+ {

45687

+ tree decl = global_regs_decl[HARD_FRAME_POINTER_REGNUM];

45688

+ error_at (DECL_SOURCE_LOCATION (current_function_decl),

45689

+ "frame pointer required, but reserved");

45690

+ inform (DECL_SOURCE_LOCATION (decl), "for %qD", decl);

45691

+ }

45692

+

45693

timevar_pop (TV_IRA);

45694

}

45695

45696

Index: gcc/rtl.h

45697

===================================================================

45698

--- a/src/gcc/rtl.h (.../tags/gcc_4_8_2_release)

45699

+++ b/src/gcc/rtl.h (.../branches/gcc-4_8-branch)

45700

@@ -2705,6 +2705,8 @@

45701

const_rtx, rtx);

45702

extern int read_dependence (const_rtx, const_rtx);

45703

extern int anti_dependence (const_rtx, const_rtx);

45704

+extern int canon_anti_dependence (const_rtx, bool,

45705

+ const_rtx, enum machine_mode, rtx);

45706

extern int output_dependence (const_rtx, const_rtx);

45707

extern int may_alias_p (const_rtx, const_rtx);

45708

extern void init_alias_target (void);

45709

@@ -2789,6 +2791,8 @@

45710

#define fatal_insn_not_found(insn) \

45711

_fatal_insn_not_found (insn, __FILE__, __LINE__, __FUNCTION__)

45712

45713

+/* reginfo.c */

45714

+extern tree GTY(()) global_regs_decl[FIRST_PSEUDO_REGISTER];

45715

45716

45717

#endif /* ! GCC_RTL_H */

45718

Index: gcc/tree-vect-stmts.c

45719

===================================================================

45720

--- a/src/gcc/tree-vect-stmts.c (.../tags/gcc_4_8_2_release)

45721

+++ b/src/gcc/tree-vect-stmts.c (.../branches/gcc-4_8-branch)

45722

@@ -4369,6 +4369,20 @@

45723

return false;

45724

}

45725

45726

+ /* Invalidate assumptions made by dependence analysis when vectorization

45727

+ on the unrolled body effectively re-orders stmts. */

45728

+ if (ncopies > 1

45729

+ && STMT_VINFO_MIN_NEG_DIST (stmt_info) != 0

45730

+ && ((unsigned)LOOP_VINFO_VECT_FACTOR (loop_vinfo)

45731

+ > STMT_VINFO_MIN_NEG_DIST (stmt_info)))

45732

+ {

45733

+ if (dump_enabled_p ())

45734

+ dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location,

45735

+ "cannot perform implicit CSE when unrolling "

45736

+ "with negative dependence distance\n");

45737

+ return false;

45738

+ }

45739

+

45740

if (!STMT_VINFO_RELEVANT_P (stmt_info) && !bb_vinfo)

45741

return false;

45742

45743

@@ -4425,6 +4439,20 @@

45744

else if (!vect_grouped_load_supported (vectype, group_size))

45745

return false;

45746

}

45747

+

45748

+ /* Invalidate assumptions made by dependence analysis when vectorization

45749

+ on the unrolled body effectively re-orders stmts. */

45750

+ if (!PURE_SLP_STMT (stmt_info)

45751

+ && STMT_VINFO_MIN_NEG_DIST (stmt_info) != 0

45752

+ && ((unsigned)LOOP_VINFO_VECT_FACTOR (loop_vinfo)

45753

+ > STMT_VINFO_MIN_NEG_DIST (stmt_info)))

45754

+ {

45755

+ if (dump_enabled_p ())

45756

+ dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location,

45757

+ "cannot perform implicit CSE when performing "

45758

+ "group loads with negative dependence distance\n");

45759

+ return false;

45760

+ }

45761

}

45762

45763

45764

@@ -6054,8 +6082,7 @@

45765

corresponding to that mode. The theory is that any use that

45766

would cause problems with this will disable vectorization anyway. */

45767

else if (!SCALAR_FLOAT_TYPE_P (scalar_type)

45768

- && !INTEGRAL_TYPE_P (scalar_type)

45769

- && !POINTER_TYPE_P (scalar_type))

45770

+ && !INTEGRAL_TYPE_P (scalar_type))

45771

scalar_type = lang_hooks.types.type_for_mode (inner_mode, 1);

45772

45773

/* We can't build a vector type of elements with alignment bigger than

45774

Index: gcc/tree-inline.c

45775

===================================================================

45776

--- a/src/gcc/tree-inline.c (.../tags/gcc_4_8_2_release)

45777

+++ b/src/gcc/tree-inline.c (.../branches/gcc-4_8-branch)

45778

@@ -2841,7 +2841,8 @@

45779

{

45780

var = return_slot;

45781

gcc_assert (TREE_CODE (var) != SSA_NAME);

45782

- TREE_ADDRESSABLE (var) |= TREE_ADDRESSABLE (result);

45783

+ if (TREE_ADDRESSABLE (result))

45784

+ mark_addressable (var);

45785

}

45786

if ((TREE_CODE (TREE_TYPE (result)) == COMPLEX_TYPE

45787

|| TREE_CODE (TREE_TYPE (result)) == VECTOR_TYPE)

45788

Index: gcc/tree-ssa-phiprop.c

45789

===================================================================

45790

--- a/src/gcc/tree-ssa-phiprop.c (.../tags/gcc_4_8_2_release)

45791

+++ b/src/gcc/tree-ssa-phiprop.c (.../branches/gcc-4_8-branch)

45792

@@ -307,6 +307,12 @@

45793

gimple def_stmt;

45794

tree vuse;

45795

45796

+ /* Only replace loads in blocks that post-dominate the PHI node. That

45797

+ makes sure we don't end up speculating loads. */

45798

+ if (!dominated_by_p (CDI_POST_DOMINATORS,

45799

+ bb, gimple_bb (use_stmt)))

45800

+ continue;

45801

+

45802

/* Check whether this is a load of *ptr. */

45803

if (!(is_gimple_assign (use_stmt)

45804

&& TREE_CODE (gimple_assign_lhs (use_stmt)) == SSA_NAME

45805

@@ -378,6 +384,7 @@

45806

size_t n;

45807

45808

calculate_dominance_info (CDI_DOMINATORS);

45809

+ calculate_dominance_info (CDI_POST_DOMINATORS);

45810

45811

n = num_ssa_names;

45812

phivn = XCNEWVEC (struct phiprop_d, n);

45813

@@ -395,6 +402,8 @@

45814

bbs.release ();

45815

free (phivn);

45816

45817

+ free_dominance_info (CDI_POST_DOMINATORS);

45818

+

45819

return 0;

45820

}

45821

45822

Index: gcc/tree-object-size.c

45823

===================================================================

45824

--- a/src/gcc/tree-object-size.c (.../tags/gcc_4_8_2_release)

45825

+++ b/src/gcc/tree-object-size.c (.../branches/gcc-4_8-branch)

45826

@@ -64,7 +64,7 @@

45827

the subobject (innermost array or field with address taken).

45828

object_sizes[2] is lower bound for number of bytes till the end of

45829

the object and object_sizes[3] lower bound for subobject. */

45830

-static unsigned HOST_WIDE_INT *object_sizes[4];

45831

+static vec<unsigned HOST_WIDE_INT> object_sizes[4];

45832

45833

/* Bitmaps what object sizes have been computed already. */

45834

static bitmap computed[4];

45835

@@ -493,7 +493,7 @@

45836

45837

if (TREE_CODE (ptr) == SSA_NAME

45838

&& POINTER_TYPE_P (TREE_TYPE (ptr))

45839

- && object_sizes[object_size_type] != NULL)

45840

+ && computed[object_size_type] != NULL)

45841

{

45842

if (!bitmap_bit_p (computed[object_size_type], SSA_NAME_VERSION (ptr)))

45843

{

45844

@@ -501,6 +501,8 @@

45845

bitmap_iterator bi;

45846

unsigned int i;

45847

45848

+ if (num_ssa_names > object_sizes[object_size_type].length ())

45849

+ object_sizes[object_size_type].safe_grow (num_ssa_names);

45850

if (dump_file)

45851

{

45852

fprintf (dump_file, "Computing %s %sobject size for ",

45853

@@ -1162,12 +1164,12 @@

45854

{

45855

int object_size_type;

45856

45857

- if (object_sizes[0])

45858

+ if (computed[0])

45859

return;

45860

45861

for (object_size_type = 0; object_size_type <= 3; object_size_type++)

45862

{

45863

- object_sizes[object_size_type] = XNEWVEC (unsigned HOST_WIDE_INT, num_ssa_names);

45864

+ object_sizes[object_size_type].safe_grow (num_ssa_names);

45865

computed[object_size_type] = BITMAP_ALLOC (NULL);

45866

}

45867

45868

@@ -1184,9 +1186,8 @@

45869

45870

for (object_size_type = 0; object_size_type <= 3; object_size_type++)

45871

{

45872

- free (object_sizes[object_size_type]);

45873

+ object_sizes[object_size_type].release ();

45874

BITMAP_FREE (computed[object_size_type]);

45875

- object_sizes[object_size_type] = NULL;

45876

}

45877

}

45878

45879

@@ -1202,18 +1203,11 @@

45880

gimple_stmt_iterator i;

45881

for (i = gsi_start_bb (bb); !gsi_end_p (i); gsi_next (&i))

45882

{

45883

- tree callee, result;

45884

+ tree result;

45885

gimple call = gsi_stmt (i);

45886

-

45887

- if (gimple_code (call) != GIMPLE_CALL)

45888

+ if (!gimple_call_builtin_p (call, BUILT_IN_OBJECT_SIZE))

45889

continue;

45890

45891

- callee = gimple_call_fndecl (call);

45892

- if (!callee

45893

- || DECL_BUILT_IN_CLASS (callee) != BUILT_IN_NORMAL

45894

- || DECL_FUNCTION_CODE (callee) != BUILT_IN_OBJECT_SIZE)

45895

- continue;

45896

-

45897

init_object_sizes ();

45898

result = fold_call_stmt (call, false);

45899

if (!result)

45900

@@ -1240,20 +1234,32 @@

45901

continue;

45902

}

45903

45904

+ gcc_assert (TREE_CODE (result) == INTEGER_CST);

45905

+

45906

if (dump_file && (dump_flags & TDF_DETAILS))

45907

{

45908

fprintf (dump_file, "Simplified\n ");

45909

print_gimple_stmt (dump_file, call, 0, dump_flags);

45910

+ fprintf (dump_file, " to ");

45911

+ print_generic_expr (dump_file, result, 0);

45912

+ fprintf (dump_file, "\n");

45913

}

45914

45915

- if (!update_call_from_tree (&i, result))

45916

- gcc_unreachable ();

45917

+ tree lhs = gimple_call_lhs (call);

45918

+ if (!lhs)

45919

+ continue;

45920

45921

- if (dump_file && (dump_flags & TDF_DETAILS))

45922

+ /* Propagate into all uses and fold those stmts. */

45923

+ gimple use_stmt;

45924

+ imm_use_iterator iter;

45925

+ FOR_EACH_IMM_USE_STMT (use_stmt, iter, lhs)

45926

{

45927

- fprintf (dump_file, "to\n ");

45928

- print_gimple_stmt (dump_file, gsi_stmt (i), 0, dump_flags);

45929

- fprintf (dump_file, "\n");

45930

+ use_operand_p use_p;

45931

+ FOR_EACH_IMM_USE_ON_STMT (use_p, iter)

45932

+ SET_USE (use_p, result);

45933

+ gimple_stmt_iterator gsi = gsi_for_stmt (use_stmt);

45934

+ fold_stmt (&gsi);

45935

+ update_stmt (gsi_stmt (gsi));

45936

}

45937

}

45938

}

45939

Index: gcc/combine.c

45940

===================================================================

45941

--- a/src/gcc/combine.c (.../tags/gcc_4_8_2_release)

45942

+++ b/src/gcc/combine.c (.../branches/gcc-4_8-branch)

45943

@@ -3884,15 +3884,19 @@

45944

45945

PATTERN (undobuf.other_insn) = other_pat;

45946

45947

- /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they

45948

- are still valid. Then add any non-duplicate notes added by

45949

- recog_for_combine. */

45950

+ /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,

45951

+ ensure that they are still valid. Then add any non-duplicate

45952

+ notes added by recog_for_combine. */

45953

for (note = REG_NOTES (undobuf.other_insn); note; note = next)

45954

{

45955

next = XEXP (note, 1);

45956

45957

- if (REG_NOTE_KIND (note) == REG_UNUSED

45958

- && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))

45959

+ if ((REG_NOTE_KIND (note) == REG_DEAD

45960

+ && !reg_referenced_p (XEXP (note, 0),

45961

+ PATTERN (undobuf.other_insn)))

45962

+ ||(REG_NOTE_KIND (note) == REG_UNUSED

45963

+ && !reg_set_p (XEXP (note, 0),

45964

+ PATTERN (undobuf.other_insn))))

45965

remove_note (undobuf.other_insn, note);

45966

}

45967

45968

@@ -5798,8 +5802,15 @@

45969

return x;

45970

}

45971

45972

- /* If the code changed, return a whole new comparison. */

45973

- if (new_code != code)

45974

+ /* If the code changed, return a whole new comparison.

45975

+ We also need to avoid using SUBST in cases where

45976

+ simplify_comparison has widened a comparison with a CONST_INT,

45977

+ since in that case the wider CONST_INT may fail the sanity

45978

+ checks in do_SUBST. */

45979

+ if (new_code != code

45980

+ || (CONST_INT_P (op1)

45981

+ && GET_MODE (op0) != GET_MODE (XEXP (x, 0))

45982

+ && GET_MODE (op0) != GET_MODE (XEXP (x, 1))))

45983

return gen_rtx_fmt_ee (new_code, mode, op0, op1);

45984

45985

/* Otherwise, keep this operation, but maybe change its operands.

45986

@@ -7991,7 +8002,7 @@

45987

if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)

45988

return x;

45989

45990

- /* We want to perform the operation is its present mode unless we know

45991

+ /* We want to perform the operation in its present mode unless we know

45992

that the operation is valid in MODE, in which case we do the operation

45993

in MODE. */

45994

op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))

45995

@@ -8427,9 +8438,10 @@

45996

GET_MODE (x), GEN_INT (mask),

45997

XEXP (x, 1));

45998

if (temp && CONST_INT_P (temp))

45999

- SUBST (XEXP (x, 0),

46000

- force_to_mode (XEXP (x, 0), GET_MODE (x),

46001

- INTVAL (temp), next_select));

46002

+ x = simplify_gen_binary (code, GET_MODE (x),

46003

+ force_to_mode (XEXP (x, 0), GET_MODE (x),

46004

+ INTVAL (temp), next_select),

46005

+ XEXP (x, 1));

46006

}

46007

break;

46008

46009

@@ -8497,14 +8509,16 @@

46010

/* We have no way of knowing if the IF_THEN_ELSE can itself be

46011

written in a narrower mode. We play it safe and do not do so. */

46012

46013

- SUBST (XEXP (x, 1),

46014

- gen_lowpart_or_truncate (GET_MODE (x),

46015

- force_to_mode (XEXP (x, 1), mode,

46016

- mask, next_select)));

46017

- SUBST (XEXP (x, 2),

46018

- gen_lowpart_or_truncate (GET_MODE (x),

46019

- force_to_mode (XEXP (x, 2), mode,

46020

- mask, next_select)));

46021

+ op0 = gen_lowpart_or_truncate (GET_MODE (x),

46022

+ force_to_mode (XEXP (x, 1), mode,

46023

+ mask, next_select));

46024

+ op1 = gen_lowpart_or_truncate (GET_MODE (x),

46025

+ force_to_mode (XEXP (x, 2), mode,

46026

+ mask, next_select));

46027

+ if (op0 != XEXP (x, 1) || op1 != XEXP (x, 2))

46028

+ x = simplify_gen_ternary (IF_THEN_ELSE, GET_MODE (x),

46029

+ GET_MODE (XEXP (x, 0)), XEXP (x, 0),

46030

+ op0, op1);

46031

break;

46032

46033

default:

46034

Index: gcc/bb-reorder.c

46035

===================================================================

46036

--- a/src/gcc/bb-reorder.c (.../tags/gcc_4_8_2_release)

46037

+++ b/src/gcc/bb-reorder.c (.../branches/gcc-4_8-branch)

46038

@@ -1685,9 +1685,8 @@

46039

edge e;

46040

edge_iterator ei;

46041

46042

- /* Find EDGE_CAN_FALLTHRU edge. */

46043

FOR_EACH_EDGE (e, ei, cur_bb->succs)

46044

- if (e->flags & EDGE_CAN_FALLTHRU)

46045

+ if (e->flags & EDGE_FALLTHRU)

46046

{

46047

fall_thru = e;

46048

break;

46049

Index: gcc/tree-vect-generic.c

46050

===================================================================

46051

--- a/src/gcc/tree-vect-generic.c (.../tags/gcc_4_8_2_release)

46052

+++ b/src/gcc/tree-vect-generic.c (.../branches/gcc-4_8-branch)

46053

@@ -1006,7 +1006,8 @@

46054

46055

if (!optimize

46056

|| !VECTOR_INTEGER_TYPE_P (type)

46057

- || TREE_CODE (rhs2) != VECTOR_CST)

46058

+ || TREE_CODE (rhs2) != VECTOR_CST

46059

+ || !VECTOR_MODE_P (TYPE_MODE (type)))

46060

break;

46061

46062

ret = expand_vector_divmod (gsi, type, rhs1, rhs2, code);

46063

Index: gcc/tree-flow.h

46064

===================================================================

46065

--- a/src/gcc/tree-flow.h (.../tags/gcc_4_8_2_release)

46066

+++ b/src/gcc/tree-flow.h (.../branches/gcc-4_8-branch)

46067

@@ -425,6 +425,7 @@

46068

basic_block, tree);

46069

void remove_edge_and_dominated_blocks (edge);

46070

bool tree_node_can_be_shared (tree);

46071

+extern unsigned int split_critical_edges (void);

46072

46073

/* In tree-cfgcleanup.c */

46074

extern bitmap cfgcleanup_altered_bbs;

46075

Index: gcc/config.gcc

46076

===================================================================

46077

--- a/src/gcc/config.gcc (.../tags/gcc_4_8_2_release)

46078

+++ b/src/gcc/config.gcc (.../branches/gcc-4_8-branch)

46079

@@ -420,7 +420,7 @@

46080

;;

46081

powerpc*-*-*)

46082

cpu_type=rs6000

46083

- extra_headers="ppc-asm.h altivec.h spe.h ppu_intrinsics.h paired.h spu2vmx.h vec_types.h si2vmx.h"

46084

+ extra_headers="ppc-asm.h altivec.h spe.h ppu_intrinsics.h paired.h spu2vmx.h vec_types.h si2vmx.h htmintrin.h htmxlintrin.h"

46085

need_64bit_hwint=yes

46086

case x$with_cpu in

46087

xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[345678]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|Xe6500)

46088

@@ -1761,6 +1761,14 @@

46089

tmake_file="${tmake_file} microblaze/t-microblaze-linux"

46090

;;

46091

microblaze*-*-rtems*)

46092

+ case $target in

46093

+ microblazeel-*)

46094

+ tm_defines="${tm_defines} TARGET_BIG_ENDIAN_DEFAULT=0"

46095

+ ;;

46096

+ microblaze-*)

46097

+ tm_defines="${tm_defines} TARGET_BIG_ENDIAN_DEFAULT=4321"

46098

+ ;;

46099

+ esac

46100

tm_file="${tm_file} dbxelf.h"

46101

tm_file="${tm_file} microblaze/rtems.h rtems.h newlib-stdint.h"

46102

c_target_objs="${c_target_objs} microblaze-c.o"

46103

@@ -2073,7 +2081,7 @@

46104

tmake_file="rs6000/t-fprules rs6000/t-ppcos ${tmake_file} rs6000/t-ppccomm"

46105

case ${target} in

46106

powerpc*le-*-*)

46107

- tm_file="${tm_file} rs6000/sysv4le.h" ;;

46108

+ tm_file="${tm_file} rs6000/sysv4le.h" ;;

46109

esac

46110

maybe_biarch=yes

46111

case ${target} in

46112

@@ -2096,6 +2104,19 @@

46113

fi

46114

tm_file="rs6000/biarch64.h ${tm_file} rs6000/linux64.h glibc-stdint.h"

46115

tmake_file="$tmake_file rs6000/t-linux64"

46116

+ case ${target} in

46117

+ powerpc*le-*-*)

46118

+ tmake_file="$tmake_file rs6000/t-linux64le"

46119

+ case ${enable_targets} in

46120

+ all | *powerpc64-* | *powerpc-*)

46121

+ tmake_file="$tmake_file rs6000/t-linux64lebe" ;;

46122

+ esac ;;

46123

+ *)

46124

+ case ${enable_targets} in

46125

+ all | *powerpc64le-* | *powerpcle-*)

46126

+ tmake_file="$tmake_file rs6000/t-linux64bele" ;;

46127

+ esac ;;

46128

+ esac

46129

extra_options="${extra_options} rs6000/linux64.opt"

46130

;;

46131

*)

46132

@@ -2963,11 +2984,18 @@

46133

with_cpu=8540

46134

fi

46135

;;

46136

- sparc-leon*-*)

46137

- with_cpu=v8;

46138

- ;;

46139

sparc*-*-*)

46140

- with_cpu="`echo ${target} | sed 's/-.*$//'`"

46141

+ case ${target} in

46142

+ *-leon-*)

46143

+ with_cpu=leon

46144

+ ;;

46145

+ *-leon[3-9]*)

46146

+ with_cpu=leon3

46147

+ ;;

46148

+ *)

46149

+ with_cpu="`echo ${target} | sed 's/-.*$//'`"

46150

+ ;;

46151

+ esac

46152

;;

46153

esac

46154

46155

@@ -3122,6 +3150,11 @@

46156

${srcdir}/config/aarch64/$def | \

46157

sed -e 's/^[^,]*,[ ]*//' | \

46158

sed -e 's/,.*$//'`

46159

+ # Extract the architecture flags from aarch64-arches.def

46160

+ ext_mask=`grep "^$pattern(\"$base_val\"," \

46161

+ ${srcdir}/config/aarch64/$def | \

46162

+ sed -e 's/)$//' | \

46163

+ sed -e 's/^.*,//'`

46164

else

46165

base_id=`grep "^$pattern(\"$base_val\"," \

46166

${srcdir}/config/aarch64/$def | \

46167

@@ -3494,7 +3527,7 @@

46168

;;

46169

46170

powerpc*-*-* | rs6000-*-*)

46171

- supported_defaults="cpu cpu_32 cpu_64 float tune tune_32 tune_64"

46172

+ supported_defaults="abi cpu cpu_32 cpu_64 float tune tune_32 tune_64"

46173

46174

for which in cpu cpu_32 cpu_64 tune tune_32 tune_64; do

46175

eval "val=\$with_$which"

46176

@@ -3531,6 +3564,16 @@

46177

;;

46178

esac

46179

done

46180

+

46181

+ case "$with_abi" in

46182

+ "" | elfv1 | elfv2 )

46183

+ #OK

46184

+ ;;

46185

+ *)

46186

+ echo "Unknown ABI used in --with-abi=$with_abi"

46187

+ exit 1

46188

+ ;;

46189

+ esac

46190

;;

46191

46192

s390*-*-*)

46193

@@ -3587,7 +3630,7 @@

46194

case ${val} in

46195

"" | sparc | sparcv9 | sparc64 \

46196

| v7 | cypress \

46197

- | v8 | supersparc | hypersparc | leon \

46198

46199

| sparclite | f930 | f934 | sparclite86x \

46200

| sparclet | tsc701 \

46201

46202

@@ -3661,10 +3704,8 @@

46203

target_cpu_default2=

46204

case ${target} in

46205

aarch64*-*-*)

46206

- if test x$target_cpu_cname = x

46207

+ if test x"$target_cpu_cname" != x

46208

then

46209

- target_cpu_default2=TARGET_CPU_generic

46210

- else

46211

target_cpu_default2=$target_cpu_cname

46212

fi

46213

;;

46214

@@ -3745,15 +3786,6 @@

46215

cxx_target_objs="${cxx_target_objs} sh-c.o"

46216

;;

46217

46218

- sparc-leon*-*)

46219

- if test x$with_tune = x ; then

46220

- with_tune=leon;

46221

- fi

46222

-

46223

- # The SPARC port checks this value at compile-time.

46224

- target_cpu_default2="TARGET_CPU_$with_cpu"

46225

- ;;

46226

-

46227

sparc*-*-*)

46228

# Some standard aliases.

46229

case x$with_cpu in

46230

@@ -3765,6 +3797,17 @@

46231

;;

46232

esac

46233

46234

+ if test x$with_tune = x ; then

46235

+ case ${target} in

46236

+ *-leon-*)

46237

+ with_tune=leon

46238

+ ;;

46239

+ *-leon[3-9]*)

46240

+ with_tune=leon3

46241

+ ;;

46242

+ esac

46243

+ fi

46244

+

46245

# The SPARC port checks this value at compile-time.

46246

target_cpu_default2="TARGET_CPU_$with_cpu"

46247

;;

46248

Index: gcc/reginfo.c

46249

===================================================================

46250

--- a/src/gcc/reginfo.c (.../tags/gcc_4_8_2_release)

46251

+++ b/src/gcc/reginfo.c (.../branches/gcc-4_8-branch)

46252

@@ -85,7 +85,7 @@

46253

char global_regs[FIRST_PSEUDO_REGISTER];

46254

46255

/* Declaration for the global register. */

46256

-static tree GTY(()) global_regs_decl[FIRST_PSEUDO_REGISTER];

46257

+tree global_regs_decl[FIRST_PSEUDO_REGISTER];

46258

46259

/* Same information as REGS_INVALIDATED_BY_CALL but in regset form to be used

46260

in dataflow more conveniently. */

46261

@@ -620,40 +620,35 @@

46262

mode = GET_MODE_WIDER_MODE (mode))

46263

if ((unsigned) hard_regno_nregs[regno][mode] == nregs

46264

&& HARD_REGNO_MODE_OK (regno, mode)

46265

- && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)))

46266

+ && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))

46267

+ && GET_MODE_SIZE (mode) > GET_MODE_SIZE (found_mode))

46268

found_mode = mode;

46269

46270

- if (found_mode != VOIDmode)

46271

- return found_mode;

46272

-

46273

for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT);

46274

mode != VOIDmode;

46275

mode = GET_MODE_WIDER_MODE (mode))

46276

if ((unsigned) hard_regno_nregs[regno][mode] == nregs

46277

&& HARD_REGNO_MODE_OK (regno, mode)

46278

- && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)))

46279

+ && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))

46280

+ && GET_MODE_SIZE (mode) > GET_MODE_SIZE (found_mode))

46281

found_mode = mode;

46282

46283

- if (found_mode != VOIDmode)

46284

- return found_mode;

46285

-

46286

for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FLOAT);

46287

mode != VOIDmode;

46288

mode = GET_MODE_WIDER_MODE (mode))

46289

if ((unsigned) hard_regno_nregs[regno][mode] == nregs

46290

&& HARD_REGNO_MODE_OK (regno, mode)

46291

- && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)))

46292

+ && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))

46293

+ && GET_MODE_SIZE (mode) > GET_MODE_SIZE (found_mode))

46294

found_mode = mode;

46295

46296

- if (found_mode != VOIDmode)

46297

- return found_mode;

46298

-

46299

for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_INT);

46300

mode != VOIDmode;

46301

mode = GET_MODE_WIDER_MODE (mode))

46302

if ((unsigned) hard_regno_nregs[regno][mode] == nregs

46303

&& HARD_REGNO_MODE_OK (regno, mode)

46304

- && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)))

46305

+ && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))

46306

+ && GET_MODE_SIZE (mode) > GET_MODE_SIZE (found_mode))

46307

found_mode = mode;

46308

46309

if (found_mode != VOIDmode)

46310

Index: gcc/Makefile.in

46311

===================================================================

46312

--- a/src/gcc/Makefile.in (.../tags/gcc_4_8_2_release)

46313

+++ b/src/gcc/Makefile.in (.../branches/gcc-4_8-branch)

46314

@@ -747,7 +747,8 @@

46315

46316

# Native linker and preprocessor flags. For x-fragment overrides.

46317

BUILD_LDFLAGS=@BUILD_LDFLAGS@

46318

-BUILD_CPPFLAGS=$(ALL_CPPFLAGS)

46319

+BUILD_CPPFLAGS= -I. -I$(@D) -I$(srcdir) -I$(srcdir)/$(@D) \

46320

+ -I$(srcdir)/../include @INCINTL@ $(CPPINC) $(CPPFLAGS)

46321

46322

# Actual name to use when installing a native compiler.

46323

GCC_INSTALL_NAME := $(shell echo gcc|sed '$(program_transform_name)')

46324

@@ -1827,7 +1828,7 @@

46325

"$(MULTILIB_EXCLUSIONS)" \

46326

"$(MULTILIB_OSDIRNAMES)" \

46327

"$(MULTILIB_REQUIRED)" \

46328

- "$(MULTIARCH_DIRNAME)" \

46329

+ "$(if $(MULTILIB_OSDIRNAMES),,$(MULTIARCH_DIRNAME))" \

46330

"$(MULTILIB_REUSE)" \

46331

"@enable_multilib@" \

46332

> tmp-mlib.h; \

46333

@@ -2256,7 +2257,7 @@

46334

$(FUNCTION_H) $(TM_H) coretypes.h \

46335

$(TREE_PASS_H) $(BASIC_BLOCK_H) $(BITMAP_H) \

46336

$(FLAGS_H) $(HASHTAB_H) pointer-set.h \

46337

- $(GIMPLE_H) $(TREE_INLINE_H) $(GIMPLE_PRETTY_PRINT_H)

46338

+ $(GIMPLE_H) $(TREE_INLINE_H) $(GIMPLE_PRETTY_PRINT_H) $(PARAMS_H)

46339

tree-ssa.o : tree-ssa.c $(TREE_FLOW_H) $(CONFIG_H) $(SYSTEM_H) \

46340

$(TREE_H) $(TM_P_H) $(EXPR_H) $(DIAGNOSTIC_H) \

46341

toplev.h $(FUNCTION_H) $(TM_H) coretypes.h \

46342

@@ -3037,7 +3038,7 @@

46343

$(TM_H) coretypes.h $(GIMPLE_H) \

46344

$(TREE_PASS_H) $(FLAGS_H) $(EXPR_H) $(BASIC_BLOCK_H) \

46345

$(GGC_H) $(OBSTACK_H) $(PARAMS_H) $(CPPLIB_H) $(PARAMS_H) \

46346

- $(GIMPLE_PRETTY_PRINT_H) langhooks.h

46347

+ $(GIMPLE_PRETTY_PRINT_H) langhooks.h $(OPTABS_H)

46348

tree-complex.o : tree-complex.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TREE_H) \

46349

$(TM_H) $(FLAGS_H) $(TREE_FLOW_H) $(GIMPLE_H) \

46350

tree-iterator.h $(TREE_PASS_H) tree-ssa-propagate.h

46351

@@ -3276,12 +3277,12 @@

46352

$(TM_H) $(RTL_H) $(REGS_H) insn-config.h insn-codes.h $(DF_H) \

46353

$(RECOG_H) output.h addresses.h $(REGS_H) hard-reg-set.h $(FLAGS_H) \

46354

$(FUNCTION_H) $(EXPR_H) $(BASIC_BLOCK_H) $(TM_P_H) $(EXCEPT_H) \

46355

- ira.h rtl-error.h $(LRA_INT_H)

46356

+ ira.h rtl-error.h $(LRA_INT_H) $(OPTABS_H)

46357

lra-eliminations.o : lra-eliminations.c $(CONFIG_H) $(SYSTEM_H) coretypes.h \

46358

$(TM_H) $(RTL_H) $(REGS_H) insn-config.h $(DF_H) \

46359

$(RECOG_H) output.h $(REGS_H) hard-reg-set.h $(FLAGS_H) $(FUNCTION_H) \

46360

$(EXPR_H) $(BASIC_BLOCK_H) $(TM_P_H) $(EXCEPT_H) ira.h \

46361

- rtl-error.h $(LRA_INT_H)

46362

+ rtl-error.h $(LRA_INT_H) $(OPTABS_H)

46363

lra-lives.o : lra-lives.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \

46364

$(RTL_H) $(REGS_H) insn-config.h $(DF_H) \

46365

$(RECOG_H) output.h $(REGS_H) hard-reg-set.h $(FLAGS_H) $(FUNCTION_H) \

46366

Index: gcc/gimple.c

46367

===================================================================

46368

--- a/src/gcc/gimple.c (.../tags/gcc_4_8_2_release)

46369

+++ b/src/gcc/gimple.c (.../branches/gcc-4_8-branch)

46370

@@ -3841,42 +3841,46 @@

46371

46372

/* For the statement STMT call the callbacks VISIT_LOAD, VISIT_STORE and

46373

VISIT_ADDR if non-NULL on loads, store and address-taken operands

46374

- passing the STMT, the base of the operand and DATA to it. The base

46375

- will be either a decl, an indirect reference (including TARGET_MEM_REF)

46376

- or the argument of an address expression.

46377

+ passing the STMT, the base of the operand, the operand itself containing

46378

+ the base and DATA to it. The base will be either a decl, an indirect

46379

+ reference (including TARGET_MEM_REF) or the argument of an address

46380

+ expression.

46381

Returns the results of these callbacks or'ed. */

46382

46383

bool

46384

walk_stmt_load_store_addr_ops (gimple stmt, void *data,

46385

- bool (*visit_load)(gimple, tree, void *),

46386

- bool (*visit_store)(gimple, tree, void *),

46387

- bool (*visit_addr)(gimple, tree, void *))

46388

+ walk_stmt_load_store_addr_fn visit_load,

46389

+ walk_stmt_load_store_addr_fn visit_store,

46390

+ walk_stmt_load_store_addr_fn visit_addr)

46391

{

46392

bool ret = false;

46393

unsigned i;

46394

if (gimple_assign_single_p (stmt))

46395

{

46396

- tree lhs, rhs;

46397

+ tree lhs, rhs, arg;

46398

if (visit_store)

46399

{

46400

- lhs = get_base_loadstore (gimple_assign_lhs (stmt));

46401

+ arg = gimple_assign_lhs (stmt);

46402

+ lhs = get_base_loadstore (arg);

46403

if (lhs)

46404

- ret |= visit_store (stmt, lhs, data);

46405

+ ret |= visit_store (stmt, lhs, arg, data);

46406

}

46407

- rhs = gimple_assign_rhs1 (stmt);

46408

+ arg = gimple_assign_rhs1 (stmt);

46409

+ rhs = arg;

46410

while (handled_component_p (rhs))

46411

rhs = TREE_OPERAND (rhs, 0);

46412

if (visit_addr)

46413

{

46414

if (TREE_CODE (rhs) == ADDR_EXPR)

46415

- ret |= visit_addr (stmt, TREE_OPERAND (rhs, 0), data);

46416

+ ret |= visit_addr (stmt, TREE_OPERAND (rhs, 0), arg, data);

46417

else if (TREE_CODE (rhs) == TARGET_MEM_REF

46418

&& TREE_CODE (TMR_BASE (rhs)) == ADDR_EXPR)

46419

- ret |= visit_addr (stmt, TREE_OPERAND (TMR_BASE (rhs), 0), data);

46420

+ ret |= visit_addr (stmt, TREE_OPERAND (TMR_BASE (rhs), 0), arg,

46421

+ data);

46422

else if (TREE_CODE (rhs) == OBJ_TYPE_REF

46423

&& TREE_CODE (OBJ_TYPE_REF_OBJECT (rhs)) == ADDR_EXPR)

46424

ret |= visit_addr (stmt, TREE_OPERAND (OBJ_TYPE_REF_OBJECT (rhs),

46425

- 0), data);

46426

+ 0), arg, data);

46427

else if (TREE_CODE (rhs) == CONSTRUCTOR)

46428

{

46429

unsigned int ix;

46430

@@ -3884,23 +3888,23 @@

46431

46432

FOR_EACH_CONSTRUCTOR_VALUE (CONSTRUCTOR_ELTS (rhs), ix, val)

46433

if (TREE_CODE (val) == ADDR_EXPR)

46434

- ret |= visit_addr (stmt, TREE_OPERAND (val, 0), data);

46435

+ ret |= visit_addr (stmt, TREE_OPERAND (val, 0), arg, data);

46436

else if (TREE_CODE (val) == OBJ_TYPE_REF

46437

&& TREE_CODE (OBJ_TYPE_REF_OBJECT (val)) == ADDR_EXPR)

46438

ret |= visit_addr (stmt,

46439

TREE_OPERAND (OBJ_TYPE_REF_OBJECT (val),

46440

- 0), data);

46441

+ 0), arg, data);

46442

}

46443

lhs = gimple_assign_lhs (stmt);

46444

if (TREE_CODE (lhs) == TARGET_MEM_REF

46445

&& TREE_CODE (TMR_BASE (lhs)) == ADDR_EXPR)

46446

- ret |= visit_addr (stmt, TREE_OPERAND (TMR_BASE (lhs), 0), data);

46447

+ ret |= visit_addr (stmt, TREE_OPERAND (TMR_BASE (lhs), 0), lhs, data);

46448

}

46449

if (visit_load)

46450

{

46451

rhs = get_base_loadstore (rhs);

46452

if (rhs)

46453

- ret |= visit_load (stmt, rhs, data);

46454

+ ret |= visit_load (stmt, rhs, arg, data);

46455

}

46456

}

46457

else if (visit_addr

46458

@@ -3913,7 +3917,7 @@

46459

if (op == NULL_TREE)

46460

;

46461

else if (TREE_CODE (op) == ADDR_EXPR)

46462

- ret |= visit_addr (stmt, TREE_OPERAND (op, 0), data);

46463

+ ret |= visit_addr (stmt, TREE_OPERAND (op, 0), op, data);

46464

/* COND_EXPR and VCOND_EXPR rhs1 argument is a comparison

46465

tree with two operands. */

46466

else if (i == 1 && COMPARISON_CLASS_P (op))

46467

@@ -3920,10 +3924,10 @@

46468

{

46469

if (TREE_CODE (TREE_OPERAND (op, 0)) == ADDR_EXPR)

46470

ret |= visit_addr (stmt, TREE_OPERAND (TREE_OPERAND (op, 0),

46471

- 0), data);

46472

+ 0), op, data);

46473

if (TREE_CODE (TREE_OPERAND (op, 1)) == ADDR_EXPR)

46474

ret |= visit_addr (stmt, TREE_OPERAND (TREE_OPERAND (op, 1),

46475

- 0), data);

46476

+ 0), op, data);

46477

}

46478

}

46479

}

46480

@@ -3931,26 +3935,26 @@

46481

{

46482

if (visit_store)

46483

{

46484

- tree lhs = gimple_call_lhs (stmt);

46485

- if (lhs)

46486

+ tree arg = gimple_call_lhs (stmt);

46487

+ if (arg)

46488

{

46489

- lhs = get_base_loadstore (lhs);

46490

+ tree lhs = get_base_loadstore (arg);

46491

if (lhs)

46492

- ret |= visit_store (stmt, lhs, data);

46493

+ ret |= visit_store (stmt, lhs, arg, data);

46494

}

46495

}

46496

if (visit_load || visit_addr)

46497

for (i = 0; i < gimple_call_num_args (stmt); ++i)

46498

{

46499

- tree rhs = gimple_call_arg (stmt, i);

46500

+ tree arg = gimple_call_arg (stmt, i);

46501

if (visit_addr

46502

- && TREE_CODE (rhs) == ADDR_EXPR)

46503

- ret |= visit_addr (stmt, TREE_OPERAND (rhs, 0), data);

46504

+ && TREE_CODE (arg) == ADDR_EXPR)

46505

+ ret |= visit_addr (stmt, TREE_OPERAND (arg, 0), arg, data);

46506

else if (visit_load)

46507

{

46508

- rhs = get_base_loadstore (rhs);

46509

+ tree rhs = get_base_loadstore (arg);

46510

if (rhs)

46511

- ret |= visit_load (stmt, rhs, data);

46512

+ ret |= visit_load (stmt, rhs, arg, data);

46513

}

46514

}

46515

if (visit_addr

46516

@@ -3957,12 +3961,13 @@

46517

&& gimple_call_chain (stmt)

46518

&& TREE_CODE (gimple_call_chain (stmt)) == ADDR_EXPR)

46519

ret |= visit_addr (stmt, TREE_OPERAND (gimple_call_chain (stmt), 0),

46520

- data);

46521

+ gimple_call_chain (stmt), data);

46522

if (visit_addr

46523

&& gimple_call_return_slot_opt_p (stmt)

46524

&& gimple_call_lhs (stmt) != NULL_TREE

46525

&& TREE_ADDRESSABLE (TREE_TYPE (gimple_call_lhs (stmt))))

46526

- ret |= visit_addr (stmt, gimple_call_lhs (stmt), data);

46527

+ ret |= visit_addr (stmt, gimple_call_lhs (stmt),

46528

+ gimple_call_lhs (stmt), data);

46529

}

46530

else if (gimple_code (stmt) == GIMPLE_ASM)

46531

{

46532

@@ -3978,7 +3983,7 @@

46533

tree link = gimple_asm_output_op (stmt, i);

46534

tree op = get_base_loadstore (TREE_VALUE (link));

46535

if (op && visit_store)

46536

- ret |= visit_store (stmt, op, data);

46537

+ ret |= visit_store (stmt, op, TREE_VALUE (link), data);

46538

if (visit_addr)

46539

{

46540

constraint = TREE_STRING_POINTER

46541

@@ -3987,7 +3992,7 @@

46542

parse_output_constraint (&constraint, i, 0, 0, &allows_mem,

46543

&allows_reg, &is_inout);

46544

if (op && !allows_reg && allows_mem)

46545

- ret |= visit_addr (stmt, op, data);

46546

+ ret |= visit_addr (stmt, op, TREE_VALUE (link), data);

46547

}

46548

}

46549

if (visit_load || visit_addr)

46550

@@ -3997,7 +4002,7 @@

46551

tree op = TREE_VALUE (link);

46552

if (visit_addr

46553

&& TREE_CODE (op) == ADDR_EXPR)

46554

- ret |= visit_addr (stmt, TREE_OPERAND (op, 0), data);

46555

+ ret |= visit_addr (stmt, TREE_OPERAND (op, 0), op, data);

46556

else if (visit_load || visit_addr)

46557

{

46558

op = get_base_loadstore (op);

46559

@@ -4004,7 +4009,7 @@

46560

if (op)

46561

{

46562

if (visit_load)

46563

- ret |= visit_load (stmt, op, data);

46564

+ ret |= visit_load (stmt, op, TREE_VALUE (link), data);

46565

if (visit_addr)

46566

{

46567

constraint = TREE_STRING_POINTER

46568

@@ -4013,7 +4018,8 @@

46569

0, oconstraints,

46570

&allows_mem, &allows_reg);

46571

if (!allows_reg && allows_mem)

46572

- ret |= visit_addr (stmt, op, data);

46573

+ ret |= visit_addr (stmt, op, TREE_VALUE (link),

46574

+ data);

46575

}

46576

}

46577

}

46578

@@ -4026,12 +4032,12 @@

46579

{

46580

if (visit_addr

46581

&& TREE_CODE (op) == ADDR_EXPR)

46582

- ret |= visit_addr (stmt, TREE_OPERAND (op, 0), data);

46583

+ ret |= visit_addr (stmt, TREE_OPERAND (op, 0), op, data);

46584

else if (visit_load)

46585

{

46586

- op = get_base_loadstore (op);

46587

- if (op)

46588

- ret |= visit_load (stmt, op, data);

46589

+ tree base = get_base_loadstore (op);

46590

+ if (base)

46591

+ ret |= visit_load (stmt, base, op, data);

46592

}

46593

}

46594

}

46595

@@ -4042,7 +4048,7 @@

46596

{

46597

tree op = PHI_ARG_DEF (stmt, i);

46598

if (TREE_CODE (op) == ADDR_EXPR)

46599

- ret |= visit_addr (stmt, TREE_OPERAND (op, 0), data);

46600

+ ret |= visit_addr (stmt, TREE_OPERAND (op, 0), op, data);

46601

}

46602

}

46603

else if (visit_addr

46604

@@ -4050,7 +4056,7 @@

46605

{

46606

tree op = gimple_goto_dest (stmt);

46607

if (TREE_CODE (op) == ADDR_EXPR)

46608

- ret |= visit_addr (stmt, TREE_OPERAND (op, 0), data);

46609

+ ret |= visit_addr (stmt, TREE_OPERAND (op, 0), op, data);

46610

}

46611

46612

return ret;

46613

@@ -4061,8 +4067,8 @@

46614

46615

bool

46616

walk_stmt_load_store_ops (gimple stmt, void *data,

46617

- bool (*visit_load)(gimple, tree, void *),

46618

- bool (*visit_store)(gimple, tree, void *))

46619

+ walk_stmt_load_store_addr_fn visit_load,

46620

+ walk_stmt_load_store_addr_fn visit_store)

46621

{

46622

return walk_stmt_load_store_addr_ops (stmt, data,

46623

visit_load, visit_store, NULL);

46624

@@ -4071,8 +4077,7 @@

46625

/* Helper for gimple_ior_addresses_taken_1. */

46626

46627

static bool

46628

-gimple_ior_addresses_taken_1 (gimple stmt ATTRIBUTE_UNUSED,

46629

- tree addr, void *data)

46630

+gimple_ior_addresses_taken_1 (gimple, tree addr, tree, void *data)

46631

{

46632

bitmap addresses_taken = (bitmap)data;

46633

addr = get_base_address (addr);

46634

Index: gcc/tree-ssa-structalias.c

46635

===================================================================

46636

--- a/src/gcc/tree-ssa-structalias.c (.../tags/gcc_4_8_2_release)

46637

+++ b/src/gcc/tree-ssa-structalias.c (.../branches/gcc-4_8-branch)

46638

@@ -949,24 +949,27 @@

46639

bitmap_set_bit (result, i);

46640

else

46641

{

46642

- unsigned HOST_WIDE_INT fieldoffset = vi->offset + offset;

46643

+ HOST_WIDE_INT fieldoffset = vi->offset + offset;

46644

+ unsigned HOST_WIDE_INT size = vi->size;

46645

46646

/* If the offset makes the pointer point to before the

46647

variable use offset zero for the field lookup. */

46648

- if (offset < 0

46649

- && fieldoffset > vi->offset)

46650

- fieldoffset = 0;

46651

-

46652

- if (offset != 0)

46653

+ if (fieldoffset < 0)

46654

+ vi = lookup_vi_for_tree (vi->decl);

46655

+ else

46656

vi = first_or_preceding_vi_for_offset (vi, fieldoffset);

46657

46658

- bitmap_set_bit (result, vi->id);

46659

- /* If the result is not exactly at fieldoffset include the next

46660

- field as well. See get_constraint_for_ptr_offset for more

46661

- rationale. */

46662

- if (vi->offset != fieldoffset

46663

- && vi->next != NULL)

46664

- bitmap_set_bit (result, vi->next->id);

46665

+ do

46666

+ {

46667

+ bitmap_set_bit (result, vi->id);

46668

+ if (!vi->next)

46669

+ break;

46670

+

46671

+ /* We have to include all fields that overlap the current field

46672

+ shifted by offset. */

46673

+ vi = vi->next;

46674

+ }

46675

+ while (vi->offset < fieldoffset + size);

46676

}

46677

}

46678

46679

@@ -1607,16 +1610,21 @@

46680

{

46681

varinfo_t v = get_varinfo (j);

46682

HOST_WIDE_INT fieldoffset = v->offset + roffset;

46683

+ unsigned HOST_WIDE_INT size = v->size;

46684

unsigned int t;

46685

46686

if (v->is_full_var)

46687

- fieldoffset = v->offset;

46688

+ ;

46689

else if (roffset != 0)

46690

- v = first_vi_for_offset (v, fieldoffset);

46691

- /* If the access is outside of the variable we can ignore it. */

46692

- if (!v)

46693

- continue;

46694

+ {

46695

+ if (fieldoffset < 0)

46696

+ v = lookup_vi_for_tree (v->decl);

46697

+ else

46698

+ v = first_or_preceding_vi_for_offset (v, fieldoffset);

46699

+ }

46700

46701

+ /* We have to include all fields that overlap the current field

46702

+ shifted by roffset. */

46703

do

46704

{

46705

t = find (v->id);

46706

@@ -1633,16 +1641,13 @@

46707

&& add_graph_edge (graph, lhs, t))

46708

flag |= bitmap_ior_into (sol, get_varinfo (t)->solution);

46709

46710

- /* If the variable is not exactly at the requested offset

46711

- we have to include the next one. */

46712

- if (v->offset == (unsigned HOST_WIDE_INT)fieldoffset

46713

+ if (v->is_full_var

46714

|| v->next == NULL)

46715

break;

46716

46717

v = v->next;

46718

- fieldoffset = v->offset;

46719

}

46720

- while (1);

46721

+ while (v->offset < fieldoffset + size);

46722

}

46723

46724

done:

46725

@@ -1705,15 +1710,20 @@

46726

varinfo_t v = get_varinfo (j);

46727

unsigned int t;

46728

HOST_WIDE_INT fieldoffset = v->offset + loff;

46729

+ unsigned HOST_WIDE_INT size = v->size;

46730

46731

if (v->is_full_var)

46732

- fieldoffset = v->offset;

46733

+ ;

46734

else if (loff != 0)

46735

- v = first_vi_for_offset (v, fieldoffset);

46736

- /* If the access is outside of the variable we can ignore it. */

46737

- if (!v)

46738

- continue;

46739

+ {

46740

+ if (fieldoffset < 0)

46741

+ v = lookup_vi_for_tree (v->decl);

46742

+ else

46743

+ v = first_or_preceding_vi_for_offset (v, fieldoffset);

46744

+ }

46745

46746

+ /* We have to include all fields that overlap the current field

46747

+ shifted by loff. */

46748

do

46749

{

46750

if (v->may_have_pointers)

46751

@@ -1739,16 +1749,13 @@

46752

bitmap_set_bit (changed, t);

46753

}

46754

46755

- /* If the variable is not exactly at the requested offset

46756

- we have to include the next one. */

46757

- if (v->offset == (unsigned HOST_WIDE_INT)fieldoffset

46758

+ if (v->is_full_var

46759

|| v->next == NULL)

46760

break;

46761

46762

v = v->next;

46763

- fieldoffset = v->offset;

46764

}

46765

- while (1);

46766

+ while (v->offset < fieldoffset + size);

46767

}

46768

}

46769

46770

@@ -2997,35 +3004,30 @@

46771

varinfo_t temp;

46772

unsigned HOST_WIDE_INT offset = curr->offset + rhsoffset;

46773

46774

- /* Search the sub-field which overlaps with the

46775

- pointed-to offset. If the result is outside of the variable

46776

- we have to provide a conservative result, as the variable is

46777

- still reachable from the resulting pointer (even though it

46778

- technically cannot point to anything). The last and first

46779

- sub-fields are such conservative results.

46780

- ??? If we always had a sub-field for &object + 1 then

46781

- we could represent this in a more precise way. */

46782

+ /* If curr->offset + rhsoffset is less than zero adjust it. */

46783

if (rhsoffset < 0

46784

&& curr->offset < offset)

46785

offset = 0;

46786

+

46787

+ /* We have to include all fields that overlap the current

46788

+ field shifted by rhsoffset. And we include at least

46789

+ the last or the first field of the variable to represent

46790

+ reachability of off-bound addresses, in particular &object + 1,

46791

+ conservatively correct. */

46792

temp = first_or_preceding_vi_for_offset (curr, offset);

46793

-

46794

- /* If the found variable is not exactly at the pointed to

46795

- result, we have to include the next variable in the

46796

- solution as well. Otherwise two increments by offset / 2

46797

- do not result in the same or a conservative superset

46798

- solution. */

46799

- if (temp->offset != offset

46800

- && temp->next != NULL)

46801

+ c.var = temp->id;

46802

+ c.offset = 0;

46803

+ temp = temp->next;

46804

+ while (temp

46805

+ && temp->offset < offset + curr->size)

46806

{

46807

struct constraint_expr c2;

46808

- c2.var = temp->next->id;

46809

+ c2.var = temp->id;

46810

c2.type = ADDRESSOF;

46811

c2.offset = 0;

46812

results->safe_push (c2);

46813

+ temp = temp->next;

46814

}

46815

- c.var = temp->id;

46816

- c.offset = 0;

46817

}

46818

else

46819

c.offset = rhsoffset;

46820

Index: gcc/gimple.h

46821

===================================================================

46822

--- a/src/gcc/gimple.h (.../tags/gcc_4_8_2_release)

46823

+++ b/src/gcc/gimple.h (.../branches/gcc-4_8-branch)

46824

@@ -176,6 +176,9 @@

46825

/* Nonzero if this statement contains volatile operands. */

46826

unsigned has_volatile_ops : 1;

46827

46828

+ /* Padding to get subcode to 16 bit alignment. */

46829

+ unsigned pad : 1;

46830

+

46831

/* The SUBCODE field can be used for tuple-specific flags for tuples

46832

that do not require subcodes. Note that SUBCODE should be at

46833

least as wide as tree codes, as several tuples store tree codes

46834

@@ -888,13 +891,14 @@

46835

extern alias_set_type gimple_get_alias_set (tree);

46836

extern void count_uses_and_derefs (tree, gimple, unsigned *, unsigned *,

46837

unsigned *);

46838

+typedef bool (*walk_stmt_load_store_addr_fn) (gimple, tree, tree, void *);

46839

extern bool walk_stmt_load_store_addr_ops (gimple, void *,

46840

- bool (*)(gimple, tree, void *),

46841

- bool (*)(gimple, tree, void *),

46842

- bool (*)(gimple, tree, void *));

46843

+ walk_stmt_load_store_addr_fn,

46844

+ walk_stmt_load_store_addr_fn,

46845

+ walk_stmt_load_store_addr_fn);

46846

extern bool walk_stmt_load_store_ops (gimple, void *,

46847

- bool (*)(gimple, tree, void *),

46848

- bool (*)(gimple, tree, void *));

46849

+ walk_stmt_load_store_addr_fn,

46850

+ walk_stmt_load_store_addr_fn);

46851

extern bool gimple_ior_addresses_taken (bitmap, gimple);

46852

extern bool gimple_call_builtin_p (gimple, enum built_in_class);

46853

extern bool gimple_call_builtin_p (gimple, enum built_in_function);

46854

Index: gcc/tree-cfg.c

46855

===================================================================

46856

--- a/src/gcc/tree-cfg.c (.../tags/gcc_4_8_2_release)

46857

+++ b/src/gcc/tree-cfg.c (.../branches/gcc-4_8-branch)

46858

@@ -104,7 +104,6 @@

46859

static void assign_discriminator (location_t, basic_block);

46860

static edge gimple_redirect_edge_and_branch (edge, basic_block);

46861

static edge gimple_try_redirect_by_replacing_jump (edge, basic_block);

46862

-static unsigned int split_critical_edges (void);

46863

46864

/* Various helpers. */

46865

static inline bool stmt_starts_bb_p (gimple, gimple);

46866

@@ -1535,6 +1534,11 @@

46867

46868

FOR_EACH_IMM_USE_STMT (stmt, imm_iter, name)

46869

{

46870

+ /* Mark the block if we change the last stmt in it. */

46871

+ if (cfgcleanup_altered_bbs

46872

+ && stmt_ends_bb_p (stmt))

46873

+ bitmap_set_bit (cfgcleanup_altered_bbs, gimple_bb (stmt)->index);

46874

+

46875

FOR_EACH_IMM_USE_ON_STMT (use, imm_iter)

46876

{

46877

replace_exp (use, val);

46878

@@ -1559,11 +1563,6 @@

46879

gimple orig_stmt = stmt;

46880

size_t i;

46881

46882

- /* Mark the block if we changed the last stmt in it. */

46883

- if (cfgcleanup_altered_bbs

46884

- && stmt_ends_bb_p (stmt))

46885

- bitmap_set_bit (cfgcleanup_altered_bbs, gimple_bb (stmt)->index);

46886

-

46887

/* FIXME. It shouldn't be required to keep TREE_CONSTANT

46888

on ADDR_EXPRs up-to-date on GIMPLE. Propagation will

46889

only change sth from non-invariant to invariant, and only

46890

@@ -3513,11 +3512,10 @@

46891

case PLUS_EXPR:

46892

case MINUS_EXPR:

46893

{

46894

- /* We use regular PLUS_EXPR and MINUS_EXPR for vectors.

46895

- ??? This just makes the checker happy and may not be what is

46896

- intended. */

46897

- if (TREE_CODE (lhs_type) == VECTOR_TYPE

46898

- && POINTER_TYPE_P (TREE_TYPE (lhs_type)))

46899

+ tree lhs_etype = lhs_type;

46900

+ tree rhs1_etype = rhs1_type;

46901

+ tree rhs2_etype = rhs2_type;

46902

+ if (TREE_CODE (lhs_type) == VECTOR_TYPE)

46903

{

46904

if (TREE_CODE (rhs1_type) != VECTOR_TYPE

46905

|| TREE_CODE (rhs2_type) != VECTOR_TYPE)

46906

@@ -3525,22 +3523,13 @@

46907

error ("invalid non-vector operands to vector valued plus");

46908

return true;

46909

}

46910

- lhs_type = TREE_TYPE (lhs_type);

46911

- rhs1_type = TREE_TYPE (rhs1_type);

46912

- rhs2_type = TREE_TYPE (rhs2_type);

46913

- /* PLUS_EXPR is commutative, so we might end up canonicalizing

46914

- the pointer to 2nd place. */

46915

- if (POINTER_TYPE_P (rhs2_type))

46916

- {

46917

- tree tem = rhs1_type;

46918

- rhs1_type = rhs2_type;

46919

- rhs2_type = tem;

46920

- }

46921

- goto do_pointer_plus_expr_check;

46922

+ lhs_etype = TREE_TYPE (lhs_type);

46923

+ rhs1_etype = TREE_TYPE (rhs1_type);

46924

+ rhs2_etype = TREE_TYPE (rhs2_type);

46925

}

46926

- if (POINTER_TYPE_P (lhs_type)

46927

- || POINTER_TYPE_P (rhs1_type)

46928

- || POINTER_TYPE_P (rhs2_type))

46929

+ if (POINTER_TYPE_P (lhs_etype)

46930

+ || POINTER_TYPE_P (rhs1_etype)

46931

+ || POINTER_TYPE_P (rhs2_etype))

46932

{

46933

error ("invalid (pointer) operands to plus/minus");

46934

return true;

46935

@@ -3552,7 +3541,6 @@

46936

46937

case POINTER_PLUS_EXPR:

46938

{

46939

-do_pointer_plus_expr_check:

46940

if (!POINTER_TYPE_P (rhs1_type)

46941

|| !useless_type_conversion_p (lhs_type, rhs1_type)

46942

|| !ptrofftype_p (rhs2_type))

46943

@@ -7658,7 +7646,7 @@

46944

46945

/* Split all critical edges. */

46946

46947

-static unsigned int

46948

+unsigned int

46949

split_critical_edges (void)

46950

{

46951

basic_block bb;

46952

Index: gcc/passes.c

46953

===================================================================

46954

--- a/src/gcc/passes.c (.../tags/gcc_4_8_2_release)

46955

+++ b/src/gcc/passes.c (.../branches/gcc-4_8-branch)

46956

@@ -1398,6 +1398,7 @@

46957

/* After CCP we rewrite no longer addressed locals into SSA

46958

form if possible. */

46959

NEXT_PASS (pass_forwprop);

46960

+ NEXT_PASS (pass_object_sizes);

46961

/* pass_build_alias is a dummy pass that ensures that we

46962

execute TODO_rebuild_alias at this point. */

46963

NEXT_PASS (pass_build_alias);

46964

@@ -1435,7 +1436,6 @@

46965

NEXT_PASS (pass_dce);

46966

NEXT_PASS (pass_forwprop);

46967

NEXT_PASS (pass_phiopt);

46968

- NEXT_PASS (pass_object_sizes);

46969

NEXT_PASS (pass_strlen);

46970

NEXT_PASS (pass_ccp);

46971

/* After CCP we rewrite no longer addressed locals into SSA

46972

Index: gcc/tree-ssa-reassoc.c

46973

===================================================================

46974

--- a/src/gcc/tree-ssa-reassoc.c (.../tags/gcc_4_8_2_release)

46975

+++ b/src/gcc/tree-ssa-reassoc.c (.../branches/gcc-4_8-branch)

46976

@@ -785,8 +785,7 @@

46977

if (opcode == BIT_AND_EXPR)

46978

oe->op = build_zero_cst (TREE_TYPE (oe->op));

46979

else if (opcode == BIT_IOR_EXPR)

46980

- oe->op = build_low_bits_mask (TREE_TYPE (oe->op),

46981

- TYPE_PRECISION (TREE_TYPE (oe->op)));

46982

+ oe->op = build_all_ones_cst (TREE_TYPE (oe->op));

46983

46984

reassociate_stats.ops_eliminated += ops->length () - 1;

46985

ops->truncate (0);

46986

@@ -1980,8 +1979,15 @@

46987

46988

tem = fold_convert_loc (loc, optype, tem);

46989

gsi = gsi_for_stmt (stmt);

46990

- tem = force_gimple_operand_gsi (&gsi, tem, true, NULL_TREE, true,

46991

- GSI_SAME_STMT);

46992

+ /* In rare cases range->exp can be equal to lhs of stmt.

46993

+ In that case we have to insert after the stmt rather then before

46994

+ it. */

46995

+ if (op == range->exp)

46996

+ tem = force_gimple_operand_gsi (&gsi, tem, true, NULL_TREE, false,

46997

+ GSI_SAME_STMT);

46998

+ else

46999

+ tem = force_gimple_operand_gsi (&gsi, tem, true, NULL_TREE, true,

47000

+ GSI_SAME_STMT);

47001

47002

/* If doing inter-bb range test optimization, update the

47003

stmts immediately. Start with changing the first range test

47004

Index: gcc/config/s390/s390.c

47005

===================================================================

47006

--- a/src/gcc/config/s390/s390.c (.../tags/gcc_4_8_2_release)

47007

+++ b/src/gcc/config/s390/s390.c (.../branches/gcc-4_8-branch)

47008

@@ -407,6 +407,65 @@

47009

bytes on a z10 (or higher) CPU. */

47010

#define PREDICT_DISTANCE (TARGET_Z10 ? 384 : 2048)

47011

47012

+static const int s390_hotpatch_trampoline_halfwords_default = 12;

47013

+static const int s390_hotpatch_trampoline_halfwords_max = 1000000;

47014

+static int s390_hotpatch_trampoline_halfwords = -1;

47015

+

47016

+/* Return the argument of the given hotpatch attribute or the default value if

47017

+ no argument is present. */

47018

+

47019

+static inline int

47020

+get_hotpatch_attribute (tree hotpatch_attr)

47021

+{

47022

+ const_tree args;

47023

+

47024

+ args = TREE_VALUE (hotpatch_attr);

47025

+

47026

+ return (args) ?

47027

+ TREE_INT_CST_LOW (TREE_VALUE (args)):

47028

+ s390_hotpatch_trampoline_halfwords_default;

47029

+}

47030

+

47031

+/* Check whether the hotpatch attribute is applied to a function and, if it has

47032

+ an argument, the argument is valid. */

47033

+

47034

+static tree

47035

+s390_handle_hotpatch_attribute (tree *node, tree name, tree args,

47036

+ int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)

47037

+{

47038

+ if (TREE_CODE (*node) != FUNCTION_DECL)

47039

+ {

47040

+ warning (OPT_Wattributes, "%qE attribute only applies to functions",

47041

+ name);

47042

+ *no_add_attrs = true;

47043

+ }

47044

+ else if (args)

47045

+ {

47046

+ tree expr = TREE_VALUE (args);

47047

+

47048

+ if (TREE_CODE (expr) != INTEGER_CST

47049

+ || !INTEGRAL_TYPE_P (TREE_TYPE (expr))

47050

+ || TREE_INT_CST_HIGH (expr) != 0

47051

+ || TREE_INT_CST_LOW (expr) > (unsigned int)

47052

+ s390_hotpatch_trampoline_halfwords_max)

47053

+ {

47054

+ error ("requested %qE attribute is not a non-negative integer"

47055

+ " constant or too large (max. %d)", name,

47056

+ s390_hotpatch_trampoline_halfwords_max);

47057

+ *no_add_attrs = true;

47058

+ }

47059

+ }

47060

+

47061

+ return NULL_TREE;

47062

+}

47063

+

47064

+static const struct attribute_spec s390_attribute_table[] = {

47065

+ { "hotpatch", 0, 1, true, false, false, s390_handle_hotpatch_attribute, false

47066

+ },

47067

+ /* End element. */

47068

+ { NULL, 0, 0, false, false, false, NULL, false }

47069

+};

47070

+

47071

/* Return the alignment for LABEL. We default to the -falign-labels

47072

value except for the literal pool base label. */

47073

int

47074

@@ -883,7 +942,8 @@

47075

{

47076

/* For CCRAWmode put the required cc mask into the second

47077

operand. */

47078

- if (GET_MODE (XVECEXP (*op0, 0, 0)) == CCRAWmode)

47079

+ if (GET_MODE (XVECEXP (*op0, 0, 0)) == CCRAWmode

47080

+ && INTVAL (*op1) >= 0 && INTVAL (*op1) <= 3)

47081

*op1 = gen_rtx_CONST_INT (VOIDmode, 1 << (3 - INTVAL (*op1)));

47082

*op0 = XVECEXP (*op0, 0, 0);

47083

*code = new_code;

47084

@@ -1594,6 +1654,46 @@

47085

static void

47086

s390_option_override (void)

47087

{

47088

+ unsigned int i;

47089

+ cl_deferred_option *opt;

47090

+ vec<cl_deferred_option> *v =

47091

+ (vec<cl_deferred_option> *) s390_deferred_options;

47092

+

47093

+ if (v)

47094

+ FOR_EACH_VEC_ELT (*v, i, opt)

47095

+ {

47096

+ switch (opt->opt_index)

47097

+ {

47098

+ case OPT_mhotpatch:

47099

+ s390_hotpatch_trampoline_halfwords = (opt->value) ?

47100

+ s390_hotpatch_trampoline_halfwords_default : -1;

47101

+ break;

47102

+ case OPT_mhotpatch_:

47103

+ {

47104

+ int val;

47105

+

47106

+ val = integral_argument (opt->arg);

47107

+ if (val == -1)

47108

+ {

47109

+ /* argument is not a plain number */

47110

+ error ("argument to %qs should be a non-negative integer",

47111

+ "-mhotpatch=");

47112

+ break;

47113

+ }

47114

+ else if (val > s390_hotpatch_trampoline_halfwords_max)

47115

+ {

47116

+ error ("argument to %qs is too large (max. %d)",

47117

+ "-mhotpatch=", s390_hotpatch_trampoline_halfwords_max);

47118

+ break;

47119

+ }

47120

+ s390_hotpatch_trampoline_halfwords = val;

47121

+ break;

47122

+ }

47123

+ default:

47124

+ gcc_unreachable ();

47125

+ }

47126

+ }

47127

+

47128

/* Set up function hooks. */

47129

init_machine_status = s390_init_machine_status;

47130

47131

@@ -3015,15 +3115,22 @@

47132

prefer ADDR_REGS. If 'class' is not a superset

47133

of ADDR_REGS, e.g. FP_REGS, reject this reload. */

47134

case CONST:

47135

- /* A larl operand with odd addend will get fixed via secondary

47136

- reload. So don't request it to be pushed into literal

47137

- pool. */

47138

+ /* Symrefs cannot be pushed into the literal pool with -fPIC

47139

+ so we *MUST NOT* return NO_REGS for these cases

47140

+ (s390_cannot_force_const_mem will return true).

47141

+

47142

+ On the other hand we MUST return NO_REGS for symrefs with

47143

+ invalid addend which might have been pushed to the literal

47144

+ pool (no -fPIC). Usually we would expect them to be

47145

+ handled via secondary reload but this does not happen if

47146

+ they are used as literal pool slot replacement in reload

47147

+ inheritance (see emit_input_reload_insns). */

47148

if (TARGET_CPU_ZARCH

47149

&& GET_CODE (XEXP (op, 0)) == PLUS

47150

&& GET_CODE (XEXP (XEXP(op, 0), 0)) == SYMBOL_REF

47151

&& GET_CODE (XEXP (XEXP(op, 0), 1)) == CONST_INT)

47152

{

47153

- if (reg_class_subset_p (ADDR_REGS, rclass))

47154

+ if (flag_pic && reg_class_subset_p (ADDR_REGS, rclass))

47155

return ADDR_REGS;

47156

else

47157

return NO_REGS;

47158

@@ -4683,7 +4790,7 @@

47159

int smode_bsize, mode_bsize;

47160

rtx op, clobber;

47161

47162

- if (bitsize + bitpos > GET_MODE_SIZE (mode))

47163

+ if (bitsize + bitpos > GET_MODE_BITSIZE (mode))

47164

return false;

47165

47166

/* Generate INSERT IMMEDIATE (IILL et al). */

47167

@@ -5311,6 +5418,101 @@

47168

gcc_unreachable ();

47169

}

47170

47171

+/* Returns -1 if the function should not be made hotpatchable. Otherwise it

47172

+ returns a number >= 0 that is the desired size of the hotpatch trampoline

47173

+ in halfwords. */

47174

+

47175

+static int s390_function_num_hotpatch_trampoline_halfwords (tree decl,

47176

+ bool do_warn)

47177

+{

47178

+ tree attr;

47179

+

47180

+ if (DECL_DECLARED_INLINE_P (decl)

47181

+ || DECL_ARTIFICIAL (decl)

47182

+ || MAIN_NAME_P (DECL_NAME (decl)))

47183

+ {

47184

+ /* - Explicitly inlined functions cannot be hotpatched.

47185

+ - Artificial functions need not be hotpatched.

47186

+ - Making the main function hotpatchable is useless. */

47187

+ return -1;

47188

+ }

47189

+ attr = lookup_attribute ("hotpatch", DECL_ATTRIBUTES (decl));

47190

+ if (attr || s390_hotpatch_trampoline_halfwords >= 0)

47191

+ {

47192

+ if (lookup_attribute ("always_inline", DECL_ATTRIBUTES (decl)))

47193

+ {

47194

+ if (do_warn)

47195

+ warning (OPT_Wattributes, "function %qE with the %qs attribute"

47196

+ " is not hotpatchable", DECL_NAME (decl), "always_inline");

47197

+ return -1;

47198

+ }

47199

+ else

47200

+ {

47201

+ return (attr) ?

47202

+ get_hotpatch_attribute (attr) : s390_hotpatch_trampoline_halfwords;

47203

+ }

47204

+ }

47205

+

47206

+ return -1;

47207

+}

47208

+

47209

+/* Hook to determine if one function can safely inline another. */

47210

+

47211

+static bool

47212

+s390_can_inline_p (tree caller, tree callee)

47213

+{

47214

+ if (s390_function_num_hotpatch_trampoline_halfwords (callee, false) >= 0)

47215

+ return false;

47216

+

47217

+ return default_target_can_inline_p (caller, callee);

47218

+}

47219

+

47220

+/* Write the extra assembler code needed to declare a function properly. */

47221

+

47222

+void

47223

+s390_asm_output_function_label (FILE *asm_out_file, const char *fname,

47224

+ tree decl)

47225

+{

47226

+ int hotpatch_trampoline_halfwords = -1;

47227

+

47228

+ if (decl)

47229

+ {

47230

+ hotpatch_trampoline_halfwords =

47231

+ s390_function_num_hotpatch_trampoline_halfwords (decl, true);

47232

+ if (hotpatch_trampoline_halfwords >= 0

47233

+ && decl_function_context (decl) != NULL_TREE)

47234

+ {

47235

+ warning_at (DECL_SOURCE_LOCATION (decl), OPT_mhotpatch,

47236

+ "hotpatching is not compatible with nested functions");

47237

+ hotpatch_trampoline_halfwords = -1;

47238

+ }

47239

+ }

47240

+

47241

+ if (hotpatch_trampoline_halfwords > 0)

47242

+ {

47243

+ int i;

47244

+

47245

+ /* Add a trampoline code area before the function label and initialize it

47246

+ with two-byte nop instructions. This area can be overwritten with code

47247

+ that jumps to a patched version of the function. */

47248

+ for (i = 0; i < hotpatch_trampoline_halfwords; i++)

47249

+ asm_fprintf (asm_out_file, "\tnopr\t%%r7\n");

47250

+ /* Note: The function label must be aligned so that (a) the bytes of the

47251

+ following nop do not cross a cacheline boundary, and (b) a jump address

47252

+ (eight bytes for 64 bit targets, 4 bytes for 32 bit targets) can be

47253

+ stored directly before the label without crossing a cacheline

47254

+ boundary. All this is necessary to make sure the trampoline code can

47255

+ be changed atomically. */

47256

+ }

47257

+

47258

+ ASM_OUTPUT_LABEL (asm_out_file, fname);

47259

+

47260

+ /* Output a four-byte nop if hotpatching is enabled. This can be overwritten

47261

+ atomically with a relative backwards jump to the trampoline area. */

47262

+ if (hotpatch_trampoline_halfwords >= 0)

47263

+ asm_fprintf (asm_out_file, "\tnop\t0\n");

47264

+}

47265

+

47266

/* Output machine-dependent UNSPECs occurring in address constant X

47267

in assembler syntax to stdio stream FILE. Returns true if the

47268

constant X could be recognized, false otherwise. */

47269

@@ -7846,6 +8048,9 @@

47270

{

47271

bb = BASIC_BLOCK (bb_index);

47272

47273

+ if (!bb)

47274

+ continue;

47275

+

47276

FOR_BB_INSNS (bb, insn)

47277

{

47278

rtx ite, cc, pat, target;

47279

@@ -7959,7 +8164,10 @@

47280

if (!result)

47281

return;

47282

47283

- PATTERN (tbegin_insn) = XVECEXP (PATTERN (tbegin_insn), 0, 0);

47284

+ PATTERN (tbegin_insn) = gen_rtx_PARALLEL (VOIDmode,

47285

+ gen_rtvec (2,

47286

+ XVECEXP (PATTERN (tbegin_insn), 0, 0),

47287

+ XVECEXP (PATTERN (tbegin_insn), 0, 1)));

47288

INSN_CODE (tbegin_insn) = -1;

47289

df_insn_rescan (tbegin_insn);

47290

47291

@@ -9568,61 +9776,47 @@

47292

void

47293

s390_expand_tbegin (rtx dest, rtx tdb, rtx retry, bool clobber_fprs_p)

47294

{

47295

- const int CC0 = 1 << 3;

47296

- const int CC1 = 1 << 2;

47297

- const int CC3 = 1 << 0;

47298

- rtx abort_label = gen_label_rtx ();

47299

- rtx leave_label = gen_label_rtx ();

47300

+ rtx retry_plus_two = gen_reg_rtx (SImode);

47301

rtx retry_reg = gen_reg_rtx (SImode);

47302

rtx retry_label = NULL_RTX;

47303

- rtx jump;

47304

- rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1);

47305

47306

if (retry != NULL_RTX)

47307

{

47308

emit_move_insn (retry_reg, retry);

47309

+ emit_insn (gen_addsi3 (retry_plus_two, retry_reg, const2_rtx));

47310

+ emit_insn (gen_addsi3 (retry_reg, retry_reg, const1_rtx));

47311

retry_label = gen_label_rtx ();

47312

emit_label (retry_label);

47313

}

47314

47315

if (clobber_fprs_p)

47316

- emit_insn (gen_tbegin_1 (tdb,

47317

- gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK)));

47318

+ emit_insn (gen_tbegin_1 (gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK), tdb));

47319

else

47320

- emit_insn (gen_tbegin_nofloat_1 (tdb,

47321

- gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK)));

47322

+ emit_insn (gen_tbegin_nofloat_1 (gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK),

47323

+ tdb));

47324

47325

- jump = s390_emit_jump (abort_label,

47326

- gen_rtx_NE (VOIDmode,

47327

- gen_rtx_REG (CCRAWmode, CC_REGNUM),

47328

- gen_rtx_CONST_INT (VOIDmode, CC0)));

47329

-

47330

- JUMP_LABEL (jump) = abort_label;

47331

- LABEL_NUSES (abort_label) = 1;

47332

- add_reg_note (jump, REG_BR_PROB, very_unlikely);

47333

-

47334

- /* Initialize CC return value. */

47335

- emit_move_insn (dest, const0_rtx);

47336

-

47337

- s390_emit_jump (leave_label, NULL_RTX);

47338

- LABEL_NUSES (leave_label) = 1;

47339

- emit_barrier ();

47340

-

47341

- /* Abort handler code. */

47342

-

47343

- emit_label (abort_label);

47344

+ emit_move_insn (dest, gen_rtx_UNSPEC (SImode,

47345

+ gen_rtvec (1, gen_rtx_REG (CCRAWmode,

47346

+ CC_REGNUM)),

47347

+ UNSPEC_CC_TO_INT));

47348

if (retry != NULL_RTX)

47349

{

47350

+ const int CC0 = 1 << 3;

47351

+ const int CC1 = 1 << 2;

47352

+ const int CC3 = 1 << 0;

47353

+ rtx jump;

47354

rtx count = gen_reg_rtx (SImode);

47355

+ rtx leave_label = gen_label_rtx ();

47356

+

47357

+ /* Exit for success and permanent failures. */

47358

jump = s390_emit_jump (leave_label,

47359

gen_rtx_EQ (VOIDmode,

47360

gen_rtx_REG (CCRAWmode, CC_REGNUM),

47361

- gen_rtx_CONST_INT (VOIDmode, CC1 | CC3)));

47362

- LABEL_NUSES (leave_label) = 2;

47363

- add_reg_note (jump, REG_BR_PROB, very_unlikely);

47364

+ gen_rtx_CONST_INT (VOIDmode, CC0 | CC1 | CC3)));

47365

+ LABEL_NUSES (leave_label) = 1;

47366

47367

/* CC2 - transient failure. Perform retry with ppa. */

47368

- emit_move_insn (count, retry);

47369

+ emit_move_insn (count, retry_plus_two);

47370

emit_insn (gen_subsi3 (count, count, retry_reg));

47371

emit_insn (gen_tx_assist (count));

47372

jump = emit_jump_insn (gen_doloop_si64 (retry_label,

47373

@@ -9630,13 +9824,8 @@

47374

retry_reg));

47375

JUMP_LABEL (jump) = retry_label;

47376

LABEL_NUSES (retry_label) = 1;

47377

+ emit_label (leave_label);

47378

}

47379

-

47380

- emit_move_insn (dest, gen_rtx_UNSPEC (SImode,

47381

- gen_rtvec (1, gen_rtx_REG (CCRAWmode,

47382

- CC_REGNUM)),

47383

- UNSPEC_CC_TO_INT));

47384

- emit_label (leave_label);

47385

}

47386

47387

/* Builtins. */

47388

@@ -9674,6 +9863,9 @@

47389

s390_init_builtins (void)

47390

{

47391

tree ftype, uint64_type;

47392

+ tree returns_twice_attr = tree_cons (get_identifier ("returns_twice"),

47393

+ NULL, NULL);

47394

+ tree noreturn_attr = tree_cons (get_identifier ("noreturn"), NULL, NULL);

47395

47396

/* void foo (void) */

47397

ftype = build_function_type_list (void_type_node, NULL_TREE);

47398

@@ -9684,7 +9876,7 @@

47399

ftype = build_function_type_list (void_type_node, integer_type_node,

47400

NULL_TREE);

47401

add_builtin_function ("__builtin_tabort", ftype,

47402

- S390_BUILTIN_TABORT, BUILT_IN_MD, NULL, NULL_TREE);

47403

+ S390_BUILTIN_TABORT, BUILT_IN_MD, NULL, noreturn_attr);

47404

add_builtin_function ("__builtin_tx_assist", ftype,

47405

S390_BUILTIN_TX_ASSIST, BUILT_IN_MD, NULL, NULL_TREE);

47406

47407

@@ -9691,10 +9883,10 @@

47408

/* int foo (void *) */

47409

ftype = build_function_type_list (integer_type_node, ptr_type_node, NULL_TREE);

47410

add_builtin_function ("__builtin_tbegin", ftype, S390_BUILTIN_TBEGIN,

47411

- BUILT_IN_MD, NULL, NULL_TREE);

47412

+ BUILT_IN_MD, NULL, returns_twice_attr);

47413

add_builtin_function ("__builtin_tbegin_nofloat", ftype,

47414

S390_BUILTIN_TBEGIN_NOFLOAT,

47415

- BUILT_IN_MD, NULL, NULL_TREE);

47416

+ BUILT_IN_MD, NULL, returns_twice_attr);

47417

47418

/* int foo (void *, int) */

47419

ftype = build_function_type_list (integer_type_node, ptr_type_node,

47420

@@ -9702,11 +9894,11 @@

47421

add_builtin_function ("__builtin_tbegin_retry", ftype,

47422

S390_BUILTIN_TBEGIN_RETRY,

47423

BUILT_IN_MD,

47424

- NULL, NULL_TREE);

47425

+ NULL, returns_twice_attr);

47426

add_builtin_function ("__builtin_tbegin_retry_nofloat", ftype,

47427

S390_BUILTIN_TBEGIN_RETRY_NOFLOAT,

47428

BUILT_IN_MD,

47429

- NULL, NULL_TREE);

47430

+ NULL, returns_twice_attr);

47431

47432

/* int foo (void) */

47433

ftype = build_function_type_list (integer_type_node, NULL_TREE);

47434

@@ -11622,6 +11814,12 @@

47435

#undef TARGET_CANONICALIZE_COMPARISON

47436

#define TARGET_CANONICALIZE_COMPARISON s390_canonicalize_comparison

47437

47438

+#undef TARGET_ATTRIBUTE_TABLE

47439

+#define TARGET_ATTRIBUTE_TABLE s390_attribute_table

47440

+

47441

+#undef TARGET_CAN_INLINE_P

47442

+#define TARGET_CAN_INLINE_P s390_can_inline_p

47443

+

47444

struct gcc_target targetm = TARGET_INITIALIZER;

47445

47446

#include "gt-s390.h"

47447

Index: gcc/config/s390/s390.h

47448

===================================================================

47449

--- a/src/gcc/config/s390/s390.h (.../tags/gcc_4_8_2_release)

47450

+++ b/src/gcc/config/s390/s390.h (.../branches/gcc-4_8-branch)

47451

@@ -217,7 +217,7 @@

47452

#define STACK_BOUNDARY 64

47453

47454

/* Allocation boundary (in *bits*) for the code of a function. */

47455

-#define FUNCTION_BOUNDARY 32

47456

+#define FUNCTION_BOUNDARY 64

47457

47458

/* There is no point aligning anything to a rounder boundary than this. */

47459

#define BIGGEST_ALIGNMENT 64

47460

@@ -878,6 +878,9 @@

47461

fputc ('\n', (FILE)); \

47462

} while (0)

47463

47464

+#undef ASM_OUTPUT_FUNCTION_LABEL

47465

+#define ASM_OUTPUT_FUNCTION_LABEL(FILE, NAME, DECL) \

47466

+ s390_asm_output_function_label (FILE, NAME, DECL)

47467

47468

/* Miscellaneous parameters. */

47469

47470

Index: gcc/config/s390/s390.md

47471

===================================================================

47472

--- a/src/gcc/config/s390/s390.md (.../tags/gcc_4_8_2_release)

47473

+++ b/src/gcc/config/s390/s390.md (.../branches/gcc-4_8-branch)

47474

@@ -147,6 +147,7 @@

47475

47476

; Transactional Execution support

47477

UNSPECV_TBEGIN

47478

+ UNSPECV_TBEGIN_TDB

47479

UNSPECV_TBEGINC

47480

UNSPECV_TEND

47481

UNSPECV_TABORT

47482

@@ -9896,9 +9897,10 @@

47483

47484

(define_insn "tbegin_1"

47485

[(set (reg:CCRAW CC_REGNUM)

47486

- (unspec_volatile:CCRAW [(match_operand:BLK 0 "memory_operand" "=Q")

47487

- (match_operand 1 "const_int_operand" " D")]

47488

+ (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]

47489

UNSPECV_TBEGIN))

47490

+ (set (match_operand:BLK 1 "memory_operand" "=Q")

47491

+ (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))

47492

(clobber (reg:DF 16))

47493

(clobber (reg:DF 17))

47494

(clobber (reg:DF 18))

47495

@@ -9917,18 +9919,19 @@

47496

(clobber (reg:DF 31))]

47497

; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is

47498

; not supposed to be used for immediates (see genpreds.c).

47499

- "TARGET_HTM && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 0xffff"

47500

- "tbegin\t%0,%x1"

47501

+ "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"

47502

+ "tbegin\t%1,%x0"

47503

[(set_attr "op_type" "SIL")])

47504

47505

; Same as above but without the FPR clobbers

47506

(define_insn "tbegin_nofloat_1"

47507

[(set (reg:CCRAW CC_REGNUM)

47508

- (unspec_volatile:CCRAW [(match_operand:BLK 0 "memory_operand" "=Q")

47509

- (match_operand 1 "const_int_operand" " D")]

47510

- UNSPECV_TBEGIN))]

47511

- "TARGET_HTM && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 0xffff"

47512

- "tbegin\t%0,%x1"

47513

+ (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]

47514

+ UNSPECV_TBEGIN))

47515

+ (set (match_operand:BLK 1 "memory_operand" "=Q")

47516

+ (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))]

47517

+ "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"

47518

+ "tbegin\t%1,%x0"

47519

[(set_attr "op_type" "SIL")])

47520

47521

47522

@@ -10012,15 +10015,12 @@

47523

; Transaction perform processor assist

47524

47525

(define_expand "tx_assist"

47526

- [(set (match_dup 1) (const_int 0))

47527

- (unspec_volatile [(match_operand:SI 0 "register_operand" "")

47528

- (match_dup 1)

47529

+ [(unspec_volatile [(match_operand:SI 0 "register_operand" "")

47530

+ (reg:SI GPR0_REGNUM)

47531

(const_int 1)]

47532

UNSPECV_PPA)]

47533

"TARGET_HTM"

47534

-{

47535

- operands[1] = gen_reg_rtx (SImode);

47536

-})

47537

+ "")

47538

47539

(define_insn "*ppa"

47540

[(unspec_volatile [(match_operand:SI 0 "register_operand" "d")

47541

@@ -10028,5 +10028,5 @@

47542

(match_operand 2 "const_int_operand" "I")]

47543

UNSPECV_PPA)]

47544

"TARGET_HTM && INTVAL (operands[2]) < 16"

47545

- "ppa\t%0,%1,1"

47546

+ "ppa\t%0,%1,%2"

47547

[(set_attr "op_type" "RRF")])

47548

Index: gcc/config/s390/s390.opt

47549

===================================================================

47550

--- a/src/gcc/config/s390/s390.opt (.../tags/gcc_4_8_2_release)

47551

+++ b/src/gcc/config/s390/s390.opt (.../branches/gcc-4_8-branch)

47552

@@ -96,6 +96,14 @@

47553

Target Report RejectNegative Negative(msoft-float) InverseMask(SOFT_FLOAT, HARD_FLOAT)

47554

Enable hardware floating point

47555

47556

+mhotpatch

47557

+Target Report Var(s390_deferred_options) Defer

47558

+Prepend the function label with 12 two-byte Nop instructions, and add a four byte Nop instruction after the label for hotpatching.

47559

+

47560

+mhotpatch=

47561

+Target RejectNegative Report Joined Var(s390_deferred_options) Defer

47562

+Prepend the function label with the given number of two-byte Nop instructions, and add a four byte Nop instruction after the label for hotpatching.

47563

+

47564

mlong-double-128

47565

Target Report RejectNegative Negative(mlong-double-64) Mask(LONG_DOUBLE_128)

47566

Use 128-bit long double

47567

Index: gcc/config/s390/htmxlintrin.h

47568

===================================================================

47569

--- a/src/gcc/config/s390/htmxlintrin.h (.../tags/gcc_4_8_2_release)

47570

+++ b/src/gcc/config/s390/htmxlintrin.h (.../branches/gcc-4_8-branch)

47571

@@ -33,13 +33,20 @@

47572

the IBM XL compiler. For documentation please see the "z/OS XL

47573

C/C++ Programming Guide" publically available on the web. */

47574

47575

-extern __inline long __attribute__((__gnu_inline__, __always_inline__, __artificial__))

47576

+/* FIXME: __TM_simple_begin and __TM_begin should be marked

47577

+ __always_inline__ as well but this currently produces an error

47578

+ since the tbegin builtins are "returns_twice" and setjmp_call_p

47579

+ (calls.c) therefore identifies the functions as calling setjmp.

47580

+ The tree inliner currently refuses to inline functions calling

47581

+ setjmp. */

47582

+

47583

+long

47584

__TM_simple_begin ()

47585

{

47586

return __builtin_tbegin_nofloat (0);

47587

}

47588

47589

-extern __inline long __attribute__((__gnu_inline__, __always_inline__, __artificial__))

47590

+long

47591

__TM_begin (void* const tdb)

47592

{

47593

return __builtin_tbegin_nofloat (tdb);

47594

@@ -78,7 +85,7 @@

47595

if (depth != 0)

47596

return depth;

47597

47598

- if (tdb->format == 0)

47599

+ if (tdb->format != 1)

47600

return 0;

47601

return tdb->nesting_depth;

47602

}

47603

@@ -90,7 +97,7 @@

47604

{

47605

struct __htm_tdb *tdb = (struct __htm_tdb*)tdb_ptr;

47606

47607

- if (tdb->format == 0)

47608

+ if (tdb->format != 1)

47609

return 0;

47610

47611

return !!(tdb->abort_code >= _HTM_FIRST_USER_ABORT_CODE);

47612

@@ -101,7 +108,7 @@

47613

{

47614

struct __htm_tdb *tdb = (struct __htm_tdb*)tdb_ptr;

47615

47616

- if (tdb->format == 0)

47617

+ if (tdb->format != 1)

47618

return 0;

47619

47620

if (tdb->abort_code >= _HTM_FIRST_USER_ABORT_CODE)

47621

@@ -117,7 +124,7 @@

47622

{

47623

struct __htm_tdb *tdb = (struct __htm_tdb*)tdb_ptr;

47624

47625

- return (tdb->format == 0

47626

+ return (tdb->format == 1

47627

&& (tdb->abort_code == 4 /* unfiltered program interruption */

47628

|| tdb->abort_code == 11 /* restricted instruction */));

47629

}

47630

@@ -127,7 +134,7 @@

47631

{

47632

struct __htm_tdb *tdb = (struct __htm_tdb*)tdb_ptr;

47633

47634

- return (tdb->format == 0

47635

+ return (tdb->format == 1

47636

&& (tdb->abort_code == 7 /* fetch overflow */

47637

|| tdb->abort_code == 8 /* store overflow */));

47638

}

47639

@@ -137,7 +144,7 @@

47640

{

47641

struct __htm_tdb *tdb = (struct __htm_tdb*)tdb_ptr;

47642

47643

- return tdb->format == 0 && tdb->abort_code == 13; /* depth exceeded */

47644

+ return tdb->format == 1 && tdb->abort_code == 13; /* depth exceeded */

47645

}

47646

47647

extern __inline long __attribute__((__gnu_inline__, __always_inline__, __artificial__))

47648

@@ -145,7 +152,7 @@

47649

{

47650

struct __htm_tdb *tdb = (struct __htm_tdb*)tdb_ptr;

47651

47652

- return (tdb->format == 0

47653

+ return (tdb->format == 1

47654

&& (tdb->abort_code == 9 /* fetch conflict */

47655

|| tdb->abort_code == 10 /* store conflict */));

47656

}

47657

Index: gcc/config/s390/s390-protos.h

47658

===================================================================

47659

--- a/src/gcc/config/s390/s390-protos.h (.../tags/gcc_4_8_2_release)

47660

+++ b/src/gcc/config/s390/s390-protos.h (.../branches/gcc-4_8-branch)

47661

@@ -110,5 +110,6 @@

47662

extern int s390_branch_condition_mask (rtx);

47663

extern int s390_compare_and_branch_condition_mask (rtx);

47664

extern bool s390_extzv_shift_ok (int, int, unsigned HOST_WIDE_INT);

47665

+extern void s390_asm_output_function_label (FILE *, const char *, tree);

47666

47667

#endif /* RTX_CODE */

47668

Index: gcc/config/sparc/t-rtems

47669

===================================================================

47670

--- a/src/gcc/config/sparc/t-rtems (.../tags/gcc_4_8_2_release)

47671

+++ b/src/gcc/config/sparc/t-rtems (.../branches/gcc-4_8-branch)

47672

@@ -17,6 +17,6 @@

47673

# <http://www.gnu.org/licenses/>.

47674

#

47675

47676

-MULTILIB_OPTIONS = msoft-float mcpu=v8

47677

-MULTILIB_DIRNAMES = soft v8

47678

+MULTILIB_OPTIONS = msoft-float mcpu=v8/mcpu=leon3

47679

+MULTILIB_DIRNAMES = soft v8 leon3

47680

MULTILIB_MATCHES = msoft-float=mno-fpu

47681

Index: gcc/config/sparc/sparc.md

47682

===================================================================

47683

--- a/src/gcc/config/sparc/sparc.md (.../tags/gcc_4_8_2_release)

47684

+++ b/src/gcc/config/sparc/sparc.md (.../branches/gcc-4_8-branch)

47685

@@ -206,7 +206,7 @@

47686

;; 'f' for all DF/TFmode values, including those that are specific to the v8.

47687

47688

;; Attribute for cpu type.

47689

-;; These must match the values for enum processor_type in sparc.h.

47690

+;; These must match the values of the enum processor_type in sparc-opts.h.

47691

(define_attr "cpu"

47692

"v7,

47693

cypress,

47694

@@ -214,6 +214,7 @@

47695

supersparc,

47696

hypersparc,

47697

leon,

47698

+ leon3,

47699

sparclite,

47700

f930,

47701

f934,

47702

@@ -284,7 +285,8 @@

47703

(const_string "none"))

47704

47705

(define_attr "pic" "false,true"

47706

- (symbol_ref "(flag_pic != 0 ? PIC_TRUE : PIC_FALSE)"))

47707

+ (symbol_ref "(flag_pic != 0

47708

+ ? PIC_TRUE : PIC_FALSE)"))

47709

47710

(define_attr "calls_alloca" "false,true"

47711

(symbol_ref "(cfun->calls_alloca != 0

47712

@@ -306,6 +308,10 @@

47713

(symbol_ref "(TARGET_FLAT != 0

47714

? FLAT_TRUE : FLAT_FALSE)"))

47715

47716

+(define_attr "fix_ut699" "false,true"

47717

+ (symbol_ref "(sparc_fix_ut699 != 0

47718

+ ? FIX_UT699_TRUE : FIX_UT699_FALSE)"))

47719

+

47720

;; Length (in # of insns).

47721

;; Beware that setting a length greater or equal to 3 for conditional branches

47722

;; has a side-effect (see output_cbranch and output_v9branch).

47723

@@ -420,32 +426,18 @@

47724

[(set_attr "length" "2")

47725

(set_attr "type" "multi")])

47726

47727

-;; Attributes for instruction and branch scheduling

47728

-(define_attr "tls_call_delay" "false,true"

47729

- (symbol_ref "(tls_call_delay (insn)

47730

- ? TLS_CALL_DELAY_TRUE : TLS_CALL_DELAY_FALSE)"))

47731

-

47732

+;; Attributes for branch scheduling

47733

(define_attr "in_call_delay" "false,true"

47734

- (cond [(eq_attr "type" "uncond_branch,branch,cbcond,uncond_cbcond,call,sibcall,call_no_delay_slot,multi")

47735

- (const_string "false")

47736

- (eq_attr "type" "load,fpload,store,fpstore")

47737

- (if_then_else (eq_attr "length" "1")

47738

- (const_string "true")

47739

- (const_string "false"))]

47740

- (if_then_else (and (eq_attr "length" "1")

47741

- (eq_attr "tls_call_delay" "true"))

47742

- (const_string "true")

47743

- (const_string "false"))))

47744

+ (symbol_ref "(eligible_for_call_delay (insn)

47745

+ ? IN_CALL_DELAY_TRUE : IN_CALL_DELAY_FALSE)"))

47746

47747

-(define_attr "eligible_for_sibcall_delay" "false,true"

47748

+(define_attr "in_sibcall_delay" "false,true"

47749

(symbol_ref "(eligible_for_sibcall_delay (insn)

47750

- ? ELIGIBLE_FOR_SIBCALL_DELAY_TRUE

47751

- : ELIGIBLE_FOR_SIBCALL_DELAY_FALSE)"))

47752

+ ? IN_SIBCALL_DELAY_TRUE : IN_SIBCALL_DELAY_FALSE)"))

47753

47754

-(define_attr "eligible_for_return_delay" "false,true"

47755

+(define_attr "in_return_delay" "false,true"

47756

(symbol_ref "(eligible_for_return_delay (insn)

47757

- ? ELIGIBLE_FOR_RETURN_DELAY_TRUE

47758

- : ELIGIBLE_FOR_RETURN_DELAY_FALSE)"))

47759

+ ? IN_RETURN_DELAY_TRUE : IN_RETURN_DELAY_FALSE)"))

47760

47761

;; ??? !v9: Should implement the notion of predelay slots for floating-point

47762

;; branches. This would allow us to remove the nop always inserted before

47763

@@ -460,41 +452,34 @@

47764

;; because it prevents us from moving back the final store of inner loops.

47765

47766

(define_attr "in_branch_delay" "false,true"

47767

- (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbcond,uncond_cbcond,call,sibcall,call_no_delay_slot,multi")

47768

- (eq_attr "length" "1"))

47769

- (const_string "true")

47770

- (const_string "false")))

47771

+ (cond [(eq_attr "type" "uncond_branch,branch,cbcond,uncond_cbcond,call,sibcall,call_no_delay_slot,multi")

47772

+ (const_string "false")

47773

+ (and (eq_attr "fix_ut699" "true") (eq_attr "type" "load,sload"))

47774

+ (const_string "false")

47775

+ (and (eq_attr "fix_ut699" "true")

47776

+ (and (eq_attr "type" "fpload,fp,fpmove,fpmul,fpdivs,fpsqrts")

47777

+ (eq_attr "fptype" "single")))

47778

+ (const_string "false")

47779

+ (eq_attr "length" "1")

47780

+ (const_string "true")

47781

+ ] (const_string "false")))

47782

47783

-(define_attr "in_uncond_branch_delay" "false,true"

47784

- (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbcond,uncond_cbcond,call,sibcall,call_no_delay_slot,multi")

47785

- (eq_attr "length" "1"))

47786

- (const_string "true")

47787

- (const_string "false")))

47788

-

47789

-(define_attr "in_annul_branch_delay" "false,true"

47790

- (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbcond,uncond_cbcond,call,sibcall,call_no_delay_slot,multi")

47791

- (eq_attr "length" "1"))

47792

- (const_string "true")

47793

- (const_string "false")))

47794

-

47795

(define_delay (eq_attr "type" "call")

47796

[(eq_attr "in_call_delay" "true") (nil) (nil)])

47797

47798

(define_delay (eq_attr "type" "sibcall")

47799

- [(eq_attr "eligible_for_sibcall_delay" "true") (nil) (nil)])

47800

+ [(eq_attr "in_sibcall_delay" "true") (nil) (nil)])

47801

47802

+(define_delay (eq_attr "type" "return")

47803

+ [(eq_attr "in_return_delay" "true") (nil) (nil)])

47804

+

47805

(define_delay (eq_attr "type" "branch")

47806

- [(eq_attr "in_branch_delay" "true")

47807

- (nil) (eq_attr "in_annul_branch_delay" "true")])

47808

+ [(eq_attr "in_branch_delay" "true") (nil) (eq_attr "in_branch_delay" "true")])

47809

47810

(define_delay (eq_attr "type" "uncond_branch")

47811

- [(eq_attr "in_uncond_branch_delay" "true")

47812

- (nil) (nil)])

47813

+ [(eq_attr "in_branch_delay" "true") (nil) (nil)])

47814

47815

-(define_delay (eq_attr "type" "return")

47816

- [(eq_attr "eligible_for_return_delay" "true") (nil) (nil)])

47817

47818

-

47819

;; Include SPARC DFA schedulers

47820

47821

(include "cypress.md")

47822

@@ -5548,7 +5533,7 @@

47823

[(set (match_operand:DF 0 "register_operand" "=e")

47824

(mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "f"))

47825

(float_extend:DF (match_operand:SF 2 "register_operand" "f"))))]

47826

- "(TARGET_V8 || TARGET_V9) && TARGET_FPU"

47827

+ "(TARGET_V8 || TARGET_V9) && TARGET_FPU && !sparc_fix_ut699"

47828

"fsmuld\t%1, %2, %0"

47829

[(set_attr "type" "fpmul")

47830

(set_attr "fptype" "double")])

47831

@@ -5575,22 +5560,39 @@

47832

(match_operand:TF 2 "register_operand" "e")))]

47833

"TARGET_FPU && TARGET_HARD_QUAD"

47834

"fdivq\t%1, %2, %0"

47835

- [(set_attr "type" "fpdivd")])

47836

+ [(set_attr "type" "fpdivs")])

47837

47838

-(define_insn "divdf3"

47839

+(define_expand "divdf3"

47840

[(set (match_operand:DF 0 "register_operand" "=e")

47841

(div:DF (match_operand:DF 1 "register_operand" "e")

47842

(match_operand:DF 2 "register_operand" "e")))]

47843

"TARGET_FPU"

47844

+ "")

47845

+

47846

+(define_insn "*divdf3_nofix"

47847

+ [(set (match_operand:DF 0 "register_operand" "=e")

47848

+ (div:DF (match_operand:DF 1 "register_operand" "e")

47849

+ (match_operand:DF 2 "register_operand" "e")))]

47850

+ "TARGET_FPU && !sparc_fix_ut699"

47851

"fdivd\t%1, %2, %0"

47852

[(set_attr "type" "fpdivd")

47853

(set_attr "fptype" "double")])

47854

47855

+(define_insn "*divdf3_fix"

47856

+ [(set (match_operand:DF 0 "register_operand" "=e")

47857

+ (div:DF (match_operand:DF 1 "register_operand" "e")

47858

+ (match_operand:DF 2 "register_operand" "e")))]

47859

+ "TARGET_FPU && sparc_fix_ut699"

47860

+ "fdivd\t%1, %2, %0\n\tstd\t%0, [%%sp-8]"

47861

+ [(set_attr "type" "fpdivd")

47862

+ (set_attr "fptype" "double")

47863

+ (set_attr "length" "2")])

47864

+

47865

(define_insn "divsf3"

47866

[(set (match_operand:SF 0 "register_operand" "=f")

47867

(div:SF (match_operand:SF 1 "register_operand" "f")

47868

(match_operand:SF 2 "register_operand" "f")))]

47869

- "TARGET_FPU"

47870

+ "TARGET_FPU && !sparc_fix_ut699"

47871

"fdivs\t%1, %2, %0"

47872

[(set_attr "type" "fpdivs")])

47873

47874

@@ -5789,20 +5791,35 @@

47875

(sqrt:TF (match_operand:TF 1 "register_operand" "e")))]

47876

"TARGET_FPU && TARGET_HARD_QUAD"

47877

"fsqrtq\t%1, %0"

47878

- [(set_attr "type" "fpsqrtd")])

47879

+ [(set_attr "type" "fpsqrts")])

47880

47881

-(define_insn "sqrtdf2"

47882

+(define_expand "sqrtdf2"

47883

[(set (match_operand:DF 0 "register_operand" "=e")

47884

(sqrt:DF (match_operand:DF 1 "register_operand" "e")))]

47885

"TARGET_FPU"

47886

+ "")

47887

+

47888

+(define_insn "*sqrtdf2_nofix"

47889

+ [(set (match_operand:DF 0 "register_operand" "=e")

47890

+ (sqrt:DF (match_operand:DF 1 "register_operand" "e")))]

47891

+ "TARGET_FPU && !sparc_fix_ut699"

47892

"fsqrtd\t%1, %0"

47893

[(set_attr "type" "fpsqrtd")

47894

(set_attr "fptype" "double")])

47895

47896

+(define_insn "*sqrtdf2_fix"

47897

+ [(set (match_operand:DF 0 "register_operand" "=e")

47898

+ (sqrt:DF (match_operand:DF 1 "register_operand" "e")))]

47899

+ "TARGET_FPU && sparc_fix_ut699"

47900

+ "fsqrtd\t%1, %0\n\tstd\t%0, [%%sp-8]"

47901

+ [(set_attr "type" "fpsqrtd")

47902

+ (set_attr "fptype" "double")

47903

+ (set_attr "length" "2")])

47904

+

47905

(define_insn "sqrtsf2"

47906

[(set (match_operand:SF 0 "register_operand" "=f")

47907

(sqrt:SF (match_operand:SF 1 "register_operand" "f")))]

47908

- "TARGET_FPU"

47909

+ "TARGET_FPU && !sparc_fix_ut699"

47910

"fsqrts\t%1, %0"

47911

[(set_attr "type" "fpsqrts")])

47912

47913

@@ -5821,19 +5838,6 @@

47914

}

47915

[(set_attr "type" "shift")])

47916

47917

-(define_insn "*ashlsi3_extend"

47918

- [(set (match_operand:DI 0 "register_operand" "=r")

47919

- (zero_extend:DI

47920

- (ashift:SI (match_operand:SI 1 "register_operand" "r")

47921

- (match_operand:SI 2 "arith_operand" "rI"))))]

47922

- "TARGET_ARCH64"

47923

-{

47924

- if (GET_CODE (operands[2]) == CONST_INT)

47925

- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);

47926

- return "sll\t%1, %2, %0";

47927

-}

47928

- [(set_attr "type" "shift")])

47929

-

47930

(define_expand "ashldi3"

47931

[(set (match_operand:DI 0 "register_operand" "=r")

47932

(ashift:DI (match_operand:DI 1 "register_operand" "r")

47933

Index: gcc/config/sparc/t-sparc

47934

===================================================================

47935

--- a/src/gcc/config/sparc/t-sparc (.../tags/gcc_4_8_2_release)

47936

+++ b/src/gcc/config/sparc/t-sparc (.../branches/gcc-4_8-branch)

47937

@@ -23,7 +23,7 @@

47938

insn-codes.h conditions.h output.h $(INSN_ATTR_H) $(FLAGS_H) \

47939

$(FUNCTION_H) $(EXCEPT_H) $(EXPR_H) $(OPTABS_H) $(RECOG_H) \

47940

$(DIAGNOSTIC_CORE_H) $(GGC_H) $(TM_P_H) debug.h $(TARGET_H) \

47941

- $(TARGET_DEF_H) $(COMMON_TARGET_H) $(GIMPLE_H) \

47942

+ $(TARGET_DEF_H) $(COMMON_TARGET_H) $(GIMPLE_H) $(TREE_PASS_H) \

47943

langhooks.h reload.h $(PARAMS_H) $(DF_H) $(OPTS_H) \

47944

gt-sparc.h

47945

47946

Index: gcc/config/sparc/sparc.opt

47947

===================================================================

47948

--- a/src/gcc/config/sparc/sparc.opt (.../tags/gcc_4_8_2_release)

47949

+++ b/src/gcc/config/sparc/sparc.opt (.../branches/gcc-4_8-branch)

47950

@@ -113,6 +113,10 @@

47951

Target

47952

Optimize tail call instructions in assembler and linker

47953

47954

+muser-mode

47955

+Target Report Mask(USER_MODE)

47956

+Do not generate code that can only run in supervisor mode

47957

+

47958

mcpu=

47959

Target RejectNegative Joined Var(sparc_cpu_and_features) Enum(sparc_processor_type) Init(PROCESSOR_V7)

47960

Use features of and schedule code for given CPU

47961

@@ -146,6 +150,9 @@

47962

Enum(sparc_processor_type) String(leon) Value(PROCESSOR_LEON)

47963

47964

EnumValue

47965

+Enum(sparc_processor_type) String(leon3) Value(PROCESSOR_LEON3)

47966

+

47967

+EnumValue

47968

Enum(sparc_processor_type) String(sparclite) Value(PROCESSOR_SPARCLITE)

47969

47970

EnumValue

47971

@@ -201,9 +208,19 @@

47972

Enable workaround for single erratum of AT697F processor

47973

(corresponding to erratum #13 of AT697E processor)

47974

47975

+mfix-ut699

47976

+Target Report RejectNegative Var(sparc_fix_ut699)

47977

+Enable workarounds for the errata of the UT699 processor

47978

+

47979

Mask(LONG_DOUBLE_128)

47980

;; Use 128-bit long double

47981

47982

+Mask(LEON)

47983

+;; Generate code for LEON

47984

+

47985

+Mask(LEON3)

47986

+;; Generate code for LEON3

47987

+

47988

Mask(SPARCLITE)

47989

;; Generate code for SPARClite

47990

47991

Index: gcc/config/sparc/sync.md

47992

===================================================================

47993

--- a/src/gcc/config/sparc/sync.md (.../tags/gcc_4_8_2_release)

47994

+++ b/src/gcc/config/sparc/sync.md (.../branches/gcc-4_8-branch)

47995

@@ -161,7 +161,8 @@

47996

(match_operand:SI 5 "const_int_operand" "") ;; is_weak

47997

(match_operand:SI 6 "const_int_operand" "") ;; mod_s

47998

(match_operand:SI 7 "const_int_operand" "")] ;; mod_f

47999

- "TARGET_V9 && (<MODE>mode != DImode || TARGET_ARCH64 || TARGET_V8PLUS)"

48000

+ "(TARGET_V9 || TARGET_LEON3)

48001

+ && (<MODE>mode != DImode || TARGET_ARCH64 || TARGET_V8PLUS)"

48002

{

48003

sparc_expand_compare_and_swap (operands);

48004

DONE;

48005

@@ -176,7 +177,7 @@

48006

[(match_operand:I48MODE 2 "register_operand" "")

48007

(match_operand:I48MODE 3 "register_operand" "")]

48008

UNSPECV_CAS))])]

48009

- "TARGET_V9"

48010

+ "TARGET_V9 || TARGET_LEON3"

48011

"")

48012

48013

(define_insn "*atomic_compare_and_swap<mode>_1"

48014

@@ -187,10 +188,27 @@

48015

[(match_operand:I48MODE 2 "register_operand" "r")

48016

(match_operand:I48MODE 3 "register_operand" "0")]

48017

UNSPECV_CAS))]

48018

- "TARGET_V9 && (<MODE>mode == SImode || TARGET_ARCH64)"

48019

+ "TARGET_V9 && (<MODE>mode != DImode || TARGET_ARCH64)"

48020

"cas<modesuffix>\t%1, %2, %0"

48021

[(set_attr "type" "multi")])

48022

48023

+(define_insn "*atomic_compare_and_swap_leon3_1"

48024

+ [(set (match_operand:SI 0 "register_operand" "=r")

48025

+ (match_operand:SI 1 "mem_noofs_operand" "+w"))

48026

+ (set (match_dup 1)

48027

+ (unspec_volatile:SI

48028

+ [(match_operand:SI 2 "register_operand" "r")

48029

+ (match_operand:SI 3 "register_operand" "0")]

48030

+ UNSPECV_CAS))]

48031

+ "TARGET_LEON3"

48032

+{

48033

+ if (TARGET_USER_MODE)

48034

+ return "casa\t%1 0xa, %2, %0"; /* ASI for user data space. */

48035

+ else

48036

+ return "casa\t%1 0xb, %2, %0"; /* ASI for supervisor data space. */

48037

+}

48038

+ [(set_attr "type" "multi")])

48039

+

48040

(define_insn "*atomic_compare_and_swapdi_v8plus"

48041

[(set (match_operand:DI 0 "register_operand" "=h")

48042

(match_operand:DI 1 "mem_noofs_operand" "+w"))

48043

@@ -220,7 +238,7 @@

48044

(match_operand:SI 1 "memory_operand" "")

48045

(match_operand:SI 2 "register_operand" "")

48046

(match_operand:SI 3 "const_int_operand" "")]

48047

- "TARGET_V8 || TARGET_V9"

48048

+ "(TARGET_V8 || TARGET_V9) && !sparc_fix_ut699"

48049

{

48050

enum memmodel model = (enum memmodel) INTVAL (operands[3]);

48051

48052

@@ -236,7 +254,7 @@

48053

UNSPECV_SWAP))

48054

(set (match_dup 1)

48055

(match_operand:SI 2 "register_operand" "0"))]

48056

- "TARGET_V8 || TARGET_V9"

48057

+ "(TARGET_V8 || TARGET_V9) && !sparc_fix_ut699"

48058

"swap\t%1, %0"

48059

[(set_attr "type" "multi")])

48060

48061

@@ -244,7 +262,7 @@

48062

[(match_operand:QI 0 "register_operand" "")

48063

(match_operand:QI 1 "memory_operand" "")

48064

(match_operand:SI 2 "const_int_operand" "")]

48065

- ""

48066

+ "!sparc_fix_ut699"

48067

{

48068

enum memmodel model = (enum memmodel) INTVAL (operands[2]);

48069

rtx ret;

48070

@@ -268,6 +286,6 @@

48071

(unspec_volatile:QI [(match_operand:QI 1 "memory_operand" "+m")]

48072

UNSPECV_LDSTUB))

48073

(set (match_dup 1) (const_int -1))]

48074

- ""

48075

+ "!sparc_fix_ut699"

48076

"ldstub\t%1, %0"

48077

[(set_attr "type" "multi")])

48078

Index: gcc/config/sparc/sparc-opts.h

48079

===================================================================

48080

--- a/src/gcc/config/sparc/sparc-opts.h (.../tags/gcc_4_8_2_release)

48081

+++ b/src/gcc/config/sparc/sparc-opts.h (.../branches/gcc-4_8-branch)

48082

@@ -30,6 +30,7 @@

48083

PROCESSOR_SUPERSPARC,

48084

PROCESSOR_HYPERSPARC,

48085

PROCESSOR_LEON,

48086

+ PROCESSOR_LEON3,

48087

PROCESSOR_SPARCLITE,

48088

PROCESSOR_F930,

48089

PROCESSOR_F934,

48090

Index: gcc/config/sparc/sparc-protos.h

48091

===================================================================

48092

--- a/src/gcc/config/sparc/sparc-protos.h (.../tags/gcc_4_8_2_release)

48093

+++ b/src/gcc/config/sparc/sparc-protos.h (.../branches/gcc-4_8-branch)

48094

@@ -84,9 +84,9 @@

48095

extern int mems_ok_for_ldd_peep (rtx, rtx, rtx);

48096

extern int empty_delay_slot (rtx);

48097

extern int emit_cbcond_nop (rtx);

48098

+extern int eligible_for_call_delay (rtx);

48099

extern int eligible_for_return_delay (rtx);

48100

extern int eligible_for_sibcall_delay (rtx);

48101

-extern int tls_call_delay (rtx);

48102

extern int emit_move_sequence (rtx, enum machine_mode);

48103

extern int fp_sethi_p (rtx);

48104

extern int fp_mov_p (rtx);

48105

Index: gcc/config/sparc/sparc.c

48106

===================================================================

48107

--- a/src/gcc/config/sparc/sparc.c (.../tags/gcc_4_8_2_release)

48108

+++ b/src/gcc/config/sparc/sparc.c (.../branches/gcc-4_8-branch)

48109

@@ -52,6 +52,7 @@

48110

#include "params.h"

48111

#include "df.h"

48112

#include "opts.h"

48113

+#include "tree-pass.h"

48114

48115

/* Processor costs */

48116

48117

@@ -226,6 +227,30 @@

48118

};

48119

48120

static const

48121

+struct processor_costs leon3_costs = {

48122

+ COSTS_N_INSNS (1), /* int load */

48123

+ COSTS_N_INSNS (1), /* int signed load */

48124

+ COSTS_N_INSNS (1), /* int zeroed load */

48125

+ COSTS_N_INSNS (1), /* float load */

48126

+ COSTS_N_INSNS (1), /* fmov, fneg, fabs */

48127

+ COSTS_N_INSNS (1), /* fadd, fsub */

48128

+ COSTS_N_INSNS (1), /* fcmp */

48129

+ COSTS_N_INSNS (1), /* fmov, fmovr */

48130

+ COSTS_N_INSNS (1), /* fmul */

48131

+ COSTS_N_INSNS (14), /* fdivs */

48132

+ COSTS_N_INSNS (15), /* fdivd */

48133

+ COSTS_N_INSNS (22), /* fsqrts */

48134

+ COSTS_N_INSNS (23), /* fsqrtd */

48135

+ COSTS_N_INSNS (5), /* imul */

48136

+ COSTS_N_INSNS (5), /* imulX */

48137

+ 0, /* imul bit factor */

48138

+ COSTS_N_INSNS (35), /* idiv */

48139

+ COSTS_N_INSNS (35), /* idivX */

48140

+ COSTS_N_INSNS (1), /* movcc/movr */

48141

+ 0, /* shift penalty */

48142

+};

48143

+

48144

+static const

48145

struct processor_costs sparclet_costs = {

48146

COSTS_N_INSNS (3), /* int load */

48147

COSTS_N_INSNS (3), /* int signed load */

48148

@@ -538,7 +563,6 @@

48149

HOST_WIDE_INT, tree);

48150

static bool sparc_can_output_mi_thunk (const_tree, HOST_WIDE_INT,

48151

HOST_WIDE_INT, const_tree);

48152

-static void sparc_reorg (void);

48153

static struct machine_function * sparc_init_machine_status (void);

48154

static bool sparc_cannot_force_const_mem (enum machine_mode, rtx);

48155

static rtx sparc_tls_get_addr (void);

48156

@@ -680,9 +704,6 @@

48157

#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK

48158

#define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk

48159

48160

-#undef TARGET_MACHINE_DEPENDENT_REORG

48161

-#define TARGET_MACHINE_DEPENDENT_REORG sparc_reorg

48162

-

48163

#undef TARGET_RTX_COSTS

48164

#define TARGET_RTX_COSTS sparc_rtx_costs

48165

#undef TARGET_ADDRESS_COST

48166

@@ -804,6 +825,306 @@

48167

48168

struct gcc_target targetm = TARGET_INITIALIZER;

48169

48170

+/* Return the memory reference contained in X if any, zero otherwise. */

48171

+

48172

+static rtx

48173

+mem_ref (rtx x)

48174

+{

48175

+ if (GET_CODE (x) == SIGN_EXTEND || GET_CODE (x) == ZERO_EXTEND)

48176

+ x = XEXP (x, 0);

48177

+

48178

+ if (MEM_P (x))

48179

+ return x;

48180

+

48181

+ return NULL_RTX;

48182

+}

48183

+

48184

+/* We use a machine specific pass to enable workarounds for errata.

48185

+ We need to have the (essentially) final form of the insn stream in order

48186

+ to properly detect the various hazards. Therefore, this machine specific

48187

+ pass runs as late as possible. The pass is inserted in the pass pipeline

48188

+ at the end of sparc_option_override. */

48189

+

48190

+static bool

48191

+sparc_gate_work_around_errata (void)

48192

+{

48193

+ /* The only errata we handle are those of the AT697F and UT699. */

48194

+ return sparc_fix_at697f != 0 || sparc_fix_ut699 != 0;

48195

+}

48196

+

48197

+static unsigned int

48198

+sparc_do_work_around_errata (void)

48199

+{

48200

+ rtx insn, next;

48201

+

48202

+ /* Force all instructions to be split into their final form. */

48203

+ split_all_insns_noflow ();

48204

+

48205

+ /* Now look for specific patterns in the insn stream. */

48206

+ for (insn = get_insns (); insn; insn = next)

48207

+ {

48208

+ bool insert_nop = false;

48209

+ rtx set;

48210

+

48211

+ /* Look into the instruction in a delay slot. */

48212

+ if (NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == SEQUENCE)

48213

+ insn = XVECEXP (PATTERN (insn), 0, 1);

48214

+

48215

+ /* Look for a single-word load into an odd-numbered FP register. */

48216

+ if (sparc_fix_at697f

48217

+ && NONJUMP_INSN_P (insn)

48218

+ && (set = single_set (insn)) != NULL_RTX

48219

+ && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) == 4

48220

+ && MEM_P (SET_SRC (set))

48221

+ && REG_P (SET_DEST (set))

48222

+ && REGNO (SET_DEST (set)) > 31

48223

+ && REGNO (SET_DEST (set)) % 2 != 0)

48224

+ {

48225

+ /* The wrong dependency is on the enclosing double register. */

48226

+ const unsigned int x = REGNO (SET_DEST (set)) - 1;

48227

+ unsigned int src1, src2, dest;

48228

+ int code;

48229

+

48230

+ next = next_active_insn (insn);

48231

+ if (!next)

48232

+ break;

48233

+ /* If the insn is a branch, then it cannot be problematic. */

48234

+ if (!NONJUMP_INSN_P (next) || GET_CODE (PATTERN (next)) == SEQUENCE)

48235

+ continue;

48236

+

48237

+ extract_insn (next);

48238

+ code = INSN_CODE (next);

48239

+

48240

+ switch (code)

48241

+ {

48242

+ case CODE_FOR_adddf3:

48243

+ case CODE_FOR_subdf3:

48244

+ case CODE_FOR_muldf3:

48245

+ case CODE_FOR_divdf3:

48246

+ dest = REGNO (recog_data.operand[0]);

48247

+ src1 = REGNO (recog_data.operand[1]);

48248

+ src2 = REGNO (recog_data.operand[2]);

48249

+ if (src1 != src2)

48250

+ {

48251

+ /* Case [1-4]:

48252

+ ld [address], %fx+1

48253

+ FPOPd %f{x,y}, %f{y,x}, %f{x,y} */

48254

+ if ((src1 == x || src2 == x)

48255

+ && (dest == src1 || dest == src2))

48256

+ insert_nop = true;

48257

+ }

48258

+ else

48259

+ {

48260

+ /* Case 5:

48261

+ ld [address], %fx+1

48262

+ FPOPd %fx, %fx, %fx */

48263

+ if (src1 == x

48264

+ && dest == src1

48265

+ && (code == CODE_FOR_adddf3 || code == CODE_FOR_muldf3))

48266

+ insert_nop = true;

48267

+ }

48268

+ break;

48269

+

48270

+ case CODE_FOR_sqrtdf2:

48271

+ dest = REGNO (recog_data.operand[0]);

48272

+ src1 = REGNO (recog_data.operand[1]);

48273

+ /* Case 6:

48274

+ ld [address], %fx+1

48275

+ fsqrtd %fx, %fx */

48276

+ if (src1 == x && dest == src1)

48277

+ insert_nop = true;

48278

+ break;

48279

+

48280

+ default:

48281

+ break;

48282

+ }

48283

+ }

48284

+

48285

+ /* Look for a single-word load into an integer register. */

48286

+ else if (sparc_fix_ut699

48287

+ && NONJUMP_INSN_P (insn)

48288

+ && (set = single_set (insn)) != NULL_RTX

48289

+ && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) <= 4

48290

+ && mem_ref (SET_SRC (set)) != NULL_RTX

48291

+ && REG_P (SET_DEST (set))

48292

+ && REGNO (SET_DEST (set)) < 32)

48293

+ {

48294

+ /* There is no problem if the second memory access has a data

48295

+ dependency on the first single-cycle load. */

48296

+ rtx x = SET_DEST (set);

48297

+

48298

+ next = next_active_insn (insn);

48299

+ if (!next)

48300

+ break;

48301

+ /* If the insn is a branch, then it cannot be problematic. */

48302

+ if (!NONJUMP_INSN_P (next) || GET_CODE (PATTERN (next)) == SEQUENCE)

48303

+ continue;

48304

+

48305

+ /* Look for a second memory access to/from an integer register. */

48306

+ if ((set = single_set (next)) != NULL_RTX)

48307

+ {

48308

+ rtx src = SET_SRC (set);

48309

+ rtx dest = SET_DEST (set);

48310

+ rtx mem;

48311

+

48312

+ /* LDD is affected. */

48313

+ if ((mem = mem_ref (src)) != NULL_RTX

48314

+ && REG_P (dest)

48315

+ && REGNO (dest) < 32

48316

+ && !reg_mentioned_p (x, XEXP (mem, 0)))

48317

+ insert_nop = true;

48318

+

48319

+ /* STD is *not* affected. */

48320

+ else if (MEM_P (dest)

48321

+ && GET_MODE_SIZE (GET_MODE (dest)) <= 4

48322

+ && (src == CONST0_RTX (GET_MODE (dest))

48323

+ || (REG_P (src)

48324

+ && REGNO (src) < 32

48325

+ && REGNO (src) != REGNO (x)))

48326

+ && !reg_mentioned_p (x, XEXP (dest, 0)))

48327

+ insert_nop = true;

48328

+ }

48329

+ }

48330

+

48331

+ /* Look for a single-word load/operation into an FP register. */

48332

+ else if (sparc_fix_ut699

48333

+ && NONJUMP_INSN_P (insn)

48334

+ && (set = single_set (insn)) != NULL_RTX

48335

+ && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) == 4

48336

+ && REG_P (SET_DEST (set))

48337

+ && REGNO (SET_DEST (set)) > 31)

48338

+ {

48339

+ /* Number of instructions in the problematic window. */

48340

+ const int n_insns = 4;

48341

+ /* The problematic combination is with the sibling FP register. */

48342

+ const unsigned int x = REGNO (SET_DEST (set));

48343

+ const unsigned int y = x ^ 1;

48344

+ rtx after;

48345

+ int i;

48346

+

48347

+ next = next_active_insn (insn);

48348

+ if (!next)

48349

+ break;

48350

+ /* If the insn is a branch, then it cannot be problematic. */

48351

+ if (!NONJUMP_INSN_P (next) || GET_CODE (PATTERN (next)) == SEQUENCE)

48352

+ continue;

48353

+

48354

+ /* Look for a second load/operation into the sibling FP register. */

48355

+ if (!((set = single_set (next)) != NULL_RTX

48356

+ && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) == 4

48357

+ && REG_P (SET_DEST (set))

48358

+ && REGNO (SET_DEST (set)) == y))

48359

+ continue;

48360

+

48361

+ /* Look for a (possible) store from the FP register in the next N

48362

+ instructions, but bail out if it is again modified or if there

48363

+ is a store from the sibling FP register before this store. */

48364

+ for (after = next, i = 0; i < n_insns; i++)

48365

+ {

48366

+ bool branch_p;

48367

+

48368

+ after = next_active_insn (after);

48369

+ if (!after)

48370

+ break;

48371

+

48372

+ /* This is a branch with an empty delay slot. */

48373

+ if (!NONJUMP_INSN_P (after))

48374

+ {

48375

+ if (++i == n_insns)

48376

+ break;

48377

+ branch_p = true;

48378

+ after = NULL_RTX;

48379

+ }

48380

+ /* This is a branch with a filled delay slot. */

48381

+ else if (GET_CODE (PATTERN (after)) == SEQUENCE)

48382

+ {

48383

+ if (++i == n_insns)

48384

+ break;

48385

+ branch_p = true;

48386

+ after = XVECEXP (PATTERN (after), 0, 1);

48387

+ }

48388

+ /* This is a regular instruction. */

48389

+ else

48390

+ branch_p = false;

48391

+

48392

+ if (after && (set = single_set (after)) != NULL_RTX)

48393

+ {

48394

+ const rtx src = SET_SRC (set);

48395

+ const rtx dest = SET_DEST (set);

48396

+ const unsigned int size = GET_MODE_SIZE (GET_MODE (dest));

48397

+

48398

+ /* If the FP register is again modified before the store,

48399

+ then the store isn't affected. */

48400

+ if (REG_P (dest)

48401

+ && (REGNO (dest) == x

48402

+ || (REGNO (dest) == y && size == 8)))

48403

+ break;

48404

+

48405

+ if (MEM_P (dest) && REG_P (src))

48406

+ {

48407

+ /* If there is a store from the sibling FP register

48408

+ before the store, then the store is not affected. */

48409

+ if (REGNO (src) == y || (REGNO (src) == x && size == 8))

48410

+ break;

48411

+

48412

+ /* Otherwise, the store is affected. */

48413

+ if (REGNO (src) == x && size == 4)

48414

+ {

48415

+ insert_nop = true;

48416

+ break;

48417

+ }

48418

+ }

48419

+ }

48420

+

48421

+ /* If we have a branch in the first M instructions, then we

48422

+ cannot see the (M+2)th instruction so we play safe. */

48423

+ if (branch_p && i <= (n_insns - 2))

48424

+ {

48425

+ insert_nop = true;

48426

+ break;

48427

+ }

48428

+ }

48429

+ }

48430

+

48431

+ else

48432

+ next = NEXT_INSN (insn);

48433

+

48434

+ if (insert_nop)

48435

+ emit_insn_before (gen_nop (), next);

48436

+ }

48437

+

48438

+ return 0;

48439

+}

48440

+

48441

+struct rtl_opt_pass pass_work_around_errata =

48442

+{

48443

+ {

48444

+ RTL_PASS,

48445

+ "errata", /* name */

48446

+ OPTGROUP_NONE, /* optinfo_flags */

48447

+ sparc_gate_work_around_errata, /* gate */

48448

+ sparc_do_work_around_errata, /* execute */

48449

+ NULL, /* sub */

48450

+ NULL, /* next */

48451

+ 0, /* static_pass_number */

48452

+ TV_MACH_DEP, /* tv_id */

48453

+ 0, /* properties_required */

48454

+ 0, /* properties_provided */

48455

+ 0, /* properties_destroyed */

48456

+ 0, /* todo_flags_start */

48457

+ TODO_verify_rtl_sharing, /* todo_flags_finish */

48458

+ }

48459

+};

48460

+

48461

+struct register_pass_info insert_pass_work_around_errata =

48462

+{

48463

+ &pass_work_around_errata.pass, /* pass */

48464

+ "dbr", /* reference_pass_name */

48465

+ 1, /* ref_pass_instance_number */

48466

+ PASS_POS_INSERT_AFTER /* po_op */

48467

+};

48468

+

48469

+/* Helpers for TARGET_DEBUG_OPTIONS. */

48470

static void

48471

dump_target_flag_bits (const int flags)

48472

{

48473

@@ -888,6 +1209,7 @@

48474

{ TARGET_CPU_supersparc, PROCESSOR_SUPERSPARC },

48475

{ TARGET_CPU_hypersparc, PROCESSOR_HYPERSPARC },

48476

{ TARGET_CPU_leon, PROCESSOR_LEON },

48477

+ { TARGET_CPU_leon3, PROCESSOR_LEON3 },

48478

{ TARGET_CPU_sparclite, PROCESSOR_F930 },

48479

{ TARGET_CPU_sparclite86x, PROCESSOR_SPARCLITE86X },

48480

{ TARGET_CPU_sparclet, PROCESSOR_TSC701 },

48481

@@ -902,7 +1224,7 @@

48482

};

48483

const struct cpu_default *def;

48484

/* Table of values for -m{cpu,tune}=. This must match the order of

48485

- the PROCESSOR_* enumeration. */

48486

+ the enum processor_type in sparc-opts.h. */

48487

static struct cpu_table {

48488

const char *const name;

48489

const int disable;

48490

@@ -914,8 +1236,8 @@

48491

/* TI TMS390Z55 supersparc */

48492

{ "supersparc", MASK_ISA, MASK_V8 },

48493

{ "hypersparc", MASK_ISA, MASK_V8|MASK_FPU },

48494

- /* LEON */

48495

- { "leon", MASK_ISA, MASK_V8|MASK_FPU },

48496

+ { "leon", MASK_ISA, MASK_V8|MASK_LEON|MASK_FPU },

48497

+ { "leon3", MASK_ISA, MASK_V8|MASK_LEON3|MASK_FPU },

48498

{ "sparclite", MASK_ISA, MASK_SPARCLITE },

48499

/* The Fujitsu MB86930 is the original sparclite chip, with no FPU. */

48500

{ "f930", MASK_ISA|MASK_FPU, MASK_SPARCLITE },

48501

@@ -1075,6 +1397,9 @@

48502

#ifndef HAVE_AS_SPARC4

48503

& ~MASK_CBCOND

48504

#endif

48505

+#ifndef HAVE_AS_LEON

48506

+ & ~(MASK_LEON | MASK_LEON3)

48507

+#endif

48508

);

48509

48510

/* If -mfpu or -mno-fpu was explicitly used, don't override with

48511

@@ -1164,6 +1489,9 @@

48512

case PROCESSOR_LEON:

48513

sparc_costs = &leon_costs;

48514

break;

48515

+ case PROCESSOR_LEON3:

48516

+ sparc_costs = &leon3_costs;

48517

+ break;

48518

case PROCESSOR_SPARCLET:

48519

case PROCESSOR_TSC701:

48520

sparc_costs = &sparclet_costs;

48521

@@ -1200,6 +1528,10 @@

48522

/* Choose the most relaxed model for the processor. */

48523

else if (TARGET_V9)

48524

sparc_memory_model = SMM_RMO;

48525

+ else if (TARGET_LEON3)

48526

+ sparc_memory_model = SMM_TSO;

48527

+ else if (TARGET_LEON)

48528

+ sparc_memory_model = SMM_SC;

48529

else if (TARGET_V8)

48530

sparc_memory_model = SMM_PSO;

48531

else

48532

@@ -1241,6 +1573,13 @@

48533

pessimizes for double floating-point registers. */

48534

if (!global_options_set.x_flag_ira_share_save_slots)

48535

flag_ira_share_save_slots = 0;

48536

+

48537

+ /* We register a machine specific pass to work around errata, if any.

48538

+ The pass mut be scheduled as late as possible so that we have the

48539

+ (essentially) final form of the insn stream to work on.

48540

+ Registering the pass must be done at start up. It's convenient to

48541

+ do it here. */

48542

+ register_pass (&insert_pass_work_around_errata);

48543

}

48544

48545

/* Miscellaneous utilities. */

48546

@@ -3090,10 +3429,13 @@

48547

/* Return nonzero if TRIAL can go into the call delay slot. */

48548

48549

int

48550

-tls_call_delay (rtx trial)

48551

+eligible_for_call_delay (rtx trial)

48552

{

48553

rtx pat;

48554

48555

+ if (get_attr_in_branch_delay (trial) == IN_BRANCH_DELAY_FALSE)

48556

+ return 0;

48557

+

48558

/* Binutils allows

48559

call __tls_get_addr, %tgd_call (foo)

48560

add %l7, %o0, %o0, %tgd_add (foo)

48561

@@ -3175,11 +3517,7 @@

48562

48563

/* If we have the 'return' instruction, anything that does not use

48564

local or output registers and can go into a delay slot wins. */

48565

- else if (return_p

48566

- && TARGET_V9

48567

- && !epilogue_renumber (&pat, 1)

48568

- && get_attr_in_uncond_branch_delay (trial)

48569

- == IN_UNCOND_BRANCH_DELAY_TRUE)

48570

+ else if (return_p && TARGET_V9 && !epilogue_renumber (&pat, 1))

48571

return 1;

48572

48573

/* The 'restore src1,src2,dest' pattern for SImode. */

48574

@@ -3222,22 +3560,21 @@

48575

int regno;

48576

rtx pat;

48577

48578

- if (GET_CODE (trial) != INSN)

48579

- return 0;

48580

-

48581

- if (get_attr_length (trial) != 1)

48582

- return 0;

48583

-

48584

/* If the function uses __builtin_eh_return, the eh_return machinery

48585

occupies the delay slot. */

48586

if (crtl->calls_eh_return)

48587

return 0;

48588

48589

+ if (get_attr_in_branch_delay (trial) == IN_BRANCH_DELAY_FALSE)

48590

+ return 0;

48591

+

48592

/* In the case of a leaf or flat function, anything can go into the slot. */

48593

if (sparc_leaf_function_p || TARGET_FLAT)

48594

- return

48595

- get_attr_in_uncond_branch_delay (trial) == IN_UNCOND_BRANCH_DELAY_TRUE;

48596

+ return 1;

48597

48598

+ if (!NONJUMP_INSN_P (trial))

48599

+ return 0;

48600

+

48601

pat = PATTERN (trial);

48602

if (GET_CODE (pat) == PARALLEL)

48603

{

48604

@@ -3256,9 +3593,7 @@

48605

if (regno >= 8 && regno < 24)

48606

return 0;

48607

}

48608

- return !epilogue_renumber (&pat, 1)

48609

- && (get_attr_in_uncond_branch_delay (trial)

48610

- == IN_UNCOND_BRANCH_DELAY_TRUE);

48611

+ return !epilogue_renumber (&pat, 1);

48612

}

48613

48614

if (GET_CODE (pat) != SET)

48615

@@ -3278,10 +3613,7 @@

48616

instruction, it can probably go in. But restore will not work

48617

with FP_REGS. */

48618

if (! SPARC_INT_REG_P (regno))

48619

- return (TARGET_V9

48620

- && !epilogue_renumber (&pat, 1)

48621

- && get_attr_in_uncond_branch_delay (trial)

48622

- == IN_UNCOND_BRANCH_DELAY_TRUE);

48623

+ return TARGET_V9 && !epilogue_renumber (&pat, 1);

48624

48625

return eligible_for_restore_insn (trial, true);

48626

}

48627

@@ -3293,10 +3625,10 @@

48628

{

48629

rtx pat;

48630

48631

- if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)

48632

+ if (get_attr_in_branch_delay (trial) == IN_BRANCH_DELAY_FALSE)

48633

return 0;

48634

48635

- if (get_attr_length (trial) != 1)

48636

+ if (!NONJUMP_INSN_P (trial))

48637

return 0;

48638

48639

pat = PATTERN (trial);

48640

@@ -3315,6 +3647,9 @@

48641

return 1;

48642

}

48643

48644

+ if (GET_CODE (pat) != SET)

48645

+ return 0;

48646

+

48647

/* Otherwise, only operations which can be done in tandem with

48648

a `restore' insn can go into the delay slot. */

48649

if (GET_CODE (SET_DEST (pat)) != REG

48650

@@ -10355,7 +10690,8 @@

48651

tmp = e0.add_with_sign (tmp, false, &add1_ovf);

48652

if (tmp.is_negative ())

48653

tmp = tmp.neg_with_overflow (&neg2_ovf);

48654

-

48655

+ else

48656

+ neg2_ovf = false;

48657

result = result.add_with_sign (tmp, false, &add2_ovf);

48658

overflow |= neg1_ovf | neg2_ovf | add1_ovf | add2_ovf;

48659

}

48660

@@ -10897,107 +11233,6 @@

48661

return (vcall_offset >= -32768 || ! fixed_regs[5]);

48662

}

48663

48664

-/* We use the machine specific reorg pass to enable workarounds for errata. */

48665

-

48666

-static void

48667

-sparc_reorg (void)

48668

-{

48669

- rtx insn, next;

48670

-

48671

- /* The only erratum we handle for now is that of the AT697F processor. */

48672

- if (!sparc_fix_at697f)

48673

- return;

48674

-

48675

- /* We need to have the (essentially) final form of the insn stream in order

48676

- to properly detect the various hazards. Run delay slot scheduling. */

48677

- if (optimize > 0 && flag_delayed_branch)

48678

- {

48679

- cleanup_barriers ();

48680

- dbr_schedule (get_insns ());

48681

- }

48682

-

48683

- /* Now look for specific patterns in the insn stream. */

48684

- for (insn = get_insns (); insn; insn = next)

48685

- {

48686

- bool insert_nop = false;

48687

- rtx set;

48688

-

48689

- /* Look for a single-word load into an odd-numbered FP register. */

48690

- if (NONJUMP_INSN_P (insn)

48691

- && (set = single_set (insn)) != NULL_RTX

48692

- && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) == 4

48693

- && MEM_P (SET_SRC (set))

48694

- && REG_P (SET_DEST (set))

48695

- && REGNO (SET_DEST (set)) > 31

48696

- && REGNO (SET_DEST (set)) % 2 != 0)

48697

- {

48698

- /* The wrong dependency is on the enclosing double register. */

48699

- unsigned int x = REGNO (SET_DEST (set)) - 1;

48700

- unsigned int src1, src2, dest;

48701

- int code;

48702

-

48703

- /* If the insn has a delay slot, then it cannot be problematic. */

48704

- next = next_active_insn (insn);

48705

- if (NONJUMP_INSN_P (next) && GET_CODE (PATTERN (next)) == SEQUENCE)

48706

- code = -1;

48707

- else

48708

- {

48709

- extract_insn (next);

48710

- code = INSN_CODE (next);

48711

- }

48712

-

48713

- switch (code)

48714

- {

48715

- case CODE_FOR_adddf3:

48716

- case CODE_FOR_subdf3:

48717

- case CODE_FOR_muldf3:

48718

- case CODE_FOR_divdf3:

48719

- dest = REGNO (recog_data.operand[0]);

48720

- src1 = REGNO (recog_data.operand[1]);

48721

- src2 = REGNO (recog_data.operand[2]);

48722

- if (src1 != src2)

48723

- {

48724

- /* Case [1-4]:

48725

- ld [address], %fx+1

48726

- FPOPd %f{x,y}, %f{y,x}, %f{x,y} */

48727

- if ((src1 == x || src2 == x)

48728

- && (dest == src1 || dest == src2))

48729

- insert_nop = true;

48730

- }

48731

- else

48732

- {

48733

- /* Case 5:

48734

- ld [address], %fx+1

48735

- FPOPd %fx, %fx, %fx */

48736

- if (src1 == x

48737

- && dest == src1

48738

- && (code == CODE_FOR_adddf3 || code == CODE_FOR_muldf3))

48739

- insert_nop = true;

48740

- }

48741

- break;

48742

-

48743

- case CODE_FOR_sqrtdf2:

48744

- dest = REGNO (recog_data.operand[0]);

48745

- src1 = REGNO (recog_data.operand[1]);

48746

- /* Case 6:

48747

- ld [address], %fx+1

48748

- fsqrtd %fx, %fx */

48749

- if (src1 == x && dest == src1)

48750

- insert_nop = true;

48751

- break;

48752

-

48753

- default:

48754

- break;

48755

- }

48756

- }

48757

- else

48758

- next = NEXT_INSN (insn);

48759

-

48760

- if (insert_nop)

48761

- emit_insn_after (gen_nop (), insn);

48762

- }

48763

-}

48764

-

48765

/* How to allocate a 'struct machine_function'. */

48766

48767

static struct machine_function *

48768

Index: gcc/config/sparc/leon.md

48769

===================================================================

48770

--- a/src/gcc/config/sparc/leon.md (.../tags/gcc_4_8_2_release)

48771

+++ b/src/gcc/config/sparc/leon.md (.../branches/gcc-4_8-branch)

48772

@@ -17,40 +17,48 @@

48773

;; along with GCC; see the file COPYING3. If not see

48774

;; <http://www.gnu.org/licenses/>.

48775

48776

+;; Leon is a single-issue processor.

48777

48778

(define_automaton "leon")

48779

48780

-(define_cpu_unit "leon_memory, leon_fpalu" "leon")

48781

-(define_cpu_unit "leon_fpmds" "leon")

48782

-(define_cpu_unit "write_buf" "leon")

48783

+(define_cpu_unit "leon_memory" "leon")

48784

48785

(define_insn_reservation "leon_load" 1

48786

- (and (eq_attr "cpu" "leon")

48787

- (eq_attr "type" "load,sload,fpload"))

48788

+ (and (eq_attr "cpu" "leon") (eq_attr "type" "load,sload"))

48789

"leon_memory")

48790

48791

-(define_insn_reservation "leon_store" 1

48792

- (and (eq_attr "cpu" "leon")

48793

- (eq_attr "type" "store,fpstore"))

48794

- "leon_memory+write_buf")

48795

-

48796

-(define_insn_reservation "leon_fp_alu" 1

48797

- (and (eq_attr "cpu" "leon")

48798

- (eq_attr "type" "fp,fpmove"))

48799

- "leon_fpalu, nothing")

48800

+;; Use a double reservation to work around the load pipeline hazard on UT699.

48801

+(define_insn_reservation "leon3_load" 1

48802

+ (and (eq_attr "cpu" "leon3") (eq_attr "type" "load,sload"))

48803

+ "leon_memory*2")

48804

48805

-(define_insn_reservation "leon_fp_mult" 1

48806

- (and (eq_attr "cpu" "leon")

48807

- (eq_attr "type" "fpmul"))

48808

- "leon_fpmds, nothing")

48809

+(define_insn_reservation "leon_store" 2

48810

+ (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "store"))

48811

+ "leon_memory*2")

48812

48813

-(define_insn_reservation "leon_fp_div" 16

48814

- (and (eq_attr "cpu" "leon")

48815

- (eq_attr "type" "fpdivs,fpdivd"))

48816

- "leon_fpmds, nothing*15")

48817

+;; This describes Gaisler Research's FPU

48818

48819

-(define_insn_reservation "leon_fp_sqrt" 23

48820

- (and (eq_attr "cpu" "leon")

48821

- (eq_attr "type" "fpsqrts,fpsqrtd"))

48822

- "leon_fpmds, nothing*21")

48823

+(define_automaton "grfpu")

48824

48825

+(define_cpu_unit "grfpu_alu" "grfpu")

48826

+(define_cpu_unit "grfpu_ds" "grfpu")

48827

+

48828

+(define_insn_reservation "leon_fp_alu" 4

48829

+ (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fp,fpcmp,fpmul"))

48830

+ "grfpu_alu, nothing*3")

48831

+

48832

+(define_insn_reservation "leon_fp_divs" 16

48833

+ (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fpdivs"))

48834

+ "grfpu_ds*14, nothing*2")

48835

+

48836

+(define_insn_reservation "leon_fp_divd" 17

48837

+ (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fpdivd"))

48838

+ "grfpu_ds*15, nothing*2")

48839

+

48840

+(define_insn_reservation "leon_fp_sqrts" 24

48841

+ (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fpsqrts"))

48842

+ "grfpu_ds*22, nothing*2")

48843

+

48844

+(define_insn_reservation "leon_fp_sqrtd" 25

48845

+ (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fpsqrtd"))

48846

+ "grfpu_ds*23, nothing*2")

48847

Index: gcc/config/sparc/sparc.h

48848

===================================================================

48849

--- a/src/gcc/config/sparc/sparc.h (.../tags/gcc_4_8_2_release)

48850

+++ b/src/gcc/config/sparc/sparc.h (.../branches/gcc-4_8-branch)

48851

@@ -136,21 +136,22 @@

48852

#define TARGET_CPU_supersparc 2

48853

#define TARGET_CPU_hypersparc 3

48854

#define TARGET_CPU_leon 4

48855

-#define TARGET_CPU_sparclite 5

48856

-#define TARGET_CPU_f930 5 /* alias */

48857

-#define TARGET_CPU_f934 5 /* alias */

48858

-#define TARGET_CPU_sparclite86x 6

48859

-#define TARGET_CPU_sparclet 7

48860

-#define TARGET_CPU_tsc701 7 /* alias */

48861

-#define TARGET_CPU_v9 8 /* generic v9 implementation */

48862

-#define TARGET_CPU_sparcv9 8 /* alias */

48863

-#define TARGET_CPU_sparc64 8 /* alias */

48864

-#define TARGET_CPU_ultrasparc 9

48865

-#define TARGET_CPU_ultrasparc3 10

48866

-#define TARGET_CPU_niagara 11

48867

-#define TARGET_CPU_niagara2 12

48868

-#define TARGET_CPU_niagara3 13

48869

-#define TARGET_CPU_niagara4 14

48870

+#define TARGET_CPU_leon3 5

48871

+#define TARGET_CPU_sparclite 6

48872

+#define TARGET_CPU_f930 6 /* alias */

48873

+#define TARGET_CPU_f934 6 /* alias */

48874

+#define TARGET_CPU_sparclite86x 7

48875

+#define TARGET_CPU_sparclet 8

48876

+#define TARGET_CPU_tsc701 8 /* alias */

48877

+#define TARGET_CPU_v9 9 /* generic v9 implementation */

48878

+#define TARGET_CPU_sparcv9 9 /* alias */

48879

+#define TARGET_CPU_sparc64 9 /* alias */

48880

+#define TARGET_CPU_ultrasparc 10

48881

+#define TARGET_CPU_ultrasparc3 11

48882

+#define TARGET_CPU_niagara 12

48883

+#define TARGET_CPU_niagara2 13

48884

+#define TARGET_CPU_niagara3 14

48885

+#define TARGET_CPU_niagara4 15

48886

48887

#if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \

48888

|| TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \

48889

@@ -232,9 +233,10 @@

48890

#define ASM_CPU32_DEFAULT_SPEC ""

48891

#endif

48892

48893

-#if TARGET_CPU_DEFAULT == TARGET_CPU_leon

48894

+#if TARGET_CPU_DEFAULT == TARGET_CPU_leon \

48895

+ || TARGET_CPU_DEFAULT == TARGET_CPU_leon3

48896

#define CPP_CPU32_DEFAULT_SPEC "-D__leon__ -D__sparc_v8__"

48897

-#define ASM_CPU32_DEFAULT_SPEC ""

48898

+#define ASM_CPU32_DEFAULT_SPEC AS_LEON_FLAG

48899

#endif

48900

48901

#endif

48902

@@ -282,6 +284,7 @@

48903

%{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \

48904

%{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \

48905

%{mcpu=leon:-D__leon__ -D__sparc_v8__} \

48906

+%{mcpu=leon3:-D__leon__ -D__sparc_v8__} \

48907

%{mcpu=v9:-D__sparc_v9__} \

48908

%{mcpu=ultrasparc:-D__sparc_v9__} \

48909

%{mcpu=ultrasparc3:-D__sparc_v9__} \

48910

@@ -329,7 +332,8 @@

48911

%{mcpu=v8:-Av8} \

48912

%{mcpu=supersparc:-Av8} \

48913

%{mcpu=hypersparc:-Av8} \

48914

-%{mcpu=leon:-Av8} \

48915

+%{mcpu=leon:" AS_LEON_FLAG "} \

48916

+%{mcpu=leon3:" AS_LEON_FLAG "} \

48917

%{mv8plus:-Av8plus} \

48918

%{mcpu=v9:-Av9} \

48919

%{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \

48920

@@ -1754,6 +1758,12 @@

48921

#define AS_NIAGARA4_FLAG "-Av9" AS_NIAGARA3_FLAG

48922

#endif

48923

48924

+#ifdef HAVE_AS_LEON

48925

+#define AS_LEON_FLAG "-Aleon"

48926

+#else

48927

+#define AS_LEON_FLAG "-Av8"

48928

+#endif

48929

+

48930

/* We use gcc _mcount for profiling. */

48931

#define NO_PROFILE_COUNTERS 0

48932

48933

Index: gcc/config/i386/i386.h

48934

===================================================================

48935

--- a/src/gcc/config/i386/i386.h (.../tags/gcc_4_8_2_release)

48936

+++ b/src/gcc/config/i386/i386.h (.../branches/gcc-4_8-branch)

48937

@@ -197,10 +197,10 @@

48938

48939

/* Macros used in the machine description to test the flags. */

48940

48941

-/* configure can arrange to make this 2, to force a 486. */

48942

+/* configure can arrange to change it. */

48943

48944

#ifndef TARGET_CPU_DEFAULT

48945

-#define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_generic

48946

+#define TARGET_CPU_DEFAULT PROCESSOR_GENERIC32

48947

#endif

48948

48949

#ifndef TARGET_FPMATH_DEFAULT

48950

@@ -591,43 +591,6 @@

48951

/* Target Pragmas. */

48952

#define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas ()

48953

48954

-enum target_cpu_default

48955

-{

48956

- TARGET_CPU_DEFAULT_generic = 0,

48957

-

48958

- TARGET_CPU_DEFAULT_i386,

48959

- TARGET_CPU_DEFAULT_i486,

48960

- TARGET_CPU_DEFAULT_pentium,

48961

- TARGET_CPU_DEFAULT_pentium_mmx,

48962

- TARGET_CPU_DEFAULT_pentiumpro,

48963

- TARGET_CPU_DEFAULT_pentium2,

48964

- TARGET_CPU_DEFAULT_pentium3,

48965

- TARGET_CPU_DEFAULT_pentium4,

48966

- TARGET_CPU_DEFAULT_pentium_m,

48967

- TARGET_CPU_DEFAULT_prescott,

48968

- TARGET_CPU_DEFAULT_nocona,

48969

- TARGET_CPU_DEFAULT_core2,

48970

- TARGET_CPU_DEFAULT_corei7,

48971

- TARGET_CPU_DEFAULT_haswell,

48972

- TARGET_CPU_DEFAULT_atom,

48973

-

48974

- TARGET_CPU_DEFAULT_geode,

48975

- TARGET_CPU_DEFAULT_k6,

48976

- TARGET_CPU_DEFAULT_k6_2,

48977

- TARGET_CPU_DEFAULT_k6_3,

48978

- TARGET_CPU_DEFAULT_athlon,

48979

- TARGET_CPU_DEFAULT_athlon_sse,

48980

- TARGET_CPU_DEFAULT_k8,

48981

- TARGET_CPU_DEFAULT_amdfam10,

48982

- TARGET_CPU_DEFAULT_bdver1,

48983

- TARGET_CPU_DEFAULT_bdver2,

48984

- TARGET_CPU_DEFAULT_bdver3,

48985

- TARGET_CPU_DEFAULT_btver1,

48986

- TARGET_CPU_DEFAULT_btver2,

48987

-

48988

- TARGET_CPU_DEFAULT_max

48989

-};

48990

-

48991

#ifndef CC1_SPEC

48992

#define CC1_SPEC "%(cc1_cpu) "

48993

#endif

48994

@@ -2089,25 +2052,27 @@

48995

with x86-64 medium memory model */

48996

#define DEFAULT_LARGE_SECTION_THRESHOLD 65536

48997

48998

-/* Which processor to tune code generation for. */

48999

+/* Which processor to tune code generation for. These must be in sync

49000

+ with processor_target_table in i386.c. */

49001

49002

enum processor_type

49003

{

49004

- PROCESSOR_I386 = 0, /* 80386 */

49005

+ PROCESSOR_GENERIC32 = 0,

49006

+ PROCESSOR_GENERIC64,

49007

+ PROCESSOR_I386, /* 80386 */

49008

PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */

49009

PROCESSOR_PENTIUM,

49010

PROCESSOR_PENTIUMPRO,

49011

- PROCESSOR_GEODE,

49012

- PROCESSOR_K6,

49013

- PROCESSOR_ATHLON,

49014

PROCESSOR_PENTIUM4,

49015

- PROCESSOR_K8,

49016

PROCESSOR_NOCONA,

49017

PROCESSOR_CORE2,

49018

PROCESSOR_COREI7,

49019

PROCESSOR_HASWELL,

49020

- PROCESSOR_GENERIC32,

49021

- PROCESSOR_GENERIC64,

49022

+ PROCESSOR_ATOM,

49023

+ PROCESSOR_GEODE,

49024

+ PROCESSOR_K6,

49025

+ PROCESSOR_ATHLON,

49026

+ PROCESSOR_K8,

49027

PROCESSOR_AMDFAM10,

49028

PROCESSOR_BDVER1,

49029

PROCESSOR_BDVER2,

49030

@@ -2114,7 +2079,6 @@

49031

PROCESSOR_BDVER3,

49032

PROCESSOR_BTVER1,

49033

PROCESSOR_BTVER2,

49034

- PROCESSOR_ATOM,

49035

PROCESSOR_max

49036

};

49037

49038

Index: gcc/config/i386/i386.md

49039

===================================================================

49040

--- a/src/gcc/config/i386/i386.md (.../tags/gcc_4_8_2_release)

49041

+++ b/src/gcc/config/i386/i386.md (.../branches/gcc-4_8-branch)

49042

@@ -363,6 +363,13 @@

49043

(const_string "unknown")]

49044

(const_string "integer")))

49045

49046

+;; The minimum required alignment of vector mode memory operands of the SSE

49047

+;; (non-VEX/EVEX) instruction in bits, if it is different from

49048

+;; GET_MODE_ALIGNMENT of the operand, otherwise 0. If an instruction has

49049

+;; multiple alternatives, this should be conservative maximum of those minimum

49050

+;; required alignments.

49051

+(define_attr "ssememalign" "" (const_int 0))

49052

+

49053

;; The (bounding maximum) length of an instruction immediate.

49054

(define_attr "length_immediate" ""

49055

(cond [(eq_attr "type" "incdec,setcc,icmov,str,lea,other,multi,idiv,leave,

49056

@@ -1570,7 +1577,7 @@

49057

split_double_mode (DImode, &operands[1], 1, &operands[2], &operands[3]);

49058

49059

operands[1] = gen_lowpart (DImode, operands[2]);

49060

- operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,

49061

+ operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (Pmode, stack_pointer_rtx,

49062

GEN_INT (4)));

49063

})

49064

49065

@@ -1587,7 +1594,7 @@

49066

split_double_mode (DImode, &operands[1], 1, &operands[2], &operands[3]);

49067

49068

operands[1] = gen_lowpart (DImode, operands[2]);

49069

- operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,

49070

+ operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (Pmode, stack_pointer_rtx,

49071

GEN_INT (4)));

49072

})

49073

49074

@@ -2715,7 +2722,20 @@

49075

"reload_completed"

49076

[(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (match_dup 2)))

49077

(set (mem:SF (reg:P SP_REG)) (match_dup 1))]

49078

- "operands[2] = GEN_INT (-GET_MODE_SIZE (<P:MODE>mode));")

49079

+{

49080

+ rtx op = XEXP (operands[0], 0);

49081

+ if (GET_CODE (op) == PRE_DEC)

49082

+ {

49083

+ gcc_assert (!TARGET_64BIT);

49084

+ op = GEN_INT (-4);

49085

+ }

49086

+ else

49087

+ {

49088

+ op = XEXP (XEXP (op, 1), 1);

49089

+ gcc_assert (CONST_INT_P (op));

49090

+ }

49091

+ operands[2] = op;

49092

+})

49093

49094

(define_split

49095

[(set (match_operand:SF 0 "push_operand")

49096

@@ -5443,6 +5463,12 @@

49097

mode = SImode;

49098

49099

ix86_split_lea_for_addr (curr_insn, operands, mode);

49100

+

49101

+ /* Zero-extend return register to DImode for zero-extended addresses. */

49102

+ if (mode != <MODE>mode)

49103

+ emit_insn (gen_zero_extendsidi2

49104

+ (operands[0], gen_lowpart (mode, operands[0])));

49105

+

49106

DONE;

49107

}

49108

[(set_attr "type" "lea")

49109

@@ -6589,7 +6615,7 @@

49110

(set_attr "use_carry" "1")

49111

(set_attr "mode" "<MODE>")])

49112

49113

-;; Overflow setting add and subtract instructions

49114

+;; Overflow setting add instructions

49115

49116

(define_insn "*add<mode>3_cconly_overflow"

49117

[(set (reg:CCC FLAGS_REG)

49118

@@ -6604,43 +6630,31 @@

49119

[(set_attr "type" "alu")

49120

(set_attr "mode" "<MODE>")])

49121

49122

-(define_insn "*sub<mode>3_cconly_overflow"

49123

+(define_insn "*add<mode>3_cc_overflow"

49124

[(set (reg:CCC FLAGS_REG)

49125

(compare:CCC

49126

- (minus:SWI

49127

- (match_operand:SWI 0 "nonimmediate_operand" "<r>m,<r>")

49128

- (match_operand:SWI 1 "<general_operand>" "<r><i>,<r>m"))

49129

- (match_dup 0)))]

49130

- ""

49131

- "cmp{<imodesuffix>}\t{%1, %0|%0, %1}"

49132

- [(set_attr "type" "icmp")

49133

- (set_attr "mode" "<MODE>")])

49134

-

49135

-(define_insn "*<plusminus_insn><mode>3_cc_overflow"

49136

- [(set (reg:CCC FLAGS_REG)

49137

- (compare:CCC

49138

- (plusminus:SWI

49139

- (match_operand:SWI 1 "nonimmediate_operand" "<comm>0,0")

49140

+ (plus:SWI

49141

+ (match_operand:SWI 1 "nonimmediate_operand" "%0,0")

49142

(match_operand:SWI 2 "<general_operand>" "<r><i>,<r>m"))

49143

(match_dup 1)))

49144

(set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")

49145

- (plusminus:SWI (match_dup 1) (match_dup 2)))]

49146

- "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"

49147

- "<plusminus_mnemonic>{<imodesuffix>}\t{%2, %0|%0, %2}"

49148

+ (plus:SWI (match_dup 1) (match_dup 2)))]

49149

+ "ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"

49150

+ "add{<imodesuffix>}\t{%2, %0|%0, %2}"

49151

[(set_attr "type" "alu")

49152

(set_attr "mode" "<MODE>")])

49153

49154

-(define_insn "*<plusminus_insn>si3_zext_cc_overflow"

49155

+(define_insn "*addsi3_zext_cc_overflow"

49156

[(set (reg:CCC FLAGS_REG)

49157

(compare:CCC

49158

- (plusminus:SI

49159

- (match_operand:SI 1 "nonimmediate_operand" "<comm>0")

49160

+ (plus:SI

49161

+ (match_operand:SI 1 "nonimmediate_operand" "%0")

49162

(match_operand:SI 2 "x86_64_general_operand" "rme"))

49163

(match_dup 1)))

49164

(set (match_operand:DI 0 "register_operand" "=r")

49165

- (zero_extend:DI (plusminus:SI (match_dup 1) (match_dup 2))))]

49166

- "TARGET_64BIT && ix86_binary_operator_ok (<CODE>, SImode, operands)"

49167

- "<plusminus_mnemonic>{l}\t{%2, %k0|%k0, %2}"

49168

+ (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]

49169

+ "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"

49170

+ "add{l}\t{%2, %k0|%k0, %2}"

49171

[(set_attr "type" "alu")

49172

(set_attr "mode" "SI")])

49173

49174

@@ -8012,7 +8026,18 @@

49175

(const_int 0)))

49176

(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,rm")

49177

(and:DI (match_dup 1) (match_dup 2)))]

49178

- "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)

49179

+ "TARGET_64BIT

49180

+ && ix86_match_ccmode

49181

+ (insn,

49182

+ /* If we are going to emit andl instead of andq, and the operands[2]

49183

+ constant might have the SImode sign bit set, make sure the sign

49184

+ flag isn't tested, because the instruction will set the sign flag

49185

+ based on bit 31 rather than bit 63. If it isn't CONST_INT,

49186

+ conservatively assume it might have bit 31 set. */

49187

+ (satisfies_constraint_Z (operands[2])

49188

+ && (!CONST_INT_P (operands[2])

49189

+ || val_signbit_known_set_p (SImode, INTVAL (operands[2]))))

49190

+ ? CCZmode : CCNOmode)

49191

&& ix86_binary_operator_ok (AND, DImode, operands)"

49192

"@

49193

and{l}\t{%k2, %k0|%k0, %k2}

49194

@@ -17569,7 +17594,13 @@

49195

(define_insn "trap"

49196

[(trap_if (const_int 1) (const_int 6))]

49197

""

49198

- { return ASM_SHORT "0x0b0f"; }

49199

+{

49200

+#ifdef HAVE_AS_IX86_UD2

49201

+ return "ud2";

49202

+#else

49203

+ return ASM_SHORT "0x0b0f";

49204

+#endif

49205

+}

49206

[(set_attr "length" "2")])

49207

49208

(define_expand "prefetch"

49209

Index: gcc/config/i386/f16cintrin.h

49210

===================================================================

49211

--- a/src/gcc/config/i386/f16cintrin.h (.../tags/gcc_4_8_2_release)

49212

+++ b/src/gcc/config/i386/f16cintrin.h (.../branches/gcc-4_8-branch)

49213

@@ -35,7 +35,7 @@

49214

extern __inline float __attribute__((__gnu_inline__, __always_inline__, __artificial__))

49215

_cvtsh_ss (unsigned short __S)

49216

{

49217

- __v8hi __H = __extension__ (__v8hi){ __S, 0, 0, 0, 0, 0, 0, 0 };

49218

+ __v8hi __H = __extension__ (__v8hi){ (short) __S, 0, 0, 0, 0, 0, 0, 0 };

49219

__v4sf __A = __builtin_ia32_vcvtph2ps (__H);

49220

return __builtin_ia32_vec_ext_v4sf (__A, 0);

49221

}

49222

Index: gcc/config/i386/t-rtems

49223

===================================================================

49224

--- a/src/gcc/config/i386/t-rtems (.../tags/gcc_4_8_2_release)

49225

+++ b/src/gcc/config/i386/t-rtems (.../branches/gcc-4_8-branch)

49226

@@ -17,11 +17,10 @@

49227

# <http://www.gnu.org/licenses/>.

49228

#

49229

49230

-MULTILIB_OPTIONS = mtune=i486/mtune=pentium/mtune=pentiumpro \

49231

-msoft-float

49232

+MULTILIB_OPTIONS = mtune=i486/mtune=pentium/mtune=pentiumpro msoft-float

49233

MULTILIB_DIRNAMES= m486 mpentium mpentiumpro soft-float

49234

-MULTILIB_MATCHES = msoft-float=mno-m80387

49235

-MULTILIB_MATCHES += mtune?pentium=mtune?k6 mtune?pentiumpro=mtune?mathlon

49236

+MULTILIB_MATCHES = msoft-float=mno-80387

49237

+MULTILIB_MATCHES += mtune?pentium=mtune?k6 mtune?pentiumpro=mtune?athlon

49238

MULTILIB_EXCEPTIONS = \

49239

mtune=pentium/*msoft-float* \

49240

mtune=pentiumpro/*msoft-float*

49241

Index: gcc/config/i386/winnt.c

49242

===================================================================

49243

--- a/src/gcc/config/i386/winnt.c (.../tags/gcc_4_8_2_release)

49244

+++ b/src/gcc/config/i386/winnt.c (.../branches/gcc-4_8-branch)

49245

@@ -547,8 +547,9 @@

49246

sets 'discard' characteristic, rather than telling linker

49247

to warn of size or content mismatch, so do the same. */

49248

bool discard = (flags & SECTION_CODE)

49249

- || lookup_attribute ("selectany",

49250

- DECL_ATTRIBUTES (decl));

49251

+ || (TREE_CODE (decl) != IDENTIFIER_NODE

49252

+ && lookup_attribute ("selectany",

49253

+ DECL_ATTRIBUTES (decl)));

49254

fprintf (asm_out_file, "\t.linkonce %s\n",

49255

(discard ? "discard" : "same_size"));

49256

}

49257

Index: gcc/config/i386/sse.md

49258

===================================================================

49259

--- a/src/gcc/config/i386/sse.md (.../tags/gcc_4_8_2_release)

49260

+++ b/src/gcc/config/i386/sse.md (.../branches/gcc-4_8-branch)

49261

@@ -605,6 +605,7 @@

49262

}

49263

[(set_attr "type" "ssemov")

49264

(set_attr "movu" "1")

49265

+ (set_attr "ssememalign" "8")

49266

(set_attr "prefix" "maybe_vex")

49267

(set (attr "mode")

49268

(cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")

49269

@@ -634,6 +635,7 @@

49270

}

49271

[(set_attr "type" "ssemov")

49272

(set_attr "movu" "1")

49273

+ (set_attr "ssememalign" "8")

49274

(set_attr "prefix" "maybe_vex")

49275

(set (attr "mode")

49276

(cond [(ior (match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")

49277

@@ -663,6 +665,7 @@

49278

}

49279

[(set_attr "type" "ssemov")

49280

(set_attr "movu" "1")

49281

+ (set_attr "ssememalign" "8")

49282

(set (attr "prefix_data16")

49283

(if_then_else

49284

(match_test "TARGET_AVX")

49285

@@ -696,6 +699,7 @@

49286

}

49287

[(set_attr "type" "ssemov")

49288

(set_attr "movu" "1")

49289

+ (set_attr "ssememalign" "8")

49290

(set (attr "prefix_data16")

49291

(if_then_else

49292

(match_test "TARGET_AVX")

49293

@@ -721,6 +725,7 @@

49294

"%vlddqu\t{%1, %0|%0, %1}"

49295

[(set_attr "type" "ssemov")

49296

(set_attr "movu" "1")

49297

+ (set_attr "ssememalign" "8")

49298

(set (attr "prefix_data16")

49299

(if_then_else

49300

(match_test "TARGET_AVX")

49301

@@ -1001,6 +1006,7 @@

49302

vrcpss\t{%1, %2, %0|%0, %2, %1}"

49303

[(set_attr "isa" "noavx,avx")

49304

(set_attr "type" "sse")

49305

+ (set_attr "ssememalign" "32")

49306

(set_attr "atom_sse_attr" "rcp")

49307

(set_attr "btver2_sse_attr" "rcp")

49308

(set_attr "prefix" "orig,vex")

49309

@@ -1089,6 +1095,7 @@

49310

vrsqrtss\t{%1, %2, %0|%0, %2, %1}"

49311

[(set_attr "isa" "noavx,avx")

49312

(set_attr "type" "sse")

49313

+ (set_attr "ssememalign" "32")

49314

(set_attr "prefix" "orig,vex")

49315

(set_attr "mode" "SF")])

49316

49317

@@ -2844,6 +2851,7 @@

49318

"%vcvtdq2pd\t{%1, %0|%0, %q1}"

49319

[(set_attr "type" "ssecvt")

49320

(set_attr "prefix" "maybe_vex")

49321

+ (set_attr "ssememalign" "64")

49322

(set_attr "mode" "V2DF")])

49323

49324

(define_insn "avx_cvtpd2dq256"

49325

@@ -3572,6 +3580,7 @@

49326

%vmovhps\t{%2, %0|%0, %2}"

49327

[(set_attr "isa" "noavx,avx,noavx,avx,*")

49328

(set_attr "type" "ssemov")

49329

+ (set_attr "ssememalign" "64")

49330

(set_attr "prefix" "orig,vex,orig,vex,maybe_vex")

49331

(set_attr "mode" "V4SF,V4SF,V2SF,V2SF,V2SF")])

49332

49333

@@ -3617,6 +3626,7 @@

49334

%vmovlps\t{%2, %H0|%H0, %2}"

49335

[(set_attr "isa" "noavx,avx,noavx,avx,*")

49336

(set_attr "type" "ssemov")

49337

+ (set_attr "ssememalign" "64")

49338

(set_attr "prefix" "orig,vex,orig,vex,maybe_vex")

49339

(set_attr "mode" "V4SF,V4SF,V2SF,V2SF,V2SF")])

49340

49341

@@ -3941,6 +3951,7 @@

49342

%vmovhlps\t{%1, %d0|%d0, %1}

49343

%vmovlps\t{%H1, %d0|%d0, %H1}"

49344

[(set_attr "type" "ssemov")

49345

+ (set_attr "ssememalign" "64")

49346

(set_attr "prefix" "maybe_vex")

49347

(set_attr "mode" "V2SF,V4SF,V2SF")])

49348

49349

@@ -3980,6 +3991,7 @@

49350

%vmovlps\t{%2, %H0|%H0, %2}"

49351

[(set_attr "isa" "noavx,avx,noavx,avx,*")

49352

(set_attr "type" "ssemov")

49353

+ (set_attr "ssememalign" "64")

49354

(set_attr "prefix" "orig,vex,orig,vex,maybe_vex")

49355

(set_attr "mode" "V2SF,V2SF,V4SF,V4SF,V2SF")])

49356

49357

@@ -4033,6 +4045,7 @@

49358

%vmovlps\t{%2, %0|%0, %2}"

49359

[(set_attr "isa" "noavx,avx,noavx,avx,*")

49360

(set_attr "type" "sseshuf,sseshuf,ssemov,ssemov,ssemov")

49361

+ (set_attr "ssememalign" "64")

49362

(set_attr "length_immediate" "1,1,*,*,*")

49363

(set_attr "prefix" "orig,vex,orig,vex,maybe_vex")

49364

(set_attr "mode" "V4SF,V4SF,V2SF,V2SF,V2SF")])

49365

@@ -4642,7 +4655,8 @@

49366

vmovlpd\t{%H1, %2, %0|%0, %2, %H1}

49367

%vmovhpd\t{%1, %0|%0, %1}"

49368

[(set_attr "isa" "noavx,avx,sse3,noavx,avx,*")

49369

- (set_attr "type" "sselog,sselog,sselog,ssemov,ssemov,ssemov")

49370

+ (set_attr "type" "sselog,sselog,sselog,ssemov,ssemov,ssemov")

49371

+ (set_attr "ssememalign" "64")

49372

(set_attr "prefix_data16" "*,*,*,1,*,1")

49373

(set_attr "prefix" "orig,vex,maybe_vex,orig,vex,maybe_vex")

49374

(set_attr "mode" "V2DF,V2DF,DF,V1DF,V1DF,V1DF")])

49375

@@ -4744,6 +4758,7 @@

49376

%vmovlpd\t{%2, %H0|%H0, %2}"

49377

[(set_attr "isa" "noavx,avx,sse3,noavx,avx,*")

49378

(set_attr "type" "sselog,sselog,sselog,ssemov,ssemov,ssemov")

49379

+ (set_attr "ssememalign" "64")

49380

(set_attr "prefix_data16" "*,*,*,1,*,1")

49381

(set_attr "prefix" "orig,vex,maybe_vex,orig,vex,maybe_vex")

49382

(set_attr "mode" "V2DF,V2DF,DF,V1DF,V1DF,V1DF")])

49383

@@ -4982,6 +4997,7 @@

49384

movhlps\t{%1, %0|%0, %1}

49385

movlps\t{%H1, %0|%0, %H1}"

49386

[(set_attr "type" "ssemov")

49387

+ (set_attr "ssememalign" "64")

49388

(set_attr "mode" "V2SF,V4SF,V2SF")])

49389

49390

;; Avoid combining registers from different units in a single alternative,

49391

@@ -5077,6 +5093,7 @@

49392

#"

49393

[(set_attr "isa" "noavx,avx,noavx,avx,*,*,*")

49394

(set_attr "type" "ssemov,ssemov,sselog,sselog,ssemov,fmov,imov")

49395

+ (set_attr "ssememalign" "64")

49396

(set_attr "prefix_data16" "1,*,*,*,*,*,*")

49397

(set_attr "prefix" "orig,vex,orig,vex,*,*,*")

49398

(set_attr "mode" "V1DF,V1DF,V2DF,V2DF,DF,DF,DF")])

49399

@@ -5145,6 +5162,7 @@

49400

(const_string "imov")

49401

]

49402

(const_string "ssemov")))

49403

+ (set_attr "ssememalign" "64")

49404

(set_attr "prefix_data16" "*,1,*,*,*,*,1,*,*,*,*")

49405

(set_attr "length_immediate" "*,*,*,*,*,1,*,*,*,*,*")

49406

(set_attr "prefix" "maybe_vex,orig,vex,orig,vex,orig,orig,vex,*,*,*")

49407

@@ -5189,6 +5207,7 @@

49408

(const_string "1")

49409

(const_string "*")))

49410

(set_attr "length_immediate" "*,*,*,*,*,1,*,*,*")

49411

+ (set_attr "ssememalign" "64")

49412

(set_attr "prefix" "orig,vex,orig,vex,maybe_vex,orig,orig,vex,maybe_vex")

49413

(set_attr "mode" "DF,DF,V1DF,V1DF,V1DF,V2DF,V1DF,V1DF,V1DF")])

49414

49415

@@ -8736,6 +8755,7 @@

49416

"TARGET_SSE4_1"

49417

"%vpmov<extsuffix>bw\t{%1, %0|%0, %q1}"

49418

[(set_attr "type" "ssemov")

49419

+ (set_attr "ssememalign" "64")

49420

(set_attr "prefix_extra" "1")

49421

(set_attr "prefix" "maybe_vex")

49422

(set_attr "mode" "TI")])

49423

@@ -8766,6 +8786,7 @@

49424

"TARGET_SSE4_1"

49425

"%vpmov<extsuffix>bd\t{%1, %0|%0, %k1}"

49426

[(set_attr "type" "ssemov")

49427

+ (set_attr "ssememalign" "32")

49428

(set_attr "prefix_extra" "1")

49429

(set_attr "prefix" "maybe_vex")

49430

(set_attr "mode" "TI")])

49431

@@ -8791,6 +8812,7 @@

49432

"TARGET_SSE4_1"

49433

"%vpmov<extsuffix>wd\t{%1, %0|%0, %q1}"

49434

[(set_attr "type" "ssemov")

49435

+ (set_attr "ssememalign" "64")

49436

(set_attr "prefix_extra" "1")

49437

(set_attr "prefix" "maybe_vex")

49438

(set_attr "mode" "TI")])

49439

@@ -8818,6 +8840,7 @@

49440

"TARGET_SSE4_1"

49441

"%vpmov<extsuffix>bq\t{%1, %0|%0, %w1}"

49442

[(set_attr "type" "ssemov")

49443

+ (set_attr "ssememalign" "16")

49444

(set_attr "prefix_extra" "1")

49445

(set_attr "prefix" "maybe_vex")

49446

(set_attr "mode" "TI")])

49447

@@ -8845,6 +8868,7 @@

49448

"TARGET_SSE4_1"

49449

"%vpmov<extsuffix>wq\t{%1, %0|%0, %k1}"

49450

[(set_attr "type" "ssemov")

49451

+ (set_attr "ssememalign" "32")

49452

(set_attr "prefix_extra" "1")

49453

(set_attr "prefix" "maybe_vex")

49454

(set_attr "mode" "TI")])

49455

@@ -8868,6 +8892,7 @@

49456

"TARGET_SSE4_1"

49457

"%vpmov<extsuffix>dq\t{%1, %0|%0, %q1}"

49458

[(set_attr "type" "ssemov")

49459

+ (set_attr "ssememalign" "64")

49460

(set_attr "prefix_extra" "1")

49461

(set_attr "prefix" "maybe_vex")

49462

(set_attr "mode" "TI")])

49463

@@ -9151,6 +9176,7 @@

49464

[(set_attr "type" "sselog")

49465

(set_attr "prefix_data16" "1")

49466

(set_attr "prefix_extra" "1")

49467

+ (set_attr "ssememalign" "8")

49468

(set_attr "length_immediate" "1")

49469

(set_attr "memory" "none,load")

49470

(set_attr "mode" "TI")])

49471

@@ -9213,6 +9239,7 @@

49472

[(set_attr "type" "sselog")

49473

(set_attr "prefix_data16" "1")

49474

(set_attr "prefix_extra" "1")

49475

+ (set_attr "ssememalign" "8")

49476

(set_attr "length_immediate" "1")

49477

(set_attr "memory" "load")

49478

(set_attr "mode" "TI")])

49479

@@ -9240,6 +9267,7 @@

49480

(set_attr "prefix_data16" "1")

49481

(set_attr "prefix_extra" "1")

49482

(set_attr "prefix" "maybe_vex")

49483

+ (set_attr "ssememalign" "8")

49484

(set_attr "length_immediate" "1")

49485

(set_attr "btver2_decode" "vector")

49486

(set_attr "memory" "none,load")

49487

@@ -9267,6 +9295,7 @@

49488

[(set_attr "type" "sselog")

49489

(set_attr "prefix_data16" "1")

49490

(set_attr "prefix_extra" "1")

49491

+ (set_attr "ssememalign" "8")

49492

(set_attr "length_immediate" "1")

49493

(set_attr "prefix" "maybe_vex")

49494

(set_attr "btver2_decode" "vector")

49495

@@ -9293,6 +9322,7 @@

49496

[(set_attr "type" "sselog")

49497

(set_attr "prefix_data16" "1")

49498

(set_attr "prefix_extra" "1")

49499

+ (set_attr "ssememalign" "8")

49500

(set_attr "length_immediate" "1")

49501

(set_attr "memory" "none,load,none,load")

49502

(set_attr "btver2_decode" "vector,vector,vector,vector")

49503

@@ -9346,6 +9376,7 @@

49504

[(set_attr "type" "sselog")

49505

(set_attr "prefix_data16" "1")

49506

(set_attr "prefix_extra" "1")

49507

+ (set_attr "ssememalign" "8")

49508

(set_attr "length_immediate" "1")

49509

(set_attr "memory" "none,load")

49510

(set_attr "mode" "TI")])

49511

@@ -9399,6 +9430,7 @@

49512

[(set_attr "type" "sselog")

49513

(set_attr "prefix_data16" "1")

49514

(set_attr "prefix_extra" "1")

49515

+ (set_attr "ssememalign" "8")

49516

(set_attr "length_immediate" "1")

49517

(set_attr "memory" "load")

49518

(set_attr "mode" "TI")])

49519

@@ -9421,6 +9453,7 @@

49520

[(set_attr "type" "sselog")

49521

(set_attr "prefix_data16" "1")

49522

(set_attr "prefix_extra" "1")

49523

+ (set_attr "ssememalign" "8")

49524

(set_attr "length_immediate" "1")

49525

(set_attr "prefix" "maybe_vex")

49526

(set_attr "memory" "none,load")

49527

@@ -9445,6 +9478,7 @@

49528

[(set_attr "type" "sselog")

49529

(set_attr "prefix_data16" "1")

49530

(set_attr "prefix_extra" "1")

49531

+ (set_attr "ssememalign" "8")

49532

(set_attr "length_immediate" "1")

49533

(set_attr "prefix" "maybe_vex")

49534

(set_attr "memory" "none,load")

49535

@@ -9469,6 +9503,7 @@

49536

[(set_attr "type" "sselog")

49537

(set_attr "prefix_data16" "1")

49538

(set_attr "prefix_extra" "1")

49539

+ (set_attr "ssememalign" "8")

49540

(set_attr "length_immediate" "1")

49541

(set_attr "memory" "none,load,none,load")

49542

(set_attr "prefix" "maybe_vex")

49543

@@ -10213,7 +10248,6 @@

49544

[(set_attr "type" "ssecvt1")

49545

(set_attr "mode" "<MODE>")])

49546

49547

-;; scalar insns

49548

(define_expand "xop_vmfrcz<mode>2"

49549

[(set (match_operand:VF_128 0 "register_operand")

49550

(vec_merge:VF_128

49551

@@ -10220,14 +10254,12 @@

49552

(unspec:VF_128

49553

[(match_operand:VF_128 1 "nonimmediate_operand")]

49554

UNSPEC_FRCZ)

49555

- (match_dup 3)

49556

+ (match_dup 2)

49557

(const_int 1)))]

49558

"TARGET_XOP"

49559

-{

49560

- operands[3] = CONST0_RTX (<MODE>mode);

49561

-})

49562

+ "operands[2] = CONST0_RTX (<MODE>mode);")

49563

49564

-(define_insn "*xop_vmfrcz_<mode>"

49565

+(define_insn "*xop_vmfrcz<mode>2"

49566

[(set (match_operand:VF_128 0 "register_operand" "=x")

49567

(vec_merge:VF_128

49568

(unspec:VF_128

49569

Index: gcc/config/i386/xopintrin.h

49570

===================================================================

49571

--- a/src/gcc/config/i386/xopintrin.h (.../tags/gcc_4_8_2_release)

49572

+++ b/src/gcc/config/i386/xopintrin.h (.../branches/gcc-4_8-branch)

49573

@@ -745,13 +745,17 @@

49574

extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))

49575

_mm_frcz_ss (__m128 __A, __m128 __B)

49576

{

49577

- return (__m128) __builtin_ia32_vfrczss ((__v4sf)__A, (__v4sf)__B);

49578

+ return (__m128) __builtin_ia32_movss ((__v4sf)__A,

49579

+ (__v4sf)

49580

+ __builtin_ia32_vfrczss ((__v4sf)__B));

49581

}

49582

49583

extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))

49584

_mm_frcz_sd (__m128d __A, __m128d __B)

49585

{

49586

- return (__m128d) __builtin_ia32_vfrczsd ((__v2df)__A, (__v2df)__B);

49587

+ return (__m128d) __builtin_ia32_movsd ((__v2df)__A,

49588

+ (__v2df)

49589

+ __builtin_ia32_vfrczsd ((__v2df)__B));

49590

}

49591

49592

extern __inline __m256 __attribute__((__gnu_inline__, __always_inline__, __artificial__))

49593

Index: gcc/config/i386/driver-i386.c

49594

===================================================================

49595

--- a/src/gcc/config/i386/driver-i386.c (.../tags/gcc_4_8_2_release)

49596

+++ b/src/gcc/config/i386/driver-i386.c (.../branches/gcc-4_8-branch)

49597

@@ -126,6 +126,18 @@

49598

case 0x0c:

49599

level1->sizekb = 16; level1->assoc = 4; level1->line = 32;

49600

break;

49601

+ case 0x0d:

49602

+ level1->sizekb = 16; level1->assoc = 4; level1->line = 64;

49603

+ break;

49604

+ case 0x0e:

49605

+ level1->sizekb = 24; level1->assoc = 6; level1->line = 64;

49606

+ break;

49607

+ case 0x21:

49608

+ level2->sizekb = 256; level2->assoc = 8; level2->line = 64;

49609

+ break;

49610

+ case 0x24:

49611

+ level2->sizekb = 1024; level2->assoc = 16; level2->line = 64;

49612

+ break;

49613

case 0x2c:

49614

level1->sizekb = 32; level1->assoc = 8; level1->line = 64;

49615

break;

49616

@@ -162,6 +174,9 @@

49617

case 0x45:

49618

level2->sizekb = 2048; level2->assoc = 4; level2->line = 32;

49619

break;

49620

+ case 0x48:

49621

+ level2->sizekb = 3072; level2->assoc = 12; level2->line = 64;

49622

+ break;

49623

case 0x49:

49624

if (xeon_mp)

49625

break;

49626

@@ -203,6 +218,9 @@

49627

case 0x7f:

49628

level2->sizekb = 512; level2->assoc = 2; level2->line = 64;

49629

break;

49630

+ case 0x80:

49631

+ level2->sizekb = 512; level2->assoc = 8; level2->line = 64;

49632

+ break;

49633

case 0x82:

49634

level2->sizekb = 256; level2->assoc = 8; level2->line = 32;

49635

break;

49636

@@ -470,6 +488,28 @@

49637

has_xsaveopt = eax & bit_XSAVEOPT;

49638

}

49639

49640

+ /* Check cpuid level of extended features. */

49641

+ __cpuid (0x80000000, ext_level, ebx, ecx, edx);

49642

+

49643

+ if (ext_level > 0x80000000)

49644

+ {

49645

+ __cpuid (0x80000001, eax, ebx, ecx, edx);

49646

+

49647

+ has_lahf_lm = ecx & bit_LAHF_LM;

49648

+ has_sse4a = ecx & bit_SSE4a;

49649

+ has_abm = ecx & bit_ABM;

49650

+ has_lwp = ecx & bit_LWP;

49651

+ has_fma4 = ecx & bit_FMA4;

49652

+ has_xop = ecx & bit_XOP;

49653

+ has_tbm = ecx & bit_TBM;

49654

+ has_lzcnt = ecx & bit_LZCNT;

49655

+ has_prfchw = ecx & bit_PRFCHW;

49656

+

49657

+ has_longmode = edx & bit_LM;

49658

+ has_3dnowp = edx & bit_3DNOWP;

49659

+ has_3dnow = edx & bit_3DNOW;

49660

+ }

49661

+

49662

/* Get XCR_XFEATURE_ENABLED_MASK register with xgetbv. */

49663

#define XCR_XFEATURE_ENABLED_MASK 0x0

49664

#define XSTATE_FP 0x1

49665

@@ -488,33 +528,12 @@

49666

has_avx2 = 0;

49667

has_fma = 0;

49668

has_fma4 = 0;

49669

+ has_f16c = 0;

49670

has_xop = 0;

49671

has_xsave = 0;

49672

has_xsaveopt = 0;

49673

}

49674

49675

- /* Check cpuid level of extended features. */

49676

- __cpuid (0x80000000, ext_level, ebx, ecx, edx);

49677

-

49678

- if (ext_level > 0x80000000)

49679

- {

49680

- __cpuid (0x80000001, eax, ebx, ecx, edx);

49681

-

49682

- has_lahf_lm = ecx & bit_LAHF_LM;

49683

- has_sse4a = ecx & bit_SSE4a;

49684

- has_abm = ecx & bit_ABM;

49685

- has_lwp = ecx & bit_LWP;

49686

- has_fma4 = ecx & bit_FMA4;

49687

- has_xop = ecx & bit_XOP;

49688

- has_tbm = ecx & bit_TBM;

49689

- has_lzcnt = ecx & bit_LZCNT;

49690

- has_prfchw = ecx & bit_PRFCHW;

49691

-

49692

- has_longmode = edx & bit_LM;

49693

- has_3dnowp = edx & bit_3DNOWP;

49694

- has_3dnow = edx & bit_3DNOW;

49695

- }

49696

-

49697

if (!arch)

49698

{

49699

if (vendor == signature_AMD_ebx

49700

Index: gcc/config/i386/i386.c

49701

===================================================================

49702

--- a/src/gcc/config/i386/i386.c (.../tags/gcc_4_8_2_release)

49703

+++ b/src/gcc/config/i386/i386.c (.../branches/gcc-4_8-branch)

49704

@@ -1378,7 +1378,7 @@

49705

8, /* MMX or SSE register to integer */

49706

8, /* size of l1 cache. */

49707

1024, /* size of l2 cache. */

49708

- 128, /* size of prefetch block */

49709

+ 64, /* size of prefetch block */

49710

8, /* number of parallel prefetches */

49711

1, /* Branch cost */

49712

COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */

49713

@@ -1894,10 +1894,10 @@

49714

49715

49716

/* X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL */

49717

- m_COREI7 | m_AMDFAM10 | m_BDVER | m_BTVER,

49718

+ m_COREI7 | m_HASWELL | m_AMDFAM10 | m_BDVER | m_BTVER,

49719

49720

/* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL */

49721

- m_COREI7 | m_BDVER,

49722

+ m_COREI7 | m_HASWELL| m_BDVER,

49723

49724

/* X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL */

49725

m_BDVER ,

49726

@@ -2409,6 +2409,7 @@

49727

/* Processor target table, indexed by processor number */

49728

struct ptt

49729

{

49730

+ const char *const name; /* processor name */

49731

const struct processor_costs *cost; /* Processor costs */

49732

const int align_loop; /* Default alignments. */

49733

const int align_loop_max_skip;

49734

@@ -2417,67 +2418,32 @@

49735

const int align_func;

49736

};

49737

49738

+/* This table must be in sync with enum processor_type in i386.h. */

49739

static const struct ptt processor_target_table[PROCESSOR_max] =

49740

{

49741

- {&i386_cost, 4, 3, 4, 3, 4},

49742

- {&i486_cost, 16, 15, 16, 15, 16},

49743

- {&pentium_cost, 16, 7, 16, 7, 16},

49744

- {&pentiumpro_cost, 16, 15, 16, 10, 16},

49745

- {&geode_cost, 0, 0, 0, 0, 0},

49746

- {&k6_cost, 32, 7, 32, 7, 32},

49747

- {&athlon_cost, 16, 7, 16, 7, 16},

49748

- {&pentium4_cost, 0, 0, 0, 0, 0},

49749

- {&k8_cost, 16, 7, 16, 7, 16},

49750

- {&nocona_cost, 0, 0, 0, 0, 0},

49751

- /* Core 2 */

49752

- {&core_cost, 16, 10, 16, 10, 16},

49753

- /* Core i7 */

49754

- {&core_cost, 16, 10, 16, 10, 16},

49755

- /* Core avx2 */

49756

- {&core_cost, 16, 10, 16, 10, 16},

49757

- {&generic32_cost, 16, 7, 16, 7, 16},

49758

- {&generic64_cost, 16, 10, 16, 10, 16},

49759

- {&amdfam10_cost, 32, 24, 32, 7, 32},

49760

- {&bdver1_cost, 16, 10, 16, 7, 11},

49761

- {&bdver2_cost, 16, 10, 16, 7, 11},

49762

- {&bdver3_cost, 16, 10, 16, 7, 11},

49763

- {&btver1_cost, 16, 10, 16, 7, 11},

49764

- {&btver2_cost, 16, 10, 16, 7, 11},

49765

- {&atom_cost, 16, 15, 16, 7, 16}

49766

+ {"generic", &generic32_cost, 16, 7, 16, 7, 16},

49767

+ {"generic", &generic64_cost, 16, 10, 16, 10, 16},

49768

+ {"i386", &i386_cost, 4, 3, 4, 3, 4},

49769

+ {"i486", &i486_cost, 16, 15, 16, 15, 16},

49770

+ {"pentium", &pentium_cost, 16, 7, 16, 7, 16},

49771

+ {"pentiumpro", &pentiumpro_cost, 16, 15, 16, 10, 16},

49772

+ {"pentium4", &pentium4_cost, 0, 0, 0, 0, 0},

49773

+ {"nocona", &nocona_cost, 0, 0, 0, 0, 0},

49774

+ {"core2", &core_cost, 16, 10, 16, 10, 16},

49775

+ {"corei7", &core_cost, 16, 10, 16, 10, 16},

49776

+ {"core-avx2", &core_cost, 16, 10, 16, 10, 16},

49777

+ {"atom", &atom_cost, 16, 15, 16, 7, 16},

49778

+ {"geode", &geode_cost, 0, 0, 0, 0, 0},

49779

+ {"k6", &k6_cost, 32, 7, 32, 7, 32},

49780

+ {"athlon", &athlon_cost, 16, 7, 16, 7, 16},

49781

+ {"k8", &k8_cost, 16, 7, 16, 7, 16},

49782

+ {"amdfam10", &amdfam10_cost, 32, 24, 32, 7, 32},

49783

+ {"bdver1", &bdver1_cost, 16, 10, 16, 7, 11},

49784

+ {"bdver2", &bdver2_cost, 16, 10, 16, 7, 11},

49785

+ {"bdver3", &bdver3_cost, 16, 10, 16, 7, 11},

49786

+ {"btver1", &btver1_cost, 16, 10, 16, 7, 11},

49787

+ {"btver2", &btver2_cost, 16, 10, 16, 7, 11}

49788

};

49789

-

49790

-static const char *const cpu_names[TARGET_CPU_DEFAULT_max] =

49791

-{

49792

- "generic",

49793

- "i386",

49794

- "i486",

49795

- "pentium",

49796

- "pentium-mmx",

49797

- "pentiumpro",

49798

- "pentium2",

49799

- "pentium3",

49800

- "pentium4",

49801

- "pentium-m",

49802

- "prescott",

49803

- "nocona",

49804

- "core2",

49805

- "corei7",

49806

- "core-avx2",

49807

- "atom",

49808

- "geode",

49809

- "k6",

49810

- "k6-2",

49811

- "k6-3",

49812

- "athlon",

49813

- "athlon-4",

49814

- "k8",

49815

- "amdfam10",

49816

- "bdver1",

49817

- "bdver2",

49818

- "bdver3",

49819

- "btver1",

49820

- "btver2"

49821

-};

49822

49823

static bool

49824

gate_insert_vzeroupper (void)

49825

@@ -2983,7 +2949,7 @@

49826

{"bdver3", PROCESSOR_BDVER3, CPU_BDVER3,

49827

PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3

49828

49829

- | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX

49830

49831

49832

| PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE

49833

| PTA_XSAVEOPT},

49834

@@ -3125,7 +3091,8 @@

49835

ix86_tune_string = ix86_arch_string;

49836

if (!ix86_tune_string)

49837

{

49838

- ix86_tune_string = cpu_names[TARGET_CPU_DEFAULT];

49839

+ ix86_tune_string

49840

+ = processor_target_table[TARGET_CPU_DEFAULT].name;

49841

ix86_tune_defaulted = 1;

49842

}

49843

49844

@@ -4078,19 +4045,15 @@

49845

= ix86_target_string (ptr->x_ix86_isa_flags, ptr->x_target_flags,

49846

NULL, NULL, ptr->x_ix86_fpmath, false);

49847

49848

+ gcc_assert (ptr->arch < PROCESSOR_max);

49849

fprintf (file, "%*sarch = %d (%s)\n",

49850

indent, "",

49851

- ptr->arch,

49852

- ((ptr->arch < TARGET_CPU_DEFAULT_max)

49853

- ? cpu_names[ptr->arch]

49854

- : "<unknown>"));

49855

+ ptr->arch, processor_target_table[ptr->arch].name);

49856

49857

+ gcc_assert (ptr->tune < PROCESSOR_max);

49858

fprintf (file, "%*stune = %d (%s)\n",

49859

indent, "",

49860

- ptr->tune,

49861

- ((ptr->tune < TARGET_CPU_DEFAULT_max)

49862

- ? cpu_names[ptr->tune]

49863

- : "<unknown>"));

49864

+ ptr->tune, processor_target_table[ptr->tune].name);

49865

49866

fprintf (file, "%*sbranch_cost = %d\n", indent, "", ptr->branch_cost);

49867

49868

@@ -5213,7 +5176,12 @@

49869

/* Use register calling convention for local functions when possible. */

49870

if (decl

49871

&& TREE_CODE (decl) == FUNCTION_DECL

49872

- && optimize

49873

+ /* Caller and callee must agree on the calling convention, so

49874

+ checking here just optimize means that with

49875

+ __attribute__((optimize (...))) caller could use regparm convention

49876

+ and callee not, or vice versa. Instead look at whether the callee

49877

+ is optimized or not. */

49878

+ && opt_for_fn (decl, optimize)

49879

&& !(profile_flag && !flag_fentry))

49880

{

49881

/* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */

49882

@@ -5409,6 +5377,17 @@

49883

bool win;

49884

int j;

49885

49886

+ /* For pre-AVX disallow unaligned loads/stores where the

49887

+ instructions don't support it. */

49888

+ if (!TARGET_AVX

49889

+ && VECTOR_MODE_P (GET_MODE (op))

49890

+ && misaligned_operand (op, GET_MODE (op)))

49891

+ {

49892

+ int min_align = get_attr_ssememalign (insn);

49893

+ if (min_align == 0)

49894

+ return false;

49895

+ }

49896

+

49897

/* A unary operator may be accepted by the predicate, but it

49898

is irrelevant for matching constraints. */

49899

if (UNARY_P (op))

49900

@@ -5747,9 +5726,9 @@

49901

cum->nregs = 0;

49902

cum->sse_nregs = 0;

49903

cum->mmx_nregs = 0;

49904

- cum->warn_avx = 0;

49905

- cum->warn_sse = 0;

49906

- cum->warn_mmx = 0;

49907

+ cum->warn_avx = false;

49908

+ cum->warn_sse = false;

49909

+ cum->warn_mmx = false;

49910

return;

49911

}

49912

49913

@@ -5790,10 +5769,14 @@

49914

49915

The midde-end can't deal with the vector types > 16 bytes. In this

49916

case, we return the original mode and warn ABI change if CUM isn't

49917

- NULL. */

49918

+ NULL.

49919

49920

+ If INT_RETURN is true, warn ABI change if the vector mode isn't

49921

+ available for function return value. */

49922

+

49923

static enum machine_mode

49924

-type_natural_mode (const_tree type, const CUMULATIVE_ARGS *cum)

49925

+type_natural_mode (const_tree type, const CUMULATIVE_ARGS *cum,

49926

+ bool in_return)

49927

{

49928

enum machine_mode mode = TYPE_MODE (type);

49929

49930

@@ -5819,33 +5802,61 @@

49931

if (size == 32 && !TARGET_AVX)

49932

{

49933

static bool warnedavx;

49934

+ static bool warnedavx_ret;

49935

49936

- if (cum

49937

- && !warnedavx

49938

- && cum->warn_avx)

49939

+ if (cum && cum->warn_avx && !warnedavx)

49940

{

49941

- warnedavx = true;

49942

- warning (0, "AVX vector argument without AVX "

49943

- "enabled changes the ABI");

49944

+ if (warning (OPT_Wpsabi, "AVX vector argument "

49945

+ "without AVX enabled changes the ABI"))

49946

+ warnedavx = true;

49947

}

49948

+ else if (in_return && !warnedavx_ret)

49949

+ {

49950

+ if (warning (OPT_Wpsabi, "AVX vector return "

49951

+ "without AVX enabled changes the ABI"))

49952

+ warnedavx_ret = true;

49953

+ }

49954

+

49955

return TYPE_MODE (type);

49956

}

49957

- else if ((size == 8 || size == 16) && !TARGET_SSE)

49958

+ else if (((size == 8 && TARGET_64BIT) || size == 16)

49959

+ && !TARGET_SSE)

49960

{

49961

static bool warnedsse;

49962

+ static bool warnedsse_ret;

49963

49964

- if (cum

49965

- && !warnedsse

49966

- && cum->warn_sse)

49967

+ if (cum && cum->warn_sse && !warnedsse)

49968

{

49969

- warnedsse = true;

49970

- warning (0, "SSE vector argument without SSE "

49971

- "enabled changes the ABI");

49972

+ if (warning (OPT_Wpsabi, "SSE vector argument "

49973

+ "without SSE enabled changes the ABI"))

49974

+ warnedsse = true;

49975

}

49976

- return mode;

49977

+ else if (!TARGET_64BIT && in_return && !warnedsse_ret)

49978

+ {

49979

+ if (warning (OPT_Wpsabi, "SSE vector return "

49980

+ "without SSE enabled changes the ABI"))

49981

+ warnedsse_ret = true;

49982

+ }

49983

}

49984

- else

49985

- return mode;

49986

+ else if ((size == 8 && !TARGET_64BIT) && !TARGET_MMX)

49987

+ {

49988

+ static bool warnedmmx;

49989

+ static bool warnedmmx_ret;

49990

+

49991

+ if (cum && cum->warn_mmx && !warnedmmx)

49992

+ {

49993

+ if (warning (OPT_Wpsabi, "MMX vector argument "

49994

+ "without MMX enabled changes the ABI"))

49995

+ warnedmmx = true;

49996

+ }

49997

+ else if (in_return && !warnedmmx_ret)

49998

+ {

49999

+ if (warning (OPT_Wpsabi, "MMX vector return "

50000

+ "without MMX enabled changes the ABI"))

50001

+ warnedmmx_ret = true;

50002

+ }

50003

+ }

50004

+ return mode;

50005

}

50006

50007

gcc_unreachable ();

50008

@@ -6190,25 +6201,28 @@

50009

case CHImode:

50010

case CQImode:

50011

{

50012

- int size = (bit_offset % 64)+ (int) GET_MODE_BITSIZE (mode);

50013

+ int size = bit_offset + (int) GET_MODE_BITSIZE (mode);

50014

50015

- if (size <= 32)

50016

+ /* Analyze last 128 bits only. */

50017

+ size = (size - 1) & 0x7f;

50018

+

50019

+ if (size < 32)

50020

{

50021

classes[0] = X86_64_INTEGERSI_CLASS;

50022

return 1;

50023

}

50024

- else if (size <= 64)

50025

+ else if (size < 64)

50026

{

50027

classes[0] = X86_64_INTEGER_CLASS;

50028

return 1;

50029

}

50030

- else if (size <= 64+32)

50031

+ else if (size < 64+32)

50032

{

50033

classes[0] = X86_64_INTEGER_CLASS;

50034

classes[1] = X86_64_INTEGERSI_CLASS;

50035

return 2;

50036

}

50037

- else if (size <= 64+64)

50038

+ else if (size < 64+64)

50039

{

50040

classes[0] = classes[1] = X86_64_INTEGER_CLASS;

50041

return 2;

50042

@@ -6475,7 +6489,7 @@

50043

if (n == 2

50044

&& regclass[0] == X86_64_INTEGER_CLASS

50045

&& regclass[1] == X86_64_INTEGER_CLASS

50046

- && (mode == CDImode || mode == TImode || mode == TFmode)

50047

+ && (mode == CDImode || mode == TImode)

50048

&& intreg[0] + 1 == intreg[1])

50049

return gen_rtx_REG (mode, intreg[0]);

50050

50051

@@ -6725,7 +6739,7 @@

50052

words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;

50053

50054

if (type)

50055

- mode = type_natural_mode (type, NULL);

50056

+ mode = type_natural_mode (type, NULL, false);

50057

50058

if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI)

50059

function_arg_advance_ms_64 (cum, bytes, words);

50060

@@ -6753,8 +6767,6 @@

50061

enum machine_mode orig_mode, const_tree type,

50062

HOST_WIDE_INT bytes, HOST_WIDE_INT words)

50063

{

50064

- static bool warnedsse, warnedmmx;

50065

-

50066

/* Avoid the AL settings for the Unix64 ABI. */

50067

if (mode == VOIDmode)

50068

return constm1_rtx;

50069

@@ -6811,12 +6823,6 @@

50070

case V2DFmode:

50071

if (!type || !AGGREGATE_TYPE_P (type))

50072

{

50073

- if (!TARGET_SSE && !warnedsse && cum->warn_sse)

50074

- {

50075

- warnedsse = true;

50076

- warning (0, "SSE vector argument without SSE enabled "

50077

- "changes the ABI");

50078

- }

50079

if (cum->sse_nregs)

50080

return gen_reg_or_parallel (mode, orig_mode,

50081

cum->sse_regno + FIRST_SSE_REG);

50082

@@ -6849,12 +6855,6 @@

50083

case V1DImode:

50084

if (!type || !AGGREGATE_TYPE_P (type))

50085

{

50086

- if (!TARGET_MMX && !warnedmmx && cum->warn_mmx)

50087

- {

50088

- warnedmmx = true;

50089

- warning (0, "MMX vector argument without MMX enabled "

50090

- "changes the ABI");

50091

- }

50092

if (cum->mmx_nregs)

50093

return gen_reg_or_parallel (mode, orig_mode,

50094

cum->mmx_regno + FIRST_MMX_REG);

50095

@@ -6977,7 +6977,7 @@

50096

/* To simplify the code below, represent vector types with a vector mode

50097

even if MMX/SSE are not active. */

50098

if (type && TREE_CODE (type) == VECTOR_TYPE)

50099

- mode = type_natural_mode (type, cum);

50100

+ mode = type_natural_mode (type, cum, false);

50101

50102

if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI)

50103

arg = function_arg_ms_64 (cum, mode, omode, named, bytes);

50104

@@ -7235,9 +7235,15 @@

50105

switch (regno)

50106

{

50107

case AX_REG:

50108

+ case DX_REG:

50109

return true;

50110

+ case DI_REG:

50111

+ case SI_REG:

50112

+ return TARGET_64BIT && ix86_abi != MS_ABI;

50113

50114

- case FIRST_FLOAT_REG:

50115

+ /* Complex values are returned in %st(0)/%st(1) pair. */

50116

+ case ST0_REG:

50117

+ case ST1_REG:

50118

/* TODO: The function should depend on current function ABI but

50119

builtins.c would need updating then. Therefore we use the

50120

default ABI. */

50121

@@ -7245,10 +7251,12 @@

50122

return false;

50123

return TARGET_FLOAT_RETURNS_IN_80387;

50124

50125

- case FIRST_SSE_REG:

50126

+ /* Complex values are returned in %xmm0/%xmm1 pair. */

50127

+ case XMM0_REG:

50128

+ case XMM1_REG:

50129

return TARGET_SSE;

50130

50131

- case FIRST_MMX_REG:

50132

+ case MM0_REG:

50133

if (TARGET_MACHO || TARGET_64BIT)

50134

return false;

50135

return TARGET_MMX;

50136

@@ -7420,7 +7428,7 @@

50137

enum machine_mode mode, orig_mode;

50138

50139

orig_mode = TYPE_MODE (valtype);

50140

- mode = type_natural_mode (valtype, NULL);

50141

+ mode = type_natural_mode (valtype, NULL, true);

50142

return ix86_function_value_1 (valtype, fntype_or_decl, orig_mode, mode);

50143

}

50144

50145

@@ -7535,7 +7543,7 @@

50146

#ifdef SUBTARGET_RETURN_IN_MEMORY

50147

return SUBTARGET_RETURN_IN_MEMORY (type, fntype);

50148

#else

50149

- const enum machine_mode mode = type_natural_mode (type, NULL);

50150

+ const enum machine_mode mode = type_natural_mode (type, NULL, true);

50151

50152

if (TARGET_64BIT)

50153

{

50154

@@ -7549,52 +7557,6 @@

50155

#endif

50156

}

50157

50158

-/* When returning SSE vector types, we have a choice of either

50159

- (1) being abi incompatible with a -march switch, or

50160

- (2) generating an error.

50161

- Given no good solution, I think the safest thing is one warning.

50162

- The user won't be able to use -Werror, but....

50163

-

50164

- Choose the STRUCT_VALUE_RTX hook because that's (at present) only

50165

- called in response to actually generating a caller or callee that

50166

- uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called

50167

- via aggregate_value_p for general type probing from tree-ssa. */

50168

-

50169

-static rtx

50170

-ix86_struct_value_rtx (tree type, int incoming ATTRIBUTE_UNUSED)

50171

-{

50172

- static bool warnedsse, warnedmmx;

50173

-

50174

- if (!TARGET_64BIT && type)

50175

- {

50176

- /* Look at the return type of the function, not the function type. */

50177

- enum machine_mode mode = TYPE_MODE (TREE_TYPE (type));

50178

-

50179

- if (!TARGET_SSE && !warnedsse)

50180

- {

50181

- if (mode == TImode

50182

- || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))

50183

- {

50184

- warnedsse = true;

50185

- warning (0, "SSE vector return without SSE enabled "

50186

- "changes the ABI");

50187

- }

50188

- }

50189

-

50190

- if (!TARGET_MMX && !warnedmmx)

50191

- {

50192

- if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)

50193

- {

50194

- warnedmmx = true;

50195

- warning (0, "MMX vector return without MMX enabled "

50196

- "changes the ABI");

50197

- }

50198

- }

50199

- }

50200

-

50201

- return NULL;

50202

-}

50203

-

50204

50205

/* Create the va_list data type. */

50206

50207

@@ -8019,7 +7981,7 @@

50208

size = int_size_in_bytes (type);

50209

rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;

50210

50211

- nat_mode = type_natural_mode (type, NULL);

50212

+ nat_mode = type_natural_mode (type, NULL, false);

50213

switch (nat_mode)

50214

{

50215

case V8SFmode:

50216

@@ -10560,18 +10522,20 @@

50217

}

50218

m->fs.sp_offset += allocate;

50219

50220

+ /* Use stack_pointer_rtx for relative addressing so that code

50221

+ works for realigned stack, too. */

50222

if (r10_live && eax_live)

50223

{

50224

- t = choose_baseaddr (m->fs.sp_offset - allocate);

50225

+ t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, eax);

50226

emit_move_insn (gen_rtx_REG (word_mode, R10_REG),

50227

gen_frame_mem (word_mode, t));

50228

- t = choose_baseaddr (m->fs.sp_offset - allocate - UNITS_PER_WORD);

50229

+ t = plus_constant (Pmode, t, UNITS_PER_WORD);

50230

emit_move_insn (gen_rtx_REG (word_mode, AX_REG),

50231

gen_frame_mem (word_mode, t));

50232

}

50233

else if (eax_live || r10_live)

50234

{

50235

- t = choose_baseaddr (m->fs.sp_offset - allocate);

50236

+ t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, eax);

50237

emit_move_insn (gen_rtx_REG (word_mode,

50238

(eax_live ? AX_REG : R10_REG)),

50239

gen_frame_mem (word_mode, t));

50240

@@ -11164,8 +11128,9 @@

50241

m->fs.cfa_offset -= UNITS_PER_WORD;

50242

m->fs.sp_offset -= UNITS_PER_WORD;

50243

50244

- add_reg_note (insn, REG_CFA_ADJUST_CFA,

50245

- copy_rtx (XVECEXP (PATTERN (insn), 0, 1)));

50246

+ rtx x = plus_constant (Pmode, stack_pointer_rtx, UNITS_PER_WORD);

50247

+ x = gen_rtx_SET (VOIDmode, stack_pointer_rtx, x);

50248

+ add_reg_note (insn, REG_CFA_ADJUST_CFA, x);

50249

add_reg_note (insn, REG_CFA_REGISTER,

50250

gen_rtx_SET (VOIDmode, ecx, pc_rtx));

50251

RTX_FRAME_RELATED_P (insn) = 1;

50252

@@ -11561,30 +11526,6 @@

50253

}

50254

}

50255

50256

-/* Determine if op is suitable SUBREG RTX for address. */

50257

-

50258

-static bool

50259

-ix86_address_subreg_operand (rtx op)

50260

-{

50261

- enum machine_mode mode;

50262

-

50263

- if (!REG_P (op))

50264

- return false;

50265

-

50266

- mode = GET_MODE (op);

50267

-

50268

- if (GET_MODE_CLASS (mode) != MODE_INT)

50269

- return false;

50270

-

50271

- /* Don't allow SUBREGs that span more than a word. It can lead to spill

50272

- failures when the register is one word out of a two word structure. */

50273

- if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)

50274

- return false;

50275

-

50276

- /* Allow only SUBREGs of non-eliminable hard registers. */

50277

- return register_no_elim_operand (op, mode);

50278

-}

50279

-

50280

/* Extract the parts of an RTL expression that is a valid memory address

50281

for an instruction. Return 0 if the structure of the address is

50282

grossly off. Return -1 if the address contains ASHIFT, so it is not

50283

@@ -11641,7 +11582,7 @@

50284

base = addr;

50285

else if (GET_CODE (addr) == SUBREG)

50286

{

50287

- if (ix86_address_subreg_operand (SUBREG_REG (addr)))

50288

+ if (REG_P (SUBREG_REG (addr)))

50289

base = addr;

50290

else

50291

return 0;

50292

@@ -11705,7 +11646,7 @@

50293

break;

50294

50295

case SUBREG:

50296

- if (!ix86_address_subreg_operand (SUBREG_REG (op)))

50297

+ if (!REG_P (SUBREG_REG (op)))

50298

return 0;

50299

/* FALLTHRU */

50300

50301

@@ -11750,19 +11691,6 @@

50302

scale = 1 << scale;

50303

retval = -1;

50304

}

50305

- else if (CONST_INT_P (addr))

50306

- {

50307

- if (!x86_64_immediate_operand (addr, VOIDmode))

50308

- return 0;

50309

-

50310

- /* Constant addresses are sign extended to 64bit, we have to

50311

- prevent addresses from 0x80000000 to 0xffffffff in x32 mode. */

50312

- if (TARGET_X32

50313

- && val_signbit_known_set_p (SImode, INTVAL (addr)))

50314

- return 0;

50315

-

50316

- disp = addr;

50317

- }

50318

else

50319

disp = addr; /* displacement */

50320

50321

@@ -11771,18 +11699,12 @@

50322

if (REG_P (index))

50323

;

50324

else if (GET_CODE (index) == SUBREG

50325

- && ix86_address_subreg_operand (SUBREG_REG (index)))

50326

+ && REG_P (SUBREG_REG (index)))

50327

;

50328

else

50329

return 0;

50330

}

50331

50332

-/* Address override works only on the (%reg) part of %fs:(%reg). */

50333

- if (seg != SEG_DEFAULT

50334

- && ((base && GET_MODE (base) != word_mode)

50335

- || (index && GET_MODE (index) != word_mode)))

50336

- return 0;

50337

-

50338

/* Extract the integral value of scale. */

50339

if (scale_rtx)

50340

{

50341

@@ -12258,6 +12180,45 @@

50342

return false;

50343

}

50344

50345

+/* Determine if op is suitable RTX for an address register.

50346

+ Return naked register if a register or a register subreg is

50347

+ found, otherwise return NULL_RTX. */

50348

+

50349

+static rtx

50350

+ix86_validate_address_register (rtx op)

50351

+{

50352

+ enum machine_mode mode = GET_MODE (op);

50353

+

50354

+ /* Only SImode or DImode registers can form the address. */

50355

+ if (mode != SImode && mode != DImode)

50356

+ return NULL_RTX;

50357

+

50358

+ if (REG_P (op))

50359

+ return op;

50360

+ else if (GET_CODE (op) == SUBREG)

50361

+ {

50362

+ rtx reg = SUBREG_REG (op);

50363

+

50364

+ if (!REG_P (reg))

50365

+ return NULL_RTX;

50366

+

50367

+ mode = GET_MODE (reg);

50368

+

50369

+ /* Don't allow SUBREGs that span more than a word. It can

50370

+ lead to spill failures when the register is one word out

50371

+ of a two word structure. */

50372

+ if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)

50373

+ return NULL_RTX;

50374

+

50375

+ /* Allow only SUBREGs of non-eliminable hard registers. */

50376

+ if (register_no_elim_operand (reg, mode))

50377

+ return reg;

50378

+ }

50379

+

50380

+ /* Op is not a register. */

50381

+ return NULL_RTX;

50382

+}

50383

+

50384

/* Recognizes RTL expressions that are valid memory addresses for an

50385

instruction. The MODE argument is the machine mode for the MEM

50386

expression that wants to use this address.

50387

@@ -12273,6 +12234,7 @@

50388

struct ix86_address parts;

50389

rtx base, index, disp;

50390

HOST_WIDE_INT scale;

50391

+ enum ix86_address_seg seg;

50392

50393

if (ix86_decompose_address (addr, &parts) <= 0)

50394

/* Decomposition failed. */

50395

@@ -12282,23 +12244,16 @@

50396

index = parts.index;

50397

disp = parts.disp;

50398

scale = parts.scale;

50399

+ seg = parts.seg;

50400

50401

/* Validate base register. */

50402

if (base)

50403

{

50404

- rtx reg;

50405

+ rtx reg = ix86_validate_address_register (base);

50406

50407

- if (REG_P (base))

50408

- reg = base;

50409

- else if (GET_CODE (base) == SUBREG && REG_P (SUBREG_REG (base)))

50410

- reg = SUBREG_REG (base);

50411

- else

50412

- /* Base is not a register. */

50413

+ if (reg == NULL_RTX)

50414

return false;

50415

50416

- if (GET_MODE (base) != SImode && GET_MODE (base) != DImode)

50417

- return false;

50418

-

50419

if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg))

50420

|| (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (reg)))

50421

/* Base is not valid. */

50422

@@ -12308,19 +12263,11 @@

50423

/* Validate index register. */

50424

if (index)

50425

{

50426

- rtx reg;

50427

+ rtx reg = ix86_validate_address_register (index);

50428

50429

- if (REG_P (index))

50430

- reg = index;

50431

- else if (GET_CODE (index) == SUBREG && REG_P (SUBREG_REG (index)))

50432

- reg = SUBREG_REG (index);

50433

- else

50434

- /* Index is not a register. */

50435

+ if (reg == NULL_RTX)

50436

return false;

50437

50438

- if (GET_MODE (index) != SImode && GET_MODE (index) != DImode)

50439

- return false;

50440

-

50441

if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (reg))

50442

|| (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (reg)))

50443

/* Index is not valid. */

50444

@@ -12332,6 +12279,12 @@

50445

&& GET_MODE (base) != GET_MODE (index))

50446

return false;

50447

50448

+ /* Address override works only on the (%reg) part of %fs:(%reg). */

50449

+ if (seg != SEG_DEFAULT

50450

+ && ((base && GET_MODE (base) != word_mode)

50451

+ || (index && GET_MODE (index) != word_mode)))

50452

+ return false;

50453

+

50454

/* Validate scale factor. */

50455

if (scale != 1)

50456

{

50457

@@ -12453,6 +12406,12 @@

50458

&& !x86_64_immediate_operand (disp, VOIDmode))

50459

/* Displacement is out of range. */

50460

return false;

50461

+ /* In x32 mode, constant addresses are sign extended to 64bit, so

50462

+ we have to prevent addresses from 0x80000000 to 0xffffffff. */

50463

+ else if (TARGET_X32 && !(index || base)

50464

+ && CONST_INT_P (disp)

50465

+ && val_signbit_known_set_p (SImode, INTVAL (disp)))

50466

+ return false;

50467

}

50468

50469

/* Everything looks valid. */

50470

@@ -13817,8 +13776,6 @@

50471

Those same assemblers have the same but opposite lossage on cmov. */

50472

if (mode == CCmode)

50473

suffix = fp ? "nbe" : "a";

50474

- else if (mode == CCCmode)

50475

- suffix = "b";

50476

else

50477

gcc_unreachable ();

50478

break;

50479

@@ -13840,8 +13797,12 @@

50480

}

50481

break;

50482

case LTU:

50483

- gcc_assert (mode == CCmode || mode == CCCmode);

50484

- suffix = "b";

50485

+ if (mode == CCmode)

50486

+ suffix = "b";

50487

+ else if (mode == CCCmode)

50488

+ suffix = "c";

50489

+ else

50490

+ gcc_unreachable ();

50491

break;

50492

case GE:

50493

switch (mode)

50494

@@ -13861,9 +13822,12 @@

50495

}

50496

break;

50497

case GEU:

50498

- /* ??? As above. */

50499

- gcc_assert (mode == CCmode || mode == CCCmode);

50500

- suffix = fp ? "nb" : "ae";

50501

+ if (mode == CCmode)

50502

+ suffix = fp ? "nb" : "ae";

50503

+ else if (mode == CCCmode)

50504

+ suffix = "nc";

50505

+ else

50506

+ gcc_unreachable ();

50507

break;

50508

case LE:

50509

gcc_assert (mode == CCmode || mode == CCGCmode || mode == CCNOmode);

50510

@@ -13870,11 +13834,8 @@

50511

suffix = "le";

50512

break;

50513

case LEU:

50514

- /* ??? As above. */

50515

if (mode == CCmode)

50516

suffix = "be";

50517

- else if (mode == CCCmode)

50518

- suffix = fp ? "nb" : "ae";

50519

else

50520

gcc_unreachable ();

50521

break;

50522

@@ -15340,7 +15301,7 @@

50523

rtx arg = XEXP (XEXP (link, 0), 0);

50524

50525

if (ix86_check_avx256_register (&arg, NULL))

50526

- return AVX_U128_ANY;

50527

+ return AVX_U128_DIRTY;

50528

}

50529

}

50530

50531

@@ -15460,8 +15421,8 @@

50532

{

50533

bool avx_reg256_found = false;

50534

note_stores (pat, ix86_check_avx256_stores, &avx_reg256_found);

50535

- if (!avx_reg256_found)

50536

- return AVX_U128_CLEAN;

50537

+

50538

+ return avx_reg256_found ? AVX_U128_DIRTY : AVX_U128_CLEAN;

50539

}

50540

50541

/* Otherwise, return current mode. Remember that if insn

50542

@@ -17350,10 +17311,20 @@

50543

if (!TARGET_OPT_AGU || optimize_function_for_size_p (cfun))

50544

return false;

50545

50546

- /* Check it is correct to split here. */

50547

- if (!ix86_ok_to_clobber_flags(insn))

50548

+ /* The "at least two components" test below might not catch simple

50549

+ move or zero extension insns if parts.base is non-NULL and parts.disp

50550

+ is const0_rtx as the only components in the address, e.g. if the

50551

+ register is %rbp or %r13. As this test is much cheaper and moves or

50552

+ zero extensions are the common case, do this check first. */

50553

+ if (REG_P (operands[1])

50554

+ || (SImode_address_operand (operands[1], VOIDmode)

50555

+ && REG_P (XEXP (operands[1], 0))))

50556

return false;

50557

50558

+ /* Check if it is OK to split here. */

50559

+ if (!ix86_ok_to_clobber_flags (insn))

50560

+ return false;

50561

+

50562

ok = ix86_decompose_address (operands[1], &parts);

50563

gcc_assert (ok);

50564

50565

@@ -18486,12 +18457,7 @@

50566

return CCmode;

50567

case GTU: /* CF=0 & ZF=0 */

50568

case LEU: /* CF=1 | ZF=1 */

50569

- /* Detect overflow checks. They need just the carry flag. */

50570

- if (GET_CODE (op0) == MINUS

50571

- && rtx_equal_p (op1, XEXP (op0, 0)))

50572

- return CCCmode;

50573

- else

50574

- return CCmode;

50575

+ return CCmode;

50576

/* Codes possibly doable only with sign flag when

50577

comparing against zero. */

50578

case GE: /* SF=OF or SF=0 */

50579

@@ -20500,7 +20466,7 @@

50580

return;

50581

50582

case V8SFmode:

50583

- mask = gen_lowpart (V8SFmode, mask);

50584

+ mask = gen_lowpart (V8SImode, mask);

50585

if (one_operand_shuffle)

50586

emit_insn (gen_avx2_permvarv8sf (target, op0, mask));

50587

else

50588

@@ -21740,6 +21706,21 @@

50589

return SImode;

50590

}

50591

50592

+/* Copy the address to a Pmode register. This is used for x32 to

50593

+ truncate DImode TLS address to a SImode register. */

50594

+

50595

+static rtx

50596

+ix86_copy_addr_to_reg (rtx addr)

50597

+{

50598

+ if (GET_MODE (addr) == Pmode || GET_MODE (addr) == VOIDmode)

50599

+ return copy_addr_to_reg (addr);

50600

+ else

50601

+ {

50602

+ gcc_assert (GET_MODE (addr) == DImode && Pmode == SImode);

50603

+ return gen_rtx_SUBREG (SImode, copy_to_mode_reg (DImode, addr), 0);

50604

+ }

50605

+}

50606

+

50607

/* When SRCPTR is non-NULL, output simple loop to move memory

50608

pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,

50609

overall size is COUNT specified in bytes. When SRCPTR is NULL, output the

50610

@@ -22728,8 +22709,8 @@

50611

gcc_assert (alg != no_stringop);

50612

if (!count)

50613

count_exp = copy_to_mode_reg (GET_MODE (count_exp), count_exp);

50614

- destreg = copy_addr_to_reg (XEXP (dst, 0));

50615

- srcreg = copy_addr_to_reg (XEXP (src, 0));

50616

+ destreg = ix86_copy_addr_to_reg (XEXP (dst, 0));

50617

+ srcreg = ix86_copy_addr_to_reg (XEXP (src, 0));

50618

switch (alg)

50619

{

50620

case libcall:

50621

@@ -23119,7 +23100,7 @@

50622

gcc_assert (alg != no_stringop);

50623

if (!count)

50624

count_exp = copy_to_mode_reg (counter_mode (count_exp), count_exp);

50625

- destreg = copy_addr_to_reg (XEXP (dst, 0));

50626

+ destreg = ix86_copy_addr_to_reg (XEXP (dst, 0));

50627

switch (alg)

50628

{

50629

case libcall:

50630

@@ -24988,7 +24969,8 @@

50631

int

50632

ix86_data_alignment (tree type, int align)

50633

{

50634

- int max_align = optimize_size ? BITS_PER_WORD : MIN (256, MAX_OFILE_ALIGNMENT);

50635

+ int max_align

50636

+ = optimize_size ? BITS_PER_WORD : MIN (256, MAX_OFILE_ALIGNMENT);

50637

50638

if (AGGREGATE_TYPE_P (type)

50639

&& TYPE_SIZE (type)

50640

@@ -27984,8 +27966,8 @@

50641

{ OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },

50642

{ OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },

50643

50644

- { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_2_SF },

50645

- { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_2_DF },

50646

+ { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_1_SF },

50647

+ { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_1_DF },

50648

{ OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },

50649

{ OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },

50650

{ OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },

50651

@@ -31245,11 +31227,12 @@

50652

50653

static rtx

50654

ix86_expand_special_args_builtin (const struct builtin_description *d,

50655

- tree exp, rtx target)

50656

+ tree exp, rtx target)

50657

{

50658

tree arg;

50659

rtx pat, op;

50660

unsigned int i, nargs, arg_adjust, memory;

50661

+ bool aligned_mem = false;

50662

struct

50663

{

50664

rtx op;

50665

@@ -31295,6 +31278,15 @@

50666

nargs = 1;

50667

klass = load;

50668

memory = 0;

50669

+ switch (icode)

50670

+ {

50671

+ case CODE_FOR_sse4_1_movntdqa:

50672

+ case CODE_FOR_avx2_movntdqa:

50673

+ aligned_mem = true;

50674

+ break;

50675

+ default:

50676

+ break;

50677

+ }

50678

break;

50679

case VOID_FTYPE_PV2SF_V4SF:

50680

case VOID_FTYPE_PV4DI_V4DI:

50681

@@ -31312,6 +31304,26 @@

50682

klass = store;

50683

/* Reserve memory operand for target. */

50684

memory = ARRAY_SIZE (args);

50685

+ switch (icode)

50686

+ {

50687

+ /* These builtins and instructions require the memory

50688

+ to be properly aligned. */

50689

+ case CODE_FOR_avx_movntv4di:

50690

+ case CODE_FOR_sse2_movntv2di:

50691

+ case CODE_FOR_avx_movntv8sf:

50692

+ case CODE_FOR_sse_movntv4sf:

50693

+ case CODE_FOR_sse4a_vmmovntv4sf:

50694

+ case CODE_FOR_avx_movntv4df:

50695

+ case CODE_FOR_sse2_movntv2df:

50696

+ case CODE_FOR_sse4a_vmmovntv2df:

50697

+ case CODE_FOR_sse2_movntidi:

50698

+ case CODE_FOR_sse_movntq:

50699

+ case CODE_FOR_sse2_movntisi:

50700

+ aligned_mem = true;

50701

+ break;

50702

+ default:

50703

+ break;

50704

+ }

50705

break;

50706

case V4SF_FTYPE_V4SF_PCV2SF:

50707

case V2DF_FTYPE_V2DF_PCDOUBLE:

50708

@@ -31368,6 +31380,17 @@

50709

{

50710

op = force_reg (Pmode, convert_to_mode (Pmode, op, 1));

50711

target = gen_rtx_MEM (tmode, op);

50712

+ /* target at this point has just BITS_PER_UNIT MEM_ALIGN

50713

+ on it. Try to improve it using get_pointer_alignment,

50714

+ and if the special builtin is one that requires strict

50715

+ mode alignment, also from it's GET_MODE_ALIGNMENT.

50716

+ Failure to do so could lead to ix86_legitimate_combined_insn

50717

+ rejecting all changes to such insns. */

50718

+ unsigned int align = get_pointer_alignment (arg);

50719

+ if (aligned_mem && align < GET_MODE_ALIGNMENT (tmode))

50720

+ align = GET_MODE_ALIGNMENT (tmode);

50721

+ if (MEM_ALIGN (target) < align)

50722

+ set_mem_align (target, align);

50723

}

50724

else

50725

target = force_reg (tmode, op);

50726

@@ -31413,8 +31436,17 @@

50727

/* This must be the memory operand. */

50728

op = force_reg (Pmode, convert_to_mode (Pmode, op, 1));

50729

op = gen_rtx_MEM (mode, op);

50730

- gcc_assert (GET_MODE (op) == mode

50731

- || GET_MODE (op) == VOIDmode);

50732

+ /* op at this point has just BITS_PER_UNIT MEM_ALIGN

50733

+ on it. Try to improve it using get_pointer_alignment,

50734

+ and if the special builtin is one that requires strict

50735

+ mode alignment, also from it's GET_MODE_ALIGNMENT.

50736

+ Failure to do so could lead to ix86_legitimate_combined_insn

50737

+ rejecting all changes to such insns. */

50738

+ unsigned int align = get_pointer_alignment (arg);

50739

+ if (aligned_mem && align < GET_MODE_ALIGNMENT (mode))

50740

+ align = GET_MODE_ALIGNMENT (mode);

50741

+ if (MEM_ALIGN (op) < align)

50742

+ set_mem_align (op, align);

50743

}

50744

else

50745

{

50746

@@ -32027,7 +32059,8 @@

50747

else

50748

op2 = gen_rtx_SUBREG (SImode, op0, 0);

50749

50750

- if (target == 0)

50751

+ if (target == 0

50752

+ || !register_operand (target, SImode))

50753

target = gen_reg_rtx (SImode);

50754

50755

pat = gen_rtx_GEU (VOIDmode, gen_rtx_REG (CCCmode, FLAGS_REG),

50756

@@ -32069,7 +32102,8 @@

50757

const0_rtx);

50758

emit_insn (gen_rtx_SET (VOIDmode, op2, pat));

50759

50760

- if (target == 0)

50761

+ if (target == 0

50762

+ || !register_operand (target, SImode))

50763

target = gen_reg_rtx (SImode);

50764

50765

emit_insn (gen_zero_extendqisi2 (target, op2));

50766

@@ -32208,7 +32242,9 @@

50767

mode4 = insn_data[icode].operand[5].mode;

50768

50769

if (target == NULL_RTX

50770

- || GET_MODE (target) != insn_data[icode].operand[0].mode)

50771

+ || GET_MODE (target) != insn_data[icode].operand[0].mode

50772

+ || !insn_data[icode].operand[0].predicate (target,

50773

+ GET_MODE (target)))

50774

subtarget = gen_reg_rtx (insn_data[icode].operand[0].mode);

50775

else

50776

subtarget = target;

50777

@@ -33879,10 +33915,10 @@

50778

{

50779

/* We implement the move patterns for all vector modes into and

50780

out of SSE registers, even when no operation instructions

50781

- are available. OImode move is available only when AVX is

50782

- enabled. */

50783

- return ((TARGET_AVX && mode == OImode)

50784

- || VALID_AVX256_REG_MODE (mode)

50785

+ are available. OImode and AVX modes are available only when

50786

+ AVX is enabled. */

50787

+ return ((TARGET_AVX

50788

+ && VALID_AVX256_REG_OR_OI_MODE (mode))

50789

|| VALID_SSE_REG_MODE (mode)

50790

|| VALID_SSE2_REG_MODE (mode)

50791

|| VALID_MMX_REG_MODE (mode)

50792

@@ -35020,7 +35056,7 @@

50793

{

50794

tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, fnaddr), UNSPEC_GOTPCREL);

50795

tmp = gen_rtx_CONST (Pmode, tmp);

50796

- fnaddr = gen_rtx_MEM (Pmode, tmp);

50797

+ fnaddr = gen_const_mem (Pmode, tmp);

50798

}

50799

}

50800

else

50801

@@ -35040,8 +35076,9 @@

50802

output_set_got (tmp, NULL_RTX);

50803

50804

fnaddr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, fnaddr), UNSPEC_GOT);

50805

- fnaddr = gen_rtx_PLUS (Pmode, fnaddr, tmp);

50806

- fnaddr = gen_rtx_MEM (Pmode, fnaddr);

50807

+ fnaddr = gen_rtx_CONST (Pmode, fnaddr);

50808

+ fnaddr = gen_rtx_PLUS (Pmode, tmp, fnaddr);

50809

+ fnaddr = gen_const_mem (Pmode, fnaddr);

50810

}

50811

}

50812

50813

@@ -35232,7 +35269,10 @@

50814

The smallest offset in the page INSN can start is the case where START

50815

ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).

50816

We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).

50817

- */

50818

+

50819

+ Don't consider asm goto as jump, while it can contain a jump, it doesn't

50820

+ have to, control transfer to label(s) can be performed through other

50821

+ means, and also we estimate minimum length of all asm stmts as 0. */

50822

for (insn = start; insn; insn = NEXT_INSN (insn))

50823

{

50824

int min_size;

50825

@@ -35260,6 +35300,7 @@

50826

{

50827

start = NEXT_INSN (start);

50828

if ((JUMP_P (start)

50829

+ && asm_noperands (PATTERN (start)) < 0

50830

&& GET_CODE (PATTERN (start)) != ADDR_VEC

50831

&& GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)

50832

|| CALL_P (start))

50833

@@ -35278,6 +35319,7 @@

50834

fprintf (dump_file, "Insn %i estimated to %i bytes\n",

50835

INSN_UID (insn), min_size);

50836

if ((JUMP_P (insn)

50837

+ && asm_noperands (PATTERN (insn)) < 0

50838

&& GET_CODE (PATTERN (insn)) != ADDR_VEC

50839

&& GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)

50840

|| CALL_P (insn))

50841

@@ -35289,6 +35331,7 @@

50842

{

50843

start = NEXT_INSN (start);

50844

if ((JUMP_P (start)

50845

+ && asm_noperands (PATTERN (start)) < 0

50846

&& GET_CODE (PATTERN (start)) != ADDR_VEC

50847

&& GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)

50848

|| CALL_P (start))

50849

@@ -39371,7 +39414,9 @@

50850

else

50851

dfinal.perm[i] = e;

50852

}

50853

- dfinal.op0 = gen_reg_rtx (dfinal.vmode);

50854

+

50855

+ if (!d->testing_p)

50856

+ dfinal.op0 = gen_reg_rtx (dfinal.vmode);

50857

dfinal.op1 = dfinal.op0;

50858

dfinal.one_operand_p = true;

50859

dremap.target = dfinal.op0;

50860

@@ -39806,6 +39851,9 @@

50861

return false;

50862

gcc_assert (!d->one_operand_p);

50863

50864

+ if (d->testing_p)

50865

+ return true;

50866

+

50867

nelt = d->nelt;

50868

eltsz = GET_MODE_SIZE (GET_MODE_INNER (d->vmode));

50869

50870

@@ -40005,6 +40053,8 @@

50871

switch (d->vmode)

50872

{

50873

case V4DFmode:

50874

+ if (d->testing_p)

50875

+ break;

50876

t1 = gen_reg_rtx (V4DFmode);

50877

t2 = gen_reg_rtx (V4DFmode);

50878

50879

@@ -40024,6 +40074,8 @@

50880

{

50881

int mask = odd ? 0xdd : 0x88;

50882

50883

+ if (d->testing_p)

50884

+ break;

50885

t1 = gen_reg_rtx (V8SFmode);

50886

t2 = gen_reg_rtx (V8SFmode);

50887

t3 = gen_reg_rtx (V8SFmode);

50888

@@ -40065,6 +40117,8 @@

50889

return expand_vec_perm_pshufb2 (d);

50890

else

50891

{

50892

+ if (d->testing_p)

50893

+ break;

50894

/* We need 2*log2(N)-1 operations to achieve odd/even

50895

with interleave. */

50896

t1 = gen_reg_rtx (V8HImode);

50897

@@ -40086,6 +40140,8 @@

50898

return expand_vec_perm_pshufb2 (d);

50899

else

50900

{

50901

+ if (d->testing_p)

50902

+ break;

50903

t1 = gen_reg_rtx (V16QImode);

50904

t2 = gen_reg_rtx (V16QImode);

50905

t3 = gen_reg_rtx (V16QImode);

50906

@@ -40118,6 +40174,9 @@

50907

return expand_vec_perm_even_odd_1 (&d_copy, odd);

50908

}

50909

50910

+ if (d->testing_p)

50911

+ break;

50912

+

50913

t1 = gen_reg_rtx (V4DImode);

50914

t2 = gen_reg_rtx (V4DImode);

50915

50916

@@ -40144,6 +40203,9 @@

50917

return expand_vec_perm_even_odd_1 (&d_copy, odd);

50918

}

50919

50920

+ if (d->testing_p)

50921

+ break;

50922

+

50923

t1 = gen_reg_rtx (V8SImode);

50924

t2 = gen_reg_rtx (V8SImode);

50925

50926

@@ -40236,6 +40298,8 @@

50927

case V16QImode:

50928

/* These can be implemented via interleave. We save one insn by

50929

stopping once we have promoted to V4SImode and then use pshufd. */

50930

+ if (d->testing_p)

50931

+ return true;

50932

do

50933

{

50934

rtx dest;

50935

@@ -42473,8 +42537,6 @@

50936

50937

#undef TARGET_PROMOTE_PROTOTYPES

50938

#define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true

50939

-#undef TARGET_STRUCT_VALUE_RTX

50940

-#define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx

50941

#undef TARGET_SETUP_INCOMING_VARARGS

50942

#define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs

50943

#undef TARGET_MUST_PASS_IN_STACK

50944

Index: gcc/config/tilegx/tilegx.md

50945

===================================================================

50946

--- a/src/gcc/config/tilegx/tilegx.md (.../tags/gcc_4_8_2_release)

50947

+++ b/src/gcc/config/tilegx/tilegx.md (.../branches/gcc-4_8-branch)

50948

@@ -5076,10 +5076,8 @@

50949

50950

;; Network intrinsics

50951

50952

-;; Note the "pseudo" text is handled specially by the

50953

-;; asm_output_opcode routine. If the output is an empty string, the

50954

-;; instruction would bypass the asm_output_opcode routine, bypassing

50955

-;; the bundle handling code.

50956

+;; Note the this barrier is of type "nothing," which is deleted after

50957

+;; the final scheduling pass so that nothing is emitted for it.

50958

(define_insn "tilegx_network_barrier"

50959

[(unspec_volatile:SI [(const_int 0)] UNSPEC_NETWORK_BARRIER)]

50960

""

50961

Index: gcc/config/tilegx/tilegx-c.c

50962

===================================================================

50963

--- a/src/gcc/config/tilegx/tilegx-c.c (.../tags/gcc_4_8_2_release)

50964

+++ b/src/gcc/config/tilegx/tilegx-c.c (.../branches/gcc-4_8-branch)

50965

@@ -47,6 +47,9 @@

50966

if (TARGET_32BIT)

50967

builtin_define ("__tilegx32__");

50968

50969

+ builtin_define ("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");

50970

+ builtin_define ("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");

50971

+

50972

TILEGX_CPU_CPP_ENDIAN_BUILTINS ();

50973

GNU_USER_TARGET_OS_CPP_BUILTINS ();

50974

}

50975

Index: gcc/config/tilegx/sync.md

50976

===================================================================

50977

--- a/src/gcc/config/tilegx/sync.md (.../tags/gcc_4_8_2_release)

50978

+++ b/src/gcc/config/tilegx/sync.md (.../branches/gcc-4_8-branch)

50979

@@ -150,15 +150,22 @@

50980

(match_operand:SI 3 "const_int_operand" "")] ;; model

50981

""

50982

{

50983

+ rtx addend;

50984

enum memmodel model = (enum memmodel) INTVAL (operands[3]);

50985

50986

if (operands[2] != const0_rtx)

50987

- emit_move_insn (operands[2], gen_rtx_NEG (<MODE>mode, operands[2]));

50988

+ {

50989

+ addend = gen_reg_rtx (<MODE>mode);

50990

+ emit_move_insn (addend,

50991

+ gen_rtx_MINUS (<MODE>mode, const0_rtx, operands[2]));

50992

+ }

50993

+ else

50994

+ addend = operands[2];

50995

50996

tilegx_pre_atomic_barrier (model);

50997

emit_insn (gen_atomic_fetch_add_bare<mode> (operands[0],

50998

operands[1],

50999

- operands[2]));

51000

+ addend));

51001

tilegx_post_atomic_barrier (model);

51002

DONE;

51003

})

51004

Index: gcc/config/tilegx/tilegx.c

51005

===================================================================

51006

--- a/src/gcc/config/tilegx/tilegx.c (.../tags/gcc_4_8_2_release)

51007

+++ b/src/gcc/config/tilegx/tilegx.c (.../branches/gcc-4_8-branch)

51008

@@ -702,6 +702,16 @@

51009

}

51010

51011

51012

+/* Implement TARGET_EXPAND_TO_RTL_HOOK. */

51013

+static void

51014

+tilegx_expand_to_rtl_hook (void)

51015

+{

51016

+ /* Exclude earlier sets of crtl->uses_pic_offset_table, because we

51017

+ only care about uses actually emitted. */

51018

+ crtl->uses_pic_offset_table = 0;

51019

+}

51020

+

51021

+

51022

/* Implement TARGET_SHIFT_TRUNCATION_MASK. DImode shifts use the mode

51023

matching insns and therefore guarantee that the shift count is

51024

modulo 64. SImode shifts sometimes use the 64 bit version so do

51025

@@ -3543,6 +3553,12 @@

51026

}

51027

if (!pat)

51028

return NULL_RTX;

51029

+

51030

+ /* If we are generating a prefetch, tell the scheduler not to move

51031

+ it around. */

51032

+ if (GET_CODE (pat) == PREFETCH)

51033

+ PREFETCH_SCHEDULE_BARRIER_P (pat) = true;

51034

+

51035

emit_insn (pat);

51036

51037

if (nonvoid)

51038

@@ -4368,10 +4384,12 @@

51039

basic_block bb;

51040

FOR_EACH_BB (bb)

51041

{

51042

- rtx insn, next;

51043

+ rtx insn, next, prev;

51044

rtx end = NEXT_INSN (BB_END (bb));

51045

51046

- for (insn = next_insn_to_bundle (BB_HEAD (bb), end); insn; insn = next)

51047

+ prev = NULL_RTX;

51048

+ for (insn = next_insn_to_bundle (BB_HEAD (bb), end); insn;

51049

+ prev = insn, insn = next)

51050

{

51051

next = next_insn_to_bundle (NEXT_INSN (insn), end);

51052

51053

@@ -4396,6 +4414,18 @@

51054

PUT_MODE (insn, SImode);

51055

}

51056

}

51057

+

51058

+ /* Delete barrier insns, because they can mess up the

51059

+ emitting of bundle braces. If it is end-of-bundle, then

51060

+ the previous insn must be marked end-of-bundle. */

51061

+ if (get_attr_type (insn) == TYPE_NOTHING) {

51062

+ if (GET_MODE (insn) == QImode && prev != NULL

51063

+ && GET_MODE (prev) == SImode)

51064

+ {

51065

+ PUT_MODE (prev, QImode);

51066

+ }

51067

+ delete_insn (insn);

51068

+ }

51069

}

51070

}

51071

}

51072

@@ -5498,6 +5528,9 @@

51073

#undef TARGET_RTX_COSTS

51074

#define TARGET_RTX_COSTS tilegx_rtx_costs

51075

51076

+#undef TARGET_EXPAND_TO_RTL_HOOK

51077

+#define TARGET_EXPAND_TO_RTL_HOOK tilegx_expand_to_rtl_hook

51078

+

51079

#undef TARGET_SHIFT_TRUNCATION_MASK

51080

#define TARGET_SHIFT_TRUNCATION_MASK tilegx_shift_truncation_mask

51081

51082

Index: gcc/config/sh/predicates.md

51083

===================================================================

51084

--- a/src/gcc/config/sh/predicates.md (.../tags/gcc_4_8_2_release)

51085

+++ b/src/gcc/config/sh/predicates.md (.../branches/gcc-4_8-branch)

51086

@@ -389,6 +389,12 @@

51087

XEXP (XEXP (op, 0), 1),

51088

TARGET_SH2A, true)")))

51089

51090

+;; Returns true if OP is a displacement address that can fit into a

51091

+;; 16 bit (non-SH2A) memory load / store insn.

51092

+(define_predicate "short_displacement_mem_operand"

51093

+ (match_test "sh_disp_addr_displacement (op)

51094

+ <= sh_max_mov_insn_displacement (GET_MODE (op), false)"))

51095

+

51096

;; Returns 1 if the operand can be used in an SH2A movu.{b|w} insn.

51097

(define_predicate "zero_extend_movu_operand"

51098

(and (match_operand 0 "displacement_mem_operand")

51099

@@ -413,6 +419,11 @@

51100

if (t_reg_operand (op, mode))

51101

return 0;

51102

51103

+ /* Disallow PC relative QImode loads, since these is no insn to do that

51104

+ and an imm8 load should be used instead. */

51105

+ if (IS_PC_RELATIVE_LOAD_ADDR_P (op) && GET_MODE (op) == QImode)

51106

+ return false;

51107

+

51108

if (MEM_P (op))

51109

{

51110

rtx inside = XEXP (op, 0);

51111

Index: gcc/config/sh/sh-protos.h

51112

===================================================================

51113

--- a/src/gcc/config/sh/sh-protos.h (.../tags/gcc_4_8_2_release)

51114

+++ b/src/gcc/config/sh/sh-protos.h (.../branches/gcc-4_8-branch)

51115

@@ -159,6 +159,8 @@

51116

extern bool sh_cfun_trap_exit_p (void);

51117

extern rtx sh_find_equiv_gbr_addr (rtx cur_insn, rtx mem);

51118

extern int sh_eval_treg_value (rtx op);

51119

+extern HOST_WIDE_INT sh_disp_addr_displacement (rtx mem_op);

51120

+extern int sh_max_mov_insn_displacement (machine_mode mode, bool consider_sh2a);

51121

51122

/* Result value of sh_find_set_of_reg. */

51123

struct set_of_reg

51124

Index: gcc/config/sh/sh.c

51125

===================================================================

51126

--- a/src/gcc/config/sh/sh.c (.../tags/gcc_4_8_2_release)

51127

+++ b/src/gcc/config/sh/sh.c (.../branches/gcc-4_8-branch)

51128

@@ -24,6 +24,9 @@

51129

malloc & co, which are poisoned by "system.h". The proper solution is

51130

to include <cstdlib> in "system.h" instead of <stdlib.h>. */

51131

#include <cstdlib>

51132

+#include <sstream>

51133

+#include <vector>

51134

+#include <algorithm>

51135

51136

#include "config.h"

51137

#include "system.h"

51138

@@ -60,10 +63,6 @@

51139

#include "tm-constrs.h"

51140

#include "opts.h"

51141

51142

-#include <sstream>

51143

-#include <vector>

51144

-#include <algorithm>

51145

-

51146

int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch;

51147

51148

#define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)

51149

@@ -310,9 +309,7 @@

51150

static void sh_conditional_register_usage (void);

51151

static bool sh_legitimate_constant_p (enum machine_mode, rtx);

51152

static int mov_insn_size (enum machine_mode, bool);

51153

-static int max_mov_insn_displacement (enum machine_mode, bool);

51154

static int mov_insn_alignment_mask (enum machine_mode, bool);

51155

-static HOST_WIDE_INT disp_addr_displacement (rtx);

51156

static bool sequence_insn_p (rtx);

51157

static void sh_canonicalize_comparison (int *, rtx *, rtx *, bool);

51158

static void sh_canonicalize_comparison (enum rtx_code&, rtx&, rtx&,

51159

@@ -3628,8 +3625,8 @@

51160

51161

/* Determine the maximum possible displacement for a move insn for the

51162

specified mode. */

51163

-static int

51164

-max_mov_insn_displacement (enum machine_mode mode, bool consider_sh2a)

51165

+int

51166

+sh_max_mov_insn_displacement (machine_mode mode, bool consider_sh2a)

51167

{

51168

/* The 4 byte displacement move insns are the same as the 2 byte

51169

versions but take a 12 bit displacement. All we need to do is to

51170

@@ -3665,8 +3662,8 @@

51171

}

51172

51173

/* Return the displacement value of a displacement address. */

51174

-static inline HOST_WIDE_INT

51175

-disp_addr_displacement (rtx x)

51176

+HOST_WIDE_INT

51177

+sh_disp_addr_displacement (rtx x)

51178

{

51179

gcc_assert (satisfies_constraint_Sdd (x));

51180

return INTVAL (XEXP (XEXP (x, 0), 1));

51181

@@ -3703,12 +3700,12 @@

51182

HImode and QImode loads/stores with displacement put pressure on

51183

R0 which will most likely require another reg copy. Thus account

51184

a higher cost for that. */

51185

- if (offset > 0 && offset <= max_mov_insn_displacement (mode, false))

51186

+ if (offset > 0 && offset <= sh_max_mov_insn_displacement (mode, false))

51187

return (mode == HImode || mode == QImode) ? 2 : 1;

51188

51189

/* The displacement would fit into a 4 byte move insn (SH2A). */

51190

if (TARGET_SH2A

51191

- && offset > 0 && offset <= max_mov_insn_displacement (mode, true))

51192

+ && offset > 0 && offset <= sh_max_mov_insn_displacement (mode, true))

51193

return 2;

51194

51195

/* The displacement is probably out of range and will require extra

51196

@@ -10218,7 +10215,7 @@

51197

else

51198

{

51199

const HOST_WIDE_INT offset = INTVAL (op);

51200

- const int max_disp = max_mov_insn_displacement (mode, consider_sh2a);

51201

+ const int max_disp = sh_max_mov_insn_displacement (mode, consider_sh2a);

51202

const int align_mask = mov_insn_alignment_mask (mode, consider_sh2a);

51203

51204

/* If the mode does not support any displacement always return false.

51205

@@ -10404,7 +10401,7 @@

51206

effectively disable the small displacement insns. */

51207

const int mode_sz = GET_MODE_SIZE (mode);

51208

const int mov_insn_sz = mov_insn_size (mode, false);

51209

- const int max_disp = max_mov_insn_displacement (mode, false);

51210

+ const int max_disp = sh_max_mov_insn_displacement (mode, false);

51211

const int max_disp_next = max_disp + mov_insn_sz;

51212

HOST_WIDE_INT align_modifier = offset > 127 ? mov_insn_sz : 0;

51213

HOST_WIDE_INT offset_adjust;

51214

@@ -13165,7 +13162,8 @@

51215

the insns must have the appropriate alternatives. */

51216

if ((mode == QImode || mode == HImode) && rclass != R0_REGS

51217

&& satisfies_constraint_Sdd (x)

51218

- && disp_addr_displacement (x) <= max_mov_insn_displacement (mode, false))

51219

+ && sh_disp_addr_displacement (x)

51220

+ <= sh_max_mov_insn_displacement (mode, false))

51221

return R0_REGS;

51222

51223

/* When reload is trying to address a QImode or HImode subreg on the stack,

51224

Index: gcc/config/sh/constraints.md

51225

===================================================================

51226

--- a/src/gcc/config/sh/constraints.md (.../tags/gcc_4_8_2_release)

51227

+++ b/src/gcc/config/sh/constraints.md (.../branches/gcc-4_8-branch)

51228

@@ -221,6 +221,7 @@

51229

(define_constraint "Q"

51230

"A pc relative load operand."

51231

(and (match_code "mem")

51232

+ (match_test "GET_MODE (op) != QImode")

51233

(match_test "IS_PC_RELATIVE_LOAD_ADDR_P (XEXP (op, 0))")))

51234

51235

(define_constraint "Bsc"

51236

@@ -295,13 +296,15 @@

51237

51238

(define_memory_constraint "Sdd"

51239

"A memory reference that uses displacement addressing."

51240

- (and (match_test "MEM_P (op) && GET_CODE (XEXP (op, 0)) == PLUS")

51241

+ (and (match_code "mem")

51242

+ (match_test "GET_CODE (XEXP (op, 0)) == PLUS")

51243

(match_test "REG_P (XEXP (XEXP (op, 0), 0))")

51244

(match_test "CONST_INT_P (XEXP (XEXP (op, 0), 1))")))

51245

51246

(define_memory_constraint "Snd"

51247

"A memory reference that excludes displacement addressing."

51248

- (match_test "! satisfies_constraint_Sdd (op)"))

51249

+ (and (match_code "mem")

51250

+ (match_test "! satisfies_constraint_Sdd (op)")))

51251

51252

(define_memory_constraint "Sbv"

51253

"A memory reference, as used in SH2A bclr.b, bset.b, etc."

51254

Index: gcc/config/sh/sh.md

51255

===================================================================

51256

--- a/src/gcc/config/sh/sh.md (.../tags/gcc_4_8_2_release)

51257

+++ b/src/gcc/config/sh/sh.md (.../branches/gcc-4_8-branch)

51258

@@ -2152,6 +2152,7 @@

51259

(udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))

51260

(clobber (reg:SI T_REG))

51261

(clobber (reg:SI PR_REG))

51262

+ (clobber (reg:SI R1_REG))

51263

(clobber (reg:SI R4_REG))

51264

(use (match_operand:SI 1 "arith_reg_operand" "r"))]

51265

"TARGET_SH1 && TARGET_DIVIDE_CALL_DIV1"

51266

@@ -6831,34 +6832,9 @@

51267

prepare_move_operands (operands, QImode);

51268

})

51269

51270

-;; If movqi_reg_reg is specified as an alternative of movqi, movqi will be

51271

-;; selected to copy QImode regs. If one of them happens to be allocated

51272

-;; on the stack, reload will stick to movqi insn and generate wrong

51273

-;; displacement addressing because of the generic m alternatives.

51274

-;; With the movqi_reg_reg being specified before movqi it will be initially

51275

-;; picked to load/store regs. If the regs regs are on the stack reload

51276

-;; try other insns and not stick to movqi_reg_reg, unless there were spilled

51277

-;; pseudos in which case 'm' constraints pertain.

51278

-;; The same applies to the movhi variants.

51279

-;;

51280

-;; Notice, that T bit is not allowed as a mov src operand here. This is to

51281

-;; avoid things like (set (reg:QI) (subreg:QI (reg:SI T_REG) 0)), which

51282

-;; introduces zero extensions after T bit stores and redundant reg copies.

51283

-;;

51284

-;; FIXME: We can't use 'arith_reg_operand' (which disallows T_REG) as a

51285

-;; predicate for the mov src operand because reload will have trouble

51286

-;; reloading MAC subregs otherwise. For that probably special patterns

51287

-;; would be required.

51288

-(define_insn "*mov<mode>_reg_reg"

51289

- [(set (match_operand:QIHI 0 "arith_reg_dest" "=r,m,*z")

51290

- (match_operand:QIHI 1 "register_operand" "r,*z,m"))]

51291

- "TARGET_SH1 && !t_reg_operand (operands[1], VOIDmode)"

51292

- "@

51293

- mov %1,%0

51294

- mov.<bw> %1,%0

51295

- mov.<bw> %1,%0"

51296

- [(set_attr "type" "move,store,load")])

51297

-

51298

+;; Specifying the displacement addressing load / store patterns separately

51299

+;; before the generic movqi / movhi pattern allows controlling the order

51300

+;; in which load / store insns are selected in a more fine grained way.

51301

;; FIXME: The non-SH2A and SH2A variants should be combined by adding

51302

;; "enabled" attribute as it is done in other targets.

51303

(define_insn "*mov<mode>_store_mem_disp04"

51304

@@ -6908,38 +6884,44 @@

51305

[(set_attr "type" "load")

51306

(set_attr "length" "2,2,4")])

51307

51308

-;; The m constraints basically allow any kind of addresses to be used with any

51309

-;; source/target register as the other operand. This is not true for

51310

-;; displacement addressing modes on anything but SH2A. That's why the

51311

-;; specialized load/store insns are specified above.

51312

-(define_insn "*movqi"

51313

- [(set (match_operand:QI 0 "general_movdst_operand" "=r,r,m,r,l")

51314

- (match_operand:QI 1 "general_movsrc_operand" "i,m,r,l,r"))]

51315

+;; The order of the constraint alternatives is important here.

51316

+;; Q/r has to come first, otherwise PC relative loads might wrongly get

51317

+;; placed into delay slots. Since there is no QImode PC relative load, the

51318

+;; Q constraint and general_movsrc_operand will reject it for QImode.

51319

+;; The Snd alternatives should come before Sdd in order to avoid a preference

51320

+;; of using r0 als the register operand for addressing modes other than

51321

+;; displacement addressing.

51322

+;; The Sdd alternatives allow only r0 as register operand, even though on

51323

+;; SH2A any register could be allowed by switching to a 32 bit insn.

51324

+;; Generally sticking to the r0 is preferrable, since it generates smaller

51325

+;; code. Obvious r0 reloads can then be eliminated with a peephole on SH2A.

51326

+(define_insn "*mov<mode>"

51327

+ [(set (match_operand:QIHI 0 "general_movdst_operand"

51328

+ "=r,r,r,Snd,r, Sdd,z, r,l")

51329

+ (match_operand:QIHI 1 "general_movsrc_operand"

51330

+ "Q,r,i,r, Snd,z, Sdd,l,r"))]

51331

"TARGET_SH1

51332

- && (arith_reg_operand (operands[0], QImode)

51333

- || arith_reg_operand (operands[1], QImode))"

51334

+ && (arith_reg_operand (operands[0], <MODE>mode)

51335

+ || arith_reg_operand (operands[1], <MODE>mode))"

51336

"@

51337

+ mov.<bw> %1,%0

51338

mov %1,%0

51339

- mov.b %1,%0

51340

- mov.b %1,%0

51341

- sts %1,%0

51342

- lds %1,%0"

51343

- [(set_attr "type" "movi8,load,store,prget,prset")])

51344

-

51345

-(define_insn "*movhi"

51346

- [(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,m,r,l")

51347

- (match_operand:HI 1 "general_movsrc_operand" "Q,i,m,r,l,r"))]

51348

- "TARGET_SH1

51349

- && (arith_reg_operand (operands[0], HImode)

51350

- || arith_reg_operand (operands[1], HImode))"

51351

- "@

51352

- mov.w %1,%0

51353

mov %1,%0

51354

- mov.w %1,%0

51355

- mov.w %1,%0

51356

+ mov.<bw> %1,%0

51357

+ mov.<bw> %1,%0

51358

+ mov.<bw> %1,%0

51359

+ mov.<bw> %1,%0

51360

sts %1,%0

51361

lds %1,%0"

51362

- [(set_attr "type" "pcload,movi8,load,store,prget,prset")])

51363

+ [(set_attr "type" "pcload,move,movi8,store,load,store,load,prget,prset")

51364

+ (set (attr "length")

51365

+ (cond [(and (match_operand 0 "displacement_mem_operand")

51366

+ (not (match_operand 0 "short_displacement_mem_operand")))

51367

+ (const_int 4)

51368

+ (and (match_operand 1 "displacement_mem_operand")

51369

+ (not (match_operand 1 "short_displacement_mem_operand")))

51370

+ (const_int 4)]

51371

+ (const_int 2)))])

51372

51373

(define_insn "*movqi_media"

51374

[(set (match_operand:QI 0 "general_movdst_operand" "=r,r,r,m")

51375

@@ -8427,11 +8409,9 @@

51376

51377

while (true)

51378

{

51379

- /* It's not safe to go beyond the current basic block after reload. */

51380

set_of_reg s1 = sh_find_set_of_reg (tested_reg, s0.insn,

51381

- reload_completed

51382

- ? prev_nonnote_insn_bb

51383

- : prev_nonnote_insn);

51384

+ prev_nonnote_insn);

51385

+

51386

if (s1.set_src == NULL_RTX)

51387

break;

51388

51389

@@ -8449,15 +8429,25 @@

51390

continue;

51391

}

51392

51393

- /* It's only safe to remove the testing insn if the T bit is not

51394

- modified between the testing insn and the insn that stores the

51395

- T bit. Notice that some T bit stores such as negc also modify

51396

- the T bit. */

51397

- if (modified_between_p (get_t_reg_rtx (), s1.insn, testing_insn)

51398

- || modified_in_p (get_t_reg_rtx (), s1.insn))

51399

- operands[2] = NULL_RTX;

51400

+ /* It's only safe to remove the testing insn if the T bit is not

51401

+ modified between the testing insn and the insn that stores the

51402

+ T bit. Notice that some T bit stores such as negc also modify

51403

+ the T bit. */

51404

+ if (modified_between_p (get_t_reg_rtx (), s1.insn, testing_insn)

51405

+ || modified_in_p (get_t_reg_rtx (), s1.insn)

51406

+ || !no_labels_between_p (s1.insn, testing_insn))

51407

+ operands[2] = NULL_RTX;

51408

+ else

51409

+ {

51410

+ /* If the insn that sets the tested reg has a REG_DEAD note on

51411

+ the T bit remove that note since we're extending the usage

51412

+ of the T bit. */

51413

+ rtx n = find_regno_note (s1.insn, REG_DEAD, T_REG);

51414

+ if (n != NULL_RTX)

51415

+ remove_note (s1.insn, n);

51416

+ }

51417

51418

- break;

51419

+ break;

51420

}

51421

51422

if (operands[2] == NULL_RTX)

51423

Index: gcc/config/sh/sh.opt

51424

===================================================================

51425

--- a/src/gcc/config/sh/sh.opt (.../tags/gcc_4_8_2_release)

51426

+++ b/src/gcc/config/sh/sh.opt (.../branches/gcc-4_8-branch)

51427

@@ -21,7 +21,7 @@

51428

;; Used for various architecture options.

51429

Mask(SH_E)

51430

51431

-;; Set if the default precision of th FPU is single.

51432

+;; Set if the default precision of the FPU is single.

51433

Mask(FPU_SINGLE)

51434

51435

;; Set if the a double-precision FPU is present but is restricted to

51436

Index: gcc/config/microblaze/predicates.md

51437

===================================================================

51438

--- a/src/gcc/config/microblaze/predicates.md (.../tags/gcc_4_8_2_release)

51439

+++ b/src/gcc/config/microblaze/predicates.md (.../branches/gcc-4_8-branch)

51440

@@ -85,6 +85,10 @@

51441

(ior (match_operand 0 "const_0_operand")

51442

(match_operand 0 "register_operand")))

51443

51444

+(define_predicate "reg_or_mem_operand"

51445

+ (ior (match_operand 0 "memory_operand")

51446

+ (match_operand 0 "register_operand")))

51447

+

51448

;; Return if the operand is either the PC or a label_ref.

51449

(define_special_predicate "pc_or_label_operand"

51450

(ior (match_code "pc,label_ref")

51451

@@ -119,3 +123,7 @@

51452

;; Test for valid PIC call operand

51453

(define_predicate "call_insn_plt_operand"

51454

(match_test "PLT_ADDR_P (op)"))

51455

+

51456

+;; Return if the code of this rtx pattern is a comparison.

51457

+(define_predicate "cmp_op"

51458

+ (match_code "gt,ge,gtu,geu,lt,le,ltu,leu"))

51459

Index: gcc/config/microblaze/microblaze.md

51460

===================================================================

51461

--- a/src/gcc/config/microblaze/microblaze.md (.../tags/gcc_4_8_2_release)

51462

+++ b/src/gcc/config/microblaze/microblaze.md (.../branches/gcc-4_8-branch)

51463

@@ -74,7 +74,7 @@

51464

;; bshift Shift operations

51465

51466

(define_attr "type"

51467

- "unknown,branch,jump,call,load,store,move,arith,darith,imul,idiv,icmp,multi,nop,no_delay_arith,no_delay_load,no_delay_store,no_delay_imul,no_delay_move,bshift,fadd,frsub,fmul,fdiv,fcmp,fsl,fsqrt,fcvt"

51468

+ "unknown,branch,jump,call,load,store,move,arith,darith,imul,idiv,icmp,multi,nop,no_delay_arith,no_delay_load,no_delay_store,no_delay_imul,no_delay_move,bshift,fadd,frsub,fmul,fdiv,fcmp,fsl,fsqrt,fcvt,trap"

51469

(const_string "unknown"))

51470

51471

;; Main data type used by the insn

51472

@@ -365,7 +365,8 @@

51473

[(set (match_operand:HI 0 "register_operand" "=r")

51474

(bswap:HI (match_operand:HI 1 "register_operand" "r")))]

51475

"TARGET_REORDER"

51476

- "swaph %0, %1"

51477

+ "swapb %0, %1

51478

+ swaph %0, %0"

51479

)

51480

51481

;;----------------------------------------------------------------

51482

@@ -1118,6 +1119,18 @@

51483

}

51484

)

51485

51486

+;;Load and store reverse

51487

+(define_insn "movsi4_rev"

51488

+ [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Q")

51489

+ (bswap:SI (match_operand:SF 1 "reg_or_mem_operand" "Q,r")))]

51490

+ "TARGET_REORDER"

51491

+ "@

51492

+ lwr\t%0,%y1,r0

51493

+ swr\t%1,%y0,r0"

51494

+ [(set_attr "type" "load,store")

51495

+ (set_attr "mode" "SI")

51496

+ (set_attr "length" "4,4")])

51497

+

51498

;; 32-bit floating point moves

51499

51500

(define_expand "movsf"

51501

@@ -1472,7 +1485,7 @@

51502

(set_attr "length" "124")]

51503

)

51504

51505

-(define_insn "*ashlri_reg"

51506

+(define_insn "*ashrsi_reg"

51507

[(set (match_operand:SI 0 "register_operand" "=&d")

51508

(ashiftrt:SI (match_operand:SI 1 "register_operand" "d")

51509

(match_operand:SI 2 "register_operand" "d")))]

51510

@@ -1561,7 +1574,7 @@

51511

(set_attr "length" "124")]

51512

)

51513

51514

-(define_insn "*lshlri_reg"

51515

+(define_insn "*lshrsi_reg"

51516

[(set (match_operand:SI 0 "register_operand" "=&d")

51517

(lshiftrt:SI (match_operand:SI 1 "register_operand" "d")

51518

(match_operand:SI 2 "register_operand" "d")))]

51519

@@ -1622,34 +1635,12 @@

51520

(set_attr "length" "4")]

51521

)

51522

51523

-(define_insn "signed_compare"

51524

- [(set (match_operand:SI 0 "register_operand" "=d")

51525

- (unspec

51526

- [(match_operand:SI 1 "register_operand" "d")

51527

- (match_operand:SI 2 "register_operand" "d")] UNSPEC_CMP))]

51528

- ""

51529

- "cmp\t%0,%1,%2"

51530

- [(set_attr "type" "arith")

51531

- (set_attr "mode" "SI")

51532

- (set_attr "length" "4")])

51533

-

51534

-(define_insn "unsigned_compare"

51535

- [(set (match_operand:SI 0 "register_operand" "=d")

51536

- (unspec

51537

- [(match_operand:SI 1 "register_operand" "d")

51538

- (match_operand:SI 2 "register_operand" "d")] UNSPEC_CMPU))]

51539

- ""

51540

- "cmpu\t%0,%1,%2"

51541

- [(set_attr "type" "arith")

51542

- (set_attr "mode" "SI")

51543

- (set_attr "length" "4")])

51544

-

51545

;;----------------------------------------------------------------

51546

;; Setting a register from an floating point comparison.

51547

;;----------------------------------------------------------------

51548

(define_insn "cstoresf4"

51549

[(set (match_operand:SI 0 "register_operand" "=r")

51550

- (match_operator 1 "comparison_operator"

51551

+ (match_operator:SI 1 "ordered_comparison_operator"

51552

[(match_operand:SF 2 "register_operand" "r")

51553

(match_operand:SF 3 "register_operand" "r")]))]

51554

"TARGET_HARD_FLOAT"

51555

@@ -1678,7 +1669,7 @@

51556

51557

(define_expand "cbranchsf4"

51558

[(set (pc)

51559

- (if_then_else (match_operator 0 "comparison_operator"

51560

+ (if_then_else (match_operator 0 "ordered_comparison_operator"

51561

[(match_operand:SF 1 "register_operand")

51562

(match_operand:SF 2 "register_operand")])

51563

(label_ref (match_operand 3 ""))

51564

@@ -1717,6 +1708,47 @@

51565

(set_attr "length" "4")]

51566

)

51567

51568

+(define_insn "branch_compare"

51569

+ [(set (pc)

51570

+ (if_then_else (match_operator:SI 0 "cmp_op"

51571

+ [(match_operand:SI 1 "register_operand" "d")

51572

+ (match_operand:SI 2 "register_operand" "d")

51573

+ ])

51574

+ (label_ref (match_operand 3))

51575

+ (pc)))

51576

+ (clobber(reg:SI R_TMP))]

51577

+ ""

51578

+ {

51579

+ operands[4] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);

51580

+ enum rtx_code code = GET_CODE (operands[0]);

51581

+

51582

+ if (code == GT || code == LE)

51583

+ {

51584

+ output_asm_insn ("cmp\tr18,%z1,%z2", operands);

51585

+ code = swap_condition (code);

51586

+ }

51587

+ else if (code == GTU || code == LEU)

51588

+ {

51589

+ output_asm_insn ("cmpu\tr18,%z1,%z2", operands);

51590

+ code = swap_condition (code);

51591

+ }

51592

+ else if (code == GE || code == LT)

51593

+ {

51594

+ output_asm_insn ("cmp\tr18,%z2,%z1", operands);

51595

+ }

51596

+ else if (code == GEU || code == LTU)

51597

+ {

51598

+ output_asm_insn ("cmpu\tr18,%z2,%z1", operands);

51599

+ }

51600

+

51601

+ operands[0] = gen_rtx_fmt_ee (signed_condition (code), SImode, operands[4], const0_rtx);

51602

+ return "b%C0i%?\tr18,%3";

51603

+ }

51604

+ [(set_attr "type" "branch")

51605

+ (set_attr "mode" "none")

51606

+ (set_attr "length" "12")]

51607

+)

51608

+

51609

;;----------------------------------------------------------------

51610

;; Unconditional branches

51611

;;----------------------------------------------------------------

51612

@@ -2201,6 +2233,14 @@

51613

(set_attr "mode" "none")

51614

(set_attr "length" "4")])

51615

51616

+;; Trap instruction pattern for __builtin_trap. Same as the glibc ABORT_INSTRUCTION

51617

+(define_insn "trap"

51618

+ [(trap_if (const_int 1) (const_int 0))]

51619

+ ""

51620

+ "brki\tr0,-1"

51621

+ [(set_attr "type" "trap")]

51622

+)

51623

+

51624

;; The insn to set GOT. The hardcoded number "8" accounts for $pc difference

51625

;; between "mfs" and "addik" instructions.

51626

(define_insn "set_got"

51627

Index: gcc/config/microblaze/microblaze.c

51628

===================================================================

51629

--- a/src/gcc/config/microblaze/microblaze.c (.../tags/gcc_4_8_2_release)

51630

+++ b/src/gcc/config/microblaze/microblaze.c (.../branches/gcc-4_8-branch)

51631

@@ -1609,21 +1609,28 @@

51632

microblaze_version_to_int (const char *version)

51633

{

51634

const char *p, *v;

51635

- const char *tmpl = "vX.YY.Z";

51636

+ const char *tmpl = "vXX.YY.Z";

51637

int iver = 0;

51638

51639

p = version;

51640

v = tmpl;

51641

51642

- while (*v)

51643

+ while (*p)

51644

{

51645

if (*v == 'X')

51646

{ /* Looking for major */

51647

- if (!(*p >= '0' && *p <= '9'))

51648

- return -1;

51649

- iver += (int) (*p - '0');

51650

- iver *= 10;

51651

- }

51652

+ if (*p == '.')

51653

+ {

51654

+ *v++;

51655

+ }

51656

+ else

51657

+ {

51658

+ if (!(*p >= '0' && *p <= '9'))

51659

+ return -1;

51660

+ iver += (int) (*p - '0');

51661

+ iver *= 10;

51662

+ }

51663

+ }

51664

else if (*v == 'Y')

51665

{ /* Looking for minor */

51666

if (!(*p >= '0' && *p <= '9'))

51667

@@ -3064,6 +3071,73 @@

51668

return result;

51669

}

51670

51671

+static void

51672

+microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,

51673

+ HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,

51674

+ tree function)

51675

+{

51676

+ rtx this_rtx, insn, funexp;

51677

+

51678

+ reload_completed = 1;

51679

+ epilogue_completed = 1;

51680

+

51681

+ /* Mark the end of the (empty) prologue. */

51682

+ emit_note (NOTE_INSN_PROLOGUE_END);

51683

+

51684

+ /* Find the "this" pointer. If the function returns a structure,

51685

+ the structure return pointer is in MB_ABI_FIRST_ARG_REGNUM. */

51686

+ if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))

51687

+ this_rtx = gen_rtx_REG (Pmode, (MB_ABI_FIRST_ARG_REGNUM + 1));

51688

+ else

51689

+ this_rtx = gen_rtx_REG (Pmode, MB_ABI_FIRST_ARG_REGNUM);

51690

+

51691

+ /* Apply the constant offset, if required. */

51692

+ if (delta)

51693

+ emit_insn (gen_addsi3 (this_rtx, this_rtx, GEN_INT (delta)));

51694

+

51695

+ /* Apply the offset from the vtable, if required. */

51696

+ if (vcall_offset)

51697

+ {

51698

+ rtx vcall_offset_rtx = GEN_INT (vcall_offset);

51699

+ rtx temp1 = gen_rtx_REG (Pmode, MB_ABI_TEMP1_REGNUM);

51700

+

51701

+ emit_move_insn (temp1, gen_rtx_MEM (Pmode, this_rtx));

51702

+

51703

+ rtx loc = gen_rtx_PLUS (Pmode, temp1, vcall_offset_rtx);

51704

+ emit_move_insn (temp1, gen_rtx_MEM (Pmode, loc));

51705

+

51706

+ emit_insn (gen_addsi3 (this_rtx, this_rtx, temp1));

51707

+ }

51708

+

51709

+ /* Generate a tail call to the target function. */

51710

+ if (!TREE_USED (function))

51711

+ {

51712

+ assemble_external (function);

51713

+ TREE_USED (function) = 1;

51714

+ }

51715

+

51716

+ funexp = XEXP (DECL_RTL (function), 0);

51717

+ rtx temp2 = gen_rtx_REG (Pmode, MB_ABI_TEMP2_REGNUM);

51718

+

51719

+ if (flag_pic)

51720

+ emit_move_insn (temp2, expand_pic_symbol_ref (Pmode, funexp));

51721

+ else

51722

+ emit_move_insn (temp2, funexp);

51723

+

51724

+ emit_insn (gen_indirect_jump (temp2));

51725

+

51726

+ /* Run just enough of rest_of_compilation. This sequence was

51727

+ "borrowed" from rs6000.c. */

51728

+ insn = get_insns ();

51729

+ shorten_branches (insn);

51730

+ final_start_function (insn, file, 1);

51731

+ final (insn, file, 1);

51732

+ final_end_function ();

51733

+

51734

+ reload_completed = 0;

51735

+ epilogue_completed = 0;

51736

+}

51737

+

51738

bool

51739

microblaze_expand_move (enum machine_mode mode, rtx operands[])

51740

{

51741

@@ -3234,67 +3308,47 @@

51742

emit_move_insn (mem, fnaddr);

51743

}

51744

51745

-/* Emit instruction to perform compare.

51746

- cmp is (compare_op op0 op1). */

51747

-static rtx

51748

-microblaze_emit_compare (enum machine_mode mode, rtx cmp, enum rtx_code *cmp_code)

51749

+/* Generate conditional branch -- first, generate test condition,

51750

+ second, generate correct branch instruction. */

51751

+

51752

+void

51753

+microblaze_expand_conditional_branch (enum machine_mode mode, rtx operands[])

51754

{

51755

- rtx cmp_op0 = XEXP (cmp, 0);

51756

- rtx cmp_op1 = XEXP (cmp, 1);

51757

+ enum rtx_code code = GET_CODE (operands[0]);

51758

+ rtx cmp_op0 = operands[1];

51759

+ rtx cmp_op1 = operands[2];

51760

+ rtx label1 = operands[3];

51761

rtx comp_reg = gen_reg_rtx (SImode);

51762

- enum rtx_code code = *cmp_code;

51763

-

51764

+ rtx condition;

51765

+

51766

gcc_assert ((GET_CODE (cmp_op0) == REG) || (GET_CODE (cmp_op0) == SUBREG));

51767

51768

/* If comparing against zero, just test source reg. */

51769

- if (cmp_op1 == const0_rtx)

51770

- return cmp_op0;

51771

+ if (cmp_op1 == const0_rtx)

51772

+ {

51773

+ comp_reg = cmp_op0;

51774

+ condition = gen_rtx_fmt_ee (signed_condition (code), SImode, comp_reg, const0_rtx);

51775

+ emit_jump_insn (gen_condjump (condition, label1));

51776

+ }

51777

51778

- if (code == EQ || code == NE)

51779

+ else if (code == EQ || code == NE)

51780

{

51781

/* Use xor for equal/not-equal comparison. */

51782

emit_insn (gen_xorsi3 (comp_reg, cmp_op0, cmp_op1));

51783

+ condition = gen_rtx_fmt_ee (signed_condition (code), SImode, comp_reg, const0_rtx);

51784

+ emit_jump_insn (gen_condjump (condition, label1));

51785

}

51786

- else if (code == GT || code == GTU || code == LE || code == LEU)

51787

+ else

51788

{

51789

- /* MicroBlaze compare is not symmetrical. */

51790

- /* Swap argument order. */

51791

+ /* Generate compare and branch in single instruction. */

51792

cmp_op1 = force_reg (mode, cmp_op1);

51793

- if (code == GT || code == LE)

51794

- emit_insn (gen_signed_compare (comp_reg, cmp_op0, cmp_op1));

51795

- else

51796

- emit_insn (gen_unsigned_compare (comp_reg, cmp_op0, cmp_op1));

51797

- /* Translate test condition. */

51798

- *cmp_code = swap_condition (code);

51799

+ condition = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);

51800

+ emit_jump_insn (gen_branch_compare(condition, cmp_op0, cmp_op1, label1));

51801

}

51802

- else /* if (code == GE || code == GEU || code == LT || code == LTU) */

51803

- {

51804

- cmp_op1 = force_reg (mode, cmp_op1);

51805

- if (code == GE || code == LT)

51806

- emit_insn (gen_signed_compare (comp_reg, cmp_op1, cmp_op0));

51807

- else

51808

- emit_insn (gen_unsigned_compare (comp_reg, cmp_op1, cmp_op0));

51809

- }

51810

-

51811

- return comp_reg;

51812

}

51813

51814

-/* Generate conditional branch -- first, generate test condition,

51815

- second, generate correct branch instruction. */

51816

51817

void

51818

-microblaze_expand_conditional_branch (enum machine_mode mode, rtx operands[])

51819

-{

51820

- enum rtx_code code = GET_CODE (operands[0]);

51821

- rtx comp;

51822

- rtx condition;

51823

-

51824

- comp = microblaze_emit_compare (mode, operands[0], &code);

51825

- condition = gen_rtx_fmt_ee (signed_condition (code), SImode, comp, const0_rtx);

51826

- emit_jump_insn (gen_condjump (condition, operands[3]));

51827

-}

51828

-

51829

-void

51830

microblaze_expand_conditional_branch_sf (rtx operands[])

51831

{

51832

rtx condition;

51833

@@ -3501,6 +3555,12 @@

51834

#undef TARGET_SECONDARY_RELOAD

51835

#define TARGET_SECONDARY_RELOAD microblaze_secondary_reload

51836

51837

+#undef TARGET_ASM_OUTPUT_MI_THUNK

51838

+#define TARGET_ASM_OUTPUT_MI_THUNK microblaze_asm_output_mi_thunk

51839

+

51840

+#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK

51841

+#define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true

51842

+

51843

#undef TARGET_SCHED_ADJUST_COST

51844

#define TARGET_SCHED_ADJUST_COST microblaze_adjust_cost

51845

51846

Index: gcc/config/microblaze/microblaze.h

51847

===================================================================

51848

--- a/src/gcc/config/microblaze/microblaze.h (.../tags/gcc_4_8_2_release)

51849

+++ b/src/gcc/config/microblaze/microblaze.h (.../branches/gcc-4_8-branch)

51850

@@ -213,6 +213,12 @@

51851

#define STRICT_ALIGNMENT 1

51852

#define PCC_BITFIELD_TYPE_MATTERS 1

51853

51854

+#undef SIZE_TYPE

51855

+#define SIZE_TYPE "unsigned int"

51856

+

51857

+#undef PTRDIFF_TYPE

51858

+#define PTRDIFF_TYPE "int"

51859

+

51860

#define CONSTANT_ALIGNMENT(EXP, ALIGN) \

51861

((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \

51862

&& (ALIGN) < BITS_PER_WORD \

51863

@@ -407,9 +413,6 @@

51864

|| GET_MODE (X) == VOIDmode) \

51865

? (GR_REGS) : (CLASS))))

51866

51867

-#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \

51868

- (GET_MODE_CLASS (MODE) == MODE_INT)

51869

-

51870

/* Stack layout; function entry, exit and calling. */

51871

51872

#define STACK_GROWS_DOWNWARD

51873

Index: gcc/config/avr/avr.c

51874

===================================================================

51875

--- a/src/gcc/config/avr/avr.c (.../tags/gcc_4_8_2_release)

51876

+++ b/src/gcc/config/avr/avr.c (.../branches/gcc-4_8-branch)

51877

@@ -587,10 +587,14 @@

51878

const char *name;

51879

51880

name = DECL_ASSEMBLER_NAME_SET_P (decl)

51881

- /* Remove the leading '*' added in set_user_assembler_name. */

51882

- ? 1 + IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))

51883

+ ? IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))

51884

: IDENTIFIER_POINTER (DECL_NAME (decl));

51885

51886

+ /* Skip a leading '*' that might still prefix the assembler name,

51887

+ e.g. in non-LTO runs. */

51888

+

51889

+ name = default_strip_name_encoding (name);

51890

+

51891

/* Silently ignore 'signal' if 'interrupt' is present. AVR-LibC startet

51892

using this when it switched from SIGNAL and INTERRUPT to ISR. */

51893

51894

@@ -6806,8 +6810,8 @@

51895

51896

/* Work out the shortest sequence. */

51897

51898

- avr_out_plus_1 (op, &len_minus, MINUS, &cc_plus, code_sat, sign, out_label);

51899

- avr_out_plus_1 (op, &len_plus, PLUS, &cc_minus, code_sat, sign, out_label);

51900

+ avr_out_plus_1 (op, &len_minus, MINUS, &cc_minus, code_sat, sign, out_label);

51901

+ avr_out_plus_1 (op, &len_plus, PLUS, &cc_plus, code_sat, sign, out_label);

51902

51903

if (plen)

51904

{

51905

Index: gcc/config/cris/cris.md

51906

===================================================================

51907

--- a/src/gcc/config/cris/cris.md (.../tags/gcc_4_8_2_release)

51908

+++ b/src/gcc/config/cris/cris.md (.../branches/gcc-4_8-branch)

51909

@@ -758,7 +758,7 @@

51910

(match_operand:SI 1 "const_int_operand" ""))

51911

(match_operand:SI 2 "register_operand" ""))])

51912

(match_operand 3 "register_operand" ""))

51913

- (set (match_operand:SI 4 "register_operand" "")

51914

+ (set (match_operand:SI 4 "cris_nonsp_register_operand" "")

51915

(plus:SI (mult:SI (match_dup 0)

51916

(match_dup 1))

51917

(match_dup 2)))])]

51918

@@ -859,7 +859,7 @@

51919

(match_operand:SI 0 "cris_bdap_operand" "")

51920

(match_operand:SI 1 "cris_bdap_operand" ""))])

51921

(match_operand 2 "register_operand" ""))

51922

- (set (match_operand:SI 3 "register_operand" "")

51923

+ (set (match_operand:SI 3 "cris_nonsp_register_operand" "")

51924

(plus:SI (match_dup 0) (match_dup 1)))])]

51925

"reload_completed && reg_overlap_mentioned_p (operands[3], operands[2])"

51926

[(set (match_dup 4) (match_dup 2))

51927

@@ -3960,7 +3960,7 @@

51928

;; up.

51929

51930

(define_split

51931

- [(set (match_operand 0 "register_operand" "")

51932

+ [(set (match_operand 0 "cris_nonsp_register_operand" "")

51933

(match_operator

51934

4 "cris_operand_extend_operator"

51935

[(match_operand 1 "register_operand" "")

51936

@@ -3990,7 +3990,7 @@

51937

;; Call this op-extend-split-rx=rz

51938

51939

(define_split

51940

- [(set (match_operand 0 "register_operand" "")

51941

+ [(set (match_operand 0 "cris_nonsp_register_operand" "")

51942

(match_operator

51943

4 "cris_plus_or_bound_operator"

51944

[(match_operand 1 "register_operand" "")

51945

@@ -4018,7 +4018,7 @@

51946

;; Call this op-extend-split-swapped

51947

51948

(define_split

51949

- [(set (match_operand 0 "register_operand" "")

51950

+ [(set (match_operand 0 "cris_nonsp_register_operand" "")

51951

(match_operator

51952

4 "cris_plus_or_bound_operator"

51953

[(match_operator

51954

@@ -4044,7 +4044,7 @@

51955

;; bound. Call this op-extend-split-swapped-rx=rz.

51956

51957

(define_split

51958

- [(set (match_operand 0 "register_operand" "")

51959

+ [(set (match_operand 0 "cris_nonsp_register_operand" "")

51960

(match_operator

51961

4 "cris_plus_or_bound_operator"

51962

[(match_operator

51963

@@ -4075,7 +4075,7 @@

51964

;; Call this op-extend.

51965

51966

(define_split

51967

- [(set (match_operand 0 "register_operand" "")

51968

+ [(set (match_operand 0 "cris_nonsp_register_operand" "")

51969

(match_operator

51970

3 "cris_orthogonal_operator"

51971

[(match_operand 1 "register_operand" "")

51972

@@ -4099,7 +4099,7 @@

51973

;; Call this op-split-rx=rz

51974

51975

(define_split

51976

- [(set (match_operand 0 "register_operand" "")

51977

+ [(set (match_operand 0 "cris_nonsp_register_operand" "")

51978

(match_operator

51979

3 "cris_commutative_orth_op"

51980

[(match_operand 2 "memory_operand" "")

51981

@@ -4123,7 +4123,7 @@

51982

;; Call this op-split-swapped.

51983

51984

(define_split

51985

- [(set (match_operand 0 "register_operand" "")

51986

+ [(set (match_operand 0 "cris_nonsp_register_operand" "")

51987

(match_operator

51988

3 "cris_commutative_orth_op"

51989

[(match_operand 1 "register_operand" "")

51990

@@ -4146,7 +4146,7 @@

51991

;; Call this op-split-swapped-rx=rz.

51992

51993

(define_split

51994

- [(set (match_operand 0 "register_operand" "")

51995

+ [(set (match_operand 0 "cris_nonsp_register_operand" "")

51996

(match_operator

51997

3 "cris_orthogonal_operator"

51998

[(match_operand 2 "memory_operand" "")

51999

@@ -4555,10 +4555,11 @@

52000

;; We're not allowed to generate copies of registers with different mode

52001

;; until after reload; copying pseudos upsets reload. CVS as of

52002

;; 2001-08-24, unwind-dw2-fde.c, _Unwind_Find_FDE ICE in

52003

-;; cselib_invalidate_regno.

52004

+;; cselib_invalidate_regno. Also, don't do this for the stack-pointer,

52005

+;; as we don't want it set temporarily to an invalid value.

52006

52007

(define_split ; indir_to_reg_split

52008

- [(set (match_operand 0 "register_operand" "")

52009

+ [(set (match_operand 0 "cris_nonsp_register_operand" "")

52010

(match_operand 1 "indirect_operand" ""))]

52011

"reload_completed

52012

&& REG_P (operands[0])

52013

@@ -4574,7 +4575,7 @@

52014

;; As the above, but MOVS and MOVU.

52015

52016

(define_split

52017

- [(set (match_operand 0 "register_operand" "")

52018

+ [(set (match_operand 0 "cris_nonsp_register_operand" "")

52019

(match_operator

52020

4 "cris_extend_operator"

52021

[(match_operand 1 "indirect_operand" "")]))]

52022

Index: gcc/config/cris/predicates.md

52023

===================================================================

52024

--- a/src/gcc/config/cris/predicates.md (.../tags/gcc_4_8_2_release)

52025

+++ b/src/gcc/config/cris/predicates.md (.../branches/gcc-4_8-branch)

52026

@@ -76,6 +76,10 @@

52027

(match_test "cris_simple_address_operand (XEXP (op, 0),

52028

Pmode)"))))

52029

52030

+(define_predicate "cris_nonsp_register_operand"

52031

+ (and (match_operand 0 "register_operand")

52032

+ (match_test "op != stack_pointer_rtx")))

52033

+

52034

;; The caller needs to use :SI.

52035

(define_predicate "cris_bdap_sign_extend_operand"

52036

; Disabled until <URL:http://gcc.gnu.org/ml/gcc-patches/2005-10/msg01376.html>

52037

Index: gcc/config/m68k/m68k.c

52038

===================================================================

52039

--- a/src/gcc/config/m68k/m68k.c (.../tags/gcc_4_8_2_release)

52040

+++ b/src/gcc/config/m68k/m68k.c (.../branches/gcc-4_8-branch)

52041

@@ -3325,12 +3325,12 @@

52042

latehalf[1] = adjust_address (operands[1], SImode, 0);

52043

}

52044

52045

- /* If insn is effectively movd N(sp),-(sp) then we will do the

52046

- high word first. We should use the adjusted operand 1 (which is N+4(sp))

52047

- for the low word as well, to compensate for the first decrement of sp. */

52048

+ /* If insn is effectively movd N(REG),-(REG) then we will do the high

52049

+ word first. We should use the adjusted operand 1 (which is N+4(REG))

52050

+ for the low word as well, to compensate for the first decrement of

52051

+ REG. */

52052

if (optype0 == PUSHOP

52053

- && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM

52054

- && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))

52055

+ && reg_overlap_mentioned_p (XEXP (XEXP (operands[0], 0), 0), operands[1]))

52056

operands[1] = middlehalf[1] = latehalf[1];

52057

52058

/* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),

52059

Index: gcc/config/aarch64/aarch64-simd.md

52060

===================================================================

52061

--- a/src/gcc/config/aarch64/aarch64-simd.md (.../tags/gcc_4_8_2_release)

52062

+++ b/src/gcc/config/aarch64/aarch64-simd.md (.../branches/gcc-4_8-branch)

52063

@@ -21,7 +21,7 @@

52064

52065

; Main data types used by the insntructions

52066

52067

-(define_attr "simd_mode" "unknown,none,V8QI,V16QI,V4HI,V8HI,V2SI,V4SI,V2DI,V2SF,V4SF,V2DF,OI,CI,XI,DI,DF,SI,HI,QI"

52068

+(define_attr "simd_mode" "unknown,none,V8QI,V16QI,V4HI,V8HI,V2SI,V4SI,V2DI,V2SF,V4SF,V2DF,OI,CI,XI,DI,DF,SI,SF,HI,QI"

52069

(const_string "unknown"))

52070

52071

52072

@@ -1548,12 +1548,12 @@

52073

52074

case LTU:

52075

case GEU:

52076

- emit_insn (gen_aarch64_cmhs<mode> (mask, operands[4], operands[5]));

52077

+ emit_insn (gen_aarch64_cmgeu<mode> (mask, operands[4], operands[5]));

52078

break;

52079

52080

case LEU:

52081

case GTU:

52082

- emit_insn (gen_aarch64_cmhi<mode> (mask, operands[4], operands[5]));

52083

+ emit_insn (gen_aarch64_cmgtu<mode> (mask, operands[4], operands[5]));

52084

break;

52085

52086

case NE:

52087

@@ -3034,48 +3034,181 @@

52088

)

52089

52090

52091

-;; cm(eq|ge|le|lt|gt)

52092

+;; cm(eq|ge|gt|lt|le)

52093

+;; Note, we have constraints for Dz and Z as different expanders

52094

+;; have different ideas of what should be passed to this pattern.

52095

52096

-(define_insn "aarch64_cm<cmp><mode>"

52097

+(define_insn "aarch64_cm<optab><mode>"

52098

[(set (match_operand:<V_cmp_result> 0 "register_operand" "=w,w")

52099

- (unspec:<V_cmp_result>

52100

- [(match_operand:VSDQ_I_DI 1 "register_operand" "w,w")

52101

- (match_operand:VSDQ_I_DI 2 "aarch64_simd_reg_or_zero" "w,Z")]

52102

- VCMP_S))]

52103

+ (neg:<V_cmp_result>

52104

+ (COMPARISONS:<V_cmp_result>

52105

+ (match_operand:VDQ 1 "register_operand" "w,w")

52106

+ (match_operand:VDQ 2 "aarch64_simd_reg_or_zero" "w,ZDz")

52107

+ )))]

52108

"TARGET_SIMD"

52109

"@

52110

- cm<cmp>\t%<v>0<Vmtype>, %<v>1<Vmtype>, %<v>2<Vmtype>

52111

- cm<cmp>\t%<v>0<Vmtype>, %<v>1<Vmtype>, #0"

52112

+ cm<n_optab>\t%<v>0<Vmtype>, %<v><cmp_1><Vmtype>, %<v><cmp_2><Vmtype>

52113

+ cm<optab>\t%<v>0<Vmtype>, %<v>1<Vmtype>, #0"

52114

[(set_attr "simd_type" "simd_cmp")

52115

(set_attr "simd_mode" "<MODE>")]

52116

)

52117

52118

-;; cm(hs|hi|tst)

52119

+(define_insn_and_split "aarch64_cm<optab>di"

52120

+ [(set (match_operand:DI 0 "register_operand" "=w,w,r")

52121

+ (neg:DI

52122

+ (COMPARISONS:DI

52123

+ (match_operand:DI 1 "register_operand" "w,w,r")

52124

+ (match_operand:DI 2 "aarch64_simd_reg_or_zero" "w,ZDz,r")

52125

+ )))]

52126

+ "TARGET_SIMD"

52127

+ "@

52128

+ cm<n_optab>\t%d0, %d<cmp_1>, %d<cmp_2>

52129

+ cm<optab>\t%d0, %d1, #0

52130

+ #"

52131

+ "reload_completed

52132

+ /* We need to prevent the split from

52133

+ happening in the 'w' constraint cases. */

52134

+ && GP_REGNUM_P (REGNO (operands[0]))

52135

+ && GP_REGNUM_P (REGNO (operands[1]))"

52136

+ [(set (reg:CC CC_REGNUM)

52137

+ (compare:CC

52138

+ (match_dup 1)

52139

+ (match_dup 2)))

52140

+ (set (match_dup 0)

52141

+ (neg:DI

52142

+ (COMPARISONS:DI

52143

+ (match_operand 3 "cc_register" "")

52144

+ (const_int 0))))]

52145

+ {

52146

+ enum machine_mode mode = SELECT_CC_MODE (<CMP>, operands[1], operands[2]);

52147

+ rtx cc_reg = aarch64_gen_compare_reg (<CMP>, operands[1], operands[2]);

52148

+ rtx comparison = gen_rtx_<CMP> (mode, operands[1], operands[2]);

52149

+ emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg));

52150

+ DONE;

52151

+ }

52152

+ [(set_attr "simd_type" "simd_cmp")

52153

+ (set_attr "simd_mode" "DI")]

52154

+)

52155

52156

-(define_insn "aarch64_cm<cmp><mode>"

52157

+;; cm(hs|hi)

52158

+

52159

+(define_insn "aarch64_cm<optab><mode>"

52160

[(set (match_operand:<V_cmp_result> 0 "register_operand" "=w")

52161

- (unspec:<V_cmp_result>

52162

- [(match_operand:VSDQ_I_DI 1 "register_operand" "w")

52163

- (match_operand:VSDQ_I_DI 2 "register_operand" "w")]

52164

- VCMP_U))]

52165

+ (neg:<V_cmp_result>

52166

+ (UCOMPARISONS:<V_cmp_result>

52167

+ (match_operand:VDQ 1 "register_operand" "w")

52168

+ (match_operand:VDQ 2 "register_operand" "w")

52169

+ )))]

52170

"TARGET_SIMD"

52171

- "cm<cmp>\t%<v>0<Vmtype>, %<v>1<Vmtype>, %<v>2<Vmtype>"

52172

+ "cm<n_optab>\t%<v>0<Vmtype>, %<v><cmp_1><Vmtype>, %<v><cmp_2><Vmtype>"

52173

[(set_attr "simd_type" "simd_cmp")

52174

(set_attr "simd_mode" "<MODE>")]

52175

)

52176

52177

-;; fcm(eq|ge|le|lt|gt)

52178

+(define_insn_and_split "aarch64_cm<optab>di"

52179

+ [(set (match_operand:DI 0 "register_operand" "=w,r")

52180

+ (neg:DI

52181

+ (UCOMPARISONS:DI

52182

+ (match_operand:DI 1 "register_operand" "w,r")

52183

+ (match_operand:DI 2 "aarch64_simd_reg_or_zero" "w,r")

52184

+ )))]

52185

+ "TARGET_SIMD"

52186

+ "@

52187

+ cm<n_optab>\t%d0, %d<cmp_1>, %d<cmp_2>

52188

+ #"

52189

+ "reload_completed

52190

+ /* We need to prevent the split from

52191

+ happening in the 'w' constraint cases. */

52192

+ && GP_REGNUM_P (REGNO (operands[0]))

52193

+ && GP_REGNUM_P (REGNO (operands[1]))"

52194

+ [(set (reg:CC CC_REGNUM)

52195

+ (compare:CC

52196

+ (match_dup 1)

52197

+ (match_dup 2)))

52198

+ (set (match_dup 0)

52199

+ (neg:DI

52200

+ (UCOMPARISONS:DI

52201

+ (match_operand 3 "cc_register" "")

52202

+ (const_int 0))))]

52203

+ {

52204

+ enum machine_mode mode = SELECT_CC_MODE (<CMP>, operands[1], operands[2]);

52205

+ rtx cc_reg = aarch64_gen_compare_reg (<CMP>, operands[1], operands[2]);

52206

+ rtx comparison = gen_rtx_<CMP> (mode, operands[1], operands[2]);

52207

+ emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg));

52208

+ DONE;

52209

+ }

52210

+ [(set_attr "simd_type" "simd_cmp")

52211

+ (set_attr "simd_mode" "DI")]

52212

+)

52213

52214

-(define_insn "aarch64_cm<cmp><mode>"

52215

+;; cmtst

52216

+

52217

+(define_insn "aarch64_cmtst<mode>"

52218

+ [(set (match_operand:<V_cmp_result> 0 "register_operand" "=w")

52219

+ (neg:<V_cmp_result>

52220

+ (ne:<V_cmp_result>

52221

+ (and:VDQ

52222

+ (match_operand:VDQ 1 "register_operand" "w")

52223

+ (match_operand:VDQ 2 "register_operand" "w"))

52224

+ (vec_duplicate:<V_cmp_result> (const_int 0)))))]

52225

+ "TARGET_SIMD"

52226

+ "cmtst\t%<v>0<Vmtype>, %<v>1<Vmtype>, %<v>2<Vmtype>"

52227

+ [(set_attr "simd_type" "simd_cmp")

52228

+ (set_attr "simd_mode" "<MODE>")]

52229

+)

52230

+

52231

+(define_insn_and_split "aarch64_cmtstdi"

52232

+ [(set (match_operand:DI 0 "register_operand" "=w,r")

52233

+ (neg:DI

52234

+ (ne:DI

52235

+ (and:DI

52236

+ (match_operand:DI 1 "register_operand" "w,r")

52237

+ (match_operand:DI 2 "register_operand" "w,r"))

52238

+ (const_int 0))))]

52239

+ "TARGET_SIMD"

52240

+ "@

52241

+ cmtst\t%d0, %d1, %d2

52242

+ #"

52243

+ "reload_completed

52244

+ /* We need to prevent the split from

52245

+ happening in the 'w' constraint cases. */

52246

+ && GP_REGNUM_P (REGNO (operands[0]))

52247

+ && GP_REGNUM_P (REGNO (operands[1]))"

52248

+ [(set (reg:CC_NZ CC_REGNUM)

52249

+ (compare:CC_NZ

52250

+ (and:DI (match_dup 1)

52251

+ (match_dup 2))

52252

+ (const_int 0)))

52253

+ (set (match_dup 0)

52254

+ (neg:DI

52255

+ (ne:DI

52256

+ (match_operand 3 "cc_register" "")

52257

+ (const_int 0))))]

52258

+ {

52259

+ rtx and_tree = gen_rtx_AND (DImode, operands[1], operands[2]);

52260

+ enum machine_mode mode = SELECT_CC_MODE (NE, and_tree, const0_rtx);

52261

+ rtx cc_reg = aarch64_gen_compare_reg (NE, and_tree, const0_rtx);

52262

+ rtx comparison = gen_rtx_NE (mode, and_tree, const0_rtx);

52263

+ emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg));

52264

+ DONE;

52265

+ }

52266

+ [(set_attr "simd_type" "simd_cmp")

52267

+ (set_attr "simd_mode" "DI")]

52268

+)

52269

+

52270

+;; fcm(eq|ge|gt|le|lt)

52271

+

52272

+(define_insn "aarch64_cm<optab><mode>"

52273

[(set (match_operand:<V_cmp_result> 0 "register_operand" "=w,w")

52274

- (unspec:<V_cmp_result>

52275

- [(match_operand:VDQF 1 "register_operand" "w,w")

52276

- (match_operand:VDQF 2 "aarch64_simd_reg_or_zero" "w,Dz")]

52277

- VCMP_S))]

52278

+ (neg:<V_cmp_result>

52279

+ (COMPARISONS:<V_cmp_result>

52280

+ (match_operand:VALLF 1 "register_operand" "w,w")

52281

+ (match_operand:VALLF 2 "aarch64_simd_reg_or_zero" "w,YDz")

52282

+ )))]

52283

"TARGET_SIMD"

52284

"@

52285

- fcm<cmp>\t%<v>0<Vmtype>, %<v>1<Vmtype>, %<v>2<Vmtype>

52286

- fcm<cmp>\t%<v>0<Vmtype>, %<v>1<Vmtype>, 0"

52287

+ fcm<n_optab>\t%<v>0<Vmtype>, %<v><cmp_1><Vmtype>, %<v><cmp_2><Vmtype>

52288

+ fcm<optab>\t%<v>0<Vmtype>, %<v>1<Vmtype>, 0"

52289

[(set_attr "simd_type" "simd_fcmp")

52290

(set_attr "simd_mode" "<MODE>")]

52291

)

52292

Index: gcc/config/aarch64/predicates.md

52293

===================================================================

52294

--- a/src/gcc/config/aarch64/predicates.md (.../tags/gcc_4_8_2_release)

52295

+++ b/src/gcc/config/aarch64/predicates.md (.../branches/gcc-4_8-branch)

52296

@@ -31,6 +31,11 @@

52297

(ior (match_operand 0 "register_operand")

52298

(match_test "op == const0_rtx"))))

52299

52300

+(define_predicate "aarch64_reg_or_fp_zero"

52301

+ (and (match_code "reg,subreg,const_double")

52302

+ (ior (match_operand 0 "register_operand")

52303

+ (match_test "aarch64_float_const_zero_rtx_p (op)"))))

52304

+

52305

(define_predicate "aarch64_reg_zero_or_m1_or_1"

52306

(and (match_code "reg,subreg,const_int")

52307

(ior (match_operand 0 "register_operand")

52308

Index: gcc/config/aarch64/arm_neon.h

52309

===================================================================

52310

--- a/src/gcc/config/aarch64/arm_neon.h (.../tags/gcc_4_8_2_release)

52311

+++ b/src/gcc/config/aarch64/arm_neon.h (.../branches/gcc-4_8-branch)

52312

@@ -19551,7 +19551,7 @@

52313

__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))

52314

vcge_u8 (uint8x8_t __a, uint8x8_t __b)

52315

{

52316

- return (uint8x8_t) __builtin_aarch64_cmhsv8qi ((int8x8_t) __a,

52317

+ return (uint8x8_t) __builtin_aarch64_cmgeuv8qi ((int8x8_t) __a,

52318

(int8x8_t) __b);

52319

}

52320

52321

@@ -19558,7 +19558,7 @@

52322

__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))

52323

vcge_u16 (uint16x4_t __a, uint16x4_t __b)

52324

{

52325

- return (uint16x4_t) __builtin_aarch64_cmhsv4hi ((int16x4_t) __a,

52326

+ return (uint16x4_t) __builtin_aarch64_cmgeuv4hi ((int16x4_t) __a,

52327

(int16x4_t) __b);

52328

}

52329

52330

@@ -19565,7 +19565,7 @@

52331

__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))

52332

vcge_u32 (uint32x2_t __a, uint32x2_t __b)

52333

{

52334

- return (uint32x2_t) __builtin_aarch64_cmhsv2si ((int32x2_t) __a,

52335

+ return (uint32x2_t) __builtin_aarch64_cmgeuv2si ((int32x2_t) __a,

52336

(int32x2_t) __b);

52337

}

52338

52339

@@ -19572,7 +19572,7 @@

52340

__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))

52341

vcge_u64 (uint64x1_t __a, uint64x1_t __b)

52342

{

52343

- return (uint64x1_t) __builtin_aarch64_cmhsdi ((int64x1_t) __a,

52344

+ return (uint64x1_t) __builtin_aarch64_cmgeudi ((int64x1_t) __a,

52345

(int64x1_t) __b);

52346

}

52347

52348

@@ -19603,7 +19603,7 @@

52349

__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))

52350

vcgeq_u8 (uint8x16_t __a, uint8x16_t __b)

52351

{

52352

- return (uint8x16_t) __builtin_aarch64_cmhsv16qi ((int8x16_t) __a,

52353

+ return (uint8x16_t) __builtin_aarch64_cmgeuv16qi ((int8x16_t) __a,

52354

(int8x16_t) __b);

52355

}

52356

52357

@@ -19610,7 +19610,7 @@

52358

__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))

52359

vcgeq_u16 (uint16x8_t __a, uint16x8_t __b)

52360

{

52361

- return (uint16x8_t) __builtin_aarch64_cmhsv8hi ((int16x8_t) __a,

52362

+ return (uint16x8_t) __builtin_aarch64_cmgeuv8hi ((int16x8_t) __a,

52363

(int16x8_t) __b);

52364

}

52365

52366

@@ -19617,7 +19617,7 @@

52367

__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))

52368

vcgeq_u32 (uint32x4_t __a, uint32x4_t __b)

52369

{

52370

- return (uint32x4_t) __builtin_aarch64_cmhsv4si ((int32x4_t) __a,

52371

+ return (uint32x4_t) __builtin_aarch64_cmgeuv4si ((int32x4_t) __a,

52372

(int32x4_t) __b);

52373

}

52374

52375

@@ -19624,7 +19624,7 @@

52376

__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))

52377

vcgeq_u64 (uint64x2_t __a, uint64x2_t __b)

52378

{

52379

- return (uint64x2_t) __builtin_aarch64_cmhsv2di ((int64x2_t) __a,

52380

+ return (uint64x2_t) __builtin_aarch64_cmgeuv2di ((int64x2_t) __a,

52381

(int64x2_t) __b);

52382

}

52383

52384

@@ -19637,7 +19637,7 @@

52385

__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))

52386

vcged_u64 (uint64x1_t __a, uint64x1_t __b)

52387

{

52388

- return (uint64x1_t) __builtin_aarch64_cmhsdi ((int64x1_t) __a,

52389

+ return (uint64x1_t) __builtin_aarch64_cmgeudi ((int64x1_t) __a,

52390

(int64x1_t) __b);

52391

}

52392

52393

@@ -19676,7 +19676,7 @@

52394

__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))

52395

vcgt_u8 (uint8x8_t __a, uint8x8_t __b)

52396

{

52397

- return (uint8x8_t) __builtin_aarch64_cmhiv8qi ((int8x8_t) __a,

52398

+ return (uint8x8_t) __builtin_aarch64_cmgtuv8qi ((int8x8_t) __a,

52399

(int8x8_t) __b);

52400

}

52401

52402

@@ -19683,7 +19683,7 @@

52403

__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))

52404

vcgt_u16 (uint16x4_t __a, uint16x4_t __b)

52405

{

52406

- return (uint16x4_t) __builtin_aarch64_cmhiv4hi ((int16x4_t) __a,

52407

+ return (uint16x4_t) __builtin_aarch64_cmgtuv4hi ((int16x4_t) __a,

52408

(int16x4_t) __b);

52409

}

52410

52411

@@ -19690,7 +19690,7 @@

52412

__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))

52413

vcgt_u32 (uint32x2_t __a, uint32x2_t __b)

52414

{

52415

- return (uint32x2_t) __builtin_aarch64_cmhiv2si ((int32x2_t) __a,

52416

+ return (uint32x2_t) __builtin_aarch64_cmgtuv2si ((int32x2_t) __a,

52417

(int32x2_t) __b);

52418

}

52419

52420

@@ -19697,7 +19697,7 @@

52421

__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))

52422

vcgt_u64 (uint64x1_t __a, uint64x1_t __b)

52423

{

52424

- return (uint64x1_t) __builtin_aarch64_cmhidi ((int64x1_t) __a,

52425

+ return (uint64x1_t) __builtin_aarch64_cmgtudi ((int64x1_t) __a,

52426

(int64x1_t) __b);

52427

}

52428

52429

@@ -19728,7 +19728,7 @@

52430

__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))

52431

vcgtq_u8 (uint8x16_t __a, uint8x16_t __b)

52432

{

52433

- return (uint8x16_t) __builtin_aarch64_cmhiv16qi ((int8x16_t) __a,

52434

+ return (uint8x16_t) __builtin_aarch64_cmgtuv16qi ((int8x16_t) __a,

52435

(int8x16_t) __b);

52436

}

52437

52438

@@ -19735,7 +19735,7 @@

52439

__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))

52440

vcgtq_u16 (uint16x8_t __a, uint16x8_t __b)

52441

{

52442

- return (uint16x8_t) __builtin_aarch64_cmhiv8hi ((int16x8_t) __a,

52443

+ return (uint16x8_t) __builtin_aarch64_cmgtuv8hi ((int16x8_t) __a,

52444

(int16x8_t) __b);

52445

}

52446

52447

@@ -19742,7 +19742,7 @@

52448

__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))

52449

vcgtq_u32 (uint32x4_t __a, uint32x4_t __b)

52450

{

52451

- return (uint32x4_t) __builtin_aarch64_cmhiv4si ((int32x4_t) __a,

52452

+ return (uint32x4_t) __builtin_aarch64_cmgtuv4si ((int32x4_t) __a,

52453

(int32x4_t) __b);

52454

}

52455

52456

@@ -19749,7 +19749,7 @@

52457

__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))

52458

vcgtq_u64 (uint64x2_t __a, uint64x2_t __b)

52459

{

52460

- return (uint64x2_t) __builtin_aarch64_cmhiv2di ((int64x2_t) __a,

52461

+ return (uint64x2_t) __builtin_aarch64_cmgtuv2di ((int64x2_t) __a,

52462

(int64x2_t) __b);

52463

}

52464

52465

@@ -19762,7 +19762,7 @@

52466

__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))

52467

vcgtd_u64 (uint64x1_t __a, uint64x1_t __b)

52468

{

52469

- return (uint64x1_t) __builtin_aarch64_cmhidi ((int64x1_t) __a,

52470

+ return (uint64x1_t) __builtin_aarch64_cmgtudi ((int64x1_t) __a,

52471

(int64x1_t) __b);

52472

}

52473

52474

@@ -19801,7 +19801,7 @@

52475

__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))

52476

vcle_u8 (uint8x8_t __a, uint8x8_t __b)

52477

{

52478

- return (uint8x8_t) __builtin_aarch64_cmhsv8qi ((int8x8_t) __b,

52479

+ return (uint8x8_t) __builtin_aarch64_cmgeuv8qi ((int8x8_t) __b,

52480

(int8x8_t) __a);

52481

}

52482

52483

@@ -19808,7 +19808,7 @@

52484

__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))

52485

vcle_u16 (uint16x4_t __a, uint16x4_t __b)

52486

{

52487

- return (uint16x4_t) __builtin_aarch64_cmhsv4hi ((int16x4_t) __b,

52488

+ return (uint16x4_t) __builtin_aarch64_cmgeuv4hi ((int16x4_t) __b,

52489

(int16x4_t) __a);

52490

}

52491

52492

@@ -19815,7 +19815,7 @@

52493

__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))

52494

vcle_u32 (uint32x2_t __a, uint32x2_t __b)

52495

{

52496

- return (uint32x2_t) __builtin_aarch64_cmhsv2si ((int32x2_t) __b,

52497

+ return (uint32x2_t) __builtin_aarch64_cmgeuv2si ((int32x2_t) __b,

52498

(int32x2_t) __a);

52499

}

52500

52501

@@ -19822,7 +19822,7 @@

52502

__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))

52503

vcle_u64 (uint64x1_t __a, uint64x1_t __b)

52504

{

52505

- return (uint64x1_t) __builtin_aarch64_cmhsdi ((int64x1_t) __b,

52506

+ return (uint64x1_t) __builtin_aarch64_cmgeudi ((int64x1_t) __b,

52507

(int64x1_t) __a);

52508

}

52509

52510

@@ -19853,7 +19853,7 @@

52511

__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))

52512

vcleq_u8 (uint8x16_t __a, uint8x16_t __b)

52513

{

52514

- return (uint8x16_t) __builtin_aarch64_cmhsv16qi ((int8x16_t) __b,

52515

+ return (uint8x16_t) __builtin_aarch64_cmgeuv16qi ((int8x16_t) __b,

52516

(int8x16_t) __a);

52517

}

52518

52519

@@ -19860,7 +19860,7 @@

52520

__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))

52521

vcleq_u16 (uint16x8_t __a, uint16x8_t __b)

52522

{

52523

- return (uint16x8_t) __builtin_aarch64_cmhsv8hi ((int16x8_t) __b,

52524

+ return (uint16x8_t) __builtin_aarch64_cmgeuv8hi ((int16x8_t) __b,

52525

(int16x8_t) __a);

52526

}

52527

52528

@@ -19867,7 +19867,7 @@

52529

__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))

52530

vcleq_u32 (uint32x4_t __a, uint32x4_t __b)

52531

{

52532

- return (uint32x4_t) __builtin_aarch64_cmhsv4si ((int32x4_t) __b,

52533

+ return (uint32x4_t) __builtin_aarch64_cmgeuv4si ((int32x4_t) __b,

52534

(int32x4_t) __a);

52535

}

52536

52537

@@ -19874,7 +19874,7 @@

52538

__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))

52539

vcleq_u64 (uint64x2_t __a, uint64x2_t __b)

52540

{

52541

- return (uint64x2_t) __builtin_aarch64_cmhsv2di ((int64x2_t) __b,

52542

+ return (uint64x2_t) __builtin_aarch64_cmgeuv2di ((int64x2_t) __b,

52543

(int64x2_t) __a);

52544

}

52545

52546

@@ -19919,7 +19919,7 @@

52547

__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))

52548

vclt_u8 (uint8x8_t __a, uint8x8_t __b)

52549

{

52550

- return (uint8x8_t) __builtin_aarch64_cmhiv8qi ((int8x8_t) __b,

52551

+ return (uint8x8_t) __builtin_aarch64_cmgtuv8qi ((int8x8_t) __b,

52552

(int8x8_t) __a);

52553

}

52554

52555

@@ -19926,7 +19926,7 @@

52556

__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))

52557

vclt_u16 (uint16x4_t __a, uint16x4_t __b)

52558

{

52559

- return (uint16x4_t) __builtin_aarch64_cmhiv4hi ((int16x4_t) __b,

52560

+ return (uint16x4_t) __builtin_aarch64_cmgtuv4hi ((int16x4_t) __b,

52561

(int16x4_t) __a);

52562

}

52563

52564

@@ -19933,7 +19933,7 @@

52565

__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))

52566

vclt_u32 (uint32x2_t __a, uint32x2_t __b)

52567

{

52568

- return (uint32x2_t) __builtin_aarch64_cmhiv2si ((int32x2_t) __b,

52569

+ return (uint32x2_t) __builtin_aarch64_cmgtuv2si ((int32x2_t) __b,

52570

(int32x2_t) __a);

52571

}

52572

52573

@@ -19940,7 +19940,7 @@

52574

__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))

52575

vclt_u64 (uint64x1_t __a, uint64x1_t __b)

52576

{

52577

- return (uint64x1_t) __builtin_aarch64_cmhidi ((int64x1_t) __b,

52578

+ return (uint64x1_t) __builtin_aarch64_cmgtudi ((int64x1_t) __b,

52579

(int64x1_t) __a);

52580

}

52581

52582

@@ -19971,7 +19971,7 @@

52583

__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))

52584

vcltq_u8 (uint8x16_t __a, uint8x16_t __b)

52585

{

52586

- return (uint8x16_t) __builtin_aarch64_cmhiv16qi ((int8x16_t) __b,

52587

+ return (uint8x16_t) __builtin_aarch64_cmgtuv16qi ((int8x16_t) __b,

52588

(int8x16_t) __a);

52589

}

52590

52591

@@ -19978,7 +19978,7 @@

52592

__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))

52593

vcltq_u16 (uint16x8_t __a, uint16x8_t __b)

52594

{

52595

- return (uint16x8_t) __builtin_aarch64_cmhiv8hi ((int16x8_t) __b,

52596

+ return (uint16x8_t) __builtin_aarch64_cmgtuv8hi ((int16x8_t) __b,

52597

(int16x8_t) __a);

52598

}

52599

52600

@@ -19985,7 +19985,7 @@

52601

__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))

52602

vcltq_u32 (uint32x4_t __a, uint32x4_t __b)

52603

{

52604

- return (uint32x4_t) __builtin_aarch64_cmhiv4si ((int32x4_t) __b,

52605

+ return (uint32x4_t) __builtin_aarch64_cmgtuv4si ((int32x4_t) __b,

52606

(int32x4_t) __a);

52607

}

52608

52609

@@ -19992,7 +19992,7 @@

52610

__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))

52611

vcltq_u64 (uint64x2_t __a, uint64x2_t __b)

52612

{

52613

- return (uint64x2_t) __builtin_aarch64_cmhiv2di ((int64x2_t) __b,

52614

+ return (uint64x2_t) __builtin_aarch64_cmgtuv2di ((int64x2_t) __b,

52615

(int64x2_t) __a);

52616

}

52617

52618

Index: gcc/config/aarch64/aarch64.md

52619

===================================================================

52620

--- a/src/gcc/config/aarch64/aarch64.md (.../tags/gcc_4_8_2_release)

52621

+++ b/src/gcc/config/aarch64/aarch64.md (.../branches/gcc-4_8-branch)

52622

@@ -2211,7 +2211,7 @@

52623

(set_attr "mode" "SI")]

52624

)

52625

52626

-(define_insn "*cstore<mode>_neg"

52627

+(define_insn "cstore<mode>_neg"

52628

[(set (match_operand:ALLI 0 "register_operand" "=r")

52629

(neg:ALLI (match_operator:ALLI 1 "aarch64_comparison_operator"

52630

[(match_operand 2 "cc_register" "") (const_int 0)])))]

52631

Index: gcc/config/aarch64/aarch64-simd-builtins.def

52632

===================================================================

52633

--- a/src/gcc/config/aarch64/aarch64-simd-builtins.def (.../tags/gcc_4_8_2_release)

52634

+++ b/src/gcc/config/aarch64/aarch64-simd-builtins.def (.../branches/gcc-4_8-branch)

52635

@@ -217,8 +217,8 @@

52636

BUILTIN_VSDQ_I_DI (BINOP, cmle)

52637

BUILTIN_VSDQ_I_DI (BINOP, cmlt)

52638

/* Implemented by aarch64_cm<cmp><mode>. */

52639

- BUILTIN_VSDQ_I_DI (BINOP, cmhs)

52640

- BUILTIN_VSDQ_I_DI (BINOP, cmhi)

52641

+ BUILTIN_VSDQ_I_DI (BINOP, cmgeu)

52642

+ BUILTIN_VSDQ_I_DI (BINOP, cmgtu)

52643

BUILTIN_VSDQ_I_DI (BINOP, cmtst)

52644

52645

/* Implemented by aarch64_<fmaxmin><mode>. */

52646

Index: gcc/config/aarch64/aarch64.c

52647

===================================================================

52648

--- a/src/gcc/config/aarch64/aarch64.c (.../tags/gcc_4_8_2_release)

52649

+++ b/src/gcc/config/aarch64/aarch64.c (.../branches/gcc-4_8-branch)

52650

@@ -2274,7 +2274,7 @@

52651

if (ncount < zcount)

52652

{

52653

emit_move_insn (gen_rtx_REG (Pmode, regnum),

52654

- GEN_INT ((~val) & 0xffff));

52655

+ GEN_INT (val | ~(HOST_WIDE_INT) 0xffff));

52656

tval = 0xffff;

52657

}

52658

else

52659

@@ -4568,9 +4568,11 @@

52660

}

52661

52662

static int

52663

-aarch64_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,

52664

- reg_class_t from, reg_class_t to)

52665

+aarch64_register_move_cost (enum machine_mode mode,

52666

+ reg_class_t from_i, reg_class_t to_i)

52667

{

52668

+ enum reg_class from = (enum reg_class) from_i;

52669

+ enum reg_class to = (enum reg_class) to_i;

52670

const struct cpu_regmove_cost *regmove_cost

52671

= aarch64_tune_params->regmove_cost;

52672

52673

@@ -4586,8 +4588,7 @@

52674

secondary reload. A general register is used as a scratch to move

52675

the upper DI value and the lower DI value is moved directly,

52676

hence the cost is the sum of three moves. */

52677

-

52678

- if (! TARGET_SIMD && GET_MODE_SIZE (from) == 128 && GET_MODE_SIZE (to) == 128)

52679

+ if (! TARGET_SIMD && GET_MODE_SIZE (mode) == 128)

52680

return regmove_cost->GP2FP + regmove_cost->FP2GP + regmove_cost->FP2FP;

52681

52682

return regmove_cost->FP2FP;

52683

Index: gcc/config/aarch64/iterators.md

52684

===================================================================

52685

--- a/src/gcc/config/aarch64/iterators.md (.../tags/gcc_4_8_2_release)

52686

+++ b/src/gcc/config/aarch64/iterators.md (.../branches/gcc-4_8-branch)

52687

@@ -83,6 +83,9 @@

52688

;; Vector Float modes.

52689

(define_mode_iterator VDQF [V2SF V4SF V2DF])

52690

52691

+;; All Float modes.

52692

+(define_mode_iterator VALLF [V2SF V4SF V2DF SF DF])

52693

+

52694

;; Vector Float modes with 2 elements.

52695

(define_mode_iterator V2F [V2SF V2DF])

52696

52697

@@ -213,13 +216,6 @@

52698

UNSPEC_URSHL ; Used in aarch64-simd.md.

52699

UNSPEC_SQRSHL ; Used in aarch64-simd.md.

52700

UNSPEC_UQRSHL ; Used in aarch64-simd.md.

52701

- UNSPEC_CMEQ ; Used in aarch64-simd.md.

52702

- UNSPEC_CMLE ; Used in aarch64-simd.md.

52703

- UNSPEC_CMLT ; Used in aarch64-simd.md.

52704

- UNSPEC_CMGE ; Used in aarch64-simd.md.

52705

- UNSPEC_CMGT ; Used in aarch64-simd.md.

52706

- UNSPEC_CMHS ; Used in aarch64-simd.md.

52707

- UNSPEC_CMHI ; Used in aarch64-simd.md.

52708

UNSPEC_SSLI ; Used in aarch64-simd.md.

52709

UNSPEC_USLI ; Used in aarch64-simd.md.

52710

UNSPEC_SSRI ; Used in aarch64-simd.md.

52711

@@ -227,7 +223,6 @@

52712

UNSPEC_SSHLL ; Used in aarch64-simd.md.

52713

UNSPEC_USHLL ; Used in aarch64-simd.md.

52714

UNSPEC_ADDP ; Used in aarch64-simd.md.

52715

- UNSPEC_CMTST ; Used in aarch64-simd.md.

52716

UNSPEC_FMAX ; Used in aarch64-simd.md.

52717

UNSPEC_FMIN ; Used in aarch64-simd.md.

52718

UNSPEC_BSL ; Used in aarch64-simd.md.

52719

@@ -251,6 +246,7 @@

52720

52721

;; For scalar usage of vector/FP registers

52722

(define_mode_attr v [(QI "b") (HI "h") (SI "s") (DI "d")

52723

+ (SF "s") (DF "d")

52724

(V8QI "") (V16QI "")

52725

(V4HI "") (V8HI "")

52726

(V2SI "") (V4SI "")

52727

@@ -305,7 +301,8 @@

52728

(V4SF ".4s") (V2DF ".2d")

52729

(DI "") (SI "")

52730

(HI "") (QI "")

52731

- (TI "")])

52732

+ (TI "") (SF "")

52733

+ (DF "")])

52734

52735

;; Register suffix narrowed modes for VQN.

52736

(define_mode_attr Vmntype [(V8HI ".8b") (V4SI ".4h")

52737

@@ -444,7 +441,8 @@

52738

(V2SI "V2SI") (V4SI "V4SI")

52739

(DI "DI") (V2DI "V2DI")

52740

(V2SF "V2SI") (V4SF "V4SI")

52741

- (V2DF "V2DI")])

52742

+ (V2DF "V2DI") (DF "DI")

52743

+ (SF "SI")])

52744

52745

;; Lower case mode of results of comparison operations.

52746

(define_mode_attr v_cmp_result [(V8QI "v8qi") (V16QI "v16qi")

52747

@@ -452,7 +450,8 @@

52748

(V2SI "v2si") (V4SI "v4si")

52749

(DI "di") (V2DI "v2di")

52750

(V2SF "v2si") (V4SF "v4si")

52751

- (V2DF "v2di")])

52752

+ (V2DF "v2di") (DF "di")

52753

+ (SF "si")])

52754

52755

;; Vm for lane instructions is restricted to FP_LO_REGS.

52756

(define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x")

52757

@@ -543,6 +542,12 @@

52758

;; Code iterator for signed variants of vector saturating binary ops.

52759

(define_code_iterator SBINQOPS [ss_plus ss_minus])

52760

52761

+;; Comparison operators for <F>CM.

52762

+(define_code_iterator COMPARISONS [lt le eq ge gt])

52763

+

52764

+;; Unsigned comparison operators.

52765

+(define_code_iterator UCOMPARISONS [ltu leu geu gtu])

52766

+

52767

;; -------------------------------------------------------------------

52768

;; Code Attributes

52769

;; -------------------------------------------------------------------

52770

@@ -571,8 +576,29 @@

52771

(eq "eq")

52772

(ne "ne")

52773

(lt "lt")

52774

- (ge "ge")])

52775

+ (ge "ge")

52776

+ (le "le")

52777

+ (gt "gt")

52778

+ (ltu "ltu")

52779

+ (leu "leu")

52780

+ (geu "geu")

52781

+ (gtu "gtu")])

52782

52783

+;; For comparison operators we use the FCM* and CM* instructions.

52784

+;; As there are no CMLE or CMLT instructions which act on 3 vector

52785

+;; operands, we must use CMGE or CMGT and swap the order of the

52786

+;; source operands.

52787

+

52788

+(define_code_attr n_optab [(lt "gt") (le "ge") (eq "eq") (ge "ge") (gt "gt")

52789

+ (ltu "hi") (leu "hs") (geu "hs") (gtu "hi")])

52790

+(define_code_attr cmp_1 [(lt "2") (le "2") (eq "1") (ge "1") (gt "1")

52791

+ (ltu "2") (leu "2") (geu "1") (gtu "1")])

52792

+(define_code_attr cmp_2 [(lt "1") (le "1") (eq "2") (ge "2") (gt "2")

52793

+ (ltu "1") (leu "1") (geu "2") (gtu "2")])

52794

+

52795

+(define_code_attr CMP [(lt "LT") (le "LE") (eq "EQ") (ge "GE") (gt "GT")

52796

+ (ltu "LTU") (leu "LEU") (geu "GEU") (gtu "GTU")])

52797

+

52798

;; Optab prefix for sign/zero-extending operations

52799

(define_code_attr su_optab [(sign_extend "") (zero_extend "u")

52800

(div "") (udiv "u")

52801

@@ -680,11 +706,6 @@

52802

UNSPEC_SQSHRN UNSPEC_UQSHRN

52803

UNSPEC_SQRSHRN UNSPEC_UQRSHRN])

52804

52805

-(define_int_iterator VCMP_S [UNSPEC_CMEQ UNSPEC_CMGE UNSPEC_CMGT

52806

- UNSPEC_CMLE UNSPEC_CMLT])

52807

-

52808

-(define_int_iterator VCMP_U [UNSPEC_CMHS UNSPEC_CMHI UNSPEC_CMTST])

52809

-

52810

(define_int_iterator PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2

52811

UNSPEC_TRN1 UNSPEC_TRN2

52812

UNSPEC_UZP1 UNSPEC_UZP2])

52813

@@ -768,12 +789,6 @@

52814

(UNSPEC_RADDHN2 "add")

52815

(UNSPEC_RSUBHN2 "sub")])

52816

52817

-(define_int_attr cmp [(UNSPEC_CMGE "ge") (UNSPEC_CMGT "gt")

52818

- (UNSPEC_CMLE "le") (UNSPEC_CMLT "lt")

52819

- (UNSPEC_CMEQ "eq")

52820

- (UNSPEC_CMHS "hs") (UNSPEC_CMHI "hi")

52821

- (UNSPEC_CMTST "tst")])

52822

-

52823

(define_int_attr offsetlr [(UNSPEC_SSLI "1") (UNSPEC_USLI "1")

52824

(UNSPEC_SSRI "0") (UNSPEC_USRI "0")])

52825

52826

Index: gcc/config/aarch64/aarch64.h

52827

===================================================================

52828

--- a/src/gcc/config/aarch64/aarch64.h (.../tags/gcc_4_8_2_release)

52829

+++ b/src/gcc/config/aarch64/aarch64.h (.../branches/gcc-4_8-branch)

52830

@@ -73,9 +73,9 @@

52831

#define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN)

52832

52833

/* AdvSIMD is supported in the default configuration, unless disabled by

52834

- -mgeneral-regs-only. */

52835

-#define TARGET_SIMD !TARGET_GENERAL_REGS_ONLY

52836

-#define TARGET_FLOAT !TARGET_GENERAL_REGS_ONLY

52837

+ -mgeneral-regs-only or the +nosimd extension. */

52838

+#define TARGET_SIMD (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_SIMD)

52839

+#define TARGET_FLOAT (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_FP)

52840

52841

#define UNITS_PER_WORD 8

52842

52843

Index: gcc/config/rs6000/power8.md

52844

===================================================================

52845

--- a/src/gcc/config/rs6000/power8.md (.../tags/gcc_4_8_2_release)

52846

+++ b/src/gcc/config/rs6000/power8.md (.../branches/gcc-4_8-branch)

52847

@@ -0,0 +1,373 @@

52848

+;; Scheduling description for IBM POWER8 processor.

52849

52850

+;;

52851

+;; Contributed by Pat Haugen (pthaugen@us.ibm.com).

52852

+

52853

+;; This file is part of GCC.

52854

+;;

52855

+;; GCC is free software; you can redistribute it and/or modify it

52856

+;; under the terms of the GNU General Public License as published

52857

+;; by the Free Software Foundation; either version 3, or (at your

52858

+;; option) any later version.

52859

+;;

52860

+;; GCC is distributed in the hope that it will be useful, but WITHOUT

52861

+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY

52862

+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public

52863

+;; License for more details.

52864

+;;

52865

+;; You should have received a copy of the GNU General Public License

52866

+;; along with GCC; see the file COPYING3. If not see

52867

+;; <http://www.gnu.org/licenses/>.

52868

+

52869

+(define_automaton "power8fxu,power8lsu,power8vsu,power8misc")

52870

+

52871

+(define_cpu_unit "fxu0_power8,fxu1_power8" "power8fxu")

52872

+(define_cpu_unit "lu0_power8,lu1_power8" "power8lsu")

52873

+(define_cpu_unit "lsu0_power8,lsu1_power8" "power8lsu")

52874

+(define_cpu_unit "vsu0_power8,vsu1_power8" "power8vsu")

52875

+(define_cpu_unit "bpu_power8,cru_power8" "power8misc")

52876

+(define_cpu_unit "du0_power8,du1_power8,du2_power8,du3_power8,du4_power8,\

52877

+ du5_power8,du6_power8" "power8misc")

52878

+

52879

+

52880

+; Dispatch group reservations

52881

+(define_reservation "DU_any_power8"

52882

52883

+ du5_power8")

52884

+

52885

+; 2-way Cracked instructions go in slots 0-1

52886

+; (can also have a second in slots 3-4 if insns are adjacent)

52887

+(define_reservation "DU_cracked_power8"

52888

+ "du0_power8+du1_power8")

52889

+

52890

+; Insns that are first in group

52891

+(define_reservation "DU_first_power8"

52892

+ "du0_power8")

52893

+

52894

+; Insns that are first and last in group

52895

+(define_reservation "DU_both_power8"

52896

+ "du0_power8+du1_power8+du2_power8+du3_power8+du4_power8+\

52897

+ du5_power8+du6_power8")

52898

+

52899

+; Dispatch slots are allocated in order conforming to program order.

52900

+(absence_set "du0_power8" "du1_power8,du2_power8,du3_power8,du4_power8,\

52901

+ du5_power8,du6_power8")

52902

+(absence_set "du1_power8" "du2_power8,du3_power8,du4_power8,du5_power8,\

52903

+ du6_power8")

52904

+(absence_set "du2_power8" "du3_power8,du4_power8,du5_power8,du6_power8")

52905

+(absence_set "du3_power8" "du4_power8,du5_power8,du6_power8")

52906

+(absence_set "du4_power8" "du5_power8,du6_power8")

52907

+(absence_set "du5_power8" "du6_power8")

52908

+

52909

+

52910

+; Execution unit reservations

52911

+(define_reservation "FXU_power8"

52912

+ "fxu0_power8|fxu1_power8")

52913

+

52914

+(define_reservation "LU_power8"

52915

+ "lu0_power8|lu1_power8")

52916

+

52917

+(define_reservation "LSU_power8"

52918

+ "lsu0_power8|lsu1_power8")

52919

+

52920

+(define_reservation "LU_or_LSU_power8"

52921

+ "lu0_power8|lu1_power8|lsu0_power8|lsu1_power8")

52922

+

52923

+(define_reservation "VSU_power8"

52924

+ "vsu0_power8|vsu1_power8")

52925

+

52926

+

52927

+; LS Unit

52928

+(define_insn_reservation "power8-load" 3

52929

+ (and (eq_attr "type" "load")

52930

+ (eq_attr "cpu" "power8"))

52931

+ "DU_any_power8,LU_or_LSU_power8")

52932

+

52933

+(define_insn_reservation "power8-load-update" 3

52934

+ (and (eq_attr "type" "load_u,load_ux")

52935

+ (eq_attr "cpu" "power8"))

52936

+ "DU_cracked_power8,LU_or_LSU_power8+FXU_power8")

52937

+

52938

+(define_insn_reservation "power8-load-ext" 3

52939

+ (and (eq_attr "type" "load_ext")

52940

+ (eq_attr "cpu" "power8"))

52941

+ "DU_cracked_power8,LU_or_LSU_power8,FXU_power8")

52942

+

52943

+(define_insn_reservation "power8-load-ext-update" 3

52944

+ (and (eq_attr "type" "load_ext_u,load_ext_ux")

52945

+ (eq_attr "cpu" "power8"))

52946

+ "DU_both_power8,LU_or_LSU_power8+FXU_power8,FXU_power8")

52947

+

52948

+(define_insn_reservation "power8-fpload" 5

52949

+ (and (eq_attr "type" "fpload,vecload")

52950

+ (eq_attr "cpu" "power8"))

52951

+ "DU_any_power8,LU_power8")

52952

+

52953

+(define_insn_reservation "power8-fpload-update" 5

52954

+ (and (eq_attr "type" "fpload_u,fpload_ux")

52955

+ (eq_attr "cpu" "power8"))

52956

+ "DU_cracked_power8,LU_power8+FXU_power8")

52957

+

52958

+(define_insn_reservation "power8-store" 5 ; store-forwarding latency

52959

+ (and (eq_attr "type" "store,store_u")

52960

+ (eq_attr "cpu" "power8"))

52961

+ "DU_any_power8,LSU_power8+LU_power8")

52962

+

52963

+(define_insn_reservation "power8-store-update-indexed" 5

52964

+ (and (eq_attr "type" "store_ux")

52965

+ (eq_attr "cpu" "power8"))

52966

+ "DU_cracked_power8,LSU_power8+LU_power8")

52967

+

52968

+(define_insn_reservation "power8-fpstore" 5

52969

+ (and (eq_attr "type" "fpstore")

52970

+ (eq_attr "cpu" "power8"))

52971

+ "DU_any_power8,LSU_power8+VSU_power8")

52972

+

52973

+(define_insn_reservation "power8-fpstore-update" 5

52974

+ (and (eq_attr "type" "fpstore_u,fpstore_ux")

52975

+ (eq_attr "cpu" "power8"))

52976

+ "DU_any_power8,LSU_power8+VSU_power8")

52977

+

52978

+(define_insn_reservation "power8-vecstore" 5

52979

+ (and (eq_attr "type" "vecstore")

52980

+ (eq_attr "cpu" "power8"))

52981

+ "DU_cracked_power8,LSU_power8+VSU_power8")

52982

+

52983

+(define_insn_reservation "power8-larx" 3

52984

+ (and (eq_attr "type" "load_l")

52985

+ (eq_attr "cpu" "power8"))

52986

+ "DU_both_power8,LU_or_LSU_power8")

52987

+

52988

+(define_insn_reservation "power8-stcx" 10

52989

+ (and (eq_attr "type" "store_c")

52990

+ (eq_attr "cpu" "power8"))

52991

+ "DU_both_power8,LSU_power8+LU_power8")

52992

+

52993

+(define_insn_reservation "power8-sync" 1

52994

+ (and (eq_attr "type" "sync,isync")

52995

+ (eq_attr "cpu" "power8"))

52996

+ "DU_both_power8,LSU_power8")

52997

+

52998

+

52999

+; FX Unit

53000

+(define_insn_reservation "power8-1cyc" 1

53001

+ (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\

53002

+ var_shift_rotate,exts,isel")

53003

+ (eq_attr "cpu" "power8"))

53004

+ "DU_any_power8,FXU_power8")

53005

+

53006

+; Extra cycle to LU/LSU

53007

+(define_bypass 2 "power8-1cyc"

53008

+ "power8-load*,power8-fpload*,power8-store*,power8-fpstore*,\

53009

+ power8-vecstore,power8-larx,power8-stcx")

53010

+; "power8-load,power8-load-update,power8-load-ext,\

53011

+; power8-load-ext-update,power8-fpload,power8-fpload-update,\

53012

+; power8-store,power8-store-update,power8-store-update-indexed,\

53013

+; power8-fpstore,power8-fpstore-update,power8-vecstore,\

53014

+; power8-larx,power8-stcx")

53015

+

53016

+(define_insn_reservation "power8-2cyc" 2

53017

+ (and (eq_attr "type" "cntlz,popcnt")

53018

+ (eq_attr "cpu" "power8"))

53019

+ "DU_any_power8,FXU_power8")

53020

+

53021

+(define_insn_reservation "power8-two" 2

53022

+ (and (eq_attr "type" "two")

53023

+ (eq_attr "cpu" "power8"))

53024

+ "DU_any_power8+DU_any_power8,FXU_power8,FXU_power8")

53025

+

53026

+(define_insn_reservation "power8-three" 3

53027

+ (and (eq_attr "type" "three")

53028

+ (eq_attr "cpu" "power8"))

53029

+ "DU_any_power8+DU_any_power8+DU_any_power8,FXU_power8,FXU_power8,FXU_power8")

53030

+

53031

+; cmp - Normal compare insns

53032

+(define_insn_reservation "power8-cmp" 2

53033

+ (and (eq_attr "type" "cmp")

53034

+ (eq_attr "cpu" "power8"))

53035

+ "DU_any_power8,FXU_power8")

53036

+

53037

+; fast_compare : add./and./nor./etc

53038

+(define_insn_reservation "power8-fast-compare" 2

53039

+ (and (eq_attr "type" "fast_compare")

53040

+ (eq_attr "cpu" "power8"))

53041

+ "DU_any_power8,FXU_power8")

53042

+

53043

+; compare : rldicl./exts./etc

53044

+; delayed_compare : rlwinm./slwi./etc

53045

+; var_delayed_compare : rlwnm./slw./etc

53046

+(define_insn_reservation "power8-compare" 2

53047

+ (and (eq_attr "type" "compare,delayed_compare,var_delayed_compare")

53048

+ (eq_attr "cpu" "power8"))

53049

+ "DU_cracked_power8,FXU_power8,FXU_power8")

53050

+

53051

+; Extra cycle to LU/LSU

53052

+(define_bypass 3 "power8-fast-compare,power8-compare"

53053

+ "power8-load*,power8-fpload*,power8-store*,power8-fpstore*,\

53054

+ power8-vecstore,power8-larx,power8-stcx")

53055

+

53056

+; 5 cycle CR latency

53057

+(define_bypass 5 "power8-fast-compare,power8-compare"

53058

+ "power8-crlogical,power8-mfcr,power8-mfcrf,power8-branch")

53059

+

53060

+(define_insn_reservation "power8-mul" 4

53061

+ (and (eq_attr "type" "imul,imul2,imul3,lmul")

53062

+ (eq_attr "cpu" "power8"))

53063

+ "DU_any_power8,FXU_power8")

53064

+

53065

+(define_insn_reservation "power8-mul-compare" 4

53066

+ (and (eq_attr "type" "imul_compare,lmul_compare")

53067

+ (eq_attr "cpu" "power8"))

53068

+ "DU_cracked_power8,FXU_power8")

53069

+

53070

+; Extra cycle to LU/LSU

53071

+(define_bypass 5 "power8-mul,power8-mul-compare"

53072

+ "power8-load*,power8-fpload*,power8-store*,power8-fpstore*,\

53073

+ power8-vecstore,power8-larx,power8-stcx")

53074

+

53075

+; 7 cycle CR latency

53076

+(define_bypass 7 "power8-mul,power8-mul-compare"

53077

+ "power8-crlogical,power8-mfcr,power8-mfcrf,power8-branch")

53078

+

53079

+; FXU divides are not pipelined

53080

+(define_insn_reservation "power8-idiv" 37

53081

+ (and (eq_attr "type" "idiv")

53082

+ (eq_attr "cpu" "power8"))

53083

+ "DU_any_power8,fxu0_power8*37|fxu1_power8*37")

53084

+

53085

+(define_insn_reservation "power8-ldiv" 68

53086

+ (and (eq_attr "type" "ldiv")

53087

+ (eq_attr "cpu" "power8"))

53088

+ "DU_any_power8,fxu0_power8*68|fxu1_power8*68")

53089

+

53090

+(define_insn_reservation "power8-mtjmpr" 5

53091

+ (and (eq_attr "type" "mtjmpr")

53092

+ (eq_attr "cpu" "power8"))

53093

+ "DU_first_power8,FXU_power8")

53094

+

53095

+; Should differentiate between 1 cr field and > 1 since mtocrf is not microcode

53096

+(define_insn_reservation "power8-mtcr" 3

53097

+ (and (eq_attr "type" "mtcr")

53098

+ (eq_attr "cpu" "power8"))

53099

+ "DU_both_power8,FXU_power8")

53100

+

53101

+

53102

+; CR Unit

53103

+(define_insn_reservation "power8-mfjmpr" 5

53104

+ (and (eq_attr "type" "mfjmpr")

53105

+ (eq_attr "cpu" "power8"))

53106

+ "DU_first_power8,cru_power8+FXU_power8")

53107

+

53108

+(define_insn_reservation "power8-crlogical" 3

53109

+ (and (eq_attr "type" "cr_logical,delayed_cr")

53110

+ (eq_attr "cpu" "power8"))

53111

+ "DU_first_power8,cru_power8")

53112

+

53113

+(define_insn_reservation "power8-mfcr" 5

53114

+ (and (eq_attr "type" "mfcr")

53115

+ (eq_attr "cpu" "power8"))

53116

+ "DU_both_power8,cru_power8")

53117

+

53118

+(define_insn_reservation "power8-mfcrf" 3

53119

+ (and (eq_attr "type" "mfcrf")

53120

+ (eq_attr "cpu" "power8"))

53121

+ "DU_first_power8,cru_power8")

53122

+

53123

+

53124

+; BR Unit

53125

+; Branches take dispatch slot 7, but reserve any remaining prior slots to

53126

+; prevent other insns from grabbing them once this is assigned.

53127

+(define_insn_reservation "power8-branch" 3

53128

+ (and (eq_attr "type" "jmpreg,branch")

53129

+ (eq_attr "cpu" "power8"))

53130

+ "(du6_power8\

53131

+ |du5_power8+du6_power8\

53132

+ |du4_power8+du5_power8+du6_power8\

53133

+ |du3_power8+du4_power8+du5_power8+du6_power8\

53134

+ |du2_power8+du3_power8+du4_power8+du5_power8+du6_power8\

53135

+ |du1_power8+du2_power8+du3_power8+du4_power8+du5_power8+du6_power8\

53136

+ |du0_power8+du1_power8+du2_power8+du3_power8+du4_power8+du5_power8+\

53137

+ du6_power8),bpu_power8")

53138

+

53139

+; Branch updating LR/CTR feeding mf[lr|ctr]

53140

+(define_bypass 4 "power8-branch" "power8-mfjmpr")

53141

+

53142

+

53143

+; VS Unit (includes FP/VSX/VMX/DFP/Crypto)

53144

+(define_insn_reservation "power8-fp" 6

53145

+ (and (eq_attr "type" "fp,dmul")

53146

+ (eq_attr "cpu" "power8"))

53147

+ "DU_any_power8,VSU_power8")

53148

+

53149

+; Additional 3 cycles for any CR result

53150

+(define_bypass 9 "power8-fp" "power8-crlogical,power8-mfcr*,power8-branch")

53151

+

53152

+(define_insn_reservation "power8-fpcompare" 8

53153

+ (and (eq_attr "type" "fpcompare")

53154

+ (eq_attr "cpu" "power8"))

53155

+ "DU_any_power8,VSU_power8")

53156

+

53157

+(define_insn_reservation "power8-sdiv" 27

53158

+ (and (eq_attr "type" "sdiv")

53159

+ (eq_attr "cpu" "power8"))

53160

+ "DU_any_power8,VSU_power8")

53161

+

53162

+(define_insn_reservation "power8-ddiv" 33

53163

+ (and (eq_attr "type" "ddiv")

53164

+ (eq_attr "cpu" "power8"))

53165

+ "DU_any_power8,VSU_power8")

53166

+

53167

+(define_insn_reservation "power8-sqrt" 32

53168

+ (and (eq_attr "type" "ssqrt")

53169

+ (eq_attr "cpu" "power8"))

53170

+ "DU_any_power8,VSU_power8")

53171

+

53172

+(define_insn_reservation "power8-dsqrt" 44

53173

+ (and (eq_attr "type" "dsqrt")

53174

+ (eq_attr "cpu" "power8"))

53175

+ "DU_any_power8,VSU_power8")

53176

+

53177

+(define_insn_reservation "power8-vecsimple" 2

53178

+ (and (eq_attr "type" "vecperm,vecsimple,veccmp")

53179

+ (eq_attr "cpu" "power8"))

53180

+ "DU_any_power8,VSU_power8")

53181

+

53182

+(define_insn_reservation "power8-vecnormal" 6

53183

+ (and (eq_attr "type" "vecfloat,vecdouble")

53184

+ (eq_attr "cpu" "power8"))

53185

+ "DU_any_power8,VSU_power8")

53186

+

53187

+(define_bypass 7 "power8-vecnormal"

53188

+ "power8-vecsimple,power8-veccomplex,power8-fpstore*,\

53189

+ power8-vecstore")

53190

+

53191

+(define_insn_reservation "power8-veccomplex" 7

53192

+ (and (eq_attr "type" "veccomplex")

53193

+ (eq_attr "cpu" "power8"))

53194

+ "DU_any_power8,VSU_power8")

53195

+

53196

+(define_insn_reservation "power8-vecfdiv" 25

53197

+ (and (eq_attr "type" "vecfdiv")

53198

+ (eq_attr "cpu" "power8"))

53199

+ "DU_any_power8,VSU_power8")

53200

+

53201

+(define_insn_reservation "power8-vecdiv" 31

53202

+ (and (eq_attr "type" "vecdiv")

53203

+ (eq_attr "cpu" "power8"))

53204

+ "DU_any_power8,VSU_power8")

53205

+

53206

+(define_insn_reservation "power8-mffgpr" 5

53207

+ (and (eq_attr "type" "mffgpr")

53208

+ (eq_attr "cpu" "power8"))

53209

+ "DU_any_power8,VSU_power8")

53210

+

53211

+(define_insn_reservation "power8-mftgpr" 6

53212

+ (and (eq_attr "type" "mftgpr")

53213

+ (eq_attr "cpu" "power8"))

53214

+ "DU_any_power8,VSU_power8")

53215

+

53216

+(define_insn_reservation "power8-crypto" 7

53217

+ (and (eq_attr "type" "crypto")

53218

+ (eq_attr "cpu" "power8"))

53219

+ "DU_any_power8,VSU_power8")

53220

+

53221

Index: gcc/config/rs6000/vector.md

53222

===================================================================

53223

--- a/src/gcc/config/rs6000/vector.md (.../tags/gcc_4_8_2_release)

53224

+++ b/src/gcc/config/rs6000/vector.md (.../branches/gcc-4_8-branch)

53225

@@ -24,28 +24,28 @@

53226

53227

53228

;; Vector int modes

53229

-(define_mode_iterator VEC_I [V16QI V8HI V4SI])

53230

+(define_mode_iterator VEC_I [V16QI V8HI V4SI V2DI])

53231

53232

;; Vector float modes

53233

(define_mode_iterator VEC_F [V4SF V2DF])

53234

53235

;; Vector arithmetic modes

53236

-(define_mode_iterator VEC_A [V16QI V8HI V4SI V4SF V2DF])

53237

+(define_mode_iterator VEC_A [V16QI V8HI V4SI V2DI V4SF V2DF])

53238

53239

;; Vector modes that need alginment via permutes

53240

(define_mode_iterator VEC_K [V16QI V8HI V4SI V4SF])

53241

53242

;; Vector logical modes

53243

-(define_mode_iterator VEC_L [V16QI V8HI V4SI V2DI V4SF V2DF TI])

53244

+(define_mode_iterator VEC_L [V16QI V8HI V4SI V2DI V4SF V2DF V1TI TI])

53245

53246

;; Vector modes for moves. Don't do TImode here.

53247

-(define_mode_iterator VEC_M [V16QI V8HI V4SI V2DI V4SF V2DF])

53248

+(define_mode_iterator VEC_M [V16QI V8HI V4SI V2DI V4SF V2DF V1TI])

53249

53250

;; Vector modes for types that don't need a realignment under VSX

53251

-(define_mode_iterator VEC_N [V4SI V4SF V2DI V2DF])

53252

+(define_mode_iterator VEC_N [V4SI V4SF V2DI V2DF V1TI])

53253

53254

;; Vector comparison modes

53255

-(define_mode_iterator VEC_C [V16QI V8HI V4SI V4SF V2DF])

53256

+(define_mode_iterator VEC_C [V16QI V8HI V4SI V2DI V4SF V2DF])

53257

53258

;; Vector init/extract modes

53259

(define_mode_iterator VEC_E [V16QI V8HI V4SI V2DI V4SF V2DF])

53260

@@ -54,7 +54,8 @@

53261

(define_mode_iterator VEC_64 [V2DI V2DF])

53262

53263

;; Vector reload iterator

53264

-(define_mode_iterator VEC_R [V16QI V8HI V4SI V2DI V4SF V2DF DF TI])

53265

+(define_mode_iterator VEC_R [V16QI V8HI V4SI V2DI V4SF V2DF V1TI

53266

+ SF SD SI DF DD DI TI])

53267

53268

;; Base type from vector mode

53269

(define_mode_attr VEC_base [(V16QI "QI")

53270

@@ -63,6 +64,7 @@

53271

(V2DI "DI")

53272

(V4SF "SF")

53273

(V2DF "DF")

53274

+ (V1TI "TI")

53275

(TI "TI")])

53276

53277

;; Same size integer type for floating point data

53278

@@ -88,7 +90,8 @@

53279

(smax "smax")])

53280

53281

53282

-;; Vector move instructions.

53283

+;; Vector move instructions. Little-endian VSX loads and stores require

53284

+;; special handling to circumvent "element endianness."

53285

(define_expand "mov<mode>"

53286

[(set (match_operand:VEC_M 0 "nonimmediate_operand" "")

53287

(match_operand:VEC_M 1 "any_operand" ""))]

53288

@@ -104,6 +107,15 @@

53289

&& !vlogical_operand (operands[1], <MODE>mode))

53290

operands[1] = force_reg (<MODE>mode, operands[1]);

53291

}

53292

+ if (!BYTES_BIG_ENDIAN

53293

+ && VECTOR_MEM_VSX_P (<MODE>mode)

53294

+ && !gpr_or_gpr_p (operands[0], operands[1])

53295

+ && (memory_operand (operands[0], <MODE>mode)

53296

+ ^ memory_operand (operands[1], <MODE>mode)))

53297

+ {

53298

+ rs6000_emit_le_vsx_move (operands[0], operands[1], <MODE>mode);

53299

+ DONE;

53300

+ }

53301

})

53302

53303

;; Generic vector floating point load/store instructions. These will match

53304

@@ -126,7 +138,9 @@

53305

(match_operand:VEC_L 1 "input_operand" ""))]

53306

"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)

53307

&& reload_completed

53308

- && gpr_or_gpr_p (operands[0], operands[1])"

53309

+ && gpr_or_gpr_p (operands[0], operands[1])

53310

+ && !direct_move_p (operands[0], operands[1])

53311

+ && !quad_load_store_p (operands[0], operands[1])"

53312

[(pc)]

53313

{

53314

rs6000_split_multireg_move (operands[0], operands[1]);

53315

@@ -249,7 +263,7 @@

53316

[(set (match_operand:VEC_F 0 "vfloat_operand" "")

53317

(mult:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")

53318

(match_operand:VEC_F 2 "vfloat_operand" "")))]

53319

- "VECTOR_UNIT_VSX_P (<MODE>mode) || VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"

53320

+ "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"

53321

{

53322

if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))

53323

{

53324

@@ -395,7 +409,7 @@

53325

(match_operand:VEC_I 5 "vint_operand" "")])

53326

(match_operand:VEC_I 1 "vint_operand" "")

53327

(match_operand:VEC_I 2 "vint_operand" "")))]

53328

- "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"

53329

+ "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"

53330

"

53331

{

53332

if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],

53333

@@ -451,7 +465,7 @@

53334

(match_operand:VEC_I 5 "vint_operand" "")])

53335

(match_operand:VEC_I 1 "vint_operand" "")

53336

(match_operand:VEC_I 2 "vint_operand" "")))]

53337

- "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"

53338

+ "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"

53339

"

53340

{

53341

if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],

53342

@@ -505,7 +519,7 @@

53343

[(set (match_operand:VEC_I 0 "vint_operand" "")

53344

(gtu:VEC_I (match_operand:VEC_I 1 "vint_operand" "")

53345

(match_operand:VEC_I 2 "vint_operand" "")))]

53346

- "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"

53347

+ "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"

53348

"")

53349

53350

(define_expand "vector_geu<mode>"

53351

@@ -512,7 +526,7 @@

53352

[(set (match_operand:VEC_I 0 "vint_operand" "")

53353

(geu:VEC_I (match_operand:VEC_I 1 "vint_operand" "")

53354

(match_operand:VEC_I 2 "vint_operand" "")))]

53355

- "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"

53356

+ "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"

53357

"")

53358

53359

(define_insn_and_split "*vector_uneq<mode>"

53360

@@ -595,8 +609,8 @@

53361

(ge:VEC_F (match_dup 2)

53362

(match_dup 1)))

53363

(set (match_dup 0)

53364

- (not:VEC_F (ior:VEC_F (match_dup 3)

53365

- (match_dup 4))))]

53366

+ (and:VEC_F (not:VEC_F (match_dup 3))

53367

+ (not:VEC_F (match_dup 4))))]

53368

"

53369

{

53370

operands[3] = gen_reg_rtx (<MODE>mode);

53371

@@ -708,48 +722,19 @@

53372

"")

53373

53374

53375

-;; Vector logical instructions

53376

-(define_expand "xor<mode>3"

53377

- [(set (match_operand:VEC_L 0 "vlogical_operand" "")

53378

- (xor:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")

53379

- (match_operand:VEC_L 2 "vlogical_operand" "")))]

53380

- "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"

53381

- "")

53382

+;; Vector count leading zeros

53383

+(define_expand "clz<mode>2"

53384

+ [(set (match_operand:VEC_I 0 "register_operand" "")

53385

+ (clz:VEC_I (match_operand:VEC_I 1 "register_operand" "")))]

53386

+ "TARGET_P8_VECTOR")

53387

53388

-(define_expand "ior<mode>3"

53389

- [(set (match_operand:VEC_L 0 "vlogical_operand" "")

53390

- (ior:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")

53391

- (match_operand:VEC_L 2 "vlogical_operand" "")))]

53392

- "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"

53393

- "")

53394

+;; Vector population count

53395

+(define_expand "popcount<mode>2"

53396

+ [(set (match_operand:VEC_I 0 "register_operand" "")

53397

+ (popcount:VEC_I (match_operand:VEC_I 1 "register_operand" "")))]

53398

+ "TARGET_P8_VECTOR")

53399

53400

-(define_expand "and<mode>3"

53401

- [(set (match_operand:VEC_L 0 "vlogical_operand" "")

53402

- (and:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")

53403

- (match_operand:VEC_L 2 "vlogical_operand" "")))]

53404

- "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"

53405

- "")

53406

-

53407

-(define_expand "one_cmpl<mode>2"

53408

- [(set (match_operand:VEC_L 0 "vlogical_operand" "")

53409

- (not:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")))]

53410

- "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"

53411

- "")

53412

-

53413

-(define_expand "nor<mode>3"

53414

- [(set (match_operand:VEC_L 0 "vlogical_operand" "")

53415

- (not:VEC_L (ior:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")

53416

- (match_operand:VEC_L 2 "vlogical_operand" ""))))]

53417

- "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"

53418

- "")

53419

-

53420

-(define_expand "andc<mode>3"

53421

- [(set (match_operand:VEC_L 0 "vlogical_operand" "")

53422

- (and:VEC_L (not:VEC_L (match_operand:VEC_L 2 "vlogical_operand" ""))

53423

- (match_operand:VEC_L 1 "vlogical_operand" "")))]

53424

- "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"

53425

- "")

53426

-

53427

+

53428

;; Same size conversions

53429

(define_expand "float<VEC_int><mode>2"

53430

[(set (match_operand:VEC_F 0 "vfloat_operand" "")

53431

@@ -889,7 +874,7 @@

53432

{

53433

rtx reg = gen_reg_rtx (V4SFmode);

53434

53435

- rs6000_expand_interleave (reg, operands[1], operands[1], true);

53436

+ rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN);

53437

emit_insn (gen_vsx_xvcvspdp (operands[0], reg));

53438

DONE;

53439

})

53440

@@ -901,7 +886,7 @@

53441

{

53442

rtx reg = gen_reg_rtx (V4SFmode);

53443

53444

- rs6000_expand_interleave (reg, operands[1], operands[1], false);

53445

+ rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN);

53446

emit_insn (gen_vsx_xvcvspdp (operands[0], reg));

53447

DONE;

53448

})

53449

@@ -913,7 +898,7 @@

53450

{

53451

rtx reg = gen_reg_rtx (V4SImode);

53452

53453

- rs6000_expand_interleave (reg, operands[1], operands[1], true);

53454

+ rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN);

53455

emit_insn (gen_vsx_xvcvsxwdp (operands[0], reg));

53456

DONE;

53457

})

53458

@@ -925,7 +910,7 @@

53459

{

53460

rtx reg = gen_reg_rtx (V4SImode);

53461

53462

- rs6000_expand_interleave (reg, operands[1], operands[1], false);

53463

+ rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN);

53464

emit_insn (gen_vsx_xvcvsxwdp (operands[0], reg));

53465

DONE;

53466

})

53467

@@ -937,7 +922,7 @@

53468

{

53469

rtx reg = gen_reg_rtx (V4SImode);

53470

53471

- rs6000_expand_interleave (reg, operands[1], operands[1], true);

53472

+ rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN);

53473

emit_insn (gen_vsx_xvcvuxwdp (operands[0], reg));

53474

DONE;

53475

})

53476

@@ -949,7 +934,7 @@

53477

{

53478

rtx reg = gen_reg_rtx (V4SImode);

53479

53480

- rs6000_expand_interleave (reg, operands[1], operands[1], false);

53481

+ rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN);

53482

emit_insn (gen_vsx_xvcvuxwdp (operands[0], reg));

53483

DONE;

53484

})

53485

@@ -963,8 +948,19 @@

53486

(match_operand:V16QI 3 "vlogical_operand" "")]

53487

"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"

53488

{

53489

- emit_insn (gen_altivec_vperm_<mode> (operands[0], operands[1], operands[2],

53490

- operands[3]));

53491

+ if (BYTES_BIG_ENDIAN)

53492

+ emit_insn (gen_altivec_vperm_<mode> (operands[0], operands[1],

53493

+ operands[2], operands[3]));

53494

+ else

53495

+ {

53496

+ /* We have changed lvsr to lvsl, so to complete the transformation

53497

+ of vperm for LE, we must swap the inputs. */

53498

+ rtx unspec = gen_rtx_UNSPEC (<MODE>mode,

53499

+ gen_rtvec (3, operands[2],

53500

+ operands[1], operands[3]),

53501

+ UNSPEC_VPERM);

53502

+ emit_move_insn (operands[0], unspec);

53503

+ }

53504

DONE;

53505

})

53506

53507

@@ -1064,7 +1060,7 @@

53508

[(set (match_operand:VEC_I 0 "vint_operand" "")

53509

(rotate:VEC_I (match_operand:VEC_I 1 "vint_operand" "")

53510

(match_operand:VEC_I 2 "vint_operand" "")))]

53511

- "TARGET_ALTIVEC"

53512

+ "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"

53513

"")

53514

53515

;; Expanders for arithmetic shift left on each vector element

53516

@@ -1072,7 +1068,7 @@

53517

[(set (match_operand:VEC_I 0 "vint_operand" "")

53518

(ashift:VEC_I (match_operand:VEC_I 1 "vint_operand" "")

53519

(match_operand:VEC_I 2 "vint_operand" "")))]

53520

- "TARGET_ALTIVEC"

53521

+ "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"

53522

"")

53523

53524

;; Expanders for logical shift right on each vector element

53525

@@ -1080,7 +1076,7 @@

53526

[(set (match_operand:VEC_I 0 "vint_operand" "")

53527

(lshiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand" "")

53528

(match_operand:VEC_I 2 "vint_operand" "")))]

53529

- "TARGET_ALTIVEC"

53530

+ "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"

53531

"")

53532

53533

;; Expanders for arithmetic shift right on each vector element

53534

@@ -1088,7 +1084,7 @@

53535

[(set (match_operand:VEC_I 0 "vint_operand" "")

53536

(ashiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand" "")

53537

(match_operand:VEC_I 2 "vint_operand" "")))]

53538

- "TARGET_ALTIVEC"

53539

+ "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"

53540

"")

53541

53542

;; Vector reduction expanders for VSX

53543

Index: gcc/config/rs6000/constraints.md

53544

===================================================================

53545

--- a/src/gcc/config/rs6000/constraints.md (.../tags/gcc_4_8_2_release)

53546

+++ b/src/gcc/config/rs6000/constraints.md (.../branches/gcc-4_8-branch)

53547

@@ -52,22 +52,62 @@

53548

"@internal")

53549

53550

;; Use w as a prefix to add VSX modes

53551

-;; vector double (V2DF)

53552

+;; any VSX register

53553

+(define_register_constraint "wa" "rs6000_constraints[RS6000_CONSTRAINT_wa]"

53554

+ "Any VSX register if the -mvsx option was used or NO_REGS.")

53555

+

53556

(define_register_constraint "wd" "rs6000_constraints[RS6000_CONSTRAINT_wd]"

53557

- "@internal")

53558

+ "VSX vector register to hold vector double data or NO_REGS.")

53559

53560

-;; vector float (V4SF)

53561

(define_register_constraint "wf" "rs6000_constraints[RS6000_CONSTRAINT_wf]"

53562

- "@internal")

53563

+ "VSX vector register to hold vector float data or NO_REGS.")

53564

53565

-;; scalar double (DF)

53566

+(define_register_constraint "wg" "rs6000_constraints[RS6000_CONSTRAINT_wg]"

53567

+ "If -mmfpgpr was used, a floating point register or NO_REGS.")

53568

+

53569

+(define_register_constraint "wl" "rs6000_constraints[RS6000_CONSTRAINT_wl]"

53570

+ "Floating point register if the LFIWAX instruction is enabled or NO_REGS.")

53571

+

53572

+(define_register_constraint "wm" "rs6000_constraints[RS6000_CONSTRAINT_wm]"

53573

+ "VSX register if direct move instructions are enabled, or NO_REGS.")

53574

+

53575

+;; NO_REGs register constraint, used to merge mov{sd,sf}, since movsd can use

53576

+;; direct move directly, and movsf can't to move between the register sets.

53577

+;; There is a mode_attr that resolves to wm for SDmode and wn for SFmode

53578

+(define_register_constraint "wn" "NO_REGS" "No register (NO_REGS).")

53579

+

53580

+(define_register_constraint "wr" "rs6000_constraints[RS6000_CONSTRAINT_wr]"

53581

+ "General purpose register if 64-bit instructions are enabled or NO_REGS.")

53582

+

53583

(define_register_constraint "ws" "rs6000_constraints[RS6000_CONSTRAINT_ws]"

53584

- "@internal")

53585

+ "VSX vector register to hold scalar double values or NO_REGS.")

53586

53587

-;; any VSX register

53588

-(define_register_constraint "wa" "rs6000_constraints[RS6000_CONSTRAINT_wa]"

53589

- "@internal")

53590

+(define_register_constraint "wt" "rs6000_constraints[RS6000_CONSTRAINT_wt]"

53591

+ "VSX vector register to hold 128 bit integer or NO_REGS.")

53592

53593

+(define_register_constraint "wu" "rs6000_constraints[RS6000_CONSTRAINT_wu]"

53594

+ "Altivec register to use for float/32-bit int loads/stores or NO_REGS.")

53595

+

53596

+(define_register_constraint "wv" "rs6000_constraints[RS6000_CONSTRAINT_wv]"

53597

+ "Altivec register to use for double loads/stores or NO_REGS.")

53598

+

53599

+(define_register_constraint "ww" "rs6000_constraints[RS6000_CONSTRAINT_ww]"

53600

+ "FP or VSX register to perform float operations under -mvsx or NO_REGS.")

53601

+

53602

+(define_register_constraint "wx" "rs6000_constraints[RS6000_CONSTRAINT_wx]"

53603

+ "Floating point register if the STFIWX instruction is enabled or NO_REGS.")

53604

+

53605

+(define_register_constraint "wy" "rs6000_constraints[RS6000_CONSTRAINT_wy]"

53606

+ "VSX vector register to hold scalar float values or NO_REGS.")

53607

+

53608

+(define_register_constraint "wz" "rs6000_constraints[RS6000_CONSTRAINT_wz]"

53609

+ "Floating point register if the LFIWZX instruction is enabled or NO_REGS.")

53610

+

53611

+;; Lq/stq validates the address for load/store quad

53612

+(define_memory_constraint "wQ"

53613

+ "Memory operand suitable for the load/store quad instructions"

53614

+ (match_operand 0 "quad_memory_operand"))

53615

+

53616

;; Altivec style load/store that ignores the bottom bits of the address

53617

(define_memory_constraint "wZ"

53618

"Indexed or indirect memory operand, ignoring the bottom 4 bits"

53619

Index: gcc/config/rs6000/predicates.md

53620

===================================================================

53621

--- a/src/gcc/config/rs6000/predicates.md (.../tags/gcc_4_8_2_release)

53622

+++ b/src/gcc/config/rs6000/predicates.md (.../branches/gcc-4_8-branch)

53623

@@ -124,6 +124,11 @@

53624

(and (match_code "const_int")

53625

(match_test "INTVAL (op) >= -16 && INTVAL (op) <= 15")))

53626

53627

+;; Return 1 if op is a unsigned 3-bit constant integer.

53628

+(define_predicate "u3bit_cint_operand"

53629

+ (and (match_code "const_int")

53630

+ (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 7")))

53631

+

53632

;; Return 1 if op is a unsigned 5-bit constant integer.

53633

(define_predicate "u5bit_cint_operand"

53634

(and (match_code "const_int")

53635

@@ -135,6 +140,11 @@

53636

(and (match_code "const_int")

53637

(match_test "INTVAL (op) >= -128 && INTVAL (op) <= 127")))

53638

53639

+;; Return 1 if op is a unsigned 10-bit constant integer.

53640

+(define_predicate "u10bit_cint_operand"

53641

+ (and (match_code "const_int")

53642

+ (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 1023")))

53643

+

53644

;; Return 1 if op is a constant integer that can fit in a D field.

53645

(define_predicate "short_cint_operand"

53646

(and (match_code "const_int")

53647

@@ -161,11 +171,21 @@

53648

(and (match_code "const_int")

53649

(match_test "IN_RANGE (INTVAL (op), 0, 1)")))

53650

53651

+;; Match op = 0..3.

53652

+(define_predicate "const_0_to_3_operand"

53653

+ (and (match_code "const_int")

53654

+ (match_test "IN_RANGE (INTVAL (op), 0, 3)")))

53655

+

53656

;; Match op = 2 or op = 3.

53657

(define_predicate "const_2_to_3_operand"

53658

(and (match_code "const_int")

53659

(match_test "IN_RANGE (INTVAL (op), 2, 3)")))

53660

53661

+;; Match op = 0..15

53662

+(define_predicate "const_0_to_15_operand"

53663

+ (and (match_code "const_int")

53664

+ (match_test "IN_RANGE (INTVAL (op), 0, 15)")))

53665

+

53666

;; Return 1 if op is a register that is not special.

53667

(define_predicate "gpc_reg_operand"

53668

(match_operand 0 "register_operand")

53669

@@ -182,9 +202,95 @@

53670

if (REGNO (op) >= ARG_POINTER_REGNUM && !CA_REGNO_P (REGNO (op)))

53671

return 1;

53672

53673

+ if (TARGET_VSX && VSX_REGNO_P (REGNO (op)))

53674

+ return 1;

53675

+

53676

return INT_REGNO_P (REGNO (op)) || FP_REGNO_P (REGNO (op));

53677

})

53678

53679

+;; Return 1 if op is a general purpose register. Unlike gpc_reg_operand, don't

53680

+;; allow floating point or vector registers.

53681

+(define_predicate "int_reg_operand"

53682

+ (match_operand 0 "register_operand")

53683

+{

53684

+ if ((TARGET_E500_DOUBLE || TARGET_SPE) && invalid_e500_subreg (op, mode))

53685

+ return 0;

53686

+

53687

+ if (GET_CODE (op) == SUBREG)

53688

+ op = SUBREG_REG (op);

53689

+

53690

+ if (!REG_P (op))

53691

+ return 0;

53692

+

53693

+ if (REGNO (op) >= FIRST_PSEUDO_REGISTER)

53694

+ return 1;

53695

+

53696

+ return INT_REGNO_P (REGNO (op));

53697

+})

53698

+

53699

+;; Like int_reg_operand, but only return true for base registers

53700

+(define_predicate "base_reg_operand"

53701

+ (match_operand 0 "int_reg_operand")

53702

+{

53703

+ if (GET_CODE (op) == SUBREG)

53704

+ op = SUBREG_REG (op);

53705

+

53706

+ if (!REG_P (op))

53707

+ return 0;

53708

+

53709

+ return (REGNO (op) != FIRST_GPR_REGNO);

53710

+})

53711

+

53712

+;; Return 1 if op is a HTM specific SPR register.

53713

+(define_predicate "htm_spr_reg_operand"

53714

+ (match_operand 0 "register_operand")

53715

+{

53716

+ if (!TARGET_HTM)

53717

+ return 0;

53718

+

53719

+ if (GET_CODE (op) == SUBREG)

53720

+ op = SUBREG_REG (op);

53721

+

53722

+ if (!REG_P (op))

53723

+ return 0;

53724

+

53725

+ switch (REGNO (op))

53726

+ {

53727

+ case TFHAR_REGNO:

53728

+ case TFIAR_REGNO:

53729

+ case TEXASR_REGNO:

53730

+ return 1;

53731

+ default:

53732

+ break;

53733

+ }

53734

+

53735

+ /* Unknown SPR. */

53736

+ return 0;

53737

+})

53738

+

53739

+;; Return 1 if op is a general purpose register that is an even register

53740

+;; which suitable for a load/store quad operation

53741

+(define_predicate "quad_int_reg_operand"

53742

+ (match_operand 0 "register_operand")

53743

+{

53744

+ HOST_WIDE_INT r;

53745

+

53746

+ if (!TARGET_QUAD_MEMORY && !TARGET_QUAD_MEMORY_ATOMIC)

53747

+ return 0;

53748

+

53749

+ if (GET_CODE (op) == SUBREG)

53750

+ op = SUBREG_REG (op);

53751

+

53752

+ if (!REG_P (op))

53753

+ return 0;

53754

+

53755

+ r = REGNO (op);

53756

+ if (r >= FIRST_PSEUDO_REGISTER)

53757

+ return 1;

53758

+

53759

+ return (INT_REGNO_P (r) && ((r & 1) == 0));

53760

+})

53761

+

53762

;; Return 1 if op is a register that is a condition register field.

53763

(define_predicate "cc_reg_operand"

53764

(match_operand 0 "register_operand")

53765

@@ -315,6 +421,11 @@

53766

&& CONST_DOUBLE_HIGH (op) == 0")

53767

(match_operand 0 "gpc_reg_operand"))))

53768

53769

+;; Like reg_or_logical_cint_operand, but allow vsx registers

53770

+(define_predicate "vsx_reg_or_cint_operand"

53771

+ (ior (match_operand 0 "vsx_register_operand")

53772

+ (match_operand 0 "reg_or_logical_cint_operand")))

53773

+

53774

;; Return 1 if operand is a CONST_DOUBLE that can be set in a register

53775

;; with no more than one instruction per word.

53776

(define_predicate "easy_fp_constant"

53777

@@ -333,6 +444,11 @@

53778

&& mode != DImode)

53779

return 1;

53780

53781

+ /* The constant 0.0 is easy under VSX. */

53782

+ if ((mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode)

53783

+ && VECTOR_UNIT_VSX_P (DFmode) && op == CONST0_RTX (mode))

53784

+ return 1;

53785

+

53786

if (DECIMAL_FLOAT_MODE_P (mode))

53787

return 0;

53788

53789

@@ -521,6 +637,55 @@

53790

(and (match_operand 0 "memory_operand")

53791

(match_test "offsettable_nonstrict_memref_p (op)")))

53792

53793

+;; Return 1 if the operand is suitable for load/store quad memory.

53794

+;; This predicate only checks for non-atomic loads/stores (not lqarx/stqcx).

53795

+(define_predicate "quad_memory_operand"

53796

+ (match_code "mem")

53797

+{

53798

+ rtx addr, op0, op1;

53799

+ int ret;

53800

+

53801

+ if (!TARGET_QUAD_MEMORY && !TARGET_SYNC_TI)

53802

+ ret = 0;

53803

+

53804

+ else if (!memory_operand (op, mode))

53805

+ ret = 0;

53806

+

53807

+ else if (GET_MODE_SIZE (GET_MODE (op)) != 16)

53808

+ ret = 0;

53809

+

53810

+ else if (MEM_ALIGN (op) < 128)

53811

+ ret = 0;

53812

+

53813

+ else

53814

+ {

53815

+ addr = XEXP (op, 0);

53816

+ if (int_reg_operand (addr, Pmode))

53817

+ ret = 1;

53818

+

53819

+ else if (GET_CODE (addr) != PLUS)

53820

+ ret = 0;

53821

+

53822

+ else

53823

+ {

53824

+ op0 = XEXP (addr, 0);

53825

+ op1 = XEXP (addr, 1);

53826

+ ret = (int_reg_operand (op0, Pmode)

53827

+ && GET_CODE (op1) == CONST_INT

53828

+ && IN_RANGE (INTVAL (op1), -32768, 32767)

53829

+ && (INTVAL (op1) & 15) == 0);

53830

+ }

53831

+ }

53832

+

53833

+ if (TARGET_DEBUG_ADDR)

53834

+ {

53835

+ fprintf (stderr, "\nquad_memory_operand, ret = %s\n", ret ? "true" : "false");

53836

+ debug_rtx (op);

53837

+ }

53838

+

53839

+ return ret;

53840

+})

53841

+

53842

;; Return 1 if the operand is an indexed or indirect memory operand.

53843

(define_predicate "indexed_or_indirect_operand"

53844

(match_code "mem")

53845

@@ -535,6 +700,19 @@

53846

return indexed_or_indirect_address (op, mode);

53847

})

53848

53849

+;; Like indexed_or_indirect_operand, but also allow a GPR register if direct

53850

+;; moves are supported.

53851

+(define_predicate "reg_or_indexed_operand"

53852

+ (match_code "mem,reg")

53853

+{

53854

+ if (MEM_P (op))

53855

+ return indexed_or_indirect_operand (op, mode);

53856

+ else if (TARGET_DIRECT_MOVE)

53857

+ return register_operand (op, mode);

53858

+ return

53859

+ 0;

53860

+})

53861

+

53862

;; Return 1 if the operand is an indexed or indirect memory operand with an

53863

;; AND -16 in it, used to recognize when we need to switch to Altivec loads

53864

;; to realign loops instead of VSX (altivec silently ignores the bottom bits,

53865

@@ -560,6 +738,28 @@

53866

&& REG_P (XEXP (op, 1)))")

53867

(match_operand 0 "address_operand")))

53868

53869

+;; Return 1 if the operand is an index-form address.

53870

+(define_special_predicate "indexed_address"

53871

+ (match_test "(GET_CODE (op) == PLUS

53872

+ && REG_P (XEXP (op, 0))

53873

+ && REG_P (XEXP (op, 1)))"))

53874

+

53875

+;; Return 1 if the operand is a MEM with an update-form address. This may

53876

+;; also include update-indexed form.

53877

+(define_special_predicate "update_address_mem"

53878

+ (match_test "(MEM_P (op)

53879

+ && (GET_CODE (XEXP (op, 0)) == PRE_INC

53880

+ || GET_CODE (XEXP (op, 0)) == PRE_DEC

53881

+ || GET_CODE (XEXP (op, 0)) == PRE_MODIFY))"))

53882

+

53883

+;; Return 1 if the operand is a MEM with an update-indexed-form address. Note

53884

+;; that PRE_INC/PRE_DEC will always be non-indexed (i.e. non X-form) since the

53885

+;; increment is based on the mode size and will therefor always be a const.

53886

+(define_special_predicate "update_indexed_address_mem"

53887

+ (match_test "(MEM_P (op)

53888

+ && GET_CODE (XEXP (op, 0)) == PRE_MODIFY

53889

+ && indexed_address (XEXP (XEXP (op, 0), 1), mode))"))

53890

+

53891

;; Used for the destination of the fix_truncdfsi2 expander.

53892

;; If stfiwx will be used, the result goes to memory; otherwise,

53893

;; we're going to emit a store and a load of a subreg, so the dest is a

53894

@@ -883,7 +1083,8 @@

53895

(and (match_code "symbol_ref")

53896

(match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))

53897

&& ((SYMBOL_REF_LOCAL_P (op)

53898

- && (DEFAULT_ABI != ABI_AIX

53899

+ && ((DEFAULT_ABI != ABI_AIX

53900

+ && DEFAULT_ABI != ABI_ELFv2)

53901

|| !SYMBOL_REF_EXTERNAL_P (op)))

53902

|| (op == XEXP (DECL_RTL (current_function_decl),

53903

0)))")))

53904

@@ -1364,6 +1565,26 @@

53905

return 1;

53906

})

53907

53908

+;; Return 1 if OP is valid for crsave insn, known to be a PARALLEL.

53909

+(define_predicate "crsave_operation"

53910

+ (match_code "parallel")

53911

+{

53912

+ int count = XVECLEN (op, 0);

53913

+ int i;

53914

+

53915

+ for (i = 1; i < count; i++)

53916

+ {

53917

+ rtx exp = XVECEXP (op, 0, i);

53918

+

53919

+ if (GET_CODE (exp) != USE

53920

+ || GET_CODE (XEXP (exp, 0)) != REG

53921

+ || GET_MODE (XEXP (exp, 0)) != CCmode

53922

+ || ! CR_REGNO_P (REGNO (XEXP (exp, 0))))

53923

+ return 0;

53924

+ }

53925

+ return 1;

53926

+})

53927

+

53928

;; Return 1 if OP is valid for lmw insn, known to be a PARALLEL.

53929

(define_predicate "lmw_operation"

53930

(match_code "parallel")

53931

@@ -1534,3 +1755,99 @@

53932

53933

return GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_TOCREL;

53934

})

53935

+

53936

+;; Match the first insn (addis) in fusing the combination of addis and loads to

53937

+;; GPR registers on power8.

53938

+(define_predicate "fusion_gpr_addis"

53939

+ (match_code "const_int,high,plus")

53940

+{

53941

+ HOST_WIDE_INT value;

53942

+ rtx int_const;

53943

+

53944

+ if (GET_CODE (op) == HIGH)

53945

+ return 1;

53946

+

53947

+ if (CONST_INT_P (op))

53948

+ int_const = op;

53949

+

53950

+ else if (GET_CODE (op) == PLUS

53951

+ && base_reg_operand (XEXP (op, 0), Pmode)

53952

+ && CONST_INT_P (XEXP (op, 1)))

53953

+ int_const = XEXP (op, 1);

53954

+

53955

+ else

53956

+ return 0;

53957

+

53958

+ /* Power8 currently will only do the fusion if the top 11 bits of the addis

53959

+ value are all 1's or 0's. */

53960

+ value = INTVAL (int_const);

53961

+ if ((value & (HOST_WIDE_INT)0xffff) != 0)

53962

+ return 0;

53963

+

53964

+ if ((value & (HOST_WIDE_INT)0xffff0000) == 0)

53965

+ return 0;

53966

+

53967

+ return (IN_RANGE (value >> 16, -32, 31));

53968

+})

53969

+

53970

+;; Match the second insn (lbz, lhz, lwz, ld) in fusing the combination of addis

53971

+;; and loads to GPR registers on power8.

53972

+(define_predicate "fusion_gpr_mem_load"

53973

+ (match_code "mem,sign_extend,zero_extend")

53974

+{

53975

+ rtx addr;

53976

+

53977

+ /* Handle sign/zero extend. */

53978

+ if (GET_CODE (op) == ZERO_EXTEND

53979

+ || (TARGET_P8_FUSION_SIGN && GET_CODE (op) == SIGN_EXTEND))

53980

+ {

53981

+ op = XEXP (op, 0);

53982

+ mode = GET_MODE (op);

53983

+ }

53984

+

53985

+ if (!MEM_P (op))

53986

+ return 0;

53987

+

53988

+ switch (mode)

53989

+ {

53990

+ case QImode:

53991

+ case HImode:

53992

+ case SImode:

53993

+ break;

53994

+

53995

+ case DImode:

53996

+ if (!TARGET_POWERPC64)

53997

+ return 0;

53998

+ break;

53999

+

54000

+ default:

54001

+ return 0;

54002

+ }

54003

+

54004

+ addr = XEXP (op, 0);

54005

+ if (GET_CODE (addr) == PLUS)

54006

+ {

54007

+ rtx base = XEXP (addr, 0);

54008

+ rtx offset = XEXP (addr, 1);

54009

+

54010

+ return (base_reg_operand (base, GET_MODE (base))

54011

+ && satisfies_constraint_I (offset));

54012

+ }

54013

+

54014

+ else if (GET_CODE (addr) == LO_SUM)

54015

+ {

54016

+ rtx base = XEXP (addr, 0);

54017

+ rtx offset = XEXP (addr, 1);

54018

+

54019

+ if (!base_reg_operand (base, GET_MODE (base)))

54020

+ return 0;

54021

+

54022

+ else if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))

54023

+ return small_toc_ref (offset, GET_MODE (offset));

54024

+

54025

+ else if (TARGET_ELF && !TARGET_POWERPC64)

54026

+ return CONSTANT_P (offset);

54027

+ }

54028

+

54029

+ return 0;

54030

+})

54031

Index: gcc/config/rs6000/ppc-asm.h

54032

===================================================================

54033

--- a/src/gcc/config/rs6000/ppc-asm.h (.../tags/gcc_4_8_2_release)

54034

+++ b/src/gcc/config/rs6000/ppc-asm.h (.../branches/gcc-4_8-branch)

54035

@@ -256,7 +256,30 @@

54036

* the real function with one or two leading periods respectively.

54037

*/

54038

54039

-#if defined (__powerpc64__)

54040

+#if defined(__powerpc64__) && _CALL_ELF == 2

54041

+

54042

+/* Defining "toc" above breaks @toc in assembler code. */

54043

+#undef toc

54044

+

54045

+#define FUNC_NAME(name) GLUE(__USER_LABEL_PREFIX__,name)

54046

+#define JUMP_TARGET(name) FUNC_NAME(name)

54047

+#define FUNC_START(name) \

54048

+ .type FUNC_NAME(name),@function; \

54049

+ .globl FUNC_NAME(name); \

54050

+FUNC_NAME(name): \

54051

+0: addis 2,12,(.TOC.-0b)@ha; \

54052

+ addi 2,2,(.TOC.-0b)@l; \

54053

+ .localentry FUNC_NAME(name),.-FUNC_NAME(name)

54054

+

54055

+#define HIDDEN_FUNC(name) \

54056

+ FUNC_START(name) \

54057

+ .hidden FUNC_NAME(name);

54058

+

54059

+#define FUNC_END(name) \

54060

+ .size FUNC_NAME(name),.-FUNC_NAME(name)

54061

+

54062

+#elif defined (__powerpc64__)

54063

+

54064

#define FUNC_NAME(name) GLUE(.,name)

54065

#define JUMP_TARGET(name) FUNC_NAME(name)

54066

#define FUNC_START(name) \

54067

Index: gcc/config/rs6000/htm.md

54068

===================================================================

54069

--- a/src/gcc/config/rs6000/htm.md (.../tags/gcc_4_8_2_release)

54070

+++ b/src/gcc/config/rs6000/htm.md (.../branches/gcc-4_8-branch)

54071

@@ -0,0 +1,366 @@

54072

+;; Hardware Transactional Memory (HTM) patterns.

54073

54074

+;; Contributed by Peter Bergner <bergner@vnet.ibm.com>.

54075

+

54076

+;; This file is part of GCC.

54077

+

54078

+;; GCC is free software; you can redistribute it and/or modify it

54079

+;; under the terms of the GNU General Public License as published

54080

+;; by the Free Software Foundation; either version 3, or (at your

54081

+;; option) any later version.

54082

+

54083

+;; GCC is distributed in the hope that it will be useful, but WITHOUT

54084

+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY

54085

+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public

54086

+;; License for more details.

54087

+

54088

+;; You should have received a copy of the GNU General Public License

54089

+;; along with GCC; see the file COPYING3. If not see

54090

+;; <http://www.gnu.org/licenses/>.

54091

+

54092

+(define_constants

54093

+ [(TFHAR_SPR 128)

54094

+ (TFIAR_SPR 129)

54095

+ (TEXASR_SPR 130)

54096

+ (TEXASRU_SPR 131)

54097

+ (MAX_HTM_OPERANDS 4)

54098

+ ])

54099

+

54100

+;;

54101

+;; UNSPEC_VOLATILE usage

54102

+;;

54103

+

54104

+(define_c_enum "unspecv"

54105

+ [UNSPECV_HTM_TABORT

54106

+ UNSPECV_HTM_TABORTDC

54107

+ UNSPECV_HTM_TABORTDCI

54108

+ UNSPECV_HTM_TABORTWC

54109

+ UNSPECV_HTM_TABORTWCI

54110

+ UNSPECV_HTM_TBEGIN

54111

+ UNSPECV_HTM_TCHECK

54112

+ UNSPECV_HTM_TEND

54113

+ UNSPECV_HTM_TRECHKPT

54114

+ UNSPECV_HTM_TRECLAIM

54115

+ UNSPECV_HTM_TSR

54116

+ UNSPECV_HTM_MFSPR

54117

+ UNSPECV_HTM_MTSPR

54118

+ ])

54119

+

54120

+

54121

+(define_expand "tabort"

54122

+ [(set (match_dup 2)

54123

+ (unspec_volatile:CC [(match_operand:SI 1 "int_reg_operand" "")]

54124

+ UNSPECV_HTM_TABORT))

54125

+ (set (match_dup 3)

54126

+ (eq:SI (match_dup 2)

54127

+ (const_int 0)))

54128

+ (set (match_operand:SI 0 "int_reg_operand" "")

54129

+ (minus:SI (const_int 1) (match_dup 3)))]

54130

+ "TARGET_HTM"

54131

+{

54132

+ operands[2] = gen_rtx_REG (CCmode, CR0_REGNO);

54133

+ operands[3] = gen_reg_rtx (SImode);

54134

+})

54135

+

54136

+(define_insn "*tabort_internal"

54137

+ [(set (match_operand:CC 1 "cc_reg_operand" "=x")

54138

+ (unspec_volatile:CC [(match_operand:SI 0 "int_reg_operand" "r")]

54139

+ UNSPECV_HTM_TABORT))]

54140

+ "TARGET_HTM"

54141

+ "tabort. %0"

54142

+ [(set_attr "type" "htm")

54143

+ (set_attr "length" "4")])

54144

+

54145

+(define_expand "tabortdc"

54146

+ [(set (match_dup 4)

54147

+ (unspec_volatile:CC [(match_operand 1 "u5bit_cint_operand" "n")

54148

+ (match_operand:SI 2 "gpc_reg_operand" "r")

54149

+ (match_operand:SI 3 "gpc_reg_operand" "r")]

54150

+ UNSPECV_HTM_TABORTDC))

54151

+ (set (match_dup 5)

54152

+ (eq:SI (match_dup 4)

54153

+ (const_int 0)))

54154

+ (set (match_operand:SI 0 "int_reg_operand" "")

54155

+ (minus:SI (const_int 1) (match_dup 5)))]

54156

+ "TARGET_HTM"

54157

+{

54158

+ operands[4] = gen_rtx_REG (CCmode, CR0_REGNO);

54159

+ operands[5] = gen_reg_rtx (SImode);

54160

+})

54161

+

54162

+(define_insn "*tabortdc_internal"

54163

+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")

54164

+ (unspec_volatile:CC [(match_operand 0 "u5bit_cint_operand" "n")

54165

+ (match_operand:SI 1 "gpc_reg_operand" "r")

54166

+ (match_operand:SI 2 "gpc_reg_operand" "r")]

54167

+ UNSPECV_HTM_TABORTDC))]

54168

+ "TARGET_HTM"

54169

+ "tabortdc. %0,%1,%2"

54170

+ [(set_attr "type" "htm")

54171

+ (set_attr "length" "4")])

54172

+

54173

+(define_expand "tabortdci"

54174

+ [(set (match_dup 4)

54175

+ (unspec_volatile:CC [(match_operand 1 "u5bit_cint_operand" "n")

54176

+ (match_operand:SI 2 "gpc_reg_operand" "r")

54177

+ (match_operand 3 "s5bit_cint_operand" "n")]

54178

+ UNSPECV_HTM_TABORTDCI))

54179

+ (set (match_dup 5)

54180

+ (eq:SI (match_dup 4)

54181

+ (const_int 0)))

54182

+ (set (match_operand:SI 0 "int_reg_operand" "")

54183

+ (minus:SI (const_int 1) (match_dup 5)))]

54184

+ "TARGET_HTM"

54185

+{

54186

+ operands[4] = gen_rtx_REG (CCmode, CR0_REGNO);

54187

+ operands[5] = gen_reg_rtx (SImode);

54188

+})

54189

+

54190

+(define_insn "*tabortdci_internal"

54191

+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")

54192

+ (unspec_volatile:CC [(match_operand 0 "u5bit_cint_operand" "n")

54193

+ (match_operand:SI 1 "gpc_reg_operand" "r")

54194

+ (match_operand 2 "s5bit_cint_operand" "n")]

54195

+ UNSPECV_HTM_TABORTDCI))]

54196

+ "TARGET_HTM"

54197

+ "tabortdci. %0,%1,%2"

54198

+ [(set_attr "type" "htm")

54199

+ (set_attr "length" "4")])

54200

+

54201

+(define_expand "tabortwc"

54202

+ [(set (match_dup 4)

54203

+ (unspec_volatile:CC [(match_operand 1 "u5bit_cint_operand" "n")

54204

+ (match_operand:SI 2 "gpc_reg_operand" "r")

54205

+ (match_operand:SI 3 "gpc_reg_operand" "r")]

54206

+ UNSPECV_HTM_TABORTWC))

54207

+ (set (match_dup 5)

54208

+ (eq:SI (match_dup 4)

54209

+ (const_int 0)))

54210

+ (set (match_operand:SI 0 "int_reg_operand" "")

54211

+ (minus:SI (const_int 1) (match_dup 5)))]

54212

+ "TARGET_HTM"

54213

+{

54214

+ operands[4] = gen_rtx_REG (CCmode, CR0_REGNO);

54215

+ operands[5] = gen_reg_rtx (SImode);

54216

+})

54217

+

54218

+(define_insn "*tabortwc_internal"

54219

+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")

54220

+ (unspec_volatile:CC [(match_operand 0 "u5bit_cint_operand" "n")

54221

+ (match_operand:SI 1 "gpc_reg_operand" "r")

54222

+ (match_operand:SI 2 "gpc_reg_operand" "r")]

54223

+ UNSPECV_HTM_TABORTWC))]

54224

+ "TARGET_HTM"

54225

+ "tabortwc. %0,%1,%2"

54226

+ [(set_attr "type" "htm")

54227

+ (set_attr "length" "4")])

54228

+

54229

+(define_expand "tabortwci"

54230

+ [(set (match_dup 4)

54231

+ (unspec_volatile:CC [(match_operand 1 "u5bit_cint_operand" "n")

54232

+ (match_operand:SI 2 "gpc_reg_operand" "r")

54233

+ (match_operand 3 "s5bit_cint_operand" "n")]

54234

+ UNSPECV_HTM_TABORTWCI))

54235

+ (set (match_dup 5)

54236

+ (eq:SI (match_dup 4)

54237

+ (const_int 0)))

54238

+ (set (match_operand:SI 0 "int_reg_operand" "")

54239

+ (minus:SI (const_int 1) (match_dup 5)))]

54240

+ "TARGET_HTM"

54241

+{

54242

+ operands[4] = gen_rtx_REG (CCmode, CR0_REGNO);

54243

+ operands[5] = gen_reg_rtx (SImode);

54244

+})

54245

+

54246

+(define_expand "ttest"

54247

+ [(set (match_dup 1)

54248

+ (unspec_volatile:CC [(const_int 0)

54249

+ (reg:SI 0)

54250

+ (const_int 0)]

54251

+ UNSPECV_HTM_TABORTWCI))

54252

+ (set (subreg:CC (match_dup 2) 0) (match_dup 1))

54253

+ (set (match_dup 3) (lshiftrt:SI (match_dup 2) (const_int 24)))

54254

+ (parallel [(set (match_operand:SI 0 "int_reg_operand" "")

54255

+ (and:SI (match_dup 3) (const_int 15)))

54256

+ (clobber (scratch:CC))])]

54257

+ "TARGET_HTM"

54258

+{

54259

+ operands[1] = gen_rtx_REG (CCmode, CR0_REGNO);

54260

+ operands[2] = gen_reg_rtx (SImode);

54261

+ operands[3] = gen_reg_rtx (SImode);

54262

+})

54263

+

54264

+(define_insn "*tabortwci_internal"

54265

+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")

54266

+ (unspec_volatile:CC [(match_operand 0 "u5bit_cint_operand" "n")

54267

+ (match_operand:SI 1 "gpc_reg_operand" "r")

54268

+ (match_operand 2 "s5bit_cint_operand" "n")]

54269

+ UNSPECV_HTM_TABORTWCI))]

54270

+ "TARGET_HTM"

54271

+ "tabortwci. %0,%1,%2"

54272

+ [(set_attr "type" "htm")

54273

+ (set_attr "length" "4")])

54274

+

54275

+(define_expand "tbegin"

54276

+ [(set (match_dup 2)

54277

+ (unspec_volatile:CC [(match_operand 1 "const_0_to_1_operand" "n")]

54278

+ UNSPECV_HTM_TBEGIN))

54279

+ (set (match_dup 3)

54280

+ (eq:SI (match_dup 2)

54281

+ (const_int 0)))

54282

+ (set (match_operand:SI 0 "int_reg_operand" "")

54283

+ (minus:SI (const_int 1) (match_dup 3)))]

54284

+ "TARGET_HTM"

54285

+{

54286

+ operands[2] = gen_rtx_REG (CCmode, CR0_REGNO);

54287

+ operands[3] = gen_reg_rtx (SImode);

54288

+})

54289

+

54290

+(define_insn "*tbegin_internal"

54291

+ [(set (match_operand:CC 1 "cc_reg_operand" "=x")

54292

+ (unspec_volatile:CC [(match_operand 0 "const_0_to_1_operand" "n")]

54293

+ UNSPECV_HTM_TBEGIN))]

54294

+ "TARGET_HTM"

54295

+ "tbegin. %0"

54296

+ [(set_attr "type" "htm")

54297

+ (set_attr "length" "4")])

54298

+

54299

+(define_expand "tcheck"

54300

+ [(set (match_dup 2)

54301

+ (unspec_volatile:CC [(match_operand 1 "u3bit_cint_operand" "n")]

54302

+ UNSPECV_HTM_TCHECK))

54303

+ (set (match_dup 3)

54304

+ (eq:SI (match_dup 2)

54305

+ (const_int 0)))

54306

+ (set (match_operand:SI 0 "int_reg_operand" "")

54307

+ (minus:SI (const_int 1) (match_dup 3)))]

54308

+ "TARGET_HTM"

54309

+{

54310

+ operands[2] = gen_rtx_REG (CCmode, CR0_REGNO);

54311

+ operands[3] = gen_reg_rtx (SImode);

54312

+})

54313

+

54314

+(define_insn "*tcheck_internal"

54315

+ [(set (match_operand:CC 1 "cc_reg_operand" "=x")

54316

+ (unspec_volatile:CC [(match_operand 0 "u3bit_cint_operand" "n")]

54317

+ UNSPECV_HTM_TCHECK))]

54318

+ "TARGET_HTM"

54319

+ "tcheck. %0"

54320

+ [(set_attr "type" "htm")

54321

+ (set_attr "length" "4")])

54322

+

54323

+(define_expand "tend"

54324

+ [(set (match_dup 2)

54325

+ (unspec_volatile:CC [(match_operand 1 "const_0_to_1_operand" "n")]

54326

+ UNSPECV_HTM_TEND))

54327

+ (set (match_dup 3)

54328

+ (eq:SI (match_dup 2)

54329

+ (const_int 0)))

54330

+ (set (match_operand:SI 0 "int_reg_operand" "")

54331

+ (minus:SI (const_int 1) (match_dup 3)))]

54332

+ "TARGET_HTM"

54333

+{

54334

+ operands[2] = gen_rtx_REG (CCmode, CR0_REGNO);

54335

+ operands[3] = gen_reg_rtx (SImode);

54336

+})

54337

+

54338

+(define_insn "*tend_internal"

54339

+ [(set (match_operand:CC 1 "cc_reg_operand" "=x")

54340

+ (unspec_volatile:CC [(match_operand 0 "const_0_to_1_operand" "n")]

54341

+ UNSPECV_HTM_TEND))]

54342

+ "TARGET_HTM"

54343

+ "tend. %0"

54344

+ [(set_attr "type" "htm")

54345

+ (set_attr "length" "4")])

54346

+

54347

+(define_expand "trechkpt"

54348

+ [(set (match_dup 1)

54349

+ (unspec_volatile:CC [(const_int 0)]

54350

+ UNSPECV_HTM_TRECHKPT))

54351

+ (set (match_dup 2)

54352

+ (eq:SI (match_dup 1)

54353

+ (const_int 0)))

54354

+ (set (match_operand:SI 0 "int_reg_operand" "")

54355

+ (minus:SI (const_int 1) (match_dup 2)))]

54356

+ "TARGET_HTM"

54357

+{

54358

+ operands[1] = gen_rtx_REG (CCmode, CR0_REGNO);

54359

+ operands[2] = gen_reg_rtx (SImode);

54360

+})

54361

+

54362

+(define_insn "*trechkpt_internal"

54363

+ [(set (match_operand:CC 0 "cc_reg_operand" "=x")

54364

+ (unspec_volatile:CC [(const_int 0)]

54365

+ UNSPECV_HTM_TRECHKPT))]

54366

+ "TARGET_HTM"

54367

+ "trechkpt."

54368

+ [(set_attr "type" "htm")

54369

+ (set_attr "length" "4")])

54370

+

54371

+(define_expand "treclaim"

54372

+ [(set (match_dup 2)

54373

+ (unspec_volatile:CC [(match_operand:SI 1 "gpc_reg_operand" "r")]

54374

+ UNSPECV_HTM_TRECLAIM))

54375

+ (set (match_dup 3)

54376

+ (eq:SI (match_dup 2)

54377

+ (const_int 0)))

54378

+ (set (match_operand:SI 0 "int_reg_operand" "")

54379

+ (minus:SI (const_int 1) (match_dup 3)))]

54380

+ "TARGET_HTM"

54381

+{

54382

+ operands[2] = gen_rtx_REG (CCmode, CR0_REGNO);

54383

+ operands[3] = gen_reg_rtx (SImode);

54384

+})

54385

+

54386

+(define_insn "*treclaim_internal"

54387

+ [(set (match_operand:CC 1 "cc_reg_operand" "=x")

54388

+ (unspec_volatile:CC [(match_operand:SI 0 "gpc_reg_operand" "r")]

54389

+ UNSPECV_HTM_TRECLAIM))]

54390

+ "TARGET_HTM"

54391

+ "treclaim. %0"

54392

+ [(set_attr "type" "htm")

54393

+ (set_attr "length" "4")])

54394

+

54395

+(define_expand "tsr"

54396

+ [(set (match_dup 2)

54397

+ (unspec_volatile:CC [(match_operand 1 "const_0_to_1_operand" "n")]

54398

+ UNSPECV_HTM_TSR))

54399

+ (set (match_dup 3)

54400

+ (eq:SI (match_dup 2)

54401

+ (const_int 0)))

54402

+ (set (match_operand:SI 0 "int_reg_operand" "")

54403

+ (minus:SI (const_int 1) (match_dup 3)))]

54404

+ "TARGET_HTM"

54405

+{

54406

+ operands[2] = gen_rtx_REG (CCmode, CR0_REGNO);

54407

+ operands[3] = gen_reg_rtx (SImode);

54408

+})

54409

+

54410

+(define_insn "*tsr_internal"

54411

+ [(set (match_operand:CC 1 "cc_reg_operand" "=x")

54412

+ (unspec_volatile:CC [(match_operand 0 "const_0_to_1_operand" "n")]

54413

+ UNSPECV_HTM_TSR))]

54414

+ "TARGET_HTM"

54415

+ "tsr. %0"

54416

+ [(set_attr "type" "htm")

54417

+ (set_attr "length" "4")])

54418

+

54419

+(define_insn "htm_mfspr_<mode>"

54420

+ [(set (match_operand:P 0 "gpc_reg_operand" "=r")

54421

+ (unspec_volatile:P [(match_operand 1 "u10bit_cint_operand" "n")

54422

+ (match_operand:P 2 "htm_spr_reg_operand" "")]

54423

+ UNSPECV_HTM_MFSPR))]

54424

+ "TARGET_HTM"

54425

+ "mfspr %0,%1";

54426

+ [(set_attr "type" "htm")

54427

+ (set_attr "length" "4")])

54428

+

54429

+(define_insn "htm_mtspr_<mode>"

54430

+ [(set (match_operand:P 2 "htm_spr_reg_operand" "")

54431

+ (unspec_volatile:P [(match_operand:P 0 "gpc_reg_operand" "r")

54432

+ (match_operand 1 "u10bit_cint_operand" "n")]

54433

+ UNSPECV_HTM_MTSPR))]

54434

+ "TARGET_HTM"

54435

+ "mtspr %1,%0";

54436

+ [(set_attr "type" "htm")

54437

+ (set_attr "length" "4")])

54438

Index: gcc/config/rs6000/rs6000-modes.def

54439

===================================================================

54440

--- a/src/gcc/config/rs6000/rs6000-modes.def (.../tags/gcc_4_8_2_release)

54441

+++ b/src/gcc/config/rs6000/rs6000-modes.def (.../branches/gcc-4_8-branch)

54442

@@ -38,6 +38,12 @@

54443

VECTOR_MODES (INT, 16); /* V16QI V8HI V4SI V2DI */

54444

VECTOR_MODES (INT, 32); /* V32QI V16HI V8SI V4DI */

54445

VECTOR_MODE (INT, DI, 1);

54446

+VECTOR_MODE (INT, TI, 1);

54447

VECTOR_MODES (FLOAT, 8); /* V4HF V2SF */

54448

VECTOR_MODES (FLOAT, 16); /* V8HF V4SF V2DF */

54449

VECTOR_MODES (FLOAT, 32); /* V16HF V8SF V4DF */

54450

+

54451

+/* Replacement for TImode that only is allowed in GPRs. We also use PTImode

54452

+ for quad memory atomic operations to force getting an even/odd register

54453

+ combination. */

54454

+PARTIAL_INT_MODE (TI);

54455

Index: gcc/config/rs6000/rs6000-cpus.def

54456

===================================================================

54457

--- a/src/gcc/config/rs6000/rs6000-cpus.def (.../tags/gcc_4_8_2_release)

54458

+++ b/src/gcc/config/rs6000/rs6000-cpus.def (.../branches/gcc-4_8-branch)

54459

@@ -28,7 +28,7 @@

54460

ALTIVEC, since in general it isn't a win on power6. In ISA 2.04, fsel,

54461

fre, fsqrt, etc. were no longer documented as optional. Group masks by

54462

server and embedded. */

54463

-#define ISA_2_5_MASKS_EMBEDDED (ISA_2_2_MASKS \

54464

+#define ISA_2_5_MASKS_EMBEDDED (ISA_2_4_MASKS \

54465

| OPTION_MASK_CMPB \

54466

| OPTION_MASK_RECIP_PRECISION \

54467

| OPTION_MASK_PPC_GFXOPT \

54468

@@ -38,6 +38,8 @@

54469

54470

/* For ISA 2.06, don't add ISEL, since in general it isn't a win, but

54471

altivec is a win so enable it. */

54472

+ /* OPTION_MASK_VSX_TIMODE should be set, but disable it for now until

54473

+ PR 58587 is fixed. */

54474

#define ISA_2_6_MASKS_EMBEDDED (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_POPCNTD)

54475

#define ISA_2_6_MASKS_SERVER (ISA_2_5_MASKS_SERVER \

54476

| OPTION_MASK_POPCNTD \

54477

@@ -44,6 +46,16 @@

54478

| OPTION_MASK_ALTIVEC \

54479

| OPTION_MASK_VSX)

54480

54481

+/* For now, don't provide an embedded version of ISA 2.07. */

54482

+#define ISA_2_7_MASKS_SERVER (ISA_2_6_MASKS_SERVER \

54483

+ | OPTION_MASK_P8_FUSION \

54484

+ | OPTION_MASK_P8_VECTOR \

54485

+ | OPTION_MASK_CRYPTO \

54486

+ | OPTION_MASK_DIRECT_MOVE \

54487

+ | OPTION_MASK_HTM \

54488

+ | OPTION_MASK_QUAD_MEMORY \

54489

+ | OPTION_MASK_QUAD_MEMORY_ATOMIC)

54490

+

54491

#define POWERPC_7400_MASK (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC)

54492

54493

/* Deal with ports that do not have -mstrict-align. */

54494

@@ -60,23 +72,30 @@

54495

/* Mask of all options to set the default isa flags based on -mcpu=<xxx>. */

54496

#define POWERPC_MASKS (OPTION_MASK_ALTIVEC \

54497

| OPTION_MASK_CMPB \

54498

+ | OPTION_MASK_CRYPTO \

54499

| OPTION_MASK_DFP \

54500

+ | OPTION_MASK_DIRECT_MOVE \

54501

| OPTION_MASK_DLMZB \

54502

| OPTION_MASK_FPRND \

54503

+ | OPTION_MASK_HTM \

54504

| OPTION_MASK_ISEL \

54505

| OPTION_MASK_MFCRF \

54506

| OPTION_MASK_MFPGPR \

54507

| OPTION_MASK_MULHW \

54508

| OPTION_MASK_NO_UPDATE \

54509

+ | OPTION_MASK_P8_FUSION \

54510

+ | OPTION_MASK_P8_VECTOR \

54511

| OPTION_MASK_POPCNTB \

54512

| OPTION_MASK_POPCNTD \

54513

| OPTION_MASK_POWERPC64 \

54514

| OPTION_MASK_PPC_GFXOPT \

54515

| OPTION_MASK_PPC_GPOPT \

54516

+ | OPTION_MASK_QUAD_MEMORY \

54517

| OPTION_MASK_RECIP_PRECISION \

54518

| OPTION_MASK_SOFT_FLOAT \

54519

| OPTION_MASK_STRICT_ALIGN_OPTIONAL \

54520

- | OPTION_MASK_VSX)

54521

+ | OPTION_MASK_VSX \

54522

+ | OPTION_MASK_VSX_TIMODE)

54523

54524

#endif

54525

54526

@@ -166,10 +185,7 @@

54527

POWERPC_7400_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_MFCRF

54528

54529

| MASK_VSX | MASK_RECIP_PRECISION)

54530

-RS6000_CPU ("power8", PROCESSOR_POWER7, /* Don't add MASK_ISEL by default */

54531

- POWERPC_7400_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_MFCRF

54532

54533

- | MASK_VSX | MASK_RECIP_PRECISION)

54534

+RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER)

54535

RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0)

54536

RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT | MASK_POWERPC64)

54537

RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT | MASK_POWERPC64)

54538

Index: gcc/config/rs6000/t-linux64bele

54539

===================================================================

54540

--- a/src/gcc/config/rs6000/t-linux64bele (.../tags/gcc_4_8_2_release)

54541

+++ b/src/gcc/config/rs6000/t-linux64bele (.../branches/gcc-4_8-branch)

54542

@@ -0,0 +1,7 @@

54543

+#rs6000/t-linux64end

54544

+

54545

+MULTILIB_OPTIONS += mlittle

54546

+MULTILIB_DIRNAMES += le

54547

+MULTILIB_OSDIRNAMES += $(subst =,.mlittle=,$(subst lible32,lib32le,$(subst lible64,lib64le,$(subst lib,lible,$(subst -linux,le-linux,$(MULTILIB_OSDIRNAMES))))))

54548

+MULTILIB_OSDIRNAMES += $(subst $(if $(findstring 64,$(target)),m64,m32).,,$(filter $(if $(findstring 64,$(target)),m64,m32).mlittle%,$(MULTILIB_OSDIRNAMES)))

54549

+MULTILIB_MATCHES := ${MULTILIB_MATCHES_ENDIAN}

54550

Index: gcc/config/rs6000/htmintrin.h

54551

===================================================================

54552

--- a/src/gcc/config/rs6000/htmintrin.h (.../tags/gcc_4_8_2_release)

54553

+++ b/src/gcc/config/rs6000/htmintrin.h (.../branches/gcc-4_8-branch)

54554

@@ -0,0 +1,131 @@

54555

+/* Hardware Transactional Memory (HTM) intrinsics.

54556

54557

+ Contributed by Peter Bergner <bergner@vnet.ibm.com>.

54558

+

54559

+ This file is free software; you can redistribute it and/or modify it under

54560

+ the terms of the GNU General Public License as published by the Free

54561

+ Software Foundation; either version 3 of the License, or (at your option)

54562

+ any later version.

54563

+

54564

+ This file is distributed in the hope that it will be useful, but WITHOUT

54565

+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

54566

+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License

54567

+ for more details.

54568

+

54569

+ Under Section 7 of GPL version 3, you are granted additional

54570

+ permissions described in the GCC Runtime Library Exception, version

54571

+ 3.1, as published by the Free Software Foundation.

54572

+

54573

+ You should have received a copy of the GNU General Public License and

54574

+ a copy of the GCC Runtime Library Exception along with this program;

54575

+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see

54576

+ <http://www.gnu.org/licenses/>. */

54577

+

54578

+#ifndef __HTM__

54579

+# error "HTM instruction set not enabled"

54580

+#endif /* __HTM__ */

54581

+

54582

+#ifndef _HTMINTRIN_H

54583

+#define _HTMINTRIN_H

54584

+

54585

+#include <stdint.h>

54586

+

54587

+typedef uint64_t texasr_t;

54588

+typedef uint32_t texasru_t;

54589

+typedef uint32_t texasrl_t;

54590

+typedef uintptr_t tfiar_t;

54591

+typedef uintptr_t tfhar_t;

54592

+

54593

+#define _HTM_STATE(CR0) ((CR0 >> 1) & 0x3)

54594

+#define _HTM_NONTRANSACTIONAL 0x0

54595

+#define _HTM_SUSPENDED 0x1

54596

+#define _HTM_TRANSACTIONAL 0x2

54597

+

54598

+/* The following macros use the IBM bit numbering for BITNUM

54599

+ as used in the ISA documentation. */

54600

+

54601

+#define _TEXASR_EXTRACT_BITS(TEXASR,BITNUM,SIZE) \

54602

+ (((TEXASR) >> (63-(BITNUM))) & ((1<<(SIZE))-1))

54603

+#define _TEXASRU_EXTRACT_BITS(TEXASR,BITNUM,SIZE) \

54604

+ (((TEXASR) >> (31-(BITNUM))) & ((1<<(SIZE))-1))

54605

+

54606

+#define _TEXASR_FAILURE_CODE(TEXASR) \

54607

+ _TEXASR_EXTRACT_BITS(TEXASR, 7, 8)

54608

+#define _TEXASRU_FAILURE_CODE(TEXASRU) \

54609

+ _TEXASRU_EXTRACT_BITS(TEXASRU, 7, 8)

54610

+

54611

+#define _TEXASR_FAILURE_PERSISTENT(TEXASR) \

54612

+ _TEXASR_EXTRACT_BITS(TEXASR, 7, 1)

54613

+#define _TEXASRU_FAILURE_PERSISTENT(TEXASRU) \

54614

+ _TEXASRU_EXTRACT_BITS(TEXASRU, 7, 1)

54615

+

54616

+#define _TEXASR_DISALLOWED(TEXASR) \

54617

+ _TEXASR_EXTRACT_BITS(TEXASR, 8, 1)

54618

+#define _TEXASRU_DISALLOWED(TEXASRU) \

54619

+ _TEXASRU_EXTRACT_BITS(TEXASRU, 8, 1)

54620

+

54621

+#define _TEXASR_NESTING_OVERFLOW(TEXASR) \

54622

+ _TEXASR_EXTRACT_BITS(TEXASR, 9, 1)

54623

+#define _TEXASRU_NESTING_OVERFLOW(TEXASRU) \

54624

+ _TEXASRU_EXTRACT_BITS(TEXASRU, 9, 1)

54625

+

54626

+#define _TEXASR_FOOTPRINT_OVERFLOW(TEXASR) \

54627

+ _TEXASR_EXTRACT_BITS(TEXASR, 10, 1)

54628

+#define _TEXASRU_FOOTPRINT_OVERFLOW(TEXASRU) \

54629

+ _TEXASRU_EXTRACT_BITS(TEXASRU, 10, 1)

54630

+

54631

+#define _TEXASR_SELF_INDUCED_CONFLICT(TEXASR) \

54632

+ _TEXASR_EXTRACT_BITS(TEXASR, 11, 1)

54633

+#define _TEXASRU_SELF_INDUCED_CONFLICT(TEXASRU) \

54634

+ _TEXASRU_EXTRACT_BITS(TEXASRU, 11, 1)

54635

+

54636

+#define _TEXASR_NON_TRANSACTIONAL_CONFLICT(TEXASR) \

54637

+ _TEXASR_EXTRACT_BITS(TEXASR, 12, 1)

54638

+#define _TEXASRU_NON_TRANSACTIONAL_CONFLICT(TEXASRU) \

54639

+ _TEXASRU_EXTRACT_BITS(TEXASRU, 12, 1)

54640

+

54641

+#define _TEXASR_TRANSACTION_CONFLICT(TEXASR) \

54642

+ _TEXASR_EXTRACT_BITS(TEXASR, 13, 1)

54643

+#define _TEXASRU_TRANSACTION_CONFLICT(TEXASRU) \

54644

+ _TEXASRU_EXTRACT_BITS(TEXASRU, 13, 1)

54645

+

54646

+#define _TEXASR_TRANSLATION_INVALIDATION_CONFLICT(TEXASR) \

54647

+ _TEXASR_EXTRACT_BITS(TEXASR, 14, 1)

54648

+#define _TEXASRU_TRANSLATION_INVALIDATION_CONFLICT(TEXASRU) \

54649

+ _TEXASRU_EXTRACT_BITS(TEXASRU, 14, 1)

54650

+

54651

+#define _TEXASR_IMPLEMENTAION_SPECIFIC(TEXASR) \

54652

+ _TEXASR_EXTRACT_BITS(TEXASR, 15, 1)

54653

+#define _TEXASRU_IMPLEMENTAION_SPECIFIC(TEXASRU) \

54654

+ _TEXASRU_EXTRACT_BITS(TEXASRU, 15, 1)

54655

+

54656

+#define _TEXASR_INSTRUCTION_FETCH_CONFLICT(TEXASR) \

54657

+ _TEXASR_EXTRACT_BITS(TEXASR, 16, 1)

54658

+#define _TEXASRU_INSTRUCTION_FETCH_CONFLICT(TEXASRU) \

54659

+ _TEXASRU_EXTRACT_BITS(TEXASRU, 16, 1)

54660

+

54661

+#define _TEXASR_ABORT(TEXASR) \

54662

+ _TEXASR_EXTRACT_BITS(TEXASR, 31, 1)

54663

+#define _TEXASRU_ABORT(TEXASRU) \

54664

+ _TEXASRU_EXTRACT_BITS(TEXASRU, 31, 1)

54665

+

54666

+

54667

+#define _TEXASR_SUSPENDED(TEXASR) \

54668

+ _TEXASR_EXTRACT_BITS(TEXASR, 32, 1)

54669

+

54670

+#define _TEXASR_PRIVILEGE(TEXASR) \

54671

+ _TEXASR_EXTRACT_BITS(TEXASR, 35, 2)

54672

+

54673

+#define _TEXASR_FAILURE_SUMMARY(TEXASR) \

54674

+ _TEXASR_EXTRACT_BITS(TEXASR, 36, 1)

54675

+

54676

+#define _TEXASR_TFIAR_EXACT(TEXASR) \

54677

+ _TEXASR_EXTRACT_BITS(TEXASR, 37, 1)

54678

+

54679

+#define _TEXASR_ROT(TEXASR) \

54680

+ _TEXASR_EXTRACT_BITS(TEXASR, 38, 1)

54681

+

54682

+#define _TEXASR_TRANSACTION_LEVEL(TEXASR) \

54683

+ _TEXASR_EXTRACT_BITS(TEXASR, 63, 12)

54684

+

54685

+#endif /* _HTMINTRIN_H */

54686

Index: gcc/config/rs6000/rs6000-protos.h

54687

===================================================================

54688

--- a/src/gcc/config/rs6000/rs6000-protos.h (.../tags/gcc_4_8_2_release)

54689

+++ b/src/gcc/config/rs6000/rs6000-protos.h (.../branches/gcc-4_8-branch)

54690

@@ -50,12 +50,19 @@

54691

extern rtx find_addr_reg (rtx);

54692

extern rtx gen_easy_altivec_constant (rtx);

54693

extern const char *output_vec_const_move (rtx *);

54694

+extern const char *rs6000_output_move_128bit (rtx *);

54695

+extern bool rs6000_move_128bit_ok_p (rtx []);

54696

+extern bool rs6000_split_128bit_ok_p (rtx []);

54697

extern void rs6000_expand_vector_init (rtx, rtx);

54698

extern void paired_expand_vector_init (rtx, rtx);

54699

extern void rs6000_expand_vector_set (rtx, rtx, int);

54700

extern void rs6000_expand_vector_extract (rtx, rtx, int);

54701

extern bool altivec_expand_vec_perm_const (rtx op[4]);

54702

+extern void altivec_expand_vec_perm_le (rtx op[4]);

54703

extern bool rs6000_expand_vec_perm_const (rtx op[4]);

54704

+extern void altivec_expand_lvx_be (rtx, rtx, enum machine_mode, unsigned);

54705

+extern void altivec_expand_stvx_be (rtx, rtx, enum machine_mode, unsigned);

54706

+extern void altivec_expand_stvex_be (rtx, rtx, enum machine_mode, unsigned);

54707

extern void rs6000_expand_extract_even (rtx, rtx, rtx);

54708

extern void rs6000_expand_interleave (rtx, rtx, rtx, bool);

54709

extern void build_mask64_2_operands (rtx, rtx *);

54710

@@ -70,6 +77,11 @@

54711

extern int registers_ok_for_quad_peep (rtx, rtx);

54712

extern int mems_ok_for_quad_peep (rtx, rtx);

54713

extern bool gpr_or_gpr_p (rtx, rtx);

54714

+extern bool direct_move_p (rtx, rtx);

54715

+extern bool quad_load_store_p (rtx, rtx);

54716

+extern bool fusion_gpr_load_p (rtx *, bool);

54717

+extern void expand_fusion_gpr_load (rtx *);

54718

+extern const char *emit_fusion_gpr_load (rtx *);

54719

extern enum reg_class (*rs6000_preferred_reload_class_ptr) (rtx,

54720

enum reg_class);

54721

extern enum reg_class (*rs6000_secondary_reload_class_ptr) (enum reg_class,

54722

@@ -116,6 +128,7 @@

54723

extern void rs6000_fatal_bad_address (rtx);

54724

extern rtx create_TOC_reference (rtx, rtx);

54725

extern void rs6000_split_multireg_move (rtx, rtx);

54726

+extern void rs6000_emit_le_vsx_move (rtx, rtx, enum machine_mode);

54727

extern void rs6000_emit_move (rtx, rtx, enum machine_mode);

54728

extern rtx rs6000_secondary_memory_needed_rtx (enum machine_mode);

54729

extern rtx (*rs6000_legitimize_reload_address_ptr) (rtx, enum machine_mode,

54730

@@ -135,9 +148,11 @@

54731

extern rtx rs6000_address_for_altivec (rtx);

54732

extern rtx rs6000_allocate_stack_temp (enum machine_mode, bool, bool);

54733

extern int rs6000_loop_align (rtx);

54734

+extern void rs6000_split_logical (rtx [], enum rtx_code, bool, bool, bool, rtx);

54735

#endif /* RTX_CODE */

54736

54737

#ifdef TREE_CODE

54738

+extern unsigned int rs6000_data_alignment (tree, unsigned int, enum data_align);

54739

extern unsigned int rs6000_special_round_type_align (tree, unsigned int,

54740

unsigned int);

54741

extern unsigned int darwin_rs6000_special_round_type_align (tree, unsigned int,

54742

@@ -146,6 +161,7 @@

54743

extern rtx rs6000_libcall_value (enum machine_mode);

54744

extern rtx rs6000_va_arg (tree, tree);

54745

extern int function_ok_for_sibcall (tree);

54746

+extern int rs6000_reg_parm_stack_space (tree);

54747

extern void rs6000_elf_declare_function_name (FILE *, const char *, tree);

54748

extern bool rs6000_elf_in_small_data_p (const_tree);

54749

#ifdef ARGS_SIZE_RTX

54750

@@ -170,7 +186,8 @@

54751

extern void rs6000_emit_epilogue (int);

54752

extern void rs6000_emit_eh_reg_restore (rtx, rtx);

54753

extern const char * output_isel (rtx *);

54754

-extern void rs6000_call_indirect_aix (rtx, rtx, rtx);

54755

+extern void rs6000_call_aix (rtx, rtx, rtx, rtx);

54756

+extern void rs6000_sibcall_aix (rtx, rtx, rtx, rtx);

54757

extern void rs6000_aix_asm_output_dwarf_table_ref (char *);

54758

extern void get_ppc476_thunk_name (char name[32]);

54759

extern bool rs6000_overloaded_builtin_p (enum rs6000_builtins);

54760

Index: gcc/config/rs6000/t-rs6000

54761

===================================================================

54762

--- a/src/gcc/config/rs6000/t-rs6000 (.../tags/gcc_4_8_2_release)

54763

+++ b/src/gcc/config/rs6000/t-rs6000 (.../branches/gcc-4_8-branch)

54764

@@ -60,6 +60,7 @@

54765

$(srcdir)/config/rs6000/power5.md \

54766

$(srcdir)/config/rs6000/power6.md \

54767

$(srcdir)/config/rs6000/power7.md \

54768

+ $(srcdir)/config/rs6000/power8.md \

54769

$(srcdir)/config/rs6000/cell.md \

54770

$(srcdir)/config/rs6000/xfpu.md \

54771

$(srcdir)/config/rs6000/a2.md \

54772

@@ -70,6 +71,8 @@

54773

$(srcdir)/config/rs6000/vector.md \

54774

$(srcdir)/config/rs6000/vsx.md \

54775

$(srcdir)/config/rs6000/altivec.md \

54776

+ $(srcdir)/config/rs6000/crypto.md \

54777

+ $(srcdir)/config/rs6000/htm.md \

54778

$(srcdir)/config/rs6000/spe.md \

54779

$(srcdir)/config/rs6000/dfp.md \

54780

$(srcdir)/config/rs6000/paired.md

54781

Index: gcc/config/rs6000/htmxlintrin.h

54782

===================================================================

54783

--- a/src/gcc/config/rs6000/htmxlintrin.h (.../tags/gcc_4_8_2_release)

54784

+++ b/src/gcc/config/rs6000/htmxlintrin.h (.../branches/gcc-4_8-branch)

54785

@@ -0,0 +1,208 @@

54786

+/* XL compiler Hardware Transactional Memory (HTM) execution intrinsics.

54787

54788

+ Contributed by Peter Bergner <bergner@vnet.ibm.com>.

54789

+

54790

+ This file is free software; you can redistribute it and/or modify it under

54791

+ the terms of the GNU General Public License as published by the Free

54792

+ Software Foundation; either version 3 of the License, or (at your option)

54793

+ any later version.

54794

+

54795

+ This file is distributed in the hope that it will be useful, but WITHOUT

54796

+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

54797

+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License

54798

+ for more details.

54799

+

54800

+ Under Section 7 of GPL version 3, you are granted additional

54801

+ permissions described in the GCC Runtime Library Exception, version

54802

+ 3.1, as published by the Free Software Foundation.

54803

+

54804

+ You should have received a copy of the GNU General Public License and

54805

+ a copy of the GCC Runtime Library Exception along with this program;

54806

+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see

54807

+ <http://www.gnu.org/licenses/>. */

54808

+

54809

+#ifndef __HTM__

54810

+# error "HTM instruction set not enabled"

54811

+#endif /* __HTM__ */

54812

+

54813

+#ifndef _HTMXLINTRIN_H

54814

+#define _HTMXLINTRIN_H

54815

+

54816

+#include <stdint.h>

54817

+#include <htmintrin.h>

54818

+

54819

+#ifdef __cplusplus

54820

+extern "C" {

54821

+#endif

54822

+

54823

+#define _TEXASR_PTR(TM_BUF) \

54824

+ ((texasr_t *)((TM_BUF)+0))

54825

+#define _TEXASRU_PTR(TM_BUF) \

54826

+ ((texasru_t *)((TM_BUF)+0))

54827

+#define _TEXASRL_PTR(TM_BUF) \

54828

+ ((texasrl_t *)((TM_BUF)+4))

54829

+#define _TFIAR_PTR(TM_BUF) \

54830

+ ((tfiar_t *)((TM_BUF)+8))

54831

+

54832

+typedef char TM_buff_type[16];

54833

+

54834

+extern __inline long

54835

+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))

54836

+__TM_simple_begin (void)

54837

+{

54838

+ if (__builtin_expect (__builtin_tbegin (0), 1))

54839

+ return 1;

54840

+ return 0;

54841

+}

54842

+

54843

+extern __inline long

54844

+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))

54845

+__TM_begin (void* const TM_buff)

54846

+{

54847

+ *_TEXASRL_PTR (TM_buff) = 0;

54848

+ if (__builtin_expect (__builtin_tbegin (0), 1))

54849

+ return 1;

54850

+#ifdef __powerpc64__

54851

+ *_TEXASR_PTR (TM_buff) = __builtin_get_texasr ();

54852

+#else

54853

+ *_TEXASRU_PTR (TM_buff) = __builtin_get_texasru ();

54854

+ *_TEXASRL_PTR (TM_buff) = __builtin_get_texasr ();

54855

+#endif

54856

+ *_TFIAR_PTR (TM_buff) = __builtin_get_tfiar ();

54857

+ return 0;

54858

+}

54859

+

54860

+extern __inline long

54861

+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))

54862

+__TM_end (void)

54863

+{

54864

+ if (__builtin_expect (__builtin_tend (0), 1))

54865

+ return 1;

54866

+ return 0;

54867

+}

54868

+

54869

+extern __inline void

54870

+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))

54871

+__TM_abort (void)

54872

+{

54873

+ __builtin_tabort (0);

54874

+}

54875

+

54876

+extern __inline void

54877

+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))

54878

+__TM_named_abort (unsigned char const code)

54879

+{

54880

+ __builtin_tabort (code);

54881

+}

54882

+

54883

+extern __inline void

54884

+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))

54885

+__TM_resume (void)

54886

+{

54887

+ __builtin_tresume ();

54888

+}

54889

+

54890

+extern __inline void

54891

+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))

54892

+__TM_suspend (void)

54893

+{

54894

+ __builtin_tsuspend ();

54895

+}

54896

+

54897

+extern __inline long

54898

+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))

54899

+__TM_is_user_abort (void* const TM_buff)

54900

+{

54901

+ texasru_t texasru = *_TEXASRU_PTR (TM_buff);

54902

+ return _TEXASRU_ABORT (texasru);

54903

+}

54904

+

54905

+extern __inline long

54906

+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))

54907

+__TM_is_named_user_abort (void* const TM_buff, unsigned char *code)

54908

+{

54909

+ texasru_t texasru = *_TEXASRU_PTR (TM_buff);

54910

+

54911

+ *code = _TEXASRU_FAILURE_CODE (texasru);

54912

+ return _TEXASRU_ABORT (texasru);

54913

+}

54914

+

54915

+extern __inline long

54916

+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))

54917

+__TM_is_illegal (void* const TM_buff)

54918

+{

54919

+ texasru_t texasru = *_TEXASRU_PTR (TM_buff);

54920

+ return _TEXASRU_DISALLOWED (texasru);

54921

+}

54922

+

54923

+extern __inline long

54924

+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))

54925

+__TM_is_footprint_exceeded (void* const TM_buff)

54926

+{

54927

+ texasru_t texasru = *_TEXASRU_PTR (TM_buff);

54928

+ return _TEXASRU_FOOTPRINT_OVERFLOW (texasru);

54929

+}

54930

+

54931

+extern __inline long

54932

+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))

54933

+__TM_nesting_depth (void* const TM_buff)

54934

+{

54935

+ texasrl_t texasrl;

54936

+

54937

+ if (_HTM_STATE (__builtin_ttest ()) == _HTM_NONTRANSACTIONAL)

54938

+ {

54939

+ texasrl = *_TEXASRL_PTR (TM_buff);

54940

+ if (!_TEXASR_FAILURE_SUMMARY (texasrl))

54941

+ texasrl = 0;

54942

+ }

54943

+ else

54944

+ texasrl = (texasrl_t) __builtin_get_texasr ();

54945

+

54946

+ return _TEXASR_TRANSACTION_LEVEL (texasrl);

54947

+}

54948

+

54949

+extern __inline long

54950

+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))

54951

+__TM_is_nested_too_deep(void* const TM_buff)

54952

+{

54953

+ texasru_t texasru = *_TEXASRU_PTR (TM_buff);

54954

+ return _TEXASRU_NESTING_OVERFLOW (texasru);

54955

+}

54956

+

54957

+extern __inline long

54958

+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))

54959

+__TM_is_conflict(void* const TM_buff)

54960

+{

54961

+ texasru_t texasru = *_TEXASRU_PTR (TM_buff);

54962

+ /* Return TEXASR bits 11 (Self-Induced Conflict) through

54963

+ 14 (Translation Invalidation Conflict). */

54964

+ return (_TEXASRU_EXTRACT_BITS (texasru, 14, 4)) ? 1 : 0;

54965

+}

54966

+

54967

+extern __inline long

54968

+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))

54969

+__TM_is_failure_persistent(void* const TM_buff)

54970

+{

54971

+ texasru_t texasru = *_TEXASRU_PTR (TM_buff);

54972

+ return _TEXASRU_FAILURE_PERSISTENT (texasru);

54973

+}

54974

+

54975

+extern __inline long

54976

+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))

54977

+__TM_failure_address(void* const TM_buff)

54978

+{

54979

+ return *_TFIAR_PTR (TM_buff);

54980

+}

54981

+

54982

+extern __inline long long

54983

+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))

54984

+__TM_failure_code(void* const TM_buff)

54985

+{

54986

+ return *_TEXASR_PTR (TM_buff);

54987

+}

54988

+

54989

+#ifdef __cplusplus

54990

+}

54991

+#endif

54992

+

54993

+#endif /* _HTMXLINTRIN_H */

54994

Index: gcc/config/rs6000/rs6000-builtin.def

54995

===================================================================

54996

--- a/src/gcc/config/rs6000/rs6000-builtin.def (.../tags/gcc_4_8_2_release)

54997

+++ b/src/gcc/config/rs6000/rs6000-builtin.def (.../branches/gcc-4_8-branch)

54998

@@ -30,7 +30,8 @@

54999

RS6000_BUILTIN_A -- ABS builtins

55000

RS6000_BUILTIN_D -- DST builtins

55001

RS6000_BUILTIN_E -- SPE EVSEL builtins.

55002

- RS6000_BUILTIN_P -- Altivec and VSX predicate builtins

55003

+ RS6000_BUILTIN_H -- HTM builtins

55004

+ RS6000_BUILTIN_P -- Altivec, VSX, ISA 2.07 vector predicate builtins

55005

RS6000_BUILTIN_Q -- Paired floating point VSX predicate builtins

55006

RS6000_BUILTIN_S -- SPE predicate builtins

55007

RS6000_BUILTIN_X -- special builtins

55008

@@ -66,6 +67,10 @@

55009

#error "RS6000_BUILTIN_E is not defined."

55010

#endif

55011

55012

+#ifndef RS6000_BUILTIN_H

55013

+ #error "RS6000_BUILTIN_H is not defined."

55014

+#endif

55015

+

55016

#ifndef RS6000_BUILTIN_P

55017

#error "RS6000_BUILTIN_P is not defined."

55018

#endif

55019

@@ -301,6 +306,174 @@

55020

| RS6000_BTC_SPECIAL), \

55021

CODE_FOR_nothing) /* ICODE */

55022

55023

+/* ISA 2.07 (power8) vector convenience macros. */

55024

+/* For the instructions that are encoded as altivec instructions use

55025

+ __builtin_altivec_ as the builtin name. */

55026

+#define BU_P8V_AV_1(ENUM, NAME, ATTR, ICODE) \

55027

+ RS6000_BUILTIN_1 (P8V_BUILTIN_ ## ENUM, /* ENUM */ \

55028

+ "__builtin_altivec_" NAME, /* NAME */ \

55029

+ RS6000_BTM_P8_VECTOR, /* MASK */ \

55030

+ (RS6000_BTC_ ## ATTR /* ATTR */ \

55031

+ | RS6000_BTC_UNARY), \

55032

+ CODE_FOR_ ## ICODE) /* ICODE */

55033

+

55034

+#define BU_P8V_AV_2(ENUM, NAME, ATTR, ICODE) \

55035

+ RS6000_BUILTIN_2 (P8V_BUILTIN_ ## ENUM, /* ENUM */ \

55036

+ "__builtin_altivec_" NAME, /* NAME */ \

55037

+ RS6000_BTM_P8_VECTOR, /* MASK */ \

55038

+ (RS6000_BTC_ ## ATTR /* ATTR */ \

55039

+ | RS6000_BTC_BINARY), \

55040

+ CODE_FOR_ ## ICODE) /* ICODE */

55041

+

55042

+#define BU_P8V_AV_3(ENUM, NAME, ATTR, ICODE) \

55043

+ RS6000_BUILTIN_3 (P8V_BUILTIN_ ## ENUM, /* ENUM */ \

55044

+ "__builtin_altivec_" NAME, /* NAME */ \

55045

+ RS6000_BTM_P8_VECTOR, /* MASK */ \

55046

+ (RS6000_BTC_ ## ATTR /* ATTR */ \

55047

+ | RS6000_BTC_TERNARY), \

55048

+ CODE_FOR_ ## ICODE) /* ICODE */

55049

+

55050

+#define BU_P8V_AV_P(ENUM, NAME, ATTR, ICODE) \

55051

+ RS6000_BUILTIN_P (P8V_BUILTIN_ ## ENUM, /* ENUM */ \

55052

+ "__builtin_altivec_" NAME, /* NAME */ \

55053

+ RS6000_BTM_P8_VECTOR, /* MASK */ \

55054

+ (RS6000_BTC_ ## ATTR /* ATTR */ \

55055

+ | RS6000_BTC_PREDICATE), \

55056

+ CODE_FOR_ ## ICODE) /* ICODE */

55057

+

55058

+/* For the instructions encoded as VSX instructions use __builtin_vsx as the

55059

+ builtin name. */

55060

+#define BU_P8V_VSX_1(ENUM, NAME, ATTR, ICODE) \

55061

+ RS6000_BUILTIN_1 (P8V_BUILTIN_ ## ENUM, /* ENUM */ \

55062

+ "__builtin_vsx_" NAME, /* NAME */ \

55063

+ RS6000_BTM_P8_VECTOR, /* MASK */ \

55064

+ (RS6000_BTC_ ## ATTR /* ATTR */ \

55065

+ | RS6000_BTC_UNARY), \

55066

+ CODE_FOR_ ## ICODE) /* ICODE */

55067

+

55068

+#define BU_P8V_OVERLOAD_1(ENUM, NAME) \

55069

+ RS6000_BUILTIN_1 (P8V_BUILTIN_VEC_ ## ENUM, /* ENUM */ \

55070

+ "__builtin_vec_" NAME, /* NAME */ \

55071

+ RS6000_BTM_P8_VECTOR, /* MASK */ \

55072

+ (RS6000_BTC_OVERLOADED /* ATTR */ \

55073

+ | RS6000_BTC_UNARY), \

55074

+ CODE_FOR_nothing) /* ICODE */

55075

+

55076

+#define BU_P8V_OVERLOAD_2(ENUM, NAME) \

55077

+ RS6000_BUILTIN_2 (P8V_BUILTIN_VEC_ ## ENUM, /* ENUM */ \

55078

+ "__builtin_vec_" NAME, /* NAME */ \

55079

+ RS6000_BTM_P8_VECTOR, /* MASK */ \

55080

+ (RS6000_BTC_OVERLOADED /* ATTR */ \

55081

+ | RS6000_BTC_BINARY), \

55082

+ CODE_FOR_nothing) /* ICODE */

55083

+

55084

+#define BU_P8V_OVERLOAD_3(ENUM, NAME) \

55085

+ RS6000_BUILTIN_3 (P8V_BUILTIN_VEC_ ## ENUM, /* ENUM */ \

55086

+ "__builtin_vec_" NAME, /* NAME */ \

55087

+ RS6000_BTM_P8_VECTOR, /* MASK */ \

55088

+ (RS6000_BTC_OVERLOADED /* ATTR */ \

55089

+ | RS6000_BTC_TERNARY), \

55090

+ CODE_FOR_nothing) /* ICODE */

55091

+

55092

+/* Crypto convenience macros. */

55093

+#define BU_CRYPTO_1(ENUM, NAME, ATTR, ICODE) \

55094

+ RS6000_BUILTIN_1 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \

55095

+ "__builtin_crypto_" NAME, /* NAME */ \

55096

+ RS6000_BTM_CRYPTO, /* MASK */ \

55097

+ (RS6000_BTC_ ## ATTR /* ATTR */ \

55098

+ | RS6000_BTC_UNARY), \

55099

+ CODE_FOR_ ## ICODE) /* ICODE */

55100

+

55101

+#define BU_CRYPTO_2(ENUM, NAME, ATTR, ICODE) \

55102

+ RS6000_BUILTIN_2 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \

55103

+ "__builtin_crypto_" NAME, /* NAME */ \

55104

+ RS6000_BTM_CRYPTO, /* MASK */ \

55105

+ (RS6000_BTC_ ## ATTR /* ATTR */ \

55106

+ | RS6000_BTC_BINARY), \

55107

+ CODE_FOR_ ## ICODE) /* ICODE */

55108

+

55109

+#define BU_CRYPTO_3(ENUM, NAME, ATTR, ICODE) \

55110

+ RS6000_BUILTIN_3 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \

55111

+ "__builtin_crypto_" NAME, /* NAME */ \

55112

+ RS6000_BTM_CRYPTO, /* MASK */ \

55113

+ (RS6000_BTC_ ## ATTR /* ATTR */ \

55114

+ | RS6000_BTC_TERNARY), \

55115

+ CODE_FOR_ ## ICODE) /* ICODE */

55116

+

55117

+#define BU_CRYPTO_OVERLOAD_1(ENUM, NAME) \

55118

+ RS6000_BUILTIN_1 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \

55119

+ "__builtin_crypto_" NAME, /* NAME */ \

55120

+ RS6000_BTM_CRYPTO, /* MASK */ \

55121

+ (RS6000_BTC_OVERLOADED /* ATTR */ \

55122

+ | RS6000_BTC_UNARY), \

55123

+ CODE_FOR_nothing) /* ICODE */

55124

+

55125

+#define BU_CRYPTO_OVERLOAD_2(ENUM, NAME) \

55126

+ RS6000_BUILTIN_2 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \

55127

+ "__builtin_crypto_" NAME, /* NAME */ \

55128

+ RS6000_BTM_CRYPTO, /* MASK */ \

55129

+ (RS6000_BTC_OVERLOADED /* ATTR */ \

55130

+ | RS6000_BTC_BINARY), \

55131

+ CODE_FOR_nothing) /* ICODE */

55132

+

55133

+#define BU_CRYPTO_OVERLOAD_3(ENUM, NAME) \

55134

+ RS6000_BUILTIN_3 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \

55135

+ "__builtin_crypto_" NAME, /* NAME */ \

55136

+ RS6000_BTM_CRYPTO, /* MASK */ \

55137

+ (RS6000_BTC_OVERLOADED /* ATTR */ \

55138

+ | RS6000_BTC_TERNARY), \

55139

+ CODE_FOR_nothing) /* ICODE */

55140

+

55141

+/* HTM convenience macros. */

55142

+#define BU_HTM_0(ENUM, NAME, ATTR, ICODE) \

55143

+ RS6000_BUILTIN_H (HTM_BUILTIN_ ## ENUM, /* ENUM */ \

55144

+ "__builtin_" NAME, /* NAME */ \

55145

+ RS6000_BTM_HTM, /* MASK */ \

55146

+ RS6000_BTC_ ## ATTR, /* ATTR */ \

55147

+ CODE_FOR_ ## ICODE) /* ICODE */

55148

+

55149

+#define BU_HTM_1(ENUM, NAME, ATTR, ICODE) \

55150

+ RS6000_BUILTIN_H (HTM_BUILTIN_ ## ENUM, /* ENUM */ \

55151

+ "__builtin_" NAME, /* NAME */ \

55152

+ RS6000_BTM_HTM, /* MASK */ \

55153

+ (RS6000_BTC_ ## ATTR /* ATTR */ \

55154

+ | RS6000_BTC_UNARY), \

55155

+ CODE_FOR_ ## ICODE) /* ICODE */

55156

+

55157

+#define BU_HTM_2(ENUM, NAME, ATTR, ICODE) \

55158

+ RS6000_BUILTIN_H (HTM_BUILTIN_ ## ENUM, /* ENUM */ \

55159

+ "__builtin_" NAME, /* NAME */ \

55160

+ RS6000_BTM_HTM, /* MASK */ \

55161

+ (RS6000_BTC_ ## ATTR /* ATTR */ \

55162

+ | RS6000_BTC_BINARY), \

55163

+ CODE_FOR_ ## ICODE) /* ICODE */

55164

+

55165

+#define BU_HTM_3(ENUM, NAME, ATTR, ICODE) \

55166

+ RS6000_BUILTIN_H (HTM_BUILTIN_ ## ENUM, /* ENUM */ \

55167

+ "__builtin_" NAME, /* NAME */ \

55168

+ RS6000_BTM_HTM, /* MASK */ \

55169

+ (RS6000_BTC_ ## ATTR /* ATTR */ \

55170

+ | RS6000_BTC_TERNARY), \

55171

+ CODE_FOR_ ## ICODE) /* ICODE */

55172

+

55173

+#define BU_HTM_SPR0(ENUM, NAME, ATTR, ICODE) \

55174

+ RS6000_BUILTIN_H (HTM_BUILTIN_ ## ENUM, /* ENUM */ \

55175

+ "__builtin_" NAME, /* NAME */ \

55176

+ RS6000_BTM_HTM, /* MASK */ \

55177

+ (RS6000_BTC_ ## ATTR /* ATTR */ \

55178

+ | RS6000_BTC_SPR), \

55179

+ CODE_FOR_ ## ICODE) /* ICODE */

55180

+

55181

+#define BU_HTM_SPR1(ENUM, NAME, ATTR, ICODE) \

55182

+ RS6000_BUILTIN_H (HTM_BUILTIN_ ## ENUM, /* ENUM */ \

55183

+ "__builtin_" NAME, /* NAME */ \

55184

+ RS6000_BTM_HTM, /* MASK */ \

55185

+ (RS6000_BTC_ ## ATTR /* ATTR */ \

55186

+ | RS6000_BTC_UNARY \

55187

+ | RS6000_BTC_SPR \

55188

+ | RS6000_BTC_VOID), \

55189

+ CODE_FOR_ ## ICODE) /* ICODE */

55190

+

55191

/* SPE convenience macros. */

55192

#define BU_SPE_1(ENUM, NAME, ATTR, ICODE) \

55193

RS6000_BUILTIN_1 (SPE_BUILTIN_ ## ENUM, /* ENUM */ \

55194

@@ -397,6 +570,75 @@

55195

MASK, /* MASK */ \

55196

(ATTR | RS6000_BTC_SPECIAL), /* ATTR */ \

55197

CODE_FOR_nothing) /* ICODE */

55198

+

55199

+

55200

+/* Decimal floating point builtins for instructions. */

55201

+#define BU_DFP_MISC_1(ENUM, NAME, ATTR, ICODE) \

55202

+ RS6000_BUILTIN_1 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \

55203

+ "__builtin_" NAME, /* NAME */ \

55204

+ RS6000_BTM_DFP, /* MASK */ \

55205

+ (RS6000_BTC_ ## ATTR /* ATTR */ \

55206

+ | RS6000_BTC_UNARY), \

55207

+ CODE_FOR_ ## ICODE) /* ICODE */

55208

+

55209

+#define BU_DFP_MISC_2(ENUM, NAME, ATTR, ICODE) \

55210

+ RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \

55211

+ "__builtin_" NAME, /* NAME */ \

55212

+ RS6000_BTM_DFP, /* MASK */ \

55213

+ (RS6000_BTC_ ## ATTR /* ATTR */ \

55214

+ | RS6000_BTC_BINARY), \

55215

+ CODE_FOR_ ## ICODE) /* ICODE */

55216

+

55217

+

55218

+/* Miscellaneous builtins for instructions added in ISA 2.06. These

55219

+ instructions don't require either the DFP or VSX options, just the basic ISA

55220

+ 2.06 (popcntd) enablement since they operate on general purpose

55221

+ registers. */

55222

+#define BU_P7_MISC_1(ENUM, NAME, ATTR, ICODE) \

55223

+ RS6000_BUILTIN_1 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \

55224

+ "__builtin_" NAME, /* NAME */ \

55225

+ RS6000_BTM_POPCNTD, /* MASK */ \

55226

+ (RS6000_BTC_ ## ATTR /* ATTR */ \

55227

+ | RS6000_BTC_UNARY), \

55228

+ CODE_FOR_ ## ICODE) /* ICODE */

55229

+

55230

+#define BU_P7_MISC_2(ENUM, NAME, ATTR, ICODE) \

55231

+ RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \

55232

+ "__builtin_" NAME, /* NAME */ \

55233

+ RS6000_BTM_POPCNTD, /* MASK */ \

55234

+ (RS6000_BTC_ ## ATTR /* ATTR */ \

55235

+ | RS6000_BTC_BINARY), \

55236

+ CODE_FOR_ ## ICODE) /* ICODE */

55237

+

55238

+

55239

+/* Miscellaneous builtins for instructions added in ISA 2.07. These

55240

+ instructions do require the ISA 2.07 vector support, but they aren't vector

55241

+ instructions. */

55242

+#define BU_P8V_MISC_3(ENUM, NAME, ATTR, ICODE) \

55243

+ RS6000_BUILTIN_3 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \

55244

+ "__builtin_" NAME, /* NAME */ \

55245

+ RS6000_BTM_P8_VECTOR, /* MASK */ \

55246

+ (RS6000_BTC_ ## ATTR /* ATTR */ \

55247

+ | RS6000_BTC_TERNARY), \

55248

+ CODE_FOR_ ## ICODE) /* ICODE */

55249

+

55250

+/* Miscellaneous builtins. */

55251

+#define BU_MISC_1(ENUM, NAME, ATTR, ICODE) \

55252

+ RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \

55253

+ "__builtin_" NAME, /* NAME */ \

55254

+ RS6000_BTM_HARD_FLOAT, /* MASK */ \

55255

+ (RS6000_BTC_ ## ATTR /* ATTR */ \

55256

+ | RS6000_BTC_UNARY), \

55257

+ CODE_FOR_ ## ICODE) /* ICODE */

55258

+

55259

+#define BU_MISC_2(ENUM, NAME, ATTR, ICODE) \

55260

+ RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \

55261

+ "__builtin_" NAME, /* NAME */ \

55262

+ RS6000_BTM_HARD_FLOAT, /* MASK */ \

55263

+ (RS6000_BTC_ ## ATTR /* ATTR */ \

55264

+ | RS6000_BTC_BINARY), \

55265

+ CODE_FOR_ ## ICODE) /* ICODE */

55266

+

55267

#endif

55268

55269

/* Insure 0 is not a legitimate index. */

55270

@@ -414,6 +656,7 @@

55271

BU_ALTIVEC_3 (VMSUMUHS, "vmsumuhs", SAT, altivec_vmsumuhs)

55272

BU_ALTIVEC_3 (VMSUMSHS, "vmsumshs", SAT, altivec_vmsumshs)

55273

BU_ALTIVEC_3 (VNMSUBFP, "vnmsubfp", FP, nfmsv4sf4)

55274

+BU_ALTIVEC_3 (VPERM_1TI, "vperm_1ti", CONST, altivec_vperm_v1ti)

55275

BU_ALTIVEC_3 (VPERM_2DF, "vperm_2df", CONST, altivec_vperm_v2df)

55276

BU_ALTIVEC_3 (VPERM_2DI, "vperm_2di", CONST, altivec_vperm_v2di)

55277

BU_ALTIVEC_3 (VPERM_4SF, "vperm_4sf", CONST, altivec_vperm_v4sf)

55278

@@ -420,6 +663,7 @@

55279

BU_ALTIVEC_3 (VPERM_4SI, "vperm_4si", CONST, altivec_vperm_v4si)

55280

BU_ALTIVEC_3 (VPERM_8HI, "vperm_8hi", CONST, altivec_vperm_v8hi)

55281

BU_ALTIVEC_3 (VPERM_16QI, "vperm_16qi", CONST, altivec_vperm_v16qi_uns)

55282

+BU_ALTIVEC_3 (VPERM_1TI_UNS, "vperm_1ti_uns", CONST, altivec_vperm_v1ti_uns)

55283

BU_ALTIVEC_3 (VPERM_2DI_UNS, "vperm_2di_uns", CONST, altivec_vperm_v2di_uns)

55284

BU_ALTIVEC_3 (VPERM_4SI_UNS, "vperm_4si_uns", CONST, altivec_vperm_v4si_uns)

55285

BU_ALTIVEC_3 (VPERM_8HI_UNS, "vperm_8hi_uns", CONST, altivec_vperm_v8hi_uns)

55286

@@ -430,10 +674,12 @@

55287

BU_ALTIVEC_3 (VSEL_16QI, "vsel_16qi", CONST, vector_select_v16qi)

55288

BU_ALTIVEC_3 (VSEL_2DF, "vsel_2df", CONST, vector_select_v2df)

55289

BU_ALTIVEC_3 (VSEL_2DI, "vsel_2di", CONST, vector_select_v2di)

55290

+BU_ALTIVEC_3 (VSEL_1TI, "vsel_1ti", CONST, vector_select_v1ti)

55291

BU_ALTIVEC_3 (VSEL_4SI_UNS, "vsel_4si_uns", CONST, vector_select_v4si_uns)

55292

BU_ALTIVEC_3 (VSEL_8HI_UNS, "vsel_8hi_uns", CONST, vector_select_v8hi_uns)

55293

BU_ALTIVEC_3 (VSEL_16QI_UNS, "vsel_16qi_uns", CONST, vector_select_v16qi_uns)

55294

BU_ALTIVEC_3 (VSEL_2DI_UNS, "vsel_2di_uns", CONST, vector_select_v2di_uns)

55295

+BU_ALTIVEC_3 (VSEL_1TI_UNS, "vsel_1ti_uns", CONST, vector_select_v1ti_uns)

55296

BU_ALTIVEC_3 (VSLDOI_16QI, "vsldoi_16qi", CONST, altivec_vsldoi_v16qi)

55297

BU_ALTIVEC_3 (VSLDOI_8HI, "vsldoi_8hi", CONST, altivec_vsldoi_v8hi)

55298

BU_ALTIVEC_3 (VSLDOI_4SI, "vsldoi_4si", CONST, altivec_vsldoi_v4si)

55299

@@ -626,6 +872,8 @@

55300

BU_ALTIVEC_X (LD_INTERNAL_2df, "ld_internal_2df", MEM)

55301

BU_ALTIVEC_X (ST_INTERNAL_2di, "st_internal_2di", MEM)

55302

BU_ALTIVEC_X (LD_INTERNAL_2di, "ld_internal_2di", MEM)

55303

+BU_ALTIVEC_X (ST_INTERNAL_1ti, "st_internal_1ti", MEM)

55304

+BU_ALTIVEC_X (LD_INTERNAL_1ti, "ld_internal_1ti", MEM)

55305

BU_ALTIVEC_X (MTVSCR, "mtvscr", MISC)

55306

BU_ALTIVEC_X (MFVSCR, "mfvscr", MISC)

55307

BU_ALTIVEC_X (DSSALL, "dssall", MISC)

55308

@@ -636,8 +884,26 @@

55309

BU_ALTIVEC_X (LVEHX, "lvehx", MEM)

55310

BU_ALTIVEC_X (LVEWX, "lvewx", MEM)

55311

BU_ALTIVEC_X (LVXL, "lvxl", MEM)

55312

+BU_ALTIVEC_X (LVXL_V2DF, "lvxl_v2df", MEM)

55313

+BU_ALTIVEC_X (LVXL_V2DI, "lvxl_v2di", MEM)

55314

+BU_ALTIVEC_X (LVXL_V4SF, "lvxl_v4sf", MEM)

55315

+BU_ALTIVEC_X (LVXL_V4SI, "lvxl_v4si", MEM)

55316

+BU_ALTIVEC_X (LVXL_V8HI, "lvxl_v8hi", MEM)

55317

+BU_ALTIVEC_X (LVXL_V16QI, "lvxl_v16qi", MEM)

55318

BU_ALTIVEC_X (LVX, "lvx", MEM)

55319

+BU_ALTIVEC_X (LVX_V2DF, "lvx_v2df", MEM)

55320

+BU_ALTIVEC_X (LVX_V2DI, "lvx_v2di", MEM)

55321

+BU_ALTIVEC_X (LVX_V4SF, "lvx_v4sf", MEM)

55322

+BU_ALTIVEC_X (LVX_V4SI, "lvx_v4si", MEM)

55323

+BU_ALTIVEC_X (LVX_V8HI, "lvx_v8hi", MEM)

55324

+BU_ALTIVEC_X (LVX_V16QI, "lvx_v16qi", MEM)

55325

BU_ALTIVEC_X (STVX, "stvx", MEM)

55326

+BU_ALTIVEC_X (STVX_V2DF, "stvx_v2df", MEM)

55327

+BU_ALTIVEC_X (STVX_V2DI, "stvx_v2di", MEM)

55328

+BU_ALTIVEC_X (STVX_V4SF, "stvx_v4sf", MEM)

55329

+BU_ALTIVEC_X (STVX_V4SI, "stvx_v4si", MEM)

55330

+BU_ALTIVEC_X (STVX_V8HI, "stvx_v8hi", MEM)

55331

+BU_ALTIVEC_X (STVX_V16QI, "stvx_v16qi", MEM)

55332

BU_ALTIVEC_C (LVLX, "lvlx", MEM)

55333

BU_ALTIVEC_C (LVLXL, "lvlxl", MEM)

55334

BU_ALTIVEC_C (LVRX, "lvrx", MEM)

55335

@@ -646,6 +912,12 @@

55336

BU_ALTIVEC_X (STVEHX, "stvehx", MEM)

55337

BU_ALTIVEC_X (STVEWX, "stvewx", MEM)

55338

BU_ALTIVEC_X (STVXL, "stvxl", MEM)

55339

+BU_ALTIVEC_X (STVXL_V2DF, "stvxl_v2df", MEM)

55340

+BU_ALTIVEC_X (STVXL_V2DI, "stvxl_v2di", MEM)

55341

+BU_ALTIVEC_X (STVXL_V4SF, "stvxl_v4sf", MEM)

55342

+BU_ALTIVEC_X (STVXL_V4SI, "stvxl_v4si", MEM)

55343

+BU_ALTIVEC_X (STVXL_V8HI, "stvxl_v8hi", MEM)

55344

+BU_ALTIVEC_X (STVXL_V16QI, "stvxl_v16qi", MEM)

55345

BU_ALTIVEC_C (STVLX, "stvlx", MEM)

55346

BU_ALTIVEC_C (STVLXL, "stvlxl", MEM)

55347

BU_ALTIVEC_C (STVRX, "stvrx", MEM)

55348

@@ -904,6 +1176,7 @@

55349

BU_VSX_3 (XVNMADDDP, "xvnmadddp", CONST, nfmav2df4)

55350

BU_VSX_3 (XVNMSUBDP, "xvnmsubdp", CONST, nfmsv2df4)

55351

55352

+BU_VSX_3 (XXSEL_1TI, "xxsel_1ti", CONST, vector_select_v1ti)

55353

BU_VSX_3 (XXSEL_2DI, "xxsel_2di", CONST, vector_select_v2di)

55354

BU_VSX_3 (XXSEL_2DF, "xxsel_2df", CONST, vector_select_v2df)

55355

BU_VSX_3 (XXSEL_4SF, "xxsel_4sf", CONST, vector_select_v4sf)

55356

@@ -910,11 +1183,13 @@

55357

BU_VSX_3 (XXSEL_4SI, "xxsel_4si", CONST, vector_select_v4si)

55358

BU_VSX_3 (XXSEL_8HI, "xxsel_8hi", CONST, vector_select_v8hi)

55359

BU_VSX_3 (XXSEL_16QI, "xxsel_16qi", CONST, vector_select_v16qi)

55360

+BU_VSX_3 (XXSEL_1TI_UNS, "xxsel_1ti_uns", CONST, vector_select_v1ti_uns)

55361

BU_VSX_3 (XXSEL_2DI_UNS, "xxsel_2di_uns", CONST, vector_select_v2di_uns)

55362

BU_VSX_3 (XXSEL_4SI_UNS, "xxsel_4si_uns", CONST, vector_select_v4si_uns)

55363

BU_VSX_3 (XXSEL_8HI_UNS, "xxsel_8hi_uns", CONST, vector_select_v8hi_uns)

55364

BU_VSX_3 (XXSEL_16QI_UNS, "xxsel_16qi_uns", CONST, vector_select_v16qi_uns)

55365

55366

+BU_VSX_3 (VPERM_1TI, "vperm_1ti", CONST, altivec_vperm_v1ti)

55367

BU_VSX_3 (VPERM_2DI, "vperm_2di", CONST, altivec_vperm_v2di)

55368

BU_VSX_3 (VPERM_2DF, "vperm_2df", CONST, altivec_vperm_v2df)

55369

BU_VSX_3 (VPERM_4SF, "vperm_4sf", CONST, altivec_vperm_v4sf)

55370

@@ -921,11 +1196,13 @@

55371

BU_VSX_3 (VPERM_4SI, "vperm_4si", CONST, altivec_vperm_v4si)

55372

BU_VSX_3 (VPERM_8HI, "vperm_8hi", CONST, altivec_vperm_v8hi)

55373

BU_VSX_3 (VPERM_16QI, "vperm_16qi", CONST, altivec_vperm_v16qi)

55374

+BU_VSX_3 (VPERM_1TI_UNS, "vperm_1ti_uns", CONST, altivec_vperm_v1ti_uns)

55375

BU_VSX_3 (VPERM_2DI_UNS, "vperm_2di_uns", CONST, altivec_vperm_v2di_uns)

55376

BU_VSX_3 (VPERM_4SI_UNS, "vperm_4si_uns", CONST, altivec_vperm_v4si_uns)

55377

BU_VSX_3 (VPERM_8HI_UNS, "vperm_8hi_uns", CONST, altivec_vperm_v8hi_uns)

55378

BU_VSX_3 (VPERM_16QI_UNS, "vperm_16qi_uns", CONST, altivec_vperm_v16qi_uns)

55379

55380

+BU_VSX_3 (XXPERMDI_1TI, "xxpermdi_1ti", CONST, vsx_xxpermdi_v1ti)

55381

BU_VSX_3 (XXPERMDI_2DF, "xxpermdi_2df", CONST, vsx_xxpermdi_v2df)

55382

BU_VSX_3 (XXPERMDI_2DI, "xxpermdi_2di", CONST, vsx_xxpermdi_v2di)

55383

BU_VSX_3 (XXPERMDI_4SF, "xxpermdi_4sf", CONST, vsx_xxpermdi_v4sf)

55384

@@ -932,6 +1209,7 @@

55385

BU_VSX_3 (XXPERMDI_4SI, "xxpermdi_4si", CONST, vsx_xxpermdi_v4si)

55386

BU_VSX_3 (XXPERMDI_8HI, "xxpermdi_8hi", CONST, vsx_xxpermdi_v8hi)

55387

BU_VSX_3 (XXPERMDI_16QI, "xxpermdi_16qi", CONST, vsx_xxpermdi_v16qi)

55388

+BU_VSX_3 (SET_1TI, "set_1ti", CONST, vsx_set_v1ti)

55389

BU_VSX_3 (SET_2DF, "set_2df", CONST, vsx_set_v2df)

55390

BU_VSX_3 (SET_2DI, "set_2di", CONST, vsx_set_v2di)

55391

BU_VSX_3 (XXSLDWI_2DI, "xxsldwi_2di", CONST, vsx_xxsldwi_v2di)

55392

@@ -1012,7 +1290,7 @@

55393

BU_VSX_1 (XVRESP, "xvresp", CONST, vsx_frev4sf2)

55394

55395

BU_VSX_1 (XSCVDPSP, "xscvdpsp", CONST, vsx_xscvdpsp)

55396

-BU_VSX_1 (XSCVSPDP, "xscvspdp", CONST, vsx_xscvdpsp)

55397

+BU_VSX_1 (XSCVSPDP, "xscvspdp", CONST, vsx_xscvspdp)

55398

BU_VSX_1 (XVCVDPSP, "xvcvdpsp", CONST, vsx_xvcvdpsp)

55399

BU_VSX_1 (XVCVSPDP, "xvcvspdp", CONST, vsx_xvcvspdp)

55400

BU_VSX_1 (XSTSQRTDP_FE, "xstsqrtdp_fe", CONST, vsx_tsqrtdf2_fe)

55401

@@ -1052,9 +1330,9 @@

55402

55403

BU_VSX_1 (XSRDPI, "xsrdpi", CONST, vsx_xsrdpi)

55404

BU_VSX_1 (XSRDPIC, "xsrdpic", CONST, vsx_xsrdpic)

55405

-BU_VSX_1 (XSRDPIM, "xsrdpim", CONST, vsx_floordf2)

55406

-BU_VSX_1 (XSRDPIP, "xsrdpip", CONST, vsx_ceildf2)

55407

-BU_VSX_1 (XSRDPIZ, "xsrdpiz", CONST, vsx_btruncdf2)

55408

+BU_VSX_1 (XSRDPIM, "xsrdpim", CONST, floordf2)

55409

+BU_VSX_1 (XSRDPIP, "xsrdpip", CONST, ceildf2)

55410

+BU_VSX_1 (XSRDPIZ, "xsrdpiz", CONST, btruncdf2)

55411

55412

/* VSX predicate functions. */

55413

BU_VSX_P (XVCMPEQSP_P, "xvcmpeqsp_p", CONST, vector_eq_v4sf_p)

55414

@@ -1066,6 +1344,7 @@

55415

55416

/* VSX builtins that are handled as special cases. */

55417

BU_VSX_X (LXSDX, "lxsdx", MEM)

55418

+BU_VSX_X (LXVD2X_V1TI, "lxvd2x_v1ti", MEM)

55419

BU_VSX_X (LXVD2X_V2DF, "lxvd2x_v2df", MEM)

55420

BU_VSX_X (LXVD2X_V2DI, "lxvd2x_v2di", MEM)

55421

BU_VSX_X (LXVDSX, "lxvdsx", MEM)

55422

@@ -1074,6 +1353,7 @@

55423

BU_VSX_X (LXVW4X_V8HI, "lxvw4x_v8hi", MEM)

55424

BU_VSX_X (LXVW4X_V16QI, "lxvw4x_v16qi", MEM)

55425

BU_VSX_X (STXSDX, "stxsdx", MEM)

55426

+BU_VSX_X (STXVD2X_V1TI, "stxsdx_v1ti", MEM)

55427

BU_VSX_X (STXVD2X_V2DF, "stxsdx_v2df", MEM)

55428

BU_VSX_X (STXVD2X_V2DI, "stxsdx_v2di", MEM)

55429

BU_VSX_X (STXVW4X_V4SF, "stxsdx_v4sf", MEM)

55430

@@ -1104,10 +1384,13 @@

55431

BU_VSX_X (XSNMSUBADP, "xsnmsubadp", FP)

55432

BU_VSX_X (XSNMSUBMDP, "xsnmsubmdp", FP)

55433

BU_VSX_X (XSSUBDP, "xssubdp", FP)

55434

+BU_VSX_X (VEC_INIT_V1TI, "vec_init_v1ti", CONST)

55435

BU_VSX_X (VEC_INIT_V2DF, "vec_init_v2df", CONST)

55436

BU_VSX_X (VEC_INIT_V2DI, "vec_init_v2di", CONST)

55437

+BU_VSX_X (VEC_SET_V1TI, "vec_set_v1ti", CONST)

55438

BU_VSX_X (VEC_SET_V2DF, "vec_set_v2df", CONST)

55439

BU_VSX_X (VEC_SET_V2DI, "vec_set_v2di", CONST)

55440

+BU_VSX_X (VEC_EXT_V1TI, "vec_ext_v1ti", CONST)

55441

BU_VSX_X (VEC_EXT_V2DF, "vec_ext_v2df", CONST)

55442

BU_VSX_X (VEC_EXT_V2DI, "vec_ext_v2di", CONST)

55443

55444

@@ -1132,6 +1415,249 @@

55445

BU_VSX_OVERLOAD_X (LD, "ld")

55446

BU_VSX_OVERLOAD_X (ST, "st")

55447

55448

+/* 1 argument VSX instructions added in ISA 2.07. */

55449

+BU_P8V_VSX_1 (XSCVSPDPN, "xscvspdpn", CONST, vsx_xscvspdpn)

55450

+BU_P8V_VSX_1 (XSCVDPSPN, "xscvdpspn", CONST, vsx_xscvdpspn)

55451

+

55452

+/* 1 argument altivec instructions added in ISA 2.07. */

55453

+BU_P8V_AV_1 (ABS_V2DI, "abs_v2di", CONST, absv2di2)

55454

+BU_P8V_AV_1 (VUPKHSW, "vupkhsw", CONST, altivec_vupkhsw)

55455

+BU_P8V_AV_1 (VUPKLSW, "vupklsw", CONST, altivec_vupklsw)

55456

+BU_P8V_AV_1 (VCLZB, "vclzb", CONST, clzv16qi2)

55457

+BU_P8V_AV_1 (VCLZH, "vclzh", CONST, clzv8hi2)

55458

+BU_P8V_AV_1 (VCLZW, "vclzw", CONST, clzv4si2)

55459

+BU_P8V_AV_1 (VCLZD, "vclzd", CONST, clzv2di2)

55460

+BU_P8V_AV_1 (VPOPCNTB, "vpopcntb", CONST, popcountv16qi2)

55461

+BU_P8V_AV_1 (VPOPCNTH, "vpopcnth", CONST, popcountv8hi2)

55462

+BU_P8V_AV_1 (VPOPCNTW, "vpopcntw", CONST, popcountv4si2)

55463

+BU_P8V_AV_1 (VPOPCNTD, "vpopcntd", CONST, popcountv2di2)

55464

+BU_P8V_AV_1 (VGBBD, "vgbbd", CONST, p8v_vgbbd)

55465

+

55466

+/* 2 argument altivec instructions added in ISA 2.07. */

55467

+BU_P8V_AV_2 (VADDCUQ, "vaddcuq", CONST, altivec_vaddcuq)

55468

+BU_P8V_AV_2 (VADDUDM, "vaddudm", CONST, addv2di3)

55469

+BU_P8V_AV_2 (VADDUQM, "vadduqm", CONST, altivec_vadduqm)

55470

+BU_P8V_AV_2 (VMINSD, "vminsd", CONST, sminv2di3)

55471

+BU_P8V_AV_2 (VMAXSD, "vmaxsd", CONST, smaxv2di3)

55472

+BU_P8V_AV_2 (VMINUD, "vminud", CONST, uminv2di3)

55473

+BU_P8V_AV_2 (VMAXUD, "vmaxud", CONST, umaxv2di3)

55474

+BU_P8V_AV_2 (VMRGEW, "vmrgew", CONST, p8_vmrgew)

55475

+BU_P8V_AV_2 (VMRGOW, "vmrgow", CONST, p8_vmrgow)

55476

+BU_P8V_AV_2 (VBPERMQ, "vbpermq", CONST, altivec_vbpermq)

55477

+BU_P8V_AV_2 (VPKUDUM, "vpkudum", CONST, altivec_vpkudum)

55478

+BU_P8V_AV_2 (VPKSDSS, "vpksdss", CONST, altivec_vpksdss)

55479

+BU_P8V_AV_2 (VPKUDUS, "vpkudus", CONST, altivec_vpkudus)

55480

+BU_P8V_AV_2 (VPKSDUS, "vpksdus", CONST, altivec_vpksdus)

55481

+BU_P8V_AV_2 (VRLD, "vrld", CONST, vrotlv2di3)

55482

+BU_P8V_AV_2 (VSLD, "vsld", CONST, vashlv2di3)

55483

+BU_P8V_AV_2 (VSRD, "vsrd", CONST, vlshrv2di3)

55484

+BU_P8V_AV_2 (VSRAD, "vsrad", CONST, vashrv2di3)

55485

+BU_P8V_AV_2 (VSUBCUQ, "vsubcuq", CONST, altivec_vsubcuq)

55486

+BU_P8V_AV_2 (VSUBUDM, "vsubudm", CONST, subv2di3)

55487

+BU_P8V_AV_2 (VSUBUQM, "vsubuqm", CONST, altivec_vsubuqm)

55488

+

55489

+BU_P8V_AV_2 (EQV_V16QI, "eqv_v16qi", CONST, eqvv16qi3)

55490

+BU_P8V_AV_2 (EQV_V8HI, "eqv_v8hi", CONST, eqvv8hi3)

55491

+BU_P8V_AV_2 (EQV_V4SI, "eqv_v4si", CONST, eqvv4si3)

55492

+BU_P8V_AV_2 (EQV_V2DI, "eqv_v2di", CONST, eqvv2di3)

55493

+BU_P8V_AV_2 (EQV_V1TI, "eqv_v1ti", CONST, eqvv1ti3)

55494

+BU_P8V_AV_2 (EQV_V4SF, "eqv_v4sf", CONST, eqvv4sf3)

55495

+BU_P8V_AV_2 (EQV_V2DF, "eqv_v2df", CONST, eqvv2df3)

55496

+

55497

+BU_P8V_AV_2 (NAND_V16QI, "nand_v16qi", CONST, nandv16qi3)

55498

+BU_P8V_AV_2 (NAND_V8HI, "nand_v8hi", CONST, nandv8hi3)

55499

+BU_P8V_AV_2 (NAND_V4SI, "nand_v4si", CONST, nandv4si3)

55500

+BU_P8V_AV_2 (NAND_V2DI, "nand_v2di", CONST, nandv2di3)

55501

+BU_P8V_AV_2 (NAND_V1TI, "nand_v1ti", CONST, nandv1ti3)

55502

+BU_P8V_AV_2 (NAND_V4SF, "nand_v4sf", CONST, nandv4sf3)

55503

+BU_P8V_AV_2 (NAND_V2DF, "nand_v2df", CONST, nandv2df3)

55504

+

55505

+BU_P8V_AV_2 (ORC_V16QI, "orc_v16qi", CONST, orcv16qi3)

55506

+BU_P8V_AV_2 (ORC_V8HI, "orc_v8hi", CONST, orcv8hi3)

55507

+BU_P8V_AV_2 (ORC_V4SI, "orc_v4si", CONST, orcv4si3)

55508

+BU_P8V_AV_2 (ORC_V2DI, "orc_v2di", CONST, orcv2di3)

55509

+BU_P8V_AV_2 (ORC_V1TI, "orc_v1ti", CONST, orcv1ti3)

55510

+BU_P8V_AV_2 (ORC_V4SF, "orc_v4sf", CONST, orcv4sf3)

55511

+BU_P8V_AV_2 (ORC_V2DF, "orc_v2df", CONST, orcv2df3)

55512

+

55513

+/* 3 argument altivec instructions added in ISA 2.07. */

55514

+BU_P8V_AV_3 (VADDEUQM, "vaddeuqm", CONST, altivec_vaddeuqm)

55515

+BU_P8V_AV_3 (VADDECUQ, "vaddecuq", CONST, altivec_vaddecuq)

55516

+BU_P8V_AV_3 (VSUBEUQM, "vsubeuqm", CONST, altivec_vsubeuqm)

55517

+BU_P8V_AV_3 (VSUBECUQ, "vsubecuq", CONST, altivec_vsubecuq)

55518

+

55519

+/* Vector comparison instructions added in ISA 2.07. */

55520

+BU_P8V_AV_2 (VCMPEQUD, "vcmpequd", CONST, vector_eqv2di)

55521

+BU_P8V_AV_2 (VCMPGTSD, "vcmpgtsd", CONST, vector_gtv2di)

55522

+BU_P8V_AV_2 (VCMPGTUD, "vcmpgtud", CONST, vector_gtuv2di)

55523

+

55524

+/* Vector comparison predicate instructions added in ISA 2.07. */

55525

+BU_P8V_AV_P (VCMPEQUD_P, "vcmpequd_p", CONST, vector_eq_v2di_p)

55526

+BU_P8V_AV_P (VCMPGTSD_P, "vcmpgtsd_p", CONST, vector_gt_v2di_p)

55527

+BU_P8V_AV_P (VCMPGTUD_P, "vcmpgtud_p", CONST, vector_gtu_v2di_p)

55528

+

55529

+/* ISA 2.07 vector overloaded 1 argument functions. */

55530

+BU_P8V_OVERLOAD_1 (VUPKHSW, "vupkhsw")

55531

+BU_P8V_OVERLOAD_1 (VUPKLSW, "vupklsw")

55532

+BU_P8V_OVERLOAD_1 (VCLZ, "vclz")

55533

+BU_P8V_OVERLOAD_1 (VCLZB, "vclzb")

55534

+BU_P8V_OVERLOAD_1 (VCLZH, "vclzh")

55535

+BU_P8V_OVERLOAD_1 (VCLZW, "vclzw")

55536

+BU_P8V_OVERLOAD_1 (VCLZD, "vclzd")

55537

+BU_P8V_OVERLOAD_1 (VPOPCNT, "vpopcnt")

55538

+BU_P8V_OVERLOAD_1 (VPOPCNTB, "vpopcntb")

55539

+BU_P8V_OVERLOAD_1 (VPOPCNTH, "vpopcnth")

55540

+BU_P8V_OVERLOAD_1 (VPOPCNTW, "vpopcntw")

55541

+BU_P8V_OVERLOAD_1 (VPOPCNTD, "vpopcntd")

55542

+BU_P8V_OVERLOAD_1 (VGBBD, "vgbbd")

55543

+

55544

+/* ISA 2.07 vector overloaded 2 argument functions. */

55545

+BU_P8V_OVERLOAD_2 (EQV, "eqv")

55546

+BU_P8V_OVERLOAD_2 (NAND, "nand")

55547

+BU_P8V_OVERLOAD_2 (ORC, "orc")

55548

+BU_P8V_OVERLOAD_2 (VADDCUQ, "vaddcuq")

55549

+BU_P8V_OVERLOAD_2 (VADDUDM, "vaddudm")

55550

+BU_P8V_OVERLOAD_2 (VADDUQM, "vadduqm")

55551

+BU_P8V_OVERLOAD_2 (VBPERMQ, "vbpermq")

55552

+BU_P8V_OVERLOAD_2 (VMAXSD, "vmaxsd")

55553

+BU_P8V_OVERLOAD_2 (VMAXUD, "vmaxud")

55554

+BU_P8V_OVERLOAD_2 (VMINSD, "vminsd")

55555

+BU_P8V_OVERLOAD_2 (VMINUD, "vminud")

55556

+BU_P8V_OVERLOAD_2 (VMRGEW, "vmrgew")

55557

+BU_P8V_OVERLOAD_2 (VMRGOW, "vmrgow")

55558

+BU_P8V_OVERLOAD_2 (VPKSDSS, "vpksdss")

55559

+BU_P8V_OVERLOAD_2 (VPKSDUS, "vpksdus")

55560

+BU_P8V_OVERLOAD_2 (VPKUDUM, "vpkudum")

55561

+BU_P8V_OVERLOAD_2 (VPKUDUS, "vpkudus")

55562

+BU_P8V_OVERLOAD_2 (VRLD, "vrld")

55563

+BU_P8V_OVERLOAD_2 (VSLD, "vsld")

55564

+BU_P8V_OVERLOAD_2 (VSRAD, "vsrad")

55565

+BU_P8V_OVERLOAD_2 (VSRD, "vsrd")

55566

+BU_P8V_OVERLOAD_2 (VSUBCUQ, "vsubcuq")

55567

+BU_P8V_OVERLOAD_2 (VSUBUDM, "vsubudm")

55568

+BU_P8V_OVERLOAD_2 (VSUBUQM, "vsubuqm")

55569

+

55570

+/* ISA 2.07 vector overloaded 3 argument functions. */

55571

+BU_P8V_OVERLOAD_3 (VADDECUQ, "vaddecuq")

55572

+BU_P8V_OVERLOAD_3 (VADDEUQM, "vaddeuqm")

55573

+BU_P8V_OVERLOAD_3 (VSUBECUQ, "vsubecuq")

55574

+BU_P8V_OVERLOAD_3 (VSUBEUQM, "vsubeuqm")

55575

+

55576

+

55577

+/* 2 argument extended divide functions added in ISA 2.06. */

55578

+BU_P7_MISC_2 (DIVWE, "divwe", CONST, dive_si)

55579

+BU_P7_MISC_2 (DIVWEO, "divweo", CONST, diveo_si)

55580

+BU_P7_MISC_2 (DIVWEU, "divweu", CONST, diveu_si)

55581

+BU_P7_MISC_2 (DIVWEUO, "divweuo", CONST, diveuo_si)

55582

+BU_P7_MISC_2 (DIVDE, "divde", CONST, dive_di)

55583

+BU_P7_MISC_2 (DIVDEO, "divdeo", CONST, diveo_di)

55584

+BU_P7_MISC_2 (DIVDEU, "divdeu", CONST, diveu_di)

55585

+BU_P7_MISC_2 (DIVDEUO, "divdeuo", CONST, diveuo_di)

55586

+

55587

+/* 1 argument DFP (decimal floating point) functions added in ISA 2.05. */

55588

+BU_DFP_MISC_1 (DXEX, "dxex", CONST, dfp_dxex_dd)

55589

+BU_DFP_MISC_1 (DXEXQ, "dxexq", CONST, dfp_dxex_td)

55590

+

55591

+/* 2 argument DFP (decimal floating point) functions added in ISA 2.05. */

55592

+BU_DFP_MISC_2 (DDEDPD, "ddedpd", CONST, dfp_ddedpd_dd)

55593

+BU_DFP_MISC_2 (DDEDPDQ, "ddedpdq", CONST, dfp_ddedpd_td)

55594

+BU_DFP_MISC_2 (DENBCD, "denbcd", CONST, dfp_denbcd_dd)

55595

+BU_DFP_MISC_2 (DENBCDQ, "denbcdq", CONST, dfp_denbcd_td)

55596

+BU_DFP_MISC_2 (DIEX, "diex", CONST, dfp_diex_dd)

55597

+BU_DFP_MISC_2 (DIEXQ, "diexq", CONST, dfp_diex_td)

55598

+BU_DFP_MISC_2 (DSCLI, "dscli", CONST, dfp_dscli_dd)

55599

+BU_DFP_MISC_2 (DSCLIQ, "dscliq", CONST, dfp_dscli_td)

55600

+BU_DFP_MISC_2 (DSCRI, "dscri", CONST, dfp_dscri_dd)

55601

+BU_DFP_MISC_2 (DSCRIQ, "dscriq", CONST, dfp_dscri_td)

55602

+

55603

+/* 1 argument BCD functions added in ISA 2.06. */

55604

+BU_P7_MISC_1 (CDTBCD, "cdtbcd", CONST, cdtbcd)

55605

+BU_P7_MISC_1 (CBCDTD, "cbcdtd", CONST, cbcdtd)

55606

+

55607

+/* 2 argument BCD functions added in ISA 2.06. */

55608

+BU_P7_MISC_2 (ADDG6S, "addg6s", CONST, addg6s)

55609

+

55610

+/* 3 argument BCD functions added in ISA 2.07. */

55611

+BU_P8V_MISC_3 (BCDADD, "bcdadd", CONST, bcdadd)

55612

+BU_P8V_MISC_3 (BCDADD_LT, "bcdadd_lt", CONST, bcdadd_lt)

55613

+BU_P8V_MISC_3 (BCDADD_EQ, "bcdadd_eq", CONST, bcdadd_eq)

55614

+BU_P8V_MISC_3 (BCDADD_GT, "bcdadd_gt", CONST, bcdadd_gt)

55615

+BU_P8V_MISC_3 (BCDADD_OV, "bcdadd_ov", CONST, bcdadd_unordered)

55616

+BU_P8V_MISC_3 (BCDSUB, "bcdsub", CONST, bcdsub)

55617

+BU_P8V_MISC_3 (BCDSUB_LT, "bcdsub_lt", CONST, bcdsub_lt)

55618

+BU_P8V_MISC_3 (BCDSUB_EQ, "bcdsub_eq", CONST, bcdsub_eq)

55619

+BU_P8V_MISC_3 (BCDSUB_GT, "bcdsub_gt", CONST, bcdsub_gt)

55620

+BU_P8V_MISC_3 (BCDSUB_OV, "bcdsub_ov", CONST, bcdsub_unordered)

55621

+

55622

+/* 2 argument pack/unpack 128-bit floating point types. */

55623

+BU_DFP_MISC_2 (PACK_TD, "pack_dec128", CONST, packtd)

55624

+BU_DFP_MISC_2 (UNPACK_TD, "unpack_dec128", CONST, unpacktd)

55625

+

55626

+BU_MISC_2 (PACK_TF, "pack_longdouble", CONST, packtf)

55627

+BU_MISC_2 (UNPACK_TF, "unpack_longdouble", CONST, unpacktf)

55628

+BU_MISC_1 (UNPACK_TF_0, "longdouble_dw0", CONST, unpacktf_0)

55629

+BU_MISC_1 (UNPACK_TF_1, "longdouble_dw1", CONST, unpacktf_1)

55630

+

55631

+BU_P7_MISC_2 (PACK_V1TI, "pack_vector_int128", CONST, packv1ti)

55632

+BU_P7_MISC_2 (UNPACK_V1TI, "unpack_vector_int128", CONST, unpackv1ti)

55633

+

55634

+

55635

+/* 1 argument crypto functions. */

55636

+BU_CRYPTO_1 (VSBOX, "vsbox", CONST, crypto_vsbox)

55637

+

55638

+/* 2 argument crypto functions. */

55639

+BU_CRYPTO_2 (VCIPHER, "vcipher", CONST, crypto_vcipher)

55640

+BU_CRYPTO_2 (VCIPHERLAST, "vcipherlast", CONST, crypto_vcipherlast)

55641

+BU_CRYPTO_2 (VNCIPHER, "vncipher", CONST, crypto_vncipher)

55642

+BU_CRYPTO_2 (VNCIPHERLAST, "vncipherlast", CONST, crypto_vncipherlast)

55643

+BU_CRYPTO_2 (VPMSUMB, "vpmsumb", CONST, crypto_vpmsumb)

55644

+BU_CRYPTO_2 (VPMSUMH, "vpmsumh", CONST, crypto_vpmsumh)

55645

+BU_CRYPTO_2 (VPMSUMW, "vpmsumw", CONST, crypto_vpmsumw)

55646

+BU_CRYPTO_2 (VPMSUMD, "vpmsumd", CONST, crypto_vpmsumd)

55647

+

55648

+/* 3 argument crypto functions. */

55649

+BU_CRYPTO_3 (VPERMXOR_V2DI, "vpermxor_v2di", CONST, crypto_vpermxor_v2di)

55650

+BU_CRYPTO_3 (VPERMXOR_V4SI, "vpermxor_v4si", CONST, crypto_vpermxor_v4si)

55651

+BU_CRYPTO_3 (VPERMXOR_V8HI, "vpermxor_v8hi", CONST, crypto_vpermxor_v8hi)

55652

+BU_CRYPTO_3 (VPERMXOR_V16QI, "vpermxor_v16qi", CONST, crypto_vpermxor_v16qi)

55653

+BU_CRYPTO_3 (VSHASIGMAW, "vshasigmaw", CONST, crypto_vshasigmaw)

55654

+BU_CRYPTO_3 (VSHASIGMAD, "vshasigmad", CONST, crypto_vshasigmad)

55655

+

55656

+/* 2 argument crypto overloaded functions. */

55657

+BU_CRYPTO_OVERLOAD_2 (VPMSUM, "vpmsum")

55658

+

55659

+/* 3 argument crypto overloaded functions. */

55660

+BU_CRYPTO_OVERLOAD_3 (VPERMXOR, "vpermxor")

55661

+BU_CRYPTO_OVERLOAD_3 (VSHASIGMA, "vshasigma")

55662

+

55663

+

55664

+/* HTM functions. */

55665

+BU_HTM_1 (TABORT, "tabort", MISC, tabort)

55666

+BU_HTM_3 (TABORTDC, "tabortdc", MISC, tabortdc)

55667

+BU_HTM_3 (TABORTDCI, "tabortdci", MISC, tabortdci)

55668

+BU_HTM_3 (TABORTWC, "tabortwc", MISC, tabortwc)

55669

+BU_HTM_3 (TABORTWCI, "tabortwci", MISC, tabortwci)

55670

+BU_HTM_1 (TBEGIN, "tbegin", MISC, tbegin)

55671

+BU_HTM_1 (TCHECK, "tcheck", MISC, tcheck)

55672

+BU_HTM_1 (TEND, "tend", MISC, tend)

55673

+BU_HTM_0 (TENDALL, "tendall", MISC, tend)

55674

+BU_HTM_0 (TRECHKPT, "trechkpt", MISC, trechkpt)

55675

+BU_HTM_1 (TRECLAIM, "treclaim", MISC, treclaim)

55676

+BU_HTM_0 (TRESUME, "tresume", MISC, tsr)

55677

+BU_HTM_0 (TSUSPEND, "tsuspend", MISC, tsr)

55678

+BU_HTM_1 (TSR, "tsr", MISC, tsr)

55679

+BU_HTM_0 (TTEST, "ttest", MISC, ttest)

55680

+

55681

+BU_HTM_SPR0 (GET_TFHAR, "get_tfhar", MISC, nothing)

55682

+BU_HTM_SPR1 (SET_TFHAR, "set_tfhar", MISC, nothing)

55683

+BU_HTM_SPR0 (GET_TFIAR, "get_tfiar", MISC, nothing)

55684

+BU_HTM_SPR1 (SET_TFIAR, "set_tfiar", MISC, nothing)

55685

+BU_HTM_SPR0 (GET_TEXASR, "get_texasr", MISC, nothing)

55686

+BU_HTM_SPR1 (SET_TEXASR, "set_texasr", MISC, nothing)

55687

+BU_HTM_SPR0 (GET_TEXASRU, "get_texasru", MISC, nothing)

55688

+BU_HTM_SPR1 (SET_TEXASRU, "set_texasru", MISC, nothing)

55689

+

55690

+

55691

/* 3 argument paired floating point builtins. */

55692

BU_PAIRED_3 (MSUB, "msub", FP, fmsv2sf4)

55693

BU_PAIRED_3 (MADD, "madd", FP, fmav2sf4)

55694

@@ -1430,10 +1956,10 @@

55695

RS6000_BTC_FP)

55696

55697

BU_SPECIAL_X (RS6000_BUILTIN_GET_TB, "__builtin_ppc_get_timebase",

55698

- RS6000_BTM_ALWAYS, RS6000_BTC_MISC)

55699

+ RS6000_BTM_ALWAYS, RS6000_BTC_MISC)

55700

55701

BU_SPECIAL_X (RS6000_BUILTIN_MFTB, "__builtin_ppc_mftb",

55702

- RS6000_BTM_ALWAYS, RS6000_BTC_MISC)

55703

+ RS6000_BTM_ALWAYS, RS6000_BTC_MISC)

55704

55705

/* Darwin CfString builtin. */

55706

BU_SPECIAL_X (RS6000_BUILTIN_CFSTRING, "__builtin_cfstring", RS6000_BTM_ALWAYS,

55707

Index: gcc/config/rs6000/rs6000-c.c

55708

===================================================================

55709

--- a/src/gcc/config/rs6000/rs6000-c.c (.../tags/gcc_4_8_2_release)

55710

+++ b/src/gcc/config/rs6000/rs6000-c.c (.../branches/gcc-4_8-branch)

55711

@@ -90,6 +90,8 @@

55712

static GTY(()) tree __bool_keyword;

55713

static GTY(()) tree bool_keyword;

55714

static GTY(()) tree _Bool_keyword;

55715

+static GTY(()) tree __int128_type;

55716

+static GTY(()) tree __uint128_type;

55717

55718

/* Preserved across calls. */

55719

static tree expand_bool_pixel;

55720

@@ -122,9 +124,10 @@

55721

static void

55722

init_vector_keywords (void)

55723

{

55724

- /* Keywords without two leading underscores are context-sensitive,

55725

- and hence implemented as conditional macros, controlled by the

55726

- rs6000_macro_to_expand() function below. */

55727

+ /* Keywords without two leading underscores are context-sensitive, and hence

55728

+ implemented as conditional macros, controlled by the

55729

+ rs6000_macro_to_expand() function below. If we have ISA 2.07 64-bit

55730

+ support, record the __int128_t and __uint128_t types. */

55731

55732

__vector_keyword = get_identifier ("__vector");

55733

C_CPP_HASHNODE (__vector_keyword)->flags |= NODE_CONDITIONAL;

55734

@@ -146,6 +149,12 @@

55735

55736

_Bool_keyword = get_identifier ("_Bool");

55737

C_CPP_HASHNODE (_Bool_keyword)->flags |= NODE_CONDITIONAL;

55738

+

55739

+ if (TARGET_VADDUQM)

55740

+ {

55741

+ __int128_type = get_identifier ("__int128_t");

55742

+ __uint128_type = get_identifier ("__uint128_t");

55743

+ }

55744

}

55745

55746

/* Called to decide whether a conditional macro should be expanded.

55747

@@ -221,7 +230,8 @@

55748

|| rid_code == RID_SHORT || rid_code == RID_SIGNED

55749

|| rid_code == RID_INT || rid_code == RID_CHAR

55750

|| rid_code == RID_FLOAT

55751

- || (rid_code == RID_DOUBLE && TARGET_VSX))

55752

+ || (rid_code == RID_DOUBLE && TARGET_VSX)

55753

+ || (rid_code == RID_INT128 && TARGET_VADDUQM))

55754

{

55755

expand_this = C_CPP_HASHNODE (__vector_keyword);

55756

/* If the next keyword is bool or pixel, it

55757

@@ -248,6 +258,13 @@

55758

expand_bool_pixel = __bool_keyword;

55759

}

55760

}

55761

+

55762

+ /* Support vector __int128_t, but we don't need to worry about bool

55763

+ or pixel on this type. */

55764

+ else if (TARGET_VADDUQM

55765

+ && (ident == C_CPP_HASHNODE (__int128_type)

55766

+ || ident == C_CPP_HASHNODE (__uint128_type)))

55767

+ expand_this = C_CPP_HASHNODE (__vector_keyword);

55768

}

55769

}

55770

else if (expand_bool_pixel && ident == C_CPP_HASHNODE (__pixel_keyword))

55771

@@ -315,6 +332,8 @@

55772

rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6X");

55773

if ((flags & OPTION_MASK_POPCNTD) != 0)

55774

rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");

55775

+ if ((flags & OPTION_MASK_DIRECT_MOVE) != 0)

55776

+ rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8");

55777

if ((flags & OPTION_MASK_SOFT_FLOAT) != 0)

55778

rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT");

55779

if ((flags & OPTION_MASK_RECIP_PRECISION) != 0)

55780

@@ -331,6 +350,16 @@

55781

}

55782

if ((flags & OPTION_MASK_VSX) != 0)

55783

rs6000_define_or_undefine_macro (define_p, "__VSX__");

55784

+ if ((flags & OPTION_MASK_HTM) != 0)

55785

+ rs6000_define_or_undefine_macro (define_p, "__HTM__");

55786

+ if ((flags & OPTION_MASK_P8_VECTOR) != 0)

55787

+ rs6000_define_or_undefine_macro (define_p, "__POWER8_VECTOR__");

55788

+ if ((flags & OPTION_MASK_QUAD_MEMORY) != 0)

55789

+ rs6000_define_or_undefine_macro (define_p, "__QUAD_MEMORY__");

55790

+ if ((flags & OPTION_MASK_QUAD_MEMORY_ATOMIC) != 0)

55791

+ rs6000_define_or_undefine_macro (define_p, "__QUAD_MEMORY_ATOMIC__");

55792

+ if ((flags & OPTION_MASK_CRYPTO) != 0)

55793

+ rs6000_define_or_undefine_macro (define_p, "__CRYPTO__");

55794

55795

/* options from the builtin masks. */

55796

if ((bu_mask & RS6000_BTM_SPE) != 0)

55797

@@ -453,7 +482,11 @@

55798

case ABI_AIX:

55799

builtin_define ("_CALL_AIXDESC");

55800

builtin_define ("_CALL_AIX");

55801

+ builtin_define ("_CALL_ELF=1");

55802

break;

55803

+ case ABI_ELFv2:

55804

+ builtin_define ("_CALL_ELF=2");

55805

+ break;

55806

case ABI_DARWIN:

55807

builtin_define ("_CALL_DARWIN");

55808

break;

55809

@@ -465,6 +498,13 @@

55810

if (TARGET_SOFT_FLOAT || !TARGET_FPRS)

55811

builtin_define ("__NO_FPRS__");

55812

55813

+ /* Whether aggregates passed by value are aligned to a 16 byte boundary

55814

+ if their alignment is 16 bytes or larger. */

55815

+ if ((TARGET_MACHO && rs6000_darwin64_abi)

55816

+ || DEFAULT_ABI == ABI_ELFv2

55817

+ || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm))

55818

+ builtin_define ("__STRUCT_PARM_ALIGN__=16");

55819

+

55820

/* Generate defines for Xilinx FPU. */

55821

if (rs6000_xilinx_fpu)

55822

{

55823

@@ -505,6 +545,8 @@

55824

RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },

55825

{ ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SI,

55826

RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },

55827

+ { ALTIVEC_BUILTIN_VEC_ABS, P8V_BUILTIN_ABS_V2DI,

55828

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },

55829

{ ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SF,

55830

RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },

55831

{ ALTIVEC_BUILTIN_VEC_ABS, VSX_BUILTIN_XVABSDP,

55832

@@ -577,6 +619,10 @@

55833

RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },

55834

{ ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSH,

55835

RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },

55836

+ { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW,

55837

+ RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },

55838

+ { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW,

55839

+ RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },

55840

{ ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHPX,

55841

RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },

55842

{ ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH,

55843

@@ -583,6 +629,10 @@

55844

RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },

55845

{ ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH,

55846

RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },

55847

+ { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW,

55848

+ RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },

55849

+ { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW,

55850

+ RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },

55851

{ ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX,

55852

RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 },

55853

{ ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX,

55854

@@ -601,6 +651,10 @@

55855

RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },

55856

{ ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSH,

55857

RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },

55858

+ { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW,

55859

+ RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },

55860

+ { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW,

55861

+ RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },

55862

{ ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX,

55863

RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 },

55864

{ ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX,

55865

@@ -651,10 +705,27 @@

55866

RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },

55867

{ ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,

55868

RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },

55869

+ { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,

55870

+ RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },

55871

+ { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,

55872

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },

55873

+ { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,

55874

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },

55875

+ { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,

55876

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

55877

+ { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,

55878

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },

55879

+ { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,

55880

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

55881

{ ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDFP,

55882

RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },

55883

{ ALTIVEC_BUILTIN_VEC_ADD, VSX_BUILTIN_XVADDDP,

55884

RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },

55885

+ { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUQM,

55886

+ RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },

55887

+ { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUQM,

55888

+ RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,

55889

+ RS6000_BTI_unsigned_V1TI, 0 },

55890

{ ALTIVEC_BUILTIN_VEC_VADDFP, ALTIVEC_BUILTIN_VADDFP,

55891

RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },

55892

{ ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,

55893

@@ -937,6 +1008,10 @@

55894

RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },

55895

{ ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW,

55896

RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },

55897

+ { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD,

55898

+ RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },

55899

+ { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD,

55900

+ RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

55901

{ ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQFP,

55902

RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },

55903

{ ALTIVEC_BUILTIN_VEC_CMPEQ, VSX_BUILTIN_XVCMPEQDP,

55904

@@ -975,6 +1050,10 @@

55905

RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },

55906

{ ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSW,

55907

RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },

55908

+ { ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTUD,

55909

+ RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

55910

+ { ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTSD,

55911

+ RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },

55912

{ ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTFP,

55913

RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },

55914

{ ALTIVEC_BUILTIN_VEC_CMPGT, VSX_BUILTIN_XVCMPGTDP,

55915

@@ -1021,6 +1100,10 @@

55916

RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },

55917

{ ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSW,

55918

RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },

55919

+ { ALTIVEC_BUILTIN_VEC_CMPLT, P8V_BUILTIN_VCMPGTUD,

55920

+ RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

55921

+ { ALTIVEC_BUILTIN_VEC_CMPLT, P8V_BUILTIN_VCMPGTSD,

55922

+ RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },

55923

{ ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTFP,

55924

RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },

55925

{ ALTIVEC_BUILTIN_VEC_CMPLT, VSX_BUILTIN_XVCMPGTDP,

55926

@@ -1045,54 +1128,54 @@

55927

RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },

55928

{ VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVDP,

55929

RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },

55930

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55931

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DF,

55932

RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },

55933

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55934

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,

55935

RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },

55936

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55937

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,

55938

RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,

55939

~RS6000_BTI_unsigned_V2DI, 0 },

55940

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55941

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,

55942

RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },

55943

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55944

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SF,

55945

RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },

55946

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55947

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SF,

55948

RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },

55949

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55950

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,

55951

RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },

55952

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55953

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,

55954

RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },

55955

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55956

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,

55957

RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },

55958

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55959

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,

55960

RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },

55961

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55962

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,

55963

RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },

55964

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55965

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,

55966

RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },

55967

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55968

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,

55969

RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },

55970

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55971

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,

55972

RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },

55973

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55974

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,

55975

RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },

55976

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55977

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,

55978

RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },

55979

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55980

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,

55981

RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },

55982

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55983

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,

55984

RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },

55985

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55986

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,

55987

RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },

55988

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55989

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,

55990

RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },

55991

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55992

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,

55993

RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },

55994

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55995

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,

55996

RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },

55997

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55998

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,

55999

RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },

56000

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

56001

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,

56002

RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },

56003

{ ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEBX,

56004

RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },

56005

@@ -1130,55 +1213,55 @@

56006

RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },

56007

{ ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_LVEBX,

56008

RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },

56009

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

56010

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF,

56011

RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },

56012

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

56013

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF,

56014

RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },

56015

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

56016

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,

56017

RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },

56018

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

56019

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,

56020

RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },

56021

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

56022

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,

56023

RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },

56024

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

56025

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,

56026

RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },

56027

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

56028

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,

56029

RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },

56030

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

56031

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,

56032

RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },

56033

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

56034

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,

56035

RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },

56036

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

56037

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,

56038

RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },

56039

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

56040

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,

56041

RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },

56042

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

56043

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,

56044

RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },

56045

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

56046

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,

56047

RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },

56048

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

56049

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,

56050

RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },

56051

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

56052

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,

56053

RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },

56054

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

56055

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,

56056

RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },

56057

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

56058

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,

56059

RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },

56060

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

56061

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,

56062

RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },

56063

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

56064

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,

56065

RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,

56066

~RS6000_BTI_unsigned_V16QI, 0 },

56067

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

56068

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,

56069

RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },

56070

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

56071

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DF,

56072

RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },

56073

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

56074

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,

56075

RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },

56076

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

56077

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,

56078

RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,

56079

~RS6000_BTI_unsigned_V2DI, 0 },

56080

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

56081

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,

56082

RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },

56083

{ ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,

56084

RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },

56085

@@ -1418,6 +1501,18 @@

56086

RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },

56087

{ ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW,

56088

RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },

56089

+ { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD,

56090

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

56091

+ { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD,

56092

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },

56093

+ { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD,

56094

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

56095

+ { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD,

56096

+ RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },

56097

+ { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD,

56098

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },

56099

+ { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD,

56100

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },

56101

{ ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXFP,

56102

RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },

56103

{ ALTIVEC_BUILTIN_VEC_MAX, VSX_BUILTIN_XVMAXDP,

56104

@@ -1604,6 +1699,18 @@

56105

RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },

56106

{ ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW,

56107

RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },

56108

+ { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD,

56109

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

56110

+ { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD,

56111

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },

56112

+ { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD,

56113

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

56114

+ { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD,

56115

+ RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },

56116

+ { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD,

56117

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },

56118

+ { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD,

56119

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },

56120

{ ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINFP,

56121

RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },

56122

{ ALTIVEC_BUILTIN_VEC_MIN, VSX_BUILTIN_XVMINDP,

56123

@@ -1786,6 +1893,12 @@

56124

RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },

56125

{ ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM,

56126

RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },

56127

+ { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,

56128

+ RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },

56129

+ { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,

56130

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

56131

+ { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,

56132

+ RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },

56133

{ ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM,

56134

RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },

56135

{ ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM,

56136

@@ -1812,6 +1925,10 @@

56137

RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },

56138

{ ALTIVEC_BUILTIN_VEC_VPKUWUS, ALTIVEC_BUILTIN_VPKUWUS,

56139

RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },

56140

+ { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKUDUS,

56141

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

56142

+ { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKSDSS,

56143

+ RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },

56144

{ ALTIVEC_BUILTIN_VEC_VPKSHSS, ALTIVEC_BUILTIN_VPKSHSS,

56145

RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },

56146

{ ALTIVEC_BUILTIN_VEC_VPKUHUS, ALTIVEC_BUILTIN_VPKUHUS,

56147

@@ -1824,6 +1941,8 @@

56148

RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },

56149

{ ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKSWUS,

56150

RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },

56151

+ { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKSDUS,

56152

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },

56153

{ ALTIVEC_BUILTIN_VEC_VPKSWUS, ALTIVEC_BUILTIN_VPKSWUS,

56154

RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },

56155

{ ALTIVEC_BUILTIN_VEC_VPKSHUS, ALTIVEC_BUILTIN_VPKSHUS,

56156

@@ -1844,6 +1963,10 @@

56157

RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },

56158

{ ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLW,

56159

RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },

56160

+ { ALTIVEC_BUILTIN_VEC_RL, P8V_BUILTIN_VRLD,

56161

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

56162

+ { ALTIVEC_BUILTIN_VEC_RL, P8V_BUILTIN_VRLD,

56163

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

56164

{ ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VRLW,

56165

RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },

56166

{ ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VRLW,

56167

@@ -1868,6 +1991,10 @@

56168

RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },

56169

{ ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLW,

56170

RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },

56171

+ { ALTIVEC_BUILTIN_VEC_SL, P8V_BUILTIN_VSLD,

56172

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

56173

+ { ALTIVEC_BUILTIN_VEC_SL, P8V_BUILTIN_VSLD,

56174

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

56175

{ ALTIVEC_BUILTIN_VEC_SQRT, VSX_BUILTIN_XVSQRTDP,

56176

RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },

56177

{ ALTIVEC_BUILTIN_VEC_SQRT, VSX_BUILTIN_XVSQRTSP,

56178

@@ -2032,6 +2159,10 @@

56179

RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },

56180

{ ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRW,

56181

RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },

56182

+ { ALTIVEC_BUILTIN_VEC_SR, P8V_BUILTIN_VSRD,

56183

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

56184

+ { ALTIVEC_BUILTIN_VEC_SR, P8V_BUILTIN_VSRD,

56185

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

56186

{ ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VSRW,

56187

RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },

56188

{ ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VSRW,

56189

@@ -2056,6 +2187,10 @@

56190

RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },

56191

{ ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAW,

56192

RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },

56193

+ { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRAD,

56194

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

56195

+ { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRD,

56196

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

56197

{ ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW,

56198

RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },

56199

{ ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW,

56200

@@ -2196,10 +2331,27 @@

56201

RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },

56202

{ ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,

56203

RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },

56204

+ { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,

56205

+ RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },

56206

+ { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,

56207

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },

56208

+ { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,

56209

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },

56210

+ { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,

56211

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

56212

+ { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,

56213

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },

56214

+ { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,

56215

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

56216

{ ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBFP,

56217

RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },

56218

{ ALTIVEC_BUILTIN_VEC_SUB, VSX_BUILTIN_XVSUBDP,

56219

RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },

56220

+ { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUQM,

56221

+ RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },

56222

+ { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUQM,

56223

+ RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,

56224

+ RS6000_BTI_unsigned_V1TI, 0 },

56225

{ ALTIVEC_BUILTIN_VEC_VSUBFP, ALTIVEC_BUILTIN_VSUBFP,

56226

RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },

56227

{ ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,

56228

@@ -2730,63 +2882,63 @@

56229

RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_NOT_OPAQUE },

56230

{ ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,

56231

RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_NOT_OPAQUE },

56232

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

56233

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DF,

56234

RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },

56235

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

56236

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,

56237

RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },

56238

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

56239

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,

56240

RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,

56241

~RS6000_BTI_unsigned_V2DI },

56242

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

56243

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,

56244

RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,

56245

~RS6000_BTI_bool_V2DI },

56246

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

56247

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SF,

56248

RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },

56249

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

56250

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SF,

56251

RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },

56252

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

56253

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,

56254

RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },

56255

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

56256

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,

56257

RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },

56258

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

56259

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,

56260

RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },

56261

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

56262

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,

56263

RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },

56264

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

56265

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,

56266

RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },

56267

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

56268

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,

56269

RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },

56270

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

56271

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,

56272

RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },

56273

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

56274

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,

56275

RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },

56276

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

56277

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,

56278

RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },

56279

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

56280

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,

56281

RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },

56282

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

56283

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,

56284

RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },

56285

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

56286

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,

56287

RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },

56288

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

56289

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,

56290

RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },

56291

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

56292

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,

56293

RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },

56294

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

56295

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,

56296

RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },

56297

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

56298

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,

56299

RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },

56300

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

56301

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,

56302

RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },

56303

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

56304

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,

56305

RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },

56306

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

56307

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,

56308

RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },

56309

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

56310

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,

56311

RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },

56312

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

56313

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,

56314

RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },

56315

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

56316

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,

56317

RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },

56318

{ ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,

56319

RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },

56320

@@ -2858,64 +3010,64 @@

56321

RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void },

56322

{ ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,

56323

RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void },

56324

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

56325

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SF,

56326

RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },

56327

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

56328

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SF,

56329

RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },

56330

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

56331

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,

56332

RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },

56333

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

56334

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,

56335

RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },

56336

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

56337

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,

56338

RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },

56339

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

56340

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,

56341

RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },

56342

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

56343

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,

56344

RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },

56345

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

56346

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,

56347

RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },

56348

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

56349

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,

56350

RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },

56351

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

56352

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,

56353

RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },

56354

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

56355

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,

56356

RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },

56357

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

56358

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,

56359

RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },

56360

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

56361

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,

56362

RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },

56363

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

56364

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,

56365

RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },

56366

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

56367

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,

56368

RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },

56369

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

56370

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,

56371

RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },

56372

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

56373

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,

56374

RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },

56375

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

56376

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,

56377

RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },

56378

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

56379

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,

56380

RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },

56381

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

56382

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,

56383

RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },

56384

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

56385

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,

56386

RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },

56387

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

56388

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,

56389

RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },

56390

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

56391

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,

56392

RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },

56393

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

56394

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,

56395

RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },

56396

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

56397

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DF,

56398

RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },

56399

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

56400

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DF,

56401

RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },

56402

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

56403

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI,

56404

RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },

56405

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

56406

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI,

56407

RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,

56408

~RS6000_BTI_unsigned_V2DI },

56409

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

56410

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI,

56411

RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,

56412

~RS6000_BTI_bool_V2DI },

56413

{ ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,

56414

@@ -3327,6 +3479,20 @@

56415

RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },

56416

{ ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,

56417

RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI },

56418

+ { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,

56419

+ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI },

56420

+ { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,

56421

+ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },

56422

+ { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,

56423

+ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },

56424

+ { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,

56425

+ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI },

56426

+ { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,

56427

+ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },

56428

+ { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,

56429

+ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },

56430

+ { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,

56431

+ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI },

56432

{ ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQFP_P,

56433

RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },

56434

{ ALTIVEC_BUILTIN_VEC_VCMPEQ_P, VSX_BUILTIN_XVCMPEQDP_P,

56435

@@ -3372,11 +3538,509 @@

56436

RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },

56437

{ ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P,

56438

RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },

56439

+ { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P,

56440

+ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI },

56441

+ { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P,

56442

+ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },

56443

+ { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P,

56444

+ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },

56445

+ { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P,

56446

+ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI },

56447

+ { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P,

56448

+ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },

56449

+ { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P,

56450

+ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },

56451

{ ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGEFP_P,

56452

RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },

56453

{ ALTIVEC_BUILTIN_VEC_VCMPGE_P, VSX_BUILTIN_XVCMPGEDP_P,

56454

RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF },

56455

56456

+ /* Power8 vector overloaded functions. */

56457

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,

56458

+ RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },

56459

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,

56460

+ RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },

56461

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,

56462

+ RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },

56463

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,

56464

+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI,

56465

+ RS6000_BTI_unsigned_V16QI, 0 },

56466

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,

56467

+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,

56468

+ RS6000_BTI_bool_V16QI, 0 },

56469

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,

56470

+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,

56471

+ RS6000_BTI_unsigned_V16QI, 0 },

56472

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,

56473

+ RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },

56474

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,

56475

+ RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },

56476

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,

56477

+ RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },

56478

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,

56479

+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI,

56480

+ RS6000_BTI_unsigned_V8HI, 0 },

56481

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,

56482

+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,

56483

+ RS6000_BTI_bool_V8HI, 0 },

56484

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,

56485

+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,

56486

+ RS6000_BTI_unsigned_V8HI, 0 },

56487

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,

56488

+ RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },

56489

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,

56490

+ RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },

56491

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,

56492

+ RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },

56493

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,

56494

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI,

56495

+ RS6000_BTI_unsigned_V4SI, 0 },

56496

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,

56497

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,

56498

+ RS6000_BTI_bool_V4SI, 0 },

56499

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,

56500

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,

56501

+ RS6000_BTI_unsigned_V4SI, 0 },

56502

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,

56503

+ RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },

56504

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,

56505

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },

56506

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,

56507

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },

56508

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,

56509

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,

56510

+ RS6000_BTI_unsigned_V2DI, 0 },

56511

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,

56512

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,

56513

+ RS6000_BTI_bool_V2DI, 0 },

56514

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,

56515

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,

56516

+ RS6000_BTI_unsigned_V2DI, 0 },

56517

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SF,

56518

+ RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },

56519

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DF,

56520

+ RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },

56521

+

56522

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,

56523

+ RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },

56524

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,

56525

+ RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },

56526

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,

56527

+ RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },

56528

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,

56529

+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI,

56530

+ RS6000_BTI_unsigned_V16QI, 0 },

56531

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,

56532

+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,

56533

+ RS6000_BTI_bool_V16QI, 0 },

56534

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,

56535

+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,

56536

+ RS6000_BTI_unsigned_V16QI, 0 },

56537

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,

56538

+ RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },

56539

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,

56540

+ RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },

56541

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,

56542

+ RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },

56543

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,

56544

+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI,

56545

+ RS6000_BTI_unsigned_V8HI, 0 },

56546

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,

56547

+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,

56548

+ RS6000_BTI_bool_V8HI, 0 },

56549

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,

56550

+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,

56551

+ RS6000_BTI_unsigned_V8HI, 0 },

56552

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,

56553

+ RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },

56554

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,

56555

+ RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },

56556

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,

56557

+ RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },

56558

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,

56559

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI,

56560

+ RS6000_BTI_unsigned_V4SI, 0 },

56561

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,

56562

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,

56563

+ RS6000_BTI_bool_V4SI, 0 },

56564

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,

56565

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,

56566

+ RS6000_BTI_unsigned_V4SI, 0 },

56567

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,

56568

+ RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },

56569

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,

56570

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },

56571

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,

56572

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },

56573

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,

56574

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,

56575

+ RS6000_BTI_unsigned_V2DI, 0 },

56576

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,

56577

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,

56578

+ RS6000_BTI_bool_V2DI, 0 },

56579

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,

56580

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,

56581

+ RS6000_BTI_unsigned_V2DI, 0 },

56582

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SF,

56583

+ RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },

56584

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DF,

56585

+ RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },

56586

+

56587

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,

56588

+ RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },

56589

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,

56590

+ RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },

56591

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,

56592

+ RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },

56593

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,

56594

+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI,

56595

+ RS6000_BTI_unsigned_V16QI, 0 },

56596

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,

56597

+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,

56598

+ RS6000_BTI_bool_V16QI, 0 },

56599

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,

56600

+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,

56601

+ RS6000_BTI_unsigned_V16QI, 0 },

56602

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,

56603

+ RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },

56604

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,

56605

+ RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },

56606

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,

56607

+ RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },

56608

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,

56609

+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI,

56610

+ RS6000_BTI_unsigned_V8HI, 0 },

56611

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,

56612

+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,

56613

+ RS6000_BTI_bool_V8HI, 0 },

56614

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,

56615

+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,

56616

+ RS6000_BTI_unsigned_V8HI, 0 },

56617

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,

56618

+ RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },

56619

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,

56620

+ RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },

56621

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,

56622

+ RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },

56623

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,

56624

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI,

56625

+ RS6000_BTI_unsigned_V4SI, 0 },

56626

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,

56627

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,

56628

+ RS6000_BTI_bool_V4SI, 0 },

56629

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,

56630

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,

56631

+ RS6000_BTI_unsigned_V4SI, 0 },

56632

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,

56633

+ RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },

56634

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,

56635

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },

56636

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,

56637

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },

56638

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,

56639

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,

56640

+ RS6000_BTI_unsigned_V2DI, 0 },

56641

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,

56642

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,

56643

+ RS6000_BTI_bool_V2DI, 0 },

56644

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,

56645

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,

56646

+ RS6000_BTI_unsigned_V2DI, 0 },

56647

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SF,

56648

+ RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },

56649

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DF,

56650

+ RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },

56651

+

56652

+ { P8V_BUILTIN_VEC_VADDCUQ, P8V_BUILTIN_VADDCUQ,

56653

+ RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },

56654

+ { P8V_BUILTIN_VEC_VADDCUQ, P8V_BUILTIN_VADDCUQ,

56655

+ RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,

56656

+ RS6000_BTI_unsigned_V1TI, 0 },

56657

+

56658

+ { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,

56659

+ RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },

56660

+ { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,

56661

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },

56662

+ { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,

56663

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },

56664

+ { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,

56665

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

56666

+ { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,

56667

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },

56668

+ { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,

56669

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

56670

+

56671

+ { P8V_BUILTIN_VEC_VADDUQM, P8V_BUILTIN_VADDUQM,

56672

+ RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },

56673

+ { P8V_BUILTIN_VEC_VADDUQM, P8V_BUILTIN_VADDUQM,

56674

+ RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,

56675

+ RS6000_BTI_unsigned_V1TI, 0 },

56676

+

56677

+ { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,

56678

+ RS6000_BTI_V2DI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },

56679

+ { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,

56680

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI,

56681

+ RS6000_BTI_unsigned_V16QI, 0 },

56682

+

56683

+ { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZB,

56684

+ RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },

56685

+ { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZB,

56686

+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },

56687

+ { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZH,

56688

+ RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },

56689

+ { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZH,

56690

+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },

56691

+ { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZW,

56692

+ RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },

56693

+ { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZW,

56694

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },

56695

+ { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZD,

56696

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },

56697

+ { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZD,

56698

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },

56699

+

56700

+ { P8V_BUILTIN_VEC_VCLZB, P8V_BUILTIN_VCLZB,

56701

+ RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },

56702

+ { P8V_BUILTIN_VEC_VCLZB, P8V_BUILTIN_VCLZB,

56703

+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },

56704

+

56705

+ { P8V_BUILTIN_VEC_VCLZH, P8V_BUILTIN_VCLZH,

56706

+ RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },

56707

+ { P8V_BUILTIN_VEC_VCLZH, P8V_BUILTIN_VCLZH,

56708

+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },

56709

+

56710

+ { P8V_BUILTIN_VEC_VCLZW, P8V_BUILTIN_VCLZW,

56711

+ RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },

56712

+ { P8V_BUILTIN_VEC_VCLZW, P8V_BUILTIN_VCLZW,

56713

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },

56714

+

56715

+ { P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD,

56716

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },

56717

+ { P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD,

56718

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },

56719

+

56720

+ { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,

56721

+ RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },

56722

+ { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,

56723

+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },

56724

+

56725

+ { P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ,

56726

+ RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },

56727

+ { P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ,

56728

+ RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,

56729

+ RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },

56730

+

56731

+ { P8V_BUILTIN_VEC_VADDEUQM, P8V_BUILTIN_VADDEUQM,

56732

+ RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },

56733

+ { P8V_BUILTIN_VEC_VADDEUQM, P8V_BUILTIN_VADDEUQM,

56734

+ RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,

56735

+ RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },

56736

+

56737

+ { P8V_BUILTIN_VEC_VSUBECUQ, P8V_BUILTIN_VSUBECUQ,

56738

+ RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },

56739

+ { P8V_BUILTIN_VEC_VSUBECUQ, P8V_BUILTIN_VSUBECUQ,

56740

+ RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,

56741

+ RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },

56742

+

56743

+ { P8V_BUILTIN_VEC_VSUBEUQM, P8V_BUILTIN_VSUBEUQM,

56744

+ RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },

56745

+ { P8V_BUILTIN_VEC_VSUBEUQM, P8V_BUILTIN_VSUBEUQM,

56746

+ RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,

56747

+ RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },

56748

+

56749

+ { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD,

56750

+ RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },

56751

+ { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD,

56752

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },

56753

+ { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD,

56754

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },

56755

+

56756

+ { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD,

56757

+ RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },

56758

+ { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD,

56759

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },

56760

+ { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD,

56761

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },

56762

+

56763

+ { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD,

56764

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,

56765

+ RS6000_BTI_unsigned_V2DI, 0 },

56766

+ { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD,

56767

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,

56768

+ RS6000_BTI_bool_V2DI, 0 },

56769

+ { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD,

56770

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,

56771

+ RS6000_BTI_unsigned_V2DI, 0 },

56772

+

56773

+ { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD,

56774

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,

56775

+ RS6000_BTI_unsigned_V2DI, 0 },

56776

+ { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD,

56777

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,

56778

+ RS6000_BTI_bool_V2DI, 0 },

56779

+ { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD,

56780

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,

56781

+ RS6000_BTI_unsigned_V2DI, 0 },

56782

+

56783

+ { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW,

56784

+ RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },

56785

+ { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW,

56786

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,

56787

+ RS6000_BTI_unsigned_V4SI, 0 },

56788

+

56789

+ { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW,

56790

+ RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },

56791

+ { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW,

56792

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,

56793

+ RS6000_BTI_unsigned_V4SI, 0 },

56794

+

56795

+ { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTB,

56796

+ RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },

56797

+ { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTB,

56798

+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },

56799

+ { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTH,

56800

+ RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },

56801

+ { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTH,

56802

+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },

56803

+ { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTW,

56804

+ RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },

56805

+ { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTW,

56806

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },

56807

+ { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTD,

56808

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },

56809

+ { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTD,

56810

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },

56811

+

56812

+ { P8V_BUILTIN_VEC_VPOPCNTB, P8V_BUILTIN_VPOPCNTB,

56813

+ RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },

56814

+ { P8V_BUILTIN_VEC_VPOPCNTB, P8V_BUILTIN_VPOPCNTB,

56815

+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },

56816

+

56817

+ { P8V_BUILTIN_VEC_VPOPCNTH, P8V_BUILTIN_VPOPCNTH,

56818

+ RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },

56819

+ { P8V_BUILTIN_VEC_VPOPCNTH, P8V_BUILTIN_VPOPCNTH,

56820

+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },

56821

+

56822

+ { P8V_BUILTIN_VEC_VPOPCNTW, P8V_BUILTIN_VPOPCNTW,

56823

+ RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },

56824

+ { P8V_BUILTIN_VEC_VPOPCNTW, P8V_BUILTIN_VPOPCNTW,

56825

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },

56826

+

56827

+ { P8V_BUILTIN_VEC_VPOPCNTD, P8V_BUILTIN_VPOPCNTD,

56828

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },

56829

+ { P8V_BUILTIN_VEC_VPOPCNTD, P8V_BUILTIN_VPOPCNTD,

56830

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },

56831

+

56832

+ { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM,

56833

+ RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },

56834

+ { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM,

56835

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

56836

+ { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM,

56837

+ RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },

56838

+

56839

+ { P8V_BUILTIN_VEC_VPKSDSS, P8V_BUILTIN_VPKSDSS,

56840

+ RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },

56841

+

56842

+ { P8V_BUILTIN_VEC_VPKUDUS, P8V_BUILTIN_VPKUDUS,

56843

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

56844

+

56845

+ { P8V_BUILTIN_VEC_VPKSDUS, P8V_BUILTIN_VPKSDUS,

56846

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },

56847

+

56848

+ { P8V_BUILTIN_VEC_VRLD, P8V_BUILTIN_VRLD,

56849

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

56850

+ { P8V_BUILTIN_VEC_VRLD, P8V_BUILTIN_VRLD,

56851

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

56852

+

56853

+ { P8V_BUILTIN_VEC_VSLD, P8V_BUILTIN_VSLD,

56854

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

56855

+ { P8V_BUILTIN_VEC_VSLD, P8V_BUILTIN_VSLD,

56856

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

56857

+

56858

+ { P8V_BUILTIN_VEC_VSRD, P8V_BUILTIN_VSRD,

56859

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

56860

+ { P8V_BUILTIN_VEC_VSRD, P8V_BUILTIN_VSRD,

56861

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

56862

+

56863

+ { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRAD,

56864

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

56865

+ { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRD,

56866

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

56867

+

56868

+ { P8V_BUILTIN_VEC_VSUBCUQ, P8V_BUILTIN_VSUBCUQ,

56869

+ RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },

56870

+ { P8V_BUILTIN_VEC_VSUBCUQ, P8V_BUILTIN_VSUBCUQ,

56871

+ RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,

56872

+ RS6000_BTI_unsigned_V1TI, 0 },

56873

+

56874

+ { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,

56875

+ RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },

56876

+ { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,

56877

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },

56878

+ { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,

56879

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },

56880

+ { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,

56881

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

56882

+ { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,

56883

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },

56884

+ { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,

56885

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

56886

+

56887

+ { P8V_BUILTIN_VEC_VSUBUQM, P8V_BUILTIN_VSUBUQM,

56888

+ RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },

56889

+ { P8V_BUILTIN_VEC_VSUBUQM, P8V_BUILTIN_VSUBUQM,

56890

+ RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,

56891

+ RS6000_BTI_unsigned_V1TI, 0 },

56892

+

56893

+ { P8V_BUILTIN_VEC_VUPKHSW, P8V_BUILTIN_VUPKHSW,

56894

+ RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },

56895

+ { P8V_BUILTIN_VEC_VUPKHSW, P8V_BUILTIN_VUPKHSW,

56896

+ RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },

56897

+

56898

+ { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW,

56899

+ RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },

56900

+ { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW,

56901

+ RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },

56902

+

56903

+ { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,

56904

+ RS6000_BTI_V16QI, 0, 0, 0 },

56905

+ { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,

56906

+ RS6000_BTI_unsigned_V16QI, 0, 0, 0 },

56907

+

56908

+ /* Crypto builtins. */

56909

+ { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V16QI,

56910

+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,

56911

+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },

56912

+ { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V8HI,

56913

+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,

56914

+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },

56915

+ { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V4SI,

56916

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,

56917

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },

56918

+ { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V2DI,

56919

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,

56920

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },

56921

+

56922

+ { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMB,

56923

+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,

56924

+ RS6000_BTI_unsigned_V16QI, 0 },

56925

+ { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMH,

56926

+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,

56927

+ RS6000_BTI_unsigned_V8HI, 0 },

56928

+ { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMW,

56929

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,

56930

+ RS6000_BTI_unsigned_V4SI, 0 },

56931

+ { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMD,

56932

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,

56933

+ RS6000_BTI_unsigned_V2DI, 0 },

56934

+

56935

+ { CRYPTO_BUILTIN_VSHASIGMA, CRYPTO_BUILTIN_VSHASIGMAW,

56936

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,

56937

+ RS6000_BTI_INTSI, RS6000_BTI_INTSI },

56938

+ { CRYPTO_BUILTIN_VSHASIGMA, CRYPTO_BUILTIN_VSHASIGMAD,

56939

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,

56940

+ RS6000_BTI_INTSI, RS6000_BTI_INTSI },

56941

+

56942

{ (enum rs6000_builtins) 0, (enum rs6000_builtins) 0, 0, 0, 0, 0 }

56943

};

56944

56945

@@ -3560,6 +4224,10 @@

56946

unsigned_p = TYPE_UNSIGNED (type);

56947

switch (TYPE_MODE (type))

56948

{

56949

+ case TImode:

56950

+ type = (unsigned_p ? unsigned_V1TI_type_node : V1TI_type_node);

56951

+ size = 1;

56952

+ break;

56953

case DImode:

56954

type = (unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node);

56955

size = 2;

56956

@@ -3591,7 +4259,7 @@

56957

return build_constructor (type, vec);

56958

}

56959

56960

- /* For now use pointer tricks to do the extaction, unless we are on VSX

56961

+ /* For now use pointer tricks to do the extraction, unless we are on VSX

56962

extracting a double from a constant offset. */

56963

if (fcode == ALTIVEC_BUILTIN_VEC_EXTRACT)

56964

{

56965

@@ -3619,6 +4287,17 @@

56966

if (!INTEGRAL_TYPE_P (TREE_TYPE (arg2)))

56967

goto bad;

56968

56969

+ /* If we are targeting little-endian, but -maltivec=be has been

56970

+ specified to override the element order, adjust the element

56971

+ number accordingly. */

56972

+ if (!BYTES_BIG_ENDIAN && rs6000_altivec_element_order == 2)

56973

+ {

56974

+ unsigned int last_elem = TYPE_VECTOR_SUBPARTS (arg1_type) - 1;

56975

+ arg2 = fold_build2_loc (loc, MINUS_EXPR, TREE_TYPE (arg2),

56976

+ build_int_cstu (TREE_TYPE (arg2), last_elem),

56977

+ arg2);

56978

+ }

56979

+

56980

/* If we can use the VSX xxpermdi instruction, use that for extract. */

56981

mode = TYPE_MODE (arg1_type);

56982

if ((mode == V2DFmode || mode == V2DImode) && VECTOR_MEM_VSX_P (mode)

56983

@@ -3636,6 +4315,14 @@

56984

if (call)

56985

return build_call_expr (call, 2, arg1, arg2);

56986

}

56987

+ else if (mode == V1TImode && VECTOR_MEM_VSX_P (mode)

56988

+ && TREE_CODE (arg2) == INTEGER_CST

56989

+ && TREE_INT_CST_HIGH (arg2) == 0

56990

+ && TREE_INT_CST_LOW (arg2) == 0)

56991

+ {

56992

+ tree call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V1TI];

56993

+ return build_call_expr (call, 2, arg1, arg2);

56994

+ }

56995

56996

/* Build *(((arg1_inner_type*)&(vector type){arg1})+arg2). */

56997

arg1_inner_type = TREE_TYPE (arg1_type);

56998

@@ -3666,7 +4353,7 @@

56999

return stmt;

57000

}

57001

57002

- /* For now use pointer tricks to do the insertation, unless we are on VSX

57003

+ /* For now use pointer tricks to do the insertion, unless we are on VSX

57004

inserting a double to a constant offset.. */

57005

if (fcode == ALTIVEC_BUILTIN_VEC_INSERT)

57006

{

57007

@@ -3696,6 +4383,17 @@

57008

if (!INTEGRAL_TYPE_P (TREE_TYPE (arg2)))

57009

goto bad;

57010

57011

+ /* If we are targeting little-endian, but -maltivec=be has been

57012

+ specified to override the element order, adjust the element

57013

+ number accordingly. */

57014

+ if (!BYTES_BIG_ENDIAN && rs6000_altivec_element_order == 2)

57015

+ {

57016

+ unsigned int last_elem = TYPE_VECTOR_SUBPARTS (arg1_type) - 1;

57017

+ arg2 = fold_build2_loc (loc, MINUS_EXPR, TREE_TYPE (arg2),

57018

+ build_int_cstu (TREE_TYPE (arg2), last_elem),

57019

+ arg2);

57020

+ }

57021

+

57022

/* If we can use the VSX xxpermdi instruction, use that for insert. */

57023

mode = TYPE_MODE (arg1_type);

57024

if ((mode == V2DFmode || mode == V2DImode) && VECTOR_UNIT_VSX_P (mode)

57025

@@ -3715,7 +4413,18 @@

57026

if (call)

57027

return build_call_expr (call, 3, arg1, arg0, arg2);

57028

}

57029

+ else if (mode == V1TImode && VECTOR_UNIT_VSX_P (mode)

57030

+ && TREE_CODE (arg2) == INTEGER_CST

57031

+ && TREE_INT_CST_HIGH (arg2) == 0

57032

+ && TREE_INT_CST_LOW (arg2) == 0)

57033

+ {

57034

+ tree call = rs6000_builtin_decls[VSX_BUILTIN_VEC_SET_V1TI];

57035

57036

+ /* Note, __builtin_vec_insert_<xxx> has vector and scalar types

57037

+ reversed. */

57038

+ return build_call_expr (call, 3, arg1, arg0, arg2);

57039

+ }

57040

+

57041

/* Build *(((arg1_inner_type*)&(vector type){arg1})+arg2) = arg0. */

57042

arg1_inner_type = TREE_TYPE (arg1_type);

57043

arg2 = build_binary_op (loc, BIT_AND_EXPR, arg2,

57044

@@ -3824,7 +4533,8 @@

57045

&& (desc->op2 == RS6000_BTI_NOT_OPAQUE

57046

|| rs6000_builtin_type_compatible (types[1], desc->op2))

57047

&& (desc->op3 == RS6000_BTI_NOT_OPAQUE

57048

- || rs6000_builtin_type_compatible (types[2], desc->op3)))

57049

+ || rs6000_builtin_type_compatible (types[2], desc->op3))

57050

+ && rs6000_builtin_decls[desc->overloaded_code] != NULL_TREE)

57051

return altivec_build_resolved_builtin (args, n, desc);

57052

57053

bad:

57054

Index: gcc/config/rs6000/rs6000.opt

57055

===================================================================

57056

--- a/src/gcc/config/rs6000/rs6000.opt (.../tags/gcc_4_8_2_release)

57057

+++ b/src/gcc/config/rs6000/rs6000.opt (.../branches/gcc-4_8-branch)

57058

@@ -1,6 +1,6 @@

57059

; Options for the rs6000 port of the compiler

57060

;

57061

57062

57063

; Contributed by Aldy Hernandez <aldy@quesejoda.com>.

57064

;

57065

; This file is part of GCC.

57066

@@ -137,6 +137,14 @@

57067

Target Report Mask(ALTIVEC) Var(rs6000_isa_flags)

57068

Use AltiVec instructions

57069

57070

+maltivec=le

57071

+Target Report RejectNegative Var(rs6000_altivec_element_order, 1) Save

57072

+Generate Altivec instructions using little-endian element order

57073

+

57074

+maltivec=be

57075

+Target Report RejectNegative Var(rs6000_altivec_element_order, 2)

57076

+Generate Altivec instructions using big-endian element order

57077

+

57078

mhard-dfp

57079

Target Report Mask(DFP) Var(rs6000_isa_flags)

57080

Use decimal floating point instructions

57081

@@ -181,13 +189,16 @@

57082

Target Report Mask(VSX) Var(rs6000_isa_flags)

57083

Use vector/scalar (VSX) instructions

57084

57085

+mvsx-scalar-float

57086

+Target Undocumented Report Var(TARGET_VSX_SCALAR_FLOAT) Init(1)

57087

+; If -mpower8-vector, use VSX arithmetic instructions for SFmode (on by default)

57088

+

57089

mvsx-scalar-double

57090

-Target Undocumented Report Var(TARGET_VSX_SCALAR_DOUBLE) Init(-1)

57091

-; If -mvsx, use VSX arithmetic instructions for scalar double (on by default)

57092

+Target Undocumented Report Var(TARGET_VSX_SCALAR_DOUBLE) Init(1)

57093

+; If -mvsx, use VSX arithmetic instructions for DFmode (on by default)

57094

57095

mvsx-scalar-memory

57096

-Target Undocumented Report Var(TARGET_VSX_SCALAR_MEMORY)

57097

-; If -mvsx, use VSX scalar memory reference instructions for scalar double (off by default)

57098

+Target Undocumented Report Alias(mupper-regs-df)

57099

57100

mvsx-align-128

57101

Target Undocumented Report Var(TARGET_VSX_ALIGN_128)

57102

@@ -363,6 +374,14 @@

57103

Target RejectNegative Var(rs6000_spe_abi, 0)

57104

Do not use the SPE ABI extensions

57105

57106

+mabi=elfv1

57107

+Target RejectNegative Var(rs6000_elf_abi, 1) Save

57108

+Use the ELFv1 ABI

57109

+

57110

+mabi=elfv2

57111

+Target RejectNegative Var(rs6000_elf_abi, 2)

57112

+Use the ELFv2 ABI

57113

+

57114

; These are here for testing during development only, do not document

57115

; in the manual please.

57116

57117

@@ -443,6 +462,10 @@

57118

Target RejectNegative Joined UInteger Var(rs6000_long_double_type_size) Save

57119

-mlong-double-<n> Specify size of long double (64 or 128 bits)

57120

57121

+mlra

57122

+Target Report Var(rs6000_lra_flag) Init(0) Save

57123

+Use LRA instead of reload

57124

+

57125

msched-costly-dep=

57126

Target RejectNegative Joined Var(rs6000_sched_costly_dep_str)

57127

Determine which dependences between insns are considered costly

57128

@@ -514,3 +537,51 @@

57129

msave-toc-indirect

57130

Target Report Var(TARGET_SAVE_TOC_INDIRECT) Save

57131

Control whether we save the TOC in the prologue for indirect calls or generate the save inline

57132

+

57133

+mvsx-timode

57134

+Target Undocumented Mask(VSX_TIMODE) Var(rs6000_isa_flags)

57135

+Allow 128-bit integers in VSX registers

57136

+

57137

+mpower8-fusion

57138

+Target Report Mask(P8_FUSION) Var(rs6000_isa_flags)

57139

+Fuse certain integer operations together for better performance on power8

57140

+

57141

+mpower8-fusion-sign

57142

+Target Undocumented Mask(P8_FUSION_SIGN) Var(rs6000_isa_flags)

57143

+Allow sign extension in fusion operations

57144

+

57145

+mpower8-vector

57146

+Target Report Mask(P8_VECTOR) Var(rs6000_isa_flags)

57147

+Use/do not use vector and scalar instructions added in ISA 2.07.

57148

+

57149

+mcrypto

57150

+Target Report Mask(CRYPTO) Var(rs6000_isa_flags)

57151

+Use ISA 2.07 crypto instructions

57152

+

57153

+mdirect-move

57154

+Target Report Mask(DIRECT_MOVE) Var(rs6000_isa_flags)

57155

+Use ISA 2.07 direct move between GPR & VSX register instructions

57156

+

57157

+mhtm

57158

+Target Report Mask(HTM) Var(rs6000_isa_flags)

57159

+Use ISA 2.07 transactional memory (HTM) instructions

57160

+

57161

+mquad-memory

57162

+Target Report Mask(QUAD_MEMORY) Var(rs6000_isa_flags)

57163

+Generate the quad word memory instructions (lq/stq).

57164

+

57165

+mquad-memory-atomic

57166

+Target Report Mask(QUAD_MEMORY_ATOMIC) Var(rs6000_isa_flags)

57167

+Generate the quad word memory atomic instructions (lqarx/stqcx).

57168

+

57169

+mcompat-align-parm

57170

+Target Report Var(rs6000_compat_align_parm) Init(1) Save

57171

+Generate aggregate parameter passing code with at most 64-bit alignment.

57172

+

57173

+mupper-regs-df

57174

+Target Undocumented Mask(UPPER_REGS_DF) Var(rs6000_isa_flags)

57175

+Allow double variables in upper registers with -mcpu=power7 or -mvsx

57176

+

57177

+mupper-regs-sf

57178

+Target Undocumented Mask(UPPER_REGS_SF) Var(rs6000_isa_flags)

57179

+Allow float variables in upper registers with -mcpu=power8 or -mp8-vector

57180

Index: gcc/config/rs6000/linux64.h

57181

===================================================================

57182

--- a/src/gcc/config/rs6000/linux64.h (.../tags/gcc_4_8_2_release)

57183

+++ b/src/gcc/config/rs6000/linux64.h (.../branches/gcc-4_8-branch)

57184

@@ -25,9 +25,6 @@

57185

57186

#ifndef RS6000_BI_ARCH

57187

57188

-#undef DEFAULT_ABI

57189

-#define DEFAULT_ABI ABI_AIX

57190

-

57191

#undef TARGET_64BIT

57192

#define TARGET_64BIT 1

57193

57194

@@ -74,7 +71,11 @@

57195

#undef PROCESSOR_DEFAULT

57196

#define PROCESSOR_DEFAULT PROCESSOR_POWER7

57197

#undef PROCESSOR_DEFAULT64

57198

+#ifdef LINUX64_DEFAULT_ABI_ELFv2

57199

+#define PROCESSOR_DEFAULT64 PROCESSOR_POWER8

57200

+#else

57201

#define PROCESSOR_DEFAULT64 PROCESSOR_POWER7

57202

+#endif

57203

57204

/* We don't need to generate entries in .fixup, except when

57205

-mrelocatable or -mrelocatable-lib is given. */

57206

@@ -88,6 +89,12 @@

57207

#define INVALID_64BIT "-m%s not supported in this configuration"

57208

#define INVALID_32BIT INVALID_64BIT

57209

57210

+#ifdef LINUX64_DEFAULT_ABI_ELFv2

57211

+#define ELFv2_ABI_CHECK (rs6000_elf_abi != 1)

57212

+#else

57213

+#define ELFv2_ABI_CHECK (rs6000_elf_abi == 2)

57214

+#endif

57215

+

57216

#undef SUBSUBTARGET_OVERRIDE_OPTIONS

57217

#define SUBSUBTARGET_OVERRIDE_OPTIONS \

57218

do \

57219

@@ -102,6 +109,12 @@

57220

error (INVALID_64BIT, "call"); \

57221

} \

57222

dot_symbols = !strcmp (rs6000_abi_name, "aixdesc"); \

57223

+ if (ELFv2_ABI_CHECK) \

57224

+ { \

57225

+ rs6000_current_abi = ABI_ELFv2; \

57226

+ if (dot_symbols) \

57227

+ error ("-mcall-aixdesc incompatible with -mabi=elfv2"); \

57228

+ } \

57229

if (rs6000_isa_flags & OPTION_MASK_RELOCATABLE) \

57230

{ \

57231

rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE; \

57232

@@ -136,8 +149,11 @@

57233

SET_CMODEL (CMODEL_MEDIUM); \

57234

if (rs6000_current_cmodel != CMODEL_SMALL) \

57235

{ \

57236

- TARGET_NO_FP_IN_TOC = 0; \

57237

- TARGET_NO_SUM_IN_TOC = 0; \

57238

+ if (!global_options_set.x_TARGET_NO_FP_IN_TOC) \

57239

+ TARGET_NO_FP_IN_TOC \

57240

+ = rs6000_current_cmodel == CMODEL_MEDIUM; \

57241

+ if (!global_options_set.x_TARGET_NO_SUM_IN_TOC) \

57242

+ TARGET_NO_SUM_IN_TOC = 0; \

57243

} \

57244

} \

57245

} \

57246

@@ -351,7 +367,11 @@

57247

#define LINK_OS_DEFAULT_SPEC "%(link_os_linux)"

57248

57249

#define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1"

57250

-#define GLIBC_DYNAMIC_LINKER64 "/lib64/ld64.so.1"

57251

+#ifdef LINUX64_DEFAULT_ABI_ELFv2

57252

+#define GLIBC_DYNAMIC_LINKER64 "%{mabi=elfv1:/lib64/ld64.so.1;:/lib64/ld64.so.2}"

57253

+#else

57254

+#define GLIBC_DYNAMIC_LINKER64 "%{mabi=elfv2:/lib64/ld64.so.2;:/lib64/ld64.so.1}"

57255

+#endif

57256

#define UCLIBC_DYNAMIC_LINKER32 "/lib/ld-uClibc.so.0"

57257

#define UCLIBC_DYNAMIC_LINKER64 "/lib/ld64-uClibc.so.0"

57258

#if DEFAULT_LIBC == LIBC_UCLIBC

57259

Index: gcc/config/rs6000/darwin.h

57260

===================================================================

57261

--- a/src/gcc/config/rs6000/darwin.h (.../tags/gcc_4_8_2_release)

57262

+++ b/src/gcc/config/rs6000/darwin.h (.../branches/gcc-4_8-branch)

57263

@@ -205,7 +205,8 @@

57264

"v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", \

57265

"vrsave", "vscr", \

57266

"spe_acc", "spefscr", \

57267

- "sfp" \

57268

+ "sfp", \

57269

+ "tfhar", "tfiar", "texasr" \

57270

}

57271

57272

/* This outputs NAME to FILE. */

57273

Index: gcc/config/rs6000/rs6000.c

57274

===================================================================

57275

--- a/src/gcc/config/rs6000/rs6000.c (.../tags/gcc_4_8_2_release)

57276

+++ b/src/gcc/config/rs6000/rs6000.c (.../branches/gcc-4_8-branch)

57277

@@ -1,5 +1,5 @@

57278

/* Subroutines used for code generation on IBM RS/6000.

57279

57280

57281

Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)

57282

57283

This file is part of GCC.

57284

@@ -56,6 +56,7 @@

57285

#include "intl.h"

57286

#include "params.h"

57287

#include "tm-constrs.h"

57288

+#include "ira.h"

57289

#include "opts.h"

57290

#include "tree-vectorizer.h"

57291

#include "dumpfile.h"

57292

@@ -96,6 +97,7 @@

57293

int spe_gp_save_offset; /* offset to save spe 64-bit gprs */

57294

int varargs_save_offset; /* offset to save the varargs registers */

57295

int ehrd_offset; /* offset to EH return data */

57296

+ int ehcr_offset; /* offset to EH CR field data */

57297

int reg_size; /* register size (4 or 8) */

57298

HOST_WIDE_INT vars_size; /* variable save area size */

57299

int parm_size; /* outgoing parameter size */

57300

@@ -139,6 +141,8 @@

57301

64-bits wide and is allocated early enough so that the offset

57302

does not overflow the 16-bit load/store offset field. */

57303

rtx sdmode_stack_slot;

57304

+ /* Flag if r2 setup is needed with ELFv2 ABI. */

57305

+ bool r2_setup_needed;

57306

} machine_function;

57307

57308

/* Support targetm.vectorize.builtin_mask_for_load. */

57309

@@ -189,9 +193,6 @@

57310

/* Map register number to register class. */

57311

enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER];

57312

57313

-/* Reload functions based on the type and the vector unit. */

57314

-static enum insn_code rs6000_vector_reload[NUM_MACHINE_MODES][2];

57315

-

57316

static int dbg_cost_ctrl;

57317

57318

/* Built in types. */

57319

@@ -289,6 +290,105 @@

57320

don't link in rs6000-c.c, so we can't call it directly. */

57321

void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT, HOST_WIDE_INT);

57322

57323

+/* Simplfy register classes into simpler classifications. We assume

57324

+ GPR_REG_TYPE - FPR_REG_TYPE are ordered so that we can use a simple range

57325

+ check for standard register classes (gpr/floating/altivec/vsx) and

57326

+ floating/vector classes (float/altivec/vsx). */

57327

+

57328

+enum rs6000_reg_type {

57329

+ NO_REG_TYPE,

57330

+ PSEUDO_REG_TYPE,

57331

+ GPR_REG_TYPE,

57332

+ VSX_REG_TYPE,

57333

+ ALTIVEC_REG_TYPE,

57334

+ FPR_REG_TYPE,

57335

+ SPR_REG_TYPE,

57336

+ CR_REG_TYPE,

57337

+ SPE_ACC_TYPE,

57338

+ SPEFSCR_REG_TYPE

57339

+};

57340

+

57341

+/* Map register class to register type. */

57342

+static enum rs6000_reg_type reg_class_to_reg_type[N_REG_CLASSES];

57343

+

57344

+/* First/last register type for the 'normal' register types (i.e. general

57345

+ purpose, floating point, altivec, and VSX registers). */

57346

+#define IS_STD_REG_TYPE(RTYPE) IN_RANGE(RTYPE, GPR_REG_TYPE, FPR_REG_TYPE)

57347

+

57348

+#define IS_FP_VECT_REG_TYPE(RTYPE) IN_RANGE(RTYPE, VSX_REG_TYPE, FPR_REG_TYPE)

57349

+

57350

+

57351

+/* Register classes we care about in secondary reload or go if legitimate

57352

+ address. We only need to worry about GPR, FPR, and Altivec registers here,

57353

+ along an ANY field that is the OR of the 3 register classes. */

57354

+

57355

+enum rs6000_reload_reg_type {

57356

+ RELOAD_REG_GPR, /* General purpose registers. */

57357

+ RELOAD_REG_FPR, /* Traditional floating point regs. */

57358

+ RELOAD_REG_VMX, /* Altivec (VMX) registers. */

57359

+ RELOAD_REG_ANY, /* OR of GPR, FPR, Altivec masks. */

57360

+ N_RELOAD_REG

57361

+};

57362

+

57363

+/* For setting up register classes, loop through the 3 register classes mapping

57364

+ into real registers, and skip the ANY class, which is just an OR of the

57365

+ bits. */

57366

+#define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR

57367

+#define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX

57368

+

57369

+/* Map reload register type to a register in the register class. */

57370

+struct reload_reg_map_type {

57371

+ const char *name; /* Register class name. */

57372

+ int reg; /* Register in the register class. */

57373

+};

57374

+

57375

+static const struct reload_reg_map_type reload_reg_map[N_RELOAD_REG] = {

57376

+ { "Gpr", FIRST_GPR_REGNO }, /* RELOAD_REG_GPR. */

57377

+ { "Fpr", FIRST_FPR_REGNO }, /* RELOAD_REG_FPR. */

57378

+ { "VMX", FIRST_ALTIVEC_REGNO }, /* RELOAD_REG_VMX. */

57379

+ { "Any", -1 }, /* RELOAD_REG_ANY. */

57380

+};

57381

+

57382

+/* Mask bits for each register class, indexed per mode. Historically the

57383

+ compiler has been more restrictive which types can do PRE_MODIFY instead of

57384

+ PRE_INC and PRE_DEC, so keep track of sepaate bits for these two. */

57385

+typedef unsigned char addr_mask_type;

57386

+

57387

+#define RELOAD_REG_VALID 0x01 /* Mode valid in register.. */

57388

+#define RELOAD_REG_MULTIPLE 0x02 /* Mode takes multiple registers. */

57389

+#define RELOAD_REG_INDEXED 0x04 /* Reg+reg addressing. */

57390

+#define RELOAD_REG_OFFSET 0x08 /* Reg+offset addressing. */

57391

+#define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */

57392

+#define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */

57393

+

57394

+/* Register type masks based on the type, of valid addressing modes. */

57395

+struct rs6000_reg_addr {

57396

+ enum insn_code reload_load; /* INSN to reload for loading. */

57397

+ enum insn_code reload_store; /* INSN to reload for storing. */

57398

+ enum insn_code reload_fpr_gpr; /* INSN to move from FPR to GPR. */

57399

+ enum insn_code reload_gpr_vsx; /* INSN to move from GPR to VSX. */

57400

+ enum insn_code reload_vsx_gpr; /* INSN to move from VSX to GPR. */

57401

+ addr_mask_type addr_mask[(int)N_RELOAD_REG]; /* Valid address masks. */

57402

+};

57403

+

57404

+static struct rs6000_reg_addr reg_addr[NUM_MACHINE_MODES];

57405

+

57406

+/* Helper function to say whether a mode supports PRE_INC or PRE_DEC. */

57407

+static inline bool

57408

+mode_supports_pre_incdec_p (enum machine_mode mode)

57409

+{

57410

+ return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_INCDEC)

57411

+ != 0);

57412

+}

57413

+

57414

+/* Helper function to say whether a mode supports PRE_MODIFY. */

57415

+static inline bool

57416

+mode_supports_pre_modify_p (enum machine_mode mode)

57417

+{

57418

+ return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY)

57419

+ != 0);

57420

+}

57421

+

57422

57423

/* Target cpu costs. */

57424

57425

@@ -828,6 +928,25 @@

57426

12, /* prefetch streams */

57427

};

57428

57429

+/* Instruction costs on POWER8 processors. */

57430

+static const

57431

+struct processor_costs power8_cost = {

57432

+ COSTS_N_INSNS (3), /* mulsi */

57433

+ COSTS_N_INSNS (3), /* mulsi_const */

57434

+ COSTS_N_INSNS (3), /* mulsi_const9 */

57435

+ COSTS_N_INSNS (3), /* muldi */

57436

+ COSTS_N_INSNS (19), /* divsi */

57437

+ COSTS_N_INSNS (35), /* divdi */

57438

+ COSTS_N_INSNS (3), /* fp */

57439

+ COSTS_N_INSNS (3), /* dmul */

57440

+ COSTS_N_INSNS (14), /* sdiv */

57441

+ COSTS_N_INSNS (17), /* ddiv */

57442

+ 128, /* cache line size */

57443

+ 32, /* l1 cache */

57444

+ 256, /* l2 cache */

57445

+ 12, /* prefetch streams */

57446

+};

57447

+

57448

/* Instruction costs on POWER A2 processors. */

57449

static const

57450

struct processor_costs ppca2_cost = {

57451

@@ -855,6 +974,7 @@

57452

#undef RS6000_BUILTIN_A

57453

#undef RS6000_BUILTIN_D

57454

#undef RS6000_BUILTIN_E

57455

+#undef RS6000_BUILTIN_H

57456

#undef RS6000_BUILTIN_P

57457

#undef RS6000_BUILTIN_Q

57458

#undef RS6000_BUILTIN_S

57459

@@ -878,6 +998,9 @@

57460

#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \

57461

{ NAME, ICODE, MASK, ATTR },

57462

57463

+#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \

57464

+ { NAME, ICODE, MASK, ATTR },

57465

+

57466

#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \

57467

{ NAME, ICODE, MASK, ATTR },

57468

57469

@@ -908,6 +1031,7 @@

57470

#undef RS6000_BUILTIN_A

57471

#undef RS6000_BUILTIN_D

57472

#undef RS6000_BUILTIN_E

57473

+#undef RS6000_BUILTIN_H

57474

#undef RS6000_BUILTIN_P

57475

#undef RS6000_BUILTIN_Q

57476

#undef RS6000_BUILTIN_S

57477

@@ -948,6 +1072,7 @@

57478

static void paired_init_builtins (void);

57479

static rtx paired_expand_predicate_builtin (enum insn_code, tree, rtx);

57480

static void spe_init_builtins (void);

57481

+static void htm_init_builtins (void);

57482

static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);

57483

static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);

57484

static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);

57485

@@ -1020,6 +1145,13 @@

57486

static void rs6000_print_builtin_options (FILE *, int, const char *,

57487

HOST_WIDE_INT);

57488

57489

+static enum rs6000_reg_type register_to_reg_type (rtx, bool *);

57490

+static bool rs6000_secondary_reload_move (enum rs6000_reg_type,

57491

+ enum rs6000_reg_type,

57492

+ enum machine_mode,

57493

+ secondary_reload_info *,

57494

+ bool);

57495

+

57496

/* Hash table stuff for keeping track of TOC entries. */

57497

57498

struct GTY(()) toc_hash_struct

57499

@@ -1068,7 +1200,9 @@

57500

/* SPE registers. */

57501

"spe_acc", "spefscr",

57502

/* Soft frame pointer. */

57503

- "sfp"

57504

+ "sfp",

57505

+ /* HTM SPR registers. */

57506

+ "tfhar", "tfiar", "texasr"

57507

};

57508

57509

#ifdef TARGET_REGNAMES

57510

@@ -1094,7 +1228,9 @@

57511

/* SPE registers. */

57512

"spe_acc", "spefscr",

57513

/* Soft frame pointer. */

57514

- "sfp"

57515

+ "sfp",

57516

+ /* HTM SPR registers. */

57517

+ "tfhar", "tfiar", "texasr"

57518

};

57519

#endif

57520

57521

@@ -1316,6 +1452,9 @@

57522

#undef TARGET_RETURN_IN_MEMORY

57523

#define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory

57524

57525

+#undef TARGET_RETURN_IN_MSB

57526

+#define TARGET_RETURN_IN_MSB rs6000_return_in_msb

57527

+

57528

#undef TARGET_SETUP_INCOMING_VARARGS

57529

#define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs

57530

57531

@@ -1425,6 +1564,9 @@

57532

#undef TARGET_MODE_DEPENDENT_ADDRESS_P

57533

#define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p

57534

57535

+#undef TARGET_LRA_P

57536

+#define TARGET_LRA_P rs6000_lra_p

57537

+

57538

#undef TARGET_CAN_ELIMINATE

57539

#define TARGET_CAN_ELIMINATE rs6000_can_eliminate

57540

57541

@@ -1513,8 +1655,9 @@

57542

{

57543

unsigned HOST_WIDE_INT reg_size;

57544

57545

+ /* TF/TD modes are special in that they always take 2 registers. */

57546

if (FP_REGNO_P (regno))

57547

- reg_size = (VECTOR_MEM_VSX_P (mode)

57548

+ reg_size = ((VECTOR_MEM_VSX_P (mode) && mode != TDmode && mode != TFmode)

57549

? UNITS_PER_VSX_WORD

57550

: UNITS_PER_FP_WORD);

57551

57552

@@ -1546,16 +1689,39 @@

57553

{

57554

int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1;

57555

57556

+ /* PTImode can only go in GPRs. Quad word memory operations require even/odd

57557

+ register combinations, and use PTImode where we need to deal with quad

57558

+ word memory operations. Don't allow quad words in the argument or frame

57559

+ pointer registers, just registers 0..31. */

57560

+ if (mode == PTImode)

57561

+ return (IN_RANGE (regno, FIRST_GPR_REGNO, LAST_GPR_REGNO)

57562

+ && IN_RANGE (last_regno, FIRST_GPR_REGNO, LAST_GPR_REGNO)

57563

+ && ((regno & 1) == 0));

57564

+

57565

/* VSX registers that overlap the FPR registers are larger than for non-VSX

57566

implementations. Don't allow an item to be split between a FP register

57567

- and an Altivec register. */

57568

- if (VECTOR_MEM_VSX_P (mode))

57569

+ and an Altivec register. Allow TImode in all VSX registers if the user

57570

+ asked for it. */

57571

+ if (TARGET_VSX && VSX_REGNO_P (regno)

57572

+ && (VECTOR_MEM_VSX_P (mode)

57573

+ || (TARGET_VSX_SCALAR_FLOAT && mode == SFmode)

57574

+ || (TARGET_VSX_SCALAR_DOUBLE && (mode == DFmode || mode == DImode))

57575

+ || (TARGET_VSX_TIMODE && mode == TImode)

57576

+ || (TARGET_VADDUQM && mode == V1TImode)))

57577

{

57578

if (FP_REGNO_P (regno))

57579

return FP_REGNO_P (last_regno);

57580

57581

if (ALTIVEC_REGNO_P (regno))

57582

- return ALTIVEC_REGNO_P (last_regno);

57583

+ {

57584

+ if (mode == SFmode && !TARGET_UPPER_REGS_SF)

57585

+ return 0;

57586

+

57587

+ if ((mode == DFmode || mode == DImode) && !TARGET_UPPER_REGS_DF)

57588

+ return 0;

57589

+

57590

+ return ALTIVEC_REGNO_P (last_regno);

57591

+ }

57592

}

57593

57594

/* The GPRs can hold any mode, but values bigger than one register

57595

@@ -1564,8 +1730,7 @@

57596

return INT_REGNO_P (last_regno);

57597

57598

/* The float registers (except for VSX vector modes) can only hold floating

57599

- modes and DImode. This excludes the 32-bit decimal float mode for

57600

- now. */

57601

+ modes and DImode. */

57602

if (FP_REGNO_P (regno))

57603

{

57604

if (SCALAR_FLOAT_MODE_P (mode)

57605

@@ -1593,15 +1758,15 @@

57606

57607

/* AltiVec only in AldyVec registers. */

57608

if (ALTIVEC_REGNO_P (regno))

57609

- return VECTOR_MEM_ALTIVEC_OR_VSX_P (mode);

57610

+ return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)

57611

+ || mode == V1TImode);

57612

57613

/* ...but GPRs can hold SIMD data on the SPE in one register. */

57614

if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))

57615

return 1;

57616

57617

- /* We cannot put TImode anywhere except general register and it must be able

57618

- to fit within the register set. In the future, allow TImode in the

57619

- Altivec or VSX registers. */

57620

+ /* We cannot put non-VSX TImode or PTImode anywhere except general register

57621

+ and it must be able to fit within the register set. */

57622

57623

return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;

57624

}

57625

@@ -1674,10 +1839,77 @@

57626

comma = "";

57627

}

57628

57629

+ len += fprintf (stderr, "%sreg-class = %s", comma,

57630

+ reg_class_names[(int)rs6000_regno_regclass[r]]);

57631

+ comma = ", ";

57632

+

57633

+ if (len > 70)

57634

+ {

57635

+ fprintf (stderr, ",\n\t");

57636

+ comma = "";

57637

+ }

57638

+

57639

fprintf (stderr, "%sregno = %d\n", comma, r);

57640

}

57641

}

57642

57643

+static const char *

57644

+rs6000_debug_vector_unit (enum rs6000_vector v)

57645

+{

57646

+ const char *ret;

57647

+

57648

+ switch (v)

57649

+ {

57650

+ case VECTOR_NONE: ret = "none"; break;

57651

+ case VECTOR_ALTIVEC: ret = "altivec"; break;

57652

+ case VECTOR_VSX: ret = "vsx"; break;

57653

+ case VECTOR_P8_VECTOR: ret = "p8_vector"; break;

57654

+ case VECTOR_PAIRED: ret = "paired"; break;

57655

+ case VECTOR_SPE: ret = "spe"; break;

57656

+ case VECTOR_OTHER: ret = "other"; break;

57657

+ default: ret = "unknown"; break;

57658

+ }

57659

+

57660

+ return ret;

57661

+}

57662

+

57663

+/* Print the address masks in a human readble fashion. */

57664

+DEBUG_FUNCTION void

57665

+rs6000_debug_print_mode (ssize_t m)

57666

+{

57667

+ ssize_t rc;

57668

+

57669

+ fprintf (stderr, "Mode: %-5s", GET_MODE_NAME (m));

57670

+ for (rc = 0; rc < N_RELOAD_REG; rc++)

57671

+ {

57672

+ addr_mask_type mask = reg_addr[m].addr_mask[rc];

57673

+ fprintf (stderr,

57674

+ " %s: %c%c%c%c%c%c",

57675

+ reload_reg_map[rc].name,

57676

+ (mask & RELOAD_REG_VALID) != 0 ? 'v' : ' ',

57677

+ (mask & RELOAD_REG_MULTIPLE) != 0 ? 'm' : ' ',

57678

+ (mask & RELOAD_REG_INDEXED) != 0 ? 'i' : ' ',

57679

+ (mask & RELOAD_REG_OFFSET) != 0 ? 'o' : ' ',

57680

+ (mask & RELOAD_REG_PRE_INCDEC) != 0 ? '+' : ' ',

57681

+ (mask & RELOAD_REG_PRE_MODIFY) != 0 ? '+' : ' ');

57682

+ }

57683

+

57684

+ if (rs6000_vector_unit[m] != VECTOR_NONE

57685

+ || rs6000_vector_mem[m] != VECTOR_NONE

57686

+ || (reg_addr[m].reload_store != CODE_FOR_nothing)

57687

+ || (reg_addr[m].reload_load != CODE_FOR_nothing))

57688

+ {

57689

+ fprintf (stderr,

57690

+ " Vector-arith=%-10s Vector-mem=%-10s Reload=%c%c",

57691

+ rs6000_debug_vector_unit (rs6000_vector_unit[m]),

57692

+ rs6000_debug_vector_unit (rs6000_vector_mem[m]),

57693

+ (reg_addr[m].reload_store != CODE_FOR_nothing) ? 's' : '*',

57694

+ (reg_addr[m].reload_load != CODE_FOR_nothing) ? 'l' : '*');

57695

+ }

57696

+

57697

+ fputs ("\n", stderr);

57698

+}

57699

+

57700

#define DEBUG_FMT_ID "%-32s= "

57701

#define DEBUG_FMT_D DEBUG_FMT_ID "%d\n"

57702

#define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: "

57703

@@ -1690,6 +1922,7 @@

57704

static const char *const tf[2] = { "false", "true" };

57705

const char *nl = (const char *)0;

57706

int m;

57707

+ size_t m1, m2, v;

57708

char costly_num[20];

57709

char nop_num[20];

57710

char flags_buffer[40];

57711

@@ -1700,20 +1933,69 @@

57712

const char *cmodel_str;

57713

struct cl_target_option cl_opts;

57714

57715

- /* Map enum rs6000_vector to string. */

57716

- static const char *rs6000_debug_vector_unit[] = {

57717

- "none",

57718

- "altivec",

57719

- "vsx",

57720

- "paired",

57721

- "spe",

57722

- "other"

57723

+ /* Modes we want tieable information on. */

57724

+ static const enum machine_mode print_tieable_modes[] = {

57725

+ QImode,

57726

+ HImode,

57727

+ SImode,

57728

+ DImode,

57729

+ TImode,

57730

+ PTImode,

57731

+ SFmode,

57732

+ DFmode,

57733

+ TFmode,

57734

+ SDmode,

57735

+ DDmode,

57736

+ TDmode,

57737

+ V8QImode,

57738

+ V4HImode,

57739

+ V2SImode,

57740

+ V16QImode,

57741

+ V8HImode,

57742

+ V4SImode,

57743

+ V2DImode,

57744

+ V1TImode,

57745

+ V32QImode,

57746

+ V16HImode,

57747

+ V8SImode,

57748

+ V4DImode,

57749

+ V2TImode,

57750

+ V2SFmode,

57751

+ V4SFmode,

57752

+ V2DFmode,

57753

+ V8SFmode,

57754

+ V4DFmode,

57755

+ CCmode,

57756

+ CCUNSmode,

57757

+ CCEQmode,

57758

};

57759

57760

- fprintf (stderr, "Register information: (last virtual reg = %d)\n",

57761

- LAST_VIRTUAL_REGISTER);

57762

- rs6000_debug_reg_print (0, 31, "gr");

57763

- rs6000_debug_reg_print (32, 63, "fp");

57764

+ /* Virtual regs we are interested in. */

57765

+ const static struct {

57766

+ int regno; /* register number. */

57767

+ const char *name; /* register name. */

57768

+ } virtual_regs[] = {

57769

+ { STACK_POINTER_REGNUM, "stack pointer:" },

57770

+ { TOC_REGNUM, "toc: " },

57771

+ { STATIC_CHAIN_REGNUM, "static chain: " },

57772

+ { RS6000_PIC_OFFSET_TABLE_REGNUM, "pic offset: " },

57773

+ { HARD_FRAME_POINTER_REGNUM, "hard frame: " },

57774

+ { ARG_POINTER_REGNUM, "arg pointer: " },

57775

+ { FRAME_POINTER_REGNUM, "frame pointer:" },

57776

+ { FIRST_PSEUDO_REGISTER, "first pseudo: " },

57777

+ { FIRST_VIRTUAL_REGISTER, "first virtual:" },

57778

+ { VIRTUAL_INCOMING_ARGS_REGNUM, "incoming_args:" },

57779

+ { VIRTUAL_STACK_VARS_REGNUM, "stack_vars: " },

57780

+ { VIRTUAL_STACK_DYNAMIC_REGNUM, "stack_dynamic:" },

57781

+ { VIRTUAL_OUTGOING_ARGS_REGNUM, "outgoing_args:" },

57782

+ { VIRTUAL_CFA_REGNUM, "cfa (frame): " },

57783

+ { VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM, "stack boundry:" },

57784

+ { LAST_VIRTUAL_REGISTER, "last virtual: " },

57785

+ };

57786

+

57787

+ fputs ("\nHard register information:\n", stderr);

57788

+ rs6000_debug_reg_print (FIRST_GPR_REGNO, LAST_GPR_REGNO, "gr");

57789

+ rs6000_debug_reg_print (FIRST_FPR_REGNO, LAST_FPR_REGNO, "fp");

57790

rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO,

57791

LAST_ALTIVEC_REGNO,

57792

"vs");

57793

@@ -1726,6 +2008,10 @@

57794

rs6000_debug_reg_print (SPE_ACC_REGNO, SPE_ACC_REGNO, "spe_a");

57795

rs6000_debug_reg_print (SPEFSCR_REGNO, SPEFSCR_REGNO, "spe_f");

57796

57797

+ fputs ("\nVirtual/stack/frame registers:\n", stderr);

57798

+ for (v = 0; v < ARRAY_SIZE (virtual_regs); v++)

57799

+ fprintf (stderr, "%s regno = %3d\n", virtual_regs[v].name, virtual_regs[v].regno);

57800

+

57801

fprintf (stderr,

57802

"\n"

57803

"d reg_class = %s\n"

57804

@@ -1734,7 +2020,19 @@

57805

"wa reg_class = %s\n"

57806

"wd reg_class = %s\n"

57807

"wf reg_class = %s\n"

57808

- "ws reg_class = %s\n\n",

57809

+ "wg reg_class = %s\n"

57810

+ "wl reg_class = %s\n"

57811

+ "wm reg_class = %s\n"

57812

+ "wr reg_class = %s\n"

57813

+ "ws reg_class = %s\n"

57814

+ "wt reg_class = %s\n"

57815

+ "wu reg_class = %s\n"

57816

+ "wv reg_class = %s\n"

57817

+ "ww reg_class = %s\n"

57818

+ "wx reg_class = %s\n"

57819

+ "wy reg_class = %s\n"

57820

+ "wz reg_class = %s\n"

57821

+ "\n",

57822

reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_d]],

57823

reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_f]],

57824

reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_v]],

57825

@@ -1741,18 +2039,51 @@

57826

reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wa]],

57827

reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wd]],

57828

reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]],

57829

- reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ws]]);

57830

+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wg]],

57831

+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wl]],

57832

+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wm]],

57833

+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]],

57834

+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ws]],

57835

+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wt]],

57836

+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wu]],

57837

+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wv]],

57838

+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ww]],

57839

+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]],

57840

+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wy]],

57841

+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wz]]);

57842

57843

+ nl = "\n";

57844

for (m = 0; m < NUM_MACHINE_MODES; ++m)

57845

- if (rs6000_vector_unit[m] || rs6000_vector_mem[m])

57846

- {

57847

- nl = "\n";

57848

- fprintf (stderr, "Vector mode: %-5s arithmetic: %-8s move: %-8s\n",

57849

- GET_MODE_NAME (m),

57850

- rs6000_debug_vector_unit[ rs6000_vector_unit[m] ],

57851

- rs6000_debug_vector_unit[ rs6000_vector_mem[m] ]);

57852

- }

57853

+ rs6000_debug_print_mode (m);

57854

57855

+ fputs ("\n", stderr);

57856

+

57857

+ for (m1 = 0; m1 < ARRAY_SIZE (print_tieable_modes); m1++)

57858

+ {

57859

+ enum machine_mode mode1 = print_tieable_modes[m1];

57860

+ bool first_time = true;

57861

+

57862

+ nl = (const char *)0;

57863

+ for (m2 = 0; m2 < ARRAY_SIZE (print_tieable_modes); m2++)

57864

+ {

57865

+ enum machine_mode mode2 = print_tieable_modes[m2];

57866

+ if (mode1 != mode2 && MODES_TIEABLE_P (mode1, mode2))

57867

+ {

57868

+ if (first_time)

57869

+ {

57870

+ fprintf (stderr, "Tieable modes %s:", GET_MODE_NAME (mode1));

57871

+ nl = "\n";

57872

+ first_time = false;

57873

+ }

57874

+

57875

+ fprintf (stderr, " %s", GET_MODE_NAME (mode2));

57876

+ }

57877

+ }

57878

+

57879

+ if (!first_time)

57880

+ fputs ("\n", stderr);

57881

+ }

57882

+

57883

if (nl)

57884

fputs (nl, stderr);

57885

57886

@@ -1913,6 +2244,7 @@

57887

{

57888

case ABI_NONE: abi_str = "none"; break;

57889

case ABI_AIX: abi_str = "aix"; break;

57890

+ case ABI_ELFv2: abi_str = "ELFv2"; break;

57891

case ABI_V4: abi_str = "V4"; break;

57892

case ABI_DARWIN: abi_str = "darwin"; break;

57893

default: abi_str = "unknown"; break;

57894

@@ -1932,9 +2264,34 @@

57895

if (rs6000_float_gprs)

57896

fprintf (stderr, DEBUG_FMT_S, "float_gprs", "true");

57897

57898

+ fprintf (stderr, DEBUG_FMT_S, "fprs",

57899

+ (TARGET_FPRS ? "true" : "false"));

57900

+

57901

+ fprintf (stderr, DEBUG_FMT_S, "single_float",

57902

+ (TARGET_SINGLE_FLOAT ? "true" : "false"));

57903

+

57904

+ fprintf (stderr, DEBUG_FMT_S, "double_float",

57905

+ (TARGET_DOUBLE_FLOAT ? "true" : "false"));

57906

+

57907

+ fprintf (stderr, DEBUG_FMT_S, "soft_float",

57908

+ (TARGET_SOFT_FLOAT ? "true" : "false"));

57909

+

57910

+ fprintf (stderr, DEBUG_FMT_S, "e500_single",

57911

+ (TARGET_E500_SINGLE ? "true" : "false"));

57912

+

57913

+ fprintf (stderr, DEBUG_FMT_S, "e500_double",

57914

+ (TARGET_E500_DOUBLE ? "true" : "false"));

57915

+

57916

if (TARGET_LINK_STACK)

57917

fprintf (stderr, DEBUG_FMT_S, "link_stack", "true");

57918

57919

+ if (targetm.lra_p ())

57920

+ fprintf (stderr, DEBUG_FMT_S, "lra", "true");

57921

+

57922

+ if (TARGET_P8_FUSION)

57923

+ fprintf (stderr, DEBUG_FMT_S, "p8 fusion",

57924

+ (TARGET_P8_FUSION_SIGN) ? "zero+sign" : "zero");

57925

+

57926

fprintf (stderr, DEBUG_FMT_S, "plt-format",

57927

TARGET_SECURE_PLT ? "secure" : "bss");

57928

fprintf (stderr, DEBUG_FMT_S, "struct-return",

57929

@@ -1954,11 +2311,106 @@

57930

(int)RS6000_BUILTIN_COUNT);

57931

}

57932

57933

+

57934

+/* Update the addr mask bits in reg_addr to help secondary reload and go if

57935

+ legitimate address support to figure out the appropriate addressing to

57936

+ use. */

57937

+

57938

+static void

57939

+rs6000_setup_reg_addr_masks (void)

57940

+{

57941

+ ssize_t rc, reg, m, nregs;

57942

+ addr_mask_type any_addr_mask, addr_mask;

57943

+

57944

+ for (m = 0; m < NUM_MACHINE_MODES; ++m)

57945

+ {

57946

+ /* SDmode is special in that we want to access it only via REG+REG

57947

+ addressing on power7 and above, since we want to use the LFIWZX and

57948

+ STFIWZX instructions to load it. */

57949

+ bool indexed_only_p = (m == SDmode && TARGET_NO_SDMODE_STACK);

57950

+

57951

+ any_addr_mask = 0;

57952

+ for (rc = FIRST_RELOAD_REG_CLASS; rc <= LAST_RELOAD_REG_CLASS; rc++)

57953

+ {

57954

+ addr_mask = 0;

57955

+ reg = reload_reg_map[rc].reg;

57956

+

57957

+ /* Can mode values go in the GPR/FPR/Altivec registers? */

57958

+ if (reg >= 0 && rs6000_hard_regno_mode_ok_p[m][reg])

57959

+ {

57960

+ nregs = rs6000_hard_regno_nregs[m][reg];

57961

+ addr_mask |= RELOAD_REG_VALID;

57962

+

57963

+ /* Indicate if the mode takes more than 1 physical register. If

57964

+ it takes a single register, indicate it can do REG+REG

57965

+ addressing. */

57966

+ if (nregs > 1 || m == BLKmode)

57967

+ addr_mask |= RELOAD_REG_MULTIPLE;

57968

+ else

57969

+ addr_mask |= RELOAD_REG_INDEXED;

57970

+

57971

+ /* Figure out if we can do PRE_INC, PRE_DEC, or PRE_MODIFY

57972

+ addressing. Restrict addressing on SPE for 64-bit types

57973

+ because of the SUBREG hackery used to address 64-bit floats in

57974

+ '32-bit' GPRs. To simplify secondary reload, don't allow

57975

+ update forms on scalar floating point types that can go in the

57976

+ upper registers. */

57977

+

57978

+ if (TARGET_UPDATE

57979

+ && (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR)

57980

+ && GET_MODE_SIZE (m) <= 8

57981

+ && !VECTOR_MODE_P (m)

57982

+ && !COMPLEX_MODE_P (m)

57983

+ && !indexed_only_p

57984

+ && !(TARGET_E500_DOUBLE && GET_MODE_SIZE (m) == 8)

57985

+ && !(m == DFmode && TARGET_UPPER_REGS_DF)

57986

+ && !(m == SFmode && TARGET_UPPER_REGS_SF))

57987

+ {

57988

+ addr_mask |= RELOAD_REG_PRE_INCDEC;

57989

+

57990

+ /* PRE_MODIFY is more restricted than PRE_INC/PRE_DEC in that

57991

+ we don't allow PRE_MODIFY for some multi-register

57992

+ operations. */

57993

+ switch (m)

57994

+ {

57995

+ default:

57996

+ addr_mask |= RELOAD_REG_PRE_MODIFY;

57997

+ break;

57998

+

57999

+ case DImode:

58000

+ if (TARGET_POWERPC64)

58001

+ addr_mask |= RELOAD_REG_PRE_MODIFY;

58002

+ break;

58003

+

58004

+ case DFmode:

58005

+ case DDmode:

58006

+ if (TARGET_DF_INSN)

58007

+ addr_mask |= RELOAD_REG_PRE_MODIFY;

58008

+ break;

58009

+ }

58010

+ }

58011

+ }

58012

+

58013

+ /* GPR and FPR registers can do REG+OFFSET addressing, except

58014

+ possibly for SDmode. */

58015

+ if ((addr_mask != 0) && !indexed_only_p

58016

+ && (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR))

58017

+ addr_mask |= RELOAD_REG_OFFSET;

58018

+

58019

+ reg_addr[m].addr_mask[rc] = addr_mask;

58020

+ any_addr_mask |= addr_mask;

58021

+ }

58022

+

58023

+ reg_addr[m].addr_mask[RELOAD_REG_ANY] = any_addr_mask;

58024

+ }

58025

+}

58026

+

58027

+

58028

/* Initialize the various global tables that are based on register size. */

58029

static void

58030

rs6000_init_hard_regno_mode_ok (bool global_init_p)

58031

{

58032

- int r, m, c;

58033

+ ssize_t r, m, c;

58034

int align64;

58035

int align32;

58036

58037

@@ -1987,21 +2439,55 @@

58038

rs6000_regno_regclass[VSCR_REGNO] = VRSAVE_REGS;

58039

rs6000_regno_regclass[SPE_ACC_REGNO] = SPE_ACC_REGS;

58040

rs6000_regno_regclass[SPEFSCR_REGNO] = SPEFSCR_REGS;

58041

+ rs6000_regno_regclass[TFHAR_REGNO] = SPR_REGS;

58042

+ rs6000_regno_regclass[TFIAR_REGNO] = SPR_REGS;

58043

+ rs6000_regno_regclass[TEXASR_REGNO] = SPR_REGS;

58044

rs6000_regno_regclass[ARG_POINTER_REGNUM] = BASE_REGS;

58045

rs6000_regno_regclass[FRAME_POINTER_REGNUM] = BASE_REGS;

58046

58047

- /* Precalculate vector information, this must be set up before the

58048

- rs6000_hard_regno_nregs_internal below. */

58049

- for (m = 0; m < NUM_MACHINE_MODES; ++m)

58050

+ /* Precalculate register class to simpler reload register class. We don't

58051

+ need all of the register classes that are combinations of different

58052

+ classes, just the simple ones that have constraint letters. */

58053

+ for (c = 0; c < N_REG_CLASSES; c++)

58054

+ reg_class_to_reg_type[c] = NO_REG_TYPE;

58055

+

58056

+ reg_class_to_reg_type[(int)GENERAL_REGS] = GPR_REG_TYPE;

58057

+ reg_class_to_reg_type[(int)BASE_REGS] = GPR_REG_TYPE;

58058

+ reg_class_to_reg_type[(int)VSX_REGS] = VSX_REG_TYPE;

58059

+ reg_class_to_reg_type[(int)VRSAVE_REGS] = SPR_REG_TYPE;

58060

+ reg_class_to_reg_type[(int)VSCR_REGS] = SPR_REG_TYPE;

58061

+ reg_class_to_reg_type[(int)LINK_REGS] = SPR_REG_TYPE;

58062

+ reg_class_to_reg_type[(int)CTR_REGS] = SPR_REG_TYPE;

58063

+ reg_class_to_reg_type[(int)LINK_OR_CTR_REGS] = SPR_REG_TYPE;

58064

+ reg_class_to_reg_type[(int)CR_REGS] = CR_REG_TYPE;

58065

+ reg_class_to_reg_type[(int)CR0_REGS] = CR_REG_TYPE;

58066

+ reg_class_to_reg_type[(int)SPE_ACC_REGS] = SPE_ACC_TYPE;

58067

+ reg_class_to_reg_type[(int)SPEFSCR_REGS] = SPEFSCR_REG_TYPE;

58068

+

58069

+ if (TARGET_VSX)

58070

{

58071

- rs6000_vector_unit[m] = rs6000_vector_mem[m] = VECTOR_NONE;

58072

- rs6000_vector_reload[m][0] = CODE_FOR_nothing;

58073

- rs6000_vector_reload[m][1] = CODE_FOR_nothing;

58074

+ reg_class_to_reg_type[(int)FLOAT_REGS] = VSX_REG_TYPE;

58075

+ reg_class_to_reg_type[(int)ALTIVEC_REGS] = VSX_REG_TYPE;

58076

}

58077

+ else

58078

+ {

58079

+ reg_class_to_reg_type[(int)FLOAT_REGS] = FPR_REG_TYPE;

58080

+ reg_class_to_reg_type[(int)ALTIVEC_REGS] = ALTIVEC_REG_TYPE;

58081

+ }

58082

58083

- for (c = 0; c < (int)(int)RS6000_CONSTRAINT_MAX; c++)

58084

- rs6000_constraints[c] = NO_REGS;

58085

+ /* Precalculate the valid memory formats as well as the vector information,

58086

+ this must be set up before the rs6000_hard_regno_nregs_internal calls

58087

+ below. */

58088

+ gcc_assert ((int)VECTOR_NONE == 0);

58089

+ memset ((void *) &rs6000_vector_unit[0], '\0', sizeof (rs6000_vector_unit));

58090

+ memset ((void *) &rs6000_vector_mem[0], '\0', sizeof (rs6000_vector_unit));

58091

58092

+ gcc_assert ((int)CODE_FOR_nothing == 0);

58093

+ memset ((void *) &reg_addr[0], '\0', sizeof (reg_addr));

58094

+

58095

+ gcc_assert ((int)NO_REGS == 0);

58096

+ memset ((void *) &rs6000_constraints[0], '\0', sizeof (rs6000_constraints));

58097

+

58098

/* The VSX hardware allows native alignment for vectors, but control whether the compiler

58099

believes it can use native alignment or still uses 128-bit alignment. */

58100

if (TARGET_VSX && !TARGET_VSX_ALIGN_128)

58101

@@ -2062,13 +2548,19 @@

58102

}

58103

}

58104

58105

- /* V2DImode, only allow under VSX, which can do V2DI insert/splat/extract.

58106

- Altivec doesn't have 64-bit support. */

58107

+ /* V2DImode, full mode depends on ISA 2.07 vector mode. Allow under VSX to

58108

+ do insert/splat/extract. Altivec doesn't have 64-bit integer support. */

58109

if (TARGET_VSX)

58110

{

58111

rs6000_vector_mem[V2DImode] = VECTOR_VSX;

58112

- rs6000_vector_unit[V2DImode] = VECTOR_NONE;

58113

+ rs6000_vector_unit[V2DImode]

58114

+ = (TARGET_P8_VECTOR) ? VECTOR_P8_VECTOR : VECTOR_NONE;

58115

rs6000_vector_align[V2DImode] = align64;

58116

+

58117

+ rs6000_vector_mem[V1TImode] = VECTOR_VSX;

58118

+ rs6000_vector_unit[V1TImode]

58119

+ = (TARGET_P8_VECTOR) ? VECTOR_P8_VECTOR : VECTOR_NONE;

58120

+ rs6000_vector_align[V1TImode] = 128;

58121

}

58122

58123

/* DFmode, see if we want to use the VSX unit. */

58124

@@ -2076,14 +2568,48 @@

58125

{

58126

rs6000_vector_unit[DFmode] = VECTOR_VSX;

58127

rs6000_vector_mem[DFmode]

58128

- = (TARGET_VSX_SCALAR_MEMORY ? VECTOR_VSX : VECTOR_NONE);

58129

+ = (TARGET_UPPER_REGS_DF ? VECTOR_VSX : VECTOR_NONE);

58130

rs6000_vector_align[DFmode] = align64;

58131

}

58132

58133

+ /* Allow TImode in VSX register and set the VSX memory macros. */

58134

+ if (TARGET_VSX && TARGET_VSX_TIMODE)

58135

+ {

58136

+ rs6000_vector_mem[TImode] = VECTOR_VSX;

58137

+ rs6000_vector_align[TImode] = align64;

58138

+ }

58139

+

58140

/* TODO add SPE and paired floating point vector support. */

58141

58142

/* Register class constraints for the constraints that depend on compile

58143

- switches. */

58144

+ switches. When the VSX code was added, different constraints were added

58145

+ based on the type (DFmode, V2DFmode, V4SFmode). For the vector types, all

58146

+ of the VSX registers are used. The register classes for scalar floating

58147

+ point types is set, based on whether we allow that type into the upper

58148

+ (Altivec) registers. GCC has register classes to target the Altivec

58149

+ registers for load/store operations, to select using a VSX memory

58150

+ operation instead of the traditional floating point operation. The

58151

+ constraints are:

58152

+

58153

+ d - Register class to use with traditional DFmode instructions.

58154

+ f - Register class to use with traditional SFmode instructions.

58155

+ v - Altivec register.

58156

+ wa - Any VSX register.

58157

+ wd - Preferred register class for V2DFmode.

58158

+ wf - Preferred register class for V4SFmode.

58159

+ wg - Float register for power6x move insns.

58160

+ wl - Float register if we can do 32-bit signed int loads.

58161

+ wm - VSX register for ISA 2.07 direct move operations.

58162

+ wr - GPR if 64-bit mode is permitted.

58163

+ ws - Register class to do ISA 2.06 DF operations.

58164

+ wu - Altivec register for ISA 2.07 VSX SF/SI load/stores.

58165

+ wv - Altivec register for ISA 2.06 VSX DF/DI load/stores.

58166

+ wt - VSX register for TImode in VSX registers.

58167

+ ww - Register class to do SF conversions in with VSX operations.

58168

+ wx - Float register if we can do 32-bit int stores.

58169

+ wy - Register class to do ISA 2.07 SF operations.

58170

+ wz - Float register if we can do 32-bit unsigned int loads. */

58171

+

58172

if (TARGET_HARD_FLOAT && TARGET_FPRS)

58173

rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS;

58174

58175

@@ -2092,64 +2618,164 @@

58176

58177

if (TARGET_VSX)

58178

{

58179

- /* At present, we just use VSX_REGS, but we have different constraints

58180

- based on the use, in case we want to fine tune the default register

58181

- class used. wa = any VSX register, wf = register class to use for

58182

- V4SF, wd = register class to use for V2DF, and ws = register classs to

58183

- use for DF scalars. */

58184

rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS;

58185

+ rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS;

58186

rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS;

58187

- rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS;

58188

- rs6000_constraints[RS6000_CONSTRAINT_ws] = (TARGET_VSX_SCALAR_MEMORY

58189

- ? VSX_REGS

58190

- : FLOAT_REGS);

58191

+

58192

+ if (TARGET_VSX_TIMODE)

58193

+ rs6000_constraints[RS6000_CONSTRAINT_wt] = VSX_REGS;

58194

+

58195

+ if (TARGET_UPPER_REGS_DF)

58196

+ {

58197

+ rs6000_constraints[RS6000_CONSTRAINT_ws] = VSX_REGS;

58198

+ rs6000_constraints[RS6000_CONSTRAINT_wv] = ALTIVEC_REGS;

58199

+ }

58200

+ else

58201

+ rs6000_constraints[RS6000_CONSTRAINT_ws] = FLOAT_REGS;

58202

}

58203

58204

+ /* Add conditional constraints based on various options, to allow us to

58205

+ collapse multiple insn patterns. */

58206

if (TARGET_ALTIVEC)

58207

rs6000_constraints[RS6000_CONSTRAINT_v] = ALTIVEC_REGS;

58208

58209

- /* Set up the reload helper functions. */

58210

+ if (TARGET_MFPGPR)

58211

+ rs6000_constraints[RS6000_CONSTRAINT_wg] = FLOAT_REGS;

58212

+

58213

+ if (TARGET_LFIWAX)

58214

+ rs6000_constraints[RS6000_CONSTRAINT_wl] = FLOAT_REGS;

58215

+

58216

+ if (TARGET_DIRECT_MOVE)

58217

+ rs6000_constraints[RS6000_CONSTRAINT_wm] = VSX_REGS;

58218

+

58219

+ if (TARGET_POWERPC64)

58220

+ rs6000_constraints[RS6000_CONSTRAINT_wr] = GENERAL_REGS;

58221

+

58222

+ if (TARGET_P8_VECTOR && TARGET_UPPER_REGS_SF)

58223

+ {

58224

+ rs6000_constraints[RS6000_CONSTRAINT_wu] = ALTIVEC_REGS;

58225

+ rs6000_constraints[RS6000_CONSTRAINT_wy] = VSX_REGS;

58226

+ rs6000_constraints[RS6000_CONSTRAINT_ww] = VSX_REGS;

58227

+ }

58228

+ else if (TARGET_P8_VECTOR)

58229

+ {

58230

+ rs6000_constraints[RS6000_CONSTRAINT_wy] = FLOAT_REGS;

58231

+ rs6000_constraints[RS6000_CONSTRAINT_ww] = FLOAT_REGS;

58232

+ }

58233

+ else if (TARGET_VSX)

58234

+ rs6000_constraints[RS6000_CONSTRAINT_ww] = FLOAT_REGS;

58235

+

58236

+ if (TARGET_STFIWX)

58237

+ rs6000_constraints[RS6000_CONSTRAINT_wx] = FLOAT_REGS;

58238

+

58239

+ if (TARGET_LFIWZX)

58240

+ rs6000_constraints[RS6000_CONSTRAINT_wz] = FLOAT_REGS;

58241

+

58242

+ /* Set up the reload helper and direct move functions. */

58243

if (TARGET_VSX || TARGET_ALTIVEC)

58244

{

58245

if (TARGET_64BIT)

58246

{

58247

- rs6000_vector_reload[V16QImode][0] = CODE_FOR_reload_v16qi_di_store;

58248

- rs6000_vector_reload[V16QImode][1] = CODE_FOR_reload_v16qi_di_load;

58249

- rs6000_vector_reload[V8HImode][0] = CODE_FOR_reload_v8hi_di_store;

58250

- rs6000_vector_reload[V8HImode][1] = CODE_FOR_reload_v8hi_di_load;

58251

- rs6000_vector_reload[V4SImode][0] = CODE_FOR_reload_v4si_di_store;

58252

- rs6000_vector_reload[V4SImode][1] = CODE_FOR_reload_v4si_di_load;

58253

- rs6000_vector_reload[V2DImode][0] = CODE_FOR_reload_v2di_di_store;

58254

- rs6000_vector_reload[V2DImode][1] = CODE_FOR_reload_v2di_di_load;

58255

- rs6000_vector_reload[V4SFmode][0] = CODE_FOR_reload_v4sf_di_store;

58256

- rs6000_vector_reload[V4SFmode][1] = CODE_FOR_reload_v4sf_di_load;

58257

- rs6000_vector_reload[V2DFmode][0] = CODE_FOR_reload_v2df_di_store;

58258

- rs6000_vector_reload[V2DFmode][1] = CODE_FOR_reload_v2df_di_load;

58259

- if (TARGET_VSX && TARGET_VSX_SCALAR_MEMORY)

58260

+ reg_addr[V16QImode].reload_store = CODE_FOR_reload_v16qi_di_store;

58261

+ reg_addr[V16QImode].reload_load = CODE_FOR_reload_v16qi_di_load;

58262

+ reg_addr[V8HImode].reload_store = CODE_FOR_reload_v8hi_di_store;

58263

+ reg_addr[V8HImode].reload_load = CODE_FOR_reload_v8hi_di_load;

58264

+ reg_addr[V4SImode].reload_store = CODE_FOR_reload_v4si_di_store;

58265

+ reg_addr[V4SImode].reload_load = CODE_FOR_reload_v4si_di_load;

58266

+ reg_addr[V2DImode].reload_store = CODE_FOR_reload_v2di_di_store;

58267

+ reg_addr[V2DImode].reload_load = CODE_FOR_reload_v2di_di_load;

58268

+ reg_addr[V1TImode].reload_store = CODE_FOR_reload_v1ti_di_store;

58269

+ reg_addr[V1TImode].reload_load = CODE_FOR_reload_v1ti_di_load;

58270

+ reg_addr[V4SFmode].reload_store = CODE_FOR_reload_v4sf_di_store;

58271

+ reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_di_load;

58272

+ reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_di_store;

58273

+ reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_di_load;

58274

+ if (TARGET_VSX && TARGET_UPPER_REGS_DF)

58275

{

58276

- rs6000_vector_reload[DFmode][0] = CODE_FOR_reload_df_di_store;

58277

- rs6000_vector_reload[DFmode][1] = CODE_FOR_reload_df_di_load;

58278

+ reg_addr[DFmode].reload_store = CODE_FOR_reload_df_di_store;

58279

+ reg_addr[DFmode].reload_load = CODE_FOR_reload_df_di_load;

58280

+ reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_di_store;

58281

+ reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_di_load;

58282

}

58283

+ if (TARGET_P8_VECTOR)

58284

+ {

58285

+ reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_di_store;

58286

+ reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_di_load;

58287

+ reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_di_store;

58288

+ reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_di_load;

58289

+ }

58290

+ if (TARGET_VSX_TIMODE)

58291

+ {

58292

+ reg_addr[TImode].reload_store = CODE_FOR_reload_ti_di_store;

58293

+ reg_addr[TImode].reload_load = CODE_FOR_reload_ti_di_load;

58294

+ }

58295

+ if (TARGET_DIRECT_MOVE)

58296

+ {

58297

+ if (TARGET_POWERPC64)

58298

+ {

58299

+ reg_addr[TImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxti;

58300

+ reg_addr[V1TImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv1ti;

58301

+ reg_addr[V2DFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv2df;

58302

+ reg_addr[V2DImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv2di;

58303

+ reg_addr[V4SFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv4sf;

58304

+ reg_addr[V4SImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv4si;

58305

+ reg_addr[V8HImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv8hi;

58306

+ reg_addr[V16QImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv16qi;

58307

+ reg_addr[SFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxsf;

58308

+

58309

+ reg_addr[TImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprti;

58310

+ reg_addr[V1TImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv1ti;

58311

+ reg_addr[V2DFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv2df;

58312

+ reg_addr[V2DImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv2di;

58313

+ reg_addr[V4SFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv4sf;

58314

+ reg_addr[V4SImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv4si;

58315

+ reg_addr[V8HImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv8hi;

58316

+ reg_addr[V16QImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv16qi;

58317

+ reg_addr[SFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprsf;

58318

+ }

58319

+ else

58320

+ {

58321

+ reg_addr[DImode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdi;

58322

+ reg_addr[DDmode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdd;

58323

+ reg_addr[DFmode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdf;

58324

+ }

58325

+ }

58326

}

58327

else

58328

{

58329

- rs6000_vector_reload[V16QImode][0] = CODE_FOR_reload_v16qi_si_store;

58330

- rs6000_vector_reload[V16QImode][1] = CODE_FOR_reload_v16qi_si_load;

58331

- rs6000_vector_reload[V8HImode][0] = CODE_FOR_reload_v8hi_si_store;

58332

- rs6000_vector_reload[V8HImode][1] = CODE_FOR_reload_v8hi_si_load;

58333

- rs6000_vector_reload[V4SImode][0] = CODE_FOR_reload_v4si_si_store;

58334

- rs6000_vector_reload[V4SImode][1] = CODE_FOR_reload_v4si_si_load;

58335

- rs6000_vector_reload[V2DImode][0] = CODE_FOR_reload_v2di_si_store;

58336

- rs6000_vector_reload[V2DImode][1] = CODE_FOR_reload_v2di_si_load;

58337

- rs6000_vector_reload[V4SFmode][0] = CODE_FOR_reload_v4sf_si_store;

58338

- rs6000_vector_reload[V4SFmode][1] = CODE_FOR_reload_v4sf_si_load;

58339

- rs6000_vector_reload[V2DFmode][0] = CODE_FOR_reload_v2df_si_store;

58340

- rs6000_vector_reload[V2DFmode][1] = CODE_FOR_reload_v2df_si_load;

58341

- if (TARGET_VSX && TARGET_VSX_SCALAR_MEMORY)

58342

+ reg_addr[V16QImode].reload_store = CODE_FOR_reload_v16qi_si_store;

58343

+ reg_addr[V16QImode].reload_load = CODE_FOR_reload_v16qi_si_load;

58344

+ reg_addr[V8HImode].reload_store = CODE_FOR_reload_v8hi_si_store;

58345

+ reg_addr[V8HImode].reload_load = CODE_FOR_reload_v8hi_si_load;

58346

+ reg_addr[V4SImode].reload_store = CODE_FOR_reload_v4si_si_store;

58347

+ reg_addr[V4SImode].reload_load = CODE_FOR_reload_v4si_si_load;

58348

+ reg_addr[V2DImode].reload_store = CODE_FOR_reload_v2di_si_store;

58349

+ reg_addr[V2DImode].reload_load = CODE_FOR_reload_v2di_si_load;

58350

+ reg_addr[V1TImode].reload_store = CODE_FOR_reload_v1ti_si_store;

58351

+ reg_addr[V1TImode].reload_load = CODE_FOR_reload_v1ti_si_load;

58352

+ reg_addr[V4SFmode].reload_store = CODE_FOR_reload_v4sf_si_store;

58353

+ reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_si_load;

58354

+ reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_si_store;

58355

+ reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_si_load;

58356

+ if (TARGET_VSX && TARGET_UPPER_REGS_DF)

58357

{

58358

- rs6000_vector_reload[DFmode][0] = CODE_FOR_reload_df_si_store;

58359

- rs6000_vector_reload[DFmode][1] = CODE_FOR_reload_df_si_load;

58360

+ reg_addr[DFmode].reload_store = CODE_FOR_reload_df_si_store;

58361

+ reg_addr[DFmode].reload_load = CODE_FOR_reload_df_si_load;

58362

+ reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_si_store;

58363

+ reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_si_load;

58364

}

58365

+ if (TARGET_P8_VECTOR)

58366

+ {

58367

+ reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_si_store;

58368

+ reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_si_load;

58369

+ reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_si_store;

58370

+ reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_si_load;

58371

+ }

58372

+ if (TARGET_VSX_TIMODE)

58373

+ {

58374

+ reg_addr[TImode].reload_store = CODE_FOR_reload_ti_si_store;

58375

+ reg_addr[TImode].reload_load = CODE_FOR_reload_ti_si_load;

58376

+ }

58377

}

58378

}

58379

58380

@@ -2267,6 +2893,11 @@

58381

}

58382

}

58383

58384

+ /* Update the addr mask bits in reg_addr to help secondary reload and go if

58385

+ legitimate address support to figure out the appropriate addressing to

58386

+ use. */

58387

+ rs6000_setup_reg_addr_masks ();

58388

+

58389

if (global_init_p || TARGET_DEBUG_TARGET)

58390

{

58391

if (TARGET_DEBUG_REG)

58392

@@ -2369,16 +3000,21 @@

58393

HOST_WIDE_INT

58394

rs6000_builtin_mask_calculate (void)

58395

{

58396

- return (((TARGET_ALTIVEC) ? RS6000_BTM_ALTIVEC : 0)

58397

- | ((TARGET_VSX) ? RS6000_BTM_VSX : 0)

58398

- | ((TARGET_SPE) ? RS6000_BTM_SPE : 0)

58399

- | ((TARGET_PAIRED_FLOAT) ? RS6000_BTM_PAIRED : 0)

58400

- | ((TARGET_FRE) ? RS6000_BTM_FRE : 0)

58401

- | ((TARGET_FRES) ? RS6000_BTM_FRES : 0)

58402

- | ((TARGET_FRSQRTE) ? RS6000_BTM_FRSQRTE : 0)

58403

- | ((TARGET_FRSQRTES) ? RS6000_BTM_FRSQRTES : 0)

58404

- | ((TARGET_POPCNTD) ? RS6000_BTM_POPCNTD : 0)

58405

- | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0));

58406

+ return (((TARGET_ALTIVEC) ? RS6000_BTM_ALTIVEC : 0)

58407

+ | ((TARGET_VSX) ? RS6000_BTM_VSX : 0)

58408

+ | ((TARGET_SPE) ? RS6000_BTM_SPE : 0)

58409

+ | ((TARGET_PAIRED_FLOAT) ? RS6000_BTM_PAIRED : 0)

58410

+ | ((TARGET_FRE) ? RS6000_BTM_FRE : 0)

58411

+ | ((TARGET_FRES) ? RS6000_BTM_FRES : 0)

58412

+ | ((TARGET_FRSQRTE) ? RS6000_BTM_FRSQRTE : 0)

58413

+ | ((TARGET_FRSQRTES) ? RS6000_BTM_FRSQRTES : 0)

58414

+ | ((TARGET_POPCNTD) ? RS6000_BTM_POPCNTD : 0)

58415

+ | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0)

58416

+ | ((TARGET_P8_VECTOR) ? RS6000_BTM_P8_VECTOR : 0)

58417

+ | ((TARGET_CRYPTO) ? RS6000_BTM_CRYPTO : 0)

58418

+ | ((TARGET_HTM) ? RS6000_BTM_HTM : 0)

58419

+ | ((TARGET_DFP) ? RS6000_BTM_DFP : 0)

58420

+ | ((TARGET_HARD_FLOAT) ? RS6000_BTM_HARD_FLOAT : 0));

58421

}

58422

58423

/* Override command line options. Mostly we process the processor type and

58424

@@ -2415,7 +3051,8 @@

58425

calculation works better for RTL loop invariant motion on targets

58426

with enough (>= 32) registers. It is an expensive optimization.

58427

So it is on only for peak performance. */

58428

- if (optimize >= 3 && global_init_p)

58429

+ if (optimize >= 3 && global_init_p

58430

+ && !global_options_set.x_flag_ira_loop_pressure)

58431

flag_ira_loop_pressure = 1;

58432

58433

/* Set the pointer size. */

58434

@@ -2609,6 +3246,24 @@

58435

}

58436

}

58437

58438

+ /* If little-endian, default to -mstrict-align on older processors.

58439

+ Testing for htm matches power8 and later. */

58440

+ if (!BYTES_BIG_ENDIAN

58441

+ && !(processor_target_table[tune_index].target_enable & OPTION_MASK_HTM))

58442

+ rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_STRICT_ALIGN;

58443

+

58444

+ /* -maltivec={le,be} implies -maltivec. */

58445

+ if (rs6000_altivec_element_order != 0)

58446

+ rs6000_isa_flags |= OPTION_MASK_ALTIVEC;

58447

+

58448

+ /* Disallow -maltivec=le in big endian mode for now. This is not

58449

+ known to be useful for anyone. */

58450

+ if (BYTES_BIG_ENDIAN && rs6000_altivec_element_order == 1)

58451

+ {

58452

+ warning (0, N_("-maltivec=le not allowed for big-endian targets"));

58453

+ rs6000_altivec_element_order = 0;

58454

+ }

58455

+

58456

/* Add some warnings for VSX. */

58457

if (TARGET_VSX)

58458

{

58459

@@ -2619,15 +3274,13 @@

58460

if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)

58461

msg = N_("-mvsx requires hardware floating point");

58462

else

58463

- rs6000_isa_flags &= ~ OPTION_MASK_VSX;

58464

+ {

58465

+ rs6000_isa_flags &= ~ OPTION_MASK_VSX;

58466

+ rs6000_isa_flags_explicit |= OPTION_MASK_VSX;

58467

+ }

58468

}

58469

else if (TARGET_PAIRED_FLOAT)

58470

msg = N_("-mvsx and -mpaired are incompatible");

58471

- /* The hardware will allow VSX and little endian, but until we make sure

58472

- things like vector select, etc. work don't allow VSX on little endian

58473

- systems at this point. */

58474

- else if (!BYTES_BIG_ENDIAN)

58475

- msg = N_("-mvsx used with little endian code");

58476

else if (TARGET_AVOID_XFORM > 0)

58477

msg = N_("-mvsx needs indexed addressing");

58478

else if (!TARGET_ALTIVEC && (rs6000_isa_flags_explicit

58479

@@ -2647,9 +3300,24 @@

58480

}

58481

}

58482

58483

+ /* If hard-float/altivec/vsx were explicitly turned off then don't allow

58484

+ the -mcpu setting to enable options that conflict. */

58485

+ if ((!TARGET_HARD_FLOAT || !TARGET_ALTIVEC || !TARGET_VSX)

58486

+ && (rs6000_isa_flags_explicit & (OPTION_MASK_SOFT_FLOAT

58487

+ | OPTION_MASK_ALTIVEC

58488

+ | OPTION_MASK_VSX)) != 0)

58489

+ rs6000_isa_flags &= ~((OPTION_MASK_P8_VECTOR | OPTION_MASK_CRYPTO

58490

+ | OPTION_MASK_DIRECT_MOVE)

58491

+ & ~rs6000_isa_flags_explicit);

58492

+

58493

+ if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)

58494

+ rs6000_print_isa_options (stderr, 0, "before defaults", rs6000_isa_flags);

58495

+

58496

/* For the newer switches (vsx, dfp, etc.) set some of the older options,

58497

unless the user explicitly used the -mno-<option> to disable the code. */

58498

- if (TARGET_VSX)

58499

+ if (TARGET_P8_VECTOR || TARGET_DIRECT_MOVE || TARGET_CRYPTO)

58500

+ rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~rs6000_isa_flags_explicit);

58501

+ else if (TARGET_VSX)

58502

rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~rs6000_isa_flags_explicit);

58503

else if (TARGET_POPCNTD)

58504

rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~rs6000_isa_flags_explicit);

58505

@@ -2664,6 +3332,99 @@

58506

else if (TARGET_ALTIVEC)

58507

rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~rs6000_isa_flags_explicit);

58508

58509

+ if (TARGET_CRYPTO && !TARGET_ALTIVEC)

58510

+ {

58511

+ if (rs6000_isa_flags_explicit & OPTION_MASK_CRYPTO)

58512

+ error ("-mcrypto requires -maltivec");

58513

+ rs6000_isa_flags &= ~OPTION_MASK_CRYPTO;

58514

+ }

58515

+

58516

+ if (TARGET_DIRECT_MOVE && !TARGET_VSX)

58517

+ {

58518

+ if (rs6000_isa_flags_explicit & OPTION_MASK_DIRECT_MOVE)

58519

+ error ("-mdirect-move requires -mvsx");

58520

+ rs6000_isa_flags &= ~OPTION_MASK_DIRECT_MOVE;

58521

+ }

58522

+

58523

+ if (TARGET_P8_VECTOR && !TARGET_ALTIVEC)

58524

+ {

58525

+ if (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)

58526

+ error ("-mpower8-vector requires -maltivec");

58527

+ rs6000_isa_flags &= ~OPTION_MASK_P8_VECTOR;

58528

+ }

58529

+

58530

+ if (TARGET_P8_VECTOR && !TARGET_VSX)

58531

+ {

58532

+ if (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)

58533

+ error ("-mpower8-vector requires -mvsx");

58534

+ rs6000_isa_flags &= ~OPTION_MASK_P8_VECTOR;

58535

+ }

58536

+

58537

+ if (TARGET_VSX_TIMODE && !TARGET_VSX)

58538

+ {

58539

+ if (rs6000_isa_flags_explicit & OPTION_MASK_VSX_TIMODE)

58540

+ error ("-mvsx-timode requires -mvsx");

58541

+ rs6000_isa_flags &= ~OPTION_MASK_VSX_TIMODE;

58542

+ }

58543

+

58544

+ if (TARGET_DFP && !TARGET_HARD_FLOAT)

58545

+ {

58546

+ if (rs6000_isa_flags_explicit & OPTION_MASK_DFP)

58547

+ error ("-mhard-dfp requires -mhard-float");

58548

+ rs6000_isa_flags &= ~OPTION_MASK_DFP;

58549

+ }

58550

+

58551

+ /* The quad memory instructions only works in 64-bit mode. In 32-bit mode,

58552

+ silently turn off quad memory mode. */

58553

+ if ((TARGET_QUAD_MEMORY || TARGET_QUAD_MEMORY_ATOMIC) && !TARGET_POWERPC64)

58554

+ {

58555

+ if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY) != 0)

58556

+ warning (0, N_("-mquad-memory requires 64-bit mode"));

58557

+

58558

+ if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY_ATOMIC) != 0)

58559

+ warning (0, N_("-mquad-memory-atomic requires 64-bit mode"));

58560

+

58561

+ rs6000_isa_flags &= ~(OPTION_MASK_QUAD_MEMORY

58562

+ | OPTION_MASK_QUAD_MEMORY_ATOMIC);

58563

+ }

58564

+

58565

+ /* Non-atomic quad memory load/store are disabled for little endian, since

58566

+ the words are reversed, but atomic operations can still be done by

58567

+ swapping the words. */

58568

+ if (TARGET_QUAD_MEMORY && !WORDS_BIG_ENDIAN)

58569

+ {

58570

+ if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY) != 0)

58571

+ warning (0, N_("-mquad-memory is not available in little endian mode"));

58572

+

58573

+ rs6000_isa_flags &= ~OPTION_MASK_QUAD_MEMORY;

58574

+ }

58575

+

58576

+ /* Assume if the user asked for normal quad memory instructions, they want

58577

+ the atomic versions as well, unless they explicity told us not to use quad

58578

+ word atomic instructions. */

58579

+ if (TARGET_QUAD_MEMORY

58580

+ && !TARGET_QUAD_MEMORY_ATOMIC

58581

+ && ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY_ATOMIC) == 0))

58582

+ rs6000_isa_flags |= OPTION_MASK_QUAD_MEMORY_ATOMIC;

58583

+

58584

+ /* Enable power8 fusion if we are tuning for power8, even if we aren't

58585

+ generating power8 instructions. */

58586

+ if (!(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION))

58587

+ rs6000_isa_flags |= (processor_target_table[tune_index].target_enable

58588

+ & OPTION_MASK_P8_FUSION);

58589

+

58590

+ /* Power8 does not fuse sign extended loads with the addis. If we are

58591

+ optimizing at high levels for speed, convert a sign extended load into a

58592

+ zero extending load, and an explicit sign extension. */

58593

+ if (TARGET_P8_FUSION

58594

+ && !(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION_SIGN)

58595

+ && optimize_function_for_speed_p (cfun)

58596

+ && optimize >= 3)

58597

+ rs6000_isa_flags |= OPTION_MASK_P8_FUSION_SIGN;

58598

+

58599

+ if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)

58600

+ rs6000_print_isa_options (stderr, 0, "after defaults", rs6000_isa_flags);

58601

+

58602

/* E500mc does "better" if we inline more aggressively. Respect the

58603

user's opinion, though. */

58604

if (rs6000_block_move_inline_limit == 0

58605

@@ -2787,9 +3548,13 @@

58606

58607

/* Place FP constants in the constant pool instead of TOC

58608

if section anchors enabled. */

58609

- if (flag_section_anchors)

58610

+ if (flag_section_anchors

58611

+ && !global_options_set.x_TARGET_NO_FP_IN_TOC)

58612

TARGET_NO_FP_IN_TOC = 1;

58613

58614

+ if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)

58615

+ rs6000_print_isa_options (stderr, 0, "before subtarget", rs6000_isa_flags);

58616

+

58617

#ifdef SUBTARGET_OVERRIDE_OPTIONS

58618

SUBTARGET_OVERRIDE_OPTIONS;

58619

#endif

58620

@@ -2800,6 +3565,9 @@

58621

SUB3TARGET_OVERRIDE_OPTIONS;

58622

#endif

58623

58624

+ if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)

58625

+ rs6000_print_isa_options (stderr, 0, "after subtarget", rs6000_isa_flags);

58626

+

58627

/* For the E500 family of cores, reset the single/double FP flags to let us

58628

check that they remain constant across attributes or pragmas. Also,

58629

clear a possible request for string instructions, not supported and which

58630

@@ -2849,16 +3617,19 @@

58631

&& rs6000_cpu != PROCESSOR_POWER5

58632

&& rs6000_cpu != PROCESSOR_POWER6

58633

&& rs6000_cpu != PROCESSOR_POWER7

58634

+ && rs6000_cpu != PROCESSOR_POWER8

58635

&& rs6000_cpu != PROCESSOR_PPCA2

58636

&& rs6000_cpu != PROCESSOR_CELL

58637

&& rs6000_cpu != PROCESSOR_PPC476);

58638

rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4

58639

|| rs6000_cpu == PROCESSOR_POWER5

58640

- || rs6000_cpu == PROCESSOR_POWER7);

58641

+ || rs6000_cpu == PROCESSOR_POWER7

58642

+ || rs6000_cpu == PROCESSOR_POWER8);

58643

rs6000_align_branch_targets = (rs6000_cpu == PROCESSOR_POWER4

58644

|| rs6000_cpu == PROCESSOR_POWER5

58645

|| rs6000_cpu == PROCESSOR_POWER6

58646

|| rs6000_cpu == PROCESSOR_POWER7

58647

+ || rs6000_cpu == PROCESSOR_POWER8

58648

|| rs6000_cpu == PROCESSOR_PPCE500MC

58649

|| rs6000_cpu == PROCESSOR_PPCE500MC64

58650

|| rs6000_cpu == PROCESSOR_PPCE5500

58651

@@ -2988,7 +3759,7 @@

58652

58653

/* We should always be splitting complex arguments, but we can't break

58654

Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */

58655

- if (DEFAULT_ABI != ABI_AIX)

58656

+ if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN)

58657

targetm.calls.split_complex_arg = NULL;

58658

}

58659

58660

@@ -3102,6 +3873,10 @@

58661

rs6000_cost = &power7_cost;

58662

break;

58663

58664

+ case PROCESSOR_POWER8:

58665

+ rs6000_cost = &power8_cost;

58666

+ break;

58667

+

58668

case PROCESSOR_PPCA2:

58669

rs6000_cost = &ppca2_cost;

58670

break;

58671

@@ -3274,7 +4049,8 @@

58672

&& (rs6000_cpu == PROCESSOR_POWER4

58673

|| rs6000_cpu == PROCESSOR_POWER5

58674

|| rs6000_cpu == PROCESSOR_POWER6

58675

- || rs6000_cpu == PROCESSOR_POWER7))

58676

+ || rs6000_cpu == PROCESSOR_POWER7

58677

+ || rs6000_cpu == PROCESSOR_POWER8))

58678

return 5;

58679

else

58680

return align_loops_log;

58681

@@ -3493,6 +4269,8 @@

58682

{

58683

case SFmode:

58684

return V4SFmode;

58685

+ case TImode:

58686

+ return V1TImode;

58687

case DImode:

58688

return V2DImode;

58689

case SImode:

58690

@@ -3813,6 +4591,22 @@

58691

enum built_in_function fn = DECL_FUNCTION_CODE (fndecl);

58692

switch (fn)

58693

{

58694

+ case BUILT_IN_CLZIMAX:

58695

+ case BUILT_IN_CLZLL:

58696

+ case BUILT_IN_CLZL:

58697

+ case BUILT_IN_CLZ:

58698

+ if (TARGET_P8_VECTOR && in_mode == out_mode && out_n == in_n)

58699

+ {

58700

+ if (out_mode == QImode && out_n == 16)

58701

+ return rs6000_builtin_decls[P8V_BUILTIN_VCLZB];

58702

+ else if (out_mode == HImode && out_n == 8)

58703

+ return rs6000_builtin_decls[P8V_BUILTIN_VCLZH];

58704

+ else if (out_mode == SImode && out_n == 4)

58705

+ return rs6000_builtin_decls[P8V_BUILTIN_VCLZW];

58706

+ else if (out_mode == DImode && out_n == 2)

58707

+ return rs6000_builtin_decls[P8V_BUILTIN_VCLZD];

58708

+ }

58709

+ break;

58710

case BUILT_IN_COPYSIGN:

58711

if (VECTOR_UNIT_VSX_P (V2DFmode)

58712

&& out_mode == DFmode && out_n == 2

58713

@@ -3828,6 +4622,22 @@

58714

if (VECTOR_UNIT_ALTIVEC_P (V4SFmode))

58715

return rs6000_builtin_decls[ALTIVEC_BUILTIN_COPYSIGN_V4SF];

58716

break;

58717

+ case BUILT_IN_POPCOUNTIMAX:

58718

+ case BUILT_IN_POPCOUNTLL:

58719

+ case BUILT_IN_POPCOUNTL:

58720

+ case BUILT_IN_POPCOUNT:

58721

+ if (TARGET_P8_VECTOR && in_mode == out_mode && out_n == in_n)

58722

+ {

58723

+ if (out_mode == QImode && out_n == 16)

58724

+ return rs6000_builtin_decls[P8V_BUILTIN_VPOPCNTB];

58725

+ else if (out_mode == HImode && out_n == 8)

58726

+ return rs6000_builtin_decls[P8V_BUILTIN_VPOPCNTH];

58727

+ else if (out_mode == SImode && out_n == 4)

58728

+ return rs6000_builtin_decls[P8V_BUILTIN_VPOPCNTW];

58729

+ else if (out_mode == DImode && out_n == 2)

58730

+ return rs6000_builtin_decls[P8V_BUILTIN_VPOPCNTD];

58731

+ }

58732

+ break;

58733

case BUILT_IN_SQRT:

58734

if (VECTOR_UNIT_VSX_P (V2DFmode)

58735

&& out_mode == DFmode && out_n == 2

58736

@@ -4043,7 +4853,11 @@

58737

putc ('\n', file);

58738

}

58739

58740

- if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))

58741

+ if (DEFAULT_ABI == ABI_ELFv2)

58742

+ fprintf (file, "\t.abiversion 2\n");

58743

+

58744

+ if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2

58745

+ || (TARGET_ELF && flag_pic == 2))

58746

{

58747

switch_to_section (toc_section);

58748

switch_to_section (text_section);

58749

@@ -4230,7 +5044,7 @@

58750

HOST_WIDE_INT splat_val;

58751

HOST_WIDE_INT msb_val;

58752

58753

- if (mode == V2DImode || mode == V2DFmode)

58754

+ if (mode == V2DImode || mode == V2DFmode || mode == V1TImode)

58755

return false;

58756

58757

nunits = GET_MODE_NUNITS (mode);

58758

@@ -4239,7 +5053,7 @@

58759

58760

val = const_vector_elt_as_int (op, BYTES_BIG_ENDIAN ? nunits - 1 : 0);

58761

splat_val = val;

58762

- msb_val = val > 0 ? 0 : -1;

58763

+ msb_val = val >= 0 ? 0 : -1;

58764

58765

/* Construct the value to be splatted, if possible. If not, return 0. */

58766

for (i = 2; i <= copies; i *= 2)

58767

@@ -4274,15 +5088,16 @@

58768

58769

/* Check if VAL is present in every STEP-th element, and the

58770

other elements are filled with its most significant bit. */

58771

- for (i = 0; i < nunits - 1; ++i)

58772

+ for (i = 1; i < nunits; ++i)

58773

{

58774

HOST_WIDE_INT desired_val;

58775

- if (((BYTES_BIG_ENDIAN ? i + 1 : i) & (step - 1)) == 0)

58776

+ unsigned elt = BYTES_BIG_ENDIAN ? nunits - 1 - i : i;

58777

+ if ((i & (step - 1)) == 0)

58778

desired_val = val;

58779

else

58780

desired_val = msb_val;

58781

58782

- if (desired_val != const_vector_elt_as_int (op, i))

58783

+ if (desired_val != const_vector_elt_as_int (op, elt))

58784

return false;

58785

}

58786

58787

@@ -4308,7 +5123,7 @@

58788

if (mode == V2DFmode)

58789

return zero_constant (op, mode);

58790

58791

- if (mode == V2DImode)

58792

+ else if (mode == V2DImode)

58793

{

58794

/* In case the compiler is built 32-bit, CONST_DOUBLE constants are not

58795

easy. */

58796

@@ -4326,6 +5141,10 @@

58797

return false;

58798

}

58799

58800

+ /* V1TImode is a special container for TImode. Ignore for now. */

58801

+ else if (mode == V1TImode)

58802

+ return false;

58803

+

58804

/* Start with a vspltisw. */

58805

step = GET_MODE_NUNITS (mode) / 4;

58806

copies = 1;

58807

@@ -4407,7 +5226,7 @@

58808

if (zero_constant (vec, mode))

58809

return "xxlxor %x0,%x0,%x0";

58810

58811

- if (mode == V2DImode

58812

+ if ((mode == V2DImode || mode == V1TImode)

58813

&& INTVAL (CONST_VECTOR_ELT (vec, 0)) == -1

58814

&& INTVAL (CONST_VECTOR_ELT (vec, 1)) == -1)

58815

return "vspltisw %0,-1";

58816

@@ -4698,9 +5517,12 @@

58817

{

58818

rtx freg = gen_reg_rtx (V4SFmode);

58819

rtx sreg = force_reg (SFmode, XVECEXP (vals, 0, 0));

58820

+ rtx cvt = ((TARGET_XSCVDPSPN)

58821

+ ? gen_vsx_xscvdpspn_scalar (freg, sreg)

58822

+ : gen_vsx_xscvdpsp_scalar (freg, sreg));

58823

58824

- emit_insn (gen_vsx_xscvdpsp_scalar (freg, sreg));

58825

- emit_insn (gen_vsx_xxspltw_v4sf (target, freg, const0_rtx));

58826

+ emit_insn (cvt);

58827

+ emit_insn (gen_vsx_xxspltw_v4sf_direct (target, freg, const0_rtx));

58828

}

58829

else

58830

{

58831

@@ -4790,6 +5612,13 @@

58832

return;

58833

}

58834

58835

+ /* Simplify setting single element vectors like V1TImode. */

58836

+ if (GET_MODE_SIZE (mode) == GET_MODE_SIZE (inner_mode) && elt == 0)

58837

+ {

58838

+ emit_move_insn (target, gen_lowpart (mode, val));

58839

+ return;

58840

+ }

58841

+

58842

/* Load single variable value. */

58843

mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode));

58844

emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);

58845

@@ -4811,10 +5640,29 @@

58846

XVECEXP (mask, 0, elt*width + i)

58847

= GEN_INT (i + 0x10);

58848

x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));

58849

- x = gen_rtx_UNSPEC (mode,

58850

- gen_rtvec (3, target, reg,

58851

- force_reg (V16QImode, x)),

58852

- UNSPEC_VPERM);

58853

+

58854

+ if (BYTES_BIG_ENDIAN)

58855

+ x = gen_rtx_UNSPEC (mode,

58856

+ gen_rtvec (3, target, reg,

58857

+ force_reg (V16QImode, x)),

58858

+ UNSPEC_VPERM);

58859

+ else

58860

+ {

58861

+ /* Invert selector. We prefer to generate VNAND on P8 so

58862

+ that future fusion opportunities can kick in, but must

58863

+ generate VNOR elsewhere. */

58864

+ rtx notx = gen_rtx_NOT (V16QImode, force_reg (V16QImode, x));

58865

+ rtx iorx = (TARGET_P8_VECTOR

58866

+ ? gen_rtx_IOR (V16QImode, notx, notx)

58867

+ : gen_rtx_AND (V16QImode, notx, notx));

58868

+ rtx tmp = gen_reg_rtx (V16QImode);

58869

+ emit_insn (gen_rtx_SET (VOIDmode, tmp, iorx));

58870

+

58871

+ /* Permute with operands reversed and adjusted selector. */

58872

+ x = gen_rtx_UNSPEC (mode, gen_rtvec (3, reg, target, tmp),

58873

+ UNSPEC_VPERM);

58874

+ }

58875

+

58876

emit_insn (gen_rtx_SET (VOIDmode, target, x));

58877

}

58878

58879

@@ -4833,6 +5681,10 @@

58880

{

58881

default:

58882

break;

58883

+ case V1TImode:

58884

+ gcc_assert (elt == 0 && inner_mode == TImode);

58885

+ emit_move_insn (target, gen_lowpart (TImode, vec));

58886

+ break;

58887

case V2DFmode:

58888

emit_insn (gen_vsx_extract_v2df (target, vec, GEN_INT (elt)));

58889

return;

58890

@@ -4938,7 +5790,7 @@

58891

purpose. */

58892

if (GET_CODE (op) == SUBREG

58893

&& (mode == SImode || mode == DImode || mode == TImode

58894

- || mode == DDmode || mode == TDmode)

58895

+ || mode == DDmode || mode == TDmode || mode == PTImode)

58896

&& REG_P (SUBREG_REG (op))

58897

&& (GET_MODE (SUBREG_REG (op)) == DFmode

58898

|| GET_MODE (SUBREG_REG (op)) == TFmode))

58899

@@ -4951,6 +5803,7 @@

58900

&& REG_P (SUBREG_REG (op))

58901

&& (GET_MODE (SUBREG_REG (op)) == DImode

58902

|| GET_MODE (SUBREG_REG (op)) == TImode

58903

+ || GET_MODE (SUBREG_REG (op)) == PTImode

58904

|| GET_MODE (SUBREG_REG (op)) == DDmode

58905

|| GET_MODE (SUBREG_REG (op)) == TDmode))

58906

return true;

58907

@@ -4966,6 +5819,48 @@

58908

return false;

58909

}

58910

58911

+/* Return alignment of TYPE. Existing alignment is ALIGN. HOW

58912

+ selects whether the alignment is abi mandated, optional, or

58913

+ both abi and optional alignment. */

58914

+

58915

+unsigned int

58916

+rs6000_data_alignment (tree type, unsigned int align, enum data_align how)

58917

+{

58918

+ if (how != align_opt)

58919

+ {

58920

+ if (TREE_CODE (type) == VECTOR_TYPE)

58921

+ {

58922

+ if ((TARGET_SPE && SPE_VECTOR_MODE (TYPE_MODE (type)))

58923

+ || (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (TYPE_MODE (type))))

58924

+ {

58925

+ if (align < 64)

58926

+ align = 64;

58927

+ }

58928

+ else if (align < 128)

58929

+ align = 128;

58930

+ }

58931

+ else if (TARGET_E500_DOUBLE

58932

+ && TREE_CODE (type) == REAL_TYPE

58933

+ && TYPE_MODE (type) == DFmode)

58934

+ {

58935

+ if (align < 64)

58936

+ align = 64;

58937

+ }

58938

+ }

58939

+

58940

+ if (how != align_abi)

58941

+ {

58942

+ if (TREE_CODE (type) == ARRAY_TYPE

58943

+ && TYPE_MODE (TREE_TYPE (type)) == QImode)

58944

+ {

58945

+ if (align < BITS_PER_WORD)

58946

+ align = BITS_PER_WORD;

58947

+ }

58948

+ }

58949

+

58950

+ return align;

58951

+}

58952

+

58953

/* AIX increases natural record alignment to doubleword if the first

58954

field is an FP double while the FP fields remain word aligned. */

58955

58956

@@ -5087,6 +5982,73 @@

58957

|| (REG_P (op1) && INT_REGNO_P (REGNO (op1))));

58958

}

58959

58960

+/* Return true if this is a move direct operation between GPR registers and

58961

+ floating point/VSX registers. */

58962

+

58963

+bool

58964

+direct_move_p (rtx op0, rtx op1)

58965

+{

58966

+ int regno0, regno1;

58967

+

58968

+ if (!REG_P (op0) || !REG_P (op1))

58969

+ return false;

58970

+

58971

+ if (!TARGET_DIRECT_MOVE && !TARGET_MFPGPR)

58972

+ return false;

58973

+

58974

+ regno0 = REGNO (op0);

58975

+ regno1 = REGNO (op1);

58976

+ if (regno0 >= FIRST_PSEUDO_REGISTER || regno1 >= FIRST_PSEUDO_REGISTER)

58977

+ return false;

58978

+

58979

+ if (INT_REGNO_P (regno0))

58980

+ return (TARGET_DIRECT_MOVE) ? VSX_REGNO_P (regno1) : FP_REGNO_P (regno1);

58981

+

58982

+ else if (INT_REGNO_P (regno1))

58983

+ {

58984

+ if (TARGET_MFPGPR && FP_REGNO_P (regno0))

58985

+ return true;

58986

+

58987

+ else if (TARGET_DIRECT_MOVE && VSX_REGNO_P (regno0))

58988

+ return true;

58989

+ }

58990

+

58991

+ return false;

58992

+}

58993

+

58994

+/* Return true if this is a load or store quad operation. This function does

58995

+ not handle the atomic quad memory instructions. */

58996

+

58997

+bool

58998

+quad_load_store_p (rtx op0, rtx op1)

58999

+{

59000

+ bool ret;

59001

+

59002

+ if (!TARGET_QUAD_MEMORY)

59003

+ ret = false;

59004

+

59005

+ else if (REG_P (op0) && MEM_P (op1))

59006

+ ret = (quad_int_reg_operand (op0, GET_MODE (op0))

59007

+ && quad_memory_operand (op1, GET_MODE (op1))

59008

+ && !reg_overlap_mentioned_p (op0, op1));

59009

+

59010

+ else if (MEM_P (op0) && REG_P (op1))

59011

+ ret = (quad_memory_operand (op0, GET_MODE (op0))

59012

+ && quad_int_reg_operand (op1, GET_MODE (op1)));

59013

+

59014

+ else

59015

+ ret = false;

59016

+

59017

+ if (TARGET_DEBUG_ADDR)

59018

+ {

59019

+ fprintf (stderr, "\n========== quad_load_store, return %s\n",

59020

+ ret ? "true" : "false");

59021

+ debug_rtx (gen_rtx_SET (VOIDmode, op0, op1));

59022

+ }

59023

+

59024

+ return ret;

59025

+}

59026

+

59027

/* Given an address, return a constant offset term if one exists. */

59028

59029

static rtx

59030

@@ -5170,7 +6132,12 @@

59031

case V4SImode:

59032

case V2DFmode:

59033

case V2DImode:

59034

- /* AltiVec/VSX vector modes. Only reg+reg addressing is valid. */

59035

+ case V1TImode:

59036

+ case TImode:

59037

+ /* AltiVec/VSX vector modes. Only reg+reg addressing is valid. While

59038

+ TImode is not a vector mode, if we want to use the VSX registers to

59039

+ move it around, we need to restrict ourselves to reg+reg

59040

+ addressing. */

59041

if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))

59042

return false;

59043

break;

59044

@@ -5184,6 +6151,13 @@

59045

return false;

59046

break;

59047

59048

+ case SDmode:

59049

+ /* If we can do direct load/stores of SDmode, restrict it to reg+reg

59050

+ addressing for the LFIWZX and STFIWX instructions. */

59051

+ if (TARGET_NO_SDMODE_STACK)

59052

+ return false;

59053

+ break;

59054

+

59055

default:

59056

break;

59057

}

59058

@@ -5211,8 +6185,8 @@

59059

&& regnum <= LAST_VIRTUAL_POINTER_REGISTER);

59060

}

59061

59062

-/* Return true if memory accesses to OP are known to never straddle

59063

- a 32k boundary. */

59064

+/* Return true if a MODE sized memory accesses to OP plus OFFSET

59065

+ is known to not straddle a 32k boundary. */

59066

59067

static bool

59068

offsettable_ok_by_alignment (rtx op, HOST_WIDE_INT offset,

59069

@@ -5219,15 +6193,16 @@

59070

enum machine_mode mode)

59071

{

59072

tree decl, type;

59073

- unsigned HOST_WIDE_INT dsize, dalign;

59074

+ unsigned HOST_WIDE_INT dsize, dalign, lsb, mask;

59075

59076

if (GET_CODE (op) != SYMBOL_REF)

59077

return false;

59078

59079

+ dsize = GET_MODE_SIZE (mode);

59080

decl = SYMBOL_REF_DECL (op);

59081

if (!decl)

59082

{

59083

- if (GET_MODE_SIZE (mode) == 0)

59084

+ if (dsize == 0)

59085

return false;

59086

59087

/* -fsection-anchors loses the original SYMBOL_REF_DECL when

59088

@@ -5234,68 +6209,78 @@

59089

replacing memory addresses with an anchor plus offset. We

59090

could find the decl by rummaging around in the block->objects

59091

VEC for the given offset but that seems like too much work. */

59092

- dalign = 1;

59093

+ dalign = BITS_PER_UNIT;

59094

if (SYMBOL_REF_HAS_BLOCK_INFO_P (op)

59095

&& SYMBOL_REF_ANCHOR_P (op)

59096

&& SYMBOL_REF_BLOCK (op) != NULL)

59097

{

59098

struct object_block *block = SYMBOL_REF_BLOCK (op);

59099

- HOST_WIDE_INT lsb, mask;

59100

59101

- /* Given the alignment of the block.. */

59102

dalign = block->alignment;

59103

- mask = dalign / BITS_PER_UNIT - 1;

59104

-

59105

- /* ..and the combined offset of the anchor and any offset

59106

- to this block object.. */

59107

offset += SYMBOL_REF_BLOCK_OFFSET (op);

59108

- lsb = offset & -offset;

59109

+ }

59110

+ else if (CONSTANT_POOL_ADDRESS_P (op))

59111

+ {

59112

+ /* It would be nice to have get_pool_align().. */

59113

+ enum machine_mode cmode = get_pool_mode (op);

59114

59115

- /* ..find how many bits of the alignment we know for the

59116

- object. */

59117

- mask &= lsb - 1;

59118

- dalign = mask + 1;

59119

+ dalign = GET_MODE_ALIGNMENT (cmode);

59120

}

59121

- return dalign >= GET_MODE_SIZE (mode);

59122

}

59123

-

59124

- if (DECL_P (decl))

59125

+ else if (DECL_P (decl))

59126

{

59127

- if (TREE_CODE (decl) == FUNCTION_DECL)

59128

- return true;

59129

+ dalign = DECL_ALIGN (decl);

59130

59131

- if (!DECL_SIZE_UNIT (decl))

59132

- return false;

59133

+ if (dsize == 0)

59134

+ {

59135

+ /* Allow BLKmode when the entire object is known to not

59136

+ cross a 32k boundary. */

59137

+ if (!DECL_SIZE_UNIT (decl))

59138

+ return false;

59139

59140

- if (!host_integerp (DECL_SIZE_UNIT (decl), 1))

59141

- return false;

59142

+ if (!host_integerp (DECL_SIZE_UNIT (decl), 1))

59143

+ return false;

59144

59145

- dsize = tree_low_cst (DECL_SIZE_UNIT (decl), 1);

59146

- if (dsize > 32768)

59147

- return false;

59148

+ dsize = tree_low_cst (DECL_SIZE_UNIT (decl), 1);

59149

+ if (dsize > 32768)

59150

+ return false;

59151

59152

- dalign = DECL_ALIGN_UNIT (decl);

59153

- return dalign >= dsize;

59154

+ return dalign / BITS_PER_UNIT >= dsize;

59155

+ }

59156

}

59157

+ else

59158

+ {

59159

+ type = TREE_TYPE (decl);

59160

59161

- type = TREE_TYPE (decl);

59162

+ dalign = TYPE_ALIGN (type);

59163

+ if (CONSTANT_CLASS_P (decl))

59164

+ dalign = CONSTANT_ALIGNMENT (decl, dalign);

59165

+ else

59166

+ dalign = DATA_ALIGNMENT (decl, dalign);

59167

59168

- if (TREE_CODE (decl) == STRING_CST)

59169

- dsize = TREE_STRING_LENGTH (decl);

59170

- else if (TYPE_SIZE_UNIT (type)

59171

- && host_integerp (TYPE_SIZE_UNIT (type), 1))

59172

- dsize = tree_low_cst (TYPE_SIZE_UNIT (type), 1);

59173

- else

59174

- return false;

59175

- if (dsize > 32768)

59176

- return false;

59177

+ if (dsize == 0)

59178

+ {

59179

+ /* BLKmode, check the entire object. */

59180

+ if (TREE_CODE (decl) == STRING_CST)

59181

+ dsize = TREE_STRING_LENGTH (decl);

59182

+ else if (TYPE_SIZE_UNIT (type)

59183

+ && host_integerp (TYPE_SIZE_UNIT (type), 1))

59184

+ dsize = tree_low_cst (TYPE_SIZE_UNIT (type), 1);

59185

+ else

59186

+ return false;

59187

+ if (dsize > 32768)

59188

+ return false;

59189

59190

- dalign = TYPE_ALIGN (type);

59191

- if (CONSTANT_CLASS_P (decl))

59192

- dalign = CONSTANT_ALIGNMENT (decl, dalign);

59193

- else

59194

- dalign = DATA_ALIGNMENT (decl, dalign);

59195

- dalign /= BITS_PER_UNIT;

59196

+ return dalign / BITS_PER_UNIT >= dsize;

59197

+ }

59198

+ }

59199

+

59200

+ /* Find how many bits of the alignment we know for this access. */

59201

+ mask = dalign / BITS_PER_UNIT - 1;

59202

+ lsb = offset & -offset;

59203

+ mask &= lsb - 1;

59204

+ dalign = mask + 1;

59205

+

59206

return dalign >= dsize;

59207

}

59208

59209

@@ -5387,7 +6372,7 @@

59210

return false;

59211

if (!reg_offset_addressing_ok_p (mode))

59212

return virtual_stack_registers_memory_p (x);

59213

- if (legitimate_constant_pool_address_p (x, mode, strict))

59214

+ if (legitimate_constant_pool_address_p (x, mode, strict || lra_in_progress))

59215

return true;

59216

if (GET_CODE (XEXP (x, 1)) != CONST_INT)

59217

return false;

59218

@@ -5416,7 +6401,7 @@

59219

59220

/* If we are using VSX scalar loads, restrict ourselves to reg+reg

59221

addressing. */

59222

- if (mode == DFmode && VECTOR_MEM_VSX_P (DFmode))

59223

+ if (VECTOR_MEM_VSX_P (mode))

59224

return false;

59225

59226

if (!worst_case)

59227

@@ -5428,12 +6413,14 @@

59228

break;

59229

59230

case TFmode:

59231

- case TDmode:

59232

- case TImode:

59233

if (TARGET_E500_DOUBLE)

59234

return (SPE_CONST_OFFSET_OK (offset)

59235

&& SPE_CONST_OFFSET_OK (offset + 8));

59236

+ /* fall through */

59237

59238

+ case TDmode:

59239

+ case TImode:

59240

+ case PTImode:

59241

extra = 8;

59242

if (!worst_case)

59243

break;

59244

@@ -5526,9 +6513,21 @@

59245

59246

if (TARGET_ELF || TARGET_MACHO)

59247

{

59248

- if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)

59249

+ bool large_toc_ok;

59250

+

59251

+ if (DEFAULT_ABI == ABI_V4 && flag_pic)

59252

return false;

59253

- if (TARGET_TOC)

59254

+ /* LRA don't use LEGITIMIZE_RELOAD_ADDRESS as it usually calls

59255

+ push_reload from reload pass code. LEGITIMIZE_RELOAD_ADDRESS

59256

+ recognizes some LO_SUM addresses as valid although this

59257

+ function says opposite. In most cases, LRA through different

59258

+ transformations can generate correct code for address reloads.

59259

+ It can not manage only some LO_SUM cases. So we need to add

59260

+ code analogous to one in rs6000_legitimize_reload_address for

59261

+ LOW_SUM here saying that some addresses are still valid. */

59262

+ large_toc_ok = (lra_in_progress && TARGET_CMODEL != CMODEL_SMALL

59263

+ && small_toc_ref (x, VOIDmode));

59264

+ if (TARGET_TOC && ! large_toc_ok)

59265

return false;

59266

if (GET_MODE_NUNITS (mode) != 1)

59267

return false;

59268

@@ -5538,7 +6537,7 @@

59269

&& (mode == DFmode || mode == DDmode)))

59270

return false;

59271

59272

- return CONSTANT_P (x);

59273

+ return CONSTANT_P (x) || large_toc_ok;

59274

}

59275

59276

return false;

59277

@@ -5582,8 +6581,11 @@

59278

if (GET_CODE (x) == PLUS && XEXP (x, 1) == const0_rtx)

59279

return force_reg (Pmode, XEXP (x, 0));

59280

59281

+ /* For TImode with load/store quad, restrict addresses to just a single

59282

+ pointer, so it works with both GPRs and VSX registers. */

59283

/* Make sure both operands are registers. */

59284

- else if (GET_CODE (x) == PLUS)

59285

+ else if (GET_CODE (x) == PLUS

59286

+ && (mode != TImode || !TARGET_QUAD_MEMORY))

59287

return gen_rtx_PLUS (Pmode,

59288

force_reg (Pmode, XEXP (x, 0)),

59289

force_reg (Pmode, XEXP (x, 1)));

59290

@@ -5603,11 +6605,12 @@

59291

case TFmode:

59292

case TDmode:

59293

case TImode:

59294

+ case PTImode:

59295

/* As in legitimate_offset_address_p we do not assume

59296

worst-case. The mode here is just a hint as to the registers

59297

used. A TImode is usually in gprs, but may actually be in

59298

fprs. Leave worst-case scenario for reload to handle via

59299

- insn constraints. */

59300

+ insn constraints. PTImode is only GPRs. */

59301

extra = 8;

59302

break;

59303

default:

59304

@@ -6099,10 +7102,13 @@

59305

1, const0_rtx, Pmode);

59306

59307

r3 = gen_rtx_REG (Pmode, 3);

59308

- if (DEFAULT_ABI == ABI_AIX && TARGET_64BIT)

59309

- insn = gen_tls_gd_aix64 (r3, got, addr, tga, const0_rtx);

59310

- else if (DEFAULT_ABI == ABI_AIX && !TARGET_64BIT)

59311

- insn = gen_tls_gd_aix32 (r3, got, addr, tga, const0_rtx);

59312

+ if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)

59313

+ {

59314

+ if (TARGET_64BIT)

59315

+ insn = gen_tls_gd_aix64 (r3, got, addr, tga, const0_rtx);

59316

+ else

59317

+ insn = gen_tls_gd_aix32 (r3, got, addr, tga, const0_rtx);

59318

+ }

59319

else if (DEFAULT_ABI == ABI_V4)

59320

insn = gen_tls_gd_sysvsi (r3, got, addr, tga, const0_rtx);

59321

else

59322

@@ -6121,10 +7127,13 @@

59323

1, const0_rtx, Pmode);

59324

59325

r3 = gen_rtx_REG (Pmode, 3);

59326

- if (DEFAULT_ABI == ABI_AIX && TARGET_64BIT)

59327

- insn = gen_tls_ld_aix64 (r3, got, tga, const0_rtx);

59328

- else if (DEFAULT_ABI == ABI_AIX && !TARGET_64BIT)

59329

- insn = gen_tls_ld_aix32 (r3, got, tga, const0_rtx);

59330

+ if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)

59331

+ {

59332

+ if (TARGET_64BIT)

59333

+ insn = gen_tls_ld_aix64 (r3, got, tga, const0_rtx);

59334

+ else

59335

+ insn = gen_tls_ld_aix32 (r3, got, tga, const0_rtx);

59336

+ }

59337

else if (DEFAULT_ABI == ABI_V4)

59338

insn = gen_tls_ld_sysvsi (r3, got, tga, const0_rtx);

59339

else

59340

@@ -6239,7 +7248,6 @@

59341

&& ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (sym),

59342

get_pool_mode (sym)))

59343

|| (TARGET_CMODEL == CMODEL_MEDIUM

59344

- && !CONSTANT_POOL_ADDRESS_P (sym)

59345

&& SYMBOL_REF_LOCAL_P (sym)));

59346

}

59347

59348

@@ -6338,7 +7346,7 @@

59349

&& !(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode

59350

|| mode == DDmode || mode == TDmode

59351

|| mode == DImode))

59352

- && VECTOR_MEM_NONE_P (mode))

59353

+ && (!VECTOR_MODE_P (mode) || VECTOR_MEM_NONE_P (mode)))

59354

{

59355

HOST_WIDE_INT val = INTVAL (XEXP (x, 1));

59356

HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;

59357

@@ -6369,7 +7377,7 @@

59358

59359

if (GET_CODE (x) == SYMBOL_REF

59360

&& reg_offset_p

59361

- && VECTOR_MEM_NONE_P (mode)

59362

+ && (!VECTOR_MODE_P (mode) || VECTOR_MEM_NONE_P (mode))

59363

&& !SPE_VECTOR_MODE (mode)

59364

#if TARGET_MACHO

59365

&& DEFAULT_ABI == ABI_DARWIN

59366

@@ -6395,6 +7403,8 @@

59367

mem is sufficiently aligned. */

59368

&& mode != TFmode

59369

&& mode != TDmode

59370

+ && (mode != TImode || !TARGET_VSX_TIMODE)

59371

+ && mode != PTImode

59372

&& (mode != DImode || TARGET_POWERPC64)

59373

&& ((mode != DFmode && mode != DDmode) || TARGET_POWERPC64

59374

|| (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)))

59375

@@ -6515,15 +7525,9 @@

59376

return 0;

59377

if (legitimate_indirect_address_p (x, reg_ok_strict))

59378

return 1;

59379

- if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)

59380

- && !VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)

59381

- && !SPE_VECTOR_MODE (mode)

59382

- && mode != TFmode

59383

- && mode != TDmode

59384

- /* Restrict addressing for DI because of our SUBREG hackery. */

59385

- && !(TARGET_E500_DOUBLE

59386

- && (mode == DFmode || mode == DDmode || mode == DImode))

59387

- && TARGET_UPDATE

59388

+ if (TARGET_UPDATE

59389

+ && (GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)

59390

+ && mode_supports_pre_incdec_p (mode)

59391

&& legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))

59392

return 1;

59393

if (virtual_stack_registers_memory_p (x))

59394

@@ -6531,8 +7535,16 @@

59395

if (reg_offset_p && legitimate_small_data_p (mode, x))

59396

return 1;

59397

if (reg_offset_p

59398

- && legitimate_constant_pool_address_p (x, mode, reg_ok_strict))

59399

+ && legitimate_constant_pool_address_p (x, mode,

59400

+ reg_ok_strict || lra_in_progress))

59401

return 1;

59402

+ /* For TImode, if we have load/store quad and TImode in VSX registers, only

59403

+ allow register indirect addresses. This will allow the values to go in

59404

+ either GPRs or VSX registers without reloading. The vector types would

59405

+ tend to go into VSX registers, so we allow REG+REG, while TImode seems

59406

+ somewhat split, in that some uses are GPR based, and some VSX based. */

59407

+ if (mode == TImode && TARGET_QUAD_MEMORY && TARGET_VSX_TIMODE)

59408

+ return 0;

59409

/* If not REG_OK_STRICT (before reload) let pass any stack offset. */

59410

if (! reg_ok_strict

59411

&& reg_offset_p

59412

@@ -6544,8 +7556,7 @@

59413

return 1;

59414

if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict, false))

59415

return 1;

59416

- if (mode != TImode

59417

- && mode != TFmode

59418

+ if (mode != TFmode

59419

&& mode != TDmode

59420

&& ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)

59421

|| TARGET_POWERPC64

59422

@@ -6552,23 +7563,13 @@

59423

|| (mode != DFmode && mode != DDmode)

59424

|| (TARGET_E500_DOUBLE && mode != DDmode))

59425

&& (TARGET_POWERPC64 || mode != DImode)

59426

+ && (mode != TImode || VECTOR_MEM_VSX_P (TImode))

59427

+ && mode != PTImode

59428

&& !avoiding_indexed_address_p (mode)

59429

&& legitimate_indexed_address_p (x, reg_ok_strict))

59430

return 1;

59431

- if (GET_CODE (x) == PRE_MODIFY

59432

- && mode != TImode

59433

- && mode != TFmode

59434

- && mode != TDmode

59435

- && ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)

59436

- || TARGET_POWERPC64

59437

- || ((mode != DFmode && mode != DDmode) || TARGET_E500_DOUBLE))

59438

- && (TARGET_POWERPC64 || mode != DImode)

59439

- && !VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)

59440

- && !SPE_VECTOR_MODE (mode)

59441

- /* Restrict addressing for DI because of our SUBREG hackery. */

59442

- && !(TARGET_E500_DOUBLE

59443

- && (mode == DFmode || mode == DDmode || mode == DImode))

59444

- && TARGET_UPDATE

59445

+ if (TARGET_UPDATE && GET_CODE (x) == PRE_MODIFY

59446

+ && mode_supports_pre_modify_p (mode)

59447

&& legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)

59448

&& (rs6000_legitimate_offset_address_p (mode, XEXP (x, 1),

59449

reg_ok_strict, false)

59450

@@ -6589,10 +7590,13 @@

59451

bool ret = rs6000_legitimate_address_p (mode, x, reg_ok_strict);

59452

fprintf (stderr,

59453

"\nrs6000_legitimate_address_p: return = %s, mode = %s, "

59454

- "strict = %d, code = %s\n",

59455

+ "strict = %d, reload = %s, code = %s\n",

59456

ret ? "true" : "false",

59457

GET_MODE_NAME (mode),

59458

reg_ok_strict,

59459

+ (reload_completed

59460

+ ? "after"

59461

+ : (reload_in_progress ? "progress" : "before")),

59462

GET_RTX_NAME (GET_CODE (x)));

59463

debug_rtx (x);

59464

59465

@@ -6758,7 +7762,7 @@

59466

59467

/* The TOC register is not killed across calls in a way that is

59468

visible to the compiler. */

59469

- if (DEFAULT_ABI == ABI_AIX)

59470

+ if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)

59471

call_really_used_regs[2] = 0;

59472

59473

if (DEFAULT_ABI == ABI_V4

59474

@@ -6818,6 +7822,7 @@

59475

fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;

59476

}

59477

}

59478

+

59479

59480

/* Try to output insns to set TARGET equal to the constant C if it can

59481

be done in less than N insns. Do all computations in MODE.

59482

@@ -7006,7 +8011,7 @@

59483

}

59484

59485

/* Helper for the following. Get rid of [r+r] memory refs

59486

- in cases where it won't work (TImode, TFmode, TDmode). */

59487

+ in cases where it won't work (TImode, TFmode, TDmode, PTImode). */

59488

59489

static void

59490

rs6000_eliminate_indexed_memrefs (rtx operands[2])

59491

@@ -7031,6 +8036,131 @@

59492

copy_addr_to_reg (XEXP (operands[1], 0)));

59493

}

59494

59495

+/* Generate a vector of constants to permute MODE for a little-endian

59496

+ storage operation by swapping the two halves of a vector. */

59497

+static rtvec

59498

+rs6000_const_vec (enum machine_mode mode)

59499

+{

59500

+ int i, subparts;

59501

+ rtvec v;

59502

+

59503

+ switch (mode)

59504

+ {

59505

+ case V1TImode:

59506

+ subparts = 1;

59507

+ break;

59508

+ case V2DFmode:

59509

+ case V2DImode:

59510

+ subparts = 2;

59511

+ break;

59512

+ case V4SFmode:

59513

+ case V4SImode:

59514

+ subparts = 4;

59515

+ break;

59516

+ case V8HImode:

59517

+ subparts = 8;

59518

+ break;

59519

+ case V16QImode:

59520

+ subparts = 16;

59521

+ break;

59522

+ default:

59523

+ gcc_unreachable();

59524

+ }

59525

+

59526

+ v = rtvec_alloc (subparts);

59527

+

59528

+ for (i = 0; i < subparts / 2; ++i)

59529

+ RTVEC_ELT (v, i) = gen_rtx_CONST_INT (DImode, i + subparts / 2);

59530

+ for (i = subparts / 2; i < subparts; ++i)

59531

+ RTVEC_ELT (v, i) = gen_rtx_CONST_INT (DImode, i - subparts / 2);

59532

+

59533

+ return v;

59534

+}

59535

+

59536

+/* Generate a permute rtx that represents an lxvd2x, stxvd2x, or xxpermdi

59537

+ for a VSX load or store operation. */

59538

+rtx

59539

+rs6000_gen_le_vsx_permute (rtx source, enum machine_mode mode)

59540

+{

59541

+ rtx par = gen_rtx_PARALLEL (VOIDmode, rs6000_const_vec (mode));

59542

+ return gen_rtx_VEC_SELECT (mode, source, par);

59543

+}

59544

+

59545

+/* Emit a little-endian load from vector memory location SOURCE to VSX

59546

+ register DEST in mode MODE. The load is done with two permuting

59547

+ insn's that represent an lxvd2x and xxpermdi. */

59548

+void

59549

+rs6000_emit_le_vsx_load (rtx dest, rtx source, enum machine_mode mode)

59550

+{

59551

+ rtx tmp, permute_mem, permute_reg;

59552

+

59553

+ /* Use V2DImode to do swaps of types with 128-bit scalare parts (TImode,

59554

+ V1TImode). */

59555

+ if (mode == TImode || mode == V1TImode)

59556

+ {

59557

+ mode = V2DImode;

59558

+ dest = gen_lowpart (V2DImode, dest);

59559

+ source = adjust_address (source, V2DImode, 0);

59560

+ }

59561

+

59562

+ tmp = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (dest) : dest;

59563

+ permute_mem = rs6000_gen_le_vsx_permute (source, mode);

59564

+ permute_reg = rs6000_gen_le_vsx_permute (tmp, mode);

59565

+ emit_insn (gen_rtx_SET (VOIDmode, tmp, permute_mem));

59566

+ emit_insn (gen_rtx_SET (VOIDmode, dest, permute_reg));

59567

+}

59568

+

59569

+/* Emit a little-endian store to vector memory location DEST from VSX

59570

+ register SOURCE in mode MODE. The store is done with two permuting

59571

+ insn's that represent an xxpermdi and an stxvd2x. */

59572

+void

59573

+rs6000_emit_le_vsx_store (rtx dest, rtx source, enum machine_mode mode)

59574

+{

59575

+ rtx tmp, permute_src, permute_tmp;

59576

+

59577

+ /* Use V2DImode to do swaps of types with 128-bit scalare parts (TImode,

59578

+ V1TImode). */

59579

+ if (mode == TImode || mode == V1TImode)

59580

+ {

59581

+ mode = V2DImode;

59582

+ dest = adjust_address (dest, V2DImode, 0);

59583

+ source = gen_lowpart (V2DImode, source);

59584

+ }

59585

+

59586

+ tmp = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (source) : source;

59587

+ permute_src = rs6000_gen_le_vsx_permute (source, mode);

59588

+ permute_tmp = rs6000_gen_le_vsx_permute (tmp, mode);

59589

+ emit_insn (gen_rtx_SET (VOIDmode, tmp, permute_src));

59590

+ emit_insn (gen_rtx_SET (VOIDmode, dest, permute_tmp));

59591

+}

59592

+

59593

+/* Emit a sequence representing a little-endian VSX load or store,

59594

+ moving data from SOURCE to DEST in mode MODE. This is done

59595

+ separately from rs6000_emit_move to ensure it is called only

59596

+ during expand. LE VSX loads and stores introduced later are

59597

+ handled with a split. The expand-time RTL generation allows

59598

+ us to optimize away redundant pairs of register-permutes. */

59599

+void

59600

+rs6000_emit_le_vsx_move (rtx dest, rtx source, enum machine_mode mode)

59601

+{

59602

+ gcc_assert (!BYTES_BIG_ENDIAN

59603

+ && VECTOR_MEM_VSX_P (mode)

59604

+ && !gpr_or_gpr_p (dest, source)

59605

+ && (MEM_P (source) ^ MEM_P (dest)));

59606

+

59607

+ if (MEM_P (source))

59608

+ {

59609

+ gcc_assert (REG_P (dest) || GET_CODE (dest) == SUBREG);

59610

+ rs6000_emit_le_vsx_load (dest, source, mode);

59611

+ }

59612

+ else

59613

+ {

59614

+ if (!REG_P (source))

59615

+ source = force_reg (mode, source);

59616

+ rs6000_emit_le_vsx_store (dest, source, mode);

59617

+ }

59618

+}

59619

+

59620

/* Emit a move from SOURCE to DEST in mode MODE. */

59621

void

59622

rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)

59623

@@ -7149,8 +8279,71 @@

59624

cfun->machine->sdmode_stack_slot =

59625

eliminate_regs (cfun->machine->sdmode_stack_slot, VOIDmode, NULL_RTX);

59626

59627

+

59628

+ if (lra_in_progress

59629

+ && mode == SDmode

59630

+ && REG_P (operands[0]) && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER

59631

+ && reg_preferred_class (REGNO (operands[0])) == NO_REGS

59632

+ && (REG_P (operands[1])

59633

+ || (GET_CODE (operands[1]) == SUBREG

59634

+ && REG_P (SUBREG_REG (operands[1])))))

59635

+ {

59636

+ int regno = REGNO (GET_CODE (operands[1]) == SUBREG

59637

+ ? SUBREG_REG (operands[1]) : operands[1]);

59638

+ enum reg_class cl;

59639

+

59640

+ if (regno >= FIRST_PSEUDO_REGISTER)

59641

+ {

59642

+ cl = reg_preferred_class (regno);

59643

+ gcc_assert (cl != NO_REGS);

59644

+ regno = ira_class_hard_regs[cl][0];

59645

+ }

59646

+ if (FP_REGNO_P (regno))

59647

+ {

59648

+ if (GET_MODE (operands[0]) != DDmode)

59649

+ operands[0] = gen_rtx_SUBREG (DDmode, operands[0], 0);

59650

+ emit_insn (gen_movsd_store (operands[0], operands[1]));

59651

+ }

59652

+ else if (INT_REGNO_P (regno))

59653

+ emit_insn (gen_movsd_hardfloat (operands[0], operands[1]));

59654

+ else

59655

+ gcc_unreachable();

59656

+ return;

59657

+ }

59658

+ if (lra_in_progress

59659

+ && mode == SDmode

59660

+ && (REG_P (operands[0])

59661

+ || (GET_CODE (operands[0]) == SUBREG

59662

+ && REG_P (SUBREG_REG (operands[0]))))

59663

+ && REG_P (operands[1]) && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER

59664

+ && reg_preferred_class (REGNO (operands[1])) == NO_REGS)

59665

+ {

59666

+ int regno = REGNO (GET_CODE (operands[0]) == SUBREG

59667

+ ? SUBREG_REG (operands[0]) : operands[0]);

59668

+ enum reg_class cl;

59669

+

59670

+ if (regno >= FIRST_PSEUDO_REGISTER)

59671

+ {

59672

+ cl = reg_preferred_class (regno);

59673

+ gcc_assert (cl != NO_REGS);

59674

+ regno = ira_class_hard_regs[cl][0];

59675

+ }

59676

+ if (FP_REGNO_P (regno))

59677

+ {

59678

+ if (GET_MODE (operands[1]) != DDmode)

59679

+ operands[1] = gen_rtx_SUBREG (DDmode, operands[1], 0);

59680

+ emit_insn (gen_movsd_load (operands[0], operands[1]));

59681

+ }

59682

+ else if (INT_REGNO_P (regno))

59683

+ emit_insn (gen_movsd_hardfloat (operands[0], operands[1]));

59684

+ else

59685

+ gcc_unreachable();

59686

+ return;

59687

+ }

59688

+

59689

if (reload_in_progress

59690

&& mode == SDmode

59691

+ && cfun->machine->sdmode_stack_slot != NULL_RTX

59692

&& MEM_P (operands[0])

59693

&& rtx_equal_p (operands[0], cfun->machine->sdmode_stack_slot)

59694

&& REG_P (operands[1]))

59695

@@ -7163,7 +8356,9 @@

59696

}

59697

else if (INT_REGNO_P (REGNO (operands[1])))

59698

{

59699

- rtx mem = adjust_address_nv (operands[0], mode, 4);

59700

+ rtx mem = operands[0];

59701

+ if (BYTES_BIG_ENDIAN)

59702

+ mem = adjust_address_nv (mem, mode, 4);

59703

mem = eliminate_regs (mem, VOIDmode, NULL_RTX);

59704

emit_insn (gen_movsd_hardfloat (mem, operands[1]));

59705

}

59706

@@ -7175,6 +8370,7 @@

59707

&& mode == SDmode

59708

&& REG_P (operands[0])

59709

&& MEM_P (operands[1])

59710

+ && cfun->machine->sdmode_stack_slot != NULL_RTX

59711

&& rtx_equal_p (operands[1], cfun->machine->sdmode_stack_slot))

59712

{

59713

if (FP_REGNO_P (REGNO (operands[0])))

59714

@@ -7185,7 +8381,9 @@

59715

}

59716

else if (INT_REGNO_P (REGNO (operands[0])))

59717

{

59718

- rtx mem = adjust_address_nv (operands[1], mode, 4);

59719

+ rtx mem = operands[1];

59720

+ if (BYTES_BIG_ENDIAN)

59721

+ mem = adjust_address_nv (mem, mode, 4);

59722

mem = eliminate_regs (mem, VOIDmode, NULL_RTX);

59723

emit_insn (gen_movsd_hardfloat (operands[0], mem));

59724

}

59725

@@ -7230,6 +8428,7 @@

59726

case V1DImode:

59727

case V2DFmode:

59728

case V2DImode:

59729

+ case V1TImode:

59730

if (CONSTANT_P (operands[1])

59731

&& !easy_vector_constant (operands[1], mode))

59732

operands[1] = force_const_mem (mode, operands[1]);

59733

@@ -7388,6 +8587,11 @@

59734

break;

59735

59736

case TImode:

59737

+ if (!VECTOR_MEM_VSX_P (TImode))

59738

+ rs6000_eliminate_indexed_memrefs (operands);

59739

+ break;

59740

+

59741

+ case PTImode:

59742

rs6000_eliminate_indexed_memrefs (operands);

59743

break;

59744

59745

@@ -7426,18 +8630,231 @@

59746

}

59747

59748

/* Nonzero if we can use a floating-point register to pass this arg. */

59749

-#define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \

59750

+#define USE_FP_FOR_ARG_P(CUM,MODE) \

59751

(SCALAR_FLOAT_MODE_P (MODE) \

59752

&& (CUM)->fregno <= FP_ARG_MAX_REG \

59753

&& TARGET_HARD_FLOAT && TARGET_FPRS)

59754

59755

/* Nonzero if we can use an AltiVec register to pass this arg. */

59756

-#define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \

59757

+#define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,NAMED) \

59758

(ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \

59759

&& (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \

59760

&& TARGET_ALTIVEC_ABI \

59761

&& (NAMED))

59762

59763

+/* Walk down the type tree of TYPE counting consecutive base elements.

59764

+ If *MODEP is VOIDmode, then set it to the first valid floating point

59765

+ or vector type. If a non-floating point or vector type is found, or

59766

+ if a floating point or vector type that doesn't match a non-VOIDmode

59767

+ *MODEP is found, then return -1, otherwise return the count in the

59768

+ sub-tree. */

59769

+

59770

+static int

59771

+rs6000_aggregate_candidate (const_tree type, enum machine_mode *modep)

59772

+{

59773

+ enum machine_mode mode;

59774

+ HOST_WIDE_INT size;

59775

+

59776

+ switch (TREE_CODE (type))

59777

+ {

59778

+ case REAL_TYPE:

59779

+ mode = TYPE_MODE (type);

59780

+ if (!SCALAR_FLOAT_MODE_P (mode))

59781

+ return -1;

59782

+

59783

+ if (*modep == VOIDmode)

59784

+ *modep = mode;

59785

+

59786

+ if (*modep == mode)

59787

+ return 1;

59788

+

59789

+ break;

59790

+

59791

+ case COMPLEX_TYPE:

59792

+ mode = TYPE_MODE (TREE_TYPE (type));

59793

+ if (!SCALAR_FLOAT_MODE_P (mode))

59794

+ return -1;

59795

+

59796

+ if (*modep == VOIDmode)

59797

+ *modep = mode;

59798

+

59799

+ if (*modep == mode)

59800

+ return 2;

59801

+

59802

+ break;

59803

+

59804

+ case VECTOR_TYPE:

59805

+ if (!TARGET_ALTIVEC_ABI || !TARGET_ALTIVEC)

59806

+ return -1;

59807

+

59808

+ /* Use V4SImode as representative of all 128-bit vector types. */

59809

+ size = int_size_in_bytes (type);

59810

+ switch (size)

59811

+ {

59812

+ case 16:

59813

+ mode = V4SImode;

59814

+ break;

59815

+ default:

59816

+ return -1;

59817

+ }

59818

+

59819

+ if (*modep == VOIDmode)

59820

+ *modep = mode;

59821

+

59822

+ /* Vector modes are considered to be opaque: two vectors are

59823

+ equivalent for the purposes of being homogeneous aggregates

59824

+ if they are the same size. */

59825

+ if (*modep == mode)

59826

+ return 1;

59827

+

59828

+ break;

59829

+

59830

+ case ARRAY_TYPE:

59831

+ {

59832

+ int count;

59833

+ tree index = TYPE_DOMAIN (type);

59834

+

59835

+ /* Can't handle incomplete types. */

59836

+ if (!COMPLETE_TYPE_P (type))

59837

+ return -1;

59838

+

59839

+ count = rs6000_aggregate_candidate (TREE_TYPE (type), modep);

59840

+ if (count == -1

59841

+ || !index

59842

+ || !TYPE_MAX_VALUE (index)

59843

+ || !host_integerp (TYPE_MAX_VALUE (index), 1)

59844

+ || !TYPE_MIN_VALUE (index)

59845

+ || !host_integerp (TYPE_MIN_VALUE (index), 1)

59846

+ || count < 0)

59847

+ return -1;

59848

+

59849

+ count *= (1 + tree_low_cst (TYPE_MAX_VALUE (index), 1)

59850

+ - tree_low_cst (TYPE_MIN_VALUE (index), 1));

59851

+

59852

+ /* There must be no padding. */

59853

+ if (!host_integerp (TYPE_SIZE (type), 1)

59854

+ || (tree_low_cst (TYPE_SIZE (type), 1)

59855

+ != count * GET_MODE_BITSIZE (*modep)))

59856

+ return -1;

59857

+

59858

+ return count;

59859

+ }

59860

+

59861

+ case RECORD_TYPE:

59862

+ {

59863

+ int count = 0;

59864

+ int sub_count;

59865

+ tree field;

59866

+

59867

+ /* Can't handle incomplete types. */

59868

+ if (!COMPLETE_TYPE_P (type))

59869

+ return -1;

59870

+

59871

+ for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))

59872

+ {

59873

+ if (TREE_CODE (field) != FIELD_DECL)

59874

+ continue;

59875

+

59876

+ sub_count = rs6000_aggregate_candidate (TREE_TYPE (field), modep);

59877

+ if (sub_count < 0)

59878

+ return -1;

59879

+ count += sub_count;

59880

+ }

59881

+

59882

+ /* There must be no padding. */

59883

+ if (!host_integerp (TYPE_SIZE (type), 1)

59884

+ || (tree_low_cst (TYPE_SIZE (type), 1)

59885

+ != count * GET_MODE_BITSIZE (*modep)))

59886

+ return -1;

59887

+

59888

+ return count;

59889

+ }

59890

+

59891

+ case UNION_TYPE:

59892

+ case QUAL_UNION_TYPE:

59893

+ {

59894

+ /* These aren't very interesting except in a degenerate case. */

59895

+ int count = 0;

59896

+ int sub_count;

59897

+ tree field;

59898

+

59899

+ /* Can't handle incomplete types. */

59900

+ if (!COMPLETE_TYPE_P (type))

59901

+ return -1;

59902

+

59903

+ for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))

59904

+ {

59905

+ if (TREE_CODE (field) != FIELD_DECL)

59906

+ continue;

59907

+

59908

+ sub_count = rs6000_aggregate_candidate (TREE_TYPE (field), modep);

59909

+ if (sub_count < 0)

59910

+ return -1;

59911

+ count = count > sub_count ? count : sub_count;

59912

+ }

59913

+

59914

+ /* There must be no padding. */

59915

+ if (!host_integerp (TYPE_SIZE (type), 1)

59916

+ || (tree_low_cst (TYPE_SIZE (type), 1)

59917

+ != count * GET_MODE_BITSIZE (*modep)))

59918

+ return -1;

59919

+

59920

+ return count;

59921

+ }

59922

+

59923

+ default:

59924

+ break;

59925

+ }

59926

+

59927

+ return -1;

59928

+}

59929

+

59930

+/* If an argument, whose type is described by TYPE and MODE, is a homogeneous

59931

+ float or vector aggregate that shall be passed in FP/vector registers

59932

+ according to the ELFv2 ABI, return the homogeneous element mode in

59933

+ *ELT_MODE and the number of elements in *N_ELTS, and return TRUE.

59934

+

59935

+ Otherwise, set *ELT_MODE to MODE and *N_ELTS to 1, and return FALSE. */

59936

+

59937

+static bool

59938

+rs6000_discover_homogeneous_aggregate (enum machine_mode mode, const_tree type,

59939

+ enum machine_mode *elt_mode,

59940

+ int *n_elts)

59941

+{

59942

+ /* Note that we do not accept complex types at the top level as

59943

+ homogeneous aggregates; these types are handled via the

59944

+ targetm.calls.split_complex_arg mechanism. Complex types

59945

+ can be elements of homogeneous aggregates, however. */

59946

+ if (DEFAULT_ABI == ABI_ELFv2 && type && AGGREGATE_TYPE_P (type))

59947

+ {

59948

+ enum machine_mode field_mode = VOIDmode;

59949

+ int field_count = rs6000_aggregate_candidate (type, &field_mode);

59950

+

59951

+ if (field_count > 0)

59952

+ {

59953

+ int n_regs = (SCALAR_FLOAT_MODE_P (field_mode)?

59954

+ (GET_MODE_SIZE (field_mode) + 7) >> 3 : 1);

59955

+

59956

+ /* The ELFv2 ABI allows homogeneous aggregates to occupy

59957

+ up to AGGR_ARG_NUM_REG registers. */

59958

+ if (field_count * n_regs <= AGGR_ARG_NUM_REG)

59959

+ {

59960

+ if (elt_mode)

59961

+ *elt_mode = field_mode;

59962

+ if (n_elts)

59963

+ *n_elts = field_count;

59964

+ return true;

59965

+ }

59966

+ }

59967

+ }

59968

+

59969

+ if (elt_mode)

59970

+ *elt_mode = mode;

59971

+ if (n_elts)

59972

+ *n_elts = 1;

59973

+ return false;

59974

+}

59975

+

59976

/* Return a nonzero value to say to return the function value in

59977

memory, just as large structures are always returned. TYPE will be

59978

the data type of the value, and FNTYPE will be the type of the

59979

@@ -7490,6 +8907,16 @@

59980

/* Otherwise fall through to more conventional ABI rules. */

59981

}

59982

59983

+ /* The ELFv2 ABI returns homogeneous VFP aggregates in registers */

59984

+ if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (type), type,

59985

+ NULL, NULL))

59986

+ return false;

59987

+

59988

+ /* The ELFv2 ABI returns aggregates up to 16B in registers */

59989

+ if (DEFAULT_ABI == ABI_ELFv2 && AGGREGATE_TYPE_P (type)

59990

+ && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) <= 16)

59991

+ return false;

59992

+

59993

if (AGGREGATE_TYPE_P (type)

59994

&& (aix_struct_return

59995

|| (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))

59996

@@ -7521,6 +8948,19 @@

59997

return false;

59998

}

59999

60000

+/* Specify whether values returned in registers should be at the most

60001

+ significant end of a register. We want aggregates returned by

60002

+ value to match the way aggregates are passed to functions. */

60003

+

60004

+static bool

60005

+rs6000_return_in_msb (const_tree valtype)

60006

+{

60007

+ return (DEFAULT_ABI == ABI_ELFv2

60008

+ && BYTES_BIG_ENDIAN

60009

+ && AGGREGATE_TYPE_P (valtype)

60010

+ && FUNCTION_ARG_PADDING (TYPE_MODE (valtype), valtype) == upward);

60011

+}

60012

+

60013

#ifdef HAVE_AS_GNU_ATTRIBUTE

60014

/* Return TRUE if a call to function FNDECL may be one that

60015

potentially affects the function calling ABI of the object file. */

60016

@@ -7657,7 +9097,7 @@

60017

static bool

60018

rs6000_must_pass_in_stack (enum machine_mode mode, const_tree type)

60019

{

60020

- if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)

60021

+ if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 || TARGET_64BIT)

60022

return must_pass_in_stack_var_size (mode, type);

60023

else

60024

return must_pass_in_stack_var_size_or_pad (mode, type);

60025

@@ -7738,6 +9178,11 @@

60026

static unsigned int

60027

rs6000_function_arg_boundary (enum machine_mode mode, const_tree type)

60028

{

60029

+ enum machine_mode elt_mode;

60030

+ int n_elts;

60031

+

60032

+ rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);

60033

+

60034

if (DEFAULT_ABI == ABI_V4

60035

&& (GET_MODE_SIZE (mode) == 8

60036

|| (TARGET_HARD_FLOAT

60037

@@ -7749,12 +9194,13 @@

60038

&& int_size_in_bytes (type) >= 8

60039

&& int_size_in_bytes (type) < 16))

60040

return 64;

60041

- else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode)

60042

+ else if (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode)

60043

|| (type && TREE_CODE (type) == VECTOR_TYPE

60044

&& int_size_in_bytes (type) >= 16))

60045

return 128;

60046

- else if (TARGET_MACHO

60047

- && rs6000_darwin64_abi

60048

+ else if (((TARGET_MACHO && rs6000_darwin64_abi)

60049

+ || DEFAULT_ABI == ABI_ELFv2

60050

+ || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm))

60051

&& mode == BLKmode

60052

&& type && TYPE_ALIGN (type) > 64)

60053

return 128;

60054

@@ -7762,6 +9208,16 @@

60055

return PARM_BOUNDARY;

60056

}

60057

60058

+/* The offset in words to the start of the parameter save area. */

60059

+

60060

+static unsigned int

60061

+rs6000_parm_offset (void)

60062

+{

60063

+ return (DEFAULT_ABI == ABI_V4 ? 2

60064

+ : DEFAULT_ABI == ABI_ELFv2 ? 4

60065

+ : 6);

60066

+}

60067

+

60068

/* For a function parm of MODE and TYPE, return the starting word in

60069

the parameter area. NWORDS of the parameter area are already used. */

60070

60071

@@ -7770,11 +9226,9 @@

60072

unsigned int nwords)

60073

{

60074

unsigned int align;

60075

- unsigned int parm_offset;

60076

60077

align = rs6000_function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;

60078

- parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;

60079

- return nwords + (-(parm_offset + nwords) & align);

60080

+ return nwords + (-(rs6000_parm_offset () + nwords) & align);

60081

}

60082

60083

/* Compute the size (in words) of a function argument. */

60084

@@ -7881,7 +9335,7 @@

60085

60086

if (TREE_CODE (ftype) == RECORD_TYPE)

60087

rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);

60088

- else if (USE_FP_FOR_ARG_P (cum, mode, ftype))

60089

+ else if (USE_FP_FOR_ARG_P (cum, mode))

60090

{

60091

unsigned n_fpregs = (GET_MODE_SIZE (mode) + 7) >> 3;

60092

rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);

60093

@@ -7922,7 +9376,7 @@

60094

else

60095

cum->words += n_fpregs;

60096

}

60097

- else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))

60098

+ else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, 1))

60099

{

60100

rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);

60101

cum->vregno++;

60102

@@ -7959,6 +9413,11 @@

60103

rs6000_function_arg_advance_1 (CUMULATIVE_ARGS *cum, enum machine_mode mode,

60104

const_tree type, bool named, int depth)

60105

{

60106

+ enum machine_mode elt_mode;

60107

+ int n_elts;

60108

+

60109

+ rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);

60110

+

60111

/* Only tick off an argument if we're not recursing. */

60112

if (depth == 0)

60113

cum->nargs_prototype--;

60114

@@ -7979,15 +9438,16 @@

60115

#endif

60116

60117

if (TARGET_ALTIVEC_ABI

60118

- && (ALTIVEC_OR_VSX_VECTOR_MODE (mode)

60119

+ && (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode)

60120

|| (type && TREE_CODE (type) == VECTOR_TYPE

60121

&& int_size_in_bytes (type) == 16)))

60122

{

60123

bool stack = false;

60124

60125

- if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))

60126

+ if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))

60127

{

60128

- cum->vregno++;

60129

+ cum->vregno += n_elts;

60130

+

60131

if (!TARGET_ALTIVEC)

60132

error ("cannot pass argument in vector register because"

60133

" altivec instructions are disabled, use -maltivec"

60134

@@ -7996,7 +9456,8 @@

60135

/* PowerPC64 Linux and AIX allocate GPRs for a vector argument

60136

even if it is going to be passed in a vector register.

60137

Darwin does the same for variable-argument functions. */

60138

- if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)

60139

+ if (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)

60140

+ && TARGET_64BIT)

60141

|| (cum->stdarg && DEFAULT_ABI != ABI_V4))

60142

stack = true;

60143

}

60144

@@ -8007,15 +9468,13 @@

60145

{

60146

int align;

60147

60148

- /* Vector parameters must be 16-byte aligned. This places

60149

- them at 2 mod 4 in terms of words in 32-bit mode, since

60150

- the parameter save area starts at offset 24 from the

60151

- stack. In 64-bit mode, they just have to start on an

60152

- even word, since the parameter save area is 16-byte

60153

- aligned. Space for GPRs is reserved even if the argument

60154

- will be passed in memory. */

60155

+ /* Vector parameters must be 16-byte aligned. In 32-bit

60156

+ mode this means we need to take into account the offset

60157

+ to the parameter save area. In 64-bit mode, they just

60158

+ have to start on an even word, since the parameter save

60159

+ area is 16-byte aligned. */

60160

if (TARGET_32BIT)

60161

- align = (2 - cum->words) & 3;

60162

+ align = -(rs6000_parm_offset () + cum->words) & 3;

60163

else

60164

align = cum->words & 1;

60165

cum->words += align + rs6000_arg_size (mode, type);

60166

@@ -8140,15 +9599,15 @@

60167

60168

cum->words = align_words + n_words;

60169

60170

- if (SCALAR_FLOAT_MODE_P (mode)

60171

+ if (SCALAR_FLOAT_MODE_P (elt_mode)

60172

&& TARGET_HARD_FLOAT && TARGET_FPRS)

60173

{

60174

/* _Decimal128 must be passed in an even/odd float register pair.

60175

This assumes that the register number is odd when fregno is

60176

odd. */

60177

- if (mode == TDmode && (cum->fregno % 2) == 1)

60178

+ if (elt_mode == TDmode && (cum->fregno % 2) == 1)

60179

cum->fregno++;

60180

- cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;

60181

+ cum->fregno += n_elts * ((GET_MODE_SIZE (elt_mode) + 7) >> 3);

60182

}

60183

60184

if (TARGET_DEBUG_ARG)

60185

@@ -8358,7 +9817,7 @@

60186

60187

if (TREE_CODE (ftype) == RECORD_TYPE)

60188

rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);

60189

- else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))

60190

+ else if (cum->named && USE_FP_FOR_ARG_P (cum, mode))

60191

{

60192

unsigned n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;

60193

#if 0

60194

@@ -8386,7 +9845,7 @@

60195

if (mode == TFmode || mode == TDmode)

60196

cum->fregno++;

60197

}

60198

- else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))

60199

+ else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, 1))

60200

{

60201

rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);

60202

rvec[(*k)++]

60203

@@ -8503,6 +9962,84 @@

60204

return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));

60205

}

60206

60207

+/* We have an argument of MODE and TYPE that goes into FPRs or VRs,

60208

+ but must also be copied into the parameter save area starting at

60209

+ offset ALIGN_WORDS. Fill in RVEC with the elements corresponding

60210

+ to the GPRs and/or memory. Return the number of elements used. */

60211

+

60212

+static int

60213

+rs6000_psave_function_arg (enum machine_mode mode, const_tree type,

60214

+ int align_words, rtx *rvec)

60215

+{

60216

+ int k = 0;

60217

+

60218

+ if (align_words < GP_ARG_NUM_REG)

60219

+ {

60220

+ int n_words = rs6000_arg_size (mode, type);

60221

+

60222

+ if (align_words + n_words > GP_ARG_NUM_REG

60223

+ || mode == BLKmode

60224

+ || (TARGET_32BIT && TARGET_POWERPC64))

60225

+ {

60226

+ /* If this is partially on the stack, then we only

60227

+ include the portion actually in registers here. */

60228

+ enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;

60229

+ int i = 0;

60230

+

60231

+ if (align_words + n_words > GP_ARG_NUM_REG)

60232

+ {

60233

+ /* Not all of the arg fits in gprs. Say that it goes in memory

60234

+ too, using a magic NULL_RTX component. Also see comment in

60235

+ rs6000_mixed_function_arg for why the normal

60236

+ function_arg_partial_nregs scheme doesn't work in this case. */

60237

+ rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);

60238

+ }

60239

+

60240

+ do

60241

+ {

60242

+ rtx r = gen_rtx_REG (rmode, GP_ARG_MIN_REG + align_words);

60243

+ rtx off = GEN_INT (i++ * GET_MODE_SIZE (rmode));

60244

+ rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);

60245

+ }

60246

+ while (++align_words < GP_ARG_NUM_REG && --n_words != 0);

60247

+ }

60248

+ else

60249

+ {

60250

+ /* The whole arg fits in gprs. */

60251

+ rtx r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);

60252

+ rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);

60253

+ }

60254

+ }

60255

+ else

60256

+ {

60257

+ /* It's entirely in memory. */

60258

+ rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);

60259

+ }

60260

+

60261

+ return k;

60262

+}

60263

+

60264

+/* RVEC is a vector of K components of an argument of mode MODE.

60265

+ Construct the final function_arg return value from it. */

60266

+

60267

+static rtx

60268

+rs6000_finish_function_arg (enum machine_mode mode, rtx *rvec, int k)

60269

+{

60270

+ gcc_assert (k >= 1);

60271

+

60272

+ /* Avoid returning a PARALLEL in the trivial cases. */

60273

+ if (k == 1)

60274

+ {

60275

+ if (XEXP (rvec[0], 0) == NULL_RTX)

60276

+ return NULL_RTX;

60277

+

60278

+ if (GET_MODE (XEXP (rvec[0], 0)) == mode)

60279

+ return XEXP (rvec[0], 0);

60280

+ }

60281

+

60282

+ return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));

60283

+}

60284

+

60285

/* Determine where to put an argument to a function.

60286

Value is zero to push the argument on the stack,

60287

or a hard register in which to store the argument.

60288

@@ -8537,6 +10074,8 @@

60289

{

60290

CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);

60291

enum rs6000_abi abi = DEFAULT_ABI;

60292

+ enum machine_mode elt_mode;

60293

+ int n_elts;

60294

60295

/* Return a marker to indicate whether CR1 needs to set or clear the

60296

bit that V.4 uses to say fp args were passed in registers.

60297

@@ -8563,6 +10102,8 @@

60298

return GEN_INT (cum->call_cookie & ~CALL_LIBCALL);

60299

}

60300

60301

+ rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);

60302

+

60303

if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))

60304

{

60305

rtx rslt = rs6000_darwin64_record_arg (cum, type, named, /*retval= */false);

60306

@@ -8571,33 +10112,30 @@

60307

/* Else fall through to usual handling. */

60308

}

60309

60310

- if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))

60311

- if (TARGET_64BIT && ! cum->prototype)

60312

- {

60313

- /* Vector parameters get passed in vector register

60314

- and also in GPRs or memory, in absence of prototype. */

60315

- int align_words;

60316

- rtx slot;

60317

- align_words = (cum->words + 1) & ~1;

60318

+ if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))

60319

+ {

60320

+ rtx rvec[GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + 1];

60321

+ rtx r, off;

60322

+ int i, k = 0;

60323

60324

- if (align_words >= GP_ARG_NUM_REG)

60325

- {

60326

- slot = NULL_RTX;

60327

- }

60328

- else

60329

- {

60330

- slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);

60331

- }

60332

- return gen_rtx_PARALLEL (mode,

60333

- gen_rtvec (2,

60334

- gen_rtx_EXPR_LIST (VOIDmode,

60335

- slot, const0_rtx),

60336

- gen_rtx_EXPR_LIST (VOIDmode,

60337

- gen_rtx_REG (mode, cum->vregno),

60338

- const0_rtx)));

60339

- }

60340

- else

60341

- return gen_rtx_REG (mode, cum->vregno);

60342

+ /* Do we also need to pass this argument in the parameter

60343

+ save area? */

60344

+ if (TARGET_64BIT && ! cum->prototype)

60345

+ {

60346

+ int align_words = (cum->words + 1) & ~1;

60347

+ k = rs6000_psave_function_arg (mode, type, align_words, rvec);

60348

+ }

60349

+

60350

+ /* Describe where this argument goes in the vector registers. */

60351

+ for (i = 0; i < n_elts && cum->vregno + i <= ALTIVEC_ARG_MAX_REG; i++)

60352

+ {

60353

+ r = gen_rtx_REG (elt_mode, cum->vregno + i);

60354

+ off = GEN_INT (i * GET_MODE_SIZE (elt_mode));

60355

+ rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);

60356

+ }

60357

+

60358

+ return rs6000_finish_function_arg (mode, rvec, k);

60359

+ }

60360

else if (TARGET_ALTIVEC_ABI

60361

&& (ALTIVEC_OR_VSX_VECTOR_MODE (mode)

60362

|| (type && TREE_CODE (type) == VECTOR_TYPE

60363

@@ -8612,13 +10150,13 @@

60364

int align, align_words, n_words;

60365

enum machine_mode part_mode;

60366

60367

- /* Vector parameters must be 16-byte aligned. This places them at

60368

- 2 mod 4 in terms of words in 32-bit mode, since the parameter

60369

- save area starts at offset 24 from the stack. In 64-bit mode,

60370

- they just have to start on an even word, since the parameter

60371

- save area is 16-byte aligned. */

60372

+ /* Vector parameters must be 16-byte aligned. In 32-bit

60373

+ mode this means we need to take into account the offset

60374

+ to the parameter save area. In 64-bit mode, they just

60375

+ have to start on an even word, since the parameter save

60376

+ area is 16-byte aligned. */

60377

if (TARGET_32BIT)

60378

- align = (2 - cum->words) & 3;

60379

+ align = -(rs6000_parm_offset () + cum->words) & 3;

60380

else

60381

align = cum->words & 1;

60382

align_words = cum->words + align;

60383

@@ -8696,92 +10234,44 @@

60384

60385

/* _Decimal128 must be passed in an even/odd float register pair.

60386

This assumes that the register number is odd when fregno is odd. */

60387

- if (mode == TDmode && (cum->fregno % 2) == 1)

60388

+ if (elt_mode == TDmode && (cum->fregno % 2) == 1)

60389

cum->fregno++;

60390

60391

- if (USE_FP_FOR_ARG_P (cum, mode, type))

60392

+ if (USE_FP_FOR_ARG_P (cum, elt_mode))

60393

{

60394

- rtx rvec[GP_ARG_NUM_REG + 1];

60395

- rtx r;

60396

- int k;

60397

- bool needs_psave;

60398

- enum machine_mode fmode = mode;

60399

- unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;

60400

+ rtx rvec[GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + 1];

60401

+ rtx r, off;

60402

+ int i, k = 0;

60403

+ unsigned long n_fpreg = (GET_MODE_SIZE (elt_mode) + 7) >> 3;

60404

60405

- if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)

60406

- {

60407

- /* Currently, we only ever need one reg here because complex

60408

- doubles are split. */

60409

- gcc_assert (cum->fregno == FP_ARG_MAX_REG

60410

- && (fmode == TFmode || fmode == TDmode));

60411

+ /* Do we also need to pass this argument in the parameter

60412

+ save area? */

60413

+ if (type && (cum->nargs_prototype <= 0

60414

+ || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)

60415

+ && TARGET_XL_COMPAT

60416

+ && align_words >= GP_ARG_NUM_REG)))

60417

+ k = rs6000_psave_function_arg (mode, type, align_words, rvec);

60418

60419

- /* Long double or _Decimal128 split over regs and memory. */

60420

- fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode;

60421

- }

60422

-

60423

- /* Do we also need to pass this arg in the parameter save

60424

- area? */

60425

- needs_psave = (type

60426

- && (cum->nargs_prototype <= 0

60427

- || (DEFAULT_ABI == ABI_AIX

60428

- && TARGET_XL_COMPAT

60429

- && align_words >= GP_ARG_NUM_REG)));

60430

-

60431

- if (!needs_psave && mode == fmode)

60432

- return gen_rtx_REG (fmode, cum->fregno);

60433

-

60434

- k = 0;

60435

- if (needs_psave)

60436

+ /* Describe where this argument goes in the fprs. */

60437

+ for (i = 0; i < n_elts

60438

+ && cum->fregno + i * n_fpreg <= FP_ARG_MAX_REG; i++)

60439

{

60440

- /* Describe the part that goes in gprs or the stack.

60441

- This piece must come first, before the fprs. */

60442

- if (align_words < GP_ARG_NUM_REG)

60443

+ /* Check if the argument is split over registers and memory.

60444

+ This can only ever happen for long double or _Decimal128;

60445

+ complex types are handled via split_complex_arg. */

60446

+ enum machine_mode fmode = elt_mode;

60447

+ if (cum->fregno + (i + 1) * n_fpreg > FP_ARG_MAX_REG + 1)

60448

{

60449

- unsigned long n_words = rs6000_arg_size (mode, type);

60450

+ gcc_assert (fmode == TFmode || fmode == TDmode);

60451

+ fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode;

60452

+ }

60453

60454

- if (align_words + n_words > GP_ARG_NUM_REG

60455

- || (TARGET_32BIT && TARGET_POWERPC64))

60456

- {

60457

- /* If this is partially on the stack, then we only

60458

- include the portion actually in registers here. */

60459

- enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;

60460

- rtx off;

60461

- int i = 0;

60462

- if (align_words + n_words > GP_ARG_NUM_REG)

60463

- /* Not all of the arg fits in gprs. Say that it

60464

- goes in memory too, using a magic NULL_RTX

60465

- component. Also see comment in

60466

- rs6000_mixed_function_arg for why the normal

60467

- function_arg_partial_nregs scheme doesn't work

60468

- in this case. */

60469

- rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,

60470

- const0_rtx);

60471

- do

60472

- {

60473

- r = gen_rtx_REG (rmode,

60474

- GP_ARG_MIN_REG + align_words);

60475

- off = GEN_INT (i++ * GET_MODE_SIZE (rmode));

60476

- rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);

60477

- }

60478

- while (++align_words < GP_ARG_NUM_REG && --n_words != 0);

60479

- }

60480

- else

60481

- {

60482

- /* The whole arg fits in gprs. */

60483

- r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);

60484

- rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);

60485

- }

60486

- }

60487

- else

60488

- /* It's entirely in memory. */

60489

- rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);

60490

+ r = gen_rtx_REG (fmode, cum->fregno + i * n_fpreg);

60491

+ off = GEN_INT (i * GET_MODE_SIZE (elt_mode));

60492

+ rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);

60493

}

60494

60495

- /* Describe where this piece goes in the fprs. */

60496

- r = gen_rtx_REG (fmode, cum->fregno);

60497

- rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);

60498

-

60499

- return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));

60500

+ return rs6000_finish_function_arg (mode, rvec, k);

60501

}

60502

else if (align_words < GP_ARG_NUM_REG)

60503

{

60504

@@ -8788,9 +10278,6 @@

60505

if (TARGET_32BIT && TARGET_POWERPC64)

60506

return rs6000_mixed_function_arg (mode, type, align_words);

60507

60508

- if (mode == BLKmode)

60509

- mode = Pmode;

60510

-

60511

return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);

60512

}

60513

else

60514

@@ -8809,16 +10296,32 @@

60515

tree type, bool named)

60516

{

60517

CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);

60518

+ bool passed_in_gprs = true;

60519

int ret = 0;

60520

int align_words;

60521

+ enum machine_mode elt_mode;

60522

+ int n_elts;

60523

60524

+ rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);

60525

+

60526

if (DEFAULT_ABI == ABI_V4)

60527

return 0;

60528

60529

- if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)

60530

- && cum->nargs_prototype >= 0)

60531

- return 0;

60532

+ if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))

60533

+ {

60534

+ /* If we are passing this arg in the fixed parameter save area

60535

+ (gprs or memory) as well as VRs, we do not use the partial

60536

+ bytes mechanism; instead, rs6000_function_arg will return a

60537

+ PARALLEL including a memory element as necessary. */

60538

+ if (TARGET_64BIT && ! cum->prototype)

60539

+ return 0;

60540

60541

+ /* Otherwise, we pass in VRs only. Check for partial copies. */

60542

+ passed_in_gprs = false;

60543

+ if (cum->vregno + n_elts > ALTIVEC_ARG_MAX_REG + 1)

60544

+ ret = (ALTIVEC_ARG_MAX_REG + 1 - cum->vregno) * 16;

60545

+ }

60546

+

60547

/* In this complicated case we just disable the partial_nregs code. */

60548

if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))

60549

return 0;

60550

@@ -8825,26 +10328,30 @@

60551

60552

align_words = rs6000_parm_start (mode, type, cum->words);

60553

60554

- if (USE_FP_FOR_ARG_P (cum, mode, type))

60555

+ if (USE_FP_FOR_ARG_P (cum, elt_mode))

60556

{

60557

+ unsigned long n_fpreg = (GET_MODE_SIZE (elt_mode) + 7) >> 3;

60558

+

60559

/* If we are passing this arg in the fixed parameter save area

60560

- (gprs or memory) as well as fprs, then this function should

60561

- return the number of partial bytes passed in the parameter

60562

- save area rather than partial bytes passed in fprs. */

60563

+ (gprs or memory) as well as FPRs, we do not use the partial

60564

+ bytes mechanism; instead, rs6000_function_arg will return a

60565

+ PARALLEL including a memory element as necessary. */

60566

if (type

60567

&& (cum->nargs_prototype <= 0

60568

- || (DEFAULT_ABI == ABI_AIX

60569

+ || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)

60570

&& TARGET_XL_COMPAT

60571

&& align_words >= GP_ARG_NUM_REG)))

60572

return 0;

60573

- else if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3)

60574

- > FP_ARG_MAX_REG + 1)

60575

- ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8;

60576

- else if (cum->nargs_prototype >= 0)

60577

- return 0;

60578

+

60579

+ /* Otherwise, we pass in FPRs only. Check for partial copies. */

60580

+ passed_in_gprs = false;

60581

+ if (cum->fregno + n_elts * n_fpreg > FP_ARG_MAX_REG + 1)

60582

+ ret = ((FP_ARG_MAX_REG + 1 - cum->fregno)

60583

+ * MIN (8, GET_MODE_SIZE (elt_mode)));

60584

}

60585

60586

- if (align_words < GP_ARG_NUM_REG

60587

+ if (passed_in_gprs

60588

+ && align_words < GP_ARG_NUM_REG

60589

&& GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))

60590

ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);

60591

60592

@@ -8925,6 +10432,139 @@

60593

return 0;

60594

}

60595

60596

+/* Process parameter of type TYPE after ARGS_SO_FAR parameters were

60597

+ already processes. Return true if the parameter must be passed

60598

+ (fully or partially) on the stack. */

60599

+

60600

+static bool

60601

+rs6000_parm_needs_stack (cumulative_args_t args_so_far, tree type)

60602

+{

60603

+ enum machine_mode mode;

60604

+ int unsignedp;

60605

+ rtx entry_parm;

60606

+

60607

+ /* Catch errors. */

60608

+ if (type == NULL || type == error_mark_node)

60609

+ return true;

60610

+

60611

+ /* Handle types with no storage requirement. */

60612

+ if (TYPE_MODE (type) == VOIDmode)

60613

+ return false;

60614

+

60615

+ /* Handle complex types. */

60616

+ if (TREE_CODE (type) == COMPLEX_TYPE)

60617

+ return (rs6000_parm_needs_stack (args_so_far, TREE_TYPE (type))

60618

+ || rs6000_parm_needs_stack (args_so_far, TREE_TYPE (type)));

60619

+

60620

+ /* Handle transparent aggregates. */

60621

+ if ((TREE_CODE (type) == UNION_TYPE || TREE_CODE (type) == RECORD_TYPE)

60622

+ && TYPE_TRANSPARENT_AGGR (type))

60623

+ type = TREE_TYPE (first_field (type));

60624

+

60625

+ /* See if this arg was passed by invisible reference. */

60626

+ if (pass_by_reference (get_cumulative_args (args_so_far),

60627

+ TYPE_MODE (type), type, true))

60628

+ type = build_pointer_type (type);

60629

+

60630

+ /* Find mode as it is passed by the ABI. */

60631

+ unsignedp = TYPE_UNSIGNED (type);

60632

+ mode = promote_mode (type, TYPE_MODE (type), &unsignedp);

60633

+

60634

+ /* If we must pass in stack, we need a stack. */

60635

+ if (rs6000_must_pass_in_stack (mode, type))

60636

+ return true;

60637

+

60638

+ /* If there is no incoming register, we need a stack. */

60639

+ entry_parm = rs6000_function_arg (args_so_far, mode, type, true);

60640

+ if (entry_parm == NULL)

60641

+ return true;

60642

+

60643

+ /* Likewise if we need to pass both in registers and on the stack. */

60644

+ if (GET_CODE (entry_parm) == PARALLEL

60645

+ && XEXP (XVECEXP (entry_parm, 0, 0), 0) == NULL_RTX)

60646

+ return true;

60647

+

60648

+ /* Also true if we're partially in registers and partially not. */

60649

+ if (rs6000_arg_partial_bytes (args_so_far, mode, type, true) != 0)

60650

+ return true;

60651

+

60652

+ /* Update info on where next arg arrives in registers. */

60653

+ rs6000_function_arg_advance (args_so_far, mode, type, true);

60654

+ return false;

60655

+}

60656

+

60657

+/* Return true if FUN has no prototype, has a variable argument

60658

+ list, or passes any parameter in memory. */

60659

+

60660

+static bool

60661

+rs6000_function_parms_need_stack (tree fun)

60662

+{

60663

+ function_args_iterator args_iter;

60664

+ tree arg_type;

60665

+ CUMULATIVE_ARGS args_so_far_v;

60666

+ cumulative_args_t args_so_far;

60667

+

60668

+ if (!fun)

60669

+ /* Must be a libcall, all of which only use reg parms. */

60670

+ return false;

60671

+ if (!TYPE_P (fun))

60672

+ fun = TREE_TYPE (fun);

60673

+

60674

+ /* Varargs functions need the parameter save area. */

60675

+ if (!prototype_p (fun) || stdarg_p (fun))

60676

+ return true;

60677

+

60678

+ INIT_CUMULATIVE_INCOMING_ARGS (args_so_far_v, fun, NULL_RTX);

60679

+ args_so_far = pack_cumulative_args (&args_so_far_v);

60680

+

60681

+ if (aggregate_value_p (TREE_TYPE (fun), fun))

60682

+ {

60683

+ tree type = build_pointer_type (TREE_TYPE (fun));

60684

+ rs6000_parm_needs_stack (args_so_far, type);

60685

+ }

60686

+

60687

+ FOREACH_FUNCTION_ARGS (fun, arg_type, args_iter)

60688

+ if (rs6000_parm_needs_stack (args_so_far, arg_type))

60689

+ return true;

60690

+

60691

+ return false;

60692

+}

60693

+

60694

+/* Return the size of the REG_PARM_STACK_SPACE are for FUN. This is

60695

+ usually a constant depending on the ABI. However, in the ELFv2 ABI

60696

+ the register parameter area is optional when calling a function that

60697

+ has a prototype is scope, has no variable argument list, and passes

60698

+ all parameters in registers. */

60699

+

60700

+int

60701

+rs6000_reg_parm_stack_space (tree fun)

60702

+{

60703

+ int reg_parm_stack_space;

60704

+

60705

+ switch (DEFAULT_ABI)

60706

+ {

60707

+ default:

60708

+ reg_parm_stack_space = 0;

60709

+ break;

60710

+

60711

+ case ABI_AIX:

60712

+ case ABI_DARWIN:

60713

+ reg_parm_stack_space = TARGET_64BIT ? 64 : 32;

60714

+ break;

60715

+

60716

+ case ABI_ELFv2:

60717

+ /* ??? Recomputing this every time is a bit expensive. Is there

60718

+ a place to cache this information? */

60719

+ if (rs6000_function_parms_need_stack (fun))

60720

+ reg_parm_stack_space = TARGET_64BIT ? 64 : 32;

60721

+ else

60722

+ reg_parm_stack_space = 0;

60723

+ break;

60724

+ }

60725

+

60726

+ return reg_parm_stack_space;

60727

+}

60728

+

60729

static void

60730

rs6000_move_block_from_reg (int regno, rtx x, int nregs)

60731

{

60732

@@ -9306,8 +10946,10 @@

60733

We don't need to check for pass-by-reference because of the test above.

60734

We can return a simplifed answer, since we know there's no offset to add. */

60735

60736

- if (TARGET_MACHO

60737

- && rs6000_darwin64_abi

60738

+ if (((TARGET_MACHO

60739

+ && rs6000_darwin64_abi)

60740

+ || DEFAULT_ABI == ABI_ELFv2

60741

+ || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm))

60742

&& integer_zerop (TYPE_SIZE (type)))

60743

{

60744

unsigned HOST_WIDE_INT align, boundary;

60745

@@ -9602,6 +11244,7 @@

60746

#undef RS6000_BUILTIN_A

60747

#undef RS6000_BUILTIN_D

60748

#undef RS6000_BUILTIN_E

60749

+#undef RS6000_BUILTIN_H

60750

#undef RS6000_BUILTIN_P

60751

#undef RS6000_BUILTIN_Q

60752

#undef RS6000_BUILTIN_S

60753

@@ -9615,6 +11258,7 @@

60754

#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)

60755

#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)

60756

#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)

60757

+#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)

60758

#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)

60759

#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)

60760

#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)

60761

@@ -9633,6 +11277,7 @@

60762

#undef RS6000_BUILTIN_A

60763

#undef RS6000_BUILTIN_D

60764

#undef RS6000_BUILTIN_E

60765

+#undef RS6000_BUILTIN_H

60766

#undef RS6000_BUILTIN_P

60767

#undef RS6000_BUILTIN_Q

60768

#undef RS6000_BUILTIN_S

60769

@@ -9646,6 +11291,7 @@

60770

{ MASK, ICODE, NAME, ENUM },

60771

60772

#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)

60773

+#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)

60774

#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)

60775

#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)

60776

#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)

60777

@@ -9664,6 +11310,7 @@

60778

#undef RS6000_BUILTIN_A

60779

#undef RS6000_BUILTIN_D

60780

#undef RS6000_BUILTIN_E

60781

+#undef RS6000_BUILTIN_H

60782

#undef RS6000_BUILTIN_P

60783

#undef RS6000_BUILTIN_Q

60784

#undef RS6000_BUILTIN_S

60785

@@ -9677,6 +11324,7 @@

60786

#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)

60787

#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)

60788

#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)

60789

+#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)

60790

#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)

60791

#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)

60792

#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)

60793

@@ -9693,6 +11341,7 @@

60794

#undef RS6000_BUILTIN_A

60795

#undef RS6000_BUILTIN_D

60796

#undef RS6000_BUILTIN_E

60797

+#undef RS6000_BUILTIN_H

60798

#undef RS6000_BUILTIN_P

60799

#undef RS6000_BUILTIN_Q

60800

#undef RS6000_BUILTIN_S

60801

@@ -9704,6 +11353,7 @@

60802

#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)

60803

#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)

60804

#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)

60805

+#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)

60806

#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \

60807

{ MASK, ICODE, NAME, ENUM },

60808

60809

@@ -9725,6 +11375,7 @@

60810

#undef RS6000_BUILTIN_A

60811

#undef RS6000_BUILTIN_D

60812

#undef RS6000_BUILTIN_E

60813

+#undef RS6000_BUILTIN_H

60814

#undef RS6000_BUILTIN_P

60815

#undef RS6000_BUILTIN_Q

60816

#undef RS6000_BUILTIN_S

60817

@@ -9736,6 +11387,7 @@

60818

#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)

60819

#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)

60820

#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)

60821

+#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)

60822

#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)

60823

#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)

60824

#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \

60825

@@ -9755,6 +11407,7 @@

60826

#undef RS6000_BUILTIN_A

60827

#undef RS6000_BUILTIN_D

60828

#undef RS6000_BUILTIN_E

60829

+#undef RS6000_BUILTIN_H

60830

#undef RS6000_BUILTIN_P

60831

#undef RS6000_BUILTIN_Q

60832

#undef RS6000_BUILTIN_S

60833

@@ -9768,6 +11421,7 @@

60834

#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \

60835

{ MASK, ICODE, NAME, ENUM },

60836

60837

+#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)

60838

#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)

60839

#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)

60840

#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)

60841

@@ -9785,6 +11439,7 @@

60842

#undef RS6000_BUILTIN_A

60843

#undef RS6000_BUILTIN_D

60844

#undef RS6000_BUILTIN_E

60845

+#undef RS6000_BUILTIN_H

60846

#undef RS6000_BUILTIN_P

60847

#undef RS6000_BUILTIN_Q

60848

#undef RS6000_BUILTIN_S

60849

@@ -9796,6 +11451,7 @@

60850

#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)

60851

#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)

60852

#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)

60853

+#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)

60854

#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)

60855

#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \

60856

{ MASK, ICODE, NAME, ENUM },

60857

@@ -9816,6 +11472,7 @@

60858

#undef RS6000_BUILTIN_A

60859

#undef RS6000_BUILTIN_D

60860

#undef RS6000_BUILTIN_E

60861

+#undef RS6000_BUILTIN_H

60862

#undef RS6000_BUILTIN_P

60863

#undef RS6000_BUILTIN_Q

60864

#undef RS6000_BUILTIN_S

60865

@@ -9829,6 +11486,7 @@

60866

60867

#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)

60868

#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)

60869

+#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)

60870

#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)

60871

#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)

60872

#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)

60873

@@ -9846,8 +11504,9 @@

60874

#undef RS6000_BUILTIN_2

60875

#undef RS6000_BUILTIN_3

60876

#undef RS6000_BUILTIN_A

60877

+#undef RS6000_BUILTIN_D

60878

#undef RS6000_BUILTIN_E

60879

-#undef RS6000_BUILTIN_D

60880

+#undef RS6000_BUILTIN_H

60881

#undef RS6000_BUILTIN_P

60882

#undef RS6000_BUILTIN_Q

60883

#undef RS6000_BUILTIN_S

60884

@@ -9861,6 +11520,7 @@

60885

#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)

60886

#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)

60887

#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)

60888

+#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)

60889

#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)

60890

#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)

60891

#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)

60892

@@ -9871,6 +11531,7 @@

60893

#include "rs6000-builtin.def"

60894

};

60895

60896

+/* HTM builtins. */

60897

#undef RS6000_BUILTIN_1

60898

#undef RS6000_BUILTIN_2

60899

#undef RS6000_BUILTIN_3

60900

@@ -9877,11 +11538,42 @@

60901

#undef RS6000_BUILTIN_A

60902

#undef RS6000_BUILTIN_D

60903

#undef RS6000_BUILTIN_E

60904

+#undef RS6000_BUILTIN_H

60905

#undef RS6000_BUILTIN_P

60906

#undef RS6000_BUILTIN_Q

60907

#undef RS6000_BUILTIN_S

60908

#undef RS6000_BUILTIN_X

60909

60910

+#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)

60911

+#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)

60912

+#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)

60913

+#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)

60914

+#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)

60915

+#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)

60916

+#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \

60917

+ { MASK, ICODE, NAME, ENUM },

60918

+

60919

+#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)

60920

+#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)

60921

+#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)

60922

+#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)

60923

+

60924

+static const struct builtin_description bdesc_htm[] =

60925

+{

60926

+#include "rs6000-builtin.def"

60927

+};

60928

+

60929

+#undef RS6000_BUILTIN_1

60930

+#undef RS6000_BUILTIN_2

60931

+#undef RS6000_BUILTIN_3

60932

+#undef RS6000_BUILTIN_A

60933

+#undef RS6000_BUILTIN_D

60934

+#undef RS6000_BUILTIN_E

60935

+#undef RS6000_BUILTIN_H

60936

+#undef RS6000_BUILTIN_P

60937

+#undef RS6000_BUILTIN_Q

60938

+#undef RS6000_BUILTIN_S

60939

+

60940

/* Return true if a builtin function is overloaded. */

60941

bool

60942

rs6000_overloaded_builtin_p (enum rs6000_builtins fncode)

60943

@@ -10189,7 +11881,101 @@

60944

return target;

60945

}

60946

60947

+/* Return a constant vector for use as a little-endian permute control vector

60948

+ to reverse the order of elements of the given vector mode. */

60949

static rtx

60950

+swap_selector_for_mode (enum machine_mode mode)

60951

+{

60952

+ /* These are little endian vectors, so their elements are reversed

60953

+ from what you would normally expect for a permute control vector. */

60954

+ unsigned int swap2[16] = {7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8};

60955

+ unsigned int swap4[16] = {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12};

60956

+ unsigned int swap8[16] = {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14};

60957

+ unsigned int swap16[16] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

60958

+ unsigned int *swaparray, i;

60959

+ rtx perm[16];

60960

+

60961

+ switch (mode)

60962

+ {

60963

+ case V2DFmode:

60964

+ case V2DImode:

60965

+ swaparray = swap2;

60966

+ break;

60967

+ case V4SFmode:

60968

+ case V4SImode:

60969

+ swaparray = swap4;

60970

+ break;

60971

+ case V8HImode:

60972

+ swaparray = swap8;

60973

+ break;

60974

+ case V16QImode:

60975

+ swaparray = swap16;

60976

+ break;

60977

+ default:

60978

+ gcc_unreachable ();

60979

+ }

60980

+

60981

+ for (i = 0; i < 16; ++i)

60982

+ perm[i] = GEN_INT (swaparray[i]);

60983

+

60984

+ return force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, perm)));

60985

+}

60986

+

60987

+/* Generate code for an "lvx", "lvxl", or "lve*x" built-in for a little endian target

60988

+ with -maltivec=be specified. Issue the load followed by an element-reversing

60989

+ permute. */

60990

+void

60991

+altivec_expand_lvx_be (rtx op0, rtx op1, enum machine_mode mode, unsigned unspec)

60992

+{

60993

+ rtx tmp = gen_reg_rtx (mode);

60994

+ rtx load = gen_rtx_SET (VOIDmode, tmp, op1);

60995

+ rtx lvx = gen_rtx_UNSPEC (mode, gen_rtvec (1, const0_rtx), unspec);

60996

+ rtx par = gen_rtx_PARALLEL (mode, gen_rtvec (2, load, lvx));

60997

+ rtx sel = swap_selector_for_mode (mode);

60998

+ rtx vperm = gen_rtx_UNSPEC (mode, gen_rtvec (3, tmp, tmp, sel), UNSPEC_VPERM);

60999

+

61000

+ gcc_assert (REG_P (op0));

61001

+ emit_insn (par);

61002

+ emit_insn (gen_rtx_SET (VOIDmode, op0, vperm));

61003

+}

61004

+

61005

+/* Generate code for a "stvx" or "stvxl" built-in for a little endian target

61006

+ with -maltivec=be specified. Issue the store preceded by an element-reversing

61007

+ permute. */

61008

+void

61009

+altivec_expand_stvx_be (rtx op0, rtx op1, enum machine_mode mode, unsigned unspec)

61010

+{

61011

+ rtx tmp = gen_reg_rtx (mode);

61012

+ rtx store = gen_rtx_SET (VOIDmode, op0, tmp);

61013

+ rtx stvx = gen_rtx_UNSPEC (mode, gen_rtvec (1, const0_rtx), unspec);

61014

+ rtx par = gen_rtx_PARALLEL (mode, gen_rtvec (2, store, stvx));

61015

+ rtx sel = swap_selector_for_mode (mode);

61016

+ rtx vperm;

61017

+

61018

+ gcc_assert (REG_P (op1));

61019

+ vperm = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op1, sel), UNSPEC_VPERM);

61020

+ emit_insn (gen_rtx_SET (VOIDmode, tmp, vperm));

61021

+ emit_insn (par);

61022

+}

61023

+

61024

+/* Generate code for a "stve*x" built-in for a little endian target with -maltivec=be

61025

+ specified. Issue the store preceded by an element-reversing permute. */

61026

+void

61027

+altivec_expand_stvex_be (rtx op0, rtx op1, enum machine_mode mode, unsigned unspec)

61028

+{

61029

+ enum machine_mode inner_mode = GET_MODE_INNER (mode);

61030

+ rtx tmp = gen_reg_rtx (mode);

61031

+ rtx stvx = gen_rtx_UNSPEC (inner_mode, gen_rtvec (1, tmp), unspec);

61032

+ rtx sel = swap_selector_for_mode (mode);

61033

+ rtx vperm;

61034

+

61035

+ gcc_assert (REG_P (op1));

61036

+ vperm = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op1, sel), UNSPEC_VPERM);

61037

+ emit_insn (gen_rtx_SET (VOIDmode, tmp, vperm));

61038

+ emit_insn (gen_rtx_SET (VOIDmode, op0, stvx));

61039

+}

61040

+

61041

+static rtx

61042

altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target, bool blk)

61043

{

61044

rtx pat, addr;

61045

@@ -10351,7 +12137,198 @@

61046

return NULL_RTX;

61047

}

61048

61049

+/* Return the appropriate SPR number associated with the given builtin. */

61050

+static inline HOST_WIDE_INT

61051

+htm_spr_num (enum rs6000_builtins code)

61052

+{

61053

+ if (code == HTM_BUILTIN_GET_TFHAR

61054

+ || code == HTM_BUILTIN_SET_TFHAR)

61055

+ return TFHAR_SPR;

61056

+ else if (code == HTM_BUILTIN_GET_TFIAR

61057

+ || code == HTM_BUILTIN_SET_TFIAR)

61058

+ return TFIAR_SPR;

61059

+ else if (code == HTM_BUILTIN_GET_TEXASR

61060

+ || code == HTM_BUILTIN_SET_TEXASR)

61061

+ return TEXASR_SPR;

61062

+ gcc_assert (code == HTM_BUILTIN_GET_TEXASRU

61063

+ || code == HTM_BUILTIN_SET_TEXASRU);

61064

+ return TEXASRU_SPR;

61065

+}

61066

+

61067

+/* Return the appropriate SPR regno associated with the given builtin. */

61068

+static inline HOST_WIDE_INT

61069

+htm_spr_regno (enum rs6000_builtins code)

61070

+{

61071

+ if (code == HTM_BUILTIN_GET_TFHAR

61072

+ || code == HTM_BUILTIN_SET_TFHAR)

61073

+ return TFHAR_REGNO;

61074

+ else if (code == HTM_BUILTIN_GET_TFIAR

61075

+ || code == HTM_BUILTIN_SET_TFIAR)

61076

+ return TFIAR_REGNO;

61077

+ gcc_assert (code == HTM_BUILTIN_GET_TEXASR

61078

+ || code == HTM_BUILTIN_SET_TEXASR

61079

+ || code == HTM_BUILTIN_GET_TEXASRU

61080

+ || code == HTM_BUILTIN_SET_TEXASRU);

61081

+ return TEXASR_REGNO;

61082

+}

61083

+

61084

+/* Return the correct ICODE value depending on whether we are

61085

+ setting or reading the HTM SPRs. */

61086

+static inline enum insn_code

61087

+rs6000_htm_spr_icode (bool nonvoid)

61088

+{

61089

+ if (nonvoid)

61090

+ return (TARGET_64BIT) ? CODE_FOR_htm_mfspr_di : CODE_FOR_htm_mfspr_si;

61091

+ else

61092

+ return (TARGET_64BIT) ? CODE_FOR_htm_mtspr_di : CODE_FOR_htm_mtspr_si;

61093

+}

61094

+

61095

+/* Expand the HTM builtin in EXP and store the result in TARGET.

61096

+ Store true in *EXPANDEDP if we found a builtin to expand. */

61097

static rtx

61098

+htm_expand_builtin (tree exp, rtx target, bool * expandedp)

61099

+{

61100

+ tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);

61101

+ bool nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;

61102

+ enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);

61103

+ const struct builtin_description *d;

61104

+ size_t i;

61105

+

61106

+ *expandedp = false;

61107

+

61108

+ /* Expand the HTM builtins. */

61109

+ d = bdesc_htm;

61110

+ for (i = 0; i < ARRAY_SIZE (bdesc_htm); i++, d++)

61111

+ if (d->code == fcode)

61112

+ {

61113

+ rtx op[MAX_HTM_OPERANDS], pat;

61114

+ int nopnds = 0;

61115

+ tree arg;

61116

+ call_expr_arg_iterator iter;

61117

+ unsigned attr = rs6000_builtin_info[fcode].attr;

61118

+ enum insn_code icode = d->icode;

61119

+

61120

+ if (attr & RS6000_BTC_SPR)

61121

+ icode = rs6000_htm_spr_icode (nonvoid);

61122

+

61123

+ if (nonvoid)

61124

+ {

61125

+ enum machine_mode tmode = insn_data[icode].operand[0].mode;

61126

+ if (!target

61127

+ || GET_MODE (target) != tmode

61128

+ || !(*insn_data[icode].operand[0].predicate) (target, tmode))

61129

+ target = gen_reg_rtx (tmode);

61130

+ op[nopnds++] = target;

61131

+ }

61132

+

61133

+ FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)

61134

+ {

61135

+ const struct insn_operand_data *insn_op;

61136

+

61137

+ if (arg == error_mark_node || nopnds >= MAX_HTM_OPERANDS)

61138

+ return NULL_RTX;

61139

+

61140

+ insn_op = &insn_data[icode].operand[nopnds];

61141

+

61142

+ op[nopnds] = expand_normal (arg);

61143

+

61144

+ if (!(*insn_op->predicate) (op[nopnds], insn_op->mode))

61145

+ {

61146

+ if (!strcmp (insn_op->constraint, "n"))

61147

+ {

61148

+ int arg_num = (nonvoid) ? nopnds : nopnds + 1;

61149

+ if (!CONST_INT_P (op[nopnds]))

61150

+ error ("argument %d must be an unsigned literal", arg_num);

61151

+ else

61152

+ error ("argument %d is an unsigned literal that is "

61153

+ "out of range", arg_num);

61154

+ return const0_rtx;

61155

+ }

61156

+ op[nopnds] = copy_to_mode_reg (insn_op->mode, op[nopnds]);

61157

+ }

61158

+

61159

+ nopnds++;

61160

+ }

61161

+

61162

+ /* Handle the builtins for extended mnemonics. These accept

61163

+ no arguments, but map to builtins that take arguments. */

61164

+ switch (fcode)

61165

+ {

61166

+ case HTM_BUILTIN_TENDALL: /* Alias for: tend. 1 */

61167

+ case HTM_BUILTIN_TRESUME: /* Alias for: tsr. 1 */

61168

+ op[nopnds++] = GEN_INT (1);

61169

+#ifdef ENABLE_CHECKING

61170

+ attr |= RS6000_BTC_UNARY;

61171

+#endif

61172

+ break;

61173

+ case HTM_BUILTIN_TSUSPEND: /* Alias for: tsr. 0 */

61174

+ op[nopnds++] = GEN_INT (0);

61175

+#ifdef ENABLE_CHECKING

61176

+ attr |= RS6000_BTC_UNARY;

61177

+#endif

61178

+ break;

61179

+ default:

61180

+ break;

61181

+ }

61182

+

61183

+ /* If this builtin accesses SPRs, then pass in the appropriate

61184

+ SPR number and SPR regno as the last two operands. */

61185

+ if (attr & RS6000_BTC_SPR)

61186

+ {

61187

+ op[nopnds++] = gen_rtx_CONST_INT (Pmode, htm_spr_num (fcode));

61188

+ op[nopnds++] = gen_rtx_REG (Pmode, htm_spr_regno (fcode));

61189

+ }

61190

+

61191

+#ifdef ENABLE_CHECKING

61192

+ int expected_nopnds = 0;

61193

+ if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_UNARY)

61194

+ expected_nopnds = 1;

61195

+ else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_BINARY)

61196

+ expected_nopnds = 2;

61197

+ else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_TERNARY)

61198

+ expected_nopnds = 3;

61199

+ if (!(attr & RS6000_BTC_VOID))

61200

+ expected_nopnds += 1;

61201

+ if (attr & RS6000_BTC_SPR)

61202

+ expected_nopnds += 2;

61203

+

61204

+ gcc_assert (nopnds == expected_nopnds && nopnds <= MAX_HTM_OPERANDS);

61205

+#endif

61206

+

61207

+ switch (nopnds)

61208

+ {

61209

+ case 0:

61210

+ pat = GEN_FCN (icode) (NULL_RTX);

61211

+ break;

61212

+ case 1:

61213

+ pat = GEN_FCN (icode) (op[0]);

61214

+ break;

61215

+ case 2:

61216

+ pat = GEN_FCN (icode) (op[0], op[1]);

61217

+ break;

61218

+ case 3:

61219

+ pat = GEN_FCN (icode) (op[0], op[1], op[2]);

61220

+ break;

61221

+ case 4:

61222

+ pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);

61223

+ break;

61224

+ default:

61225

+ gcc_unreachable ();

61226

+ }

61227

+ if (!pat)

61228

+ return NULL_RTX;

61229

+ emit_insn (pat);

61230

+

61231

+ *expandedp = true;

61232

+ if (nonvoid)

61233

+ return target;

61234

+ return const0_rtx;

61235

+ }

61236

+

61237

+ return NULL_RTX;

61238

+}

61239

+

61240

+static rtx

61241

rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target)

61242

{

61243

rtx pat;

61244

@@ -10416,7 +12393,15 @@

61245

}

61246

}

61247

else if (icode == CODE_FOR_vsx_set_v2df

61248

- || icode == CODE_FOR_vsx_set_v2di)

61249

+ || icode == CODE_FOR_vsx_set_v2di

61250

+ || icode == CODE_FOR_bcdadd

61251

+ || icode == CODE_FOR_bcdadd_lt

61252

+ || icode == CODE_FOR_bcdadd_eq

61253

+ || icode == CODE_FOR_bcdadd_gt

61254

+ || icode == CODE_FOR_bcdsub

61255

+ || icode == CODE_FOR_bcdsub_lt

61256

+ || icode == CODE_FOR_bcdsub_eq

61257

+ || icode == CODE_FOR_bcdsub_gt)

61258

{

61259

/* Only allow 1-bit unsigned literals. */

61260

STRIP_NOPS (arg2);

61261

@@ -10427,7 +12412,66 @@

61262

return const0_rtx;

61263

}

61264

}

61265

+ else if (icode == CODE_FOR_dfp_ddedpd_dd

61266

+ || icode == CODE_FOR_dfp_ddedpd_td)

61267

+ {

61268

+ /* Only allow 2-bit unsigned literals where the value is 0 or 2. */

61269

+ STRIP_NOPS (arg0);

61270

+ if (TREE_CODE (arg0) != INTEGER_CST

61271

+ || TREE_INT_CST_LOW (arg2) & ~0x3)

61272

+ {

61273

+ error ("argument 1 must be 0 or 2");

61274

+ return const0_rtx;

61275

+ }

61276

+ }

61277

+ else if (icode == CODE_FOR_dfp_denbcd_dd

61278

+ || icode == CODE_FOR_dfp_denbcd_td)

61279

+ {

61280

+ /* Only allow 1-bit unsigned literals. */

61281

+ STRIP_NOPS (arg0);

61282

+ if (TREE_CODE (arg0) != INTEGER_CST

61283

+ || TREE_INT_CST_LOW (arg0) & ~0x1)

61284

+ {

61285

+ error ("argument 1 must be a 1-bit unsigned literal");

61286

+ return const0_rtx;

61287

+ }

61288

+ }

61289

+ else if (icode == CODE_FOR_dfp_dscli_dd

61290

+ || icode == CODE_FOR_dfp_dscli_td

61291

+ || icode == CODE_FOR_dfp_dscri_dd

61292

+ || icode == CODE_FOR_dfp_dscri_td)

61293

+ {

61294

+ /* Only allow 6-bit unsigned literals. */

61295

+ STRIP_NOPS (arg1);

61296

+ if (TREE_CODE (arg1) != INTEGER_CST

61297

+ || TREE_INT_CST_LOW (arg1) & ~0x3f)

61298

+ {

61299

+ error ("argument 2 must be a 6-bit unsigned literal");

61300

+ return const0_rtx;

61301

+ }

61302

+ }

61303

+ else if (icode == CODE_FOR_crypto_vshasigmaw

61304

+ || icode == CODE_FOR_crypto_vshasigmad)

61305

+ {

61306

+ /* Check whether the 2nd and 3rd arguments are integer constants and in

61307

+ range and prepare arguments. */

61308

+ STRIP_NOPS (arg1);

61309

+ if (TREE_CODE (arg1) != INTEGER_CST

61310

+ || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 1))

61311

+ {

61312

+ error ("argument 2 must be 0 or 1");

61313

+ return const0_rtx;

61314

+ }

61315

61316

+ STRIP_NOPS (arg2);

61317

+ if (TREE_CODE (arg2) != INTEGER_CST

61318

+ || !IN_RANGE (TREE_INT_CST_LOW (arg2), 0, 15))

61319

+ {

61320

+ error ("argument 3 must be in the range 0..15");

61321

+ return const0_rtx;

61322

+ }

61323

+ }

61324

+

61325

if (target == 0

61326

|| GET_MODE (target) != tmode

61327

|| ! (*insn_data[icode].operand[0].predicate) (target, tmode))

61328

@@ -10481,6 +12525,8 @@

61329

break;

61330

case ALTIVEC_BUILTIN_LD_INTERNAL_2di:

61331

icode = CODE_FOR_vector_altivec_load_v2di;

61332

+ case ALTIVEC_BUILTIN_LD_INTERNAL_1ti:

61333

+ icode = CODE_FOR_vector_altivec_load_v1ti;

61334

break;

61335

default:

61336

*expandedp = false;

61337

@@ -10540,6 +12586,8 @@

61338

break;

61339

case ALTIVEC_BUILTIN_ST_INTERNAL_2di:

61340

icode = CODE_FOR_vector_altivec_store_v2di;

61341

+ case ALTIVEC_BUILTIN_ST_INTERNAL_1ti:

61342

+ icode = CODE_FOR_vector_altivec_store_v1ti;

61343

break;

61344

default:

61345

*expandedp = false;

61346

@@ -10632,21 +12680,33 @@

61347

enum machine_mode tmode = TYPE_MODE (type);

61348

enum machine_mode inner_mode = GET_MODE_INNER (tmode);

61349

int i, n_elt = GET_MODE_NUNITS (tmode);

61350

- rtvec v = rtvec_alloc (n_elt);

61351

61352

gcc_assert (VECTOR_MODE_P (tmode));

61353

gcc_assert (n_elt == call_expr_nargs (exp));

61354

61355

- for (i = 0; i < n_elt; ++i)

61356

+ if (!target || !register_operand (target, tmode))

61357

+ target = gen_reg_rtx (tmode);

61358

+

61359

+ /* If we have a vector compromised of a single element, such as V1TImode, do

61360

+ the initialization directly. */

61361

+ if (n_elt == 1 && GET_MODE_SIZE (tmode) == GET_MODE_SIZE (inner_mode))

61362

{

61363

- rtx x = expand_normal (CALL_EXPR_ARG (exp, i));

61364

- RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);

61365

+ rtx x = expand_normal (CALL_EXPR_ARG (exp, 0));

61366

+ emit_move_insn (target, gen_lowpart (tmode, x));

61367

}

61368

+ else

61369

+ {

61370

+ rtvec v = rtvec_alloc (n_elt);

61371

61372

- if (!target || !register_operand (target, tmode))

61373

- target = gen_reg_rtx (tmode);

61374

+ for (i = 0; i < n_elt; ++i)

61375

+ {

61376

+ rtx x = expand_normal (CALL_EXPR_ARG (exp, i));

61377

+ RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);

61378

+ }

61379

61380

- rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));

61381

+ rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));

61382

+ }

61383

+

61384

return target;

61385

}

61386

61387

@@ -10769,8 +12829,19 @@

61388

61389

switch (fcode)

61390

{

61391

+ case ALTIVEC_BUILTIN_STVX_V2DF:

61392

+ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2df, exp);

61393

+ case ALTIVEC_BUILTIN_STVX_V2DI:

61394

+ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2di, exp);

61395

+ case ALTIVEC_BUILTIN_STVX_V4SF:

61396

+ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4sf, exp);

61397

case ALTIVEC_BUILTIN_STVX:

61398

+ case ALTIVEC_BUILTIN_STVX_V4SI:

61399

return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si, exp);

61400

+ case ALTIVEC_BUILTIN_STVX_V8HI:

61401

+ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v8hi, exp);

61402

+ case ALTIVEC_BUILTIN_STVX_V16QI:

61403

+ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v16qi, exp);

61404

case ALTIVEC_BUILTIN_STVEBX:

61405

return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);

61406

case ALTIVEC_BUILTIN_STVEHX:

61407

@@ -10777,8 +12848,19 @@

61408

return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp);

61409

case ALTIVEC_BUILTIN_STVEWX:

61410

return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp);

61411

+ case ALTIVEC_BUILTIN_STVXL_V2DF:

61412

+ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2df, exp);

61413

+ case ALTIVEC_BUILTIN_STVXL_V2DI:

61414

+ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2di, exp);

61415

+ case ALTIVEC_BUILTIN_STVXL_V4SF:

61416

+ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4sf, exp);

61417

case ALTIVEC_BUILTIN_STVXL:

61418

- return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, exp);

61419

+ case ALTIVEC_BUILTIN_STVXL_V4SI:

61420

+ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4si, exp);

61421

+ case ALTIVEC_BUILTIN_STVXL_V8HI:

61422

+ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v8hi, exp);

61423

+ case ALTIVEC_BUILTIN_STVXL_V16QI:

61424

+ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v16qi, exp);

61425

61426

case ALTIVEC_BUILTIN_STVLX:

61427

return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx, exp);

61428

@@ -10789,6 +12871,8 @@

61429

case ALTIVEC_BUILTIN_STVRXL:

61430

return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl, exp);

61431

61432

+ case VSX_BUILTIN_STXVD2X_V1TI:

61433

+ return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v1ti, exp);

61434

case VSX_BUILTIN_STXVD2X_V2DF:

61435

return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df, exp);

61436

case VSX_BUILTIN_STXVD2X_V2DI:

61437

@@ -10869,6 +12953,7 @@

61438

case ALTIVEC_BUILTIN_VEC_INIT_V4SF:

61439

case VSX_BUILTIN_VEC_INIT_V2DF:

61440

case VSX_BUILTIN_VEC_INIT_V2DI:

61441

+ case VSX_BUILTIN_VEC_INIT_V1TI:

61442

return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);

61443

61444

case ALTIVEC_BUILTIN_VEC_SET_V4SI:

61445

@@ -10877,6 +12962,7 @@

61446

case ALTIVEC_BUILTIN_VEC_SET_V4SF:

61447

case VSX_BUILTIN_VEC_SET_V2DF:

61448

case VSX_BUILTIN_VEC_SET_V2DI:

61449

+ case VSX_BUILTIN_VEC_SET_V1TI:

61450

return altivec_expand_vec_set_builtin (exp);

61451

61452

case ALTIVEC_BUILTIN_VEC_EXT_V4SI:

61453

@@ -10885,6 +12971,7 @@

61454

case ALTIVEC_BUILTIN_VEC_EXT_V4SF:

61455

case VSX_BUILTIN_VEC_EXT_V2DF:

61456

case VSX_BUILTIN_VEC_EXT_V2DI:

61457

+ case VSX_BUILTIN_VEC_EXT_V1TI:

61458

return altivec_expand_vec_ext_builtin (exp, target);

61459

61460

default:

61461

@@ -10922,12 +13009,44 @@

61462

case ALTIVEC_BUILTIN_LVEWX:

61463

return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,

61464

exp, target, false);

61465

+ case ALTIVEC_BUILTIN_LVXL_V2DF:

61466

+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2df,

61467

+ exp, target, false);

61468

+ case ALTIVEC_BUILTIN_LVXL_V2DI:

61469

+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2di,

61470

+ exp, target, false);

61471

+ case ALTIVEC_BUILTIN_LVXL_V4SF:

61472

+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4sf,

61473

+ exp, target, false);

61474

case ALTIVEC_BUILTIN_LVXL:

61475

- return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,

61476

+ case ALTIVEC_BUILTIN_LVXL_V4SI:

61477

+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4si,

61478

exp, target, false);

61479

+ case ALTIVEC_BUILTIN_LVXL_V8HI:

61480

+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v8hi,

61481

+ exp, target, false);

61482

+ case ALTIVEC_BUILTIN_LVXL_V16QI:

61483

+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v16qi,

61484

+ exp, target, false);

61485

+ case ALTIVEC_BUILTIN_LVX_V2DF:

61486

+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2df,

61487

+ exp, target, false);

61488

+ case ALTIVEC_BUILTIN_LVX_V2DI:

61489

+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2di,

61490

+ exp, target, false);

61491

+ case ALTIVEC_BUILTIN_LVX_V4SF:

61492

+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4sf,

61493

+ exp, target, false);

61494

case ALTIVEC_BUILTIN_LVX:

61495

+ case ALTIVEC_BUILTIN_LVX_V4SI:

61496

return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si,

61497

exp, target, false);

61498

+ case ALTIVEC_BUILTIN_LVX_V8HI:

61499

+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v8hi,

61500

+ exp, target, false);

61501

+ case ALTIVEC_BUILTIN_LVX_V16QI:

61502

+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v16qi,

61503

+ exp, target, false);

61504

case ALTIVEC_BUILTIN_LVLX:

61505

return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx,

61506

exp, target, true);

61507

@@ -10940,6 +13059,9 @@

61508

case ALTIVEC_BUILTIN_LVRXL:

61509

return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl,

61510

exp, target, true);

61511

+ case VSX_BUILTIN_LXVD2X_V1TI:

61512

+ return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v1ti,

61513

+ exp, target, false);

61514

case VSX_BUILTIN_LXVD2X_V2DF:

61515

return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df,

61516

exp, target, false);

61517

@@ -11411,6 +13533,8 @@

61518

error ("Builtin function %s is only valid for the cell processor", name);

61519

else if ((fnmask & RS6000_BTM_VSX) != 0)

61520

error ("Builtin function %s requires the -mvsx option", name);

61521

+ else if ((fnmask & RS6000_BTM_HTM) != 0)

61522

+ error ("Builtin function %s requires the -mhtm option", name);

61523

else if ((fnmask & RS6000_BTM_ALTIVEC) != 0)

61524

error ("Builtin function %s requires the -maltivec option", name);

61525

else if ((fnmask & RS6000_BTM_PAIRED) != 0)

61526

@@ -11417,6 +13541,16 @@

61527

error ("Builtin function %s requires the -mpaired option", name);

61528

else if ((fnmask & RS6000_BTM_SPE) != 0)

61529

error ("Builtin function %s requires the -mspe option", name);

61530

+ else if ((fnmask & (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))

61531

+ == (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))

61532

+ error ("Builtin function %s requires the -mhard-dfp and"

61533

+ "-mpower8-vector options", name);

61534

+ else if ((fnmask & RS6000_BTM_DFP) != 0)

61535

+ error ("Builtin function %s requires the -mhard-dfp option", name);

61536

+ else if ((fnmask & RS6000_BTM_P8_VECTOR) != 0)

61537

+ error ("Builtin function %s requires the -mpower8-vector option", name);

61538

+ else if ((fnmask & RS6000_BTM_HARD_FLOAT) != 0)

61539

+ error ("Builtin function %s requires the -mhard-float option", name);

61540

else

61541

error ("Builtin function %s is not supported with the current options",

61542

name);

61543

@@ -11515,7 +13649,8 @@

61544

case ALTIVEC_BUILTIN_MASK_FOR_LOAD:

61545

case ALTIVEC_BUILTIN_MASK_FOR_STORE:

61546

{

61547

- int icode = (int) CODE_FOR_altivec_lvsr;

61548

+ int icode = (BYTES_BIG_ENDIAN ? (int) CODE_FOR_altivec_lvsr

61549

+ : (int) CODE_FOR_altivec_lvsl);

61550

enum machine_mode tmode = insn_data[icode].operand[0].mode;

61551

enum machine_mode mode = insn_data[icode].operand[1].mode;

61552

tree arg;

61553

@@ -11590,9 +13725,19 @@

61554

if (success)

61555

return ret;

61556

}

61557

+ if (TARGET_HTM)

61558

+ {

61559

+ ret = htm_expand_builtin (exp, target, &success);

61560

61561

- gcc_assert (TARGET_ALTIVEC || TARGET_VSX || TARGET_SPE || TARGET_PAIRED_FLOAT);

61562

+ if (success)

61563

+ return ret;

61564

+ }

61565

61566

+ unsigned attr = rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK;

61567

+ gcc_assert (attr == RS6000_BTC_UNARY

61568

+ || attr == RS6000_BTC_BINARY

61569

+ || attr == RS6000_BTC_TERNARY);

61570

+

61571

/* Handle simple unary operations. */

61572

d = bdesc_1arg;

61573

for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)

61574

@@ -11648,6 +13793,14 @@

61575

opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);

61576

opaque_V4SI_type_node = build_opaque_vector_type (intSI_type_node, 4);

61577

61578

+ /* We use V1TI mode as a special container to hold __int128_t items that

61579

+ must live in VSX registers. */

61580

+ if (intTI_type_node)

61581

+ {

61582

+ V1TI_type_node = build_vector_type (intTI_type_node, 1);

61583

+ unsigned_V1TI_type_node = build_vector_type (unsigned_intTI_type_node, 1);

61584

+ }

61585

+

61586

/* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'

61587

types, especially in C++ land. Similarly, 'vector pixel' is distinct from

61588

'vector unsigned short'. */

61589

@@ -11670,8 +13823,13 @@

61590

uintSI_type_internal_node = unsigned_intSI_type_node;

61591

intDI_type_internal_node = intDI_type_node;

61592

uintDI_type_internal_node = unsigned_intDI_type_node;

61593

+ intTI_type_internal_node = intTI_type_node;

61594

+ uintTI_type_internal_node = unsigned_intTI_type_node;

61595

float_type_internal_node = float_type_node;

61596

double_type_internal_node = double_type_node;

61597

+ long_double_type_internal_node = long_double_type_node;

61598

+ dfloat64_type_internal_node = dfloat64_type_node;

61599

+ dfloat128_type_internal_node = dfloat128_type_node;

61600

void_type_internal_node = void_type_node;

61601

61602

/* Initialize the modes for builtin_function_type, mapping a machine mode to

61603

@@ -11682,8 +13840,15 @@

61604

builtin_mode_to_type[SImode][1] = unsigned_intSI_type_node;

61605

builtin_mode_to_type[DImode][0] = intDI_type_node;

61606

builtin_mode_to_type[DImode][1] = unsigned_intDI_type_node;

61607

+ builtin_mode_to_type[TImode][0] = intTI_type_node;

61608

+ builtin_mode_to_type[TImode][1] = unsigned_intTI_type_node;

61609

builtin_mode_to_type[SFmode][0] = float_type_node;

61610

builtin_mode_to_type[DFmode][0] = double_type_node;

61611

+ builtin_mode_to_type[TFmode][0] = long_double_type_node;

61612

+ builtin_mode_to_type[DDmode][0] = dfloat64_type_node;

61613

+ builtin_mode_to_type[TDmode][0] = dfloat128_type_node;

61614

+ builtin_mode_to_type[V1TImode][0] = V1TI_type_node;

61615

+ builtin_mode_to_type[V1TImode][1] = unsigned_V1TI_type_node;

61616

builtin_mode_to_type[V2SImode][0] = V2SI_type_node;

61617

builtin_mode_to_type[V2SFmode][0] = V2SF_type_node;

61618

builtin_mode_to_type[V2DImode][0] = V2DI_type_node;

61619

@@ -11752,15 +13917,42 @@

61620

tdecl = add_builtin_type ("__vector double", V2DF_type_node);

61621

TYPE_NAME (V2DF_type_node) = tdecl;

61622

61623

- tdecl = add_builtin_type ("__vector long", V2DI_type_node);

61624

- TYPE_NAME (V2DI_type_node) = tdecl;

61625

+ if (TARGET_POWERPC64)

61626

+ {

61627

+ tdecl = add_builtin_type ("__vector long", V2DI_type_node);

61628

+ TYPE_NAME (V2DI_type_node) = tdecl;

61629

61630

- tdecl = add_builtin_type ("__vector unsigned long", unsigned_V2DI_type_node);

61631

- TYPE_NAME (unsigned_V2DI_type_node) = tdecl;

61632

+ tdecl = add_builtin_type ("__vector unsigned long",

61633

+ unsigned_V2DI_type_node);

61634

+ TYPE_NAME (unsigned_V2DI_type_node) = tdecl;

61635

61636

- tdecl = add_builtin_type ("__vector __bool long", bool_V2DI_type_node);

61637

- TYPE_NAME (bool_V2DI_type_node) = tdecl;

61638

+ tdecl = add_builtin_type ("__vector __bool long", bool_V2DI_type_node);

61639

+ TYPE_NAME (bool_V2DI_type_node) = tdecl;

61640

+ }

61641

+ else

61642

+ {

61643

+ tdecl = add_builtin_type ("__vector long long", V2DI_type_node);

61644

+ TYPE_NAME (V2DI_type_node) = tdecl;

61645

61646

+ tdecl = add_builtin_type ("__vector unsigned long long",

61647

+ unsigned_V2DI_type_node);

61648

+ TYPE_NAME (unsigned_V2DI_type_node) = tdecl;

61649

+

61650

+ tdecl = add_builtin_type ("__vector __bool long long",

61651

+ bool_V2DI_type_node);

61652

+ TYPE_NAME (bool_V2DI_type_node) = tdecl;

61653

+ }

61654

+

61655

+ if (V1TI_type_node)

61656

+ {

61657

+ tdecl = add_builtin_type ("__vector __int128", V1TI_type_node);

61658

+ TYPE_NAME (V1TI_type_node) = tdecl;

61659

+

61660

+ tdecl = add_builtin_type ("__vector unsigned __int128",

61661

+ unsigned_V1TI_type_node);

61662

+ TYPE_NAME (unsigned_V1TI_type_node) = tdecl;

61663

+ }

61664

+

61665

/* Paired and SPE builtins are only available if you build a compiler with

61666

the appropriate options, so only create those builtins with the

61667

appropriate compiler option. Create Altivec and VSX builtins on machines

61668

@@ -11772,6 +13964,9 @@

61669

spe_init_builtins ();

61670

if (TARGET_EXTRA_BUILTINS)

61671

altivec_init_builtins ();

61672

+ if (TARGET_HTM)

61673

+ htm_init_builtins ();

61674

+

61675

if (TARGET_EXTRA_BUILTINS || TARGET_SPE || TARGET_PAIRED_FLOAT)

61676

rs6000_common_init_builtins ();

61677

61678

@@ -12117,6 +14312,10 @@

61679

= build_function_type_list (integer_type_node,

61680

integer_type_node, V4SI_type_node,

61681

V4SI_type_node, NULL_TREE);

61682

+ tree int_ftype_int_v2di_v2di

61683

+ = build_function_type_list (integer_type_node,

61684

+ integer_type_node, V2DI_type_node,

61685

+ V2DI_type_node, NULL_TREE);

61686

tree void_ftype_v4si

61687

= build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);

61688

tree v8hi_ftype_void

61689

@@ -12199,6 +14398,8 @@

61690

= build_function_type_list (integer_type_node,

61691

integer_type_node, V2DF_type_node,

61692

V2DF_type_node, NULL_TREE);

61693

+ tree v2di_ftype_v2di

61694

+ = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);

61695

tree v4si_ftype_v4si

61696

= build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);

61697

tree v8hi_ftype_v8hi

61698

@@ -12224,10 +14425,58 @@

61699

def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);

61700

def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);

61701

def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);

61702

+ def_builtin ("__builtin_altivec_lvxl_v2df", v2df_ftype_long_pcvoid,

61703

+ ALTIVEC_BUILTIN_LVXL_V2DF);

61704

+ def_builtin ("__builtin_altivec_lvxl_v2di", v2di_ftype_long_pcvoid,

61705

+ ALTIVEC_BUILTIN_LVXL_V2DI);

61706

+ def_builtin ("__builtin_altivec_lvxl_v4sf", v4sf_ftype_long_pcvoid,

61707

+ ALTIVEC_BUILTIN_LVXL_V4SF);

61708

+ def_builtin ("__builtin_altivec_lvxl_v4si", v4si_ftype_long_pcvoid,

61709

+ ALTIVEC_BUILTIN_LVXL_V4SI);

61710

+ def_builtin ("__builtin_altivec_lvxl_v8hi", v8hi_ftype_long_pcvoid,

61711

+ ALTIVEC_BUILTIN_LVXL_V8HI);

61712

+ def_builtin ("__builtin_altivec_lvxl_v16qi", v16qi_ftype_long_pcvoid,

61713

+ ALTIVEC_BUILTIN_LVXL_V16QI);

61714

def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);

61715

+ def_builtin ("__builtin_altivec_lvx_v2df", v2df_ftype_long_pcvoid,

61716

+ ALTIVEC_BUILTIN_LVX_V2DF);

61717

+ def_builtin ("__builtin_altivec_lvx_v2di", v2di_ftype_long_pcvoid,

61718

+ ALTIVEC_BUILTIN_LVX_V2DI);

61719

+ def_builtin ("__builtin_altivec_lvx_v4sf", v4sf_ftype_long_pcvoid,

61720

+ ALTIVEC_BUILTIN_LVX_V4SF);

61721

+ def_builtin ("__builtin_altivec_lvx_v4si", v4si_ftype_long_pcvoid,

61722

+ ALTIVEC_BUILTIN_LVX_V4SI);

61723

+ def_builtin ("__builtin_altivec_lvx_v8hi", v8hi_ftype_long_pcvoid,

61724

+ ALTIVEC_BUILTIN_LVX_V8HI);

61725

+ def_builtin ("__builtin_altivec_lvx_v16qi", v16qi_ftype_long_pcvoid,

61726

+ ALTIVEC_BUILTIN_LVX_V16QI);

61727

def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);

61728

+ def_builtin ("__builtin_altivec_stvx_v2df", void_ftype_v2df_long_pvoid,

61729

+ ALTIVEC_BUILTIN_STVX_V2DF);

61730

+ def_builtin ("__builtin_altivec_stvx_v2di", void_ftype_v2di_long_pvoid,

61731

+ ALTIVEC_BUILTIN_STVX_V2DI);

61732

+ def_builtin ("__builtin_altivec_stvx_v4sf", void_ftype_v4sf_long_pvoid,

61733

+ ALTIVEC_BUILTIN_STVX_V4SF);

61734

+ def_builtin ("__builtin_altivec_stvx_v4si", void_ftype_v4si_long_pvoid,

61735

+ ALTIVEC_BUILTIN_STVX_V4SI);

61736

+ def_builtin ("__builtin_altivec_stvx_v8hi", void_ftype_v8hi_long_pvoid,

61737

+ ALTIVEC_BUILTIN_STVX_V8HI);

61738

+ def_builtin ("__builtin_altivec_stvx_v16qi", void_ftype_v16qi_long_pvoid,

61739

+ ALTIVEC_BUILTIN_STVX_V16QI);

61740

def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);

61741

def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);

61742

+ def_builtin ("__builtin_altivec_stvxl_v2df", void_ftype_v2df_long_pvoid,

61743

+ ALTIVEC_BUILTIN_STVXL_V2DF);

61744

+ def_builtin ("__builtin_altivec_stvxl_v2di", void_ftype_v2di_long_pvoid,

61745

+ ALTIVEC_BUILTIN_STVXL_V2DI);

61746

+ def_builtin ("__builtin_altivec_stvxl_v4sf", void_ftype_v4sf_long_pvoid,

61747

+ ALTIVEC_BUILTIN_STVXL_V4SF);

61748

+ def_builtin ("__builtin_altivec_stvxl_v4si", void_ftype_v4si_long_pvoid,

61749

+ ALTIVEC_BUILTIN_STVXL_V4SI);

61750

+ def_builtin ("__builtin_altivec_stvxl_v8hi", void_ftype_v8hi_long_pvoid,

61751

+ ALTIVEC_BUILTIN_STVXL_V8HI);

61752

+ def_builtin ("__builtin_altivec_stvxl_v16qi", void_ftype_v16qi_long_pvoid,

61753

+ ALTIVEC_BUILTIN_STVXL_V16QI);

61754

def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);

61755

def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);

61756

def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);

61757

@@ -12334,6 +14583,9 @@

61758

case VOIDmode:

61759

type = int_ftype_int_opaque_opaque;

61760

break;

61761

+ case V2DImode:

61762

+ type = int_ftype_int_v2di_v2di;

61763

+ break;

61764

case V4SImode:

61765

type = int_ftype_int_v4si_v4si;

61766

break;

61767

@@ -12367,6 +14619,9 @@

61768

61769

switch (mode0)

61770

{

61771

+ case V2DImode:

61772

+ type = v2di_ftype_v2di;

61773

+ break;

61774

case V4SImode:

61775

type = v4si_ftype_v4si;

61776

break;

61777

@@ -12497,8 +14752,109 @@

61778

ftype = build_function_type_list (intDI_type_node, V2DI_type_node,

61779

integer_type_node, NULL_TREE);

61780

def_builtin ("__builtin_vec_ext_v2di", ftype, VSX_BUILTIN_VEC_EXT_V2DI);

61781

+

61782

+

61783

+ if (V1TI_type_node)

61784

+ {

61785

+ tree v1ti_ftype_long_pcvoid

61786

+ = build_function_type_list (V1TI_type_node,

61787

+ long_integer_type_node, pcvoid_type_node,

61788

+ NULL_TREE);

61789

+ tree void_ftype_v1ti_long_pvoid

61790

+ = build_function_type_list (void_type_node,

61791

+ V1TI_type_node, long_integer_type_node,

61792

+ pvoid_type_node, NULL_TREE);

61793

+ def_builtin ("__builtin_vsx_lxvd2x_v1ti", v1ti_ftype_long_pcvoid,

61794

+ VSX_BUILTIN_LXVD2X_V1TI);

61795

+ def_builtin ("__builtin_vsx_stxvd2x_v1ti", void_ftype_v1ti_long_pvoid,

61796

+ VSX_BUILTIN_STXVD2X_V1TI);

61797

+ ftype = build_function_type_list (V1TI_type_node, intTI_type_node,

61798

+ NULL_TREE, NULL_TREE);

61799

+ def_builtin ("__builtin_vec_init_v1ti", ftype, VSX_BUILTIN_VEC_INIT_V1TI);

61800

+ ftype = build_function_type_list (V1TI_type_node, V1TI_type_node,

61801

+ intTI_type_node,

61802

+ integer_type_node, NULL_TREE);

61803

+ def_builtin ("__builtin_vec_set_v1ti", ftype, VSX_BUILTIN_VEC_SET_V1TI);

61804

+ ftype = build_function_type_list (intTI_type_node, V1TI_type_node,

61805

+ integer_type_node, NULL_TREE);

61806

+ def_builtin ("__builtin_vec_ext_v1ti", ftype, VSX_BUILTIN_VEC_EXT_V1TI);

61807

+ }

61808

+

61809

}

61810

61811

+static void

61812

+htm_init_builtins (void)

61813

+{

61814

+ HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;

61815

+ const struct builtin_description *d;

61816

+ size_t i;

61817

+

61818

+ d = bdesc_htm;

61819

+ for (i = 0; i < ARRAY_SIZE (bdesc_htm); i++, d++)

61820

+ {

61821

+ tree op[MAX_HTM_OPERANDS], type;

61822

+ HOST_WIDE_INT mask = d->mask;

61823

+ unsigned attr = rs6000_builtin_info[d->code].attr;

61824

+ bool void_func = (attr & RS6000_BTC_VOID);

61825

+ int attr_args = (attr & RS6000_BTC_TYPE_MASK);

61826

+ int nopnds = 0;

61827

+ tree argtype = (attr & RS6000_BTC_SPR) ? long_unsigned_type_node

61828

+ : unsigned_type_node;

61829

+

61830

+ if ((mask & builtin_mask) != mask)

61831

+ {

61832

+ if (TARGET_DEBUG_BUILTIN)

61833

+ fprintf (stderr, "htm_builtin, skip binary %s\n", d->name);

61834

+ continue;

61835

+ }

61836

+

61837

+ if (d->name == 0)

61838

+ {

61839

+ if (TARGET_DEBUG_BUILTIN)

61840

+ fprintf (stderr, "htm_builtin, bdesc_htm[%ld] no name\n",

61841

+ (long unsigned) i);

61842

+ continue;

61843

+ }

61844

+

61845

+ op[nopnds++] = (void_func) ? void_type_node : argtype;

61846

+

61847

+ if (attr_args == RS6000_BTC_UNARY)

61848

+ op[nopnds++] = argtype;

61849

+ else if (attr_args == RS6000_BTC_BINARY)

61850

+ {

61851

+ op[nopnds++] = argtype;

61852

+ op[nopnds++] = argtype;

61853

+ }

61854

+ else if (attr_args == RS6000_BTC_TERNARY)

61855

+ {

61856

+ op[nopnds++] = argtype;

61857

+ op[nopnds++] = argtype;

61858

+ op[nopnds++] = argtype;

61859

+ }

61860

+

61861

+ switch (nopnds)

61862

+ {

61863

+ case 1:

61864

+ type = build_function_type_list (op[0], NULL_TREE);

61865

+ break;

61866

+ case 2:

61867

+ type = build_function_type_list (op[0], op[1], NULL_TREE);

61868

+ break;

61869

+ case 3:

61870

+ type = build_function_type_list (op[0], op[1], op[2], NULL_TREE);

61871

+ break;

61872

+ case 4:

61873

+ type = build_function_type_list (op[0], op[1], op[2], op[3],

61874

+ NULL_TREE);

61875

+ break;

61876

+ default:

61877

+ gcc_unreachable ();

61878

+ }

61879

+

61880

+ def_builtin (d->name, type, d->code);

61881

+ }

61882

+}

61883

+

61884

/* Hash function for builtin functions with up to 3 arguments and a return

61885

type. */

61886

static unsigned

61887

@@ -12572,11 +14928,34 @@

61888

are type correct. */

61889

switch (builtin)

61890

{

61891

+ /* unsigned 1 argument functions. */

61892

+ case CRYPTO_BUILTIN_VSBOX:

61893

+ case P8V_BUILTIN_VGBBD:

61894

+ case MISC_BUILTIN_CDTBCD:

61895

+ case MISC_BUILTIN_CBCDTD:

61896

+ h.uns_p[0] = 1;

61897

+ h.uns_p[1] = 1;

61898

+ break;

61899

+

61900

/* unsigned 2 argument functions. */

61901

case ALTIVEC_BUILTIN_VMULEUB_UNS:

61902

case ALTIVEC_BUILTIN_VMULEUH_UNS:

61903

case ALTIVEC_BUILTIN_VMULOUB_UNS:

61904

case ALTIVEC_BUILTIN_VMULOUH_UNS:

61905

+ case CRYPTO_BUILTIN_VCIPHER:

61906

+ case CRYPTO_BUILTIN_VCIPHERLAST:

61907

+ case CRYPTO_BUILTIN_VNCIPHER:

61908

+ case CRYPTO_BUILTIN_VNCIPHERLAST:

61909

+ case CRYPTO_BUILTIN_VPMSUMB:

61910

+ case CRYPTO_BUILTIN_VPMSUMH:

61911

+ case CRYPTO_BUILTIN_VPMSUMW:

61912

+ case CRYPTO_BUILTIN_VPMSUMD:

61913

+ case CRYPTO_BUILTIN_VPMSUM:

61914

+ case MISC_BUILTIN_ADDG6S:

61915

+ case MISC_BUILTIN_DIVWEU:

61916

+ case MISC_BUILTIN_DIVWEUO:

61917

+ case MISC_BUILTIN_DIVDEU:

61918

+ case MISC_BUILTIN_DIVDEUO:

61919

h.uns_p[0] = 1;

61920

h.uns_p[1] = 1;

61921

h.uns_p[2] = 1;

61922

@@ -12599,6 +14978,14 @@

61923

case VSX_BUILTIN_XXSEL_8HI_UNS:

61924

case VSX_BUILTIN_XXSEL_4SI_UNS:

61925

case VSX_BUILTIN_XXSEL_2DI_UNS:

61926

+ case CRYPTO_BUILTIN_VPERMXOR:

61927

+ case CRYPTO_BUILTIN_VPERMXOR_V2DI:

61928

+ case CRYPTO_BUILTIN_VPERMXOR_V4SI:

61929

+ case CRYPTO_BUILTIN_VPERMXOR_V8HI:

61930

+ case CRYPTO_BUILTIN_VPERMXOR_V16QI:

61931

+ case CRYPTO_BUILTIN_VSHASIGMAW:

61932

+ case CRYPTO_BUILTIN_VSHASIGMAD:

61933

+ case CRYPTO_BUILTIN_VSHASIGMA:

61934

h.uns_p[0] = 1;

61935

h.uns_p[1] = 1;

61936

h.uns_p[2] = 1;

61937

@@ -12630,9 +15017,18 @@

61938

/* signed args, unsigned return. */

61939

case VSX_BUILTIN_XVCVDPUXDS_UNS:

61940

case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI:

61941

+ case MISC_BUILTIN_UNPACK_TD:

61942

+ case MISC_BUILTIN_UNPACK_V1TI:

61943

h.uns_p[0] = 1;

61944

break;

61945

61946

+ /* unsigned arguments for 128-bit pack instructions. */

61947

+ case MISC_BUILTIN_PACK_TD:

61948

+ case MISC_BUILTIN_PACK_V1TI:

61949

+ h.uns_p[1] = 1;

61950

+ h.uns_p[2] = 1;

61951

+ break;

61952

+

61953

default:

61954

break;

61955

}

61956

@@ -12740,9 +15136,24 @@

61957

else

61958

{

61959

enum insn_code icode = d->icode;

61960

- if (d->name == 0 || icode == CODE_FOR_nothing)

61961

- continue;

61962

+ if (d->name == 0)

61963

+ {

61964

+ if (TARGET_DEBUG_BUILTIN)

61965

+ fprintf (stderr, "rs6000_builtin, bdesc_3arg[%ld] no name\n",

61966

+ (long unsigned)i);

61967

61968

+ continue;

61969

+ }

61970

+

61971

+ if (icode == CODE_FOR_nothing)

61972

+ {

61973

+ if (TARGET_DEBUG_BUILTIN)

61974

+ fprintf (stderr, "rs6000_builtin, skip ternary %s (no code)\n",

61975

+ d->name);

61976

+

61977

+ continue;

61978

+ }

61979

+

61980

type = builtin_function_type (insn_data[icode].operand[0].mode,

61981

insn_data[icode].operand[1].mode,

61982

insn_data[icode].operand[2].mode,

61983

@@ -12780,9 +15191,24 @@

61984

else

61985

{

61986

enum insn_code icode = d->icode;

61987

- if (d->name == 0 || icode == CODE_FOR_nothing)

61988

- continue;

61989

+ if (d->name == 0)

61990

+ {

61991

+ if (TARGET_DEBUG_BUILTIN)

61992

+ fprintf (stderr, "rs6000_builtin, bdesc_2arg[%ld] no name\n",

61993

+ (long unsigned)i);

61994

61995

+ continue;

61996

+ }

61997

+

61998

+ if (icode == CODE_FOR_nothing)

61999

+ {

62000

+ if (TARGET_DEBUG_BUILTIN)

62001

+ fprintf (stderr, "rs6000_builtin, skip binary %s (no code)\n",

62002

+ d->name);

62003

+

62004

+ continue;

62005

+ }

62006

+

62007

mode0 = insn_data[icode].operand[0].mode;

62008

mode1 = insn_data[icode].operand[1].mode;

62009

mode2 = insn_data[icode].operand[2].mode;

62010

@@ -12842,9 +15268,24 @@

62011

else

62012

{

62013

enum insn_code icode = d->icode;

62014

- if (d->name == 0 || icode == CODE_FOR_nothing)

62015

- continue;

62016

+ if (d->name == 0)

62017

+ {

62018

+ if (TARGET_DEBUG_BUILTIN)

62019

+ fprintf (stderr, "rs6000_builtin, bdesc_1arg[%ld] no name\n",

62020

+ (long unsigned)i);

62021

62022

+ continue;

62023

+ }

62024

+

62025

+ if (icode == CODE_FOR_nothing)

62026

+ {

62027

+ if (TARGET_DEBUG_BUILTIN)

62028

+ fprintf (stderr, "rs6000_builtin, skip unary %s (no code)\n",

62029

+ d->name);

62030

+

62031

+ continue;

62032

+ }

62033

+

62034

mode0 = insn_data[icode].operand[0].mode;

62035

mode1 = insn_data[icode].operand[1].mode;

62036

62037

@@ -13631,7 +16072,7 @@

62038

static bool eliminated = false;

62039

rtx ret;

62040

62041

- if (mode != SDmode)

62042

+ if (mode != SDmode || TARGET_NO_SDMODE_STACK)

62043

ret = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);

62044

else

62045

{

62046

@@ -13660,6 +16101,17 @@

62047

return ret;

62048

}

62049

62050

+/* Return the mode to be used for memory when a secondary memory

62051

+ location is needed. For SDmode values we need to use DDmode, in

62052

+ all other cases we can use the same mode. */

62053

+enum machine_mode

62054

+rs6000_secondary_memory_needed_mode (enum machine_mode mode)

62055

+{

62056

+ if (mode == SDmode)

62057

+ return DDmode;

62058

+ return mode;

62059

+}

62060

+

62061

static tree

62062

rs6000_check_sdmode (tree *tp, int *walk_subtrees, void *data ATTRIBUTE_UNUSED)

62063

{

62064

@@ -13690,31 +16142,228 @@

62065

return NULL_TREE;

62066

}

62067

62068

-enum reload_reg_type {

62069

- GPR_REGISTER_TYPE,

62070

- VECTOR_REGISTER_TYPE,

62071

- OTHER_REGISTER_TYPE

62072

-};

62073

+/* Classify a register type. Because the FMRGOW/FMRGEW instructions only work

62074

+ on traditional floating point registers, and the VMRGOW/VMRGEW instructions

62075

+ only work on the traditional altivec registers, note if an altivec register

62076

+ was chosen. */

62077

62078

-static enum reload_reg_type

62079

-rs6000_reload_register_type (enum reg_class rclass)

62080

+static enum rs6000_reg_type

62081

+register_to_reg_type (rtx reg, bool *is_altivec)

62082

{

62083

- switch (rclass)

62084

+ HOST_WIDE_INT regno;

62085

+ enum reg_class rclass;

62086

+

62087

+ if (GET_CODE (reg) == SUBREG)

62088

+ reg = SUBREG_REG (reg);

62089

+

62090

+ if (!REG_P (reg))

62091

+ return NO_REG_TYPE;

62092

+

62093

+ regno = REGNO (reg);

62094

+ if (regno >= FIRST_PSEUDO_REGISTER)

62095

{

62096

- case GENERAL_REGS:

62097

- case BASE_REGS:

62098

- return GPR_REGISTER_TYPE;

62099

+ if (!lra_in_progress && !reload_in_progress && !reload_completed)

62100

+ return PSEUDO_REG_TYPE;

62101

62102

- case FLOAT_REGS:

62103

- case ALTIVEC_REGS:

62104

- case VSX_REGS:

62105

- return VECTOR_REGISTER_TYPE;

62106

+ regno = true_regnum (reg);

62107

+ if (regno < 0 || regno >= FIRST_PSEUDO_REGISTER)

62108

+ return PSEUDO_REG_TYPE;

62109

+ }

62110

62111

- default:

62112

- return OTHER_REGISTER_TYPE;

62113

+ gcc_assert (regno >= 0);

62114

+

62115

+ if (is_altivec && ALTIVEC_REGNO_P (regno))

62116

+ *is_altivec = true;

62117

+

62118

+ rclass = rs6000_regno_regclass[regno];

62119

+ return reg_class_to_reg_type[(int)rclass];

62120

+}

62121

+

62122

+/* Helper function for rs6000_secondary_reload to return true if a move to a

62123

+ different register classe is really a simple move. */

62124

+

62125

+static bool

62126

+rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type,

62127

+ enum rs6000_reg_type from_type,

62128

+ enum machine_mode mode)

62129

+{

62130

+ int size;

62131

+

62132

+ /* Add support for various direct moves available. In this function, we only

62133

+ look at cases where we don't need any extra registers, and one or more

62134

+ simple move insns are issued. At present, 32-bit integers are not allowed

62135

+ in FPR/VSX registers. Single precision binary floating is not a simple

62136

+ move because we need to convert to the single precision memory layout.

62137

+ The 4-byte SDmode can be moved. */

62138

+ size = GET_MODE_SIZE (mode);

62139

+ if (TARGET_DIRECT_MOVE

62140

+ && ((mode == SDmode) || (TARGET_POWERPC64 && size == 8))

62141

+ && ((to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)

62142

+ || (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)))

62143

+ return true;

62144

+

62145

+ else if (TARGET_MFPGPR && TARGET_POWERPC64 && size == 8

62146

+ && ((to_type == GPR_REG_TYPE && from_type == FPR_REG_TYPE)

62147

+ || (to_type == FPR_REG_TYPE && from_type == GPR_REG_TYPE)))

62148

+ return true;

62149

+

62150

+ else if ((size == 4 || (TARGET_POWERPC64 && size == 8))

62151

+ && ((to_type == GPR_REG_TYPE && from_type == SPR_REG_TYPE)

62152

+ || (to_type == SPR_REG_TYPE && from_type == GPR_REG_TYPE)))

62153

+ return true;

62154

+

62155

+ return false;

62156

+}

62157

+

62158

+/* Power8 helper function for rs6000_secondary_reload, handle all of the

62159

+ special direct moves that involve allocating an extra register, return the

62160

+ insn code of the helper function if there is such a function or

62161

+ CODE_FOR_nothing if not. */

62162

+

62163

+static bool

62164

+rs6000_secondary_reload_direct_move (enum rs6000_reg_type to_type,

62165

+ enum rs6000_reg_type from_type,

62166

+ enum machine_mode mode,

62167

+ secondary_reload_info *sri,

62168

+ bool altivec_p)

62169

+{

62170

+ bool ret = false;

62171

+ enum insn_code icode = CODE_FOR_nothing;

62172

+ int cost = 0;

62173

+ int size = GET_MODE_SIZE (mode);

62174

+

62175

+ if (TARGET_POWERPC64)

62176

+ {

62177

+ if (size == 16)

62178

+ {

62179

+ /* Handle moving 128-bit values from GPRs to VSX point registers on

62180

+ power8 when running in 64-bit mode using XXPERMDI to glue the two

62181

+ 64-bit values back together. */

62182

+ if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)

62183

+ {

62184

+ cost = 3; /* 2 mtvsrd's, 1 xxpermdi. */

62185

+ icode = reg_addr[mode].reload_vsx_gpr;

62186

+ }

62187

+

62188

+ /* Handle moving 128-bit values from VSX point registers to GPRs on

62189

+ power8 when running in 64-bit mode using XXPERMDI to get access to the

62190

+ bottom 64-bit value. */

62191

+ else if (to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)

62192

+ {

62193

+ cost = 3; /* 2 mfvsrd's, 1 xxpermdi. */

62194

+ icode = reg_addr[mode].reload_gpr_vsx;

62195

+ }

62196

+ }

62197

+

62198

+ else if (mode == SFmode)

62199

+ {

62200

+ if (to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)

62201

+ {

62202

+ cost = 3; /* xscvdpspn, mfvsrd, and. */

62203

+ icode = reg_addr[mode].reload_gpr_vsx;

62204

+ }

62205

+

62206

+ else if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)

62207

+ {

62208

+ cost = 2; /* mtvsrz, xscvspdpn. */

62209

+ icode = reg_addr[mode].reload_vsx_gpr;

62210

+ }

62211

+ }

62212

}

62213

+

62214

+ if (TARGET_POWERPC64 && size == 16)

62215

+ {

62216

+ /* Handle moving 128-bit values from GPRs to VSX point registers on

62217

+ power8 when running in 64-bit mode using XXPERMDI to glue the two

62218

+ 64-bit values back together. */

62219

+ if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)

62220

+ {

62221

+ cost = 3; /* 2 mtvsrd's, 1 xxpermdi. */

62222

+ icode = reg_addr[mode].reload_vsx_gpr;

62223

+ }

62224

+

62225

+ /* Handle moving 128-bit values from VSX point registers to GPRs on

62226

+ power8 when running in 64-bit mode using XXPERMDI to get access to the

62227

+ bottom 64-bit value. */

62228

+ else if (to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)

62229

+ {

62230

+ cost = 3; /* 2 mfvsrd's, 1 xxpermdi. */

62231

+ icode = reg_addr[mode].reload_gpr_vsx;

62232

+ }

62233

+ }

62234

+

62235

+ else if (!TARGET_POWERPC64 && size == 8)

62236

+ {

62237

+ /* Handle moving 64-bit values from GPRs to floating point registers on

62238

+ power8 when running in 32-bit mode using FMRGOW to glue the two 32-bit

62239

+ values back together. Altivec register classes must be handled

62240

+ specially since a different instruction is used, and the secondary

62241

+ reload support requires a single instruction class in the scratch

62242

+ register constraint. However, right now TFmode is not allowed in

62243

+ Altivec registers, so the pattern will never match. */

62244

+ if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE && !altivec_p)

62245

+ {

62246

+ cost = 3; /* 2 mtvsrwz's, 1 fmrgow. */

62247

+ icode = reg_addr[mode].reload_fpr_gpr;

62248

+ }

62249

+ }

62250

+

62251

+ if (icode != CODE_FOR_nothing)

62252

+ {

62253

+ ret = true;

62254

+ if (sri)

62255

+ {

62256

+ sri->icode = icode;

62257

+ sri->extra_cost = cost;

62258

+ }

62259

+ }

62260

+

62261

+ return ret;

62262

}

62263

62264

+/* Return whether a move between two register classes can be done either

62265

+ directly (simple move) or via a pattern that uses a single extra temporary

62266

+ (using power8's direct move in this case. */

62267

+

62268

+static bool

62269

+rs6000_secondary_reload_move (enum rs6000_reg_type to_type,

62270

+ enum rs6000_reg_type from_type,

62271

+ enum machine_mode mode,

62272

+ secondary_reload_info *sri,

62273

+ bool altivec_p)

62274

+{

62275

+ /* Fall back to load/store reloads if either type is not a register. */

62276

+ if (to_type == NO_REG_TYPE || from_type == NO_REG_TYPE)

62277

+ return false;

62278

+

62279

+ /* If we haven't allocated registers yet, assume the move can be done for the

62280

+ standard register types. */

62281

+ if ((to_type == PSEUDO_REG_TYPE && from_type == PSEUDO_REG_TYPE)

62282

+ || (to_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE (from_type))

62283

+ || (from_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE (to_type)))

62284

+ return true;

62285

+

62286

+ /* Moves to the same set of registers is a simple move for non-specialized

62287

+ registers. */

62288

+ if (to_type == from_type && IS_STD_REG_TYPE (to_type))

62289

+ return true;

62290

+

62291

+ /* Check whether a simple move can be done directly. */

62292

+ if (rs6000_secondary_reload_simple_move (to_type, from_type, mode))

62293

+ {

62294

+ if (sri)

62295

+ {

62296

+ sri->icode = CODE_FOR_nothing;

62297

+ sri->extra_cost = 0;

62298

+ }

62299

+ return true;

62300

+ }

62301

+

62302

+ /* Now check if we can do it in a few steps. */

62303

+ return rs6000_secondary_reload_direct_move (to_type, from_type, mode, sri,

62304

+ altivec_p);

62305

+}

62306

+

62307

/* Inform reload about cases where moving X with a mode MODE to a register in

62308

RCLASS requires an extra scratch or immediate register. Return the class

62309

needed for the immediate register.

62310

@@ -13738,12 +16387,36 @@

62311

bool default_p = false;

62312

62313

sri->icode = CODE_FOR_nothing;

62314

+ icode = ((in_p)

62315

+ ? reg_addr[mode].reload_load

62316

+ : reg_addr[mode].reload_store);

62317

62318

- /* Convert vector loads and stores into gprs to use an additional base

62319

- register. */

62320

- icode = rs6000_vector_reload[mode][in_p != false];

62321

- if (icode != CODE_FOR_nothing)

62322

+ if (REG_P (x) || register_operand (x, mode))

62323

{

62324

+ enum rs6000_reg_type to_type = reg_class_to_reg_type[(int)rclass];

62325

+ bool altivec_p = (rclass == ALTIVEC_REGS);

62326

+ enum rs6000_reg_type from_type = register_to_reg_type (x, &altivec_p);

62327

+

62328

+ if (!in_p)

62329

+ {

62330

+ enum rs6000_reg_type exchange = to_type;

62331

+ to_type = from_type;

62332

+ from_type = exchange;

62333

+ }

62334

+

62335

+ /* Can we do a direct move of some sort? */

62336

+ if (rs6000_secondary_reload_move (to_type, from_type, mode, sri,

62337

+ altivec_p))

62338

+ {

62339

+ icode = (enum insn_code)sri->icode;

62340

+ default_p = false;

62341

+ ret = NO_REGS;

62342

+ }

62343

+ }

62344

+

62345

+ /* Handle vector moves with reload helper functions. */

62346

+ if (ret == ALL_REGS && icode != CODE_FOR_nothing)

62347

+ {

62348

ret = NO_REGS;

62349

sri->icode = CODE_FOR_nothing;

62350

sri->extra_cost = 0;

62351

@@ -13754,14 +16427,23 @@

62352

62353

/* Loads to and stores from gprs can do reg+offset, and wouldn't need

62354

an extra register in that case, but it would need an extra

62355

- register if the addressing is reg+reg or (reg+reg)&(-16). */

62356

+ register if the addressing is reg+reg or (reg+reg)&(-16). Special

62357

+ case load/store quad. */

62358

if (rclass == GENERAL_REGS || rclass == BASE_REGS)

62359

{

62360

- if (!legitimate_indirect_address_p (addr, false)

62361

- && !rs6000_legitimate_offset_address_p (TImode, addr,

62362

- false, true))

62363

+ if (TARGET_POWERPC64 && TARGET_QUAD_MEMORY

62364

+ && GET_MODE_SIZE (mode) == 16

62365

+ && quad_memory_operand (x, mode))

62366

{

62367

sri->icode = icode;

62368

+ sri->extra_cost = 2;

62369

+ }

62370

+

62371

+ else if (!legitimate_indirect_address_p (addr, false)

62372

+ && !rs6000_legitimate_offset_address_p (PTImode, addr,

62373

+ false, true))

62374

+ {

62375

+ sri->icode = icode;

62376

/* account for splitting the loads, and converting the

62377

address from reg+reg to reg. */

62378

sri->extra_cost = (((TARGET_64BIT) ? 3 : 5)

62379

@@ -13768,8 +16450,20 @@

62380

+ ((GET_CODE (addr) == AND) ? 1 : 0));

62381

}

62382

}

62383

- /* Loads to and stores from vector registers can only do reg+reg

62384

- addressing. Altivec registers can also do (reg+reg)&(-16). */

62385

+ /* Allow scalar loads to/from the traditional floating point

62386

+ registers, even if VSX memory is set. */

62387

+ else if ((rclass == FLOAT_REGS || rclass == NO_REGS)

62388

+ && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8)

62389

+ && (legitimate_indirect_address_p (addr, false)

62390

+ || legitimate_indirect_address_p (addr, false)

62391

+ || rs6000_legitimate_offset_address_p (mode, addr,

62392

+ false, true)))

62393

+

62394

+ ;

62395

+ /* Loads to and stores from vector registers can only do reg+reg

62396

+ addressing. Altivec registers can also do (reg+reg)&(-16). Allow

62397

+ scalar modes loading up the traditional floating point registers

62398

+ to use offset addresses. */

62399

else if (rclass == VSX_REGS || rclass == ALTIVEC_REGS

62400

|| rclass == FLOAT_REGS || rclass == NO_REGS)

62401

{

62402

@@ -13813,12 +16507,12 @@

62403

else

62404

{

62405

enum reg_class xclass = REGNO_REG_CLASS (regno);

62406

- enum reload_reg_type rtype1 = rs6000_reload_register_type (rclass);

62407

- enum reload_reg_type rtype2 = rs6000_reload_register_type (xclass);

62408

+ enum rs6000_reg_type rtype1 = reg_class_to_reg_type[(int)rclass];

62409

+ enum rs6000_reg_type rtype2 = reg_class_to_reg_type[(int)xclass];

62410

62411

/* If memory is needed, use default_secondary_reload to create the

62412

stack slot. */

62413

- if (rtype1 != rtype2 || rtype1 == OTHER_REGISTER_TYPE)

62414

+ if (rtype1 != rtype2 || !IS_STD_REG_TYPE (rtype1))

62415

default_p = true;

62416

else

62417

ret = NO_REGS;

62418

@@ -13828,7 +16522,7 @@

62419

default_p = true;

62420

}

62421

else if (TARGET_POWERPC64

62422

- && rs6000_reload_register_type (rclass) == GPR_REGISTER_TYPE

62423

+ && reg_class_to_reg_type[(int)rclass] == GPR_REG_TYPE

62424

&& MEM_P (x)

62425

&& GET_MODE_SIZE (GET_MODE (x)) >= UNITS_PER_WORD)

62426

{

62427

@@ -13867,7 +16561,7 @@

62428

default_p = true;

62429

}

62430

else if (!TARGET_POWERPC64

62431

- && rs6000_reload_register_type (rclass) == GPR_REGISTER_TYPE

62432

+ && reg_class_to_reg_type[(int)rclass] == GPR_REG_TYPE

62433

&& MEM_P (x)

62434

&& GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)

62435

{

62436

@@ -13945,6 +16639,36 @@

62437

return ret;

62438

}

62439

62440

+/* Better tracing for rs6000_secondary_reload_inner. */

62441

+

62442

+static void

62443

+rs6000_secondary_reload_trace (int line, rtx reg, rtx mem, rtx scratch,

62444

+ bool store_p)

62445

+{

62446

+ rtx set, clobber;

62447

+

62448

+ gcc_assert (reg != NULL_RTX && mem != NULL_RTX && scratch != NULL_RTX);

62449

+

62450

+ fprintf (stderr, "rs6000_secondary_reload_inner:%d, type = %s\n", line,

62451

+ store_p ? "store" : "load");

62452

+

62453

+ if (store_p)

62454

+ set = gen_rtx_SET (VOIDmode, mem, reg);

62455

+ else

62456

+ set = gen_rtx_SET (VOIDmode, reg, mem);

62457

+

62458

+ clobber = gen_rtx_CLOBBER (VOIDmode, scratch);

62459

+ debug_rtx (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));

62460

+}

62461

+

62462

+static void

62463

+rs6000_secondary_reload_fail (int line, rtx reg, rtx mem, rtx scratch,

62464

+ bool store_p)

62465

+{

62466

+ rs6000_secondary_reload_trace (line, reg, mem, scratch, store_p);

62467

+ gcc_unreachable ();

62468

+}

62469

+

62470

/* Fixup reload addresses for Altivec or VSX loads/stores to change SP+offset

62471

to SP+reg addressing. */

62472

62473

@@ -13963,21 +16687,16 @@

62474

rtx cc_clobber;

62475

62476

if (TARGET_DEBUG_ADDR)

62477

- {

62478

- fprintf (stderr, "\nrs6000_secondary_reload_inner, type = %s\n",

62479

- store_p ? "store" : "load");

62480

- fprintf (stderr, "reg:\n");

62481

- debug_rtx (reg);

62482

- fprintf (stderr, "mem:\n");

62483

- debug_rtx (mem);

62484

- fprintf (stderr, "scratch:\n");

62485

- debug_rtx (scratch);

62486

- }

62487

+ rs6000_secondary_reload_trace (__LINE__, reg, mem, scratch, store_p);

62488

62489

- gcc_assert (regno >= 0 && regno < FIRST_PSEUDO_REGISTER);

62490

- gcc_assert (GET_CODE (mem) == MEM);

62491

+ if (regno < 0 || regno >= FIRST_PSEUDO_REGISTER)

62492

+ rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);

62493

+

62494

+ if (GET_CODE (mem) != MEM)

62495

+ rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);

62496

+

62497

rclass = REGNO_REG_CLASS (regno);

62498

- addr = XEXP (mem, 0);

62499

+ addr = find_replacement (&XEXP (mem, 0));

62500

62501

switch (rclass)

62502

{

62503

@@ -13988,25 +16707,31 @@

62504

if (GET_CODE (addr) == AND)

62505

{

62506

and_op2 = XEXP (addr, 1);

62507

- addr = XEXP (addr, 0);

62508

+ addr = find_replacement (&XEXP (addr, 0));

62509

}

62510

62511

if (GET_CODE (addr) == PRE_MODIFY)

62512

{

62513

- scratch_or_premodify = XEXP (addr, 0);

62514

- gcc_assert (REG_P (scratch_or_premodify));

62515

- gcc_assert (GET_CODE (XEXP (addr, 1)) == PLUS);

62516

- addr = XEXP (addr, 1);

62517

+ scratch_or_premodify = find_replacement (&XEXP (addr, 0));

62518

+ if (!REG_P (scratch_or_premodify))

62519

+ rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);

62520

+

62521

+ addr = find_replacement (&XEXP (addr, 1));

62522

+ if (GET_CODE (addr) != PLUS)

62523

+ rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);

62524

}

62525

62526

if (GET_CODE (addr) == PLUS

62527

&& (and_op2 != NULL_RTX

62528

- || !rs6000_legitimate_offset_address_p (TImode, addr,

62529

+ || !rs6000_legitimate_offset_address_p (PTImode, addr,

62530

false, true)))

62531

{

62532

+ /* find_replacement already recurses into both operands of

62533

+ PLUS so we don't need to call it here. */

62534

addr_op1 = XEXP (addr, 0);

62535

addr_op2 = XEXP (addr, 1);

62536

- gcc_assert (legitimate_indirect_address_p (addr_op1, false));

62537

+ if (!legitimate_indirect_address_p (addr_op1, false))

62538

+ rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);

62539

62540

if (!REG_P (addr_op2)

62541

&& (GET_CODE (addr_op2) != CONST_INT

62542

@@ -14034,7 +16759,7 @@

62543

scratch_or_premodify = scratch;

62544

}

62545

else if (!legitimate_indirect_address_p (addr, false)

62546

- && !rs6000_legitimate_offset_address_p (TImode, addr,

62547

+ && !rs6000_legitimate_offset_address_p (PTImode, addr,

62548

false, true))

62549

{

62550

if (TARGET_DEBUG_ADDR)

62551

@@ -14050,9 +16775,21 @@

62552

}

62553

break;

62554

62555

- /* Float/Altivec registers can only handle reg+reg addressing. Move

62556

- other addresses into a scratch register. */

62557

+ /* Float registers can do offset+reg addressing for scalar types. */

62558

case FLOAT_REGS:

62559

+ if (legitimate_indirect_address_p (addr, false) /* reg */

62560

+ || legitimate_indexed_address_p (addr, false) /* reg+reg */

62561

+ || ((GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8)

62562

+ && and_op2 == NULL_RTX

62563

+ && scratch_or_premodify == scratch

62564

+ && rs6000_legitimate_offset_address_p (mode, addr, false, false)))

62565

+ break;

62566

+

62567

+ /* If this isn't a legacy floating point load/store, fall through to the

62568

+ VSX defaults. */

62569

+

62570

+ /* VSX/Altivec registers can only handle reg+reg addressing. Move other

62571

+ addresses into a scratch register. */

62572

case VSX_REGS:

62573

case ALTIVEC_REGS:

62574

62575

@@ -14066,35 +16803,35 @@

62576

|| !VECTOR_MEM_ALTIVEC_P (mode)))

62577

{

62578

and_op2 = XEXP (addr, 1);

62579

- addr = XEXP (addr, 0);

62580

+ addr = find_replacement (&XEXP (addr, 0));

62581

}

62582

62583

/* If we aren't using a VSX load, save the PRE_MODIFY register and use it

62584

as the address later. */

62585

if (GET_CODE (addr) == PRE_MODIFY

62586

- && (!VECTOR_MEM_VSX_P (mode)

62587

+ && ((ALTIVEC_OR_VSX_VECTOR_MODE (mode)

62588

+ && (rclass != FLOAT_REGS

62589

+ || (GET_MODE_SIZE (mode) != 4 && GET_MODE_SIZE (mode) != 8)))

62590

|| and_op2 != NULL_RTX

62591

|| !legitimate_indexed_address_p (XEXP (addr, 1), false)))

62592

{

62593

- scratch_or_premodify = XEXP (addr, 0);

62594

- gcc_assert (legitimate_indirect_address_p (scratch_or_premodify,

62595

- false));

62596

- gcc_assert (GET_CODE (XEXP (addr, 1)) == PLUS);

62597

- addr = XEXP (addr, 1);

62598

+ scratch_or_premodify = find_replacement (&XEXP (addr, 0));

62599

+ if (!legitimate_indirect_address_p (scratch_or_premodify, false))

62600

+ rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);

62601

+

62602

+ addr = find_replacement (&XEXP (addr, 1));

62603

+ if (GET_CODE (addr) != PLUS)

62604

+ rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);

62605

}

62606

62607

if (legitimate_indirect_address_p (addr, false) /* reg */

62608

|| legitimate_indexed_address_p (addr, false) /* reg+reg */

62609

- || GET_CODE (addr) == PRE_MODIFY /* VSX pre-modify */

62610

|| (GET_CODE (addr) == AND /* Altivec memory */

62611

+ && rclass == ALTIVEC_REGS

62612

&& GET_CODE (XEXP (addr, 1)) == CONST_INT

62613

&& INTVAL (XEXP (addr, 1)) == -16

62614

- && VECTOR_MEM_ALTIVEC_P (mode))

62615

- || (rclass == FLOAT_REGS /* legacy float mem */

62616

- && GET_MODE_SIZE (mode) == 8

62617

- && and_op2 == NULL_RTX

62618

- && scratch_or_premodify == scratch

62619

- && rs6000_legitimate_offset_address_p (mode, addr, false, false)))

62620

+ && (legitimate_indirect_address_p (XEXP (addr, 0), false)

62621

+ || legitimate_indexed_address_p (XEXP (addr, 0), false))))

62622

;

62623

62624

else if (GET_CODE (addr) == PLUS)

62625

@@ -14101,7 +16838,8 @@

62626

{

62627

addr_op1 = XEXP (addr, 0);

62628

addr_op2 = XEXP (addr, 1);

62629

- gcc_assert (REG_P (addr_op1));

62630

+ if (!REG_P (addr_op1))

62631

+ rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);

62632

62633

if (TARGET_DEBUG_ADDR)

62634

{

62635

@@ -14120,7 +16858,8 @@

62636

}

62637

62638

else if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == CONST

62639

- || GET_CODE (addr) == CONST_INT || REG_P (addr))

62640

+ || GET_CODE (addr) == CONST_INT || GET_CODE (addr) == LO_SUM

62641

+ || REG_P (addr))

62642

{

62643

if (TARGET_DEBUG_ADDR)

62644

{

62645

@@ -14136,12 +16875,12 @@

62646

}

62647

62648

else

62649

- gcc_unreachable ();

62650

+ rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);

62651

62652

break;

62653

62654

default:

62655

- gcc_unreachable ();

62656

+ rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);

62657

}

62658

62659

/* If the original address involved a pre-modify that we couldn't use the VSX

62660

@@ -14188,7 +16927,7 @@

62661

/* Adjust the address if it changed. */

62662

if (addr != XEXP (mem, 0))

62663

{

62664

- mem = change_address (mem, mode, addr);

62665

+ mem = replace_equiv_address_nv (mem, addr);

62666

if (TARGET_DEBUG_ADDR)

62667

fprintf (stderr, "\nrs6000_secondary_reload_inner, mem adjusted.\n");

62668

}

62669

@@ -14253,8 +16992,10 @@

62670

return;

62671

}

62672

62673

-/* Allocate a 64-bit stack slot to be used for copying SDmode

62674

- values through if this function has any SDmode references. */

62675

+/* Allocate a 64-bit stack slot to be used for copying SDmode values through if

62676

+ this function has any SDmode references. If we are on a power7 or later, we

62677

+ don't need the 64-bit stack slot since the LFIWZX and STIFWX instructions

62678

+ can load/store the value. */

62679

62680

static void

62681

rs6000_alloc_sdmode_stack_slot (void)

62682

@@ -14264,7 +17005,14 @@

62683

gimple_stmt_iterator gsi;

62684

62685

gcc_assert (cfun->machine->sdmode_stack_slot == NULL_RTX);

62686

+ /* We use a different approach for dealing with the secondary

62687

+ memory in LRA. */

62688

+ if (ira_use_lra_p)

62689

+ return;

62690

62691

+ if (TARGET_NO_SDMODE_STACK)

62692

+ return;

62693

+

62694

FOR_EACH_BB (bb)

62695

for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi))

62696

{

62697

@@ -14325,8 +17073,7 @@

62698

{

62699

enum machine_mode mode = GET_MODE (x);

62700

62701

- if (VECTOR_UNIT_VSX_P (mode)

62702

- && x == CONST0_RTX (mode) && VSX_REG_CLASS_P (rclass))

62703

+ if (TARGET_VSX && x == CONST0_RTX (mode) && VSX_REG_CLASS_P (rclass))

62704

return rclass;

62705

62706

if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)

62707

@@ -14334,8 +17081,14 @@

62708

&& easy_vector_constant (x, mode))

62709

return ALTIVEC_REGS;

62710

62711

- if (CONSTANT_P (x) && reg_classes_intersect_p (rclass, FLOAT_REGS))

62712

- return NO_REGS;

62713

+ if ((CONSTANT_P (x) || GET_CODE (x) == PLUS))

62714

+ {

62715

+ if (reg_class_subset_p (GENERAL_REGS, rclass))

62716

+ return GENERAL_REGS;

62717

+ if (reg_class_subset_p (BASE_REGS, rclass))

62718

+ return BASE_REGS;

62719

+ return NO_REGS;

62720

+ }

62721

62722

if (GET_MODE_CLASS (mode) == MODE_INT && rclass == NON_SPECIAL_REGS)

62723

return GENERAL_REGS;

62724

@@ -14349,7 +17102,8 @@

62725

if (GET_MODE_SIZE (mode) <= 8)

62726

return FLOAT_REGS;

62727

62728

- if (VECTOR_UNIT_ALTIVEC_P (mode) || VECTOR_MEM_ALTIVEC_P (mode))

62729

+ if (VECTOR_UNIT_ALTIVEC_P (mode) || VECTOR_MEM_ALTIVEC_P (mode)

62730

+ || mode == V1TImode)

62731

return ALTIVEC_REGS;

62732

62733

return rclass;

62734

@@ -14381,60 +17135,45 @@

62735

set and vice versa. */

62736

62737

static bool

62738

-rs6000_secondary_memory_needed (enum reg_class class1,

62739

- enum reg_class class2,

62740

+rs6000_secondary_memory_needed (enum reg_class from_class,

62741

+ enum reg_class to_class,

62742

enum machine_mode mode)

62743

{

62744

- if (class1 == class2)

62745

- return false;

62746

+ enum rs6000_reg_type from_type, to_type;

62747

+ bool altivec_p = ((from_class == ALTIVEC_REGS)

62748

+ || (to_class == ALTIVEC_REGS));

62749

62750

- /* Under VSX, there are 3 register classes that values could be in (VSX_REGS,

62751

- ALTIVEC_REGS, and FLOAT_REGS). We don't need to use memory to copy

62752

- between these classes. But we need memory for other things that can go in

62753

- FLOAT_REGS like SFmode. */

62754

- if (TARGET_VSX

62755

- && (VECTOR_MEM_VSX_P (mode) || VECTOR_UNIT_VSX_P (mode))

62756

- && (class1 == VSX_REGS || class1 == ALTIVEC_REGS

62757

- || class1 == FLOAT_REGS))

62758

- return (class2 != VSX_REGS && class2 != ALTIVEC_REGS

62759

- && class2 != FLOAT_REGS);

62760

+ /* If a simple/direct move is available, we don't need secondary memory */

62761

+ from_type = reg_class_to_reg_type[(int)from_class];

62762

+ to_type = reg_class_to_reg_type[(int)to_class];

62763

62764

- if (class1 == VSX_REGS || class2 == VSX_REGS)

62765

- return true;

62766

+ if (rs6000_secondary_reload_move (to_type, from_type, mode,

62767

+ (secondary_reload_info *)0, altivec_p))

62768

+ return false;

62769

62770

- if (class1 == FLOAT_REGS

62771

- && (!TARGET_MFPGPR || !TARGET_POWERPC64

62772

- || ((mode != DFmode)

62773

- && (mode != DDmode)

62774

- && (mode != DImode))))

62775

+ /* If we have a floating point or vector register class, we need to use

62776

+ memory to transfer the data. */

62777

+ if (IS_FP_VECT_REG_TYPE (from_type) || IS_FP_VECT_REG_TYPE (to_type))

62778

return true;

62779

62780

- if (class2 == FLOAT_REGS

62781

- && (!TARGET_MFPGPR || !TARGET_POWERPC64

62782

- || ((mode != DFmode)

62783

- && (mode != DDmode)

62784

- && (mode != DImode))))

62785

- return true;

62786

-

62787

- if (class1 == ALTIVEC_REGS || class2 == ALTIVEC_REGS)

62788

- return true;

62789

-

62790

return false;

62791

}

62792

62793

/* Debug version of rs6000_secondary_memory_needed. */

62794

static bool

62795

-rs6000_debug_secondary_memory_needed (enum reg_class class1,

62796

- enum reg_class class2,

62797

+rs6000_debug_secondary_memory_needed (enum reg_class from_class,

62798

+ enum reg_class to_class,

62799

enum machine_mode mode)

62800

{

62801

- bool ret = rs6000_secondary_memory_needed (class1, class2, mode);

62802

+ bool ret = rs6000_secondary_memory_needed (from_class, to_class, mode);

62803

62804

fprintf (stderr,

62805

- "rs6000_secondary_memory_needed, return: %s, class1 = %s, "

62806

- "class2 = %s, mode = %s\n",

62807

- ret ? "true" : "false", reg_class_names[class1],

62808

- reg_class_names[class2], GET_MODE_NAME (mode));

62809

+ "rs6000_secondary_memory_needed, return: %s, from_class = %s, "

62810

+ "to_class = %s, mode = %s\n",

62811

+ ret ? "true" : "false",

62812

+ reg_class_names[from_class],

62813

+ reg_class_names[to_class],

62814

+ GET_MODE_NAME (mode));

62815

62816

return ret;

62817

}

62818

@@ -14498,15 +17237,21 @@

62819

/* Constants, memory, and FP registers can go into FP registers. */

62820

if ((regno == -1 || FP_REGNO_P (regno))

62821

&& (rclass == FLOAT_REGS || rclass == NON_SPECIAL_REGS))

62822

- return (mode != SDmode) ? NO_REGS : GENERAL_REGS;

62823

+ return (mode != SDmode || lra_in_progress) ? NO_REGS : GENERAL_REGS;

62824

62825

/* Memory, and FP/altivec registers can go into fp/altivec registers under

62826

- VSX. */

62827

+ VSX. However, for scalar variables, use the traditional floating point

62828

+ registers so that we can use offset+register addressing. */

62829

if (TARGET_VSX

62830

&& (regno == -1 || VSX_REGNO_P (regno))

62831

&& VSX_REG_CLASS_P (rclass))

62832

- return NO_REGS;

62833

+ {

62834

+ if (GET_MODE_SIZE (mode) < 16)

62835

+ return FLOAT_REGS;

62836

62837

+ return NO_REGS;

62838

+ }

62839

+

62840

/* Memory, and AltiVec registers can go into AltiVec registers. */

62841

if ((regno == -1 || ALTIVEC_REGNO_P (regno))

62842

&& rclass == ALTIVEC_REGS)

62843

@@ -14550,8 +17295,42 @@

62844

if (from_size != to_size)

62845

{

62846

enum reg_class xclass = (TARGET_VSX) ? VSX_REGS : FLOAT_REGS;

62847

- return ((from_size < 8 || to_size < 8 || TARGET_IEEEQUAD)

62848

- && reg_classes_intersect_p (xclass, rclass));

62849

+

62850

+ if (reg_classes_intersect_p (xclass, rclass))

62851

+ {

62852

+ unsigned to_nregs = hard_regno_nregs[FIRST_FPR_REGNO][to];

62853

+ unsigned from_nregs = hard_regno_nregs[FIRST_FPR_REGNO][from];

62854

+

62855

+ /* Don't allow 64-bit types to overlap with 128-bit types that take a

62856

+ single register under VSX because the scalar part of the register

62857

+ is in the upper 64-bits, and not the lower 64-bits. Types like

62858

+ TFmode/TDmode that take 2 scalar register can overlap. 128-bit

62859

+ IEEE floating point can't overlap, and neither can small

62860

+ values. */

62861

+

62862

+ if (TARGET_IEEEQUAD && (to == TFmode || from == TFmode))

62863

+ return true;

62864

+

62865

+ /* TDmode in floating-mode registers must always go into a register

62866

+ pair with the most significant word in the even-numbered register

62867

+ to match ISA requirements. In little-endian mode, this does not

62868

+ match subreg numbering, so we cannot allow subregs. */

62869

+ if (!BYTES_BIG_ENDIAN && (to == TDmode || from == TDmode))

62870

+ return true;

62871

+

62872

+ if (from_size < 8 || to_size < 8)

62873

+ return true;

62874

+

62875

+ if (from_size == 8 && (8 * to_nregs) != to_size)

62876

+ return true;

62877

+

62878

+ if (to_size == 8 && (8 * from_nregs) != from_size)

62879

+ return true;

62880

+

62881

+ return false;

62882

+ }

62883

+ else

62884

+ return false;

62885

}

62886

62887

if (TARGET_E500_DOUBLE

62888

@@ -14565,10 +17344,19 @@

62889

/* Since the VSX register set includes traditional floating point registers

62890

and altivec registers, just check for the size being different instead of

62891

trying to check whether the modes are vector modes. Otherwise it won't

62892

- allow say DF and DI to change classes. */

62893

+ allow say DF and DI to change classes. For types like TFmode and TDmode

62894

+ that take 2 64-bit registers, rather than a single 128-bit register, don't

62895

+ allow subregs of those types to other 128 bit types. */

62896

if (TARGET_VSX && VSX_REG_CLASS_P (rclass))

62897

- return (from_size != 8 && from_size != 16);

62898

+ {

62899

+ unsigned num_regs = (from_size + 15) / 16;

62900

+ if (hard_regno_nregs[FIRST_FPR_REGNO][to] > num_regs

62901

+ || hard_regno_nregs[FIRST_FPR_REGNO][from] > num_regs)

62902

+ return true;

62903

62904

+ return (from_size != 8 && from_size != 16);

62905

+ }

62906

+

62907

if (TARGET_ALTIVEC && rclass == ALTIVEC_REGS

62908

&& (ALTIVEC_VECTOR_MODE (from) + ALTIVEC_VECTOR_MODE (to)) == 1)

62909

return true;

62910

@@ -14598,6 +17386,186 @@

62911

return ret;

62912

}

62913

62914

+/* Return a string to do a move operation of 128 bits of data. */

62915

+

62916

+const char *

62917

+rs6000_output_move_128bit (rtx operands[])

62918

+{

62919

+ rtx dest = operands[0];

62920

+ rtx src = operands[1];

62921

+ enum machine_mode mode = GET_MODE (dest);

62922

+ int dest_regno;

62923

+ int src_regno;

62924

+ bool dest_gpr_p, dest_fp_p, dest_vmx_p, dest_vsx_p;

62925

+ bool src_gpr_p, src_fp_p, src_vmx_p, src_vsx_p;

62926

+

62927

+ if (REG_P (dest))

62928

+ {

62929

+ dest_regno = REGNO (dest);

62930

+ dest_gpr_p = INT_REGNO_P (dest_regno);

62931

+ dest_fp_p = FP_REGNO_P (dest_regno);

62932

+ dest_vmx_p = ALTIVEC_REGNO_P (dest_regno);

62933

+ dest_vsx_p = dest_fp_p | dest_vmx_p;

62934

+ }

62935

+ else

62936

+ {

62937

+ dest_regno = -1;

62938

+ dest_gpr_p = dest_fp_p = dest_vmx_p = dest_vsx_p = false;

62939

+ }

62940

+

62941

+ if (REG_P (src))

62942

+ {

62943

+ src_regno = REGNO (src);

62944

+ src_gpr_p = INT_REGNO_P (src_regno);

62945

+ src_fp_p = FP_REGNO_P (src_regno);

62946

+ src_vmx_p = ALTIVEC_REGNO_P (src_regno);

62947

+ src_vsx_p = src_fp_p | src_vmx_p;

62948

+ }

62949

+ else

62950

+ {

62951

+ src_regno = -1;

62952

+ src_gpr_p = src_fp_p = src_vmx_p = src_vsx_p = false;

62953

+ }

62954

+

62955

+ /* Register moves. */

62956

+ if (dest_regno >= 0 && src_regno >= 0)

62957

+ {

62958

+ if (dest_gpr_p)

62959

+ {

62960

+ if (src_gpr_p)

62961

+ return "#";

62962

+

62963

+ else if (TARGET_VSX && TARGET_DIRECT_MOVE && src_vsx_p)

62964

+ return "#";

62965

+ }

62966

+

62967

+ else if (TARGET_VSX && dest_vsx_p)

62968

+ {

62969

+ if (src_vsx_p)

62970

+ return "xxlor %x0,%x1,%x1";

62971

+

62972

+ else if (TARGET_DIRECT_MOVE && src_gpr_p)

62973

+ return "#";

62974

+ }

62975

+

62976

+ else if (TARGET_ALTIVEC && dest_vmx_p && src_vmx_p)

62977

+ return "vor %0,%1,%1";

62978

+

62979

+ else if (dest_fp_p && src_fp_p)

62980

+ return "#";

62981

+ }

62982

+

62983

+ /* Loads. */

62984

+ else if (dest_regno >= 0 && MEM_P (src))

62985

+ {

62986

+ if (dest_gpr_p)

62987

+ {

62988

+ if (TARGET_QUAD_MEMORY && quad_load_store_p (dest, src))

62989

+ return "lq %0,%1";

62990

+ else

62991

+ return "#";

62992

+ }

62993

+

62994

+ else if (TARGET_ALTIVEC && dest_vmx_p

62995

+ && altivec_indexed_or_indirect_operand (src, mode))

62996

+ return "lvx %0,%y1";

62997

+

62998

+ else if (TARGET_VSX && dest_vsx_p)

62999

+ {

63000

+ if (mode == V16QImode || mode == V8HImode || mode == V4SImode)

63001

+ return "lxvw4x %x0,%y1";

63002

+ else

63003

+ return "lxvd2x %x0,%y1";

63004

+ }

63005

+

63006

+ else if (TARGET_ALTIVEC && dest_vmx_p)

63007

+ return "lvx %0,%y1";

63008

+

63009

+ else if (dest_fp_p)

63010

+ return "#";

63011

+ }

63012

+

63013

+ /* Stores. */

63014

+ else if (src_regno >= 0 && MEM_P (dest))

63015

+ {

63016

+ if (src_gpr_p)

63017

+ {

63018

+ if (TARGET_QUAD_MEMORY && quad_load_store_p (dest, src))

63019

+ return "stq %1,%0";

63020

+ else

63021

+ return "#";

63022

+ }

63023

+

63024

+ else if (TARGET_ALTIVEC && src_vmx_p

63025

+ && altivec_indexed_or_indirect_operand (src, mode))

63026

+ return "stvx %1,%y0";

63027

+

63028

+ else if (TARGET_VSX && src_vsx_p)

63029

+ {

63030

+ if (mode == V16QImode || mode == V8HImode || mode == V4SImode)

63031

+ return "stxvw4x %x1,%y0";

63032

+ else

63033

+ return "stxvd2x %x1,%y0";

63034

+ }

63035

+

63036

+ else if (TARGET_ALTIVEC && src_vmx_p)

63037

+ return "stvx %1,%y0";

63038

+

63039

+ else if (src_fp_p)

63040

+ return "#";

63041

+ }

63042

+

63043

+ /* Constants. */

63044

+ else if (dest_regno >= 0

63045

+ && (GET_CODE (src) == CONST_INT

63046

+ || GET_CODE (src) == CONST_DOUBLE

63047

+ || GET_CODE (src) == CONST_VECTOR))

63048

+ {

63049

+ if (dest_gpr_p)

63050

+ return "#";

63051

+

63052

+ else if (TARGET_VSX && dest_vsx_p && zero_constant (src, mode))

63053

+ return "xxlxor %x0,%x0,%x0";

63054

+

63055

+ else if (TARGET_ALTIVEC && dest_vmx_p)

63056

+ return output_vec_const_move (operands);

63057

+ }

63058

+

63059

+ if (TARGET_DEBUG_ADDR)

63060

+ {

63061

+ fprintf (stderr, "\n===== Bad 128 bit move:\n");

63062

+ debug_rtx (gen_rtx_SET (VOIDmode, dest, src));

63063

+ }

63064

+

63065

+ gcc_unreachable ();

63066

+}

63067

+

63068

+/* Validate a 128-bit move. */

63069

+bool

63070

+rs6000_move_128bit_ok_p (rtx operands[])

63071

+{

63072

+ enum machine_mode mode = GET_MODE (operands[0]);

63073

+ return (gpc_reg_operand (operands[0], mode)

63074

+ || gpc_reg_operand (operands[1], mode));

63075

+}

63076

+

63077

+/* Return true if a 128-bit move needs to be split. */

63078

+bool

63079

+rs6000_split_128bit_ok_p (rtx operands[])

63080

+{

63081

+ if (!reload_completed)

63082

+ return false;

63083

+

63084

+ if (!gpr_or_gpr_p (operands[0], operands[1]))

63085

+ return false;

63086

+

63087

+ if (quad_load_store_p (operands[0], operands[1]))

63088

+ return false;

63089

+

63090

+ return true;

63091

+}

63092

+

63093

+

63094

/* Given a comparison operation, return the bit number in CCR to test. We

63095

know this is a valid comparison.

63096

63097

@@ -14823,6 +17791,7 @@

63098

ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");

63099

break;

63100

63101

+ case ABI_ELFv2:

63102

case ABI_V4:

63103

case ABI_DARWIN:

63104

break;

63105

@@ -15302,7 +18271,7 @@

63106

return;

63107

63108

case 'Y':

63109

- /* Like 'L', for third word of TImode */

63110

+ /* Like 'L', for third word of TImode/PTImode */

63111

if (REG_P (x))

63112

fputs (reg_names[REGNO (x) + 2], file);

63113

else if (MEM_P (x))

63114

@@ -15352,7 +18321,7 @@

63115

return;

63116

63117

case 'Z':

63118

- /* Like 'L', for last word of TImode. */

63119

+ /* Like 'L', for last word of TImode/PTImode. */

63120

if (REG_P (x))

63121

fputs (reg_names[REGNO (x) + 3], file);

63122

else if (MEM_P (x))

63123

@@ -15383,7 +18352,8 @@

63124

if ((TARGET_SPE || TARGET_E500_DOUBLE)

63125

&& (GET_MODE_SIZE (GET_MODE (x)) == 8

63126

|| GET_MODE (x) == TFmode

63127

- || GET_MODE (x) == TImode))

63128

+ || GET_MODE (x) == TImode

63129

+ || GET_MODE (x) == PTImode))

63130

{

63131

/* Handle [reg]. */

63132

if (REG_P (tmp))

63133

@@ -16766,7 +19736,8 @@

63134

}

63135

63136

/* A subroutine of the atomic operation splitters. Emit a load-locked

63137

- instruction in MODE. */

63138

+ instruction in MODE. For QI/HImode, possibly use a pattern than includes

63139

+ the zero_extend operation. */

63140

63141

static void

63142

emit_load_locked (enum machine_mode mode, rtx reg, rtx mem)

63143

@@ -16775,12 +19746,26 @@

63144

63145

switch (mode)

63146

{

63147

+ case QImode:

63148

+ fn = gen_load_lockedqi;

63149

+ break;

63150

+ case HImode:

63151

+ fn = gen_load_lockedhi;

63152

+ break;

63153

case SImode:

63154

- fn = gen_load_lockedsi;

63155

+ if (GET_MODE (mem) == QImode)

63156

+ fn = gen_load_lockedqi_si;

63157

+ else if (GET_MODE (mem) == HImode)

63158

+ fn = gen_load_lockedhi_si;

63159

+ else

63160

+ fn = gen_load_lockedsi;

63161

break;

63162

case DImode:

63163

fn = gen_load_lockeddi;

63164

break;

63165

+ case TImode:

63166

+ fn = gen_load_lockedti;

63167

+ break;

63168

default:

63169

gcc_unreachable ();

63170

}

63171

@@ -16797,6 +19782,12 @@

63172

63173

switch (mode)

63174

{

63175

+ case QImode:

63176

+ fn = gen_store_conditionalqi;

63177

+ break;

63178

+ case HImode:

63179

+ fn = gen_store_conditionalhi;

63180

+ break;

63181

case SImode:

63182

fn = gen_store_conditionalsi;

63183

break;

63184

@@ -16803,6 +19794,9 @@

63185

case DImode:

63186

fn = gen_store_conditionaldi;

63187

break;

63188

+ case TImode:

63189

+ fn = gen_store_conditionalti;

63190

+ break;

63191

default:

63192

gcc_unreachable ();

63193

}

63194

@@ -16949,7 +19943,7 @@

63195

{

63196

rtx boolval, retval, mem, oldval, newval, cond;

63197

rtx label1, label2, x, mask, shift;

63198

- enum machine_mode mode;

63199

+ enum machine_mode mode, orig_mode;

63200

enum memmodel mod_s, mod_f;

63201

bool is_weak;

63202

63203

@@ -16961,23 +19955,30 @@

63204

is_weak = (INTVAL (operands[5]) != 0);

63205

mod_s = (enum memmodel) INTVAL (operands[6]);

63206

mod_f = (enum memmodel) INTVAL (operands[7]);

63207

- mode = GET_MODE (mem);

63208

+ orig_mode = mode = GET_MODE (mem);

63209

63210

mask = shift = NULL_RTX;

63211

if (mode == QImode || mode == HImode)

63212

{

63213

- mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);

63214

-

63215

- /* Shift and mask OLDVAL into position with the word. */

63216

+ /* Before power8, we didn't have access to lbarx/lharx, so generate a

63217

+ lwarx and shift/mask operations. With power8, we need to do the

63218

+ comparison in SImode, but the store is still done in QI/HImode. */

63219

oldval = convert_modes (SImode, mode, oldval, 1);

63220

- oldval = expand_simple_binop (SImode, ASHIFT, oldval, shift,

63221

- NULL_RTX, 1, OPTAB_LIB_WIDEN);

63222

63223

- /* Shift and mask NEWVAL into position within the word. */

63224

- newval = convert_modes (SImode, mode, newval, 1);

63225

- newval = expand_simple_binop (SImode, ASHIFT, newval, shift,

63226

- NULL_RTX, 1, OPTAB_LIB_WIDEN);

63227

+ if (!TARGET_SYNC_HI_QI)

63228

+ {

63229

+ mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);

63230

63231

+ /* Shift and mask OLDVAL into position with the word. */

63232

+ oldval = expand_simple_binop (SImode, ASHIFT, oldval, shift,

63233

+ NULL_RTX, 1, OPTAB_LIB_WIDEN);

63234

+

63235

+ /* Shift and mask NEWVAL into position within the word. */

63236

+ newval = convert_modes (SImode, mode, newval, 1);

63237

+ newval = expand_simple_binop (SImode, ASHIFT, newval, shift,

63238

+ NULL_RTX, 1, OPTAB_LIB_WIDEN);

63239

+ }

63240

+

63241

/* Prepare to adjust the return value. */

63242

retval = gen_reg_rtx (SImode);

63243

mode = SImode;

63244

@@ -17005,7 +20006,25 @@

63245

}

63246

63247

cond = gen_reg_rtx (CCmode);

63248

- x = gen_rtx_COMPARE (CCmode, x, oldval);

63249

+ /* If we have TImode, synthesize a comparison. */

63250

+ if (mode != TImode)

63251

+ x = gen_rtx_COMPARE (CCmode, x, oldval);

63252

+ else

63253

+ {

63254

+ rtx xor1_result = gen_reg_rtx (DImode);

63255

+ rtx xor2_result = gen_reg_rtx (DImode);

63256

+ rtx or_result = gen_reg_rtx (DImode);

63257

+ rtx new_word0 = simplify_gen_subreg (DImode, x, TImode, 0);

63258

+ rtx new_word1 = simplify_gen_subreg (DImode, x, TImode, 8);

63259

+ rtx old_word0 = simplify_gen_subreg (DImode, oldval, TImode, 0);

63260

+ rtx old_word1 = simplify_gen_subreg (DImode, oldval, TImode, 8);

63261

+

63262

+ emit_insn (gen_xordi3 (xor1_result, new_word0, old_word0));

63263

+ emit_insn (gen_xordi3 (xor2_result, new_word1, old_word1));

63264

+ emit_insn (gen_iordi3 (or_result, xor1_result, xor2_result));

63265

+ x = gen_rtx_COMPARE (CCmode, or_result, const0_rtx);

63266

+ }

63267

+

63268

emit_insn (gen_rtx_SET (VOIDmode, cond, x));

63269

63270

x = gen_rtx_NE (VOIDmode, cond, const0_rtx);

63271

@@ -17015,7 +20034,7 @@

63272

if (mask)

63273

x = rs6000_mask_atomic_subword (retval, newval, mask);

63274

63275

- emit_store_conditional (mode, cond, mem, x);

63276

+ emit_store_conditional (orig_mode, cond, mem, x);

63277

63278

if (!is_weak)

63279

{

63280

@@ -17033,6 +20052,8 @@

63281

63282

if (shift)

63283

rs6000_finish_atomic_subword (operands[1], retval, shift);

63284

+ else if (mode != GET_MODE (operands[1]))

63285

+ convert_move (operands[1], retval, 1);

63286

63287

/* In all cases, CR0 contains EQ on success, and NE on failure. */

63288

x = gen_rtx_EQ (SImode, cond, const0_rtx);

63289

@@ -17056,7 +20077,7 @@

63290

mode = GET_MODE (mem);

63291

63292

mask = shift = NULL_RTX;

63293

- if (mode == QImode || mode == HImode)

63294

+ if (!TARGET_SYNC_HI_QI && (mode == QImode || mode == HImode))

63295

{

63296

mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);

63297

63298

@@ -17105,53 +20126,70 @@

63299

{

63300

enum memmodel model = (enum memmodel) INTVAL (model_rtx);

63301

enum machine_mode mode = GET_MODE (mem);

63302

+ enum machine_mode store_mode = mode;

63303

rtx label, x, cond, mask, shift;

63304

rtx before = orig_before, after = orig_after;

63305

63306

mask = shift = NULL_RTX;

63307

+ /* On power8, we want to use SImode for the operation. On previous systems,

63308

+ use the operation in a subword and shift/mask to get the proper byte or

63309

+ halfword. */

63310

if (mode == QImode || mode == HImode)

63311

{

63312

- mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);

63313

+ if (TARGET_SYNC_HI_QI)

63314

+ {

63315

+ val = convert_modes (SImode, mode, val, 1);

63316

63317

- /* Shift and mask VAL into position with the word. */

63318

- val = convert_modes (SImode, mode, val, 1);

63319

- val = expand_simple_binop (SImode, ASHIFT, val, shift,

63320

- NULL_RTX, 1, OPTAB_LIB_WIDEN);

63321

-

63322

- switch (code)

63323

+ /* Prepare to adjust the return value. */

63324

+ before = gen_reg_rtx (SImode);

63325

+ if (after)

63326

+ after = gen_reg_rtx (SImode);

63327

+ mode = SImode;

63328

+ }

63329

+ else

63330

{

63331

- case IOR:

63332

- case XOR:

63333

- /* We've already zero-extended VAL. That is sufficient to

63334

- make certain that it does not affect other bits. */

63335

- mask = NULL;

63336

- break;

63337

+ mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);

63338

63339

- case AND:

63340

- /* If we make certain that all of the other bits in VAL are

63341

- set, that will be sufficient to not affect other bits. */

63342

- x = gen_rtx_NOT (SImode, mask);

63343

- x = gen_rtx_IOR (SImode, x, val);

63344

- emit_insn (gen_rtx_SET (VOIDmode, val, x));

63345

- mask = NULL;

63346

- break;

63347

+ /* Shift and mask VAL into position with the word. */

63348

+ val = convert_modes (SImode, mode, val, 1);

63349

+ val = expand_simple_binop (SImode, ASHIFT, val, shift,

63350

+ NULL_RTX, 1, OPTAB_LIB_WIDEN);

63351

63352

- case NOT:

63353

- case PLUS:

63354

- case MINUS:

63355

- /* These will all affect bits outside the field and need

63356

- adjustment via MASK within the loop. */

63357

- break;

63358

+ switch (code)

63359

+ {

63360

+ case IOR:

63361

+ case XOR:

63362

+ /* We've already zero-extended VAL. That is sufficient to

63363

+ make certain that it does not affect other bits. */

63364

+ mask = NULL;

63365

+ break;

63366

63367

- default:

63368

- gcc_unreachable ();

63369

+ case AND:

63370

+ /* If we make certain that all of the other bits in VAL are

63371

+ set, that will be sufficient to not affect other bits. */

63372

+ x = gen_rtx_NOT (SImode, mask);

63373

+ x = gen_rtx_IOR (SImode, x, val);

63374

+ emit_insn (gen_rtx_SET (VOIDmode, val, x));

63375

+ mask = NULL;

63376

+ break;

63377

+

63378

+ case NOT:

63379

+ case PLUS:

63380

+ case MINUS:

63381

+ /* These will all affect bits outside the field and need

63382

+ adjustment via MASK within the loop. */

63383

+ break;

63384

+

63385

+ default:

63386

+ gcc_unreachable ();

63387

+ }

63388

+

63389

+ /* Prepare to adjust the return value. */

63390

+ before = gen_reg_rtx (SImode);

63391

+ if (after)

63392

+ after = gen_reg_rtx (SImode);

63393

+ store_mode = mode = SImode;

63394

}

63395

-

63396

- /* Prepare to adjust the return value. */

63397

- before = gen_reg_rtx (SImode);

63398

- if (after)

63399

- after = gen_reg_rtx (SImode);

63400

- mode = SImode;

63401

}

63402

63403

mem = rs6000_pre_atomic_barrier (mem, model);

63404

@@ -17184,9 +20222,11 @@

63405

NULL_RTX, 1, OPTAB_LIB_WIDEN);

63406

x = rs6000_mask_atomic_subword (before, x, mask);

63407

}

63408

+ else if (store_mode != mode)

63409

+ x = convert_modes (store_mode, mode, x, 1);

63410

63411

cond = gen_reg_rtx (CCmode);

63412

- emit_store_conditional (mode, cond, mem, x);

63413

+ emit_store_conditional (store_mode, cond, mem, x);

63414

63415

x = gen_rtx_NE (VOIDmode, cond, const0_rtx);

63416

emit_unlikely_jump (x, label);

63417

@@ -17195,11 +20235,22 @@

63418

63419

if (shift)

63420

{

63421

+ /* QImode/HImode on machines without lbarx/lharx where we do a lwarx and

63422

+ then do the calcuations in a SImode register. */

63423

if (orig_before)

63424

rs6000_finish_atomic_subword (orig_before, before, shift);

63425

if (orig_after)

63426

rs6000_finish_atomic_subword (orig_after, after, shift);

63427

}

63428

+ else if (store_mode != mode)

63429

+ {

63430

+ /* QImode/HImode on machines with lbarx/lharx where we do the native

63431

+ operation and then do the calcuations in a SImode register. */

63432

+ if (orig_before)

63433

+ convert_move (orig_before, before, 1);

63434

+ if (orig_after)

63435

+ convert_move (orig_after, after, 1);

63436

+ }

63437

else if (orig_after && after != orig_after)

63438

emit_move_insn (orig_after, after);

63439

}

63440

@@ -17239,6 +20290,39 @@

63441

63442

gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));

63443

63444

+ /* TDmode residing in FP registers is special, since the ISA requires that

63445

+ the lower-numbered word of a register pair is always the most significant

63446

+ word, even in little-endian mode. This does not match the usual subreg

63447

+ semantics, so we cannnot use simplify_gen_subreg in those cases. Access

63448

+ the appropriate constituent registers "by hand" in little-endian mode.

63449

+

63450

+ Note we do not need to check for destructive overlap here since TDmode

63451

+ can only reside in even/odd register pairs. */

63452

+ if (FP_REGNO_P (reg) && DECIMAL_FLOAT_MODE_P (mode) && !BYTES_BIG_ENDIAN)

63453

+ {

63454

+ rtx p_src, p_dst;

63455

+ int i;

63456

+

63457

+ for (i = 0; i < nregs; i++)

63458

+ {

63459

+ if (REG_P (src) && FP_REGNO_P (REGNO (src)))

63460

+ p_src = gen_rtx_REG (reg_mode, REGNO (src) + nregs - 1 - i);

63461

+ else

63462

+ p_src = simplify_gen_subreg (reg_mode, src, mode,

63463

+ i * reg_mode_size);

63464

+

63465

+ if (REG_P (dst) && FP_REGNO_P (REGNO (dst)))

63466

+ p_dst = gen_rtx_REG (reg_mode, REGNO (dst) + nregs - 1 - i);

63467

+ else

63468

+ p_dst = simplify_gen_subreg (reg_mode, dst, mode,

63469

+ i * reg_mode_size);

63470

+

63471

+ emit_insn (gen_rtx_SET (VOIDmode, p_dst, p_src));

63472

+ }

63473

+

63474

+ return;

63475

+ }

63476

+

63477

if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))

63478

{

63479

/* Move register range backwards, if we might have destructive

63480

@@ -17693,7 +20777,7 @@

63481

}

63482

else

63483

{

63484

- gcc_checking_assert (DEFAULT_ABI == ABI_AIX);

63485

+ gcc_checking_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);

63486

if (info->first_fp_reg_save > 61)

63487

strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;

63488

strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;

63489

@@ -17704,7 +20788,8 @@

63490

by the static chain. It would require too much fiddling and the

63491

static chain is rarely used anyway. FPRs are saved w.r.t the stack

63492

pointer on Darwin, and AIX uses r1 or r12. */

63493

- if (using_static_chain_p && DEFAULT_ABI != ABI_AIX)

63494

+ if (using_static_chain_p

63495

+ && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN))

63496

strategy |= ((DEFAULT_ABI == ABI_DARWIN ? 0 : SAVE_INLINE_FPRS)

63497

| SAVE_INLINE_GPRS

63498

| SAVE_INLINE_VRS | REST_INLINE_VRS);

63499

@@ -17837,7 +20922,35 @@

63500

The required alignment for AIX configurations is two words (i.e., 8

63501

or 16 bytes).

63502

63503

+ The ELFv2 ABI is a variant of the AIX ABI. Stack frames look like:

63504

63505

+ SP----> +---------------------------------------+

63506

+ | Back chain to caller | 0

63507

+ +---------------------------------------+

63508

+ | Save area for CR | 8

63509

+ +---------------------------------------+

63510

+ | Saved LR | 16

63511

+ +---------------------------------------+

63512

+ | Saved TOC pointer | 24

63513

+ +---------------------------------------+

63514

+ | Parameter save area (P) | 32

63515

+ +---------------------------------------+

63516

+ | Alloca space (A) | 32+P

63517

+ +---------------------------------------+

63518

+ | Local variable space (L) | 32+P+A

63519

+ +---------------------------------------+

63520

+ | Save area for AltiVec registers (W) | 32+P+A+L

63521

+ +---------------------------------------+

63522

+ | AltiVec alignment padding (Y) | 32+P+A+L+W

63523

+ +---------------------------------------+

63524

+ | Save area for GP registers (G) | 32+P+A+L+W+Y

63525

+ +---------------------------------------+

63526

+ | Save area for FP registers (F) | 32+P+A+L+W+Y+G

63527

+ +---------------------------------------+

63528

+ old SP->| back chain to caller's caller | 32+P+A+L+W+Y+G+F

63529

+ +---------------------------------------+

63530

+

63531

+

63532

V.4 stack frames look like:

63533

63534

SP----> +---------------------------------------+

63535

@@ -17897,6 +21010,7 @@

63536

rs6000_stack_t *info_ptr = &stack_info;

63537

int reg_size = TARGET_32BIT ? 4 : 8;

63538

int ehrd_size;

63539

+ int ehcr_size;

63540

int save_align;

63541

int first_gp;

63542

HOST_WIDE_INT non_fixed_size;

63543

@@ -17990,6 +21104,18 @@

63544

else

63545

ehrd_size = 0;

63546

63547

+ /* In the ELFv2 ABI, we also need to allocate space for separate

63548

+ CR field save areas if the function calls __builtin_eh_return. */

63549

+ if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)

63550

+ {

63551

+ /* This hard-codes that we have three call-saved CR fields. */

63552

+ ehcr_size = 3 * reg_size;

63553

+ /* We do *not* use the regular CR save mechanism. */

63554

+ info_ptr->cr_save_p = 0;

63555

+ }

63556

+ else

63557

+ ehcr_size = 0;

63558

+

63559

/* Determine various sizes. */

63560

info_ptr->reg_size = reg_size;

63561

info_ptr->fixed_size = RS6000_SAVE_AREA;

63562

@@ -18029,6 +21155,7 @@

63563

gcc_unreachable ();

63564

63565

case ABI_AIX:

63566

+ case ABI_ELFv2:

63567

case ABI_DARWIN:

63568

info_ptr->fp_save_offset = - info_ptr->fp_size;

63569

info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;

63570

@@ -18058,6 +21185,8 @@

63571

}

63572

else

63573

info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;

63574

+

63575

+ info_ptr->ehcr_offset = info_ptr->ehrd_offset - ehcr_size;

63576

info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */

63577

info_ptr->lr_save_offset = 2*reg_size;

63578

break;

63579

@@ -18120,6 +21249,7 @@

63580

+ info_ptr->spe_gp_size

63581

+ info_ptr->spe_padding_size

63582

+ ehrd_size

63583

+ + ehcr_size

63584

+ info_ptr->cr_size

63585

+ info_ptr->vrsave_size,

63586

save_align);

63587

@@ -18133,7 +21263,7 @@

63588

63589

/* Determine if we need to save the link register. */

63590

if (info_ptr->calls_p

63591

- || (DEFAULT_ABI == ABI_AIX

63592

+ || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)

63593

&& crtl->profile

63594

&& !TARGET_PROFILE_KERNEL)

63595

|| (DEFAULT_ABI == ABI_V4 && cfun->calls_alloca)

63596

@@ -18279,6 +21409,7 @@

63597

default: abi_string = "Unknown"; break;

63598

case ABI_NONE: abi_string = "NONE"; break;

63599

case ABI_AIX: abi_string = "AIX"; break;

63600

+ case ABI_ELFv2: abi_string = "ELFv2"; break;

63601

case ABI_DARWIN: abi_string = "Darwin"; break;

63602

case ABI_V4: abi_string = "V.4"; break;

63603

}

63604

@@ -18400,7 +21531,8 @@

63605

/* Currently we don't optimize very well between prolog and body

63606

code and for PIC code the code can be actually quite bad, so

63607

don't try to be too clever here. */

63608

- if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))

63609

+ if (count != 0

63610

+ || ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN) && flag_pic))

63611

{

63612

cfun->machine->ra_needs_full_frame = 1;

63613

63614

@@ -18459,13 +21591,13 @@

63615

return false;

63616

}

63617

63618

- /* Under the AIX ABI we can't allow calls to non-local functions,

63619

- because the callee may have a different TOC pointer to the

63620

- caller and there's no way to ensure we restore the TOC when we

63621

- return. With the secure-plt SYSV ABI we can't make non-local

63622

+ /* Under the AIX or ELFv2 ABIs we can't allow calls to non-local

63623

+ functions, because the callee may have a different TOC pointer to

63624

+ the caller and there's no way to ensure we restore the TOC when

63625

+ we return. With the secure-plt SYSV ABI we can't make non-local

63626

calls when -fpic/PIC because the plt call stubs use r30. */

63627

if (DEFAULT_ABI == ABI_DARWIN

63628

- || (DEFAULT_ABI == ABI_AIX

63629

+ || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)

63630

&& decl

63631

&& !DECL_EXTERNAL (decl)

63632

&& (*targetm.binds_local_p) (decl))

63633

@@ -18566,7 +21698,7 @@

63634

rtx dest;

63635

dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);

63636

63637

- if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic)

63638

+ if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic)

63639

{

63640

char buf[30];

63641

rtx lab, tmp1, tmp2, got;

63642

@@ -18594,7 +21726,7 @@

63643

emit_insn (gen_load_toc_v4_pic_si ());

63644

emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));

63645

}

63646

- else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)

63647

+ else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2)

63648

{

63649

char buf[30];

63650

rtx temp0 = (fromprolog

63651

@@ -18642,7 +21774,7 @@

63652

}

63653

else

63654

{

63655

- gcc_assert (DEFAULT_ABI == ABI_AIX);

63656

+ gcc_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);

63657

63658

if (TARGET_32BIT)

63659

emit_insn (gen_load_toc_aix_si (dest));

63660

@@ -19047,7 +22179,7 @@

63661

63662

static rtx

63663

rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,

63664

- rtx reg2, rtx rreg)

63665

+ rtx reg2, rtx rreg, rtx split_reg)

63666

{

63667

rtx real, temp;

63668

63669

@@ -19138,6 +22270,11 @@

63670

}

63671

}

63672

63673

+ /* If a store insn has been split into multiple insns, the

63674

+ true source register is given by split_reg. */

63675

+ if (split_reg != NULL_RTX)

63676

+ real = gen_rtx_SET (VOIDmode, SET_DEST (real), split_reg);

63677

+

63678

RTX_FRAME_RELATED_P (insn) = 1;

63679

add_reg_note (insn, REG_FRAME_RELATED_EXPR, real);

63680

63681

@@ -19245,7 +22382,7 @@

63682

reg = gen_rtx_REG (mode, regno);

63683

insn = emit_insn (gen_frame_store (reg, frame_reg, offset));

63684

return rs6000_frame_related (insn, frame_reg, frame_reg_to_sp,

63685

- NULL_RTX, NULL_RTX);

63686

+ NULL_RTX, NULL_RTX, NULL_RTX);

63687

}

63688

63689

/* Emit an offset memory reference suitable for a frame store, while

63690

@@ -19361,7 +22498,7 @@

63691

if ((sel & SAVRES_LR))

63692

suffix = "_x";

63693

}

63694

- else if (DEFAULT_ABI == ABI_AIX)

63695

+ else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)

63696

{

63697

#if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)

63698

/* No out-of-line save/restore routines for GPRs on AIX. */

63699

@@ -19502,7 +22639,7 @@

63700

static inline unsigned

63701

ptr_regno_for_savres (int sel)

63702

{

63703

- if (DEFAULT_ABI == ABI_AIX)

63704

+ if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)

63705

return (sel & SAVRES_REG) == SAVRES_FPR || (sel & SAVRES_LR) ? 1 : 12;

63706

return DEFAULT_ABI == ABI_DARWIN && (sel & SAVRES_REG) == SAVRES_FPR ? 1 : 11;

63707

}

63708

@@ -19587,6 +22724,43 @@

63709

return insn;

63710

}

63711

63712

+/* Emit code to store CR fields that need to be saved into REG. */

63713

+

63714

+static void

63715

+rs6000_emit_move_from_cr (rtx reg)

63716

+{

63717

+ /* Only the ELFv2 ABI allows storing only selected fields. */

63718

+ if (DEFAULT_ABI == ABI_ELFv2 && TARGET_MFCRF)

63719

+ {

63720

+ int i, cr_reg[8], count = 0;

63721

+

63722

+ /* Collect CR fields that must be saved. */

63723

+ for (i = 0; i < 8; i++)

63724

+ if (save_reg_p (CR0_REGNO + i))

63725

+ cr_reg[count++] = i;

63726

+

63727

+ /* If it's just a single one, use mfcrf. */

63728

+ if (count == 1)

63729

+ {

63730

+ rtvec p = rtvec_alloc (1);

63731

+ rtvec r = rtvec_alloc (2);

63732

+ RTVEC_ELT (r, 0) = gen_rtx_REG (CCmode, CR0_REGNO + cr_reg[0]);

63733

+ RTVEC_ELT (r, 1) = GEN_INT (1 << (7 - cr_reg[0]));

63734

+ RTVEC_ELT (p, 0)

63735

+ = gen_rtx_SET (VOIDmode, reg,

63736

+ gen_rtx_UNSPEC (SImode, r, UNSPEC_MOVESI_FROM_CR));

63737

+

63738

+ emit_insn (gen_rtx_PARALLEL (VOIDmode, p));

63739

+ return;

63740

+ }

63741

+

63742

+ /* ??? It might be better to handle count == 2 / 3 cases here

63743

+ as well, using logical operations to combine the values. */

63744

+ }

63745

+

63746

+ emit_insn (gen_movesi_from_cr (reg));

63747

+}

63748

+

63749

/* Determine whether the gp REG is really used. */

63750

63751

static bool

63752

@@ -19652,6 +22826,17 @@

63753

#define NOT_INUSE(R) do {} while (0)

63754

#endif

63755

63756

+ if (DEFAULT_ABI == ABI_ELFv2)

63757

+ {

63758

+ cfun->machine->r2_setup_needed = df_regs_ever_live_p (TOC_REGNUM);

63759

+

63760

+ /* With -mminimal-toc we may generate an extra use of r2 below. */

63761

+ if (!TARGET_SINGLE_PIC_BASE

63762

+ && TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)

63763

+ cfun->machine->r2_setup_needed = true;

63764

+ }

63765

+

63766

+

63767

if (flag_stack_usage_info)

63768

current_function_static_stack_size = info->total_size;

63769

63770

@@ -19766,7 +22951,7 @@

63771

63772

insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));

63773

rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,

63774

- treg, GEN_INT (-info->total_size));

63775

+ treg, GEN_INT (-info->total_size), NULL_RTX);

63776

sp_off = frame_off = info->total_size;

63777

}

63778

63779

@@ -19851,7 +23036,7 @@

63780

63781

insn = emit_move_insn (mem, reg);

63782

rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,

63783

- NULL_RTX, NULL_RTX);

63784

+ NULL_RTX, NULL_RTX, NULL_RTX);

63785

END_USE (0);

63786

}

63787

}

63788

@@ -19858,7 +23043,7 @@

63789

63790

/* If we need to save CR, put it into r12 or r11. Choose r12 except when

63791

r12 will be needed by out-of-line gpr restore. */

63792

- cr_save_regno = (DEFAULT_ABI == ABI_AIX

63793

+ cr_save_regno = ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)

63794

&& !(strategy & (SAVE_INLINE_GPRS

63795

| SAVE_NOINLINE_GPRS_SAVES_LR))

63796

? 11 : 12);

63797

@@ -19867,21 +23052,9 @@

63798

&& REGNO (frame_reg_rtx) != cr_save_regno

63799

&& !(using_static_chain_p && cr_save_regno == 11))

63800

{

63801

- rtx set;

63802

-

63803

cr_save_rtx = gen_rtx_REG (SImode, cr_save_regno);

63804

START_USE (cr_save_regno);

63805

- insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));

63806

- RTX_FRAME_RELATED_P (insn) = 1;

63807

- /* Now, there's no way that dwarf2out_frame_debug_expr is going

63808

- to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.

63809

- But that's OK. All we have to do is specify that _one_ condition

63810

- code register is saved in this stack slot. The thrower's epilogue

63811

- will then restore all the call-saved registers.

63812

- We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */

63813

- set = gen_rtx_SET (VOIDmode, cr_save_rtx,

63814

- gen_rtx_REG (SImode, CR2_REGNO));

63815

- add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);

63816

+ rs6000_emit_move_from_cr (cr_save_rtx);

63817

}

63818

63819

/* Do any required saving of fpr's. If only one or two to save, do

63820

@@ -19919,7 +23092,7 @@

63821

info->lr_save_offset,

63822

DFmode, sel);

63823

rs6000_frame_related (insn, ptr_reg, sp_off,

63824

- NULL_RTX, NULL_RTX);

63825

+ NULL_RTX, NULL_RTX, NULL_RTX);

63826

if (lr)

63827

END_USE (0);

63828

}

63829

@@ -19998,7 +23171,7 @@

63830

SAVRES_SAVE | SAVRES_GPR);

63831

63832

rs6000_frame_related (insn, spe_save_area_ptr, sp_off - save_off,

63833

- NULL_RTX, NULL_RTX);

63834

+ NULL_RTX, NULL_RTX, NULL_RTX);

63835

}

63836

63837

/* Move the static chain pointer back. */

63838

@@ -20048,7 +23221,7 @@

63839

info->lr_save_offset + ptr_off,

63840

reg_mode, sel);

63841

rs6000_frame_related (insn, ptr_reg, sp_off - ptr_off,

63842

- NULL_RTX, NULL_RTX);

63843

+ NULL_RTX, NULL_RTX, NULL_RTX);

63844

if (lr)

63845

END_USE (0);

63846

}

63847

@@ -20064,7 +23237,7 @@

63848

info->gp_save_offset + frame_off + reg_size * i);

63849

insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));

63850

rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,

63851

- NULL_RTX, NULL_RTX);

63852

+ NULL_RTX, NULL_RTX, NULL_RTX);

63853

}

63854

else if (!WORLD_SAVE_P (info))

63855

{

63856

@@ -20133,7 +23306,8 @@

63857

be updated if we arrived at this function via a plt call or

63858

toc adjusting stub. */

63859

emit_move_insn (tmp_reg_si, gen_rtx_MEM (SImode, tmp_reg));

63860

- toc_restore_insn = TARGET_32BIT ? 0x80410014 : 0xE8410028;

63861

+ toc_restore_insn = ((TARGET_32BIT ? 0x80410000 : 0xE8410000)

63862

+ + RS6000_TOC_SAVE_SLOT);

63863

hi = gen_int_mode (toc_restore_insn & ~0xffff, SImode);

63864

emit_insn (gen_xorsi3 (tmp_reg_si, tmp_reg_si, hi));

63865

compare_result = gen_rtx_REG (CCUNSmode, CR0_REGNO);

63866

@@ -20152,7 +23326,7 @@

63867

LABEL_NUSES (toc_save_done) += 1;

63868

63869

save_insn = emit_frame_save (frame_reg_rtx, reg_mode,

63870

- TOC_REGNUM, frame_off + 5 * reg_size,

63871

+ TOC_REGNUM, frame_off + RS6000_TOC_SAVE_SLOT,

63872

sp_off - frame_off);

63873

63874

emit_label (toc_save_done);

63875

@@ -20192,28 +23366,123 @@

63876

rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,

63877

GEN_INT (info->cr_save_offset + frame_off));

63878

rtx mem = gen_frame_mem (SImode, addr);

63879

- /* See the large comment above about why CR2_REGNO is used. */

63880

- rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);

63881

63882

/* If we didn't copy cr before, do so now using r0. */

63883

if (cr_save_rtx == NULL_RTX)

63884

{

63885

- rtx set;

63886

-

63887

START_USE (0);

63888

cr_save_rtx = gen_rtx_REG (SImode, 0);

63889

- insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));

63890

- RTX_FRAME_RELATED_P (insn) = 1;

63891

- set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);

63892

- add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);

63893

+ rs6000_emit_move_from_cr (cr_save_rtx);

63894

}

63895

- insn = emit_move_insn (mem, cr_save_rtx);

63896

+

63897

+ /* Saving CR requires a two-instruction sequence: one instruction

63898

+ to move the CR to a general-purpose register, and a second

63899

+ instruction that stores the GPR to memory.

63900

+

63901

+ We do not emit any DWARF CFI records for the first of these,

63902

+ because we cannot properly represent the fact that CR is saved in

63903

+ a register. One reason is that we cannot express that multiple

63904

+ CR fields are saved; another reason is that on 64-bit, the size

63905

+ of the CR register in DWARF (4 bytes) differs from the size of

63906

+ a general-purpose register.

63907

+

63908

+ This means if any intervening instruction were to clobber one of

63909

+ the call-saved CR fields, we'd have incorrect CFI. To prevent

63910

+ this from happening, we mark the store to memory as a use of

63911

+ those CR fields, which prevents any such instruction from being

63912

+ scheduled in between the two instructions. */

63913

+ rtx crsave_v[9];

63914

+ int n_crsave = 0;

63915

+ int i;

63916

+

63917

+ crsave_v[n_crsave++] = gen_rtx_SET (VOIDmode, mem, cr_save_rtx);

63918

+ for (i = 0; i < 8; i++)

63919

+ if (save_reg_p (CR0_REGNO + i))

63920

+ crsave_v[n_crsave++]

63921

+ = gen_rtx_USE (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO + i));

63922

+

63923

+ insn = emit_insn (gen_rtx_PARALLEL (VOIDmode,

63924

+ gen_rtvec_v (n_crsave, crsave_v)));

63925

END_USE (REGNO (cr_save_rtx));

63926

63927

- rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,

63928

- NULL_RTX, NULL_RTX);

63929

+ /* Now, there's no way that dwarf2out_frame_debug_expr is going to

63930

+ understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)',

63931

+ so we need to construct a frame expression manually. */

63932

+ RTX_FRAME_RELATED_P (insn) = 1;

63933

+

63934

+ /* Update address to be stack-pointer relative, like

63935

+ rs6000_frame_related would do. */

63936

+ addr = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM),

63937

+ GEN_INT (info->cr_save_offset + sp_off));

63938

+ mem = gen_frame_mem (SImode, addr);

63939

+

63940

+ if (DEFAULT_ABI == ABI_ELFv2)

63941

+ {

63942

+ /* In the ELFv2 ABI we generate separate CFI records for each

63943

+ CR field that was actually saved. They all point to the

63944

+ same 32-bit stack slot. */

63945

+ rtx crframe[8];

63946

+ int n_crframe = 0;

63947

+

63948

+ for (i = 0; i < 8; i++)

63949

+ if (save_reg_p (CR0_REGNO + i))

63950

+ {

63951

+ crframe[n_crframe]

63952

+ = gen_rtx_SET (VOIDmode, mem,

63953

+ gen_rtx_REG (SImode, CR0_REGNO + i));

63954

+

63955

+ RTX_FRAME_RELATED_P (crframe[n_crframe]) = 1;

63956

+ n_crframe++;

63957

+ }

63958

+

63959

+ add_reg_note (insn, REG_FRAME_RELATED_EXPR,

63960

+ gen_rtx_PARALLEL (VOIDmode,

63961

+ gen_rtvec_v (n_crframe, crframe)));

63962

+ }

63963

+ else

63964

+ {

63965

+ /* In other ABIs, by convention, we use a single CR regnum to

63966

+ represent the fact that all call-saved CR fields are saved.

63967

+ We use CR2_REGNO to be compatible with gcc-2.95 on Linux. */

63968

+ rtx set = gen_rtx_SET (VOIDmode, mem,

63969

+ gen_rtx_REG (SImode, CR2_REGNO));

63970

+ add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);

63971

+ }

63972

}

63973

63974

+ /* In the ELFv2 ABI we need to save all call-saved CR fields into

63975

+ *separate* slots if the routine calls __builtin_eh_return, so

63976

+ that they can be independently restored by the unwinder. */

63977

+ if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)

63978

+ {

63979

+ int i, cr_off = info->ehcr_offset;

63980

+ rtx crsave;

63981

+

63982

+ /* ??? We might get better performance by using multiple mfocrf

63983

+ instructions. */

63984

+ crsave = gen_rtx_REG (SImode, 0);

63985

+ emit_insn (gen_movesi_from_cr (crsave));

63986

+

63987

+ for (i = 0; i < 8; i++)

63988

+ if (!call_used_regs[CR0_REGNO + i])

63989

+ {

63990

+ rtvec p = rtvec_alloc (2);

63991

+ RTVEC_ELT (p, 0)

63992

+ = gen_frame_store (crsave, frame_reg_rtx, cr_off + frame_off);

63993

+ RTVEC_ELT (p, 1)

63994

+ = gen_rtx_USE (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO + i));

63995

+

63996

+ insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));

63997

+

63998

+ RTX_FRAME_RELATED_P (insn) = 1;

63999

+ add_reg_note (insn, REG_FRAME_RELATED_EXPR,

64000

+ gen_frame_store (gen_rtx_REG (SImode, CR0_REGNO + i),

64001

+ sp_reg_rtx, cr_off + sp_off));

64002

+

64003

+ cr_off += reg_size;

64004

+ }

64005

+ }

64006

+

64007

/* Update stack and set back pointer unless this is V.4,

64008

for which it was done previously. */

64009

if (!WORLD_SAVE_P (info) && info->push_p

64010

@@ -20291,7 +23560,7 @@

64011

info->altivec_save_offset + ptr_off,

64012

0, V4SImode, SAVRES_SAVE | SAVRES_VR);

64013

rs6000_frame_related (insn, scratch_reg, sp_off - ptr_off,

64014

- NULL_RTX, NULL_RTX);

64015

+ NULL_RTX, NULL_RTX, NULL_RTX);

64016

if (REGNO (frame_reg_rtx) == REGNO (scratch_reg))

64017

{

64018

/* The oddity mentioned above clobbered our frame reg. */

64019

@@ -20307,7 +23576,7 @@

64020

for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)

64021

if (info->vrsave_mask & ALTIVEC_REG_BIT (i))

64022

{

64023

- rtx areg, savereg, mem;

64024

+ rtx areg, savereg, mem, split_reg;

64025

int offset;

64026

64027

offset = (info->altivec_save_offset + frame_off

64028

@@ -20325,8 +23594,18 @@

64029

64030

insn = emit_move_insn (mem, savereg);

64031

64032

+ /* When we split a VSX store into two insns, we need to make

64033

+ sure the DWARF info knows which register we are storing.

64034

+ Pass it in to be used on the appropriate note. */

64035

+ if (!BYTES_BIG_ENDIAN

64036

+ && GET_CODE (PATTERN (insn)) == SET

64037

+ && GET_CODE (SET_SRC (PATTERN (insn))) == VEC_SELECT)

64038

+ split_reg = savereg;

64039

+ else

64040

+ split_reg = NULL_RTX;

64041

+

64042

rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,

64043

- areg, GEN_INT (offset));

64044

+ areg, GEN_INT (offset), split_reg);

64045

}

64046

}

64047

64048

@@ -20350,7 +23629,8 @@

64049

be using r12 as frame_reg_rtx and r11 as the static chain

64050

pointer for nested functions. */

64051

save_regno = 12;

64052

- if (DEFAULT_ABI == ABI_AIX && !using_static_chain_p)

64053

+ if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)

64054

+ && !using_static_chain_p)

64055

save_regno = 11;

64056

else if (REGNO (frame_reg_rtx) == 12)

64057

{

64058

@@ -20389,7 +23669,7 @@

64059

can use register 0. This allows us to use a plain 'blr' to return

64060

from the procedure more often. */

64061

int save_LR_around_toc_setup = (TARGET_ELF

64062

- && DEFAULT_ABI != ABI_AIX

64063

+ && DEFAULT_ABI == ABI_V4

64064

&& flag_pic

64065

&& ! info->lr_save_p

64066

&& EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);

64067

@@ -20451,7 +23731,7 @@

64068

if (rs6000_save_toc_in_prologue_p ())

64069

{

64070

rtx reg = gen_rtx_REG (reg_mode, TOC_REGNUM);

64071

- emit_insn (gen_frame_store (reg, sp_reg_rtx, 5 * reg_size));

64072

+ emit_insn (gen_frame_store (reg, sp_reg_rtx, RS6000_TOC_SAVE_SLOT));

64073

}

64074

}

64075

64076

@@ -20492,6 +23772,49 @@

64077

}

64078

}

64079

64080

+ /* ELFv2 ABI r2 setup code and local entry point. This must follow

64081

+ immediately after the global entry point label. */

64082

+ if (DEFAULT_ABI == ABI_ELFv2 && cfun->machine->r2_setup_needed)

64083

+ {

64084

+ const char *name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);

64085

+

64086

+ fprintf (file, "0:\taddis 2,12,.TOC.-0b@ha\n");

64087

+ fprintf (file, "\taddi 2,2,.TOC.-0b@l\n");

64088

+

64089

+ fputs ("\t.localentry\t", file);

64090

+ assemble_name (file, name);

64091

+ fputs (",.-", file);

64092

+ assemble_name (file, name);

64093

+ fputs ("\n", file);

64094

+ }

64095

+

64096

+ /* Output -mprofile-kernel code. This needs to be done here instead of

64097

+ in output_function_profile since it must go after the ELFv2 ABI

64098

+ local entry point. */

64099

+ if (TARGET_PROFILE_KERNEL)

64100

+ {

64101

+ gcc_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);

64102

+ gcc_assert (!TARGET_32BIT);

64103

+

64104

+ asm_fprintf (file, "\tmflr %s\n", reg_names[0]);

64105

+ asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);

64106

+

64107

+ /* In the ELFv2 ABI we have no compiler stack word. It must be

64108

+ the resposibility of _mcount to preserve the static chain

64109

+ register if required. */

64110

+ if (DEFAULT_ABI != ABI_ELFv2

64111

+ && cfun->static_chain_decl != NULL)

64112

+ {

64113

+ asm_fprintf (file, "\tstd %s,24(%s)\n",

64114

+ reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);

64115

+ fprintf (file, "\tbl %s\n", RS6000_MCOUNT);

64116

+ asm_fprintf (file, "\tld %s,24(%s)\n",

64117

+ reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);

64118

+ }

64119

+ else

64120

+ fprintf (file, "\tbl %s\n", RS6000_MCOUNT);

64121

+ }

64122

+

64123

rs6000_pic_labelno++;

64124

}

64125

64126

@@ -20544,6 +23867,7 @@

64127

64128

if (using_mfcr_multiple && count > 1)

64129

{

64130

+ rtx insn;

64131

rtvec p;

64132

int ndx;

64133

64134

@@ -20561,16 +23885,43 @@

64135

gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));

64136

ndx++;

64137

}

64138

- emit_insn (gen_rtx_PARALLEL (VOIDmode, p));

64139

+ insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));

64140

gcc_assert (ndx == count);

64141

+

64142

+ /* For the ELFv2 ABI we generate a CFA_RESTORE for each

64143

+ CR field separately. */

64144

+ if (!exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap)

64145

+ {

64146

+ for (i = 0; i < 8; i++)

64147

+ if (save_reg_p (CR0_REGNO + i))

64148

+ add_reg_note (insn, REG_CFA_RESTORE,

64149

+ gen_rtx_REG (SImode, CR0_REGNO + i));

64150

+

64151

+ RTX_FRAME_RELATED_P (insn) = 1;

64152

+ }

64153

}

64154

else

64155

for (i = 0; i < 8; i++)

64156

if (save_reg_p (CR0_REGNO + i))

64157

- emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode, CR0_REGNO + i),

64158

- reg));

64159

+ {

64160

+ rtx insn = emit_insn (gen_movsi_to_cr_one

64161

+ (gen_rtx_REG (CCmode, CR0_REGNO + i), reg));

64162

64163

- if (!exit_func && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap))

64164

+ /* For the ELFv2 ABI we generate a CFA_RESTORE for each

64165

+ CR field separately, attached to the insn that in fact

64166

+ restores this particular CR field. */

64167

+ if (!exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap)

64168

+ {

64169

+ add_reg_note (insn, REG_CFA_RESTORE,

64170

+ gen_rtx_REG (SImode, CR0_REGNO + i));

64171

+

64172

+ RTX_FRAME_RELATED_P (insn) = 1;

64173

+ }

64174

+ }

64175

+

64176

+ /* For other ABIs, we just generate a single CFA_RESTORE for CR2. */

64177

+ if (!exit_func && DEFAULT_ABI != ABI_ELFv2

64178

+ && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap))

64179

{

64180

rtx insn = get_last_insn ();

64181

rtx cr = gen_rtx_REG (SImode, CR2_REGNO);

64182

@@ -20611,10 +23962,22 @@

64183

static rtx

64184

add_crlr_cfa_restore (const rs6000_stack_t *info, rtx cfa_restores)

64185

{

64186

- if (info->cr_save_p)

64187

+ if (DEFAULT_ABI == ABI_ELFv2)

64188

+ {

64189

+ int i;

64190

+ for (i = 0; i < 8; i++)

64191

+ if (save_reg_p (CR0_REGNO + i))

64192

+ {

64193

+ rtx cr = gen_rtx_REG (SImode, CR0_REGNO + i);

64194

+ cfa_restores = alloc_reg_note (REG_CFA_RESTORE, cr,

64195

+ cfa_restores);

64196

+ }

64197

+ }

64198

+ else if (info->cr_save_p)

64199

cfa_restores = alloc_reg_note (REG_CFA_RESTORE,

64200

gen_rtx_REG (SImode, CR2_REGNO),

64201

cfa_restores);

64202

+

64203

if (info->lr_save_p)

64204

cfa_restores = alloc_reg_note (REG_CFA_RESTORE,

64205

gen_rtx_REG (Pmode, LR_REGNO),

64206

@@ -21112,6 +24475,35 @@

64207

|| (!restoring_GPRs_inline

64208

&& info->first_fp_reg_save == 64));

64209

64210

+ /* In the ELFv2 ABI we need to restore all call-saved CR fields from

64211

+ *separate* slots if the routine calls __builtin_eh_return, so

64212

+ that they can be independently restored by the unwinder. */

64213

+ if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)

64214

+ {

64215

+ int i, cr_off = info->ehcr_offset;

64216

+

64217

+ for (i = 0; i < 8; i++)

64218

+ if (!call_used_regs[CR0_REGNO + i])

64219

+ {

64220

+ rtx reg = gen_rtx_REG (SImode, 0);

64221

+ emit_insn (gen_frame_load (reg, frame_reg_rtx,

64222

+ cr_off + frame_off));

64223

+

64224

+ insn = emit_insn (gen_movsi_to_cr_one

64225

+ (gen_rtx_REG (CCmode, CR0_REGNO + i), reg));

64226

+

64227

+ if (!exit_func && flag_shrink_wrap)

64228

+ {

64229

+ add_reg_note (insn, REG_CFA_RESTORE,

64230

+ gen_rtx_REG (SImode, CR0_REGNO + i));

64231

+

64232

+ RTX_FRAME_RELATED_P (insn) = 1;

64233

+ }

64234

+

64235

+ cr_off += reg_size;

64236

+ }

64237

+ }

64238

+

64239

/* Get the old lr if we saved it. If we are restoring registers

64240

out-of-line, then the out-of-line routines can do this for us. */

64241

if (restore_lr && restoring_GPRs_inline)

64242

@@ -21155,7 +24547,7 @@

64243

{

64244

rtx reg = gen_rtx_REG (reg_mode, 2);

64245

emit_insn (gen_frame_load (reg, frame_reg_rtx,

64246

- frame_off + 5 * reg_size));

64247

+ frame_off + RS6000_TOC_SAVE_SLOT));

64248

}

64249

64250

for (i = 0; ; ++i)

64251

@@ -21441,6 +24833,7 @@

64252

if (! restoring_FPRs_inline)

64253

{

64254

int i;

64255

+ int reg;

64256

rtx sym;

64257

64258

if (flag_shrink_wrap)

64259

@@ -21449,10 +24842,9 @@

64260

sym = rs6000_savres_routine_sym (info,

64261

SAVRES_FPR | (lr ? SAVRES_LR : 0));

64262

RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode, sym);

64263

- RTVEC_ELT (p, 3) = gen_rtx_USE (VOIDmode,

64264

- gen_rtx_REG (Pmode,

64265

- DEFAULT_ABI == ABI_AIX

64266

- ? 1 : 11));

64267

+ reg = (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)? 1 : 11;

64268

+ RTVEC_ELT (p, 3) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, reg));

64269

+

64270

for (i = 0; i < 64 - info->first_fp_reg_save; i++)

64271

{

64272

rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);

64273

@@ -21530,7 +24922,8 @@

64274

64275

System V.4 Powerpc's (and the embedded ABI derived from it) use a

64276

different traceback table. */

64277

- if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive

64278

+ if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)

64279

+ && ! flag_inhibit_size_directive

64280

&& rs6000_traceback != traceback_none && !cfun->is_thunk)

64281

{

64282

const char *fname = NULL;

64283

@@ -21858,6 +25251,12 @@

64284

SIBLING_CALL_P (insn) = 1;

64285

emit_barrier ();

64286

64287

+ /* Ensure we have a global entry point for the thunk. ??? We could

64288

+ avoid that if the target routine doesn't need a global entry point,

64289

+ but we do not know whether this is the case at this point. */

64290

+ if (DEFAULT_ABI == ABI_ELFv2)

64291

+ cfun->machine->r2_setup_needed = true;

64292

+

64293

/* Run just enough of rest_of_compilation to get the insns emitted.

64294

There's not really enough bulk here to make other passes such as

64295

instruction scheduling worth while. Note that use_thunk calls

64296

@@ -22554,7 +25953,7 @@

64297

if (TARGET_PROFILE_KERNEL)

64298

return;

64299

64300

- if (DEFAULT_ABI == ABI_AIX)

64301

+ if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)

64302

{

64303

#ifndef NO_PROFILE_COUNTERS

64304

# define NO_PROFILE_COUNTERS 0

64305

@@ -22698,29 +26097,9 @@

64306

break;

64307

64308

case ABI_AIX:

64309

+ case ABI_ELFv2:

64310

case ABI_DARWIN:

64311

- if (!TARGET_PROFILE_KERNEL)

64312

- {

64313

- /* Don't do anything, done in output_profile_hook (). */

64314

- }

64315

- else

64316

- {

64317

- gcc_assert (!TARGET_32BIT);

64318

-

64319

- asm_fprintf (file, "\tmflr %s\n", reg_names[0]);

64320

- asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);

64321

-

64322

- if (cfun->static_chain_decl != NULL)

64323

- {

64324

- asm_fprintf (file, "\tstd %s,24(%s)\n",

64325

- reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);

64326

- fprintf (file, "\tbl %s\n", RS6000_MCOUNT);

64327

- asm_fprintf (file, "\tld %s,24(%s)\n",

64328

- reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);

64329

- }

64330

- else

64331

- fprintf (file, "\tbl %s\n", RS6000_MCOUNT);

64332

- }

64333

+ /* Don't do anything, done in output_profile_hook (). */

64334

break;

64335

}

64336

}

64337

@@ -22846,6 +26225,7 @@

64338

|| rs6000_cpu_attr == CPU_POWER4

64339

|| rs6000_cpu_attr == CPU_POWER5

64340

|| rs6000_cpu_attr == CPU_POWER7

64341

+ || rs6000_cpu_attr == CPU_POWER8

64342

|| rs6000_cpu_attr == CPU_CELL)

64343

&& recog_memoized (dep_insn)

64344

&& (INSN_CODE (dep_insn) >= 0))

64345

@@ -23128,7 +26508,8 @@

64346

if (rs6000_cpu_attr == CPU_CELL)

64347

return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS;

64348

64349

- if (rs6000_sched_groups)

64350

+ if (rs6000_sched_groups

64351

+ && (rs6000_cpu == PROCESSOR_POWER4 || rs6000_cpu == PROCESSOR_POWER5))

64352

{

64353

enum attr_type type = get_attr_type (insn);

64354

if (type == TYPE_LOAD_EXT_U

64355

@@ -23153,7 +26534,8 @@

64356

|| GET_CODE (PATTERN (insn)) == CLOBBER)

64357

return false;

64358

64359

- if (rs6000_sched_groups)

64360

+ if (rs6000_sched_groups

64361

+ && (rs6000_cpu == PROCESSOR_POWER4 || rs6000_cpu == PROCESSOR_POWER5))

64362

{

64363

enum attr_type type = get_attr_type (insn);

64364

if (type == TYPE_LOAD_U || type == TYPE_STORE_U

64365

@@ -23432,6 +26814,8 @@

64366

case CPU_POWER6:

64367

case CPU_POWER7:

64368

return 5;

64369

+ case CPU_POWER8:

64370

+ return 7;

64371

default:

64372

return 1;

64373

}

64374

@@ -24059,6 +27443,39 @@

64375

break;

64376

}

64377

break;

64378

+ case PROCESSOR_POWER8:

64379

+ type = get_attr_type (insn);

64380

+

64381

+ switch (type)

64382

+ {

64383

+ case TYPE_CR_LOGICAL:

64384

+ case TYPE_DELAYED_CR:

64385

+ case TYPE_MFCR:

64386

+ case TYPE_MFCRF:

64387

+ case TYPE_MTCR:

64388

+ case TYPE_COMPARE:

64389

+ case TYPE_DELAYED_COMPARE:

64390

+ case TYPE_VAR_DELAYED_COMPARE:

64391

+ case TYPE_IMUL_COMPARE:

64392

+ case TYPE_LMUL_COMPARE:

64393

+ case TYPE_SYNC:

64394

+ case TYPE_ISYNC:

64395

+ case TYPE_LOAD_L:

64396

+ case TYPE_STORE_C:

64397

+ case TYPE_LOAD_U:

64398

+ case TYPE_LOAD_UX:

64399

+ case TYPE_LOAD_EXT:

64400

+ case TYPE_LOAD_EXT_U:

64401

+ case TYPE_LOAD_EXT_UX:

64402

+ case TYPE_STORE_UX:

64403

+ case TYPE_VECSTORE:

64404

+ case TYPE_MFJMPR:

64405

+ case TYPE_MTJMPR:

64406

+ return true;

64407

+ default:

64408

+ break;

64409

+ }

64410

+ break;

64411

default:

64412

break;

64413

}

64414

@@ -24137,6 +27554,25 @@

64415

break;

64416

}

64417

break;

64418

+ case PROCESSOR_POWER8:

64419

+ type = get_attr_type (insn);

64420

+

64421

+ switch (type)

64422

+ {

64423

+ case TYPE_MFCR:

64424

+ case TYPE_MTCR:

64425

+ case TYPE_ISYNC:

64426

+ case TYPE_SYNC:

64427

+ case TYPE_LOAD_L:

64428

+ case TYPE_STORE_C:

64429

+ case TYPE_LOAD_EXT_U:

64430

+ case TYPE_LOAD_EXT_UX:

64431

+ case TYPE_STORE_UX:

64432

+ return true;

64433

+ default:

64434

+ break;

64435

+ }

64436

+ break;

64437

default:

64438

break;

64439

}

64440

@@ -24226,8 +27662,9 @@

64441

if (can_issue_more && !is_branch_slot_insn (next_insn))

64442

can_issue_more--;

64443

64444

- /* Power6 and Power7 have special group ending nop. */

64445

- if (rs6000_cpu_attr == CPU_POWER6 || rs6000_cpu_attr == CPU_POWER7)

64446

+ /* Do we have a special group ending nop? */

64447

+ if (rs6000_cpu_attr == CPU_POWER6 || rs6000_cpu_attr == CPU_POWER7

64448

+ || rs6000_cpu_attr == CPU_POWER8)

64449

{

64450

nop = gen_group_ending_nop ();

64451

emit_insn_before (nop, next_insn);

64452

@@ -24598,6 +28035,11 @@

64453

ret = (TARGET_32BIT) ? 12 : 24;

64454

break;

64455

64456

+ case ABI_ELFv2:

64457

+ gcc_assert (!TARGET_32BIT);

64458

+ ret = 32;

64459

+ break;

64460

+

64461

case ABI_DARWIN:

64462

case ABI_V4:

64463

ret = (TARGET_32BIT) ? 40 : 48;

64464

@@ -24653,6 +28095,7 @@

64465

break;

64466

64467

/* Under V.4/eabi/darwin, __trampoline_setup does the real work. */

64468

+ case ABI_ELFv2:

64469

case ABI_DARWIN:

64470

case ABI_V4:

64471

emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"),

64472

@@ -24743,6 +28186,9 @@

64473

unsigned_p = TYPE_UNSIGNED (type);

64474

switch (mode)

64475

{

64476

+ case TImode:

64477

+ result = (unsigned_p ? unsigned_V1TI_type_node : V1TI_type_node);

64478

+ break;

64479

case DImode:

64480

result = (unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node);

64481

break;

64482

@@ -24947,7 +28393,7 @@

64483

static void

64484

rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)

64485

{

64486

- if (DEFAULT_ABI == ABI_AIX

64487

+ if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)

64488

&& TARGET_MINIMAL_TOC

64489

&& !TARGET_RELOCATABLE)

64490

{

64491

@@ -24968,7 +28414,8 @@

64492

else

64493

fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);

64494

}

64495

- else if (DEFAULT_ABI == ABI_AIX && !TARGET_RELOCATABLE)

64496

+ else if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)

64497

+ && !TARGET_RELOCATABLE)

64498

fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);

64499

else

64500

{

64501

@@ -25518,7 +28965,7 @@

64502

{

64503

if (flag_pic)

64504

return 3;

64505

- else if (DEFAULT_ABI == ABI_AIX)

64506

+ else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)

64507

return 2;

64508

else

64509

return 0;

64510

@@ -25594,7 +29041,7 @@

64511

void

64512

rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)

64513

{

64514

- if (TARGET_64BIT)

64515

+ if (TARGET_64BIT && DEFAULT_ABI != ABI_ELFv2)

64516

{

64517

fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);

64518

ASM_OUTPUT_LABEL (file, name);

64519

@@ -25660,8 +29107,7 @@

64520

fprintf (file, "%s:\n", desc_name);

64521

fprintf (file, "\t.long %s\n", orig_name);

64522

fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);

64523

- if (DEFAULT_ABI == ABI_AIX)

64524

- fputs ("\t.long 0\n", file);

64525

+ fputs ("\t.long 0\n", file);

64526

fprintf (file, "\t.previous\n");

64527

}

64528

ASM_OUTPUT_LABEL (file, name);

64529

@@ -25690,7 +29136,7 @@

64530

}

64531

#endif

64532

#if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)

64533

- if (TARGET_32BIT)

64534

+ if (TARGET_32BIT || DEFAULT_ABI == ABI_ELFv2)

64535

file_end_indicate_exec_stack ();

64536

#endif

64537

}

64538

@@ -25829,10 +29275,23 @@

64539

name, suffix[smclass], flags & SECTION_ENTSIZE);

64540

}

64541

64542

+#define IN_NAMED_SECTION(DECL) \

64543

+ ((TREE_CODE (DECL) == FUNCTION_DECL || TREE_CODE (DECL) == VAR_DECL) \

64544

+ && DECL_SECTION_NAME (DECL) != NULL_TREE)

64545

+

64546

static section *

64547

rs6000_xcoff_select_section (tree decl, int reloc,

64548

- unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)

64549

+ unsigned HOST_WIDE_INT align)

64550

{

64551

+ /* Place variables with alignment stricter than BIGGEST_ALIGNMENT into

64552

+ named section. */

64553

+ if (align > BIGGEST_ALIGNMENT)

64554

+ {

64555

+ resolve_unique_section (decl, reloc, true);

64556

+ if (IN_NAMED_SECTION (decl))

64557

+ return get_named_section (decl, NULL, reloc);

64558

+ }

64559

+

64560

if (decl_readonly_section (decl, reloc))

64561

{

64562

if (TREE_PUBLIC (decl))

64563

@@ -25870,10 +29329,12 @@

64564

{

64565

const char *name;

64566

64567

- /* Use select_section for private and uninitialized data. */

64568

+ /* Use select_section for private data and uninitialized data with

64569

+ alignment <= BIGGEST_ALIGNMENT. */

64570

if (!TREE_PUBLIC (decl)

64571

|| DECL_COMMON (decl)

64572

- || DECL_INITIAL (decl) == NULL_TREE

64573

+ || (DECL_INITIAL (decl) == NULL_TREE

64574

+ && DECL_ALIGN (decl) <= BIGGEST_ALIGNMENT)

64575

|| DECL_INITIAL (decl) == error_mark_node

64576

|| (flag_zero_initialized_in_bss

64577

&& initializer_zerop (DECL_INITIAL (decl))))

64578

@@ -26430,7 +29891,8 @@

64579

/* For those processors that have slow LR/CTR moves, make them more

64580

expensive than memory in order to bias spills to memory .*/

64581

else if ((rs6000_cpu == PROCESSOR_POWER6

64582

- || rs6000_cpu == PROCESSOR_POWER7)

64583

+ || rs6000_cpu == PROCESSOR_POWER7

64584

+ || rs6000_cpu == PROCESSOR_POWER8)

64585

&& reg_classes_intersect_p (rclass, LINK_OR_CTR_REGS))

64586

ret = 6 * hard_regno_nregs[0][mode];

64587

64588

@@ -26440,7 +29902,7 @@

64589

}

64590

64591

/* If we have VSX, we can easily move between FPR or Altivec registers. */

64592

- else if (VECTOR_UNIT_VSX_P (mode)

64593

+ else if (VECTOR_MEM_VSX_P (mode)

64594

&& reg_classes_intersect_p (to, VSX_REGS)

64595

&& reg_classes_intersect_p (from, VSX_REGS))

64596

ret = 2 * hard_regno_nregs[32][mode];

64597

@@ -26481,7 +29943,8 @@

64598

64599

if (reg_classes_intersect_p (rclass, GENERAL_REGS))

64600

ret = 4 * hard_regno_nregs[0][mode];

64601

- else if (reg_classes_intersect_p (rclass, FLOAT_REGS))

64602

+ else if ((reg_classes_intersect_p (rclass, FLOAT_REGS)

64603

+ || reg_classes_intersect_p (rclass, VSX_REGS)))

64604

ret = 4 * hard_regno_nregs[32][mode];

64605

else if (reg_classes_intersect_p (rclass, ALTIVEC_REGS))

64606

ret = 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode];

64607

@@ -26643,54 +30106,26 @@

64608

emit_insn (gen_rtx_SET (VOIDmode, dst, r));

64609

}

64610

64611

-/* Newton-Raphson approximation of floating point divide with just 2 passes

64612

- (either single precision floating point, or newer machines with higher

64613

- accuracy estimates). Support both scalar and vector divide. Assumes no

64614

- trapping math and finite arguments. */

64615

+/* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,

64616

+ add a reg_note saying that this was a division. Support both scalar and

64617

+ vector divide. Assumes no trapping math and finite arguments. */

64618

64619

-static void

64620

-rs6000_emit_swdiv_high_precision (rtx dst, rtx n, rtx d)

64621

+void

64622

+rs6000_emit_swdiv (rtx dst, rtx n, rtx d, bool note_p)

64623

{

64624

enum machine_mode mode = GET_MODE (dst);

64625

- rtx x0, e0, e1, y1, u0, v0;

64626

- enum insn_code code = optab_handler (smul_optab, mode);

64627

- insn_gen_fn gen_mul = GEN_FCN (code);

64628

- rtx one = rs6000_load_constant_and_splat (mode, dconst1);

64629

+ rtx one, x0, e0, x1, xprev, eprev, xnext, enext, u, v;

64630

+ int i;

64631

64632

- gcc_assert (code != CODE_FOR_nothing);

64633

+ /* Low precision estimates guarantee 5 bits of accuracy. High

64634

+ precision estimates guarantee 14 bits of accuracy. SFmode

64635

+ requires 23 bits of accuracy. DFmode requires 52 bits of

64636

+ accuracy. Each pass at least doubles the accuracy, leading

64637

+ to the following. */

64638

+ int passes = (TARGET_RECIP_PRECISION) ? 1 : 3;

64639

+ if (mode == DFmode || mode == V2DFmode)

64640

+ passes++;

64641

64642

- /* x0 = 1./d estimate */

64643

- x0 = gen_reg_rtx (mode);

64644

- emit_insn (gen_rtx_SET (VOIDmode, x0,

64645

- gen_rtx_UNSPEC (mode, gen_rtvec (1, d),

64646

- UNSPEC_FRES)));

64647

-

64648

- e0 = gen_reg_rtx (mode);

64649

- rs6000_emit_nmsub (e0, d, x0, one); /* e0 = 1. - (d * x0) */

64650

-

64651

- e1 = gen_reg_rtx (mode);

64652

- rs6000_emit_madd (e1, e0, e0, e0); /* e1 = (e0 * e0) + e0 */

64653

-

64654

- y1 = gen_reg_rtx (mode);

64655

- rs6000_emit_madd (y1, e1, x0, x0); /* y1 = (e1 * x0) + x0 */

64656

-

64657

- u0 = gen_reg_rtx (mode);

64658

- emit_insn (gen_mul (u0, n, y1)); /* u0 = n * y1 */

64659

-

64660

- v0 = gen_reg_rtx (mode);

64661

- rs6000_emit_nmsub (v0, d, u0, n); /* v0 = n - (d * u0) */

64662

-

64663

- rs6000_emit_madd (dst, v0, y1, u0); /* dst = (v0 * y1) + u0 */

64664

-}

64665

-

64666

-/* Newton-Raphson approximation of floating point divide that has a low

64667

- precision estimate. Assumes no trapping math and finite arguments. */

64668

-

64669

-static void

64670

-rs6000_emit_swdiv_low_precision (rtx dst, rtx n, rtx d)

64671

-{

64672

- enum machine_mode mode = GET_MODE (dst);

64673

- rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one;

64674

enum insn_code code = optab_handler (smul_optab, mode);

64675

insn_gen_fn gen_mul = GEN_FCN (code);

64676

64677

@@ -26704,47 +30139,45 @@

64678

gen_rtx_UNSPEC (mode, gen_rtvec (1, d),

64679

UNSPEC_FRES)));

64680

64681

- e0 = gen_reg_rtx (mode);

64682

- rs6000_emit_nmsub (e0, d, x0, one); /* e0 = 1. - d * x0 */

64683

+ /* Each iteration but the last calculates x_(i+1) = x_i * (2 - d * x_i). */

64684

+ if (passes > 1) {

64685

64686

- y1 = gen_reg_rtx (mode);

64687

- rs6000_emit_madd (y1, e0, x0, x0); /* y1 = x0 + e0 * x0 */

64688

+ /* e0 = 1. - d * x0 */

64689

+ e0 = gen_reg_rtx (mode);

64690

+ rs6000_emit_nmsub (e0, d, x0, one);

64691

64692

- e1 = gen_reg_rtx (mode);

64693

- emit_insn (gen_mul (e1, e0, e0)); /* e1 = e0 * e0 */

64694

+ /* x1 = x0 + e0 * x0 */

64695

+ x1 = gen_reg_rtx (mode);

64696

+ rs6000_emit_madd (x1, e0, x0, x0);

64697

64698

- y2 = gen_reg_rtx (mode);

64699

- rs6000_emit_madd (y2, e1, y1, y1); /* y2 = y1 + e1 * y1 */

64700

+ for (i = 0, xprev = x1, eprev = e0; i < passes - 2;

64701

+ ++i, xprev = xnext, eprev = enext) {

64702

+

64703

+ /* enext = eprev * eprev */

64704

+ enext = gen_reg_rtx (mode);

64705

+ emit_insn (gen_mul (enext, eprev, eprev));

64706

64707

- e2 = gen_reg_rtx (mode);

64708

- emit_insn (gen_mul (e2, e1, e1)); /* e2 = e1 * e1 */

64709

+ /* xnext = xprev + enext * xprev */

64710

+ xnext = gen_reg_rtx (mode);

64711

+ rs6000_emit_madd (xnext, enext, xprev, xprev);

64712

+ }

64713

64714

- y3 = gen_reg_rtx (mode);

64715

- rs6000_emit_madd (y3, e2, y2, y2); /* y3 = y2 + e2 * y2 */

64716

+ } else

64717

+ xprev = x0;

64718

64719

- u0 = gen_reg_rtx (mode);

64720

- emit_insn (gen_mul (u0, n, y3)); /* u0 = n * y3 */

64721

+ /* The last iteration calculates x_(i+1) = n * x_i * (2 - d * x_i). */

64722

64723

- v0 = gen_reg_rtx (mode);

64724

- rs6000_emit_nmsub (v0, d, u0, n); /* v0 = n - d * u0 */

64725

+ /* u = n * xprev */

64726

+ u = gen_reg_rtx (mode);

64727

+ emit_insn (gen_mul (u, n, xprev));

64728

64729

- rs6000_emit_madd (dst, v0, y3, u0); /* dst = u0 + v0 * y3 */

64730

-}

64731

+ /* v = n - (d * u) */

64732

+ v = gen_reg_rtx (mode);

64733

+ rs6000_emit_nmsub (v, d, u, n);

64734

64735

-/* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,

64736

- add a reg_note saying that this was a division. Support both scalar and

64737

- vector divide. Assumes no trapping math and finite arguments. */

64738

+ /* dst = (v * xprev) + u */

64739

+ rs6000_emit_madd (dst, v, xprev, u);

64740

64741

-void

64742

-rs6000_emit_swdiv (rtx dst, rtx n, rtx d, bool note_p)

64743

-{

64744

- enum machine_mode mode = GET_MODE (dst);

64745

-

64746

- if (RS6000_RECIP_HIGH_PRECISION_P (mode))

64747

- rs6000_emit_swdiv_high_precision (dst, n, d);

64748

- else

64749

- rs6000_emit_swdiv_low_precision (dst, n, d);

64750

-

64751

if (note_p)

64752

add_reg_note (get_last_insn (), REG_EQUAL, gen_rtx_DIV (mode, n, d));

64753

}

64754

@@ -26758,7 +30191,16 @@

64755

enum machine_mode mode = GET_MODE (src);

64756

rtx x0 = gen_reg_rtx (mode);

64757

rtx y = gen_reg_rtx (mode);

64758

- int passes = (TARGET_RECIP_PRECISION) ? 2 : 3;

64759

+

64760

+ /* Low precision estimates guarantee 5 bits of accuracy. High

64761

+ precision estimates guarantee 14 bits of accuracy. SFmode

64762

+ requires 23 bits of accuracy. DFmode requires 52 bits of

64763

+ accuracy. Each pass at least doubles the accuracy, leading

64764

+ to the following. */

64765

+ int passes = (TARGET_RECIP_PRECISION) ? 1 : 3;

64766

+ if (mode == DFmode || mode == V2DFmode)

64767

+ passes++;

64768

+

64769

REAL_VALUE_TYPE dconst3_2;

64770

int i;

64771

rtx halfthree;

64772

@@ -26920,6 +30362,136 @@

64773

}

64774

}

64775

64776

+/* Expand an Altivec constant permutation for little endian mode.

64777

+ There are two issues: First, the two input operands must be

64778

+ swapped so that together they form a double-wide array in LE

64779

+ order. Second, the vperm instruction has surprising behavior

64780

+ in LE mode: it interprets the elements of the source vectors

64781

+ in BE mode ("left to right") and interprets the elements of

64782

+ the destination vector in LE mode ("right to left"). To

64783

+ correct for this, we must subtract each element of the permute

64784

+ control vector from 31.

64785

+

64786

+ For example, suppose we want to concatenate vr10 = {0, 1, 2, 3}

64787

+ with vr11 = {4, 5, 6, 7} and extract {0, 2, 4, 6} using a vperm.

64788

+ We place {0,1,2,3,8,9,10,11,16,17,18,19,24,25,26,27} in vr12 to

64789

+ serve as the permute control vector. Then, in BE mode,

64790

+

64791

+ vperm 9,10,11,12

64792

+

64793

+ places the desired result in vr9. However, in LE mode the

64794

+ vector contents will be

64795

+

64796

+ vr10 = 00000003 00000002 00000001 00000000

64797

+ vr11 = 00000007 00000006 00000005 00000004

64798

+

64799

+ The result of the vperm using the same permute control vector is

64800

+

64801

+ vr9 = 05000000 07000000 01000000 03000000

64802

+

64803

+ That is, the leftmost 4 bytes of vr10 are interpreted as the

64804

+ source for the rightmost 4 bytes of vr9, and so on.

64805

+

64806

+ If we change the permute control vector to

64807

+

64808

+ vr12 = {31,20,29,28,23,22,21,20,15,14,13,12,7,6,5,4}

64809

+

64810

+ and issue

64811

+

64812

+ vperm 9,11,10,12

64813

+

64814

+ we get the desired

64815

+

64816

+ vr9 = 00000006 00000004 00000002 00000000. */

64817

+

64818

+void

64819

+altivec_expand_vec_perm_const_le (rtx operands[4])

64820

+{

64821

+ unsigned int i;

64822

+ rtx perm[16];

64823

+ rtx constv, unspec;

64824

+ rtx target = operands[0];

64825

+ rtx op0 = operands[1];

64826

+ rtx op1 = operands[2];

64827

+ rtx sel = operands[3];

64828

+

64829

+ /* Unpack and adjust the constant selector. */

64830

+ for (i = 0; i < 16; ++i)

64831

+ {

64832

+ rtx e = XVECEXP (sel, 0, i);

64833

+ unsigned int elt = 31 - (INTVAL (e) & 31);

64834

+ perm[i] = GEN_INT (elt);

64835

+ }

64836

+

64837

+ /* Expand to a permute, swapping the inputs and using the

64838

+ adjusted selector. */

64839

+ if (!REG_P (op0))

64840

+ op0 = force_reg (V16QImode, op0);

64841

+ if (!REG_P (op1))

64842

+ op1 = force_reg (V16QImode, op1);

64843

+

64844

+ constv = gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, perm));

64845

+ constv = force_reg (V16QImode, constv);

64846

+ unspec = gen_rtx_UNSPEC (V16QImode, gen_rtvec (3, op1, op0, constv),

64847

+ UNSPEC_VPERM);

64848

+ if (!REG_P (target))

64849

+ {

64850

+ rtx tmp = gen_reg_rtx (V16QImode);

64851

+ emit_move_insn (tmp, unspec);

64852

+ unspec = tmp;

64853

+ }

64854

+

64855

+ emit_move_insn (target, unspec);

64856

+}

64857

+

64858

+/* Similarly to altivec_expand_vec_perm_const_le, we must adjust the

64859

+ permute control vector. But here it's not a constant, so we must

64860

+ generate a vector NAND or NOR to do the adjustment. */

64861

+

64862

+void

64863

+altivec_expand_vec_perm_le (rtx operands[4])

64864

+{

64865

+ rtx notx, iorx, unspec;

64866

+ rtx target = operands[0];

64867

+ rtx op0 = operands[1];

64868

+ rtx op1 = operands[2];

64869

+ rtx sel = operands[3];

64870

+ rtx tmp = target;

64871

+ rtx norreg = gen_reg_rtx (V16QImode);

64872

+ enum machine_mode mode = GET_MODE (target);

64873

+

64874

+ /* Get everything in regs so the pattern matches. */

64875

+ if (!REG_P (op0))

64876

+ op0 = force_reg (mode, op0);

64877

+ if (!REG_P (op1))

64878

+ op1 = force_reg (mode, op1);

64879

+ if (!REG_P (sel))

64880

+ sel = force_reg (V16QImode, sel);

64881

+ if (!REG_P (target))

64882

+ tmp = gen_reg_rtx (mode);

64883

+

64884

+ /* Invert the selector with a VNAND if available, else a VNOR.

64885

+ The VNAND is preferred for future fusion opportunities. */

64886

+ notx = gen_rtx_NOT (V16QImode, sel);

64887

+ iorx = (TARGET_P8_VECTOR

64888

+ ? gen_rtx_IOR (V16QImode, notx, notx)

64889

+ : gen_rtx_AND (V16QImode, notx, notx));

64890

+ emit_insn (gen_rtx_SET (VOIDmode, norreg, iorx));

64891

+

64892

+ /* Permute with operands reversed and adjusted selector. */

64893

+ unspec = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op0, norreg),

64894

+ UNSPEC_VPERM);

64895

+

64896

+ /* Copy into target, possibly by way of a register. */

64897

+ if (!REG_P (target))

64898

+ {

64899

+ emit_move_insn (tmp, unspec);

64900

+ unspec = tmp;

64901

+ }

64902

+

64903

+ emit_move_insn (target, unspec);

64904

+}

64905

+

64906

/* Expand an Altivec constant permutation. Return true if we match

64907

an efficient implementation; false to fall back to VPERM. */

64908

64909

@@ -26927,26 +30499,43 @@

64910

altivec_expand_vec_perm_const (rtx operands[4])

64911

{

64912

struct altivec_perm_insn {

64913

+ HOST_WIDE_INT mask;

64914

enum insn_code impl;

64915

unsigned char perm[16];

64916

};

64917

static const struct altivec_perm_insn patterns[] = {

64918

- { CODE_FOR_altivec_vpkuhum,

64919

+ { OPTION_MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum_direct,

64920

{ 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },

64921

- { CODE_FOR_altivec_vpkuwum,

64922

+ { OPTION_MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum_direct,

64923

{ 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },

64924

- { CODE_FOR_altivec_vmrghb,

64925

+ { OPTION_MASK_ALTIVEC,

64926

+ (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghb_direct

64927

+ : CODE_FOR_altivec_vmrglb_direct),

64928

{ 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },

64929

- { CODE_FOR_altivec_vmrghh,

64930

+ { OPTION_MASK_ALTIVEC,

64931

+ (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghh_direct

64932

+ : CODE_FOR_altivec_vmrglh_direct),

64933

{ 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },

64934

- { CODE_FOR_altivec_vmrghw,

64935

+ { OPTION_MASK_ALTIVEC,

64936

+ (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghw_direct

64937

+ : CODE_FOR_altivec_vmrglw_direct),

64938

{ 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },

64939

- { CODE_FOR_altivec_vmrglb,

64940

+ { OPTION_MASK_ALTIVEC,

64941

+ (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglb_direct

64942

+ : CODE_FOR_altivec_vmrghb_direct),

64943

{ 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },

64944

- { CODE_FOR_altivec_vmrglh,

64945

+ { OPTION_MASK_ALTIVEC,

64946

+ (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglh_direct

64947

+ : CODE_FOR_altivec_vmrghh_direct),

64948

{ 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },

64949

- { CODE_FOR_altivec_vmrglw,

64950

- { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } }

64951

+ { OPTION_MASK_ALTIVEC,

64952

+ (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglw_direct

64953

+ : CODE_FOR_altivec_vmrghw_direct),

64954

+ { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },

64955

+ { OPTION_MASK_P8_VECTOR, CODE_FOR_p8_vmrgew,

64956

+ { 0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 24, 25, 26, 27 } },

64957

+ { OPTION_MASK_P8_VECTOR, CODE_FOR_p8_vmrgow,

64958

+ { 4, 5, 6, 7, 20, 21, 22, 23, 12, 13, 14, 15, 28, 29, 30, 31 } }

64959

};

64960

64961

unsigned int i, j, elt, which;

64962

@@ -27003,7 +30592,9 @@

64963

break;

64964

if (i == 16)

64965

{

64966

- emit_insn (gen_altivec_vspltb (target, op0, GEN_INT (elt)));

64967

+ if (!BYTES_BIG_ENDIAN)

64968

+ elt = 15 - elt;

64969

+ emit_insn (gen_altivec_vspltb_direct (target, op0, GEN_INT (elt)));

64970

return true;

64971

}

64972

64973

@@ -27014,9 +30605,10 @@

64974

break;

64975

if (i == 16)

64976

{

64977

+ int field = BYTES_BIG_ENDIAN ? elt / 2 : 7 - elt / 2;

64978

x = gen_reg_rtx (V8HImode);

64979

- emit_insn (gen_altivec_vsplth (x, gen_lowpart (V8HImode, op0),

64980

- GEN_INT (elt / 2)));

64981

+ emit_insn (gen_altivec_vsplth_direct (x, gen_lowpart (V8HImode, op0),

64982

+ GEN_INT (field)));

64983

emit_move_insn (target, gen_lowpart (V16QImode, x));

64984

return true;

64985

}

64986

@@ -27032,9 +30624,10 @@

64987

break;

64988

if (i == 16)

64989

{

64990

+ int field = BYTES_BIG_ENDIAN ? elt / 4 : 3 - elt / 4;

64991

x = gen_reg_rtx (V4SImode);

64992

- emit_insn (gen_altivec_vspltw (x, gen_lowpart (V4SImode, op0),

64993

- GEN_INT (elt / 4)));

64994

+ emit_insn (gen_altivec_vspltw_direct (x, gen_lowpart (V4SImode, op0),

64995

+ GEN_INT (field)));

64996

emit_move_insn (target, gen_lowpart (V16QImode, x));

64997

return true;

64998

}

64999

@@ -27046,6 +30639,9 @@

65000

{

65001

bool swapped;

65002

65003

+ if ((patterns[j].mask & rs6000_isa_flags) == 0)

65004

+ continue;

65005

+

65006

elt = patterns[j].perm[0];

65007

if (perm[0] == elt)

65008

swapped = false;

65009

@@ -27069,7 +30665,30 @@

65010

enum machine_mode omode = insn_data[icode].operand[0].mode;

65011

enum machine_mode imode = insn_data[icode].operand[1].mode;

65012

65013

- if (swapped)

65014

+ /* For little-endian, don't use vpkuwum and vpkuhum if the

65015

+ underlying vector type is not V4SI and V8HI, respectively.

65016

+ For example, using vpkuwum with a V8HI picks up the even

65017

+ halfwords (BE numbering) when the even halfwords (LE

65018

+ numbering) are what we need. */

65019

+ if (!BYTES_BIG_ENDIAN

65020

+ && icode == CODE_FOR_altivec_vpkuwum_direct

65021

+ && ((GET_CODE (op0) == REG

65022

+ && GET_MODE (op0) != V4SImode)

65023

+ || (GET_CODE (op0) == SUBREG

65024

+ && GET_MODE (XEXP (op0, 0)) != V4SImode)))

65025

+ continue;

65026

+ if (!BYTES_BIG_ENDIAN

65027

+ && icode == CODE_FOR_altivec_vpkuhum_direct

65028

+ && ((GET_CODE (op0) == REG

65029

+ && GET_MODE (op0) != V8HImode)

65030

+ || (GET_CODE (op0) == SUBREG

65031

+ && GET_MODE (XEXP (op0, 0)) != V8HImode)))

65032

+ continue;

65033

+

65034

+ /* For little-endian, the two input operands must be swapped

65035

+ (or swapped back) to ensure proper right-to-left numbering

65036

+ from 0 to 2N-1. */

65037

+ if (swapped ^ !BYTES_BIG_ENDIAN)

65038

x = op0, op0 = op1, op1 = x;

65039

if (imode != V16QImode)

65040

{

65041

@@ -27087,6 +30706,12 @@

65042

}

65043

}

65044

65045

+ if (!BYTES_BIG_ENDIAN)

65046

+ {

65047

+ altivec_expand_vec_perm_const_le (operands);

65048

+ return true;

65049

+ }

65050

+

65051

return false;

65052

}

65053

65054

@@ -27135,7 +30760,6 @@

65055

vmode = GET_MODE (target);

65056

gcc_assert (GET_MODE_NUNITS (vmode) == 2);

65057

dmode = mode_for_vector (GET_MODE_INNER (vmode), 4);

65058

-

65059

x = gen_rtx_VEC_CONCAT (dmode, op0, op1);

65060

v = gen_rtvec (2, GEN_INT (perm0), GEN_INT (perm1));

65061

x = gen_rtx_VEC_SELECT (vmode, x, gen_rtx_PARALLEL (VOIDmode, v));

65062

@@ -27231,7 +30855,7 @@

65063

unsigned i, high, nelt = GET_MODE_NUNITS (vmode);

65064

rtx perm[16];

65065

65066

- high = (highp == BYTES_BIG_ENDIAN ? 0 : nelt / 2);

65067

+ high = (highp ? 0 : nelt / 2);

65068

for (i = 0; i < nelt / 2; i++)

65069

{

65070

perm[i * 2] = GEN_INT (i + high);

65071

@@ -27286,6 +30910,8 @@

65072

{

65073

enum machine_mode mode;

65074

unsigned int regno;

65075

+ enum machine_mode elt_mode;

65076

+ int n_elts;

65077

65078

/* Special handling for structs in darwin64. */

65079

if (TARGET_MACHO

65080

@@ -27305,6 +30931,36 @@

65081

/* Otherwise fall through to standard ABI rules. */

65082

}

65083

65084

+ /* The ELFv2 ABI returns homogeneous VFP aggregates in registers. */

65085

+ if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (valtype), valtype,

65086

+ &elt_mode, &n_elts))

65087

+ {

65088

+ int first_reg, n_regs, i;

65089

+ rtx par;

65090

+

65091

+ if (SCALAR_FLOAT_MODE_P (elt_mode))

65092

+ {

65093

+ /* _Decimal128 must use even/odd register pairs. */

65094

+ first_reg = (elt_mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;

65095

+ n_regs = (GET_MODE_SIZE (elt_mode) + 7) >> 3;

65096

+ }

65097

+ else

65098

+ {

65099

+ first_reg = ALTIVEC_ARG_RETURN;

65100

+ n_regs = 1;

65101

+ }

65102

+

65103

+ par = gen_rtx_PARALLEL (TYPE_MODE (valtype), rtvec_alloc (n_elts));

65104

+ for (i = 0; i < n_elts; i++)

65105

+ {

65106

+ rtx r = gen_rtx_REG (elt_mode, first_reg + i * n_regs);

65107

+ rtx off = GEN_INT (i * GET_MODE_SIZE (elt_mode));

65108

+ XVECEXP (par, 0, i) = gen_rtx_EXPR_LIST (VOIDmode, r, off);

65109

+ }

65110

+

65111

+ return par;

65112

+ }

65113

+

65114

if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)

65115

{

65116

/* Long long return value need be split in -mpowerpc64, 32bit ABI. */

65117

@@ -27417,6 +31073,13 @@

65118

}

65119

65120

65121

+/* Return true if we use LRA instead of reload pass. */

65122

+static bool

65123

+rs6000_lra_p (void)

65124

+{

65125

+ return rs6000_lra_flag;

65126

+}

65127

+

65128

/* Given FROM and TO register numbers, say whether this elimination is allowed.

65129

Frame pointer elimination is automatically handled.

65130

65131

@@ -27679,22 +31342,33 @@

65132

{

65133

{ "altivec", OPTION_MASK_ALTIVEC, false, true },

65134

{ "cmpb", OPTION_MASK_CMPB, false, true },

65135

+ { "crypto", OPTION_MASK_CRYPTO, false, true },

65136

+ { "direct-move", OPTION_MASK_DIRECT_MOVE, false, true },

65137

{ "dlmzb", OPTION_MASK_DLMZB, false, true },

65138

{ "fprnd", OPTION_MASK_FPRND, false, true },

65139

{ "hard-dfp", OPTION_MASK_DFP, false, true },

65140

+ { "htm", OPTION_MASK_HTM, false, true },

65141

{ "isel", OPTION_MASK_ISEL, false, true },

65142

{ "mfcrf", OPTION_MASK_MFCRF, false, true },

65143

{ "mfpgpr", OPTION_MASK_MFPGPR, false, true },

65144

{ "mulhw", OPTION_MASK_MULHW, false, true },

65145

{ "multiple", OPTION_MASK_MULTIPLE, false, true },

65146

- { "update", OPTION_MASK_NO_UPDATE, true , true },

65147

{ "popcntb", OPTION_MASK_POPCNTB, false, true },

65148

{ "popcntd", OPTION_MASK_POPCNTD, false, true },

65149

+ { "power8-fusion", OPTION_MASK_P8_FUSION, false, true },

65150

+ { "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN, false, true },

65151

+ { "power8-vector", OPTION_MASK_P8_VECTOR, false, true },

65152

{ "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT, false, true },

65153

{ "powerpc-gpopt", OPTION_MASK_PPC_GPOPT, false, true },

65154

+ { "quad-memory", OPTION_MASK_QUAD_MEMORY, false, true },

65155

+ { "quad-memory-atomic", OPTION_MASK_QUAD_MEMORY_ATOMIC, false, true },

65156

{ "recip-precision", OPTION_MASK_RECIP_PRECISION, false, true },

65157

{ "string", OPTION_MASK_STRING, false, true },

65158

+ { "update", OPTION_MASK_NO_UPDATE, true , true },

65159

+ { "upper-regs-df", OPTION_MASK_UPPER_REGS_DF, false, false },

65160

+ { "upper-regs-sf", OPTION_MASK_UPPER_REGS_SF, false, false },

65161

{ "vsx", OPTION_MASK_VSX, false, true },

65162

+ { "vsx-timode", OPTION_MASK_VSX_TIMODE, false, true },

65163

#ifdef OPTION_MASK_64BIT

65164

#if TARGET_AIX_OS

65165

{ "aix64", OPTION_MASK_64BIT, false, false },

65166

@@ -27734,6 +31408,11 @@

65167

{ "frsqrtes", RS6000_BTM_FRSQRTES, false, false },

65168

{ "popcntd", RS6000_BTM_POPCNTD, false, false },

65169

{ "cell", RS6000_BTM_CELL, false, false },

65170

+ { "power8-vector", RS6000_BTM_P8_VECTOR, false, false },

65171

+ { "crypto", RS6000_BTM_CRYPTO, false, false },

65172

+ { "htm", RS6000_BTM_HTM, false, false },

65173

+ { "hard-dfp", RS6000_BTM_DFP, false, false },

65174

+ { "hard-float", RS6000_BTM_HARD_FLOAT, false, false },

65175

};

65176

65177

/* Option variables that we want to support inside attribute((target)) and

65178

@@ -28250,7 +31929,6 @@

65179

size_t cur_column;

65180

size_t max_column = 76;

65181

const char *comma = "";

65182

- const char *nl = "\n";

65183

65184

if (indent)

65185

start_column += fprintf (file, "%*s", indent, "");

65186

@@ -28281,7 +31959,6 @@

65187

fprintf (stderr, ", \\\n%*s", (int)start_column, "");

65188

cur_column = start_column + len;

65189

comma = "";

65190

- nl = "\n\n";

65191

}

65192

65193

fprintf (file, "%s%s%s%s", comma, prefix, no_str,

65194

@@ -28291,7 +31968,7 @@

65195

}

65196

}

65197

65198

- fputs (nl, file);

65199

+ fputs ("\n", file);

65200

}

65201

65202

/* Helper function to print the current isa options on a line. */

65203

@@ -28467,118 +32144,149 @@

65204

}

65205

65206

65207

-/* A function pointer under AIX is a pointer to a data area whose first word

65208

- contains the actual address of the function, whose second word contains a

65209

- pointer to its TOC, and whose third word contains a value to place in the

65210

- static chain register (r11). Note that if we load the static chain, our

65211

- "trampoline" need not have any executable code. */

65212

65213

+/* Expand code to perform a call under the AIX or ELFv2 ABI. */

65214

+

65215

void

65216

-rs6000_call_indirect_aix (rtx value, rtx func_desc, rtx flag)

65217

+rs6000_call_aix (rtx value, rtx func_desc, rtx flag, rtx cookie)

65218

{

65219

+ rtx toc_reg = gen_rtx_REG (Pmode, TOC_REGNUM);

65220

+ rtx toc_load = NULL_RTX;

65221

+ rtx toc_restore = NULL_RTX;

65222

rtx func_addr;

65223

- rtx toc_reg;

65224

- rtx sc_reg;

65225

- rtx stack_ptr;

65226

- rtx stack_toc_offset;

65227

- rtx stack_toc_mem;

65228

- rtx func_toc_offset;

65229

- rtx func_toc_mem;

65230

- rtx func_sc_offset;

65231

- rtx func_sc_mem;

65232

+ rtx abi_reg = NULL_RTX;

65233

+ rtx call[4];

65234

+ int n_call;

65235

rtx insn;

65236

- rtx (*call_func) (rtx, rtx, rtx, rtx);

65237

- rtx (*call_value_func) (rtx, rtx, rtx, rtx, rtx);

65238

65239

- stack_ptr = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);

65240

- toc_reg = gen_rtx_REG (Pmode, TOC_REGNUM);

65241

+ /* Handle longcall attributes. */

65242

+ if (INTVAL (cookie) & CALL_LONG)

65243

+ func_desc = rs6000_longcall_ref (func_desc);

65244

65245

- /* Load up address of the actual function. */

65246

- func_desc = force_reg (Pmode, func_desc);

65247

- func_addr = gen_reg_rtx (Pmode);

65248

- emit_move_insn (func_addr, gen_rtx_MEM (Pmode, func_desc));

65249

-

65250

- if (TARGET_32BIT)

65251

+ /* Handle indirect calls. */

65252

+ if (GET_CODE (func_desc) != SYMBOL_REF

65253

+ || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (func_desc)))

65254

{

65255

+ /* Save the TOC into its reserved slot before the call,

65256

+ and prepare to restore it after the call. */

65257

+ rtx stack_ptr = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);

65258

+ rtx stack_toc_offset = GEN_INT (RS6000_TOC_SAVE_SLOT);

65259

+ rtx stack_toc_mem = gen_frame_mem (Pmode,

65260

+ gen_rtx_PLUS (Pmode, stack_ptr,

65261

+ stack_toc_offset));

65262

+ toc_restore = gen_rtx_SET (VOIDmode, toc_reg, stack_toc_mem);

65263

65264

- stack_toc_offset = GEN_INT (TOC_SAVE_OFFSET_32BIT);

65265

- func_toc_offset = GEN_INT (AIX_FUNC_DESC_TOC_32BIT);

65266

- func_sc_offset = GEN_INT (AIX_FUNC_DESC_SC_32BIT);

65267

- if (TARGET_POINTERS_TO_NESTED_FUNCTIONS)

65268

- {

65269

- call_func = gen_call_indirect_aix32bit;

65270

- call_value_func = gen_call_value_indirect_aix32bit;

65271

- }

65272

+ /* Can we optimize saving the TOC in the prologue or

65273

+ do we need to do it at every call? */

65274

+ if (TARGET_SAVE_TOC_INDIRECT && !cfun->calls_alloca)

65275

+ cfun->machine->save_toc_in_prologue = true;

65276

else

65277

{

65278

- call_func = gen_call_indirect_aix32bit_nor11;

65279

- call_value_func = gen_call_value_indirect_aix32bit_nor11;

65280

+ MEM_VOLATILE_P (stack_toc_mem) = 1;

65281

+ emit_move_insn (stack_toc_mem, toc_reg);

65282

}

65283

- }

65284

- else

65285

- {

65286

- stack_toc_offset = GEN_INT (TOC_SAVE_OFFSET_64BIT);

65287

- func_toc_offset = GEN_INT (AIX_FUNC_DESC_TOC_64BIT);

65288

- func_sc_offset = GEN_INT (AIX_FUNC_DESC_SC_64BIT);

65289

- if (TARGET_POINTERS_TO_NESTED_FUNCTIONS)

65290

+

65291

+ if (DEFAULT_ABI == ABI_ELFv2)

65292

{

65293

- call_func = gen_call_indirect_aix64bit;

65294

- call_value_func = gen_call_value_indirect_aix64bit;

65295

+ /* A function pointer in the ELFv2 ABI is just a plain address, but

65296

+ the ABI requires it to be loaded into r12 before the call. */

65297

+ func_addr = gen_rtx_REG (Pmode, 12);

65298

+ emit_move_insn (func_addr, func_desc);

65299

+ abi_reg = func_addr;

65300

}

65301

else

65302

{

65303

- call_func = gen_call_indirect_aix64bit_nor11;

65304

- call_value_func = gen_call_value_indirect_aix64bit_nor11;

65305

- }

65306

- }

65307

+ /* A function pointer under AIX is a pointer to a data area whose

65308

+ first word contains the actual address of the function, whose

65309

+ second word contains a pointer to its TOC, and whose third word

65310

+ contains a value to place in the static chain register (r11).

65311

+ Note that if we load the static chain, our "trampoline" need

65312

+ not have any executable code. */

65313

65314

- /* Reserved spot to store the TOC. */

65315

- stack_toc_mem = gen_frame_mem (Pmode,

65316

- gen_rtx_PLUS (Pmode,

65317

- stack_ptr,

65318

- stack_toc_offset));

65319

+ /* Load up address of the actual function. */

65320

+ func_desc = force_reg (Pmode, func_desc);

65321

+ func_addr = gen_reg_rtx (Pmode);

65322

+ emit_move_insn (func_addr, gen_rtx_MEM (Pmode, func_desc));

65323

65324

- gcc_assert (cfun);

65325

- gcc_assert (cfun->machine);

65326

+ /* Prepare to load the TOC of the called function. Note that the

65327

+ TOC load must happen immediately before the actual call so

65328

+ that unwinding the TOC registers works correctly. See the

65329

+ comment in frob_update_context. */

65330

+ rtx func_toc_offset = GEN_INT (GET_MODE_SIZE (Pmode));

65331

+ rtx func_toc_mem = gen_rtx_MEM (Pmode,

65332

+ gen_rtx_PLUS (Pmode, func_desc,

65333

+ func_toc_offset));

65334

+ toc_load = gen_rtx_USE (VOIDmode, func_toc_mem);

65335

65336

- /* Can we optimize saving the TOC in the prologue or do we need to do it at

65337

- every call? */

65338

- if (TARGET_SAVE_TOC_INDIRECT && !cfun->calls_alloca)

65339

- cfun->machine->save_toc_in_prologue = true;

65340

-

65341

+ /* If we have a static chain, load it up. */

65342

+ if (TARGET_POINTERS_TO_NESTED_FUNCTIONS)

65343

+ {

65344

+ rtx sc_reg = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM);

65345

+ rtx func_sc_offset = GEN_INT (2 * GET_MODE_SIZE (Pmode));

65346

+ rtx func_sc_mem = gen_rtx_MEM (Pmode,

65347

+ gen_rtx_PLUS (Pmode, func_desc,

65348

+ func_sc_offset));

65349

+ emit_move_insn (sc_reg, func_sc_mem);

65350

+ abi_reg = sc_reg;

65351

+ }

65352

+ }

65353

+ }

65354

else

65355

{

65356

- MEM_VOLATILE_P (stack_toc_mem) = 1;

65357

- emit_move_insn (stack_toc_mem, toc_reg);

65358

+ /* Direct calls use the TOC: for local calls, the callee will

65359

+ assume the TOC register is set; for non-local calls, the

65360

+ PLT stub needs the TOC register. */

65361

+ abi_reg = toc_reg;

65362

+ func_addr = func_desc;

65363

}

65364

65365

- /* Calculate the address to load the TOC of the called function. We don't

65366

- actually load this until the split after reload. */

65367

- func_toc_mem = gen_rtx_MEM (Pmode,

65368

- gen_rtx_PLUS (Pmode,

65369

- func_desc,

65370

- func_toc_offset));

65371

+ /* Create the call. */

65372

+ call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_addr), flag);

65373

+ if (value != NULL_RTX)

65374

+ call[0] = gen_rtx_SET (VOIDmode, value, call[0]);

65375

+ n_call = 1;

65376

65377

- /* If we have a static chain, load it up. */

65378

- if (TARGET_POINTERS_TO_NESTED_FUNCTIONS)

65379

- {

65380

- func_sc_mem = gen_rtx_MEM (Pmode,

65381

- gen_rtx_PLUS (Pmode,

65382

- func_desc,

65383

- func_sc_offset));

65384

+ if (toc_load)

65385

+ call[n_call++] = toc_load;

65386

+ if (toc_restore)

65387

+ call[n_call++] = toc_restore;

65388

65389

- sc_reg = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM);

65390

- emit_move_insn (sc_reg, func_sc_mem);

65391

- }

65392

+ call[n_call++] = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, LR_REGNO));

65393

65394

+ insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (n_call, call));

65395

+ insn = emit_call_insn (insn);

65396

+

65397

+ /* Mention all registers defined by the ABI to hold information

65398

+ as uses in CALL_INSN_FUNCTION_USAGE. */

65399

+ if (abi_reg)

65400

+ use_reg (&CALL_INSN_FUNCTION_USAGE (insn), abi_reg);

65401

+}

65402

+

65403

+/* Expand code to perform a sibling call under the AIX or ELFv2 ABI. */

65404

+

65405

+void

65406

+rs6000_sibcall_aix (rtx value, rtx func_desc, rtx flag, rtx cookie)

65407

+{

65408

+ rtx call[2];

65409

+ rtx insn;

65410

+

65411

+ gcc_assert (INTVAL (cookie) == 0);

65412

+

65413

/* Create the call. */

65414

- if (value)

65415

- insn = call_value_func (value, func_addr, flag, func_toc_mem,

65416

- stack_toc_mem);

65417

- else

65418

- insn = call_func (func_addr, flag, func_toc_mem, stack_toc_mem);

65419

+ call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_desc), flag);

65420

+ if (value != NULL_RTX)

65421

+ call[0] = gen_rtx_SET (VOIDmode, value, call[0]);

65422

65423

- emit_call_insn (insn);

65424

+ call[1] = simple_return_rtx;

65425

+

65426

+ insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (2, call));

65427

+ insn = emit_call_insn (insn);

65428

+

65429

+ /* Note use of the TOC register. */

65430

+ use_reg (&CALL_INSN_FUNCTION_USAGE (insn), gen_rtx_REG (Pmode, TOC_REGNUM));

65431

+ /* We need to also mark a use of the link register since the function we

65432

+ sibling-call to will use it to return to our caller. */

65433

+ use_reg (&CALL_INSN_FUNCTION_USAGE (insn), gen_rtx_REG (Pmode, LR_REGNO));

65434

}

65435

65436

/* Return whether we need to always update the saved TOC pointer when we update

65437

@@ -28679,6 +32387,661 @@

65438

add_to_hard_reg_set (&set->set, Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);

65439

}

65440

65441

+

65442

+/* Helper function for rs6000_split_logical to emit a logical instruction after

65443

+ spliting the operation to single GPR registers.

65444

+

65445

+ DEST is the destination register.

65446

+ OP1 and OP2 are the input source registers.

65447

+ CODE is the base operation (AND, IOR, XOR, NOT).

65448

+ MODE is the machine mode.

65449

+ If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.

65450

+ If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.

65451

+ If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.

65452

+ CLOBBER_REG is either NULL or a scratch register of type CC to allow

65453

+ formation of the AND instructions. */

65454

+

65455

+static void

65456

+rs6000_split_logical_inner (rtx dest,

65457

+ rtx op1,

65458

+ rtx op2,

65459

+ enum rtx_code code,

65460

+ enum machine_mode mode,

65461

+ bool complement_final_p,

65462

+ bool complement_op1_p,

65463

+ bool complement_op2_p,

65464

+ rtx clobber_reg)

65465

+{

65466

+ rtx bool_rtx;

65467

+ rtx set_rtx;

65468

+

65469

+ /* Optimize AND of 0/0xffffffff and IOR/XOR of 0. */

65470

+ if (op2 && GET_CODE (op2) == CONST_INT

65471

+ && (mode == SImode || (mode == DImode && TARGET_POWERPC64))

65472

+ && !complement_final_p && !complement_op1_p && !complement_op2_p)

65473

+ {

65474

+ HOST_WIDE_INT mask = GET_MODE_MASK (mode);

65475

+ HOST_WIDE_INT value = INTVAL (op2) & mask;

65476

+

65477

+ /* Optimize AND of 0 to just set 0. Optimize AND of -1 to be a move. */

65478

+ if (code == AND)

65479

+ {

65480

+ if (value == 0)

65481

+ {

65482

+ emit_insn (gen_rtx_SET (VOIDmode, dest, const0_rtx));

65483

+ return;

65484

+ }

65485

+

65486

+ else if (value == mask)

65487

+ {

65488

+ if (!rtx_equal_p (dest, op1))

65489

+ emit_insn (gen_rtx_SET (VOIDmode, dest, op1));

65490

+ return;

65491

+ }

65492

+ }

65493

+

65494

+ /* Optimize IOR/XOR of 0 to be a simple move. Split large operations

65495

+ into separate ORI/ORIS or XORI/XORIS instrucitons. */

65496

+ else if (code == IOR || code == XOR)

65497

+ {

65498

+ if (value == 0)

65499

+ {

65500

+ if (!rtx_equal_p (dest, op1))

65501

+ emit_insn (gen_rtx_SET (VOIDmode, dest, op1));

65502

+ return;

65503

+ }

65504

+ }

65505

+ }

65506

+

65507

+ if (complement_op1_p)

65508

+ op1 = gen_rtx_NOT (mode, op1);

65509

+

65510

+ if (complement_op2_p)

65511

+ op2 = gen_rtx_NOT (mode, op2);

65512

+

65513

+ bool_rtx = ((code == NOT)

65514

+ ? gen_rtx_NOT (mode, op1)

65515

+ : gen_rtx_fmt_ee (code, mode, op1, op2));

65516

+

65517

+ if (complement_final_p)

65518

+ bool_rtx = gen_rtx_NOT (mode, bool_rtx);

65519

+

65520

+ set_rtx = gen_rtx_SET (VOIDmode, dest, bool_rtx);

65521

+

65522

+ /* Is this AND with an explicit clobber? */

65523

+ if (clobber_reg)

65524

+ {

65525

+ rtx clobber = gen_rtx_CLOBBER (VOIDmode, clobber_reg);

65526

+ set_rtx = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set_rtx, clobber));

65527

+ }

65528

+

65529

+ emit_insn (set_rtx);

65530

+ return;

65531

+}

65532

+

65533

+/* Split a DImode AND/IOR/XOR with a constant on a 32-bit system. These

65534

+ operations are split immediately during RTL generation to allow for more

65535

+ optimizations of the AND/IOR/XOR.

65536

+

65537

+ OPERANDS is an array containing the destination and two input operands.

65538

+ CODE is the base operation (AND, IOR, XOR, NOT).

65539

+ MODE is the machine mode.

65540

+ If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.

65541

+ If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.

65542

+ If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.

65543

+ CLOBBER_REG is either NULL or a scratch register of type CC to allow

65544

+ formation of the AND instructions. */

65545

+

65546

+static void

65547

+rs6000_split_logical_di (rtx operands[3],

65548

+ enum rtx_code code,

65549

+ bool complement_final_p,

65550

+ bool complement_op1_p,

65551

+ bool complement_op2_p,

65552

+ rtx clobber_reg)

65553

+{

65554

+ const HOST_WIDE_INT lower_32bits = HOST_WIDE_INT_C(0xffffffff);

65555

+ const HOST_WIDE_INT upper_32bits = ~ lower_32bits;

65556

+ const HOST_WIDE_INT sign_bit = HOST_WIDE_INT_C(0x80000000);

65557

+ enum hi_lo { hi = 0, lo = 1 };

65558

+ rtx op0_hi_lo[2], op1_hi_lo[2], op2_hi_lo[2];

65559

+ size_t i;

65560

+

65561

+ op0_hi_lo[hi] = gen_highpart (SImode, operands[0]);

65562

+ op1_hi_lo[hi] = gen_highpart (SImode, operands[1]);

65563

+ op0_hi_lo[lo] = gen_lowpart (SImode, operands[0]);

65564

+ op1_hi_lo[lo] = gen_lowpart (SImode, operands[1]);

65565

+

65566

+ if (code == NOT)

65567

+ op2_hi_lo[hi] = op2_hi_lo[lo] = NULL_RTX;

65568

+ else

65569

+ {

65570

+ if (GET_CODE (operands[2]) != CONST_INT)

65571

+ {

65572

+ op2_hi_lo[hi] = gen_highpart_mode (SImode, DImode, operands[2]);

65573

+ op2_hi_lo[lo] = gen_lowpart (SImode, operands[2]);

65574

+ }

65575

+ else

65576

+ {

65577

+ HOST_WIDE_INT value = INTVAL (operands[2]);

65578

+ HOST_WIDE_INT value_hi_lo[2];

65579

+

65580

+ gcc_assert (!complement_final_p);

65581

+ gcc_assert (!complement_op1_p);

65582

+ gcc_assert (!complement_op2_p);

65583

+

65584

+ value_hi_lo[hi] = value >> 32;

65585

+ value_hi_lo[lo] = value & lower_32bits;

65586

+

65587

+ for (i = 0; i < 2; i++)

65588

+ {

65589

+ HOST_WIDE_INT sub_value = value_hi_lo[i];

65590

+

65591

+ if (sub_value & sign_bit)

65592

+ sub_value |= upper_32bits;

65593

+

65594

+ op2_hi_lo[i] = GEN_INT (sub_value);

65595

+

65596

+ /* If this is an AND instruction, check to see if we need to load

65597

+ the value in a register. */

65598

+ if (code == AND && sub_value != -1 && sub_value != 0

65599

+ && !and_operand (op2_hi_lo[i], SImode))

65600

+ op2_hi_lo[i] = force_reg (SImode, op2_hi_lo[i]);

65601

+ }

65602

+ }

65603

+ }

65604

+

65605

+ for (i = 0; i < 2; i++)

65606

+ {

65607

+ /* Split large IOR/XOR operations. */

65608

+ if ((code == IOR || code == XOR)

65609

+ && GET_CODE (op2_hi_lo[i]) == CONST_INT

65610

+ && !complement_final_p

65611

+ && !complement_op1_p

65612

+ && !complement_op2_p

65613

+ && clobber_reg == NULL_RTX

65614

+ && !logical_const_operand (op2_hi_lo[i], SImode))

65615

+ {

65616

+ HOST_WIDE_INT value = INTVAL (op2_hi_lo[i]);

65617

+ HOST_WIDE_INT hi_16bits = value & HOST_WIDE_INT_C(0xffff0000);

65618

+ HOST_WIDE_INT lo_16bits = value & HOST_WIDE_INT_C(0x0000ffff);

65619

+ rtx tmp = gen_reg_rtx (SImode);

65620

+

65621

+ /* Make sure the constant is sign extended. */

65622

+ if ((hi_16bits & sign_bit) != 0)

65623

+ hi_16bits |= upper_32bits;

65624

+

65625

+ rs6000_split_logical_inner (tmp, op1_hi_lo[i], GEN_INT (hi_16bits),

65626

+ code, SImode, false, false, false,

65627

+ NULL_RTX);

65628

+

65629

+ rs6000_split_logical_inner (op0_hi_lo[i], tmp, GEN_INT (lo_16bits),

65630

+ code, SImode, false, false, false,

65631

+ NULL_RTX);

65632

+ }

65633

+ else

65634

+ rs6000_split_logical_inner (op0_hi_lo[i], op1_hi_lo[i], op2_hi_lo[i],

65635

+ code, SImode, complement_final_p,

65636

+ complement_op1_p, complement_op2_p,

65637

+ clobber_reg);

65638

+ }

65639

+

65640

+ return;

65641

+}

65642

+

65643

+/* Split the insns that make up boolean operations operating on multiple GPR

65644

+ registers. The boolean MD patterns ensure that the inputs either are

65645

+ exactly the same as the output registers, or there is no overlap.

65646

+

65647

+ OPERANDS is an array containing the destination and two input operands.

65648

+ CODE is the base operation (AND, IOR, XOR, NOT).

65649

+ MODE is the machine mode.

65650

+ If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.

65651

+ If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.

65652

+ If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.

65653

+ CLOBBER_REG is either NULL or a scratch register of type CC to allow

65654

+ formation of the AND instructions. */

65655

+

65656

+void

65657

+rs6000_split_logical (rtx operands[3],

65658

+ enum rtx_code code,

65659

+ bool complement_final_p,

65660

+ bool complement_op1_p,

65661

+ bool complement_op2_p,

65662

+ rtx clobber_reg)

65663

+{

65664

+ enum machine_mode mode = GET_MODE (operands[0]);

65665

+ enum machine_mode sub_mode;

65666

+ rtx op0, op1, op2;

65667

+ int sub_size, regno0, regno1, nregs, i;

65668

+

65669

+ /* If this is DImode, use the specialized version that can run before

65670

+ register allocation. */

65671

+ if (mode == DImode && !TARGET_POWERPC64)

65672

+ {

65673

+ rs6000_split_logical_di (operands, code, complement_final_p,

65674

+ complement_op1_p, complement_op2_p,

65675

+ clobber_reg);

65676

+ return;

65677

+ }

65678

+

65679

+ op0 = operands[0];

65680

+ op1 = operands[1];

65681

+ op2 = (code == NOT) ? NULL_RTX : operands[2];

65682

+ sub_mode = (TARGET_POWERPC64) ? DImode : SImode;

65683

+ sub_size = GET_MODE_SIZE (sub_mode);

65684

+ regno0 = REGNO (op0);

65685

+ regno1 = REGNO (op1);

65686

+

65687

+ gcc_assert (reload_completed);

65688

+ gcc_assert (IN_RANGE (regno0, FIRST_GPR_REGNO, LAST_GPR_REGNO));

65689

+ gcc_assert (IN_RANGE (regno1, FIRST_GPR_REGNO, LAST_GPR_REGNO));

65690

+

65691

+ nregs = rs6000_hard_regno_nregs[(int)mode][regno0];

65692

+ gcc_assert (nregs > 1);

65693

+

65694

+ if (op2 && REG_P (op2))

65695

+ gcc_assert (IN_RANGE (REGNO (op2), FIRST_GPR_REGNO, LAST_GPR_REGNO));

65696

+

65697

+ for (i = 0; i < nregs; i++)

65698

+ {

65699

+ int offset = i * sub_size;

65700

+ rtx sub_op0 = simplify_subreg (sub_mode, op0, mode, offset);

65701

+ rtx sub_op1 = simplify_subreg (sub_mode, op1, mode, offset);

65702

+ rtx sub_op2 = ((code == NOT)

65703

+ ? NULL_RTX

65704

+ : simplify_subreg (sub_mode, op2, mode, offset));

65705

+

65706

+ rs6000_split_logical_inner (sub_op0, sub_op1, sub_op2, code, sub_mode,

65707

+ complement_final_p, complement_op1_p,

65708

+ complement_op2_p, clobber_reg);

65709

+ }

65710

+

65711

+ return;

65712

+}

65713

+

65714

+

65715

+/* Return true if the peephole2 can combine a load involving a combination of

65716

+ an addis instruction and a load with an offset that can be fused together on

65717

+ a power8.

65718

+

65719

+ The operands are:

65720

+ operands[0] register set with addis

65721

+ operands[1] value set via addis

65722

+ operands[2] target register being loaded

65723

+ operands[3] D-form memory reference using operands[0].

65724

+

65725

+ In addition, we are passed a boolean that is true if this is a peephole2,

65726

+ and we can use see if the addis_reg is dead after the insn and can be

65727

+ replaced by the target register. */

65728

+

65729

+bool

65730

+fusion_gpr_load_p (rtx *operands, bool peep2_p)

65731

+{

65732

+ rtx addis_reg = operands[0];

65733

+ rtx addis_value = operands[1];

65734

+ rtx target = operands[2];

65735

+ rtx mem = operands[3];

65736

+ rtx addr;

65737

+ rtx base_reg;

65738

+

65739

+ /* Validate arguments. */

65740

+ if (!base_reg_operand (addis_reg, GET_MODE (addis_reg)))

65741

+ return false;

65742

+

65743

+ if (!base_reg_operand (target, GET_MODE (target)))

65744

+ return false;

65745

+

65746

+ if (!fusion_gpr_addis (addis_value, GET_MODE (addis_value)))

65747

+ return false;

65748

+

65749

+ if (!fusion_gpr_mem_load (mem, GET_MODE (mem)))

65750

+ return false;

65751

+

65752

+ /* Allow sign/zero extension. */

65753

+ if (GET_CODE (mem) == ZERO_EXTEND

65754

+ || (GET_CODE (mem) == SIGN_EXTEND && TARGET_P8_FUSION_SIGN))

65755

+ mem = XEXP (mem, 0);

65756

+

65757

+ if (!MEM_P (mem))

65758

+ return false;

65759

+

65760

+ addr = XEXP (mem, 0); /* either PLUS or LO_SUM. */

65761

+ if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)

65762

+ return false;

65763

+

65764

+ /* Validate that the register used to load the high value is either the

65765

+ register being loaded, or we can safely replace its use in a peephole2.

65766

+

65767

+ If this is a peephole2, we assume that there are 2 instructions in the

65768

+ peephole (addis and load), so we want to check if the target register was

65769

+ not used in the memory address and the register to hold the addis result

65770

+ is dead after the peephole. */

65771

+ if (REGNO (addis_reg) != REGNO (target))

65772

+ {

65773

+ if (!peep2_p)

65774

+ return false;

65775

+

65776

+ if (reg_mentioned_p (target, mem))

65777

+ return false;

65778

+

65779

+ if (!peep2_reg_dead_p (2, addis_reg))

65780

+ return false;

65781

+

65782

+ /* If the target register being loaded is the stack pointer, we must

65783

+ avoid loading any other value into it, even temporarily. */

65784

+ if (REG_P (target) && REGNO (target) == STACK_POINTER_REGNUM)

65785

+ return false;

65786

+ }

65787

+

65788

+ base_reg = XEXP (addr, 0);

65789

+ return REGNO (addis_reg) == REGNO (base_reg);

65790

+}

65791

+

65792

+/* During the peephole2 pass, adjust and expand the insns for a load fusion

65793

+ sequence. We adjust the addis register to use the target register. If the

65794

+ load sign extends, we adjust the code to do the zero extending load, and an

65795

+ explicit sign extension later since the fusion only covers zero extending

65796

+ loads.

65797

+

65798

+ The operands are:

65799

+ operands[0] register set with addis (to be replaced with target)

65800

+ operands[1] value set via addis

65801

+ operands[2] target register being loaded

65802

+ operands[3] D-form memory reference using operands[0]. */

65803

+

65804

+void

65805

+expand_fusion_gpr_load (rtx *operands)

65806

+{

65807

+ rtx addis_value = operands[1];

65808

+ rtx target = operands[2];

65809

+ rtx orig_mem = operands[3];

65810

+ rtx new_addr, new_mem, orig_addr, offset;

65811

+ enum rtx_code plus_or_lo_sum;

65812

+ enum machine_mode target_mode = GET_MODE (target);

65813

+ enum machine_mode extend_mode = target_mode;

65814

+ enum machine_mode ptr_mode = Pmode;

65815

+ enum rtx_code extend = UNKNOWN;

65816

+ rtx addis_reg = ((ptr_mode == target_mode)

65817

+ ? target

65818

+ : simplify_subreg (ptr_mode, target, target_mode, 0));

65819

+

65820

+ if (GET_CODE (orig_mem) == ZERO_EXTEND

65821

+ || (TARGET_P8_FUSION_SIGN && GET_CODE (orig_mem) == SIGN_EXTEND))

65822

+ {

65823

+ extend = GET_CODE (orig_mem);

65824

+ orig_mem = XEXP (orig_mem, 0);

65825

+ target_mode = GET_MODE (orig_mem);

65826

+ }

65827

+

65828

+ gcc_assert (MEM_P (orig_mem));

65829

+

65830

+ orig_addr = XEXP (orig_mem, 0);

65831

+ plus_or_lo_sum = GET_CODE (orig_addr);

65832

+ gcc_assert (plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM);

65833

+

65834

+ offset = XEXP (orig_addr, 1);

65835

+ new_addr = gen_rtx_fmt_ee (plus_or_lo_sum, ptr_mode, addis_reg, offset);

65836

+ new_mem = change_address (orig_mem, target_mode, new_addr);

65837

+

65838

+ if (extend != UNKNOWN)

65839

+ new_mem = gen_rtx_fmt_e (ZERO_EXTEND, extend_mode, new_mem);

65840

+

65841

+ emit_insn (gen_rtx_SET (VOIDmode, addis_reg, addis_value));

65842

+ emit_insn (gen_rtx_SET (VOIDmode, target, new_mem));

65843

+

65844

+ if (extend == SIGN_EXTEND)

65845

+ {

65846

+ int sub_off = ((BYTES_BIG_ENDIAN)

65847

+ ? GET_MODE_SIZE (extend_mode) - GET_MODE_SIZE (target_mode)

65848

+ : 0);

65849

+ rtx sign_reg

65850

+ = simplify_subreg (target_mode, target, extend_mode, sub_off);

65851

+

65852

+ emit_insn (gen_rtx_SET (VOIDmode, target,

65853

+ gen_rtx_SIGN_EXTEND (extend_mode, sign_reg)));

65854

+ }

65855

+

65856

+ return;

65857

+}

65858

+

65859

+/* Return a string to fuse an addis instruction with a gpr load to the same

65860

+ register that we loaded up the addis instruction. The code is complicated,

65861

+ so we call output_asm_insn directly, and just return "".

65862

+

65863

+ The operands are:

65864

+ operands[0] register set with addis (must be same reg as target).

65865

+ operands[1] value set via addis

65866

+ operands[2] target register being loaded

65867

+ operands[3] D-form memory reference using operands[0]. */

65868

+

65869

+const char *

65870

+emit_fusion_gpr_load (rtx *operands)

65871

+{

65872

+ rtx addis_reg = operands[0];

65873

+ rtx addis_value = operands[1];

65874

+ rtx target = operands[2];

65875

+ rtx mem = operands[3];

65876

+ rtx fuse_ops[10];

65877

+ rtx addr;

65878

+ rtx load_offset;

65879

+ const char *addis_str = NULL;

65880

+ const char *load_str = NULL;

65881

+ const char *extend_insn = NULL;

65882

+ const char *mode_name = NULL;

65883

+ char insn_template[80];

65884

+ enum machine_mode mode;

65885

+ const char *comment_str = ASM_COMMENT_START;

65886

+ bool sign_p = false;

65887

+

65888

+ gcc_assert (REG_P (addis_reg) && REG_P (target));

65889

+ gcc_assert (REGNO (addis_reg) == REGNO (target));

65890

+

65891

+ if (*comment_str == ' ')

65892

+ comment_str++;

65893

+

65894

+ /* Allow sign/zero extension. */

65895

+ if (GET_CODE (mem) == ZERO_EXTEND)

65896

+ mem = XEXP (mem, 0);

65897

+

65898

+ else if (GET_CODE (mem) == SIGN_EXTEND && TARGET_P8_FUSION_SIGN)

65899

+ {

65900

+ sign_p = true;

65901

+ mem = XEXP (mem, 0);

65902

+ }

65903

+

65904

+ gcc_assert (MEM_P (mem));

65905

+ addr = XEXP (mem, 0);

65906

+ if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)

65907

+ gcc_unreachable ();

65908

+

65909

+ load_offset = XEXP (addr, 1);

65910

+

65911

+ /* Now emit the load instruction to the same register. */

65912

+ mode = GET_MODE (mem);

65913

+ switch (mode)

65914

+ {

65915

+ case QImode:

65916

+ mode_name = "char";

65917

+ load_str = "lbz";

65918

+ extend_insn = "extsb %0,%0";

65919

+ break;

65920

+

65921

+ case HImode:

65922

+ mode_name = "short";

65923

+ load_str = "lhz";

65924

+ extend_insn = "extsh %0,%0";

65925

+ break;

65926

+

65927

+ case SImode:

65928

+ mode_name = "int";

65929

+ load_str = "lwz";

65930

+ extend_insn = "extsw %0,%0";

65931

+ break;

65932

+

65933

+ case DImode:

65934

+ if (TARGET_POWERPC64)

65935

+ {

65936

+ mode_name = "long";

65937

+ load_str = "ld";

65938

+ }

65939

+ else

65940

+ gcc_unreachable ();

65941

+ break;

65942

+

65943

+ default:

65944

+ gcc_unreachable ();

65945

+ }

65946

+

65947

+ /* Emit the addis instruction. */

65948

+ fuse_ops[0] = target;

65949

+ if (satisfies_constraint_L (addis_value))

65950

+ {

65951

+ fuse_ops[1] = addis_value;

65952

+ addis_str = "lis %0,%v1";

65953

+ }

65954

+

65955

+ else if (GET_CODE (addis_value) == PLUS)

65956

+ {

65957

+ rtx op0 = XEXP (addis_value, 0);

65958

+ rtx op1 = XEXP (addis_value, 1);

65959

+

65960

+ if (REG_P (op0) && CONST_INT_P (op1)

65961

+ && satisfies_constraint_L (op1))

65962

+ {

65963

+ fuse_ops[1] = op0;

65964

+ fuse_ops[2] = op1;

65965

+ addis_str = "addis %0,%1,%v2";

65966

+ }

65967

+ }

65968

+

65969

+ else if (GET_CODE (addis_value) == HIGH)

65970

+ {

65971

+ rtx value = XEXP (addis_value, 0);

65972

+ if (GET_CODE (value) == UNSPEC && XINT (value, 1) == UNSPEC_TOCREL)

65973

+ {

65974

+ fuse_ops[1] = XVECEXP (value, 0, 0); /* symbol ref. */

65975

+ fuse_ops[2] = XVECEXP (value, 0, 1); /* TOC register. */

65976

+ if (TARGET_ELF)

65977

+ addis_str = "addis %0,%2,%1@toc@ha";

65978

+

65979

+ else if (TARGET_XCOFF)

65980

+ addis_str = "addis %0,%1@u(%2)";

65981

+

65982

+ else

65983

+ gcc_unreachable ();

65984

+ }

65985

+

65986

+ else if (GET_CODE (value) == PLUS)

65987

+ {

65988

+ rtx op0 = XEXP (value, 0);

65989

+ rtx op1 = XEXP (value, 1);

65990

+

65991

+ if (GET_CODE (op0) == UNSPEC

65992

+ && XINT (op0, 1) == UNSPEC_TOCREL

65993

+ && CONST_INT_P (op1))

65994

+ {

65995

+ fuse_ops[1] = XVECEXP (op0, 0, 0); /* symbol ref. */

65996

+ fuse_ops[2] = XVECEXP (op0, 0, 1); /* TOC register. */

65997

+ fuse_ops[3] = op1;

65998

+ if (TARGET_ELF)

65999

+ addis_str = "addis %0,%2,%1+%3@toc@ha";

66000

+

66001

+ else if (TARGET_XCOFF)

66002

+ addis_str = "addis %0,%1+%3@u(%2)";

66003

+

66004

+ else

66005

+ gcc_unreachable ();

66006

+ }

66007

+ }

66008

+

66009

+ else if (satisfies_constraint_L (value))

66010

+ {

66011

+ fuse_ops[1] = value;

66012

+ addis_str = "lis %0,%v1";

66013

+ }

66014

+

66015

+ else if (TARGET_ELF && !TARGET_POWERPC64 && CONSTANT_P (value))

66016

+ {

66017

+ fuse_ops[1] = value;

66018

+ addis_str = "lis %0,%1@ha";

66019

+ }

66020

+ }

66021

+

66022

+ if (!addis_str)

66023

+ fatal_insn ("Could not generate addis value for fusion", addis_value);

66024

+

66025

+ sprintf (insn_template, "%s\t\t%s gpr load fusion, type %s", addis_str,

66026

+ comment_str, mode_name);

66027

+ output_asm_insn (insn_template, fuse_ops);

66028

+

66029

+ /* Emit the D-form load instruction. */

66030

+ if (CONST_INT_P (load_offset) && satisfies_constraint_I (load_offset))

66031

+ {

66032

+ sprintf (insn_template, "%s %%0,%%1(%%0)", load_str);

66033

+ fuse_ops[1] = load_offset;

66034

+ output_asm_insn (insn_template, fuse_ops);

66035

+ }

66036

+

66037

+ else if (GET_CODE (load_offset) == UNSPEC

66038

+ && XINT (load_offset, 1) == UNSPEC_TOCREL)

66039

+ {

66040

+ if (TARGET_ELF)

66041

+ sprintf (insn_template, "%s %%0,%%1@toc@l(%%0)", load_str);

66042

+

66043

+ else if (TARGET_XCOFF)

66044

+ sprintf (insn_template, "%s %%0,%%1@l(%%0)", load_str);

66045

+

66046

+ else

66047

+ gcc_unreachable ();

66048

+

66049

+ fuse_ops[1] = XVECEXP (load_offset, 0, 0);

66050

+ output_asm_insn (insn_template, fuse_ops);

66051

+ }

66052

+

66053

+ else if (GET_CODE (load_offset) == PLUS

66054

+ && GET_CODE (XEXP (load_offset, 0)) == UNSPEC

66055

+ && XINT (XEXP (load_offset, 0), 1) == UNSPEC_TOCREL

66056

+ && CONST_INT_P (XEXP (load_offset, 1)))

66057

+ {

66058

+ rtx tocrel_unspec = XEXP (load_offset, 0);

66059

+ if (TARGET_ELF)

66060

+ sprintf (insn_template, "%s %%0,%%1+%%2@toc@l(%%0)", load_str);

66061

+

66062

+ else if (TARGET_XCOFF)

66063

+ sprintf (insn_template, "%s %%0,%%1+%%2@l(%%0)", load_str);

66064

+

66065

+ else

66066

+ gcc_unreachable ();

66067

+

66068

+ fuse_ops[1] = XVECEXP (tocrel_unspec, 0, 0);

66069

+ fuse_ops[2] = XEXP (load_offset, 1);

66070

+ output_asm_insn (insn_template, fuse_ops);

66071

+ }

66072

+

66073

+ else if (TARGET_ELF && !TARGET_POWERPC64 && CONSTANT_P (load_offset))

66074

+ {

66075

+ sprintf (insn_template, "%s %%0,%%1@l(%%0)", load_str);

66076

+

66077

+ fuse_ops[1] = load_offset;

66078

+ output_asm_insn (insn_template, fuse_ops);

66079

+ }

66080

+

66081

+ else

66082

+ fatal_insn ("Unable to generate load offset for fusion", load_offset);

66083

+

66084

+ /* Handle sign extension. The peephole2 pass generates this as a separate

66085

+ insn, but we handle it just in case it got reattached. */

66086

+ if (sign_p)

66087

+ {

66088

+ gcc_assert (extend_insn != NULL);

66089

+ output_asm_insn (extend_insn, fuse_ops);

66090

+ }

66091

+

66092

+ return "";

66093

+}

66094

+

66095

+

66096

struct gcc_target targetm = TARGET_INITIALIZER;

66097

66098

#include "gt-rs6000.h"

66099

Index: gcc/config/rs6000/vsx.md

66100

===================================================================

66101

--- a/src/gcc/config/rs6000/vsx.md (.../tags/gcc_4_8_2_release)

66102

+++ b/src/gcc/config/rs6000/vsx.md (.../branches/gcc-4_8-branch)

66103

@@ -34,12 +34,21 @@

66104

(define_mode_iterator VSX_F [V4SF V2DF])

66105

66106

;; Iterator for logical types supported by VSX

66107

-(define_mode_iterator VSX_L [V16QI V8HI V4SI V2DI V4SF V2DF TI])

66108

+(define_mode_iterator VSX_L [V16QI V8HI V4SI V2DI V4SF V2DF V1TI TI])

66109

66110

;; Iterator for memory move. Handle TImode specially to allow

66111

;; it to use gprs as well as vsx registers.

66112

-(define_mode_iterator VSX_M [V16QI V8HI V4SI V2DI V4SF V2DF])

66113

+(define_mode_iterator VSX_M [V16QI V8HI V4SI V2DI V4SF V2DF V1TI])

66114

66115

+(define_mode_iterator VSX_M2 [V16QI

66116

+ V8HI

66117

+ V4SI

66118

+ V2DI

66119

+ V4SF

66120

+ V2DF

66121

+ V1TI

66122

+ (TI "TARGET_VSX_TIMODE")])

66123

+

66124

;; Map into the appropriate load/store name based on the type

66125

(define_mode_attr VSm [(V16QI "vw4")

66126

(V8HI "vw4")

66127

@@ -48,7 +57,8 @@

66128

(V2DF "vd2")

66129

(V2DI "vd2")

66130

(DF "d")

66131

- (TI "vw4")])

66132

+ (V1TI "vd2")

66133

+ (TI "vd2")])

66134

66135

;; Map into the appropriate suffix based on the type

66136

(define_mode_attr VSs [(V16QI "sp")

66137

@@ -59,7 +69,8 @@

66138

(V2DI "dp")

66139

(DF "dp")

66140

(SF "sp")

66141

- (TI "sp")])

66142

+ (V1TI "dp")

66143

+ (TI "dp")])

66144

66145

;; Map the register class used

66146

(define_mode_attr VSr [(V16QI "v")

66147

@@ -70,7 +81,8 @@

66148

(V2DF "wd")

66149

(DF "ws")

66150

(SF "d")

66151

- (TI "wd")])

66152

+ (V1TI "v")

66153

+ (TI "wt")])

66154

66155

;; Map the register class used for float<->int conversions

66156

(define_mode_attr VSr2 [(V2DF "wd")

66157

@@ -115,7 +127,7 @@

66158

(V4SF "v")

66159

(V2DI "v")

66160

(V2DF "v")

66161

- (TI "v")

66162

+ (V1TI "v")

66163

(DF "s")])

66164

66165

;; Appropriate type for add ops (and other simple FP ops)

66166

@@ -173,7 +185,8 @@

66167

(V2DF "vecdouble")])

66168

66169

;; Map the scalar mode for a vector type

66170

-(define_mode_attr VS_scalar [(V2DF "DF")

66171

+(define_mode_attr VS_scalar [(V1TI "TI")

66172

+ (V2DF "DF")

66173

(V2DI "DI")

66174

(V4SF "SF")

66175

(V4SI "SI")

66176

@@ -184,7 +197,8 @@

66177

(define_mode_attr VS_double [(V4SI "V8SI")

66178

(V4SF "V8SF")

66179

(V2DI "V4DI")

66180

- (V2DF "V4DF")])

66181

+ (V2DF "V4DF")

66182

+ (V1TI "V2TI")])

66183

66184

;; Constants for creating unspecs

66185

(define_c_enum "unspec"

66186

@@ -192,6 +206,8 @@

66187

UNSPEC_VSX_CVDPSXWS

66188

UNSPEC_VSX_CVDPUXWS

66189

UNSPEC_VSX_CVSPDP

66190

+ UNSPEC_VSX_CVSPDPN

66191

+ UNSPEC_VSX_CVDPSPN

66192

UNSPEC_VSX_CVSXWDP

66193

UNSPEC_VSX_CVUXWDP

66194

UNSPEC_VSX_CVSXDSP

66195

@@ -204,80 +220,397 @@

66196

UNSPEC_VSX_ROUND_I

66197

UNSPEC_VSX_ROUND_IC

66198

UNSPEC_VSX_SLDWI

66199

+ UNSPEC_VSX_XXSPLTW

66200

])

66201

66202

;; VSX moves

66203

-(define_insn "*vsx_mov<mode>"

66204

- [(set (match_operand:VSX_M 0 "nonimmediate_operand" "=Z,<VSr>,<VSr>,?Z,?wa,?wa,*Y,*r,*r,<VSr>,?wa,*r,v,wZ,v")

66205

- (match_operand:VSX_M 1 "input_operand" "<VSr>,Z,<VSr>,wa,Z,wa,r,Y,r,j,j,j,W,v,wZ"))]

66206

- "VECTOR_MEM_VSX_P (<MODE>mode)

66207

- && (register_operand (operands[0], <MODE>mode)

66208

- || register_operand (operands[1], <MODE>mode))"

66209

+

66210

+;; The patterns for LE permuted loads and stores come before the general

66211

+;; VSX moves so they match first.

66212

+(define_insn_and_split "*vsx_le_perm_load_<mode>"

66213

+ [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wa")

66214

+ (match_operand:VSX_D 1 "memory_operand" "Z"))]

66215

+ "!BYTES_BIG_ENDIAN && TARGET_VSX"

66216

+ "#"

66217

+ "!BYTES_BIG_ENDIAN && TARGET_VSX"

66218

+ [(set (match_dup 2)

66219

+ (vec_select:<MODE>

66220

+ (match_dup 1)

66221

+ (parallel [(const_int 1) (const_int 0)])))

66222

+ (set (match_dup 0)

66223

+ (vec_select:<MODE>

66224

+ (match_dup 2)

66225

+ (parallel [(const_int 1) (const_int 0)])))]

66226

+ "

66227

{

66228

- switch (which_alternative)

66229

- {

66230

- case 0:

66231

- case 3:

66232

- gcc_assert (MEM_P (operands[0])

66233

- && GET_CODE (XEXP (operands[0], 0)) != PRE_INC

66234

- && GET_CODE (XEXP (operands[0], 0)) != PRE_DEC

66235

- && GET_CODE (XEXP (operands[0], 0)) != PRE_MODIFY);

66236

- return "stx<VSm>x %x1,%y0";

66237

+ operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[0])

66238

+ : operands[0];

66239

+}

66240

+ "

66241

+ [(set_attr "type" "vecload")

66242

+ (set_attr "length" "8")])

66243

66244

- case 1:

66245

- case 4:

66246

- gcc_assert (MEM_P (operands[1])

66247

- && GET_CODE (XEXP (operands[1], 0)) != PRE_INC

66248

- && GET_CODE (XEXP (operands[1], 0)) != PRE_DEC

66249

- && GET_CODE (XEXP (operands[1], 0)) != PRE_MODIFY);

66250

- return "lx<VSm>x %x0,%y1";

66251

+(define_insn_and_split "*vsx_le_perm_load_<mode>"

66252

+ [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa")

66253

+ (match_operand:VSX_W 1 "memory_operand" "Z"))]

66254

+ "!BYTES_BIG_ENDIAN && TARGET_VSX"

66255

+ "#"

66256

+ "!BYTES_BIG_ENDIAN && TARGET_VSX"

66257

+ [(set (match_dup 2)

66258

+ (vec_select:<MODE>

66259

+ (match_dup 1)

66260

+ (parallel [(const_int 2) (const_int 3)

66261

+ (const_int 0) (const_int 1)])))

66262

+ (set (match_dup 0)

66263

+ (vec_select:<MODE>

66264

+ (match_dup 2)

66265

+ (parallel [(const_int 2) (const_int 3)

66266

+ (const_int 0) (const_int 1)])))]

66267

+ "

66268

+{

66269

+ operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[0])

66270

+ : operands[0];

66271

+}

66272

+ "

66273

+ [(set_attr "type" "vecload")

66274

+ (set_attr "length" "8")])

66275

66276

- case 2:

66277

- case 5:

66278

- return "xxlor %x0,%x1,%x1";

66279

+(define_insn_and_split "*vsx_le_perm_load_v8hi"

66280

+ [(set (match_operand:V8HI 0 "vsx_register_operand" "=wa")

66281

+ (match_operand:V8HI 1 "memory_operand" "Z"))]

66282

+ "!BYTES_BIG_ENDIAN && TARGET_VSX"

66283

+ "#"

66284

+ "!BYTES_BIG_ENDIAN && TARGET_VSX"

66285

+ [(set (match_dup 2)

66286

+ (vec_select:V8HI

66287

+ (match_dup 1)

66288

+ (parallel [(const_int 4) (const_int 5)

66289

+ (const_int 6) (const_int 7)

66290

+ (const_int 0) (const_int 1)

66291

+ (const_int 2) (const_int 3)])))

66292

+ (set (match_dup 0)

66293

+ (vec_select:V8HI

66294

+ (match_dup 2)

66295

+ (parallel [(const_int 4) (const_int 5)

66296

+ (const_int 6) (const_int 7)

66297

+ (const_int 0) (const_int 1)

66298

+ (const_int 2) (const_int 3)])))]

66299

+ "

66300

+{

66301

+ operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[0])

66302

+ : operands[0];

66303

+}

66304

+ "

66305

+ [(set_attr "type" "vecload")

66306

+ (set_attr "length" "8")])

66307

66308

- case 6:

66309

- case 7:

66310

- case 8:

66311

- case 11:

66312

- return "#";

66313

+(define_insn_and_split "*vsx_le_perm_load_v16qi"

66314

+ [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa")

66315

+ (match_operand:V16QI 1 "memory_operand" "Z"))]

66316

+ "!BYTES_BIG_ENDIAN && TARGET_VSX"

66317

+ "#"

66318

+ "!BYTES_BIG_ENDIAN && TARGET_VSX"

66319

+ [(set (match_dup 2)

66320

+ (vec_select:V16QI

66321

+ (match_dup 1)

66322

+ (parallel [(const_int 8) (const_int 9)

66323

+ (const_int 10) (const_int 11)

66324

+ (const_int 12) (const_int 13)

66325

+ (const_int 14) (const_int 15)

66326

+ (const_int 0) (const_int 1)

66327

+ (const_int 2) (const_int 3)

66328

+ (const_int 4) (const_int 5)

66329

+ (const_int 6) (const_int 7)])))

66330

+ (set (match_dup 0)

66331

+ (vec_select:V16QI

66332

+ (match_dup 2)

66333

+ (parallel [(const_int 8) (const_int 9)

66334

+ (const_int 10) (const_int 11)

66335

+ (const_int 12) (const_int 13)

66336

+ (const_int 14) (const_int 15)

66337

+ (const_int 0) (const_int 1)

66338

+ (const_int 2) (const_int 3)

66339

+ (const_int 4) (const_int 5)

66340

+ (const_int 6) (const_int 7)])))]

66341

+ "

66342

+{

66343

+ operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[0])

66344

+ : operands[0];

66345

+}

66346

+ "

66347

+ [(set_attr "type" "vecload")

66348

+ (set_attr "length" "8")])

66349

66350

- case 9:

66351

- case 10:

66352

- return "xxlxor %x0,%x0,%x0";

66353

+(define_insn "*vsx_le_perm_store_<mode>"

66354

+ [(set (match_operand:VSX_D 0 "memory_operand" "=Z")

66355

+ (match_operand:VSX_D 1 "vsx_register_operand" "+wa"))]

66356

+ "!BYTES_BIG_ENDIAN && TARGET_VSX"

66357

+ "#"

66358

+ [(set_attr "type" "vecstore")

66359

+ (set_attr "length" "12")])

66360

66361

- case 12:

66362

- return output_vec_const_move (operands);

66363

+(define_split

66364

+ [(set (match_operand:VSX_D 0 "memory_operand" "")

66365

+ (match_operand:VSX_D 1 "vsx_register_operand" ""))]

66366

+ "!BYTES_BIG_ENDIAN && TARGET_VSX && !reload_completed"

66367

+ [(set (match_dup 2)

66368

+ (vec_select:<MODE>

66369

+ (match_dup 1)

66370

+ (parallel [(const_int 1) (const_int 0)])))

66371

+ (set (match_dup 0)

66372

+ (vec_select:<MODE>

66373

+ (match_dup 2)

66374

+ (parallel [(const_int 1) (const_int 0)])))]

66375

+{

66376

+ operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[1])

66377

+ : operands[1];

66378

+})

66379

66380

- case 13:

66381

- gcc_assert (MEM_P (operands[0])

66382

- && GET_CODE (XEXP (operands[0], 0)) != PRE_INC

66383

- && GET_CODE (XEXP (operands[0], 0)) != PRE_DEC

66384

- && GET_CODE (XEXP (operands[0], 0)) != PRE_MODIFY);

66385

- return "stvx %1,%y0";

66386

+;; The post-reload split requires that we re-permute the source

66387

+;; register in case it is still live.

66388

+(define_split

66389

+ [(set (match_operand:VSX_D 0 "memory_operand" "")

66390

+ (match_operand:VSX_D 1 "vsx_register_operand" ""))]

66391

+ "!BYTES_BIG_ENDIAN && TARGET_VSX && reload_completed"

66392

+ [(set (match_dup 1)

66393

+ (vec_select:<MODE>

66394

+ (match_dup 1)

66395

+ (parallel [(const_int 1) (const_int 0)])))

66396

+ (set (match_dup 0)

66397

+ (vec_select:<MODE>

66398

+ (match_dup 1)

66399

+ (parallel [(const_int 1) (const_int 0)])))

66400

+ (set (match_dup 1)

66401

+ (vec_select:<MODE>

66402

+ (match_dup 1)

66403

+ (parallel [(const_int 1) (const_int 0)])))]

66404

+ "")

66405

66406

- case 14:

66407

- gcc_assert (MEM_P (operands[0])

66408

- && GET_CODE (XEXP (operands[0], 0)) != PRE_INC

66409

- && GET_CODE (XEXP (operands[0], 0)) != PRE_DEC

66410

- && GET_CODE (XEXP (operands[0], 0)) != PRE_MODIFY);

66411

- return "lvx %0,%y1";

66412

+(define_insn "*vsx_le_perm_store_<mode>"

66413

+ [(set (match_operand:VSX_W 0 "memory_operand" "=Z")

66414

+ (match_operand:VSX_W 1 "vsx_register_operand" "+wa"))]

66415

+ "!BYTES_BIG_ENDIAN && TARGET_VSX"

66416

+ "#"

66417

+ [(set_attr "type" "vecstore")

66418

+ (set_attr "length" "12")])

66419

66420

- default:

66421

- gcc_unreachable ();

66422

- }

66423

+(define_split

66424

+ [(set (match_operand:VSX_W 0 "memory_operand" "")

66425

+ (match_operand:VSX_W 1 "vsx_register_operand" ""))]

66426

+ "!BYTES_BIG_ENDIAN && TARGET_VSX && !reload_completed"

66427

+ [(set (match_dup 2)

66428

+ (vec_select:<MODE>

66429

+ (match_dup 1)

66430

+ (parallel [(const_int 2) (const_int 3)

66431

+ (const_int 0) (const_int 1)])))

66432

+ (set (match_dup 0)

66433

+ (vec_select:<MODE>

66434

+ (match_dup 2)

66435

+ (parallel [(const_int 2) (const_int 3)

66436

+ (const_int 0) (const_int 1)])))]

66437

+{

66438

+ operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[1])

66439

+ : operands[1];

66440

+})

66441

+

66442

+;; The post-reload split requires that we re-permute the source

66443

+;; register in case it is still live.

66444

+(define_split

66445

+ [(set (match_operand:VSX_W 0 "memory_operand" "")

66446

+ (match_operand:VSX_W 1 "vsx_register_operand" ""))]

66447

+ "!BYTES_BIG_ENDIAN && TARGET_VSX && reload_completed"

66448

+ [(set (match_dup 1)

66449

+ (vec_select:<MODE>

66450

+ (match_dup 1)

66451

+ (parallel [(const_int 2) (const_int 3)

66452

+ (const_int 0) (const_int 1)])))

66453

+ (set (match_dup 0)

66454

+ (vec_select:<MODE>

66455

+ (match_dup 1)

66456

+ (parallel [(const_int 2) (const_int 3)

66457

+ (const_int 0) (const_int 1)])))

66458

+ (set (match_dup 1)

66459

+ (vec_select:<MODE>

66460

+ (match_dup 1)

66461

+ (parallel [(const_int 2) (const_int 3)

66462

+ (const_int 0) (const_int 1)])))]

66463

+ "")

66464

+

66465

+(define_insn "*vsx_le_perm_store_v8hi"

66466

+ [(set (match_operand:V8HI 0 "memory_operand" "=Z")

66467

+ (match_operand:V8HI 1 "vsx_register_operand" "+wa"))]

66468

+ "!BYTES_BIG_ENDIAN && TARGET_VSX"

66469

+ "#"

66470

+ [(set_attr "type" "vecstore")

66471

+ (set_attr "length" "12")])

66472

+

66473

+(define_split

66474

+ [(set (match_operand:V8HI 0 "memory_operand" "")

66475

+ (match_operand:V8HI 1 "vsx_register_operand" ""))]

66476

+ "!BYTES_BIG_ENDIAN && TARGET_VSX && !reload_completed"

66477

+ [(set (match_dup 2)

66478

+ (vec_select:V8HI

66479

+ (match_dup 1)

66480

+ (parallel [(const_int 4) (const_int 5)

66481

+ (const_int 6) (const_int 7)

66482

+ (const_int 0) (const_int 1)

66483

+ (const_int 2) (const_int 3)])))

66484

+ (set (match_dup 0)

66485

+ (vec_select:V8HI

66486

+ (match_dup 2)

66487

+ (parallel [(const_int 4) (const_int 5)

66488

+ (const_int 6) (const_int 7)

66489

+ (const_int 0) (const_int 1)

66490

+ (const_int 2) (const_int 3)])))]

66491

+{

66492

+ operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[1])

66493

+ : operands[1];

66494

+})

66495

+

66496

+;; The post-reload split requires that we re-permute the source

66497

+;; register in case it is still live.

66498

+(define_split

66499

+ [(set (match_operand:V8HI 0 "memory_operand" "")

66500

+ (match_operand:V8HI 1 "vsx_register_operand" ""))]

66501

+ "!BYTES_BIG_ENDIAN && TARGET_VSX && reload_completed"

66502

+ [(set (match_dup 1)

66503

+ (vec_select:V8HI

66504

+ (match_dup 1)

66505

+ (parallel [(const_int 4) (const_int 5)

66506

+ (const_int 6) (const_int 7)

66507

+ (const_int 0) (const_int 1)

66508

+ (const_int 2) (const_int 3)])))

66509

+ (set (match_dup 0)

66510

+ (vec_select:V8HI

66511

+ (match_dup 1)

66512

+ (parallel [(const_int 4) (const_int 5)

66513

+ (const_int 6) (const_int 7)

66514

+ (const_int 0) (const_int 1)

66515

+ (const_int 2) (const_int 3)])))

66516

+ (set (match_dup 1)

66517

+ (vec_select:V8HI

66518

+ (match_dup 1)

66519

+ (parallel [(const_int 4) (const_int 5)

66520

+ (const_int 6) (const_int 7)

66521

+ (const_int 0) (const_int 1)

66522

+ (const_int 2) (const_int 3)])))]

66523

+ "")

66524

+

66525

+(define_insn "*vsx_le_perm_store_v16qi"

66526

+ [(set (match_operand:V16QI 0 "memory_operand" "=Z")

66527

+ (match_operand:V16QI 1 "vsx_register_operand" "+wa"))]

66528

+ "!BYTES_BIG_ENDIAN && TARGET_VSX"

66529

+ "#"

66530

+ [(set_attr "type" "vecstore")

66531

+ (set_attr "length" "12")])

66532

+

66533

+(define_split

66534

+ [(set (match_operand:V16QI 0 "memory_operand" "")

66535

+ (match_operand:V16QI 1 "vsx_register_operand" ""))]

66536

+ "!BYTES_BIG_ENDIAN && TARGET_VSX && !reload_completed"

66537

+ [(set (match_dup 2)

66538

+ (vec_select:V16QI

66539

+ (match_dup 1)

66540

+ (parallel [(const_int 8) (const_int 9)

66541

+ (const_int 10) (const_int 11)

66542

+ (const_int 12) (const_int 13)

66543

+ (const_int 14) (const_int 15)

66544

+ (const_int 0) (const_int 1)

66545

+ (const_int 2) (const_int 3)

66546

+ (const_int 4) (const_int 5)

66547

+ (const_int 6) (const_int 7)])))

66548

+ (set (match_dup 0)

66549

+ (vec_select:V16QI

66550

+ (match_dup 2)

66551

+ (parallel [(const_int 8) (const_int 9)

66552

+ (const_int 10) (const_int 11)

66553

+ (const_int 12) (const_int 13)

66554

+ (const_int 14) (const_int 15)

66555

+ (const_int 0) (const_int 1)

66556

+ (const_int 2) (const_int 3)

66557

+ (const_int 4) (const_int 5)

66558

+ (const_int 6) (const_int 7)])))]

66559

+{

66560

+ operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[1])

66561

+ : operands[1];

66562

+})

66563

+

66564

+;; The post-reload split requires that we re-permute the source

66565

+;; register in case it is still live.

66566

+(define_split

66567

+ [(set (match_operand:V16QI 0 "memory_operand" "")

66568

+ (match_operand:V16QI 1 "vsx_register_operand" ""))]

66569

+ "!BYTES_BIG_ENDIAN && TARGET_VSX && reload_completed"

66570

+ [(set (match_dup 1)

66571

+ (vec_select:V16QI

66572

+ (match_dup 1)

66573

+ (parallel [(const_int 8) (const_int 9)

66574

+ (const_int 10) (const_int 11)

66575

+ (const_int 12) (const_int 13)

66576

+ (const_int 14) (const_int 15)

66577

+ (const_int 0) (const_int 1)

66578

+ (const_int 2) (const_int 3)

66579

+ (const_int 4) (const_int 5)

66580

+ (const_int 6) (const_int 7)])))

66581

+ (set (match_dup 0)

66582

+ (vec_select:V16QI

66583

+ (match_dup 1)

66584

+ (parallel [(const_int 8) (const_int 9)

66585

+ (const_int 10) (const_int 11)

66586

+ (const_int 12) (const_int 13)

66587

+ (const_int 14) (const_int 15)

66588

+ (const_int 0) (const_int 1)

66589

+ (const_int 2) (const_int 3)

66590

+ (const_int 4) (const_int 5)

66591

+ (const_int 6) (const_int 7)])))

66592

+ (set (match_dup 1)

66593

+ (vec_select:V16QI

66594

+ (match_dup 1)

66595

+ (parallel [(const_int 8) (const_int 9)

66596

+ (const_int 10) (const_int 11)

66597

+ (const_int 12) (const_int 13)

66598

+ (const_int 14) (const_int 15)

66599

+ (const_int 0) (const_int 1)

66600

+ (const_int 2) (const_int 3)

66601

+ (const_int 4) (const_int 5)

66602

+ (const_int 6) (const_int 7)])))]

66603

+ "")

66604

+

66605

+

66606

+(define_insn "*vsx_mov<mode>"

66607

+ [(set (match_operand:VSX_M 0 "nonimmediate_operand" "=Z,<VSr>,<VSr>,?Z,?wa,?wa,wQ,?&r,??Y,??r,??r,<VSr>,?wa,*r,v,wZ, v")

66608

+ (match_operand:VSX_M 1 "input_operand" "<VSr>,Z,<VSr>,wa,Z,wa,r,wQ,r,Y,r,j,j,j,W,v,wZ"))]

66609

+ "VECTOR_MEM_VSX_P (<MODE>mode)

66610

+ && (register_operand (operands[0], <MODE>mode)

66611

+ || register_operand (operands[1], <MODE>mode))"

66612

+{

66613

+ return rs6000_output_move_128bit (operands);

66614

}

66615

- [(set_attr "type" "vecstore,vecload,vecsimple,vecstore,vecload,vecsimple,*,*,*,vecsimple,vecsimple,*,*,vecstore,vecload")])

66616

+ [(set_attr "type" "vecstore,vecload,vecsimple,vecstore,vecload,vecsimple,load,store,store,load, *,vecsimple,vecsimple,*, *,vecstore,vecload")

66617

+ (set_attr "length" "4,4,4,4,4,4,12,12,12,12,16,4,4,*,16,4,4")])

66618

66619

-;; Unlike other VSX moves, allow the GPRs, since a normal use of TImode is for

66620

-;; unions. However for plain data movement, slightly favor the vector loads

66621

-(define_insn "*vsx_movti"

66622

- [(set (match_operand:TI 0 "nonimmediate_operand" "=Z,wa,wa,?Y,?r,?r,wa,v,v,wZ")

66623

- (match_operand:TI 1 "input_operand" "wa,Z,wa,r,Y,r,j,W,wZ,v"))]

66624

- "VECTOR_MEM_VSX_P (TImode)

66625

+;; Unlike other VSX moves, allow the GPRs even for reloading, since a normal

66626

+;; use of TImode is for unions. However for plain data movement, slightly

66627

+;; favor the vector loads

66628

+(define_insn "*vsx_movti_64bit"

66629

+ [(set (match_operand:TI 0 "nonimmediate_operand" "=Z,wa,wa,wa,v,v,wZ,wQ,&r,Y,r,r,?r")

66630

+ (match_operand:TI 1 "input_operand" "wa,Z,wa,O,W,wZ,v,r,wQ,r,Y,r,n"))]

66631

+ "TARGET_POWERPC64 && VECTOR_MEM_VSX_P (TImode)

66632

&& (register_operand (operands[0], TImode)

66633

|| register_operand (operands[1], TImode))"

66634

{

66635

+ return rs6000_output_move_128bit (operands);

66636

+}

66637

+ [(set_attr "type" "vecstore,vecload,vecsimple,vecsimple,vecsimple,vecstore,vecload,store,load,store,load,*,*")

66638

+ (set_attr "length" "4,4,4,4,16,4,4,8,8,8,8,8,8")])

66639

+

66640

+(define_insn "*vsx_movti_32bit"

66641

+ [(set (match_operand:TI 0 "nonimmediate_operand" "=Z,wa,wa,wa,v, v,wZ,Q,Y,????r,????r,????r,r")

66642

+ (match_operand:TI 1 "input_operand" "wa, Z,wa, O,W,wZ, v,r,r, Q, Y, r,n"))]

66643

+ "! TARGET_POWERPC64 && VECTOR_MEM_VSX_P (TImode)

66644

+ && (register_operand (operands[0], TImode)

66645

+ || register_operand (operands[1], TImode))"

66646

+{

66647

switch (which_alternative)

66648

{

66649

case 0:

66650

@@ -290,27 +623,45 @@

66651

return "xxlor %x0,%x1,%x1";

66652

66653

case 3:

66654

+ return "xxlxor %x0,%x0,%x0";

66655

+

66656

case 4:

66657

+ return output_vec_const_move (operands);

66658

+

66659

case 5:

66660

- return "#";

66661

+ return "stvx %1,%y0";

66662

66663

case 6:

66664

- return "xxlxor %x0,%x0,%x0";

66665

+ return "lvx %0,%y1";

66666

66667

case 7:

66668

- return output_vec_const_move (operands);

66669

+ if (TARGET_STRING)

66670

+ return \"stswi %1,%P0,16\";

66671

66672

case 8:

66673

- return "stvx %1,%y0";

66674

+ return \"#\";

66675

66676

case 9:

66677

- return "lvx %0,%y1";

66678

+ /* If the address is not used in the output, we can use lsi. Otherwise,

66679

+ fall through to generating four loads. */

66680

+ if (TARGET_STRING

66681

+ && ! reg_overlap_mentioned_p (operands[0], operands[1]))

66682

+ return \"lswi %0,%P1,16\";

66683

+ /* ... fall through ... */

66684

66685

+ case 10:

66686

+ case 11:

66687

+ case 12:

66688

+ return \"#\";

66689

default:

66690

gcc_unreachable ();

66691

}

66692

}

66693

- [(set_attr "type" "vecstore,vecload,vecsimple,*,*,*,vecsimple,*,vecstore,vecload")])

66694

+ [(set_attr "type" "vecstore,vecload,vecsimple,vecsimple,vecsimple,vecstore,vecload,store_ux,store_ux,load_ux,load_ux, *, *")

66695

+ (set_attr "length" " 4, 4, 4, 4, 8, 4, 4, 16, 16, 16, 16,16,16")

66696

+ (set (attr "cell_micro") (if_then_else (match_test "TARGET_STRING")

66697

+ (const_string "always")

66698

+ (const_string "conditional")))])

66699

66700

;; Explicit load/store expanders for the builtin functions

66701

(define_expand "vsx_load_<mode>"

66702

@@ -320,46 +671,48 @@

66703

"")

66704

66705

(define_expand "vsx_store_<mode>"

66706

- [(set (match_operand:VEC_M 0 "memory_operand" "")

66707

- (match_operand:VEC_M 1 "vsx_register_operand" ""))]

66708

+ [(set (match_operand:VSX_M 0 "memory_operand" "")

66709

+ (match_operand:VSX_M 1 "vsx_register_operand" ""))]

66710

"VECTOR_MEM_VSX_P (<MODE>mode)"

66711

"")

66712

66713

66714

-;; VSX scalar and vector floating point arithmetic instructions

66715

+;; VSX vector floating point arithmetic instructions. The VSX scalar

66716

+;; instructions are now combined with the insn for the traditional floating

66717

+;; point unit.

66718

(define_insn "*vsx_add<mode>3"

66719

- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")

66720

- (plus:VSX_B (match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")

66721

- (match_operand:VSX_B 2 "vsx_register_operand" "<VSr>,wa")))]

66722

+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")

66723

+ (plus:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")

66724

+ (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))]

66725

"VECTOR_UNIT_VSX_P (<MODE>mode)"

66726

- "x<VSv>add<VSs> %x0,%x1,%x2"

66727

+ "xvadd<VSs> %x0,%x1,%x2"

66728

[(set_attr "type" "<VStype_simple>")

66729

(set_attr "fp_type" "<VSfptype_simple>")])

66730

66731

(define_insn "*vsx_sub<mode>3"

66732

- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")

66733

- (minus:VSX_B (match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")

66734

- (match_operand:VSX_B 2 "vsx_register_operand" "<VSr>,wa")))]

66735

+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")

66736

+ (minus:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")

66737

+ (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))]

66738

"VECTOR_UNIT_VSX_P (<MODE>mode)"

66739

- "x<VSv>sub<VSs> %x0,%x1,%x2"

66740

+ "xvsub<VSs> %x0,%x1,%x2"

66741

[(set_attr "type" "<VStype_simple>")

66742

(set_attr "fp_type" "<VSfptype_simple>")])

66743

66744

(define_insn "*vsx_mul<mode>3"

66745

- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")

66746

- (mult:VSX_B (match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")

66747

- (match_operand:VSX_B 2 "vsx_register_operand" "<VSr>,wa")))]

66748

+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")

66749

+ (mult:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")

66750

+ (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))]

66751

"VECTOR_UNIT_VSX_P (<MODE>mode)"

66752

- "x<VSv>mul<VSs> %x0,%x1,%x2"

66753

- [(set_attr "type" "<VStype_mul>")

66754

+ "xvmul<VSs> %x0,%x1,%x2"

66755

+ [(set_attr "type" "<VStype_simple>")

66756

(set_attr "fp_type" "<VSfptype_mul>")])

66757

66758

(define_insn "*vsx_div<mode>3"

66759

- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")

66760

- (div:VSX_B (match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")

66761

- (match_operand:VSX_B 2 "vsx_register_operand" "<VSr>,wa")))]

66762

+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")

66763

+ (div:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")

66764

+ (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))]

66765

"VECTOR_UNIT_VSX_P (<MODE>mode)"

66766

- "x<VSv>div<VSs> %x0,%x1,%x2"

66767

+ "xvdiv<VSs> %x0,%x1,%x2"

66768

[(set_attr "type" "<VStype_div>")

66769

(set_attr "fp_type" "<VSfptype_div>")])

66770

66771

@@ -402,94 +755,72 @@

66772

(set_attr "fp_type" "<VSfptype_simple>")])

66773

66774

(define_insn "vsx_fre<mode>2"

66775

- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")

66776

- (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")]

66777

+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")

66778

+ (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")]

66779

UNSPEC_FRES))]

66780

"VECTOR_UNIT_VSX_P (<MODE>mode)"

66781

- "x<VSv>re<VSs> %x0,%x1"

66782

+ "xvre<VSs> %x0,%x1"

66783

[(set_attr "type" "<VStype_simple>")

66784

(set_attr "fp_type" "<VSfptype_simple>")])

66785

66786

(define_insn "*vsx_neg<mode>2"

66787

- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")

66788

- (neg:VSX_B (match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")))]

66789

+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")

66790

+ (neg:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")))]

66791

"VECTOR_UNIT_VSX_P (<MODE>mode)"

66792

- "x<VSv>neg<VSs> %x0,%x1"

66793

+ "xvneg<VSs> %x0,%x1"

66794

[(set_attr "type" "<VStype_simple>")

66795

(set_attr "fp_type" "<VSfptype_simple>")])

66796

66797

(define_insn "*vsx_abs<mode>2"

66798

- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")

66799

- (abs:VSX_B (match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")))]

66800

+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")

66801

+ (abs:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")))]

66802

"VECTOR_UNIT_VSX_P (<MODE>mode)"

66803

- "x<VSv>abs<VSs> %x0,%x1"

66804

+ "xvabs<VSs> %x0,%x1"

66805

[(set_attr "type" "<VStype_simple>")

66806

(set_attr "fp_type" "<VSfptype_simple>")])

66807

66808

(define_insn "vsx_nabs<mode>2"

66809

- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")

66810

- (neg:VSX_B

66811

- (abs:VSX_B

66812

- (match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa"))))]

66813

+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")

66814

+ (neg:VSX_F

66815

+ (abs:VSX_F

66816

+ (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa"))))]

66817

"VECTOR_UNIT_VSX_P (<MODE>mode)"

66818

- "x<VSv>nabs<VSs> %x0,%x1"

66819

+ "xvnabs<VSs> %x0,%x1"

66820

[(set_attr "type" "<VStype_simple>")

66821

(set_attr "fp_type" "<VSfptype_simple>")])

66822

66823

(define_insn "vsx_smax<mode>3"

66824

- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")

66825

- (smax:VSX_B (match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")

66826

- (match_operand:VSX_B 2 "vsx_register_operand" "<VSr>,wa")))]

66827

+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")

66828

+ (smax:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")

66829

+ (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))]

66830

"VECTOR_UNIT_VSX_P (<MODE>mode)"

66831

- "x<VSv>max<VSs> %x0,%x1,%x2"

66832

+ "xvmax<VSs> %x0,%x1,%x2"

66833

[(set_attr "type" "<VStype_simple>")

66834

(set_attr "fp_type" "<VSfptype_simple>")])

66835

66836

(define_insn "*vsx_smin<mode>3"

66837

- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")

66838

- (smin:VSX_B (match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")

66839

- (match_operand:VSX_B 2 "vsx_register_operand" "<VSr>,wa")))]

66840

+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")

66841

+ (smin:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")

66842

+ (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))]

66843

"VECTOR_UNIT_VSX_P (<MODE>mode)"

66844

- "x<VSv>min<VSs> %x0,%x1,%x2"

66845

+ "xvmin<VSs> %x0,%x1,%x2"

66846

[(set_attr "type" "<VStype_simple>")

66847

(set_attr "fp_type" "<VSfptype_simple>")])

66848

66849

-;; Special VSX version of smin/smax for single precision floating point. Since

66850

-;; both numbers are rounded to single precision, we can just use the DP version

66851

-;; of the instruction.

66852

-

66853

-(define_insn "*vsx_smaxsf3"

66854

- [(set (match_operand:SF 0 "vsx_register_operand" "=f")

66855

- (smax:SF (match_operand:SF 1 "vsx_register_operand" "f")

66856

- (match_operand:SF 2 "vsx_register_operand" "f")))]

66857

- "VECTOR_UNIT_VSX_P (DFmode)"

66858

- "xsmaxdp %x0,%x1,%x2"

66859

- [(set_attr "type" "fp")

66860

- (set_attr "fp_type" "fp_addsub_d")])

66861

-

66862

-(define_insn "*vsx_sminsf3"

66863

- [(set (match_operand:SF 0 "vsx_register_operand" "=f")

66864

- (smin:SF (match_operand:SF 1 "vsx_register_operand" "f")

66865

- (match_operand:SF 2 "vsx_register_operand" "f")))]

66866

- "VECTOR_UNIT_VSX_P (DFmode)"

66867

- "xsmindp %x0,%x1,%x2"

66868

- [(set_attr "type" "fp")

66869

- (set_attr "fp_type" "fp_addsub_d")])

66870

-

66871

(define_insn "*vsx_sqrt<mode>2"

66872

- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")

66873

- (sqrt:VSX_B (match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")))]

66874

+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")

66875

+ (sqrt:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")))]

66876

"VECTOR_UNIT_VSX_P (<MODE>mode)"

66877

- "x<VSv>sqrt<VSs> %x0,%x1"

66878

+ "xvsqrt<VSs> %x0,%x1"

66879

[(set_attr "type" "<VStype_sqrt>")

66880

(set_attr "fp_type" "<VSfptype_sqrt>")])

66881

66882

(define_insn "*vsx_rsqrte<mode>2"

66883

- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")

66884

- (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")]

66885

+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")

66886

+ (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")]

66887

UNSPEC_RSQRT))]

66888

"VECTOR_UNIT_VSX_P (<MODE>mode)"

66889

- "x<VSv>rsqrte<VSs> %x0,%x1"

66890

+ "xvrsqrte<VSs> %x0,%x1"

66891

[(set_attr "type" "<VStype_simple>")

66892

(set_attr "fp_type" "<VSfptype_simple>")])

66893

66894

@@ -528,27 +859,11 @@

66895

[(set_attr "type" "<VStype_simple>")

66896

(set_attr "fp_type" "<VSfptype_simple>")])

66897

66898

-;; Fused vector multiply/add instructions Support the classical DF versions of

66899

-;; fma, which allows the target to be a separate register from the 3 inputs.

66900

-;; Under VSX, the target must be either the addend or the first multiply.

66901

-;; Where we can, also do the same for the Altivec V4SF fmas.

66902

+;; Fused vector multiply/add instructions. Support the classical Altivec

66903

+;; versions of fma, which allows the target to be a separate register from the

66904

+;; 3 inputs. Under VSX, the target must be either the addend or the first

66905

+;; multiply.

66906

66907

-(define_insn "*vsx_fmadf4"

66908

- [(set (match_operand:DF 0 "vsx_register_operand" "=ws,ws,?wa,?wa,d")

66909

- (fma:DF

66910

- (match_operand:DF 1 "vsx_register_operand" "%ws,ws,wa,wa,d")

66911

- (match_operand:DF 2 "vsx_register_operand" "ws,0,wa,0,d")

66912

- (match_operand:DF 3 "vsx_register_operand" "0,ws,0,wa,d")))]

66913

- "VECTOR_UNIT_VSX_P (DFmode)"

66914

- "@

66915

- xsmaddadp %x0,%x1,%x2

66916

- xsmaddmdp %x0,%x1,%x3

66917

- xsmaddadp %x0,%x1,%x2

66918

- xsmaddmdp %x0,%x1,%x3

66919

- fmadd %0,%1,%2,%3"

66920

- [(set_attr "type" "fp")

66921

- (set_attr "fp_type" "fp_maddsub_d")])

66922

-

66923

(define_insn "*vsx_fmav4sf4"

66924

[(set (match_operand:V4SF 0 "vsx_register_operand" "=ws,ws,?wa,?wa,v")

66925

(fma:V4SF

66926

@@ -578,23 +893,6 @@

66927

xvmaddmdp %x0,%x1,%x3"

66928

[(set_attr "type" "vecdouble")])

66929

66930

-(define_insn "*vsx_fmsdf4"

66931

- [(set (match_operand:DF 0 "vsx_register_operand" "=ws,ws,?wa,?wa,d")

66932

- (fma:DF

66933

- (match_operand:DF 1 "vsx_register_operand" "%ws,ws,wa,wa,d")

66934

- (match_operand:DF 2 "vsx_register_operand" "ws,0,wa,0,d")

66935

- (neg:DF

66936

- (match_operand:DF 3 "vsx_register_operand" "0,ws,0,wa,d"))))]

66937

- "VECTOR_UNIT_VSX_P (DFmode)"

66938

- "@

66939

- xsmsubadp %x0,%x1,%x2

66940

- xsmsubmdp %x0,%x1,%x3

66941

- xsmsubadp %x0,%x1,%x2

66942

- xsmsubmdp %x0,%x1,%x3

66943

- fmsub %0,%1,%2,%3"

66944

- [(set_attr "type" "fp")

66945

- (set_attr "fp_type" "fp_maddsub_d")])

66946

-

66947

(define_insn "*vsx_fms<mode>4"

66948

[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,<VSr>,?wa,?wa")

66949

(fma:VSX_F

66950

@@ -604,29 +902,12 @@

66951

(match_operand:VSX_F 3 "vsx_register_operand" "0,<VSr>,0,wa"))))]

66952

"VECTOR_UNIT_VSX_P (<MODE>mode)"

66953

"@

66954

- x<VSv>msuba<VSs> %x0,%x1,%x2

66955

- x<VSv>msubm<VSs> %x0,%x1,%x3

66956

- x<VSv>msuba<VSs> %x0,%x1,%x2

66957

- x<VSv>msubm<VSs> %x0,%x1,%x3"

66958

+ xvmsuba<VSs> %x0,%x1,%x2

66959

+ xvmsubm<VSs> %x0,%x1,%x3

66960

+ xvmsuba<VSs> %x0,%x1,%x2

66961

+ xvmsubm<VSs> %x0,%x1,%x3"

66962

[(set_attr "type" "<VStype_mul>")])

66963

66964

-(define_insn "*vsx_nfmadf4"

66965

- [(set (match_operand:DF 0 "vsx_register_operand" "=ws,ws,?wa,?wa,d")

66966

- (neg:DF

66967

- (fma:DF

66968

- (match_operand:DF 1 "vsx_register_operand" "ws,ws,wa,wa,d")

66969

- (match_operand:DF 2 "vsx_register_operand" "ws,0,wa,0,d")

66970

- (match_operand:DF 3 "vsx_register_operand" "0,ws,0,wa,d"))))]

66971

- "VECTOR_UNIT_VSX_P (DFmode)"

66972

- "@

66973

- xsnmaddadp %x0,%x1,%x2

66974

- xsnmaddmdp %x0,%x1,%x3

66975

- xsnmaddadp %x0,%x1,%x2

66976

- xsnmaddmdp %x0,%x1,%x3

66977

- fnmadd %0,%1,%2,%3"

66978

- [(set_attr "type" "fp")

66979

- (set_attr "fp_type" "fp_maddsub_d")])

66980

-

66981

(define_insn "*vsx_nfma<mode>4"

66982

[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,<VSr>,?wa,?wa")

66983

(neg:VSX_F

66984

@@ -636,31 +917,13 @@

66985

(match_operand:VSX_F 3 "vsx_register_operand" "0,<VSr>,0,wa"))))]

66986

"VECTOR_UNIT_VSX_P (<MODE>mode)"

66987

"@

66988

- x<VSv>nmadda<VSs> %x0,%x1,%x2

66989

- x<VSv>nmaddm<VSs> %x0,%x1,%x3

66990

- x<VSv>nmadda<VSs> %x0,%x1,%x2

66991

- x<VSv>nmaddm<VSs> %x0,%x1,%x3"

66992

+ xvnmadda<VSs> %x0,%x1,%x2

66993

+ xvnmaddm<VSs> %x0,%x1,%x3

66994

+ xvnmadda<VSs> %x0,%x1,%x2

66995

+ xvnmaddm<VSs> %x0,%x1,%x3"

66996

[(set_attr "type" "<VStype_mul>")

66997

(set_attr "fp_type" "<VSfptype_mul>")])

66998

66999

-(define_insn "*vsx_nfmsdf4"

67000

- [(set (match_operand:DF 0 "vsx_register_operand" "=ws,ws,?wa,?wa,d")

67001

- (neg:DF

67002

- (fma:DF

67003

- (match_operand:DF 1 "vsx_register_operand" "%ws,ws,wa,wa,d")

67004

- (match_operand:DF 2 "vsx_register_operand" "ws,0,wa,0,d")

67005

- (neg:DF

67006

- (match_operand:DF 3 "vsx_register_operand" "0,ws,0,wa,d")))))]

67007

- "VECTOR_UNIT_VSX_P (DFmode)"

67008

- "@

67009

- xsnmsubadp %x0,%x1,%x2

67010

- xsnmsubmdp %x0,%x1,%x3

67011

- xsnmsubadp %x0,%x1,%x2

67012

- xsnmsubmdp %x0,%x1,%x3

67013

- fnmsub %0,%1,%2,%3"

67014

- [(set_attr "type" "fp")

67015

- (set_attr "fp_type" "fp_maddsub_d")])

67016

-

67017

(define_insn "*vsx_nfmsv4sf4"

67018

[(set (match_operand:V4SF 0 "vsx_register_operand" "=wf,wf,?wa,?wa,v")

67019

(neg:V4SF

67020

@@ -722,16 +985,6 @@

67021

[(set_attr "type" "<VStype_simple>")

67022

(set_attr "fp_type" "<VSfptype_simple>")])

67023

67024

-;; Floating point scalar compare

67025

-(define_insn "*vsx_cmpdf_internal1"

67026

- [(set (match_operand:CCFP 0 "cc_reg_operand" "=y,?y")

67027

- (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "ws,wa")

67028

- (match_operand:DF 2 "gpc_reg_operand" "ws,wa")))]

67029

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT

67030

- && VECTOR_UNIT_VSX_P (DFmode)"

67031

- "xscmpudp %0,%x1,%x2"

67032

- [(set_attr "type" "fpcompare")])

67033

-

67034

;; Compare vectors producing a vector result and a predicate, setting CR6 to

67035

;; indicate a combined status

67036

(define_insn "*vsx_eq_<mode>_p"

67037

@@ -798,13 +1051,13 @@

67038

67039

;; Copy sign

67040

(define_insn "vsx_copysign<mode>3"

67041

- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")

67042

- (unspec:VSX_B

67043

- [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")

67044

- (match_operand:VSX_B 2 "vsx_register_operand" "<VSr>,wa")]

67045

+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")

67046

+ (unspec:VSX_F

67047

+ [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")

67048

+ (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")]

67049

UNSPEC_COPYSIGN))]

67050

"VECTOR_UNIT_VSX_P (<MODE>mode)"

67051

- "x<VSv>cpsgn<VSs> %x0,%x2,%x1"

67052

+ "xvcpsgn<VSs> %x0,%x2,%x1"

67053

[(set_attr "type" "<VStype_simple>")

67054

(set_attr "fp_type" "<VSfptype_simple>")])

67055

67056

@@ -865,10 +1118,10 @@

67057

(set_attr "fp_type" "<VSfptype_simple>")])

67058

67059

(define_insn "vsx_btrunc<mode>2"

67060

- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")

67061

- (fix:VSX_B (match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")))]

67062

+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")

67063

+ (fix:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")))]

67064

"VECTOR_UNIT_VSX_P (<MODE>mode)"

67065

- "x<VSv>r<VSs>iz %x0,%x1"

67066

+ "xvr<VSs>iz %x0,%x1"

67067

[(set_attr "type" "<VStype_simple>")

67068

(set_attr "fp_type" "<VSfptype_simple>")])

67069

67070

@@ -882,20 +1135,20 @@

67071

(set_attr "fp_type" "<VSfptype_simple>")])

67072

67073

(define_insn "vsx_floor<mode>2"

67074

- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")

67075

- (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")]

67076

+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")

67077

+ (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")]

67078

UNSPEC_FRIM))]

67079

"VECTOR_UNIT_VSX_P (<MODE>mode)"

67080

- "x<VSv>r<VSs>im %x0,%x1"

67081

+ "xvr<VSs>im %x0,%x1"

67082

[(set_attr "type" "<VStype_simple>")

67083

(set_attr "fp_type" "<VSfptype_simple>")])

67084

67085

(define_insn "vsx_ceil<mode>2"

67086

- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")

67087

- (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")]

67088

+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")

67089

+ (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")]

67090

UNSPEC_FRIP))]

67091

"VECTOR_UNIT_VSX_P (<MODE>mode)"

67092

- "x<VSv>r<VSs>ip %x0,%x1"

67093

+ "xvr<VSs>ip %x0,%x1"

67094

[(set_attr "type" "<VStype_simple>")

67095

(set_attr "fp_type" "<VSfptype_simple>")])

67096

67097

@@ -942,6 +1195,40 @@

67098

"xscvspdp %x0,%x1"

67099

[(set_attr "type" "fp")])

67100

67101

+;; ISA 2.07 xscvdpspn/xscvspdpn that does not raise an error on signalling NaNs

67102

+(define_insn "vsx_xscvdpspn"

67103

+ [(set (match_operand:V4SF 0 "vsx_register_operand" "=ws,?wa")

67104

+ (unspec:V4SF [(match_operand:DF 1 "vsx_register_operand" "wd,wa")]

67105

+ UNSPEC_VSX_CVDPSPN))]

67106

+ "TARGET_XSCVDPSPN"

67107

+ "xscvdpspn %x0,%x1"

67108

+ [(set_attr "type" "fp")])

67109

+

67110

+(define_insn "vsx_xscvspdpn"

67111

+ [(set (match_operand:DF 0 "vsx_register_operand" "=ws,?wa")

67112

+ (unspec:DF [(match_operand:V4SF 1 "vsx_register_operand" "wa,wa")]

67113

+ UNSPEC_VSX_CVSPDPN))]

67114

+ "TARGET_XSCVSPDPN"

67115

+ "xscvspdpn %x0,%x1"

67116

+ [(set_attr "type" "fp")])

67117

+

67118

+(define_insn "vsx_xscvdpspn_scalar"

67119

+ [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa")

67120

+ (unspec:V4SF [(match_operand:SF 1 "vsx_register_operand" "f")]

67121

+ UNSPEC_VSX_CVDPSPN))]

67122

+ "TARGET_XSCVDPSPN"

67123

+ "xscvdpspn %x0,%x1"

67124

+ [(set_attr "type" "fp")])

67125

+

67126

+;; Used by direct move to move a SFmode value from GPR to VSX register

67127

+(define_insn "vsx_xscvspdpn_directmove"

67128

+ [(set (match_operand:SF 0 "vsx_register_operand" "=wa")

67129

+ (unspec:SF [(match_operand:SF 1 "vsx_register_operand" "wa")]

67130

+ UNSPEC_VSX_CVSPDPN))]

67131

+ "TARGET_XSCVSPDPN"

67132

+ "xscvspdpn %x0,%x1"

67133

+ [(set_attr "type" "fp")])

67134

+

67135

;; Convert from 64-bit to 32-bit types

67136

;; Note, favor the Altivec registers since the usual use of these instructions

67137

;; is in vector converts and we need to use the Altivec vperm instruction.

67138

@@ -1027,73 +1314,21 @@

67139

(set_attr "fp_type" "<VSfptype_simple>")])

67140

67141

67142

-;; Logical and permute operations

67143

-(define_insn "*vsx_and<mode>3"

67144

- [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?wa")

67145

- (and:VSX_L

67146

- (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,?wa")

67147

- (match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,?wa")))]

67148

- "VECTOR_MEM_VSX_P (<MODE>mode)"

67149

- "xxland %x0,%x1,%x2"

67150

- [(set_attr "type" "vecsimple")])

67151

-

67152

-(define_insn "*vsx_ior<mode>3"

67153

- [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?wa")

67154

- (ior:VSX_L (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,?wa")

67155

- (match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,?wa")))]

67156

- "VECTOR_MEM_VSX_P (<MODE>mode)"

67157

- "xxlor %x0,%x1,%x2"

67158

- [(set_attr "type" "vecsimple")])

67159

-

67160

-(define_insn "*vsx_xor<mode>3"

67161

- [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?wa")

67162

- (xor:VSX_L

67163

- (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,?wa")

67164

- (match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,?wa")))]

67165

- "VECTOR_MEM_VSX_P (<MODE>mode)"

67166

- "xxlxor %x0,%x1,%x2"

67167

- [(set_attr "type" "vecsimple")])

67168

-

67169

-(define_insn "*vsx_one_cmpl<mode>2"

67170

- [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?wa")

67171

- (not:VSX_L

67172

- (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,?wa")))]

67173

- "VECTOR_MEM_VSX_P (<MODE>mode)"

67174

- "xxlnor %x0,%x1,%x1"

67175

- [(set_attr "type" "vecsimple")])

67176

-

67177

-(define_insn "*vsx_nor<mode>3"

67178

- [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?wa")

67179

- (not:VSX_L

67180

- (ior:VSX_L

67181

- (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,?wa")

67182

- (match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,?wa"))))]

67183

- "VECTOR_MEM_VSX_P (<MODE>mode)"

67184

- "xxlnor %x0,%x1,%x2"

67185

- [(set_attr "type" "vecsimple")])

67186

-

67187

-(define_insn "*vsx_andc<mode>3"

67188

- [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?wa")

67189

- (and:VSX_L

67190

- (not:VSX_L

67191

- (match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,?wa"))

67192

- (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,?wa")))]

67193

- "VECTOR_MEM_VSX_P (<MODE>mode)"

67194

- "xxlandc %x0,%x1,%x2"

67195

- [(set_attr "type" "vecsimple")])

67196

-

67197

-

67198

;; Permute operations

67199

67200

;; Build a V2DF/V2DI vector from two scalars

67201

(define_insn "vsx_concat_<mode>"

67202

- [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wd,?wa")

67203

- (unspec:VSX_D

67204

- [(match_operand:<VS_scalar> 1 "vsx_register_operand" "ws,wa")

67205

- (match_operand:<VS_scalar> 2 "vsx_register_operand" "ws,wa")]

67206

- UNSPEC_VSX_CONCAT))]

67207

+ [(set (match_operand:VSX_D 0 "vsx_register_operand" "=<VSr>,?wa")

67208

+ (vec_concat:VSX_D

67209

+ (match_operand:<VS_scalar> 1 "vsx_register_operand" "ws,wa")

67210

+ (match_operand:<VS_scalar> 2 "vsx_register_operand" "ws,wa")))]

67211

"VECTOR_MEM_VSX_P (<MODE>mode)"

67212

- "xxpermdi %x0,%x1,%x2,0"

67213

+{

67214

+ if (BYTES_BIG_ENDIAN)

67215

+ return "xxpermdi %x0,%x1,%x2,0";

67216

+ else

67217

+ return "xxpermdi %x0,%x2,%x1,0";

67218

+}

67219

[(set_attr "type" "vecperm")])

67220

67221

;; Special purpose concat using xxpermdi to glue two single precision values

67222

@@ -1106,9 +1341,176 @@

67223

(match_operand:SF 2 "vsx_register_operand" "f,f")]

67224

UNSPEC_VSX_CONCAT))]

67225

"VECTOR_MEM_VSX_P (V2DFmode)"

67226

- "xxpermdi %x0,%x1,%x2,0"

67227

+{

67228

+ if (BYTES_BIG_ENDIAN)

67229

+ return "xxpermdi %x0,%x1,%x2,0";

67230

+ else

67231

+ return "xxpermdi %x0,%x2,%x1,0";

67232

+}

67233

[(set_attr "type" "vecperm")])

67234

67235

+;; xxpermdi for little endian loads and stores. We need several of

67236

+;; these since the form of the PARALLEL differs by mode.

67237

+(define_insn "*vsx_xxpermdi2_le_<mode>"

67238

+ [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wa")

67239

+ (vec_select:VSX_D

67240

+ (match_operand:VSX_D 1 "vsx_register_operand" "wa")

67241

+ (parallel [(const_int 1) (const_int 0)])))]

67242

+ "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode)"

67243

+ "xxpermdi %x0,%x1,%x1,2"

67244

+ [(set_attr "type" "vecperm")])

67245

+

67246

+(define_insn "*vsx_xxpermdi4_le_<mode>"

67247

+ [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa")

67248

+ (vec_select:VSX_W

67249

+ (match_operand:VSX_W 1 "vsx_register_operand" "wa")

67250

+ (parallel [(const_int 2) (const_int 3)

67251

+ (const_int 0) (const_int 1)])))]

67252

+ "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode)"

67253

+ "xxpermdi %x0,%x1,%x1,2"

67254

+ [(set_attr "type" "vecperm")])

67255

+

67256

+(define_insn "*vsx_xxpermdi8_le_V8HI"

67257

+ [(set (match_operand:V8HI 0 "vsx_register_operand" "=wa")

67258

+ (vec_select:V8HI

67259

+ (match_operand:V8HI 1 "vsx_register_operand" "wa")

67260

+ (parallel [(const_int 4) (const_int 5)

67261

+ (const_int 6) (const_int 7)

67262

+ (const_int 0) (const_int 1)

67263

+ (const_int 2) (const_int 3)])))]

67264

+ "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (V8HImode)"

67265

+ "xxpermdi %x0,%x1,%x1,2"

67266

+ [(set_attr "type" "vecperm")])

67267

+

67268

+(define_insn "*vsx_xxpermdi16_le_V16QI"

67269

+ [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa")

67270

+ (vec_select:V16QI

67271

+ (match_operand:V16QI 1 "vsx_register_operand" "wa")

67272

+ (parallel [(const_int 8) (const_int 9)

67273

+ (const_int 10) (const_int 11)

67274

+ (const_int 12) (const_int 13)

67275

+ (const_int 14) (const_int 15)

67276

+ (const_int 0) (const_int 1)

67277

+ (const_int 2) (const_int 3)

67278

+ (const_int 4) (const_int 5)

67279

+ (const_int 6) (const_int 7)])))]

67280

+ "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (V16QImode)"

67281

+ "xxpermdi %x0,%x1,%x1,2"

67282

+ [(set_attr "type" "vecperm")])

67283

+

67284

+;; lxvd2x for little endian loads. We need several of

67285

+;; these since the form of the PARALLEL differs by mode.

67286

+(define_insn "*vsx_lxvd2x2_le_<mode>"

67287

+ [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wa")

67288

+ (vec_select:VSX_D

67289

+ (match_operand:VSX_D 1 "memory_operand" "Z")

67290

+ (parallel [(const_int 1) (const_int 0)])))]

67291

+ "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode)"

67292

+ "lxvd2x %x0,%y1"

67293

+ [(set_attr "type" "vecload")])

67294

+

67295

+(define_insn "*vsx_lxvd2x4_le_<mode>"

67296

+ [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa")

67297

+ (vec_select:VSX_W

67298

+ (match_operand:VSX_W 1 "memory_operand" "Z")

67299

+ (parallel [(const_int 2) (const_int 3)

67300

+ (const_int 0) (const_int 1)])))]

67301

+ "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode)"

67302

+ "lxvd2x %x0,%y1"

67303

+ [(set_attr "type" "vecload")])

67304

+

67305

+(define_insn "*vsx_lxvd2x8_le_V8HI"

67306

+ [(set (match_operand:V8HI 0 "vsx_register_operand" "=wa")

67307

+ (vec_select:V8HI

67308

+ (match_operand:V8HI 1 "memory_operand" "Z")

67309

+ (parallel [(const_int 4) (const_int 5)

67310

+ (const_int 6) (const_int 7)

67311

+ (const_int 0) (const_int 1)

67312

+ (const_int 2) (const_int 3)])))]

67313

+ "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (V8HImode)"

67314

+ "lxvd2x %x0,%y1"

67315

+ [(set_attr "type" "vecload")])

67316

+

67317

+(define_insn "*vsx_lxvd2x16_le_V16QI"

67318

+ [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa")

67319

+ (vec_select:V16QI

67320

+ (match_operand:V16QI 1 "memory_operand" "Z")

67321

+ (parallel [(const_int 8) (const_int 9)

67322

+ (const_int 10) (const_int 11)

67323

+ (const_int 12) (const_int 13)

67324

+ (const_int 14) (const_int 15)

67325

+ (const_int 0) (const_int 1)

67326

+ (const_int 2) (const_int 3)

67327

+ (const_int 4) (const_int 5)

67328

+ (const_int 6) (const_int 7)])))]

67329

+ "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (V16QImode)"

67330

+ "lxvd2x %x0,%y1"

67331

+ [(set_attr "type" "vecload")])

67332

+

67333

+;; stxvd2x for little endian stores. We need several of

67334

+;; these since the form of the PARALLEL differs by mode.

67335

+(define_insn "*vsx_stxvd2x2_le_<mode>"

67336

+ [(set (match_operand:VSX_D 0 "memory_operand" "=Z")

67337

+ (vec_select:VSX_D

67338

+ (match_operand:VSX_D 1 "vsx_register_operand" "wa")

67339

+ (parallel [(const_int 1) (const_int 0)])))]

67340

+ "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode)"

67341

+ "stxvd2x %x1,%y0"

67342

+ [(set_attr "type" "vecstore")])

67343

+

67344

+(define_insn "*vsx_stxvd2x4_le_<mode>"

67345

+ [(set (match_operand:VSX_W 0 "memory_operand" "=Z")

67346

+ (vec_select:VSX_W

67347

+ (match_operand:VSX_W 1 "vsx_register_operand" "wa")

67348

+ (parallel [(const_int 2) (const_int 3)

67349

+ (const_int 0) (const_int 1)])))]

67350

+ "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode)"

67351

+ "stxvd2x %x1,%y0"

67352

+ [(set_attr "type" "vecstore")])

67353

+

67354

+(define_insn "*vsx_stxvd2x8_le_V8HI"

67355

+ [(set (match_operand:V8HI 0 "memory_operand" "=Z")

67356

+ (vec_select:V8HI

67357

+ (match_operand:V8HI 1 "vsx_register_operand" "wa")

67358

+ (parallel [(const_int 4) (const_int 5)

67359

+ (const_int 6) (const_int 7)

67360

+ (const_int 0) (const_int 1)

67361

+ (const_int 2) (const_int 3)])))]

67362

+ "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (V8HImode)"

67363

+ "stxvd2x %x1,%y0"

67364

+ [(set_attr "type" "vecstore")])

67365

+

67366

+(define_insn "*vsx_stxvd2x16_le_V16QI"

67367

+ [(set (match_operand:V16QI 0 "memory_operand" "=Z")

67368

+ (vec_select:V16QI

67369

+ (match_operand:V16QI 1 "vsx_register_operand" "wa")

67370

+ (parallel [(const_int 8) (const_int 9)

67371

+ (const_int 10) (const_int 11)

67372

+ (const_int 12) (const_int 13)

67373

+ (const_int 14) (const_int 15)

67374

+ (const_int 0) (const_int 1)

67375

+ (const_int 2) (const_int 3)

67376

+ (const_int 4) (const_int 5)

67377

+ (const_int 6) (const_int 7)])))]

67378

+ "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (V16QImode)"

67379

+ "stxvd2x %x1,%y0"

67380

+ [(set_attr "type" "vecstore")])

67381

+

67382

+;; Convert a TImode value into V1TImode

67383

+(define_expand "vsx_set_v1ti"

67384

+ [(match_operand:V1TI 0 "nonimmediate_operand" "")

67385

+ (match_operand:V1TI 1 "nonimmediate_operand" "")

67386

+ (match_operand:TI 2 "input_operand" "")

67387

+ (match_operand:QI 3 "u5bit_cint_operand" "")]

67388

+ "VECTOR_MEM_VSX_P (V1TImode)"

67389

+{

67390

+ if (operands[3] != const0_rtx)

67391

+ gcc_unreachable ();

67392

+

67393

+ emit_move_insn (operands[0], gen_lowpart (V1TImode, operands[1]));

67394

+ DONE;

67395

+})

67396

+

67397

;; Set the element of a V2DI/VD2F mode

67398

(define_insn "vsx_set_<mode>"

67399

[(set (match_operand:VSX_D 0 "vsx_register_operand" "=wd,?wa")

67400

@@ -1118,9 +1520,10 @@

67401

UNSPEC_VSX_SET))]

67402

"VECTOR_MEM_VSX_P (<MODE>mode)"

67403

{

67404

- if (INTVAL (operands[3]) == 0)

67405

+ int idx_first = BYTES_BIG_ENDIAN ? 0 : 1;

67406

+ if (INTVAL (operands[3]) == idx_first)

67407

return \"xxpermdi %x0,%x2,%x1,1\";

67408

- else if (INTVAL (operands[3]) == 1)

67409

+ else if (INTVAL (operands[3]) == 1 - idx_first)

67410

return \"xxpermdi %x0,%x1,%x2,0\";

67411

else

67412

gcc_unreachable ();

67413

@@ -1135,8 +1538,12 @@

67414

[(match_operand:QI 2 "u5bit_cint_operand" "i,i,i")])))]

67415

"VECTOR_MEM_VSX_P (<MODE>mode)"

67416

{

67417

+ int fldDM;

67418

gcc_assert (UINTVAL (operands[2]) <= 1);

67419

- operands[3] = GEN_INT (INTVAL (operands[2]) << 1);

67420

+ fldDM = INTVAL (operands[2]) << 1;

67421

+ if (!BYTES_BIG_ENDIAN)

67422

+ fldDM = 3 - fldDM;

67423

+ operands[3] = GEN_INT (fldDM);

67424

return \"xxpermdi %x0,%x1,%x1,%3\";

67425

}

67426

[(set_attr "type" "vecperm")])

67427

@@ -1149,9 +1556,28 @@

67428

(parallel [(const_int 0)])))]

67429

"VECTOR_MEM_VSX_P (<MODE>mode) && WORDS_BIG_ENDIAN"

67430

"lxsd%U1x %x0,%y1"

67431

- [(set_attr "type" "fpload")

67432

+ [(set (attr "type")

67433

+ (if_then_else

67434

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

67435

+ (const_string "fpload_ux")

67436

+ (const_string "fpload")))

67437

(set_attr "length" "4")])

67438

67439

+;; Optimize extracting element 1 from memory for little endian

67440

+(define_insn "*vsx_extract_<mode>_one_le"

67441

+ [(set (match_operand:<VS_scalar> 0 "vsx_register_operand" "=ws,d,?wa")

67442

+ (vec_select:<VS_scalar>

67443

+ (match_operand:VSX_D 1 "indexed_or_indirect_operand" "Z,Z,Z")

67444

+ (parallel [(const_int 1)])))]

67445

+ "VECTOR_MEM_VSX_P (<MODE>mode) && !WORDS_BIG_ENDIAN"

67446

+ "lxsd%U1x %x0,%y1"

67447

+ [(set (attr "type")

67448

+ (if_then_else

67449

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

67450

+ (const_string "fpload_ux")

67451

+ (const_string "fpload")))

67452

+ (set_attr "length" "4")])

67453

+

67454

;; Extract a SF element from V4SF

67455

(define_insn_and_split "vsx_extract_v4sf"

67456

[(set (match_operand:SF 0 "vsx_register_operand" "=f,f")

67457

@@ -1172,7 +1598,7 @@

67458

rtx op2 = operands[2];

67459

rtx op3 = operands[3];

67460

rtx tmp;

67461

- HOST_WIDE_INT ele = INTVAL (op2);

67462

+ HOST_WIDE_INT ele = BYTES_BIG_ENDIAN ? INTVAL (op2) : 3 - INTVAL (op2);

67463

67464

if (ele == 0)

67465

tmp = op1;

67466

@@ -1213,11 +1639,22 @@

67467

if (<MODE>mode != V2DImode)

67468

{

67469

target = gen_lowpart (V2DImode, target);

67470

- op0 = gen_lowpart (V2DImode, target);

67471

- op1 = gen_lowpart (V2DImode, target);

67472

+ op0 = gen_lowpart (V2DImode, op0);

67473

+ op1 = gen_lowpart (V2DImode, op1);

67474

}

67475

}

67476

- emit_insn (gen (target, op0, op1, perm0, perm1));

67477

+ /* In little endian mode, vsx_xxpermdi2_<mode>_1 will perform a

67478

+ transformation we don't want; it is necessary for

67479

+ rs6000_expand_vec_perm_const_1 but not for this use. So we

67480

+ prepare for that by reversing the transformation here. */

67481

+ if (BYTES_BIG_ENDIAN)

67482

+ emit_insn (gen (target, op0, op1, perm0, perm1));

67483

+ else

67484

+ {

67485

+ rtx p0 = GEN_INT (3 - INTVAL (perm1));

67486

+ rtx p1 = GEN_INT (3 - INTVAL (perm0));

67487

+ emit_insn (gen (target, op1, op0, p0, p1));

67488

+ }

67489

DONE;

67490

})

67491

67492

@@ -1231,9 +1668,32 @@

67493

(match_operand 4 "const_2_to_3_operand" "")])))]

67494

"VECTOR_MEM_VSX_P (<MODE>mode)"

67495

{

67496

- int mask = (INTVAL (operands[3]) << 1) | (INTVAL (operands[4]) - 2);

67497

+ int op3, op4, mask;

67498

+

67499

+ /* For little endian, swap operands and invert/swap selectors

67500

+ to get the correct xxpermdi. The operand swap sets up the

67501

+ inputs as a little endian array. The selectors are swapped

67502

+ because they are defined to use big endian ordering. The

67503

+ selectors are inverted to get the correct doublewords for

67504

+ little endian ordering. */

67505

+ if (BYTES_BIG_ENDIAN)

67506

+ {

67507

+ op3 = INTVAL (operands[3]);

67508

+ op4 = INTVAL (operands[4]);

67509

+ }

67510

+ else

67511

+ {

67512

+ op3 = 3 - INTVAL (operands[4]);

67513

+ op4 = 3 - INTVAL (operands[3]);

67514

+ }

67515

+

67516

+ mask = (op3 << 1) | (op4 - 2);

67517

operands[3] = GEN_INT (mask);

67518

- return "xxpermdi %x0,%x1,%x2,%3";

67519

+

67520

+ if (BYTES_BIG_ENDIAN)

67521

+ return "xxpermdi %x0,%x1,%x2,%3";

67522

+ else

67523

+ return "xxpermdi %x0,%x2,%x1,%3";

67524

}

67525

[(set_attr "type" "vecperm")])

67526

67527

@@ -1252,25 +1712,57 @@

67528

67529

;; Expanders for builtins

67530

(define_expand "vsx_mergel_<mode>"

67531

- [(set (match_operand:VSX_D 0 "vsx_register_operand" "")

67532

- (vec_select:VSX_D

67533

- (vec_concat:<VS_double>

67534

- (match_operand:VSX_D 1 "vsx_register_operand" "")

67535

- (match_operand:VSX_D 2 "vsx_register_operand" ""))

67536

- (parallel [(const_int 1) (const_int 3)])))]

67537

+ [(use (match_operand:VSX_D 0 "vsx_register_operand" ""))

67538

+ (use (match_operand:VSX_D 1 "vsx_register_operand" ""))

67539

+ (use (match_operand:VSX_D 2 "vsx_register_operand" ""))]

67540

"VECTOR_MEM_VSX_P (<MODE>mode)"

67541

- "")

67542

+{

67543

+ rtvec v;

67544

+ rtx x;

67545

67546

+ /* Special handling for LE with -maltivec=be. */

67547

+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)

67548

+ {

67549

+ v = gen_rtvec (2, GEN_INT (0), GEN_INT (2));

67550

+ x = gen_rtx_VEC_CONCAT (<VS_double>mode, operands[2], operands[1]);

67551

+ }

67552

+ else

67553

+ {

67554

+ v = gen_rtvec (2, GEN_INT (1), GEN_INT (3));

67555

+ x = gen_rtx_VEC_CONCAT (<VS_double>mode, operands[1], operands[2]);

67556

+ }

67557

+

67558

+ x = gen_rtx_VEC_SELECT (<MODE>mode, x, gen_rtx_PARALLEL (VOIDmode, v));

67559

+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));

67560

+ DONE;

67561

+})

67562

+

67563

(define_expand "vsx_mergeh_<mode>"

67564

- [(set (match_operand:VSX_D 0 "vsx_register_operand" "")

67565

- (vec_select:VSX_D

67566

- (vec_concat:<VS_double>

67567

- (match_operand:VSX_D 1 "vsx_register_operand" "")

67568

- (match_operand:VSX_D 2 "vsx_register_operand" ""))

67569

- (parallel [(const_int 0) (const_int 2)])))]

67570

+ [(use (match_operand:VSX_D 0 "vsx_register_operand" ""))

67571

+ (use (match_operand:VSX_D 1 "vsx_register_operand" ""))

67572

+ (use (match_operand:VSX_D 2 "vsx_register_operand" ""))]

67573

"VECTOR_MEM_VSX_P (<MODE>mode)"

67574

- "")

67575

+{

67576

+ rtvec v;

67577

+ rtx x;

67578

67579

+ /* Special handling for LE with -maltivec=be. */

67580

+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)

67581

+ {

67582

+ v = gen_rtvec (2, GEN_INT (1), GEN_INT (3));

67583

+ x = gen_rtx_VEC_CONCAT (<VS_double>mode, operands[2], operands[1]);

67584

+ }

67585

+ else

67586

+ {

67587

+ v = gen_rtvec (2, GEN_INT (0), GEN_INT (2));

67588

+ x = gen_rtx_VEC_CONCAT (<VS_double>mode, operands[1], operands[2]);

67589

+ }

67590

+

67591

+ x = gen_rtx_VEC_SELECT (<MODE>mode, x, gen_rtx_PARALLEL (VOIDmode, v));

67592

+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));

67593

+ DONE;

67594

+})

67595

+

67596

;; V2DF/V2DI splat

67597

(define_insn "vsx_splat_<mode>"

67598

[(set (match_operand:VSX_D 0 "vsx_register_operand" "=wd,wd,wd,?wa,?wa,?wa")

67599

@@ -1295,6 +1787,20 @@

67600

(parallel

67601

[(match_operand:QI 2 "u5bit_cint_operand" "i,i")]))))]

67602

"VECTOR_MEM_VSX_P (<MODE>mode)"

67603

+{

67604

+ if (!BYTES_BIG_ENDIAN)

67605

+ operands[2] = GEN_INT (3 - INTVAL (operands[2]));

67606

+

67607

+ return "xxspltw %x0,%x1,%2";

67608

+}

67609

+ [(set_attr "type" "vecperm")])

67610

+

67611

+(define_insn "vsx_xxspltw_<mode>_direct"

67612

+ [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?wa")

67613

+ (unspec:VSX_W [(match_operand:VSX_W 1 "vsx_register_operand" "wf,wa")

67614

+ (match_operand:QI 2 "u5bit_cint_operand" "i,i")]

67615

+ UNSPEC_VSX_XXSPLTW))]

67616

+ "VECTOR_MEM_VSX_P (<MODE>mode)"

67617

"xxspltw %x0,%x1,%2"

67618

[(set_attr "type" "vecperm")])

67619

67620

@@ -1308,7 +1814,12 @@

67621

(parallel [(const_int 0) (const_int 4)

67622

(const_int 1) (const_int 5)])))]

67623

"VECTOR_MEM_VSX_P (<MODE>mode)"

67624

- "xxmrghw %x0,%x1,%x2"

67625

+{

67626

+ if (BYTES_BIG_ENDIAN)

67627

+ return "xxmrghw %x0,%x1,%x2";

67628

+ else

67629

+ return "xxmrglw %x0,%x2,%x1";

67630

+}

67631

[(set_attr "type" "vecperm")])

67632

67633

(define_insn "vsx_xxmrglw_<mode>"

67634

@@ -1320,7 +1831,12 @@

67635

(parallel [(const_int 2) (const_int 6)

67636

(const_int 3) (const_int 7)])))]

67637

"VECTOR_MEM_VSX_P (<MODE>mode)"

67638

- "xxmrglw %x0,%x1,%x2"

67639

+{

67640

+ if (BYTES_BIG_ENDIAN)

67641

+ return "xxmrglw %x0,%x1,%x2";

67642

+ else

67643

+ return "xxmrghw %x0,%x2,%x1";

67644

+}

67645

[(set_attr "type" "vecperm")])

67646

67647

;; Shift left double by word immediate

67648

@@ -1483,3 +1999,27 @@

67649

}"

67650

[(set_attr "length" "20")

67651

(set_attr "type" "veccomplex")])

67652

+

67653

+

67654

+;; Power8 Vector fusion. The fused ops must be physically adjacent.

67655

+(define_peephole

67656

+ [(set (match_operand:P 0 "base_reg_operand" "")

67657

+ (match_operand:P 1 "short_cint_operand" ""))

67658

+ (set (match_operand:VSX_M2 2 "vsx_register_operand" "")

67659

+ (mem:VSX_M2 (plus:P (match_dup 0)

67660

+ (match_operand:P 3 "int_reg_operand" ""))))]

67661

+ "TARGET_VSX && TARGET_P8_FUSION"

67662

+ "li %0,%1\t\t\t# vector load fusion\;lx<VSX_M2:VSm>x %x2,%0,%3"

67663

+ [(set_attr "length" "8")

67664

+ (set_attr "type" "vecload")])

67665

+

67666

+(define_peephole

67667

+ [(set (match_operand:P 0 "base_reg_operand" "")

67668

+ (match_operand:P 1 "short_cint_operand" ""))

67669

+ (set (match_operand:VSX_M2 2 "vsx_register_operand" "")

67670

+ (mem:VSX_M2 (plus:P (match_operand:P 3 "int_reg_operand" "")

67671

+ (match_dup 0))))]

67672

+ "TARGET_VSX && TARGET_P8_FUSION"

67673

+ "li %0,%1\t\t\t# vector load fusion\;lx<VSX_M2:VSm>x %x2,%0,%3"

67674

+ [(set_attr "length" "8")

67675

+ (set_attr "type" "vecload")])

67676

Index: gcc/config/rs6000/rs6000.h

67677

===================================================================

67678

--- a/src/gcc/config/rs6000/rs6000.h (.../tags/gcc_4_8_2_release)

67679

+++ b/src/gcc/config/rs6000/rs6000.h (.../branches/gcc-4_8-branch)

67680

@@ -92,7 +92,7 @@

67681

#ifdef HAVE_AS_POWER8

67682

#define ASM_CPU_POWER8_SPEC "-mpower8"

67683

#else

67684

-#define ASM_CPU_POWER8_SPEC "-mpower4 -maltivec"

67685

+#define ASM_CPU_POWER8_SPEC ASM_CPU_POWER7_SPEC

67686

#endif

67687

67688

#ifdef HAVE_AS_DCI

67689

@@ -164,6 +164,7 @@

67690

%{mcpu=e6500: -me6500} \

67691

%{maltivec: -maltivec} \

67692

%{mvsx: -mvsx %{!maltivec: -maltivec} %{!mcpu*: %(asm_cpu_power7)}} \

67693

+%{mpower8-vector|mcrypto|mdirect-move|mhtm: %{!mcpu*: %(asm_cpu_power8)}} \

67694

-many"

67695

67696

#define CPP_DEFAULT_SPEC ""

67697

@@ -277,6 +278,21 @@

67698

#define TARGET_POPCNTD 0

67699

#endif

67700

67701

+/* Define the ISA 2.07 flags as 0 if the target assembler does not support the

67702

+ waitasecond instruction. Allow -mpower8-fusion, since it does not add new

67703

+ instructions. */

67704

+

67705

+#ifndef HAVE_AS_POWER8

67706

+#undef TARGET_DIRECT_MOVE

67707

+#undef TARGET_CRYPTO

67708

+#undef TARGET_HTM

67709

+#undef TARGET_P8_VECTOR

67710

+#define TARGET_DIRECT_MOVE 0

67711

+#define TARGET_CRYPTO 0

67712

+#define TARGET_HTM 0

67713

+#define TARGET_P8_VECTOR 0

67714

+#endif

67715

+

67716

/* Define TARGET_LWSYNC_INSTRUCTION if the assembler knows about lwsync. If

67717

not, generate the lwsync code as an integer constant. */

67718

#ifdef HAVE_AS_LWSYNC

67719

@@ -386,6 +402,7 @@

67720

#define TARGET_DEBUG_TARGET (rs6000_debug & MASK_DEBUG_TARGET)

67721

#define TARGET_DEBUG_BUILTIN (rs6000_debug & MASK_DEBUG_BUILTIN)

67722

67723

+/* Describe the vector unit used for arithmetic operations. */

67724

extern enum rs6000_vector rs6000_vector_unit[];

67725

67726

#define VECTOR_UNIT_NONE_P(MODE) \

67727

@@ -394,12 +411,25 @@

67728

#define VECTOR_UNIT_VSX_P(MODE) \

67729

(rs6000_vector_unit[(MODE)] == VECTOR_VSX)

67730

67731

+#define VECTOR_UNIT_P8_VECTOR_P(MODE) \

67732

+ (rs6000_vector_unit[(MODE)] == VECTOR_P8_VECTOR)

67733

+

67734

#define VECTOR_UNIT_ALTIVEC_P(MODE) \

67735

(rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC)

67736

67737

+#define VECTOR_UNIT_VSX_OR_P8_VECTOR_P(MODE) \

67738

+ (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \

67739

+ (int)VECTOR_VSX, \

67740

+ (int)VECTOR_P8_VECTOR))

67741

+

67742

+/* VECTOR_UNIT_ALTIVEC_OR_VSX_P is used in places where we are using either

67743

+ altivec (VMX) or VSX vector instructions. P8 vector support is upwards

67744

+ compatible, so allow it as well, rather than changing all of the uses of the

67745

+ macro. */

67746

#define VECTOR_UNIT_ALTIVEC_OR_VSX_P(MODE) \

67747

- (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC \

67748

- || rs6000_vector_unit[(MODE)] == VECTOR_VSX)

67749

+ (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \

67750

+ (int)VECTOR_ALTIVEC, \

67751

+ (int)VECTOR_P8_VECTOR))

67752

67753

/* Describe whether to use VSX loads or Altivec loads. For now, just use the

67754

same unit as the vector unit we are using, but we may want to migrate to

67755

@@ -412,12 +442,21 @@

67756

#define VECTOR_MEM_VSX_P(MODE) \

67757

(rs6000_vector_mem[(MODE)] == VECTOR_VSX)

67758

67759

+#define VECTOR_MEM_P8_VECTOR_P(MODE) \

67760

+ (rs6000_vector_mem[(MODE)] == VECTOR_VSX)

67761

+

67762

#define VECTOR_MEM_ALTIVEC_P(MODE) \

67763

(rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC)

67764

67765

+#define VECTOR_MEM_VSX_OR_P8_VECTOR_P(MODE) \

67766

+ (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \

67767

+ (int)VECTOR_VSX, \

67768

+ (int)VECTOR_P8_VECTOR))

67769

+

67770

#define VECTOR_MEM_ALTIVEC_OR_VSX_P(MODE) \

67771

- (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC \

67772

- || rs6000_vector_mem[(MODE)] == VECTOR_VSX)

67773

+ (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \

67774

+ (int)VECTOR_ALTIVEC, \

67775

+ (int)VECTOR_P8_VECTOR))

67776

67777

/* Return the alignment of a given vector type, which is set based on the

67778

vector unit use. VSX for instance can load 32 or 64 bit aligned words

67779

@@ -429,6 +468,15 @@

67780

? rs6000_vector_align[(MODE)] \

67781

: (int)GET_MODE_BITSIZE ((MODE)))

67782

67783

+/* Determine the element order to use for vector instructions. By

67784

+ default we use big-endian element order when targeting big-endian,

67785

+ and little-endian element order when targeting little-endian. For

67786

+ programs being ported from BE Power to LE Power, it can sometimes

67787

+ be useful to use big-endian element order when targeting little-endian.

67788

+ This is set via -maltivec=be, for example. */

67789

+#define VECTOR_ELT_ORDER_BIG \

67790

+ (BYTES_BIG_ENDIAN || (rs6000_altivec_element_order == 2))

67791

+

67792

/* Alignment options for fields in structures for sub-targets following

67793

AIX-like ABI.

67794

ALIGN_POWER word-aligns FP doubles (default AIX ABI).

67795

@@ -479,16 +527,38 @@

67796

#define TARGET_FCTIDUZ TARGET_POPCNTD

67797

#define TARGET_FCTIWUZ TARGET_POPCNTD

67798

67799

+#define TARGET_XSCVDPSPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR)

67800

+#define TARGET_XSCVSPDPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR)

67801

+#define TARGET_VADDUQM (TARGET_P8_VECTOR && TARGET_POWERPC64)

67802

+

67803

+/* Byte/char syncs were added as phased in for ISA 2.06B, but are not present

67804

+ in power7, so conditionalize them on p8 features. TImode syncs need quad

67805

+ memory support. */

67806

+#define TARGET_SYNC_HI_QI (TARGET_QUAD_MEMORY \

67807

+ || TARGET_QUAD_MEMORY_ATOMIC \

67808

+ || TARGET_DIRECT_MOVE)

67809

+

67810

+#define TARGET_SYNC_TI TARGET_QUAD_MEMORY_ATOMIC

67811

+

67812

+/* Power7 has both 32-bit load and store integer for the FPRs, so we don't need

67813

+ to allocate the SDmode stack slot to get the value into the proper location

67814

+ in the register. */

67815

+#define TARGET_NO_SDMODE_STACK (TARGET_LFIWZX && TARGET_STFIWX && TARGET_DFP)

67816

+

67817

/* In switching from using target_flags to using rs6000_isa_flags, the options

67818

machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. For now map

67819

OPTION_MASK_<xxx> back into MASK_<xxx>. */

67820

#define MASK_ALTIVEC OPTION_MASK_ALTIVEC

67821

#define MASK_CMPB OPTION_MASK_CMPB

67822

+#define MASK_CRYPTO OPTION_MASK_CRYPTO

67823

#define MASK_DFP OPTION_MASK_DFP

67824

+#define MASK_DIRECT_MOVE OPTION_MASK_DIRECT_MOVE

67825

#define MASK_DLMZB OPTION_MASK_DLMZB

67826

#define MASK_EABI OPTION_MASK_EABI

67827

#define MASK_FPRND OPTION_MASK_FPRND

67828

+#define MASK_P8_FUSION OPTION_MASK_P8_FUSION

67829

#define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT

67830

+#define MASK_HTM OPTION_MASK_HTM

67831

#define MASK_ISEL OPTION_MASK_ISEL

67832

#define MASK_MFCRF OPTION_MASK_MFCRF

67833

#define MASK_MFPGPR OPTION_MASK_MFPGPR

67834

@@ -495,6 +565,7 @@

67835

#define MASK_MULHW OPTION_MASK_MULHW

67836

#define MASK_MULTIPLE OPTION_MASK_MULTIPLE

67837

#define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE

67838

+#define MASK_P8_VECTOR OPTION_MASK_P8_VECTOR

67839

#define MASK_POPCNTB OPTION_MASK_POPCNTB

67840

#define MASK_POPCNTD OPTION_MASK_POPCNTD

67841

#define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT

67842

@@ -505,6 +576,7 @@

67843

#define MASK_STRING OPTION_MASK_STRING

67844

#define MASK_UPDATE OPTION_MASK_UPDATE

67845

#define MASK_VSX OPTION_MASK_VSX

67846

+#define MASK_VSX_TIMODE OPTION_MASK_VSX_TIMODE

67847

67848

#ifndef IN_LIBGCC2

67849

#define MASK_POWERPC64 OPTION_MASK_POWERPC64

67850

@@ -551,7 +623,8 @@

67851

|| TARGET_CMPB /* ISA 2.05 */ \

67852

|| TARGET_POPCNTD /* ISA 2.06 */ \

67853

|| TARGET_ALTIVEC \

67854

- || TARGET_VSX)))

67855

+ || TARGET_VSX \

67856

+ || TARGET_HARD_FLOAT)))

67857

67858

/* E500 cores only support plain "sync", not lwsync. */

67859

#define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \

67860

@@ -558,6 +631,25 @@

67861

|| rs6000_cpu == PROCESSOR_PPC8548)

67862

67863

67864

+/* Whether SF/DF operations are supported on the E500. */

67865

+#define TARGET_SF_SPE (TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT \

67866

+ && !TARGET_FPRS)

67867

+

67868

+#define TARGET_DF_SPE (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT \

67869

+ && !TARGET_FPRS && TARGET_E500_DOUBLE)

67870

+

67871

+/* Whether SF/DF operations are supported by by the normal floating point unit

67872

+ (or the vector/scalar unit). */

67873

+#define TARGET_SF_FPR (TARGET_HARD_FLOAT && TARGET_FPRS \

67874

+ && TARGET_SINGLE_FLOAT)

67875

+

67876

+#define TARGET_DF_FPR (TARGET_HARD_FLOAT && TARGET_FPRS \

67877

+ && TARGET_DOUBLE_FLOAT)

67878

+

67879

+/* Whether SF/DF operations are supported by any hardware. */

67880

+#define TARGET_SF_INSN (TARGET_SF_FPR || TARGET_SF_SPE)

67881

+#define TARGET_DF_INSN (TARGET_DF_FPR || TARGET_DF_SPE)

67882

+

67883

/* Which machine supports the various reciprocal estimate instructions. */

67884

#define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \

67885

&& TARGET_FPRS && TARGET_SINGLE_FLOAT)

67886

@@ -595,9 +687,6 @@

67887

#define RS6000_RECIP_AUTO_RSQRTE_P(MODE) \

67888

(rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RSQRTE)

67889

67890

-#define RS6000_RECIP_HIGH_PRECISION_P(MODE) \

67891

- ((MODE) == SFmode || (MODE) == V4SFmode || TARGET_RECIP_PRECISION)

67892

-

67893

/* The default CPU for TARGET_OPTION_OVERRIDE. */

67894

#define OPTION_TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT

67895

67896

@@ -760,12 +849,6 @@

67897

/* No data type wants to be aligned rounder than this. */

67898

#define BIGGEST_ALIGNMENT 128

67899

67900

-/* A C expression to compute the alignment for a variables in the

67901

- local store. TYPE is the data type, and ALIGN is the alignment

67902

- that the object would ordinarily have. */

67903

-#define LOCAL_ALIGNMENT(TYPE, ALIGN) \

67904

- DATA_ALIGNMENT (TYPE, ALIGN)

67905

-

67906

/* Alignment of field after `int : 0' in a structure. */

67907

#define EMPTY_FIELD_BOUNDARY 32

67908

67909

@@ -775,8 +858,15 @@

67910

/* A bit-field declared as `int' forces `int' alignment for the struct. */

67911

#define PCC_BITFIELD_TYPE_MATTERS 1

67912

67913

-/* Make strings word-aligned so strcpy from constants will be faster.

67914

- Make vector constants quadword aligned. */

67915

+enum data_align { align_abi, align_opt, align_both };

67916

+

67917

+/* A C expression to compute the alignment for a variables in the

67918

+ local store. TYPE is the data type, and ALIGN is the alignment

67919

+ that the object would ordinarily have. */

67920

+#define LOCAL_ALIGNMENT(TYPE, ALIGN) \

67921

+ rs6000_data_alignment (TYPE, ALIGN, align_both)

67922

+

67923

+/* Make strings word-aligned so strcpy from constants will be faster. */

67924

#define CONSTANT_ALIGNMENT(EXP, ALIGN) \

67925

(TREE_CODE (EXP) == STRING_CST \

67926

&& (STRICT_ALIGNMENT || !optimize_size) \

67927

@@ -784,21 +874,14 @@

67928

? BITS_PER_WORD \

67929

: (ALIGN))

67930

67931

-/* Make arrays of chars word-aligned for the same reasons.

67932

- Align vectors to 128 bits. Align SPE vectors and E500 v2 doubles to

67933

+/* Make arrays of chars word-aligned for the same reasons. */

67934

+#define DATA_ALIGNMENT(TYPE, ALIGN) \

67935

+ rs6000_data_alignment (TYPE, ALIGN, align_opt)

67936

+

67937

+/* Align vectors to 128 bits. Align SPE vectors and E500 v2 doubles to

67938

64 bits. */

67939

-#define DATA_ALIGNMENT(TYPE, ALIGN) \

67940

- (TREE_CODE (TYPE) == VECTOR_TYPE \

67941

- ? (((TARGET_SPE && SPE_VECTOR_MODE (TYPE_MODE (TYPE))) \

67942

- || (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (TYPE_MODE (TYPE)))) \

67943

- ? 64 : 128) \

67944

- : ((TARGET_E500_DOUBLE \

67945

- && TREE_CODE (TYPE) == REAL_TYPE \

67946

- && TYPE_MODE (TYPE) == DFmode) \

67947

- ? 64 \

67948

- : (TREE_CODE (TYPE) == ARRAY_TYPE \

67949

- && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \

67950

- && (ALIGN) < BITS_PER_WORD) ? BITS_PER_WORD : (ALIGN)))

67951

+#define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \

67952

+ rs6000_data_alignment (TYPE, ALIGN, align_abi)

67953

67954

/* Nonzero if move instructions will actually fail to work

67955

when given unaligned data. */

67956

@@ -842,15 +925,17 @@

67957

in inline functions.

67958

67959

Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame

67960

- pointer, which is eventually eliminated in favor of SP or FP. */

67961

+ pointer, which is eventually eliminated in favor of SP or FP.

67962

67963

-#define FIRST_PSEUDO_REGISTER 114

67964

+ The 3 HTM registers aren't also included in DWARF_FRAME_REGISTERS. */

67965

67966

+#define FIRST_PSEUDO_REGISTER 117

67967

+

67968

/* This must be included for pre gcc 3.0 glibc compatibility. */

67969

#define PRE_GCC3_DWARF_FRAME_REGISTERS 77

67970

67971

/* Add 32 dwarf columns for synthetic SPE registers. */

67972

-#define DWARF_FRAME_REGISTERS ((FIRST_PSEUDO_REGISTER - 1) + 32)

67973

+#define DWARF_FRAME_REGISTERS ((FIRST_PSEUDO_REGISTER - 4) + 32)

67974

67975

/* The SPE has an additional 32 synthetic registers, with DWARF debug

67976

info numbering for these registers starting at 1200. While eh_frame

67977

@@ -866,7 +951,7 @@

67978

We must map them here to avoid huge unwinder tables mostly consisting

67979

of unused space. */

67980

#define DWARF_REG_TO_UNWIND_COLUMN(r) \

67981

- ((r) > 1200 ? ((r) - 1200 + FIRST_PSEUDO_REGISTER - 1) : (r))

67982

+ ((r) > 1200 ? ((r) - 1200 + (DWARF_FRAME_REGISTERS - 32)) : (r))

67983

67984

/* Use standard DWARF numbering for DWARF debugging information. */

67985

#define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO)

67986

@@ -906,7 +991,7 @@

67987

0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \

67988

0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \

67989

1, 1 \

67990

- , 1, 1, 1 \

67991

+ , 1, 1, 1, 1, 1, 1 \

67992

}

67993

67994

/* 1 for registers not available across function calls.

67995

@@ -926,7 +1011,7 @@

67996

0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \

67997

0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \

67998

1, 1 \

67999

- , 1, 1, 1 \

68000

+ , 1, 1, 1, 1, 1, 1 \

68001

}

68002

68003

/* Like `CALL_USED_REGISTERS' except this macro doesn't require that

68004

@@ -945,7 +1030,7 @@

68005

0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \

68006

0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \

68007

0, 0 \

68008

- , 0, 0, 0 \

68009

+ , 0, 0, 0, 0, 0, 0 \

68010

}

68011

68012

#define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)

68013

@@ -984,6 +1069,9 @@

68014

vrsave, vscr (fixed)

68015

spe_acc, spefscr (fixed)

68016

sfp (fixed)

68017

+ tfhar (fixed)

68018

+ tfiar (fixed)

68019

+ texasr (fixed)

68020

*/

68021

68022

#if FIXED_R2 == 1

68023

@@ -1004,7 +1092,9 @@

68024

68025

#define REG_ALLOC_ORDER \

68026

{32, \

68027

- 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \

68028

+ /* move fr13 (ie 45) later, so if we need TFmode, it does */ \

68029

+ /* not use fr14 which is a saved register. */ \

68030

+ 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, 45, \

68031

33, \

68032

63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \

68033

50, 49, 48, 47, 46, \

68034

@@ -1023,7 +1113,7 @@

68035

96, 95, 94, 93, 92, 91, \

68036

108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \

68037

109, 110, \

68038

- 111, 112, 113 \

68039

+ 111, 112, 113, 114, 115, 116 \

68040

}

68041

68042

/* True if register is floating-point. */

68043

@@ -1064,8 +1154,11 @@

68044

#define VINT_REGNO_P(N) ALTIVEC_REGNO_P (N)

68045

68046

/* Alternate name for any vector register supporting logical operations, no

68047

- matter which instruction set(s) are available. */

68048

-#define VLOGICAL_REGNO_P(N) VFLOAT_REGNO_P (N)

68049

+ matter which instruction set(s) are available. Allow GPRs as well as the

68050

+ vector registers. */

68051

+#define VLOGICAL_REGNO_P(N) \

68052

+ (INT_REGNO_P (N) || ALTIVEC_REGNO_P (N) \

68053

+ || (TARGET_VSX && FP_REGNO_P (N))) \

68054

68055

/* Return number of consecutive hard regs needed starting at reg REGNO

68056

to hold something of mode MODE. */

68057

@@ -1106,7 +1199,7 @@

68058

68059

#define ALTIVEC_OR_VSX_VECTOR_MODE(MODE) \

68060

(ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \

68061

- || (MODE) == V2DImode)

68062

+ || (MODE) == V2DImode || (MODE) == V1TImode)

68063

68064

#define SPE_VECTOR_MODE(MODE) \

68065

((MODE) == V4HImode \

68066

@@ -1125,28 +1218,32 @@

68067

/* Value is 1 if it is a good idea to tie two pseudo registers

68068

when one has mode MODE1 and one has mode MODE2.

68069

If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,

68070

- for any hard reg, then this must be 0 for correct output. */

68071

-#define MODES_TIEABLE_P(MODE1, MODE2) \

68072

- (SCALAR_FLOAT_MODE_P (MODE1) \

68073

+ for any hard reg, then this must be 0 for correct output.

68074

+

68075

+ PTImode cannot tie with other modes because PTImode is restricted to even

68076

+ GPR registers, and TImode can go in any GPR as well as VSX registers (PR

68077

+ 57744). */

68078

+#define MODES_TIEABLE_P(MODE1, MODE2) \

68079

+ ((MODE1) == PTImode \

68080

+ ? (MODE2) == PTImode \

68081

+ : (MODE2) == PTImode \

68082

+ ? 0 \

68083

+ : SCALAR_FLOAT_MODE_P (MODE1) \

68084

? SCALAR_FLOAT_MODE_P (MODE2) \

68085

: SCALAR_FLOAT_MODE_P (MODE2) \

68086

- ? SCALAR_FLOAT_MODE_P (MODE1) \

68087

+ ? 0 \

68088

: GET_MODE_CLASS (MODE1) == MODE_CC \

68089

? GET_MODE_CLASS (MODE2) == MODE_CC \

68090

: GET_MODE_CLASS (MODE2) == MODE_CC \

68091

- ? GET_MODE_CLASS (MODE1) == MODE_CC \

68092

+ ? 0 \

68093

: SPE_VECTOR_MODE (MODE1) \

68094

? SPE_VECTOR_MODE (MODE2) \

68095

: SPE_VECTOR_MODE (MODE2) \

68096

- ? SPE_VECTOR_MODE (MODE1) \

68097

- : ALTIVEC_VECTOR_MODE (MODE1) \

68098

- ? ALTIVEC_VECTOR_MODE (MODE2) \

68099

- : ALTIVEC_VECTOR_MODE (MODE2) \

68100

- ? ALTIVEC_VECTOR_MODE (MODE1) \

68101

+ ? 0 \

68102

: ALTIVEC_OR_VSX_VECTOR_MODE (MODE1) \

68103

? ALTIVEC_OR_VSX_VECTOR_MODE (MODE2) \

68104

: ALTIVEC_OR_VSX_VECTOR_MODE (MODE2) \

68105

- ? ALTIVEC_OR_VSX_VECTOR_MODE (MODE1) \

68106

+ ? 0 \

68107

: 1)

68108

68109

/* Post-reload, we can't use any new AltiVec registers, as we already

68110

@@ -1240,6 +1337,7 @@

68111

VSCR_REGS,

68112

SPE_ACC_REGS,

68113

SPEFSCR_REGS,

68114

+ SPR_REGS,

68115

NON_SPECIAL_REGS,

68116

LINK_REGS,

68117

CTR_REGS,

68118

@@ -1270,6 +1368,7 @@

68119

"VSCR_REGS", \

68120

"SPE_ACC_REGS", \

68121

"SPEFSCR_REGS", \

68122

+ "SPR_REGS", \

68123

"NON_SPECIAL_REGS", \

68124

"LINK_REGS", \

68125

"CTR_REGS", \

68126

@@ -1299,6 +1398,7 @@

68127

{ 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \

68128

{ 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \

68129

{ 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \

68130

+ { 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, /* SPR_REGS */ \

68131

{ 0xffffffff, 0xffffffff, 0x00000008, 0x00020000 }, /* NON_SPECIAL_REGS */ \

68132

{ 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \

68133

{ 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \

68134

@@ -1309,7 +1409,7 @@

68135

{ 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \

68136

{ 0xffffffff, 0x00000000, 0x00000ffe, 0x00020000 }, /* NON_FLOAT_REGS */ \

68137

{ 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* CA_REGS */ \

68138

- { 0xffffffff, 0xffffffff, 0xfffffffe, 0x0003ffff } /* ALL_REGS */ \

68139

+ { 0xffffffff, 0xffffffff, 0xfffffffe, 0x0007ffff } /* ALL_REGS */ \

68140

}

68141

68142

/* The same information, inverted:

68143

@@ -1337,7 +1437,18 @@

68144

RS6000_CONSTRAINT_wa, /* Any VSX register */

68145

RS6000_CONSTRAINT_wd, /* VSX register for V2DF */

68146

RS6000_CONSTRAINT_wf, /* VSX register for V4SF */

68147

+ RS6000_CONSTRAINT_wg, /* FPR register for -mmfpgpr */

68148

+ RS6000_CONSTRAINT_wl, /* FPR register for LFIWAX */

68149

+ RS6000_CONSTRAINT_wm, /* VSX register for direct move */

68150

+ RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */

68151

RS6000_CONSTRAINT_ws, /* VSX register for DF */

68152

+ RS6000_CONSTRAINT_wt, /* VSX register for TImode */

68153

+ RS6000_CONSTRAINT_wu, /* Altivec register for float load/stores. */

68154

+ RS6000_CONSTRAINT_wv, /* Altivec register for double load/stores. */

68155

+ RS6000_CONSTRAINT_ww, /* FP or VSX register for vsx float ops. */

68156

+ RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */

68157

+ RS6000_CONSTRAINT_wy, /* VSX register for SF */

68158

+ RS6000_CONSTRAINT_wz, /* FPR register for LFIWZX */

68159

RS6000_CONSTRAINT_MAX

68160

};

68161

68162

@@ -1425,21 +1536,14 @@

68163

arguments. */

68164

#define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0 || flag_asan != 0)

68165

68166

-/* Size of the outgoing register save area */

68167

-#define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \

68168

- || DEFAULT_ABI == ABI_DARWIN) \

68169

- ? (TARGET_64BIT ? 64 : 32) \

68170

- : 0)

68171

-

68172

/* Size of the fixed area on the stack */

68173

#define RS6000_SAVE_AREA \

68174

- (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \

68175

+ ((DEFAULT_ABI == ABI_V4 ? 8 : DEFAULT_ABI == ABI_ELFv2 ? 16 : 24) \

68176

<< (TARGET_64BIT ? 1 : 0))

68177

68178

-/* MEM representing address to save the TOC register */

68179

-#define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \

68180

- plus_constant (Pmode, stack_pointer_rtx, \

68181

- (TARGET_32BIT ? 20 : 40)))

68182

+/* Stack offset for toc save slot. */

68183

+#define RS6000_TOC_SAVE_SLOT \

68184

+ ((DEFAULT_ABI == ABI_ELFv2 ? 12 : 20) << (TARGET_64BIT ? 1 : 0))

68185

68186

/* Align an address */

68187

#define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1))

68188

@@ -1489,7 +1593,7 @@

68189

/* Define this if stack space is still allocated for a parameter passed

68190

in a register. The value is the number of bytes allocated to this

68191

area. */

68192

-#define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE

68193

+#define REG_PARM_STACK_SPACE(FNDECL) rs6000_reg_parm_stack_space((FNDECL))

68194

68195

/* Define this if the above stack space is to be considered part of the

68196

space allocated by the caller. */

68197

@@ -1522,7 +1626,7 @@

68198

NONLOCAL needs twice Pmode to maintain both backchain and SP. */

68199

#define STACK_SAVEAREA_MODE(LEVEL) \

68200

(LEVEL == SAVE_FUNCTION ? VOIDmode \

68201

- : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode)

68202

+ : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : PTImode) : Pmode)

68203

68204

/* Minimum and maximum general purpose registers used to hold arguments. */

68205

#define GP_ARG_MIN_REG 3

68206

@@ -1533,9 +1637,8 @@

68207

#define FP_ARG_MIN_REG 33

68208

#define FP_ARG_AIX_MAX_REG 45

68209

#define FP_ARG_V4_MAX_REG 40

68210

-#define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \

68211

- || DEFAULT_ABI == ABI_DARWIN) \

68212

- ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG)

68213

+#define FP_ARG_MAX_REG (DEFAULT_ABI == ABI_V4 \

68214

+ ? FP_ARG_V4_MAX_REG : FP_ARG_AIX_MAX_REG)

68215

#define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)

68216

68217

/* Minimum and maximum AltiVec registers used to hold arguments. */

68218

@@ -1543,10 +1646,17 @@

68219

#define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)

68220

#define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)

68221

68222

+/* Maximum number of registers per ELFv2 homogeneous aggregate argument. */

68223

+#define AGGR_ARG_NUM_REG 8

68224

+

68225

/* Return registers */

68226

#define GP_ARG_RETURN GP_ARG_MIN_REG

68227

#define FP_ARG_RETURN FP_ARG_MIN_REG

68228

#define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)

68229

+#define FP_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 ? FP_ARG_RETURN \

68230

+ : (FP_ARG_RETURN + AGGR_ARG_NUM_REG - 1))

68231

+#define ALTIVEC_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 ? ALTIVEC_ARG_RETURN \

68232

+ : (ALTIVEC_ARG_RETURN + AGGR_ARG_NUM_REG - 1))

68233

68234

/* Flags for the call/call_value rtl operations set up by function_arg */

68235

#define CALL_NORMAL 0x00000000 /* no special processing */

68236

@@ -1566,8 +1676,10 @@

68237

On RS/6000, this is r3, fp1, and v2 (for AltiVec). */

68238

#define FUNCTION_VALUE_REGNO_P(N) \

68239

((N) == GP_ARG_RETURN \

68240

- || ((N) == FP_ARG_RETURN && TARGET_HARD_FLOAT && TARGET_FPRS) \

68241

- || ((N) == ALTIVEC_ARG_RETURN && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI))

68242

+ || ((N) >= FP_ARG_RETURN && (N) <= FP_ARG_MAX_RETURN \

68243

+ && TARGET_HARD_FLOAT && TARGET_FPRS) \

68244

+ || ((N) >= ALTIVEC_ARG_RETURN && (N) <= ALTIVEC_ARG_MAX_RETURN \

68245

+ && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI))

68246

68247

/* 1 if N is a possible register number for function argument passing.

68248

On RS/6000, these are r3-r10 and fp1-fp13.

68249

@@ -1691,11 +1803,8 @@

68250

/* Number of bytes into the frame return addresses can be found. See

68251

rs6000_stack_info in rs6000.c for more information on how the different

68252

abi's store the return address. */

68253

-#define RETURN_ADDRESS_OFFSET \

68254

- ((DEFAULT_ABI == ABI_AIX \

68255

- || DEFAULT_ABI == ABI_DARWIN) ? (TARGET_32BIT ? 8 : 16) : \

68256

- (DEFAULT_ABI == ABI_V4) ? 4 : \

68257

- (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0))

68258

+#define RETURN_ADDRESS_OFFSET \

68259

+ ((DEFAULT_ABI == ABI_V4 ? 4 : 8) << (TARGET_64BIT ? 1 : 0))

68260

68261

/* The current return address is in link register (65). The return address

68262

of anything farther back is accessed normally at an offset of 8 from the

68263

@@ -2215,6 +2324,9 @@

68264

&rs6000_reg_names[111][0], /* spe_acc */ \

68265

&rs6000_reg_names[112][0], /* spefscr */ \

68266

&rs6000_reg_names[113][0], /* sfp */ \

68267

+ &rs6000_reg_names[114][0], /* tfhar */ \

68268

+ &rs6000_reg_names[115][0], /* tfiar */ \

68269

+ &rs6000_reg_names[116][0], /* texasr */ \

68270

}

68271

68272

/* Table of additional register names to use in user input. */

68273

@@ -2268,7 +2380,9 @@

68274

{"vs48", 93}, {"vs49", 94}, {"vs50", 95}, {"vs51", 96}, \

68275

{"vs52", 97}, {"vs53", 98}, {"vs54", 99}, {"vs55", 100}, \

68276

{"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104}, \

68277

- {"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108} }

68278

+ {"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108}, \

68279

+ /* Transactional Memory Facility (HTM) Registers. */ \

68280

+ {"tfhar", 114}, {"tfiar", 115}, {"texasr", 116} }

68281

68282

/* This is how to output an element of a case-vector that is relative. */

68283

68284

@@ -2357,7 +2471,12 @@

68285

#define RS6000_BTC_ATTR_MASK 0x00000700 /* Mask of the attributes. */

68286

68287

/* Miscellaneous information. */

68288

-#define RS6000_BTC_OVERLOADED 0x4000000 /* function is overloaded. */

68289

+#define RS6000_BTC_SPR 0x01000000 /* function references SPRs. */

68290

+#define RS6000_BTC_VOID 0x02000000 /* function has no return value. */

68291

+#define RS6000_BTC_OVERLOADED 0x04000000 /* function is overloaded. */

68292

+#define RS6000_BTC_32BIT 0x08000000 /* function references SPRs. */

68293

+#define RS6000_BTC_64BIT 0x10000000 /* function references SPRs. */

68294

+#define RS6000_BTC_MISC_MASK 0x1f000000 /* Mask of the misc info. */

68295

68296

/* Convenience macros to document the instruction type. */

68297

#define RS6000_BTC_MEM RS6000_BTC_MISC /* load/store touches mem. */

68298

@@ -2369,6 +2488,9 @@

68299

#define RS6000_BTM_ALWAYS 0 /* Always enabled. */

68300

#define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */

68301

#define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */

68302

+#define RS6000_BTM_P8_VECTOR MASK_P8_VECTOR /* ISA 2.07 vector. */

68303

+#define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */

68304

+#define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */

68305

#define RS6000_BTM_SPE MASK_STRING /* E500 */

68306

#define RS6000_BTM_PAIRED MASK_MULHW /* 750CL paired insns. */

68307

#define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */

68308

@@ -2377,15 +2499,22 @@

68309

#define RS6000_BTM_FRSQRTES MASK_POPCNTB /* FRSQRTES instruction. */

68310

#define RS6000_BTM_POPCNTD MASK_POPCNTD /* Target supports ISA 2.06. */

68311

#define RS6000_BTM_CELL MASK_FPRND /* Target is cell powerpc. */

68312

+#define RS6000_BTM_DFP MASK_DFP /* Decimal floating point. */

68313

+#define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */

68314

68315

#define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \

68316

| RS6000_BTM_VSX \

68317

+ | RS6000_BTM_P8_VECTOR \

68318

+ | RS6000_BTM_CRYPTO \

68319

| RS6000_BTM_FRE \

68320

| RS6000_BTM_FRES \

68321

| RS6000_BTM_FRSQRTE \

68322

| RS6000_BTM_FRSQRTES \

68323

+ | RS6000_BTM_HTM \

68324

| RS6000_BTM_POPCNTD \

68325

- | RS6000_BTM_CELL)

68326

+ | RS6000_BTM_CELL \

68327

+ | RS6000_BTM_DFP \

68328

+ | RS6000_BTM_HARD_FLOAT)

68329

68330

/* Define builtin enum index. */

68331

68332

@@ -2395,6 +2524,7 @@

68333

#undef RS6000_BUILTIN_A

68334

#undef RS6000_BUILTIN_D

68335

#undef RS6000_BUILTIN_E

68336

+#undef RS6000_BUILTIN_H

68337

#undef RS6000_BUILTIN_P

68338

#undef RS6000_BUILTIN_Q

68339

#undef RS6000_BUILTIN_S

68340

@@ -2406,6 +2536,7 @@

68341

#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) ENUM,

68342

#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) ENUM,

68343

#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) ENUM,

68344

+#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) ENUM,

68345

#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) ENUM,

68346

#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) ENUM,

68347

#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) ENUM,

68348

@@ -2424,6 +2555,7 @@

68349

#undef RS6000_BUILTIN_A

68350

#undef RS6000_BUILTIN_D

68351

#undef RS6000_BUILTIN_E

68352

+#undef RS6000_BUILTIN_H

68353

#undef RS6000_BUILTIN_P

68354

#undef RS6000_BUILTIN_Q

68355

#undef RS6000_BUILTIN_S

68356

@@ -2437,6 +2569,7 @@

68357

RS6000_BTI_opaque_p_V2SI,

68358

RS6000_BTI_opaque_V4SI,

68359

RS6000_BTI_V16QI,

68360

+ RS6000_BTI_V1TI,

68361

RS6000_BTI_V2SI,

68362

RS6000_BTI_V2SF,

68363

RS6000_BTI_V2DI,

68364

@@ -2446,6 +2579,7 @@

68365

RS6000_BTI_V4SF,

68366

RS6000_BTI_V8HI,

68367

RS6000_BTI_unsigned_V16QI,

68368

+ RS6000_BTI_unsigned_V1TI,

68369

RS6000_BTI_unsigned_V8HI,

68370

RS6000_BTI_unsigned_V4SI,

68371

RS6000_BTI_unsigned_V2DI,

68372

@@ -2471,8 +2605,13 @@

68373

RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */

68374

RS6000_BTI_INTDI, /* intDI_type_node */

68375

RS6000_BTI_UINTDI, /* unsigned_intDI_type_node */

68376

+ RS6000_BTI_INTTI, /* intTI_type_node */

68377

+ RS6000_BTI_UINTTI, /* unsigned_intTI_type_node */

68378

RS6000_BTI_float, /* float_type_node */

68379

RS6000_BTI_double, /* double_type_node */

68380

+ RS6000_BTI_long_double, /* long_double_type_node */

68381

+ RS6000_BTI_dfloat64, /* dfloat64_type_node */

68382

+ RS6000_BTI_dfloat128, /* dfloat128_type_node */

68383

RS6000_BTI_void, /* void_type_node */

68384

RS6000_BTI_MAX

68385

};

68386

@@ -2483,6 +2622,7 @@

68387

#define opaque_p_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_p_V2SI])

68388

#define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI])

68389

#define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI])

68390

+#define V1TI_type_node (rs6000_builtin_types[RS6000_BTI_V1TI])

68391

#define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI])

68392

#define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF])

68393

#define V2SI_type_node (rs6000_builtin_types[RS6000_BTI_V2SI])

68394

@@ -2492,6 +2632,7 @@

68395

#define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF])

68396

#define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI])

68397

#define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI])

68398

+#define unsigned_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V1TI])

68399

#define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI])

68400

#define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI])

68401

#define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI])

68402

@@ -2518,8 +2659,13 @@

68403

#define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI])

68404

#define intDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTDI])

68405

#define uintDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTDI])

68406

+#define intTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTTI])

68407

+#define uintTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTTI])

68408

#define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float])

68409

#define double_type_internal_node (rs6000_builtin_types[RS6000_BTI_double])

68410

+#define long_double_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_double])

68411

+#define dfloat64_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat64])

68412

+#define dfloat128_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat128])

68413

#define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void])

68414

68415

extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX];

68416

Index: gcc/config/rs6000/altivec.md

68417

===================================================================

68418

--- a/src/gcc/config/rs6000/altivec.md (.../tags/gcc_4_8_2_release)

68419

+++ b/src/gcc/config/rs6000/altivec.md (.../branches/gcc-4_8-branch)

68420

@@ -41,15 +41,12 @@

68421

UNSPEC_VMULOSB

68422

UNSPEC_VMULOUH

68423

UNSPEC_VMULOSH

68424

- UNSPEC_VPKUHUM

68425

- UNSPEC_VPKUWUM

68426

UNSPEC_VPKPX

68427

- UNSPEC_VPKSHSS

68428

- UNSPEC_VPKSWSS

68429

- UNSPEC_VPKUHUS

68430

- UNSPEC_VPKSHUS

68431

- UNSPEC_VPKUWUS

68432

- UNSPEC_VPKSWUS

68433

+ UNSPEC_VPACK_SIGN_SIGN_SAT

68434

+ UNSPEC_VPACK_SIGN_UNS_SAT

68435

+ UNSPEC_VPACK_UNS_UNS_SAT

68436

+ UNSPEC_VPACK_UNS_UNS_MOD

68437

+ UNSPEC_VPACK_UNS_UNS_MOD_DIRECT

68438

UNSPEC_VSLV4SI

68439

UNSPEC_VSLO

68440

UNSPEC_VSR

68441

@@ -71,12 +68,12 @@

68442

UNSPEC_VLOGEFP

68443

UNSPEC_VEXPTEFP

68444

UNSPEC_VLSDOI

68445

- UNSPEC_VUPKHSB

68446

+ UNSPEC_VUNPACK_HI_SIGN

68447

+ UNSPEC_VUNPACK_LO_SIGN

68448

+ UNSPEC_VUNPACK_HI_SIGN_DIRECT

68449

+ UNSPEC_VUNPACK_LO_SIGN_DIRECT

68450

UNSPEC_VUPKHPX

68451

- UNSPEC_VUPKHSH

68452

- UNSPEC_VUPKLSB

68453

UNSPEC_VUPKLPX

68454

- UNSPEC_VUPKLSH

68455

UNSPEC_DST

68456

UNSPEC_DSTT

68457

UNSPEC_DSTST

68458

@@ -134,6 +131,21 @@

68459

UNSPEC_VUPKLS_V4SF

68460

UNSPEC_VUPKHU_V4SF

68461

UNSPEC_VUPKLU_V4SF

68462

+ UNSPEC_VGBBD

68463

+ UNSPEC_VMRGH_DIRECT

68464

+ UNSPEC_VMRGL_DIRECT

68465

+ UNSPEC_VSPLT_DIRECT

68466

+ UNSPEC_VSUMSWS_DIRECT

68467

+ UNSPEC_VADDCUQ

68468

+ UNSPEC_VADDEUQM

68469

+ UNSPEC_VADDECUQ

68470

+ UNSPEC_VSUBCUQ

68471

+ UNSPEC_VSUBEUQM

68472

+ UNSPEC_VSUBECUQ

68473

+ UNSPEC_VBPERMQ

68474

+ UNSPEC_BCDADD

68475

+ UNSPEC_BCDSUB

68476

+ UNSPEC_BCD_OVERFLOW

68477

])

68478

68479

(define_c_enum "unspecv"

68480

@@ -146,6 +158,8 @@

68481

68482

;; Vec int modes

68483

(define_mode_iterator VI [V4SI V8HI V16QI])

68484

+;; Like VI, but add ISA 2.07 integer vector ops

68485

+(define_mode_iterator VI2 [V4SI V8HI V16QI V2DI])

68486

;; Short vec in modes

68487

(define_mode_iterator VIshort [V8HI V16QI])

68488

;; Vec float modes

68489

@@ -154,14 +168,25 @@

68490

(define_mode_iterator V [V4SI V8HI V16QI V4SF])

68491

;; Vec modes for move/logical/permute ops, include vector types for move not

68492

;; otherwise handled by altivec (v2df, v2di, ti)

68493

-(define_mode_iterator VM [V4SI V8HI V16QI V4SF V2DF V2DI TI])

68494

+(define_mode_iterator VM [V4SI V8HI V16QI V4SF V2DF V2DI V1TI TI])

68495

68496

;; Like VM, except don't do TImode

68497

-(define_mode_iterator VM2 [V4SI V8HI V16QI V4SF V2DF V2DI])

68498

+(define_mode_iterator VM2 [V4SI V8HI V16QI V4SF V2DF V2DI V1TI])

68499

68500

-(define_mode_attr VI_char [(V4SI "w") (V8HI "h") (V16QI "b")])

68501

-(define_mode_attr VI_scalar [(V4SI "SI") (V8HI "HI") (V16QI "QI")])

68502

+(define_mode_attr VI_char [(V2DI "d") (V4SI "w") (V8HI "h") (V16QI "b")])

68503

+(define_mode_attr VI_scalar [(V2DI "DI") (V4SI "SI") (V8HI "HI") (V16QI "QI")])

68504

+(define_mode_attr VI_unit [(V16QI "VECTOR_UNIT_ALTIVEC_P (V16QImode)")

68505

+ (V8HI "VECTOR_UNIT_ALTIVEC_P (V8HImode)")

68506

+ (V4SI "VECTOR_UNIT_ALTIVEC_P (V4SImode)")

68507

+ (V2DI "VECTOR_UNIT_P8_VECTOR_P (V2DImode)")

68508

+ (V1TI "VECTOR_UNIT_ALTIVEC_P (V1TImode)")])

68509

68510

+;; Vector pack/unpack

68511

+(define_mode_iterator VP [V2DI V4SI V8HI])

68512

+(define_mode_attr VP_small [(V2DI "V4SI") (V4SI "V8HI") (V8HI "V16QI")])

68513

+(define_mode_attr VP_small_lc [(V2DI "v4si") (V4SI "v8hi") (V8HI "v16qi")])

68514

+(define_mode_attr VU_char [(V2DI "w") (V4SI "h") (V8HI "b")])

68515

+

68516

;; Vector move instructions.

68517

(define_insn "*altivec_mov<mode>"

68518

[(set (match_operand:VM2 0 "nonimmediate_operand" "=Z,v,v,*Y,*r,*r,v,v")

68519

@@ -378,10 +403,10 @@

68520

68521

;; add

68522

(define_insn "add<mode>3"

68523

- [(set (match_operand:VI 0 "register_operand" "=v")

68524

- (plus:VI (match_operand:VI 1 "register_operand" "v")

68525

- (match_operand:VI 2 "register_operand" "v")))]

68526

- "TARGET_ALTIVEC"

68527

+ [(set (match_operand:VI2 0 "register_operand" "=v")

68528

+ (plus:VI2 (match_operand:VI2 1 "register_operand" "v")

68529

+ (match_operand:VI2 2 "register_operand" "v")))]

68530

+ "<VI_unit>"

68531

"vaddu<VI_char>m %0,%1,%2"

68532

[(set_attr "type" "vecsimple")])

68533

68534

@@ -398,7 +423,7 @@

68535

(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")

68536

(match_operand:V4SI 2 "register_operand" "v")]

68537

UNSPEC_VADDCUW))]

68538

- "TARGET_ALTIVEC"

68539

+ "VECTOR_UNIT_ALTIVEC_P (V4SImode)"

68540

"vaddcuw %0,%1,%2"

68541

[(set_attr "type" "vecsimple")])

68542

68543

@@ -405,10 +430,10 @@

68544

(define_insn "altivec_vaddu<VI_char>s"

68545

[(set (match_operand:VI 0 "register_operand" "=v")

68546

(unspec:VI [(match_operand:VI 1 "register_operand" "v")

68547

- (match_operand:VI 2 "register_operand" "v")]

68548

+ (match_operand:VI 2 "register_operand" "v")]

68549

UNSPEC_VADDU))

68550

(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]

68551

- "TARGET_ALTIVEC"

68552

+ "<VI_unit>"

68553

"vaddu<VI_char>s %0,%1,%2"

68554

[(set_attr "type" "vecsimple")])

68555

68556

@@ -418,16 +443,16 @@

68557

(match_operand:VI 2 "register_operand" "v")]

68558

UNSPEC_VADDS))

68559

(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]

68560

- "TARGET_ALTIVEC"

68561

+ "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"

68562

"vadds<VI_char>s %0,%1,%2"

68563

[(set_attr "type" "vecsimple")])

68564

68565

;; sub

68566

(define_insn "sub<mode>3"

68567

- [(set (match_operand:VI 0 "register_operand" "=v")

68568

- (minus:VI (match_operand:VI 1 "register_operand" "v")

68569

- (match_operand:VI 2 "register_operand" "v")))]

68570

- "TARGET_ALTIVEC"

68571

+ [(set (match_operand:VI2 0 "register_operand" "=v")

68572

+ (minus:VI2 (match_operand:VI2 1 "register_operand" "v")

68573

+ (match_operand:VI2 2 "register_operand" "v")))]

68574

+ "<VI_unit>"

68575

"vsubu<VI_char>m %0,%1,%2"

68576

[(set_attr "type" "vecsimple")])

68577

68578

@@ -444,7 +469,7 @@

68579

(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")

68580

(match_operand:V4SI 2 "register_operand" "v")]

68581

UNSPEC_VSUBCUW))]

68582

- "TARGET_ALTIVEC"

68583

+ "VECTOR_UNIT_ALTIVEC_P (V4SImode)"

68584

"vsubcuw %0,%1,%2"

68585

[(set_attr "type" "vecsimple")])

68586

68587

@@ -454,7 +479,7 @@

68588

(match_operand:VI 2 "register_operand" "v")]

68589

UNSPEC_VSUBU))

68590

(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]

68591

- "TARGET_ALTIVEC"

68592

+ "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"

68593

"vsubu<VI_char>s %0,%1,%2"

68594

[(set_attr "type" "vecsimple")])

68595

68596

@@ -464,7 +489,7 @@

68597

(match_operand:VI 2 "register_operand" "v")]

68598

UNSPEC_VSUBS))

68599

(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]

68600

- "TARGET_ALTIVEC"

68601

+ "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"

68602

"vsubs<VI_char>s %0,%1,%2"

68603

[(set_attr "type" "vecsimple")])

68604

68605

@@ -483,7 +508,7 @@

68606

(unspec:VI [(match_operand:VI 1 "register_operand" "v")

68607

(match_operand:VI 2 "register_operand" "v")]

68608

UNSPEC_VAVGS))]

68609

- "TARGET_ALTIVEC"

68610

+ "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"

68611

"vavgs<VI_char> %0,%1,%2"

68612

[(set_attr "type" "vecsimple")])

68613

68614

@@ -492,31 +517,31 @@

68615

(unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")

68616

(match_operand:V4SF 2 "register_operand" "v")]

68617

UNSPEC_VCMPBFP))]

68618

- "TARGET_ALTIVEC"

68619

+ "VECTOR_UNIT_ALTIVEC_P (V4SImode)"

68620

"vcmpbfp %0,%1,%2"

68621

[(set_attr "type" "veccmp")])

68622

68623

(define_insn "*altivec_eq<mode>"

68624

- [(set (match_operand:VI 0 "altivec_register_operand" "=v")

68625

- (eq:VI (match_operand:VI 1 "altivec_register_operand" "v")

68626

- (match_operand:VI 2 "altivec_register_operand" "v")))]

68627

- "TARGET_ALTIVEC"

68628

+ [(set (match_operand:VI2 0 "altivec_register_operand" "=v")

68629

+ (eq:VI2 (match_operand:VI2 1 "altivec_register_operand" "v")

68630

+ (match_operand:VI2 2 "altivec_register_operand" "v")))]

68631

+ "<VI_unit>"

68632

"vcmpequ<VI_char> %0,%1,%2"

68633

[(set_attr "type" "veccmp")])

68634

68635

(define_insn "*altivec_gt<mode>"

68636

- [(set (match_operand:VI 0 "altivec_register_operand" "=v")

68637

- (gt:VI (match_operand:VI 1 "altivec_register_operand" "v")

68638

- (match_operand:VI 2 "altivec_register_operand" "v")))]

68639

- "TARGET_ALTIVEC"

68640

+ [(set (match_operand:VI2 0 "altivec_register_operand" "=v")

68641

+ (gt:VI2 (match_operand:VI2 1 "altivec_register_operand" "v")

68642

+ (match_operand:VI2 2 "altivec_register_operand" "v")))]

68643

+ "<VI_unit>"

68644

"vcmpgts<VI_char> %0,%1,%2"

68645

[(set_attr "type" "veccmp")])

68646

68647

(define_insn "*altivec_gtu<mode>"

68648

- [(set (match_operand:VI 0 "altivec_register_operand" "=v")

68649

- (gtu:VI (match_operand:VI 1 "altivec_register_operand" "v")

68650

- (match_operand:VI 2 "altivec_register_operand" "v")))]

68651

- "TARGET_ALTIVEC"

68652

+ [(set (match_operand:VI2 0 "altivec_register_operand" "=v")

68653

+ (gtu:VI2 (match_operand:VI2 1 "altivec_register_operand" "v")

68654

+ (match_operand:VI2 2 "altivec_register_operand" "v")))]

68655

+ "<VI_unit>"

68656

"vcmpgtu<VI_char> %0,%1,%2"

68657

[(set_attr "type" "veccmp")])

68658

68659

@@ -642,7 +667,7 @@

68660

convert_move (small_swap, swap, 0);

68661

68662

low_product = gen_reg_rtx (V4SImode);

68663

- emit_insn (gen_vec_widen_umult_odd_v8hi (low_product, one, two));

68664

+ emit_insn (gen_altivec_vmulouh (low_product, one, two));

68665

68666

high_product = gen_reg_rtx (V4SImode);

68667

emit_insn (gen_altivec_vmsumuhm (high_product, one, small_swap, zero));

68668

@@ -666,14 +691,23 @@

68669

rtx high = gen_reg_rtx (V4SImode);

68670

rtx low = gen_reg_rtx (V4SImode);

68671

68672

- emit_insn (gen_vec_widen_smult_even_v8hi (even, operands[1], operands[2]));

68673

- emit_insn (gen_vec_widen_smult_odd_v8hi (odd, operands[1], operands[2]));

68674

+ if (BYTES_BIG_ENDIAN)

68675

+ {

68676

+ emit_insn (gen_altivec_vmulesh (even, operands[1], operands[2]));

68677

+ emit_insn (gen_altivec_vmulosh (odd, operands[1], operands[2]));

68678

+ emit_insn (gen_altivec_vmrghw_direct (high, even, odd));

68679

+ emit_insn (gen_altivec_vmrglw_direct (low, even, odd));

68680

+ emit_insn (gen_altivec_vpkuwum_direct (operands[0], high, low));

68681

+ }

68682

+ else

68683

+ {

68684

+ emit_insn (gen_altivec_vmulosh (even, operands[1], operands[2]));

68685

+ emit_insn (gen_altivec_vmulesh (odd, operands[1], operands[2]));

68686

+ emit_insn (gen_altivec_vmrghw_direct (high, odd, even));

68687

+ emit_insn (gen_altivec_vmrglw_direct (low, odd, even));

68688

+ emit_insn (gen_altivec_vpkuwum_direct (operands[0], low, high));

68689

+ }

68690

68691

- emit_insn (gen_altivec_vmrghw (high, even, odd));

68692

- emit_insn (gen_altivec_vmrglw (low, even, odd));

68693

-

68694

- emit_insn (gen_altivec_vpkuwum (operands[0], high, low));

68695

-

68696

DONE;

68697

}")

68698

68699

@@ -744,18 +778,18 @@

68700

;; max

68701

68702

(define_insn "umax<mode>3"

68703

- [(set (match_operand:VI 0 "register_operand" "=v")

68704

- (umax:VI (match_operand:VI 1 "register_operand" "v")

68705

- (match_operand:VI 2 "register_operand" "v")))]

68706

- "TARGET_ALTIVEC"

68707

+ [(set (match_operand:VI2 0 "register_operand" "=v")

68708

+ (umax:VI2 (match_operand:VI2 1 "register_operand" "v")

68709

+ (match_operand:VI2 2 "register_operand" "v")))]

68710

+ "<VI_unit>"

68711

"vmaxu<VI_char> %0,%1,%2"

68712

[(set_attr "type" "vecsimple")])

68713

68714

(define_insn "smax<mode>3"

68715

- [(set (match_operand:VI 0 "register_operand" "=v")

68716

- (smax:VI (match_operand:VI 1 "register_operand" "v")

68717

- (match_operand:VI 2 "register_operand" "v")))]

68718

- "TARGET_ALTIVEC"

68719

+ [(set (match_operand:VI2 0 "register_operand" "=v")

68720

+ (smax:VI2 (match_operand:VI2 1 "register_operand" "v")

68721

+ (match_operand:VI2 2 "register_operand" "v")))]

68722

+ "<VI_unit>"

68723

"vmaxs<VI_char> %0,%1,%2"

68724

[(set_attr "type" "vecsimple")])

68725

68726

@@ -768,18 +802,18 @@

68727

[(set_attr "type" "veccmp")])

68728

68729

(define_insn "umin<mode>3"

68730

- [(set (match_operand:VI 0 "register_operand" "=v")

68731

- (umin:VI (match_operand:VI 1 "register_operand" "v")

68732

- (match_operand:VI 2 "register_operand" "v")))]

68733

- "TARGET_ALTIVEC"

68734

+ [(set (match_operand:VI2 0 "register_operand" "=v")

68735

+ (umin:VI2 (match_operand:VI2 1 "register_operand" "v")

68736

+ (match_operand:VI2 2 "register_operand" "v")))]

68737

+ "<VI_unit>"

68738

"vminu<VI_char> %0,%1,%2"

68739

[(set_attr "type" "vecsimple")])

68740

68741

(define_insn "smin<mode>3"

68742

- [(set (match_operand:VI 0 "register_operand" "=v")

68743

- (smin:VI (match_operand:VI 1 "register_operand" "v")

68744

- (match_operand:VI 2 "register_operand" "v")))]

68745

- "TARGET_ALTIVEC"

68746

+ [(set (match_operand:VI2 0 "register_operand" "=v")

68747

+ (smin:VI2 (match_operand:VI2 1 "register_operand" "v")

68748

+ (match_operand:VI2 2 "register_operand" "v")))]

68749

+ "<VI_unit>"

68750

"vmins<VI_char> %0,%1,%2"

68751

[(set_attr "type" "vecsimple")])

68752

68753

@@ -823,9 +857,41 @@

68754

"vmladduhm %0,%1,%2,%3"

68755

[(set_attr "type" "veccomplex")])

68756

68757

-(define_insn "altivec_vmrghb"

68758

+(define_expand "altivec_vmrghb"

68759

+ [(use (match_operand:V16QI 0 "register_operand" ""))

68760

+ (use (match_operand:V16QI 1 "register_operand" ""))

68761

+ (use (match_operand:V16QI 2 "register_operand" ""))]

68762

+ "TARGET_ALTIVEC"

68763

+{

68764

+ rtvec v;

68765

+ rtx x;

68766

+

68767

+ /* Special handling for LE with -maltivec=be. */

68768

+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)

68769

+ {

68770

+ v = gen_rtvec (16, GEN_INT (8), GEN_INT (24), GEN_INT (9), GEN_INT (25),

68771

+ GEN_INT (10), GEN_INT (26), GEN_INT (11), GEN_INT (27),

68772

+ GEN_INT (12), GEN_INT (28), GEN_INT (13), GEN_INT (29),

68773

+ GEN_INT (14), GEN_INT (30), GEN_INT (15), GEN_INT (31));

68774

+ x = gen_rtx_VEC_CONCAT (V32QImode, operands[2], operands[1]);

68775

+ }

68776

+ else

68777

+ {

68778

+ v = gen_rtvec (16, GEN_INT (0), GEN_INT (16), GEN_INT (1), GEN_INT (17),

68779

+ GEN_INT (2), GEN_INT (18), GEN_INT (3), GEN_INT (19),

68780

+ GEN_INT (4), GEN_INT (20), GEN_INT (5), GEN_INT (21),

68781

+ GEN_INT (6), GEN_INT (22), GEN_INT (7), GEN_INT (23));

68782

+ x = gen_rtx_VEC_CONCAT (V32QImode, operands[1], operands[2]);

68783

+ }

68784

+

68785

+ x = gen_rtx_VEC_SELECT (V16QImode, x, gen_rtx_PARALLEL (VOIDmode, v));

68786

+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));

68787

+ DONE;

68788

+})

68789

+

68790

+(define_insn "*altivec_vmrghb_internal"

68791

[(set (match_operand:V16QI 0 "register_operand" "=v")

68792

- (vec_select:V16QI

68793

+ (vec_select:V16QI

68794

(vec_concat:V32QI

68795

(match_operand:V16QI 1 "register_operand" "v")

68796

(match_operand:V16QI 2 "register_operand" "v"))

68797

@@ -838,12 +904,54 @@

68798

(const_int 6) (const_int 22)

68799

(const_int 7) (const_int 23)])))]

68800

"TARGET_ALTIVEC"

68801

+{

68802

+ if (BYTES_BIG_ENDIAN)

68803

+ return "vmrghb %0,%1,%2";

68804

+ else

68805

+ return "vmrglb %0,%2,%1";

68806

+}

68807

+ [(set_attr "type" "vecperm")])

68808

+

68809

+(define_insn "altivec_vmrghb_direct"

68810

+ [(set (match_operand:V16QI 0 "register_operand" "=v")

68811

+ (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")

68812

+ (match_operand:V16QI 2 "register_operand" "v")]

68813

+ UNSPEC_VMRGH_DIRECT))]

68814

+ "TARGET_ALTIVEC"

68815

"vmrghb %0,%1,%2"

68816

[(set_attr "type" "vecperm")])

68817

68818

-(define_insn "altivec_vmrghh"

68819

+(define_expand "altivec_vmrghh"

68820

+ [(use (match_operand:V8HI 0 "register_operand" ""))

68821

+ (use (match_operand:V8HI 1 "register_operand" ""))

68822

+ (use (match_operand:V8HI 2 "register_operand" ""))]

68823

+ "TARGET_ALTIVEC"

68824

+{

68825

+ rtvec v;

68826

+ rtx x;

68827

+

68828

+ /* Special handling for LE with -maltivec=be. */

68829

+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)

68830

+ {

68831

+ v = gen_rtvec (8, GEN_INT (4), GEN_INT (12), GEN_INT (5), GEN_INT (13),

68832

+ GEN_INT (6), GEN_INT (14), GEN_INT (7), GEN_INT (15));

68833

+ x = gen_rtx_VEC_CONCAT (V16HImode, operands[2], operands[1]);

68834

+ }

68835

+ else

68836

+ {

68837

+ v = gen_rtvec (8, GEN_INT (0), GEN_INT (8), GEN_INT (1), GEN_INT (9),

68838

+ GEN_INT (2), GEN_INT (10), GEN_INT (3), GEN_INT (11));

68839

+ x = gen_rtx_VEC_CONCAT (V16HImode, operands[1], operands[2]);

68840

+ }

68841

+

68842

+ x = gen_rtx_VEC_SELECT (V8HImode, x, gen_rtx_PARALLEL (VOIDmode, v));

68843

+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));

68844

+ DONE;

68845

+})

68846

+

68847

+(define_insn "*altivec_vmrghh_internal"

68848

[(set (match_operand:V8HI 0 "register_operand" "=v")

68849

- (vec_select:V8HI

68850

+ (vec_select:V8HI

68851

(vec_concat:V16HI

68852

(match_operand:V8HI 1 "register_operand" "v")

68853

(match_operand:V8HI 2 "register_operand" "v"))

68854

@@ -852,10 +960,50 @@

68855

(const_int 2) (const_int 10)

68856

(const_int 3) (const_int 11)])))]

68857

"TARGET_ALTIVEC"

68858

+{

68859

+ if (BYTES_BIG_ENDIAN)

68860

+ return "vmrghh %0,%1,%2";

68861

+ else

68862

+ return "vmrglh %0,%2,%1";

68863

+}

68864

+ [(set_attr "type" "vecperm")])

68865

+

68866

+(define_insn "altivec_vmrghh_direct"

68867

+ [(set (match_operand:V8HI 0 "register_operand" "=v")

68868

+ (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")

68869

+ (match_operand:V8HI 2 "register_operand" "v")]

68870

+ UNSPEC_VMRGH_DIRECT))]

68871

+ "TARGET_ALTIVEC"

68872

"vmrghh %0,%1,%2"

68873

[(set_attr "type" "vecperm")])

68874

68875

-(define_insn "altivec_vmrghw"

68876

+(define_expand "altivec_vmrghw"

68877

+ [(use (match_operand:V4SI 0 "register_operand" ""))

68878

+ (use (match_operand:V4SI 1 "register_operand" ""))

68879

+ (use (match_operand:V4SI 2 "register_operand" ""))]

68880

+ "VECTOR_MEM_ALTIVEC_P (V4SImode)"

68881

+{

68882

+ rtvec v;

68883

+ rtx x;

68884

+

68885

+ /* Special handling for LE with -maltivec=be. */

68886

+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)

68887

+ {

68888

+ v = gen_rtvec (4, GEN_INT (2), GEN_INT (6), GEN_INT (3), GEN_INT (7));

68889

+ x = gen_rtx_VEC_CONCAT (V8SImode, operands[2], operands[1]);

68890

+ }

68891

+ else

68892

+ {

68893

+ v = gen_rtvec (4, GEN_INT (0), GEN_INT (4), GEN_INT (1), GEN_INT (5));

68894

+ x = gen_rtx_VEC_CONCAT (V8SImode, operands[1], operands[2]);

68895

+ }

68896

+

68897

+ x = gen_rtx_VEC_SELECT (V4SImode, x, gen_rtx_PARALLEL (VOIDmode, v));

68898

+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));

68899

+ DONE;

68900

+})

68901

+

68902

+(define_insn "*altivec_vmrghw_internal"

68903

[(set (match_operand:V4SI 0 "register_operand" "=v")

68904

(vec_select:V4SI

68905

(vec_concat:V8SI

68906

@@ -864,6 +1012,20 @@

68907

(parallel [(const_int 0) (const_int 4)

68908

(const_int 1) (const_int 5)])))]

68909

"VECTOR_MEM_ALTIVEC_P (V4SImode)"

68910

+{

68911

+ if (BYTES_BIG_ENDIAN)

68912

+ return "vmrghw %0,%1,%2";

68913

+ else

68914

+ return "vmrglw %0,%2,%1";

68915

+}

68916

+ [(set_attr "type" "vecperm")])

68917

+

68918

+(define_insn "altivec_vmrghw_direct"

68919

+ [(set (match_operand:V4SI 0 "register_operand" "=v")

68920

+ (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")

68921

+ (match_operand:V4SI 2 "register_operand" "v")]

68922

+ UNSPEC_VMRGH_DIRECT))]

68923

+ "TARGET_ALTIVEC"

68924

"vmrghw %0,%1,%2"

68925

[(set_attr "type" "vecperm")])

68926

68927

@@ -876,10 +1038,47 @@

68928

(parallel [(const_int 0) (const_int 4)

68929

(const_int 1) (const_int 5)])))]

68930

"VECTOR_MEM_ALTIVEC_P (V4SFmode)"

68931

- "vmrghw %0,%1,%2"

68932

+{

68933

+ if (BYTES_BIG_ENDIAN)

68934

+ return "vmrghw %0,%1,%2";

68935

+ else

68936

+ return "vmrglw %0,%2,%1";

68937

+}

68938

[(set_attr "type" "vecperm")])

68939

68940

-(define_insn "altivec_vmrglb"

68941

+(define_expand "altivec_vmrglb"

68942

+ [(use (match_operand:V16QI 0 "register_operand" ""))

68943

+ (use (match_operand:V16QI 1 "register_operand" ""))

68944

+ (use (match_operand:V16QI 2 "register_operand" ""))]

68945

+ "TARGET_ALTIVEC"

68946

+{

68947

+ rtvec v;

68948

+ rtx x;

68949

+

68950

+ /* Special handling for LE with -maltivec=be. */

68951

+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)

68952

+ {

68953

+ v = gen_rtvec (16, GEN_INT (0), GEN_INT (16), GEN_INT (1), GEN_INT (17),

68954

+ GEN_INT (2), GEN_INT (18), GEN_INT (3), GEN_INT (19),

68955

+ GEN_INT (4), GEN_INT (20), GEN_INT (5), GEN_INT (21),

68956

+ GEN_INT (6), GEN_INT (22), GEN_INT (7), GEN_INT (23));

68957

+ x = gen_rtx_VEC_CONCAT (V32QImode, operands[2], operands[1]);

68958

+ }

68959

+ else

68960

+ {

68961

+ v = gen_rtvec (16, GEN_INT (8), GEN_INT (24), GEN_INT (9), GEN_INT (25),

68962

+ GEN_INT (10), GEN_INT (26), GEN_INT (11), GEN_INT (27),

68963

+ GEN_INT (12), GEN_INT (28), GEN_INT (13), GEN_INT (29),

68964

+ GEN_INT (14), GEN_INT (30), GEN_INT (15), GEN_INT (31));

68965

+ x = gen_rtx_VEC_CONCAT (V32QImode, operands[1], operands[2]);

68966

+ }

68967

+

68968

+ x = gen_rtx_VEC_SELECT (V16QImode, x, gen_rtx_PARALLEL (VOIDmode, v));

68969

+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));

68970

+ DONE;

68971

+})

68972

+

68973

+(define_insn "*altivec_vmrglb_internal"

68974

[(set (match_operand:V16QI 0 "register_operand" "=v")

68975

(vec_select:V16QI

68976

(vec_concat:V32QI

68977

@@ -894,10 +1093,52 @@

68978

(const_int 14) (const_int 30)

68979

(const_int 15) (const_int 31)])))]

68980

"TARGET_ALTIVEC"

68981

+{

68982

+ if (BYTES_BIG_ENDIAN)

68983

+ return "vmrglb %0,%1,%2";

68984

+ else

68985

+ return "vmrghb %0,%2,%1";

68986

+}

68987

+ [(set_attr "type" "vecperm")])

68988

+

68989

+(define_insn "altivec_vmrglb_direct"

68990

+ [(set (match_operand:V16QI 0 "register_operand" "=v")

68991

+ (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")

68992

+ (match_operand:V16QI 2 "register_operand" "v")]

68993

+ UNSPEC_VMRGL_DIRECT))]

68994

+ "TARGET_ALTIVEC"

68995

"vmrglb %0,%1,%2"

68996

[(set_attr "type" "vecperm")])

68997

68998

-(define_insn "altivec_vmrglh"

68999

+(define_expand "altivec_vmrglh"

69000

+ [(use (match_operand:V8HI 0 "register_operand" ""))

69001

+ (use (match_operand:V8HI 1 "register_operand" ""))

69002

+ (use (match_operand:V8HI 2 "register_operand" ""))]

69003

+ "TARGET_ALTIVEC"

69004

+{

69005

+ rtvec v;

69006

+ rtx x;

69007

+

69008

+ /* Special handling for LE with -maltivec=be. */

69009

+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)

69010

+ {

69011

+ v = gen_rtvec (8, GEN_INT (0), GEN_INT (8), GEN_INT (1), GEN_INT (9),

69012

+ GEN_INT (2), GEN_INT (10), GEN_INT (3), GEN_INT (11));

69013

+ x = gen_rtx_VEC_CONCAT (V16HImode, operands[2], operands[1]);

69014

+ }

69015

+ else

69016

+ {

69017

+ v = gen_rtvec (8, GEN_INT (4), GEN_INT (12), GEN_INT (5), GEN_INT (13),

69018

+ GEN_INT (6), GEN_INT (14), GEN_INT (7), GEN_INT (15));

69019

+ x = gen_rtx_VEC_CONCAT (V16HImode, operands[1], operands[2]);

69020

+ }

69021

+

69022

+ x = gen_rtx_VEC_SELECT (V8HImode, x, gen_rtx_PARALLEL (VOIDmode, v));

69023

+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));

69024

+ DONE;

69025

+})

69026

+

69027

+(define_insn "*altivec_vmrglh_internal"

69028

[(set (match_operand:V8HI 0 "register_operand" "=v")

69029

(vec_select:V8HI

69030

(vec_concat:V16HI

69031

@@ -908,10 +1149,50 @@

69032

(const_int 6) (const_int 14)

69033

(const_int 7) (const_int 15)])))]

69034

"TARGET_ALTIVEC"

69035

+{

69036

+ if (BYTES_BIG_ENDIAN)

69037

+ return "vmrglh %0,%1,%2";

69038

+ else

69039

+ return "vmrghh %0,%2,%1";

69040

+}

69041

+ [(set_attr "type" "vecperm")])

69042

+

69043

+(define_insn "altivec_vmrglh_direct"

69044

+ [(set (match_operand:V8HI 0 "register_operand" "=v")

69045

+ (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")

69046

+ (match_operand:V8HI 2 "register_operand" "v")]

69047

+ UNSPEC_VMRGL_DIRECT))]

69048

+ "TARGET_ALTIVEC"

69049

"vmrglh %0,%1,%2"

69050

[(set_attr "type" "vecperm")])

69051

69052

-(define_insn "altivec_vmrglw"

69053

+(define_expand "altivec_vmrglw"

69054

+ [(use (match_operand:V4SI 0 "register_operand" ""))

69055

+ (use (match_operand:V4SI 1 "register_operand" ""))

69056

+ (use (match_operand:V4SI 2 "register_operand" ""))]

69057

+ "VECTOR_MEM_ALTIVEC_P (V4SImode)"

69058

+{

69059

+ rtvec v;

69060

+ rtx x;

69061

+

69062

+ /* Special handling for LE with -maltivec=be. */

69063

+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)

69064

+ {

69065

+ v = gen_rtvec (4, GEN_INT (0), GEN_INT (4), GEN_INT (1), GEN_INT (5));

69066

+ x = gen_rtx_VEC_CONCAT (V8SImode, operands[2], operands[1]);

69067

+ }

69068

+ else

69069

+ {

69070

+ v = gen_rtvec (4, GEN_INT (2), GEN_INT (6), GEN_INT (3), GEN_INT (7));

69071

+ x = gen_rtx_VEC_CONCAT (V8SImode, operands[1], operands[2]);

69072

+ }

69073

+

69074

+ x = gen_rtx_VEC_SELECT (V4SImode, x, gen_rtx_PARALLEL (VOIDmode, v));

69075

+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));

69076

+ DONE;

69077

+})

69078

+

69079

+(define_insn "*altivec_vmrglw_internal"

69080

[(set (match_operand:V4SI 0 "register_operand" "=v")

69081

(vec_select:V4SI

69082

(vec_concat:V8SI

69083

@@ -920,6 +1201,20 @@

69084

(parallel [(const_int 2) (const_int 6)

69085

(const_int 3) (const_int 7)])))]

69086

"VECTOR_MEM_ALTIVEC_P (V4SImode)"

69087

+{

69088

+ if (BYTES_BIG_ENDIAN)

69089

+ return "vmrglw %0,%1,%2";

69090

+ else

69091

+ return "vmrghw %0,%2,%1";

69092

+}

69093

+ [(set_attr "type" "vecperm")])

69094

+

69095

+(define_insn "altivec_vmrglw_direct"

69096

+ [(set (match_operand:V4SI 0 "register_operand" "=v")

69097

+ (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")

69098

+ (match_operand:V4SI 2 "register_operand" "v")]

69099

+ UNSPEC_VMRGL_DIRECT))]

69100

+ "TARGET_ALTIVEC"

69101

"vmrglw %0,%1,%2"

69102

[(set_attr "type" "vecperm")])

69103

69104

@@ -932,10 +1227,154 @@

69105

(parallel [(const_int 2) (const_int 6)

69106

(const_int 3) (const_int 7)])))]

69107

"VECTOR_MEM_ALTIVEC_P (V4SFmode)"

69108

- "vmrglw %0,%1,%2"

69109

+{

69110

+ if (BYTES_BIG_ENDIAN)

69111

+ return "vmrglw %0,%1,%2";

69112

+ else

69113

+ return "vmrghw %0,%2,%1";

69114

+}

69115

[(set_attr "type" "vecperm")])

69116

69117

-(define_insn "vec_widen_umult_even_v16qi"

69118

+;; Power8 vector merge even/odd

69119

+(define_insn "p8_vmrgew"

69120

+ [(set (match_operand:V4SI 0 "register_operand" "=v")

69121

+ (vec_select:V4SI

69122

+ (vec_concat:V8SI

69123

+ (match_operand:V4SI 1 "register_operand" "v")

69124

+ (match_operand:V4SI 2 "register_operand" "v"))

69125

+ (parallel [(const_int 0) (const_int 4)

69126

+ (const_int 2) (const_int 6)])))]

69127

+ "TARGET_P8_VECTOR"

69128

+{

69129

+ if (BYTES_BIG_ENDIAN)

69130

+ return "vmrgew %0,%1,%2";

69131

+ else

69132

+ return "vmrgow %0,%2,%1";

69133

+}

69134

+ [(set_attr "type" "vecperm")])

69135

+

69136

+(define_insn "p8_vmrgow"

69137

+ [(set (match_operand:V4SI 0 "register_operand" "=v")

69138

+ (vec_select:V4SI

69139

+ (vec_concat:V8SI

69140

+ (match_operand:V4SI 1 "register_operand" "v")

69141

+ (match_operand:V4SI 2 "register_operand" "v"))

69142

+ (parallel [(const_int 1) (const_int 5)

69143

+ (const_int 3) (const_int 7)])))]

69144

+ "TARGET_P8_VECTOR"

69145

+{

69146

+ if (BYTES_BIG_ENDIAN)

69147

+ return "vmrgow %0,%1,%2";

69148

+ else

69149

+ return "vmrgew %0,%2,%1";

69150

+}

69151

+ [(set_attr "type" "vecperm")])

69152

+

69153

+(define_expand "vec_widen_umult_even_v16qi"

69154

+ [(use (match_operand:V8HI 0 "register_operand" ""))

69155

+ (use (match_operand:V16QI 1 "register_operand" ""))

69156

+ (use (match_operand:V16QI 2 "register_operand" ""))]

69157

+ "TARGET_ALTIVEC"

69158

+{

69159

+ if (VECTOR_ELT_ORDER_BIG)

69160

+ emit_insn (gen_altivec_vmuleub (operands[0], operands[1], operands[2]));

69161

+ else

69162

+ emit_insn (gen_altivec_vmuloub (operands[0], operands[1], operands[2]));

69163

+ DONE;

69164

+})

69165

+

69166

+(define_expand "vec_widen_smult_even_v16qi"

69167

+ [(use (match_operand:V8HI 0 "register_operand" ""))

69168

+ (use (match_operand:V16QI 1 "register_operand" ""))

69169

+ (use (match_operand:V16QI 2 "register_operand" ""))]

69170

+ "TARGET_ALTIVEC"

69171

+{

69172

+ if (VECTOR_ELT_ORDER_BIG)

69173

+ emit_insn (gen_altivec_vmulesb (operands[0], operands[1], operands[2]));

69174

+ else

69175

+ emit_insn (gen_altivec_vmulosb (operands[0], operands[1], operands[2]));

69176

+ DONE;

69177

+})

69178

+

69179

+(define_expand "vec_widen_umult_even_v8hi"

69180

+ [(use (match_operand:V4SI 0 "register_operand" ""))

69181

+ (use (match_operand:V8HI 1 "register_operand" ""))

69182

+ (use (match_operand:V8HI 2 "register_operand" ""))]

69183

+ "TARGET_ALTIVEC"

69184

+{

69185

+ if (VECTOR_ELT_ORDER_BIG)

69186

+ emit_insn (gen_altivec_vmuleuh (operands[0], operands[1], operands[2]));

69187

+ else

69188

+ emit_insn (gen_altivec_vmulouh (operands[0], operands[1], operands[2]));

69189

+ DONE;

69190

+})

69191

+

69192

+(define_expand "vec_widen_smult_even_v8hi"

69193

+ [(use (match_operand:V4SI 0 "register_operand" ""))

69194

+ (use (match_operand:V8HI 1 "register_operand" ""))

69195

+ (use (match_operand:V8HI 2 "register_operand" ""))]

69196

+ "TARGET_ALTIVEC"

69197

+{

69198

+ if (VECTOR_ELT_ORDER_BIG)

69199

+ emit_insn (gen_altivec_vmulesh (operands[0], operands[1], operands[2]));

69200

+ else

69201

+ emit_insn (gen_altivec_vmulosh (operands[0], operands[1], operands[2]));

69202

+ DONE;

69203

+})

69204

+

69205

+(define_expand "vec_widen_umult_odd_v16qi"

69206

+ [(use (match_operand:V8HI 0 "register_operand" ""))

69207

+ (use (match_operand:V16QI 1 "register_operand" ""))

69208

+ (use (match_operand:V16QI 2 "register_operand" ""))]

69209

+ "TARGET_ALTIVEC"

69210

+{

69211

+ if (VECTOR_ELT_ORDER_BIG)

69212

+ emit_insn (gen_altivec_vmuloub (operands[0], operands[1], operands[2]));

69213

+ else

69214

+ emit_insn (gen_altivec_vmuleub (operands[0], operands[1], operands[2]));

69215

+ DONE;

69216

+})

69217

+

69218

+(define_expand "vec_widen_smult_odd_v16qi"

69219

+ [(use (match_operand:V8HI 0 "register_operand" ""))

69220

+ (use (match_operand:V16QI 1 "register_operand" ""))

69221

+ (use (match_operand:V16QI 2 "register_operand" ""))]

69222

+ "TARGET_ALTIVEC"

69223

+{

69224

+ if (VECTOR_ELT_ORDER_BIG)

69225

+ emit_insn (gen_altivec_vmulosb (operands[0], operands[1], operands[2]));

69226

+ else

69227

+ emit_insn (gen_altivec_vmulesb (operands[0], operands[1], operands[2]));

69228

+ DONE;

69229

+})

69230

+

69231

+(define_expand "vec_widen_umult_odd_v8hi"

69232

+ [(use (match_operand:V4SI 0 "register_operand" ""))

69233

+ (use (match_operand:V8HI 1 "register_operand" ""))

69234

+ (use (match_operand:V8HI 2 "register_operand" ""))]

69235

+ "TARGET_ALTIVEC"

69236

+{

69237

+ if (VECTOR_ELT_ORDER_BIG)

69238

+ emit_insn (gen_altivec_vmulouh (operands[0], operands[1], operands[2]));

69239

+ else

69240

+ emit_insn (gen_altivec_vmuleuh (operands[0], operands[1], operands[2]));

69241

+ DONE;

69242

+})

69243

+

69244

+(define_expand "vec_widen_smult_odd_v8hi"

69245

+ [(use (match_operand:V4SI 0 "register_operand" ""))

69246

+ (use (match_operand:V8HI 1 "register_operand" ""))

69247

+ (use (match_operand:V8HI 2 "register_operand" ""))]

69248

+ "TARGET_ALTIVEC"

69249

+{

69250

+ if (VECTOR_ELT_ORDER_BIG)

69251

+ emit_insn (gen_altivec_vmulosh (operands[0], operands[1], operands[2]));

69252

+ else

69253

+ emit_insn (gen_altivec_vmulesh (operands[0], operands[1], operands[2]));

69254

+ DONE;

69255

+})

69256

+

69257

+(define_insn "altivec_vmuleub"

69258

[(set (match_operand:V8HI 0 "register_operand" "=v")

69259

(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")

69260

(match_operand:V16QI 2 "register_operand" "v")]

69261

@@ -944,43 +1383,25 @@

69262

"vmuleub %0,%1,%2"

69263

[(set_attr "type" "veccomplex")])

69264

69265

-(define_insn "vec_widen_smult_even_v16qi"

69266

+(define_insn "altivec_vmuloub"

69267

[(set (match_operand:V8HI 0 "register_operand" "=v")

69268

(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")

69269

(match_operand:V16QI 2 "register_operand" "v")]

69270

- UNSPEC_VMULESB))]

69271

+ UNSPEC_VMULOUB))]

69272

"TARGET_ALTIVEC"

69273

- "vmulesb %0,%1,%2"

69274

+ "vmuloub %0,%1,%2"

69275

[(set_attr "type" "veccomplex")])

69276

69277

-(define_insn "vec_widen_umult_even_v8hi"

69278

- [(set (match_operand:V4SI 0 "register_operand" "=v")

69279

- (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")

69280

- (match_operand:V8HI 2 "register_operand" "v")]

69281

- UNSPEC_VMULEUH))]

69282

- "TARGET_ALTIVEC"

69283

- "vmuleuh %0,%1,%2"

69284

- [(set_attr "type" "veccomplex")])

69285

-

69286

-(define_insn "vec_widen_smult_even_v8hi"

69287

- [(set (match_operand:V4SI 0 "register_operand" "=v")

69288

- (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")

69289

- (match_operand:V8HI 2 "register_operand" "v")]

69290

- UNSPEC_VMULESH))]

69291

- "TARGET_ALTIVEC"

69292

- "vmulesh %0,%1,%2"

69293

- [(set_attr "type" "veccomplex")])

69294

-

69295

-(define_insn "vec_widen_umult_odd_v16qi"

69296

+(define_insn "altivec_vmulesb"

69297

[(set (match_operand:V8HI 0 "register_operand" "=v")

69298

(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")

69299

(match_operand:V16QI 2 "register_operand" "v")]

69300

- UNSPEC_VMULOUB))]

69301

+ UNSPEC_VMULESB))]

69302

"TARGET_ALTIVEC"

69303

- "vmuloub %0,%1,%2"

69304

+ "vmulesb %0,%1,%2"

69305

[(set_attr "type" "veccomplex")])

69306

69307

-(define_insn "vec_widen_smult_odd_v16qi"

69308

+(define_insn "altivec_vmulosb"

69309

[(set (match_operand:V8HI 0 "register_operand" "=v")

69310

(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")

69311

(match_operand:V16QI 2 "register_operand" "v")]

69312

@@ -989,19 +1410,37 @@

69313

"vmulosb %0,%1,%2"

69314

[(set_attr "type" "veccomplex")])

69315

69316

-(define_insn "vec_widen_umult_odd_v8hi"

69317

+(define_insn "altivec_vmuleuh"

69318

[(set (match_operand:V4SI 0 "register_operand" "=v")

69319

(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")

69320

(match_operand:V8HI 2 "register_operand" "v")]

69321

+ UNSPEC_VMULEUH))]

69322

+ "TARGET_ALTIVEC"

69323

+ "vmuleuh %0,%1,%2"

69324

+ [(set_attr "type" "veccomplex")])

69325

+

69326

+(define_insn "altivec_vmulouh"

69327

+ [(set (match_operand:V4SI 0 "register_operand" "=v")

69328

+ (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")

69329

+ (match_operand:V8HI 2 "register_operand" "v")]

69330

UNSPEC_VMULOUH))]

69331

"TARGET_ALTIVEC"

69332

"vmulouh %0,%1,%2"

69333

[(set_attr "type" "veccomplex")])

69334

69335

-(define_insn "vec_widen_smult_odd_v8hi"

69336

+(define_insn "altivec_vmulesh"

69337

[(set (match_operand:V4SI 0 "register_operand" "=v")

69338

(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")

69339

(match_operand:V8HI 2 "register_operand" "v")]

69340

+ UNSPEC_VMULESH))]

69341

+ "TARGET_ALTIVEC"

69342

+ "vmulesh %0,%1,%2"

69343

+ [(set_attr "type" "veccomplex")])

69344

+

69345

+(define_insn "altivec_vmulosh"

69346

+ [(set (match_operand:V4SI 0 "register_operand" "=v")

69347

+ (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")

69348

+ (match_operand:V8HI 2 "register_operand" "v")]

69349

UNSPEC_VMULOSH))]

69350

"TARGET_ALTIVEC"

69351

"vmulosh %0,%1,%2"

69352

@@ -1008,74 +1447,7 @@

69353

[(set_attr "type" "veccomplex")])

69354

69355

69356

-;; logical ops. Have the logical ops follow the memory ops in

69357

-;; terms of whether to prefer VSX or Altivec

69358

-

69359

-(define_insn "*altivec_and<mode>3"

69360

- [(set (match_operand:VM 0 "register_operand" "=v")

69361

- (and:VM (match_operand:VM 1 "register_operand" "v")

69362

- (match_operand:VM 2 "register_operand" "v")))]

69363

- "VECTOR_MEM_ALTIVEC_P (<MODE>mode)"

69364

- "vand %0,%1,%2"

69365

- [(set_attr "type" "vecsimple")])

69366

-

69367

-(define_insn "*altivec_ior<mode>3"

69368

- [(set (match_operand:VM 0 "register_operand" "=v")

69369

- (ior:VM (match_operand:VM 1 "register_operand" "v")

69370

- (match_operand:VM 2 "register_operand" "v")))]

69371

- "VECTOR_MEM_ALTIVEC_P (<MODE>mode)"

69372

- "vor %0,%1,%2"

69373

- [(set_attr "type" "vecsimple")])

69374

-

69375

-(define_insn "*altivec_xor<mode>3"

69376

- [(set (match_operand:VM 0 "register_operand" "=v")

69377

- (xor:VM (match_operand:VM 1 "register_operand" "v")

69378

- (match_operand:VM 2 "register_operand" "v")))]

69379

- "VECTOR_MEM_ALTIVEC_P (<MODE>mode)"

69380

- "vxor %0,%1,%2"

69381

- [(set_attr "type" "vecsimple")])

69382

-

69383

-(define_insn "*altivec_one_cmpl<mode>2"

69384

- [(set (match_operand:VM 0 "register_operand" "=v")

69385

- (not:VM (match_operand:VM 1 "register_operand" "v")))]

69386

- "VECTOR_MEM_ALTIVEC_P (<MODE>mode)"

69387

- "vnor %0,%1,%1"

69388

- [(set_attr "type" "vecsimple")])

69389

-

69390

-(define_insn "*altivec_nor<mode>3"

69391

- [(set (match_operand:VM 0 "register_operand" "=v")

69392

- (not:VM (ior:VM (match_operand:VM 1 "register_operand" "v")

69393

- (match_operand:VM 2 "register_operand" "v"))))]

69394

- "VECTOR_MEM_ALTIVEC_P (<MODE>mode)"

69395

- "vnor %0,%1,%2"

69396

- [(set_attr "type" "vecsimple")])

69397

-

69398

-(define_insn "*altivec_andc<mode>3"

69399

- [(set (match_operand:VM 0 "register_operand" "=v")

69400

- (and:VM (not:VM (match_operand:VM 2 "register_operand" "v"))

69401

- (match_operand:VM 1 "register_operand" "v")))]

69402

- "VECTOR_MEM_ALTIVEC_P (<MODE>mode)"

69403

- "vandc %0,%1,%2"

69404

- [(set_attr "type" "vecsimple")])

69405

-

69406

-(define_insn "altivec_vpkuhum"

69407

- [(set (match_operand:V16QI 0 "register_operand" "=v")

69408

- (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")

69409

- (match_operand:V8HI 2 "register_operand" "v")]

69410

- UNSPEC_VPKUHUM))]

69411

- "TARGET_ALTIVEC"

69412

- "vpkuhum %0,%1,%2"

69413

- [(set_attr "type" "vecperm")])

69414

-

69415

-(define_insn "altivec_vpkuwum"

69416

- [(set (match_operand:V8HI 0 "register_operand" "=v")

69417

- (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")

69418

- (match_operand:V4SI 2 "register_operand" "v")]

69419

- UNSPEC_VPKUWUM))]

69420

- "TARGET_ALTIVEC"

69421

- "vpkuwum %0,%1,%2"

69422

- [(set_attr "type" "vecperm")])

69423

-

69424

+;; Vector pack/unpack

69425

(define_insn "altivec_vpkpx"

69426

[(set (match_operand:V8HI 0 "register_operand" "=v")

69427

(unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")

69428

@@ -1082,74 +1454,95 @@

69429

(match_operand:V4SI 2 "register_operand" "v")]

69430

UNSPEC_VPKPX))]

69431

"TARGET_ALTIVEC"

69432

- "vpkpx %0,%1,%2"

69433

+ "*

69434

+ {

69435

+ if (VECTOR_ELT_ORDER_BIG)

69436

+ return \"vpkpx %0,%1,%2\";

69437

+ else

69438

+ return \"vpkpx %0,%2,%1\";

69439

+ }"

69440

[(set_attr "type" "vecperm")])

69441

69442

-(define_insn "altivec_vpkshss"

69443

- [(set (match_operand:V16QI 0 "register_operand" "=v")

69444

- (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")

69445

- (match_operand:V8HI 2 "register_operand" "v")]

69446

- UNSPEC_VPKSHSS))

69447

- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]

69448

- "TARGET_ALTIVEC"

69449

- "vpkshss %0,%1,%2"

69450

+(define_insn "altivec_vpks<VI_char>ss"

69451

+ [(set (match_operand:<VP_small> 0 "register_operand" "=v")

69452

+ (unspec:<VP_small> [(match_operand:VP 1 "register_operand" "v")

69453

+ (match_operand:VP 2 "register_operand" "v")]

69454

+ UNSPEC_VPACK_SIGN_SIGN_SAT))]

69455

+ "<VI_unit>"

69456

+ "*

69457

+ {

69458

+ if (VECTOR_ELT_ORDER_BIG)

69459

+ return \"vpks<VI_char>ss %0,%1,%2\";

69460

+ else

69461

+ return \"vpks<VI_char>ss %0,%2,%1\";

69462

+ }"

69463

[(set_attr "type" "vecperm")])

69464

69465

-(define_insn "altivec_vpkswss"

69466

- [(set (match_operand:V8HI 0 "register_operand" "=v")

69467

- (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")

69468

- (match_operand:V4SI 2 "register_operand" "v")]

69469

- UNSPEC_VPKSWSS))

69470

- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]

69471

- "TARGET_ALTIVEC"

69472

- "vpkswss %0,%1,%2"

69473

+(define_insn "altivec_vpks<VI_char>us"

69474

+ [(set (match_operand:<VP_small> 0 "register_operand" "=v")

69475

+ (unspec:<VP_small> [(match_operand:VP 1 "register_operand" "v")

69476

+ (match_operand:VP 2 "register_operand" "v")]

69477

+ UNSPEC_VPACK_SIGN_UNS_SAT))]

69478

+ "<VI_unit>"

69479

+ "*

69480

+ {

69481

+ if (VECTOR_ELT_ORDER_BIG)

69482

+ return \"vpks<VI_char>us %0,%1,%2\";

69483

+ else

69484

+ return \"vpks<VI_char>us %0,%2,%1\";

69485

+ }"

69486

[(set_attr "type" "vecperm")])

69487

69488

-(define_insn "altivec_vpkuhus"

69489

- [(set (match_operand:V16QI 0 "register_operand" "=v")

69490

- (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")

69491

- (match_operand:V8HI 2 "register_operand" "v")]

69492

- UNSPEC_VPKUHUS))

69493

- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]

69494

- "TARGET_ALTIVEC"

69495

- "vpkuhus %0,%1,%2"

69496

+(define_insn "altivec_vpku<VI_char>us"

69497

+ [(set (match_operand:<VP_small> 0 "register_operand" "=v")

69498

+ (unspec:<VP_small> [(match_operand:VP 1 "register_operand" "v")

69499

+ (match_operand:VP 2 "register_operand" "v")]

69500

+ UNSPEC_VPACK_UNS_UNS_SAT))]

69501

+ "<VI_unit>"

69502

+ "*

69503

+ {

69504

+ if (VECTOR_ELT_ORDER_BIG)

69505

+ return \"vpku<VI_char>us %0,%1,%2\";

69506

+ else

69507

+ return \"vpku<VI_char>us %0,%2,%1\";

69508

+ }"

69509

[(set_attr "type" "vecperm")])

69510

69511

-(define_insn "altivec_vpkshus"

69512

- [(set (match_operand:V16QI 0 "register_operand" "=v")

69513

- (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")

69514

- (match_operand:V8HI 2 "register_operand" "v")]

69515

- UNSPEC_VPKSHUS))

69516

- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]

69517

- "TARGET_ALTIVEC"

69518

- "vpkshus %0,%1,%2"

69519

+(define_insn "altivec_vpku<VI_char>um"

69520

+ [(set (match_operand:<VP_small> 0 "register_operand" "=v")

69521

+ (unspec:<VP_small> [(match_operand:VP 1 "register_operand" "v")

69522

+ (match_operand:VP 2 "register_operand" "v")]

69523

+ UNSPEC_VPACK_UNS_UNS_MOD))]

69524

+ "<VI_unit>"

69525

+ "*

69526

+ {

69527

+ if (VECTOR_ELT_ORDER_BIG)

69528

+ return \"vpku<VI_char>um %0,%1,%2\";

69529

+ else

69530

+ return \"vpku<VI_char>um %0,%2,%1\";

69531

+ }"

69532

[(set_attr "type" "vecperm")])

69533

69534

-(define_insn "altivec_vpkuwus"

69535

- [(set (match_operand:V8HI 0 "register_operand" "=v")

69536

- (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")

69537

- (match_operand:V4SI 2 "register_operand" "v")]

69538

- UNSPEC_VPKUWUS))

69539

- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]

69540

- "TARGET_ALTIVEC"

69541

- "vpkuwus %0,%1,%2"

69542

+(define_insn "altivec_vpku<VI_char>um_direct"

69543

+ [(set (match_operand:<VP_small> 0 "register_operand" "=v")

69544

+ (unspec:<VP_small> [(match_operand:VP 1 "register_operand" "v")

69545

+ (match_operand:VP 2 "register_operand" "v")]

69546

+ UNSPEC_VPACK_UNS_UNS_MOD_DIRECT))]

69547

+ "<VI_unit>"

69548

+ "*

69549

+ {

69550

+ if (BYTES_BIG_ENDIAN)

69551

+ return \"vpku<VI_char>um %0,%1,%2\";

69552

+ else

69553

+ return \"vpku<VI_char>um %0,%2,%1\";

69554

+ }"

69555

[(set_attr "type" "vecperm")])

69556

69557

-(define_insn "altivec_vpkswus"

69558

- [(set (match_operand:V8HI 0 "register_operand" "=v")

69559

- (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")

69560

- (match_operand:V4SI 2 "register_operand" "v")]

69561

- UNSPEC_VPKSWUS))

69562

- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]

69563

- "TARGET_ALTIVEC"

69564

- "vpkswus %0,%1,%2"

69565

- [(set_attr "type" "vecperm")])

69566

-

69567

(define_insn "*altivec_vrl<VI_char>"

69568

- [(set (match_operand:VI 0 "register_operand" "=v")

69569

- (rotate:VI (match_operand:VI 1 "register_operand" "v")

69570

- (match_operand:VI 2 "register_operand" "v")))]

69571

- "TARGET_ALTIVEC"

69572

+ [(set (match_operand:VI2 0 "register_operand" "=v")

69573

+ (rotate:VI2 (match_operand:VI2 1 "register_operand" "v")

69574

+ (match_operand:VI2 2 "register_operand" "v")))]

69575

+ "<VI_unit>"

69576

"vrl<VI_char> %0,%1,%2"

69577

[(set_attr "type" "vecsimple")])

69578

69579

@@ -1172,26 +1565,26 @@

69580

[(set_attr "type" "vecperm")])

69581

69582

(define_insn "*altivec_vsl<VI_char>"

69583

- [(set (match_operand:VI 0 "register_operand" "=v")

69584

- (ashift:VI (match_operand:VI 1 "register_operand" "v")

69585

- (match_operand:VI 2 "register_operand" "v")))]

69586

- "TARGET_ALTIVEC"

69587

+ [(set (match_operand:VI2 0 "register_operand" "=v")

69588

+ (ashift:VI2 (match_operand:VI2 1 "register_operand" "v")

69589

+ (match_operand:VI2 2 "register_operand" "v")))]

69590

+ "<VI_unit>"

69591

"vsl<VI_char> %0,%1,%2"

69592

[(set_attr "type" "vecsimple")])

69593

69594

(define_insn "*altivec_vsr<VI_char>"

69595

- [(set (match_operand:VI 0 "register_operand" "=v")

69596

- (lshiftrt:VI (match_operand:VI 1 "register_operand" "v")

69597

- (match_operand:VI 2 "register_operand" "v")))]

69598

- "TARGET_ALTIVEC"

69599

+ [(set (match_operand:VI2 0 "register_operand" "=v")

69600

+ (lshiftrt:VI2 (match_operand:VI2 1 "register_operand" "v")

69601

+ (match_operand:VI2 2 "register_operand" "v")))]

69602

+ "<VI_unit>"

69603

"vsr<VI_char> %0,%1,%2"

69604

[(set_attr "type" "vecsimple")])

69605

69606

(define_insn "*altivec_vsra<VI_char>"

69607

- [(set (match_operand:VI 0 "register_operand" "=v")

69608

- (ashiftrt:VI (match_operand:VI 1 "register_operand" "v")

69609

- (match_operand:VI 2 "register_operand" "v")))]

69610

- "TARGET_ALTIVEC"

69611

+ [(set (match_operand:VI2 0 "register_operand" "=v")

69612

+ (ashiftrt:VI2 (match_operand:VI2 1 "register_operand" "v")

69613

+ (match_operand:VI2 2 "register_operand" "v")))]

69614

+ "<VI_unit>"

69615

"vsra<VI_char> %0,%1,%2"

69616

[(set_attr "type" "vecsimple")])

69617

69618

@@ -1233,15 +1626,29 @@

69619

"vsum4s<VI_char>s %0,%1,%2"

69620

[(set_attr "type" "veccomplex")])

69621

69622

+;; FIXME: For the following two patterns, the scratch should only be

69623

+;; allocated for !VECTOR_ELT_ORDER_BIG, and the instructions should

69624

+;; be emitted separately.

69625

(define_insn "altivec_vsum2sws"

69626

[(set (match_operand:V4SI 0 "register_operand" "=v")

69627

(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")

69628

(match_operand:V4SI 2 "register_operand" "v")]

69629

UNSPEC_VSUM2SWS))

69630

- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]

69631

+ (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))

69632

+ (clobber (match_scratch:V4SI 3 "=v"))]

69633

"TARGET_ALTIVEC"

69634

- "vsum2sws %0,%1,%2"

69635

- [(set_attr "type" "veccomplex")])

69636

+{

69637

+ if (VECTOR_ELT_ORDER_BIG)

69638

+ return "vsum2sws %0,%1,%2";

69639

+ else

69640

+ return "vsldoi %3,%2,%2,12\n\tvsum2sws %3,%1,%3\n\tvsldoi %0,%3,%3,4";

69641

+}

69642

+ [(set_attr "type" "veccomplex")

69643

+ (set (attr "length")

69644

+ (if_then_else

69645

+ (match_test "VECTOR_ELT_ORDER_BIG")

69646

+ (const_string "4")

69647

+ (const_string "12")))])

69648

69649

(define_insn "altivec_vsumsws"

69650

[(set (match_operand:V4SI 0 "register_operand" "=v")

69651

@@ -1248,12 +1655,54 @@

69652

(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")

69653

(match_operand:V4SI 2 "register_operand" "v")]

69654

UNSPEC_VSUMSWS))

69655

+ (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))

69656

+ (clobber (match_scratch:V4SI 3 "=v"))]

69657

+ "TARGET_ALTIVEC"

69658

+{

69659

+ if (VECTOR_ELT_ORDER_BIG)

69660

+ return "vsumsws %0,%1,%2";

69661

+ else

69662

+ return "vspltw %3,%2,0\n\tvsumsws %3,%1,%3\n\tvsldoi %0,%3,%3,12";

69663

+}

69664

+ [(set_attr "type" "veccomplex")

69665

+ (set (attr "length")

69666

+ (if_then_else

69667

+ (match_test "(VECTOR_ELT_ORDER_BIG)")

69668

+ (const_string "4")

69669

+ (const_string "12")))])

69670

+

69671

+(define_insn "altivec_vsumsws_direct"

69672

+ [(set (match_operand:V4SI 0 "register_operand" "=v")

69673

+ (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")

69674

+ (match_operand:V4SI 2 "register_operand" "v")]

69675

+ UNSPEC_VSUMSWS_DIRECT))

69676

(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]

69677

"TARGET_ALTIVEC"

69678

"vsumsws %0,%1,%2"

69679

[(set_attr "type" "veccomplex")])

69680

69681

-(define_insn "altivec_vspltb"

69682

+(define_expand "altivec_vspltb"

69683

+ [(use (match_operand:V16QI 0 "register_operand" ""))

69684

+ (use (match_operand:V16QI 1 "register_operand" ""))

69685

+ (use (match_operand:QI 2 "u5bit_cint_operand" ""))]

69686

+ "TARGET_ALTIVEC"

69687

+{

69688

+ rtvec v;

69689

+ rtx x;

69690

+

69691

+ /* Special handling for LE with -maltivec=be. We have to reflect

69692

+ the actual selected index for the splat in the RTL. */

69693

+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)

69694

+ operands[2] = GEN_INT (15 - INTVAL (operands[2]));

69695

+

69696

+ v = gen_rtvec (1, operands[2]);

69697

+ x = gen_rtx_VEC_SELECT (QImode, operands[1], gen_rtx_PARALLEL (VOIDmode, v));

69698

+ x = gen_rtx_VEC_DUPLICATE (V16QImode, x);

69699

+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));

69700

+ DONE;

69701

+})

69702

+

69703

+(define_insn "*altivec_vspltb_internal"

69704

[(set (match_operand:V16QI 0 "register_operand" "=v")

69705

(vec_duplicate:V16QI

69706

(vec_select:QI (match_operand:V16QI 1 "register_operand" "v")

69707

@@ -1260,10 +1709,48 @@

69708

(parallel

69709

[(match_operand:QI 2 "u5bit_cint_operand" "")]))))]

69710

"TARGET_ALTIVEC"

69711

+{

69712

+ /* For true LE, this adjusts the selected index. For LE with

69713

+ -maltivec=be, this reverses what was done in the define_expand

69714

+ because the instruction already has big-endian bias. */

69715

+ if (!BYTES_BIG_ENDIAN)

69716

+ operands[2] = GEN_INT (15 - INTVAL (operands[2]));

69717

+

69718

+ return "vspltb %0,%1,%2";

69719

+}

69720

+ [(set_attr "type" "vecperm")])

69721

+

69722

+(define_insn "altivec_vspltb_direct"

69723

+ [(set (match_operand:V16QI 0 "register_operand" "=v")

69724

+ (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")

69725

+ (match_operand:QI 2 "u5bit_cint_operand" "i")]

69726

+ UNSPEC_VSPLT_DIRECT))]

69727

+ "TARGET_ALTIVEC"

69728

"vspltb %0,%1,%2"

69729

[(set_attr "type" "vecperm")])

69730

69731

-(define_insn "altivec_vsplth"

69732

+(define_expand "altivec_vsplth"

69733

+ [(use (match_operand:V8HI 0 "register_operand" ""))

69734

+ (use (match_operand:V8HI 1 "register_operand" ""))

69735

+ (use (match_operand:QI 2 "u5bit_cint_operand" ""))]

69736

+ "TARGET_ALTIVEC"

69737

+{

69738

+ rtvec v;

69739

+ rtx x;

69740

+

69741

+ /* Special handling for LE with -maltivec=be. We have to reflect

69742

+ the actual selected index for the splat in the RTL. */

69743

+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)

69744

+ operands[2] = GEN_INT (7 - INTVAL (operands[2]));

69745

+

69746

+ v = gen_rtvec (1, operands[2]);

69747

+ x = gen_rtx_VEC_SELECT (HImode, operands[1], gen_rtx_PARALLEL (VOIDmode, v));

69748

+ x = gen_rtx_VEC_DUPLICATE (V8HImode, x);

69749

+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));

69750

+ DONE;

69751

+})

69752

+

69753

+(define_insn "*altivec_vsplth_internal"

69754

[(set (match_operand:V8HI 0 "register_operand" "=v")

69755

(vec_duplicate:V8HI

69756

(vec_select:HI (match_operand:V8HI 1 "register_operand" "v")

69757

@@ -1270,10 +1757,48 @@

69758

(parallel

69759

[(match_operand:QI 2 "u5bit_cint_operand" "")]))))]

69760

"TARGET_ALTIVEC"

69761

+{

69762

+ /* For true LE, this adjusts the selected index. For LE with

69763

+ -maltivec=be, this reverses what was done in the define_expand

69764

+ because the instruction already has big-endian bias. */

69765

+ if (!BYTES_BIG_ENDIAN)

69766

+ operands[2] = GEN_INT (7 - INTVAL (operands[2]));

69767

+

69768

+ return "vsplth %0,%1,%2";

69769

+}

69770

+ [(set_attr "type" "vecperm")])

69771

+

69772

+(define_insn "altivec_vsplth_direct"

69773

+ [(set (match_operand:V8HI 0 "register_operand" "=v")

69774

+ (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")

69775

+ (match_operand:QI 2 "u5bit_cint_operand" "i")]

69776

+ UNSPEC_VSPLT_DIRECT))]

69777

+ "TARGET_ALTIVEC"

69778

"vsplth %0,%1,%2"

69779

[(set_attr "type" "vecperm")])

69780

69781

-(define_insn "altivec_vspltw"

69782

+(define_expand "altivec_vspltw"

69783

+ [(use (match_operand:V4SI 0 "register_operand" ""))

69784

+ (use (match_operand:V4SI 1 "register_operand" ""))

69785

+ (use (match_operand:QI 2 "u5bit_cint_operand" ""))]

69786

+ "TARGET_ALTIVEC"

69787

+{

69788

+ rtvec v;

69789

+ rtx x;

69790

+

69791

+ /* Special handling for LE with -maltivec=be. We have to reflect

69792

+ the actual selected index for the splat in the RTL. */

69793

+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)

69794

+ operands[2] = GEN_INT (3 - INTVAL (operands[2]));

69795

+

69796

+ v = gen_rtvec (1, operands[2]);

69797

+ x = gen_rtx_VEC_SELECT (SImode, operands[1], gen_rtx_PARALLEL (VOIDmode, v));

69798

+ x = gen_rtx_VEC_DUPLICATE (V4SImode, x);

69799

+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));

69800

+ DONE;

69801

+})

69802

+

69803

+(define_insn "*altivec_vspltw_internal"

69804

[(set (match_operand:V4SI 0 "register_operand" "=v")

69805

(vec_duplicate:V4SI

69806

(vec_select:SI (match_operand:V4SI 1 "register_operand" "v")

69807

@@ -1280,10 +1805,48 @@

69808

(parallel

69809

[(match_operand:QI 2 "u5bit_cint_operand" "i")]))))]

69810

"TARGET_ALTIVEC"

69811

+{

69812

+ /* For true LE, this adjusts the selected index. For LE with

69813

+ -maltivec=be, this reverses what was done in the define_expand

69814

+ because the instruction already has big-endian bias. */

69815

+ if (!BYTES_BIG_ENDIAN)

69816

+ operands[2] = GEN_INT (3 - INTVAL (operands[2]));

69817

+

69818

+ return "vspltw %0,%1,%2";

69819

+}

69820

+ [(set_attr "type" "vecperm")])

69821

+

69822

+(define_insn "altivec_vspltw_direct"

69823

+ [(set (match_operand:V4SI 0 "register_operand" "=v")

69824

+ (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")

69825

+ (match_operand:QI 2 "u5bit_cint_operand" "i")]

69826

+ UNSPEC_VSPLT_DIRECT))]

69827

+ "TARGET_ALTIVEC"

69828

"vspltw %0,%1,%2"

69829

[(set_attr "type" "vecperm")])

69830

69831

-(define_insn "altivec_vspltsf"

69832

+(define_expand "altivec_vspltsf"

69833

+ [(use (match_operand:V4SF 0 "register_operand" ""))

69834

+ (use (match_operand:V4SF 1 "register_operand" ""))

69835

+ (use (match_operand:QI 2 "u5bit_cint_operand" ""))]

69836

+ "TARGET_ALTIVEC"

69837

+{

69838

+ rtvec v;

69839

+ rtx x;

69840

+

69841

+ /* Special handling for LE with -maltivec=be. We have to reflect

69842

+ the actual selected index for the splat in the RTL. */

69843

+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)

69844

+ operands[2] = GEN_INT (3 - INTVAL (operands[2]));

69845

+

69846

+ v = gen_rtvec (1, operands[2]);

69847

+ x = gen_rtx_VEC_SELECT (SFmode, operands[1], gen_rtx_PARALLEL (VOIDmode, v));

69848

+ x = gen_rtx_VEC_DUPLICATE (V4SFmode, x);

69849

+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));

69850

+ DONE;

69851

+})

69852

+

69853

+(define_insn "*altivec_vspltsf_internal"

69854

[(set (match_operand:V4SF 0 "register_operand" "=v")

69855

(vec_duplicate:V4SF

69856

(vec_select:SF (match_operand:V4SF 1 "register_operand" "v")

69857

@@ -1290,7 +1853,15 @@

69858

(parallel

69859

[(match_operand:QI 2 "u5bit_cint_operand" "i")]))))]

69860

"VECTOR_UNIT_ALTIVEC_P (V4SFmode)"

69861

- "vspltw %0,%1,%2"

69862

+{

69863

+ /* For true LE, this adjusts the selected index. For LE with

69864

+ -maltivec=be, this reverses what was done in the define_expand

69865

+ because the instruction already has big-endian bias. */

69866

+ if (!BYTES_BIG_ENDIAN)

69867

+ operands[2] = GEN_INT (3 - INTVAL (operands[2]));

69868

+

69869

+ return "vspltw %0,%1,%2";

69870

+}

69871

[(set_attr "type" "vecperm")])

69872

69873

(define_insn "altivec_vspltis<VI_char>"

69874

@@ -1308,7 +1879,7 @@

69875

"vrfiz %0,%1"

69876

[(set_attr "type" "vecfloat")])

69877

69878

-(define_insn "altivec_vperm_<mode>"

69879

+(define_expand "altivec_vperm_<mode>"

69880

[(set (match_operand:VM 0 "register_operand" "=v")

69881

(unspec:VM [(match_operand:VM 1 "register_operand" "v")

69882

(match_operand:VM 2 "register_operand" "v")

69883

@@ -1315,10 +1886,25 @@

69884

(match_operand:V16QI 3 "register_operand" "v")]

69885

UNSPEC_VPERM))]

69886

"TARGET_ALTIVEC"

69887

+{

69888

+ if (!VECTOR_ELT_ORDER_BIG)

69889

+ {

69890

+ altivec_expand_vec_perm_le (operands);

69891

+ DONE;

69892

+ }

69893

+})

69894

+

69895

+(define_insn "*altivec_vperm_<mode>_internal"

69896

+ [(set (match_operand:VM 0 "register_operand" "=v")

69897

+ (unspec:VM [(match_operand:VM 1 "register_operand" "v")

69898

+ (match_operand:VM 2 "register_operand" "v")

69899

+ (match_operand:V16QI 3 "register_operand" "v")]

69900

+ UNSPEC_VPERM))]

69901

+ "TARGET_ALTIVEC"

69902

"vperm %0,%1,%2,%3"

69903

[(set_attr "type" "vecperm")])

69904

69905

-(define_insn "altivec_vperm_<mode>_uns"

69906

+(define_expand "altivec_vperm_<mode>_uns"

69907

[(set (match_operand:VM 0 "register_operand" "=v")

69908

(unspec:VM [(match_operand:VM 1 "register_operand" "v")

69909

(match_operand:VM 2 "register_operand" "v")

69910

@@ -1325,6 +1911,21 @@

69911

(match_operand:V16QI 3 "register_operand" "v")]

69912

UNSPEC_VPERM_UNS))]

69913

"TARGET_ALTIVEC"

69914

+{

69915

+ if (!VECTOR_ELT_ORDER_BIG)

69916

+ {

69917

+ altivec_expand_vec_perm_le (operands);

69918

+ DONE;

69919

+ }

69920

+})

69921

+

69922

+(define_insn "*altivec_vperm_<mode>_uns_internal"

69923

+ [(set (match_operand:VM 0 "register_operand" "=v")

69924

+ (unspec:VM [(match_operand:VM 1 "register_operand" "v")

69925

+ (match_operand:VM 2 "register_operand" "v")

69926

+ (match_operand:V16QI 3 "register_operand" "v")]

69927

+ UNSPEC_VPERM_UNS))]

69928

+ "TARGET_ALTIVEC"

69929

"vperm %0,%1,%2,%3"

69930

[(set_attr "type" "vecperm")])

69931

69932

@@ -1335,7 +1936,12 @@

69933

(match_operand:V16QI 3 "register_operand" "")]

69934

UNSPEC_VPERM))]

69935

"TARGET_ALTIVEC"

69936

- "")

69937

+{

69938

+ if (!BYTES_BIG_ENDIAN) {

69939

+ altivec_expand_vec_perm_le (operands);

69940

+ DONE;

69941

+ }

69942

+})

69943

69944

(define_expand "vec_perm_constv16qi"

69945

[(match_operand:V16QI 0 "register_operand" "")

69946

@@ -1476,52 +2082,72 @@

69947

"vsldoi %0,%1,%2,%3"

69948

[(set_attr "type" "vecperm")])

69949

69950

-(define_insn "altivec_vupkhsb"

69951

- [(set (match_operand:V8HI 0 "register_operand" "=v")

69952

- (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]

69953

- UNSPEC_VUPKHSB))]

69954

- "TARGET_ALTIVEC"

69955

- "vupkhsb %0,%1"

69956

+(define_insn "altivec_vupkhs<VU_char>"

69957

+ [(set (match_operand:VP 0 "register_operand" "=v")

69958

+ (unspec:VP [(match_operand:<VP_small> 1 "register_operand" "v")]

69959

+ UNSPEC_VUNPACK_HI_SIGN))]

69960

+ "<VI_unit>"

69961

+{

69962

+ if (VECTOR_ELT_ORDER_BIG)

69963

+ return "vupkhs<VU_char> %0,%1";

69964

+ else

69965

+ return "vupkls<VU_char> %0,%1";

69966

+}

69967

[(set_attr "type" "vecperm")])

69968

69969

-(define_insn "altivec_vupkhpx"

69970

- [(set (match_operand:V4SI 0 "register_operand" "=v")

69971

- (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]

69972

- UNSPEC_VUPKHPX))]

69973

- "TARGET_ALTIVEC"

69974

- "vupkhpx %0,%1"

69975

+(define_insn "*altivec_vupkhs<VU_char>_direct"

69976

+ [(set (match_operand:VP 0 "register_operand" "=v")

69977

+ (unspec:VP [(match_operand:<VP_small> 1 "register_operand" "v")]

69978

+ UNSPEC_VUNPACK_HI_SIGN_DIRECT))]

69979

+ "<VI_unit>"

69980

+ "vupkhs<VU_char> %0,%1"

69981

[(set_attr "type" "vecperm")])

69982

69983

-(define_insn "altivec_vupkhsh"

69984

- [(set (match_operand:V4SI 0 "register_operand" "=v")

69985

- (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]

69986

- UNSPEC_VUPKHSH))]

69987

- "TARGET_ALTIVEC"

69988

- "vupkhsh %0,%1"

69989

+(define_insn "altivec_vupkls<VU_char>"

69990

+ [(set (match_operand:VP 0 "register_operand" "=v")

69991

+ (unspec:VP [(match_operand:<VP_small> 1 "register_operand" "v")]

69992

+ UNSPEC_VUNPACK_LO_SIGN))]

69993

+ "<VI_unit>"

69994

+{

69995

+ if (VECTOR_ELT_ORDER_BIG)

69996

+ return "vupkls<VU_char> %0,%1";

69997

+ else

69998

+ return "vupkhs<VU_char> %0,%1";

69999

+}

70000

[(set_attr "type" "vecperm")])

70001

70002

-(define_insn "altivec_vupklsb"

70003

- [(set (match_operand:V8HI 0 "register_operand" "=v")

70004

- (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]

70005

- UNSPEC_VUPKLSB))]

70006

- "TARGET_ALTIVEC"

70007

- "vupklsb %0,%1"

70008

+(define_insn "*altivec_vupkls<VU_char>_direct"

70009

+ [(set (match_operand:VP 0 "register_operand" "=v")

70010

+ (unspec:VP [(match_operand:<VP_small> 1 "register_operand" "v")]

70011

+ UNSPEC_VUNPACK_LO_SIGN_DIRECT))]

70012

+ "<VI_unit>"

70013

+ "vupkls<VU_char> %0,%1"

70014

[(set_attr "type" "vecperm")])

70015

70016

-(define_insn "altivec_vupklpx"

70017

+(define_insn "altivec_vupkhpx"

70018

[(set (match_operand:V4SI 0 "register_operand" "=v")

70019

(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]

70020

- UNSPEC_VUPKLPX))]

70021

+ UNSPEC_VUPKHPX))]

70022

"TARGET_ALTIVEC"

70023

- "vupklpx %0,%1"

70024

+{

70025

+ if (VECTOR_ELT_ORDER_BIG)

70026

+ return "vupkhpx %0,%1";

70027

+ else

70028

+ return "vupklpx %0,%1";

70029

+}

70030

[(set_attr "type" "vecperm")])

70031

70032

-(define_insn "altivec_vupklsh"

70033

+(define_insn "altivec_vupklpx"

70034

[(set (match_operand:V4SI 0 "register_operand" "=v")

70035

(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]

70036

- UNSPEC_VUPKLSH))]

70037

+ UNSPEC_VUPKLPX))]

70038

"TARGET_ALTIVEC"

70039

- "vupklsh %0,%1"

70040

+{

70041

+ if (VECTOR_ELT_ORDER_BIG)

70042

+ return "vupklpx %0,%1";

70043

+ else

70044

+ return "vupkhpx %0,%1";

70045

+}

70046

[(set_attr "type" "vecperm")])

70047

70048

;; Compare vectors producing a vector result and a predicate, setting CR6 to

70049

@@ -1528,37 +2154,37 @@

70050

;; indicate a combined status

70051

(define_insn "*altivec_vcmpequ<VI_char>_p"

70052

[(set (reg:CC 74)

70053

- (unspec:CC [(eq:CC (match_operand:VI 1 "register_operand" "v")

70054

- (match_operand:VI 2 "register_operand" "v"))]

70055

+ (unspec:CC [(eq:CC (match_operand:VI2 1 "register_operand" "v")

70056

+ (match_operand:VI2 2 "register_operand" "v"))]

70057

UNSPEC_PREDICATE))

70058

- (set (match_operand:VI 0 "register_operand" "=v")

70059

- (eq:VI (match_dup 1)

70060

- (match_dup 2)))]

70061

- "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"

70062

+ (set (match_operand:VI2 0 "register_operand" "=v")

70063

+ (eq:VI2 (match_dup 1)

70064

+ (match_dup 2)))]

70065

+ "<VI_unit>"

70066

"vcmpequ<VI_char>. %0,%1,%2"

70067

[(set_attr "type" "veccmp")])

70068

70069

(define_insn "*altivec_vcmpgts<VI_char>_p"

70070

[(set (reg:CC 74)

70071

- (unspec:CC [(gt:CC (match_operand:VI 1 "register_operand" "v")

70072

- (match_operand:VI 2 "register_operand" "v"))]

70073

+ (unspec:CC [(gt:CC (match_operand:VI2 1 "register_operand" "v")

70074

+ (match_operand:VI2 2 "register_operand" "v"))]

70075

UNSPEC_PREDICATE))

70076

- (set (match_operand:VI 0 "register_operand" "=v")

70077

- (gt:VI (match_dup 1)

70078

- (match_dup 2)))]

70079

- "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"

70080

+ (set (match_operand:VI2 0 "register_operand" "=v")

70081

+ (gt:VI2 (match_dup 1)

70082

+ (match_dup 2)))]

70083

+ "<VI_unit>"

70084

"vcmpgts<VI_char>. %0,%1,%2"

70085

[(set_attr "type" "veccmp")])

70086

70087

(define_insn "*altivec_vcmpgtu<VI_char>_p"

70088

[(set (reg:CC 74)

70089

- (unspec:CC [(gtu:CC (match_operand:VI 1 "register_operand" "v")

70090

- (match_operand:VI 2 "register_operand" "v"))]

70091

+ (unspec:CC [(gtu:CC (match_operand:VI2 1 "register_operand" "v")

70092

+ (match_operand:VI2 2 "register_operand" "v"))]

70093

UNSPEC_PREDICATE))

70094

- (set (match_operand:VI 0 "register_operand" "=v")

70095

- (gtu:VI (match_dup 1)

70096

- (match_dup 2)))]

70097

- "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"

70098

+ (set (match_operand:VI2 0 "register_operand" "=v")

70099

+ (gtu:VI2 (match_dup 1)

70100

+ (match_dup 2)))]

70101

+ "<VI_unit>"

70102

"vcmpgtu<VI_char>. %0,%1,%2"

70103

[(set_attr "type" "veccmp")])

70104

70105

@@ -1710,12 +2336,26 @@

70106

;; Parallel some of the LVE* and STV*'s with unspecs because some have

70107

;; identical rtl but different instructions-- and gcc gets confused.

70108

70109

-(define_insn "altivec_lve<VI_char>x"

70110

+(define_expand "altivec_lve<VI_char>x"

70111

[(parallel

70112

[(set (match_operand:VI 0 "register_operand" "=v")

70113

(match_operand:VI 1 "memory_operand" "Z"))

70114

(unspec [(const_int 0)] UNSPEC_LVE)])]

70115

"TARGET_ALTIVEC"

70116

+{

70117

+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)

70118

+ {

70119

+ altivec_expand_lvx_be (operands[0], operands[1], <MODE>mode, UNSPEC_LVE);

70120

+ DONE;

70121

+ }

70122

+})

70123

+

70124

+(define_insn "*altivec_lve<VI_char>x_internal"

70125

+ [(parallel

70126

+ [(set (match_operand:VI 0 "register_operand" "=v")

70127

+ (match_operand:VI 1 "memory_operand" "Z"))

70128

+ (unspec [(const_int 0)] UNSPEC_LVE)])]

70129

+ "TARGET_ALTIVEC"

70130

"lve<VI_char>x %0,%y1"

70131

[(set_attr "type" "vecload")])

70132

70133

@@ -1728,46 +2368,114 @@

70134

"lvewx %0,%y1"

70135

[(set_attr "type" "vecload")])

70136

70137

-(define_insn "altivec_lvxl"

70138

+(define_expand "altivec_lvxl_<mode>"

70139

[(parallel

70140

- [(set (match_operand:V4SI 0 "register_operand" "=v")

70141

- (match_operand:V4SI 1 "memory_operand" "Z"))

70142

+ [(set (match_operand:VM2 0 "register_operand" "=v")

70143

+ (match_operand:VM2 1 "memory_operand" "Z"))

70144

(unspec [(const_int 0)] UNSPEC_SET_VSCR)])]

70145

"TARGET_ALTIVEC"

70146

- "lvxl %0,%y1"

70147

+{

70148

+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)

70149

+ {

70150

+ altivec_expand_lvx_be (operands[0], operands[1], <MODE>mode, UNSPEC_SET_VSCR);

70151

+ DONE;

70152

+ }

70153

+})

70154

+

70155

+(define_insn "*altivec_lvxl_<mode>_internal"

70156

+ [(parallel

70157

+ [(set (match_operand:VM2 0 "register_operand" "=v")

70158

+ (match_operand:VM2 1 "memory_operand" "Z"))

70159

+ (unspec [(const_int 0)] UNSPEC_SET_VSCR)])]

70160

+ "TARGET_ALTIVEC"

70161

+ "lvx %0,%y1"

70162

[(set_attr "type" "vecload")])

70163

70164

-(define_insn "altivec_lvx_<mode>"

70165

+(define_expand "altivec_lvx_<mode>"

70166

[(parallel

70167

[(set (match_operand:VM2 0 "register_operand" "=v")

70168

(match_operand:VM2 1 "memory_operand" "Z"))

70169

(unspec [(const_int 0)] UNSPEC_LVX)])]

70170

"TARGET_ALTIVEC"

70171

+{

70172

+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)

70173

+ {

70174

+ altivec_expand_lvx_be (operands[0], operands[1], <MODE>mode, UNSPEC_LVX);

70175

+ DONE;

70176

+ }

70177

+})

70178

+

70179

+(define_insn "*altivec_lvx_<mode>_internal"

70180

+ [(parallel

70181

+ [(set (match_operand:VM2 0 "register_operand" "=v")

70182

+ (match_operand:VM2 1 "memory_operand" "Z"))

70183

+ (unspec [(const_int 0)] UNSPEC_LVX)])]

70184

+ "TARGET_ALTIVEC"

70185

"lvx %0,%y1"

70186

[(set_attr "type" "vecload")])

70187

70188

-(define_insn "altivec_stvx_<mode>"

70189

+(define_expand "altivec_stvx_<mode>"

70190

[(parallel

70191

[(set (match_operand:VM2 0 "memory_operand" "=Z")

70192

(match_operand:VM2 1 "register_operand" "v"))

70193

(unspec [(const_int 0)] UNSPEC_STVX)])]

70194

"TARGET_ALTIVEC"

70195

+{

70196

+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)

70197

+ {

70198

+ altivec_expand_stvx_be (operands[0], operands[1], <MODE>mode, UNSPEC_STVX);

70199

+ DONE;

70200

+ }

70201

+})

70202

+

70203

+(define_insn "*altivec_stvx_<mode>_internal"

70204

+ [(parallel

70205

+ [(set (match_operand:VM2 0 "memory_operand" "=Z")

70206

+ (match_operand:VM2 1 "register_operand" "v"))

70207

+ (unspec [(const_int 0)] UNSPEC_STVX)])]

70208

+ "TARGET_ALTIVEC"

70209

"stvx %1,%y0"

70210

[(set_attr "type" "vecstore")])

70211

70212

-(define_insn "altivec_stvxl"

70213

+(define_expand "altivec_stvxl_<mode>"

70214

[(parallel

70215

- [(set (match_operand:V4SI 0 "memory_operand" "=Z")

70216

- (match_operand:V4SI 1 "register_operand" "v"))

70217

+ [(set (match_operand:VM2 0 "memory_operand" "=Z")

70218

+ (match_operand:VM2 1 "register_operand" "v"))

70219

(unspec [(const_int 0)] UNSPEC_STVXL)])]

70220

"TARGET_ALTIVEC"

70221

+{

70222

+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)

70223

+ {

70224

+ altivec_expand_stvx_be (operands[0], operands[1], <MODE>mode, UNSPEC_STVXL);

70225

+ DONE;

70226

+ }

70227

+})

70228

+

70229

+(define_insn "*altivec_stvxl_<mode>_internal"

70230

+ [(parallel

70231

+ [(set (match_operand:VM2 0 "memory_operand" "=Z")

70232

+ (match_operand:VM2 1 "register_operand" "v"))

70233

+ (unspec [(const_int 0)] UNSPEC_STVXL)])]

70234

+ "TARGET_ALTIVEC"

70235

"stvxl %1,%y0"

70236

[(set_attr "type" "vecstore")])

70237

70238

-(define_insn "altivec_stve<VI_char>x"

70239

+(define_expand "altivec_stve<VI_char>x"

70240

[(set (match_operand:<VI_scalar> 0 "memory_operand" "=Z")

70241

(unspec:<VI_scalar> [(match_operand:VI 1 "register_operand" "v")] UNSPEC_STVE))]

70242

"TARGET_ALTIVEC"

70243

+{

70244

+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)

70245

+ {

70246

+ altivec_expand_stvex_be (operands[0], operands[1], <MODE>mode, UNSPEC_STVE);

70247

+ DONE;

70248

+ }

70249

+})

70250

+

70251

+(define_insn "*altivec_stve<VI_char>x_internal"

70252

+ [(set (match_operand:<VI_scalar> 0 "memory_operand" "=Z")

70253

+ (unspec:<VI_scalar> [(match_operand:VI 1 "register_operand" "v")] UNSPEC_STVE))]

70254

+ "TARGET_ALTIVEC"

70255

"stve<VI_char>x %1,%y0"

70256

[(set_attr "type" "vecstore")])

70257

70258

@@ -1779,20 +2487,28 @@

70259

[(set_attr "type" "vecstore")])

70260

70261

;; Generate

70262

-;; vspltis? SCRATCH0,0

70263

+;; xxlxor/vxor SCRATCH0,SCRATCH0,SCRATCH0

70264

;; vsubu?m SCRATCH2,SCRATCH1,%1

70265

;; vmaxs? %0,%1,SCRATCH2"

70266

(define_expand "abs<mode>2"

70267

- [(set (match_dup 2) (vec_duplicate:VI (const_int 0)))

70268

- (set (match_dup 3)

70269

- (minus:VI (match_dup 2)

70270

- (match_operand:VI 1 "register_operand" "v")))

70271

- (set (match_operand:VI 0 "register_operand" "=v")

70272

- (smax:VI (match_dup 1) (match_dup 3)))]

70273

- "TARGET_ALTIVEC"

70274

+ [(set (match_dup 2) (match_dup 3))

70275

+ (set (match_dup 4)

70276

+ (minus:VI2 (match_dup 2)

70277

+ (match_operand:VI2 1 "register_operand" "v")))

70278

+ (set (match_operand:VI2 0 "register_operand" "=v")

70279

+ (smax:VI2 (match_dup 1) (match_dup 4)))]

70280

+ "<VI_unit>"

70281

{

70282

- operands[2] = gen_reg_rtx (GET_MODE (operands[0]));

70283

- operands[3] = gen_reg_rtx (GET_MODE (operands[0]));

70284

+ int i, n_elt = GET_MODE_NUNITS (<MODE>mode);

70285

+ rtvec v = rtvec_alloc (n_elt);

70286

+

70287

+ /* Create an all 0 constant. */

70288

+ for (i = 0; i < n_elt; ++i)

70289

+ RTVEC_ELT (v, i) = const0_rtx;

70290

+

70291

+ operands[2] = gen_reg_rtx (<MODE>mode);

70292

+ operands[3] = gen_rtx_CONST_VECTOR (<MODE>mode, v);

70293

+ operands[4] = gen_reg_rtx (<MODE>mode);

70294

})

70295

70296

;; Generate

70297

@@ -1844,7 +2560,7 @@

70298

70299

emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));

70300

emit_insn (gen_altivec_vsum4s<VI_char>s (vtmp1, operands[1], vzero));

70301

- emit_insn (gen_altivec_vsumsws (dest, vtmp1, vzero));

70302

+ emit_insn (gen_altivec_vsumsws_direct (dest, vtmp1, vzero));

70303

DONE;

70304

})

70305

70306

@@ -1860,7 +2576,7 @@

70307

70308

emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));

70309

emit_insn (gen_altivec_vsum4ubs (vtmp1, operands[1], vzero));

70310

- emit_insn (gen_altivec_vsumsws (dest, vtmp1, vzero));

70311

+ emit_insn (gen_altivec_vsumsws_direct (dest, vtmp1, vzero));

70312

DONE;

70313

})

70314

70315

@@ -1950,50 +2666,20 @@

70316

DONE;

70317

}")

70318

70319

-(define_expand "vec_unpacks_hi_v16qi"

70320

- [(set (match_operand:V8HI 0 "register_operand" "=v")

70321

- (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]

70322

- UNSPEC_VUPKHSB))]

70323

- "TARGET_ALTIVEC"

70324

- "

70325

-{

70326

- emit_insn (gen_altivec_vupkhsb (operands[0], operands[1]));

70327

- DONE;

70328

-}")

70329

+(define_expand "vec_unpacks_hi_<VP_small_lc>"

70330

+ [(set (match_operand:VP 0 "register_operand" "=v")

70331

+ (unspec:VP [(match_operand:<VP_small> 1 "register_operand" "v")]

70332

+ UNSPEC_VUNPACK_HI_SIGN_DIRECT))]

70333

+ "<VI_unit>"

70334

+ "")

70335

70336

-(define_expand "vec_unpacks_hi_v8hi"

70337

- [(set (match_operand:V4SI 0 "register_operand" "=v")

70338

- (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]

70339

- UNSPEC_VUPKHSH))]

70340

- "TARGET_ALTIVEC"

70341

- "

70342

-{

70343

- emit_insn (gen_altivec_vupkhsh (operands[0], operands[1]));

70344

- DONE;

70345

-}")

70346

+(define_expand "vec_unpacks_lo_<VP_small_lc>"

70347

+ [(set (match_operand:VP 0 "register_operand" "=v")

70348

+ (unspec:VP [(match_operand:<VP_small> 1 "register_operand" "v")]

70349

+ UNSPEC_VUNPACK_LO_SIGN_DIRECT))]

70350

+ "<VI_unit>"

70351

+ "")

70352

70353

-(define_expand "vec_unpacks_lo_v16qi"

70354

- [(set (match_operand:V8HI 0 "register_operand" "=v")

70355

- (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]

70356

- UNSPEC_VUPKLSB))]

70357

- "TARGET_ALTIVEC"

70358

- "

70359

-{

70360

- emit_insn (gen_altivec_vupklsb (operands[0], operands[1]));

70361

- DONE;

70362

-}")

70363

-

70364

-(define_expand "vec_unpacks_lo_v8hi"

70365

- [(set (match_operand:V4SI 0 "register_operand" "=v")

70366

- (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]

70367

- UNSPEC_VUPKLSH))]

70368

- "TARGET_ALTIVEC"

70369

- "

70370

-{

70371

- emit_insn (gen_altivec_vupklsh (operands[0], operands[1]));

70372

- DONE;

70373

-}")

70374

-

70375

(define_insn "vperm_v8hiv4si"

70376

[(set (match_operand:V4SI 0 "register_operand" "=v")

70377

(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")

70378

@@ -2025,25 +2711,26 @@

70379

rtx vzero = gen_reg_rtx (V8HImode);

70380

rtx mask = gen_reg_rtx (V16QImode);

70381

rtvec v = rtvec_alloc (16);

70382

+ bool be = BYTES_BIG_ENDIAN;

70383

70384

emit_insn (gen_altivec_vspltish (vzero, const0_rtx));

70385

70386

- RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16);

70387

- RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 0);

70388

- RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 16);

70389

- RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 1);

70390

- RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16);

70391

- RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 2);

70392

- RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 16);

70393

- RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 3);

70394

- RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);

70395

- RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 4);

70396

- RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 16);

70397

- RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 5);

70398

- RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16);

70399

- RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 6);

70400

- RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 16);

70401

- RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 7);

70402

+ RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, be ? 16 : 7);

70403

+ RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, be ? 0 : 16);

70404

+ RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, be ? 16 : 6);

70405

+ RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, be ? 1 : 16);

70406

+ RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, be ? 16 : 5);

70407

+ RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, be ? 2 : 16);

70408

+ RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, be ? 16 : 4);

70409

+ RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, be ? 3 : 16);

70410

+ RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, be ? 16 : 3);

70411

+ RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, be ? 4 : 16);

70412

+ RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, be ? 16 : 2);

70413

+ RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, be ? 5 : 16);

70414

+ RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, be ? 16 : 1);

70415

+ RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, be ? 6 : 16);

70416

+ RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, be ? 16 : 0);

70417

+ RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, be ? 7 : 16);

70418

70419

emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));

70420

emit_insn (gen_vperm_v16qiv8hi (operands[0], operands[1], vzero, mask));

70421

@@ -2060,25 +2747,26 @@

70422

rtx vzero = gen_reg_rtx (V4SImode);

70423

rtx mask = gen_reg_rtx (V16QImode);

70424

rtvec v = rtvec_alloc (16);

70425

+ bool be = BYTES_BIG_ENDIAN;

70426

70427

emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));

70428

70429

- RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16);

70430

- RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 17);

70431

- RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 0);

70432

- RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 1);

70433

- RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16);

70434

- RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 17);

70435

- RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 2);

70436

- RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 3);

70437

- RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);

70438

- RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17);

70439

- RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 4);

70440

- RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 5);

70441

- RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16);

70442

- RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 17);

70443

- RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 6);

70444

- RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 7);

70445

+ RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, be ? 16 : 7);

70446

+ RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, be ? 17 : 6);

70447

+ RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, be ? 0 : 17);

70448

+ RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, be ? 1 : 16);

70449

+ RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, be ? 16 : 5);

70450

+ RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, be ? 17 : 4);

70451

+ RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, be ? 2 : 17);

70452

+ RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, be ? 3 : 16);

70453

+ RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, be ? 16 : 3);

70454

+ RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, be ? 17 : 2);

70455

+ RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, be ? 4 : 17);

70456

+ RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, be ? 5 : 16);

70457

+ RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, be ? 16 : 1);

70458

+ RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, be ? 17 : 0);

70459

+ RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, be ? 6 : 17);

70460

+ RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, be ? 7 : 16);

70461

70462

emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));

70463

emit_insn (gen_vperm_v8hiv4si (operands[0], operands[1], vzero, mask));

70464

@@ -2095,25 +2783,26 @@

70465

rtx vzero = gen_reg_rtx (V8HImode);

70466

rtx mask = gen_reg_rtx (V16QImode);

70467

rtvec v = rtvec_alloc (16);

70468

+ bool be = BYTES_BIG_ENDIAN;

70469

70470

emit_insn (gen_altivec_vspltish (vzero, const0_rtx));

70471

70472

- RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16);

70473

- RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 8);

70474

- RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 16);

70475

- RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 9);

70476

- RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16);

70477

- RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 10);

70478

- RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 16);

70479

- RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 11);

70480

- RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);

70481

- RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 12);

70482

- RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 16);

70483

- RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 13);

70484

- RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16);

70485

- RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 14);

70486

- RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 16);

70487

- RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 15);

70488

+ RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, be ? 16 : 15);

70489

+ RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, be ? 8 : 16);

70490

+ RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, be ? 16 : 14);

70491

+ RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, be ? 9 : 16);

70492

+ RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, be ? 16 : 13);

70493

+ RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, be ? 10 : 16);

70494

+ RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, be ? 16 : 12);

70495

+ RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, be ? 11 : 16);

70496

+ RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, be ? 16 : 11);

70497

+ RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, be ? 12 : 16);

70498

+ RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, be ? 16 : 10);

70499

+ RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, be ? 13 : 16);

70500

+ RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, be ? 16 : 9);

70501

+ RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, be ? 14 : 16);

70502

+ RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, be ? 16 : 8);

70503

+ RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, be ? 15 : 16);

70504

70505

emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));

70506

emit_insn (gen_vperm_v16qiv8hi (operands[0], operands[1], vzero, mask));

70507

@@ -2130,25 +2819,26 @@

70508

rtx vzero = gen_reg_rtx (V4SImode);

70509

rtx mask = gen_reg_rtx (V16QImode);

70510

rtvec v = rtvec_alloc (16);

70511

+ bool be = BYTES_BIG_ENDIAN;

70512

70513

emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));

70514

70515

- RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16);

70516

- RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 17);

70517

- RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 8);

70518

- RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 9);

70519

- RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16);

70520

- RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 17);

70521

- RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 10);

70522

- RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 11);

70523

- RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);

70524

- RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17);

70525

- RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 12);

70526

- RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 13);

70527

- RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16);

70528

- RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 17);

70529

- RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 14);

70530

- RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 15);

70531

+ RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, be ? 16 : 15);

70532

+ RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, be ? 17 : 14);

70533

+ RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, be ? 8 : 17);

70534

+ RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, be ? 9 : 16);

70535

+ RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, be ? 16 : 13);

70536

+ RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, be ? 17 : 12);

70537

+ RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, be ? 10 : 17);

70538

+ RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, be ? 11 : 16);

70539

+ RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, be ? 16 : 11);

70540

+ RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, be ? 17 : 10);

70541

+ RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, be ? 12 : 17);

70542

+ RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, be ? 13 : 16);

70543

+ RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, be ? 16 : 9);

70544

+ RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, be ? 17 : 8);

70545

+ RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, be ? 14 : 17);

70546

+ RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, be ? 15 : 16);

70547

70548

emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));

70549

emit_insn (gen_vperm_v8hiv4si (operands[0], operands[1], vzero, mask));

70550

@@ -2166,9 +2856,18 @@

70551

rtx ve = gen_reg_rtx (V8HImode);

70552

rtx vo = gen_reg_rtx (V8HImode);

70553

70554

- emit_insn (gen_vec_widen_umult_even_v16qi (ve, operands[1], operands[2]));

70555

- emit_insn (gen_vec_widen_umult_odd_v16qi (vo, operands[1], operands[2]));

70556

- emit_insn (gen_altivec_vmrghh (operands[0], ve, vo));

70557

+ if (BYTES_BIG_ENDIAN)

70558

+ {

70559

+ emit_insn (gen_altivec_vmuleub (ve, operands[1], operands[2]));

70560

+ emit_insn (gen_altivec_vmuloub (vo, operands[1], operands[2]));

70561

+ emit_insn (gen_altivec_vmrghh_direct (operands[0], ve, vo));

70562

+ }

70563

+ else

70564

+ {

70565

+ emit_insn (gen_altivec_vmuloub (ve, operands[1], operands[2]));

70566

+ emit_insn (gen_altivec_vmuleub (vo, operands[1], operands[2]));

70567

+ emit_insn (gen_altivec_vmrghh_direct (operands[0], vo, ve));

70568

+ }

70569

DONE;

70570

}")

70571

70572

@@ -2183,9 +2882,18 @@

70573

rtx ve = gen_reg_rtx (V8HImode);

70574

rtx vo = gen_reg_rtx (V8HImode);

70575

70576

- emit_insn (gen_vec_widen_umult_even_v16qi (ve, operands[1], operands[2]));

70577

- emit_insn (gen_vec_widen_umult_odd_v16qi (vo, operands[1], operands[2]));

70578

- emit_insn (gen_altivec_vmrglh (operands[0], ve, vo));

70579

+ if (BYTES_BIG_ENDIAN)

70580

+ {

70581

+ emit_insn (gen_altivec_vmuleub (ve, operands[1], operands[2]));

70582

+ emit_insn (gen_altivec_vmuloub (vo, operands[1], operands[2]));

70583

+ emit_insn (gen_altivec_vmrglh_direct (operands[0], ve, vo));

70584

+ }

70585

+ else

70586

+ {

70587

+ emit_insn (gen_altivec_vmuloub (ve, operands[1], operands[2]));

70588

+ emit_insn (gen_altivec_vmuleub (vo, operands[1], operands[2]));

70589

+ emit_insn (gen_altivec_vmrglh_direct (operands[0], vo, ve));

70590

+ }

70591

DONE;

70592

}")

70593

70594

@@ -2200,9 +2908,18 @@

70595

rtx ve = gen_reg_rtx (V8HImode);

70596

rtx vo = gen_reg_rtx (V8HImode);

70597

70598

- emit_insn (gen_vec_widen_smult_even_v16qi (ve, operands[1], operands[2]));

70599

- emit_insn (gen_vec_widen_smult_odd_v16qi (vo, operands[1], operands[2]));

70600

- emit_insn (gen_altivec_vmrghh (operands[0], ve, vo));

70601

+ if (BYTES_BIG_ENDIAN)

70602

+ {

70603

+ emit_insn (gen_altivec_vmulesb (ve, operands[1], operands[2]));

70604

+ emit_insn (gen_altivec_vmulosb (vo, operands[1], operands[2]));

70605

+ emit_insn (gen_altivec_vmrghh_direct (operands[0], ve, vo));

70606

+ }

70607

+ else

70608

+ {

70609

+ emit_insn (gen_altivec_vmulosb (ve, operands[1], operands[2]));

70610

+ emit_insn (gen_altivec_vmulesb (vo, operands[1], operands[2]));

70611

+ emit_insn (gen_altivec_vmrghh_direct (operands[0], vo, ve));

70612

+ }

70613

DONE;

70614

}")

70615

70616

@@ -2217,9 +2934,18 @@

70617

rtx ve = gen_reg_rtx (V8HImode);

70618

rtx vo = gen_reg_rtx (V8HImode);

70619

70620

- emit_insn (gen_vec_widen_smult_even_v16qi (ve, operands[1], operands[2]));

70621

- emit_insn (gen_vec_widen_smult_odd_v16qi (vo, operands[1], operands[2]));

70622

- emit_insn (gen_altivec_vmrglh (operands[0], ve, vo));

70623

+ if (BYTES_BIG_ENDIAN)

70624

+ {

70625

+ emit_insn (gen_altivec_vmulesb (ve, operands[1], operands[2]));

70626

+ emit_insn (gen_altivec_vmulosb (vo, operands[1], operands[2]));

70627

+ emit_insn (gen_altivec_vmrglh_direct (operands[0], ve, vo));

70628

+ }

70629

+ else

70630

+ {

70631

+ emit_insn (gen_altivec_vmulosb (ve, operands[1], operands[2]));

70632

+ emit_insn (gen_altivec_vmulesb (vo, operands[1], operands[2]));

70633

+ emit_insn (gen_altivec_vmrglh_direct (operands[0], vo, ve));

70634

+ }

70635

DONE;

70636

}")

70637

70638

@@ -2234,9 +2960,18 @@

70639

rtx ve = gen_reg_rtx (V4SImode);

70640

rtx vo = gen_reg_rtx (V4SImode);

70641

70642

- emit_insn (gen_vec_widen_umult_even_v8hi (ve, operands[1], operands[2]));

70643

- emit_insn (gen_vec_widen_umult_odd_v8hi (vo, operands[1], operands[2]));

70644

- emit_insn (gen_altivec_vmrghw (operands[0], ve, vo));

70645

+ if (BYTES_BIG_ENDIAN)

70646

+ {

70647

+ emit_insn (gen_altivec_vmuleuh (ve, operands[1], operands[2]));

70648

+ emit_insn (gen_altivec_vmulouh (vo, operands[1], operands[2]));

70649

+ emit_insn (gen_altivec_vmrghw_direct (operands[0], ve, vo));

70650

+ }

70651

+ else

70652

+ {

70653

+ emit_insn (gen_altivec_vmulouh (ve, operands[1], operands[2]));

70654

+ emit_insn (gen_altivec_vmuleuh (vo, operands[1], operands[2]));

70655

+ emit_insn (gen_altivec_vmrghw_direct (operands[0], vo, ve));

70656

+ }

70657

DONE;

70658

}")

70659

70660

@@ -2251,9 +2986,18 @@

70661

rtx ve = gen_reg_rtx (V4SImode);

70662

rtx vo = gen_reg_rtx (V4SImode);

70663

70664

- emit_insn (gen_vec_widen_umult_even_v8hi (ve, operands[1], operands[2]));

70665

- emit_insn (gen_vec_widen_umult_odd_v8hi (vo, operands[1], operands[2]));

70666

- emit_insn (gen_altivec_vmrglw (operands[0], ve, vo));

70667

+ if (BYTES_BIG_ENDIAN)

70668

+ {

70669

+ emit_insn (gen_altivec_vmuleuh (ve, operands[1], operands[2]));

70670

+ emit_insn (gen_altivec_vmulouh (vo, operands[1], operands[2]));

70671

+ emit_insn (gen_altivec_vmrglw_direct (operands[0], ve, vo));

70672

+ }

70673

+ else

70674

+ {

70675

+ emit_insn (gen_altivec_vmulouh (ve, operands[1], operands[2]));

70676

+ emit_insn (gen_altivec_vmuleuh (vo, operands[1], operands[2]));

70677

+ emit_insn (gen_altivec_vmrglw_direct (operands[0], vo, ve));

70678

+ }

70679

DONE;

70680

}")

70681

70682

@@ -2268,9 +3012,18 @@

70683

rtx ve = gen_reg_rtx (V4SImode);

70684

rtx vo = gen_reg_rtx (V4SImode);

70685

70686

- emit_insn (gen_vec_widen_smult_even_v8hi (ve, operands[1], operands[2]));

70687

- emit_insn (gen_vec_widen_smult_odd_v8hi (vo, operands[1], operands[2]));

70688

- emit_insn (gen_altivec_vmrghw (operands[0], ve, vo));

70689

+ if (BYTES_BIG_ENDIAN)

70690

+ {

70691

+ emit_insn (gen_altivec_vmulesh (ve, operands[1], operands[2]));

70692

+ emit_insn (gen_altivec_vmulosh (vo, operands[1], operands[2]));

70693

+ emit_insn (gen_altivec_vmrghw_direct (operands[0], ve, vo));

70694

+ }

70695

+ else

70696

+ {

70697

+ emit_insn (gen_altivec_vmulosh (ve, operands[1], operands[2]));

70698

+ emit_insn (gen_altivec_vmulesh (vo, operands[1], operands[2]));

70699

+ emit_insn (gen_altivec_vmrghw_direct (operands[0], vo, ve));

70700

+ }

70701

DONE;

70702

}")

70703

70704

@@ -2285,35 +3038,28 @@

70705

rtx ve = gen_reg_rtx (V4SImode);

70706

rtx vo = gen_reg_rtx (V4SImode);

70707

70708

- emit_insn (gen_vec_widen_smult_even_v8hi (ve, operands[1], operands[2]));

70709

- emit_insn (gen_vec_widen_smult_odd_v8hi (vo, operands[1], operands[2]));

70710

- emit_insn (gen_altivec_vmrglw (operands[0], ve, vo));

70711

+ if (BYTES_BIG_ENDIAN)

70712

+ {

70713

+ emit_insn (gen_altivec_vmulesh (ve, operands[1], operands[2]));

70714

+ emit_insn (gen_altivec_vmulosh (vo, operands[1], operands[2]));

70715

+ emit_insn (gen_altivec_vmrglw_direct (operands[0], ve, vo));

70716

+ }

70717

+ else

70718

+ {

70719

+ emit_insn (gen_altivec_vmulosh (ve, operands[1], operands[2]));

70720

+ emit_insn (gen_altivec_vmulesh (vo, operands[1], operands[2]));

70721

+ emit_insn (gen_altivec_vmrglw_direct (operands[0], vo, ve));

70722

+ }

70723

DONE;

70724

}")

70725

70726

-(define_expand "vec_pack_trunc_v8hi"

70727

- [(set (match_operand:V16QI 0 "register_operand" "=v")

70728

- (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")

70729

- (match_operand:V8HI 2 "register_operand" "v")]

70730

- UNSPEC_VPKUHUM))]

70731

- "TARGET_ALTIVEC"

70732

- "

70733

-{

70734

- emit_insn (gen_altivec_vpkuhum (operands[0], operands[1], operands[2]));

70735

- DONE;

70736

-}")

70737

-

70738

-(define_expand "vec_pack_trunc_v4si"

70739

- [(set (match_operand:V8HI 0 "register_operand" "=v")

70740

- (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")

70741

- (match_operand:V4SI 2 "register_operand" "v")]

70742

- UNSPEC_VPKUWUM))]

70743

- "TARGET_ALTIVEC"

70744

- "

70745

-{

70746

- emit_insn (gen_altivec_vpkuwum (operands[0], operands[1], operands[2]));

70747

- DONE;

70748

-}")

70749

+(define_expand "vec_pack_trunc_<mode>"

70750

+ [(set (match_operand:<VP_small> 0 "register_operand" "=v")

70751

+ (unspec:<VP_small> [(match_operand:VP 1 "register_operand" "v")

70752

+ (match_operand:VP 2 "register_operand" "v")]

70753

+ UNSPEC_VPACK_UNS_UNS_MOD))]

70754

+ "<VI_unit>"

70755

+ "")

70756

70757

(define_expand "altivec_negv4sf2"

70758

[(use (match_operand:V4SF 0 "register_operand" ""))

70759

@@ -2460,3 +3206,243 @@

70760

emit_insn (gen_altivec_vcfux (operands[0], tmp, const0_rtx));

70761

DONE;

70762

}")

70763

+

70764

+

70765

+;; Power8 vector instructions encoded as Altivec instructions

70766

+

70767

+;; Vector count leading zeros

70768

+(define_insn "*p8v_clz<mode>2"

70769

+ [(set (match_operand:VI2 0 "register_operand" "=v")

70770

+ (clz:VI2 (match_operand:VI2 1 "register_operand" "v")))]

70771

+ "TARGET_P8_VECTOR"

70772

+ "vclz<wd> %0,%1"

70773

+ [(set_attr "length" "4")

70774

+ (set_attr "type" "vecsimple")])

70775

+

70776

+;; Vector population count

70777

+(define_insn "*p8v_popcount<mode>2"

70778

+ [(set (match_operand:VI2 0 "register_operand" "=v")

70779

+ (popcount:VI2 (match_operand:VI2 1 "register_operand" "v")))]

70780

+ "TARGET_P8_VECTOR"

70781

+ "vpopcnt<wd> %0,%1"

70782

+ [(set_attr "length" "4")

70783

+ (set_attr "type" "vecsimple")])

70784

+

70785

+;; Vector Gather Bits by Bytes by Doubleword

70786

+(define_insn "p8v_vgbbd"

70787

+ [(set (match_operand:V16QI 0 "register_operand" "=v")

70788

+ (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")]

70789

+ UNSPEC_VGBBD))]

70790

+ "TARGET_P8_VECTOR"

70791

+ "vgbbd %0,%1"

70792

+ [(set_attr "length" "4")

70793

+ (set_attr "type" "vecsimple")])

70794

+

70795

+

70796

+;; 128-bit binary integer arithmetic

70797

+;; We have a special container type (V1TImode) to allow operations using the

70798

+;; ISA 2.07 128-bit binary support to target the VMX/altivec registers without

70799

+;; having to worry about the register allocator deciding GPRs are better.

70800

+

70801

+(define_insn "altivec_vadduqm"

70802

+ [(set (match_operand:V1TI 0 "register_operand" "=v")

70803

+ (plus:V1TI (match_operand:V1TI 1 "register_operand" "v")

70804

+ (match_operand:V1TI 2 "register_operand" "v")))]

70805

+ "TARGET_VADDUQM"

70806

+ "vadduqm %0,%1,%2"

70807

+ [(set_attr "length" "4")

70808

+ (set_attr "type" "vecsimple")])

70809

+

70810

+(define_insn "altivec_vaddcuq"

70811

+ [(set (match_operand:V1TI 0 "register_operand" "=v")

70812

+ (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "v")

70813

+ (match_operand:V1TI 2 "register_operand" "v")]

70814

+ UNSPEC_VADDCUQ))]

70815

+ "TARGET_VADDUQM"

70816

+ "vaddcuq %0,%1,%2"

70817

+ [(set_attr "length" "4")

70818

+ (set_attr "type" "vecsimple")])

70819

+

70820

+(define_insn "altivec_vsubuqm"

70821

+ [(set (match_operand:V1TI 0 "register_operand" "=v")

70822

+ (minus:V1TI (match_operand:V1TI 1 "register_operand" "v")

70823

+ (match_operand:V1TI 2 "register_operand" "v")))]

70824

+ "TARGET_VADDUQM"

70825

+ "vsubuqm %0,%1,%2"

70826

+ [(set_attr "length" "4")

70827

+ (set_attr "type" "vecsimple")])

70828

+

70829

+(define_insn "altivec_vsubcuq"

70830

+ [(set (match_operand:V1TI 0 "register_operand" "=v")

70831

+ (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "v")

70832

+ (match_operand:V1TI 2 "register_operand" "v")]

70833

+ UNSPEC_VSUBCUQ))]

70834

+ "TARGET_VADDUQM"

70835

+ "vsubcuq %0,%1,%2"

70836

+ [(set_attr "length" "4")

70837

+ (set_attr "type" "vecsimple")])

70838

+

70839

+(define_insn "altivec_vaddeuqm"

70840

+ [(set (match_operand:V1TI 0 "register_operand" "=v")

70841

+ (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "v")

70842

+ (match_operand:V1TI 2 "register_operand" "v")

70843

+ (match_operand:V1TI 3 "register_operand" "v")]

70844

+ UNSPEC_VADDEUQM))]

70845

+ "TARGET_VADDUQM"

70846

+ "vaddeuqm %0,%1,%2,%3"

70847

+ [(set_attr "length" "4")

70848

+ (set_attr "type" "vecsimple")])

70849

+

70850

+(define_insn "altivec_vaddecuq"

70851

+ [(set (match_operand:V1TI 0 "register_operand" "=v")

70852

+ (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "v")

70853

+ (match_operand:V1TI 2 "register_operand" "v")

70854

+ (match_operand:V1TI 3 "register_operand" "v")]

70855

+ UNSPEC_VADDECUQ))]

70856

+ "TARGET_VADDUQM"

70857

+ "vaddecuq %0,%1,%2,%3"

70858

+ [(set_attr "length" "4")

70859

+ (set_attr "type" "vecsimple")])

70860

+

70861

+(define_insn "altivec_vsubeuqm"

70862

+ [(set (match_operand:V1TI 0 "register_operand" "=v")

70863

+ (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "v")

70864

+ (match_operand:V1TI 2 "register_operand" "v")

70865

+ (match_operand:V1TI 3 "register_operand" "v")]

70866

+ UNSPEC_VSUBEUQM))]

70867

+ "TARGET_VADDUQM"

70868

+ "vsubeuqm %0,%1,%2,%3"

70869

+ [(set_attr "length" "4")

70870

+ (set_attr "type" "vecsimple")])

70871

+

70872

+(define_insn "altivec_vsubecuq"

70873

+ [(set (match_operand:V1TI 0 "register_operand" "=v")

70874

+ (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "v")

70875

+ (match_operand:V1TI 2 "register_operand" "v")

70876

+ (match_operand:V1TI 3 "register_operand" "v")]

70877

+ UNSPEC_VSUBECUQ))]

70878

+ "TARGET_VADDUQM"

70879

+ "vsubecuq %0,%1,%2,%3"

70880

+ [(set_attr "length" "4")

70881

+ (set_attr "type" "vecsimple")])

70882

+

70883

+;; We use V2DI as the output type to simplify converting the permute

70884

+;; bits into an integer

70885

+(define_insn "altivec_vbpermq"

70886

+ [(set (match_operand:V2DI 0 "register_operand" "=v")

70887

+ (unspec:V2DI [(match_operand:V16QI 1 "register_operand" "v")

70888

+ (match_operand:V16QI 2 "register_operand" "v")]

70889

+ UNSPEC_VBPERMQ))]

70890

+ "TARGET_P8_VECTOR"

70891

+ "vbpermq %0,%1,%2"

70892

+ [(set_attr "length" "4")

70893

+ (set_attr "type" "vecsimple")])

70894

+

70895

+;; Decimal Integer operations

70896

+(define_int_iterator UNSPEC_BCD_ADD_SUB [UNSPEC_BCDADD UNSPEC_BCDSUB])

70897

+

70898

+(define_int_attr bcd_add_sub [(UNSPEC_BCDADD "add")

70899

+ (UNSPEC_BCDSUB "sub")])

70900

+

70901

+(define_code_iterator BCD_TEST [eq lt gt unordered])

70902

+

70903

+(define_insn "bcd<bcd_add_sub>"

70904

+ [(set (match_operand:V1TI 0 "register_operand" "")

70905

+ (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "")

70906

+ (match_operand:V1TI 2 "register_operand" "")

70907

+ (match_operand:QI 3 "const_0_to_1_operand" "")]

70908

+ UNSPEC_BCD_ADD_SUB))

70909

+ (clobber (reg:CCFP 74))]

70910

+ "TARGET_P8_VECTOR"

70911

+ "bcd<bcd_add_sub>. %0,%1,%2,%3"

70912

+ [(set_attr "length" "4")

70913

+ (set_attr "type" "vecsimple")])

70914

+

70915

+;; Use a floating point type (V2DFmode) for the compare to set CR6 so that we

70916

+;; can use the unordered test for BCD nans and add/subtracts that overflow. An

70917

+;; UNORDERED test on an integer type (like V1TImode) is not defined. The type

70918

+;; probably should be one that can go in the VMX (Altivec) registers, so we

70919

+;; can't use DDmode or DFmode.

70920

+(define_insn "*bcd<bcd_add_sub>_test"

70921

+ [(set (reg:CCFP 74)

70922

+ (compare:CCFP

70923

+ (unspec:V2DF [(match_operand:V1TI 1 "register_operand" "v")

70924

+ (match_operand:V1TI 2 "register_operand" "v")

70925

+ (match_operand:QI 3 "const_0_to_1_operand" "i")]

70926

+ UNSPEC_BCD_ADD_SUB)

70927

+ (match_operand:V2DF 4 "zero_constant" "j")))

70928

+ (clobber (match_scratch:V1TI 0 "=v"))]

70929

+ "TARGET_P8_VECTOR"

70930

+ "bcd<bcd_add_sub>. %0,%1,%2,%3"

70931

+ [(set_attr "length" "4")

70932

+ (set_attr "type" "vecsimple")])

70933

+

70934

+(define_insn "*bcd<bcd_add_sub>_test2"

70935

+ [(set (match_operand:V1TI 0 "register_operand" "=v")

70936

+ (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "v")

70937

+ (match_operand:V1TI 2 "register_operand" "v")

70938

+ (match_operand:QI 3 "const_0_to_1_operand" "i")]

70939

+ UNSPEC_BCD_ADD_SUB))

70940

+ (set (reg:CCFP 74)

70941

+ (compare:CCFP

70942

+ (unspec:V2DF [(match_dup 1)

70943

+ (match_dup 2)

70944

+ (match_dup 3)]

70945

+ UNSPEC_BCD_ADD_SUB)

70946

+ (match_operand:V2DF 4 "zero_constant" "j")))]

70947

+ "TARGET_P8_VECTOR"

70948

+ "bcd<bcd_add_sub>. %0,%1,%2,%3"

70949

+ [(set_attr "length" "4")

70950

+ (set_attr "type" "vecsimple")])

70951

+

70952

+(define_expand "bcd<bcd_add_sub>_<code>"

70953

+ [(parallel [(set (reg:CCFP 74)

70954

+ (compare:CCFP

70955

+ (unspec:V2DF [(match_operand:V1TI 1 "register_operand" "")

70956

+ (match_operand:V1TI 2 "register_operand" "")

70957

+ (match_operand:QI 3 "const_0_to_1_operand" "")]

70958

+ UNSPEC_BCD_ADD_SUB)

70959

+ (match_dup 4)))

70960

+ (clobber (match_scratch:V1TI 5 ""))])

70961

+ (set (match_operand:SI 0 "register_operand" "")

70962

+ (BCD_TEST:SI (reg:CCFP 74)

70963

+ (const_int 0)))]

70964

+ "TARGET_P8_VECTOR"

70965

+{

70966

+ operands[4] = CONST0_RTX (V2DFmode);

70967

+})

70968

+

70969

+;; Peephole2 pattern to combine a bcdadd/bcdsub that calculates the value and

70970

+;; the bcdadd/bcdsub that tests the value. The combiner won't work since

70971

+;; CR6 is a hard coded register. Unfortunately, all of the Altivec predicate

70972

+;; support is hard coded to use the fixed register CR6 instead of creating

70973

+;; a register class for CR6.

70974

+

70975

+(define_peephole2

70976

+ [(parallel [(set (match_operand:V1TI 0 "register_operand" "")

70977

+ (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "")

70978

+ (match_operand:V1TI 2 "register_operand" "")

70979

+ (match_operand:QI 3 "const_0_to_1_operand" "")]

70980

+ UNSPEC_BCD_ADD_SUB))

70981

+ (clobber (reg:CCFP 74))])

70982

+ (parallel [(set (reg:CCFP 74)

70983

+ (compare:CCFP

70984

+ (unspec:V2DF [(match_dup 1)

70985

+ (match_dup 2)

70986

+ (match_dup 3)]

70987

+ UNSPEC_BCD_ADD_SUB)

70988

+ (match_operand:V2DF 4 "zero_constant" "")))

70989

+ (clobber (match_operand:V1TI 5 "register_operand" ""))])]

70990

+ "TARGET_P8_VECTOR"

70991

+ [(parallel [(set (match_dup 0)

70992

+ (unspec:V1TI [(match_dup 1)

70993

+ (match_dup 2)

70994

+ (match_dup 3)]

70995

+ UNSPEC_BCD_ADD_SUB))

70996

+ (set (reg:CCFP 74)

70997

+ (compare:CCFP

70998

+ (unspec:V2DF [(match_dup 1)

70999

+ (match_dup 2)

71000

+ (match_dup 3)]

71001

+ UNSPEC_BCD_ADD_SUB)

71002

+ (match_dup 4)))])])

71003

Index: gcc/config/rs6000/sysv4le.h

71004

===================================================================

71005

--- a/src/gcc/config/rs6000/sysv4le.h (.../tags/gcc_4_8_2_release)

71006

+++ b/src/gcc/config/rs6000/sysv4le.h (.../branches/gcc-4_8-branch)

71007

@@ -22,9 +22,6 @@

71008

#undef TARGET_DEFAULT

71009

#define TARGET_DEFAULT MASK_LITTLE_ENDIAN

71010

71011

-#undef CC1_ENDIAN_DEFAULT_SPEC

71012

-#define CC1_ENDIAN_DEFAULT_SPEC "%(cc1_endian_little)"

71013

-

71014

#undef DEFAULT_ASM_ENDIAN

71015

#define DEFAULT_ASM_ENDIAN " -mlittle"

71016

71017

@@ -34,3 +31,7 @@

71018

71019

#undef MULTILIB_DEFAULTS

71020

#define MULTILIB_DEFAULTS { "mlittle", "mcall-sysv" }

71021

+

71022

+/* Little-endian PowerPC64 Linux uses the ELF v2 ABI by default. */

71023

+#define LINUX64_DEFAULT_ABI_ELFv2

71024

+

71025

Index: gcc/config/rs6000/dfp.md

71026

===================================================================

71027

--- a/src/gcc/config/rs6000/dfp.md (.../tags/gcc_4_8_2_release)

71028

+++ b/src/gcc/config/rs6000/dfp.md (.../branches/gcc-4_8-branch)

71029

@@ -29,77 +29,6 @@

71030

])

71031

71032

71033

-(define_expand "movsd"

71034

- [(set (match_operand:SD 0 "nonimmediate_operand" "")

71035

- (match_operand:SD 1 "any_operand" ""))]

71036

- "TARGET_HARD_FLOAT && TARGET_FPRS"

71037

- "{ rs6000_emit_move (operands[0], operands[1], SDmode); DONE; }")

71038

-

71039

-(define_split

71040

- [(set (match_operand:SD 0 "gpc_reg_operand" "")

71041

- (match_operand:SD 1 "const_double_operand" ""))]

71042

- "reload_completed

71043

- && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)

71044

- || (GET_CODE (operands[0]) == SUBREG

71045

- && GET_CODE (SUBREG_REG (operands[0])) == REG

71046

- && REGNO (SUBREG_REG (operands[0])) <= 31))"

71047

- [(set (match_dup 2) (match_dup 3))]

71048

- "

71049

-{

71050

- long l;

71051

- REAL_VALUE_TYPE rv;

71052

-

71053

- REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);

71054

- REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);

71055

-

71056

- if (! TARGET_POWERPC64)

71057

- operands[2] = operand_subword (operands[0], 0, 0, SDmode);

71058

- else

71059

- operands[2] = gen_lowpart (SImode, operands[0]);

71060

-

71061

- operands[3] = gen_int_mode (l, SImode);

71062

-}")

71063

-

71064

-(define_insn "movsd_hardfloat"

71065

- [(set (match_operand:SD 0 "nonimmediate_operand" "=r,r,m,f,*c*l,!r,*h,!r,!r")

71066

- (match_operand:SD 1 "input_operand" "r,m,r,f,r,h,0,G,Fn"))]

71067

- "(gpc_reg_operand (operands[0], SDmode)

71068

- || gpc_reg_operand (operands[1], SDmode))

71069

- && (TARGET_HARD_FLOAT && TARGET_FPRS)"

71070

- "@

71071

- mr %0,%1

71072

- lwz%U1%X1 %0,%1

71073

- stw%U0%X0 %1,%0

71074

- fmr %0,%1

71075

- mt%0 %1

71076

- mf%1 %0

71077

- nop

71078

- #

71079

- #"

71080

- [(set_attr "type" "*,load,store,fp,mtjmpr,mfjmpr,*,*,*")

71081

- (set_attr "length" "4,4,4,4,4,4,4,4,8")])

71082

-

71083

-(define_insn "movsd_softfloat"

71084

- [(set (match_operand:SD 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,r,*h")

71085

- (match_operand:SD 1 "input_operand" "r,r,h,m,r,I,L,R,G,Fn,0"))]

71086

- "(gpc_reg_operand (operands[0], SDmode)

71087

- || gpc_reg_operand (operands[1], SDmode))

71088

- && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"

71089

- "@

71090

- mr %0,%1

71091

- mt%0 %1

71092

- mf%1 %0

71093

- lwz%U1%X1 %0,%1

71094

- stw%U0%X0 %1,%0

71095

- li %0,%1

71096

- lis %0,%v1

71097

- la %0,%a1

71098

- #

71099

- #

71100

- nop"

71101

- [(set_attr "type" "*,mtjmpr,mfjmpr,load,store,*,*,*,*,*,*")

71102

- (set_attr "length" "4,4,4,4,4,4,4,4,4,8,4")])

71103

-

71104

(define_insn "movsd_store"

71105

[(set (match_operand:DD 0 "nonimmediate_operand" "=m")

71106

(unspec:DD [(match_operand:SD 1 "input_operand" "d")]

71107

@@ -108,7 +37,14 @@

71108

|| gpc_reg_operand (operands[1], SDmode))

71109

&& TARGET_HARD_FLOAT && TARGET_FPRS"

71110

"stfd%U0%X0 %1,%0"

71111

- [(set_attr "type" "fpstore")

71112

+ [(set (attr "type")

71113

+ (if_then_else

71114

+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")

71115

+ (const_string "fpstore_ux")

71116

+ (if_then_else

71117

+ (match_test "update_address_mem (operands[0], VOIDmode)")

71118

+ (const_string "fpstore_u")

71119

+ (const_string "fpstore"))))

71120

(set_attr "length" "4")])

71121

71122

(define_insn "movsd_load"

71123

@@ -119,7 +55,14 @@

71124

|| gpc_reg_operand (operands[1], DDmode))

71125

&& TARGET_HARD_FLOAT && TARGET_FPRS"

71126

"lfd%U1%X1 %0,%1"

71127

- [(set_attr "type" "fpload")

71128

+ [(set (attr "type")

71129

+ (if_then_else

71130

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

71131

+ (const_string "fpload_ux")

71132

+ (if_then_else

71133

+ (match_test "update_address_mem (operands[1], VOIDmode)")

71134

+ (const_string "fpload_u")

71135

+ (const_string "fpload"))))

71136

(set_attr "length" "4")])

71137

71138

;; Hardware support for decimal floating point operations.

71139

@@ -182,211 +125,6 @@

71140

"fnabs %0,%1"

71141

[(set_attr "type" "fp")])

71142

71143

-(define_expand "movdd"

71144

- [(set (match_operand:DD 0 "nonimmediate_operand" "")

71145

- (match_operand:DD 1 "any_operand" ""))]

71146

- ""

71147

- "{ rs6000_emit_move (operands[0], operands[1], DDmode); DONE; }")

71148

-

71149

-(define_split

71150

- [(set (match_operand:DD 0 "gpc_reg_operand" "")

71151

- (match_operand:DD 1 "const_int_operand" ""))]

71152

- "! TARGET_POWERPC64 && reload_completed

71153

- && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)

71154

- || (GET_CODE (operands[0]) == SUBREG

71155

- && GET_CODE (SUBREG_REG (operands[0])) == REG

71156

- && REGNO (SUBREG_REG (operands[0])) <= 31))"

71157

- [(set (match_dup 2) (match_dup 4))

71158

- (set (match_dup 3) (match_dup 1))]

71159

- "

71160

-{

71161

- int endian = (WORDS_BIG_ENDIAN == 0);

71162

- HOST_WIDE_INT value = INTVAL (operands[1]);

71163

-

71164

- operands[2] = operand_subword (operands[0], endian, 0, DDmode);

71165

- operands[3] = operand_subword (operands[0], 1 - endian, 0, DDmode);

71166

-#if HOST_BITS_PER_WIDE_INT == 32

71167

- operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;

71168

-#else

71169

- operands[4] = GEN_INT (value >> 32);

71170

- operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);

71171

-#endif

71172

-}")

71173

-

71174

-(define_split

71175

- [(set (match_operand:DD 0 "gpc_reg_operand" "")

71176

- (match_operand:DD 1 "const_double_operand" ""))]

71177

- "! TARGET_POWERPC64 && reload_completed

71178

- && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)

71179

- || (GET_CODE (operands[0]) == SUBREG

71180

- && GET_CODE (SUBREG_REG (operands[0])) == REG

71181

- && REGNO (SUBREG_REG (operands[0])) <= 31))"

71182

- [(set (match_dup 2) (match_dup 4))

71183

- (set (match_dup 3) (match_dup 5))]

71184

- "

71185

-{

71186

- int endian = (WORDS_BIG_ENDIAN == 0);

71187

- long l[2];

71188

- REAL_VALUE_TYPE rv;

71189

-

71190

- REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);

71191

- REAL_VALUE_TO_TARGET_DECIMAL64 (rv, l);

71192

-

71193

- operands[2] = operand_subword (operands[0], endian, 0, DDmode);

71194

- operands[3] = operand_subword (operands[0], 1 - endian, 0, DDmode);

71195

- operands[4] = gen_int_mode (l[endian], SImode);

71196

- operands[5] = gen_int_mode (l[1 - endian], SImode);

71197

-}")

71198

-

71199

-(define_split

71200

- [(set (match_operand:DD 0 "gpc_reg_operand" "")

71201

- (match_operand:DD 1 "const_double_operand" ""))]

71202

- "TARGET_POWERPC64 && reload_completed

71203

- && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)

71204

- || (GET_CODE (operands[0]) == SUBREG

71205

- && GET_CODE (SUBREG_REG (operands[0])) == REG

71206

- && REGNO (SUBREG_REG (operands[0])) <= 31))"

71207

- [(set (match_dup 2) (match_dup 3))]

71208

- "

71209

-{

71210

- int endian = (WORDS_BIG_ENDIAN == 0);

71211

- long l[2];

71212

- REAL_VALUE_TYPE rv;

71213

-#if HOST_BITS_PER_WIDE_INT >= 64

71214

- HOST_WIDE_INT val;

71215

-#endif

71216

-

71217

- REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);

71218

- REAL_VALUE_TO_TARGET_DECIMAL64 (rv, l);

71219

-

71220

- operands[2] = gen_lowpart (DImode, operands[0]);

71221

- /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */

71222

-#if HOST_BITS_PER_WIDE_INT >= 64

71223

- val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32

71224

- | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));

71225

-

71226

- operands[3] = gen_int_mode (val, DImode);

71227

-#else

71228

- operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);

71229

-#endif

71230

-}")

71231

-

71232

-;; Don't have reload use general registers to load a constant. First,

71233

-;; it might not work if the output operand is the equivalent of

71234

-;; a non-offsettable memref, but also it is less efficient than loading

71235

-;; the constant into an FP register, since it will probably be used there.

71236

-;; The "??" is a kludge until we can figure out a more reasonable way

71237

-;; of handling these non-offsettable values.

71238

-(define_insn "*movdd_hardfloat32"

71239

- [(set (match_operand:DD 0 "nonimmediate_operand" "=!r,??r,m,d,d,m,!r,!r,!r")

71240

- (match_operand:DD 1 "input_operand" "r,m,r,d,m,d,G,H,F"))]

71241

- "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS

71242

- && (gpc_reg_operand (operands[0], DDmode)

71243

- || gpc_reg_operand (operands[1], DDmode))"

71244

- "*

71245

-{

71246

- switch (which_alternative)

71247

- {

71248

- default:

71249

- gcc_unreachable ();

71250

- case 0:

71251

- case 1:

71252

- case 2:

71253

- return \"#\";

71254

- case 3:

71255

- return \"fmr %0,%1\";

71256

- case 4:

71257

- return \"lfd%U1%X1 %0,%1\";

71258

- case 5:

71259

- return \"stfd%U0%X0 %1,%0\";

71260

- case 6:

71261

- case 7:

71262

- case 8:

71263

- return \"#\";

71264

- }

71265

-}"

71266

- [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")

71267

- (set_attr "length" "8,16,16,4,4,4,8,12,16")])

71268

-

71269

-(define_insn "*movdd_softfloat32"

71270

- [(set (match_operand:DD 0 "nonimmediate_operand" "=r,r,m,r,r,r")

71271

- (match_operand:DD 1 "input_operand" "r,m,r,G,H,F"))]

71272

- "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)

71273

- && (gpc_reg_operand (operands[0], DDmode)

71274

- || gpc_reg_operand (operands[1], DDmode))"

71275

- "#"

71276

- [(set_attr "type" "two,load,store,*,*,*")

71277

- (set_attr "length" "8,8,8,8,12,16")])

71278

-

71279

-; ld/std require word-aligned displacements -> 'Y' constraint.

71280

-; List Y->r and r->Y before r->r for reload.

71281

-(define_insn "*movdd_hardfloat64_mfpgpr"

71282

- [(set (match_operand:DD 0 "nonimmediate_operand" "=Y,r,!r,d,d,m,*c*l,!r,*h,!r,!r,!r,r,d")

71283

- (match_operand:DD 1 "input_operand" "r,Y,r,d,m,d,r,h,0,G,H,F,d,r"))]

71284

- "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS

71285

- && (gpc_reg_operand (operands[0], DDmode)

71286

- || gpc_reg_operand (operands[1], DDmode))"

71287

- "@

71288

- std%U0%X0 %1,%0

71289

- ld%U1%X1 %0,%1

71290

- mr %0,%1

71291

- fmr %0,%1

71292

- lfd%U1%X1 %0,%1

71293

- stfd%U0%X0 %1,%0

71294

- mt%0 %1

71295

- mf%1 %0

71296

- nop

71297

- #

71298

- #

71299

- #

71300

- mftgpr %0,%1

71301

- mffgpr %0,%1"

71302

- [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")

71303

- (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16,4,4")])

71304

-

71305

-; ld/std require word-aligned displacements -> 'Y' constraint.

71306

-; List Y->r and r->Y before r->r for reload.

71307

-(define_insn "*movdd_hardfloat64"

71308

- [(set (match_operand:DD 0 "nonimmediate_operand" "=Y,r,!r,d,d,m,*c*l,!r,*h,!r,!r,!r")

71309

- (match_operand:DD 1 "input_operand" "r,Y,r,d,m,d,r,h,0,G,H,F"))]

71310

- "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS

71311

- && (gpc_reg_operand (operands[0], DDmode)

71312

- || gpc_reg_operand (operands[1], DDmode))"

71313

- "@

71314

- std%U0%X0 %1,%0

71315

- ld%U1%X1 %0,%1

71316

- mr %0,%1

71317

- fmr %0,%1

71318

- lfd%U1%X1 %0,%1

71319

- stfd%U0%X0 %1,%0

71320

- mt%0 %1

71321

- mf%1 %0

71322

- nop

71323

- #

71324

- #

71325

- #"

71326

- [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*")

71327

- (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])

71328

-

71329

-(define_insn "*movdd_softfloat64"

71330

- [(set (match_operand:DD 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")

71331

- (match_operand:DD 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]

71332

- "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)

71333

- && (gpc_reg_operand (operands[0], DDmode)

71334

- || gpc_reg_operand (operands[1], DDmode))"

71335

- "@

71336

- ld%U1%X1 %0,%1

71337

- std%U0%X0 %1,%0

71338

- mr %0,%1

71339

- mt%0 %1

71340

- mf%1 %0

71341

- #

71342

- #

71343

- #

71344

- nop"

71345

- [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")

71346

- (set_attr "length" "4,4,4,4,4,8,12,16,4")])

71347

-

71348

(define_expand "negtd2"

71349

[(set (match_operand:TD 0 "gpc_reg_operand" "")

71350

(neg:TD (match_operand:TD 1 "gpc_reg_operand" "")))]

71351

@@ -410,40 +148,25 @@

71352

"")

71353

71354

(define_insn "*abstd2_fpr"

71355

- [(set (match_operand:TD 0 "gpc_reg_operand" "=d")

71356

- (abs:TD (match_operand:TD 1 "gpc_reg_operand" "d")))]

71357

+ [(set (match_operand:TD 0 "gpc_reg_operand" "=d,d")

71358

+ (abs:TD (match_operand:TD 1 "gpc_reg_operand" "0,d")))]

71359

"TARGET_HARD_FLOAT && TARGET_FPRS"

71360

- "fabs %0,%1"

71361

- [(set_attr "type" "fp")])

71362

+ "@

71363

+ fabs %0,%1

71364

+ fabs %0,%1\;fmr %L0,%L1"

71365

+ [(set_attr "type" "fp")

71366

+ (set_attr "length" "4,8")])

71367

71368

(define_insn "*nabstd2_fpr"

71369

- [(set (match_operand:TD 0 "gpc_reg_operand" "=d")

71370

- (neg:TD (abs:TD (match_operand:TD 1 "gpc_reg_operand" "d"))))]

71371

+ [(set (match_operand:TD 0 "gpc_reg_operand" "=d,d")

71372

+ (neg:TD (abs:TD (match_operand:TD 1 "gpc_reg_operand" "0,d"))))]

71373

"TARGET_HARD_FLOAT && TARGET_FPRS"

71374

- "fnabs %0,%1"

71375

- [(set_attr "type" "fp")])

71376

+ "@

71377

+ fnabs %0,%1

71378

+ fnabs %0,%1\;fmr %L0,%L1"

71379

+ [(set_attr "type" "fp")

71380

+ (set_attr "length" "4,8")])

71381

71382

-(define_expand "movtd"

71383

- [(set (match_operand:TD 0 "general_operand" "")

71384

- (match_operand:TD 1 "any_operand" ""))]

71385

- "TARGET_HARD_FLOAT && TARGET_FPRS"

71386

- "{ rs6000_emit_move (operands[0], operands[1], TDmode); DONE; }")

71387

-

71388

-; It's important to list the Y->r and r->Y moves before r->r because

71389

-; otherwise reload, given m->r, will try to pick r->r and reload it,

71390

-; which doesn't make progress.

71391

-(define_insn_and_split "*movtd_internal"

71392

- [(set (match_operand:TD 0 "nonimmediate_operand" "=m,d,d,Y,r,r")

71393

- (match_operand:TD 1 "input_operand" "d,m,d,r,YGHF,r"))]

71394

- "TARGET_HARD_FLOAT && TARGET_FPRS

71395

- && (gpc_reg_operand (operands[0], TDmode)

71396

- || gpc_reg_operand (operands[1], TDmode))"

71397

- "#"

71398

- "&& reload_completed"

71399

- [(pc)]

71400

-{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }

71401

- [(set_attr "length" "8,8,8,20,20,16")])

71402

-

71403

;; Hardware support for decimal floating point operations.

71404

71405

(define_insn "extendddtd2"

71406

@@ -599,3 +322,72 @@

71407

"TARGET_DFP"

71408

"dctfixq %0,%1"

71409

[(set_attr "type" "fp")])

71410

+

71411

+

71412

+;; Decimal builtin support

71413

+

71414

+(define_c_enum "unspec"

71415

+ [UNSPEC_DDEDPD

71416

+ UNSPEC_DENBCD

71417

+ UNSPEC_DXEX

71418

+ UNSPEC_DIEX

71419

+ UNSPEC_DSCLI

71420

+ UNSPEC_DSCRI])

71421

+

71422

+(define_mode_iterator D64_D128 [DD TD])

71423

+

71424

+(define_mode_attr dfp_suffix [(DD "")

71425

+ (TD "q")])

71426

+

71427

+(define_insn "dfp_ddedpd_<mode>"

71428

+ [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")

71429

+ (unspec:D64_D128 [(match_operand:QI 1 "const_0_to_3_operand" "i")

71430

+ (match_operand:D64_D128 2 "gpc_reg_operand" "d")]

71431

+ UNSPEC_DDEDPD))]

71432

+ "TARGET_DFP"

71433

+ "ddedpd<dfp_suffix> %1,%0,%2"

71434

+ [(set_attr "type" "fp")])

71435

+

71436

+(define_insn "dfp_denbcd_<mode>"

71437

+ [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")

71438

+ (unspec:D64_D128 [(match_operand:QI 1 "const_0_to_1_operand" "i")

71439

+ (match_operand:D64_D128 2 "gpc_reg_operand" "d")]

71440

+ UNSPEC_DENBCD))]

71441

+ "TARGET_DFP"

71442

+ "denbcd<dfp_suffix> %1,%0,%2"

71443

+ [(set_attr "type" "fp")])

71444

+

71445

+(define_insn "dfp_dxex_<mode>"

71446

+ [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")

71447

+ (unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d")]

71448

+ UNSPEC_DXEX))]

71449

+ "TARGET_DFP"

71450

+ "dxex<dfp_suffix> %0,%1"

71451

+ [(set_attr "type" "fp")])

71452

+

71453

+(define_insn "dfp_diex_<mode>"

71454

+ [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")

71455

+ (unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d")

71456

+ (match_operand:D64_D128 2 "gpc_reg_operand" "d")]

71457

+ UNSPEC_DXEX))]

71458

+ "TARGET_DFP"

71459

+ "diex<dfp_suffix> %0,%1,%2"

71460

+ [(set_attr "type" "fp")])

71461

+

71462

+(define_insn "dfp_dscli_<mode>"

71463

+ [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")

71464

+ (unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d")

71465

+ (match_operand:QI 2 "immediate_operand" "i")]

71466

+ UNSPEC_DSCLI))]

71467

+ "TARGET_DFP"

71468

+ "dscli<dfp_suffix> %0,%1,%2"

71469

+ [(set_attr "type" "fp")])

71470

+

71471

+(define_insn "dfp_dscri_<mode>"

71472

+ [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")

71473

+ (unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d")

71474

+ (match_operand:QI 2 "immediate_operand" "i")]

71475

+ UNSPEC_DSCRI))]

71476

+ "TARGET_DFP"

71477

+ "dscri<dfp_suffix> %0,%1,%2"

71478

+ [(set_attr "type" "fp")])

71479

Index: gcc/config/rs6000/t-linux64

71480

===================================================================

71481

--- a/src/gcc/config/rs6000/t-linux64 (.../tags/gcc_4_8_2_release)

71482

+++ b/src/gcc/config/rs6000/t-linux64 (.../branches/gcc-4_8-branch)

71483

@@ -25,8 +25,8 @@

71484

# it doesn't tell anything about the 32bit libraries on those systems. Set

71485

# MULTILIB_OSDIRNAMES according to what is found on the target.

71486

71487

-MULTILIB_OPTIONS = m64/m32

71488

-MULTILIB_DIRNAMES = 64 32

71489

-MULTILIB_EXTRA_OPTS = fPIC

71490

-MULTILIB_OSDIRNAMES = ../lib64$(call if_multiarch,:powerpc64-linux-gnu)

71491

-MULTILIB_OSDIRNAMES += $(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib)$(call if_multiarch,:powerpc-linux-gnu)

71492

+MULTILIB_OPTIONS := m64/m32

71493

+MULTILIB_DIRNAMES := 64 32

71494

+MULTILIB_EXTRA_OPTS :=

71495

+MULTILIB_OSDIRNAMES := m64=../lib64$(call if_multiarch,:powerpc64-linux-gnu)

71496

+MULTILIB_OSDIRNAMES += m32=$(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib)$(call if_multiarch,:powerpc-linux-gnu)

71497

Index: gcc/config/rs6000/sync.md

71498

===================================================================

71499

--- a/src/gcc/config/rs6000/sync.md (.../tags/gcc_4_8_2_release)

71500

+++ b/src/gcc/config/rs6000/sync.md (.../branches/gcc-4_8-branch)

71501

@@ -1,5 +1,5 @@

71502

;; Machine description for PowerPC synchronization instructions.

71503

71504

71505

;; Contributed by Geoffrey Keating.

71506

71507

;; This file is part of GCC.

71508

@@ -18,14 +18,23 @@

71509

;; along with GCC; see the file COPYING3. If not see

71510

;; <http://www.gnu.org/licenses/>.

71511

71512

-(define_mode_attr larx [(SI "lwarx") (DI "ldarx")])

71513

-(define_mode_attr stcx [(SI "stwcx.") (DI "stdcx.")])

71514

+(define_mode_attr larx [(QI "lbarx")

71515

+ (HI "lharx")

71516

+ (SI "lwarx")

71517

+ (DI "ldarx")

71518

+ (TI "lqarx")])

71519

71520

+(define_mode_attr stcx [(QI "stbcx.")

71521

+ (HI "sthcx.")

71522

+ (SI "stwcx.")

71523

+ (DI "stdcx.")

71524

+ (TI "stqcx.")])

71525

+

71526

(define_code_iterator FETCHOP [plus minus ior xor and])

71527

(define_code_attr fetchop_name

71528

[(plus "add") (minus "sub") (ior "or") (xor "xor") (and "and")])

71529

(define_code_attr fetchop_pred

71530

- [(plus "add_operand") (minus "gpc_reg_operand")

71531

+ [(plus "add_operand") (minus "int_reg_operand")

71532

(ior "logical_operand") (xor "logical_operand") (and "and_operand")])

71533

71534

(define_expand "mem_thread_fence"

71535

@@ -98,10 +107,17 @@

71536

"isync"

71537

[(set_attr "type" "isync")])

71538

71539

+;; Types that we should provide atomic instructions for.

71540

+(define_mode_iterator AINT [QI

71541

+ HI

71542

+ SI

71543

+ (DI "TARGET_POWERPC64")

71544

+ (TI "TARGET_SYNC_TI")])

71545

+

71546

;; The control dependency used for load dependency described

71547

;; in B.2.3 of the Power ISA 2.06B.

71548

(define_insn "loadsync_<mode>"

71549

- [(unspec_volatile:BLK [(match_operand:INT1 0 "register_operand" "r")]

71550

+ [(unspec_volatile:BLK [(match_operand:AINT 0 "register_operand" "r")]

71551

UNSPECV_ISYNC)

71552

(clobber (match_scratch:CC 1 "=y"))]

71553

""

71554

@@ -109,19 +125,74 @@

71555

[(set_attr "type" "isync")

71556

(set_attr "length" "12")])

71557

71558

+(define_insn "load_quadpti"

71559

+ [(set (match_operand:PTI 0 "quad_int_reg_operand" "=&r")

71560

+ (unspec:PTI

71561

+ [(match_operand:TI 1 "quad_memory_operand" "wQ")] UNSPEC_LSQ))]

71562

+ "TARGET_SYNC_TI

71563

+ && !reg_mentioned_p (operands[0], operands[1])"

71564

+ "lq %0,%1"

71565

+ [(set_attr "type" "load")

71566

+ (set_attr "length" "4")])

71567

+

71568

(define_expand "atomic_load<mode>"

71569

- [(set (match_operand:INT1 0 "register_operand" "") ;; output

71570

- (match_operand:INT1 1 "memory_operand" "")) ;; memory

71571

+ [(set (match_operand:AINT 0 "register_operand" "") ;; output

71572

+ (match_operand:AINT 1 "memory_operand" "")) ;; memory

71573

(use (match_operand:SI 2 "const_int_operand" ""))] ;; model

71574

""

71575

{

71576

+ if (<MODE>mode == TImode && !TARGET_SYNC_TI)

71577

+ FAIL;

71578

+

71579

enum memmodel model = (enum memmodel) INTVAL (operands[2]);

71580

71581

if (model == MEMMODEL_SEQ_CST)

71582

emit_insn (gen_hwsync ());

71583

71584

- emit_move_insn (operands[0], operands[1]);

71585

+ if (<MODE>mode != TImode)

71586

+ emit_move_insn (operands[0], operands[1]);

71587

+ else

71588

+ {

71589

+ rtx op0 = operands[0];

71590

+ rtx op1 = operands[1];

71591

+ rtx pti_reg = gen_reg_rtx (PTImode);

71592

71593

+ // Can't have indexed address for 'lq'

71594

+ if (indexed_address (XEXP (op1, 0), TImode))

71595

+ {

71596

+ rtx old_addr = XEXP (op1, 0);

71597

+ rtx new_addr = force_reg (Pmode, old_addr);

71598

+ operands[1] = op1 = replace_equiv_address (op1, new_addr);

71599

+ }

71600

+

71601

+ emit_insn (gen_load_quadpti (pti_reg, op1));

71602

+

71603

+ /* For 4.8 we need to do explicit dword copies, even in big endian mode,

71604

+ unless we are using the LRA register allocator. The 4.9 register

71605

+ allocator is smart enough to assign an even/odd pair. */

71606

+ if (WORDS_BIG_ENDIAN && rs6000_lra_flag)

71607

+ emit_move_insn (op0, gen_lowpart (TImode, pti_reg));

71608

+ else

71609

+ {

71610

+ rtx op0_lo = gen_lowpart (DImode, op0);

71611

+ rtx op0_hi = gen_highpart (DImode, op0);

71612

+ rtx pti_lo = gen_lowpart (DImode, pti_reg);

71613

+ rtx pti_hi = gen_highpart (DImode, pti_reg);

71614

+

71615

+ emit_insn (gen_rtx_CLOBBER (VOIDmode, op0));

71616

+ if (WORDS_BIG_ENDIAN)

71617

+ {

71618

+ emit_move_insn (op0_hi, pti_hi);

71619

+ emit_move_insn (op0_lo, pti_lo);

71620

+ }

71621

+ else

71622

+ {

71623

+ emit_move_insn (op0_hi, pti_lo);

71624

+ emit_move_insn (op0_lo, pti_hi);

71625

+ }

71626

+ }

71627

+ }

71628

+

71629

switch (model)

71630

{

71631

case MEMMODEL_RELAXED:

71632

@@ -129,16 +200,7 @@

71633

case MEMMODEL_CONSUME:

71634

case MEMMODEL_ACQUIRE:

71635

case MEMMODEL_SEQ_CST:

71636

- if (GET_MODE (operands[0]) == QImode)

71637

- emit_insn (gen_loadsync_qi (operands[0]));

71638

- else if (GET_MODE (operands[0]) == HImode)

71639

- emit_insn (gen_loadsync_hi (operands[0]));

71640

- else if (GET_MODE (operands[0]) == SImode)

71641

- emit_insn (gen_loadsync_si (operands[0]));

71642

- else if (GET_MODE (operands[0]) == DImode)

71643

- emit_insn (gen_loadsync_di (operands[0]));

71644

- else

71645

- gcc_unreachable ();

71646

+ emit_insn (gen_loadsync_<mode> (operands[0]));

71647

break;

71648

default:

71649

gcc_unreachable ();

71650

@@ -146,12 +208,24 @@

71651

DONE;

71652

})

71653

71654

+(define_insn "store_quadpti"

71655

+ [(set (match_operand:PTI 0 "quad_memory_operand" "=wQ")

71656

+ (unspec:PTI

71657

+ [(match_operand:PTI 1 "quad_int_reg_operand" "r")] UNSPEC_LSQ))]

71658

+ "TARGET_SYNC_TI"

71659

+ "stq %1,%0"

71660

+ [(set_attr "type" "store")

71661

+ (set_attr "length" "4")])

71662

+

71663

(define_expand "atomic_store<mode>"

71664

- [(set (match_operand:INT1 0 "memory_operand" "") ;; memory

71665

- (match_operand:INT1 1 "register_operand" "")) ;; input

71666

+ [(set (match_operand:AINT 0 "memory_operand" "") ;; memory

71667

+ (match_operand:AINT 1 "register_operand" "")) ;; input

71668

(use (match_operand:SI 2 "const_int_operand" ""))] ;; model

71669

""

71670

{

71671

+ if (<MODE>mode == TImode && !TARGET_SYNC_TI)

71672

+ FAIL;

71673

+

71674

enum memmodel model = (enum memmodel) INTVAL (operands[2]);

71675

switch (model)

71676

{

71677

@@ -166,18 +240,65 @@

71678

default:

71679

gcc_unreachable ();

71680

}

71681

- emit_move_insn (operands[0], operands[1]);

71682

+ if (<MODE>mode != TImode)

71683

+ emit_move_insn (operands[0], operands[1]);

71684

+ else

71685

+ {

71686

+ rtx op0 = operands[0];

71687

+ rtx op1 = operands[1];

71688

+ rtx pti_reg = gen_reg_rtx (PTImode);

71689

+

71690

+ // Can't have indexed address for 'stq'

71691

+ if (indexed_address (XEXP (op0, 0), TImode))

71692

+ {

71693

+ rtx old_addr = XEXP (op0, 0);

71694

+ rtx new_addr = force_reg (Pmode, old_addr);

71695

+ operands[0] = op0 = replace_equiv_address (op0, new_addr);

71696

+ }

71697

+

71698

+ /* For 4.8 we need to do explicit dword copies, even in big endian mode,

71699

+ unless we are using the LRA register allocator. The 4.9 register

71700

+ allocator is smart enough to assign an even/odd pair. */

71701

+ if (WORDS_BIG_ENDIAN && rs6000_lra_flag)

71702

+ emit_move_insn (pti_reg, gen_lowpart (PTImode, op1));

71703

+ else

71704

+ {

71705

+ rtx op1_lo = gen_lowpart (DImode, op1);

71706

+ rtx op1_hi = gen_highpart (DImode, op1);

71707

+ rtx pti_lo = gen_lowpart (DImode, pti_reg);

71708

+ rtx pti_hi = gen_highpart (DImode, pti_reg);

71709

+

71710

+ emit_insn (gen_rtx_CLOBBER (VOIDmode, pti_reg));

71711

+ if (WORDS_BIG_ENDIAN)

71712

+ {

71713

+ emit_move_insn (pti_hi, op1_hi);

71714

+ emit_move_insn (pti_lo, op1_lo);

71715

+ }

71716

+ else

71717

+ {

71718

+ emit_move_insn (pti_hi, op1_lo);

71719

+ emit_move_insn (pti_lo, op1_hi);

71720

+ }

71721

+ }

71722

+

71723

+ emit_insn (gen_store_quadpti (gen_lowpart (PTImode, op0), pti_reg));

71724

+ }

71725

+

71726

DONE;

71727

})

71728

71729

-;; ??? Power ISA 2.06B says that there *is* a load-{byte,half}-and-reserve

71730

-;; opcode that is "phased-in". Not implemented as of Power7, so not yet used,

71731

-;; but let's prepare the macros anyway.

71732

+;; Any supported integer mode that has atomic l<x>arx/st<x>cx. instrucitons

71733

+;; other than the quad memory operations, which have special restrictions.

71734

+;; Byte/halfword atomic instructions were added in ISA 2.06B, but were phased

71735

+;; in and did not show up until power8. TImode atomic lqarx/stqcx. require

71736

+;; special handling due to even/odd register requirements.

71737

+(define_mode_iterator ATOMIC [(QI "TARGET_SYNC_HI_QI")

71738

+ (HI "TARGET_SYNC_HI_QI")

71739

+ SI

71740

+ (DI "TARGET_POWERPC64")])

71741

71742

-(define_mode_iterator ATOMIC [SI (DI "TARGET_POWERPC64")])

71743

-

71744

(define_insn "load_locked<mode>"

71745

- [(set (match_operand:ATOMIC 0 "gpc_reg_operand" "=r")

71746

+ [(set (match_operand:ATOMIC 0 "int_reg_operand" "=r")

71747

(unspec_volatile:ATOMIC

71748

[(match_operand:ATOMIC 1 "memory_operand" "Z")] UNSPECV_LL))]

71749

""

71750

@@ -184,21 +305,159 @@

71751

"<larx> %0,%y1"

71752

[(set_attr "type" "load_l")])

71753

71754

+(define_insn "load_locked<QHI:mode>_si"

71755

+ [(set (match_operand:SI 0 "int_reg_operand" "=r")

71756

+ (unspec_volatile:SI

71757

+ [(match_operand:QHI 1 "memory_operand" "Z")] UNSPECV_LL))]

71758

+ "TARGET_SYNC_HI_QI"

71759

+ "<QHI:larx> %0,%y1"

71760

+ [(set_attr "type" "load_l")])

71761

+

71762

+;; Use PTImode to get even/odd register pairs.

71763

+

71764

+;; Use a temporary register to force getting an even register for the

71765

+;; lqarx/stqcrx. instructions. Under AT 7.0, we need use an explicit copy,

71766

+;; even in big endian mode, unless we are using the LRA register allocator. In

71767

+;; GCC 4.9, the register allocator is smart enough to assign a even/odd

71768

+;; register pair.

71769

+

71770

+;; On little endian systems where non-atomic quad word load/store instructions

71771

+;; are not used, the address can be register+offset, so make sure the address

71772

+;; is indexed or indirect before register allocation.

71773

+

71774

+(define_expand "load_lockedti"

71775

+ [(use (match_operand:TI 0 "quad_int_reg_operand" ""))

71776

+ (use (match_operand:TI 1 "memory_operand" ""))]

71777

+ "TARGET_SYNC_TI"

71778

+{

71779

+ rtx op0 = operands[0];

71780

+ rtx op1 = operands[1];

71781

+ rtx pti = gen_reg_rtx (PTImode);

71782

+

71783

+ if (!indexed_or_indirect_operand (op1, TImode))

71784

+ {

71785

+ rtx old_addr = XEXP (op1, 0);

71786

+ rtx new_addr = force_reg (Pmode, old_addr);

71787

+ operands[1] = op1 = change_address (op1, TImode, new_addr);

71788

+ }

71789

+

71790

+ emit_insn (gen_load_lockedpti (pti, op1));

71791

+ if (WORDS_BIG_ENDIAN && rs6000_lra_flag)

71792

+ emit_move_insn (op0, gen_lowpart (TImode, pti));

71793

+ else

71794

+ {

71795

+ rtx op0_lo = gen_lowpart (DImode, op0);

71796

+ rtx op0_hi = gen_highpart (DImode, op0);

71797

+ rtx pti_lo = gen_lowpart (DImode, pti);

71798

+ rtx pti_hi = gen_highpart (DImode, pti);

71799

+

71800

+ emit_insn (gen_rtx_CLOBBER (VOIDmode, op0));

71801

+ if (WORDS_BIG_ENDIAN)

71802

+ {

71803

+ emit_move_insn (op0_hi, pti_hi);

71804

+ emit_move_insn (op0_lo, pti_lo);

71805

+ }

71806

+ else

71807

+ {

71808

+ emit_move_insn (op0_hi, pti_lo);

71809

+ emit_move_insn (op0_lo, pti_hi);

71810

+ }

71811

+ }

71812

+ DONE;

71813

+})

71814

+

71815

+(define_insn "load_lockedpti"

71816

+ [(set (match_operand:PTI 0 "quad_int_reg_operand" "=&r")

71817

+ (unspec_volatile:PTI

71818

+ [(match_operand:TI 1 "indexed_or_indirect_operand" "Z")] UNSPECV_LL))]

71819

+ "TARGET_SYNC_TI

71820

+ && !reg_mentioned_p (operands[0], operands[1])

71821

+ && quad_int_reg_operand (operands[0], PTImode)"

71822

+ "lqarx %0,%y1"

71823

+ [(set_attr "type" "load_l")])

71824

+

71825

(define_insn "store_conditional<mode>"

71826

[(set (match_operand:CC 0 "cc_reg_operand" "=x")

71827

(unspec_volatile:CC [(const_int 0)] UNSPECV_SC))

71828

(set (match_operand:ATOMIC 1 "memory_operand" "=Z")

71829

- (match_operand:ATOMIC 2 "gpc_reg_operand" "r"))]

71830

+ (match_operand:ATOMIC 2 "int_reg_operand" "r"))]

71831

""

71832

"<stcx> %2,%y1"

71833

[(set_attr "type" "store_c")])

71834

71835

+;; Use a temporary register to force getting an even register for the

71836

+;; lqarx/stqcrx. instructions. Under AT 7.0, we need use an explicit copy,

71837

+;; even in big endian mode. In GCC 4.9, the register allocator is smart enough

71838

+;; to assign a even/odd register pair.

71839

+

71840

+;; On little endian systems where non-atomic quad word load/store instructions

71841

+;; are not used, the address can be register+offset, so make sure the address

71842

+;; is indexed or indirect before register allocation.

71843

+

71844

+(define_expand "store_conditionalti"

71845

+ [(use (match_operand:CC 0 "cc_reg_operand" ""))

71846

+ (use (match_operand:TI 1 "memory_operand" ""))

71847

+ (use (match_operand:TI 2 "quad_int_reg_operand" ""))]

71848

+ "TARGET_SYNC_TI"

71849

+{

71850

+ rtx op0 = operands[0];

71851

+ rtx op1 = operands[1];

71852

+ rtx op2 = operands[2];

71853

+ rtx addr = XEXP (op1, 0);

71854

+ rtx pti_mem;

71855

+ rtx pti_reg;

71856

+

71857

+ if (!indexed_or_indirect_operand (op1, TImode))

71858

+ {

71859

+ rtx new_addr = force_reg (Pmode, addr);

71860

+ operands[1] = op1 = change_address (op1, TImode, new_addr);

71861

+ addr = new_addr;

71862

+ }

71863

+

71864

+ pti_mem = change_address (op1, PTImode, addr);

71865

+ pti_reg = gen_reg_rtx (PTImode);

71866

+

71867

+ if (WORDS_BIG_ENDIAN && rs6000_lra_flag)

71868

+ emit_move_insn (pti_reg, gen_lowpart (PTImode, op2));

71869

+ else

71870

+ {

71871

+ rtx op2_lo = gen_lowpart (DImode, op2);

71872

+ rtx op2_hi = gen_highpart (DImode, op2);

71873

+ rtx pti_lo = gen_lowpart (DImode, pti_reg);

71874

+ rtx pti_hi = gen_highpart (DImode, pti_reg);

71875

+

71876

+ emit_insn (gen_rtx_CLOBBER (VOIDmode, op0));

71877

+ if (WORDS_BIG_ENDIAN)

71878

+ {

71879

+ emit_move_insn (pti_hi, op2_hi);

71880

+ emit_move_insn (pti_lo, op2_lo);

71881

+ }

71882

+ else

71883

+ {

71884

+ emit_move_insn (pti_hi, op2_lo);

71885

+ emit_move_insn (pti_lo, op2_hi);

71886

+ }

71887

+ }

71888

+

71889

+ emit_insn (gen_store_conditionalpti (op0, pti_mem, pti_reg));

71890

+ DONE;

71891

+})

71892

+

71893

+(define_insn "store_conditionalpti"

71894

+ [(set (match_operand:CC 0 "cc_reg_operand" "=x")

71895

+ (unspec_volatile:CC [(const_int 0)] UNSPECV_SC))

71896

+ (set (match_operand:PTI 1 "indexed_or_indirect_operand" "=Z")

71897

+ (match_operand:PTI 2 "quad_int_reg_operand" "r"))]

71898

+ "TARGET_SYNC_TI && quad_int_reg_operand (operands[2], PTImode)"

71899

+ "stqcx. %2,%y1"

71900

+ [(set_attr "type" "store_c")])

71901

+

71902

(define_expand "atomic_compare_and_swap<mode>"

71903

- [(match_operand:SI 0 "gpc_reg_operand" "") ;; bool out

71904

- (match_operand:INT1 1 "gpc_reg_operand" "") ;; val out

71905

- (match_operand:INT1 2 "memory_operand" "") ;; memory

71906

- (match_operand:INT1 3 "reg_or_short_operand" "") ;; expected

71907

- (match_operand:INT1 4 "gpc_reg_operand" "") ;; desired

71908

+ [(match_operand:SI 0 "int_reg_operand" "") ;; bool out

71909

+ (match_operand:AINT 1 "int_reg_operand" "") ;; val out

71910

+ (match_operand:AINT 2 "memory_operand" "") ;; memory

71911

+ (match_operand:AINT 3 "reg_or_short_operand" "") ;; expected

71912

+ (match_operand:AINT 4 "int_reg_operand" "") ;; desired

71913

(match_operand:SI 5 "const_int_operand" "") ;; is_weak

71914

(match_operand:SI 6 "const_int_operand" "") ;; model succ

71915

(match_operand:SI 7 "const_int_operand" "")] ;; model fail

71916

@@ -209,9 +468,9 @@

71917

})

71918

71919

(define_expand "atomic_exchange<mode>"

71920

- [(match_operand:INT1 0 "gpc_reg_operand" "") ;; output

71921

- (match_operand:INT1 1 "memory_operand" "") ;; memory

71922

- (match_operand:INT1 2 "gpc_reg_operand" "") ;; input

71923

+ [(match_operand:AINT 0 "int_reg_operand" "") ;; output

71924

+ (match_operand:AINT 1 "memory_operand" "") ;; memory

71925

+ (match_operand:AINT 2 "int_reg_operand" "") ;; input

71926

(match_operand:SI 3 "const_int_operand" "")] ;; model

71927

""

71928

{

71929

@@ -220,9 +479,9 @@

71930

})

71931

71932

(define_expand "atomic_<fetchop_name><mode>"

71933

- [(match_operand:INT1 0 "memory_operand" "") ;; memory

71934

- (FETCHOP:INT1 (match_dup 0)

71935

- (match_operand:INT1 1 "<fetchop_pred>" "")) ;; operand

71936

+ [(match_operand:AINT 0 "memory_operand" "") ;; memory

71937

+ (FETCHOP:AINT (match_dup 0)

71938

+ (match_operand:AINT 1 "<fetchop_pred>" "")) ;; operand

71939

(match_operand:SI 2 "const_int_operand" "")] ;; model

71940

""

71941

{

71942

@@ -232,8 +491,8 @@

71943

})

71944

71945

(define_expand "atomic_nand<mode>"

71946

- [(match_operand:INT1 0 "memory_operand" "") ;; memory

71947

- (match_operand:INT1 1 "gpc_reg_operand" "") ;; operand

71948

+ [(match_operand:AINT 0 "memory_operand" "") ;; memory

71949

+ (match_operand:AINT 1 "int_reg_operand" "") ;; operand

71950

(match_operand:SI 2 "const_int_operand" "")] ;; model

71951

""

71952

{

71953

@@ -243,10 +502,10 @@

71954

})

71955

71956

(define_expand "atomic_fetch_<fetchop_name><mode>"

71957

- [(match_operand:INT1 0 "gpc_reg_operand" "") ;; output

71958

- (match_operand:INT1 1 "memory_operand" "") ;; memory

71959

- (FETCHOP:INT1 (match_dup 1)

71960

- (match_operand:INT1 2 "<fetchop_pred>" "")) ;; operand

71961

+ [(match_operand:AINT 0 "int_reg_operand" "") ;; output

71962

+ (match_operand:AINT 1 "memory_operand" "") ;; memory

71963

+ (FETCHOP:AINT (match_dup 1)

71964

+ (match_operand:AINT 2 "<fetchop_pred>" "")) ;; operand

71965

(match_operand:SI 3 "const_int_operand" "")] ;; model

71966

""

71967

{

71968

@@ -256,9 +515,9 @@

71969

})

71970

71971

(define_expand "atomic_fetch_nand<mode>"

71972

- [(match_operand:INT1 0 "gpc_reg_operand" "") ;; output

71973

- (match_operand:INT1 1 "memory_operand" "") ;; memory

71974

- (match_operand:INT1 2 "gpc_reg_operand" "") ;; operand

71975

+ [(match_operand:AINT 0 "int_reg_operand" "") ;; output

71976

+ (match_operand:AINT 1 "memory_operand" "") ;; memory

71977

+ (match_operand:AINT 2 "int_reg_operand" "") ;; operand

71978

(match_operand:SI 3 "const_int_operand" "")] ;; model

71979

""

71980

{

71981

@@ -268,10 +527,10 @@

71982

})

71983

71984

(define_expand "atomic_<fetchop_name>_fetch<mode>"

71985

- [(match_operand:INT1 0 "gpc_reg_operand" "") ;; output

71986

- (match_operand:INT1 1 "memory_operand" "") ;; memory

71987

- (FETCHOP:INT1 (match_dup 1)

71988

- (match_operand:INT1 2 "<fetchop_pred>" "")) ;; operand

71989

+ [(match_operand:AINT 0 "int_reg_operand" "") ;; output

71990

+ (match_operand:AINT 1 "memory_operand" "") ;; memory

71991

+ (FETCHOP:AINT (match_dup 1)

71992

+ (match_operand:AINT 2 "<fetchop_pred>" "")) ;; operand

71993

(match_operand:SI 3 "const_int_operand" "")] ;; model

71994

""

71995

{

71996

@@ -281,9 +540,9 @@

71997

})

71998

71999

(define_expand "atomic_nand_fetch<mode>"

72000

- [(match_operand:INT1 0 "gpc_reg_operand" "") ;; output

72001

- (match_operand:INT1 1 "memory_operand" "") ;; memory

72002

- (match_operand:INT1 2 "gpc_reg_operand" "") ;; operand

72003

+ [(match_operand:AINT 0 "int_reg_operand" "") ;; output

72004

+ (match_operand:AINT 1 "memory_operand" "") ;; memory

72005

+ (match_operand:AINT 2 "int_reg_operand" "") ;; operand

72006

(match_operand:SI 3 "const_int_operand" "")] ;; model

72007

""

72008

{

72009

Index: gcc/config/rs6000/crypto.md

72010

===================================================================

72011

--- a/src/gcc/config/rs6000/crypto.md (.../tags/gcc_4_8_2_release)

72012

+++ b/src/gcc/config/rs6000/crypto.md (.../branches/gcc-4_8-branch)

72013

@@ -0,0 +1,101 @@

72014

+;; Cryptographic instructions added in ISA 2.07

72015

72016

+;; Contributed by Michael Meissner (meissner@linux.vnet.ibm.com)

72017

+

72018

+;; This file is part of GCC.

72019

+

72020

+;; GCC is free software; you can redistribute it and/or modify it

72021

+;; under the terms of the GNU General Public License as published

72022

+;; by the Free Software Foundation; either version 3, or (at your

72023

+;; option) any later version.

72024

+

72025

+;; GCC is distributed in the hope that it will be useful, but WITHOUT

72026

+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY

72027

+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public

72028

+;; License for more details.

72029

+

72030

+;; You should have received a copy of the GNU General Public License

72031

+;; along with GCC; see the file COPYING3. If not see

72032

+;; <http://www.gnu.org/licenses/>.

72033

+

72034

+(define_c_enum "unspec"

72035

+ [UNSPEC_VCIPHER

72036

+ UNSPEC_VNCIPHER

72037

+ UNSPEC_VCIPHERLAST

72038

+ UNSPEC_VNCIPHERLAST

72039

+ UNSPEC_VSBOX

72040

+ UNSPEC_VSHASIGMA

72041

+ UNSPEC_VPERMXOR

72042

+ UNSPEC_VPMSUM])

72043

+

72044

+;; Iterator for VPMSUM/VPERMXOR

72045

+(define_mode_iterator CR_mode [V16QI V8HI V4SI V2DI])

72046

+

72047

+(define_mode_attr CR_char [(V16QI "b")

72048

+ (V8HI "h")

72049

+ (V4SI "w")

72050

+ (V2DI "d")])

72051

+

72052

+;; Iterator for VSHASIGMAD/VSHASIGMAW

72053

+(define_mode_iterator CR_hash [V4SI V2DI])

72054

+

72055

+;; Iterator for the other crypto functions

72056

+(define_int_iterator CR_code [UNSPEC_VCIPHER

72057

+ UNSPEC_VNCIPHER

72058

+ UNSPEC_VCIPHERLAST

72059

+ UNSPEC_VNCIPHERLAST])

72060

+

72061

+(define_int_attr CR_insn [(UNSPEC_VCIPHER "vcipher")

72062

+ (UNSPEC_VNCIPHER "vncipher")

72063

+ (UNSPEC_VCIPHERLAST "vcipherlast")

72064

+ (UNSPEC_VNCIPHERLAST "vncipherlast")])

72065

+

72066

+;; 2 operand crypto instructions

72067

+(define_insn "crypto_<CR_insn>"

72068

+ [(set (match_operand:V2DI 0 "register_operand" "=v")

72069

+ (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "v")

72070

+ (match_operand:V2DI 2 "register_operand" "v")]

72071

+ CR_code))]

72072

+ "TARGET_CRYPTO"

72073

+ "<CR_insn> %0,%1,%2"

72074

+ [(set_attr "type" "crypto")])

72075

+

72076

+(define_insn "crypto_vpmsum<CR_char>"

72077

+ [(set (match_operand:CR_mode 0 "register_operand" "=v")

72078

+ (unspec:CR_mode [(match_operand:CR_mode 1 "register_operand" "v")

72079

+ (match_operand:CR_mode 2 "register_operand" "v")]

72080

+ UNSPEC_VPMSUM))]

72081

+ "TARGET_CRYPTO"

72082

+ "vpmsum<CR_char> %0,%1,%2"

72083

+ [(set_attr "type" "crypto")])

72084

+

72085

+;; 3 operand crypto instructions

72086

+(define_insn "crypto_vpermxor_<mode>"

72087

+ [(set (match_operand:CR_mode 0 "register_operand" "=v")

72088

+ (unspec:CR_mode [(match_operand:CR_mode 1 "register_operand" "v")

72089

+ (match_operand:CR_mode 2 "register_operand" "v")

72090

+ (match_operand:CR_mode 3 "register_operand" "v")]

72091

+ UNSPEC_VPERMXOR))]

72092

+ "TARGET_CRYPTO"

72093

+ "vpermxor %0,%1,%2,%3"

72094

+ [(set_attr "type" "crypto")])

72095

+

72096

+;; 1 operand crypto instruction

72097

+(define_insn "crypto_vsbox"

72098

+ [(set (match_operand:V2DI 0 "register_operand" "=v")

72099

+ (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "v")]

72100

+ UNSPEC_VSBOX))]

72101

+ "TARGET_CRYPTO"

72102

+ "vsbox %0,%1"

72103

+ [(set_attr "type" "crypto")])

72104

+

72105

+;; Hash crypto instructions

72106

+(define_insn "crypto_vshasigma<CR_char>"

72107

+ [(set (match_operand:CR_hash 0 "register_operand" "=v")

72108

+ (unspec:CR_hash [(match_operand:CR_hash 1 "register_operand" "v")

72109

+ (match_operand:SI 2 "const_0_to_1_operand" "n")

72110

+ (match_operand:SI 3 "const_0_to_15_operand" "n")]

72111

+ UNSPEC_VSHASIGMA))]

72112

+ "TARGET_CRYPTO"

72113

+ "vshasigma<CR_char> %0,%1,%2,%3"

72114

+ [(set_attr "type" "crypto")])

72115

Index: gcc/config/rs6000/rs6000.md

72116

===================================================================

72117

--- a/src/gcc/config/rs6000/rs6000.md (.../tags/gcc_4_8_2_release)

72118

+++ b/src/gcc/config/rs6000/rs6000.md (.../branches/gcc-4_8-branch)

72119

@@ -25,10 +25,14 @@

72120

;;

72121

72122

(define_constants

72123

- [(STACK_POINTER_REGNUM 1)

72124

+ [(FIRST_GPR_REGNO 0)

72125

+ (STACK_POINTER_REGNUM 1)

72126

(TOC_REGNUM 2)

72127

(STATIC_CHAIN_REGNUM 11)

72128

(HARD_FRAME_POINTER_REGNUM 31)

72129

+ (LAST_GPR_REGNO 31)

72130

+ (FIRST_FPR_REGNO 32)

72131

+ (LAST_FPR_REGNO 63)

72132

(LR_REGNO 65)

72133

(CTR_REGNO 66)

72134

(ARG_POINTER_REGNUM 67)

72135

@@ -49,18 +53,9 @@

72136

(SPE_ACC_REGNO 111)

72137

(SPEFSCR_REGNO 112)

72138

(FRAME_POINTER_REGNUM 113)

72139

-

72140

- ; ABI defined stack offsets for storing the TOC pointer with AIX calls.

72141

- (TOC_SAVE_OFFSET_32BIT 20)

72142

- (TOC_SAVE_OFFSET_64BIT 40)

72143

-

72144

- ; Function TOC offset in the AIX function descriptor.

72145

- (AIX_FUNC_DESC_TOC_32BIT 4)

72146

- (AIX_FUNC_DESC_TOC_64BIT 8)

72147

-

72148

- ; Static chain offset in the AIX function descriptor.

72149

- (AIX_FUNC_DESC_SC_32BIT 8)

72150

- (AIX_FUNC_DESC_SC_64BIT 16)

72151

+ (TFHAR_REGNO 114)

72152

+ (TFIAR_REGNO 115)

72153

+ (TEXASR_REGNO 116)

72154

])

72155

72156

;;

72157

@@ -123,6 +118,22 @@

72158

UNSPEC_LFIWZX

72159

UNSPEC_FCTIWUZ

72160

UNSPEC_GRP_END_NOP

72161

+ UNSPEC_P8V_FMRGOW

72162

+ UNSPEC_P8V_MTVSRWZ

72163

+ UNSPEC_P8V_RELOAD_FROM_GPR

72164

+ UNSPEC_P8V_MTVSRD

72165

+ UNSPEC_P8V_XXPERMDI

72166

+ UNSPEC_P8V_RELOAD_FROM_VSX

72167

+ UNSPEC_ADDG6S

72168

+ UNSPEC_CDTBCD

72169

+ UNSPEC_CBCDTD

72170

+ UNSPEC_DIVE

72171

+ UNSPEC_DIVEO

72172

+ UNSPEC_DIVEU

72173

+ UNSPEC_DIVEUO

72174

+ UNSPEC_UNPACK_128BIT

72175

+ UNSPEC_PACK_128BIT

72176

+ UNSPEC_LSQ

72177

])

72178

72179

;;

72180

@@ -142,7 +153,7 @@

72181

72182

;; Define an insn type attribute. This is used in function unit delay

72183

;; computations.

72184

-(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,vecdouble,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel,popcnt"

72185

+(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,vecdouble,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel,popcnt,crypto,htm"

72186

(const_string "integer"))

72187

72188

;; Define floating point instruction sub-types for use with Xfpu.md

72189

@@ -164,7 +175,7 @@

72190

;; Processor type -- this attribute must exactly match the processor_type

72191

;; enumeration in rs6000.h.

72192

72193

-(define_attr "cpu" "rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,power4,power5,power6,power7,cell,ppca2,titan"

72194

+(define_attr "cpu" "rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,power4,power5,power6,power7,cell,ppca2,titan,power8"

72195

(const (symbol_ref "rs6000_cpu_attr")))

72196

72197

72198

@@ -197,6 +208,7 @@

72199

(include "power5.md")

72200

(include "power6.md")

72201

(include "power7.md")

72202

+(include "power8.md")

72203

(include "cell.md")

72204

(include "xfpu.md")

72205

(include "a2.md")

72206

@@ -215,7 +227,7 @@

72207

(define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])

72208

72209

; Any supported integer mode.

72210

-(define_mode_iterator INT [QI HI SI DI TI])

72211

+(define_mode_iterator INT [QI HI SI DI TI PTI])

72212

72213

; Any supported integer mode that fits in one register.

72214

(define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])

72215

@@ -223,6 +235,12 @@

72216

; extend modes for DImode

72217

(define_mode_iterator QHSI [QI HI SI])

72218

72219

+; QImode or HImode for small atomic ops

72220

+(define_mode_iterator QHI [QI HI])

72221

+

72222

+; HImode or SImode for sign extended fusion ops

72223

+(define_mode_iterator HSI [HI SI])

72224

+

72225

; SImode or DImode, even if DImode doesn't fit in GPRs.

72226

(define_mode_iterator SDI [SI DI])

72227

72228

@@ -230,6 +248,10 @@

72229

; (one with a '.') will compare; and the size used for arithmetic carries.

72230

(define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])

72231

72232

+; Iterator to add PTImode along with TImode (TImode can go in VSX registers,

72233

+; PTImode is GPR only)

72234

+(define_mode_iterator TI2 [TI PTI])

72235

+

72236

; Any hardware-supported floating-point mode

72237

(define_mode_iterator FP [

72238

(SF "TARGET_HARD_FLOAT

72239

@@ -253,6 +275,50 @@

72240

(V2DF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DFmode)")

72241

])

72242

72243

+; Floating point move iterators to combine binary and decimal moves

72244

+(define_mode_iterator FMOVE32 [SF SD])

72245

+(define_mode_iterator FMOVE64 [DF DD])

72246

+(define_mode_iterator FMOVE64X [DI DF DD])

72247

+(define_mode_iterator FMOVE128 [(TF "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128")

72248

+ (TD "TARGET_HARD_FLOAT && TARGET_FPRS")])

72249

+

72250

+; Iterators for 128 bit types for direct move

72251

+(define_mode_iterator FMOVE128_GPR [(TI "TARGET_VSX_TIMODE")

72252

+ (V16QI "")

72253

+ (V8HI "")

72254

+ (V4SI "")

72255

+ (V4SF "")

72256

+ (V2DI "")

72257

+ (V2DF "")

72258

+ (V1TI "")])

72259

+

72260

+; Whether a floating point move is ok, don't allow SD without hardware FP

72261

+(define_mode_attr fmove_ok [(SF "")

72262

+ (DF "")

72263

+ (SD "TARGET_HARD_FLOAT && TARGET_FPRS")

72264

+ (DD "")])

72265

+

72266

+; Convert REAL_VALUE to the appropriate bits

72267

+(define_mode_attr real_value_to_target [(SF "REAL_VALUE_TO_TARGET_SINGLE")

72268

+ (DF "REAL_VALUE_TO_TARGET_DOUBLE")

72269

+ (SD "REAL_VALUE_TO_TARGET_DECIMAL32")

72270

+ (DD "REAL_VALUE_TO_TARGET_DECIMAL64")])

72271

+

72272

+; Definitions for load to 32-bit fpr register

72273

+(define_mode_attr f32_lr [(SF "f") (SD "wz")])

72274

+(define_mode_attr f32_lm [(SF "m") (SD "Z")])

72275

+(define_mode_attr f32_li [(SF "lfs%U1%X1 %0,%1") (SD "lfiwzx %0,%y1")])

72276

+(define_mode_attr f32_lv [(SF "lxsspx %x0,%y1") (SD "lxsiwzx %x0,%y1")])

72277

+

72278

+; Definitions for store from 32-bit fpr register

72279

+(define_mode_attr f32_sr [(SF "f") (SD "wx")])

72280

+(define_mode_attr f32_sm [(SF "m") (SD "Z")])

72281

+(define_mode_attr f32_si [(SF "stfs%U0%X0 %1,%0") (SD "stfiwx %1,%y0")])

72282

+(define_mode_attr f32_sv [(SF "stxsspx %x1,%y0") (SD "stxsiwzx %x1,%y0")])

72283

+

72284

+; Definitions for 32-bit fpr direct move

72285

+(define_mode_attr f32_dm [(SF "wn") (SD "wm")])

72286

+

72287

; These modes do not fit in integer registers in 32-bit mode.

72288

; but on e500v2, the gpr are 64 bit registers

72289

(define_mode_iterator DIFD [DI (DF "!TARGET_E500_DOUBLE") DD])

72290

@@ -263,6 +329,25 @@

72291

; Iterator for just SF/DF

72292

(define_mode_iterator SFDF [SF DF])

72293

72294

+; SF/DF suffix for traditional floating instructions

72295

+(define_mode_attr Ftrad [(SF "s") (DF "")])

72296

+

72297

+; SF/DF suffix for VSX instructions

72298

+(define_mode_attr Fvsx [(SF "sp") (DF "dp")])

72299

+

72300

+; SF/DF constraint for arithmetic on traditional floating point registers

72301

+(define_mode_attr Ff [(SF "f") (DF "d")])

72302

+

72303

+; SF/DF constraint for arithmetic on VSX registers

72304

+(define_mode_attr Fv [(SF "wy") (DF "ws")])

72305

+

72306

+; s/d suffix for things like fp_addsub_s/fp_addsub_d

72307

+(define_mode_attr Fs [(SF "s") (DF "d")])

72308

+

72309

+; FRE/FRES support

72310

+(define_mode_attr Ffre [(SF "fres") (DF "fre")])

72311

+(define_mode_attr FFRE [(SF "FRES") (DF "FRE")])

72312

+

72313

; Conditional returns.

72314

(define_code_iterator any_return [return simple_return])

72315

(define_code_attr return_pred [(return "direct_return ()")

72316

@@ -271,7 +356,14 @@

72317

72318

; Various instructions that come in SI and DI forms.

72319

; A generic w/d attribute, for things like cmpw/cmpd.

72320

-(define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])

72321

+(define_mode_attr wd [(QI "b")

72322

+ (HI "h")

72323

+ (SI "w")

72324

+ (DI "d")

72325

+ (V16QI "b")

72326

+ (V8HI "h")

72327

+ (V4SI "w")

72328

+ (V2DI "d")])

72329

72330

; DImode bits

72331

(define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])

72332

@@ -297,6 +389,8 @@

72333

72334

(define_mode_attr rreg [(SF "f")

72335

(DF "ws")

72336

+ (TF "f")

72337

+ (TD "f")

72338

(V4SF "wf")

72339

(V2DF "wd")])

72340

72341

@@ -311,6 +405,87 @@

72342

72343

(define_mode_attr TARGET_FLOAT [(SF "TARGET_SINGLE_FLOAT")

72344

(DF "TARGET_DOUBLE_FLOAT")])

72345

+

72346

+;; Mode iterator for logical operations on 128-bit types

72347

+(define_mode_iterator BOOL_128 [TI

72348

+ PTI

72349

+ (V16QI "TARGET_ALTIVEC")

72350

+ (V8HI "TARGET_ALTIVEC")

72351

+ (V4SI "TARGET_ALTIVEC")

72352

+ (V4SF "TARGET_ALTIVEC")

72353

+ (V2DI "TARGET_ALTIVEC")

72354

+ (V2DF "TARGET_ALTIVEC")

72355

+ (V1TI "TARGET_ALTIVEC")])

72356

+

72357

+;; For the GPRs we use 3 constraints for register outputs, two that are the

72358

+;; same as the output register, and a third where the output register is an

72359

+;; early clobber, so we don't have to deal with register overlaps. For the

72360

+;; vector types, we prefer to use the vector registers. For TI mode, allow

72361

+;; either.

72362

+

72363

+;; Mode attribute for boolean operation register constraints for output

72364

+(define_mode_attr BOOL_REGS_OUTPUT [(TI "&r,r,r,wa,v")

72365

+ (PTI "&r,r,r")

72366

+ (V16QI "wa,v,&?r,?r,?r")

72367

+ (V8HI "wa,v,&?r,?r,?r")

72368

+ (V4SI "wa,v,&?r,?r,?r")

72369

+ (V4SF "wa,v,&?r,?r,?r")

72370

+ (V2DI "wa,v,&?r,?r,?r")

72371

+ (V2DF "wa,v,&?r,?r,?r")

72372

+ (V1TI "wa,v,&?r,?r,?r")])

72373

+

72374

+;; Mode attribute for boolean operation register constraints for operand1

72375

+(define_mode_attr BOOL_REGS_OP1 [(TI "r,0,r,wa,v")

72376

+ (PTI "r,0,r")

72377

+ (V16QI "wa,v,r,0,r")

72378

+ (V8HI "wa,v,r,0,r")

72379

+ (V4SI "wa,v,r,0,r")

72380

+ (V4SF "wa,v,r,0,r")

72381

+ (V2DI "wa,v,r,0,r")

72382

+ (V2DF "wa,v,r,0,r")

72383

+ (V1TI "wa,v,r,0,r")])

72384

+

72385

+;; Mode attribute for boolean operation register constraints for operand2

72386

+(define_mode_attr BOOL_REGS_OP2 [(TI "r,r,0,wa,v")

72387

+ (PTI "r,r,0")

72388

+ (V16QI "wa,v,r,r,0")

72389

+ (V8HI "wa,v,r,r,0")

72390

+ (V4SI "wa,v,r,r,0")

72391

+ (V4SF "wa,v,r,r,0")

72392

+ (V2DI "wa,v,r,r,0")

72393

+ (V2DF "wa,v,r,r,0")

72394

+ (V1TI "wa,v,r,r,0")])

72395

+

72396

+;; Mode attribute for boolean operation register constraints for operand1

72397

+;; for one_cmpl. To simplify things, we repeat the constraint where 0

72398

+;; is used for operand1 or operand2

72399

+(define_mode_attr BOOL_REGS_UNARY [(TI "r,0,0,wa,v")

72400

+ (PTI "r,0,0")

72401

+ (V16QI "wa,v,r,0,0")

72402

+ (V8HI "wa,v,r,0,0")

72403

+ (V4SI "wa,v,r,0,0")

72404

+ (V4SF "wa,v,r,0,0")

72405

+ (V2DI "wa,v,r,0,0")

72406

+ (V2DF "wa,v,r,0,0")

72407

+ (V1TI "wa,v,r,0,0")])

72408

+

72409

+;; Mode attribute for the clobber of CC0 for AND expansion.

72410

+;; For the 128-bit types, we never do AND immediate, but we need to

72411

+;; get the correct number of X's for the number of operands.

72412

+(define_mode_attr BOOL_REGS_AND_CR0 [(TI "X,X,X,X,X")

72413

+ (PTI "X,X,X")

72414

+ (V16QI "X,X,X,X,X")

72415

+ (V8HI "X,X,X,X,X")

72416

+ (V4SI "X,X,X,X,X")

72417

+ (V4SF "X,X,X,X,X")

72418

+ (V2DI "X,X,X,X,X")

72419

+ (V2DF "X,X,X,X,X")

72420

+ (V1TI "X,X,X,X,X")])

72421

+

72422

+;; Mode attribute to give the correct type for integer divides

72423

+(define_mode_attr idiv_ldiv [(SI "idiv")

72424

+ (DI "ldiv")])

72425

+

72426

72427

;; Start with fixed-point load and store insns. Here we put only the more

72428

;; complex forms. Basic data transfer is done later.

72429

@@ -324,11 +499,19 @@

72430

(define_insn "*zero_extend<mode>di2_internal1"

72431

[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")

72432

(zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]

72433

- "TARGET_POWERPC64"

72434

+ "TARGET_POWERPC64 && (<MODE>mode != SImode || !TARGET_LFIWZX)"

72435

"@

72436

l<wd>z%U1%X1 %0,%1

72437

rldicl %0,%1,0,<dbits>"

72438

- [(set_attr "type" "load,*")])

72439

+ [(set_attr_alternative "type"

72440

+ [(if_then_else

72441

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

72442

+ (const_string "load_ux")

72443

+ (if_then_else

72444

+ (match_test "update_address_mem (operands[1], VOIDmode)")

72445

+ (const_string "load_u")

72446

+ (const_string "load")))

72447

+ (const_string "*")])])

72448

72449

(define_insn "*zero_extend<mode>di2_internal2"

72450

[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")

72451

@@ -382,6 +565,29 @@

72452

(const_int 0)))]

72453

"")

72454

72455

+(define_insn "*zero_extendsidi2_lfiwzx"

72456

+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wm,!wz,!wu")

72457

+ (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r,r,Z,Z")))]

72458

+ "TARGET_POWERPC64 && TARGET_LFIWZX"

72459

+ "@

72460

+ lwz%U1%X1 %0,%1

72461

+ rldicl %0,%1,0,32

72462

+ mtvsrwz %x0,%1

72463

+ lfiwzx %0,%y1

72464

+ lxsiwzx %x0,%y1"

72465

+ [(set_attr_alternative "type"

72466

+ [(if_then_else

72467

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

72468

+ (const_string "load_ux")

72469

+ (if_then_else

72470

+ (match_test "update_address_mem (operands[1], VOIDmode)")

72471

+ (const_string "load_u")

72472

+ (const_string "load")))

72473

+ (const_string "*")

72474

+ (const_string "mffgpr")

72475

+ (const_string "fpload")

72476

+ (const_string "fpload")])])

72477

+

72478

(define_insn "extendqidi2"

72479

[(set (match_operand:DI 0 "gpc_reg_operand" "=r")

72480

(sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]

72481

@@ -454,7 +660,15 @@

72482

"@

72483

lha%U1%X1 %0,%1

72484

extsh %0,%1"

72485

- [(set_attr "type" "load_ext,exts")])

72486

+ [(set_attr_alternative "type"

72487

+ [(if_then_else

72488

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

72489

+ (const_string "load_ext_ux")

72490

+ (if_then_else

72491

+ (match_test "update_address_mem (operands[1], VOIDmode)")

72492

+ (const_string "load_ext_u")

72493

+ (const_string "load_ext")))

72494

+ (const_string "exts")])])

72495

72496

(define_insn ""

72497

[(set (match_operand:DI 0 "gpc_reg_operand" "=r")

72498

@@ -521,16 +735,47 @@

72499

"TARGET_POWERPC64"

72500

"")

72501

72502

-(define_insn ""

72503

+(define_insn "*extendsidi2_lfiwax"

72504

+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wm,!wl,!wu")

72505

+ (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r,r,Z,Z")))]

72506

+ "TARGET_POWERPC64 && TARGET_LFIWAX"

72507

+ "@

72508

+ lwa%U1%X1 %0,%1

72509

+ extsw %0,%1

72510

+ mtvsrwa %x0,%1

72511

+ lfiwax %0,%y1

72512

+ lxsiwax %x0,%y1"

72513

+ [(set_attr_alternative "type"

72514

+ [(if_then_else

72515

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

72516

+ (const_string "load_ext_ux")

72517

+ (if_then_else

72518

+ (match_test "update_address_mem (operands[1], VOIDmode)")

72519

+ (const_string "load_ext_u")

72520

+ (const_string "load_ext")))

72521

+ (const_string "exts")

72522

+ (const_string "mffgpr")

72523

+ (const_string "fpload")

72524

+ (const_string "fpload")])])

72525

+

72526

+(define_insn "*extendsidi2_nocell"

72527

[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")

72528

(sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]

72529

- "TARGET_POWERPC64 && rs6000_gen_cell_microcode"

72530

+ "TARGET_POWERPC64 && rs6000_gen_cell_microcode && !TARGET_LFIWAX"

72531

"@

72532

lwa%U1%X1 %0,%1

72533

extsw %0,%1"

72534

- [(set_attr "type" "load_ext,exts")])

72535

+ [(set_attr_alternative "type"

72536

+ [(if_then_else

72537

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

72538

+ (const_string "load_ext_ux")

72539

+ (if_then_else

72540

+ (match_test "update_address_mem (operands[1], VOIDmode)")

72541

+ (const_string "load_ext_u")

72542

+ (const_string "load_ext")))

72543

+ (const_string "exts")])])

72544

72545

-(define_insn ""

72546

+(define_insn "*extendsidi2_nocell"

72547

[(set (match_operand:DI 0 "gpc_reg_operand" "=r")

72548

(sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")))]

72549

"TARGET_POWERPC64 && !rs6000_gen_cell_microcode"

72550

@@ -602,7 +847,15 @@

72551

"@

72552

lbz%U1%X1 %0,%1

72553

rlwinm %0,%1,0,0xff"

72554

- [(set_attr "type" "load,*")])

72555

+ [(set_attr_alternative "type"

72556

+ [(if_then_else

72557

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

72558

+ (const_string "load_ux")

72559

+ (if_then_else

72560

+ (match_test "update_address_mem (operands[1], VOIDmode)")

72561

+ (const_string "load_u")

72562

+ (const_string "load")))

72563

+ (const_string "*")])])

72564

72565

(define_insn ""

72566

[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")

72567

@@ -722,7 +975,15 @@

72568

"@

72569

lbz%U1%X1 %0,%1

72570

rlwinm %0,%1,0,0xff"

72571

- [(set_attr "type" "load,*")])

72572

+ [(set_attr_alternative "type"

72573

+ [(if_then_else

72574

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

72575

+ (const_string "load_ux")

72576

+ (if_then_else

72577

+ (match_test "update_address_mem (operands[1], VOIDmode)")

72578

+ (const_string "load_u")

72579

+ (const_string "load")))

72580

+ (const_string "*")])])

72581

72582

(define_insn ""

72583

[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")

72584

@@ -848,7 +1109,15 @@

72585

"@

72586

lhz%U1%X1 %0,%1

72587

rlwinm %0,%1,0,0xffff"

72588

- [(set_attr "type" "load,*")])

72589

+ [(set_attr_alternative "type"

72590

+ [(if_then_else

72591

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

72592

+ (const_string "load_ux")

72593

+ (if_then_else

72594

+ (match_test "update_address_mem (operands[1], VOIDmode)")

72595

+ (const_string "load_u")

72596

+ (const_string "load")))

72597

+ (const_string "*")])])

72598

72599

(define_insn ""

72600

[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")

72601

@@ -915,7 +1184,15 @@

72602

"@

72603

lha%U1%X1 %0,%1

72604

extsh %0,%1"

72605

- [(set_attr "type" "load_ext,exts")])

72606

+ [(set_attr_alternative "type"

72607

+ [(if_then_else

72608

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

72609

+ (const_string "load_ext_ux")

72610

+ (if_then_else

72611

+ (match_test "update_address_mem (operands[1], VOIDmode)")

72612

+ (const_string "load_ext_u")

72613

+ (const_string "load_ext")))

72614

+ (const_string "exts")])])

72615

72616

(define_insn ""

72617

[(set (match_operand:SI 0 "gpc_reg_operand" "=r")

72618

@@ -1658,7 +1935,19 @@

72619

FAIL;

72620

})

72621

72622

-(define_insn "one_cmpl<mode>2"

72623

+(define_expand "one_cmpl<mode>2"

72624

+ [(set (match_operand:SDI 0 "gpc_reg_operand" "")

72625

+ (not:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]

72626

+ ""

72627

+{

72628

+ if (<MODE>mode == DImode && !TARGET_POWERPC64)

72629

+ {

72630

+ rs6000_split_logical (operands, NOT, false, false, false, NULL_RTX);

72631

+ DONE;

72632

+ }

72633

+})

72634

+

72635

+(define_insn "*one_cmpl<mode>2"

72636

[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")

72637

(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]

72638

""

72639

@@ -1935,7 +2224,9 @@

72640

[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")

72641

(unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] UNSPEC_PARITY))]

72642

"TARGET_CMPB && TARGET_POPCNTB"

72643

- "prty<wd> %0,%1")

72644

+ "prty<wd> %0,%1"

72645

+ [(set_attr "length" "4")

72646

+ (set_attr "type" "popcnt")])

72647

72648

(define_expand "parity<mode>2"

72649

[(set (match_operand:GPR 0 "gpc_reg_operand" "")

72650

@@ -2412,7 +2703,7 @@

72651

(match_operand:SI 2 "gpc_reg_operand" "r,r"))

72652

(const_int 0)))

72653

(clobber (match_scratch:SI 3 "=r,r"))]

72654

- ""

72655

+ "TARGET_32BIT"

72656

"@

72657

mullw. %3,%1,%2

72658

#"

72659

@@ -2425,7 +2716,7 @@

72660

(match_operand:SI 2 "gpc_reg_operand" ""))

72661

(const_int 0)))

72662

(clobber (match_scratch:SI 3 ""))]

72663

- "reload_completed"

72664

+ "TARGET_32BIT && reload_completed"

72665

[(set (match_dup 3)

72666

(mult:SI (match_dup 1) (match_dup 2)))

72667

(set (match_dup 0)

72668

@@ -2440,7 +2731,7 @@

72669

(const_int 0)))

72670

(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")

72671

(mult:SI (match_dup 1) (match_dup 2)))]

72672

- ""

72673

+ "TARGET_32BIT"

72674

"@

72675

mullw. %0,%1,%2

72676

#"

72677

@@ -2454,7 +2745,7 @@

72678

(const_int 0)))

72679

(set (match_operand:SI 0 "gpc_reg_operand" "")

72680

(mult:SI (match_dup 1) (match_dup 2)))]

72681

- "reload_completed"

72682

+ "TARGET_32BIT && reload_completed"

72683

[(set (match_dup 0)

72684

(mult:SI (match_dup 1) (match_dup 2)))

72685

(set (match_dup 3)

72686

@@ -2469,10 +2760,7 @@

72687

(match_operand:GPR 2 "gpc_reg_operand" "r")))]

72688

""

72689

"div<wd>u %0,%1,%2"

72690

- [(set (attr "type")

72691

- (cond [(match_operand:SI 0 "" "")

72692

- (const_string "idiv")]

72693

- (const_string "ldiv")))])

72694

+ [(set_attr "type" "<idiv_ldiv>")])

72695

72696

72697

;; For powers of two we can do srai/aze for divide and then adjust for

72698

@@ -2496,10 +2784,7 @@

72699

(match_operand:GPR 2 "gpc_reg_operand" "r")))]

72700

""

72701

"div<wd> %0,%1,%2"

72702

- [(set (attr "type")

72703

- (cond [(match_operand:SI 0 "" "")

72704

- (const_string "idiv")]

72705

- (const_string "ldiv")))])

72706

+ [(set_attr "type" "<idiv_ldiv>")])

72707

72708

(define_expand "mod<mode>3"

72709

[(use (match_operand:GPR 0 "gpc_reg_operand" ""))

72710

@@ -3698,13 +3983,13 @@

72711

(const_int 0)))]

72712

"")

72713

72714

-(define_insn "*rotlsi3_internal7"

72715

+(define_insn "*rotlsi3_internal7le"

72716

[(set (match_operand:SI 0 "gpc_reg_operand" "=r")

72717

(zero_extend:SI

72718

(subreg:QI

72719

(rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")

72720

(match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]

72721

- ""

72722

+ "!BYTES_BIG_ENDIAN"

72723

"rlw%I2nm %0,%1,%h2,0xff"

72724

[(set (attr "cell_micro")

72725

(if_then_else (match_operand:SI 2 "const_int_operand" "")

72726

@@ -3711,7 +3996,20 @@

72727

(const_string "not")

72728

(const_string "always")))])

72729

72730

-(define_insn "*rotlsi3_internal8"

72731

+(define_insn "*rotlsi3_internal7be"

72732

+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")

72733

+ (zero_extend:SI

72734

+ (subreg:QI

72735

+ (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")

72736

+ (match_operand:SI 2 "reg_or_cint_operand" "ri")) 3)))]

72737

+ "BYTES_BIG_ENDIAN"

72738

+ "rlw%I2nm %0,%1,%h2,0xff"

72739

+ [(set (attr "cell_micro")

72740

+ (if_then_else (match_operand:SI 2 "const_int_operand" "")

72741

+ (const_string "not")

72742

+ (const_string "always")))])

72743

+

72744

+(define_insn "*rotlsi3_internal8le"

72745

[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")

72746

(compare:CC (zero_extend:SI

72747

(subreg:QI

72748

@@ -3719,7 +4017,7 @@

72749

(match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))

72750

(const_int 0)))

72751

(clobber (match_scratch:SI 3 "=r,r,r,r"))]

72752

- ""

72753

+ "!BYTES_BIG_ENDIAN"

72754

"@

72755

rlwnm. %3,%1,%2,0xff

72756

rlwinm. %3,%1,%h2,0xff

72757

@@ -3728,6 +4026,23 @@

72758

[(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

72759

(set_attr "length" "4,4,8,8")])

72760

72761

+(define_insn "*rotlsi3_internal8be"

72762

+ [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")

72763

+ (compare:CC (zero_extend:SI

72764

+ (subreg:QI

72765

+ (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")

72766

+ (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 3))

72767

+ (const_int 0)))

72768

+ (clobber (match_scratch:SI 3 "=r,r,r,r"))]

72769

+ "BYTES_BIG_ENDIAN"

72770

+ "@

72771

+ rlwnm. %3,%1,%2,0xff

72772

+ rlwinm. %3,%1,%h2,0xff

72773

+ #

72774

+ #"

72775

+ [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

72776

+ (set_attr "length" "4,4,8,8")])

72777

+

72778

(define_split

72779

[(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")

72780

(compare:CC (zero_extend:SI

72781

@@ -3736,7 +4051,7 @@

72782

(match_operand:SI 2 "reg_or_cint_operand" "")) 0))

72783

(const_int 0)))

72784

(clobber (match_scratch:SI 3 ""))]

72785

- "reload_completed"

72786

+ "!BYTES_BIG_ENDIAN && reload_completed"

72787

[(set (match_dup 3)

72788

(zero_extend:SI (subreg:QI

72789

(rotate:SI (match_dup 1)

72790

@@ -3746,7 +4061,25 @@

72791

(const_int 0)))]

72792

"")

72793

72794

-(define_insn "*rotlsi3_internal9"

72795

+(define_split

72796

+ [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")

72797

+ (compare:CC (zero_extend:SI

72798

+ (subreg:QI

72799

+ (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")

72800

+ (match_operand:SI 2 "reg_or_cint_operand" "")) 3))

72801

+ (const_int 0)))

72802

+ (clobber (match_scratch:SI 3 ""))]

72803

+ "BYTES_BIG_ENDIAN && reload_completed"

72804

+ [(set (match_dup 3)

72805

+ (zero_extend:SI (subreg:QI

72806

+ (rotate:SI (match_dup 1)

72807

+ (match_dup 2)) 3)))

72808

+ (set (match_dup 0)

72809

+ (compare:CC (match_dup 3)

72810

+ (const_int 0)))]

72811

+ "")

72812

+

72813

+(define_insn "*rotlsi3_internal9le"

72814

[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")

72815

(compare:CC (zero_extend:SI

72816

(subreg:QI

72817

@@ -3755,7 +4088,7 @@

72818

(const_int 0)))

72819

(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")

72820

(zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]

72821

- ""

72822

+ "!BYTES_BIG_ENDIAN"

72823

"@

72824

rlwnm. %0,%1,%2,0xff

72825

rlwinm. %0,%1,%h2,0xff

72826

@@ -3764,6 +4097,24 @@

72827

[(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

72828

(set_attr "length" "4,4,8,8")])

72829

72830

+(define_insn "*rotlsi3_internal9be"

72831

+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")

72832

+ (compare:CC (zero_extend:SI

72833

+ (subreg:QI

72834

+ (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")

72835

+ (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 3))

72836

+ (const_int 0)))

72837

+ (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")

72838

+ (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))]

72839

+ "BYTES_BIG_ENDIAN"

72840

+ "@

72841

+ rlwnm. %0,%1,%2,0xff

72842

+ rlwinm. %0,%1,%h2,0xff

72843

+ #

72844

+ #"

72845

+ [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

72846

+ (set_attr "length" "4,4,8,8")])

72847

+

72848

(define_split

72849

[(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")

72850

(compare:CC (zero_extend:SI

72851

@@ -3773,7 +4124,7 @@

72852

(const_int 0)))

72853

(set (match_operand:SI 0 "gpc_reg_operand" "")

72854

(zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]

72855

- "reload_completed"

72856

+ "!BYTES_BIG_ENDIAN && reload_completed"

72857

[(set (match_dup 0)

72858

(zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))

72859

(set (match_dup 3)

72860

@@ -3781,20 +4132,48 @@

72861

(const_int 0)))]

72862

"")

72863

72864

-(define_insn "*rotlsi3_internal10"

72865

+(define_split

72866

+ [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")

72867

+ (compare:CC (zero_extend:SI

72868

+ (subreg:QI

72869

+ (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")

72870

+ (match_operand:SI 2 "reg_or_cint_operand" "")) 3))

72871

+ (const_int 0)))

72872

+ (set (match_operand:SI 0 "gpc_reg_operand" "")

72873

+ (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))]

72874

+ "BYTES_BIG_ENDIAN && reload_completed"

72875

+ [(set (match_dup 0)

72876

+ (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))

72877

+ (set (match_dup 3)

72878

+ (compare:CC (match_dup 0)

72879

+ (const_int 0)))]

72880

+ "")

72881

+

72882

+(define_insn "*rotlsi3_internal10le"

72883

[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")

72884

(zero_extend:SI

72885

(subreg:HI

72886

(rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")

72887

(match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]

72888

- ""

72889

+ "!BYTES_BIG_ENDIAN"

72890

"@

72891

rlwnm %0,%1,%2,0xffff

72892

rlwinm %0,%1,%h2,0xffff"

72893

[(set_attr "type" "var_shift_rotate,integer")])

72894

72895

+(define_insn "*rotlsi3_internal10be"

72896

+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")

72897

+ (zero_extend:SI

72898

+ (subreg:HI

72899

+ (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")

72900

+ (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 2)))]

72901

+ "BYTES_BIG_ENDIAN"

72902

+ "@

72903

+ rlwnm %0,%1,%2,0xffff

72904

+ rlwinm %0,%1,%h2,0xffff"

72905

+ [(set_attr "type" "var_shift_rotate,integer")])

72906

72907

-(define_insn "*rotlsi3_internal11"

72908

+(define_insn "*rotlsi3_internal11le"

72909

[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")

72910

(compare:CC (zero_extend:SI

72911

(subreg:HI

72912

@@ -3802,7 +4181,7 @@

72913

(match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))

72914

(const_int 0)))

72915

(clobber (match_scratch:SI 3 "=r,r,r,r"))]

72916

- ""

72917

+ "!BYTES_BIG_ENDIAN"

72918

"@

72919

rlwnm. %3,%1,%2,0xffff

72920

rlwinm. %3,%1,%h2,0xffff

72921

@@ -3811,6 +4190,23 @@

72922

[(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

72923

(set_attr "length" "4,4,8,8")])

72924

72925

+(define_insn "*rotlsi3_internal11be"

72926

+ [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")

72927

+ (compare:CC (zero_extend:SI

72928

+ (subreg:HI

72929

+ (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")

72930

+ (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 2))

72931

+ (const_int 0)))

72932

+ (clobber (match_scratch:SI 3 "=r,r,r,r"))]

72933

+ "BYTES_BIG_ENDIAN"

72934

+ "@

72935

+ rlwnm. %3,%1,%2,0xffff

72936

+ rlwinm. %3,%1,%h2,0xffff

72937

+ #

72938

+ #"

72939

+ [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

72940

+ (set_attr "length" "4,4,8,8")])

72941

+

72942

(define_split

72943

[(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")

72944

(compare:CC (zero_extend:SI

72945

@@ -3819,7 +4215,7 @@

72946

(match_operand:SI 2 "reg_or_cint_operand" "")) 0))

72947

(const_int 0)))

72948

(clobber (match_scratch:SI 3 ""))]

72949

- "reload_completed"

72950

+ "!BYTES_BIG_ENDIAN && reload_completed"

72951

[(set (match_dup 3)

72952

(zero_extend:SI (subreg:HI

72953

(rotate:SI (match_dup 1)

72954

@@ -3829,7 +4225,25 @@

72955

(const_int 0)))]

72956

"")

72957

72958

-(define_insn "*rotlsi3_internal12"

72959

+(define_split

72960

+ [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")

72961

+ (compare:CC (zero_extend:SI

72962

+ (subreg:HI

72963

+ (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")

72964

+ (match_operand:SI 2 "reg_or_cint_operand" "")) 2))

72965

+ (const_int 0)))

72966

+ (clobber (match_scratch:SI 3 ""))]

72967

+ "BYTES_BIG_ENDIAN && reload_completed"

72968

+ [(set (match_dup 3)

72969

+ (zero_extend:SI (subreg:HI

72970

+ (rotate:SI (match_dup 1)

72971

+ (match_dup 2)) 2)))

72972

+ (set (match_dup 0)

72973

+ (compare:CC (match_dup 3)

72974

+ (const_int 0)))]

72975

+ "")

72976

+

72977

+(define_insn "*rotlsi3_internal12le"

72978

[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")

72979

(compare:CC (zero_extend:SI

72980

(subreg:HI

72981

@@ -3838,7 +4252,7 @@

72982

(const_int 0)))

72983

(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")

72984

(zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]

72985

- ""

72986

+ "!BYTES_BIG_ENDIAN"

72987

"@

72988

rlwnm. %0,%1,%2,0xffff

72989

rlwinm. %0,%1,%h2,0xffff

72990

@@ -3847,6 +4261,24 @@

72991

[(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

72992

(set_attr "length" "4,4,8,8")])

72993

72994

+(define_insn "*rotlsi3_internal12be"

72995

+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")

72996

+ (compare:CC (zero_extend:SI

72997

+ (subreg:HI

72998

+ (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")

72999

+ (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 2))

73000

+ (const_int 0)))

73001

+ (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")

73002

+ (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))]

73003

+ "BYTES_BIG_ENDIAN"

73004

+ "@

73005

+ rlwnm. %0,%1,%2,0xffff

73006

+ rlwinm. %0,%1,%h2,0xffff

73007

+ #

73008

+ #"

73009

+ [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

73010

+ (set_attr "length" "4,4,8,8")])

73011

+

73012

(define_split

73013

[(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")

73014

(compare:CC (zero_extend:SI

73015

@@ -3856,7 +4288,7 @@

73016

(const_int 0)))

73017

(set (match_operand:SI 0 "gpc_reg_operand" "")

73018

(zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]

73019

- "reload_completed"

73020

+ "!BYTES_BIG_ENDIAN && reload_completed"

73021

[(set (match_dup 0)

73022

(zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))

73023

(set (match_dup 3)

73024

@@ -3864,6 +4296,23 @@

73025

(const_int 0)))]

73026

"")

73027

73028

+(define_split

73029

+ [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")

73030

+ (compare:CC (zero_extend:SI

73031

+ (subreg:HI

73032

+ (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")

73033

+ (match_operand:SI 2 "reg_or_cint_operand" "")) 2))

73034

+ (const_int 0)))

73035

+ (set (match_operand:SI 0 "gpc_reg_operand" "")

73036

+ (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))]

73037

+ "BYTES_BIG_ENDIAN && reload_completed"

73038

+ [(set (match_dup 0)

73039

+ (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))

73040

+ (set (match_dup 3)

73041

+ (compare:CC (match_dup 0)

73042

+ (const_int 0)))]

73043

+ "")

73044

+

73045

(define_insn "ashlsi3"

73046

[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")

73047

(ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")

73048

@@ -4054,7 +4503,7 @@

73049

#

73050

#

73051

#"

73052

- [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

73053

+ [(set_attr "type" "fast_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

73054

(set_attr "length" "4,4,4,8,8,8")])

73055

73056

(define_split

73057

@@ -4086,7 +4535,7 @@

73058

#

73059

#

73060

#"

73061

- [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

73062

+ [(set_attr "type" "fast_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

73063

(set_attr "length" "4,4,4,8,8,8")])

73064

73065

(define_split

73066

@@ -4177,16 +4626,25 @@

73067

(const_int 0)))]

73068

"")

73069

73070

-(define_insn ""

73071

+(define_insn "*lshiftrt_internal1le"

73072

[(set (match_operand:SI 0 "gpc_reg_operand" "=r")

73073

(zero_extend:SI

73074

(subreg:QI

73075

(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")

73076

(match_operand:SI 2 "const_int_operand" "i")) 0)))]

73077

- "includes_rshift_p (operands[2], GEN_INT (255))"

73078

+ "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"

73079

"rlwinm %0,%1,%s2,0xff")

73080

73081

-(define_insn ""

73082

+(define_insn "*lshiftrt_internal1be"

73083

+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")

73084

+ (zero_extend:SI

73085

+ (subreg:QI

73086

+ (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")

73087

+ (match_operand:SI 2 "const_int_operand" "i")) 3)))]

73088

+ "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"

73089

+ "rlwinm %0,%1,%s2,0xff")

73090

+

73091

+(define_insn "*lshiftrt_internal2le"

73092

[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")

73093

(compare:CC

73094

(zero_extend:SI

73095

@@ -4195,7 +4653,7 @@

73096

(match_operand:SI 2 "const_int_operand" "i,i")) 0))

73097

(const_int 0)))

73098

(clobber (match_scratch:SI 3 "=r,r"))]

73099

- "includes_rshift_p (operands[2], GEN_INT (255))"

73100

+ "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"

73101

"@

73102

rlwinm. %3,%1,%s2,0xff

73103

#"

73104

@@ -4202,6 +4660,22 @@

73105

[(set_attr "type" "delayed_compare")

73106

(set_attr "length" "4,8")])

73107

73108

+(define_insn "*lshiftrt_internal2be"

73109

+ [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")

73110

+ (compare:CC

73111

+ (zero_extend:SI

73112

+ (subreg:QI

73113

+ (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")

73114

+ (match_operand:SI 2 "const_int_operand" "i,i")) 3))

73115

+ (const_int 0)))

73116

+ (clobber (match_scratch:SI 3 "=r,r"))]

73117

+ "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"

73118

+ "@

73119

+ rlwinm. %3,%1,%s2,0xff

73120

+ #"

73121

+ [(set_attr "type" "delayed_compare")

73122

+ (set_attr "length" "4,8")])

73123

+

73124

(define_split

73125

[(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")

73126

(compare:CC

73127

@@ -4211,7 +4685,7 @@

73128

(match_operand:SI 2 "const_int_operand" "")) 0))

73129

(const_int 0)))

73130

(clobber (match_scratch:SI 3 ""))]

73131

- "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"

73132

+ "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"

73133

[(set (match_dup 3)

73134

(zero_extend:SI (subreg:QI

73135

(lshiftrt:SI (match_dup 1)

73136

@@ -4221,7 +4695,26 @@

73137

(const_int 0)))]

73138

"")

73139

73140

-(define_insn ""

73141

+(define_split

73142

+ [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")

73143

+ (compare:CC

73144

+ (zero_extend:SI

73145

+ (subreg:QI

73146

+ (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")

73147

+ (match_operand:SI 2 "const_int_operand" "")) 3))

73148

+ (const_int 0)))

73149

+ (clobber (match_scratch:SI 3 ""))]

73150

+ "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"

73151

+ [(set (match_dup 3)

73152

+ (zero_extend:SI (subreg:QI

73153

+ (lshiftrt:SI (match_dup 1)

73154

+ (match_dup 2)) 3)))

73155

+ (set (match_dup 0)

73156

+ (compare:CC (match_dup 3)

73157

+ (const_int 0)))]

73158

+ "")

73159

+

73160

+(define_insn "*lshiftrt_internal3le"

73161

[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")

73162

(compare:CC

73163

(zero_extend:SI

73164

@@ -4231,7 +4724,7 @@

73165

(const_int 0)))

73166

(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")

73167

(zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]

73168

- "includes_rshift_p (operands[2], GEN_INT (255))"

73169

+ "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"

73170

"@

73171

rlwinm. %0,%1,%s2,0xff

73172

#"

73173

@@ -4238,6 +4731,23 @@

73174

[(set_attr "type" "delayed_compare")

73175

(set_attr "length" "4,8")])

73176

73177

+(define_insn "*lshiftrt_internal3be"

73178

+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")

73179

+ (compare:CC

73180

+ (zero_extend:SI

73181

+ (subreg:QI

73182

+ (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")

73183

+ (match_operand:SI 2 "const_int_operand" "i,i")) 3))

73184

+ (const_int 0)))

73185

+ (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")

73186

+ (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))]

73187

+ "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"

73188

+ "@

73189

+ rlwinm. %0,%1,%s2,0xff

73190

+ #"

73191

+ [(set_attr "type" "delayed_compare")

73192

+ (set_attr "length" "4,8")])

73193

+

73194

(define_split

73195

[(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")

73196

(compare:CC

73197

@@ -4248,7 +4758,7 @@

73198

(const_int 0)))

73199

(set (match_operand:SI 0 "gpc_reg_operand" "")

73200

(zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]

73201

- "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"

73202

+ "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"

73203

[(set (match_dup 0)

73204

(zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))

73205

(set (match_dup 3)

73206

@@ -4256,16 +4766,43 @@

73207

(const_int 0)))]

73208

"")

73209

73210

-(define_insn ""

73211

+(define_split

73212

+ [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")

73213

+ (compare:CC

73214

+ (zero_extend:SI

73215

+ (subreg:QI

73216

+ (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")

73217

+ (match_operand:SI 2 "const_int_operand" "")) 3))

73218

+ (const_int 0)))

73219

+ (set (match_operand:SI 0 "gpc_reg_operand" "")

73220

+ (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))]

73221

+ "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"

73222

+ [(set (match_dup 0)

73223

+ (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))

73224

+ (set (match_dup 3)

73225

+ (compare:CC (match_dup 0)

73226

+ (const_int 0)))]

73227

+ "")

73228

+

73229

+(define_insn "*lshiftrt_internal4le"

73230

[(set (match_operand:SI 0 "gpc_reg_operand" "=r")

73231

(zero_extend:SI

73232

(subreg:HI

73233

(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")

73234

(match_operand:SI 2 "const_int_operand" "i")) 0)))]

73235

- "includes_rshift_p (operands[2], GEN_INT (65535))"

73236

+ "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"

73237

"rlwinm %0,%1,%s2,0xffff")

73238

73239

-(define_insn ""

73240

+(define_insn "*lshiftrt_internal4be"

73241

+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")

73242

+ (zero_extend:SI

73243

+ (subreg:HI

73244

+ (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")

73245

+ (match_operand:SI 2 "const_int_operand" "i")) 2)))]

73246

+ "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"

73247

+ "rlwinm %0,%1,%s2,0xffff")

73248

+

73249

+(define_insn "*lshiftrt_internal5le"

73250

[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")

73251

(compare:CC

73252

(zero_extend:SI

73253

@@ -4274,7 +4811,7 @@

73254

(match_operand:SI 2 "const_int_operand" "i,i")) 0))

73255

(const_int 0)))

73256

(clobber (match_scratch:SI 3 "=r,r"))]

73257

- "includes_rshift_p (operands[2], GEN_INT (65535))"

73258

+ "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"

73259

"@

73260

rlwinm. %3,%1,%s2,0xffff

73261

#"

73262

@@ -4281,6 +4818,22 @@

73263

[(set_attr "type" "delayed_compare")

73264

(set_attr "length" "4,8")])

73265

73266

+(define_insn "*lshiftrt_internal5be"

73267

+ [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")

73268

+ (compare:CC

73269

+ (zero_extend:SI

73270

+ (subreg:HI

73271

+ (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")

73272

+ (match_operand:SI 2 "const_int_operand" "i,i")) 2))

73273

+ (const_int 0)))

73274

+ (clobber (match_scratch:SI 3 "=r,r"))]

73275

+ "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"

73276

+ "@

73277

+ rlwinm. %3,%1,%s2,0xffff

73278

+ #"

73279

+ [(set_attr "type" "delayed_compare")

73280

+ (set_attr "length" "4,8")])

73281

+

73282

(define_split

73283

[(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")

73284

(compare:CC

73285

@@ -4290,7 +4843,7 @@

73286

(match_operand:SI 2 "const_int_operand" "")) 0))

73287

(const_int 0)))

73288

(clobber (match_scratch:SI 3 ""))]

73289

- "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"

73290

+ "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"

73291

[(set (match_dup 3)

73292

(zero_extend:SI (subreg:HI

73293

(lshiftrt:SI (match_dup 1)

73294

@@ -4300,7 +4853,26 @@

73295

(const_int 0)))]

73296

"")

73297

73298

-(define_insn ""

73299

+(define_split

73300

+ [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")

73301

+ (compare:CC

73302

+ (zero_extend:SI

73303

+ (subreg:HI

73304

+ (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")

73305

+ (match_operand:SI 2 "const_int_operand" "")) 2))

73306

+ (const_int 0)))

73307

+ (clobber (match_scratch:SI 3 ""))]

73308

+ "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"

73309

+ [(set (match_dup 3)

73310

+ (zero_extend:SI (subreg:HI

73311

+ (lshiftrt:SI (match_dup 1)

73312

+ (match_dup 2)) 2)))

73313

+ (set (match_dup 0)

73314

+ (compare:CC (match_dup 3)

73315

+ (const_int 0)))]

73316

+ "")

73317

+

73318

+(define_insn "*lshiftrt_internal5le"

73319

[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")

73320

(compare:CC

73321

(zero_extend:SI

73322

@@ -4310,7 +4882,7 @@

73323

(const_int 0)))

73324

(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")

73325

(zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]

73326

- "includes_rshift_p (operands[2], GEN_INT (65535))"

73327

+ "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"

73328

"@

73329

rlwinm. %0,%1,%s2,0xffff

73330

#"

73331

@@ -4317,6 +4889,23 @@

73332

[(set_attr "type" "delayed_compare")

73333

(set_attr "length" "4,8")])

73334

73335

+(define_insn "*lshiftrt_internal5be"

73336

+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")

73337

+ (compare:CC

73338

+ (zero_extend:SI

73339

+ (subreg:HI

73340

+ (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")

73341

+ (match_operand:SI 2 "const_int_operand" "i,i")) 2))

73342

+ (const_int 0)))

73343

+ (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")

73344

+ (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))]

73345

+ "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"

73346

+ "@

73347

+ rlwinm. %0,%1,%s2,0xffff

73348

+ #"

73349

+ [(set_attr "type" "delayed_compare")

73350

+ (set_attr "length" "4,8")])

73351

+

73352

(define_split

73353

[(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")

73354

(compare:CC

73355

@@ -4327,7 +4916,7 @@

73356

(const_int 0)))

73357

(set (match_operand:SI 0 "gpc_reg_operand" "")

73358

(zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]

73359

- "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"

73360

+ "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"

73361

[(set (match_dup 0)

73362

(zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))

73363

(set (match_dup 3)

73364

@@ -4335,6 +4924,24 @@

73365

(const_int 0)))]

73366

"")

73367

73368

+(define_split

73369

+ [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")

73370

+ (compare:CC

73371

+ (zero_extend:SI

73372

+ (subreg:HI

73373

+ (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")

73374

+ (match_operand:SI 2 "const_int_operand" "")) 2))

73375

+ (const_int 0)))

73376

+ (set (match_operand:SI 0 "gpc_reg_operand" "")

73377

+ (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))]

73378

+ "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"

73379

+ [(set (match_dup 0)

73380

+ (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))

73381

+ (set (match_dup 3)

73382

+ (compare:CC (match_dup 0)

73383

+ (const_int 0)))]

73384

+ "")

73385

+

73386

(define_insn "ashrsi3"

73387

[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")

73388

(ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")

73389

@@ -4455,224 +5062,226 @@

73390

(const_int 0)))]

73391

"")

73392

73393

-;; Floating-point insns, excluding normal data motion.

73394

-;;

73395

-;; PowerPC has a full set of single-precision floating point instructions.

73396

-;;

73397

-;; For the POWER architecture, we pretend that we have both SFmode and

73398

-;; DFmode insns, while, in fact, all fp insns are actually done in double.

73399

-;; The only conversions we will do will be when storing to memory. In that

73400

-;; case, we will use the "frsp" instruction before storing.

73401

-;;

73402

-;; Note that when we store into a single-precision memory location, we need to

73403

-;; use the frsp insn first. If the register being stored isn't dead, we

73404

-;; need a scratch register for the frsp. But this is difficult when the store

73405

-;; is done by reload. It is not incorrect to do the frsp on the register in

73406

-;; this case, we just lose precision that we would have otherwise gotten but

73407

-;; is not guaranteed. Perhaps this should be tightened up at some point.

73408

+

73409

+;; Floating-point insns, excluding normal data motion. We combine the SF/DF

73410

+;; modes here, and also add in conditional vsx/power8-vector support to access

73411

+;; values in the traditional Altivec registers if the appropriate

73412

+;; -mupper-regs-{df,sf} option is enabled.

73413

73414

-(define_expand "extendsfdf2"

73415

- [(set (match_operand:DF 0 "gpc_reg_operand" "")

73416

- (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]

73417

- "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"

73418

+(define_expand "abs<mode>2"

73419

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "")

73420

+ (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))]

73421

+ "TARGET_<MODE>_INSN"

73422

"")

73423

73424

-(define_insn_and_split "*extendsfdf2_fpr"

73425

- [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d")

73426

- (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]

73427

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"

73428

+(define_insn "*abs<mode>2_fpr"

73429

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")

73430

+ (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]

73431

+ "TARGET_<MODE>_FPR"

73432

"@

73433

- #

73434

- fmr %0,%1

73435

- lfs%U1%X1 %0,%1"

73436

- "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"

73437

- [(const_int 0)]

73438

-{

73439

- emit_note (NOTE_INSN_DELETED);

73440

- DONE;

73441

-}

73442

- [(set_attr "type" "fp,fp,fpload")])

73443

+ fabs %0,%1

73444

+ xsabsdp %x0,%x1"

73445

+ [(set_attr "type" "fp")

73446

+ (set_attr "fp_type" "fp_addsub_<Fs>")])

73447

73448

-(define_expand "truncdfsf2"

73449

- [(set (match_operand:SF 0 "gpc_reg_operand" "")

73450

- (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]

73451

- "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"

73452

- "")

73453

+(define_insn "*nabs<mode>2_fpr"

73454

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")

73455

+ (neg:SFDF

73456

+ (abs:SFDF

73457

+ (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))))]

73458

+ "TARGET_<MODE>_FPR"

73459

+ "@

73460

+ fnabs %0,%1

73461

+ xsnabsdp %x0,%x1"

73462

+ [(set_attr "type" "fp")

73463

+ (set_attr "fp_type" "fp_addsub_<Fs>")])

73464

73465

-(define_insn "*truncdfsf2_fpr"

73466

- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")

73467

- (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]

73468

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"

73469

- "frsp %0,%1"

73470

- [(set_attr "type" "fp")])

73471

-

73472

-(define_expand "negsf2"

73473

- [(set (match_operand:SF 0 "gpc_reg_operand" "")

73474

- (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]

73475

- "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"

73476

+(define_expand "neg<mode>2"

73477

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "")

73478

+ (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))]

73479

+ "TARGET_<MODE>_INSN"

73480

"")

73481

73482

-(define_insn "*negsf2"

73483

- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")

73484

- (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]

73485

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"

73486

- "fneg %0,%1"

73487

- [(set_attr "type" "fp")])

73488

+(define_insn "*neg<mode>2_fpr"

73489

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")

73490

+ (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]

73491

+ "TARGET_<MODE>_FPR"

73492

+ "@

73493

+ fneg %0,%1

73494

+ xsnegdp %x0,%x1"

73495

+ [(set_attr "type" "fp")

73496

+ (set_attr "fp_type" "fp_addsub_<Fs>")])

73497

73498

-(define_expand "abssf2"

73499

- [(set (match_operand:SF 0 "gpc_reg_operand" "")

73500

- (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]

73501

- "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"

73502

+(define_expand "add<mode>3"

73503

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "")

73504

+ (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")

73505

+ (match_operand:SFDF 2 "gpc_reg_operand" "")))]

73506

+ "TARGET_<MODE>_INSN"

73507

"")

73508

73509

-(define_insn "*abssf2"

73510

- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")

73511

- (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]

73512

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"

73513

- "fabs %0,%1"

73514

- [(set_attr "type" "fp")])

73515

+(define_insn "*add<mode>3_fpr"

73516

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")

73517

+ (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")

73518

+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]

73519

+ "TARGET_<MODE>_FPR"

73520

+ "@

73521

+ fadd<Ftrad> %0,%1,%2

73522

+ xsadd<Fvsx> %x0,%x1,%x2"

73523

+ [(set_attr "type" "fp")

73524

+ (set_attr "fp_type" "fp_addsub_<Fs>")])

73525

73526

-(define_insn ""

73527

- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")

73528

- (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]

73529

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"

73530

- "fnabs %0,%1"

73531

- [(set_attr "type" "fp")])

73532

-

73533

-(define_expand "addsf3"

73534

- [(set (match_operand:SF 0 "gpc_reg_operand" "")

73535

- (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")

73536

- (match_operand:SF 2 "gpc_reg_operand" "")))]

73537

- "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"

73538

+(define_expand "sub<mode>3"

73539

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "")

73540

+ (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")

73541

+ (match_operand:SFDF 2 "gpc_reg_operand" "")))]

73542

+ "TARGET_<MODE>_INSN"

73543

"")

73544

73545

-(define_insn ""

73546

- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")

73547

- (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")

73548

- (match_operand:SF 2 "gpc_reg_operand" "f")))]

73549

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"

73550

- "fadds %0,%1,%2"

73551

+(define_insn "*sub<mode>3_fpr"

73552

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")

73553

+ (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")

73554

+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]

73555

+ "TARGET_<MODE>_FPR"

73556

+ "@

73557

+ fsub<Ftrad> %0,%1,%2

73558

+ xssub<Fvsx> %x0,%x1,%x2"

73559

[(set_attr "type" "fp")

73560

- (set_attr "fp_type" "fp_addsub_s")])

73561

+ (set_attr "fp_type" "fp_addsub_<Fs>")])

73562

73563

-(define_expand "subsf3"

73564

- [(set (match_operand:SF 0 "gpc_reg_operand" "")

73565

- (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")

73566

- (match_operand:SF 2 "gpc_reg_operand" "")))]

73567

- "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"

73568

+(define_expand "mul<mode>3"

73569

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "")

73570

+ (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")

73571

+ (match_operand:SFDF 2 "gpc_reg_operand" "")))]

73572

+ "TARGET_<MODE>_INSN"

73573

"")

73574

73575

-(define_insn ""

73576

- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")

73577

- (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")

73578

- (match_operand:SF 2 "gpc_reg_operand" "f")))]

73579

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"

73580

- "fsubs %0,%1,%2"

73581

- [(set_attr "type" "fp")

73582

- (set_attr "fp_type" "fp_addsub_s")])

73583

+(define_insn "*mul<mode>3_fpr"

73584

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")

73585

+ (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")

73586

+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]

73587

+ "TARGET_<MODE>_FPR"

73588

+ "@

73589

+ fmul<Ftrad> %0,%1,%2

73590

+ xsmul<Fvsx> %x0,%x1,%x2"

73591

+ [(set_attr "type" "dmul")

73592

+ (set_attr "fp_type" "fp_mul_<Fs>")])

73593

73594

-(define_expand "mulsf3"

73595

- [(set (match_operand:SF 0 "gpc_reg_operand" "")

73596

- (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")

73597

- (match_operand:SF 2 "gpc_reg_operand" "")))]

73598

- "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"

73599

+(define_expand "div<mode>3"

73600

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "")

73601

+ (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")

73602

+ (match_operand:SFDF 2 "gpc_reg_operand" "")))]

73603

+ "TARGET_<MODE>_INSN && !TARGET_SIMPLE_FPU"

73604

"")

73605

73606

-(define_insn ""

73607

- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")

73608

- (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")

73609

- (match_operand:SF 2 "gpc_reg_operand" "f")))]

73610

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"

73611

- "fmuls %0,%1,%2"

73612

- [(set_attr "type" "fp")

73613

- (set_attr "fp_type" "fp_mul_s")])

73614

+(define_insn "*div<mode>3_fpr"

73615

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")

73616

+ (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")

73617

+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]

73618

+ "TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU"

73619

+ "@

73620

+ fdiv<Ftrad> %0,%1,%2

73621

+ xsdiv<Fvsx> %x0,%x1,%x2"

73622

+ [(set_attr "type" "<Fs>div")

73623

+ (set_attr "fp_type" "fp_div_<Fs>")])

73624

73625

-(define_expand "divsf3"

73626

- [(set (match_operand:SF 0 "gpc_reg_operand" "")

73627

- (div:SF (match_operand:SF 1 "gpc_reg_operand" "")

73628

- (match_operand:SF 2 "gpc_reg_operand" "")))]

73629

- "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"

73630

- "")

73631

+(define_insn "sqrt<mode>2"

73632

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")

73633

+ (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]

73634

+ "TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU

73635

+ && (TARGET_PPC_GPOPT || (<MODE>mode == SFmode && TARGET_XILINX_FPU))"

73636

+ "@

73637

+ fsqrt<Ftrad> %0,%1

73638

+ xssqrt<Fvsx> %x0,%x1"

73639

+ [(set_attr "type" "<Fs>sqrt")

73640

+ (set_attr "fp_type" "fp_sqrt_<Fs>")])

73641

73642

-(define_insn ""

73643

- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")

73644

- (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")

73645

- (match_operand:SF 2 "gpc_reg_operand" "f")))]

73646

- "TARGET_HARD_FLOAT && TARGET_FPRS

73647

- && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"

73648

- "fdivs %0,%1,%2"

73649

- [(set_attr "type" "sdiv")])

73650

+;; Floating point reciprocal approximation

73651

+(define_insn "fre<Fs>"

73652

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")

73653

+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]

73654

+ UNSPEC_FRES))]

73655

+ "TARGET_<FFRE>"

73656

+ "@

73657

+ fre<Ftrad> %0,%1

73658

+ xsre<Fvsx> %x0,%x1"

73659

+ [(set_attr "type" "fp")])

73660

73661

-(define_insn "fres"

73662

- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")

73663

- (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]

73664

- "TARGET_FRES"

73665

- "fres %0,%1"

73666

+(define_insn "*rsqrt<mode>2"

73667

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")

73668

+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]

73669

+ UNSPEC_RSQRT))]

73670

+ "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"

73671

+ "@

73672

+ frsqrte<Ftrad> %0,%1

73673

+ xsrsqrte<Fvsx> %x0,%x1"

73674

[(set_attr "type" "fp")])

73675

73676

-; builtin fmaf support

73677

-(define_insn "*fmasf4_fpr"

73678

- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")

73679

- (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")

73680

- (match_operand:SF 2 "gpc_reg_operand" "f")

73681

- (match_operand:SF 3 "gpc_reg_operand" "f")))]

73682

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"

73683

- "fmadds %0,%1,%2,%3"

73684

- [(set_attr "type" "fp")

73685

- (set_attr "fp_type" "fp_maddsub_s")])

73686

+;; Floating point comparisons

73687

+(define_insn "*cmp<mode>_fpr"

73688

+ [(set (match_operand:CCFP 0 "cc_reg_operand" "=y,y")

73689

+ (compare:CCFP (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")

73690

+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]

73691

+ "TARGET_<MODE>_FPR"

73692

+ "@

73693

+ fcmpu %0,%1,%2

73694

+ xscmpudp %0,%x1,%x2"

73695

+ [(set_attr "type" "fpcompare")])

73696

73697

-(define_insn "*fmssf4_fpr"

73698

- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")

73699

- (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")

73700

- (match_operand:SF 2 "gpc_reg_operand" "f")

73701

- (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f"))))]

73702

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"

73703

- "fmsubs %0,%1,%2,%3"

73704

- [(set_attr "type" "fp")

73705

- (set_attr "fp_type" "fp_maddsub_s")])

73706

+;; Floating point conversions

73707

+(define_expand "extendsfdf2"

73708

+ [(set (match_operand:DF 0 "gpc_reg_operand" "")

73709

+ (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]

73710

+ "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"

73711

+ "")

73712

73713

-(define_insn "*nfmasf4_fpr"

73714

- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")

73715

- (neg:SF (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")

73716

- (match_operand:SF 2 "gpc_reg_operand" "f")

73717

- (match_operand:SF 3 "gpc_reg_operand" "f"))))]

73718

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"

73719

- "fnmadds %0,%1,%2,%3"

73720

- [(set_attr "type" "fp")

73721

- (set_attr "fp_type" "fp_maddsub_s")])

73722

+(define_insn_and_split "*extendsfdf2_fpr"

73723

+ [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d,ws,?ws,wv")

73724

+ (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m,0,wy,Z")))]

73725

+ "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"

73726

+ "@

73727

+ #

73728

+ fmr %0,%1

73729

+ lfs%U1%X1 %0,%1

73730

+ #

73731

+ xxlor %x0,%x1,%x1

73732

+ lxsspx %x0,%y1"

73733

+ "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"

73734

+ [(const_int 0)]

73735

+{

73736

+ emit_note (NOTE_INSN_DELETED);

73737

+ DONE;

73738

+}

73739

+ [(set_attr_alternative "type"

73740

+ [(const_string "fp")

73741

+ (const_string "fp")

73742

+ (if_then_else

73743

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

73744

+ (const_string "fpload_ux")

73745

+ (if_then_else

73746

+ (match_test "update_address_mem (operands[1], VOIDmode)")

73747

+ (const_string "fpload_u")

73748

+ (const_string "fpload")))

73749

+ (const_string "fp")

73750

+ (const_string "vecsimple")

73751

+ (if_then_else

73752

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

73753

+ (const_string "fpload_ux")

73754

+ (if_then_else

73755

+ (match_test "update_address_mem (operands[1], VOIDmode)")

73756

+ (const_string "fpload_u")

73757

+ (const_string "fpload")))])])

73758

73759

-(define_insn "*nfmssf4_fpr"

73760

- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")

73761

- (neg:SF (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")

73762

- (match_operand:SF 2 "gpc_reg_operand" "f")

73763

- (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f")))))]

73764

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"

73765

- "fnmsubs %0,%1,%2,%3"

73766

- [(set_attr "type" "fp")

73767

- (set_attr "fp_type" "fp_maddsub_s")])

73768

-

73769

-(define_expand "sqrtsf2"

73770

+(define_expand "truncdfsf2"

73771

[(set (match_operand:SF 0 "gpc_reg_operand" "")

73772

- (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]

73773

- "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU)

73774

- && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT

73775

- && !TARGET_SIMPLE_FPU"

73776

+ (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]

73777

+ "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"

73778

"")

73779

73780

-(define_insn ""

73781

+(define_insn "*truncdfsf2_fpr"

73782

[(set (match_operand:SF 0 "gpc_reg_operand" "=f")

73783

- (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]

73784

- "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT

73785

- && TARGET_FPRS && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"

73786

- "fsqrts %0,%1"

73787

- [(set_attr "type" "ssqrt")])

73788

-

73789

-(define_insn "*rsqrtsf_internal1"

73790

- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")

73791

- (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]

73792

- UNSPEC_RSQRT))]

73793

- "TARGET_FRSQRTES"

73794

- "frsqrtes %0,%1"

73795

+ (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]

73796

+ "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"

73797

+ "frsp %0,%1"

73798

[(set_attr "type" "fp")])

73799

73800

;; This expander is here to avoid FLOAT_WORDS_BIGENDIAN tests in

73801

@@ -4742,12 +5351,14 @@

73802

;; Use an unspec rather providing an if-then-else in RTL, to prevent the

73803

;; compiler from optimizing -0.0

73804

(define_insn "copysign<mode>3_fcpsgn"

73805

- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")

73806

- (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")

73807

- (match_operand:SFDF 2 "gpc_reg_operand" "<rreg2>")]

73808

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")

73809

+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")

73810

+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")]

73811

UNSPEC_COPYSIGN))]

73812

- "TARGET_CMPB && !VECTOR_UNIT_VSX_P (<MODE>mode)"

73813

- "fcpsgn %0,%2,%1"

73814

+ "TARGET_<MODE>_FPR && TARGET_CMPB"

73815

+ "@

73816

+ fcpsgn %0,%2,%1

73817

+ xscpsgn<Fvsx> %x0,%x2,%x1"

73818

[(set_attr "type" "fp")])

73819

73820

;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a

73821

@@ -4754,27 +5365,70 @@

73822

;; fsel instruction and some auxiliary computations. Then we just have a

73823

;; single DEFINE_INSN for fsel and the define_splits to make them if made by

73824

;; combine.

73825

-(define_expand "smaxsf3"

73826

- [(set (match_operand:SF 0 "gpc_reg_operand" "")

73827

- (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")

73828

- (match_operand:SF 2 "gpc_reg_operand" ""))

73829

- (match_dup 1)

73830

- (match_dup 2)))]

73831

- "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS

73832

- && TARGET_SINGLE_FLOAT && !flag_trapping_math"

73833

- "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")

73834

+;; For MIN, MAX on non-VSX machines, and conditional move all of the time, we

73835

+;; use DEFINE_EXPAND's that involve a fsel instruction and some auxiliary

73836

+;; computations. Then we just have a single DEFINE_INSN for fsel and the

73837

+;; define_splits to make them if made by combine. On VSX machines we have the

73838

+;; min/max instructions.

73839

+;;

73840

+;; On VSX, we only check for TARGET_VSX instead of checking for a vsx/p8 vector

73841

+;; to allow either DF/SF to use only traditional registers.

73842

73843

-(define_expand "sminsf3"

73844

- [(set (match_operand:SF 0 "gpc_reg_operand" "")

73845

- (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")

73846

- (match_operand:SF 2 "gpc_reg_operand" ""))

73847

- (match_dup 2)

73848

- (match_dup 1)))]

73849

- "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS

73850

- && TARGET_SINGLE_FLOAT && !flag_trapping_math"

73851

- "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")

73852

+(define_expand "smax<mode>3"

73853

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "")

73854

+ (if_then_else:SFDF (ge (match_operand:SFDF 1 "gpc_reg_operand" "")

73855

+ (match_operand:SFDF 2 "gpc_reg_operand" ""))

73856

+ (match_dup 1)

73857

+ (match_dup 2)))]

73858

+ "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math"

73859

+{

73860

+ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);

73861

+ DONE;

73862

+})

73863

73864

+(define_insn "*smax<mode>3_vsx"

73865

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")

73866

+ (smax:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")

73867

+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]

73868

+ "TARGET_<MODE>_FPR && TARGET_VSX"

73869

+ "xsmaxdp %x0,%x1,%x2"

73870

+ [(set_attr "type" "fp")])

73871

+

73872

+(define_expand "smin<mode>3"

73873

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "")

73874

+ (if_then_else:SFDF (ge (match_operand:SFDF 1 "gpc_reg_operand" "")

73875

+ (match_operand:SFDF 2 "gpc_reg_operand" ""))

73876

+ (match_dup 2)

73877

+ (match_dup 1)))]

73878

+ "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math"

73879

+{

73880

+ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);

73881

+ DONE;

73882

+})

73883

+

73884

+(define_insn "*smin<mode>3_vsx"

73885

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")

73886

+ (smin:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")

73887

+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]

73888

+ "TARGET_<MODE>_FPR && TARGET_VSX"

73889

+ "xsmindp %x0,%x1,%x2"

73890

+ [(set_attr "type" "fp")])

73891

+

73892

(define_split

73893

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "")

73894

+ (match_operator:SFDF 3 "min_max_operator"

73895

+ [(match_operand:SFDF 1 "gpc_reg_operand" "")

73896

+ (match_operand:SFDF 2 "gpc_reg_operand" "")]))]

73897

+ "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math

73898

+ && !TARGET_VSX"

73899

+ [(const_int 0)]

73900

+{

73901

+ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), operands[1],

73902

+ operands[2]);

73903

+ DONE;

73904

+})

73905

+

73906

+(define_split

73907

[(set (match_operand:SF 0 "gpc_reg_operand" "")

73908

(match_operator:SF 3 "min_max_operator"

73909

[(match_operand:SF 1 "gpc_reg_operand" "")

73910

@@ -4904,208 +5558,9 @@

73911

"fsel %0,%1,%2,%3"

73912

[(set_attr "type" "fp")])

73913

73914

-(define_expand "negdf2"

73915

- [(set (match_operand:DF 0 "gpc_reg_operand" "")

73916

- (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]

73917

- "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"

73918

- "")

73919

-

73920

-(define_insn "*negdf2_fpr"

73921

- [(set (match_operand:DF 0 "gpc_reg_operand" "=d")

73922

- (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]

73923

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT

73924

- && !VECTOR_UNIT_VSX_P (DFmode)"

73925

- "fneg %0,%1"

73926

- [(set_attr "type" "fp")])

73927

-

73928

-(define_expand "absdf2"

73929

- [(set (match_operand:DF 0 "gpc_reg_operand" "")

73930

- (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]

73931

- "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"

73932

- "")

73933

-

73934

-(define_insn "*absdf2_fpr"

73935

- [(set (match_operand:DF 0 "gpc_reg_operand" "=d")

73936

- (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]

73937

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT

73938

- && !VECTOR_UNIT_VSX_P (DFmode)"

73939

- "fabs %0,%1"

73940

- [(set_attr "type" "fp")])

73941

-

73942

-(define_insn "*nabsdf2_fpr"

73943

- [(set (match_operand:DF 0 "gpc_reg_operand" "=d")

73944

- (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d"))))]

73945

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT

73946

- && !VECTOR_UNIT_VSX_P (DFmode)"

73947

- "fnabs %0,%1"

73948

- [(set_attr "type" "fp")])

73949

-

73950

-(define_expand "adddf3"

73951

- [(set (match_operand:DF 0 "gpc_reg_operand" "")

73952

- (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")

73953

- (match_operand:DF 2 "gpc_reg_operand" "")))]

73954

- "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"

73955

- "")

73956

-

73957

-(define_insn "*adddf3_fpr"

73958

- [(set (match_operand:DF 0 "gpc_reg_operand" "=d")

73959

- (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%d")

73960

- (match_operand:DF 2 "gpc_reg_operand" "d")))]

73961

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT

73962

- && !VECTOR_UNIT_VSX_P (DFmode)"

73963

- "fadd %0,%1,%2"

73964

- [(set_attr "type" "fp")

73965

- (set_attr "fp_type" "fp_addsub_d")])

73966

-

73967

-(define_expand "subdf3"

73968

- [(set (match_operand:DF 0 "gpc_reg_operand" "")

73969

- (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")

73970

- (match_operand:DF 2 "gpc_reg_operand" "")))]

73971

- "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"

73972

- "")

73973

-

73974

-(define_insn "*subdf3_fpr"

73975

- [(set (match_operand:DF 0 "gpc_reg_operand" "=d")

73976

- (minus:DF (match_operand:DF 1 "gpc_reg_operand" "d")

73977

- (match_operand:DF 2 "gpc_reg_operand" "d")))]

73978

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT

73979

- && !VECTOR_UNIT_VSX_P (DFmode)"

73980

- "fsub %0,%1,%2"

73981

- [(set_attr "type" "fp")

73982

- (set_attr "fp_type" "fp_addsub_d")])

73983

-

73984

-(define_expand "muldf3"

73985

- [(set (match_operand:DF 0 "gpc_reg_operand" "")

73986

- (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")

73987

- (match_operand:DF 2 "gpc_reg_operand" "")))]

73988

- "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"

73989

- "")

73990

-

73991

-(define_insn "*muldf3_fpr"

73992

- [(set (match_operand:DF 0 "gpc_reg_operand" "=d")

73993

- (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")

73994

- (match_operand:DF 2 "gpc_reg_operand" "d")))]

73995

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT

73996

- && !VECTOR_UNIT_VSX_P (DFmode)"

73997

- "fmul %0,%1,%2"

73998

- [(set_attr "type" "dmul")

73999

- (set_attr "fp_type" "fp_mul_d")])

74000

-

74001

-(define_expand "divdf3"

74002

- [(set (match_operand:DF 0 "gpc_reg_operand" "")

74003

- (div:DF (match_operand:DF 1 "gpc_reg_operand" "")

74004

- (match_operand:DF 2 "gpc_reg_operand" "")))]

74005

- "TARGET_HARD_FLOAT

74006

- && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)

74007

- && !TARGET_SIMPLE_FPU"

74008

- "")

74009

-

74010

-(define_insn "*divdf3_fpr"

74011

- [(set (match_operand:DF 0 "gpc_reg_operand" "=d")

74012

- (div:DF (match_operand:DF 1 "gpc_reg_operand" "d")

74013

- (match_operand:DF 2 "gpc_reg_operand" "d")))]

74014

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !TARGET_SIMPLE_FPU

74015

- && !VECTOR_UNIT_VSX_P (DFmode)"

74016

- "fdiv %0,%1,%2"

74017

- [(set_attr "type" "ddiv")])

74018

-

74019

-(define_insn "*fred_fpr"

74020

- [(set (match_operand:DF 0 "gpc_reg_operand" "=f")

74021

- (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]

74022

- "TARGET_FRE && !VECTOR_UNIT_VSX_P (DFmode)"

74023

- "fre %0,%1"

74024

- [(set_attr "type" "fp")])

74025

-

74026

-(define_insn "*rsqrtdf_internal1"

74027

- [(set (match_operand:DF 0 "gpc_reg_operand" "=d")

74028

- (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")]

74029

- UNSPEC_RSQRT))]

74030

- "TARGET_FRSQRTE && !VECTOR_UNIT_VSX_P (DFmode)"

74031

- "frsqrte %0,%1"

74032

- [(set_attr "type" "fp")])

74033

-

74034

-; builtin fma support

74035

-(define_insn "*fmadf4_fpr"

74036

- [(set (match_operand:DF 0 "gpc_reg_operand" "=f")

74037

- (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")

74038

- (match_operand:DF 2 "gpc_reg_operand" "f")

74039

- (match_operand:DF 3 "gpc_reg_operand" "f")))]

74040

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT

74041

- && VECTOR_UNIT_NONE_P (DFmode)"

74042

- "fmadd %0,%1,%2,%3"

74043

- [(set_attr "type" "fp")

74044

- (set_attr "fp_type" "fp_maddsub_d")])

74045

-

74046

-(define_insn "*fmsdf4_fpr"

74047

- [(set (match_operand:DF 0 "gpc_reg_operand" "=f")

74048

- (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")

74049

- (match_operand:DF 2 "gpc_reg_operand" "f")

74050

- (neg:DF (match_operand:DF 3 "gpc_reg_operand" "f"))))]

74051

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT

74052

- && VECTOR_UNIT_NONE_P (DFmode)"

74053

- "fmsub %0,%1,%2,%3"

74054

- [(set_attr "type" "fp")

74055

- (set_attr "fp_type" "fp_maddsub_d")])

74056

-

74057

-(define_insn "*nfmadf4_fpr"

74058

- [(set (match_operand:DF 0 "gpc_reg_operand" "=f")

74059

- (neg:DF (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")

74060

- (match_operand:DF 2 "gpc_reg_operand" "f")

74061

- (match_operand:DF 3 "gpc_reg_operand" "f"))))]

74062

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT

74063

- && VECTOR_UNIT_NONE_P (DFmode)"

74064

- "fnmadd %0,%1,%2,%3"

74065

- [(set_attr "type" "fp")

74066

- (set_attr "fp_type" "fp_maddsub_d")])

74067

-

74068

-(define_insn "*nfmsdf4_fpr"

74069

- [(set (match_operand:DF 0 "gpc_reg_operand" "=f")

74070

- (neg:DF (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")

74071

- (match_operand:DF 2 "gpc_reg_operand" "f")

74072

- (neg:DF (match_operand:DF 3 "gpc_reg_operand" "f")))))]

74073

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT

74074

- && VECTOR_UNIT_NONE_P (DFmode)"

74075

- "fnmsub %0,%1,%2,%3"

74076

- [(set_attr "type" "fp")

74077

- (set_attr "fp_type" "fp_maddsub_d")])

74078

-

74079

-(define_expand "sqrtdf2"

74080

- [(set (match_operand:DF 0 "gpc_reg_operand" "")

74081

- (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "")))]

74082

- "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"

74083

- "")

74084

-

74085

-(define_insn "*sqrtdf2_fpr"

74086

- [(set (match_operand:DF 0 "gpc_reg_operand" "=d")

74087

- (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]

74088

- "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT

74089

- && !VECTOR_UNIT_VSX_P (DFmode)"

74090

- "fsqrt %0,%1"

74091

- [(set_attr "type" "dsqrt")])

74092

-

74093

;; The conditional move instructions allow us to perform max and min

74094

;; operations even when

74095

74096

-(define_expand "smaxdf3"

74097

- [(set (match_operand:DF 0 "gpc_reg_operand" "")

74098

- (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")

74099

- (match_operand:DF 2 "gpc_reg_operand" ""))

74100

- (match_dup 1)

74101

- (match_dup 2)))]

74102

- "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT

74103

- && !flag_trapping_math"

74104

- "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")

74105

-

74106

-(define_expand "smindf3"

74107

- [(set (match_operand:DF 0 "gpc_reg_operand" "")

74108

- (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")

74109

- (match_operand:DF 2 "gpc_reg_operand" ""))

74110

- (match_dup 2)

74111

- (match_dup 1)))]

74112

- "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT

74113

- && !flag_trapping_math"

74114

- "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")

74115

-

74116

(define_split

74117

[(set (match_operand:DF 0 "gpc_reg_operand" "")

74118

(match_operator:DF 3 "min_max_operator"

74119

@@ -5159,12 +5614,15 @@

74120

; We don't define lfiwax/lfiwzx with the normal definition, because we

74121

; don't want to support putting SImode in FPR registers.

74122

(define_insn "lfiwax"

74123

- [(set (match_operand:DI 0 "gpc_reg_operand" "=d")

74124

- (unspec:DI [(match_operand:SI 1 "indexed_or_indirect_operand" "Z")]

74125

+ [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wm,!wm")

74126

+ (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]

74127

UNSPEC_LFIWAX))]

74128

"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX"

74129

- "lfiwax %0,%y1"

74130

- [(set_attr "type" "fpload")])

74131

+ "@

74132

+ lfiwax %0,%y1

74133

+ lxsiwax %x0,%y1

74134

+ mtvsrwa %x0,%1"

74135

+ [(set_attr "type" "fpload,fpload,mffgpr")])

74136

74137

; This split must be run before register allocation because it allocates the

74138

; memory slot that is needed to move values to/from the FPR. We don't allocate

74139

@@ -5186,7 +5644,8 @@

74140

rtx src = operands[1];

74141

rtx tmp;

74142

74143

- if (!MEM_P (src) && TARGET_MFPGPR && TARGET_POWERPC64)

74144

+ if (!MEM_P (src) && TARGET_POWERPC64

74145

+ && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))

74146

tmp = convert_to_mode (DImode, src, false);

74147

else

74148

{

74149

@@ -5235,12 +5694,15 @@

74150

(set_attr "type" "fpload")])

74151

74152

(define_insn "lfiwzx"

74153

- [(set (match_operand:DI 0 "gpc_reg_operand" "=d")

74154

- (unspec:DI [(match_operand:SI 1 "indexed_or_indirect_operand" "Z")]

74155

+ [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wm,!wm")

74156

+ (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]

74157

UNSPEC_LFIWZX))]

74158

"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX"

74159

- "lfiwzx %0,%y1"

74160

- [(set_attr "type" "fpload")])

74161

+ "@

74162

+ lfiwzx %0,%y1

74163

+ lxsiwzx %x0,%y1

74164

+ mtvsrwz %x0,%1"

74165

+ [(set_attr "type" "fpload,fpload,mftgpr")])

74166

74167

(define_insn_and_split "floatunssi<mode>2_lfiwzx"

74168

[(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")

74169

@@ -5257,7 +5719,8 @@

74170

rtx src = operands[1];

74171

rtx tmp;

74172

74173

- if (!MEM_P (src) && TARGET_MFPGPR && TARGET_POWERPC64)

74174

+ if (!MEM_P (src) && TARGET_POWERPC64

74175

+ && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))

74176

tmp = convert_to_mode (DImode, src, true);

74177

else

74178

{

74179

@@ -5548,7 +6011,7 @@

74180

emit_insn (gen_stfiwx (dest, tmp));

74181

DONE;

74182

}

74183

- else if (TARGET_MFPGPR && TARGET_POWERPC64)

74184

+ else if (TARGET_POWERPC64 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))

74185

{

74186

dest = gen_lowpart (DImode, dest);

74187

emit_move_insn (dest, tmp);

74188

@@ -5642,7 +6105,7 @@

74189

emit_insn (gen_stfiwx (dest, tmp));

74190

DONE;

74191

}

74192

- else if (TARGET_MFPGPR && TARGET_POWERPC64)

74193

+ else if (TARGET_POWERPC64 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))

74194

{

74195

dest = gen_lowpart (DImode, dest);

74196

emit_move_insn (dest, tmp);

74197

@@ -5781,66 +6244,52 @@

74198

[(set (match_operand:DI 0 "gpc_reg_operand" "=d")

74199

(unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]

74200

UNSPEC_FCTID))]

74201

- "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"

74202

+ "TARGET_<MODE>_FPR && TARGET_FPRND"

74203

"fctid %0,%1"

74204

[(set_attr "type" "fp")])

74205

74206

-(define_expand "btrunc<mode>2"

74207

- [(set (match_operand:SFDF 0 "gpc_reg_operand" "")

74208

- (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]

74209

+(define_insn "btrunc<mode>2"

74210

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")

74211

+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]

74212

UNSPEC_FRIZ))]

74213

- "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"

74214

- "")

74215

+ "TARGET_<MODE>_FPR && TARGET_FPRND"

74216

+ "@

74217

+ friz %0,%1

74218

+ xsrdpiz %x0,%x1"

74219

+ [(set_attr "type" "fp")

74220

+ (set_attr "fp_type" "fp_addsub_<Fs>")])

74221

74222

-(define_insn "*btrunc<mode>2_fpr"

74223

- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")

74224

- (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]

74225

- UNSPEC_FRIZ))]

74226

- "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>

74227

- && !VECTOR_UNIT_VSX_P (<MODE>mode)"

74228

- "friz %0,%1"

74229

- [(set_attr "type" "fp")])

74230

-

74231

-(define_expand "ceil<mode>2"

74232

- [(set (match_operand:SFDF 0 "gpc_reg_operand" "")

74233

- (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]

74234

+(define_insn "ceil<mode>2"

74235

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")

74236

+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]

74237

UNSPEC_FRIP))]

74238

- "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"

74239

- "")

74240

+ "TARGET_<MODE>_FPR && TARGET_FPRND"

74241

+ "@

74242

+ frip %0,%1

74243

+ xsrdpip %x0,%x1"

74244

+ [(set_attr "type" "fp")

74245

+ (set_attr "fp_type" "fp_addsub_<Fs>")])

74246

74247

-(define_insn "*ceil<mode>2_fpr"

74248

- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")

74249

- (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]

74250

- UNSPEC_FRIP))]

74251

- "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>

74252

- && !VECTOR_UNIT_VSX_P (<MODE>mode)"

74253

- "frip %0,%1"

74254

- [(set_attr "type" "fp")])

74255

-

74256

-(define_expand "floor<mode>2"

74257

- [(set (match_operand:SFDF 0 "gpc_reg_operand" "")

74258

- (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]

74259

+(define_insn "floor<mode>2"

74260

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")

74261

+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]

74262

UNSPEC_FRIM))]

74263

- "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"

74264

- "")

74265

+ "TARGET_<MODE>_FPR && TARGET_FPRND"

74266

+ "@

74267

+ frim %0,%1

74268

+ xsrdpim %x0,%x1"

74269

+ [(set_attr "type" "fp")

74270

+ (set_attr "fp_type" "fp_addsub_<Fs>")])

74271

74272

-(define_insn "*floor<mode>2_fpr"

74273

- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")

74274

- (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]

74275

- UNSPEC_FRIM))]

74276

- "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>

74277

- && !VECTOR_UNIT_VSX_P (<MODE>mode)"

74278

- "frim %0,%1"

74279

- [(set_attr "type" "fp")])

74280

-

74281

;; No VSX equivalent to frin

74282

(define_insn "round<mode>2"

74283

[(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")

74284

(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]

74285

UNSPEC_FRIN))]

74286

- "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"

74287

+ "TARGET_<MODE>_FPR && TARGET_FPRND"

74288

"frin %0,%1"

74289

- [(set_attr "type" "fp")])

74290

+ [(set_attr "type" "fp")

74291

+ (set_attr "fp_type" "fp_addsub_<Fs>")])

74292

74293

; An UNSPEC is used so we don't have to support SImode in FP registers.

74294

(define_insn "stfiwx"

74295

@@ -6084,6 +6533,49 @@

74296

[(set_attr "length" "8")

74297

(set_attr "type" "fpload")])

74298

74299

+;; Define the TImode operations that can be done in a small number

74300

+;; of instructions. The & constraints are to prevent the register

74301

+;; allocator from allocating registers that overlap with the inputs

74302

+;; (for example, having an input in 7,8 and an output in 6,7). We

74303

+;; also allow for the output being the same as one of the inputs.

74304

+

74305

+(define_insn "addti3"

74306

+ [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,&r,r,r")

74307

+ (plus:TI (match_operand:TI 1 "gpc_reg_operand" "%r,r,0,0")

74308

+ (match_operand:TI 2 "reg_or_short_operand" "r,I,r,I")))]

74309

+ "TARGET_64BIT"

74310

+{

74311

+ if (WORDS_BIG_ENDIAN)

74312

+ return (GET_CODE (operands[2])) != CONST_INT

74313

+ ? \"addc %L0,%L1,%L2\;adde %0,%1,%2\"

74314

+ : \"addic %L0,%L1,%2\;add%G2e %0,%1\";

74315

+ else

74316

+ return (GET_CODE (operands[2])) != CONST_INT

74317

+ ? \"addc %0,%1,%2\;adde %L0,%L1,%L2\"

74318

+ : \"addic %0,%1,%2\;add%G2e %L0,%L1\";

74319

+}

74320

+ [(set_attr "type" "two")

74321

+ (set_attr "length" "8")])

74322

+

74323

+(define_insn "subti3"

74324

+ [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,&r,r,r,r")

74325

+ (minus:TI (match_operand:TI 1 "reg_or_short_operand" "r,I,0,r,I")

74326

+ (match_operand:TI 2 "gpc_reg_operand" "r,r,r,0,0")))]

74327

+ "TARGET_64BIT"

74328

+{

74329

+ if (WORDS_BIG_ENDIAN)

74330

+ return (GET_CODE (operands[1]) != CONST_INT)

74331

+ ? \"subfc %L0,%L2,%L1\;subfe %0,%2,%1\"

74332

+ : \"subfic %L0,%L2,%1\;subf%G1e %0,%2\";

74333

+ else

74334

+ return (GET_CODE (operands[1]) != CONST_INT)

74335

+ ? \"subfc %0,%2,%1\;subfe %L0,%L2,%L1\"

74336

+ : \"subfic %0,%2,%1\;subf%G1e %L0,%L2\";

74337

+}

74338

+ [(set_attr "type" "two")

74339

+ (set_attr "length" "8")])

74340

+

74341

+

74342

;; Define the DImode operations that can be done in a small number

74343

;; of instructions. The & constraints are to prevent the register

74344

;; allocator from allocating registers that overlap with the inputs

74345

@@ -6260,11 +6752,11 @@

74346

[(set_attr "type" "two,three")

74347

(set_attr "length" "8,12")])

74348

74349

-(define_insn "*ashrdisi3_noppc64"

74350

+(define_insn "*ashrdisi3_noppc64be"

74351

[(set (match_operand:SI 0 "gpc_reg_operand" "=r")

74352

(subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")

74353

(const_int 32)) 4))]

74354

- "TARGET_32BIT && !TARGET_POWERPC64"

74355

+ "TARGET_32BIT && !TARGET_POWERPC64 && WORDS_BIG_ENDIAN"

74356

"*

74357

{

74358

if (REGNO (operands[0]) == REGNO (operands[1]))

74359

@@ -6551,19 +7043,31 @@

74360

(const_int 0)))]

74361

"")

74362

74363

-(define_insn "*rotldi3_internal7"

74364

+(define_insn "*rotldi3_internal7le"

74365

[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")

74366

(zero_extend:DI

74367

(subreg:QI

74368

(rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")

74369

(match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]

74370

- "TARGET_POWERPC64"

74371

+ "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"

74372

"@

74373

rldcl %0,%1,%2,56

74374

rldicl %0,%1,%H2,56"

74375

[(set_attr "type" "var_shift_rotate,integer")])

74376

74377

-(define_insn "*rotldi3_internal8"

74378

+(define_insn "*rotldi3_internal7be"

74379

+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")

74380

+ (zero_extend:DI

74381

+ (subreg:QI

74382

+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")

74383

+ (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 7)))]

74384

+ "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"

74385

+ "@

74386

+ rldcl %0,%1,%2,56

74387

+ rldicl %0,%1,%H2,56"

74388

+ [(set_attr "type" "var_shift_rotate,integer")])

74389

+

74390

+(define_insn "*rotldi3_internal8le"

74391

[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")

74392

(compare:CC (zero_extend:DI

74393

(subreg:QI

74394

@@ -6571,7 +7075,7 @@

74395

(match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))

74396

(const_int 0)))

74397

(clobber (match_scratch:DI 3 "=r,r,r,r"))]

74398

- "TARGET_64BIT"

74399

+ "TARGET_64BIT && !BYTES_BIG_ENDIAN"

74400

"@

74401

rldcl. %3,%1,%2,56

74402

rldicl. %3,%1,%H2,56

74403

@@ -6580,6 +7084,23 @@

74404

[(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

74405

(set_attr "length" "4,4,8,8")])

74406

74407

+(define_insn "*rotldi3_internal8be"

74408

+ [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")

74409

+ (compare:CC (zero_extend:DI

74410

+ (subreg:QI

74411

+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")

74412

+ (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 7))

74413

+ (const_int 0)))

74414

+ (clobber (match_scratch:DI 3 "=r,r,r,r"))]

74415

+ "TARGET_64BIT && BYTES_BIG_ENDIAN"

74416

+ "@

74417

+ rldcl. %3,%1,%2,56

74418

+ rldicl. %3,%1,%H2,56

74419

+ #

74420

+ #"

74421

+ [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

74422

+ (set_attr "length" "4,4,8,8")])

74423

+

74424

(define_split

74425

[(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")

74426

(compare:CC (zero_extend:DI

74427

@@ -6588,7 +7109,7 @@

74428

(match_operand:DI 2 "reg_or_cint_operand" "")) 0))

74429

(const_int 0)))

74430

(clobber (match_scratch:DI 3 ""))]

74431

- "TARGET_POWERPC64 && reload_completed"

74432

+ "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"

74433

[(set (match_dup 3)

74434

(zero_extend:DI (subreg:QI

74435

(rotate:DI (match_dup 1)

74436

@@ -6598,7 +7119,25 @@

74437

(const_int 0)))]

74438

"")

74439

74440

-(define_insn "*rotldi3_internal9"

74441

+(define_split

74442

+ [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")

74443

+ (compare:CC (zero_extend:DI

74444

+ (subreg:QI

74445

+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")

74446

+ (match_operand:DI 2 "reg_or_cint_operand" "")) 7))

74447

+ (const_int 0)))

74448

+ (clobber (match_scratch:DI 3 ""))]

74449

+ "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"

74450

+ [(set (match_dup 3)

74451

+ (zero_extend:DI (subreg:QI

74452

+ (rotate:DI (match_dup 1)

74453

+ (match_dup 2)) 7)))

74454

+ (set (match_dup 0)

74455

+ (compare:CC (match_dup 3)

74456

+ (const_int 0)))]

74457

+ "")

74458

+

74459

+(define_insn "*rotldi3_internal9le"

74460

[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")

74461

(compare:CC (zero_extend:DI

74462

(subreg:QI

74463

@@ -6607,7 +7146,7 @@

74464

(const_int 0)))

74465

(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")

74466

(zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]

74467

- "TARGET_64BIT"

74468

+ "TARGET_64BIT && !BYTES_BIG_ENDIAN"

74469

"@

74470

rldcl. %0,%1,%2,56

74471

rldicl. %0,%1,%H2,56

74472

@@ -6616,6 +7155,24 @@

74473

[(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

74474

(set_attr "length" "4,4,8,8")])

74475

74476

+(define_insn "*rotldi3_internal9be"

74477

+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")

74478

+ (compare:CC (zero_extend:DI

74479

+ (subreg:QI

74480

+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")

74481

+ (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 7))

74482

+ (const_int 0)))

74483

+ (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")

74484

+ (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]

74485

+ "TARGET_64BIT && BYTES_BIG_ENDIAN"

74486

+ "@

74487

+ rldcl. %0,%1,%2,56

74488

+ rldicl. %0,%1,%H2,56

74489

+ #

74490

+ #"

74491

+ [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

74492

+ (set_attr "length" "4,4,8,8")])

74493

+

74494

(define_split

74495

[(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")

74496

(compare:CC (zero_extend:DI

74497

@@ -6625,7 +7182,7 @@

74498

(const_int 0)))

74499

(set (match_operand:DI 0 "gpc_reg_operand" "")

74500

(zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]

74501

- "TARGET_POWERPC64 && reload_completed"

74502

+ "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"

74503

[(set (match_dup 0)

74504

(zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))

74505

(set (match_dup 3)

74506

@@ -6633,19 +7190,48 @@

74507

(const_int 0)))]

74508

"")

74509

74510

-(define_insn "*rotldi3_internal10"

74511

+(define_split

74512

+ [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")

74513

+ (compare:CC (zero_extend:DI

74514

+ (subreg:QI

74515

+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")

74516

+ (match_operand:DI 2 "reg_or_cint_operand" "")) 7))

74517

+ (const_int 0)))

74518

+ (set (match_operand:DI 0 "gpc_reg_operand" "")

74519

+ (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]

74520

+ "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"

74521

+ [(set (match_dup 0)

74522

+ (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))

74523

+ (set (match_dup 3)

74524

+ (compare:CC (match_dup 0)

74525

+ (const_int 0)))]

74526

+ "")

74527

+

74528

+(define_insn "*rotldi3_internal10le"

74529

[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")

74530

(zero_extend:DI

74531

(subreg:HI

74532

(rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")

74533

(match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]

74534

- "TARGET_POWERPC64"

74535

+ "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"

74536

"@

74537

rldcl %0,%1,%2,48

74538

rldicl %0,%1,%H2,48"

74539

[(set_attr "type" "var_shift_rotate,integer")])

74540

74541

-(define_insn "*rotldi3_internal11"

74542

+(define_insn "*rotldi3_internal10be"

74543

+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")

74544

+ (zero_extend:DI

74545

+ (subreg:HI

74546

+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")

74547

+ (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 6)))]

74548

+ "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"

74549

+ "@

74550

+ rldcl %0,%1,%2,48

74551

+ rldicl %0,%1,%H2,48"

74552

+ [(set_attr "type" "var_shift_rotate,integer")])

74553

+

74554

+(define_insn "*rotldi3_internal11le"

74555

[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")

74556

(compare:CC (zero_extend:DI

74557

(subreg:HI

74558

@@ -6653,7 +7239,7 @@

74559

(match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))

74560

(const_int 0)))

74561

(clobber (match_scratch:DI 3 "=r,r,r,r"))]

74562

- "TARGET_64BIT"

74563

+ "TARGET_64BIT && !BYTES_BIG_ENDIAN"

74564

"@

74565

rldcl. %3,%1,%2,48

74566

rldicl. %3,%1,%H2,48

74567

@@ -6662,6 +7248,23 @@

74568

[(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

74569

(set_attr "length" "4,4,8,8")])

74570

74571

+(define_insn "*rotldi3_internal11be"

74572

+ [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")

74573

+ (compare:CC (zero_extend:DI

74574

+ (subreg:HI

74575

+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")

74576

+ (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 6))

74577

+ (const_int 0)))

74578

+ (clobber (match_scratch:DI 3 "=r,r,r,r"))]

74579

+ "TARGET_64BIT && BYTES_BIG_ENDIAN"

74580

+ "@

74581

+ rldcl. %3,%1,%2,48

74582

+ rldicl. %3,%1,%H2,48

74583

+ #

74584

+ #"

74585

+ [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

74586

+ (set_attr "length" "4,4,8,8")])

74587

+

74588

(define_split

74589

[(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")

74590

(compare:CC (zero_extend:DI

74591

@@ -6670,7 +7273,7 @@

74592

(match_operand:DI 2 "reg_or_cint_operand" "")) 0))

74593

(const_int 0)))

74594

(clobber (match_scratch:DI 3 ""))]

74595

- "TARGET_POWERPC64 && reload_completed"

74596

+ "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"

74597

[(set (match_dup 3)

74598

(zero_extend:DI (subreg:HI

74599

(rotate:DI (match_dup 1)

74600

@@ -6680,7 +7283,25 @@

74601

(const_int 0)))]

74602

"")

74603

74604

-(define_insn "*rotldi3_internal12"

74605

+(define_split

74606

+ [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")

74607

+ (compare:CC (zero_extend:DI

74608

+ (subreg:HI

74609

+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")

74610

+ (match_operand:DI 2 "reg_or_cint_operand" "")) 6))

74611

+ (const_int 0)))

74612

+ (clobber (match_scratch:DI 3 ""))]

74613

+ "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"

74614

+ [(set (match_dup 3)

74615

+ (zero_extend:DI (subreg:HI

74616

+ (rotate:DI (match_dup 1)

74617

+ (match_dup 2)) 6)))

74618

+ (set (match_dup 0)

74619

+ (compare:CC (match_dup 3)

74620

+ (const_int 0)))]

74621

+ "")

74622

+

74623

+(define_insn "*rotldi3_internal12le"

74624

[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")

74625

(compare:CC (zero_extend:DI

74626

(subreg:HI

74627

@@ -6689,7 +7310,7 @@

74628

(const_int 0)))

74629

(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")

74630

(zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]

74631

- "TARGET_64BIT"

74632

+ "TARGET_64BIT && !BYTES_BIG_ENDIAN"

74633

"@

74634

rldcl. %0,%1,%2,48

74635

rldicl. %0,%1,%H2,48

74636

@@ -6698,6 +7319,24 @@

74637

[(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

74638

(set_attr "length" "4,4,8,8")])

74639

74640

+(define_insn "*rotldi3_internal12be"

74641

+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")

74642

+ (compare:CC (zero_extend:DI

74643

+ (subreg:HI

74644

+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")

74645

+ (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 6))

74646

+ (const_int 0)))

74647

+ (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")

74648

+ (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]

74649

+ "TARGET_64BIT && BYTES_BIG_ENDIAN"

74650

+ "@

74651

+ rldcl. %0,%1,%2,48

74652

+ rldicl. %0,%1,%H2,48

74653

+ #

74654

+ #"

74655

+ [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

74656

+ (set_attr "length" "4,4,8,8")])

74657

+

74658

(define_split

74659

[(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")

74660

(compare:CC (zero_extend:DI

74661

@@ -6707,7 +7346,7 @@

74662

(const_int 0)))

74663

(set (match_operand:DI 0 "gpc_reg_operand" "")

74664

(zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]

74665

- "TARGET_POWERPC64 && reload_completed"

74666

+ "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"

74667

[(set (match_dup 0)

74668

(zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))

74669

(set (match_dup 3)

74670

@@ -6715,19 +7354,48 @@

74671

(const_int 0)))]

74672

"")

74673

74674

-(define_insn "*rotldi3_internal13"

74675

+(define_split

74676

+ [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")

74677

+ (compare:CC (zero_extend:DI

74678

+ (subreg:HI

74679

+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")

74680

+ (match_operand:DI 2 "reg_or_cint_operand" "")) 6))

74681

+ (const_int 0)))

74682

+ (set (match_operand:DI 0 "gpc_reg_operand" "")

74683

+ (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]

74684

+ "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"

74685

+ [(set (match_dup 0)

74686

+ (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))

74687

+ (set (match_dup 3)

74688

+ (compare:CC (match_dup 0)

74689

+ (const_int 0)))]

74690

+ "")

74691

+

74692

+(define_insn "*rotldi3_internal13le"

74693

[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")

74694

(zero_extend:DI

74695

(subreg:SI

74696

(rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")

74697

(match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]

74698

- "TARGET_POWERPC64"

74699

+ "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"

74700

"@

74701

rldcl %0,%1,%2,32

74702

rldicl %0,%1,%H2,32"

74703

[(set_attr "type" "var_shift_rotate,integer")])

74704

74705

-(define_insn "*rotldi3_internal14"

74706

+(define_insn "*rotldi3_internal13be"

74707

+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")

74708

+ (zero_extend:DI

74709

+ (subreg:SI

74710

+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")

74711

+ (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 4)))]

74712

+ "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"

74713

+ "@

74714

+ rldcl %0,%1,%2,32

74715

+ rldicl %0,%1,%H2,32"

74716

+ [(set_attr "type" "var_shift_rotate,integer")])

74717

+

74718

+(define_insn "*rotldi3_internal14le"

74719

[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")

74720

(compare:CC (zero_extend:DI

74721

(subreg:SI

74722

@@ -6735,7 +7403,7 @@

74723

(match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))

74724

(const_int 0)))

74725

(clobber (match_scratch:DI 3 "=r,r,r,r"))]

74726

- "TARGET_64BIT"

74727

+ "TARGET_64BIT && !BYTES_BIG_ENDIAN"

74728

"@

74729

rldcl. %3,%1,%2,32

74730

rldicl. %3,%1,%H2,32

74731

@@ -6744,6 +7412,23 @@

74732

[(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

74733

(set_attr "length" "4,4,8,8")])

74734

74735

+(define_insn "*rotldi3_internal14be"

74736

+ [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")

74737

+ (compare:CC (zero_extend:DI

74738

+ (subreg:SI

74739

+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")

74740

+ (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 4))

74741

+ (const_int 0)))

74742

+ (clobber (match_scratch:DI 3 "=r,r,r,r"))]

74743

+ "TARGET_64BIT && BYTES_BIG_ENDIAN"

74744

+ "@

74745

+ rldcl. %3,%1,%2,32

74746

+ rldicl. %3,%1,%H2,32

74747

+ #

74748

+ #"

74749

+ [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

74750

+ (set_attr "length" "4,4,8,8")])

74751

+

74752

(define_split

74753

[(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")

74754

(compare:CC (zero_extend:DI

74755

@@ -6752,7 +7437,7 @@

74756

(match_operand:DI 2 "reg_or_cint_operand" "")) 0))

74757

(const_int 0)))

74758

(clobber (match_scratch:DI 3 ""))]

74759

- "TARGET_POWERPC64 && reload_completed"

74760

+ "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"

74761

[(set (match_dup 3)

74762

(zero_extend:DI (subreg:SI

74763

(rotate:DI (match_dup 1)

74764

@@ -6762,7 +7447,25 @@

74765

(const_int 0)))]

74766

"")

74767

74768

-(define_insn "*rotldi3_internal15"

74769

+(define_split

74770

+ [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")

74771

+ (compare:CC (zero_extend:DI

74772

+ (subreg:SI

74773

+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")

74774

+ (match_operand:DI 2 "reg_or_cint_operand" "")) 4))

74775

+ (const_int 0)))

74776

+ (clobber (match_scratch:DI 3 ""))]

74777

+ "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"

74778

+ [(set (match_dup 3)

74779

+ (zero_extend:DI (subreg:SI

74780

+ (rotate:DI (match_dup 1)

74781

+ (match_dup 2)) 4)))

74782

+ (set (match_dup 0)

74783

+ (compare:CC (match_dup 3)

74784

+ (const_int 0)))]

74785

+ "")

74786

+

74787

+(define_insn "*rotldi3_internal15le"

74788

[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")

74789

(compare:CC (zero_extend:DI

74790

(subreg:SI

74791

@@ -6771,7 +7474,7 @@

74792

(const_int 0)))

74793

(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")

74794

(zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]

74795

- "TARGET_64BIT"

74796

+ "TARGET_64BIT && !BYTES_BIG_ENDIAN"

74797

"@

74798

rldcl. %0,%1,%2,32

74799

rldicl. %0,%1,%H2,32

74800

@@ -6780,6 +7483,24 @@

74801

[(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

74802

(set_attr "length" "4,4,8,8")])

74803

74804

+(define_insn "*rotldi3_internal15be"

74805

+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")

74806

+ (compare:CC (zero_extend:DI

74807

+ (subreg:SI

74808

+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")

74809

+ (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 4))

74810

+ (const_int 0)))

74811

+ (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")

74812

+ (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]

74813

+ "TARGET_64BIT && BYTES_BIG_ENDIAN"

74814

+ "@

74815

+ rldcl. %0,%1,%2,32

74816

+ rldicl. %0,%1,%H2,32

74817

+ #

74818

+ #"

74819

+ [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

74820

+ (set_attr "length" "4,4,8,8")])

74821

+

74822

(define_split

74823

[(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")

74824

(compare:CC (zero_extend:DI

74825

@@ -6789,7 +7510,7 @@

74826

(const_int 0)))

74827

(set (match_operand:DI 0 "gpc_reg_operand" "")

74828

(zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]

74829

- "TARGET_POWERPC64 && reload_completed"

74830

+ "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"

74831

[(set (match_dup 0)

74832

(zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))

74833

(set (match_dup 3)

74834

@@ -6797,6 +7518,23 @@

74835

(const_int 0)))]

74836

"")

74837

74838

+(define_split

74839

+ [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")

74840

+ (compare:CC (zero_extend:DI

74841

+ (subreg:SI

74842

+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")

74843

+ (match_operand:DI 2 "reg_or_cint_operand" "")) 4))

74844

+ (const_int 0)))

74845

+ (set (match_operand:DI 0 "gpc_reg_operand" "")

74846

+ (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]

74847

+ "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"

74848

+ [(set (match_dup 0)

74849

+ (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))

74850

+ (set (match_dup 3)

74851

+ (compare:CC (match_dup 0)

74852

+ (const_int 0)))]

74853

+ "")

74854

+

74855

(define_expand "ashldi3"

74856

[(set (match_operand:DI 0 "gpc_reg_operand" "")

74857

(ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")

74858

@@ -7195,10 +7933,19 @@

74859

[(parallel

74860

[(set (match_operand:DI 0 "gpc_reg_operand" "")

74861

(and:DI (match_operand:DI 1 "gpc_reg_operand" "")

74862

- (match_operand:DI 2 "and64_2_operand" "")))

74863

+ (match_operand:DI 2 "reg_or_cint_operand" "")))

74864

(clobber (match_scratch:CC 3 ""))])]

74865

- "TARGET_POWERPC64"

74866

- "")

74867

+ ""

74868

+{

74869

+ if (!TARGET_POWERPC64)

74870

+ {

74871

+ rtx cc = gen_rtx_SCRATCH (CCmode);

74872

+ rs6000_split_logical (operands, AND, false, false, false, cc);

74873

+ DONE;

74874

+ }

74875

+ else if (!and64_2_operand (operands[2], DImode))

74876

+ operands[2] = force_reg (DImode, operands[2]);

74877

+})

74878

74879

(define_insn "anddi3_mc"

74880

[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")

74881

@@ -7379,12 +8126,18 @@

74882

(define_expand "iordi3"

74883

[(set (match_operand:DI 0 "gpc_reg_operand" "")

74884

(ior:DI (match_operand:DI 1 "gpc_reg_operand" "")

74885

- (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]

74886

- "TARGET_POWERPC64"

74887

- "

74888

+ (match_operand:DI 2 "reg_or_cint_operand" "")))]

74889

+ ""

74890

{

74891

- if (non_logical_cint_operand (operands[2], DImode))

74892

+ if (!TARGET_POWERPC64)

74893

{

74894

+ rs6000_split_logical (operands, IOR, false, false, false, NULL_RTX);

74895

+ DONE;

74896

+ }

74897

+ else if (!reg_or_logical_cint_operand (operands[2], DImode))

74898

+ operands[2] = force_reg (DImode, operands[2]);

74899

+ else if (non_logical_cint_operand (operands[2], DImode))

74900

+ {

74901

HOST_WIDE_INT value;

74902

rtx tmp = ((!can_create_pseudo_p ()

74903

|| rtx_equal_p (operands[0], operands[1]))

74904

@@ -7408,15 +8161,21 @@

74905

emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));

74906

DONE;

74907

}

74908

-}")

74909

+})

74910

74911

(define_expand "xordi3"

74912

[(set (match_operand:DI 0 "gpc_reg_operand" "")

74913

(xor:DI (match_operand:DI 1 "gpc_reg_operand" "")

74914

- (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]

74915

- "TARGET_POWERPC64"

74916

- "

74917

+ (match_operand:DI 2 "reg_or_cint_operand" "")))]

74918

+ ""

74919

{

74920

+ if (!TARGET_POWERPC64)

74921

+ {

74922

+ rs6000_split_logical (operands, XOR, false, false, false, NULL_RTX);

74923

+ DONE;

74924

+ }

74925

+ else if (!reg_or_logical_cint_operand (operands[2], DImode))

74926

+ operands[2] = force_reg (DImode, operands[2]);

74927

if (non_logical_cint_operand (operands[2], DImode))

74928

{

74929

HOST_WIDE_INT value;

74930

@@ -7442,7 +8201,7 @@

74931

emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));

74932

DONE;

74933

}

74934

-}")

74935

+})

74936

74937

(define_insn "*booldi3_internal1"

74938

[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")

74939

@@ -7678,7 +8437,385 @@

74940

(compare:CC (match_dup 0)

74941

(const_int 0)))]

74942

"")

74943

+

74944

+;; Eqv operation.

74945

+(define_insn "*eqv<mode>3"

74946

+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")

74947

+ (not:GPR

74948

+ (xor:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")

74949

+ (match_operand:GPR 2 "gpc_reg_operand" "r"))))]

74950

+ ""

74951

+ "eqv %0,%1,%2"

74952

+ [(set_attr "type" "integer")

74953

+ (set_attr "length" "4")])

74954

+

74955

74956

+;; 128-bit logical operations expanders

74957

+

74958

+(define_expand "and<mode>3"

74959

+ [(parallel [(set (match_operand:BOOL_128 0 "vlogical_operand" "")

74960

+ (and:BOOL_128

74961

+ (match_operand:BOOL_128 1 "vlogical_operand" "")

74962

+ (match_operand:BOOL_128 2 "vlogical_operand" "")))

74963

+ (clobber (match_scratch:CC 3 ""))])]

74964

+ ""

74965

+ "")

74966

+

74967

+(define_expand "ior<mode>3"

74968

+ [(set (match_operand:BOOL_128 0 "vlogical_operand" "")

74969

+ (ior:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")

74970

+ (match_operand:BOOL_128 2 "vlogical_operand" "")))]

74971

+ ""

74972

+ "")

74973

+

74974

+(define_expand "xor<mode>3"

74975

+ [(set (match_operand:BOOL_128 0 "vlogical_operand" "")

74976

+ (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")

74977

+ (match_operand:BOOL_128 2 "vlogical_operand" "")))]

74978

+ ""

74979

+ "")

74980

+

74981

+(define_expand "one_cmpl<mode>2"

74982

+ [(set (match_operand:BOOL_128 0 "vlogical_operand" "")

74983

+ (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")))]

74984

+ ""

74985

+ "")

74986

+

74987

+(define_expand "nor<mode>3"

74988

+ [(set (match_operand:BOOL_128 0 "vlogical_operand" "")

74989

+ (and:BOOL_128

74990

+ (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" ""))

74991

+ (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]

74992

+ ""

74993

+ "")

74994

+

74995

+(define_expand "andc<mode>3"

74996

+ [(set (match_operand:BOOL_128 0 "vlogical_operand" "")

74997

+ (and:BOOL_128

74998

+ (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))

74999

+ (match_operand:BOOL_128 1 "vlogical_operand" "")))]

75000

+ ""

75001

+ "")

75002

+

75003

+;; Power8 vector logical instructions.

75004

+(define_expand "eqv<mode>3"

75005

+ [(set (match_operand:BOOL_128 0 "vlogical_operand" "")

75006

+ (not:BOOL_128

75007

+ (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")

75008

+ (match_operand:BOOL_128 2 "vlogical_operand" ""))))]

75009

+ "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"

75010

+ "")

75011

+

75012

+;; Rewrite nand into canonical form

75013

+(define_expand "nand<mode>3"

75014

+ [(set (match_operand:BOOL_128 0 "vlogical_operand" "")

75015

+ (ior:BOOL_128

75016

+ (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" ""))

75017

+ (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]

75018

+ "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"

75019

+ "")

75020

+

75021

+;; The canonical form is to have the negated element first, so we need to

75022

+;; reverse arguments.

75023

+(define_expand "orc<mode>3"

75024

+ [(set (match_operand:BOOL_128 0 "vlogical_operand" "")

75025

+ (ior:BOOL_128

75026

+ (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))

75027

+ (match_operand:BOOL_128 1 "vlogical_operand" "")))]

75028

+ "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"

75029

+ "")

75030

+

75031

+;; 128-bit logical operations insns and split operations

75032

+(define_insn_and_split "*and<mode>3_internal"

75033

+ [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")

75034

+ (and:BOOL_128

75035

+ (match_operand:BOOL_128 1 "vlogical_operand" "%<BOOL_REGS_OP1>")

75036

+ (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>")))

75037

+ (clobber (match_scratch:CC 3 "<BOOL_REGS_AND_CR0>"))]

75038

+ ""

75039

+{

75040

+ if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))

75041

+ return "xxland %x0,%x1,%x2";

75042

+

75043

+ if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))

75044

+ return "vand %0,%1,%2";

75045

+

75046

+ return "#";

75047

+}

75048

+ "reload_completed && int_reg_operand (operands[0], <MODE>mode)"

75049

+ [(const_int 0)]

75050

+{

75051

+ rs6000_split_logical (operands, AND, false, false, false, operands[3]);

75052

+ DONE;

75053

+}

75054

+ [(set (attr "type")

75055

+ (if_then_else

75056

+ (match_test "vsx_register_operand (operands[0], <MODE>mode)")

75057

+ (const_string "vecsimple")

75058

+ (const_string "integer")))

75059

+ (set (attr "length")

75060

+ (if_then_else

75061

+ (match_test "vsx_register_operand (operands[0], <MODE>mode)")

75062

+ (const_string "4")

75063

+ (if_then_else

75064

+ (match_test "TARGET_POWERPC64")

75065

+ (const_string "8")

75066

+ (const_string "16"))))])

75067

+

75068

+;; 128-bit IOR/XOR

75069

+(define_insn_and_split "*bool<mode>3_internal"

75070

+ [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")

75071

+ (match_operator:BOOL_128 3 "boolean_or_operator"

75072

+ [(match_operand:BOOL_128 1 "vlogical_operand" "%<BOOL_REGS_OP1>")

75073

+ (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>")]))]

75074

+ ""

75075

+{

75076

+ if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))

75077

+ return "xxl%q3 %x0,%x1,%x2";

75078

+

75079

+ if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))

75080

+ return "v%q3 %0,%1,%2";

75081

+

75082

+ return "#";

75083

+}

75084

+ "reload_completed && int_reg_operand (operands[0], <MODE>mode)"

75085

+ [(const_int 0)]

75086

+{

75087

+ rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, false,

75088

+ NULL_RTX);

75089

+ DONE;

75090

+}

75091

+ [(set (attr "type")

75092

+ (if_then_else

75093

+ (match_test "vsx_register_operand (operands[0], <MODE>mode)")

75094

+ (const_string "vecsimple")

75095

+ (const_string "integer")))

75096

+ (set (attr "length")

75097

+ (if_then_else

75098

+ (match_test "vsx_register_operand (operands[0], <MODE>mode)")

75099

+ (const_string "4")

75100

+ (if_then_else

75101

+ (match_test "TARGET_POWERPC64")

75102

+ (const_string "8")

75103

+ (const_string "16"))))])

75104

+

75105

+;; 128-bit ANDC/ORC

75106

+(define_insn_and_split "*boolc<mode>3_internal1"

75107

+ [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")

75108

+ (match_operator:BOOL_128 3 "boolean_operator"

75109

+ [(not:BOOL_128

75110

+ (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP1>"))

75111

+ (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP2>")]))]

75112

+ "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)"

75113

+{

75114

+ if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))

75115

+ return "xxl%q3 %x0,%x1,%x2";

75116

+

75117

+ if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))

75118

+ return "v%q3 %0,%1,%2";

75119

+

75120

+ return "#";

75121

+}

75122

+ "(TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND))

75123

+ && reload_completed && int_reg_operand (operands[0], <MODE>mode)"

75124

+ [(const_int 0)]

75125

+{

75126

+ rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false,

75127

+ NULL_RTX);

75128

+ DONE;

75129

+}

75130

+ [(set (attr "type")

75131

+ (if_then_else

75132

+ (match_test "vsx_register_operand (operands[0], <MODE>mode)")

75133

+ (const_string "vecsimple")

75134

+ (const_string "integer")))

75135

+ (set (attr "length")

75136

+ (if_then_else

75137

+ (match_test "vsx_register_operand (operands[0], <MODE>mode)")

75138

+ (const_string "4")

75139

+ (if_then_else

75140

+ (match_test "TARGET_POWERPC64")

75141

+ (const_string "8")

75142

+ (const_string "16"))))])

75143

+

75144

+(define_insn_and_split "*boolc<mode>3_internal2"

75145

+ [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")

75146

+ (match_operator:TI2 3 "boolean_operator"

75147

+ [(not:TI2

75148

+ (match_operand:TI2 1 "int_reg_operand" "r,0,r"))

75149

+ (match_operand:TI2 2 "int_reg_operand" "r,r,0")]))]

75150

+ "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"

75151

+ "#"

75152

+ "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"

75153

+ [(const_int 0)]

75154

+{

75155

+ rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false,

75156

+ NULL_RTX);

75157

+ DONE;

75158

+}

75159

+ [(set_attr "type" "integer")

75160

+ (set (attr "length")

75161

+ (if_then_else

75162

+ (match_test "TARGET_POWERPC64")

75163

+ (const_string "8")

75164

+ (const_string "16")))])

75165

+

75166

+;; 128-bit NAND/NOR

75167

+(define_insn_and_split "*boolcc<mode>3_internal1"

75168

+ [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")

75169

+ (match_operator:BOOL_128 3 "boolean_operator"

75170

+ [(not:BOOL_128

75171

+ (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>"))

75172

+ (not:BOOL_128

75173

+ (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))]))]

75174

+ "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)"

75175

+{

75176

+ if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))

75177

+ return "xxl%q3 %x0,%x1,%x2";

75178

+

75179

+ if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))

75180

+ return "v%q3 %0,%1,%2";

75181

+

75182

+ return "#";

75183

+}

75184

+ "(TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND))

75185

+ && reload_completed && int_reg_operand (operands[0], <MODE>mode)"

75186

+ [(const_int 0)]

75187

+{

75188

+ rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true,

75189

+ NULL_RTX);

75190

+ DONE;

75191

+}

75192

+ [(set (attr "type")

75193

+ (if_then_else

75194

+ (match_test "vsx_register_operand (operands[0], <MODE>mode)")

75195

+ (const_string "vecsimple")

75196

+ (const_string "integer")))

75197

+ (set (attr "length")

75198

+ (if_then_else

75199

+ (match_test "vsx_register_operand (operands[0], <MODE>mode)")

75200

+ (const_string "4")

75201

+ (if_then_else

75202

+ (match_test "TARGET_POWERPC64")

75203

+ (const_string "8")

75204

+ (const_string "16"))))])

75205

+

75206

+(define_insn_and_split "*boolcc<mode>3_internal2"

75207

+ [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")

75208

+ (match_operator:TI2 3 "boolean_operator"

75209

+ [(not:TI2

75210

+ (match_operand:TI2 1 "int_reg_operand" "r,0,r"))

75211

+ (not:TI2

75212

+ (match_operand:TI2 2 "int_reg_operand" "r,r,0"))]))]

75213

+ "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"

75214

+ "#"

75215

+ "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"

75216

+ [(const_int 0)]

75217

+{

75218

+ rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true,

75219

+ NULL_RTX);

75220

+ DONE;

75221

+}

75222

+ [(set_attr "type" "integer")

75223

+ (set (attr "length")

75224

+ (if_then_else

75225

+ (match_test "TARGET_POWERPC64")

75226

+ (const_string "8")

75227

+ (const_string "16")))])

75228

+

75229

+

75230

+;; 128-bit EQV

75231

+(define_insn_and_split "*eqv<mode>3_internal1"

75232

+ [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")

75233

+ (not:BOOL_128

75234

+ (xor:BOOL_128

75235

+ (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>")

75236

+ (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))))]

75237

+ "TARGET_P8_VECTOR"

75238

+{

75239

+ if (vsx_register_operand (operands[0], <MODE>mode))

75240

+ return "xxleqv %x0,%x1,%x2";

75241

+

75242

+ return "#";

75243

+}

75244

+ "TARGET_P8_VECTOR && reload_completed

75245

+ && int_reg_operand (operands[0], <MODE>mode)"

75246

+ [(const_int 0)]

75247

+{

75248

+ rs6000_split_logical (operands, XOR, true, false, false, NULL_RTX);

75249

+ DONE;

75250

+}

75251

+ [(set (attr "type")

75252

+ (if_then_else

75253

+ (match_test "vsx_register_operand (operands[0], <MODE>mode)")

75254

+ (const_string "vecsimple")

75255

+ (const_string "integer")))

75256

+ (set (attr "length")

75257

+ (if_then_else

75258

+ (match_test "vsx_register_operand (operands[0], <MODE>mode)")

75259

+ (const_string "4")

75260

+ (if_then_else

75261

+ (match_test "TARGET_POWERPC64")

75262

+ (const_string "8")

75263

+ (const_string "16"))))])

75264

+

75265

+(define_insn_and_split "*eqv<mode>3_internal2"

75266

+ [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")

75267

+ (not:TI2

75268

+ (xor:TI2

75269

+ (match_operand:TI2 1 "int_reg_operand" "r,0,r")

75270

+ (match_operand:TI2 2 "int_reg_operand" "r,r,0"))))]

75271

+ "!TARGET_P8_VECTOR"

75272

+ "#"

75273

+ "reload_completed && !TARGET_P8_VECTOR"

75274

+ [(const_int 0)]

75275

+{

75276

+ rs6000_split_logical (operands, XOR, true, false, false, NULL_RTX);

75277

+ DONE;

75278

+}

75279

+ [(set_attr "type" "integer")

75280

+ (set (attr "length")

75281

+ (if_then_else

75282

+ (match_test "TARGET_POWERPC64")

75283

+ (const_string "8")

75284

+ (const_string "16")))])

75285

+

75286

+;; 128-bit one's complement

75287

+(define_insn_and_split "*one_cmpl<mode>3_internal"

75288

+ [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")

75289

+ (not:BOOL_128

75290

+ (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_UNARY>")))]

75291

+ ""

75292

+{

75293

+ if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))

75294

+ return "xxlnor %x0,%x1,%x1";

75295

+

75296

+ if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))

75297

+ return "vnor %0,%1,%1";

75298

+

75299

+ return "#";

75300

+}

75301

+ "reload_completed && int_reg_operand (operands[0], <MODE>mode)"

75302

+ [(const_int 0)]

75303

+{

75304

+ rs6000_split_logical (operands, NOT, false, false, false, NULL_RTX);

75305

+ DONE;

75306

+}

75307

+ [(set (attr "type")

75308

+ (if_then_else

75309

+ (match_test "vsx_register_operand (operands[0], <MODE>mode)")

75310

+ (const_string "vecsimple")

75311

+ (const_string "integer")))

75312

+ (set (attr "length")

75313

+ (if_then_else

75314

+ (match_test "vsx_register_operand (operands[0], <MODE>mode)")

75315

+ (const_string "4")

75316

+ (if_then_else

75317

+ (match_test "TARGET_POWERPC64")

75318

+ (const_string "8")

75319

+ (const_string "16"))))])

75320

+

75321

+

75322

;; Now define ways of moving data around.

75323

75324

;; Set up a register with a value from the GOT table

75325

@@ -7765,7 +8902,31 @@

75326

mt%0 %1

75327

mt%0 %1

75328

nop"

75329

- [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*")

75330

+ [(set_attr_alternative "type"

75331

+ [(const_string "*")

75332

+ (const_string "*")

75333

+ (if_then_else

75334

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

75335

+ (const_string "load_ux")

75336

+ (if_then_else

75337

+ (match_test "update_address_mem (operands[1], VOIDmode)")

75338

+ (const_string "load_u")

75339

+ (const_string "load")))

75340

+ (if_then_else

75341

+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")

75342

+ (const_string "store_ux")

75343

+ (if_then_else

75344

+ (match_test "update_address_mem (operands[0], VOIDmode)")

75345

+ (const_string "store_u")

75346

+ (const_string "store")))

75347

+ (const_string "*")

75348

+ (const_string "*")

75349

+ (const_string "*")

75350

+ (const_string "mfjmpr")

75351

+ (const_string "mtjmpr")

75352

+ (const_string "*")

75353

+ (const_string "*")])

75354

+

75355

(set_attr "length" "4,4,4,4,4,4,8,4,4,4,4")])

75356

75357

(define_insn "*movsi_internal1_single"

75358

@@ -7787,7 +8948,44 @@

75359

nop

75360

stfs%U0%X0 %1,%0

75361

lfs%U1%X1 %0,%1"

75362

- [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*,*,*")

75363

+ [(set_attr_alternative "type"

75364

+ [(const_string "*")

75365

+ (const_string "*")

75366

+ (if_then_else

75367

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

75368

+ (const_string "load_ux")

75369

+ (if_then_else

75370

+ (match_test "update_address_mem (operands[1], VOIDmode)")

75371

+ (const_string "load_u")

75372

+ (const_string "load")))

75373

+ (if_then_else

75374

+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")

75375

+ (const_string "store_ux")

75376

+ (if_then_else

75377

+ (match_test "update_address_mem (operands[0], VOIDmode)")

75378

+ (const_string "store_u")

75379

+ (const_string "store")))

75380

+ (const_string "*")

75381

+ (const_string "*")

75382

+ (const_string "*")

75383

+ (const_string "mfjmpr")

75384

+ (const_string "mtjmpr")

75385

+ (const_string "*")

75386

+ (const_string "*")

75387

+ (if_then_else

75388

+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")

75389

+ (const_string "fpstore_ux")

75390

+ (if_then_else

75391

+ (match_test "update_address_mem (operands[0], VOIDmode)")

75392

+ (const_string "fpstore_u")

75393

+ (const_string "fpstore")))

75394

+ (if_then_else

75395

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

75396

+ (const_string "fpload_ux")

75397

+ (if_then_else

75398

+ (match_test "update_address_mem (operands[1], VOIDmode)")

75399

+ (const_string "fpload_u")

75400

+ (const_string "fpload")))])

75401

(set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])

75402

75403

;; Split a load of a large constant into the appropriate two-insn

75404

@@ -7822,7 +9020,7 @@

75405

cmp<wd>i %2,%0,0

75406

mr. %0,%1

75407

#"

75408

- [(set_attr "type" "cmp,compare,cmp")

75409

+ [(set_attr "type" "cmp,fast_compare,cmp")

75410

(set_attr "length" "4,4,8")])

75411

75412

(define_split

75413

@@ -7850,7 +9048,26 @@

75414

mf%1 %0

75415

mt%0 %1

75416

nop"

75417

- [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")])

75418

+ [(set_attr_alternative "type"

75419

+ [(const_string "*")

75420

+ (if_then_else

75421

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

75422

+ (const_string "load_ux")

75423

+ (if_then_else

75424

+ (match_test "update_address_mem (operands[1], VOIDmode)")

75425

+ (const_string "load_u")

75426

+ (const_string "load")))

75427

+ (if_then_else

75428

+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")

75429

+ (const_string "store_ux")

75430

+ (if_then_else

75431

+ (match_test "update_address_mem (operands[0], VOIDmode)")

75432

+ (const_string "store_u")

75433

+ (const_string "store")))

75434

+ (const_string "*")

75435

+ (const_string "mfjmpr")

75436

+ (const_string "mtjmpr")

75437

+ (const_string "*")])])

75438

75439

(define_expand "mov<mode>"

75440

[(set (match_operand:INT 0 "general_operand" "")

75441

@@ -7871,7 +9088,26 @@

75442

mf%1 %0

75443

mt%0 %1

75444

nop"

75445

- [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")])

75446

+ [(set_attr_alternative "type"

75447

+ [(const_string "*")

75448

+ (if_then_else

75449

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

75450

+ (const_string "load_ux")

75451

+ (if_then_else

75452

+ (match_test "update_address_mem (operands[1], VOIDmode)")

75453

+ (const_string "load_u")

75454

+ (const_string "load")))

75455

+ (if_then_else

75456

+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")

75457

+ (const_string "store_ux")

75458

+ (if_then_else

75459

+ (match_test "update_address_mem (operands[0], VOIDmode)")

75460

+ (const_string "store_u")

75461

+ (const_string "store")))

75462

+ (const_string "*")

75463

+ (const_string "mfjmpr")

75464

+ (const_string "mtjmpr")

75465

+ (const_string "*")])])

75466

75467

;; Here is how to move condition codes around. When we store CC data in

75468

;; an integer register or memory, we store just the high-order 4 bits.

75469

@@ -7899,7 +9135,7 @@

75470

mf%1 %0

75471

mt%0 %1

75472

lwz%U1%X1 %0,%1

75473

- stw%U0%U1 %1,%0"

75474

+ stw%U0%X0 %1,%0"

75475

[(set (attr "type")

75476

(cond [(eq_attr "alternative" "0,3")

75477

(const_string "cr_logical")

75478

@@ -7912,9 +9148,23 @@

75479

(eq_attr "alternative" "9")

75480

(const_string "mtjmpr")

75481

(eq_attr "alternative" "10")

75482

- (const_string "load")

75483

+ (if_then_else

75484

+ (match_test "update_indexed_address_mem (operands[1],

75485

+ VOIDmode)")

75486

+ (const_string "load_ux")

75487

+ (if_then_else

75488

+ (match_test "update_address_mem (operands[1], VOIDmode)")

75489

+ (const_string "load_u")

75490

+ (const_string "load")))

75491

(eq_attr "alternative" "11")

75492

- (const_string "store")

75493

+ (if_then_else

75494

+ (match_test "update_indexed_address_mem (operands[0],

75495

+ VOIDmode)")

75496

+ (const_string "store_ux")

75497

+ (if_then_else

75498

+ (match_test "update_address_mem (operands[0], VOIDmode)")

75499

+ (const_string "store_u")

75500

+ (const_string "store")))

75501

(match_test "TARGET_MFCRF")

75502

(const_string "mfcrf")

75503

]

75504

@@ -7926,15 +9176,17 @@

75505

;; can produce floating-point values in fixed-point registers. Unless the

75506

;; value is a simple constant or already in memory, we deal with this by

75507

;; allocating memory and copying the value explicitly via that memory location.

75508

-(define_expand "movsf"

75509

- [(set (match_operand:SF 0 "nonimmediate_operand" "")

75510

- (match_operand:SF 1 "any_operand" ""))]

75511

- ""

75512

- "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")

75513

75514

+;; Move 32-bit binary/decimal floating point

75515

+(define_expand "mov<mode>"

75516

+ [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "")

75517

+ (match_operand:FMOVE32 1 "any_operand" ""))]

75518

+ "<fmove_ok>"

75519

+ "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")

75520

+

75521

(define_split

75522

- [(set (match_operand:SF 0 "gpc_reg_operand" "")

75523

- (match_operand:SF 1 "const_double_operand" ""))]

75524

+ [(set (match_operand:FMOVE32 0 "gpc_reg_operand" "")

75525

+ (match_operand:FMOVE32 1 "const_double_operand" ""))]

75526

"reload_completed

75527

&& ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)

75528

|| (GET_CODE (operands[0]) == SUBREG

75529

@@ -7947,10 +9199,10 @@

75530

REAL_VALUE_TYPE rv;

75531

75532

REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);

75533

- REAL_VALUE_TO_TARGET_SINGLE (rv, l);

75534

+ <real_value_to_target> (rv, l);

75535

75536

if (! TARGET_POWERPC64)

75537

- operands[2] = operand_subword (operands[0], 0, 0, SFmode);

75538

+ operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);

75539

else

75540

operands[2] = gen_lowpart (SImode, operands[0]);

75541

75542

@@ -7957,11 +9209,11 @@

75543

operands[3] = gen_int_mode (l, SImode);

75544

}")

75545

75546

-(define_insn "*movsf_hardfloat"

75547

- [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,!r,*h,!r,!r")

75548

- (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,h,0,G,Fn"))]

75549

- "(gpc_reg_operand (operands[0], SFmode)

75550

- || gpc_reg_operand (operands[1], SFmode))

75551

+(define_insn "mov<mode>_hardfloat"

75552

+ [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=!r,!r,m,f,wa,wa,<f32_lr>,<f32_sm>,wu,Z,?<f32_dm>,?r,*c*l,!r,*h,!r,!r")

75553

+ (match_operand:FMOVE32 1 "input_operand" "r,m,r,f,wa,j,<f32_lm>,<f32_sr>,Z,wu,r,<f32_dm>,r,h,0,G,Fn"))]

75554

+ "(gpc_reg_operand (operands[0], <MODE>mode)

75555

+ || gpc_reg_operand (operands[1], <MODE>mode))

75556

&& (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"

75557

"@

75558

mr %0,%1

75559

@@ -7968,21 +9220,68 @@

75560

lwz%U1%X1 %0,%1

75561

stw%U0%X0 %1,%0

75562

fmr %0,%1

75563

- lfs%U1%X1 %0,%1

75564

- stfs%U0%X0 %1,%0

75565

+ xxlor %x0,%x1,%x1

75566

+ xxlxor %x0,%x0,%x0

75567

+ <f32_li>

75568

+ <f32_si>

75569

+ <f32_lv>

75570

+ <f32_sv>

75571

+ mtvsrwz %x0,%1

75572

+ mfvsrwz %0,%x1

75573

mt%0 %1

75574

mf%1 %0

75575

nop

75576

#

75577

#"

75578

- [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*")

75579

- (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8")])

75580

+ [(set_attr_alternative "type"

75581

+ [(const_string "*")

75582

+ (if_then_else

75583

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

75584

+ (const_string "load_ux")

75585

+ (if_then_else

75586

+ (match_test "update_address_mem (operands[1], VOIDmode)")

75587

+ (const_string "load_u")

75588

+ (const_string "load")))

75589

+ (if_then_else

75590

+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")

75591

+ (const_string "store_ux")

75592

+ (if_then_else

75593

+ (match_test "update_address_mem (operands[0], VOIDmode)")

75594

+ (const_string "store_u")

75595

+ (const_string "store")))

75596

+ (const_string "fp")

75597

+ (const_string "vecsimple")

75598

+ (const_string "vecsimple")

75599

+ (if_then_else

75600

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

75601

+ (const_string "fpload_ux")

75602

+ (if_then_else

75603

+ (match_test "update_address_mem (operands[1], VOIDmode)")

75604

+ (const_string "fpload_u")

75605

+ (const_string "fpload")))

75606

+ (if_then_else

75607

+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")

75608

+ (const_string "fpstore_ux")

75609

+ (if_then_else

75610

+ (match_test "update_address_mem (operands[0], VOIDmode)")

75611

+ (const_string "fpstore_u")

75612

+ (const_string "fpstore")))

75613

+ (const_string "fpload")

75614

+ (const_string "fpstore")

75615

+ (const_string "mftgpr")

75616

+ (const_string "mffgpr")

75617

+ (const_string "mtjmpr")

75618

+ (const_string "mfjmpr")

75619

+ (const_string "*")

75620

+ (const_string "*")

75621

+ (const_string "*")])

75622

+ (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8")])

75623

75624

-(define_insn "*movsf_softfloat"

75625

- [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,*h")

75626

- (match_operand:SF 1 "input_operand" "r,r,h,m,r,I,L,G,Fn,0"))]

75627

- "(gpc_reg_operand (operands[0], SFmode)

75628

- || gpc_reg_operand (operands[1], SFmode))

75629

+(define_insn "*mov<mode>_softfloat"

75630

+ [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,*h")

75631

+ (match_operand:FMOVE32 1 "input_operand" "r,r,h,m,r,I,L,G,Fn,0"))]

75632

+ "(gpc_reg_operand (operands[0], <MODE>mode)

75633

+ || gpc_reg_operand (operands[1], <MODE>mode))

75634

&& (TARGET_SOFT_FLOAT || !TARGET_FPRS)"

75635

"@

75636

mr %0,%1

75637

@@ -7995,19 +9294,42 @@

75638

#

75639

#

75640

nop"

75641

- [(set_attr "type" "*,mtjmpr,mfjmpr,load,store,*,*,*,*,*")

75642

+ [(set_attr_alternative "type"

75643

+ [(const_string "*")

75644

+ (const_string "mtjmpr")

75645

+ (const_string "mfjmpr")

75646

+ (if_then_else

75647

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

75648

+ (const_string "load_ux")

75649

+ (if_then_else

75650

+ (match_test "update_address_mem (operands[1], VOIDmode)")

75651

+ (const_string "load_u")

75652

+ (const_string "load")))

75653

+ (if_then_else

75654

+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")

75655

+ (const_string "store_ux")

75656

+ (if_then_else

75657

+ (match_test "update_address_mem (operands[0], VOIDmode)")

75658

+ (const_string "store_u")

75659

+ (const_string "store")))

75660

+ (const_string "*")

75661

+ (const_string "*")

75662

+ (const_string "*")

75663

+ (const_string "*")

75664

+ (const_string "*")])

75665

(set_attr "length" "4,4,4,4,4,4,4,4,8,4")])

75666

75667

75668

-(define_expand "movdf"

75669

- [(set (match_operand:DF 0 "nonimmediate_operand" "")

75670

- (match_operand:DF 1 "any_operand" ""))]

75671

+;; Move 64-bit binary/decimal floating point

75672

+(define_expand "mov<mode>"

75673

+ [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "")

75674

+ (match_operand:FMOVE64 1 "any_operand" ""))]

75675

""

75676

- "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")

75677

+ "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")

75678

75679

(define_split

75680

- [(set (match_operand:DF 0 "gpc_reg_operand" "")

75681

- (match_operand:DF 1 "const_int_operand" ""))]

75682

+ [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")

75683

+ (match_operand:FMOVE64 1 "const_int_operand" ""))]

75684

"! TARGET_POWERPC64 && reload_completed

75685

&& ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)

75686

|| (GET_CODE (operands[0]) == SUBREG

75687

@@ -8020,8 +9342,8 @@

75688

int endian = (WORDS_BIG_ENDIAN == 0);

75689

HOST_WIDE_INT value = INTVAL (operands[1]);

75690

75691

- operands[2] = operand_subword (operands[0], endian, 0, DFmode);

75692

- operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);

75693

+ operands[2] = operand_subword (operands[0], endian, 0, <MODE>mode);

75694

+ operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);

75695

#if HOST_BITS_PER_WIDE_INT == 32

75696

operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;

75697

#else

75698

@@ -8031,8 +9353,8 @@

75699

}")

75700

75701

(define_split

75702

- [(set (match_operand:DF 0 "gpc_reg_operand" "")

75703

- (match_operand:DF 1 "const_double_operand" ""))]

75704

+ [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")

75705

+ (match_operand:FMOVE64 1 "const_double_operand" ""))]

75706

"! TARGET_POWERPC64 && reload_completed

75707

&& ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)

75708

|| (GET_CODE (operands[0]) == SUBREG

75709

@@ -8047,17 +9369,17 @@

75710

REAL_VALUE_TYPE rv;

75711

75712

REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);

75713

- REAL_VALUE_TO_TARGET_DOUBLE (rv, l);

75714

+ <real_value_to_target> (rv, l);

75715

75716

- operands[2] = operand_subword (operands[0], endian, 0, DFmode);

75717

- operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);

75718

+ operands[2] = operand_subword (operands[0], endian, 0, <MODE>mode);

75719

+ operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);

75720

operands[4] = gen_int_mode (l[endian], SImode);

75721

operands[5] = gen_int_mode (l[1 - endian], SImode);

75722

}")

75723

75724

(define_split

75725

- [(set (match_operand:DF 0 "gpc_reg_operand" "")

75726

- (match_operand:DF 1 "const_double_operand" ""))]

75727

+ [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")

75728

+ (match_operand:FMOVE64 1 "const_double_operand" ""))]

75729

"TARGET_POWERPC64 && reload_completed

75730

&& ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)

75731

|| (GET_CODE (operands[0]) == SUBREG

75732

@@ -8074,7 +9396,7 @@

75733

#endif

75734

75735

REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);

75736

- REAL_VALUE_TO_TARGET_DOUBLE (rv, l);

75737

+ <real_value_to_target> (rv, l);

75738

75739

operands[2] = gen_lowpart (DImode, operands[0]);

75740

/* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */

75741

@@ -8099,22 +9421,19 @@

75742

;; since the D-form version of the memory instructions does not need a GPR for

75743

;; reloading.

75744

75745

-(define_insn "*movdf_hardfloat32"

75746

- [(set (match_operand:DF 0 "nonimmediate_operand" "=m,d,d,ws,?wa,Z,?Z,ws,?wa,wa,Y,r,!r,!r,!r,!r")

75747

- (match_operand:DF 1 "input_operand" "d,m,d,Z,Z,ws,wa,ws,wa,j,r,Y,r,G,H,F"))]

75748

+(define_insn "*mov<mode>_hardfloat32"

75749

+ [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,wv,Z,wa,wa,Y,r,!r,!r,!r,!r")

75750

+ (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,wv,wa,j,r,Y,r,G,H,F"))]

75751

"! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT

75752

- && (gpc_reg_operand (operands[0], DFmode)

75753

- || gpc_reg_operand (operands[1], DFmode))"

75754

+ && (gpc_reg_operand (operands[0], <MODE>mode)

75755

+ || gpc_reg_operand (operands[1], <MODE>mode))"

75756

"@

75757

stfd%U0%X0 %1,%0

75758

lfd%U1%X1 %0,%1

75759

fmr %0,%1

75760

lxsd%U1x %x0,%y1

75761

- lxsd%U1x %x0,%y1

75762

stxsd%U0x %x1,%y0

75763

- stxsd%U0x %x1,%y0

75764

xxlor %x0,%x1,%x1

75765

- xxlor %x0,%x1,%x1

75766

xxlxor %x0,%x0,%x0

75767

#

75768

#

75769

@@ -8122,115 +9441,141 @@

75770

#

75771

#

75772

#"

75773

- [(set_attr "type" "fpstore,fpload,fp,fpload,fpload,fpstore,fpstore,vecsimple,vecsimple,vecsimple,store,load,two,fp,fp,*")

75774

- (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,8,8,8,12,16")])

75775

+ [(set_attr_alternative "type"

75776

+ [(if_then_else

75777

+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")

75778

+ (const_string "fpstore_ux")

75779

+ (if_then_else

75780

+ (match_test "update_address_mem (operands[0], VOIDmode)")

75781

+ (const_string "fpstore_u")

75782

+ (const_string "fpstore")))

75783

+ (if_then_else

75784

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

75785

+ (const_string "fpload_ux")

75786

+ (if_then_else

75787

+ (match_test "update_address_mem (operands[1], VOIDmode)")

75788

+ (const_string "fpload_u")

75789

+ (const_string "fpload")))

75790

+ (const_string "fp")

75791

+ (if_then_else

75792

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

75793

+ (const_string "fpload_ux")

75794

+ (const_string "fpload"))

75795

+ (if_then_else

75796

+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")

75797

+ (const_string "fpstore_ux")

75798

+ (const_string "fpstore"))

75799

+ (const_string "vecsimple")

75800

+ (const_string "vecsimple")

75801

+ (const_string "store")

75802

+ (const_string "load")

75803

+ (const_string "two")

75804

+ (const_string "fp")

75805

+ (const_string "fp")

75806

+ (const_string "*")])

75807

+ (set_attr "length" "4,4,4,4,4,4,4,8,8,8,8,12,16")])

75808

75809

-(define_insn "*movdf_softfloat32"

75810

- [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,r,r,r,r")

75811

- (match_operand:DF 1 "input_operand" "r,Y,r,G,H,F"))]

75812

+(define_insn "*mov<mode>_softfloat32"

75813

+ [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,r,r,r")

75814

+ (match_operand:FMOVE64 1 "input_operand" "r,Y,r,G,H,F"))]

75815

"! TARGET_POWERPC64

75816

&& ((TARGET_FPRS && TARGET_SINGLE_FLOAT)

75817

- || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)

75818

- && (gpc_reg_operand (operands[0], DFmode)

75819

- || gpc_reg_operand (operands[1], DFmode))"

75820

+ || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE

75821

+ || (<MODE>mode == DDmode && TARGET_E500_DOUBLE))

75822

+ && (gpc_reg_operand (operands[0], <MODE>mode)

75823

+ || gpc_reg_operand (operands[1], <MODE>mode))"

75824

"#"

75825

[(set_attr "type" "store,load,two,*,*,*")

75826

(set_attr "length" "8,8,8,8,12,16")])

75827

75828

-;; Reload patterns to support gpr load/store with misaligned mem.

75829

-;; and multiple gpr load/store at offset >= 0xfffc

75830

-(define_expand "reload_<mode>_store"

75831

- [(parallel [(match_operand 0 "memory_operand" "=m")

75832

- (match_operand 1 "gpc_reg_operand" "r")

75833

- (match_operand:GPR 2 "register_operand" "=&b")])]

75834

- ""

75835

-{

75836

- rs6000_secondary_reload_gpr (operands[1], operands[0], operands[2], true);

75837

- DONE;

75838

-})

75839

-

75840

-(define_expand "reload_<mode>_load"

75841

- [(parallel [(match_operand 0 "gpc_reg_operand" "=r")

75842

- (match_operand 1 "memory_operand" "m")

75843

- (match_operand:GPR 2 "register_operand" "=b")])]

75844

- ""

75845

-{

75846

- rs6000_secondary_reload_gpr (operands[0], operands[1], operands[2], false);

75847

- DONE;

75848

-})

75849

-

75850

; ld/std require word-aligned displacements -> 'Y' constraint.

75851

; List Y->r and r->Y before r->r for reload.

75852

-(define_insn "*movdf_hardfloat64_mfpgpr"

75853

- [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,m,d,d,wa,*c*l,!r,*h,!r,!r,!r,r,d")

75854

- (match_operand:DF 1 "input_operand" "r,Y,r,ws,?wa,Z,Z,ws,wa,d,m,d,j,r,h,0,G,H,F,d,r"))]

75855

- "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS

75856

- && TARGET_DOUBLE_FLOAT

75857

- && (gpc_reg_operand (operands[0], DFmode)

75858

- || gpc_reg_operand (operands[1], DFmode))"

75859

+(define_insn "*mov<mode>_hardfloat64"

75860

+ [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,wv,Z,wa,wa,Y,r,!r,*c*l,!r,*h,!r,!r,!r,r,wg,r,wm")

75861

+ (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,wv,wa,j,r,Y,r,r,h,0,G,H,F,wg,r,wm,r"))]

75862

+ "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT

75863

+ && (gpc_reg_operand (operands[0], <MODE>mode)

75864

+ || gpc_reg_operand (operands[1], <MODE>mode))"

75865

"@

75866

- std%U0%X0 %1,%0

75867

- ld%U1%X1 %0,%1

75868

- mr %0,%1

75869

- xxlor %x0,%x1,%x1

75870

- xxlor %x0,%x1,%x1

75871

- lxsd%U1x %x0,%y1

75872

- lxsd%U1x %x0,%y1

75873

- stxsd%U0x %x1,%y0

75874

- stxsd%U0x %x1,%y0

75875

stfd%U0%X0 %1,%0

75876

lfd%U1%X1 %0,%1

75877

fmr %0,%1

75878

+ lxsd%U1x %x0,%y1

75879

+ stxsd%U0x %x1,%y0

75880

+ xxlor %x0,%x1,%x1

75881

xxlxor %x0,%x0,%x0

75882

- mt%0 %1

75883

- mf%1 %0

75884

- nop

75885

- #

75886

- #

75887

- #

75888

- mftgpr %0,%1

75889

- mffgpr %0,%1"

75890

- [(set_attr "type" "store,load,*,fp,fp,fpload,fpload,fpstore,fpstore,fpstore,fpload,fp,vecsimple,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")

75891

- (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4")])

75892

-

75893

-; ld/std require word-aligned displacements -> 'Y' constraint.

75894

-; List Y->r and r->Y before r->r for reload.

75895

-(define_insn "*movdf_hardfloat64"

75896

- [(set (match_operand:DF 0 "nonimmediate_operand" "=m,d,d,Y,r,!r,ws,?wa,Z,?Z,ws,?wa,wa,*c*l,!r,*h,!r,!r,!r")

75897

- (match_operand:DF 1 "input_operand" "d,m,d,r,Y,r,Z,Z,ws,wa,ws,wa,j,r,h,0,G,H,F"))]

75898

- "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS

75899

- && TARGET_DOUBLE_FLOAT

75900

- && (gpc_reg_operand (operands[0], DFmode)

75901

- || gpc_reg_operand (operands[1], DFmode))"

75902

- "@

75903

- stfd%U0%X0 %1,%0

75904

- lfd%U1%X1 %0,%1

75905

- fmr %0,%1

75906

std%U0%X0 %1,%0

75907

ld%U1%X1 %0,%1

75908

mr %0,%1

75909

- lxsd%U1x %x0,%y1

75910

- lxsd%U1x %x0,%y1

75911

- stxsd%U0x %x1,%y0

75912

- stxsd%U0x %x1,%y0

75913

- xxlor %x0,%x1,%x1

75914

- xxlor %x0,%x1,%x1

75915

- xxlxor %x0,%x0,%x0

75916

mt%0 %1

75917

mf%1 %0

75918

nop

75919

#

75920

#

75921

- #"

75922

- [(set_attr "type" "fpstore,fpload,fp,store,load,*,fpload,fpload,fpstore,fpstore,vecsimple,vecsimple,vecsimple,mtjmpr,mfjmpr,*,*,*,*")

75923

- (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16")])

75924

+ #

75925

+ mftgpr %0,%1

75926

+ mffgpr %0,%1

75927

+ mfvsrd %0,%x1

75928

+ mtvsrd %x0,%1"

75929

+ [(set_attr_alternative "type"

75930

+ [(if_then_else

75931

+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")

75932

+ (const_string "fpstore_ux")

75933

+ (if_then_else

75934

+ (match_test "update_address_mem (operands[0], VOIDmode)")

75935

+ (const_string "fpstore_u")

75936

+ (const_string "fpstore")))

75937

+ (if_then_else

75938

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

75939

+ (const_string "fpload_ux")

75940

+ (if_then_else

75941

+ (match_test "update_address_mem (operands[1], VOIDmode)")

75942

+ (const_string "fpload_u")

75943

+ (const_string "fpload")))

75944

+ (const_string "fp")

75945

+ (if_then_else

75946

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

75947

+ (const_string "fpload_ux")

75948

+ (const_string "fpload"))

75949

+ (if_then_else

75950

+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")

75951

+ (const_string "fpstore_ux")

75952

+ (const_string "fpstore"))

75953

+ (const_string "vecsimple")

75954

+ (const_string "vecsimple")

75955

+ (if_then_else

75956

+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")

75957

+ (const_string "store_ux")

75958

+ (if_then_else

75959

+ (match_test "update_address_mem (operands[0], VOIDmode)")

75960

+ (const_string "store_u")

75961

+ (const_string "store")))

75962

+ (if_then_else

75963

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

75964

+ (const_string "load_ux")

75965

+ (if_then_else

75966

+ (match_test "update_address_mem (operands[1], VOIDmode)")

75967

+ (const_string "load_u")

75968

+ (const_string "load")))

75969

+ (const_string "*")

75970

+ (const_string "mtjmpr")

75971

+ (const_string "mfjmpr")

75972

+ (const_string "*")

75973

+ (const_string "*")

75974

+ (const_string "*")

75975

+ (const_string "*")

75976

+ (const_string "mftgpr")

75977

+ (const_string "mffgpr")

75978

+ (const_string "mftgpr")

75979

+ (const_string "mffgpr")])

75980

+ (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4,4,4")])

75981

75982

-(define_insn "*movdf_softfloat64"

75983

- [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,r,cl,r,r,r,r,*h")

75984

- (match_operand:DF 1 "input_operand" "r,Y,r,r,h,G,H,F,0"))]

75985

+(define_insn "*mov<mode>_softfloat64"

75986

+ [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,cl,r,r,r,r,*h")

75987

+ (match_operand:FMOVE64 1 "input_operand" "r,Y,r,r,h,G,H,F,0"))]

75988

"TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)

75989

- && (gpc_reg_operand (operands[0], DFmode)

75990

- || gpc_reg_operand (operands[1], DFmode))"

75991

+ && (gpc_reg_operand (operands[0], <MODE>mode)

75992

+ || gpc_reg_operand (operands[1], <MODE>mode))"

75993

"@

75994

std%U0%X0 %1,%0

75995

ld%U1%X1 %0,%1

75996

@@ -8241,38 +9586,87 @@

75997

#

75998

#

75999

nop"

76000

- [(set_attr "type" "store,load,*,mtjmpr,mfjmpr,*,*,*,*")

76001

+ [(set_attr_alternative "type"

76002

+ [(if_then_else

76003

+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")

76004

+ (const_string "store_ux")

76005

+ (if_then_else

76006

+ (match_test "update_address_mem (operands[0], VOIDmode)")

76007

+ (const_string "store_u")

76008

+ (const_string "store")))

76009

+ (if_then_else

76010

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

76011

+ (const_string "load_ux")

76012

+ (if_then_else

76013

+ (match_test "update_address_mem (operands[1], VOIDmode)")

76014

+ (const_string "load_u")

76015

+ (const_string "load")))

76016

+ (const_string "*")

76017

+ (const_string "mtjmpr")

76018

+ (const_string "mfjmpr")

76019

+ (const_string "*")

76020

+ (const_string "*")

76021

+ (const_string "*")

76022

+ (const_string "*")])

76023

(set_attr "length" "4,4,4,4,4,8,12,16,4")])

76024

76025

-(define_expand "movtf"

76026

- [(set (match_operand:TF 0 "general_operand" "")

76027

- (match_operand:TF 1 "any_operand" ""))]

76028

- "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"

76029

- "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")

76030

+(define_expand "mov<mode>"

76031

+ [(set (match_operand:FMOVE128 0 "general_operand" "")

76032

+ (match_operand:FMOVE128 1 "any_operand" ""))]

76033

+ ""

76034

+ "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")

76035

76036

;; It's important to list Y->r and r->Y before r->r because otherwise

76037

;; reload, given m->r, will try to pick r->r and reload it, which

76038

;; doesn't make progress.

76039

-(define_insn_and_split "*movtf_internal"

76040

- [(set (match_operand:TF 0 "nonimmediate_operand" "=m,d,d,Y,r,r")

76041

- (match_operand:TF 1 "input_operand" "d,m,d,r,YGHF,r"))]

76042

- "!TARGET_IEEEQUAD

76043

- && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128

76044

- && (gpc_reg_operand (operands[0], TFmode)

76045

- || gpc_reg_operand (operands[1], TFmode))"

76046

+

76047

+;; We can't split little endian direct moves of TDmode, because the words are

76048

+;; not swapped like they are for TImode or TFmode. Subregs therefore are

76049

+;; problematical. Don't allow direct move for this case.

76050

+

76051

+(define_insn_and_split "*mov<mode>_64bit_dm"

76052

+ [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,Y,r,r,r,wm")

76053

+ (match_operand:FMOVE128 1 "input_operand" "d,m,d,r,YGHF,r,wm,r"))]

76054

+ "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64

76055

+ && (<MODE>mode != TDmode || WORDS_BIG_ENDIAN)

76056

+ && (gpc_reg_operand (operands[0], <MODE>mode)

76057

+ || gpc_reg_operand (operands[1], <MODE>mode))"

76058

"#"

76059

"&& reload_completed"

76060

[(pc)]

76061

{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }

76062

+ [(set_attr "length" "8,8,8,12,12,8,8,8")])

76063

+

76064

+(define_insn_and_split "*movtd_64bit_nodm"

76065

+ [(set (match_operand:TD 0 "nonimmediate_operand" "=m,d,d,Y,r,r")

76066

+ (match_operand:TD 1 "input_operand" "d,m,d,r,YGHF,r"))]

76067

+ "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64 && !WORDS_BIG_ENDIAN

76068

+ && (gpc_reg_operand (operands[0], TDmode)

76069

+ || gpc_reg_operand (operands[1], TDmode))"

76070

+ "#"

76071

+ "&& reload_completed"

76072

+ [(pc)]

76073

+{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }

76074

+ [(set_attr "length" "8,8,8,12,12,8")])

76075

+

76076

+(define_insn_and_split "*mov<mode>_32bit"

76077

+ [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,Y,r,r")

76078

+ (match_operand:FMOVE128 1 "input_operand" "d,m,d,r,YGHF,r"))]

76079

+ "TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_POWERPC64

76080

+ && (gpc_reg_operand (operands[0], <MODE>mode)

76081

+ || gpc_reg_operand (operands[1], <MODE>mode))"

76082

+ "#"

76083

+ "&& reload_completed"

76084

+ [(pc)]

76085

+{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }

76086

[(set_attr "length" "8,8,8,20,20,16")])

76087

76088

-(define_insn_and_split "*movtf_softfloat"

76089

- [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=Y,r,r")

76090

- (match_operand:TF 1 "input_operand" "r,YGHF,r"))]

76091

- "!TARGET_IEEEQUAD

76092

- && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128

76093

- && (gpc_reg_operand (operands[0], TFmode)

76094

- || gpc_reg_operand (operands[1], TFmode))"

76095

+(define_insn_and_split "*mov<mode>_softfloat"

76096

+ [(set (match_operand:FMOVE128 0 "rs6000_nonimmediate_operand" "=Y,r,r")

76097

+ (match_operand:FMOVE128 1 "input_operand" "r,YGHF,r"))]

76098

+ "(TARGET_SOFT_FLOAT || !TARGET_FPRS)

76099

+ && (gpc_reg_operand (operands[0], <MODE>mode)

76100

+ || gpc_reg_operand (operands[1], <MODE>mode))"

76101

"#"

76102

"&& reload_completed"

76103

[(pc)]

76104

@@ -8557,6 +9951,252 @@

76105

operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);

76106

}")

76107

76108

+;; Reload helper functions used by rs6000_secondary_reload. The patterns all

76109

+;; must have 3 arguments, and scratch register constraint must be a single

76110

+;; constraint.

76111

+

76112

+;; Reload patterns to support gpr load/store with misaligned mem.

76113

+;; and multiple gpr load/store at offset >= 0xfffc

76114

+(define_expand "reload_<mode>_store"

76115

+ [(parallel [(match_operand 0 "memory_operand" "=m")

76116

+ (match_operand 1 "gpc_reg_operand" "r")

76117

+ (match_operand:GPR 2 "register_operand" "=&b")])]

76118

+ ""

76119

+{

76120

+ rs6000_secondary_reload_gpr (operands[1], operands[0], operands[2], true);

76121

+ DONE;

76122

+})

76123

+

76124

+(define_expand "reload_<mode>_load"

76125

+ [(parallel [(match_operand 0 "gpc_reg_operand" "=r")

76126

+ (match_operand 1 "memory_operand" "m")

76127

+ (match_operand:GPR 2 "register_operand" "=b")])]

76128

+ ""

76129

+{

76130

+ rs6000_secondary_reload_gpr (operands[0], operands[1], operands[2], false);

76131

+ DONE;

76132

+})

76133

+

76134

+

76135

+;; Power8 merge instructions to allow direct move to/from floating point

76136

+;; registers in 32-bit mode. We use TF mode to get two registers to move the

76137

+;; individual 32-bit parts across. Subreg doesn't work too well on the TF

76138

+;; value, since it is allocated in reload and not all of the flow information

76139

+;; is setup for it. We have two patterns to do the two moves between gprs and

76140

+;; fprs. There isn't a dependancy between the two, but we could potentially

76141

+;; schedule other instructions between the two instructions. TFmode is

76142

+;; currently limited to traditional FPR registers. If/when this is changed, we

76143

+;; will need to revist %L to make sure it works with VSX registers, or add an

76144

+;; %x version of %L.

76145

+

76146

+(define_insn "p8_fmrgow_<mode>"

76147

+ [(set (match_operand:FMOVE64X 0 "register_operand" "=d")

76148

+ (unspec:FMOVE64X [(match_operand:TF 1 "register_operand" "d")]

76149

+ UNSPEC_P8V_FMRGOW))]

76150

+ "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"

76151

+ "fmrgow %0,%1,%L1"

76152

+ [(set_attr "type" "vecperm")])

76153

+

76154

+(define_insn "p8_mtvsrwz_1"

76155

+ [(set (match_operand:TF 0 "register_operand" "=d")

76156

+ (unspec:TF [(match_operand:SI 1 "register_operand" "r")]

76157

+ UNSPEC_P8V_MTVSRWZ))]

76158

+ "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"

76159

+ "mtvsrwz %x0,%1"

76160

+ [(set_attr "type" "mftgpr")])

76161

+

76162

+(define_insn "p8_mtvsrwz_2"

76163

+ [(set (match_operand:TF 0 "register_operand" "+d")

76164

+ (unspec:TF [(match_dup 0)

76165

+ (match_operand:SI 1 "register_operand" "r")]

76166

+ UNSPEC_P8V_MTVSRWZ))]

76167

+ "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"

76168

+ "mtvsrwz %L0,%1"

76169

+ [(set_attr "type" "mftgpr")])

76170

+

76171

+(define_insn_and_split "reload_fpr_from_gpr<mode>"

76172

+ [(set (match_operand:FMOVE64X 0 "register_operand" "=ws")

76173

+ (unspec:FMOVE64X [(match_operand:FMOVE64X 1 "register_operand" "r")]

76174

+ UNSPEC_P8V_RELOAD_FROM_GPR))

76175

+ (clobber (match_operand:TF 2 "register_operand" "=d"))]

76176

+ "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"

76177

+ "#"

76178

+ "&& reload_completed"

76179

+ [(const_int 0)]

76180

+{

76181

+ rtx dest = operands[0];

76182

+ rtx src = operands[1];

76183

+ rtx tmp = operands[2];

76184

+ rtx gpr_hi_reg = gen_highpart (SImode, src);

76185

+ rtx gpr_lo_reg = gen_lowpart (SImode, src);

76186

+

76187

+ emit_insn (gen_p8_mtvsrwz_1 (tmp, gpr_hi_reg));

76188

+ emit_insn (gen_p8_mtvsrwz_2 (tmp, gpr_lo_reg));

76189

+ emit_insn (gen_p8_fmrgow_<mode> (dest, tmp));

76190

+ DONE;

76191

+}

76192

+ [(set_attr "length" "12")

76193

+ (set_attr "type" "three")])

76194

+

76195

+;; Move 128 bit values from GPRs to VSX registers in 64-bit mode

76196

+(define_insn "p8_mtvsrd_1"

76197

+ [(set (match_operand:TF 0 "register_operand" "=ws")

76198

+ (unspec:TF [(match_operand:DI 1 "register_operand" "r")]

76199

+ UNSPEC_P8V_MTVSRD))]

76200

+ "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"

76201

+ "mtvsrd %0,%1"

76202

+ [(set_attr "type" "mftgpr")])

76203

+

76204

+(define_insn "p8_mtvsrd_2"

76205

+ [(set (match_operand:TF 0 "register_operand" "+ws")

76206

+ (unspec:TF [(match_dup 0)

76207

+ (match_operand:DI 1 "register_operand" "r")]

76208

+ UNSPEC_P8V_MTVSRD))]

76209

+ "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"

76210

+ "mtvsrd %L0,%1"

76211

+ [(set_attr "type" "mftgpr")])

76212

+

76213

+(define_insn "p8_xxpermdi_<mode>"

76214

+ [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=wa")

76215

+ (unspec:FMOVE128_GPR [(match_operand:TF 1 "register_operand" "ws")]

76216

+ UNSPEC_P8V_XXPERMDI))]

76217

+ "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"

76218

+ "xxpermdi %x0,%1,%L1,0"

76219

+ [(set_attr "type" "vecperm")])

76220

+

76221

+(define_insn_and_split "reload_vsx_from_gpr<mode>"

76222

+ [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=wa")

76223

+ (unspec:FMOVE128_GPR

76224

+ [(match_operand:FMOVE128_GPR 1 "register_operand" "r")]

76225

+ UNSPEC_P8V_RELOAD_FROM_GPR))

76226

+ (clobber (match_operand:TF 2 "register_operand" "=ws"))]

76227

+ "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"

76228

+ "#"

76229

+ "&& reload_completed"

76230

+ [(const_int 0)]

76231

+{

76232

+ rtx dest = operands[0];

76233

+ rtx src = operands[1];

76234

+ rtx tmp = operands[2];

76235

+ rtx gpr_hi_reg = gen_highpart (DImode, src);

76236

+ rtx gpr_lo_reg = gen_lowpart (DImode, src);

76237

+

76238

+ emit_insn (gen_p8_mtvsrd_1 (tmp, gpr_hi_reg));

76239

+ emit_insn (gen_p8_mtvsrd_2 (tmp, gpr_lo_reg));

76240

+ emit_insn (gen_p8_xxpermdi_<mode> (dest, tmp));

76241

+}

76242

+ [(set_attr "length" "12")

76243

+ (set_attr "type" "three")])

76244

+

76245

+(define_split

76246

+ [(set (match_operand:FMOVE128_GPR 0 "nonimmediate_operand" "")

76247

+ (match_operand:FMOVE128_GPR 1 "input_operand" ""))]

76248

+ "reload_completed

76249

+ && (int_reg_operand (operands[0], <MODE>mode)

76250

+ || int_reg_operand (operands[1], <MODE>mode))"

76251

+ [(pc)]

76252

+{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })

76253

+

76254

+;; Move SFmode to a VSX from a GPR register. Because scalar floating point

76255

+;; type is stored internally as double precision in the VSX registers, we have

76256

+;; to convert it from the vector format.

76257

+

76258

+(define_insn_and_split "reload_vsx_from_gprsf"

76259

+ [(set (match_operand:SF 0 "register_operand" "=wa")

76260

+ (unspec:SF [(match_operand:SF 1 "register_operand" "r")]

76261

+ UNSPEC_P8V_RELOAD_FROM_GPR))

76262

+ (clobber (match_operand:DI 2 "register_operand" "=r"))]

76263

+ "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"

76264

+ "#"

76265

+ "&& reload_completed"

76266

+ [(const_int 0)]

76267

+{

76268

+ rtx op0 = operands[0];

76269

+ rtx op1 = operands[1];

76270

+ rtx op2 = operands[2];

76271

+ rtx op0_di = simplify_gen_subreg (DImode, op0, SFmode, 0);

76272

+ rtx op1_di = simplify_gen_subreg (DImode, op1, SFmode, 0);

76273

+

76274

+ /* Move SF value to upper 32-bits for xscvspdpn. */

76275

+ emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (32)));

76276

+ emit_move_insn (op0_di, op2);

76277

+ emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0));

76278

+ DONE;

76279

+}

76280

+ [(set_attr "length" "8")

76281

+ (set_attr "type" "two")])

76282

+

76283

+;; Move 128 bit values from VSX registers to GPRs in 64-bit mode by doing a

76284

+;; normal 64-bit move, followed by an xxpermdi to get the bottom 64-bit value,

76285

+;; and then doing a move of that.

76286

+(define_insn "p8_mfvsrd_3_<mode>"

76287

+ [(set (match_operand:DF 0 "register_operand" "=r")

76288

+ (unspec:DF [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]

76289

+ UNSPEC_P8V_RELOAD_FROM_VSX))]

76290

+ "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"

76291

+ "mfvsrd %0,%x1"

76292

+ [(set_attr "type" "mftgpr")])

76293

+

76294

+(define_insn_and_split "reload_gpr_from_vsx<mode>"

76295

+ [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=r")

76296

+ (unspec:FMOVE128_GPR

76297

+ [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]

76298

+ UNSPEC_P8V_RELOAD_FROM_VSX))

76299

+ (clobber (match_operand:FMOVE128_GPR 2 "register_operand" "=wa"))]

76300

+ "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"

76301

+ "#"

76302

+ "&& reload_completed"

76303

+ [(const_int 0)]

76304

+{

76305

+ rtx dest = operands[0];

76306

+ rtx src = operands[1];

76307

+ rtx tmp = operands[2];

76308

+ rtx gpr_hi_reg = gen_highpart (DFmode, dest);

76309

+ rtx gpr_lo_reg = gen_lowpart (DFmode, dest);

76310

+

76311

+ emit_insn (gen_p8_mfvsrd_3_<mode> (gpr_hi_reg, src));

76312

+ emit_insn (gen_vsx_xxpermdi_<mode> (tmp, src, src, GEN_INT (3)));

76313

+ emit_insn (gen_p8_mfvsrd_3_<mode> (gpr_lo_reg, tmp));

76314

+}

76315

+ [(set_attr "length" "12")

76316

+ (set_attr "type" "three")])

76317

+

76318

+;; Move SFmode to a GPR from a VSX register. Because scalar floating point

76319

+;; type is stored internally as double precision, we have to convert it to the

76320

+;; vector format.

76321

+

76322

+(define_insn_and_split "reload_gpr_from_vsxsf"

76323

+ [(set (match_operand:SF 0 "register_operand" "=r")

76324

+ (unspec:SF [(match_operand:SF 1 "register_operand" "wa")]

76325

+ UNSPEC_P8V_RELOAD_FROM_VSX))

76326

+ (clobber (match_operand:V4SF 2 "register_operand" "=wa"))]

76327

+ "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"

76328

+ "#"

76329

+ "&& reload_completed"

76330

+ [(const_int 0)]

76331

+{

76332

+ rtx op0 = operands[0];

76333

+ rtx op1 = operands[1];

76334

+ rtx op2 = operands[2];

76335

+ rtx diop0 = simplify_gen_subreg (DImode, op0, SFmode, 0);

76336

+

76337

+ emit_insn (gen_vsx_xscvdpspn_scalar (op2, op1));

76338

+ emit_insn (gen_p8_mfvsrd_4_disf (diop0, op2));

76339

+ emit_insn (gen_lshrdi3 (diop0, diop0, GEN_INT (32)));

76340

+ DONE;

76341

+}

76342

+ [(set_attr "length" "12")

76343

+ (set_attr "type" "three")])

76344

+

76345

+(define_insn "p8_mfvsrd_4_disf"

76346

+ [(set (match_operand:DI 0 "register_operand" "=r")

76347

+ (unspec:DI [(match_operand:V4SF 1 "register_operand" "wa")]

76348

+ UNSPEC_P8V_RELOAD_FROM_VSX))]

76349

+ "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"

76350

+ "mfvsrd %0,%x1"

76351

+ [(set_attr "type" "mftgpr")])

76352

+

76353

+

76354

;; Next come the multi-word integer load and store and the load and store

76355

;; multiple insns.

76356

76357

@@ -8565,8 +10205,8 @@

76358

;; Use of fprs is disparaged slightly otherwise reload prefers to reload

76359

;; a gpr into a fpr instead of reloading an invalid 'Y' address

76360

(define_insn "*movdi_internal32"

76361

- [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=Y,r,r,?m,?*d,?*d,r,?wa")

76362

- (match_operand:DI 1 "input_operand" "r,Y,r,d,m,d,IJKnGHF,O"))]

76363

+ [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=Y,r,r,?m,?*d,?*d,r")

76364

+ (match_operand:DI 1 "input_operand" "r,Y,r,d,m,d,IJKnGHF"))]

76365

"! TARGET_POWERPC64

76366

&& (gpc_reg_operand (operands[0], DImode)

76367

|| gpc_reg_operand (operands[1], DImode))"

76368

@@ -8577,15 +10217,34 @@

76369

stfd%U0%X0 %1,%0

76370

lfd%U1%X1 %0,%1

76371

fmr %0,%1

76372

- #

76373

- xxlxor %x0,%x0,%x0"

76374

- [(set_attr "type" "store,load,*,fpstore,fpload,fp,*,vecsimple")])

76375

+ #"

76376

+ [(set_attr_alternative "type"

76377

+ [(const_string "store")

76378

+ (const_string "load")

76379

+ (const_string "*")

76380

+ (if_then_else

76381

+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")

76382

+ (const_string "fpstore_ux")

76383

+ (if_then_else

76384

+ (match_test "update_address_mem (operands[0], VOIDmode)")

76385

+ (const_string "fpstore_u")

76386

+ (const_string "fpstore")))

76387

+ (if_then_else

76388

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

76389

+ (const_string "fpload_ux")

76390

+ (if_then_else

76391

+ (match_test "update_address_mem (operands[1], VOIDmode)")

76392

+ (const_string "fpload_u")

76393

+ (const_string "fpload")))

76394

+ (const_string "fp")

76395

+ (const_string "*")])])

76396

76397

(define_split

76398

[(set (match_operand:DI 0 "gpc_reg_operand" "")

76399

(match_operand:DI 1 "const_int_operand" ""))]

76400

"! TARGET_POWERPC64 && reload_completed

76401

- && gpr_or_gpr_p (operands[0], operands[1])"

76402

+ && gpr_or_gpr_p (operands[0], operands[1])

76403

+ && !direct_move_p (operands[0], operands[1])"

76404

[(set (match_dup 2) (match_dup 4))

76405

(set (match_dup 3) (match_dup 1))]

76406

"

76407

@@ -8607,14 +10266,15 @@

76408

[(set (match_operand:DIFD 0 "rs6000_nonimmediate_operand" "")

76409

(match_operand:DIFD 1 "input_operand" ""))]

76410

"reload_completed && !TARGET_POWERPC64

76411

- && gpr_or_gpr_p (operands[0], operands[1])"

76412

+ && gpr_or_gpr_p (operands[0], operands[1])

76413

+ && !direct_move_p (operands[0], operands[1])"

76414

[(pc)]

76415

{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })

76416

76417

-(define_insn "*movdi_mfpgpr"

76418

- [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*d")

76419

- (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*d,r"))]

76420

- "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS

76421

+(define_insn "*movdi_internal64"

76422

+ [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*wg,r,?*wm")

76423

+ (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*wg,r,*wm,r"))]

76424

+ "TARGET_POWERPC64

76425

&& (gpc_reg_operand (operands[0], DImode)

76426

|| gpc_reg_operand (operands[1], DImode))"

76427

"@

76428

@@ -8631,33 +10291,52 @@

76429

mt%0 %1

76430

nop

76431

mftgpr %0,%1

76432

- mffgpr %0,%1"

76433

- [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,mftgpr,mffgpr")

76434

- (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4")])

76435

+ mffgpr %0,%1

76436

+ mfvsrd %0,%x1

76437

+ mtvsrd %x0,%1"

76438

+ [(set_attr_alternative "type"

76439

+ [(if_then_else

76440

+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")

76441

+ (const_string "store_ux")

76442

+ (if_then_else

76443

+ (match_test "update_address_mem (operands[0], VOIDmode)")

76444

+ (const_string "store_u")

76445

+ (const_string "store")))

76446

+ (if_then_else

76447

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

76448

+ (const_string "load_ux")

76449

+ (if_then_else

76450

+ (match_test "update_address_mem (operands[1], VOIDmode)")

76451

+ (const_string "load_u")

76452

+ (const_string "load")))

76453

+ (const_string "*")

76454

+ (const_string "*")

76455

+ (const_string "*")

76456

+ (const_string "*")

76457

+ (if_then_else

76458

+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")

76459

+ (const_string "fpstore_ux")

76460

+ (if_then_else

76461

+ (match_test "update_address_mem (operands[0], VOIDmode)")

76462

+ (const_string "fpstore_u")

76463

+ (const_string "fpstore")))

76464

+ (if_then_else

76465

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

76466

+ (const_string "fpload_ux")

76467

+ (if_then_else

76468

+ (match_test "update_address_mem (operands[1], VOIDmode)")

76469

+ (const_string "fpload_u")

76470

+ (const_string "fpload")))

76471

+ (const_string "fp")

76472

+ (const_string "mfjmpr")

76473

+ (const_string "mtjmpr")

76474

+ (const_string "*")

76475

+ (const_string "mftgpr")

76476

+ (const_string "mffgpr")

76477

+ (const_string "mftgpr")

76478

+ (const_string "mffgpr")])

76479

+ (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4,4")])

76480

76481

-(define_insn "*movdi_internal64"

76482

- [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,?wa")

76483

- (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,O"))]

76484

- "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)

76485

- && (gpc_reg_operand (operands[0], DImode)

76486

- || gpc_reg_operand (operands[1], DImode))"

76487

- "@

76488

- std%U0%X0 %1,%0

76489

- ld%U1%X1 %0,%1

76490

- mr %0,%1

76491

- li %0,%1

76492

- lis %0,%v1

76493

- #

76494

- stfd%U0%X0 %1,%0

76495

- lfd%U1%X1 %0,%1

76496

- fmr %0,%1

76497

- mf%1 %0

76498

- mt%0 %1

76499

- nop

76500

- xxlxor %x0,%x0,%x0"

76501

- [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,vecsimple")

76502

- (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])

76503

-

76504

;; immediate value valid for a single instruction hiding in a const_double

76505

(define_insn ""

76506

[(set (match_operand:DI 0 "gpc_reg_operand" "=r")

76507

@@ -8719,14 +10398,16 @@

76508

FAIL;

76509

}")

76510

76511

-;; TImode is similar, except that we usually want to compute the address into

76512

-;; a register and use lsi/stsi (the exception is during reload).

76513

+;; TImode/PTImode is similar, except that we usually want to compute the

76514

+;; address into a register and use lsi/stsi (the exception is during reload).

76515

76516

-(define_insn "*movti_string"

76517

- [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,Y,????r,????r,????r,r")

76518

- (match_operand:TI 1 "input_operand" "r,r,Q,Y,r,n"))]

76519

+(define_insn "*mov<mode>_string"

76520

+ [(set (match_operand:TI2 0 "reg_or_mem_operand" "=Q,Y,????r,????r,????r,r")

76521

+ (match_operand:TI2 1 "input_operand" "r,r,Q,Y,r,n"))]

76522

"! TARGET_POWERPC64

76523

- && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"

76524

+ && (<MODE>mode != TImode || VECTOR_MEM_NONE_P (TImode))

76525

+ && (gpc_reg_operand (operands[0], <MODE>mode)

76526

+ || gpc_reg_operand (operands[1], <MODE>mode))"

76527

"*

76528

{

76529

switch (which_alternative)

76530

@@ -8756,27 +10437,32 @@

76531

(const_string "always")

76532

(const_string "conditional")))])

76533

76534

-(define_insn "*movti_ppc64"

76535

- [(set (match_operand:TI 0 "nonimmediate_operand" "=Y,r,r")

76536

- (match_operand:TI 1 "input_operand" "r,Y,r"))]

76537

- "(TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)

76538

- || gpc_reg_operand (operands[1], TImode)))

76539

- && VECTOR_MEM_NONE_P (TImode)"

76540

- "#"

76541

- [(set_attr "type" "store,load,*")])

76542

+(define_insn "*mov<mode>_ppc64"

76543

+ [(set (match_operand:TI2 0 "nonimmediate_operand" "=wQ,Y,r,r,r,r")

76544

+ (match_operand:TI2 1 "input_operand" "r,r,wQ,Y,r,n"))]

76545

+ "(TARGET_POWERPC64 && VECTOR_MEM_NONE_P (<MODE>mode)

76546

+ && (gpc_reg_operand (operands[0], <MODE>mode)

76547

+ || gpc_reg_operand (operands[1], <MODE>mode)))"

76548

+{

76549

+ return rs6000_output_move_128bit (operands);

76550

+}

76551

+ [(set_attr "type" "store,store,load,load,*,*")

76552

+ (set_attr "length" "8")])

76553

76554

(define_split

76555

- [(set (match_operand:TI 0 "gpc_reg_operand" "")

76556

- (match_operand:TI 1 "const_double_operand" ""))]

76557

- "TARGET_POWERPC64 && VECTOR_MEM_NONE_P (TImode)"

76558

+ [(set (match_operand:TI2 0 "int_reg_operand" "")

76559

+ (match_operand:TI2 1 "const_double_operand" ""))]

76560

+ "TARGET_POWERPC64

76561

+ && (VECTOR_MEM_NONE_P (<MODE>mode)

76562

+ || (reload_completed && INT_REGNO_P (REGNO (operands[0]))))"

76563

[(set (match_dup 2) (match_dup 4))

76564

(set (match_dup 3) (match_dup 5))]

76565

"

76566

{

76567

operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,

76568

- TImode);

76569

+ <MODE>mode);

76570

operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,

76571

- TImode);

76572

+ <MODE>mode);

76573

if (GET_CODE (operands[1]) == CONST_DOUBLE)

76574

{

76575

operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));

76576

@@ -8792,10 +10478,12 @@

76577

}")

76578

76579

(define_split

76580

- [(set (match_operand:TI 0 "nonimmediate_operand" "")

76581

- (match_operand:TI 1 "input_operand" ""))]

76582

- "reload_completed && VECTOR_MEM_NONE_P (TImode)

76583

- && gpr_or_gpr_p (operands[0], operands[1])"

76584

+ [(set (match_operand:TI2 0 "nonimmediate_operand" "")

76585

+ (match_operand:TI2 1 "input_operand" ""))]

76586

+ "reload_completed

76587

+ && gpr_or_gpr_p (operands[0], operands[1])

76588

+ && !direct_move_p (operands[0], operands[1])

76589

+ && !quad_load_store_p (operands[0], operands[1])"

76590

[(pc)]

76591

{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })

76592

76593

@@ -9651,7 +11339,7 @@

76594

(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]

76595

UNSPEC_TLSGD)

76596

(clobber (reg:SI LR_REGNO))]

76597

- "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"

76598

+ "HAVE_AS_TLS && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"

76599

{

76600

if (TARGET_CMODEL != CMODEL_SMALL)

76601

return "addis %0,%1,%2@got@tlsgd@ha\;addi %0,%0,%2@got@tlsgd@l\;"

76602

@@ -9723,7 +11411,7 @@

76603

(unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))

76604

(set (match_dup 0)

76605

(lo_sum:TLSmode (match_dup 3)

76606

- (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)))]

76607

+ (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))]

76608

"

76609

{

76610

operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);

76611

@@ -9746,7 +11434,8 @@

76612

(define_insn "*tls_gd_low<TLSmode:tls_abi_suffix>"

76613

[(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")

76614

(lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")

76615

- (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]

76616

+ (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")

76617

+ (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]

76618

UNSPEC_TLSGD)))]

76619

"HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"

76620

"addi %0,%1,%2@got@tlsgd@l"

76621

@@ -9759,7 +11448,8 @@

76622

(unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]

76623

UNSPEC_TLSGD)

76624

(clobber (reg:SI LR_REGNO))]

76625

- "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"

76626

+ "HAVE_AS_TLS && TARGET_TLS_MARKERS

76627

+ && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"

76628

"bl %z1(%3@tlsgd)\;nop"

76629

[(set_attr "type" "branch")

76630

(set_attr "length" "8")])

76631

@@ -9791,7 +11481,7 @@

76632

(unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]

76633

UNSPEC_TLSLD)

76634

(clobber (reg:SI LR_REGNO))]

76635

- "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"

76636

+ "HAVE_AS_TLS && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"

76637

{

76638

if (TARGET_CMODEL != CMODEL_SMALL)

76639

return "addis %0,%1,%&@got@tlsld@ha\;addi %0,%0,%&@got@tlsld@l\;"

76640

@@ -9858,7 +11548,7 @@

76641

(unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))

76642

(set (match_dup 0)

76643

(lo_sum:TLSmode (match_dup 2)

76644

- (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))]

76645

+ (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))]

76646

"

76647

{

76648

operands[2] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);

76649

@@ -9881,7 +11571,9 @@

76650

(define_insn "*tls_ld_low<TLSmode:tls_abi_suffix>"

76651

[(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")

76652

(lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")

76653

- (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))]

76654

+ (unspec:TLSmode [(const_int 0)

76655

+ (match_operand:TLSmode 2 "gpc_reg_operand" "b")]

76656

+ UNSPEC_TLSLD)))]

76657

"HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"

76658

"addi %0,%1,%&@got@tlsld@l"

76659

[(set_attr "length" "4")])

76660

@@ -9892,7 +11584,8 @@

76661

(match_operand 2 "" "g")))

76662

(unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)

76663

(clobber (reg:SI LR_REGNO))]

76664

- "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"

76665

+ "HAVE_AS_TLS && TARGET_TLS_MARKERS

76666

+ && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"

76667

"bl %z1(%&@tlsld)\;nop"

76668

[(set_attr "type" "branch")

76669

(set_attr "length" "8")])

76670

@@ -9953,7 +11646,7 @@

76671

(unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))

76672

(set (match_dup 0)

76673

(lo_sum:TLSmode (match_dup 3)

76674

- (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTDTPREL)))]

76675

+ (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))]

76676

"

76677

{

76678

operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);

76679

@@ -9976,7 +11669,8 @@

76680

(define_insn "*tls_got_dtprel_low<TLSmode:tls_abi_suffix>"

76681

[(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")

76682

(lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")

76683

- (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]

76684

+ (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")

76685

+ (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]

76686

UNSPEC_TLSGOTDTPREL)))]

76687

"HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"

76688

"l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel@l(%1)"

76689

@@ -10022,7 +11716,7 @@

76690

(unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))

76691

(set (match_dup 0)

76692

(lo_sum:TLSmode (match_dup 3)

76693

- (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTTPREL)))]

76694

+ (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))]

76695

"

76696

{

76697

operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);

76698

@@ -10045,7 +11739,8 @@

76699

(define_insn "*tls_got_tprel_low<TLSmode:tls_abi_suffix>"

76700

[(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")

76701

(lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")

76702

- (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]

76703

+ (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")

76704

+ (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]

76705

UNSPEC_TLSGOTTPREL)))]

76706

"HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"

76707

"l<TLSmode:tls_insn_suffix> %0,%2@got@tprel@l(%1)"

76708

@@ -10261,7 +11956,7 @@

76709

[(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")

76710

(unspec:SI [(const_int 0)] UNSPEC_TOC))

76711

(use (reg:SI 2))])]

76712

- "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"

76713

+ "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_32BIT"

76714

"*

76715

{

76716

char buf[30];

76717

@@ -10276,7 +11971,7 @@

76718

[(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")

76719

(unspec:DI [(const_int 0)] UNSPEC_TOC))

76720

(use (reg:DI 2))])]

76721

- "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"

76722

+ "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_64BIT"

76723

"*

76724

{

76725

char buf[30];

76726

@@ -10306,7 +12001,7 @@

76727

[(parallel [(set (reg:SI LR_REGNO)

76728

(match_operand:SI 0 "immediate_operand" "s"))

76729

(use (unspec [(match_dup 0)] UNSPEC_TOC))])]

76730

- "TARGET_ELF && DEFAULT_ABI != ABI_AIX

76731

+ "TARGET_ELF && DEFAULT_ABI == ABI_V4

76732

&& (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"

76733

"")

76734

76735

@@ -10314,7 +12009,7 @@

76736

[(set (reg:SI LR_REGNO)

76737

(match_operand:SI 0 "immediate_operand" "s"))

76738

(use (unspec [(match_dup 0)] UNSPEC_TOC))]

76739

- "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX

76740

+ "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4

76741

&& (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"

76742

"bcl 20,31,%0\\n%0:"

76743

[(set_attr "type" "branch")

76744

@@ -10324,7 +12019,7 @@

76745

[(set (reg:SI LR_REGNO)

76746

(match_operand:SI 0 "immediate_operand" "s"))

76747

(use (unspec [(match_dup 0)] UNSPEC_TOC))]

76748

- "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX

76749

+ "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4

76750

&& (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"

76751

"*

76752

{

76753

@@ -10344,7 +12039,7 @@

76754

(label_ref (match_operand 1 "" ""))]

76755

UNSPEC_TOCPTR))

76756

(match_dup 1)])]

76757

- "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"

76758

+ "TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"

76759

"")

76760

76761

(define_insn "load_toc_v4_PIC_1b_normal"

76762

@@ -10353,7 +12048,7 @@

76763

(label_ref (match_operand 1 "" ""))]

76764

UNSPEC_TOCPTR))

76765

(match_dup 1)]

76766

- "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"

76767

+ "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"

76768

"bcl 20,31,$+8\;.long %0-$"

76769

[(set_attr "type" "branch")

76770

(set_attr "length" "8")])

76771

@@ -10364,7 +12059,7 @@

76772

(label_ref (match_operand 1 "" ""))]

76773

UNSPEC_TOCPTR))

76774

(match_dup 1)]

76775

- "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"

76776

+ "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"

76777

"*

76778

{

76779

char name[32];

76780

@@ -10382,7 +12077,7 @@

76781

(mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")

76782

(minus:SI (match_operand:SI 2 "immediate_operand" "s")

76783

(match_operand:SI 3 "immediate_operand" "s")))))]

76784

- "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"

76785

+ "TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"

76786

"lwz %0,%2-%3(%1)"

76787

[(set_attr "type" "load")])

76788

76789

@@ -10392,7 +12087,7 @@

76790

(high:SI

76791

(minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")

76792

(match_operand:SI 3 "symbol_ref_operand" "s")))))]

76793

- "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"

76794

+ "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic"

76795

"addis %0,%1,%2-%3@ha")

76796

76797

(define_insn "load_toc_v4_PIC_3c"

76798

@@ -10400,7 +12095,7 @@

76799

(lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")

76800

(minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")

76801

(match_operand:SI 3 "symbol_ref_operand" "s"))))]

76802

- "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"

76803

+ "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic"

76804

"addi %0,%1,%2-%3@l")

76805

76806

;; If the TOC is shared over a translation unit, as happens with all

76807

@@ -10542,8 +12237,13 @@

76808

76809

operands[0] = XEXP (operands[0], 0);

76810

76811

+ if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)

76812

+ {

76813

+ rs6000_call_aix (NULL_RTX, operands[0], operands[1], operands[2]);

76814

+ DONE;

76815

+ }

76816

+

76817

if (GET_CODE (operands[0]) != SYMBOL_REF

76818

- || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))

76819

|| (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))

76820

{

76821

if (INTVAL (operands[2]) & CALL_LONG)

76822

@@ -10556,12 +12256,6 @@

76823

operands[0] = force_reg (Pmode, operands[0]);

76824

break;

76825

76826

- case ABI_AIX:

76827

- /* AIX function pointers are really pointers to a three word

76828

- area. */

76829

- rs6000_call_indirect_aix (NULL_RTX, operands[0], operands[1]);

76830

- DONE;

76831

-

76832

default:

76833

gcc_unreachable ();

76834

}

76835

@@ -10587,8 +12281,13 @@

76836

76837

operands[1] = XEXP (operands[1], 0);

76838

76839

+ if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)

76840

+ {

76841

+ rs6000_call_aix (operands[0], operands[1], operands[2], operands[3]);

76842

+ DONE;

76843

+ }

76844

+

76845

if (GET_CODE (operands[1]) != SYMBOL_REF

76846

- || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))

76847

|| (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))

76848

{

76849

if (INTVAL (operands[3]) & CALL_LONG)

76850

@@ -10601,12 +12300,6 @@

76851

operands[1] = force_reg (Pmode, operands[1]);

76852

break;

76853

76854

- case ABI_AIX:

76855

- /* AIX function pointers are really pointers to a three word

76856

- area. */

76857

- rs6000_call_indirect_aix (operands[0], operands[1], operands[2]);

76858

- DONE;

76859

-

76860

default:

76861

gcc_unreachable ();

76862

}

76863

@@ -10698,136 +12391,7 @@

76864

[(set_attr "type" "branch")

76865

(set_attr "length" "4,8")])

76866

76867

-;; Call to indirect functions with the AIX abi using a 3 word descriptor.

76868

-;; Operand0 is the addresss of the function to call

76869

-;; Operand1 is the flag for System V.4 for unprototyped or FP registers

76870

-;; Operand2 is the location in the function descriptor to load r2 from

76871

-;; Operand3 is the stack location to hold the current TOC pointer

76872

76873

-(define_insn "call_indirect_aix<ptrsize>"

76874

- [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))

76875

- (match_operand 1 "" "g,g"))

76876

- (use (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))

76877

- (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))

76878

- (use (reg:P STATIC_CHAIN_REGNUM))

76879

- (clobber (reg:P LR_REGNO))]

76880

- "DEFAULT_ABI == ABI_AIX && TARGET_POINTERS_TO_NESTED_FUNCTIONS"

76881

- "<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3"

76882

- [(set_attr "type" "jmpreg")

76883

- (set_attr "length" "12")])

76884

-

76885

-;; Like call_indirect_aix<ptrsize>, but no use of the static chain

76886

-;; Operand0 is the addresss of the function to call

76887

-;; Operand1 is the flag for System V.4 for unprototyped or FP registers

76888

-;; Operand2 is the location in the function descriptor to load r2 from

76889

-;; Operand3 is the stack location to hold the current TOC pointer

76890

-

76891

-(define_insn "call_indirect_aix<ptrsize>_nor11"

76892

- [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))

76893

- (match_operand 1 "" "g,g"))

76894

- (use (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))

76895

- (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))

76896

- (clobber (reg:P LR_REGNO))]

76897

- "DEFAULT_ABI == ABI_AIX && !TARGET_POINTERS_TO_NESTED_FUNCTIONS"

76898

- "<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3"

76899

- [(set_attr "type" "jmpreg")

76900

- (set_attr "length" "12")])

76901

-

76902

-;; Operand0 is the return result of the function

76903

-;; Operand1 is the addresss of the function to call

76904

-;; Operand2 is the flag for System V.4 for unprototyped or FP registers

76905

-;; Operand3 is the location in the function descriptor to load r2 from

76906

-;; Operand4 is the stack location to hold the current TOC pointer

76907

-

76908

-(define_insn "call_value_indirect_aix<ptrsize>"

76909

- [(set (match_operand 0 "" "")

76910

- (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))

76911

- (match_operand 2 "" "g,g")))

76912

- (use (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))

76913

- (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "<ptrm>,<ptrm>"))

76914

- (use (reg:P STATIC_CHAIN_REGNUM))

76915

- (clobber (reg:P LR_REGNO))]

76916

- "DEFAULT_ABI == ABI_AIX && TARGET_POINTERS_TO_NESTED_FUNCTIONS"

76917

- "<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4"

76918

- [(set_attr "type" "jmpreg")

76919

- (set_attr "length" "12")])

76920

-

76921

-;; Like call_value_indirect_aix<ptrsize>, but no use of the static chain

76922

-;; Operand0 is the return result of the function

76923

-;; Operand1 is the addresss of the function to call

76924

-;; Operand2 is the flag for System V.4 for unprototyped or FP registers

76925

-;; Operand3 is the location in the function descriptor to load r2 from

76926

-;; Operand4 is the stack location to hold the current TOC pointer

76927

-

76928

-(define_insn "call_value_indirect_aix<ptrsize>_nor11"

76929

- [(set (match_operand 0 "" "")

76930

- (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))

76931

- (match_operand 2 "" "g,g")))

76932

- (use (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))

76933

- (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "<ptrm>,<ptrm>"))

76934

- (clobber (reg:P LR_REGNO))]

76935

- "DEFAULT_ABI == ABI_AIX && !TARGET_POINTERS_TO_NESTED_FUNCTIONS"

76936

- "<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4"

76937

- [(set_attr "type" "jmpreg")

76938

- (set_attr "length" "12")])

76939

-

76940

-;; Call to function which may be in another module. Restore the TOC

76941

-;; pointer (r2) after the call unless this is System V.

76942

-;; Operand2 is nonzero if we are using the V.4 calling sequence and

76943

-;; either the function was not prototyped, or it was prototyped as a

76944

-;; variable argument function. It is > 0 if FP registers were passed

76945

-;; and < 0 if they were not.

76946

-

76947

-(define_insn "*call_nonlocal_aix32"

76948

- [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))

76949

- (match_operand 1 "" "g"))

76950

- (use (match_operand:SI 2 "immediate_operand" "O"))

76951

- (clobber (reg:SI LR_REGNO))]

76952

- "TARGET_32BIT

76953

- && DEFAULT_ABI == ABI_AIX

76954

- && (INTVAL (operands[2]) & CALL_LONG) == 0"

76955

- "bl %z0\;nop"

76956

- [(set_attr "type" "branch")

76957

- (set_attr "length" "8")])

76958

-

76959

-(define_insn "*call_nonlocal_aix64"

76960

- [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))

76961

- (match_operand 1 "" "g"))

76962

- (use (match_operand:SI 2 "immediate_operand" "O"))

76963

- (clobber (reg:SI LR_REGNO))]

76964

- "TARGET_64BIT

76965

- && DEFAULT_ABI == ABI_AIX

76966

- && (INTVAL (operands[2]) & CALL_LONG) == 0"

76967

- "bl %z0\;nop"

76968

- [(set_attr "type" "branch")

76969

- (set_attr "length" "8")])

76970

-

76971

-(define_insn "*call_value_nonlocal_aix32"

76972

- [(set (match_operand 0 "" "")

76973

- (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))

76974

- (match_operand 2 "" "g")))

76975

- (use (match_operand:SI 3 "immediate_operand" "O"))

76976

- (clobber (reg:SI LR_REGNO))]

76977

- "TARGET_32BIT

76978

- && DEFAULT_ABI == ABI_AIX

76979

- && (INTVAL (operands[3]) & CALL_LONG) == 0"

76980

- "bl %z1\;nop"

76981

- [(set_attr "type" "branch")

76982

- (set_attr "length" "8")])

76983

-

76984

-(define_insn "*call_value_nonlocal_aix64"

76985

- [(set (match_operand 0 "" "")

76986

- (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))

76987

- (match_operand 2 "" "g")))

76988

- (use (match_operand:SI 3 "immediate_operand" "O"))

76989

- (clobber (reg:SI LR_REGNO))]

76990

- "TARGET_64BIT

76991

- && DEFAULT_ABI == ABI_AIX

76992

- && (INTVAL (operands[3]) & CALL_LONG) == 0"

76993

- "bl %z1\;nop"

76994

- [(set_attr "type" "branch")

76995

- (set_attr "length" "8")])

76996

-

76997

;; A function pointer under System V is just a normal pointer

76998

;; operands[0] is the function pointer

76999

;; operands[1] is the stack size to clean up

77000

@@ -11009,6 +12573,104 @@

77001

[(set_attr "type" "branch,branch")

77002

(set_attr "length" "4,8")])

77003

77004

+

77005

+;; Call to AIX abi function in the same module.

77006

+

77007

+(define_insn "*call_local_aix<mode>"

77008

+ [(call (mem:SI (match_operand:P 0 "current_file_function_operand" "s"))

77009

+ (match_operand 1 "" "g"))

77010

+ (clobber (reg:P LR_REGNO))]

77011

+ "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"

77012

+ "bl %z0"

77013

+ [(set_attr "type" "branch")

77014

+ (set_attr "length" "4")])

77015

+

77016

+(define_insn "*call_value_local_aix<mode>"

77017

+ [(set (match_operand 0 "" "")

77018

+ (call (mem:SI (match_operand:P 1 "current_file_function_operand" "s"))

77019

+ (match_operand 2 "" "g")))

77020

+ (clobber (reg:P LR_REGNO))]

77021

+ "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"

77022

+ "bl %z1"

77023

+ [(set_attr "type" "branch")

77024

+ (set_attr "length" "4")])

77025

+

77026

+;; Call to AIX abi function which may be in another module.

77027

+;; Restore the TOC pointer (r2) after the call.

77028

+

77029

+(define_insn "*call_nonlocal_aix<mode>"

77030

+ [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s"))

77031

+ (match_operand 1 "" "g"))

77032

+ (clobber (reg:P LR_REGNO))]

77033

+ "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"

77034

+ "bl %z0\;nop"

77035

+ [(set_attr "type" "branch")

77036

+ (set_attr "length" "8")])

77037

+

77038

+(define_insn "*call_value_nonlocal_aix<mode>"

77039

+ [(set (match_operand 0 "" "")

77040

+ (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s"))

77041

+ (match_operand 2 "" "g")))

77042

+ (clobber (reg:P LR_REGNO))]

77043

+ "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"

77044

+ "bl %z1\;nop"

77045

+ [(set_attr "type" "branch")

77046

+ (set_attr "length" "8")])

77047

+

77048

+;; Call to indirect functions with the AIX abi using a 3 word descriptor.

77049

+;; Operand0 is the addresss of the function to call

77050

+;; Operand2 is the location in the function descriptor to load r2 from

77051

+;; Operand3 is the stack location to hold the current TOC pointer

77052

+

77053

+(define_insn "*call_indirect_aix<mode>"

77054

+ [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))

77055

+ (match_operand 1 "" "g,g"))

77056

+ (use (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))

77057

+ (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))

77058

+ (clobber (reg:P LR_REGNO))]

77059

+ "DEFAULT_ABI == ABI_AIX"

77060

+ "<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3"

77061

+ [(set_attr "type" "jmpreg")

77062

+ (set_attr "length" "12")])

77063

+

77064

+(define_insn "*call_value_indirect_aix<mode>"

77065

+ [(set (match_operand 0 "" "")

77066

+ (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))

77067

+ (match_operand 2 "" "g,g")))

77068

+ (use (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))

77069

+ (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "<ptrm>,<ptrm>"))

77070

+ (clobber (reg:P LR_REGNO))]

77071

+ "DEFAULT_ABI == ABI_AIX"

77072

+ "<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4"

77073

+ [(set_attr "type" "jmpreg")

77074

+ (set_attr "length" "12")])

77075

+

77076

+;; Call to indirect functions with the ELFv2 ABI.

77077

+;; Operand0 is the addresss of the function to call

77078

+;; Operand2 is the stack location to hold the current TOC pointer

77079

+

77080

+(define_insn "*call_indirect_elfv2<mode>"

77081

+ [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))

77082

+ (match_operand 1 "" "g,g"))

77083

+ (set (reg:P TOC_REGNUM) (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))

77084

+ (clobber (reg:P LR_REGNO))]

77085

+ "DEFAULT_ABI == ABI_ELFv2"

77086

+ "b%T0l\;<ptrload> 2,%2"

77087

+ [(set_attr "type" "jmpreg")

77088

+ (set_attr "length" "8")])

77089

+

77090

+(define_insn "*call_value_indirect_elfv2<mode>"

77091

+ [(set (match_operand 0 "" "")

77092

+ (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))

77093

+ (match_operand 2 "" "g,g")))

77094

+ (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))

77095

+ (clobber (reg:P LR_REGNO))]

77096

+ "DEFAULT_ABI == ABI_ELFv2"

77097

+ "b%T1l\;<ptrload> 2,%3"

77098

+ [(set_attr "type" "jmpreg")

77099

+ (set_attr "length" "8")])

77100

+

77101

+

77102

;; Call subroutine returning any type.

77103

(define_expand "untyped_call"

77104

[(parallel [(call (match_operand 0 "" "")

77105

@@ -11056,8 +12718,41 @@

77106

gcc_assert (GET_CODE (operands[1]) == CONST_INT);

77107

77108

operands[0] = XEXP (operands[0], 0);

77109

+

77110

+ if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)

77111

+ {

77112

+ rs6000_sibcall_aix (NULL_RTX, operands[0], operands[1], operands[2]);

77113

+ DONE;

77114

+ }

77115

}")

77116

77117

+(define_expand "sibcall_value"

77118

+ [(parallel [(set (match_operand 0 "register_operand" "")

77119

+ (call (mem:SI (match_operand 1 "address_operand" ""))

77120

+ (match_operand 2 "" "")))

77121

+ (use (match_operand 3 "" ""))

77122

+ (use (reg:SI LR_REGNO))

77123

+ (simple_return)])]

77124

+ ""

77125

+ "

77126

+{

77127

+#if TARGET_MACHO

77128

+ if (MACHOPIC_INDIRECT)

77129

+ operands[1] = machopic_indirect_call_target (operands[1]);

77130

+#endif

77131

+

77132

+ gcc_assert (GET_CODE (operands[1]) == MEM);

77133

+ gcc_assert (GET_CODE (operands[2]) == CONST_INT);

77134

+

77135

+ operands[1] = XEXP (operands[1], 0);

77136

+

77137

+ if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)

77138

+ {

77139

+ rs6000_sibcall_aix (operands[0], operands[1], operands[2], operands[3]);

77140

+ DONE;

77141

+ }

77142

+}")

77143

+

77144

;; this and similar patterns must be marked as using LR, otherwise

77145

;; dataflow will try to delete the store into it. This is true

77146

;; even when the actual reg to jump to is in CTR, when LR was

77147

@@ -11123,7 +12818,6 @@

77148

[(set_attr "type" "branch")

77149

(set_attr "length" "4,8")])

77150

77151

-

77152

(define_insn "*sibcall_value_local64"

77153

[(set (match_operand 0 "" "")

77154

(call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))

77155

@@ -11145,35 +12839,6 @@

77156

[(set_attr "type" "branch")

77157

(set_attr "length" "4,8")])

77158

77159

-(define_insn "*sibcall_nonlocal_aix<mode>"

77160

- [(call (mem:SI (match_operand:P 0 "call_operand" "s,c"))

77161

- (match_operand 1 "" "g,g"))

77162

- (use (match_operand:SI 2 "immediate_operand" "O,O"))

77163

- (use (reg:SI LR_REGNO))

77164

- (simple_return)]

77165

- "DEFAULT_ABI == ABI_AIX

77166

- && (INTVAL (operands[2]) & CALL_LONG) == 0"

77167

- "@

77168

- b %z0

77169

- b%T0"

77170

- [(set_attr "type" "branch")

77171

- (set_attr "length" "4")])

77172

-

77173

-(define_insn "*sibcall_value_nonlocal_aix<mode>"

77174

- [(set (match_operand 0 "" "")

77175

- (call (mem:SI (match_operand:P 1 "call_operand" "s,c"))

77176

- (match_operand 2 "" "g,g")))

77177

- (use (match_operand:SI 3 "immediate_operand" "O,O"))

77178

- (use (reg:SI LR_REGNO))

77179

- (simple_return)]

77180

- "DEFAULT_ABI == ABI_AIX

77181

- && (INTVAL (operands[3]) & CALL_LONG) == 0"

77182

- "@

77183

- b %z1

77184

- b%T1"

77185

- [(set_attr "type" "branch")

77186

- (set_attr "length" "4")])

77187

-

77188

(define_insn "*sibcall_nonlocal_sysv<mode>"

77189

[(call (mem:SI (match_operand:P 0 "call_operand" "s,s,c,c"))

77190

(match_operand 1 "" ""))

77191

@@ -11204,27 +12869,6 @@

77192

[(set_attr "type" "branch")

77193

(set_attr "length" "4,8,4,8")])

77194

77195

-(define_expand "sibcall_value"

77196

- [(parallel [(set (match_operand 0 "register_operand" "")

77197

- (call (mem:SI (match_operand 1 "address_operand" ""))

77198

- (match_operand 2 "" "")))

77199

- (use (match_operand 3 "" ""))

77200

- (use (reg:SI LR_REGNO))

77201

- (simple_return)])]

77202

- ""

77203

- "

77204

-{

77205

-#if TARGET_MACHO

77206

- if (MACHOPIC_INDIRECT)

77207

- operands[1] = machopic_indirect_call_target (operands[1]);

77208

-#endif

77209

-

77210

- gcc_assert (GET_CODE (operands[1]) == MEM);

77211

- gcc_assert (GET_CODE (operands[2]) == CONST_INT);

77212

-

77213

- operands[1] = XEXP (operands[1], 0);

77214

-}")

77215

-

77216

(define_insn "*sibcall_value_nonlocal_sysv<mode>"

77217

[(set (match_operand 0 "" "")

77218

(call (mem:SI (match_operand:P 1 "call_operand" "s,s,c,c"))

77219

@@ -11256,6 +12900,31 @@

77220

[(set_attr "type" "branch")

77221

(set_attr "length" "4,8,4,8")])

77222

77223

+;; AIX ABI sibling call patterns.

77224

+

77225

+(define_insn "*sibcall_aix<mode>"

77226

+ [(call (mem:SI (match_operand:P 0 "call_operand" "s,c"))

77227

+ (match_operand 1 "" "g,g"))

77228

+ (simple_return)]

77229

+ "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"

77230

+ "@

77231

+ b %z0

77232

+ b%T0"

77233

+ [(set_attr "type" "branch")

77234

+ (set_attr "length" "4")])

77235

+

77236

+(define_insn "*sibcall_value_aix<mode>"

77237

+ [(set (match_operand 0 "" "")

77238

+ (call (mem:SI (match_operand:P 1 "call_operand" "s,c"))

77239

+ (match_operand 2 "" "g,g")))

77240

+ (simple_return)]

77241

+ "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"

77242

+ "@

77243

+ b %z1

77244

+ b%T1"

77245

+ [(set_attr "type" "branch")

77246

+ (set_attr "length" "4")])

77247

+

77248

(define_expand "sibcall_epilogue"

77249

[(use (const_int 0))]

77250

""

77251

@@ -11294,7 +12963,14 @@

77252

operands[1] = gen_rtx_REG (Pmode, 0);

77253

return "st<wd>%U0%X0 %1,%0";

77254

}

77255

- [(set_attr "type" "store")

77256

+ [(set (attr "type")

77257

+ (if_then_else

77258

+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")

77259

+ (const_string "store_ux")

77260

+ (if_then_else

77261

+ (match_test "update_address_mem (operands[0], VOIDmode)")

77262

+ (const_string "store_u")

77263

+ (const_string "store"))))

77264

(set_attr "length" "4")])

77265

77266

(define_insn "probe_stack_range<P:mode>"

77267

@@ -11589,23 +13265,6 @@

77268

[(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))

77269

(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])

77270

77271

-(define_insn "*cmpsf_internal1"

77272

- [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")

77273

- (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")

77274

- (match_operand:SF 2 "gpc_reg_operand" "f")))]

77275

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"

77276

- "fcmpu %0,%1,%2"

77277

- [(set_attr "type" "fpcompare")])

77278

-

77279

-(define_insn "*cmpdf_internal1"

77280

- [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")

77281

- (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "d")

77282

- (match_operand:DF 2 "gpc_reg_operand" "d")))]

77283

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT

77284

- && !VECTOR_UNIT_VSX_P (DFmode)"

77285

- "fcmpu %0,%1,%2"

77286

- [(set_attr "type" "fpcompare")])

77287

-

77288

;; Only need to compare second words if first words equal

77289

(define_insn "*cmptf_internal1"

77290

[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")

77291

@@ -13501,6 +15160,14 @@

77292

"mfcr %0"

77293

[(set_attr "type" "mfcr")])

77294

77295

+(define_insn "*crsave"

77296

+ [(match_parallel 0 "crsave_operation"

77297

+ [(set (match_operand:SI 1 "memory_operand" "=m")

77298

+ (match_operand:SI 2 "gpc_reg_operand" "r"))])]

77299

+ ""

77300

+ "stw %2,%1"

77301

+ [(set_attr "type" "store")])

77302

+

77303

(define_insn "*stmw"

77304

[(match_parallel 0 "stmw_operation"

77305

[(set (match_operand:SI 1 "memory_operand" "=m")

77306

@@ -13885,7 +15552,7 @@

77307

(match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]

77308

"TARGET_POPCNTD"

77309

"bpermd %0,%1,%2"

77310

- [(set_attr "type" "integer")])

77311

+ [(set_attr "type" "popcnt")])

77312

77313

77314

;; Builtin fma support. Handle

77315

@@ -13900,6 +15567,20 @@

77316

""

77317

"")

77318

77319

+(define_insn "*fma<mode>4_fpr"

77320

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")

77321

+ (fma:SFDF

77322

+ (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>,<Fv>")

77323

+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")

77324

+ (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>")))]

77325

+ "TARGET_<MODE>_FPR"

77326

+ "@

77327

+ fmadd<Ftrad> %0,%1,%2,%3

77328

+ xsmadda<Fvsx> %x0,%x1,%x2

77329

+ xsmaddm<Fvsx> %x0,%x1,%x3"

77330

+ [(set_attr "type" "fp")

77331

+ (set_attr "fp_type" "fp_maddsub_<Fs>")])

77332

+

77333

; Altivec only has fma and nfms.

77334

(define_expand "fms<mode>4"

77335

[(set (match_operand:FMA_F 0 "register_operand" "")

77336

@@ -13910,6 +15591,20 @@

77337

"!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"

77338

"")

77339

77340

+(define_insn "*fms<mode>4_fpr"

77341

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")

77342

+ (fma:SFDF

77343

+ (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")

77344

+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")

77345

+ (neg:SFDF (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>"))))]

77346

+ "TARGET_<MODE>_FPR"

77347

+ "@

77348

+ fmsub<Ftrad> %0,%1,%2,%3

77349

+ xsmsuba<Fvsx> %x0,%x1,%x2

77350

+ xsmsubm<Fvsx> %x0,%x1,%x3"

77351

+ [(set_attr "type" "fp")

77352

+ (set_attr "fp_type" "fp_maddsub_<Fs>")])

77353

+

77354

;; If signed zeros are ignored, -(a * b - c) = -a * b + c.

77355

(define_expand "fnma<mode>4"

77356

[(set (match_operand:FMA_F 0 "register_operand" "")

77357

@@ -13943,6 +15638,21 @@

77358

"!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"

77359

"")

77360

77361

+(define_insn "*nfma<mode>4_fpr"

77362

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")

77363

+ (neg:SFDF

77364

+ (fma:SFDF

77365

+ (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")

77366

+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")

77367

+ (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>"))))]

77368

+ "TARGET_<MODE>_FPR"

77369

+ "@

77370

+ fnmadd<Ftrad> %0,%1,%2,%3

77371

+ xsnmadda<Fvsx> %x0,%x1,%x2

77372

+ xsnmaddm<Fvsx> %x0,%x1,%x3"

77373

+ [(set_attr "type" "fp")

77374

+ (set_attr "fp_type" "fp_maddsub_<Fs>")])

77375

+

77376

; Not an official optab name, but used from builtins.

77377

(define_expand "nfms<mode>4"

77378

[(set (match_operand:FMA_F 0 "register_operand" "")

77379

@@ -13954,6 +15664,23 @@

77380

""

77381

"")

77382

77383

+(define_insn "*nfmssf4_fpr"

77384

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")

77385

+ (neg:SFDF

77386

+ (fma:SFDF

77387

+ (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")

77388

+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")

77389

+ (neg:SFDF

77390

+ (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>")))))]

77391

+ "TARGET_<MODE>_FPR"

77392

+ "@

77393

+ fnmsub<Ftrad> %0,%1,%2,%3

77394

+ xsnmsuba<Fvsx> %x0,%x1,%x2

77395

+ xsnmsubm<Fvsx> %x0,%x1,%x3"

77396

+ [(set_attr "type" "fp")

77397

+ (set_attr "fp_type" "fp_maddsub_<Fs>")])

77398

+

77399

+

77400

(define_expand "rs6000_get_timebase"

77401

[(use (match_operand:DI 0 "gpc_reg_operand" ""))]

77402

""

77403

@@ -14020,7 +15747,229 @@

77404

})

77405

77406

77407

+;; Power8 fusion support for fusing an addis instruction with a D-form load of

77408

+;; a GPR. The addis instruction must be adjacent to the load, and use the same

77409

+;; register that is being loaded. The fused ops must be physically adjacent.

77410

77411

+;; We use define_peephole for the actual addis/load, and the register used to

77412

+;; hold the addis value must be the same as the register being loaded. We use

77413

+;; define_peephole2 to change the register used for addis to be the register

77414

+;; being loaded, since we can look at whether it is dead after the load insn.

77415

+

77416

+(define_peephole

77417

+ [(set (match_operand:P 0 "base_reg_operand" "")

77418

+ (match_operand:P 1 "fusion_gpr_addis" ""))

77419

+ (set (match_operand:INT1 2 "base_reg_operand" "")

77420

+ (match_operand:INT1 3 "fusion_gpr_mem_load" ""))]

77421

+ "TARGET_P8_FUSION && fusion_gpr_load_p (operands, false)"

77422

+{

77423

+ return emit_fusion_gpr_load (operands);

77424

+}

77425

+ [(set_attr "type" "load")

77426

+ (set_attr "length" "8")])

77427

+

77428

+(define_peephole2

77429

+ [(set (match_operand:P 0 "base_reg_operand" "")

77430

+ (match_operand:P 1 "fusion_gpr_addis" ""))

77431

+ (set (match_operand:INT1 2 "base_reg_operand" "")

77432

+ (match_operand:INT1 3 "fusion_gpr_mem_load" ""))]

77433

+ "TARGET_P8_FUSION

77434

+ && (REGNO (operands[0]) != REGNO (operands[2])

77435

+ || GET_CODE (operands[3]) == SIGN_EXTEND)

77436

+ && fusion_gpr_load_p (operands, true)"

77437

+ [(const_int 0)]

77438

+{

77439

+ expand_fusion_gpr_load (operands);

77440

+ DONE;

77441

+})

77442

+

77443

+

77444

+;; Miscellaneous ISA 2.06 (power7) instructions

77445

+(define_insn "addg6s"

77446

+ [(set (match_operand:SI 0 "register_operand" "=r")

77447

+ (unspec:SI [(match_operand:SI 1 "register_operand" "r")

77448

+ (match_operand:SI 2 "register_operand" "r")]

77449

+ UNSPEC_ADDG6S))]

77450

+ "TARGET_POPCNTD"

77451

+ "addg6s %0,%1,%2"

77452

+ [(set_attr "type" "integer")

77453

+ (set_attr "length" "4")])

77454

+

77455

+(define_insn "cdtbcd"

77456

+ [(set (match_operand:SI 0 "register_operand" "=r")

77457

+ (unspec:SI [(match_operand:SI 1 "register_operand" "r")]

77458

+ UNSPEC_CDTBCD))]

77459

+ "TARGET_POPCNTD"

77460

+ "cdtbcd %0,%1"

77461

+ [(set_attr "type" "integer")

77462

+ (set_attr "length" "4")])

77463

+

77464

+(define_insn "cbcdtd"

77465

+ [(set (match_operand:SI 0 "register_operand" "=r")

77466

+ (unspec:SI [(match_operand:SI 1 "register_operand" "r")]

77467

+ UNSPEC_CBCDTD))]

77468

+ "TARGET_POPCNTD"

77469

+ "cbcdtd %0,%1"

77470

+ [(set_attr "type" "integer")

77471

+ (set_attr "length" "4")])

77472

+

77473

+(define_int_iterator UNSPEC_DIV_EXTEND [UNSPEC_DIVE

77474

+ UNSPEC_DIVEO

77475

+ UNSPEC_DIVEU

77476

+ UNSPEC_DIVEUO])

77477

+

77478

+(define_int_attr div_extend [(UNSPEC_DIVE "e")

77479

+ (UNSPEC_DIVEO "eo")

77480

+ (UNSPEC_DIVEU "eu")

77481

+ (UNSPEC_DIVEUO "euo")])

77482

+

77483

+(define_insn "div<div_extend>_<mode>"

77484

+ [(set (match_operand:GPR 0 "register_operand" "=r")

77485

+ (unspec:GPR [(match_operand:GPR 1 "register_operand" "r")

77486

+ (match_operand:GPR 2 "register_operand" "r")]

77487

+ UNSPEC_DIV_EXTEND))]

77488

+ "TARGET_POPCNTD"

77489

+ "div<wd><div_extend> %0,%1,%2"

77490

+ [(set_attr "type" "<idiv_ldiv>")])

77491

+

77492

+

77493

+;; Pack/unpack 128-bit floating point types that take 2 scalar registers

77494

+

77495

+; Type of the 64-bit part when packing/unpacking 128-bit floating point types

77496

+(define_mode_attr FP128_64 [(TF "DF") (TD "DI")])

77497

+

77498

+(define_expand "unpack<mode>"

77499

+ [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "")

77500

+ (unspec:<FP128_64>

77501

+ [(match_operand:FMOVE128 1 "register_operand" "")

77502

+ (match_operand:QI 2 "const_0_to_1_operand" "")]

77503

+ UNSPEC_UNPACK_128BIT))]

77504

+ ""

77505

+ "")

77506

+

77507

+;; The Advance Toolchain 7.0-3 added private builtins: __builtin_longdouble_dw0

77508

+;; and __builtin_longdouble_dw1 to optimize glibc. Add support for these

77509

+;; builtins here.

77510

+

77511

+(define_expand "unpacktf_0"

77512

+ [(set (match_operand:DF 0 "nonimmediate_operand" "")

77513

+ (unspec:DF [(match_operand:TF 1 "register_operand" "")

77514

+ (const_int 0)]

77515

+ UNSPEC_UNPACK_128BIT))]

77516

+ ""

77517

+ "")

77518

+

77519

+(define_expand "unpacktf_1"

77520

+ [(set (match_operand:DF 0 "nonimmediate_operand" "")

77521

+ (unspec:DF [(match_operand:TF 1 "register_operand" "")

77522

+ (const_int 1)]

77523

+ UNSPEC_UNPACK_128BIT))]

77524

+ ""

77525

+ "")

77526

+

77527

+(define_insn_and_split "unpack<mode>_dm"

77528

+ [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m,d,r,m")

77529

+ (unspec:<FP128_64>

77530

+ [(match_operand:FMOVE128 1 "register_operand" "d,d,r,d,r")

77531

+ (match_operand:QI 2 "const_0_to_1_operand" "i,i,i,i,i")]

77532

+ UNSPEC_UNPACK_128BIT))]

77533

+ "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"

77534

+ "#"

77535

+ "&& reload_completed"

77536

+ [(set (match_dup 0) (match_dup 3))]

77537

+{

77538

+ unsigned fp_regno = REGNO (operands[1]) + UINTVAL (operands[2]);

77539

+

77540

+ if (REG_P (operands[0]) && REGNO (operands[0]) == fp_regno)

77541

+ {

77542

+ emit_note (NOTE_INSN_DELETED);

77543

+ DONE;

77544

+ }

77545

+

77546

+ operands[3] = gen_rtx_REG (<FP128_64>mode, fp_regno);

77547

+}

77548

+ [(set_attr "type" "fp,fpstore,mffgpr,mftgpr,store")

77549

+ (set_attr "length" "4")])

77550

+

77551

+(define_insn_and_split "unpack<mode>_nodm"

77552

+ [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m")

77553

+ (unspec:<FP128_64>

77554

+ [(match_operand:FMOVE128 1 "register_operand" "d,d")

77555

+ (match_operand:QI 2 "const_0_to_1_operand" "i,i")]

77556

+ UNSPEC_UNPACK_128BIT))]

77557

+ "!TARGET_POWERPC64 || !TARGET_DIRECT_MOVE"

77558

+ "#"

77559

+ "&& reload_completed"

77560

+ [(set (match_dup 0) (match_dup 3))]

77561

+{

77562

+ unsigned fp_regno = REGNO (operands[1]) + UINTVAL (operands[2]);

77563

+

77564

+ if (REG_P (operands[0]) && REGNO (operands[0]) == fp_regno)

77565

+ {

77566

+ emit_note (NOTE_INSN_DELETED);

77567

+ DONE;

77568

+ }

77569

+

77570

+ operands[3] = gen_rtx_REG (<FP128_64>mode, fp_regno);

77571

+}

77572

+ [(set_attr "type" "fp,fpstore")

77573

+ (set_attr "length" "4")])

77574

+

77575

+(define_insn_and_split "pack<mode>"

77576

+ [(set (match_operand:FMOVE128 0 "register_operand" "=d,&d")

77577

+ (unspec:FMOVE128

77578

+ [(match_operand:<FP128_64> 1 "register_operand" "0,d")

77579

+ (match_operand:<FP128_64> 2 "register_operand" "d,d")]

77580

+ UNSPEC_PACK_128BIT))]

77581

+ ""

77582

+ "@

77583

+ fmr %L0,%2

77584

+ #"

77585

+ "&& reload_completed && REGNO (operands[0]) != REGNO (operands[1])"

77586

+ [(set (match_dup 3) (match_dup 1))

77587

+ (set (match_dup 4) (match_dup 2))]

77588

+{

77589

+ unsigned dest_hi = REGNO (operands[0]);

77590

+ unsigned dest_lo = dest_hi + 1;

77591

+

77592

+ gcc_assert (!IN_RANGE (REGNO (operands[1]), dest_hi, dest_lo));

77593

+ gcc_assert (!IN_RANGE (REGNO (operands[2]), dest_hi, dest_lo));

77594

+

77595

+ operands[3] = gen_rtx_REG (<FP128_64>mode, dest_hi);

77596

+ operands[4] = gen_rtx_REG (<FP128_64>mode, dest_lo);

77597

+}

77598

+ [(set_attr "type" "fp,fp")

77599

+ (set_attr "length" "4,8")])

77600

+

77601

+(define_insn "unpackv1ti"

77602

+ [(set (match_operand:DI 0 "register_operand" "=d,d")

77603

+ (unspec:DI [(match_operand:V1TI 1 "register_operand" "0,wa")

77604

+ (match_operand:QI 2 "const_0_to_1_operand" "O,i")]

77605

+ UNSPEC_UNPACK_128BIT))]

77606

+ "TARGET_VSX"

77607

+{

77608

+ if (REGNO (operands[0]) == REGNO (operands[1]) && INTVAL (operands[2]) == 0)

77609

+ return ASM_COMMENT_START " xxpermdi to same register";

77610

+

77611

+ operands[3] = GEN_INT (INTVAL (operands[2]) == 0 ? 0 : 3);

77612

+ return "xxpermdi %x0,%x1,%x1,%3";

77613

+}

77614

+ [(set_attr "type" "vecperm")

77615

+ (set_attr "length" "4")])

77616

+

77617

+(define_insn "packv1ti"

77618

+ [(set (match_operand:V1TI 0 "register_operand" "=wa")

77619

+ (unspec:V1TI

77620

+ [(match_operand:DI 1 "register_operand" "d")

77621

+ (match_operand:DI 2 "register_operand" "d")]

77622

+ UNSPEC_PACK_128BIT))]

77623

+ "TARGET_VSX"

77624

+ "xxpermdi %x0,%x1,%x2,0"

77625

+ [(set_attr "type" "vecperm")

77626

+ (set_attr "length" "4")])

77627

+

77628

+

77629

+

77630

(include "sync.md")

77631

(include "vector.md")

77632

(include "vsx.md")

77633

@@ -14028,3 +15977,5 @@

77634

(include "spe.md")

77635

(include "dfp.md")

77636

(include "paired.md")

77637

+(include "crypto.md")

77638

+(include "htm.md")

77639

Index: gcc/config/rs6000/t-linux64le

77640

===================================================================

77641

--- a/src/gcc/config/rs6000/t-linux64le (.../tags/gcc_4_8_2_release)

77642

+++ b/src/gcc/config/rs6000/t-linux64le (.../branches/gcc-4_8-branch)

77643

@@ -0,0 +1,3 @@

77644

+#rs6000/t-linux64le

77645

+

77646

+MULTILIB_OSDIRNAMES := $(subst -linux,le-linux,$(MULTILIB_OSDIRNAMES))

77647

Index: gcc/config/rs6000/t-linux64lebe

77648

===================================================================

77649

--- a/src/gcc/config/rs6000/t-linux64lebe (.../tags/gcc_4_8_2_release)

77650

+++ b/src/gcc/config/rs6000/t-linux64lebe (.../branches/gcc-4_8-branch)

77651

@@ -0,0 +1,7 @@

77652

+#rs6000/t-linux64leend

77653

+

77654

+MULTILIB_OPTIONS += mbig

77655

+MULTILIB_DIRNAMES += be

77656

+MULTILIB_OSDIRNAMES += $(subst =,.mbig=,$(subst libbe32,lib32be,$(subst libbe64,lib64be,$(subst lib,libbe,$(subst le-linux,-linux,$(MULTILIB_OSDIRNAMES))))))

77657

+MULTILIB_OSDIRNAMES += $(subst $(if $(findstring 64,$(target)),m64,m32).,,$(filter $(if $(findstring 64,$(target)),m64,m32).mbig%,$(MULTILIB_OSDIRNAMES)))

77658

+MULTILIB_MATCHES := ${MULTILIB_MATCHES_ENDIAN}

77659

Index: gcc/config/rs6000/rs6000-opts.h

77660

===================================================================

77661

--- a/src/gcc/config/rs6000/rs6000-opts.h (.../tags/gcc_4_8_2_release)

77662

+++ b/src/gcc/config/rs6000/rs6000-opts.h (.../branches/gcc-4_8-branch)

77663

@@ -59,7 +59,8 @@

77664

PROCESSOR_POWER7,

77665

PROCESSOR_CELL,

77666

PROCESSOR_PPCA2,

77667

- PROCESSOR_TITAN

77668

+ PROCESSOR_TITAN,

77669

+ PROCESSOR_POWER8

77670

};

77671

77672

/* FP processor type. */

77673

@@ -100,7 +101,8 @@

77674

/* Enumeration to give which calling sequence to use. */

77675

enum rs6000_abi {

77676

ABI_NONE,

77677

- ABI_AIX, /* IBM's AIX */

77678

+ ABI_AIX, /* IBM's AIX, or Linux ELFv1 */

77679

+ ABI_ELFv2, /* Linux ELFv2 ABI */

77680

ABI_V4, /* System V.4/eabi */

77681

ABI_DARWIN /* Apple's Darwin (OS X kernel) */

77682

};

77683

@@ -131,11 +133,14 @@

77684

CMODEL_LARGE

77685

};

77686

77687

-/* Describe which vector unit to use for a given machine mode. */

77688

+/* Describe which vector unit to use for a given machine mode. The

77689

+ VECTOR_MEM_* and VECTOR_UNIT_* macros assume that Altivec, VSX, and

77690

+ P8_VECTOR are contiguous. */

77691

enum rs6000_vector {

77692

VECTOR_NONE, /* Type is not a vector or not supported */

77693

VECTOR_ALTIVEC, /* Use altivec for vector processing */

77694

VECTOR_VSX, /* Use VSX for vector processing */

77695

+ VECTOR_P8_VECTOR, /* Use ISA 2.07 VSX for vector processing */

77696

VECTOR_PAIRED, /* Use paired floating point for vectors */

77697

VECTOR_SPE, /* Use SPE for vector processing */

77698

VECTOR_OTHER /* Some other vector unit */

77699

Index: gcc/config/rs6000/option-defaults.h

77700

===================================================================

77701

--- a/src/gcc/config/rs6000/option-defaults.h (.../tags/gcc_4_8_2_release)

77702

+++ b/src/gcc/config/rs6000/option-defaults.h (.../branches/gcc-4_8-branch)

77703

@@ -54,6 +54,7 @@

77704

--with-float is ignored if -mhard-float or -msoft-float are

77705

specified. */

77706

#define OPTION_DEFAULT_SPECS \

77707

+ {"abi", "%{!mabi=elfv*:-mabi=%(VALUE)}" }, \

77708

{"tune", "%{!mtune=*:%{!mcpu=*:-mtune=%(VALUE)}}" }, \

77709

{"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:-mtune=%(VALUE)}}}" }, \

77710

{"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:-mtune=%(VALUE)}}}" }, \

77711

Index: gcc/config/rs6000/altivec.h

77712

===================================================================

77713

--- a/src/gcc/config/rs6000/altivec.h (.../tags/gcc_4_8_2_release)

77714

+++ b/src/gcc/config/rs6000/altivec.h (.../branches/gcc-4_8-branch)

77715

@@ -319,8 +319,58 @@

77716

#define vec_sqrt __builtin_vec_sqrt

77717

#define vec_vsx_ld __builtin_vec_vsx_ld

77718

#define vec_vsx_st __builtin_vec_vsx_st

77719

+

77720

+/* Note, xxsldi and xxpermdi were added as __builtin_vsx_<xxx> functions

77721

+ instead of __builtin_vec_<xxx> */

77722

+#define vec_xxsldwi __builtin_vsx_xxsldwi

77723

+#define vec_xxpermdi __builtin_vsx_xxpermdi

77724

#endif

77725

77726

+#ifdef _ARCH_PWR8

77727

+/* Vector additions added in ISA 2.07. */

77728

+#define vec_eqv __builtin_vec_eqv

77729

+#define vec_nand __builtin_vec_nand

77730

+#define vec_orc __builtin_vec_orc

77731

+#define vec_vaddcuq __builtin_vec_vaddcuq

77732

+#define vec_vaddudm __builtin_vec_vaddudm

77733

+#define vec_vadduqm __builtin_vec_vadduqm

77734

+#define vec_vbpermq __builtin_vec_vbpermq

77735

+#define vec_vclz __builtin_vec_vclz

77736

+#define vec_vclzb __builtin_vec_vclzb

77737

+#define vec_vclzd __builtin_vec_vclzd

77738

+#define vec_vclzh __builtin_vec_vclzh

77739

+#define vec_vclzw __builtin_vec_vclzw

77740

+#define vec_vaddecuq __builtin_vec_vaddecuq

77741

+#define vec_vaddeuqm __builtin_vec_vaddeuqm

77742

+#define vec_vsubecuq __builtin_vec_vsubecuq

77743

+#define vec_vsubeuqm __builtin_vec_vsubeuqm

77744

+#define vec_vgbbd __builtin_vec_vgbbd

77745

+#define vec_vmaxsd __builtin_vec_vmaxsd

77746

+#define vec_vmaxud __builtin_vec_vmaxud

77747

+#define vec_vminsd __builtin_vec_vminsd

77748

+#define vec_vminud __builtin_vec_vminud

77749

+#define vec_vmrgew __builtin_vec_vmrgew

77750

+#define vec_vmrgow __builtin_vec_vmrgow

77751

+#define vec_vpksdss __builtin_vec_vpksdss

77752

+#define vec_vpksdus __builtin_vec_vpksdus

77753

+#define vec_vpkudum __builtin_vec_vpkudum

77754

+#define vec_vpkudus __builtin_vec_vpkudus

77755

+#define vec_vpopcnt __builtin_vec_vpopcnt

77756

+#define vec_vpopcntb __builtin_vec_vpopcntb

77757

+#define vec_vpopcntd __builtin_vec_vpopcntd

77758

+#define vec_vpopcnth __builtin_vec_vpopcnth

77759

+#define vec_vpopcntw __builtin_vec_vpopcntw

77760

+#define vec_vrld __builtin_vec_vrld

77761

+#define vec_vsld __builtin_vec_vsld

77762

+#define vec_vsrad __builtin_vec_vsrad

77763

+#define vec_vsrd __builtin_vec_vsrd

77764

+#define vec_vsubcuq __builtin_vec_vsubcuq

77765

+#define vec_vsubudm __builtin_vec_vsubudm

77766

+#define vec_vsubuqm __builtin_vec_vsubuqm

77767

+#define vec_vupkhsw __builtin_vec_vupkhsw

77768

+#define vec_vupklsw __builtin_vec_vupklsw

77769

+#endif

77770

+

77771

/* Predicates.

77772

For C++, we use templates in order to allow non-parenthesized arguments.

77773

For C, instead, we use macros since non-parenthesized arguments were

77774

Index: gcc/config/rs6000/sysv4.h

77775

===================================================================

77776

--- a/src/gcc/config/rs6000/sysv4.h (.../tags/gcc_4_8_2_release)

77777

+++ b/src/gcc/config/rs6000/sysv4.h (.../branches/gcc-4_8-branch)

77778

@@ -45,7 +45,7 @@

77779

& (OPTION_MASK_RELOCATABLE \

77780

| OPTION_MASK_MINIMAL_TOC)) \

77781

&& flag_pic > 1) \

77782

- || DEFAULT_ABI == ABI_AIX)

77783

+ || DEFAULT_ABI != ABI_V4)

77784

77785

#define TARGET_BITFIELD_TYPE (! TARGET_NO_BITFIELD_TYPE)

77786

#define TARGET_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN)

77787

@@ -147,7 +147,7 @@

77788

rs6000_sdata_name); \

77789

} \

77790

\

77791

- else if (flag_pic && DEFAULT_ABI != ABI_AIX \

77792

+ else if (flag_pic && DEFAULT_ABI == ABI_V4 \

77793

&& (rs6000_sdata == SDATA_EABI \

77794

|| rs6000_sdata == SDATA_SYSV)) \

77795

{ \

77796

@@ -173,7 +173,7 @@

77797

error ("-mrelocatable and -mno-minimal-toc are incompatible"); \

77798

} \

77799

\

77800

- if (TARGET_RELOCATABLE && rs6000_current_abi == ABI_AIX) \

77801

+ if (TARGET_RELOCATABLE && rs6000_current_abi != ABI_V4) \

77802

{ \

77803

rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE; \

77804

error ("-mrelocatable and -mcall-%s are incompatible", \

77805

@@ -180,7 +180,7 @@

77806

rs6000_abi_name); \

77807

} \

77808

\

77809

- if (!TARGET_64BIT && flag_pic > 1 && rs6000_current_abi == ABI_AIX) \

77810

+ if (!TARGET_64BIT && flag_pic > 1 && rs6000_current_abi != ABI_V4) \

77811

{ \

77812

flag_pic = 0; \

77813

error ("-fPIC and -mcall-%s are incompatible", \

77814

@@ -193,7 +193,7 @@

77815

} \

77816

\

77817

/* Treat -fPIC the same as -mrelocatable. */ \

77818

- if (flag_pic > 1 && DEFAULT_ABI != ABI_AIX) \

77819

+ if (flag_pic > 1 && DEFAULT_ABI == ABI_V4) \

77820

{ \

77821

rs6000_isa_flags |= OPTION_MASK_RELOCATABLE | OPTION_MASK_MINIMAL_TOC; \

77822

TARGET_NO_FP_IN_TOC = 1; \

77823

@@ -317,7 +317,7 @@

77824

77825

/* Put PC relative got entries in .got2. */

77826

#define MINIMAL_TOC_SECTION_ASM_OP \

77827

- (TARGET_RELOCATABLE || (flag_pic && DEFAULT_ABI != ABI_AIX) \

77828

+ (TARGET_RELOCATABLE || (flag_pic && DEFAULT_ABI == ABI_V4) \

77829

? "\t.section\t\".got2\",\"aw\"" : "\t.section\t\".got1\",\"aw\"")

77830

77831

#define SDATA_SECTION_ASM_OP "\t.section\t\".sdata\",\"aw\""

77832

@@ -522,8 +522,6 @@

77833

#define ENDIAN_SELECT(BIG_OPT, LITTLE_OPT, DEFAULT_OPT) \

77834

"%{mlittle|mlittle-endian:" LITTLE_OPT ";" \

77835

"mbig|mbig-endian:" BIG_OPT ";" \

77836

- "mcall-aixdesc|mcall-freebsd|mcall-netbsd|" \

77837

- "mcall-openbsd|mcall-linux:" BIG_OPT ";" \

77838

"mcall-i960-old:" LITTLE_OPT ";" \

77839

":" DEFAULT_OPT "}"

77840

77841

@@ -536,25 +534,12 @@

77842

%{memb|msdata=eabi: -memb}" \

77843

ENDIAN_SELECT(" -mbig", " -mlittle", DEFAULT_ASM_ENDIAN)

77844

77845

-#define CC1_ENDIAN_BIG_SPEC ""

77846

-

77847

-#define CC1_ENDIAN_LITTLE_SPEC "\

77848

-%{!mstrict-align: %{!mno-strict-align: \

77849

- %{!mcall-i960-old: \

77850

- -mstrict-align \

77851

- } \

77852

-}}"

77853

-

77854

-#define CC1_ENDIAN_DEFAULT_SPEC "%(cc1_endian_big)"

77855

-

77856

#ifndef CC1_SECURE_PLT_DEFAULT_SPEC

77857

#define CC1_SECURE_PLT_DEFAULT_SPEC ""

77858

#endif

77859

77860

-/* Pass -G xxx to the compiler and set correct endian mode. */

77861

+/* Pass -G xxx to the compiler. */

77862

#define CC1_SPEC "%{G*} %(cc1_cpu)" \

77863

- ENDIAN_SELECT(" %(cc1_endian_big)", " %(cc1_endian_little)", \

77864

- " %(cc1_endian_default)") \

77865

"%{meabi: %{!mcall-*: -mcall-sysv }} \

77866

%{!meabi: %{!mno-eabi: \

77867

%{mrelocatable: -meabi } \

77868

@@ -908,9 +893,6 @@

77869

{ "link_os_netbsd", LINK_OS_NETBSD_SPEC }, \

77870

{ "link_os_openbsd", LINK_OS_OPENBSD_SPEC }, \

77871

{ "link_os_default", LINK_OS_DEFAULT_SPEC }, \

77872

- { "cc1_endian_big", CC1_ENDIAN_BIG_SPEC }, \

77873

- { "cc1_endian_little", CC1_ENDIAN_LITTLE_SPEC }, \

77874

- { "cc1_endian_default", CC1_ENDIAN_DEFAULT_SPEC }, \

77875

{ "cc1_secure_plt_default", CC1_SECURE_PLT_DEFAULT_SPEC }, \

77876

{ "cpp_os_ads", CPP_OS_ADS_SPEC }, \

77877

{ "cpp_os_yellowknife", CPP_OS_YELLOWKNIFE_SPEC }, \

77878

Index: gcc/config/darwin.c

77879

===================================================================

77880

--- a/src/gcc/config/darwin.c (.../tags/gcc_4_8_2_release)

77881

+++ b/src/gcc/config/darwin.c (.../branches/gcc-4_8-branch)

77882

@@ -1329,6 +1329,9 @@

77883

return NULL_TREE;

77884

}

77885

77886

+static int classes_seen;

77887

+static int objc_metadata_seen;

77888

+

77889

/* Return the section required for Objective C ABI 2 metadata. */

77890

static section *

77891

darwin_objc2_section (tree decl ATTRIBUTE_UNUSED, tree meta, section * base)

77892

@@ -1338,12 +1341,9 @@

77893

gcc_assert (TREE_CODE (ident) == IDENTIFIER_NODE);

77894

p = IDENTIFIER_POINTER (ident);

77895

77896

- /* If we are in LTO, then we don't know the state of flag_next_runtime

77897

- or flag_objc_abi when the code was generated. We set these from the

77898

- meta-data - which is needed to deal with const string constructors. */

77899

+ gcc_checking_assert (flag_next_runtime == 1 && flag_objc_abi == 2);

77900

77901

- flag_next_runtime = 1;

77902

- flag_objc_abi = 2;

77903

+ objc_metadata_seen = 1;

77904

77905

if (base == data_section)

77906

base = darwin_sections[objc2_metadata_section];

77907

@@ -1366,7 +1366,10 @@

77908

else if (!strncmp (p, "V2_NLCL", 7))

77909

return darwin_sections[objc2_nonlazy_class_section];

77910

else if (!strncmp (p, "V2_CLAB", 7))

77911

- return darwin_sections[objc2_classlist_section];

77912

+ {

77913

+ classes_seen = 1;

77914

+ return darwin_sections[objc2_classlist_section];

77915

+ }

77916

else if (!strncmp (p, "V2_SRFS", 7))

77917

return darwin_sections[objc2_selector_refs_section];

77918

else if (!strncmp (p, "V2_NLCA", 7))

77919

@@ -1401,13 +1404,10 @@

77920

gcc_assert (TREE_CODE (ident) == IDENTIFIER_NODE);

77921

p = IDENTIFIER_POINTER (ident);

77922

77923

- /* If we are in LTO, then we don't know the state of flag_next_runtime

77924

- or flag_objc_abi when the code was generated. We set these from the

77925

- meta-data - which is needed to deal with const string constructors. */

77926

- flag_next_runtime = 1;

77927

- if (!global_options_set.x_flag_objc_abi)

77928

- flag_objc_abi = 1;

77929

+ gcc_checking_assert (flag_next_runtime == 1 && flag_objc_abi < 2);

77930

77931

+ objc_metadata_seen = 1;

77932

+

77933

/* String sections first, cos there are lots of strings. */

77934

if (!strncmp (p, "V1_STRG", 7))

77935

return darwin_sections[cstring_section];

77936

@@ -1419,7 +1419,10 @@

77937

return darwin_sections[objc_meth_var_types_section];

77938

77939

else if (!strncmp (p, "V1_CLAS", 7))

77940

- return darwin_sections[objc_class_section];

77941

+ {

77942

+ classes_seen = 1;

77943

+ return darwin_sections[objc_class_section];

77944

+ }

77945

else if (!strncmp (p, "V1_META", 7))

77946

return darwin_sections[objc_meta_class_section];

77947

else if (!strncmp (p, "V1_CATG", 7))

77948

@@ -1603,8 +1606,6 @@

77949

if (TREE_CODE (name) == TYPE_DECL)

77950

name = DECL_NAME (name);

77951

77952

- /* FIXME: This is unsatisfactory for LTO, since it relies on other

77953

- metadata determining the source FE. */

77954

if (!strcmp (IDENTIFIER_POINTER (name), "__builtin_ObjCString"))

77955

{

77956

if (flag_next_runtime)

77957

@@ -2845,6 +2846,33 @@

77958

finalize_ctors ();

77959

if (!vec_safe_is_empty (dtors))

77960

finalize_dtors ();

77961

+

77962

+ /* If we are expecting to output NeXT ObjC meta-data, (and we actually see

77963

+ some) then we output the fix-and-continue marker (Image Info).

77964

+ This applies to Objective C, Objective C++ and LTO with either language

77965

+ as part of the input. */

77966

+ if (flag_next_runtime && objc_metadata_seen)

77967

+ {

77968

+ unsigned int flags = 0;

77969

+ if (flag_objc_abi >= 2)

77970

+ {

77971

+ flags = 16;

77972

+ output_section_asm_op

77973

+ (darwin_sections[objc2_image_info_section]->unnamed.data);

77974

+ }

77975

+ else

77976

+ output_section_asm_op

77977

+ (darwin_sections[objc_image_info_section]->unnamed.data);

77978

+

77979

+ ASM_OUTPUT_ALIGN (asm_out_file, 2);

77980

+ fputs ("L_OBJC_ImageInfo:\n", asm_out_file);

77981

+

77982

+ flags |= (flag_replace_objc_classes && classes_seen) ? 1 : 0;

77983

+ flags |= flag_objc_gc ? 2 : 0;

77984

+

77985

+ fprintf (asm_out_file, "\t.long\t0\n\t.long\t%u\n", flags);

77986

+ }

77987

+

77988

machopic_finish (asm_out_file);

77989

if (strcmp (lang_hooks.name, "GNU C++") == 0)

77990

{

77991

Index: gcc/config/tilepro/tilepro-c.c

77992

===================================================================

77993

--- a/src/gcc/config/tilepro/tilepro-c.c (.../tags/gcc_4_8_2_release)

77994

+++ b/src/gcc/config/tilepro/tilepro-c.c (.../branches/gcc-4_8-branch)

77995

@@ -44,6 +44,11 @@

77996

builtin_define ("__tile_chip__=1");

77997

builtin_define ("__tile_chip_rev__=0");

77998

77999

+ builtin_define ("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");

78000

+ builtin_define ("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");

78001

+ builtin_define ("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");

78002

+ builtin_define ("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");

78003

+

78004

TILEPRO_CPU_CPP_ENDIAN_BUILTINS ();

78005

GNU_USER_TARGET_OS_CPP_BUILTINS ();

78006

}

78007

Index: gcc/config/tilepro/tilepro.c

78008

===================================================================

78009

--- a/src/gcc/config/tilepro/tilepro.c (.../tags/gcc_4_8_2_release)

78010

+++ b/src/gcc/config/tilepro/tilepro.c (.../branches/gcc-4_8-branch)

78011

@@ -3167,6 +3167,12 @@

78012

}

78013

if (!pat)

78014

return NULL_RTX;

78015

+

78016

+ /* If we are generating a prefetch, tell the scheduler not to move

78017

+ it around. */

78018

+ if (GET_CODE (pat) == PREFETCH)

78019

+ PREFETCH_SCHEDULE_BARRIER_P (pat) = true;

78020

+

78021

emit_insn (pat);

78022

78023

if (nonvoid)

78024

Index: gcc/config/tilepro/tilepro.md

78025

===================================================================

78026

--- a/src/gcc/config/tilepro/tilepro.md (.../tags/gcc_4_8_2_release)

78027

+++ b/src/gcc/config/tilepro/tilepro.md (.../branches/gcc-4_8-branch)

78028

@@ -795,7 +795,7 @@

78029

78030

(define_expand "ctzdi2"

78031

[(set (match_operand:DI 0 "register_operand" "")

78032

- (ctz:DI (match_operand:DI 1 "reg_or_0_operand" "")))]

78033

+ (ctz:DI (match_operand:DI 1 "register_operand" "")))]

78034

""

78035

{

78036

rtx lo, hi, ctz_lo, ctz_hi, ctz_hi_plus_32, result;

78037

@@ -823,7 +823,7 @@

78038

78039

(define_expand "clzdi2"

78040

[(set (match_operand:DI 0 "register_operand" "")

78041

- (clz:DI (match_operand:DI 1 "reg_or_0_operand" "")))]

78042

+ (clz:DI (match_operand:DI 1 "register_operand" "")))]

78043

""

78044

{

78045

rtx lo, hi, clz_lo, clz_hi, clz_lo_plus_32, result;

78046

@@ -851,7 +851,7 @@

78047

78048

(define_expand "ffsdi2"

78049

[(set (match_operand:DI 0 "register_operand" "")

78050

- (ffs:DI (match_operand:DI 1 "reg_or_0_operand" "")))]

78051

+ (ffs:DI (match_operand:DI 1 "register_operand" "")))]

78052

""

78053

{

78054

rtx lo, hi, ctz_lo, ctz_hi, ctz_hi_plus_32, ctz, ctz_plus_1,ctz_cond;

78055

Index: gcc/config/arm/arm.c

78056

===================================================================

78057

--- a/src/gcc/config/arm/arm.c (.../tags/gcc_4_8_2_release)

78058

+++ b/src/gcc/config/arm/arm.c (.../branches/gcc-4_8-branch)

78059

@@ -230,7 +230,6 @@

78060

static void arm_option_override (void);

78061

static unsigned HOST_WIDE_INT arm_shift_truncation_mask (enum machine_mode);

78062

static bool arm_cannot_copy_insn_p (rtx);

78063

-static bool arm_tls_symbol_p (rtx x);

78064

static int arm_issue_rate (void);

78065

static void arm_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;

78066

static bool arm_output_addr_const_extra (FILE *, rtx);

78067

@@ -5425,7 +5424,8 @@

78068

if (!crtl->uses_pic_offset_table)

78069

{

78070

gcc_assert (can_create_pseudo_p ());

78071

- if (arm_pic_register != INVALID_REGNUM)

78072

+ if (arm_pic_register != INVALID_REGNUM

78073

+ && !(TARGET_THUMB1 && arm_pic_register > LAST_LO_REGNUM))

78074

{

78075

if (!cfun->machine->pic_reg)

78076

cfun->machine->pic_reg = gen_rtx_REG (Pmode, arm_pic_register);

78077

@@ -5451,7 +5451,12 @@

78078

crtl->uses_pic_offset_table = 1;

78079

start_sequence ();

78080

78081

- arm_load_pic_register (0UL);

78082

+ if (TARGET_THUMB1 && arm_pic_register != INVALID_REGNUM

78083

+ && arm_pic_register > LAST_LO_REGNUM)

78084

+ emit_move_insn (cfun->machine->pic_reg,

78085

+ gen_rtx_REG (Pmode, arm_pic_register));

78086

+ else

78087

+ arm_load_pic_register (0UL);

78088

78089

seq = get_insns ();

78090

end_sequence ();

78091

@@ -5709,6 +5714,14 @@

78092

emit_insn (gen_movsi (pic_offset_table_rtx, pic_tmp));

78093

emit_insn (gen_pic_add_dot_plus_four (pic_reg, pic_reg, labelno));

78094

}

78095

+ else if (arm_pic_register != INVALID_REGNUM

78096

+ && arm_pic_register > LAST_LO_REGNUM

78097

+ && REGNO (pic_reg) <= LAST_LO_REGNUM)

78098

+ {

78099

+ emit_insn (gen_pic_load_addr_unified (pic_reg, pic_rtx, labelno));

78100

+ emit_move_insn (gen_rtx_REG (Pmode, arm_pic_register), pic_reg);

78101

+ emit_use (gen_rtx_REG (Pmode, arm_pic_register));

78102

+ }

78103

else

78104

emit_insn (gen_pic_load_addr_unified (pic_reg, pic_rtx, labelno));

78105

}

78106

@@ -6573,6 +6586,32 @@

78107

rtx

78108

arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)

78109

{

78110

+ if (arm_tls_referenced_p (x))

78111

+ {

78112

+ rtx addend = NULL;

78113

+

78114

+ if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS)

78115

+ {

78116

+ addend = XEXP (XEXP (x, 0), 1);

78117

+ x = XEXP (XEXP (x, 0), 0);

78118

+ }

78119

+

78120

+ if (GET_CODE (x) != SYMBOL_REF)

78121

+ return x;

78122

+

78123

+ gcc_assert (SYMBOL_REF_TLS_MODEL (x) != 0);

78124

+

78125

+ x = legitimize_tls_address (x, NULL_RTX);

78126

+

78127

+ if (addend)

78128

+ {

78129

+ x = gen_rtx_PLUS (SImode, x, addend);

78130

+ orig_x = x;

78131

+ }

78132

+ else

78133

+ return x;

78134

+ }

78135

+

78136

if (!TARGET_ARM)

78137

{

78138

/* TODO: legitimize_address for Thumb2. */

78139

@@ -6581,9 +6620,6 @@

78140

return thumb_legitimize_address (x, orig_x, mode);

78141

}

78142

78143

- if (arm_tls_symbol_p (x))

78144

- return legitimize_tls_address (x, NULL_RTX);

78145

-

78146

if (GET_CODE (x) == PLUS)

78147

{

78148

rtx xop0 = XEXP (x, 0);

78149

@@ -6695,9 +6731,6 @@

78150

rtx

78151

thumb_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)

78152

{

78153

- if (arm_tls_symbol_p (x))

78154

- return legitimize_tls_address (x, NULL_RTX);

78155

-

78156

if (GET_CODE (x) == PLUS

78157

&& CONST_INT_P (XEXP (x, 1))

78158

&& (INTVAL (XEXP (x, 1)) >= 32 * GET_MODE_SIZE (mode)

78159

@@ -6988,20 +7021,6 @@

78160

78161

/* Test for various thread-local symbols. */

78162

78163

-/* Return TRUE if X is a thread-local symbol. */

78164

-

78165

-static bool

78166

-arm_tls_symbol_p (rtx x)

78167

-{

78168

- if (! TARGET_HAVE_TLS)

78169

- return false;

78170

-

78171

- if (GET_CODE (x) != SYMBOL_REF)

78172

- return false;

78173

-

78174

- return SYMBOL_REF_TLS_MODEL (x) != 0;

78175

-}

78176

-

78177

/* Helper for arm_tls_referenced_p. */

78178

78179

static int

78180

@@ -21279,7 +21298,11 @@

78181

type_mode);

78182

}

78183

78184

- op[argc] = expand_normal (arg[argc]);

78185

+ /* Use EXPAND_MEMORY for NEON_ARG_MEMORY to ensure a MEM_P

78186

+ be returned. */

78187

+ op[argc] = expand_expr (arg[argc], NULL_RTX, VOIDmode,

78188

+ (thisarg == NEON_ARG_MEMORY

78189

+ ? EXPAND_MEMORY : EXPAND_NORMAL));

78190

78191

switch (thisarg)

78192

{

78193

@@ -21298,6 +21321,9 @@

78194

break;

78195

78196

case NEON_ARG_MEMORY:

78197

+ /* Check if expand failed. */

78198

+ if (op[argc] == const0_rtx)

78199

+ return 0;

78200

gcc_assert (MEM_P (op[argc]));

78201

PUT_MODE (op[argc], mode[argc]);

78202

/* ??? arm_neon.h uses the same built-in functions for signed

78203

@@ -23555,6 +23581,7 @@

78204

num_regs = bit_count (saved_regs_mask);

78205

if ((offsets->outgoing_args != (1 + num_regs)) || cfun->calls_alloca)

78206

{

78207

+ emit_insn (gen_blockage ());

78208

/* Unwind the stack to just below the saved registers. */

78209

emit_insn (gen_addsi3 (stack_pointer_rtx,

78210

hard_frame_pointer_rtx,

78211

@@ -23583,8 +23610,8 @@

78212

78213

if (crtl->calls_eh_return)

78214

emit_insn (gen_addsi3 (stack_pointer_rtx,

78215

- stack_pointer_rtx,

78216

- GEN_INT (ARM_EH_STACKADJ_REGNUM)));

78217

+ stack_pointer_rtx,

78218

+ gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)));

78219

78220

if (IS_STACKALIGN (func_type))

78221

/* Restore the original stack pointer. Before prologue, the stack was

78222

Index: gcc/config/arm/arm.h

78223

===================================================================

78224

--- a/src/gcc/config/arm/arm.h (.../tags/gcc_4_8_2_release)

78225

+++ b/src/gcc/config/arm/arm.h (.../branches/gcc-4_8-branch)

78226

@@ -1213,11 +1213,15 @@

78227

VFPv2.

78228

In big-endian mode, modes greater than word size (i.e. DFmode) are stored in

78229

VFP registers in little-endian order. We can't describe that accurately to

78230

- GCC, so avoid taking subregs of such values. */

78231

-#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \

78232

- (TARGET_VFP && TARGET_BIG_END \

78233

- && (GET_MODE_SIZE (FROM) > UNITS_PER_WORD \

78234

- || GET_MODE_SIZE (TO) > UNITS_PER_WORD) \

78235

+ GCC, so avoid taking subregs of such values.

78236

+ The only exception is going from a 128-bit to a 64-bit type. In that case

78237

+ the data layout happens to be consistent for big-endian, so we explicitly allow

78238

+ that case. */

78239

+#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \

78240

+ (TARGET_VFP && TARGET_BIG_END \

78241

+ && !(GET_MODE_SIZE (FROM) == 16 && GET_MODE_SIZE (TO) == 8) \

78242

+ && (GET_MODE_SIZE (FROM) > UNITS_PER_WORD \

78243

+ || GET_MODE_SIZE (TO) > UNITS_PER_WORD) \

78244

&& reg_classes_intersect_p (VFP_REGS, (CLASS)))

78245

78246

/* The class value for index registers, and the one for base regs. */

78247

Index: gcc/config/arm/vfp.md

78248

===================================================================

78249

--- a/src/gcc/config/arm/vfp.md (.../tags/gcc_4_8_2_release)

78250

+++ b/src/gcc/config/arm/vfp.md (.../branches/gcc-4_8-branch)

78251

@@ -1264,6 +1264,7 @@

78252

"TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>"

78253

"vrint<vrint_variant>%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1"

78254

[(set_attr "predicable" "<vrint_predicable>")

78255

+ (set_attr "conds" "<vrint_conds>")

78256

(set_attr "type" "f_rint<vfp_type>")]

78257

)

78258

78259

@@ -1280,7 +1281,8 @@

78260

(match_operand:SDF 2 "register_operand" "<F_constraint>")))]

78261

"TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>"

78262

"vmaxnm.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"

78263

- [(set_attr "type" "f_minmax<vfp_type>")]

78264

+ [(set_attr "type" "f_minmax<vfp_type>")

78265

+ (set_attr "conds" "unconditional")]

78266

)

78267

78268

(define_insn "smin<mode>3"

78269

@@ -1289,7 +1291,8 @@

78270

(match_operand:SDF 2 "register_operand" "<F_constraint>")))]

78271

"TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>"

78272

"vminnm.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"

78273

- [(set_attr "type" "f_minmax<vfp_type>")]

78274

+ [(set_attr "type" "f_minmax<vfp_type>")

78275

+ (set_attr "conds" "unconditional")]

78276

)

78277

78278

;; Unimplemented insns:

78279

Index: gcc/config/arm/ldmstm.md

78280

===================================================================

78281

--- a/src/gcc/config/arm/ldmstm.md (.../tags/gcc_4_8_2_release)

78282

+++ b/src/gcc/config/arm/ldmstm.md (.../branches/gcc-4_8-branch)

78283

@@ -23,15 +23,15 @@

78284

78285

(define_insn "*ldm4_ia"

78286

[(match_parallel 0 "load_multiple_operation"

78287

- [(set (match_operand:SI 1 "arm_hard_register_operand" "")

78288

+ [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")

78289

(mem:SI (match_operand:SI 5 "s_register_operand" "rk")))

78290

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78291

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

78292

(mem:SI (plus:SI (match_dup 5)

78293

(const_int 4))))

78294

- (set (match_operand:SI 3 "arm_hard_register_operand" "")

78295

+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")

78296

(mem:SI (plus:SI (match_dup 5)

78297

(const_int 8))))

78298

- (set (match_operand:SI 4 "arm_hard_register_operand" "")

78299

+ (set (match_operand:SI 4 "arm_hard_general_register_operand" "")

78300

(mem:SI (plus:SI (match_dup 5)

78301

(const_int 12))))])]

78302

"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"

78303

@@ -41,15 +41,15 @@

78304

78305

(define_insn "*thumb_ldm4_ia"

78306

[(match_parallel 0 "load_multiple_operation"

78307

- [(set (match_operand:SI 1 "arm_hard_register_operand" "")

78308

+ [(set (match_operand:SI 1 "low_register_operand" "")

78309

(mem:SI (match_operand:SI 5 "s_register_operand" "l")))

78310

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78311

+ (set (match_operand:SI 2 "low_register_operand" "")

78312

(mem:SI (plus:SI (match_dup 5)

78313

(const_int 4))))

78314

- (set (match_operand:SI 3 "arm_hard_register_operand" "")

78315

+ (set (match_operand:SI 3 "low_register_operand" "")

78316

(mem:SI (plus:SI (match_dup 5)

78317

(const_int 8))))

78318

- (set (match_operand:SI 4 "arm_hard_register_operand" "")

78319

+ (set (match_operand:SI 4 "low_register_operand" "")

78320

(mem:SI (plus:SI (match_dup 5)

78321

(const_int 12))))])]

78322

"TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4"

78323

@@ -60,15 +60,15 @@

78324

[(match_parallel 0 "load_multiple_operation"

78325

[(set (match_operand:SI 5 "s_register_operand" "+&rk")

78326

(plus:SI (match_dup 5) (const_int 16)))

78327

- (set (match_operand:SI 1 "arm_hard_register_operand" "")

78328

+ (set (match_operand:SI 1 "arm_hard_general_register_operand" "")

78329

(mem:SI (match_dup 5)))

78330

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78331

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

78332

(mem:SI (plus:SI (match_dup 5)

78333

(const_int 4))))

78334

- (set (match_operand:SI 3 "arm_hard_register_operand" "")

78335

+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")

78336

(mem:SI (plus:SI (match_dup 5)

78337

(const_int 8))))

78338

- (set (match_operand:SI 4 "arm_hard_register_operand" "")

78339

+ (set (match_operand:SI 4 "arm_hard_general_register_operand" "")

78340

(mem:SI (plus:SI (match_dup 5)

78341

(const_int 12))))])]

78342

"TARGET_32BIT && XVECLEN (operands[0], 0) == 5"

78343

@@ -80,15 +80,15 @@

78344

[(match_parallel 0 "load_multiple_operation"

78345

[(set (match_operand:SI 5 "s_register_operand" "+&l")

78346

(plus:SI (match_dup 5) (const_int 16)))

78347

- (set (match_operand:SI 1 "arm_hard_register_operand" "")

78348

+ (set (match_operand:SI 1 "low_register_operand" "")

78349

(mem:SI (match_dup 5)))

78350

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78351

+ (set (match_operand:SI 2 "low_register_operand" "")

78352

(mem:SI (plus:SI (match_dup 5)

78353

(const_int 4))))

78354

- (set (match_operand:SI 3 "arm_hard_register_operand" "")

78355

+ (set (match_operand:SI 3 "low_register_operand" "")

78356

(mem:SI (plus:SI (match_dup 5)

78357

(const_int 8))))

78358

- (set (match_operand:SI 4 "arm_hard_register_operand" "")

78359

+ (set (match_operand:SI 4 "low_register_operand" "")

78360

(mem:SI (plus:SI (match_dup 5)

78361

(const_int 12))))])]

78362

"TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5"

78363

@@ -98,13 +98,13 @@

78364

(define_insn "*stm4_ia"

78365

[(match_parallel 0 "store_multiple_operation"

78366

[(set (mem:SI (match_operand:SI 5 "s_register_operand" "rk"))

78367

- (match_operand:SI 1 "arm_hard_register_operand" ""))

78368

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

78369

(set (mem:SI (plus:SI (match_dup 5) (const_int 4)))

78370

- (match_operand:SI 2 "arm_hard_register_operand" ""))

78371

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))

78372

(set (mem:SI (plus:SI (match_dup 5) (const_int 8)))

78373

- (match_operand:SI 3 "arm_hard_register_operand" ""))

78374

+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))

78375

(set (mem:SI (plus:SI (match_dup 5) (const_int 12)))

78376

- (match_operand:SI 4 "arm_hard_register_operand" ""))])]

78377

+ (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]

78378

"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"

78379

"stm%(ia%)\t%5, {%1, %2, %3, %4}"

78380

[(set_attr "type" "store4")

78381

@@ -115,13 +115,13 @@

78382

[(set (match_operand:SI 5 "s_register_operand" "+&rk")

78383

(plus:SI (match_dup 5) (const_int 16)))

78384

(set (mem:SI (match_dup 5))

78385

- (match_operand:SI 1 "arm_hard_register_operand" ""))

78386

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

78387

(set (mem:SI (plus:SI (match_dup 5) (const_int 4)))

78388

- (match_operand:SI 2 "arm_hard_register_operand" ""))

78389

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))

78390

(set (mem:SI (plus:SI (match_dup 5) (const_int 8)))

78391

- (match_operand:SI 3 "arm_hard_register_operand" ""))

78392

+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))

78393

(set (mem:SI (plus:SI (match_dup 5) (const_int 12)))

78394

- (match_operand:SI 4 "arm_hard_register_operand" ""))])]

78395

+ (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]

78396

"TARGET_32BIT && XVECLEN (operands[0], 0) == 5"

78397

"stm%(ia%)\t%5!, {%1, %2, %3, %4}"

78398

[(set_attr "type" "store4")

78399

@@ -132,13 +132,13 @@

78400

[(set (match_operand:SI 5 "s_register_operand" "+&l")

78401

(plus:SI (match_dup 5) (const_int 16)))

78402

(set (mem:SI (match_dup 5))

78403

- (match_operand:SI 1 "arm_hard_register_operand" ""))

78404

+ (match_operand:SI 1 "low_register_operand" ""))

78405

(set (mem:SI (plus:SI (match_dup 5) (const_int 4)))

78406

- (match_operand:SI 2 "arm_hard_register_operand" ""))

78407

+ (match_operand:SI 2 "low_register_operand" ""))

78408

(set (mem:SI (plus:SI (match_dup 5) (const_int 8)))

78409

- (match_operand:SI 3 "arm_hard_register_operand" ""))

78410

+ (match_operand:SI 3 "low_register_operand" ""))

78411

(set (mem:SI (plus:SI (match_dup 5) (const_int 12)))

78412

- (match_operand:SI 4 "arm_hard_register_operand" ""))])]

78413

+ (match_operand:SI 4 "low_register_operand" ""))])]

78414

"TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5"

78415

"stm%(ia%)\t%5!, {%1, %2, %3, %4}"

78416

[(set_attr "type" "store4")])

78417

@@ -145,16 +145,16 @@

78418

78419

(define_insn "*ldm4_ib"

78420

[(match_parallel 0 "load_multiple_operation"

78421

- [(set (match_operand:SI 1 "arm_hard_register_operand" "")

78422

+ [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")

78423

(mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk")

78424

(const_int 4))))

78425

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78426

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

78427

(mem:SI (plus:SI (match_dup 5)

78428

(const_int 8))))

78429

- (set (match_operand:SI 3 "arm_hard_register_operand" "")

78430

+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")

78431

(mem:SI (plus:SI (match_dup 5)

78432

(const_int 12))))

78433

- (set (match_operand:SI 4 "arm_hard_register_operand" "")

78434

+ (set (match_operand:SI 4 "arm_hard_general_register_operand" "")

78435

(mem:SI (plus:SI (match_dup 5)

78436

(const_int 16))))])]

78437

"TARGET_ARM && XVECLEN (operands[0], 0) == 4"

78438

@@ -166,16 +166,16 @@

78439

[(match_parallel 0 "load_multiple_operation"

78440

[(set (match_operand:SI 5 "s_register_operand" "+&rk")

78441

(plus:SI (match_dup 5) (const_int 16)))

78442

- (set (match_operand:SI 1 "arm_hard_register_operand" "")

78443

+ (set (match_operand:SI 1 "arm_hard_general_register_operand" "")

78444

(mem:SI (plus:SI (match_dup 5)

78445

(const_int 4))))

78446

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78447

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

78448

(mem:SI (plus:SI (match_dup 5)

78449

(const_int 8))))

78450

- (set (match_operand:SI 3 "arm_hard_register_operand" "")

78451

+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")

78452

(mem:SI (plus:SI (match_dup 5)

78453

(const_int 12))))

78454

- (set (match_operand:SI 4 "arm_hard_register_operand" "")

78455

+ (set (match_operand:SI 4 "arm_hard_general_register_operand" "")

78456

(mem:SI (plus:SI (match_dup 5)

78457

(const_int 16))))])]

78458

"TARGET_ARM && XVECLEN (operands[0], 0) == 5"

78459

@@ -186,13 +186,13 @@

78460

(define_insn "*stm4_ib"

78461

[(match_parallel 0 "store_multiple_operation"

78462

[(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int 4)))

78463

- (match_operand:SI 1 "arm_hard_register_operand" ""))

78464

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

78465

(set (mem:SI (plus:SI (match_dup 5) (const_int 8)))

78466

- (match_operand:SI 2 "arm_hard_register_operand" ""))

78467

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))

78468

(set (mem:SI (plus:SI (match_dup 5) (const_int 12)))

78469

- (match_operand:SI 3 "arm_hard_register_operand" ""))

78470

+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))

78471

(set (mem:SI (plus:SI (match_dup 5) (const_int 16)))

78472

- (match_operand:SI 4 "arm_hard_register_operand" ""))])]

78473

+ (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]

78474

"TARGET_ARM && XVECLEN (operands[0], 0) == 4"

78475

"stm%(ib%)\t%5, {%1, %2, %3, %4}"

78476

[(set_attr "type" "store4")

78477

@@ -203,13 +203,13 @@

78478

[(set (match_operand:SI 5 "s_register_operand" "+&rk")

78479

(plus:SI (match_dup 5) (const_int 16)))

78480

(set (mem:SI (plus:SI (match_dup 5) (const_int 4)))

78481

- (match_operand:SI 1 "arm_hard_register_operand" ""))

78482

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

78483

(set (mem:SI (plus:SI (match_dup 5) (const_int 8)))

78484

- (match_operand:SI 2 "arm_hard_register_operand" ""))

78485

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))

78486

(set (mem:SI (plus:SI (match_dup 5) (const_int 12)))

78487

- (match_operand:SI 3 "arm_hard_register_operand" ""))

78488

+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))

78489

(set (mem:SI (plus:SI (match_dup 5) (const_int 16)))

78490

- (match_operand:SI 4 "arm_hard_register_operand" ""))])]

78491

+ (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]

78492

"TARGET_ARM && XVECLEN (operands[0], 0) == 5"

78493

"stm%(ib%)\t%5!, {%1, %2, %3, %4}"

78494

[(set_attr "type" "store4")

78495

@@ -217,16 +217,16 @@

78496

78497

(define_insn "*ldm4_da"

78498

[(match_parallel 0 "load_multiple_operation"

78499

- [(set (match_operand:SI 1 "arm_hard_register_operand" "")

78500

+ [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")

78501

(mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk")

78502

(const_int -12))))

78503

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78504

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

78505

(mem:SI (plus:SI (match_dup 5)

78506

(const_int -8))))

78507

- (set (match_operand:SI 3 "arm_hard_register_operand" "")

78508

+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")

78509

(mem:SI (plus:SI (match_dup 5)

78510

(const_int -4))))

78511

- (set (match_operand:SI 4 "arm_hard_register_operand" "")

78512

+ (set (match_operand:SI 4 "arm_hard_general_register_operand" "")

78513

(mem:SI (match_dup 5)))])]

78514

"TARGET_ARM && XVECLEN (operands[0], 0) == 4"

78515

"ldm%(da%)\t%5, {%1, %2, %3, %4}"

78516

@@ -237,16 +237,16 @@

78517

[(match_parallel 0 "load_multiple_operation"

78518

[(set (match_operand:SI 5 "s_register_operand" "+&rk")

78519

(plus:SI (match_dup 5) (const_int -16)))

78520

- (set (match_operand:SI 1 "arm_hard_register_operand" "")

78521

+ (set (match_operand:SI 1 "arm_hard_general_register_operand" "")

78522

(mem:SI (plus:SI (match_dup 5)

78523

(const_int -12))))

78524

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78525

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

78526

(mem:SI (plus:SI (match_dup 5)

78527

(const_int -8))))

78528

- (set (match_operand:SI 3 "arm_hard_register_operand" "")

78529

+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")

78530

(mem:SI (plus:SI (match_dup 5)

78531

(const_int -4))))

78532

- (set (match_operand:SI 4 "arm_hard_register_operand" "")

78533

+ (set (match_operand:SI 4 "arm_hard_general_register_operand" "")

78534

(mem:SI (match_dup 5)))])]

78535

"TARGET_ARM && XVECLEN (operands[0], 0) == 5"

78536

"ldm%(da%)\t%5!, {%1, %2, %3, %4}"

78537

@@ -256,13 +256,13 @@

78538

(define_insn "*stm4_da"

78539

[(match_parallel 0 "store_multiple_operation"

78540

[(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int -12)))

78541

- (match_operand:SI 1 "arm_hard_register_operand" ""))

78542

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

78543

(set (mem:SI (plus:SI (match_dup 5) (const_int -8)))

78544

- (match_operand:SI 2 "arm_hard_register_operand" ""))

78545

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))

78546

(set (mem:SI (plus:SI (match_dup 5) (const_int -4)))

78547

- (match_operand:SI 3 "arm_hard_register_operand" ""))

78548

+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))

78549

(set (mem:SI (match_dup 5))

78550

- (match_operand:SI 4 "arm_hard_register_operand" ""))])]

78551

+ (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]

78552

"TARGET_ARM && XVECLEN (operands[0], 0) == 4"

78553

"stm%(da%)\t%5, {%1, %2, %3, %4}"

78554

[(set_attr "type" "store4")

78555

@@ -273,13 +273,13 @@

78556

[(set (match_operand:SI 5 "s_register_operand" "+&rk")

78557

(plus:SI (match_dup 5) (const_int -16)))

78558

(set (mem:SI (plus:SI (match_dup 5) (const_int -12)))

78559

- (match_operand:SI 1 "arm_hard_register_operand" ""))

78560

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

78561

(set (mem:SI (plus:SI (match_dup 5) (const_int -8)))

78562

- (match_operand:SI 2 "arm_hard_register_operand" ""))

78563

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))

78564

(set (mem:SI (plus:SI (match_dup 5) (const_int -4)))

78565

- (match_operand:SI 3 "arm_hard_register_operand" ""))

78566

+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))

78567

(set (mem:SI (match_dup 5))

78568

- (match_operand:SI 4 "arm_hard_register_operand" ""))])]

78569

+ (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]

78570

"TARGET_ARM && XVECLEN (operands[0], 0) == 5"

78571

"stm%(da%)\t%5!, {%1, %2, %3, %4}"

78572

[(set_attr "type" "store4")

78573

@@ -287,16 +287,16 @@

78574

78575

(define_insn "*ldm4_db"

78576

[(match_parallel 0 "load_multiple_operation"

78577

- [(set (match_operand:SI 1 "arm_hard_register_operand" "")

78578

+ [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")

78579

(mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk")

78580

(const_int -16))))

78581

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78582

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

78583

(mem:SI (plus:SI (match_dup 5)

78584

(const_int -12))))

78585

- (set (match_operand:SI 3 "arm_hard_register_operand" "")

78586

+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")

78587

(mem:SI (plus:SI (match_dup 5)

78588

(const_int -8))))

78589

- (set (match_operand:SI 4 "arm_hard_register_operand" "")

78590

+ (set (match_operand:SI 4 "arm_hard_general_register_operand" "")

78591

(mem:SI (plus:SI (match_dup 5)

78592

(const_int -4))))])]

78593

"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"

78594

@@ -308,16 +308,16 @@

78595

[(match_parallel 0 "load_multiple_operation"

78596

[(set (match_operand:SI 5 "s_register_operand" "+&rk")

78597

(plus:SI (match_dup 5) (const_int -16)))

78598

- (set (match_operand:SI 1 "arm_hard_register_operand" "")

78599

+ (set (match_operand:SI 1 "arm_hard_general_register_operand" "")

78600

(mem:SI (plus:SI (match_dup 5)

78601

(const_int -16))))

78602

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78603

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

78604

(mem:SI (plus:SI (match_dup 5)

78605

(const_int -12))))

78606

- (set (match_operand:SI 3 "arm_hard_register_operand" "")

78607

+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")

78608

(mem:SI (plus:SI (match_dup 5)

78609

(const_int -8))))

78610

- (set (match_operand:SI 4 "arm_hard_register_operand" "")

78611

+ (set (match_operand:SI 4 "arm_hard_general_register_operand" "")

78612

(mem:SI (plus:SI (match_dup 5)

78613

(const_int -4))))])]

78614

"TARGET_32BIT && XVECLEN (operands[0], 0) == 5"

78615

@@ -328,13 +328,13 @@

78616

(define_insn "*stm4_db"

78617

[(match_parallel 0 "store_multiple_operation"

78618

[(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int -16)))

78619

- (match_operand:SI 1 "arm_hard_register_operand" ""))

78620

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

78621

(set (mem:SI (plus:SI (match_dup 5) (const_int -12)))

78622

- (match_operand:SI 2 "arm_hard_register_operand" ""))

78623

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))

78624

(set (mem:SI (plus:SI (match_dup 5) (const_int -8)))

78625

- (match_operand:SI 3 "arm_hard_register_operand" ""))

78626

+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))

78627

(set (mem:SI (plus:SI (match_dup 5) (const_int -4)))

78628

- (match_operand:SI 4 "arm_hard_register_operand" ""))])]

78629

+ (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]

78630

"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"

78631

"stm%(db%)\t%5, {%1, %2, %3, %4}"

78632

[(set_attr "type" "store4")

78633

@@ -345,13 +345,13 @@

78634

[(set (match_operand:SI 5 "s_register_operand" "+&rk")

78635

(plus:SI (match_dup 5) (const_int -16)))

78636

(set (mem:SI (plus:SI (match_dup 5) (const_int -16)))

78637

- (match_operand:SI 1 "arm_hard_register_operand" ""))

78638

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

78639

(set (mem:SI (plus:SI (match_dup 5) (const_int -12)))

78640

- (match_operand:SI 2 "arm_hard_register_operand" ""))

78641

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))

78642

(set (mem:SI (plus:SI (match_dup 5) (const_int -8)))

78643

- (match_operand:SI 3 "arm_hard_register_operand" ""))

78644

+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))

78645

(set (mem:SI (plus:SI (match_dup 5) (const_int -4)))

78646

- (match_operand:SI 4 "arm_hard_register_operand" ""))])]

78647

+ (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]

78648

"TARGET_32BIT && XVECLEN (operands[0], 0) == 5"

78649

"stm%(db%)\t%5!, {%1, %2, %3, %4}"

78650

[(set_attr "type" "store4")

78651

@@ -466,12 +466,12 @@

78652

78653

(define_insn "*ldm3_ia"

78654

[(match_parallel 0 "load_multiple_operation"

78655

- [(set (match_operand:SI 1 "arm_hard_register_operand" "")

78656

+ [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")

78657

(mem:SI (match_operand:SI 4 "s_register_operand" "rk")))

78658

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78659

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

78660

(mem:SI (plus:SI (match_dup 4)

78661

(const_int 4))))

78662

- (set (match_operand:SI 3 "arm_hard_register_operand" "")

78663

+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")

78664

(mem:SI (plus:SI (match_dup 4)

78665

(const_int 8))))])]

78666

"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"

78667

@@ -481,12 +481,12 @@

78668

78669

(define_insn "*thumb_ldm3_ia"

78670

[(match_parallel 0 "load_multiple_operation"

78671

- [(set (match_operand:SI 1 "arm_hard_register_operand" "")

78672

+ [(set (match_operand:SI 1 "low_register_operand" "")

78673

(mem:SI (match_operand:SI 4 "s_register_operand" "l")))

78674

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78675

+ (set (match_operand:SI 2 "low_register_operand" "")

78676

(mem:SI (plus:SI (match_dup 4)

78677

(const_int 4))))

78678

- (set (match_operand:SI 3 "arm_hard_register_operand" "")

78679

+ (set (match_operand:SI 3 "low_register_operand" "")

78680

(mem:SI (plus:SI (match_dup 4)

78681

(const_int 8))))])]

78682

"TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3"

78683

@@ -497,12 +497,12 @@

78684

[(match_parallel 0 "load_multiple_operation"

78685

[(set (match_operand:SI 4 "s_register_operand" "+&rk")

78686

(plus:SI (match_dup 4) (const_int 12)))

78687

- (set (match_operand:SI 1 "arm_hard_register_operand" "")

78688

+ (set (match_operand:SI 1 "arm_hard_general_register_operand" "")

78689

(mem:SI (match_dup 4)))

78690

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78691

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

78692

(mem:SI (plus:SI (match_dup 4)

78693

(const_int 4))))

78694

- (set (match_operand:SI 3 "arm_hard_register_operand" "")

78695

+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")

78696

(mem:SI (plus:SI (match_dup 4)

78697

(const_int 8))))])]

78698

"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"

78699

@@ -514,12 +514,12 @@

78700

[(match_parallel 0 "load_multiple_operation"

78701

[(set (match_operand:SI 4 "s_register_operand" "+&l")

78702

(plus:SI (match_dup 4) (const_int 12)))

78703

- (set (match_operand:SI 1 "arm_hard_register_operand" "")

78704

+ (set (match_operand:SI 1 "low_register_operand" "")

78705

(mem:SI (match_dup 4)))

78706

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78707

+ (set (match_operand:SI 2 "low_register_operand" "")

78708

(mem:SI (plus:SI (match_dup 4)

78709

(const_int 4))))

78710

- (set (match_operand:SI 3 "arm_hard_register_operand" "")

78711

+ (set (match_operand:SI 3 "low_register_operand" "")

78712

(mem:SI (plus:SI (match_dup 4)

78713

(const_int 8))))])]

78714

"TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4"

78715

@@ -529,11 +529,11 @@

78716

(define_insn "*stm3_ia"

78717

[(match_parallel 0 "store_multiple_operation"

78718

[(set (mem:SI (match_operand:SI 4 "s_register_operand" "rk"))

78719

- (match_operand:SI 1 "arm_hard_register_operand" ""))

78720

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

78721

(set (mem:SI (plus:SI (match_dup 4) (const_int 4)))

78722

- (match_operand:SI 2 "arm_hard_register_operand" ""))

78723

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))

78724

(set (mem:SI (plus:SI (match_dup 4) (const_int 8)))

78725

- (match_operand:SI 3 "arm_hard_register_operand" ""))])]

78726

+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]

78727

"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"

78728

"stm%(ia%)\t%4, {%1, %2, %3}"

78729

[(set_attr "type" "store3")

78730

@@ -544,11 +544,11 @@

78731

[(set (match_operand:SI 4 "s_register_operand" "+&rk")

78732

(plus:SI (match_dup 4) (const_int 12)))

78733

(set (mem:SI (match_dup 4))

78734

- (match_operand:SI 1 "arm_hard_register_operand" ""))

78735

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

78736

(set (mem:SI (plus:SI (match_dup 4) (const_int 4)))

78737

- (match_operand:SI 2 "arm_hard_register_operand" ""))

78738

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))

78739

(set (mem:SI (plus:SI (match_dup 4) (const_int 8)))

78740

- (match_operand:SI 3 "arm_hard_register_operand" ""))])]

78741

+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]

78742

"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"

78743

"stm%(ia%)\t%4!, {%1, %2, %3}"

78744

[(set_attr "type" "store3")

78745

@@ -559,11 +559,11 @@

78746

[(set (match_operand:SI 4 "s_register_operand" "+&l")

78747

(plus:SI (match_dup 4) (const_int 12)))

78748

(set (mem:SI (match_dup 4))

78749

- (match_operand:SI 1 "arm_hard_register_operand" ""))

78750

+ (match_operand:SI 1 "low_register_operand" ""))

78751

(set (mem:SI (plus:SI (match_dup 4) (const_int 4)))

78752

- (match_operand:SI 2 "arm_hard_register_operand" ""))

78753

+ (match_operand:SI 2 "low_register_operand" ""))

78754

(set (mem:SI (plus:SI (match_dup 4) (const_int 8)))

78755

- (match_operand:SI 3 "arm_hard_register_operand" ""))])]

78756

+ (match_operand:SI 3 "low_register_operand" ""))])]

78757

"TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4"

78758

"stm%(ia%)\t%4!, {%1, %2, %3}"

78759

[(set_attr "type" "store3")])

78760

@@ -570,13 +570,13 @@

78761

78762

(define_insn "*ldm3_ib"

78763

[(match_parallel 0 "load_multiple_operation"

78764

- [(set (match_operand:SI 1 "arm_hard_register_operand" "")

78765

+ [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")

78766

(mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk")

78767

(const_int 4))))

78768

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78769

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

78770

(mem:SI (plus:SI (match_dup 4)

78771

(const_int 8))))

78772

- (set (match_operand:SI 3 "arm_hard_register_operand" "")

78773

+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")

78774

(mem:SI (plus:SI (match_dup 4)

78775

(const_int 12))))])]

78776

"TARGET_ARM && XVECLEN (operands[0], 0) == 3"

78777

@@ -588,13 +588,13 @@

78778

[(match_parallel 0 "load_multiple_operation"

78779

[(set (match_operand:SI 4 "s_register_operand" "+&rk")

78780

(plus:SI (match_dup 4) (const_int 12)))

78781

- (set (match_operand:SI 1 "arm_hard_register_operand" "")

78782

+ (set (match_operand:SI 1 "arm_hard_general_register_operand" "")

78783

(mem:SI (plus:SI (match_dup 4)

78784

(const_int 4))))

78785

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78786

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

78787

(mem:SI (plus:SI (match_dup 4)

78788

(const_int 8))))

78789

- (set (match_operand:SI 3 "arm_hard_register_operand" "")

78790

+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")

78791

(mem:SI (plus:SI (match_dup 4)

78792

(const_int 12))))])]

78793

"TARGET_ARM && XVECLEN (operands[0], 0) == 4"

78794

@@ -605,11 +605,11 @@

78795

(define_insn "*stm3_ib"

78796

[(match_parallel 0 "store_multiple_operation"

78797

[(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int 4)))

78798

- (match_operand:SI 1 "arm_hard_register_operand" ""))

78799

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

78800

(set (mem:SI (plus:SI (match_dup 4) (const_int 8)))

78801

- (match_operand:SI 2 "arm_hard_register_operand" ""))

78802

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))

78803

(set (mem:SI (plus:SI (match_dup 4) (const_int 12)))

78804

- (match_operand:SI 3 "arm_hard_register_operand" ""))])]

78805

+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]

78806

"TARGET_ARM && XVECLEN (operands[0], 0) == 3"

78807

"stm%(ib%)\t%4, {%1, %2, %3}"

78808

[(set_attr "type" "store3")

78809

@@ -620,11 +620,11 @@

78810

[(set (match_operand:SI 4 "s_register_operand" "+&rk")

78811

(plus:SI (match_dup 4) (const_int 12)))

78812

(set (mem:SI (plus:SI (match_dup 4) (const_int 4)))

78813

- (match_operand:SI 1 "arm_hard_register_operand" ""))

78814

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

78815

(set (mem:SI (plus:SI (match_dup 4) (const_int 8)))

78816

- (match_operand:SI 2 "arm_hard_register_operand" ""))

78817

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))

78818

(set (mem:SI (plus:SI (match_dup 4) (const_int 12)))

78819

- (match_operand:SI 3 "arm_hard_register_operand" ""))])]

78820

+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]

78821

"TARGET_ARM && XVECLEN (operands[0], 0) == 4"

78822

"stm%(ib%)\t%4!, {%1, %2, %3}"

78823

[(set_attr "type" "store3")

78824

@@ -632,13 +632,13 @@

78825

78826

(define_insn "*ldm3_da"

78827

[(match_parallel 0 "load_multiple_operation"

78828

- [(set (match_operand:SI 1 "arm_hard_register_operand" "")

78829

+ [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")

78830

(mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk")

78831

(const_int -8))))

78832

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78833

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

78834

(mem:SI (plus:SI (match_dup 4)

78835

(const_int -4))))

78836

- (set (match_operand:SI 3 "arm_hard_register_operand" "")

78837

+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")

78838

(mem:SI (match_dup 4)))])]

78839

"TARGET_ARM && XVECLEN (operands[0], 0) == 3"

78840

"ldm%(da%)\t%4, {%1, %2, %3}"

78841

@@ -649,13 +649,13 @@

78842

[(match_parallel 0 "load_multiple_operation"

78843

[(set (match_operand:SI 4 "s_register_operand" "+&rk")

78844

(plus:SI (match_dup 4) (const_int -12)))

78845

- (set (match_operand:SI 1 "arm_hard_register_operand" "")

78846

+ (set (match_operand:SI 1 "arm_hard_general_register_operand" "")

78847

(mem:SI (plus:SI (match_dup 4)

78848

(const_int -8))))

78849

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78850

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

78851

(mem:SI (plus:SI (match_dup 4)

78852

(const_int -4))))

78853

- (set (match_operand:SI 3 "arm_hard_register_operand" "")

78854

+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")

78855

(mem:SI (match_dup 4)))])]

78856

"TARGET_ARM && XVECLEN (operands[0], 0) == 4"

78857

"ldm%(da%)\t%4!, {%1, %2, %3}"

78858

@@ -665,11 +665,11 @@

78859

(define_insn "*stm3_da"

78860

[(match_parallel 0 "store_multiple_operation"

78861

[(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int -8)))

78862

- (match_operand:SI 1 "arm_hard_register_operand" ""))

78863

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

78864

(set (mem:SI (plus:SI (match_dup 4) (const_int -4)))

78865

- (match_operand:SI 2 "arm_hard_register_operand" ""))

78866

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))

78867

(set (mem:SI (match_dup 4))

78868

- (match_operand:SI 3 "arm_hard_register_operand" ""))])]

78869

+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]

78870

"TARGET_ARM && XVECLEN (operands[0], 0) == 3"

78871

"stm%(da%)\t%4, {%1, %2, %3}"

78872

[(set_attr "type" "store3")

78873

@@ -680,11 +680,11 @@

78874

[(set (match_operand:SI 4 "s_register_operand" "+&rk")

78875

(plus:SI (match_dup 4) (const_int -12)))

78876

(set (mem:SI (plus:SI (match_dup 4) (const_int -8)))

78877

- (match_operand:SI 1 "arm_hard_register_operand" ""))

78878

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

78879

(set (mem:SI (plus:SI (match_dup 4) (const_int -4)))

78880

- (match_operand:SI 2 "arm_hard_register_operand" ""))

78881

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))

78882

(set (mem:SI (match_dup 4))

78883

- (match_operand:SI 3 "arm_hard_register_operand" ""))])]

78884

+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]

78885

"TARGET_ARM && XVECLEN (operands[0], 0) == 4"

78886

"stm%(da%)\t%4!, {%1, %2, %3}"

78887

[(set_attr "type" "store3")

78888

@@ -692,13 +692,13 @@

78889

78890

(define_insn "*ldm3_db"

78891

[(match_parallel 0 "load_multiple_operation"

78892

- [(set (match_operand:SI 1 "arm_hard_register_operand" "")

78893

+ [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")

78894

(mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk")

78895

(const_int -12))))

78896

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78897

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

78898

(mem:SI (plus:SI (match_dup 4)

78899

(const_int -8))))

78900

- (set (match_operand:SI 3 "arm_hard_register_operand" "")

78901

+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")

78902

(mem:SI (plus:SI (match_dup 4)

78903

(const_int -4))))])]

78904

"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"

78905

@@ -710,13 +710,13 @@

78906

[(match_parallel 0 "load_multiple_operation"

78907

[(set (match_operand:SI 4 "s_register_operand" "+&rk")

78908

(plus:SI (match_dup 4) (const_int -12)))

78909

- (set (match_operand:SI 1 "arm_hard_register_operand" "")

78910

+ (set (match_operand:SI 1 "arm_hard_general_register_operand" "")

78911

(mem:SI (plus:SI (match_dup 4)

78912

(const_int -12))))

78913

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78914

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

78915

(mem:SI (plus:SI (match_dup 4)

78916

(const_int -8))))

78917

- (set (match_operand:SI 3 "arm_hard_register_operand" "")

78918

+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")

78919

(mem:SI (plus:SI (match_dup 4)

78920

(const_int -4))))])]

78921

"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"

78922

@@ -727,11 +727,11 @@

78923

(define_insn "*stm3_db"

78924

[(match_parallel 0 "store_multiple_operation"

78925

[(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int -12)))

78926

- (match_operand:SI 1 "arm_hard_register_operand" ""))

78927

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

78928

(set (mem:SI (plus:SI (match_dup 4) (const_int -8)))

78929

- (match_operand:SI 2 "arm_hard_register_operand" ""))

78930

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))

78931

(set (mem:SI (plus:SI (match_dup 4) (const_int -4)))

78932

- (match_operand:SI 3 "arm_hard_register_operand" ""))])]

78933

+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]

78934

"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"

78935

"stm%(db%)\t%4, {%1, %2, %3}"

78936

[(set_attr "type" "store3")

78937

@@ -742,11 +742,11 @@

78938

[(set (match_operand:SI 4 "s_register_operand" "+&rk")

78939

(plus:SI (match_dup 4) (const_int -12)))

78940

(set (mem:SI (plus:SI (match_dup 4) (const_int -12)))

78941

- (match_operand:SI 1 "arm_hard_register_operand" ""))

78942

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

78943

(set (mem:SI (plus:SI (match_dup 4) (const_int -8)))

78944

- (match_operand:SI 2 "arm_hard_register_operand" ""))

78945

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))

78946

(set (mem:SI (plus:SI (match_dup 4) (const_int -4)))

78947

- (match_operand:SI 3 "arm_hard_register_operand" ""))])]

78948

+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]

78949

"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"

78950

"stm%(db%)\t%4!, {%1, %2, %3}"

78951

[(set_attr "type" "store3")

78952

@@ -847,9 +847,9 @@

78953

78954

(define_insn "*ldm2_ia"

78955

[(match_parallel 0 "load_multiple_operation"

78956

- [(set (match_operand:SI 1 "arm_hard_register_operand" "")

78957

+ [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")

78958

(mem:SI (match_operand:SI 3 "s_register_operand" "rk")))

78959

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78960

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

78961

(mem:SI (plus:SI (match_dup 3)

78962

(const_int 4))))])]

78963

"TARGET_32BIT && XVECLEN (operands[0], 0) == 2"

78964

@@ -859,9 +859,9 @@

78965

78966

(define_insn "*thumb_ldm2_ia"

78967

[(match_parallel 0 "load_multiple_operation"

78968

- [(set (match_operand:SI 1 "arm_hard_register_operand" "")

78969

+ [(set (match_operand:SI 1 "low_register_operand" "")

78970

(mem:SI (match_operand:SI 3 "s_register_operand" "l")))

78971

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78972

+ (set (match_operand:SI 2 "low_register_operand" "")

78973

(mem:SI (plus:SI (match_dup 3)

78974

(const_int 4))))])]

78975

"TARGET_THUMB1 && XVECLEN (operands[0], 0) == 2"

78976

@@ -872,9 +872,9 @@

78977

[(match_parallel 0 "load_multiple_operation"

78978

[(set (match_operand:SI 3 "s_register_operand" "+&rk")

78979

(plus:SI (match_dup 3) (const_int 8)))

78980

- (set (match_operand:SI 1 "arm_hard_register_operand" "")

78981

+ (set (match_operand:SI 1 "arm_hard_general_register_operand" "")

78982

(mem:SI (match_dup 3)))

78983

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78984

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

78985

(mem:SI (plus:SI (match_dup 3)

78986

(const_int 4))))])]

78987

"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"

78988

@@ -886,9 +886,9 @@

78989

[(match_parallel 0 "load_multiple_operation"

78990

[(set (match_operand:SI 3 "s_register_operand" "+&l")

78991

(plus:SI (match_dup 3) (const_int 8)))

78992

- (set (match_operand:SI 1 "arm_hard_register_operand" "")

78993

+ (set (match_operand:SI 1 "low_register_operand" "")

78994

(mem:SI (match_dup 3)))

78995

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78996

+ (set (match_operand:SI 2 "low_register_operand" "")

78997

(mem:SI (plus:SI (match_dup 3)

78998

(const_int 4))))])]

78999

"TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3"

79000

@@ -898,9 +898,9 @@

79001

(define_insn "*stm2_ia"

79002

[(match_parallel 0 "store_multiple_operation"

79003

[(set (mem:SI (match_operand:SI 3 "s_register_operand" "rk"))

79004

- (match_operand:SI 1 "arm_hard_register_operand" ""))

79005

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

79006

(set (mem:SI (plus:SI (match_dup 3) (const_int 4)))

79007

- (match_operand:SI 2 "arm_hard_register_operand" ""))])]

79008

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]

79009

"TARGET_32BIT && XVECLEN (operands[0], 0) == 2"

79010

"stm%(ia%)\t%3, {%1, %2}"

79011

[(set_attr "type" "store2")

79012

@@ -911,9 +911,9 @@

79013

[(set (match_operand:SI 3 "s_register_operand" "+&rk")

79014

(plus:SI (match_dup 3) (const_int 8)))

79015

(set (mem:SI (match_dup 3))

79016

- (match_operand:SI 1 "arm_hard_register_operand" ""))

79017

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

79018

(set (mem:SI (plus:SI (match_dup 3) (const_int 4)))

79019

- (match_operand:SI 2 "arm_hard_register_operand" ""))])]

79020

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]

79021

"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"

79022

"stm%(ia%)\t%3!, {%1, %2}"

79023

[(set_attr "type" "store2")

79024

@@ -924,9 +924,9 @@

79025

[(set (match_operand:SI 3 "s_register_operand" "+&l")

79026

(plus:SI (match_dup 3) (const_int 8)))

79027

(set (mem:SI (match_dup 3))

79028

- (match_operand:SI 1 "arm_hard_register_operand" ""))

79029

+ (match_operand:SI 1 "low_register_operand" ""))

79030

(set (mem:SI (plus:SI (match_dup 3) (const_int 4)))

79031

- (match_operand:SI 2 "arm_hard_register_operand" ""))])]

79032

+ (match_operand:SI 2 "low_register_operand" ""))])]

79033

"TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3"

79034

"stm%(ia%)\t%3!, {%1, %2}"

79035

[(set_attr "type" "store2")])

79036

@@ -933,10 +933,10 @@

79037

79038

(define_insn "*ldm2_ib"

79039

[(match_parallel 0 "load_multiple_operation"

79040

- [(set (match_operand:SI 1 "arm_hard_register_operand" "")

79041

+ [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")

79042

(mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk")

79043

(const_int 4))))

79044

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

79045

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

79046

(mem:SI (plus:SI (match_dup 3)

79047

(const_int 8))))])]

79048

"TARGET_ARM && XVECLEN (operands[0], 0) == 2"

79049

@@ -948,10 +948,10 @@

79050

[(match_parallel 0 "load_multiple_operation"

79051

[(set (match_operand:SI 3 "s_register_operand" "+&rk")

79052

(plus:SI (match_dup 3) (const_int 8)))

79053

- (set (match_operand:SI 1 "arm_hard_register_operand" "")

79054

+ (set (match_operand:SI 1 "arm_hard_general_register_operand" "")

79055

(mem:SI (plus:SI (match_dup 3)

79056

(const_int 4))))

79057

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

79058

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

79059

(mem:SI (plus:SI (match_dup 3)

79060

(const_int 8))))])]

79061

"TARGET_ARM && XVECLEN (operands[0], 0) == 3"

79062

@@ -962,9 +962,9 @@

79063

(define_insn "*stm2_ib"

79064

[(match_parallel 0 "store_multiple_operation"

79065

[(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int 4)))

79066

- (match_operand:SI 1 "arm_hard_register_operand" ""))

79067

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

79068

(set (mem:SI (plus:SI (match_dup 3) (const_int 8)))

79069

- (match_operand:SI 2 "arm_hard_register_operand" ""))])]

79070

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]

79071

"TARGET_ARM && XVECLEN (operands[0], 0) == 2"

79072

"stm%(ib%)\t%3, {%1, %2}"

79073

[(set_attr "type" "store2")

79074

@@ -975,9 +975,9 @@

79075

[(set (match_operand:SI 3 "s_register_operand" "+&rk")

79076

(plus:SI (match_dup 3) (const_int 8)))

79077

(set (mem:SI (plus:SI (match_dup 3) (const_int 4)))

79078

- (match_operand:SI 1 "arm_hard_register_operand" ""))

79079

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

79080

(set (mem:SI (plus:SI (match_dup 3) (const_int 8)))

79081

- (match_operand:SI 2 "arm_hard_register_operand" ""))])]

79082

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]

79083

"TARGET_ARM && XVECLEN (operands[0], 0) == 3"

79084

"stm%(ib%)\t%3!, {%1, %2}"

79085

[(set_attr "type" "store2")

79086

@@ -985,10 +985,10 @@

79087

79088

(define_insn "*ldm2_da"

79089

[(match_parallel 0 "load_multiple_operation"

79090

- [(set (match_operand:SI 1 "arm_hard_register_operand" "")

79091

+ [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")

79092

(mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk")

79093

(const_int -4))))

79094

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

79095

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

79096

(mem:SI (match_dup 3)))])]

79097

"TARGET_ARM && XVECLEN (operands[0], 0) == 2"

79098

"ldm%(da%)\t%3, {%1, %2}"

79099

@@ -999,10 +999,10 @@

79100

[(match_parallel 0 "load_multiple_operation"

79101

[(set (match_operand:SI 3 "s_register_operand" "+&rk")

79102

(plus:SI (match_dup 3) (const_int -8)))

79103

- (set (match_operand:SI 1 "arm_hard_register_operand" "")

79104

+ (set (match_operand:SI 1 "arm_hard_general_register_operand" "")

79105

(mem:SI (plus:SI (match_dup 3)

79106

(const_int -4))))

79107

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

79108

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

79109

(mem:SI (match_dup 3)))])]

79110

"TARGET_ARM && XVECLEN (operands[0], 0) == 3"

79111

"ldm%(da%)\t%3!, {%1, %2}"

79112

@@ -1012,9 +1012,9 @@

79113

(define_insn "*stm2_da"

79114

[(match_parallel 0 "store_multiple_operation"

79115

[(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int -4)))

79116

- (match_operand:SI 1 "arm_hard_register_operand" ""))

79117

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

79118

(set (mem:SI (match_dup 3))

79119

- (match_operand:SI 2 "arm_hard_register_operand" ""))])]

79120

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]

79121

"TARGET_ARM && XVECLEN (operands[0], 0) == 2"

79122

"stm%(da%)\t%3, {%1, %2}"

79123

[(set_attr "type" "store2")

79124

@@ -1025,9 +1025,9 @@

79125

[(set (match_operand:SI 3 "s_register_operand" "+&rk")

79126

(plus:SI (match_dup 3) (const_int -8)))

79127

(set (mem:SI (plus:SI (match_dup 3) (const_int -4)))

79128

- (match_operand:SI 1 "arm_hard_register_operand" ""))

79129

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

79130

(set (mem:SI (match_dup 3))

79131

- (match_operand:SI 2 "arm_hard_register_operand" ""))])]

79132

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]

79133

"TARGET_ARM && XVECLEN (operands[0], 0) == 3"

79134

"stm%(da%)\t%3!, {%1, %2}"

79135

[(set_attr "type" "store2")

79136

@@ -1035,10 +1035,10 @@

79137

79138

(define_insn "*ldm2_db"

79139

[(match_parallel 0 "load_multiple_operation"

79140

- [(set (match_operand:SI 1 "arm_hard_register_operand" "")

79141

+ [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")

79142

(mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk")

79143

(const_int -8))))

79144

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

79145

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

79146

(mem:SI (plus:SI (match_dup 3)

79147

(const_int -4))))])]

79148

"TARGET_32BIT && XVECLEN (operands[0], 0) == 2"

79149

@@ -1050,10 +1050,10 @@

79150

[(match_parallel 0 "load_multiple_operation"

79151

[(set (match_operand:SI 3 "s_register_operand" "+&rk")

79152

(plus:SI (match_dup 3) (const_int -8)))

79153

- (set (match_operand:SI 1 "arm_hard_register_operand" "")

79154

+ (set (match_operand:SI 1 "arm_hard_general_register_operand" "")

79155

(mem:SI (plus:SI (match_dup 3)

79156

(const_int -8))))

79157

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

79158

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

79159

(mem:SI (plus:SI (match_dup 3)

79160

(const_int -4))))])]

79161

"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"

79162

@@ -1064,9 +1064,9 @@

79163

(define_insn "*stm2_db"

79164

[(match_parallel 0 "store_multiple_operation"

79165

[(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int -8)))

79166

- (match_operand:SI 1 "arm_hard_register_operand" ""))

79167

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

79168

(set (mem:SI (plus:SI (match_dup 3) (const_int -4)))

79169

- (match_operand:SI 2 "arm_hard_register_operand" ""))])]

79170

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]

79171

"TARGET_32BIT && XVECLEN (operands[0], 0) == 2"

79172

"stm%(db%)\t%3, {%1, %2}"

79173

[(set_attr "type" "store2")

79174

@@ -1077,9 +1077,9 @@

79175

[(set (match_operand:SI 3 "s_register_operand" "+&rk")

79176

(plus:SI (match_dup 3) (const_int -8)))

79177

(set (mem:SI (plus:SI (match_dup 3) (const_int -8)))

79178

- (match_operand:SI 1 "arm_hard_register_operand" ""))

79179

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

79180

(set (mem:SI (plus:SI (match_dup 3) (const_int -4)))

79181

- (match_operand:SI 2 "arm_hard_register_operand" ""))])]

79182

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]

79183

"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"

79184

"stm%(db%)\t%3!, {%1, %2}"

79185

[(set_attr "type" "store2")

79186

Index: gcc/config/arm/predicates.md

79187

===================================================================

79188

--- a/src/gcc/config/arm/predicates.md (.../tags/gcc_4_8_2_release)

79189

+++ b/src/gcc/config/arm/predicates.md (.../branches/gcc-4_8-branch)

79190

@@ -31,11 +31,11 @@

79191

|| REGNO_REG_CLASS (REGNO (op)) != NO_REGS));

79192

})

79193

79194

-;; Any hard register.

79195

-(define_predicate "arm_hard_register_operand"

79196

+;; Any general register.

79197

+(define_predicate "arm_hard_general_register_operand"

79198

(match_code "reg")

79199

{

79200

- return REGNO (op) < FIRST_PSEUDO_REGISTER;

79201

+ return REGNO (op) <= LAST_ARM_REGNUM;

79202

})

79203

79204

;; A low register.

79205

@@ -76,6 +76,12 @@

79206

&& REGNO_REG_CLASS (REGNO (op)) == VFP_REGS)));

79207

})

79208

79209

+(define_predicate "vfp_hard_register_operand"

79210

+ (match_code "reg")

79211

+{

79212

+ return (IS_VFP_REGNUM (REGNO (op)));

79213

+})

79214

+

79215

(define_predicate "zero_operand"

79216

(and (match_code "const_int,const_double,const_vector")

79217

(match_test "op == CONST0_RTX (mode)")))

79218

Index: gcc/config/arm/arm-ldmstm.ml

79219

===================================================================

79220

--- a/src/gcc/config/arm/arm-ldmstm.ml (.../tags/gcc_4_8_2_release)

79221

+++ b/src/gcc/config/arm/arm-ldmstm.ml (.../branches/gcc-4_8-branch)

79222

@@ -67,10 +67,13 @@

79223

Printf.sprintf ("(match_operand:SI %d \"s_register_operand\" \"%s%s\")")

79224

(nregs + 1) (inout_constr op_type) (constr thumb)

79225

79226

+let reg_predicate thumb =

79227

+ if thumb then "low_register_operand" else "arm_hard_general_register_operand"

79228

+

79229

let write_ldm_set thumb nregs offset opnr first =

79230

let indent = " " in

79231

Printf.printf "%s" (if first then " [" else indent);

79232

- Printf.printf "(set (match_operand:SI %d \"arm_hard_register_operand\" \"\")\n" opnr;

79233

+ Printf.printf "(set (match_operand:SI %d \"%s\" \"\")\n" opnr (reg_predicate thumb);

79234

Printf.printf "%s (mem:SI " indent;

79235

begin if offset != 0 then Printf.printf "(plus:SI " end;

79236

Printf.printf "%s" (destreg nregs first IN thumb);

79237

@@ -84,7 +87,7 @@

79238

begin if offset != 0 then Printf.printf "(plus:SI " end;

79239

Printf.printf "%s" (destreg nregs first IN thumb);

79240

begin if offset != 0 then Printf.printf " (const_int %d))" offset end;

79241

- Printf.printf ")\n%s (match_operand:SI %d \"arm_hard_register_operand\" \"\"))" indent opnr

79242

+ Printf.printf ")\n%s (match_operand:SI %d \"%s\" \"\"))" indent opnr (reg_predicate thumb)

79243

79244

let write_ldm_peep_set extra_indent nregs opnr first =

79245

let indent = " " ^ extra_indent in

79246

Index: gcc/config/arm/iterators.md

79247

===================================================================

79248

--- a/src/gcc/config/arm/iterators.md (.../tags/gcc_4_8_2_release)

79249

+++ b/src/gcc/config/arm/iterators.md (.../branches/gcc-4_8-branch)

79250

@@ -493,6 +493,10 @@

79251

(UNSPEC_VRINTA "no") (UNSPEC_VRINTM "no")

79252

(UNSPEC_VRINTR "yes") (UNSPEC_VRINTX "yes")])

79253

79254

+(define_int_attr vrint_conds [(UNSPEC_VRINTZ "nocond") (UNSPEC_VRINTP "unconditional")

79255

+ (UNSPEC_VRINTA "unconditional") (UNSPEC_VRINTM "unconditional")

79256

+ (UNSPEC_VRINTR "nocond") (UNSPEC_VRINTX "nocond")])

79257

+

79258

(define_int_attr nvrint_variant [(UNSPEC_NVRINTZ "z") (UNSPEC_NVRINTP "p")

79259

(UNSPEC_NVRINTA "a") (UNSPEC_NVRINTM "m")

79260

(UNSPEC_NVRINTX "x") (UNSPEC_NVRINTN "n")])

79261

Index: gcc/config/arm/arm.md

79262

===================================================================

79263

--- a/src/gcc/config/arm/arm.md (.../tags/gcc_4_8_2_release)

79264

+++ b/src/gcc/config/arm/arm.md (.../branches/gcc-4_8-branch)

79265

@@ -11036,7 +11036,7 @@

79266

[(set (match_operand:SI 1 "s_register_operand" "+rk")

79267

(plus:SI (match_dup 1)

79268

(match_operand:SI 2 "const_int_operand" "I")))

79269

- (set (match_operand:DF 3 "arm_hard_register_operand" "")

79270

+ (set (match_operand:DF 3 "vfp_hard_register_operand" "")

79271

(mem:DF (match_dup 1)))])]

79272

"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"

79273

"*

79274

@@ -11270,7 +11270,9 @@

79275

(match_operand:SI 1 "" "")

79276

(match_operand:SI 2 "" ""))]

79277

"TARGET_32BIT && arm_arch5e"

79278

- "pld\\t%a0")

79279

+ "pld\\t%a0"

79280

+ [(set_attr "type" "load1")]

79281

+)

79282

79283

;; General predication pattern

79284

79285

Index: gcc/config/pa/pa.c

79286

===================================================================

79287

--- a/src/gcc/config/pa/pa.c (.../tags/gcc_4_8_2_release)

79288

+++ b/src/gcc/config/pa/pa.c (.../branches/gcc-4_8-branch)

79289

@@ -912,9 +912,12 @@

79290

legitimize_tls_address (rtx addr)

79291

{

79292

rtx ret, insn, tmp, t1, t2, tp;

79293

- enum tls_model model = SYMBOL_REF_TLS_MODEL (addr);

79294

79295

- switch (model)

79296

+ /* Currently, we can't handle anything but a SYMBOL_REF. */

79297

+ if (GET_CODE (addr) != SYMBOL_REF)

79298

+ return addr;

79299

+

79300

+ switch (SYMBOL_REF_TLS_MODEL (addr))

79301

{

79302

case TLS_MODEL_GLOBAL_DYNAMIC:

79303

tmp = gen_reg_rtx (Pmode);

79304

@@ -1035,7 +1038,7 @@

79305

&& !REG_POINTER (XEXP (x, 1)))

79306

return gen_rtx_PLUS (Pmode, XEXP (x, 1), XEXP (x, 0));

79307

79308

- if (PA_SYMBOL_REF_TLS_P (x))

79309

+ if (pa_tls_referenced_p (x))

79310

return legitimize_tls_address (x);

79311

else if (flag_pic)

79312

return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));

79313

@@ -1916,9 +1919,10 @@

79314

not consider them legitimate constants. Loop optimizations can

79315

call the emit_move_xxx with one as a source. */

79316

if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))

79317

+ || (GET_CODE (operand1) == HIGH

79318

+ && symbolic_operand (XEXP (operand1, 0), mode))

79319

|| function_label_operand (operand1, VOIDmode)

79320

- || (GET_CODE (operand1) == HIGH

79321

- && symbolic_operand (XEXP (operand1, 0), mode)))

79322

+ || pa_tls_referenced_p (operand1))

79323

{

79324

int ishighonly = 0;

79325

79326

@@ -2625,7 +2629,7 @@

79327

if (optype0 == REGOP)

79328

latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);

79329

else if (optype0 == OFFSOP)

79330

- latehalf[0] = adjust_address (operands[0], SImode, 4);

79331

+ latehalf[0] = adjust_address_nv (operands[0], SImode, 4);

79332

else

79333

latehalf[0] = operands[0];

79334

79335

@@ -2632,7 +2636,7 @@

79336

if (optype1 == REGOP)

79337

latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);

79338

else if (optype1 == OFFSOP)

79339

- latehalf[1] = adjust_address (operands[1], SImode, 4);

79340

+ latehalf[1] = adjust_address_nv (operands[1], SImode, 4);

79341

else if (optype1 == CNSTOP)

79342

split_double (operands[1], &operands[1], &latehalf[1]);

79343

else

79344

@@ -7539,7 +7543,7 @@

79345

if (!TARGET_LONG_CALLS && distance < MAX_PCREL17F_OFFSET)

79346

return 8;

79347

79348

- if (TARGET_LONG_ABS_CALL && !flag_pic)

79349

+ if (!flag_pic)

79350

return 12;

79351

79352

return 24;

79353

@@ -8104,7 +8108,8 @@

79354

return 12;

79355

79356

if (TARGET_FAST_INDIRECT_CALLS

79357

- || (!TARGET_PORTABLE_RUNTIME

79358

+ || (!TARGET_LONG_CALLS

79359

+ && !TARGET_PORTABLE_RUNTIME

79360

&& ((TARGET_PA_20 && !TARGET_SOM && distance < 7600000)

79361

|| distance < MAX_PCREL17F_OFFSET)))

79362

return 8;

79363

@@ -10397,7 +10402,7 @@

79364

/* TLS_MODEL_GLOBAL_DYNAMIC and TLS_MODEL_LOCAL_DYNAMIC are not

79365

legitimate constants. The other variants can't be handled by

79366

the move patterns after reload starts. */

79367

- if (PA_SYMBOL_REF_TLS_P (x))

79368

+ if (pa_tls_referenced_p (x))

79369

return false;

79370

79371

if (TARGET_64BIT && GET_CODE (x) == CONST_DOUBLE)

79372

@@ -10522,13 +10527,13 @@

79373

79374

/* When INT14_OK_STRICT is false, a secondary reload is needed

79375

to adjust the displacement of SImode and DImode floating point

79376

- instructions. So, we return false when STRICT is true. We

79377

+ instructions but this may fail when the register also needs

79378

+ reloading. So, we return false when STRICT is true. We

79379

also reject long displacements for float mode addresses since

79380

the majority of accesses will use floating point instructions

79381

that don't support 14-bit offsets. */

79382

if (!INT14_OK_STRICT

79383

- && reload_in_progress

79384

- && strict

79385

+ && (strict || !(reload_in_progress || reload_completed))

79386

&& mode != QImode

79387

&& mode != HImode)

79388

return false;

79389

@@ -10588,8 +10593,7 @@

79390

return true;

79391

79392

if (!INT14_OK_STRICT

79393

- && reload_in_progress

79394

- && strict

79395

+ && (strict || !(reload_in_progress || reload_completed))

79396

&& mode != QImode

79397

&& mode != HImode)

79398

return false;

79399

Index: gcc/config/pa/pa.h

79400

===================================================================

79401

--- a/src/gcc/config/pa/pa.h (.../tags/gcc_4_8_2_release)

79402

+++ b/src/gcc/config/pa/pa.h (.../branches/gcc-4_8-branch)

79403

@@ -784,9 +784,9 @@

79404

79405

#define MAX_REGS_PER_ADDRESS 2

79406

79407

-/* Non-TLS symbolic references. */

79408

-#define PA_SYMBOL_REF_TLS_P(RTX) \

79409

- (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)

79410

+/* TLS symbolic reference. */

79411

+#define PA_SYMBOL_REF_TLS_P(X) \

79412

+ (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (X) != 0)

79413

79414

/* Recognize any constant value that is a valid address except

79415

for symbolic addresses. We get better CSE by rejecting them

79416

@@ -796,7 +796,8 @@

79417

#define CONSTANT_ADDRESS_P(X) \

79418

((GET_CODE (X) == LABEL_REF \

79419

|| (GET_CODE (X) == SYMBOL_REF && !SYMBOL_REF_TLS_MODEL (X)) \

79420

- || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \

79421

+ || GET_CODE (X) == CONST_INT \

79422

+ || (GET_CODE (X) == CONST && !pa_tls_referenced_p (X)) \

79423

|| GET_CODE (X) == HIGH) \

79424

&& (reload_in_progress || reload_completed \

79425

|| ! pa_symbolic_expression_p (X)))

79426

Index: gcc/config/mips/driver-native.c

79427

===================================================================

79428

--- a/src/gcc/config/mips/driver-native.c (.../tags/gcc_4_8_2_release)

79429

+++ b/src/gcc/config/mips/driver-native.c (.../branches/gcc-4_8-branch)

79430

@@ -58,11 +58,17 @@

79431

if (strncmp (buf, "cpu model", sizeof ("cpu model") - 1) == 0)

79432

{

79433

if (strstr (buf, "Godson2 V0.2") != NULL

79434

- || strstr (buf, "Loongson-2 V0.2") != NULL)

79435

+ || strstr (buf, "Loongson-2 V0.2") != NULL

79436

+ || strstr (buf, "Loongson-2E") != NULL)

79437

cpu = "loongson2e";

79438

else if (strstr (buf, "Godson2 V0.3") != NULL

79439

- || strstr (buf, "Loongson-2 V0.3") != NULL)

79440

+ || strstr (buf, "Loongson-2 V0.3") != NULL

79441

+ || strstr (buf, "Loongson-2F") != NULL)

79442

cpu = "loongson2f";

79443

+ else if (strstr (buf, "Godson3 V0.5") != NULL

79444

+ || strstr (buf, "Loongson-3 V0.5") != NULL

79445

+ || strstr (buf, "Loongson-3A") != NULL)

79446

+ cpu = "loongson3a";

79447

else if (strstr (buf, "SiByte SB1") != NULL)

79448

cpu = "sb1";

79449

else if (strstr (buf, "R5000") != NULL)

79450

Index: gcc/config/mips/mips.md

79451

===================================================================

79452

--- a/src/gcc/config/mips/mips.md (.../tags/gcc_4_8_2_release)

79453

+++ b/src/gcc/config/mips/mips.md (.../branches/gcc-4_8-branch)

79454

@@ -73,6 +73,11 @@

79455

UNSPEC_STORE_LEFT

79456

UNSPEC_STORE_RIGHT

79457

79458

+ ;; Integer operations that are too cumbersome to describe directly.

79459

+ UNSPEC_WSBH

79460

+ UNSPEC_DSBH

79461

+ UNSPEC_DSHD

79462

+

79463

;; Floating-point moves.

79464

UNSPEC_LOAD_LOW

79465

UNSPEC_LOAD_HIGH

79466

@@ -1294,20 +1299,32 @@

79467

79468

;; Combiner patterns for unsigned byte-add.

79469

79470

-(define_insn "*baddu_si"

79471

+(define_insn "*baddu_si_eb"

79472

[(set (match_operand:SI 0 "register_operand" "=d")

79473

(zero_extend:SI

79474

- (plus:QI (match_operand:QI 1 "register_operand" "d")

79475

- (match_operand:QI 2 "register_operand" "d"))))]

79476

- "ISA_HAS_BADDU"

79477

+ (subreg:QI

79478

+ (plus:SI (match_operand:SI 1 "register_operand" "d")

79479

+ (match_operand:SI 2 "register_operand" "d")) 3)))]

79480

+ "ISA_HAS_BADDU && BYTES_BIG_ENDIAN"

79481

"baddu\\t%0,%1,%2"

79482

[(set_attr "alu_type" "add")])

79483

79484

+(define_insn "*baddu_si_el"

79485

+ [(set (match_operand:SI 0 "register_operand" "=d")

79486

+ (zero_extend:SI

79487

+ (subreg:QI

79488

+ (plus:SI (match_operand:SI 1 "register_operand" "d")

79489

+ (match_operand:SI 2 "register_operand" "d")) 0)))]

79490

+ "ISA_HAS_BADDU && !BYTES_BIG_ENDIAN"

79491

+ "baddu\\t%0,%1,%2"

79492

+ [(set_attr "alu_type" "add")])

79493

+

79494

(define_insn "*baddu_di<mode>"

79495

[(set (match_operand:GPR 0 "register_operand" "=d")

79496

(zero_extend:GPR

79497

- (plus:QI (truncate:QI (match_operand:DI 1 "register_operand" "d"))

79498

- (truncate:QI (match_operand:DI 2 "register_operand" "d")))))]

79499

+ (truncate:QI

79500

+ (plus:DI (match_operand:DI 1 "register_operand" "d")

79501

+ (match_operand:DI 2 "register_operand" "d")))))]

79502

"ISA_HAS_BADDU && TARGET_64BIT"

79503

"baddu\\t%0,%1,%2"

79504

[(set_attr "alu_type" "add")])

79505

@@ -5367,6 +5384,56 @@

79506

}

79507

[(set_attr "type" "shift")

79508

(set_attr "mode" "<MODE>")])

79509

+

79510

+(define_insn "bswaphi2"

79511

+ [(set (match_operand:HI 0 "register_operand" "=d")

79512

+ (bswap:HI (match_operand:HI 1 "register_operand" "d")))]

79513

+ "ISA_HAS_WSBH"

79514

+ "wsbh\t%0,%1"

79515

+ [(set_attr "type" "shift")])

79516

+

79517

+(define_insn_and_split "bswapsi2"

79518

+ [(set (match_operand:SI 0 "register_operand" "=d")

79519

+ (bswap:SI (match_operand:SI 1 "register_operand" "d")))]

79520

+ "ISA_HAS_WSBH && ISA_HAS_ROR"

79521

+ "#"

79522

+ ""

79523

+ [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_WSBH))

79524

+ (set (match_dup 0) (rotatert:SI (match_dup 0) (const_int 16)))]

79525

+ ""

79526

+ [(set_attr "length" "8")])

79527

+

79528

+(define_insn_and_split "bswapdi2"

79529

+ [(set (match_operand:DI 0 "register_operand" "=d")

79530

+ (bswap:DI (match_operand:DI 1 "register_operand" "d")))]

79531

+ "TARGET_64BIT && ISA_HAS_WSBH"

79532

+ "#"

79533

+ ""

79534

+ [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_DSBH))

79535

+ (set (match_dup 0) (unspec:DI [(match_dup 0)] UNSPEC_DSHD))]

79536

+ ""

79537

+ [(set_attr "length" "8")])

79538

+

79539

+(define_insn "wsbh"

79540

+ [(set (match_operand:SI 0 "register_operand" "=d")

79541

+ (unspec:SI [(match_operand:SI 1 "register_operand" "d")] UNSPEC_WSBH))]

79542

+ "ISA_HAS_WSBH"

79543

+ "wsbh\t%0,%1"

79544

+ [(set_attr "type" "shift")])

79545

+

79546

+(define_insn "dsbh"

79547

+ [(set (match_operand:DI 0 "register_operand" "=d")

79548

+ (unspec:DI [(match_operand:DI 1 "register_operand" "d")] UNSPEC_DSBH))]

79549

+ "TARGET_64BIT && ISA_HAS_WSBH"

79550

+ "dsbh\t%0,%1"

79551

+ [(set_attr "type" "shift")])

79552

+

79553

+(define_insn "dshd"

79554

+ [(set (match_operand:DI 0 "register_operand" "=d")

79555

+ (unspec:DI [(match_operand:DI 1 "register_operand" "d")] UNSPEC_DSHD))]

79556

+ "TARGET_64BIT && ISA_HAS_WSBH"

79557

+ "dshd\t%0,%1"

79558

+ [(set_attr "type" "shift")])

79559

79560

;;

79561

;; ....................

79562

Index: gcc/config/mips/mips.c

79563

===================================================================

79564

--- a/src/gcc/config/mips/mips.c (.../tags/gcc_4_8_2_release)

79565

+++ b/src/gcc/config/mips/mips.c (.../branches/gcc-4_8-branch)

79566

@@ -3560,17 +3560,6 @@

79567

}

79568

}

79569

79570

-/* Return the cost of an operand X that can be trucated for free.

79571

- SPEED says whether we're optimizing for size or speed. */

79572

-

79573

-static int

79574

-mips_truncated_op_cost (rtx x, bool speed)

79575

-{

79576

- if (GET_CODE (x) == TRUNCATE)

79577

- x = XEXP (x, 0);

79578

- return set_src_cost (x, speed);

79579

-}

79580

-

79581

/* Implement TARGET_RTX_COSTS. */

79582

79583

static bool

79584

@@ -3951,13 +3940,12 @@

79585

case ZERO_EXTEND:

79586

if (outer_code == SET

79587

&& ISA_HAS_BADDU

79588

+ && (GET_CODE (XEXP (x, 0)) == TRUNCATE

79589

+ || GET_CODE (XEXP (x, 0)) == SUBREG)

79590

&& GET_MODE (XEXP (x, 0)) == QImode

79591

- && GET_CODE (XEXP (x, 0)) == PLUS)

79592

+ && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)

79593

{

79594

- rtx plus = XEXP (x, 0);

79595

- *total = (COSTS_N_INSNS (1)

79596

- + mips_truncated_op_cost (XEXP (plus, 0), speed)

79597

- + mips_truncated_op_cost (XEXP (plus, 1), speed));

79598

+ *total = set_src_cost (XEXP (XEXP (x, 0), 0), speed);

79599

return true;

79600

}

79601

*total = mips_zero_extend_cost (mode, XEXP (x, 0));

79602

@@ -8057,7 +8045,7 @@

79603

case 't':

79604

{

79605

int truth = (code == NE) == (letter == 'T');

79606

- fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);

79607

+ fputc ("zfnt"[truth * 2 + ST_REG_P (REGNO (XEXP (op, 0)))], file);

79608

}

79609

break;

79610

79611

Index: gcc/config/mips/mips.h

79612

===================================================================

79613

--- a/src/gcc/config/mips/mips.h (.../tags/gcc_4_8_2_release)

79614

+++ b/src/gcc/config/mips/mips.h (.../branches/gcc-4_8-branch)

79615

@@ -949,6 +949,11 @@

79616

|| TARGET_SMARTMIPS) \

79617

&& !TARGET_MIPS16)

79618

79619

+/* ISA has the WSBH (word swap bytes within halfwords) instruction.

79620

+ 64-bit targets also provide DSBH and DSHD. */

79621

+#define ISA_HAS_WSBH ((ISA_MIPS32R2 || ISA_MIPS64R2) \

79622

+ && !TARGET_MIPS16)

79623

+

79624

/* ISA has data prefetch instructions. This controls use of 'pref'. */

79625

#define ISA_HAS_PREFETCH ((ISA_MIPS4 \

79626

|| TARGET_LOONGSON_2EF \

79627

Index: gcc/params.def

79628

===================================================================

79629

--- a/src/gcc/params.def (.../tags/gcc_4_8_2_release)

79630

+++ b/src/gcc/params.def (.../branches/gcc-4_8-branch)

79631

@@ -1014,6 +1014,12 @@

79632

"strength reduction",

79633

50, 1, 999999)

79634

79635

+DEFPARAM (PARAM_UNINIT_CONTROL_DEP_ATTEMPTS,

79636

+ "uninit-control-dep-attempts",

79637

+ "Maximum number of nested calls to search for control dependencies "

79638

+ "during uninitialized variable analysis",

79639

+ 1000, 1, 0)

79640

+

79641

/*

79642

Local variables:

79643

mode:c

79644

Index: gcc/tree-ssanames.c

79645

===================================================================

79646

--- a/src/gcc/tree-ssanames.c (.../tags/gcc_4_8_2_release)

79647

+++ b/src/gcc/tree-ssanames.c (.../branches/gcc-4_8-branch)

79648

@@ -128,7 +128,7 @@

79649

79650

/* The node was cleared out when we put it on the free list, so

79651

there is no need to do so again here. */

79652

- gcc_assert (ssa_name (SSA_NAME_VERSION (t)) == NULL);

79653

+ gcc_assert ((*SSANAMES (fn))[SSA_NAME_VERSION (t)] == NULL);

79654

(*SSANAMES (fn))[SSA_NAME_VERSION (t)] = t;

79655

}

79656

else

79657

Index: gcc/regcprop.c

79658

===================================================================

79659

--- a/src/gcc/regcprop.c (.../tags/gcc_4_8_2_release)

79660

+++ b/src/gcc/regcprop.c (.../branches/gcc-4_8-branch)

79661

@@ -747,6 +747,7 @@

79662

int n_ops, i, alt, predicated;

79663

bool is_asm, any_replacements;

79664

rtx set;

79665

+ rtx link;

79666

bool replaced[MAX_RECOG_OPERANDS];

79667

bool changed = false;

79668

struct kill_set_value_data ksvd;

79669

@@ -815,6 +816,23 @@

79670

if (recog_op_alt[i][alt].earlyclobber)

79671

kill_value (recog_data.operand[i], vd);

79672

79673

+ /* If we have dead sets in the insn, then we need to note these as we

79674

+ would clobbers. */

79675

+ for (link = REG_NOTES (insn); link; link = XEXP (link, 1))

79676

+ {

79677

+ if (REG_NOTE_KIND (link) == REG_UNUSED)

79678

+ {

79679

+ kill_value (XEXP (link, 0), vd);

79680

+ /* Furthermore, if the insn looked like a single-set,

79681

+ but the dead store kills the source value of that

79682

+ set, then we can no-longer use the plain move

79683

+ special case below. */

79684

+ if (set

79685

+ && reg_overlap_mentioned_p (XEXP (link, 0), SET_SRC (set)))

79686

+ set = NULL;

79687

+ }

79688

+ }

79689

+

79690

/* Special-case plain move instructions, since we may well

79691

be able to do the move from a different register class. */

79692

if (set && REG_P (SET_SRC (set)))

79693

Index: gcc/tree-ssa-operands.c

79694

===================================================================

79695

--- a/src/gcc/tree-ssa-operands.c (.../tags/gcc_4_8_2_release)

79696

+++ b/src/gcc/tree-ssa-operands.c (.../branches/gcc-4_8-branch)

79697

@@ -626,10 +626,8 @@

79698

call-clobbered. */

79699

if (!(call_flags & ECF_NOVOPS))

79700

{

79701

- /* A 'pure' or a 'const' function never call-clobbers anything.

79702

- A 'noreturn' function might, but since we don't return anyway

79703

- there is no point in recording that. */

79704

- if (!(call_flags & (ECF_PURE | ECF_CONST | ECF_NORETURN)))

79705

+ /* A 'pure' or a 'const' function never call-clobbers anything. */

79706

+ if (!(call_flags & (ECF_PURE | ECF_CONST)))

79707

add_virtual_operand (stmt, opf_def);

79708

else if (!(call_flags & ECF_CONST))

79709

add_virtual_operand (stmt, opf_use);

79710

Index: libgo/configure

79711

===================================================================

79712

--- a/src/libgo/configure (.../tags/gcc_4_8_2_release)

79713

+++ b/src/libgo/configure (.../branches/gcc-4_8-branch)

79714

@@ -6501,7 +6501,7 @@

79715

rm -rf conftest*

79716

;;

79717

79718

-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \

79719

+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \

79720

s390*-*linux*|s390*-*tpf*|sparc*-*linux*)

79721

# Find out which ABI we are using.

79722

echo 'int i;' > conftest.$ac_ext

79723

@@ -6519,7 +6519,10 @@

79724

x86_64-*linux*)

79725

LD="${LD-ld} -m elf_i386"

79726

;;

79727

- ppc64-*linux*|powerpc64-*linux*)

79728

+ powerpc64le-*linux*)

79729

+ LD="${LD-ld} -m elf32lppclinux"

79730

+ ;;

79731

+ powerpc64-*linux*)

79732

LD="${LD-ld} -m elf32ppclinux"

79733

;;

79734

s390x-*linux*)

79735

@@ -6538,7 +6541,10 @@

79736

x86_64-*linux*)

79737

LD="${LD-ld} -m elf_x86_64"

79738

;;

79739

- ppc*-*linux*|powerpc*-*linux*)

79740

+ powerpcle-*linux*)

79741

+ LD="${LD-ld} -m elf64lppc"

79742

+ ;;

79743

+ powerpc-*linux*)

79744

LD="${LD-ld} -m elf64ppc"

79745

;;

79746

s390*-*linux*|s390*-*tpf*)

79747

@@ -11105,7 +11111,7 @@

79748

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

79749

lt_status=$lt_dlunknown

79750

cat > conftest.$ac_ext <<_LT_EOF

79751

-#line 11108 "configure"

79752

+#line 11114 "configure"

79753

#include "confdefs.h"

79754

79755

#if HAVE_DLFCN_H

79756

@@ -11211,7 +11217,7 @@

79757

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

79758

lt_status=$lt_dlunknown

79759

cat > conftest.$ac_ext <<_LT_EOF

79760

-#line 11214 "configure"

79761

+#line 11220 "configure"

79762

#include "confdefs.h"

79763

79764

#if HAVE_DLFCN_H

79765

@@ -14700,7 +14706,7 @@

79766

fi

79767

79768

79769

-for ac_func in accept4 epoll_create1 faccessat fallocate fchmodat fchownat futimesat inotify_add_watch inotify_init inotify_init1 inotify_rm_watch mkdirat mknodat openat pipe2 renameat sync_file_range splice tee unlinkat unshare utimensat

79770

+for ac_func in accept4 dup3 epoll_create1 faccessat fallocate fchmodat fchownat futimesat getxattr inotify_add_watch inotify_init inotify_init1 inotify_rm_watch listxattr mkdirat mknodat openat pipe2 removexattr renameat setxattr sync_file_range splice tee unlinkat unshare utimensat

79771

do :

79772

as_ac_var=`$as_echo "ac_cv_func_$ac_func" | $as_tr_sh`

79773

ac_fn_c_check_func "$LINENO" "$ac_func" "$as_ac_var"

79774

Index: libgo/Makefile.in

79775

===================================================================

79776

--- a/src/libgo/Makefile.in (.../tags/gcc_4_8_2_release)

79777

+++ b/src/libgo/Makefile.in (.../branches/gcc-4_8-branch)

79778

@@ -195,7 +195,7 @@

79779

@LIBGO_IS_LINUX_TRUE@am__objects_5 = getncpu-linux.lo

79780

am__objects_6 = go-append.lo go-assert.lo go-assert-interface.lo \

79781

go-byte-array-to-string.lo go-breakpoint.lo go-caller.lo \

79782

- go-callers.lo go-can-convert-interface.lo go-cgo.lo \

79783

+ go-callers.lo go-can-convert-interface.lo go-cdiv.lo go-cgo.lo \

79784

go-check-interface.lo go-construct-map.lo \

79785

go-convert-interface.lo go-copy.lo go-defer.lo \

79786

go-deferred-recover.lo go-eface-compare.lo \

79787

@@ -757,6 +757,7 @@

79788

runtime/go-caller.c \

79789

runtime/go-callers.c \

79790

runtime/go-can-convert-interface.c \

79791

+ runtime/go-cdiv.c \

79792

runtime/go-cgo.c \

79793

runtime/go-check-interface.c \

79794

runtime/go-construct-map.c \

79795

@@ -1446,7 +1447,7 @@

79796

go/go/build/build.go \

79797

go/go/build/doc.go \

79798

go/go/build/read.go \

79799

- syslist.go

79800

+ go/go/build/syslist.go

79801

79802

go_go_doc_files = \

79803

go/go/doc/comment.go \

79804

@@ -2368,6 +2369,7 @@

79805

@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/go-caller.Plo@am__quote@

79806

@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/go-callers.Plo@am__quote@

79807

@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/go-can-convert-interface.Plo@am__quote@

79808

+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/go-cdiv.Plo@am__quote@

79809

@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/go-cgo.Plo@am__quote@

79810

@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/go-check-interface.Plo@am__quote@

79811

@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/go-construct-map.Plo@am__quote@

79812

@@ -2554,6 +2556,13 @@

79813

@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@

79814

@am__fastdepCC_FALSE@ $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o go-can-convert-interface.lo `test -f 'runtime/go-can-convert-interface.c' || echo '$(srcdir)/'`runtime/go-can-convert-interface.c

79815

79816

+go-cdiv.lo: runtime/go-cdiv.c

79817

+@am__fastdepCC_TRUE@ $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT go-cdiv.lo -MD -MP -MF $(DEPDIR)/go-cdiv.Tpo -c -o go-cdiv.lo `test -f 'runtime/go-cdiv.c' || echo '$(srcdir)/'`runtime/go-cdiv.c

79818

+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/go-cdiv.Tpo $(DEPDIR)/go-cdiv.Plo

79819

+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='runtime/go-cdiv.c' object='go-cdiv.lo' libtool=yes @AMDEPBACKSLASH@

79820

+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@

79821

+@am__fastdepCC_FALSE@ $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o go-cdiv.lo `test -f 'runtime/go-cdiv.c' || echo '$(srcdir)/'`runtime/go-cdiv.c

79822

+

79823

go-cgo.lo: runtime/go-cgo.c

79824

@am__fastdepCC_TRUE@ $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT go-cgo.lo -MD -MP -MF $(DEPDIR)/go-cgo.Tpo -c -o go-cgo.lo `test -f 'runtime/go-cgo.c' || echo '$(srcdir)/'`runtime/go-cgo.c

79825

@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/go-cgo.Tpo $(DEPDIR)/go-cgo.Plo

79826

@@ -5062,15 +5071,6 @@

79827

@$(CHECK)

79828

.PHONY: go/build/check

79829

79830

-syslist.go: s-syslist; @true

79831

-s-syslist: Makefile

79832

- echo '// Generated automatically by make.' >syslist.go.tmp

79833

- echo 'package build' >>syslist.go.tmp

79834

- echo 'const goosList = "$(GOOS)"' >>syslist.go.tmp

79835

- echo 'const goarchList = "$(GOARCH)"' >>syslist.go.tmp

79836

- $(SHELL) $(srcdir)/../move-if-change syslist.go.tmp syslist.go

79837

- $(STAMP) $@

79838

-

79839

@go_include@ go/doc.lo.dep

79840

go/doc.lo.dep: $(go_go_doc_files)

79841

$(BUILDDEPS)

79842

Index: libgo/runtime/go-defer.c

79843

===================================================================

79844

--- a/src/libgo/runtime/go-defer.c (.../tags/gcc_4_8_2_release)

79845

+++ b/src/libgo/runtime/go-defer.c (.../branches/gcc-4_8-branch)

79846

@@ -27,6 +27,7 @@

79847

n->__pfn = pfn;

79848

n->__arg = arg;

79849

n->__retaddr = NULL;

79850

+ n->__makefunc_can_recover = 0;

79851

g->defer = n;

79852

}

79853

79854

Index: libgo/runtime/go-defer.h

79855

===================================================================

79856

--- a/src/libgo/runtime/go-defer.h (.../tags/gcc_4_8_2_release)

79857

+++ b/src/libgo/runtime/go-defer.h (.../branches/gcc-4_8-branch)

79858

@@ -34,4 +34,10 @@

79859

set by __go_set_defer_retaddr which is called by the thunks

79860

created by defer statements. */

79861

const void *__retaddr;

79862

+

79863

+ /* Set to true if a function created by reflect.MakeFunc is

79864

+ permitted to recover. The return address of such a function

79865

+ function will be somewhere in libffi, so __retaddr is not

79866

+ useful. */

79867

+ _Bool __makefunc_can_recover;

79868

};

79869

Index: libgo/runtime/go-int-array-to-string.c

79870

===================================================================

79871

--- a/src/libgo/runtime/go-int-array-to-string.c (.../tags/gcc_4_8_2_release)

79872

+++ b/src/libgo/runtime/go-int-array-to-string.c (.../branches/gcc-4_8-branch)

79873

@@ -30,6 +30,8 @@

79874

79875

if (v < 0 || v > 0x10ffff)

79876

v = 0xfffd;

79877

+ else if (0xd800 <= v && v <= 0xdfff)

79878

+ v = 0xfffd;

79879

79880

if (v <= 0x7f)

79881

slen += 1;

79882

@@ -56,6 +58,8 @@

79883

character. */

79884

if (v < 0 || v > 0x10ffff)

79885

v = 0xfffd;

79886

+ else if (0xd800 <= v && v <= 0xdfff)

79887

+ v = 0xfffd;

79888

79889

if (v <= 0x7f)

79890

*s++ = v;

79891

Index: libgo/runtime/go-nosys.c

79892

===================================================================

79893

--- a/src/libgo/runtime/go-nosys.c (.../tags/gcc_4_8_2_release)

79894

+++ b/src/libgo/runtime/go-nosys.c (.../branches/gcc-4_8-branch)

79895

@@ -43,6 +43,17 @@

79896

}

79897

#endif

79898

79899

+#ifndef HAVE_DUP3

79900

+int

79901

+dup3 (int oldfd __attribute__ ((unused)),

79902

+ int newfd __attribute__ ((unused)),

79903

+ int flags __attribute__ ((unused)))

79904

+{

79905

+ errno = ENOSYS;

79906

+ return -1;

79907

+}

79908

+#endif

79909

+

79910

#ifndef HAVE_EPOLL_CREATE1

79911

int

79912

epoll_create1 (int flags __attribute__ ((unused)))

79913

@@ -112,6 +123,18 @@

79914

}

79915

#endif

79916

79917

+#ifndef HAVE_GETXATTR

79918

+ssize_t

79919

+getxattr (const char *path __attribute__ ((unused)),

79920

+ const char *name __attribute__ ((unused)),

79921

+ void *value __attribute__ ((unused)),

79922

+ size_t size __attribute__ ((unused)))

79923

+{

79924

+ errno = ENOSYS;

79925

+ return -1;

79926

+}

79927

+#endif

79928

+

79929

#ifndef HAVE_INOTIFY_ADD_WATCH

79930

int

79931

inotify_add_watch (int fd __attribute__ ((unused)),

79932

@@ -151,6 +174,17 @@

79933

}

79934

#endif

79935

79936

+#ifndef HAVE_LISTXATTR

79937

+ssize_t

79938

+listxattr (const char *path __attribute__ ((unused)),

79939

+ char *list __attribute__ ((unused)),

79940

+ size_t size __attribute__ ((unused)))

79941

+{

79942

+ errno = ENOSYS;

79943

+ return -1;

79944

+}

79945

+#endif

79946

+

79947

#ifndef HAVE_MKDIRAT

79948

int

79949

mkdirat (int dirfd __attribute__ ((unused)),

79950

@@ -196,6 +230,16 @@

79951

}

79952

#endif

79953

79954

+#ifndef HAVE_REMOVEXATTR

79955

+int

79956

+removexattr (const char *path __attribute__ ((unused)),

79957

+ const char *name __attribute__ ((unused)))

79958

+{

79959

+ errno = ENOSYS;

79960

+ return -1;

79961

+}

79962

+#endif

79963

+

79964

#ifndef HAVE_RENAMEAT

79965

int

79966

renameat (int olddirfd __attribute__ ((unused)),

79967

@@ -208,6 +252,19 @@

79968

}

79969

#endif

79970

79971

+#ifndef HAVE_SETXATTR

79972

+int

79973

+setxattr (const char *path __attribute__ ((unused)),

79974

+ const char *name __attribute__ ((unused)),

79975

+ const void *value __attribute__ ((unused)),

79976

+ size_t size __attribute__ ((unused)),

79977

+ int flags __attribute__ ((unused)))

79978

+{

79979

+ errno = ENOSYS;

79980

+ return -1;

79981

+}

79982

+#endif

79983

+

79984

#ifndef HAVE_SPLICE

79985

int

79986

splice (int fd __attribute__ ((unused)),

79987

Index: libgo/runtime/runtime.h

79988

===================================================================

79989

--- a/src/libgo/runtime/runtime.h (.../tags/gcc_4_8_2_release)

79990

+++ b/src/libgo/runtime/runtime.h (.../branches/gcc-4_8-branch)

79991

@@ -440,7 +440,7 @@

79992

};

79993

void runtime_hashinit(void);

79994

79995

-void runtime_traceback();

79996

+void runtime_traceback(void);

79997

void runtime_tracebackothers(G*);

79998

79999

/*

80000

@@ -756,6 +756,7 @@

80001

extern _Bool __go_file_line(uintptr, String*, String*, intgo *);

80002

extern byte* runtime_progname();

80003

extern void runtime_main(void*);

80004

+extern uint32 runtime_in_callers;

80005

80006

int32 getproccount(void);

80007

80008

Index: libgo/runtime/proc.c

80009

===================================================================

80010

--- a/src/libgo/runtime/proc.c (.../tags/gcc_4_8_2_release)

80011

+++ b/src/libgo/runtime/proc.c (.../branches/gcc-4_8-branch)

80012

@@ -1716,10 +1716,30 @@

80013

// entersyscall is going to return immediately after.

80014

80015

void runtime_entersyscall(void) __attribute__ ((no_split_stack));

80016

+static void doentersyscall(void) __attribute__ ((no_split_stack, noinline));

80017

80018

void

80019

runtime_entersyscall()

80020

{

80021

+ // Save the registers in the g structure so that any pointers

80022

+ // held in registers will be seen by the garbage collector.

80023

+ getcontext(&g->gcregs);

80024

+

80025

+ // Do the work in a separate function, so that this function

80026

+ // doesn't save any registers on its own stack. If this

80027

+ // function does save any registers, we might store the wrong

80028

+ // value in the call to getcontext.

80029

+ //

80030

+ // FIXME: This assumes that we do not need to save any

80031

+ // callee-saved registers to access the TLS variable g. We

80032

+ // don't want to put the ucontext_t on the stack because it is

80033

+ // large and we can not split the stack here.

80034

+ doentersyscall();

80035

+}

80036

+

80037

+static void

80038

+doentersyscall()

80039

+{

80040

if(m->profilehz > 0)

80041

runtime_setprof(false);

80042

80043

@@ -1736,10 +1756,6 @@

80044

}

80045

#endif

80046

80047

- // Save the registers in the g structure so that any pointers

80048

- // held in registers will be seen by the garbage collector.

80049

- getcontext(&g->gcregs);

80050

-

80051

g->status = Gsyscall;

80052

80053

if(runtime_atomicload(&runtime_sched.sysmonwait)) { // TODO: fast atomic

80054

@@ -2239,6 +2255,14 @@

80055

if(prof.fn == nil || prof.hz == 0)

80056

return;

80057

80058

+ if(runtime_atomicload(&runtime_in_callers) > 0) {

80059

+ // If SIGPROF arrived while already fetching runtime

80060

+ // callers we can have trouble on older systems

80061

+ // because the unwind library calls dl_iterate_phdr

80062

+ // which was not recursive in the past.

80063

+ return;

80064

+ }

80065

+

80066

runtime_lock(&prof);

80067

if(prof.fn == nil) {

80068

runtime_unlock(&prof);

80069

Index: libgo/runtime/mgc0.c

80070

===================================================================

80071

--- a/src/libgo/runtime/mgc0.c (.../tags/gcc_4_8_2_release)

80072

+++ b/src/libgo/runtime/mgc0.c (.../branches/gcc-4_8-branch)

80073

@@ -174,7 +174,7 @@

80074

Obj *roots;

80075

uint32 nroot;

80076

uint32 rootcap;

80077

-} work;

80078

+} work __attribute__((aligned(8)));

80079

80080

enum {

80081

GC_DEFAULT_PTR = GC_NUM_INSTR,

80082

@@ -239,8 +239,7 @@

80083

// (Manually inlined copy of MHeap_LookupMaybe.)

80084

k = (uintptr)obj>>PageShift;

80085

x = k;

80086

- if(sizeof(void*) == 8)

80087

- x -= (uintptr)runtime_mheap->arena_start>>PageShift;

80088

+ x -= (uintptr)runtime_mheap->arena_start>>PageShift;

80089

s = runtime_mheap->map[x];

80090

if(s == nil || k < s->start || k - s->start >= s->npages || s->state != MSpanInUse)

80091

return false;

80092

@@ -418,8 +417,7 @@

80093

// (Manually inlined copy of MHeap_LookupMaybe.)

80094

k = (uintptr)obj>>PageShift;

80095

x = k;

80096

- if(sizeof(void*) == 8)

80097

- x -= (uintptr)arena_start>>PageShift;

80098

+ x -= (uintptr)arena_start>>PageShift;

80099

s = runtime_mheap->map[x];

80100

if(s == nil || k < s->start || k - s->start >= s->npages || s->state != MSpanInUse)

80101

continue;

80102

@@ -466,8 +464,7 @@

80103

// Ask span about size class.

80104

// (Manually inlined copy of MHeap_Lookup.)

80105

x = (uintptr)obj >> PageShift;

80106

- if(sizeof(void*) == 8)

80107

- x -= (uintptr)arena_start>>PageShift;

80108

+ x -= (uintptr)arena_start>>PageShift;

80109

s = runtime_mheap->map[x];

80110

80111

PREFETCH(obj);

80112

@@ -585,8 +582,7 @@

80113

if(t == nil)

80114

return;

80115

x = (uintptr)obj >> PageShift;

80116

- if(sizeof(void*) == 8)

80117

- x -= (uintptr)(runtime_mheap->arena_start)>>PageShift;

80118

+ x -= (uintptr)(runtime_mheap->arena_start)>>PageShift;

80119

s = runtime_mheap->map[x];

80120

objstart = (byte*)((uintptr)s->start<<PageShift);

80121

if(s->sizeclass != 0) {

80122

Index: libgo/runtime/go-signal.c

80123

===================================================================

80124

--- a/src/libgo/runtime/go-signal.c (.../tags/gcc_4_8_2_release)

80125

+++ b/src/libgo/runtime/go-signal.c (.../branches/gcc-4_8-branch)

80126

@@ -234,7 +234,7 @@

80127

G *g;

80128

80129

g = runtime_g ();

80130

- runtime_traceback (g);

80131

+ runtime_traceback ();

80132

runtime_tracebackothers (g);

80133

80134

/* The gc library calls runtime_dumpregs here, and provides

80135

@@ -399,6 +399,9 @@

80136

{

80137

G *gp;

80138

M *mp;

80139

+#ifdef USING_SPLIT_STACK

80140

+ void *stack_context[10];

80141

+#endif

80142

80143

/* We are now running on the stack registered via sigaltstack.

80144

(Actually there is a small span of time between runtime_siginit

80145

@@ -409,7 +412,7 @@

80146

if (gp != NULL)

80147

{

80148

#ifdef USING_SPLIT_STACK

80149

- __splitstack_getcontext (&gp->stack_context[0]);

80150

+ __splitstack_getcontext (&stack_context[0]);

80151

#endif

80152

}

80153

80154

@@ -432,7 +435,7 @@

80155

if (gp != NULL)

80156

{

80157

#ifdef USING_SPLIT_STACK

80158

- __splitstack_setcontext (&gp->stack_context[0]);

80159

+ __splitstack_setcontext (&stack_context[0]);

80160

#endif

80161

}

80162

}

80163

Index: libgo/runtime/go-callers.c

80164

===================================================================

80165

--- a/src/libgo/runtime/go-callers.c (.../tags/gcc_4_8_2_release)

80166

+++ b/src/libgo/runtime/go-callers.c (.../branches/gcc-4_8-branch)

80167

@@ -11,6 +11,13 @@

80168

#include "runtime.h"

80169

#include "array.h"

80170

80171

+/* This is set to non-zero when calling backtrace_full. This is used

80172

+ to avoid getting hanging on a recursive lock in dl_iterate_phdr on

80173

+ older versions of glibc when a SIGPROF signal arrives while

80174

+ collecting a backtrace. */

80175

+

80176

+uint32 runtime_in_callers;

80177

+

80178

/* Argument passed to callback function. */

80179

80180

struct callers_data

80181

@@ -111,8 +118,10 @@

80182

data.skip = skip + 1;

80183

data.index = 0;

80184

data.max = m;

80185

+ runtime_xadd (&runtime_in_callers, 1);

80186

backtrace_full (__go_get_backtrace_state (), 0, callback, error_callback,

80187

&data);

80188

+ runtime_xadd (&runtime_in_callers, -1);

80189

return data.index;

80190

}

80191

80192

Index: libgo/runtime/go-cdiv.c

80193

===================================================================

80194

--- a/src/libgo/runtime/go-cdiv.c (.../tags/gcc_4_8_2_release)

80195

+++ b/src/libgo/runtime/go-cdiv.c (.../branches/gcc-4_8-branch)

80196

@@ -0,0 +1,46 @@

80197

+/* go-cdiv.c -- complex division routines

80198

+

80199

80200

+ Use of this source code is governed by a BSD-style

80201

+ license that can be found in the LICENSE file. */

80202

+

80203

+/* Calls to these functions are generated by the Go frontend for

80204

+ division of complex64 or complex128. We use these because Go's

80205

+ complex division expects slightly different results from the GCC

80206

+ default. When dividing NaN+1.0i / 0+0i, Go expects NaN+NaNi but

80207

+ GCC generates NaN+Infi. NaN+Infi seems wrong seems the rules of

80208

+ C99 Annex G specify that if either side of a complex number is Inf,

80209

+ the the whole number is Inf, but an operation involving NaN ought

80210

+ to result in NaN, not Inf. */

80211

+

80212

+__complex float

80213

+__go_complex64_div (__complex float a, __complex float b)

80214

+{

80215

+ if (__builtin_expect (b == 0+0i, 0))

80216

+ {

80217

+ if (!__builtin_isinff (__real__ a)

80218

+ && !__builtin_isinff (__imag__ a)

80219

+ && (__builtin_isnanf (__real__ a) || __builtin_isnanf (__imag__ a)))

80220

+ {

80221

+ /* Pass "1" to nanf to match math/bits.go. */

80222

+ return __builtin_nanf("1") + __builtin_nanf("1")*1i;

80223

+ }

80224

+ }

80225

+ return a / b;

80226

+}

80227

+

80228

+__complex double

80229

+__go_complex128_div (__complex double a, __complex double b)

80230

+{

80231

+ if (__builtin_expect (b == 0+0i, 0))

80232

+ {

80233

+ if (!__builtin_isinf (__real__ a)

80234

+ && !__builtin_isinf (__imag__ a)

80235

+ && (__builtin_isnan (__real__ a) || __builtin_isnan (__imag__ a)))

80236

+ {

80237

+ /* Pass "1" to nan to match math/bits.go. */

80238

+ return __builtin_nan("1") + __builtin_nan("1")*1i;

80239

+ }

80240

+ }

80241

+ return a / b;

80242

+}

80243

Index: libgo/runtime/go-reflect-call.c

80244

===================================================================

80245

--- a/src/libgo/runtime/go-reflect-call.c (.../tags/gcc_4_8_2_release)

80246

+++ b/src/libgo/runtime/go-reflect-call.c (.../branches/gcc-4_8-branch)

80247

@@ -98,9 +98,12 @@

80248

const struct __go_struct_field *fields;

80249

int i;

80250

80251

+ field_count = descriptor->__fields.__count;

80252

+ if (field_count == 0) {

80253

+ return &ffi_type_void;

80254

+ }

80255

ret = (ffi_type *) __go_alloc (sizeof (ffi_type));

80256

ret->type = FFI_TYPE_STRUCT;

80257

- field_count = descriptor->__fields.__count;

80258

fields = (const struct __go_struct_field *) descriptor->__fields.__values;

80259

ret->elements = (ffi_type **) __go_alloc ((field_count + 1)

80260

* sizeof (ffi_type *));

80261

Index: libgo/runtime/go-recover.c

80262

===================================================================

80263

--- a/src/libgo/runtime/go-recover.c (.../tags/gcc_4_8_2_release)

80264

+++ b/src/libgo/runtime/go-recover.c (.../branches/gcc-4_8-branch)

80265

@@ -16,12 +16,14 @@

80266

__go_can_recover--this is, the thunk. */

80267

80268

_Bool

80269

-__go_can_recover (const void* retaddr)

80270

+__go_can_recover (const void *retaddr)

80271

{

80272

G *g;

80273

struct __go_defer_stack *d;

80274

const char* ret;

80275

const char* dret;

80276

+ Location loc;

80277

+ const byte *name;

80278

80279

g = runtime_g ();

80280

80281

@@ -52,9 +54,80 @@

80282

#endif

80283

80284

dret = (const char *) d->__retaddr;

80285

- return ret <= dret && ret + 16 >= dret;

80286

+ if (ret <= dret && ret + 16 >= dret)

80287

+ return 1;

80288

+

80289

+ /* If the function calling recover was created by reflect.MakeFunc,

80290

+ then RETADDR will be somewhere in libffi. Our caller is

80291

+ permitted to recover if it was called from libffi. */

80292

+ if (!d->__makefunc_can_recover)

80293

+ return 0;

80294

+

80295

+ if (runtime_callers (2, &loc, 1) < 1)

80296

+ return 0;

80297

+

80298

+ /* If we have no function name, then we weren't called by Go code.

80299

+ Guess that we were called by libffi. */

80300

+ if (loc.function.len == 0)

80301

+ return 1;

80302

+

80303

+ if (loc.function.len < 4)

80304

+ return 0;

80305

+ name = loc.function.str;

80306

+ if (*name == '_')

80307

+ {

80308

+ if (loc.function.len < 5)

80309

+ return 0;

80310

+ ++name;

80311

+ }

80312

+

80313

+ if (name[0] == 'f' && name[1] == 'f' && name[2] == 'i' && name[3] == '_')

80314

+ return 1;

80315

+

80316

+ /* We may also be called by reflect.makeFuncImpl.call, for a

80317

+ function created by reflect.MakeFunc. */

80318

+ if (__builtin_strstr ((const char *) name, "makeFuncImpl") != NULL)

80319

+ return 1;

80320

+

80321

+ return 0;

80322

}

80323

80324

+/* This function is called when code is about to enter a function

80325

+ created by reflect.MakeFunc. It is called by the function stub

80326

+ used by MakeFunc. If the stub is permitted to call recover, then a

80327

+ real MakeFunc function is permitted to call recover. */

80328

+

80329

+void

80330

+__go_makefunc_can_recover (const void *retaddr)

80331

+{

80332

+ struct __go_defer_stack *d;

80333

+

80334

+ d = runtime_g ()->defer;

80335

+ if (d != NULL

80336

+ && !d->__makefunc_can_recover

80337

+ && __go_can_recover (retaddr))

80338

+ d->__makefunc_can_recover = 1;

80339

+}

80340

+

80341

+/* This function is called when code is about to exit a function

80342

+ created by reflect.MakeFunc. It is called by the function stub

80343

+ used by MakeFunc. It clears the __makefunc_can_recover field.

80344

+ It's OK to always clear this field, because __go_can_recover will

80345

+ only be called by a stub created for a function that calls recover.

80346

+ That stub will not call a function created by reflect.MakeFunc, so

80347

+ by the time we get here any caller higher up on the call stack no

80348

+ longer needs the information. */

80349

+

80350

+void

80351

+__go_makefunc_returning (void)

80352

+{

80353

+ struct __go_defer_stack *d;

80354

+

80355

+ d = runtime_g ()->defer;

80356

+ if (d != NULL)

80357

+ d->__makefunc_can_recover = 0;

80358

+}

80359

+

80360

/* This is only called when it is valid for the caller to recover the

80361

value on top of the panic stack, if there is one. */

80362

80363

Index: libgo/runtime/malloc.goc

80364

===================================================================

80365

--- a/src/libgo/runtime/malloc.goc (.../tags/gcc_4_8_2_release)

80366

+++ b/src/libgo/runtime/malloc.goc (.../branches/gcc-4_8-branch)

80367

@@ -541,8 +541,7 @@

80368

80369

// (Manually inlined copy of runtime_MHeap_Lookup)

80370

p = (uintptr)v>>PageShift;

80371

- if(sizeof(void*) == 8)

80372

- p -= (uintptr)runtime_mheap->arena_start >> PageShift;

80373

+ p -= (uintptr)runtime_mheap->arena_start >> PageShift;

80374

s = runtime_mheap->map[p];

80375

80376

if(s->sizeclass == 0) {

80377

Index: libgo/runtime/go-make-slice.c

80378

===================================================================

80379

--- a/src/libgo/runtime/go-make-slice.c (.../tags/gcc_4_8_2_release)

80380

+++ b/src/libgo/runtime/go-make-slice.c (.../branches/gcc-4_8-branch)

80381

@@ -34,7 +34,10 @@

80382

std = (const struct __go_slice_type *) td;

80383

80384

ilen = (intgo) len;

80385

- if (ilen < 0 || (uintptr_t) ilen != len)

80386

+ if (ilen < 0

80387

+ || (uintptr_t) ilen != len

80388

+ || (std->__element_type->__size > 0

80389

+ && len > MaxMem / std->__element_type->__size))

80390

runtime_panicstring ("makeslice: len out of range");

80391

80392

icap = (intgo) cap;

80393

Index: libgo/runtime/mheap.c

80394

===================================================================

80395

--- a/src/libgo/runtime/mheap.c (.../tags/gcc_4_8_2_release)

80396

+++ b/src/libgo/runtime/mheap.c (.../branches/gcc-4_8-branch)

80397

@@ -150,8 +150,7 @@

80398

runtime_MSpan_Init(t, s->start + npage, s->npages - npage);

80399

s->npages = npage;

80400

p = t->start;

80401

- if(sizeof(void*) == 8)

80402

- p -= ((uintptr)h->arena_start>>PageShift);

80403

+ p -= ((uintptr)h->arena_start>>PageShift);

80404

if(p > 0)

80405

h->map[p-1] = s;

80406

h->map[p] = t;

80407

@@ -169,8 +168,7 @@

80408

s->elemsize = (sizeclass==0 ? s->npages<<PageShift : (uintptr)runtime_class_to_size[sizeclass]);

80409

s->types.compression = MTypes_Empty;

80410

p = s->start;

80411

- if(sizeof(void*) == 8)

80412

- p -= ((uintptr)h->arena_start>>PageShift);

80413

+ p -= ((uintptr)h->arena_start>>PageShift);

80414

for(n=0; n<npage; n++)

80415

h->map[p+n] = s;

80416

return s;

80417

@@ -241,8 +239,7 @@

80418

mstats.mspan_sys = h->spanalloc.sys;

80419

runtime_MSpan_Init(s, (uintptr)v>>PageShift, ask>>PageShift);

80420

p = s->start;

80421

- if(sizeof(void*) == 8)

80422

- p -= ((uintptr)h->arena_start>>PageShift);

80423

+ p -= ((uintptr)h->arena_start>>PageShift);

80424

h->map[p] = s;

80425

h->map[p + s->npages - 1] = s;

80426

s->state = MSpanInUse;

80427

@@ -259,8 +256,7 @@

80428

uintptr p;

80429

80430

p = (uintptr)v;

80431

- if(sizeof(void*) == 8)

80432

- p -= (uintptr)h->arena_start;

80433

+ p -= (uintptr)h->arena_start;

80434

return h->map[p >> PageShift];

80435

}

80436

80437

@@ -281,8 +277,7 @@

80438

return nil;

80439

p = (uintptr)v>>PageShift;

80440

q = p;

80441

- if(sizeof(void*) == 8)

80442

- q -= (uintptr)h->arena_start >> PageShift;

80443

+ q -= (uintptr)h->arena_start >> PageShift;

80444

s = h->map[q];

80445

if(s == nil || p < s->start || p - s->start >= s->npages)

80446

return nil;

80447

@@ -332,8 +327,7 @@

80448

80449

// Coalesce with earlier, later spans.

80450

p = s->start;

80451

- if(sizeof(void*) == 8)

80452

- p -= (uintptr)h->arena_start >> PageShift;

80453

+ p -= (uintptr)h->arena_start >> PageShift;

80454

if(p > 0 && (t = h->map[p-1]) != nil && t->state != MSpanInUse) {

80455

tp = (uintptr*)(t->start<<PageShift);

80456

*tp |= *sp; // propagate "needs zeroing" mark

80457

Index: libgo/testsuite/gotest

80458

===================================================================

80459

--- a/src/libgo/testsuite/gotest (.../tags/gcc_4_8_2_release)

80460

+++ b/src/libgo/testsuite/gotest (.../branches/gcc-4_8-branch)

80461

@@ -369,7 +369,7 @@

80462

{

80463

text="T"

80464

case "$GOARCH" in

80465

- ppc64) text="D" ;;

80466

+ ppc64) text="[TD]" ;;

80467

esac

80468

80469

symtogo='sed -e s/_test/XXXtest/ -e s/.*_$[^_]*\.$/\1/ -e s/XXXtest/_test/'

80470

Index: libgo/mksysinfo.sh

80471

===================================================================

80472

--- a/src/libgo/mksysinfo.sh (.../tags/gcc_4_8_2_release)

80473

+++ b/src/libgo/mksysinfo.sh (.../branches/gcc-4_8-branch)

80474

@@ -1035,6 +1035,10 @@

80475

grep '^const _LOCK_' gen-sysinfo.go |

80476

sed -e 's/^$const $_$LOCK_[^= ]*$$.*$$/\1\2 = _\2/' >> ${OUT}

80477

80478

+# The PRIO constants.

80479

+grep '^const _PRIO_' gen-sysinfo.go | \

80480

+ sed -e 's/^$const $_$PRIO_[^= ]*$$.*$$/\1\2 = _\2/' >> ${OUT}

80481

+

80482

# The GNU/Linux LINUX_REBOOT flags.

80483

grep '^const _LINUX_REBOOT_' gen-sysinfo.go |

80484

sed -e 's/^$const $_$LINUX_REBOOT_[^= ]*$$.*$$/\1\2 = _\2/' >> ${OUT}

80485

Index: libgo/config.h.in

80486

===================================================================

80487

--- a/src/libgo/config.h.in (.../tags/gcc_4_8_2_release)

80488

+++ b/src/libgo/config.h.in (.../branches/gcc-4_8-branch)

80489

@@ -39,6 +39,9 @@

80490

/* Define to 1 if you have the `dl_iterate_phdr' function. */

80491

#undef HAVE_DL_ITERATE_PHDR

80492

80493

+/* Define to 1 if you have the `dup3' function. */

80494

+#undef HAVE_DUP3

80495

+

80496

/* Define to 1 if you have the `epoll_create1' function. */

80497

#undef HAVE_EPOLL_CREATE1

80498

80499

@@ -66,6 +69,9 @@

80500

/* Define if _Unwind_GetIPInfo is available. */

80501

#undef HAVE_GETIPINFO

80502

80503

+/* Define to 1 if you have the `getxattr' function. */

80504

+#undef HAVE_GETXATTR

80505

+

80506

/* Define to 1 if you have the `inotify_add_watch' function. */

80507

#undef HAVE_INOTIFY_ADD_WATCH

80508

80509

@@ -111,6 +117,9 @@

80510

/* Define to 1 if you have the <linux/rtnetlink.h> header file. */

80511

#undef HAVE_LINUX_RTNETLINK_H

80512

80513

+/* Define to 1 if you have the `listxattr' function. */

80514

+#undef HAVE_LISTXATTR

80515

+

80516

/* Define to 1 if the system has the type `loff_t'. */

80517

#undef HAVE_LOFF_T

80518

80519

@@ -171,6 +180,9 @@

80520

/* Define to 1 if you have the `pipe2' function. */

80521

#undef HAVE_PIPE2

80522

80523

+/* Define to 1 if you have the `removexattr' function. */

80524

+#undef HAVE_REMOVEXATTR

80525

+

80526

/* Define to 1 if you have the `renameat' function. */

80527

#undef HAVE_RENAMEAT

80528

80529

@@ -180,6 +192,9 @@

80530

/* Define to 1 if you have the `setenv' function. */

80531

#undef HAVE_SETENV

80532

80533

+/* Define to 1 if you have the `setxattr' function. */

80534

+#undef HAVE_SETXATTR

80535

+

80536

/* Define to 1 if you have the `sinl' function. */

80537

#undef HAVE_SINL

80538

80539

Index: libgo/configure.ac

80540

===================================================================

80541

--- a/src/libgo/configure.ac (.../tags/gcc_4_8_2_release)

80542

+++ b/src/libgo/configure.ac (.../branches/gcc-4_8-branch)

80543

@@ -503,7 +503,7 @@

80544

AM_CONDITIONAL(HAVE_STRERROR_R, test "$ac_cv_func_strerror_r" = yes)

80545

AM_CONDITIONAL(HAVE_WAIT4, test "$ac_cv_func_wait4" = yes)

80546

80547

-AC_CHECK_FUNCS(accept4 epoll_create1 faccessat fallocate fchmodat fchownat futimesat inotify_add_watch inotify_init inotify_init1 inotify_rm_watch mkdirat mknodat openat pipe2 renameat sync_file_range splice tee unlinkat unshare utimensat)

80548

+AC_CHECK_FUNCS(accept4 dup3 epoll_create1 faccessat fallocate fchmodat fchownat futimesat getxattr inotify_add_watch inotify_init inotify_init1 inotify_rm_watch listxattr mkdirat mknodat openat pipe2 removexattr renameat setxattr sync_file_range splice tee unlinkat unshare utimensat)

80549

AC_TYPE_OFF_T

80550

AC_CHECK_TYPES([loff_t])

80551

80552

Index: libgo/config/libtool.m4

80553

===================================================================

80554

--- a/src/libgo/config/libtool.m4 (.../tags/gcc_4_8_2_release)

80555

+++ b/src/libgo/config/libtool.m4 (.../branches/gcc-4_8-branch)

80556

@@ -1225,7 +1225,7 @@

80557

rm -rf conftest*

80558

;;

80559

80560

-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \

80561

+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \

80562

s390*-*linux*|s390*-*tpf*|sparc*-*linux*)

80563

# Find out which ABI we are using.

80564

echo 'int i;' > conftest.$ac_ext

80565

@@ -1239,7 +1239,10 @@

80566

x86_64-*linux*)

80567

LD="${LD-ld} -m elf_i386"

80568

;;

80569

- ppc64-*linux*|powerpc64-*linux*)

80570

+ powerpc64le-*linux*)

80571

+ LD="${LD-ld} -m elf32lppclinux"

80572

+ ;;

80573

+ powerpc64-*linux*)

80574

LD="${LD-ld} -m elf32ppclinux"

80575

;;

80576

s390x-*linux*)

80577

@@ -1258,7 +1261,10 @@

80578

x86_64-*linux*)

80579

LD="${LD-ld} -m elf_x86_64"

80580

;;

80581

- ppc*-*linux*|powerpc*-*linux*)

80582

+ powerpcle-*linux*)

80583

+ LD="${LD-ld} -m elf64lppc"

80584

+ ;;

80585

+ powerpc-*linux*)

80586

LD="${LD-ld} -m elf64ppc"

80587

;;

80588

s390*-*linux*|s390*-*tpf*)

80589

Index: libgo/go/reflect/value.go

80590

===================================================================

80591

--- a/src/libgo/go/reflect/value.go (.../tags/gcc_4_8_2_release)

80592

+++ b/src/libgo/go/reflect/value.go (.../branches/gcc-4_8-branch)

80593

@@ -98,6 +98,7 @@

80594

flagIndir

80595

flagAddr

80596

flagMethod

80597

+ flagMethodFn // gccgo: first fn parameter is always pointer

80598

flagKindShift = iota

80599

flagKindWidth = 5 // there are 27 kinds

80600

flagKindMask flag = 1<<flagKindWidth - 1

80601

@@ -433,7 +434,7 @@

80602

if v.flag&flagMethod != 0 {

80603

nin++

80604

}

80605

- firstPointer := len(in) > 0 && t.In(0).Kind() != Ptr && v.flag&flagMethod == 0 && isMethod(v.typ)

80606

+ firstPointer := len(in) > 0 && t.In(0).Kind() != Ptr && v.flag&flagMethodFn != 0

80607

params := make([]unsafe.Pointer, nin)

80608

off := 0

80609

if v.flag&flagMethod != 0 {

80610

@@ -484,33 +485,6 @@

80611

return ret

80612

}

80613

80614

-// gccgo specific test to see if typ is a method. We can tell by

80615

-// looking at the string to see if there is a receiver. We need this

80616

-// because for gccgo all methods take pointer receivers.

80617

-func isMethod(t *rtype) bool {

80618

- if Kind(t.kind) != Func {

80619

- return false

80620

- }

80621

- s := *t.string

80622

- parens := 0

80623

- params := 0

80624

- sawRet := false

80625

- for i, c := range s {

80626

- if c == '(' {

80627

- if parens == 0 {

80628

- params++

80629

- }

80630

- parens++

80631

- } else if c == ')' {

80632

- parens--

80633

- } else if parens == 0 && c == ' ' && s[i+1] != '(' && !sawRet {

80634

- params++

80635

- sawRet = true

80636

- }

80637

- }

80638

- return params > 2

80639

-}

80640

-

80641

// methodReceiver returns information about the receiver

80642

// described by v. The Value v may or may not have the

80643

// flagMethod bit set, so the kind cached in v.flag should

80644

@@ -917,6 +891,16 @@

80645

v = makeMethodValue("Interface", v)

80646

}

80647

80648

+ if v.flag&flagMethodFn != 0 {

80649

+ if v.typ.Kind() != Func {

80650

+ panic("reflect: MethodFn of non-Func")

80651

+ }

80652

+ ft := (*funcType)(unsafe.Pointer(v.typ))

80653

+ if ft.in[0].Kind() != Ptr {

80654

+ v = makeValueMethod(v)

80655

+ }

80656

+ }

80657

+

80658

k := v.kind()

80659

if k == Interface {

80660

// Special case: return the element inside the interface.

80661

@@ -1230,8 +1214,7 @@

80662

// created via reflect have the same underlying code pointer,

80663

// so their Pointers are equal. The function used here must

80664

// match the one used in makeMethodValue.

80665

- // This is not properly implemented for gccgo.

80666

- f := Zero

80667

+ f := makeFuncStub

80668

return **(**uintptr)(unsafe.Pointer(&f))

80669

}

80670

p := v.val

80671

Index: libgo/go/reflect/makefuncgo_386.go

80672

===================================================================

80673

--- a/src/libgo/go/reflect/makefuncgo_386.go (.../tags/gcc_4_8_2_release)

80674

+++ b/src/libgo/go/reflect/makefuncgo_386.go (.../branches/gcc-4_8-branch)

80675

@@ -14,8 +14,10 @@

80676

// registers that might hold result values.

80677

type i386Regs struct {

80678

esp uint32

80679

- eax uint32 // Value to return in %eax.

80680

- st0 uint64 // Value to return in %st(0).

80681

+ eax uint32 // Value to return in %eax.

80682

+ st0 float64 // Value to return in %st(0).

80683

+ sr bool // Set to true if hidden struct pointer.

80684

+ sf bool // Set to true if returning float

80685

}

80686

80687

// MakeFuncStubGo implements the 386 calling convention for MakeFunc.

80688

@@ -56,10 +58,13 @@

80689

in := make([]Value, 0, len(ftyp.in))

80690

ap := uintptr(regs.esp)

80691

80692

+ regs.sr = false

80693

+ regs.sf = false

80694

var retPtr unsafe.Pointer

80695

if retStruct {

80696

retPtr = *(*unsafe.Pointer)(unsafe.Pointer(ap))

80697

ap += ptrSize

80698

+ regs.sr = true

80699

}

80700

80701

for _, rt := range ftyp.in {

80702

@@ -77,7 +82,7 @@

80703

80704

// Call the real function.

80705

80706

- out := c.fn(in)

80707

+ out := c.call(in)

80708

80709

if len(out) != len(ftyp.out) {

80710

panic("reflect: wrong return count from function created by MakeFunc")

80711

@@ -123,13 +128,16 @@

80712

80713

v := out[0]

80714

w := v.iword()

80715

- if v.Kind() != Ptr && v.Kind() != UnsafePointer {

80716

- w = loadIword(unsafe.Pointer(w), v.typ.size)

80717

- }

80718

switch v.Kind() {

80719

- case Float32, Float64:

80720

- regs.st0 = uint64(uintptr(w))

80721

+ case Ptr, UnsafePointer:

80722

+ regs.eax = uint32(uintptr(w))

80723

+ case Float32:

80724

+ regs.st0 = float64(*(*float32)(unsafe.Pointer(w)))

80725

+ regs.sf = true

80726

+ case Float64:

80727

+ regs.st0 = *(*float64)(unsafe.Pointer(w))

80728

+ regs.sf = true

80729

default:

80730

- regs.eax = uint32(uintptr(w))

80731

+ regs.eax = uint32(uintptr(loadIword(unsafe.Pointer(w), v.typ.size)))

80732

}

80733

}

80734

Index: libgo/go/reflect/makefunc_amd64.S

80735

===================================================================

80736

--- a/src/libgo/go/reflect/makefunc_amd64.S (.../tags/gcc_4_8_2_release)

80737

+++ b/src/libgo/go/reflect/makefunc_amd64.S (.../branches/gcc-4_8-branch)

80738

@@ -61,6 +61,14 @@

80739

movdqa %xmm6, 0xa0(%rsp)

80740

movdqa %xmm7, 0xb0(%rsp)

80741

80742

+ /* For MakeFunc functions that call recover. */

80743

+ movq 8(%rbp), %rdi

80744

+#ifdef __PIC__

80745

+ call __go_makefunc_can_recover@PLT

80746

+#else

80747

+ call __go_makefunc_can_recover

80748

+#endif

80749

+

80750

# Get function type.

80751

#ifdef __PIC__

80752

call __go_get_closure@PLT

80753

@@ -77,6 +85,13 @@

80754

call reflect.MakeFuncStubGo

80755

#endif

80756

80757

+ /* MakeFunc functions can no longer call recover. */

80758

+#ifdef __PIC__

80759

+ call __go_makefunc_returning@PLT

80760

+#else

80761

+ call __go_makefunc_returning

80762

+#endif

80763

+

80764

# The structure will be updated with any return values. Load

80765

# all possible return registers before returning to the caller.

80766

80767

Index: libgo/go/reflect/type.go

80768

===================================================================

80769

--- a/src/libgo/go/reflect/type.go (.../tags/gcc_4_8_2_release)

80770

+++ b/src/libgo/go/reflect/type.go (.../branches/gcc-4_8-branch)

80771

@@ -508,7 +508,7 @@

80772

m.Type = toType(mt)

80773

x := new(unsafe.Pointer)

80774

*x = unsafe.Pointer(&p.tfn)

80775

- m.Func = Value{mt, unsafe.Pointer(x), fl | flagIndir}

80776

+ m.Func = Value{mt, unsafe.Pointer(x), fl | flagIndir | flagMethodFn}

80777

m.Index = i

80778

return

80779

}

80780

Index: libgo/go/reflect/makefunc_386.S

80781

===================================================================

80782

--- a/src/libgo/go/reflect/makefunc_386.S (.../tags/gcc_4_8_2_release)

80783

+++ b/src/libgo/go/reflect/makefunc_386.S (.../branches/gcc-4_8-branch)

80784

@@ -25,9 +25,13 @@

80785

struct {

80786

esp uint32 // 0x0

80787

eax uint32 // 0x4

80788

- st0 uint64 // 0x8

80789

+ st0 float64 // 0x8

80790

+ sr bool // 0x10

80791

+ sf bool // 0x11

80792

}

80793

- */

80794

+ The sr field is set by the function to a non-zero value if

80795

+ the function takes a struct hidden pointer that must be

80796

+ popped off the stack. */

80797

80798

pushl %ebp

80799

.LCFI0:

80800

@@ -45,7 +49,16 @@

80801

leal 8(%ebp), %eax /* Set esp field in struct. */

80802

movl %eax, -24(%ebp)

80803

80804

+ /* For MakeFunc functions that call recover. */

80805

+ movl 4(%ebp), %eax

80806

+ movl %eax, (%esp)

80807

#ifdef __PIC__

80808

+ call __go_makefunc_can_recover@PLT

80809

+#else

80810

+ call __go_makefunc_can_recover

80811

+#endif

80812

+

80813

+#ifdef __PIC__

80814

call __go_get_closure@PLT

80815

#else

80816

call __go_get_closure

80817

@@ -62,9 +75,20 @@

80818

call reflect.MakeFuncStubGo

80819

#endif

80820

80821

+ /* MakeFunc functions can no longer call recover. */

80822

+#ifdef __PIC__

80823

+ call __go_makefunc_returning@PLT

80824

+#else

80825

+ call __go_makefunc_returning

80826

+#endif

80827

+

80828

/* Set return registers. */

80829

80830

movl -20(%ebp), %eax

80831

+

80832

+ cmpb $0, -7(%ebp)

80833

+ je 2f

80834

+

80835

fldl -16(%ebp)

80836

80837

#ifdef __SSE2__

80838

@@ -73,12 +97,20 @@

80839

movsd -16(%ebp), %xmm0

80840

#endif

80841

80842

+2:

80843

+ movb -8(%ebp), %dl

80844

+

80845

addl $36, %esp

80846

popl %ebx

80847

.LCFI3:

80848

popl %ebp

80849

.LCFI4:

80850

+

80851

+ testb %dl,%dl

80852

+ jne 1f

80853

ret

80854

+1:

80855

+ ret $4

80856

.LFE1:

80857

#ifdef __ELF__

80858

.size reflect.makeFuncStub, . - reflect.makeFuncStub

80859

Index: libgo/go/reflect/all_test.go

80860

===================================================================

80861

--- a/src/libgo/go/reflect/all_test.go (.../tags/gcc_4_8_2_release)

80862

+++ b/src/libgo/go/reflect/all_test.go (.../branches/gcc-4_8-branch)

80863

@@ -1430,6 +1430,46 @@

80864

}

80865

}

80866

80867

+type emptyStruct struct{}

80868

+

80869

+type nonEmptyStruct struct {

80870

+ member int

80871

+}

80872

+

80873

+func returnEmpty() emptyStruct {

80874

+ return emptyStruct{}

80875

+}

80876

+

80877

+func takesEmpty(e emptyStruct) {

80878

+}

80879

+

80880

+func returnNonEmpty(i int) nonEmptyStruct {

80881

+ return nonEmptyStruct{member: i}

80882

+}

80883

+

80884

+func takesNonEmpty(n nonEmptyStruct) int {

80885

+ return n.member

80886

+}

80887

+

80888

+func TestCallWithStruct(t *testing.T) {

80889

+ r := ValueOf(returnEmpty).Call([]Value{})

80890

+ if len(r) != 1 || r[0].Type() != TypeOf(emptyStruct{}) {

80891

+ t.Errorf("returning empty struct returned %s instead", r)

80892

+ }

80893

+ r = ValueOf(takesEmpty).Call([]Value{ValueOf(emptyStruct{})})

80894

+ if len(r) != 0 {

80895

+ t.Errorf("takesEmpty returned values: %s", r)

80896

+ }

80897

+ r = ValueOf(returnNonEmpty).Call([]Value{ValueOf(42)})

80898

+ if len(r) != 1 || r[0].Type() != TypeOf(nonEmptyStruct{}) || r[0].Field(0).Int() != 42 {

80899

+ t.Errorf("returnNonEmpty returned %s", r)

80900

+ }

80901

+ r = ValueOf(takesNonEmpty).Call([]Value{ValueOf(nonEmptyStruct{member: 42})})

80902

+ if len(r) != 1 || r[0].Type() != TypeOf(1) || r[0].Int() != 42 {

80903

+ t.Errorf("takesNonEmpty returned %s", r)

80904

+ }

80905

+}

80906

+

80907

func TestMakeFunc(t *testing.T) {

80908

switch runtime.GOARCH {

80909

case "amd64", "386":

80910

@@ -1587,9 +1627,13 @@

80911

}

80912

}

80913

80914

-/* Not yet implemented for gccgo

80915

+func TestMethodValue(t *testing.T) {

80916

+ switch runtime.GOARCH {

80917

+ case "amd64", "386":

80918

+ default:

80919

+ t.Skip("reflect method values not implemented for " + runtime.GOARCH)

80920

+ }

80921

80922

-func TestMethodValue(t *testing.T) {

80923

p := Point{3, 4}

80924

var i int64

80925

80926

@@ -1658,8 +1702,6 @@

80927

}

80928

}

80929

80930

-*/

80931

-

80932

// Reflect version of $GOROOT/test/method5.go

80933

80934

// Concrete types implementing M method.

80935

@@ -1744,7 +1786,12 @@

80936

func (t4 Tm4) M(x int, b byte) (byte, int) { return b, x + 40 }

80937

80938

func TestMethod5(t *testing.T) {

80939

- /* Not yet used for gccgo

80940

+ switch runtime.GOARCH {

80941

+ case "amd64", "386":

80942

+ default:

80943

+ t.Skip("reflect method values not implemented for " + runtime.GOARCH)

80944

+ }

80945

+

80946

CheckF := func(name string, f func(int, byte) (byte, int), inc int) {

80947

b, x := f(1000, 99)

80948

if b != 99 || x != 1000+inc {

80949

@@ -1751,7 +1798,6 @@

80950

t.Errorf("%s(1000, 99) = %v, %v, want 99, %v", name, b, x, 1000+inc)

80951

}

80952

}

80953

- */

80954

80955

CheckV := func(name string, i Value, inc int) {

80956

bx := i.Method(0).Call([]Value{ValueOf(1000), ValueOf(byte(99))})

80957

@@ -1761,9 +1807,7 @@

80958

t.Errorf("direct %s.M(1000, 99) = %v, %v, want 99, %v", name, b, x, 1000+inc)

80959

}

80960

80961

- /* Not yet implemented for gccgo

80962

CheckF(name+".M", i.Method(0).Interface().(func(int, byte) (byte, int)), inc)

80963

- */

80964

}

80965

80966

var TinterType = TypeOf(new(Tinter)).Elem()

80967

Index: libgo/go/reflect/makefunc.go

80968

===================================================================

80969

--- a/src/libgo/go/reflect/makefunc.go (.../tags/gcc_4_8_2_release)

80970

+++ b/src/libgo/go/reflect/makefunc.go (.../branches/gcc-4_8-branch)

80971

@@ -17,6 +17,11 @@

80972

code uintptr

80973

typ *funcType

80974

fn func([]Value) []Value

80975

+

80976

+ // For gccgo we use the same entry point for functions and for

80977

+ // method values.

80978

+ method int

80979

+ rcvr Value

80980

}

80981

80982

// MakeFunc returns a new function of the given Type

80983

@@ -61,7 +66,7 @@

80984

dummy := makeFuncStub

80985

code := **(**uintptr)(unsafe.Pointer(&dummy))

80986

80987

- impl := &makeFuncImpl{code: code, typ: ftyp, fn: fn}

80988

+ impl := &makeFuncImpl{code: code, typ: ftyp, fn: fn, method: -1}

80989

80990

return Value{t, unsafe.Pointer(&impl), flag(Func<<flagKindShift) | flagIndir}

80991

}

80992

@@ -85,15 +90,94 @@

80993

panic("reflect: internal error: invalid use of makePartialFunc")

80994

}

80995

80996

+ switch runtime.GOARCH {

80997

+ case "amd64", "386":

80998

+ default:

80999

+ panic("reflect.makeMethodValue not implemented for " + runtime.GOARCH)

81000

+ }

81001

+

81002

// Ignoring the flagMethod bit, v describes the receiver, not the method type.

81003

fl := v.flag & (flagRO | flagAddr | flagIndir)

81004

fl |= flag(v.typ.Kind()) << flagKindShift

81005

rcvr := Value{v.typ, v.val, fl}

81006

81007

+ // v.Type returns the actual type of the method value.

81008

+ ft := v.Type().(*rtype)

81009

+

81010

+ // Indirect Go func value (dummy) to obtain

81011

+ // actual code address. (A Go func value is a pointer

81012

+ // to a C function pointer. http://golang.org/s/go11func.)

81013

+ dummy := makeFuncStub

81014

+ code := **(**uintptr)(unsafe.Pointer(&dummy))

81015

+

81016

// Cause panic if method is not appropriate.

81017

// The panic would still happen during the call if we omit this,

81018

// but we want Interface() and other operations to fail early.

81019

- methodReceiver(op, rcvr, int(v.flag)>>flagMethodShift)

81020

+ t, _, _ := methodReceiver(op, rcvr, int(v.flag)>>flagMethodShift)

81021

81022

- panic("reflect makeMethodValue not implemented")

81023

+ fv := &makeFuncImpl{

81024

+ code: code,

81025

+ typ: (*funcType)(unsafe.Pointer(t)),

81026

+ method: int(v.flag) >> flagMethodShift,

81027

+ rcvr: rcvr,

81028

+ }

81029

+

81030

+ return Value{ft, unsafe.Pointer(&fv), v.flag&flagRO | flag(Func)<<flagKindShift | flagIndir}

81031

}

81032

+

81033

+// makeValueMethod takes a method function and returns a function that

81034

+// takes a value receiver and calls the real method with a pointer to

81035

+// it.

81036

+func makeValueMethod(v Value) Value {

81037

+ typ := v.typ

81038

+ if typ.Kind() != Func {

81039

+ panic("reflect: call of makeValueMethod with non-Func type")

81040

+ }

81041

+ if v.flag&flagMethodFn == 0 {

81042

+ panic("reflect: call of makeValueMethod with non-MethodFn")

81043

+ }

81044

+

81045

+ switch runtime.GOARCH {

81046

+ case "amd64", "386":

81047

+ default:

81048

+ panic("reflect.makeValueMethod not implemented for " + runtime.GOARCH)

81049

+ }

81050

+

81051

+ t := typ.common()

81052

+ ftyp := (*funcType)(unsafe.Pointer(t))

81053

+

81054

+ // Indirect Go func value (dummy) to obtain

81055

+ // actual code address. (A Go func value is a pointer

81056

+ // to a C function pointer. http://golang.org/s/go11func.)

81057

+ dummy := makeFuncStub

81058

+ code := **(**uintptr)(unsafe.Pointer(&dummy))

81059

+

81060

+ impl := &makeFuncImpl{

81061

+ code: code,

81062

+ typ: ftyp,

81063

+ method: -2,

81064

+ rcvr: v,

81065

+ }

81066

+

81067

+ return Value{t, unsafe.Pointer(&impl), flag(Func<<flagKindShift) | flagIndir}

81068

+}

81069

+

81070

+// Call the function represented by a makeFuncImpl.

81071

+func (c *makeFuncImpl) call(in []Value) []Value {

81072

+ if c.method == -1 {

81073

+ return c.fn(in)

81074

+ } else if c.method == -2 {

81075

+ if c.typ.IsVariadic() {

81076

+ return c.rcvr.CallSlice(in)

81077

+ } else {

81078

+ return c.rcvr.Call(in)

81079

+ }

81080

+ } else {

81081

+ m := c.rcvr.Method(c.method)

81082

+ if c.typ.IsVariadic() {

81083

+ return m.CallSlice(in)

81084

+ } else {

81085

+ return m.Call(in)

81086

+ }

81087

+ }

81088

+}

81089

Index: libgo/go/reflect/makefuncgo_amd64.go

81090

===================================================================

81091

--- a/src/libgo/go/reflect/makefuncgo_amd64.go (.../tags/gcc_4_8_2_release)

81092

+++ b/src/libgo/go/reflect/makefuncgo_amd64.go (.../branches/gcc-4_8-branch)

81093

@@ -319,7 +319,7 @@

81094

// All the real arguments have been found and turned into

81095

// Value's. Call the real function.

81096

81097

- out := c.fn(in)

81098

+ out := c.call(in)

81099

81100

if len(out) != len(ftyp.out) {

81101

panic("reflect: wrong return count from function created by MakeFunc")

81102

Index: libgo/go/net/fd_unix.go

81103

===================================================================

81104

--- a/src/libgo/go/net/fd_unix.go (.../tags/gcc_4_8_2_release)

81105

+++ b/src/libgo/go/net/fd_unix.go (.../branches/gcc-4_8-branch)

81106

@@ -9,6 +9,7 @@

81107

import (

81108

"io"

81109

"os"

81110

+ "runtime"

81111

"sync"

81112

"syscall"

81113

"time"

81114

@@ -90,6 +91,16 @@

81115

if err == nil || err == syscall.EISCONN {

81116

break

81117

}

81118

+

81119

+ // On Solaris we can see EINVAL if the socket has

81120

+ // already been accepted and closed by the server.

81121

+ // Treat this as a successful connection--writes to

81122

+ // the socket will see EOF. For details and a test

81123

+ // case in C see http://golang.org/issue/6828.

81124

+ if runtime.GOOS == "solaris" && err == syscall.EINVAL {

81125

+ break

81126

+ }

81127

+

81128

if err != syscall.EINPROGRESS && err != syscall.EALREADY && err != syscall.EINTR {

81129

return err

81130

}

81131

Index: libgo/go/go/build/build.go

81132

===================================================================

81133

--- a/src/libgo/go/go/build/build.go (.../tags/gcc_4_8_2_release)

81134

+++ b/src/libgo/go/go/build/build.go (.../branches/gcc-4_8-branch)

81135

@@ -429,7 +429,7 @@

81136

switch ctxt.Compiler {

81137

case "gccgo":

81138

dir, elem := pathpkg.Split(p.ImportPath)

81139

- pkga = "pkg/gccgo/" + dir + "lib" + elem + ".a"

81140

+ pkga = "pkg/gccgo_" + ctxt.GOOS + "_" + ctxt.GOARCH + "/" + dir + "lib" + elem + ".a"

81141

case "gc":

81142

suffix := ""

81143

if ctxt.InstallSuffix != "" {

81144

Index: libgo/go/go/build/syslist.go

81145

===================================================================

81146

--- a/src/libgo/go/go/build/syslist.go (.../tags/gcc_4_8_2_release)

81147

+++ b/src/libgo/go/go/build/syslist.go (.../branches/gcc-4_8-branch)

81148

@@ -0,0 +1,8 @@

81149

81150

+// Use of this source code is governed by a BSD-style

81151

+// license that can be found in the LICENSE file.

81152

+

81153

+package build

81154

+

81155

+const goosList = "darwin dragonfly freebsd linux netbsd openbsd plan9 windows solaris "

81156

+const goarchList = "386 amd64 arm alpha m68k mipso32 mipsn32 mipsn64 mipso64 ppc ppc64 sparc sparc64 "

81157

Index: libgo/go/syscall/libcall_linux.go

81158

===================================================================

81159

--- a/src/libgo/go/syscall/libcall_linux.go (.../tags/gcc_4_8_2_release)

81160

+++ b/src/libgo/go/syscall/libcall_linux.go (.../branches/gcc-4_8-branch)

81161

@@ -190,6 +190,9 @@

81162

//sys Adjtimex(buf *Timex) (state int, err error)

81163

//adjtimex(buf *Timex) _C_int

81164

81165

+//sysnb Dup3(oldfd int, newfd int, flags int) (err error)

81166

+//dup3(oldfd _C_int, newfd _C_int, flags _C_int) _C_int

81167

+

81168

//sys Faccessat(dirfd int, path string, mode uint32, flags int) (err error)

81169

//faccessat(dirfd _C_int, pathname *byte, mode _C_int, flags _C_int) _C_int

81170

81171

@@ -268,6 +271,9 @@

81172

return origlen - len(buf), count, names

81173

}

81174

81175

+//sys Getxattr(path string, attr string, dest []byte) (sz int, err error)

81176

+//getxattr(path *byte, attr *byte, buf *byte, count Size_t) Ssize_t

81177

+

81178

//sys InotifyAddWatch(fd int, pathname string, mask uint32) (watchdesc int, err error)

81179

//inotify_add_watch(fd _C_int, pathname *byte, mask uint32) _C_int

81180

81181

@@ -283,6 +289,9 @@

81182

//sys Klogctl(typ int, buf []byte) (n int, err error)

81183

//klogctl(typ _C_int, bufp *byte, len _C_int) _C_int

81184

81185

+//sys Listxattr(path string, dest []byte) (sz int, err error)

81186

+//listxattr(path *byte, list *byte, size Size_t) Ssize_t

81187

+

81188

//sys Mkdirat(dirfd int, path string, mode uint32) (err error)

81189

//mkdirat(dirfd _C_int, path *byte, mode Mode_t) _C_int

81190

81191

@@ -305,6 +314,9 @@

81192

//sys PivotRoot(newroot string, putold string) (err error)

81193

//pivot_root(newroot *byte, putold *byte) _C_int

81194

81195

+//sys Removexattr(path string, attr string) (err error)

81196

+//removexattr(path *byte, name *byte) _C_int

81197

+

81198

//sys Renameat(olddirfd int, oldpath string, newdirfd int, newpath string) (err error)

81199

//renameat(olddirfd _C_int, oldpath *byte, newdirfd _C_int, newpath *byte) _C_int

81200

81201

@@ -338,6 +350,9 @@

81202

//sysnb Setresuid(ruid int, eguid int, suid int) (err error)

81203

//setresuid(ruid Uid_t, euid Uid_t, suid Uid_t) _C_int

81204

81205

+//sys Setxattr(path string, attr string, data []byte, flags int) (err error)

81206

+//setxattr(path *byte, name *byte, value *byte, size Size_t, flags _C_int) _C_int

81207

+

81208

//sys splice(rfd int, roff *_loff_t, wfd int, woff *_loff_t, len int, flags int) (n int64, err error)

81209

//splice(rfd _C_int, roff *_loff_t, wfd _C_int, woff *_loff_t, len Size_t, flags _C_uint) Ssize_t

81210

func Splice(rfd int, roff *int64, wfd int, woff *int64, len int, flags int) (n int64, err error) {

81211

Index: libgo/go/syscall/socket.go

81212

===================================================================

81213

--- a/src/libgo/go/syscall/socket.go (.../tags/gcc_4_8_2_release)

81214

+++ b/src/libgo/go/syscall/socket.go (.../branches/gcc-4_8-branch)

81215

@@ -25,7 +25,7 @@

81216

Pad [96]int8

81217

}

81218

81219

-const SizeofSockaddrAny = 0x1c

81220

+const SizeofSockaddrAny = 0x6c

81221

81222

type SockaddrInet4 struct {

81223

Port int

81224

Index: libgo/go/syscall/libcall_posix.go

81225

===================================================================

81226

--- a/src/libgo/go/syscall/libcall_posix.go (.../tags/gcc_4_8_2_release)

81227

+++ b/src/libgo/go/syscall/libcall_posix.go (.../branches/gcc-4_8-branch)

81228

@@ -238,6 +238,9 @@

81229

//sysnb Getppid() (ppid int)

81230

//getppid() Pid_t

81231

81232

+//sys Getpriority(which int, who int) (prio int, err error)

81233

+//getpriority(which _C_int, who _C_int) _C_int

81234

+

81235

//sysnb Getrlimit(resource int, rlim *Rlimit) (err error)

81236

//getrlimit(resource _C_int, rlim *Rlimit) _C_int

81237

81238

@@ -307,6 +310,9 @@

81239

//sysnb Setpgid(pid int, pgid int) (err error)

81240

//setpgid(pid Pid_t, pgid Pid_t) _C_int

81241

81242

+//sys Setpriority(which int, who int, prio int) (err error)

81243

+//setpriority(which _C_int, who _C_int, prio _C_int) _C_int

81244

+

81245

//sysnb Setreuid(ruid int, euid int) (err error)

81246

//setreuid(ruid Uid_t, euid Uid_t) _C_int

81247

81248

Index: libgo/Makefile.am

81249

===================================================================

81250

--- a/src/libgo/Makefile.am (.../tags/gcc_4_8_2_release)

81251

+++ b/src/libgo/Makefile.am (.../branches/gcc-4_8-branch)

81252

@@ -424,6 +424,7 @@

81253

runtime/go-caller.c \

81254

runtime/go-callers.c \

81255

runtime/go-can-convert-interface.c \

81256

+ runtime/go-cdiv.c \

81257

runtime/go-cgo.c \

81258

runtime/go-check-interface.c \

81259

runtime/go-construct-map.c \

81260

@@ -1254,7 +1255,7 @@

81261

go/go/build/build.go \

81262

go/go/build/doc.go \

81263

go/go/build/read.go \

81264

- syslist.go

81265

+ go/go/build/syslist.go

81266

go_go_doc_files = \

81267

go/go/doc/comment.go \

81268

go/go/doc/doc.go \

81269

@@ -2712,15 +2713,6 @@

81270

@$(CHECK)

81271

.PHONY: go/build/check

81272

81273

-syslist.go: s-syslist; @true

81274

-s-syslist: Makefile

81275

- echo '// Generated automatically by make.' >syslist.go.tmp

81276

- echo 'package build' >>syslist.go.tmp

81277

- echo 'const goosList = "$(GOOS)"' >>syslist.go.tmp

81278

- echo 'const goarchList = "$(GOARCH)"' >>syslist.go.tmp

81279

- $(SHELL) $(srcdir)/../move-if-change syslist.go.tmp syslist.go

81280

- $(STAMP) $@

81281

-

81282

@go_include@ go/doc.lo.dep

81283

go/doc.lo.dep: $(go_go_doc_files)

81284

$(BUILDDEPS)

81285

Index: config.sub

81286

===================================================================

81287

--- a/src/config.sub (.../tags/gcc_4_8_2_release)

81288

+++ b/src/config.sub (.../branches/gcc-4_8-branch)

81289

@@ -1,10 +1,8 @@

81290

#! /bin/sh

81291

# Configuration validation subroutine script.

81292

81293

-# 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,

81294

-# 2011, 2012, 2013 Free Software Foundation, Inc.

81295

81296

81297

-timestamp='2013-01-11'

81298

+timestamp='2013-10-01'

81299

81300

# This file is free software; you can redistribute it and/or modify it

81301

# under the terms of the GNU General Public License as published by

81302

@@ -70,9 +68,7 @@

81303

version="\

81304

GNU config.sub ($timestamp)

81305

81306

81307

-2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011,

81308

-2012, 2013 Free Software Foundation, Inc.

81309

81310

81311

This is free software; see the source for copying conditions. There is NO

81312

warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE."

81313

@@ -256,12 +252,12 @@

81314

81315

81316

| am33_2.0 \

81317

- | arc \

81318

+ | arc | arceb \

81319

81320

| avr | avr32 \

81321

| be32 | be64 \

81322

| bfin \

81323

- | c4x | clipper \

81324

+ | c4x | c8051 | clipper \

81325

| d10v | d30v | dlx | dsp16xx \

81326

| epiphany \

81327

| fido | fr30 | frv \

81328

@@ -269,6 +265,7 @@

81329

| hexagon \

81330

| i370 | i860 | i960 | ia64 \

81331

| ip2k | iq2000 \

81332

+ | k1om \

81333

| le32 | le64 \

81334

| lm32 \

81335

| m32c | m32r | m32rle | m68000 | m68k | m88k \

81336

@@ -297,10 +294,10 @@

81337

| mt \

81338

| msp430 \

81339

| nds32 | nds32le | nds32be \

81340

- | nios | nios2 \

81341

+ | nios | nios2 | nios2eb | nios2el \

81342

| ns16k | ns32k \

81343

| open8 \

81344

- | or32 \

81345

+ | or1k | or32 \

81346

| pdp10 | pdp11 | pj | pjl \

81347

| powerpc | powerpc64 | powerpc64le | powerpcle \

81348

| pyramid \

81349

@@ -328,7 +325,7 @@

81350

c6x)

81351

basic_machine=tic6x-unknown

81352

;;

81353

- m6811 | m68hc11 | m6812 | m68hc12 | m68hcs12x | picochip)

81354

+ m6811 | m68hc11 | m6812 | m68hc12 | m68hcs12x | nvptx | picochip)

81355

basic_machine=$basic_machine-unknown

81356

os=-none

81357

;;

81358

@@ -370,13 +367,13 @@

81359

| aarch64-* | aarch64_be-* \

81360

| alpha-* | alphaev[4-8]-* | alphaev56-* | alphaev6[78]-* \

81361

| alpha64-* | alpha64ev[4-8]-* | alpha64ev56-* | alpha64ev6[78]-* \

81362

- | alphapca5[67]-* | alpha64pca5[67]-* | arc-* \

81363

+ | alphapca5[67]-* | alpha64pca5[67]-* | arc-* | arceb-* \

81364

81365

| avr-* | avr32-* \

81366

| be32-* | be64-* \

81367

| bfin-* | bs2000-* \

81368

| c[123]* | c30-* | [cjt]90-* | c4x-* \

81369

- | clipper-* | craynv-* | cydra-* \

81370

+ | c8051-* | clipper-* | craynv-* | cydra-* \

81371

| d10v-* | d30v-* | dlx-* \

81372

| elxsi-* \

81373

| f30[01]-* | f700-* | fido-* | fr30-* | frv-* | fx80-* \

81374

@@ -385,6 +382,7 @@

81375

| hexagon-* \

81376

| i*86-* | i860-* | i960-* | ia64-* \

81377

| ip2k-* | iq2000-* \

81378

+ | k1om-* \

81379

| le32-* | le64-* \

81380

| lm32-* \

81381

| m32c-* | m32r-* | m32rle-* \

81382

@@ -414,7 +412,7 @@

81383

| mt-* \

81384

| msp430-* \

81385

| nds32-* | nds32le-* | nds32be-* \

81386

- | nios-* | nios2-* \

81387

+ | nios-* | nios2-* | nios2eb-* | nios2el-* \

81388

| none-* | np1-* | ns16k-* | ns32k-* \

81389

| open8-* \

81390

| orion-* \

81391

@@ -798,7 +796,7 @@

81392

os=-mingw64

81393

;;

81394

mingw32)

81395

- basic_machine=i386-pc

81396

+ basic_machine=i686-pc

81397

os=-mingw32

81398

;;

81399

mingw32ce)

81400

@@ -834,7 +832,7 @@

81401

basic_machine=`echo $basic_machine | sed -e 's/ms1-/mt-/'`

81402

;;

81403

msys)

81404

- basic_machine=i386-pc

81405

+ basic_machine=i686-pc

81406

os=-msys

81407

;;

81408

mvs)

81409

@@ -1550,6 +1548,9 @@

81410

c4x-* | tic4x-*)

81411

os=-coff

81412

;;

81413

+ c8051-*)

81414

+ os=-elf

81415

+ ;;

81416

hexagon-*)

81417

os=-elf

81418

;;

81419

@@ -1593,6 +1594,9 @@

81420

mips*-*)

81421

os=-elf

81422

;;

81423

+ or1k-*)

81424

+ os=-elf

81425

+ ;;

81426

or32-*)

81427

os=-coff

81428

;;

81429

Index: libobjc/configure

81430

===================================================================

81431

--- a/src/libobjc/configure (.../tags/gcc_4_8_2_release)

81432

+++ b/src/libobjc/configure (.../branches/gcc-4_8-branch)

81433

@@ -6056,7 +6056,7 @@

81434

rm -rf conftest*

81435

;;

81436

81437

-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \

81438

+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \

81439

s390*-*linux*|s390*-*tpf*|sparc*-*linux*)

81440

# Find out which ABI we are using.

81441

echo 'int i;' > conftest.$ac_ext

81442

@@ -6081,7 +6081,10 @@

81443

;;

81444

esac

81445

;;

81446

- ppc64-*linux*|powerpc64-*linux*)

81447

+ powerpc64le-*linux*)

81448

+ LD="${LD-ld} -m elf32lppclinux"

81449

+ ;;

81450

+ powerpc64-*linux*)

81451

LD="${LD-ld} -m elf32ppclinux"

81452

;;

81453

s390x-*linux*)

81454

@@ -6100,7 +6103,10 @@

81455

x86_64-*linux*)

81456

LD="${LD-ld} -m elf_x86_64"

81457

;;

81458

- ppc*-*linux*|powerpc*-*linux*)

81459

+ powerpcle-*linux*)

81460

+ LD="${LD-ld} -m elf64lppc"

81461

+ ;;

81462

+ powerpc-*linux*)

81463

LD="${LD-ld} -m elf64ppc"

81464

;;

81465

s390*-*linux*|s390*-*tpf*)

81466

@@ -10595,7 +10601,7 @@

81467

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

81468

lt_status=$lt_dlunknown

81469

cat > conftest.$ac_ext <<_LT_EOF

81470

-#line 10598 "configure"

81471

+#line 10604 "configure"

81472

#include "confdefs.h"

81473

81474

#if HAVE_DLFCN_H

81475

@@ -10701,7 +10707,7 @@

81476

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

81477

lt_status=$lt_dlunknown

81478

cat > conftest.$ac_ext <<_LT_EOF

81479

-#line 10704 "configure"

81480

+#line 10710 "configure"

81481

#include "confdefs.h"

81482

81483

#if HAVE_DLFCN_H

81484

@@ -11472,7 +11478,7 @@

81485

enableval=$enable_sjlj_exceptions; :

81486

else

81487

cat > conftest.$ac_ext << EOF

81488

-#line 11475 "configure"

81489

+#line 11481 "configure"

81490

@interface Frob

81491

@end

81492

@implementation Frob

81493

Index: libobjc/ChangeLog

81494

===================================================================

81495

--- a/src/libobjc/ChangeLog (.../tags/gcc_4_8_2_release)

81496

+++ b/src/libobjc/ChangeLog (.../branches/gcc-4_8-branch)

81497

@@ -1,3 +1,10 @@

81498

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

81499

+

81500

+ Backport from mainline

81501

+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

81502

+

81503

+ * configure: Regenerate.

81504

+

81505

2013-10-16 Release Manager

81506

81507

* GCC 4.8.2 released.

81508

Index: libgfortran/configure

81509

===================================================================

81510

--- a/src/libgfortran/configure (.../tags/gcc_4_8_2_release)

81511

+++ b/src/libgfortran/configure (.../branches/gcc-4_8-branch)

81512

@@ -8062,7 +8062,7 @@

81513

rm -rf conftest*

81514

;;

81515

81516

-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \

81517

+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \

81518

s390*-*linux*|s390*-*tpf*|sparc*-*linux*)

81519

# Find out which ABI we are using.

81520

echo 'int i;' > conftest.$ac_ext

81521

@@ -8087,7 +8087,10 @@

81522

;;

81523

esac

81524

;;

81525

- ppc64-*linux*|powerpc64-*linux*)

81526

+ powerpc64le-*linux*)

81527

+ LD="${LD-ld} -m elf32lppclinux"

81528

+ ;;

81529

+ powerpc64-*linux*)

81530

LD="${LD-ld} -m elf32ppclinux"

81531

;;

81532

s390x-*linux*)

81533

@@ -8106,7 +8109,10 @@

81534

x86_64-*linux*)

81535

LD="${LD-ld} -m elf_x86_64"

81536

;;

81537

- ppc*-*linux*|powerpc*-*linux*)

81538

+ powerpcle-*linux*)

81539

+ LD="${LD-ld} -m elf64lppc"

81540

+ ;;

81541

+ powerpc-*linux*)

81542

LD="${LD-ld} -m elf64ppc"

81543

;;

81544

s390*-*linux*|s390*-*tpf*)

81545

@@ -12333,7 +12339,7 @@

81546

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

81547

lt_status=$lt_dlunknown

81548

cat > conftest.$ac_ext <<_LT_EOF

81549

-#line 12336 "configure"

81550

+#line 12342 "configure"

81551

#include "confdefs.h"

81552

81553

#if HAVE_DLFCN_H

81554

@@ -12439,7 +12445,7 @@

81555

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

81556

lt_status=$lt_dlunknown

81557

cat > conftest.$ac_ext <<_LT_EOF

81558

-#line 12442 "configure"

81559

+#line 12448 "configure"

81560

#include "confdefs.h"

81561

81562

#if HAVE_DLFCN_H

81563

Index: libgfortran/intrinsics/system_clock.c

81564

===================================================================

81565

--- a/src/libgfortran/intrinsics/system_clock.c (.../tags/gcc_4_8_2_release)

81566

+++ b/src/libgfortran/intrinsics/system_clock.c (.../branches/gcc-4_8-branch)

81567

@@ -32,7 +32,8 @@

81568

/* POSIX states that CLOCK_REALTIME must be present if clock_gettime

81569

is available, others are optional. */

81570

#if defined(HAVE_CLOCK_GETTIME) || defined(HAVE_CLOCK_GETTIME_LIBRT)

81571

-#ifdef CLOCK_MONOTONIC

81572

+#if defined(CLOCK_MONOTONIC) && defined(_POSIX_MONOTONIC_CLOCK) \

81573

+ && _POSIX_MONOTONIC_CLOCK >= 0

81574

#define GF_CLOCK_MONOTONIC CLOCK_MONOTONIC

81575

#else

81576

#define GF_CLOCK_MONOTONIC CLOCK_REALTIME

81577

Index: libgfortran/ChangeLog

81578

===================================================================

81579

--- a/src/libgfortran/ChangeLog (.../tags/gcc_4_8_2_release)

81580

+++ b/src/libgfortran/ChangeLog (.../branches/gcc-4_8-branch)

81581

@@ -1,3 +1,75 @@

81582

+2014-05-03 Janne Blomqvist <jb@gcc.gnu.org>

81583

+

81584

+ Backport from 4.9

81585

+ PR libfortran/56919

81586

+ * intrinsics/system_clock.c (GF_CLOCK_MONOTONIC): Check

81587

+ _POSIX_MONOTONIC_CLOCK as well.

81588

+

81589

+2014-04-12 Jerry DeLisle <jvdelisle@gcc.gnu>

81590

+

81591

+ Backport from mainline

81592

+ PR libfortran/60810

81593

+ * io/unit.c (is_trim_ok): If internal unit is array, do not trim.

81594

+

81595

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

81596

+

81597

+ Backport from mainline

81598

+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

81599

+ * configure: Regenerate.

81600

+

81601

+2014-03-15 Dominique d'Humieres <dominiq@lps.ens.fr>

81602

+

81603

+ Backport from mainline

81604

+ PR libgfortran/60128

81605

+ * io/write_float.def (output_float): Remove unused variable

81606

+ nzero_real. Replace a double space with a single one.

81607

+ (determine_en_precision): Fix wrong handling of the EN format.

81608

+

81609

+2014-03-15 Jerry DeLisle <jvdelisle@gcc.gnu>

81610

+

81611

+ Backport from mainline

81612

+ PR libfortran/58324

81613

+ PR libfortran/38199

81614

+ * io/list_read.c (finish_list_read): Read one character to check

81615

+ for the end of the file. If it is the end, then issue the file

81616

+ end error message. If not, use eat_line to reach the end

81617

+ without giving error. The next attempt to read will then

81618

+ issue the error as described above.

81619

+ * io/read.c (read_decimal): Quickly skip spaces to avoid calls

81620

+ to next_char.

81621

+ * io/unit.c (is_trim_ok): New helper function to check various

81622

+ conditions to see if its OK to trim the internal unit string.

81623

+ (get_internal_unit): Use LEN_TRIM to shorten selected internal

81624

+ unit strings for optimizing READ. Enable this optimization for

81625

+ formatted READ.

81626

+

81627

+2014-02-21 Jerry DeLisle <jvdelisle@gcc.gnu>

81628

+ Dominique d'Humieres <dominiq@lps.ens.fr>

81629

+ Steven G. Kargl <kargl@gcc.gnu.org>

81630

+

81631

+ Backport from mainline

81632

+ PR libfortran/59700

81633

+ PR libfortran/59764

81634

+ * io/io.h (struct st_parameter_dt): Assign expanded_read flag to

81635

+ unused bit. Define new variable line_buffer_pos.

81636

+ * io/list_read.c (free_saved, next_char, l_push_char,

81637

+ read_logical, read_real): Replace use of item_count with

81638

+ line_buffer_pos for line_buffer look ahead.

81639

+ (read_logical, read_integer, parse_real, read_real, check_type):

81640

+ Adjust location of free_line to after generating error messages

81641

+ to retain the correct item count for the message.

81642

+

81643

+2014-02-15 Jerry DeLisle <jvdelisle@gcc.gnu>

81644

+ Dominique d'Humieres <dominiq@lps.ens.fr>

81645

+

81646

+ Backport from mainline

81647

+ PR libfortran/59771

81648

+ PR libfortran/59774

81649

+ PR libfortran/59836

81650

+ * io/write_float.def (output_float): Fix wrong handling of the

81651

+ Fw.0 format.

81652

+ (output_float_FMT_G_): Fixes rounding issues with -m32.

81653

+

81654

2013-10-16 Release Manager

81655

81656

* GCC 4.8.2 released.

81657

Index: libgfortran/io/list_read.c

81658

===================================================================

81659

--- a/src/libgfortran/io/list_read.c (.../tags/gcc_4_8_2_release)

81660

+++ b/src/libgfortran/io/list_read.c (.../branches/gcc-4_8-branch)

81661

@@ -118,7 +118,7 @@

81662

static void

81663

free_line (st_parameter_dt *dtp)

81664

{

81665

- dtp->u.p.item_count = 0;

81666

+ dtp->u.p.line_buffer_pos = 0;

81667

dtp->u.p.line_buffer_enabled = 0;

81668

81669

if (dtp->u.p.line_buffer == NULL)

81670

@@ -150,15 +150,15 @@

81671

{

81672

dtp->u.p.at_eol = 0;

81673

81674

- c = dtp->u.p.line_buffer[dtp->u.p.item_count];

81675

- if (c != '\0' && dtp->u.p.item_count < 64)

81676

+ c = dtp->u.p.line_buffer[dtp->u.p.line_buffer_pos];

81677

+ if (c != '\0' && dtp->u.p.line_buffer_pos < 64)

81678

{

81679

- dtp->u.p.line_buffer[dtp->u.p.item_count] = '\0';

81680

- dtp->u.p.item_count++;

81681

+ dtp->u.p.line_buffer[dtp->u.p.line_buffer_pos] = '\0';

81682

+ dtp->u.p.line_buffer_pos++;

81683

goto done;

81684

}

81685

81686

- dtp->u.p.item_count = 0;

81687

+ dtp->u.p.line_buffer_pos = 0;

81688

dtp->u.p.line_buffer_enabled = 0;

81689

}

81690

81691

@@ -640,7 +640,7 @@

81692

if (dtp->u.p.line_buffer == NULL)

81693

dtp->u.p.line_buffer = xcalloc (SCRATCH_SIZE, 1);

81694

81695

- dtp->u.p.line_buffer[dtp->u.p.item_count++] = c;

81696

+ dtp->u.p.line_buffer[dtp->u.p.line_buffer_pos++] = c;

81697

}

81698

81699

81700

@@ -750,7 +750,7 @@

81701

{

81702

dtp->u.p.nml_read_error = 1;

81703

dtp->u.p.line_buffer_enabled = 1;

81704

- dtp->u.p.item_count = 0;

81705

+ dtp->u.p.line_buffer_pos = 0;

81706

return;

81707

}

81708

81709

@@ -758,14 +758,17 @@

81710

81711

bad_logical:

81712

81713

- free_line (dtp);

81714

-

81715

if (nml_bad_return (dtp, c))

81716

- return;

81717

+ {

81718

+ free_line (dtp);

81719

+ return;

81720

+ }

81721

81722

+

81723

free_saved (dtp);

81724

if (c == EOF)

81725

{

81726

+ free_line (dtp);

81727

hit_eof (dtp);

81728

return;

81729

}

81730

@@ -773,6 +776,7 @@

81731

eat_line (dtp);

81732

snprintf (message, MSGLEN, "Bad logical value while reading item %d",

81733

dtp->u.p.item_count);

81734

+ free_line (dtp);

81735

generate_error (&dtp->common, LIBERROR_READ_VALUE, message);

81736

return;

81737

81738

@@ -913,9 +917,9 @@

81739

else if (c != '\n')

81740

eat_line (dtp);

81741

81742

- free_line (dtp);

81743

snprintf (message, MSGLEN, "Bad integer for item %d in list input",

81744

dtp->u.p.item_count);

81745

+ free_line (dtp);

81746

generate_error (&dtp->common, LIBERROR_READ_VALUE, message);

81747

81748

return;

81749

@@ -1298,9 +1302,9 @@

81750

else if (c != '\n')

81751

eat_line (dtp);

81752

81753

- free_line (dtp);

81754

snprintf (message, MSGLEN, "Bad floating point number for item %d",

81755

dtp->u.p.item_count);

81756

+ free_line (dtp);

81757

generate_error (&dtp->common, LIBERROR_READ_VALUE, message);

81758

81759

return 1;

81760

@@ -1406,9 +1410,9 @@

81761

else if (c != '\n')

81762

eat_line (dtp);

81763

81764

- free_line (dtp);

81765

snprintf (message, MSGLEN, "Bad complex value in item %d of list input",

81766

dtp->u.p.item_count);

81767

+ free_line (dtp);

81768

generate_error (&dtp->common, LIBERROR_READ_VALUE, message);

81769

}

81770

81771

@@ -1770,7 +1774,7 @@

81772

{

81773

dtp->u.p.nml_read_error = 1;

81774

dtp->u.p.line_buffer_enabled = 1;

81775

- dtp->u.p.item_count = 0;

81776

+ dtp->u.p.line_buffer_pos = 0;

81777

return;

81778

}

81779

81780

@@ -1789,9 +1793,9 @@

81781

else if (c != '\n')

81782

eat_line (dtp);

81783

81784

- free_line (dtp);

81785

snprintf (message, MSGLEN, "Bad real number in item %d of list input",

81786

dtp->u.p.item_count);

81787

+ free_line (dtp);

81788

generate_error (&dtp->common, LIBERROR_READ_VALUE, message);

81789

}

81790

81791

@@ -1806,11 +1810,10 @@

81792

81793

if (dtp->u.p.saved_type != BT_UNKNOWN && dtp->u.p.saved_type != type)

81794

{

81795

- free_line (dtp);

81796

snprintf (message, MSGLEN, "Read type %s where %s was expected for item %d",

81797

type_name (dtp->u.p.saved_type), type_name (type),

81798

dtp->u.p.item_count);

81799

-

81800

+ free_line (dtp);

81801

generate_error (&dtp->common, LIBERROR_READ_VALUE, message);

81802

return 1;

81803

}

81804

@@ -1820,12 +1823,12 @@

81805

81806

if (dtp->u.p.saved_length != len)

81807

{

81808

- free_line (dtp);

81809

snprintf (message, MSGLEN,

81810

"Read kind %d %s where kind %d is required for item %d",

81811

dtp->u.p.saved_length, type_name (dtp->u.p.saved_type), len,

81812

dtp->u.p.item_count);

81813

generate_error (&dtp->common, LIBERROR_READ_VALUE, message);

81814

+ free_line (dtp);

81815

return 1;

81816

}

81817

81818

@@ -2031,8 +2034,6 @@

81819

void

81820

finish_list_read (st_parameter_dt *dtp)

81821

{

81822

- int err;

81823

-

81824

free_saved (dtp);

81825

81826

fbuf_flush (dtp->u.p.current_unit, dtp->u.p.mode);

81827

@@ -2043,12 +2044,22 @@

81828

return;

81829

}

81830

81831

- err = eat_line (dtp);

81832

- if (err == LIBERROR_END)

81833

+ if (!is_internal_unit (dtp))

81834

{

81835

- free_line (dtp);

81836

- hit_eof (dtp);

81837

+ int c;

81838

+ c = next_char (dtp);

81839

+ if (c == EOF)

81840

+ {

81841

+ free_line (dtp);

81842

+ hit_eof (dtp);

81843

+ return;

81844

+ }

81845

+ if (c != '\n')

81846

+ eat_line (dtp);

81847

}

81848

+

81849

+ free_line (dtp);

81850

+

81851

}

81852

81853

/* NAMELIST INPUT

81854

Index: libgfortran/io/read.c

81855

===================================================================

81856

--- a/src/libgfortran/io/read.c (.../tags/gcc_4_8_2_release)

81857

+++ b/src/libgfortran/io/read.c (.../branches/gcc-4_8-branch)

81858

@@ -655,7 +655,13 @@

81859

81860

if (c == ' ')

81861

{

81862

- if (dtp->u.p.blank_status == BLANK_NULL) continue;

81863

+ if (dtp->u.p.blank_status == BLANK_NULL)

81864

+ {

81865

+ /* Skip spaces. */

81866

+ for ( ; w > 0; p++, w--)

81867

+ if (*p != ' ') break;

81868

+ continue;

81869

+ }

81870

if (dtp->u.p.blank_status == BLANK_ZERO) c = '0';

81871

}

81872

81873

Index: libgfortran/io/io.h

81874

===================================================================

81875

--- a/src/libgfortran/io/io.h (.../tags/gcc_4_8_2_release)

81876

+++ b/src/libgfortran/io/io.h (.../branches/gcc-4_8-branch)

81877

@@ -424,7 +424,10 @@

81878

unsigned g0_no_blanks : 1;

81879

/* Used to signal use of free_format_data. */

81880

unsigned format_not_saved : 1;

81881

- /* 14 unused bits. */

81882

+ /* A flag used to identify when a non-standard expanded namelist read

81883

+ has occurred. */

81884

+ unsigned expanded_read : 1;

81885

+ /* 13 unused bits. */

81886

81887

/* Used for ungetc() style functionality. Possible values

81888

are an unsigned char, EOF, or EOF - 1 used to mark the

81889

@@ -441,9 +444,8 @@

81890

char *line_buffer;

81891

struct format_data *fmt;

81892

namelist_info *ionml;

81893

- /* A flag used to identify when a non-standard expanded namelist read

81894

- has occurred. */

81895

- int expanded_read;

81896

+ /* Current position within the look-ahead line buffer. */

81897

+ int line_buffer_pos;

81898

/* Storage area for values except for strings. Must be

81899

large enough to hold a complex value (two reals) of the

81900

largest kind. */

81901

Index: libgfortran/io/unit.c

81902

===================================================================

81903

--- a/src/libgfortran/io/unit.c (.../tags/gcc_4_8_2_release)

81904

+++ b/src/libgfortran/io/unit.c (.../branches/gcc-4_8-branch)

81905

@@ -29,6 +29,7 @@

81906

#include "unix.h"

81907

#include <stdlib.h>

81908

#include <string.h>

81909

+#include <stdbool.h>

81910

81911

81912

/* IO locking rules:

81913

@@ -375,6 +376,36 @@

81914

}

81915

81916

81917

+/* Helper function to check rank, stride, format string, and namelist.

81918

+ This is used for optimization. You can't trim out blanks or shorten

81919

+ the string if trailing spaces are significant. */

81920

+static bool

81921

+is_trim_ok (st_parameter_dt *dtp)

81922

+{

81923

+ /* Check rank and stride. */

81924

+ if (dtp->internal_unit_desc)

81925

+ return false;

81926

+ /* Format strings can not have 'BZ' or '/'. */

81927

+ if (dtp->common.flags & IOPARM_DT_HAS_FORMAT)

81928

+ {

81929

+ char *p = dtp->format;

81930

+ off_t i;

81931

+ if (dtp->common.flags & IOPARM_DT_HAS_BLANK)

81932

+ return false;

81933

+ for (i = 0; i < dtp->format_len; i++)

81934

+ {

81935

+ if (p[i] == '/') return false;

81936

+ if (p[i] == 'b' || p[i] == 'B')

81937

+ if (p[i+1] == 'z' || p[i+1] == 'Z')

81938

+ return false;

81939

+ }

81940

+ }

81941

+ if (dtp->u.p.ionml) /* A namelist. */

81942

+ return false;

81943

+ return true;

81944

+}

81945

+

81946

+

81947

gfc_unit *

81948

get_internal_unit (st_parameter_dt *dtp)

81949

{

81950

@@ -402,6 +433,22 @@

81951

some other file I/O unit. */

81952

iunit->unit_number = -1;

81953

81954

+ /* As an optimization, adjust the unit record length to not

81955

+ include trailing blanks. This will not work under certain conditions

81956

+ where trailing blanks have significance. */

81957

+ if (dtp->u.p.mode == READING && is_trim_ok (dtp))

81958

+ {

81959

+ int len;

81960

+ if (dtp->common.unit == 0)

81961

+ len = string_len_trim (dtp->internal_unit_len,

81962

+ dtp->internal_unit);

81963

+ else

81964

+ len = string_len_trim_char4 (dtp->internal_unit_len,

81965

+ (const gfc_char4_t*) dtp->internal_unit);

81966

+ dtp->internal_unit_len = len;

81967

+ iunit->recl = dtp->internal_unit_len;

81968

+ }

81969

+

81970

/* Set up the looping specification from the array descriptor, if any. */

81971

81972

if (is_array_io (dtp))

81973

@@ -414,27 +461,6 @@

81974

81975

start_record *= iunit->recl;

81976

}

81977

- else

81978

- {

81979

- /* If we are not processing an array, adjust the unit record length not

81980

- to include trailing blanks for list-formatted reads. */

81981

- if (dtp->u.p.mode == READING && !(dtp->common.flags & IOPARM_DT_HAS_FORMAT))

81982

- {

81983

- if (dtp->common.unit == 0)

81984

- {

81985

- dtp->internal_unit_len =

81986

- string_len_trim (dtp->internal_unit_len, dtp->internal_unit);

81987

- iunit->recl = dtp->internal_unit_len;

81988

- }

81989

- else

81990

- {

81991

- dtp->internal_unit_len =

81992

- string_len_trim_char4 (dtp->internal_unit_len,

81993

- (const gfc_char4_t*) dtp->internal_unit);

81994

- iunit->recl = dtp->internal_unit_len;

81995

- }

81996

- }

81997

- }

81998

81999

/* Set initial values for unit parameters. */

82000

if (dtp->common.unit)

82001

Index: libgfortran/io/write_float.def

82002

===================================================================

82003

--- a/src/libgfortran/io/write_float.def (.../tags/gcc_4_8_2_release)

82004

+++ b/src/libgfortran/io/write_float.def (.../branches/gcc-4_8-branch)

82005

@@ -125,8 +125,6 @@

82006

int nzero;

82007

/* Number of digits after the decimal point. */

82008

int nafter;

82009

- /* Number of zeros after the decimal point, whatever the precision. */

82010

- int nzero_real;

82011

int leadzero;

82012

int nblanks;

82013

int ndigits, edigits;

82014

@@ -138,7 +136,6 @@

82015

p = dtp->u.p.scale_factor;

82016

82017

rchar = '5';

82018

- nzero_real = -1;

82019

82020

/* We should always know the field width and precision. */

82021

if (d < 0)

82022

@@ -191,7 +188,7 @@

82023

if (nafter < 0)

82024

nafter = 0;

82025

nafter = d;

82026

- nzero = nzero_real = 0;

82027

+ nzero = 0;

82028

}

82029

else /* p < 0 */

82030

{

82031

@@ -211,7 +208,6 @@

82032

nafter = d + nbefore;

82033

nbefore = 0;

82034

}

82035

- nzero_real = nzero;

82036

if (nzero > d)

82037

nzero = d;

82038

}

82039

@@ -218,7 +214,7 @@

82040

}

82041

else

82042

{

82043

- nzero = nzero_real = 0;

82044

+ nzero = 0;

82045

nafter = d;

82046

}

82047

82048

@@ -373,7 +369,7 @@

82049

updown:

82050

82051

rchar = '0';

82052

- if (w > 0 && d == 0 && p == 0)

82053

+ if (ft != FMT_F && w > 0 && d == 0 && p == 0)

82054

nbefore = 1;

82055

/* Scan for trailing zeros to see if we really need to round it. */

82056

for(i = nbefore + nafter; i < ndigits; i++)

82057

@@ -386,13 +382,14 @@

82058

do_rnd:

82059

82060

if (nbefore + nafter == 0)

82061

+ /* Handle the case Fw.0 and value < 1.0 */

82062

{

82063

ndigits = 0;

82064

- if (nzero_real == d && digits[0] >= rchar)

82065

+ if (digits[0] >= rchar)

82066

{

82067

/* We rounded to zero but shouldn't have */

82068

- nzero--;

82069

- nafter = 1;

82070

+ nbefore = 1;

82071

+ digits--;

82072

digits[0] = '1';

82073

ndigits = 1;

82074

}

82075

@@ -990,7 +987,7 @@

82076

int d = f->u.real.d;\

82077

int w = f->u.real.w;\

82078

fnode newf;\

82079

- GFC_REAL_ ## x rexp_d, r = 0.5;\

82080

+ GFC_REAL_ ## x exp_d, r = 0.5, r_sc;\

82081

int low, high, mid;\

82082

int ubound, lbound;\

82083

char *p, pad = ' ';\

82084

@@ -997,6 +994,7 @@

82085

int save_scale_factor, nb = 0;\

82086

try result;\

82087

int nprinted, precision;\

82088

+ volatile GFC_REAL_ ## x temp;\

82089

\

82090

save_scale_factor = dtp->u.p.scale_factor;\

82091

\

82092

@@ -1015,10 +1013,13 @@

82093

break;\

82094

}\

82095

\

82096

- rexp_d = calculate_exp_ ## x (-d);\

82097

- if ((m > 0.0 && ((m < 0.1 - 0.1 * r * rexp_d) || (rexp_d * (m + r) >= 1.0)))\

82098

+ exp_d = calculate_exp_ ## x (d);\

82099

+ r_sc = (1 - r / exp_d);\

82100

+ temp = 0.1 * r_sc;\

82101

+ if ((m > 0.0 && ((m < temp) || (r >= (exp_d - m))))\

82102

|| ((m == 0.0) && !(compile_options.allow_std\

82103

- & (GFC_STD_F2003 | GFC_STD_F2008))))\

82104

+ & (GFC_STD_F2003 | GFC_STD_F2008)))\

82105

+ || d == 0)\

82106

{ \

82107

newf.format = FMT_E;\

82108

newf.u.real.w = w;\

82109

@@ -1038,10 +1039,9 @@

82110

\

82111

while (low <= high)\

82112

{ \

82113

- volatile GFC_REAL_ ## x temp;\

82114

mid = (low + high) / 2;\

82115

\

82116

- temp = (calculate_exp_ ## x (mid - 1) * (1 - r * rexp_d));\

82117

+ temp = (calculate_exp_ ## x (mid - 1) * r_sc);\

82118

\

82119

if (m < temp)\

82120

{ \

82121

@@ -1121,14 +1121,36 @@

82122

/* EN format is tricky since the number of significant digits depends

82123

on the magnitude. Solve it by first printing a temporary value and

82124

figure out the number of significant digits from the printed

82125

- exponent. */

82126

+ exponent. Values y, 0.95*10.0**e <= y <10.0**e, are rounded to

82127

+ 10.0**e even when the final result will not be rounded to 10.0**e.

82128

+ For these values the exponent returned by atoi has to be decremented

82129

+ by one. The values y in the ranges

82130

+ (1000.0-0.5*10.0**(-d))*10.0**(3*n) <= y < 10.0*(3*(n+1))

82131

+ (100.0-0.5*10.0**(-d))*10.0**(3*n) <= y < 10.0*(3*n+2)

82132

+ (10.0-0.5*10.0**(-d))*10.0**(3*n) <= y < 10.0*(3*n+1)

82133

+ are correctly rounded respectively to 1.0...0*10.0*(3*(n+1)),

82134

+ 100.0...0*10.0*(3*n), and 10.0...0*10.0*(3*n), where 0...0

82135

+ represents d zeroes, by the lines 279 to 297. */

82136

82137

#define EN_PREC(x,y)\

82138

{\

82139

- GFC_REAL_ ## x tmp; \

82140

- tmp = * (GFC_REAL_ ## x *)source; \

82141

+ volatile GFC_REAL_ ## x tmp, one = 1.0;\

82142

+ tmp = * (GFC_REAL_ ## x *)source;\

82143

if (isfinite (tmp)) \

82144

- nprinted = DTOA(y,0,tmp); \

82145

+ {\

82146

+ nprinted = DTOA(y,0,tmp);\

82147

+ int e = atoi (&buffer[4]);\

82148

+ if (buffer[1] == '1')\

82149

+ {\

82150

+ tmp = (calculate_exp_ ## x (-e)) * tmp;\

82151

+ tmp = one - (tmp < 0 ? -tmp : tmp); \

82152

+ if (tmp > 0)\

82153

+ e = e - 1;\

82154

+ }\

82155

+ nbefore = e%3;\

82156

+ if (nbefore < 0)\

82157

+ nbefore = 3 + nbefore;\

82158

+ }\

82159

else\

82160

nprinted = -1;\

82161

}\

82162

@@ -1140,6 +1162,7 @@

82163

int nprinted;

82164

char buffer[10];

82165

const size_t size = 10;

82166

+ int nbefore; /* digits before decimal point - 1. */

82167

82168

switch (len)

82169

{

82170

@@ -1172,16 +1195,6 @@

82171

if (nprinted == -1)

82172

return -1;

82173

82174

- int e = atoi (&buffer[5]);

82175

- int nbefore; /* digits before decimal point - 1. */

82176

- if (e >= 0)

82177

- nbefore = e % 3;

82178

- else

82179

- {

82180

- nbefore = (-e) % 3;

82181

- if (nbefore != 0)

82182

- nbefore = 3 - nbefore;

82183

- }

82184

int prec = f->u.real.d + nbefore;

82185

if (dtp->u.p.current_unit->round_status != ROUND_UNSPECIFIED

82186

&& dtp->u.p.current_unit->round_status != ROUND_PROCDEFINED)

82187

Index: libffi/configure

82188

===================================================================

82189

--- a/src/libffi/configure (.../tags/gcc_4_8_2_release)

82190

+++ b/src/libffi/configure (.../branches/gcc-4_8-branch)

82191

@@ -613,6 +613,7 @@

82192

FFI_EXEC_TRAMPOLINE_TABLE

82193

FFI_EXEC_TRAMPOLINE_TABLE_FALSE

82194

FFI_EXEC_TRAMPOLINE_TABLE_TRUE

82195

+HAVE_LONG_DOUBLE_VARIANT

82196

HAVE_LONG_DOUBLE

82197

ALLOCA

82198

TILE_FALSE

82199

@@ -6392,7 +6393,7 @@

82200

rm -rf conftest*

82201

;;

82202

82203

-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \

82204

+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \

82205

s390*-*linux*|s390*-*tpf*|sparc*-*linux*)

82206

# Find out which ABI we are using.

82207

echo 'int i;' > conftest.$ac_ext

82208

@@ -6417,7 +6418,10 @@

82209

;;

82210

esac

82211

;;

82212

- ppc64-*linux*|powerpc64-*linux*)

82213

+ powerpc64le-*linux*)

82214

+ LD="${LD-ld} -m elf32lppclinux"

82215

+ ;;

82216

+ powerpc64-*linux*)

82217

LD="${LD-ld} -m elf32ppclinux"

82218

;;

82219

s390x-*linux*)

82220

@@ -6436,7 +6440,10 @@

82221

x86_64-*linux*)

82222

LD="${LD-ld} -m elf_x86_64"

82223

;;

82224

- ppc*-*linux*|powerpc*-*linux*)

82225

+ powerpcle-*linux*)

82226

+ LD="${LD-ld} -m elf64lppc"

82227

+ ;;

82228

+ powerpc-*linux*)

82229

LD="${LD-ld} -m elf64ppc"

82230

;;

82231

s390*-*linux*|s390*-*tpf*)

82232

@@ -10900,7 +10907,7 @@

82233

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

82234

lt_status=$lt_dlunknown

82235

cat > conftest.$ac_ext <<_LT_EOF

82236

-#line 10903 "configure"

82237

+#line 10910 "configure"

82238

#include "confdefs.h"

82239

82240

#if HAVE_DLFCN_H

82241

@@ -11006,7 +11013,7 @@

82242

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

82243

lt_status=$lt_dlunknown

82244

cat > conftest.$ac_ext <<_LT_EOF

82245

-#line 11009 "configure"

82246

+#line 11016 "configure"

82247

#include "confdefs.h"

82248

82249

#if HAVE_DLFCN_H

82250

@@ -11443,6 +11450,7 @@

82251

82252

82253

TARGETDIR="unknown"

82254

+HAVE_LONG_DOUBLE_VARIANT=0

82255

case "$host" in

82256

aarch64*-*-*)

82257

TARGET=AARCH64; TARGETDIR=aarch64

82258

@@ -11540,6 +11548,7 @@

82259

82260

powerpc*-*-linux* | powerpc-*-sysv*)

82261

TARGET=POWERPC; TARGETDIR=powerpc

82262

+ HAVE_LONG_DOUBLE_VARIANT=1

82263

;;

82264

powerpc-*-amigaos*)

82265

TARGET=POWERPC; TARGETDIR=powerpc

82266

@@ -11555,6 +11564,7 @@

82267

;;

82268

powerpc-*-freebsd* | powerpc-*-openbsd*)

82269

TARGET=POWERPC_FREEBSD; TARGETDIR=powerpc

82270

+ HAVE_LONG_DOUBLE_VARIANT=1

82271

;;

82272

powerpc64-*-freebsd*)

82273

TARGET=POWERPC; TARGETDIR=powerpc

82274

@@ -12230,17 +12240,25 @@

82275

# Also AC_SUBST this variable for ffi.h.

82276

if test -z "$HAVE_LONG_DOUBLE"; then

82277

HAVE_LONG_DOUBLE=0

82278

- if test $ac_cv_sizeof_double != $ac_cv_sizeof_long_double; then

82279

- if test $ac_cv_sizeof_long_double != 0; then

82280

+ if test $ac_cv_sizeof_long_double != 0; then

82281

+ if test $HAVE_LONG_DOUBLE_VARIANT != 0; then

82282

+

82283

+$as_echo "#define HAVE_LONG_DOUBLE_VARIANT 1" >>confdefs.h

82284

+

82285

HAVE_LONG_DOUBLE=1

82286

+ else

82287

+ if test $ac_cv_sizeof_double != $ac_cv_sizeof_long_double; then

82288

+ HAVE_LONG_DOUBLE=1

82289

82290

$as_echo "#define HAVE_LONG_DOUBLE 1" >>confdefs.h

82291

82292

+ fi

82293

fi

82294

fi

82295

fi

82296

82297

82298

+

82299

{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether byte ordering is bigendian" >&5

82300

$as_echo_n "checking whether byte ordering is bigendian... " >&6; }

82301

if test "${ac_cv_c_bigendian+set}" = set; then :

82302

Index: libffi/Makefile.in

82303

===================================================================

82304

--- a/src/libffi/Makefile.in (.../tags/gcc_4_8_2_release)

82305

+++ b/src/libffi/Makefile.in (.../branches/gcc-4_8-branch)

82306

@@ -48,10 +48,10 @@

82307

@IA64_TRUE@am__append_11 = src/ia64/ffi.c src/ia64/unix.S

82308

@M32R_TRUE@am__append_12 = src/m32r/sysv.S src/m32r/ffi.c

82309

@M68K_TRUE@am__append_13 = src/m68k/ffi.c src/m68k/sysv.S

82310

-@POWERPC_TRUE@am__append_14 = src/powerpc/ffi.c src/powerpc/sysv.S src/powerpc/ppc_closure.S src/powerpc/linux64.S src/powerpc/linux64_closure.S

82311

+@POWERPC_TRUE@am__append_14 = src/powerpc/ffi.c src/powerpc/ffi_sysv.c src/powerpc/ffi_linux64.c src/powerpc/sysv.S src/powerpc/ppc_closure.S src/powerpc/linux64.S src/powerpc/linux64_closure.S

82312

@POWERPC_AIX_TRUE@am__append_15 = src/powerpc/ffi_darwin.c src/powerpc/aix.S src/powerpc/aix_closure.S

82313

@POWERPC_DARWIN_TRUE@am__append_16 = src/powerpc/ffi_darwin.c src/powerpc/darwin.S src/powerpc/darwin_closure.S

82314

-@POWERPC_FREEBSD_TRUE@am__append_17 = src/powerpc/ffi.c src/powerpc/sysv.S src/powerpc/ppc_closure.S

82315

+@POWERPC_FREEBSD_TRUE@am__append_17 = src/powerpc/ffi.c src/powerpc/ffi_sysv.c src/powerpc/sysv.S src/powerpc/ppc_closure.S

82316

@AARCH64_TRUE@am__append_18 = src/aarch64/sysv.S src/aarch64/ffi.c

82317

@ARM_TRUE@am__append_19 = src/arm/sysv.S src/arm/ffi.c

82318

@ARM_TRUE@@FFI_EXEC_TRAMPOLINE_TABLE_TRUE@am__append_20 = src/arm/trampoline.S

82319

@@ -133,7 +133,9 @@

82320

@IA64_TRUE@am__objects_11 = src/ia64/ffi.lo src/ia64/unix.lo

82321

@M32R_TRUE@am__objects_12 = src/m32r/sysv.lo src/m32r/ffi.lo

82322

@M68K_TRUE@am__objects_13 = src/m68k/ffi.lo src/m68k/sysv.lo

82323

-@POWERPC_TRUE@am__objects_14 = src/powerpc/ffi.lo src/powerpc/sysv.lo \

82324

+@POWERPC_TRUE@am__objects_14 = src/powerpc/ffi.lo \

82325

+@POWERPC_TRUE@ src/powerpc/ffi_sysv.lo \

82326

+@POWERPC_TRUE@ src/powerpc/ffi_linux64.lo src/powerpc/sysv.lo \

82327

@POWERPC_TRUE@ src/powerpc/ppc_closure.lo \

82328

@POWERPC_TRUE@ src/powerpc/linux64.lo \

82329

@POWERPC_TRUE@ src/powerpc/linux64_closure.lo

82330

@@ -144,6 +146,7 @@

82331

@POWERPC_DARWIN_TRUE@ src/powerpc/darwin.lo \

82332

@POWERPC_DARWIN_TRUE@ src/powerpc/darwin_closure.lo

82333

@POWERPC_FREEBSD_TRUE@am__objects_17 = src/powerpc/ffi.lo \

82334

+@POWERPC_FREEBSD_TRUE@ src/powerpc/ffi_sysv.lo \

82335

@POWERPC_FREEBSD_TRUE@ src/powerpc/sysv.lo \

82336

@POWERPC_FREEBSD_TRUE@ src/powerpc/ppc_closure.lo

82337

@AARCH64_TRUE@am__objects_18 = src/aarch64/sysv.lo src/aarch64/ffi.lo

82338

@@ -278,6 +281,7 @@

82339

FGREP = @FGREP@

82340

GREP = @GREP@

82341

HAVE_LONG_DOUBLE = @HAVE_LONG_DOUBLE@

82342

+HAVE_LONG_DOUBLE_VARIANT = @HAVE_LONG_DOUBLE_VARIANT@

82343

INSTALL = @INSTALL@

82344

INSTALL_DATA = @INSTALL_DATA@

82345

INSTALL_PROGRAM = @INSTALL_PROGRAM@

82346

@@ -387,10 +391,12 @@

82347

src/ia64/unix.S src/mips/ffi.c src/mips/n32.S src/mips/o32.S \

82348

src/mips/ffitarget.h src/m32r/ffi.c src/m32r/sysv.S \

82349

src/m32r/ffitarget.h src/m68k/ffi.c src/m68k/sysv.S \

82350

- src/m68k/ffitarget.h src/powerpc/ffi.c src/powerpc/sysv.S \

82351

- src/powerpc/linux64.S src/powerpc/linux64_closure.S \

82352

- src/powerpc/ppc_closure.S src/powerpc/asm.h \

82353

- src/powerpc/aix.S src/powerpc/darwin.S \

82354

+ src/m68k/ffitarget.h \

82355

+ src/powerpc/ffi.c src/powerpc/ffi_powerpc.h \

82356

+ src/powerpc/ffi_sysv.c src/powerpc/ffi_linux64.c \

82357

+ src/powerpc/sysv.S src/powerpc/linux64.S \

82358

+ src/powerpc/linux64_closure.S src/powerpc/ppc_closure.S \

82359

+ src/powerpc/asm.h src/powerpc/aix.S src/powerpc/darwin.S \

82360

src/powerpc/aix_closure.S src/powerpc/darwin_closure.S \

82361

src/powerpc/ffi_darwin.c src/powerpc/ffitarget.h \

82362

src/s390/ffi.c src/s390/sysv.S src/s390/ffitarget.h \

82363

@@ -711,6 +717,10 @@

82364

@: > src/powerpc/$(DEPDIR)/$(am__dirstamp)

82365

src/powerpc/ffi.lo: src/powerpc/$(am__dirstamp) \

82366

src/powerpc/$(DEPDIR)/$(am__dirstamp)

82367

+src/powerpc/ffi_sysv.lo: src/powerpc/$(am__dirstamp) \

82368

+ src/powerpc/$(DEPDIR)/$(am__dirstamp)

82369

+src/powerpc/ffi_linux64.lo: src/powerpc/$(am__dirstamp) \

82370

+ src/powerpc/$(DEPDIR)/$(am__dirstamp)

82371

src/powerpc/sysv.lo: src/powerpc/$(am__dirstamp) \

82372

src/powerpc/$(DEPDIR)/$(am__dirstamp)

82373

src/powerpc/ppc_closure.lo: src/powerpc/$(am__dirstamp) \

82374

@@ -912,6 +922,10 @@

82375

-rm -f src/powerpc/ffi.lo

82376

-rm -f src/powerpc/ffi_darwin.$(OBJEXT)

82377

-rm -f src/powerpc/ffi_darwin.lo

82378

+ -rm -f src/powerpc/ffi_linux64.$(OBJEXT)

82379

+ -rm -f src/powerpc/ffi_linux64.lo

82380

+ -rm -f src/powerpc/ffi_sysv.$(OBJEXT)

82381

+ -rm -f src/powerpc/ffi_sysv.lo

82382

-rm -f src/powerpc/linux64.$(OBJEXT)

82383

-rm -f src/powerpc/linux64.lo

82384

-rm -f src/powerpc/linux64_closure.$(OBJEXT)

82385

@@ -1009,6 +1023,8 @@

82386

@AMDEP_TRUE@@am__include@ @am__quote@src/powerpc/$(DEPDIR)/darwin_closure.Plo@am__quote@

82387

@AMDEP_TRUE@@am__include@ @am__quote@src/powerpc/$(DEPDIR)/ffi.Plo@am__quote@

82388

@AMDEP_TRUE@@am__include@ @am__quote@src/powerpc/$(DEPDIR)/ffi_darwin.Plo@am__quote@

82389

+@AMDEP_TRUE@@am__include@ @am__quote@src/powerpc/$(DEPDIR)/ffi_linux64.Plo@am__quote@

82390

+@AMDEP_TRUE@@am__include@ @am__quote@src/powerpc/$(DEPDIR)/ffi_sysv.Plo@am__quote@

82391

@AMDEP_TRUE@@am__include@ @am__quote@src/powerpc/$(DEPDIR)/linux64.Plo@am__quote@

82392

@AMDEP_TRUE@@am__include@ @am__quote@src/powerpc/$(DEPDIR)/linux64_closure.Plo@am__quote@

82393

@AMDEP_TRUE@@am__include@ @am__quote@src/powerpc/$(DEPDIR)/ppc_closure.Plo@am__quote@

82394

Index: libffi/include/ffi.h.in

82395

===================================================================

82396

--- a/src/libffi/include/ffi.h.in (.../tags/gcc_4_8_2_release)

82397

+++ b/src/libffi/include/ffi.h.in (.../branches/gcc-4_8-branch)

82398

@@ -207,6 +207,11 @@

82399

#endif

82400

} ffi_cif;

82401

82402

+#if HAVE_LONG_DOUBLE_VARIANT

82403

+/* Used to adjust size/alignment of ffi types. */

82404

+void ffi_prep_types (ffi_abi abi);

82405

+# endif

82406

+

82407

/* Used internally, but overridden by some architectures */

82408

ffi_status ffi_prep_cif_core(ffi_cif *cif,

82409

ffi_abi abi,

82410

Index: libffi/include/Makefile.in

82411

===================================================================

82412

--- a/src/libffi/include/Makefile.in (.../tags/gcc_4_8_2_release)

82413

+++ b/src/libffi/include/Makefile.in (.../branches/gcc-4_8-branch)

82414

@@ -113,6 +113,7 @@

82415

FGREP = @FGREP@

82416

GREP = @GREP@

82417

HAVE_LONG_DOUBLE = @HAVE_LONG_DOUBLE@

82418

+HAVE_LONG_DOUBLE_VARIANT = @HAVE_LONG_DOUBLE_VARIANT@

82419

INSTALL = @INSTALL@

82420

INSTALL_DATA = @INSTALL_DATA@

82421

INSTALL_PROGRAM = @INSTALL_PROGRAM@

82422

Index: libffi/fficonfig.h.in

82423

===================================================================

82424

--- a/src/libffi/fficonfig.h.in (.../tags/gcc_4_8_2_release)

82425

+++ b/src/libffi/fficonfig.h.in (.../branches/gcc-4_8-branch)

82426

@@ -73,6 +73,9 @@

82427

/* Define if you have the long double type and it is bigger than a double */

82428

#undef HAVE_LONG_DOUBLE

82429

82430

+/* Define if you support more than one size of the long double type */

82431

+#undef HAVE_LONG_DOUBLE_VARIANT

82432

+

82433

/* Define to 1 if you have the `memcpy' function. */

82434

#undef HAVE_MEMCPY

82435

82436

Index: libffi/src/powerpc/ppc_closure.S

82437

===================================================================

82438

--- a/src/libffi/src/powerpc/ppc_closure.S (.../tags/gcc_4_8_2_release)

82439

+++ b/src/libffi/src/powerpc/ppc_closure.S (.../branches/gcc-4_8-branch)

82440

@@ -31,7 +31,7 @@

82441

82442

.file "ppc_closure.S"

82443

82444

-#ifndef __powerpc64__

82445

+#ifndef POWERPC64

82446

82447

ENTRY(ffi_closure_SYSV)

82448

.LFB1:

82449

@@ -238,7 +238,7 @@

82450

lwz %r3,112+0(%r1)

82451

lwz %r4,112+4(%r1)

82452

lwz %r5,112+8(%r1)

82453

- bl .Luint128

82454

+ b .Luint128

82455

82456

# The return types below are only used when the ABI type is FFI_SYSV.

82457

# case FFI_SYSV_TYPE_SMALL_STRUCT + 1. One byte struct.

82458

@@ -378,8 +378,7 @@

82459

.align 2

82460

.LEFDE1:

82461

82462

-#endif

82463

-

82464

#if defined __ELF__ && defined __linux__

82465

.section .note.GNU-stack,"",@progbits

82466

#endif

82467

+#endif

82468

Index: libffi/src/powerpc/ffitarget.h

82469

===================================================================

82470

--- a/src/libffi/src/powerpc/ffitarget.h (.../tags/gcc_4_8_2_release)

82471

+++ b/src/libffi/src/powerpc/ffitarget.h (.../branches/gcc-4_8-branch)

82472

@@ -60,45 +60,76 @@

82473

typedef enum ffi_abi {

82474

FFI_FIRST_ABI = 0,

82475

82476

-#ifdef POWERPC

82477

- FFI_SYSV,

82478

- FFI_GCC_SYSV,

82479

- FFI_LINUX64,

82480

- FFI_LINUX,

82481

- FFI_LINUX_SOFT_FLOAT,

82482

-# if defined(POWERPC64)

82483

- FFI_DEFAULT_ABI = FFI_LINUX64,

82484

-# elif defined(__NO_FPRS__)

82485

- FFI_DEFAULT_ABI = FFI_LINUX_SOFT_FLOAT,

82486

-# elif (__LDBL_MANT_DIG__ == 106)

82487

- FFI_DEFAULT_ABI = FFI_LINUX,

82488

-# else

82489

- FFI_DEFAULT_ABI = FFI_GCC_SYSV,

82490

-# endif

82491

-#endif

82492

-

82493

-#ifdef POWERPC_AIX

82494

+#if defined (POWERPC_AIX)

82495

FFI_AIX,

82496

FFI_DARWIN,

82497

FFI_DEFAULT_ABI = FFI_AIX,

82498

-#endif

82499

+ FFI_LAST_ABI

82500

82501

-#ifdef POWERPC_DARWIN

82502

+#elif defined (POWERPC_DARWIN)

82503

FFI_AIX,

82504

FFI_DARWIN,

82505

FFI_DEFAULT_ABI = FFI_DARWIN,

82506

-#endif

82507

+ FFI_LAST_ABI

82508

82509

-#ifdef POWERPC_FREEBSD

82510

- FFI_SYSV,

82511

- FFI_GCC_SYSV,

82512

- FFI_LINUX64,

82513

- FFI_LINUX,

82514

- FFI_LINUX_SOFT_FLOAT,

82515

- FFI_DEFAULT_ABI = FFI_SYSV,

82516

+#else

82517

+ /* The FFI_COMPAT values are used by old code. Since libffi may be

82518

+ a shared library we have to support old values for backwards

82519

+ compatibility. */

82520

+ FFI_COMPAT_SYSV,

82521

+ FFI_COMPAT_GCC_SYSV,

82522

+ FFI_COMPAT_LINUX64,

82523

+ FFI_COMPAT_LINUX,

82524

+ FFI_COMPAT_LINUX_SOFT_FLOAT,

82525

+

82526

+# if defined (POWERPC64)

82527

+ /* This bit, always set in new code, must not be set in any of the

82528

+ old FFI_COMPAT values that might be used for 64-bit linux. We

82529

+ only need worry about FFI_COMPAT_LINUX64, but to be safe avoid

82530

+ all old values. */

82531

+ FFI_LINUX = 8,

82532

+ /* This and following bits can reuse FFI_COMPAT values. */

82533

+ FFI_LINUX_STRUCT_ALIGN = 1,

82534

+ FFI_LINUX_LONG_DOUBLE_128 = 2,

82535

+ FFI_DEFAULT_ABI = (FFI_LINUX

82536

+# ifdef __STRUCT_PARM_ALIGN__

82537

+ | FFI_LINUX_STRUCT_ALIGN

82538

+# endif

82539

+# ifdef __LONG_DOUBLE_128__

82540

+ | FFI_LINUX_LONG_DOUBLE_128

82541

+# endif

82542

+ ),

82543

+ FFI_LAST_ABI = 12

82544

+

82545

+# else

82546

+ /* This bit, always set in new code, must not be set in any of the

82547

+ old FFI_COMPAT values that might be used for 32-bit linux/sysv/bsd. */

82548

+ FFI_SYSV = 8,

82549

+ /* This and following bits can reuse FFI_COMPAT values. */

82550

+ FFI_SYSV_SOFT_FLOAT = 1,

82551

+ FFI_SYSV_STRUCT_RET = 2,

82552

+ FFI_SYSV_IBM_LONG_DOUBLE = 4,

82553

+ FFI_SYSV_LONG_DOUBLE_128 = 16,

82554

+

82555

+ FFI_DEFAULT_ABI = (FFI_SYSV

82556

+# ifdef __NO_FPRS__

82557

+ | FFI_SYSV_SOFT_FLOAT

82558

+# endif

82559

+# if (defined (__SVR4_STRUCT_RETURN) \

82560

+ || defined (POWERPC_FREEBSD) && !defined (__AIX_STRUCT_RETURN))

82561

+ | FFI_SYSV_STRUCT_RET

82562

+# endif

82563

+# if __LDBL_MANT_DIG__ == 106

82564

+ | FFI_SYSV_IBM_LONG_DOUBLE

82565

+# endif

82566

+# ifdef __LONG_DOUBLE_128__

82567

+ | FFI_SYSV_LONG_DOUBLE_128

82568

+# endif

82569

+ ),

82570

+ FFI_LAST_ABI = 32

82571

+# endif

82572

#endif

82573

82574

- FFI_LAST_ABI

82575

} ffi_abi;

82576

#endif

82577

82578

@@ -106,6 +137,10 @@

82579

82580

#define FFI_CLOSURES 1

82581

#define FFI_NATIVE_RAW_API 0

82582

+#if defined (POWERPC) || defined (POWERPC_FREEBSD)

82583

+# define FFI_TARGET_SPECIFIC_VARIADIC 1

82584

+# define FFI_EXTRA_CIF_FIELDS unsigned nfixedargs

82585

+#endif

82586

82587

/* For additional types like the below, take care about the order in

82588

ppc_closures.S. They must follow after the FFI_TYPE_LAST. */

82589

@@ -113,19 +148,26 @@

82590

/* Needed for soft-float long-double-128 support. */

82591

#define FFI_TYPE_UINT128 (FFI_TYPE_LAST + 1)

82592

82593

-/* Needed for FFI_SYSV small structure returns.

82594

- We use two flag bits, (FLAG_SYSV_SMST_R3, FLAG_SYSV_SMST_R4) which are

82595

- defined in ffi.c, to determine the exact return type and its size. */

82596

+/* Needed for FFI_SYSV small structure returns. */

82597

#define FFI_SYSV_TYPE_SMALL_STRUCT (FFI_TYPE_LAST + 2)

82598

82599

-#if defined(POWERPC64) || defined(POWERPC_AIX)

82600

+/* Used by ELFv2 for homogenous structure returns. */

82601

+#define FFI_V2_TYPE_FLOAT_HOMOG (FFI_TYPE_LAST + 1)

82602

+#define FFI_V2_TYPE_DOUBLE_HOMOG (FFI_TYPE_LAST + 2)

82603

+#define FFI_V2_TYPE_SMALL_STRUCT (FFI_TYPE_LAST + 3)

82604

+

82605

+#if _CALL_ELF == 2

82606

+# define FFI_TRAMPOLINE_SIZE 32

82607

+#else

82608

+# if defined(POWERPC64) || defined(POWERPC_AIX)

82609

# if defined(POWERPC_DARWIN64)

82610

# define FFI_TRAMPOLINE_SIZE 48

82611

# else

82612

# define FFI_TRAMPOLINE_SIZE 24

82613

# endif

82614

-#else /* POWERPC || POWERPC_AIX */

82615

+# else /* POWERPC || POWERPC_AIX */

82616

# define FFI_TRAMPOLINE_SIZE 40

82617

+# endif

82618

#endif

82619

82620

#ifndef LIBFFI_ASM

82621

Index: libffi/src/powerpc/ffi.c

82622

===================================================================

82623

--- a/src/libffi/src/powerpc/ffi.c (.../tags/gcc_4_8_2_release)

82624

+++ b/src/libffi/src/powerpc/ffi.c (.../branches/gcc-4_8-branch)

82625

@@ -1,5 +1,6 @@

82626

/* -----------------------------------------------------------------------

82627

82628

82629

82630

82631

82632

82633

@@ -27,966 +28,104 @@

82634

OTHER DEALINGS IN THE SOFTWARE.

82635

----------------------------------------------------------------------- */

82636

82637

-#include <ffi.h>

82638

-#include <ffi_common.h>

82639

+#include "ffi.h"

82640

+#include "ffi_common.h"

82641

+#include "ffi_powerpc.h"

82642

82643

-#include <stdlib.h>

82644

-#include <stdio.h>

82645

-

82646

-

82647

-extern void ffi_closure_SYSV (void);

82648

-extern void FFI_HIDDEN ffi_closure_LINUX64 (void);

82649

-

82650

-enum {

82651

- /* The assembly depends on these exact flags. */

82652

- FLAG_RETURNS_SMST = 1 << (31-31), /* Used for FFI_SYSV small structs. */

82653

- FLAG_RETURNS_NOTHING = 1 << (31-30), /* These go in cr7 */

82654

-#ifndef __NO_FPRS__

82655

- FLAG_RETURNS_FP = 1 << (31-29),

82656

-#endif

82657

- FLAG_RETURNS_64BITS = 1 << (31-28),

82658

-

82659

- FLAG_RETURNS_128BITS = 1 << (31-27), /* cr6 */

82660

-

82661

- FLAG_ARG_NEEDS_COPY = 1 << (31- 7),

82662

-#ifndef __NO_FPRS__

82663

- FLAG_FP_ARGUMENTS = 1 << (31- 6), /* cr1.eq; specified by ABI */

82664

-#endif

82665

- FLAG_4_GPR_ARGUMENTS = 1 << (31- 5),

82666

- FLAG_RETVAL_REFERENCE = 1 << (31- 4)

82667

-};

82668

-

82669

-/* About the SYSV ABI. */

82670

-#define ASM_NEEDS_REGISTERS 4

82671

-#define NUM_GPR_ARG_REGISTERS 8

82672

-#ifndef __NO_FPRS__

82673

-# define NUM_FPR_ARG_REGISTERS 8

82674

-#endif

82675

-

82676

-/* ffi_prep_args_SYSV is called by the assembly routine once stack space

82677

- has been allocated for the function's arguments.

82678

-

82679

- The stack layout we want looks like this:

82680

-

82681

- | Return address from ffi_call_SYSV 4bytes | higher addresses

82682

- |--------------------------------------------|

82683

- | Previous backchain pointer 4 | stack pointer here

82684

- |--------------------------------------------|<+ <<< on entry to

82685

- | Saved r28-r31 4*4 | | ffi_call_SYSV

82686

- |--------------------------------------------| |

82687

- | GPR registers r3-r10 8*4 | | ffi_call_SYSV

82688

- |--------------------------------------------| |

82689

- | FPR registers f1-f8 (optional) 8*8 | |

82690

- |--------------------------------------------| | stack |

82691

- | Space for copied structures | | grows |

82692

- |--------------------------------------------| | down V

82693

- | Parameters that didn't fit in registers | |

82694

- |--------------------------------------------| | lower addresses

82695

- | Space for callee's LR 4 | |

82696

- |--------------------------------------------| | stack pointer here

82697

- | Current backchain pointer 4 |-/ during

82698

- |--------------------------------------------| <<< ffi_call_SYSV

82699

-

82700

-*/

82701

-

82702

-void

82703

-ffi_prep_args_SYSV (extended_cif *ecif, unsigned *const stack)

82704

+#if HAVE_LONG_DOUBLE_VARIANT

82705

+/* Adjust ffi_type_longdouble. */

82706

+void FFI_HIDDEN

82707

+ffi_prep_types (ffi_abi abi)

82708

{

82709

- const unsigned bytes = ecif->cif->bytes;

82710

- const unsigned flags = ecif->cif->flags;

82711

-

82712

- typedef union {

82713

- char *c;

82714

- unsigned *u;

82715

- long long *ll;

82716

- float *f;

82717

- double *d;

82718

- } valp;

82719

-

82720

- /* 'stacktop' points at the previous backchain pointer. */

82721

- valp stacktop;

82722

-

82723

- /* 'gpr_base' points at the space for gpr3, and grows upwards as

82724

- we use GPR registers. */

82725

- valp gpr_base;

82726

- int intarg_count;

82727

-

82728

-#ifndef __NO_FPRS__

82729

- /* 'fpr_base' points at the space for fpr1, and grows upwards as

82730

- we use FPR registers. */

82731

- valp fpr_base;

82732

- int fparg_count;

82733

-#endif

82734

-

82735

- /* 'copy_space' grows down as we put structures in it. It should

82736

- stay 16-byte aligned. */

82737

- valp copy_space;

82738

-

82739

- /* 'next_arg' grows up as we put parameters in it. */

82740

- valp next_arg;

82741

-

82742

- int i;

82743

- ffi_type **ptr;

82744

-#ifndef __NO_FPRS__

82745

- double double_tmp;

82746

-#endif

82747

- union {

82748

- void **v;

82749

- char **c;

82750

- signed char **sc;

82751

- unsigned char **uc;

82752

- signed short **ss;

82753

- unsigned short **us;

82754

- unsigned int **ui;

82755

- long long **ll;

82756

- float **f;

82757

- double **d;

82758

- } p_argv;

82759

- size_t struct_copy_size;

82760

- unsigned gprvalue;

82761

-

82762

- stacktop.c = (char *) stack + bytes;

82763

- gpr_base.u = stacktop.u - ASM_NEEDS_REGISTERS - NUM_GPR_ARG_REGISTERS;

82764

- intarg_count = 0;

82765

-#ifndef __NO_FPRS__

82766

- fpr_base.d = gpr_base.d - NUM_FPR_ARG_REGISTERS;

82767

- fparg_count = 0;

82768

- copy_space.c = ((flags & FLAG_FP_ARGUMENTS) ? fpr_base.c : gpr_base.c);

82769

-#else

82770

- copy_space.c = gpr_base.c;

82771

-#endif

82772

- next_arg.u = stack + 2;

82773

-

82774

- /* Check that everything starts aligned properly. */

82775

- FFI_ASSERT (((unsigned long) (char *) stack & 0xF) == 0);

82776

- FFI_ASSERT (((unsigned long) copy_space.c & 0xF) == 0);

82777

- FFI_ASSERT (((unsigned long) stacktop.c & 0xF) == 0);

82778

- FFI_ASSERT ((bytes & 0xF) == 0);

82779

- FFI_ASSERT (copy_space.c >= next_arg.c);

82780

-

82781

- /* Deal with return values that are actually pass-by-reference. */

82782

- if (flags & FLAG_RETVAL_REFERENCE)

82783

- {

82784

- *gpr_base.u++ = (unsigned long) (char *) ecif->rvalue;

82785

- intarg_count++;

82786

- }

82787

-

82788

- /* Now for the arguments. */

82789

- p_argv.v = ecif->avalue;

82790

- for (ptr = ecif->cif->arg_types, i = ecif->cif->nargs;

82791

- i > 0;

82792

- i--, ptr++, p_argv.v++)

82793

- {

82794

- unsigned short typenum = (*ptr)->type;

82795

-

82796

- /* We may need to handle some values depending on ABI */

82797

- if (ecif->cif->abi == FFI_LINUX_SOFT_FLOAT) {

82798

- if (typenum == FFI_TYPE_FLOAT)

82799

- typenum = FFI_TYPE_UINT32;

82800

- if (typenum == FFI_TYPE_DOUBLE)

82801

- typenum = FFI_TYPE_UINT64;

82802

- if (typenum == FFI_TYPE_LONGDOUBLE)

82803

- typenum = FFI_TYPE_UINT128;

82804

- } else if (ecif->cif->abi != FFI_LINUX) {

82805

-#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

82806

- if (typenum == FFI_TYPE_LONGDOUBLE)

82807

- typenum = FFI_TYPE_STRUCT;

82808

-#endif

82809

- }

82810

-

82811

- /* Now test the translated value */

82812

- switch (typenum) {

82813

-#ifndef __NO_FPRS__

82814

- case FFI_TYPE_FLOAT:

82815

- /* With FFI_LINUX_SOFT_FLOAT floats are handled like UINT32. */

82816

- double_tmp = **p_argv.f;

82817

- if (fparg_count >= NUM_FPR_ARG_REGISTERS)

82818

- {

82819

- *next_arg.f = (float) double_tmp;

82820

- next_arg.u += 1;

82821

- intarg_count++;

82822

- }

82823

- else

82824

- *fpr_base.d++ = double_tmp;

82825

- fparg_count++;

82826

- FFI_ASSERT (flags & FLAG_FP_ARGUMENTS);

82827

- break;

82828

-

82829

- case FFI_TYPE_DOUBLE:

82830

- /* With FFI_LINUX_SOFT_FLOAT doubles are handled like UINT64. */

82831

- double_tmp = **p_argv.d;

82832

-

82833

- if (fparg_count >= NUM_FPR_ARG_REGISTERS)

82834

- {

82835

- if (intarg_count >= NUM_GPR_ARG_REGISTERS

82836

- && intarg_count % 2 != 0)

82837

- {

82838

- intarg_count++;

82839

- next_arg.u++;

82840

- }

82841

- *next_arg.d = double_tmp;

82842

- next_arg.u += 2;

82843

- }

82844

- else

82845

- *fpr_base.d++ = double_tmp;

82846

- fparg_count++;

82847

- FFI_ASSERT (flags & FLAG_FP_ARGUMENTS);

82848

- break;

82849

-

82850

-#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

82851

- case FFI_TYPE_LONGDOUBLE:

82852

- double_tmp = (*p_argv.d)[0];

82853

-

82854

- if (fparg_count >= NUM_FPR_ARG_REGISTERS - 1)

82855

- {

82856

- if (intarg_count >= NUM_GPR_ARG_REGISTERS

82857

- && intarg_count % 2 != 0)

82858

- {

82859

- intarg_count++;

82860

- next_arg.u++;

82861

- }

82862

- *next_arg.d = double_tmp;

82863

- next_arg.u += 2;

82864

- double_tmp = (*p_argv.d)[1];

82865

- *next_arg.d = double_tmp;

82866

- next_arg.u += 2;

82867

- }

82868

- else

82869

- {

82870

- *fpr_base.d++ = double_tmp;

82871

- double_tmp = (*p_argv.d)[1];

82872

- *fpr_base.d++ = double_tmp;

82873

- }

82874

-

82875

- fparg_count += 2;

82876

- FFI_ASSERT (flags & FLAG_FP_ARGUMENTS);

82877

- break;

82878

-#endif

82879

-#endif /* have FPRs */

82880

-

82881

- /*

82882

- * The soft float ABI for long doubles works like this, a long double

82883

- * is passed in four consecutive GPRs if available. A maximum of 2

82884

- * long doubles can be passed in gprs. If we do not have 4 GPRs

82885

- * left, the long double is passed on the stack, 4-byte aligned.

82886

- */

82887

- case FFI_TYPE_UINT128: {

82888

- unsigned int int_tmp = (*p_argv.ui)[0];

82889

- unsigned int ii;

82890

- if (intarg_count >= NUM_GPR_ARG_REGISTERS - 3) {

82891

- if (intarg_count < NUM_GPR_ARG_REGISTERS)

82892

- intarg_count += NUM_GPR_ARG_REGISTERS - intarg_count;

82893

- *(next_arg.u++) = int_tmp;

82894

- for (ii = 1; ii < 4; ii++) {

82895

- int_tmp = (*p_argv.ui)[ii];

82896

- *(next_arg.u++) = int_tmp;

82897

- }

82898

- } else {

82899

- *(gpr_base.u++) = int_tmp;

82900

- for (ii = 1; ii < 4; ii++) {

82901

- int_tmp = (*p_argv.ui)[ii];

82902

- *(gpr_base.u++) = int_tmp;

82903

- }

82904

- }

82905

- intarg_count += 4;

82906

- break;

82907

- }

82908

-

82909

- case FFI_TYPE_UINT64:

82910

- case FFI_TYPE_SINT64:

82911

- if (intarg_count == NUM_GPR_ARG_REGISTERS-1)

82912

- intarg_count++;

82913

- if (intarg_count >= NUM_GPR_ARG_REGISTERS)

82914

- {

82915

- if (intarg_count % 2 != 0)

82916

- {

82917

- intarg_count++;

82918

- next_arg.u++;

82919

- }

82920

- *next_arg.ll = **p_argv.ll;

82921

- next_arg.u += 2;

82922

- }

82923

- else

82924

- {

82925

- /* whoops: abi states only certain register pairs

82926

- * can be used for passing long long int

82927

- * specifically (r3,r4), (r5,r6), (r7,r8),

82928

- * (r9,r10) and if next arg is long long but

82929

- * not correct starting register of pair then skip

82930

- * until the proper starting register

82931

- */

82932

- if (intarg_count % 2 != 0)

82933

- {

82934

- intarg_count ++;

82935

- gpr_base.u++;

82936

- }

82937

- *gpr_base.ll++ = **p_argv.ll;

82938

- }

82939

- intarg_count += 2;

82940

- break;

82941

-

82942

- case FFI_TYPE_STRUCT:

82943

- struct_copy_size = ((*ptr)->size + 15) & ~0xF;

82944

- copy_space.c -= struct_copy_size;

82945

- memcpy (copy_space.c, *p_argv.c, (*ptr)->size);

82946

-

82947

- gprvalue = (unsigned long) copy_space.c;

82948

-

82949

- FFI_ASSERT (copy_space.c > next_arg.c);

82950

- FFI_ASSERT (flags & FLAG_ARG_NEEDS_COPY);

82951

- goto putgpr;

82952

-

82953

- case FFI_TYPE_UINT8:

82954

- gprvalue = **p_argv.uc;

82955

- goto putgpr;

82956

- case FFI_TYPE_SINT8:

82957

- gprvalue = **p_argv.sc;

82958

- goto putgpr;

82959

- case FFI_TYPE_UINT16:

82960

- gprvalue = **p_argv.us;

82961

- goto putgpr;

82962

- case FFI_TYPE_SINT16:

82963

- gprvalue = **p_argv.ss;

82964

- goto putgpr;

82965

-

82966

- case FFI_TYPE_INT:

82967

- case FFI_TYPE_UINT32:

82968

- case FFI_TYPE_SINT32:

82969

- case FFI_TYPE_POINTER:

82970

-

82971

- gprvalue = **p_argv.ui;

82972

-

82973

- putgpr:

82974

- if (intarg_count >= NUM_GPR_ARG_REGISTERS)

82975

- *next_arg.u++ = gprvalue;

82976

- else

82977

- *gpr_base.u++ = gprvalue;

82978

- intarg_count++;

82979

- break;

82980

- }

82981

- }

82982

-

82983

- /* Check that we didn't overrun the stack... */

82984

- FFI_ASSERT (copy_space.c >= next_arg.c);

82985

- FFI_ASSERT (gpr_base.u <= stacktop.u - ASM_NEEDS_REGISTERS);

82986

-#ifndef __NO_FPRS__

82987

- FFI_ASSERT (fpr_base.u

82988

- <= stacktop.u - ASM_NEEDS_REGISTERS - NUM_GPR_ARG_REGISTERS);

82989

-#endif

82990

- FFI_ASSERT (flags & FLAG_4_GPR_ARGUMENTS || intarg_count <= 4);

82991

+# if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

82992

+# ifdef POWERPC64

82993

+ ffi_prep_types_linux64 (abi);

82994

+# else

82995

+ ffi_prep_types_sysv (abi);

82996

+# endif

82997

+# endif

82998

}

82999

-

83000

-/* About the LINUX64 ABI. */

83001

-enum {

83002

- NUM_GPR_ARG_REGISTERS64 = 8,

83003

- NUM_FPR_ARG_REGISTERS64 = 13

83004

-};

83005

-enum { ASM_NEEDS_REGISTERS64 = 4 };

83006

-

83007

-/* ffi_prep_args64 is called by the assembly routine once stack space

83008

- has been allocated for the function's arguments.

83009

-

83010

- The stack layout we want looks like this:

83011

-

83012

- | Ret addr from ffi_call_LINUX64 8bytes | higher addresses

83013

- |--------------------------------------------|

83014

- | CR save area 8bytes |

83015

- |--------------------------------------------|

83016

- | Previous backchain pointer 8 | stack pointer here

83017

- |--------------------------------------------|<+ <<< on entry to

83018

- | Saved r28-r31 4*8 | | ffi_call_LINUX64

83019

- |--------------------------------------------| |

83020

- | GPR registers r3-r10 8*8 | |

83021

- |--------------------------------------------| |

83022

- | FPR registers f1-f13 (optional) 13*8 | |

83023

- |--------------------------------------------| |

83024

- | Parameter save area | |

83025

- |--------------------------------------------| |

83026

- | TOC save area 8 | |

83027

- |--------------------------------------------| | stack |

83028

- | Linker doubleword 8 | | grows |

83029

- |--------------------------------------------| | down V

83030

- | Compiler doubleword 8 | |

83031

- |--------------------------------------------| | lower addresses

83032

- | Space for callee's LR 8 | |

83033

- |--------------------------------------------| |

83034

- | CR save area 8 | |

83035

- |--------------------------------------------| | stack pointer here

83036

- | Current backchain pointer 8 |-/ during

83037

- |--------------------------------------------| <<< ffi_call_LINUX64

83038

-

83039

-*/

83040

-

83041

-void FFI_HIDDEN

83042

-ffi_prep_args64 (extended_cif *ecif, unsigned long *const stack)

83043

-{

83044

- const unsigned long bytes = ecif->cif->bytes;

83045

- const unsigned long flags = ecif->cif->flags;

83046

-

83047

- typedef union {

83048

- char *c;

83049

- unsigned long *ul;

83050

- float *f;

83051

- double *d;

83052

- } valp;

83053

-

83054

- /* 'stacktop' points at the previous backchain pointer. */

83055

- valp stacktop;

83056

-

83057

- /* 'next_arg' points at the space for gpr3, and grows upwards as

83058

- we use GPR registers, then continues at rest. */

83059

- valp gpr_base;

83060

- valp gpr_end;

83061

- valp rest;

83062

- valp next_arg;

83063

-

83064

- /* 'fpr_base' points at the space for fpr3, and grows upwards as

83065

- we use FPR registers. */

83066

- valp fpr_base;

83067

- int fparg_count;

83068

-

83069

- int i, words;

83070

- ffi_type **ptr;

83071

- double double_tmp;

83072

- union {

83073

- void **v;

83074

- char **c;

83075

- signed char **sc;

83076

- unsigned char **uc;

83077

- signed short **ss;

83078

- unsigned short **us;

83079

- signed int **si;

83080

- unsigned int **ui;

83081

- unsigned long **ul;

83082

- float **f;

83083

- double **d;

83084

- } p_argv;

83085

- unsigned long gprvalue;

83086

-

83087

- stacktop.c = (char *) stack + bytes;

83088

- gpr_base.ul = stacktop.ul - ASM_NEEDS_REGISTERS64 - NUM_GPR_ARG_REGISTERS64;

83089

- gpr_end.ul = gpr_base.ul + NUM_GPR_ARG_REGISTERS64;

83090

- rest.ul = stack + 6 + NUM_GPR_ARG_REGISTERS64;

83091

- fpr_base.d = gpr_base.d - NUM_FPR_ARG_REGISTERS64;

83092

- fparg_count = 0;

83093

- next_arg.ul = gpr_base.ul;

83094

-

83095

- /* Check that everything starts aligned properly. */

83096

- FFI_ASSERT (((unsigned long) (char *) stack & 0xF) == 0);

83097

- FFI_ASSERT (((unsigned long) stacktop.c & 0xF) == 0);

83098

- FFI_ASSERT ((bytes & 0xF) == 0);

83099

-

83100

- /* Deal with return values that are actually pass-by-reference. */

83101

- if (flags & FLAG_RETVAL_REFERENCE)

83102

- *next_arg.ul++ = (unsigned long) (char *) ecif->rvalue;

83103

-

83104

- /* Now for the arguments. */

83105

- p_argv.v = ecif->avalue;

83106

- for (ptr = ecif->cif->arg_types, i = ecif->cif->nargs;

83107

- i > 0;

83108

- i--, ptr++, p_argv.v++)

83109

- {

83110

- switch ((*ptr)->type)

83111

- {

83112

- case FFI_TYPE_FLOAT:

83113

- double_tmp = **p_argv.f;

83114

- *next_arg.f = (float) double_tmp;

83115

- if (++next_arg.ul == gpr_end.ul)

83116

- next_arg.ul = rest.ul;

83117

- if (fparg_count < NUM_FPR_ARG_REGISTERS64)

83118

- *fpr_base.d++ = double_tmp;

83119

- fparg_count++;

83120

- FFI_ASSERT (flags & FLAG_FP_ARGUMENTS);

83121

- break;

83122

-

83123

- case FFI_TYPE_DOUBLE:

83124

- double_tmp = **p_argv.d;

83125

- *next_arg.d = double_tmp;

83126

- if (++next_arg.ul == gpr_end.ul)

83127

- next_arg.ul = rest.ul;

83128

- if (fparg_count < NUM_FPR_ARG_REGISTERS64)

83129

- *fpr_base.d++ = double_tmp;

83130

- fparg_count++;

83131

- FFI_ASSERT (flags & FLAG_FP_ARGUMENTS);

83132

- break;

83133

-

83134

-#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

83135

- case FFI_TYPE_LONGDOUBLE:

83136

- double_tmp = (*p_argv.d)[0];

83137

- *next_arg.d = double_tmp;

83138

- if (++next_arg.ul == gpr_end.ul)

83139

- next_arg.ul = rest.ul;

83140

- if (fparg_count < NUM_FPR_ARG_REGISTERS64)

83141

- *fpr_base.d++ = double_tmp;

83142

- fparg_count++;

83143

- double_tmp = (*p_argv.d)[1];

83144

- *next_arg.d = double_tmp;

83145

- if (++next_arg.ul == gpr_end.ul)

83146

- next_arg.ul = rest.ul;

83147

- if (fparg_count < NUM_FPR_ARG_REGISTERS64)

83148

- *fpr_base.d++ = double_tmp;

83149

- fparg_count++;

83150

- FFI_ASSERT (__LDBL_MANT_DIG__ == 106);

83151

- FFI_ASSERT (flags & FLAG_FP_ARGUMENTS);

83152

- break;

83153

#endif

83154

83155

- case FFI_TYPE_STRUCT:

83156

- words = ((*ptr)->size + 7) / 8;

83157

- if (next_arg.ul >= gpr_base.ul && next_arg.ul + words > gpr_end.ul)

83158

- {

83159

- size_t first = gpr_end.c - next_arg.c;

83160

- memcpy (next_arg.c, *p_argv.c, first);

83161

- memcpy (rest.c, *p_argv.c + first, (*ptr)->size - first);

83162

- next_arg.c = rest.c + words * 8 - first;

83163

- }

83164

- else

83165

- {

83166

- char *where = next_arg.c;

83167

-

83168

-#ifndef __LITTLE_ENDIAN__

83169

- /* Structures with size less than eight bytes are passed

83170

- left-padded. */

83171

- if ((*ptr)->size < 8)

83172

- where += 8 - (*ptr)->size;

83173

-#endif

83174

- memcpy (where, *p_argv.c, (*ptr)->size);

83175

- next_arg.ul += words;

83176

- if (next_arg.ul == gpr_end.ul)

83177

- next_arg.ul = rest.ul;

83178

- }

83179

- break;

83180

-

83181

- case FFI_TYPE_UINT8:

83182

- gprvalue = **p_argv.uc;

83183

- goto putgpr;

83184

- case FFI_TYPE_SINT8:

83185

- gprvalue = **p_argv.sc;

83186

- goto putgpr;

83187

- case FFI_TYPE_UINT16:

83188

- gprvalue = **p_argv.us;

83189

- goto putgpr;

83190

- case FFI_TYPE_SINT16:

83191

- gprvalue = **p_argv.ss;

83192

- goto putgpr;

83193

- case FFI_TYPE_UINT32:

83194

- gprvalue = **p_argv.ui;

83195

- goto putgpr;

83196

- case FFI_TYPE_INT:

83197

- case FFI_TYPE_SINT32:

83198

- gprvalue = **p_argv.si;

83199

- goto putgpr;

83200

-

83201

- case FFI_TYPE_UINT64:

83202

- case FFI_TYPE_SINT64:

83203

- case FFI_TYPE_POINTER:

83204

- gprvalue = **p_argv.ul;

83205

- putgpr:

83206

- *next_arg.ul++ = gprvalue;

83207

- if (next_arg.ul == gpr_end.ul)

83208

- next_arg.ul = rest.ul;

83209

- break;

83210

- }

83211

- }

83212

-

83213

- FFI_ASSERT (flags & FLAG_4_GPR_ARGUMENTS

83214

- || (next_arg.ul >= gpr_base.ul

83215

- && next_arg.ul <= gpr_base.ul + 4));

83216

-}

83217

-

83218

-

83219

-

83220

/* Perform machine dependent cif processing */

83221

-ffi_status

83222

+ffi_status FFI_HIDDEN

83223

ffi_prep_cif_machdep (ffi_cif *cif)

83224

{

83225

- /* All this is for the SYSV and LINUX64 ABI. */

83226

- int i;

83227

- ffi_type **ptr;

83228

- unsigned bytes;

83229

- int fparg_count = 0, intarg_count = 0;

83230

- unsigned flags = 0;

83231

- unsigned struct_copy_size = 0;

83232

- unsigned type = cif->rtype->type;

83233

- unsigned size = cif->rtype->size;

83234

-

83235

- if (cif->abi != FFI_LINUX64)

83236

- {

83237

- /* All the machine-independent calculation of cif->bytes will be wrong.

83238

- Redo the calculation for SYSV. */

83239

-

83240

- /* Space for the frame pointer, callee's LR, and the asm's temp regs. */

83241

- bytes = (2 + ASM_NEEDS_REGISTERS) * sizeof (int);

83242

-

83243

- /* Space for the GPR registers. */

83244

- bytes += NUM_GPR_ARG_REGISTERS * sizeof (int);

83245

- }

83246

- else

83247

- {

83248

- /* 64-bit ABI. */

83249

-

83250

- /* Space for backchain, CR, LR, cc/ld doubleword, TOC and the asm's temp

83251

- regs. */

83252

- bytes = (6 + ASM_NEEDS_REGISTERS64) * sizeof (long);

83253

-

83254

- /* Space for the mandatory parm save area and general registers. */

83255

- bytes += 2 * NUM_GPR_ARG_REGISTERS64 * sizeof (long);

83256

- }

83257

-

83258

- /* Return value handling. The rules for SYSV are as follows:

83259

- - 32-bit (or less) integer values are returned in gpr3;

83260

- - Structures of size <= 4 bytes also returned in gpr3;

83261

- - 64-bit integer values and structures between 5 and 8 bytes are returned

83262

- in gpr3 and gpr4;

83263

- - Single/double FP values are returned in fpr1;

83264

- - Larger structures are allocated space and a pointer is passed as

83265

- the first argument.

83266

- - long doubles (if not equivalent to double) are returned in

83267

- fpr1,fpr2 for Linux and as for large structs for SysV.

83268

- For LINUX64:

83269

- - integer values in gpr3;

83270

- - Structures/Unions by reference;

83271

- - Single/double FP values in fpr1, long double in fpr1,fpr2.

83272

- - soft-float float/doubles are treated as UINT32/UINT64 respectivley.

83273

- - soft-float long doubles are returned in gpr3-gpr6. */

83274

- /* First translate for softfloat/nonlinux */

83275

- if (cif->abi == FFI_LINUX_SOFT_FLOAT) {

83276

- if (type == FFI_TYPE_FLOAT)

83277

- type = FFI_TYPE_UINT32;

83278

- if (type == FFI_TYPE_DOUBLE)

83279

- type = FFI_TYPE_UINT64;

83280

- if (type == FFI_TYPE_LONGDOUBLE)

83281

- type = FFI_TYPE_UINT128;

83282

- } else if (cif->abi != FFI_LINUX && cif->abi != FFI_LINUX64) {

83283

-#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

83284

- if (type == FFI_TYPE_LONGDOUBLE)

83285

- type = FFI_TYPE_STRUCT;

83286

+#ifdef POWERPC64

83287

+ return ffi_prep_cif_linux64 (cif);

83288

+#else

83289

+ return ffi_prep_cif_sysv (cif);

83290

#endif

83291

- }

83292

+}

83293

83294

- switch (type)

83295

- {

83296

-#ifndef __NO_FPRS__

83297

-#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

83298

- case FFI_TYPE_LONGDOUBLE:

83299

- flags |= FLAG_RETURNS_128BITS;

83300

- /* Fall through. */

83301

+ffi_status FFI_HIDDEN

83302

+ffi_prep_cif_machdep_var (ffi_cif *cif,

83303

+ unsigned int nfixedargs MAYBE_UNUSED,

83304

+ unsigned int ntotalargs MAYBE_UNUSED)

83305

+{

83306

+#ifdef POWERPC64

83307

+ return ffi_prep_cif_linux64_var (cif, nfixedargs, ntotalargs);

83308

+#else

83309

+ return ffi_prep_cif_sysv (cif);

83310

#endif

83311

- case FFI_TYPE_DOUBLE:

83312

- flags |= FLAG_RETURNS_64BITS;

83313

- /* Fall through. */

83314

- case FFI_TYPE_FLOAT:

83315

- flags |= FLAG_RETURNS_FP;

83316

- break;

83317

-#endif

83318

-

83319

- case FFI_TYPE_UINT128:

83320

- flags |= FLAG_RETURNS_128BITS;

83321

- /* Fall through. */

83322

- case FFI_TYPE_UINT64:

83323

- case FFI_TYPE_SINT64:

83324

- flags |= FLAG_RETURNS_64BITS;

83325

- break;

83326

-

83327

- case FFI_TYPE_STRUCT:

83328

- /*

83329

- * The final SYSV ABI says that structures smaller or equal 8 bytes

83330

- * are returned in r3/r4. The FFI_GCC_SYSV ABI instead returns them

83331

- * in memory.

83332

- *

83333

- * NOTE: The assembly code can safely assume that it just needs to

83334

- * store both r3 and r4 into a 8-byte word-aligned buffer, as

83335

- * we allocate a temporary buffer in ffi_call() if this flag is

83336

- * set.

83337

- */

83338

- if (cif->abi == FFI_SYSV && size <= 8)

83339

- flags |= FLAG_RETURNS_SMST;

83340

- intarg_count++;

83341

- flags |= FLAG_RETVAL_REFERENCE;

83342

- /* Fall through. */

83343

- case FFI_TYPE_VOID:

83344

- flags |= FLAG_RETURNS_NOTHING;

83345

- break;

83346

-

83347

- default:

83348

- /* Returns 32-bit integer, or similar. Nothing to do here. */

83349

- break;

83350

- }

83351

-

83352

- if (cif->abi != FFI_LINUX64)

83353

- /* The first NUM_GPR_ARG_REGISTERS words of integer arguments, and the

83354

- first NUM_FPR_ARG_REGISTERS fp arguments, go in registers; the rest

83355

- goes on the stack. Structures and long doubles (if not equivalent

83356

- to double) are passed as a pointer to a copy of the structure.

83357

- Stuff on the stack needs to keep proper alignment. */

83358

- for (ptr = cif->arg_types, i = cif->nargs; i > 0; i--, ptr++)

83359

- {

83360

- unsigned short typenum = (*ptr)->type;

83361

-

83362

- /* We may need to handle some values depending on ABI */

83363

- if (cif->abi == FFI_LINUX_SOFT_FLOAT) {

83364

- if (typenum == FFI_TYPE_FLOAT)

83365

- typenum = FFI_TYPE_UINT32;

83366

- if (typenum == FFI_TYPE_DOUBLE)

83367

- typenum = FFI_TYPE_UINT64;

83368

- if (typenum == FFI_TYPE_LONGDOUBLE)

83369

- typenum = FFI_TYPE_UINT128;

83370

- } else if (cif->abi != FFI_LINUX && cif->abi != FFI_LINUX64) {

83371

-#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

83372

- if (typenum == FFI_TYPE_LONGDOUBLE)

83373

- typenum = FFI_TYPE_STRUCT;

83374

-#endif

83375

- }

83376

-

83377

- switch (typenum) {

83378

-#ifndef __NO_FPRS__

83379

- case FFI_TYPE_FLOAT:

83380

- fparg_count++;

83381

- /* floating singles are not 8-aligned on stack */

83382

- break;

83383

-

83384

-#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

83385

- case FFI_TYPE_LONGDOUBLE:

83386

- fparg_count++;

83387

- /* Fall thru */

83388

-#endif

83389

- case FFI_TYPE_DOUBLE:

83390

- fparg_count++;

83391

- /* If this FP arg is going on the stack, it must be

83392

- 8-byte-aligned. */

83393

- if (fparg_count > NUM_FPR_ARG_REGISTERS

83394

- && intarg_count >= NUM_GPR_ARG_REGISTERS

83395

- && intarg_count % 2 != 0)

83396

- intarg_count++;

83397

- break;

83398

-#endif

83399

- case FFI_TYPE_UINT128:

83400

- /*

83401

- * A long double in FFI_LINUX_SOFT_FLOAT can use only a set

83402

- * of four consecutive gprs. If we do not have enough, we

83403

- * have to adjust the intarg_count value.

83404

- */

83405

- if (intarg_count >= NUM_GPR_ARG_REGISTERS - 3

83406

- && intarg_count < NUM_GPR_ARG_REGISTERS)

83407

- intarg_count = NUM_GPR_ARG_REGISTERS;

83408

- intarg_count += 4;

83409

- break;

83410

-

83411

- case FFI_TYPE_UINT64:

83412

- case FFI_TYPE_SINT64:

83413

- /* 'long long' arguments are passed as two words, but

83414

- either both words must fit in registers or both go

83415

- on the stack. If they go on the stack, they must

83416

- be 8-byte-aligned.

83417

-

83418

- Also, only certain register pairs can be used for

83419

- passing long long int -- specifically (r3,r4), (r5,r6),

83420

- (r7,r8), (r9,r10).

83421

- */

83422

- if (intarg_count == NUM_GPR_ARG_REGISTERS-1

83423

- || intarg_count % 2 != 0)

83424

- intarg_count++;

83425

- intarg_count += 2;

83426

- break;

83427

-

83428

- case FFI_TYPE_STRUCT:

83429

- /* We must allocate space for a copy of these to enforce

83430

- pass-by-value. Pad the space up to a multiple of 16

83431

- bytes (the maximum alignment required for anything under

83432

- the SYSV ABI). */

83433

- struct_copy_size += ((*ptr)->size + 15) & ~0xF;

83434

- /* Fall through (allocate space for the pointer). */

83435

-

83436

- case FFI_TYPE_POINTER:

83437

- case FFI_TYPE_INT:

83438

- case FFI_TYPE_UINT32:

83439

- case FFI_TYPE_SINT32:

83440

- case FFI_TYPE_UINT16:

83441

- case FFI_TYPE_SINT16:

83442

- case FFI_TYPE_UINT8:

83443

- case FFI_TYPE_SINT8:

83444

- /* Everything else is passed as a 4-byte word in a GPR, either

83445

- the object itself or a pointer to it. */

83446

- intarg_count++;

83447

- break;

83448

- default:

83449

- FFI_ASSERT (0);

83450

- }

83451

- }

83452

- else

83453

- for (ptr = cif->arg_types, i = cif->nargs; i > 0; i--, ptr++)

83454

- {

83455

- switch ((*ptr)->type)

83456

- {

83457

-#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

83458

- case FFI_TYPE_LONGDOUBLE:

83459

- if (cif->abi == FFI_LINUX_SOFT_FLOAT)

83460

- intarg_count += 4;

83461

- else

83462

- {

83463

- fparg_count += 2;

83464

- intarg_count += 2;

83465

- }

83466

- break;

83467

-#endif

83468

- case FFI_TYPE_FLOAT:

83469

- case FFI_TYPE_DOUBLE:

83470

- fparg_count++;

83471

- intarg_count++;

83472

- break;

83473

-

83474

- case FFI_TYPE_STRUCT:

83475

- intarg_count += ((*ptr)->size + 7) / 8;

83476

- break;

83477

-

83478

- case FFI_TYPE_POINTER:

83479

- case FFI_TYPE_UINT64:

83480

- case FFI_TYPE_SINT64:

83481

- case FFI_TYPE_INT:

83482

- case FFI_TYPE_UINT32:

83483

- case FFI_TYPE_SINT32:

83484

- case FFI_TYPE_UINT16:

83485

- case FFI_TYPE_SINT16:

83486

- case FFI_TYPE_UINT8:

83487

- case FFI_TYPE_SINT8:

83488

- /* Everything else is passed as a 8-byte word in a GPR, either

83489

- the object itself or a pointer to it. */

83490

- intarg_count++;

83491

- break;

83492

- default:

83493

- FFI_ASSERT (0);

83494

- }

83495

- }

83496

-

83497

-#ifndef __NO_FPRS__

83498

- if (fparg_count != 0)

83499

- flags |= FLAG_FP_ARGUMENTS;

83500

-#endif

83501

- if (intarg_count > 4)

83502

- flags |= FLAG_4_GPR_ARGUMENTS;

83503

- if (struct_copy_size != 0)

83504

- flags |= FLAG_ARG_NEEDS_COPY;

83505

-

83506

- if (cif->abi != FFI_LINUX64)

83507

- {

83508

-#ifndef __NO_FPRS__

83509

- /* Space for the FPR registers, if needed. */

83510

- if (fparg_count != 0)

83511

- bytes += NUM_FPR_ARG_REGISTERS * sizeof (double);

83512

-#endif

83513

-

83514

- /* Stack space. */

83515

- if (intarg_count > NUM_GPR_ARG_REGISTERS)

83516

- bytes += (intarg_count - NUM_GPR_ARG_REGISTERS) * sizeof (int);

83517

-#ifndef __NO_FPRS__

83518

- if (fparg_count > NUM_FPR_ARG_REGISTERS)

83519

- bytes += (fparg_count - NUM_FPR_ARG_REGISTERS) * sizeof (double);

83520

-#endif

83521

- }

83522

- else

83523

- {

83524

-#ifndef __NO_FPRS__

83525

- /* Space for the FPR registers, if needed. */

83526

- if (fparg_count != 0)

83527

- bytes += NUM_FPR_ARG_REGISTERS64 * sizeof (double);

83528

-#endif

83529

-

83530

- /* Stack space. */

83531

- if (intarg_count > NUM_GPR_ARG_REGISTERS64)

83532

- bytes += (intarg_count - NUM_GPR_ARG_REGISTERS64) * sizeof (long);

83533

- }

83534

-

83535

- /* The stack space allocated needs to be a multiple of 16 bytes. */

83536

- bytes = (bytes + 15) & ~0xF;

83537

-

83538

- /* Add in the space for the copied structures. */

83539

- bytes += struct_copy_size;

83540

-

83541

- cif->flags = flags;

83542

- cif->bytes = bytes;

83543

-

83544

- return FFI_OK;

83545

}

83546

83547

-extern void ffi_call_SYSV(extended_cif *, unsigned, unsigned, unsigned *,

83548

- void (*fn)(void));

83549

-extern void FFI_HIDDEN ffi_call_LINUX64(extended_cif *, unsigned long,

83550

- unsigned long, unsigned long *,

83551

- void (*fn)(void));

83552

-

83553

void

83554

ffi_call(ffi_cif *cif, void (*fn)(void), void *rvalue, void **avalue)

83555

{

83556

- /*

83557

- * The final SYSV ABI says that structures smaller or equal 8 bytes

83558

- * are returned in r3/r4. The FFI_GCC_SYSV ABI instead returns them

83559

- * in memory.

83560

- *

83561

- * Just to keep things simple for the assembly code, we will always

83562

- * bounce-buffer struct return values less than or equal to 8 bytes.

83563

- * This allows the ASM to handle SYSV small structures by directly

83564

- * writing r3 and r4 to memory without worrying about struct size.

83565

- */

83566

- unsigned int smst_buffer[2];

83567

+ /* The final SYSV ABI says that structures smaller or equal 8 bytes

83568

+ are returned in r3/r4. A draft ABI used by linux instead returns

83569

+ them in memory.

83570

+

83571

+ We bounce-buffer SYSV small struct return values so that sysv.S

83572

+ can write r3 and r4 to memory without worrying about struct size.

83573

+

83574

+ For ELFv2 ABI, use a bounce buffer for homogeneous structs too,

83575

+ for similar reasons. */

83576

+ unsigned long smst_buffer[8];

83577

extended_cif ecif;

83578

- unsigned int rsize = 0;

83579

83580

ecif.cif = cif;

83581

ecif.avalue = avalue;

83582

83583

- /* Ensure that we have a valid struct return value */

83584

ecif.rvalue = rvalue;

83585

- if (cif->rtype->type == FFI_TYPE_STRUCT) {

83586

- rsize = cif->rtype->size;

83587

- if (rsize <= 8)

83588

- ecif.rvalue = smst_buffer;

83589

- else if (!rvalue)

83590

- ecif.rvalue = alloca(rsize);

83591

- }

83592

+ if ((cif->flags & FLAG_RETURNS_SMST) != 0)

83593

+ ecif.rvalue = smst_buffer;

83594

+ /* Ensure that we have a valid struct return value.

83595

+ FIXME: Isn't this just papering over a user problem? */

83596

+ else if (!rvalue && cif->rtype->type == FFI_TYPE_STRUCT)

83597

+ ecif.rvalue = alloca (cif->rtype->size);

83598

83599

- switch (cif->abi)

83600

- {

83601

-#ifndef POWERPC64

83602

-# ifndef __NO_FPRS__

83603

- case FFI_SYSV:

83604

- case FFI_GCC_SYSV:

83605

- case FFI_LINUX:

83606

-# endif

83607

- case FFI_LINUX_SOFT_FLOAT:

83608

- ffi_call_SYSV (&ecif, -cif->bytes, cif->flags, ecif.rvalue, fn);

83609

- break;

83610

+#ifdef POWERPC64

83611

+ ffi_call_LINUX64 (&ecif, -(long) cif->bytes, cif->flags, ecif.rvalue, fn);

83612

#else

83613

- case FFI_LINUX64:

83614

- ffi_call_LINUX64 (&ecif, -(long) cif->bytes, cif->flags, ecif.rvalue, fn);

83615

- break;

83616

+ ffi_call_SYSV (&ecif, -cif->bytes, cif->flags, ecif.rvalue, fn);

83617

#endif

83618

- default:

83619

- FFI_ASSERT (0);

83620

- break;

83621

- }

83622

83623

/* Check for a bounce-buffered return value */

83624

if (rvalue && ecif.rvalue == smst_buffer)

83625

- memcpy(rvalue, smst_buffer, rsize);

83626

+ {

83627

+ unsigned int rsize = cif->rtype->size;

83628

+#ifndef __LITTLE_ENDIAN__

83629

+ /* The SYSV ABI returns a structure of up to 4 bytes in size

83630

+ left-padded in r3. */

83631

+# ifndef POWERPC64

83632

+ if (rsize <= 4)

83633

+ memcpy (rvalue, (char *) smst_buffer + 4 - rsize, rsize);

83634

+ else

83635

+# endif

83636

+ /* The SYSV ABI returns a structure of up to 8 bytes in size

83637

+ left-padded in r3/r4, and the ELFv2 ABI similarly returns a

83638

+ structure of up to 8 bytes in size left-padded in r3. */

83639

+ if (rsize <= 8)

83640

+ memcpy (rvalue, (char *) smst_buffer + 8 - rsize, rsize);

83641

+ else

83642

+#endif

83643

+ memcpy (rvalue, smst_buffer, rsize);

83644

+ }

83645

}

83646

83647

83648

-#ifndef POWERPC64

83649

-#define MIN_CACHE_LINE_SIZE 8

83650

-

83651

-static void

83652

-flush_icache (char *wraddr, char *xaddr, int size)

83653

-{

83654

- int i;

83655

- for (i = 0; i < size; i += MIN_CACHE_LINE_SIZE)

83656

- __asm__ volatile ("icbi 0,%0;" "dcbf 0,%1;"

83657

- : : "r" (xaddr + i), "r" (wraddr + i) : "memory");

83658

- __asm__ volatile ("icbi 0,%0;" "dcbf 0,%1;" "sync;" "isync;"

83659

- : : "r"(xaddr + size - 1), "r"(wraddr + size - 1)

83660

- : "memory");

83661

-}

83662

-#endif

83663

-

83664

ffi_status

83665

ffi_prep_closure_loc (ffi_closure *closure,

83666

ffi_cif *cif,

83667

@@ -995,487 +134,8 @@

83668

void *codeloc)

83669

{

83670

#ifdef POWERPC64

83671

- void **tramp = (void **) &closure->tramp[0];

83672

-

83673

- if (cif->abi != FFI_LINUX64)

83674

- return FFI_BAD_ABI;

83675

- /* Copy function address and TOC from ffi_closure_LINUX64. */

83676

- memcpy (tramp, (char *) ffi_closure_LINUX64, 16);

83677

- tramp[2] = codeloc;

83678

+ return ffi_prep_closure_loc_linux64 (closure, cif, fun, user_data, codeloc);

83679

#else

83680

- unsigned int *tramp;

83681

-

83682

- if (! (cif->abi == FFI_GCC_SYSV

83683

- || cif->abi == FFI_SYSV

83684

- || cif->abi == FFI_LINUX

83685

- || cif->abi == FFI_LINUX_SOFT_FLOAT))

83686

- return FFI_BAD_ABI;

83687

-

83688

- tramp = (unsigned int *) &closure->tramp[0];

83689

- tramp[0] = 0x7c0802a6; /* mflr r0 */

83690

- tramp[1] = 0x4800000d; /* bl 10 <trampoline_initial+0x10> */

83691

- tramp[4] = 0x7d6802a6; /* mflr r11 */

83692

- tramp[5] = 0x7c0803a6; /* mtlr r0 */

83693

- tramp[6] = 0x800b0000; /* lwz r0,0(r11) */

83694

- tramp[7] = 0x816b0004; /* lwz r11,4(r11) */

83695

- tramp[8] = 0x7c0903a6; /* mtctr r0 */

83696

- tramp[9] = 0x4e800420; /* bctr */

83697

- *(void **) &tramp[2] = (void *) ffi_closure_SYSV; /* function */

83698

- *(void **) &tramp[3] = codeloc; /* context */

83699

-

83700

- /* Flush the icache. */

83701

- flush_icache ((char *)tramp, (char *)codeloc, FFI_TRAMPOLINE_SIZE);

83702

+ return ffi_prep_closure_loc_sysv (closure, cif, fun, user_data, codeloc);

83703

#endif

83704

-

83705

- closure->cif = cif;

83706

- closure->fun = fun;

83707

- closure->user_data = user_data;

83708

-

83709

- return FFI_OK;

83710

}

83711

-

83712

-typedef union

83713

-{

83714

- float f;

83715

- double d;

83716

-} ffi_dblfl;

83717

-

83718

-int ffi_closure_helper_SYSV (ffi_closure *, void *, unsigned long *,

83719

- ffi_dblfl *, unsigned long *);

83720

-

83721

-/* Basically the trampoline invokes ffi_closure_SYSV, and on

83722

- * entry, r11 holds the address of the closure.

83723

- * After storing the registers that could possibly contain

83724

- * parameters to be passed into the stack frame and setting

83725

- * up space for a return value, ffi_closure_SYSV invokes the

83726

- * following helper function to do most of the work

83727

- */

83728

-

83729

-int

83730

-ffi_closure_helper_SYSV (ffi_closure *closure, void *rvalue,

83731

- unsigned long *pgr, ffi_dblfl *pfr,

83732

- unsigned long *pst)

83733

-{

83734

- /* rvalue is the pointer to space for return value in closure assembly */

83735

- /* pgr is the pointer to where r3-r10 are stored in ffi_closure_SYSV */

83736

- /* pfr is the pointer to where f1-f8 are stored in ffi_closure_SYSV */

83737

- /* pst is the pointer to outgoing parameter stack in original caller */

83738

-

83739

- void ** avalue;

83740

- ffi_type ** arg_types;

83741

- long i, avn;

83742

-#ifndef __NO_FPRS__

83743

- long nf = 0; /* number of floating registers already used */

83744

-#endif

83745

- long ng = 0; /* number of general registers already used */

83746

-

83747

- ffi_cif *cif = closure->cif;

83748

- unsigned size = cif->rtype->size;

83749

- unsigned short rtypenum = cif->rtype->type;

83750

-

83751

- avalue = alloca (cif->nargs * sizeof (void *));

83752

-

83753

- /* First translate for softfloat/nonlinux */

83754

- if (cif->abi == FFI_LINUX_SOFT_FLOAT) {

83755

- if (rtypenum == FFI_TYPE_FLOAT)

83756

- rtypenum = FFI_TYPE_UINT32;

83757

- if (rtypenum == FFI_TYPE_DOUBLE)

83758

- rtypenum = FFI_TYPE_UINT64;

83759

- if (rtypenum == FFI_TYPE_LONGDOUBLE)

83760

- rtypenum = FFI_TYPE_UINT128;

83761

- } else if (cif->abi != FFI_LINUX && cif->abi != FFI_LINUX64) {

83762

-#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

83763

- if (rtypenum == FFI_TYPE_LONGDOUBLE)

83764

- rtypenum = FFI_TYPE_STRUCT;

83765

-#endif

83766

- }

83767

-

83768

-

83769

- /* Copy the caller's structure return value address so that the closure

83770

- returns the data directly to the caller.

83771

- For FFI_SYSV the result is passed in r3/r4 if the struct size is less

83772

- or equal 8 bytes. */

83773

- if (rtypenum == FFI_TYPE_STRUCT && ((cif->abi != FFI_SYSV) || (size > 8))) {

83774

- rvalue = (void *) *pgr;

83775

- ng++;

83776

- pgr++;

83777

- }

83778

-

83779

- i = 0;

83780

- avn = cif->nargs;

83781

- arg_types = cif->arg_types;

83782

-

83783

- /* Grab the addresses of the arguments from the stack frame. */

83784

- while (i < avn) {

83785

- unsigned short typenum = arg_types[i]->type;

83786

-

83787

- /* We may need to handle some values depending on ABI */

83788

- if (cif->abi == FFI_LINUX_SOFT_FLOAT) {

83789

- if (typenum == FFI_TYPE_FLOAT)

83790

- typenum = FFI_TYPE_UINT32;

83791

- if (typenum == FFI_TYPE_DOUBLE)

83792

- typenum = FFI_TYPE_UINT64;

83793

- if (typenum == FFI_TYPE_LONGDOUBLE)

83794

- typenum = FFI_TYPE_UINT128;

83795

- } else if (cif->abi != FFI_LINUX && cif->abi != FFI_LINUX64) {

83796

-#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

83797

- if (typenum == FFI_TYPE_LONGDOUBLE)

83798

- typenum = FFI_TYPE_STRUCT;

83799

-#endif

83800

- }

83801

-

83802

- switch (typenum) {

83803

-#ifndef __NO_FPRS__

83804

- case FFI_TYPE_FLOAT:

83805

- /* unfortunately float values are stored as doubles

83806

- * in the ffi_closure_SYSV code (since we don't check

83807

- * the type in that routine).

83808

- */

83809

-

83810

- /* there are 8 64bit floating point registers */

83811

-

83812

- if (nf < 8)

83813

- {

83814

- double temp = pfr->d;

83815

- pfr->f = (float) temp;

83816

- avalue[i] = pfr;

83817

- nf++;

83818

- pfr++;

83819

- }

83820

- else

83821

- {

83822

- /* FIXME? here we are really changing the values

83823

- * stored in the original calling routines outgoing

83824

- * parameter stack. This is probably a really

83825

- * naughty thing to do but...

83826

- */

83827

- avalue[i] = pst;

83828

- pst += 1;

83829

- }

83830

- break;

83831

-

83832

- case FFI_TYPE_DOUBLE:

83833

- /* On the outgoing stack all values are aligned to 8 */

83834

- /* there are 8 64bit floating point registers */

83835

-

83836

- if (nf < 8)

83837

- {

83838

- avalue[i] = pfr;

83839

- nf++;

83840

- pfr++;

83841

- }

83842

- else

83843

- {

83844

- if (((long) pst) & 4)

83845

- pst++;

83846

- avalue[i] = pst;

83847

- pst += 2;

83848

- }

83849

- break;

83850

-

83851

-#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

83852

- case FFI_TYPE_LONGDOUBLE:

83853

- if (nf < 7)

83854

- {

83855

- avalue[i] = pfr;

83856

- pfr += 2;

83857

- nf += 2;

83858

- }

83859

- else

83860

- {

83861

- if (((long) pst) & 4)

83862

- pst++;

83863

- avalue[i] = pst;

83864

- pst += 4;

83865

- nf = 8;

83866

- }

83867

- break;

83868

-#endif

83869

-#endif /* have FPRS */

83870

-

83871

- case FFI_TYPE_UINT128:

83872

- /*

83873

- * Test if for the whole long double, 4 gprs are available.

83874

- * otherwise the stuff ends up on the stack.

83875

- */

83876

- if (ng < 5) {

83877

- avalue[i] = pgr;

83878

- pgr += 4;

83879

- ng += 4;

83880

- } else {

83881

- avalue[i] = pst;

83882

- pst += 4;

83883

- ng = 8+4;

83884

- }

83885

- break;

83886

-

83887

- case FFI_TYPE_SINT8:

83888

- case FFI_TYPE_UINT8:

83889

-#ifndef __LITTLE_ENDIAN__

83890

- /* there are 8 gpr registers used to pass values */

83891

- if (ng < 8)

83892

- {

83893

- avalue[i] = (char *) pgr + 3;

83894

- ng++;

83895

- pgr++;

83896

- }

83897

- else

83898

- {

83899

- avalue[i] = (char *) pst + 3;

83900

- pst++;

83901

- }

83902

- break;

83903

-#endif

83904

- case FFI_TYPE_SINT16:

83905

- case FFI_TYPE_UINT16:

83906

-#ifndef __LITTLE_ENDIAN__

83907

- /* there are 8 gpr registers used to pass values */

83908

- if (ng < 8)

83909

- {

83910

- avalue[i] = (char *) pgr + 2;

83911

- ng++;

83912

- pgr++;

83913

- }

83914

- else

83915

- {

83916

- avalue[i] = (char *) pst + 2;

83917

- pst++;

83918

- }

83919

- break;

83920

-#endif

83921

- case FFI_TYPE_SINT32:

83922

- case FFI_TYPE_UINT32:

83923

- case FFI_TYPE_POINTER:

83924

- /* there are 8 gpr registers used to pass values */

83925

- if (ng < 8)

83926

- {

83927

- avalue[i] = pgr;

83928

- ng++;

83929

- pgr++;

83930

- }

83931

- else

83932

- {

83933

- avalue[i] = pst;

83934

- pst++;

83935

- }

83936

- break;

83937

-

83938

- case FFI_TYPE_STRUCT:

83939

- /* Structs are passed by reference. The address will appear in a

83940

- gpr if it is one of the first 8 arguments. */

83941

- if (ng < 8)

83942

- {

83943

- avalue[i] = (void *) *pgr;

83944

- ng++;

83945

- pgr++;

83946

- }

83947

- else

83948

- {

83949

- avalue[i] = (void *) *pst;

83950

- pst++;

83951

- }

83952

- break;

83953

-

83954

- case FFI_TYPE_SINT64:

83955

- case FFI_TYPE_UINT64:

83956

- /* passing long long ints are complex, they must

83957

- * be passed in suitable register pairs such as

83958

- * (r3,r4) or (r5,r6) or (r6,r7), or (r7,r8) or (r9,r10)

83959

- * and if the entire pair aren't available then the outgoing

83960

- * parameter stack is used for both but an alignment of 8

83961

- * must will be kept. So we must either look in pgr

83962

- * or pst to find the correct address for this type

83963

- * of parameter.

83964

- */

83965

- if (ng < 7)

83966

- {

83967

- if (ng & 0x01)

83968

- {

83969

- /* skip r4, r6, r8 as starting points */

83970

- ng++;

83971

- pgr++;

83972

- }

83973

- avalue[i] = pgr;

83974

- ng += 2;

83975

- pgr += 2;

83976

- }

83977

- else

83978

- {

83979

- if (((long) pst) & 4)

83980

- pst++;

83981

- avalue[i] = pst;

83982

- pst += 2;

83983

- ng = 8;

83984

- }

83985

- break;

83986

-

83987

- default:

83988

- FFI_ASSERT (0);

83989

- }

83990

-

83991

- i++;

83992

- }

83993

-

83994

-

83995

- (closure->fun) (cif, rvalue, avalue, closure->user_data);

83996

-

83997

- /* Tell ffi_closure_SYSV how to perform return type promotions.

83998

- Because the FFI_SYSV ABI returns the structures <= 8 bytes in r3/r4

83999

- we have to tell ffi_closure_SYSV how to treat them. We combine the base

84000

- type FFI_SYSV_TYPE_SMALL_STRUCT - 1 with the size of the struct.

84001

- So a one byte struct gets the return type 16. Return type 1 to 15 are

84002

- already used and we never have a struct with size zero. That is the reason

84003

- for the subtraction of 1. See the comment in ffitarget.h about ordering.

84004

- */

84005

- if (cif->abi == FFI_SYSV && rtypenum == FFI_TYPE_STRUCT && size <= 8)

84006

- return (FFI_SYSV_TYPE_SMALL_STRUCT - 1) + size;

84007

- return rtypenum;

84008

-}

84009

-

84010

-int FFI_HIDDEN ffi_closure_helper_LINUX64 (ffi_closure *, void *,

84011

- unsigned long *, ffi_dblfl *);

84012

-

84013

-int FFI_HIDDEN

84014

-ffi_closure_helper_LINUX64 (ffi_closure *closure, void *rvalue,

84015

- unsigned long *pst, ffi_dblfl *pfr)

84016

-{

84017

- /* rvalue is the pointer to space for return value in closure assembly */

84018

- /* pst is the pointer to parameter save area

84019

- (r3-r10 are stored into its first 8 slots by ffi_closure_LINUX64) */

84020

- /* pfr is the pointer to where f1-f13 are stored in ffi_closure_LINUX64 */

84021

-

84022

- void **avalue;

84023

- ffi_type **arg_types;

84024

- long i, avn;

84025

- ffi_cif *cif;

84026

- ffi_dblfl *end_pfr = pfr + NUM_FPR_ARG_REGISTERS64;

84027

-

84028

- cif = closure->cif;

84029

- avalue = alloca (cif->nargs * sizeof (void *));

84030

-

84031

- /* Copy the caller's structure return value address so that the closure

84032

- returns the data directly to the caller. */

84033

- if (cif->rtype->type == FFI_TYPE_STRUCT)

84034

- {

84035

- rvalue = (void *) *pst;

84036

- pst++;

84037

- }

84038

-

84039

- i = 0;

84040

- avn = cif->nargs;

84041

- arg_types = cif->arg_types;

84042

-

84043

- /* Grab the addresses of the arguments from the stack frame. */

84044

- while (i < avn)

84045

- {

84046

- switch (arg_types[i]->type)

84047

- {

84048

- case FFI_TYPE_SINT8:

84049

- case FFI_TYPE_UINT8:

84050

-#ifndef __LITTLE_ENDIAN__

84051

- avalue[i] = (char *) pst + 7;

84052

- pst++;

84053

- break;

84054

-#endif

84055

- case FFI_TYPE_SINT16:

84056

- case FFI_TYPE_UINT16:

84057

-#ifndef __LITTLE_ENDIAN__

84058

- avalue[i] = (char *) pst + 6;

84059

- pst++;

84060

- break;

84061

-#endif

84062

- case FFI_TYPE_SINT32:

84063

- case FFI_TYPE_UINT32:

84064

-#ifndef __LITTLE_ENDIAN__

84065

- avalue[i] = (char *) pst + 4;

84066

- pst++;

84067

- break;

84068

-#endif

84069

- case FFI_TYPE_SINT64:

84070

- case FFI_TYPE_UINT64:

84071

- case FFI_TYPE_POINTER:

84072

- avalue[i] = pst;

84073

- pst++;

84074

- break;

84075

-

84076

- case FFI_TYPE_STRUCT:

84077

-#ifndef __LITTLE_ENDIAN__

84078

- /* Structures with size less than eight bytes are passed

84079

- left-padded. */

84080

- if (arg_types[i]->size < 8)

84081

- avalue[i] = (char *) pst + 8 - arg_types[i]->size;

84082

- else

84083

-#endif

84084

- avalue[i] = pst;

84085

- pst += (arg_types[i]->size + 7) / 8;

84086

- break;

84087

-

84088

- case FFI_TYPE_FLOAT:

84089

- /* unfortunately float values are stored as doubles

84090

- * in the ffi_closure_LINUX64 code (since we don't check

84091

- * the type in that routine).

84092

- */

84093

-

84094

- /* there are 13 64bit floating point registers */

84095

-

84096

- if (pfr < end_pfr)

84097

- {

84098

- double temp = pfr->d;

84099

- pfr->f = (float) temp;

84100

- avalue[i] = pfr;

84101

- pfr++;

84102

- }

84103

- else

84104

- avalue[i] = pst;

84105

- pst++;

84106

- break;

84107

-

84108

- case FFI_TYPE_DOUBLE:

84109

- /* On the outgoing stack all values are aligned to 8 */

84110

- /* there are 13 64bit floating point registers */

84111

-

84112

- if (pfr < end_pfr)

84113

- {

84114

- avalue[i] = pfr;

84115

- pfr++;

84116

- }

84117

- else

84118

- avalue[i] = pst;

84119

- pst++;

84120

- break;

84121

-

84122

-#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

84123

- case FFI_TYPE_LONGDOUBLE:

84124

- if (pfr + 1 < end_pfr)

84125

- {

84126

- avalue[i] = pfr;

84127

- pfr += 2;

84128

- }

84129

- else

84130

- {

84131

- if (pfr < end_pfr)

84132

- {

84133

- /* Passed partly in f13 and partly on the stack.

84134

- Move it all to the stack. */

84135

- *pst = *(unsigned long *) pfr;

84136

- pfr++;

84137

- }

84138

- avalue[i] = pst;

84139

- }

84140

- pst += 2;

84141

- break;

84142

-#endif

84143

-

84144

- default:

84145

- FFI_ASSERT (0);

84146

- }

84147

-

84148

- i++;

84149

- }

84150

-

84151

-

84152

- (closure->fun) (cif, rvalue, avalue, closure->user_data);

84153

-

84154

- /* Tell ffi_closure_LINUX64 how to perform return type promotions. */

84155

- return cif->rtype->type;

84156

-}

84157

Index: libffi/src/powerpc/sysv.S

84158

===================================================================

84159

--- a/src/libffi/src/powerpc/sysv.S (.../tags/gcc_4_8_2_release)

84160

+++ b/src/libffi/src/powerpc/sysv.S (.../branches/gcc-4_8-branch)

84161

@@ -30,7 +30,7 @@

84162

#include <ffi.h>

84163

#include <powerpc/asm.h>

84164

84165

-#ifndef __powerpc64__

84166

+#ifndef POWERPC64

84167

.globl ffi_prep_args_SYSV

84168

ENTRY(ffi_call_SYSV)

84169

.LFB1:

84170

@@ -213,8 +213,8 @@

84171

.uleb128 0x1c

84172

.align 2

84173

.LEFDE1:

84174

-#endif

84175

84176

#if defined __ELF__ && defined __linux__

84177

.section .note.GNU-stack,"",@progbits

84178

#endif

84179

+#endif

84180

Index: libffi/src/powerpc/linux64_closure.S

84181

===================================================================

84182

--- a/src/libffi/src/powerpc/linux64_closure.S (.../tags/gcc_4_8_2_release)

84183

+++ b/src/libffi/src/powerpc/linux64_closure.S (.../branches/gcc-4_8-branch)

84184

@@ -30,18 +30,25 @@

84185

84186

.file "linux64_closure.S"

84187

84188

-#ifdef __powerpc64__

84189

+#ifdef POWERPC64

84190

FFI_HIDDEN (ffi_closure_LINUX64)

84191

.globl ffi_closure_LINUX64

84192

+# if _CALL_ELF == 2

84193

+ .text

84194

+ffi_closure_LINUX64:

84195

+ addis %r2, %r12, .TOC.-ffi_closure_LINUX64@ha

84196

+ addi %r2, %r2, .TOC.-ffi_closure_LINUX64@l

84197

+ .localentry ffi_closure_LINUX64, . - ffi_closure_LINUX64

84198

+# else

84199

.section ".opd","aw"

84200

.align 3

84201

ffi_closure_LINUX64:

84202

-#ifdef _CALL_LINUX

84203

+# ifdef _CALL_LINUX

84204

.quad .L.ffi_closure_LINUX64,.TOC.@tocbase,0

84205

.type ffi_closure_LINUX64,@function

84206

.text

84207

.L.ffi_closure_LINUX64:

84208

-#else

84209

+# else

84210

FFI_HIDDEN (.ffi_closure_LINUX64)

84211

.globl .ffi_closure_LINUX64

84212

.quad .ffi_closure_LINUX64,.TOC.@tocbase,0

84213

@@ -49,61 +56,101 @@

84214

.type .ffi_closure_LINUX64,@function

84215

.text

84216

.ffi_closure_LINUX64:

84217

-#endif

84218

+# endif

84219

+# endif

84220

+

84221

+# if _CALL_ELF == 2

84222

+# 32 byte special reg save area + 64 byte parm save area

84223

+# + 64 byte retval area + 13*8 fpr save area + round to 16

84224

+# define STACKFRAME 272

84225

+# define PARMSAVE 32

84226

+# define RETVAL PARMSAVE+64

84227

+# else

84228

+# 48 bytes special reg save area + 64 bytes parm save area

84229

+# + 16 bytes retval area + 13*8 bytes fpr save area + round to 16

84230

+# define STACKFRAME 240

84231

+# define PARMSAVE 48

84232

+# define RETVAL PARMSAVE+64

84233

+# endif

84234

+

84235

.LFB1:

84236

- # save general regs into parm save area

84237

- std %r3, 48(%r1)

84238

- std %r4, 56(%r1)

84239

- std %r5, 64(%r1)

84240

- std %r6, 72(%r1)

84241

+# if _CALL_ELF == 2

84242

+ ld %r12, FFI_TRAMPOLINE_SIZE(%r11) # closure->cif

84243

mflr %r0

84244

+ lwz %r12, 28(%r12) # cif->flags

84245

+ mtcrf 0x40, %r12

84246

+ addi %r12, %r1, PARMSAVE

84247

+ bt 7, .Lparmsave

84248

+ # Our caller has not allocated a parameter save area.

84249

+ # We need to allocate one here and use it to pass gprs to

84250

+ # ffi_closure_helper_LINUX64.

84251

+ addi %r12, %r1, -STACKFRAME+PARMSAVE

84252

+.Lparmsave:

84253

+ std %r0, 16(%r1)

84254

+ # Save general regs into parm save area

84255

+ std %r3, 0(%r12)

84256

+ std %r4, 8(%r12)

84257

+ std %r5, 16(%r12)

84258

+ std %r6, 24(%r12)

84259

+ std %r7, 32(%r12)

84260

+ std %r8, 40(%r12)

84261

+ std %r9, 48(%r12)

84262

+ std %r10, 56(%r12)

84263

84264

- std %r7, 80(%r1)

84265

- std %r8, 88(%r1)

84266

- std %r9, 96(%r1)

84267

- std %r10, 104(%r1)

84268

+ # load up the pointer to the parm save area

84269

+ mr %r5, %r12

84270

+# else

84271

+ mflr %r0

84272

+ # Save general regs into parm save area

84273

+ # This is the parameter save area set up by our caller.

84274

+ std %r3, PARMSAVE+0(%r1)

84275

+ std %r4, PARMSAVE+8(%r1)

84276

+ std %r5, PARMSAVE+16(%r1)

84277

+ std %r6, PARMSAVE+24(%r1)

84278

+ std %r7, PARMSAVE+32(%r1)

84279

+ std %r8, PARMSAVE+40(%r1)

84280

+ std %r9, PARMSAVE+48(%r1)

84281

+ std %r10, PARMSAVE+56(%r1)

84282

+

84283

std %r0, 16(%r1)

84284

84285

- # mandatory 48 bytes special reg save area + 64 bytes parm save area

84286

- # + 16 bytes retval area + 13*8 bytes fpr save area + round to 16

84287

- stdu %r1, -240(%r1)

84288

-.LCFI0:

84289

+ # load up the pointer to the parm save area

84290

+ addi %r5, %r1, PARMSAVE

84291

+# endif

84292

84293

# next save fpr 1 to fpr 13

84294

- stfd %f1, 128+(0*8)(%r1)

84295

- stfd %f2, 128+(1*8)(%r1)

84296

- stfd %f3, 128+(2*8)(%r1)

84297

- stfd %f4, 128+(3*8)(%r1)

84298

- stfd %f5, 128+(4*8)(%r1)

84299

- stfd %f6, 128+(5*8)(%r1)

84300

- stfd %f7, 128+(6*8)(%r1)

84301

- stfd %f8, 128+(7*8)(%r1)

84302

- stfd %f9, 128+(8*8)(%r1)

84303

- stfd %f10, 128+(9*8)(%r1)

84304

- stfd %f11, 128+(10*8)(%r1)

84305

- stfd %f12, 128+(11*8)(%r1)

84306

- stfd %f13, 128+(12*8)(%r1)

84307

+ stfd %f1, -104+(0*8)(%r1)

84308

+ stfd %f2, -104+(1*8)(%r1)

84309

+ stfd %f3, -104+(2*8)(%r1)

84310

+ stfd %f4, -104+(3*8)(%r1)

84311

+ stfd %f5, -104+(4*8)(%r1)

84312

+ stfd %f6, -104+(5*8)(%r1)

84313

+ stfd %f7, -104+(6*8)(%r1)

84314

+ stfd %f8, -104+(7*8)(%r1)

84315

+ stfd %f9, -104+(8*8)(%r1)

84316

+ stfd %f10, -104+(9*8)(%r1)

84317

+ stfd %f11, -104+(10*8)(%r1)

84318

+ stfd %f12, -104+(11*8)(%r1)

84319

+ stfd %f13, -104+(12*8)(%r1)

84320

84321

- # set up registers for the routine that actually does the work

84322

- # get the context pointer from the trampoline

84323

- mr %r3, %r11

84324

+ # load up the pointer to the saved fpr registers */

84325

+ addi %r6, %r1, -104

84326

84327

- # now load up the pointer to the result storage

84328

- addi %r4, %r1, 112

84329

+ # load up the pointer to the result storage

84330

+ addi %r4, %r1, -STACKFRAME+RETVAL

84331

84332

- # now load up the pointer to the parameter save area

84333

- # in the previous frame

84334

- addi %r5, %r1, 240 + 48

84335

+ stdu %r1, -STACKFRAME(%r1)

84336

+.LCFI0:

84337

84338

- # now load up the pointer to the saved fpr registers */

84339

- addi %r6, %r1, 128

84340

+ # get the context pointer from the trampoline

84341

+ mr %r3, %r11

84342

84343

# make the call

84344

-#ifdef _CALL_LINUX

84345

+# if defined _CALL_LINUX || _CALL_ELF == 2

84346

bl ffi_closure_helper_LINUX64

84347

-#else

84348

+# else

84349

bl .ffi_closure_helper_LINUX64

84350

-#endif

84351

+# endif

84352

.Lret:

84353

84354

# now r3 contains the return type

84355

@@ -112,10 +159,12 @@

84356

84357

# look up the proper starting point in table

84358

# by using return type as offset

84359

+ ld %r0, STACKFRAME+16(%r1)

84360

+ cmpldi %r3, FFI_V2_TYPE_SMALL_STRUCT

84361

+ bge .Lsmall

84362

mflr %r4 # move address of .Lret to r4

84363

sldi %r3, %r3, 4 # now multiply return type by 16

84364

addi %r4, %r4, .Lret_type0 - .Lret

84365

- ld %r0, 240+16(%r1)

84366

add %r3, %r3, %r4 # add contents of table to table address

84367

mtctr %r3

84368

bctr # jump to it

84369

@@ -128,117 +177,175 @@

84370

.Lret_type0:

84371

# case FFI_TYPE_VOID

84372

mtlr %r0

84373

- addi %r1, %r1, 240

84374

+ addi %r1, %r1, STACKFRAME

84375

blr

84376

nop

84377

# case FFI_TYPE_INT

84378

-#ifdef __LITTLE_ENDIAN__

84379

- lwa %r3, 112+0(%r1)

84380

-#else

84381

- lwa %r3, 112+4(%r1)

84382

-#endif

84383

+# ifdef __LITTLE_ENDIAN__

84384

+ lwa %r3, RETVAL+0(%r1)

84385

+# else

84386

+ lwa %r3, RETVAL+4(%r1)

84387

+# endif

84388

mtlr %r0

84389

- addi %r1, %r1, 240

84390

+ addi %r1, %r1, STACKFRAME

84391

blr

84392

# case FFI_TYPE_FLOAT

84393

- lfs %f1, 112+0(%r1)

84394

+ lfs %f1, RETVAL+0(%r1)

84395

mtlr %r0

84396

- addi %r1, %r1, 240

84397

+ addi %r1, %r1, STACKFRAME

84398

blr

84399

# case FFI_TYPE_DOUBLE

84400

- lfd %f1, 112+0(%r1)

84401

+ lfd %f1, RETVAL+0(%r1)

84402

mtlr %r0

84403

- addi %r1, %r1, 240

84404

+ addi %r1, %r1, STACKFRAME

84405

blr

84406

# case FFI_TYPE_LONGDOUBLE

84407

- lfd %f1, 112+0(%r1)

84408

+ lfd %f1, RETVAL+0(%r1)

84409

mtlr %r0

84410

- lfd %f2, 112+8(%r1)

84411

+ lfd %f2, RETVAL+8(%r1)

84412

b .Lfinish

84413

# case FFI_TYPE_UINT8

84414

-#ifdef __LITTLE_ENDIAN__

84415

- lbz %r3, 112+0(%r1)

84416

-#else

84417

- lbz %r3, 112+7(%r1)

84418

-#endif

84419

+# ifdef __LITTLE_ENDIAN__

84420

+ lbz %r3, RETVAL+0(%r1)

84421

+# else

84422

+ lbz %r3, RETVAL+7(%r1)

84423

+# endif

84424

mtlr %r0

84425

- addi %r1, %r1, 240

84426

+ addi %r1, %r1, STACKFRAME

84427

blr

84428

# case FFI_TYPE_SINT8

84429

-#ifdef __LITTLE_ENDIAN__

84430

- lbz %r3, 112+0(%r1)

84431

-#else

84432

- lbz %r3, 112+7(%r1)

84433

-#endif

84434

+# ifdef __LITTLE_ENDIAN__

84435

+ lbz %r3, RETVAL+0(%r1)

84436

+# else

84437

+ lbz %r3, RETVAL+7(%r1)

84438

+# endif

84439

extsb %r3,%r3

84440

mtlr %r0

84441

b .Lfinish

84442

# case FFI_TYPE_UINT16

84443

-#ifdef __LITTLE_ENDIAN__

84444

- lhz %r3, 112+0(%r1)

84445

-#else

84446

- lhz %r3, 112+6(%r1)

84447

-#endif

84448

+# ifdef __LITTLE_ENDIAN__

84449

+ lhz %r3, RETVAL+0(%r1)

84450

+# else

84451

+ lhz %r3, RETVAL+6(%r1)

84452

+# endif

84453

mtlr %r0

84454

.Lfinish:

84455

- addi %r1, %r1, 240

84456

+ addi %r1, %r1, STACKFRAME

84457

blr

84458

# case FFI_TYPE_SINT16

84459

-#ifdef __LITTLE_ENDIAN__

84460

- lha %r3, 112+0(%r1)

84461

-#else

84462

- lha %r3, 112+6(%r1)

84463

-#endif

84464

+# ifdef __LITTLE_ENDIAN__

84465

+ lha %r3, RETVAL+0(%r1)

84466

+# else

84467

+ lha %r3, RETVAL+6(%r1)

84468

+# endif

84469

mtlr %r0

84470

- addi %r1, %r1, 240

84471

+ addi %r1, %r1, STACKFRAME

84472

blr

84473

# case FFI_TYPE_UINT32

84474

-#ifdef __LITTLE_ENDIAN__

84475

- lwz %r3, 112+0(%r1)

84476

-#else

84477

- lwz %r3, 112+4(%r1)

84478

-#endif

84479

+# ifdef __LITTLE_ENDIAN__

84480

+ lwz %r3, RETVAL+0(%r1)

84481

+# else

84482

+ lwz %r3, RETVAL+4(%r1)

84483

+# endif

84484

mtlr %r0

84485

- addi %r1, %r1, 240

84486

+ addi %r1, %r1, STACKFRAME

84487

blr

84488

# case FFI_TYPE_SINT32

84489

-#ifdef __LITTLE_ENDIAN__

84490

- lwa %r3, 112+0(%r1)

84491

-#else

84492

- lwa %r3, 112+4(%r1)

84493

-#endif

84494

+# ifdef __LITTLE_ENDIAN__

84495

+ lwa %r3, RETVAL+0(%r1)

84496

+# else

84497

+ lwa %r3, RETVAL+4(%r1)

84498

+# endif

84499

mtlr %r0

84500

- addi %r1, %r1, 240

84501

+ addi %r1, %r1, STACKFRAME

84502

blr

84503

# case FFI_TYPE_UINT64

84504

- ld %r3, 112+0(%r1)

84505

+ ld %r3, RETVAL+0(%r1)

84506

mtlr %r0

84507

- addi %r1, %r1, 240

84508

+ addi %r1, %r1, STACKFRAME

84509

blr

84510

# case FFI_TYPE_SINT64

84511

- ld %r3, 112+0(%r1)

84512

+ ld %r3, RETVAL+0(%r1)

84513

mtlr %r0

84514

- addi %r1, %r1, 240

84515

+ addi %r1, %r1, STACKFRAME

84516

blr

84517

# case FFI_TYPE_STRUCT

84518

mtlr %r0

84519

- addi %r1, %r1, 240

84520

+ addi %r1, %r1, STACKFRAME

84521

blr

84522

nop

84523

# case FFI_TYPE_POINTER

84524

- ld %r3, 112+0(%r1)

84525

+ ld %r3, RETVAL+0(%r1)

84526

mtlr %r0

84527

- addi %r1, %r1, 240

84528

+ addi %r1, %r1, STACKFRAME

84529

blr

84530

-# esac

84531

+# case FFI_V2_TYPE_FLOAT_HOMOG

84532

+ lfs %f1, RETVAL+0(%r1)

84533

+ lfs %f2, RETVAL+4(%r1)

84534

+ lfs %f3, RETVAL+8(%r1)

84535

+ b .Lmorefloat

84536

+# case FFI_V2_TYPE_DOUBLE_HOMOG

84537

+ lfd %f1, RETVAL+0(%r1)

84538

+ lfd %f2, RETVAL+8(%r1)

84539

+ lfd %f3, RETVAL+16(%r1)

84540

+ lfd %f4, RETVAL+24(%r1)

84541

+ mtlr %r0

84542

+ lfd %f5, RETVAL+32(%r1)

84543

+ lfd %f6, RETVAL+40(%r1)

84544

+ lfd %f7, RETVAL+48(%r1)

84545

+ lfd %f8, RETVAL+56(%r1)

84546

+ addi %r1, %r1, STACKFRAME

84547

+ blr

84548

+.Lmorefloat:

84549

+ lfs %f4, RETVAL+12(%r1)

84550

+ mtlr %r0

84551

+ lfs %f5, RETVAL+16(%r1)

84552

+ lfs %f6, RETVAL+20(%r1)

84553

+ lfs %f7, RETVAL+24(%r1)

84554

+ lfs %f8, RETVAL+28(%r1)

84555

+ addi %r1, %r1, STACKFRAME

84556

+ blr

84557

+.Lsmall:

84558

+# ifdef __LITTLE_ENDIAN__

84559

+ ld %r3,RETVAL+0(%r1)

84560

+ mtlr %r0

84561

+ ld %r4,RETVAL+8(%r1)

84562

+ addi %r1, %r1, STACKFRAME

84563

+ blr

84564

+# else

84565

+ # A struct smaller than a dword is returned in the low bits of r3

84566

+ # ie. right justified. Larger structs are passed left justified

84567

+ # in r3 and r4. The return value area on the stack will have

84568

+ # the structs as they are usually stored in memory.

84569

+ cmpldi %r3, FFI_V2_TYPE_SMALL_STRUCT + 7 # size 8 bytes?

84570

+ neg %r5, %r3

84571

+ ld %r3,RETVAL+0(%r1)

84572

+ blt .Lsmalldown

84573

+ mtlr %r0

84574

+ ld %r4,RETVAL+8(%r1)

84575

+ addi %r1, %r1, STACKFRAME

84576

+ blr

84577

+.Lsmalldown:

84578

+ addi %r5, %r5, FFI_V2_TYPE_SMALL_STRUCT + 7

84579

+ mtlr %r0

84580

+ sldi %r5, %r5, 3

84581

+ addi %r1, %r1, STACKFRAME

84582

+ srd %r3, %r3, %r5

84583

+ blr

84584

+# endif

84585

+

84586

.LFE1:

84587

.long 0

84588

.byte 0,12,0,1,128,0,0,0

84589

-#ifdef _CALL_LINUX

84590

+# if _CALL_ELF == 2

84591

+ .size ffi_closure_LINUX64,.-ffi_closure_LINUX64

84592

+# else

84593

+# ifdef _CALL_LINUX

84594

.size ffi_closure_LINUX64,.-.L.ffi_closure_LINUX64

84595

-#else

84596

+# else

84597

.size .ffi_closure_LINUX64,.-.ffi_closure_LINUX64

84598

-#endif

84599

+# endif

84600

+# endif

84601

84602

.section .eh_frame,EH_FRAME_FLAGS,@progbits

84603

.Lframe1:

84604

@@ -267,14 +374,14 @@

84605

.byte 0x2 # DW_CFA_advance_loc1

84606

.byte .LCFI0-.LFB1

84607

.byte 0xe # DW_CFA_def_cfa_offset

84608

- .uleb128 240

84609

+ .uleb128 STACKFRAME

84610

.byte 0x11 # DW_CFA_offset_extended_sf

84611

.uleb128 0x41

84612

.sleb128 -2

84613

.align 3

84614

.LEFDE1:

84615

-#endif

84616

84617

-#if defined __ELF__ && defined __linux__

84618

+# if defined __ELF__ && defined __linux__

84619

.section .note.GNU-stack,"",@progbits

84620

+# endif

84621

#endif

84622

Index: libffi/src/powerpc/ffi_powerpc.h

84623

===================================================================

84624

--- a/src/libffi/src/powerpc/ffi_powerpc.h (.../tags/gcc_4_8_2_release)

84625

+++ b/src/libffi/src/powerpc/ffi_powerpc.h (.../branches/gcc-4_8-branch)

84626

@@ -0,0 +1,77 @@

84627

+/* -----------------------------------------------------------------------

84628

84629

84630

84631

84632

84633

84634

+

84635

+ PowerPC Foreign Function Interface

84636

+

84637

+ Permission is hereby granted, free of charge, to any person obtaining

84638

+ a copy of this software and associated documentation files (the

84639

+ ``Software''), to deal in the Software without restriction, including

84640

+ without limitation the rights to use, copy, modify, merge, publish,

84641

+ distribute, sublicense, and/or sell copies of the Software, and to

84642

+ permit persons to whom the Software is furnished to do so, subject to

84643

+ the following conditions:

84644

+

84645

+ The above copyright notice and this permission notice shall be included

84646

+ in all copies or substantial portions of the Software.

84647

+

84648

+ THE SOFTWARE IS PROVIDED ``AS IS'', WITHOUT WARRANTY OF ANY KIND, EXPRESS

84649

+ OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

84650

+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.

84651

+ IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR

84652

+ OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

84653

+ ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

84654

+ OTHER DEALINGS IN THE SOFTWARE.

84655

+ ----------------------------------------------------------------------- */

84656

+

84657

+enum {

84658

+ /* The assembly depends on these exact flags. */

84659

+ /* These go in cr7 */

84660

+ FLAG_RETURNS_SMST = 1 << (31-31), /* Used for FFI_SYSV small structs. */

84661

+ FLAG_RETURNS_NOTHING = 1 << (31-30),

84662

+ FLAG_RETURNS_FP = 1 << (31-29),

84663

+ FLAG_RETURNS_64BITS = 1 << (31-28),

84664

+

84665

+ /* This goes in cr6 */

84666

+ FLAG_RETURNS_128BITS = 1 << (31-27),

84667

+

84668

+ FLAG_COMPAT = 1 << (31- 8), /* Not used by assembly */

84669

+

84670

+ /* These go in cr1 */

84671

+ FLAG_ARG_NEEDS_COPY = 1 << (31- 7), /* Used by sysv code */

84672

+ FLAG_ARG_NEEDS_PSAVE = FLAG_ARG_NEEDS_COPY, /* Used by linux64 code */

84673

+ FLAG_FP_ARGUMENTS = 1 << (31- 6), /* cr1.eq; specified by ABI */

84674

+ FLAG_4_GPR_ARGUMENTS = 1 << (31- 5),

84675

+ FLAG_RETVAL_REFERENCE = 1 << (31- 4)

84676

+};

84677

+

84678

+typedef union

84679

+{

84680

+ float f;

84681

+ double d;

84682

+} ffi_dblfl;

84683

+

84684

+void FFI_HIDDEN ffi_closure_SYSV (void);

84685

+void FFI_HIDDEN ffi_call_SYSV(extended_cif *, unsigned, unsigned, unsigned *,

84686

+ void (*)(void));

84687

+

84688

+void FFI_HIDDEN ffi_prep_types_sysv (ffi_abi);

84689

+ffi_status FFI_HIDDEN ffi_prep_cif_sysv (ffi_cif *);

84690

+int FFI_HIDDEN ffi_closure_helper_SYSV (ffi_closure *, void *, unsigned long *,

84691

+ ffi_dblfl *, unsigned long *);

84692

+

84693

+void FFI_HIDDEN ffi_call_LINUX64(extended_cif *, unsigned long, unsigned long,

84694

+ unsigned long *, void (*)(void));

84695

+void FFI_HIDDEN ffi_closure_LINUX64 (void);

84696

+

84697

+void FFI_HIDDEN ffi_prep_types_linux64 (ffi_abi);

84698

+ffi_status FFI_HIDDEN ffi_prep_cif_linux64 (ffi_cif *);

84699

+ffi_status FFI_HIDDEN ffi_prep_cif_linux64_var (ffi_cif *, unsigned int,

84700

+ unsigned int);

84701

+void FFI_HIDDEN ffi_prep_args64 (extended_cif *, unsigned long *const);

84702

+int FFI_HIDDEN ffi_closure_helper_LINUX64 (ffi_closure *, void *,

84703

+ unsigned long *, ffi_dblfl *);

84704

Index: libffi/src/powerpc/ffi_sysv.c

84705

===================================================================

84706

--- a/src/libffi/src/powerpc/ffi_sysv.c (.../tags/gcc_4_8_2_release)

84707

+++ b/src/libffi/src/powerpc/ffi_sysv.c (.../branches/gcc-4_8-branch)

84708

@@ -0,0 +1,931 @@

84709

+/* -----------------------------------------------------------------------

84710

84711

84712

84713

84714

84715

84716

+

84717

+ PowerPC Foreign Function Interface

84718

+

84719

+ Permission is hereby granted, free of charge, to any person obtaining

84720

+ a copy of this software and associated documentation files (the

84721

+ ``Software''), to deal in the Software without restriction, including

84722

+ without limitation the rights to use, copy, modify, merge, publish,

84723

+ distribute, sublicense, and/or sell copies of the Software, and to

84724

+ permit persons to whom the Software is furnished to do so, subject to

84725

+ the following conditions:

84726

+

84727

+ The above copyright notice and this permission notice shall be included

84728

+ in all copies or substantial portions of the Software.

84729

+

84730

+ THE SOFTWARE IS PROVIDED ``AS IS'', WITHOUT WARRANTY OF ANY KIND, EXPRESS

84731

+ OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

84732

+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.

84733

+ IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR

84734

+ OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

84735

+ ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

84736

+ OTHER DEALINGS IN THE SOFTWARE.

84737

+ ----------------------------------------------------------------------- */

84738

+

84739

+#include "ffi.h"

84740

+

84741

+#ifndef POWERPC64

84742

+#include "ffi_common.h"

84743

+#include "ffi_powerpc.h"

84744

+

84745

+

84746

+/* About the SYSV ABI. */

84747

+#define ASM_NEEDS_REGISTERS 4

84748

+#define NUM_GPR_ARG_REGISTERS 8

84749

+#define NUM_FPR_ARG_REGISTERS 8

84750

+

84751

+

84752

+#if HAVE_LONG_DOUBLE_VARIANT && FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

84753

+/* Adjust size of ffi_type_longdouble. */

84754

+void FFI_HIDDEN

84755

+ffi_prep_types_sysv (ffi_abi abi)

84756

+{

84757

+ if ((abi & (FFI_SYSV | FFI_SYSV_LONG_DOUBLE_128)) == FFI_SYSV)

84758

+ {

84759

+ ffi_type_longdouble.size = 8;

84760

+ ffi_type_longdouble.alignment = 8;

84761

+ }

84762

+ else

84763

+ {

84764

+ ffi_type_longdouble.size = 16;

84765

+ ffi_type_longdouble.alignment = 16;

84766

+ }

84767

+}

84768

+#endif

84769

+

84770

+/* Transform long double, double and float to other types as per abi. */

84771

+static int

84772

+translate_float (int abi, int type)

84773

+{

84774

+#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

84775

+ if (type == FFI_TYPE_LONGDOUBLE

84776

+ && (abi & FFI_SYSV_LONG_DOUBLE_128) == 0)

84777

+ type = FFI_TYPE_DOUBLE;

84778

+#endif

84779

+ if ((abi & FFI_SYSV_SOFT_FLOAT) != 0)

84780

+ {

84781

+ if (type == FFI_TYPE_FLOAT)

84782

+ type = FFI_TYPE_UINT32;

84783

+ else if (type == FFI_TYPE_DOUBLE)

84784

+ type = FFI_TYPE_UINT64;

84785

+#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

84786

+ else if (type == FFI_TYPE_LONGDOUBLE)

84787

+ type = FFI_TYPE_UINT128;

84788

+ }

84789

+ else if ((abi & FFI_SYSV_IBM_LONG_DOUBLE) == 0)

84790

+ {

84791

+ if (type == FFI_TYPE_LONGDOUBLE)

84792

+ type = FFI_TYPE_STRUCT;

84793

+#endif

84794

+ }

84795

+ return type;

84796

+}

84797

+

84798

+/* Perform machine dependent cif processing */

84799

+static ffi_status

84800

+ffi_prep_cif_sysv_core (ffi_cif *cif)

84801

+{

84802

+ ffi_type **ptr;

84803

+ unsigned bytes;

84804

+ unsigned i, fparg_count = 0, intarg_count = 0;

84805

+ unsigned flags = cif->flags;

84806

+ unsigned struct_copy_size = 0;

84807

+ unsigned type = cif->rtype->type;

84808

+ unsigned size = cif->rtype->size;

84809

+

84810

+ /* The machine-independent calculation of cif->bytes doesn't work

84811

+ for us. Redo the calculation. */

84812

+

84813

+ /* Space for the frame pointer, callee's LR, and the asm's temp regs. */

84814

+ bytes = (2 + ASM_NEEDS_REGISTERS) * sizeof (int);

84815

+

84816

+ /* Space for the GPR registers. */

84817

+ bytes += NUM_GPR_ARG_REGISTERS * sizeof (int);

84818

+

84819

+ /* Return value handling. The rules for SYSV are as follows:

84820

+ - 32-bit (or less) integer values are returned in gpr3;

84821

+ - Structures of size <= 4 bytes also returned in gpr3;

84822

+ - 64-bit integer values and structures between 5 and 8 bytes are returned

84823

+ in gpr3 and gpr4;

84824

+ - Larger structures are allocated space and a pointer is passed as

84825

+ the first argument.

84826

+ - Single/double FP values are returned in fpr1;

84827

+ - long doubles (if not equivalent to double) are returned in

84828

+ fpr1,fpr2 for Linux and as for large structs for SysV. */

84829

+

84830

+ type = translate_float (cif->abi, type);

84831

+

84832

+ switch (type)

84833

+ {

84834

+#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

84835

+ case FFI_TYPE_LONGDOUBLE:

84836

+ flags |= FLAG_RETURNS_128BITS;

84837

+ /* Fall through. */

84838

+#endif

84839

+ case FFI_TYPE_DOUBLE:

84840

+ flags |= FLAG_RETURNS_64BITS;

84841

+ /* Fall through. */

84842

+ case FFI_TYPE_FLOAT:

84843

+ flags |= FLAG_RETURNS_FP;

84844

+#ifdef __NO_FPRS__

84845

+ return FFI_BAD_ABI;

84846

+#endif

84847

+ break;

84848

+

84849

+ case FFI_TYPE_UINT128:

84850

+ flags |= FLAG_RETURNS_128BITS;

84851

+ /* Fall through. */

84852

+ case FFI_TYPE_UINT64:

84853

+ case FFI_TYPE_SINT64:

84854

+ flags |= FLAG_RETURNS_64BITS;

84855

+ break;

84856

+

84857

+ case FFI_TYPE_STRUCT:

84858

+ /* The final SYSV ABI says that structures smaller or equal 8 bytes

84859

+ are returned in r3/r4. A draft ABI used by linux instead

84860

+ returns them in memory. */

84861

+ if ((cif->abi & FFI_SYSV_STRUCT_RET) != 0 && size <= 8)

84862

+ {

84863

+ flags |= FLAG_RETURNS_SMST;

84864

+ break;

84865

+ }

84866

+ intarg_count++;

84867

+ flags |= FLAG_RETVAL_REFERENCE;

84868

+ /* Fall through. */

84869

+ case FFI_TYPE_VOID:

84870

+ flags |= FLAG_RETURNS_NOTHING;

84871

+ break;

84872

+

84873

+ default:

84874

+ /* Returns 32-bit integer, or similar. Nothing to do here. */

84875

+ break;

84876

+ }

84877

+

84878

+ /* The first NUM_GPR_ARG_REGISTERS words of integer arguments, and the

84879

+ first NUM_FPR_ARG_REGISTERS fp arguments, go in registers; the rest

84880

+ goes on the stack. Structures and long doubles (if not equivalent

84881

+ to double) are passed as a pointer to a copy of the structure.

84882

+ Stuff on the stack needs to keep proper alignment. */

84883

+ for (ptr = cif->arg_types, i = cif->nargs; i > 0; i--, ptr++)

84884

+ {

84885

+ unsigned short typenum = (*ptr)->type;

84886

+

84887

+ typenum = translate_float (cif->abi, typenum);

84888

+

84889

+ switch (typenum)

84890

+ {

84891

+#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

84892

+ case FFI_TYPE_LONGDOUBLE:

84893

+ fparg_count++;

84894

+ /* Fall thru */

84895

+#endif

84896

+ case FFI_TYPE_DOUBLE:

84897

+ fparg_count++;

84898

+ /* If this FP arg is going on the stack, it must be

84899

+ 8-byte-aligned. */

84900

+ if (fparg_count > NUM_FPR_ARG_REGISTERS

84901

+ && intarg_count >= NUM_GPR_ARG_REGISTERS

84902

+ && intarg_count % 2 != 0)

84903

+ intarg_count++;

84904

+#ifdef __NO_FPRS__

84905

+ return FFI_BAD_ABI;

84906

+#endif

84907

+ break;

84908

+

84909

+ case FFI_TYPE_FLOAT:

84910

+ fparg_count++;

84911

+#ifdef __NO_FPRS__

84912

+ return FFI_BAD_ABI;

84913

+#endif

84914

+ break;

84915

+

84916

+ case FFI_TYPE_UINT128:

84917

+ /* A long double in FFI_LINUX_SOFT_FLOAT can use only a set

84918

+ of four consecutive gprs. If we do not have enough, we

84919

+ have to adjust the intarg_count value. */

84920

+ if (intarg_count >= NUM_GPR_ARG_REGISTERS - 3

84921

+ && intarg_count < NUM_GPR_ARG_REGISTERS)

84922

+ intarg_count = NUM_GPR_ARG_REGISTERS;

84923

+ intarg_count += 4;

84924

+ break;

84925

+

84926

+ case FFI_TYPE_UINT64:

84927

+ case FFI_TYPE_SINT64:

84928

+ /* 'long long' arguments are passed as two words, but

84929

+ either both words must fit in registers or both go

84930

+ on the stack. If they go on the stack, they must

84931

+ be 8-byte-aligned.

84932

+

84933

+ Also, only certain register pairs can be used for

84934

+ passing long long int -- specifically (r3,r4), (r5,r6),

84935

+ (r7,r8), (r9,r10). */

84936

+ if (intarg_count == NUM_GPR_ARG_REGISTERS-1

84937

+ || intarg_count % 2 != 0)

84938

+ intarg_count++;

84939

+ intarg_count += 2;

84940

+ break;

84941

+

84942

+ case FFI_TYPE_STRUCT:

84943

+ /* We must allocate space for a copy of these to enforce

84944

+ pass-by-value. Pad the space up to a multiple of 16

84945

+ bytes (the maximum alignment required for anything under

84946

+ the SYSV ABI). */

84947

+ struct_copy_size += ((*ptr)->size + 15) & ~0xF;

84948

+ /* Fall through (allocate space for the pointer). */

84949

+

84950

+ case FFI_TYPE_POINTER:

84951

+ case FFI_TYPE_INT:

84952

+ case FFI_TYPE_UINT32:

84953

+ case FFI_TYPE_SINT32:

84954

+ case FFI_TYPE_UINT16:

84955

+ case FFI_TYPE_SINT16:

84956

+ case FFI_TYPE_UINT8:

84957

+ case FFI_TYPE_SINT8:

84958

+ /* Everything else is passed as a 4-byte word in a GPR, either

84959

+ the object itself or a pointer to it. */

84960

+ intarg_count++;

84961

+ break;

84962

+

84963

+ default:

84964

+ FFI_ASSERT (0);

84965

+ }

84966

+ }

84967

+

84968

+ if (fparg_count != 0)

84969

+ flags |= FLAG_FP_ARGUMENTS;

84970

+ if (intarg_count > 4)

84971

+ flags |= FLAG_4_GPR_ARGUMENTS;

84972

+ if (struct_copy_size != 0)

84973

+ flags |= FLAG_ARG_NEEDS_COPY;

84974

+

84975

+ /* Space for the FPR registers, if needed. */

84976

+ if (fparg_count != 0)

84977

+ bytes += NUM_FPR_ARG_REGISTERS * sizeof (double);

84978

+

84979

+ /* Stack space. */

84980

+ if (intarg_count > NUM_GPR_ARG_REGISTERS)

84981

+ bytes += (intarg_count - NUM_GPR_ARG_REGISTERS) * sizeof (int);

84982

+ if (fparg_count > NUM_FPR_ARG_REGISTERS)

84983

+ bytes += (fparg_count - NUM_FPR_ARG_REGISTERS) * sizeof (double);

84984

+

84985

+ /* The stack space allocated needs to be a multiple of 16 bytes. */

84986

+ bytes = (bytes + 15) & ~0xF;

84987

+

84988

+ /* Add in the space for the copied structures. */

84989

+ bytes += struct_copy_size;

84990

+

84991

+ cif->flags = flags;

84992

+ cif->bytes = bytes;

84993

+

84994

+ return FFI_OK;

84995

+}

84996

+

84997

+ffi_status FFI_HIDDEN

84998

+ffi_prep_cif_sysv (ffi_cif *cif)

84999

+{

85000

+ if ((cif->abi & FFI_SYSV) == 0)

85001

+ {

85002

+ /* This call is from old code. Translate to new ABI values. */

85003

+ cif->flags |= FLAG_COMPAT;

85004

+ switch (cif->abi)

85005

+ {

85006

+ default:

85007

+ return FFI_BAD_ABI;

85008

+

85009

+ case FFI_COMPAT_SYSV:

85010

+ cif->abi = FFI_SYSV | FFI_SYSV_STRUCT_RET | FFI_SYSV_LONG_DOUBLE_128;

85011

+ break;

85012

+

85013

+ case FFI_COMPAT_GCC_SYSV:

85014

+ cif->abi = FFI_SYSV | FFI_SYSV_LONG_DOUBLE_128;

85015

+ break;

85016

+

85017

+ case FFI_COMPAT_LINUX:

85018

+ cif->abi = (FFI_SYSV | FFI_SYSV_IBM_LONG_DOUBLE

85019

+ | FFI_SYSV_LONG_DOUBLE_128);

85020

+ break;

85021

+

85022

+ case FFI_COMPAT_LINUX_SOFT_FLOAT:

85023

+ cif->abi = (FFI_SYSV | FFI_SYSV_SOFT_FLOAT | FFI_SYSV_IBM_LONG_DOUBLE

85024

+ | FFI_SYSV_LONG_DOUBLE_128);

85025

+ break;

85026

+ }

85027

+ }

85028

+ return ffi_prep_cif_sysv_core (cif);

85029

+}

85030

+

85031

+/* ffi_prep_args_SYSV is called by the assembly routine once stack space

85032

+ has been allocated for the function's arguments.

85033

+

85034

+ The stack layout we want looks like this:

85035

+

85036

+ | Return address from ffi_call_SYSV 4bytes | higher addresses

85037

+ |--------------------------------------------|

85038

+ | Previous backchain pointer 4 | stack pointer here

85039

+ |--------------------------------------------|<+ <<< on entry to

85040

+ | Saved r28-r31 4*4 | | ffi_call_SYSV

85041

+ |--------------------------------------------| |

85042

+ | GPR registers r3-r10 8*4 | | ffi_call_SYSV

85043

+ |--------------------------------------------| |

85044

+ | FPR registers f1-f8 (optional) 8*8 | |

85045

+ |--------------------------------------------| | stack |

85046

+ | Space for copied structures | | grows |

85047

+ |--------------------------------------------| | down V

85048

+ | Parameters that didn't fit in registers | |

85049

+ |--------------------------------------------| | lower addresses

85050

+ | Space for callee's LR 4 | |

85051

+ |--------------------------------------------| | stack pointer here

85052

+ | Current backchain pointer 4 |-/ during

85053

+ |--------------------------------------------| <<< ffi_call_SYSV

85054

+

85055

+*/

85056

+

85057

+void FFI_HIDDEN

85058

+ffi_prep_args_SYSV (extended_cif *ecif, unsigned *const stack)

85059

+{

85060

+ const unsigned bytes = ecif->cif->bytes;

85061

+ const unsigned flags = ecif->cif->flags;

85062

+

85063

+ typedef union

85064

+ {

85065

+ char *c;

85066

+ unsigned *u;

85067

+ long long *ll;

85068

+ float *f;

85069

+ double *d;

85070

+ } valp;

85071

+

85072

+ /* 'stacktop' points at the previous backchain pointer. */

85073

+ valp stacktop;

85074

+

85075

+ /* 'gpr_base' points at the space for gpr3, and grows upwards as

85076

+ we use GPR registers. */

85077

+ valp gpr_base;

85078

+ int intarg_count;

85079

+

85080

+#ifndef __NO_FPRS__

85081

+ /* 'fpr_base' points at the space for fpr1, and grows upwards as

85082

+ we use FPR registers. */

85083

+ valp fpr_base;

85084

+ int fparg_count;

85085

+#endif

85086

+

85087

+ /* 'copy_space' grows down as we put structures in it. It should

85088

+ stay 16-byte aligned. */

85089

+ valp copy_space;

85090

+

85091

+ /* 'next_arg' grows up as we put parameters in it. */

85092

+ valp next_arg;

85093

+

85094

+ int i;

85095

+ ffi_type **ptr;

85096

+#ifndef __NO_FPRS__

85097

+ double double_tmp;

85098

+#endif

85099

+ union

85100

+ {

85101

+ void **v;

85102

+ char **c;

85103

+ signed char **sc;

85104

+ unsigned char **uc;

85105

+ signed short **ss;

85106

+ unsigned short **us;

85107

+ unsigned int **ui;

85108

+ long long **ll;

85109

+ float **f;

85110

+ double **d;

85111

+ } p_argv;

85112

+ size_t struct_copy_size;

85113

+ unsigned gprvalue;

85114

+

85115

+ stacktop.c = (char *) stack + bytes;

85116

+ gpr_base.u = stacktop.u - ASM_NEEDS_REGISTERS - NUM_GPR_ARG_REGISTERS;

85117

+ intarg_count = 0;

85118

+#ifndef __NO_FPRS__

85119

+ fpr_base.d = gpr_base.d - NUM_FPR_ARG_REGISTERS;

85120

+ fparg_count = 0;

85121

+ copy_space.c = ((flags & FLAG_FP_ARGUMENTS) ? fpr_base.c : gpr_base.c);

85122

+#else

85123

+ copy_space.c = gpr_base.c;

85124

+#endif

85125

+ next_arg.u = stack + 2;

85126

+

85127

+ /* Check that everything starts aligned properly. */

85128

+ FFI_ASSERT (((unsigned long) (char *) stack & 0xF) == 0);

85129

+ FFI_ASSERT (((unsigned long) copy_space.c & 0xF) == 0);

85130

+ FFI_ASSERT (((unsigned long) stacktop.c & 0xF) == 0);

85131

+ FFI_ASSERT ((bytes & 0xF) == 0);

85132

+ FFI_ASSERT (copy_space.c >= next_arg.c);

85133

+

85134

+ /* Deal with return values that are actually pass-by-reference. */

85135

+ if (flags & FLAG_RETVAL_REFERENCE)

85136

+ {

85137

+ *gpr_base.u++ = (unsigned long) (char *) ecif->rvalue;

85138

+ intarg_count++;

85139

+ }

85140

+

85141

+ /* Now for the arguments. */

85142

+ p_argv.v = ecif->avalue;

85143

+ for (ptr = ecif->cif->arg_types, i = ecif->cif->nargs;

85144

+ i > 0;

85145

+ i--, ptr++, p_argv.v++)

85146

+ {

85147

+ unsigned int typenum = (*ptr)->type;

85148

+

85149

+ typenum = translate_float (ecif->cif->abi, typenum);

85150

+

85151

+ /* Now test the translated value */

85152

+ switch (typenum)

85153

+ {

85154

+#ifndef __NO_FPRS__

85155

+# if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

85156

+ case FFI_TYPE_LONGDOUBLE:

85157

+ double_tmp = (*p_argv.d)[0];

85158

+

85159

+ if (fparg_count >= NUM_FPR_ARG_REGISTERS - 1)

85160

+ {

85161

+ if (intarg_count >= NUM_GPR_ARG_REGISTERS

85162

+ && intarg_count % 2 != 0)

85163

+ {

85164

+ intarg_count++;

85165

+ next_arg.u++;

85166

+ }

85167

+ *next_arg.d = double_tmp;

85168

+ next_arg.u += 2;

85169

+ double_tmp = (*p_argv.d)[1];

85170

+ *next_arg.d = double_tmp;

85171

+ next_arg.u += 2;

85172

+ }

85173

+ else

85174

+ {

85175

+ *fpr_base.d++ = double_tmp;

85176

+ double_tmp = (*p_argv.d)[1];

85177

+ *fpr_base.d++ = double_tmp;

85178

+ }

85179

+

85180

+ fparg_count += 2;

85181

+ FFI_ASSERT (flags & FLAG_FP_ARGUMENTS);

85182

+ break;

85183

+# endif

85184

+ case FFI_TYPE_DOUBLE:

85185

+ double_tmp = **p_argv.d;

85186

+

85187

+ if (fparg_count >= NUM_FPR_ARG_REGISTERS)

85188

+ {

85189

+ if (intarg_count >= NUM_GPR_ARG_REGISTERS

85190

+ && intarg_count % 2 != 0)

85191

+ {

85192

+ intarg_count++;

85193

+ next_arg.u++;

85194

+ }

85195

+ *next_arg.d = double_tmp;

85196

+ next_arg.u += 2;

85197

+ }

85198

+ else

85199

+ *fpr_base.d++ = double_tmp;

85200

+ fparg_count++;

85201

+ FFI_ASSERT (flags & FLAG_FP_ARGUMENTS);

85202

+ break;

85203

+

85204

+ case FFI_TYPE_FLOAT:

85205

+ double_tmp = **p_argv.f;

85206

+ if (fparg_count >= NUM_FPR_ARG_REGISTERS)

85207

+ {

85208

+ *next_arg.f = (float) double_tmp;

85209

+ next_arg.u += 1;

85210

+ intarg_count++;

85211

+ }

85212

+ else

85213

+ *fpr_base.d++ = double_tmp;

85214

+ fparg_count++;

85215

+ FFI_ASSERT (flags & FLAG_FP_ARGUMENTS);

85216

+ break;

85217

+#endif /* have FPRs */

85218

+

85219

+ case FFI_TYPE_UINT128:

85220

+ /* The soft float ABI for long doubles works like this, a long double

85221

+ is passed in four consecutive GPRs if available. A maximum of 2

85222

+ long doubles can be passed in gprs. If we do not have 4 GPRs

85223

+ left, the long double is passed on the stack, 4-byte aligned. */

85224

+ {

85225

+ unsigned int int_tmp;

85226

+ unsigned int ii;

85227

+ if (intarg_count >= NUM_GPR_ARG_REGISTERS - 3)

85228

+ {

85229

+ if (intarg_count < NUM_GPR_ARG_REGISTERS)

85230

+ intarg_count = NUM_GPR_ARG_REGISTERS;

85231

+ for (ii = 0; ii < 4; ii++)

85232

+ {

85233

+ int_tmp = (*p_argv.ui)[ii];

85234

+ *next_arg.u++ = int_tmp;

85235

+ }

85236

+ }

85237

+ else

85238

+ {

85239

+ for (ii = 0; ii < 4; ii++)

85240

+ {

85241

+ int_tmp = (*p_argv.ui)[ii];

85242

+ *gpr_base.u++ = int_tmp;

85243

+ }

85244

+ }

85245

+ intarg_count += 4;

85246

+ break;

85247

+ }

85248

+

85249

+ case FFI_TYPE_UINT64:

85250

+ case FFI_TYPE_SINT64:

85251

+ if (intarg_count == NUM_GPR_ARG_REGISTERS-1)

85252

+ intarg_count++;

85253

+ if (intarg_count >= NUM_GPR_ARG_REGISTERS)

85254

+ {

85255

+ if (intarg_count % 2 != 0)

85256

+ {

85257

+ intarg_count++;

85258

+ next_arg.u++;

85259

+ }

85260

+ *next_arg.ll = **p_argv.ll;

85261

+ next_arg.u += 2;

85262

+ }

85263

+ else

85264

+ {

85265

+ /* The abi states only certain register pairs can be

85266

+ used for passing long long int specifically (r3,r4),

85267

+ (r5,r6), (r7,r8), (r9,r10). If next arg is long long

85268

+ but not correct starting register of pair then skip

85269

+ until the proper starting register. */

85270

+ if (intarg_count % 2 != 0)

85271

+ {

85272

+ intarg_count ++;

85273

+ gpr_base.u++;

85274

+ }

85275

+ *gpr_base.ll++ = **p_argv.ll;

85276

+ }

85277

+ intarg_count += 2;

85278

+ break;

85279

+

85280

+ case FFI_TYPE_STRUCT:

85281

+ struct_copy_size = ((*ptr)->size + 15) & ~0xF;

85282

+ copy_space.c -= struct_copy_size;

85283

+ memcpy (copy_space.c, *p_argv.c, (*ptr)->size);

85284

+

85285

+ gprvalue = (unsigned long) copy_space.c;

85286

+

85287

+ FFI_ASSERT (copy_space.c > next_arg.c);

85288

+ FFI_ASSERT (flags & FLAG_ARG_NEEDS_COPY);

85289

+ goto putgpr;

85290

+

85291

+ case FFI_TYPE_UINT8:

85292

+ gprvalue = **p_argv.uc;

85293

+ goto putgpr;

85294

+ case FFI_TYPE_SINT8:

85295

+ gprvalue = **p_argv.sc;

85296

+ goto putgpr;

85297

+ case FFI_TYPE_UINT16:

85298

+ gprvalue = **p_argv.us;

85299

+ goto putgpr;

85300

+ case FFI_TYPE_SINT16:

85301

+ gprvalue = **p_argv.ss;

85302

+ goto putgpr;

85303

+

85304

+ case FFI_TYPE_INT:

85305

+ case FFI_TYPE_UINT32:

85306

+ case FFI_TYPE_SINT32:

85307

+ case FFI_TYPE_POINTER:

85308

+

85309

+ gprvalue = **p_argv.ui;

85310

+

85311

+ putgpr:

85312

+ if (intarg_count >= NUM_GPR_ARG_REGISTERS)

85313

+ *next_arg.u++ = gprvalue;

85314

+ else

85315

+ *gpr_base.u++ = gprvalue;

85316

+ intarg_count++;

85317

+ break;

85318

+ }

85319

+ }

85320

+

85321

+ /* Check that we didn't overrun the stack... */

85322

+ FFI_ASSERT (copy_space.c >= next_arg.c);

85323

+ FFI_ASSERT (gpr_base.u <= stacktop.u - ASM_NEEDS_REGISTERS);

85324

+ /* The assert below is testing that the number of integer arguments agrees

85325

+ with the number found in ffi_prep_cif_machdep(). However, intarg_count

85326

+ is incremented whenever we place an FP arg on the stack, so account for

85327

+ that before our assert test. */

85328

+#ifndef __NO_FPRS__

85329

+ if (fparg_count > NUM_FPR_ARG_REGISTERS)

85330

+ intarg_count -= fparg_count - NUM_FPR_ARG_REGISTERS;

85331

+ FFI_ASSERT (fpr_base.u

85332

+ <= stacktop.u - ASM_NEEDS_REGISTERS - NUM_GPR_ARG_REGISTERS);

85333

+#endif

85334

+ FFI_ASSERT (flags & FLAG_4_GPR_ARGUMENTS || intarg_count <= 4);

85335

+}

85336

+

85337

+#define MIN_CACHE_LINE_SIZE 8

85338

+

85339

+static void

85340

+flush_icache (char *wraddr, char *xaddr, int size)

85341

+{

85342

+ int i;

85343

+ for (i = 0; i < size; i += MIN_CACHE_LINE_SIZE)

85344

+ __asm__ volatile ("icbi 0,%0;" "dcbf 0,%1;"

85345

+ : : "r" (xaddr + i), "r" (wraddr + i) : "memory");

85346

+ __asm__ volatile ("icbi 0,%0;" "dcbf 0,%1;" "sync;" "isync;"

85347

+ : : "r"(xaddr + size - 1), "r"(wraddr + size - 1)

85348

+ : "memory");

85349

+}

85350

+

85351

+ffi_status FFI_HIDDEN

85352

+ffi_prep_closure_loc_sysv (ffi_closure *closure,

85353

+ ffi_cif *cif,

85354

+ void (*fun) (ffi_cif *, void *, void **, void *),

85355

+ void *user_data,

85356

+ void *codeloc)

85357

+{

85358

+ unsigned int *tramp;

85359

+

85360

+ if (cif->abi < FFI_SYSV || cif->abi >= FFI_LAST_ABI)

85361

+ return FFI_BAD_ABI;

85362

+

85363

+ tramp = (unsigned int *) &closure->tramp[0];

85364

+ tramp[0] = 0x7c0802a6; /* mflr r0 */

85365

+ tramp[1] = 0x4800000d; /* bl 10 <trampoline_initial+0x10> */

85366

+ tramp[4] = 0x7d6802a6; /* mflr r11 */

85367

+ tramp[5] = 0x7c0803a6; /* mtlr r0 */

85368

+ tramp[6] = 0x800b0000; /* lwz r0,0(r11) */

85369

+ tramp[7] = 0x816b0004; /* lwz r11,4(r11) */

85370

+ tramp[8] = 0x7c0903a6; /* mtctr r0 */

85371

+ tramp[9] = 0x4e800420; /* bctr */

85372

+ *(void **) &tramp[2] = (void *) ffi_closure_SYSV; /* function */

85373

+ *(void **) &tramp[3] = codeloc; /* context */

85374

+

85375

+ /* Flush the icache. */

85376

+ flush_icache ((char *)tramp, (char *)codeloc, FFI_TRAMPOLINE_SIZE);

85377

+

85378

+ closure->cif = cif;

85379

+ closure->fun = fun;

85380

+ closure->user_data = user_data;

85381

+

85382

+ return FFI_OK;

85383

+}

85384

+

85385

+/* Basically the trampoline invokes ffi_closure_SYSV, and on

85386

+ entry, r11 holds the address of the closure.

85387

+ After storing the registers that could possibly contain

85388

+ parameters to be passed into the stack frame and setting

85389

+ up space for a return value, ffi_closure_SYSV invokes the

85390

+ following helper function to do most of the work. */

85391

+

85392

+int

85393

+ffi_closure_helper_SYSV (ffi_closure *closure, void *rvalue,

85394

+ unsigned long *pgr, ffi_dblfl *pfr,

85395

+ unsigned long *pst)

85396

+{

85397

+ /* rvalue is the pointer to space for return value in closure assembly */

85398

+ /* pgr is the pointer to where r3-r10 are stored in ffi_closure_SYSV */

85399

+ /* pfr is the pointer to where f1-f8 are stored in ffi_closure_SYSV */

85400

+ /* pst is the pointer to outgoing parameter stack in original caller */

85401

+

85402

+ void ** avalue;

85403

+ ffi_type ** arg_types;

85404

+ long i, avn;

85405

+#ifndef __NO_FPRS__

85406

+ long nf = 0; /* number of floating registers already used */

85407

+#endif

85408

+ long ng = 0; /* number of general registers already used */

85409

+

85410

+ ffi_cif *cif = closure->cif;

85411

+ unsigned size = cif->rtype->size;

85412

+ unsigned short rtypenum = cif->rtype->type;

85413

+

85414

+ avalue = alloca (cif->nargs * sizeof (void *));

85415

+

85416

+ /* First translate for softfloat/nonlinux */

85417

+ rtypenum = translate_float (cif->abi, rtypenum);

85418

+

85419

+ /* Copy the caller's structure return value address so that the closure

85420

+ returns the data directly to the caller.

85421

+ For FFI_SYSV the result is passed in r3/r4 if the struct size is less

85422

+ or equal 8 bytes. */

85423

+ if (rtypenum == FFI_TYPE_STRUCT

85424

+ && !((cif->abi & FFI_SYSV_STRUCT_RET) != 0 && size <= 8))

85425

+ {

85426

+ rvalue = (void *) *pgr;

85427

+ ng++;

85428

+ pgr++;

85429

+ }

85430

+

85431

+ i = 0;

85432

+ avn = cif->nargs;

85433

+ arg_types = cif->arg_types;

85434

+

85435

+ /* Grab the addresses of the arguments from the stack frame. */

85436

+ while (i < avn) {

85437

+ unsigned short typenum = arg_types[i]->type;

85438

+

85439

+ /* We may need to handle some values depending on ABI. */

85440

+ typenum = translate_float (cif->abi, typenum);

85441

+

85442

+ switch (typenum)

85443

+ {

85444

+#ifndef __NO_FPRS__

85445

+ case FFI_TYPE_FLOAT:

85446

+ /* Unfortunately float values are stored as doubles

85447

+ in the ffi_closure_SYSV code (since we don't check

85448

+ the type in that routine). */

85449

+ if (nf < NUM_FPR_ARG_REGISTERS)

85450

+ {

85451

+ /* FIXME? here we are really changing the values

85452

+ stored in the original calling routines outgoing

85453

+ parameter stack. This is probably a really

85454

+ naughty thing to do but... */

85455

+ double temp = pfr->d;

85456

+ pfr->f = (float) temp;

85457

+ avalue[i] = pfr;

85458

+ nf++;

85459

+ pfr++;

85460

+ }

85461

+ else

85462

+ {

85463

+ avalue[i] = pst;

85464

+ pst += 1;

85465

+ }

85466

+ break;

85467

+

85468

+ case FFI_TYPE_DOUBLE:

85469

+ if (nf < NUM_FPR_ARG_REGISTERS)

85470

+ {

85471

+ avalue[i] = pfr;

85472

+ nf++;

85473

+ pfr++;

85474

+ }

85475

+ else

85476

+ {

85477

+ if (((long) pst) & 4)

85478

+ pst++;

85479

+ avalue[i] = pst;

85480

+ pst += 2;

85481

+ }

85482

+ break;

85483

+

85484

+# if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

85485

+ case FFI_TYPE_LONGDOUBLE:

85486

+ if (nf < NUM_FPR_ARG_REGISTERS - 1)

85487

+ {

85488

+ avalue[i] = pfr;

85489

+ pfr += 2;

85490

+ nf += 2;

85491

+ }

85492

+ else

85493

+ {

85494

+ if (((long) pst) & 4)

85495

+ pst++;

85496

+ avalue[i] = pst;

85497

+ pst += 4;

85498

+ nf = 8;

85499

+ }

85500

+ break;

85501

+# endif

85502

+#endif

85503

+

85504

+ case FFI_TYPE_UINT128:

85505

+ /* Test if for the whole long double, 4 gprs are available.

85506

+ otherwise the stuff ends up on the stack. */

85507

+ if (ng < NUM_GPR_ARG_REGISTERS - 3)

85508

+ {

85509

+ avalue[i] = pgr;

85510

+ pgr += 4;

85511

+ ng += 4;

85512

+ }

85513

+ else

85514

+ {

85515

+ avalue[i] = pst;

85516

+ pst += 4;

85517

+ ng = 8+4;

85518

+ }

85519

+ break;

85520

+

85521

+ case FFI_TYPE_SINT8:

85522

+ case FFI_TYPE_UINT8:

85523

+#ifndef __LITTLE_ENDIAN__

85524

+ if (ng < NUM_GPR_ARG_REGISTERS)

85525

+ {

85526

+ avalue[i] = (char *) pgr + 3;

85527

+ ng++;

85528

+ pgr++;

85529

+ }

85530

+ else

85531

+ {

85532

+ avalue[i] = (char *) pst + 3;

85533

+ pst++;

85534

+ }

85535

+ break;

85536

+#endif

85537

+

85538

+ case FFI_TYPE_SINT16:

85539

+ case FFI_TYPE_UINT16:

85540

+#ifndef __LITTLE_ENDIAN__

85541

+ if (ng < NUM_GPR_ARG_REGISTERS)

85542

+ {

85543

+ avalue[i] = (char *) pgr + 2;

85544

+ ng++;

85545

+ pgr++;

85546

+ }

85547

+ else

85548

+ {

85549

+ avalue[i] = (char *) pst + 2;

85550

+ pst++;

85551

+ }

85552

+ break;

85553

+#endif

85554

+

85555

+ case FFI_TYPE_SINT32:

85556

+ case FFI_TYPE_UINT32:

85557

+ case FFI_TYPE_POINTER:

85558

+ if (ng < NUM_GPR_ARG_REGISTERS)

85559

+ {

85560

+ avalue[i] = pgr;

85561

+ ng++;

85562

+ pgr++;

85563

+ }

85564

+ else

85565

+ {

85566

+ avalue[i] = pst;

85567

+ pst++;

85568

+ }

85569

+ break;

85570

+

85571

+ case FFI_TYPE_STRUCT:

85572

+ /* Structs are passed by reference. The address will appear in a

85573

+ gpr if it is one of the first 8 arguments. */

85574

+ if (ng < NUM_GPR_ARG_REGISTERS)

85575

+ {

85576

+ avalue[i] = (void *) *pgr;

85577

+ ng++;

85578

+ pgr++;

85579

+ }

85580

+ else

85581

+ {

85582

+ avalue[i] = (void *) *pst;

85583

+ pst++;

85584

+ }

85585

+ break;

85586

+

85587

+ case FFI_TYPE_SINT64:

85588

+ case FFI_TYPE_UINT64:

85589

+ /* Passing long long ints are complex, they must

85590

+ be passed in suitable register pairs such as

85591

+ (r3,r4) or (r5,r6) or (r6,r7), or (r7,r8) or (r9,r10)

85592

+ and if the entire pair aren't available then the outgoing

85593

+ parameter stack is used for both but an alignment of 8

85594

+ must will be kept. So we must either look in pgr

85595

+ or pst to find the correct address for this type

85596

+ of parameter. */

85597

+ if (ng < NUM_GPR_ARG_REGISTERS - 1)

85598

+ {

85599

+ if (ng & 1)

85600

+ {

85601

+ /* skip r4, r6, r8 as starting points */

85602

+ ng++;

85603

+ pgr++;

85604

+ }

85605

+ avalue[i] = pgr;

85606

+ ng += 2;

85607

+ pgr += 2;

85608

+ }

85609

+ else

85610

+ {

85611

+ if (((long) pst) & 4)

85612

+ pst++;

85613

+ avalue[i] = pst;

85614

+ pst += 2;

85615

+ ng = NUM_GPR_ARG_REGISTERS;

85616

+ }

85617

+ break;

85618

+

85619

+ default:

85620

+ FFI_ASSERT (0);

85621

+ }

85622

+

85623

+ i++;

85624

+ }

85625

+

85626

+ (closure->fun) (cif, rvalue, avalue, closure->user_data);

85627

+

85628

+ /* Tell ffi_closure_SYSV how to perform return type promotions.

85629

+ Because the FFI_SYSV ABI returns the structures <= 8 bytes in

85630

+ r3/r4 we have to tell ffi_closure_SYSV how to treat them. We

85631

+ combine the base type FFI_SYSV_TYPE_SMALL_STRUCT with the size of

85632

+ the struct less one. We never have a struct with size zero.

85633

+ See the comment in ffitarget.h about ordering. */

85634

+ if (rtypenum == FFI_TYPE_STRUCT

85635

+ && (cif->abi & FFI_SYSV_STRUCT_RET) != 0 && size <= 8)

85636

+ return FFI_SYSV_TYPE_SMALL_STRUCT - 1 + size;

85637

+ return rtypenum;

85638

+}

85639

+#endif

85640

Index: libffi/src/powerpc/linux64.S

85641

===================================================================

85642

--- a/src/libffi/src/powerpc/linux64.S (.../tags/gcc_4_8_2_release)

85643

+++ b/src/libffi/src/powerpc/linux64.S (.../branches/gcc-4_8-branch)

85644

@@ -29,18 +29,25 @@

85645

#include <fficonfig.h>

85646

#include <ffi.h>

85647

85648

-#ifdef __powerpc64__

85649

+#ifdef POWERPC64

85650

.hidden ffi_call_LINUX64

85651

.globl ffi_call_LINUX64

85652

+# if _CALL_ELF == 2

85653

+ .text

85654

+ffi_call_LINUX64:

85655

+ addis %r2, %r12, .TOC.-ffi_call_LINUX64@ha

85656

+ addi %r2, %r2, .TOC.-ffi_call_LINUX64@l

85657

+ .localentry ffi_call_LINUX64, . - ffi_call_LINUX64

85658

+# else

85659

.section ".opd","aw"

85660

.align 3

85661

ffi_call_LINUX64:

85662

-#ifdef _CALL_LINUX

85663

+# ifdef _CALL_LINUX

85664

.quad .L.ffi_call_LINUX64,.TOC.@tocbase,0

85665

.type ffi_call_LINUX64,@function

85666

.text

85667

.L.ffi_call_LINUX64:

85668

-#else

85669

+# else

85670

.hidden .ffi_call_LINUX64

85671

.globl .ffi_call_LINUX64

85672

.quad .ffi_call_LINUX64,.TOC.@tocbase,0

85673

@@ -48,7 +55,8 @@

85674

.type .ffi_call_LINUX64,@function

85675

.text

85676

.ffi_call_LINUX64:

85677

-#endif

85678

+# endif

85679

+# endif

85680

.LFB1:

85681

mflr %r0

85682

std %r28, -32(%r1)

85683

@@ -63,26 +71,35 @@

85684

mr %r31, %r5 /* flags, */

85685

mr %r30, %r6 /* rvalue, */

85686

mr %r29, %r7 /* function address. */

85687

+/* Save toc pointer, not for the ffi_prep_args64 call, but for the later

85688

+ bctrl function call. */

85689

+# if _CALL_ELF == 2

85690

+ std %r2, 24(%r1)

85691

+# else

85692

std %r2, 40(%r1)

85693

+# endif

85694

85695

/* Call ffi_prep_args64. */

85696

mr %r4, %r1

85697

-#ifdef _CALL_LINUX

85698

+# if defined _CALL_LINUX || _CALL_ELF == 2

85699

bl ffi_prep_args64

85700

-#else

85701

+# else

85702

bl .ffi_prep_args64

85703

-#endif

85704

+# endif

85705

85706

- ld %r0, 0(%r29)

85707

+# if _CALL_ELF == 2

85708

+ mr %r12, %r29

85709

+# else

85710

+ ld %r12, 0(%r29)

85711

ld %r2, 8(%r29)

85712

ld %r11, 16(%r29)

85713

-

85714

+# endif

85715

/* Now do the call. */

85716

/* Set up cr1 with bits 4-7 of the flags. */

85717

mtcrf 0x40, %r31

85718

85719

/* Get the address to call into CTR. */

85720

- mtctr %r0

85721

+ mtctr %r12

85722

/* Load all those argument registers. */

85723

ld %r3, -32-(8*8)(%r28)

85724

ld %r4, -32-(7*8)(%r28)

85725

@@ -117,12 +134,17 @@

85726

85727

/* This must follow the call immediately, the unwinder

85728

uses this to find out if r2 has been saved or not. */

85729

+# if _CALL_ELF == 2

85730

+ ld %r2, 24(%r1)

85731

+# else

85732

ld %r2, 40(%r1)

85733

+# endif

85734

85735

/* Now, deal with the return value. */

85736

mtcrf 0x01, %r31

85737

- bt- 30, .Ldone_return_value

85738

- bt- 29, .Lfp_return_value

85739

+ bt 31, .Lstruct_return_value

85740

+ bt 30, .Ldone_return_value

85741

+ bt 29, .Lfp_return_value

85742

std %r3, 0(%r30)

85743

/* Fall through... */

85744

85745

@@ -130,7 +152,7 @@

85746

/* Restore the registers we used and return. */

85747

mr %r1, %r28

85748

ld %r0, 16(%r28)

85749

- ld %r28, -32(%r1)

85750

+ ld %r28, -32(%r28)

85751

mtlr %r0

85752

ld %r29, -24(%r1)

85753

ld %r30, -16(%r1)

85754

@@ -147,14 +169,48 @@

85755

.Lfloat_return_value:

85756

stfs %f1, 0(%r30)

85757

b .Ldone_return_value

85758

+

85759

+.Lstruct_return_value:

85760

+ bf 29, .Lsmall_struct

85761

+ bf 28, .Lfloat_homog_return_value

85762

+ stfd %f1, 0(%r30)

85763

+ stfd %f2, 8(%r30)

85764

+ stfd %f3, 16(%r30)

85765

+ stfd %f4, 24(%r30)

85766

+ stfd %f5, 32(%r30)

85767

+ stfd %f6, 40(%r30)

85768

+ stfd %f7, 48(%r30)

85769

+ stfd %f8, 56(%r30)

85770

+ b .Ldone_return_value

85771

+

85772

+.Lfloat_homog_return_value:

85773

+ stfs %f1, 0(%r30)

85774

+ stfs %f2, 4(%r30)

85775

+ stfs %f3, 8(%r30)

85776

+ stfs %f4, 12(%r30)

85777

+ stfs %f5, 16(%r30)

85778

+ stfs %f6, 20(%r30)

85779

+ stfs %f7, 24(%r30)

85780

+ stfs %f8, 28(%r30)

85781

+ b .Ldone_return_value

85782

+

85783

+.Lsmall_struct:

85784

+ std %r3, 0(%r30)

85785

+ std %r4, 8(%r30)

85786

+ b .Ldone_return_value

85787

+

85788

.LFE1:

85789

.long 0

85790

.byte 0,12,0,1,128,4,0,0

85791

-#ifdef _CALL_LINUX

85792

+# if _CALL_ELF == 2

85793

+ .size ffi_call_LINUX64,.-ffi_call_LINUX64

85794

+# else

85795

+# ifdef _CALL_LINUX

85796

.size ffi_call_LINUX64,.-.L.ffi_call_LINUX64

85797

-#else

85798

+# else

85799

.size .ffi_call_LINUX64,.-.ffi_call_LINUX64

85800

-#endif

85801

+# endif

85802

+# endif

85803

85804

.section .eh_frame,EH_FRAME_FLAGS,@progbits

85805

.Lframe1:

85806

@@ -197,8 +253,8 @@

85807

.uleb128 0x4

85808

.align 3

85809

.LEFDE1:

85810

-#endif

85811

85812

-#if defined __ELF__ && defined __linux__

85813

+# if (defined __ELF__ && defined __linux__) || _CALL_ELF == 2

85814

.section .note.GNU-stack,"",@progbits

85815

+# endif

85816

#endif

85817

Index: libffi/src/powerpc/ffi_linux64.c

85818

===================================================================

85819

--- a/src/libffi/src/powerpc/ffi_linux64.c (.../tags/gcc_4_8_2_release)

85820

+++ b/src/libffi/src/powerpc/ffi_linux64.c (.../branches/gcc-4_8-branch)

85821

@@ -0,0 +1,942 @@

85822

+/* -----------------------------------------------------------------------

85823

85824

85825

85826

85827

85828

85829

+

85830

+ PowerPC Foreign Function Interface

85831

+

85832

+ Permission is hereby granted, free of charge, to any person obtaining

85833

+ a copy of this software and associated documentation files (the

85834

+ ``Software''), to deal in the Software without restriction, including

85835

+ without limitation the rights to use, copy, modify, merge, publish,

85836

+ distribute, sublicense, and/or sell copies of the Software, and to

85837

+ permit persons to whom the Software is furnished to do so, subject to

85838

+ the following conditions:

85839

+

85840

+ The above copyright notice and this permission notice shall be included

85841

+ in all copies or substantial portions of the Software.

85842

+

85843

+ THE SOFTWARE IS PROVIDED ``AS IS'', WITHOUT WARRANTY OF ANY KIND, EXPRESS

85844

+ OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

85845

+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.

85846

+ IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR

85847

+ OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

85848

+ ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

85849

+ OTHER DEALINGS IN THE SOFTWARE.

85850

+ ----------------------------------------------------------------------- */

85851

+

85852

+#include "ffi.h"

85853

+

85854

+#ifdef POWERPC64

85855

+#include "ffi_common.h"

85856

+#include "ffi_powerpc.h"

85857

+

85858

+

85859

+/* About the LINUX64 ABI. */

85860

+enum {

85861

+ NUM_GPR_ARG_REGISTERS64 = 8,

85862

+ NUM_FPR_ARG_REGISTERS64 = 13

85863

+};

85864

+enum { ASM_NEEDS_REGISTERS64 = 4 };

85865

+

85866

+

85867

+#if HAVE_LONG_DOUBLE_VARIANT && FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

85868

+/* Adjust size of ffi_type_longdouble. */

85869

+void FFI_HIDDEN

85870

+ffi_prep_types_linux64 (ffi_abi abi)

85871

+{

85872

+ if ((abi & (FFI_LINUX | FFI_LINUX_LONG_DOUBLE_128)) == FFI_LINUX)

85873

+ {

85874

+ ffi_type_longdouble.size = 8;

85875

+ ffi_type_longdouble.alignment = 8;

85876

+ }

85877

+ else

85878

+ {

85879

+ ffi_type_longdouble.size = 16;

85880

+ ffi_type_longdouble.alignment = 16;

85881

+ }

85882

+}

85883

+#endif

85884

+

85885

+

85886

+#if _CALL_ELF == 2

85887

+static unsigned int

85888

+discover_homogeneous_aggregate (const ffi_type *t, unsigned int *elnum)

85889

+{

85890

+ switch (t->type)

85891

+ {

85892

+ case FFI_TYPE_FLOAT:

85893

+ case FFI_TYPE_DOUBLE:

85894

+ *elnum = 1;

85895

+ return (int) t->type;

85896

+

85897

+ case FFI_TYPE_STRUCT:;

85898

+ {

85899

+ unsigned int base_elt = 0, total_elnum = 0;

85900

+ ffi_type **el = t->elements;

85901

+ while (*el)

85902

+ {

85903

+ unsigned int el_elt, el_elnum = 0;

85904

+ el_elt = discover_homogeneous_aggregate (*el, &el_elnum);

85905

+ if (el_elt == 0

85906

+ || (base_elt && base_elt != el_elt))

85907

+ return 0;

85908

+ base_elt = el_elt;

85909

+ total_elnum += el_elnum;

85910

+ if (total_elnum > 8)

85911

+ return 0;

85912

+ el++;

85913

+ }

85914

+ *elnum = total_elnum;

85915

+ return base_elt;

85916

+ }

85917

+

85918

+ default:

85919

+ return 0;

85920

+ }

85921

+}

85922

+#endif

85923

+

85924

+

85925

+/* Perform machine dependent cif processing */

85926

+static ffi_status

85927

+ffi_prep_cif_linux64_core (ffi_cif *cif)

85928

+{

85929

+ ffi_type **ptr;

85930

+ unsigned bytes;

85931

+ unsigned i, fparg_count = 0, intarg_count = 0;

85932

+ unsigned flags = cif->flags;

85933

+#if _CALL_ELF == 2

85934

+ unsigned int elt, elnum;

85935

+#endif

85936

+

85937

+#if FFI_TYPE_LONGDOUBLE == FFI_TYPE_DOUBLE

85938

+ /* If compiled without long double support.. */

85939

+ if ((cif->abi & FFI_LINUX_LONG_DOUBLE_128) != 0)

85940

+ return FFI_BAD_ABI;

85941

+#endif

85942

+

85943

+ /* The machine-independent calculation of cif->bytes doesn't work

85944

+ for us. Redo the calculation. */

85945

+#if _CALL_ELF == 2

85946

+ /* Space for backchain, CR, LR, TOC and the asm's temp regs. */

85947

+ bytes = (4 + ASM_NEEDS_REGISTERS64) * sizeof (long);

85948

+

85949

+ /* Space for the general registers. */

85950

+ bytes += NUM_GPR_ARG_REGISTERS64 * sizeof (long);

85951

+#else

85952

+ /* Space for backchain, CR, LR, cc/ld doubleword, TOC and the asm's temp

85953

+ regs. */

85954

+ bytes = (6 + ASM_NEEDS_REGISTERS64) * sizeof (long);

85955

+

85956

+ /* Space for the mandatory parm save area and general registers. */

85957

+ bytes += 2 * NUM_GPR_ARG_REGISTERS64 * sizeof (long);

85958

+#endif

85959

+

85960

+ /* Return value handling. */

85961

+ switch (cif->rtype->type)

85962

+ {

85963

+#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

85964

+ case FFI_TYPE_LONGDOUBLE:

85965

+ if ((cif->abi & FFI_LINUX_LONG_DOUBLE_128) != 0)

85966

+ flags |= FLAG_RETURNS_128BITS;

85967

+ /* Fall through. */

85968

+#endif

85969

+ case FFI_TYPE_DOUBLE:

85970

+ flags |= FLAG_RETURNS_64BITS;

85971

+ /* Fall through. */

85972

+ case FFI_TYPE_FLOAT:

85973

+ flags |= FLAG_RETURNS_FP;

85974

+ break;

85975

+

85976

+ case FFI_TYPE_UINT128:

85977

+ flags |= FLAG_RETURNS_128BITS;

85978

+ /* Fall through. */

85979

+ case FFI_TYPE_UINT64:

85980

+ case FFI_TYPE_SINT64:

85981

+ flags |= FLAG_RETURNS_64BITS;

85982

+ break;

85983

+

85984

+ case FFI_TYPE_STRUCT:

85985

+#if _CALL_ELF == 2

85986

+ elt = discover_homogeneous_aggregate (cif->rtype, &elnum);

85987

+ if (elt)

85988

+ {

85989

+ if (elt == FFI_TYPE_DOUBLE)

85990

+ flags |= FLAG_RETURNS_64BITS;

85991

+ flags |= FLAG_RETURNS_FP | FLAG_RETURNS_SMST;

85992

+ break;

85993

+ }

85994

+ if (cif->rtype->size <= 16)

85995

+ {

85996

+ flags |= FLAG_RETURNS_SMST;

85997

+ break;

85998

+ }

85999

+#endif

86000

+ intarg_count++;

86001

+ flags |= FLAG_RETVAL_REFERENCE;

86002

+ /* Fall through. */

86003

+ case FFI_TYPE_VOID:

86004

+ flags |= FLAG_RETURNS_NOTHING;

86005

+ break;

86006

+

86007

+ default:

86008

+ /* Returns 32-bit integer, or similar. Nothing to do here. */

86009

+ break;

86010

+ }

86011

+

86012

+ for (ptr = cif->arg_types, i = cif->nargs; i > 0; i--, ptr++)

86013

+ {

86014

+ unsigned int align;

86015

+

86016

+ switch ((*ptr)->type)

86017

+ {

86018

+#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

86019

+ case FFI_TYPE_LONGDOUBLE:

86020

+ if ((cif->abi & FFI_LINUX_LONG_DOUBLE_128) != 0)

86021

+ {

86022

+ fparg_count++;

86023

+ intarg_count++;

86024

+ }

86025

+ /* Fall through. */

86026

+#endif

86027

+ case FFI_TYPE_DOUBLE:

86028

+ case FFI_TYPE_FLOAT:

86029

+ fparg_count++;

86030

+ intarg_count++;

86031

+ if (fparg_count > NUM_FPR_ARG_REGISTERS64)

86032

+ flags |= FLAG_ARG_NEEDS_PSAVE;

86033

+ break;

86034

+

86035

+ case FFI_TYPE_STRUCT:

86036

+ if ((cif->abi & FFI_LINUX_STRUCT_ALIGN) != 0)

86037

+ {

86038

+ align = (*ptr)->alignment;

86039

+ if (align > 16)

86040

+ align = 16;

86041

+ align = align / 8;

86042

+ if (align > 1)

86043

+ intarg_count = ALIGN (intarg_count, align);

86044

+ }

86045

+ intarg_count += ((*ptr)->size + 7) / 8;

86046

+#if _CALL_ELF == 2

86047

+ elt = discover_homogeneous_aggregate (*ptr, &elnum);

86048

+ if (elt)

86049

+ {

86050

+ fparg_count += elnum;

86051

+ if (fparg_count > NUM_FPR_ARG_REGISTERS64)

86052

+ flags |= FLAG_ARG_NEEDS_PSAVE;

86053

+ }

86054

+ else

86055

+#endif

86056

+ {

86057

+ if (intarg_count > NUM_GPR_ARG_REGISTERS64)

86058

+ flags |= FLAG_ARG_NEEDS_PSAVE;

86059

+ }

86060

+ break;

86061

+

86062

+ case FFI_TYPE_POINTER:

86063

+ case FFI_TYPE_UINT64:

86064

+ case FFI_TYPE_SINT64:

86065

+ case FFI_TYPE_INT:

86066

+ case FFI_TYPE_UINT32:

86067

+ case FFI_TYPE_SINT32:

86068

+ case FFI_TYPE_UINT16:

86069

+ case FFI_TYPE_SINT16:

86070

+ case FFI_TYPE_UINT8:

86071

+ case FFI_TYPE_SINT8:

86072

+ /* Everything else is passed as a 8-byte word in a GPR, either

86073

+ the object itself or a pointer to it. */

86074

+ intarg_count++;

86075

+ if (intarg_count > NUM_GPR_ARG_REGISTERS64)

86076

+ flags |= FLAG_ARG_NEEDS_PSAVE;

86077

+ break;

86078

+ default:

86079

+ FFI_ASSERT (0);

86080

+ }

86081

+ }

86082

+

86083

+ if (fparg_count != 0)

86084

+ flags |= FLAG_FP_ARGUMENTS;

86085

+ if (intarg_count > 4)

86086

+ flags |= FLAG_4_GPR_ARGUMENTS;

86087

+

86088

+ /* Space for the FPR registers, if needed. */

86089

+ if (fparg_count != 0)

86090

+ bytes += NUM_FPR_ARG_REGISTERS64 * sizeof (double);

86091

+

86092

+ /* Stack space. */

86093

+#if _CALL_ELF == 2

86094

+ if ((flags & FLAG_ARG_NEEDS_PSAVE) != 0)

86095

+ bytes += intarg_count * sizeof (long);

86096

+#else

86097

+ if (intarg_count > NUM_GPR_ARG_REGISTERS64)

86098

+ bytes += (intarg_count - NUM_GPR_ARG_REGISTERS64) * sizeof (long);

86099

+#endif

86100

+

86101

+ /* The stack space allocated needs to be a multiple of 16 bytes. */

86102

+ bytes = (bytes + 15) & ~0xF;

86103

+

86104

+ cif->flags = flags;

86105

+ cif->bytes = bytes;

86106

+

86107

+ return FFI_OK;

86108

+}

86109

+

86110

+ffi_status FFI_HIDDEN

86111

+ffi_prep_cif_linux64 (ffi_cif *cif)

86112

+{

86113

+ if ((cif->abi & FFI_LINUX) != 0)

86114

+ cif->nfixedargs = cif->nargs;

86115

+#if _CALL_ELF != 2

86116

+ else if (cif->abi == FFI_COMPAT_LINUX64)

86117

+ {

86118

+ /* This call is from old code. Don't touch cif->nfixedargs

86119

+ since old code will be using a smaller cif. */

86120

+ cif->flags |= FLAG_COMPAT;

86121

+ /* Translate to new abi value. */

86122

+ cif->abi = FFI_LINUX | FFI_LINUX_LONG_DOUBLE_128;

86123

+ }

86124

+#endif

86125

+ else

86126

+ return FFI_BAD_ABI;

86127

+ return ffi_prep_cif_linux64_core (cif);

86128

+}

86129

+

86130

+ffi_status FFI_HIDDEN

86131

+ffi_prep_cif_linux64_var (ffi_cif *cif,

86132

+ unsigned int nfixedargs,

86133

+ unsigned int ntotalargs MAYBE_UNUSED)

86134

+{

86135

+ if ((cif->abi & FFI_LINUX) != 0)

86136

+ cif->nfixedargs = nfixedargs;

86137

+#if _CALL_ELF != 2

86138

+ else if (cif->abi == FFI_COMPAT_LINUX64)

86139

+ {

86140

+ /* This call is from old code. Don't touch cif->nfixedargs

86141

+ since old code will be using a smaller cif. */

86142

+ cif->flags |= FLAG_COMPAT;

86143

+ /* Translate to new abi value. */

86144

+ cif->abi = FFI_LINUX | FFI_LINUX_LONG_DOUBLE_128;

86145

+ }

86146

+#endif

86147

+ else

86148

+ return FFI_BAD_ABI;

86149

+#if _CALL_ELF == 2

86150

+ cif->flags |= FLAG_ARG_NEEDS_PSAVE;

86151

+#endif

86152

+ return ffi_prep_cif_linux64_core (cif);

86153

+}

86154

+

86155

+

86156

+/* ffi_prep_args64 is called by the assembly routine once stack space

86157

+ has been allocated for the function's arguments.

86158

+

86159

+ The stack layout we want looks like this:

86160

+

86161

+ | Ret addr from ffi_call_LINUX64 8bytes | higher addresses

86162

+ |--------------------------------------------|

86163

+ | CR save area 8bytes |

86164

+ |--------------------------------------------|

86165

+ | Previous backchain pointer 8 | stack pointer here

86166

+ |--------------------------------------------|<+ <<< on entry to

86167

+ | Saved r28-r31 4*8 | | ffi_call_LINUX64

86168

+ |--------------------------------------------| |

86169

+ | GPR registers r3-r10 8*8 | |

86170

+ |--------------------------------------------| |

86171

+ | FPR registers f1-f13 (optional) 13*8 | |

86172

+ |--------------------------------------------| |

86173

+ | Parameter save area | |

86174

+ |--------------------------------------------| |

86175

+ | TOC save area 8 | |

86176

+ |--------------------------------------------| | stack |

86177

+ | Linker doubleword 8 | | grows |

86178

+ |--------------------------------------------| | down V

86179

+ | Compiler doubleword 8 | |

86180

+ |--------------------------------------------| | lower addresses

86181

+ | Space for callee's LR 8 | |

86182

+ |--------------------------------------------| |

86183

+ | CR save area 8 | |

86184

+ |--------------------------------------------| | stack pointer here

86185

+ | Current backchain pointer 8 |-/ during

86186

+ |--------------------------------------------| <<< ffi_call_LINUX64

86187

+

86188

+*/

86189

+

86190

+void FFI_HIDDEN

86191

+ffi_prep_args64 (extended_cif *ecif, unsigned long *const stack)

86192

+{

86193

+ const unsigned long bytes = ecif->cif->bytes;

86194

+ const unsigned long flags = ecif->cif->flags;

86195

+

86196

+ typedef union

86197

+ {

86198

+ char *c;

86199

+ unsigned long *ul;

86200

+ float *f;

86201

+ double *d;

86202

+ size_t p;

86203

+ } valp;

86204

+

86205

+ /* 'stacktop' points at the previous backchain pointer. */

86206

+ valp stacktop;

86207

+

86208

+ /* 'next_arg' points at the space for gpr3, and grows upwards as

86209

+ we use GPR registers, then continues at rest. */

86210

+ valp gpr_base;

86211

+ valp gpr_end;

86212

+ valp rest;

86213

+ valp next_arg;

86214

+

86215

+ /* 'fpr_base' points at the space for fpr3, and grows upwards as

86216

+ we use FPR registers. */

86217

+ valp fpr_base;

86218

+ unsigned int fparg_count;

86219

+

86220

+ unsigned int i, words, nargs, nfixedargs;

86221

+ ffi_type **ptr;

86222

+ double double_tmp;

86223

+ union

86224

+ {

86225

+ void **v;

86226

+ char **c;

86227

+ signed char **sc;

86228

+ unsigned char **uc;

86229

+ signed short **ss;

86230

+ unsigned short **us;

86231

+ signed int **si;

86232

+ unsigned int **ui;

86233

+ unsigned long **ul;

86234

+ float **f;

86235

+ double **d;

86236

+ } p_argv;

86237

+ unsigned long gprvalue;

86238

+ unsigned long align;

86239

+

86240

+ stacktop.c = (char *) stack + bytes;

86241

+ gpr_base.ul = stacktop.ul - ASM_NEEDS_REGISTERS64 - NUM_GPR_ARG_REGISTERS64;

86242

+ gpr_end.ul = gpr_base.ul + NUM_GPR_ARG_REGISTERS64;

86243

+#if _CALL_ELF == 2

86244

+ rest.ul = stack + 4 + NUM_GPR_ARG_REGISTERS64;

86245

+#else

86246

+ rest.ul = stack + 6 + NUM_GPR_ARG_REGISTERS64;

86247

+#endif

86248

+ fpr_base.d = gpr_base.d - NUM_FPR_ARG_REGISTERS64;

86249

+ fparg_count = 0;

86250

+ next_arg.ul = gpr_base.ul;

86251

+

86252

+ /* Check that everything starts aligned properly. */

86253

+ FFI_ASSERT (((unsigned long) (char *) stack & 0xF) == 0);

86254

+ FFI_ASSERT (((unsigned long) stacktop.c & 0xF) == 0);

86255

+ FFI_ASSERT ((bytes & 0xF) == 0);

86256

+

86257

+ /* Deal with return values that are actually pass-by-reference. */

86258

+ if (flags & FLAG_RETVAL_REFERENCE)

86259

+ *next_arg.ul++ = (unsigned long) (char *) ecif->rvalue;

86260

+

86261

+ /* Now for the arguments. */

86262

+ p_argv.v = ecif->avalue;

86263

+ nargs = ecif->cif->nargs;

86264

+#if _CALL_ELF != 2

86265

+ nfixedargs = (unsigned) -1;

86266

+ if ((flags & FLAG_COMPAT) == 0)

86267

+#endif

86268

+ nfixedargs = ecif->cif->nfixedargs;

86269

+ for (ptr = ecif->cif->arg_types, i = 0;

86270

+ i < nargs;

86271

+ i++, ptr++, p_argv.v++)

86272

+ {

86273

+#if _CALL_ELF == 2

86274

+ unsigned int elt, elnum;

86275

+#endif

86276

+

86277

+ switch ((*ptr)->type)

86278

+ {

86279

+#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

86280

+ case FFI_TYPE_LONGDOUBLE:

86281

+ if ((ecif->cif->abi & FFI_LINUX_LONG_DOUBLE_128) != 0)

86282

+ {

86283

+ double_tmp = (*p_argv.d)[0];

86284

+ if (fparg_count < NUM_FPR_ARG_REGISTERS64 && i < nfixedargs)

86285

+ {

86286

+ *fpr_base.d++ = double_tmp;

86287

+# if _CALL_ELF != 2

86288

+ if ((flags & FLAG_COMPAT) != 0)

86289

+ *next_arg.d = double_tmp;

86290

+# endif

86291

+ }

86292

+ else

86293

+ *next_arg.d = double_tmp;

86294

+ if (++next_arg.ul == gpr_end.ul)

86295

+ next_arg.ul = rest.ul;

86296

+ fparg_count++;

86297

+ double_tmp = (*p_argv.d)[1];

86298

+ if (fparg_count < NUM_FPR_ARG_REGISTERS64 && i < nfixedargs)

86299

+ {

86300

+ *fpr_base.d++ = double_tmp;

86301

+# if _CALL_ELF != 2

86302

+ if ((flags & FLAG_COMPAT) != 0)

86303

+ *next_arg.d = double_tmp;

86304

+# endif

86305

+ }

86306

+ else

86307

+ *next_arg.d = double_tmp;

86308

+ if (++next_arg.ul == gpr_end.ul)

86309

+ next_arg.ul = rest.ul;

86310

+ fparg_count++;

86311

+ FFI_ASSERT (__LDBL_MANT_DIG__ == 106);

86312

+ FFI_ASSERT (flags & FLAG_FP_ARGUMENTS);

86313

+ break;

86314

+ }

86315

+ /* Fall through. */

86316

+#endif

86317

+ case FFI_TYPE_DOUBLE:

86318

+ double_tmp = **p_argv.d;

86319

+ if (fparg_count < NUM_FPR_ARG_REGISTERS64 && i < nfixedargs)

86320

+ {

86321

+ *fpr_base.d++ = double_tmp;

86322

+#if _CALL_ELF != 2

86323

+ if ((flags & FLAG_COMPAT) != 0)

86324

+ *next_arg.d = double_tmp;

86325

+#endif

86326

+ }

86327

+ else

86328

+ *next_arg.d = double_tmp;

86329

+ if (++next_arg.ul == gpr_end.ul)

86330

+ next_arg.ul = rest.ul;

86331

+ fparg_count++;

86332

+ FFI_ASSERT (flags & FLAG_FP_ARGUMENTS);

86333

+ break;

86334

+

86335

+ case FFI_TYPE_FLOAT:

86336

+ double_tmp = **p_argv.f;

86337

+ if (fparg_count < NUM_FPR_ARG_REGISTERS64 && i < nfixedargs)

86338

+ {

86339

+ *fpr_base.d++ = double_tmp;

86340

+#if _CALL_ELF != 2

86341

+ if ((flags & FLAG_COMPAT) != 0)

86342

+ *next_arg.f = (float) double_tmp;

86343

+#endif

86344

+ }

86345

+ else

86346

+ *next_arg.f = (float) double_tmp;

86347

+ if (++next_arg.ul == gpr_end.ul)

86348

+ next_arg.ul = rest.ul;

86349

+ fparg_count++;

86350

+ FFI_ASSERT (flags & FLAG_FP_ARGUMENTS);

86351

+ break;

86352

+

86353

+ case FFI_TYPE_STRUCT:

86354

+ if ((ecif->cif->abi & FFI_LINUX_STRUCT_ALIGN) != 0)

86355

+ {

86356

+ align = (*ptr)->alignment;

86357

+ if (align > 16)

86358

+ align = 16;

86359

+ if (align > 1)

86360

+ next_arg.p = ALIGN (next_arg.p, align);

86361

+ }

86362

+#if _CALL_ELF == 2

86363

+ elt = discover_homogeneous_aggregate (*ptr, &elnum);

86364

+ if (elt)

86365

+ {

86366

+ union {

86367

+ void *v;

86368

+ float *f;

86369

+ double *d;

86370

+ } arg;

86371

+

86372

+ arg.v = *p_argv.v;

86373

+ if (elt == FFI_TYPE_FLOAT)

86374

+ {

86375

+ do

86376

+ {

86377

+ double_tmp = *arg.f++;

86378

+ if (fparg_count < NUM_FPR_ARG_REGISTERS64

86379

+ && i < nfixedargs)

86380

+ *fpr_base.d++ = double_tmp;

86381

+ else

86382

+ *next_arg.f = (float) double_tmp;

86383

+ if (++next_arg.f == gpr_end.f)

86384

+ next_arg.f = rest.f;

86385

+ fparg_count++;

86386

+ }

86387

+ while (--elnum != 0);

86388

+ if ((next_arg.p & 3) != 0)

86389

+ {

86390

+ if (++next_arg.f == gpr_end.f)

86391

+ next_arg.f = rest.f;

86392

+ }

86393

+ }

86394

+ else

86395

+ do

86396

+ {

86397

+ double_tmp = *arg.d++;

86398

+ if (fparg_count < NUM_FPR_ARG_REGISTERS64 && i < nfixedargs)

86399

+ *fpr_base.d++ = double_tmp;

86400

+ else

86401

+ *next_arg.d = double_tmp;

86402

+ if (++next_arg.d == gpr_end.d)

86403

+ next_arg.d = rest.d;

86404

+ fparg_count++;

86405

+ }

86406

+ while (--elnum != 0);

86407

+ }

86408

+ else

86409

+#endif

86410

+ {

86411

+ words = ((*ptr)->size + 7) / 8;

86412

+ if (next_arg.ul >= gpr_base.ul && next_arg.ul + words > gpr_end.ul)

86413

+ {

86414

+ size_t first = gpr_end.c - next_arg.c;

86415

+ memcpy (next_arg.c, *p_argv.c, first);

86416

+ memcpy (rest.c, *p_argv.c + first, (*ptr)->size - first);

86417

+ next_arg.c = rest.c + words * 8 - first;

86418

+ }

86419

+ else

86420

+ {

86421

+ char *where = next_arg.c;

86422

+

86423

+#ifndef __LITTLE_ENDIAN__

86424

+ /* Structures with size less than eight bytes are passed

86425

+ left-padded. */

86426

+ if ((*ptr)->size < 8)

86427

+ where += 8 - (*ptr)->size;

86428

+#endif

86429

+ memcpy (where, *p_argv.c, (*ptr)->size);

86430

+ next_arg.ul += words;

86431

+ if (next_arg.ul == gpr_end.ul)

86432

+ next_arg.ul = rest.ul;

86433

+ }

86434

+ }

86435

+ break;

86436

+

86437

+ case FFI_TYPE_UINT8:

86438

+ gprvalue = **p_argv.uc;

86439

+ goto putgpr;

86440

+ case FFI_TYPE_SINT8:

86441

+ gprvalue = **p_argv.sc;

86442

+ goto putgpr;

86443

+ case FFI_TYPE_UINT16:

86444

+ gprvalue = **p_argv.us;

86445

+ goto putgpr;

86446

+ case FFI_TYPE_SINT16:

86447

+ gprvalue = **p_argv.ss;

86448

+ goto putgpr;

86449

+ case FFI_TYPE_UINT32:

86450

+ gprvalue = **p_argv.ui;

86451

+ goto putgpr;

86452

+ case FFI_TYPE_INT:

86453

+ case FFI_TYPE_SINT32:

86454

+ gprvalue = **p_argv.si;

86455

+ goto putgpr;

86456

+

86457

+ case FFI_TYPE_UINT64:

86458

+ case FFI_TYPE_SINT64:

86459

+ case FFI_TYPE_POINTER:

86460

+ gprvalue = **p_argv.ul;

86461

+ putgpr:

86462

+ *next_arg.ul++ = gprvalue;

86463

+ if (next_arg.ul == gpr_end.ul)

86464

+ next_arg.ul = rest.ul;

86465

+ break;

86466

+ }

86467

+ }

86468

+

86469

+ FFI_ASSERT (flags & FLAG_4_GPR_ARGUMENTS

86470

+ || (next_arg.ul >= gpr_base.ul

86471

+ && next_arg.ul <= gpr_base.ul + 4));

86472

+}

86473

+

86474

+

86475

+#if _CALL_ELF == 2

86476

+#define MIN_CACHE_LINE_SIZE 8

86477

+

86478

+static void

86479

+flush_icache (char *wraddr, char *xaddr, int size)

86480

+{

86481

+ int i;

86482

+ for (i = 0; i < size; i += MIN_CACHE_LINE_SIZE)

86483

+ __asm__ volatile ("icbi 0,%0;" "dcbf 0,%1;"

86484

+ : : "r" (xaddr + i), "r" (wraddr + i) : "memory");

86485

+ __asm__ volatile ("icbi 0,%0;" "dcbf 0,%1;" "sync;" "isync;"

86486

+ : : "r"(xaddr + size - 1), "r"(wraddr + size - 1)

86487

+ : "memory");

86488

+}

86489

+#endif

86490

+

86491

+ffi_status

86492

+ffi_prep_closure_loc_linux64 (ffi_closure *closure,

86493

+ ffi_cif *cif,

86494

+ void (*fun) (ffi_cif *, void *, void **, void *),

86495

+ void *user_data,

86496

+ void *codeloc)

86497

+{

86498

+#if _CALL_ELF == 2

86499

+ unsigned int *tramp = (unsigned int *) &closure->tramp[0];

86500

+

86501

+ if (cif->abi < FFI_LINUX || cif->abi >= FFI_LAST_ABI)

86502

+ return FFI_BAD_ABI;

86503

+

86504

+ tramp[0] = 0xe96c0018; /* 0: ld 11,2f-0b(12) */

86505

+ tramp[1] = 0xe98c0010; /* ld 12,1f-0b(12) */

86506

+ tramp[2] = 0x7d8903a6; /* mtctr 12 */

86507

+ tramp[3] = 0x4e800420; /* bctr */

86508

+ /* 1: .quad function_addr */

86509

+ /* 2: .quad context */

86510

+ *(void **) &tramp[4] = (void *) ffi_closure_LINUX64;

86511

+ *(void **) &tramp[6] = codeloc;

86512

+ flush_icache ((char *)tramp, (char *)codeloc, FFI_TRAMPOLINE_SIZE);

86513

+#else

86514

+ void **tramp = (void **) &closure->tramp[0];

86515

+

86516

+ if (cif->abi < FFI_LINUX || cif->abi >= FFI_LAST_ABI)

86517

+ return FFI_BAD_ABI;

86518

+

86519

+ /* Copy function address and TOC from ffi_closure_LINUX64. */

86520

+ memcpy (tramp, (char *) ffi_closure_LINUX64, 16);

86521

+ tramp[2] = codeloc;

86522

+#endif

86523

+

86524

+ closure->cif = cif;

86525

+ closure->fun = fun;

86526

+ closure->user_data = user_data;

86527

+

86528

+ return FFI_OK;

86529

+}

86530

+

86531

+

86532

+int FFI_HIDDEN

86533

+ffi_closure_helper_LINUX64 (ffi_closure *closure, void *rvalue,

86534

+ unsigned long *pst, ffi_dblfl *pfr)

86535

+{

86536

+ /* rvalue is the pointer to space for return value in closure assembly */

86537

+ /* pst is the pointer to parameter save area

86538

+ (r3-r10 are stored into its first 8 slots by ffi_closure_LINUX64) */

86539

+ /* pfr is the pointer to where f1-f13 are stored in ffi_closure_LINUX64 */

86540

+

86541

+ void **avalue;

86542

+ ffi_type **arg_types;

86543

+ unsigned long i, avn, nfixedargs;

86544

+ ffi_cif *cif;

86545

+ ffi_dblfl *end_pfr = pfr + NUM_FPR_ARG_REGISTERS64;

86546

+ unsigned long align;

86547

+

86548

+ cif = closure->cif;

86549

+ avalue = alloca (cif->nargs * sizeof (void *));

86550

+

86551

+ /* Copy the caller's structure return value address so that the

86552

+ closure returns the data directly to the caller. */

86553

+ if (cif->rtype->type == FFI_TYPE_STRUCT

86554

+ && (cif->flags & FLAG_RETURNS_SMST) == 0)

86555

+ {

86556

+ rvalue = (void *) *pst;

86557

+ pst++;

86558

+ }

86559

+

86560

+ i = 0;

86561

+ avn = cif->nargs;

86562

+#if _CALL_ELF != 2

86563

+ nfixedargs = (unsigned) -1;

86564

+ if ((cif->flags & FLAG_COMPAT) == 0)

86565

+#endif

86566

+ nfixedargs = cif->nfixedargs;

86567

+ arg_types = cif->arg_types;

86568

+

86569

+ /* Grab the addresses of the arguments from the stack frame. */

86570

+ while (i < avn)

86571

+ {

86572

+ unsigned int elt, elnum;

86573

+

86574

+ switch (arg_types[i]->type)

86575

+ {

86576

+ case FFI_TYPE_SINT8:

86577

+ case FFI_TYPE_UINT8:

86578

+#ifndef __LITTLE_ENDIAN__

86579

+ avalue[i] = (char *) pst + 7;

86580

+ pst++;

86581

+ break;

86582

+#endif

86583

+

86584

+ case FFI_TYPE_SINT16:

86585

+ case FFI_TYPE_UINT16:

86586

+#ifndef __LITTLE_ENDIAN__

86587

+ avalue[i] = (char *) pst + 6;

86588

+ pst++;

86589

+ break;

86590

+#endif

86591

+

86592

+ case FFI_TYPE_SINT32:

86593

+ case FFI_TYPE_UINT32:

86594

+#ifndef __LITTLE_ENDIAN__

86595

+ avalue[i] = (char *) pst + 4;

86596

+ pst++;

86597

+ break;

86598

+#endif

86599

+

86600

+ case FFI_TYPE_SINT64:

86601

+ case FFI_TYPE_UINT64:

86602

+ case FFI_TYPE_POINTER:

86603

+ avalue[i] = pst;

86604

+ pst++;

86605

+ break;

86606

+

86607

+ case FFI_TYPE_STRUCT:

86608

+ if ((cif->abi & FFI_LINUX_STRUCT_ALIGN) != 0)

86609

+ {

86610

+ align = arg_types[i]->alignment;

86611

+ if (align > 16)

86612

+ align = 16;

86613

+ if (align > 1)

86614

+ pst = (unsigned long *) ALIGN ((size_t) pst, align);

86615

+ }

86616

+ elt = 0;

86617

+#if _CALL_ELF == 2

86618

+ elt = discover_homogeneous_aggregate (arg_types[i], &elnum);

86619

+#endif

86620

+ if (elt)

86621

+ {

86622

+ union {

86623

+ void *v;

86624

+ unsigned long *ul;

86625

+ float *f;

86626

+ double *d;

86627

+ size_t p;

86628

+ } to, from;

86629

+

86630

+ /* Repackage the aggregate from its parts. The

86631

+ aggregate size is not greater than the space taken by

86632

+ the registers so store back to the register/parameter

86633

+ save arrays. */

86634

+ if (pfr + elnum <= end_pfr)

86635

+ to.v = pfr;

86636

+ else

86637

+ to.v = pst;

86638

+

86639

+ avalue[i] = to.v;

86640

+ from.ul = pst;

86641

+ if (elt == FFI_TYPE_FLOAT)

86642

+ {

86643

+ do

86644

+ {

86645

+ if (pfr < end_pfr && i < nfixedargs)

86646

+ {

86647

+ *to.f = (float) pfr->d;

86648

+ pfr++;

86649

+ }

86650

+ else

86651

+ *to.f = *from.f;

86652

+ to.f++;

86653

+ from.f++;

86654

+ }

86655

+ while (--elnum != 0);

86656

+ }

86657

+ else

86658

+ {

86659

+ do

86660

+ {

86661

+ if (pfr < end_pfr && i < nfixedargs)

86662

+ {

86663

+ *to.d = pfr->d;

86664

+ pfr++;

86665

+ }

86666

+ else

86667

+ *to.d = *from.d;

86668

+ to.d++;

86669

+ from.d++;

86670

+ }

86671

+ while (--elnum != 0);

86672

+ }

86673

+ }

86674

+ else

86675

+ {

86676

+#ifndef __LITTLE_ENDIAN__

86677

+ /* Structures with size less than eight bytes are passed

86678

+ left-padded. */

86679

+ if (arg_types[i]->size < 8)

86680

+ avalue[i] = (char *) pst + 8 - arg_types[i]->size;

86681

+ else

86682

+#endif

86683

+ avalue[i] = pst;

86684

+ }

86685

+ pst += (arg_types[i]->size + 7) / 8;

86686

+ break;

86687

+

86688

+#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

86689

+ case FFI_TYPE_LONGDOUBLE:

86690

+ if ((cif->abi & FFI_LINUX_LONG_DOUBLE_128) != 0)

86691

+ {

86692

+ if (pfr + 1 < end_pfr && i + 1 < nfixedargs)

86693

+ {

86694

+ avalue[i] = pfr;

86695

+ pfr += 2;

86696

+ }

86697

+ else

86698

+ {

86699

+ if (pfr < end_pfr && i < nfixedargs)

86700

+ {

86701

+ /* Passed partly in f13 and partly on the stack.

86702

+ Move it all to the stack. */

86703

+ *pst = *(unsigned long *) pfr;

86704

+ pfr++;

86705

+ }

86706

+ avalue[i] = pst;

86707

+ }

86708

+ pst += 2;

86709

+ break;

86710

+ }

86711

+ /* Fall through. */

86712

+#endif

86713

+ case FFI_TYPE_DOUBLE:

86714

+ /* On the outgoing stack all values are aligned to 8 */

86715

+ /* there are 13 64bit floating point registers */

86716

+

86717

+ if (pfr < end_pfr && i < nfixedargs)

86718

+ {

86719

+ avalue[i] = pfr;

86720

+ pfr++;

86721

+ }

86722

+ else

86723

+ avalue[i] = pst;

86724

+ pst++;

86725

+ break;

86726

+

86727

+ case FFI_TYPE_FLOAT:

86728

+ if (pfr < end_pfr && i < nfixedargs)

86729

+ {

86730

+ /* Float values are stored as doubles in the

86731

+ ffi_closure_LINUX64 code. Fix them here. */

86732

+ pfr->f = (float) pfr->d;

86733

+ avalue[i] = pfr;

86734

+ pfr++;

86735

+ }

86736

+ else

86737

+ avalue[i] = pst;

86738

+ pst++;

86739

+ break;

86740

+

86741

+ default:

86742

+ FFI_ASSERT (0);

86743

+ }

86744

+

86745

+ i++;

86746

+ }

86747

+

86748

+

86749

+ (closure->fun) (cif, rvalue, avalue, closure->user_data);

86750

+

86751

+ /* Tell ffi_closure_LINUX64 how to perform return type promotions. */

86752

+ if ((cif->flags & FLAG_RETURNS_SMST) != 0)

86753

+ {

86754

+ if ((cif->flags & FLAG_RETURNS_FP) == 0)

86755

+ return FFI_V2_TYPE_SMALL_STRUCT + cif->rtype->size - 1;

86756

+ else if ((cif->flags & FLAG_RETURNS_64BITS) != 0)

86757

+ return FFI_V2_TYPE_DOUBLE_HOMOG;

86758

+ else

86759

+ return FFI_V2_TYPE_FLOAT_HOMOG;

86760

+ }

86761

+ return cif->rtype->type;

86762

+}

86763

+#endif

86764

Index: libffi/src/types.c

86765

===================================================================

86766

--- a/src/libffi/src/types.c (.../tags/gcc_4_8_2_release)

86767

+++ b/src/libffi/src/types.c (.../branches/gcc-4_8-branch)

86768

@@ -44,6 +44,17 @@

86769

id, NULL \

86770

}

86771

86772

+#define FFI_NONCONST_TYPEDEF(name, type, id) \

86773

+struct struct_align_##name { \

86774

+ char c; \

86775

+ type x; \

86776

+}; \

86777

+ffi_type ffi_type_##name = { \

86778

+ sizeof(type), \

86779

+ offsetof(struct struct_align_##name, x), \

86780

+ id, NULL \

86781

+}

86782

+

86783

/* Size and alignment are fake here. They must not be 0. */

86784

const ffi_type ffi_type_void = {

86785

1, 1, FFI_TYPE_VOID, NULL

86786

@@ -73,5 +84,9 @@

86787

# endif

86788

const ffi_type ffi_type_longdouble = { 16, 16, 4, NULL };

86789

#elif FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

86790

+# if HAVE_LONG_DOUBLE_VARIANT

86791

+FFI_NONCONST_TYPEDEF(longdouble, long double, FFI_TYPE_LONGDOUBLE);

86792

+# else

86793

FFI_TYPEDEF(longdouble, long double, FFI_TYPE_LONGDOUBLE);

86794

+# endif

86795

#endif

86796

Index: libffi/src/prep_cif.c

86797

===================================================================

86798

--- a/src/libffi/src/prep_cif.c (.../tags/gcc_4_8_2_release)

86799

+++ b/src/libffi/src/prep_cif.c (.../branches/gcc-4_8-branch)

86800

@@ -126,6 +126,10 @@

86801

86802

cif->flags = 0;

86803

86804

+#if HAVE_LONG_DOUBLE_VARIANT

86805

+ ffi_prep_types (abi);

86806

+#endif

86807

+

86808

/* Initialize the return type if necessary */

86809

if ((cif->rtype->size == 0) && (initialize_aggregate(cif->rtype) != FFI_OK))

86810

return FFI_BAD_TYPEDEF;

86811

Index: libffi/ChangeLog

86812

===================================================================

86813

--- a/src/libffi/ChangeLog (.../tags/gcc_4_8_2_release)

86814

+++ b/src/libffi/ChangeLog (.../branches/gcc-4_8-branch)

86815

@@ -1,3 +1,39 @@

86816

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

86817

+

86818

+ Backport mainline r205844.

86819

+ 2013-11-18 Alan Modra <amodra@gmail.com>

86820

+ * src/powerpc/ffitarget.h: Import from upstream.

86821

+ * src/powerpc/ffi_powerpc.h: Likewise.

86822

+ * src/powerpc/ffi.c: Likewise.

86823

+ * src/powerpc/ffi_sysv.c: Likewise.

86824

+ * src/powerpc/ffi_linux64.c: Likewise.

86825

+ * src/powerpc/sysv.S: Likewise.

86826

+ * src/powerpc/ppc_closure.S: Likewise.

86827

+ * src/powerpc/linux64.S: Likewise.

86828

+ * src/powerpc/linux64_closure.S: Likewise.

86829

+ * src/types.c: Likewise.

86830

+ * Makefile.am (EXTRA_DIST): Add new src/powerpc files.

86831

+ (nodist_libffi_la_SOURCES <POWERPC, POWERPC_FREEBSD>): Likewise.

86832

+ * configure.ac (HAVE_LONG_DOUBLE_VARIANT): Define for powerpc.

86833

+ * include/ffi.h.in (ffi_prep_types): Declare.

86834

+ * src/prep_cif.c (ffi_prep_cif_core): Call ffi_prep_types.

86835

+ * configure: Regenerate.

86836

+ * fficonfig.h.in: Regenerate.

86837

+ * Makefile.in: Regenerate.

86838

+ * man/Makefile.in: Regenerate.

86839

+ * include/Makefile.in: Regenerate.

86840

+ * testsuite/Makefile.in: Regenerate.

86841

+

86842

+ * src/powerpc/ppc_closure.S: Don't bl .Luint128.

86843

+

86844

+ * src/powerpc/ffitarget.h: Import from upstream.

86845

+ * src/powerpc/ffi.c: Likewise.

86846

+ * src/powerpc/linux64.S: Likewise.

86847

+ * src/powerpc/linux64_closure.S: Likewise.

86848

+ * doc/libffi.texi: Likewise.

86849

+ * testsuite/libffi.call/cls_double_va.c: Likewise.

86850

+ * testsuite/libffi.call/cls_longdouble_va.c: Likewise.

86851

+

86852

2013-10-16 Release Manager

86853

86854

* GCC 4.8.2 released.

86855

Index: libffi/testsuite/Makefile.in

86856

===================================================================

86857

--- a/src/libffi/testsuite/Makefile.in (.../tags/gcc_4_8_2_release)

86858

+++ b/src/libffi/testsuite/Makefile.in (.../branches/gcc-4_8-branch)

86859

@@ -88,6 +88,7 @@

86860

FGREP = @FGREP@

86861

GREP = @GREP@

86862

HAVE_LONG_DOUBLE = @HAVE_LONG_DOUBLE@

86863

+HAVE_LONG_DOUBLE_VARIANT = @HAVE_LONG_DOUBLE_VARIANT@

86864

INSTALL = @INSTALL@

86865

INSTALL_DATA = @INSTALL_DATA@

86866

INSTALL_PROGRAM = @INSTALL_PROGRAM@

86867

Index: libffi/testsuite/libffi.call/cls_double_va.c

86868

===================================================================

86869

--- a/src/libffi/testsuite/libffi.call/cls_double_va.c (.../tags/gcc_4_8_2_release)

86870

+++ b/src/libffi/testsuite/libffi.call/cls_double_va.c (.../branches/gcc-4_8-branch)

86871

@@ -38,7 +38,7 @@

86872

86873

/* This printf call is variadic */

86874

CHECK(ffi_prep_cif_var(&cif, FFI_DEFAULT_ABI, 1, 2, &ffi_type_sint,

86875

- arg_types) == FFI_OK);

86876

+ arg_types) == FFI_OK);

86877

86878

args[0] = &format;

86879

args[1] = &doubleArg;

86880

@@ -45,19 +45,17 @@

86881

args[2] = NULL;

86882

86883

ffi_call(&cif, FFI_FN(printf), &res, args);

86884

- // { dg-output "7.0" }

86885

+ /* { dg-output "7.0" } */

86886

printf("res: %d\n", (int) res);

86887

- // { dg-output "\nres: 4" }

86888

+ /* { dg-output "\nres: 4" } */

86889

86890

- /* The call to cls_double_va_fn is static, so have to use a normal prep_cif */

86891

- CHECK(ffi_prep_cif(&cif, FFI_DEFAULT_ABI, 2, &ffi_type_sint, arg_types) == FFI_OK);

86892

+ CHECK(ffi_prep_closure_loc(pcl, &cif, cls_double_va_fn, NULL,

86893

+ code) == FFI_OK);

86894

86895

- CHECK(ffi_prep_closure_loc(pcl, &cif, cls_double_va_fn, NULL, code) == FFI_OK);

86896

-

86897

- res = ((int(*)(char*, double))(code))(format, doubleArg);

86898

- // { dg-output "\n7.0" }

86899

+ res = ((int(*)(char*, ...))(code))(format, doubleArg);

86900

+ /* { dg-output "\n7.0" } */

86901

printf("res: %d\n", (int) res);

86902

- // { dg-output "\nres: 4" }

86903

+ /* { dg-output "\nres: 4" } */

86904

86905

exit(0);

86906

}

86907

Index: libffi/testsuite/libffi.call/cls_longdouble_va.c

86908

===================================================================

86909

--- a/src/libffi/testsuite/libffi.call/cls_longdouble_va.c (.../tags/gcc_4_8_2_release)

86910

+++ b/src/libffi/testsuite/libffi.call/cls_longdouble_va.c (.../branches/gcc-4_8-branch)

86911

@@ -38,7 +38,7 @@

86912

86913

/* This printf call is variadic */

86914

CHECK(ffi_prep_cif_var(&cif, FFI_DEFAULT_ABI, 1, 2, &ffi_type_sint,

86915

- arg_types) == FFI_OK);

86916

+ arg_types) == FFI_OK);

86917

86918

args[0] = &format;

86919

args[1] = &ldArg;

86920

@@ -45,20 +45,17 @@

86921

args[2] = NULL;

86922

86923

ffi_call(&cif, FFI_FN(printf), &res, args);

86924

- // { dg-output "7.0" }

86925

+ /* { dg-output "7.0" } */

86926

printf("res: %d\n", (int) res);

86927

- // { dg-output "\nres: 4" }

86928

+ /* { dg-output "\nres: 4" } */

86929

86930

- /* The call to cls_longdouble_va_fn is static, so have to use a normal prep_cif */

86931

- CHECK(ffi_prep_cif(&cif, FFI_DEFAULT_ABI, 2, &ffi_type_sint,

86932

- arg_types) == FFI_OK);

86933

+ CHECK(ffi_prep_closure_loc(pcl, &cif, cls_longdouble_va_fn, NULL,

86934

+ code) == FFI_OK);

86935

86936

- CHECK(ffi_prep_closure_loc(pcl, &cif, cls_longdouble_va_fn, NULL, code) == FFI_OK);

86937

-

86938

- res = ((int(*)(char*, long double))(code))(format, ldArg);

86939

- // { dg-output "\n7.0" }

86940

+ res = ((int(*)(char*, ...))(code))(format, ldArg);

86941

+ /* { dg-output "\n7.0" } */

86942

printf("res: %d\n", (int) res);

86943

- // { dg-output "\nres: 4" }

86944

+ /* { dg-output "\nres: 4" } */

86945

86946

exit(0);

86947

}

86948

Index: libffi/configure.ac

86949

===================================================================

86950

--- a/src/libffi/configure.ac (.../tags/gcc_4_8_2_release)

86951

+++ b/src/libffi/configure.ac (.../branches/gcc-4_8-branch)

86952

@@ -65,6 +65,7 @@

86953

AM_CONDITIONAL(TESTSUBDIR, test -d $srcdir/testsuite)

86954

86955

TARGETDIR="unknown"

86956

+HAVE_LONG_DOUBLE_VARIANT=0

86957

case "$host" in

86958

aarch64*-*-*)

86959

TARGET=AARCH64; TARGETDIR=aarch64

86960

@@ -162,6 +163,7 @@

86961

86962

powerpc*-*-linux* | powerpc-*-sysv*)

86963

TARGET=POWERPC; TARGETDIR=powerpc

86964

+ HAVE_LONG_DOUBLE_VARIANT=1

86965

;;

86966

powerpc-*-amigaos*)

86967

TARGET=POWERPC; TARGETDIR=powerpc

86968

@@ -177,6 +179,7 @@

86969

;;

86970

powerpc-*-freebsd* | powerpc-*-openbsd*)

86971

TARGET=POWERPC_FREEBSD; TARGETDIR=powerpc

86972

+ HAVE_LONG_DOUBLE_VARIANT=1

86973

;;

86974

powerpc64-*-freebsd*)

86975

TARGET=POWERPC; TARGETDIR=powerpc

86976

@@ -273,14 +276,20 @@

86977

# Also AC_SUBST this variable for ffi.h.

86978

if test -z "$HAVE_LONG_DOUBLE"; then

86979

HAVE_LONG_DOUBLE=0

86980

- if test $ac_cv_sizeof_double != $ac_cv_sizeof_long_double; then

86981

- if test $ac_cv_sizeof_long_double != 0; then

86982

+ if test $ac_cv_sizeof_long_double != 0; then

86983

+ if test $HAVE_LONG_DOUBLE_VARIANT != 0; then

86984

+ AC_DEFINE(HAVE_LONG_DOUBLE_VARIANT, 1, [Define if you support more than one size of the long double type])

86985

HAVE_LONG_DOUBLE=1

86986

- AC_DEFINE(HAVE_LONG_DOUBLE, 1, [Define if you have the long double type and it is bigger than a double])

86987

+ else

86988

+ if test $ac_cv_sizeof_double != $ac_cv_sizeof_long_double; then

86989

+ HAVE_LONG_DOUBLE=1

86990

+ AC_DEFINE(HAVE_LONG_DOUBLE, 1, [Define if you have the long double type and it is bigger than a double])

86991

+ fi

86992

fi

86993

fi

86994

fi

86995

AC_SUBST(HAVE_LONG_DOUBLE)

86996

+AC_SUBST(HAVE_LONG_DOUBLE_VARIANT)

86997

86998

AC_C_BIGENDIAN

86999

87000

Index: libffi/Makefile.am

87001

===================================================================

87002

--- a/src/libffi/Makefile.am (.../tags/gcc_4_8_2_release)

87003

+++ b/src/libffi/Makefile.am (.../branches/gcc-4_8-branch)

87004

@@ -15,10 +15,12 @@

87005

src/ia64/unix.S src/mips/ffi.c src/mips/n32.S src/mips/o32.S \

87006

src/mips/ffitarget.h src/m32r/ffi.c src/m32r/sysv.S \

87007

src/m32r/ffitarget.h src/m68k/ffi.c src/m68k/sysv.S \

87008

- src/m68k/ffitarget.h src/powerpc/ffi.c src/powerpc/sysv.S \

87009

- src/powerpc/linux64.S src/powerpc/linux64_closure.S \

87010

- src/powerpc/ppc_closure.S src/powerpc/asm.h \

87011

- src/powerpc/aix.S src/powerpc/darwin.S \

87012

+ src/m68k/ffitarget.h \

87013

+ src/powerpc/ffi.c src/powerpc/ffi_powerpc.h \

87014

+ src/powerpc/ffi_sysv.c src/powerpc/ffi_linux64.c \

87015

+ src/powerpc/sysv.S src/powerpc/linux64.S \

87016

+ src/powerpc/linux64_closure.S src/powerpc/ppc_closure.S \

87017

+ src/powerpc/asm.h src/powerpc/aix.S src/powerpc/darwin.S \

87018

src/powerpc/aix_closure.S src/powerpc/darwin_closure.S \

87019

src/powerpc/ffi_darwin.c src/powerpc/ffitarget.h \

87020

src/s390/ffi.c src/s390/sysv.S src/s390/ffitarget.h \

87021

@@ -179,7 +181,7 @@

87022

nodist_libffi_la_SOURCES += src/m68k/ffi.c src/m68k/sysv.S

87023

endif

87024

if POWERPC

87025

-nodist_libffi_la_SOURCES += src/powerpc/ffi.c src/powerpc/sysv.S src/powerpc/ppc_closure.S src/powerpc/linux64.S src/powerpc/linux64_closure.S

87026

+nodist_libffi_la_SOURCES += src/powerpc/ffi.c src/powerpc/ffi_sysv.c src/powerpc/ffi_linux64.c src/powerpc/sysv.S src/powerpc/ppc_closure.S src/powerpc/linux64.S src/powerpc/linux64_closure.S

87027

endif

87028

if POWERPC_AIX

87029

nodist_libffi_la_SOURCES += src/powerpc/ffi_darwin.c src/powerpc/aix.S src/powerpc/aix_closure.S

87030

@@ -188,7 +190,7 @@

87031

nodist_libffi_la_SOURCES += src/powerpc/ffi_darwin.c src/powerpc/darwin.S src/powerpc/darwin_closure.S

87032

endif

87033

if POWERPC_FREEBSD

87034

-nodist_libffi_la_SOURCES += src/powerpc/ffi.c src/powerpc/sysv.S src/powerpc/ppc_closure.S

87035

+nodist_libffi_la_SOURCES += src/powerpc/ffi.c src/powerpc/ffi_sysv.c src/powerpc/sysv.S src/powerpc/ppc_closure.S

87036

endif

87037

if AARCH64

87038

nodist_libffi_la_SOURCES += src/aarch64/sysv.S src/aarch64/ffi.c

87039

Index: libffi/man/Makefile.in

87040

===================================================================

87041

--- a/src/libffi/man/Makefile.in (.../tags/gcc_4_8_2_release)

87042

+++ b/src/libffi/man/Makefile.in (.../branches/gcc-4_8-branch)

87043

@@ -111,6 +111,7 @@

87044

FGREP = @FGREP@

87045

GREP = @GREP@

87046

HAVE_LONG_DOUBLE = @HAVE_LONG_DOUBLE@

87047

+HAVE_LONG_DOUBLE_VARIANT = @HAVE_LONG_DOUBLE_VARIANT@

87048

INSTALL = @INSTALL@

87049

INSTALL_DATA = @INSTALL_DATA@

87050

INSTALL_PROGRAM = @INSTALL_PROGRAM@

87051

Index: libssp/configure

87052

===================================================================

87053

--- a/src/libssp/configure (.../tags/gcc_4_8_2_release)

87054

+++ b/src/libssp/configure (.../branches/gcc-4_8-branch)

87055

@@ -6385,7 +6385,7 @@

87056

rm -rf conftest*

87057

;;

87058

87059

-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \

87060

+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \

87061

s390*-*linux*|s390*-*tpf*|sparc*-*linux*)

87062

# Find out which ABI we are using.

87063

echo 'int i;' > conftest.$ac_ext

87064

@@ -6410,7 +6410,10 @@

87065

;;

87066

esac

87067

;;

87068

- ppc64-*linux*|powerpc64-*linux*)

87069

+ powerpc64le-*linux*)

87070

+ LD="${LD-ld} -m elf32lppclinux"

87071

+ ;;

87072

+ powerpc64-*linux*)

87073

LD="${LD-ld} -m elf32ppclinux"

87074

;;

87075

s390x-*linux*)

87076

@@ -6429,7 +6432,10 @@

87077

x86_64-*linux*)

87078

LD="${LD-ld} -m elf_x86_64"

87079

;;

87080

- ppc*-*linux*|powerpc*-*linux*)

87081

+ powerpcle-*linux*)

87082

+ LD="${LD-ld} -m elf64lppc"

87083

+ ;;

87084

+ powerpc-*linux*)

87085

LD="${LD-ld} -m elf64ppc"

87086

;;

87087

s390*-*linux*|s390*-*tpf*)

87088

@@ -10658,7 +10664,7 @@

87089

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

87090

lt_status=$lt_dlunknown

87091

cat > conftest.$ac_ext <<_LT_EOF

87092

-#line 10661 "configure"

87093

+#line 10667 "configure"

87094

#include "confdefs.h"

87095

87096

#if HAVE_DLFCN_H

87097

@@ -10764,7 +10770,7 @@

87098

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

87099

lt_status=$lt_dlunknown

87100

cat > conftest.$ac_ext <<_LT_EOF

87101

-#line 10767 "configure"

87102

+#line 10773 "configure"

87103

#include "confdefs.h"

87104

87105

#if HAVE_DLFCN_H

87106

Index: libssp/ChangeLog

87107

===================================================================

87108

--- a/src/libssp/ChangeLog (.../tags/gcc_4_8_2_release)

87109

+++ b/src/libssp/ChangeLog (.../branches/gcc-4_8-branch)

87110

@@ -1,3 +1,10 @@

87111

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

87112

+

87113

+ Backport from mainline

87114

+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

87115

+

87116

+ * configure: Regenerate.

87117

+

87118

2013-10-16 Release Manager

87119

87120

* GCC 4.8.2 released.

87121

Index: libcpp/macro.c

87122

===================================================================

87123

--- a/src/libcpp/macro.c (.../tags/gcc_4_8_2_release)

87124

+++ b/src/libcpp/macro.c (.../branches/gcc-4_8-branch)

87125

@@ -1108,21 +1108,22 @@

87126

87127

if (macro->paramc == 0)

87128

{

87129

+ unsigned tokens_count = macro_real_token_count (macro);

87130

if (CPP_OPTION (pfile, track_macro_expansion))

87131

{

87132

- unsigned int i, count = macro->count;

87133

+ unsigned int i;

87134

const cpp_token *src = macro->exp.tokens;

87135

const struct line_map *map;

87136

source_location *virt_locs = NULL;

87137

- _cpp_buff *macro_tokens =

87138

- tokens_buff_new (pfile, count, &virt_locs);

87139

+ _cpp_buff *macro_tokens

87140

+ = tokens_buff_new (pfile, tokens_count, &virt_locs);

87141

87142

/* Create a macro map to record the locations of the

87143

tokens that are involved in the expansion. LOCATION

87144

is the location of the macro expansion point. */

87145

- map = linemap_enter_macro (pfile->line_table,

87146

- node, location, count);

87147

- for (i = 0; i < count; ++i)

87148

+ map = linemap_enter_macro (pfile->line_table,

87149

+ node, location, tokens_count);

87150

+ for (i = 0; i < tokens_count; ++i)

87151

{

87152

tokens_buff_add_token (macro_tokens, virt_locs,

87153

src, src->src_loc,

87154

@@ -1134,16 +1135,12 @@

87155

virt_locs,

87156

(const cpp_token **)

87157

macro_tokens->base,

87158

- count);

87159

- num_macro_tokens_counter += count;

87160

+ tokens_count);

87161

}

87162

else

87163

- {

87164

- unsigned tokens_count = macro_real_token_count (macro);

87165

- _cpp_push_token_context (pfile, node, macro->exp.tokens,

87166

- tokens_count);

87167

- num_macro_tokens_counter += tokens_count;

87168

- }

87169

+ _cpp_push_token_context (pfile, node, macro->exp.tokens,

87170

+ tokens_count);

87171

+ num_macro_tokens_counter += tokens_count;

87172

}

87173

87174

if (pragma_buff)

87175

Index: libcpp/line-map.c

87176

===================================================================

87177

--- a/src/libcpp/line-map.c (.../tags/gcc_4_8_2_release)

87178

+++ b/src/libcpp/line-map.c (.../branches/gcc-4_8-branch)

87179

@@ -1024,6 +1024,11 @@

87180

bool pre_virtual_p, post_virtual_p;

87181

source_location l0 = pre, l1 = post;

87182

87183

+ if (IS_ADHOC_LOC (l0))

87184

+ l0 = set->location_adhoc_data_map.data[l0 & MAX_SOURCE_LOCATION].locus;

87185

+ if (IS_ADHOC_LOC (l1))

87186

+ l1 = set->location_adhoc_data_map.data[l1 & MAX_SOURCE_LOCATION].locus;

87187

+

87188

if (l0 == l1)

87189

return 0;

87190

87191

Index: libcpp/files.c

87192

===================================================================

87193

--- a/src/libcpp/files.c (.../tags/gcc_4_8_2_release)

87194

+++ b/src/libcpp/files.c (.../branches/gcc-4_8-branch)

87195

@@ -983,6 +983,7 @@

87196

{

87197

struct cpp_dir *dir;

87198

_cpp_file *file;

87199

+ bool stacked;

87200

87201

dir = search_path_head (pfile, fname, angle_brackets, type);

87202

if (!dir)

87203

@@ -993,19 +994,26 @@

87204

if (type == IT_DEFAULT && file == NULL)

87205

return false;

87206

87207

- /* Compensate for the increment in linemap_add that occurs in

87208

- _cpp_stack_file. In the case of a normal #include, we're

87209

- currently at the start of the line *following* the #include. A

87210

- separate source_location for this location makes no sense (until

87211

- we do the LC_LEAVE), and complicates LAST_SOURCE_LINE_LOCATION.

87212

- This does not apply if we found a PCH file (in which case

87213

- linemap_add is not called) or we were included from the

87214

- command-line. */

87215

+ /* Compensate for the increment in linemap_add that occurs if

87216

+ _cpp_stack_file actually stacks the file. In the case of a

87217

+ normal #include, we're currently at the start of the line

87218

+ *following* the #include. A separate source_location for this

87219

+ location makes no sense (until we do the LC_LEAVE), and

87220

+ complicates LAST_SOURCE_LINE_LOCATION. This does not apply if we

87221

+ found a PCH file (in which case linemap_add is not called) or we

87222

+ were included from the command-line. */

87223

if (file->pchname == NULL && file->err_no == 0

87224

&& type != IT_CMDLINE && type != IT_DEFAULT)

87225

pfile->line_table->highest_location--;

87226

87227

- return _cpp_stack_file (pfile, file, type == IT_IMPORT);

87228

+ stacked = _cpp_stack_file (pfile, file, type == IT_IMPORT);

87229

+

87230

+ if (!stacked)

87231

+ /* _cpp_stack_file didn't stack the file, so let's rollback the

87232

+ compensation dance we performed above. */

87233

+ pfile->line_table->highest_location++;

87234

+

87235

+ return stacked;

87236

}

87237

87238

/* Could not open FILE. The complication is dependency output. */

87239

Index: libcpp/ChangeLog

87240

===================================================================

87241

--- a/src/libcpp/ChangeLog (.../tags/gcc_4_8_2_release)

87242

+++ b/src/libcpp/ChangeLog (.../branches/gcc-4_8-branch)

87243

@@ -1,3 +1,36 @@

87244

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

87245

+

87246

+ Backport from mainline

87247

+ 2013-11-18 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

87248

+

87249

+ * lex.c (search_line_fast): Correct for little endian.

87250

+

87251

+2014-03-06 Jakub Jelinek <jakub@redhat.com>

87252

+

87253

+ Backport from mainline

87254

+ 2014-02-19 Jakub Jelinek <jakub@redhat.com>

87255

+

87256

+ PR preprocessor/58844

87257

+ * macro.c (enter_macro_context): Only push

87258

+ macro_real_token_count (macro) tokens rather than

87259

+ macro->count tokens, regardless of

87260

+ CPP_OPTION (pfile, track-macro-expansion).

87261

+

87262

+ 2014-02-07 Jakub Jelinek <jakub@redhat.com>

87263

+

87264

+ PR preprocessor/56824

87265

+ * line-map.c (linemap_compare_locations): Look through adhoc locations

87266

+ for both l0 and l1.

87267

+

87268

+2014-03-06 Jakub Jelinek <jakub@redhat.com>

87269

+

87270

+ PR preprocessor/60400

87271

+ Backport from mainline

87272

+ 2013-06-24 Dehao Chen <dehao@google.com>

87273

+

87274

+ * files.c (_cpp_stack_include): Fix the highest_location when header

87275

+ file is guarded by #ifndef and is included twice.

87276

+

87277

2013-10-16 Release Manager

87278

87279

* GCC 4.8.2 released.

87280

Index: libcpp/lex.c

87281

===================================================================

87282

--- a/src/libcpp/lex.c (.../tags/gcc_4_8_2_release)

87283

+++ b/src/libcpp/lex.c (.../branches/gcc-4_8-branch)

87284

@@ -559,8 +559,13 @@

87285

beginning with all ones and shifting in zeros according to the

87286

mis-alignment. The LVSR instruction pulls the exact shift we

87287

want from the address. */

87288

+#ifdef __BIG_ENDIAN__

87289

mask = __builtin_vec_lvsr(0, s);

87290

mask = __builtin_vec_perm(zero, ones, mask);

87291

+#else

87292

+ mask = __builtin_vec_lvsl(0, s);

87293

+ mask = __builtin_vec_perm(ones, zero, mask);

87294

+#endif

87295

data &= mask;

87296

87297

/* While altivec loads mask addresses, we still need to align S so

87298

@@ -624,7 +629,11 @@

87299

/* L now contains 0xff in bytes for which we matched one of the

87300

relevant characters. We can find the byte index by finding

87301

its bit index and dividing by 8. */

87302

+#ifdef __BIG_ENDIAN__

87303

l = __builtin_clzl(l) >> 3;

87304

+#else

87305

+ l = __builtin_ctzl(l) >> 3;

87306

+#endif

87307

return s + l;

87308

87309

#undef N

87310

Index: libcpp/po/pt_BR.po

87311

===================================================================

87312

--- a/src/libcpp/po/pt_BR.po (.../tags/gcc_4_8_2_release)

87313

+++ b/src/libcpp/po/pt_BR.po (.../branches/gcc-4_8-branch)

87314

@@ -0,0 +1,908 @@

87315

+# Brazilian Portuguese translation for cpplib

87316

87317

+# This file is distributed under the same license as the gcc package.

87318

+# Rafael Ferreira <rafael.f.f1@gmail.com>, 2013.

87319

+#

87320

+msgid ""

87321

+msgstr ""

87322

+"Project-Id-Version: cpplib 4.8.0\n"

87323

+"Report-Msgid-Bugs-To: http://gcc.gnu.org/bugs.html\n"

87324

+"POT-Creation-Date: 2013-03-15 17:42+0000\n"

87325

+"PO-Revision-Date: 2013-12-18 03:12-0300\n"

87326

+"Last-Translator: Rafael Ferreira <rafael.f.f1@gmail.com>\n"

87327

+"Language-Team: Brazilian Portuguese <ldpbr-translation@lists.sourceforge.net>\n"

87328

+"Language: pt_BR\n"

87329

+"MIME-Version: 1.0\n"

87330

+"Content-Type: text/plain; charset=UTF-8\n"

87331

+"Content-Transfer-Encoding: 8bit\n"

87332

+"X-Generator: Poedit 1.5.7\n"

87333

+"Plural-Forms: nplurals=2; plural=(n > 1);\n"

87334

+

87335

+#: charset.c:673

87336

+#, c-format

87337

+msgid "conversion from %s to %s not supported by iconv"

87338

+msgstr "sem suporte a conversão de %s para %s por iconv"

87339

+

87340

+#: charset.c:676

87341

+msgid "iconv_open"

87342

+msgstr "iconv_open"

87343

+

87344

+#: charset.c:684

87345

+#, c-format

87346

+msgid "no iconv implementation, cannot convert from %s to %s"

87347

+msgstr "nenhuma implementação iconv, não foi possível converter de %s para %s"

87348

+

87349

+#: charset.c:780

87350

+#, c-format

87351

+msgid "character 0x%lx is not in the basic source character set\n"

87352

+msgstr "caractere 0x%lx não está no conjunto de caracteres fonte básico\n"

87353

+

87354

+#: charset.c:797 charset.c:1443

87355

+msgid "converting to execution character set"

87356

+msgstr "convertendo para conjunto de caracteres da execução"

87357

+

87358

+#: charset.c:803

87359

+#, c-format

87360

+msgid "character 0x%lx is not unibyte in execution character set"

87361

+msgstr "caractere 0x%lx não é unibyte no conjunto de caracteres de execução"

87362

+

87363

+#: charset.c:927

87364

+#, c-format

87365

+msgid "Character %x might not be NFKC"

87366

+msgstr "Caractere %x pode não ser NFKC"

87367

+

87368

+#: charset.c:993

87369

+msgid "universal character names are only valid in C++ and C99"

87370

+msgstr "nomes de caractere universais são válidos apenas em C++ e C99"

87371

+

87372

+#: charset.c:996

87373

+#, c-format

87374

+msgid "the meaning of '\\%c' is different in traditional C"

87375

+msgstr "o significado de \"\\%c\" é diferente em C tradicional"

87376

+

87377

+#: charset.c:1005

87378

+msgid "In _cpp_valid_ucn but not a UCN"

87379

+msgstr "Em _cpp_valid_ucn, mas não é um UCN"

87380

+

87381

+#: charset.c:1030

87382

+#, c-format

87383

+msgid "incomplete universal character name %.*s"

87384

+msgstr "nome de caractere universal incompleto %.*s"

87385

+

87386

+#: charset.c:1045

87387

+#, c-format

87388

+msgid "%.*s is not a valid universal character"

87389

+msgstr "%.*s não é um caractere universal válido"

87390

+

87391

+#: charset.c:1055 lex.c:1117

87392

+msgid "'$' in identifier or number"

87393

+msgstr "\"$\" em identificador ou número"

87394

+

87395

+#: charset.c:1065

87396

+#, c-format

87397

+msgid "universal character %.*s is not valid in an identifier"

87398

+msgstr "caractere universal %.*s não é válido em um identificador"

87399

+

87400

+#: charset.c:1069

87401

+#, c-format

87402

+msgid "universal character %.*s is not valid at the start of an identifier"

87403

+msgstr "caractere universal %.*s não é válido no começo de um identificador"

87404

+

87405

+#: charset.c:1101 charset.c:1673

87406

+msgid "converting UCN to source character set"

87407

+msgstr "convertendo UCN para conjunto de caracteres fonte"

87408

+

87409

+#: charset.c:1105

87410

+msgid "converting UCN to execution character set"

87411

+msgstr "convertendo UCN para conjunto de caracteres de execução"

87412

+

87413

+#: charset.c:1177

87414

+msgid "the meaning of '\\x' is different in traditional C"

87415

+msgstr "o significado de \"\\x\" é diferente em C tradicional"

87416

+

87417

+#: charset.c:1194

87418

+msgid "\\x used with no following hex digits"

87419

+msgstr "\\x usado com nenhum dígito hexa"

87420

+

87421

+#: charset.c:1201

87422

+msgid "hex escape sequence out of range"

87423

+msgstr "sequência de escape hexa fora de alcance"

87424

+

87425

+#: charset.c:1239

87426

+msgid "octal escape sequence out of range"

87427

+msgstr "sequência de escape octal fora de alcance"

87428

+

87429

+#: charset.c:1305

87430

+msgid "the meaning of '\\a' is different in traditional C"

87431

+msgstr "o significado de \"\\a\" é diferente em C tradicional"

87432

+

87433

+#: charset.c:1312

87434

+#, c-format

87435

+msgid "non-ISO-standard escape sequence, '\\%c'"

87436

+msgstr "sequência de escape não padrão ISO, \"\\%c\""

87437

+

87438

+#: charset.c:1320

87439

+#, c-format

87440

+msgid "unknown escape sequence: '\\%c'"

87441

+msgstr "sequência de escape desconhecida: \"\\%c\""

87442

+

87443

+#: charset.c:1328

87444

+#, c-format

87445

+msgid "unknown escape sequence: '\\%s'"

87446

+msgstr "sequência de escape desconhecida: \"\\%s\""

87447

+

87448

+#: charset.c:1335

87449

+msgid "converting escape sequence to execution character set"

87450

+msgstr "convertendo sequência de escape para conjunto de caracteres de execução"

87451

+

87452

+#: charset.c:1508 charset.c:1572

87453

+msgid "character constant too long for its type"

87454

+msgstr "constante caractere muito longa para seu tipo"

87455

+

87456

+#: charset.c:1511

87457

+msgid "multi-character character constant"

87458

+msgstr "constante de caractere multi-caractere"

87459

+

87460

+#: charset.c:1611

87461

+msgid "empty character constant"

87462

+msgstr "constante caractere vazia"

87463

+

87464

+#: charset.c:1720

87465

+#, c-format

87466

+msgid "failure to convert %s to %s"

87467

+msgstr "falha ao converter %s para %s"

87468

+

87469

+#: directives.c:224 directives.c:250

87470

+#, c-format

87471

+msgid "extra tokens at end of #%s directive"

87472

+msgstr "tokens extras ao final da diretiva %#s"

87473

+

87474

+#: directives.c:357

87475

+#, c-format

87476

+msgid "#%s is a GCC extension"

87477

+msgstr "#%s é uma extensão GCC"

87478

+

87479

+#: directives.c:362

87480

+#, c-format

87481

+msgid "#%s is a deprecated GCC extension"

87482

+msgstr "#%s é uma extensão GCC obsoleta"

87483

+

87484

+#: directives.c:375

87485

+msgid "suggest not using #elif in traditional C"

87486

+msgstr "sugere-se não usar #elif em C tradicional"

87487

+

87488

+#: directives.c:378

87489

+#, c-format

87490

+msgid "traditional C ignores #%s with the # indented"

87491

+msgstr "C tradicional ignora #%s com o # com recuo"

87492

+

87493

+#: directives.c:382

87494

+#, c-format

87495

+msgid "suggest hiding #%s from traditional C with an indented #"

87496

+msgstr "sugere-se ocultar #%s do C tradicional com um # com recuo"

87497

+

87498

+#: directives.c:408

87499

+msgid "embedding a directive within macro arguments is not portable"

87500

+msgstr "embutir uma diretiva dentro de argumentos macro não é portátil"

87501

+

87502

+#: directives.c:428

87503

+msgid "style of line directive is a GCC extension"

87504

+msgstr "estilo de diretiva de linha é uma extensão GCC"

87505

+

87506

+#: directives.c:483

87507

+#, c-format

87508

+msgid "invalid preprocessing directive #%s"

87509

+msgstr "diretiva de preprocessamento inválida #%s"

87510

+

87511

+#: directives.c:551

87512

+msgid "\"defined\" cannot be used as a macro name"

87513

+msgstr "\"defined\" não pode ser usado como um nome de macro"

87514

+

87515

+#: directives.c:557

87516

+#, c-format

87517

+msgid "\"%s\" cannot be used as a macro name as it is an operator in C++"

87518

+msgstr "\"%s\" não pode ser usado como um nome de macro, pois é um operador em C++"

87519

+

87520

+#: directives.c:560

87521

+#, c-format

87522

+msgid "no macro name given in #%s directive"

87523

+msgstr "nenhum nome de macro fornecido na diretiva #%s"

87524

+

87525

+#: directives.c:563

87526

+msgid "macro names must be identifiers"

87527

+msgstr "nomes de macro devem ser identificadores"

87528

+

87529

+#: directives.c:612

87530

+#, c-format

87531

+msgid "undefining \"%s\""

87532

+msgstr "removendo definição de \"%s\""

87533

+

87534

+#: directives.c:667

87535

+msgid "missing terminating > character"

87536

+msgstr "faltando caractere terminador >"

87537

+

87538

+#: directives.c:726

87539

+#, c-format

87540

+msgid "#%s expects \"FILENAME\" or <FILENAME>"

87541

+msgstr "#%s espera \"NOME DE ARQUIVO\" OU <NOME DE ARQUIVO>"

87542

+

87543

+#: directives.c:772

87544

+#, c-format

87545

+msgid "empty filename in #%s"

87546

+msgstr "nome de arquivo vazio em #%s"

87547

+

87548

+#: directives.c:782

87549

+msgid "#include nested too deeply"

87550

+msgstr "#include aninhado profundo demais"

87551

+

87552

+#: directives.c:823

87553

+msgid "#include_next in primary source file"

87554

+msgstr "#include_next no arquivo fonte primário"

87555

+

87556

+#: directives.c:849

87557

+#, c-format

87558

+msgid "invalid flag \"%s\" in line directive"

87559

+msgstr "opção inválida \"%s\" na diretiva line"

87560

+

87561

+#: directives.c:909

87562

+msgid "unexpected end of file after #line"

87563

+msgstr "fim de arquivo inesperado após #line"

87564

+

87565

+#: directives.c:912

87566

+#, c-format

87567

+msgid "\"%s\" after #line is not a positive integer"

87568

+msgstr "\"%s\" após #line não é um inteiro positivo"

87569

+

87570

+#: directives.c:918 directives.c:920

87571

+msgid "line number out of range"

87572

+msgstr "número da linha fora de alcance"

87573

+

87574

+#: directives.c:933 directives.c:1013

87575

+#, c-format

87576

+msgid "\"%s\" is not a valid filename"

87577

+msgstr "\"%s\" não é um nome de arquivo válido"

87578

+

87579

+#: directives.c:973

87580

+#, c-format

87581

+msgid "\"%s\" after # is not a positive integer"

87582

+msgstr "\"%s\" após # não é um inteiro positivo"

87583

+

87584

+#: directives.c:1068 directives.c:1070 directives.c:1072 directives.c:1658

87585

+#, c-format

87586

+msgid "%s"

87587

+msgstr "%s"

87588

+

87589

+#: directives.c:1096

87590

+#, c-format

87591

+msgid "invalid #%s directive"

87592

+msgstr "diretiva inválida #%s"

87593

+

87594

+#: directives.c:1159

87595

+#, c-format

87596

+msgid "registering pragmas in namespace \"%s\" with mismatched name expansion"

87597

+msgstr "registrando pragmas em espaço de nomes \"%s\" com expansão de nome incompatível"

87598

+

87599

+#: directives.c:1168

87600

+#, c-format

87601

+msgid "registering pragma \"%s\" with name expansion and no namespace"

87602

+msgstr "registrando pragma \"%s\" com expansão de nome e nenhum espaço de nomes"

87603

+

87604

+#: directives.c:1186

87605

+#, c-format

87606

+msgid "registering \"%s\" as both a pragma and a pragma namespace"

87607

+msgstr "registrando \"%s\" como tanto um pragma e um espaço de nomes de pragma"

87608

+

87609

+#: directives.c:1189

87610

+#, c-format

87611

+msgid "#pragma %s %s is already registered"

87612

+msgstr "#pragma %s %s já está registrado"

87613

+

87614

+#: directives.c:1192

87615

+#, c-format

87616

+msgid "#pragma %s is already registered"

87617

+msgstr "#pragma %s já está registrado"

87618

+

87619

+#: directives.c:1222

87620

+msgid "registering pragma with NULL handler"

87621

+msgstr "registrando pragma com manipulador NULO"

87622

+

87623

+#: directives.c:1439

87624

+msgid "#pragma once in main file"

87625

+msgstr "#pragma ocorre uma vez no arquivo principal"

87626

+

87627

+#: directives.c:1462

87628

+msgid "invalid #pragma push_macro directive"

87629

+msgstr "diretiva inválida #pragma push_macro"

87630

+

87631

+#: directives.c:1517

87632

+msgid "invalid #pragma pop_macro directive"

87633

+msgstr "diretiva inválida #pragma pop_macro"

87634

+

87635

+#: directives.c:1572

87636

+msgid "invalid #pragma GCC poison directive"

87637

+msgstr "diretiva inválida #pragma GCC poison"

87638

+

87639

+#: directives.c:1581

87640

+#, c-format

87641

+msgid "poisoning existing macro \"%s\""

87642

+msgstr "envenenando macro existente \"%s\""

87643

+

87644

+#: directives.c:1600

87645

+msgid "#pragma system_header ignored outside include file"

87646

+msgstr "#pragma system_header ignorado fora do arquivo include"

87647

+

87648

+#: directives.c:1625

87649

+#, c-format

87650

+msgid "cannot find source file %s"

87651

+msgstr "não foi possível localizar o arquivo fonte %s"

87652

+

87653

+#: directives.c:1629

87654

+#, c-format

87655

+msgid "current file is older than %s"

87656

+msgstr "arquivo atual é mais velho do que %s"

87657

+

87658

+#: directives.c:1653

87659

+#, c-format

87660

+msgid "invalid \"#pragma GCC %s\" directive"

87661

+msgstr "diretiva inválida \"#pragma GCC %s\""

87662

+

87663

+#: directives.c:1847

87664

+msgid "_Pragma takes a parenthesized string literal"

87665

+msgstr "_Pragma leva uma literal de string entre parenteses"

87666

+

87667

+#: directives.c:1968

87668

+msgid "#else without #if"

87669

+msgstr "#else sem #if"

87670

+

87671

+#: directives.c:1973

87672

+msgid "#else after #else"

87673

+msgstr "#else após #else"

87674

+

87675

+#: directives.c:1975 directives.c:2008

87676

+msgid "the conditional began here"

87677

+msgstr "a condicional começou aqui"

87678

+

87679

+#: directives.c:2001

87680

+msgid "#elif without #if"

87681

+msgstr "#elif sem #if"

87682

+

87683

+#: directives.c:2006

87684

+msgid "#elif after #else"

87685

+msgstr "#elif após #else"

87686

+

87687

+#: directives.c:2044

87688

+msgid "#endif without #if"

87689

+msgstr "#endif sem #if"

87690

+

87691

+#: directives.c:2124

87692

+msgid "missing '(' after predicate"

87693

+msgstr "faltando \"(\" após predicado"

87694

+

87695

+#: directives.c:2139

87696

+msgid "missing ')' to complete answer"

87697

+msgstr "faltando \")\" para uma resposta completa"

87698

+

87699

+#: directives.c:2159

87700

+msgid "predicate's answer is empty"

87701

+msgstr "resposta do predicado está vazia"

87702

+

87703

+#: directives.c:2186

87704

+msgid "assertion without predicate"

87705

+msgstr "asserção sem predicado"

87706

+

87707

+#: directives.c:2189

87708

+msgid "predicate must be an identifier"

87709

+msgstr "predicado deve ser um identificador"

87710

+

87711

+#: directives.c:2275

87712

+#, c-format

87713

+msgid "\"%s\" re-asserted"

87714

+msgstr "\"%s\" re-assertado"

87715

+

87716

+#: directives.c:2567

87717

+#, c-format

87718

+msgid "unterminated #%s"

87719

+msgstr "#%s não terminado"

87720

+

87721

+#: directives-only.c:221 lex.c:2234 traditional.c:162

87722

+msgid "unterminated comment"

87723

+msgstr "comentário não terminado"

87724

+

87725

+#: errors.c:234

87726

+msgid "stdout"

87727

+msgstr "saída padrão"

87728

+

87729

+#: errors.c:236

87730

+#, c-format

87731

+msgid "%s: %s"

87732

+msgstr "%s: %s"

87733

+

87734

+#: expr.c:479 expr.c:577

87735

+msgid "fixed-point constants are a GCC extension"

87736

+msgstr "constantes de ponto fixo (fixed-point constants) é uma extensão GCC"

87737

+

87738

+#: expr.c:504

87739

+msgid "invalid prefix \"0b\" for floating constant"

87740

+msgstr "prefixo inválido \"0b\" para constante flutuante"

87741

+

87742

+#: expr.c:514

87743

+msgid "use of C99 hexadecimal floating constant"

87744

+msgstr "uso de constante flutuante hexadecimal de C99"

87745

+

87746

+#: expr.c:545

87747

+#, c-format

87748

+msgid "invalid suffix \"%.*s\" on floating constant"

87749

+msgstr "sufixo inválido \"%.*s\" na constante flutuante"

87750

+

87751

+#: expr.c:556 expr.c:616

87752

+#, c-format

87753

+msgid "traditional C rejects the \"%.*s\" suffix"

87754

+msgstr "C tradicional rejeita o sufixo \"%.*s\""

87755

+

87756

+#: expr.c:564

87757

+msgid "suffix for double constant is a GCC extension"

87758

+msgstr "sufixo para constante dupla (suffix for double constant) é uma extensão GCC"

87759

+

87760

+#: expr.c:570

87761

+#, c-format

87762

+msgid "invalid suffix \"%.*s\" with hexadecimal floating constant"

87763

+msgstr "sufixo inválido \"%.*s\" com constante flutuante hexadecimal"

87764

+

87765

+#: expr.c:581

87766

+msgid "decimal float constants are a GCC extension"

87767

+msgstr "constantes flutuante decimais (decimal float constants) é uma extensão GCC"

87768

+

87769

+#: expr.c:599

87770

+#, c-format

87771

+msgid "invalid suffix \"%.*s\" on integer constant"

87772

+msgstr "sufixo inválido \"%.*s\" em constante inteiro"

87773

+

87774

+#: expr.c:624

87775

+msgid "use of C++0x long long integer constant"

87776

+msgstr "uso de constante longo longo inteiro de C++0x"

87777

+

87778

+#: expr.c:625

87779

+msgid "use of C99 long long integer constant"

87780

+msgstr "uso de constante longo longo inteiro de C99"

87781

+

87782

+#: expr.c:641

87783

+msgid "imaginary constants are a GCC extension"

87784

+msgstr "constantes imaginárias (imaginary constants) é uma extensão GCC"

87785

+

87786

+#: expr.c:644

87787

+msgid "binary constants are a GCC extension"

87788

+msgstr "constantes binárias (binary constants) é uma extensão GCC"

87789

+

87790

+#: expr.c:737

87791

+msgid "integer constant is too large for its type"

87792

+msgstr "constante inteira é muito grande para seu tipo"

87793

+

87794

+#: expr.c:768

87795

+msgid "integer constant is so large that it is unsigned"

87796

+msgstr "constante inteira é tão grande que não está assinada"

87797

+

87798

+#: expr.c:863

87799

+msgid "missing ')' after \"defined\""

87800

+msgstr "faltando \")\" após \"defined\""

87801

+

87802

+#: expr.c:870

87803

+msgid "operator \"defined\" requires an identifier"

87804

+msgstr "operador \"defined\" requer um identificador"

87805

+

87806

+#: expr.c:878

87807

+#, c-format

87808

+msgid "(\"%s\" is an alternative token for \"%s\" in C++)"

87809

+msgstr "(\"%s\" é um token alternativo para \"%s\" em C++)"

87810

+

87811

+#: expr.c:888

87812

+msgid "this use of \"defined\" may not be portable"

87813

+msgstr "esse uso de \"defined\" pode não ser portátil"

87814

+

87815

+#: expr.c:948

87816

+msgid "user-defined literal in preprocessor expression"

87817

+msgstr "literal definida pelo usuário em expressão do preprocessador"

87818

+

87819

+#: expr.c:953

87820

+msgid "floating constant in preprocessor expression"

87821

+msgstr "constante flutuante em expressão do preprocessador"

87822

+

87823

+#: expr.c:959

87824

+msgid "imaginary number in preprocessor expression"

87825

+msgstr "número imaginário em expressão do preprocessador"

87826

+

87827

+#: expr.c:1007

87828

+#, c-format

87829

+msgid "\"%s\" is not defined"

87830

+msgstr "\"%s\" não está definido"

87831

+

87832

+#: expr.c:1020

87833

+msgid "assertions are a GCC extension"

87834

+msgstr "asserções (assertions) é uma extensão GCC"

87835

+

87836

+#: expr.c:1023

87837

+msgid "assertions are a deprecated extension"

87838

+msgstr "asserções (assertions) é uma extensão obsoleta"

87839

+

87840

+#: expr.c:1268

87841

+#, c-format

87842

+msgid "unbalanced stack in %s"

87843

+msgstr "pilha não balanceada em %s"

87844

+

87845

+#: expr.c:1288

87846

+#, c-format

87847

+msgid "impossible operator '%u'"

87848

+msgstr "operador impossível \"%u\""

87849

+

87850

+#: expr.c:1389

87851

+msgid "missing ')' in expression"

87852

+msgstr "faltando \")\" na expressão"

87853

+

87854

+#: expr.c:1418

87855

+msgid "'?' without following ':'"

87856

+msgstr "\"?\" sem estar seguido por \":\""

87857

+

87858

+#: expr.c:1428

87859

+msgid "integer overflow in preprocessor expression"

87860

+msgstr "estouro de inteiro em expressão do preprocessador"

87861

+

87862

+#: expr.c:1433

87863

+msgid "missing '(' in expression"

87864

+msgstr "faltando \"(\" na expressão"

87865

+

87866

+#: expr.c:1465

87867

+#, c-format

87868

+msgid "the left operand of \"%s\" changes sign when promoted"

87869

+msgstr "o operador à esquerda de \"%s\" altera o sinal quando promovido"

87870

+

87871

+#: expr.c:1470

87872

+#, c-format

87873

+msgid "the right operand of \"%s\" changes sign when promoted"

87874

+msgstr "o operador à direita de \"%s\" altera o sinal quando promovido"

87875

+

87876

+#: expr.c:1729

87877

+msgid "traditional C rejects the unary plus operator"

87878

+msgstr "C tradicional rejeita o operador unário mais"

87879

+

87880

+#: expr.c:1812

87881

+msgid "comma operator in operand of #if"

87882

+msgstr "operador vírgula em operando de #if"

87883

+

87884

+#: expr.c:1948

87885

+msgid "division by zero in #if"

87886

+msgstr "divisão por zero em #if"

87887

+

87888

+#: files.c:505

87889

+msgid "NULL directory in find_file"

87890

+msgstr "diretório NULO em find_file"

87891

+

87892

+#: files.c:553

87893

+msgid "one or more PCH files were found, but they were invalid"

87894

+msgstr "um ou mais arquivos PCH foram encontrados, mas são inválidos"

87895

+

87896

+#: files.c:556

87897

+msgid "use -Winvalid-pch for more information"

87898

+msgstr "use -Winvalid-pch para mais informações"

87899

+

87900

+#: files.c:660

87901

+#, c-format

87902

+msgid "%s is a block device"

87903

+msgstr "%s é um dispositivo de bloco"

87904

+

87905

+#: files.c:677

87906

+#, c-format

87907

+msgid "%s is too large"

87908

+msgstr "%s é muito grande"

87909

+

87910

+#: files.c:717

87911

+#, c-format

87912

+msgid "%s is shorter than expected"

87913

+msgstr "%s é muito menor do que esperado"

87914

+

87915

+#: files.c:953

87916

+#, c-format

87917

+msgid "no include path in which to search for %s"

87918

+msgstr "não foi incluído nenhum caminho no qual se possa procurar por %s"

87919

+

87920

+#: files.c:1381

87921

+msgid "Multiple include guards may be useful for:\n"

87922

+msgstr "Múltiplos include guards podem ser úteis para:\n"

87923

+

87924

+#: init.c:524

87925

+msgid "cppchar_t must be an unsigned type"

87926

+msgstr "cppchar_t deve ser um tipo não assinado"

87927

+

87928

+#: init.c:528

87929

+#, c-format

87930

+msgid "preprocessor arithmetic has maximum precision of %lu bits; target requires %lu bits"

87931

+msgstr "aritmética do preprocessador possui uma precisão máxima de %lu bits; o alvo requer %lu bits"

87932

+

87933

+#: init.c:535

87934

+msgid "CPP arithmetic must be at least as precise as a target int"

87935

+msgstr "aritmética do CPP deve ser pelo menos tão precisa quanto um int alvo"

87936

+

87937

+#: init.c:538

87938

+msgid "target char is less than 8 bits wide"

87939

+msgstr "char alvo é menor do que 8 bits"

87940

+

87941

+#: init.c:542

87942

+msgid "target wchar_t is narrower than target char"

87943

+msgstr "wchar_t alvo é mais estreito do que o char alvo"

87944

+

87945

+#: init.c:546

87946

+msgid "target int is narrower than target char"

87947

+msgstr "int alvo é mais estreito do que o char alvo"

87948

+

87949

+#: init.c:551

87950

+msgid "CPP half-integer narrower than CPP character"

87951

+msgstr "meio-inteiro do CPP é mais estreito do que o caractere do CPP"

87952

+

87953

+#: init.c:555

87954

+#, c-format

87955

+msgid "CPP on this host cannot handle wide character constants over %lu bits, but the target requires %lu bits"

87956

+msgstr "CPP nesta máquina não consegue manipular constantes de wide character acima de %lu bits, mas o alvo requer %lu bits"

87957

+

87958

+#: lex.c:910

87959

+msgid "backslash and newline separated by space"

87960

+msgstr "barra invertida e nova linha separadas por espaço"

87961

+

87962

+#: lex.c:915

87963

+msgid "backslash-newline at end of file"

87964

+msgstr "barra invertida e nova linha no final do arquivo"

87965

+

87966

+#: lex.c:931

87967

+#, c-format

87968

+msgid "trigraph ??%c converted to %c"

87969

+msgstr "trígrafo ??%c convertido para %c"

87970

+

87971

+#: lex.c:939

87972

+#, c-format

87973

+msgid "trigraph ??%c ignored, use -trigraphs to enable"

87974

+msgstr "trígrafo ??%c ignorado, use -trigraphs para habilitá-lo"

87975

+

87976

+#: lex.c:988

87977

+msgid "\"/*\" within comment"

87978

+msgstr "\"/*\" dentro de comentário"

87979

+

87980

+#: lex.c:1046

87981

+#, c-format

87982

+msgid "%s in preprocessing directive"

87983

+msgstr "%s em diretiva de preprocessamento"

87984

+

87985

+#: lex.c:1055

87986

+msgid "null character(s) ignored"

87987

+msgstr "um ou mais caracteres nulos ignorados"

87988

+

87989

+#: lex.c:1092

87990

+#, c-format

87991

+msgid "`%.*s' is not in NFKC"

87992

+msgstr "\"%.*s\" não está em NFKC"

87993

+

87994

+#: lex.c:1095

87995

+#, c-format

87996

+msgid "`%.*s' is not in NFC"

87997

+msgstr "\"%.*s\" não está em NFC"

87998

+

87999

+#: lex.c:1164 lex.c:1241

88000

+#, c-format

88001

+msgid "attempt to use poisoned \"%s\""

88002

+msgstr "tentativa de usar \"%s\" envenenado"

88003

+

88004

+#: lex.c:1172 lex.c:1249

88005

+msgid "__VA_ARGS__ can only appear in the expansion of a C99 variadic macro"

88006

+msgstr "__VA_ARGS__ pode aparecer apenas na expansão de uma macro variádica C99"

88007

+

88008

+#: lex.c:1178 lex.c:1255

88009

+#, c-format

88010

+msgid "identifier \"%s\" is a special operator name in C++"

88011

+msgstr "identificador \"%s\" é o nome de um operador especial em C++"

88012

+

88013

+#: lex.c:1399

88014

+msgid "raw string delimiter longer than 16 characters"

88015

+msgstr "delimitador de string não tratada (raw) maior do que 16 caracteres"

88016

+

88017

+#: lex.c:1402

88018

+#, c-format

88019

+msgid "invalid character '%c' in raw string delimiter"

88020

+msgstr "caractere inválido \"%c\" em delimitador de string não tratada (raw)"

88021

+

88022

+#: lex.c:1525 lex.c:1547

88023

+msgid "unterminated raw string"

88024

+msgstr "string não tratada (raw) não terminada"

88025

+

88026

+#: lex.c:1573 lex.c:1706

88027

+msgid "invalid suffix on literal; C++11 requires a space between literal and identifier"

88028

+msgstr "sufixo inválido em literal; C++11 requer um espaço entre literal e identificador"

88029

+

88030

+#: lex.c:1684

88031

+msgid "null character(s) preserved in literal"

88032

+msgstr "um ou mais caracteres nulos preservados em literal"

88033

+

88034

+#: lex.c:1687

88035

+#, c-format

88036

+msgid "missing terminating %c character"

88037

+msgstr "faltando o caractere de terminação %c"

88038

+

88039

+#: lex.c:2245

88040

+msgid "C++ style comments are not allowed in ISO C90"

88041

+msgstr "comentários no estilo C++ não são permitidos em ISO C90"

88042

+

88043

+#: lex.c:2247

88044

+msgid "(this will be reported only once per input file)"

88045

+msgstr "(isso será relatado apenas uma vez por arquivo de entrada)"

88046

+

88047

+#: lex.c:2252

88048

+msgid "multi-line comment"

88049

+msgstr "comentário multilinha"

88050

+

88051

+#: lex.c:2583

88052

+#, c-format

88053

+msgid "unspellable token %s"

88054

+msgstr "token %s impronunciável"

88055

+

88056

+#: macro.c:191

88057

+#, c-format

88058

+msgid "macro \"%s\" is not used"

88059

+msgstr "macro \"%s\" não é usada"

88060

+

88061

+#: macro.c:229 macro.c:426

88062

+#, c-format

88063

+msgid "invalid built-in macro \"%s\""

88064

+msgstr "macro interna inválida \"%s\""

88065

+

88066

+#: macro.c:263

88067

+msgid "could not determine file timestamp"

88068

+msgstr "não foi possível determinar o arquivo de marca de tempo"

88069

+

88070

+#: macro.c:361

88071

+msgid "could not determine date and time"

88072

+msgstr "não foi possível determinar a data e a hora"

88073

+

88074

+#: macro.c:377

88075

+msgid "__COUNTER__ expanded inside directive with -fdirectives-only"

88076

+msgstr "__COUNTER__ expandido dentro diretiva com -fdirectives-only"

88077

+

88078

+#: macro.c:535

88079

+msgid "invalid string literal, ignoring final '\\'"

88080

+msgstr "literal de string inválida, ignorando final \"\\\""

88081

+

88082

+#: macro.c:597

88083

+#, c-format

88084

+msgid "pasting \"%s\" and \"%s\" does not give a valid preprocessing token"

88085

+msgstr "colar \"%s\" em \"%s\" não resulta em nenhum token de preprocessamento válido"

88086

+

88087

+#: macro.c:719

88088

+msgid "ISO C99 requires rest arguments to be used"

88089

+msgstr "ISO C99 requer que argumentos restantes sejam usados"

88090

+

88091

+#: macro.c:724

88092

+#, c-format

88093

+msgid "macro \"%s\" requires %u arguments, but only %u given"

88094

+msgstr "macro \"%s\" requer %u argumentos, mas apenas %u foram fornecidos"

88095

+

88096

+#: macro.c:729

88097

+#, c-format

88098

+msgid "macro \"%s\" passed %u arguments, but takes just %u"

88099

+msgstr "macro \"%s\" passou %u argumentos, mas usa apenas %u"

88100

+

88101

+#: macro.c:923 traditional.c:680

88102

+#, c-format

88103

+msgid "unterminated argument list invoking macro \"%s\""

88104

+msgstr "lista de argumentos interminável chamando macro \"%s\""

88105

+

88106

+#: macro.c:1074

88107

+#, c-format

88108

+msgid "function-like macro \"%s\" must be used with arguments in traditional C"

88109

+msgstr "macro \"%s\" do tipo função deve ser usada com argumento em C tradicional"

88110

+

88111

+# http://gcc.gnu.org/bugzilla/show_bug.cgi?id=33305

88112

+#: macro.c:1746

88113

+#, c-format

88114

+msgid "invoking macro %s argument %d: empty macro arguments are undefined in ISO C90 and ISO C++98"

88115

+msgstr "chamando macro %s argumento %d: argumentos de macro vazios estão indefinidos em ISO C90 e ISO C++98"

88116

+

88117

+#: macro.c:2708

88118

+#, c-format

88119

+msgid "duplicate macro parameter \"%s\""

88120

+msgstr "parâmetro de macro \"%s\" duplicado"

88121

+

88122

+#: macro.c:2754

88123

+#, c-format

88124

+msgid "\"%s\" may not appear in macro parameter list"

88125

+msgstr "\"%s\" não pode aparecer na lista de parâmetros de macro"

88126

+

88127

+#: macro.c:2762

88128

+msgid "macro parameters must be comma-separated"

88129

+msgstr "parâmetros de macro devem ser separados por vírgula"

88130

+

88131

+#: macro.c:2779

88132

+msgid "parameter name missing"

88133

+msgstr "faltando nome de parâmetro"

88134

+

88135

+#: macro.c:2797

88136

+msgid "anonymous variadic macros were introduced in C99"

88137

+msgstr "macros variádicas anônimas foram introduzidas em C99"

88138

+

88139

+#: macro.c:2802

88140

+msgid "ISO C does not permit named variadic macros"

88141

+msgstr "ISO C não permite macros variádicas nomeadas"

88142

+

88143

+#: macro.c:2811

88144

+msgid "missing ')' in macro parameter list"

88145

+msgstr "faltando \")\" na lista de parâmetros de macro"

88146

+

88147

+#: macro.c:2860

88148

+msgid "'##' cannot appear at either end of a macro expansion"

88149

+msgstr "\"##\" não pode aparecer no final da expansão de macro"

88150

+

88151

+#: macro.c:2895

88152

+msgid "ISO C99 requires whitespace after the macro name"

88153

+msgstr "ISO C99 requer espaço em branco após o nome de macro"

88154

+

88155

+#: macro.c:2919

88156

+msgid "missing whitespace after the macro name"

88157

+msgstr "faltando espaço em branco após o nome de macro"

88158

+

88159

+#: macro.c:2953

88160

+msgid "'#' is not followed by a macro parameter"

88161

+msgstr "\"#\" não está seguido por um parâmetro de macro"

88162

+

88163

+#: macro.c:3111

88164

+#, c-format

88165

+msgid "\"%s\" redefined"

88166

+msgstr "\"%s\" re-definido"

88167

+

88168

+#: macro.c:3117

88169

+msgid "this is the location of the previous definition"

88170

+msgstr "essa é a localização da definição anterior"

88171

+

88172

+#: macro.c:3178

88173

+#, c-format

88174

+msgid "macro argument \"%s\" would be stringified in traditional C"

88175

+msgstr "argumento de macro \"%s\" estaria em uma string no C tradicional"

88176

+

88177

+#: macro.c:3205

88178

+#, c-format

88179

+msgid "invalid hash type %d in cpp_macro_definition"

88180

+msgstr "tipo de hash inválido %d em cpp_macro_definition"

88181

+

88182

+#: pch.c:87 pch.c:345 pch.c:359 pch.c:377 pch.c:383 pch.c:392 pch.c:399

88183

+msgid "while writing precompiled header"

88184

+msgstr "enquanto realizava escrita de header pré-compilado"

88185

+

88186

+#: pch.c:619

88187

+#, c-format

88188

+msgid "%s: not used because `%.*s' is poisoned"

88189

+msgstr "%s: não usado porque \"%.*s\" está envenenado"

88190

+

88191

+#: pch.c:641

88192

+#, c-format

88193

+msgid "%s: not used because `%.*s' not defined"

88194

+msgstr "%s: não usado porque \"%.*s\" não está definido"

88195

+

88196

+#: pch.c:653

88197

+#, c-format

88198

+msgid "%s: not used because `%.*s' defined as `%s' not `%.*s'"

88199

+msgstr "%s: não usado porque \"%.*s\" está definido como \"%s\", e não \"%.*s\""

88200

+

88201

+#: pch.c:694

88202

+#, c-format

88203

+msgid "%s: not used because `%s' is defined"

88204

+msgstr "%s: não usado porque \"%s\" está definido"

88205

+

88206

+#: pch.c:714

88207

+#, c-format

88208

+msgid "%s: not used because `__COUNTER__' is invalid"

88209

+msgstr "%s: não usado porque \"__COUNTER__\" é inválido"

88210

+

88211

+#: pch.c:723 pch.c:898

88212

+msgid "while reading precompiled header"

88213

+msgstr "enquanto realizava leitura de header pré-compilado"

88214

+

88215

+#: traditional.c:750

88216

+#, c-format

88217

+msgid "detected recursion whilst expanding macro \"%s\""

88218

+msgstr "detectada recursão enquanto expandia macro \"%s\""

88219

+

88220

+#: traditional.c:968

88221

+msgid "syntax error in macro parameter list"

88222

+msgstr "erro de sintaxe na lista de parâmetros de macro"

88223

Index: libcpp/po/ChangeLog

88224

===================================================================

88225

--- a/src/libcpp/po/ChangeLog (.../tags/gcc_4_8_2_release)

88226

+++ b/src/libcpp/po/ChangeLog (.../branches/gcc-4_8-branch)

88227

@@ -1,3 +1,11 @@

88228

+2013-12-18 Joseph Myers <joseph@codesourcery.com>

88229

+

88230

+ * pt_BR.po: New.

88231

+

88232

+2013-11-01 Joseph Myers <joseph@codesourcery.com>

88233

+

88234

+ * tr.po: Update.

88235

+

88236

2013-10-16 Release Manager

88237

88238

* GCC 4.8.2 released.

88239

Index: libcpp/po/tr.po

88240

===================================================================

88241

--- a/src/libcpp/po/tr.po (.../tags/gcc_4_8_2_release)

88242

+++ b/src/libcpp/po/tr.po (.../branches/gcc-4_8-branch)

88243

@@ -1,20 +1,22 @@

88244

# Turkish translations for cpplib messages.

88245

88246

+# This file is distributed under the same license as the gcc package.

88247

#

88248

# Nilgün Belma Bugüner <nilgun@buguner.name.tr>, 2001, ..., 2007.

88249

+# Volkan Gezer <vlkngzr@gmail.com>, 2013.

88250

msgid ""

88251

msgstr ""

88252

-"Project-Id-Version: cpplib 4.2.0\n"

88253

+"Project-Id-Version: cpplib 4.8.0\n"

88254

"Report-Msgid-Bugs-To: http://gcc.gnu.org/bugs.html\n"

88255

-"POT-Creation-Date: 2013-02-24 01:05+0000\n"

88256

-"PO-Revision-Date: 2007-05-23 01:17+0300\n"

88257

-"Last-Translator: Nilgün Belma Bugüner <nilgun@buguner.name.tr>\n"

88258

+"POT-Creation-Date: 2013-03-15 17:42+0000\n"

88259

+"PO-Revision-Date: 2013-11-01 22:29+0100\n"

88260

+"Last-Translator: Volkan Gezer <vlkngzr@gmail.com>\n"

88261

"Language-Team: Turkish <gnu-tr-u12a@lists.sourceforge.net>\n"

88262

"Language: tr\n"

88263

"MIME-Version: 1.0\n"

88264

"Content-Type: text/plain; charset=UTF-8\n"

88265

"Content-Transfer-Encoding: 8bit\n"

88266

-"X-Generator: KBabel 1.11.4\n"

88267

+"X-Generator: Lokalize 1.5\n"

88268

"Plural-Forms: nplurals=2; plural=(n != 1);\n"

88269

88270

#: charset.c:673

88271

@@ -121,10 +123,9 @@

88272

msgstr "ISO standardı olmayan önceleme dizgesi, '\\%c'"

88273

88274

#: charset.c:1320

88275

-#, fuzzy, c-format

88276

-#| msgid "unknown escape sequence '\\%c'"

88277

+#, c-format

88278

msgid "unknown escape sequence: '\\%c'"

88279

-msgstr "bilinmeyen önceleme dizgesi '\\%c'"

88280

+msgstr "bilinmeyen kaçış dizgesi: '\\%c'"

88281

88282

#: charset.c:1328

88283

#, c-format

88284

@@ -163,10 +164,9 @@

88285

msgstr "#%s bir GCC uzantısıdır"

88286

88287

#: directives.c:362

88288

-#, fuzzy, c-format

88289

-#| msgid "#%s is a GCC extension"

88290

+#, c-format

88291

msgid "#%s is a deprecated GCC extension"

88292

-msgstr "#%s bir GCC uzantısıdır"

88293

+msgstr "#%s eskimiş bir GCC uzantısıdır"

88294

88295

#: directives.c:375

88296

msgid "suggest not using #elif in traditional C"

88297

@@ -247,7 +247,7 @@

88298

88299

#: directives.c:909

88300

msgid "unexpected end of file after #line"

88301

-msgstr ""

88302

+msgstr "#line satırından sonra beklenmeyen dosya sonu"

88303

88304

#: directives.c:912

88305

#, c-format

88306

@@ -271,7 +271,7 @@

88307

#: directives.c:1068 directives.c:1070 directives.c:1072 directives.c:1658

88308

#, c-format

88309

msgid "%s"

88310

-msgstr ""

88311

+msgstr "%s"

88312

88313

#: directives.c:1096

88314

#, c-format

88315

@@ -312,16 +312,12 @@

88316

msgstr "main dosyasında '#pragma once'"

88317

88318

#: directives.c:1462

88319

-#, fuzzy

88320

-#| msgid "invalid #pragma GCC poison directive"

88321

msgid "invalid #pragma push_macro directive"

88322

-msgstr "geçersiz #pragma GCC poison yönergesi"

88323

+msgstr "geçersiz #pragma güdümlü_makro yönergesi"

88324

88325

#: directives.c:1517

88326

-#, fuzzy

88327

-#| msgid "invalid #pragma GCC poison directive"

88328

msgid "invalid #pragma pop_macro directive"

88329

-msgstr "geçersiz #pragma GCC poison yönergesi"

88330

+msgstr "geçersiz #pragma güdümlü_makro yönergesi"

88331

88332

#: directives.c:1572

88333

msgid "invalid #pragma GCC poison directive"

88334

@@ -347,10 +343,9 @@

88335

msgstr "mevcut dosya %s den daha eski"

88336

88337

#: directives.c:1653

88338

-#, fuzzy, c-format

88339

-#| msgid "invalid #pragma GCC poison directive"

88340

+#, c-format

88341

msgid "invalid \"#pragma GCC %s\" directive"

88342

-msgstr "geçersiz #pragma GCC poison yönergesi"

88343

+msgstr "geçersiz \"#pragma GCC %s\" yönergesi"

88344

88345

#: directives.c:1847

88346

msgid "_Pragma takes a parenthesized string literal"

88347

@@ -405,7 +400,7 @@

88348

msgid "\"%s\" re-asserted"

88349

msgstr "\"%s\" tekrar olumlanmış"

88350

88351

-#: directives.c:2566

88352

+#: directives.c:2567

88353

#, c-format

88354

msgid "unterminated #%s"

88355

msgstr "sonlandırılmamış #%s"

88356

@@ -424,16 +419,12 @@

88357

msgstr "%s: %s"

88358

88359

#: expr.c:479 expr.c:577

88360

-#, fuzzy

88361

-#| msgid "imaginary constants are a GCC extension"

88362

msgid "fixed-point constants are a GCC extension"

88363

-msgstr "sanal sabitler bir GCC genişletmesidir"

88364

+msgstr "sabit noktalı sabitler bir GCC uzantısıdır"

88365

88366

#: expr.c:504

88367

-#, fuzzy

88368

-#| msgid "invalid suffix \"%.*s\" on floating constant"

88369

msgid "invalid prefix \"0b\" for floating constant"

88370

-msgstr "gerçel sabitin \"%.*s\" soneki geçersiz"

88371

+msgstr "kayan nokta için geçerisz \"0b\" öntakısı"

88372

88373

#: expr.c:514

88374

msgid "use of C99 hexadecimal floating constant"

88375

@@ -450,10 +441,8 @@

88376

msgstr "geleneksel C \"%.*s\" sonekini kullanmaz"

88377

88378

#: expr.c:564

88379

-#, fuzzy

88380

-#| msgid "imaginary constants are a GCC extension"

88381

msgid "suffix for double constant is a GCC extension"

88382

-msgstr "sanal sabitler bir GCC genişletmesidir"

88383

+msgstr "çift sabit için öntakı bir GCC uzantısıdır"

88384

88385

#: expr.c:570

88386

#, c-format

88387

@@ -461,10 +450,8 @@

88388

msgstr "onaltılık kayan sabitli \"%.*s\" soneki geçersiz"

88389

88390

#: expr.c:581

88391

-#, fuzzy

88392

-#| msgid "imaginary constants are a GCC extension"

88393

msgid "decimal float constants are a GCC extension"

88394

-msgstr "sanal sabitler bir GCC genişletmesidir"

88395

+msgstr "onluk kayan sabitler bir GCC uzantısıdır"

88396

88397

#: expr.c:599

88398

#, c-format

88399

@@ -472,10 +459,8 @@

88400

msgstr "tamsayı sabitte sonek \"%.*s\" soneki geçersiz"

88401

88402

#: expr.c:624

88403

-#, fuzzy

88404

-#| msgid "use of C99 long long integer constant"

88405

msgid "use of C++0x long long integer constant"

88406

-msgstr "ISO C99 long long tamsayı sabitleri yasaklar"

88407

+msgstr "ISO C++0x long long tamsayı sabitlerinin kullanımı"

88408

88409

#: expr.c:625

88410

msgid "use of C99 long long integer constant"

88411

@@ -486,10 +471,8 @@

88412

msgstr "sanal sabitler bir GCC genişletmesidir"

88413

88414

#: expr.c:644

88415

-#, fuzzy

88416

-#| msgid "imaginary constants are a GCC extension"

88417

msgid "binary constants are a GCC extension"

88418

-msgstr "sanal sabitler bir GCC genişletmesidir"

88419

+msgstr "ikili sabitler bir GCC uzantısıdır"

88420

88421

#: expr.c:737

88422

msgid "integer constant is too large for its type"

88423

@@ -517,10 +500,8 @@

88424

msgstr "\"defined\" bu kullanımıyla uyarlanabilir olmayabilir"

88425

88426

#: expr.c:948

88427

-#, fuzzy

88428

-#| msgid "integer overflow in preprocessor expression"

88429

msgid "user-defined literal in preprocessor expression"

88430

-msgstr "önişlemci ifadesinde tamsayı taşması"

88431

+msgstr "önişleyici ifadesinde kullanıcı tanımlı bağımlı"

88432

88433

#: expr.c:953

88434

msgid "floating constant in preprocessor expression"

88435

@@ -536,20 +517,17 @@

88436

msgstr "\"%s\" tanımlı değil"

88437

88438

#: expr.c:1020

88439

-#, fuzzy

88440

-#| msgid "#%s is a GCC extension"

88441

msgid "assertions are a GCC extension"

88442

-msgstr "#%s bir GCC uzantısıdır"

88443

+msgstr "belirteçler bir GCC uzantısıdır"

88444

88445

#: expr.c:1023

88446

msgid "assertions are a deprecated extension"

88447

-msgstr ""

88448

+msgstr "belirteçler artık kullanılmayan bir ifadedir"

88449

88450

#: expr.c:1268

88451

-#, fuzzy, c-format

88452

-#| msgid "unbalanced stack in #if"

88453

+#, c-format

88454

msgid "unbalanced stack in %s"

88455

-msgstr "#if ifadesinde karşılıksız yığın"

88456

+msgstr "%s içinde dengelenmemiş yığın"

88457

88458

#: expr.c:1288

88459

#, c-format

88460

@@ -594,39 +572,39 @@

88461

msgid "division by zero in #if"

88462

msgstr "#if içinde sıfırla bölme"

88463

88464

-#: files.c:504

88465

+#: files.c:505

88466

msgid "NULL directory in find_file"

88467

msgstr "find_file içinde boş dizin"

88468

88469

-#: files.c:542

88470

+#: files.c:553

88471

msgid "one or more PCH files were found, but they were invalid"

88472

msgstr "bir veya daha fazla PCH dosyası bulundu ama bunlar geçersiz"

88473

88474

-#: files.c:545

88475

+#: files.c:556

88476

msgid "use -Winvalid-pch for more information"

88477

msgstr "daha fazla bilgi almak için -Winvalid-pch kullanın"

88478

88479

-#: files.c:643

88480

+#: files.c:660

88481

#, c-format

88482

msgid "%s is a block device"

88483

msgstr "%s bir blok aygıtıdır"

88484

88485

-#: files.c:660

88486

+#: files.c:677

88487

#, c-format

88488

msgid "%s is too large"

88489

msgstr "%s çok büyük"

88490

88491

-#: files.c:700

88492

+#: files.c:717

88493

#, c-format

88494

msgid "%s is shorter than expected"

88495

msgstr "%s beklenenden daha kısa"

88496

88497

-#: files.c:935

88498

+#: files.c:953

88499

#, c-format

88500

msgid "no include path in which to search for %s"

88501

msgstr "%s için aranacaklar içinde başlık dosyaları yolu yok"

88502

88503

-#: files.c:1363

88504

+#: files.c:1381

88505

msgid "Multiple include guards may be useful for:\n"

88506

msgstr "Çoklu include önlemleri aşağıdakiler için kullanışlı olabilir:\n"

88507

88508

@@ -717,27 +695,24 @@

88509

#: lex.c:1178 lex.c:1255

88510

#, c-format

88511

msgid "identifier \"%s\" is a special operator name in C++"

88512

-msgstr ""

88513

+msgstr "\"%s\" belirteci, C++'da özel bir işleç adıdır"

88514

88515

#: lex.c:1399

88516

msgid "raw string delimiter longer than 16 characters"

88517

-msgstr ""

88518

+msgstr "ham dizge ayracı 16 karakterden uzun"

88519

88520

#: lex.c:1402

88521

-#, fuzzy, c-format

88522

-#| msgid "universal character %.*s is not valid in an identifier"

88523

+#, c-format

88524

msgid "invalid character '%c' in raw string delimiter"

88525

-msgstr "evrensel karakter %.*s bir belirteç içinde geçerli değil"

88526

+msgstr "ham dizge ayracında geçersiz karakter '%c'"

88527

88528

#: lex.c:1525 lex.c:1547

88529

-#, fuzzy

88530

-#| msgid "unterminated #%s"

88531

msgid "unterminated raw string"

88532

-msgstr "sonlandırılmamış #%s"

88533

+msgstr "bitirilmemiş ham dizge"

88534

88535

#: lex.c:1573 lex.c:1706

88536

msgid "invalid suffix on literal; C++11 requires a space between literal and identifier"

88537

-msgstr ""

88538

+msgstr "geçersiz ifade soneki; C++11 ifade ve tanımlayıcı arasında bir boşluk gerektirir"

88539

88540

#: lex.c:1684

88541

msgid "null character(s) preserved in literal"

88542

@@ -785,7 +760,7 @@

88543

88544

#: macro.c:377

88545

msgid "__COUNTER__ expanded inside directive with -fdirectives-only"

88546

-msgstr ""

88547

+msgstr "__COUNTER__ -fdirectives-only ile talimat içerisinde genişletildi"

88548

88549

#: macro.c:535

88550

msgid "invalid string literal, ignoring final '\\'"

88551

@@ -823,7 +798,7 @@

88552

#: macro.c:1746

88553

#, c-format

88554

msgid "invoking macro %s argument %d: empty macro arguments are undefined in ISO C90 and ISO C++98"

88555

-msgstr ""

88556

+msgstr "%s makrosu %d argümanı uygulanıyor: ISO C90 ve ISO C++98 içerisinde boş makro argümanları tanımsızdır"

88557

88558

#: macro.c:2708

88559

#, c-format

88560

@@ -890,38 +865,36 @@

88561

msgid "invalid hash type %d in cpp_macro_definition"

88562

msgstr "cpp_macro_definition içindeki isimli yapı türü %d geçersiz"

88563

88564

-#: pch.c:87 pch.c:335 pch.c:347 pch.c:365 pch.c:371 pch.c:380 pch.c:387

88565

+#: pch.c:87 pch.c:345 pch.c:359 pch.c:377 pch.c:383 pch.c:392 pch.c:399

88566

msgid "while writing precompiled header"

88567

msgstr "önderlemeli başlık yazılırken"

88568

88569

-#: pch.c:607

88570

-#, fuzzy, c-format

88571

-#| msgid "%s: not used because `%s' is defined"

88572

+#: pch.c:619

88573

+#, c-format

88574

msgid "%s: not used because `%.*s' is poisoned"

88575

-msgstr "%s: `%s' tanımlı olduğundan kullanılmadı"

88576

+msgstr "%s: `%.*s' zehirli olduğu için kullanılmadı"

88577

88578

-#: pch.c:629

88579

+#: pch.c:641

88580

#, c-format

88581

msgid "%s: not used because `%.*s' not defined"

88582

msgstr "%s: `%.*s' tanımlı olmadığından kullanılmadı"

88583

88584

-#: pch.c:641

88585

+#: pch.c:653

88586

#, c-format

88587

msgid "%s: not used because `%.*s' defined as `%s' not `%.*s'"

88588

msgstr "%s: `%.*s' kullanılmadı çünkü `%s' olarak tanımlı, `%.*s' değil"

88589

88590

-#: pch.c:682

88591

+#: pch.c:694

88592

#, c-format

88593

msgid "%s: not used because `%s' is defined"

88594

msgstr "%s: `%s' tanımlı olduğundan kullanılmadı"

88595

88596

-#: pch.c:702

88597

-#, fuzzy, c-format

88598

-#| msgid "%s: not used because `%s' is defined"

88599

+#: pch.c:714

88600

+#, c-format

88601

msgid "%s: not used because `__COUNTER__' is invalid"

88602

-msgstr "%s: `%s' tanımlı olduğundan kullanılmadı"

88603

+msgstr "%s: `__COUNTER__' geçersiz olduğundan kullanılmadı"

88604

88605

-#: pch.c:711 pch.c:886

88606

+#: pch.c:723 pch.c:898

88607

msgid "while reading precompiled header"

88608

msgstr "önderlemeli başlık okunurken"

88609

88610

Index: .

88611

===================================================================

88612

--- a/src/. (.../tags/gcc_4_8_2_release)

88613

+++ b/src/. (.../branches/gcc-4_8-branch)

88614

88615

Property changes on: .

88616

___________________________________________________________________

88617

Modified: svn:mergeinfo

88618

Merged /trunk:r202766,204547,206123-206126,206395,206628,207387