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# DP: Changes from the ibm/gcc-4_8-branch (documentation)
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LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@206665 \
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svn://gcc.gnu.org/svn/gcc/branches/ibm/gcc-4_8-branch@208166 \
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| filterdiff --remove-timestamps --addoldprefix=a/src/ --addnewprefix=b/src/
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--- a/src/gcc/doc/extend.texi
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+++ b/src/gcc/doc/extend.texi
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* picoChip Built-in Functions::
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* PowerPC Built-in Functions::
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* PowerPC AltiVec/VSX Built-in Functions::
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+* PowerPC Hardware Transactional Memory Built-in Functions::
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* RX Built-in Functions::
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* S/390 System z Built-in Functions::
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* SH Built-in Functions::
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@@ -13931,6 +13932,531 @@
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@samp{vec_vsx_st} built-in functions always generate the VSX @samp{LXVD2X},
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@samp{LXVW4X}, @samp{STXVD2X}, and @samp{STXVW4X} instructions.
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+If the ISA 2.07 additions to the vector/scalar (power8-vector)
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+instruction set is available, the following additional functions are
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+available for both 32-bit and 64-bit targets. For 64-bit targets, you
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+can use @var{vector long} instead of @var{vector long long},
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+@var{vector bool long} instead of @var{vector bool long long}, and
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+@var{vector unsigned long} instead of @var{vector unsigned long long}.
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+vector long long vec_abs (vector long long);
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+vector long long vec_add (vector long long, vector long long);
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+vector unsigned long long vec_add (vector unsigned long long,
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+ vector unsigned long long);
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+int vec_all_eq (vector long long, vector long long);
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+int vec_all_ge (vector long long, vector long long);
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+int vec_all_gt (vector long long, vector long long);
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+int vec_all_le (vector long long, vector long long);
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+int vec_all_lt (vector long long, vector long long);
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+int vec_all_ne (vector long long, vector long long);
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+int vec_any_eq (vector long long, vector long long);
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+int vec_any_ge (vector long long, vector long long);
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+int vec_any_gt (vector long long, vector long long);
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+int vec_any_le (vector long long, vector long long);
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+int vec_any_lt (vector long long, vector long long);
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+int vec_any_ne (vector long long, vector long long);
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+vector long long vec_eqv (vector long long, vector long long);
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+vector long long vec_eqv (vector bool long long, vector long long);
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+vector long long vec_eqv (vector long long, vector bool long long);
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+vector unsigned long long vec_eqv (vector unsigned long long,
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+ vector unsigned long long);
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+vector unsigned long long vec_eqv (vector bool long long,
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+ vector unsigned long long);
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+vector unsigned long long vec_eqv (vector unsigned long long,
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+ vector bool long long);
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+vector int vec_eqv (vector int, vector int);
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+vector int vec_eqv (vector bool int, vector int);
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+vector int vec_eqv (vector int, vector bool int);
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+vector unsigned int vec_eqv (vector unsigned int, vector unsigned int);
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+vector unsigned int vec_eqv (vector bool unsigned int,
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+ vector unsigned int);
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+vector unsigned int vec_eqv (vector unsigned int,
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+ vector bool unsigned int);
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+vector short vec_eqv (vector short, vector short);
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+vector short vec_eqv (vector bool short, vector short);
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+vector short vec_eqv (vector short, vector bool short);
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+vector unsigned short vec_eqv (vector unsigned short, vector unsigned short);
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+vector unsigned short vec_eqv (vector bool unsigned short,
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+ vector unsigned short);
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+vector unsigned short vec_eqv (vector unsigned short,
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+ vector bool unsigned short);
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+vector signed char vec_eqv (vector signed char, vector signed char);
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+vector signed char vec_eqv (vector bool signed char, vector signed char);
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+vector signed char vec_eqv (vector signed char, vector bool signed char);
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+vector unsigned char vec_eqv (vector unsigned char, vector unsigned char);
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+vector unsigned char vec_eqv (vector bool unsigned char, vector unsigned char);
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+vector unsigned char vec_eqv (vector unsigned char, vector bool unsigned char);
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+vector long long vec_max (vector long long, vector long long);
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+vector unsigned long long vec_max (vector unsigned long long,
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+ vector unsigned long long);
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+vector long long vec_min (vector long long, vector long long);
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+vector unsigned long long vec_min (vector unsigned long long,
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+ vector unsigned long long);
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+vector long long vec_nand (vector long long, vector long long);
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+vector long long vec_nand (vector bool long long, vector long long);
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+vector long long vec_nand (vector long long, vector bool long long);
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+vector unsigned long long vec_nand (vector unsigned long long,
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+ vector unsigned long long);
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+vector unsigned long long vec_nand (vector bool long long,
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+ vector unsigned long long);
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+vector unsigned long long vec_nand (vector unsigned long long,
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+ vector bool long long);
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+vector int vec_nand (vector int, vector int);
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+vector int vec_nand (vector bool int, vector int);
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+vector int vec_nand (vector int, vector bool int);
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+vector unsigned int vec_nand (vector unsigned int, vector unsigned int);
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+vector unsigned int vec_nand (vector bool unsigned int,
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+ vector unsigned int);
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+vector unsigned int vec_nand (vector unsigned int,
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+ vector bool unsigned int);
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+vector short vec_nand (vector short, vector short);
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+vector short vec_nand (vector bool short, vector short);
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+vector short vec_nand (vector short, vector bool short);
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+vector unsigned short vec_nand (vector unsigned short, vector unsigned short);
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+vector unsigned short vec_nand (vector bool unsigned short,
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+ vector unsigned short);
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+vector unsigned short vec_nand (vector unsigned short,
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+ vector bool unsigned short);
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+vector signed char vec_nand (vector signed char, vector signed char);
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+vector signed char vec_nand (vector bool signed char, vector signed char);
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+vector signed char vec_nand (vector signed char, vector bool signed char);
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+vector unsigned char vec_nand (vector unsigned char, vector unsigned char);
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+vector unsigned char vec_nand (vector bool unsigned char, vector unsigned char);
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+vector unsigned char vec_nand (vector unsigned char, vector bool unsigned char);
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+vector long long vec_orc (vector long long, vector long long);
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+vector long long vec_orc (vector bool long long, vector long long);
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+vector long long vec_orc (vector long long, vector bool long long);
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+vector unsigned long long vec_orc (vector unsigned long long,
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+ vector unsigned long long);
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+vector unsigned long long vec_orc (vector bool long long,
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+ vector unsigned long long);
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+vector unsigned long long vec_orc (vector unsigned long long,
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+ vector bool long long);
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+vector int vec_orc (vector int, vector int);
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+vector int vec_orc (vector bool int, vector int);
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+vector int vec_orc (vector int, vector bool int);
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+vector unsigned int vec_orc (vector unsigned int, vector unsigned int);
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+vector unsigned int vec_orc (vector bool unsigned int,
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+ vector unsigned int);
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+vector unsigned int vec_orc (vector unsigned int,
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+ vector bool unsigned int);
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+vector short vec_orc (vector short, vector short);
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+vector short vec_orc (vector bool short, vector short);
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+vector short vec_orc (vector short, vector bool short);
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+vector unsigned short vec_orc (vector unsigned short, vector unsigned short);
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+vector unsigned short vec_orc (vector bool unsigned short,
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+ vector unsigned short);
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+vector unsigned short vec_orc (vector unsigned short,
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+ vector bool unsigned short);
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+vector signed char vec_orc (vector signed char, vector signed char);
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+vector signed char vec_orc (vector bool signed char, vector signed char);
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+vector signed char vec_orc (vector signed char, vector bool signed char);
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+vector unsigned char vec_orc (vector unsigned char, vector unsigned char);
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+vector unsigned char vec_orc (vector bool unsigned char, vector unsigned char);
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+vector unsigned char vec_orc (vector unsigned char, vector bool unsigned char);
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+vector int vec_pack (vector long long, vector long long);
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+vector unsigned int vec_pack (vector unsigned long long,
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+ vector unsigned long long);
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+vector bool int vec_pack (vector bool long long, vector bool long long);
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+vector int vec_packs (vector long long, vector long long);
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+vector unsigned int vec_packs (vector unsigned long long,
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+ vector unsigned long long);
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+vector unsigned int vec_packsu (vector long long, vector long long);
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+vector long long vec_rl (vector long long,
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+ vector unsigned long long);
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+vector long long vec_rl (vector unsigned long long,
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+ vector unsigned long long);
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+vector long long vec_sl (vector long long, vector unsigned long long);
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+vector long long vec_sl (vector unsigned long long,
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+ vector unsigned long long);
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+vector long long vec_sr (vector long long, vector unsigned long long);
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+vector unsigned long long char vec_sr (vector unsigned long long,
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+ vector unsigned long long);
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+vector long long vec_sra (vector long long, vector unsigned long long);
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+vector unsigned long long vec_sra (vector unsigned long long,
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+ vector unsigned long long);
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+vector long long vec_sub (vector long long, vector long long);
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+vector unsigned long long vec_sub (vector unsigned long long,
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+ vector unsigned long long);
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+vector long long vec_unpackh (vector int);
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+vector unsigned long long vec_unpackh (vector unsigned int);
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+vector long long vec_unpackl (vector int);
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+vector unsigned long long vec_unpackl (vector unsigned int);
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+vector long long vec_vaddudm (vector long long, vector long long);
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+vector long long vec_vaddudm (vector bool long long, vector long long);
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+vector long long vec_vaddudm (vector long long, vector bool long long);
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+vector unsigned long long vec_vaddudm (vector unsigned long long,
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+ vector unsigned long long);
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+vector unsigned long long vec_vaddudm (vector bool unsigned long long,
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+ vector unsigned long long);
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+vector unsigned long long vec_vaddudm (vector unsigned long long,
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+ vector bool unsigned long long);
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+vector long long vec_vclz (vector long long);
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+vector unsigned long long vec_vclz (vector unsigned long long);
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+vector int vec_vclz (vector int);
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+vector unsigned int vec_vclz (vector int);
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+vector short vec_vclz (vector short);
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+vector unsigned short vec_vclz (vector unsigned short);
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+vector signed char vec_vclz (vector signed char);
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+vector unsigned char vec_vclz (vector unsigned char);
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+vector signed char vec_vclzb (vector signed char);
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+vector unsigned char vec_vclzb (vector unsigned char);
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+vector long long vec_vclzd (vector long long);
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+vector unsigned long long vec_vclzd (vector unsigned long long);
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+vector short vec_vclzh (vector short);
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+vector unsigned short vec_vclzh (vector unsigned short);
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+vector int vec_vclzw (vector int);
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+vector unsigned int vec_vclzw (vector int);
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+vector long long vec_vmaxsd (vector long long, vector long long);
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+vector unsigned long long vec_vmaxud (vector unsigned long long,
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+ unsigned vector long long);
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+vector long long vec_vminsd (vector long long, vector long long);
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+vector unsigned long long vec_vminud (vector long long,
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+vector int vec_vpksdss (vector long long, vector long long);
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+vector unsigned int vec_vpksdss (vector long long, vector long long);
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+vector unsigned int vec_vpkudus (vector unsigned long long,
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+ vector unsigned long long);
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+vector int vec_vpkudum (vector long long, vector long long);
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+vector unsigned int vec_vpkudum (vector unsigned long long,
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+ vector unsigned long long);
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+vector bool int vec_vpkudum (vector bool long long, vector bool long long);
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+vector long long vec_vpopcnt (vector long long);
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+vector unsigned long long vec_vpopcnt (vector unsigned long long);
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+vector int vec_vpopcnt (vector int);
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+vector unsigned int vec_vpopcnt (vector int);
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+vector short vec_vpopcnt (vector short);
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+vector unsigned short vec_vpopcnt (vector unsigned short);
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+vector signed char vec_vpopcnt (vector signed char);
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+vector unsigned char vec_vpopcnt (vector unsigned char);
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+vector signed char vec_vpopcntb (vector signed char);
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+vector unsigned char vec_vpopcntb (vector unsigned char);
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+vector long long vec_vpopcntd (vector long long);
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+vector unsigned long long vec_vpopcntd (vector unsigned long long);
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+vector short vec_vpopcnth (vector short);
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+vector unsigned short vec_vpopcnth (vector unsigned short);
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+vector int vec_vpopcntw (vector int);
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+vector unsigned int vec_vpopcntw (vector int);
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+vector long long vec_vrld (vector long long, vector unsigned long long);
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+vector unsigned long long vec_vrld (vector unsigned long long,
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+ vector unsigned long long);
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+vector long long vec_vsld (vector long long, vector unsigned long long);
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+vector long long vec_vsld (vector unsigned long long,
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+ vector unsigned long long);
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+vector long long vec_vsrad (vector long long, vector unsigned long long);
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+vector unsigned long long vec_vsrad (vector unsigned long long,
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+ vector unsigned long long);
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+vector long long vec_vsrd (vector long long, vector unsigned long long);
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+vector unsigned long long char vec_vsrd (vector unsigned long long,
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+ vector unsigned long long);
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+vector long long vec_vsubudm (vector long long, vector long long);
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+vector long long vec_vsubudm (vector bool long long, vector long long);
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+vector long long vec_vsubudm (vector long long, vector bool long long);
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+vector unsigned long long vec_vsubudm (vector unsigned long long,
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+ vector unsigned long long);
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+vector unsigned long long vec_vsubudm (vector bool long long,
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+ vector unsigned long long);
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+vector unsigned long long vec_vsubudm (vector unsigned long long,
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+ vector bool long long);
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+vector long long vec_vupkhsw (vector int);
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+vector unsigned long long vec_vupkhsw (vector unsigned int);
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+vector long long vec_vupklsw (vector int);
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+vector unsigned long long vec_vupklsw (vector int);
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+If the cryptographic instructions are enabled (@option{-mcrypto} or
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+@option{-mcpu=power8}), the following builtins are enabled.
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+vector unsigned long long __builtin_crypto_vsbox (vector unsigned long long);
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+vector unsigned long long __builtin_crypto_vcipher (vector unsigned long long,
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+ vector unsigned long long);
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+vector unsigned long long __builtin_crypto_vcipherlast
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+ (vector unsigned long long,
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+ vector unsigned long long);
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+vector unsigned long long __builtin_crypto_vncipher (vector unsigned long long,
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+ vector unsigned long long);
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+vector unsigned long long __builtin_crypto_vncipherlast
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+ (vector unsigned long long,
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+ vector unsigned long long);
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+vector unsigned char __builtin_crypto_vpermxor (vector unsigned char,
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+ vector unsigned char,
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+ vector unsigned char);
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+vector unsigned short __builtin_crypto_vpermxor (vector unsigned short,
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+ vector unsigned short,
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+ vector unsigned short);
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+vector unsigned int __builtin_crypto_vpermxor (vector unsigned int,
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+ vector unsigned int,
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+ vector unsigned int);
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+vector unsigned long long __builtin_crypto_vpermxor (vector unsigned long long,
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+ vector unsigned long long,
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+ vector unsigned long long);
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+vector unsigned char __builtin_crypto_vpmsumb (vector unsigned char,
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+ vector unsigned char);
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+vector unsigned short __builtin_crypto_vpmsumb (vector unsigned short,
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+ vector unsigned short);
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+vector unsigned int __builtin_crypto_vpmsumb (vector unsigned int,
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+ vector unsigned int);
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+vector unsigned long long __builtin_crypto_vpmsumb (vector unsigned long long,
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+ vector unsigned long long);
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+vector unsigned long long __builtin_crypto_vshasigmad
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+ (vector unsigned long long, int, int);
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+vector unsigned int __builtin_crypto_vshasigmaw (vector unsigned int,
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+The second argument to the @var{__builtin_crypto_vshasigmad} and
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+@var{__builtin_crypto_vshasigmaw} builtin functions must be a constant
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+integer that is 0 or 1. The third argument to these builtin functions
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+must be a constant integer in the range of 0 to 15.
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+@node PowerPC Hardware Transactional Memory Built-in Functions
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+@subsection PowerPC Hardware Transactional Memory Built-in Functions
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+GCC provides two interfaces for accessing the Hardware Transactional
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+Memory (HTM) instructions available on some of the PowerPC family
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+of prcoessors (eg, POWER8). The two interfaces come in a low level
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+interface, consisting of built-in functions specific to PowerPC and a
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+higher level interface consisting of inline functions that are common
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+between PowerPC and S/390.
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+@subsubsection PowerPC HTM Low Level Built-in Functions
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+The following low level built-in functions are available with
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+@option{-mhtm} or @option{-mcpu=CPU} where CPU is `power8' or later.
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+They all generate the machine instruction that is part of the name.
371
+The HTM built-ins return true or false depending on their success and
372
+their arguments match exactly the type and order of the associated
373
+hardware instruction's operands. Refer to the ISA manual for a
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+description of each instruction's operands.
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+unsigned int __builtin_tbegin (unsigned int)
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+unsigned int __builtin_tend (unsigned int)
380
+unsigned int __builtin_tabort (unsigned int)
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+unsigned int __builtin_tabortdc (unsigned int, unsigned int, unsigned int)
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+unsigned int __builtin_tabortdci (unsigned int, unsigned int, int)
383
+unsigned int __builtin_tabortwc (unsigned int, unsigned int, unsigned int)
384
+unsigned int __builtin_tabortwci (unsigned int, unsigned int, int)
386
+unsigned int __builtin_tcheck (unsigned int)
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+unsigned int __builtin_treclaim (unsigned int)
388
+unsigned int __builtin_trechkpt (void)
389
+unsigned int __builtin_tsr (unsigned int)
392
+In addition to the above HTM built-ins, we have added built-ins for
393
+some common extended mnemonics of the HTM instructions:
396
+unsigned int __builtin_tendall (void)
397
+unsigned int __builtin_tresume (void)
398
+unsigned int __builtin_tsuspend (void)
401
+The following set of built-in functions are available to gain access
402
+to the HTM specific special purpose registers.
405
+unsigned long __builtin_get_texasr (void)
406
+unsigned long __builtin_get_texasru (void)
407
+unsigned long __builtin_get_tfhar (void)
408
+unsigned long __builtin_get_tfiar (void)
410
+void __builtin_set_texasr (unsigned long);
411
+void __builtin_set_texasru (unsigned long);
412
+void __builtin_set_tfhar (unsigned long);
413
+void __builtin_set_tfiar (unsigned long);
416
+Example usage of these low level built-in functions may look like:
419
+#include <htmintrin.h>
421
+int num_retries = 10;
425
+ if (__builtin_tbegin (0))
427
+ /* Transaction State Initiated. */
428
+ if (is_locked (lock))
429
+ __builtin_tabort (0);
430
+ ... transaction code...
431
+ __builtin_tend (0);
436
+ /* Transaction State Failed. Use locks if the transaction
437
+ failure is "persistent" or we've tried too many times. */
438
+ if (num_retries-- <= 0
439
+ || _TEXASRU_FAILURE_PERSISTENT (__builtin_get_texasru ()))
441
+ acquire_lock (lock);
442
+ ... non transactional fallback path...
443
+ release_lock (lock);
450
+One final built-in function has been added that returns the value of
451
+the 2-bit Transaction State field of the Machine Status Register (MSR)
452
+as stored in @code{CR0}.
455
+unsigned long __builtin_ttest (void)
458
+This built-in can be used to determine the current transaction state
459
+using the following code example:
462
+#include <htmintrin.h>
464
+unsigned char tx_state = _HTM_STATE (__builtin_ttest ());
466
+if (tx_state == _HTM_TRANSACTIONAL)
468
+ /* Code to use in transactional state. */
470
+else if (tx_state == _HTM_NONTRANSACTIONAL)
472
+ /* Code to use in non-transactional state. */
474
+else if (tx_state == _HTM_SUSPENDED)
476
+ /* Code to use in transaction suspended state. */
480
+@subsubsection PowerPC HTM High Level Inline Functions
482
+The following high level HTM interface is made available by including
483
+@code{<htmxlintrin.h>} and using @option{-mhtm} or @option{-mcpu=CPU}
484
+where CPU is `power8' or later. This interface is common between PowerPC
485
+and S/390, allowing users to write one HTM source implementation that
486
+can be compiled and executed on either system.
489
+long __TM_simple_begin (void)
490
+long __TM_begin (void* const TM_buff)
491
+long __TM_end (void)
492
+void __TM_abort (void)
493
+void __TM_named_abort (unsigned char const code)
494
+void __TM_resume (void)
495
+void __TM_suspend (void)
497
+long __TM_is_user_abort (void* const TM_buff)
498
+long __TM_is_named_user_abort (void* const TM_buff, unsigned char *code)
499
+long __TM_is_illegal (void* const TM_buff)
500
+long __TM_is_footprint_exceeded (void* const TM_buff)
501
+long __TM_nesting_depth (void* const TM_buff)
502
+long __TM_is_nested_too_deep(void* const TM_buff)
503
+long __TM_is_conflict(void* const TM_buff)
504
+long __TM_is_failure_persistent(void* const TM_buff)
505
+long __TM_failure_address(void* const TM_buff)
506
+long long __TM_failure_code(void* const TM_buff)
509
+Using these common set of HTM inline functions, we can create
510
+a more portable version of the HTM example in the previous
511
+section that will work on either PowerPC or S/390:
514
+#include <htmxlintrin.h>
516
+int num_retries = 10;
517
+TM_buff_type TM_buff;
521
+ if (__TM_begin (TM_buff))
523
+ /* Transaction State Initiated. */
524
+ if (is_locked (lock))
526
+ ... transaction code...
532
+ /* Transaction State Failed. Use locks if the transaction
533
+ failure is "persistent" or we've tried too many times. */
534
+ if (num_retries-- <= 0
535
+ || __TM_is_failure_persistent (TM_buff))
537
+ acquire_lock (lock);
538
+ ... non transactional fallback path...
539
+ release_lock (lock);
546
@node RX Built-in Functions
547
@subsection RX Built-in Functions
548
GCC supports some of the RX instructions which cannot be expressed in
549
--- a/src/gcc/doc/invoke.texi
550
+++ b/src/gcc/doc/invoke.texi
552
-mno-recip-precision @gol
553
-mveclibabi=@var{type} -mfriz -mno-friz @gol
554
-mpointers-to-nested-functions -mno-pointers-to-nested-functions @gol
555
--msave-toc-indirect -mno-save-toc-indirect}
556
+-msave-toc-indirect -mno-save-toc-indirect @gol
557
+-mpower8-fusion -mno-mpower8-fusion -mpower8-vector -mno-power8-vector @gol
558
+-mcrypto -mno-crypto -mdirect-move -mno-direct-move @gol
559
+-mquad-memory -mno-quad-memory @gol
560
+-mquad-memory-atomic -mno-quad-memory-atomic @gol
561
+-mcompat-align-parm -mno-compat-align-parm}
564
@gccoptlist{-m64bit-doubles -m32bit-doubles -fpu -nofpu@gol
565
@@ -17237,7 +17242,9 @@
566
@gccoptlist{-maltivec -mfprnd -mhard-float -mmfcrf -mmultiple @gol
567
-mpopcntb -mpopcntd -mpowerpc64 @gol
568
-mpowerpc-gpopt -mpowerpc-gfxopt -msingle-float -mdouble-float @gol
569
--msimple-fpu -mstring -mmulhw -mdlmzb -mmfpgpr -mvsx}
570
+-msimple-fpu -mstring -mmulhw -mdlmzb -mmfpgpr -mvsx @gol
571
+-mcrypto -mdirect-move -mpower8-fusion -mpower8-vector @gol
572
+-mquad-memory -mquad-memory-atomic}
574
The particular options set for any particular CPU varies between
575
compiler versions, depending on what setting seems to produce optimal
576
@@ -17288,6 +17295,38 @@
577
@option{-mabi=altivec} to adjust the current ABI with AltiVec ABI
580
+When @option{-maltivec} is used, rather than @option{-maltivec=le} or
581
+@option{-maltivec=be}, the element order for Altivec intrinsics such
582
+as @code{vec_splat}, @code{vec_extract}, and @code{vec_insert} will
583
+match array element order corresponding to the endianness of the
584
+target. That is, element zero identifies the leftmost element in a
585
+vector register when targeting a big-endian platform, and identifies
586
+the rightmost element in a vector register when targeting a
587
+little-endian platform.
590
+@opindex maltivec=be
591
+Generate Altivec instructions using big-endian element order,
592
+regardless of whether the target is big- or little-endian. This is
593
+the default when targeting a big-endian platform.
595
+The element order is used to interpret element numbers in Altivec
596
+intrinsics such as @code{vec_splat}, @code{vec_extract}, and
597
+@code{vec_insert}. By default, these will match array element order
598
+corresponding to the endianness for the target.
601
+@opindex maltivec=le
602
+Generate Altivec instructions using little-endian element order,
603
+regardless of whether the target is big- or little-endian. This is
604
+the default when targeting a little-endian platform. This option is
605
+currently ignored when targeting a big-endian platform.
607
+The element order is used to interpret element numbers in Altivec
608
+intrinsics such as @code{vec_splat}, @code{vec_extract}, and
609
+@code{vec_insert}. By default, these will match array element order
610
+corresponding to the endianness for the target.
615
@@ -17355,6 +17394,55 @@
616
instructions, and also enable the use of built-in functions that allow
617
more direct access to the VSX instruction set.
623
+Enable the use (disable) of the built-in functions that allow direct
624
+access to the cryptographic instructions that were added in version
625
+2.07 of the PowerPC ISA.
628
+@itemx -mno-direct-move
629
+@opindex mdirect-move
630
+@opindex mno-direct-move
631
+Generate code that uses (does not use) the instructions to move data
632
+between the general purpose registers and the vector/scalar (VSX)
633
+registers that were added in version 2.07 of the PowerPC ISA.
635
+@item -mpower8-fusion
636
+@itemx -mno-power8-fusion
637
+@opindex mpower8-fusion
638
+@opindex mno-power8-fusion
639
+Generate code that keeps (does not keeps) some integer operations
640
+adjacent so that the instructions can be fused together on power8 and
643
+@item -mpower8-vector
644
+@itemx -mno-power8-vector
645
+@opindex mpower8-vector
646
+@opindex mno-power8-vector
647
+Generate code that uses (does not use) the vector and scalar
648
+instructions that were added in version 2.07 of the PowerPC ISA. Also
649
+enable the use of built-in functions that allow more direct access to
650
+the vector instructions.
653
+@itemx -mno-quad-memory
654
+@opindex mquad-memory
655
+@opindex mno-quad-memory
656
+Generate code that uses (does not use) the non-atomic quad word memory
657
+instructions. The @option{-mquad-memory} option requires use of
660
+@item -mquad-memory-atomic
661
+@itemx -mno-quad-memory-atomic
662
+@opindex mquad-memory-atomic
663
+@opindex mno-quad-memory-atomic
664
+Generate code that uses (does not use) the atomic quad word memory
665
+instructions. The @option{-mquad-memory-atomic} option requires use of
668
@item -mfloat-gprs=@var{yes/single/double/no}
671
@@ -17774,7 +17862,8 @@
673
Extend the current ABI with a particular extension, or remove such extension.
674
Valid values are @var{altivec}, @var{no-altivec}, @var{spe},
675
-@var{no-spe}, @var{ibmlongdouble}, @var{ieeelongdouble}@.
676
+@var{no-spe}, @var{ibmlongdouble}, @var{ieeelongdouble},
677
+@var{elfv1}, @var{elfv2}@.
681
@@ -17796,6 +17885,20 @@
682
Change the current ABI to use IEEE extended-precision long double.
683
This is a PowerPC 32-bit Linux ABI option.
687
+Change the current ABI to use the ELFv1 ABI.
688
+This is the default ABI for big-endian PowerPC 64-bit Linux.
689
+Overriding the default ABI requires special system support and is
690
+likely to fail in spectacular ways.
694
+Change the current ABI to use the ELFv2 ABI.
695
+This is the default ABI for little-endian PowerPC 64-bit Linux.
696
+Overriding the default ABI requires special system support and is
697
+likely to fail in spectacular ways.
700
@itemx -mno-prototype
702
@@ -18081,6 +18184,23 @@
703
a pointer on AIX and 64-bit Linux systems. If the TOC value is not
704
saved in the prologue, it is saved just before the call through the
705
pointer. The @option{-mno-save-toc-indirect} option is the default.
707
+@item -mcompat-align-parm
708
+@itemx -mno-compat-align-parm
709
+@opindex mcompat-align-parm
710
+Generate (do not generate) code to pass structure parameters with a
711
+maximum alignment of 64 bits, for compatibility with older versions
714
+Older versions of GCC (prior to 4.9.0) incorrectly did not align a
715
+structure parameter on a 128-bit boundary when that structure contained
716
+a member requiring 128-bit alignment. This is corrected in more
717
+recent versions of GCC. This option may be used to generate code
718
+that is compatible with functions compiled with older versions of
721
+In this version of the compiler, the @option{-mcompat-align-parm}
722
+is the default, except when using the Linux ELFv2 ABI.
726
--- a/src/gcc/doc/md.texi
727
+++ b/src/gcc/doc/md.texi
728
@@ -2055,7 +2055,7 @@
732
-@item PowerPC and IBM RS6000---@file{config/rs6000/rs6000.h}
733
+@item PowerPC and IBM RS6000---@file{config/rs6000/constraints.md}
736
Address base register
737
@@ -2069,18 +2069,58 @@
739
Altivec vector register
742
+Any VSX register if the -mvsx option was used or NO_REGS.
745
-VSX vector register to hold vector double data
746
+VSX vector register to hold vector double data or NO_REGS.
749
-VSX vector register to hold vector float data
750
+VSX vector register to hold vector float data or NO_REGS.
753
+If @option{-mmfpgpr} was used, a floating point register or NO_REGS.
756
+Floating point register if the LFIWAX instruction is enabled or NO_REGS.
759
+VSX register if direct move instructions are enabled, or NO_REGS.
762
+No register (NO_REGS).
765
+General purpose register if 64-bit instructions are enabled or NO_REGS.
768
-VSX vector register to hold scalar float data
769
+VSX vector register to hold scalar double values or NO_REGS.
774
+VSX vector register to hold 128 bit integer or NO_REGS.
777
+Altivec register to use for float/32-bit int loads/stores or NO_REGS.
780
+Altivec register to use for double loads/stores or NO_REGS.
783
+FP or VSX register to perform float operations under @option{-mvsx} or NO_REGS.
786
+Floating point register if the STFIWX instruction is enabled or NO_REGS.
789
+VSX vector register to hold scalar float values or NO_REGS.
792
+Floating point register if the LFIWZX instruction is enabled or NO_REGS.
795
+A memory address that will work with the @code{lq} and @code{stq}
799
@samp{MQ}, @samp{CTR}, or @samp{LINK} register
added
removed
.svn/pristine/7c/7c8ee749253d8671930a477eed23520c813d12b9.svn-base
