~ubuntu-branches/debian/sid/gcc-4.8/sid : revision 78

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# DP: updates from the 4.8 branch upto 20140505 (r210076).

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last_updated()

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{

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cat > ${dir}LAST_UPDATED <<EOF

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Mon May 5 20:24:06 CEST 2014

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Mon May 5 18:24:06 UTC 2014 (revision 210076)

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EOF

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}

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LANG=C svn diff svn://gcc.gnu.org/svn/gcc/tags/gcc_4_8_2_release svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch \

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| sed -r 's,^--- (\S+)\t(\S+)(.*)$,--- a/src/\1\t\2,;s,^\+\+\+ (\S+)\t(\S+)(.*)$,+++ b/src/\1\t\2,' \

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| awk '/^Index:.*\.(class|texi)/ {skip=1; next} /^Index:/ { skip=0 } skip==0'

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Index: libitm/configure

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===================================================================

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--- a/src/libitm/configure (.../tags/gcc_4_8_2_release)

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+++ b/src/libitm/configure (.../branches/gcc-4_8-branch)

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@@ -7270,7 +7270,7 @@

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rm -rf conftest*

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;;

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-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \

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+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \

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s390*-*linux*|s390*-*tpf*|sparc*-*linux*)

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# Find out which ABI we are using.

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echo 'int i;' > conftest.$ac_ext

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@@ -7295,7 +7295,10 @@

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;;

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esac

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;;

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- ppc64-*linux*|powerpc64-*linux*)

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+ powerpc64le-*linux*)

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+ LD="${LD-ld} -m elf32lppclinux"

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+ ;;

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+ powerpc64-*linux*)

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LD="${LD-ld} -m elf32ppclinux"

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;;

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s390x-*linux*)

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@@ -7314,7 +7317,10 @@

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x86_64-*linux*)

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LD="${LD-ld} -m elf_x86_64"

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;;

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- ppc*-*linux*|powerpc*-*linux*)

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+ powerpcle-*linux*)

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+ LD="${LD-ld} -m elf64lppc"

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+ ;;

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+ powerpc-*linux*)

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LD="${LD-ld} -m elf64ppc"

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;;

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s390*-*linux*|s390*-*tpf*)

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@@ -11779,7 +11785,7 @@

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lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

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lt_status=$lt_dlunknown

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cat > conftest.$ac_ext <<_LT_EOF

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-#line 11782 "configure"

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+#line 11788 "configure"

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#include "confdefs.h"

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#if HAVE_DLFCN_H

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@@ -11885,7 +11891,7 @@

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lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

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lt_status=$lt_dlunknown

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cat > conftest.$ac_ext <<_LT_EOF

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-#line 11888 "configure"

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+#line 11894 "configure"

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#include "confdefs.h"

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#if HAVE_DLFCN_H

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@@ -17362,6 +17368,43 @@

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fi

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;;

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+esac

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+

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+case "${target_cpu}" in

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+powerpc*)

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+ { $as_echo "$as_me:${as_lineno-$LINENO}: checking if the assembler supports HTM" >&5

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+$as_echo_n "checking if the assembler supports HTM... " >&6; }

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+if test "${libitm_cv_as_htm+set}" = set; then :

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+ $as_echo_n "(cached) " >&6

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+else

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+

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+ cat confdefs.h - <<_ACEOF >conftest.$ac_ext

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+/* end confdefs.h. */

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+

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+int

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+main ()

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+{

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+asm("tbegin. 0; tend. 0");

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+ ;

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+ return 0;

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+}

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+_ACEOF

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+if ac_fn_c_try_compile "$LINENO"; then :

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+ libitm_cv_as_htm=yes

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+else

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+ libitm_cv_as_htm=no

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+fi

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+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext

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+

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+fi

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+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $libitm_cv_as_htm" >&5

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+$as_echo "$libitm_cv_as_htm" >&6; }

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+ if test x$libitm_cv_as_htm = xyes; then

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+

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+$as_echo "#define HAVE_AS_HTM 1" >>confdefs.h

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+

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+ fi

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+ ;;

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s390*)

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{ $as_echo "$as_me:${as_lineno-$LINENO}: checking if the assembler supports HTM" >&5

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$as_echo_n "checking if the assembler supports HTM... " >&6; }

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@@ -17399,7 +17442,6 @@

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fi

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;;

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esac

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-LIBITM_CHECK_AS_HTM

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{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether weak refs work like ELF" >&5

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Index: libitm/configure.tgt

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===================================================================

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--- a/src/libitm/configure.tgt (.../tags/gcc_4_8_2_release)

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+++ b/src/libitm/configure.tgt (.../branches/gcc-4_8-branch)

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@@ -47,7 +47,10 @@

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# work out any special compilation flags as necessary.

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case "${target_cpu}" in

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alpha*) ARCH=alpha ;;

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- rs6000 | powerpc*) ARCH=powerpc ;;

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+ rs6000 | powerpc*)

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+ XCFLAGS="${XCFLAGS} -mhtm"

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+ ARCH=powerpc

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+ ;;

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arm*) ARCH=arm ;;

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138

Index: libitm/ChangeLog

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===================================================================

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--- a/src/libitm/ChangeLog (.../tags/gcc_4_8_2_release)

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+++ b/src/libitm/ChangeLog (.../branches/gcc-4_8-branch)

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@@ -1,3 +1,62 @@

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+2014-04-14 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>

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+

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+ * acinclude.m4: Move s390* case from RTM to HTM check.

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+ * configure: Regenerate.

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+

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+2014-04-09 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>

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+

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+ * config/generic/asmcfi.h: Also check for

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+ __GCC_HAVE_DWARF2_CFI_ASM.

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+

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+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

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+

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+ Backport from mainline r204808:

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+

157

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

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+

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+ * config/powerpc/sjlj.S [__powerpc64__ && _CALL_ELF == 2]:

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+ (FUNC): Define ELFv2 variant.

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+ (END): Likewise.

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+ (HIDDEN): Likewise.

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+ (CALL): Likewise.

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+ (BASE): Likewise.

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+ (LR_SAVE): Likewise.

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+

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+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

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+

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+ Power8 HTM Support

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+ Backport from mainline

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+ * acinclude.m4 (LIBITM_CHECK_AS_HTM): New.

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+ * configure: Rebuild.

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+ * configure.tgt (target_cpu): Add -mhtm to XCFLAGS.

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+ * config/powerpc/target.h: Include sys/auxv.h and htmintrin.h.

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+ (USE_HTM_FASTPATH): Define.

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+ (_TBEGIN_STARTED, _TBEGIN_INDETERMINATE, _TBEGIN_PERSISTENT)

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+ (_HTM_RETRIES) New macros.

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+ (htm_abort, htm_abort_should_retry, htm_available, htm_begin, htm_init)

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+ (htm_begin_success, htm_commit, htm_transaction_active): New functions.

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+

181

+2014-03-26 Jakub Jelinek <jakub@redhat.com>

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+

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+ * config/linux/futex_bits.h: Include errno.h.

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+ (sys_futex0): If syscall returns -1, return -errno rather than

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+ -1.

186

+

187

+2014-03-03 Peter Bergner <bergner@vnet.ibm.com>

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+

189

+ Backport from mainline

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+ 2013-06-20 Torvald Riegel <triegel@redhat.com>

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+

192

+ * query.cc (_ITM_inTransaction): Abort when using the HTM fastpath.

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+ (_ITM_getTransactionId): Same.

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+ * config/x86/target.h (htm_transaction_active): New.

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+

196

+ 2013-06-20 Torvald Riegel <triegel@redhat.com>

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+

198

+ PR libitm/57643

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+ * beginend.cc (gtm_thread::begin_transaction): Handle reentrancy in

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+ the HTM fastpath.

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+

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2013-10-16 Release Manager

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204

* GCC 4.8.2 released.

205

@@ -8,13 +67,12 @@

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2013-08-02 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>

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208

* configure.tgt: Add -msoft-float to XCFLAGS.

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-

210

211

2013-08-14 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>

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213

* config/s390/sjlj.S: Add file missing from last commit.

214

* config/s390/target.h: Likewise.

215

-

216

+

217

2013-08-02 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>

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219

Backports from mainline:

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Index: libitm/query.cc

221

===================================================================

222

--- a/src/libitm/query.cc (.../tags/gcc_4_8_2_release)

223

+++ b/src/libitm/query.cc (.../branches/gcc-4_8-branch)

224

@@ -43,6 +43,15 @@

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_ITM_howExecuting ITM_REGPARM

226

_ITM_inTransaction (void)

227

{

228

+#if defined(USE_HTM_FASTPATH)

229

+ // If we use the HTM fastpath, we cannot reliably detect whether we are

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+ // in a transaction because this function can be called outside of

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+ // a transaction and thus we can't deduce this by looking at just the serial

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+ // lock. This function isn't used in practice currently, so the easiest

233

+ // way to handle it is to just abort.

234

+ if (htm_fastpath && htm_transaction_active())

235

+ htm_abort();

236

+#endif

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struct gtm_thread *tx = gtm_thr();

238

if (tx && (tx->nesting > 0))

239

{

240

@@ -58,6 +67,11 @@

241

_ITM_transactionId_t ITM_REGPARM

242

_ITM_getTransactionId (void)

243

{

244

+#if defined(USE_HTM_FASTPATH)

245

+ // See ITM_inTransaction.

246

+ if (htm_fastpath && htm_transaction_active())

247

+ htm_abort();

248

+#endif

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struct gtm_thread *tx = gtm_thr();

250

return (tx && (tx->nesting > 0)) ? tx->id : _ITM_noTransactionId;

251

}

252

Index: libitm/beginend.cc

253

===================================================================

254

--- a/src/libitm/beginend.cc (.../tags/gcc_4_8_2_release)

255

+++ b/src/libitm/beginend.cc (.../branches/gcc-4_8-branch)

256

@@ -197,6 +197,8 @@

257

// We are executing a transaction now.

258

// Monitor the writer flag in the serial-mode lock, and abort

259

// if there is an active or waiting serial-mode transaction.

260

+ // Note that this can also happen due to an enclosing

261

+ // serial-mode transaction; we handle this case below.

262

if (unlikely(serial_lock.is_write_locked()))

263

htm_abort();

264

else

265

@@ -219,6 +221,14 @@

266

tx = new gtm_thread();

267

set_gtm_thr(tx);

268

}

269

+ // Check whether there is an enclosing serial-mode transaction;

270

+ // if so, we just continue as a nested transaction and don't

271

+ // try to use the HTM fastpath. This case can happen when an

272

+ // outermost relaxed transaction calls unsafe code that starts

273

+ // a transaction.

274

+ if (tx->nesting > 0)

275

+ break;

276

+ // Another thread is running a serial-mode transaction. Wait.

277

serial_lock.read_lock(tx);

278

serial_lock.read_unlock(tx);

279

// TODO We should probably reset the retry count t here, unless

280

Index: libitm/config/linux/futex_bits.h

281

===================================================================

282

--- a/src/libitm/config/linux/futex_bits.h (.../tags/gcc_4_8_2_release)

283

+++ b/src/libitm/config/linux/futex_bits.h (.../branches/gcc-4_8-branch)

284

@@ -31,9 +31,13 @@

285

286

#include <unistd.h>

287

#include <sys/syscall.h>

288

+#include <errno.h>

289

290

static inline long

291

sys_futex0 (std::atomic<int> *addr, long op, long val)

292

{

293

- return syscall (SYS_futex, (int*) addr, op, val, 0);

294

+ long res = syscall (SYS_futex, (int*) addr, op, val, 0);

295

+ if (__builtin_expect (res == -1, 0))

296

+ return -errno;

297

+ return res;

298

}

299

Index: libitm/config/powerpc/sjlj.S

300

===================================================================

301

--- a/src/libitm/config/powerpc/sjlj.S (.../tags/gcc_4_8_2_release)

302

+++ b/src/libitm/config/powerpc/sjlj.S (.../branches/gcc-4_8-branch)

303

@@ -26,8 +26,27 @@

304

305

#include "asmcfi.h"

306

307

-#if defined(__powerpc64__) && defined(__ELF__)

308

+#if defined(__powerpc64__) && _CALL_ELF == 2

309

.macro FUNC name

310

+ .globl \name

311

+ .type \name, @function

312

+\name:

313

+0: addis 2,12,(.TOC.-0b)@ha

314

+ addi 2,2,(.TOC.-0b)@l

315

+ .localentry \name, . - \name

316

+.endm

317

+.macro END name

318

+ .size \name, . - \name

319

+.endm

320

+.macro HIDDEN name

321

+ .hidden \name

322

+.endm

323

+.macro CALL name

324

+ bl \name

325

+ nop

326

+.endm

327

+#elif defined(__powerpc64__) && defined(__ELF__)

328

+.macro FUNC name

329

.globl \name, .\name

330

.section ".opd","aw"

331

.align 3

332

@@ -117,6 +136,9 @@

333

#if defined(_CALL_AIXDESC)

334

# define BASE 6*WS

335

# define LR_SAVE 2*WS

336

+#elif _CALL_ELF == 2

337

+# define BASE 6*WS

338

+# define LR_SAVE 2*WS

339

#elif defined(_CALL_SYSV)

340

# define BASE 2*WS

341

# define LR_SAVE 1*WS

342

Index: libitm/config/powerpc/target.h

343

===================================================================

344

--- a/src/libitm/config/powerpc/target.h (.../tags/gcc_4_8_2_release)

345

+++ b/src/libitm/config/powerpc/target.h (.../branches/gcc-4_8-branch)

346

@@ -22,6 +22,10 @@

347

see the files COPYING3 and COPYING.RUNTIME respectively. If not, see

348

<http://www.gnu.org/licenses/>. */

349

350

+#ifdef HAVE_SYS_AUXV_H

351

+#include <sys/auxv.h>

352

+#endif

353

+

354

namespace GTM HIDDEN {

355

356

typedef int v128 __attribute__((vector_size(16), may_alias, aligned(16)));

357

@@ -55,4 +59,82 @@

358

__asm volatile ("" : : : "memory");

359

}

360

361

+// Use HTM if it is supported by the system.

362

+// See gtm_thread::begin_transaction for how these functions are used.

363

+#if defined (__linux__) \

364

+ && defined (HAVE_AS_HTM) \

365

+ && defined (HAVE_GETAUXVAL) \

366

+ && defined (AT_HWCAP2) \

367

+ && defined (PPC_FEATURE2_HAS_HTM)

368

+

369

+#include <htmintrin.h>

370

+

371

+#define USE_HTM_FASTPATH

372

+

373

+#define _TBEGIN_STARTED 0

374

+#define _TBEGIN_INDETERMINATE 1

375

+#define _TBEGIN_PERSISTENT 2

376

+

377

+/* Number of retries for transient failures. */

378

+#define _HTM_RETRIES 10

379

+

380

+static inline bool

381

+htm_available (void)

382

+{

383

+ return (getauxval (AT_HWCAP2) & PPC_FEATURE2_HAS_HTM) ? true : false;

384

+}

385

+

386

+static inline uint32_t

387

+htm_init (void)

388

+{

389

+ // Maximum number of times we try to execute a transaction

390

+ // as a HW transaction.

391

+ return htm_available () ? _HTM_RETRIES : 0;

392

+}

393

+

394

+static inline uint32_t

395

+htm_begin (void)

396

+{

397

+ if (__builtin_expect (__builtin_tbegin (0), 1))

398

+ return _TBEGIN_STARTED;

399

+

400

+ if (_TEXASRU_FAILURE_PERSISTENT (__builtin_get_texasru ()))

401

+ return _TBEGIN_PERSISTENT;

402

+

403

+ return _TBEGIN_INDETERMINATE;

404

+}

405

+

406

+static inline bool

407

+htm_begin_success (uint32_t begin_ret)

408

+{

409

+ return begin_ret == _TBEGIN_STARTED;

410

+}

411

+

412

+static inline void

413

+htm_commit (void)

414

+{

415

+ __builtin_tend (0);

416

+}

417

+

418

+static inline void

419

+htm_abort (void)

420

+{

421

+ __builtin_tabort (0);

422

+}

423

+

424

+static inline bool

425

+htm_abort_should_retry (uint32_t begin_ret)

426

+{

427

+ return begin_ret != _TBEGIN_PERSISTENT;

428

+}

429

+

430

+/* Returns true iff a hardware transaction is currently being executed. */

431

+static inline bool

432

+htm_transaction_active (void)

433

+{

434

+ return (_HTM_STATE (__builtin_ttest ()) == _HTM_TRANSACTIONAL);

435

+}

436

+

437

+#endif

438

+

439

} // namespace GTM

440

Index: libitm/config/x86/target.h

441

===================================================================

442

--- a/src/libitm/config/x86/target.h (.../tags/gcc_4_8_2_release)

443

+++ b/src/libitm/config/x86/target.h (.../branches/gcc-4_8-branch)

444

@@ -125,6 +125,13 @@

445

{

446

return begin_ret & _XABORT_RETRY;

447

}

448

+

449

+/* Returns true iff a hardware transaction is currently being executed. */

450

+static inline bool

451

+htm_transaction_active ()

452

+{

453

+ return _xtest() != 0;

454

+}

455

#endif

456

457

458

Index: libitm/config/generic/asmcfi.h

459

===================================================================

460

--- a/src/libitm/config/generic/asmcfi.h (.../tags/gcc_4_8_2_release)

461

+++ b/src/libitm/config/generic/asmcfi.h (.../branches/gcc-4_8-branch)

462

@@ -24,7 +24,7 @@

463

464

#include "config.h"

465

466

-#ifdef HAVE_AS_CFI_PSEUDO_OP

467

+#if defined(HAVE_AS_CFI_PSEUDO_OP) && defined(__GCC_HAVE_DWARF2_CFI_ASM)

468

469

#define cfi_startproc .cfi_startproc

470

#define cfi_endproc .cfi_endproc

471

@@ -50,4 +50,4 @@

472

#define cfi_restore(r)

473

#define cfi_undefined(r)

474

475

-#endif /* HAVE_AS_CFI_PSEUDO_OP */

476

+#endif /* HAVE_AS_CFI_PSEUDO_OP && __GCC_HAVE_DWARF2_CFI_ASM */

477

Index: libitm/acinclude.m4

478

===================================================================

479

--- a/src/libitm/acinclude.m4 (.../tags/gcc_4_8_2_release)

480

+++ b/src/libitm/acinclude.m4 (.../branches/gcc-4_8-branch)

481

@@ -121,12 +121,26 @@

482

AC_DEFINE(HAVE_AS_RTM, 1, [Define to 1 if the assembler supports RTM.])

483

fi

484

;;

485

+esac])

486

+

487

+dnl Check if as supports HTM instructions.

488

+AC_DEFUN([LIBITM_CHECK_AS_HTM], [

489

+case "${target_cpu}" in

490

+powerpc*)

491

+ AC_CACHE_CHECK([if the assembler supports HTM], libitm_cv_as_htm, [

492

+ AC_TRY_COMPILE([], [asm("tbegin. 0; tend. 0");],

493

+ [libitm_cv_as_htm=yes], [libitm_cv_as_htm=no])

494

+ ])

495

+ if test x$libitm_cv_as_htm = xyes; then

496

+ AC_DEFINE(HAVE_AS_HTM, 1, [Define to 1 if the assembler supports HTM.])

497

+ fi

498

+ ;;

499

s390*)

500

AC_CACHE_CHECK([if the assembler supports HTM], libitm_cv_as_htm, [

501

save_CFLAGS="$CFLAGS"

502

CFLAGS="$CFLAGS -march=zEC12"

503

AC_TRY_COMPILE([], [asm("tbegin 0,0; tend");],

504

- [libitm_cv_as_htm=yes], [libitm_cv_as_htm=no])

505

+ [libitm_cv_as_htm=yes], [libitm_cv_as_htm=no])

506

CFLAGS="$save_CFLAGS"])

507

if test x$libitm_cv_as_htm = xyes; then

508

AC_DEFINE(HAVE_AS_HTM, 1, [Define to 1 if the assembler supports HTM.])

509

Index: libtool.m4

510

===================================================================

511

--- a/src/libtool.m4 (.../tags/gcc_4_8_2_release)

512

+++ b/src/libtool.m4 (.../branches/gcc-4_8-branch)

513

@@ -1220,7 +1220,7 @@

514

rm -rf conftest*

515

;;

516

517

-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \

518

+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \

519

s390*-*linux*|s390*-*tpf*|sparc*-*linux*)

520

# Find out which ABI we are using.

521

echo 'int i;' > conftest.$ac_ext

522

@@ -1241,7 +1241,10 @@

523

;;

524

esac

525

;;

526

- ppc64-*linux*|powerpc64-*linux*)

527

+ powerpc64le-*linux*)

528

+ LD="${LD-ld} -m elf32lppclinux"

529

+ ;;

530

+ powerpc64-*linux*)

531

LD="${LD-ld} -m elf32ppclinux"

532

;;

533

s390x-*linux*)

534

@@ -1260,7 +1263,10 @@

535

x86_64-*linux*)

536

LD="${LD-ld} -m elf_x86_64"

537

;;

538

- ppc*-*linux*|powerpc*-*linux*)

539

+ powerpcle-*linux*)

540

+ LD="${LD-ld} -m elf64lppc"

541

+ ;;

542

+ powerpc-*linux*)

543

LD="${LD-ld} -m elf64ppc"

544

;;

545

s390*-*linux*|s390*-*tpf*)

546

Index: libgomp/configure

547

===================================================================

548

--- a/src/libgomp/configure (.../tags/gcc_4_8_2_release)

549

+++ b/src/libgomp/configure (.../branches/gcc-4_8-branch)

550

@@ -6580,7 +6580,7 @@

551

rm -rf conftest*

552

;;

553

554

-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \

555

+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \

556

s390*-*linux*|s390*-*tpf*|sparc*-*linux*)

557

# Find out which ABI we are using.

558

echo 'int i;' > conftest.$ac_ext

559

@@ -6605,7 +6605,10 @@

560

;;

561

esac

562

;;

563

- ppc64-*linux*|powerpc64-*linux*)

564

+ powerpc64le-*linux*)

565

+ LD="${LD-ld} -m elf32lppclinux"

566

+ ;;

567

+ powerpc64-*linux*)

568

LD="${LD-ld} -m elf32ppclinux"

569

;;

570

s390x-*linux*)

571

@@ -6624,7 +6627,10 @@

572

x86_64-*linux*)

573

LD="${LD-ld} -m elf_x86_64"

574

;;

575

- ppc*-*linux*|powerpc*-*linux*)

576

+ powerpcle-*linux*)

577

+ LD="${LD-ld} -m elf64lppc"

578

+ ;;

579

+ powerpc-*linux*)

580

LD="${LD-ld} -m elf64ppc"

581

;;

582

s390*-*linux*|s390*-*tpf*)

583

@@ -11088,7 +11094,7 @@

584

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

585

lt_status=$lt_dlunknown

586

cat > conftest.$ac_ext <<_LT_EOF

587

-#line 11091 "configure"

588

+#line 11097 "configure"

589

#include "confdefs.h"

590

591

#if HAVE_DLFCN_H

592

@@ -11194,7 +11200,7 @@

593

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

594

lt_status=$lt_dlunknown

595

cat > conftest.$ac_ext <<_LT_EOF

596

-#line 11197 "configure"

597

+#line 11203 "configure"

598

#include "confdefs.h"

599

600

#if HAVE_DLFCN_H

601

Index: libgomp/ChangeLog

602

===================================================================

603

--- a/src/libgomp/ChangeLog (.../tags/gcc_4_8_2_release)

604

+++ b/src/libgomp/ChangeLog (.../branches/gcc-4_8-branch)

605

@@ -1,3 +1,21 @@

606

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

607

+

608

+ Backport from mainline

609

+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

610

+

611

+ * configure: Regenerate.

612

+

613

+2014-04-02 Richard Henderson <rth@redhat.com>

614

+

615

+ * config/linux/futex.h (futex_wait): Get error value from errno.

616

+ (futex_wake): Likewise.

617

+

618

+2013-12-12 Jakub Jelinek <jakub@redhat.com>

619

+

620

+ PR libgomp/59467

621

+ * testsuite/libgomp.fortran/crayptr2.f90: Add private (d) clause to

622

+ !$omp parallel.

623

+

624

2013-10-16 Release Manager

625

626

* GCC 4.8.2 released.

627

Index: libgomp/testsuite/libgomp.fortran/crayptr2.f90

628

===================================================================

629

--- a/src/libgomp/testsuite/libgomp.fortran/crayptr2.f90 (.../tags/gcc_4_8_2_release)

630

+++ b/src/libgomp/testsuite/libgomp.fortran/crayptr2.f90 (.../branches/gcc-4_8-branch)

631

@@ -12,7 +12,7 @@

632

b = 2

633

c = 3

634

l = .false.

635

-!$omp parallel num_threads (3) reduction (.or.:l)

636

+!$omp parallel num_threads (3) reduction (.or.:l) private (d)

637

if (omp_get_thread_num () .eq. 0) then

638

ip = loc (a)

639

elseif (omp_get_thread_num () .eq. 1) then

640

Index: libgomp/config/linux/futex.h

641

===================================================================

642

--- a/src/libgomp/config/linux/futex.h (.../tags/gcc_4_8_2_release)

643

+++ b/src/libgomp/config/linux/futex.h (.../branches/gcc-4_8-branch)

644

@@ -41,8 +41,8 @@

645

static inline void

646

futex_wait (int *addr, int val)

647

{

648

- long err = syscall (SYS_futex, addr, gomp_futex_wait, val, NULL);

649

- if (__builtin_expect (err == -ENOSYS, 0))

650

+ int err = syscall (SYS_futex, addr, gomp_futex_wait, val, NULL);

651

+ if (__builtin_expect (err < 0 && errno == ENOSYS, 0))

652

{

653

gomp_futex_wait &= ~FUTEX_PRIVATE_FLAG;

654

gomp_futex_wake &= ~FUTEX_PRIVATE_FLAG;

655

@@ -53,8 +53,8 @@

656

static inline void

657

futex_wake (int *addr, int count)

658

{

659

- long err = syscall (SYS_futex, addr, gomp_futex_wake, count);

660

- if (__builtin_expect (err == -ENOSYS, 0))

661

+ int err = syscall (SYS_futex, addr, gomp_futex_wake, count);

662

+ if (__builtin_expect (err < 0 && errno == ENOSYS, 0))

663

{

664

gomp_futex_wait &= ~FUTEX_PRIVATE_FLAG;

665

gomp_futex_wake &= ~FUTEX_PRIVATE_FLAG;

666

Index: libquadmath/configure

667

===================================================================

668

--- a/src/libquadmath/configure (.../tags/gcc_4_8_2_release)

669

+++ b/src/libquadmath/configure (.../branches/gcc-4_8-branch)

670

@@ -6248,7 +6248,7 @@

671

rm -rf conftest*

672

;;

673

674

-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \

675

+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \

676

s390*-*linux*|s390*-*tpf*|sparc*-*linux*)

677

# Find out which ABI we are using.

678

echo 'int i;' > conftest.$ac_ext

679

@@ -6273,7 +6273,10 @@

680

;;

681

esac

682

;;

683

- ppc64-*linux*|powerpc64-*linux*)

684

+ powerpc64le-*linux*)

685

+ LD="${LD-ld} -m elf32lppclinux"

686

+ ;;

687

+ powerpc64-*linux*)

688

LD="${LD-ld} -m elf32ppclinux"

689

;;

690

s390x-*linux*)

691

@@ -6292,7 +6295,10 @@

692

x86_64-*linux*)

693

LD="${LD-ld} -m elf_x86_64"

694

;;

695

- ppc*-*linux*|powerpc*-*linux*)

696

+ powerpcle-*linux*)

697

+ LD="${LD-ld} -m elf64lppc"

698

+ ;;

699

+ powerpc-*linux*)

700

LD="${LD-ld} -m elf64ppc"

701

;;

702

s390*-*linux*|s390*-*tpf*)

703

@@ -10521,7 +10527,7 @@

704

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

705

lt_status=$lt_dlunknown

706

cat > conftest.$ac_ext <<_LT_EOF

707

-#line 10524 "configure"

708

+#line 10530 "configure"

709

#include "confdefs.h"

710

711

#if HAVE_DLFCN_H

712

@@ -10627,7 +10633,7 @@

713

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

714

lt_status=$lt_dlunknown

715

cat > conftest.$ac_ext <<_LT_EOF

716

-#line 10630 "configure"

717

+#line 10636 "configure"

718

#include "confdefs.h"

719

720

#if HAVE_DLFCN_H

721

Index: libquadmath/ChangeLog

722

===================================================================

723

--- a/src/libquadmath/ChangeLog (.../tags/gcc_4_8_2_release)

724

+++ b/src/libquadmath/ChangeLog (.../branches/gcc-4_8-branch)

725

@@ -1,3 +1,10 @@

726

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

727

+

728

+ Backport from mainline

729

+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

730

+

731

+ * configure: Regenerate.

732

+

733

2013-10-16 Release Manager

734

735

* GCC 4.8.2 released.

736

Index: libsanitizer/configure

737

===================================================================

738

--- a/src/libsanitizer/configure (.../tags/gcc_4_8_2_release)

739

+++ b/src/libsanitizer/configure (.../branches/gcc-4_8-branch)

740

@@ -6604,7 +6604,7 @@

741

rm -rf conftest*

742

;;

743

744

-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \

745

+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \

746

s390*-*linux*|s390*-*tpf*|sparc*-*linux*)

747

# Find out which ABI we are using.

748

echo 'int i;' > conftest.$ac_ext

749

@@ -6629,7 +6629,10 @@

750

;;

751

esac

752

;;

753

- ppc64-*linux*|powerpc64-*linux*)

754

+ powerpc64le-*linux*)

755

+ LD="${LD-ld} -m elf32lppclinux"

756

+ ;;

757

+ powerpc64-*linux*)

758

LD="${LD-ld} -m elf32ppclinux"

759

;;

760

s390x-*linux*)

761

@@ -6648,7 +6651,10 @@

762

x86_64-*linux*)

763

LD="${LD-ld} -m elf_x86_64"

764

;;

765

- ppc*-*linux*|powerpc*-*linux*)

766

+ powerpcle-*linux*)

767

+ LD="${LD-ld} -m elf64lppc"

768

+ ;;

769

+ powerpc-*linux*)

770

LD="${LD-ld} -m elf64ppc"

771

;;

772

s390*-*linux*|s390*-*tpf*)

773

@@ -11111,7 +11117,7 @@

774

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

775

lt_status=$lt_dlunknown

776

cat > conftest.$ac_ext <<_LT_EOF

777

-#line 11114 "configure"

778

+#line 11120 "configure"

779

#include "confdefs.h"

780

781

#if HAVE_DLFCN_H

782

@@ -11217,7 +11223,7 @@

783

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

784

lt_status=$lt_dlunknown

785

cat > conftest.$ac_ext <<_LT_EOF

786

-#line 11220 "configure"

787

+#line 11226 "configure"

788

#include "confdefs.h"

789

790

#if HAVE_DLFCN_H

791

Index: libsanitizer/ChangeLog

792

===================================================================

793

--- a/src/libsanitizer/ChangeLog (.../tags/gcc_4_8_2_release)

794

+++ b/src/libsanitizer/ChangeLog (.../branches/gcc-4_8-branch)

795

@@ -1,3 +1,17 @@

796

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

797

+

798

+ Backport from mainline r208290

799

+ 2014-03-03 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

800

+

801

+ * configure.tgt: Unsupported for little endian PowerPC for now.

802

+

803

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

804

+

805

+ Backport from mainline

806

+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

807

+

808

+ * configure: Regenerate.

809

+

810

2013-10-16 Release Manager

811

812

* GCC 4.8.2 released.

813

Index: libsanitizer/configure.tgt

814

===================================================================

815

--- a/src/libsanitizer/configure.tgt (.../tags/gcc_4_8_2_release)

816

+++ b/src/libsanitizer/configure.tgt (.../branches/gcc-4_8-branch)

817

@@ -25,6 +25,9 @@

818

TSAN_SUPPORTED=yes

819

fi

820

;;

821

+ powerpc*le-*-linux*)

822

+ UNSUPPORTED=1

823

+ ;;

824

powerpc*-*-linux*)

825

;;

826

sparc*-*-linux*)

827

Index: zlib/configure

828

===================================================================

829

--- a/src/zlib/configure (.../tags/gcc_4_8_2_release)

830

+++ b/src/zlib/configure (.../branches/gcc-4_8-branch)

831

@@ -5853,7 +5853,7 @@

832

rm -rf conftest*

833

;;

834

835

-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \

836

+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \

837

s390*-*linux*|s390*-*tpf*|sparc*-*linux*)

838

# Find out which ABI we are using.

839

echo 'int i;' > conftest.$ac_ext

840

@@ -5878,7 +5878,10 @@

841

;;

842

esac

843

;;

844

- ppc64-*linux*|powerpc64-*linux*)

845

+ powerpc64le-*linux*)

846

+ LD="${LD-ld} -m elf32lppclinux"

847

+ ;;

848

+ powerpc64-*linux*)

849

LD="${LD-ld} -m elf32ppclinux"

850

;;

851

s390x-*linux*)

852

@@ -5897,7 +5900,10 @@

853

x86_64-*linux*)

854

LD="${LD-ld} -m elf_x86_64"

855

;;

856

- ppc*-*linux*|powerpc*-*linux*)

857

+ powerpcle-*linux*)

858

+ LD="${LD-ld} -m elf64lppc"

859

+ ;;

860

+ powerpc-*linux*)

861

LD="${LD-ld} -m elf64ppc"

862

;;

863

s390*-*linux*|s390*-*tpf*)

864

@@ -10394,7 +10400,7 @@

865

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

866

lt_status=$lt_dlunknown

867

cat > conftest.$ac_ext <<_LT_EOF

868

-#line 10397 "configure"

869

+#line 10403 "configure"

870

#include "confdefs.h"

871

872

#if HAVE_DLFCN_H

873

@@ -10500,7 +10506,7 @@

874

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

875

lt_status=$lt_dlunknown

876

cat > conftest.$ac_ext <<_LT_EOF

877

-#line 10503 "configure"

878

+#line 10509 "configure"

879

#include "confdefs.h"

880

881

#if HAVE_DLFCN_H

882

Index: zlib/ChangeLog

883

===================================================================

884

--- a/src/zlib/ChangeLog (.../tags/gcc_4_8_2_release)

885

+++ b/src/zlib/ChangeLog (.../branches/gcc-4_8-branch)

886

@@ -1,3 +1,10 @@

887

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

888

+

889

+ Backport from mainline

890

+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

891

+

892

+ * configure: Regenerate.

893

+

894

2013-10-16 Release Manager

895

896

* GCC 4.8.2 released.

897

Index: libstdc++-v3/configure

898

===================================================================

899

--- a/src/libstdc++-v3/configure (.../tags/gcc_4_8_2_release)

900

+++ b/src/libstdc++-v3/configure (.../branches/gcc-4_8-branch)

901

@@ -7111,7 +7111,7 @@

902

rm -rf conftest*

903

;;

904

905

-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \

906

+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \

907

s390*-*linux*|s390*-*tpf*|sparc*-*linux*)

908

# Find out which ABI we are using.

909

echo 'int i;' > conftest.$ac_ext

910

@@ -7136,7 +7136,10 @@

911

;;

912

esac

913

;;

914

- ppc64-*linux*|powerpc64-*linux*)

915

+ powerpc64le-*linux*)

916

+ LD="${LD-ld} -m elf32lppclinux"

917

+ ;;

918

+ powerpc64-*linux*)

919

LD="${LD-ld} -m elf32ppclinux"

920

;;

921

s390x-*linux*)

922

@@ -7155,7 +7158,10 @@

923

x86_64-*linux*)

924

LD="${LD-ld} -m elf_x86_64"

925

;;

926

- ppc*-*linux*|powerpc*-*linux*)

927

+ powerpcle-*linux*)

928

+ LD="${LD-ld} -m elf64lppc"

929

+ ;;

930

+ powerpc-*linux*)

931

LD="${LD-ld} -m elf64ppc"

932

;;

933

s390*-*linux*|s390*-*tpf*)

934

@@ -11513,7 +11519,7 @@

935

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

936

lt_status=$lt_dlunknown

937

cat > conftest.$ac_ext <<_LT_EOF

938

-#line 11516 "configure"

939

+#line 11522 "configure"

940

#include "confdefs.h"

941

942

#if HAVE_DLFCN_H

943

@@ -11619,7 +11625,7 @@

944

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

945

lt_status=$lt_dlunknown

946

cat > conftest.$ac_ext <<_LT_EOF

947

-#line 11622 "configure"

948

+#line 11628 "configure"

949

#include "confdefs.h"

950

951

#if HAVE_DLFCN_H

952

@@ -15033,7 +15039,7 @@

953

#

954

# Fake what AC_TRY_COMPILE does. XXX Look at redoing this new-style.

955

cat > conftest.$ac_ext << EOF

956

-#line 15036 "configure"

957

+#line 15042 "configure"

958

struct S { ~S(); };

959

void bar();

960

void foo()

961

@@ -15383,7 +15389,7 @@

962

# Fake what AC_TRY_COMPILE does.

963

964

cat > conftest.$ac_ext << EOF

965

-#line 15386 "configure"

966

+#line 15392 "configure"

967

int main()

968

{

969

typedef bool atomic_type;

970

@@ -15418,7 +15424,7 @@

971

rm -f conftest*

972

973

cat > conftest.$ac_ext << EOF

974

-#line 15421 "configure"

975

+#line 15427 "configure"

976

int main()

977

{

978

typedef short atomic_type;

979

@@ -15453,7 +15459,7 @@

980

rm -f conftest*

981

982

cat > conftest.$ac_ext << EOF

983

-#line 15456 "configure"

984

+#line 15462 "configure"

985

int main()

986

{

987

// NB: _Atomic_word not necessarily int.

988

@@ -15489,7 +15495,7 @@

989

rm -f conftest*

990

991

cat > conftest.$ac_ext << EOF

992

-#line 15492 "configure"

993

+#line 15498 "configure"

994

int main()

995

{

996

typedef long long atomic_type;

997

@@ -15568,7 +15574,7 @@

998

# unnecessary for this test.

999

1000

cat > conftest.$ac_ext << EOF

1001

-#line 15571 "configure"

1002

+#line 15577 "configure"

1003

int main()

1004

{

1005

_Decimal32 d1;

1006

@@ -15610,7 +15616,7 @@

1007

# unnecessary for this test.

1008

1009

cat > conftest.$ac_ext << EOF

1010

-#line 15613 "configure"

1011

+#line 15619 "configure"

1012

template<typename T1, typename T2>

1013

struct same

1014

{ typedef T2 type; };

1015

@@ -15644,7 +15650,7 @@

1016

rm -f conftest*

1017

1018

cat > conftest.$ac_ext << EOF

1019

-#line 15647 "configure"

1020

+#line 15653 "configure"

1021

template<typename T1, typename T2>

1022

struct same

1023

{ typedef T2 type; };

1024

@@ -71573,7 +71579,7 @@

1025

fi

1026

1027

# For libtool versioning info, format is CURRENT:REVISION:AGE

1028

-libtool_VERSION=6:18:0

1029

+libtool_VERSION=6:19:0

1030

1031

# Everything parsed; figure out what files and settings to use.

1032

case $enable_symvers in

1033

Index: libstdc++-v3/scripts/extract_symvers.in

1034

===================================================================

1035

--- a/src/libstdc++-v3/scripts/extract_symvers.in (.../tags/gcc_4_8_2_release)

1036

+++ b/src/libstdc++-v3/scripts/extract_symvers.in (.../branches/gcc-4_8-branch)

1037

@@ -53,6 +53,7 @@

1038

# present on Solaris.

1039

${readelf} ${lib} |\

1040

sed -e 's/ \[<other>: [A-Fa-f0-9]*\] //' -e '/\.dynsym/,/^$/p;d' |\

1041

+ sed -e 's/ \[<localentry>: [0-9]*\] //' |\

1042

egrep -v ' (LOCAL|UND) ' |\

1043

1044

sed -e 's/ <processor specific>: / <processor_specific>:_/g' |\

1045

Index: libstdc++-v3/src/c++11/thread.cc

1046

===================================================================

1047

--- a/src/libstdc++-v3/src/c++11/thread.cc (.../tags/gcc_4_8_2_release)

1048

+++ b/src/libstdc++-v3/src/c++11/thread.cc (.../branches/gcc-4_8-branch)

1049

@@ -183,7 +183,7 @@

1050

::usleep(__us);

1051

}

1052

# else

1053

- ::sleep(__s.count() + (__ns >= 1000000));

1054

+ ::sleep(__s.count() + (__ns.count() >= 1000000));

1055

# endif

1056

#elif defined(_GLIBCXX_HAVE_WIN32_SLEEP)

1057

unsigned long ms = __ns.count() / 1000000;

1058

Index: libstdc++-v3/doc/xml/manual/abi.xml

1059

===================================================================

1060

--- a/src/libstdc++-v3/doc/xml/manual/abi.xml (.../tags/gcc_4_8_2_release)

1061

+++ b/src/libstdc++-v3/doc/xml/manual/abi.xml (.../branches/gcc-4_8-branch)

1062

@@ -203,6 +203,7 @@

1063

1064

1065

1066

+ <listitem><para>GCC 4.8.0: GCC_4.8.0</para></listitem>

1067

</itemizedlist>

1068

</listitem>

1069

1070

@@ -261,6 +262,7 @@

1071

<listitem><para>GCC 4.6.1: libstdc++.so.6.0.16</para></listitem>

1072

<listitem><para>GCC 4.7.0: libstdc++.so.6.0.17</para></listitem>

1073

<listitem><para>GCC 4.8.0: libstdc++.so.6.0.18</para></listitem>

1074

+ <listitem><para>GCC 4.8.3: libstdc++.so.6.0.19</para></listitem>

1075

</itemizedlist>

1076

<para>

1077

Note 1: Error should be libstdc++.so.3.0.3.

1078

@@ -324,6 +326,7 @@

1079

<listitem><para>GCC 4.6.1: GLIBCXX_3.4.16, CXXABI_1.3.5</para></listitem>

1080

<listitem><para>GCC 4.7.0: GLIBCXX_3.4.17, CXXABI_1.3.6</para></listitem>

1081

<listitem><para>GCC 4.8.0: GLIBCXX_3.4.18, CXXABI_1.3.7</para></listitem>

1082

+ <listitem><para>GCC 4.8.3: GLIBCXX_3.4.19, CXXABI_1.3.7</para></listitem>

1083

</itemizedlist>

1084

</listitem>

1085

1086

Index: libstdc++-v3/doc/xml/manual/status_cxx2011.xml

1087

===================================================================

1088

--- a/src/libstdc++-v3/doc/xml/manual/status_cxx2011.xml (.../tags/gcc_4_8_2_release)

1089

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1090

@@ -877,10 +877,11 @@

1091

1092

</row>

1093

<row>

1094

+ <?dbhtml bgcolor="#B0B0B0" ?>

1095

1096

<entry>Other transformations</entry>

1097

- <entry>Y</entry>

1098

- <entry/>

1099

+ <entry>Partial</entry>

1100

+ <entry>Missing <code>aligned_union</code>.</entry>

1101

</row>

1102

<row>

1103

1104

Index: libstdc++-v3/doc/xml/manual/spine.xml

1105

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1106

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1107

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1108

@@ -20,6 +20,7 @@

1109

1110

1111

1112

+ <year>2013</year>

1113

1114

1115

</holder>

1116

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1117

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1123

\ No newline at end of file

1124

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title></title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="index.html" title="The GNU C++ Library" /><link rel="up" href="index.html" title="The GNU C++ Library" /><link rel="prev" href="manual/backwards.html" title="Backwards Compatibility" /><link rel="next" href="api.html" title="The GNU C++ Library API Reference" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center"></th></tr><tr><td width="20%" align="left"><a accesskey="p" href="manual/backwards.html">Prev</a> </td><th width="60%" align="center"> </th><td width="20%" align="right"> <a accesskey="n" href="api.html">Next</a></td></tr></table><hr /></div><div class="book"><div class="titlepage"><hr /></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="article"><a href="api.html">The GNU C++ Library API Reference</a></span></dt></dl></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="manual/backwards.html">Prev</a> </td><td width="20%" align="center"> </td><td width="40%" align="right"> <a accesskey="n" href="api.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">Backwards Compatibility </td><td width="20%" align="center"><a accesskey="h" href="index.html">Home</a></td><td width="40%" align="right" valign="top"> The GNU C++ Library API Reference</td></tr></table></div></body></html>

1125

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1127

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1130

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1131

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1133

\ No newline at end of file

1134

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title></title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="index.html" title="The GNU C++ Library" /><link rel="up" href="index.html" title="The GNU C++ Library" /><link rel="prev" href="api.html" title="The GNU C++ Library API Reference" /><link rel="next" href="faq.html" title="Frequently Asked Questions" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center"></th></tr><tr><td width="20%" align="left"><a accesskey="p" href="api.html">Prev</a> </td><th width="60%" align="center"> </th><td width="20%" align="right"> <a accesskey="n" href="faq.html">Next</a></td></tr></table><hr /></div><div class="book"><div class="titlepage"><hr /></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="article"><a href="faq.html">Frequently Asked Questions</a></span></dt></dl></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="api.html">Prev</a> </td><td width="20%" align="center"> </td><td width="40%" align="right"> <a accesskey="n" href="faq.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">The GNU C++ Library API Reference </td><td width="20%" align="center"><a accesskey="h" href="index.html">Home</a></td><td width="40%" align="right" valign="top"> Frequently Asked Questions</td></tr></table></div></body></html>

1135

\ No newline at end of file

1136

Index: libstdc++-v3/doc/html/faq.html

1137

===================================================================

1138

--- a/src/libstdc++-v3/doc/html/faq.html (.../tags/gcc_4_8_2_release)

1139

+++ b/src/libstdc++-v3/doc/html/faq.html (.../branches/gcc-4_8-branch)

1140

@@ -1,9 +1,9 @@

1141

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

1142

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Frequently Asked Questions</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="index.html" title="The GNU C++ Library" /><link rel="up" href="bk03.html" title="" /><link rel="prev" href="bk03.html" title="" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Frequently Asked Questions</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="bk03.html">Prev</a> </td><th width="60%" align="center"></th><td width="20%" align="right"> </td></tr></table><hr /></div><div class="article"><div class="titlepage"><div><div><h1 class="title"><a id="faq"></a>Frequently Asked Questions</h1></div><div><p class="copyright">Copyright ©

1143

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Frequently Asked Questions</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="index.html" title="The GNU C++ Library" /><link rel="up" href="bk03.html" title="" /><link rel="prev" href="bk03.html" title="" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Frequently Asked Questions</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="bk03.html">Prev</a> </td><th width="60%" align="center"></th><td width="20%" align="right"> </td></tr></table><hr /></div><div class="article"><div class="titlepage"><div><div><h1 class="title"><a id="faq"></a>Frequently Asked Questions</h1></div><div><p class="copyright">Copyright ©

1144

2008, 2010

1145

1146

1147

- </p></div></div><hr /></div><div class="qandaset"><a id="idp1581728"></a><dl><dt></dt><dd><dl><dt>1.1. <a href="faq.html#faq.what">

1148

+ </p></div></div><hr /></div><div class="qandaset"><a id="idm270011560848"></a><dl><dt></dt><dd><dl><dt>1.1. <a href="faq.html#faq.what">

1149

What is libstdc++?

1150

</a></dt><dt>1.2. <a href="faq.html#faq.why">

1151

Why should I use libstdc++?

1152

Index: libstdc++-v3/doc/html/index.html

1153

===================================================================

1154

--- a/src/libstdc++-v3/doc/html/index.html (.../tags/gcc_4_8_2_release)

1155

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1156

@@ -1,5 +1,5 @@

1157

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

1158

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>The GNU C++ Library</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="description" content="Short Contents Copyright (C) 2008-2013 FSF Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, with no Front-Cover Texts, and with no Back-Cover Texts. This is the top level of the libstdc++ documentation set. The documentation is divided into the following three sections. Manual Frequently Asked Questions API and Source Documentation" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="index.html" title="The GNU C++ Library" /><link rel="next" href="manual/index.html" title="The GNU C++ Library Manual" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">The GNU C++ Library</th></tr><tr><td width="20%" align="left"> </td><th width="60%" align="center"> </th><td width="20%" align="right"> <a accesskey="n" href="manual/index.html">Next</a></td></tr></table><hr /></div><div class="set" lang="en" xml:lang="en"><div class="titlepage"><div><div><h1 class="title"><a id="set-index"></a>The GNU C++ Library</h1></div><div><div class="abstract"><a id="contents"></a><p class="title"><strong>Short Contents</strong></p><p>

1159

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>The GNU C++ Library</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="description" content="Short Contents Copyright (C) 2008-2013 FSF Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, with no Front-Cover Texts, and with no Back-Cover Texts. This is the top level of the libstdc++ documentation set. The documentation is divided into the following three sections. Manual Frequently Asked Questions API and Source Documentation" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="index.html" title="The GNU C++ Library" /><link rel="next" href="manual/index.html" title="The GNU C++ Library Manual" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">The GNU C++ Library</th></tr><tr><td width="20%" align="left"> </td><th width="60%" align="center"> </th><td width="20%" align="right"> <a accesskey="n" href="manual/index.html">Next</a></td></tr></table><hr /></div><div class="set" lang="en" xml:lang="en"><div class="titlepage"><div><div><h1 class="title"><a id="set-index"></a>The GNU C++ Library</h1></div><div><div class="abstract"><a id="contents"></a><p class="title"><strong>Short Contents</strong></p><p>

1160

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<a class="link" href="http://www.fsf.org/" target="_top">FSF

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1165

<a class="link" href="api.html" title="The GNU C++ Library API Reference">API and Source Documentation</a>

1166

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1167

- </p></div></div></div><hr /></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="book"><a href="manual/index.html">The GNU C++ Library Manual</a></span></dt><dd><dl><dt><span class="part"><a href="manual/intro.html">I.

1168

+ </p></div></div></div><hr /></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="book"><a href="manual/index.html">The GNU C++ Library Manual</a></span></dt><dd><dl><dt><span class="part"><a href="manual/intro.html">I.

1169

Introduction

1170

1171

</a></span></dt><dd><dl><dt><span class="chapter"><a href="manual/status.html">1. Status</a></span></dt><dd><dl><dt><span class="section"><a href="manual/status.html#manual.intro.status.iso">Implementation Status</a></span></dt><dd><dl><dt><span class="section"><a href="manual/status.html#status.iso.1998">C++ 1998/2003</a></span></dt><dd><dl><dt><span class="section"><a href="manual/status.html#iso.1998.status">Implementation Status</a></span></dt><dt><span class="section"><a href="manual/status.html#iso.1998.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="manual/status.html#status.iso.2011">C++ 2011</a></span></dt><dd><dl><dt><span class="section"><a href="manual/status.html#iso.2011.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="manual/status.html#status.iso.tr1">C++ TR1</a></span></dt><dd><dl><dt><span class="section"><a href="manual/status.html#iso.tr1.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="manual/status.html#status.iso.tr24733">C++ TR 24733</a></span></dt></dl></dd><dt><span class="section"><a href="manual/license.html">License</a></span></dt><dd><dl><dt><span class="section"><a href="manual/license.html#manual.intro.status.license.gpl">The Code: GPL</a></span></dt><dt><span class="section"><a href="manual/license.html#manual.intro.status.license.fdl">The Documentation: GPL, FDL</a></span></dt></dl></dd><dt><span class="section"><a href="manual/bugs.html">Bugs</a></span></dt><dd><dl><dt><span class="section"><a href="manual/bugs.html#manual.intro.status.bugs.impl">Implementation Bugs</a></span></dt><dt><span class="section"><a href="manual/bugs.html#manual.intro.status.bugs.iso">Standard Bugs</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="manual/setup.html">2. Setup</a></span></dt><dd><dl><dt><span class="section"><a href="manual/setup.html#manual.intro.setup.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="manual/configure.html">Configure</a></span></dt><dt><span class="section"><a href="manual/make.html">Make</a></span></dt></dl></dd><dt><span class="chapter"><a href="manual/using.html">3. Using</a></span></dt><dd><dl><dt><span class="section"><a href="manual/using.html#manual.intro.using.flags">Command Options</a></span></dt><dt><span class="section"><a href="manual/using_headers.html">Headers</a></span></dt><dd><dl><dt><span class="section"><a href="manual/using_headers.html#manual.intro.using.headers.all">Header Files</a></span></dt><dt><span class="section"><a href="manual/using_headers.html#manual.intro.using.headers.mixing">Mixing Headers</a></span></dt><dt><span class="section"><a href="manual/using_headers.html#manual.intro.using.headers.cheaders">The C Headers and <code class="code">namespace std</code></a></span></dt><dt><span class="section"><a href="manual/using_headers.html#manual.intro.using.headers.pre">Precompiled Headers</a></span></dt></dl></dd><dt><span class="section"><a href="manual/using_macros.html">Macros</a></span></dt><dt><span class="section"><a href="manual/using_namespaces.html">Namespaces</a></span></dt><dd><dl><dt><span class="section"><a href="manual/using_namespaces.html#manual.intro.using.namespaces.all">Available Namespaces</a></span></dt><dt><span class="section"><a href="manual/using_namespaces.html#manual.intro.using.namespaces.std">namespace std</a></span></dt><dt><span class="section"><a href="manual/using_namespaces.html#manual.intro.using.namespaces.comp">Using Namespace Composition</a></span></dt></dl></dd><dt><span class="section"><a href="manual/using_dynamic_or_shared.html">Linking</a></span></dt><dd><dl><dt><span class="section"><a href="manual/using_dynamic_or_shared.html#manual.intro.using.linkage.freestanding">Almost Nothing</a></span></dt><dt><span class="section"><a href="manual/using_dynamic_or_shared.html#manual.intro.using.linkage.dynamic">Finding Dynamic or Shared Libraries</a></span></dt></dl></dd><dt><span class="section"><a href="manual/using_concurrency.html">Concurrency</a></span></dt><dd><dl><dt><span class="section"><a href="manual/using_concurrency.html#manual.intro.using.concurrency.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="manual/using_concurrency.html#manual.intro.using.concurrency.thread_safety">Thread Safety</a></span></dt><dt><span class="section"><a href="manual/using_concurrency.html#manual.intro.using.concurrency.atomics">Atomics</a></span></dt><dt><span class="section"><a href="manual/using_concurrency.html#manual.intro.using.concurrency.io">IO</a></span></dt><dd><dl><dt><span class="section"><a href="manual/using_concurrency.html#concurrency.io.structure">Structure</a></span></dt><dt><span class="section"><a href="manual/using_concurrency.html#concurrency.io.defaults">Defaults</a></span></dt><dt><span class="section"><a href="manual/using_concurrency.html#concurrency.io.future">Future</a></span></dt><dt><span class="section"><a href="manual/using_concurrency.html#concurrency.io.alt">Alternatives</a></span></dt></dl></dd><dt><span class="section"><a href="manual/using_concurrency.html#manual.intro.using.concurrency.containers">Containers</a></span></dt></dl></dd><dt><span class="section"><a href="manual/using_exceptions.html">Exceptions</a></span></dt><dd><dl><dt><span class="section"><a href="manual/using_exceptions.html#intro.using.exception.safety">Exception Safety</a></span></dt><dt><span class="section"><a href="manual/using_exceptions.html#intro.using.exception.propagating">Exception Neutrality</a></span></dt><dt><span class="section"><a href="manual/using_exceptions.html#intro.using.exception.no">Doing without</a></span></dt><dt><span class="section"><a href="manual/using_exceptions.html#intro.using.exception.compat">Compatibility</a></span></dt><dd><dl><dt><span class="section"><a href="manual/using_exceptions.html#using.exception.compat.c">With <code class="literal">C</code></a></span></dt><dt><span class="section"><a href="manual/using_exceptions.html#using.exception.compat.posix">With <code class="literal">POSIX</code> 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Support

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Iterators

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Standard Contents

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Iterators

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- <a id="idp16156992" class="indexterm"></a>

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-</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="iterators.html#std.iterators.predefined">Predefined</a></span></dt><dd><dl><dt><span class="section"><a href="iterators.html#iterators.predefined.vs_pointers">Iterators vs. Pointers</a></span></dt><dt><span class="section"><a href="iterators.html#iterators.predefined.end">One Past the End</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.iterators.predefined"></a>Predefined</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="iterators.predefined.vs_pointers"></a>Iterators vs. Pointers</h3></div></div></div><p>

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+ <a id="idm269999374096" class="indexterm"></a>

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+</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="iterators.html#std.iterators.predefined">Predefined</a></span></dt><dd><dl><dt><span class="section"><a href="iterators.html#iterators.predefined.vs_pointers">Iterators vs. Pointers</a></span></dt><dt><span class="section"><a href="iterators.html#iterators.predefined.end">One Past the End</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.iterators.predefined"></a>Predefined</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="iterators.predefined.vs_pointers"></a>Iterators vs. Pointers</h3></div></div></div><p>

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The following

1239

FAQ <a class="link" href="../faq.html#faq.iterator_as_pod" title="7.1.">entry</a> points out that

1240

iterators are not implemented as pointers. They are a generalization

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1249

Let's start by describing how the data on a freelist is laid out in memory.

1250

This is the first two blocks in freelist for thread id 3 in bin 3 (8 bytes):

1251

</p><pre class="programlisting">

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Extensions

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</p><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="allocator.mt.intro"></a>Intro</h2></div></div></div><p>

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The mt allocator [hereinafter referred to simply as "the allocator"]

1277

is a fixed size (power of two) allocator that was initially

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Configure</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, configure, options" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="setup.html" title="Chapter 2. Setup" /><link rel="prev" href="setup.html" title="Chapter 2. Setup" /><link rel="next" href="make.html" title="Make" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Configure</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="setup.html">Prev</a> </td><th width="60%" align="center">Chapter 2. Setup</th><td width="20%" align="right"> <a accesskey="n" href="make.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.setup.configure"></a>Configure</h2></div></div></div><p>

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When configuring libstdc++, you'll have to configure the entire

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<span class="emphasis"><em>gccsrcdir</em></span> directory. Consider using the

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toplevel gcc configuration option

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Index: libstdc++-v3/doc/html/manual/status.html

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===================================================================

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>

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-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 1. Status</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="intro.html" title="Part I. Introduction" /><link rel="prev" href="intro.html" title="Part I. Introduction" /><link rel="next" href="license.html" title="License" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 1. Status</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="intro.html">Prev</a> </td><th width="60%" align="center">Part I.

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 1. Status</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="intro.html" title="Part I. Introduction" /><link rel="prev" href="intro.html" title="Part I. Introduction" /><link rel="next" href="license.html" title="License" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 1. Status</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="intro.html">Prev</a> </td><th width="60%" align="center">Part I.

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Introduction

1309

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-</th><td width="20%" align="right"> <a accesskey="n" href="license.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.intro.status"></a>Chapter 1. Status</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="status.html#manual.intro.status.iso">Implementation Status</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#status.iso.1998">C++ 1998/2003</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.1998.status">Implementation Status</a></span></dt><dt><span class="section"><a href="status.html#iso.1998.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.2011">C++ 2011</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.2011.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.tr1">C++ TR1</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.tr1.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.tr24733">C++ TR 24733</a></span></dt></dl></dd><dt><span class="section"><a href="license.html">License</a></span></dt><dd><dl><dt><span class="section"><a href="license.html#manual.intro.status.license.gpl">The Code: GPL</a></span></dt><dt><span class="section"><a href="license.html#manual.intro.status.license.fdl">The Documentation: GPL, FDL</a></span></dt></dl></dd><dt><span class="section"><a href="bugs.html">Bugs</a></span></dt><dd><dl><dt><span class="section"><a href="bugs.html#manual.intro.status.bugs.impl">Implementation Bugs</a></span></dt><dt><span class="section"><a href="bugs.html#manual.intro.status.bugs.iso">Standard Bugs</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.status.iso"></a>Implementation Status</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="status.iso.1998"></a>C++ 1998/2003</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="iso.1998.status"></a>Implementation Status</h4></div></div></div><p>

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+</th><td width="20%" align="right"> <a accesskey="n" href="license.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.intro.status"></a>Chapter 1. Status</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="status.html#manual.intro.status.iso">Implementation Status</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#status.iso.1998">C++ 1998/2003</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.1998.status">Implementation Status</a></span></dt><dt><span class="section"><a href="status.html#iso.1998.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.2011">C++ 2011</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.2011.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.tr1">C++ TR1</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.tr1.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.tr24733">C++ TR 24733</a></span></dt></dl></dd><dt><span class="section"><a href="license.html">License</a></span></dt><dd><dl><dt><span class="section"><a href="license.html#manual.intro.status.license.gpl">The Code: GPL</a></span></dt><dt><span class="section"><a href="license.html#manual.intro.status.license.fdl">The Documentation: GPL, FDL</a></span></dt></dl></dd><dt><span class="section"><a href="bugs.html">Bugs</a></span></dt><dd><dl><dt><span class="section"><a href="bugs.html#manual.intro.status.bugs.impl">Implementation Bugs</a></span></dt><dt><span class="section"><a href="bugs.html#manual.intro.status.bugs.iso">Standard Bugs</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.status.iso"></a>Implementation Status</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="status.iso.1998"></a>C++ 1998/2003</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="iso.1998.status"></a>Implementation Status</h4></div></div></div><p>

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This status table is based on the table of contents of ISO/IEC 14882:2003.

1313

</p><p>

1314

This page describes the C++ support in mainline GCC SVN, not in any

1315

particular release.

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-</p><div class="table"><a id="idp452240"></a><p class="title"><strong>Table 1.1. C++ 1998/2003 Implementation Status</strong></p><div class="table-contents"><table summary="C++ 1998/2003 Implementation Status" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Section</th><th align="left">Description</th><th align="left">Status</th><th align="left">Comments</th></tr></thead><tbody><tr><td align="left">

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+</p><div class="table"><a id="idm270008034928"></a><p class="title"><strong>Table 1.1. C++ 1998/2003 Implementation Status</strong></p><div class="table-contents"><table summary="C++ 1998/2003 Implementation Status" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Section</th><th align="left">Description</th><th align="left">Status</th><th align="left">Comments</th></tr></thead><tbody><tr><td align="left">

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</td><td colspan="3" align="left">

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<span class="emphasis"><em>Language support</em></span>

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</p><p>

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This page describes the C++11 support in mainline GCC SVN, not in any

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-</p><div class="table"><a id="idp8670848"></a><p class="title"><strong>Table 1.2. C++ 2011 Implementation Status</strong></p><div class="table-contents"><table summary="C++ 2011 Implementation Status" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Section</th><th align="left">Description</th><th align="left">Status</th><th align="left">Comments</th></tr></thead><tbody><tr><td align="left">

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+</p><div class="table"><a id="idm270007982624"></a><p class="title"><strong>Table 1.2. C++ 2011 Implementation Status</strong></p><div class="table-contents"><table summary="C++ 2011 Implementation Status" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Section</th><th align="left">Description</th><th align="left">Status</th><th align="left">Comments</th></tr></thead><tbody><tr><td align="left">

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</td><td colspan="3" align="left">

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<span class="emphasis"><em>Language support</em></span>

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@@ -183,7 +183,7 @@

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is_trivially_copy_constructible, is_trivially_move_constructible,

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is_trivially_assignable, is_trivially_default_assignable,

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is_trivially_copy_assignable, is_trivially_move_assignable

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- </td></tr><tr><td align="left">20.9.5</td><td align="left">Type property queries</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.9.6</td><td align="left">Relationships between types</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.9.7</td><td align="left">Transformations between types</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.9.7.1</td><td align="left">Const-volatile modifications</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.9.7.2</td><td align="left">Reference modifications</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.9.7.3</td><td align="left">Sign modifications</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.9.7.4</td><td align="left">Array modifications</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.9.7.5</td><td align="left">Pointer modifications</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.9.7.6</td><td align="left">Other transformations</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.10</td><td align="left">Compile-time rational arithmetic</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.10.1</td><td align="left">In general</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.10.2</td><td align="left">Header <code class="code"><ratio></code> synopsis</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.10.3</td><td align="left">Class template <code class="code">ratio</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.10.4</td><td align="left">Arithmetic on <code class="code">ratio</code>s</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.10.5</td><td align="left">Comparison of <code class="code">ratio</code>s</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.10.6</td><td align="left">SI types for <code class="code">ratio</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11</td><td align="left">Time utilities</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.11.3</td><td align="left">Clock requirements</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11.4</td><td align="left">Time-related traits</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.11.4.1</td><td align="left"><code class="code">treat_as_floating_point</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11.4.2</td><td align="left"><code class="code">duration_values</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11.4.3</td><td align="left">Specializations of <code class="code">common_type</code></td><td align="left">Y</td><td align="left"> </td></tr><tr bgcolor="#B0B0B0"><td align="left">20.11.5</td><td align="left">Class template <code class="code">duration</code></td><td align="left">Partial</td><td align="left">Missing constexpr for non-member arithmetic operations</td></tr><tr><td align="left">20.11.6</td><td align="left">Class template <code class="code">time_point</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11.7</td><td align="left">Clocks</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.11.7.1</td><td align="left">Class <code class="code">system_clock</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11.7.2</td><td align="left">Class <code class="code">steady_clock</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11.7.3</td><td align="left">Class <code class="code">high_resolution_clock</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11.8</td><td align="left">Date and time functions</td><td align="left">Y</td><td align="left"> </td></tr><tr bgcolor="#B0B0B0"><td align="left">20.12</td><td align="left">Scoped allocator adaptor</td><td align="left">Partial</td><td align="left"> </td></tr><tr><td align="left">20.12.1</td><td align="left">Header <code class="code"><scoped_allocator></code> synopsis</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.12.2</td><td align="left">Scoped allocator adaptor member types</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.12.3</td><td align="left">Scoped allocator adaptor constructors</td><td align="left">Y</td><td align="left"> </td></tr><tr bgcolor="#B0B0B0"><td align="left">20.12.4</td><td align="left">Scoped allocator adaptor members</td><td align="left">Partial</td><td align="left">OUTERMOST is not recursive.</td></tr><tr><td align="left">20.12.5</td><td align="left">Scoped allocator operators</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.13</td><td align="left">Class <code class="code">type_index</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">

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+ </td></tr><tr><td align="left">20.9.5</td><td align="left">Type property queries</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.9.6</td><td align="left">Relationships between types</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.9.7</td><td align="left">Transformations between types</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.9.7.1</td><td align="left">Const-volatile modifications</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.9.7.2</td><td align="left">Reference modifications</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.9.7.3</td><td align="left">Sign modifications</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.9.7.4</td><td align="left">Array modifications</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.9.7.5</td><td align="left">Pointer modifications</td><td align="left">Y</td><td align="left"> </td></tr><tr bgcolor="#B0B0B0"><td align="left">20.9.7.6</td><td align="left">Other transformations</td><td align="left">Partial</td><td align="left">Missing <code class="code">aligned_union</code>.</td></tr><tr><td align="left">20.10</td><td align="left">Compile-time rational arithmetic</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.10.1</td><td align="left">In general</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.10.2</td><td align="left">Header <code class="code"><ratio></code> synopsis</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.10.3</td><td align="left">Class template <code class="code">ratio</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.10.4</td><td align="left">Arithmetic on <code class="code">ratio</code>s</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.10.5</td><td align="left">Comparison of <code class="code">ratio</code>s</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.10.6</td><td align="left">SI types for <code class="code">ratio</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11</td><td align="left">Time utilities</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.11.3</td><td align="left">Clock requirements</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11.4</td><td align="left">Time-related traits</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.11.4.1</td><td align="left"><code class="code">treat_as_floating_point</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11.4.2</td><td align="left"><code class="code">duration_values</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11.4.3</td><td align="left">Specializations of <code class="code">common_type</code></td><td align="left">Y</td><td align="left"> </td></tr><tr bgcolor="#B0B0B0"><td align="left">20.11.5</td><td align="left">Class template <code class="code">duration</code></td><td align="left">Partial</td><td align="left">Missing constexpr for non-member arithmetic operations</td></tr><tr><td align="left">20.11.6</td><td align="left">Class template <code class="code">time_point</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11.7</td><td align="left">Clocks</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.11.7.1</td><td align="left">Class <code class="code">system_clock</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11.7.2</td><td align="left">Class <code class="code">steady_clock</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11.7.3</td><td align="left">Class <code class="code">high_resolution_clock</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11.8</td><td align="left">Date and time functions</td><td align="left">Y</td><td align="left"> </td></tr><tr bgcolor="#B0B0B0"><td align="left">20.12</td><td align="left">Scoped allocator adaptor</td><td align="left">Partial</td><td align="left"> </td></tr><tr><td align="left">20.12.1</td><td align="left">Header <code class="code"><scoped_allocator></code> synopsis</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.12.2</td><td align="left">Scoped allocator adaptor member types</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.12.3</td><td align="left">Scoped allocator adaptor constructors</td><td align="left">Y</td><td align="left"> </td></tr><tr bgcolor="#B0B0B0"><td align="left">20.12.4</td><td align="left">Scoped allocator adaptor members</td><td align="left">Partial</td><td align="left">OUTERMOST is not recursive.</td></tr><tr><td align="left">20.12.5</td><td align="left">Scoped allocator operators</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.13</td><td align="left">Class <code class="code">type_index</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">

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</td><td colspan="3" align="left">

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<span class="emphasis"><em>Strings</em></span>

1339

@@ -302,7 +302,7 @@

1340

</p><p>

1341

This page describes the TR1 support in mainline GCC SVN, not in any particular

1342

release.

1343

-</p><div class="table"><a id="idp7483200"></a><p class="title"><strong>Table 1.3. C++ TR1 Implementation Status</strong></p><div class="table-contents"><table summary="C++ TR1 Implementation Status" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Section</th><th align="left">Description</th><th align="left">Status</th><th align="left">Comments</th></tr></thead><tbody><tr><td align="left"><span class="emphasis"><em>2</em></span></td><td colspan="3" align="left"><span class="emphasis"><em>General Utilities</em></span></td></tr><tr><td align="left">2.1</td><td align="left">Reference wrappers</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">2.1.1</td><td align="left">Additions to header <code class="code"><functional></code> synopsis</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.1.2</td><td align="left">Class template <code class="code">reference_wrapper</code></td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">2.1.2.1</td><td align="left"><code class="code">reference_wrapper</code> construct/copy/destroy</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.1.2.2</td><td align="left"><code class="code">reference_wrapper</code> assignment</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.1.2.3</td><td align="left"><code class="code">reference_wrapper</code> access</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.1.2.4</td><td align="left"><code class="code">reference_wrapper</code> invocation</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.1.2.5</td><td align="left"><code class="code">reference_wrapper</code> helper functions</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.2</td><td align="left">Smart pointers</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">2.2.1</td><td align="left">Additions to header <code class="code"><memory></code> synopsis</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.2.2</td><td align="left">Class <code class="code">bad_weak_ptr</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.2.3</td><td align="left">Class template <code class="code">shared_ptr</code></td><td align="left"> </td><td align="left">

1344

+</p><div class="table"><a id="idm270006687472"></a><p class="title"><strong>Table 1.3. C++ TR1 Implementation Status</strong></p><div class="table-contents"><table summary="C++ TR1 Implementation Status" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Section</th><th align="left">Description</th><th align="left">Status</th><th align="left">Comments</th></tr></thead><tbody><tr><td align="left"><span class="emphasis"><em>2</em></span></td><td colspan="3" align="left"><span class="emphasis"><em>General Utilities</em></span></td></tr><tr><td align="left">2.1</td><td align="left">Reference wrappers</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">2.1.1</td><td align="left">Additions to header <code class="code"><functional></code> synopsis</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.1.2</td><td align="left">Class template <code class="code">reference_wrapper</code></td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">2.1.2.1</td><td align="left"><code class="code">reference_wrapper</code> construct/copy/destroy</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.1.2.2</td><td align="left"><code class="code">reference_wrapper</code> assignment</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.1.2.3</td><td align="left"><code class="code">reference_wrapper</code> access</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.1.2.4</td><td align="left"><code class="code">reference_wrapper</code> invocation</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.1.2.5</td><td align="left"><code class="code">reference_wrapper</code> helper functions</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.2</td><td align="left">Smart pointers</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">2.2.1</td><td align="left">Additions to header <code class="code"><memory></code> synopsis</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.2.2</td><td align="left">Class <code class="code">bad_weak_ptr</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.2.3</td><td align="left">Class template <code class="code">shared_ptr</code></td><td align="left"> </td><td align="left">

1345

<p>

1346

Uses code from

1347

<a class="link" href="http://www.boost.org/libs/smart_ptr/shared_ptr.htm" target="_top">boost::shared_ptr</a>.

1348

@@ -323,7 +323,7 @@

1349

</p><p>

1350

This page describes the TR 24733 support in mainline GCC SVN, not in any

1351

particular release.

1352

-</p><div class="table"><a id="idp12559072"></a><p class="title"><strong>Table 1.4. C++ TR 24733 Implementation Status</strong></p><div class="table-contents"><table summary="C++ TR 24733 Implementation Status" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Section</th><th align="left">Description</th><th align="left">Status</th><th align="left">Comments</th></tr></thead><tbody><tr><td align="left">

1353

+</p><div class="table"><a id="idm270002960368"></a><p class="title"><strong>Table 1.4. C++ TR 24733 Implementation Status</strong></p><div class="table-contents"><table summary="C++ TR 24733 Implementation Status" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Section</th><th align="left">Description</th><th align="left">Status</th><th align="left">Comments</th></tr></thead><tbody><tr><td align="left">

1354

1355

</td><td colspan="3" align="left">

1356

<span class="emphasis"><em>Introduction</em></span>

1357

Index: libstdc++-v3/doc/html/manual/profile_mode_devel.html

1358

===================================================================

1359

--- a/src/libstdc++-v3/doc/html/manual/profile_mode_devel.html (.../tags/gcc_4_8_2_release)

1360

+++ b/src/libstdc++-v3/doc/html/manual/profile_mode_devel.html (.../branches/gcc-4_8-branch)

1361

@@ -1,5 +1,5 @@

1362

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

1363

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Developer Information</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="prev" href="profile_mode_impl.html" title="Implementation Issues" /><link rel="next" href="profile_mode_diagnostics.html" title="Diagnostics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Developer Information</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="profile_mode_impl.html">Prev</a> </td><th width="60%" align="center">Chapter 19. Profile Mode</th><td width="20%" align="right"> <a accesskey="n" href="profile_mode_diagnostics.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.developer"></a>Developer Information</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.ext.profile_mode.developer.bigpic"></a>Big Picture</h3></div></div></div><p>The profile mode headers are included with

1364

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Developer Information</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="prev" href="profile_mode_impl.html" title="Implementation Issues" /><link rel="next" href="profile_mode_diagnostics.html" title="Diagnostics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Developer Information</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="profile_mode_impl.html">Prev</a> </td><th width="60%" align="center">Chapter 19. Profile Mode</th><td width="20%" align="right"> <a accesskey="n" href="profile_mode_diagnostics.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.developer"></a>Developer Information</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.ext.profile_mode.developer.bigpic"></a>Big Picture</h3></div></div></div><p>The profile mode headers are included with

1365

<code class="code">-D_GLIBCXX_PROFILE</code> through preprocessor directives in

1366

<code class="code">include/std/*</code>.

1367

</p><p>Instrumented implementations are provided in

1368

Index: libstdc++-v3/doc/html/manual/debug_mode_design.html

1369

===================================================================

1370

--- a/src/libstdc++-v3/doc/html/manual/debug_mode_design.html (.../tags/gcc_4_8_2_release)

1371

+++ b/src/libstdc++-v3/doc/html/manual/debug_mode_design.html (.../branches/gcc-4_8-branch)

1372

@@ -1,5 +1,5 @@

1373

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

1374

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="C++, library, debug" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="debug_mode.html" title="Chapter 17. Debug Mode" /><link rel="prev" href="debug_mode_using.html" title="Using" /><link rel="next" href="parallel_mode.html" title="Chapter 18. Parallel Mode" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="debug_mode_using.html">Prev</a> </td><th width="60%" align="center">Chapter 17. Debug Mode</th><td width="20%" align="right"> <a accesskey="n" href="parallel_mode.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.debug_mode.design"></a>Design</h2></div></div></div><p>

1375

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, debug" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="debug_mode.html" title="Chapter 17. Debug Mode" /><link rel="prev" href="debug_mode_using.html" title="Using" /><link rel="next" href="parallel_mode.html" title="Chapter 18. Parallel Mode" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="debug_mode_using.html">Prev</a> </td><th width="60%" align="center">Chapter 17. Debug Mode</th><td width="20%" align="right"> <a accesskey="n" href="parallel_mode.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.debug_mode.design"></a>Design</h2></div></div></div><p>

1376

</p><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="debug_mode.design.goals"></a>Goals</h3></div></div></div><p>

1377

</p><p> The libstdc++ debug mode replaces unsafe (but efficient) standard

1378

containers and iterators with semantically equivalent safe standard

1379

@@ -391,7 +391,7 @@

1380

</p><p> There are several existing implementations of debug modes for C++

1381

standard library implementations, although none of them directly

1382

supports debugging for programs using libstdc++. The existing

1383

- implementations include:</p><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p><a class="link" href="http://www.mathcs.sjsu.edu/faculty/horstman/safestl.html" target="_top">SafeSTL</a>:

1384

+ implementations include:</p><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p><a class="link" href="http://www.cs.sjsu.edu/faculty/horstman/safestl.html" target="_top">SafeSTL</a>:

1385

SafeSTL was the original debugging version of the Standard Template

1386

Library (STL), implemented by Cay S. Horstmann on top of the

1387

Hewlett-Packard STL. Though it inspired much work in this area, it

1388

Index: libstdc++-v3/doc/html/manual/policy_data_structures_design.html

1389

===================================================================

1390

--- a/src/libstdc++-v3/doc/html/manual/policy_data_structures_design.html (.../tags/gcc_4_8_2_release)

1391

+++ b/src/libstdc++-v3/doc/html/manual/policy_data_structures_design.html (.../branches/gcc-4_8-branch)

1392

@@ -1,5 +1,5 @@

1393

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

1394

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, policy, container, data, structure, associated, tree, trie, hash, metaprogramming" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="policy_data_structures.html" title="Chapter 22. Policy-Based Data Structures" /><link rel="prev" href="policy_data_structures_using.html" title="Using" /><link rel="next" href="policy_based_data_structures_test.html" title="Testing" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="policy_data_structures_using.html">Prev</a> </td><th width="60%" align="center">Chapter 22. Policy-Based Data Structures</th><td width="20%" align="right"> <a accesskey="n" href="policy_based_data_structures_test.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="containers.pbds.design"></a>Design</h2></div></div></div><p></p><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="pbds.design.concepts"></a>Concepts</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="pbds.design.concepts.null_type"></a>Null Policy Classes</h4></div></div></div><p>

1395

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, policy, container, data, structure, associated, tree, trie, hash, metaprogramming" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="policy_data_structures.html" title="Chapter 22. Policy-Based Data Structures" /><link rel="prev" href="policy_data_structures_using.html" title="Using" /><link rel="next" href="policy_based_data_structures_test.html" title="Testing" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="policy_data_structures_using.html">Prev</a> </td><th width="60%" align="center">Chapter 22. Policy-Based Data Structures</th><td width="20%" align="right"> <a accesskey="n" href="policy_based_data_structures_test.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="containers.pbds.design"></a>Design</h2></div></div></div><p></p><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="pbds.design.concepts"></a>Concepts</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="pbds.design.concepts.null_type"></a>Null Policy Classes</h4></div></div></div><p>

1396

Associative containers are typically parametrized by various

1397

policies. For example, a hash-based associative container is

1398

parametrized by a hash-functor, transforming each key into an

1399

@@ -170,7 +170,7 @@

1400

naturally; collision-chaining hash tables (label B) store

1401

equivalent-key values in the same bucket, the bucket can be

1402

arranged so that equivalent-key values are consecutive.

1403

- </p><div class="figure"><a id="idp18000448"></a><p class="title"><strong>Figure 22.8. Non-unique Mapping Standard Containers</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_embedded_lists_1.png" align="middle" alt="Non-unique Mapping Standard Containers" /></div></div></div><br class="figure-break" /><p>

1404

+ </p><div class="figure"><a id="idm269997530416"></a><p class="title"><strong>Figure 22.8. Non-unique Mapping Standard Containers</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_embedded_lists_1.png" align="middle" alt="Non-unique Mapping Standard Containers" /></div></div></div><br class="figure-break" /><p>

1405

Put differently, the standards' non-unique mapping

1406

associative-containers are associative containers that map

1407

primary keys to linked lists that are embedded into the

1408

@@ -252,7 +252,7 @@

1409

first graphic above. Labels A and B, respectively. Each shaded

1410

box represents some size-type or secondary

1411

associative-container.

1412

- </p><div class="figure"><a id="idp18023952"></a><p class="title"><strong>Figure 22.10. Non-unique Mapping Containers</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_embedded_lists_3.png" align="middle" alt="Non-unique Mapping Containers" /></div></div></div><br class="figure-break" /><p>

1413

+ </p><div class="figure"><a id="idm269997506912"></a><p class="title"><strong>Figure 22.10. Non-unique Mapping Containers</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_embedded_lists_3.png" align="middle" alt="Non-unique Mapping Containers" /></div></div></div><br class="figure-break" /><p>

1414

In the first example above, then, one would use an associative

1415

container mapping each user to an associative container which

1416

maps each application id to a start time (see

1417

@@ -305,7 +305,7 @@

1418

shows invariants for order-preserving containers: point-type

1419

iterators are synonymous with range-type iterators.

1420

Orthogonally, <span class="emphasis"><em>C</em></span>shows invariants for "set"

1421

- containers: iterators are synonymous with const iterators.</p><div class="figure"><a id="idp18043824"></a><p class="title"><strong>Figure 22.11. Point Iterator Hierarchy</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_point_iterator_hierarchy.png" align="middle" alt="Point Iterator Hierarchy" /></div></div></div><br class="figure-break" /><p>Note that point-type iterators in self-organizing containers

1422

+ containers: iterators are synonymous with const iterators.</p><div class="figure"><a id="idm269997487104"></a><p class="title"><strong>Figure 22.11. Point Iterator Hierarchy</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_point_iterator_hierarchy.png" align="middle" alt="Point Iterator Hierarchy" /></div></div></div><br class="figure-break" /><p>Note that point-type iterators in self-organizing containers

1423

(hash-based associative containers) lack movement

1424

operators, such as <code class="literal">operator++</code> - in fact, this

1425

is the reason why this library differentiates from the standard C++ librarys

1426

@@ -344,7 +344,7 @@

1427

to the question of whether point-type iterators and range-type

1428

iterators are valid. The graphic below shows tags corresponding to

1429

different types of invalidation guarantees.

1430

- </p><div class="figure"><a id="idp18057168"></a><p class="title"><strong>Figure 22.12. Invalidation Guarantee Tags Hierarchy</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_invalidation_tag_hierarchy.png" align="middle" alt="Invalidation Guarantee Tags Hierarchy" /></div></div></div><br class="figure-break" /><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p>

1431

+ </p><div class="figure"><a id="idm269997473760"></a><p class="title"><strong>Figure 22.12. Invalidation Guarantee Tags Hierarchy</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_invalidation_tag_hierarchy.png" align="middle" alt="Invalidation Guarantee Tags Hierarchy" /></div></div></div><br class="figure-break" /><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p>

1432

<code class="classname">basic_invalidation_guarantee</code>

1433

corresponds to a basic guarantee that a point-type iterator,

1434

a found pointer, or a found reference, remains valid as long

1435

@@ -428,7 +428,7 @@

1436

</p><p>

1437

This library contains a container tag hierarchy corresponding to the

1438

diagram below.

1439

- </p><div class="figure"><a id="idp18087392"></a><p class="title"><strong>Figure 22.13. Container Tag Hierarchy</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_container_tag_hierarchy.png" align="middle" alt="Container Tag Hierarchy" /></div></div></div><br class="figure-break" /><p>

1440

+ </p><div class="figure"><a id="idm269997443664"></a><p class="title"><strong>Figure 22.13. Container Tag Hierarchy</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_container_tag_hierarchy.png" align="middle" alt="Container Tag Hierarchy" /></div></div></div><br class="figure-break" /><p>

1441

Given any container <span class="type">Cntnr</span>, the tag of

1442

the underlying data structure can be found via <code class="literal">typename

1443

Cntnr::container_category</code>.

1444

@@ -487,7 +487,7 @@

1445

collision-chaining container, except for the following.</p><div class="orderedlist"><ol class="orderedlist" type="1"><li class="listitem"><p><code class="classname">Comb_Probe_Fn</code> describes how to transform a probe

1446

sequence into a sequence of positions within the table.</p></li><li class="listitem"><p><code class="classname">Probe_Fn</code> describes a probe sequence policy.</p></li></ol></div><p>Some of the default template values depend on the values of

1447

other parameters, and are explained below.</p></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="container.hash.details"></a>Details</h5></div></div></div><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="container.hash.details.hash_policies"></a>Hash Policies</h6></div></div></div><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="details.hash_policies.general"></a>General</h6></div></div></div><p>Following is an explanation of some functions which hashing

1448

- involves. The graphic below illustrates the discussion.</p><div class="figure"><a id="idp18127536"></a><p class="title"><strong>Figure 22.14. Hash functions, ranged-hash functions, and

1449

+ involves. The graphic below illustrates the discussion.</p><div class="figure"><a id="idm269997403584"></a><p class="title"><strong>Figure 22.14. Hash functions, ranged-hash functions, and

1450

range-hashing functions</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_hash_ranged_hash_range_hashing_fns.png" align="middle" alt="Hash functions, ranged-hash functions, and range-hashing functions" /></div></div></div><br class="figure-break" /><p>Let U be a domain (e.g., the integers, or the

1451

strings of 3 characters). A hash-table algorithm needs to map

1452

elements of U "uniformly" into the range [0,..., m -

1453

@@ -504,7 +504,7 @@

1454

Z<sub>+</sub>,</p><p>which maps a non-negative hash value, and a non-negative

1455

range upper-bound into a non-negative integral in the range

1456

between 0 (inclusive) and the range upper bound (exclusive),

1457

- i.e., for any r in Z<sub>+</sub>,</p><p>0 ≤ g(r, m) ≤ m - 1</p><p>The resulting ranged-hash function, is</p><div class="equation"><a id="idp18141344"></a><p class="title"><strong>Equation 22.1. Ranged Hash Function</strong></p><div class="equation-contents"><span class="mathphrase">

1458

+ i.e., for any r in Z<sub>+</sub>,</p><p>0 ≤ g(r, m) ≤ m - 1</p><p>The resulting ranged-hash function, is</p><div class="equation"><a id="idm269997389776"></a><p class="title"><strong>Equation 22.1. Ranged Hash Function</strong></p><div class="equation-contents"><span class="mathphrase">

1459

f(u , m) = g(h(u), m)

1460

</span></div></div><br class="equation-break" /><p>From the above, it is obvious that given g and

1461

h, f can always be composed (however the converse

1462

@@ -524,7 +524,7 @@

1463

transforming the sequence of hash values into a sequence of

1464

positions.</p></div><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="details.hash_policies.range"></a>Range Hashing</h6></div></div></div><p>Some common choices for range-hashing functions are the

1465

division, multiplication, and middle-square methods (<a class="xref" href="policy_data_structures.html#biblio.knuth98sorting" title="The Art of Computer Programming - Sorting and Searching">[biblio.knuth98sorting]</a>), defined

1466

- as</p><div class="equation"><a id="idp18147232"></a><p class="title"><strong>Equation 22.2. Range-Hashing, Division Method</strong></p><div class="equation-contents"><span class="mathphrase">

1467

+ as</p><div class="equation"><a id="idm269997383888"></a><p class="title"><strong>Equation 22.2. Range-Hashing, Division Method</strong></p><div class="equation-contents"><span class="mathphrase">

1468

g(r, m) = r mod m

1469

</span></div></div><br class="equation-break" /><p>g(r, m) = ⌈ u/v ( a r mod v ) ⌉</p><p>and</p><p>g(r, m) = ⌈ u/v ( r<sup>2</sup> mod v ) ⌉</p><p>respectively, for some positive integrals u and

1470

v (typically powers of 2), and some a. Each of

1471

@@ -535,9 +535,9 @@

1472

implement using the low

1473

level % (modulo) operation (for any m), or the

1474

low level & (bit-mask) operation (for the case where

1475

- m is a power of 2), i.e.,</p><div class="equation"><a id="idp18151744"></a><p class="title"><strong>Equation 22.3. Division via Prime Modulo</strong></p><div class="equation-contents"><span class="mathphrase">

1476

+ m is a power of 2), i.e.,</p><div class="equation"><a id="idm269997379376"></a><p class="title"><strong>Equation 22.3. Division via Prime Modulo</strong></p><div class="equation-contents"><span class="mathphrase">

1477

g(r, m) = r % m

1478

- </span></div></div><br class="equation-break" /><p>and</p><div class="equation"><a id="idp18153568"></a><p class="title"><strong>Equation 22.4. Division via Bit Mask</strong></p><div class="equation-contents"><span class="mathphrase">

1479

+ </span></div></div><br class="equation-break" /><p>and</p><div class="equation"><a id="idm269997377552"></a><p class="title"><strong>Equation 22.4. Division via Bit Mask</strong></p><div class="equation-contents"><span class="mathphrase">

1480

g(r, m) = r & m - 1, (with m =

1481

2<sup>k</sup> for some k)

1482

</span></div></div><br class="equation-break" /><p>respectively.</p><p>The % (modulo) implementation has the advantage that for

1483

@@ -563,7 +563,7 @@

1484

s = [ s<sub>0</sub>,..., s<sub>t - 1</sub>]

1485

</p><p>be a string of t characters, each of which is from

1486

domain S. Consider the following ranged-hash

1487

- function:</p><div class="equation"><a id="idp18163200"></a><p class="title"><strong>Equation 22.5.

1488

+ function:</p><div class="equation"><a id="idm269997367984"></a><p class="title"><strong>Equation 22.5.

1489

A Standard String Hash Function

1490

</strong></p><div class="equation-contents"><span class="mathphrase">

1491

f<sub>1</sub>(s, m) = ∑ <sub>i =

1492

@@ -575,7 +575,7 @@

1493

of a long DNA sequence (and so S = {'A', 'C', 'G',

1494

'T'}). In this case, scanning the entire string might be

1495

prohibitively expensive. A possible alternative might be to use

1496

- only the first k characters of the string, where</p><p>|S|<sup>k</sup> ≥ m ,</p><p>i.e., using the hash function</p><div class="equation"><a id="idp18169344"></a><p class="title"><strong>Equation 22.6.

1497

+ only the first k characters of the string, where</p><p>|S|<sup>k</sup> ≥ m ,</p><p>i.e., using the hash function</p><div class="equation"><a id="idm269997361840"></a><p class="title"><strong>Equation 22.6.

1498

Only k String DNA Hash

1499

</strong></p><div class="equation-contents"><span class="mathphrase">

1500

f<sub>2</sub>(s, m) = ∑ <sub>i

1501

@@ -606,12 +606,12 @@

1502

the container transforms the key into a non-negative integral

1503

using the hash functor (points B and C), and transforms the

1504

result into a position using the combining functor (points D

1505

- and E).</p><div class="figure"><a id="idp18191968"></a><p class="title"><strong>Figure 22.15. Insert hash sequence diagram</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_hash_range_hashing_seq_diagram.png" align="middle" alt="Insert hash sequence diagram" /></div></div></div><br class="figure-break" /><p>If <code class="classname">cc_hash_table</code>'s

1506

+ and E).</p><div class="figure"><a id="idm269997339216"></a><p class="title"><strong>Figure 22.15. Insert hash sequence diagram</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_hash_range_hashing_seq_diagram.png" align="middle" alt="Insert hash sequence diagram" /></div></div></div><br class="figure-break" /><p>If <code class="classname">cc_hash_table</code>'s

1507

hash-functor, <code class="classname">Hash_Fn</code> is instantiated by <code class="classname">null_type</code> , then <code class="classname">Comb_Hash_Fn</code> is taken to be

1508

a ranged-hash function. The graphic below shows an <code class="function">insert</code> sequence

1509

diagram. The user inserts an element (point A), the container

1510

transforms the key into a position using the combining functor

1511

- (points B and C).</p><div class="figure"><a id="idp18199024"></a><p class="title"><strong>Figure 22.16. Insert hash sequence diagram with a null policy</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_hash_range_hashing_seq_diagram2.png" align="middle" alt="Insert hash sequence diagram with a null policy" /></div></div></div><br class="figure-break" /></div><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="hash_policies.implementation.probe"></a>

1512

+ (points B and C).</p><div class="figure"><a id="idm269997332160"></a><p class="title"><strong>Figure 22.16. Insert hash sequence diagram with a null policy</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_hash_range_hashing_seq_diagram2.png" align="middle" alt="Insert hash sequence diagram with a null policy" /></div></div></div><br class="figure-break" /></div><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="hash_policies.implementation.probe"></a>

1513

Probing tables

1514

</h6></div></div></div><p><code class="classname">gp_hash_table</code> is parametrized by

1515

<code class="classname">Hash_Fn</code>, <code class="classname">Probe_Fn</code>,

1516

@@ -634,7 +634,7 @@

1517

a linear probe and a quadratic probe function,

1518

respectively.</p></li></ol></div><p>

1519

The graphic below shows the relationships.

1520

- </p><div class="figure"><a id="idp18215840"></a><p class="title"><strong>Figure 22.17. Hash policy class diagram</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_hash_policy_cd.png" align="middle" alt="Hash policy class diagram" /></div></div></div><br class="figure-break" /></div></div></div><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="container.hash.details.resize_policies"></a>Resize Policies</h6></div></div></div><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="resize_policies.general"></a>General</h6></div></div></div><p>Hash-tables, as opposed to trees, do not naturally grow or

1521

+ </p><div class="figure"><a id="idm269997315408"></a><p class="title"><strong>Figure 22.17. Hash policy class diagram</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_hash_policy_cd.png" align="middle" alt="Hash policy class diagram" /></div></div></div><br class="figure-break" /></div></div></div><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="container.hash.details.resize_policies"></a>Resize Policies</h6></div></div></div><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="resize_policies.general"></a>General</h6></div></div></div><p>Hash-tables, as opposed to trees, do not naturally grow or

1522

shrink. It is necessary to specify policies to determine how

1523

and when a hash table should change its size. Usually, resize

1524

policies can be decomposed into orthogonal policies:</p><div class="orderedlist"><ol class="orderedlist" type="1"><li class="listitem"><p>A size policy indicating how a hash table

1525

@@ -667,10 +667,10 @@

1526

and some load factor be denoted by Α. We would like to

1527

calculate the minimal length of k, such that if there were Α

1528

m elements in the hash table, a probe sequence of length k would

1529

- be found with probability at most 1/m.</p><div class="figure"><a id="idp18234944"></a><p class="title"><strong>Figure 22.18. Balls and bins</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_balls_and_bins.png" align="middle" alt="Balls and bins" /></div></div></div><br class="figure-break" /><p>Denote the probability that a probe sequence of length

1530

+ be found with probability at most 1/m.</p><div class="figure"><a id="idm269997296368"></a><p class="title"><strong>Figure 22.18. Balls and bins</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_balls_and_bins.png" align="middle" alt="Balls and bins" /></div></div></div><br class="figure-break" /><p>Denote the probability that a probe sequence of length

1531

k appears in bin i by p<sub>i</sub>, the

1532

length of the probe sequence of bin i by

1533

- l<sub>i</sub>, and assume uniform distribution. Then</p><div class="equation"><a id="idp18240448"></a><p class="title"><strong>Equation 22.7.

1534

+ l<sub>i</sub>, and assume uniform distribution. Then</p><div class="equation"><a id="idm269997290864"></a><p class="title"><strong>Equation 22.7.

1535

Probability of Probe Sequence of Length k

1536

</strong></p><div class="equation-contents"><span class="mathphrase">

1537

p<sub>1</sub> =

1538

@@ -684,7 +684,7 @@

1539

l<sub>i</sub> are negatively-dependent

1540

(<a class="xref" href="policy_data_structures.html#biblio.dubhashi98neg" title="Balls and bins: A study in negative dependence">[biblio.dubhashi98neg]</a>)

1541

. Let

1542

- I(.) denote the indicator function. Then</p><div class="equation"><a id="idp18247216"></a><p class="title"><strong>Equation 22.8.

1543

+ I(.) denote the indicator function. Then</p><div class="equation"><a id="idm269997284096"></a><p class="title"><strong>Equation 22.8.

1544

Probability Probe Sequence in Some Bin

1545

</strong></p><div class="equation-contents"><span class="mathphrase">

1546

P( exists<sub>i</sub> l<sub>i</sub> ≥ k ) =

1547

@@ -723,7 +723,7 @@

1548

a resize is needed, and if so, what is the new size (points D

1549

to G); following the resize, it notifies the policy that a

1550

resize has completed (point H); finally, the element is

1551

- inserted, and the policy notified (point I).</p><div class="figure"><a id="idp18265728"></a><p class="title"><strong>Figure 22.19. Insert resize sequence diagram</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_insert_resize_sequence_diagram1.png" align="middle" alt="Insert resize sequence diagram" /></div></div></div><br class="figure-break" /><p>In practice, a resize policy can be usually orthogonally

1552

+ inserted, and the policy notified (point I).</p><div class="figure"><a id="idm269997265648"></a><p class="title"><strong>Figure 22.19. Insert resize sequence diagram</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_insert_resize_sequence_diagram1.png" align="middle" alt="Insert resize sequence diagram" /></div></div></div><br class="figure-break" /><p>In practice, a resize policy can be usually orthogonally

1553

decomposed to a size policy and a trigger policy. Consequently,

1554

the library contains a single class for instantiating a resize

1555

policy: <code class="classname">hash_standard_resize_policy</code>

1556

@@ -732,8 +732,8 @@

1557

both, and acts as a standard delegate (<a class="xref" href="policy_data_structures.html#biblio.gof" title="Design Patterns - Elements of Reusable Object-Oriented Software">[biblio.gof]</a>)

1558

to these policies.</p><p>The two graphics immediately below show sequence diagrams

1559

illustrating the interaction between the standard resize policy

1560

- and its trigger and size policies, respectively.</p><div class="figure"><a id="idp18273504"></a><p class="title"><strong>Figure 22.20. Standard resize policy trigger sequence

1561

- diagram</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_insert_resize_sequence_diagram2.png" align="middle" alt="Standard resize policy trigger sequence diagram" /></div></div></div><br class="figure-break" /><div class="figure"><a id="idp18277664"></a><p class="title"><strong>Figure 22.21. Standard resize policy size sequence

1562

+ and its trigger and size policies, respectively.</p><div class="figure"><a id="idm269997257872"></a><p class="title"><strong>Figure 22.20. Standard resize policy trigger sequence

1563

+ diagram</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_insert_resize_sequence_diagram2.png" align="middle" alt="Standard resize policy trigger sequence diagram" /></div></div></div><br class="figure-break" /><div class="figure"><a id="idm269997253712"></a><p class="title"><strong>Figure 22.21. Standard resize policy size sequence

1564

diagram</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_insert_resize_sequence_diagram3.png" align="middle" alt="Standard resize policy size sequence diagram" /></div></div></div><br class="figure-break" /></div><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="resize_policies.impl.predefined"></a>Predefined Policies</h6></div></div></div><p>The library includes the following

1565

instantiations of size and trigger policies:</p><div class="orderedlist"><ol class="orderedlist" type="1"><li class="listitem"><p><code class="classname">hash_load_check_resize_trigger</code>

1566

implements a load check trigger policy.</p></li><li class="listitem"><p><code class="classname">cc_hash_max_collision_check_resize_trigger</code>

1567

@@ -876,7 +876,7 @@

1568

each node, and maintains node invariants (see <a class="xref" href="policy_data_structures.html#biblio.clrs2001" title="Introduction to Algorithms, 2nd edition">[biblio.clrs2001]</a>.) The first stores in

1569

each node the size of the sub-tree rooted at the node; the

1570

second stores at each node the maximal endpoint of the

1571

- intervals at the sub-tree rooted at the node.</p><div class="figure"><a id="idp18355696"></a><p class="title"><strong>Figure 22.22. Tree node invariants</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_tree_node_invariants.png" align="middle" alt="Tree node invariants" /></div></div></div><br class="figure-break" /><p>Supporting such trees is difficult for a number of

1572

+ intervals at the sub-tree rooted at the node.</p><div class="figure"><a id="idm269997175616"></a><p class="title"><strong>Figure 22.22. Tree node invariants</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_tree_node_invariants.png" align="middle" alt="Tree node invariants" /></div></div></div><br class="figure-break" /><p>Supporting such trees is difficult for a number of

1573

reasons:</p><div class="orderedlist"><ol class="orderedlist" type="1"><li class="listitem"><p>There must be a way to specify what a node's metadata

1574

should be (if any).</p></li><li class="listitem"><p>Various operations can invalidate node

1575

invariants. The graphic below shows how a right rotation,

1576

@@ -890,7 +890,7 @@

1577

metadata.</p></li><li class="listitem"><p>It is not feasible to know in advance which methods trees

1578

can support. Besides the usual <code class="classname">find</code> method, the

1579

first tree can support a <code class="classname">find_by_order</code> method, while

1580

- the second can support an <code class="classname">overlaps</code> method.</p></li></ol></div><div class="figure"><a id="idp18365136"></a><p class="title"><strong>Figure 22.23. Tree node invalidation</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_tree_node_invalidations.png" align="middle" alt="Tree node invalidation" /></div></div></div><br class="figure-break" /><p>These problems are solved by a combination of two means:

1581

+ the second can support an <code class="classname">overlaps</code> method.</p></li></ol></div><div class="figure"><a id="idm269997166176"></a><p class="title"><strong>Figure 22.23. Tree node invalidation</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_tree_node_invalidations.png" align="middle" alt="Tree node invalidation" /></div></div></div><br class="figure-break" /><p>These problems are solved by a combination of two means:

1582

node iterators, and template-template node updater

1583

parameters.</p><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="container.tree.node.iterators"></a>Node Iterators</h6></div></div></div><p>Each tree-based container defines two additional iterator

1584

types, <code class="classname">const_node_iterator</code>

1585

@@ -919,7 +919,7 @@

1586

<code class="classname">node_update</code> class, and publicly subclasses

1587

<code class="classname">node_update</code>. The graphic below shows this

1588

scheme, as well as some predefined policies (which are explained

1589

- below).</p><div class="figure"><a id="idp18378304"></a><p class="title"><strong>Figure 22.24. A tree and its update policy</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_tree_node_updator_policy_cd.png" align="middle" alt="A tree and its update policy" /></div></div></div><br class="figure-break" /><p><code class="classname">node_update</code> (an instantiation of

1590

+ below).</p><div class="figure"><a id="idm269997153072"></a><p class="title"><strong>Figure 22.24. A tree and its update policy</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_tree_node_updator_policy_cd.png" align="middle" alt="A tree and its update policy" /></div></div></div><br class="figure-break" /><p><code class="classname">node_update</code> (an instantiation of

1591

<code class="classname">Node_Update</code>) must define <code class="classname">metadata_type</code> as

1592

the type of metadata it requires. For order statistics,

1593

e.g., <code class="classname">metadata_type</code> might be <code class="classname">size_t</code>.

1594

@@ -938,7 +938,7 @@

1595

<code class="classname">nd_it</code>. For example, say node x in the

1596

graphic below label A has an invalid invariant, but its' children,

1597

y and z have valid invariants. After the invocation, all three

1598

- nodes should have valid invariants, as in label B.</p><div class="figure"><a id="idp18389968"></a><p class="title"><strong>Figure 22.25. Restoring node invariants</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_restoring_node_invariants.png" align="middle" alt="Restoring node invariants" /></div></div></div><br class="figure-break" /><p>When a tree operation might invalidate some node invariant,

1599

+ nodes should have valid invariants, as in label B.</p><div class="figure"><a id="idm269997141408"></a><p class="title"><strong>Figure 22.25. Restoring node invariants</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_restoring_node_invariants.png" align="middle" alt="Restoring node invariants" /></div></div></div><br class="figure-break" /><p>When a tree operation might invalidate some node invariant,

1600

it invokes this method in its <code class="classname">node_update</code> base to

1601

restore the invariant. For example, the graphic below shows

1602

an <code class="function">insert</code> operation (point A); the tree performs some

1603

@@ -946,7 +946,7 @@

1604

C, and D). (It is well known that any <code class="function">insert</code>,

1605

<code class="function">erase</code>, <code class="function">split</code> or <code class="function">join</code>, can restore

1606

all node invariants by a small number of node invariant updates (<a class="xref" href="policy_data_structures.html#biblio.clrs2001" title="Introduction to Algorithms, 2nd edition">[biblio.clrs2001]</a>)

1607

- .</p><div class="figure"><a id="idp18398144"></a><p class="title"><strong>Figure 22.26. Insert update sequence</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_update_seq_diagram.png" align="middle" alt="Insert update sequence" /></div></div></div><br class="figure-break" /><p>To complete the description of the scheme, three questions

1608

+ .</p><div class="figure"><a id="idm269997133232"></a><p class="title"><strong>Figure 22.26. Insert update sequence</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_update_seq_diagram.png" align="middle" alt="Insert update sequence" /></div></div></div><br class="figure-break" /><p>To complete the description of the scheme, three questions

1609

need to be answered:</p><div class="orderedlist"><ol class="orderedlist" type="1"><li class="listitem"><p>How can a tree which supports order statistics define a

1610

method such as <code class="classname">find_by_order</code>?</p></li><li class="listitem"><p>How can the node updater base access methods of the

1611

tree?</p></li><li class="listitem"><p>How can the following cyclic dependency be resolved?

1612

@@ -988,7 +988,7 @@

1613

node's metadata (this is halting reducible). In the graphic

1614

below, assume the shaded node is inserted. The tree would have

1615

to traverse the useless path shown to the root, applying

1616

- redundant updates all the way.</p></li></ol></div><div class="figure"><a id="idp18420400"></a><p class="title"><strong>Figure 22.27. Useless update path</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_rationale_null_node_updator.png" align="middle" alt="Useless update path" /></div></div></div><br class="figure-break" /><p>A null policy class, <code class="classname">null_node_update</code>

1617

+ redundant updates all the way.</p></li></ol></div><div class="figure"><a id="idm269997110976"></a><p class="title"><strong>Figure 22.27. Useless update path</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_rationale_null_node_updator.png" align="middle" alt="Useless update path" /></div></div></div><br class="figure-break" /><p>A null policy class, <code class="classname">null_node_update</code>

1618

solves both these problems. The tree detects that node

1619

invariants are irrelevant, and defines all accordingly.</p></div></div><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="container.tree.details.split"></a>Split and Join</h6></div></div></div><p>Tree-based containers support split and join methods.

1620

It is possible to split a tree so that it passes

1621

@@ -1071,7 +1071,7 @@

1622

sub-tree with leafs "a" and "as". The maximal common prefix is

1623

"a". The internal node contains, consequently, to const

1624

iterators, one pointing to <code class="varname">'a'</code>, and the other to

1625

- <code class="varname">'s'</code>.</p><div class="figure"><a id="idp18465088"></a><p class="title"><strong>Figure 22.28. A PATRICIA trie</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_pat_trie.png" align="middle" alt="A PATRICIA trie" /></div></div></div><br class="figure-break" /></div><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="container.trie.details.node"></a>Node Invariants</h6></div></div></div><p>Trie-based containers support node invariants, as do

1626

+ <code class="varname">'s'</code>.</p><div class="figure"><a id="idm269997066288"></a><p class="title"><strong>Figure 22.28. A PATRICIA trie</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_pat_trie.png" align="middle" alt="A PATRICIA trie" /></div></div></div><br class="figure-break" /></div><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="container.trie.details.node"></a>Node Invariants</h6></div></div></div><p>Trie-based containers support node invariants, as do

1627

tree-based containers. There are two minor

1628

differences, though, which, unfortunately, thwart sharing them

1629

sharing the same node-updating policies:</p><div class="orderedlist"><ol class="orderedlist" type="1"><li class="listitem"><p>A trie's <code class="classname">Node_Update</code> template-template

1630

@@ -1080,7 +1080,7 @@

1631

parametrized by <code class="classname">Cmp_Fn</code>.</p></li><li class="listitem"><p>Tree-based containers store values in all nodes, while

1632

trie-based containers (at least in this implementation) store

1633

values in leafs.</p></li></ol></div><p>The graphic below shows the scheme, as well as some predefined

1634

- policies (which are explained below).</p><div class="figure"><a id="idp18475584"></a><p class="title"><strong>Figure 22.29. A trie and its update policy</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_trie_node_updator_policy_cd.png" align="middle" alt="A trie and its update policy" /></div></div></div><br class="figure-break" /><p>This library offers the following pre-defined trie node

1635

+ policies (which are explained below).</p><div class="figure"><a id="idm269997055856"></a><p class="title"><strong>Figure 22.29. A trie and its update policy</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_trie_node_updator_policy_cd.png" align="middle" alt="A trie and its update policy" /></div></div></div><br class="figure-break" /><p>This library offers the following pre-defined trie node

1636

updating policies:</p><div class="orderedlist"><ol class="orderedlist" type="1"><li class="listitem"><p>

1637

<code class="classname">trie_order_statistics_node_update</code>

1638

supports order statistics.

1639

@@ -1128,7 +1128,7 @@

1640

simple list of integer keys. If we search for the integer 6, we

1641

are paying an overhead: the link with key 6 is only the fifth

1642

link; if it were the first link, it could be accessed

1643

- faster.</p><div class="figure"><a id="idp18506160"></a><p class="title"><strong>Figure 22.30. A simple list</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_simple_list.png" align="middle" alt="A simple list" /></div></div></div><br class="figure-break" /><p>List-update algorithms reorder lists as elements are

1644

+ faster.</p><div class="figure"><a id="idm269997025344"></a><p class="title"><strong>Figure 22.30. A simple list</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_simple_list.png" align="middle" alt="A simple list" /></div></div></div><br class="figure-break" /><p>List-update algorithms reorder lists as elements are

1645

accessed. They try to determine, by the access history, which

1646

keys to move to the front of the list. Some of these algorithms

1647

require adding some metadata alongside each entry.</p><p>For example, in the graphic below label A shows the counter

1648

@@ -1138,7 +1138,7 @@

1649

predetermined value, say 10, as shown in label C, the count is set

1650

to 0 and the node is moved to the front of the list, as in label

1651

D.

1652

- </p><div class="figure"><a id="idp18511744"></a><p class="title"><strong>Figure 22.31. The counter algorithm</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_list_update.png" align="middle" alt="The counter algorithm" /></div></div></div><br class="figure-break" /></div><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="container.list.details.policies"></a>Policies</h6></div></div></div><p>this library allows instantiating lists with policies

1653

+ </p><div class="figure"><a id="idm269997019760"></a><p class="title"><strong>Figure 22.31. The counter algorithm</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_list_update.png" align="middle" alt="The counter algorithm" /></div></div></div><br class="figure-break" /></div><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="container.list.details.policies"></a>Policies</h6></div></div></div><p>this library allows instantiating lists with policies

1654

implementing any algorithm moving nodes to the front of the

1655

list (policies implementing algorithms interchanging nodes are

1656

unsupported).</p><p>Associative containers based on lists are parametrized by a

1657

@@ -1310,7 +1310,7 @@

1658

sequence; the second uses a tree (or forest of trees), which is

1659

typically less structured than an associative container's tree;

1660

the third simply uses an associative container. These are

1661

- shown in the graphic below, in labels A1 and A2, label B, and label C.</p><div class="figure"><a id="idp18575568"></a><p class="title"><strong>Figure 22.32. Underlying Priority-Queue Data-Structures.</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_priority_queue_different_underlying_dss.png" align="middle" alt="Underlying Priority-Queue Data-Structures." /></div></div></div><br class="figure-break" /><p>Roughly speaking, any value that is both pushed and popped

1662

+ shown in the graphic below, in labels A1 and A2, label B, and label C.</p><div class="figure"><a id="idm269996955920"></a><p class="title"><strong>Figure 22.32. Underlying Priority-Queue Data-Structures.</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_priority_queue_different_underlying_dss.png" align="middle" alt="Underlying Priority-Queue Data-Structures." /></div></div></div><br class="figure-break" /><p>Roughly speaking, any value that is both pushed and popped

1663

from a priority queue must incur a logarithmic expense (in the

1664

amortized sense). Any priority queue implementation that would

1665

avoid this, would violate known bounds on comparison-based

1666

@@ -1390,7 +1390,7 @@

1667

container <code class="classname">Cntnr</code>, the tag of the underlying

1668

data structure can be found via <code class="classname">typename

1669

Cntnr::container_category</code>; this is one of the possible tags shown in the graphic below.

1670

- </p><div class="figure"><a id="idp18610544"></a><p class="title"><strong>Figure 22.33. Priority-Queue Data-Structure Tags.</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_priority_queue_tag_hierarchy.png" align="middle" alt="Priority-Queue Data-Structure Tags." /></div></div></div><br class="figure-break" /><p>Additionally, a traits mechanism can be used to query a

1671

+ </p><div class="figure"><a id="idm269996920880"></a><p class="title"><strong>Figure 22.33. Priority-Queue Data-Structure Tags.</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_priority_queue_tag_hierarchy.png" align="middle" alt="Priority-Queue Data-Structure Tags." /></div></div></div><br class="figure-break" /><p>Additionally, a traits mechanism can be used to query a

1672

container type for its attributes. Given any container

1673

<code class="classname">Cntnr</code>, then </p><pre class="programlisting">__gnu_pbds::container_traits<Cntnr></pre><p>

1674

is a traits class identifying the properties of the

1675

Index: libstdc++-v3/doc/html/manual/using.html

1676

===================================================================

1677

--- a/src/libstdc++-v3/doc/html/manual/using.html (.../tags/gcc_4_8_2_release)

1678

+++ b/src/libstdc++-v3/doc/html/manual/using.html (.../branches/gcc-4_8-branch)

1679

@@ -1,8 +1,8 @@

1680

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

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-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 3. Using</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="intro.html" title="Part I. Introduction" /><link rel="prev" href="make.html" title="Make" /><link rel="next" href="using_headers.html" title="Headers" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 3. Using</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="make.html">Prev</a> </td><th width="60%" align="center">Part I.

1682

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 3. Using</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="intro.html" title="Part I. Introduction" /><link rel="prev" href="make.html" title="Make" /><link rel="next" href="using_headers.html" title="Headers" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 3. Using</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="make.html">Prev</a> </td><th width="60%" align="center">Part I.

1683

Introduction

1684

1685

-</th><td width="20%" align="right"> <a accesskey="n" href="using_headers.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.intro.using"></a>Chapter 3. Using</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="using.html#manual.intro.using.flags">Command Options</a></span></dt><dt><span class="section"><a href="using_headers.html">Headers</a></span></dt><dd><dl><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.all">Header Files</a></span></dt><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.mixing">Mixing Headers</a></span></dt><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.cheaders">The C Headers and <code class="code">namespace std</code></a></span></dt><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.pre">Precompiled Headers</a></span></dt></dl></dd><dt><span class="section"><a href="using_macros.html">Macros</a></span></dt><dt><span class="section"><a href="using_namespaces.html">Namespaces</a></span></dt><dd><dl><dt><span class="section"><a href="using_namespaces.html#manual.intro.using.namespaces.all">Available Namespaces</a></span></dt><dt><span class="section"><a href="using_namespaces.html#manual.intro.using.namespaces.std">namespace std</a></span></dt><dt><span class="section"><a href="using_namespaces.html#manual.intro.using.namespaces.comp">Using Namespace Composition</a></span></dt></dl></dd><dt><span class="section"><a href="using_dynamic_or_shared.html">Linking</a></span></dt><dd><dl><dt><span class="section"><a href="using_dynamic_or_shared.html#manual.intro.using.linkage.freestanding">Almost Nothing</a></span></dt><dt><span class="section"><a href="using_dynamic_or_shared.html#manual.intro.using.linkage.dynamic">Finding Dynamic or Shared Libraries</a></span></dt></dl></dd><dt><span class="section"><a href="using_concurrency.html">Concurrency</a></span></dt><dd><dl><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.thread_safety">Thread Safety</a></span></dt><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.atomics">Atomics</a></span></dt><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.io">IO</a></span></dt><dd><dl><dt><span class="section"><a href="using_concurrency.html#concurrency.io.structure">Structure</a></span></dt><dt><span class="section"><a href="using_concurrency.html#concurrency.io.defaults">Defaults</a></span></dt><dt><span class="section"><a href="using_concurrency.html#concurrency.io.future">Future</a></span></dt><dt><span class="section"><a href="using_concurrency.html#concurrency.io.alt">Alternatives</a></span></dt></dl></dd><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.containers">Containers</a></span></dt></dl></dd><dt><span class="section"><a href="using_exceptions.html">Exceptions</a></span></dt><dd><dl><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.safety">Exception Safety</a></span></dt><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.propagating">Exception Neutrality</a></span></dt><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.no">Doing without</a></span></dt><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.compat">Compatibility</a></span></dt><dd><dl><dt><span class="section"><a href="using_exceptions.html#using.exception.compat.c">With <code class="literal">C</code></a></span></dt><dt><span class="section"><a href="using_exceptions.html#using.exception.compat.posix">With <code class="literal">POSIX</code> thread cancellation</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="debug.html">Debugging Support</a></span></dt><dd><dl><dt><span class="section"><a href="debug.html#debug.compiler">Using <span class="command"><strong>g++</strong></span></a></span></dt><dt><span class="section"><a href="debug.html#debug.req">Debug Versions of Library Binary Files</a></span></dt><dt><span class="section"><a href="debug.html#debug.memory">Memory Leak Hunting</a></span></dt><dt><span class="section"><a href="debug.html#debug.races">Data Race Hunting</a></span></dt><dt><span class="section"><a href="debug.html#debug.gdb">Using <span class="command"><strong>gdb</strong></span></a></span></dt><dt><span class="section"><a href="debug.html#debug.exceptions">Tracking uncaught exceptions</a></span></dt><dt><span class="section"><a href="debug.html#debug.debug_mode">Debug Mode</a></span></dt><dt><span class="section"><a href="debug.html#debug.compile_time_checks">Compile Time Checking</a></span></dt><dt><span class="section"><a href="debug.html#debug.profile_mode">Profile-based Performance Analysis</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.flags"></a>Command Options</h2></div></div></div><p>

1686

+</th><td width="20%" align="right"> <a accesskey="n" href="using_headers.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.intro.using"></a>Chapter 3. Using</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="using.html#manual.intro.using.flags">Command Options</a></span></dt><dt><span class="section"><a href="using_headers.html">Headers</a></span></dt><dd><dl><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.all">Header Files</a></span></dt><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.mixing">Mixing Headers</a></span></dt><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.cheaders">The C Headers and <code class="code">namespace std</code></a></span></dt><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.pre">Precompiled Headers</a></span></dt></dl></dd><dt><span class="section"><a href="using_macros.html">Macros</a></span></dt><dt><span class="section"><a href="using_namespaces.html">Namespaces</a></span></dt><dd><dl><dt><span class="section"><a href="using_namespaces.html#manual.intro.using.namespaces.all">Available Namespaces</a></span></dt><dt><span class="section"><a href="using_namespaces.html#manual.intro.using.namespaces.std">namespace std</a></span></dt><dt><span class="section"><a href="using_namespaces.html#manual.intro.using.namespaces.comp">Using Namespace Composition</a></span></dt></dl></dd><dt><span class="section"><a href="using_dynamic_or_shared.html">Linking</a></span></dt><dd><dl><dt><span class="section"><a href="using_dynamic_or_shared.html#manual.intro.using.linkage.freestanding">Almost Nothing</a></span></dt><dt><span class="section"><a href="using_dynamic_or_shared.html#manual.intro.using.linkage.dynamic">Finding Dynamic or Shared Libraries</a></span></dt></dl></dd><dt><span class="section"><a href="using_concurrency.html">Concurrency</a></span></dt><dd><dl><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.thread_safety">Thread Safety</a></span></dt><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.atomics">Atomics</a></span></dt><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.io">IO</a></span></dt><dd><dl><dt><span class="section"><a href="using_concurrency.html#concurrency.io.structure">Structure</a></span></dt><dt><span class="section"><a href="using_concurrency.html#concurrency.io.defaults">Defaults</a></span></dt><dt><span class="section"><a href="using_concurrency.html#concurrency.io.future">Future</a></span></dt><dt><span class="section"><a href="using_concurrency.html#concurrency.io.alt">Alternatives</a></span></dt></dl></dd><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.containers">Containers</a></span></dt></dl></dd><dt><span class="section"><a href="using_exceptions.html">Exceptions</a></span></dt><dd><dl><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.safety">Exception Safety</a></span></dt><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.propagating">Exception Neutrality</a></span></dt><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.no">Doing without</a></span></dt><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.compat">Compatibility</a></span></dt><dd><dl><dt><span class="section"><a href="using_exceptions.html#using.exception.compat.c">With <code class="literal">C</code></a></span></dt><dt><span class="section"><a href="using_exceptions.html#using.exception.compat.posix">With <code class="literal">POSIX</code> thread cancellation</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="debug.html">Debugging Support</a></span></dt><dd><dl><dt><span class="section"><a href="debug.html#debug.compiler">Using <span class="command"><strong>g++</strong></span></a></span></dt><dt><span class="section"><a href="debug.html#debug.req">Debug Versions of Library Binary Files</a></span></dt><dt><span class="section"><a href="debug.html#debug.memory">Memory Leak Hunting</a></span></dt><dt><span class="section"><a href="debug.html#debug.races">Data Race Hunting</a></span></dt><dt><span class="section"><a href="debug.html#debug.gdb">Using <span class="command"><strong>gdb</strong></span></a></span></dt><dt><span class="section"><a href="debug.html#debug.exceptions">Tracking uncaught exceptions</a></span></dt><dt><span class="section"><a href="debug.html#debug.debug_mode">Debug Mode</a></span></dt><dt><span class="section"><a href="debug.html#debug.compile_time_checks">Compile Time Checking</a></span></dt><dt><span class="section"><a href="debug.html#debug.profile_mode">Profile-based Performance Analysis</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.flags"></a>Command Options</h2></div></div></div><p>

1687

The set of features available in the GNU C++ library is shaped

1688

by

1689

several <a class="link" href="http://gcc.gnu.org/onlinedocs/gcc-4.3.2/gcc/Invoking-GCC.html" target="_top">GCC

1690

@@ -10,5 +10,5 @@

1691

enumerated and detailed in the table below.

1692

</p><p>

1693

By default, <span class="command"><strong>g++</strong></span> is equivalent to <span class="command"><strong>g++ -std=gnu++98</strong></span>. The standard library also defaults to this dialect.

1694

- </p><div class="table"><a id="idp13051936"></a><p class="title"><strong>Table 3.1. C++ Command Options</strong></p><div class="table-contents"><table summary="C++ Command Options" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><thead><tr><th align="left">Option Flags</th><th align="left">Description</th></tr></thead><tbody><tr><td align="left"><code class="literal">-std=c++98</code></td><td align="left">Use the 1998 ISO C++ standard plus amendments.</td></tr><tr><td align="left"><code class="literal">-std=gnu++98</code></td><td align="left">As directly above, with GNU extensions.</td></tr><tr><td align="left"><code class="literal">-std=c++11</code></td><td align="left">Use the 2011 ISO C++ standard.</td></tr><tr><td align="left"><code class="literal">-std=gnu++11</code></td><td align="left">As directly above, with GNU extensions.</td></tr><tr><td align="left"><code class="literal">-fexceptions</code></td><td align="left">See <a class="link" href="using_exceptions.html#intro.using.exception.no" title="Doing without">exception-free dialect</a></td></tr><tr><td align="left"><code class="literal">-frtti</code></td><td align="left">As above, but RTTI-free dialect.</td></tr><tr><td align="left"><code class="literal">-pthread</code> or <code class="literal">-pthreads</code></td><td align="left">For ISO C++11 <thread>, <future>,

1695

+ </p><div class="table"><a id="idm270002481088"></a><p class="title"><strong>Table 3.1. C++ Command Options</strong></p><div class="table-contents"><table summary="C++ Command Options" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><thead><tr><th align="left">Option Flags</th><th align="left">Description</th></tr></thead><tbody><tr><td align="left"><code class="literal">-std=c++98</code></td><td align="left">Use the 1998 ISO C++ standard plus amendments.</td></tr><tr><td align="left"><code class="literal">-std=gnu++98</code></td><td align="left">As directly above, with GNU extensions.</td></tr><tr><td align="left"><code class="literal">-std=c++11</code></td><td align="left">Use the 2011 ISO C++ standard.</td></tr><tr><td align="left"><code class="literal">-std=gnu++11</code></td><td align="left">As directly above, with GNU extensions.</td></tr><tr><td align="left"><code class="literal">-fexceptions</code></td><td align="left">See <a class="link" href="using_exceptions.html#intro.using.exception.no" title="Doing without">exception-free dialect</a></td></tr><tr><td align="left"><code class="literal">-frtti</code></td><td align="left">As above, but RTTI-free dialect.</td></tr><tr><td align="left"><code class="literal">-pthread</code> or <code class="literal">-pthreads</code></td><td align="left">For ISO C++11 <thread>, <future>,

1696

<mutex>, or <condition_variable>.</td></tr><tr><td align="left"><code class="literal">-fopenmp</code></td><td align="left">For <a class="link" href="parallel_mode.html" title="Chapter 18. Parallel Mode">parallel</a> mode.</td></tr></tbody></table></div></div><br class="table-break" /></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="make.html">Prev</a> </td><td width="20%" align="center"><a accesskey="u" href="intro.html">Up</a></td><td width="40%" align="right"> <a accesskey="n" href="using_headers.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">Make </td><td width="20%" align="center"><a accesskey="h" href="../index.html">Home</a></td><td width="40%" align="right" valign="top"> Headers</td></tr></table></div></body></html>

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Implementation Issues</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="prev" href="profile_mode_cost_model.html" title="Empirical Cost Model" /><link rel="next" href="profile_mode_devel.html" title="Developer Information" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Implementation Issues</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="profile_mode_cost_model.html">Prev</a> </td><th width="60%" align="center">Chapter 19. Profile Mode</th><td width="20%" align="right"> <a accesskey="n" href="profile_mode_devel.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.implementation"></a>Implementation Issues</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.ext.profile_mode.implementation.stack"></a>Stack Traces</h3></div></div></div><p>

1706

Accurate stack traces are needed during profiling since we group events by

1707

call context and dynamic instance. Without accurate traces, diagnostics

1708

may be hard to interpret. For instance, when giving advice to the user

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 23. HP/SGI Extensions</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III. Extensions" /><link rel="prev" href="policy_data_structures_ack.html" title="Acknowledgments" /><link rel="next" href="ext_sgi.html" title="Deprecated" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 23. HP/SGI Extensions</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="policy_data_structures_ack.html">Prev</a> </td><th width="60%" align="center">Part III.

1717

Extensions

1718

1719

-</th><td width="20%" align="right"> <a accesskey="n" href="ext_sgi.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.containers"></a>Chapter 23. HP/SGI Extensions</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="ext_containers.html#manual.ext.containers.sgi">Backwards Compatibility</a></span></dt><dt><span class="section"><a href="ext_sgi.html">Deprecated</a></span></dt></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.containers.sgi"></a>Backwards Compatibility</h2></div></div></div><p>A few extensions and nods to backwards-compatibility have

1720

+</th><td width="20%" align="right"> <a accesskey="n" href="ext_sgi.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.containers"></a>Chapter 23. HP/SGI Extensions</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="ext_containers.html#manual.ext.containers.sgi">Backwards Compatibility</a></span></dt><dt><span class="section"><a href="ext_sgi.html">Deprecated</a></span></dt></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.containers.sgi"></a>Backwards Compatibility</h2></div></div></div><p>A few extensions and nods to backwards-compatibility have

1721

been made with containers. Those dealing with older SGI-style

1722

allocators are dealt with elsewhere. The remaining ones all deal

1723

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1728

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1729

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

1730

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Use</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="ext_concurrency.html" title="Chapter 30. Concurrency" /><link rel="prev" href="ext_concurrency_impl.html" title="Implementation" /><link rel="next" href="appendix.html" title="Part IV. Appendices" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Use</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_concurrency_impl.html">Prev</a> </td><th width="60%" align="center">Chapter 30. Concurrency</th><td width="20%" align="right"> <a accesskey="n" href="appendix.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.concurrency.use"></a>Use</h2></div></div></div><p>Typical usage of the last two constructs is demonstrated as follows:

1731

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Use</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="ext_concurrency.html" title="Chapter 30. Concurrency" /><link rel="prev" href="ext_concurrency_impl.html" title="Implementation" /><link rel="next" href="appendix.html" title="Part IV. Appendices" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Use</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_concurrency_impl.html">Prev</a> </td><th width="60%" align="center">Chapter 30. Concurrency</th><td width="20%" align="right"> <a accesskey="n" href="appendix.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.concurrency.use"></a>Use</h2></div></div></div><p>Typical usage of the last two constructs is demonstrated as follows:

1732

</p><pre class="programlisting">

1733

#include <ext/concurrence.h>

1734

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 28. Input and Output</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III. Extensions" /><link rel="prev" href="ext_iterators.html" title="Chapter 27. Iterators" /><link rel="next" href="ext_demangling.html" title="Chapter 29. Demangling" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 28. Input and Output</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_iterators.html">Prev</a> </td><th width="60%" align="center">Part III.

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Extensions

1744

1745

-</th><td width="20%" align="right"> <a accesskey="n" href="ext_demangling.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.io"></a>Chapter 28. Input and Output</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="ext_io.html#manual.ext.io.filebuf_derived">Derived filebufs</a></span></dt></dl></div><p>

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+</th><td width="20%" align="right"> <a accesskey="n" href="ext_demangling.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.io"></a>Chapter 28. Input and Output</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="ext_io.html#manual.ext.io.filebuf_derived">Derived filebufs</a></span></dt></dl></div><p>

1747

Extensions allowing <code class="code">filebuf</code>s to be constructed from

1748

"C" types like FILE*s and file descriptors.

1749

</p><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.io.filebuf_derived"></a>Derived filebufs</h2></div></div></div><p>The v2 library included non-standard extensions to construct

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Termination</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="support.html" title="Chapter 4. Support" /><link rel="prev" href="dynamic_memory.html" title="Dynamic Memory" /><link rel="next" href="diagnostics.html" title="Chapter 5. Diagnostics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Termination</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="dynamic_memory.html">Prev</a> </td><th width="60%" align="center">Chapter 4.

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Support

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Macros</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_headers.html" title="Headers" /><link rel="next" href="using_namespaces.html" title="Namespaces" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Macros</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_headers.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="using_namespaces.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.macros"></a>Macros</h2></div></div></div><p>

1769

All library macros begin with <code class="code">_GLIBCXX_</code>.

1770

</p><p>

1771

Furthermore, all pre-processor macros, switches, and

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Concurrency

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Standard Contents

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</th><td width="20%" align="right"> <a accesskey="n" href="extensions.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="std.concurrency"></a>Chapter 15.

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Concurrency

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-</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="concurrency.html#std.concurrency.api">API Reference</a></span></dt></dl></div><p>

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+</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="concurrency.html#std.concurrency.api">API Reference</a></span></dt></dl></div><p>

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Facilities for concurrent operation, and control thereof.

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</p><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.concurrency.api"></a>API Reference</h2></div></div></div><p>

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All items are declared in one of four standard header files.

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 24. Utilities</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III. Extensions" /><link rel="prev" href="ext_sgi.html" title="Deprecated" /><link rel="next" href="ext_algorithms.html" title="Chapter 25. Algorithms" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 24. Utilities</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_sgi.html">Prev</a> </td><th width="60%" align="center">Part III.

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Extensions

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</th><td width="20%" align="right"> <a accesskey="n" href="ext_algorithms.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.util"></a>Chapter 24. Utilities</h2></div></div></div><p>

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Extensions

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-</th><td width="20%" align="right"> <a accesskey="n" href="policy_data_structures_using.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.containers.pbds"></a>Chapter 22. Policy-Based Data Structures</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="policy_data_structures.html#pbds.intro">Intro</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.issues">Performance Issues</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.issues.associative">Associative</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.issues.priority_queue">Priority Que</a></span></dt></dl></dd><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.motivation">Goals</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.motivation.associative">Associative</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#motivation.associative.policy">Policy Choices</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.associative.underlying">Underlying Data Structures</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.associative.iterators">Iterators</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.associative.functions">Functional</a></span></dt></dl></dd><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.motivation.priority_queue">Priority Queues</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#motivation.priority_queue.policy">Policy Choices</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.priority_queue.underlying">Underlying Data Structures</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.priority_queue.binary_heap">Binary Heaps</a></span></dt></dl></dd></dl></dd></dl></dd><dt><span class="section"><a href="policy_data_structures_using.html">Using</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.organization">Organization</a></span></dt><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.tutorial">Tutorial</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.tutorial.basic">Basic Use</a></span></dt><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.tutorial.configuring">

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+</th><td width="20%" align="right"> <a accesskey="n" href="policy_data_structures_using.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.containers.pbds"></a>Chapter 22. Policy-Based Data Structures</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="policy_data_structures.html#pbds.intro">Intro</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.issues">Performance Issues</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.issues.associative">Associative</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.issues.priority_queue">Priority Que</a></span></dt></dl></dd><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.motivation">Goals</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.motivation.associative">Associative</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#motivation.associative.policy">Policy Choices</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.associative.underlying">Underlying Data Structures</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.associative.iterators">Iterators</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.associative.functions">Functional</a></span></dt></dl></dd><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.motivation.priority_queue">Priority Queues</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#motivation.priority_queue.policy">Policy Choices</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.priority_queue.underlying">Underlying Data Structures</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.priority_queue.binary_heap">Binary Heaps</a></span></dt></dl></dd></dl></dd></dl></dd><dt><span class="section"><a href="policy_data_structures_using.html">Using</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.organization">Organization</a></span></dt><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.tutorial">Tutorial</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.tutorial.basic">Basic Use</a></span></dt><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.tutorial.configuring">

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Configuring via Template Parameters

1818

</a></span></dt><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.tutorial.traits">

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Querying Container Attributes

1820

@@ -248,7 +248,7 @@

1821

these invariants, one must supply some policy that is aware

1822

of these changes. Without this, it would be better to use a

1823

linked list (in itself very efficient for these purposes).

1824

- </p></li></ol></div><div class="figure"><a id="idp17613296"></a><p class="title"><strong>Figure 22.1. Node Invariants</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_node_invariants.png" align="middle" alt="Node Invariants" /></div></div></div><br class="figure-break" /></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="motivation.associative.underlying"></a>Underlying Data Structures</h5></div></div></div><p>

1825

+ </p></li></ol></div><div class="figure"><a id="idm269997917584"></a><p class="title"><strong>Figure 22.1. Node Invariants</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_node_invariants.png" align="middle" alt="Node Invariants" /></div></div></div><br class="figure-break" /></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="motivation.associative.underlying"></a>Underlying Data Structures</h5></div></div></div><p>

1826

The standard C++ library contains associative containers based on

1827

red-black trees and collision-chaining hash tables. These are

1828

very useful, but they are not ideal for all types of

1829

@@ -256,7 +256,7 @@

1830

</p><p>

1831

The figure below shows the different underlying data structures

1832

currently supported in this library.

1833

- </p><div class="figure"><a id="idp17619952"></a><p class="title"><strong>Figure 22.2. Underlying Associative Data Structures</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_different_underlying_dss_1.png" align="middle" alt="Underlying Associative Data Structures" /></div></div></div><br class="figure-break" /><p>

1834

+ </p><div class="figure"><a id="idm269997910864"></a><p class="title"><strong>Figure 22.2. Underlying Associative Data Structures</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_different_underlying_dss_1.png" align="middle" alt="Underlying Associative Data Structures" /></div></div></div><br class="figure-break" /><p>

1835

A shows a collision-chaining hash-table, B shows a probing

1836

hash-table, C shows a red-black tree, D shows a splay tree, E shows

1837

a tree based on an ordered vector(implicit in the order of the

1838

@@ -375,7 +375,7 @@

1839

no guarantee that the elements traversed will coincide with the

1840

<span class="emphasis"><em>logical</em></span> elements between 1 and 5, as in

1841

label B.

1842

- </p><div class="figure"><a id="idp17651648"></a><p class="title"><strong>Figure 22.3. Range Iteration in Different Data Structures</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_point_iterators_range_ops_1.png" align="middle" alt="Node Invariants" /></div></div></div><br class="figure-break" /><p>

1843

+ </p><div class="figure"><a id="idm269997879168"></a><p class="title"><strong>Figure 22.3. Range Iteration in Different Data Structures</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_point_iterators_range_ops_1.png" align="middle" alt="Node Invariants" /></div></div></div><br class="figure-break" /><p>

1844

In our opinion, this problem is not caused just because

1845

red-black trees are order preserving while

1846

collision-chaining hash tables are (generally) not - it

1847

@@ -426,7 +426,7 @@

1848

list, as in the graphic below, label B. Here the iterators are as

1849

light as can be, but the hash-table's operations are more

1850

complicated.

1851

- </p><div class="figure"><a id="idp17666528"></a><p class="title"><strong>Figure 22.4. Point Iteration in Hash Data Structures</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_point_iterators_range_ops_2.png" align="middle" alt="Point Iteration in Hash Data Structures" /></div></div></div><br class="figure-break" /><p>

1852

+ </p><div class="figure"><a id="idm269997864256"></a><p class="title"><strong>Figure 22.4. Point Iteration in Hash Data Structures</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_point_iterators_range_ops_2.png" align="middle" alt="Point Iteration in Hash Data Structures" /></div></div></div><br class="figure-break" /><p>

1853

It should be noted that containers based on collision-chaining

1854

hash-tables are not the only ones with this type of behavior;

1855

many other self-organizing data structures display it as well.

1856

@@ -442,7 +442,7 @@

1857

container. The graphic below shows three cases: A1 and A2 show

1858

a red-black tree; B1 and B2 show a probing hash-table; C1 and C2

1859

show a collision-chaining hash table.

1860

- </p><div class="figure"><a id="idp17675840"></a><p class="title"><strong>Figure 22.5. Effect of erase in different underlying data structures</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_invalidation_guarantee_erase.png" align="middle" alt="Effect of erase in different underlying data structures" /></div></div></div><br class="figure-break" /><div class="orderedlist"><ol class="orderedlist" type="1"><li class="listitem"><p>

1861

+ </p><div class="figure"><a id="idm269997855056"></a><p class="title"><strong>Figure 22.5. Effect of erase in different underlying data structures</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_invalidation_guarantee_erase.png" align="middle" alt="Effect of erase in different underlying data structures" /></div></div></div><br class="figure-break" /><div class="orderedlist"><ol class="orderedlist" type="1"><li class="listitem"><p>

1862

Erasing 5 from A1 yields A2. Clearly, an iterator to 3 can

1863

be de-referenced and incremented. The sequence of iterators

1864

changed, but in a way that is well-defined by the interface.

1865

@@ -678,7 +678,7 @@

1866

typically less structured than an associative container's tree;

1867

the third simply uses an associative container. These are

1868

shown in the figure below with labels A1 and A2, B, and C.

1869

- </p><div class="figure"><a id="idp17743424"></a><p class="title"><strong>Figure 22.6. Underlying Priority Queue Data Structures</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_different_underlying_dss_2.png" align="middle" alt="Underlying Priority Queue Data Structures" /></div></div></div><br class="figure-break" /><p>

1870

+ </p><div class="figure"><a id="idm269997787392"></a><p class="title"><strong>Figure 22.6. Underlying Priority Queue Data Structures</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_different_underlying_dss_2.png" align="middle" alt="Underlying Priority Queue Data Structures" /></div></div></div><br class="figure-break" /><p>

1871

No single implementation can completely replace any of the

1872

others. Some have better <code class="function">push</code>

1873

and <code class="function">pop</code> amortized performance, some have

1874

@@ -1098,7 +1098,7 @@

1875

</span>. </span><span class="publisher"><span class="publishername">

1876

Proceedings of International Conference on Very Large Data Bases

1877

. </span></span></p></div><div class="biblioentry"><a id="biblio.maverik_lowerbounds"></a><p>[biblio.maverik_lowerbounds] <span class="title"><em>

1878

- <a class="link" href="http://magic.aladdin.cs.cmu.edu/2005/08/01/deamortization-part-2-binomial-heaps" target="_top">

1879

+ <a class="link" href="http://magic.aladdin.cs.cmu.edu/2005/08/01/deamortization-part-2-binomial-heaps/" target="_top">

1880

Deamortization - Part 2: Binomial Heaps

1881

</a>

1882

</em>. </span><span class="date">

1883

@@ -1190,7 +1190,7 @@

1884

</span>. </span><span class="publisher"><span class="publishername">

1885

Addison-Wesley Publishing Company

1886

. </span></span></p></div><div class="biblioentry"><a id="biblio.nelson96stlpq"></a><p>[biblio.nelson96stlpq] <span class="title"><em>

1887

- <a class="link" href="http://www.dogma.net/markn/articles/pq_stl/priority.htm" target="_top">Priority Queues and the STL

1888

+ <a class="link" href="http://marknelson.us/1996/01/01/priority-queues/" target="_top">Priority Queues and the STL

1889

</a>

1890

</em>. </span><span class="date">

1891

January 1996

1892

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-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 27. Iterators</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III. Extensions" /><link rel="prev" href="ext_numerics.html" title="Chapter 26. Numerics" /><link rel="next" href="ext_io.html" title="Chapter 28. Input and Output" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 27. Iterators</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_numerics.html">Prev</a> </td><th width="60%" align="center">Part III.

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 27. Iterators</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III. Extensions" /><link rel="prev" href="ext_numerics.html" title="Chapter 26. Numerics" /><link rel="next" href="ext_io.html" title="Chapter 28. Input and Output" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 27. Iterators</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_numerics.html">Prev</a> </td><th width="60%" align="center">Part III.

1900

Extensions

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1902

</th><td width="20%" align="right"> <a accesskey="n" href="ext_io.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.iterators"></a>Chapter 27. Iterators</h2></div></div></div><p>24.3.2 describes <code class="code">struct iterator</code>, which didn't exist in the

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>

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-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Implementation</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, allocator" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="bitmap_allocator.html" title="Chapter 21. The bitmap_allocator" /><link rel="prev" href="bitmap_allocator.html" title="Chapter 21. The bitmap_allocator" /><link rel="next" href="policy_data_structures.html" title="Chapter 22. Policy-Based Data Structures" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Implementation</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="bitmap_allocator.html">Prev</a> </td><th width="60%" align="center">Chapter 21. The bitmap_allocator</th><td width="20%" align="right"> <a accesskey="n" href="policy_data_structures.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="allocator.bitmap.impl"></a>Implementation</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="bitmap.impl.free_list_store"></a>Free List Store</h3></div></div></div><p>

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The Free List Store (referred to as FLS for the remaining part of this

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document) is the Global memory pool that is shared by all instances of

1913

the bitmapped allocator instantiated for any type. This maintains a

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1915

</p><p>

1916

Consider a block of size 64 ints. In memory, it would look like this:

1917

(assume a 32-bit system where, size_t is a 32-bit entity).

1918

- </p><div class="table"><a id="idp17500848"></a><p class="title"><strong>Table 21.1. Bitmap Allocator Memory Map</strong></p><div class="table-contents"><table summary="Bitmap Allocator Memory Map" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left">268</td><td align="left">0</td><td align="left">4294967295</td><td align="left">4294967295</td><td align="left">Data -> Space for 64 ints</td></tr></tbody></table></div></div><br class="table-break" /><p>

1919

+ </p><div class="table"><a id="idm269998030352"></a><p class="title"><strong>Table 21.1. Bitmap Allocator Memory Map</strong></p><div class="table-contents"><table summary="Bitmap Allocator Memory Map" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left">268</td><td align="left">0</td><td align="left">4294967295</td><td align="left">4294967295</td><td align="left">Data -> Space for 64 ints</td></tr></tbody></table></div></div><br class="table-break" /><p>

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The first Column(268) represents the size of the Block in bytes as

1921

seen by the Bitmap Allocator. Internally, a global free list is

1922

used to keep track of the free blocks used and given back by the

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Appendix A. Contributing</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix.html" title="Part IV. Appendices" /><link rel="prev" href="appendix.html" title="Part IV. Appendices" /><link rel="next" href="source_organization.html" title="Directory Layout and Source Conventions" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Appendix A.

1931

Contributing

1932

1933

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Appendices

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</th><td width="20%" align="right"> <a accesskey="n" href="source_organization.html">Next</a></td></tr></table><hr /></div><div class="appendix"><div class="titlepage"><div><div><h1 class="title"><a id="appendix.contrib"></a>

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Contributing

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-</h1></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="appendix_contributing.html#contrib.list">Contributor Checklist</a></span></dt><dd><dl><dt><span class="section"><a href="appendix_contributing.html#list.reading">Reading</a></span></dt><dt><span class="section"><a href="appendix_contributing.html#list.copyright">Assignment</a></span></dt><dt><span class="section"><a href="appendix_contributing.html#list.getting">Getting Sources</a></span></dt><dt><span class="section"><a href="appendix_contributing.html#list.patches">Submitting Patches</a></span></dt></dl></dd><dt><span class="section"><a href="source_organization.html">Directory Layout and Source Conventions</a></span></dt><dt><span class="section"><a href="source_code_style.html">Coding Style</a></span></dt><dd><dl><dt><span class="section"><a href="source_code_style.html#coding_style.bad_identifiers">Bad Identifiers</a></span></dt><dt><span class="section"><a href="source_code_style.html#coding_style.example">By Example</a></span></dt></dl></dd><dt><span class="section"><a href="source_design_notes.html">Design Notes</a></span></dt></dl></div><p>

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+ <a id="idm269993657472" class="indexterm"></a>

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+</h1></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="appendix_contributing.html#contrib.list">Contributor Checklist</a></span></dt><dd><dl><dt><span class="section"><a href="appendix_contributing.html#list.reading">Reading</a></span></dt><dt><span class="section"><a href="appendix_contributing.html#list.copyright">Assignment</a></span></dt><dt><span class="section"><a href="appendix_contributing.html#list.getting">Getting Sources</a></span></dt><dt><span class="section"><a href="appendix_contributing.html#list.patches">Submitting Patches</a></span></dt></dl></dd><dt><span class="section"><a href="source_organization.html">Directory Layout and Source Conventions</a></span></dt><dt><span class="section"><a href="source_code_style.html">Coding Style</a></span></dt><dd><dl><dt><span class="section"><a href="source_code_style.html#coding_style.bad_identifiers">Bad Identifiers</a></span></dt><dt><span class="section"><a href="source_code_style.html#coding_style.example">By Example</a></span></dt></dl></dd><dt><span class="section"><a href="source_design_notes.html">Design Notes</a></span></dt></dl></div><p>

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The GNU C++ Library follows an open development model. Active

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contributors are assigned maintainer-ship responsibility, and given

1944

write access to the source repository. First time contributors

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@@ -36,7 +36,7 @@

1946

for this group is quite useful.

1947

</p></li><li class="listitem"><p>

1948

Peruse

1949

- the <a class="link" href="http://www.gnu.org/prep/standards" target="_top">GNU

1950

+ the <a class="link" href="http://www.gnu.org/prep/standards/" target="_top">GNU

1951

Coding Standards</a>, and chuckle when you hit the part

1952

about <span class="quote">“<span class="quote">Using Languages Other Than C</span>”</span>.

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</p></li><li class="listitem"><p>

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Testing</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, parallel" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="parallel_mode.html" title="Chapter 18. Parallel Mode" /><link rel="prev" href="parallel_mode_design.html" title="Design" /><link rel="next" href="profile_mode.html" title="Chapter 19. Profile Mode" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Testing</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="parallel_mode_design.html">Prev</a> </td><th width="60%" align="center">Chapter 18. Parallel Mode</th><td width="20%" align="right"> <a accesskey="n" href="profile_mode.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.parallel_mode.test"></a>Testing</h2></div></div></div><p>

1962

Both the normal conformance and regression tests and the

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supplemental performance tests work.

1964

</p><p>

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 19. Profile Mode</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III. Extensions" /><link rel="prev" href="parallel_mode_test.html" title="Testing" /><link rel="next" href="profile_mode_design.html" title="Design" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 19. Profile Mode</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="parallel_mode_test.html">Prev</a> </td><th width="60%" align="center">Part III.

1973

Extensions

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1975

-</th><td width="20%" align="right"> <a accesskey="n" href="profile_mode_design.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.profile_mode"></a>Chapter 19. Profile Mode</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="profile_mode.html#manual.ext.profile_mode.intro">Intro</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode.html#manual.ext.profile_mode.using">Using the Profile Mode</a></span></dt><dt><span class="section"><a href="profile_mode.html#manual.ext.profile_mode.tuning">Tuning the Profile Mode</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_design.html">Design</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.wrapper">Wrapper Model</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.instrumentation">Instrumentation</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.rtlib">Run Time Behavior</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.analysis">Analysis and Diagnostics</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.cost-model">Cost Model</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.reports">Reports</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.testing">Testing</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_api.html">Extensions for Custom Containers</a></span></dt><dt><span class="section"><a href="profile_mode_cost_model.html">Empirical Cost Model</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html">Implementation Issues</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.stack">Stack Traces</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.symbols">Symbolization of Instruction Addresses</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.concurrency">Concurrency</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.stdlib-in-proflib">Using the Standard Library in the Instrumentation Implementation</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.malloc-hooks">Malloc Hooks</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.construction-destruction">Construction and Destruction of Global Objects</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_devel.html">Developer Information</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_devel.html#manual.ext.profile_mode.developer.bigpic">Big Picture</a></span></dt><dt><span class="section"><a href="profile_mode_devel.html#manual.ext.profile_mode.developer.howto">How To Add A Diagnostic</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html">Diagnostics</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.template">Diagnostic Template</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.containers">Containers</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.hashtable_too_small">Hashtable Too Small</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.hashtable_too_large">Hashtable Too Large</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.inefficient_hash">Inefficient Hash</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.vector_too_small">Vector Too Small</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.vector_too_large">Vector Too Large</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.vector_to_hashtable">Vector to Hashtable</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.hashtable_to_vector">Hashtable to Vector</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.vector_to_list">Vector to List</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.list_to_vector">List to Vector</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.list_to_slist">List to Forward List (Slist)</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.assoc_ord_to_unord">Ordered to Unordered Associative Container</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.algorithms">Algorithms</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.algorithms.sort">Sort Algorithm Performance</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.locality">Data Locality</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.locality.sw_prefetch">Need Software Prefetch</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.locality.linked">Linked Structure Locality</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.mthread">Multithreaded Data Access</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.mthread.ddtest">Data Dependence Violations at Container Level</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.mthread.false_share">False Sharing</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.statistics">Statistics</a></span></dt></dl></dd><dt><span class="bibliography"><a href="profile_mode.html#profile_mode.biblio">Bibliography</a></span></dt></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.intro"></a>Intro</h2></div></div></div><p>

1976

+</th><td width="20%" align="right"> <a accesskey="n" href="profile_mode_design.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.profile_mode"></a>Chapter 19. Profile Mode</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="profile_mode.html#manual.ext.profile_mode.intro">Intro</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode.html#manual.ext.profile_mode.using">Using the Profile Mode</a></span></dt><dt><span class="section"><a href="profile_mode.html#manual.ext.profile_mode.tuning">Tuning the Profile Mode</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_design.html">Design</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.wrapper">Wrapper Model</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.instrumentation">Instrumentation</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.rtlib">Run Time Behavior</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.analysis">Analysis and Diagnostics</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.cost-model">Cost Model</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.reports">Reports</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.testing">Testing</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_api.html">Extensions for Custom Containers</a></span></dt><dt><span class="section"><a href="profile_mode_cost_model.html">Empirical Cost Model</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html">Implementation Issues</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.stack">Stack Traces</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.symbols">Symbolization of Instruction Addresses</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.concurrency">Concurrency</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.stdlib-in-proflib">Using the Standard Library in the Instrumentation Implementation</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.malloc-hooks">Malloc Hooks</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.construction-destruction">Construction and Destruction of Global Objects</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_devel.html">Developer Information</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_devel.html#manual.ext.profile_mode.developer.bigpic">Big Picture</a></span></dt><dt><span class="section"><a href="profile_mode_devel.html#manual.ext.profile_mode.developer.howto">How To Add A Diagnostic</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html">Diagnostics</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.template">Diagnostic Template</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.containers">Containers</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.hashtable_too_small">Hashtable Too Small</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.hashtable_too_large">Hashtable Too Large</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.inefficient_hash">Inefficient Hash</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.vector_too_small">Vector Too Small</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.vector_too_large">Vector Too Large</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.vector_to_hashtable">Vector to Hashtable</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.hashtable_to_vector">Hashtable to Vector</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.vector_to_list">Vector to List</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.list_to_vector">List to Vector</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.list_to_slist">List to Forward List (Slist)</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.assoc_ord_to_unord">Ordered to Unordered Associative Container</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.algorithms">Algorithms</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.algorithms.sort">Sort Algorithm Performance</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.locality">Data Locality</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.locality.sw_prefetch">Need Software Prefetch</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.locality.linked">Linked Structure Locality</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.mthread">Multithreaded Data Access</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.mthread.ddtest">Data Dependence Violations at Container Level</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.mthread.false_share">False Sharing</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.statistics">Statistics</a></span></dt></dl></dd><dt><span class="bibliography"><a href="profile_mode.html#profile_mode.biblio">Bibliography</a></span></dt></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.intro"></a>Intro</h2></div></div></div><p>

1977

<span class="emphasis"><em>Goal: </em></span>Give performance improvement advice based on

1978

recognition of suboptimal usage patterns of the standard library.

1979

</p><p>

1980

@@ -137,7 +137,7 @@

1981

call context.

1982

(Environment variable not supported.)

1983

</p></li></ul></div><p>

1984

- </p></div></div><div class="bibliography"><div class="titlepage"><div><div><h2 class="title"><a id="profile_mode.biblio"></a>Bibliography</h2></div></div></div><div class="biblioentry"><a id="idp17395456"></a><p><span class="citetitle"><em class="citetitle">

1985

+ </p></div></div><div class="bibliography"><div class="titlepage"><div><div><h2 class="title"><a id="profile_mode.biblio"></a>Bibliography</h2></div></div></div><div class="biblioentry"><a id="idm269998135936"></a><p><span class="citetitle"><em class="citetitle">

1986

Perflint: A Context Sensitive Performance Advisor for C++ Programs

1987

</em>. </span><span class="author"><span class="firstname">Lixia</span> <span class="surname">Liu</span>. </span><span class="author"><span class="firstname">Silvius</span> <span class="surname">Rus</span>. </span><span class="copyright">Copyright © 2009 . </span><span class="publisher"><span class="publishername">

1988

Proceedings of the 2009 International Symposium on Code Generation

1989

Index: libstdc++-v3/doc/html/manual/stringstreams.html

1990

===================================================================

1991

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1994

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

1995

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Memory Based Streams</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="io.html" title="Chapter 13. Input and Output" /><link rel="prev" href="streambufs.html" title="Stream Buffers" /><link rel="next" href="fstreams.html" title="File Based Streams" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Memory Based Streams</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="streambufs.html">Prev</a> </td><th width="60%" align="center">Chapter 13.

1996

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Memory Based Streams</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="io.html" title="Chapter 13. Input and Output" /><link rel="prev" href="streambufs.html" title="Stream Buffers" /><link rel="next" href="fstreams.html" title="File Based Streams" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Memory Based Streams</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="streambufs.html">Prev</a> </td><th width="60%" align="center">Chapter 13.

1997

Input and Output

1998

1999

</th><td width="20%" align="right"> <a accesskey="n" href="fstreams.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.io.memstreams"></a>Memory Based Streams</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="std.io.memstreams.compat"></a>Compatibility With strstream</h3></div></div></div><p>

2000

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2001

===================================================================

2002

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>

2006

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Traits</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="utilities.html" title="Chapter 6. Utilities" /><link rel="prev" href="memory.html" title="Memory" /><link rel="next" href="strings.html" title="Chapter 7. Strings" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Traits</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="memory.html">Prev</a> </td><th width="60%" align="center">Chapter 6.

2007

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Traits</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="utilities.html" title="Chapter 6. Utilities" /><link rel="prev" href="memory.html" title="Memory" /><link rel="next" href="strings.html" title="Chapter 7. Strings" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Traits</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="memory.html">Prev</a> </td><th width="60%" align="center">Chapter 6.

2008

Utilities

2009

2010

</th><td width="20%" align="right"> <a accesskey="n" href="strings.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.util.traits"></a>Traits</h2></div></div></div><p>

2011

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2012

===================================================================

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2014

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2015

@@ -1,10 +1,9 @@

2016

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

2017

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Acknowledgments</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, policy, container, data, structure, associated, tree, trie, hash, metaprogramming" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="policy_data_structures.html" title="Chapter 22. Policy-Based Data Structures" /><link rel="prev" href="policy_based_data_structures_test.html" title="Testing" /><link rel="next" href="ext_containers.html" title="Chapter 23. HP/SGI Extensions" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Acknowledgments</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="policy_based_data_structures_test.html">Prev</a> </td><th width="60%" align="center">Chapter 22. Policy-Based Data Structures</th><td width="20%" align="right"> <a accesskey="n" href="ext_containers.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="pbds.ack"></a>Acknowledgments</h2></div></div></div><p>

2018

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Acknowledgments</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, policy, container, data, structure, associated, tree, trie, hash, metaprogramming" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="policy_data_structures.html" title="Chapter 22. Policy-Based Data Structures" /><link rel="prev" href="policy_based_data_structures_test.html" title="Testing" /><link rel="next" href="ext_containers.html" title="Chapter 23. HP/SGI Extensions" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Acknowledgments</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="policy_based_data_structures_test.html">Prev</a> </td><th width="60%" align="center">Chapter 22. Policy-Based Data Structures</th><td width="20%" align="right"> <a accesskey="n" href="ext_containers.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="pbds.ack"></a>Acknowledgments</h2></div></div></div><p>

2019

Written by Ami Tavory and Vladimir Dreizin (IBM Haifa Research

2020

Laboratories), and Benjamin Kosnik (Red Hat).

2021

</p><p>

2022

- This library was partially written at

2023

- <a class="link" href="http://www.haifa.il.ibm.com/" target="_top">IBM's Haifa Research Labs</a>.

2024

+ This library was partially written at IBM's Haifa Research Labs.

2025

It is based heavily on policy-based design and uses many useful

2026

techniques from Modern C++ Design: Generic Programming and Design

2027

Patterns Applied by Andrei Alexandrescu.

2028

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2030

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2033

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

2034

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Associative</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="containers.html" title="Chapter 9. Containers" /><link rel="prev" href="containers.html" title="Chapter 9. Containers" /><link rel="next" href="unordered_associative.html" title="Unordered Associative" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Associative</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="containers.html">Prev</a> </td><th width="60%" align="center">Chapter 9.

2035

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Associative</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="containers.html" title="Chapter 9. Containers" /><link rel="prev" href="containers.html" title="Chapter 9. Containers" /><link rel="next" href="unordered_associative.html" title="Unordered Associative" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Associative</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="containers.html">Prev</a> </td><th width="60%" align="center">Chapter 9.

2036

Containers

2037

2038

</th><td width="20%" align="right"> <a accesskey="n" href="unordered_associative.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.containers.associative"></a>Associative</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="containers.associative.insert_hints"></a>Insertion Hints</h3></div></div></div><p>

2039

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Extensions

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contains all the higher-level

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the concurrence layer consists largely of types. All types are defined within <code class="code">namespace __gnu_cxx</code>.

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Support

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Standard Contents

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This part deals with the functions called and objects created

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Extensions

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+</th><td width="20%" align="right"> <a accesskey="n" href="bitmap_allocator_impl.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.allocator.bitmap"></a>Chapter 21. The bitmap_allocator</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="bitmap_allocator.html#allocator.bitmap.design">Design</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.free_list_store">Free List Store</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.super_block">Super Block</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.super_block_data">Super Block Data Layout</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.max_wasted">Maximum Wasted Percentage</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.allocate"><code class="function">allocate</code></a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.deallocate"><code class="function">deallocate</code></a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.questions">Questions</a></span></dt><dd><dl><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.question.1">1</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.question.2">2</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.question.3">3</a></span></dt></dl></dd><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.locality">Locality</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.grow_policy">Overhead and Grow Policy</a></span></dt></dl></dd></dl></div><p>

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</p><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="allocator.bitmap.design"></a>Design</h2></div></div></div><p>

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As this name suggests, this allocator uses a bit-map to keep track

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and one for the documentation.

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Numerics

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Standard Contents

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+</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="numerics.html#std.numerics.complex">Complex</a></span></dt><dd><dl><dt><span class="section"><a href="numerics.html#numerics.complex.processing">complex Processing</a></span></dt></dl></dd><dt><span class="section"><a href="generalized_numeric_operations.html">Generalized Operations</a></span></dt><dt><span class="section"><a href="numerics_and_c.html">Interacting with C</a></span></dt><dd><dl><dt><span class="section"><a href="numerics_and_c.html#numerics.c.array">Numerics vs. Arrays</a></span></dt><dt><span class="section"><a href="numerics_and_c.html#numerics.c.c99">C99</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.numerics.complex"></a>Complex</h2></div></div></div><p>

2121

</p><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="numerics.complex.processing"></a>complex Processing</h3></div></div></div><p>

2122

</p><p>Using <code class="code">complex<></code> becomes even more comple- er, sorry,

2123

<span class="emphasis"><em>complicated</em></span>, with the not-quite-gratuitously-incompatible

2124

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2125

===================================================================

2126

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2127

+++ b/src/libstdc++-v3/doc/html/manual/using_exceptions.html (.../branches/gcc-4_8-branch)

2128

@@ -1,5 +1,5 @@

2129

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

2130

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Exceptions</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="C++, exception, error, exception neutrality, exception safety, exception propagation, -fno-exceptions" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_concurrency.html" title="Concurrency" /><link rel="next" href="debug.html" title="Debugging Support" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Exceptions</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_concurrency.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="debug.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.exceptions"></a>Exceptions</h2></div></div></div><p>

2131

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Exceptions</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, exception, error, exception neutrality, exception safety, exception propagation, -fno-exceptions" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_concurrency.html" title="Concurrency" /><link rel="next" href="debug.html" title="Debugging Support" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Exceptions</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_concurrency.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="debug.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.exceptions"></a>Exceptions</h2></div></div></div><p>

2132

The C++ language provides language support for stack unwinding

2133

with <code class="literal">try</code> and <code class="literal">catch</code> blocks and

2134

the <code class="literal">throw</code> keyword.

2135

@@ -265,7 +265,7 @@

2136

}

2137

catch(...)

2138

{ this->_M_setstate(ios_base::badbit); }

2139

-</pre></div></div><div class="bibliography"><div class="titlepage"><div><div><h3 class="title"><a id="using.exceptions.biblio"></a>Bibliography</h3></div></div></div><div class="biblioentry"><a id="idp13644000"></a><p><span class="title"><em>

2140

+</pre></div></div><div class="bibliography"><div class="titlepage"><div><div><h3 class="title"><a id="using.exceptions.biblio"></a>Bibliography</h3></div></div></div><div class="biblioentry"><a id="idm270001889024"></a><p><span class="title"><em>

2141

2142

System Interface Definitions, Issue 7 (IEEE Std. 1003.1-2008)

2143

</a>

2144

@@ -274,39 +274,39 @@

2145

2146

The Open Group/The Institute of Electrical and Electronics

2147

Engineers, Inc.

2148

- . </span></p></div><div class="biblioentry"><a id="idp13647696"></a><p><span class="title"><em>

2149

+ . </span></p></div><div class="biblioentry"><a id="idm270001885328"></a><p><span class="title"><em>

2150

2151

Error and Exception Handling

2152

</a>

2153

</em>. </span><span class="author"><span class="firstname">David</span> <span class="surname">Abrahams </span>. </span><span class="publisher"><span class="publishername">

2154

Boost

2155

- . </span></span></p></div><div class="biblioentry"><a id="idp13651392"></a><p><span class="title"><em>

2156

+ . </span></span></p></div><div class="biblioentry"><a id="idm270001881632"></a><p><span class="title"><em>

2157

2158

Exception-Safety in Generic Components

2159

</a>

2160

</em>. </span><span class="author"><span class="firstname">David</span> <span class="surname">Abrahams</span>. </span><span class="publisher"><span class="publishername">

2161

Boost

2162

- . </span></span></p></div><div class="biblioentry"><a id="idp13655104"></a><p><span class="title"><em>

2163

+ . </span></span></p></div><div class="biblioentry"><a id="idm270001877920"></a><p><span class="title"><em>

2164

2165

Standard Library Exception Policy

2166

</a>

2167

</em>. </span><span class="author"><span class="firstname">Matt</span> <span class="surname">Austern</span>. </span><span class="publisher"><span class="publishername">

2168

WG21 N1077

2169

- . </span></span></p></div><div class="biblioentry"><a id="idp13658816"></a><p><span class="title"><em>

2170

+ . </span></span></p></div><div class="biblioentry"><a id="idm270001874208"></a><p><span class="title"><em>

2171

2172

ia64 c++ abi exception handling

2173

</a>

2174

</em>. </span><span class="author"><span class="firstname">Richard</span> <span class="surname">Henderson</span>. </span><span class="publisher"><span class="publishername">

2175

GNU

2176

- . </span></span></p></div><div class="biblioentry"><a id="idp13662512"></a><p><span class="title"><em>

2177

+ . </span></span></p></div><div class="biblioentry"><a id="idm270001870512"></a><p><span class="title"><em>

2178

2179

Appendix E: Standard-Library Exception Safety

2180

</a>

2181

- </em>. </span><span class="author"><span class="firstname">Bjarne</span> <span class="surname">Stroustrup</span>. </span></p></div><div class="biblioentry"><a id="idp13665328"></a><p><span class="citetitle"><em class="citetitle">

2182

+ </em>. </span><span class="author"><span class="firstname">Bjarne</span> <span class="surname">Stroustrup</span>. </span></p></div><div class="biblioentry"><a id="idm270001867696"></a><p><span class="citetitle"><em class="citetitle">

2183

Exceptional C++

2184

</em>. </span><span class="pagenums">

2185

Exception-Safety Issues and Techniques

2186

- . </span><span class="author"><span class="firstname">Herb</span> <span class="surname">Sutter</span>. </span></p></div><div class="biblioentry"><a id="idp13667712"></a><p><span class="title"><em>

2187

+ . </span><span class="author"><span class="firstname">Herb</span> <span class="surname">Sutter</span>. </span></p></div><div class="biblioentry"><a id="idm270001865312"></a><p><span class="title"><em>

2188

2189

GCC Bug 25191: exception_defines.h #defines try/catch

2190

</a>

2191

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2192

===================================================================

2193

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2194

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2195

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2196

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

2197

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Testing</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, policy, container, data, structure, associated, tree, trie, hash, metaprogramming" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="policy_data_structures.html" title="Chapter 22. Policy-Based Data Structures" /><link rel="prev" href="policy_data_structures_design.html" title="Design" /><link rel="next" href="policy_data_structures_ack.html" title="Acknowledgments" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Testing</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="policy_data_structures_design.html">Prev</a> </td><th width="60%" align="center">Chapter 22. Policy-Based Data Structures</th><td width="20%" align="right"> <a accesskey="n" href="policy_data_structures_ack.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="pbds.test"></a>Testing</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="pbds.test.regression"></a>Regression</h3></div></div></div><p>The library contains a single comprehensive regression test.

2198

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Testing</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, policy, container, data, structure, associated, tree, trie, hash, metaprogramming" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="policy_data_structures.html" title="Chapter 22. Policy-Based Data Structures" /><link rel="prev" href="policy_data_structures_design.html" title="Design" /><link rel="next" href="policy_data_structures_ack.html" title="Acknowledgments" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Testing</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="policy_data_structures_design.html">Prev</a> </td><th width="60%" align="center">Chapter 22. Policy-Based Data Structures</th><td width="20%" align="right"> <a accesskey="n" href="policy_data_structures_ack.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="pbds.test"></a>Testing</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="pbds.test.regression"></a>Regression</h3></div></div></div><p>The library contains a single comprehensive regression test.

2199

For a given container type in this library, the test creates

2200

an object of the container type and an object of the

2201

corresponding standard type (e.g., <code class="classname">std::set</code>). It

2202

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2203

===================================================================

2204

--- a/src/libstdc++-v3/doc/html/manual/parallel_mode_design.html (.../tags/gcc_4_8_2_release)

2205

+++ b/src/libstdc++-v3/doc/html/manual/parallel_mode_design.html (.../branches/gcc-4_8-branch)

2206

@@ -1,5 +1,5 @@

2207

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

2208

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="C++, library, parallel" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="parallel_mode.html" title="Chapter 18. Parallel Mode" /><link rel="prev" href="parallel_mode_using.html" title="Using" /><link rel="next" href="parallel_mode_test.html" title="Testing" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="parallel_mode_using.html">Prev</a> </td><th width="60%" align="center">Chapter 18. Parallel Mode</th><td width="20%" align="right"> <a accesskey="n" href="parallel_mode_test.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.parallel_mode.design"></a>Design</h2></div></div></div><p>

2209

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, parallel" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="parallel_mode.html" title="Chapter 18. Parallel Mode" /><link rel="prev" href="parallel_mode_using.html" title="Using" /><link rel="next" href="parallel_mode_test.html" title="Testing" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="parallel_mode_using.html">Prev</a> </td><th width="60%" align="center">Chapter 18. Parallel Mode</th><td width="20%" align="right"> <a accesskey="n" href="parallel_mode_test.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.parallel_mode.design"></a>Design</h2></div></div></div><p>

2210

</p><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="parallel_mode.design.intro"></a>Interface Basics</h3></div></div></div><p>

2211

All parallel algorithms are intended to have signatures that are

2212

equivalent to the ISO C++ algorithms replaced. For instance, the

2213

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2214

===================================================================

2215

--- a/src/libstdc++-v3/doc/html/manual/abi.html (.../tags/gcc_4_8_2_release)

2216

+++ b/src/libstdc++-v3/doc/html/manual/abi.html (.../branches/gcc-4_8-branch)

2217

@@ -1,5 +1,5 @@

2218

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

2219

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>ABI Policy and Guidelines</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="C++, ABI, version, dynamic, shared, compatibility" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B. Porting and Maintenance" /><link rel="prev" href="test.html" title="Test" /><link rel="next" href="api.html" title="API Evolution and Deprecation History" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">ABI Policy and Guidelines</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="test.html">Prev</a> </td><th width="60%" align="center">Appendix B.

2220

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>ABI Policy and Guidelines</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, ABI, version, dynamic, shared, compatibility" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B. Porting and Maintenance" /><link rel="prev" href="test.html" title="Test" /><link rel="next" href="api.html" title="API Evolution and Deprecation History" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">ABI Policy and Guidelines</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="test.html">Prev</a> </td><th width="60%" align="center">Appendix B.

2221

Porting and Maintenance

2222

2223

</th><td width="20%" align="right"> <a accesskey="n" href="api.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="appendix.porting.abi"></a>ABI Policy and Guidelines</h2></div></div></div><p>

2224

@@ -493,39 +493,39 @@

2225

2226

C++ ABI Summary

2227

</a>

2228

- </em>. </span></p></div><div class="biblioentry"><a id="idp22945936"></a><p><span class="title"><em>

2229

+ </em>. </span></p></div><div class="biblioentry"><a id="idm269992586624"></a><p><span class="title"><em>

2230

2231

Intel Compilers for Linux Compatibility with the GNU Compilers

2232

</a>

2233

- </em>. </span></p></div><div class="biblioentry"><a id="idp22947792"></a><p><span class="title"><em>

2234

+ </em>. </span></p></div><div class="biblioentry"><a id="idm269992584768"></a><p><span class="title"><em>

2235

2236

Linker and Libraries Guide (document 819-0690)

2237

</a>

2238

- </em>. </span></p></div><div class="biblioentry"><a id="idp22949632"></a><p><span class="title"><em>

2239

+ </em>. </span></p></div><div class="biblioentry"><a id="idm269992582928"></a><p><span class="title"><em>

2240

2241

Sun Studio 11: C++ Migration Guide (document 819-3689)

2242

</a>

2243

- </em>. </span></p></div><div class="biblioentry"><a id="idp22951488"></a><p><span class="title"><em>

2244

+ </em>. </span></p></div><div class="biblioentry"><a id="idm269992581072"></a><p><span class="title"><em>

2245

2246

How to Write Shared Libraries

2247

</a>

2248

- </em>. </span><span class="author"><span class="firstname">Ulrich</span> <span class="surname">Drepper</span>. </span></p></div><div class="biblioentry"><a id="idp22954928"></a><p><span class="title"><em>

2249

+ </em>. </span><span class="author"><span class="firstname">Ulrich</span> <span class="surname">Drepper</span>. </span></p></div><div class="biblioentry"><a id="idm269992577632"></a><p><span class="title"><em>

2250

2251

C++ ABI for the ARM Architecture

2252

</a>

2253

- </em>. </span></p></div><div class="biblioentry"><a id="idp22956736"></a><p><span class="title"><em>

2254

+ </em>. </span></p></div><div class="biblioentry"><a id="idm269992575824"></a><p><span class="title"><em>

2255

2256

Dynamic Shared Objects: Survey and Issues

2257

</a>

2258

</em>. </span><span class="subtitle">

2259

ISO C++ J16/06-0046

2260

- . </span><span class="author"><span class="firstname">Benjamin</span> <span class="surname">Kosnik</span>. </span></p></div><div class="biblioentry"><a id="idp22960032"></a><p><span class="title"><em>

2261

+ . </span><span class="author"><span class="firstname">Benjamin</span> <span class="surname">Kosnik</span>. </span></p></div><div class="biblioentry"><a id="idm269992572528"></a><p><span class="title"><em>

2262

2263

Versioning With Namespaces

2264

</a>

2265

</em>. </span><span class="subtitle">

2266

ISO C++ J16/06-0083

2267

- . </span><span class="author"><span class="firstname">Benjamin</span> <span class="surname">Kosnik</span>. </span></p></div><div class="biblioentry"><a id="idp22963312"></a><p><span class="title"><em>

2268

+ . </span><span class="author"><span class="firstname">Benjamin</span> <span class="surname">Kosnik</span>. </span></p></div><div class="biblioentry"><a id="idm269992569248"></a><p><span class="title"><em>

2269

2270

Binary Compatibility of Shared Libraries Implemented in C++

2271

on GNU/Linux Systems

2272

Index: libstdc++-v3/doc/html/manual/intro.html

2273

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2274

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2275

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2276

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2277

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

2278

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-</h1></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="chapter"><a href="status.html">1. Status</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#manual.intro.status.iso">Implementation Status</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#status.iso.1998">C++ 1998/2003</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.1998.status">Implementation Status</a></span></dt><dt><span class="section"><a href="status.html#iso.1998.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.2011">C++ 2011</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.2011.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.tr1">C++ TR1</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.tr1.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.tr24733">C++ TR 24733</a></span></dt></dl></dd><dt><span class="section"><a href="license.html">License</a></span></dt><dd><dl><dt><span class="section"><a href="license.html#manual.intro.status.license.gpl">The Code: GPL</a></span></dt><dt><span class="section"><a href="license.html#manual.intro.status.license.fdl">The Documentation: GPL, FDL</a></span></dt></dl></dd><dt><span class="section"><a href="bugs.html">Bugs</a></span></dt><dd><dl><dt><span class="section"><a href="bugs.html#manual.intro.status.bugs.impl">Implementation Bugs</a></span></dt><dt><span class="section"><a href="bugs.html#manual.intro.status.bugs.iso">Standard Bugs</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="setup.html">2. Setup</a></span></dt><dd><dl><dt><span class="section"><a href="setup.html#manual.intro.setup.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="configure.html">Configure</a></span></dt><dt><span class="section"><a href="make.html">Make</a></span></dt></dl></dd><dt><span class="chapter"><a href="using.html">3. Using</a></span></dt><dd><dl><dt><span class="section"><a href="using.html#manual.intro.using.flags">Command Options</a></span></dt><dt><span class="section"><a href="using_headers.html">Headers</a></span></dt><dd><dl><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.all">Header Files</a></span></dt><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.mixing">Mixing Headers</a></span></dt><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.cheaders">The C Headers and <code class="code">namespace std</code></a></span></dt><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.pre">Precompiled Headers</a></span></dt></dl></dd><dt><span class="section"><a href="using_macros.html">Macros</a></span></dt><dt><span class="section"><a href="using_namespaces.html">Namespaces</a></span></dt><dd><dl><dt><span class="section"><a href="using_namespaces.html#manual.intro.using.namespaces.all">Available Namespaces</a></span></dt><dt><span class="section"><a href="using_namespaces.html#manual.intro.using.namespaces.std">namespace std</a></span></dt><dt><span class="section"><a href="using_namespaces.html#manual.intro.using.namespaces.comp">Using Namespace Composition</a></span></dt></dl></dd><dt><span class="section"><a href="using_dynamic_or_shared.html">Linking</a></span></dt><dd><dl><dt><span class="section"><a href="using_dynamic_or_shared.html#manual.intro.using.linkage.freestanding">Almost Nothing</a></span></dt><dt><span class="section"><a href="using_dynamic_or_shared.html#manual.intro.using.linkage.dynamic">Finding Dynamic or Shared Libraries</a></span></dt></dl></dd><dt><span class="section"><a href="using_concurrency.html">Concurrency</a></span></dt><dd><dl><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.thread_safety">Thread Safety</a></span></dt><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.atomics">Atomics</a></span></dt><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.io">IO</a></span></dt><dd><dl><dt><span class="section"><a href="using_concurrency.html#concurrency.io.structure">Structure</a></span></dt><dt><span class="section"><a href="using_concurrency.html#concurrency.io.defaults">Defaults</a></span></dt><dt><span class="section"><a href="using_concurrency.html#concurrency.io.future">Future</a></span></dt><dt><span class="section"><a href="using_concurrency.html#concurrency.io.alt">Alternatives</a></span></dt></dl></dd><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.containers">Containers</a></span></dt></dl></dd><dt><span class="section"><a href="using_exceptions.html">Exceptions</a></span></dt><dd><dl><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.safety">Exception Safety</a></span></dt><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.propagating">Exception Neutrality</a></span></dt><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.no">Doing without</a></span></dt><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.compat">Compatibility</a></span></dt><dd><dl><dt><span class="section"><a href="using_exceptions.html#using.exception.compat.c">With <code class="literal">C</code></a></span></dt><dt><span class="section"><a href="using_exceptions.html#using.exception.compat.posix">With <code class="literal">POSIX</code> thread cancellation</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="debug.html">Debugging Support</a></span></dt><dd><dl><dt><span class="section"><a href="debug.html#debug.compiler">Using <span class="command"><strong>g++</strong></span></a></span></dt><dt><span class="section"><a href="debug.html#debug.req">Debug Versions of Library Binary Files</a></span></dt><dt><span class="section"><a href="debug.html#debug.memory">Memory Leak Hunting</a></span></dt><dt><span class="section"><a href="debug.html#debug.races">Data Race Hunting</a></span></dt><dt><span class="section"><a href="debug.html#debug.gdb">Using <span class="command"><strong>gdb</strong></span></a></span></dt><dt><span class="section"><a href="debug.html#debug.exceptions">Tracking uncaught exceptions</a></span></dt><dt><span class="section"><a href="debug.html#debug.debug_mode">Debug Mode</a></span></dt><dt><span class="section"><a href="debug.html#debug.compile_time_checks">Compile Time Checking</a></span></dt><dt><span class="section"><a href="debug.html#debug.profile_mode">Profile-based Performance Analysis</a></span></dt></dl></dd></dl></dd></dl></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="index.html">Prev</a> </td><td width="20%" align="center"><a accesskey="u" href="index.html">Up</a></td><td width="40%" align="right"> <a accesskey="n" href="status.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">The GNU C++ Library Manual </td><td width="20%" align="center"><a accesskey="h" href="../index.html">Home</a></td><td width="40%" align="right" valign="top"> Chapter 1. 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Status</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#manual.intro.status.iso">Implementation Status</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#status.iso.1998">C++ 1998/2003</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.1998.status">Implementation Status</a></span></dt><dt><span class="section"><a href="status.html#iso.1998.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.2011">C++ 2011</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.2011.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.tr1">C++ TR1</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.tr1.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.tr24733">C++ TR 24733</a></span></dt></dl></dd><dt><span class="section"><a href="license.html">License</a></span></dt><dd><dl><dt><span class="section"><a href="license.html#manual.intro.status.license.gpl">The Code: GPL</a></span></dt><dt><span class="section"><a href="license.html#manual.intro.status.license.fdl">The Documentation: GPL, FDL</a></span></dt></dl></dd><dt><span class="section"><a href="bugs.html">Bugs</a></span></dt><dd><dl><dt><span class="section"><a href="bugs.html#manual.intro.status.bugs.impl">Implementation Bugs</a></span></dt><dt><span class="section"><a href="bugs.html#manual.intro.status.bugs.iso">Standard Bugs</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="setup.html">2. Setup</a></span></dt><dd><dl><dt><span class="section"><a href="setup.html#manual.intro.setup.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="configure.html">Configure</a></span></dt><dt><span class="section"><a href="make.html">Make</a></span></dt></dl></dd><dt><span class="chapter"><a href="using.html">3. Using</a></span></dt><dd><dl><dt><span class="section"><a href="using.html#manual.intro.using.flags">Command Options</a></span></dt><dt><span class="section"><a href="using_headers.html">Headers</a></span></dt><dd><dl><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.all">Header Files</a></span></dt><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.mixing">Mixing Headers</a></span></dt><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.cheaders">The C Headers and <code class="code">namespace std</code></a></span></dt><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.pre">Precompiled Headers</a></span></dt></dl></dd><dt><span class="section"><a href="using_macros.html">Macros</a></span></dt><dt><span class="section"><a href="using_namespaces.html">Namespaces</a></span></dt><dd><dl><dt><span class="section"><a href="using_namespaces.html#manual.intro.using.namespaces.all">Available Namespaces</a></span></dt><dt><span class="section"><a href="using_namespaces.html#manual.intro.using.namespaces.std">namespace std</a></span></dt><dt><span class="section"><a href="using_namespaces.html#manual.intro.using.namespaces.comp">Using Namespace Composition</a></span></dt></dl></dd><dt><span class="section"><a href="using_dynamic_or_shared.html">Linking</a></span></dt><dd><dl><dt><span class="section"><a href="using_dynamic_or_shared.html#manual.intro.using.linkage.freestanding">Almost Nothing</a></span></dt><dt><span class="section"><a href="using_dynamic_or_shared.html#manual.intro.using.linkage.dynamic">Finding Dynamic or Shared Libraries</a></span></dt></dl></dd><dt><span class="section"><a href="using_concurrency.html">Concurrency</a></span></dt><dd><dl><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.thread_safety">Thread Safety</a></span></dt><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.atomics">Atomics</a></span></dt><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.io">IO</a></span></dt><dd><dl><dt><span class="section"><a href="using_concurrency.html#concurrency.io.structure">Structure</a></span></dt><dt><span class="section"><a href="using_concurrency.html#concurrency.io.defaults">Defaults</a></span></dt><dt><span class="section"><a href="using_concurrency.html#concurrency.io.future">Future</a></span></dt><dt><span class="section"><a href="using_concurrency.html#concurrency.io.alt">Alternatives</a></span></dt></dl></dd><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.containers">Containers</a></span></dt></dl></dd><dt><span class="section"><a href="using_exceptions.html">Exceptions</a></span></dt><dd><dl><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.safety">Exception Safety</a></span></dt><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.propagating">Exception Neutrality</a></span></dt><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.no">Doing without</a></span></dt><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.compat">Compatibility</a></span></dt><dd><dl><dt><span class="section"><a href="using_exceptions.html#using.exception.compat.c">With <code class="literal">C</code></a></span></dt><dt><span class="section"><a href="using_exceptions.html#using.exception.compat.posix">With <code class="literal">POSIX</code> thread cancellation</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="debug.html">Debugging Support</a></span></dt><dd><dl><dt><span class="section"><a href="debug.html#debug.compiler">Using <span class="command"><strong>g++</strong></span></a></span></dt><dt><span class="section"><a href="debug.html#debug.req">Debug Versions of Library Binary Files</a></span></dt><dt><span class="section"><a href="debug.html#debug.memory">Memory Leak Hunting</a></span></dt><dt><span class="section"><a href="debug.html#debug.races">Data Race Hunting</a></span></dt><dt><span class="section"><a href="debug.html#debug.gdb">Using <span class="command"><strong>gdb</strong></span></a></span></dt><dt><span class="section"><a href="debug.html#debug.exceptions">Tracking uncaught exceptions</a></span></dt><dt><span class="section"><a href="debug.html#debug.debug_mode">Debug Mode</a></span></dt><dt><span class="section"><a href="debug.html#debug.compile_time_checks">Compile Time Checking</a></span></dt><dt><span class="section"><a href="debug.html#debug.profile_mode">Profile-based Performance Analysis</a></span></dt></dl></dd></dl></dd></dl></div></div><div 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Facilities for atomic operations.

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-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Porting to New Hardware or Operating Systems</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, internals" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B. Porting and Maintenance" /><link rel="prev" href="documentation_hacking.html" title="Writing and Generating Documentation" /><link rel="next" href="test.html" title="Test" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Porting to New Hardware or Operating Systems</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="documentation_hacking.html">Prev</a> </td><th width="60%" align="center">Appendix B.

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Porting to New Hardware or Operating Systems</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, internals" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B. Porting and Maintenance" /><link rel="prev" href="documentation_hacking.html" title="Writing and Generating Documentation" /><link rel="next" href="test.html" title="Test" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Porting to New Hardware or Operating Systems</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="documentation_hacking.html">Prev</a> </td><th width="60%" align="center">Appendix B.

2331

Porting and Maintenance

2332

2333

</th><td width="20%" align="right"> <a accesskey="n" href="test.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="appendix.porting.internals"></a>Porting to New Hardware or Operating Systems</h2></div></div></div><p>

2334

Index: libstdc++-v3/doc/html/manual/policy_data_structures_using.html

2335

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2336

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>

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-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Using</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, policy, container, data, structure, associated, tree, trie, hash, metaprogramming" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="policy_data_structures.html" title="Chapter 22. Policy-Based Data Structures" /><link rel="prev" href="policy_data_structures.html" title="Chapter 22. Policy-Based Data Structures" /><link rel="next" href="policy_data_structures_design.html" title="Design" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Using</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="policy_data_structures.html">Prev</a> </td><th width="60%" align="center">Chapter 22. Policy-Based Data Structures</th><td width="20%" align="right"> <a accesskey="n" href="policy_data_structures_design.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="containers.pbds.using"></a>Using</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="pbds.using.prereq"></a>Prerequisites</h3></div></div></div><p>The library contains only header files, and does not require any

2341

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Using</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, policy, container, data, structure, associated, tree, trie, hash, metaprogramming" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="policy_data_structures.html" title="Chapter 22. Policy-Based Data Structures" /><link rel="prev" href="policy_data_structures.html" title="Chapter 22. Policy-Based Data Structures" /><link rel="next" href="policy_data_structures_design.html" title="Design" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Using</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="policy_data_structures.html">Prev</a> </td><th width="60%" align="center">Chapter 22. Policy-Based Data Structures</th><td width="20%" align="right"> <a accesskey="n" href="policy_data_structures_design.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="containers.pbds.using"></a>Using</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="pbds.using.prereq"></a>Prerequisites</h3></div></div></div><p>The library contains only header files, and does not require any

2342

other libraries except the standard C++ library . All classes are

2343

defined in namespace <code class="code">__gnu_pbds</code>. The library internally

2344

uses macros beginning with <code class="code">PB_DS</code>, but

2345

@@ -61,7 +61,7 @@

2346

In addition, there are the following diagnostics classes,

2347

used to report errors specific to this library's data

2348

structures.

2349

- </p><div class="figure"><a id="idp17806128"></a><p class="title"><strong>Figure 22.7. Exception Hierarchy</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_exception_hierarchy.png" align="middle" alt="Exception Hierarchy" /></div></div></div><br class="figure-break" /></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="pbds.using.tutorial"></a>Tutorial</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="pbds.using.tutorial.basic"></a>Basic Use</h4></div></div></div><p>

2350

+ </p><div class="figure"><a id="idm269997724688"></a><p class="title"><strong>Figure 22.7. Exception Hierarchy</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_exception_hierarchy.png" align="middle" alt="Exception Hierarchy" /></div></div></div><br class="figure-break" /></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="pbds.using.tutorial"></a>Tutorial</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="pbds.using.tutorial.basic"></a>Basic Use</h4></div></div></div><p>

2351

For the most part, the policy-based containers containers in

2352

namespace <code class="literal">__gnu_pbds</code> have the same interface as

2353

the equivalent containers in the standard C++ library, except for

2354

Index: libstdc++-v3/doc/html/manual/bugs.html

2355

===================================================================

2356

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2357

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2358

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2359

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

2360

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Bugs</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="status.html" title="Chapter 1. Status" /><link rel="prev" href="license.html" title="License" /><link rel="next" href="setup.html" title="Chapter 2. Setup" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Bugs</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="license.html">Prev</a> </td><th width="60%" align="center">Chapter 1. Status</th><td width="20%" align="right"> <a accesskey="n" href="setup.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.status.bugs"></a>Bugs</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.intro.status.bugs.impl"></a>Implementation Bugs</h3></div></div></div><p>

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Bugs</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="status.html" title="Chapter 1. Status" /><link rel="prev" href="license.html" title="License" /><link rel="next" href="setup.html" title="Chapter 2. Setup" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Bugs</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="license.html">Prev</a> </td><th width="60%" align="center">Chapter 1. Status</th><td width="20%" align="right"> <a accesskey="n" href="setup.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.status.bugs"></a>Bugs</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.intro.status.bugs.impl"></a>Implementation Bugs</h3></div></div></div><p>

2362

Information on known bugs, details on efforts to fix them, and

2363

fixed bugs are all available as part of the <a class="link" href="http://gcc.gnu.org/bugs/" target="_top">GCC bug tracking system</a>,

2364

with the category set to <code class="literal">libstdc++</code>.

2365

Index: libstdc++-v3/doc/html/manual/parallel_mode_using.html

2366

===================================================================

2367

--- a/src/libstdc++-v3/doc/html/manual/parallel_mode_using.html (.../tags/gcc_4_8_2_release)

2368

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2369

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2370

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

2371

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Using</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="C++, library, parallel" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="parallel_mode.html" title="Chapter 18. Parallel Mode" /><link rel="prev" href="parallel_mode_semantics.html" title="Semantics" /><link rel="next" href="parallel_mode_design.html" title="Design" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Using</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="parallel_mode_semantics.html">Prev</a> </td><th width="60%" align="center">Chapter 18. Parallel Mode</th><td width="20%" align="right"> <a accesskey="n" href="parallel_mode_design.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.parallel_mode.using"></a>Using</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="parallel_mode.using.prereq_flags"></a>Prerequisite Compiler Flags</h3></div></div></div><p>

2372

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Using</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, parallel" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="parallel_mode.html" title="Chapter 18. Parallel Mode" /><link rel="prev" href="parallel_mode_semantics.html" title="Semantics" /><link rel="next" href="parallel_mode_design.html" title="Design" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Using</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="parallel_mode_semantics.html">Prev</a> </td><th width="60%" align="center">Chapter 18. Parallel Mode</th><td width="20%" align="right"> <a accesskey="n" href="parallel_mode_design.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.parallel_mode.using"></a>Using</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="parallel_mode.using.prereq_flags"></a>Prerequisite Compiler Flags</h3></div></div></div><p>

2373

Any use of parallel functionality requires additional compiler

2374

and runtime support, in particular support for OpenMP. Adding this support is

2375

not difficult: just compile your application with the compiler

2376

@@ -62,4 +62,4 @@

2377

flags for atomic operations.)

2378

</p><p> The following table provides the names and headers of all the

2379

parallel algorithms that can be used in a similar manner:

2380

-</p><div class="table"><a id="idp16725920"></a><p class="title"><strong>Table 18.1. Parallel Algorithms</strong></p><div class="table-contents"><table summary="Parallel Algorithms" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Algorithm</th><th align="left">Header</th><th align="left">Parallel algorithm</th><th align="left">Parallel header</th></tr></thead><tbody><tr><td align="left"><code class="function">std::accumulate</code></td><td align="left"><code class="filename">numeric</code></td><td align="left"><code class="function">__gnu_parallel::accumulate</code></td><td align="left"><code class="filename">parallel/numeric</code></td></tr><tr><td align="left"><code class="function">std::adjacent_difference</code></td><td align="left"><code class="filename">numeric</code></td><td align="left"><code class="function">__gnu_parallel::adjacent_difference</code></td><td align="left"><code class="filename">parallel/numeric</code></td></tr><tr><td align="left"><code class="function">std::inner_product</code></td><td align="left"><code class="filename">numeric</code></td><td align="left"><code class="function">__gnu_parallel::inner_product</code></td><td align="left"><code class="filename">parallel/numeric</code></td></tr><tr><td align="left"><code class="function">std::partial_sum</code></td><td align="left"><code class="filename">numeric</code></td><td align="left"><code class="function">__gnu_parallel::partial_sum</code></td><td align="left"><code class="filename">parallel/numeric</code></td></tr><tr><td align="left"><code class="function">std::adjacent_find</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::adjacent_find</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::count</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::count</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::count_if</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::count_if</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::equal</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::equal</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::find</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::find</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::find_if</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::find_if</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::find_first_of</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::find_first_of</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::for_each</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::for_each</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::generate</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::generate</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::generate_n</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::generate_n</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::lexicographical_compare</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::lexicographical_compare</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::mismatch</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::mismatch</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::search</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::search</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::search_n</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::search_n</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::transform</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::transform</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::replace</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::replace</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::replace_if</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::replace_if</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::max_element</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::max_element</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::merge</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::merge</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::min_element</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::min_element</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::nth_element</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::nth_element</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::partial_sort</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::partial_sort</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::partition</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::partition</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::random_shuffle</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::random_shuffle</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::set_union</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::set_union</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::set_intersection</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::set_intersection</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::set_symmetric_difference</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::set_symmetric_difference</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::set_difference</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::set_difference</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::sort</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::sort</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::stable_sort</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::stable_sort</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::unique_copy</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::unique_copy</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr></tbody></table></div></div><br class="table-break" /></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="parallel_mode_semantics.html">Prev</a> </td><td width="20%" align="center"><a accesskey="u" href="parallel_mode.html">Up</a></td><td width="40%" align="right"> <a accesskey="n" href="parallel_mode_design.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">Semantics </td><td width="20%" align="center"><a accesskey="h" href="../index.html">Home</a></td><td width="40%" align="right" valign="top"> Design</td></tr></table></div></body></html>

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+</p><div class="table"><a id="idm269998805216"></a><p class="title"><strong>Table 18.1. Parallel Algorithms</strong></p><div class="table-contents"><table summary="Parallel Algorithms" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Algorithm</th><th align="left">Header</th><th align="left">Parallel algorithm</th><th align="left">Parallel header</th></tr></thead><tbody><tr><td align="left"><code class="function">std::accumulate</code></td><td align="left"><code class="filename">numeric</code></td><td align="left"><code class="function">__gnu_parallel::accumulate</code></td><td align="left"><code class="filename">parallel/numeric</code></td></tr><tr><td align="left"><code class="function">std::adjacent_difference</code></td><td align="left"><code class="filename">numeric</code></td><td align="left"><code class="function">__gnu_parallel::adjacent_difference</code></td><td align="left"><code class="filename">parallel/numeric</code></td></tr><tr><td align="left"><code class="function">std::inner_product</code></td><td align="left"><code class="filename">numeric</code></td><td align="left"><code class="function">__gnu_parallel::inner_product</code></td><td align="left"><code class="filename">parallel/numeric</code></td></tr><tr><td align="left"><code class="function">std::partial_sum</code></td><td align="left"><code class="filename">numeric</code></td><td align="left"><code class="function">__gnu_parallel::partial_sum</code></td><td align="left"><code class="filename">parallel/numeric</code></td></tr><tr><td align="left"><code class="function">std::adjacent_find</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::adjacent_find</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::count</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::count</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::count_if</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::count_if</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::equal</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::equal</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::find</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::find</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::find_if</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::find_if</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::find_first_of</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::find_first_of</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::for_each</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::for_each</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::generate</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::generate</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::generate_n</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::generate_n</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::lexicographical_compare</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::lexicographical_compare</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::mismatch</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::mismatch</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::search</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::search</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::search_n</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::search_n</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::transform</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::transform</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::replace</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::replace</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::replace_if</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::replace_if</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::max_element</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::max_element</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::merge</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::merge</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::min_element</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::min_element</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::nth_element</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::nth_element</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::partial_sort</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::partial_sort</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::partition</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::partition</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::random_shuffle</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::random_shuffle</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::set_union</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::set_union</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::set_intersection</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::set_intersection</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::set_symmetric_difference</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::set_symmetric_difference</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::set_difference</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::set_difference</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::sort</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::sort</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::stable_sort</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::stable_sort</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::unique_copy</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::unique_copy</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr></tbody></table></div></div><br class="table-break" /></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="parallel_mode_semantics.html">Prev</a> </td><td width="20%" align="center"><a accesskey="u" href="parallel_mode.html">Up</a></td><td width="40%" align="right"> <a accesskey="n" href="parallel_mode_design.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">Semantics </td><td width="20%" align="center"><a accesskey="h" href="../index.html">Home</a></td><td width="40%" align="right" valign="top"> Design</td></tr></table></div></body></html>

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+</a></span></dt><dd><dl><dt><span class="section"><a href="utilities.html#std.util.functors">Functors</a></span></dt><dt><span class="section"><a href="pairs.html">Pairs</a></span></dt><dt><span class="section"><a href="memory.html">Memory</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#std.util.memory.allocator">Allocators</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#allocator.req">Requirements</a></span></dt><dt><span class="section"><a href="memory.html#allocator.design_issues">Design Issues</a></span></dt><dt><span class="section"><a href="memory.html#allocator.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idm270001611968">Interface Design</a></span></dt><dt><span class="section"><a href="memory.html#idm270001608416">Selecting Default Allocation Policy</a></span></dt><dt><span class="section"><a href="memory.html#idm270001595120">Disabling Memory Caching</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#allocator.using">Using a Specific Allocator</a></span></dt><dt><span class="section"><a href="memory.html#allocator.custom">Custom Allocators</a></span></dt><dt><span class="section"><a href="memory.html#allocator.ext">Extension Allocators</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#std.util.memory.auto_ptr">auto_ptr</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#auto_ptr.limitations">Limitations</a></span></dt><dt><span class="section"><a href="memory.html#auto_ptr.using">Use in Containers</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#std.util.memory.shared_ptr">shared_ptr</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#shared_ptr.req">Requirements</a></span></dt><dt><span class="section"><a href="memory.html#shared_ptr.design_issues">Design Issues</a></span></dt><dt><span class="section"><a href="memory.html#shared_ptr.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idm270000019344">Class Hierarchy</a></span></dt><dt><span class="section"><a href="memory.html#idm269999996832">Thread Safety</a></span></dt><dt><span class="section"><a href="memory.html#idm269999989536">Selecting Lock Policy</a></span></dt><dt><span class="section"><a href="memory.html#idm269999974912">Related functions and classes</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#shared_ptr.using">Use</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idm269999958496">Examples</a></span></dt><dt><span class="section"><a href="memory.html#idm269999954912">Unresolved Issues</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#shared_ptr.ack">Acknowledgments</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="traits.html">Traits</a></span></dt></dl></dd><dt><span class="chapter"><a href="strings.html">7.

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</a></span></dt><dd><dl><dt><span class="section"><a href="strings.html#std.strings.string">String Classes</a></span></dt><dd><dl><dt><span class="section"><a href="strings.html#strings.string.simple">Simple Transformations</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.case">Case Sensitivity</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.character_types">Arbitrary Character Types</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.token">Tokenizing</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.shrink">Shrink to Fit</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.Cstring">CString (MFC)</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="localization.html">8.

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Localization

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-</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#std.localization.locales">Locales</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#std.localization.locales.locale">locale</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#locales.locale.req">Requirements</a></span></dt><dt><span class="section"><a href="localization.html#locales.locale.design">Design</a></span></dt><dt><span class="section"><a href="localization.html#locales.locale.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#locale.impl.c">Interacting with "C" locales</a></span></dt></dl></dd><dt><span class="section"><a href="localization.html#locales.locale.future">Future</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="facets.html">Facets</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#std.localization.facet.ctype">ctype</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.ctype.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#idp15778336">Specializations</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.ctype.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#std.localization.facet.codecvt">codecvt</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.codecvt.req">Requirements</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.design">Design</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#codecvt.design.wchar_t_size"><span class="type">wchar_t</span> Size</a></span></dt><dt><span class="section"><a href="facets.html#codecvt.design.unicode">Support for Unicode</a></span></dt><dt><span class="section"><a href="facets.html#codecvt.design.issues">Other Issues</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.codecvt.impl">Implementation</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.use">Use</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#manual.localization.facet.messages">messages</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.messages.req">Requirements</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.design">Design</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#messages.impl.models">Models</a></span></dt><dt><span class="section"><a href="facets.html#messages.impl.gnu">The GNU Model</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.messages.use">Use</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.future">Future</a></span></dt></dl></dd></dl></dd></dl></dd><dt><span class="chapter"><a href="containers.html">9.

2434

+</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#std.localization.locales">Locales</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#std.localization.locales.locale">locale</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#locales.locale.req">Requirements</a></span></dt><dt><span class="section"><a href="localization.html#locales.locale.design">Design</a></span></dt><dt><span class="section"><a href="localization.html#locales.locale.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#locale.impl.c">Interacting with "C" locales</a></span></dt></dl></dd><dt><span class="section"><a href="localization.html#locales.locale.future">Future</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="facets.html">Facets</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#std.localization.facet.ctype">ctype</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.ctype.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#idm269999753024">Specializations</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.ctype.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#std.localization.facet.codecvt">codecvt</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.codecvt.req">Requirements</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.design">Design</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#codecvt.design.wchar_t_size"><span class="type">wchar_t</span> Size</a></span></dt><dt><span class="section"><a href="facets.html#codecvt.design.unicode">Support for Unicode</a></span></dt><dt><span class="section"><a href="facets.html#codecvt.design.issues">Other Issues</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.codecvt.impl">Implementation</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.use">Use</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#manual.localization.facet.messages">messages</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.messages.req">Requirements</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.design">Design</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#messages.impl.models">Models</a></span></dt><dt><span class="section"><a href="facets.html#messages.impl.gnu">The GNU Model</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.messages.use">Use</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.future">Future</a></span></dt></dl></dd></dl></dd></dl></dd><dt><span class="chapter"><a href="containers.html">9.

2435

Containers

2436

2437

</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#std.containers.sequences">Sequences</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#containers.sequences.list">list</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#sequences.list.size">list::size() is O(n)</a></span></dt></dl></dd><dt><span class="section"><a href="containers.html#containers.sequences.vector">vector</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#sequences.vector.management">Space Overhead Management</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="associative.html">Associative</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#containers.associative.insert_hints">Insertion Hints</a></span></dt><dt><span class="section"><a href="associative.html#containers.associative.bitset">bitset</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#associative.bitset.size_variable">Size Variable</a></span></dt><dt><span class="section"><a href="associative.html#associative.bitset.type_string">Type String</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="unordered_associative.html">Unordered Associative</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.hash">Hash Code</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.cache">Hash Code Caching Policy</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="containers_and_c.html">Interacting with C</a></span></dt><dd><dl><dt><span class="section"><a href="containers_and_c.html#containers.c.vs_array">Containers vs. Arrays</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="iterators.html">10.

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2439

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2440

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2441

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2442

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2443

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

2444

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Part IV. Appendices</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="index.html" title="The GNU C++ Library Manual" /><link rel="prev" href="ext_concurrency_use.html" title="Use" /><link rel="next" href="appendix_contributing.html" title="Appendix A. Contributing" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Part IV.

2445

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Part IV. Appendices</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="index.html" title="The GNU C++ Library Manual" /><link rel="prev" href="ext_concurrency_use.html" title="Use" /><link rel="next" href="appendix_contributing.html" title="Appendix A. Contributing" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Part IV.

2446

Appendices

2447

</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_concurrency_use.html">Prev</a> </td><th width="60%" align="center">The GNU C++ Library Manual</th><td width="20%" align="right"> <a accesskey="n" href="appendix_contributing.html">Next</a></td></tr></table><hr /></div><div class="part"><div class="titlepage"><div><div><h1 class="title"><a id="appendix"></a>Part IV.

2448

Appendices

2449

-</h1></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="appendix"><a href="appendix_contributing.html">A.

2450

+</h1></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="appendix"><a href="appendix_contributing.html">A.

2451

Contributing

2452

2453

</a></span></dt><dd><dl><dt><span class="section"><a href="appendix_contributing.html#contrib.list">Contributor Checklist</a></span></dt><dd><dl><dt><span class="section"><a href="appendix_contributing.html#list.reading">Reading</a></span></dt><dt><span class="section"><a href="appendix_contributing.html#list.copyright">Assignment</a></span></dt><dt><span class="section"><a href="appendix_contributing.html#list.getting">Getting Sources</a></span></dt><dt><span class="section"><a href="appendix_contributing.html#list.patches">Submitting Patches</a></span></dt></dl></dd><dt><span class="section"><a href="source_organization.html">Directory Layout and Source Conventions</a></span></dt><dt><span class="section"><a href="source_code_style.html">Coding Style</a></span></dt><dd><dl><dt><span class="section"><a href="source_code_style.html#coding_style.bad_identifiers">Bad Identifiers</a></span></dt><dt><span class="section"><a href="source_code_style.html#coding_style.example">By Example</a></span></dt></dl></dd><dt><span class="section"><a href="source_design_notes.html">Design Notes</a></span></dt></dl></dd><dt><span class="appendix"><a href="appendix_porting.html">B.

2454

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2455

===================================================================

2456

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2457

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2458

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2459

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

2460

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Memory</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="utilities.html" title="Chapter 6. Utilities" /><link rel="prev" href="pairs.html" title="Pairs" /><link rel="next" href="traits.html" title="Traits" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Memory</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="pairs.html">Prev</a> </td><th width="60%" align="center">Chapter 6.

2461

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Memory</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="utilities.html" title="Chapter 6. Utilities" /><link rel="prev" href="pairs.html" title="Pairs" /><link rel="next" href="traits.html" title="Traits" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Memory</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="pairs.html">Prev</a> </td><th width="60%" align="center">Chapter 6.

2462

Utilities

2463

2464

</th><td width="20%" align="right"> <a accesskey="n" href="traits.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.util.memory"></a>Memory</h2></div></div></div><p>

2465

@@ -92,7 +92,7 @@

2466

or loading and unloading shared objects in memory. As such, using

2467

caching allocators on systems that do not support

2468

<code class="function">abi::__cxa_atexit</code> is not recommended.

2469

- </p></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="allocator.impl"></a>Implementation</h4></div></div></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idp13920976"></a>Interface Design</h5></div></div></div><p>

2470

+ </p></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="allocator.impl"></a>Implementation</h4></div></div></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idm270001611968"></a>Interface Design</h5></div></div></div><p>

2471

The only allocator interface that

2472

is supported is the standard C++ interface. As such, all STL

2473

containers have been adjusted, and all external allocators have

2474

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2475

</p><p>

2476

The base class that <code class="classname">allocator</code> is derived from

2477

may not be user-configurable.

2478

-</p></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idp13924528"></a>Selecting Default Allocation Policy</h5></div></div></div><p>

2479

+</p></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idm270001608416"></a>Selecting Default Allocation Policy</h5></div></div></div><p>

2480

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2481

maximum utility, without excessively penalizing some behavior. In

2482

fact, it's difficult just deciding which typical actions to measure

2483

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2484

The current default choice for

2485

<code class="classname">allocator</code> is

2486

<code class="classname">__gnu_cxx::new_allocator</code>.

2487

- </p></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idp13937824"></a>Disabling Memory Caching</h5></div></div></div><p>

2488

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2489

In use, <code class="classname">allocator</code> may allocate and

2490

deallocate using implementation-specific strategies and

2491

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2492

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2493

of the used and unused memory locations. It has its own

2494

<a class="link" href="bitmap_allocator.html" title="Chapter 21. The bitmap_allocator">chapter</a>

2495

in the documentation.

2496

- </p></li></ol></div></div><div class="bibliography"><div class="titlepage"><div><div><h4 class="title"><a id="allocator.biblio"></a>Bibliography</h4></div></div></div><div class="biblioentry"><a id="idp13992848"></a><p><span class="citetitle"><em class="citetitle">

2497

+ </p></li></ol></div></div><div class="bibliography"><div class="titlepage"><div><div><h4 class="title"><a id="allocator.biblio"></a>Bibliography</h4></div></div></div><div class="biblioentry"><a id="idm270000084224"></a><p><span class="citetitle"><em class="citetitle">

2498

ISO/IEC 14882:1998 Programming languages - C++

2499

</em>. </span>

2500

isoc++_1998

2501

- <span class="pagenums">20.4 Memory. </span></p></div><div class="biblioentry"><a id="idp13994688"></a><p><span class="title"><em>

2502

- <a class="link" href="http://www.drdobbs.com/cpp/184403759" target="_top">

2503

+ <span class="pagenums">20.4 Memory. </span></p></div><div class="biblioentry"><a id="idm270000082384"></a><p><span class="title"><em>

2504

+ <a class="link" href="http://www.drdobbs.com/the-standard-librarian-what-are-allocato/184403759" target="_top">

2505

The Standard Librarian: What Are Allocators Good For?

2506

</a>

2507

</em>. </span><span class="author"><span class="firstname">Matt</span> <span class="surname">Austern</span>. </span><span class="publisher"><span class="publishername">

2508

C/C++ Users Journal

2509

- . </span></span></p></div><div class="biblioentry"><a id="idp13998416"></a><p><span class="title"><em>

2510

+ . </span></span></p></div><div class="biblioentry"><a id="idm270000078608"></a><p><span class="title"><em>

2511

2512

The Hoard Memory Allocator

2513

</a>

2514

- </em>. </span><span class="author"><span class="firstname">Emery</span> <span class="surname">Berger</span>. </span></p></div><div class="biblioentry"><a id="idp14001184"></a><p><span class="title"><em>

2515

+ </em>. </span><span class="author"><span class="firstname">Emery</span> <span class="surname">Berger</span>. </span></p></div><div class="biblioentry"><a id="idm270000075840"></a><p><span class="title"><em>

2516

2517

Reconsidering Custom Memory Allocation

2518

</a>

2519

- </em>. </span><span class="author"><span class="firstname">Emery</span> <span class="surname">Berger</span>. </span><span class="author"><span class="firstname">Ben</span> <span class="surname">Zorn</span>. </span><span class="author"><span class="firstname">Kathryn</span> <span class="surname">McKinley</span>. </span><span class="copyright">Copyright © 2002 OOPSLA. </span></p></div><div class="biblioentry"><a id="idp14007344"></a><p><span class="title"><em>

2520

+ </em>. </span><span class="author"><span class="firstname">Emery</span> <span class="surname">Berger</span>. </span><span class="author"><span class="firstname">Ben</span> <span class="surname">Zorn</span>. </span><span class="author"><span class="firstname">Kathryn</span> <span class="surname">McKinley</span>. </span><span class="copyright">Copyright © 2002 OOPSLA. </span></p></div><div class="biblioentry"><a id="idm270000069680"></a><p><span class="title"><em>

2521

2522

Allocator Types

2523

</a>

2524

</em>. </span><span class="author"><span class="firstname">Klaus</span> <span class="surname">Kreft</span>. </span><span class="author"><span class="firstname">Angelika</span> <span class="surname">Langer</span>. </span><span class="publisher"><span class="publishername">

2525

C/C++ Users Journal

2526

- . </span></span></p></div><div class="biblioentry"><a id="idp14012080"></a><p><span class="citetitle"><em class="citetitle">The C++ Programming Language</em>. </span><span class="author"><span class="firstname">Bjarne</span> <span class="surname">Stroustrup</span>. </span><span class="copyright">Copyright © 2000 . </span><span class="pagenums">19.4 Allocators. </span><span class="publisher"><span class="publishername">

2527

+ . </span></span></p></div><div class="biblioentry"><a id="idm270000064944"></a><p><span class="citetitle"><em class="citetitle">The C++ Programming Language</em>. </span><span class="author"><span class="firstname">Bjarne</span> <span class="surname">Stroustrup</span>. </span><span class="copyright">Copyright © 2000 . </span><span class="pagenums">19.4 Allocators. </span><span class="publisher"><span class="publishername">

2528

Addison Wesley

2529

- . </span></span></p></div><div class="biblioentry"><a id="idp14016512"></a><p><span class="citetitle"><em class="citetitle">Yalloc: A Recycling C++ Allocator</em>. </span><span class="author"><span class="firstname">Felix</span> <span class="surname">Yen</span>. </span></p></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="std.util.memory.auto_ptr"></a>auto_ptr</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="auto_ptr.limitations"></a>Limitations</h4></div></div></div><p>Explaining all of the fun and delicious things that can

2530

+ . </span></span></p></div><div class="biblioentry"><a id="idm270000060512"></a><p><span class="citetitle"><em class="citetitle">Yalloc: A Recycling C++ Allocator</em>. </span><span class="author"><span class="firstname">Felix</span> <span class="surname">Yen</span>. </span></p></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="std.util.memory.auto_ptr"></a>auto_ptr</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="auto_ptr.limitations"></a>Limitations</h4></div></div></div><p>Explaining all of the fun and delicious things that can

2531

happen with misuse of the <code class="classname">auto_ptr</code> class

2532

template (called <acronym class="acronym">AP</acronym> here) would take some

2533

time. Suffice it to say that the use of <acronym class="acronym">AP</acronym>

2534

@@ -445,7 +445,7 @@

2535

Derived classes override those functions to destroy resources in a context

2536

where the correct dynamic type is known. This is an application of the

2537

technique known as type erasure.

2538

- </p></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="shared_ptr.impl"></a>Implementation</h4></div></div></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idp15512272"></a>Class Hierarchy</h5></div></div></div><p>

2539

+ </p></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="shared_ptr.impl"></a>Implementation</h4></div></div></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idm270000019344"></a>Class Hierarchy</h5></div></div></div><p>

2540

A <code class="classname">shared_ptr<T></code> contains a pointer of

2541

type <span class="type">T*</span> and an object of type

2542

<code class="classname">__shared_count</code>. The shared_count contains a

2543

@@ -492,9 +492,9 @@

2544

aliasing constructor, make_shared & allocate_shared. Additionally,

2545

the constructors taking <code class="classname">auto_ptr</code> parameters are

2546

deprecated in C++11 mode.

2547

- </p></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idp15534784"></a>Thread Safety</h5></div></div></div><p>

2548

+ </p></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idm269999996832"></a>Thread Safety</h5></div></div></div><p>

2549

The

2550

-<a class="link" href="http://boost.org/libs/smart_ptr/shared_ptr.htm#ThreadSafety" target="_top">Thread

2551

+<a class="link" href="http://www.boost.org/libs/smart_ptr/shared_ptr.htm#ThreadSafety" target="_top">Thread

2552

Safety</a> section of the Boost shared_ptr documentation says "shared_ptr

2553

objects offer the same level of thread safety as built-in types."

2554

The implementation must ensure that concurrent updates to separate shared_ptr

2555

@@ -537,7 +537,7 @@

2556

shared_ptr in libstdc++ the compiler and library are fixed, which

2557

makes things much simpler: we have an atomic CAS or we don't, see Lock

2558

Policy below for details.

2559

-</p></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idp15542080"></a>Selecting Lock Policy</h5></div></div></div><p>

2560

+</p></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idm269999989536"></a>Selecting Lock Policy</h5></div></div></div><p>

2561

</p><p>

2562

There is a single <code class="classname">_Sp_counted_base</code> class,

2563

which is a template parameterized on the enum

2564

@@ -578,7 +578,7 @@

2565

<code class="filename">ext/atomicity.h</code>, which detect if the program

2566

is multi-threaded. If only one thread of execution exists in

2567

the program then less expensive non-atomic operations are used.

2568

- </p></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idp15556704"></a>Related functions and classes</h5></div></div></div><div class="variablelist"><dl class="variablelist"><dt><span class="term"><code class="code">dynamic_pointer_cast</code>, <code class="code">static_pointer_cast</code>,

2569

+ </p></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idm269999974912"></a>Related functions and classes</h5></div></div></div><div class="variablelist"><dl class="variablelist"><dt><span class="term"><code class="code">dynamic_pointer_cast</code>, <code class="code">static_pointer_cast</code>,

2570

<code class="code">const_pointer_cast</code></span></dt><dd><p>

2571

As noted in N2351, these functions can be implemented non-intrusively using

2572

the alias constructor. However the aliasing constructor is only available

2573

@@ -611,13 +611,13 @@

2574

As well as the extra constructors, this implementation also needs some

2575

members of _Sp_counted_deleter to be protected where they could otherwise

2576

be private.

2577

- </p></dd></dl></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="shared_ptr.using"></a>Use</h4></div></div></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idp15573056"></a>Examples</h5></div></div></div><p>

2578

+ </p></dd></dl></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="shared_ptr.using"></a>Use</h4></div></div></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idm269999958496"></a>Examples</h5></div></div></div><p>

2579

Examples of use can be found in the testsuite, under

2580

<code class="filename">testsuite/tr1/2_general_utilities/shared_ptr</code>,

2581

<code class="filename">testsuite/20_util/shared_ptr</code>

2582

and

2583

<code class="filename">testsuite/20_util/weak_ptr</code>.

2584

- </p></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idp15576640"></a>Unresolved Issues</h5></div></div></div><p>

2585

+ </p></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idm269999954912"></a>Unresolved Issues</h5></div></div></div><p>

2586

The <span class="emphasis"><em><code class="classname">shared_ptr</code> atomic access</em></span>

2587

clause in the C++11 standard is not implemented in GCC.

2588

</p><p>

2589

@@ -658,25 +658,25 @@

2590

code to work with, Peter Dimov in particular for his help and

2591

invaluable advice on thread safety. Phillip Jordan and Paolo

2592

Carlini for the lock policy implementation.

2593

- </p></div><div class="bibliography"><div class="titlepage"><div><div><h4 class="title"><a id="shared_ptr.biblio"></a>Bibliography</h4></div></div></div><div class="biblioentry"><a id="idp15587936"></a><p><span class="title"><em>

2594

+ </p></div><div class="bibliography"><div class="titlepage"><div><div><h4 class="title"><a id="shared_ptr.biblio"></a>Bibliography</h4></div></div></div><div class="biblioentry"><a id="idm269999943680"></a><p><span class="title"><em>

2595

2596

Improving shared_ptr for C++0x, Revision 2

2597

</a>

2598

</em>. </span><span class="subtitle">

2599

N2351

2600

- . </span></p></div><div class="biblioentry"><a id="idp15590224"></a><p><span class="title"><em>

2601

+ . </span></p></div><div class="biblioentry"><a id="idm269999941392"></a><p><span class="title"><em>

2602

2603

C++ Standard Library Active Issues List

2604

</a>

2605

</em>. </span><span class="subtitle">

2606

N2456

2607

- . </span></p></div><div class="biblioentry"><a id="idp15592512"></a><p><span class="title"><em>

2608

+ . </span></p></div><div class="biblioentry"><a id="idm269999939104"></a><p><span class="title"><em>

2609

2610

Working Draft, Standard for Programming Language C++

2611

</a>

2612

</em>. </span><span class="subtitle">

2613

N2461

2614

- . </span></p></div><div class="biblioentry"><a id="idp15594816"></a><p><span class="title"><em>

2615

+ . </span></p></div><div class="biblioentry"><a id="idm269999936800"></a><p><span class="title"><em>

2616

2617

Boost C++ Libraries documentation, shared_ptr

2618

</a>

2619

Index: libstdc++-v3/doc/html/manual/api.html

2620

===================================================================

2621

--- a/src/libstdc++-v3/doc/html/manual/api.html (.../tags/gcc_4_8_2_release)

2622

+++ b/src/libstdc++-v3/doc/html/manual/api.html (.../branches/gcc-4_8-branch)

2623

@@ -1,5 +1,5 @@

2624

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

2625

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>API Evolution and Deprecation History</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, api, evolution, deprecation, history" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B. Porting and Maintenance" /><link rel="prev" href="abi.html" title="ABI Policy and Guidelines" /><link rel="next" href="backwards.html" title="Backwards Compatibility" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">API Evolution and Deprecation History</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="abi.html">Prev</a> </td><th width="60%" align="center">Appendix B.

2626

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>API Evolution and Deprecation History</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, api, evolution, deprecation, history" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B. Porting and Maintenance" /><link rel="prev" href="abi.html" title="ABI Policy and Guidelines" /><link rel="next" href="backwards.html" title="Backwards Compatibility" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">API Evolution and Deprecation History</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="abi.html">Prev</a> </td><th width="60%" align="center">Appendix B.

2627

Porting and Maintenance

2628

2629

</th><td width="20%" align="right"> <a accesskey="n" href="backwards.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="appendix.porting.api"></a>API Evolution and Deprecation History</h2></div></div></div><p>

2630

@@ -77,11 +77,11 @@

2631

<span class="type">__alloc</span> to select an underlying allocator that

2632

satisfied memory allocation requests. The selection of this

2633

underlying allocator was not user-configurable.

2634

- </p><div class="table"><a id="idp23030528"></a><p class="title"><strong>Table B.6. Extension Allocators</strong></p><div class="table-contents"><table summary="Extension Allocators" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Allocator (3.4)</th><th align="left">Header (3.4)</th><th align="left">Allocator (3.[0-3])</th><th align="left">Header (3.[0-3])</th></tr></thead><tbody><tr><td align="left"><code class="classname">__gnu_cxx::new_allocator<T></code></td><td align="left"><code class="filename">ext/new_allocator.h</code></td><td align="left"><code class="classname">std::__new_alloc</code></td><td align="left"><code class="filename">memory</code></td></tr><tr><td align="left"><code class="classname">__gnu_cxx::malloc_allocator<T></code></td><td align="left"><code class="filename">ext/malloc_allocator.h</code></td><td align="left"><code class="classname">std::__malloc_alloc_template<int></code></td><td align="left"><code class="filename">memory</code></td></tr><tr><td align="left"><code class="classname">__gnu_cxx::debug_allocator<T></code></td><td align="left"><code class="filename">ext/debug_allocator.h</code></td><td align="left"><code class="classname">std::debug_alloc<T></code></td><td align="left"><code class="filename">memory</code></td></tr><tr><td align="left"><code class="classname">__gnu_cxx::__pool_alloc<T></code></td><td align="left"><code class="filename">ext/pool_allocator.h</code></td><td align="left"><code class="classname">std::__default_alloc_template<bool,int></code></td><td align="left"><code class="filename">memory</code></td></tr><tr><td align="left"><code class="classname">__gnu_cxx::__mt_alloc<T></code></td><td align="left"><code class="filename">ext/mt_allocator.h</code></td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left"><code class="classname">__gnu_cxx::bitmap_allocator<T></code></td><td align="left"><code class="filename">ext/bitmap_allocator.h</code></td><td align="left"> </td><td align="left"> </td></tr></tbody></table></div></div><br class="table-break" /><p> Releases after gcc-3.4 have continued to add to the collection

2635

+ </p><div class="table"><a id="idm269992502096"></a><p class="title"><strong>Table B.6. Extension Allocators</strong></p><div class="table-contents"><table summary="Extension Allocators" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Allocator (3.4)</th><th align="left">Header (3.4)</th><th align="left">Allocator (3.[0-3])</th><th align="left">Header (3.[0-3])</th></tr></thead><tbody><tr><td align="left"><code class="classname">__gnu_cxx::new_allocator<T></code></td><td align="left"><code class="filename">ext/new_allocator.h</code></td><td align="left"><code class="classname">std::__new_alloc</code></td><td align="left"><code class="filename">memory</code></td></tr><tr><td align="left"><code class="classname">__gnu_cxx::malloc_allocator<T></code></td><td align="left"><code class="filename">ext/malloc_allocator.h</code></td><td align="left"><code class="classname">std::__malloc_alloc_template<int></code></td><td align="left"><code class="filename">memory</code></td></tr><tr><td align="left"><code class="classname">__gnu_cxx::debug_allocator<T></code></td><td align="left"><code class="filename">ext/debug_allocator.h</code></td><td align="left"><code class="classname">std::debug_alloc<T></code></td><td align="left"><code class="filename">memory</code></td></tr><tr><td align="left"><code class="classname">__gnu_cxx::__pool_alloc<T></code></td><td align="left"><code class="filename">ext/pool_allocator.h</code></td><td align="left"><code class="classname">std::__default_alloc_template<bool,int></code></td><td align="left"><code class="filename">memory</code></td></tr><tr><td align="left"><code class="classname">__gnu_cxx::__mt_alloc<T></code></td><td align="left"><code class="filename">ext/mt_allocator.h</code></td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left"><code class="classname">__gnu_cxx::bitmap_allocator<T></code></td><td align="left"><code class="filename">ext/bitmap_allocator.h</code></td><td align="left"> </td><td align="left"> </td></tr></tbody></table></div></div><br class="table-break" /><p> Releases after gcc-3.4 have continued to add to the collection

2636

of available allocators. All of these new allocators are

2637

standard-style. The following table includes details, along with

2638

the first released version of GCC that included the extension allocator.

2639

- </p><div class="table"><a id="idp23058160"></a><p class="title"><strong>Table B.7. Extension Allocators Continued</strong></p><div class="table-contents"><table summary="Extension Allocators Continued" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left">Allocator</th><th align="left">Include</th><th align="left">Version</th></tr></thead><tbody><tr><td align="left"><code class="classname">__gnu_cxx::array_allocator<T></code></td><td align="left"><code class="filename">ext/array_allocator.h</code></td><td align="left">4.0.0</td></tr><tr><td align="left"><code class="classname">__gnu_cxx::throw_allocator<T></code></td><td align="left"><code class="filename">ext/throw_allocator.h</code></td><td align="left">4.2.0</td></tr></tbody></table></div></div><br class="table-break" /><p>

2640

+ </p><div class="table"><a id="idm269992474464"></a><p class="title"><strong>Table B.7. Extension Allocators Continued</strong></p><div class="table-contents"><table summary="Extension Allocators Continued" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left">Allocator</th><th align="left">Include</th><th align="left">Version</th></tr></thead><tbody><tr><td align="left"><code class="classname">__gnu_cxx::array_allocator<T></code></td><td align="left"><code class="filename">ext/array_allocator.h</code></td><td align="left">4.0.0</td></tr><tr><td align="left"><code class="classname">__gnu_cxx::throw_allocator<T></code></td><td align="left"><code class="filename">ext/throw_allocator.h</code></td><td align="left">4.2.0</td></tr></tbody></table></div></div><br class="table-break" /><p>

2641

Debug mode first appears.

2642

</p><p>

2643

Precompiled header support <acronym class="acronym">PCH</acronym> support.

2644

Index: libstdc++-v3/doc/html/manual/source_organization.html

2645

===================================================================

2646

--- a/src/libstdc++-v3/doc/html/manual/source_organization.html (.../tags/gcc_4_8_2_release)

2647

+++ b/src/libstdc++-v3/doc/html/manual/source_organization.html (.../branches/gcc-4_8-branch)

2648

@@ -1,5 +1,5 @@

2649

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

2650

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Directory Layout and Source Conventions</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_contributing.html" title="Appendix A. Contributing" /><link rel="prev" href="appendix_contributing.html" title="Appendix A. Contributing" /><link rel="next" href="source_code_style.html" title="Coding Style" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Directory Layout and Source Conventions</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="appendix_contributing.html">Prev</a> </td><th width="60%" align="center">Appendix A.

2651

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Directory Layout and Source Conventions</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_contributing.html" title="Appendix A. Contributing" /><link rel="prev" href="appendix_contributing.html" title="Appendix A. Contributing" /><link rel="next" href="source_code_style.html" title="Coding Style" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Directory Layout and Source Conventions</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="appendix_contributing.html">Prev</a> </td><th width="60%" align="center">Appendix A.

2652

Contributing

2653

2654

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2655

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2656

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2660

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

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2662

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>File Based Streams</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="io.html" title="Chapter 13. Input and Output" /><link rel="prev" href="stringstreams.html" title="Memory Based Streams" /><link rel="next" href="io_and_c.html" title="Interacting with C" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">File Based Streams</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="stringstreams.html">Prev</a> </td><th width="60%" align="center">Chapter 13.

2663

Input and Output

2664

2665

</th><td width="20%" align="right"> <a accesskey="n" href="io_and_c.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.io.filestreams"></a>File Based Streams</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="std.io.filestreams.copying_a_file"></a>Copying a File</h3></div></div></div><p>

2666

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2667

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2668

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2670

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2671

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2672

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2673

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 29. Demangling</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III. Extensions" /><link rel="prev" href="ext_io.html" title="Chapter 28. Input and Output" /><link rel="next" href="ext_concurrency.html" title="Chapter 30. Concurrency" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 29. Demangling</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_io.html">Prev</a> </td><th width="60%" align="center">Part III.

2674

Extensions

2675

2676

</th><td width="20%" align="right"> <a accesskey="n" href="ext_concurrency.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.demangle"></a>Chapter 29. Demangling</h2></div></div></div><p>

2677

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2678

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2679

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2681

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2682

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

2683

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title></title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III. Extensions" /><link rel="prev" href="extensions.html" title="Part III. Extensions" /><link rel="next" href="ext_compile_checks.html" title="Chapter 16. Compile Time Checks" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center"></th></tr><tr><td width="20%" align="left"><a accesskey="p" href="extensions.html">Prev</a> </td><th width="60%" align="center">Part III.

2684

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title></title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III. Extensions" /><link rel="prev" href="extensions.html" title="Part III. Extensions" /><link rel="next" href="ext_compile_checks.html" title="Chapter 16. Compile Time Checks" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center"></th></tr><tr><td width="20%" align="left"><a accesskey="p" href="extensions.html">Prev</a> </td><th width="60%" align="center">Part III.

2685

Extensions

2686

2687

-</th><td width="20%" align="right"> <a accesskey="n" href="ext_compile_checks.html">Next</a></td></tr></table><hr /></div><div class="preface"><div class="titlepage"><div><div><h1 class="title"><a id="idp16425920"></a></h1></div></div></div><p>

2688

+</th><td width="20%" align="right"> <a accesskey="n" href="ext_compile_checks.html">Next</a></td></tr></table><hr /></div><div class="preface"><div class="titlepage"><div><div><h1 class="title"><a id="idm269999105296"></a></h1></div></div></div><p>

2689

Here we will make an attempt at describing the non-Standard

2690

extensions to the library. Some of these are from older versions of

2691

standard library components, namely SGI's STL, and some of these are

2692

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2693

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2694

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2695

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2696

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2697

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2698

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2699

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Concept Checking</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="diagnostics.html" title="Chapter 5. Diagnostics" /><link rel="prev" href="diagnostics.html" title="Chapter 5. Diagnostics" /><link rel="next" href="utilities.html" title="Chapter 6. Utilities" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Concept Checking</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="diagnostics.html">Prev</a> </td><th width="60%" align="center">Chapter 5.

2700

Diagnostics

2701

2702

</th><td width="20%" align="right"> <a accesskey="n" href="utilities.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.diagnostics.concept_checking"></a>Concept Checking</h2></div></div></div><p>

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2704

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2705

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2707

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2708

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2709

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2710

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Multiple Thread Example</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, allocator" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="mt_allocator.html" title="Chapter 20. The mt_allocator" /><link rel="prev" href="mt_allocator_ex_single.html" title="Single Thread Example" /><link rel="next" href="bitmap_allocator.html" title="Chapter 21. The bitmap_allocator" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Multiple Thread Example</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="mt_allocator_ex_single.html">Prev</a> </td><th width="60%" align="center">Chapter 20. The mt_allocator</th><td width="20%" align="right"> <a accesskey="n" href="bitmap_allocator.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="allocator.mt.example_multi"></a>Multiple Thread Example</h2></div></div></div><p>

2711

In the ST example we never used the thread_id variable present in each block.

2712

Let's start by explaining the purpose of this in a MT application.

2713

</p><p>

2714

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2715

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2716

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2717

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2718

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2719

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2721

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 16. Compile Time Checks</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III. Extensions" /><link rel="prev" href="ext_preface.html" title="" /><link rel="next" href="debug_mode.html" title="Chapter 17. Debug Mode" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 16. Compile Time Checks</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_preface.html">Prev</a> </td><th width="60%" align="center">Part III.

2722

Extensions

2723

2724

</th><td width="20%" align="right"> <a accesskey="n" href="debug_mode.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.compile_checks"></a>Chapter 16. Compile Time Checks</h2></div></div></div><p>

2725

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2726

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2727

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2732

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2733

Strings

2734

2735

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2736

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2737

Standard Contents

2738

</th><td width="20%" align="right"> <a accesskey="n" href="localization.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="std.strings"></a>Chapter 7.

2739

Strings

2740

- <a id="idp15603440" class="indexterm"></a>

2741

-</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="strings.html#std.strings.string">String Classes</a></span></dt><dd><dl><dt><span class="section"><a href="strings.html#strings.string.simple">Simple Transformations</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.case">Case Sensitivity</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.character_types">Arbitrary Character Types</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.token">Tokenizing</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.shrink">Shrink to Fit</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.Cstring">CString (MFC)</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.strings.string"></a>String Classes</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="strings.string.simple"></a>Simple Transformations</h3></div></div></div><p>

2742

+ <a id="idm269999928112" class="indexterm"></a>

2743

+</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="strings.html#std.strings.string">String Classes</a></span></dt><dd><dl><dt><span class="section"><a href="strings.html#strings.string.simple">Simple Transformations</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.case">Case Sensitivity</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.character_types">Arbitrary Character Types</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.token">Tokenizing</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.shrink">Shrink to Fit</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.Cstring">CString (MFC)</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.strings.string"></a>String Classes</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="strings.string.simple"></a>Simple Transformations</h3></div></div></div><p>

2744

Here are Standard, simple, and portable ways to perform common

2745

transformations on a <code class="code">string</code> instance, such as

2746

"convert to all upper case." The word transformations

2747

Index: libstdc++-v3/doc/html/manual/containers_and_c.html

2748

===================================================================

2749

--- a/src/libstdc++-v3/doc/html/manual/containers_and_c.html (.../tags/gcc_4_8_2_release)

2750

+++ b/src/libstdc++-v3/doc/html/manual/containers_and_c.html (.../branches/gcc-4_8-branch)

2751

@@ -1,5 +1,5 @@

2752

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

2753

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Interacting with C</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="containers.html" title="Chapter 9. Containers" /><link rel="prev" href="unordered_associative.html" title="Unordered Associative" /><link rel="next" href="iterators.html" title="Chapter 10. Iterators" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Interacting with C</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="unordered_associative.html">Prev</a> </td><th width="60%" align="center">Chapter 9.

2754

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Interacting with C</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="containers.html" title="Chapter 9. Containers" /><link rel="prev" href="unordered_associative.html" title="Unordered Associative" /><link rel="next" href="iterators.html" title="Chapter 10. Iterators" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Interacting with C</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="unordered_associative.html">Prev</a> </td><th width="60%" align="center">Chapter 9.

2755

Containers

2756

2757

</th><td width="20%" align="right"> <a accesskey="n" href="iterators.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.containers.c"></a>Interacting with C</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="containers.c.vs_array"></a>Containers vs. Arrays</h3></div></div></div><p>

2758

Index: libstdc++-v3/doc/html/manual/profile_mode_diagnostics.html

2759

===================================================================

2760

--- a/src/libstdc++-v3/doc/html/manual/profile_mode_diagnostics.html (.../tags/gcc_4_8_2_release)

2761

+++ b/src/libstdc++-v3/doc/html/manual/profile_mode_diagnostics.html (.../branches/gcc-4_8-branch)

2762

@@ -1,5 +1,5 @@

2763

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

2764

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Diagnostics</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="prev" href="profile_mode_devel.html" title="Developer Information" /><link rel="next" href="mt_allocator.html" title="Chapter 20. The mt_allocator" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Diagnostics</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="profile_mode_devel.html">Prev</a> </td><th width="60%" align="center">Chapter 19. Profile Mode</th><td width="20%" align="right"> <a accesskey="n" href="mt_allocator.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.diagnostics"></a>Diagnostics</h2></div></div></div><p>

2765

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Diagnostics</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="prev" href="profile_mode_devel.html" title="Developer Information" /><link rel="next" href="mt_allocator.html" title="Chapter 20. The mt_allocator" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Diagnostics</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="profile_mode_devel.html">Prev</a> </td><th width="60%" align="center">Chapter 19. Profile Mode</th><td width="20%" align="right"> <a accesskey="n" href="mt_allocator.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.diagnostics"></a>Diagnostics</h2></div></div></div><p>

2766

The table below presents all the diagnostics we intend to implement.

2767

Each diagnostic has a corresponding compile time switch

2768

<code class="code">-D_GLIBCXX_PROFILE_<diagnostic></code>.

2769

@@ -17,7 +17,7 @@

2770

A high accuracy means that the diagnostic is unlikely to be wrong.

2771

These grades are not perfect. They are just meant to guide users with

2772

specific needs or time budgets.

2773

- </p><div class="table"><a id="idp17088912"></a><p class="title"><strong>Table 19.2. Profile Diagnostics</strong></p><div class="table-contents"><table summary="Profile Diagnostics" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /><col align="left" class="c6" /><col align="left" class="c7" /></colgroup><thead><tr><th align="left">Group</th><th align="left">Flag</th><th align="left">Benefit</th><th align="left">Cost</th><th align="left">Freq.</th><th align="left">Implemented</th><td class="auto-generated"> </td></tr></thead><tbody><tr><td align="left"><a class="link" href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.containers" title="Containers">

2774

+ </p><div class="table"><a id="idm269998442544"></a><p class="title"><strong>Table 19.2. Profile Diagnostics</strong></p><div class="table-contents"><table summary="Profile Diagnostics" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /><col align="left" class="c6" /><col align="left" class="c7" /></colgroup><thead><tr><th align="left">Group</th><th align="left">Flag</th><th align="left">Benefit</th><th align="left">Cost</th><th align="left">Freq.</th><th align="left">Implemented</th><td class="auto-generated"> </td></tr></thead><tbody><tr><td align="left"><a class="link" href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.containers" title="Containers">

2775

CONTAINERS</a></td><td align="left"><a class="link" href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.hashtable_too_small" title="Hashtable Too Small">

2776

HASHTABLE_TOO_SMALL</a></td><td align="left">10</td><td align="left">1</td><td align="left"> </td><td align="left">10</td><td align="left">yes</td></tr><tr><td align="left"> </td><td align="left"><a class="link" href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.hashtable_too_large" title="Hashtable Too Large">

2777

HASHTABLE_TOO_LARGE</a></td><td align="left">5</td><td align="left">1</td><td align="left"> </td><td align="left">10</td><td align="left">yes</td></tr><tr><td align="left"> </td><td align="left"><a class="link" href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.inefficient_hash" title="Inefficient Hash">

2778

@@ -374,7 +374,7 @@

2779

Quick Sort for a particular call context.

2780

</p></li><li class="listitem"><p><span class="emphasis"><em>Fundamentals:</em></span>

2781

See papers:

2782

- <a class="link" href="http://portal.acm.org/citation.cfm?doid=1065944.1065981" target="_top">

2783

+ <a class="link" href="https://dl.acm.org/citation.cfm?doid=1065944.1065981" target="_top">

2784

A framework for adaptive algorithm selection in STAPL</a> and

2785

2786

Optimizing Sorting with Machine Learning Algorithms</a>.

2787

@@ -500,7 +500,7 @@

2788

Keep a shadow for each container. Record iterator dereferences and

2789

container member accesses. Issue advice for elements referenced by

2790

multiple threads.

2791

- See paper: <a class="link" href="http://portal.acm.org/citation.cfm?id=207110.207148" target="_top">

2792

+ See paper: <a class="link" href="https://dl.acm.org/citation.cfm?id=207110.207148" target="_top">

2793

The LRPD test: speculative run-time parallelization of loops with

2794

privatization and reduction parallelization</a>.

2795

</p></li><li class="listitem"><p><span class="emphasis"><em>Cost model:</em></span>

2796

Index: libstdc++-v3/doc/html/manual/ext_concurrency_impl.html

2797

===================================================================

2798

--- a/src/libstdc++-v3/doc/html/manual/ext_concurrency_impl.html (.../tags/gcc_4_8_2_release)

2799

+++ b/src/libstdc++-v3/doc/html/manual/ext_concurrency_impl.html (.../branches/gcc-4_8-branch)

2800

@@ -1,5 +1,5 @@

2801

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

2802

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Implementation</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="ext_concurrency.html" title="Chapter 30. Concurrency" /><link rel="prev" href="ext_concurrency.html" title="Chapter 30. Concurrency" /><link rel="next" href="ext_concurrency_use.html" title="Use" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Implementation</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_concurrency.html">Prev</a> </td><th width="60%" align="center">Chapter 30. Concurrency</th><td width="20%" align="right"> <a accesskey="n" href="ext_concurrency_use.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.concurrency.impl"></a>Implementation</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.ext.concurrency.impl.atomic_fallbacks"></a>Using Builtin Atomic Functions</h3></div></div></div><p>The functions for atomic operations described above are either

2803

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Implementation</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="ext_concurrency.html" title="Chapter 30. Concurrency" /><link rel="prev" href="ext_concurrency.html" title="Chapter 30. Concurrency" /><link rel="next" href="ext_concurrency_use.html" title="Use" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Implementation</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_concurrency.html">Prev</a> </td><th width="60%" align="center">Chapter 30. Concurrency</th><td width="20%" align="right"> <a accesskey="n" href="ext_concurrency_use.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.concurrency.impl"></a>Implementation</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.ext.concurrency.impl.atomic_fallbacks"></a>Using Builtin Atomic Functions</h3></div></div></div><p>The functions for atomic operations described above are either

2804

implemented via compiler intrinsics (if the underlying host is

2805

capable) or by library fallbacks.</p><p>Compiler intrinsics (builtins) are always preferred. However, as

2806

the compiler builtins for atomics are not universally implemented,

2807

Index: libstdc++-v3/doc/html/manual/io_and_c.html

2808

===================================================================

2809

--- a/src/libstdc++-v3/doc/html/manual/io_and_c.html (.../tags/gcc_4_8_2_release)

2810

+++ b/src/libstdc++-v3/doc/html/manual/io_and_c.html (.../branches/gcc-4_8-branch)

2811

@@ -1,5 +1,5 @@

2812

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

2813

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Interacting with C</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="io.html" title="Chapter 13. Input and Output" /><link rel="prev" href="fstreams.html" title="File Based Streams" /><link rel="next" href="atomics.html" title="Chapter 14. Atomics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Interacting with C</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="fstreams.html">Prev</a> </td><th width="60%" align="center">Chapter 13.

2814

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Interacting with C</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="io.html" title="Chapter 13. Input and Output" /><link rel="prev" href="fstreams.html" title="File Based Streams" /><link rel="next" href="atomics.html" title="Chapter 14. Atomics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Interacting with C</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="fstreams.html">Prev</a> </td><th width="60%" align="center">Chapter 13.

2815

Input and Output

2816

2817

</th><td width="20%" align="right"> <a accesskey="n" href="atomics.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.io.c"></a>Interacting with C</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="std.io.c.FILE"></a>Using FILE* and file descriptors</h3></div></div></div><p>

2818

Index: libstdc++-v3/doc/html/manual/documentation_hacking.html

2819

===================================================================

2820

--- a/src/libstdc++-v3/doc/html/manual/documentation_hacking.html (.../tags/gcc_4_8_2_release)

2821

+++ b/src/libstdc++-v3/doc/html/manual/documentation_hacking.html (.../branches/gcc-4_8-branch)

2822

@@ -1,5 +1,5 @@

2823

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

2824

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Writing and Generating Documentation</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, documentation, style, docbook, doxygen" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B. Porting and Maintenance" /><link rel="prev" href="appendix_porting.html" title="Appendix B. Porting and Maintenance" /><link rel="next" href="internals.html" title="Porting to New Hardware or Operating Systems" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Writing and Generating Documentation</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="appendix_porting.html">Prev</a> </td><th width="60%" align="center">Appendix B.

2825

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Writing and Generating Documentation</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, documentation, style, docbook, doxygen" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B. Porting and Maintenance" /><link rel="prev" href="appendix_porting.html" title="Appendix B. Porting and Maintenance" /><link rel="next" href="internals.html" title="Porting to New Hardware or Operating Systems" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Writing and Generating Documentation</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="appendix_porting.html">Prev</a> </td><th width="60%" align="center">Appendix B.

2826

Porting and Maintenance

2827

2828

</th><td width="20%" align="right"> <a accesskey="n" href="internals.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="appendix.porting.doc"></a>Writing and Generating Documentation</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="doc.intro"></a>Introduction</h3></div></div></div><p>

2829

@@ -112,7 +112,7 @@

2830

supported, and are always aliased to dummy rules. These

2831

unsupported formats are: <span class="emphasis"><em>info</em></span>,

2832

<span class="emphasis"><em>ps</em></span>, and <span class="emphasis"><em>dvi</em></span>.

2833

- </p></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="doc.doxygen"></a>Doxygen</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="doxygen.prereq"></a>Prerequisites</h4></div></div></div><div class="table"><a id="idp22162432"></a><p class="title"><strong>Table B.1. Doxygen Prerequisites</strong></p><div class="table-contents"><table summary="Doxygen Prerequisites" border="1"><colgroup><col align="center" class="c1" /><col align="center" class="c2" /><col align="center" class="c3" /></colgroup><thead><tr><th align="center">Tool</th><th align="center">Version</th><th align="center">Required By</th></tr></thead><tbody><tr><td align="center">coreutils</td><td align="center">8.5</td><td align="center">all</td></tr><tr><td align="center">bash</td><td align="center">4.1</td><td align="center">all</td></tr><tr><td align="center">doxygen</td><td align="center">1.7.6.1</td><td align="center">all</td></tr><tr><td align="center">graphviz</td><td align="center">2.26</td><td align="center">graphical hierarchies</td></tr><tr><td align="center">pdflatex</td><td align="center">2007-59</td><td align="center">pdf output</td></tr></tbody></table></div></div><br class="table-break" /><p>

2834

+ </p></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="doc.doxygen"></a>Doxygen</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="doxygen.prereq"></a>Prerequisites</h4></div></div></div><div class="table"><a id="idm269993370272"></a><p class="title"><strong>Table B.1. Doxygen Prerequisites</strong></p><div class="table-contents"><table summary="Doxygen Prerequisites" border="1"><colgroup><col align="center" class="c1" /><col align="center" class="c2" /><col align="center" class="c3" /></colgroup><thead><tr><th align="center">Tool</th><th align="center">Version</th><th align="center">Required By</th></tr></thead><tbody><tr><td align="center">coreutils</td><td align="center">8.5</td><td align="center">all</td></tr><tr><td align="center">bash</td><td align="center">4.1</td><td align="center">all</td></tr><tr><td align="center">doxygen</td><td align="center">1.7.6.1</td><td align="center">all</td></tr><tr><td align="center">graphviz</td><td align="center">2.26</td><td align="center">graphical hierarchies</td></tr><tr><td align="center">pdflatex</td><td align="center">2007-59</td><td align="center">pdf output</td></tr></tbody></table></div></div><br class="table-break" /><p>

2835

Prerequisite tools are Bash 2.0 or later,

2836

<a class="link" href="http://www.doxygen.org/" target="_top">Doxygen</a>, and

2837

the <a class="link" href="http://www.gnu.org/software/coreutils/" target="_top">GNU

2838

@@ -232,9 +232,8 @@

2839

member functions.

2840

</p><p>

2841

Some commentary to accompany

2842

- the first list in the <a class="link" href="http://www.stack.nl/~dimitri/doxygen/docblocks.html" target="_top">Special

2843

- Documentation Blocks</a> section of

2844

- the Doxygen manual:

2845

+ the first list in the <a class="link" href="http://www.stack.nl/~dimitri/doxygen/manual/docblocks.html" target="_top">Special

2846

+ Documentation Blocks</a> section of the Doxygen manual:

2847

</p><div class="orderedlist"><ol class="orderedlist" type="1"><li class="listitem"><p>For longer comments, use the Javadoc style...</p></li><li class="listitem"><p>

2848

...not the Qt style. The intermediate *'s are preferred.

2849

</p></li><li class="listitem"><p>

2850

@@ -310,7 +309,7 @@

2851

writing Doxygen comments. Single and double quotes, and

2852

separators in filenames are two common trouble spots. When in

2853

doubt, consult the following table.

2854

- </p><div class="table"><a id="idp22238096"></a><p class="title"><strong>Table B.2. HTML to Doxygen Markup Comparison</strong></p><div class="table-contents"><table summary="HTML to Doxygen Markup Comparison" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><thead><tr><th align="left">HTML</th><th align="left">Doxygen</th></tr></thead><tbody><tr><td align="left">\</td><td align="left">\\</td></tr><tr><td align="left">"</td><td align="left">\"</td></tr><tr><td align="left">'</td><td align="left">\'</td></tr><tr><td align="left"><i></td><td align="left">@a word</td></tr><tr><td align="left"><b></td><td align="left">@b word</td></tr><tr><td align="left"><code></td><td align="left">@c word</td></tr><tr><td align="left"><em></td><td align="left">@a word</td></tr><tr><td align="left"><em></td><td align="left"><em>two words or more</em></td></tr></tbody></table></div></div><br class="table-break" /></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="doc.docbook"></a>Docbook</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="docbook.prereq"></a>Prerequisites</h4></div></div></div><div class="table"><a id="idp22257536"></a><p class="title"><strong>Table B.3. Docbook Prerequisites</strong></p><div class="table-contents"><table summary="Docbook Prerequisites" border="1"><colgroup><col align="center" class="c1" /><col align="center" class="c2" /><col align="center" class="c3" /></colgroup><thead><tr><th align="center">Tool</th><th align="center">Version</th><th align="center">Required By</th></tr></thead><tbody><tr><td align="center">docbook5-style-xsl</td><td align="center">1.76.1</td><td align="center">all</td></tr><tr><td align="center">xsltproc</td><td align="center">1.1.26</td><td align="center">all</td></tr><tr><td align="center">xmllint</td><td align="center">2.7.7</td><td align="center">validation</td></tr><tr><td align="center">dblatex</td><td align="center">0.3</td><td align="center">pdf output</td></tr><tr><td align="center">pdflatex</td><td align="center">2007-59</td><td align="center">pdf output</td></tr><tr><td align="center">docbook2X</td><td align="center">0.8.8</td><td align="center">info output</td></tr><tr><td align="center">epub3 stylesheets</td><td align="center">b3</td><td align="center">epub output</td></tr></tbody></table></div></div><br class="table-break" /><p>

2855

+ </p><div class="table"><a id="idm269993294592"></a><p class="title"><strong>Table B.2. HTML to Doxygen Markup Comparison</strong></p><div class="table-contents"><table summary="HTML to Doxygen Markup Comparison" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><thead><tr><th align="left">HTML</th><th align="left">Doxygen</th></tr></thead><tbody><tr><td align="left">\</td><td align="left">\\</td></tr><tr><td align="left">"</td><td align="left">\"</td></tr><tr><td align="left">'</td><td align="left">\'</td></tr><tr><td align="left"><i></td><td align="left">@a word</td></tr><tr><td align="left"><b></td><td align="left">@b word</td></tr><tr><td align="left"><code></td><td align="left">@c word</td></tr><tr><td align="left"><em></td><td align="left">@a word</td></tr><tr><td align="left"><em></td><td align="left"><em>two words or more</em></td></tr></tbody></table></div></div><br class="table-break" /></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="doc.docbook"></a>Docbook</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="docbook.prereq"></a>Prerequisites</h4></div></div></div><div class="table"><a id="idm269993275152"></a><p class="title"><strong>Table B.3. Docbook Prerequisites</strong></p><div class="table-contents"><table summary="Docbook Prerequisites" border="1"><colgroup><col align="center" class="c1" /><col align="center" class="c2" /><col align="center" class="c3" /></colgroup><thead><tr><th align="center">Tool</th><th align="center">Version</th><th align="center">Required By</th></tr></thead><tbody><tr><td align="center">docbook5-style-xsl</td><td align="center">1.76.1</td><td align="center">all</td></tr><tr><td align="center">xsltproc</td><td align="center">1.1.26</td><td align="center">all</td></tr><tr><td align="center">xmllint</td><td align="center">2.7.7</td><td align="center">validation</td></tr><tr><td align="center">dblatex</td><td align="center">0.3</td><td align="center">pdf output</td></tr><tr><td align="center">pdflatex</td><td align="center">2007-59</td><td align="center">pdf output</td></tr><tr><td align="center">docbook2X</td><td align="center">0.8.8</td><td align="center">info output</td></tr><tr><td align="center">epub3 stylesheets</td><td align="center">b3</td><td align="center">epub output</td></tr></tbody></table></div></div><br class="table-break" /><p>

2856

Editing the DocBook sources requires an XML editor. Many

2857

exist: some notable options

2858

include <span class="command"><strong>emacs</strong></span>, <span class="application">Kate</span>,

2859

@@ -520,11 +519,11 @@

2860

<a class="link" href="http://www.docbook.org/tdg/en/html/part2.html" target="_top">online</a>.

2861

An incomplete reference for HTML to Docbook conversion is

2862

detailed in the table below.

2863

- </p><div class="table"><a id="idp22335040"></a><p class="title"><strong>Table B.4. HTML to Docbook XML Markup Comparison</strong></p><div class="table-contents"><table summary="HTML to Docbook XML Markup Comparison" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><thead><tr><th align="left">HTML</th><th align="left">Docbook</th></tr></thead><tbody><tr><td align="left"><p></td><td align="left"><para></td></tr><tr><td align="left"><pre></td><td align="left"><computeroutput>, <programlisting>,

2864

+ </p><div class="table"><a id="idm269993197520"></a><p class="title"><strong>Table B.4. HTML to Docbook XML Markup Comparison</strong></p><div class="table-contents"><table summary="HTML to Docbook XML Markup Comparison" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><thead><tr><th align="left">HTML</th><th align="left">Docbook</th></tr></thead><tbody><tr><td align="left"><p></td><td align="left"><para></td></tr><tr><td align="left"><pre></td><td align="left"><computeroutput>, <programlisting>,

2865

2866

And examples of detailed markup for which there are no real HTML

2867

equivalents are listed in the table below.

2868

-</p><div class="table"><a id="idp22359184"></a><p class="title"><strong>Table B.5. Docbook XML Element Use</strong></p><div class="table-contents"><table summary="Docbook XML Element Use" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><thead><tr><th align="left">Element</th><th align="left">Use</th></tr></thead><tbody><tr><td align="left"><structname></td><td align="left"><structname>char_traits</structname></td></tr><tr><td align="left"><classname></td><td align="left"><classname>string</classname></td></tr><tr><td align="left"><function></td><td align="left">

2869

+</p><div class="table"><a id="idm269993173376"></a><p class="title"><strong>Table B.5. Docbook XML Element Use</strong></p><div class="table-contents"><table summary="Docbook XML Element Use" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><thead><tr><th align="left">Element</th><th align="left">Use</th></tr></thead><tbody><tr><td align="left"><structname></td><td align="left"><structname>char_traits</structname></td></tr><tr><td align="left"><classname></td><td align="left"><classname>string</classname></td></tr><tr><td align="left"><function></td><td align="left">

2870

<p><function>clear()</function></p>

2871

<p><function>fs.clear()</function></p>

2872

</td></tr><tr><td align="left"><type></td><td align="left"><type>long long</type></td></tr><tr><td align="left"><varname></td><td align="left"><varname>fs</varname></td></tr><tr><td align="left"><literal></td><td align="left">

2873

Index: libstdc++-v3/doc/html/manual/extensions.html

2874

===================================================================

2875

--- a/src/libstdc++-v3/doc/html/manual/extensions.html (.../tags/gcc_4_8_2_release)

2876

+++ b/src/libstdc++-v3/doc/html/manual/extensions.html (.../branches/gcc-4_8-branch)

2877

@@ -1,11 +1,11 @@

2878

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

2879

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Part III. Extensions</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="index.html" title="The GNU C++ Library Manual" /><link rel="prev" href="io_and_c.html" title="Interacting with C" /><link rel="next" href="ext_preface.html" title="" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Part III.

2880

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Part III. Extensions</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="index.html" title="The GNU C++ Library Manual" /><link rel="prev" href="io_and_c.html" title="Interacting with C" /><link rel="next" href="ext_preface.html" title="" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Part III.

2881

Extensions

2882

2883

</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="io_and_c.html">Prev</a> </td><th width="60%" align="center">The GNU C++ Library Manual</th><td width="20%" align="right"> <a accesskey="n" href="ext_preface.html">Next</a></td></tr></table><hr /></div><div class="part"><div class="titlepage"><div><div><h1 class="title"><a id="manual.ext"></a>Part III.

2884

Extensions

2885

- <a id="idp16423680" class="indexterm"></a>

2886

-</h1></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="preface"><a href="ext_preface.html"></a></span></dt><dt><span class="chapter"><a href="ext_compile_checks.html">16. Compile Time Checks</a></span></dt><dt><span class="chapter"><a href="debug_mode.html">17. Debug Mode</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode.html#manual.ext.debug_mode.intro">Intro</a></span></dt><dt><span class="section"><a href="debug_mode_semantics.html">Semantics</a></span></dt><dt><span class="section"><a href="debug_mode_using.html">Using</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_using.html#debug_mode.using.mode">Using the Debug Mode</a></span></dt><dt><span class="section"><a href="debug_mode_using.html#debug_mode.using.specific">Using a Specific Debug Container</a></span></dt></dl></dd><dt><span class="section"><a href="debug_mode_design.html">Design</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.goals">Goals</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods">Methods</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.wrappers">The Wrapper Model</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.safe_iter">Safe Iterators</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.safe_seq">Safe Sequences (Containers)</a></span></dt></dl></dd><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.precond">Precondition Checking</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.coexistence">Release- and debug-mode coexistence</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#methods.coexistence.compile">Compile-time coexistence of release- and debug-mode components</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#methods.coexistence.link">Link- and run-time coexistence of release- and

2887

+ <a id="idm269999107536" class="indexterm"></a>

2888

+</h1></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="preface"><a href="ext_preface.html"></a></span></dt><dt><span class="chapter"><a href="ext_compile_checks.html">16. Compile Time Checks</a></span></dt><dt><span class="chapter"><a href="debug_mode.html">17. Debug Mode</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode.html#manual.ext.debug_mode.intro">Intro</a></span></dt><dt><span class="section"><a href="debug_mode_semantics.html">Semantics</a></span></dt><dt><span class="section"><a href="debug_mode_using.html">Using</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_using.html#debug_mode.using.mode">Using the Debug Mode</a></span></dt><dt><span class="section"><a href="debug_mode_using.html#debug_mode.using.specific">Using a Specific Debug Container</a></span></dt></dl></dd><dt><span class="section"><a href="debug_mode_design.html">Design</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.goals">Goals</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods">Methods</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.wrappers">The Wrapper Model</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.safe_iter">Safe Iterators</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.safe_seq">Safe Sequences (Containers)</a></span></dt></dl></dd><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.precond">Precondition Checking</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.coexistence">Release- and debug-mode coexistence</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#methods.coexistence.compile">Compile-time coexistence of release- and debug-mode components</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#methods.coexistence.link">Link- and run-time coexistence of release- and

2889

debug-mode components</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#methods.coexistence.alt">Alternatives for Coexistence</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.other">Other Implementations</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="parallel_mode.html">18. Parallel Mode</a></span></dt><dd><dl><dt><span class="section"><a href="parallel_mode.html#manual.ext.parallel_mode.intro">Intro</a></span></dt><dt><span class="section"><a href="parallel_mode_semantics.html">Semantics</a></span></dt><dt><span class="section"><a href="parallel_mode_using.html">Using</a></span></dt><dd><dl><dt><span class="section"><a href="parallel_mode_using.html#parallel_mode.using.prereq_flags">Prerequisite Compiler Flags</a></span></dt><dt><span class="section"><a href="parallel_mode_using.html#parallel_mode.using.parallel_mode">Using Parallel Mode</a></span></dt><dt><span class="section"><a href="parallel_mode_using.html#parallel_mode.using.specific">Using Specific Parallel Components</a></span></dt></dl></dd><dt><span class="section"><a href="parallel_mode_design.html">Design</a></span></dt><dd><dl><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.intro">Interface Basics</a></span></dt><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.tuning">Configuration and Tuning</a></span></dt><dd><dl><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.tuning.omp">Setting up the OpenMP Environment</a></span></dt><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.tuning.compile">Compile Time Switches</a></span></dt><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.tuning.settings">Run Time Settings and Defaults</a></span></dt></dl></dd><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.impl">Implementation Namespaces</a></span></dt></dl></dd><dt><span class="section"><a href="parallel_mode_test.html">Testing</a></span></dt><dt><span class="bibliography"><a href="parallel_mode.html#parallel_mode.biblio">Bibliography</a></span></dt></dl></dd><dt><span class="chapter"><a href="profile_mode.html">19. Profile Mode</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode.html#manual.ext.profile_mode.intro">Intro</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode.html#manual.ext.profile_mode.using">Using the Profile Mode</a></span></dt><dt><span class="section"><a href="profile_mode.html#manual.ext.profile_mode.tuning">Tuning the Profile Mode</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_design.html">Design</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.wrapper">Wrapper Model</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.instrumentation">Instrumentation</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.rtlib">Run Time Behavior</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.analysis">Analysis and Diagnostics</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.cost-model">Cost Model</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.reports">Reports</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.testing">Testing</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_api.html">Extensions for Custom Containers</a></span></dt><dt><span class="section"><a href="profile_mode_cost_model.html">Empirical Cost Model</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html">Implementation Issues</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.stack">Stack Traces</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.symbols">Symbolization of Instruction Addresses</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.concurrency">Concurrency</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.stdlib-in-proflib">Using the Standard Library in the Instrumentation Implementation</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.malloc-hooks">Malloc Hooks</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.construction-destruction">Construction and Destruction of Global Objects</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_devel.html">Developer Information</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_devel.html#manual.ext.profile_mode.developer.bigpic">Big Picture</a></span></dt><dt><span class="section"><a href="profile_mode_devel.html#manual.ext.profile_mode.developer.howto">How To Add A Diagnostic</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html">Diagnostics</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.template">Diagnostic Template</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.containers">Containers</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.hashtable_too_small">Hashtable Too Small</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.hashtable_too_large">Hashtable Too Large</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.inefficient_hash">Inefficient Hash</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.vector_too_small">Vector Too Small</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.vector_too_large">Vector Too Large</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.vector_to_hashtable">Vector to Hashtable</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.hashtable_to_vector">Hashtable to Vector</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.vector_to_list">Vector to List</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.list_to_vector">List to Vector</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.list_to_slist">List to Forward List (Slist)</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.assoc_ord_to_unord">Ordered to Unordered Associative Container</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.algorithms">Algorithms</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.algorithms.sort">Sort Algorithm Performance</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.locality">Data Locality</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.locality.sw_prefetch">Need Software Prefetch</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.locality.linked">Linked Structure Locality</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.mthread">Multithreaded Data Access</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.mthread.ddtest">Data Dependence Violations at Container Level</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.mthread.false_share">False Sharing</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.statistics">Statistics</a></span></dt></dl></dd><dt><span class="bibliography"><a href="profile_mode.html#profile_mode.biblio">Bibliography</a></span></dt></dl></dd><dt><span class="chapter"><a href="mt_allocator.html">20. The mt_allocator</a></span></dt><dd><dl><dt><span class="section"><a href="mt_allocator.html#allocator.mt.intro">Intro</a></span></dt><dt><span class="section"><a href="mt_allocator_design.html">Design Issues</a></span></dt><dd><dl><dt><span class="section"><a href="mt_allocator_design.html#allocator.mt.overview">Overview</a></span></dt></dl></dd><dt><span class="section"><a href="mt_allocator_impl.html">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="mt_allocator_impl.html#allocator.mt.tune">Tunable Parameters</a></span></dt><dt><span class="section"><a href="mt_allocator_impl.html#allocator.mt.init">Initialization</a></span></dt><dt><span class="section"><a href="mt_allocator_impl.html#allocator.mt.deallocation">Deallocation Notes</a></span></dt></dl></dd><dt><span class="section"><a href="mt_allocator_ex_single.html">Single Thread Example</a></span></dt><dt><span class="section"><a href="mt_allocator_ex_multi.html">Multiple Thread Example</a></span></dt></dl></dd><dt><span class="chapter"><a href="bitmap_allocator.html">21. The bitmap_allocator</a></span></dt><dd><dl><dt><span class="section"><a href="bitmap_allocator.html#allocator.bitmap.design">Design</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.free_list_store">Free List Store</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.super_block">Super Block</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.super_block_data">Super Block Data Layout</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.max_wasted">Maximum Wasted Percentage</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.allocate"><code class="function">allocate</code></a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.deallocate"><code class="function">deallocate</code></a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.questions">Questions</a></span></dt><dd><dl><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.question.1">1</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.question.2">2</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.question.3">3</a></span></dt></dl></dd><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.locality">Locality</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.grow_policy">Overhead and Grow Policy</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="policy_data_structures.html">22. Policy-Based Data Structures</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#pbds.intro">Intro</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.issues">Performance Issues</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.issues.associative">Associative</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.issues.priority_queue">Priority Que</a></span></dt></dl></dd><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.motivation">Goals</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.motivation.associative">Associative</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#motivation.associative.policy">Policy Choices</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.associative.underlying">Underlying Data Structures</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.associative.iterators">Iterators</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.associative.functions">Functional</a></span></dt></dl></dd><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.motivation.priority_queue">Priority Queues</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#motivation.priority_queue.policy">Policy Choices</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.priority_queue.underlying">Underlying Data Structures</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.priority_queue.binary_heap">Binary Heaps</a></span></dt></dl></dd></dl></dd></dl></dd><dt><span class="section"><a href="policy_data_structures_using.html">Using</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.organization">Organization</a></span></dt><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.tutorial">Tutorial</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.tutorial.basic">Basic Use</a></span></dt><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.tutorial.configuring">

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Configuring via Template Parameters

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</a></span></dt><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.tutorial.traits">

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>

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-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Using</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="C++, library, debug" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="debug_mode.html" title="Chapter 17. Debug Mode" /><link rel="prev" href="debug_mode_semantics.html" title="Semantics" /><link rel="next" href="debug_mode_design.html" title="Design" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Using</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="debug_mode_semantics.html">Prev</a> </td><th width="60%" align="center">Chapter 17. Debug Mode</th><td width="20%" align="right"> <a accesskey="n" href="debug_mode_design.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.debug_mode.using"></a>Using</h2></div></div></div><p>

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Using</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, debug" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="debug_mode.html" title="Chapter 17. Debug Mode" /><link rel="prev" href="debug_mode_semantics.html" title="Semantics" /><link rel="next" href="debug_mode_design.html" title="Design" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Using</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="debug_mode_semantics.html">Prev</a> </td><th width="60%" align="center">Chapter 17. Debug Mode</th><td width="20%" align="right"> <a accesskey="n" href="debug_mode_design.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.debug_mode.using"></a>Using</h2></div></div></div><p>

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</p><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="debug_mode.using.mode"></a>Using the Debug Mode</h3></div></div></div><p>To use the libstdc++ debug mode, compile your application with the

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compiler flag <code class="code">-D_GLIBCXX_DEBUG</code>. Note that this flag

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changes the sizes and behavior of standard class templates such

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@@ -18,6 +18,6 @@

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mode or with debug mode. The

2905

following table provides the names and headers of the debugging

2906

containers:

2907

-</p><div class="table"><a id="idp16490400"></a><p class="title"><strong>Table 17.1. Debugging Containers</strong></p><div class="table-contents"><table summary="Debugging Containers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Container</th><th align="left">Header</th><th align="left">Debug container</th><th align="left">Debug header</th></tr></thead><tbody><tr><td align="left"><code class="classname">std::bitset</code></td><td align="left"><code class="filename">bitset</code></td><td align="left"><code class="classname">__gnu_debug::bitset</code></td><td align="left"><code class="filename"><debug/bitset></code></td></tr><tr><td align="left"><code class="classname">std::deque</code></td><td align="left"><code class="filename">deque</code></td><td align="left"><code class="classname">__gnu_debug::deque</code></td><td align="left"><code class="filename"><debug/deque></code></td></tr><tr><td align="left"><code class="classname">std::list</code></td><td align="left"><code class="filename">list</code></td><td align="left"><code class="classname">__gnu_debug::list</code></td><td align="left"><code class="filename"><debug/list></code></td></tr><tr><td align="left"><code class="classname">std::map</code></td><td align="left"><code class="filename">map</code></td><td align="left"><code class="classname">__gnu_debug::map</code></td><td align="left"><code class="filename"><debug/map></code></td></tr><tr><td align="left"><code class="classname">std::multimap</code></td><td align="left"><code class="filename">map</code></td><td align="left"><code class="classname">__gnu_debug::multimap</code></td><td align="left"><code class="filename"><debug/map></code></td></tr><tr><td align="left"><code class="classname">std::multiset</code></td><td align="left"><code class="filename">set</code></td><td align="left"><code class="classname">__gnu_debug::multiset</code></td><td align="left"><code class="filename"><debug/set></code></td></tr><tr><td align="left"><code class="classname">std::set</code></td><td align="left"><code class="filename">set</code></td><td align="left"><code class="classname">__gnu_debug::set</code></td><td align="left"><code class="filename"><debug/set></code></td></tr><tr><td align="left"><code class="classname">std::string</code></td><td align="left"><code class="filename">string</code></td><td align="left"><code class="classname">__gnu_debug::string</code></td><td align="left"><code class="filename"><debug/string></code></td></tr><tr><td align="left"><code class="classname">std::wstring</code></td><td align="left"><code class="filename">string</code></td><td align="left"><code class="classname">__gnu_debug::wstring</code></td><td align="left"><code class="filename"><debug/string></code></td></tr><tr><td align="left"><code class="classname">std::basic_string</code></td><td align="left"><code class="filename">string</code></td><td align="left"><code class="classname">__gnu_debug::basic_string</code></td><td align="left"><code class="filename"><debug/string></code></td></tr><tr><td align="left"><code class="classname">std::vector</code></td><td align="left"><code class="filename">vector</code></td><td align="left"><code class="classname">__gnu_debug::vector</code></td><td align="left"><code class="filename"><debug/vector></code></td></tr></tbody></table></div></div><br class="table-break" /><p>In addition, when compiling in C++11 mode, these additional

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+</p><div class="table"><a id="idm269999040896"></a><p class="title"><strong>Table 17.1. Debugging Containers</strong></p><div class="table-contents"><table summary="Debugging Containers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Container</th><th align="left">Header</th><th align="left">Debug container</th><th align="left">Debug header</th></tr></thead><tbody><tr><td align="left"><code class="classname">std::bitset</code></td><td align="left"><code class="filename">bitset</code></td><td align="left"><code class="classname">__gnu_debug::bitset</code></td><td align="left"><code class="filename"><debug/bitset></code></td></tr><tr><td align="left"><code class="classname">std::deque</code></td><td align="left"><code class="filename">deque</code></td><td align="left"><code class="classname">__gnu_debug::deque</code></td><td align="left"><code class="filename"><debug/deque></code></td></tr><tr><td align="left"><code class="classname">std::list</code></td><td align="left"><code class="filename">list</code></td><td align="left"><code class="classname">__gnu_debug::list</code></td><td align="left"><code class="filename"><debug/list></code></td></tr><tr><td align="left"><code class="classname">std::map</code></td><td align="left"><code class="filename">map</code></td><td align="left"><code class="classname">__gnu_debug::map</code></td><td align="left"><code class="filename"><debug/map></code></td></tr><tr><td align="left"><code class="classname">std::multimap</code></td><td align="left"><code class="filename">map</code></td><td align="left"><code class="classname">__gnu_debug::multimap</code></td><td align="left"><code class="filename"><debug/map></code></td></tr><tr><td align="left"><code class="classname">std::multiset</code></td><td align="left"><code class="filename">set</code></td><td align="left"><code class="classname">__gnu_debug::multiset</code></td><td align="left"><code class="filename"><debug/set></code></td></tr><tr><td align="left"><code class="classname">std::set</code></td><td align="left"><code class="filename">set</code></td><td align="left"><code class="classname">__gnu_debug::set</code></td><td align="left"><code class="filename"><debug/set></code></td></tr><tr><td align="left"><code class="classname">std::string</code></td><td align="left"><code class="filename">string</code></td><td align="left"><code class="classname">__gnu_debug::string</code></td><td align="left"><code class="filename"><debug/string></code></td></tr><tr><td align="left"><code class="classname">std::wstring</code></td><td align="left"><code class="filename">string</code></td><td align="left"><code class="classname">__gnu_debug::wstring</code></td><td align="left"><code class="filename"><debug/string></code></td></tr><tr><td align="left"><code class="classname">std::basic_string</code></td><td align="left"><code class="filename">string</code></td><td align="left"><code class="classname">__gnu_debug::basic_string</code></td><td align="left"><code class="filename"><debug/string></code></td></tr><tr><td align="left"><code class="classname">std::vector</code></td><td align="left"><code class="filename">vector</code></td><td align="left"><code class="classname">__gnu_debug::vector</code></td><td align="left"><code class="filename"><debug/vector></code></td></tr></tbody></table></div></div><br class="table-break" /><p>In addition, when compiling in C++11 mode, these additional

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containers have additional debug capability.

2910

-</p><div class="table"><a id="idp16535296"></a><p class="title"><strong>Table 17.2. Debugging Containers C++11</strong></p><div class="table-contents"><table summary="Debugging Containers C++11" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Container</th><th align="left">Header</th><th align="left">Debug container</th><th align="left">Debug header</th></tr></thead><tbody><tr><td align="left"><code class="classname">std::unordered_map</code></td><td align="left"><code class="filename">unordered_map</code></td><td align="left"><code class="classname">__gnu_debug::unordered_map</code></td><td align="left"><code class="filename"><debug/unordered_map></code></td></tr><tr><td align="left"><code class="classname">std::unordered_multimap</code></td><td align="left"><code class="filename">unordered_map</code></td><td align="left"><code class="classname">__gnu_debug::unordered_multimap</code></td><td align="left"><code class="filename"><debug/unordered_map></code></td></tr><tr><td align="left"><code class="classname">std::unordered_set</code></td><td align="left"><code class="filename">unordered_set</code></td><td align="left"><code class="classname">__gnu_debug::unordered_set</code></td><td align="left"><code class="filename"><debug/unordered_set></code></td></tr><tr><td align="left"><code class="classname">std::unordered_multiset</code></td><td align="left"><code class="filename">unordered_set</code></td><td align="left"><code class="classname">__gnu_debug::unordered_multiset</code></td><td align="left"><code class="filename"><debug/unordered_set></code></td></tr></tbody></table></div></div><br class="table-break" /></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="debug_mode_semantics.html">Prev</a> </td><td width="20%" align="center"><a accesskey="u" href="debug_mode.html">Up</a></td><td width="40%" align="right"> <a accesskey="n" href="debug_mode_design.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">Semantics </td><td width="20%" align="center"><a accesskey="h" href="../index.html">Home</a></td><td width="40%" align="right" valign="top"> Design</td></tr></table></div></body></html>

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\ No newline at end of file

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+</p><div class="table"><a id="idm269998996000"></a><p class="title"><strong>Table 17.2. Debugging Containers C++11</strong></p><div class="table-contents"><table summary="Debugging Containers C++11" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Container</th><th align="left">Header</th><th align="left">Debug container</th><th align="left">Debug header</th></tr></thead><tbody><tr><td align="left"><code class="classname">std::unordered_map</code></td><td align="left"><code class="filename">unordered_map</code></td><td align="left"><code class="classname">__gnu_debug::unordered_map</code></td><td align="left"><code class="filename"><debug/unordered_map></code></td></tr><tr><td align="left"><code class="classname">std::unordered_multimap</code></td><td align="left"><code class="filename">unordered_map</code></td><td align="left"><code class="classname">__gnu_debug::unordered_multimap</code></td><td align="left"><code class="filename"><debug/unordered_map></code></td></tr><tr><td align="left"><code class="classname">std::unordered_set</code></td><td align="left"><code class="filename">unordered_set</code></td><td align="left"><code class="classname">__gnu_debug::unordered_set</code></td><td align="left"><code class="filename"><debug/unordered_set></code></td></tr><tr><td align="left"><code class="classname">std::unordered_multiset</code></td><td align="left"><code class="filename">unordered_set</code></td><td align="left"><code class="classname">__gnu_debug::unordered_multiset</code></td><td align="left"><code class="filename"><debug/unordered_set></code></td></tr></tbody></table></div></div><br class="table-break" /></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="debug_mode_semantics.html">Prev</a> </td><td width="20%" align="center"><a accesskey="u" href="debug_mode.html">Up</a></td><td width="40%" align="right"> <a accesskey="n" href="debug_mode_design.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">Semantics </td><td width="20%" align="center"><a accesskey="h" href="../index.html">Home</a></td><td width="40%" align="right" valign="top"> Design</td></tr></table></div></body></html>

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>

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-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 18. Parallel Mode</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="C++, library, parallel" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III. Extensions" /><link rel="prev" href="debug_mode_design.html" title="Design" /><link rel="next" href="parallel_mode_semantics.html" title="Semantics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 18. Parallel Mode</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="debug_mode_design.html">Prev</a> </td><th width="60%" align="center">Part III.

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 18. Parallel Mode</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, parallel" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III. Extensions" /><link rel="prev" href="debug_mode_design.html" title="Design" /><link rel="next" href="parallel_mode_semantics.html" title="Semantics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 18. Parallel Mode</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="debug_mode_design.html">Prev</a> </td><th width="60%" align="center">Part III.

2922

Extensions

2923

2924

-</th><td width="20%" align="right"> <a accesskey="n" href="parallel_mode_semantics.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.parallel_mode"></a>Chapter 18. Parallel Mode</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="parallel_mode.html#manual.ext.parallel_mode.intro">Intro</a></span></dt><dt><span class="section"><a href="parallel_mode_semantics.html">Semantics</a></span></dt><dt><span class="section"><a href="parallel_mode_using.html">Using</a></span></dt><dd><dl><dt><span class="section"><a href="parallel_mode_using.html#parallel_mode.using.prereq_flags">Prerequisite Compiler Flags</a></span></dt><dt><span class="section"><a href="parallel_mode_using.html#parallel_mode.using.parallel_mode">Using Parallel Mode</a></span></dt><dt><span class="section"><a href="parallel_mode_using.html#parallel_mode.using.specific">Using Specific Parallel Components</a></span></dt></dl></dd><dt><span class="section"><a href="parallel_mode_design.html">Design</a></span></dt><dd><dl><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.intro">Interface Basics</a></span></dt><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.tuning">Configuration and Tuning</a></span></dt><dd><dl><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.tuning.omp">Setting up the OpenMP Environment</a></span></dt><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.tuning.compile">Compile Time Switches</a></span></dt><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.tuning.settings">Run Time Settings and Defaults</a></span></dt></dl></dd><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.impl">Implementation Namespaces</a></span></dt></dl></dd><dt><span class="section"><a href="parallel_mode_test.html">Testing</a></span></dt><dt><span class="bibliography"><a href="parallel_mode.html#parallel_mode.biblio">Bibliography</a></span></dt></dl></div><p> The libstdc++ parallel mode is an experimental parallel

2925

+</th><td width="20%" align="right"> <a accesskey="n" href="parallel_mode_semantics.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.parallel_mode"></a>Chapter 18. Parallel Mode</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="parallel_mode.html#manual.ext.parallel_mode.intro">Intro</a></span></dt><dt><span class="section"><a href="parallel_mode_semantics.html">Semantics</a></span></dt><dt><span class="section"><a href="parallel_mode_using.html">Using</a></span></dt><dd><dl><dt><span class="section"><a href="parallel_mode_using.html#parallel_mode.using.prereq_flags">Prerequisite Compiler Flags</a></span></dt><dt><span class="section"><a href="parallel_mode_using.html#parallel_mode.using.parallel_mode">Using Parallel Mode</a></span></dt><dt><span class="section"><a href="parallel_mode_using.html#parallel_mode.using.specific">Using Specific Parallel Components</a></span></dt></dl></dd><dt><span class="section"><a href="parallel_mode_design.html">Design</a></span></dt><dd><dl><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.intro">Interface Basics</a></span></dt><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.tuning">Configuration and Tuning</a></span></dt><dd><dl><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.tuning.omp">Setting up the OpenMP Environment</a></span></dt><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.tuning.compile">Compile Time Switches</a></span></dt><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.tuning.settings">Run Time Settings and Defaults</a></span></dt></dl></dd><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.impl">Implementation Namespaces</a></span></dt></dl></dd><dt><span class="section"><a href="parallel_mode_test.html">Testing</a></span></dt><dt><span class="bibliography"><a href="parallel_mode.html#parallel_mode.biblio">Bibliography</a></span></dt></dl></div><p> The libstdc++ parallel mode is an experimental parallel

2926

implementation of many algorithms the C++ Standard Library.

2927

</p><p>

2928

Several of the standard algorithms, for instance

2929

@@ -12,11 +12,11 @@

2930

specific compiler flag.

2931

</p><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.parallel_mode.intro"></a>Intro</h2></div></div></div><p>The following library components in the include

2932

<code class="filename">numeric</code> are included in the parallel mode:</p><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p><code class="function">std::accumulate</code></p></li><li class="listitem"><p><code class="function">std::adjacent_difference</code></p></li><li class="listitem"><p><code class="function">std::inner_product</code></p></li><li class="listitem"><p><code class="function">std::partial_sum</code></p></li></ul></div><p>The following library components in the include

2933

-<code class="filename">algorithm</code> are included in the parallel mode:</p><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p><code class="function">std::adjacent_find</code></p></li><li class="listitem"><p><code class="function">std::count</code></p></li><li class="listitem"><p><code class="function">std::count_if</code></p></li><li class="listitem"><p><code class="function">std::equal</code></p></li><li class="listitem"><p><code class="function">std::find</code></p></li><li class="listitem"><p><code class="function">std::find_if</code></p></li><li class="listitem"><p><code class="function">std::find_first_of</code></p></li><li class="listitem"><p><code class="function">std::for_each</code></p></li><li class="listitem"><p><code class="function">std::generate</code></p></li><li class="listitem"><p><code class="function">std::generate_n</code></p></li><li class="listitem"><p><code class="function">std::lexicographical_compare</code></p></li><li class="listitem"><p><code class="function">std::mismatch</code></p></li><li class="listitem"><p><code class="function">std::search</code></p></li><li class="listitem"><p><code class="function">std::search_n</code></p></li><li class="listitem"><p><code class="function">std::transform</code></p></li><li class="listitem"><p><code class="function">std::replace</code></p></li><li class="listitem"><p><code class="function">std::replace_if</code></p></li><li class="listitem"><p><code class="function">std::max_element</code></p></li><li class="listitem"><p><code class="function">std::merge</code></p></li><li class="listitem"><p><code class="function">std::min_element</code></p></li><li class="listitem"><p><code class="function">std::nth_element</code></p></li><li class="listitem"><p><code class="function">std::partial_sort</code></p></li><li class="listitem"><p><code class="function">std::partition</code></p></li><li class="listitem"><p><code class="function">std::random_shuffle</code></p></li><li class="listitem"><p><code class="function">std::set_union</code></p></li><li class="listitem"><p><code class="function">std::set_intersection</code></p></li><li class="listitem"><p><code class="function">std::set_symmetric_difference</code></p></li><li class="listitem"><p><code class="function">std::set_difference</code></p></li><li class="listitem"><p><code class="function">std::sort</code></p></li><li class="listitem"><p><code class="function">std::stable_sort</code></p></li><li class="listitem"><p><code class="function">std::unique_copy</code></p></li></ul></div></div><div class="bibliography"><div class="titlepage"><div><div><h2 class="title"><a id="parallel_mode.biblio"></a>Bibliography</h2></div></div></div><div class="biblioentry"><a id="idp16926864"></a><p><span class="citetitle"><em class="citetitle">

2934

+<code class="filename">algorithm</code> are included in the parallel mode:</p><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p><code class="function">std::adjacent_find</code></p></li><li class="listitem"><p><code class="function">std::count</code></p></li><li class="listitem"><p><code class="function">std::count_if</code></p></li><li class="listitem"><p><code class="function">std::equal</code></p></li><li class="listitem"><p><code class="function">std::find</code></p></li><li class="listitem"><p><code class="function">std::find_if</code></p></li><li class="listitem"><p><code class="function">std::find_first_of</code></p></li><li class="listitem"><p><code class="function">std::for_each</code></p></li><li class="listitem"><p><code class="function">std::generate</code></p></li><li class="listitem"><p><code class="function">std::generate_n</code></p></li><li class="listitem"><p><code class="function">std::lexicographical_compare</code></p></li><li class="listitem"><p><code class="function">std::mismatch</code></p></li><li class="listitem"><p><code class="function">std::search</code></p></li><li class="listitem"><p><code class="function">std::search_n</code></p></li><li class="listitem"><p><code class="function">std::transform</code></p></li><li class="listitem"><p><code class="function">std::replace</code></p></li><li class="listitem"><p><code class="function">std::replace_if</code></p></li><li class="listitem"><p><code class="function">std::max_element</code></p></li><li class="listitem"><p><code class="function">std::merge</code></p></li><li class="listitem"><p><code class="function">std::min_element</code></p></li><li class="listitem"><p><code class="function">std::nth_element</code></p></li><li class="listitem"><p><code class="function">std::partial_sort</code></p></li><li class="listitem"><p><code class="function">std::partition</code></p></li><li class="listitem"><p><code class="function">std::random_shuffle</code></p></li><li class="listitem"><p><code class="function">std::set_union</code></p></li><li class="listitem"><p><code class="function">std::set_intersection</code></p></li><li class="listitem"><p><code class="function">std::set_symmetric_difference</code></p></li><li class="listitem"><p><code class="function">std::set_difference</code></p></li><li class="listitem"><p><code class="function">std::sort</code></p></li><li class="listitem"><p><code class="function">std::stable_sort</code></p></li><li class="listitem"><p><code class="function">std::unique_copy</code></p></li></ul></div></div><div class="bibliography"><div class="titlepage"><div><div><h2 class="title"><a id="parallel_mode.biblio"></a>Bibliography</h2></div></div></div><div class="biblioentry"><a id="idm269998604464"></a><p><span class="citetitle"><em class="citetitle">

2935

Parallelization of Bulk Operations for STL Dictionaries

2936

</em>. </span><span class="author"><span class="firstname">Johannes</span> <span class="surname">Singler</span>. </span><span class="author"><span class="firstname">Leonor</span> <span class="surname">Frias</span>. </span><span class="copyright">Copyright © 2007 . </span><span class="publisher"><span class="publishername">

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Workshop on Highly Parallel Processing on a Chip (HPPC) 2007. (LNCS)

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- . </span></span></p></div><div class="biblioentry"><a id="idp16931936"></a><p><span class="citetitle"><em class="citetitle">

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+ . </span></span></p></div><div class="biblioentry"><a id="idm269998599392"></a><p><span class="citetitle"><em class="citetitle">

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The Multi-Core Standard Template Library

2941

</em>. </span><span class="author"><span class="firstname">Johannes</span> <span class="surname">Singler</span>. </span><span class="author"><span class="firstname">Peter</span> <span class="surname">Sanders</span>. </span><span class="author"><span class="firstname">Felix</span> <span class="surname">Putze</span>. </span><span class="copyright">Copyright © 2007 . </span><span class="publisher"><span class="publishername">

2942

Euro-Par 2007: Parallel Processing. (LNCS 4641)

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>

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-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Semantics</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="C++, library, debug" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="debug_mode.html" title="Chapter 17. Debug Mode" /><link rel="prev" href="debug_mode.html" title="Chapter 17. Debug Mode" /><link rel="next" href="debug_mode_using.html" title="Using" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Semantics</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="debug_mode.html">Prev</a> </td><th width="60%" align="center">Chapter 17. Debug Mode</th><td width="20%" align="right"> <a accesskey="n" href="debug_mode_using.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.debug_mode.semantics"></a>Semantics</h2></div></div></div><p>

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Semantics</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, debug" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="debug_mode.html" title="Chapter 17. Debug Mode" /><link rel="prev" href="debug_mode.html" title="Chapter 17. Debug Mode" /><link rel="next" href="debug_mode_using.html" title="Using" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Semantics</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="debug_mode.html">Prev</a> </td><th width="60%" align="center">Chapter 17. Debug Mode</th><td width="20%" align="right"> <a accesskey="n" href="debug_mode_using.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.debug_mode.semantics"></a>Semantics</h2></div></div></div><p>

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</p><p>A program that uses the C++ standard library correctly

2952

will maintain the same semantics under debug mode as it had with

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the normal (release) library. All functional and exception-handling

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>

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-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 2. Setup</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="intro.html" title="Part I. Introduction" /><link rel="prev" href="bugs.html" title="Bugs" /><link rel="next" href="configure.html" title="Configure" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 2. Setup</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="bugs.html">Prev</a> </td><th width="60%" align="center">Part I.

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 2. Setup</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="intro.html" title="Part I. Introduction" /><link rel="prev" href="bugs.html" title="Bugs" /><link rel="next" href="configure.html" title="Configure" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 2. Setup</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="bugs.html">Prev</a> </td><th width="60%" align="center">Part I.

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Introduction

2963

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-</th><td width="20%" align="right"> <a accesskey="n" href="configure.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.intro.setup"></a>Chapter 2. Setup</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="setup.html#manual.intro.setup.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="configure.html">Configure</a></span></dt><dt><span class="section"><a href="make.html">Make</a></span></dt></dl></div><p>To transform libstdc++ sources into installed include files

2965

+</th><td width="20%" align="right"> <a accesskey="n" href="configure.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.intro.setup"></a>Chapter 2. Setup</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="setup.html#manual.intro.setup.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="configure.html">Configure</a></span></dt><dt><span class="section"><a href="make.html">Make</a></span></dt></dl></div><p>To transform libstdc++ sources into installed include files

2966

and properly built binaries useful for linking to other software is

2967

a multi-step process. Steps include getting the sources,

2968

configuring and building the sources, testing, and installation.

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===================================================================

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>

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-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Backwards Compatibility</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, backwards" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B. Porting and Maintenance" /><link rel="prev" href="api.html" title="API Evolution and Deprecation History" /><link rel="next" href="appendix_free.html" title="Appendix C. Free Software Needs Free Documentation" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Backwards Compatibility</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="api.html">Prev</a> </td><th width="60%" align="center">Appendix B.

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Backwards Compatibility</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, backwards" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B. Porting and Maintenance" /><link rel="prev" href="api.html" title="API Evolution and Deprecation History" /><link rel="next" href="appendix_free.html" title="Appendix C. Free Software Needs Free Documentation" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Backwards Compatibility</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="api.html">Prev</a> </td><th width="60%" align="center">Appendix B.

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Porting and Maintenance

2978

2979

</th><td width="20%" align="right"> <a accesskey="n" href="appendix_free.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.appendix.porting.backwards"></a>Backwards Compatibility</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="backwards.first"></a>First</h3></div></div></div><p>The first generation GNU C++ library was called libg++. It was a

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This is a change in behavior from older versions. Now, most

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<span class="type">iterator_type</span> typedefs in container classes are POD

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objects, not <span class="type">value_type</span> pointers.

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-</p></div></div><div class="bibliography"><div class="titlepage"><div><div><h3 class="title"><a id="backwards.biblio"></a>Bibliography</h3></div></div></div><div class="biblioentry"><a id="idp23415104"></a><p><span class="title"><em>

2985

+</p></div></div><div class="bibliography"><div class="titlepage"><div><div><h3 class="title"><a id="backwards.biblio"></a>Bibliography</h3></div></div></div><div class="biblioentry"><a id="idm269992117648"></a><p><span class="title"><em>

2986

2987

Migrating to GCC 4.1

2988

</a>

2989

- </em>. </span><span class="author"><span class="firstname">Dan</span> <span class="surname">Kegel</span>. </span></p></div><div class="biblioentry"><a id="idp23417888"></a><p><span class="title"><em>

2990

+ </em>. </span><span class="author"><span class="firstname">Dan</span> <span class="surname">Kegel</span>. </span></p></div><div class="biblioentry"><a id="idm269992114864"></a><p><span class="title"><em>

2991

2992

Building the Whole Debian Archive with GCC 4.1: A Summary

2993

</a>

2994

- </em>. </span><span class="author"><span class="firstname">Martin</span> <span class="surname">Michlmayr</span>. </span></p></div><div class="biblioentry"><a id="idp23420736"></a><p><span class="title"><em>

2995

+ </em>. </span><span class="author"><span class="firstname">Martin</span> <span class="surname">Michlmayr</span>. </span></p></div><div class="biblioentry"><a id="idm269992112016"></a><p><span class="title"><em>

2996

2997

Migration guide for GCC-3.2

2998

</a>

2999

Index: libstdc++-v3/doc/html/manual/source_design_notes.html

3000

===================================================================

3001

--- a/src/libstdc++-v3/doc/html/manual/source_design_notes.html (.../tags/gcc_4_8_2_release)

3002

+++ b/src/libstdc++-v3/doc/html/manual/source_design_notes.html (.../branches/gcc-4_8-branch)

3003

@@ -1,5 +1,5 @@

3004

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

3005

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design Notes</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_contributing.html" title="Appendix A. Contributing" /><link rel="prev" href="source_code_style.html" title="Coding Style" /><link rel="next" href="appendix_porting.html" title="Appendix B. Porting and Maintenance" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design Notes</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="source_code_style.html">Prev</a> </td><th width="60%" align="center">Appendix A.

3006

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design Notes</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_contributing.html" title="Appendix A. Contributing" /><link rel="prev" href="source_code_style.html" title="Coding Style" /><link rel="next" href="appendix_porting.html" title="Appendix B. Porting and Maintenance" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design Notes</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="source_code_style.html">Prev</a> </td><th width="60%" align="center">Appendix A.

3007

Contributing

3008

3009

</th><td width="20%" align="right"> <a accesskey="n" href="appendix_porting.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="contrib.design_notes"></a>Design Notes</h2></div></div></div><p>

3010

Index: libstdc++-v3/doc/html/manual/ext_sgi.html

3011

===================================================================

3012

--- a/src/libstdc++-v3/doc/html/manual/ext_sgi.html (.../tags/gcc_4_8_2_release)

3013

+++ b/src/libstdc++-v3/doc/html/manual/ext_sgi.html (.../branches/gcc-4_8-branch)

3014

@@ -1,5 +1,5 @@

3015

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

3016

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Deprecated</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="ext_containers.html" title="Chapter 23. HP/SGI Extensions" /><link rel="prev" href="ext_containers.html" title="Chapter 23. HP/SGI Extensions" /><link rel="next" href="ext_utilities.html" title="Chapter 24. Utilities" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Deprecated</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_containers.html">Prev</a> </td><th width="60%" align="center">Chapter 23. HP/SGI Extensions</th><td width="20%" align="right"> <a accesskey="n" href="ext_utilities.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.containers.deprecated_sgi"></a>Deprecated</h2></div></div></div><p>

3017

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Deprecated</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="ext_containers.html" title="Chapter 23. HP/SGI Extensions" /><link rel="prev" href="ext_containers.html" title="Chapter 23. HP/SGI Extensions" /><link rel="next" href="ext_utilities.html" title="Chapter 24. Utilities" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Deprecated</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_containers.html">Prev</a> </td><th width="60%" align="center">Chapter 23. HP/SGI Extensions</th><td width="20%" align="right"> <a accesskey="n" href="ext_utilities.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.containers.deprecated_sgi"></a>Deprecated</h2></div></div></div><p>

3018

The SGI hashing classes <code class="classname">hash_set</code> and

3019

<code class="classname">hash_set</code> have been deprecated by the

3020

unordered_set, unordered_multiset, unordered_map,

3021

Index: libstdc++-v3/doc/html/manual/facets.html

3022

===================================================================

3023

--- a/src/libstdc++-v3/doc/html/manual/facets.html (.../tags/gcc_4_8_2_release)

3024

+++ b/src/libstdc++-v3/doc/html/manual/facets.html (.../branches/gcc-4_8-branch)

3025

@@ -1,8 +1,8 @@

3026

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

3027

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Facets</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="localization.html" title="Chapter 8. Localization" /><link rel="prev" href="localization.html" title="Chapter 8. Localization" /><link rel="next" href="containers.html" title="Chapter 9. Containers" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Facets</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="localization.html">Prev</a> </td><th width="60%" align="center">Chapter 8.

3028

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Facets</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="localization.html" title="Chapter 8. Localization" /><link rel="prev" href="localization.html" title="Chapter 8. Localization" /><link rel="next" href="containers.html" title="Chapter 9. Containers" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Facets</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="localization.html">Prev</a> </td><th width="60%" align="center">Chapter 8.

3029

Localization

3030

3031

-</th><td width="20%" align="right"> <a accesskey="n" href="containers.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.localization.facet"></a>Facets</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="std.localization.facet.ctype"></a>ctype</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="facet.ctype.impl"></a>Implementation</h4></div></div></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idp15778336"></a>Specializations</h5></div></div></div><p>

3032

+</th><td width="20%" align="right"> <a accesskey="n" href="containers.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.localization.facet"></a>Facets</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="std.localization.facet.ctype"></a>ctype</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="facet.ctype.impl"></a>Implementation</h4></div></div></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idm269999753024"></a>Specializations</h5></div></div></div><p>

3033

For the required specialization codecvt<wchar_t, char, mbstate_t> ,

3034

conversions are made between the internal character set (always UCS4

3035

on GNU/Linux) and whatever the currently selected locale for the

3036

@@ -49,24 +49,24 @@

3037

</p></li><li class="listitem"><p>

3038

Rename abstract base class. See if just smash-overriding is a

3039

better approach. Clarify, add sanity to naming.

3040

- </p></li></ul></div></div><div class="bibliography"><div class="titlepage"><div><div><h4 class="title"><a id="facet.ctype.biblio"></a>Bibliography</h4></div></div></div><div class="biblioentry"><a id="idp15793392"></a><p><span class="citetitle"><em class="citetitle">

3041

+ </p></li></ul></div></div><div class="bibliography"><div class="titlepage"><div><div><h4 class="title"><a id="facet.ctype.biblio"></a>Bibliography</h4></div></div></div><div class="biblioentry"><a id="idm269999738032"></a><p><span class="citetitle"><em class="citetitle">

3042

The GNU C Library

3043

- </em>. </span><span class="author"><span class="firstname">Roland</span> <span class="surname">McGrath</span>. </span><span class="author"><span class="firstname">Ulrich</span> <span class="surname">Drepper</span>. </span><span class="copyright">Copyright © 2007 FSF. </span><span class="pagenums">Chapters 6 Character Set Handling and 7 Locales and Internationalization. </span></p></div><div class="biblioentry"><a id="idp15798144"></a><p><span class="citetitle"><em class="citetitle">

3044

+ </em>. </span><span class="author"><span class="firstname">Roland</span> <span class="surname">McGrath</span>. </span><span class="author"><span class="firstname">Ulrich</span> <span class="surname">Drepper</span>. </span><span class="copyright">Copyright © 2007 FSF. </span><span class="pagenums">Chapters 6 Character Set Handling and 7 Locales and Internationalization. </span></p></div><div class="biblioentry"><a id="idm269999733280"></a><p><span class="citetitle"><em class="citetitle">

3045

Correspondence

3046

- </em>. </span><span class="author"><span class="firstname">Ulrich</span> <span class="surname">Drepper</span>. </span><span class="copyright">Copyright © 2002 . </span></p></div><div class="biblioentry"><a id="idp15801232"></a><p><span class="citetitle"><em class="citetitle">

3047

+ </em>. </span><span class="author"><span class="firstname">Ulrich</span> <span class="surname">Drepper</span>. </span><span class="copyright">Copyright © 2002 . </span></p></div><div class="biblioentry"><a id="idm269999730192"></a><p><span class="citetitle"><em class="citetitle">

3048

ISO/IEC 14882:1998 Programming languages - C++

3049

3050

3051

ISO/IEC 9899:1999 Programming languages - C

3052

3053

3054

3055

The Open Group Base Specifications, Issue 6 (IEEE Std. 1003.1-2004)

3056

</a>

3057

3058

- The Open Group/The Institute of Electrical and Electronics Engineers, Inc.. </span></p></div><div class="biblioentry"><a id="idp15809040"></a><p><span class="citetitle"><em class="citetitle">

3059

+ The Open Group/The Institute of Electrical and Electronics Engineers, Inc.. </span></p></div><div class="biblioentry"><a id="idm269999722384"></a><p><span class="citetitle"><em class="citetitle">

3060

The C++ Programming Language, Special Edition

3061

</em>. </span><span class="author"><span class="firstname">Bjarne</span> <span class="surname">Stroustrup</span>. </span><span class="copyright">Copyright © 2000 Addison Wesley, Inc.. </span><span class="pagenums">Appendix D. </span><span class="publisher"><span class="publishername">

3062

Addison Wesley

3063

- . </span></span></p></div><div class="biblioentry"><a id="idp15813664"></a><p><span class="citetitle"><em class="citetitle">

3064

+ . </span></span></p></div><div class="biblioentry"><a id="idm269999717760"></a><p><span class="citetitle"><em class="citetitle">

3065

Standard C++ IOStreams and Locales

3066

</em>. </span><span class="subtitle">

3067

Advanced Programmer's Guide and Reference

3068

@@ -409,17 +409,17 @@

3069

</p></li><li class="listitem"><p>

3070

wchar_t/char internal buffers and conversions between

3071

internal/external buffers?

3072

- </p></li></ul></div></li></ul></div></div><div class="bibliography"><div class="titlepage"><div><div><h4 class="title"><a id="facet.codecvt.biblio"></a>Bibliography</h4></div></div></div><div class="biblioentry"><a id="idp15891136"></a><p><span class="citetitle"><em class="citetitle">

3073

+ </p></li></ul></div></li></ul></div></div><div class="bibliography"><div class="titlepage"><div><div><h4 class="title"><a id="facet.codecvt.biblio"></a>Bibliography</h4></div></div></div><div class="biblioentry"><a id="idm269999640080"></a><p><span class="citetitle"><em class="citetitle">

3074

The GNU C Library

3075

</em>. </span><span class="author"><span class="firstname">Roland</span> <span class="surname">McGrath</span>. </span><span class="author"><span class="firstname">Ulrich</span> <span class="surname">Drepper</span>. </span><span class="copyright">Copyright © 2007 FSF. </span><span class="pagenums">

3076

Chapters 6 Character Set Handling and 7 Locales and Internationalization

3077

- . </span></p></div><div class="biblioentry"><a id="idp15895888"></a><p><span class="citetitle"><em class="citetitle">

3078

+ . </span></p></div><div class="biblioentry"><a id="idm269999635328"></a><p><span class="citetitle"><em class="citetitle">

3079

Correspondence

3080

- </em>. </span><span class="author"><span class="firstname">Ulrich</span> <span class="surname">Drepper</span>. </span><span class="copyright">Copyright © 2002 . </span></p></div><div class="biblioentry"><a id="idp15898976"></a><p><span class="citetitle"><em class="citetitle">

3081

+ </em>. </span><span class="author"><span class="firstname">Ulrich</span> <span class="surname">Drepper</span>. </span><span class="copyright">Copyright © 2002 . </span></p></div><div class="biblioentry"><a id="idm269999632240"></a><p><span class="citetitle"><em class="citetitle">

3082

ISO/IEC 14882:1998 Programming languages - C++

3083

3084

3085

ISO/IEC 9899:1999 Programming languages - C

3086

3087

3088

3089

System Interface Definitions, Issue 7 (IEEE Std. 1003.1-2008)

3090

</a>

3091

@@ -426,25 +426,25 @@

3092

3093

The Open Group/The Institute of Electrical and Electronics

3094

Engineers, Inc.

3095

- . </span></p></div><div class="biblioentry"><a id="idp15906768"></a><p><span class="citetitle"><em class="citetitle">

3096

+ . </span></p></div><div class="biblioentry"><a id="idm269999624448"></a><p><span class="citetitle"><em class="citetitle">

3097

The C++ Programming Language, Special Edition

3098

</em>. </span><span class="author"><span class="firstname">Bjarne</span> <span class="surname">Stroustrup</span>. </span><span class="copyright">Copyright © 2000 Addison Wesley, Inc.. </span><span class="pagenums">Appendix D. </span><span class="publisher"><span class="publishername">

3099

Addison Wesley

3100

- . </span></span></p></div><div class="biblioentry"><a id="idp15911392"></a><p><span class="citetitle"><em class="citetitle">

3101

+ . </span></span></p></div><div class="biblioentry"><a id="idm269999619824"></a><p><span class="citetitle"><em class="citetitle">

3102

Standard C++ IOStreams and Locales

3103

</em>. </span><span class="subtitle">

3104

Advanced Programmer's Guide and Reference

3105

. </span><span class="author"><span class="firstname">Angelika</span> <span class="surname">Langer</span>. </span><span class="author"><span class="firstname">Klaus</span> <span class="surname">Kreft</span>. </span><span class="copyright">Copyright © 2000 Addison Wesley Longman, Inc.. </span><span class="publisher"><span class="publishername">

3106

Addison Wesley Longman

3107

- . </span></span></p></div><div class="biblioentry"><a id="idp15917056"></a><p><span class="title"><em>

3108

+ . </span></span></p></div><div class="biblioentry"><a id="idm269999614160"></a><p><span class="title"><em>

3109

3110

A brief description of Normative Addendum 1

3111

</a>

3112

- </em>. </span><span class="author"><span class="firstname">Clive</span> <span class="surname">Feather</span>. </span><span class="pagenums">Extended Character Sets. </span></p></div><div class="biblioentry"><a id="idp15920304"></a><p><span class="title"><em>

3113

+ </em>. </span><span class="author"><span class="firstname">Clive</span> <span class="surname">Feather</span>. </span><span class="pagenums">Extended Character Sets. </span></p></div><div class="biblioentry"><a id="idm269999610912"></a><p><span class="title"><em>

3114

3115

The Unicode HOWTO

3116

</a>

3117

- </em>. </span><span class="author"><span class="firstname">Bruno</span> <span class="surname">Haible</span>. </span></p></div><div class="biblioentry"><a id="idp15923088"></a><p><span class="title"><em>

3118

+ </em>. </span><span class="author"><span class="firstname">Bruno</span> <span class="surname">Haible</span>. </span></p></div><div class="biblioentry"><a id="idm269999608128"></a><p><span class="title"><em>

3119

3120

UTF-8 and Unicode FAQ for Unix/Linux

3121

</a>

3122

@@ -690,16 +690,16 @@

3123

model. As of this writing, it is unknown how to query to see

3124

if a specified message catalog exists using the gettext

3125

package.

3126

- </p></li></ul></div></div><div class="bibliography"><div class="titlepage"><div><div><h4 class="title"><a id="facet.messages.biblio"></a>Bibliography</h4></div></div></div><div class="biblioentry"><a id="idp16003632"></a><p><span class="citetitle"><em class="citetitle">

3127

+ </p></li></ul></div></div><div class="bibliography"><div class="titlepage"><div><div><h4 class="title"><a id="facet.messages.biblio"></a>Bibliography</h4></div></div></div><div class="biblioentry"><a id="idm269999527584"></a><p><span class="citetitle"><em class="citetitle">

3128

The GNU C Library

3129

</em>. </span><span class="author"><span class="firstname">Roland</span> <span class="surname">McGrath</span>. </span><span class="author"><span class="firstname">Ulrich</span> <span class="surname">Drepper</span>. </span><span class="copyright">Copyright © 2007 FSF. </span><span class="pagenums">Chapters 6 Character Set Handling, and 7 Locales and Internationalization

3130

- . </span></p></div><div class="biblioentry"><a id="idp16008384"></a><p><span class="citetitle"><em class="citetitle">

3131

+ . </span></p></div><div class="biblioentry"><a id="idm269999522832"></a><p><span class="citetitle"><em class="citetitle">

3132

Correspondence

3133

- </em>. </span><span class="author"><span class="firstname">Ulrich</span> <span class="surname">Drepper</span>. </span><span class="copyright">Copyright © 2002 . </span></p></div><div class="biblioentry"><a id="idp16011472"></a><p><span class="citetitle"><em class="citetitle">

3134

+ </em>. </span><span class="author"><span class="firstname">Ulrich</span> <span class="surname">Drepper</span>. </span><span class="copyright">Copyright © 2002 . </span></p></div><div class="biblioentry"><a id="idm269999519744"></a><p><span class="citetitle"><em class="citetitle">

3135

ISO/IEC 14882:1998 Programming languages - C++

3136

3137

3138

ISO/IEC 9899:1999 Programming languages - C

3139

3140

3141

3142

System Interface Definitions, Issue 7 (IEEE Std. 1003.1-2008)

3143

</a>

3144

@@ -706,23 +706,23 @@

3145

3146

The Open Group/The Institute of Electrical and Electronics

3147

Engineers, Inc.

3148

- . </span></p></div><div class="biblioentry"><a id="idp16019264"></a><p><span class="citetitle"><em class="citetitle">

3149

+ . </span></p></div><div class="biblioentry"><a id="idm269999511952"></a><p><span class="citetitle"><em class="citetitle">

3150

The C++ Programming Language, Special Edition

3151

</em>. </span><span class="author"><span class="firstname">Bjarne</span> <span class="surname">Stroustrup</span>. </span><span class="copyright">Copyright © 2000 Addison Wesley, Inc.. </span><span class="pagenums">Appendix D. </span><span class="publisher"><span class="publishername">

3152

Addison Wesley

3153

- . </span></span></p></div><div class="biblioentry"><a id="idp16023888"></a><p><span class="citetitle"><em class="citetitle">

3154

+ . </span></span></p></div><div class="biblioentry"><a id="idm269999507328"></a><p><span class="citetitle"><em class="citetitle">

3155

Standard C++ IOStreams and Locales

3156

</em>. </span><span class="subtitle">

3157

Advanced Programmer's Guide and Reference

3158

. </span><span class="author"><span class="firstname">Angelika</span> <span class="surname">Langer</span>. </span><span class="author"><span class="firstname">Klaus</span> <span class="surname">Kreft</span>. </span><span class="copyright">Copyright © 2000 Addison Wesley Longman, Inc.. </span><span class="publisher"><span class="publishername">

3159

Addison Wesley Longman

3160

- . </span></span></p></div><div class="biblioentry"><a id="idp16029552"></a><p><span class="title"><em>

3161

- <a class="link" href="http://java.sun.com/reference/api/index.html" target="_top">

3162

+ . </span></span></p></div><div class="biblioentry"><a id="idm269999501664"></a><p><span class="title"><em>

3163

+ <a class="link" href="http://www.oracle.com/technetwork/java/api/index.html" target="_top">

3164

API Specifications, Java Platform

3165

</a>

3166

</em>. </span><span class="pagenums">java.util.Properties, java.text.MessageFormat,

3167

java.util.Locale, java.util.ResourceBundle

3168

- . </span></p></div><div class="biblioentry"><a id="idp16031888"></a><p><span class="title"><em>

3169

+ . </span></p></div><div class="biblioentry"><a id="idm269999499328"></a><p><span class="title"><em>

3170

3171

GNU gettext tools, version 0.10.38, Native Language Support

3172

Library and Tools.

3173

Index: libstdc++-v3/doc/html/manual/diagnostics.html

3174

===================================================================

3175

--- a/src/libstdc++-v3/doc/html/manual/diagnostics.html (.../tags/gcc_4_8_2_release)

3176

+++ b/src/libstdc++-v3/doc/html/manual/diagnostics.html (.../branches/gcc-4_8-branch)

3177

@@ -1,5 +1,5 @@

3178

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

3179

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 5. Diagnostics</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II. Standard Contents" /><link rel="prev" href="termination.html" title="Termination" /><link rel="next" href="concept_checking.html" title="Concept Checking" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 5.

3180

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 5. Diagnostics</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II. Standard Contents" /><link rel="prev" href="termination.html" title="Termination" /><link rel="next" href="concept_checking.html" title="Concept Checking" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 5.

3181

Diagnostics

3182

3183

</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="termination.html">Prev</a> </td><th width="60%" align="center">Part II.

3184

@@ -6,8 +6,8 @@

3185

Standard Contents

3186

</th><td width="20%" align="right"> <a accesskey="n" href="concept_checking.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="std.diagnostics"></a>Chapter 5.

3187

Diagnostics

3188

- <a id="idp13835248" class="indexterm"></a>

3189

-</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="diagnostics.html#std.diagnostics.exceptions">Exceptions</a></span></dt><dd><dl><dt><span class="section"><a href="diagnostics.html#std.diagnostics.exceptions.api">API Reference</a></span></dt><dt><span class="section"><a href="diagnostics.html#std.diagnostics.exceptions.data">Adding Data to <code class="classname">exception</code></a></span></dt></dl></dd><dt><span class="section"><a href="concept_checking.html">Concept Checking</a></span></dt></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.diagnostics.exceptions"></a>Exceptions</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="std.diagnostics.exceptions.api"></a>API Reference</h3></div></div></div><p>

3190

+ <a id="idm270001697504" class="indexterm"></a>

3191

+</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="diagnostics.html#std.diagnostics.exceptions">Exceptions</a></span></dt><dd><dl><dt><span class="section"><a href="diagnostics.html#std.diagnostics.exceptions.api">API Reference</a></span></dt><dt><span class="section"><a href="diagnostics.html#std.diagnostics.exceptions.data">Adding Data to <code class="classname">exception</code></a></span></dt></dl></dd><dt><span class="section"><a href="concept_checking.html">Concept Checking</a></span></dt></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.diagnostics.exceptions"></a>Exceptions</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="std.diagnostics.exceptions.api"></a>API Reference</h3></div></div></div><p>

3192

All exception objects are defined in one of the standard header

3193

files: <code class="filename">exception</code>,

3194

<code class="filename">stdexcept</code>, <code class="filename">new</code>, and

3195

Index: libstdc++-v3/doc/html/manual/mt_allocator_design.html

3196

===================================================================

3197

--- a/src/libstdc++-v3/doc/html/manual/mt_allocator_design.html (.../tags/gcc_4_8_2_release)

3198

+++ b/src/libstdc++-v3/doc/html/manual/mt_allocator_design.html (.../branches/gcc-4_8-branch)

3199

@@ -1,5 +1,5 @@

3200

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

3201

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design Issues</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, allocator" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="mt_allocator.html" title="Chapter 20. The mt_allocator" /><link rel="prev" href="mt_allocator.html" title="Chapter 20. The mt_allocator" /><link rel="next" href="mt_allocator_impl.html" title="Implementation" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design Issues</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="mt_allocator.html">Prev</a> </td><th width="60%" align="center">Chapter 20. The mt_allocator</th><td width="20%" align="right"> <a accesskey="n" href="mt_allocator_impl.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="allocator.mt.design_issues"></a>Design Issues</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="allocator.mt.overview"></a>Overview</h3></div></div></div><p> There are three general components to the allocator: a datum

3202

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design Issues</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, allocator" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="mt_allocator.html" title="Chapter 20. The mt_allocator" /><link rel="prev" href="mt_allocator.html" title="Chapter 20. The mt_allocator" /><link rel="next" href="mt_allocator_impl.html" title="Implementation" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design Issues</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="mt_allocator.html">Prev</a> </td><th width="60%" align="center">Chapter 20. The mt_allocator</th><td width="20%" align="right"> <a accesskey="n" href="mt_allocator_impl.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="allocator.mt.design_issues"></a>Design Issues</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="allocator.mt.overview"></a>Overview</h3></div></div></div><p> There are three general components to the allocator: a datum

3203

describing the characteristics of the memory pool, a policy class

3204

containing this pool that links instantiation types to common or

3205

individual pools, and a class inheriting from the policy class that is

3206

Index: libstdc++-v3/doc/html/manual/appendix_free.html

3207

===================================================================

3208

--- a/src/libstdc++-v3/doc/html/manual/appendix_free.html (.../tags/gcc_4_8_2_release)

3209

+++ b/src/libstdc++-v3/doc/html/manual/appendix_free.html (.../branches/gcc-4_8-branch)

3210

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3211

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

3212

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Appendix C. Free Software Needs Free Documentation</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix.html" title="Part IV. Appendices" /><link rel="prev" href="backwards.html" title="Backwards Compatibility" /><link rel="next" href="appendix_gpl.html" title="Appendix D. GNU General Public License version 3" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Appendix C.

3213

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Appendix C. Free Software Needs Free Documentation</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix.html" title="Part IV. Appendices" /><link rel="prev" href="backwards.html" title="Backwards Compatibility" /><link rel="next" href="appendix_gpl.html" title="Appendix D. GNU General Public License version 3" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Appendix C.

3214

Free Software Needs Free Documentation

3215

3216

</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="backwards.html">Prev</a> </td><th width="60%" align="center">Part IV.

3217

@@ -6,7 +6,7 @@

3218

Appendices

3219

</th><td width="20%" align="right"> <a accesskey="n" href="appendix_gpl.html">Next</a></td></tr></table><hr /></div><div class="appendix"><div class="titlepage"><div><div><h1 class="title"><a id="appendix.free"></a>

3220

Free Software Needs Free Documentation

3221

- <a id="idp23426192" class="indexterm"></a>

3222

+ <a id="idm269992106560" class="indexterm"></a>

3223

</h1></div></div></div><p>

3224

The biggest deficiency in free operating systems is not in the

3225

software--it is the lack of good free manuals that we can include in

3226

Index: libstdc++-v3/doc/html/manual/algorithms.html

3227

===================================================================

3228

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3229

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3230

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3231

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

3232

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3233

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 11. Algorithms</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library, algorithm" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II. Standard Contents" /><link rel="prev" href="iterators.html" title="Chapter 10. Iterators" /><link rel="next" href="numerics.html" title="Chapter 12. Numerics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 11.

3234

Algorithms

3235

3236

</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="iterators.html">Prev</a> </td><th width="60%" align="center">Part II.

3237

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3238

Standard Contents

3239

</th><td width="20%" align="right"> <a accesskey="n" href="numerics.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="std.algorithms"></a>Chapter 11.

3240

Algorithms

3241

- <a id="idp16191968" class="indexterm"></a>

3242

-</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="algorithms.html#std.algorithms.mutating">Mutating</a></span></dt><dd><dl><dt><span class="section"><a href="algorithms.html#algorithms.mutating.swap"><code class="function">swap</code></a></span></dt><dd><dl><dt><span class="section"><a href="algorithms.html#algorithms.swap.specializations">Specializations</a></span></dt></dl></dd></dl></dd></dl></div><p>

3243

+ <a id="idm269999339120" class="indexterm"></a>

3244

+</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="algorithms.html#std.algorithms.mutating">Mutating</a></span></dt><dd><dl><dt><span class="section"><a href="algorithms.html#algorithms.mutating.swap"><code class="function">swap</code></a></span></dt><dd><dl><dt><span class="section"><a href="algorithms.html#algorithms.swap.specializations">Specializations</a></span></dt></dl></dd></dl></dd></dl></div><p>

3245

The neatest accomplishment of the algorithms section is that all the

3246

work is done via iterators, not containers directly. This means two

3247

important things:

3248

Index: libstdc++-v3/doc/html/manual/appendix_porting.html

3249

===================================================================

3250

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3251

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3252

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3253

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

3254

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3255

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Appendix B. Porting and Maintenance</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix.html" title="Part IV. Appendices" /><link rel="prev" href="source_design_notes.html" title="Design Notes" /><link rel="next" href="documentation_hacking.html" title="Writing and Generating Documentation" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Appendix B.

3256

Porting and Maintenance

3257

3258

</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="source_design_notes.html">Prev</a> </td><th width="60%" align="center">Part IV.

3259

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3260

Appendices

3261

</th><td width="20%" align="right"> <a accesskey="n" href="documentation_hacking.html">Next</a></td></tr></table><hr /></div><div class="appendix"><div class="titlepage"><div><div><h1 class="title"><a id="appendix.porting"></a>

3262

Porting and Maintenance

3263

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3264

-</h1></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="appendix_porting.html#appendix.porting.build_hacking">Configure and Build Hacking</a></span></dt><dd><dl><dt><span class="section"><a href="appendix_porting.html#build_hacking.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="appendix_porting.html#build_hacking.overview">Overview</a></span></dt><dd><dl><dt><span class="section"><a href="appendix_porting.html#build_hacking.overview.basic">General Process</a></span></dt><dt><span class="section"><a href="appendix_porting.html#build_hacking.overview.map">What Comes from Where</a></span></dt></dl></dd><dt><span class="section"><a href="appendix_porting.html#build_hacking.configure">Configure</a></span></dt><dd><dl><dt><span class="section"><a href="appendix_porting.html#build_hacking.configure.scripts">Storing Information in non-AC files (like configure.host)</a></span></dt><dt><span class="section"><a href="appendix_porting.html#build_hacking.configure.conventions">Coding and Commenting Conventions</a></span></dt><dt><span class="section"><a href="appendix_porting.html#build_hacking.configure.acinclude">The acinclude.m4 layout</a></span></dt><dt><span class="section"><a href="appendix_porting.html#build_hacking.configure.enable"><code class="constant">GLIBCXX_ENABLE</code>, the <code class="literal">--enable</code> maker</a></span></dt></dl></dd><dt><span class="section"><a href="appendix_porting.html#build_hacking.make">Make</a></span></dt></dl></dd><dt><span class="section"><a href="documentation_hacking.html">Writing and Generating Documentation</a></span></dt><dd><dl><dt><span class="section"><a href="documentation_hacking.html#doc.intro">Introduction</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#doc.generation">Generating Documentation</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#doc.doxygen">Doxygen</a></span></dt><dd><dl><dt><span class="section"><a href="documentation_hacking.html#doxygen.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#doxygen.rules">Generating the Doxygen Files</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#doxygen.debug">Debugging Generation</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#doxygen.markup">Markup</a></span></dt></dl></dd><dt><span class="section"><a href="documentation_hacking.html#doc.docbook">Docbook</a></span></dt><dd><dl><dt><span class="section"><a href="documentation_hacking.html#docbook.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#docbook.rules">Generating the DocBook Files</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#docbook.debug">Debugging Generation</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#docbook.validation">Editing and Validation</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#docbook.examples">File Organization and Basics</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#docbook.markup">Markup By Example</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="internals.html">Porting to New Hardware or Operating Systems</a></span></dt><dd><dl><dt><span class="section"><a href="internals.html#internals.os">Operating System</a></span></dt><dt><span class="section"><a href="internals.html#internals.cpu">CPU</a></span></dt><dt><span class="section"><a href="internals.html#internals.char_types">Character Types</a></span></dt><dt><span class="section"><a href="internals.html#internals.thread_safety">Thread Safety</a></span></dt><dt><span class="section"><a href="internals.html#internals.numeric_limits">Numeric Limits</a></span></dt><dt><span class="section"><a href="internals.html#internals.libtool">Libtool</a></span></dt></dl></dd><dt><span class="section"><a href="test.html">Test</a></span></dt><dd><dl><dt><span class="section"><a href="test.html#test.organization">Organization</a></span></dt><dd><dl><dt><span class="section"><a href="test.html#test.organization.layout">Directory Layout</a></span></dt><dt><span class="section"><a href="test.html#test.organization.naming">Naming Conventions</a></span></dt></dl></dd><dt><span class="section"><a href="test.html#test.run">Running the Testsuite</a></span></dt><dd><dl><dt><span class="section"><a href="test.html#test.run.basic">Basic</a></span></dt><dt><span class="section"><a href="test.html#test.run.variations">Variations</a></span></dt><dt><span class="section"><a href="test.html#test.run.permutations">Permutations</a></span></dt></dl></dd><dt><span class="section"><a href="test.html#test.new_tests">Writing a new test case</a></span></dt><dt><span class="section"><a href="test.html#test.harness">Test Harness and Utilities</a></span></dt><dd><dl><dt><span class="section"><a href="test.html#test.harness.dejagnu">Dejagnu Harness Details</a></span></dt><dt><span class="section"><a href="test.html#test.harness.utils">Utilities</a></span></dt></dl></dd><dt><span class="section"><a href="test.html#test.special">Special Topics</a></span></dt><dd><dl><dt><span class="section"><a href="test.html#test.exception.safety">

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+ <a id="idm269993523968" class="indexterm"></a>

3266

+</h1></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="appendix_porting.html#appendix.porting.build_hacking">Configure and Build Hacking</a></span></dt><dd><dl><dt><span class="section"><a href="appendix_porting.html#build_hacking.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="appendix_porting.html#build_hacking.overview">Overview</a></span></dt><dd><dl><dt><span class="section"><a href="appendix_porting.html#build_hacking.overview.basic">General Process</a></span></dt><dt><span class="section"><a href="appendix_porting.html#build_hacking.overview.map">What Comes from Where</a></span></dt></dl></dd><dt><span class="section"><a href="appendix_porting.html#build_hacking.configure">Configure</a></span></dt><dd><dl><dt><span class="section"><a href="appendix_porting.html#build_hacking.configure.scripts">Storing Information in non-AC files (like configure.host)</a></span></dt><dt><span class="section"><a href="appendix_porting.html#build_hacking.configure.conventions">Coding and Commenting Conventions</a></span></dt><dt><span class="section"><a href="appendix_porting.html#build_hacking.configure.acinclude">The acinclude.m4 layout</a></span></dt><dt><span class="section"><a href="appendix_porting.html#build_hacking.configure.enable"><code class="constant">GLIBCXX_ENABLE</code>, the <code class="literal">--enable</code> maker</a></span></dt></dl></dd><dt><span class="section"><a href="appendix_porting.html#build_hacking.make">Make</a></span></dt></dl></dd><dt><span class="section"><a href="documentation_hacking.html">Writing and Generating Documentation</a></span></dt><dd><dl><dt><span class="section"><a href="documentation_hacking.html#doc.intro">Introduction</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#doc.generation">Generating Documentation</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#doc.doxygen">Doxygen</a></span></dt><dd><dl><dt><span class="section"><a href="documentation_hacking.html#doxygen.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#doxygen.rules">Generating the Doxygen Files</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#doxygen.debug">Debugging Generation</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#doxygen.markup">Markup</a></span></dt></dl></dd><dt><span class="section"><a href="documentation_hacking.html#doc.docbook">Docbook</a></span></dt><dd><dl><dt><span class="section"><a href="documentation_hacking.html#docbook.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#docbook.rules">Generating the DocBook Files</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#docbook.debug">Debugging Generation</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#docbook.validation">Editing and Validation</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#docbook.examples">File Organization and Basics</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#docbook.markup">Markup By Example</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="internals.html">Porting to New Hardware or Operating Systems</a></span></dt><dd><dl><dt><span class="section"><a href="internals.html#internals.os">Operating System</a></span></dt><dt><span class="section"><a href="internals.html#internals.cpu">CPU</a></span></dt><dt><span class="section"><a href="internals.html#internals.char_types">Character Types</a></span></dt><dt><span class="section"><a href="internals.html#internals.thread_safety">Thread Safety</a></span></dt><dt><span class="section"><a href="internals.html#internals.numeric_limits">Numeric Limits</a></span></dt><dt><span class="section"><a href="internals.html#internals.libtool">Libtool</a></span></dt></dl></dd><dt><span class="section"><a href="test.html">Test</a></span></dt><dd><dl><dt><span class="section"><a href="test.html#test.organization">Organization</a></span></dt><dd><dl><dt><span class="section"><a href="test.html#test.organization.layout">Directory Layout</a></span></dt><dt><span class="section"><a href="test.html#test.organization.naming">Naming Conventions</a></span></dt></dl></dd><dt><span class="section"><a href="test.html#test.run">Running the Testsuite</a></span></dt><dd><dl><dt><span class="section"><a href="test.html#test.run.basic">Basic</a></span></dt><dt><span class="section"><a href="test.html#test.run.variations">Variations</a></span></dt><dt><span class="section"><a href="test.html#test.run.permutations">Permutations</a></span></dt></dl></dd><dt><span class="section"><a href="test.html#test.new_tests">Writing a new test case</a></span></dt><dt><span class="section"><a href="test.html#test.harness">Test Harness and Utilities</a></span></dt><dd><dl><dt><span class="section"><a href="test.html#test.harness.dejagnu">Dejagnu Harness Details</a></span></dt><dt><span class="section"><a href="test.html#test.harness.utils">Utilities</a></span></dt></dl></dd><dt><span class="section"><a href="test.html#test.special">Special Topics</a></span></dt><dd><dl><dt><span class="section"><a href="test.html#test.exception.safety">

3267

Qualifying Exception Safety Guarantees

3268

3269

</a></span></dt><dd><dl><dt><span class="section"><a href="test.html#test.exception.safety.overview">Overview</a></span></dt><dt><span class="section"><a href="test.html#test.exception.safety.status">

3270

@@ -61,7 +61,7 @@

3271

in the build directory starts the build process. The <code class="literal">all</code> target comes from the <code class="filename">Makefile</code> file, which is generated via <span class="command"><strong>configure</strong></span> from the <code class="filename">Makefile.in</code> file, which is in turn generated (via

3272

<span class="command"><strong>automake</strong></span>) from the file

3273

<code class="filename">Makefile.am</code>.

3274

-</p></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="build_hacking.overview.map"></a>What Comes from Where</h4></div></div></div><div class="figure"><a id="idp22035648"></a><p class="title"><strong>Figure B.1. Configure and Build File Dependencies</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/confdeps.png" align="middle" alt="Dependency Graph for Configure and Build Files" /></div></div></div><br class="figure-break" /><p>

3275

+</p></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="build_hacking.overview.map"></a>What Comes from Where</h4></div></div></div><div class="figure"><a id="idm269993497120"></a><p class="title"><strong>Figure B.1. Configure and Build File Dependencies</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/confdeps.png" align="middle" alt="Dependency Graph for Configure and Build Files" /></div></div></div><br class="figure-break" /><p>

3276

Regenerate all generated files by using the command

3277

<code class="code">autoreconf</code> at the top level of the libstdc++ source

3278

directory.

3279

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3280

===================================================================

3281

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3282

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3283

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3284

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

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-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Empirical Cost Model</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="prev" href="profile_mode_api.html" title="Extensions for Custom Containers" /><link rel="next" href="profile_mode_impl.html" title="Implementation Issues" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Empirical Cost Model</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="profile_mode_api.html">Prev</a> </td><th width="60%" align="center">Chapter 19. Profile Mode</th><td width="20%" align="right"> <a accesskey="n" href="profile_mode_impl.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.cost_model"></a>Empirical Cost Model</h2></div></div></div><p>

3286

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Empirical Cost Model</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="prev" href="profile_mode_api.html" title="Extensions for Custom Containers" /><link rel="next" href="profile_mode_impl.html" title="Implementation Issues" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Empirical Cost Model</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="profile_mode_api.html">Prev</a> </td><th width="60%" align="center">Chapter 19. Profile Mode</th><td width="20%" align="right"> <a accesskey="n" href="profile_mode_impl.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.cost_model"></a>Empirical Cost Model</h2></div></div></div><p>

3287

Currently, the cost model uses formulas with predefined relative weights

3288

for alternative containers or container implementations. For instance,

3289

iterating through a vector is X times faster than iterating through a list.

3290

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3291

===================================================================

3292

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3293

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3294

@@ -1,5 +1,5 @@

3295

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

3296

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Make</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="setup.html" title="Chapter 2. Setup" /><link rel="prev" href="configure.html" title="Configure" /><link rel="next" href="using.html" title="Chapter 3. Using" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Make</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="configure.html">Prev</a> </td><th width="60%" align="center">Chapter 2. Setup</th><td width="20%" align="right"> <a accesskey="n" href="using.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.setup.make"></a>Make</h2></div></div></div><p>If you have never done this before, you should read the basic

3297

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Make</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="setup.html" title="Chapter 2. Setup" /><link rel="prev" href="configure.html" title="Configure" /><link rel="next" href="using.html" title="Chapter 3. Using" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Make</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="configure.html">Prev</a> </td><th width="60%" align="center">Chapter 2. Setup</th><td width="20%" align="right"> <a accesskey="n" href="using.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.setup.make"></a>Make</h2></div></div></div><p>If you have never done this before, you should read the basic

3298

<a class="link" href="http://gcc.gnu.org/install/" target="_top">GCC Installation

3299

Instructions</a> first. Read <span class="emphasis"><em>all of them</em></span>.

3300

<span class="emphasis"><em>Twice.</em></span>

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3303

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>

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-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Pairs</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="utilities.html" title="Chapter 6. Utilities" /><link rel="prev" href="utilities.html" title="Chapter 6. Utilities" /><link rel="next" href="memory.html" title="Memory" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Pairs</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="utilities.html">Prev</a> </td><th width="60%" align="center">Chapter 6.

3308

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Pairs</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="utilities.html" title="Chapter 6. Utilities" /><link rel="prev" href="utilities.html" title="Chapter 6. Utilities" /><link rel="next" href="memory.html" title="Memory" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Pairs</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="utilities.html">Prev</a> </td><th width="60%" align="center">Chapter 6.

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Utilities

3310

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</th><td width="20%" align="right"> <a accesskey="n" href="memory.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.util.pairs"></a>Pairs</h2></div></div></div><p>The <code class="code">pair<T1,T2></code> is a simple and handy way to

3312

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===================================================================

3314

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>

3318

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Test</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, test, testsuite, performance, conformance, ABI, exception safety" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B. Porting and Maintenance" /><link rel="prev" href="internals.html" title="Porting to New Hardware or Operating Systems" /><link rel="next" href="abi.html" title="ABI Policy and Guidelines" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Test</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="internals.html">Prev</a> </td><th width="60%" align="center">Appendix B.

3319

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Test</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, test, testsuite, performance, conformance, ABI, exception safety" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B. Porting and Maintenance" /><link rel="prev" href="internals.html" title="Porting to New Hardware or Operating Systems" /><link rel="next" href="abi.html" title="ABI Policy and Guidelines" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Test</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="internals.html">Prev</a> </td><th width="60%" align="center">Appendix B.

3320

Porting and Maintenance

3321

3322

</th><td width="20%" align="right"> <a accesskey="n" href="abi.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.setup.test"></a>Test</h2></div></div></div><p>

3323

@@ -492,7 +492,7 @@

3324

reporting functions including:

3325

</p><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: circle; "><li class="listitem"><p>time_counter</p></li><li class="listitem"><p>resource_counter</p></li><li class="listitem"><p>report_performance</p></li></ul></div></li></ul></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="test.special"></a>Special Topics</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="test.exception.safety"></a>

3326

Qualifying Exception Safety Guarantees

3327

- <a id="idp22628992" class="indexterm"></a>

3328

+ <a id="idm269992903504" class="indexterm"></a>

3329

</h4></div></div></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="test.exception.safety.overview"></a>Overview</h5></div></div></div><p>

3330

Testing is composed of running a particular test sequence,

3331

and looking at what happens to the surrounding code when

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===================================================================

3334

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>

3338

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Linking</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_namespaces.html" title="Namespaces" /><link rel="next" href="using_concurrency.html" title="Concurrency" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Linking</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_namespaces.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="using_concurrency.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.linkage"></a>Linking</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.intro.using.linkage.freestanding"></a>Almost Nothing</h3></div></div></div><p>

3339

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Linking</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_namespaces.html" title="Namespaces" /><link rel="next" href="using_concurrency.html" title="Concurrency" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Linking</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_namespaces.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="using_concurrency.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.linkage"></a>Linking</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.intro.using.linkage.freestanding"></a>Almost Nothing</h3></div></div></div><p>

3340

Or as close as it gets: freestanding. This is a minimal

3341

configuration, with only partial support for the standard

3342

library. Assume only the following header files can be used:

3343

Index: libstdc++-v3/doc/html/manual/using_headers.html

3344

===================================================================

3345

--- a/src/libstdc++-v3/doc/html/manual/using_headers.html (.../tags/gcc_4_8_2_release)

3346

+++ b/src/libstdc++-v3/doc/html/manual/using_headers.html (.../branches/gcc-4_8-branch)

3347

@@ -1,5 +1,5 @@

3348

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

3349

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Headers</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using.html" title="Chapter 3. Using" /><link rel="next" href="using_macros.html" title="Macros" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Headers</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="using_macros.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.headers"></a>Headers</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.intro.using.headers.all"></a>Header Files</h3></div></div></div><p>

3350

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Headers</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using.html" title="Chapter 3. Using" /><link rel="next" href="using_macros.html" title="Macros" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Headers</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="using_macros.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.headers"></a>Headers</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.intro.using.headers.all"></a>Header Files</h3></div></div></div><p>

3351

The C++ standard specifies the entire set of header files that

3352

must be available to all hosted implementations. Actually, the

3353

word "files" is a misnomer, since the contents of the

3354

@@ -18,19 +18,19 @@

3355

the 1998 standard as updated for 2003, and the current 2011 standard.

3356

</p><p>

3357

C++98/03 include files. These are available in the default compilation mode, i.e. <code class="code">-std=c++98</code> or <code class="code">-std=gnu++98</code>.

3358

- </p><div class="table"><a id="idp13079360"></a><p class="title"><strong>Table 3.2. C++ 1998 Library Headers</strong></p><div class="table-contents"><table summary="C++ 1998 Library Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="filename">bitset</code></td><td align="left"><code class="filename">complex</code></td><td align="left"><code class="filename">deque</code></td><td align="left"><code class="filename">exception</code></td></tr><tr><td align="left"><code class="filename">fstream</code></td><td align="left"><code class="filename">functional</code></td><td align="left"><code class="filename">iomanip</code></td><td align="left"><code class="filename">ios</code></td><td align="left"><code class="filename">iosfwd</code></td></tr><tr><td align="left"><code class="filename">iostream</code></td><td align="left"><code class="filename">istream</code></td><td align="left"><code class="filename">iterator</code></td><td align="left"><code class="filename">limits</code></td><td align="left"><code class="filename">list</code></td></tr><tr><td align="left"><code class="filename">locale</code></td><td align="left"><code class="filename">map</code></td><td align="left"><code class="filename">memory</code></td><td align="left"><code class="filename">new</code></td><td align="left"><code class="filename">numeric</code></td></tr><tr><td align="left"><code class="filename">ostream</code></td><td align="left"><code class="filename">queue</code></td><td align="left"><code class="filename">set</code></td><td align="left"><code class="filename">sstream</code></td><td align="left"><code class="filename">stack</code></td></tr><tr><td align="left"><code class="filename">stdexcept</code></td><td align="left"><code class="filename">streambuf</code></td><td align="left"><code class="filename">string</code></td><td align="left"><code class="filename">utility</code></td><td align="left"><code class="filename">typeinfo</code></td></tr><tr><td align="left"><code class="filename">valarray</code></td><td align="left"><code class="filename">vector</code></td><td class="auto-generated"> </td><td class="auto-generated"> </td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="idp13115840"></a><p class="title"><strong>Table 3.3. C++ 1998 Library Headers for C Library Facilities</strong></p><div class="table-contents"><table summary="C++ 1998 Library Headers for C Library Facilities" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">cassert</code></td><td align="left"><code class="filename">cerrno</code></td><td align="left"><code class="filename">cctype</code></td><td align="left"><code class="filename">cfloat</code></td><td align="left"><code class="filename">ciso646</code></td></tr><tr><td align="left"><code class="filename">climits</code></td><td align="left"><code class="filename">clocale</code></td><td align="left"><code class="filename">cmath</code></td><td align="left"><code class="filename">csetjmp</code></td><td align="left"><code class="filename">csignal</code></td></tr><tr><td align="left"><code class="filename">cstdarg</code></td><td align="left"><code class="filename">cstddef</code></td><td align="left"><code class="filename">cstdio</code></td><td align="left"><code class="filename">cstdlib</code></td><td align="left"><code class="filename">cstring</code></td></tr><tr><td align="left"><code class="filename">ctime</code></td><td align="left"><code class="filename">cwchar</code></td><td align="left"><code class="filename">cwctype</code></td><td class="auto-generated"> </td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p>

3359

+ </p><div class="table"><a id="idm270002453792"></a><p class="title"><strong>Table 3.2. C++ 1998 Library Headers</strong></p><div class="table-contents"><table summary="C++ 1998 Library Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="filename">bitset</code></td><td align="left"><code class="filename">complex</code></td><td align="left"><code class="filename">deque</code></td><td align="left"><code class="filename">exception</code></td></tr><tr><td align="left"><code class="filename">fstream</code></td><td align="left"><code class="filename">functional</code></td><td align="left"><code class="filename">iomanip</code></td><td align="left"><code class="filename">ios</code></td><td align="left"><code class="filename">iosfwd</code></td></tr><tr><td align="left"><code class="filename">iostream</code></td><td align="left"><code class="filename">istream</code></td><td align="left"><code class="filename">iterator</code></td><td align="left"><code class="filename">limits</code></td><td align="left"><code class="filename">list</code></td></tr><tr><td align="left"><code class="filename">locale</code></td><td align="left"><code class="filename">map</code></td><td align="left"><code class="filename">memory</code></td><td align="left"><code class="filename">new</code></td><td align="left"><code class="filename">numeric</code></td></tr><tr><td align="left"><code class="filename">ostream</code></td><td align="left"><code class="filename">queue</code></td><td align="left"><code class="filename">set</code></td><td align="left"><code class="filename">sstream</code></td><td align="left"><code class="filename">stack</code></td></tr><tr><td align="left"><code class="filename">stdexcept</code></td><td align="left"><code class="filename">streambuf</code></td><td align="left"><code class="filename">string</code></td><td align="left"><code class="filename">utility</code></td><td align="left"><code class="filename">typeinfo</code></td></tr><tr><td align="left"><code class="filename">valarray</code></td><td align="left"><code class="filename">vector</code></td><td class="auto-generated"> </td><td class="auto-generated"> </td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="idm270002417312"></a><p class="title"><strong>Table 3.3. C++ 1998 Library Headers for C Library Facilities</strong></p><div class="table-contents"><table summary="C++ 1998 Library Headers for C Library Facilities" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">cassert</code></td><td align="left"><code class="filename">cerrno</code></td><td align="left"><code class="filename">cctype</code></td><td align="left"><code class="filename">cfloat</code></td><td align="left"><code class="filename">ciso646</code></td></tr><tr><td align="left"><code class="filename">climits</code></td><td align="left"><code class="filename">clocale</code></td><td align="left"><code class="filename">cmath</code></td><td align="left"><code class="filename">csetjmp</code></td><td align="left"><code class="filename">csignal</code></td></tr><tr><td align="left"><code class="filename">cstdarg</code></td><td align="left"><code class="filename">cstddef</code></td><td align="left"><code class="filename">cstdio</code></td><td align="left"><code class="filename">cstdlib</code></td><td align="left"><code class="filename">cstring</code></td></tr><tr><td align="left"><code class="filename">ctime</code></td><td align="left"><code class="filename">cwchar</code></td><td align="left"><code class="filename">cwctype</code></td><td class="auto-generated"> </td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p>

3360

C++11 include files. These are only available in C++11 compilation

3361

mode, i.e. <code class="literal">-std=c++11</code> or <code class="literal">-std=gnu++11</code>.

3362

-</p><p></p><div class="table"><a id="idp13140576"></a><p class="title"><strong>Table 3.4. C++ 2011 Library Headers</strong></p><div class="table-contents"><table summary="C++ 2011 Library Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="filename">array</code></td><td align="left"><code class="filename">bitset</code></td><td align="left"><code class="filename">chrono</code></td><td align="left"><code class="filename">complex</code></td></tr><tr><td align="left"><code class="filename">condition_variable</code></td><td align="left"><code class="filename">deque</code></td><td align="left"><code class="filename">exception</code></td><td align="left"><code class="filename">forward_list</code></td><td align="left"><code class="filename">fstream</code></td></tr><tr><td align="left"><code class="filename">functional</code></td><td align="left"><code class="filename">future</code></td><td align="left"><code class="filename">initalizer_list</code></td><td align="left"><code class="filename">iomanip</code></td><td align="left"><code class="filename">ios</code></td></tr><tr><td align="left"><code class="filename">iosfwd</code></td><td align="left"><code class="filename">iostream</code></td><td align="left"><code class="filename">istream</code></td><td align="left"><code class="filename">iterator</code></td><td align="left"><code class="filename">limits</code></td></tr><tr><td align="left"><code class="filename">list</code></td><td align="left"><code class="filename">locale</code></td><td align="left"><code class="filename">map</code></td><td align="left"><code class="filename">memory</code></td><td align="left"><code class="filename">mutex</code></td></tr><tr><td align="left"><code class="filename">new</code></td><td align="left"><code class="filename">numeric</code></td><td align="left"><code class="filename">ostream</code></td><td align="left"><code class="filename">queue</code></td><td align="left"><code class="filename">random</code></td></tr><tr><td align="left"><code class="filename">ratio</code></td><td align="left"><code class="filename">regex</code></td><td align="left"><code class="filename">set</code></td><td align="left"><code class="filename">sstream</code></td><td align="left"><code class="filename">stack</code></td></tr><tr><td align="left"><code class="filename">stdexcept</code></td><td align="left"><code class="filename">streambuf</code></td><td align="left"><code class="filename">string</code></td><td align="left"><code class="filename">system_error</code></td><td align="left"><code class="filename">thread</code></td></tr><tr><td align="left"><code class="filename">tuple</code></td><td align="left"><code class="filename">type_traits</code></td><td align="left"><code class="filename">typeinfo</code></td><td align="left"><code class="filename">unordered_map</code></td><td align="left"><code class="filename">unordered_set</code></td></tr><tr><td align="left"><code class="filename">utility</code></td><td align="left"><code class="filename">valarray</code></td><td align="left"><code class="filename">vector</code></td><td class="auto-generated"> </td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="idp13192016"></a><p class="title"><strong>Table 3.5. C++ 2011 Library Headers for C Library Facilities</strong></p><div class="table-contents"><table summary="C++ 2011 Library Headers for C Library Facilities" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">cassert</code></td><td align="left"><code class="filename">ccomplex</code></td><td align="left"><code class="filename">cctype</code></td><td align="left"><code class="filename">cerrno</code></td><td align="left"><code class="filename">cfenv</code></td></tr><tr><td align="left"><code class="filename">cfloat</code></td><td align="left"><code class="filename">cinttypes</code></td><td align="left"><code class="filename">ciso646</code></td><td align="left"><code class="filename">climits</code></td><td align="left"><code class="filename">clocale</code></td></tr><tr><td align="left"><code class="filename">cmath</code></td><td align="left"><code class="filename">csetjmp</code></td><td align="left"><code class="filename">csignal</code></td><td align="left"><code class="filename">cstdarg</code></td><td align="left"><code class="filename">cstdbool</code></td></tr><tr><td align="left"><code class="filename">cstddef</code></td><td align="left"><code class="filename">cstdint</code></td><td align="left"><code class="filename">cstdlib</code></td><td align="left"><code class="filename">cstdio</code></td><td align="left"><code class="filename">cstring</code></td></tr><tr><td align="left"><code class="filename">ctgmath</code></td><td align="left"><code class="filename">ctime</code></td><td align="left"><code class="filename">cuchar</code></td><td align="left"><code class="filename">cwchar</code></td><td align="left"><code class="filename">cwctype</code></td></tr></tbody></table></div></div><br class="table-break" /><p>

3363

+</p><p></p><div class="table"><a id="idm270002392576"></a><p class="title"><strong>Table 3.4. C++ 2011 Library Headers</strong></p><div class="table-contents"><table summary="C++ 2011 Library Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="filename">array</code></td><td align="left"><code class="filename">bitset</code></td><td align="left"><code class="filename">chrono</code></td><td align="left"><code class="filename">complex</code></td></tr><tr><td align="left"><code class="filename">condition_variable</code></td><td align="left"><code class="filename">deque</code></td><td align="left"><code class="filename">exception</code></td><td align="left"><code class="filename">forward_list</code></td><td align="left"><code class="filename">fstream</code></td></tr><tr><td align="left"><code class="filename">functional</code></td><td align="left"><code class="filename">future</code></td><td align="left"><code class="filename">initalizer_list</code></td><td align="left"><code class="filename">iomanip</code></td><td align="left"><code class="filename">ios</code></td></tr><tr><td align="left"><code class="filename">iosfwd</code></td><td align="left"><code class="filename">iostream</code></td><td align="left"><code class="filename">istream</code></td><td align="left"><code class="filename">iterator</code></td><td align="left"><code class="filename">limits</code></td></tr><tr><td align="left"><code class="filename">list</code></td><td align="left"><code class="filename">locale</code></td><td align="left"><code class="filename">map</code></td><td align="left"><code class="filename">memory</code></td><td align="left"><code class="filename">mutex</code></td></tr><tr><td align="left"><code class="filename">new</code></td><td align="left"><code class="filename">numeric</code></td><td align="left"><code class="filename">ostream</code></td><td align="left"><code class="filename">queue</code></td><td align="left"><code class="filename">random</code></td></tr><tr><td align="left"><code class="filename">ratio</code></td><td align="left"><code class="filename">regex</code></td><td align="left"><code class="filename">set</code></td><td align="left"><code class="filename">sstream</code></td><td align="left"><code class="filename">stack</code></td></tr><tr><td align="left"><code class="filename">stdexcept</code></td><td align="left"><code class="filename">streambuf</code></td><td align="left"><code class="filename">string</code></td><td align="left"><code class="filename">system_error</code></td><td align="left"><code class="filename">thread</code></td></tr><tr><td align="left"><code class="filename">tuple</code></td><td align="left"><code class="filename">type_traits</code></td><td align="left"><code class="filename">typeinfo</code></td><td align="left"><code class="filename">unordered_map</code></td><td align="left"><code class="filename">unordered_set</code></td></tr><tr><td align="left"><code class="filename">utility</code></td><td align="left"><code class="filename">valarray</code></td><td align="left"><code class="filename">vector</code></td><td class="auto-generated"> </td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="idm270002341136"></a><p class="title"><strong>Table 3.5. C++ 2011 Library Headers for C Library Facilities</strong></p><div class="table-contents"><table summary="C++ 2011 Library Headers for C Library Facilities" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">cassert</code></td><td align="left"><code class="filename">ccomplex</code></td><td align="left"><code class="filename">cctype</code></td><td align="left"><code class="filename">cerrno</code></td><td align="left"><code class="filename">cfenv</code></td></tr><tr><td align="left"><code class="filename">cfloat</code></td><td align="left"><code class="filename">cinttypes</code></td><td align="left"><code class="filename">ciso646</code></td><td align="left"><code class="filename">climits</code></td><td align="left"><code class="filename">clocale</code></td></tr><tr><td align="left"><code class="filename">cmath</code></td><td align="left"><code class="filename">csetjmp</code></td><td align="left"><code class="filename">csignal</code></td><td align="left"><code class="filename">cstdarg</code></td><td align="left"><code class="filename">cstdbool</code></td></tr><tr><td align="left"><code class="filename">cstddef</code></td><td align="left"><code class="filename">cstdint</code></td><td align="left"><code class="filename">cstdlib</code></td><td align="left"><code class="filename">cstdio</code></td><td align="left"><code class="filename">cstring</code></td></tr><tr><td align="left"><code class="filename">ctgmath</code></td><td align="left"><code class="filename">ctime</code></td><td align="left"><code class="filename">cuchar</code></td><td align="left"><code class="filename">cwchar</code></td><td align="left"><code class="filename">cwctype</code></td></tr></tbody></table></div></div><br class="table-break" /><p>

3364

In addition, TR1 includes as:

3365

-</p><div class="table"><a id="idp13221904"></a><p class="title"><strong>Table 3.6. C++ TR 1 Library Headers</strong></p><div class="table-contents"><table summary="C++ TR 1 Library Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">tr1/array</code></td><td align="left"><code class="filename">tr1/complex</code></td><td align="left"><code class="filename">tr1/memory</code></td><td align="left"><code class="filename">tr1/functional</code></td><td align="left"><code class="filename">tr1/random</code></td></tr><tr><td align="left"><code class="filename">tr1/regex</code></td><td align="left"><code class="filename">tr1/tuple</code></td><td align="left"><code class="filename">tr1/type_traits</code></td><td align="left"><code class="filename">tr1/unordered_map</code></td><td align="left"><code class="filename">tr1/unordered_set</code></td></tr><tr><td align="left"><code class="filename">tr1/utility</code></td><td class="auto-generated"> </td><td class="auto-generated"> </td><td class="auto-generated"> </td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="idp13238832"></a><p class="title"><strong>Table 3.7. C++ TR 1 Library Headers for C Library Facilities</strong></p><div class="table-contents"><table summary="C++ TR 1 Library Headers for C Library Facilities" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">tr1/ccomplex</code></td><td align="left"><code class="filename">tr1/cfenv</code></td><td align="left"><code class="filename">tr1/cfloat</code></td><td align="left"><code class="filename">tr1/cmath</code></td><td align="left"><code class="filename">tr1/cinttypes</code></td></tr><tr><td align="left"><code class="filename">tr1/climits</code></td><td align="left"><code class="filename">tr1/cstdarg</code></td><td align="left"><code class="filename">tr1/cstdbool</code></td><td align="left"><code class="filename">tr1/cstdint</code></td><td align="left"><code class="filename">tr1/cstdio</code></td></tr><tr><td align="left"><code class="filename">tr1/cstdlib</code></td><td align="left"><code class="filename">tr1/ctgmath</code></td><td align="left"><code class="filename">tr1/ctime</code></td><td align="left"><code class="filename">tr1/cwchar</code></td><td align="left"><code class="filename">tr1/cwctype</code></td></tr></tbody></table></div></div><br class="table-break" /><p>Decimal floating-point arithmetic is available if the C++

3366

+</p><div class="table"><a id="idm270002311248"></a><p class="title"><strong>Table 3.6. C++ TR 1 Library Headers</strong></p><div class="table-contents"><table summary="C++ TR 1 Library Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">tr1/array</code></td><td align="left"><code class="filename">tr1/complex</code></td><td align="left"><code class="filename">tr1/memory</code></td><td align="left"><code class="filename">tr1/functional</code></td><td align="left"><code class="filename">tr1/random</code></td></tr><tr><td align="left"><code class="filename">tr1/regex</code></td><td align="left"><code class="filename">tr1/tuple</code></td><td align="left"><code class="filename">tr1/type_traits</code></td><td align="left"><code class="filename">tr1/unordered_map</code></td><td align="left"><code class="filename">tr1/unordered_set</code></td></tr><tr><td align="left"><code class="filename">tr1/utility</code></td><td class="auto-generated"> </td><td class="auto-generated"> </td><td class="auto-generated"> </td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="idm270002294320"></a><p class="title"><strong>Table 3.7. C++ TR 1 Library Headers for C Library Facilities</strong></p><div class="table-contents"><table summary="C++ TR 1 Library Headers for C Library Facilities" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">tr1/ccomplex</code></td><td align="left"><code class="filename">tr1/cfenv</code></td><td align="left"><code class="filename">tr1/cfloat</code></td><td align="left"><code class="filename">tr1/cmath</code></td><td align="left"><code class="filename">tr1/cinttypes</code></td></tr><tr><td align="left"><code class="filename">tr1/climits</code></td><td align="left"><code class="filename">tr1/cstdarg</code></td><td align="left"><code class="filename">tr1/cstdbool</code></td><td align="left"><code class="filename">tr1/cstdint</code></td><td align="left"><code class="filename">tr1/cstdio</code></td></tr><tr><td align="left"><code class="filename">tr1/cstdlib</code></td><td align="left"><code class="filename">tr1/ctgmath</code></td><td align="left"><code class="filename">tr1/ctime</code></td><td align="left"><code class="filename">tr1/cwchar</code></td><td align="left"><code class="filename">tr1/cwctype</code></td></tr></tbody></table></div></div><br class="table-break" /><p>Decimal floating-point arithmetic is available if the C++

3367

compiler supports scalar decimal floating-point types defined via

3368

<code class="code">__attribute__((mode(SD|DD|LD)))</code>.

3369

-</p><div class="table"><a id="idp13259904"></a><p class="title"><strong>Table 3.8. C++ TR 24733 Decimal Floating-Point Header</strong></p><div class="table-contents"><table summary="C++ TR 24733 Decimal Floating-Point Header" border="1"><colgroup><col align="left" class="c1" /></colgroup><tbody><tr><td align="left"><code class="filename">decimal/decimal</code></td></tr></tbody></table></div></div><br class="table-break" /><p>

3370

+</p><div class="table"><a id="idm270002273248"></a><p class="title"><strong>Table 3.8. C++ TR 24733 Decimal Floating-Point Header</strong></p><div class="table-contents"><table summary="C++ TR 24733 Decimal Floating-Point Header" border="1"><colgroup><col align="left" class="c1" /></colgroup><tbody><tr><td align="left"><code class="filename">decimal/decimal</code></td></tr></tbody></table></div></div><br class="table-break" /><p>

3371

Also included are files for the C++ ABI interface:

3372

-</p><div class="table"><a id="idp13265424"></a><p class="title"><strong>Table 3.9. C++ ABI Headers</strong></p><div class="table-contents"><table summary="C++ ABI Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><tbody><tr><td align="left"><code class="filename">cxxabi.h</code></td><td align="left"><code class="filename">cxxabi_forced.h</code></td></tr></tbody></table></div></div><br class="table-break" /><p>

3373

+</p><div class="table"><a id="idm270002267728"></a><p class="title"><strong>Table 3.9. C++ ABI Headers</strong></p><div class="table-contents"><table summary="C++ ABI Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><tbody><tr><td align="left"><code class="filename">cxxabi.h</code></td><td align="left"><code class="filename">cxxabi_forced.h</code></td></tr></tbody></table></div></div><br class="table-break" /><p>

3374

And a large variety of extensions.

3375

-</p><div class="table"><a id="idp13271824"></a><p class="title"><strong>Table 3.10. Extension Headers</strong></p><div class="table-contents"><table summary="Extension Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">ext/algorithm</code></td><td align="left"><code class="filename">ext/atomicity.h</code></td><td align="left"><code class="filename">ext/array_allocator.h</code></td><td align="left"><code class="filename">ext/bitmap_allocator.h</code></td><td align="left"><code class="filename">ext/cast.h</code></td></tr><tr><td align="left"><code class="filename">ext/codecvt_specializations.h</code></td><td align="left"><code class="filename">ext/concurrence.h</code></td><td align="left"><code class="filename">ext/debug_allocator.h</code></td><td align="left"><code class="filename">ext/enc_filebuf.h</code></td><td align="left"><code class="filename">ext/extptr_allocator.h</code></td></tr><tr><td align="left"><code class="filename">ext/functional</code></td><td align="left"><code class="filename">ext/iterator</code></td><td align="left"><code class="filename">ext/malloc_allocator.h</code></td><td align="left"><code class="filename">ext/memory</code></td><td align="left"><code class="filename">ext/mt_allocator.h</code></td></tr><tr><td align="left"><code class="filename">ext/new_allocator.h</code></td><td align="left"><code class="filename">ext/numeric</code></td><td align="left"><code class="filename">ext/numeric_traits.h</code></td><td align="left"><code class="filename">ext/pb_ds/assoc_container.h</code></td><td align="left"><code class="filename">ext/pb_ds/priority_queue.h</code></td></tr><tr><td align="left"><code class="filename">ext/pod_char_traits.h</code></td><td align="left"><code class="filename">ext/pool_allocator.h</code></td><td align="left"><code class="filename">ext/rb_tree</code></td><td align="left"><code class="filename">ext/rope</code></td><td align="left"><code class="filename">ext/slist</code></td></tr><tr><td align="left"><code class="filename">ext/stdio_filebuf.h</code></td><td align="left"><code class="filename">ext/stdio_sync_filebuf.h</code></td><td align="left"><code class="filename">ext/throw_allocator.h</code></td><td align="left"><code class="filename">ext/typelist.h</code></td><td align="left"><code class="filename">ext/type_traits.h</code></td></tr><tr><td align="left"><code class="filename">ext/vstring.h</code></td><td class="auto-generated"> </td><td class="auto-generated"> </td><td class="auto-generated"> </td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="idp13307552"></a><p class="title"><strong>Table 3.11. Extension Debug Headers</strong></p><div class="table-contents"><table summary="Extension Debug Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">debug/bitset</code></td><td align="left"><code class="filename">debug/deque</code></td><td align="left"><code class="filename">debug/list</code></td><td align="left"><code class="filename">debug/map</code></td><td align="left"><code class="filename">debug/set</code></td></tr><tr><td align="left"><code class="filename">debug/string</code></td><td align="left"><code class="filename">debug/unordered_map</code></td><td align="left"><code class="filename">debug/unordered_set</code></td><td align="left"><code class="filename">debug/vector</code></td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="idp13322320"></a><p class="title"><strong>Table 3.12. Extension Profile Headers</strong></p><div class="table-contents"><table summary="Extension Profile Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><tbody><tr><td align="left"><code class="filename">profile/bitset</code></td><td align="left"><code class="filename">profile/deque</code></td><td align="left"><code class="filename">profile/list</code></td><td align="left"><code class="filename">profile/map</code></td></tr><tr><td align="left"><code class="filename">profile/set</code></td><td align="left"><code class="filename">profile/unordered_map</code></td><td align="left"><code class="filename">profile/unordered_set</code></td><td align="left"><code class="filename">profile/vector</code></td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="idp13335696"></a><p class="title"><strong>Table 3.13. Extension Parallel Headers</strong></p><div class="table-contents"><table summary="Extension Parallel Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><tbody><tr><td align="left"><code class="filename">parallel/algorithm</code></td><td align="left"><code class="filename">parallel/numeric</code></td></tr></tbody></table></div></div><br class="table-break" /></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.intro.using.headers.mixing"></a>Mixing Headers</h3></div></div></div><p> A few simple rules.

3376

+</p><div class="table"><a id="idm270002261328"></a><p class="title"><strong>Table 3.10. Extension Headers</strong></p><div class="table-contents"><table summary="Extension Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">ext/algorithm</code></td><td align="left"><code class="filename">ext/atomicity.h</code></td><td align="left"><code class="filename">ext/array_allocator.h</code></td><td align="left"><code class="filename">ext/bitmap_allocator.h</code></td><td align="left"><code class="filename">ext/cast.h</code></td></tr><tr><td align="left"><code class="filename">ext/codecvt_specializations.h</code></td><td align="left"><code class="filename">ext/concurrence.h</code></td><td align="left"><code class="filename">ext/debug_allocator.h</code></td><td align="left"><code class="filename">ext/enc_filebuf.h</code></td><td align="left"><code class="filename">ext/extptr_allocator.h</code></td></tr><tr><td align="left"><code class="filename">ext/functional</code></td><td align="left"><code class="filename">ext/iterator</code></td><td align="left"><code class="filename">ext/malloc_allocator.h</code></td><td align="left"><code class="filename">ext/memory</code></td><td align="left"><code class="filename">ext/mt_allocator.h</code></td></tr><tr><td align="left"><code class="filename">ext/new_allocator.h</code></td><td align="left"><code class="filename">ext/numeric</code></td><td align="left"><code class="filename">ext/numeric_traits.h</code></td><td align="left"><code class="filename">ext/pb_ds/assoc_container.h</code></td><td align="left"><code class="filename">ext/pb_ds/priority_queue.h</code></td></tr><tr><td align="left"><code class="filename">ext/pod_char_traits.h</code></td><td align="left"><code class="filename">ext/pool_allocator.h</code></td><td align="left"><code class="filename">ext/rb_tree</code></td><td align="left"><code class="filename">ext/rope</code></td><td align="left"><code class="filename">ext/slist</code></td></tr><tr><td align="left"><code class="filename">ext/stdio_filebuf.h</code></td><td align="left"><code class="filename">ext/stdio_sync_filebuf.h</code></td><td align="left"><code class="filename">ext/throw_allocator.h</code></td><td align="left"><code class="filename">ext/typelist.h</code></td><td align="left"><code class="filename">ext/type_traits.h</code></td></tr><tr><td align="left"><code class="filename">ext/vstring.h</code></td><td class="auto-generated"> </td><td class="auto-generated"> </td><td class="auto-generated"> </td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="idm270002225600"></a><p class="title"><strong>Table 3.11. Extension Debug Headers</strong></p><div class="table-contents"><table summary="Extension Debug Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">debug/bitset</code></td><td align="left"><code class="filename">debug/deque</code></td><td align="left"><code class="filename">debug/list</code></td><td align="left"><code class="filename">debug/map</code></td><td align="left"><code class="filename">debug/set</code></td></tr><tr><td align="left"><code class="filename">debug/string</code></td><td align="left"><code class="filename">debug/unordered_map</code></td><td align="left"><code class="filename">debug/unordered_set</code></td><td align="left"><code class="filename">debug/vector</code></td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="idm270002210832"></a><p class="title"><strong>Table 3.12. Extension Profile Headers</strong></p><div class="table-contents"><table summary="Extension Profile Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><tbody><tr><td align="left"><code class="filename">profile/bitset</code></td><td align="left"><code class="filename">profile/deque</code></td><td align="left"><code class="filename">profile/list</code></td><td align="left"><code class="filename">profile/map</code></td></tr><tr><td align="left"><code class="filename">profile/set</code></td><td align="left"><code class="filename">profile/unordered_map</code></td><td align="left"><code class="filename">profile/unordered_set</code></td><td align="left"><code class="filename">profile/vector</code></td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="idm270002197456"></a><p class="title"><strong>Table 3.13. Extension Parallel Headers</strong></p><div class="table-contents"><table summary="Extension Parallel Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><tbody><tr><td align="left"><code class="filename">parallel/algorithm</code></td><td align="left"><code class="filename">parallel/numeric</code></td></tr></tbody></table></div></div><br class="table-break" /></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.intro.using.headers.mixing"></a>Mixing Headers</h3></div></div></div><p> A few simple rules.

3377

</p><p>First, mixing different dialects of the standard headers is not

3378

possible. It's an all-or-nothing affair. Thus, code like

3379

</p><pre class="programlisting">

3380

Index: libstdc++-v3/doc/html/manual/using_namespaces.html

3381

===================================================================

3382

--- a/src/libstdc++-v3/doc/html/manual/using_namespaces.html (.../tags/gcc_4_8_2_release)

3383

+++ b/src/libstdc++-v3/doc/html/manual/using_namespaces.html (.../branches/gcc-4_8-branch)

3384

@@ -1,5 +1,5 @@

3385

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

3386

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Namespaces</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_macros.html" title="Macros" /><link rel="next" href="using_dynamic_or_shared.html" title="Linking" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Namespaces</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_macros.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="using_dynamic_or_shared.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.namespaces"></a>Namespaces</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.intro.using.namespaces.all"></a>Available Namespaces</h3></div></div></div><p> There are three main namespaces.

3387

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Namespaces</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_macros.html" title="Macros" /><link rel="next" href="using_dynamic_or_shared.html" title="Linking" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Namespaces</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_macros.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="using_dynamic_or_shared.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.namespaces"></a>Namespaces</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.intro.using.namespaces.all"></a>Available Namespaces</h3></div></div></div><p> There are three main namespaces.

3388

</p><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p>std</p><p>The ISO C++ standards specify that "all library entities are defined

3389

within namespace std." This includes namespaces nested

3390

within <code class="code">namespace std</code>, such as <code class="code">namespace

3391

Index: libstdc++-v3/doc/html/manual/debug.html

3392

===================================================================

3393

--- a/src/libstdc++-v3/doc/html/manual/debug.html (.../tags/gcc_4_8_2_release)

3394

+++ b/src/libstdc++-v3/doc/html/manual/debug.html (.../branches/gcc-4_8-branch)

3395

@@ -1,5 +1,5 @@

3396

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

3397

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Debugging Support</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="C++, debug" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_exceptions.html" title="Exceptions" /><link rel="next" href="std_contents.html" title="Part II. Standard Contents" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Debugging Support</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_exceptions.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="std_contents.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.debug"></a>Debugging Support</h2></div></div></div><p>

3398

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Debugging Support</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, debug" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_exceptions.html" title="Exceptions" /><link rel="next" href="std_contents.html" title="Part II. Standard Contents" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Debugging Support</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_exceptions.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="std_contents.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.debug"></a>Debugging Support</h2></div></div></div><p>

3399

There are numerous things that can be done to improve the ease with

3400

which C++ binaries are debugged when using the GNU tool chain. Here

3401

are some of them.

3402

@@ -161,7 +161,7 @@

3403

DRD</a>,

3404

3405

Helgrind</a>, and

3406

- <a class="link" href="http://code.google.com/p/data-race-test" target="_top">

3407

+ <a class="link" href="http://code.google.com/p/data-race-test/" target="_top">

3408

ThreadSanitizer</a>.

3409

</p><p>

3410

With DRD, Helgrind and ThreadSanitizer you will need to define

3411

Index: libstdc++-v3/doc/html/manual/localization.html

3412

===================================================================

3413

--- a/src/libstdc++-v3/doc/html/manual/localization.html (.../tags/gcc_4_8_2_release)

3414

+++ b/src/libstdc++-v3/doc/html/manual/localization.html (.../branches/gcc-4_8-branch)

3415

@@ -1,5 +1,5 @@

3416

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

3417

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 8. Localization</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II. Standard Contents" /><link rel="prev" href="strings.html" title="Chapter 7. Strings" /><link rel="next" href="facets.html" title="Facets" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 8.

3418

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 8. Localization</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II. Standard Contents" /><link rel="prev" href="strings.html" title="Chapter 7. Strings" /><link rel="next" href="facets.html" title="Facets" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 8.

3419

Localization

3420

3421

</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="strings.html">Prev</a> </td><th width="60%" align="center">Part II.

3422

@@ -6,8 +6,8 @@

3423

Standard Contents

3424

</th><td width="20%" align="right"> <a accesskey="n" href="facets.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="std.localization"></a>Chapter 8.

3425

Localization

3426

- <a id="idp15701088" class="indexterm"></a>

3427

-</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="localization.html#std.localization.locales">Locales</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#std.localization.locales.locale">locale</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#locales.locale.req">Requirements</a></span></dt><dt><span class="section"><a href="localization.html#locales.locale.design">Design</a></span></dt><dt><span class="section"><a href="localization.html#locales.locale.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#locale.impl.c">Interacting with "C" locales</a></span></dt></dl></dd><dt><span class="section"><a href="localization.html#locales.locale.future">Future</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="facets.html">Facets</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#std.localization.facet.ctype">ctype</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.ctype.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#idp15778336">Specializations</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.ctype.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#std.localization.facet.codecvt">codecvt</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.codecvt.req">Requirements</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.design">Design</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#codecvt.design.wchar_t_size"><span class="type">wchar_t</span> Size</a></span></dt><dt><span class="section"><a href="facets.html#codecvt.design.unicode">Support for Unicode</a></span></dt><dt><span class="section"><a href="facets.html#codecvt.design.issues">Other Issues</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.codecvt.impl">Implementation</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.use">Use</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#manual.localization.facet.messages">messages</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.messages.req">Requirements</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.design">Design</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#messages.impl.models">Models</a></span></dt><dt><span class="section"><a href="facets.html#messages.impl.gnu">The GNU Model</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.messages.use">Use</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.future">Future</a></span></dt></dl></dd></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.localization.locales"></a>Locales</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="std.localization.locales.locale"></a>locale</h3></div></div></div><p>

3428

+ <a id="idm269999830208" class="indexterm"></a>

3429

+</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="localization.html#std.localization.locales">Locales</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#std.localization.locales.locale">locale</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#locales.locale.req">Requirements</a></span></dt><dt><span class="section"><a href="localization.html#locales.locale.design">Design</a></span></dt><dt><span class="section"><a href="localization.html#locales.locale.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#locale.impl.c">Interacting with "C" locales</a></span></dt></dl></dd><dt><span class="section"><a href="localization.html#locales.locale.future">Future</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="facets.html">Facets</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#std.localization.facet.ctype">ctype</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.ctype.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#idm269999753024">Specializations</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.ctype.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#std.localization.facet.codecvt">codecvt</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.codecvt.req">Requirements</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.design">Design</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#codecvt.design.wchar_t_size"><span class="type">wchar_t</span> Size</a></span></dt><dt><span class="section"><a href="facets.html#codecvt.design.unicode">Support for Unicode</a></span></dt><dt><span class="section"><a href="facets.html#codecvt.design.issues">Other Issues</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.codecvt.impl">Implementation</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.use">Use</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#manual.localization.facet.messages">messages</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.messages.req">Requirements</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.design">Design</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#messages.impl.models">Models</a></span></dt><dt><span class="section"><a href="facets.html#messages.impl.gnu">The GNU Model</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.messages.use">Use</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.future">Future</a></span></dt></dl></dd></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.localization.locales"></a>Locales</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="std.localization.locales.locale"></a>locale</h3></div></div></div><p>

3430

Describes the basic locale object, including nested

3431

classes id, facet, and the reference-counted implementation object,

3432

class _Impl.

3433

@@ -402,18 +402,18 @@

3434

What should non-required facet instantiations do? If the

3435

generic implementation is provided, then how to end-users

3436

provide specializations?

3437

- </p></li></ul></div></div><div class="bibliography"><div class="titlepage"><div><div><h4 class="title"><a id="locales.locale.biblio"></a>Bibliography</h4></div></div></div><div class="biblioentry"><a id="idp15744064"></a><p><span class="citetitle"><em class="citetitle">

3438

+ </p></li></ul></div></div><div class="bibliography"><div class="titlepage"><div><div><h4 class="title"><a id="locales.locale.biblio"></a>Bibliography</h4></div></div></div><div class="biblioentry"><a id="idm269999787232"></a><p><span class="citetitle"><em class="citetitle">

3439

The GNU C Library

3440

</em>. </span><span class="author"><span class="firstname">Roland</span> <span class="surname">McGrath</span>. </span><span class="author"><span class="firstname">Ulrich</span> <span class="surname">Drepper</span>. </span><span class="copyright">Copyright © 2007 FSF. </span><span class="pagenums">

3441

Chapters 6 Character Set Handling and 7 Locales and

3442

Internationalization

3443

- . </span></p></div><div class="biblioentry"><a id="idp15748832"></a><p><span class="citetitle"><em class="citetitle">

3444

+ . </span></p></div><div class="biblioentry"><a id="idm269999782464"></a><p><span class="citetitle"><em class="citetitle">

3445

Correspondence

3446

- </em>. </span><span class="author"><span class="firstname">Ulrich</span> <span class="surname">Drepper</span>. </span><span class="copyright">Copyright © 2002 . </span></p></div><div class="biblioentry"><a id="idp15751920"></a><p><span class="citetitle"><em class="citetitle">

3447

+ </em>. </span><span class="author"><span class="firstname">Ulrich</span> <span class="surname">Drepper</span>. </span><span class="copyright">Copyright © 2002 . </span></p></div><div class="biblioentry"><a id="idm269999779376"></a><p><span class="citetitle"><em class="citetitle">

3448

ISO/IEC 14882:1998 Programming languages - C++

3449

3450

3451

ISO/IEC 9899:1999 Programming languages - C

3452

3453

3454

3455

System Interface Definitions, Issue 7 (IEEE Std. 1003.1-2008)

3456

</a>

3457

@@ -420,11 +420,11 @@

3458

3459

The Open Group/The Institute of Electrical and Electronics

3460

Engineers, Inc.

3461

- . </span></p></div><div class="biblioentry"><a id="idp15759712"></a><p><span class="citetitle"><em class="citetitle">

3462

+ . </span></p></div><div class="biblioentry"><a id="idm269999771584"></a><p><span class="citetitle"><em class="citetitle">

3463

The C++ Programming Language, Special Edition

3464

</em>. </span><span class="author"><span class="firstname">Bjarne</span> <span class="surname">Stroustrup</span>. </span><span class="copyright">Copyright © 2000 Addison Wesley, Inc.. </span><span class="pagenums">Appendix D. </span><span class="publisher"><span class="publishername">

3465

Addison Wesley

3466

- . </span></span></p></div><div class="biblioentry"><a id="idp15764336"></a><p><span class="citetitle"><em class="citetitle">

3467

+ . </span></span></p></div><div class="biblioentry"><a id="idm269999766960"></a><p><span class="citetitle"><em class="citetitle">

3468

Standard C++ IOStreams and Locales

3469

</em>. </span><span class="subtitle">

3470

Advanced Programmer's Guide and Reference

3471

Index: libstdc++-v3/doc/html/manual/ext_algorithms.html

3472

===================================================================

3473

--- a/src/libstdc++-v3/doc/html/manual/ext_algorithms.html (.../tags/gcc_4_8_2_release)

3474

+++ b/src/libstdc++-v3/doc/html/manual/ext_algorithms.html (.../branches/gcc-4_8-branch)

3475

@@ -1,5 +1,5 @@

3476

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

3477

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 25. Algorithms</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III. Extensions" /><link rel="prev" href="ext_utilities.html" title="Chapter 24. Utilities" /><link rel="next" href="ext_numerics.html" title="Chapter 26. Numerics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 25. Algorithms</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_utilities.html">Prev</a> </td><th width="60%" align="center">Part III.

3478

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 25. Algorithms</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III. Extensions" /><link rel="prev" href="ext_utilities.html" title="Chapter 24. Utilities" /><link rel="next" href="ext_numerics.html" title="Chapter 26. Numerics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 25. Algorithms</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_utilities.html">Prev</a> </td><th width="60%" align="center">Part III.

3479

Extensions

3480

3481

</th><td width="20%" align="right"> <a accesskey="n" href="ext_numerics.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.algorithms"></a>Chapter 25. Algorithms</h2></div></div></div><p>25.1.6 (count, count_if) is extended with two more versions of count

3482

Index: libstdc++-v3/doc/html/manual/debug_mode.html

3483

===================================================================

3484

--- a/src/libstdc++-v3/doc/html/manual/debug_mode.html (.../tags/gcc_4_8_2_release)

3485

+++ b/src/libstdc++-v3/doc/html/manual/debug_mode.html (.../branches/gcc-4_8-branch)

3486

@@ -1,8 +1,8 @@

3487

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

3488

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 17. Debug Mode</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="C++, library, debug" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III. Extensions" /><link rel="prev" href="ext_compile_checks.html" title="Chapter 16. Compile Time Checks" /><link rel="next" href="debug_mode_semantics.html" title="Semantics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 17. Debug Mode</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_compile_checks.html">Prev</a> </td><th width="60%" align="center">Part III.

3489

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 17. Debug Mode</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, debug" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III. Extensions" /><link rel="prev" href="ext_compile_checks.html" title="Chapter 16. Compile Time Checks" /><link rel="next" href="debug_mode_semantics.html" title="Semantics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 17. Debug Mode</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_compile_checks.html">Prev</a> </td><th width="60%" align="center">Part III.

3490

Extensions

3491

3492

-</th><td width="20%" align="right"> <a accesskey="n" href="debug_mode_semantics.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.debug_mode"></a>Chapter 17. Debug Mode</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="debug_mode.html#manual.ext.debug_mode.intro">Intro</a></span></dt><dt><span class="section"><a href="debug_mode_semantics.html">Semantics</a></span></dt><dt><span class="section"><a href="debug_mode_using.html">Using</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_using.html#debug_mode.using.mode">Using the Debug Mode</a></span></dt><dt><span class="section"><a href="debug_mode_using.html#debug_mode.using.specific">Using a Specific Debug Container</a></span></dt></dl></dd><dt><span class="section"><a href="debug_mode_design.html">Design</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.goals">Goals</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods">Methods</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.wrappers">The Wrapper Model</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.safe_iter">Safe Iterators</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.safe_seq">Safe Sequences (Containers)</a></span></dt></dl></dd><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.precond">Precondition Checking</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.coexistence">Release- and debug-mode coexistence</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#methods.coexistence.compile">Compile-time coexistence of release- and debug-mode components</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#methods.coexistence.link">Link- and run-time coexistence of release- and

3493

+</th><td width="20%" align="right"> <a accesskey="n" href="debug_mode_semantics.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.debug_mode"></a>Chapter 17. Debug Mode</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="debug_mode.html#manual.ext.debug_mode.intro">Intro</a></span></dt><dt><span class="section"><a href="debug_mode_semantics.html">Semantics</a></span></dt><dt><span class="section"><a href="debug_mode_using.html">Using</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_using.html#debug_mode.using.mode">Using the Debug Mode</a></span></dt><dt><span class="section"><a href="debug_mode_using.html#debug_mode.using.specific">Using a Specific Debug Container</a></span></dt></dl></dd><dt><span class="section"><a href="debug_mode_design.html">Design</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.goals">Goals</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods">Methods</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.wrappers">The Wrapper Model</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.safe_iter">Safe Iterators</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.safe_seq">Safe Sequences (Containers)</a></span></dt></dl></dd><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.precond">Precondition Checking</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.coexistence">Release- and debug-mode coexistence</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#methods.coexistence.compile">Compile-time coexistence of release- and debug-mode components</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#methods.coexistence.link">Link- and run-time coexistence of release- and

3494

debug-mode components</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#methods.coexistence.alt">Alternatives for Coexistence</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.other">Other Implementations</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.debug_mode.intro"></a>Intro</h2></div></div></div><p>

3495

By default, libstdc++ is built with efficiency in mind, and

3496

therefore performs little or no error checking that is not

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3499

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3500

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3501

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3502

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

3503

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="prev" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="next" href="profile_mode_api.html" title="Extensions for Custom Containers" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="profile_mode.html">Prev</a> </td><th width="60%" align="center">Chapter 19. Profile Mode</th><td width="20%" align="right"> <a accesskey="n" href="profile_mode_api.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.design"></a>Design</h2></div></div></div><p>

3504

-</p><div class="table"><a id="idp16981200"></a><p class="title"><strong>Table 19.1. Profile Code Location</strong></p><div class="table-contents"><table summary="Profile Code Location" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><thead><tr><th align="left">Code Location</th><th align="left">Use</th></tr></thead><tbody><tr><td align="left"><code class="code">libstdc++-v3/include/std/*</code></td><td align="left">Preprocessor code to redirect to profile extension headers.</td></tr><tr><td align="left"><code class="code">libstdc++-v3/include/profile/*</code></td><td align="left">Profile extension public headers (map, vector, ...).</td></tr><tr><td align="left"><code class="code">libstdc++-v3/include/profile/impl/*</code></td><td align="left">Profile extension internals. Implementation files are

3505

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="prev" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="next" href="profile_mode_api.html" title="Extensions for Custom Containers" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="profile_mode.html">Prev</a> </td><th width="60%" align="center">Chapter 19. Profile Mode</th><td width="20%" align="right"> <a accesskey="n" href="profile_mode_api.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.design"></a>Design</h2></div></div></div><p>

3506

+</p><div class="table"><a id="idm269998550064"></a><p class="title"><strong>Table 19.1. Profile Code Location</strong></p><div class="table-contents"><table summary="Profile Code Location" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><thead><tr><th align="left">Code Location</th><th align="left">Use</th></tr></thead><tbody><tr><td align="left"><code class="code">libstdc++-v3/include/std/*</code></td><td align="left">Preprocessor code to redirect to profile extension headers.</td></tr><tr><td align="left"><code class="code">libstdc++-v3/include/profile/*</code></td><td align="left">Profile extension public headers (map, vector, ...).</td></tr><tr><td align="left"><code class="code">libstdc++-v3/include/profile/impl/*</code></td><td align="left">Profile extension internals. Implementation files are

3507

only included from <code class="code">impl/profiler.h</code>, which is the only

3508

file included from the public headers.</td></tr></tbody></table></div></div><br class="table-break" /><p>

3509

</p><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.ext.profile_mode.design.wrapper"></a>Wrapper Model</h3></div></div></div><p>

3510

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3511

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3512

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3513

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3514

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3515

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

3516

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Concurrency</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_dynamic_or_shared.html" title="Linking" /><link rel="next" href="using_exceptions.html" title="Exceptions" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Concurrency</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_dynamic_or_shared.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="using_exceptions.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.concurrency"></a>Concurrency</h2></div></div></div><p>This section discusses issues surrounding the proper compilation

3517

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Concurrency</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_dynamic_or_shared.html" title="Linking" /><link rel="next" href="using_exceptions.html" title="Exceptions" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Concurrency</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_dynamic_or_shared.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="using_exceptions.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.concurrency"></a>Concurrency</h2></div></div></div><p>This section discusses issues surrounding the proper compilation

3518

of multithreaded applications which use the Standard C++

3519

library. This information is GCC-specific since the C++

3520

standard does not address matters of multithreaded applications.

3521

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3522

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3523

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3526

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-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Implementation</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, allocator" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="mt_allocator.html" title="Chapter 20. The mt_allocator" /><link rel="prev" href="mt_allocator_design.html" title="Design Issues" /><link rel="next" href="mt_allocator_ex_single.html" title="Single Thread Example" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Implementation</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="mt_allocator_design.html">Prev</a> </td><th width="60%" align="center">Chapter 20. The mt_allocator</th><td width="20%" align="right"> <a accesskey="n" href="mt_allocator_ex_single.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="allocator.mt.impl"></a>Implementation</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="allocator.mt.tune"></a>Tunable Parameters</h3></div></div></div><p>Certain allocation parameters can be modified, or tuned. There

3528

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Implementation</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, allocator" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="mt_allocator.html" title="Chapter 20. The mt_allocator" /><link rel="prev" href="mt_allocator_design.html" title="Design Issues" /><link rel="next" href="mt_allocator_ex_single.html" title="Single Thread Example" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Implementation</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="mt_allocator_design.html">Prev</a> </td><th width="60%" align="center">Chapter 20. The mt_allocator</th><td width="20%" align="right"> <a accesskey="n" href="mt_allocator_ex_single.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="allocator.mt.impl"></a>Implementation</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="allocator.mt.tune"></a>Tunable Parameters</h3></div></div></div><p>Certain allocation parameters can be modified, or tuned. There

3529

exists a nested <code class="code">struct __pool_base::_Tune</code> that contains all

3530

these parameters, which include settings for

3531

</p><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p>Alignment</p></li><li class="listitem"><p>Maximum bytes before calling <code class="code">::operator new</code> directly</p></li><li class="listitem"><p>Minimum bytes</p></li><li class="listitem"><p>Size of underlying global allocations</p></li><li class="listitem"><p>Maximum number of supported threads</p></li><li class="listitem"><p>Migration of deallocations to the global free list</p></li><li class="listitem"><p>Shunt for global <code class="code">new</code> and <code class="code">delete</code></p></li></ul></div><p>Adjusting parameters for a given instance of an allocator can only

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>

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-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Appendix E. GNU Free Documentation License</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix.html" title="Part IV. Appendices" /><link rel="prev" href="appendix_gpl.html" title="Appendix D. GNU General Public License version 3" /><link rel="next" href="../bk02.html" title="" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Appendix E. GNU Free Documentation License</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="appendix_gpl.html">Prev</a> </td><th width="60%" align="center">Part IV.

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Appendix E. GNU Free Documentation License</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix.html" title="Part IV. Appendices" /><link rel="prev" href="appendix_gpl.html" title="Appendix D. GNU General Public License version 3" /><link rel="next" href="../bk02.html" title="" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Appendix E. GNU Free Documentation License</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="appendix_gpl.html">Prev</a> </td><th width="60%" align="center">Part IV.

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Appendices

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</th><td width="20%" align="right"> <a accesskey="n" href="../bk02.html">Next</a></td></tr></table><hr /></div><div class="appendix"><div class="titlepage"><div><div><h1 class="title"><a id="appendix.gfdl-1.3"></a>GNU Free Documentation License</h1></div></div></div><p>Version 1.3, 3 November 2008</p><p>

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3545

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 9. Containers</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II. Standard Contents" /><link rel="prev" href="facets.html" title="Facets" /><link rel="next" href="associative.html" title="Associative" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 9.

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Containers

3552

3553

</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="facets.html">Prev</a> </td><th width="60%" align="center">Part II.

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Standard Contents

3556

</th><td width="20%" align="right"> <a accesskey="n" href="associative.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="std.containers"></a>Chapter 9.

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Containers

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- <a id="idp16037808" class="indexterm"></a>

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-</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="containers.html#std.containers.sequences">Sequences</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#containers.sequences.list">list</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#sequences.list.size">list::size() is O(n)</a></span></dt></dl></dd><dt><span class="section"><a href="containers.html#containers.sequences.vector">vector</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#sequences.vector.management">Space Overhead Management</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="associative.html">Associative</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#containers.associative.insert_hints">Insertion Hints</a></span></dt><dt><span class="section"><a href="associative.html#containers.associative.bitset">bitset</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#associative.bitset.size_variable">Size Variable</a></span></dt><dt><span class="section"><a href="associative.html#associative.bitset.type_string">Type String</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="unordered_associative.html">Unordered Associative</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.hash">Hash Code</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.cache">Hash Code Caching Policy</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="containers_and_c.html">Interacting with C</a></span></dt><dd><dl><dt><span class="section"><a href="containers_and_c.html#containers.c.vs_array">Containers vs. Arrays</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.containers.sequences"></a>Sequences</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="containers.sequences.list"></a>list</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="sequences.list.size"></a>list::size() is O(n)</h4></div></div></div><p>

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+ <a id="idm269999493408" class="indexterm"></a>

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+</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="containers.html#std.containers.sequences">Sequences</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#containers.sequences.list">list</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#sequences.list.size">list::size() is O(n)</a></span></dt></dl></dd><dt><span class="section"><a href="containers.html#containers.sequences.vector">vector</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#sequences.vector.management">Space Overhead Management</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="associative.html">Associative</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#containers.associative.insert_hints">Insertion Hints</a></span></dt><dt><span class="section"><a href="associative.html#containers.associative.bitset">bitset</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#associative.bitset.size_variable">Size Variable</a></span></dt><dt><span class="section"><a href="associative.html#associative.bitset.type_string">Type String</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="unordered_associative.html">Unordered Associative</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.hash">Hash Code</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.cache">Hash Code Caching Policy</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="containers_and_c.html">Interacting with C</a></span></dt><dd><dl><dt><span class="section"><a href="containers_and_c.html#containers.c.vs_array">Containers vs. Arrays</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.containers.sequences"></a>Sequences</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="containers.sequences.list"></a>list</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="sequences.list.size"></a>list::size() is O(n)</h4></div></div></div><p>

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Yes it is, and that's okay. This is a decision that we preserved

3563

when we imported SGI's STL implementation. The following is

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quoted from <a class="link" href="http://www.sgi.com/tech/stl/FAQ.html" target="_top">their FAQ</a>:

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Index: libstdc++-v3/doc/html/manual/io.html

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>

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-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 13. Input and Output</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II. Standard Contents" /><link rel="prev" href="numerics_and_c.html" title="Interacting with C" /><link rel="next" href="streambufs.html" title="Stream Buffers" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 13.

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 13. Input and Output</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II. Standard Contents" /><link rel="prev" href="numerics_and_c.html" title="Interacting with C" /><link rel="next" href="streambufs.html" title="Stream Buffers" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 13.

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Input and Output

3574

3575

</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="numerics_and_c.html">Prev</a> </td><th width="60%" align="center">Part II.

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@@ -6,8 +6,8 @@

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Standard Contents

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</th><td width="20%" align="right"> <a accesskey="n" href="streambufs.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="std.io"></a>Chapter 13.

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Input and Output

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- <a id="idp16257600" class="indexterm"></a>

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-</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="io.html#std.io.objects">Iostream Objects</a></span></dt><dt><span class="section"><a href="streambufs.html">Stream Buffers</a></span></dt><dd><dl><dt><span class="section"><a href="streambufs.html#io.streambuf.derived">Derived streambuf Classes</a></span></dt><dt><span class="section"><a href="streambufs.html#io.streambuf.buffering">Buffering</a></span></dt></dl></dd><dt><span class="section"><a href="stringstreams.html">Memory Based Streams</a></span></dt><dd><dl><dt><span class="section"><a href="stringstreams.html#std.io.memstreams.compat">Compatibility With strstream</a></span></dt></dl></dd><dt><span class="section"><a href="fstreams.html">File Based Streams</a></span></dt><dd><dl><dt><span class="section"><a href="fstreams.html#std.io.filestreams.copying_a_file">Copying a File</a></span></dt><dt><span class="section"><a href="fstreams.html#std.io.filestreams.binary">Binary Input and Output</a></span></dt></dl></dd><dt><span class="section"><a href="io_and_c.html">Interacting with C</a></span></dt><dd><dl><dt><span class="section"><a href="io_and_c.html#std.io.c.FILE">Using FILE* and file descriptors</a></span></dt><dt><span class="section"><a href="io_and_c.html#std.io.c.sync">Performance</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.io.objects"></a>Iostream Objects</h2></div></div></div><p>To minimize the time you have to wait on the compiler, it's good to

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+ <a id="idm269999273616" class="indexterm"></a>

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+</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="io.html#std.io.objects">Iostream Objects</a></span></dt><dt><span class="section"><a href="streambufs.html">Stream Buffers</a></span></dt><dd><dl><dt><span class="section"><a href="streambufs.html#io.streambuf.derived">Derived streambuf Classes</a></span></dt><dt><span class="section"><a href="streambufs.html#io.streambuf.buffering">Buffering</a></span></dt></dl></dd><dt><span class="section"><a href="stringstreams.html">Memory Based Streams</a></span></dt><dd><dl><dt><span class="section"><a href="stringstreams.html#std.io.memstreams.compat">Compatibility With strstream</a></span></dt></dl></dd><dt><span class="section"><a href="fstreams.html">File Based Streams</a></span></dt><dd><dl><dt><span class="section"><a href="fstreams.html#std.io.filestreams.copying_a_file">Copying a File</a></span></dt><dt><span class="section"><a href="fstreams.html#std.io.filestreams.binary">Binary Input and Output</a></span></dt></dl></dd><dt><span class="section"><a href="io_and_c.html">Interacting with C</a></span></dt><dd><dl><dt><span class="section"><a href="io_and_c.html#std.io.c.FILE">Using FILE* and file descriptors</a></span></dt><dt><span class="section"><a href="io_and_c.html#std.io.c.sync">Performance</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.io.objects"></a>Iostream Objects</h2></div></div></div><p>To minimize the time you have to wait on the compiler, it's good to

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only include the headers you really need. Many people simply include

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<iostream> when they don't need to -- and that can <span class="emphasis"><em>penalize

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your runtime as well.</em></span> Here are some tips on which header to use

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Index: libstdc++-v3/doc/html/manual/index.html

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===================================================================

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>

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-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>The GNU C++ Library Manual</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="../index.html" title="The GNU C++ Library" /><link rel="prev" href="../index.html" title="The GNU C++ Library" /><link rel="next" href="intro.html" title="Part I. Introduction" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">The GNU C++ Library Manual</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="../index.html">Prev</a> </td><th width="60%" align="center"> </th><td width="20%" align="right"> <a accesskey="n" href="intro.html">Next</a></td></tr></table><hr /></div><div class="book"><div class="titlepage"><div><div><h1 class="title"><a id="manual"></a>The GNU C++ Library Manual</h1></div><div><div class="authorgroup"><div class="author"><h3 class="author"><span class="firstname"></span> <span class="surname"></span></h3></div><div class="author"><h3 class="author"><span class="firstname">Paolo</span> <span class="surname">Carlini</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Phil</span> <span class="surname">Edwards</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Doug</span> <span class="surname">Gregor</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Benjamin</span> <span class="surname">Kosnik</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Dhruv</span> <span class="surname">Matani</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Jason</span> <span class="surname">Merrill</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Mark</span> <span class="surname">Mitchell</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Nathan</span> <span class="surname">Myers</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Felix</span> <span class="surname">Natter</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Stefan</span> <span class="surname">Olsson</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Silvius</span> <span class="surname">Rus</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Johannes</span> <span class="surname">Singler</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Ami</span> <span class="surname">Tavory</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Jonathan</span> <span class="surname">Wakely</span></h3></div></div></div><div><p class="copyright">Copyright © 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>The GNU C++ Library Manual</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="../index.html" title="The GNU C++ Library" /><link rel="prev" href="../index.html" title="The GNU C++ Library" /><link rel="next" href="intro.html" title="Part I. Introduction" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">The GNU C++ Library Manual</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="../index.html">Prev</a> </td><th width="60%" align="center"> </th><td width="20%" align="right"> <a accesskey="n" href="intro.html">Next</a></td></tr></table><hr /></div><div class="book"><div class="titlepage"><div><div><h1 class="title"><a id="manual"></a>The GNU C++ Library Manual</h1></div><div><div class="authorgroup"><div class="author"><h3 class="author"><span class="firstname"></span> <span class="surname"></span></h3></div><div class="author"><h3 class="author"><span class="firstname">Paolo</span> <span class="surname">Carlini</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Phil</span> <span class="surname">Edwards</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Doug</span> <span class="surname">Gregor</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Benjamin</span> <span class="surname">Kosnik</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Dhruv</span> <span class="surname">Matani</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Jason</span> <span class="surname">Merrill</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Mark</span> <span class="surname">Mitchell</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Nathan</span> <span class="surname">Myers</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Felix</span> <span class="surname">Natter</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Stefan</span> <span class="surname">Olsson</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Silvius</span> <span class="surname">Rus</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Johannes</span> <span class="surname">Singler</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Ami</span> <span class="surname">Tavory</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Jonathan</span> <span class="surname">Wakely</span></h3></div></div></div><div><p class="copyright">Copyright © 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013

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- </p></div></div><hr /></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="part"><a href="intro.html">I.

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+ </p></div></div><hr /></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="part"><a href="intro.html">I.

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Introduction

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</a></span></dt><dd><dl><dt><span class="chapter"><a href="status.html">1. Status</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#manual.intro.status.iso">Implementation Status</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#status.iso.1998">C++ 1998/2003</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.1998.status">Implementation Status</a></span></dt><dt><span class="section"><a href="status.html#iso.1998.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.2011">C++ 2011</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.2011.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.tr1">C++ TR1</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.tr1.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.tr24733">C++ TR 24733</a></span></dt></dl></dd><dt><span class="section"><a href="license.html">License</a></span></dt><dd><dl><dt><span class="section"><a href="license.html#manual.intro.status.license.gpl">The Code: GPL</a></span></dt><dt><span class="section"><a href="license.html#manual.intro.status.license.fdl">The Documentation: GPL, FDL</a></span></dt></dl></dd><dt><span class="section"><a href="bugs.html">Bugs</a></span></dt><dd><dl><dt><span class="section"><a href="bugs.html#manual.intro.status.bugs.impl">Implementation Bugs</a></span></dt><dt><span class="section"><a href="bugs.html#manual.intro.status.bugs.iso">Standard Bugs</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="setup.html">2. Setup</a></span></dt><dd><dl><dt><span class="section"><a href="setup.html#manual.intro.setup.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="configure.html">Configure</a></span></dt><dt><span class="section"><a href="make.html">Make</a></span></dt></dl></dd><dt><span class="chapter"><a href="using.html">3. Using</a></span></dt><dd><dl><dt><span class="section"><a href="using.html#manual.intro.using.flags">Command Options</a></span></dt><dt><span class="section"><a href="using_headers.html">Headers</a></span></dt><dd><dl><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.all">Header Files</a></span></dt><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.mixing">Mixing Headers</a></span></dt><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.cheaders">The C Headers and <code class="code">namespace std</code></a></span></dt><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.pre">Precompiled Headers</a></span></dt></dl></dd><dt><span class="section"><a href="using_macros.html">Macros</a></span></dt><dt><span class="section"><a href="using_namespaces.html">Namespaces</a></span></dt><dd><dl><dt><span class="section"><a href="using_namespaces.html#manual.intro.using.namespaces.all">Available Namespaces</a></span></dt><dt><span class="section"><a href="using_namespaces.html#manual.intro.using.namespaces.std">namespace std</a></span></dt><dt><span class="section"><a href="using_namespaces.html#manual.intro.using.namespaces.comp">Using Namespace Composition</a></span></dt></dl></dd><dt><span class="section"><a href="using_dynamic_or_shared.html">Linking</a></span></dt><dd><dl><dt><span class="section"><a href="using_dynamic_or_shared.html#manual.intro.using.linkage.freestanding">Almost Nothing</a></span></dt><dt><span class="section"><a href="using_dynamic_or_shared.html#manual.intro.using.linkage.dynamic">Finding Dynamic or Shared Libraries</a></span></dt></dl></dd><dt><span class="section"><a href="using_concurrency.html">Concurrency</a></span></dt><dd><dl><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.thread_safety">Thread Safety</a></span></dt><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.atomics">Atomics</a></span></dt><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.io">IO</a></span></dt><dd><dl><dt><span class="section"><a href="using_concurrency.html#concurrency.io.structure">Structure</a></span></dt><dt><span class="section"><a href="using_concurrency.html#concurrency.io.defaults">Defaults</a></span></dt><dt><span class="section"><a href="using_concurrency.html#concurrency.io.future">Future</a></span></dt><dt><span class="section"><a href="using_concurrency.html#concurrency.io.alt">Alternatives</a></span></dt></dl></dd><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.containers">Containers</a></span></dt></dl></dd><dt><span class="section"><a href="using_exceptions.html">Exceptions</a></span></dt><dd><dl><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.safety">Exception Safety</a></span></dt><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.propagating">Exception Neutrality</a></span></dt><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.no">Doing without</a></span></dt><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.compat">Compatibility</a></span></dt><dd><dl><dt><span class="section"><a href="using_exceptions.html#using.exception.compat.c">With <code class="literal">C</code></a></span></dt><dt><span class="section"><a href="using_exceptions.html#using.exception.compat.posix">With <code class="literal">POSIX</code> thread cancellation</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="debug.html">Debugging Support</a></span></dt><dd><dl><dt><span class="section"><a href="debug.html#debug.compiler">Using <span class="command"><strong>g++</strong></span></a></span></dt><dt><span class="section"><a href="debug.html#debug.req">Debug Versions of Library Binary Files</a></span></dt><dt><span class="section"><a href="debug.html#debug.memory">Memory Leak Hunting</a></span></dt><dt><span class="section"><a href="debug.html#debug.races">Data Race Hunting</a></span></dt><dt><span class="section"><a href="debug.html#debug.gdb">Using <span class="command"><strong>gdb</strong></span></a></span></dt><dt><span class="section"><a href="debug.html#debug.exceptions">Tracking uncaught exceptions</a></span></dt><dt><span class="section"><a href="debug.html#debug.debug_mode">Debug Mode</a></span></dt><dt><span class="section"><a href="debug.html#debug.compile_time_checks">Compile Time Checking</a></span></dt><dt><span class="section"><a href="debug.html#debug.profile_mode">Profile-based Performance Analysis</a></span></dt></dl></dd></dl></dd></dl></dd><dt><span class="part"><a href="std_contents.html">II.

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</a></span></dt><dd><dl><dt><span class="section"><a href="diagnostics.html#std.diagnostics.exceptions">Exceptions</a></span></dt><dd><dl><dt><span class="section"><a href="diagnostics.html#std.diagnostics.exceptions.api">API Reference</a></span></dt><dt><span class="section"><a href="diagnostics.html#std.diagnostics.exceptions.data">Adding Data to <code class="classname">exception</code></a></span></dt></dl></dd><dt><span class="section"><a href="concept_checking.html">Concept Checking</a></span></dt></dl></dd><dt><span class="chapter"><a href="utilities.html">6.

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Utilities

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-</a></span></dt><dd><dl><dt><span class="section"><a href="utilities.html#std.util.functors">Functors</a></span></dt><dt><span class="section"><a href="pairs.html">Pairs</a></span></dt><dt><span class="section"><a href="memory.html">Memory</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#std.util.memory.allocator">Allocators</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#allocator.req">Requirements</a></span></dt><dt><span class="section"><a href="memory.html#allocator.design_issues">Design Issues</a></span></dt><dt><span class="section"><a href="memory.html#allocator.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idp13920976">Interface Design</a></span></dt><dt><span class="section"><a href="memory.html#idp13924528">Selecting Default Allocation Policy</a></span></dt><dt><span class="section"><a href="memory.html#idp13937824">Disabling Memory Caching</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#allocator.using">Using a Specific Allocator</a></span></dt><dt><span class="section"><a href="memory.html#allocator.custom">Custom Allocators</a></span></dt><dt><span class="section"><a href="memory.html#allocator.ext">Extension Allocators</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#std.util.memory.auto_ptr">auto_ptr</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#auto_ptr.limitations">Limitations</a></span></dt><dt><span class="section"><a href="memory.html#auto_ptr.using">Use in Containers</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#std.util.memory.shared_ptr">shared_ptr</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#shared_ptr.req">Requirements</a></span></dt><dt><span class="section"><a href="memory.html#shared_ptr.design_issues">Design Issues</a></span></dt><dt><span class="section"><a href="memory.html#shared_ptr.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idp15512272">Class Hierarchy</a></span></dt><dt><span class="section"><a href="memory.html#idp15534784">Thread Safety</a></span></dt><dt><span class="section"><a href="memory.html#idp15542080">Selecting Lock Policy</a></span></dt><dt><span class="section"><a href="memory.html#idp15556704">Related functions and classes</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#shared_ptr.using">Use</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idp15573056">Examples</a></span></dt><dt><span class="section"><a href="memory.html#idp15576640">Unresolved Issues</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#shared_ptr.ack">Acknowledgments</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="traits.html">Traits</a></span></dt></dl></dd><dt><span class="chapter"><a href="strings.html">7.

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+</a></span></dt><dd><dl><dt><span class="section"><a href="utilities.html#std.util.functors">Functors</a></span></dt><dt><span class="section"><a href="pairs.html">Pairs</a></span></dt><dt><span class="section"><a href="memory.html">Memory</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#std.util.memory.allocator">Allocators</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#allocator.req">Requirements</a></span></dt><dt><span class="section"><a href="memory.html#allocator.design_issues">Design Issues</a></span></dt><dt><span class="section"><a href="memory.html#allocator.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idm270001611968">Interface Design</a></span></dt><dt><span class="section"><a href="memory.html#idm270001608416">Selecting Default Allocation Policy</a></span></dt><dt><span class="section"><a href="memory.html#idm270001595120">Disabling Memory Caching</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#allocator.using">Using a Specific Allocator</a></span></dt><dt><span class="section"><a href="memory.html#allocator.custom">Custom Allocators</a></span></dt><dt><span class="section"><a href="memory.html#allocator.ext">Extension Allocators</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#std.util.memory.auto_ptr">auto_ptr</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#auto_ptr.limitations">Limitations</a></span></dt><dt><span class="section"><a href="memory.html#auto_ptr.using">Use in Containers</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#std.util.memory.shared_ptr">shared_ptr</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#shared_ptr.req">Requirements</a></span></dt><dt><span class="section"><a href="memory.html#shared_ptr.design_issues">Design Issues</a></span></dt><dt><span class="section"><a href="memory.html#shared_ptr.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idm270000019344">Class Hierarchy</a></span></dt><dt><span class="section"><a href="memory.html#idm269999996832">Thread Safety</a></span></dt><dt><span class="section"><a href="memory.html#idm269999989536">Selecting Lock Policy</a></span></dt><dt><span class="section"><a href="memory.html#idm269999974912">Related functions and classes</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#shared_ptr.using">Use</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idm269999958496">Examples</a></span></dt><dt><span class="section"><a href="memory.html#idm269999954912">Unresolved Issues</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#shared_ptr.ack">Acknowledgments</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="traits.html">Traits</a></span></dt></dl></dd><dt><span class="chapter"><a href="strings.html">7.

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Strings

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</a></span></dt><dd><dl><dt><span class="section"><a href="strings.html#std.strings.string">String Classes</a></span></dt><dd><dl><dt><span class="section"><a href="strings.html#strings.string.simple">Simple Transformations</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.case">Case Sensitivity</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.character_types">Arbitrary Character Types</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.token">Tokenizing</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.shrink">Shrink to Fit</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.Cstring">CString (MFC)</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="localization.html">8.

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-</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#std.localization.locales">Locales</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#std.localization.locales.locale">locale</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#locales.locale.req">Requirements</a></span></dt><dt><span class="section"><a href="localization.html#locales.locale.design">Design</a></span></dt><dt><span class="section"><a href="localization.html#locales.locale.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#locale.impl.c">Interacting with "C" locales</a></span></dt></dl></dd><dt><span class="section"><a href="localization.html#locales.locale.future">Future</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="facets.html">Facets</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#std.localization.facet.ctype">ctype</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.ctype.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#idp15778336">Specializations</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.ctype.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#std.localization.facet.codecvt">codecvt</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.codecvt.req">Requirements</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.design">Design</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#codecvt.design.wchar_t_size"><span class="type">wchar_t</span> Size</a></span></dt><dt><span class="section"><a href="facets.html#codecvt.design.unicode">Support for Unicode</a></span></dt><dt><span class="section"><a href="facets.html#codecvt.design.issues">Other Issues</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.codecvt.impl">Implementation</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.use">Use</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#manual.localization.facet.messages">messages</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.messages.req">Requirements</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.design">Design</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#messages.impl.models">Models</a></span></dt><dt><span class="section"><a href="facets.html#messages.impl.gnu">The GNU Model</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.messages.use">Use</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.future">Future</a></span></dt></dl></dd></dl></dd></dl></dd><dt><span class="chapter"><a href="containers.html">9.

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+</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#std.localization.locales">Locales</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#std.localization.locales.locale">locale</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#locales.locale.req">Requirements</a></span></dt><dt><span class="section"><a href="localization.html#locales.locale.design">Design</a></span></dt><dt><span class="section"><a href="localization.html#locales.locale.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#locale.impl.c">Interacting with "C" locales</a></span></dt></dl></dd><dt><span class="section"><a href="localization.html#locales.locale.future">Future</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="facets.html">Facets</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#std.localization.facet.ctype">ctype</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.ctype.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#idm269999753024">Specializations</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.ctype.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#std.localization.facet.codecvt">codecvt</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.codecvt.req">Requirements</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.design">Design</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#codecvt.design.wchar_t_size"><span class="type">wchar_t</span> Size</a></span></dt><dt><span class="section"><a href="facets.html#codecvt.design.unicode">Support for Unicode</a></span></dt><dt><span class="section"><a href="facets.html#codecvt.design.issues">Other Issues</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.codecvt.impl">Implementation</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.use">Use</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#manual.localization.facet.messages">messages</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.messages.req">Requirements</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.design">Design</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#messages.impl.models">Models</a></span></dt><dt><span class="section"><a href="facets.html#messages.impl.gnu">The GNU Model</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.messages.use">Use</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.future">Future</a></span></dt></dl></dd></dl></dd></dl></dd><dt><span class="chapter"><a href="containers.html">9.

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</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#std.containers.sequences">Sequences</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#containers.sequences.list">list</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#sequences.list.size">list::size() is O(n)</a></span></dt></dl></dd><dt><span class="section"><a href="containers.html#containers.sequences.vector">vector</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#sequences.vector.management">Space Overhead Management</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="associative.html">Associative</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#containers.associative.insert_hints">Insertion Hints</a></span></dt><dt><span class="section"><a href="associative.html#containers.associative.bitset">bitset</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#associative.bitset.size_variable">Size Variable</a></span></dt><dt><span class="section"><a href="associative.html#associative.bitset.type_string">Type String</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="unordered_associative.html">Unordered Associative</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.hash">Hash Code</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.cache">Hash Code Caching Policy</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="containers_and_c.html">Interacting with C</a></span></dt><dd><dl><dt><span class="section"><a href="containers_and_c.html#containers.c.vs_array">Containers vs. Arrays</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="iterators.html">10.

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</a></span></dt><dt><span class="appendix"><a href="appendix_gpl.html">D.

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<acronym class="acronym">GNU</acronym> General Public License version 3

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- </a></span></dt><dt><span class="appendix"><a href="appendix_gfdl.html">E. GNU Free Documentation License</a></span></dt></dl></dd></dl></div><div class="list-of-figures"><p><strong>List of Figures</strong></p><dl><dt>22.1. <a href="policy_data_structures.html#idp17613296">Node Invariants</a></dt><dt>22.2. <a href="policy_data_structures.html#idp17619952">Underlying Associative Data Structures</a></dt><dt>22.3. <a href="policy_data_structures.html#idp17651648">Range Iteration in Different Data Structures</a></dt><dt>22.4. <a href="policy_data_structures.html#idp17666528">Point Iteration in Hash Data Structures</a></dt><dt>22.5. <a href="policy_data_structures.html#idp17675840">Effect of erase in different underlying data structures</a></dt><dt>22.6. <a href="policy_data_structures.html#idp17743424">Underlying Priority Queue Data Structures</a></dt><dt>22.7. <a href="policy_data_structures_using.html#idp17806128">Exception Hierarchy</a></dt><dt>22.8. <a href="policy_data_structures_design.html#idp18000448">Non-unique Mapping Standard Containers</a></dt><dt>22.9. <a href="policy_data_structures_design.html#fig.pbds_embedded_lists_2">

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+ </a></span></dt><dt><span class="appendix"><a href="appendix_gfdl.html">E. GNU Free Documentation License</a></span></dt></dl></dd></dl></div><div class="list-of-figures"><p><strong>List of Figures</strong></p><dl><dt>22.1. <a href="policy_data_structures.html#idm269997917584">Node Invariants</a></dt><dt>22.2. <a href="policy_data_structures.html#idm269997910864">Underlying Associative Data Structures</a></dt><dt>22.3. <a href="policy_data_structures.html#idm269997879168">Range Iteration in Different Data Structures</a></dt><dt>22.4. <a href="policy_data_structures.html#idm269997864256">Point Iteration in Hash Data Structures</a></dt><dt>22.5. <a href="policy_data_structures.html#idm269997855056">Effect of erase in different underlying data structures</a></dt><dt>22.6. <a href="policy_data_structures.html#idm269997787392">Underlying Priority Queue Data Structures</a></dt><dt>22.7. <a href="policy_data_structures_using.html#idm269997724688">Exception Hierarchy</a></dt><dt>22.8. <a href="policy_data_structures_design.html#idm269997530416">Non-unique Mapping Standard Containers</a></dt><dt>22.9. <a href="policy_data_structures_design.html#fig.pbds_embedded_lists_2">

3623

Effect of embedded lists in

3624

<code class="classname">std::multimap</code>

3625

- </a></dt><dt>22.10. <a href="policy_data_structures_design.html#idp18023952">Non-unique Mapping Containers</a></dt><dt>22.11. <a href="policy_data_structures_design.html#idp18043824">Point Iterator Hierarchy</a></dt><dt>22.12. <a href="policy_data_structures_design.html#idp18057168">Invalidation Guarantee Tags Hierarchy</a></dt><dt>22.13. <a href="policy_data_structures_design.html#idp18087392">Container Tag Hierarchy</a></dt><dt>22.14. <a href="policy_data_structures_design.html#idp18127536">Hash functions, ranged-hash functions, and

3626

- range-hashing functions</a></dt><dt>22.15. <a href="policy_data_structures_design.html#idp18191968">Insert hash sequence diagram</a></dt><dt>22.16. <a href="policy_data_structures_design.html#idp18199024">Insert hash sequence diagram with a null policy</a></dt><dt>22.17. <a href="policy_data_structures_design.html#idp18215840">Hash policy class diagram</a></dt><dt>22.18. <a href="policy_data_structures_design.html#idp18234944">Balls and bins</a></dt><dt>22.19. <a href="policy_data_structures_design.html#idp18265728">Insert resize sequence diagram</a></dt><dt>22.20. <a href="policy_data_structures_design.html#idp18273504">Standard resize policy trigger sequence

3627

- diagram</a></dt><dt>22.21. <a href="policy_data_structures_design.html#idp18277664">Standard resize policy size sequence

3628

- diagram</a></dt><dt>22.22. <a href="policy_data_structures_design.html#idp18355696">Tree node invariants</a></dt><dt>22.23. <a href="policy_data_structures_design.html#idp18365136">Tree node invalidation</a></dt><dt>22.24. <a href="policy_data_structures_design.html#idp18378304">A tree and its update policy</a></dt><dt>22.25. <a href="policy_data_structures_design.html#idp18389968">Restoring node invariants</a></dt><dt>22.26. <a href="policy_data_structures_design.html#idp18398144">Insert update sequence</a></dt><dt>22.27. <a href="policy_data_structures_design.html#idp18420400">Useless update path</a></dt><dt>22.28. <a href="policy_data_structures_design.html#idp18465088">A PATRICIA trie</a></dt><dt>22.29. <a href="policy_data_structures_design.html#idp18475584">A trie and its update policy</a></dt><dt>22.30. <a href="policy_data_structures_design.html#idp18506160">A simple list</a></dt><dt>22.31. <a href="policy_data_structures_design.html#idp18511744">The counter algorithm</a></dt><dt>22.32. <a href="policy_data_structures_design.html#idp18575568">Underlying Priority-Queue Data-Structures.</a></dt><dt>22.33. <a href="policy_data_structures_design.html#idp18610544">Priority-Queue Data-Structure Tags.</a></dt><dt>B.1. <a href="appendix_porting.html#idp22035648">Configure and Build File Dependencies</a></dt></dl></div><div class="list-of-tables"><p><strong>List of Tables</strong></p><dl><dt>1.1. <a href="status.html#idp452240">C++ 1998/2003 Implementation Status</a></dt><dt>1.2. <a href="status.html#idp8670848">C++ 2011 Implementation Status</a></dt><dt>1.3. <a href="status.html#idp7483200">C++ TR1 Implementation Status</a></dt><dt>1.4. <a href="status.html#idp12559072">C++ TR 24733 Implementation Status</a></dt><dt>3.1. <a href="using.html#idp13051936">C++ Command Options</a></dt><dt>3.2. <a href="using_headers.html#idp13079360">C++ 1998 Library Headers</a></dt><dt>3.3. <a href="using_headers.html#idp13115840">C++ 1998 Library Headers for C Library Facilities</a></dt><dt>3.4. <a href="using_headers.html#idp13140576">C++ 2011 Library Headers</a></dt><dt>3.5. <a href="using_headers.html#idp13192016">C++ 2011 Library Headers for C Library Facilities</a></dt><dt>3.6. <a href="using_headers.html#idp13221904">C++ TR 1 Library Headers</a></dt><dt>3.7. <a href="using_headers.html#idp13238832">C++ TR 1 Library Headers for C Library Facilities</a></dt><dt>3.8. <a href="using_headers.html#idp13259904">C++ TR 24733 Decimal Floating-Point Header</a></dt><dt>3.9. <a href="using_headers.html#idp13265424">C++ ABI Headers</a></dt><dt>3.10. <a href="using_headers.html#idp13271824">Extension Headers</a></dt><dt>3.11. <a href="using_headers.html#idp13307552">Extension Debug Headers</a></dt><dt>3.12. <a href="using_headers.html#idp13322320">Extension Profile Headers</a></dt><dt>3.13. <a href="using_headers.html#idp13335696">Extension Parallel Headers</a></dt><dt>17.1. <a href="debug_mode_using.html#idp16490400">Debugging Containers</a></dt><dt>17.2. <a href="debug_mode_using.html#idp16535296">Debugging Containers C++11</a></dt><dt>18.1. <a href="parallel_mode_using.html#idp16725920">Parallel Algorithms</a></dt><dt>19.1. <a href="profile_mode_design.html#idp16981200">Profile Code Location</a></dt><dt>19.2. <a href="profile_mode_diagnostics.html#idp17088912">Profile Diagnostics</a></dt><dt>21.1. <a href="bitmap_allocator_impl.html#idp17500848">Bitmap Allocator Memory Map</a></dt><dt>B.1. <a href="documentation_hacking.html#idp22162432">Doxygen Prerequisites</a></dt><dt>B.2. <a href="documentation_hacking.html#idp22238096">HTML to Doxygen Markup Comparison</a></dt><dt>B.3. <a href="documentation_hacking.html#idp22257536">Docbook Prerequisites</a></dt><dt>B.4. <a href="documentation_hacking.html#idp22335040">HTML to Docbook XML Markup Comparison</a></dt><dt>B.5. <a href="documentation_hacking.html#idp22359184">Docbook XML Element Use</a></dt><dt>B.6. <a href="api.html#idp23030528">Extension Allocators</a></dt><dt>B.7. <a href="api.html#idp23058160">Extension Allocators Continued</a></dt></dl></div><div class="list-of-equations"><p><strong>List of Equations</strong></p><dl><dt>22.1. <a href="policy_data_structures_design.html#idp18141344">Ranged Hash Function</a></dt><dt>22.2. <a href="policy_data_structures_design.html#idp18147232">Range-Hashing, Division Method</a></dt><dt>22.3. <a href="policy_data_structures_design.html#idp18151744">Division via Prime Modulo</a></dt><dt>22.4. <a href="policy_data_structures_design.html#idp18153568">Division via Bit Mask</a></dt><dt>22.5. <a href="policy_data_structures_design.html#idp18163200">

3629

+ </a></dt><dt>22.10. <a href="policy_data_structures_design.html#idm269997506912">Non-unique Mapping Containers</a></dt><dt>22.11. <a href="policy_data_structures_design.html#idm269997487104">Point Iterator Hierarchy</a></dt><dt>22.12. <a href="policy_data_structures_design.html#idm269997473760">Invalidation Guarantee Tags Hierarchy</a></dt><dt>22.13. <a href="policy_data_structures_design.html#idm269997443664">Container Tag Hierarchy</a></dt><dt>22.14. <a href="policy_data_structures_design.html#idm269997403584">Hash functions, ranged-hash functions, and

3630

+ range-hashing functions</a></dt><dt>22.15. <a href="policy_data_structures_design.html#idm269997339216">Insert hash sequence diagram</a></dt><dt>22.16. <a href="policy_data_structures_design.html#idm269997332160">Insert hash sequence diagram with a null policy</a></dt><dt>22.17. <a href="policy_data_structures_design.html#idm269997315408">Hash policy class diagram</a></dt><dt>22.18. <a href="policy_data_structures_design.html#idm269997296368">Balls and bins</a></dt><dt>22.19. <a href="policy_data_structures_design.html#idm269997265648">Insert resize sequence diagram</a></dt><dt>22.20. <a href="policy_data_structures_design.html#idm269997257872">Standard resize policy trigger sequence

3631

+ diagram</a></dt><dt>22.21. <a href="policy_data_structures_design.html#idm269997253712">Standard resize policy size sequence

3632

+ diagram</a></dt><dt>22.22. <a href="policy_data_structures_design.html#idm269997175616">Tree node invariants</a></dt><dt>22.23. <a href="policy_data_structures_design.html#idm269997166176">Tree node invalidation</a></dt><dt>22.24. <a href="policy_data_structures_design.html#idm269997153072">A tree and its update policy</a></dt><dt>22.25. <a href="policy_data_structures_design.html#idm269997141408">Restoring node invariants</a></dt><dt>22.26. <a href="policy_data_structures_design.html#idm269997133232">Insert update sequence</a></dt><dt>22.27. <a href="policy_data_structures_design.html#idm269997110976">Useless update path</a></dt><dt>22.28. <a href="policy_data_structures_design.html#idm269997066288">A PATRICIA trie</a></dt><dt>22.29. <a href="policy_data_structures_design.html#idm269997055856">A trie and its update policy</a></dt><dt>22.30. <a href="policy_data_structures_design.html#idm269997025344">A simple list</a></dt><dt>22.31. <a href="policy_data_structures_design.html#idm269997019760">The counter algorithm</a></dt><dt>22.32. <a href="policy_data_structures_design.html#idm269996955920">Underlying Priority-Queue Data-Structures.</a></dt><dt>22.33. <a href="policy_data_structures_design.html#idm269996920880">Priority-Queue Data-Structure Tags.</a></dt><dt>B.1. <a href="appendix_porting.html#idm269993497120">Configure and Build File Dependencies</a></dt></dl></div><div class="list-of-tables"><p><strong>List of Tables</strong></p><dl><dt>1.1. <a href="status.html#idm270008034928">C++ 1998/2003 Implementation Status</a></dt><dt>1.2. <a href="status.html#idm270007982624">C++ 2011 Implementation Status</a></dt><dt>1.3. <a href="status.html#idm270006687472">C++ TR1 Implementation Status</a></dt><dt>1.4. <a href="status.html#idm270002960368">C++ TR 24733 Implementation Status</a></dt><dt>3.1. <a href="using.html#idm270002481088">C++ Command Options</a></dt><dt>3.2. <a href="using_headers.html#idm270002453792">C++ 1998 Library Headers</a></dt><dt>3.3. <a href="using_headers.html#idm270002417312">C++ 1998 Library Headers for C Library Facilities</a></dt><dt>3.4. <a href="using_headers.html#idm270002392576">C++ 2011 Library Headers</a></dt><dt>3.5. <a href="using_headers.html#idm270002341136">C++ 2011 Library Headers for C Library Facilities</a></dt><dt>3.6. <a href="using_headers.html#idm270002311248">C++ TR 1 Library Headers</a></dt><dt>3.7. <a href="using_headers.html#idm270002294320">C++ TR 1 Library Headers for C Library Facilities</a></dt><dt>3.8. <a href="using_headers.html#idm270002273248">C++ TR 24733 Decimal Floating-Point Header</a></dt><dt>3.9. <a href="using_headers.html#idm270002267728">C++ ABI Headers</a></dt><dt>3.10. <a href="using_headers.html#idm270002261328">Extension Headers</a></dt><dt>3.11. <a href="using_headers.html#idm270002225600">Extension Debug Headers</a></dt><dt>3.12. <a href="using_headers.html#idm270002210832">Extension Profile Headers</a></dt><dt>3.13. <a href="using_headers.html#idm270002197456">Extension Parallel Headers</a></dt><dt>17.1. <a href="debug_mode_using.html#idm269999040896">Debugging Containers</a></dt><dt>17.2. <a href="debug_mode_using.html#idm269998996000">Debugging Containers C++11</a></dt><dt>18.1. <a href="parallel_mode_using.html#idm269998805216">Parallel Algorithms</a></dt><dt>19.1. <a href="profile_mode_design.html#idm269998550064">Profile Code Location</a></dt><dt>19.2. <a href="profile_mode_diagnostics.html#idm269998442544">Profile Diagnostics</a></dt><dt>21.1. <a href="bitmap_allocator_impl.html#idm269998030352">Bitmap Allocator Memory Map</a></dt><dt>B.1. <a href="documentation_hacking.html#idm269993370272">Doxygen Prerequisites</a></dt><dt>B.2. <a href="documentation_hacking.html#idm269993294592">HTML to Doxygen Markup Comparison</a></dt><dt>B.3. <a href="documentation_hacking.html#idm269993275152">Docbook Prerequisites</a></dt><dt>B.4. <a href="documentation_hacking.html#idm269993197520">HTML to Docbook XML Markup Comparison</a></dt><dt>B.5. <a href="documentation_hacking.html#idm269993173376">Docbook XML Element Use</a></dt><dt>B.6. <a href="api.html#idm269992502096">Extension Allocators</a></dt><dt>B.7. <a href="api.html#idm269992474464">Extension Allocators Continued</a></dt></dl></div><div class="list-of-equations"><p><strong>List of Equations</strong></p><dl><dt>22.1. <a href="policy_data_structures_design.html#idm269997389776">Ranged Hash Function</a></dt><dt>22.2. <a href="policy_data_structures_design.html#idm269997383888">Range-Hashing, Division Method</a></dt><dt>22.3. <a href="policy_data_structures_design.html#idm269997379376">Division via Prime Modulo</a></dt><dt>22.4. <a href="policy_data_structures_design.html#idm269997377552">Division via Bit Mask</a></dt><dt>22.5. <a href="policy_data_structures_design.html#idm269997367984">

3633

A Standard String Hash Function

3634

- </a></dt><dt>22.6. <a href="policy_data_structures_design.html#idp18169344">

3635

+ </a></dt><dt>22.6. <a href="policy_data_structures_design.html#idm269997361840">

3636

Only k String DNA Hash

3637

- </a></dt><dt>22.7. <a href="policy_data_structures_design.html#idp18240448">

3638

+ </a></dt><dt>22.7. <a href="policy_data_structures_design.html#idm269997290864">

3639

Probability of Probe Sequence of Length k

3640

- </a></dt><dt>22.8. <a href="policy_data_structures_design.html#idp18247216">

3641

+ </a></dt><dt>22.8. <a href="policy_data_structures_design.html#idm269997284096">

3642

Probability Probe Sequence in Some Bin

3643

</a></dt></dl></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="../index.html">Prev</a> </td><td width="20%" align="center"> </td><td width="40%" align="right"> <a accesskey="n" href="intro.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">The GNU C++ Library </td><td width="20%" align="center"><a accesskey="h" href="../index.html">Home</a></td><td width="40%" align="right" valign="top"> Part I.

3644

Introduction

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>

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-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Interacting with C</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="numerics.html" title="Chapter 12. Numerics" /><link rel="prev" href="generalized_numeric_operations.html" title="Generalized Operations" /><link rel="next" href="io.html" title="Chapter 13. Input and Output" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Interacting with C</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="generalized_numeric_operations.html">Prev</a> </td><th width="60%" align="center">Chapter 12.

3652

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Interacting with C</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="numerics.html" title="Chapter 12. Numerics" /><link rel="prev" href="generalized_numeric_operations.html" title="Generalized Operations" /><link rel="next" href="io.html" title="Chapter 13. Input and Output" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Interacting with C</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="generalized_numeric_operations.html">Prev</a> </td><th width="60%" align="center">Chapter 12.

3653

Numerics

3654

3655

</th><td width="20%" align="right"> <a accesskey="n" href="io.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.numerics.c"></a>Interacting with C</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="numerics.c.array"></a>Numerics vs. Arrays</h3></div></div></div><p>One of the major reasons why FORTRAN can chew through numbers so well

3656

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3657

===================================================================

3658

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3661

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

3662

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Appendix D. GNU General Public License version 3</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix.html" title="Part IV. Appendices" /><link rel="prev" href="appendix_free.html" title="Appendix C. Free Software Needs Free Documentation" /><link rel="next" href="appendix_gfdl.html" title="Appendix E. GNU Free Documentation License" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Appendix D.

3663

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Appendix D. GNU General Public License version 3</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix.html" title="Part IV. Appendices" /><link rel="prev" href="appendix_free.html" title="Appendix C. Free Software Needs Free Documentation" /><link rel="next" href="appendix_gfdl.html" title="Appendix E. GNU Free Documentation License" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Appendix D.

3664

<acronym class="acronym">GNU</acronym> General Public License version 3

3665

</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="appendix_free.html">Prev</a> </td><th width="60%" align="center">Part IV.

3666

Appendices

3667

@@ -77,7 +77,7 @@

3668

</p><p>

3669

The precise terms and conditions for copying, distribution and modification

3670

follow.

3671

- </p><h2><a id="idp23466384"></a>

3672

+ </p><h2><a id="idm269992066368"></a>

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TERMS AND CONDITIONS

3674

</h2><h2><a id="gpl-3-definitions"></a>

3675

0. Definitions.

3676

@@ -618,7 +618,7 @@

3677

waiver of all civil liability in connection with the Program, unless a

3678

warranty or assumption of liability accompanies a copy of the Program in

3679

return for a fee.

3680

- </p><h2><a id="idp23565184"></a>

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+ </p><h2><a id="idm269991967568"></a>

3682

END OF TERMS AND CONDITIONS

3683

</h2><h2><a id="HowToApply"></a>

3684

How to Apply These Terms to Your New Programs

3685

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3686

===================================================================

3687

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>

3691

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Coding Style</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_contributing.html" title="Appendix A. Contributing" /><link rel="prev" href="source_organization.html" title="Directory Layout and Source Conventions" /><link rel="next" href="source_design_notes.html" title="Design Notes" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Coding Style</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="source_organization.html">Prev</a> </td><th width="60%" align="center">Appendix A.

3692

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Coding Style</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_contributing.html" title="Appendix A. Contributing" /><link rel="prev" href="source_organization.html" title="Directory Layout and Source Conventions" /><link rel="next" href="source_design_notes.html" title="Design Notes" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Coding Style</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="source_organization.html">Prev</a> </td><th width="60%" align="center">Appendix A.

3693

Contributing

3694

3695

</th><td width="20%" align="right"> <a accesskey="n" href="source_design_notes.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="contrib.coding_style"></a>Coding Style</h2></div></div></div><p>

3696

Index: libstdc++-v3/doc/html/manual/streambufs.html

3697

===================================================================

3698

--- a/src/libstdc++-v3/doc/html/manual/streambufs.html (.../tags/gcc_4_8_2_release)

3699

+++ b/src/libstdc++-v3/doc/html/manual/streambufs.html (.../branches/gcc-4_8-branch)

3700

@@ -1,5 +1,5 @@

3701

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

3702

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Stream Buffers</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="io.html" title="Chapter 13. Input and Output" /><link rel="prev" href="io.html" title="Chapter 13. Input and Output" /><link rel="next" href="stringstreams.html" title="Memory Based Streams" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Stream Buffers</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="io.html">Prev</a> </td><th width="60%" align="center">Chapter 13.

3703

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Stream Buffers</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="io.html" title="Chapter 13. Input and Output" /><link rel="prev" href="io.html" title="Chapter 13. Input and Output" /><link rel="next" href="stringstreams.html" title="Memory Based Streams" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Stream Buffers</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="io.html">Prev</a> </td><th width="60%" align="center">Chapter 13.

3704

Input and Output

3705

3706

</th><td width="20%" align="right"> <a accesskey="n" href="stringstreams.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.io.streambufs"></a>Stream Buffers</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="io.streambuf.derived"></a>Derived streambuf Classes</h3></div></div></div><p>

3707

Index: libstdc++-v3/doc/html/manual/utilities.html

3708

===================================================================

3709

--- a/src/libstdc++-v3/doc/html/manual/utilities.html (.../tags/gcc_4_8_2_release)

3710

+++ b/src/libstdc++-v3/doc/html/manual/utilities.html (.../branches/gcc-4_8-branch)

3711

@@ -1,5 +1,5 @@

3712

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

3713

-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 6. Utilities</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II. Standard Contents" /><link rel="prev" href="concept_checking.html" title="Concept Checking" /><link rel="next" href="pairs.html" title="Pairs" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 6.

3714

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 6. Utilities</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II. Standard Contents" /><link rel="prev" href="concept_checking.html" title="Concept Checking" /><link rel="next" href="pairs.html" title="Pairs" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 6.

3715

Utilities

3716

3717

</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="concept_checking.html">Prev</a> </td><th width="60%" align="center">Part II.

3718

@@ -6,8 +6,8 @@

3719

Standard Contents

3720

</th><td width="20%" align="right"> <a accesskey="n" href="pairs.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="std.util"></a>Chapter 6.

3721

Utilities

3722

- <a id="idp13862416" class="indexterm"></a>

3723

-</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="utilities.html#std.util.functors">Functors</a></span></dt><dt><span class="section"><a href="pairs.html">Pairs</a></span></dt><dt><span class="section"><a href="memory.html">Memory</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#std.util.memory.allocator">Allocators</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#allocator.req">Requirements</a></span></dt><dt><span class="section"><a href="memory.html#allocator.design_issues">Design Issues</a></span></dt><dt><span class="section"><a href="memory.html#allocator.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idp13920976">Interface Design</a></span></dt><dt><span class="section"><a href="memory.html#idp13924528">Selecting Default Allocation Policy</a></span></dt><dt><span class="section"><a href="memory.html#idp13937824">Disabling Memory Caching</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#allocator.using">Using a Specific Allocator</a></span></dt><dt><span class="section"><a href="memory.html#allocator.custom">Custom Allocators</a></span></dt><dt><span class="section"><a href="memory.html#allocator.ext">Extension Allocators</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#std.util.memory.auto_ptr">auto_ptr</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#auto_ptr.limitations">Limitations</a></span></dt><dt><span class="section"><a href="memory.html#auto_ptr.using">Use in Containers</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#std.util.memory.shared_ptr">shared_ptr</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#shared_ptr.req">Requirements</a></span></dt><dt><span class="section"><a href="memory.html#shared_ptr.design_issues">Design Issues</a></span></dt><dt><span class="section"><a href="memory.html#shared_ptr.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idp15512272">Class Hierarchy</a></span></dt><dt><span class="section"><a href="memory.html#idp15534784">Thread Safety</a></span></dt><dt><span class="section"><a href="memory.html#idp15542080">Selecting Lock Policy</a></span></dt><dt><span class="section"><a href="memory.html#idp15556704">Related functions and classes</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#shared_ptr.using">Use</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idp15573056">Examples</a></span></dt><dt><span class="section"><a href="memory.html#idp15576640">Unresolved Issues</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#shared_ptr.ack">Acknowledgments</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="traits.html">Traits</a></span></dt></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.util.functors"></a>Functors</h2></div></div></div><p>If you don't know what functors are, you're not alone. Many people

3724

+ <a id="idm270001670464" class="indexterm"></a>

3725

+</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="utilities.html#std.util.functors">Functors</a></span></dt><dt><span class="section"><a href="pairs.html">Pairs</a></span></dt><dt><span class="section"><a href="memory.html">Memory</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#std.util.memory.allocator">Allocators</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#allocator.req">Requirements</a></span></dt><dt><span class="section"><a href="memory.html#allocator.design_issues">Design Issues</a></span></dt><dt><span class="section"><a href="memory.html#allocator.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idm270001611968">Interface Design</a></span></dt><dt><span class="section"><a href="memory.html#idm270001608416">Selecting Default Allocation Policy</a></span></dt><dt><span class="section"><a href="memory.html#idm270001595120">Disabling Memory Caching</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#allocator.using">Using a Specific Allocator</a></span></dt><dt><span class="section"><a href="memory.html#allocator.custom">Custom Allocators</a></span></dt><dt><span class="section"><a href="memory.html#allocator.ext">Extension Allocators</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#std.util.memory.auto_ptr">auto_ptr</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#auto_ptr.limitations">Limitations</a></span></dt><dt><span class="section"><a href="memory.html#auto_ptr.using">Use in Containers</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#std.util.memory.shared_ptr">shared_ptr</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#shared_ptr.req">Requirements</a></span></dt><dt><span class="section"><a href="memory.html#shared_ptr.design_issues">Design Issues</a></span></dt><dt><span class="section"><a href="memory.html#shared_ptr.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idm270000019344">Class Hierarchy</a></span></dt><dt><span class="section"><a href="memory.html#idm269999996832">Thread Safety</a></span></dt><dt><span class="section"><a href="memory.html#idm269999989536">Selecting Lock Policy</a></span></dt><dt><span class="section"><a href="memory.html#idm269999974912">Related functions and classes</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#shared_ptr.using">Use</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idm269999958496">Examples</a></span></dt><dt><span class="section"><a href="memory.html#idm269999954912">Unresolved Issues</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#shared_ptr.ack">Acknowledgments</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="traits.html">Traits</a></span></dt></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.util.functors"></a>Functors</h2></div></div></div><p>If you don't know what functors are, you're not alone. Many people

3726

get slightly the wrong idea. In the interest of not reinventing

3727

the wheel, we will refer you to the introduction to the functor

3728

concept written by SGI as part of their STL, in

3729

Index: libstdc++-v3/include/debug/functions.h

3730

===================================================================

3731

--- a/src/libstdc++-v3/include/debug/functions.h (.../tags/gcc_4_8_2_release)

3732

+++ b/src/libstdc++-v3/include/debug/functions.h (.../branches/gcc-4_8-branch)

3733

@@ -345,11 +345,13 @@

3734

return __check_sorted_set_aux(__first, __last, __pred, _SameType());

3735

}

3736

3737

+ // _GLIBCXX_RESOLVE_LIB_DEFECTS

3738

+ // 270. Binary search requirements overly strict

3739

+ // Determine if a sequence is partitioned w.r.t. this element.

3740

template<typename _ForwardIterator, typename _Tp>

3741

inline bool

3742

- __check_partitioned_lower_aux(_ForwardIterator __first,

3743

- _ForwardIterator __last, const _Tp& __value,

3744

- std::forward_iterator_tag)

3745

+ __check_partitioned_lower(_ForwardIterator __first,

3746

+ _ForwardIterator __last, const _Tp& __value)

3747

{

3748

while (__first != __last && *__first < __value)

3749

++__first;

3750

@@ -362,38 +364,11 @@

3751

return __first == __last;

3752

}

3753

3754

- // For performance reason, as the iterator range has been validated, check on

3755

- // random access safe iterators is done using the base iterator.

3756

- template<typename _Iterator, typename _Sequence, typename _Tp>

3757

- inline bool

3758

- __check_partitioned_lower_aux(

3759

- const _Safe_iterator<_Iterator, _Sequence>& __first,

3760

- const _Safe_iterator<_Iterator, _Sequence>& __last,

3761

- const _Tp& __value,

3762

- std::random_access_iterator_tag __tag)

3763

- {

3764

- return __check_partitioned_lower_aux(__first.base(), __last.base(),

3765

- __value, __tag);

3766

- }

3767

-

3768

- // _GLIBCXX_RESOLVE_LIB_DEFECTS

3769

- // 270. Binary search requirements overly strict

3770

- // Determine if a sequence is partitioned w.r.t. this element.

3771

template<typename _ForwardIterator, typename _Tp>

3772

inline bool

3773

- __check_partitioned_lower(_ForwardIterator __first,

3774

+ __check_partitioned_upper(_ForwardIterator __first,

3775

_ForwardIterator __last, const _Tp& __value)

3776

{

3777

- return __check_partitioned_lower_aux(__first, __last, __value,

3778

- std::__iterator_category(__first));

3779

- }

3780

-

3781

- template<typename _ForwardIterator, typename _Tp>

3782

- inline bool

3783

- __check_partitioned_upper_aux(_ForwardIterator __first,

3784

- _ForwardIterator __last, const _Tp& __value,

3785

- std::forward_iterator_tag)

3786

- {

3787

while (__first != __last && !(__value < *__first))

3788

++__first;

3789

if (__first != __last)

3790

@@ -405,35 +380,12 @@

3791

return __first == __last;

3792

}

3793

3794

- // For performance reason, as the iterator range has been validated, check on

3795

- // random access safe iterators is done using the base iterator.

3796

- template<typename _Iterator, typename _Sequence, typename _Tp>

3797

- inline bool

3798

- __check_partitioned_upper_aux(

3799

- const _Safe_iterator<_Iterator, _Sequence>& __first,

3800

- const _Safe_iterator<_Iterator, _Sequence>& __last,

3801

- const _Tp& __value,

3802

- std::random_access_iterator_tag __tag)

3803

- {

3804

- return __check_partitioned_upper_aux(__first.base(), __last.base(),

3805

- __value, __tag);

3806

- }

3807

-

3808

- template<typename _ForwardIterator, typename _Tp>

3809

- inline bool

3810

- __check_partitioned_upper(_ForwardIterator __first,

3811

- _ForwardIterator __last, const _Tp& __value)

3812

- {

3813

- return __check_partitioned_upper_aux(__first, __last, __value,

3814

- std::__iterator_category(__first));

3815

- }

3816

-

3817

+ // Determine if a sequence is partitioned w.r.t. this element.

3818

template<typename _ForwardIterator, typename _Tp, typename _Pred>

3819

inline bool

3820

- __check_partitioned_lower_aux(_ForwardIterator __first,

3821

- _ForwardIterator __last, const _Tp& __value,

3822

- _Pred __pred,

3823

- std::forward_iterator_tag)

3824

+ __check_partitioned_lower(_ForwardIterator __first,

3825

+ _ForwardIterator __last, const _Tp& __value,

3826

+ _Pred __pred)

3827

{

3828

while (__first != __last && bool(__pred(*__first, __value)))

3829

++__first;

3830

@@ -446,39 +398,12 @@

3831

return __first == __last;

3832

}

3833

3834

- // For performance reason, as the iterator range has been validated, check on

3835

- // random access safe iterators is done using the base iterator.

3836

- template<typename _Iterator, typename _Sequence,

3837

- typename _Tp, typename _Pred>

3838

- inline bool

3839

- __check_partitioned_lower_aux(

3840

- const _Safe_iterator<_Iterator, _Sequence>& __first,

3841

- const _Safe_iterator<_Iterator, _Sequence>& __last,

3842

- const _Tp& __value, _Pred __pred,

3843

- std::random_access_iterator_tag __tag)

3844

- {

3845

- return __check_partitioned_lower_aux(__first.base(), __last.base(),

3846

- __value, __pred, __tag);

3847

- }

3848

-

3849

- // Determine if a sequence is partitioned w.r.t. this element.

3850

template<typename _ForwardIterator, typename _Tp, typename _Pred>

3851

inline bool

3852

- __check_partitioned_lower(_ForwardIterator __first,

3853

+ __check_partitioned_upper(_ForwardIterator __first,

3854

_ForwardIterator __last, const _Tp& __value,

3855

_Pred __pred)

3856

{

3857

- return __check_partitioned_lower_aux(__first, __last, __value, __pred,

3858

- std::__iterator_category(__first));

3859

- }

3860

-

3861

- template<typename _ForwardIterator, typename _Tp, typename _Pred>

3862

- inline bool

3863

- __check_partitioned_upper_aux(_ForwardIterator __first,

3864

- _ForwardIterator __last, const _Tp& __value,

3865

- _Pred __pred,

3866

- std::forward_iterator_tag)

3867

- {

3868

while (__first != __last && !bool(__pred(__value, *__first)))

3869

++__first;

3870

if (__first != __last)

3871

@@ -490,31 +415,6 @@

3872

return __first == __last;

3873

}

3874

3875

- // For performance reason, as the iterator range has been validated, check on

3876

- // random access safe iterators is done using the base iterator.

3877

- template<typename _Iterator, typename _Sequence,

3878

- typename _Tp, typename _Pred>

3879

- inline bool

3880

- __check_partitioned_upper_aux(

3881

- const _Safe_iterator<_Iterator, _Sequence>& __first,

3882

- const _Safe_iterator<_Iterator, _Sequence>& __last,

3883

- const _Tp& __value, _Pred __pred,

3884

- std::random_access_iterator_tag __tag)

3885

- {

3886

- return __check_partitioned_upper_aux(__first.base(), __last.base(),

3887

- __value, __pred, __tag);

3888

- }

3889

-

3890

- template<typename _ForwardIterator, typename _Tp, typename _Pred>

3891

- inline bool

3892

- __check_partitioned_upper(_ForwardIterator __first,

3893

- _ForwardIterator __last, const _Tp& __value,

3894

- _Pred __pred)

3895

- {

3896

- return __check_partitioned_upper_aux(__first, __last, __value, __pred,

3897

- std::__iterator_category(__first));

3898

- }

3899

-

3900

// Helper struct to detect random access safe iterators.

3901

template<typename _Iterator>

3902

struct __is_safe_random_iterator

3903

Index: libstdc++-v3/include/debug/safe_unordered_base.h

3904

===================================================================

3905

--- a/src/libstdc++-v3/include/debug/safe_unordered_base.h (.../tags/gcc_4_8_2_release)

3906

+++ b/src/libstdc++-v3/include/debug/safe_unordered_base.h (.../branches/gcc-4_8-branch)

3907

@@ -133,9 +133,19 @@

3908

protected:

3909

// Initialize with a version number of 1 and no iterators

3910

_Safe_unordered_container_base()

3911

- : _M_local_iterators(0), _M_const_local_iterators(0)

3912

+ : _M_local_iterators(nullptr), _M_const_local_iterators(nullptr)

3913

{ }

3914

3915

+ // Initialize with a version number of 1 and no iterators

3916

+ _Safe_unordered_container_base(const _Safe_unordered_container_base&)

3917

+ noexcept

3918

+ : _Safe_unordered_container_base() { }

3919

+

3920

+ _Safe_unordered_container_base(_Safe_unordered_container_base&& __x)

3921

+ noexcept

3922

+ : _Safe_unordered_container_base()

3923

+ { this->_M_swap(__x); }

3924

+

3925

/** Notify all iterators that reference this container that the

3926

container is being destroyed. */

3927

~_Safe_unordered_container_base()

3928

Index: libstdc++-v3/include/debug/macros.h

3929

===================================================================

3930

--- a/src/libstdc++-v3/include/debug/macros.h (.../tags/gcc_4_8_2_release)

3931

+++ b/src/libstdc++-v3/include/debug/macros.h (.../branches/gcc-4_8-branch)

3932

@@ -261,8 +261,9 @@

3933

w.r.t. the value _Value. */

3934

#define __glibcxx_check_partitioned_lower(_First,_Last,_Value) \

3935

__glibcxx_check_valid_range(_First,_Last); \

3936

-_GLIBCXX_DEBUG_VERIFY(__gnu_debug::__check_partitioned_lower(_First, _Last, \

3937

- _Value), \

3938

+_GLIBCXX_DEBUG_VERIFY(__gnu_debug::__check_partitioned_lower( \

3939

+ __gnu_debug::__base(_First), \

3940

+ __gnu_debug::__base(_Last), _Value), \

3941

_M_message(__gnu_debug::__msg_unpartitioned) \

3942

._M_iterator(_First, #_First) \

3943

._M_iterator(_Last, #_Last) \

3944

@@ -270,8 +271,9 @@

3945

3946

#define __glibcxx_check_partitioned_upper(_First,_Last,_Value) \

3947

__glibcxx_check_valid_range(_First,_Last); \

3948

-_GLIBCXX_DEBUG_VERIFY(__gnu_debug::__check_partitioned_upper(_First, _Last, \

3949

- _Value), \

3950

+_GLIBCXX_DEBUG_VERIFY(__gnu_debug::__check_partitioned_upper( \

3951

+ __gnu_debug::__base(_First), \

3952

+ __gnu_debug::__base(_Last), _Value), \

3953

_M_message(__gnu_debug::__msg_unpartitioned) \

3954

._M_iterator(_First, #_First) \

3955

._M_iterator(_Last, #_Last) \

3956

@@ -281,8 +283,9 @@

3957

w.r.t. the value _Value and predicate _Pred. */

3958

#define __glibcxx_check_partitioned_lower_pred(_First,_Last,_Value,_Pred) \

3959

__glibcxx_check_valid_range(_First,_Last); \

3960

-_GLIBCXX_DEBUG_VERIFY(__gnu_debug::__check_partitioned_lower(_First, _Last, \

3961

- _Value, _Pred), \

3962

+_GLIBCXX_DEBUG_VERIFY(__gnu_debug::__check_partitioned_lower( \

3963

+ __gnu_debug::__base(_First), \

3964

+ __gnu_debug::__base(_Last), _Value, _Pred), \

3965

_M_message(__gnu_debug::__msg_unpartitioned_pred) \

3966

._M_iterator(_First, #_First) \

3967

._M_iterator(_Last, #_Last) \

3968

@@ -293,8 +296,9 @@

3969

w.r.t. the value _Value and predicate _Pred. */

3970

#define __glibcxx_check_partitioned_upper_pred(_First,_Last,_Value,_Pred) \

3971

__glibcxx_check_valid_range(_First,_Last); \

3972

-_GLIBCXX_DEBUG_VERIFY(__gnu_debug::__check_partitioned_upper(_First, _Last, \

3973

- _Value, _Pred), \

3974

+_GLIBCXX_DEBUG_VERIFY(__gnu_debug::__check_partitioned_upper( \

3975

+ __gnu_debug::__base(_First), \

3976

+ __gnu_debug::__base(_Last), _Value, _Pred), \

3977

_M_message(__gnu_debug::__msg_unpartitioned_pred) \

3978

._M_iterator(_First, #_First) \

3979

._M_iterator(_Last, #_Last) \

3980

Index: libstdc++-v3/include/std/tuple

3981

===================================================================

3982

--- a/src/libstdc++-v3/include/std/tuple (.../tags/gcc_4_8_2_release)

3983

+++ b/src/libstdc++-v3/include/std/tuple (.../branches/gcc-4_8-branch)

3984

@@ -755,7 +755,7 @@

3985

typename tuple_element<__i, tuple<_Elements...>>::type

3986

>::type

3987

get(tuple<_Elements...>& __t) noexcept

3988

- { return __get_helper<__i>(__t); }

3989

+ { return std::__get_helper<__i>(__t); }

3990

3991

template<std::size_t __i, typename... _Elements>

3992

constexpr typename __add_c_ref<

3993

@@ -762,7 +762,7 @@

3994

typename tuple_element<__i, tuple<_Elements...>>::type

3995

>::type

3996

get(const tuple<_Elements...>& __t) noexcept

3997

- { return __get_helper<__i>(__t); }

3998

+ { return std::__get_helper<__i>(__t); }

3999

4000

template<std::size_t __i, typename... _Elements>

4001

constexpr typename __add_r_ref<

4002

Index: libstdc++-v3/include/std/future

4003

===================================================================

4004

--- a/src/libstdc++-v3/include/std/future (.../tags/gcc_4_8_2_release)

4005

+++ b/src/libstdc++-v3/include/std/future (.../branches/gcc-4_8-branch)

4006

@@ -1261,9 +1261,11 @@

4007

struct __future_base::_Task_state<_Fn, _Alloc, _Res(_Args...)> final

4008

: __future_base::_Task_state_base<_Res(_Args...)>

4009

{

4010

- _Task_state(_Fn&& __fn, const _Alloc& __a)

4011

- : _Task_state_base<_Res(_Args...)>(__a), _M_impl(std::move(__fn), __a)

4012

- { }

4013

+ template<typename _Fn2>

4014

+ _Task_state(_Fn2&& __fn, const _Alloc& __a)

4015

+ : _Task_state_base<_Res(_Args...)>(__a),

4016

+ _M_impl(std::forward<_Fn2>(__fn), __a)

4017

+ { }

4018

4019

private:

4020

virtual void

4021

@@ -1292,19 +1294,21 @@

4022

4023

struct _Impl : _Alloc

4024

{

4025

- _Impl(_Fn&& __fn, const _Alloc& __a)

4026

- : _Alloc(__a), _M_fn(std::move(__fn)) { }

4027

+ template<typename _Fn2>

4028

+ _Impl(_Fn2&& __fn, const _Alloc& __a)

4029

+ : _Alloc(__a), _M_fn(std::forward<_Fn2>(__fn)) { }

4030

_Fn _M_fn;

4031

} _M_impl;

4032

};

4033

4034

- template<typename _Signature, typename _Fn, typename _Alloc>

4035

- static shared_ptr<__future_base::_Task_state_base<_Signature>>

4036

- __create_task_state(_Fn&& __fn, const _Alloc& __a)

4037

- {

4038

- typedef __future_base::_Task_state<_Fn, _Alloc, _Signature> _State;

4039

- return std::allocate_shared<_State>(__a, std::move(__fn), __a);

4040

- }

4041

+ template<typename _Signature, typename _Fn, typename _Alloc>

4042

+ static shared_ptr<__future_base::_Task_state_base<_Signature>>

4043

+ __create_task_state(_Fn&& __fn, const _Alloc& __a)

4044

+ {

4045

+ typedef typename decay<_Fn>::type _Fn2;

4046

+ typedef __future_base::_Task_state<_Fn2, _Alloc, _Signature> _State;

4047

+ return std::allocate_shared<_State>(__a, std::forward<_Fn>(__fn), __a);

4048

+ }

4049

4050

template<typename _Fn, typename _Alloc, typename _Res, typename... _Args>

4051

shared_ptr<__future_base::_Task_state_base<_Res(_Args...)>>

4052

@@ -1344,7 +1348,8 @@

4053

__constrain_pkgdtask<packaged_task, _Fn>::__type>

4054

explicit

4055

packaged_task(_Fn&& __fn)

4056

- : packaged_task(allocator_arg, std::allocator<int>(), std::move(__fn))

4057

+ : packaged_task(allocator_arg, std::allocator<int>(),

4058

+ std::forward<_Fn>(__fn))

4059

{ }

4060

4061

// _GLIBCXX_RESOLVE_LIB_DEFECTS

4062

Index: libstdc++-v3/include/bits/atomic_base.h

4063

===================================================================

4064

--- a/src/libstdc++-v3/include/bits/atomic_base.h (.../tags/gcc_4_8_2_release)

4065

+++ b/src/libstdc++-v3/include/bits/atomic_base.h (.../branches/gcc-4_8-branch)

4066

@@ -764,11 +764,11 @@

4067

4068

bool

4069

is_lock_free() const noexcept

4070

- { return __atomic_is_lock_free(_M_type_size(1), nullptr); }

4071

+ { return __atomic_is_lock_free(sizeof(__pointer_type), nullptr); }

4072

4073

bool

4074

is_lock_free() const volatile noexcept

4075

- { return __atomic_is_lock_free(_M_type_size(1), nullptr); }

4076

+ { return __atomic_is_lock_free(sizeof(__pointer_type), nullptr); }

4077

4078

void

4079

store(__pointer_type __p,

4080

Index: libstdc++-v3/include/bits/stl_vector.h

4081

===================================================================

4082

--- a/src/libstdc++-v3/include/bits/stl_vector.h (.../tags/gcc_4_8_2_release)

4083

+++ b/src/libstdc++-v3/include/bits/stl_vector.h (.../branches/gcc-4_8-branch)

4084

@@ -1361,7 +1361,8 @@

4085

void

4086

_M_move_assign(vector&& __x, std::true_type) noexcept

4087

{

4088

- const vector __tmp(std::move(*this));

4089

+ vector __tmp(get_allocator());

4090

+ this->_M_impl._M_swap_data(__tmp._M_impl);

4091

this->_M_impl._M_swap_data(__x._M_impl);

4092

if (_Alloc_traits::_S_propagate_on_move_assign())

4093

std::__alloc_on_move(_M_get_Tp_allocator(),

4094

Index: libstdc++-v3/include/bits/stl_algo.h

4095

===================================================================

4096

--- a/src/libstdc++-v3/include/bits/stl_algo.h (.../tags/gcc_4_8_2_release)

4097

+++ b/src/libstdc++-v3/include/bits/stl_algo.h (.../branches/gcc-4_8-branch)

4098

@@ -2279,7 +2279,7 @@

4099

_RandomAccessIterator __last)

4100

{

4101

_RandomAccessIterator __mid = __first + (__last - __first) / 2;

4102

- std::__move_median_to_first(__first, __first + 1, __mid, (__last - 2));

4103

+ std::__move_median_to_first(__first, __first + 1, __mid, __last - 1);

4104

return std::__unguarded_partition(__first + 1, __last, *__first);

4105

}

4106

4107

@@ -2291,7 +2291,7 @@

4108

_RandomAccessIterator __last, _Compare __comp)

4109

{

4110

_RandomAccessIterator __mid = __first + (__last - __first) / 2;

4111

- std::__move_median_to_first(__first, __first + 1, __mid, (__last - 2),

4112

+ std::__move_median_to_first(__first, __first + 1, __mid, __last - 1,

4113

__comp);

4114

return std::__unguarded_partition(__first + 1, __last, *__first, __comp);

4115

}

4116

Index: libstdc++-v3/include/bits/shared_ptr_base.h

4117

===================================================================

4118

--- a/src/libstdc++-v3/include/bits/shared_ptr_base.h (.../tags/gcc_4_8_2_release)

4119

+++ b/src/libstdc++-v3/include/bits/shared_ptr_base.h (.../branches/gcc-4_8-branch)

4120

@@ -233,7 +233,7 @@

4121

_M_add_ref_lock()

4122

{

4123

// Perform lock-free add-if-not-zero operation.

4124

- _Atomic_word __count = _M_use_count;

4125

+ _Atomic_word __count = _M_get_use_count();

4126

do

4127

{

4128

if (__count == 0)

4129

@@ -391,7 +391,7 @@

4130

public:

4131

template<typename... _Args>

4132

_Sp_counted_ptr_inplace(_Alloc __a, _Args&&... __args)

4133

- : _M_impl(__a), _M_storage()

4134

+ : _M_impl(__a)

4135

{

4136

_M_impl._M_ptr = static_cast<_Tp*>(static_cast<void*>(&_M_storage));

4137

// _GLIBCXX_RESOLVE_LIB_DEFECTS

4138

@@ -819,7 +819,7 @@

4139

: _M_ptr(__r.get()), _M_refcount()

4140

{

4141

__glibcxx_function_requires(_ConvertibleConcept<_Tp1*, _Tp*>)

4142

- auto __tmp = std::__addressof(*__r.get());

4143

+ auto __tmp = __r.get();

4144

_M_refcount = __shared_count<_Lp>(std::move(__r));

4145

__enable_shared_from_this_helper(_M_refcount, __tmp, __tmp);

4146

}

4147

Index: libstdc++-v3/include/c_global/cstdio

4148

===================================================================

4149

--- a/src/libstdc++-v3/include/c_global/cstdio (.../tags/gcc_4_8_2_release)

4150

+++ b/src/libstdc++-v3/include/c_global/cstdio (.../branches/gcc-4_8-branch)

4151

@@ -69,6 +69,7 @@

4152

#undef ftell

4153

#undef fwrite

4154

#undef getc

4155

+#undef getchar

4156

#undef gets

4157

#undef perror

4158

#undef printf

4159

Index: libstdc++-v3/ChangeLog

4160

===================================================================

4161

--- a/src/libstdc++-v3/ChangeLog (.../tags/gcc_4_8_2_release)

4162

+++ b/src/libstdc++-v3/ChangeLog (.../branches/gcc-4_8-branch)

4163

@@ -1,3 +1,178 @@

4164

+2014-04-27 Jonathan Wakely <jwakely@redhat.com>

4165

+

4166

+ PR libstdc++/60497

4167

+ * include/std/tuple (get): Qualify calls to prevent ADL.

4168

+ * testsuite/20_util/tuple/60497.cc: New.

4169

+

4170

+2012-04-05 Dominique d'Humieres <dominiq@lps.ens.fr>

4171

+ Jack Howarth <howarth@bromo.med.uc.edu>

4172

+

4173

+ PR target/54407

4174

+ * 30_threads/condition_variable/54185.cc: Skip for darwin < 11.

4175

+

4176

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

4177

+

4178

+ Backport from mainline

4179

+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

4180

+

4181

+ * configure: Regenerate.

4182

+

4183

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

4184

+

4185

+ Backport from mainline r204808:

4186

+

4187

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

4188

+

4189

+ * scripts/extract_symvers.in: Ignore <localentry: > fields

4190

+ in readelf --symbols output.

4191

+

4192

+2014-03-26 Jonathan Wakely <jwakely@redhat.com>

4193

+

4194

+ PR libstdc++/59548

4195

+ * include/debug/safe_unordered_base.h (_Safe_unordered_container_base):

4196

+ Define copy and move constructors that handle iterators correctly.

4197

+ * testsuite/23_containers/unordered_map/59548.cc: New.

4198

+

4199

+2014-03-25 Jonathan Wakely <jwakely@redhat.com>

4200

+

4201

+ PR libstdc++/60658

4202

+ * include/bits/atomic_base.h (__atomic_base<_PTp*>::is_lock_free()):

4203

+ Use sizeof pointer type not the element type.

4204

+ * testsuite/29_atomics/atomic/60658.cc: New.

4205

+

4206

+2014-03-18 Jonathan Wakely <jwakely@redhat.com>

4207

+

4208

+ PR libstdc++/60564

4209

+ * include/std/future (__future_base::_Task_state<>): Change

4210

+ constructors to template functions using perfect forwarding.

4211

+ (__create_task_state): Use decayed type as stored task.

4212

+ (packaged_task::packaged_task(_Fn&&)): Forward instead of moving.

4213

+ * testsuite/30_threads/packaged_task/60564.cc: New.

4214

+

4215

+2014-03-12 Roland McGrath <mcgrathr@google.com>

4216

+ Mark Seaborn <mseaborn@google.com>

4217

+

4218

+ PR libstdc++/59392

4219

+ * libsupc++/eh_call.cc (__cxa_call_unexpected): Call __do_catch with

4220

+ the address of a null pointer, not with a null pointer to pointer.

4221

+ Copy comment for this case from eh_personality.cc:__cxa_call_unexpected.

4222

+ * testsuite/18_support/bad_exception/59392.cc: New file.

4223

+

4224

+2014-03-11 Jonathan Wakely <jwakely@redhat.com>

4225

+

4226

+ Backport from mainline.

4227

+ 2014-01-09 Jonathan Wakely <jwakely@redhat.com>

4228

+

4229

+ PR libstdc++/59680

4230

+ * src/c++11/thread.cc (__sleep_for): Fix call to ::sleep.

4231

+

4232

+2014-03-11 Jonathan Wakely <jwakely@redhat.com>

4233

+

4234

+ Backport from mainline.

4235

+ 2014-01-27 Jonathan Wakely <jwakely@redhat.com>

4236

+

4237

+ PR libstdc++/59215

4238

+ * include/bits/shared_ptr_base.h

4239

+ (_Sp_counted_base<_S_atomic>::_M_add_ref_lock()): Use relaxed atomic

4240

+ load.

4241

+

4242

+2014-03-11 Jonathan Wakely <jwakely@redhat.com>

4243

+

4244

+ Backport from mainline.

4245

+

4246

+ 2014-01-09 Jonathan Wakely <jwakely@redhat.com>

4247

+

4248

+ PR libstdc++/59738

4249

+ * include/bits/stl_vector.h (vector<>::_M_move_assign): Restore

4250

+ support for non-Movable types.

4251

+

4252

+ 2014-01-08 François Dumont <fdumont@gcc.gnu.org>

4253

+

4254

+ * include/bits/stl_vector.h (std::vector<>::_M_move_assign): Pass

4255

+ *this allocator instance when building temporary vector instance

4256

+ so that *this allocator does not get moved.

4257

+ * testsuite/23_containers/vector/allocator/move.cc (test01): Add

4258

+ check on a vector iterator.

4259

+ * testsuite/23_containers/vector/allocator/move_assign.cc

4260

+ (test02): Likewise.

4261

+ (test03): New, test with a non-propagating allocator.

4262

+

4263

+ 2013-11-15 Jonathan Wakely <jwakely.gcc@gmail.com>

4264

+

4265

+ * testsuite/23_containers/vector/allocator/move.cc: New

4266

+

4267

+2014-01-27 Jason Merrill <jason@redhat.com>

4268

+

4269

+ Core DR 475

4270

+ PR c++/41174

4271

+ PR c++/59224

4272

+ * libsupc++/eh_throw.cc (__cxa_throw): Set uncaughtExceptions.

4273

+ * libsupc++/eh_alloc.cc (__cxa_allocate_dependent_exception)

4274

+ (__cxa_allocate_exception): Don't set it here.

4275

+

4276

+2013-12-15 H.J. Lu <hongjiu.lu@intel.com>

4277

+

4278

+ * config/abi/post/x86_64-linux-gnu/x32/baseline_symbols.txt: Update.

4279

+

4280

+2013-11-22 Jonathan Wakely <jwakely.gcc@gmail.com>

4281

+

4282

+ * acinclude.m4 (libtool_VERSION): Bump.

4283

+ * configure: Regenerate.

4284

+ * doc/xml/manual/abi.xml: Update version information.

4285

+

4286

+2013-11-05 Jonathan Wakely <jwakely.gcc@gmail.com>

4287

+

4288

+ * doc/xml/manual/status_cxx2011.xml: Document aligned_union as

4289

+ missing.

4290

+

4291

+ * doc/xml/manual/spine.xml: Update copyright years.

4292

+ * doc/html/*: Regenerate.

4293

+

4294

+2013-11-01 Paolo Carlini <paolo.carlini@oracle.com>

4295

+

4296

+ PR libstdc++/58952

4297

+ * include/c_global/cstdio: Undef getchar.

4298

+

4299

+2013-10-31 Jonathan Wakely <jwakely.gcc@gmail.com>

4300

+

4301

+ * testsuite/20_util/shared_ptr/cons/58839.cc: Do not use

4302

+ default_delete<void>.

4303

+

4304

+2013-10-30 Chris Studholme <cvs@cs.utoronto.ca>

4305

+

4306

+ PR libstdc++/58912

4307

+ * include/bits/shared_ptr_base.h (_Sp_counted_ptr_inplace): Remove

4308

+ unnecessary initialization of storage buffer.

4309

+

4310

+2013-10-29 Jonathan Wakely <jwakely.gcc@gmail.com>

4311

+

4312

+ PR libstdc++/58839

4313

+ * include/bits/shared_ptr_base.h

4314

+ (__shared_ptr<T>::__shared_ptr(unique_ptr<U,D>&&)): Do not dereference

4315

+ pointer.

4316

+ * testsuite/20_util/shared_ptr/cons/58839.cc: New.

4317

+

4318

+2013-10-20 Chris Jefferson <chris@bubblescope.net>

4319

+ Paolo Carlini <paolo.carlini@oracle.com>

4320

+

4321

+ PR libstdc++/58800

4322

+ * include/bits/stl_algo.h (__unguarded_partition_pivot): Change

4323

+ __last - 2 to __last - 1.

4324

+ * testsuite/25_algorithms/nth_element/58800.cc: New

4325

+

4326

+2013-10-16 François Dumont <fdumont@gcc.gnu.org>

4327

+

4328

+ PR libstdc++/58191

4329

+ * include/debug/macros.h (__glibcxx_check_partitioned_lower): Add

4330

+ __gnu_debug::__base calls on iterators passed to internal debug

4331

+ check.

4332

+ (__glibcxx_check_partitioned_lower_pred): Likewise.

4333

+ (__glibcxx_check_partitioned_upper): Likewise.

4334

+ (__glibcxx_check_partitioned_upper_pred): Likewise.

4335

+ * include/debug/functions.h (__check_partitioned_lower):

4336

+ Remove code to detect safe iterators.

4337

+ (__check_partitioned_upper): Likewise.

4338

+

4339

2013-10-16 Release Manager

4340

4341

* GCC 4.8.2 released.

4342

Index: libstdc++-v3/libsupc++/eh_call.cc

4343

===================================================================

4344

--- a/src/libstdc++-v3/libsupc++/eh_call.cc (.../tags/gcc_4_8_2_release)

4345

+++ b/src/libstdc++-v3/libsupc++/eh_call.cc (.../branches/gcc-4_8-branch)

4346

@@ -104,14 +104,14 @@

4347

} end_catch_protect_obj;

4348

4349

4350

- __try

4351

- {

4352

+ __try

4353

+ {

4354

if (foreign_exception)

4355

std::unexpected();

4356

else

4357

__unexpected(unexpectedHandler);

4358

}

4359

- __catch(...)

4360

+ __catch(...)

4361

{

4362

/* See if the new exception matches the rtti list. */

4363

if (foreign_exception)

4364

@@ -140,15 +140,19 @@

4365

&new_ptr) != ctm_failed)

4366

__throw_exception_again;

4367

4368

- if (catch_type->__do_catch(&bad_exc, 0, 1))

4369

+ // If the exception spec allows std::bad_exception, throw that.

4370

+ // We don't have a thrown object to compare against, but since

4371

+ // bad_exception doesn't have virtual bases, that's OK; just pass NULL.

4372

+ void* obj = NULL;

4373

+ if (catch_type->__do_catch(&bad_exc, &obj, 1))

4374

bad_exception_allowed = true;

4375

}

4376

4377

// If the exception spec allows std::bad_exception, throw that.

4378

-#ifdef __EXCEPTIONS

4379

+#ifdef __EXCEPTIONS

4380

if (bad_exception_allowed)

4381

throw std::bad_exception();

4382

-#endif

4383

+#endif

4384

4385

// Otherwise, die.

4386

__terminate(terminateHandler);

4387

Index: libstdc++-v3/libsupc++/eh_alloc.cc

4388

===================================================================

4389

--- a/src/libstdc++-v3/libsupc++/eh_alloc.cc (.../tags/gcc_4_8_2_release)

4390

+++ b/src/libstdc++-v3/libsupc++/eh_alloc.cc (.../branches/gcc-4_8-branch)

4391

@@ -129,12 +129,6 @@

4392

std::terminate ();

4393

}

4394

4395

- // We have an uncaught exception as soon as we allocate memory. This

4396

- // yields uncaught_exception() true during the copy-constructor that

4397

- // initializes the exception object. See Issue 475.

4398

- __cxa_eh_globals *globals = __cxa_get_globals ();

4399

- globals->uncaughtExceptions += 1;

4400

-

4401

memset (ret, 0, sizeof (__cxa_refcounted_exception));

4402

4403

return (void *)((char *)ret + sizeof (__cxa_refcounted_exception));

4404

@@ -191,12 +185,6 @@

4405

std::terminate ();

4406

}

4407

4408

- // We have an uncaught exception as soon as we allocate memory. This

4409

- // yields uncaught_exception() true during the copy-constructor that

4410

- // initializes the exception object. See Issue 475.

4411

- __cxa_eh_globals *globals = __cxa_get_globals ();

4412

- globals->uncaughtExceptions += 1;

4413

-

4414

memset (ret, 0, sizeof (__cxa_dependent_exception));

4415

4416

return ret;

4417

Index: libstdc++-v3/libsupc++/eh_throw.cc

4418

===================================================================

4419

--- a/src/libstdc++-v3/libsupc++/eh_throw.cc (.../tags/gcc_4_8_2_release)

4420

+++ b/src/libstdc++-v3/libsupc++/eh_throw.cc (.../branches/gcc-4_8-branch)

4421

@@ -62,6 +62,9 @@

4422

{

4423

PROBE2 (throw, obj, tinfo);

4424

4425

+ __cxa_eh_globals *globals = __cxa_get_globals ();

4426

+ globals->uncaughtExceptions += 1;

4427

+

4428

// Definitely a primary.

4429

__cxa_refcounted_exception *header

4430

= __get_refcounted_exception_header_from_obj (obj);

4431

Index: libstdc++-v3/testsuite/25_algorithms/nth_element/58800.cc

4432

===================================================================

4433

--- a/src/libstdc++-v3/testsuite/25_algorithms/nth_element/58800.cc (.../tags/gcc_4_8_2_release)

4434

+++ b/src/libstdc++-v3/testsuite/25_algorithms/nth_element/58800.cc (.../branches/gcc-4_8-branch)

4435

@@ -0,0 +1,52 @@

4436

4437

+//

4438

+// This file is part of the GNU ISO C++ Library. This library is free

4439

+// software; you can redistribute it and/or modify it under the

4440

+// terms of the GNU General Public License as published by the

4441

+// Free Software Foundation; either version 3, or (at your option)

4442

+// any later version.

4443

+

4444

+// This library is distributed in the hope that it will be useful,

4445

+// but WITHOUT ANY WARRANTY; without even the implied warranty of

4446

+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

4447

+// GNU General Public License for more details.

4448

+

4449

+// You should have received a copy of the GNU General Public License along

4450

+// with this library; see the file COPYING3. If not see

4451

+// <http://www.gnu.org/licenses/>.

4452

+

4453

+// 25.3.2 [lib.alg.nth.element]

4454

+

4455

+// { dg-options "-std=gnu++11" }

4456

+

4457

+#include <algorithm>

4458

+#include <testsuite_hooks.h>

4459

+#include <testsuite_iterators.h>

4460

+

4461

+using __gnu_test::test_container;

4462

+using __gnu_test::random_access_iterator_wrapper;

4463

+

4464

+typedef test_container<int, random_access_iterator_wrapper> Container;

4465

+

4466

+void test01()

4467

+{

4468

+ std::vector<int> v = {

4469

+ 207089,

4470

+ 202585,

4471

+ 180067,

4472

+ 157549,

4473

+ 211592,

4474

+ 216096,

4475

+ 207089

4476

+ };

4477

+

4478

+ Container con(v.data(), v.data() + 7);

4479

+

4480

+ std::nth_element(con.begin(), con.begin() + 3, con.end());

4481

+}

4482

+

4483

+int main()

4484

+{

4485

+ test01();

4486

+ return 0;

4487

+}

4488

Index: libstdc++-v3/testsuite/18_support/bad_exception/59392.cc

4489

===================================================================

4490

--- a/src/libstdc++-v3/testsuite/18_support/bad_exception/59392.cc (.../tags/gcc_4_8_2_release)

4491

+++ b/src/libstdc++-v3/testsuite/18_support/bad_exception/59392.cc (.../branches/gcc-4_8-branch)

4492

@@ -0,0 +1,51 @@

4493

4494

+//

4495

+// This file is part of the GNU ISO C++ Library. This library is free

4496

+// software; you can redistribute it and/or modify it under the

4497

+// terms of the GNU General Public License as published by the

4498

+// Free Software Foundation; either version 3, or (at your option)

4499

+// any later version.

4500

+

4501

+// This library is distributed in the hope that it will be useful,

4502

+// but WITHOUT ANY WARRANTY; without even the implied warranty of

4503

+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

4504

+// GNU General Public License for more details.

4505

+

4506

+// You should have received a copy of the GNU General Public License along

4507

+// with this library; see the file COPYING3. If not see

4508

+// <http://www.gnu.org/licenses/>.

4509

+

4510

+#include <exception>

4511

+#include <cstdlib>

4512

+

4513

+class expected {};

4514

+class unexpected {};

4515

+class from_handler {};

4516

+

4517

+static void func_with_exception_spec() throw(expected)

4518

+{

4519

+ throw unexpected();

4520

+}

4521

+

4522

+static void unexpected_handler()

4523

+{

4524

+ throw from_handler();

4525

+}

4526

+

4527

+static void terminate_handler()

4528

+{

4529

+ exit(0);

4530

+}

4531

+

4532

+// libstdc++/59392

4533

+int main()

4534

+{

4535

+ std::set_unexpected(unexpected_handler);

4536

+ std::set_terminate(terminate_handler);

4537

+ try {

4538

+ func_with_exception_spec();

4539

+ } catch (expected&) {

4540

+ abort();

4541

+ }

4542

+ abort();

4543

+}

4544

4545

Property changes on: libstdc++-v3/testsuite/18_support/bad_exception/59392.cc

4546

___________________________________________________________________

4547

Added: svn:eol-style

4548

## -0,0 +1 ##

4549

+LF

4550

\ No newline at end of property

4551

Index: libstdc++-v3/testsuite/30_threads/packaged_task/60564.cc

4552

===================================================================

4553

--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/60564.cc (.../tags/gcc_4_8_2_release)

4554

+++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/60564.cc (.../branches/gcc-4_8-branch)

4555

@@ -0,0 +1,51 @@

4556

+// { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-gnu* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } }

4557

+// { dg-options " -std=gnu++11 -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-gnu* powerpc-ibm-aix* } }

4558

+// { dg-options " -std=gnu++11 -pthreads" { target *-*-solaris* } }

4559

+// { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-darwin* } }

4560

+// { dg-require-cstdint "" }

4561

+// { dg-require-gthreads "" }

4562

+// { dg-require-atomic-builtins "" }

4563

+

4564

4565

+//

4566

+// This file is part of the GNU ISO C++ Library. This library is free

4567

+// software; you can redistribute it and/or modify it under the

4568

+// terms of the GNU General Public License as published by the

4569

+// Free Software Foundation; either version 3, or (at your option)

4570

+// any later version.

4571

+

4572

+// This library is distributed in the hope that it will be useful,

4573

+// but WITHOUT ANY WARRANTY; without even the implied warranty of

4574

+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

4575

+// GNU General Public License for more details.

4576

+

4577

+// You should have received a copy of the GNU General Public License along

4578

+// with this library; see the file COPYING3. If not see

4579

+// <http://www.gnu.org/licenses/>.

4580

+

4581

+

4582

+#include <future>

4583

+#include <testsuite_hooks.h>

4584

+

4585

+struct X

4586

+{

4587

+ X() = default;

4588

+ X(const X&) = default;

4589

+ X(X&& x) { x.moved = true; }

4590

+

4591

+ void operator()() const { }

4592

+

4593

+ bool moved = false;

4594

+};

4595

+

4596

+void test01()

4597

+{

4598

+ X x;

4599

+ std::packaged_task<void()> p(x);

4600

+ VERIFY( !x.moved );

4601

+}

4602

+

4603

+int main()

4604

+{

4605

+ test01();

4606

+}

4607

Index: libstdc++-v3/testsuite/30_threads/condition_variable/54185.cc

4608

===================================================================

4609

--- a/src/libstdc++-v3/testsuite/30_threads/condition_variable/54185.cc (.../tags/gcc_4_8_2_release)

4610

+++ b/src/libstdc++-v3/testsuite/30_threads/condition_variable/54185.cc (.../branches/gcc-4_8-branch)

4611

@@ -1,11 +1,11 @@

4612

-// { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } }

4613

-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } }

4614

+// { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-gnu* *-*-solaris* *-*-cygwin *-*-darwin1[1-9]* powerpc-ibm-aix* } }

4615

+// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-gnu* powerpc-ibm-aix* } }

4616

// { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } }

4617

// { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } }

4618

// { dg-require-cstdint "" }

4619

// { dg-require-gthreads "" }

4620

4621

4622

4623

//

4624

// This file is part of the GNU ISO C++ Library. This library is free

4625

// software; you can redistribute it and/or modify it under the

4626

Index: libstdc++-v3/testsuite/29_atomics/atomic/60658.cc

4627

===================================================================

4628

--- a/src/libstdc++-v3/testsuite/29_atomics/atomic/60658.cc (.../tags/gcc_4_8_2_release)

4629

+++ b/src/libstdc++-v3/testsuite/29_atomics/atomic/60658.cc (.../branches/gcc-4_8-branch)

4630

@@ -0,0 +1,43 @@

4631

+// { dg-require-atomic-builtins "" }

4632

+// { dg-options "-std=gnu++11" }

4633

+

4634

4635

+//

4636

+// This file is part of the GNU ISO C++ Library. This library is free

4637

+// software; you can redistribute it and/or modify it under the

4638

+// terms of the GNU General Public License as published by the

4639

+// Free Software Foundation; either version 3, or (at your option)

4640

+// any later version.

4641

+

4642

+// This library is distributed in the hope that it will be useful,

4643

+// but WITHOUT ANY WARRANTY; without even the implied warranty of

4644

+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

4645

+// GNU General Public License for more details.

4646

+

4647

+// You should have received a copy of the GNU General Public License along

4648

+// with this library; see the file COPYING3. If not see

4649

+// <http://www.gnu.org/licenses/>.

4650

+

4651

+#include <atomic>

4652

+#include <testsuite_hooks.h>

4653

+

4654

+// libstdc++/60658

4655

+

4656

+struct Foo {

4657

+ char buf[1];

4658

+};

4659

+

4660

+struct Bar {

4661

+ char buf[100];

4662

+};

4663

+

4664

+int

4665

+main ()

4666

+{

4667

+ bool test __attribute__((unused)) = true;

4668

+

4669

+ std::atomic<Foo*> a;

4670

+ std::atomic<Bar*> b;

4671

+

4672

+ VERIFY (a.is_lock_free() == b.is_lock_free());

4673

+}

4674

Index: libstdc++-v3/testsuite/23_containers/unordered_map/59548.cc

4675

===================================================================

4676

--- a/src/libstdc++-v3/testsuite/23_containers/unordered_map/59548.cc (.../tags/gcc_4_8_2_release)

4677

+++ b/src/libstdc++-v3/testsuite/23_containers/unordered_map/59548.cc (.../branches/gcc-4_8-branch)

4678

@@ -0,0 +1,34 @@

4679

+// { dg-options "-std=gnu++11" }

4680

+// { dg-do compile }

4681

+// { dg-require-debug-mode "" }

4682

+

4683

4684

+//

4685

+// This file is part of the GNU ISO C++ Library. This library is free

4686

+// software; you can redistribute it and/or modify it under the

4687

+// terms of the GNU General Public License as published by the

4688

+// Free Software Foundation; either version 3, or (at your option)

4689

+// any later version.

4690

+

4691

+// This library is distributed in the hope that it will be useful,

4692

+// but WITHOUT ANY WARRANTY; without even the implied warranty of

4693

+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

4694

+// GNU General Public License for more details.

4695

+

4696

+// You should have received a copy of the GNU General Public License along

4697

+// with this library; see the file COPYING3. If not see

4698

+// <http://www.gnu.org/licenses/>.

4699

+

4700

+// libstdc++/59548

4701

+

4702

+#include <unordered_map>

4703

+

4704

+int main()

4705

+{

4706

+ std::unordered_map<int,int> foo{ {0,1} };

4707

+ auto i = foo.begin();

4708

+ {

4709

+ auto bar = foo;

4710

+ }

4711

+ return i->first;

4712

+}

4713

Index: libstdc++-v3/testsuite/23_containers/vector/allocator/move.cc

4714

===================================================================

4715

--- a/src/libstdc++-v3/testsuite/23_containers/vector/allocator/move.cc (.../tags/gcc_4_8_2_release)

4716

+++ b/src/libstdc++-v3/testsuite/23_containers/vector/allocator/move.cc (.../branches/gcc-4_8-branch)

4717

@@ -0,0 +1,59 @@

4718

4719

+//

4720

+// This file is part of the GNU ISO C++ Library. This library is free

4721

+// software; you can redistribute it and/or modify it under the

4722

+// terms of the GNU General Public License as published by the

4723

+// Free Software Foundation; either version 3, or (at your option)

4724

+// any later version.

4725

+

4726

+// This library is distributed in the hope that it will be useful,

4727

+// but WITHOUT ANY WARRANTY; without even the implied warranty of

4728

+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

4729

+// GNU General Public License for more details.

4730

+

4731

+// You should have received a copy of the GNU General Public License along

4732

+// with this library; see the file COPYING3. If not see

4733

+// <http://www.gnu.org/licenses/>.

4734

+

4735

+// { dg-options "-std=gnu++11" }

4736

+

4737

+#include <vector>

4738

+#include <testsuite_hooks.h>

4739

+#include <testsuite_allocator.h>

4740

+

4741

+struct T { int i; };

4742

+

4743

+using __gnu_test::uneq_allocator;

4744

+

4745

+void test01()

4746

+{

4747

+ bool test __attribute__((unused)) = true;

4748

+ typedef uneq_allocator<T> alloc_type;

4749

+ typedef std::vector<T, alloc_type> test_type;

4750

+ test_type v1(alloc_type(1));

4751

+ v1 = { T() };

4752

+ auto it = v1.begin();

4753

+ test_type v2(std::move(v1));

4754

+ VERIFY(1 == v1.get_allocator().get_personality());

4755

+ VERIFY(1 == v2.get_allocator().get_personality());

4756

+ VERIFY( it == v2.begin() );

4757

+}

4758

+

4759

+void test02()

4760

+{

4761

+ bool test __attribute__((unused)) = true;

4762

+ typedef uneq_allocator<T> alloc_type;

4763

+ typedef std::vector<T, alloc_type> test_type;

4764

+ test_type v1(alloc_type(1));

4765

+ v1 = { T() };

4766

+ test_type v2(std::move(v1), alloc_type(2));

4767

+ VERIFY(1 == v1.get_allocator().get_personality());

4768

+ VERIFY(2 == v2.get_allocator().get_personality());

4769

+}

4770

+

4771

+int main()

4772

+{

4773

+ test01();

4774

+ test02();

4775

+ return 0;

4776

+}

4777

Index: libstdc++-v3/testsuite/23_containers/vector/allocator/move_assign.cc

4778

===================================================================

4779

--- a/src/libstdc++-v3/testsuite/23_containers/vector/allocator/move_assign.cc (.../tags/gcc_4_8_2_release)

4780

+++ b/src/libstdc++-v3/testsuite/23_containers/vector/allocator/move_assign.cc (.../branches/gcc-4_8-branch)

4781

@@ -46,16 +46,35 @@

4782

typedef std::vector<T, alloc_type> test_type;

4783

test_type v1(alloc_type(1));

4784

v1.push_back(T());

4785

+ auto it = v1.begin();

4786

test_type v2(alloc_type(2));

4787

+ v2.push_back(T());

4788

v2 = std::move(v1);

4789

- v2.push_back(T());

4790

+ VERIFY( it == v2.begin() );

4791

VERIFY(0 == v1.get_allocator().get_personality());

4792

VERIFY(1 == v2.get_allocator().get_personality());

4793

}

4794

4795

+void test03()

4796

+{

4797

+ bool test __attribute__((unused)) = true;

4798

+ typedef propagating_allocator<T, false> alloc_type;

4799

+ typedef std::vector<T, alloc_type> test_type;

4800

+ test_type v1(alloc_type(1));

4801

+ v1.push_back(T());

4802

+ auto it = v1.begin();

4803

+ test_type v2(alloc_type(1));

4804

+ v2.push_back(T());

4805

+ v2 = std::move(v1);

4806

+ VERIFY( it == v2.begin() );

4807

+ VERIFY(1 == v1.get_allocator().get_personality());

4808

+ VERIFY(1 == v2.get_allocator().get_personality());

4809

+}

4810

+

4811

int main()

4812

{

4813

test01();

4814

test02();

4815

+ test03();

4816

return 0;

4817

}

4818

Index: libstdc++-v3/testsuite/20_util/tuple/60497.cc

4819

===================================================================

4820

--- a/src/libstdc++-v3/testsuite/20_util/tuple/60497.cc (.../tags/gcc_4_8_2_release)

4821

+++ b/src/libstdc++-v3/testsuite/20_util/tuple/60497.cc (.../branches/gcc-4_8-branch)

4822

@@ -0,0 +1,35 @@

4823

+// { dg-options "-std=gnu++11" }

4824

+// { dg-do compile }

4825

+

4826

4827

+//

4828

+// This file is part of the GNU ISO C++ Library. This library is free

4829

+// software; you can redistribute it and/or modify it under the

4830

+// terms of the GNU General Public License as published by the

4831

+// Free Software Foundation; either version 3, or (at your option)

4832

+// any later version.

4833

+

4834

+// This library is distributed in the hope that it will be useful,

4835

+// but WITHOUT ANY WARRANTY; without even the implied warranty of

4836

+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

4837

+// GNU General Public License for more details.

4838

+

4839

+// You should have received a copy of the GNU General Public License along

4840

+// with this library; see the file COPYING3. If not see

4841

+// <http://www.gnu.org/licenses/>.

4842

+

4843

+// libstdc++/60497

4844

+

4845

+#include <tuple>

4846

+

4847

+struct A;

4848

+template<typename T> struct B { T t; };

4849

+

4850

+using element_type = B<A>*;

4851

+using tuple_type = std::tuple<element_type>;

4852

+

4853

+tuple_type t;

4854

+const tuple_type ct;

4855

+

4856

+auto a = std::get<0>(t);

4857

+auto b = std::get<0>(ct);

4858

Index: libstdc++-v3/testsuite/20_util/shared_ptr/cons/58839.cc

4859

===================================================================

4860

--- a/src/libstdc++-v3/testsuite/20_util/shared_ptr/cons/58839.cc (.../tags/gcc_4_8_2_release)

4861

+++ b/src/libstdc++-v3/testsuite/20_util/shared_ptr/cons/58839.cc (.../branches/gcc-4_8-branch)

4862

@@ -0,0 +1,33 @@

4863

+// { dg-options "-std=gnu++11" }

4864

+// { dg-do compile }

4865

+

4866

4867

+//

4868

+// This file is part of the GNU ISO C++ Library. This library is free

4869

+// software; you can redistribute it and/or modify it under the

4870

+// terms of the GNU General Public License as published by the

4871

+// Free Software Foundation; either version 3, or (at your option)

4872

+// any later version.

4873

+

4874

+// This library is distributed in the hope that it will be useful,

4875

+// but WITHOUT ANY WARRANTY; without even the implied warranty of

4876

+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

4877

+// GNU General Public License for more details.

4878

+

4879

+// You should have received a copy of the GNU General Public License along

4880

+// with this library; see the file COPYING3. If not see

4881

+// <http://www.gnu.org/licenses/>.

4882

+

4883

+#include <memory>

4884

+

4885

+// libstdc++/58839

4886

+

4887

+struct D {

4888

+ void operator()(void*) const noexcept { }

4889

+};

4890

+

4891

+void test01()

4892

+{

4893

+ std::unique_ptr<void, D> y;

4894

+ std::shared_ptr<void> x = std::move(y);

4895

+}

4896

Index: libstdc++-v3/testsuite/20_util/bind/57899.cc

4897

===================================================================

4898

--- a/src/libstdc++-v3/testsuite/20_util/bind/57899.cc (.../tags/gcc_4_8_2_release)

4899

+++ b/src/libstdc++-v3/testsuite/20_util/bind/57899.cc (.../branches/gcc-4_8-branch)

4900

@@ -0,0 +1,48 @@

4901

4902

+//

4903

+// This file is part of the GNU ISO C++ Library. This library is free

4904

+// software; you can redistribute it and/or modify it under the

4905

+// terms of the GNU General Public License as published by the

4906

+// Free Software Foundation; either version 3, or (at your option)

4907

+// any later version.

4908

+

4909

+// This library is distributed in the hope that it will be useful,

4910

+// but WITHOUT ANY WARRANTY; without even the implied warranty of

4911

+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

4912

+// GNU General Public License for more details.

4913

+

4914

+// You should have received a copy of the GNU General Public License along

4915

+// with this library; see the file COPYING3. If not see

4916

+// <http://www.gnu.org/licenses/>.

4917

+

4918

+// 20.7.11 Function template bind

4919

+

4920

+// PR c++/57899

4921

+// { dg-do compile }

4922

+// { dg-options -std=c++11 }

4923

+

4924

+#include <functional>

4925

+using std::bind;

4926

+using std::placeholders::_1;

4927

+

4928

+struct S { int i; };

4929

+

4930

+struct P { S s; };

4931

+

4932

+struct get_s

4933

+{

4934

+ const S& operator()(const P& p) const { return p.s; }

4935

+} gs;

4936

+

4937

+int gi(const S& s) { return s.i; }

4938

+

4939

+bool cmp(int, int) { return true; }

4940

+

4941

+int main()

4942

+{

4943

+ P p{};

4944

+ auto f1 = bind(gs, _1);

4945

+ auto f2 = bind(gi, f1);

4946

+ auto f3 = bind(cmp, f2, 5);

4947

+ f3(p);

4948

+}

4949

Index: libstdc++-v3/config/abi/post/x86_64-linux-gnu/x32/baseline_symbols.txt

4950

===================================================================

4951

--- a/src/libstdc++-v3/config/abi/post/x86_64-linux-gnu/x32/baseline_symbols.txt (.../tags/gcc_4_8_2_release)

4952

+++ b/src/libstdc++-v3/config/abi/post/x86_64-linux-gnu/x32/baseline_symbols.txt (.../branches/gcc-4_8-branch)

4953

@@ -403,6 +403,7 @@

4954

FUNC:_ZNKSt15basic_streambufIwSt11char_traitsIwEE6getlocEv@@GLIBCXX_3.4

4955

FUNC:_ZNKSt15basic_stringbufIcSt11char_traitsIcESaIcEE3strEv@@GLIBCXX_3.4

4956

FUNC:_ZNKSt15basic_stringbufIwSt11char_traitsIwESaIwEE3strEv@@GLIBCXX_3.4

4957

+FUNC:_ZNKSt17bad_function_call4whatEv@@GLIBCXX_3.4.18

4958

FUNC:_ZNKSt18basic_stringstreamIcSt11char_traitsIcESaIcEE3strEv@@GLIBCXX_3.4

4959

FUNC:_ZNKSt18basic_stringstreamIcSt11char_traitsIcESaIcEE5rdbufEv@@GLIBCXX_3.4

4960

FUNC:_ZNKSt18basic_stringstreamIwSt11char_traitsIwESaIwEE3strEv@@GLIBCXX_3.4

4961

@@ -590,6 +591,8 @@

4962

FUNC:_ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES3_RSt8ios_basewm@@GLIBCXX_3.4

4963

FUNC:_ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES3_RSt8ios_basewx@@GLIBCXX_3.4

4964

FUNC:_ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES3_RSt8ios_basewy@@GLIBCXX_3.4

4965

+FUNC:_ZNKSt8__detail20_Prime_rehash_policy11_M_next_bktEj@@GLIBCXX_3.4.18

4966

+FUNC:_ZNKSt8__detail20_Prime_rehash_policy14_M_need_rehashEjjj@@GLIBCXX_3.4.18

4967

FUNC:_ZNKSt8bad_cast4whatEv@@GLIBCXX_3.4.9

4968

FUNC:_ZNKSt8ios_base7failure4whatEv@@GLIBCXX_3.4

4969

FUNC:_ZNKSt8messagesIcE18_M_convert_to_charERKSs@@GLIBCXX_3.4

4970

@@ -1207,6 +1210,7 @@

4971

FUNC:_ZNSt11regex_errorD0Ev@@GLIBCXX_3.4.15

4972

FUNC:_ZNSt11regex_errorD1Ev@@GLIBCXX_3.4.15

4973

FUNC:_ZNSt11regex_errorD2Ev@@GLIBCXX_3.4.15

4974

+FUNC:_ZNSt11this_thread11__sleep_forENSt6chrono8durationIxSt5ratioILx1ELx1EEEENS1_IxS2_ILx1ELx1000000000EEEE@@GLIBCXX_3.4.18

4975

FUNC:_ZNSt12__basic_fileIcE2fdEv@@GLIBCXX_3.4

4976

FUNC:_ZNSt12__basic_fileIcE4fileEv@@GLIBCXX_3.4.1

4977

FUNC:_ZNSt12__basic_fileIcE4openEPKcSt13_Ios_Openmodei@@GLIBCXX_3.4

4978

@@ -1485,6 +1489,11 @@

4979

FUNC:_ZNSt13basic_ostreamIwSt11char_traitsIwEElsEt@@GLIBCXX_3.4

4980

FUNC:_ZNSt13basic_ostreamIwSt11char_traitsIwEElsEx@@GLIBCXX_3.4

4981

FUNC:_ZNSt13basic_ostreamIwSt11char_traitsIwEElsEy@@GLIBCXX_3.4

4982

+FUNC:_ZNSt13random_device14_M_init_pretr1ERKSs@@GLIBCXX_3.4.18

4983

+FUNC:_ZNSt13random_device16_M_getval_pretr1Ev@@GLIBCXX_3.4.18

4984

+FUNC:_ZNSt13random_device7_M_finiEv@@GLIBCXX_3.4.18

4985

+FUNC:_ZNSt13random_device7_M_initERKSs@@GLIBCXX_3.4.18

4986

+FUNC:_ZNSt13random_device9_M_getvalEv@@GLIBCXX_3.4.18

4987

FUNC:_ZNSt13runtime_errorC1ERKSs@@GLIBCXX_3.4

4988

FUNC:_ZNSt13runtime_errorC2ERKSs@@GLIBCXX_3.4

4989

FUNC:_ZNSt13runtime_errorD0Ev@@GLIBCXX_3.4

4990

@@ -1929,6 +1938,8 @@

4991

FUNC:_ZNSt6__norm15_List_node_base8transferEPS0_S1_@@GLIBCXX_3.4.9

4992

FUNC:_ZNSt6__norm15_List_node_base9_M_unhookEv@@GLIBCXX_3.4.14

4993

FUNC:_ZNSt6chrono12system_clock3nowEv@@GLIBCXX_3.4.11

4994

+FUNC:_ZNSt6chrono3_V212steady_clock3nowEv@@GLIBCXX_3.4.19

4995

+FUNC:_ZNSt6chrono3_V212system_clock3nowEv@@GLIBCXX_3.4.19

4996

FUNC:_ZNSt6gslice8_IndexerC1EjRKSt8valarrayIjES4_@@GLIBCXX_3.4

4997

FUNC:_ZNSt6gslice8_IndexerC2EjRKSt8valarrayIjES4_@@GLIBCXX_3.4

4998

FUNC:_ZNSt6locale11_M_coalesceERKS_S1_i@@GLIBCXX_3.4

4999

@@ -2467,6 +2478,7 @@

5000

FUNC:__cxa_guard_release@@CXXABI_1.3

5001

FUNC:__cxa_pure_virtual@@CXXABI_1.3

5002

FUNC:__cxa_rethrow@@CXXABI_1.3

5003

+FUNC:__cxa_thread_atexit@@CXXABI_1.3.7

5004

FUNC:__cxa_throw@@CXXABI_1.3

5005

FUNC:__cxa_tm_cleanup@@CXXABI_TM_1

5006

FUNC:__cxa_vec_cctor@@CXXABI_1.3

5007

@@ -2491,6 +2503,7 @@

5008

OBJECT:0:CXXABI_1.3.4

5009

OBJECT:0:CXXABI_1.3.5

5010

OBJECT:0:CXXABI_1.3.6

5011

+OBJECT:0:CXXABI_1.3.7

5012

OBJECT:0:CXXABI_TM_1

5013

OBJECT:0:GLIBCXX_3.4

5014

OBJECT:0:GLIBCXX_3.4.1

5015

@@ -2502,6 +2515,8 @@

5016

OBJECT:0:GLIBCXX_3.4.15

5017

OBJECT:0:GLIBCXX_3.4.16

5018

OBJECT:0:GLIBCXX_3.4.17

5019

+OBJECT:0:GLIBCXX_3.4.18

5020

+OBJECT:0:GLIBCXX_3.4.19

5021

OBJECT:0:GLIBCXX_3.4.2

5022

OBJECT:0:GLIBCXX_3.4.3

5023

OBJECT:0:GLIBCXX_3.4.4

5024

@@ -3033,6 +3048,8 @@

5025

OBJECT:1:_ZNSt21__numeric_limits_base9is_moduloE@@GLIBCXX_3.4

5026

OBJECT:1:_ZNSt21__numeric_limits_base9is_signedE@@GLIBCXX_3.4

5027

OBJECT:1:_ZNSt6chrono12system_clock12is_monotonicE@@GLIBCXX_3.4.11

5028

+OBJECT:1:_ZNSt6chrono3_V212steady_clock9is_steadyE@@GLIBCXX_3.4.19

5029

+OBJECT:1:_ZNSt6chrono3_V212system_clock9is_steadyE@@GLIBCXX_3.4.19

5030

OBJECT:1:_ZSt10adopt_lock@@GLIBCXX_3.4.11

5031

OBJECT:1:_ZSt10defer_lock@@GLIBCXX_3.4.11

5032

OBJECT:1:_ZSt11try_to_lock@@GLIBCXX_3.4.11

5033

Index: libstdc++-v3/acinclude.m4

5034

===================================================================

5035

--- a/src/libstdc++-v3/acinclude.m4 (.../tags/gcc_4_8_2_release)

5036

+++ b/src/libstdc++-v3/acinclude.m4 (.../branches/gcc-4_8-branch)

5037

@@ -3266,7 +3266,7 @@

5038

fi

5039

5040

# For libtool versioning info, format is CURRENT:REVISION:AGE

5041

-libtool_VERSION=6:18:0

5042

+libtool_VERSION=6:19:0

5043

5044

# Everything parsed; figure out what files and settings to use.

5045

case $enable_symvers in

5046

Index: libmudflap/configure

5047

===================================================================

5048

--- a/src/libmudflap/configure (.../tags/gcc_4_8_2_release)

5049

+++ b/src/libmudflap/configure (.../branches/gcc-4_8-branch)

5050

@@ -6377,7 +6377,7 @@

5051

rm -rf conftest*

5052

;;

5053

5054

-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \

5055

+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \

5056

s390*-*linux*|s390*-*tpf*|sparc*-*linux*)

5057

# Find out which ABI we are using.

5058

echo 'int i;' > conftest.$ac_ext

5059

@@ -6402,7 +6402,10 @@

5060

;;

5061

esac

5062

;;

5063

- ppc64-*linux*|powerpc64-*linux*)

5064

+ powerpc64le-*linux*)

5065

+ LD="${LD-ld} -m elf32lppclinux"

5066

+ ;;

5067

+ powerpc64-*linux*)

5068

LD="${LD-ld} -m elf32ppclinux"

5069

;;

5070

s390x-*linux*)

5071

@@ -6421,7 +6424,10 @@

5072

x86_64-*linux*)

5073

LD="${LD-ld} -m elf_x86_64"

5074

;;

5075

- ppc*-*linux*|powerpc*-*linux*)

5076

+ powerpcle-*linux*)

5077

+ LD="${LD-ld} -m elf64lppc"

5078

+ ;;

5079

+ powerpc-*linux*)

5080

LD="${LD-ld} -m elf64ppc"

5081

;;

5082

s390*-*linux*|s390*-*tpf*)

5083

@@ -10615,7 +10621,7 @@

5084

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

5085

lt_status=$lt_dlunknown

5086

cat > conftest.$ac_ext <<_LT_EOF

5087

-#line 10618 "configure"

5088

+#line 10624 "configure"

5089

#include "confdefs.h"

5090

5091

#if HAVE_DLFCN_H

5092

@@ -10721,7 +10727,7 @@

5093

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

5094

lt_status=$lt_dlunknown

5095

cat > conftest.$ac_ext <<_LT_EOF

5096

-#line 10724 "configure"

5097

+#line 10730 "configure"

5098

#include "confdefs.h"

5099

5100

#if HAVE_DLFCN_H

5101

Index: libmudflap/ChangeLog

5102

===================================================================

5103

--- a/src/libmudflap/ChangeLog (.../tags/gcc_4_8_2_release)

5104

+++ b/src/libmudflap/ChangeLog (.../branches/gcc-4_8-branch)

5105

@@ -1,3 +1,10 @@

5106

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

5107

+

5108

+ Backport from mainline

5109

+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

5110

+

5111

+ * configure: Regenerate.

5112

+

5113

2013-10-16 Release Manager

5114

5115

* GCC 4.8.2 released.

5116

Index: boehm-gc/include/private/gcconfig.h

5117

===================================================================

5118

--- a/src/boehm-gc/include/private/gcconfig.h (.../tags/gcc_4_8_2_release)

5119

+++ b/src/boehm-gc/include/private/gcconfig.h (.../branches/gcc-4_8-branch)

5120

@@ -837,7 +837,15 @@

5121

# define NO_PTHREAD_TRYLOCK

5122

# endif

5123

# ifdef FREEBSD

5124

+# if defined(__powerpc64__)

5125

+# define ALIGNMENT 8

5126

+# define CPP_WORDSZ 64

5127

+# ifndef HBLKSIZE

5128

+# define HBLKSIZE 4096

5129

+# endif

5130

+# else

5131

# define ALIGNMENT 4

5132

+# endif

5133

# define OS_TYPE "FREEBSD"

5134

# ifndef GC_FREEBSD_THREADS

5135

# define MPROTECT_VDB

5136

Index: boehm-gc/ChangeLog

5137

===================================================================

5138

--- a/src/boehm-gc/ChangeLog (.../tags/gcc_4_8_2_release)

5139

+++ b/src/boehm-gc/ChangeLog (.../branches/gcc-4_8-branch)

5140

@@ -1,3 +1,15 @@

5141

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

5142

+

5143

+ Backport from mainline

5144

+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

5145

+

5146

+ * configure: Regenerate.

5147

+

5148

+2013-12-29 Andreas Tobler <andreast@gcc.gnu.org>

5149

+

5150

+ Merge from trunk:

5151

+ * include/private/gcconfig.h: Add FreeBSD powerpc64 defines.

5152

+

5153

2013-10-16 Release Manager

5154

5155

* GCC 4.8.2 released.

5156

Index: boehm-gc/configure

5157

===================================================================

5158

--- a/src/boehm-gc/configure (.../tags/gcc_4_8_2_release)

5159

+++ b/src/boehm-gc/configure (.../branches/gcc-4_8-branch)

5160

@@ -6770,7 +6770,7 @@

5161

rm -rf conftest*

5162

;;

5163

5164

-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \

5165

+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \

5166

s390*-*linux*|s390*-*tpf*|sparc*-*linux*)

5167

# Find out which ABI we are using.

5168

echo 'int i;' > conftest.$ac_ext

5169

@@ -6795,7 +6795,10 @@

5170

;;

5171

esac

5172

;;

5173

- ppc64-*linux*|powerpc64-*linux*)

5174

+ powerpc64le-*linux*)

5175

+ LD="${LD-ld} -m elf32lppclinux"

5176

+ ;;

5177

+ powerpc64-*linux*)

5178

LD="${LD-ld} -m elf32ppclinux"

5179

;;

5180

s390x-*linux*)

5181

@@ -6814,7 +6817,10 @@

5182

x86_64-*linux*)

5183

LD="${LD-ld} -m elf_x86_64"

5184

;;

5185

- ppc*-*linux*|powerpc*-*linux*)

5186

+ powerpcle-*linux*)

5187

+ LD="${LD-ld} -m elf64lppc"

5188

+ ;;

5189

+ powerpc-*linux*)

5190

LD="${LD-ld} -m elf64ppc"

5191

;;

5192

s390*-*linux*|s390*-*tpf*)

5193

@@ -11312,7 +11318,7 @@

5194

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

5195

lt_status=$lt_dlunknown

5196

cat > conftest.$ac_ext <<_LT_EOF

5197

-#line 11315 "configure"

5198

+#line 11321 "configure"

5199

#include "confdefs.h"

5200

5201

#if HAVE_DLFCN_H

5202

@@ -11418,7 +11424,7 @@

5203

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

5204

lt_status=$lt_dlunknown

5205

cat > conftest.$ac_ext <<_LT_EOF

5206

-#line 11421 "configure"

5207

+#line 11427 "configure"

5208

#include "confdefs.h"

5209

5210

#if HAVE_DLFCN_H

5211

Index: ChangeLog

5212

===================================================================

5213

--- a/src/ChangeLog (.../tags/gcc_4_8_2_release)

5214

+++ b/src/ChangeLog (.../branches/gcc-4_8-branch)

5215

@@ -1,3 +1,21 @@

5216

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

5217

+

5218

+ Backport from mainline

5219

+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

5220

+

5221

+ * libtool.m4: Update to mainline version.

5222

+ * configure: Regenerate.

5223

+

5224

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

5225

+

5226

+ Backport from mainline r203071:

5227

+

5228

+ 2013-10-01 Joern Rennecke <joern.rennecke@embecosm.com>

5229

+

5230

+ Import from savannah.gnu.org:

5231

+ * config.guess: Update to 2013-06-10 version.

5232

+ * config.sub: Update to 2013-10-01 version.

5233

+

5234

2013-10-16 Release Manager

5235

5236

* GCC 4.8.2 released.

5237

Index: lto-plugin/configure

5238

===================================================================

5239

--- a/src/lto-plugin/configure (.../tags/gcc_4_8_2_release)

5240

+++ b/src/lto-plugin/configure (.../branches/gcc-4_8-branch)

5241

@@ -6044,7 +6044,7 @@

5242

rm -rf conftest*

5243

;;

5244

5245

-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \

5246

+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \

5247

s390*-*linux*|s390*-*tpf*|sparc*-*linux*)

5248

# Find out which ABI we are using.

5249

echo 'int i;' > conftest.$ac_ext

5250

@@ -6069,7 +6069,10 @@

5251

;;

5252

esac

5253

;;

5254

- ppc64-*linux*|powerpc64-*linux*)

5255

+ powerpc64le-*linux*)

5256

+ LD="${LD-ld} -m elf32lppclinux"

5257

+ ;;

5258

+ powerpc64-*linux*)

5259

LD="${LD-ld} -m elf32ppclinux"

5260

;;

5261

s390x-*linux*)

5262

@@ -6088,7 +6091,10 @@

5263

x86_64-*linux*)

5264

LD="${LD-ld} -m elf_x86_64"

5265

;;

5266

- ppc*-*linux*|powerpc*-*linux*)

5267

+ powerpcle-*linux*)

5268

+ LD="${LD-ld} -m elf64lppc"

5269

+ ;;

5270

+ powerpc-*linux*)

5271

LD="${LD-ld} -m elf64ppc"

5272

;;

5273

s390*-*linux*|s390*-*tpf*)

5274

@@ -10552,7 +10558,7 @@

5275

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

5276

lt_status=$lt_dlunknown

5277

cat > conftest.$ac_ext <<_LT_EOF

5278

-#line 10555 "configure"

5279

+#line 10561 "configure"

5280

#include "confdefs.h"

5281

5282

#if HAVE_DLFCN_H

5283

@@ -10658,7 +10664,7 @@

5284

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

5285

lt_status=$lt_dlunknown

5286

cat > conftest.$ac_ext <<_LT_EOF

5287

-#line 10661 "configure"

5288

+#line 10667 "configure"

5289

#include "confdefs.h"

5290

5291

#if HAVE_DLFCN_H

5292

Index: lto-plugin/ChangeLog

5293

===================================================================

5294

--- a/src/lto-plugin/ChangeLog (.../tags/gcc_4_8_2_release)

5295

+++ b/src/lto-plugin/ChangeLog (.../branches/gcc-4_8-branch)

5296

@@ -1,3 +1,10 @@

5297

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

5298

+

5299

+ Backport from mainline

5300

+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

5301

+

5302

+ * configure: Regenerate.

5303

+

5304

2013-10-16 Release Manager

5305

5306

* GCC 4.8.2 released.

5307

Index: contrib/ChangeLog

5308

===================================================================

5309

--- a/src/contrib/ChangeLog (.../tags/gcc_4_8_2_release)

5310

+++ b/src/contrib/ChangeLog (.../branches/gcc-4_8-branch)

5311

@@ -1,3 +1,7 @@

5312

+2013-10-21 Mike Stump <mikestump@comcast.net>

5313

+

5314

+ * gcc_update (configure): Update to handle svn 1.8.1.

5315

+

5316

2013-10-16 Release Manager

5317

5318

* GCC 4.8.2 released.

5319

Index: contrib/gcc_update

5320

===================================================================

5321

--- a/src/contrib/gcc_update (.../tags/gcc_4_8_2_release)

5322

+++ b/src/contrib/gcc_update (.../branches/gcc-4_8-branch)

5323

@@ -382,7 +382,7 @@

5324

fi

5325

5326

revision=`$GCC_SVN info | awk '/Revision:/ { print $2 }'`

5327

- branch=`$GCC_SVN info | sed -ne "/URL:/ {

5328

+ branch=`$GCC_SVN info | sed -ne "/^URL:/ {

5329

s,.*/trunk,trunk,

5330

s,.*/branches/,,

5331

s,.*/tags/,,

5332

Index: libatomic/configure

5333

===================================================================

5334

--- a/src/libatomic/configure (.../tags/gcc_4_8_2_release)

5335

+++ b/src/libatomic/configure (.../branches/gcc-4_8-branch)

5336

@@ -6505,7 +6505,7 @@

5337

rm -rf conftest*

5338

;;

5339

5340

-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \

5341

+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \

5342

s390*-*linux*|s390*-*tpf*|sparc*-*linux*)

5343

# Find out which ABI we are using.

5344

echo 'int i;' > conftest.$ac_ext

5345

@@ -6530,7 +6530,10 @@

5346

;;

5347

esac

5348

;;

5349

- ppc64-*linux*|powerpc64-*linux*)

5350

+ powerpc64le-*linux*)

5351

+ LD="${LD-ld} -m elf32lppclinux"

5352

+ ;;

5353

+ powerpc64-*linux*)

5354

LD="${LD-ld} -m elf32ppclinux"

5355

;;

5356

s390x-*linux*)

5357

@@ -6549,7 +6552,10 @@

5358

x86_64-*linux*)

5359

LD="${LD-ld} -m elf_x86_64"

5360

;;

5361

- ppc*-*linux*|powerpc*-*linux*)

5362

+ powerpcle-*linux*)

5363

+ LD="${LD-ld} -m elf64lppc"

5364

+ ;;

5365

+ powerpc-*linux*)

5366

LD="${LD-ld} -m elf64ppc"

5367

;;

5368

s390*-*linux*|s390*-*tpf*)

5369

@@ -11013,7 +11019,7 @@

5370

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

5371

lt_status=$lt_dlunknown

5372

cat > conftest.$ac_ext <<_LT_EOF

5373

-#line 11016 "configure"

5374

+#line 11022 "configure"

5375

#include "confdefs.h"

5376

5377

#if HAVE_DLFCN_H

5378

@@ -11119,7 +11125,7 @@

5379

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

5380

lt_status=$lt_dlunknown

5381

cat > conftest.$ac_ext <<_LT_EOF

5382

-#line 11122 "configure"

5383

+#line 11128 "configure"

5384

#include "confdefs.h"

5385

5386

#if HAVE_DLFCN_H

5387

Index: libatomic/cas_n.c

5388

===================================================================

5389

--- a/src/libatomic/cas_n.c (.../tags/gcc_4_8_2_release)

5390

+++ b/src/libatomic/cas_n.c (.../branches/gcc-4_8-branch)

5391

@@ -51,10 +51,9 @@

5392

#if !DONE && N <= WORDSIZE && defined(atomic_compare_exchange_w)

5393

bool

5394

SIZE(libat_compare_exchange) (UTYPE *mptr, UTYPE *eptr, UTYPE newval,

5395

- int smodel, int fmodel UNUSED)

5396

+ int smodel, int fmodel)

5397

{

5398

UWORD mask, shift, weval, woldval, wnewval, t, *wptr;

5399

- bool ret = false;

5400

5401

pre_barrier (smodel);

5402

5403

@@ -82,12 +81,13 @@

5404

}

5405

while (!atomic_compare_exchange_w (wptr, &woldval, t, true,

5406

__ATOMIC_RELAXED, __ATOMIC_RELAXED));

5407

- ret = true;

5408

+ post_barrier (smodel);

5409

+ return true;

5410

+

5411

failure:

5412

*eptr = woldval >> shift;

5413

-

5414

- post_barrier (smodel);

5415

- return ret;

5416

+ post_barrier (fmodel);

5417

+ return false;

5418

}

5419

5420

#define DONE 1

5421

@@ -102,18 +102,17 @@

5422

{

5423

UTYPE oldval;

5424

UWORD magic;

5425

- bool ret = false;

5426

+ bool ret;

5427

5428

pre_seq_barrier (smodel);

5429

magic = protect_start (mptr);

5430

5431

oldval = *mptr;

5432

- if (oldval == *eptr)

5433

- {

5434

- *mptr = newval;

5435

- ret = true;

5436

- }

5437

- *eptr = oldval;

5438

+ ret = (oldval == *eptr);

5439

+ if (ret)

5440

+ *mptr = newval;

5441

+ else

5442

+ *eptr = oldval;

5443

5444

protect_end (mptr, magic);

5445

post_seq_barrier (smodel);

5446

Index: libatomic/ChangeLog

5447

===================================================================

5448

--- a/src/libatomic/ChangeLog (.../tags/gcc_4_8_2_release)

5449

+++ b/src/libatomic/ChangeLog (.../branches/gcc-4_8-branch)

5450

@@ -1,3 +1,16 @@

5451

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

5452

+

5453

+ Backport from mainline

5454

+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

5455

+

5456

+ * configure: Regenerate.

5457

+

5458

+2014-02-20 Richard Henderson <rth@redhat.com>

5459

+

5460

+ PR c++/60272

5461

+ * cas_n.c (libat_compare_exchange): Conditionalize on failure

5462

+ the store back to EPTR.

5463

+

5464

2013-10-16 Release Manager

5465

5466

* GCC 4.8.2 released.

5467

Index: libbacktrace/configure

5468

===================================================================

5469

--- a/src/libbacktrace/configure (.../tags/gcc_4_8_2_release)

5470

+++ b/src/libbacktrace/configure (.../branches/gcc-4_8-branch)

5471

@@ -6842,7 +6842,7 @@

5472

rm -rf conftest*

5473

;;

5474

5475

-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \

5476

+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \

5477

s390*-*linux*|s390*-*tpf*|sparc*-*linux*)

5478

# Find out which ABI we are using.

5479

echo 'int i;' > conftest.$ac_ext

5480

@@ -6867,7 +6867,10 @@

5481

;;

5482

esac

5483

;;

5484

- ppc64-*linux*|powerpc64-*linux*)

5485

+ powerpc64le-*linux*)

5486

+ LD="${LD-ld} -m elf32lppclinux"

5487

+ ;;

5488

+ powerpc64-*linux*)

5489

LD="${LD-ld} -m elf32ppclinux"

5490

;;

5491

s390x-*linux*)

5492

@@ -6886,7 +6889,10 @@

5493

x86_64-*linux*)

5494

LD="${LD-ld} -m elf_x86_64"

5495

;;

5496

- ppc*-*linux*|powerpc*-*linux*)

5497

+ powerpcle-*linux*)

5498

+ LD="${LD-ld} -m elf64lppc"

5499

+ ;;

5500

+ powerpc-*linux*)

5501

LD="${LD-ld} -m elf64ppc"

5502

;;

5503

s390*-*linux*|s390*-*tpf*)

5504

@@ -11081,7 +11087,7 @@

5505

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

5506

lt_status=$lt_dlunknown

5507

cat > conftest.$ac_ext <<_LT_EOF

5508

-#line 11084 "configure"

5509

+#line 11090 "configure"

5510

#include "confdefs.h"

5511

5512

#if HAVE_DLFCN_H

5513

@@ -11187,7 +11193,7 @@

5514

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

5515

lt_status=$lt_dlunknown

5516

cat > conftest.$ac_ext <<_LT_EOF

5517

-#line 11190 "configure"

5518

+#line 11196 "configure"

5519

#include "confdefs.h"

5520

5521

#if HAVE_DLFCN_H

5522

@@ -11667,12 +11673,13 @@

5523

return 0;

5524

}

5525

_ACEOF

5526

-if ac_fn_c_try_compile "$LINENO"; then :

5527

+if ac_fn_c_try_link "$LINENO"; then :

5528

have_unwind_getipinfo=yes

5529

else

5530

have_unwind_getipinfo=no

5531

fi

5532

-rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext

5533

+rm -f core conftest.err conftest.$ac_objext \

5534

+ conftest$ac_exeext conftest.$ac_ext

5535

CFLAGS="$ac_save_CFLAGS"

5536

{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $have_unwind_getipinfo" >&5

5537

$as_echo "$have_unwind_getipinfo" >&6; }

5538

Index: libbacktrace/Makefile.in

5539

===================================================================

5540

--- a/src/libbacktrace/Makefile.in (.../tags/gcc_4_8_2_release)

5541

+++ b/src/libbacktrace/Makefile.in (.../branches/gcc-4_8-branch)

5542

@@ -16,7 +16,7 @@

5543

@SET_MAKE@

5544

5545

# Makefile.am -- Backtrace Makefile.

5546

5547

5548

5549

# Redistribution and use in source and binary forms, with or without

5550

# modification, are permitted provided that the following conditions are

5551

Index: libbacktrace/dwarf.c

5552

===================================================================

5553

--- a/src/libbacktrace/dwarf.c (.../tags/gcc_4_8_2_release)

5554

+++ b/src/libbacktrace/dwarf.c (.../branches/gcc-4_8-branch)

5555

@@ -2507,7 +2507,6 @@

5556

if (pfvec->count == 0)

5557

return;

5558

5559

- addrs = (struct function_addrs *) pfvec->vec.base;

5560

addrs_count = pfvec->count;

5561

5562

if (fvec == NULL)

5563

@@ -2514,12 +2513,17 @@

5564

{

5565

if (!backtrace_vector_release (state, &lvec.vec, error_callback, data))

5566

return;

5567

+ addrs = (struct function_addrs *) pfvec->vec.base;

5568

}

5569

else

5570

{

5571

/* Finish this list of addresses, but leave the remaining space in

5572

the vector available for the next function unit. */

5573

- backtrace_vector_finish (state, &fvec->vec);

5574

+ addrs = ((struct function_addrs *)

5575

+ backtrace_vector_finish (state, &fvec->vec,

5576

+ error_callback, data));

5577

+ if (addrs == NULL)

5578

+ return;

5579

fvec->count = 0;

5580

}

5581

5582

Index: libbacktrace/ChangeLog

5583

===================================================================

5584

--- a/src/libbacktrace/ChangeLog (.../tags/gcc_4_8_2_release)

5585

+++ b/src/libbacktrace/ChangeLog (.../branches/gcc-4_8-branch)

5586

@@ -1,3 +1,35 @@

5587

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

5588

+

5589

+ Backport from mainline

5590

+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

5591

+

5592

+ * configure: Regenerate.

5593

+

5594

+2014-02-07 Misty De Meo <misty@brew.sh>

5595

+

5596

+ PR target/58710

5597

+ * configure.ac: Use AC_LINK_IFELSE in check for

5598

+ _Unwind_GetIPInfo.

5599

+ * configure: Regenerate.

5600

+

5601

+2013-12-05 Ian Lance Taylor <iant@google.com>

5602

+

5603

+ * alloc.c (backtrace_vector_finish): Add error_callback and data

5604

+ parameters. Call backtrace_vector_release. Return address base.

5605

+ * mmap.c (backtrace_vector_finish): Add error_callback and data

5606

+ parameters. Return address base.

5607

+ * dwarf.c (read_function_info): Get new address base from

5608

+ backtrace_vector_finish.

5609

+ * internal.h (backtrace_vector_finish): Update declaration.

5610

+

5611

+2013-11-30 Ian Lance Taylor <iant@google.com>

5612

+

5613

+ Backport from mainline:

5614

+ 2013-10-17 Ian Lance Taylor <iant@google.com>

5615

+

5616

+ * elf.c (elf_add): Don't get the wrong offsets if a debug section

5617

+ is missing.

5618

+

5619

2013-10-16 Release Manager

5620

5621

* GCC 4.8.2 released.

5622

Index: libbacktrace/elf.c

5623

===================================================================

5624

--- a/src/libbacktrace/elf.c (.../tags/gcc_4_8_2_release)

5625

+++ b/src/libbacktrace/elf.c (.../branches/gcc-4_8-branch)

5626

@@ -725,6 +725,8 @@

5627

{

5628

off_t end;

5629

5630

+ if (sections[i].size == 0)

5631

+ continue;

5632

if (min_offset == 0 || sections[i].offset < min_offset)

5633

min_offset = sections[i].offset;

5634

end = sections[i].offset + sections[i].size;

5635

@@ -751,8 +753,13 @@

5636

descriptor = -1;

5637

5638

for (i = 0; i < (int) DEBUG_MAX; ++i)

5639

- sections[i].data = ((const unsigned char *) debug_view.data

5640

- + (sections[i].offset - min_offset));

5641

+ {

5642

+ if (sections[i].size == 0)

5643

+ sections[i].data = NULL;

5644

+ else

5645

+ sections[i].data = ((const unsigned char *) debug_view.data

5646

+ + (sections[i].offset - min_offset));

5647

+ }

5648

5649

if (!backtrace_dwarf_add (state, base_address,

5650

sections[DEBUG_INFO].data,

5651

Index: libbacktrace/internal.h

5652

===================================================================

5653

--- a/src/libbacktrace/internal.h (.../tags/gcc_4_8_2_release)

5654

+++ b/src/libbacktrace/internal.h (.../branches/gcc-4_8-branch)

5655

@@ -192,13 +192,17 @@

5656

struct backtrace_vector *vec);

5657

5658

/* Finish the current allocation on VEC. Prepare to start a new

5659

- allocation. The finished allocation will never be freed. */

5660

+ allocation. The finished allocation will never be freed. Returns

5661

+ a pointer to the base of the finished entries, or NULL on

5662

+ failure. */

5663

5664

-extern void backtrace_vector_finish (struct backtrace_state *state,

5665

- struct backtrace_vector *vec);

5666

+extern void* backtrace_vector_finish (struct backtrace_state *state,

5667

+ struct backtrace_vector *vec,

5668

+ backtrace_error_callback error_callback,

5669

+ void *data);

5670

5671

-/* Release any extra space allocated for VEC. Returns 1 on success, 0

5672

- on failure. */

5673

+/* Release any extra space allocated for VEC. This may change

5674

+ VEC->base. Returns 1 on success, 0 on failure. */

5675

5676

extern int backtrace_vector_release (struct backtrace_state *state,

5677

struct backtrace_vector *vec,

5678

Index: libbacktrace/configure.ac

5679

===================================================================

5680

--- a/src/libbacktrace/configure.ac (.../tags/gcc_4_8_2_release)

5681

+++ b/src/libbacktrace/configure.ac (.../branches/gcc-4_8-branch)

5682

@@ -144,7 +144,7 @@

5683

ac_save_CFFLAGS="$CFLAGS"

5684

CFLAGS="$CFLAGS -Werror-implicit-function-declaration"

5685

AC_MSG_CHECKING([for _Unwind_GetIPInfo])

5686

- AC_COMPILE_IFELSE(

5687

+ AC_LINK_IFELSE(

5688

[AC_LANG_PROGRAM(

5689

[#include "unwind.h"

5690

struct _Unwind_Context *context;

5691

Index: libbacktrace/alloc.c

5692

===================================================================

5693

--- a/src/libbacktrace/alloc.c (.../tags/gcc_4_8_2_release)

5694

+++ b/src/libbacktrace/alloc.c (.../branches/gcc-4_8-branch)

5695

@@ -113,12 +113,24 @@

5696

5697

/* Finish the current allocation on VEC. */

5698

5699

-void

5700

-backtrace_vector_finish (struct backtrace_state *state ATTRIBUTE_UNUSED,

5701

- struct backtrace_vector *vec)

5702

+void *

5703

+backtrace_vector_finish (struct backtrace_state *state,

5704

+ struct backtrace_vector *vec,

5705

+ backtrace_error_callback error_callback,

5706

+ void *data)

5707

{

5708

- vec->base = (char *) vec->base + vec->size;

5709

+ void *ret;

5710

+

5711

+ /* With this allocator we call realloc in backtrace_vector_grow,

5712

+ which means we can't easily reuse the memory here. So just

5713

+ release it. */

5714

+ if (!backtrace_vector_release (state, vec, error_callback, data))

5715

+ return NULL;

5716

+ ret = vec->base;

5717

+ vec->base = NULL;

5718

vec->size = 0;

5719

+ vec->alc = 0;

5720

+ return ret;

5721

}

5722

5723

/* Release any extra space allocated for VEC. */

5724

Index: libbacktrace/mmap.c

5725

===================================================================

5726

--- a/src/libbacktrace/mmap.c (.../tags/gcc_4_8_2_release)

5727

+++ b/src/libbacktrace/mmap.c (.../branches/gcc-4_8-branch)

5728

@@ -230,12 +230,19 @@

5729

5730

/* Finish the current allocation on VEC. */

5731

5732

-void

5733

-backtrace_vector_finish (struct backtrace_state *state ATTRIBUTE_UNUSED,

5734

- struct backtrace_vector *vec)

5735

+void *

5736

+backtrace_vector_finish (

5737

+ struct backtrace_state *state ATTRIBUTE_UNUSED,

5738

+ struct backtrace_vector *vec,

5739

+ backtrace_error_callback error_callback ATTRIBUTE_UNUSED,

5740

+ void *data ATTRIBUTE_UNUSED)

5741

{

5742

+ void *ret;

5743

+

5744

+ ret = vec->base;

5745

vec->base = (char *) vec->base + vec->size;

5746

vec->size = 0;

5747

+ return ret;

5748

}

5749

5750

/* Release any extra space allocated for VEC. */

5751

Index: libjava/libltdl/configure

5752

===================================================================

5753

--- a/src/libjava/libltdl/configure (.../tags/gcc_4_8_2_release)

5754

+++ b/src/libjava/libltdl/configure (.../branches/gcc-4_8-branch)

5755

@@ -4806,7 +4806,7 @@

5756

rm -rf conftest*

5757

;;

5758

5759

-x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*|s390*-*linux*|sparc*-*linux*)

5760

+x86_64-*linux*|powerpc*-*linux*|s390*-*linux*|sparc*-*linux*)

5761

# Find out which ABI we are using.

5762

echo 'int i;' > conftest.$ac_ext

5763

if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } >&5

5764

@@ -4820,7 +4820,10 @@

5765

x86_64-*linux*)

5766

LD="${LD-ld} -m elf_i386"

5767

;;

5768

- ppc64-*linux*|powerpc64-*linux*)

5769

+ powerpc64le-*linux*)

5770

+ LD="${LD-ld} -m elf32lppclinux"

5771

+ ;;

5772

+ powerpc64-*linux*)

5773

LD="${LD-ld} -m elf32ppclinux"

5774

;;

5775

s390x-*linux*)

5776

@@ -4836,7 +4839,10 @@

5777

x86_64-*linux*)

5778

LD="${LD-ld} -m elf_x86_64"

5779

;;

5780

- ppc*-*linux*|powerpc*-*linux*)

5781

+ powerpcle-*linux*)

5782

+ LD="${LD-ld} -m elf64lppc"

5783

+ ;;

5784

+ powerpc-*linux*)

5785

LD="${LD-ld} -m elf64ppc"

5786

;;

5787

s390*-*linux*)

5788

@@ -6456,11 +6462,11 @@

5789

-e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \

5790

-e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \

5791

-e 's:$: $lt_compiler_flag:'`

5792

- (eval echo "\"\$as_me:6459: $lt_compile\"" >&5)

5793

+ (eval echo "\"\$as_me:6465: $lt_compile\"" >&5)

5794

(eval "$lt_compile" 2>conftest.err)

5795

ac_status=$?

5796

cat conftest.err >&5

5797

- echo "$as_me:6463: \$? = $ac_status" >&5

5798

+ echo "$as_me:6469: \$? = $ac_status" >&5

5799

if (exit $ac_status) && test -s "$ac_outfile"; then

5800

# The compiler can only warn and ignore the option if not recognized

5801

# So say no if there are warnings other than the usual output.

5802

@@ -6718,11 +6724,11 @@

5803

-e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \

5804

-e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \

5805

-e 's:$: $lt_compiler_flag:'`

5806

- (eval echo "\"\$as_me:6721: $lt_compile\"" >&5)

5807

+ (eval echo "\"\$as_me:6727: $lt_compile\"" >&5)

5808

(eval "$lt_compile" 2>conftest.err)

5809

ac_status=$?

5810

cat conftest.err >&5

5811

- echo "$as_me:6725: \$? = $ac_status" >&5

5812

+ echo "$as_me:6731: \$? = $ac_status" >&5

5813

if (exit $ac_status) && test -s "$ac_outfile"; then

5814

# The compiler can only warn and ignore the option if not recognized

5815

# So say no if there are warnings other than the usual output.

5816

@@ -6780,11 +6786,11 @@

5817

-e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \

5818

-e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \

5819

-e 's:$: $lt_compiler_flag:'`

5820

- (eval echo "\"\$as_me:6783: $lt_compile\"" >&5)

5821

+ (eval echo "\"\$as_me:6789: $lt_compile\"" >&5)

5822

(eval "$lt_compile" 2>out/conftest.err)

5823

ac_status=$?

5824

cat out/conftest.err >&5

5825

- echo "$as_me:6787: \$? = $ac_status" >&5

5826

+ echo "$as_me:6793: \$? = $ac_status" >&5

5827

if (exit $ac_status) && test -s out/conftest2.$ac_objext

5828

then

5829

# The compiler can only warn and ignore the option if not recognized

5830

@@ -8099,7 +8105,7 @@

5831

libsuff=

5832

case "$host_cpu" in

5833

x86_64*|s390x*|powerpc64*)

5834

- echo '#line 8102 "configure"' > conftest.$ac_ext

5835

+ echo '#line 8108 "configure"' > conftest.$ac_ext

5836

if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } >&5

5837

(eval $ac_compile) 2>&5

5838

ac_status=$?

5839

@@ -8652,7 +8658,7 @@

5840

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

5841

lt_status=$lt_dlunknown

5842

cat > conftest.$ac_ext <<EOF

5843

-#line 8655 "configure"

5844

+#line 8661 "configure"

5845

#include "confdefs.h"

5846

5847

#if HAVE_DLFCN_H

5848

@@ -8750,7 +8756,7 @@

5849

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

5850

lt_status=$lt_dlunknown

5851

cat > conftest.$ac_ext <<EOF

5852

-#line 8753 "configure"

5853

+#line 8759 "configure"

5854

#include "confdefs.h"

5855

5856

#if HAVE_DLFCN_H

5857

@@ -10591,7 +10597,7 @@

5858

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

5859

lt_status=$lt_dlunknown

5860

cat > conftest.$ac_ext <<EOF

5861

-#line 10594 "configure"

5862

+#line 10600 "configure"

5863

#include "confdefs.h"

5864

5865

#if HAVE_DLFCN_H

5866

Index: libjava/libltdl/ChangeLog

5867

===================================================================

5868

--- a/src/libjava/libltdl/ChangeLog (.../tags/gcc_4_8_2_release)

5869

+++ b/src/libjava/libltdl/ChangeLog (.../branches/gcc-4_8-branch)

5870

@@ -1,3 +1,11 @@

5871

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

5872

+

5873

+ Backport from mainline

5874

+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

5875

+

5876

+ * acinclude.m4: Update to mainline version.

5877

+ * configure: Regenerate.

5878

+

5879

2013-10-16 Release Manager

5880

5881

* GCC 4.8.2 released.

5882

Index: libjava/libltdl/acinclude.m4

5883

===================================================================

5884

--- a/src/libjava/libltdl/acinclude.m4 (.../tags/gcc_4_8_2_release)

5885

+++ b/src/libjava/libltdl/acinclude.m4 (.../branches/gcc-4_8-branch)

5886

@@ -519,7 +519,7 @@

5887

rm -rf conftest*

5888

;;

5889

5890

-x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*|s390*-*linux*|sparc*-*linux*)

5891

+x86_64-*linux*|powerpc*-*linux*|s390*-*linux*|sparc*-*linux*)

5892

# Find out which ABI we are using.

5893

echo 'int i;' > conftest.$ac_ext

5894

if AC_TRY_EVAL(ac_compile); then

5895

@@ -529,7 +529,10 @@

5896

x86_64-*linux*)

5897

LD="${LD-ld} -m elf_i386"

5898

;;

5899

- ppc64-*linux*|powerpc64-*linux*)

5900

+ powerpc64le-*linux*)

5901

+ LD="${LD-ld} -m elf32lppclinux"

5902

+ ;;

5903

+ powerpc64-*linux*)

5904

LD="${LD-ld} -m elf32ppclinux"

5905

;;

5906

s390x-*linux*)

5907

@@ -545,7 +548,10 @@

5908

x86_64-*linux*)

5909

LD="${LD-ld} -m elf_x86_64"

5910

;;

5911

- ppc*-*linux*|powerpc*-*linux*)

5912

+ powerpcle-*linux*)

5913

+ LD="${LD-ld} -m elf64lppc"

5914

+ ;;

5915

+ powerpc-*linux*)

5916

LD="${LD-ld} -m elf64ppc"

5917

;;

5918

s390*-*linux*)

5919

Index: libjava/classpath/ChangeLog

5920

===================================================================

5921

--- a/src/libjava/classpath/ChangeLog (.../tags/gcc_4_8_2_release)

5922

+++ b/src/libjava/classpath/ChangeLog (.../branches/gcc-4_8-branch)

5923

@@ -1,3 +1,10 @@

5924

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

5925

+

5926

+ Backport from mainline

5927

+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

5928

+

5929

+ * configure: Regenerate.

5930

+

5931

2013-10-16 Release Manager

5932

5933

* GCC 4.8.2 released.

5934

Index: libjava/classpath/configure

5935

===================================================================

5936

--- a/src/libjava/classpath/configure (.../tags/gcc_4_8_2_release)

5937

+++ b/src/libjava/classpath/configure (.../branches/gcc-4_8-branch)

5938

@@ -7577,7 +7577,7 @@

5939

rm -rf conftest*

5940

;;

5941

5942

-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \

5943

+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \

5944

s390*-*linux*|s390*-*tpf*|sparc*-*linux*)

5945

# Find out which ABI we are using.

5946

echo 'int i;' > conftest.$ac_ext

5947

@@ -7602,7 +7602,10 @@

5948

;;

5949

esac

5950

;;

5951

- ppc64-*linux*|powerpc64-*linux*)

5952

+ powerpc64le-*linux*)

5953

+ LD="${LD-ld} -m elf32lppclinux"

5954

+ ;;

5955

+ powerpc64-*linux*)

5956

LD="${LD-ld} -m elf32ppclinux"

5957

;;

5958

s390x-*linux*)

5959

@@ -7621,7 +7624,10 @@

5960

x86_64-*linux*)

5961

LD="${LD-ld} -m elf_x86_64"

5962

;;

5963

- ppc*-*linux*|powerpc*-*linux*)

5964

+ powerpcle-*linux*)

5965

+ LD="${LD-ld} -m elf64lppc"

5966

+ ;;

5967

+ powerpc-*linux*)

5968

LD="${LD-ld} -m elf64ppc"

5969

;;

5970

s390*-*linux*|s390*-*tpf*)

5971

@@ -11820,7 +11826,7 @@

5972

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

5973

lt_status=$lt_dlunknown

5974

cat > conftest.$ac_ext <<_LT_EOF

5975

-#line 11823 "configure"

5976

+#line 11829 "configure"

5977

#include "confdefs.h"

5978

5979

#if HAVE_DLFCN_H

5980

@@ -11926,7 +11932,7 @@

5981

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

5982

lt_status=$lt_dlunknown

5983

cat > conftest.$ac_ext <<_LT_EOF

5984

-#line 11929 "configure"

5985

+#line 11935 "configure"

5986

#include "confdefs.h"

5987

5988

#if HAVE_DLFCN_H

5989

@@ -25300,7 +25306,7 @@

5990

JAVA_TEST=Object.java

5991

CLASS_TEST=Object.class

5992

cat << \EOF > $JAVA_TEST

5993

-/* #line 25303 "configure" */

5994

+/* #line 25309 "configure" */

5995

package java.lang;

5996

5997

public class Object

5998

@@ -25393,7 +25399,7 @@

5999

if uudecode$EXEEXT Test.uue; then

6000

ac_cv_prog_uudecode_base64=yes

6001

else

6002

- echo "configure: 25396: uudecode had trouble decoding base 64 file 'Test.uue'" >&5

6003

+ echo "configure: 25402: uudecode had trouble decoding base 64 file 'Test.uue'" >&5

6004

echo "configure: failed file was:" >&5

6005

cat Test.uue >&5

6006

ac_cv_prog_uudecode_base64=no

6007

@@ -25421,7 +25427,7 @@

6008

CLASS_TEST=Test.class

6009

TEST=Test

6010

cat << \EOF > $JAVA_TEST

6011

-/* [#]line 25424 "configure" */

6012

+/* [#]line 25430 "configure" */

6013

public class Test {

6014

public static void main (String args[]) {

6015

System.exit (0);

6016

@@ -25629,7 +25635,7 @@

6017

JAVA_TEST=Test.java

6018

CLASS_TEST=Test.class

6019

cat << \EOF > $JAVA_TEST

6020

- /* #line 25632 "configure" */

6021

+ /* #line 25638 "configure" */

6022

public class Test

6023

{

6024

public static void main(String args)

6025

Index: libjava/classpath/native/jni/gtk-peer/gnu_java_awt_peer_gtk_GdkFontPeer.c

6026

===================================================================

6027

--- a/src/libjava/classpath/native/jni/gtk-peer/gnu_java_awt_peer_gtk_GdkFontPeer.c (.../tags/gcc_4_8_2_release)

6028

+++ b/src/libjava/classpath/native/jni/gtk-peer/gnu_java_awt_peer_gtk_GdkFontPeer.c (.../branches/gcc-4_8-branch)

6029

@@ -39,10 +39,11 @@

6030

#include <pango/pango.h>

6031

#include <pango/pangoft2.h>

6032

#include <pango/pangofc-font.h>

6033

-#include <freetype/ftglyph.h>

6034

-#include <freetype/ftoutln.h>

6035

-#include <freetype/fttypes.h>

6036

-#include <freetype/tttables.h>

6037

+#include <ft2build.h>

6038

+#include FT_GLYPH_H

6039

+#include FT_OUTLINE_H

6040

+#include FT_TYPES_H

6041

+#include FT_TRUETYPE_TABLES_H

6042

#include "gdkfont.h"

6043

#include "gtkpeer.h"

6044

#include "gnu_java_awt_peer_gtk_GdkFontPeer.h"

6045

Index: libjava/classpath/native/jni/gtk-peer/gnu_java_awt_peer_gtk_FreetypeGlyphVector.c

6046

===================================================================

6047

--- a/src/libjava/classpath/native/jni/gtk-peer/gnu_java_awt_peer_gtk_FreetypeGlyphVector.c (.../tags/gcc_4_8_2_release)

6048

+++ b/src/libjava/classpath/native/jni/gtk-peer/gnu_java_awt_peer_gtk_FreetypeGlyphVector.c (.../branches/gcc-4_8-branch)

6049

@@ -42,8 +42,9 @@

6050

#include <pango/pango.h>

6051

#include <pango/pangoft2.h>

6052

#include <pango/pangofc-font.h>

6053

-#include <freetype/ftglyph.h>

6054

-#include <freetype/ftoutln.h>

6055

+#include <ft2build.h>

6056

+#include FT_GLYPH_H

6057

+#include FT_OUTLINE_H

6058

#include "jcl.h"

6059

#include "gdkfont.h"

6060

#include "gnu_java_awt_peer_gtk_FreetypeGlyphVector.h"

6061

Index: libjava/classpath/ChangeLog.gcj

6062

===================================================================

6063

--- a/src/libjava/classpath/ChangeLog.gcj (.../tags/gcc_4_8_2_release)

6064

+++ b/src/libjava/classpath/ChangeLog.gcj (.../branches/gcc-4_8-branch)

6065

@@ -1,3 +1,9 @@

6066

+2013-11-29 Matthias Klose <doko@ubuntu.com>

6067

+

6068

+ * native/jni/gtk-peer/gnu_java_awt_peer_gtk_FreetypeGlyphVector.c,

6069

+ native/jni/gtk-peer/gnu_java_awt_peer_gtk_GdkFontPeer.c:

6070

+ Fix freetype includes.

6071

+

6072

2013-03-22 Jakub Jelinek <jakub@redhat.com>

6073

6074

PR other/43620

6075

Index: libjava/classpath

6076

===================================================================

6077

--- a/src/libjava/classpath (.../tags/gcc_4_8_2_release)

6078

+++ b/src/libjava/classpath (.../branches/gcc-4_8-branch)

6079

6080

Property changes on: libjava/classpath

6081

___________________________________________________________________

6082

Modified: svn:mergeinfo

6083

Merged /trunk/libjava/classpath:r206395

6084

Index: libjava/ChangeLog

6085

===================================================================

6086

--- a/src/libjava/ChangeLog (.../tags/gcc_4_8_2_release)

6087

+++ b/src/libjava/ChangeLog (.../branches/gcc-4_8-branch)

6088

@@ -1,3 +1,23 @@

6089

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

6090

+

6091

+ Backport from mainline

6092

+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

6093

+

6094

+ * configure: Regenerate.

6095

+

6096

+2014-04-01 Dominique d'Humieres <dominiq@lps.ens.fr>

6097

+

6098

+ Backport from mainline

6099

+ 2014-02-20 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>

6100

+

6101

+ PR libgcj/55637

6102

+ * testsuite/libjava.lang/sourcelocation.xfail: New file.

6103

+

6104

+2014-03-11 Uros Bizjak <ubizjak@gmail.com>

6105

+

6106

+ * java/lang/natObject.cc (_Jv_MonitorEnter): Add missing parenthesis

6107

+ around comparison with (address | LOCKED) in JvAssert.

6108

+

6109

2013-10-16 Release Manager

6110

6111

* GCC 4.8.2 released.

6112

Index: libjava/testsuite/libjava.lang/sourcelocation.xfail

6113

===================================================================

6114

--- a/src/libjava/testsuite/libjava.lang/sourcelocation.xfail (.../tags/gcc_4_8_2_release)

6115

+++ b/src/libjava/testsuite/libjava.lang/sourcelocation.xfail (.../branches/gcc-4_8-branch)

6116

@@ -0,0 +1 @@

6117

+xfail-output

6118

Index: libjava/configure

6119

===================================================================

6120

--- a/src/libjava/configure (.../tags/gcc_4_8_2_release)

6121

+++ b/src/libjava/configure (.../branches/gcc-4_8-branch)

6122

@@ -8842,7 +8842,7 @@

6123

rm -rf conftest*

6124

;;

6125

6126

-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \

6127

+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \

6128

s390*-*linux*|s390*-*tpf*|sparc*-*linux*)

6129

# Find out which ABI we are using.

6130

echo 'int i;' > conftest.$ac_ext

6131

@@ -8867,7 +8867,10 @@

6132

;;

6133

esac

6134

;;

6135

- ppc64-*linux*|powerpc64-*linux*)

6136

+ powerpc64le-*linux*)

6137

+ LD="${LD-ld} -m elf32lppclinux"

6138

+ ;;

6139

+ powerpc64-*linux*)

6140

LD="${LD-ld} -m elf32ppclinux"

6141

;;

6142

s390x-*linux*)

6143

@@ -8886,7 +8889,10 @@

6144

x86_64-*linux*)

6145

LD="${LD-ld} -m elf_x86_64"

6146

;;

6147

- ppc*-*linux*|powerpc*-*linux*)

6148

+ powerpcle-*linux*)

6149

+ LD="${LD-ld} -m elf64lppc"

6150

+ ;;

6151

+ powerpc-*linux*)

6152

LD="${LD-ld} -m elf64ppc"

6153

;;

6154

s390*-*linux*|s390*-*tpf*)

6155

@@ -13382,7 +13388,7 @@

6156

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

6157

lt_status=$lt_dlunknown

6158

cat > conftest.$ac_ext <<_LT_EOF

6159

-#line 13385 "configure"

6160

+#line 13391 "configure"

6161

#include "confdefs.h"

6162

6163

#if HAVE_DLFCN_H

6164

@@ -13488,7 +13494,7 @@

6165

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

6166

lt_status=$lt_dlunknown

6167

cat > conftest.$ac_ext <<_LT_EOF

6168

-#line 13491 "configure"

6169

+#line 13497 "configure"

6170

#include "confdefs.h"

6171

6172

#if HAVE_DLFCN_H

6173

@@ -19483,7 +19489,7 @@

6174

enableval=$enable_sjlj_exceptions; :

6175

else

6176

cat > conftest.$ac_ext << EOF

6177

-#line 19486 "configure"

6178

+#line 19492 "configure"

6179

struct S { ~S(); };

6180

void bar();

6181

void foo()

6182

Index: libjava/java/lang/natObject.cc

6183

===================================================================

6184

--- a/src/libjava/java/lang/natObject.cc (.../tags/gcc_4_8_2_release)

6185

+++ b/src/libjava/java/lang/natObject.cc (.../branches/gcc-4_8-branch)

6186

@@ -929,7 +929,7 @@

6187

// only be held by other threads waiting for conversion, and

6188

// they, like us, drop it quickly without blocking.

6189

_Jv_MutexLock(&(hl->si.mutex));

6190

- JvAssert(he -> address == address | LOCKED );

6191

+ JvAssert(he -> address == (address | LOCKED));

6192

release_set(&(he -> address), (address | REQUEST_CONVERSION | HEAVY));

6193

// release lock on he

6194

LOG(REQ_CONV, (address | REQUEST_CONVERSION | HEAVY), self);

6195

@@ -961,7 +961,7 @@

6196

}

6197

obj_addr_t was_heavy = (address & HEAVY);

6198

if ((address & LOCKED) ||

6199

- !compare_and_swap(&(he -> address), address, (address | LOCKED )))

6200

+ !compare_and_swap(&(he -> address), address, address | LOCKED ))

6201

{

6202

wait_unlocked(he);

6203

goto retry;

6204

Index: gnattools/configure

6205

===================================================================

6206

--- a/src/gnattools/configure (.../tags/gcc_4_8_2_release)

6207

+++ b/src/gnattools/configure (.../branches/gcc-4_8-branch)

6208

@@ -2029,66 +2029,59 @@

6209

# Per-target case statement

6210

# -------------------------

6211

case "${target}" in

6212

- alpha*-dec-vx*) # Unlike all other Vxworks

6213

+ *-*-aix*)

6214

+ TOOLS_TARGET_PAIRS="\

6215

+ mlib-tgt-specific.adb<mlib-tgt-specific-aix.adb \

6216

+ indepsw.adb<indepsw-aix.adb"

6217

;;

6218

- m68k*-wrs-vx* \

6219

- | powerpc*-wrs-vxworks \

6220

- | sparc*-wrs-vx* \

6221

- | *86-wrs-vxworks \

6222

- | mips*-wrs-vx*)

6223

- TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-vxworks.adb"

6224

+ *-*-darwin*)

6225

+ TOOLS_TARGET_PAIRS="\

6226

+ mlib-tgt-specific.adb<mlib-tgt-specific-darwin.adb \

6227

+ indepsw.adb<indepsw-darwin.adb"

6228

;;

6229

- sparc-sun-solaris*)

6230

- TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-solaris.adb"

6231

+ *-*-freebsd*)

6232

+ TOOLS_TARGET_PAIRS="\

6233

+ mlib-tgt-specific.adb<mlib-tgt-specific-linux.adb \

6234

+ indepsw.adb<indepsw-gnu.adb"

6235

;;

6236

- *86-*-solaris2* | x86_64-*-solaris2.1[0-9]*)

6237

- TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-solaris.adb"

6238

- ;;

6239

- *86-*-linux* \

6240

- | powerpc*-*-linux* \

6241

- | *ia64-*-linux* \

6242

- | alpha*-*-linux* \

6243

- | sparc*-*-linux* \

6244

- | hppa*-*-linux* \

6245

- | *x86_64-*-linux*)

6246

+ *-*-linux*)

6247

TOOLS_TARGET_PAIRS="\

6248

mlib-tgt-specific.adb<mlib-tgt-specific-linux.adb \

6249

indepsw.adb<indepsw-gnu.adb"

6250

;;

6251

- s390*-*-linux*)

6252

- TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-linux.adb"

6253

+ *-*-lynxos*)

6254

+ TOOLS_TARGET_PAIRS="\

6255

+ mlib-tgt-specific.adb<mlib-tgt-specific-lynxos.adb \

6256

+ indepsw.adb<indepsw-gnu.adb"

6257

;;

6258

- *86-*-freebsd*)

6259

+ *-*-solaris*)

6260

+ TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-solaris.adb"

6261

+ ;;

6262

+ *-*-vxworks*)

6263

TOOLS_TARGET_PAIRS="\

6264

- mlib-tgt-specific.adb<mlib-tgt-specific-linux.adb \

6265

+ mlib-tgt-specific.adb<mlib-tgt-specific-vxworks.adb \

6266

indepsw.adb<indepsw-gnu.adb"

6267

;;

6268

- hppa*-hp-hpux10*) # Unlike hpux11

6269

+ hppa*-hp-hpux10*)

6270

;;

6271

hppa*-hp-hpux11*)

6272

TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-hpux.adb"

6273

;;

6274

- *-ibm-aix*)

6275

- TOOLS_TARGET_PAIRS="\

6276

- mlib-tgt-specific.adb<mlib-tgt-specific-aix.adb \

6277

- indepsw.adb<indepsw-aix.adb"

6278

+ ia64-hp-hpux11*)

6279

+ TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-ia64-hpux.adb"

6280

;;

6281

- alpha*-dec-vms* | alpha*-dec-openvms* | alpha*-dec-vms* \

6282

- | alpha*-hp-vms* | alpha*-hp-openvms* | alpha*-hp-vms*)

6283

+ alpha*-*-vms* | alpha*-*-openvms*)

6284

TOOLS_TARGET_PAIRS="\

6285

mlib-tgt-specific.adb<mlib-tgt-specific-vms-alpha.adb \

6286

symbols.adb<symbols-vms.adb \

6287

symbols-processing.adb<symbols-processing-vms-alpha.adb"

6288

-

6289

EXTRA_GNATTOOLS='../../gnatlbr$(exeext) ../../gnatsym$(exeext)'

6290

;;

6291

- ia64*-dec-vms* | ia64*-dec-openvms* | ia64*-dec-vms* \

6292

- | ia64*-hp-vms* | ia64*-hp-openvms* | ia64*-hp-vms*)

6293

+ ia64-*-vms* | ia64-*-openvms*)

6294

TOOLS_TARGET_PAIRS="\

6295

mlib-tgt-specific.adb<mlib-tgt-specific-vms-ia64.adb \

6296

symbols.adb<symbols-vms.adb \

6297

symbols-processing.adb<symbols-processing-vms-ia64.adb"

6298

-

6299

EXTRA_GNATTOOLS='../../gnatlbr$(exeext) ../../gnatsym$(exeext)'

6300

;;

6301

*-*-cygwin32* | *-*-mingw32* | *-*-pe)

6302

@@ -2097,14 +2090,6 @@

6303

indepsw.adb<indepsw-mingw.adb"

6304

EXTRA_GNATTOOLS='../../gnatdll$(exeext)'

6305

;;

6306

- *-*-darwin*)

6307

- TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-darwin.adb"

6308

- ;;

6309

- *-*-lynxos)

6310

- TOOLS_TARGET_PAIRS="\

6311

- mlib-tgt-specific.adb<mlib-tgt-specific-lynxos.adb \

6312

- indepsw.adb<indepsw-gnu.adb"

6313

- ;;

6314

esac

6315

6316

# From user or toplevel makefile.

6317

Index: gnattools/Makefile.in

6318

===================================================================

6319

--- a/src/gnattools/Makefile.in (.../tags/gcc_4_8_2_release)

6320

+++ b/src/gnattools/Makefile.in (.../branches/gcc-4_8-branch)

6321

@@ -24,6 +24,8 @@

6322

libdir = @libdir@

6323

build = @build@

6324

target = @target@

6325

+host = @host@

6326

+host_alias = @host_alias@

6327

prefix = @prefix@

6328

INSTALL = @INSTALL@

6329

INSTALL_DATA = @INSTALL_DATA@

6330

@@ -84,6 +86,7 @@

6331

TOOLS_FLAGS_TO_PASS_RE= \

6332

"CC=../../xgcc -B../../" \

6333

"CFLAGS=$(CFLAGS)" \

6334

+ "LDFLAGS=$(LDFLAGS)" \

6335

"ADAFLAGS=$(ADAFLAGS)" \

6336

"ADA_CFLAGS=$(ADA_CFLAGS)" \

6337

"INCLUDES=$(INCLUDES_FOR_SUBDIR)" \

6338

@@ -97,6 +100,22 @@

6339

"TOOLSCASE=cross"

6340

6341

# Variables for gnattools, cross

6342

+ifeq ($(build), $(host))

6343

+ GNATMAKE_FOR_HOST=gnatmake

6344

+ GNATLINK_FOR_HOST=gnatlink

6345

+ GNATBIND_FOR_HOST=gnatbind

6346

+ GNATLS_FOR_HOST=gnatls

6347

+else

6348

+ GNATMAKE_FOR_HOST=$(host_alias)-gnatmake

6349

+ GNATLINK_FOR_HOST=$(host_alias)-gnatlink

6350

+ GNATBIND_FOR_HOST=$(host_alias)-gnatbind

6351

+ GNATLS_FOR_HOST=$(host_alias)-gnatls

6352

+endif

6353

+

6354

+# Put the host RTS dir first in the PATH to hide the default runtime

6355

+# files that are among the sources

6356

+RTS_DIR:=$(strip $(subst \,/,$(shell $(GNATLS_FOR_HOST) -v | grep adalib )))

6357

+

6358

TOOLS_FLAGS_TO_PASS_CROSS= \

6359

"CC=$(CC)" \

6360

"CFLAGS=$(CFLAGS) $(WARN_CFLAGS)" \

6361

@@ -108,9 +127,9 @@

6362

"exeext=$(exeext)" \

6363

"fsrcdir=$(fsrcdir)" \

6364

"srcdir=$(fsrcdir)" \

6365

- "GNATMAKE=gnatmake" \

6366

- "GNATLINK=gnatlink" \

6367

- "GNATBIND=gnatbind" \

6368

+ "GNATMAKE=$(GNATMAKE_FOR_HOST)" \

6369

+ "GNATLINK=$(GNATLINK_FOR_HOST)" \

6370

+ "GNATBIND=$(GNATBIND_FOR_HOST)" \

6371

"TOOLSCASE=cross" \

6372

"LIBGNAT="

6373

6374

@@ -179,11 +198,6 @@

6375

$(MAKE) -C $(GCC_DIR)/ada/tools -f ../Makefile \

6376

$(TOOLS_FLAGS_TO_PASS_NATIVE) common-tools

6377

6378

-# For cross builds of gnattools,

6379

-# put the host RTS dir first in the PATH to hide the default runtime

6380

-# files that are among the sources

6381

-# FIXME: This should be done in configure.

6382

-RTS_DIR:=$(strip $(subst \,/,$(shell gnatls -v | grep adalib )))

6383

gnattools-cross: $(GCC_DIR)/stamp-tools

6384

# gnattools1-re

6385

$(MAKE) -C $(GCC_DIR)/ada/tools -f ../Makefile \

6386

Index: gnattools/configure.ac

6387

===================================================================

6388

--- a/src/gnattools/configure.ac (.../tags/gcc_4_8_2_release)

6389

+++ b/src/gnattools/configure.ac (.../branches/gcc-4_8-branch)

6390

@@ -69,66 +69,59 @@

6391

# Per-target case statement

6392

# -------------------------

6393

case "${target}" in

6394

- alpha*-dec-vx*) # Unlike all other Vxworks

6395

+ *-*-aix*)

6396

+ TOOLS_TARGET_PAIRS="\

6397

+ mlib-tgt-specific.adb<mlib-tgt-specific-aix.adb \

6398

+ indepsw.adb<indepsw-aix.adb"

6399

;;

6400

- m68k*-wrs-vx* \

6401

- | powerpc*-wrs-vxworks \

6402

- | sparc*-wrs-vx* \

6403

- | *86-wrs-vxworks \

6404

- | mips*-wrs-vx*)

6405

- TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-vxworks.adb"

6406

+ *-*-darwin*)

6407

+ TOOLS_TARGET_PAIRS="\

6408

+ mlib-tgt-specific.adb<mlib-tgt-specific-darwin.adb \

6409

+ indepsw.adb<indepsw-darwin.adb"

6410

;;

6411

- sparc-sun-solaris*)

6412

- TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-solaris.adb"

6413

+ *-*-freebsd*)

6414

+ TOOLS_TARGET_PAIRS="\

6415

+ mlib-tgt-specific.adb<mlib-tgt-specific-linux.adb \

6416

+ indepsw.adb<indepsw-gnu.adb"

6417

;;

6418

- *86-*-solaris2* | x86_64-*-solaris2.1[[0-9]]*)

6419

- TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-solaris.adb"

6420

- ;;

6421

- *86-*-linux* \

6422

- | powerpc*-*-linux* \

6423

- | *ia64-*-linux* \

6424

- | alpha*-*-linux* \

6425

- | sparc*-*-linux* \

6426

- | hppa*-*-linux* \

6427

- | *x86_64-*-linux*)

6428

+ *-*-linux*)

6429

TOOLS_TARGET_PAIRS="\

6430

mlib-tgt-specific.adb<mlib-tgt-specific-linux.adb \

6431

indepsw.adb<indepsw-gnu.adb"

6432

;;

6433

- s390*-*-linux*)

6434

- TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-linux.adb"

6435

+ *-*-lynxos*)

6436

+ TOOLS_TARGET_PAIRS="\

6437

+ mlib-tgt-specific.adb<mlib-tgt-specific-lynxos.adb \

6438

+ indepsw.adb<indepsw-gnu.adb"

6439

;;

6440

- *86-*-freebsd*)

6441

+ *-*-solaris*)

6442

+ TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-solaris.adb"

6443

+ ;;

6444

+ *-*-vxworks*)

6445

TOOLS_TARGET_PAIRS="\

6446

- mlib-tgt-specific.adb<mlib-tgt-specific-linux.adb \

6447

+ mlib-tgt-specific.adb<mlib-tgt-specific-vxworks.adb \

6448

indepsw.adb<indepsw-gnu.adb"

6449

;;

6450

- hppa*-hp-hpux10*) # Unlike hpux11

6451

+ hppa*-hp-hpux10*)

6452

;;

6453

hppa*-hp-hpux11*)

6454

TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-hpux.adb"

6455

;;

6456

- *-ibm-aix*)

6457

- TOOLS_TARGET_PAIRS="\

6458

- mlib-tgt-specific.adb<mlib-tgt-specific-aix.adb \

6459

- indepsw.adb<indepsw-aix.adb"

6460

+ ia64-hp-hpux11*)

6461

+ TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-ia64-hpux.adb"

6462

;;

6463

- alpha*-dec-vms* | alpha*-dec-openvms* | alpha*-dec-vms* \

6464

- | alpha*-hp-vms* | alpha*-hp-openvms* | alpha*-hp-vms*)

6465

+ alpha*-*-vms* | alpha*-*-openvms*)

6466

TOOLS_TARGET_PAIRS="\

6467

mlib-tgt-specific.adb<mlib-tgt-specific-vms-alpha.adb \

6468

symbols.adb<symbols-vms.adb \

6469

symbols-processing.adb<symbols-processing-vms-alpha.adb"

6470

-

6471

EXTRA_GNATTOOLS='../../gnatlbr$(exeext) ../../gnatsym$(exeext)'

6472

;;

6473

- ia64*-dec-vms* | ia64*-dec-openvms* | ia64*-dec-vms* \

6474

- | ia64*-hp-vms* | ia64*-hp-openvms* | ia64*-hp-vms*)

6475

+ ia64-*-vms* | ia64-*-openvms*)

6476

TOOLS_TARGET_PAIRS="\

6477

mlib-tgt-specific.adb<mlib-tgt-specific-vms-ia64.adb \

6478

symbols.adb<symbols-vms.adb \

6479

symbols-processing.adb<symbols-processing-vms-ia64.adb"

6480

-

6481

EXTRA_GNATTOOLS='../../gnatlbr$(exeext) ../../gnatsym$(exeext)'

6482

;;

6483

*-*-cygwin32* | *-*-mingw32* | *-*-pe)

6484

@@ -137,14 +130,6 @@

6485

indepsw.adb<indepsw-mingw.adb"

6486

EXTRA_GNATTOOLS='../../gnatdll$(exeext)'

6487

;;

6488

- *-*-darwin*)

6489

- TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-darwin.adb"

6490

- ;;

6491

- *-*-lynxos)

6492

- TOOLS_TARGET_PAIRS="\

6493

- mlib-tgt-specific.adb<mlib-tgt-specific-lynxos.adb \

6494

- indepsw.adb<indepsw-gnu.adb"

6495

- ;;

6496

esac

6497

6498

# From user or toplevel makefile.

6499

Index: gnattools/ChangeLog

6500

===================================================================

6501

--- a/src/gnattools/ChangeLog (.../tags/gcc_4_8_2_release)

6502

+++ b/src/gnattools/ChangeLog (.../branches/gcc-4_8-branch)

6503

@@ -1,3 +1,23 @@

6504

+2013-12-12 Eric Botcazou <ebotcazou@adacore.com>

6505

+ Iain Sandoe <iain@codesourcery.com>

6506

+

6507

+ PR ada/55946

6508

+ * Makefile.in (host): Define.

6509

+ (host_alias): Likewise.

6510

+ (TOOLS_FLAGS_TO_PASS_RE): Add LDFLAGS.

6511

+ (GNATMAKE_FOR_HOST): Define.

6512

+ (GNATLINK_FOR_HOST): Likewise.

6513

+ (GNATBIND_FOR_HOST): Likewise.

6514

+ (GNATLS_FOR_HOST): Likewise.

6515

+ (RTS_DIR): Move around and use GNATLS_FOR_HOST.

6516

+ (TOOLS_FLAGS_TO_PASS_CROSS): Use the other *_HOST variables.

6517

+

6518

+2013-12-04 Eric Botcazou <ebotcazou@adacore.com>

6519

+

6520

+ PR ada/59382

6521

+ * configure.ac (target parameterization): Rewrite.

6522

+ * configure: Regenerate.

6523

+

6524

2013-10-16 Release Manager

6525

6526

* GCC 4.8.2 released.

6527

Index: maintainer-scripts/ChangeLog

6528

===================================================================

6529

--- a/src/maintainer-scripts/ChangeLog (.../tags/gcc_4_8_2_release)

6530

+++ b/src/maintainer-scripts/ChangeLog (.../branches/gcc-4_8-branch)

6531

@@ -1,3 +1,9 @@

6532

+2014-02-01 Dmitry Gorbachev <d.g.gorbachev@gmail.com>

6533

+

6534

+ PR other/56653

6535

+ * gcc_release: Avoid printing empty line to generated MD5SUMS files.

6536

+ Bump copyright year.

6537

+

6538

2013-10-16 Release Manager

6539

6540

* GCC 4.8.2 released.

6541

Index: maintainer-scripts/gcc_release

6542

===================================================================

6543

--- a/src/maintainer-scripts/gcc_release (.../tags/gcc_4_8_2_release)

6544

+++ b/src/maintainer-scripts/gcc_release (.../branches/gcc-4_8-branch)

6545

@@ -9,7 +9,7 @@

6546

# Contents:

6547

# Script to create a GCC release.

6548

#

6549

6550

6551

#

6552

# This file is part of GCC.

6553

#

6554

@@ -213,7 +213,7 @@

6555

#

6556

# Suggested usage:

6557

# md5sum -c MD5SUMS | grep -v \"OK$\"

6558

-" > MD5SUMS

6559

+#" > MD5SUMS

6560

6561

find . -type f |

6562

sed -e 's:^\./::' -e '/MD5SUMS/d' |

6563

Index: libgcc/config.host

6564

===================================================================

6565

--- a/src/libgcc/config.host (.../tags/gcc_4_8_2_release)

6566

+++ b/src/libgcc/config.host (.../branches/gcc-4_8-branch)

6567

@@ -331,10 +331,10 @@

6568

;;

6569

arm*-*-uclinux*) # ARM ucLinux

6570

tmake_file="${tmake_file} t-fixedpoint-gnu-prefix"

6571

+ tmake_file="$tmake_file arm/t-arm arm/t-elf t-softfp-sfdf t-softfp-excl arm/t-softfp t-softfp"

6572

tmake_file="${tmake_file} arm/t-bpabi"

6573

tm_file="$tm_file arm/bpabi-lib.h"

6574

unwind_header=config/arm/unwind-arm.h

6575

- tmake_file="$tmake_file arm/t-arm arm/t-elf t-softfp-sfdf t-softfp-excl arm/t-softfp t-softfp"

6576

extra_parts="$extra_parts crti.o crtn.o"

6577

;;

6578

arm*-*-eabi* | arm*-*-symbianelf* | arm*-*-rtems*)

6579

@@ -718,6 +718,10 @@

6580

tmake_file="${tmake_file} microblaze/t-microblaze t-fdpbit"

6581

extra_parts="$extra_parts crtbeginS.o crtendS.o crtbeginT.o crti.o crtn.o"

6582

;;

6583

+microblaze*-*-rtems*)

6584

+ tmake_file="${tmake_file} microblaze/t-microblaze t-fdpbit"

6585

+ extra_parts="$extra_parts crtbeginS.o crtendS.o crtbeginT.o crti.o crtn.o"

6586

+ ;;

6587

mips*-*-netbsd*) # NetBSD/mips, either endian.

6588

;;

6589

mips*-*-linux*) # Linux MIPS, either endian.

6590

@@ -1081,7 +1085,7 @@

6591

md_unwind_header=tilepro/linux-unwind.h

6592

;;

6593

v850*-*-*)

6594

- tmake_file="v850/t-v850 t-fdpbit"

6595

+ tmake_file="${tmake_file} v850/t-v850 t-fdpbit"

6596

;;

6597

vax-*-linux*)

6598

tmake_file="$tmake_file vax/t-linux"

6599

@@ -1098,7 +1102,7 @@

6600

extra_parts="$extra_parts crti.o crtn.o"

6601

;;

6602

xtensa*-*-linux*)

6603

- tmake_file="$tmake_file xtensa/t-xtensa xtensa/t-linux"

6604

+ tmake_file="$tmake_file xtensa/t-xtensa xtensa/t-linux t-slibgcc-libgcc"

6605

md_unwind_header=xtensa/linux-unwind.h

6606

;;

6607

am33_2.0-*-linux*)

6608

Index: libgcc/ChangeLog

6609

===================================================================

6610

--- a/src/libgcc/ChangeLog (.../tags/gcc_4_8_2_release)

6611

+++ b/src/libgcc/ChangeLog (.../branches/gcc-4_8-branch)

6612

@@ -1,3 +1,206 @@

6613

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

6614

+

6615

+ Backport from mainline r204808:

6616

+

6617

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

6618

+ Alan Modra <amodra@gmail.com>

6619

+

6620

+ * config/rs6000/linux-unwind.h (TOC_SAVE_SLOT): Define.

6621

+ (frob_update_context): Use it.

6622

+

6623

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

6624

+ Alan Modra <amodra@gmail.com>

6625

+

6626

+ * config/rs6000/tramp.S [__powerpc64__ && _CALL_ELF == 2]:

6627

+ (trampoline_initial): Provide ELFv2 variant.

6628

+ (__trampoline_setup): Likewise.

6629

+

6630

+ * config/rs6000/linux-unwind.h (frob_update_context): Do not

6631

+ check for AIX indirect function call sequence if _CALL_ELF == 2.

6632

+

6633

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

6634

+ Alan Modra <amodra@gmail.com>

6635

+

6636

+ * config/rs6000/linux-unwind.h (get_regs): Do not support

6637

+ old kernel versions if _CALL_ELF == 2.

6638

+ (frob_update_context): Do not support PLT stub variants only

6639

+ generated by old linkers if _CALL_ELF == 2.

6640

+

6641

+ Backport from mainline r204800:

6642

+

6643

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

6644

+ Alan Modra <amodra@gmail.com>

6645

+

6646

+ * config/rs6000/linux-unwind.h (ppc_fallback_frame_state): Correct

6647

+ location of CR save area for 64-bit little-endian systems.

6648

+

6649

+2014-03-20 Joel Sherrill <joel.sherrill@oarcorp.com>

6650

+

6651

+ * config.host (v850*-*-*): Add to tmake_file instead of resetting it.

6652

+

6653

+2014-02-28 Joey Ye <joey.ye@arm.com>

6654

+

6655

+ Backport from mainline r208229

6656

+ 2014-02-28 Joey Ye <joey.ye@arm.com>

6657

+

6658

+ PR libgcc/60166

6659

+ * config/arm/sfp-machine.h (_FP_NANFRAC_H,

6660

+ _FP_NANFRAC_S, _FP_NANFRAC_D, _FP_NANFRAC_Q):

6661

+ Set to zero.

6662

+

6663

+2014-02-18 Kai Tietz <ktietz@redhat.com>

6664

+ Jonathan Schleifer <js@webkeks.org>

6665

+

6666

+ PR objc/56870

6667

+ * unwind-seh.c (_GCC_specific_handler): Pass proper

6668

+ value to unwind-handler.

6669

+

6670

+2014-01-25 Walter Lee <walt@tilera.com>

6671

+

6672

+ Backport from mainline

6673

+ 2014-01-25 Walter Lee <walt@tilera.com>

6674

+

6675

+ * config/tilepro/atomic.c (pre_atomic_barrier): Mark inline.

6676

+ (post_atomic_barrier): Ditto.

6677

+ (__fetch_and_do): New macro.

6678

+ (__atomic_fetch_and_do): Use __fetch_and_do.

6679

+ (__sync_fetch_and_do): New macro.

6680

+ (__sync_fetch_and_add_4): New function.

6681

+ (__sync_fetch_and_sub_4): New function.

6682

+ (__sync_fetch_and_or_4): New function.

6683

+ (__sync_fetch_and_and_4): New function.

6684

+ (__sync_fetch_and_xor_4): New function.

6685

+ (__sync_fetch_and_nand_4): New function.

6686

+ (__sync_fetch_and_add_8): New function.

6687

+ (__sync_fetch_and_sub_8): New function.

6688

+ (__sync_fetch_and_or_8): New function.

6689

+ (__sync_fetch_and_and_8): New function.

6690

+ (__sync_fetch_and_xor_8): New function.

6691

+ (__sync_fetch_and_nand_8): New function.

6692

+ (__do_and_fetch): New macro.

6693

+ (__atomic_do_and_fetch): Use __do_and_fetch.

6694

+ (__sync_do_and_fetch): New macro.

6695

+ (__sync_add_and_fetch_4): New function.

6696

+ (__sync_sub_and_fetch_4): New function.

6697

+ (__sync_or_and_fetch_4): New function.

6698

+ (__sync_and_and_fetch_4): New function.

6699

+ (__sync_xor_and_fetch_4): New function.

6700

+ (__sync_nand_and_fetch_4): New function.

6701

+ (__sync_add_and_fetch_8): New function.

6702

+ (__sync_sub_and_fetch_8): New function.

6703

+ (__sync_or_and_fetch_8): New function.

6704

+ (__sync_and_and_fetch_8): New function.

6705

+ (__sync_xor_and_fetch_8): New function.

6706

+ (__sync_nand_and_fetch_8): New function.

6707

+ (__sync_exchange_methods): New macro.

6708

+ (__sync_val_compare_and_swap_4): New function.

6709

+ (__sync_bool_compare_and_swap_4): New function.

6710

+ (__sync_lock_test_and_test_4): New function.

6711

+ (__sync_val_compare_and_swap_8): New function.

6712

+ (__sync_bool_compare_and_swap_8): New function.

6713

+ (__sync_lock_test_and_test_8): New function.

6714

+ (__subword_cmpxchg_body): New macro.

6715

+ (__atomic_compare_exchange_1): Use __subword_cmpxchg_body.

6716

+ (__atomic_compare_exchange_2): Ditto.

6717

+ (__sync_subword_cmpxchg): New macro.

6718

+ (__sync_val_compare_and_swap_1): New function.

6719

+ (__sync_bool_compare_and_swap_1): New function.

6720

+ (__sync_val_compare_and_swap_2): New function.

6721

+ (__sync_bool_compare_and_swap_2): New function.

6722

+ (__atomic_subword): Rename to ...

6723

+ (__subword): ... New name.

6724

+ (__atomic_subword_fetch): Use __subword.

6725

+ (__sync_subword_fetch): New macro.

6726

+ (__sync_fetch_and_add_1): New function.

6727

+ (__sync_fetch_and_sub_1): New function.

6728

+ (__sync_fetch_and_or_1): New function.

6729

+ (__sync_fetch_and_and_1): New function.

6730

+ (__sync_fetch_and_xor_1): New function.

6731

+ (__sync_fetch_and_nand_1): New function.

6732

+ (__sync_fetch_and_add_2): New function.

6733

+ (__sync_fetch_and_sub_2): New function.

6734

+ (__sync_fetch_and_or_2): New function.

6735

+ (__sync_fetch_and_and_2): New function.

6736

+ (__sync_fetch_and_xor_2): New function.

6737

+ (__sync_fetch_and_nand_2): New function.

6738

+ (__sync_add_and_fetch_1): New function.

6739

+ (__sync_sub_and_fetch_1): New function.

6740

+ (__sync_or_and_fetch_1): New function.

6741

+ (__sync_and_and_fetch_1): New function.

6742

+ (__sync_xor_and_fetch_1): New function.

6743

+ (__sync_nand_and_fetch_1): New function.

6744

+ (__sync_add_and_fetch_2): New function.

6745

+ (__sync_sub_and_fetch_2): New function.

6746

+ (__sync_or_and_fetch_2): New function.

6747

+ (__sync_and_and_fetch_2): New function.

6748

+ (__sync_xor_and_fetch_2): New function.

6749

+ (__sync_nand_and_fetch_2): New function.

6750

+ (__atomic_subword_lock): Use __subword.

6751

+ (__sync_subword_lock): New macro.

6752

+ (__sync_lock_test_and_set_1): New function.

6753

+ (__sync_lock_test_and_set_2): New function.

6754

+

6755

+2014-01-25 Walter Lee <walt@tilera.com>

6756

+

6757

+ Backport from mainline

6758

+ 2014-01-25 Walter Lee <walt@tilera.com>

6759

+

6760

+ * config/tilepro/atomic.c (BIT_OFFSET): Define.

6761

+ (__atomic_subword_cmpxchg): Use BIT_OFFSET.

6762

+ (__atomic_subword): Ditto.

6763

+

6764

+2014-01-25 Walter Lee <walt@tilera.com>

6765

+

6766

+ Backport from mainline

6767

+ 2014-01-25 Walter Lee <walt@tilera.com>

6768

+

6769

+ * config/tilepro/atomic.c (__atomic_do_and_fetch): Add

6770

+ a prefix op argument.

6771

+ (__atomic_nand_fetch_4): Add prefix op.

6772

+ (__atomic_nand_fetch_8): Ditto.

6773

+

6774

+2014-01-21 Baruch Siach <barch@tkos.co.il>

6775

+

6776

+ * config.host (tmake_file): add t-slibgcc-libgcc for xtensa*-*-linux*.

6777

+

6778

+2014-01-03 Joseph Myers <joseph@codesourcery.com>

6779

+

6780

+ * config/rs6000/ibm-ldouble.c (__gcc_qdiv): Scale up arguments in

6781

+ case of small numerator and finite nonzero result.

6782

+

6783

+2013-12-12 Zhenqiang Chen <zhenqiang.chen@arm.com>

6784

+

6785

+ Backport from trunk r205917.

6786

+ 2013-12-12 Zhenqiang Chen <zhenqiang.chen@arm.com>

6787

+ * config.host (arm*-*-uclinux*): Move t-arm before t-bpabi.

6788

+

6789

+2013-12-10 Uros Bizjak <ubizjak@gmail.com>

6790

+

6791

+ * config/i386/sfp-exceptions.c (__sfp_handle_exceptions): Emit SSE

6792

+ instructions when __SSE_MATH__ is defined.

6793

+

6794

+2013-12-06 Ralf Corsépius <ralf.corsepius@rtems.org>

6795

+

6796

+ * config.host (microblaze-*-rtems*): New.

6797

+

6798

+2013-11-10 Kai Tietz <ktietz@redhat.com>

6799

+

6800

+ Back-merged from trunk

6801

+ * config/i386/cygming-crtbegin.c (__gcc_register_frame):

6802

+ Increment load-count on use of LIBGCC_SONAME DLL.

6803

+ (hmod_libgcc): New static variable to hold handle of

6804

+ LIBGCC_SONAME DLL.

6805

+ (__gcc_deregister_frame): Decrement load-count of

6806

+ LIBGCC_SONAME DLL.

6807

+

6808

+2013-11-07 Uros Bizjak <ubizjak@gmail.com>

6809

+

6810

+ * config/i386/sfp-exceptions.c (__sfp_handle_exceptions): Handle

6811

+ FP_EX_DENORM. Store result to volatile location after SSE division

6812

+ to close interrupt window. Remove unneeded fwait after x87

6813

+ division since interrupt window will be closed by emitted fstp.

6814

+ Rewrite FP_EX_INEXACT handling.

6815

+

6816

2013-10-16 Release Manager

6817

6818

* GCC 4.8.2 released.

6819

@@ -151,7 +354,7 @@

6820

* config/mips/crtn.S (fini, init): New labels.

6821

6822

2012-02-19 Edgar E. Iglesias <edgar.iglesias@gmail.com>

6823

- * config/microblaze/modsi3.S (modsi3): Fix case with 0x80000000

6824

+ * config/microblaze/modsi3.S (modsi3): Fix case with 0x80000000

6825

as dividend.

6826

6827

2013-02-16 Alan Modra <amodra@gmail.com>

6828

Index: libgcc/config/i386/sfp-exceptions.c

6829

===================================================================

6830

--- a/src/libgcc/config/i386/sfp-exceptions.c (.../tags/gcc_4_8_2_release)

6831

+++ b/src/libgcc/config/i386/sfp-exceptions.c (.../branches/gcc-4_8-branch)

6832

@@ -47,21 +47,33 @@

6833

if (_fex & FP_EX_INVALID)

6834

{

6835

float f = 0.0f;

6836

-#ifdef __x86_64__

6837

+#ifdef __SSE_MATH__

6838

+ volatile float r __attribute__ ((unused));

6839

asm volatile ("%vdivss\t{%0, %d0|%d0, %0}" : "+x" (f));

6840

+ r = f; /* Needed to trigger exception. */

6841

#else

6842

asm volatile ("fdiv\t{%y0, %0|%0, %y0}" : "+t" (f));

6843

- asm volatile ("fwait");

6844

+ /* No need for fwait, exception is triggered by emitted fstp. */

6845

#endif

6846

}

6847

+ if (_fex & FP_EX_DENORM)

6848

+ {

6849

+ struct fenv temp;

6850

+ asm volatile ("fnstenv\t%0" : "=m" (temp));

6851

+ temp.__status_word |= FP_EX_DENORM;

6852

+ asm volatile ("fldenv\t%0" : : "m" (temp));

6853

+ asm volatile ("fwait");

6854

+ }

6855

if (_fex & FP_EX_DIVZERO)

6856

{

6857

float f = 1.0f, g = 0.0f;

6858

-#ifdef __x86_64__

6859

+#ifdef __SSE_MATH__

6860

+ volatile float r __attribute__ ((unused));

6861

asm volatile ("%vdivss\t{%1, %d0|%d0, %1}" : "+x" (f) : "xm" (g));

6862

+ r = f; /* Needed to trigger exception. */

6863

#else

6864

asm volatile ("fdivs\t%1" : "+t" (f) : "m" (g));

6865

- asm volatile ("fwait");

6866

+ /* No need for fwait, exception is triggered by emitted fstp. */

6867

#endif

6868

}

6869

if (_fex & FP_EX_OVERFLOW)

6870

@@ -82,11 +94,15 @@

6871

}

6872

if (_fex & FP_EX_INEXACT)

6873

{

6874

- struct fenv temp;

6875

- asm volatile ("fnstenv\t%0" : "=m" (temp));

6876

- temp.__status_word |= FP_EX_INEXACT;

6877

- asm volatile ("fldenv\t%0" : : "m" (temp));

6878

- asm volatile ("fwait");

6879

+ float f = 1.0f, g = 3.0f;

6880

+#ifdef __SSE_MATH__

6881

+ volatile float r __attribute__ ((unused));

6882

+ asm volatile ("%vdivss\t{%1, %d0|%d0, %1}" : "+x" (f) : "xm" (g));

6883

+ r = f; /* Needed to trigger exception. */

6884

+#else

6885

+ asm volatile ("fdivs\t%1" : "+t" (f) : "m" (g));

6886

+ /* No need for fwait, exception is triggered by emitted fstp. */

6887

+#endif

6888

}

6889

};

6890

#endif

6891

Index: libgcc/config/i386/cygming-crtbegin.c

6892

===================================================================

6893

--- a/src/libgcc/config/i386/cygming-crtbegin.c (.../tags/gcc_4_8_2_release)

6894

+++ b/src/libgcc/config/i386/cygming-crtbegin.c (.../branches/gcc-4_8-branch)

6895

@@ -69,6 +69,9 @@

6896

= { };

6897

6898

static struct object obj;

6899

+

6900

+/* Handle of libgcc's DLL reference. */

6901

+HANDLE hmod_libgcc;

6902

#endif

6903

6904

#if TARGET_USE_JCR_SECTION

6905

@@ -93,9 +96,14 @@

6906

6907

void (*register_frame_fn) (const void *, struct object *);

6908

HANDLE h = GetModuleHandle (LIBGCC_SONAME);

6909

+

6910

if (h)

6911

- register_frame_fn = (void (*) (const void *, struct object *))

6912

- GetProcAddress (h, "__register_frame_info");

6913

+ {

6914

+ /* Increasing the load-count of LIBGCC_SONAME DLL. */

6915

+ hmod_libgcc = LoadLibrary (LIBGCC_SONAME);

6916

+ register_frame_fn = (void (*) (const void *, struct object *))

6917

+ GetProcAddress (h, "__register_frame_info");

6918

+ }

6919

else

6920

register_frame_fn = __register_frame_info;

6921

if (register_frame_fn)

6922

@@ -132,5 +140,7 @@

6923

deregister_frame_fn = __deregister_frame_info;

6924

if (deregister_frame_fn)

6925

deregister_frame_fn (__EH_FRAME_BEGIN__);

6926

+ if (hmod_libgcc)

6927

+ FreeLibrary (hmod_libgcc);

6928

#endif

6929

}

6930

Index: libgcc/config/rs6000/tramp.S

6931

===================================================================

6932

--- a/src/libgcc/config/rs6000/tramp.S (.../tags/gcc_4_8_2_release)

6933

+++ b/src/libgcc/config/rs6000/tramp.S (.../branches/gcc-4_8-branch)

6934

@@ -116,4 +116,70 @@

6935

6936

#endif

6937

6938

+#elif _CALL_ELF == 2

6939

+ .type trampoline_initial,@object

6940

+ .align 3

6941

+trampoline_initial:

6942

+ ld r11,.Lchain(r12)

6943

+ ld r12,.Lfunc(r12)

6944

+ mtctr r12

6945

+ bctr

6946

+.Lfunc = .-trampoline_initial

6947

+ .quad 0 /* will be replaced with function address */

6948

+.Lchain = .-trampoline_initial

6949

+ .quad 0 /* will be replaced with static chain */

6950

+

6951

+trampoline_size = .-trampoline_initial

6952

+ .size trampoline_initial,trampoline_size

6953

+

6954

+

6955

+/* R3 = stack address to store trampoline */

6956

+/* R4 = length of trampoline area */

6957

+/* R5 = function address */

6958

+/* R6 = static chain */

6959

+

6960

+ .pushsection ".toc","aw"

6961

+.LC0:

6962

+ .quad trampoline_initial-8

6963

+ .popsection

6964

+

6965

+FUNC_START(__trampoline_setup)

6966

+ addis 7,2,.LC0@toc@ha

6967

+ ld 7,.LC0@toc@l(7) /* trampoline address -8 */

6968

+

6969

+ li r8,trampoline_size /* verify that the trampoline is big enough */

6970

+ cmpw cr1,r8,r4

6971

+ srwi r4,r4,3 /* # doublewords to move */

6972

+ addi r9,r3,-8 /* adjust pointer for stdu */

6973

+ mtctr r4

6974

+ blt cr1,.Labort

6975

+

6976

+ /* Copy the instructions to the stack */

6977

+.Lmove:

6978

+ ldu r10,8(r7)

6979

+ stdu r10,8(r9)

6980

+ bdnz .Lmove

6981

+

6982

+ /* Store correct function and static chain */

6983

+ std r5,.Lfunc(r3)

6984

+ std r6,.Lchain(r3)

6985

+

6986

+ /* Now flush both caches */

6987

+ mtctr r4

6988

+.Lcache:

6989

+ icbi 0,r3

6990

+ dcbf 0,r3

6991

+ addi r3,r3,8

6992

+ bdnz .Lcache

6993

+

6994

+ /* Finally synchronize things & return */

6995

+ sync

6996

+ isync

6997

+ blr

6998

+

6999

+.Labort:

7000

+ bl JUMP_TARGET(abort)

7001

+ nop

7002

+FUNC_END(__trampoline_setup)

7003

+

7004

#endif

7005

Index: libgcc/config/rs6000/linux-unwind.h

7006

===================================================================

7007

--- a/src/libgcc/config/rs6000/linux-unwind.h (.../tags/gcc_4_8_2_release)

7008

+++ b/src/libgcc/config/rs6000/linux-unwind.h (.../branches/gcc-4_8-branch)

7009

@@ -24,9 +24,19 @@

7010

7011

#define R_LR 65

7012

#define R_CR2 70

7013

+#define R_CR3 71

7014

+#define R_CR4 72

7015

#define R_VR0 77

7016

#define R_VRSAVE 109

7017

7018

+#ifdef __powerpc64__

7019

+#if _CALL_ELF == 2

7020

+#define TOC_SAVE_SLOT 24

7021

+#else

7022

+#define TOC_SAVE_SLOT 40

7023

+#endif

7024

+#endif

7025

+

7026

struct gcc_vregs

7027

{

7028

__attribute__ ((vector_size (16))) int vr[32];

7029

@@ -107,6 +117,8 @@

7030

}

7031

else if (pc[1] == 0x380000AC)

7032

{

7033

+#if _CALL_ELF != 2

7034

+ /* These old kernel versions never supported ELFv2. */

7035

/* This works for 2.4 kernels, but not for 2.6 kernels with vdso

7036

because pc isn't pointing into the stack. Can be removed when

7037

no one is running 2.4.19 or 2.4.20, the first two ppc64

7038

@@ -121,6 +133,7 @@

7039

if ((long) frame24->puc != -21 * 8)

7040

return frame24->puc->regs;

7041

else

7042

+#endif

7043

{

7044

/* This works for 2.4.21 and later kernels. */

7045

struct rt_sigframe {

7046

@@ -185,6 +198,7 @@

7047

{

7048

struct gcc_regs *regs = get_regs (context);

7049

struct gcc_vregs *vregs;

7050

+ long cr_offset;

7051

long new_cfa;

7052

int i;

7053

7054

@@ -206,11 +220,21 @@

7055

fs->regs.reg[i].loc.offset = (long) &regs->gpr[i] - new_cfa;

7056

}

7057

7058

+ /* The CR is saved in the low 32 bits of regs->ccr. */

7059

+ cr_offset = (long) &regs->ccr - new_cfa;

7060

+#ifndef __LITTLE_ENDIAN__

7061

+ cr_offset += sizeof (long) - 4;

7062

+#endif

7063

+ /* In the ELFv1 ABI, CR2 stands in for the whole CR. */

7064

fs->regs.reg[R_CR2].how = REG_SAVED_OFFSET;

7065

- /* CR? regs are always 32-bit and PPC is big-endian, so in 64-bit

7066

- libgcc loc.offset needs to point to the low 32 bits of regs->ccr. */

7067

- fs->regs.reg[R_CR2].loc.offset = (long) &regs->ccr - new_cfa

7068

- + sizeof (long) - 4;

7069

+ fs->regs.reg[R_CR2].loc.offset = cr_offset;

7070

+#if _CALL_ELF == 2

7071

+ /* In the ELFv2 ABI, every CR field has a separate CFI entry. */

7072

+ fs->regs.reg[R_CR3].how = REG_SAVED_OFFSET;

7073

+ fs->regs.reg[R_CR3].loc.offset = cr_offset;

7074

+ fs->regs.reg[R_CR4].how = REG_SAVED_OFFSET;

7075

+ fs->regs.reg[R_CR4].loc.offset = cr_offset;

7076

+#endif

7077

7078

fs->regs.reg[R_LR].how = REG_SAVED_OFFSET;

7079

fs->regs.reg[R_LR].loc.offset = (long) &regs->link - new_cfa;

7080

@@ -294,9 +318,13 @@

7081

figure out if it was saved. The big problem here is that the

7082

code that does the save/restore is generated by the linker, so

7083

we have no good way to determine at compile time what to do. */

7084

- if (pc[0] == 0xF8410028

7085

+ if (pc[0] == 0xF8410000 + TOC_SAVE_SLOT

7086

+#if _CALL_ELF != 2

7087

+ /* The ELFv2 linker never generates the old PLT stub form. */

7088

|| ((pc[0] & 0xFFFF0000) == 0x3D820000

7089

- && pc[1] == 0xF8410028))

7090

+ && pc[1] == 0xF8410000 + TOC_SAVE_SLOT)

7091

+#endif

7092

+ )

7093

{

7094

/* We are in a plt call stub or r2 adjusting long branch stub,

7095

before r2 has been saved. Keep REG_UNSAVED. */

7096

@@ -305,10 +333,12 @@

7097

{

7098

unsigned int *insn

7099

= (unsigned int *) _Unwind_GetGR (context, R_LR);

7100

- if (insn && *insn == 0xE8410028)

7101

- _Unwind_SetGRPtr (context, 2, context->cfa + 40);

7102

+ if (insn && *insn == 0xE8410000 + TOC_SAVE_SLOT)

7103

+ _Unwind_SetGRPtr (context, 2, context->cfa + TOC_SAVE_SLOT);

7104

+#if _CALL_ELF != 2

7105

+ /* ELFv2 does not use this function pointer call sequence. */

7106

else if (pc[0] == 0x4E800421

7107

- && pc[1] == 0xE8410028)

7108

+ && pc[1] == 0xE8410000 + TOC_SAVE_SLOT)

7109

{

7110

/* We are at the bctrl instruction in a call via function

7111

pointer. gcc always emits the load of the new R2 just

7112

@@ -315,8 +345,9 @@

7113

before the bctrl so this is the first and only place

7114

we need to use the stored R2. */

7115

_Unwind_Word sp = _Unwind_GetGR (context, 1);

7116

- _Unwind_SetGRPtr (context, 2, (void *)(sp + 40));

7117

+ _Unwind_SetGRPtr (context, 2, (void *)(sp + TOC_SAVE_SLOT));

7118

}

7119

+#endif

7120

}

7121

}

7122

#endif

7123

Index: libgcc/config/rs6000/ibm-ldouble.c

7124

===================================================================

7125

--- a/src/libgcc/config/rs6000/ibm-ldouble.c (.../tags/gcc_4_8_2_release)

7126

+++ b/src/libgcc/config/rs6000/ibm-ldouble.c (.../branches/gcc-4_8-branch)

7127

@@ -188,7 +188,16 @@

7128

|| nonfinite (t))

7129

return t;

7130

7131

- /* Finite nonzero result requires corrections to the highest order term. */

7132

+ /* Finite nonzero result requires corrections to the highest order

7133

+ term. These corrections require the low part of c * t to be

7134

+ exactly represented in double. */

7135

+ if (fabs (a) <= 0x1p-969)

7136

+ {

7137

+ a *= 0x1p106;

7138

+ b *= 0x1p106;

7139

+ c *= 0x1p106;

7140

+ d *= 0x1p106;

7141

+ }

7142

7143

s = c * t; /* (s,sigma) = c*t exactly. */

7144

w = -(-b + d * t); /* Written to get fnmsub for speed, but not

7145

Index: libgcc/config/tilepro/atomic.c

7146

===================================================================

7147

--- a/src/libgcc/config/tilepro/atomic.c (.../tags/gcc_4_8_2_release)

7148

+++ b/src/libgcc/config/tilepro/atomic.c (.../branches/gcc-4_8-branch)

7149

@@ -28,7 +28,7 @@

7150

/* This code should be inlined by the compiler, but for now support

7151

it as out-of-line methods in libgcc. */

7152

7153

-static void

7154

+static inline void

7155

pre_atomic_barrier (int model)

7156

{

7157

switch ((enum memmodel) model)

7158

@@ -44,7 +44,7 @@

7159

return;

7160

}

7161

7162

-static void

7163

+static inline void

7164

post_atomic_barrier (int model)

7165

{

7166

switch ((enum memmodel) model)

7167

@@ -62,16 +62,21 @@

7168

7169

#define __unused __attribute__((unused))

7170

7171

-#define __atomic_fetch_and_do(type, size, opname) \

7172

-type \

7173

-__atomic_fetch_##opname##_##size(type* p, type i, int model) \

7174

+#define __fetch_and_do(proto, type, size, opname, top, bottom) \

7175

+proto \

7176

{ \

7177

- pre_atomic_barrier(model); \

7178

+ top; \

7179

type rv = arch_atomic_##opname(p, i); \

7180

- post_atomic_barrier(model); \

7181

+ bottom; \

7182

return rv; \

7183

}

7184

7185

+#define __atomic_fetch_and_do(type, size, opname) \

7186

+ __fetch_and_do(type __atomic_fetch_##opname##_##size(type* p, type i, int model), \

7187

+ type, size, opname, \

7188

+ pre_atomic_barrier(model), \

7189

+ post_atomic_barrier(model)) \

7190

+

7191

__atomic_fetch_and_do (int, 4, add)

7192

__atomic_fetch_and_do (int, 4, sub)

7193

__atomic_fetch_and_do (int, 4, or)

7194

@@ -84,27 +89,73 @@

7195

__atomic_fetch_and_do (long long, 8, and)

7196

__atomic_fetch_and_do (long long, 8, xor)

7197

__atomic_fetch_and_do (long long, 8, nand)

7198

-#define __atomic_do_and_fetch(type, size, opname, op) \

7199

-type \

7200

-__atomic_##opname##_fetch_##size(type* p, type i, int model) \

7201

-{ \

7202

- pre_atomic_barrier(model); \

7203

- type rv = arch_atomic_##opname(p, i) op i; \

7204

- post_atomic_barrier(model); \

7205

- return rv; \

7206

+

7207

+#define __sync_fetch_and_do(type, size, opname) \

7208

+ __fetch_and_do(type __sync_fetch_and_##opname##_##size(type* p, type i), \

7209

+ type, size, opname, \

7210

+ arch_atomic_write_barrier(), \

7211

+ arch_atomic_read_barrier())

7212

+

7213

+__sync_fetch_and_do (int, 4, add)

7214

+__sync_fetch_and_do (int, 4, sub)

7215

+__sync_fetch_and_do (int, 4, or)

7216

+__sync_fetch_and_do (int, 4, and)

7217

+__sync_fetch_and_do (int, 4, xor)

7218

+__sync_fetch_and_do (int, 4, nand)

7219

+__sync_fetch_and_do (long long, 8, add)

7220

+__sync_fetch_and_do (long long, 8, sub)

7221

+__sync_fetch_and_do (long long, 8, or)

7222

+__sync_fetch_and_do (long long, 8, and)

7223

+__sync_fetch_and_do (long long, 8, xor)

7224

+__sync_fetch_and_do (long long, 8, nand)

7225

+

7226

+#define __do_and_fetch(proto, type, size, opname, op, op2, top, bottom) \

7227

+proto \

7228

+{ \

7229

+ top; \

7230

+ type rv = op2 (arch_atomic_##opname(p, i) op i); \

7231

+ bottom; \

7232

+ return rv; \

7233

}

7234

-__atomic_do_and_fetch (int, 4, add, +)

7235

-__atomic_do_and_fetch (int, 4, sub, -)

7236

-__atomic_do_and_fetch (int, 4, or, |)

7237

-__atomic_do_and_fetch (int, 4, and, &)

7238

-__atomic_do_and_fetch (int, 4, xor, |)

7239

-__atomic_do_and_fetch (int, 4, nand, &)

7240

-__atomic_do_and_fetch (long long, 8, add, +)

7241

-__atomic_do_and_fetch (long long, 8, sub, -)

7242

-__atomic_do_and_fetch (long long, 8, or, |)

7243

-__atomic_do_and_fetch (long long, 8, and, &)

7244

-__atomic_do_and_fetch (long long, 8, xor, |)

7245

-__atomic_do_and_fetch (long long, 8, nand, &)

7246

+

7247

+#define __atomic_do_and_fetch(type, size, opname, op, op2) \

7248

+ __do_and_fetch(type __atomic_##opname##_fetch_##size(type* p, type i, int model), \

7249

+ type, size, opname, op, op2, \

7250

+ pre_atomic_barrier(model), \

7251

+ post_atomic_barrier(model)) \

7252

+

7253

+__atomic_do_and_fetch (int, 4, add, +, )

7254

+__atomic_do_and_fetch (int, 4, sub, -, )

7255

+__atomic_do_and_fetch (int, 4, or, |, )

7256

+__atomic_do_and_fetch (int, 4, and, &, )

7257

+__atomic_do_and_fetch (int, 4, xor, |, )

7258

+__atomic_do_and_fetch (int, 4, nand, &, ~)

7259

+__atomic_do_and_fetch (long long, 8, add, +, )

7260

+__atomic_do_and_fetch (long long, 8, sub, -, )

7261

+__atomic_do_and_fetch (long long, 8, or, |, )

7262

+__atomic_do_and_fetch (long long, 8, and, &, )

7263

+__atomic_do_and_fetch (long long, 8, xor, |, )

7264

+__atomic_do_and_fetch (long long, 8, nand, &, ~)

7265

+

7266

+#define __sync_do_and_fetch(type, size, opname, op, op2) \

7267

+ __do_and_fetch(type __sync_##opname##_and_fetch_##size(type* p, type i), \

7268

+ type, size, opname, op, op2, \

7269

+ arch_atomic_write_barrier(), \

7270

+ arch_atomic_read_barrier()) \

7271

+

7272

+__sync_do_and_fetch (int, 4, add, +, )

7273

+__sync_do_and_fetch (int, 4, sub, -, )

7274

+__sync_do_and_fetch (int, 4, or, |, )

7275

+__sync_do_and_fetch (int, 4, and, &, )

7276

+__sync_do_and_fetch (int, 4, xor, |, )

7277

+__sync_do_and_fetch (int, 4, nand, &, ~)

7278

+__sync_do_and_fetch (long long, 8, add, +, )

7279

+__sync_do_and_fetch (long long, 8, sub, -, )

7280

+__sync_do_and_fetch (long long, 8, or, |, )

7281

+__sync_do_and_fetch (long long, 8, and, &, )

7282

+__sync_do_and_fetch (long long, 8, xor, |, )

7283

+__sync_do_and_fetch (long long, 8, nand, &, ~)

7284

+

7285

#define __atomic_exchange_methods(type, size) \

7286

bool \

7287

__atomic_compare_exchange_##size(volatile type* ptr, type* oldvalp, \

7288

@@ -128,49 +179,117 @@

7289

post_atomic_barrier(model); \

7290

return retval; \

7291

}

7292

+

7293

__atomic_exchange_methods (int, 4)

7294

__atomic_exchange_methods (long long, 8)

7295

7296

+#define __sync_exchange_methods(type, size) \

7297

+type \

7298

+__sync_val_compare_and_swap_##size(type* ptr, type oldval, type newval) \

7299

+{ \

7300

+ arch_atomic_write_barrier(); \

7301

+ type retval = arch_atomic_val_compare_and_exchange(ptr, oldval, newval); \

7302

+ arch_atomic_read_barrier(); \

7303

+ return retval; \

7304

+} \

7305

+ \

7306

+bool \

7307

+__sync_bool_compare_and_swap_##size(type* ptr, type oldval, type newval) \

7308

+{ \

7309

+ arch_atomic_write_barrier(); \

7310

+ bool retval = arch_atomic_bool_compare_and_exchange(ptr, oldval, newval); \

7311

+ arch_atomic_read_barrier(); \

7312

+ return retval; \

7313

+} \

7314

+ \

7315

+type \

7316

+__sync_lock_test_and_set_##size(type* ptr, type val) \

7317

+{ \

7318

+ type retval = arch_atomic_exchange(ptr, val); \

7319

+ arch_atomic_acquire_barrier_value(retval); \

7320

+ return retval; \

7321

+}

7322

+

7323

+__sync_exchange_methods (int, 4)

7324

+__sync_exchange_methods (long long, 8)

7325

+

7326

+#ifdef __LITTLE_ENDIAN__

7327

+#define BIT_OFFSET(n, type) ((n) * 8)

7328

+#else

7329

+#define BIT_OFFSET(n, type) ((4 - sizeof(type) - (n)) * 8)

7330

+#endif

7331

+

7332

/* Subword methods require the same approach for both TILEPro and

7333

TILE-Gx. We load the background data for the word, insert the

7334

desired subword piece, then compare-and-exchange it into place. */

7335

#define u8 unsigned char

7336

#define u16 unsigned short

7337

+

7338

+#define __subword_cmpxchg_body(type, size, ptr, guess, val) \

7339

+ ({ \

7340

+ unsigned int *p = (unsigned int *)((unsigned long)ptr & ~3UL); \

7341

+ const int shift = BIT_OFFSET((unsigned long)ptr & 3UL, type); \

7342

+ const unsigned int valmask = (1 << (sizeof(type) * 8)) - 1; \

7343

+ const unsigned int bgmask = ~(valmask << shift); \

7344

+ unsigned int oldword = *p; \

7345

+ type oldval = (oldword >> shift) & valmask; \

7346

+ if (__builtin_expect((oldval == guess), 1)) { \

7347

+ unsigned int word = (oldword & bgmask) | ((val & valmask) << shift); \

7348

+ oldword = arch_atomic_val_compare_and_exchange(p, oldword, word); \

7349

+ oldval = (oldword >> shift) & valmask; \

7350

+ } \

7351

+ oldval; \

7352

+ }) \

7353

+

7354

#define __atomic_subword_cmpxchg(type, size) \

7355

\

7356

bool \

7357

-__atomic_compare_exchange_##size(volatile type* ptr, type* guess, \

7358

+__atomic_compare_exchange_##size(volatile type* ptr, type* guess_ptr, \

7359

type val, bool weak __unused, int models, \

7360

int modelf __unused) \

7361

{ \

7362

pre_atomic_barrier(models); \

7363

- unsigned int *p = (unsigned int *)((unsigned long)ptr & ~3UL); \

7364

- const int shift = ((unsigned long)ptr & 3UL) * 8; \

7365

- const unsigned int valmask = (1 << (sizeof(type) * 8)) - 1; \

7366

- const unsigned int bgmask = ~(valmask << shift); \

7367

- unsigned int oldword = *p; \

7368

- type oldval = (oldword >> shift) & valmask; \

7369

- if (__builtin_expect((oldval == *guess), 1)) { \

7370

- unsigned int word = (oldword & bgmask) | ((val & valmask) << shift); \

7371

- oldword = arch_atomic_val_compare_and_exchange(p, oldword, word); \

7372

- oldval = (oldword >> shift) & valmask; \

7373

- } \

7374

+ type guess = *guess_ptr; \

7375

+ type oldval = __subword_cmpxchg_body(type, size, ptr, guess, val); \

7376

post_atomic_barrier(models); \

7377

- bool success = (oldval == *guess); \

7378

- *guess = oldval; \

7379

+ bool success = (oldval == guess); \

7380

+ *guess_ptr = oldval; \

7381

return success; \

7382

}

7383

+

7384

__atomic_subword_cmpxchg (u8, 1)

7385

__atomic_subword_cmpxchg (u16, 2)

7386

+

7387

+#define __sync_subword_cmpxchg(type, size) \

7388

+ \

7389

+type \

7390

+__sync_val_compare_and_swap_##size(type* ptr, type guess, type val) \

7391

+{ \

7392

+ arch_atomic_write_barrier(); \

7393

+ type oldval = __subword_cmpxchg_body(type, size, ptr, guess, val); \

7394

+ arch_atomic_read_barrier(); \

7395

+ return oldval; \

7396

+} \

7397

+ \

7398

+bool \

7399

+__sync_bool_compare_and_swap_##size(type* ptr, type guess, type val) \

7400

+{ \

7401

+ type oldval = __sync_val_compare_and_swap_##size(ptr, guess, val); \

7402

+ return oldval == guess; \

7403

+}

7404

+

7405

+__sync_subword_cmpxchg (u8, 1)

7406

+__sync_subword_cmpxchg (u16, 2)

7407

+

7408

/* For the atomic-update subword methods, we use the same approach as

7409

above, but we retry until we succeed if the compare-and-exchange

7410

fails. */

7411

-#define __atomic_subword(type, proto, top, expr, bottom) \

7412

+#define __subword(type, proto, top, expr, bottom) \

7413

proto \

7414

{ \

7415

top \

7416

unsigned int *p = (unsigned int *)((unsigned long)ptr & ~3UL); \

7417

- const int shift = ((unsigned long)ptr & 3UL) * 8; \

7418

+ const int shift = BIT_OFFSET((unsigned long)ptr & 3UL, type); \

7419

const unsigned int valmask = (1 << (sizeof(type) * 8)) - 1; \

7420

const unsigned int bgmask = ~(valmask << shift); \

7421

unsigned int oldword, xword = *p; \

7422

@@ -184,12 +303,14 @@

7423

} while (__builtin_expect(xword != oldword, 0)); \

7424

bottom \

7425

}

7426

+

7427

#define __atomic_subword_fetch(type, funcname, expr, retval) \

7428

- __atomic_subword(type, \

7429

- type __atomic_ ## funcname(volatile type *ptr, type i, int model), \

7430

- pre_atomic_barrier(model);, \

7431

- expr, \

7432

- post_atomic_barrier(model); return retval;)

7433

+ __subword(type, \

7434

+ type __atomic_ ## funcname(volatile type *ptr, type i, int model), \

7435

+ pre_atomic_barrier(model);, \

7436

+ expr, \

7437

+ post_atomic_barrier(model); return retval;)

7438

+

7439

__atomic_subword_fetch (u8, fetch_add_1, oldval + i, oldval)

7440

__atomic_subword_fetch (u8, fetch_sub_1, oldval - i, oldval)

7441

__atomic_subword_fetch (u8, fetch_or_1, oldval | i, oldval)

7442

@@ -196,6 +317,7 @@

7443

__atomic_subword_fetch (u8, fetch_and_1, oldval & i, oldval)

7444

__atomic_subword_fetch (u8, fetch_xor_1, oldval ^ i, oldval)

7445

__atomic_subword_fetch (u8, fetch_nand_1, ~(oldval & i), oldval)

7446

+

7447

__atomic_subword_fetch (u16, fetch_add_2, oldval + i, oldval)

7448

__atomic_subword_fetch (u16, fetch_sub_2, oldval - i, oldval)

7449

__atomic_subword_fetch (u16, fetch_or_2, oldval | i, oldval)

7450

@@ -202,6 +324,7 @@

7451

__atomic_subword_fetch (u16, fetch_and_2, oldval & i, oldval)

7452

__atomic_subword_fetch (u16, fetch_xor_2, oldval ^ i, oldval)

7453

__atomic_subword_fetch (u16, fetch_nand_2, ~(oldval & i), oldval)

7454

+

7455

__atomic_subword_fetch (u8, add_fetch_1, oldval + i, val)

7456

__atomic_subword_fetch (u8, sub_fetch_1, oldval - i, val)

7457

__atomic_subword_fetch (u8, or_fetch_1, oldval | i, val)

7458

@@ -208,6 +331,7 @@

7459

__atomic_subword_fetch (u8, and_fetch_1, oldval & i, val)

7460

__atomic_subword_fetch (u8, xor_fetch_1, oldval ^ i, val)

7461

__atomic_subword_fetch (u8, nand_fetch_1, ~(oldval & i), val)

7462

+

7463

__atomic_subword_fetch (u16, add_fetch_2, oldval + i, val)

7464

__atomic_subword_fetch (u16, sub_fetch_2, oldval - i, val)

7465

__atomic_subword_fetch (u16, or_fetch_2, oldval | i, val)

7466

@@ -214,12 +338,58 @@

7467

__atomic_subword_fetch (u16, and_fetch_2, oldval & i, val)

7468

__atomic_subword_fetch (u16, xor_fetch_2, oldval ^ i, val)

7469

__atomic_subword_fetch (u16, nand_fetch_2, ~(oldval & i), val)

7470

+

7471

+#define __sync_subword_fetch(type, funcname, expr, retval) \

7472

+ __subword(type, \

7473

+ type __sync_ ## funcname(type *ptr, type i), \

7474

+ arch_atomic_read_barrier();, \

7475

+ expr, \

7476

+ arch_atomic_write_barrier(); return retval;)

7477

+

7478

+__sync_subword_fetch (u8, fetch_and_add_1, oldval + i, oldval)

7479

+__sync_subword_fetch (u8, fetch_and_sub_1, oldval - i, oldval)

7480

+__sync_subword_fetch (u8, fetch_and_or_1, oldval | i, oldval)

7481

+__sync_subword_fetch (u8, fetch_and_and_1, oldval & i, oldval)

7482

+__sync_subword_fetch (u8, fetch_and_xor_1, oldval ^ i, oldval)

7483

+__sync_subword_fetch (u8, fetch_and_nand_1, ~(oldval & i), oldval)

7484

+

7485

+__sync_subword_fetch (u16, fetch_and_add_2, oldval + i, oldval)

7486

+__sync_subword_fetch (u16, fetch_and_sub_2, oldval - i, oldval)

7487

+__sync_subword_fetch (u16, fetch_and_or_2, oldval | i, oldval)

7488

+__sync_subword_fetch (u16, fetch_and_and_2, oldval & i, oldval)

7489

+__sync_subword_fetch (u16, fetch_and_xor_2, oldval ^ i, oldval)

7490

+__sync_subword_fetch (u16, fetch_and_nand_2, ~(oldval & i), oldval)

7491

+

7492

+__sync_subword_fetch (u8, add_and_fetch_1, oldval + i, val)

7493

+__sync_subword_fetch (u8, sub_and_fetch_1, oldval - i, val)

7494

+__sync_subword_fetch (u8, or_and_fetch_1, oldval | i, val)

7495

+__sync_subword_fetch (u8, and_and_fetch_1, oldval & i, val)

7496

+__sync_subword_fetch (u8, xor_and_fetch_1, oldval ^ i, val)

7497

+__sync_subword_fetch (u8, nand_and_fetch_1, ~(oldval & i), val)

7498

+

7499

+__sync_subword_fetch (u16, add_and_fetch_2, oldval + i, val)

7500

+__sync_subword_fetch (u16, sub_and_fetch_2, oldval - i, val)

7501

+__sync_subword_fetch (u16, or_and_fetch_2, oldval | i, val)

7502

+__sync_subword_fetch (u16, and_and_fetch_2, oldval & i, val)

7503

+__sync_subword_fetch (u16, xor_and_fetch_2, oldval ^ i, val)

7504

+__sync_subword_fetch (u16, nand_and_fetch_2, ~(oldval & i), val)

7505

+

7506

#define __atomic_subword_lock(type, size) \

7507

- \

7508

-__atomic_subword(type, \

7509

- type __atomic_exchange_##size(volatile type* ptr, type nval, int model), \

7510

- pre_atomic_barrier(model);, \

7511

- nval, \

7512

- post_atomic_barrier(model); return oldval;)

7513

+ __subword(type, \

7514

+ type __atomic_exchange_##size(volatile type* ptr, type nval, int model), \

7515

+ pre_atomic_barrier(model);, \

7516

+ nval, \

7517

+ post_atomic_barrier(model); return oldval;)

7518

+

7519

__atomic_subword_lock (u8, 1)

7520

__atomic_subword_lock (u16, 2)

7521

+

7522

+#define __sync_subword_lock(type, size) \

7523

+ __subword(type, \

7524

+ type __sync_lock_test_and_set_##size(type* ptr, type nval), \

7525

+ , \

7526

+ nval, \

7527

+ arch_atomic_acquire_barrier_value(oldval); return oldval;)

7528

+

7529

+__sync_subword_lock (u8, 1)

7530

+__sync_subword_lock (u16, 2)

7531

Index: libgcc/config/arm/sfp-machine.h

7532

===================================================================

7533

--- a/src/libgcc/config/arm/sfp-machine.h (.../tags/gcc_4_8_2_release)

7534

+++ b/src/libgcc/config/arm/sfp-machine.h (.../branches/gcc-4_8-branch)

7535

@@ -19,10 +19,12 @@

7536

#define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_2_udiv(D,R,X,Y)

7537

#define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_4_udiv(Q,R,X,Y)

7538

7539

-#define _FP_NANFRAC_H ((_FP_QNANBIT_H << 1) - 1)

7540

-#define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1)

7541

-#define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1), -1

7542

-#define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1, -1, -1

7543

+/* According to RTABI, QNAN is only with the most significant bit of the

7544

+ significand set, and all other significand bits zero. */

7545

+#define _FP_NANFRAC_H 0

7546

+#define _FP_NANFRAC_S 0

7547

+#define _FP_NANFRAC_D 0, 0

7548

+#define _FP_NANFRAC_Q 0, 0, 0, 0

7549

#define _FP_NANSIGN_H 0

7550

#define _FP_NANSIGN_S 0

7551

#define _FP_NANSIGN_D 0

7552

Index: libgcc/unwind-seh.c

7553

===================================================================

7554

--- a/src/libgcc/unwind-seh.c (.../tags/gcc_4_8_2_release)

7555

+++ b/src/libgcc/unwind-seh.c (.../branches/gcc-4_8-branch)

7556

@@ -313,8 +313,9 @@

7557

ms_exc->ExceptionInformation[3] = gcc_context.reg[1];

7558

7559

/* Begin phase 2. Perform the unwinding. */

7560

- RtlUnwindEx (this_frame, gcc_context.ra, ms_exc, gcc_exc,

7561

- ms_orig_context, ms_disp->HistoryTable);

7562

+ RtlUnwindEx (this_frame, gcc_context.ra, ms_exc,

7563

+ (PVOID)gcc_context.reg[0], ms_orig_context,

7564

+ ms_disp->HistoryTable);

7565

}

7566

7567

/* In _Unwind_RaiseException we return _URC_FATAL_PHASE1_ERROR. */

7568

Index: config.guess

7569

===================================================================

7570

--- a/src/config.guess (.../tags/gcc_4_8_2_release)

7571

+++ b/src/config.guess (.../branches/gcc-4_8-branch)

7572

@@ -1,10 +1,8 @@

7573

#! /bin/sh

7574

# Attempt to guess a canonical system name.

7575

7576

-# 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,

7577

-# 2011, 2012, 2013 Free Software Foundation, Inc.

7578

7579

7580

-timestamp='2012-12-30'

7581

+timestamp='2013-06-10'

7582

7583

# This file is free software; you can redistribute it and/or modify it

7584

# under the terms of the GNU General Public License as published by

7585

@@ -52,9 +50,7 @@

7586

GNU config.guess ($timestamp)

7587

7588

Originally written by Per Bothner.

7589

7590

-2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011,

7591

-2012, 2013 Free Software Foundation, Inc.

7592

7593

7594

This is free software; see the source for copying conditions. There is NO

7595

warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE."

7596

@@ -136,6 +132,27 @@

7597

UNAME_SYSTEM=`(uname -s) 2>/dev/null` || UNAME_SYSTEM=unknown

7598

UNAME_VERSION=`(uname -v) 2>/dev/null` || UNAME_VERSION=unknown

7599

7600

+case "${UNAME_SYSTEM}" in

7601

+Linux|GNU|GNU/*)

7602

+ # If the system lacks a compiler, then just pick glibc.

7603

+ # We could probably try harder.

7604

+ LIBC=gnu

7605

+

7606

+ eval $set_cc_for_build

7607

+ cat <<-EOF > $dummy.c

7608

+ #include <features.h>

7609

+ #if defined(__UCLIBC__)

7610

+ LIBC=uclibc

7611

+ #elif defined(__dietlibc__)

7612

+ LIBC=dietlibc

7613

+ #else

7614

+ LIBC=gnu

7615

+ #endif

7616

+ EOF

7617

+ eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep '^LIBC'`

7618

+ ;;

7619

+esac

7620

+

7621

# Note: order is significant - the case branches are not exclusive.

7622

7623

case "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" in

7624

@@ -857,21 +874,21 @@

7625

exit ;;

7626

*:GNU:*:*)

7627

# the GNU system

7628

- echo `echo ${UNAME_MACHINE}|sed -e 's,[-/].*$,,'`-unknown-gnu`echo ${UNAME_RELEASE}|sed -e 's,/.*$,,'`

7629

+ echo `echo ${UNAME_MACHINE}|sed -e 's,[-/].*$,,'`-unknown-${LIBC}`echo ${UNAME_RELEASE}|sed -e 's,/.*$,,'`

7630

exit ;;

7631

*:GNU/*:*:*)

7632

# other systems with GNU libc and userland

7633

- echo ${UNAME_MACHINE}-unknown-`echo ${UNAME_SYSTEM} | sed 's,^[^/]*/,,' | tr '[A-Z]' '[a-z]'``echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'`-gnu

7634

+ echo ${UNAME_MACHINE}-unknown-`echo ${UNAME_SYSTEM} | sed 's,^[^/]*/,,' | tr '[A-Z]' '[a-z]'``echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'`-${LIBC}

7635

exit ;;

7636

i*86:Minix:*:*)

7637

echo ${UNAME_MACHINE}-pc-minix

7638

exit ;;

7639

aarch64:Linux:*:*)

7640

- echo ${UNAME_MACHINE}-unknown-linux-gnu

7641

+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}

7642

exit ;;

7643

aarch64_be:Linux:*:*)

7644

UNAME_MACHINE=aarch64_be

7645

- echo ${UNAME_MACHINE}-unknown-linux-gnu

7646

+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}

7647

exit ;;

7648

alpha:Linux:*:*)

7649

case `sed -n '/^cpu model/s/^.*: $.*$/\1/p' < /proc/cpuinfo` in

7650

@@ -884,59 +901,54 @@

7651

EV68*) UNAME_MACHINE=alphaev68 ;;

7652

esac

7653

objdump --private-headers /bin/sh | grep -q ld.so.1

7654

- if test "$?" = 0 ; then LIBC="libc1" ; else LIBC="" ; fi

7655

- echo ${UNAME_MACHINE}-unknown-linux-gnu${LIBC}

7656

+ if test "$?" = 0 ; then LIBC="gnulibc1" ; fi

7657

+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}

7658

exit ;;

7659

+ arc:Linux:*:* | arceb:Linux:*:*)

7660

+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}

7661

+ exit ;;

7662

arm*:Linux:*:*)

7663

eval $set_cc_for_build

7664

if echo __ARM_EABI__ | $CC_FOR_BUILD -E - 2>/dev/null \

7665

| grep -q __ARM_EABI__

7666

then

7667

- echo ${UNAME_MACHINE}-unknown-linux-gnu

7668

+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}

7669

else

7670

if echo __ARM_PCS_VFP | $CC_FOR_BUILD -E - 2>/dev/null \

7671

| grep -q __ARM_PCS_VFP

7672

then

7673

- echo ${UNAME_MACHINE}-unknown-linux-gnueabi

7674

+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}eabi

7675

else

7676

- echo ${UNAME_MACHINE}-unknown-linux-gnueabihf

7677

+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}eabihf

7678

fi

7679

fi

7680

exit ;;

7681

avr32*:Linux:*:*)

7682

- echo ${UNAME_MACHINE}-unknown-linux-gnu

7683

+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}

7684

exit ;;

7685

cris:Linux:*:*)

7686

- echo ${UNAME_MACHINE}-axis-linux-gnu

7687

+ echo ${UNAME_MACHINE}-axis-linux-${LIBC}

7688

exit ;;

7689

crisv32:Linux:*:*)

7690

- echo ${UNAME_MACHINE}-axis-linux-gnu

7691

+ echo ${UNAME_MACHINE}-axis-linux-${LIBC}

7692

exit ;;

7693

frv:Linux:*:*)

7694

- echo ${UNAME_MACHINE}-unknown-linux-gnu

7695

+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}

7696

exit ;;

7697

hexagon:Linux:*:*)

7698

- echo ${UNAME_MACHINE}-unknown-linux-gnu

7699

+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}

7700

exit ;;

7701

i*86:Linux:*:*)

7702

- LIBC=gnu

7703

- eval $set_cc_for_build

7704

- sed 's/^ //' << EOF >$dummy.c

7705

- #ifdef __dietlibc__

7706

- LIBC=dietlibc

7707

- #endif

7708

-EOF

7709

- eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep '^LIBC'`

7710

- echo "${UNAME_MACHINE}-pc-linux-${LIBC}"

7711

+ echo ${UNAME_MACHINE}-pc-linux-${LIBC}

7712

exit ;;

7713

ia64:Linux:*:*)

7714

- echo ${UNAME_MACHINE}-unknown-linux-gnu

7715

+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}

7716

exit ;;

7717

m32r*:Linux:*:*)

7718

- echo ${UNAME_MACHINE}-unknown-linux-gnu

7719

+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}

7720

exit ;;

7721

m68*:Linux:*:*)

7722

- echo ${UNAME_MACHINE}-unknown-linux-gnu

7723

+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}

7724

exit ;;

7725

mips:Linux:*:* | mips64:Linux:*:*)

7726

eval $set_cc_for_build

7727

@@ -955,54 +967,63 @@

7728

#endif

7729

EOF

7730

eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep '^CPU'`

7731

- test x"${CPU}" != x && { echo "${CPU}-unknown-linux-gnu"; exit; }

7732

+ test x"${CPU}" != x && { echo "${CPU}-unknown-linux-${LIBC}"; exit; }

7733

;;

7734

+ or1k:Linux:*:*)

7735

+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}

7736

+ exit ;;

7737

or32:Linux:*:*)

7738

- echo ${UNAME_MACHINE}-unknown-linux-gnu

7739

+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}

7740

exit ;;

7741

padre:Linux:*:*)

7742

- echo sparc-unknown-linux-gnu

7743

+ echo sparc-unknown-linux-${LIBC}

7744

exit ;;

7745

parisc64:Linux:*:* | hppa64:Linux:*:*)

7746

- echo hppa64-unknown-linux-gnu

7747

+ echo hppa64-unknown-linux-${LIBC}

7748

exit ;;

7749

parisc:Linux:*:* | hppa:Linux:*:*)

7750

# Look for CPU level

7751

case `grep '^cpu[^a-z]*:' /proc/cpuinfo 2>/dev/null | cut -d' ' -f2` in

7752

- PA7*) echo hppa1.1-unknown-linux-gnu ;;

7753

- PA8*) echo hppa2.0-unknown-linux-gnu ;;

7754

- *) echo hppa-unknown-linux-gnu ;;

7755

+ PA7*) echo hppa1.1-unknown-linux-${LIBC} ;;

7756

+ PA8*) echo hppa2.0-unknown-linux-${LIBC} ;;

7757

+ *) echo hppa-unknown-linux-${LIBC} ;;

7758

esac

7759

exit ;;

7760

ppc64:Linux:*:*)

7761

- echo powerpc64-unknown-linux-gnu

7762

+ echo powerpc64-unknown-linux-${LIBC}

7763

exit ;;

7764

ppc:Linux:*:*)

7765

- echo powerpc-unknown-linux-gnu

7766

+ echo powerpc-unknown-linux-${LIBC}

7767

exit ;;

7768

+ ppc64le:Linux:*:*)

7769

+ echo powerpc64le-unknown-linux-${LIBC}

7770

+ exit ;;

7771

+ ppcle:Linux:*:*)

7772

+ echo powerpcle-unknown-linux-${LIBC}

7773

+ exit ;;

7774

s390:Linux:*:* | s390x:Linux:*:*)

7775

- echo ${UNAME_MACHINE}-ibm-linux

7776

+ echo ${UNAME_MACHINE}-ibm-linux-${LIBC}

7777

exit ;;

7778

sh64*:Linux:*:*)

7779

- echo ${UNAME_MACHINE}-unknown-linux-gnu

7780

+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}

7781

exit ;;

7782

sh*:Linux:*:*)

7783

- echo ${UNAME_MACHINE}-unknown-linux-gnu

7784

+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}

7785

exit ;;

7786

sparc:Linux:*:* | sparc64:Linux:*:*)

7787

- echo ${UNAME_MACHINE}-unknown-linux-gnu

7788

+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}

7789

exit ;;

7790

tile*:Linux:*:*)

7791

- echo ${UNAME_MACHINE}-unknown-linux-gnu

7792

+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}

7793

exit ;;

7794

vax:Linux:*:*)

7795

- echo ${UNAME_MACHINE}-dec-linux-gnu

7796

+ echo ${UNAME_MACHINE}-dec-linux-${LIBC}

7797

exit ;;

7798

x86_64:Linux:*:*)

7799

- echo ${UNAME_MACHINE}-unknown-linux-gnu

7800

+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}

7801

exit ;;

7802

xtensa*:Linux:*:*)

7803

- echo ${UNAME_MACHINE}-unknown-linux-gnu

7804

+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}

7805

exit ;;

7806

i*86:DYNIX/ptx:4*:*)

7807

# ptx 4.0 does uname -s correctly, with DYNIX/ptx in there.

7808

@@ -1235,19 +1256,21 @@

7809

exit ;;

7810

*:Darwin:*:*)

7811

UNAME_PROCESSOR=`uname -p` || UNAME_PROCESSOR=unknown

7812

- case $UNAME_PROCESSOR in

7813

- i386)

7814

- eval $set_cc_for_build

7815

- if [ "$CC_FOR_BUILD" != 'no_compiler_found' ]; then

7816

- if (echo '#ifdef __LP64__'; echo IS_64BIT_ARCH; echo '#endif') | \

7817

- (CCOPTS= $CC_FOR_BUILD -E - 2>/dev/null) | \

7818

- grep IS_64BIT_ARCH >/dev/null

7819

- then

7820

- UNAME_PROCESSOR="x86_64"

7821

- fi

7822

- fi ;;

7823

- unknown) UNAME_PROCESSOR=powerpc ;;

7824

- esac

7825

+ eval $set_cc_for_build

7826

+ if test "$UNAME_PROCESSOR" = unknown ; then

7827

+ UNAME_PROCESSOR=powerpc

7828

+ fi

7829

+ if [ "$CC_FOR_BUILD" != 'no_compiler_found' ]; then

7830

+ if (echo '#ifdef __LP64__'; echo IS_64BIT_ARCH; echo '#endif') | \

7831

+ (CCOPTS= $CC_FOR_BUILD -E - 2>/dev/null) | \

7832

+ grep IS_64BIT_ARCH >/dev/null

7833

+ then

7834

+ case $UNAME_PROCESSOR in

7835

+ i386) UNAME_PROCESSOR=x86_64 ;;

7836

+ powerpc) UNAME_PROCESSOR=powerpc64 ;;

7837

+ esac

7838

+ fi

7839

+ fi

7840

echo ${UNAME_PROCESSOR}-apple-darwin${UNAME_RELEASE}

7841

exit ;;

7842

*:procnto*:*:* | *:QNX:[0123456789]*:*)

7843

Index: gcc/tree-vrp.c

7844

===================================================================

7845

--- a/src/gcc/tree-vrp.c (.../tags/gcc_4_8_2_release)

7846

+++ b/src/gcc/tree-vrp.c (.../branches/gcc-4_8-branch)

7847

@@ -5271,9 +5271,13 @@

7848

}

7849

else if (CONVERT_EXPR_CODE_P (gimple_assign_rhs_code (op_def)))

7850

{

7851

- /* Recurse through the type conversion. */

7852

- retval |= register_edge_assert_for_1 (gimple_assign_rhs1 (op_def),

7853

- code, e, bsi);

7854

+ /* Recurse through the type conversion, unless it is a narrowing

7855

+ conversion or conversion from non-integral type. */

7856

+ tree rhs = gimple_assign_rhs1 (op_def);

7857

+ if (INTEGRAL_TYPE_P (TREE_TYPE (rhs))

7858

+ && (TYPE_PRECISION (TREE_TYPE (rhs))

7859

+ <= TYPE_PRECISION (TREE_TYPE (op))))

7860

+ retval |= register_edge_assert_for_1 (rhs, code, e, bsi);

7861

}

7862

7863

return retval;

7864

@@ -7453,7 +7457,8 @@

7865

}

7866

else if ((operand_less_p (vr1min, *vr0max) == 1

7867

|| operand_equal_p (vr1min, *vr0max, 0))

7868

- && operand_less_p (*vr0min, vr1min) == 1)

7869

+ && operand_less_p (*vr0min, vr1min) == 1

7870

+ && operand_less_p (*vr0max, vr1max) == 1)

7871

{

7872

/* [ ( ] ) or [ ]( ) */

7873

if (*vr0type == VR_RANGE

7874

@@ -7487,7 +7492,8 @@

7875

}

7876

else if ((operand_less_p (*vr0min, vr1max) == 1

7877

|| operand_equal_p (*vr0min, vr1max, 0))

7878

- && operand_less_p (vr1min, *vr0min) == 1)

7879

+ && operand_less_p (vr1min, *vr0min) == 1

7880

+ && operand_less_p (vr1max, *vr0max) == 1)

7881

{

7882

/* ( [ ) ] or ( )[ ] */

7883

if (*vr0type == VR_RANGE

7884

Index: gcc/loop-unswitch.c

7885

===================================================================

7886

--- a/src/gcc/loop-unswitch.c (.../tags/gcc_4_8_2_release)

7887

+++ b/src/gcc/loop-unswitch.c (.../branches/gcc-4_8-branch)

7888

@@ -191,6 +191,7 @@

7889

if (!test)

7890

return NULL_RTX;

7891

7892

+ mode = VOIDmode;

7893

for (i = 0; i < 2; i++)

7894

{

7895

op[i] = XEXP (test, i);

7896

@@ -205,11 +206,15 @@

7897

return NULL_RTX;

7898

7899

op[i] = get_iv_value (&iv, const0_rtx);

7900

+ if (iv.extend != IV_UNKNOWN_EXTEND

7901

+ && iv.mode != iv.extend_mode)

7902

+ op[i] = lowpart_subreg (iv.mode, op[i], iv.extend_mode);

7903

+ if (mode == VOIDmode)

7904

+ mode = iv.mode;

7905

+ else

7906

+ gcc_assert (mode == iv.mode);

7907

}

7908

7909

- mode = GET_MODE (op[0]);

7910

- if (mode == VOIDmode)

7911

- mode = GET_MODE (op[1]);

7912

if (GET_MODE_CLASS (mode) == MODE_CC)

7913

{

7914

if (at != BB_END (bb))

7915

Index: gcc/tree-ssa-loop-im.c

7916

===================================================================

7917

--- a/src/gcc/tree-ssa-loop-im.c (.../tags/gcc_4_8_2_release)

7918

+++ b/src/gcc/tree-ssa-loop-im.c (.../branches/gcc-4_8-branch)

7919

@@ -1190,6 +1190,67 @@

7920

fini_walk_dominator_tree (&walk_data);

7921

}

7922

7923

+/* Return true if CODE is an operation that when operating on signed

7924

+ integer types involves undefined behavior on overflow and the

7925

+ operation can be expressed with unsigned arithmetic. */

7926

+

7927

+static bool

7928

+arith_code_with_undefined_signed_overflow (tree_code code)

7929

+{

7930

+ switch (code)

7931

+ {

7932

+ case PLUS_EXPR:

7933

+ case MINUS_EXPR:

7934

+ case MULT_EXPR:

7935

+ case NEGATE_EXPR:

7936

+ case POINTER_PLUS_EXPR:

7937

+ return true;

7938

+ default:

7939

+ return false;

7940

+ }

7941

+}

7942

+

7943

+/* Rewrite STMT, an assignment with a signed integer or pointer arithmetic

7944

+ operation that can be transformed to unsigned arithmetic by converting

7945

+ its operand, carrying out the operation in the corresponding unsigned

7946

+ type and converting the result back to the original type.

7947

+

7948

+ Returns a sequence of statements that replace STMT and also contain

7949

+ a modified form of STMT itself. */

7950

+

7951

+static gimple_seq

7952

+rewrite_to_defined_overflow (gimple stmt)

7953

+{

7954

+ if (dump_file && (dump_flags & TDF_DETAILS))

7955

+ {

7956

+ fprintf (dump_file, "rewriting stmt with undefined signed "

7957

+ "overflow ");

7958

+ print_gimple_stmt (dump_file, stmt, 0, TDF_SLIM);

7959

+ }

7960

+

7961

+ tree lhs = gimple_assign_lhs (stmt);

7962

+ tree type = unsigned_type_for (TREE_TYPE (lhs));

7963

+ gimple_seq stmts = NULL;

7964

+ for (unsigned i = 1; i < gimple_num_ops (stmt); ++i)

7965

+ {

7966

+ gimple_seq stmts2 = NULL;

7967

+ gimple_set_op (stmt, i,

7968

+ force_gimple_operand (fold_convert (type,

7969

+ gimple_op (stmt, i)),

7970

+ &stmts2, true, NULL_TREE));

7971

+ gimple_seq_add_seq (&stmts, stmts2);

7972

+ }

7973

+ gimple_assign_set_lhs (stmt, make_ssa_name (type, stmt));

7974

+ if (gimple_assign_rhs_code (stmt) == POINTER_PLUS_EXPR)

7975

+ gimple_assign_set_rhs_code (stmt, PLUS_EXPR);

7976

+ gimple_seq_add_stmt (&stmts, stmt);

7977

+ gimple cvt = gimple_build_assign_with_ops

7978

+ (NOP_EXPR, lhs, gimple_assign_lhs (stmt), NULL_TREE);

7979

+ gimple_seq_add_stmt (&stmts, cvt);

7980

+

7981

+ return stmts;

7982

+}

7983

+

7984

/* Hoist the statements in basic block BB out of the loops prescribed by

7985

data stored in LIM_DATA structures associated with each statement. Callback

7986

for walk_dominator_tree. */

7987

@@ -1321,7 +1382,21 @@

7988

}

7989

}

7990

gsi_remove (&bsi, false);

7991

- gsi_insert_on_edge (e, stmt);

7992

+ /* In case this is a stmt that is not unconditionally executed

7993

+ when the target loop header is executed and the stmt may

7994

+ invoke undefined integer or pointer overflow rewrite it to

7995

+ unsigned arithmetic. */

7996

+ if (is_gimple_assign (stmt)

7997

+ && INTEGRAL_TYPE_P (TREE_TYPE (gimple_assign_lhs (stmt)))

7998

+ && TYPE_OVERFLOW_UNDEFINED (TREE_TYPE (gimple_assign_lhs (stmt)))

7999

+ && arith_code_with_undefined_signed_overflow

8000

+ (gimple_assign_rhs_code (stmt))

8001

+ && (!ALWAYS_EXECUTED_IN (bb)

8002

+ || !(ALWAYS_EXECUTED_IN (bb) == level

8003

+ || flow_loop_nested_p (ALWAYS_EXECUTED_IN (bb), level))))

8004

+ gsi_insert_seq_on_edge (e, rewrite_to_defined_overflow (stmt));

8005

+ else

8006

+ gsi_insert_on_edge (e, stmt);

8007

}

8008

}

8009

8010

Index: gcc/tree-ssa-tail-merge.c

8011

===================================================================

8012

--- a/src/gcc/tree-ssa-tail-merge.c (.../tags/gcc_4_8_2_release)

8013

+++ b/src/gcc/tree-ssa-tail-merge.c (.../branches/gcc-4_8-branch)

8014

@@ -297,7 +297,8 @@

8015

tree val;

8016

def_operand_p def_p;

8017

8018

- if (gimple_has_side_effects (stmt))

8019

+ if (gimple_has_side_effects (stmt)

8020

+ || gimple_vdef (stmt) != NULL_TREE)

8021

return false;

8022

8023

def_p = SINGLE_SSA_DEF_OPERAND (stmt, SSA_OP_DEF);

8024

Index: gcc/cgraphbuild.c

8025

===================================================================

8026

--- a/src/gcc/cgraphbuild.c (.../tags/gcc_4_8_2_release)

8027

+++ b/src/gcc/cgraphbuild.c (.../branches/gcc-4_8-branch)

8028

@@ -73,7 +73,7 @@

8029

decl = get_base_var (*tp);

8030

if (TREE_CODE (decl) == FUNCTION_DECL)

8031

{

8032

- struct cgraph_node *node = cgraph_get_create_node (decl);

8033

+ struct cgraph_node *node = cgraph_get_create_real_symbol_node (decl);

8034

if (!ctx->only_vars)

8035

cgraph_mark_address_taken_node (node);

8036

ipa_record_reference ((symtab_node)ctx->varpool_node,

8037

@@ -143,7 +143,7 @@

8038

{

8039

struct cgraph_node *per_node;

8040

8041

- per_node = cgraph_get_create_node (DECL_FUNCTION_PERSONALITY (node->symbol.decl));

8042

+ per_node = cgraph_get_create_real_symbol_node (DECL_FUNCTION_PERSONALITY (node->symbol.decl));

8043

ipa_record_reference ((symtab_node)node, (symtab_node)per_node, IPA_REF_ADDR, NULL);

8044

cgraph_mark_address_taken_node (per_node);

8045

}

8046

@@ -218,12 +218,12 @@

8047

/* Mark address taken in STMT. */

8048

8049

static bool

8050

-mark_address (gimple stmt, tree addr, void *data)

8051

+mark_address (gimple stmt, tree addr, tree, void *data)

8052

{

8053

addr = get_base_address (addr);

8054

if (TREE_CODE (addr) == FUNCTION_DECL)

8055

{

8056

- struct cgraph_node *node = cgraph_get_create_node (addr);

8057

+ struct cgraph_node *node = cgraph_get_create_real_symbol_node (addr);

8058

cgraph_mark_address_taken_node (node);

8059

ipa_record_reference ((symtab_node)data,

8060

(symtab_node)node,

8061

@@ -245,7 +245,7 @@

8062

/* Mark load of T. */

8063

8064

static bool

8065

-mark_load (gimple stmt, tree t, void *data)

8066

+mark_load (gimple stmt, tree t, tree, void *data)

8067

{

8068

t = get_base_address (t);

8069

if (t && TREE_CODE (t) == FUNCTION_DECL)

8070

@@ -252,7 +252,7 @@

8071

{

8072

/* ??? This can happen on platforms with descriptors when these are

8073

directly manipulated in the code. Pretend that it's an address. */

8074

- struct cgraph_node *node = cgraph_get_create_node (t);

8075

+ struct cgraph_node *node = cgraph_get_create_real_symbol_node (t);

8076

cgraph_mark_address_taken_node (node);

8077

ipa_record_reference ((symtab_node)data,

8078

(symtab_node)node,

8079

@@ -273,7 +273,7 @@

8080

/* Mark store of T. */

8081

8082

static bool

8083

-mark_store (gimple stmt, tree t, void *data)

8084

+mark_store (gimple stmt, tree t, tree, void *data)

8085

{

8086

t = get_base_address (t);

8087

if (t && TREE_CODE (t) == VAR_DECL

8088

@@ -330,7 +330,7 @@

8089

{

8090

tree fn = gimple_omp_parallel_child_fn (stmt);

8091

ipa_record_reference ((symtab_node)node,

8092

- (symtab_node)cgraph_get_create_node (fn),

8093

+ (symtab_node)cgraph_get_create_real_symbol_node (fn),

8094

IPA_REF_ADDR, stmt);

8095

}

8096

if (gimple_code (stmt) == GIMPLE_OMP_TASK)

8097

@@ -338,12 +338,12 @@

8098

tree fn = gimple_omp_task_child_fn (stmt);

8099

if (fn)

8100

ipa_record_reference ((symtab_node)node,

8101

- (symtab_node) cgraph_get_create_node (fn),

8102

+ (symtab_node) cgraph_get_create_real_symbol_node (fn),

8103

IPA_REF_ADDR, stmt);

8104

fn = gimple_omp_task_copy_fn (stmt);

8105

if (fn)

8106

ipa_record_reference ((symtab_node)node,

8107

- (symtab_node)cgraph_get_create_node (fn),

8108

+ (symtab_node)cgraph_get_create_real_symbol_node (fn),

8109

IPA_REF_ADDR, stmt);

8110

}

8111

}

8112

Index: gcc/tree-ssa-uninit.c

8113

===================================================================

8114

--- a/src/gcc/tree-ssa-uninit.c (.../tags/gcc_4_8_2_release)

8115

+++ b/src/gcc/tree-ssa-uninit.c (.../branches/gcc-4_8-branch)

8116

@@ -36,6 +36,7 @@

8117

#include "hashtab.h"

8118

#include "tree-pass.h"

8119

#include "diagnostic-core.h"

8120

+#include "params.h"

8121

8122

/* This implements the pass that does predicate aware warning on uses of

8123

possibly uninitialized variables. The pass first collects the set of

8124

@@ -246,8 +247,8 @@

8125

8126

/* Computes the control dependence chains (paths of edges)

8127

for DEP_BB up to the dominating basic block BB (the head node of a

8128

- chain should be dominated by it). CD_CHAINS is pointer to a

8129

- dynamic array holding the result chains. CUR_CD_CHAIN is the current

8130

+ chain should be dominated by it). CD_CHAINS is pointer to an

8131

+ array holding the result chains. CUR_CD_CHAIN is the current

8132

chain being computed. *NUM_CHAINS is total number of chains. The

8133

function returns true if the information is successfully computed,

8134

return false if there is no control dependence or not computed. */

8135

@@ -256,7 +257,8 @@

8136

compute_control_dep_chain (basic_block bb, basic_block dep_bb,

8137

vec<edge> *cd_chains,

8138

size_t *num_chains,

8139

- vec<edge> *cur_cd_chain)

8140

+ vec<edge> *cur_cd_chain,

8141

+ int *num_calls)

8142

{

8143

edge_iterator ei;

8144

edge e;

8145

@@ -267,6 +269,10 @@

8146

if (EDGE_COUNT (bb->succs) < 2)

8147

return false;

8148

8149

+ if (*num_calls > PARAM_VALUE (PARAM_UNINIT_CONTROL_DEP_ATTEMPTS))

8150

+ return false;

8151

+ ++*num_calls;

8152

+

8153

/* Could use a set instead. */

8154

cur_chain_len = cur_cd_chain->length ();

8155

if (cur_chain_len > MAX_CHAIN_LEN)

8156

@@ -306,7 +312,7 @@

8157

8158

/* Now check if DEP_BB is indirectly control dependent on BB. */

8159

if (compute_control_dep_chain (cd_bb, dep_bb, cd_chains,

8160

- num_chains, cur_cd_chain))

8161

+ num_chains, cur_cd_chain, num_calls))

8162

{

8163

found_cd_chain = true;

8164

break;

8165

@@ -438,14 +444,12 @@

8166

basic_block use_bb)

8167

{

8168

size_t num_chains = 0, i;

8169

- vec<edge> *dep_chains = 0;

8170

+ int num_calls = 0;

8171

+ vec<edge> dep_chains[MAX_NUM_CHAINS];

8172

vec<edge> cur_chain = vNULL;

8173

bool has_valid_pred = false;

8174

basic_block cd_root = 0;

8175

8176

- typedef vec<edge> vec_edge_heap;

8177

- dep_chains = XCNEWVEC (vec_edge_heap, MAX_NUM_CHAINS);

8178

-

8179

/* First find the closest bb that is control equivalent to PHI_BB

8180

that also dominates USE_BB. */

8181

cd_root = phi_bb;

8182

@@ -458,20 +462,16 @@

8183

break;

8184

}

8185

8186

- compute_control_dep_chain (cd_root, use_bb,

8187

- dep_chains, &num_chains,

8188

- &cur_chain);

8189

+ compute_control_dep_chain (cd_root, use_bb, dep_chains, &num_chains,

8190

+ &cur_chain, &num_calls);

8191

8192

has_valid_pred

8193

- = convert_control_dep_chain_into_preds (dep_chains,

8194

- num_chains,

8195

- preds,

8196

- num_preds);

8197

+ = convert_control_dep_chain_into_preds (dep_chains, num_chains, preds,

8198

+ num_preds);

8199

/* Free individual chain */

8200

cur_chain.release ();

8201

for (i = 0; i < num_chains; i++)

8202

dep_chains[i].release ();

8203

- free (dep_chains);

8204

return has_valid_pred;

8205

}

8206

8207

@@ -539,7 +539,7 @@

8208

size_t *num_preds, gimple phi)

8209

{

8210

size_t num_chains = 0, i, n;

8211

- vec<edge> *dep_chains = 0;

8212

+ vec<edge> dep_chains[MAX_NUM_CHAINS];

8213

vec<edge> cur_chain = vNULL;

8214

vec<edge> def_edges = vNULL;

8215

bool has_valid_pred = false;

8216

@@ -546,9 +546,6 @@

8217

basic_block phi_bb, cd_root = 0;

8218

struct pointer_set_t *visited_phis;

8219

8220

- typedef vec<edge> vec_edge_heap;

8221

- dep_chains = XCNEWVEC (vec_edge_heap, MAX_NUM_CHAINS);

8222

-

8223

phi_bb = gimple_bb (phi);

8224

/* First find the closest dominating bb to be

8225

the control dependence root */

8226

@@ -567,38 +564,33 @@

8227

for (i = 0; i < n; i++)

8228

{

8229

size_t prev_nc, j;

8230

+ int num_calls = 0;

8231

edge opnd_edge;

8232

8233

opnd_edge = def_edges[i];

8234

prev_nc = num_chains;

8235

- compute_control_dep_chain (cd_root, opnd_edge->src,

8236

- dep_chains, &num_chains,

8237

- &cur_chain);

8238

- /* Free individual chain */

8239

- cur_chain.release ();

8240

+ compute_control_dep_chain (cd_root, opnd_edge->src, dep_chains,

8241

+ &num_chains, &cur_chain, &num_calls);

8242

8243

/* Now update the newly added chains with

8244

the phi operand edge: */

8245

if (EDGE_COUNT (opnd_edge->src->succs) > 1)

8246

{

8247

- if (prev_nc == num_chains

8248

- && num_chains < MAX_NUM_CHAINS)

8249

- num_chains++;

8250

+ if (prev_nc == num_chains && num_chains < MAX_NUM_CHAINS)

8251

+ dep_chains[num_chains++] = vNULL;

8252

for (j = prev_nc; j < num_chains; j++)

8253

- {

8254

- dep_chains[j].safe_push (opnd_edge);

8255

- }

8256

+ dep_chains[j].safe_push (opnd_edge);

8257

}

8258

}

8259

8260

+ /* Free individual chain */

8261

+ cur_chain.release ();

8262

+

8263

has_valid_pred

8264

- = convert_control_dep_chain_into_preds (dep_chains,

8265

- num_chains,

8266

- preds,

8267

- num_preds);

8268

+ = convert_control_dep_chain_into_preds (dep_chains, num_chains, preds,

8269

+ num_preds);

8270

for (i = 0; i < num_chains; i++)

8271

dep_chains[i].release ();

8272

- free (dep_chains);

8273

return has_valid_pred;

8274

}

8275

8276

Index: gcc/tree-ssa-loop-niter.c

8277

===================================================================

8278

--- a/src/gcc/tree-ssa-loop-niter.c (.../tags/gcc_4_8_2_release)

8279

+++ b/src/gcc/tree-ssa-loop-niter.c (.../branches/gcc-4_8-branch)

8280

@@ -2075,7 +2075,8 @@

8281

return NULL;

8282

}

8283

8284

- if (gimple_code (stmt) != GIMPLE_ASSIGN)

8285

+ if (gimple_code (stmt) != GIMPLE_ASSIGN

8286

+ || gimple_assign_rhs_class (stmt) == GIMPLE_TERNARY_RHS)

8287

return NULL;

8288

8289

code = gimple_assign_rhs_code (stmt);

8290

@@ -2143,7 +2144,7 @@

8291

{

8292

gimple stmt;

8293

8294

- gcc_assert (is_gimple_min_invariant (base));

8295

+ gcc_checking_assert (is_gimple_min_invariant (base));

8296

8297

if (!x)

8298

return base;

8299

@@ -2152,7 +2153,7 @@

8300

if (gimple_code (stmt) == GIMPLE_PHI)

8301

return base;

8302

8303

- gcc_assert (is_gimple_assign (stmt));

8304

+ gcc_checking_assert (is_gimple_assign (stmt));

8305

8306

/* STMT must be either an assignment of a single SSA name or an

8307

expression involving an SSA name and a constant. Try to fold that

8308

Index: gcc/c-family/c.opt

8309

===================================================================

8310

--- a/src/gcc/c-family/c.opt (.../tags/gcc_4_8_2_release)

8311

+++ b/src/gcc/c-family/c.opt (.../branches/gcc-4_8-branch)

8312

@@ -933,7 +933,7 @@

8313

Recognize GNU-defined keywords

8314

8315

fgnu-runtime

8316

-ObjC ObjC++ Report RejectNegative Var(flag_next_runtime,0) Init(NEXT_OBJC_RUNTIME)

8317

+ObjC ObjC++ LTO Report RejectNegative Var(flag_next_runtime,0) Init(NEXT_OBJC_RUNTIME)

8318

Generate code for GNU runtime environment

8319

8320

fgnu89-inline

8321

@@ -1007,7 +1007,7 @@

8322

C++ ObjC++ Ignore Warn(switch %qs is no longer supported)

8323

8324

fnext-runtime

8325

-ObjC ObjC++ Report RejectNegative Var(flag_next_runtime)

8326

+ObjC ObjC++ LTO Report RejectNegative Var(flag_next_runtime)

8327

Generate code for NeXT (Apple Mac OS X) runtime environment

8328

8329

fnil-receivers

8330

@@ -1025,7 +1025,7 @@

8331

Treat a throw() exception specification as noexcept to improve code size

8332

8333

fobjc-abi-version=

8334

-ObjC ObjC++ Joined Report RejectNegative UInteger Var(flag_objc_abi)

8335

+ObjC ObjC++ LTO Joined Report RejectNegative UInteger Var(flag_objc_abi)

8336

Specify which ABI to use for Objective-C family code and meta-data generation.

8337

8338

; Generate special '- .cxx_construct' and '- .cxx_destruct' methods

8339

@@ -1045,7 +1045,7 @@

8340

Enable Objective-C exception and synchronization syntax

8341

8342

fobjc-gc

8343

-ObjC ObjC++ Var(flag_objc_gc)

8344

+ObjC ObjC++ LTO Var(flag_objc_gc)

8345

Enable garbage collection (GC) in Objective-C/Objective-C++ programs

8346

8347

fobjc-nilcheck

8348

@@ -1105,7 +1105,7 @@

8349

-fno-pretty-templates Do not pretty-print template specializations as the template signature followed by the arguments

8350

8351

freplace-objc-classes

8352

-ObjC ObjC++ Var(flag_replace_objc_classes)

8353

+ObjC ObjC++ LTO Var(flag_replace_objc_classes)

8354

Used in Fix-and-Continue mode to indicate that object files may be swapped in at runtime

8355

8356

frepo

8357

Index: gcc/c-family/c-opts.c

8358

===================================================================

8359

--- a/src/gcc/c-family/c-opts.c (.../tags/gcc_4_8_2_release)

8360

+++ b/src/gcc/c-family/c-opts.c (.../branches/gcc-4_8-branch)

8361

@@ -1258,17 +1258,18 @@

8362

{

8363

size_t i;

8364

8365

- {

8366

- /* Make sure all of the builtins about to be declared have

8367

- BUILTINS_LOCATION has their source_location. */

8368

- source_location builtins_loc = BUILTINS_LOCATION;

8369

- cpp_force_token_locations (parse_in, &builtins_loc);

8370

+ cb_file_change (parse_in,

8371

+ linemap_add (line_table, LC_RENAME, 0,

8372

+ _("<built-in>"), 0));

8373

+ /* Make sure all of the builtins about to be declared have

8374

+ BUILTINS_LOCATION has their source_location. */

8375

+ source_location builtins_loc = BUILTINS_LOCATION;

8376

+ cpp_force_token_locations (parse_in, &builtins_loc);

8377

8378

- cpp_init_builtins (parse_in, flag_hosted);

8379

- c_cpp_builtins (parse_in);

8380

+ cpp_init_builtins (parse_in, flag_hosted);

8381

+ c_cpp_builtins (parse_in);

8382

8383

- cpp_stop_forcing_token_locations (parse_in);

8384

- }

8385

+ cpp_stop_forcing_token_locations (parse_in);

8386

8387

/* We're about to send user input to cpplib, so make it warn for

8388

things that we previously (when we sent it internal definitions)

8389

Index: gcc/c-family/ChangeLog

8390

===================================================================

8391

--- a/src/gcc/c-family/ChangeLog (.../tags/gcc_4_8_2_release)

8392

+++ b/src/gcc/c-family/ChangeLog (.../branches/gcc-4_8-branch)

8393

@@ -1,3 +1,72 @@

8394

+2014-04-10 Jakub Jelinek <jakub@redhat.com>

8395

+

8396

+ Backport from mainline

8397

+ 2014-03-28 Jakub Jelinek <jakub@redhat.com>

8398

+

8399

+ PR c++/60689

8400

+ * c-common.c (add_atomic_size_parameter): When creating new

8401

+ params vector, push the size argument first.

8402

+

8403

+ 2014-03-22 Jakub Jelinek <jakub@redhat.com>

8404

+

8405

+ PR debug/60603

8406

+ * c-opts.c (c_finish_options): Restore cb_file_change call to

8407

+ <built-in>.

8408

+

8409

+ 2014-03-13 Jakub Jelinek <jakub@redhat.com>

8410

+

8411

+ PR middle-end/36282

8412

+ * c-pragma.c (apply_pragma_weak): Only look at

8413

+ TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)) if

8414

+ DECL_ASSEMBLER_NAME_SET_P (decl).

8415

+ (maybe_apply_pending_pragma_weaks): Exit early if

8416

+ vec_safe_is_empty (pending_weaks) rather than only when

8417

+ !pending_weaks.

8418

+ (maybe_apply_pragma_weak): Likewise. If !DECL_ASSEMBLER_NAME_SET_P,

8419

+ set assembler name back to NULL afterwards.

8420

+

8421

+2014-04-07 Dominique d'Humieres <dominiq@lps.ens.fr>

8422

+

8423

+ Backport from mainline

8424

+ 2013-09-14 Iain Sandoe <iains@gcc.gnu.org>

8425

+

8426

+ PR target/48094

8427

+ * c.opt (fgnu-runtime, fnext-runtime, fobjc-abi-version,

8428

+ fobjc-gc, freplace-objc-classes): Accept for LTO.

8429

+

8430

+2014-03-06 Jakub Jelinek <jakub@redhat.com>

8431

+

8432

+ Backport from mainline

8433

+ 2014-02-19 Jakub Jelinek <jakub@redhat.com>

8434

+

8435

+ PR c/37743

8436

+ * c-common.c (c_common_nodes_and_builtins): When initializing

8437

+ c_uint{16,32,64}_type_node, also set corresponding

8438

+ uint{16,32,64}_type_node to the same value.

8439

+

8440

+ 2014-02-12 Jakub Jelinek <jakub@redhat.com>

8441

+

8442

+ PR c/60101

8443

+ * c-common.c (merge_tlist): If copy is true, call new_tlist,

8444

+ if false, add ADD itself, rather than vice versa.

8445

+ (verify_tree): For COND_EXPR, don't call merge_tlist with non-zero

8446

+ copy. For SAVE_EXPR, only call merge_tlist once.

8447

+

8448

+2013-11-29 Jakub Jelinek <jakub@redhat.com>

8449

+

8450

+ PR c/59280

8451

+ * c-common.c (get_priority): If TREE_VALUE (args) is IDENTIFIER_NODE,

8452

+ goto invalid. If it is error_mark_node, don't issue further

8453

+ diagnostics.

8454

+

8455

+2013-11-04 Marek Polacek <polacek@redhat.com>

8456

+

8457

+ Backport from mainline

8458

+ 2013-11-04 Marek Polacek <polacek@redhat.com>

8459

+

8460

+ PR c++/58979

8461

+ * c-common.c (invalid_indirection_error): Handle RO_ARROW_STAR case.

8462

+

8463

2013-10-16 Release Manager

8464

8465

* GCC 4.8.2 released.

8466

Index: gcc/c-family/c-common.c

8467

===================================================================

8468

--- a/src/gcc/c-family/c-common.c (.../tags/gcc_4_8_2_release)

8469

+++ b/src/gcc/c-family/c-common.c (.../branches/gcc-4_8-branch)

8470

@@ -2894,7 +2894,7 @@

8471

}

8472

if (!found)

8473

{

8474

- *end = copy ? add : new_tlist (NULL, add->expr, add->writer);

8475

+ *end = copy ? new_tlist (NULL, add->expr, add->writer) : add;

8476

end = &(*end)->next;

8477

*end = 0;

8478

}

8479

@@ -3052,7 +3052,7 @@

8480

verify_tree (TREE_OPERAND (x, 0), &tmp_before, &tmp_list2, NULL_TREE);

8481

warn_for_collisions (tmp_list2);

8482

merge_tlist (pbefore_sp, tmp_before, 0);

8483

- merge_tlist (pbefore_sp, tmp_list2, 1);

8484

+ merge_tlist (pbefore_sp, tmp_list2, 0);

8485

8486

tmp_list3 = tmp_nosp = 0;

8487

verify_tree (TREE_OPERAND (x, 1), &tmp_list3, &tmp_nosp, NULL_TREE);

8488

@@ -3156,12 +3156,7 @@

8489

warn_for_collisions (tmp_nosp);

8490

8491

tmp_list3 = 0;

8492

- while (tmp_nosp)

8493

- {

8494

- struct tlist *t = tmp_nosp;

8495

- tmp_nosp = t->next;

8496

- merge_tlist (&tmp_list3, t, 0);

8497

- }

8498

+ merge_tlist (&tmp_list3, tmp_nosp, 0);

8499

t->cache_before_sp = tmp_before;

8500

t->cache_after_sp = tmp_list3;

8501

}

8502

@@ -5511,13 +5506,13 @@

8503

uint8_type_node =

8504

TREE_TYPE (identifier_global_value (c_get_ident (UINT8_TYPE)));

8505

if (UINT16_TYPE)

8506

- c_uint16_type_node =

8507

+ c_uint16_type_node = uint16_type_node =

8508

TREE_TYPE (identifier_global_value (c_get_ident (UINT16_TYPE)));

8509

if (UINT32_TYPE)

8510

- c_uint32_type_node =

8511

+ c_uint32_type_node = uint32_type_node =

8512

TREE_TYPE (identifier_global_value (c_get_ident (UINT32_TYPE)));

8513

if (UINT64_TYPE)

8514

- c_uint64_type_node =

8515

+ c_uint64_type_node = uint64_type_node =

8516

TREE_TYPE (identifier_global_value (c_get_ident (UINT64_TYPE)));

8517

if (INT_LEAST8_TYPE)

8518

int_least8_type_node =

8519

@@ -6917,6 +6912,10 @@

8520

}

8521

8522

arg = TREE_VALUE (args);

8523

+ if (TREE_CODE (arg) == IDENTIFIER_NODE)

8524

+ goto invalid;

8525

+ if (arg == error_mark_node)

8526

+ return DEFAULT_INIT_PRIORITY;

8527

arg = default_conversion (arg);

8528

if (!host_integerp (arg, /*pos=*/0)

8529

|| !INTEGRAL_TYPE_P (TREE_TYPE (arg)))

8530

@@ -9763,6 +9762,11 @@

8531

"invalid type argument of %<->%> (have %qT)",

8532

type);

8533

break;

8534

+ case RO_ARROW_STAR:

8535

+ error_at (loc,

8536

+ "invalid type argument of %<->*%> (have %qT)",

8537

+ type);

8538

+ break;

8539

case RO_IMPLICIT_CONVERSION:

8540

error_at (loc,

8541

"invalid type argument of implicit conversion (have %qT)",

8542

@@ -10198,6 +10202,7 @@

8543

8544

len = params->length ();

8545

vec_alloc (v, len + 1);

8546

+ v->quick_push (build_int_cst (size_type_node, n));

8547

for (z = 0; z < len; z++)

8548

v->quick_push ((*params)[z]);

8549

f = build_function_call_vec (loc, function, v, NULL);

8550

Index: gcc/c-family/c-pragma.c

8551

===================================================================

8552

--- a/src/gcc/c-family/c-pragma.c (.../tags/gcc_4_8_2_release)

8553

+++ b/src/gcc/c-family/c-pragma.c (.../branches/gcc-4_8-branch)

8554

@@ -259,6 +259,7 @@

8555

8556

if (SUPPORTS_WEAK && DECL_EXTERNAL (decl) && TREE_USED (decl)

8557

&& !DECL_WEAK (decl) /* Don't complain about a redundant #pragma. */

8558

+ && DECL_ASSEMBLER_NAME_SET_P (decl)

8559

&& TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))

8560

warning (OPT_Wpragmas, "applying #pragma weak %q+D after first use "

8561

"results in unspecified behavior", decl);

8562

@@ -276,7 +277,7 @@

8563

/* Avoid asking for DECL_ASSEMBLER_NAME when it's not needed. */

8564

8565

/* No weak symbols pending, take the short-cut. */

8566

- if (!pending_weaks)

8567

+ if (vec_safe_is_empty (pending_weaks))

8568

return;

8569

/* If it's not visible outside this file, it doesn't matter whether

8570

it's weak. */

8571

@@ -288,7 +289,13 @@

8572

if (TREE_CODE (decl) != FUNCTION_DECL && TREE_CODE (decl) != VAR_DECL)

8573

return;

8574

8575

- id = DECL_ASSEMBLER_NAME (decl);

8576

+ if (DECL_ASSEMBLER_NAME_SET_P (decl))

8577

+ id = DECL_ASSEMBLER_NAME (decl);

8578

+ else

8579

+ {

8580

+ id = DECL_ASSEMBLER_NAME (decl);

8581

+ SET_DECL_ASSEMBLER_NAME (decl, NULL_TREE);

8582

+ }

8583

8584

FOR_EACH_VEC_ELT (*pending_weaks, i, pe)

8585

if (id == pe->name)

8586

@@ -309,7 +316,7 @@

8587

pending_weak *pe;

8588

symtab_node target;

8589

8590

- if (!pending_weaks)

8591

+ if (vec_safe_is_empty (pending_weaks))

8592

return;

8593

8594

FOR_EACH_VEC_ELT (*pending_weaks, i, pe)

8595

Index: gcc/c/c-typeck.c

8596

===================================================================

8597

--- a/src/gcc/c/c-typeck.c (.../tags/gcc_4_8_2_release)

8598

+++ b/src/gcc/c/c-typeck.c (.../branches/gcc-4_8-branch)

8599

@@ -2666,7 +2666,7 @@

8600

vec_alloc (v, list_length (params));

8601

for (; params; params = TREE_CHAIN (params))

8602

v->quick_push (TREE_VALUE (params));

8603

- ret = build_function_call_vec (loc, function, v, NULL);

8604

+ ret = c_build_function_call_vec (loc, function, v, NULL);

8605

vec_free (v);

8606

return ret;

8607

}

8608

@@ -2705,14 +2705,6 @@

8609

/* Convert anything with function type to a pointer-to-function. */

8610

if (TREE_CODE (function) == FUNCTION_DECL)

8611

{

8612

- /* Implement type-directed function overloading for builtins.

8613

- resolve_overloaded_builtin and targetm.resolve_overloaded_builtin

8614

- handle all the type checking. The result is a complete expression

8615

- that implements this function call. */

8616

- tem = resolve_overloaded_builtin (loc, function, params);

8617

- if (tem)

8618

- return tem;

8619

-

8620

name = DECL_NAME (function);

8621

8622

if (flag_tm)

8623

@@ -2863,6 +2855,30 @@

8624

}

8625

return require_complete_type (result);

8626

}

8627

+

8628

+/* Like build_function_call_vec, but call also resolve_overloaded_builtin. */

8629

+

8630

+tree

8631

+c_build_function_call_vec (location_t loc, tree function,

8632

+ vec<tree, va_gc> *params,

8633

+ vec<tree, va_gc> *origtypes)

8634

+{

8635

+ /* Strip NON_LVALUE_EXPRs, etc., since we aren't using as an lvalue. */

8636

+ STRIP_TYPE_NOPS (function);

8637

+

8638

+ /* Convert anything with function type to a pointer-to-function. */

8639

+ if (TREE_CODE (function) == FUNCTION_DECL)

8640

+ {

8641

+ /* Implement type-directed function overloading for builtins.

8642

+ resolve_overloaded_builtin and targetm.resolve_overloaded_builtin

8643

+ handle all the type checking. The result is a complete expression

8644

+ that implements this function call. */

8645

+ tree tem = resolve_overloaded_builtin (loc, function, params);

8646

+ if (tem)

8647

+ return tem;

8648

+ }

8649

+ return build_function_call_vec (loc, function, params, origtypes);

8650

+}

8651

8652

/* Convert the argument expressions in the vector VALUES

8653

to the types in the list TYPELIST.

8654

@@ -3629,7 +3645,8 @@

8655

/* Report invalid types. */

8656

8657

if (typecode != POINTER_TYPE && typecode != FIXED_POINT_TYPE

8658

- && typecode != INTEGER_TYPE && typecode != REAL_TYPE)

8659

+ && typecode != INTEGER_TYPE && typecode != REAL_TYPE

8660

+ && typecode != VECTOR_TYPE)

8661

{

8662

if (code == PREINCREMENT_EXPR || code == POSTINCREMENT_EXPR)

8663

error_at (location, "wrong type argument to increment");

8664

@@ -3694,7 +3711,9 @@

8665

}

8666

else

8667

{

8668

- inc = integer_one_node;

8669

+ inc = (TREE_CODE (argtype) == VECTOR_TYPE

8670

+ ? build_one_cst (argtype)

8671

+ : integer_one_node);

8672

inc = convert (argtype, inc);

8673

}

8674

8675

@@ -4331,8 +4350,10 @@

8676

{

8677

if (int_operands)

8678

{

8679

- op1 = remove_c_maybe_const_expr (op1);

8680

- op2 = remove_c_maybe_const_expr (op2);

8681

+ /* Use c_fully_fold here, since C_MAYBE_CONST_EXPR might be

8682

+ nested inside of the expression. */

8683

+ op1 = c_fully_fold (op1, false, NULL);

8684

+ op2 = c_fully_fold (op2, false, NULL);

8685

}

8686

ret = build3 (COND_EXPR, result_type, ifexp, op1, op2);

8687

if (int_operands)

8688

@@ -10618,7 +10639,8 @@

8689

"%qE has invalid type for %<reduction%>", t);

8690

remove = true;

8691

}

8692

- else if (FLOAT_TYPE_P (TREE_TYPE (t)))

8693

+ else if (FLOAT_TYPE_P (TREE_TYPE (t))

8694

+ || TREE_CODE (TREE_TYPE (t)) == COMPLEX_TYPE)

8695

{

8696

enum tree_code r_code = OMP_CLAUSE_REDUCTION_CODE (c);

8697

const char *r_name = NULL;

8698

@@ -10628,8 +10650,14 @@

8699

case PLUS_EXPR:

8700

case MULT_EXPR:

8701

case MINUS_EXPR:

8702

+ break;

8703

case MIN_EXPR:

8704

+ if (TREE_CODE (TREE_TYPE (t)) == COMPLEX_TYPE)

8705

+ r_name = "min";

8706

+ break;

8707

case MAX_EXPR:

8708

+ if (TREE_CODE (TREE_TYPE (t)) == COMPLEX_TYPE)

8709

+ r_name = "max";

8710

break;

8711

case BIT_AND_EXPR:

8712

r_name = "&";

8713

@@ -10641,10 +10669,12 @@

8714

r_name = "|";

8715

break;

8716

case TRUTH_ANDIF_EXPR:

8717

- r_name = "&&";

8718

+ if (FLOAT_TYPE_P (TREE_TYPE (t)))

8719

+ r_name = "&&";

8720

break;

8721

case TRUTH_ORIF_EXPR:

8722

- r_name = "||";

8723

+ if (FLOAT_TYPE_P (TREE_TYPE (t)))

8724

+ r_name = "||";

8725

break;

8726

default:

8727

gcc_unreachable ();

8728

Index: gcc/c/c-tree.h

8729

===================================================================

8730

--- a/src/gcc/c/c-tree.h (.../tags/gcc_4_8_2_release)

8731

+++ b/src/gcc/c/c-tree.h (.../branches/gcc-4_8-branch)

8732

@@ -640,6 +640,8 @@

8733

extern tree c_finish_omp_clauses (tree);

8734

extern tree c_build_va_arg (location_t, tree, tree);

8735

extern tree c_finish_transaction (location_t, tree, int);

8736

+extern tree c_build_function_call_vec (location_t, tree, vec<tree, va_gc> *,

8737

+ vec<tree, va_gc> *);

8738

8739

/* Set to 0 at beginning of a function definition, set to 1 if

8740

a return statement that specifies a return value is seen. */

8741

Index: gcc/c/ChangeLog

8742

===================================================================

8743

--- a/src/gcc/c/ChangeLog (.../tags/gcc_4_8_2_release)

8744

+++ b/src/gcc/c/ChangeLog (.../branches/gcc-4_8-branch)

8745

@@ -1,3 +1,49 @@

8746

+2014-04-10 Jakub Jelinek <jakub@redhat.com>

8747

+

8748

+ Backport from mainline

8749

+ 2014-03-28 Jakub Jelinek <jakub@redhat.com>

8750

+

8751

+ PR c++/60689

8752

+ * c-tree.h (c_build_function_call_vec): New prototype.

8753

+ * c-typeck.c (build_function_call_vec): Don't call

8754

+ resolve_overloaded_builtin here.

8755

+ (c_build_function_call_vec): New wrapper function around

8756

+ build_function_call_vec. Call resolve_overloaded_builtin here.

8757

+ (convert_lvalue_to_rvalue, build_function_call, build_atomic_assign):

8758

+ Call c_build_function_call_vec instead of build_function_call_vec.

8759

+ * c-parser.c (c_parser_postfix_expression_after_primary): Likewise.

8760

+ * c-decl.c (finish_decl): Likewise.

8761

+

8762

+2014-01-23 Jakub Jelinek <jakub@redhat.com>

8763

+

8764

+ PR middle-end/58809

8765

+ * c-typeck.c (c_finish_omp_clause): Reject MIN_EXPR, MAX_EXPR,

8766

+ BIT_AND_EXPR, BIT_IOR_EXPR and BIT_XOR_EXPR on COMPLEX_TYPEs.

8767

+

8768

+2014-01-22 Marek Polacek <polacek@redhat.com>

8769

+

8770

+ Backport from mainline

8771

+ 2014-01-22 Marek Polacek <polacek@redhat.com>

8772

+

8773

+ PR c/59891

8774

+ * c-typeck.c (build_conditional_expr): Call c_fully_fold instead

8775

+ of remove_c_maybe_const_expr on op1 and op2.

8776

+

8777

+2013-12-03 Marek Polacek <polacek@redhat.com>

8778

+

8779

+ Backport from mainline

8780

+ 2013-12-03 Marek Polacek <polacek@redhat.com>

8781

+

8782

+ PR c/59351

8783

+ * c-decl.c (build_compound_literal): Allow compound literals with

8784

+ empty initial value.

8785

+

8786

+2013-11-27 Tom de Vries <tom@codesourcery.com>

8787

+ Marc Glisse <marc.glisse@inria.fr>

8788

+

8789

+ PR c++/59032

8790

+ * c-typeck.c (build_unary_op): Allow vector increment and decrement.

8791

+

8792

2013-10-16 Release Manager

8793

8794

* GCC 4.8.2 released.

8795

Index: gcc/c/c-decl.c

8796

===================================================================

8797

--- a/src/gcc/c/c-decl.c (.../tags/gcc_4_8_2_release)

8798

+++ b/src/gcc/c/c-decl.c (.../branches/gcc-4_8-branch)

8799

@@ -4507,8 +4507,8 @@

8800

cleanup = build_unary_op (input_location, ADDR_EXPR, decl, 0);

8801

vec_alloc (v, 1);

8802

v->quick_push (cleanup);

8803

- cleanup = build_function_call_vec (DECL_SOURCE_LOCATION (decl),

8804

- cleanup_decl, v, NULL);

8805

+ cleanup = c_build_function_call_vec (DECL_SOURCE_LOCATION (decl),

8806

+ cleanup_decl, v, NULL);

8807

vec_free (v);

8808

8809

/* Don't warn about decl unused; the cleanup uses it. */

8810

@@ -4632,7 +4632,9 @@

8811

{

8812

int failure = complete_array_type (&TREE_TYPE (decl),

8813

DECL_INITIAL (decl), true);

8814

- gcc_assert (!failure);

8815

+ /* If complete_array_type returns 3, it means that the

8816

+ initial value of the compound literal is empty. Allow it. */

8817

+ gcc_assert (failure == 0 || failure == 3);

8818

8819

type = TREE_TYPE (decl);

8820

TREE_TYPE (DECL_INITIAL (decl)) = type;

8821

Index: gcc/c/c-parser.c

8822

===================================================================

8823

--- a/src/gcc/c/c-parser.c (.../tags/gcc_4_8_2_release)

8824

+++ b/src/gcc/c/c-parser.c (.../branches/gcc-4_8-branch)

8825

@@ -6904,8 +6904,8 @@

8826

sizeof_ptr_memacc_comptypes);

8827

/* FIXME diagnostics: Ideally we want the FUNCNAME, not the

8828

"(" after the FUNCNAME, which is what we have now. */

8829

- expr.value = build_function_call_vec (op_loc, expr.value, exprlist,

8830

- origtypes);

8831

+ expr.value = c_build_function_call_vec (op_loc, expr.value, exprlist,

8832

+ origtypes);

8833

expr.original_code = ERROR_MARK;

8834

if (TREE_CODE (expr.value) == INTEGER_CST

8835

&& TREE_CODE (orig_expr.value) == FUNCTION_DECL

8836

Index: gcc/cgraph.c

8837

===================================================================

8838

--- a/src/gcc/cgraph.c (.../tags/gcc_4_8_2_release)

8839

+++ b/src/gcc/cgraph.c (.../branches/gcc-4_8-branch)

8840

@@ -2596,4 +2596,47 @@

8841

FOR_EACH_FUNCTION (node)

8842

verify_cgraph_node (node);

8843

}

8844

+

8845

+/* Create external decl node for DECL.

8846

+ The difference i nbetween cgraph_get_create_node and

8847

+ cgraph_get_create_real_symbol_node is that cgraph_get_create_node

8848

+ may return inline clone, while cgraph_get_create_real_symbol_node

8849

+ will create a new node in this case.

8850

+ FIXME: This function should be removed once clones are put out of decl

8851

+ hash. */

8852

+

8853

+struct cgraph_node *

8854

+cgraph_get_create_real_symbol_node (tree decl)

8855

+{

8856

+ struct cgraph_node *first_clone = cgraph_get_node (decl);

8857

+ struct cgraph_node *node;

8858

+ /* create symbol table node. even if inline clone exists, we can not take

8859

+ it as a target of non-inlined call. */

8860

+ node = cgraph_get_node (decl);

8861

+ if (node && !node->global.inlined_to)

8862

+ return node;

8863

+

8864

+ node = cgraph_create_node (decl);

8865

+

8866

+ /* ok, we previously inlined the function, then removed the offline copy and

8867

+ now we want it back for external call. this can happen when devirtualizing

8868

+ while inlining function called once that happens after extern inlined and

8869

+ virtuals are already removed. in this case introduce the external node

8870

+ and make it available for call. */

8871

+ if (first_clone)

8872

+ {

8873

+ first_clone->clone_of = node;

8874

+ node->clones = first_clone;

8875

+ symtab_prevail_in_asm_name_hash ((symtab_node) node);

8876

+ symtab_insert_node_to_hashtable ((symtab_node) node);

8877

+ if (dump_file)

8878

+ fprintf (dump_file, "Introduced new external node "

8879

+ "(%s/%i) and turned into root of the clone tree.\n",

8880

+ xstrdup (cgraph_node_name (node)), node->uid);

8881

+ }

8882

+ else if (dump_file)

8883

+ fprintf (dump_file, "Introduced new external node "

8884

+ "(%s/%i).\n", xstrdup (cgraph_node_name (node)), node->uid);

8885

+ return node;

8886

+}

8887

#include "gt-cgraph.h"

8888

Index: gcc/cgraph.h

8889

===================================================================

8890

--- a/src/gcc/cgraph.h (.../tags/gcc_4_8_2_release)

8891

+++ b/src/gcc/cgraph.h (.../branches/gcc-4_8-branch)

8892

@@ -575,6 +575,7 @@

8893

struct cgraph_node * cgraph_create_node (tree);

8894

struct cgraph_node * cgraph_create_empty_node (void);

8895

struct cgraph_node * cgraph_get_create_node (tree);

8896

+struct cgraph_node * cgraph_get_create_real_symbol_node (tree);

8897

struct cgraph_node * cgraph_same_body_alias (struct cgraph_node *, tree, tree);

8898

struct cgraph_node * cgraph_add_thunk (struct cgraph_node *, tree, tree, bool, HOST_WIDE_INT,

8899

HOST_WIDE_INT, tree, tree);

8900

Index: gcc/optabs.c

8901

===================================================================

8902

--- a/src/gcc/optabs.c (.../tags/gcc_4_8_2_release)

8903

+++ b/src/gcc/optabs.c (.../branches/gcc-4_8-branch)

8904

@@ -3376,7 +3376,8 @@

8905

{

8906

rtx temp;

8907

8908

- if (! flag_trapv)

8909

+ if (GET_MODE_CLASS (mode) != MODE_INT

8910

+ || ! flag_trapv)

8911

result_unsignedp = 1;

8912

8913

/* First try to do it with a special abs instruction. */

8914

@@ -3399,7 +3400,8 @@

8915

{

8916

rtx last = get_last_insn ();

8917

8918

- temp = expand_unop (mode, neg_optab, op0, NULL_RTX, 0);

8919

+ temp = expand_unop (mode, result_unsignedp ? neg_optab : negv_optab,

8920

+ op0, NULL_RTX, 0);

8921

if (temp != 0)

8922

temp = expand_binop (mode, smax_optab, op0, temp, target, 0,

8923

OPTAB_WIDEN);

8924

@@ -3441,7 +3443,8 @@

8925

{

8926

rtx temp, op1;

8927

8928

- if (! flag_trapv)

8929

+ if (GET_MODE_CLASS (mode) != MODE_INT

8930

+ || ! flag_trapv)

8931

result_unsignedp = 1;

8932

8933

temp = expand_abs_nojump (mode, op0, target, result_unsignedp);

8934

@@ -4558,8 +4561,11 @@

8935

if (!COMPARISON_P (comparison))

8936

return NULL_RTX;

8937

8938

+ /* State variables we need to save and restore if cmove can't be used. */

8939

+ int save_pending_stack_adjust = pending_stack_adjust;

8940

+ int save_stack_pointer_delta = stack_pointer_delta;

8941

+ last = get_last_insn ();

8942

do_pending_stack_adjust ();

8943

- last = get_last_insn ();

8944

prepare_cmp_insn (XEXP (comparison, 0), XEXP (comparison, 1),

8945

GET_CODE (comparison), NULL_RTX, unsignedp, OPTAB_WIDEN,

8946

&comparison, &cmode);

8947

@@ -4579,6 +4585,8 @@

8948

}

8949

}

8950

delete_insns_since (last);

8951

+ pending_stack_adjust = save_pending_stack_adjust;

8952

+ stack_pointer_delta = save_stack_pointer_delta;

8953

return NULL_RTX;

8954

}

8955

8956

@@ -6233,7 +6241,7 @@

8957

8958

/* If the optabs changed, record it. */

8959

if (memcmp (tmp_optabs, this_target_optabs, sizeof (struct target_optabs)))

8960

- TREE_OPTIMIZATION_OPTABS (optnode) = (unsigned char *) tmp_optabs;

8961

+ TREE_OPTIMIZATION_OPTABS (optnode) = tmp_optabs;

8962

else

8963

{

8964

TREE_OPTIMIZATION_OPTABS (optnode) = NULL;

8965

@@ -7035,8 +7043,7 @@

8966

8967

create_output_operand (&ops[0], target, mode);

8968

create_fixed_operand (&ops[1], mem);

8969

- /* VAL may have been promoted to a wider mode. Shrink it if so. */

8970

- create_convert_operand_to (&ops[2], val, mode, true);

8971

+ create_input_operand (&ops[2], val, mode);

8972

create_integer_operand (&ops[3], model);

8973

if (maybe_expand_insn (icode, 4, ops))

8974

return ops[0].value;

8975

@@ -7075,8 +7082,7 @@

8976

struct expand_operand ops[3];

8977

create_output_operand (&ops[0], target, mode);

8978

create_fixed_operand (&ops[1], mem);

8979

- /* VAL may have been promoted to a wider mode. Shrink it if so. */

8980

- create_convert_operand_to (&ops[2], val, mode, true);

8981

+ create_input_operand (&ops[2], val, mode);

8982

if (maybe_expand_insn (icode, 3, ops))

8983

return ops[0].value;

8984

}

8985

@@ -7118,8 +7124,6 @@

8986

{

8987

if (!target || !register_operand (target, mode))

8988

target = gen_reg_rtx (mode);

8989

- if (GET_MODE (val) != VOIDmode && GET_MODE (val) != mode)

8990

- val = convert_modes (mode, GET_MODE (val), val, 1);

8991

if (expand_compare_and_swap_loop (mem, target, val, NULL_RTX))

8992

return target;

8993

}

8994

@@ -7331,8 +7335,8 @@

8995

create_output_operand (&ops[0], target_bool, bool_mode);

8996

create_output_operand (&ops[1], target_oval, mode);

8997

create_fixed_operand (&ops[2], mem);

8998

- create_convert_operand_to (&ops[3], expected, mode, true);

8999

- create_convert_operand_to (&ops[4], desired, mode, true);

9000

+ create_input_operand (&ops[3], expected, mode);

9001

+ create_input_operand (&ops[4], desired, mode);

9002

create_integer_operand (&ops[5], is_weak);

9003

create_integer_operand (&ops[6], succ_model);

9004

create_integer_operand (&ops[7], fail_model);

9005

@@ -7353,8 +7357,8 @@

9006

9007

create_output_operand (&ops[0], target_oval, mode);

9008

create_fixed_operand (&ops[1], mem);

9009

- create_convert_operand_to (&ops[2], expected, mode, true);

9010

- create_convert_operand_to (&ops[3], desired, mode, true);

9011

+ create_input_operand (&ops[2], expected, mode);

9012

+ create_input_operand (&ops[3], desired, mode);

9013

if (!maybe_expand_insn (icode, 4, ops))

9014

return false;

9015

9016

Index: gcc/DATESTAMP

9017

===================================================================

9018

--- a/src/gcc/DATESTAMP (.../tags/gcc_4_8_2_release)

9019

+++ b/src/gcc/DATESTAMP (.../branches/gcc-4_8-branch)

9020

@@ -1 +1 @@

9021

-20131016

9022

+20140505

9023

Index: gcc/value-prof.c

9024

===================================================================

9025

--- a/src/gcc/value-prof.c (.../tags/gcc_4_8_2_release)

9026

+++ b/src/gcc/value-prof.c (.../branches/gcc-4_8-branch)

9027

@@ -1270,8 +1270,7 @@

9028

9029

/* Build an EH edge for the direct call if necessary. */

9030

lp_nr = lookup_stmt_eh_lp (icall_stmt);

9031

- if (lp_nr != 0

9032

- && stmt_could_throw_p (dcall_stmt))

9033

+ if (lp_nr > 0 && stmt_could_throw_p (dcall_stmt))

9034

{

9035

edge e_eh, e;

9036

edge_iterator ei;

9037

Index: gcc/tree.c

9038

===================================================================

9039

--- a/src/gcc/tree.c (.../tags/gcc_4_8_2_release)

9040

+++ b/src/gcc/tree.c (.../branches/gcc-4_8-branch)

9041

@@ -1619,6 +1619,60 @@

9042

}

9043

}

9044

9045

+/* Return an integer of type TYPE containing all 1's in as much precision as

9046

+ it contains, or a complex or vector whose subparts are such integers. */

9047

+

9048

+tree

9049

+build_all_ones_cst (tree type)

9050

+{

9051

+ if (TREE_CODE (type) == COMPLEX_TYPE)

9052

+ {

9053

+ tree scalar = build_all_ones_cst (TREE_TYPE (type));

9054

+ return build_complex (type, scalar, scalar);

9055

+ }

9056

+ else

9057

+ return build_minus_one_cst (type);

9058

+}

9059

+

9060

+/* Return a constant of arithmetic type TYPE which is the

9061

+ opposite of the multiplicative identity of the set TYPE. */

9062

+

9063

+tree

9064

+build_minus_one_cst (tree type)

9065

+{

9066

+ switch (TREE_CODE (type))

9067

+ {

9068

+ case INTEGER_TYPE: case ENUMERAL_TYPE: case BOOLEAN_TYPE:

9069

+ case POINTER_TYPE: case REFERENCE_TYPE:

9070

+ case OFFSET_TYPE:

9071

+ return build_int_cst (type, -1);

9072

+

9073

+ case REAL_TYPE:

9074

+ return build_real (type, dconstm1);

9075

+

9076

+ case FIXED_POINT_TYPE:

9077

+ /* We can only generate 1 for accum types. */

9078

+ gcc_assert (ALL_SCALAR_ACCUM_MODE_P (TYPE_MODE (type)));

9079

+ return build_fixed (type, fixed_from_double_int (double_int_minus_one,

9080

+ TYPE_MODE (type)));

9081

+

9082

+ case VECTOR_TYPE:

9083

+ {

9084

+ tree scalar = build_minus_one_cst (TREE_TYPE (type));

9085

+

9086

+ return build_vector_from_val (type, scalar);

9087

+ }

9088

+

9089

+ case COMPLEX_TYPE:

9090

+ return build_complex (type,

9091

+ build_minus_one_cst (TREE_TYPE (type)),

9092

+ build_zero_cst (TREE_TYPE (type)));

9093

+

9094

+ default:

9095

+ gcc_unreachable ();

9096

+ }

9097

+}

9098

+

9099

/* Build 0 constant of type TYPE. This is used by constructor folding

9100

and thus the constant should be represented in memory by

9101

zero(es). */

9102

Index: gcc/tree.h

9103

===================================================================

9104

--- a/src/gcc/tree.h (.../tags/gcc_4_8_2_release)

9105

+++ b/src/gcc/tree.h (.../branches/gcc-4_8-branch)

9106

@@ -3589,7 +3589,7 @@

9107

9108

/* Target optabs for this set of optimization options. This is of

9109

type `struct target_optabs *'. */

9110

- unsigned char *GTY ((atomic)) optabs;

9111

+ void *GTY ((atomic)) optabs;

9112

9113

/* The value of this_target_optabs against which the optabs above were

9114

generated. */

9115

@@ -4760,6 +4760,8 @@

9116

extern tree build_real_from_int_cst (tree, const_tree);

9117

extern tree build_complex (tree, tree, tree);

9118

extern tree build_one_cst (tree);

9119

+extern tree build_minus_one_cst (tree);

9120

+extern tree build_all_ones_cst (tree);

9121

extern tree build_zero_cst (tree);

9122

extern tree build_string (int, const char *);

9123

extern tree build_tree_list_stat (tree, tree MEM_STAT_DECL);

9124

@@ -5854,6 +5856,7 @@

9125

extern tree fold_builtin_fputs (location_t, tree, tree, bool, bool, tree);

9126

extern tree fold_builtin_strcpy (location_t, tree, tree, tree, tree);

9127

extern tree fold_builtin_strncpy (location_t, tree, tree, tree, tree, tree);

9128

+extern tree fold_builtin_strcat (location_t, tree, tree, tree);

9129

extern tree fold_builtin_memory_chk (location_t, tree, tree, tree, tree, tree, tree, bool,

9130

enum built_in_function);

9131

extern tree fold_builtin_stxcpy_chk (location_t, tree, tree, tree, tree, tree, bool,

9132

@@ -6545,4 +6548,18 @@

9133

&& builtin_info.implicit_p[uns_fncode]);

9134

}

9135

9136

+/* Return pointer to optimization flags of FNDECL. */

9137

+static inline struct cl_optimization *

9138

+opts_for_fn (const_tree fndecl)

9139

+{

9140

+ tree fn_opts = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);

9141

+ if (fn_opts == NULL_TREE)

9142

+ fn_opts = optimization_default_node;

9143

+ return TREE_OPTIMIZATION (fn_opts);

9144

+}

9145

+

9146

+/* opt flag for function FNDECL, e.g. opts_for_fn (fndecl, optimize) is

9147

+ the optimization level of function fndecl. */

9148

+#define opt_for_fn(fndecl, opt) (opts_for_fn (fndecl)->x_##opt)

9149

+

9150

#endif /* GCC_TREE_H */

9151

Index: gcc/ipa-cp.c

9152

===================================================================

9153

--- a/src/gcc/ipa-cp.c (.../tags/gcc_4_8_2_release)

9154

+++ b/src/gcc/ipa-cp.c (.../branches/gcc-4_8-branch)

9155

@@ -444,6 +444,9 @@

9156

reason = "not a tree_versionable_function";

9157

else if (cgraph_function_body_availability (node) <= AVAIL_OVERWRITABLE)

9158

reason = "insufficient body availability";

9159

+ else if (!opt_for_fn (node->symbol.decl, optimize)

9160

+ || !opt_for_fn (node->symbol.decl, flag_ipa_cp))

9161

+ reason = "non-optimized function";

9162

9163

if (reason && dump_file && !node->alias && !node->thunk.thunk_p)

9164

fprintf (dump_file, "Function %s/%i is not versionable, reason: %s.\n",

9165

@@ -1455,22 +1458,21 @@

9166

args_count = ipa_get_cs_argument_count (args);

9167

parms_count = ipa_get_param_count (callee_info);

9168

9169

- /* If this call goes through a thunk we must not propagate to the first (0th)

9170

- parameter. However, we might need to uncover a thunk from below a series

9171

- of aliases first. */

9172

+ /* If this call goes through a thunk we should not propagate because we

9173

+ cannot redirect edges to thunks. However, we might need to uncover a

9174

+ thunk from below a series of aliases first. */

9175

alias_or_thunk = cs->callee;

9176

while (alias_or_thunk->alias)

9177

alias_or_thunk = cgraph_alias_aliased_node (alias_or_thunk);

9178

if (alias_or_thunk->thunk.thunk_p)

9179

{

9180

- ret |= set_all_contains_variable (ipa_get_parm_lattices (callee_info,

9181

- 0));

9182

- i = 1;

9183

+ for (i = 0; i < parms_count; i++)

9184

+ ret |= set_all_contains_variable (ipa_get_parm_lattices (callee_info,

9185

+ i));

9186

+ return ret;

9187

}

9188

- else

9189

- i = 0;

9190

9191

- for (; (i < args_count) && (i < parms_count); i++)

9192

+ for (i = 0; (i < args_count) && (i < parms_count); i++)

9193

{

9194

struct ipa_jump_func *jump_func = ipa_get_ith_jump_func (args, i);

9195

struct ipcp_param_lattices *dest_plats;

9196

@@ -3119,6 +3121,7 @@

9197

struct cgraph_node *node)

9198

{

9199

struct ipa_node_params *orig_caller_info = IPA_NODE_REF (cs->caller);

9200

+ struct ipa_node_params *orig_node_info;

9201

struct ipa_agg_replacement_value *aggval;

9202

int i, ec, count;

9203

9204

@@ -3133,6 +3136,7 @@

9205

if (aggval->index >= ec)

9206

return false;

9207

9208

+ orig_node_info = IPA_NODE_REF (IPA_NODE_REF (node)->ipcp_orig_node);

9209

if (orig_caller_info->ipcp_orig_node)

9210

orig_caller_info = IPA_NODE_REF (orig_caller_info->ipcp_orig_node);

9211

9212

@@ -3150,7 +3154,7 @@

9213

if (!interesting)

9214

continue;

9215

9216

- plats = ipa_get_parm_lattices (orig_caller_info, aggval->index);

9217

+ plats = ipa_get_parm_lattices (orig_node_info, aggval->index);

9218

if (plats->aggs_bottom)

9219

return false;

9220

9221

Index: gcc/rtlanal.c

9222

===================================================================

9223

--- a/src/gcc/rtlanal.c (.../tags/gcc_4_8_2_release)

9224

+++ b/src/gcc/rtlanal.c (.../branches/gcc-4_8-branch)

9225

@@ -224,10 +224,10 @@

9226

return 0;

9227

}

9228

9229

-/* Return nonzero if the use of X as an address in a MEM can cause a trap.

9230

- MODE is the mode of the MEM (not that of X) and UNALIGNED_MEMS controls

9231

- whether nonzero is returned for unaligned memory accesses on strict

9232

- alignment machines. */

9233

+/* Return nonzero if the use of X+OFFSET as an address in a MEM with SIZE

9234

+ bytes can cause a trap. MODE is the mode of the MEM (not that of X) and

9235

+ UNALIGNED_MEMS controls whether nonzero is returned for unaligned memory

9236

+ references on strict alignment machines. */

9237

9238

static int

9239

rtx_addr_can_trap_p_1 (const_rtx x, HOST_WIDE_INT offset, HOST_WIDE_INT size,

9240

@@ -235,11 +235,12 @@

9241

{

9242

enum rtx_code code = GET_CODE (x);

9243

9244

- if (STRICT_ALIGNMENT

9245

- && unaligned_mems

9246

- && GET_MODE_SIZE (mode) != 0)

9247

+ /* The offset must be a multiple of the mode size if we are considering

9248

+ unaligned memory references on strict alignment machines. */

9249

+ if (STRICT_ALIGNMENT && unaligned_mems && GET_MODE_SIZE (mode) != 0)

9250

{

9251

HOST_WIDE_INT actual_offset = offset;

9252

+

9253

#ifdef SPARC_STACK_BOUNDARY_HACK

9254

/* ??? The SPARC port may claim a STACK_BOUNDARY higher than

9255

the real alignment of %sp. However, when it does this, the

9256

@@ -298,8 +299,27 @@

9257

return 0;

9258

9259

case REG:

9260

- /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */

9261

- if (x == frame_pointer_rtx || x == hard_frame_pointer_rtx

9262

+ /* Stack references are assumed not to trap, but we need to deal with

9263

+ nonsensical offsets. */

9264

+ if (x == frame_pointer_rtx)

9265

+ {

9266

+ HOST_WIDE_INT adj_offset = offset - STARTING_FRAME_OFFSET;

9267

+ if (size == 0)

9268

+ size = GET_MODE_SIZE (mode);

9269

+ if (FRAME_GROWS_DOWNWARD)

9270

+ {

9271

+ if (adj_offset < frame_offset || adj_offset + size - 1 >= 0)

9272

+ return 1;

9273

+ }

9274

+ else

9275

+ {

9276

+ if (adj_offset < 0 || adj_offset + size - 1 >= frame_offset)

9277

+ return 1;

9278

+ }

9279

+ return 0;

9280

+ }

9281

+ /* ??? Need to add a similar guard for nonsensical offsets. */

9282

+ if (x == hard_frame_pointer_rtx

9283

|| x == stack_pointer_rtx

9284

/* The arg pointer varies if it is not a fixed register. */

9285

|| (x == arg_pointer_rtx && fixed_regs[ARG_POINTER_REGNUM]))

9286

@@ -320,9 +340,7 @@

9287

if (XEXP (x, 0) == pic_offset_table_rtx && CONSTANT_P (XEXP (x, 1)))

9288

return 0;

9289

9290

- /* - or it is an address that can't trap plus a constant integer,

9291

- with the proper remainder modulo the mode size if we are

9292

- considering unaligned memory references. */

9293

+ /* - or it is an address that can't trap plus a constant integer. */

9294

if (CONST_INT_P (XEXP (x, 1))

9295

&& !rtx_addr_can_trap_p_1 (XEXP (x, 0), offset + INTVAL (XEXP (x, 1)),

9296

size, mode, unaligned_mems))

9297

Index: gcc/configure

9298

===================================================================

9299

--- a/src/gcc/configure (.../tags/gcc_4_8_2_release)

9300

+++ b/src/gcc/configure (.../branches/gcc-4_8-branch)

9301

@@ -11202,13 +11202,16 @@

9302

/* | A-Za-z:\\/* ) realsrcdir=${srcdir};;

9303

*) realsrcdir=../${srcdir};;

9304

esac

9305

- saved_CFLAGS="${CFLAGS}"

9306

+ # Clearing GMPINC is necessary to prevent host headers being

9307

+ # used by the build compiler. Defining GENERATOR_FILE stops

9308

+ # system.h from including gmp.h.

9309

CC="${CC_FOR_BUILD}" CFLAGS="${CFLAGS_FOR_BUILD}" \

9310

- LDFLAGS="${LDFLAGS_FOR_BUILD}" \

9311

+ CXX="${CXX_FOR_BUILD}" CXXFLAGS="${CXXFLAGS_FOR_BUILD}" \

9312

+ LD="${LD_FOR_BUILD}" LDFLAGS="${LDFLAGS_FOR_BUILD}" \

9313

+ GMPINC="" CPPFLAGS="${CPPFLAGS} -DGENERATOR_FILE" \

9314

${realsrcdir}/configure \

9315

--enable-languages=${enable_languages-all} \

9316

--target=$target_alias --host=$build_alias --build=$build_alias

9317

- CFLAGS="${saved_CFLAGS}"

9318

9319

# We just finished tests for the build machine, so rename

9320

# the file auto-build.h in the gcc directory.

9321

@@ -11703,6 +11706,7 @@

9322

if test x$build != x$host || test "x$coverage_flags" != x

9323

then

9324

BUILD_CFLAGS='$(INTERNAL_CFLAGS) $(T_CFLAGS) $(CFLAGS_FOR_BUILD)'

9325

+ BUILD_CXXFLAGS='$(INTERNAL_CFLAGS) $(T_CFLAGS) $(CXXFLAGS_FOR_BUILD)'

9326

BUILD_LDFLAGS='$(LDFLAGS_FOR_BUILD)'

9327

fi

9328

9329

@@ -13590,7 +13594,7 @@

9330

rm -rf conftest*

9331

;;

9332

9333

-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \

9334

+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \

9335

s390*-*linux*|s390*-*tpf*|sparc*-*linux*)

9336

# Find out which ABI we are using.

9337

echo 'int i;' > conftest.$ac_ext

9338

@@ -13615,7 +13619,10 @@

9339

;;

9340

esac

9341

;;

9342

- ppc64-*linux*|powerpc64-*linux*)

9343

+ powerpc64le-*linux*)

9344

+ LD="${LD-ld} -m elf32lppclinux"

9345

+ ;;

9346

+ powerpc64-*linux*)

9347

LD="${LD-ld} -m elf32ppclinux"

9348

;;

9349

s390x-*linux*)

9350

@@ -13634,7 +13641,10 @@

9351

x86_64-*linux*)

9352

LD="${LD-ld} -m elf_x86_64"

9353

;;

9354

- ppc*-*linux*|powerpc*-*linux*)

9355

+ powerpcle-*linux*)

9356

+ LD="${LD-ld} -m elf64lppc"

9357

+ ;;

9358

+ powerpc-*linux*)

9359

LD="${LD-ld} -m elf64ppc"

9360

;;

9361

s390*-*linux*|s390*-*tpf*)

9362

@@ -17828,7 +17838,7 @@

9363

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

9364

lt_status=$lt_dlunknown

9365

cat > conftest.$ac_ext <<_LT_EOF

9366

-#line 17831 "configure"

9367

+#line 17841 "configure"

9368

#include "confdefs.h"

9369

9370

#if HAVE_DLFCN_H

9371

@@ -17934,7 +17944,7 @@

9372

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

9373

lt_status=$lt_dlunknown

9374

cat > conftest.$ac_ext <<_LT_EOF

9375

-#line 17937 "configure"

9376

+#line 17947 "configure"

9377

#include "confdefs.h"

9378

9379

#if HAVE_DLFCN_H

9380

@@ -24263,6 +24273,43 @@

9381

$as_echo "#define HAVE_AS_SPARC4 1" >>confdefs.h

9382

9383

fi

9384

+

9385

+ { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for LEON instructions" >&5

9386

+$as_echo_n "checking assembler for LEON instructions... " >&6; }

9387

+if test "${gcc_cv_as_sparc_leon+set}" = set; then :

9388

+ $as_echo_n "(cached) " >&6

9389

+else

9390

+ gcc_cv_as_sparc_leon=no

9391

+ if test x$gcc_cv_as != x; then

9392

+ $as_echo '.text

9393

+ .register %g2, #scratch

9394

+ .register %g3, #scratch

9395

+ .align 4

9396

+ smac %g2, %g3, %g1

9397

+ umac %g2, %g3, %g1

9398

+ casa [%g2] 0xb, %g3, %g1' > conftest.s

9399

+ if { ac_try='$gcc_cv_as $gcc_cv_as_flags -Aleon -o conftest.o conftest.s >&5'

9400

+ { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5

9401

+ (eval $ac_try) 2>&5

9402

+ ac_status=$?

9403

+ $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5

9404

+ test $ac_status = 0; }; }

9405

+ then

9406

+ gcc_cv_as_sparc_leon=yes

9407

+ else

9408

+ echo "configure: failed program was" >&5

9409

+ cat conftest.s >&5

9410

+ fi

9411

+ rm -f conftest.o conftest.s

9412

+ fi

9413

+fi

9414

+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_sparc_leon" >&5

9415

+$as_echo "$gcc_cv_as_sparc_leon" >&6; }

9416

+if test $gcc_cv_as_sparc_leon = yes; then

9417

+

9418

+$as_echo "#define HAVE_AS_LEON 1" >>confdefs.h

9419

+

9420

+fi

9421

;;

9422

9423

i[34567]86-*-* | x86_64-*-*)

9424

@@ -24745,6 +24792,10 @@

9425

9426

# These two are used unconditionally by i386.[ch]; it is to be defined

9427

# to 1 if the feature is present, 0 otherwise.

9428

+ as_ix86_gotoff_in_data_opt=

9429

+ if test x$gas = xyes; then

9430

+ as_ix86_gotoff_in_data_opt="--32"

9431

+ fi

9432

{ $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for GOTOFF in data" >&5

9433

$as_echo_n "checking assembler for GOTOFF in data... " >&6; }

9434

if test "${gcc_cv_as_ix86_gotoff_in_data+set}" = set; then :

9435

@@ -24761,7 +24812,7 @@

9436

nop

9437

.data

9438

.long .L0@GOTOFF' > conftest.s

9439

- if { ac_try='$gcc_cv_as $gcc_cv_as_flags -o conftest.o conftest.s >&5'

9440

+ if { ac_try='$gcc_cv_as $gcc_cv_as_flags $as_ix86_gotoff_in_data_opt -o conftest.o conftest.s >&5'

9441

{ { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5

9442

(eval $ac_try) 2>&5

9443

ac_status=$?

9444

@@ -24822,6 +24873,37 @@

9445

9446

fi

9447

9448

+ { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for ud2 mnemonic" >&5

9449

+$as_echo_n "checking assembler for ud2 mnemonic... " >&6; }

9450

+if test "${gcc_cv_as_ix86_ud2+set}" = set; then :

9451

+ $as_echo_n "(cached) " >&6

9452

+else

9453

+ gcc_cv_as_ix86_ud2=no

9454

+ if test x$gcc_cv_as != x; then

9455

+ $as_echo 'ud2' > conftest.s

9456

+ if { ac_try='$gcc_cv_as $gcc_cv_as_flags -o conftest.o conftest.s >&5'

9457

+ { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5

9458

+ (eval $ac_try) 2>&5

9459

+ ac_status=$?

9460

+ $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5

9461

+ test $ac_status = 0; }; }

9462

+ then

9463

+ gcc_cv_as_ix86_ud2=yes

9464

+ else

9465

+ echo "configure: failed program was" >&5

9466

+ cat conftest.s >&5

9467

+ fi

9468

+ rm -f conftest.o conftest.s

9469

+ fi

9470

+fi

9471

+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_ix86_ud2" >&5

9472

+$as_echo "$gcc_cv_as_ix86_ud2" >&6; }

9473

+if test $gcc_cv_as_ix86_ud2 = yes; then

9474

+

9475

+$as_echo "#define HAVE_AS_IX86_UD2 1" >>confdefs.h

9476

+

9477

+fi

9478

+

9479

{ $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for R_386_TLS_GD_PLT reloc" >&5

9480

$as_echo_n "checking assembler for R_386_TLS_GD_PLT reloc... " >&6; }

9481

if test "${gcc_cv_as_ix86_tlsgdplt+set}" = set; then :

9482

@@ -27239,8 +27321,8 @@

9483

$as_echo_n "checking for exported symbols... " >&6; }

9484

if test "x$export_sym_check" != x; then

9485

echo "int main() {return 0;} int foobar() {return 0;}" > conftest.c

9486

- ${CC} ${CFLAGS} ${LDFLAGS} conftest.c -o conftest > /dev/null 2>&1

9487

- if $export_sym_check conftest | grep foobar > /dev/null; then

9488

+ ${CC} ${CFLAGS} ${LDFLAGS} conftest.c -o conftest$ac_exeext > /dev/null 2>&1

9489

+ if $export_sym_check conftest$ac_exeext | grep -q foobar > /dev/null; then

9490

: # No need to use a flag

9491

{ $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5

9492

$as_echo "yes" >&6; }

9493

@@ -27249,8 +27331,8 @@

9494

$as_echo "yes" >&6; }

9495

{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for -rdynamic" >&5

9496

$as_echo_n "checking for -rdynamic... " >&6; }

9497

- ${CC} ${CFLAGS} ${LDFLAGS} -rdynamic conftest.c -o conftest > /dev/null 2>&1

9498

- if $export_sym_check conftest | grep foobar > /dev/null; then

9499

+ ${CC} ${CFLAGS} ${LDFLAGS} -rdynamic conftest.c -o conftest$ac_exeext > /dev/null 2>&1

9500

+ if $export_sym_check conftest$ac_exeext | grep -q foobar > /dev/null; then

9501

plugin_rdynamic=yes

9502

pluginlibs="-rdynamic"

9503

else

9504

Index: gcc/builtins.c

9505

===================================================================

9506

--- a/src/gcc/builtins.c (.../tags/gcc_4_8_2_release)

9507

+++ b/src/gcc/builtins.c (.../branches/gcc-4_8-branch)

9508

@@ -180,7 +180,6 @@

9509

static tree fold_builtin_strpbrk (location_t, tree, tree, tree);

9510

static tree fold_builtin_strstr (location_t, tree, tree, tree);

9511

static tree fold_builtin_strrchr (location_t, tree, tree, tree);

9512

-static tree fold_builtin_strcat (location_t, tree, tree);

9513

static tree fold_builtin_strncat (location_t, tree, tree, tree);

9514

static tree fold_builtin_strspn (location_t, tree, tree);

9515

static tree fold_builtin_strcspn (location_t, tree, tree);

9516

@@ -1958,6 +1957,7 @@

9517

tree fndecl = get_callee_fndecl (exp);

9518

enum machine_mode mode;

9519

bool errno_set = false;

9520

+ bool try_widening = false;

9521

tree arg;

9522

9523

if (!validate_arglist (exp, REAL_TYPE, VOID_TYPE))

9524

@@ -1969,6 +1969,7 @@

9525

{

9526

CASE_FLT_FN (BUILT_IN_SQRT):

9527

errno_set = ! tree_expr_nonnegative_p (arg);

9528

+ try_widening = true;

9529

builtin_optab = sqrt_optab;

9530

break;

9531

CASE_FLT_FN (BUILT_IN_EXP):

9532

@@ -2025,8 +2026,10 @@

9533

if (! flag_errno_math || ! HONOR_NANS (mode))

9534

errno_set = false;

9535

9536

- /* Before working hard, check whether the instruction is available. */

9537

- if (optab_handler (builtin_optab, mode) != CODE_FOR_nothing

9538

+ /* Before working hard, check whether the instruction is available, but try

9539

+ to widen the mode for specific operations. */

9540

+ if ((optab_handler (builtin_optab, mode) != CODE_FOR_nothing

9541

+ || (try_widening && !excess_precision_type (TREE_TYPE (exp))))

9542

&& (!errno_set || !optimize_insn_for_size_p ()))

9543

{

9544

rtx result = gen_reg_rtx (mode);

9545

@@ -5347,7 +5350,7 @@

9546

expand_builtin_atomic_compare_exchange (enum machine_mode mode, tree exp,

9547

rtx target)

9548

{

9549

- rtx expect, desired, mem, oldval;

9550

+ rtx expect, desired, mem, oldval, label;

9551

enum memmodel success, failure;

9552

tree weak;

9553

bool is_weak;

9554

@@ -5385,14 +5388,26 @@

9555

if (host_integerp (weak, 0) && tree_low_cst (weak, 0) != 0)

9556

is_weak = true;

9557

9558

- oldval = expect;

9559

- if (!expand_atomic_compare_and_swap ((target == const0_rtx ? NULL : &target),

9560

- &oldval, mem, oldval, desired,

9561

+ if (target == const0_rtx)

9562

+ target = NULL;

9563

+

9564

+ /* Lest the rtl backend create a race condition with an imporoper store

9565

+ to memory, always create a new pseudo for OLDVAL. */

9566

+ oldval = NULL;

9567

+

9568

+ if (!expand_atomic_compare_and_swap (&target, &oldval, mem, expect, desired,

9569

is_weak, success, failure))

9570

return NULL_RTX;

9571

9572

- if (oldval != expect)

9573

- emit_move_insn (expect, oldval);

9574

+ /* Conditionally store back to EXPECT, lest we create a race condition

9575

+ with an improper store to memory. */

9576

+ /* ??? With a rearrangement of atomics at the gimple level, we can handle

9577

+ the normal case where EXPECT is totally private, i.e. a register. At

9578

+ which point the store can be unconditional. */

9579

+ label = gen_label_rtx ();

9580

+ emit_cmp_and_jump_insns (target, const0_rtx, NE, NULL, VOIDmode, 1, label);

9581

+ emit_move_insn (expect, oldval);

9582

+ emit_label (label);

9583

9584

return target;

9585

}

9586

@@ -5846,6 +5861,9 @@

9587

switch (fcode)

9588

{

9589

CASE_FLT_FN (BUILT_IN_FABS):

9590

+ case BUILT_IN_FABSD32:

9591

+ case BUILT_IN_FABSD64:

9592

+ case BUILT_IN_FABSD128:

9593

target = expand_builtin_fabs (exp, target, subtarget);

9594

if (target)

9595

return target;

9596

@@ -10298,6 +10316,9 @@

9597

return fold_builtin_strlen (loc, type, arg0);

9598

9599

CASE_FLT_FN (BUILT_IN_FABS):

9600

+ case BUILT_IN_FABSD32:

9601

+ case BUILT_IN_FABSD64:

9602

+ case BUILT_IN_FABSD128:

9603

return fold_builtin_fabs (loc, arg0, type);

9604

9605

case BUILT_IN_ABS:

9606

@@ -10766,7 +10787,7 @@

9607

return fold_builtin_strstr (loc, arg0, arg1, type);

9608

9609

case BUILT_IN_STRCAT:

9610

- return fold_builtin_strcat (loc, arg0, arg1);

9611

+ return fold_builtin_strcat (loc, arg0, arg1, NULL_TREE);

9612

9613

case BUILT_IN_STRSPN:

9614

return fold_builtin_strspn (loc, arg0, arg1);

9615

@@ -11809,8 +11830,9 @@

9616

COMPOUND_EXPR in the chain will contain the tree for the simplified

9617

form of the builtin function call. */

9618

9619

-static tree

9620

-fold_builtin_strcat (location_t loc ATTRIBUTE_UNUSED, tree dst, tree src)

9621

+tree

9622

+fold_builtin_strcat (location_t loc ATTRIBUTE_UNUSED, tree dst, tree src,

9623

+ tree len)

9624

{

9625

if (!validate_arg (dst, POINTER_TYPE)

9626

|| !validate_arg (src, POINTER_TYPE))

9627

@@ -11828,22 +11850,17 @@

9628

/* See if we can store by pieces into (dst + strlen(dst)). */

9629

tree newdst, call;

9630

tree strlen_fn = builtin_decl_implicit (BUILT_IN_STRLEN);

9631

- tree strcpy_fn = builtin_decl_implicit (BUILT_IN_STRCPY);

9632

+ tree memcpy_fn = builtin_decl_implicit (BUILT_IN_MEMCPY);

9633

9634

- if (!strlen_fn || !strcpy_fn)

9635

+ if (!strlen_fn || !memcpy_fn)

9636

return NULL_TREE;

9637

9638

- /* If we don't have a movstr we don't want to emit an strcpy

9639

- call. We have to do that if the length of the source string

9640

- isn't computable (in that case we can use memcpy probably

9641

- later expanding to a sequence of mov instructions). If we

9642

- have movstr instructions we can emit strcpy calls. */

9643

- if (!HAVE_movstr)

9644

- {

9645

- tree len = c_strlen (src, 1);

9646

- if (! len || TREE_SIDE_EFFECTS (len))

9647

- return NULL_TREE;

9648

- }

9649

+ /* If the length of the source string isn't computable don't

9650

+ split strcat into strlen and memcpy. */

9651

+ if (! len)

9652

+ len = c_strlen (src, 1);

9653

+ if (! len || TREE_SIDE_EFFECTS (len))

9654

+ return NULL_TREE;

9655

9656

/* Stabilize the argument list. */

9657

dst = builtin_save_expr (dst);

9658

@@ -11855,7 +11872,11 @@

9659

newdst = fold_build_pointer_plus_loc (loc, dst, newdst);

9660

newdst = builtin_save_expr (newdst);

9661

9662

- call = build_call_expr_loc (loc, strcpy_fn, 2, newdst, src);

9663

+ len = fold_convert_loc (loc, size_type_node, len);

9664

+ len = size_binop_loc (loc, PLUS_EXPR, len,

9665

+ build_int_cst (size_type_node, 1));

9666

+

9667

+ call = build_call_expr_loc (loc, memcpy_fn, 3, newdst, src, len);

9668

return build2 (COMPOUND_EXPR, TREE_TYPE (dst), call, dst);

9669

}

9670

return NULL_TREE;

9671

Index: gcc/gcc.c

9672

===================================================================

9673

--- a/src/gcc/gcc.c (.../tags/gcc_4_8_2_release)

9674

+++ b/src/gcc/gcc.c (.../branches/gcc-4_8-branch)

9675

@@ -5441,7 +5441,7 @@

9676

const char *save_suffix_subst;

9677

9678

int save_growing_size;

9679

- void *save_growing_value;

9680

+ void *save_growing_value = NULL;

9681

9682

sf = lookup_spec_function (func);

9683

if (sf == NULL)

9684

Index: gcc/fold-const.c

9685

===================================================================

9686

--- a/src/gcc/fold-const.c (.../tags/gcc_4_8_2_release)

9687

+++ b/src/gcc/fold-const.c (.../branches/gcc-4_8-branch)

9688

@@ -2664,10 +2664,11 @@

9689

case COMPONENT_REF:

9690

/* Handle operand 2 the same as for ARRAY_REF. Operand 0

9691

may be NULL when we're called to compare MEM_EXPRs. */

9692

- if (!OP_SAME_WITH_NULL (0))

9693

+ if (!OP_SAME_WITH_NULL (0)

9694

+ || !OP_SAME (1))

9695

return 0;

9696

flags &= ~OEP_CONSTANT_ADDRESS_OF;

9697

- return OP_SAME (1) && OP_SAME_WITH_NULL (2);

9698

+ return OP_SAME_WITH_NULL (2);

9699

9700

case BIT_FIELD_REF:

9701

if (!OP_SAME (0))

9702

@@ -4920,12 +4921,16 @@

9703

int in0_p, in1_p, in_p;

9704

tree low0, low1, low, high0, high1, high;

9705

bool strict_overflow_p = false;

9706

- tree lhs = make_range (op0, &in0_p, &low0, &high0, &strict_overflow_p);

9707

- tree rhs = make_range (op1, &in1_p, &low1, &high1, &strict_overflow_p);

9708

- tree tem;

9709

+ tree tem, lhs, rhs;

9710

const char * const warnmsg = G_("assuming signed overflow does not occur "

9711

"when simplifying range test");

9712

9713

+ if (!INTEGRAL_TYPE_P (type))

9714

+ return 0;

9715

+

9716

+ lhs = make_range (op0, &in0_p, &low0, &high0, &strict_overflow_p);

9717

+ rhs = make_range (op1, &in1_p, &low1, &high1, &strict_overflow_p);

9718

+

9719

/* If this is an OR operation, invert both sides; we will invert

9720

again at the end. */

9721

if (or_op)

9722

@@ -10927,6 +10932,13 @@

9723

fold_build2_loc (loc, MULT_EXPR, type,

9724

build_int_cst (type, 2) , arg1));

9725

9726

+ /* ((T) (X /[ex] C)) * C cancels out if the conversion is

9727

+ sign-changing only. */

9728

+ if (TREE_CODE (arg1) == INTEGER_CST

9729

+ && TREE_CODE (arg0) == EXACT_DIV_EXPR

9730

+ && operand_equal_p (arg1, TREE_OPERAND (arg0, 1), 0))

9731

+ return fold_convert_loc (loc, type, TREE_OPERAND (arg0, 0));

9732

+

9733

strict_overflow_p = false;

9734

if (TREE_CODE (arg1) == INTEGER_CST

9735

&& 0 != (tem = extract_muldiv (op0, arg1, code, NULL_TREE,

9736

@@ -16587,7 +16599,7 @@

9737

unsigned HOST_WIDE_INT indexi = offset * BITS_PER_UNIT;

9738

tree index = bitsize_int (indexi);

9739

9740

- if (offset/part_widthi <= TYPE_VECTOR_SUBPARTS (op00type))

9741

+ if (offset / part_widthi < TYPE_VECTOR_SUBPARTS (op00type))

9742

return fold_build3_loc (loc,

9743

BIT_FIELD_REF, type, op00,

9744

part_width, index);

9745

Index: gcc/objc/ChangeLog

9746

===================================================================

9747

--- a/src/gcc/objc/ChangeLog (.../tags/gcc_4_8_2_release)

9748

+++ b/src/gcc/objc/ChangeLog (.../branches/gcc-4_8-branch)

9749

@@ -1,3 +1,14 @@

9750

+2014-04-07 Dominique d'Humieres <dominiq@lps.ens.fr>

9751

+

9752

+ Backport from mainline

9753

+ 2013-09-14 Iain Sandoe <iains@gcc.gnu.org>

9754

+

9755

+ PR target/48094

9756

+ * objc-next-runtime-abi-01.c (generate_objc_image_info): Remove.

9757

+ (objc_generate_v1_next_metadata): Remove generation of ImageInfo.

9758

+ * objc-next-runtime-abi-02.c (generate_v2_objc_image_info): Remove.

9759

+ (objc_generate_v2_next_metadata): Remove generation of ImageInfo.

9760

+

9761

2013-10-16 Release Manager

9762

9763

* GCC 4.8.2 released.

9764

Index: gcc/objc/objc-next-runtime-abi-01.c

9765

===================================================================

9766

--- a/src/gcc/objc/objc-next-runtime-abi-01.c (.../tags/gcc_4_8_2_release)

9767

+++ b/src/gcc/objc/objc-next-runtime-abi-01.c (.../branches/gcc-4_8-branch)

9768

@@ -2332,37 +2332,7 @@

9769

return;

9770

}

9771

9772

-

9773

-/* The Fix-and-Continue functionality available in Mac OS X 10.3 and

9774

- later requires that ObjC translation units participating in F&C be

9775

- specially marked. The following routine accomplishes this. */

9776

-

9777

-/* static int _OBJC_IMAGE_INFO[2] = { 0, 1 }; */

9778

-

9779

static void

9780

-generate_objc_image_info (void)

9781

-{

9782

- tree decl;

9783

- int flags

9784

- = ((flag_replace_objc_classes && imp_count ? 1 : 0)

9785

- | (flag_objc_gc ? 2 : 0));

9786

- vec<constructor_elt, va_gc> *v = NULL;

9787

- tree array_type;

9788

-

9789

- array_type = build_sized_array_type (integer_type_node, 2);

9790

-

9791

- decl = start_var_decl (array_type, "_OBJC_ImageInfo");

9792

-

9793

- CONSTRUCTOR_APPEND_ELT (v, NULL_TREE, integer_zero_node);

9794

- CONSTRUCTOR_APPEND_ELT (v, NULL_TREE, build_int_cst (integer_type_node, flags));

9795

- /* The runtime wants this and refers to it in a manner hidden from the compiler.

9796

- So we must force the output. */

9797

- DECL_PRESERVE_P (decl) = 1;

9798

- OBJCMETA (decl, objc_meta, meta_info);

9799

- finish_var_decl (decl, objc_build_constructor (TREE_TYPE (decl), v));

9800

-}

9801

-

9802

-static void

9803

objc_generate_v1_next_metadata (void)

9804

{

9805

struct imp_entry *impent;

9806

@@ -2412,9 +2382,6 @@

9807

attr = build_tree_list (objc_meta, meta_modules);

9808

build_module_descriptor (vers, attr);

9809

9810

- /* This conveys information on GC usage and zero-link. */

9811

- generate_objc_image_info ();

9812

-

9813

/* Dump the class references. This forces the appropriate classes

9814

to be linked into the executable image, preserving unix archive

9815

semantics. */

9816

Index: gcc/objc/objc-next-runtime-abi-02.c

9817

===================================================================

9818

--- a/src/gcc/objc/objc-next-runtime-abi-02.c (.../tags/gcc_4_8_2_release)

9819

+++ b/src/gcc/objc/objc-next-runtime-abi-02.c (.../branches/gcc-4_8-branch)

9820

@@ -3329,32 +3329,7 @@

9821

finish_var_decl (ref->decl, ref->offset);

9822

}

9823

9824

-/* static int _OBJC_IMAGE_INFO[2] = { 0, 16 | flags }; */

9825

-

9826

static void

9827

-generate_v2_objc_image_info (void)

9828

-{

9829

- tree decl, array_type;

9830

- vec<constructor_elt, va_gc> *v = NULL;

9831

- int flags =

9832

- ((flag_replace_objc_classes && imp_count ? 1 : 0)

9833

- | (flag_objc_gc ? 2 : 0));

9834

-

9835

- flags |= 16;

9836

-

9837

- array_type = build_sized_array_type (integer_type_node, 2);

9838

-

9839

- decl = start_var_decl (array_type, "_OBJC_ImageInfo");

9840

-

9841

- CONSTRUCTOR_APPEND_ELT (v, NULL_TREE, integer_zero_node);

9842

- CONSTRUCTOR_APPEND_ELT (v, NULL_TREE, build_int_cst (integer_type_node, flags));

9843

- /* The Runtime wants this. */

9844

- DECL_PRESERVE_P (decl) = 1;

9845

- OBJCMETA (decl, objc_meta, meta_info);

9846

- finish_var_decl (decl, objc_build_constructor (TREE_TYPE (decl), v));

9847

-}

9848

-

9849

-static void

9850

objc_generate_v2_next_metadata (void)

9851

{

9852

struct imp_entry *impent;

9853

@@ -3405,9 +3380,6 @@

9854

build_v2_address_table (nonlazy_category_list, "_OBJC_NonLazyCategoryList$",

9855

meta_label_nonlazy_categorylist);

9856

9857

- /* This conveys information on GC usage and zero-link. */

9858

- generate_v2_objc_image_info ();

9859

-

9860

/* Generate catch objects for eh, if any are needed. */

9861

build_v2_eh_catch_objects ();

9862

9863

Index: gcc/reorg.c

9864

===================================================================

9865

--- a/src/gcc/reorg.c (.../tags/gcc_4_8_2_release)

9866

+++ b/src/gcc/reorg.c (.../branches/gcc-4_8-branch)

9867

@@ -1105,6 +1105,7 @@

9868

int used_annul = 0;

9869

int i;

9870

struct resources cc_set;

9871

+ bool *redundant;

9872

9873

/* We can't do anything if there are more delay slots in SEQ than we

9874

can handle, or if we don't know that it will be a taken branch.

9875

@@ -1145,6 +1146,7 @@

9876

return delay_list;

9877

#endif

9878

9879

+ redundant = XALLOCAVEC (bool, XVECLEN (seq, 0));

9880

for (i = 1; i < XVECLEN (seq, 0); i++)

9881

{

9882

rtx trial = XVECEXP (seq, 0, i);

9883

@@ -1166,7 +1168,8 @@

9884

9885

/* If this insn was already done (usually in a previous delay slot),

9886

pretend we put it in our delay slot. */

9887

- if (redundant_insn (trial, insn, new_delay_list))

9888

+ redundant[i] = redundant_insn (trial, insn, new_delay_list);

9889

+ if (redundant[i])

9890

continue;

9891

9892

/* We will end up re-vectoring this branch, so compute flags

9893

@@ -1199,6 +1202,12 @@

9894

return delay_list;

9895

}

9896

9897

+ /* Record the effect of the instructions that were redundant and which

9898

+ we therefore decided not to copy. */

9899

+ for (i = 1; i < XVECLEN (seq, 0); i++)

9900

+ if (redundant[i])

9901

+ update_block (XVECEXP (seq, 0, i), insn);

9902

+

9903

/* Show the place to which we will be branching. */

9904

*pnew_thread = first_active_target_insn (JUMP_LABEL (XVECEXP (seq, 0, 0)));

9905

9906

@@ -1262,6 +1271,7 @@

9907

/* If this insn was already done, we don't need it. */

9908

if (redundant_insn (trial, insn, delay_list))

9909

{

9910

+ update_block (trial, insn);

9911

delete_from_delay_slot (trial);

9912

continue;

9913

}

9914

@@ -3266,6 +3276,7 @@

9915

to reprocess this insn. */

9916

if (redundant_insn (XVECEXP (pat, 0, 1), delay_insn, 0))

9917

{

9918

+ update_block (XVECEXP (pat, 0, 1), insn);

9919

delete_from_delay_slot (XVECEXP (pat, 0, 1));

9920

next = prev_active_insn (next);

9921

continue;

9922

@@ -3385,6 +3396,7 @@

9923

&& redirect_with_delay_slots_safe_p (delay_insn, target_label,

9924

insn))

9925

{

9926

+ update_block (XVECEXP (PATTERN (trial), 0, 1), insn);

9927

reorg_redirect_jump (delay_insn, target_label);

9928

next = insn;

9929

continue;

9930

Index: gcc/tree-ssa-sccvn.c

9931

===================================================================

9932

--- a/src/gcc/tree-ssa-sccvn.c (.../tags/gcc_4_8_2_release)

9933

+++ b/src/gcc/tree-ssa-sccvn.c (.../branches/gcc-4_8-branch)

9934

@@ -660,7 +660,7 @@

9935

}

9936

9937

/* For non-calls, store the information that makes up the address. */

9938

-

9939

+ tree orig = ref;

9940

while (ref)

9941

{

9942

vn_reference_op_s temp;

9943

@@ -711,7 +711,15 @@

9944

.arshift (BITS_PER_UNIT == 8

9945

? 3 : exact_log2 (BITS_PER_UNIT),

9946

HOST_BITS_PER_DOUBLE_INT);

9947

- if (off.fits_shwi ())

9948

+ if (off.fits_shwi ()

9949

+ /* Probibit value-numbering zero offset components

9950

+ of addresses the same before the pass folding

9951

+ __builtin_object_size had a chance to run

9952

+ (checking cfun->after_inlining does the

9953

+ trick here). */

9954

+ && (TREE_CODE (orig) != ADDR_EXPR

9955

+ || !off.is_zero ()

9956

+ || cfun->after_inlining))

9957

temp.off = off.low;

9958

}

9959

}

9960

Index: gcc/ChangeLog

9961

===================================================================

9962

--- a/src/gcc/ChangeLog (.../tags/gcc_4_8_2_release)

9963

+++ b/src/gcc/ChangeLog (.../branches/gcc-4_8-branch)

9964

@@ -1,3 +1,5329 @@

9965

+2014-05-05 Richard Biener <rguenther@suse.de>

9966

+

9967

+ Backport from mainline

9968

+ 2014-04-23 Richard Biener <rguenther@suse.de>

9969

+

9970

+ PR middle-end/60895

9971

+ * tree-inline.c (declare_return_variable): Use mark_addressable.

9972

+

9973

+ 2014-04-07 Richard Biener <rguenther@suse.de>

9974

+

9975

+ PR middle-end/60750

9976

+ * tree-ssa-operands.c (maybe_add_call_vops): Also add VDEFs

9977

+ for noreturn calls.

9978

+ * tree-cfgcleanup.c (fixup_noreturn_call): Do not remove VDEFs.

9979

+

9980

+ 2014-04-14 Richard Biener <rguenther@suse.de>

9981

+

9982

+ PR tree-optimization/59817

9983

+ PR tree-optimization/60453

9984

+ * graphite-scop-detection.c (graphite_can_represent_scev): Complete

9985

+ recursion to catch all CHRECs in the scalar evolution and restrict

9986

+ the predicate for the remains appropriately.

9987

+

9988

+ 2014-04-17 Richard Biener <rguenther@suse.de>

9989

+

9990

+ PR tree-optimization/60836

9991

+ * tree-vect-loop.c (vect_create_epilog_for_reduction): Force

9992

+ initial PHI args to be gimple values.

9993

+

9994

+2014-05-05 Jakub Jelinek <jakub@redhat.com>

9995

+

9996

+ Backported from mainline

9997

+ 2014-04-25 Jakub Jelinek <jakub@redhat.com>

9998

+

9999

+ PR tree-optimization/60960

10000

+ * tree-vect-generic.c (expand_vector_operation): Only call

10001

+ expand_vector_divmod if type's mode satisfies VECTOR_MODE_P.

10002

+

10003

+2014-05-04 Peter Bergner <bergner@vnet.ibm.com>

10004

+

10005

+ * config/rs6000/rs6000.h (RS6000_BTM_HARD_FLOAT): New define.

10006

+ (RS6000_BTM_COMMON): Add RS6000_BTM_HARD_FLOAT.

10007

+ (TARGET_EXTRA_BUILTINS): Add TARGET_HARD_FLOAT.

10008

+ * config/rs6000/rs6000-builtin.def (BU_MISC_1):

10009

+ Use RS6000_BTM_HARD_FLOAT.

10010

+ (BU_MISC_2): Likewise.

10011

+ * config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Handle

10012

+ RS6000_BTM_HARD_FLOAT.

10013

+ (rs6000_option_override_internal): Enforce -mhard-float if -mhard-dfp

10014

+ is explicitly used.

10015

+ (rs6000_invalid_builtin): Add hard floating builtin support.

10016

+ (rs6000_expand_builtin): Relax the gcc_assert to allow the new

10017

+ hard float builtins.

10018

+ (rs6000_builtin_mask_names): Add RS6000_BTM_HARD_FLOAT.

10019

+

10020

+2014-05-03 Joey Ye <joey.ye@arm.com>

10021

+

10022

+ Backport from mainline r209463

10023

+ 2014-04-17 Joey Ye <joey.ye@arm.com>

10024

+

10025

+ * opts.c (OPT_fif_conversion, OPT_fif_conversion2): Disable for Og.

10026

+

10027

+2014-05-03 Oleg Endo <olegendo@gcc.gnu.org>

10028

+

10029

+ Back port from mainline

10030

+ PR target/61026

10031

+ * config/sh/sh.c: Include stdlib headers before everything else.

10032

+

10033

+2014-05-02 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10034

+

10035

+ PR tree-optimization/60930

10036

+ * gimple-ssa-strength-reduction.c (create_mul_imm_cand): Reject

10037

+ creating a multiply candidate by folding two constant

10038

+ multiplicands when the result overflows.

10039

+

10040

+2014-05-02 Kyrylo Tkachov <kyrylo.tkachov@arm.com>

10041

+

10042

+ * config/aarch64/aarch64.h (TARGET_SIMD): Take AARCH64_ISA_SIMD

10043

+ into account.

10044

+ (TARGET_FLOAT): Take AARCH64_ISA_FP into account.

10045

+

10046

+2014-04-30 Michael Meissner <meissner@linux.vnet.ibm.com>

10047

+

10048

+ Back port from mainline

10049

+ 2014-04-24 Michael Meissner <meissner@linux.vnet.ibm.com>

10050

+

10051

+ * doc/extend.texi (PowerPC Built-in Functions): Document new

10052

+ powerpc extended divide, bcd, pack/unpack 128-bit, builtin

10053

+ functions.

10054

+ (PowerPC AltiVec/VSX Built-in Functions): Likewise.

10055

+

10056

+ * config/rs6000/predicates.md (const_0_to_3_operand): New

10057

+ predicate to match 0..3 integer constants.

10058

+

10059

+ * config/rs6000/rs6000-builtin.def (BU_DFP_MISC_1): Add new macros

10060

+ to support adding miscellaneous builtin functions.

10061

+ (BU_DFP_MISC_2): Likewise.

10062

+ (BU_P7_MISC_1): Likewise.

10063

+ (BU_P7_MISC_2): Likewise.

10064

+ (BU_P8V_MISC_3): Likewise.

10065

+ (BU_MISC_1): Likewise.

10066

+ (BU_MISC_2): Likewise.

10067

+ (DIVWE): Add extended divide builtin functions.

10068

+ (DIVWEO): Likewise.

10069

+ (DIVWEU): Likewise.

10070

+ (DIVWEUO): Likewise.

10071

+ (DIVDE): Likewise.

10072

+ (DIVDEO): Likewise.

10073

+ (DIVDEU): Likewise.

10074

+ (DIVDEUO): Likewise.

10075

+ (DXEX): Add decimal floating-point builtin functions.

10076

+ (DXEXQ): Likewise.

10077

+ (DDEDPD): Likewise.

10078

+ (DDEDPDQ): Likewise.

10079

+ (DENBCD): Likewise.

10080

+ (DENBCDQ): Likewise.

10081

+ (DIEX): Likewise.

10082

+ (DIEXQ): Likewise.

10083

+ (DSCLI): Likewise.

10084

+ (DSCLIQ): Likewise.

10085

+ (DSCRI): Likewise.

10086

+ (DSCRIQ): Likewise.

10087

+ (CDTBCD): Add new BCD builtin functions.

10088

+ (CBCDTD): Likewise.

10089

+ (ADDG6S): Likewise.

10090

+ (BCDADD): Likewise.

10091

+ (BCDADD_LT): Likewise.

10092

+ (BCDADD_EQ): Likewise.

10093

+ (BCDADD_GT): Likewise.

10094

+ (BCDADD_OV): Likewise.

10095

+ (BCDSUB): Likewise.

10096

+ (BCDSUB_LT): Likewise.

10097

+ (BCDSUB_EQ): Likewise.

10098

+ (BCDSUB_GT): Likewise.

10099

+ (BCDSUB_OV): Likewise.

10100

+ (PACK_TD): Add new pack/unpack 128-bit type builtin functions.

10101

+ (UNPACK_TD): Likewise.

10102

+ (PACK_TF): Likewise.

10103

+ (UNPACK_TF): Likewise.

10104

+ (UNPACK_TF_0): Likewise.

10105

+ (UNPACK_TF_1): Likewise.

10106

+ (PACK_V1TI): Likewise.

10107

+ (UNPACK_V1TI): Likewise.

10108

+

10109

+ * config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Add

10110

+ support for decimal floating point builtin functions.

10111

+ (rs6000_expand_ternop_builtin): Add checks for the new builtin

10112

+ functions that take constant arguments.

10113

+ (rs6000_invalid_builtin): Add decimal floating point builtin

10114

+ support.

10115

+ (rs6000_init_builtins): Setup long double, _Decimal64, and

10116

+ _Decimal128 types for new builtin functions.

10117

+ (builtin_function_type): Set the unsigned flags appropriately for

10118

+ the new builtin functions.

10119

+ (rs6000_opt_masks): Add support for decimal floating point builtin

10120

+ functions.

10121

+

10122

+ * config/rs6000/rs6000.h (RS6000_BTM_DFP): Add support for decimal

10123

+ floating point builtin functions.

10124

+ (RS6000_BTM_COMMON): Likewise.

10125

+ (RS6000_BTI_long_double): Likewise.

10126

+ (RS6000_BTI_dfloat64): Likewise.

10127

+ (RS6000_BTI_dfloat128): Likewise.

10128

+ (long_double_type_internal_node): Likewise.

10129

+ (dfloat64_type_internal_node): Likewise.

10130

+ (dfloat128_type_internal_node): Likewise.

10131

+

10132

+ * config/rs6000/altivec.h (UNSPEC_BCDADD): Add support for ISA

10133

+ 2.07 bcd arithmetic instructions.

10134

+ (UNSPEC_BCDSUB): Likewise.

10135

+ (UNSPEC_BCD_OVERFLOW): Likewise.

10136

+ (UNSPEC_BCD_ADD_SUB): Likewise.

10137

+ (bcd_add_sub): Likewise.

10138

+ (BCD_TEST): Likewise.

10139

+ (bcd<bcd_add_sub>): Likewise.

10140

+ (bcd<bcd_add_sub>_test): Likewise.

10141

+ (bcd<bcd_add_sub>_test2): Likewise.

10142

+ (bcd<bcd_add_sub>_<code>): Likewise.

10143

+ (peephole2 for combined bcd ops): Likewise.

10144

+

10145

+ * config/rs6000/dfp.md (UNSPEC_DDEDPD): Add support for new

10146

+ decimal floating point builtin functions.

10147

+ (UNSPEC_DENBCD): Likewise.

10148

+ (UNSPEC_DXEX): Likewise.

10149

+ (UNSPEC_DIEX): Likewise.

10150

+ (UNSPEC_DSCLI): Likewise.

10151

+ (UNSPEC_DSCRI): Likewise.

10152

+ (D64_D128): Likewise.

10153

+ (dfp_suffix): Likewise.

10154

+ (dfp_ddedpd_<mode>): Likewise.

10155

+ (dfp_denbcd_<mode>): Likewise.

10156

+ (dfp_dxex_<mode>): Likewise.

10157

+ (dfp_diex_<mode>): Likewise.

10158

+ (dfp_dscli_<mode>): Likewise.

10159

+ (dfp_dscri_<mode>): Likewise.

10160

+

10161

+ * config/rs6000/rs6000.md (UNSPEC_ADDG6S): Add support for new BCD

10162

+ builtin functions.

10163

+ (UNSPEC_CDTBCD): Likewise.

10164

+ (UNSPEC_CBCDTD): Likewise.

10165

+ (UNSPEC_DIVE): Add support for new extended divide builtin

10166

+ functions.

10167

+ (UNSPEC_DIVEO): Likewise.

10168

+ (UNSPEC_DIVEU): Likewise.

10169

+ (UNSPEC_DIVEUO): Likewise.

10170

+ (UNSPEC_UNPACK_128BIT): Add support for new builtin functions to

10171

+ pack/unpack 128-bit types.

10172

+ (UNSPEC_PACK_128BIT): Likewise.

10173

+ (idiv_ldiv): New mode attribute to set the 32/64-bit divide type.

10174

+ (udiv<mode>3): Use idiv_ldiv mode attribute.

10175

+ (div<mode>3): Likewise.

10176

+ (addg6s): Add new BCD builtin functions.

10177

+ (cdtbcd): Likewise.

10178

+ (cbcdtd): Likewise.

10179

+ (UNSPEC_DIV_EXTEND): Add support for new extended divide

10180

+ instructions.

10181

+ (div_extend): Likewise.

10182

+ (div<div_extend>_<mode>"): Likewise.

10183

+ (FP128_64): Add support for new builtin functions to pack/unpack

10184

+ 128-bit types.

10185

+ (unpack<mode>): Likewise.

10186

+ (unpacktf_0): Likewise.

10187

+ (unpacktf_1): Likewise.

10188

+ (unpack<mode>_dm): Likewise.

10189

+ (unpack<mode>_nodm): Likewise.

10190

+ (pack<mode>): Likewise.

10191

+ (unpackv1ti): Likewise.

10192

+ (packv1ti): Likewise.

10193

+

10194

+2014-04-29 Pat Haugen <pthaugen@us.ibm.com>

10195

+

10196

+ Backport from mainline

10197

+ 2014-04-17 Pat Haugen <pthaugen@us.ibm.com>

10198

+

10199

+ * config/rs6000/rs6000.md (addti3, subti3): New.

10200

+

10201

+2014-04-28 Pat Haugen <pthaugen@us.ibm.com>

10202

+

10203

+ Backport from mainline

10204

+ 2014-04-28 Pat Haugen <pthaugen@us.ibm.com>

10205

+

10206

+ * config/rs6000/sync.md (AINT mode_iterator): Move definition.

10207

+ (loadsync_<mode>): Change mode.

10208

+ (load_quadpti, store_quadpti): New.

10209

+ (atomic_load<mode>, atomic_store<mode>): Add support for TI mode.

10210

+ * config/rs6000/rs6000.md (unspec enum): Add UNSPEC_LSQ.

10211

+

10212

+2014-04-28 Eric Botcazou <ebotcazou@adacore.com>

10213

+

10214

+ * configure.ac: Tweak GAS check for LEON instructions on SPARC.

10215

+ * configure: Regenerate.

10216

+ * config/sparc/sparc.opt (muser-mode): New option.

10217

+ * config/sparc/sync.md (atomic_compare_and_swap<mode>_1): Do not enable

10218

+ for LEON3.

10219

+ (atomic_compare_and_swap_leon3_1): New instruction for LEON3.

10220

+ * doc/invoke.texi (SPARC options): Document -muser-mode.

10221

+

10222

+2014-04-25 Eric Botcazou <ebotcazou@adacore.com>

10223

+

10224

+ PR target/60941

10225

+ * config/sparc/sparc.md (ashlsi3_extend): Delete.

10226

+

10227

+2014-04-22 Michael Meissner <meissner@linux.vnet.ibm.com>

10228

+

10229

+ Back port from main line:

10230

+ 2014-03-27 Michael Meissner <meissner@linux.vnet.ibm.com>

10231

+

10232

+ * config/rs6000/rs6000-builtins.def (VBPERMQ): Add vbpermq builtin

10233

+ for ISA 2.07.

10234

+

10235

+ * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add

10236

+ vbpermq builtins.

10237

+

10238

+ * config/rs6000/altivec.md (UNSPEC_VBPERMQ): Add support for the

10239

+ vbpermq instruction.

10240

+ (altivec_vbpermq): Likewise.

10241

+

10242

+ PR target/60672

10243

+ * config/rs6000/altivec.h (vec_xxsldwi): Add missing define to

10244

+ enable use of xxsldwi and xxpermdi builtin functions.

10245

+ (vec_xxpermdi): Likewise.

10246

+

10247

+ * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions):

10248

+ Document use of vec_xxsldwi and vec_xxpermdi builtins.

10249

+

10250

+2014-04-23 Uros Bizjak <ubizjak@gmail.com>

10251

+

10252

+ Backport from mainline

10253

+ 2014-04-21 Uros Bizjak <ubizjak@gmail.com>

10254

+

10255

+ PR target/60909

10256

+ * config/i386/i386.c (ix86_expand_builtin)

10257

+ <case IX86_BUILTIN_RDRAND{16,32,64}_STEP>: Use temporary

10258

+ register for target RTX.

10259

+ <case IX86_BUILTIN_RDSEED{16,32,64}_STEP>: Ditto.

10260

+

10261

+2014-04-23 Richard Biener <rguenther@suse.de>

10262

+

10263

+ Backport from mainline

10264

+ 2014-04-02 Richard Biener <rguenther@suse.de>

10265

+

10266

+ PR middle-end/60729

10267

+ * optabs.c (expand_abs_nojump): Honor flag_trapv only for

10268

+ MODE_INTs. Properly use negv_optab.

10269

+ (expand_abs): Likewise.

10270

+

10271

+ 2014-04-03 Richard Biener <rguenther@suse.de>

10272

+

10273

+ PR tree-optimization/60740

10274

+ * graphite-scop-detection.c (stmt_simple_for_scop_p): Iterate

10275

+ over all GIMPLE_COND operands.

10276

+

10277

+2014-04-23 Richard Biener <rguenther@suse.de>

10278

+

10279

+ PR middle-end/60635

10280

+ * gimplify.c (gimple_regimplify_operands): Update the

10281

+ re-gimplifed stmt.

10282

+

10283

+2014-04-21 Michael Meissner <meissner@linux.vnet.ibm.com>

10284

+

10285

+ Back port from the trunk, subversion id 209546.

10286

+

10287

+ 2014-04-21 Michael Meissner <meissner@linux.vnet.ibm.com>

10288

+

10289

+ PR target/60735

10290

+ * config/rs6000/rs6000.md (mov<mode>_softfloat32, FMOVE64 case):

10291

+ If mode is DDmode and TARGET_E500_DOUBLE allow move.

10292

+

10293

+ * config/rs6000/rs6000.c (rs6000_debug_reg_global): Print some

10294

+ more debug information for E500 if -mdebug=reg.

10295

+

10296

+2014-04-18 Richard Henderson <rth@redhat.com>

10297

+

10298

+ * config/aarch64/aarch64.c (aarch64_register_move_cost): Pass a mode

10299

+ to GET_MODE_SIZE, not a reg_class_t.

10300

+

10301

+2014-04-17 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10302

+

10303

+ * config/rs6000/vsx.md (vsx_xxmrghw_<mode>): Adjust for

10304

+ little-endian.

10305

+ (vsx_xxmrglw_<mode>): Likewise.

10306

+

10307

+2014-04-15 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10308

+

10309

+ PR target/60839

10310

+ Revert the following patch

10311

+

10312

+ 2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10313

+

10314

+ Back port mainline subversion id 209025.

10315

+ 2014-04-02 Michael Meissner <meissner@linux.vnet.ibm.com>

10316

+

10317

+ PR target/60735

10318

+ * config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): If we have

10319

+ software floating point or no floating point registers, do not

10320

+ allow any type in the FPRs. Eliminate a test for SPE SIMD types

10321

+ in GPRs that occurs after we tested for GPRs that would never be

10322

+ true.

10323

+

10324

+ * config/rs6000/rs6000.md (mov<mode>_softfloat32, FMOVE64):

10325

+ Rewrite tests to use TARGET_DOUBLE_FLOAT and TARGET_E500_DOUBLE,

10326

+ since the FMOVE64 type is DFmode/DDmode. If TARGET_E500_DOUBLE,

10327

+ specifically allow DDmode, since that does not use the SPE SIMD

10328

+ instructions.

10329

+

10330

+2014-04-10 Vladimir Makarov <vmakarov@redhat.com>

10331

+

10332

+ PR rtl-optimization/60769

10333

+ * lra-constraints.c (simplify_operand_subreg): Force reload of

10334

+ paradoxical subreg if it is not in the class contents.

10335

+

10336

+2014-04-10 Jakub Jelinek <jakub@redhat.com>

10337

+

10338

+ Backport from mainline

10339

+ 2014-03-12 Jakub Jelinek <jakub@redhat.com>

10340

+ Marc Glisse <marc.glisse@inria.fr>

10341

+

10342

+ PR tree-optimization/60502

10343

+ * tree-ssa-reassoc.c (eliminate_not_pairs): Use build_all_ones_cst

10344

+ instead of build_low_bits_mask.

10345

+

10346

+ 2013-06-13 Marc Glisse <marc.glisse@inria.fr>

10347

+

10348

+ * tree.c (build_all_ones_cst): New function.

10349

+ * tree.h (build_all_ones_cst): Declare it.

10350

+

10351

+ 2013-05-10 Marc Glisse <marc.glisse@inria.fr>

10352

+

10353

+ * tree.c (build_minus_one_cst): New function.

10354

+ * tree.h (build_minus_one_cst): Declare new function.

10355

+

10356

+2014-04-10 Jakub Jelinek <jakub@redhat.com>

10357

+

10358

+ Backport from mainline

10359

+ 2014-03-28 Jakub Jelinek <jakub@redhat.com>

10360

+

10361

+ PR target/60693

10362

+ * config/i386/i386.c (ix86_copy_addr_to_reg): Call copy_addr_to_reg

10363

+ also if addr has VOIDmode.

10364

+

10365

+ 2014-03-17 Jakub Jelinek <jakub@redhat.com>

10366

+

10367

+ PR target/60516

10368

+ * config/i386/i386.c (ix86_expand_epilogue): Adjust REG_CFA_ADJUST_CFA

10369

+ note creation for the 2010-08-31 changes.

10370

+

10371

+ 2014-03-06 Jakub Jelinek <jakub@redhat.com>

10372

+ Meador Inge <meadori@codesourcery.com>

10373

+

10374

+ PR target/58595

10375

+ * config/arm/arm.c (arm_tls_symbol_p): Remove.

10376

+ (arm_legitimize_address): Call legitimize_tls_address for any

10377

+ arm_tls_referenced_p expression, handle constant addend. Call it

10378

+ before testing for !TARGET_ARM.

10379

+ (thumb_legitimize_address): Don't handle arm_tls_symbol_p here.

10380

+

10381

+2014-04-09 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10382

+

10383

+ Backport from mainline r208750

10384

+ 2014-03-21 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10385

+

10386

+ * config/rs6000/rs6000.c (rs6000_expand_vector_set): Generate a

10387

+ pattern for vector nor instead of subtract from splat(-1).

10388

+ (altivec_expand_vec_perm_const_le): Likewise.

10389

+

10390

+ Backport from mainline r209235

10391

+ 2014-04-08 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10392

+

10393

+ * config/rs6000/rs6000.c (rs6000_expand_vector_set): Use vnand

10394

+ instead of vnor to exploit possible fusion opportunity in the

10395

+ future.

10396

+ (altivec_expand_vec_perm_const_le): Likewise.

10397

+

10398

+2014-04-09 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10399

+

10400

+ Revert following patch

10401

+ 2014-04-08 Pat Haugen <pthaugen@us.ibm.com>

10402

+

10403

+ Backport from mainline

10404

+ 2014-04-08 Pat Haugen <pthaugen@us.ibm.com>

10405

+

10406

+ * config/rs6000/sync.md (AINT mode_iterator): Move definition.

10407

+ (loadsync_<mode>): Change mode.

10408

+ (load_quadpti, store_quadpti): New.

10409

+ (atomic_load<mode>, atomic_store<mode>): Add support for TI mode.

10410

+ * config/rs6000/rs6000.md (unspec enum): Add UNSPEC_LSQ.

10411

+

10412

+2014-04-09 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10413

+

10414

+ Backport from mainline r202642

10415

+ 2013-09-17 Alan Modra <amodra@gmail.com>

10416

+

10417

+ PR target/57589

10418

+ * config/rs6000/driver-rs6000.c (elf_platform): Revert 2013-06-11

10419

+ patch (r199972).

10420

+

10421

+2014-04-08 Pat Haugen <pthaugen@us.ibm.com>

10422

+

10423

+ Backport from mainline

10424

+ 2014-04-08 Pat Haugen <pthaugen@us.ibm.com>

10425

+

10426

+ * config/rs6000/sync.md (AINT mode_iterator): Move definition.

10427

+ (loadsync_<mode>): Change mode.

10428

+ (load_quadpti, store_quadpti): New.

10429

+ (atomic_load<mode>, atomic_store<mode>): Add support for TI mode.

10430

+ * config/rs6000/rs6000.md (unspec enum): Add UNSPEC_LSQ.

10431

+

10432

+2014-04-07 Martin Jambor <mjambor@suse.cz>

10433

+

10434

+ PR ipa/60640

10435

+ * ipa-cp.c (propagate_constants_accross_call): Do not propagate

10436

+ accross thunks.

10437

+

10438

+2014-04-07 Dominique d'Humieres <dominiq@lps.ens.fr>

10439

+

10440

+ Backport from mainline

10441

+ 2013-09-14 Iain Sandoe <iains@gcc.gnu.org>

10442

+

10443

+ PR target/48094

10444

+ * config/darwin.c (darwin_objc2_section): Note if ObjC Metadata

10445

+ is seen.

10446

+ (darwin_objc1_section): Likewise.

10447

+ (darwin_file_end): Emit Image Info section when required.

10448

+

10449

+2014-04-05 Alan Modra <amodra@gmail.com>

10450

+

10451

+ Apply from mainline

10452

+ 2014-01-28 Alan Modra <amodra@gmail.com>

10453

+ * Makefile.in (BUILD_CPPFLAGS): Do not use ALL_CPPFLAGS.

10454

+ * configure.ac <recursive call for build != host>: Define

10455

+ GENERATOR_FILE. Comment. Use CXX_FOR_BUILD, CXXFLAGS_FOR_BUILD

10456

+ and LD_FOR_BUILD too.

10457

+ * configure: Regenerate.

10458

+

10459

+2014-04-04 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

10460

+

10461

+ Backport from mainline r208895:

10462

+ 2014-03-28 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

10463

+

10464

+ * config/rs6000/rs6000.c (fusion_gpr_load_p): Refuse optimization

10465

+ if it would clobber the stack pointer, even temporarily.

10466

+

10467

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10468

+

10469

+ Back port from main line:

10470

+ 2014-04-01 Michael Meissner <meissner@linux.vnet.ibm.com>

10471

+

10472

+ * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions):

10473

+ Document vec_vgbbd.

10474

+

10475

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10476

+

10477

+ Back port mainline subversion id 209025.

10478

+ 2014-04-02 Michael Meissner <meissner@linux.vnet.ibm.com>

10479

+

10480

+ PR target/60735

10481

+ * config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): If we have

10482

+ software floating point or no floating point registers, do not

10483

+ allow any type in the FPRs. Eliminate a test for SPE SIMD types

10484

+ in GPRs that occurs after we tested for GPRs that would never be

10485

+ true.

10486

+

10487

+ * config/rs6000/rs6000.md (mov<mode>_softfloat32, FMOVE64):

10488

+ Rewrite tests to use TARGET_DOUBLE_FLOAT and TARGET_E500_DOUBLE,

10489

+ since the FMOVE64 type is DFmode/DDmode. If TARGET_E500_DOUBLE,

10490

+ specifically allow DDmode, since that does not use the SPE SIMD

10491

+ instructions.

10492

+

10493

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10494

+

10495

+ Backport from mainline r205308

10496

+ 2013-11-23 David Edelsohn <dje.gcc@gmail.com>

10497

+

10498

+ * config/rs6000/rs6000.c (IN_NAMED_SECTION): New macro.

10499

+ (rs6000_xcoff_select_section): Place decls with stricter alignment

10500

+ into named sections.

10501

+ (rs6000_xcoff_unique_section): Allow unique sections for

10502

+ uninitialized data with strict alignment.

10503

+

10504

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10505

+

10506

+ Backport from mainline

10507

+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

10508

+

10509

+ * gcc/configure: Regenerate.

10510

+

10511

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10512

+

10513

+ Back port from trunk

10514

+ 2013-04-25 Alan Modra <amodra@gmail.com>

10515

+

10516

+ PR target/57052

10517

+ * config/rs6000/rs6000.md (rotlsi3_internal7): Rename to

10518

+ rotlsi3_internal7le and condition on !BYTES_BIG_ENDIAN.

10519

+ (rotlsi3_internal8be): New BYTES_BIG_ENDIAN insn.

10520

+ Repeat for many other rotate/shift and mask patterns using subregs.

10521

+ Name lshiftrt insns.

10522

+ (ashrdisi3_noppc64): Rename to ashrdisi3_noppc64be and condition

10523

+ on WORDS_BIG_ENDIAN.

10524

+

10525

+ 2013-06-07 Alan Modra <amodra@gmail.com>

10526

+

10527

+ * config/rs6000/rs6000.c (rs6000_option_override_internal): Don't

10528

+ override user -mfp-in-toc.

10529

+ (offsettable_ok_by_alignment): Consider just the current access

10530

+ rather than the whole object, unless BLKmode. Handle

10531

+ CONSTANT_POOL_ADDRESS_P constants that lack a decl too.

10532

+ (use_toc_relative_ref): Allow CONSTANT_POOL_ADDRESS_P constants

10533

+ for -mcmodel=medium.

10534

+ * config/rs6000/linux64.h (SUBSUBTARGET_OVERRIDE_OPTIONS): Don't

10535

+ override user -mfp-in-toc or -msum-in-toc. Default to

10536

+ -mno-fp-in-toc for -mcmodel=medium.

10537

+

10538

+ 2013-06-18 Alan Modra <amodra@gmail.com>

10539

+

10540

+ * config/rs6000/rs6000.h (enum data_align): New.

10541

+ (LOCAL_ALIGNMENT, DATA_ALIGNMENT): Use rs6000_data_alignment.

10542

+ (DATA_ABI_ALIGNMENT): Define.

10543

+ (CONSTANT_ALIGNMENT): Correct comment.

10544

+ * config/rs6000/rs6000-protos.h (rs6000_data_alignment): Declare.

10545

+ * config/rs6000/rs6000.c (rs6000_data_alignment): New function.

10546

+

10547

+ 2013-07-11 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

10548

+

10549

+ * config/rs6000/rs6000.md (""*tls_gd_low<TLSmode:tls_abi_suffix>"):

10550

+ Require GOT register as additional operand in UNSPEC.

10551

+ ("*tls_ld_low<TLSmode:tls_abi_suffix>"): Likewise.

10552

+ ("*tls_got_dtprel_low<TLSmode:tls_abi_suffix>"): Likewise.

10553

+ ("*tls_got_tprel_low<TLSmode:tls_abi_suffix>"): Likewise.

10554

+ ("*tls_gd<TLSmode:tls_abi_suffix>"): Update splitter.

10555

+ ("*tls_ld<TLSmode:tls_abi_suffix>"): Likewise.

10556

+ ("tls_got_dtprel_<TLSmode:tls_abi_suffix>"): Likewise.

10557

+ ("tls_got_tprel_<TLSmode:tls_abi_suffix>"): Likewise.

10558

+

10559

+ 2014-01-23 Pat Haugen <pthaugen@us.ibm.com>

10560

+

10561

+ * config/rs6000/rs6000.c (rs6000_option_override_internal): Don't

10562

+ force flag_ira_loop_pressure if set via command line.

10563

+

10564

+ 2014-02-06 Alan Modra <amodra@gmail.com>

10565

+

10566

+ PR target/60032

10567

+ * config/rs6000/rs6000.c (rs6000_secondary_memory_needed_mode): Only

10568

+ change SDmode to DDmode when lra_in_progress.

10569

+

10570

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10571

+

10572

+ V1TImode Support

10573

+ Back port from trunk

10574

+ 2014-03-12 Michael Meissner <meissner@linux.vnet.ibm.com>

10575

+

10576

+ * config/rs6000/vector.md (VEC_L): Add V1TI mode to vector types.

10577

+ (VEC_M): Likewise.

10578

+ (VEC_N): Likewise.

10579

+ (VEC_R): Likewise.

10580

+ (VEC_base): Likewise.

10581

+ (mov<MODE>, VEC_M modes): If we are loading TImode into VSX

10582

+ registers, we need to swap double words in little endian mode.

10583

+

10584

+ * config/rs6000/rs6000-modes.def (V1TImode): Add new vector mode

10585

+ to be a container mode for 128-bit integer operations added in ISA

10586

+ 2.07. Unlike TImode and PTImode, the preferred register set is

10587

+ the Altivec/VMX registers for the 128-bit operations.

10588

+

10589

+ * config/rs6000/rs6000-protos.h (rs6000_move_128bit_ok_p): Add

10590

+ declarations.

10591

+ (rs6000_split_128bit_ok_p): Likewise.

10592

+

10593

+ * config/rs6000/rs6000-builtin.def (BU_P8V_AV_3): Add new support

10594

+ macros for creating ISA 2.07 normal and overloaded builtin

10595

+ functions with 3 arguments.

10596

+ (BU_P8V_OVERLOAD_3): Likewise.

10597

+ (VPERM_1T): Add support for V1TImode in 128-bit vector operations

10598

+ for use as overloaded functions.

10599

+ (VPERM_1TI_UNS): Likewise.

10600

+ (VSEL_1TI): Likewise.

10601

+ (VSEL_1TI_UNS): Likewise.

10602

+ (ST_INTERNAL_1ti): Likewise.

10603

+ (LD_INTERNAL_1ti): Likewise.

10604

+ (XXSEL_1TI): Likewise.

10605

+ (XXSEL_1TI_UNS): Likewise.

10606

+ (VPERM_1TI): Likewise.

10607

+ (VPERM_1TI_UNS): Likewise.

10608

+ (XXPERMDI_1TI): Likewise.

10609

+ (SET_1TI): Likewise.

10610

+ (LXVD2X_V1TI): Likewise.

10611

+ (STXVD2X_V1TI): Likewise.

10612

+ (VEC_INIT_V1TI): Likewise.

10613

+ (VEC_SET_V1TI): Likewise.

10614

+ (VEC_EXT_V1TI): Likewise.

10615

+ (EQV_V1TI): Likewise.

10616

+ (NAND_V1TI): Likewise.

10617

+ (ORC_V1TI): Likewise.

10618

+ (VADDCUQ): Add support for 128-bit integer arithmetic instructions

10619

+ added in ISA 2.07. Add both normal 'altivec' builtins, and the

10620

+ overloaded builtin.

10621

+ (VADDUQM): Likewise.

10622

+ (VSUBCUQ): Likewise.

10623

+ (VADDEUQM): Likewise.

10624

+ (VADDECUQ): Likewise.

10625

+ (VSUBEUQM): Likewise.

10626

+ (VSUBECUQ): Likewise.

10627

+

10628

+ * config/rs6000/rs6000-c.c (__int128_type): New static to hold

10629

+ __int128_t and __uint128_t types.

10630

+ (__uint128_type): Likewise.

10631

+ (altivec_categorize_keyword): Add support for vector __int128_t,

10632

+ vector __uint128_t, vector __int128, and vector unsigned __int128

10633

+ as a container type for TImode operations that need to be done in

10634

+ VSX/Altivec registers.

10635

+ (rs6000_macro_to_expand): Likewise.

10636

+ (altivec_overloaded_builtins): Add ISA 2.07 overloaded functions

10637

+ to support 128-bit integer instructions vaddcuq, vadduqm,

10638

+ vaddecuq, vaddeuqm, vsubcuq, vsubuqm, vsubecuq, vsubeuqm.

10639

+ (altivec_resolve_overloaded_builtin): Add support for V1TImode.

10640

+

10641

+ * config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): Add support

10642

+ for V1TImode, and set up preferences to use VSX/Altivec

10643

+ registers. Setup VSX reload handlers.

10644

+ (rs6000_debug_reg_global): Likewise.

10645

+ (rs6000_init_hard_regno_mode_ok): Likewise.

10646

+ (rs6000_preferred_simd_mode): Likewise.

10647

+ (vspltis_constant): Do not allow V1TImode as easy altivec

10648

+ constants.

10649

+ (easy_altivec_constant): Likewise.

10650

+ (output_vec_const_move): Likewise.

10651

+ (rs6000_expand_vector_set): Convert V1TImode set and extract to

10652

+ simple move.

10653

+ (rs6000_expand_vector_extract): Likewise.

10654

+ (reg_offset_addressing_ok_p): Setup V1TImode to use VSX reg+reg

10655

+ addressing.

10656

+ (rs6000_const_vec): Add support for V1TImode.

10657

+ (rs6000_emit_le_vsx_load): Swap double words when loading or

10658

+ storing TImode/V1TImode.

10659

+ (rs6000_emit_le_vsx_store): Likewise.

10660

+ (rs6000_emit_le_vsx_move): Likewise.

10661

+ (rs6000_emit_move): Add support for V1TImode.

10662

+ (altivec_expand_ld_builtin): Likewise.

10663

+ (altivec_expand_st_builtin): Likewise.

10664

+ (altivec_expand_vec_init_builtin): Likewise.

10665

+ (altivec_expand_builtin): Likewise.

10666

+ (rs6000_init_builtins): Add support for V1TImode type. Add

10667

+ support for ISA 2.07 128-bit integer builtins. Define type names

10668

+ for the VSX/Altivec vector types.

10669

+ (altivec_init_builtins): Add support for overloaded vector

10670

+ functions with V1TImode type.

10671

+ (rs6000_preferred_reload_class): Prefer Altivec registers for

10672

+ V1TImode.

10673

+ (rs6000_move_128bit_ok_p): Move 128-bit move/split validation to

10674

+ external function.

10675

+ (rs6000_split_128bit_ok_p): Likewise.

10676

+ (rs6000_handle_altivec_attribute): Create V1TImode from vector

10677

+ __int128_t and vector __uint128_t.

10678

+

10679

+ * config/rs6000/vsx.md (VSX_L): Add V1TImode to vector iterators

10680

+ and mode attributes.

10681

+ (VSX_M): Likewise.

10682

+ (VSX_M2): Likewise.

10683

+ (VSm): Likewise.

10684

+ (VSs): Likewise.

10685

+ (VSr): Likewise.

10686

+ (VSv): Likewise.

10687

+ (VS_scalar): Likewise.

10688

+ (VS_double): Likewise.

10689

+ (vsx_set_v1ti): New builtin function to create V1TImode from

10690

+ TImode.

10691

+

10692

+ * config/rs6000/rs6000.h (TARGET_VADDUQM): New macro to say

10693

+ whether we support the ISA 2.07 128-bit integer arithmetic

10694

+ instructions.

10695

+ (ALTIVEC_OR_VSX_VECTOR_MODE): Add V1TImode.

10696

+ (enum rs6000_builtin_type_index): Add fields to hold V1TImode

10697

+ and TImode types for use with the builtin functions.

10698

+ (V1TI_type_node): Likewise.

10699

+ (unsigned_V1TI_type_node): Likewise.

10700

+ (intTI_type_internal_node): Likewise.

10701

+ (uintTI_type_internal_node): Likewise.

10702

+

10703

+ * config/rs6000/altivec.md (UNSPEC_VADDCUQ): New unspecs for ISA

10704

+ 2.07 128-bit builtin functions.

10705

+ (UNSPEC_VADDEUQM): Likewise.

10706

+ (UNSPEC_VADDECUQ): Likewise.

10707

+ (UNSPEC_VSUBCUQ): Likewise.

10708

+ (UNSPEC_VSUBEUQM): Likewise.

10709

+ (UNSPEC_VSUBECUQ): Likewise.

10710

+ (VM): Add V1TImode to vector mode iterators.

10711

+ (VM2): Likewise.

10712

+ (VI_unit): Likewise.

10713

+ (altivec_vadduqm): Add ISA 2.07 128-bit binary builtins.

10714

+ (altivec_vaddcuq): Likewise.

10715

+ (altivec_vsubuqm): Likewise.

10716

+ (altivec_vsubcuq): Likewise.

10717

+ (altivec_vaddeuqm): Likewise.

10718

+ (altivec_vaddecuq): Likewise.

10719

+ (altivec_vsubeuqm): Likewise.

10720

+ (altivec_vsubecuq): Likewise.

10721

+

10722

+ * config/rs6000/rs6000.md (FMOVE128_GPR): Add V1TImode to vector

10723

+ mode iterators.

10724

+ (BOOL_128): Likewise.

10725

+ (BOOL_REGS_OUTPUT): Likewise.

10726

+ (BOOL_REGS_OP1): Likewise.

10727

+ (BOOL_REGS_OP2): Likewise.

10728

+ (BOOL_REGS_UNARY): Likewise.

10729

+ (BOOL_REGS_AND_CR0): Likewise.

10730

+

10731

+ * config/rs6000/altivec.h (vec_vaddcuq): Add support for ISA 2.07

10732

+ 128-bit integer builtin support.

10733

+ (vec_vadduqm): Likewise.

10734

+ (vec_vaddecuq): Likewise.

10735

+ (vec_vaddeuqm): Likewise.

10736

+ (vec_vsubecuq): Likewise.

10737

+ (vec_vsubeuqm): Likewise.

10738

+ (vec_vsubcuq): Likewise.

10739

+ (vec_vsubuqm): Likewise.

10740

+

10741

+ * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions):

10742

+ Document vec_vaddcuq, vec_vadduqm, vec_vaddecuq, vec_vaddeuqm,

10743

+ vec_subecuq, vec_subeuqm, vec_vsubcuq, vec_vsubeqm builtins adding

10744

+ 128-bit integer add/subtract to ISA 2.07.

10745

+

10746

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10747

+

10748

+ Apply mainline r207798

10749

+ 2014-02-26 Alan Modra <amodra@gmail.com>

10750

+ PR target/58675

10751

+ PR target/57935

10752

+ * config/rs6000/rs6000.c (rs6000_secondary_reload_inner): Use

10753

+ find_replacement on parts of insn rtl that might be reloaded.

10754

+

10755

+ Backport from mainline r208287

10756

+ 2014-03-03 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10757

+

10758

+ * config/rs6000/rs6000.c (rs6000_preferred_reload_class): Disallow

10759

+ reload of PLUS rtx's outside of GENERAL_REGS or BASE_REGS; relax

10760

+ constraint on constants to permit them being loaded into

10761

+ GENERAL_REGS or BASE_REGS.

10762

+

10763

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10764

+

10765

+ Backport from mainline r207699.

10766

+ 2014-02-11 Michael Meissner <meissner@linux.vnet.ibm.com>

10767

+

10768

+ PR target/60137

10769

+ * config/rs6000/rs6000.md (128-bit GPR splitter): Add a splitter

10770

+ for VSX/Altivec vectors that land in GPR registers.

10771

+

10772

+ Backport from mainline r207808.

10773

+ 2014-02-15 Michael Meissner <meissner@linux.vnet.ibm.com>

10774

+

10775

+ PR target/60203

10776

+ * config/rs6000/rs6000.md (rreg): Add TFmode, TDmode constraints.

10777

+ (mov<mode>_internal, TFmode/TDmode): Split TFmode/TDmode moves

10778

+ into 64-bit and 32-bit moves. On 64-bit moves, add support for

10779

+ using direct move instructions on ISA 2.07. Also adjust

10780

+ instruction length for 64-bit.

10781

+ (mov<mode>_64bit, TFmode/TDmode): Likewise.

10782

+ (mov<mode>_32bit, TFmode/TDmode): Likewise.

10783

+

10784

+ Backport from mainline r207868.

10785

+ 2014-02-18 Michael Meissner <meissner@linux.vnet.ibm.com>

10786

+

10787

+ PR target/60203

10788

+ * config/rs6000/rs6000.md (mov<mode>_64bit, TF/TDmode moves):

10789

+ Split 64-bit moves into 2 patterns. Do not allow the use of

10790

+ direct move for TDmode in little endian, since the decimal value

10791

+ has little endian bytes within a word, but the 64-bit pieces are

10792

+ ordered in a big endian fashion, and normal subreg's of TDmode are

10793

+ not allowed.

10794

+ (mov<mode>_64bit_dm): Likewise.

10795

+ (movtd_64bit_nodm): Likewise.

10796

+

10797

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10798

+

10799

+ Backport from mainline r207658

10800

+ 2014-02-06 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

10801

+

10802

+ * config/rs6000/sysv4.h (ENDIAN_SELECT): Do not attempt to enforce

10803

+ big-endian mode for -mcall-aixdesc, -mcall-freebsd, -mcall-netbsd,

10804

+ -mcall-openbsd, or -mcall-linux.

10805

+ (CC1_ENDIAN_BIG_SPEC): Remove.

10806

+ (CC1_ENDIAN_LITTLE_SPEC): Remove.

10807

+ (CC1_ENDIAN_DEFAULT_SPEC): Remove.

10808

+ (CC1_SPEC): Remove (always empty) %cc1_endian_... spec.

10809

+ (SUBTARGET_EXTRA_SPECS): Remove %cc1_endian_big, %cc1_endian_little,

10810

+ and %cc1_endian_default.

10811

+ * config/rs6000/sysv4le.h (CC1_ENDIAN_DEFAULT_SPEC): Remove.

10812

+

10813

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10814

+

10815

+ Little Endian Vector API Support

10816

+ Backport from mainline r206443

10817

+ 2014-01-08 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10818

+

10819

+ * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Remove

10820

+ two duplicate entries.

10821

+

10822

+ Backport from mainline r206494

10823

+ 2014-01-09 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10824

+

10825

+ * doc/invoke.texi: Add -maltivec={be,le} options, and document

10826

+ default element-order behavior for -maltivec.

10827

+ * config/rs6000/rs6000.opt: Add -maltivec={be,le} options.

10828

+ * config/rs6000/rs6000.c (rs6000_option_override_internal): Ensure

10829

+ that -maltivec={le,be} implies -maltivec; disallow -maltivec=le

10830

+ when targeting big endian, at least for now.

10831

+ * config/rs6000/rs6000.h: Add #define of VECTOR_ELT_ORDER_BIG.

10832

+

10833

+ Backport from mainline r206541

10834

+ 2014-01-10 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10835

+

10836

+ * config/rs6000/rs6000-builtin.def: Fix pasto for VPKSDUS.

10837

+

10838

+ Backport from mainline r206590

10839

+ 2014-01-13 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10840

+

10841

+ * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin):

10842

+ Implement -maltivec=be for vec_insert and vec_extract.

10843

+

10844

+ Backport from mainline r206641

10845

+ 2014-01-15 Bill Schmidt <wschmidt@vnet.linux.ibm.com>

10846

+

10847

+ * config/rs6000/altivec.md (mulv8hi3): Explicitly generate vmulesh

10848

+ and vmulosh rather than call gen_vec_widen_smult_*.

10849

+ (vec_widen_umult_even_v16qi): Test VECTOR_ELT_ORDER_BIG rather

10850

+ than BYTES_BIG_ENDIAN to determine use of even or odd instruction.

10851

+ (vec_widen_smult_even_v16qi): Likewise.

10852

+ (vec_widen_umult_even_v8hi): Likewise.

10853

+ (vec_widen_smult_even_v8hi): Likewise.

10854

+ (vec_widen_umult_odd_v16qi): Likewise.

10855

+ (vec_widen_smult_odd_v16qi): Likewise.

10856

+ (vec_widen_umult_odd_v8hi): Likewise.

10857

+ (vec_widen_smult_odd_v8hi): Likewise.

10858

+ (vec_widen_umult_hi_v16qi): Explicitly generate vmuleub and

10859

+ vmuloub rather than call gen_vec_widen_umult_*.

10860

+ (vec_widen_umult_lo_v16qi): Likewise.

10861

+ (vec_widen_smult_hi_v16qi): Explicitly generate vmulesb and

10862

+ vmulosb rather than call gen_vec_widen_smult_*.

10863

+ (vec_widen_smult_lo_v16qi): Likewise.

10864

+ (vec_widen_umult_hi_v8hi): Explicitly generate vmuleuh and vmulouh

10865

+ rather than call gen_vec_widen_umult_*.

10866

+ (vec_widen_umult_lo_v8hi): Likewise.

10867

+ (vec_widen_smult_hi_v8hi): Explicitly gnerate vmulesh and vmulosh

10868

+ rather than call gen_vec_widen_smult_*.

10869

+ (vec_widen_smult_lo_v8hi): Likewise.

10870

+

10871

+ Backport from mainline r207062

10872

+ 2014-01-24 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10873

+

10874

+ * config/rs6000/rs6000.c (rs6000_expand_vec_perm_const_1): Remove

10875

+ correction for little endian...

10876

+ * config/rs6000/vsx.md (vsx_xxpermdi2_<mode>_1): ...and move it to

10877

+ here.

10878

+

10879

+ Backport from mainline r207262

10880

+ 2014-01-29 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10881

+

10882

+ * config/rs6000/rs6000.c (altivec_expand_vec_perm_const): Use

10883

+ CODE_FOR_altivec_vmrg*_direct rather than CODE_FOR_altivec_vmrg*.

10884

+ * config/rs6000/vsx.md (vsx_mergel_<mode>): Adjust for

10885

+ -maltivec=be with LE targets.

10886

+ (vsx_mergeh_<mode>): Likewise.

10887

+ * config/rs6000/altivec.md (UNSPEC_VMRG[HL]_DIRECT): New

10888

+ unspecs.

10889

+ (mulv8hi3): Use gen_altivec_vmrg[hl]w_direct.

10890

+ (altivec_vmrghb): Replace with define_expand and new

10891

+ *altivec_vmrghb_internal insn; adjust for -maltivec=be with LE

10892

+ targets.

10893

+ (altivec_vmrghb_direct): New define_insn.

10894

+ (altivec_vmrghh): Replace with define_expand and new

10895

+ *altivec_vmrghh_internal insn; adjust for -maltivec=be with LE

10896

+ targets.

10897

+ (altivec_vmrghh_direct): New define_insn.

10898

+ (altivec_vmrghw): Replace with define_expand and new

10899

+ *altivec_vmrghw_internal insn; adjust for -maltivec=be with LE

10900

+ targets.

10901

+ (altivec_vmrghw_direct): New define_insn.

10902

+ (*altivec_vmrghsf): Adjust for endianness.

10903

+ (altivec_vmrglb): Replace with define_expand and new

10904

+ *altivec_vmrglb_internal insn; adjust for -maltivec=be with LE

10905

+ targets.

10906

+ (altivec_vmrglb_direct): New define_insn.

10907

+ (altivec_vmrglh): Replace with define_expand and new

10908

+ *altivec_vmrglh_internal insn; adjust for -maltivec=be with LE

10909

+ targets.

10910

+ (altivec_vmrglh_direct): New define_insn.

10911

+ (altivec_vmrglw): Replace with define_expand and new

10912

+ *altivec_vmrglw_internal insn; adjust for -maltivec=be with LE

10913

+ targets.

10914

+ (altivec_vmrglw_direct): New define_insn.

10915

+ (*altivec_vmrglsf): Adjust for endianness.

10916

+ (vec_widen_umult_hi_v16qi): Use gen_altivec_vmrghh_direct.

10917

+ (vec_widen_umult_lo_v16qi): Use gen_altivec_vmrglh_direct.

10918

+ (vec_widen_smult_hi_v16qi): Use gen_altivec_vmrghh_direct.

10919

+ (vec_widen_smult_lo_v16qi): Use gen_altivec_vmrglh_direct.

10920

+ (vec_widen_umult_hi_v8hi): Use gen_altivec_vmrghw_direct.

10921

+ (vec_widen_umult_lo_v8hi): Use gen_altivec_vmrglw_direct.

10922

+ (vec_widen_smult_hi_v8hi): Use gen_altivec_vmrghw_direct.

10923

+ (vec_widen_smult_lo_v8hi): Use gen_altivec_vmrglw_direct.

10924

+

10925

+ Backport from mainline r207318

10926

+ 2014-01-30 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10927

+

10928

+ * gcc/config/rs6000/rs6000.c (rs6000_expand_vector_init): Use

10929

+ gen_vsx_xxspltw_v4sf_direct instead of gen_vsx_xxspltw_v4sf;

10930

+ remove element index adjustment for endian (now handled in vsx.md

10931

+ and altivec.md).

10932

+ (altivec_expand_vec_perm_const): Use

10933

+ gen_altivec_vsplt[bhw]_direct instead of gen_altivec_vsplt[bhw].

10934

+ * gcc/config/rs6000/vsx.md (UNSPEC_VSX_XXSPLTW): New unspec.

10935

+ (vsx_xxspltw_<mode>): Adjust element index for little endian.

10936

+ * gcc/config/rs6000/altivec.md (altivec_vspltb): Divide into a

10937

+ define_expand and a new define_insn *altivec_vspltb_internal;

10938

+ adjust for -maltivec=be on a little endian target.

10939

+ (altivec_vspltb_direct): New.

10940

+ (altivec_vsplth): Divide into a define_expand and a new

10941

+ define_insn *altivec_vsplth_internal; adjust for -maltivec=be on a

10942

+ little endian target.

10943

+ (altivec_vsplth_direct): New.

10944

+ (altivec_vspltw): Divide into a define_expand and a new

10945

+ define_insn *altivec_vspltw_internal; adjust for -maltivec=be on a

10946

+ little endian target.

10947

+ (altivec_vspltw_direct): New.

10948

+ (altivec_vspltsf): Divide into a define_expand and a new

10949

+ define_insn *altivec_vspltsf_internal; adjust for -maltivec=be on

10950

+ a little endian target.

10951

+

10952

+ Backport from mainline r207326

10953

+ 2014-01-30 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10954

+

10955

+ * config/rs6000/rs6000.c (rs6000_expand_vector_init): Remove

10956

+ unused variable "field".

10957

+ * config/rs6000/vsx.md (vsx_mergel_<mode>): Add missing DONE.

10958

+ (vsx_mergeh_<mode>): Likewise.

10959

+ * config/rs6000/altivec.md (altivec_vmrghb): Likewise.

10960

+ (altivec_vmrghh): Likewise.

10961

+ (altivec_vmrghw): Likewise.

10962

+ (altivec_vmrglb): Likewise.

10963

+ (altivec_vmrglh): Likewise.

10964

+ (altivec_vmrglw): Likewise.

10965

+ (altivec_vspltb): Add missing uses.

10966

+ (altivec_vsplth): Likewise.

10967

+ (altivec_vspltw): Likewise.

10968

+ (altivec_vspltsf): Likewise.

10969

+

10970

+ Backport from mainline r207414

10971

+ 2014-02-02 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10972

+

10973

+ * config/rs6000/altivec.md (UNSPEC_VSUMSWS_DIRECT): New unspec.

10974

+ (altivec_vsumsws): Add handling for -maltivec=be with a little

10975

+ endian target.

10976

+ (altivec_vsumsws_direct): New.

10977

+ (reduc_splus_<mode>): Call gen_altivec_vsumsws_direct instead of

10978

+ gen_altivec_vsumsws.

10979

+

10980

+ Backport from mainline r207415

10981

+ 2014-02-02 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10982

+

10983

+ * config/rs6000/rs6000.c (altivec_expand_vec_perm_le): Generalize

10984

+ for vector types other than V16QImode.

10985

+ * config/rs6000/altivec.md (altivec_vperm_<mode>): Change to a

10986

+ define_expand, and call altivec_expand_vec_perm_le when producing

10987

+ code with little endian element order.

10988

+ (*altivec_vperm_<mode>_internal): New insn having previous

10989

+ behavior of altivec_vperm_<mode>.

10990

+ (altivec_vperm_<mode>_uns): Change to a define_expand, and call

10991

+ altivec_expand_vec_perm_le when producing code with little endian

10992

+ element order.

10993

+ (*altivec_vperm_<mode>_uns_internal): New insn having previous

10994

+ behavior of altivec_vperm_<mode>_uns.

10995

+

10996

+ Backport from mainline r207520

10997

+ 2014-02-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

10998

+

10999

+ * altivec.md (UNSPEC_VPACK_UNS_UNS_MOD_DIRECT): New unspec.

11000

+ (UNSPEC_VUNPACK_HI_SIGN_DIRECT): Likewise.

11001

+ (UNSPEC_VUNPACK_LO_SIGN_DIRECT): Likewise.

11002

+ (mulv8hi3): Use gen_altivec_vpkuwum_direct instead of

11003

+ gen_altivec_vpkuwum.

11004

+ (altivec_vpkpx): Test for VECTOR_ELT_ORDER_BIG instead of for

11005

+ BYTES_BIG_ENDIAN.

11006

+ (altivec_vpks<VI_char>ss): Likewise.

11007

+ (altivec_vpks<VI_char>us): Likewise.

11008

+ (altivec_vpku<VI_char>us): Likewise.

11009

+ (altivec_vpku<VI_char>um): Likewise.

11010

+ (altivec_vpku<VI_char>um_direct): New (copy of

11011

+ altivec_vpku<VI_char>um that still relies on BYTES_BIG_ENDIAN, for

11012

+ internal use).

11013

+ (altivec_vupkhs<VU_char>): Emit vupkls* instead of vupkhs* when

11014

+ target is little endian and -maltivec=be is not specified.

11015

+ (*altivec_vupkhs<VU_char>_direct): New (copy of

11016

+ altivec_vupkhs<VU_char> that always emits vupkhs*, for internal

11017

+ use).

11018

+ (altivec_vupkls<VU_char>): Emit vupkhs* instead of vupkls* when

11019

+ target is little endian and -maltivec=be is not specified.

11020

+ (*altivec_vupkls<VU_char>_direct): New (copy of

11021

+ altivec_vupkls<VU_char> that always emits vupkls*, for internal

11022

+ use).

11023

+ (altivec_vupkhpx): Emit vupklpx instead of vupkhpx when target is

11024

+ little endian and -maltivec=be is not specified.

11025

+ (altivec_vupklpx): Emit vupkhpx instead of vupklpx when target is

11026

+ little endian and -maltivec=be is not specified.

11027

+

11028

+ Backport from mainline r207521

11029

+ 2014-02-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11030

+

11031

+ * config/rs6000/altivec.md (altivec_vsum2sws): Adjust code

11032

+ generation for -maltivec=be.

11033

+ (altivec_vsumsws): Simplify redundant test.

11034

+

11035

+ Backport from mainline r207525

11036

+ 2014-02-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11037

+

11038

+ * config/rs6000/rs6000.c (altivec_expand_vec_perm_const): Change

11039

+ CODE_FOR_altivec_vpku[hw]um to

11040

+ CODE_FOR_altivec_vpku[hw]um_direct.

11041

+ * config/rs6000/altivec.md (vec_unpacks_hi_<VP_small_lc>): Change

11042

+ UNSPEC_VUNPACK_HI_SIGN to UNSPEC_VUNPACK_HI_SIGN_DIRECT.

11043

+ (vec_unpacks_lo_<VP_small_lc>): Change UNSPEC_VUNPACK_LO_SIGN to

11044

+ UNSPEC_VUNPACK_LO_SIGN_DIRECT.

11045

+

11046

+ Backport from mainline r207814.

11047

+ 2014-02-16 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11048

+

11049

+ * config/rs6000/vsx.md (vsx_xxpermdi_<mode>): Handle little

11050

+ endian targets.

11051

+

11052

+ Backport from mainline r207815.

11053

+ 2014-02-16 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11054

+

11055

+ * config/rs6000/altivec.md (p8_vmrgew): Handle little endian

11056

+ targets.

11057

+ (p8_vmrgow): Likewise.

11058

+

11059

+ Backport from mainline r207919.

11060

+ 2014-02-19 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11061

+

11062

+ * config/rs6000/rs6000.c (vspltis_constant): Fix most significant

11063

+ bit of zero.

11064

+

11065

+ Backport from mainline 208019

11066

+ 2014-02-21 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11067

+

11068

+ * config/rs6000/altivec.md (altivec_lvxl): Rename as

11069

+ *altivec_lvxl_<mode>_internal and use VM2 iterator instead of

11070

+ V4SI.

11071

+ (altivec_lvxl_<mode>): New define_expand incorporating

11072

+ -maltivec=be semantics where needed.

11073

+ (altivec_lvx): Rename as *altivec_lvx_<mode>_internal.

11074

+ (altivec_lvx_<mode>): New define_expand incorporating -maltivec=be

11075

+ semantics where needed.

11076

+ (altivec_stvx): Rename as *altivec_stvx_<mode>_internal.

11077

+ (altivec_stvx_<mode>): New define_expand incorporating

11078

+ -maltivec=be semantics where needed.

11079

+ (altivec_stvxl): Rename as *altivec_stvxl_<mode>_internal and use

11080

+ VM2 iterator instead of V4SI.

11081

+ (altivec_stvxl_<mode>): New define_expand incorporating

11082

+ -maltivec=be semantics where needed.

11083

+ * config/rs6000/rs6000-builtin.def: Add new built-in definitions

11084

+ LVXL_V2DF, LVXL_V2DI, LVXL_V4SF, LVXL_V4SI, LVXL_V8HI, LVXL_V16QI,

11085

+ LVX_V2DF, LVX_V2DI, LVX_V4SF, LVX_V4SI, LVX_V8HI, LVX_V16QI,

11086

+ STVX_V2DF, STVX_V2DI, STVX_V4SF, STVX_V4SI, STVX_V8HI, STVX_V16QI,

11087

+ STVXL_V2DF, STVXL_V2DI, STVXL_V4SF, STVXL_V4SI, STVXL_V8HI,

11088

+ STVXL_V16QI.

11089

+ * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Replace

11090

+ ALTIVEC_BUILTIN_LVX with ALTIVEC_BUILTIN_LVX_<MODE> throughout;

11091

+ similarly for ALTIVEC_BUILTIN_LVXL, ALTIVEC_BUILTIN_STVX, and

11092

+ ALTIVEC_BUILTIN_STVXL.

11093

+ * config/rs6000/rs6000-protos.h (altivec_expand_lvx_be): New

11094

+ prototype.

11095

+ (altivec_expand_stvx_be): Likewise.

11096

+ * config/rs6000/rs6000.c (swap_selector_for_mode): New function.

11097

+ (altivec_expand_lvx_be): Likewise.

11098

+ (altivec_expand_stvx_be): Likewise.

11099

+ (altivec_expand_builtin): Add cases for

11100

+ ALTIVEC_BUILTIN_STVX_<MODE>, ALTIVEC_BUILTIN_STVXL_<MODE>,

11101

+ ALTIVEC_BUILTIN_LVXL_<MODE>, and ALTIVEC_BUILTIN_LVX_<MODE>.

11102

+ (altivec_init_builtins): Add definitions for

11103

+ __builtin_altivec_lvxl_<mode>, __builtin_altivec_lvx_<mode>,

11104

+ __builtin_altivec_stvx_<mode>, and

11105

+ __builtin_altivec_stvxl_<mode>.

11106

+

11107

+ Backport from mainline 208021

11108

+ 2014-02-21 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11109

+

11110

+ * config/rs6000/altivec.md (altivec_vsumsws): Replace second

11111

+ vspltw with vsldoi.

11112

+ (reduc_uplus_v16qi): Use gen_altivec_vsumsws_direct instead of

11113

+ gen_altivec_vsumsws.

11114

+

11115

+ Backport from mainline 208049

11116

+ 2014-02-23 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11117

+

11118

+ * config/rs6000/altivec.md (altivec_lve<VI_char>x): Replace

11119

+ define_insn with define_expand and new define_insn

11120

+ *altivec_lve<VI_char>x_internal.

11121

+ (altivec_stve<VI_char>x): Replace define_insn with define_expand

11122

+ and new define_insn *altivec_stve<VI_char>x_internal.

11123

+ * config/rs6000/rs6000-protos.h (altivec_expand_stvex_be): New

11124

+ prototype.

11125

+ * config/rs6000/rs6000.c (altivec_expand_lvx_be): Document use by

11126

+ lve*x built-ins.

11127

+ (altivec_expand_stvex_be): New function.

11128

+

11129

+ Backport from mainline

11130

+ 2014-02-23 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11131

+ * config/rs6000/rs6000.c (rs6000_emit_le_vsx_move): Relax assert

11132

+ to permit subregs.

11133

+

11134

+ Backport from mainline

11135

+ 2014-02-25 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11136

+ * config/rs6000/vector.md (*vector_unordered<mode>): Change split

11137

+ to use canonical form for nor<mode>3.

11138

+

11139

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11140

+

11141

+ Backport from mainline

11142

+ 2014-02-04 Michael Meissner <meissner@linux.vnet.ibm.com>

11143

+

11144

+ * config/rs6000/rs6000.opt (-mlra): Add switch to enable the LRA

11145

+ register allocator.

11146

+

11147

+ * config/rs6000/rs6000.c (TARGET_LRA_P): Add support for -mlra to

11148

+ enable the LRA register allocator. Back port the changes from the

11149

+ trunk to enable LRA.

11150

+ (rs6000_legitimate_offset_address_p): Likewise.

11151

+ (legitimate_lo_sum_address_p): Likewise.

11152

+ (use_toc_relative_ref): Likewise.

11153

+ (rs6000_legitimate_address_p): Likewise.

11154

+ (rs6000_emit_move): Likewise.

11155

+ (rs6000_secondary_memory_needed_mode): Likewise.

11156

+ (rs6000_alloc_sdmode_stack_slot): Likewise.

11157

+ (rs6000_lra_p): Likewise.

11158

+

11159

+ * config/rs6000/sync.md (load_lockedti): Copy TI/PTI variables by

11160

+ 64-bit parts to force the register allocator to allocate even/odd

11161

+ register pairs for the quad word atomic instructions.

11162

+ (store_conditionalti): Likewise.

11163

+

11164

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11165

+

11166

+ Back port from mainline

11167

+ 2014-01-23 Michael Meissner <meissner@linux.vnet.ibm.com>

11168

+

11169

+ PR target/59909

11170

+ * doc/invoke.texi (RS/6000 and PowerPC Options): Document

11171

+ -mquad-memory-atomic. Update -mquad-memory documentation to say

11172

+ it is only used for non-atomic loads/stores.

11173

+

11174

+ * config/rs6000/predicates.md (quad_int_reg_operand): Allow either

11175

+ -mquad-memory or -mquad-memory-atomic switches.

11176

+

11177

+ * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Add

11178

+ -mquad-memory-atomic to ISA 2.07 support.

11179

+

11180

+ * config/rs6000/rs6000.opt (-mquad-memory-atomic): Add new switch

11181

+ to separate support of normal quad word memory operations (ldq,

11182

+ stq) from the atomic quad word memory operations.

11183

+

11184

+ * config/rs6000/rs6000.c (rs6000_option_override_internal): Add

11185

+ support to separate non-atomic quad word operations from atomic

11186

+ quad word operations. Disable non-atomic quad word operations in

11187

+ little endian mode so that we don't have to swap words after the

11188

+ load and before the store.

11189

+ (quad_load_store_p): Add comment about atomic quad word support.

11190

+ (rs6000_opt_masks): Add -mquad-memory-atomic to the list of

11191

+ options printed with -mdebug=reg.

11192

+

11193

+ * config/rs6000/rs6000.h (TARGET_SYNC_TI): Use

11194

+ -mquad-memory-atomic as the test for whether we have quad word

11195

+ atomic instructions.

11196

+ (TARGET_SYNC_HI_QI): If either -mquad-memory-atomic,

11197

+ -mquad-memory, or -mp8-vector are used, allow byte/half-word

11198

+ atomic operations.

11199

+

11200

+ * config/rs6000/sync.md (load_lockedti): Insure that the address

11201

+ is a proper indexed or indirect address for the lqarx instruction.

11202

+ On little endian systems, swap the hi/lo registers after the lqarx

11203

+ instruction.

11204

+ (load_lockedpti): Use indexed_or_indirect_operand predicate to

11205

+ insure the address is valid for the lqarx instruction.

11206

+ (store_conditionalti): Insure that the address is a proper indexed

11207

+ or indirect address for the stqcrx. instruction. On little endian

11208

+ systems, swap the hi/lo registers before doing the stqcrx.

11209

+ instruction.

11210

+ (store_conditionalpti): Use indexed_or_indirect_operand predicate to

11211

+ insure the address is valid for the stqcrx. instruction.

11212

+

11213

+ * gcc/config/rs6000/rs6000-c.c (rs6000_target_modify_macros):

11214

+ Define __QUAD_MEMORY__ and __QUAD_MEMORY_ATOMIC__ based on what

11215

+ type of quad memory support is available.

11216

+

11217

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11218

+

11219

+ Apply mainline r202190, powerpc64le multilibs and multiarch dir

11220

+ 2013-09-03 Alan Modra <amodra@gmail.com>

11221

+

11222

+ * config.gcc (powerpc*-*-linux*): Add support for little-endian

11223

+ multilibs to big-endian target and vice versa.

11224

+ * config/rs6000/t-linux64: Use := assignment on all vars.

11225

+ (MULTILIB_EXTRA_OPTS): Remove fPIC.

11226

+ (MULTILIB_OSDIRNAMES): Specify using mapping from multilib_options.

11227

+ * config/rs6000/t-linux64le: New file.

11228

+ * config/rs6000/t-linux64bele: New file.

11229

+ * config/rs6000/t-linux64lebe: New file.

11230

+

11231

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11232

+

11233

+ Back port from mainline

11234

+ 2014-01-16 Michael Meissner <meissner@linux.vnet.ibm.com>

11235

+

11236

+ PR target/59844

11237

+ * config/rs6000/rs6000.md (reload_vsx_from_gprsf): Add little

11238

+ endian support, remove tests for WORDS_BIG_ENDIAN.

11239

+ (p8_mfvsrd_3_<mode>): Likewise.

11240

+ (reload_gpr_from_vsx<mode>): Likewise.

11241

+ (reload_gpr_from_vsxsf): Likewise.

11242

+ (p8_mfvsrd_4_disf): Likewise.

11243

+

11244

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11245

+

11246

+ Backport from mainline

11247

+ 2013-04-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11248

+

11249

+ PR target/56843

11250

+ * config/rs6000/rs6000.c (rs6000_emit_swdiv_high_precision): Remove.

11251

+ (rs6000_emit_swdiv_low_precision): Remove.

11252

+ (rs6000_emit_swdiv): Rewrite to handle between one and four

11253

+ iterations of Newton-Raphson generally; modify required number of

11254

+ iterations for some cases.

11255

+ * config/rs6000/rs6000.h (RS6000_RECIP_HIGH_PRECISION_P): Remove.

11256

+

11257

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11258

+

11259

+ Backport from mainline

11260

+ 2013-08-19 Peter Bergner <bergner@vnet.ibm.com>

11261

+ Jakub Jelinek <jakub@redhat.com>

11262

+

11263

+ * builtins.def (BUILT_IN_FABSD32): New DFP ABS builtin.

11264

+ (BUILT_IN_FABSD64): Likewise.

11265

+ (BUILT_IN_FABSD128): Likewise.

11266

+ * builtins.c (expand_builtin): Add support for

11267

+ new DFP ABS builtins.

11268

+ (fold_builtin_1): Likewise.

11269

+ * config/rs6000/dfp.md

11270

+ (*abstd2_fpr): Handle non-overlapping destination

11271

+ and source operands.

11272

+ (*nabstd2_fpr): Likewise.

11273

+

11274

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11275

+

11276

+ Apply mainline r205060.

11277

+ 2013-11-20 Alan Modra <amodra@gmail.com>

11278

+ * config/rs6000/sysv4.h (CC1_ENDIAN_LITTLE_SPEC): Define as empty.

11279

+ * config/rs6000/rs6000.c (rs6000_option_override_internal): Default

11280

+ to strict alignment on older processors when little-endian.

11281

+ * config/rs6000/linux64.h (PROCESSOR_DEFAULT64): Default to power8

11282

+ for ELFv2.

11283

+

11284

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11285

+

11286

+ POWER ELFv2 ABI Support

11287

+ Backport from mainline r204842:

11288

+

11289

+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

11290

+

11291

+ * doc/invoke.texi (-mabi=elfv1, -mabi=elfv2): Document.

11292

+

11293

+ Backport from mainline r204809:

11294

+

11295

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

11296

+

11297

+ * config/rs6000/sysv4le.h (LINUX64_DEFAULT_ABI_ELFv2): Define.

11298

+

11299

+ Backport from mainline r204808:

11300

+

11301

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

11302

+ Alan Modra <amodra@gmail.com>

11303

+

11304

+ * config/rs6000/rs6000.h (RS6000_SAVE_AREA): Handle ABI_ELFv2.

11305

+ (RS6000_SAVE_TOC): Remove.

11306

+ (RS6000_TOC_SAVE_SLOT): New macro.

11307

+ * config/rs6000/rs6000.c (rs6000_parm_offset): New function.

11308

+ (rs6000_parm_start): Use it.

11309

+ (rs6000_function_arg_advance_1): Likewise.

11310

+ (rs6000_emit_prologue): Use RS6000_TOC_SAVE_SLOT.

11311

+ (rs6000_emit_epilogue): Likewise.

11312

+ (rs6000_call_aix): Likewise.

11313

+ (rs6000_output_function_prologue): Do not save/restore r11

11314

+ around calling _mcount for ABI_ELFv2.

11315

+

11316

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

11317

+ Alan Modra <amodra@gmail.com>

11318

+

11319

+ * config/rs6000/rs6000-protos.h (rs6000_reg_parm_stack_space):

11320

+ Add prototype.

11321

+ * config/rs6000/rs6000.h (RS6000_REG_SAVE): Remove.

11322

+ (REG_PARM_STACK_SPACE): Call rs6000_reg_parm_stack_space.

11323

+ * config/rs6000/rs6000.c (rs6000_parm_needs_stack): New function.

11324

+ (rs6000_function_parms_need_stack): Likewise.

11325

+ (rs6000_reg_parm_stack_space): Likewise.

11326

+ (rs6000_function_arg): Do not replace BLKmode by Pmode when

11327

+ returning a register argument.

11328

+

11329

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

11330

+ Michael Gschwind <mkg@us.ibm.com>

11331

+

11332

+ * config/rs6000/rs6000.h (FP_ARG_MAX_RETURN): New macro.

11333

+ (ALTIVEC_ARG_MAX_RETURN): Likewise.

11334

+ (FUNCTION_VALUE_REGNO_P): Use them.

11335

+ * config/rs6000/rs6000.c (TARGET_RETURN_IN_MSB): Define.

11336

+ (rs6000_return_in_msb): New function.

11337

+ (rs6000_return_in_memory): Handle ELFv2 homogeneous aggregates.

11338

+ Handle aggregates of up to 16 bytes for ELFv2.

11339

+ (rs6000_function_value): Handle ELFv2 homogeneous aggregates.

11340

+

11341

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

11342

+ Michael Gschwind <mkg@us.ibm.com>

11343

+

11344

+ * config/rs6000/rs6000.h (AGGR_ARG_NUM_REG): Define.

11345

+ * config/rs6000/rs6000.c (rs6000_aggregate_candidate): New function.

11346

+ (rs6000_discover_homogeneous_aggregate): Likewise.

11347

+ (rs6000_function_arg_boundary): Handle homogeneous aggregates.

11348

+ (rs6000_function_arg_advance_1): Likewise.

11349

+ (rs6000_function_arg): Likewise.

11350

+ (rs6000_arg_partial_bytes): Likewise.

11351

+ (rs6000_psave_function_arg): Handle BLKmode arguments.

11352

+

11353

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

11354

+ Michael Gschwind <mkg@us.ibm.com>

11355

+

11356

+ * config/rs6000/rs6000.h (AGGR_ARG_NUM_REG): Define.

11357

+ * config/rs6000/rs6000.c (rs6000_aggregate_candidate): New function.

11358

+ (rs6000_discover_homogeneous_aggregate): Likewise.

11359

+ (rs6000_function_arg_boundary): Handle homogeneous aggregates.

11360

+ (rs6000_function_arg_advance_1): Likewise.

11361

+ (rs6000_function_arg): Likewise.

11362

+ (rs6000_arg_partial_bytes): Likewise.

11363

+ (rs6000_psave_function_arg): Handle BLKmode arguments.

11364

+

11365

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

11366

+

11367

+ * config/rs6000/rs6000.c (machine_function): New member

11368

+ r2_setup_needed.

11369

+ (rs6000_emit_prologue): Set r2_setup_needed if necessary.

11370

+ (rs6000_output_mi_thunk): Set r2_setup_needed.

11371

+ (rs6000_output_function_prologue): Output global entry point

11372

+ prologue and local entry point marker if needed for ABI_ELFv2.

11373

+ Output -mprofile-kernel code here.

11374

+ (output_function_profiler): Do not output -mprofile-kernel

11375

+ code here; moved to rs6000_output_function_prologue.

11376

+ (rs6000_file_start): Output ".abiversion 2" for ABI_ELFv2.

11377

+

11378

+ (rs6000_emit_move): Do not handle dot symbols for ABI_ELFv2.

11379

+ (rs6000_output_function_entry): Likewise.

11380

+ (rs6000_assemble_integer): Likewise.

11381

+ (rs6000_elf_encode_section_info): Likewise.

11382

+ (rs6000_elf_declare_function_name): Do not create dot symbols

11383

+ or .opd section for ABI_ELFv2.

11384

+

11385

+ (rs6000_trampoline_size): Update for ABI_ELFv2 trampolines.

11386

+ (rs6000_trampoline_init): Likewise.

11387

+ (rs6000_elf_file_end): Call file_end_indicate_exec_stack

11388

+ for ABI_ELFv2.

11389

+

11390

+ (rs6000_call_aix): Handle ELFv2 indirect calls. Do not check

11391

+ for function descriptors in ABI_ELFv2.

11392

+

11393

+ * config/rs6000/rs6000.md ("*call_indirect_aix<mode>"): Support

11394

+ on ABI_AIX only, not ABI_ELFv2.

11395

+ ("*call_value_indirect_aix<mode>"): Likewise.

11396

+ ("*call_indirect_elfv2<mode>"): New pattern.

11397

+ ("*call_value_indirect_elfv2<mode>"): Likewise.

11398

+

11399

+ * config/rs6000/predicates.md ("symbol_ref_operand"): Do not

11400

+ check for function descriptors in ABI_ELFv2.

11401

+ ("current_file_function_operand"): Likewise.

11402

+

11403

+ * config/rs6000/ppc-asm.h [__powerpc64__ && _CALL_ELF == 2]:

11404

+ (toc): Undefine.

11405

+ (FUNC_NAME): Define ELFv2 variant.

11406

+ (JUMP_TARGET): Likewise.

11407

+ (FUNC_START): Likewise.

11408

+ (HIDDEN_FUNC): Likewise.

11409

+ (FUNC_END): Likeiwse.

11410

+

11411

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

11412

+

11413

+ * config.gcc [powerpc*-*-* | rs6000-*-*]: Support --with-abi=elfv1

11414

+ and --with-abi=elfv2.

11415

+ * config/rs6000/option-defaults.h (OPTION_DEFAULT_SPECS): Add "abi".

11416

+ * config/rs6000/rs6000.opt (mabi=elfv1): New option.

11417

+ (mabi=elfv2): Likewise.

11418

+ * config/rs6000/rs6000-opts.h (enum rs6000_abi): Add ABI_ELFv2.

11419

+ * config/rs6000/linux64.h (DEFAULT_ABI): Do not hard-code to AIX_ABI

11420

+ if !RS6000_BI_ARCH.

11421

+ (ELFv2_ABI_CHECK): New macro.

11422

+ (SUBSUBTARGET_OVERRIDE_OPTIONS): Use it to decide whether to set

11423

+ rs6000_current_abi to ABI_AIX or ABI_ELFv2.

11424

+ (GLIBC_DYNAMIC_LINKER64): Support ELFv2 ld.so version.

11425

+ * config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): Predefine

11426

+ _CALL_ELF and __STRUCT_PARM_ALIGN__ if appropriate.

11427

+

11428

+ * config/rs6000/rs6000.c (rs6000_debug_reg_global): Handle ABI_ELFv2.

11429

+ (debug_stack_info): Likewise.

11430

+ (rs6000_file_start): Treat ABI_ELFv2 the same as ABI_AIX.

11431

+ (rs6000_legitimize_tls_address): Likewise.

11432

+ (rs6000_conditional_register_usage): Likewise.

11433

+ (rs6000_emit_move): Likewise.

11434

+ (init_cumulative_args): Likewise.

11435

+ (rs6000_function_arg_advance_1): Likewise.

11436

+ (rs6000_function_arg): Likewise.

11437

+ (rs6000_arg_partial_bytes): Likewise.

11438

+ (rs6000_output_function_entry): Likewise.

11439

+ (rs6000_assemble_integer): Likewise.

11440

+ (rs6000_savres_strategy): Likewise.

11441

+ (rs6000_stack_info): Likewise.

11442

+ (rs6000_function_ok_for_sibcall): Likewise.

11443

+ (rs6000_emit_load_toc_table): Likewise.

11444

+ (rs6000_savres_routine_name): Likewise.

11445

+ (ptr_regno_for_savres): Likewise.

11446

+ (rs6000_emit_prologue): Likewise.

11447

+ (rs6000_emit_epilogue): Likewise.

11448

+ (rs6000_output_function_epilogue): Likewise.

11449

+ (output_profile_hook): Likewise.

11450

+ (output_function_profiler): Likewise.

11451

+ (rs6000_trampoline_size): Likewise.

11452

+ (rs6000_trampoline_init): Likewise.

11453

+ (rs6000_elf_output_toc_section_asm_op): Likewise.

11454

+ (rs6000_elf_encode_section_info): Likewise.

11455

+ (rs6000_elf_reloc_rw_mask): Likewise.

11456

+ (rs6000_elf_declare_function_name): Likewise.

11457

+ (rs6000_function_arg_boundary): Treat ABI_ELFv2 the same as ABI_AIX,

11458

+ except that rs6000_compat_align_parm is always assumed false.

11459

+ (rs6000_gimplify_va_arg): Likewise.

11460

+ (rs6000_call_aix): Update comment.

11461

+ (rs6000_sibcall_aix): Likewise.

11462

+ * config/rs6000/rs6000.md ("tls_gd_aix<TLSmode:tls_abi_suffix>"):

11463

+ Treat ABI_ELFv2 the same as ABI_AIX.

11464

+ ("*tls_gd_call_aix<TLSmode:tls_abi_suffix>"): Likewise.

11465

+ ("tls_ld_aix<TLSmode:tls_abi_suffix>"): Likewise.

11466

+ ("*tls_ld_call_aix<TLSmode:tls_abi_suffix>"): Likewise.

11467

+ ("load_toc_aix_si"): Likewise.

11468

+ ("load_toc_aix_di"): Likewise.

11469

+ ("call"): Likewise.

11470

+ ("call_value"): Likewise.

11471

+ ("*call_local_aix<mode>"): Likewise.

11472

+ ("*call_value_local_aix<mode>"): Likewise.

11473

+ ("*call_nonlocal_aix<mode>"): Likewise.

11474

+ ("*call_value_nonlocal_aix<mode>"): Likewise.

11475

+ ("*call_indirect_aix<mode>"): Likewise.

11476

+ ("*call_value_indirect_aix<mode>"): Likewise.

11477

+ ("sibcall"): Likewise.

11478

+ ("sibcall_value"): Likewise.

11479

+ ("*sibcall_aix<mode>"): Likewise.

11480

+ ("*sibcall_value_aix<mode>"): Likewise.

11481

+ * config/rs6000/predicates.md ("symbol_ref_operand"): Likewise.

11482

+ ("current_file_function_operand"): Likewise.

11483

+

11484

+ Backport from mainline r204807:

11485

+

11486

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

11487

+

11488

+ * config/rs6000/rs6000.c (rs6000_arg_partial_bytes): Simplify logic

11489

+ by making use of the fact that for vector / floating point arguments

11490

+ passed both in VRs/FPRs and in the fixed parameter area, the partial

11491

+ bytes mechanism is in fact not used.

11492

+

11493

+ Backport from mainline r204806:

11494

+

11495

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

11496

+

11497

+ * config/rs6000/rs6000.c (rs6000_psave_function_arg): New function.

11498

+ (rs6000_finish_function_arg): Likewise.

11499

+ (rs6000_function_arg): Use rs6000_psave_function_arg and

11500

+ rs6000_finish_function_arg to handle both vector and floating

11501

+ point arguments that are also passed in GPRs / the stack.

11502

+

11503

+ Backport from mainline r204805:

11504

+

11505

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

11506

+

11507

+ * config/rs6000/rs6000.c (USE_FP_FOR_ARG_P): Remove TYPE argument.

11508

+ (USE_ALTIVEC_FOR_ARG_P): Likewise.

11509

+ (rs6000_darwin64_record_arg_advance_recurse): Update uses.

11510

+ (rs6000_function_arg_advance_1):Likewise.

11511

+ (rs6000_darwin64_record_arg_recurse): Likewise.

11512

+ (rs6000_function_arg): Likewise.

11513

+ (rs6000_arg_partial_bytes): Likewise.

11514

+

11515

+ Backport from mainline r204804:

11516

+

11517

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

11518

+

11519

+ * config/rs6000/rs6000.c (rs6000_option_override_internal): Replace

11520

+ "DEFAULT_ABI != ABI_AIX" test by testing for ABI_V4 or ABI_DARWIN.

11521

+ (rs6000_savres_strategy): Likewise.

11522

+ (rs6000_return_addr): Likewise.

11523

+ (rs6000_emit_load_toc_table): Replace "DEFAULT_ABI != ABI_AIX" by

11524

+ testing for ABI_V4 (since ABI_DARWIN is impossible here).

11525

+ (rs6000_emit_prologue): Likewise.

11526

+ (legitimate_lo_sum_address_p): Simplify DEFAULT_ABI test.

11527

+ (rs6000_elf_declare_function_name): Remove duplicated test.

11528

+ * config/rs6000/rs6000.md ("load_toc_v4_PIC_1"): Explicitly test

11529

+ for ABI_V4 (instead of "DEFAULT_ABI != ABI_AIX" test).

11530

+ ("load_toc_v4_PIC_1_normal"): Likewise.

11531

+ ("load_toc_v4_PIC_1_476"): Likewise.

11532

+ ("load_toc_v4_PIC_1b"): Likewise.

11533

+ ("load_toc_v4_PIC_1b_normal"): Likewise.

11534

+ ("load_toc_v4_PIC_1b_476"): Likewise.

11535

+ ("load_toc_v4_PIC_2"): Likewise.

11536

+ ("load_toc_v4_PIC_3b"): Likewise.

11537

+ ("load_toc_v4_PIC_3c"): Likewise.

11538

+ * config/rs6000/rs6000.h (RS6000_REG_SAVE): Simplify DEFAULT_ABI test.

11539

+ (RS6000_SAVE_AREA): Likewise.

11540

+ (FP_ARG_MAX_REG): Likewise.

11541

+ (RETURN_ADDRESS_OFFSET): Likewise.

11542

+ * config/rs6000/sysv.h (TARGET_TOC): Test for ABI_V4 instead

11543

+ of ABI_AIX.

11544

+ (SUBTARGET_OVERRIDE_OPTIONS): Likewise.

11545

+ (MINIMAL_TOC_SECTION_ASM_OP): Likewise.

11546

+

11547

+ Backport from mainline r204803:

11548

+

11549

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

11550

+

11551

+ * config/rs6000/rs6000.c (rs6000_call_indirect_aix): Rename to ...

11552

+ (rs6000_call_aix): ... this. Handle both direct and indirect calls.

11553

+ Create call insn directly instead of via various gen_... routines.

11554

+ Mention special registers used by the call in CALL_INSN_FUNCTION_USAGE.

11555

+ (rs6000_sibcall_aix): New function.

11556

+ * config/rs6000/rs6000.md (TOC_SAVE_OFFSET_32BIT): Remove.

11557

+ (TOC_SAVE_OFFSET_64BIT): Likewise.

11558

+ (AIX_FUNC_DESC_TOC_32BIT): Likewise.

11559

+ (AIX_FUNC_DESC_TOC_64BIT): Likewise.

11560

+ (AIX_FUNC_DESC_SC_32BIT): Likewise.

11561

+ (AIX_FUNC_DESC_SC_64BIT): Likewise.

11562

+ ("call" expander): Call rs6000_call_aix.

11563

+ ("call_value" expander): Likewise.

11564

+ ("call_indirect_aix<ptrsize>"): Replace this pattern ...

11565

+ ("call_indirect_aix<ptrsize>_nor11"): ... and this pattern ...

11566

+ ("*call_indirect_aix<mode>"): ... by this insn pattern.

11567

+ ("call_value_indirect_aix<ptrsize>"): Replace this pattern ...

11568

+ ("call_value_indirect_aix<ptrsize>_nor11"): ... and this pattern ...

11569

+ ("*call_value_indirect_aix<mode>"): ... by this insn pattern.

11570

+ ("*call_nonlocal_aix32", "*call_nonlocal_aix64"): Replace by ...

11571

+ ("*call_nonlocal_aix<mode>"): ... this pattern.

11572

+ ("*call_value_nonlocal_aix32", "*call_value_nonlocal_aix64"): Replace

11573

+ ("*call_value_nonlocal_aix<mode>"): ... by this pattern.

11574

+ ("*call_local_aix<mode>"): New insn pattern.

11575

+ ("*call_value_local_aix<mode>"): Likewise.

11576

+ ("sibcall" expander): Call rs6000_sibcall_aix.

11577

+ ("sibcall_value" expander): Likewise. Move earlier in file.

11578

+ ("*sibcall_nonlocal_aix<mode>"): Replace by ...

11579

+ ("*sibcall_aix<mode>"): ... this pattern.

11580

+ ("*sibcall_value_nonlocal_aix<mode>"): Replace by ...

11581

+ ("*sibcall_value_aix<mode>"): ... this pattern.

11582

+ * config/rs6000/rs6000-protos.h (rs6000_call_indirect_aix): Remove.

11583

+ (rs6000_call_aix): Add prototype.

11584

+ (rs6000_sibcall_aix): Likewise.

11585

+

11586

+ Backport from mainline r204799:

11587

+

11588

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

11589

+

11590

+ * config/rs6000/rs6000.c (rs6000_emit_prologue): Do not place a

11591

+ RTX_FRAME_RELATED_P marker on the UNSPEC_MOVESI_FROM_CR insn.

11592

+ Instead, add USEs of all modified call-saved CR fields to the

11593

+ insn storing the result to the stack slot, and provide an

11594

+ appropriate REG_FRAME_RELATED_EXPR for that insn.

11595

+ * config/rs6000/rs6000.md ("*crsave"): New insn pattern.

11596

+ * config/rs6000/predicates.md ("crsave_operation"): New predicate.

11597

+

11598

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11599

+

11600

+ ELFv2 ABI Call Support

11601

+ Backport from mainline r204798:

11602

+

11603

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

11604

+ Alan Modra <amodra@gmail.com>

11605

+

11606

+ * function.c (assign_parms): Use all.reg_parm_stack_space instead

11607

+ of re-evaluating REG_PARM_STACK_SPACE target macro.

11608

+ (locate_and_pad_parm): New parameter REG_PARM_STACK_SPACE. Use it

11609

+ instead of evaluating target macro REG_PARM_STACK_SPACE every time.

11610

+ (assign_parm_find_entry_rtl): Update call.

11611

+ * calls.c (initialize_argument_information): Update call.

11612

+ (emit_library_call_value_1): Likewise.

11613

+ * expr.h (locate_and_pad_parm): Update prototype.

11614

+

11615

+ Backport from mainline r204797:

11616

+

11617

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

11618

+

11619

+ * calls.c (store_unaligned_arguments_into_pseudos): Skip PARALLEL

11620

+ arguments.

11621

+

11622

+ Backport from mainline r197003:

11623

+

11624

+ 2013-03-23 Eric Botcazou <ebotcazou@adacore.com>

11625

+

11626

+ * calls.c (expand_call): Add missing guard to code handling return

11627

+ of non-BLKmode structures in MSB.

11628

+ * function.c (expand_function_end): Likewise.

11629

+

11630

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11631

+

11632

+ Backport from mainline r201750.

11633

+ Note: Default setting of -mcompat-align-parm inverted!

11634

+

11635

+ 2013-08-14 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11636

+

11637

+ PR target/57949

11638

+ * doc/invoke.texi: Add documentation of mcompat-align-parm

11639

+ option.

11640

+ * config/rs6000/rs6000.opt: Add mcompat-align-parm option.

11641

+ * config/rs6000/rs6000.c (rs6000_function_arg_boundary): For AIX

11642

+ and Linux, correct BLKmode alignment when 128-bit alignment is

11643

+ required and compatibility flag is not set.

11644

+ (rs6000_gimplify_va_arg): For AIX and Linux, honor specified

11645

+ alignment for zero-size arguments when compatibility flag is not

11646

+ set.

11647

+

11648

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11649

+

11650

+ Little Endian Vector Support

11651

+ Backport from mainline r205333

11652

+ 2013-11-24 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11653

+

11654

+ * config/rs6000/rs6000.c (rs6000_expand_vec_perm_const_1): Correct

11655

+ for little endian.

11656

+

11657

+ Backport from mainline r205241

11658

+ 2013-11-21 Bill Schmidt <wschmidt@vnet.ibm.com>

11659

+

11660

+ * config/rs6000/vector.md (vec_pack_trunc_v2df): Revert previous

11661

+ little endian change.

11662

+ (vec_pack_sfix_trunc_v2df): Likewise.

11663

+ (vec_pack_ufix_trunc_v2df): Likewise.

11664

+ * config/rs6000/rs6000.c (rs6000_expand_interleave): Correct

11665

+ double checking of endianness.

11666

+

11667

+ Backport from mainline r205146

11668

+ 2013-11-20 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11669

+

11670

+ * config/rs6000/vsx.md (vsx_set_<mode>): Adjust for little endian.

11671

+ (vsx_extract_<mode>): Likewise.

11672

+ (*vsx_extract_<mode>_one_le): New LE variant on

11673

+ *vsx_extract_<mode>_zero.

11674

+ (vsx_extract_v4sf): Adjust for little endian.

11675

+

11676

+ Backport from mainline r205080

11677

+ 2013-11-19 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11678

+

11679

+ * config/rs6000/rs6000.c (altivec_expand_vec_perm_const): Adjust

11680

+ V16QI vector splat case for little endian.

11681

+

11682

+ Backport from mainline r205045:

11683

+

11684

+ 2013-11-19 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

11685

+

11686

+ * config/rs6000/vector.md ("mov<mode>"): Do not call

11687

+ rs6000_emit_le_vsx_move to move into or out of GPRs.

11688

+ * config/rs6000/rs6000.c (rs6000_emit_le_vsx_move): Assert

11689

+ source and destination are not GPR hard regs.

11690

+

11691

+ Backport from mainline r204920

11692

+ 2011-11-17 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11693

+

11694

+ * config/rs6000/rs6000.c (rs6000_frame_related): Add split_reg

11695

+ parameter and use it in REG_FRAME_RELATED_EXPR note.

11696

+ (emit_frame_save): Call rs6000_frame_related with extra NULL_RTX

11697

+ parameter.

11698

+ (rs6000_emit_prologue): Likewise, but for little endian VSX

11699

+ stores, pass the source register of the store instead.

11700

+

11701

+ Backport from mainline r204862

11702

+ 2013-11-15 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11703

+

11704

+ * config/rs6000/altivec.md (UNSPEC_VPERM_X, UNSPEC_VPERM_UNS_X):

11705

+ Remove.

11706

+ (altivec_vperm_<mode>): Revert earlier little endian change.

11707

+ (*altivec_vperm_<mode>_internal): Remove.

11708

+ (altivec_vperm_<mode>_uns): Revert earlier little endian change.

11709

+ (*altivec_vperm_<mode>_uns_internal): Remove.

11710

+ * config/rs6000/vector.md (vec_realign_load_<mode>): Revise

11711

+ commentary.

11712

+

11713

+ Backport from mainline r204441

11714

+ 2013-11-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11715

+

11716

+ * config/rs6000/rs6000.c (rs6000_option_override_internal):

11717

+ Remove restriction against use of VSX instructions when generating

11718

+ code for little endian mode.

11719

+

11720

+ Backport from mainline r204440

11721

+ 2013-11-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11722

+

11723

+ * config/rs6000/altivec.md (mulv4si3): Ensure we generate vmulouh

11724

+ for both big and little endian.

11725

+ (mulv8hi3): Swap input operands for merge high and merge low

11726

+ instructions for little endian.

11727

+

11728

+ Backport from mainline r204439

11729

+ 2013-11-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11730

+

11731

+ * config/rs6000/altivec.md (vec_widen_umult_even_v16qi): Change

11732

+ define_insn to define_expand that uses even patterns for big

11733

+ endian and odd patterns for little endian.

11734

+ (vec_widen_smult_even_v16qi): Likewise.

11735

+ (vec_widen_umult_even_v8hi): Likewise.

11736

+ (vec_widen_smult_even_v8hi): Likewise.

11737

+ (vec_widen_umult_odd_v16qi): Likewise.

11738

+ (vec_widen_smult_odd_v16qi): Likewise.

11739

+ (vec_widen_umult_odd_v8hi): Likewise.

11740

+ (vec_widen_smult_odd_v8hi): Likewise.

11741

+ (altivec_vmuleub): New define_insn.

11742

+ (altivec_vmuloub): Likewise.

11743

+ (altivec_vmulesb): Likewise.

11744

+ (altivec_vmulosb): Likewise.

11745

+ (altivec_vmuleuh): Likewise.

11746

+ (altivec_vmulouh): Likewise.

11747

+ (altivec_vmulesh): Likewise.

11748

+ (altivec_vmulosh): Likewise.

11749

+

11750

+ Backport from mainline r204395

11751

+ 2013-11-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11752

+

11753

+ * config/rs6000/vector.md (vec_pack_sfix_trunc_v2df): Adjust for

11754

+ little endian.

11755

+ (vec_pack_ufix_trunc_v2df): Likewise.

11756

+

11757

+ Backport from mainline r204363

11758

+ 2013-11-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11759

+

11760

+ * config/rs6000/altivec.md (vec_widen_umult_hi_v16qi): Swap

11761

+ arguments to merge instruction for little endian.

11762

+ (vec_widen_umult_lo_v16qi): Likewise.

11763

+ (vec_widen_smult_hi_v16qi): Likewise.

11764

+ (vec_widen_smult_lo_v16qi): Likewise.

11765

+ (vec_widen_umult_hi_v8hi): Likewise.

11766

+ (vec_widen_umult_lo_v8hi): Likewise.

11767

+ (vec_widen_smult_hi_v8hi): Likewise.

11768

+ (vec_widen_smult_lo_v8hi): Likewise.

11769

+

11770

+ Backport from mainline r204350

11771

+ 2013-11-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11772

+

11773

+ * config/rs6000/vsx.md (*vsx_le_perm_store_<mode> for VSX_D):

11774

+ Replace the define_insn_and_split with a define_insn and two

11775

+ define_splits, with the split after reload re-permuting the source

11776

+ register to its original value.

11777

+ (*vsx_le_perm_store_<mode> for VSX_W): Likewise.

11778

+ (*vsx_le_perm_store_v8hi): Likewise.

11779

+ (*vsx_le_perm_store_v16qi): Likewise.

11780

+

11781

+ Backport from mainline r204321

11782

+ 2013-11-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11783

+

11784

+ * config/rs6000/vector.md (vec_pack_trunc_v2df): Adjust for

11785

+ little endian.

11786

+

11787

+ Backport from mainline r204321

11788

+ 2013-11-02 Bill Schmidt <wschmidt@vnet.linux.ibm.com>

11789

+

11790

+ * config/rs6000/rs6000.c (rs6000_expand_vector_set): Adjust for

11791

+ little endian.

11792

+

11793

+ Backport from mainline r203980

11794

+ 2013-10-23 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11795

+

11796

+ * config/rs6000/altivec.md (mulv8hi3): Adjust for little endian.

11797

+

11798

+ Backport from mainline r203930

11799

+ 2013-10-22 Bill Schmidt <wschmidt@vnet.ibm.com>

11800

+

11801

+ * config/rs6000/rs6000.c (altivec_expand_vec_perm_const): Reverse

11802

+ meaning of merge-high and merge-low masks for little endian; avoid

11803

+ use of vector-pack masks for little endian for mismatched modes.

11804

+

11805

+ Backport from mainline r203877

11806

+ 2013-10-20 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11807

+

11808

+ * config/rs6000/altivec.md (vec_unpacku_hi_v16qi): Adjust for

11809

+ little endian.

11810

+ (vec_unpacku_hi_v8hi): Likewise.

11811

+ (vec_unpacku_lo_v16qi): Likewise.

11812

+ (vec_unpacku_lo_v8hi): Likewise.

11813

+

11814

+ Backport from mainline r203863

11815

+ 2013-10-19 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11816

+

11817

+ * config/rs6000/rs6000.c (vspltis_constant): Make sure we check

11818

+ all elements for both endian flavors.

11819

+

11820

+ Backport from mainline r203714

11821

+ 2013-10-16 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11822

+

11823

+ * gcc/config/rs6000/vector.md (vec_unpacks_hi_v4sf): Correct for

11824

+ endianness.

11825

+ (vec_unpacks_lo_v4sf): Likewise.

11826

+ (vec_unpacks_float_hi_v4si): Likewise.

11827

+ (vec_unpacks_float_lo_v4si): Likewise.

11828

+ (vec_unpacku_float_hi_v4si): Likewise.

11829

+ (vec_unpacku_float_lo_v4si): Likewise.

11830

+

11831

+ Backport from mainline r203713

11832

+ 2013-10-16 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11833

+

11834

+ * config/rs6000/vsx.md (vsx_concat_<mode>): Adjust output for LE.

11835

+ (vsx_concat_v2sf): Likewise.

11836

+

11837

+ Backport from mainline r203458

11838

+ 2013-10-11 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11839

+

11840

+ * config/rs6000/vsx.md (*vsx_le_perm_load_v2di): Generalize to

11841

+ handle vector float as well.

11842

+ (*vsx_le_perm_load_v4si): Likewise.

11843

+ (*vsx_le_perm_store_v2di): Likewise.

11844

+ (*vsx_le_perm_store_v4si): Likewise.

11845

+

11846

+ Backport from mainline r203457

11847

+ 2013-10-11 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11848

+

11849

+ * config/rs6000/vector.md (vec_realign_load<mode>): Generate vperm

11850

+ directly to circumvent subtract from splat{31} workaround.

11851

+ * config/rs6000/rs6000-protos.h (altivec_expand_vec_perm_le): New

11852

+ prototype.

11853

+ * config/rs6000/rs6000.c (altivec_expand_vec_perm_le): New.

11854

+ * config/rs6000/altivec.md (define_c_enum "unspec"): Add

11855

+ UNSPEC_VPERM_X and UNSPEC_VPERM_UNS_X.

11856

+ (altivec_vperm_<mode>): Convert to define_insn_and_split to

11857

+ separate big and little endian logic.

11858

+ (*altivec_vperm_<mode>_internal): New define_insn.

11859

+ (altivec_vperm_<mode>_uns): Convert to define_insn_and_split to

11860

+ separate big and little endian logic.

11861

+ (*altivec_vperm_<mode>_uns_internal): New define_insn.

11862

+ (vec_permv16qi): Add little endian logic.

11863

+

11864

+ Backport from mainline r203247

11865

+ 2013-10-07 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11866

+

11867

+ * config/rs6000/rs6000.c (altivec_expand_vec_perm_const_le): New.

11868

+ (altivec_expand_vec_perm_const): Call it.

11869

+

11870

+ Backport from mainline r203246

11871

+ 2013-10-07 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11872

+

11873

+ * config/rs6000/vector.md (mov<mode>): Emit permuted move

11874

+ sequences for LE VSX loads and stores at expand time.

11875

+ * config/rs6000/rs6000-protos.h (rs6000_emit_le_vsx_move): New

11876

+ prototype.

11877

+ * config/rs6000/rs6000.c (rs6000_const_vec): New.

11878

+ (rs6000_gen_le_vsx_permute): New.

11879

+ (rs6000_gen_le_vsx_load): New.

11880

+ (rs6000_gen_le_vsx_store): New.

11881

+ (rs6000_gen_le_vsx_move): New.

11882

+ * config/rs6000/vsx.md (*vsx_le_perm_load_v2di): New.

11883

+ (*vsx_le_perm_load_v4si): New.

11884

+ (*vsx_le_perm_load_v8hi): New.

11885

+ (*vsx_le_perm_load_v16qi): New.

11886

+ (*vsx_le_perm_store_v2di): New.

11887

+ (*vsx_le_perm_store_v4si): New.

11888

+ (*vsx_le_perm_store_v8hi): New.

11889

+ (*vsx_le_perm_store_v16qi): New.

11890

+ (*vsx_xxpermdi2_le_<mode>): New.

11891

+ (*vsx_xxpermdi4_le_<mode>): New.

11892

+ (*vsx_xxpermdi8_le_V8HI): New.

11893

+ (*vsx_xxpermdi16_le_V16QI): New.

11894

+ (*vsx_lxvd2x2_le_<mode>): New.

11895

+ (*vsx_lxvd2x4_le_<mode>): New.

11896

+ (*vsx_lxvd2x8_le_V8HI): New.

11897

+ (*vsx_lxvd2x16_le_V16QI): New.

11898

+ (*vsx_stxvd2x2_le_<mode>): New.

11899

+ (*vsx_stxvd2x4_le_<mode>): New.

11900

+ (*vsx_stxvd2x8_le_V8HI): New.

11901

+ (*vsx_stxvd2x16_le_V16QI): New.

11902

+

11903

+ Backport from mainline r201235

11904

+ 2013-07-24 Bill Schmidt <wschmidt@linux.ibm.com>

11905

+ Anton Blanchard <anton@au1.ibm.com>

11906

+

11907

+ * config/rs6000/altivec.md (altivec_vpkpx): Handle little endian.

11908

+ (altivec_vpks<VI_char>ss): Likewise.

11909

+ (altivec_vpks<VI_char>us): Likewise.

11910

+ (altivec_vpku<VI_char>us): Likewise.

11911

+ (altivec_vpku<VI_char>um): Likewise.

11912

+

11913

+ Backport from mainline r201208

11914

+ 2013-07-24 Bill Schmidt <wschmidt@vnet.linux.ibm.com>

11915

+ Anton Blanchard <anton@au1.ibm.com>

11916

+

11917

+ * config/rs6000/vector.md (vec_realign_load_<mode>): Reorder input

11918

+ operands to vperm for little endian.

11919

+ * config/rs6000/rs6000.c (rs6000_expand_builtin): Use lvsr instead

11920

+ of lvsl to create the control mask for a vperm for little endian.

11921

+

11922

+ Backport from mainline r201195

11923

+ 2013-07-23 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11924

+ Anton Blanchard <anton@au1.ibm.com>

11925

+

11926

+ * config/rs6000/rs6000.c (altivec_expand_vec_perm_const): Reverse

11927

+ two operands for little-endian.

11928

+

11929

+ Backport from mainline r201193

11930

+ 2013-07-23 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11931

+ Anton Blanchard <anton@au1.ibm.com>

11932

+

11933

+ * config/rs6000/rs6000.c (altivec_expand_vec_perm_const): Correct

11934

+ selection of field for vector splat in little endian mode.

11935

+

11936

+ Backport from mainline r201149

11937

+ 2013-07-22 Bill Schmidt <wschmidt@vnet.linux.ibm.com>

11938

+ Anton Blanchard <anton@au1.ibm.com>

11939

+

11940

+ * config/rs6000/rs6000.c (rs6000_expand_vector_init): Fix

11941

+ endianness when selecting field to splat.

11942

+

11943

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11944

+

11945

+ Backport from mainline r205123:

11946

+

11947

+ 2013-11-20 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

11948

+

11949

+ * config/rs6000/rs6000.c (rs6000_cannot_change_mode_class): Do not

11950

+ allow subregs of TDmode in FPRs of smaller size in little-endian.

11951

+ (rs6000_split_multireg_move): When splitting an access to TDmode

11952

+ in FPRs, do not use simplify_gen_subreg.

11953

+

11954

+ Backport from mainline r204927:

11955

+

11956

+ 2013-11-17 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

11957

+

11958

+ * config/rs6000/rs6000.c (rs6000_emit_move): Use low word of

11959

+ sdmode_stack_slot also in little-endian mode.

11960

+

11961

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

11962

+

11963

+ Power8 HTM Support

11964

+ Backport from mainline

11965

+ 2013-12-03 Peter Bergner <bergner@vnet.ibm.com>

11966

+

11967

+ * config/rs6000/htmintrin.h (_TEXASR_INSTRUCTION_FETCH_CONFLICT): Fix

11968

+ typo in macro name.

11969

+ (_TEXASRU_INSTRUCTION_FETCH_CONFLICT): Likewise.

11970

+

11971

+ Backport from mainline r205233.

11972

+ 2013-11-21 Peter Bergner <bergner@vnet.ibm.com>

11973

+

11974

+ * doc/extend.texi: Document htm builtins.

11975

+

11976

+ Backport from mainline

11977

+ 2013-07-17 Iain Sandoe <iain@codesourcery.com>

11978

+

11979

+ * config/rs6000/darwin.h (REGISTER_NAMES): Add HTM registers.

11980

+

11981

+ Backport from mainline

11982

+ 2013-07-16 Peter Bergner <bergner@vnet.ibm.com>

11983

+

11984

+ * config/rs6000/rs6000.c (rs6000_option_override_internal): Do not

11985

+ enable extra ISA flags with TARGET_HTM.

11986

+

11987

+ 2013-07-16 Jakub Jelinek <jakub@redhat.com>

11988

+ Peter Bergner <bergner@vnet.ibm.com>

11989

+

11990

+ * config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTERS): Mention HTM

11991

+ registers in the comment.

11992

+ (DWARF_FRAME_REGISTERS): Subtract also the 3 HTM registers.

11993

+ (DWARF_REG_TO_UNWIND_COLUMN): Use DWARF_FRAME_REGISTERS

11994

+ rather than FIRST_PSEUDO_REGISTERS.

11995

+

11996

+ * config.gcc (powerpc*-*-*): Install htmintrin.h and htmxlintrin.h.

11997

+ * config/rs6000/t-rs6000 (MD_INCLUDES): Add htm.md.

11998

+ * config/rs6000/rs6000.opt: Add -mhtm option.

11999

+ * config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add OPTION_MASK_HTM.

12000

+ (ISA_2_7_MASKS_SERVER): Add OPTION_MASK_HTM.

12001

+ * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Define

12002

+ __HTM__ if the HTM instructions are available.

12003

+ * config/rs6000/predicates.md (u3bit_cint_operand, u10bit_cint_operand)

12004

+ (htm_spr_reg_operand): New define_predicates.

12005

+ * config/rs6000/rs6000.md (define_attr "type"): Add htm.

12006

+ (TFHAR_REGNO, TFIAR_REGNO, TEXASR_REGNO): New define_constants.

12007

+ Include htm.md.

12008

+ * config/rs6000/rs6000-builtin.def (BU_HTM_0, BU_HTM_1, BU_HTM_2)

12009

+ (BU_HTM_3, BU_HTM_SPR0, BU_HTM_SPR1): Add support macros for defining

12010

+ HTM builtin functions.

12011

+ * config/rs6000/rs6000.c (RS6000_BUILTIN_H): New macro.

12012

+ (rs6000_reg_names, alt_reg_names): Add HTM SPR register names.

12013

+ (rs6000_init_hard_regno_mode_ok): Add support for HTM instructions.

12014

+ (rs6000_builtin_mask_calculate): Likewise.

12015

+ (rs6000_option_override_internal): Likewise.

12016

+ (bdesc_htm): Add new HTM builtin support.

12017

+ (htm_spr_num): New function.

12018

+ (htm_spr_regno): Likewise.

12019

+ (rs6000_htm_spr_icode): Likewise.

12020

+ (htm_expand_builtin): Likewise.

12021

+ (htm_init_builtins): Likewise.

12022

+ (rs6000_expand_builtin): Add support for HTM builtin functions.

12023

+ (rs6000_init_builtins): Likewise.

12024

+ (rs6000_invalid_builtin, rs6000_opt_mask): Add support for -mhtm option.

12025

+ * config/rs6000/rs6000.h (ASM_CPU_SPEC): Add support for -mhtm.

12026

+ (TARGET_HTM, MASK_HTM): Define macros.

12027

+ (FIRST_PSEUDO_REGISTER): Adjust for new HTM SPR registers.

12028

+ (FIXED_REGISTERS): Likewise.

12029

+ (CALL_USED_REGISTERS): Likewise.

12030

+ (CALL_REALLY_USED_REGISTERS): Likewise.

12031

+ (REG_ALLOC_ORDER): Likewise.

12032

+ (enum reg_class): Likewise.

12033

+ (REG_CLASS_NAMES): Likewise.

12034

+ (REG_CLASS_CONTENTS): Likewise.

12035

+ (REGISTER_NAMES): Likewise.

12036

+ (ADDITIONAL_REGISTER_NAMES): Likewise.

12037

+ (RS6000_BTC_SPR, RS6000_BTC_VOID, RS6000_BTC_32BIT, RS6000_BTC_64BIT)

12038

+ (RS6000_BTC_MISC_MASK, RS6000_BTM_HTM): New macros.

12039

+ (RS6000_BTM_COMMON): Add RS6000_BTM_HTM.

12040

+ * config/rs6000/htm.md: New file.

12041

+ * config/rs6000/htmintrin.h: New file.

12042

+ * config/rs6000/htmxlintrin.h: New file.

12043

+

12044

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

12045

+

12046

+ Power8 Base Support

12047

+ Apply mainline

12048

+ 2013-11-23 Alan Modra <amodra@gmail.com>

12049

+ * config/rs6000/vsx.md (fusion peepholes): Disable when !TARGET_VSX.

12050

+

12051

+ Backport from mainline

12052

+ 2013-11-12 Michael Meissner <meissner@linux.vnet.ibm.com>

12053

+

12054

+ PR target/59054

12055

+ * config/rs6000/rs6000.md (movdi_internal32): Eliminate

12056

+ constraints that would allow DImode into the traditional Altivec

12057

+ registers, but cause undesirable code generation when loading 0 as

12058

+ a constant.

12059

+ (movdi_internal64): Likewise.

12060

+ (cmp<mode>_fpr): Do not use %x for CR register output.

12061

+ (extendsfdf2_fpr): Fix constraints when -mallow-upper-df and

12062

+ -mallow-upper-sf debug switches are used.

12063

+

12064

+ Backport from mainline

12065

+ 2013-10-17 Michael Meissner <meissner@linux.vnet.ibm.com>

12066

+

12067

+ * config/rs6000/rs6000.c (enum rs6000_reload_reg_type): Add new

12068

+ fields to the reg_addr array that describes the valid addressing

12069

+ mode for any register, general purpose registers, floating point

12070

+ registers, and Altivec registers.

12071

+ (FIRST_RELOAD_REG_CLASS): Likewise.

12072

+ (LAST_RELOAD_REG_CLASS): Likewise.

12073

+ (struct reload_reg_map_type): Likewise.

12074

+ (reload_reg_map_type): Likewise.

12075

+ (RELOAD_REG_VALID): Likewise.

12076

+ (RELOAD_REG_MULTIPLE): Likewise.

12077

+ (RELOAD_REG_INDEXED): Likewise.

12078

+ (RELOAD_REG_OFFSET): Likewise.

12079

+ (RELOAD_REG_PRE_INCDEC): Likewise.

12080

+ (RELOAD_REG_PRE_MODIFY): Likewise.

12081

+ (reg_addr): Likewise.

12082

+ (mode_supports_pre_incdec_p): New helper functions to say whether

12083

+ a given mode supports PRE_INC, PRE_DEC, and PRE_MODIFY.

12084

+ (mode_supports_pre_modify_p): Likewise.

12085

+ (rs6000_debug_vector_unit): Rearrange the -mdebug=reg output to

12086

+ print the valid address mode bits for each mode.

12087

+ (rs6000_debug_print_mode): Likewise.

12088

+ (rs6000_debug_reg_global): Likewise.

12089

+ (rs6000_setup_reg_addr_masks): New function to set up the address

12090

+ mask bits for each type.

12091

+ (rs6000_init_hard_regno_mode_ok): Use memset to clear arrays.

12092

+ Call rs6000_setup_reg_addr_masks to set up the address mask bits.

12093

+ (rs6000_legitimate_address_p): Use mode_supports_pre_incdec_p and

12094

+ mode_supports_pre_modify_p to determine if PRE_INC, PRE_DEC, and

12095

+ PRE_MODIFY are supported.

12096

+ (rs6000_output_move_128bit): Change to use {src,dest}_vmx_p for altivec

12097

+ registers, instead of {src,dest}_av_p.

12098

+ (rs6000_print_options_internal): Tweak the debug output slightly.

12099

+

12100

+ Backport from mainline

12101

+ 2013-10-03 Michael Meissner <meissner@linux.vnet.ibm.com>

12102

+

12103

+ * config/rs6000/rs6000-builtin.def (XSRDPIM): Use floatdf2,

12104

+ ceildf2, btruncdf2, instead of vsx_* name.

12105

+

12106

+ * config/rs6000/vsx.md (vsx_add<mode>3): Change arithmetic

12107

+ iterators to only do V2DF and V4SF here. Move the DF code to

12108

+ rs6000.md where it is combined with SF mode. Replace <VSv> with

12109

+ just 'v' since only vector operations are handled with these insns

12110

+ after moving the DF support to rs6000.md.

12111

+ (vsx_sub<mode>3): Likewise.

12112

+ (vsx_mul<mode>3): Likewise.

12113

+ (vsx_div<mode>3): Likewise.

12114

+ (vsx_fre<mode>2): Likewise.

12115

+ (vsx_neg<mode>2): Likewise.

12116

+ (vsx_abs<mode>2): Likewise.

12117

+ (vsx_nabs<mode>2): Likewise.

12118

+ (vsx_smax<mode>3): Likewise.

12119

+ (vsx_smin<mode>3): Likewise.

12120

+ (vsx_sqrt<mode>2): Likewise.

12121

+ (vsx_rsqrte<mode>2): Likewise.

12122

+ (vsx_fms<mode>4): Likewise.

12123

+ (vsx_nfma<mode>4): Likewise.

12124

+ (vsx_copysign<mode>3): Likewise.

12125

+ (vsx_btrunc<mode>2): Likewise.

12126

+ (vsx_floor<mode>2): Likewise.

12127

+ (vsx_ceil<mode>2): Likewise.

12128

+ (vsx_smaxsf3): Delete scalar ops that were moved to rs6000.md.

12129

+ (vsx_sminsf3): Likewise.

12130

+ (vsx_fmadf4): Likewise.

12131

+ (vsx_fmsdf4): Likewise.

12132

+ (vsx_nfmadf4): Likewise.

12133

+ (vsx_nfmsdf4): Likewise.

12134

+ (vsx_cmpdf_internal1): Likewise.

12135

+

12136

+ * config/rs6000/rs6000.h (TARGET_SF_SPE): Define macros to make it

12137

+ simpler to select whether a target has SPE or traditional floating

12138

+ point support in iterators.

12139

+ (TARGET_DF_SPE): Likewise.

12140

+ (TARGET_SF_FPR): Likewise.

12141

+ (TARGET_DF_FPR): Likewise.

12142

+ (TARGET_SF_INSN): Macros to say whether floating point support

12143

+ exists for a given operation for expanders.

12144

+ (TARGET_DF_INSN): Likewise.

12145

+

12146

+ * config/rs6000/rs6000.c (Ftrad): New mode attributes to allow

12147

+ combining of SF/DF mode operations, using both traditional and VSX

12148

+ registers.

12149

+ (Fvsx): Likewise.

12150

+ (Ff): Likewise.

12151

+ (Fv): Likewise.

12152

+ (Fs): Likewise.

12153

+ (Ffre): Likewise.

12154

+ (FFRE): Likewise.

12155

+ (abs<mode>2): Combine SF/DF modes using traditional floating point

12156

+ instructions. Add support for using the upper DF registers with

12157

+ VSX support, and SF registers with power8-vector support. Update

12158

+ expanders for operations supported by both the SPE and traditional

12159

+ floating point units.

12160

+ (abs<mode>2_fpr): Likewise.

12161

+ (nabs<mode>2): Likewise.

12162

+ (nabs<mode>2_fpr): Likewise.

12163

+ (neg<mode>2): Likewise.

12164

+ (neg<mode>2_fpr): Likewise.

12165

+ (add<mode>3): Likewise.

12166

+ (add<mode>3_fpr): Likewise.

12167

+ (sub<mode>3): Likewise.

12168

+ (sub<mode>3_fpr): Likewise.

12169

+ (mul<mode>3): Likewise.

12170

+ (mul<mode>3_fpr): Likewise.

12171

+ (div<mode>3): Likewise.

12172

+ (div<mode>3_fpr): Likewise.

12173

+ (sqrt<mode>3): Likewise.

12174

+ (sqrt<mode>3_fpr): Likewise.

12175

+ (fre<Fs>): Likewise.

12176

+ (rsqrt<mode>2): Likewise.

12177

+ (cmp<mode>_fpr): Likewise.

12178

+ (smax<mode>3): Likewise.

12179

+ (smin<mode>3): Likewise.

12180

+ (smax<mode>3_vsx): Likewise.

12181

+ (smin<mode>3_vsx): Likewise.

12182

+ (negsf2): Delete SF operations that are merged with DF.

12183

+ (abssf2): Likewise.

12184

+ (addsf3): Likewise.

12185

+ (subsf3): Likewise.

12186

+ (mulsf3): Likewise.

12187

+ (divsf3): Likewise.

12188

+ (fres): Likewise.

12189

+ (fmasf4_fpr): Likewise.

12190

+ (fmssf4_fpr): Likewise.

12191

+ (nfmasf4_fpr): Likewise.

12192

+ (nfmssf4_fpr): Likewise.

12193

+ (sqrtsf2): Likewise.

12194

+ (rsqrtsf_internal1): Likewise.

12195

+ (smaxsf3): Likewise.

12196

+ (sminsf3): Likewise.

12197

+ (cmpsf_internal1): Likewise.

12198

+ (copysign<mode>3_fcpsgn): Add VSX/power8-vector support.

12199

+ (negdf2): Delete DF operations that are merged with SF.

12200

+ (absdf2): Likewise.

12201

+ (nabsdf2): Likewise.

12202

+ (adddf3): Likewise.

12203

+ (subdf3): Likewise.

12204

+ (muldf3): Likewise.

12205

+ (divdf3): Likewise.

12206

+ (fred): Likewise.

12207

+ (rsqrtdf_internal1): Likewise.

12208

+ (fmadf4_fpr): Likewise.

12209

+ (fmsdf4_fpr): Likewise.

12210

+ (nfmadf4_fpr): Likewise.

12211

+ (nfmsdf4_fpr): Likewise.

12212

+ (sqrtdf2): Likewise.

12213

+ (smaxdf3): Likewise.

12214

+ (smindf3): Likewise.

12215

+ (cmpdf_internal1): Likewise.

12216

+ (lrint<mode>di2): Use TARGET_<MODE>_FPR macro.

12217

+ (btrunc<mode>2): Delete separate expander, and combine with the

12218

+ insn and add VSX instruction support. Use TARGET_<MODE>_FPR.

12219

+ (btrunc<mode>2_fpr): Likewise.

12220

+ (ceil<mode>2): Likewise.

12221

+ (ceil<mode>2_fpr): Likewise.

12222

+ (floor<mode>2): Likewise.

12223

+ (floor<mode>2_fpr): Likewise.

12224

+ (fma<mode>4_fpr): Combine SF and DF fused multiply/add support.

12225

+ Add support for using the upper registers with VSX and

12226

+ power8-vector. Move insns to be closer to the define_expands. On

12227

+ VSX systems, prefer the traditional form of FMA over the VSX

12228

+ version, since the traditional form allows the target not to

12229

+ overlap with the inputs.

12230

+ (fms<mode>4_fpr): Likewise.

12231

+ (nfma<mode>4_fpr): Likewise.

12232

+ (nfms<mode>4_fpr): Likewise.

12233

+

12234

+ Backport from mainline

12235

+ 2013-09-27 Michael Meissner <meissner@linux.vnet.ibm.com>

12236

+

12237

+ * config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): Allow

12238

+ DFmode, DImode, and SFmode in the upper VSX registers based on the

12239

+ -mupper-regs-{df,sf} flags. Fix wu constraint to be ALTIVEC_REGS

12240

+ if -mpower8-vector. Combine -mvsx-timode handling with the rest

12241

+ of the VSX register handling.

12242

+

12243

+ * config/rs6000/rs6000.md (f32_lv): Use %x0 for VSX regsters.

12244

+ (f32_sv): Likewise.

12245

+ (zero_extendsidi2_lfiwzx): Add support for loading into the

12246

+ Altivec registers with -mpower8-vector. Use wu/wv constraints to

12247

+ only do VSX memory options on Altivec registers.

12248

+ (extendsidi2_lfiwax): Likewise.

12249

+ (extendsfdf2_fpr): Likewise.

12250

+ (mov<mode>_hardfloat, SF/SD modes): Likewise.

12251

+ (mov<mode>_hardfloat32, DF/DD modes): Likewise.

12252

+ (mov<mode>_hardfloat64, DF/DD modes): Likewise.

12253

+ (movdi_internal64): Likewise.

12254

+

12255

+ Backport from mainline

12256

+ 2013-09-23 Michael Meissner <meissner@linux.vnet.ibm.com>

12257

+

12258

+ * config/rs6000/rs6000.c (rs6000_vector_reload): Delete, combine

12259

+ reload helper function arrays into a single array reg_addr.

12260

+ (reload_fpr_gpr): Likewise.

12261

+ (reload_gpr_vsx): Likewise.

12262

+ (reload_vsx_gpr): Likewise.

12263

+ (struct rs6000_reg_addr): Likewise.

12264

+ (reg_addr): Likewise.

12265

+ (rs6000_debug_reg_global): Change rs6000_vector_reload,

12266

+ reload_fpr_gpr, reload_gpr_vsx, reload_vsx_gpr uses to reg_addr.

12267

+ (rs6000_init_hard_regno_mode_ok): Likewise.

12268

+ (rs6000_secondary_reload_direct_move): Likewise.

12269

+ (rs6000_secondary_reload): Likewise.

12270

+

12271

+ * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Add new

12272

+ constraints: wu, ww, and wy. Repurpose wv constraint added during

12273

+ power8 changes. Put wg constraint in alphabetical order.

12274

+

12275

+ * config/rs6000/rs6000.opt (-mvsx-scalar-float): New debug switch

12276

+ for future work to add ISA 2.07 VSX single precision support.

12277

+ (-mvsx-scalar-double): Change default from -1 to 1, update

12278

+ documentation comment.

12279

+ (-mvsx-scalar-memory): Rename debug switch to -mupper-regs-df.

12280

+ (-mupper-regs-df): New debug switch to control whether DF values

12281

+ can go in the traditional Altivec registers.

12282

+ (-mupper-regs-sf): New debug switch to control whether SF values

12283

+ can go in the traditional Altivec registers.

12284

+

12285

+ * config/rs6000/rs6000.c (rs6000_debug_reg_global): Print wu, ww,

12286

+ and wy constraints.

12287

+ (rs6000_init_hard_regno_mode_ok): Use ssize_t instead of int for

12288

+ loop variables. Rename -mvsx-scalar-memory to -mupper-regs-df.

12289

+ Add new constraints, wu/ww/wy. Repurpose wv constraint.

12290

+ (rs6000_debug_legitimate_address_p): Print if we are running

12291

+ before, during, or after reload.

12292

+ (rs6000_secondary_reload): Add a comment.

12293

+ (rs6000_opt_masks): Add -mupper-regs-df, -mupper-regs-sf.

12294

+

12295

+ * config/rs6000/constraints.md (wa constraint): Sort w<x>

12296

+ constraints. Update documentation string.

12297

+ (wd constraint): Likewise.

12298

+ (wf constraint): Likewise.

12299

+ (wg constraint): Likewise.

12300

+ (wn constraint): Likewise.

12301

+ (ws constraint): Likewise.

12302

+ (wt constraint): Likewise.

12303

+ (wx constraint): Likewise.

12304

+ (wz constraint): Likewise.

12305

+ (wu constraint): New constraint for ISA 2.07 SFmode scalar

12306

+ instructions.

12307

+ (ww constraint): Likewise.

12308

+ (wy constraint): Likewise.

12309

+ (wv constraint): Repurpose ISA 2.07 constraint that did not use in

12310

+ the previous submissions.

12311

+ * doc/md.texi (PowerPC and IBM RS6000): Likewise.

12312

+

12313

+ Backport from mainline

12314

+ 2013-10-17 Michael Meissner <meissner@linux.vnet.ibm.com>

12315

+

12316

+ PR target/58673

12317

+ * config/rs6000/rs6000.c (rs6000_legitimate_address_p): Only

12318

+ restrict TImode addresses to single indirect registers if both

12319

+ -mquad-memory and -mvsx-timode are used.

12320

+ (rs6000_output_move_128bit): Use quad_load_store_p to determine if

12321

+ we should emit load/store quad. Remove using %y for quad memory

12322

+ addresses.

12323

+

12324

+ * config/rs6000/rs6000.md (mov<mode>_ppc64, TI/PTImode): Add

12325

+ constraints to allow load/store quad on machines where TImode is

12326

+ not allowed in VSX registers. Use 'n' instead of 'F' constraint

12327

+ for TImode to load integer constants.

12328

+

12329

+ Backport from mainline

12330

+ 2013-10-02 Michael Meissner <meissner@linux.vnet.ibm.com>

12331

+

12332

+ PR target/58587

12333

+ * config/rs6000/rs6000-cpus.def (ISA_2_6_MASKS_SERVER): Turn off

12334

+ setting -mvsx-timode by default until the underlying problem is

12335

+ fixed.

12336

+ (RS6000_CPU, power7 defaults): Likewise.

12337

+

12338

+ Backport from trunk

12339

+ 2013-08-16 Michael Meissner <meissner@linux.vnet.ibm.com>

12340

+

12341

+ PR target/58160

12342

+ * config/rs6000/predicates.md (fusion_gpr_mem_load): Allow the

12343

+ memory rtx to contain ZERO_EXTEND and SIGN_EXTEND.

12344

+

12345

+ * config/rs6000/rs6000-protos.h (fusion_gpr_load_p): Pass operands

12346

+ array instead of each individual operand as a separate argument.

12347

+ (emit_fusion_gpr_load): Likewise.

12348

+ (expand_fusion_gpr_load): Add new function declaration.

12349

+

12350

+ * config/rs6000/rs6000.c (fusion_gpr_load_p): Change the calling

12351

+ signature to have the operands passed as an array, instead of as

12352

+ separate arguments. Allow ZERO_EXTEND to be in the memory

12353

+ address, and also SIGN_EXTEND if -mpower8-fusion-sign. Do not

12354

+ depend on the register live/dead flags when peepholes are run.

12355

+ (expand_fusion_gpr_load): New function to be called from the

12356

+ peephole2 pass, to change the register that addis sets to be the

12357

+ target register.

12358

+ (emit_fusion_gpr_load): Change the calling signature to have the

12359

+ operands passed as an array, instead of as separate arguments.

12360

+ Allow ZERO_EXTEND to be in the memory address, and also

12361

+ SIGN_EXTEND if -mpower8-fusion-sign.

12362

+

12363

+ * config/rs6000/rs6000.md (UNSPEC_FUSION_GPR): Delete unused

12364

+ unspec enumeration.

12365

+ (power8 fusion peephole/peephole2): Rework the fusion peepholes to

12366

+ adjust the register addis loads up in the peephole2 pass. Do not

12367

+ depend on the register live/dead state when the peephole pass is

12368

+ done.

12369

+

12370

+ Backport from trunk

12371

+ 2013-07-23 Michael Meissner <meissner@linux.vnet.ibm.com>

12372

+

12373

+ * config/rs6000/vector.md (xor<mode>3): Move 128-bit boolean

12374

+ expanders to rs6000.md.

12375

+ (ior<mode>3): Likewise.

12376

+ (and<mode>3): Likewise.

12377

+ (one_cmpl<mode>2): Likewise.

12378

+ (nor<mode>3): Likewise.

12379

+ (andc<mode>3): Likewise.

12380

+ (eqv<mode>3): Likewise.

12381

+ (nand<mode>3): Likewise.

12382

+ (orc<mode>3): Likewise.

12383

+

12384

+ * config/rs6000/rs6000-protos.h (rs6000_split_logical): New

12385

+ declaration.

12386

+

12387

+ * config/rs6000/rs6000.c (rs6000_split_logical_inner): Add support

12388

+ to split multi-word logical operations.

12389

+ (rs6000_split_logical_di): Likewise.

12390

+ (rs6000_split_logical): Likewise.

12391

+

12392

+ * config/rs6000/vsx.md (VSX_L2): Delete, no longer used.

12393

+ (vsx_and<mode>3_32bit): Move 128-bit logical insns to rs6000.md,

12394

+ and allow TImode operations in 32-bit.

12395

+ (vsx_and<mode>3_64bit): Likewise.

12396

+ (vsx_ior<mode>3_32bit): Likewise.

12397

+ (vsx_ior<mode>3_64bit): Likewise.

12398

+ (vsx_xor<mode>3_32bit): Likewise.

12399

+ (vsx_xor<mode>3_64bit): Likewise.

12400

+ (vsx_one_cmpl<mode>2_32bit): Likewise.

12401

+ (vsx_one_cmpl<mode>2_64bit): Likewise.

12402

+ (vsx_nor<mode>3_32bit): Likewise.

12403

+ (vsx_nor<mode>3_64bit): Likewise.

12404

+ (vsx_andc<mode>3_32bit): Likewise.

12405

+ (vsx_andc<mode>3_64bit): Likewise.

12406

+ (vsx_eqv<mode>3_32bit): Likewise.

12407

+ (vsx_eqv<mode>3_64bit): Likewise.

12408

+ (vsx_nand<mode>3_32bit): Likewise.

12409

+ (vsx_nand<mode>3_64bit): Likewise.

12410

+ (vsx_orc<mode>3_32bit): Likewise.

12411

+ (vsx_orc<mode>3_64bit): Likewise.

12412

+

12413

+ * config/rs6000/rs6000.h (VLOGICAL_REGNO_P): Always allow vector

12414

+ logical types in GPRs.

12415

+

12416

+ * config/rs6000/altivec.md (altivec_and<mode>3): Move 128-bit

12417

+ logical insns to rs6000.md, and allow TImode operations in

12418

+ 32-bit.

12419

+ (altivec_ior<mode>3): Likewise.

12420

+ (altivec_xor<mode>3): Likewise.

12421

+ (altivec_one_cmpl<mode>2): Likewise.

12422

+ (altivec_nor<mode>3): Likewise.

12423

+ (altivec_andc<mode>3): Likewise.

12424

+

12425

+ * config/rs6000/rs6000.md (BOOL_128): New mode iterators and mode

12426

+ attributes for moving the 128-bit logical operations into

12427

+ rs6000.md.

12428

+ (BOOL_REGS_OUTPUT): Likewise.

12429

+ (BOOL_REGS_OP1): Likewise.

12430

+ (BOOL_REGS_OP2): Likewise.

12431

+ (BOOL_REGS_UNARY): Likewise.

12432

+ (BOOL_REGS_AND_CR0): Likewise.

12433

+ (one_cmpl<mode>2): Add support for DI logical operations on

12434

+ 32-bit, splitting the operations to 32-bit.

12435

+ (anddi3): Likewise.

12436

+ (iordi3): Likewise.

12437

+ (xordi3): Likewise.

12438

+ (and<mode>3, 128-bit types): Rewrite 2013-06-06 logical operator

12439

+ changes to combine the 32/64-bit code, allow logical operations on

12440

+ TI mode in 32-bit, and to use similar match_operator patterns like

12441

+ scalar mode uses. Combine the Altivec and VSX code for logical

12442

+ operations, and move it here.

12443

+ (ior<mode>3, 128-bit types): Likewise.

12444

+ (xor<mode>3, 128-bit types): Likewise.

12445

+ (one_cmpl<mode>3, 128-bit types): Likewise.

12446

+ (nor<mode>3, 128-bit types): Likewise.

12447

+ (andc<mode>3, 128-bit types): Likewise.

12448

+ (eqv<mode>3, 128-bit types): Likewise.

12449

+ (nand<mode>3, 128-bit types): Likewise.

12450

+ (orc<mode>3, 128-bit types): Likewise.

12451

+ (and<mode>3_internal): Likewise.

12452

+ (bool<mode>3_internal): Likewise.

12453

+ (boolc<mode>3_internal1): Likewise.

12454

+ (boolc<mode>3_internal2): Likewise.

12455

+ (boolcc<mode>3_internal1): Likewise.

12456

+ (boolcc<mode>3_internal2): Likewise.

12457

+ (eqv<mode>3_internal1): Likewise.

12458

+ (eqv<mode>3_internal2): Likewise.

12459

+ (one_cmpl1<mode>3_internal): Likewise.

12460

+

12461

+ Back port from mainline:

12462

+ 2013-06-06 Michael Meissner <meissner@linux.vnet.ibm.com>

12463

+ Pat Haugen <pthaugen@us.ibm.com>

12464

+ Peter Bergner <bergner@vnet.ibm.com>

12465

+

12466

+ * lib/target-supports.exp (check_p8vector_hw_available) Add power8

12467

+ support.

12468

+ (check_effective_target_powerpc_p8vector_ok): Likewise.

12469

+ (is-effective-target): Likewise.

12470

+ (check_vect_support_and_set_flags): Likewise.

12471

+

12472

+ Backport from mainline

12473

+ 2013-07-31 Michael Meissner <meissner@linux.vnet.ibm.com>

12474

+

12475

+ * config/rs6000/predicates.md (fusion_gpr_addis): New predicates

12476

+ to support power8 load fusion.

12477

+ (fusion_gpr_mem_load): Likewise.

12478

+

12479

+ * config/rs6000/rs6000-modes.def (PTImode): Update a comment.

12480

+

12481

+ * config/rs6000/rs6000-protos.h (fusion_gpr_load_p): New

12482

+ declarations for power8 load fusion.

12483

+ (emit_fusion_gpr_load): Likewise.

12484

+

12485

+ * config/rs6000/rs6000.c (rs6000_option_override_internal): If

12486

+ tuning for power8, turn on fusion mode by default. Turn on sign

12487

+ extending fusion mode if normal fusion mode is on, and we are at

12488

+ -O2 or -O3.

12489

+ (fusion_gpr_load_p): New function, return true if we can fuse an

12490

+ addis instruction with a dependent load to a GPR.

12491

+ (emit_fusion_gpr_load): Emit the instructions for power8 load

12492

+ fusion to GPRs.

12493

+

12494

+ * config/rs6000/vsx.md (VSX_M2): New iterator for fusion

12495

+ peepholes.

12496

+ (VSX load fusion peepholes): New peepholes to fuse together an

12497

+ addi instruction with a VSX load instruction.

12498

+

12499

+ * config/rs6000/rs6000.md (GPR load fusion peepholes): New

12500

+ peepholes to fuse an addis instruction with a load to a GPR base

12501

+ register. If we are supporting sign extending fusions, convert

12502

+ sign extending loads to zero extending loads and add an explicit

12503

+ sign extension.

12504

+

12505

+ Backport from mainline

12506

+ 2013-07-18 Pat Haugen <pthaugen@us.ibm.com>

12507

+

12508

+ * config/rs6000/rs6000.c (rs6000_option_override_internal): Adjust flag

12509

+ interaction for new Power8 flags and VSX.

12510

+

12511

+ Back port from the trunk

12512

+ 2013-06-28 Michael Meissner <meissner@linux.vnet.ibm.com>

12513

+

12514

+ PR target/57744

12515

+ * config/rs6000/rs6000.h (MODES_TIEABLE_P): Do not allow PTImode

12516

+ to tie with any other modes. Eliminate Altivec vector mode tests,

12517

+ since these are a subset of ALTIVEC or VSX vector modes. Simplify

12518

+ code, to return 0 if testing MODE2 for a condition, if we've

12519

+ already tested MODE1 for the same condition.

12520

+

12521

+ Backport from mainline

12522

+ 2013-06-28 Pat Haugen <pthaugen@us.ibm.com>

12523

+

12524

+ * config/rs6000/rs6000.md (define_insn ""): Fix insn type.

12525

+

12526

+ Back port from the trunk

12527

+ 2013-06-26 Michael Meissner <meissner@linux.vnet.ibm.com>

12528

+ Pat Haugen <pthaugen@us.ibm.com>

12529

+ Peter Bergner <bergner@vnet.ibm.com>

12530

+

12531

+ * config/rs6000/power8.md: New.

12532

+ * config/rs6000/rs6000-cpus.def (RS6000_CPU table): Adjust processor

12533

+ setting for power8 entry.

12534

+ * config/rs6000/t-rs6000 (MD_INCLUDES): Add power8.md.

12535

+ * config/rs6000/rs6000.c (is_microcoded_insn, is_cracked_insn): Adjust

12536

+ test for Power4/Power5 only.

12537

+ (insn_must_be_first_in_group, insn_must_be_last_in_group): Add Power8

12538

+ support.

12539

+ (force_new_group): Adjust comment.

12540

+ * config/rs6000/rs6000.md: Include power8.md.

12541

+

12542

+ Back port from the trunk

12543

+ 2013-06-14 Michael Meissner <meissner@linux.vnet.ibm.com>

12544

+

12545

+ PR target/57615

12546

+ * config/rs6000/rs6000.md (mov<mode>_ppc64): Call

12547

+ rs6000_output_move_128bit to handle emitting quad memory

12548

+ operations. Set attribute length to 8 bytes.

12549

+

12550

+ Back port from the trunk

12551

+ 2013-06-13 Michael Meissner <meissner@linux.vnet.ibm.com>

12552

+

12553

+ * config/rs6000/rs6000.c (rs6000_option_override_internal): Move

12554

+ test for clearing quad memory on 32-bit later.

12555

+

12556

+ Back port from the trunk

12557

+

12558

+ 2013-06-12 Michael Meissner <meissner@linux.vnet.ibm.com>

12559

+ Pat Haugen <pthaugen@us.ibm.com>

12560

+ Peter Bergner <bergner@vnet.ibm.com>

12561

+

12562

+ * config/rs6000/rs6000.c (emit_load_locked): Add support for

12563

+ power8 byte, half-word, and quad-word atomic instructions.

12564

+ (emit_store_conditional): Likewise.

12565

+ (rs6000_expand_atomic_compare_and_swap): Likewise.

12566

+ (rs6000_expand_atomic_op): Likewise.

12567

+

12568

+ * config/rs6000/sync.md (larx): Add new modes for power8.

12569

+ (stcx): Likewise.

12570

+ (AINT): New mode iterator to include TImode as well as normal

12571

+ integer modes on power8.

12572

+ (fetchop_pred): Use int_reg_operand instead of gpc_reg_operand so

12573

+ that VSX registers are not considered. Use AINT mode iterator

12574

+ instead of INT1 to allow inclusion of quad word atomic operations

12575

+ on power8.

12576

+ (load_locked<mode>): Likewise.

12577

+ (store_conditional<mode>): Likewise.

12578

+ (atomic_compare_and_swap<mode>): Likewise.

12579

+ (atomic_exchange<mode>): Likewise.

12580

+ (atomic_nand<mode>): Likewise.

12581

+ (atomic_fetch_<fetchop_name><mode>): Likewise.

12582

+ (atomic_nand_fetch<mode>): Likewise.

12583

+ (mem_thread_fence): Use gen_loadsync_<mode> instead of enumerating

12584

+ each type.

12585

+ (ATOMIC): On power8, add QImode, HImode modes.

12586

+ (load_locked<QHI:mode>_si): Varients of load_locked for QI/HI

12587

+ modes that promote to SImode.

12588

+ (load_lockedti): Convert TImode arguments to PTImode, so that we

12589

+ get a guaranteed even/odd register pair.

12590

+ (load_lockedpti): Likewise.

12591

+ (store_conditionalti): Likewise.

12592

+ (store_conditionalpti): Likewise.

12593

+

12594

+ * config/rs6000/rs6000.md (QHI): New mode iterator for power8

12595

+ atomic load/store instructions.

12596

+ (HSI): Likewise.

12597

+

12598

+ Back port from the trunk

12599

+

12600

+ 2013-06-10 Michael Meissner <meissner@linux.vnet.ibm.com>

12601

+ Pat Haugen <pthaugen@us.ibm.com>

12602

+ Peter Bergner <bergner@vnet.ibm.com>

12603

+

12604

+ * config/rs6000/vector.md (GPR move splitter): Do not split moves

12605

+ of vectors in GPRS if they are direct moves or quad word load or

12606

+ store moves.

12607

+

12608

+ * config/rs6000/rs6000-protos.h (rs6000_output_move_128bit): Add

12609

+ declaration.

12610

+ (direct_move_p): Likewise.

12611

+ (quad_load_store_p): Likewise.

12612

+

12613

+ * config/rs6000/rs6000.c (enum rs6000_reg_type): Simplify register

12614

+ classes into bins based on the physical register type.

12615

+ (reg_class_to_reg_type): Likewise.

12616

+ (IS_STD_REG_TYPE): Likewise.

12617

+ (IS_FP_VECT_REG_TYPE): Likewise.

12618

+ (reload_fpr_gpr): Arrays to determine what insn to use if we can

12619

+ use direct move instructions.

12620

+ (reload_gpr_vsx): Likewise.

12621

+ (reload_vsx_gpr): Likewise.

12622

+ (rs6000_init_hard_regno_mode_ok): Precalculate the register type

12623

+ information that is a simplification of register classes. Also

12624

+ precalculate direct move reload helpers.

12625

+ (direct_move_p): New function to return true if the operation can

12626

+ be done as a direct move instruciton.

12627

+ (quad_load_store_p): New function to return true if the operation

12628

+ is a quad memory operation.

12629

+ (rs6000_legitimize_address): If quad memory, only allow register

12630

+ indirect for TImode addresses.

12631

+ (rs6000_legitimate_address_p): Likewise.

12632

+ (enum reload_reg_type): Delete, replace with rs6000_reg_type.

12633

+ (rs6000_reload_register_type): Likewise.

12634

+ (register_to_reg_type): Return register type.

12635

+ (rs6000_secondary_reload_simple_move): New helper function for

12636

+ secondary reload and secondary memory needed to identify anything

12637

+ that is a simple move, and does not need reloading.

12638

+ (rs6000_secondary_reload_direct_move): New helper function for

12639

+ secondary reload to identify cases that can be done with several

12640

+ instructions via the direct move instructions.

12641

+ (rs6000_secondary_reload_move): New helper function for secondary

12642

+ reload to identify moves between register types that can be done.

12643

+ (rs6000_secondary_reload): Add support for quad memory operations

12644

+ and for direct move.

12645

+ (rs6000_secondary_memory_needed): Likewise.

12646

+ (rs6000_debug_secondary_memory_needed): Change argument names.

12647

+ (rs6000_output_move_128bit): New function to return the move to

12648

+ use for 128-bit moves, including knowing about the various

12649

+ limitations of quad memory operations.

12650

+

12651

+ * config/rs6000/vsx.md (vsx_mov<mode>): Add support for quad

12652

+ memory operations. call rs6000_output_move_128bit for the actual

12653

+ instruciton(s) to generate.

12654

+ (vsx_movti_64bit): Likewise.

12655

+

12656

+ * config/rs6000/rs6000.md (UNSPEC_P8V_FMRGOW): New unspec values.

12657

+ (UNSPEC_P8V_MTVSRWZ): Likewise.

12658

+ (UNSPEC_P8V_RELOAD_FROM_GPR): Likewise.

12659

+ (UNSPEC_P8V_MTVSRD): Likewise.

12660

+ (UNSPEC_P8V_XXPERMDI): Likewise.

12661

+ (UNSPEC_P8V_RELOAD_FROM_VSX): Likewise.

12662

+ (UNSPEC_FUSION_GPR): Likewise.

12663

+ (FMOVE128_GPR): New iterator for direct move.

12664

+ (f32_lv): New mode attribute for load/store of SFmode/SDmode

12665

+ values.

12666

+ (f32_sv): Likewise.

12667

+ (f32_dm): Likewise.

12668

+ (zero_extend<mode>di2_internal1): Add support for power8 32-bit

12669

+ loads and direct move instructions.

12670

+ (zero_extendsidi2_lfiwzx): Likewise.

12671

+ (extendsidi2_lfiwax): Likewise.

12672

+ (extendsidi2_nocell): Likewise.

12673

+ (floatsi<mode>2_lfiwax): Likewise.

12674

+ (lfiwax): Likewise.

12675

+ (floatunssi<mode>2_lfiwzx): Likewise.

12676

+ (lfiwzx): Likewise.

12677

+ (fix_trunc<mode>_stfiwx): Likewise.

12678

+ (fixuns_trunc<mode>_stfiwx): Likewise.

12679

+ (mov<mode>_hardfloat, 32-bit floating point): Likewise.

12680

+ (mov<move>_hardfloat64, 64-bit floating point): Likewise.

12681

+ (parity<mode>2_cmpb): Set length/type attr.

12682

+ (unnamed shift right patterns, mov<mode>_internal2): Change type attr

12683

+ for 'mr.' to fast_compare.

12684

+ (bpermd_<mode>): Change type attr to popcnt.

12685

+ (p8_fmrgow_<mode>): New insns for power8 direct move support.

12686

+ (p8_mtvsrwz_1): Likewise.

12687

+ (p8_mtvsrwz_2): Likewise.

12688

+ (reload_fpr_from_gpr<mode>): Likewise.

12689

+ (p8_mtvsrd_1): Likewise.

12690

+ (p8_mtvsrd_2): Likewise.

12691

+ (p8_xxpermdi_<mode>): Likewise.

12692

+ (reload_vsx_from_gpr<mode>): Likewise.

12693

+ (reload_vsx_from_gprsf): Likewise.

12694

+ (p8_mfvsrd_3_<mode>): LIkewise.

12695

+ (reload_gpr_from_vsx<mode>): Likewise.

12696

+ (reload_gpr_from_vsxsf): Likewise.

12697

+ (p8_mfvsrd_4_disf): Likewise.

12698

+ (multi-word GPR splits): Do not split direct moves or quad memory

12699

+ operations.

12700

+

12701

+ Backport from the trunk

12702

+

12703

+ 2013-06-06 Michael Meissner <meissner@linux.vnet.ibm.com>

12704

+ Pat Haugen <pthaugen@us.ibm.com>

12705

+ Peter Bergner <bergner@vnet.ibm.com>

12706

+

12707

+ * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions):

12708

+ Document new power8 builtins.

12709

+

12710

+ * config/rs6000/vector.md (and<mode>3): Add a clobber/scratch of a

12711

+ condition code register, to allow 128-bit logical operations to be

12712

+ done in the VSX or GPR registers.

12713

+ (nor<mode>3): Use the canonical form for nor.

12714

+ (eqv<mode>3): Add expanders for power8 xxleqv, xxlnand, xxlorc,

12715

+ vclz*, and vpopcnt* vector instructions.

12716

+ (nand<mode>3): Likewise.

12717

+ (orc<mode>3): Likewise.

12718

+ (clz<mode>2): LIkewise.

12719

+ (popcount<mode>2): Likewise.

12720

+

12721

+ * config/rs6000/predicates.md (int_reg_operand): Rework tests so

12722

+ that only the GPRs are recognized.

12723

+

12724

+ * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add

12725

+ support for new power8 builtins.

12726

+

12727

+ * config/rs6000/rs6000-builtin.def (xscvspdpn): Add new power8

12728

+ builtin functions.

12729

+ (xscvdpspn): Likewise.

12730

+ (vclz): Likewise.

12731

+ (vclzb): Likewise.

12732

+ (vclzh): Likewise.

12733

+ (vclzw): Likewise.

12734

+ (vclzd): Likewise.

12735

+ (vpopcnt): Likewise.

12736

+ (vpopcntb): Likewise.

12737

+ (vpopcnth): Likewise.

12738

+ (vpopcntw): Likewise.

12739

+ (vpopcntd): Likewise.

12740

+ (vgbbd): Likewise.

12741

+ (vmrgew): Likewise.

12742

+ (vmrgow): Likewise.

12743

+ (eqv): Likewise.

12744

+ (eqv_v16qi3): Likewise.

12745

+ (eqv_v8hi3): Likewise.

12746

+ (eqv_v4si3): Likewise.

12747

+ (eqv_v2di3): Likewise.

12748

+ (eqv_v4sf3): Likewise.

12749

+ (eqv_v2df3): Likewise.

12750

+ (nand): Likewise.

12751

+ (nand_v16qi3): Likewise.

12752

+ (nand_v8hi3): Likewise.

12753

+ (nand_v4si3): Likewise.

12754

+ (nand_v2di3): Likewise.

12755

+ (nand_v4sf3): Likewise.

12756

+ (nand_v2df3): Likewise.

12757

+ (orc): Likewise.

12758

+ (orc_v16qi3): Likewise.

12759

+ (orc_v8hi3): Likewise.

12760

+ (orc_v4si3): Likewise.

12761

+ (orc_v2di3): Likewise.

12762

+ (orc_v4sf3): Likewise.

12763

+ (orc_v2df3): Likewise.

12764

+

12765

+ * config/rs6000/rs6000.c (rs6000_option_override_internal): Only

12766

+ allow power8 quad mode in 64-bit.

12767

+ (rs6000_builtin_vectorized_function): Add support to vectorize

12768

+ ISA 2.07 count leading zeros, population count builtins.

12769

+ (rs6000_expand_vector_init): On ISA 2.07 use xscvdpspn to form

12770

+ V4SF vectors instead of xscvdpsp to avoid IEEE related traps.

12771

+ (builtin_function_type): Add vgbbd builtin function which takes an

12772

+ unsigned argument.

12773

+ (altivec_expand_vec_perm_const): Add support for new power8 merge

12774

+ instructions.

12775

+

12776

+ * config/rs6000/vsx.md (VSX_L2): New iterator for 128-bit types,

12777

+ that does not include TImdoe for use with 32-bit.

12778

+ (UNSPEC_VSX_CVSPDPN): Support for power8 xscvdpspn and xscvspdpn

12779

+ instructions.

12780

+ (UNSPEC_VSX_CVDPSPN): Likewise.

12781

+ (vsx_xscvdpspn): Likewise.

12782

+ (vsx_xscvspdpn): Likewise.

12783

+ (vsx_xscvdpspn_scalar): Likewise.

12784

+ (vsx_xscvspdpn_directmove): Likewise.

12785

+ (vsx_and<mode>3): Split logical operations into 32-bit and

12786

+ 64-bit. Add support to do logical operations on TImode as well as

12787

+ VSX vector types. Allow logical operations to be done in either

12788

+ VSX registers or in general purpose registers in 64-bit mode. Add

12789

+ splitters if GPRs were used. For AND, add clobber of CCmode to

12790

+ allow use of ANDI on GPRs. Rewrite nor to use the canonical RTL

12791

+ encoding.

12792

+ (vsx_and<mode>3_32bit): Likewise.

12793

+ (vsx_and<mode>3_64bit): Likewise.

12794

+ (vsx_ior<mode>3): Likewise.

12795

+ (vsx_ior<mode>3_32bit): Likewise.

12796

+ (vsx_ior<mode>3_64bit): Likewise.

12797

+ (vsx_xor<mode>3): Likewise.

12798

+ (vsx_xor<mode>3_32bit): Likewise.

12799

+ (vsx_xor<mode>3_64bit): Likewise.

12800

+ (vsx_one_cmpl<mode>2): Likewise.

12801

+ (vsx_one_cmpl<mode>2_32bit): Likewise.

12802

+ (vsx_one_cmpl<mode>2_64bit): Likewise.

12803

+ (vsx_nor<mode>3): Likewise.

12804

+ (vsx_nor<mode>3_32bit): Likewise.

12805

+ (vsx_nor<mode>3_64bit): Likewise.

12806

+ (vsx_andc<mode>3): Likewise.

12807

+ (vsx_andc<mode>3_32bit): Likewise.

12808

+ (vsx_andc<mode>3_64bit): Likewise.

12809

+ (vsx_eqv<mode>3_32bit): Add support for power8 xxleqv, xxlnand,

12810

+ and xxlorc instructions.

12811

+ (vsx_eqv<mode>3_64bit): Likewise.

12812

+ (vsx_nand<mode>3_32bit): Likewise.

12813

+ (vsx_nand<mode>3_64bit): Likewise.

12814

+ (vsx_orc<mode>3_32bit): Likewise.

12815

+ (vsx_orc<mode>3_64bit): Likewise.

12816

+

12817

+ * config/rs6000/rs6000.h (VLOGICAL_REGNO_P): Update comment.

12818

+

12819

+ * config/rs6000/altivec.md (UNSPEC_VGBBD): Add power8 vgbbd

12820

+ instruction.

12821

+ (p8_vmrgew): Add power8 vmrgew and vmrgow instructions.

12822

+ (p8_vmrgow): Likewise.

12823

+ (altivec_and<mode>3): Add clobber of CCmode to allow AND using

12824

+ GPRs to be split under VSX.

12825

+ (p8v_clz<mode>2): Add power8 count leading zero support.

12826

+ (p8v_popcount<mode>2): Add power8 population count support.

12827

+ (p8v_vgbbd): Add power8 gather bits by bytes by doubleword

12828

+ support.

12829

+

12830

+ * config/rs6000/rs6000.md (eqv<mode>3): Add support for powerp eqv

12831

+ instruction.

12832

+

12833

+ * config/rs6000/altivec.h (vec_eqv): Add defines to export power8

12834

+ builtin functions.

12835

+ (vec_nand): Likewise.

12836

+ (vec_vclz): Likewise.

12837

+ (vec_vclzb): Likewise.

12838

+ (vec_vclzd): Likewise.

12839

+ (vec_vclzh): Likewise.

12840

+ (vec_vclzw): Likewise.

12841

+ (vec_vgbbd): Likewise.

12842

+ (vec_vmrgew): Likewise.

12843

+ (vec_vmrgow): Likewise.

12844

+ (vec_vpopcnt): Likewise.

12845

+ (vec_vpopcntb): Likewise.

12846

+ (vec_vpopcntd): Likewise.

12847

+ (vec_vpopcnth): Likewise.

12848

+ (vec_vpopcntw): Likewise.

12849

+

12850

+ Backport from trunk

12851

+

12852

+ 2013-05-29 Michael Meissner <meissner@linux.vnet.ibm.com>

12853

+ Pat Haugen <pthaugen@us.ibm.com>

12854

+ Peter Bergner <bergner@vnet.ibm.com>

12855

+

12856

+ * config/rs6000/vector.md (VEC_I): Add support for new power8 V2DI

12857

+ instructions.

12858

+ (VEC_A): Likewise.

12859

+ (VEC_C): Likewise.

12860

+ (vrotl<mode>3): Likewise.

12861

+ (vashl<mode>3): Likewise.

12862

+ (vlshr<mode>3): Likewise.

12863

+ (vashr<mode>3): Likewise.

12864

+

12865

+ * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add

12866

+ support for power8 V2DI builtins.

12867

+

12868

+ * config/rs6000/rs6000-builtin.def (abs_v2di): Add support for

12869

+ power8 V2DI builtins.

12870

+ (vupkhsw): Likewise.

12871

+ (vupklsw): Likewise.

12872

+ (vaddudm): Likewise.

12873

+ (vminsd): Likewise.

12874

+ (vmaxsd): Likewise.

12875

+ (vminud): Likewise.

12876

+ (vmaxud): Likewise.

12877

+ (vpkudum): Likewise.

12878

+ (vpksdss): Likewise.

12879

+ (vpkudus): Likewise.

12880

+ (vpksdus): Likewise.

12881

+ (vrld): Likewise.

12882

+ (vsld): Likewise.

12883

+ (vsrd): Likewise.

12884

+ (vsrad): Likewise.

12885

+ (vsubudm): Likewise.

12886

+ (vcmpequd): Likewise.

12887

+ (vcmpgtsd): Likewise.

12888

+ (vcmpgtud): Likewise.

12889

+ (vcmpequd_p): Likewise.

12890

+ (vcmpgtsd_p): Likewise.

12891

+ (vcmpgtud_p): Likewise.

12892

+ (vupkhsw): Likewise.

12893

+ (vupklsw): Likewise.

12894

+ (vaddudm): Likewise.

12895

+ (vmaxsd): Likewise.

12896

+ (vmaxud): Likewise.

12897

+ (vminsd): Likewise.

12898

+ (vminud): Likewise.

12899

+ (vpksdss): Likewise.

12900

+ (vpksdus): Likewise.

12901

+ (vpkudum): Likewise.

12902

+ (vpkudus): Likewise.

12903

+ (vrld): Likewise.

12904

+ (vsld): Likewise.

12905

+ (vsrad): Likewise.

12906

+ (vsrd): Likewise.

12907

+ (vsubudm): Likewise.

12908

+

12909

+ * config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Add

12910

+ support for power8 V2DI instructions.

12911

+

12912

+ * config/rs6000/altivec.md (UNSPEC_VPKUHUM): Add support for

12913

+ power8 V2DI instructions. Combine pack and unpack insns to use an

12914

+ iterator for each mode. Check whether a particular mode supports

12915

+ Altivec instructions instead of just checking TARGET_ALTIVEC.

12916

+ (UNSPEC_VPKUWUM): Likewise.

12917

+ (UNSPEC_VPKSHSS): Likewise.

12918

+ (UNSPEC_VPKSWSS): Likewise.

12919

+ (UNSPEC_VPKUHUS): Likewise.

12920

+ (UNSPEC_VPKSHUS): Likewise.

12921

+ (UNSPEC_VPKUWUS): Likewise.

12922

+ (UNSPEC_VPKSWUS): Likewise.

12923

+ (UNSPEC_VPACK_SIGN_SIGN_SAT): Likewise.

12924

+ (UNSPEC_VPACK_SIGN_UNS_SAT): Likewise.

12925

+ (UNSPEC_VPACK_UNS_UNS_SAT): Likewise.

12926

+ (UNSPEC_VPACK_UNS_UNS_MOD): Likewise.

12927

+ (UNSPEC_VUPKHSB): Likewise.

12928

+ (UNSPEC_VUNPACK_HI_SIGN): Likewise.

12929

+ (UNSPEC_VUNPACK_LO_SIGN): Likewise.

12930

+ (UNSPEC_VUPKHSH): Likewise.

12931

+ (UNSPEC_VUPKLSB): Likewise.

12932

+ (UNSPEC_VUPKLSH): Likewise.

12933

+ (VI2): Likewise.

12934

+ (VI_char): Likewise.

12935

+ (VI_scalar): Likewise.

12936

+ (VI_unit): Likewise.

12937

+ (VP): Likewise.

12938

+ (VP_small): Likewise.

12939

+ (VP_small_lc): Likewise.

12940

+ (VU_char): Likewise.

12941

+ (add<mode>3): Likewise.

12942

+ (altivec_vaddcuw): Likewise.

12943

+ (altivec_vaddu<VI_char>s): Likewise.

12944

+ (altivec_vadds<VI_char>s): Likewise.

12945

+ (sub<mode>3): Likewise.

12946

+ (altivec_vsubcuw): Likewise.

12947

+ (altivec_vsubu<VI_char>s): Likewise.

12948

+ (altivec_vsubs<VI_char>s): Likewise.

12949

+ (altivec_vavgs<VI_char>): Likewise.

12950

+ (altivec_vcmpbfp): Likewise.

12951

+ (altivec_eq<mode>): Likewise.

12952

+ (altivec_gt<mode>): Likewise.

12953

+ (altivec_gtu<mode>): Likewise.

12954

+ (umax<mode>3): Likewise.

12955

+ (smax<mode>3): Likewise.

12956

+ (umin<mode>3): Likewise.

12957

+ (smin<mode>3): Likewise.

12958

+ (altivec_vpkuhum): Likewise.

12959

+ (altivec_vpkuwum): Likewise.

12960

+ (altivec_vpkshss): Likewise.

12961

+ (altivec_vpkswss): Likewise.

12962

+ (altivec_vpkuhus): Likewise.

12963

+ (altivec_vpkshus): Likewise.

12964

+ (altivec_vpkuwus): Likewise.

12965

+ (altivec_vpkswus): Likewise.

12966

+ (altivec_vpks<VI_char>ss): Likewise.

12967

+ (altivec_vpks<VI_char>us): Likewise.

12968

+ (altivec_vpku<VI_char>us): Likewise.

12969

+ (altivec_vpku<VI_char>um): Likewise.

12970

+ (altivec_vrl<VI_char>): Likewise.

12971

+ (altivec_vsl<VI_char>): Likewise.

12972

+ (altivec_vsr<VI_char>): Likewise.

12973

+ (altivec_vsra<VI_char>): Likewise.

12974

+ (altivec_vsldoi_<mode>): Likewise.

12975

+ (altivec_vupkhsb): Likewise.

12976

+ (altivec_vupkhs<VU_char>): Likewise.

12977

+ (altivec_vupkls<VU_char>): Likewise.

12978

+ (altivec_vupkhsh): Likewise.

12979

+ (altivec_vupklsb): Likewise.

12980

+ (altivec_vupklsh): Likewise.

12981

+ (altivec_vcmpequ<VI_char>_p): Likewise.

12982

+ (altivec_vcmpgts<VI_char>_p): Likewise.

12983

+ (altivec_vcmpgtu<VI_char>_p): Likewise.

12984

+ (abs<mode>2): Likewise.

12985

+ (vec_unpacks_hi_v16qi): Likewise.

12986

+ (vec_unpacks_hi_v8hi): Likewise.

12987

+ (vec_unpacks_lo_v16qi): Likewise.

12988

+ (vec_unpacks_hi_<VP_small_lc>): Likewise.

12989

+ (vec_unpacks_lo_v8hi): Likewise.

12990

+ (vec_unpacks_lo_<VP_small_lc>): Likewise.

12991

+ (vec_pack_trunc_v8h): Likewise.

12992

+ (vec_pack_trunc_v4si): Likewise.

12993

+ (vec_pack_trunc_<mode>): Likewise.

12994

+

12995

+ * config/rs6000/altivec.h (vec_vaddudm): Add defines for power8

12996

+ V2DI builtins.

12997

+ (vec_vmaxsd): Likewise.

12998

+ (vec_vmaxud): Likewise.

12999

+ (vec_vminsd): Likewise.

13000

+ (vec_vminud): Likewise.

13001

+ (vec_vpksdss): Likewise.

13002

+ (vec_vpksdus): Likewise.

13003

+ (vec_vpkudum): Likewise.

13004

+ (vec_vpkudus): Likewise.

13005

+ (vec_vrld): Likewise.

13006

+ (vec_vsld): Likewise.

13007

+ (vec_vsrad): Likewise.

13008

+ (vec_vsrd): Likewise.

13009

+ (vec_vsubudm): Likewise.

13010

+ (vec_vupkhsw): Likewise.

13011

+ (vec_vupklsw): Likewise.

13012

+

13013

+ 2013-05-22 Michael Meissner <meissner@linux.vnet.ibm.com>

13014

+ Pat Haugen <pthaugen@us.ibm.com>

13015

+ Peter Bergner <bergner@vnet.ibm.com>

13016

+

13017

+ * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions): Add

13018

+ documentation for the power8 crypto builtins.

13019

+

13020

+ * config/rs6000/t-rs6000 (MD_INCLUDES): Add crypto.md.

13021

+

13022

+ * config/rs6000/rs6000-builtin.def (BU_P8V_AV_1): Add support

13023

+ macros for defining power8 builtin functions.

13024

+ (BU_P8V_AV_2): Likewise.

13025

+ (BU_P8V_AV_P): Likewise.

13026

+ (BU_P8V_VSX_1): Likewise.

13027

+ (BU_P8V_OVERLOAD_1): Likewise.

13028

+ (BU_P8V_OVERLOAD_2): Likewise.

13029

+ (BU_CRYPTO_1): Likewise.

13030

+ (BU_CRYPTO_2): Likewise.

13031

+ (BU_CRYPTO_3): Likewise.

13032

+ (BU_CRYPTO_OVERLOAD_1): Likewise.

13033

+ (BU_CRYPTO_OVERLOAD_2): Likewise.

13034

+ (XSCVSPDP): Fix typo, point to the correct instruction.

13035

+ (VCIPHER): Add power8 crypto builtins.

13036

+ (VCIPHERLAST): Likewise.

13037

+ (VNCIPHER): Likewise.

13038

+ (VNCIPHERLAST): Likewise.

13039

+ (VPMSUMB): Likewise.

13040

+ (VPMSUMH): Likewise.

13041

+ (VPMSUMW): Likewise.

13042

+ (VPERMXOR_V2DI): Likewise.

13043

+ (VPERMXOR_V4SI: Likewise.

13044

+ (VPERMXOR_V8HI: Likewise.

13045

+ (VPERMXOR_V16QI: Likewise.

13046

+ (VSHASIGMAW): Likewise.

13047

+ (VSHASIGMAD): Likewise.

13048

+ (VPMSUM): Likewise.

13049

+ (VPERMXOR): Likewise.

13050

+ (VSHASIGMA): Likewise.

13051

+

13052

+ * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Define

13053

+ __CRYPTO__ if the crypto instructions are available.

13054

+ (altivec_overloaded_builtins): Add support for overloaded power8

13055

+ builtins.

13056

+

13057

+ * config/rs6000/rs6000.c (rs6000_expand_ternop_builtin): Add

13058

+ support for power8 crypto builtins.

13059

+ (builtin_function_type): Likewise.

13060

+ (altivec_init_builtins): Add support for builtins that take vector

13061

+ long long (V2DI) arguments.

13062

+

13063

+ * config/rs6000/crypto.md: New file, define power8 crypto

13064

+ instructions.

13065

+

13066

+ 2013-05-22 Michael Meissner <meissner@linux.vnet.ibm.com>

13067

+ Pat Haugen <pthaugen@us.ibm.com>

13068

+ Peter Bergner <bergner@vnet.ibm.com>

13069

+

13070

+ * doc/invoke.texi (Option Summary): Add power8 options.

13071

+ (RS/6000 and PowerPC Options): Likewise.

13072

+

13073

+ * doc/md.texi (PowerPC and IBM RS6000 constraints): Update to use

13074

+ constraints.md instead of rs6000.h. Reorder w* constraints. Add

13075

+ wm, wn, wr documentation.

13076

+

13077

+ * gcc/config/rs6000/constraints.md (wm): New constraint for VSX

13078

+ registers if direct move instructions are enabled.

13079

+ (wn): New constraint for no registers.

13080

+ (wq): New constraint for quad word even GPR registers.

13081

+ (wr): New constraint if 64-bit instructions are enabled.

13082

+ (wv): New constraint if power8 vector instructions are enabled.

13083

+ (wQ): New constraint for quad word memory locations.

13084

+

13085

+ * gcc/config/rs6000/predicates.md (const_0_to_15_operand): New

13086

+ constraint for 0..15 for crypto instructions.

13087

+ (gpc_reg_operand): If VSX allow registers in VSX registers as well

13088

+ as GPR and floating point registers.

13089

+ (int_reg_operand): New predicate to match only GPR registers.

13090

+ (base_reg_operand): New predicate to match base registers.

13091

+ (quad_int_reg_operand): New predicate to match even GPR registers

13092

+ for quad memory operations.

13093

+ (vsx_reg_or_cint_operand): New predicate to allow vector logical

13094

+ operations in both GPR and VSX registers.

13095

+ (quad_memory_operand): New predicate for quad memory operations.

13096

+ (reg_or_indexed_operand): New predicate for direct move support.

13097

+

13098

+ * gcc/config/rs6000/rs6000-cpus.def (ISA_2_5_MASKS_EMBEDDED):

13099

+ Inherit from ISA_2_4_MASKS, not ISA_2_2_MASKS.

13100

+ (ISA_2_7_MASKS_SERVER): New mask for ISA 2.07 (i.e. power8).

13101

+ (POWERPC_MASKS): Add power8 options.

13102

+ (power8 cpu): Use ISA_2_7_MASKS_SERVER instead of specifying the

13103

+ various options.

13104

+

13105

+ * gcc/config/rs6000/rs6000-c.c (rs6000_target_modify_macros):

13106

+ Define _ARCH_PWR8 and __POWER8_VECTOR__ for power8.

13107

+

13108

+ * gcc/config/rs6000/rs6000.opt (-mvsx-timode): Add documentation.

13109

+ (-mpower8-fusion): New power8 options.

13110

+ (-mpower8-fusion-sign): Likewise.

13111

+ (-mpower8-vector): Likewise.

13112

+ (-mcrypto): Likewise.

13113

+ (-mdirect-move): Likewise.

13114

+ (-mquad-memory): Likewise.

13115

+

13116

+ * gcc/config/rs6000/rs6000.c (power8_cost): Initial definition for

13117

+ power8.

13118

+ (rs6000_hard_regno_mode_ok): Make PTImode only match even GPR

13119

+ registers.

13120

+ (rs6000_debug_reg_print): Print the base register class if

13121

+ -mdebug=reg.

13122

+ (rs6000_debug_vector_unit): Add p8_vector.

13123

+ (rs6000_debug_reg_global): If -mdebug=reg, print power8 constraint

13124

+ definitions. Also print fusion state.

13125

+ (rs6000_init_hard_regno_mode_ok): Set up power8 constraints.

13126

+ (rs6000_builtin_mask_calculate): Add power8 builtin support.

13127

+ (rs6000_option_override_internal): Add support for power8.

13128

+ (rs6000_common_init_builtins): Add debugging for skipped builtins

13129

+ if -mdebug=builtin.

13130

+ (rs6000_adjust_cost): Add power8 support.

13131

+ (rs6000_issue_rate): Likewise.

13132

+ (insn_must_be_first_in_group): Likewise.

13133

+ (insn_must_be_last_in_group): Likewise.

13134

+ (force_new_group): Likewise.

13135

+ (rs6000_register_move_cost): Likewise.

13136

+ (rs6000_opt_masks): Likewise.

13137

+

13138

+ * config/rs6000/rs6000.h (ASM_CPU_POWER8_SPEC): If we don't have a

13139

+ power8 capable assembler, default to power7 options.

13140

+ (TARGET_DIRECT_MOVE): Likewise.

13141

+ (TARGET_CRYPTO): Likewise.

13142

+ (TARGET_P8_VECTOR): Likewise.

13143

+ (VECTOR_UNIT_P8_VECTOR_P): Define power8 vector support.

13144

+ (VECTOR_UNIT_VSX_OR_P8_VECTOR_P): Likewise.

13145

+ (VECTOR_MEM_P8_VECTOR_P): Likewise.

13146

+ (VECTOR_MEM_VSX_OR_P8_VECTOR_P): Likewise.

13147

+ (VECTOR_MEM_ALTIVEC_OR_VSX_P): Likewise.

13148

+ (TARGET_XSCVDPSPN): Likewise.

13149

+ (TARGET_XSCVSPDPN): Likewsie.

13150

+ (TARGET_SYNC_HI_QI): Likewise.

13151

+ (TARGET_SYNC_TI): Likewise.

13152

+ (MASK_CRYPTO): Likewise.

13153

+ (MASK_DIRECT_MOVE): Likewise.

13154

+ (MASK_P8_FUSION): Likewise.

13155

+ (MASK_P8_VECTOR): Likewise.

13156

+ (REG_ALLOC_ORDER): Move fr13 to be lower in priority so that the

13157

+ TFmode temporary used by some of the direct move instructions to

13158

+ get two FP temporary registers does not force creation of a stack

13159

+ frame.

13160

+ (VLOGICAL_REGNO_P): Allow vector logical operations in GPRs.

13161

+ (MODES_TIEABLE_P): Move the VSX tests above the Altivec tests so

13162

+ that any VSX registers are tieable, even if they are also an

13163

+ Altivec vector mode.

13164

+ (r6000_reg_class_enum): Add wm, wr, wv constraints.

13165

+ (RS6000_BTM_P8_VECTOR): Power8 builtin support.

13166

+ (RS6000_BTM_CRYPTO): Likewise.

13167

+ (RS6000_BTM_COMMON): Likewise.

13168

+

13169

+ * config/rs6000/rs6000.md (cpu attribute): Add power8.

13170

+ * config/rs6000/rs6000-opts.h (PROCESSOR_POWER8): Likewise.

13171

+ (enum rs6000_vector): Add power8 vector support.

13172

+

13173

+

13174

+ Backport from mainline

13175

+ 2013-03-20 Pat Haugen <pthaugen@us.ibm.com>

13176

+

13177

+ * config/rs6000/predicates.md (indexed_address, update_address_mem

13178

+ update_indexed_address_mem): New predicates.

13179

+ * config/rs6000/vsx.md (vsx_extract_<mode>_zero): Set correct "type"

13180

+ attribute for load/store instructions.

13181

+ * config/rs6000/dfp.md (movsd_store): Likewise.

13182

+ (movsd_load): Likewise.

13183

+ * config/rs6000/rs6000.md (zero_extend<mode>di2_internal1): Likewise.

13184

+ (unnamed HI->DI extend define_insn): Likewise.

13185

+ (unnamed SI->DI extend define_insn): Likewise.

13186

+ (unnamed QI->SI extend define_insn): Likewise.

13187

+ (unnamed QI->HI extend define_insn): Likewise.

13188

+ (unnamed HI->SI extend define_insn): Likewise.

13189

+ (unnamed HI->SI extend define_insn): Likewise.

13190

+ (extendsfdf2_fpr): Likewise.

13191

+ (movsi_internal1): Likewise.

13192

+ (movsi_internal1_single): Likewise.

13193

+ (movhi_internal): Likewise.

13194

+ (movqi_internal): Likewise.

13195

+ (movcc_internal1): Correct mnemonic for stw insn. Set correct "type"

13196

+ attribute for load/store instructions.

13197

+ (mov<mode>_hardfloat): Set correct "type" attribute for load/store

13198

+ instructions.

13199

+ (mov<mode>_softfloat): Likewise.

13200

+ (mov<mode>_hardfloat32): Likewise.

13201

+ (mov<mode>_hardfloat64): Likewise.

13202

+ (mov<mode>_softfloat64): Likewise.

13203

+ (movdi_internal32): Likewise.

13204

+ (movdi_internal64): Likewise.

13205

+ (probe_stack_<mode>): Likewise.

13206

+

13207

+ Backport from mainline

13208

+ 2013-03-20 Michael Meissner <meissner@linux.vnet.ibm.com>

13209

+

13210

+ * config/rs6000/vector.md (VEC_R): Add 32-bit integer, binary

13211

+ floating point, and decimal floating point to reload iterator.

13212

+

13213

+ * config/rs6000/constraints.md (wl constraint): New constraints to

13214

+ return FLOAT_REGS if certain options are used to reduce the number

13215

+ of separate patterns that exist in the file.

13216

+ (wx constraint): Likewise.

13217

+ (wz constraint): Likewise.

13218

+

13219

+ * config/rs6000/rs6000.c (rs6000_debug_reg_global): If

13220

+ -mdebug=reg, print wg, wl, wx, and wz constraints.

13221

+ (rs6000_init_hard_regno_mode_ok): Initialize new constraints.

13222

+ Initialize the reload functions for 64-bit binary/decimal floating

13223

+ point types.

13224

+ (reg_offset_addressing_ok_p): If we are on a power7 or later, use

13225

+ LFIWZX and STFIWX to load/store 32-bit decimal types, and don't

13226

+ create the buffer on the stack to overcome not having a 32-bit

13227

+ load and store.

13228

+ (rs6000_emit_move): Likewise.

13229

+ (rs6000_secondary_memory_needed_rtx): Likewise.

13230

+ (rs6000_alloc_sdmode_stack_slot): Likewise.

13231

+ (rs6000_preferred_reload_class): On VSX, we can create SFmode 0.0f

13232

+ via xxlxor, just like DFmode 0.0.

13233

+

13234

+ * config/rs6000/rs6000.h (TARGET_NO_SDMODE_STACK): New macro)

13235

+ (define as 1 if we are running on a power7 or newer.

13236

+ (enum r6000_reg_class_enum): Add new constraints.

13237

+

13238

+ * config/rs6000/dfp.md (movsd): Delete, combine with binary

13239

+ floating point moves in rs6000.md. Combine power6x (mfpgpr) moves

13240

+ with other moves by using conditional constraits (wg). Use LFIWZX

13241

+ and STFIWX for loading SDmode on power7. Use xxlxor to create

13242

+ 0.0f.

13243

+ (movsd splitter): Likewise.

13244

+ (movsd_hardfloat): Likewise.

13245

+ (movsd_softfloat): Likewise.

13246

+

13247

+ * config/rs6000/rs6000.md (FMOVE32): New iterators to combine

13248

+ binary and decimal floating point moves.

13249

+ (fmove_ok): New attributes to combine binary and decimal floating

13250

+ point moves, and to combine power6x (mfpgpr) moves along normal

13251

+ floating moves.

13252

+ (real_value_to_target): Likewise.

13253

+ (f32_lr): Likewise.

13254

+ (f32_lm): Likewise.

13255

+ (f32_li): Likewise.

13256

+ (f32_sr): Likewise.

13257

+ (f32_sm): Likewise.

13258

+ (f32_si): Likewise.

13259

+ (movsf): Combine binary and decimal floating point moves. Combine

13260

+ power6x (mfpgpr) moves with other moves by using conditional

13261

+ constraits (wg). Use LFIWZX and STFIWX for loading SDmode on

13262

+ power7.

13263

+ (mov<mode> for SFmode/SDmode); Likewise.

13264

+ (SFmode/SDmode splitters): Likewise.

13265

+ (movsf_hardfloat): Likewise.

13266

+ (mov<mode>_hardfloat for SFmode/SDmode): Likewise.

13267

+ (movsf_softfloat): Likewise.

13268

+ (mov<mode>_softfloat for SFmode/SDmode): Likewise.

13269

+

13270

+ * doc/md.texi (PowerPC and IBM RS6000 constraints): Document wl)

13271

+ (wx and wz constraints.

13272

+

13273

+ * config/rs6000/constraints.md (wg constraint): New constraint to

13274

+ return FLOAT_REGS if -mmfpgpr (power6x) was used.

13275

+

13276

+ * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Add wg

13277

+ constraint.

13278

+

13279

+ * config/rs6000/rs6000.c (rs6000_debug_reg_global): If

13280

+ -mdebug=reg, print wg, wl, wx, and wz constraints.

13281

+ (rs6000_init_hard_regno_mode_ok): Initialize new constraints.

13282

+ Initialize the reload functions for 64-bit binary/decimal floating

13283

+ point types.

13284

+ (reg_offset_addressing_ok_p): If we are on a power7 or later, use

13285

+ LFIWZX and STFIWX to load/store 32-bit decimal types, and don't

13286

+ create the buffer on the stack to overcome not having a 32-bit

13287

+ load and store.

13288

+ (rs6000_emit_move): Likewise.

13289

+ (rs6000_secondary_memory_needed_rtx): Likewise.

13290

+ (rs6000_alloc_sdmode_stack_slot): Likewise.

13291

+ (rs6000_preferred_reload_class): On VSX, we can create SFmode 0.0f

13292

+ via xxlxor, just like DFmode 0.0.

13293

+

13294

+

13295

+ * config/rs6000/dfp.md (movdd): Delete, combine with binary

13296

+ floating point moves in rs6000.md. Combine power6x (mfpgpr) moves

13297

+ with other moves by using conditional constraits (wg). Use LFIWZX

13298

+ and STFIWX for loading SDmode on power7.

13299

+ (movdd splitters): Likewise.

13300

+ (movdd_hardfloat32): Likewise.

13301

+ (movdd_softfloat32): Likewise.

13302

+ (movdd_hardfloat64_mfpgpr): Likewise.

13303

+ (movdd_hardfloat64): Likewise.

13304

+ (movdd_softfloat64): Likewise.

13305

+

13306

+ * config/rs6000/rs6000.md (FMOVE64): New iterators to combine

13307

+ 64-bit binary and decimal floating point moves.

13308

+ (FMOVE64X): Likewise.

13309

+ (movdf): Combine 64-bit binary and decimal floating point moves.

13310

+ Combine power6x (mfpgpr) moves with other moves by using

13311

+ conditional constraits (wg).

13312

+ (mov<mode> for DFmode/DDmode): Likewise.

13313

+ (DFmode/DDmode splitters): Likewise.

13314

+ (movdf_hardfloat32): Likewise.

13315

+ (mov<mode>_hardfloat32 for DFmode/DDmode): Likewise.

13316

+ (movdf_softfloat32): Likewise.

13317

+ (movdf_hardfloat64_mfpgpr): Likewise.

13318

+ (movdf_hardfloat64): Likewise.

13319

+ (mov<mode>_hardfloat64 for DFmode/DDmode): Likewise.

13320

+ (movdf_softfloat64): Likewise.

13321

+ (mov<mode>_softfloat64 for DFmode/DDmode): Likewise.

13322

+ (reload_<mode>_load): Move to later in the file so they aren't in

13323

+ the middle of the floating point move insns.

13324

+ (reload_<mode>_store): Likewise.

13325

+

13326

+ * doc/md.texi (PowerPC and IBM RS6000 constraints): Document wg

13327

+ constraint.

13328

+

13329

+ * config/rs6000/rs6000.c (rs6000_debug_reg_global): Print out wg

13330

+ constraint if -mdebug=reg.

13331

+ (rs6000_initi_hard_regno_mode_ok): Enable wg constraint if

13332

+ -mfpgpr. Enable using dd reload support if needed.

13333

+

13334

+ * config/rs6000/dfp.md (movtd): Delete, combine with 128-bit

13335

+ binary and decimal floating point moves in rs6000.md.

13336

+ (movtd_internal): Likewise.

13337

+

13338

+ * config/rs6000/rs6000.md (FMOVE128): Combine 128-bit binary and

13339

+ decimal floating point moves.

13340

+ (movtf): Likewise.

13341

+ (movtf_internal): Likewise.

13342

+ (mov<mode>_internal, TDmode/TFmode): Likewise.

13343

+ (movtf_softfloat): Likewise.

13344

+ (mov<mode>_softfloat, TDmode/TFmode): Likewise.

13345

+

13346

+ * config/rs6000/rs6000.md (movdi_mfpgpr): Delete, combine with

13347

+ movdi_internal64, using wg constraint for move direct operations.

13348

+ (movdi_internal64): Likewise.

13349

+

13350

+ * config/rs6000/rs6000.c (rs6000_debug_reg_global): Print

13351

+ MODES_TIEABLE_P for selected modes. Print the numerical value of

13352

+ the various virtual registers. Use GPR/FPR first/last values)

13353

+ (instead of hard coding the register numbers. Print which modes

13354

+ have reload functions registered.

13355

+ (rs6000_option_override_internal): If -mdebug=reg, trace the

13356

+ options settings before/after setting cpu, target and subtarget

13357

+ settings.

13358

+ (rs6000_secondary_reload_trace): Improve the RTL dump for

13359

+ -mdebug=addr and for secondary reload failures in

13360

+ rs6000_secondary_reload_inner.

13361

+ (rs6000_secondary_reload_fail): Likewise.

13362

+ (rs6000_secondary_reload_inner): Likewise.

13363

+

13364

+ * config/rs6000/rs6000.md (FIRST_GPR_REGNO): Add convenience

13365

+ macros for first/last GPR and FPR registers.

13366

+ (LAST_GPR_REGNO): Likewise.

13367

+ (FIRST_FPR_REGNO): Likewise.

13368

+ (LAST_FPR_REGNO): Likewise.

13369

+

13370

+ * config/rs6000/vector.md (mul<mode>3): Use the combined macro

13371

+ VECTOR_UNIT_ALTIVEC_OR_VSX_P instead of separate calls to

13372

+ VECTOR_UNIT_ALTIVEC_P and VECTOR_UNIT_VSX_P.

13373

+ (vcond<mode><mode>): Likewise.

13374

+ (vcondu<mode><mode>): Likewise.

13375

+ (vector_gtu<mode>): Likewise.

13376

+ (vector_gte<mode>): Likewise.

13377

+ (xor<mode>3): Don't allow logical operations on TImode in 32-bit

13378

+ to prevent the compiler from converting DImode operations to

13379

+ TImode.

13380

+ (ior<mode>3): Likewise.

13381

+ (and<mode>3): Likewise.

13382

+ (one_cmpl<mode>2): Likewise.

13383

+ (nor<mode>3): Likewise.

13384

+ (andc<mode>3): Likewise.

13385

+

13386

+ * config/rs6000/constraints.md (wt constraint): New constraint

13387

+ that returns VSX_REGS if TImode is allowed in VSX registers.

13388

+

13389

+ * config/rs6000/predicates.md (easy_fp_constant): 0.0f is an easy

13390

+ constant under VSX.

13391

+

13392

+ * config/rs6000/rs6000-modes.def (PTImode): Define, PTImode is

13393

+ similar to TImode, but it is restricted to being in the GPRs.

13394

+

13395

+ * config/rs6000/rs6000.opt (-mvsx-timode): New switch to allow

13396

+ TImode to occupy a single VSX register.

13397

+

13398

+ * config/rs6000/rs6000-cpus.def (ISA_2_6_MASKS_SERVER): Default to

13399

+ -mvsx-timode for power7/power8.

13400

+ (power7 cpu): Likewise.

13401

+ (power8 cpu): Likewise.

13402

+

13403

+ * config/rs6000/rs6000.c (rs6000_hard_regno_nregs_internal): Make

13404

+ sure that TFmode/TDmode take up two registers if they are ever

13405

+ allowed in the upper VSX registers.

13406

+ (rs6000_hard_regno_mode_ok): If -mvsx-timode, allow TImode in VSX

13407

+ registers.

13408

+ (rs6000_init_hard_regno_mode_ok): Likewise.

13409

+ (rs6000_debug_reg_global): Add debugging for PTImode and wt

13410

+ constraint. Print if LRA is turned on.

13411

+ (rs6000_option_override_internal): Give an error if -mvsx-timode

13412

+ and VSX is not enabled.

13413

+ (invalid_e500_subreg): Handle PTImode, restricting it to GPRs. If

13414

+ -mvsx-timode, restrict TImode to reg+reg addressing, and PTImode

13415

+ to reg+offset addressing. Use PTImode when checking offset

13416

+ addresses for validity.

13417

+ (reg_offset_addressing_ok_p): Likewise.

13418

+ (rs6000_legitimate_offset_address_p): Likewise.

13419

+ (rs6000_legitimize_address): Likewise.

13420

+ (rs6000_legitimize_reload_address): Likewise.

13421

+ (rs6000_legitimate_address_p): Likewise.

13422

+ (rs6000_eliminate_indexed_memrefs): Likewise.

13423

+ (rs6000_emit_move): Likewise.

13424

+ (rs6000_secondary_reload): Likewise.

13425

+ (rs6000_secondary_reload_inner): Handle PTImode. Allow 64-bit

13426

+ reloads to fpr registers to continue to use reg+offset addressing)

13427

+ (but 64-bit reloads to altivec registers need reg+reg addressing.

13428

+ Drop test for PRE_MODIFY, since VSX loads/stores no longer support

13429

+ it. Treat LO_SUM like a PLUS operation.

13430

+ (rs6000_secondary_reload_class): If type is 64-bit, prefer to use

13431

+ FLOAT_REGS instead of VSX_RGS to allow use of reg+offset

13432

+ addressing.

13433

+ (rs6000_cannot_change_mode_class): Do not allow TImode in VSX

13434

+ registers to share a register with a smaller sized type, since VSX

13435

+ puts scalars in the upper 64-bits.

13436

+ (print_operand): Add support for PTImode.

13437

+ (rs6000_register_move_cost): Use VECTOR_MEM_VSX_P instead of

13438

+ VECTOR_UNIT_VSX_P to catch types that can be loaded in VSX

13439

+ registers, but don't have arithmetic support.

13440

+ (rs6000_memory_move_cost): Add test for VSX.

13441

+ (rs6000_opt_masks): Add -mvsx-timode.

13442

+

13443

+ * config/rs6000/vsx.md (VSm): Change to use 64-bit aligned moves

13444

+ for TImode.

13445

+ (VSs): Likewise.

13446

+ (VSr): Use wt constraint for TImode.

13447

+ (VSv): Drop TImode support.

13448

+ (vsx_movti): Delete, replace with versions for 32-bit and 64-bit.

13449

+ (vsx_movti_64bit): Likewise.

13450

+ (vsx_movti_32bit): Likewise.

13451

+ (vec_store_<mode>): Use VSX iterator instead of vector iterator.

13452

+ (vsx_and<mode>3): Delete use of '?' constraint on inputs, just put

13453

+ one '?' on the appropriate output constraint. Do not allow TImode

13454

+ logical operations on 32-bit systems.

13455

+ (vsx_ior<mode>3): Likewise.

13456

+ (vsx_xor<mode>3): Likewise.

13457

+ (vsx_one_cmpl<mode>2): Likewise.

13458

+ (vsx_nor<mode>3): Likewise.

13459

+ (vsx_andc<mode>3): Likewise.

13460

+ (vsx_concat_<mode>): Likewise.

13461

+ (vsx_xxpermdi_<mode>): Fix thinko for non V2DF/V2DI modes.

13462

+

13463

+ * config/rs6000/rs6000.h (MASK_VSX_TIMODE): Map from

13464

+ OPTION_MASK_VSX_TIMODE.

13465

+ (enum rs6000_reg_class_enum): Add RS6000_CONSTRAINT_wt.

13466

+ (STACK_SAVEAREA_MODE): Use PTImode instead of TImode.

13467

+

13468

+ * config/rs6000/rs6000.md (INT mode attribute): Add PTImode.

13469

+ (TI2 iterator): New iterator for TImode, PTImode.

13470

+ (wd mode attribute): Add values for vector types.

13471

+ (movti_string): Replace TI move operations with operations for

13472

+ TImode and PTImode. Add support for TImode being allowed in VSX

13473

+ registers.

13474

+ (mov<mode>_string, TImode/PTImode): Likewise.

13475

+ (movti_ppc64): Likewise.

13476

+ (mov<mode>_ppc64, TImode/PTImode): Likewise.

13477

+ (TI mode splitters): Likewise.

13478

+

13479

+ * doc/md.texi (PowerPC and IBM RS6000 constraints): Document wt

13480

+ constraint.

13481

+

13482

+2014-04-04 Richard Biener <rguenther@suse.de>

13483

+

13484

+ * tree-ssanames.c (make_ssa_name_fn): Fix assert.

13485

+

13486

+2014-04-02 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>

13487

+

13488

+ * config/s390/s390.c (s390_expand_insv): Use GET_MODE_BITSIZE.

13489

+

13490

+2014-04-01 Richard Biener <rguenther@suse.de>

13491

+

13492

+ * gimple.h (struct gimple_statement_base): Align subcode to

13493

+ 16 bits.

13494

+

13495

+2014-04-01 Sebastian Huber <sebastian.huber@embedded-brains.de>

13496

+

13497

+ * doc/invoke.texi (mapp-regs): Clarify.

13498

+

13499

+2014-03-31 H.J. Lu <hongjiu.lu@intel.com>

13500

+

13501

+ PR rtl-optimization/60700

13502

+ Backport from mainline

13503

+ 2013-07-30 Zhenqiang Chen <zhenqiang.chen@linaro.org>

13504

+

13505

+ PR rtl-optimization/57637

13506

+ * function.c (move_insn_for_shrink_wrap): Also check the

13507

+ GEN set of the LIVE problem for the liveness analysis

13508

+ if it exists, otherwise give up.

13509

+

13510

+2014-03-30 Kaz Kojima <kkojima@gcc.gnu.org>

13511

+

13512

+ Backport from mainline

13513

+ 2014-03-19 Kaz Kojima <kkojima@gcc.gnu.org>

13514

+

13515

+ PR target/60039

13516

+ * config/sh/sh.md (udivsi3_i1): Clobber R1 register.

13517

+

13518

+2014-03-26 Martin Jambor <mjambor@suse.cz>

13519

+

13520

+ PR ipa/60419

13521

+ * ipa.c (symtab_remove_unreachable_nodes): Clear thunk and

13522

+ alias flags of nodes in the border.

13523

+

13524

+2014-03-26 Eric Botcazou <ebotcazou@adacore.com>

13525

+

13526

+ PR rtl-optimization/60452

13527

+ * rtlanal.c (rtx_addr_can_trap_p_1): Fix head comment.

13528

+ <case REG>: Return 1 for invalid offsets from the frame pointer.

13529

+

13530

+2014-03-24 Richard Biener <rguenther@suse.de>

13531

+

13532

+ PR tree-optimization/60429

13533

+ * tree-ssa-structalias.c (get_constraint_for_ptr_offset): Remove

13534

+ duplicated line.

13535

+

13536

+2014-03-23 Eric Botcazou <ebotcazou@adacore.com>

13537

+

13538

+ PR rtl-optimization/60601

13539

+ * bb-reorder.c (fix_up_fall_thru_edges): Test EDGE_FALLTHRU everywhere.

13540

+

13541

+ * gcc.c (eval_spec_function): Initialize save_growing_value.

13542

+

13543

+2014-03-20 Jakub Jelinek <jakub@redhat.com>

13544

+

13545

+ PR target/60568

13546

+ * config/i386/i386.c (x86_output_mi_thunk): Surround UNSPEC_GOT

13547

+ into CONST, put pic register as first operand of PLUS. Use

13548

+ gen_const_mem for both 32-bit and 64-bit PIC got loads.

13549

+

13550

+2014-03-20 Eric Botcazou <ebotcazou@adacore.com>

13551

+

13552

+ * config/sparc/sparc.c (sparc_do_work_around_errata): Implement work

13553

+ around for store forwarding issue in the FPU on the UT699.

13554

+ * config/sparc/sparc.md (in_branch_delay): Return false for single FP

13555

+ loads and operations if -mfix-ut699 is specified.

13556

+ (divtf3_hq): Tweak attribute.

13557

+ (sqrttf2_hq): Likewise.

13558

+

13559

+2014-03-18 Kai Tietz <ktietz@redhat.com>

13560

+

13561

+ PR rtl-optimization/56356

13562

+ * sdbout.c (sdbout_parms): Verify that parms'

13563

+ incoming argument is valid.

13564

+ (sdbout_reg_parms): Likewise.

13565

+

13566

+2014-03-18 Eric Botcazou <ebotcazou@adacore.com>

13567

+

13568

+ * config/sparc/sparc.c (sparc_do_work_around_errata): Speed up and use

13569

+ proper constant for the store mode.

13570

+

13571

+2014-03-17 Mikael Pettersson <mikpelinux@gmail.com>

13572

+ Committed by Bill Schmidt <wschmidt@linux.vnet.ibm.com>

13573

+

13574

+ Backport from mainline:

13575

+

13576

+ 2013-06-20 Joern Rennecke <joern.rennecke@embecosm.com>

13577

+

13578

+ PR rtl-optimization/57425

13579

+ PR rtl-optimization/57569

13580

+ * alias.c (write_dependence_p): Remove parameters mem_mode and

13581

+ canon_mem_addr. Add parameters x_mode, x_addr and x_canonicalized.

13582

+ Changed all callers.

13583

+ (canon_anti_dependence): Get comments and semantics in sync.

13584

+ Add parameter mem_canonicalized. Changed all callers.

13585

+ * rtl.h (canon_anti_dependence): Update prototype.

13586

+

13587

+ 2013-06-16 Joern Rennecke <joern.rennecke@embecosm.com>

13588

+

13589

+ PR rtl-optimization/57425

13590

+ PR rtl-optimization/57569

13591

+ * alias.c (write_dependence_p): Add new parameters mem_mode,

13592

+ canon_mem_addr and mem_canonicalized. Change type of writep to bool.

13593

+ Changed all callers.

13594

+ (canon_anti_dependence): New function.

13595

+ * cse.c (check_dependence): Use canon_anti_dependence.

13596

+ * cselib.c (cselib_invalidate_mem): Likewise.

13597

+ * rtl.h (canon_anti_dependence): Declare.

13598

+

13599

+2014-03-17 Richard Biener <rguenther@suse.de>

13600

+

13601

+ Backport from mainline

13602

+ 2014-03-11 Richard Biener <rguenther@suse.de>

13603

+

13604

+ PR tree-optimization/60429

13605

+ PR tree-optimization/60485

13606

+ * tree-ssa-structalias.c (set_union_with_increment): Properly

13607

+ take into account all fields that overlap the shifted vars.

13608

+ (do_sd_constraint): Likewise.

13609

+ (do_ds_constraint): Likewise.

13610

+ (get_constraint_for_ptr_offset): Likewise.

13611

+

13612

+2014-03-15 Eric Botcazou <ebotcazou@adacore.com>

13613

+

13614

+ * config/sparc/sparc-protos.h (tls_call_delay): Delete.

13615

+ (eligible_for_call_delay): New prototype.

13616

+ * config/sparc/sparc.c (tls_call_delay): Rename into...

13617

+ (eligible_for_call_delay): ...this. Return false if the instruction

13618

+ cannot be put in the delay slot of a branch.

13619

+ (eligible_for_restore_insn): Simplify.

13620

+ (eligible_for_return_delay): Return false if the instruction cannot be

13621

+ put in the delay slot of a branch and simplify.

13622

+ (eligible_for_sibcall_delay): Return false if the instruction cannot be

13623

+ put in the delay slot of a branch.

13624

+ * config/sparc/sparc.md (fix_ut699): New attribute.

13625

+ (tls_call_delay): Delete.

13626

+ (in_call_delay): Reimplement.

13627

+ (eligible_for_sibcall_delay): Rename into...

13628

+ (in_sibcall_delay): ...this.

13629

+ (eligible_for_return_delay): Rename into...

13630

+ (in_return_delay): ...this.

13631

+ (in_branch_delay): Reimplement.

13632

+ (in_uncond_branch_delay): Delete.

13633

+ (in_annul_branch_delay): Delete.

13634

+

13635

+2014-03-14 Georg-Johann Lay <avr@gjlay.de>

13636

+

13637

+ Backport from 2014-03-14 trunk r208562.

13638

+

13639

+ PR target/59396

13640

+ * config/avr/avr.c (avr_set_current_function): Pass function name

13641

+ through default_strip_name_encoding before sanity checking instead

13642

+ of skipping the first char of the assembler name.

13643

+

13644

+2014-03-13 Georg-Johann Lay <avr@gjlay.de>

13645

+

13646

+ Backport from 2014-03-13 trunk r208532.

13647

+

13648

+ PR target/60486

13649

+ * config/avr/avr.c (avr_out_plus): Swap cc_plus and cc_minus in

13650

+ calls of avr_out_plus_1.

13651

+

13652

+2014-03-13 Joey Ye <joey.ye@arm.com>

13653

+

13654

+ Backport from mainline

13655

+ 2014-03-12 Thomas Preud'homme <thomas.preudhomme@arm.com>

13656

+

13657

+ PR tree-optimization/60454

13658

+ * tree-ssa-math-opts.c (find_bswap_1): Fix bswap detection.

13659

+

13660

+2014-03-06 Matthias Klose <doko@ubuntu.com>

13661

+

13662

+ * Makefile.in (s-mlib): Only pass MULTIARCH_DIRNAME if

13663

+ MULTILIB_OSDIRNAMES is not defined.

13664

+

13665

+2014-03-06 Jakub Jelinek <jakub@redhat.com>

13666

+

13667

+ PR tree-optimization/60276

13668

+ * tree-vect-data-refs.c (vect_analyze_data_ref_dependence): Avoid

13669

+ a -Wsign-compare warning.

13670

+

13671

+ * Makefile.in (tree-ssa-uninit.o): Depend on $(PARAMS_H).

13672

+

13673

+ Backport from mainline

13674

+ 2014-02-21 Jakub Jelinek <jakub@redhat.com>

13675

+

13676

+ PR tree-optimization/56490

13677

+ * params.def (PARAM_UNINIT_CONTROL_DEP_ATTEMPTS): New param.

13678

+ * tree-ssa-uninit.c: Include params.h.

13679

+ (compute_control_dep_chain): Add num_calls argument, return false

13680

+ if it exceed PARAM_UNINIT_CONTROL_DEP_ATTEMPTS param, pass

13681

+ num_calls to recursive call.

13682

+ (find_predicates): Change dep_chain into normal array, add num_calls

13683

+ variable and adjust compute_control_dep_chain caller.

13684

+ (find_def_preds): Likewise.

13685

+

13686

+ 2014-02-13 Jakub Jelinek <jakub@redhat.com>

13687

+

13688

+ PR target/43546

13689

+ * expr.c (compress_float_constant): If x is a hard register,

13690

+ extend into a pseudo and then move to x.

13691

+

13692

+ 2014-02-11 Richard Henderson <rth@redhat.com>

13693

+ Jakub Jelinek <jakub@redhat.com>

13694

+

13695

+ PR debug/59776

13696

+ * tree-sra.c (load_assign_lhs_subreplacements): Add VIEW_CONVERT_EXPR

13697

+ around drhs if type conversion to lacc->type is not useless.

13698

+

13699

+ 2014-02-08 Jakub Jelinek <jakub@redhat.com>

13700

+

13701

+ PR ipa/60026

13702

+ * ipa-cp.c (determine_versionability): Fail at -O0

13703

+ or __attribute__((optimize (0))) or -fno-ipa-cp functions.

13704

+ * tree-sra.c (ipa_sra_preliminary_function_checks): Similarly.

13705

+

13706

+ 2014-02-06 Jakub Jelinek <jakub@redhat.com>

13707

+

13708

+ PR target/60062

13709

+ * tree.h (opts_for_fn): New inline function.

13710

+ (opt_for_fn): Define.

13711

+ * config/i386/i386.c (ix86_function_regparm): Use

13712

+ opt_for_fn (decl, optimize) instead of optimize.

13713

+

13714

+ 2014-02-05 Jakub Jelinek <jakub@redhat.com>

13715

+

13716

+ PR middle-end/57499

13717

+ * tree-eh.c (cleanup_empty_eh): Bail out on totally empty

13718

+ bb with no successors.

13719

+

13720

+2014-03-04 Richard Biener <rguenther@suse.de>

13721

+

13722

+ PR tree-optimization/60382

13723

+ * tree-vect-loop.c (vect_is_simple_reduction_1): Do not consider

13724

+ dead PHIs a reduction.

13725

+

13726

+2014-02-25 Richard Biener <rguenther@suse.de>

13727

+

13728

+ Backport from mainline

13729

+ 2014-02-21 Richard Biener <rguenther@suse.de>

13730

+

13731

+ PR tree-optimization/60276

13732

+ * tree-vectorizer.h (struct _stmt_vec_info): Add min_neg_dist field.

13733

+ (STMT_VINFO_MIN_NEG_DIST): New macro.

13734

+ * tree-vect-data-refs.c (vect_analyze_data_ref_dependence): Record

13735

+ STMT_VINFO_MIN_NEG_DIST.

13736

+ * tree-vect-stmts.c (vectorizable_load): Verify if assumptions

13737

+ made for negative dependence distances still hold.

13738

+

13739

+2014-02-25 Richard Biener <rguenther@suse.de>

13740

+

13741

+ Backport from mainline

13742

+ 2014-02-21 Richard Biener <rguenther@suse.de>

13743

+

13744

+ PR middle-end/60291

13745

+ * tree-ssa-live.c (mark_all_vars_used_1): Do not walk

13746

+ DECL_INITIAL for globals not in the current function context.

13747

+

13748

+ 2014-02-20 Richard Biener <rguenther@suse.de>

13749

+

13750

+ PR middle-end/60221

13751

+ * tree-eh.c (execute_cleanup_eh_1): Also cleanup empty EH

13752

+ regions at -O0.

13753

+

13754

+ 2014-02-14 Richard Biener <rguenther@suse.de>

13755

+

13756

+ PR tree-optimization/60183

13757

+ * tree-ssa-phiprop.c (propagate_with_phi): Avoid speculating

13758

+ loads.

13759

+ (tree_ssa_phiprop): Calculate and free post-dominators.

13760

+

13761

+2014-02-25 Kyrylo Tkachov <kyrylo.tkachov@arm.com>

13762

+

13763

+ PR target/55426

13764

+ * config/arm/arm.h (CANNOT_CHANGE_MODE_CLASS): Allow 128 to 64-bit

13765

+ conversions.

13766

+

13767

+2014-02-24 John David Anglin <danglin@gcc.gnu.org>

13768

+

13769

+ * config/pa/pa.c (pa_output_move_double): Don't valididate when

13770

+ adjusting offsetable addresses.

13771

+

13772

+2014-02-23 David Holsgrove <david.holsgrove@xilinx.com>

13773

+

13774

+ * config/microblaze/microblaze.md: Correct ashrsi_reg / lshrsi_reg names

13775

+

13776

+2014-02-23 Edgar E. Iglesias <edgar.iglesias@xilinx.com>

13777

+

13778

+ * config/microblaze/microblaze.h: Remove SECONDARY_MEMORY_NEEDED

13779

+ definition.

13780

+

13781

+2014-02-23 David Holsgrove <david.holsgrove@xilinx.com>

13782

+

13783

+ * /config/microblaze/microblaze.c: Add microblaze_asm_output_mi_thunk

13784

+ and define TARGET_ASM_OUTPUT_MI_THUNK and

13785

+ TARGET_ASM_CAN_OUTPUT_MI_THUNK.

13786

+

13787

+2014-02-23 David Holsgrove <david.holsgrove@xilinx.com>

13788

+

13789

+ * config/microblaze/predicates.md: Add cmp_op predicate.

13790

+ * config/microblaze/microblaze.md: Add branch_compare instruction

13791

+ which uses cmp_op predicate and emits cmp insn before branch.

13792

+ * config/microblaze/microblaze.c (microblaze_emit_compare): Rename

13793

+ to microblaze_expand_conditional_branch and consolidate logic.

13794

+ (microblaze_expand_conditional_branch): emit branch_compare

13795

+ insn instead of handling cmp op separate from branch insn.

13796

+

13797

+2014-02-21 Martin Jambor <mjambor@suse.cz>

13798

+

13799

+ PR ipa/55260

13800

+ * ipa-cp.c (cgraph_edge_brings_all_agg_vals_for_node): Uce correct

13801

+ info when checking whether lattices are bottom.

13802

+

13803

+2014-02-21 Jakub Jelinek <jakub@redhat.com>

13804

+

13805

+ * config/i386/i386.c (ix86_expand_vec_perm): Use V8SImode

13806

+ mode for mask of V8SFmode permutation.

13807

+

13808

+2014-02-20 Richard Henderson <rth@redhat.com>

13809

+

13810

+ PR c++/60272

13811

+ * builtins.c (expand_builtin_atomic_compare_exchange): Conditionalize

13812

+ on failure the store back into EXPECT. Always make a new pseudo for

13813

+ OLDVAL.

13814

+

13815

+2014-02-20 Jakub Jelinek <jakub@redhat.com>

13816

+

13817

+ PR target/57896

13818

+ * config/i386/i386.c (expand_vec_perm_interleave2): Don't call

13819

+ gen_reg_rtx if d->testing_p.

13820

+ (expand_vec_perm_pshufb2, expand_vec_perm_even_odd_1,

13821

+ expand_vec_perm_broadcast_1): Return early if d->testing_p and

13822

+ we will certainly return true.

13823

+

13824

+2014-02-20 Richard Biener <rguenther@suse.de>

13825

+

13826

+ * tree-cfg.c (replace_uses_by): Mark altered BBs before

13827

+ doing the substitution.

13828

+

13829

+2014-02-19 H.J. Lu <hongjiu.lu@intel.com>

13830

+

13831

+ Backport from mainline

13832

+ 2014-02-19 H.J. Lu <hongjiu.lu@intel.com>

13833

+

13834

+ PR target/60207

13835

+ * config/i386/i386.c (construct_container): Remove TFmode check

13836

+ for X86_64_INTEGER_CLASS.

13837

+

13838

+2014-02-19 Uros Bizjak <ubizjak@gmail.com>

13839

+

13840

+ Backport from mainline

13841

+ 2014-02-19 Uros Bizjak <ubizjak@gmail.com>

13842

+

13843

+ PR target/59794

13844

+ * config/i386/i386.c (type_natural_mode): Warn for ABI changes

13845

+ only when -Wpsabi is enabled.

13846

+

13847

+2014-02-19 Terry Guo <terry.guo@arm.com>

13848

+

13849

+ Backport from mainline

13850

+ 2014-02-08 Terry Guo <terry.guo@arm.com>

13851

+

13852

+ * doc/invoke.texi: Document ARM -march=armv7e-m.

13853

+

13854

+2014-02-18 Kai Tietz <ktietz@redhat.com>

13855

+

13856

+ Backport from mainline

13857

+ 2014-02-18 Kai Tietz <ktietz@redhat.com>

13858

+

13859

+ PR target/60193

13860

+ * config/i386/i386.c (ix86_expand_prologue): Use

13861

+ rax register as displacement for restoring %r10, %rax.

13862

+ Additional fix wrong offset for restoring both-registers.

13863

+

13864

+2014-02-18 Eric Botcazou <ebotcazou@adacore.com>

13865

+

13866

+ * ipa-prop.c (compute_complex_ancestor_jump_func): Replace overzealous

13867

+ assertion with conditional return.

13868

+

13869

+2014-02-18 Jakub Jelinek <jakub@redhat.com>

13870

+ Uros Bizjak <ubizjak@gmail.com>

13871

+

13872

+ PR driver/60233

13873

+ * config/i386/driver-i386.c (host_detect_local_cpu): If

13874

+ YMM state is not saved by the OS, also clear has_f16c. Move

13875

+ CPUID 0x80000001 handling before YMM state saving checking.

13876

+

13877

+2014-02-14 Roland McGrath <mcgrathr@google.com>

13878

+

13879

+ * configure.ac (HAVE_AS_IX86_UD2): New test for 'ud2' mnemonic.

13880

+ * configure: Regenerated.

13881

+ * config.in: Regenerated.

13882

+ * config/i386/i386.md (trap) [HAVE_AS_IX86_UD2]: Use the mnemonic

13883

+ instead of ASM_SHORT.

13884

+

13885

+2014-02-13 Uros Bizjak <ubizjak@gmail.com>

13886

+

13887

+ Backport from mainline

13888

+ 2014-02-13 Uros Bizjak <ubizjak@gmail.com>

13889

+

13890

+ * config/i386/sse.md (xop_vmfrcz<mode>2): Generate const0 in

13891

+ operands[2], not operands[3].

13892

+

13893

+2014-02-13 Dominik Vogt <vogt@linux.vnet.ibm.com>

13894

+

13895

+ * config/s390/s390.c (s390_asm_output_function_label): Fix crash

13896

+ caused by bad second argument to warning_at() with -mhotpatch and

13897

+ nested functions (e.g. with gfortran).

13898

+

13899

+2014-02-12 H.J. Lu <hongjiu.lu@intel.com>

13900

+

13901

+ Backport from mainline

13902

+ 2014-02-12 H.J. Lu <hongjiu.lu@intel.com>

13903

+ Uros Bizjak <ubizjak@gmail.com>

13904

+

13905

+ PR target/60151

13906

+ * configure.ac (HAVE_AS_GOTOFF_IN_DATA): Pass --32 to GNU assembler.

13907

+

13908

+2014-02-12 Eric Botcazou <ebotcazou@adacore.com>

13909

+

13910

+ PR rtl-optimization/60116

13911

+ * combine.c (try_combine): Also remove dangling REG_DEAD notes on the

13912

+ other_insn once the combination has been validated.

13913

+

13914

+2014-02-10 Nagaraju Mekala <nagaraju.mekala@xilinx.com>

13915

+

13916

+ * config/microblaze/microblaze.md: Add movsi4_rev insn pattern.

13917

+ * config/microblaze/predicates.md: Add reg_or_mem_operand predicate.

13918

+

13919

+2014-02-10 Nagaraju Mekala <nagaraju.mekala@xilinx.com>

13920

+

13921

+ * config/microblaze/microblaze.c: Extend mcpu version format

13922

+

13923

+2014-02-10 David Holsgrove <david.holsgrove@xilinx.com>

13924

+

13925

+ * config/microblaze/microblaze.h: Define SIZE_TYPE and PTRDIFF_TYPE.

13926

+

13927

+2014-02-10 Richard Biener <rguenther@suse.de>

13928

+

13929

+ Backport from mainline

13930

+ 2014-01-30 Richard Biener <rguenther@suse.de>

13931

+

13932

+ PR tree-optimization/59903

13933

+ * tree-vect-loop.c (vect_transform_loop): Guard multiple-types

13934

+ check properly.

13935

+

13936

+ 2014-02-10 Richard Biener <rguenther@suse.de>

13937

+

13938

+ PR tree-optimization/60115

13939

+ * tree-eh.c (tree_could_trap_p): Unify TARGET_MEM_REF and

13940

+ MEM_REF handling. Properly verify that the accesses are not

13941

+ out of the objects bound.

13942

+

13943

+2014-02-05 James Greenhalgh <james.greenhalgh@arm.com>

13944

+

13945

+ Backport from mainline.

13946

+ 2014-02-05 James Greenhalgh <james.greenhalgh@arm.com>

13947

+

13948

+ PR target/59718

13949

+ * doc/invoke.texi (-march): Clarify documentation for ARM.

13950

+ (-mtune): Likewise.

13951

+ (-mcpu): Likewise.

13952

+

13953

+2014-02-04 John David Anglin <danglin@gcc.gnu.org>

13954

+

13955

+ PR target/59777

13956

+ * config/pa/pa.c (legitimize_tls_address): Return original address

13957

+ if not passed a SYMBOL_REF rtx.

13958

+ (hppa_legitimize_address): Call legitimize_tls_address for all TLS

13959

+ addresses.

13960

+ (pa_emit_move_sequence): Simplify TLS source operands.

13961

+ (pa_legitimate_constant_p): Reject all TLS constants.

13962

+ * config/pa/pa.h (PA_SYMBOL_REF_TLS_P): Correct comment.

13963

+ (CONSTANT_ADDRESS_P): Reject TLS CONST addresses.

13964

+

13965

+2014-02-04 Uros Bizjak <ubizjak@gmail.com>

13966

+

13967

+ Backport from mainline

13968

+ 2014-02-02 Uros Bizjak <ubizjak@gmail.com>

13969

+

13970

+ PR target/60017

13971

+ * config/i386/i386.c (classify_argument): Fix handling of bit_offset

13972

+ when calculating size of integer atomic types.

13973

+

13974

+2014-02-02 Uros Bizjak <ubizjak@gmail.com>

13975

+

13976

+ Backport from mainline

13977

+ 2014-01-30 Jakub Jelinek <jakub@redhat.com>

13978

+

13979

+ * config/i386/f16cintrin.h (_cvtsh_ss): Avoid -Wnarrowing warning.

13980

+

13981

+2014-01-31 Richard Henderson <rth@redhat.com>

13982

+

13983

+ PR middle-end/60004

13984

+ * tree-eh.c (lower_try_finally_switch): Delay lowering finally block

13985

+ until after else_eh is processed.

13986

+

13987

+2014-01-30 David Holsgrove <david.holsgrove@xilinx.com>

13988

+

13989

+ Backport from mainline

13990

+ * config/microblaze/microblaze.md(cstoresf4, cbranchsf4): Replace

13991

+ comparison_operator with ordered_comparison_operator.

13992

+

13993

+2014-01-25 Walter Lee <walt@tilera.com>

13994

+

13995

+ Backport from mainline

13996

+ 2014-01-25 Walter Lee <walt@tilera.com>

13997

+

13998

+ * config/tilegx/sync.md (atomic_fetch_sub): Fix negation and

13999

+ avoid clobbering a live register.

14000

+

14001

+2014-01-25 Walter Lee <walt@tilera.com>

14002

+

14003

+ Backport from mainline

14004

+ 2014-01-25 Walter Lee <walt@tilera.com>

14005

+

14006

+ * config/tilegx/tilegx-c.c (tilegx_cpu_cpp_builtins):

14007

+ Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_{1,2}.

14008

+ * config/tilegx/tilepro-c.c (tilepro_cpu_cpp_builtins):

14009

+ Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_{1,2,4,8}.

14010

+

14011

+2014-01-25 Walter Lee <walt@tilera.com>

14012

+

14013

+ Backport from mainline

14014

+ 2014-01-25 Walter Lee <walt@tilera.com>

14015

+

14016

+ * config/tilegx/tilegx.c (tilegx_gen_bundles): Delete barrier

14017

+ insns before bundling.

14018

+ * config/tilegx/tilegx.md (tile_network_barrier): Update comment.

14019

+

14020

+2014-01-25 Walter Lee <walt@tilera.com>

14021

+

14022

+ Backport from mainline

14023

+ 2014-01-25 Walter Lee <walt@tilera.com>

14024

+

14025

+ * config/tilegx/tilegx.c (tilegx_expand_builtin): Set

14026

+ PREFETCH_SCHEDULE_BARRIER_P to true for prefetches.

14027

+ * config/tilepro/tilepro.c (tilepro_expand_builtin): Ditto.

14028

+

14029

+2014-01-25 Walter Lee <walt@tilera.com>

14030

+

14031

+ Backport from mainline

14032

+ 2014-01-25 Walter Lee <walt@tilera.com>

14033

+

14034

+ * config/tilepro/tilepro.md (ctzdi2): Use register_operand

14035

+ predicate.

14036

+ (clzdi2): Ditto.

14037

+ (ffsdi2): Ditto.

14038

+

14039

+2014-01-25 Walter Lee <walt@tilera.com>

14040

+

14041

+ Backport from mainline

14042

+ 2014-01-25 Walter Lee <walt@tilera.com>

14043

+

14044

+ * config/tilegx/tilegx.c (tilegx_expand_to_rtl_hook): New.

14045

+ (TARGET_EXPAND_TO_RTL_HOOK): Define.

14046

+

14047

+2014-01-24 H.J. Lu <hongjiu.lu@intel.com>

14048

+

14049

+ Backport from mainline

14050

+ 2014-01-23 H.J. Lu <hongjiu.lu@intel.com>

14051

+

14052

+ PR target/59929

14053

+ * config/i386/i386.md (pushsf splitter): Get stack adjustment

14054

+ from push operand if code of push isn't PRE_DEC.

14055

+

14056

+2014-01-23 David Holsgrove <david.holsgrove@xilinx.com>

14057

+

14058

+ Backport from mainline.

14059

+ * config/microblaze/microblaze.md: Add trap insn and attribute

14060

+

14061

+2014-01-23 Marek Polacek <polacek@redhat.com>

14062

+

14063

+ Backport from mainline

14064

+ 2013-10-21 Marek Polacek <polacek@redhat.com>

14065

+

14066

+ PR middle-end/58809

14067

+ * fold-const.c (fold_range_test): Return 0 if the type is not

14068

+ an integral type.

14069

+

14070

+2014-01-22 David Holsgrove <david.holsgrove@xilinx.com>

14071

+

14072

+ * config/microblaze/microblaze.md: Correct bswaphi2 insn.

14073

+

14074

+2014-01-22 Uros Bizjak <ubizjak@gmail.com>

14075

+

14076

+ Backport from mainline

14077

+ 2014-01-20 Uros Bizjak <ubizjak@gmail.com>

14078

+

14079

+ * config/i386/i386.c (ix86_avoid_lea_for_addr): Return false

14080

+ for SImode_address_operand operands, having only a REG argument.

14081

+

14082

+ 2014-01-20 Jakub Jelinek <jakub@redhat.com>

14083

+

14084

+ PR target/59880

14085

+ * config/i386/i386.c (ix86_avoid_lea_for_addr): Return false

14086

+ if operands[1] is a REG or ZERO_EXTEND of a REG.

14087

+

14088

+ 2014-01-18 Uros Bizjak <ubizjak@gmail.com>

14089

+ H.J. Lu <hongjiu.lu@intel.com>

14090

+

14091

+ PR target/59379

14092

+ * config/i386/i386.md (*lea<mode>): Zero-extend return register

14093

+ to DImode for zero-extended addresses.

14094

+

14095

+2014-01-21 Andrew Pinski <apinski@cavium.com>

14096

+ Steve Ellcey <sellcey@mips.com>

14097

+

14098

+ PR target/59462

14099

+ * config/mips/mips.c (mips_print_operand): Check operand mode instead

14100

+ of operator mode.

14101

+

14102

+2014-01-21 Andrey Belevantsev <abel@ispras.ru>

14103

+

14104

+ Backport from mainline

14105

+ 2013-12-23 Andrey Belevantsev <abel@ispras.ru>

14106

+

14107

+ PR rtl-optimization/57422

14108

+ * sel-sched.c (mark_unavailable_hard_regs): Fix typo when calling

14109

+ add_to_hard_reg_set.

14110

+

14111

+2014-01-20 Jakub Jelinek <jakub@redhat.com>

14112

+

14113

+ PR middle-end/59860

14114

+ * tree.h (fold_builtin_strcat): New prototype.

14115

+ * builtins.c (fold_builtin_strcat): No longer static. Add len

14116

+ argument, if non-NULL, don't call c_strlen. Optimize

14117

+ directly into __builtin_memcpy instead of __builtin_strcpy.

14118

+ (fold_builtin_2): Adjust fold_builtin_strcat caller.

14119

+ * gimple-fold.c (gimple_fold_builtin): Handle BUILT_IN_STRCAT.

14120

+

14121

+2014-01-20 Richard Biener <rguenther@suse.de>

14122

+

14123

+ PR middle-end/59860

14124

+ * builtins.c (fold_builtin_strcat): Remove case better handled

14125

+ by tree-ssa-strlen.c.

14126

+

14127

+2014-01-19 John David Anglin <danglin@gcc.gnu.org>

14128

+

14129

+ * config/pa/pa.c (pa_attr_length_millicode_call): Correct length of

14130

+ long non-pic millicode calls.

14131

+

14132

+2014-01-17 John David Anglin <danglin@gcc.gnu.org>

14133

+

14134

+ * config/pa/pa.c (pa_attr_length_indirect_call): Don't output a short

14135

+ call to $$dyncall when TARGET_LONG_CALLS is true.

14136

+

14137

+2014-01-17 H.J. Lu <hongjiu.lu@intel.com>

14138

+

14139

+ Backport from mainline

14140

+ 2014-01-14 H.J. Lu <hongjiu.lu@intel.com>

14141

+

14142

+ PR target/59794

14143

+ * config/i386/i386.c (type_natural_mode): Add a bool parameter

14144

+ to indicate if type is used for function return value. Warn

14145

+ ABI change if the vector mode isn't available for function

14146

+ return value.

14147

+ (ix86_function_arg_advance): Pass false to type_natural_mode.

14148

+ (ix86_function_arg): Likewise.

14149

+ (ix86_gimplify_va_arg): Likewise.

14150

+ (function_arg_32): Don't warn ABI change.

14151

+ (ix86_function_value): Pass true to type_natural_mode.

14152

+ (ix86_return_in_memory): Likewise.

14153

+ (ix86_struct_value_rtx): Removed.

14154

+ (TARGET_STRUCT_VALUE_RTX): Likewise.

14155

+

14156

+2014-01-17 Charles Baylis <charles.baylis@linaro.org>

14157

+

14158

+ Backport from mainline

14159

+ 2013-12-19 Charles Baylis <charles.baylis@linaro.org>

14160

+

14161

+ PR target/59142

14162

+ * config/arm/arm-ldmstm.ml: Use low_register_operand for Thumb

14163

+ patterns.

14164

+ * config/arm/ldmstm.md: Regenerate.

14165

+

14166

+ 2013-12-19 Charles Baylis <charles.baylis@linaro.org>

14167

+

14168

+ PR target/59142

14169

+ * config/arm/predicates.md (arm_hard_general_register_operand):

14170

+ New predicate.

14171

+ (arm_hard_register_operand): Remove.

14172

+ * config/arm/arm-ldmstm.ml: Use arm_hard_general_register_operand

14173

+ for all patterns.

14174

+ * config/arm/ldmstm.md: Regenerate.

14175

+

14176

+ 2013-12-19 Charles Baylis <charles.baylis@linaro.org>

14177

+

14178

+ PR target/59142

14179

+ * config/arm/predicates.md (vfp_hard_register_operand): New predicate.

14180

+ * config/arm/arm.md (vfp_pop_multiple_with_writeback): Use

14181

+ vfp_hard_register_operand.

14182

+

14183

+2014-01-17 Kugan Vivekanandarajah <kuganv@linaro.org>

14184

+

14185

+ Backport from mainline

14186

+ 2014-01-15 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org>

14187

+ Kugan Vivekanandarajah <kuganv@linaro.org>

14188

+

14189

+ PR target/59695

14190

+ * config/aarch64/aarch64.c (aarch64_build_constant): Fix incorrect

14191

+ truncation.

14192

+

14193

+2014-01-17 Terry Guo <terry.guo@arm.com>

14194

+

14195

+ PR target/59826

14196

+ * config/arm/arm.md (prefetch): Set insn type attribute to load1.

14197

+

14198

+2014-01-16 Jakub Jelinek <jakub@redhat.com>

14199

+

14200

+ PR target/59839

14201

+ * config/i386/i386.c (ix86_expand_builtin): If target doesn't

14202

+ satisfy operand 0 predicate for gathers, use a new pseudo as

14203

+ subtarget.

14204

+

14205

+2014-01-16 Richard Henderson <rth@redhat.com>

14206

+

14207

+ PR debug/54694

14208

+ * reginfo.c (global_regs_decl): Globalize.

14209

+ * rtl.h (global_regs_decl): Declare.

14210

+ * ira.c (do_reload): Diagnose frame_pointer_needed and it

14211

+ reserved via global_regs.

14212

+

14213

+2014-01-16 Peter Bergner <bergner@vnet.ibm.com>

14214

+

14215

+ Backport from mainline

14216

+ 2014-01-15 Uros Bizjak <ubizjak@gmail.com>

14217

+

14218

+ * config/i386/i386.c (ix86_hard_regno_mode_ok): Use

14219

+ VALID_AVX256_REG_OR_OI_MODE.

14220

+

14221

+ 2013-09-05 Peter Bergner <bergner@vnet.ibm.com>

14222

+

14223

+ PR target/58139

14224

+ * reginfo.c (choose_hard_reg_mode): Scan through all mode classes

14225

+ looking for widest mode.

14226

+

14227

+2014-01-16 Marek Polacek <polacek@redhat.com>

14228

+

14229

+ Backported from mainline

14230

+ 2014-01-16 Marek Polacek <polacek@redhat.com>

14231

+

14232

+ PR middle-end/59827

14233

+ * gimple-low.c (gimple_check_call_args): Don't use DECL_ARG_TYPE if

14234

+ it is error_mark_node.

14235

+

14236

+2014-01-15 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>

14237

+

14238

+ PR target/59803

14239

+ * config/s390/s390.c (s390_preferred_reload_class): Don't return

14240

+ ADDR_REGS for invalid symrefs in non-PIC code.

14241

+

14242

+2014-01-14 Uros Bizjak <ubizjak@gmail.com>

14243

+

14244

+ Revert:

14245

+ 2014-01-08 Uros Bizjak <ubizjak@gmail.com>

14246

+

14247

+ * config/i386/i386.c (ix86_data_alignment): Calculate max_align

14248

+ from prefetch_block tune setting.

14249

+

14250

+2014-01-13 Jakub Jelinek <jakub@redhat.com>

14251

+

14252

+ Backported from mainline

14253

+ 2014-01-10 Jakub Jelinek <jakub@redhat.com>

14254

+

14255

+ PR tree-optimization/59745

14256

+ * tree-predcom.c (tree_predictive_commoning_loop): Call

14257

+ free_affine_expand_cache if giving up because components is NULL.

14258

+

14259

+2014-01-10 Yufeng Zhang <yufeng.zhang@arm.com>

14260

+

14261

+ * config/arm/arm.c (arm_expand_neon_args): Call expand_expr

14262

+ with EXPAND_MEMORY for NEON_ARG_MEMORY; check if the returned

14263

+ rtx is const0_rtx or not.

14264

+

14265

+2014-01-10 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>

14266

+

14267

+ * config/s390/s390.c (s390_expand_tbegin): Remove jump over CC

14268

+ extraction in good case.

14269

+

14270

+2014-01-10 Huacai Chen <chenhc@lemote.com>

14271

+

14272

+ * config/mips/driver-native.c (host_detect_local_cpu): Handle new

14273

+ kernel strings for Loongson-2E/2F/3A.

14274

+

14275

+2014-01-10 Richard Biener <rguenther@suse.de>

14276

+

14277

+ PR tree-optimization/59715

14278

+ * tree-flow.h (split_critical_edges): Declare.

14279

+ * tree-cfg.c (split_critical_edges): Export.

14280

+ * tree-ssa-sink.c (execute_sink_code): Split critical edges.

14281

+

14282

+2014-01-09 Richard Sandiford <rdsandiford@googlemail.com>

14283

+

14284

+ * config/mips/mips.h (ISA_HAS_WSBH): Define.

14285

+ * config/mips/mips.md (UNSPEC_WSBH, UNSPEC_DSBH, UNSPEC_DSHD): New

14286

+ constants.

14287

+ (bswaphi2, bswapsi2, bswapdi2, wsbh, dsbh, dshd): New patterns.

14288

+

14289

+2014-01-09 Richard Sandiford <rdsandiford@googlemail.com>

14290

+

14291

+ PR rtl-optimization/59137

14292

+ * reorg.c (steal_delay_list_from_target): Call update_block for

14293

+ elided insns.

14294

+ (steal_delay_list_from_fallthrough, relax_delay_slots): Likewise.

14295

+

14296

+2014-01-09 Richard Sandiford <rdsandiford@googlemail.com>

14297

+

14298

+ Revert:

14299

+ 2012-10-07 Richard Sandiford <rdsandiford@googlemail.com>

14300

+

14301

+ * config/mips/mips.c (mips_truncated_op_cost): New function.

14302

+ (mips_rtx_costs): Adjust test for BADDU.

14303

+ * config/mips/mips.md (*baddu_di<mode>): Push truncates to operands.

14304

+

14305

+ 2012-10-02 Richard Sandiford <rdsandiford@googlemail.com>

14306

+

14307

+ * config/mips/mips.md (*baddu_si_eb, *baddu_si_el): Merge into...

14308

+ (*baddu_si): ...this new pattern.

14309

+

14310

+2014-01-09 Richard Biener <rguenther@suse.de>

14311

+

14312

+ Backport from mainline

14313

+ 2013-11-18 Richard Biener <rguenther@suse.de>

14314

+

14315

+ PR tree-optimization/59125

14316

+ PR tree-optimization/54570

14317

+ * tree-ssa-sccvn.c (copy_reference_ops_from_ref): When inlining

14318

+ is not complete do not treat component-references with offset zero

14319

+ but different fields as equal.

14320

+ * tree-object-size.c: Include tree-phinodes.h and ssa-iterators.h.

14321

+ (compute_object_sizes): Apply TLC. Propagate the constant

14322

+ results into all uses and fold their stmts.

14323

+ * passes.def (pass_all_optimizations): Move pass_object_sizes

14324

+ after the first pass_forwprop and before pass_fre.

14325

+

14326

+ 2013-12-03 Jakub Jelinek <jakub@redhat.com>

14327

+

14328

+ PR tree-optimization/59362

14329

+ * tree-object-size.c (object_sizes): Change into array of

14330

+ vec<unsigned HOST_WIDE_INT>.

14331

+ (compute_builtin_object_size): Check computed bitmap for

14332

+ non-NULL instead of object_sizes. Call safe_grow on object_sizes

14333

+ vector if new SSA_NAMEs appeared.

14334

+ (init_object_sizes): Check computed bitmap for non-NULL.

14335

+ Call safe_grow on object_sizes elements instead of initializing

14336

+ it with XNEWVEC.

14337

+ (fini_object_sizes): Call release on object_sizes elements, don't

14338

+ set it to NULL.

14339

+

14340

+2014-01-09 Richard Earnshaw <rearnsha@arm.com>

14341

+

14342

+ PR rtl-optimization/54300

14343

+ * regcprop.c (copyprop_hardreg_forward_1): Ensure any unused

14344

+ outputs in a single-set are killed from the value chains.

14345

+

14346

+2014-01-09 Jakub Jelinek <jakub@redhat.com>

14347

+

14348

+ PR rtl-optimization/59724

14349

+ * ifcvt.c (cond_exec_process_if_block): Don't call

14350

+ flow_find_head_matching_sequence with 0 longest_match.

14351

+ * cfgcleanup.c (flow_find_head_matching_sequence): Count even

14352

+ non-active insns if !stop_after.

14353

+ (try_head_merge_bb): Revert 2014-01-07 changes.

14354

+

14355

+2014-01-09 Hans-Peter Nilsson <hp@axis.com>

14356

+

14357

+ Backport from mainline

14358

+ 2013-12-23 Hans-Peter Nilsson <hp@axis.com>

14359

+

14360

+ PR middle-end/59584

14361

+ * config/cris/predicates.md (cris_nonsp_register_operand):

14362

+ New define_predicate.

14363

+ * config/cris/cris.md: Replace register_operand with

14364

+ cris_nonsp_register_operand for destinations in all

14365

+ define_splits where a register is set more than once.

14366

+

14367

+2014-01-08 H.J. Lu <hongjiu.lu@intel.com>

14368

+

14369

+ Backport from mainline

14370

+ 2013-12-25 H.J. Lu <hongjiu.lu@intel.com>

14371

+

14372

+ PR target/59587

14373

+ * config/i386/i386.c (struct ptt): Add a field for processor name.

14374

+ (processor_target_table): Sync with processor_type. Add

14375

+ processor names.

14376

+ (cpu_names): Removed.

14377

+ (ix86_option_override_internal): Default x_ix86_tune_string

14378

+ to processor_target_table[TARGET_CPU_DEFAULT].name.

14379

+ (ix86_function_specific_print): Assert arch and tune <

14380

+ PROCESSOR_max. Use processor_target_table to print arch and

14381

+ tune names.

14382

+ * config/i386/i386.h (TARGET_CPU_DEFAULT): Default to

14383

+ PROCESSOR_GENERIC32.

14384

+ (target_cpu_default): Removed.

14385

+ (processor_type): Reordered.

14386

+

14387

+2014-01-08 Uros Bizjak <ubizjak@gmail.com>

14388

+

14389

+ Backport from mainline

14390

+ 2014-01-05 Uros Bizjak <ubizjak@gmail.com>

14391

+

14392

+ * config/i386/i386.c (ix86_data_alignment): Calculate max_align

14393

+ from prefetch_block tune setting.

14394

+ (nocona_cost): Correct size of prefetch block to 64.

14395

+

14396

+2014-01-08 Martin Jambor <mjambor@suse.cz>

14397

+

14398

+ PR ipa/59610

14399

+ * ipa-prop.c (ipa_compute_jump_functions): Bail out if not optimizing.

14400

+ (parm_preserved_before_stmt_p): Assume modification present when not

14401

+ optimizing.

14402

+

14403

+2014-01-07 John David Anglin <danglin@gcc.gnu.org>

14404

+

14405

+ PR target/59652

14406

+ * config/pa/pa.c (pa_legitimate_address_p): Return false before reload

14407

+ for 14-bit register offsets when INT14_OK_STRICT is false.

14408

+

14409

+2014-01-07 Roland Stigge <stigge@antcom.de>

14410

+ Michael Meissner <meissner@linux.vnet.ibm.com>

14411

+

14412

+ PR 57386/target

14413

+ * config/rs6000/rs6000.c (rs6000_legitimate_offset_address_p):

14414

+ Only check TFmode for SPE constants. Don't check TImode or TDmode.

14415

+

14416

+2014-01-07 Jakub Jelinek <jakub@redhat.com>

14417

+

14418

+ PR rtl-optimization/58668

14419

+ * cfgcleanup.c (flow_find_cross_jump): Don't count

14420

+ any jumps if dir_p is NULL. Remove p1 variable and make USE/CLOBBER

14421

+ check consistent with other places.

14422

+ (flow_find_head_matching_sequence): Don't count USE or CLOBBER insns.

14423

+ (try_head_merge_bb): Adjust for the flow_find_head_matching_sequence

14424

+ counting change.

14425

+ * ifcvt.c (count_bb_insns): Don't count USE or CLOBBER insns.

14426

+

14427

+2014-01-07 Mike Stump <mikestump@comcast.net>

14428

+ Jakub Jelinek <jakub@redhat.com>

14429

+

14430

+ PR pch/59436

14431

+ * tree.h (struct tree_optimization_option): Change optabs

14432

+ type from unsigned char * to void *.

14433

+ * optabs.c (init_tree_optimization_optabs): Adjust

14434

+ TREE_OPTIMIZATION_OPTABS initialization.

14435

+

14436

+2014-01-07 Jakub Jelinek <jakub@redhat.com>

14437

+

14438

+ Backported from mainline

14439

+ 2013-12-16 Jakub Jelinek <jakub@redhat.com>

14440

+

14441

+ PR middle-end/58956

14442

+ PR middle-end/59470

14443

+ * gimple.h (walk_stmt_load_store_addr_fn): New typedef.

14444

+ (walk_stmt_load_store_addr_ops, walk_stmt_load_store_ops): Use it

14445

+ for callback params.

14446

+ * gimple.c (walk_stmt_load_store_ops): Likewise.

14447

+ (walk_stmt_load_store_addr_ops): Likewise. Adjust all callback

14448

+ calls to supply the gimple operand containing the base tree

14449

+ as an extra argument.

14450

+ * tree-ssa-ter.c (find_ssaname, find_ssaname_in_store): New helper

14451

+ functions.

14452

+ (find_replaceable_in_bb): For calls or GIMPLE_ASM, only set

14453

+ same_root_var if USE is used somewhere in the stores of the stmt.

14454

+ * ipa-prop.c (visit_ref_for_mod_analysis): Remove name of the stmt

14455

+ argument and ATTRIBUTE_UNUSED, add another unnamed tree argument.

14456

+ * ipa-pure-const.c (check_load, check_store, check_ipa_load,

14457

+ check_ipa_store): Likewise.

14458

+ * gimple.c (gimple_ior_addresses_taken_1): Likewise.

14459

+ * ipa-split.c (test_nonssa_use, mark_nonssa_use): Likewise.

14460

+ (verify_non_ssa_vars, visit_bb): Adjust their callers.

14461

+ * cfgexpand.c (add_scope_conflicts_1): Use

14462

+ walk_stmt_load_store_addr_fn type for visit variable.

14463

+ (visit_op, visit_conflict): Remove name of the stmt

14464

+ argument and ATTRIBUTE_UNUSED, add another unnamed tree argument.

14465

+ * tree-sra.c (asm_visit_addr): Likewise. Remove name of the data

14466

+ argument and ATTRIBUTE_UNUSED.

14467

+ * cgraphbuild.c (mark_address, mark_load, mark_store): Add another

14468

+ unnamed tree argument.

14469

+

14470

+2014-01-03 Andreas Schwab <schwab@linux-m68k.org>

14471

+

14472

+ * config/m68k/m68k.c (handle_move_double): Handle pushes with

14473

+ overlapping registers also for registers other than the stack

14474

+ pointer.

14475

+

14476

+2014-01-03 Jakub Jelinek <jakub@redhat.com>

14477

+

14478

+ PR target/59625

14479

+ * config/i386/i386.c (ix86_avoid_jump_mispredicts): Don't consider

14480

+ asm goto as jump.

14481

+

14482

+2014-01-01 Jakub Jelinek <jakub@redhat.com>

14483

+

14484

+ PR rtl-optimization/59647

14485

+ * cse.c (cse_process_notes_1): Don't substitute negative VOIDmode

14486

+ new_rtx into UNSIGNED_FLOAT rtxes.

14487

+

14488

+2013-12-28 Eric Botcazou <ebotcazou@adacore.com>

14489

+

14490

+ * doc/invoke.texi (output file options): Document -fada-spec-parent.

14491

+

14492

+2013-12-26 Uros Bizjak <ubizjak@gmail.com>

14493

+

14494

+ * config/i386/driver-i386.c (decode_caches_intel): Add missing entries.

14495

+

14496

+2013-12-20 Jakub Jelinek <jakub@redhat.com>

14497

+

14498

+ PR c++/59255

14499

+ Backported from mainline

14500

+ 2013-08-19 Dehao Chen <dehao@google.com>

14501

+

14502

+ * value-prof.c (gimple_ic): Fix the bug of adding EH edge.

14503

+

14504

+2013-12-19 James Greenhalgh <james.greenhalgh@arm.com>

14505

+

14506

+ Backport from Mainline.

14507

+ 2013-05-01 James Greenhalgh <james.greenhalgh@arm.com>

14508

+

14509

+ * config/aarch64/aarch64-simd-builtins.def (cmhs): Rename to...

14510

+ (cmgeu): ...This.

14511

+ (cmhi): Rename to...

14512

+ (cmgtu): ...This.

14513

+ * config/aarch64/aarch64-simd.md

14514

+ (simd_mode): Add SF.

14515

+ (aarch64_vcond_internal): Use new names for unsigned comparison insns.

14516

+ (aarch64_cm<optab><mode>): Rewrite to not use UNSPECs.

14517

+ * config/aarch64/aarch64.md (*cstore<mode>_neg): Rename to...

14518

+ (cstore<mode>_neg): ...This.

14519

+ * config/aarch64/iterators.md

14520

+ (VALLF): new.

14521

+ (unspec): Remove UNSPEC_CM<EQ, LE, LT, GE, GT, HS, HI, TST>.

14522

+ (COMPARISONS): New.

14523

+ (UCOMPARISONS): Likewise.

14524

+ (optab): Add missing comparisons.

14525

+ (n_optab): New.

14526

+ (cmp_1): Likewise.

14527

+ (cmp_2): Likewise.

14528

+ (CMP): Likewise.

14529

+ (cmp): Remove.

14530

+ (VCMP_S): Likewise.

14531

+ (VCMP_U): Likewise.

14532

+ (V_cmp_result): Add DF, SF modes.

14533

+ (v_cmp_result): Likewise.

14534

+ (v): Likewise.

14535

+ (vmtype): Likewise.

14536

+ * config/aarch64/predicates.md (aarch64_reg_or_fp_zero): New.

14537

+

14538

+ Partial Backport from mainline.

14539

+ 2013-05-01 James Greenhalgh <james.greenhalgh@arm.com>

14540

+

14541

+ * config/aarch64/arm_neon.h

14542

+ (vc<eq, lt, le, gt, ge, tst><qsd>_<u><8,16,32,64>): Remap

14543

+ to builtins or C as appropriate.

14544

+

14545

+2013-12-19 Dominik Vogt <vogt@linux.vnet.ibm.com>

14546

+ Andreas Krebbel <Andreas.Krebbel@de.ibm.com>

14547

+

14548

+ Backport from mainline

14549

+ 2013-12-19 Dominik Vogt <vogt@linux.vnet.ibm.com>

14550

+ * config/s390/s390.c (s390_hotpatch_trampoline_halfwords_default): New

14551

+ constant

14552

+ (s390_hotpatch_trampoline_halfwords_max): New constant

14553

+ (s390_hotpatch_trampoline_halfwords): New static variable

14554

+ (get_hotpatch_attribute): New function

14555

+ (s390_handle_hotpatch_attribute): New function

14556

+ (s390_attribute_table): New target specific attribute table to implement

14557

+ the hotpatch attribute

14558

+ (s390_option_override): Parse hotpatch options

14559

+ (s390_function_num_hotpatch_trampoline_halfwords): New function

14560

+ (s390_can_inline_p): Implement target hook to

14561

+ suppress hotpatching for explicitly inlined functions

14562

+ (s390_asm_output_function_label): Generate hotpatch prologue

14563

+ (TARGET_ATTRIBUTE_TABLE): Define to implement target attribute table

14564

+ (TARGET_CAN_INLINE_P): Define to implement target hook

14565

+ * config/s390/s390.opt (mhotpatch): New options -mhotpatch, -mhotpatch=

14566

+ * config/s390/s390-protos.h (s390_asm_output_function_label): Add

14567

+ prototype

14568

+ * config/s390/s390.h (ASM_OUTPUT_FUNCTION_LABEL): Target specific

14569

+ function label generation for hotpatching

14570

+ (FUNCTION_BOUNDARY): Align functions to eight bytes

14571

+ * doc/extend.texi: Document hotpatch attribute

14572

+ * doc/invoke.texi: Document -mhotpatch option

14573

+

14574

+2013-12-18 Eric Botcazou <ebotcazou@adacore.com>

14575

+

14576

+ * config/arm/arm.c (arm_expand_epilogue_apcs_frame): Fix thinko.

14577

+

14578

+2013-12-12 Vladimir Makarov <vmakarov@redhat.com>

14579

+

14580

+ PR middle-end/59470

14581

+ * lra-coalesce.c (lra_coalesce): Invalidate inheritance pseudo

14582

+ values if necessary.

14583

+

14584

+2013-12-12 Jakub Jelinek <jakub@redhat.com>

14585

+

14586

+ PR libgomp/59467

14587

+ * gimplify.c (omp_check_private): Add copyprivate argument, if it

14588

+ is true, don't check omp_privatize_by_reference.

14589

+ (gimplify_scan_omp_clauses): For OMP_CLAUSE_COPYPRIVATE verify

14590

+ decl is private in outer context. Adjust omp_check_private caller.

14591

+

14592

+2013-12-10 Eric Botcazou <ebotcazou@adacore.com>

14593

+

14594

+ PR rtl-optimization/58295

14595

+ * simplify-rtx.c (simplify_truncation): Restrict the distribution for

14596

+ WORD_REGISTER_OPERATIONS targets.

14597

+

14598

+2013-12-10 Kai Tietz <ktietz@redhat.com>

14599

+

14600

+ PR target/56807

14601

+ * config/i386/i386.c (ix86_expand_prologue): Address saved

14602

+ registers stack-relative, not via frame-pointer.

14603

+

14604

+2013-12-09 Alan Modra <amodra@gmail.com>

14605

+

14606

+ Apply from mainline

14607

+ 2013-12-05 Alan Modra <amodra@gmail.com>

14608

+ * configure.ac (BUILD_CXXFLAGS) Don't use ALL_CXXFLAGS for

14609

+ build != host.

14610

+ <recursive call for build != host>: Clear GMPINC. Don't bother

14611

+ saving CFLAGS.

14612

+ * configure: Regenerate.

14613

+

14614

+2013-12-08 Uros Bizjak <ubizjak@gmail.com>

14615

+

14616

+ Backport from mainline

14617

+ 2013-12-06 Uros Bizjak <ubizjak@gmail.com>

14618

+

14619

+ PR target/59405

14620

+ * config/i386/i386.c (type_natural_mode): Properly handle

14621

+ size 8 for !TARGET_64BIT.

14622

+

14623

+2013-12-07 Ralf Corsépius <ralf.corsepius@rtems.org>

14624

+

14625

+ * config.gcc (microblaze*-*-rtems*): Add TARGET_BIG_ENDIAN_DEFAULT.

14626

+

14627

+2013-12-06 Jakub Jelinek <jakub@redhat.com>

14628

+

14629

+ PR tree-optimization/59388

14630

+ * tree-ssa-reassoc.c (update_range_test): If op == range->exp,

14631

+ gimplify tem after stmt rather than before it.

14632

+

14633

+2013-12-06 Oleg Endo <olegendo@gcc.gnu.org>

14634

+

14635

+ Backport from mainline

14636

+ 2013-11-26 Oleg Endo <olegendo@gcc.gnu.org>

14637

+

14638

+ PR target/58314

14639

+ PR target/50751

14640

+ * config/sh/sh.c (max_mov_insn_displacement, disp_addr_displacement):

14641

+ Prefix function names with 'sh_'. Make them non-static.

14642

+ * config/sh/sh-protos.h (sh_disp_addr_displacement,

14643

+ sh_max_mov_insn_displacement): Add declarations.

14644

+ * config/sh/constraints.md (Q): Reject QImode.

14645

+ (Sdd): Use match_code "mem".

14646

+ (Snd): Fix erroneous matching of non-memory operands.

14647

+ * config/sh/predicates.md (short_displacement_mem_operand): New

14648

+ predicate.

14649

+ (general_movsrc_operand): Disallow PC relative QImode loads.

14650

+ * config/sh/sh.md (*mov<mode>_reg_reg): Remove it.

14651

+ (*movqi, *movhi): Merge both insns into...

14652

+ (*mov<mode>): ... this new insn. Replace generic 'm' constraints with

14653

+ 'Snd' and 'Sdd' constraints. Calculate insn length dynamically based

14654

+ on the operand types.

14655

+

14656

+2013-12-06 Richard Biener <rguenther@suse.de>

14657

+

14658

+ Backport from mainline

14659

+ 2013-11-29 Richard Biener <rguenther@suse.de>

14660

+

14661

+ PR tree-optimization/59334

14662

+ * tree-ssa-dce.c (eliminate_unnecessary_stmts): Fix bug

14663

+ in previous commit.

14664

+

14665

+ 2013-11-28 Richard Biener <rguenther@suse.de>

14666

+

14667

+ PR tree-optimization/59330

14668

+ * tree-ssa-dce.c (eliminate_unnecessary_stmts): Simplify

14669

+ and fix delayed marking of free calls not necessary.

14670

+

14671

+2013-12-06 Richard Biener <rguenther@suse.de>

14672

+

14673

+ Backport from mainline

14674

+ 2013-11-27 Richard Biener <rguenther@suse.de>

14675

+

14676

+ PR tree-optimization/59288

14677

+ * tree-vect-loop.c (get_initial_def_for_induction): Do not

14678

+ re-analyze the PHI but use STMT_VINFO_LOOP_PHI_EVOLUTION_PART.

14679

+

14680

+ 2013-11-19 Richard Biener <rguenther@suse.de>

14681

+

14682

+ PR tree-optimization/59164

14683

+ * tree-vect-loop.c (vect_analyze_loop_operations): Adjust

14684

+ check whether we can create an epilogue loop to reflect the

14685

+ cases where we create one.

14686

+

14687

+ 2013-09-05 Richard Biener <rguenther@suse.de>

14688

+

14689

+ PR tree-optimization/58137

14690

+ * tree-vect-stmts.c (get_vectype_for_scalar_type_and_size):

14691

+ Do not create vectors of pointers.

14692

+ * tree-vect-loop.c (get_initial_def_for_induction): Use proper

14693

+ types for the components of the vector initializer.

14694

+ * tree-cfg.c (verify_gimple_assign_binary): Remove special-casing

14695

+ allowing pointer vectors with PLUS_EXPR/MINUS_EXPR.

14696

+

14697

+2013-12-06 Oleg Endo <olegendo@gcc.gnu.org>

14698

+

14699

+ PR target/51244

14700

+ PR target/59343

14701

+ * config/sh/sh.md (*cbranch_t): Check that there are no labels between

14702

+ the s1 insn and the testing insn. Remove REG_DEAD note from s1 insn.

14703

+

14704

+2013-12-05 Richard Biener <rguenther@suse.de>

14705

+

14706

+ Backport from mainline

14707

+ 2013-11-19 Richard Biener <rguenther@suse.de>

14708

+

14709

+ PR middle-end/58956

14710

+ * tree-ssa-ter.c (find_replaceable_in_bb): Avoid forwarding

14711

+ loads into stmts that may clobber it.

14712

+

14713

+2013-12-04 Jakub Jelinek <jakub@redhat.com>

14714

+

14715

+ PR rtl-optimization/58726

14716

+ * combine.c (force_to_mode): Fix comment typo. Don't destructively

14717

+ modify x for ROTATE, ROTATERT and IF_THEN_ELSE.

14718

+

14719

+2013-12-04 Jakub Jelinek <jakub@redhat.com>

14720

+ Uros Bizjak <ubizjak@gmail.com>

14721

+

14722

+ PR target/59163

14723

+ * config/i386/i386.c (ix86_legitimate_combined_insn): If for

14724

+ !TARGET_AVX there is misaligned MEM operand with vector mode

14725

+ and get_attr_ssememalign is 0, return false.

14726

+ (ix86_expand_special_args_builtin): Add get_pointer_alignment

14727

+ computed alignment and for non-temporal loads/stores also

14728

+ at least GET_MODE_ALIGNMENT as MEM_ALIGN.

14729

+ * config/i386/sse.md

14730

+ (<sse>_loadu<ssemodesuffix><avxsizesuffix>,

14731

+ <sse>_storeu<ssemodesuffix><avxsizesuffix>,

14732

+ <sse2>_loaddqu<avxsizesuffix>,

14733

+ <sse2>_storedqu<avxsizesuffix>, <sse3>_lddqu<avxsizesuffix>,

14734

+ sse_vmrcpv4sf2, sse_vmrsqrtv4sf2, sse2_cvtdq2pd, sse_movhlps,

14735

+ sse_movlhps, sse_storehps, sse_loadhps, sse_loadlps,

14736

+ *vec_interleave_highv2df, *vec_interleave_lowv2df,

14737

+ *vec_extractv2df_1_sse, sse2_loadhpd, sse2_loadlpd, sse2_movsd,

14738

+ sse4_1_<code>v8qiv8hi2, sse4_1_<code>v4qiv4si2,

14739

+ sse4_1_<code>v4hiv4si2, sse4_1_<code>v2qiv2di2,

14740

+ sse4_1_<code>v2hiv2di2, sse4_1_<code>v2siv2di2, sse4_2_pcmpestr,

14741

+ *sse4_2_pcmpestr_unaligned, sse4_2_pcmpestri, sse4_2_pcmpestrm,

14742

+ sse4_2_pcmpestr_cconly, sse4_2_pcmpistr, *sse4_2_pcmpistr_unaligned,

14743

+ sse4_2_pcmpistri, sse4_2_pcmpistrm, sse4_2_pcmpistr_cconly): Add

14744

+ ssememalign attribute.

14745

+ * config/i386/i386.md (ssememalign): New define_attr.

14746

+

14747

+2013-12-03 Jakub Jelinek <jakub@redhat.com>

14748

+

14749

+ PR middle-end/59011

14750

+ * gimplify.c (nonlocal_vla_vars): New variable.

14751

+ (gimplify_var_or_parm_decl): Put VAR_DECLs for VLAs into

14752

+ nonlocal_vla_vars chain.

14753

+ (gimplify_body): Call declare_vars on nonlocal_vla_vars chain

14754

+ if outer_bind has DECL_INITIAL (current_function_decl) block.

14755

+

14756

+ PR target/58864

14757

+ * optabs.c (emit_conditional_move): Save and restore

14758

+ pending_stack_adjust and stack_pointer_delta if cmove can't be used.

14759

+

14760

+2013-12-02 Jakub Jelinek <jakub@redhat.com>

14761

+

14762

+ PR tree-optimization/59358

14763

+ * tree-vrp.c (union_ranges): To check for the partially

14764

+ overlapping ranges or adjacent ranges, also compare *vr0max

14765

+ with vr1max.

14766

+

14767

+2013-12-02 Richard Biener <rguenther@suse.de>

14768

+

14769

+ PR tree-optimization/59139

14770

+ * tree-ssa-loop-niter.c (chain_of_csts_start): Properly match

14771

+ code in get_val_for.

14772

+ (get_val_for): Use gcc_checking_asserts.

14773

+

14774

+2013-11-27 Tom de Vries <tom@codesourcery.com>

14775

+ Marc Glisse <marc.glisse@inria.fr>

14776

+

14777

+ PR middle-end/59037

14778

+ * fold-const.c (fold_indirect_ref_1): Don't create out-of-bounds

14779

+ BIT_FIELD_REF.

14780

+ * gimplify.c (gimple_fold_indirect_ref): Same.

14781

+

14782

+2013-12-01 Eric Botcazou <ebotcazou@adacore.com>

14783

+

14784

+ * config/i386/winnt.c (i386_pe_asm_named_section): Be prepared for an

14785

+ identifier node.

14786

+

14787

+2013-12-01 Bernd Edlinger <bernd.edlinger@hotmail.de>

14788

+

14789

+ * expr.c (emit_group_store): Fix off-by-one BITFIELD_END argument.

14790

+

14791

+2013-11-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com>

14792

+

14793

+ Backport from mainline

14794

+ 2013-11-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com>

14795

+

14796

+ * config/arm/iterators.md (vrint_conds): New int attribute.

14797

+ * config/arm/vfp.md (<vrint_pattern><SDF:mode>2): Set conds attribute.

14798

+ (smax<mode>3): Likewise.

14799

+ (smin<mode>3): Likewise.

14800

+

14801

+2013-11-28 Uros Bizjak <ubizjak@gmail.com>

14802

+

14803

+ Backport from mainline

14804

+ 2013-11-27 Uros Bizjak <ubizjak@gmail.com>

14805

+ Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>

14806

+

14807

+ PR target/56788

14808

+ * gcc.target/i386/xop-frczX.c: New test.

14809

+

14810

+2013-11-28 Terry Guo <terry.guo@arm.com>

14811

+

14812

+ Backport mainline r205391

14813

+ 2013-11-26 Terry Guo <terry.guo@arm.com>

14814

+

14815

+ * config/arm/arm.c (require_pic_register): Handle high pic base

14816

+ register for thumb-1.

14817

+ (arm_load_pic_register): Also initialize high pic base register.

14818

+ * doc/invoke.texi: Update documentation for option -mpic-register.

14819

+

14820

+2013-11-27 Jakub Jelinek <jakub@redhat.com>

14821

+

14822

+ Backported from mainline

14823

+ 2013-11-26 Jakub Jelinek <jakub@redhat.com>

14824

+

14825

+ PR tree-optimization/59014

14826

+ * tree-vrp.c (register_edge_assert_for_1): Don't look

14827

+ through conversions from non-integral types or through

14828

+ narrowing conversions.

14829

+

14830

+2013-11-27 Eric Botcazou <ebotcazou@adacore.com>

14831

+

14832

+ PR middle-end/59138

14833

+ * expr.c (emit_group_store): Don't write past the end of the structure.

14834

+ (store_bit_field): Fix formatting.

14835

+

14836

+2013-11-24 Sebastian Huber <sebastian.huber@embedded-brains.de>

14837

+

14838

+ Backport from mainline

14839

+ 2013-09-17 Sebastian Huber <sebastian.huber@embedded-brains.de>

14840

+

14841

+ * config/sparc/t-rtems: Add leon3 multilibs.

14842

+

14843

+2013-11-24 Sebastian Huber <sebastian.huber@embedded-brains.de>

14844

+

14845

+ Backport from mainline

14846

+ 2013-08-09 Eric Botcazou <ebotcazou@adacore.com>

14847

+

14848

+ * configure.ac: Add GAS check for LEON instructions on SPARC.

14849

+ * configure: Regenerate.

14850

+ * config.in: Likewise.

14851

+ * config.gcc (with_cpu): Remove sparc-leon*-* and deal with LEON in the

14852

+ sparc*-*-* block.

14853

+ * config/sparc/sparc.opt (LEON, LEON3): New masks.

14854

+ * config/sparc/sparc.h (ASM_CPU32_DEFAULT_SPEC): Set to AS_LEON_FLAG

14855

+ for LEON or LEON3.

14856

+ (ASM_CPU_SPEC): Pass AS_LEON_FLAG if -mcpu=leon or -mcpu=leon3.

14857

+ (AS_LEON_FLAG): New macro.

14858

+ * config/sparc/sparc.c (sparc_option_override): Set MASK_LEON for leon

14859

+ and MASK_LEON3 for leon3 and unset them if HAVE_AS_LEON is not defined.

14860

+ Deal with LEON and LEON3 for the memory model.

14861

+ * config/sparc/sync.md (atomic_compare_and_swap<mode>): Enable if LEON3

14862

+ (atomic_compare_and_swap<mode>_1): Likewise.

14863

+ (*atomic_compare_and_swap<mode>_1): Likewise.

14864

+

14865

+2013-11-24 Sebastian Huber <sebastian.huber@embedded-brains.de>

14866

+

14867

+ Backport from mainline

14868

+ 2013-07-23 Eric Botcazou <ebotcazou@adacore.com>

14869

+

14870

+ * doc/invoke.texi (SPARC Options): Document new leon3 processor value.

14871

+

14872

+2013-11-24 Sebastian Huber <sebastian.huber@embedded-brains.de>

14873

+

14874

+ Backport from mainline

14875

+ 2013-07-22 Eric Botcazou <ebotcazou@adacore.com>

14876

+

14877

+ * config.gcc (sparc*-*-*): Accept leon3 processor.

14878

+ (sparc-leon*-*): Merge with sparc*-*-* and add leon3 support.

14879

+ * doc/invoke.texi (SPARC Options): Adjust -mfix-ut699 entry.

14880

+ * config/sparc/sparc-opts.h (enum processor_type): Add PROCESSOR_LEON3.

14881

+ * config/sparc/sparc.opt (enum processor_type): Add leon3.

14882

+ (mfix-ut699): Adjust comment.

14883

+ * config/sparc/sparc.h (TARGET_CPU_leon3): New define.

14884

+ (CPP_CPU32_DEFAULT_SPEC): Add leon3 support.

14885

+ (CPP_CPU_SPEC): Likewise.

14886

+ (ASM_CPU_SPEC): Likewise.

14887

+ * config/sparc/sparc.c (leon3_cost): New constant.

14888

+ (sparc_option_override): Add leon3 support.

14889

+ (mem_ref): New function.

14890

+ (sparc_gate_work_around_errata): Return true if -mfix-ut699 is enabled.

14891

+ (sparc_do_work_around_errata): Look into the instruction in the delay

14892

+ slot and adjust accordingly. Add fix for the data cache nullify issues

14893

+ of the UT699. Change insertion position for the NOP.

14894

+ * config/sparc/leon.md (leon_fpalu, leon_fpmds, write_buf): Delete.

14895

+ (leon3_load): New reservation.

14896

+ (leon_store): Bump latency to 2.

14897

+ (grfpu): New automaton.

14898

+ (grfpu_alu): New unit.

14899

+ (grfpu_ds): Likewise.

14900

+ (leon_fp_alu): Adjust.

14901

+ (leon_fp_mult): Delete.

14902

+ (leon_fp_div): Split into leon_fp_divs and leon_fp_divd.

14903

+ (leon_fp_sqrt): Split into leon_fp_sqrts and leon_fp_sqrtd.

14904

+ * config/sparc/sparc.md (cpu): Add leon3.

14905

+ * config/sparc/sync.md (atomic_exchangesi): Disable if -mfix-ut699.

14906

+ (swapsi): Likewise.

14907

+ (atomic_test_and_set): Likewise.

14908

+ (ldstub): Likewise.

14909

+

14910

+2013-11-24 Sebastian Huber <sebastian.huber@embedded-brains.de>

14911

+

14912

+ Backport from mainline

14913

+ 2013-04-10 Steven Bosscher <steven@gcc.gnu.org>

14914

+

14915

+ * config/sparc/sparc.c: Include tree-pass.h.

14916

+ (TARGET_MACHINE_DEPENDENT_REORG): Do not redefine.

14917

+ (sparc_reorg): Rename to sparc_do_work_around_errata. Move to

14918

+ head of file. Change return type. Split off gate function.

14919

+ (sparc_gate_work_around_errata): New function.

14920

+ (pass_work_around_errata): New pass definition.

14921

+ (insert_pass_work_around_errata) New pass insert definition to

14922

+ insert pass_work_around_errata just after delayed-branch scheduling.

14923

+ (sparc_option_override): Insert the pass.

14924

+ * config/sparc/t-sparc (sparc.o): Add TREE_PASS_H dependence.

14925

+

14926

+2013-11-24 Sebastian Huber <sebastian.huber@embedded-brains.de>

14927

+

14928

+ Backport from mainline

14929

+ 2013-05-28 Eric Botcazou <ebotcazou@adacore.com>

14930

+

14931

+ * doc/invoke.texi (SPARC Options): Document -mfix-ut699.

14932

+ * builtins.c (expand_builtin_mathfn) <BUILT_IN_SQRT>: Try to widen the

14933

+ mode if the instruction isn't available in the original mode.

14934

+ * config/sparc/sparc.opt (mfix-ut699): New option.

14935

+ * config/sparc/sparc.md (muldf3_extend): Disable if -mfix-ut699.

14936

+ (divdf3): Turn into expander.

14937

+ (divdf3_nofix): New insn.

14938

+ (divdf3_fix): Likewise.

14939

+ (divsf3): Disable if -mfix-ut699.

14940

+ (sqrtdf2): Turn into expander.

14941

+ (sqrtdf2_nofix): New insn.

14942

+ (sqrtdf2_fix): Likewise.

14943

+ (sqrtsf2): Disable if -mfix-ut699.

14944

+

14945

+2013-11-22 Eric Botcazou <ebotcazou@adacore.com>

14946

+

14947

+ * print-rtl.c (print_rtx) <case MEM>: Output a space if no MEM_EXPR.

14948

+

14949

+2013-11-21 Zhenqiang Chen <zhenqiang.chen@linaro.org>

14950

+

14951

+ PR bootstrap/57683

14952

+ Backport from mainline: r197467 and r198999.

14953

+ 2013-04-03 Jeff Law <law@redhat.com>

14954

+

14955

+ * Makefile.in (lra-constraints.o): Depend on $(OPTABS_H).

14956

+ (lra-eliminations.o): Likewise.

14957

+

14958

+ 2013-05-16 Jeff Law <law@redhat.com>

14959

+

14960

+ * Makefile.in (tree-switch-conversion.o): Depend on $(OPTABS_H).

14961

+

14962

+2013-11-20 Eric Botcazou <ebotcazou@adacore.com>

14963

+

14964

+ PR target/59207

14965

+ * config/sparc/sparc.c (sparc_fold_builtin) <case CODE_FOR_pdist_vis>:

14966

+ Make sure neg2_ovf is set before being used.

14967

+

14968

+2013-11-20 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>

14969

+ Dominik Vogt <vogt@linux.vnet.ibm.com>

14970

+

14971

+ Backport from mainline

14972

+ * config/s390/s390.c (s390_canonicalize_comparison): Don't fold

14973

+ int comparisons with an out of range condition code.

14974

+ (s390_optimize_nonescaping_tx): Skip empty BBs.

14975

+ Generate the new tbegin RTX when removing the FPR clobbers (with

14976

+ two SETs).

14977

+ (s390_expand_tbegin): Fix the retry loop counter. Copy CC to the

14978

+ result before doing the retry calculations.

14979

+ (s390_init_builtins): Make tbegin "returns_twice" and tabort

14980

+ "noreturn".

14981

+ * config/s390/s390.md (UNSPECV_TBEGIN_TDB): New constant used for

14982

+ the TDB setting part of an tbegin.

14983

+ ("tbegin_1", "tbegin_nofloat_1"): Add a set for the TDB.

14984

+ ("tx_assist"): Set unused argument to an immediate zero instead of

14985

+ loading zero into a GPR and pass it as argument.

14986

+ * config/s390/htmxlintrin.h (__TM_simple_begin, __TM_begin):

14987

+ Remove inline and related attributes.

14988

+ (__TM_nesting_depth, __TM_is_user_abort, __TM_is_named_user_abort)

14989

+ (__TM_is_illegal, __TM_is_footprint_exceeded)

14990

+ (__TM_is_nested_too_deep, __TM_is_conflict): Fix format value

14991

+ check.

14992

+

14993

+2013-11-19 Uros Bizjak <ubizjak@gmail.com>

14994

+

14995

+ Backport from mainline

14996

+ 2013-11-18 Uros Bizjak <ubizjak@gmail.com>

14997

+

14998

+ * config/i386/i386.c (ix86_decompose_address): Use REG_P instead of

14999

+ ix86_address_subreg_operand. Move subreg checks to

15000

+ ix86_validate_address_register. Move address override check to

15001

+ ix86_legitimate_address_p.

15002

+ (ix86_validate_address_register): New function.

15003

+ (ix86_legitimate_address_p): Call ix86_validate_address_register

15004

+ to validate base and index registers. Add address override check

15005

+ from ix86_decompose_address.

15006

+ (ix86_decompose_address): Remove.

15007

+

15008

+ Backport from mainline

15009

+ 2013-11-17 Uros Bizjak <ubizjak@gmail.com>

15010

+

15011

+ PR target/59153

15012

+ * config/i386/i386.c (ix86_address_subreg_operand): Do not

15013

+ reject non-integer subregs.

15014

+ (ix86_decompose_address): Do not reject invalid CONST_INT RTXes.

15015

+ Move check for invalid x32 constant addresses ...

15016

+ (ix86_legitimate_address_p): ... here.

15017

+

15018

+2013-11-19 Richard Biener <rguenther@suse.de>

15019

+

15020

+ Backport from mainline

15021

+ 2013-11-07 Richard Biener <rguenther@suse.de>

15022

+

15023

+ * tree-dfa.c (get_ref_base_and_extent): Fix casting.

15024

+

15025

+2013-11-19 Richard Biener <rguenther@suse.de>

15026

+

15027

+ PR tree-optimization/57517

15028

+ * tree-predcom.c (combinable_refs_p): Verify the combination

15029

+ is always executed when the refs are.

15030

+

15031

+2013-11-19 Richard Biener <rguenther@suse.de>

15032

+

15033

+ Backport from mainline

15034

+ 2013-11-05 Richard Biener <rguenther@suse.de>

15035

+

15036

+ PR middle-end/58941

15037

+ * tree-dfa.c (get_ref_base_and_extent): Merge common code

15038

+ in MEM_REF and TARGET_MEM_REF handling. Make sure to

15039

+ process trailing array detection before diving into the

15040

+ view-converted object (and possibly apply some extra offset).

15041

+

15042

+2013-11-18 Richard Biener <rguenther@suse.de>

15043

+

15044

+ Backport from mainline

15045

+ 2013-10-21 Richard Biener <rguenther@suse.de>

15046

+

15047

+ PR tree-optimization/58794

15048

+ * fold-const.c (operand_equal_p): Compare FIELD_DECL operand

15049

+ of COMPONENT_REFs with OEP_CONSTANT_ADDRESS_OF left in place.

15050

+

15051

+ 2013-10-21 Richard Biener <rguenther@suse.de>

15052

+

15053

+ PR middle-end/58742

15054

+ * fold-const.c (fold_binary_loc): Fold ((T) (X /[ex] C)) * C

15055

+ to (T) X for sign-changing conversions (or no conversion).

15056

+

15057

+ 2013-11-06 Richard Biener <rguenther@suse.de>

15058

+

15059

+ PR tree-optimization/58653

15060

+ * tree-predcom.c (ref_at_iteration): Rewrite to generate

15061

+ a MEM_REF.

15062

+ (prepare_initializers_chain): Adjust.

15063

+

15064

+ PR tree-optimization/59047

15065

+ * tree-predcom.c (ref_at_iteration): Handle bitfield accesses

15066

+ properly.

15067

+

15068

+ 2013-10-15 Richard Biener <rguenther@suse.de>

15069

+

15070

+ PR tree-optimization/58143

15071

+ * tree-ssa-loop-im.c (arith_code_with_undefined_signed_overflow):

15072

+ New function.

15073

+ (rewrite_to_defined_overflow): Likewise.

15074

+ (move_computations_dom_walker::before_dom): Rewrite stmts

15075

+ with undefined signed overflow that are not always executed

15076

+ into unsigned arithmetic.

15077

+

15078

+2013-11-14 Uros Bizjak <ubizjak@gmail.com>

15079

+

15080

+ Backport from mainline

15081

+ 2013-11-10 Uros Bizjak <ubizjak@gmail.com>

15082

+

15083

+ * mode-switching.c (optimize_mode_switching): Mark block as

15084

+ nontransparent, if last_mode at block exit is different from no_mode.

15085

+

15086

+ Backport from mainline

15087

+ 2013-11-06 Uros Bizjak <ubizjak@gmail.com>

15088

+

15089

+ PR target/59021

15090

+ * config/i386/i386.c (ix86_avx_u128_mode_needed): Require

15091

+ AVX_U128_DIRTY mode for call_insn RTXes that use AVX256 registers.

15092

+ (ix86_avx_u128_mode_needed): Return AVX_U128_DIRTY mode for call_insn

15093

+ RTXes that return in AVX256 register.

15094

+

15095

+2013-11-14 Jakub Jelinek <jakub@redhat.com>

15096

+ Uros Bizjak <ubizjak@gmail.com>

15097

+

15098

+ PR target/59101

15099

+ * config/i386/i386.md (*anddi_2): Only allow CCZmode if

15100

+ operands[2] satisfies_constraint_Z that might have bit 31 set.

15101

+

15102

+2013-11-12 H.J. Lu <hongjiu.lu@intel.com>

15103

+

15104

+ Backported from mainline

15105

+ 2013-11-12 H.J. Lu <hongjiu.lu@intel.com>

15106

+

15107

+ PR target/59088

15108

+ * config/i386/i386.c (initial_ix86_tune_features): Set

15109

+ X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL and

15110

+ X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL for m_HASWELL.

15111

+

15112

+2013-11-11 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>

15113

+

15114

+ Backported from mainline

15115

+ 2013-10-30 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>

15116

+

15117

+ PR target/58854

15118

+ * config/arm/arm.c (arm_expand_epilogue_apcs_frame): Emit blockage

15119

+

15120

+2013-11-11 Jakub Jelinek <jakub@redhat.com>

15121

+

15122

+ Backported from mainline

15123

+ 2013-11-06 Jakub Jelinek <jakub@redhat.com>

15124

+

15125

+ PR middle-end/58970

15126

+ * expr.c (get_bit_range): Handle *offset == NULL_TREE.

15127

+ (expand_assignment): If *bitpos is negative, set *offset

15128

+ and adjust *bitpos, so that it is not negative.

15129

+

15130

+ 2013-11-05 Jakub Jelinek <jakub@redhat.com>

15131

+

15132

+ PR rtl-optimization/58997

15133

+ * loop-iv.c (iv_subreg): For IV_UNKNOWN_EXTEND, expect

15134

+ get_iv_value to be in iv->mode rather than iv->extend_mode.

15135

+ (iv_extend): Likewise. Otherwise, if iv->extend != extend,

15136

+ use lowpart_subreg on get_iv_value before calling simplify_gen_unary.

15137

+ * loop-unswitch.c (may_unswitch_on): Make sure op[i] is in the right

15138

+ mode.

15139

+

15140

+2013-11-10 Karlson2k <k2k@narod.ru>

15141

+ Kai Tietz <ktietz@redhat.com>

15142

+

15143

+ Merged from trunk

15144

+ PR plugins/52872

15145

+ * configure.ac: Adding for exported symbols check

15146

+ and for rdynamic-check executable-extension.

15147

+ * configure: Regenerated.

15148

+

15149

+2013-11-07 H.J. Lu <hongjiu.lu@intel.com>

15150

+

15151

+ PR target/59034

15152

+ * config/i386/i386.md (push peepholer/splitter): Use Pmode

15153

+ with stack_pointer_rtx.

15154

+

15155

+2013-11-05 Uros Bizjak <ubizjak@gmail.com>

15156

+

15157

+ * config/i386/t-rtems (MULTILIB_MATCHES): Fix option typos.

15158

+

15159

+2013-11-05 Jakub Jelinek <jakub@redhat.com>

15160

+

15161

+ PR tree-optimization/58984

15162

+ * ipa-prop.c (ipa_load_from_parm_agg_1): Add SIZE_P argument,

15163

+ set *SIZE_P if non-NULL on success.

15164

+ (ipa_load_from_parm_agg, ipa_analyze_indirect_call_uses): Adjust

15165

+ callers.

15166

+ (ipcp_transform_function): Likewise. Punt if size of access

15167

+ is different from TYPE_SIZE on v->value's type.

15168

+

15169

+2013-11-03 H.J. Lu <hongjiu.lu@intel.com>

15170

+

15171

+ Backport from mainline

15172

+ 2013-10-12 H.J. Lu <hongjiu.lu@intel.com>

15173

+

15174

+ PR target/58690

15175

+ * config/i386/i386.c (ix86_copy_addr_to_reg): New function.

15176

+ (ix86_expand_movmem): Replace copy_addr_to_reg with

15177

+ ix86_copy_addr_to_reg.

15178

+ (ix86_expand_setmem): Likewise.

15179

+

15180

+2013-10-29 Uros Bizjak <ubizjak@gmail.com>

15181

+

15182

+ Backport from mainline

15183

+ 2013-08-08 Richard Sandiford <rdsandiford@googlemail.com>

15184

+

15185

+ PR rtl-optimization/58079

15186

+ * combine.c (combine_simplify_rtx): Avoid using SUBST if

15187

+ simplify_comparison has widened a comparison with an integer.

15188

+

15189

+2013-10-29 Martin Jambor <mjambor@suse.cz>

15190

+

15191

+ PR middle-end/58789

15192

+ Backport from mainline

15193

+ 2013-05-09 Martin Jambor <mjambor@suse.cz>

15194

+

15195

+ PR lto/57084

15196

+ * gimple-fold.c (canonicalize_constructor_val): Call

15197

+ cgraph_get_create_real_symbol_node instead of cgraph_get_create_node.

15198

+

15199

+ Backport from mainline

15200

+ 2013-03-16 Jan Hubicka <jh@suse.cz>

15201

+

15202

+ * cgraph.h (cgraph_get_create_real_symbol_node): Declare.

15203

+ * cgraph.c (cgraph_get_create_real_symbol_node): New function.

15204

+ * cgrpahbuild.c: Use cgraph_get_create_real_symbol_node instead

15205

+ of cgraph_get_create_node.

15206

+ * ipa-prop.c (ipa_make_edge_direct_to_target): Likewise.

15207

+

15208

+2013-10-28 Tom de Vries <tom@codesourcery.com>

15209

+

15210

+ * cfgexpand.c (gimple_expand_cfg): Remove test for parm_birth_insn.

15211

+ Don't commit insertions after NOTE_INSN_FUNCTION_BEG.

15212

+

15213

+2013-10-26 Uros Bizjak <ubizjak@gmail.com>

15214

+

15215

+ Backport from mainline

15216

+ 2013-10-22 Uros Bizjak <ubizjak@gmail.com>

15217

+

15218

+ PR target/58779

15219

+ * config/i386/i386.c (put_condition_code) <case GTU, case LEU>:

15220

+ Remove CCCmode handling.

15221

+ <case LTU>: Return 'c' suffix for CCCmode.

15222

+ <case GEU>: Return 'nc' suffix for CCCmode.

15223

+ (ix86_cc_mode) <case GTU, case LEU>: Do not generate overflow checks.

15224

+ * config/i386/i386.md (*sub<mode>3_cconly_overflow): Remove.

15225

+ (*sub<mode>3_cc_overflow): Ditto.

15226

+ (*subsi3_zext_cc_overflow): Ditto.

15227

+

15228

+2013-10-26 Uros Bizjak <ubizjak@gmail.com>

15229

+

15230

+ Backport from mainline

15231

+ 2013-10-19 Uros Bizjak <ubizjak@gmail.com>

15232

+

15233

+ PR target/58792

15234

+ * config/i386/i386.c (ix86_function_value_regno): Add DX_REG,

15235

+ ST1_REG and XMM1_REG for 32bit and 64bit targets. Also add DI_REG

15236

+ and SI_REG for 64bit SYSV ABI targets.

15237

+

15238

+2013-08-25 Richard Henderson <rth@twiddle.net>

15239

+

15240

+ PR rtl/58542

15241

+ * optabs.c (maybe_emit_atomic_exchange): Use create_input_operand

15242

+ instead of create_convert_operand_to.

15243

+ (maybe_emit_sync_lock_test_and_set): Likewise.

15244

+ (expand_atomic_compare_and_swap): Likewise.

15245

+ (maybe_emit_compare_and_swap_exchange_loop): Don't convert_modes.

15246

+

15247

+2013-10-25 Eric Botcazou <ebotcazou@adacore.com>

15248

+

15249

+ PR rtl-optimization/58831

15250

+ * alias.c (init_alias_analysis): At the beginning of each iteration, set

15251

+ the reg_seen[N] bit if static_reg_base_value[N] is non-null.

15252

+

15253

+2013-10-25 Eric Botcazou <ebotcazou@adacore.com>

15254

+

15255

+ * recog.c (search_ofs): New static variable moved from...

15256

+ (peep2_find_free_register): ...here.

15257

+ (peephole2_optimize): Initialize it.

15258

+

15259

+2013-10-24 David Edelsohn <dje.gcc@gmail.com>

15260

+

15261

+ Backport from mainline

15262

+ 2013-10-23 David Edelsohn <dje.gcc@gmail.com>

15263

+

15264

+ PR target/58838

15265

+ * config/rs6000/rs6000.md (mulsi3_internal1 and splitter): Add

15266

+ TARGET_32BIT final condition.

15267

+ (mulsi3_internal2 and splitter): Same.

15268

+

15269

+2013-10-23 Tom de Vries <tom@codesourcery.com>

15270

+

15271

+ PR tree-optimization/58805

15272

+ * tree-ssa-tail-merge.c (stmt_local_def): Add gimple_vdef check.

15273

+

15274

+2013-10-23 Richard Biener <rguenther@suse.de>

15275

+

15276

+ Backport from mainline

15277

+ 2013-06-24 Richard Biener <rguenther@suse.de>

15278

+

15279

+ PR tree-optimization/57488

15280

+ * tree-ssa-pre.c (insert): Clear NEW sets before each iteration.

15281

+

15282

+2013-10-16 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>

15283

+

15284

+ Backport from mainline

15285

+ 2013-10-16 Ganesh Gopalasubramanian

15286

+ <Ganesh.Gopalasubramanian@amd.com>

15287

+

15288

+ * config/i386/i386.c (ix86_option_override_internal): Enable FMA4

15289

+ for AMD bdver3.

15290

+

15291

2013-10-16 Release Manager

15292

15293

* GCC 4.8.2 released.

15294

@@ -639,7 +5970,7 @@

15295

2013-07-31 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>

15296

15297

Backport from mainline

15298

- 2013-03-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>

15299

+ 2013-03-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>

15300

15301

* config/s390/s390.h (TARGET_FLT_EVAL_METHOD): Define.

15302

15303

Index: gcc/testsuite/gcc.target/arm/thumb1-pic-single-base.c

15304

===================================================================

15305

--- a/src/gcc/testsuite/gcc.target/arm/thumb1-pic-single-base.c (.../tags/gcc_4_8_2_release)

15306

+++ b/src/gcc/testsuite/gcc.target/arm/thumb1-pic-single-base.c (.../branches/gcc-4_8-branch)

15307

@@ -0,0 +1,11 @@

15308

+/* { dg-do compile } */

15309

+/* { dg-require-effective-target arm_thumb1_ok } */

15310

+/* { dg-options "-mthumb -fpic -msingle-pic-base" } */

15311

+

15312

+int g_test;

15313

+

15314

+int

15315

+foo (int par)

15316

+{

15317

+ g_test = par;

15318

+}

15319

Index: gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64-1.c

15320

===================================================================

15321

--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64-1.c (.../tags/gcc_4_8_2_release)

15322

+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64-1.c (.../branches/gcc-4_8-branch)

15323

@@ -0,0 +1,25 @@

15324

+/* Test the `vst1Q_laneu64' ARM Neon intrinsic. */

15325

+

15326

+/* Detect ICE in the case of unaligned memory address. */

15327

+

15328

+/* { dg-do compile } */

15329

+/* { dg-require-effective-target arm_neon_ok } */

15330

+/* { dg-add-options arm_neon } */

15331

+

15332

+#include "arm_neon.h"

15333

+

15334

+unsigned char dummy_store[1000];

15335

+

15336

+void

15337

+foo (char* addr)

15338

+{

15339

+ uint8x16_t vdata = vld1q_u8 (addr);

15340

+ vst1q_lane_u64 ((uint64_t*) &dummy_store, vreinterpretq_u64_u8 (vdata), 0);

15341

+}

15342

+

15343

+uint64_t

15344

+bar (uint64x2_t vdata)

15345

+{

15346

+ vdata = vld1q_lane_u64 ((uint64_t*) &dummy_store, vdata, 0);

15347

+ return vgetq_lane_u64 (vdata, 0);

15348

+}

15349

Index: gcc/testsuite/gcc.target/arm/thumb1-pic-high-reg.c

15350

===================================================================

15351

--- a/src/gcc/testsuite/gcc.target/arm/thumb1-pic-high-reg.c (.../tags/gcc_4_8_2_release)

15352

+++ b/src/gcc/testsuite/gcc.target/arm/thumb1-pic-high-reg.c (.../branches/gcc-4_8-branch)

15353

@@ -0,0 +1,11 @@

15354

+/* { dg-do compile } */

15355

+/* { dg-require-effective-target arm_thumb1_ok } */

15356

+/* { dg-options "-mthumb -fpic -mpic-register=9" } */

15357

+

15358

+int g_test;

15359

+

15360

+int

15361

+foo (int par)

15362

+{

15363

+ g_test = par;

15364

+}

15365

Index: gcc/testsuite/gcc.target/arm/require-pic-register-loc.c

15366

===================================================================

15367

--- a/src/gcc/testsuite/gcc.target/arm/require-pic-register-loc.c (.../tags/gcc_4_8_2_release)

15368

+++ b/src/gcc/testsuite/gcc.target/arm/require-pic-register-loc.c (.../branches/gcc-4_8-branch)

15369

@@ -0,0 +1,29 @@

15370

+/* { dg-do compile } */

15371

+/* { dg-options "-g -fPIC" } */

15372

+

15373

+void *v;

15374

+void a (void *x) { }

15375

+void b (void) { }

15376

+ /* line 7. */

15377

+int /* line 8. */

15378

+main (int argc) /* line 9. */

15379

+{ /* line 10. */

15380

+ if (argc == 12345) /* line 11. */

15381

+ {

15382

+ a (v);

15383

+ return 1;

15384

+ }

15385

+ b ();

15386

+

15387

+ return 0;

15388

+}

15389

+

15390

+/* { dg-final { scan-assembler-not "\.loc 1 7 0" } } */

15391

+/* { dg-final { scan-assembler-not "\.loc 1 8 0" } } */

15392

+/* { dg-final { scan-assembler-not "\.loc 1 9 0" } } */

15393

+

15394

+/* The loc at the start of the prologue. */

15395

+/* { dg-final { scan-assembler-times "\.loc 1 10 0" 1 } } */

15396

+

15397

+/* The loc at the end of the prologue, with the first user line. */

15398

+/* { dg-final { scan-assembler-times "\.loc 1 11 0" 1 } } */

15399

Index: gcc/testsuite/gcc.target/arm/vrinta-ce.c

15400

===================================================================

15401

--- a/src/gcc/testsuite/gcc.target/arm/vrinta-ce.c (.../tags/gcc_4_8_2_release)

15402

+++ b/src/gcc/testsuite/gcc.target/arm/vrinta-ce.c (.../branches/gcc-4_8-branch)

15403

@@ -0,0 +1,15 @@

15404

+/* { dg-do compile } */

15405

+/* { dg-require-effective-target arm_v8_vfp_ok } */

15406

+/* { dg-options "-O2 -marm -march=armv8-a" } */

15407

+/* { dg-add-options arm_v8_vfp } */

15408

+

15409

+double foo (double a)

15410

+{

15411

+ if (a > 3.0)

15412

+ return __builtin_round (a);

15413

+

15414

+ return 0.0;

15415

+}

15416

+

15417

+/* { dg-final { scan-assembler-times "vrinta.f64\td\[0-9\]+" 1 } } */

15418

+

15419

Index: gcc/testsuite/gcc.target/arm/pr54300.C

15420

===================================================================

15421

--- a/src/gcc/testsuite/gcc.target/arm/pr54300.C (.../tags/gcc_4_8_2_release)

15422

+++ b/src/gcc/testsuite/gcc.target/arm/pr54300.C (.../branches/gcc-4_8-branch)

15423

@@ -0,0 +1,61 @@

15424

+/* { dg-do run } */

15425

+/* { dg-require-effective-target arm_neon } */

15426

+/* { dg-options "-O2" } */

15427

+/* { dg-add-options arm_neon } */

15428

+

15429

+#include <arm_neon.h>

15430

+#include <stdlib.h>

15431

+

15432

+struct __attribute__ ((aligned(8))) _v16u8_ {

15433

+ uint8x16_t val;

15434

+ _v16u8_( const int16x8_t &src) { val = vreinterpretq_u8_s16(src); }

15435

+ operator int16x8_t () const { return vreinterpretq_s16_u8(val); }

15436

+};

15437

+typedef struct _v16u8_ v16u8;

15438

+

15439

+struct __attribute__ ((aligned(4))) _v8u8_ {

15440

+ uint8x8_t val;

15441

+ _v8u8_( const uint8x8_t &src) { val = src; }

15442

+ operator int16x4_t () const { return vreinterpret_s16_u8(val); }

15443

+};

15444

+typedef struct _v8u8_ v8u8;

15445

+

15446

+typedef v16u8 v8i16;

15447

+typedef int32x4_t v4i32;

15448

+typedef const short cv1i16;

15449

+typedef const unsigned char cv1u8;

15450

+typedef const v8i16 cv8i16;

15451

+

15452

+static inline __attribute__((always_inline)) v8u8 zero_64(){ return vdup_n_u8( 0 ); }

15453

+

15454

+static inline __attribute__((always_inline)) v8i16 loadlo_8i16( cv8i16* p ){

15455

+ return vcombine_s16( vld1_s16( (cv1i16 *)p ), zero_64() );

15456

+}

15457

+static inline __attribute__((always_inline)) v8i16 _loadlo_8i16( cv8i16* p, int offset ){

15458

+ return loadlo_8i16( (cv8i16*)(&((cv1u8*)p)[offset]) );

15459

+}

15460

+

15461

+void __attribute__((noinline))

15462

+test(unsigned short *_Inp, int32_t *_Out,

15463

+ unsigned int s1v, unsigned int dv0,

15464

+ unsigned int smask_v)

15465

+{

15466

+ int32x4_t c = vdupq_n_s32(0);

15467

+

15468

+ for(unsigned int sv=0 ; sv!=dv0 ; sv=(sv+s1v)&smask_v )

15469

+ {

15470

+ int32x4_t s;

15471

+ s = vmovl_s16( vget_low_s16( _loadlo_8i16( (cv8i16*) _Inp, sv ) ) );

15472

+ c = vaddq_s32( c, s );

15473

+ }

15474

+ vst1q_s32( _Out, c );

15475

+}

15476

+

15477

+main()

15478

+{

15479

+ unsigned short a[4] = {1, 2, 3, 4};

15480

+ int32_t b[4] = {0, 0, 0, 0};

15481

+ test(a, b, 1, 1, ~0);

15482

+ if (b[0] != 1 || b[1] != 2 || b[2] != 3 || b[3] != 4)

15483

+ abort();

15484

+}

15485

Index: gcc/testsuite/gcc.target/arm/pr59826.c

15486

===================================================================

15487

--- a/src/gcc/testsuite/gcc.target/arm/pr59826.c (.../tags/gcc_4_8_2_release)

15488

+++ b/src/gcc/testsuite/gcc.target/arm/pr59826.c (.../branches/gcc-4_8-branch)

15489

@@ -0,0 +1,35 @@

15490

+/* { dg-do compile } */

15491

+/* { dg-options "-mthumb -mcpu=cortex-m4 -fprefetch-loop-arrays -O2" } */

15492

+

15493

+typedef struct genxWriter_rec * genxWriter;

15494

+typedef unsigned char * utf8;

15495

+typedef const unsigned char * constUtf8;

15496

+

15497

+int genxScrubText(genxWriter w, constUtf8 in, utf8 out)

15498

+{

15499

+ int problems = 0;

15500

+ constUtf8 last = in;

15501

+

15502

+ while (*in)

15503

+ {

15504

+ int c = genxNextUnicodeChar(&in);

15505

+ if (c == -1)

15506

+ {

15507

+ problems++;

15508

+ last = in;

15509

+ continue;

15510

+ }

15511

+

15512

+ if (!isXMLChar(w, c))

15513

+ {

15514

+ problems++;

15515

+ last = in;

15516

+ continue;

15517

+ }

15518

+

15519

+ while (last < in)

15520

+ *out++ = *last++;

15521

+ }

15522

+ *out = 0;

15523

+ return problems;

15524

+}

15525

Index: gcc/testsuite/gcc.target/arm/pr57637.c

15526

===================================================================

15527

--- a/src/gcc/testsuite/gcc.target/arm/pr57637.c (.../tags/gcc_4_8_2_release)

15528

+++ b/src/gcc/testsuite/gcc.target/arm/pr57637.c (.../branches/gcc-4_8-branch)

15529

@@ -0,0 +1,206 @@

15530

+/* { dg-do run } */

15531

+/* { dg-options "-O2 -fno-inline" } */

15532

+

15533

+typedef struct _GtkCssStyleProperty GtkCssStyleProperty;

15534

+

15535

+struct _GtkCssStyleProperty

15536

+{

15537

+ int *initial_value;

15538

+ unsigned int id;

15539

+ unsigned int inherit :1;

15540

+ unsigned int animated :1;

15541

+ unsigned int affects_size :1;

15542

+ unsigned int affects_font :1;

15543

+

15544

+ int * parse_value;

15545

+ int * query_value;

15546

+ int * assign_value;

15547

+};

15548

+

15549

+void

15550

+g_assertion_message_expr (const char *domain,

15551

+ const char *file,

15552

+ int line,

15553

+ const char *func,

15554

+ const char *expr) __attribute__((__noreturn__));

15555

+

15556

+void

15557

+g_assertion_message_expr (const char *domain,

15558

+ const char *file,

15559

+ int line,

15560

+ const char *func,

15561

+ const char *expr)

15562

+{

15563

+ __builtin_abort ();

15564

+}

15565

+int

15566

+get_id (GtkCssStyleProperty *property)

15567

+{

15568

+ return 1;

15569

+}

15570

+int

15571

+_gtk_css_style_property_get_type ()

15572

+{

15573

+ return 1;

15574

+}

15575

+

15576

+GtkCssStyleProperty *

15577

+g_object_new (int object_type,

15578

+ const char *first_property_name,

15579

+ ...)

15580

+{

15581

+ return (GtkCssStyleProperty *) __builtin_malloc (sizeof (GtkCssStyleProperty));

15582

+}

15583

+

15584

+typedef enum {

15585

+ INHERIT = (1 << 0),

15586

+ ANIMATED = (1 << 1),

15587

+ RESIZE = (1 << 2),

15588

+ FONT = (1 << 3)

15589

+} GtkStylePropertyFlags;

15590

+

15591

+int t = 0;

15592

+void

15593

+gtk_css_style_property_register (const char * name,

15594

+ int expected_id,

15595

+ int value_type,

15596

+ int flags,

15597

+ int *parse_value,

15598

+ int *query_value,

15599

+ int *assign_value,

15600

+ int *initial_value)

15601

+{

15602

+ GtkCssStyleProperty *node;

15603

+

15604

+ do

15605

+ {

15606

+ if (__builtin_expect (__extension__ (

15607

+ {

15608

+ int _g_boolean_var_;

15609

+ if (initial_value != ((void *)0))

15610

+ _g_boolean_var_ = 1;

15611

+ else

15612

+ _g_boolean_var_ = 0;

15613

+ _g_boolean_var_;

15614

+ }),

15615

+ 1))

15616

+ ;

15617

+ else

15618

+ g_assertion_message_expr ("Gtk",

15619

+ "gtkcssstylepropertyimpl.c",

15620

+ 85,

15621

+ ((const char*) (__PRETTY_FUNCTION__)),

15622

+ "initial_value != NULL");

15623

+ } while (0);

15624

+

15625

+ do

15626

+ {

15627

+ if (__builtin_expect (__extension__ (

15628

+ {

15629

+ int _g_boolean_var_;

15630

+ if (parse_value != ((void *)0))

15631

+ _g_boolean_var_ = 1;

15632

+ else

15633

+ _g_boolean_var_ = 0;

15634

+ _g_boolean_var_;

15635

+ }),

15636

+ 1))

15637

+ ;

15638

+ else

15639

+ g_assertion_message_expr ("Gtk",

15640

+ "gtkcssstylepropertyimpl.c",

15641

+ 86,

15642

+ ((const char*) (__PRETTY_FUNCTION__)),

15643

+ "parse_value != NULL");

15644

+ } while (0);

15645

+

15646

+ do

15647

+ {

15648

+ if (__builtin_expect (__extension__ (

15649

+ {

15650

+ int _g_boolean_var_;

15651

+ if (value_type == ((int) ((1) << (2)))

15652

+ || query_value != ((void *)0))

15653

+ _g_boolean_var_ = 1;

15654

+ else

15655

+ _g_boolean_var_ = 0;

15656

+ _g_boolean_var_;

15657

+ }),

15658

+ 1))

15659

+ ;

15660

+ else

15661

+ g_assertion_message_expr ("Gtk",

15662

+ "gtkcssstylepropertyimpl.c",

15663

+ 87, ((const char*) (__PRETTY_FUNCTION__)),

15664

+ "value_type == NONE || query_value != NULL");

15665

+ } while (0);

15666

+

15667

+ /* FLAGS is changed in a cond_exec instruction with pr57637. */

15668

+ if (flags == 15)

15669

+ t = 15;

15670

+

15671

+ do

15672

+ {

15673

+ if (__builtin_expect (__extension__ (

15674

+ {

15675

+ int _g_boolean_var_;

15676

+ if (value_type == ((1) << (2))

15677

+ || assign_value != ((void *)0))

15678

+ _g_boolean_var_ = 1;

15679

+ else

15680

+ _g_boolean_var_ = 0;

15681

+ _g_boolean_var_;

15682

+ }),

15683

+ 1))

15684

+ ;

15685

+ else

15686

+ g_assertion_message_expr ("Gtk",

15687

+ "gtkcssstylepropertyimpl.c",

15688

+ 88, ((const char*) (__PRETTY_FUNCTION__)),

15689

+ "value_type == NONE || assign_value != NULL");

15690

+ } while (0);

15691

+

15692

+ node = g_object_new ((_gtk_css_style_property_get_type ()),

15693

+ "value-type", value_type,

15694

+ "affects-size", (flags & RESIZE) ? (0) : (!(0)),

15695

+ "affects-font", (flags & FONT) ? (!(0)) : (0),

15696

+ "animated", (flags & ANIMATED) ? (!(0)) : (0),

15697

+ "inherit", (flags & INHERIT) ? (!(0)) : (0),

15698

+ "initial-value", initial_value,

15699

+ "name", name,

15700

+ ((void *)0));

15701

+

15702

+ node->parse_value = parse_value;

15703

+ node->query_value = query_value;

15704

+ node->assign_value = assign_value;

15705

+

15706

+ do

15707

+ {

15708

+ if (__builtin_expect (__extension__ (

15709

+ {

15710

+ int _g_boolean_var_;

15711

+ if (get_id (node) == expected_id)

15712

+ _g_boolean_var_ = 1;

15713

+ else

15714

+ _g_boolean_var_ = 0;

15715

+ _g_boolean_var_;

15716

+ }),

15717

+ 1))

15718

+ ;

15719

+ else

15720

+ g_assertion_message_expr ("Gtk",

15721

+ "gtkcssstylepropertyimpl.c",

15722

+ 106,

15723

+ ((const char*) (__PRETTY_FUNCTION__)),

15724

+ "get_id (node) == expected_id");

15725

+ } while (0);

15726

+}

15727

+

15728

+int main ()

15729

+{

15730

+ gtk_css_style_property_register ("test", 1, 4, 15, &t, &t, &t, &t);

15731

+

15732

+ if (t != 15)

15733

+ __builtin_abort ();

15734

+ return 0;

15735

+}

15736

Index: gcc/testsuite/gcc.target/powerpc/ppc-target-2.c

15737

===================================================================

15738

--- a/src/gcc/testsuite/gcc.target/powerpc/ppc-target-2.c (.../tags/gcc_4_8_2_release)

15739

+++ b/src/gcc/testsuite/gcc.target/powerpc/ppc-target-2.c (.../branches/gcc-4_8-branch)

15740

@@ -5,8 +5,7 @@

15741

/* { dg-final { scan-assembler-times "fabs" 3 } } */

15742

/* { dg-final { scan-assembler-times "fnabs" 3 } } */

15743

/* { dg-final { scan-assembler-times "fsel" 3 } } */

15744

-/* { dg-final { scan-assembler-times "fcpsgn" 3 } } */

15745

-/* { dg-final { scan-assembler-times "xscpsgndp" 1 } } */

15746

+/* { dg-final { scan-assembler-times "fcpsgn\|xscpsgndp" 4 } } */

15747

15748

/* fabs/fnabs/fsel */

15749

double normal1 (double a, double b) { return __builtin_copysign (a, b); }

15750

Index: gcc/testsuite/gcc.target/powerpc/dfp-builtin-1.c

15751

===================================================================

15752

--- a/src/gcc/testsuite/gcc.target/powerpc/dfp-builtin-1.c (.../tags/gcc_4_8_2_release)

15753

+++ b/src/gcc/testsuite/gcc.target/powerpc/dfp-builtin-1.c (.../branches/gcc-4_8-branch)

15754

@@ -0,0 +1,88 @@

15755

+/* { dg-do compile { target { powerpc*-*-linux* } } } */

15756

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

15757

+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */

15758

+/* { dg-require-effective-target powerpc_vsx_ok } */

15759

+/* { dg-options "-mcpu=power7 -O2" } */

15760

+/* { dg-final { scan-assembler-times "ddedpd " 4 } } */

15761

+/* { dg-final { scan-assembler-times "denbcd " 2 } } */

15762

+/* { dg-final { scan-assembler-times "dxex " 1 } } */

15763

+/* { dg-final { scan-assembler-times "diex " 1 } } */

15764

+/* { dg-final { scan-assembler-times "dscli " 2 } } */

15765

+/* { dg-final { scan-assembler-times "dscri " 2 } } */

15766

+/* { dg-final { scan-assembler-not "bl __builtin" } } */

15767

+/* { dg-final { scan-assembler-not "dctqpq" } } */

15768

+/* { dg-final { scan-assembler-not "drdpq" } } */

15769

+/* { dg-final { scan-assembler-not "stfd" } } */

15770

+/* { dg-final { scan-assembler-not "lfd" } } */

15771

+

15772

+_Decimal64

15773

+do_dedpd_0 (_Decimal64 a)

15774

+{

15775

+ return __builtin_ddedpd (0, a);

15776

+}

15777

+

15778

+_Decimal64

15779

+do_dedpd_1 (_Decimal64 a)

15780

+{

15781

+ return __builtin_ddedpd (1, a);

15782

+}

15783

+

15784

+_Decimal64

15785

+do_dedpd_2 (_Decimal64 a)

15786

+{

15787

+ return __builtin_ddedpd (2, a);

15788

+}

15789

+

15790

+_Decimal64

15791

+do_dedpd_3 (_Decimal64 a)

15792

+{

15793

+ return __builtin_ddedpd (3, a);

15794

+}

15795

+

15796

+_Decimal64

15797

+do_enbcd_0 (_Decimal64 a)

15798

+{

15799

+ return __builtin_denbcd (0, a);

15800

+}

15801

+

15802

+_Decimal64

15803

+do_enbcd_1 (_Decimal64 a)

15804

+{

15805

+ return __builtin_denbcd (1, a);

15806

+}

15807

+

15808

+_Decimal64

15809

+do_xex (_Decimal64 a)

15810

+{

15811

+ return __builtin_dxex (a);

15812

+}

15813

+

15814

+_Decimal64

15815

+do_iex (_Decimal64 a, _Decimal64 b)

15816

+{

15817

+ return __builtin_diex (a, b);

15818

+}

15819

+

15820

+_Decimal64

15821

+do_scli_1 (_Decimal64 a)

15822

+{

15823

+ return __builtin_dscli (a, 1);

15824

+}

15825

+

15826

+_Decimal64

15827

+do_scli_10 (_Decimal64 a)

15828

+{

15829

+ return __builtin_dscli (a, 10);

15830

+}

15831

+

15832

+_Decimal64

15833

+do_scri_1 (_Decimal64 a)

15834

+{

15835

+ return __builtin_dscri (a, 1);

15836

+}

15837

+

15838

+_Decimal64

15839

+do_scri_10 (_Decimal64 a)

15840

+{

15841

+ return __builtin_dscri (a, 10);

15842

+}

15843

Index: gcc/testsuite/gcc.target/powerpc/p8vector-builtin-1.c

15844

===================================================================

15845

--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-1.c (.../tags/gcc_4_8_2_release)

15846

+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-1.c (.../branches/gcc-4_8-branch)

15847

@@ -0,0 +1,65 @@

15848

+/* { dg-do compile { target { powerpc*-*-* } } } */

15849

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

15850

+/* { dg-require-effective-target powerpc_p8vector_ok } */

15851

+/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model -fno-unroll-loops -fno-unroll-all-loops" } */

15852

+

15853

+#ifndef TYPE

15854

+#define TYPE long long

15855

+#endif

15856

+

15857

+#ifndef SIGN_TYPE

15858

+#define SIGN_TYPE signed TYPE

15859

+#endif

15860

+

15861

+#ifndef UNS_TYPE

15862

+#define UNS_TYPE unsigned TYPE

15863

+#endif

15864

+

15865

+typedef vector SIGN_TYPE v_sign;

15866

+typedef vector UNS_TYPE v_uns;

15867

+

15868

+v_sign sign_add (v_sign a, v_sign b)

15869

+{

15870

+ return a + b;

15871

+}

15872

+

15873

+v_sign sign_sub (v_sign a, v_sign b)

15874

+{

15875

+ return a - b;

15876

+}

15877

+

15878

+v_sign sign_shift_left (v_sign a, v_sign b)

15879

+{

15880

+ return a << b;

15881

+}

15882

+

15883

+v_sign sign_shift_right (v_sign a, v_sign b)

15884

+{

15885

+ return a >> b;

15886

+}

15887

+

15888

+v_uns uns_add (v_uns a, v_uns b)

15889

+{

15890

+ return a + b;

15891

+}

15892

+

15893

+v_uns uns_sub (v_uns a, v_uns b)

15894

+{

15895

+ return a - b;

15896

+}

15897

+

15898

+v_uns uns_shift_left (v_uns a, v_uns b)

15899

+{

15900

+ return a << b;

15901

+}

15902

+

15903

+v_uns uns_shift_right (v_uns a, v_uns b)

15904

+{

15905

+ return a >> b;

15906

+}

15907

+

15908

+/* { dg-final { scan-assembler-times "vaddudm" 2 } } */

15909

+/* { dg-final { scan-assembler-times "vsubudm" 2 } } */

15910

+/* { dg-final { scan-assembler-times "vsld" 2 } } */

15911

+/* { dg-final { scan-assembler-times "vsrad" 1 } } */

15912

+/* { dg-final { scan-assembler-times "vsrd" 1 } } */

15913

Index: gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-1.c

15914

===================================================================

15915

--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-1.c (.../tags/gcc_4_8_2_release)

15916

+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-1.c (.../branches/gcc-4_8-branch)

15917

@@ -0,0 +1,200 @@

15918

+/* { dg-do compile { target { powerpc*-*-* } } } */

15919

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

15920

+/* { dg-require-effective-target powerpc_p8vector_ok } */

15921

+/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model -fno-unroll-loops -fno-unroll-all-loops" } */

15922

+

15923

+#ifndef SIZE

15924

+#define SIZE 1024

15925

+#endif

15926

+

15927

+#ifndef ALIGN

15928

+#define ALIGN 32

15929

+#endif

15930

+

15931

+#ifndef TYPE

15932

+#define TYPE long long

15933

+#endif

15934

+

15935

+#ifndef SIGN_TYPE

15936

+#define SIGN_TYPE signed TYPE

15937

+#endif

15938

+

15939

+#ifndef UNS_TYPE

15940

+#define UNS_TYPE unsigned TYPE

15941

+#endif

15942

+

15943

+#define ALIGN_ATTR __attribute__((__aligned__(ALIGN)))

15944

+

15945

+SIGN_TYPE sa[SIZE] ALIGN_ATTR;

15946

+SIGN_TYPE sb[SIZE] ALIGN_ATTR;

15947

+SIGN_TYPE sc[SIZE] ALIGN_ATTR;

15948

+

15949

+UNS_TYPE ua[SIZE] ALIGN_ATTR;

15950

+UNS_TYPE ub[SIZE] ALIGN_ATTR;

15951

+UNS_TYPE uc[SIZE] ALIGN_ATTR;

15952

+

15953

+void

15954

+sign_add (void)

15955

+{

15956

+ unsigned long i;

15957

+

15958

+ for (i = 0; i < SIZE; i++)

15959

+ sa[i] = sb[i] + sc[i];

15960

+}

15961

+

15962

+void

15963

+sign_sub (void)

15964

+{

15965

+ unsigned long i;

15966

+

15967

+ for (i = 0; i < SIZE; i++)

15968

+ sa[i] = sb[i] - sc[i];

15969

+}

15970

+

15971

+void

15972

+sign_shift_left (void)

15973

+{

15974

+ unsigned long i;

15975

+

15976

+ for (i = 0; i < SIZE; i++)

15977

+ sa[i] = sb[i] << sc[i];

15978

+}

15979

+

15980

+void

15981

+sign_shift_right (void)

15982

+{

15983

+ unsigned long i;

15984

+

15985

+ for (i = 0; i < SIZE; i++)

15986

+ sa[i] = sb[i] >> sc[i];

15987

+}

15988

+

15989

+void

15990

+sign_max (void)

15991

+{

15992

+ unsigned long i;

15993

+

15994

+ for (i = 0; i < SIZE; i++)

15995

+ sa[i] = (sb[i] > sc[i]) ? sb[i] : sc[i];

15996

+}

15997

+

15998

+void

15999

+sign_min (void)

16000

+{

16001

+ unsigned long i;

16002

+

16003

+ for (i = 0; i < SIZE; i++)

16004

+ sa[i] = (sb[i] < sc[i]) ? sb[i] : sc[i];

16005

+}

16006

+

16007

+void

16008

+sign_abs (void)

16009

+{

16010

+ unsigned long i;

16011

+

16012

+ for (i = 0; i < SIZE; i++)

16013

+ sa[i] = (sb[i] < 0) ? -sb[i] : sb[i]; /* xor, vsubudm, vmaxsd. */

16014

+}

16015

+

16016

+void

16017

+sign_eq (SIGN_TYPE val1, SIGN_TYPE val2)

16018

+{

16019

+ unsigned long i;

16020

+

16021

+ for (i = 0; i < SIZE; i++)

16022

+ sa[i] = (sb[i] == sc[i]) ? val1 : val2;

16023

+}

16024

+

16025

+void

16026

+sign_lt (SIGN_TYPE val1, SIGN_TYPE val2)

16027

+{

16028

+ unsigned long i;

16029

+

16030

+ for (i = 0; i < SIZE; i++)

16031

+ sa[i] = (sb[i] < sc[i]) ? val1 : val2;

16032

+}

16033

+

16034

+void

16035

+uns_add (void)

16036

+{

16037

+ unsigned long i;

16038

+

16039

+ for (i = 0; i < SIZE; i++)

16040

+ ua[i] = ub[i] + uc[i];

16041

+}

16042

+

16043

+void

16044

+uns_sub (void)

16045

+{

16046

+ unsigned long i;

16047

+

16048

+ for (i = 0; i < SIZE; i++)

16049

+ ua[i] = ub[i] - uc[i];

16050

+}

16051

+

16052

+void

16053

+uns_shift_left (void)

16054

+{

16055

+ unsigned long i;

16056

+

16057

+ for (i = 0; i < SIZE; i++)

16058

+ ua[i] = ub[i] << uc[i];

16059

+}

16060

+

16061

+void

16062

+uns_shift_right (void)

16063

+{

16064

+ unsigned long i;

16065

+

16066

+ for (i = 0; i < SIZE; i++)

16067

+ ua[i] = ub[i] >> uc[i];

16068

+}

16069

+

16070

+void

16071

+uns_max (void)

16072

+{

16073

+ unsigned long i;

16074

+

16075

+ for (i = 0; i < SIZE; i++)

16076

+ ua[i] = (ub[i] > uc[i]) ? ub[i] : uc[i];

16077

+}

16078

+

16079

+void

16080

+uns_min (void)

16081

+{

16082

+ unsigned long i;

16083

+

16084

+ for (i = 0; i < SIZE; i++)

16085

+ ua[i] = (ub[i] < uc[i]) ? ub[i] : uc[i];

16086

+}

16087

+

16088

+void

16089

+uns_eq (UNS_TYPE val1, UNS_TYPE val2)

16090

+{

16091

+ unsigned long i;

16092

+

16093

+ for (i = 0; i < SIZE; i++)

16094

+ ua[i] = (ub[i] == uc[i]) ? val1 : val2;

16095

+}

16096

+

16097

+void

16098

+uns_lt (UNS_TYPE val1, UNS_TYPE val2)

16099

+{

16100

+ unsigned long i;

16101

+

16102

+ for (i = 0; i < SIZE; i++)

16103

+ ua[i] = (ub[i] < uc[i]) ? val1 : val2;

16104

+}

16105

+

16106

+/* { dg-final { scan-assembler-times "\[\t \]vaddudm\[\t \]" 2 } } */

16107

+/* { dg-final { scan-assembler-times "\[\t \]vsubudm\[\t \]" 3 } } */

16108

+/* { dg-final { scan-assembler-times "\[\t \]vmaxsd\[\t \]" 2 } } */

16109

+/* { dg-final { scan-assembler-times "\[\t \]vmaxud\[\t \]" 1 } } */

16110

+/* { dg-final { scan-assembler-times "\[\t \]vminsd\[\t \]" 1 } } */

16111

+/* { dg-final { scan-assembler-times "\[\t \]vminud\[\t \]" 1 } } */

16112

+/* { dg-final { scan-assembler-times "\[\t \]vsld\[\t \]" 2 } } */

16113

+/* { dg-final { scan-assembler-times "\[\t \]vsrad\[\t \]" 1 } } */

16114

+/* { dg-final { scan-assembler-times "\[\t \]vsrd\[\t \]" 1 } } */

16115

+/* { dg-final { scan-assembler-times "\[\t \]vcmpequd\[\t \]" 2 } } */

16116

+/* { dg-final { scan-assembler-times "\[\t \]vcmpgtsd\[\t \]" 1 } } */

16117

+/* { dg-final { scan-assembler-times "\[\t \]vcmpgtud\[\t \]" 1 } } */

16118

Index: gcc/testsuite/gcc.target/powerpc/pr57744.c

16119

===================================================================

16120

--- a/src/gcc/testsuite/gcc.target/powerpc/pr57744.c (.../tags/gcc_4_8_2_release)

16121

+++ b/src/gcc/testsuite/gcc.target/powerpc/pr57744.c (.../branches/gcc-4_8-branch)

16122

@@ -0,0 +1,39 @@

16123

+/* { dg-do run { target { powerpc*-*-* && lp64 } } } */

16124

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

16125

+/* { dg-require-effective-target powerpc_p8vector_ok } */

16126

+/* { dg-options "-mcpu=power8 -O3" } */

16127

+

16128

+void abort (void);

16129

+

16130

+typedef unsigned U_16 __attribute__((mode(TI)));

16131

+

16132

+extern int libat_compare_exchange_16 (U_16 *, U_16 *, U_16, int, int)

16133

+ __attribute__((__noinline__));

16134

+

16135

+/* PR 57744: lqarx/stqcx needs even/odd register pairs. The assembler will

16136

+ complain if the compiler gets an odd/even register pair. Create a function

16137

+ which has the 16 byte compare and exchange instructions, but don't actually

16138

+ execute it, so that we can detect these failures on older machines. */

16139

+

16140

+int

16141

+libat_compare_exchange_16 (U_16 *mptr, U_16 *eptr, U_16 newval,

16142

+ int smodel, int fmodel __attribute__((unused)))

16143

+{

16144

+ if (((smodel) == 0))

16145

+ return __atomic_compare_exchange_n (mptr, eptr, newval, 0, 0, 0);

16146

+ else if (((smodel) != 5))

16147

+ return __atomic_compare_exchange_n (mptr, eptr, newval, 0, 4, 0);

16148

+ else

16149

+ return __atomic_compare_exchange_n (mptr, eptr, newval, 0, 5, 0);

16150

+}

16151

+

16152

+U_16 a = 1, b = 1, c = -2;

16153

+volatile int do_test = 0;

16154

+

16155

+int main (void)

16156

+{

16157

+ if (do_test && !libat_compare_exchange_16 (&a, &b, c, 0, 0))

16158

+ abort ();

16159

+

16160

+ return 0;

16161

+}

16162

Index: gcc/testsuite/gcc.target/powerpc/recip-1.c

16163

===================================================================

16164

--- a/src/gcc/testsuite/gcc.target/powerpc/recip-1.c (.../tags/gcc_4_8_2_release)

16165

+++ b/src/gcc/testsuite/gcc.target/powerpc/recip-1.c (.../branches/gcc-4_8-branch)

16166

@@ -3,8 +3,8 @@

16167

/* { dg-options "-O2 -mrecip -ffast-math -mcpu=power6" } */

16168

/* { dg-final { scan-assembler-times "frsqrte" 2 } } */

16169

/* { dg-final { scan-assembler-times "fmsub" 2 } } */

16170

-/* { dg-final { scan-assembler-times "fmul" 8 } } */

16171

-/* { dg-final { scan-assembler-times "fnmsub" 4 } } */

16172

+/* { dg-final { scan-assembler-times "fmul" 6 } } */

16173

+/* { dg-final { scan-assembler-times "fnmsub" 3 } } */

16174

16175

double

16176

rsqrt_d (double a)

16177

Index: gcc/testsuite/gcc.target/powerpc/darwin-longlong.c

16178

===================================================================

16179

--- a/src/gcc/testsuite/gcc.target/powerpc/darwin-longlong.c (.../tags/gcc_4_8_2_release)

16180

+++ b/src/gcc/testsuite/gcc.target/powerpc/darwin-longlong.c (.../branches/gcc-4_8-branch)

16181

@@ -11,7 +11,11 @@

16182

int i[2];

16183

} ud;

16184

ud.ll = in;

16185

+#ifdef __LITTLE_ENDIAN__

16186

+ return ud.i[1];

16187

+#else

16188

return ud.i[0];

16189

+#endif

16190

}

16191

16192

int main()

16193

Index: gcc/testsuite/gcc.target/powerpc/bool2-p8.c

16194

===================================================================

16195

--- a/src/gcc/testsuite/gcc.target/powerpc/bool2-p8.c (.../tags/gcc_4_8_2_release)

16196

+++ b/src/gcc/testsuite/gcc.target/powerpc/bool2-p8.c (.../branches/gcc-4_8-branch)

16197

@@ -0,0 +1,32 @@

16198

+/* { dg-do compile { target { powerpc*-*-* } } } */

16199

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

16200

+/* { dg-require-effective-target powerpc_p8vector_ok } */

16201

+/* { dg-options "-O2 -mcpu=power8" } */

16202

+/* { dg-final { scan-assembler-not "\[ \t\]and " } } */

16203

+/* { dg-final { scan-assembler-not "\[ \t\]or " } } */

16204

+/* { dg-final { scan-assembler-not "\[ \t\]xor " } } */

16205

+/* { dg-final { scan-assembler-not "\[ \t\]nor " } } */

16206

+/* { dg-final { scan-assembler-not "\[ \t\]eqv " } } */

16207

+/* { dg-final { scan-assembler-not "\[ \t\]andc " } } */

16208

+/* { dg-final { scan-assembler-not "\[ \t\]orc " } } */

16209

+/* { dg-final { scan-assembler-not "\[ \t\]nand " } } */

16210

+/* { dg-final { scan-assembler-not "\[ \t\]vand " } } */

16211

+/* { dg-final { scan-assembler-not "\[ \t\]vandc " } } */

16212

+/* { dg-final { scan-assembler-not "\[ \t\]vor " } } */

16213

+/* { dg-final { scan-assembler-not "\[ \t\]vxor " } } */

16214

+/* { dg-final { scan-assembler-not "\[ \t\]vnor " } } */

16215

+/* { dg-final { scan-assembler "\[ \t\]xxland " } } */

16216

+/* { dg-final { scan-assembler "\[ \t\]xxlor " } } */

16217

+/* { dg-final { scan-assembler "\[ \t\]xxlxor " } } */

16218

+/* { dg-final { scan-assembler "\[ \t\]xxlnor " } } */

16219

+/* { dg-final { scan-assembler "\[ \t\]xxlandc " } } */

16220

+/* { dg-final { scan-assembler "\[ \t\]xxleqv " } } */

16221

+/* { dg-final { scan-assembler "\[ \t\]xxlorc " } } */

16222

+/* { dg-final { scan-assembler "\[ \t\]xxlnand " } } */

16223

+

16224

+#ifndef TYPE

16225

+typedef int v4si __attribute__ ((vector_size (16)));

16226

+#define TYPE v4si

16227

+#endif

16228

+

16229

+#include "bool2.h"

16230

Index: gcc/testsuite/gcc.target/powerpc/mmfpgpr.c

16231

===================================================================

16232

--- a/src/gcc/testsuite/gcc.target/powerpc/mmfpgpr.c (.../tags/gcc_4_8_2_release)

16233

+++ b/src/gcc/testsuite/gcc.target/powerpc/mmfpgpr.c (.../branches/gcc-4_8-branch)

16234

@@ -0,0 +1,22 @@

16235

+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */

16236

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

16237

+/* { dg-require-effective-target powerpc_vsx_ok } */

16238

+/* { dg-options "-O2 -mcpu=power6x -mmfpgpr" } */

16239

+/* { dg-final { scan-assembler "mffgpr" } } */

16240

+/* { dg-final { scan-assembler "mftgpr" } } */

16241

+

16242

+/* Test that we generate the instructions to move between the GPR and FPR

16243

+ registers under power6x. */

16244

+

16245

+extern long return_long (void);

16246

+extern double return_double (void);

16247

+

16248

+double return_double2 (void)

16249

+{

16250

+ return (double) return_long ();

16251

+}

16252

+

16253

+long return_long2 (void)

16254

+{

16255

+ return (long) return_double ();

16256

+}

16257

Index: gcc/testsuite/gcc.target/powerpc/pr60203.c

16258

===================================================================

16259

--- a/src/gcc/testsuite/gcc.target/powerpc/pr60203.c (.../tags/gcc_4_8_2_release)

16260

+++ b/src/gcc/testsuite/gcc.target/powerpc/pr60203.c (.../branches/gcc-4_8-branch)

16261

@@ -0,0 +1,40 @@

16262

+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */

16263

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

16264

+/* { dg-require-effective-target powerpc_p8vector_ok } */

16265

+/* { dg-options "-mcpu=power8 -O3" } */

16266

+

16267

+union u_ld { long double ld; double d[2]; };

16268

+

16269

+long double

16270

+pack (double a, double aa)

16271

+{

16272

+ union u_ld u;

16273

+ u.d[0] = a;

16274

+ u.d[1] = aa;

16275

+ return u.ld;

16276

+}

16277

+

16278

+double

16279

+unpack_0 (long double x)

16280

+{

16281

+ union u_ld u;

16282

+ u.ld = x;

16283

+ return u.d[0];

16284

+}

16285

+

16286

+double

16287

+unpack_1 (long double x)

16288

+{

16289

+ union u_ld u;

16290

+ u.ld = x;

16291

+ return u.d[1];

16292

+}

16293

+

16294

+/* { dg-final { scan-assembler-not "stfd" } } */

16295

+/* { dg-final { scan-assembler-not "lfd" } } */

16296

+/* { dg-final { scan-assembler-not "lxsdx" } } */

16297

+/* { dg-final { scan-assembler-not "stxsdx" } } */

16298

+/* { dg-final { scan-assembler-not "mfvsrd" } } */

16299

+/* { dg-final { scan-assembler-not "mtvsrd" } } */

16300

+

16301

+

16302

Index: gcc/testsuite/gcc.target/powerpc/direct-move-vint1.c

16303

===================================================================

16304

--- a/src/gcc/testsuite/gcc.target/powerpc/direct-move-vint1.c (.../tags/gcc_4_8_2_release)

16305

+++ b/src/gcc/testsuite/gcc.target/powerpc/direct-move-vint1.c (.../branches/gcc-4_8-branch)

16306

@@ -0,0 +1,14 @@

16307

+/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */

16308

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

16309

+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */

16310

+/* { dg-require-effective-target powerpc_p8vector_ok } */

16311

+/* { dg-options "-mcpu=power8 -O2" } */

16312

+/* { dg-final { scan-assembler "mtvsrd" } } */

16313

+/* { dg-final { scan-assembler "mfvsrd" } } */

16314

+

16315

+/* Check code generation for direct move for vector types. */

16316

+

16317

+#define TYPE vector int

16318

+#define VSX_REG_ATTR "wa"

16319

+

16320

+#include "direct-move.h"

16321

Index: gcc/testsuite/gcc.target/powerpc/bool2-av.c

16322

===================================================================

16323

--- a/src/gcc/testsuite/gcc.target/powerpc/bool2-av.c (.../tags/gcc_4_8_2_release)

16324

+++ b/src/gcc/testsuite/gcc.target/powerpc/bool2-av.c (.../branches/gcc-4_8-branch)

16325

@@ -0,0 +1,32 @@

16326

+/* { dg-do compile { target { powerpc*-*-* } } } */

16327

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

16328

+/* { dg-require-effective-target powerpc_altivec_ok } */

16329

+/* { dg-options "-O2 -mcpu=power6 -maltivec" } */

16330

+/* { dg-final { scan-assembler-not "\[ \t\]and " } } */

16331

+/* { dg-final { scan-assembler-not "\[ \t\]or " } } */

16332

+/* { dg-final { scan-assembler-not "\[ \t\]xor " } } */

16333

+/* { dg-final { scan-assembler-not "\[ \t\]nor " } } */

16334

+/* { dg-final { scan-assembler-not "\[ \t\]andc " } } */

16335

+/* { dg-final { scan-assembler-not "\[ \t\]eqv " } } */

16336

+/* { dg-final { scan-assembler-not "\[ \t\]orc " } } */

16337

+/* { dg-final { scan-assembler-not "\[ \t\]nand " } } */

16338

+/* { dg-final { scan-assembler "\[ \t\]vand " } } */

16339

+/* { dg-final { scan-assembler "\[ \t\]vandc " } } */

16340

+/* { dg-final { scan-assembler "\[ \t\]vor " } } */

16341

+/* { dg-final { scan-assembler "\[ \t\]vxor " } } */

16342

+/* { dg-final { scan-assembler "\[ \t\]vnor " } } */

16343

+/* { dg-final { scan-assembler-not "\[ \t\]xxland " } } */

16344

+/* { dg-final { scan-assembler-not "\[ \t\]xxlor " } } */

16345

+/* { dg-final { scan-assembler-not "\[ \t\]xxlxor " } } */

16346

+/* { dg-final { scan-assembler-not "\[ \t\]xxlnor " } } */

16347

+/* { dg-final { scan-assembler-not "\[ \t\]xxlandc " } } */

16348

+/* { dg-final { scan-assembler-not "\[ \t\]xxleqv " } } */

16349

+/* { dg-final { scan-assembler-not "\[ \t\]xxlorc " } } */

16350

+/* { dg-final { scan-assembler-not "\[ \t\]xxlnand " } } */

16351

+

16352

+#ifndef TYPE

16353

+typedef int v4si __attribute__ ((vector_size (16)));

16354

+#define TYPE v4si

16355

+#endif

16356

+

16357

+#include "bool2.h"

16358

Index: gcc/testsuite/gcc.target/powerpc/pr43154.c

16359

===================================================================

16360

--- a/src/gcc/testsuite/gcc.target/powerpc/pr43154.c (.../tags/gcc_4_8_2_release)

16361

+++ b/src/gcc/testsuite/gcc.target/powerpc/pr43154.c (.../branches/gcc-4_8-branch)

16362

@@ -1,5 +1,6 @@

16363

/* { dg-do compile { target { powerpc*-*-* } } } */

16364

/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

16365

+/* { dg-skip-if "" { powerpc*le-*-* } { "*" } { "" } } */

16366

/* { dg-require-effective-target powerpc_vsx_ok } */

16367

/* { dg-options "-O2 -mcpu=power7" } */

16368

16369

Index: gcc/testsuite/gcc.target/powerpc/pr59054.c

16370

===================================================================

16371

--- a/src/gcc/testsuite/gcc.target/powerpc/pr59054.c (.../tags/gcc_4_8_2_release)

16372

+++ b/src/gcc/testsuite/gcc.target/powerpc/pr59054.c (.../branches/gcc-4_8-branch)

16373

@@ -0,0 +1,9 @@

16374

+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */

16375

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

16376

+/* { dg-require-effective-target powerpc_vsx_ok } */

16377

+/* { dg-options "-mcpu=power7 -O0 -m64" } */

16378

+

16379

+long foo (void) { return 0; }

16380

+

16381

+/* { dg-final { scan-assembler-not "xxlor" } } */

16382

+/* { dg-final { scan-assembler-not "stfd" } } */

16383

Index: gcc/testsuite/gcc.target/powerpc/dfp-builtin-2.c

16384

===================================================================

16385

--- a/src/gcc/testsuite/gcc.target/powerpc/dfp-builtin-2.c (.../tags/gcc_4_8_2_release)

16386

+++ b/src/gcc/testsuite/gcc.target/powerpc/dfp-builtin-2.c (.../branches/gcc-4_8-branch)

16387

@@ -0,0 +1,88 @@

16388

+/* { dg-do compile { target { powerpc*-*-linux* } } } */

16389

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

16390

+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */

16391

+/* { dg-require-effective-target powerpc_vsx_ok } */

16392

+/* { dg-options "-mcpu=power7 -O2" } */

16393

+/* { dg-final { scan-assembler-times "ddedpdq " 4 } } */

16394

+/* { dg-final { scan-assembler-times "denbcdq " 2 } } */

16395

+/* { dg-final { scan-assembler-times "dxexq " 1 } } */

16396

+/* { dg-final { scan-assembler-times "diexq " 1 } } */

16397

+/* { dg-final { scan-assembler-times "dscliq " 2 } } */

16398

+/* { dg-final { scan-assembler-times "dscriq " 2 } } */

16399

+/* { dg-final { scan-assembler-not "bl __builtin" } } */

16400

+/* { dg-final { scan-assembler-not "dctqpq" } } */

16401

+/* { dg-final { scan-assembler-not "drdpq" } } */

16402

+/* { dg-final { scan-assembler-not "stfd" } } */

16403

+/* { dg-final { scan-assembler-not "lfd" } } */

16404

+

16405

+_Decimal128

16406

+do_dedpdq_0 (_Decimal128 a)

16407

+{

16408

+ return __builtin_ddedpdq (0, a);

16409

+}

16410

+

16411

+_Decimal128

16412

+do_dedpdq_1 (_Decimal128 a)

16413

+{

16414

+ return __builtin_ddedpdq (1, a);

16415

+}

16416

+

16417

+_Decimal128

16418

+do_dedpdq_2 (_Decimal128 a)

16419

+{

16420

+ return __builtin_ddedpdq (2, a);

16421

+}

16422

+

16423

+_Decimal128

16424

+do_dedpdq_3 (_Decimal128 a)

16425

+{

16426

+ return __builtin_ddedpdq (3, a);

16427

+}

16428

+

16429

+_Decimal128

16430

+do_enbcdq_0 (_Decimal128 a)

16431

+{

16432

+ return __builtin_denbcdq (0, a);

16433

+}

16434

+

16435

+_Decimal128

16436

+do_enbcdq_1 (_Decimal128 a)

16437

+{

16438

+ return __builtin_denbcdq (1, a);

16439

+}

16440

+

16441

+_Decimal128

16442

+do_xexq (_Decimal128 a)

16443

+{

16444

+ return __builtin_dxexq (a);

16445

+}

16446

+

16447

+_Decimal128

16448

+do_iexq (_Decimal128 a, _Decimal128 b)

16449

+{

16450

+ return __builtin_diexq (a, b);

16451

+}

16452

+

16453

+_Decimal128

16454

+do_scliq_1 (_Decimal128 a)

16455

+{

16456

+ return __builtin_dscliq (a, 1);

16457

+}

16458

+

16459

+_Decimal128

16460

+do_scliq_10 (_Decimal128 a)

16461

+{

16462

+ return __builtin_dscliq (a, 10);

16463

+}

16464

+

16465

+_Decimal128

16466

+do_scriq_1 (_Decimal128 a)

16467

+{

16468

+ return __builtin_dscriq (a, 1);

16469

+}

16470

+

16471

+_Decimal128

16472

+do_scriq_10 (_Decimal128 a)

16473

+{

16474

+ return __builtin_dscriq (a, 10);

16475

+}

16476

Index: gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c

16477

===================================================================

16478

--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c (.../tags/gcc_4_8_2_release)

16479

+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c (.../branches/gcc-4_8-branch)

16480

@@ -0,0 +1,204 @@

16481

+/* { dg-do compile { target { powerpc*-*-* } } } */

16482

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

16483

+/* { dg-require-effective-target powerpc_p8vector_ok } */

16484

+/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model -fno-unroll-loops -fno-unroll-all-loops" } */

16485

+

16486

+#include <altivec.h>

16487

+

16488

+typedef vector long long v_sign;

16489

+typedef vector unsigned long long v_uns;

16490

+typedef vector bool long long v_bool;

16491

+

16492

+v_sign sign_add_1 (v_sign a, v_sign b)

16493

+{

16494

+ return __builtin_altivec_vaddudm (a, b);

16495

+}

16496

+

16497

+v_sign sign_add_2 (v_sign a, v_sign b)

16498

+{

16499

+ return vec_add (a, b);

16500

+}

16501

+

16502

+v_sign sign_add_3 (v_sign a, v_sign b)

16503

+{

16504

+ return vec_vaddudm (a, b);

16505

+}

16506

+

16507

+v_sign sign_sub_1 (v_sign a, v_sign b)

16508

+{

16509

+ return __builtin_altivec_vsubudm (a, b);

16510

+}

16511

+

16512

+v_sign sign_sub_2 (v_sign a, v_sign b)

16513

+{

16514

+ return vec_sub (a, b);

16515

+}

16516

+

16517

+

16518

+v_sign sign_sub_3 (v_sign a, v_sign b)

16519

+{

16520

+ return vec_vsubudm (a, b);

16521

+}

16522

+

16523

+v_sign sign_min_1 (v_sign a, v_sign b)

16524

+{

16525

+ return __builtin_altivec_vminsd (a, b);

16526

+}

16527

+

16528

+v_sign sign_min_2 (v_sign a, v_sign b)

16529

+{

16530

+ return vec_min (a, b);

16531

+}

16532

+

16533

+v_sign sign_min_3 (v_sign a, v_sign b)

16534

+{

16535

+ return vec_vminsd (a, b);

16536

+}

16537

+

16538

+v_sign sign_max_1 (v_sign a, v_sign b)

16539

+{

16540

+ return __builtin_altivec_vmaxsd (a, b);

16541

+}

16542

+

16543

+v_sign sign_max_2 (v_sign a, v_sign b)

16544

+{

16545

+ return vec_max (a, b);

16546

+}

16547

+

16548

+v_sign sign_max_3 (v_sign a, v_sign b)

16549

+{

16550

+ return vec_vmaxsd (a, b);

16551

+}

16552

+

16553

+v_sign sign_abs (v_sign a)

16554

+{

16555

+ return vec_abs (a); /* xor, vsubudm, vmaxsd. */

16556

+}

16557

+

16558

+v_bool sign_eq (v_sign a, v_sign b)

16559

+{

16560

+ return vec_cmpeq (a, b);

16561

+}

16562

+

16563

+v_bool sign_lt (v_sign a, v_sign b)

16564

+{

16565

+ return vec_cmplt (a, b);

16566

+}

16567

+

16568

+v_uns uns_add_2 (v_uns a, v_uns b)

16569

+{

16570

+ return vec_add (a, b);

16571

+}

16572

+

16573

+v_uns uns_add_3 (v_uns a, v_uns b)

16574

+{

16575

+ return vec_vaddudm (a, b);

16576

+}

16577

+

16578

+v_uns uns_sub_2 (v_uns a, v_uns b)

16579

+{

16580

+ return vec_sub (a, b);

16581

+}

16582

+

16583

+v_uns uns_sub_3 (v_uns a, v_uns b)

16584

+{

16585

+ return vec_vsubudm (a, b);

16586

+}

16587

+

16588

+v_uns uns_min_2 (v_uns a, v_uns b)

16589

+{

16590

+ return vec_min (a, b);

16591

+}

16592

+

16593

+v_uns uns_min_3 (v_uns a, v_uns b)

16594

+{

16595

+ return vec_vminud (a, b);

16596

+}

16597

+

16598

+v_uns uns_max_2 (v_uns a, v_uns b)

16599

+{

16600

+ return vec_max (a, b);

16601

+}

16602

+

16603

+v_uns uns_max_3 (v_uns a, v_uns b)

16604

+{

16605

+ return vec_vmaxud (a, b);

16606

+}

16607

+

16608

+v_bool uns_eq (v_uns a, v_uns b)

16609

+{

16610

+ return vec_cmpeq (a, b);

16611

+}

16612

+

16613

+v_bool uns_lt (v_uns a, v_uns b)

16614

+{

16615

+ return vec_cmplt (a, b);

16616

+}

16617

+

16618

+v_sign sign_rl_1 (v_sign a, v_sign b)

16619

+{

16620

+ return __builtin_altivec_vrld (a, b);

16621

+}

16622

+

16623

+v_sign sign_rl_2 (v_sign a, v_uns b)

16624

+{

16625

+ return vec_rl (a, b);

16626

+}

16627

+

16628

+v_uns uns_rl_2 (v_uns a, v_uns b)

16629

+{

16630

+ return vec_rl (a, b);

16631

+}

16632

+

16633

+v_sign sign_sl_1 (v_sign a, v_sign b)

16634

+{

16635

+ return __builtin_altivec_vsld (a, b);

16636

+}

16637

+

16638

+v_sign sign_sl_2 (v_sign a, v_uns b)

16639

+{

16640

+ return vec_sl (a, b);

16641

+}

16642

+

16643

+v_sign sign_sl_3 (v_sign a, v_uns b)

16644

+{

16645

+ return vec_vsld (a, b);

16646

+}

16647

+

16648

+v_uns uns_sl_2 (v_uns a, v_uns b)

16649

+{

16650

+ return vec_sl (a, b);

16651

+}

16652

+

16653

+v_uns uns_sl_3 (v_uns a, v_uns b)

16654

+{

16655

+ return vec_vsld (a, b);

16656

+}

16657

+

16658

+v_sign sign_sra_1 (v_sign a, v_sign b)

16659

+{

16660

+ return __builtin_altivec_vsrad (a, b);

16661

+}

16662

+

16663

+v_sign sign_sra_2 (v_sign a, v_uns b)

16664

+{

16665

+ return vec_sra (a, b);

16666

+}

16667

+

16668

+v_sign sign_sra_3 (v_sign a, v_uns b)

16669

+{

16670

+ return vec_vsrad (a, b);

16671

+}

16672

+

16673

+/* { dg-final { scan-assembler-times "vaddudm" 5 } } */

16674

+/* { dg-final { scan-assembler-times "vsubudm" 6 } } */

16675

+/* { dg-final { scan-assembler-times "vmaxsd" 4 } } */

16676

+/* { dg-final { scan-assembler-times "vminsd" 3 } } */

16677

+/* { dg-final { scan-assembler-times "vmaxud" 2 } } */

16678

+/* { dg-final { scan-assembler-times "vminud" 2 } } */

16679

+/* { dg-final { scan-assembler-times "vcmpequd" 2 } } */

16680

+/* { dg-final { scan-assembler-times "vcmpgtsd" 1 } } */

16681

+/* { dg-final { scan-assembler-times "vcmpgtud" 1 } } */

16682

+/* { dg-final { scan-assembler-times "vrld" 3 } } */

16683

+/* { dg-final { scan-assembler-times "vsld" 5 } } */

16684

+/* { dg-final { scan-assembler-times "vsrad" 3 } } */

16685

Index: gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-2.c

16686

===================================================================

16687

--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-2.c (.../tags/gcc_4_8_2_release)

16688

+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-2.c (.../branches/gcc-4_8-branch)

16689

@@ -0,0 +1,30 @@

16690

+/* { dg-do compile { target { powerpc*-*-* } } } */

16691

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

16692

+/* { dg-require-effective-target powerpc_p8vector_ok } */

16693

+/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model" } */

16694

+

16695

+#include <stddef.h>

16696

+

16697

+#ifndef SIZE

16698

+#define SIZE 1024

16699

+#endif

16700

+

16701

+#ifndef ALIGN

16702

+#define ALIGN 32

16703

+#endif

16704

+

16705

+#define ALIGN_ATTR __attribute__((__aligned__(ALIGN)))

16706

+

16707

+long long sign_ll[SIZE] ALIGN_ATTR;

16708

+int sign_i [SIZE] ALIGN_ATTR;

16709

+

16710

+void copy_int_to_long_long (void)

16711

+{

16712

+ size_t i;

16713

+

16714

+ for (i = 0; i < SIZE; i++)

16715

+ sign_ll[i] = sign_i[i];

16716

+}

16717

+

16718

+/* { dg-final { scan-assembler "vupkhsw" } } */

16719

+/* { dg-final { scan-assembler "vupklsw" } } */

16720

Index: gcc/testsuite/gcc.target/powerpc/p8vector-vbpermq.c

16721

===================================================================

16722

--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-vbpermq.c (.../tags/gcc_4_8_2_release)

16723

+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-vbpermq.c (.../branches/gcc-4_8-branch)

16724

@@ -0,0 +1,27 @@

16725

+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */

16726

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

16727

+/* { dg-require-effective-target powerpc_p8vector_ok } */

16728

+/* { dg-options "-O3 -mcpu=power8" } */

16729

+/* { dg-final { scan-assembler "vbpermq" } } */

16730

+/* { dg-final { scan-assembler "mfvsrd" } } */

16731

+/* { dg-final { scan-assembler-not "stfd" } } */

16732

+/* { dg-final { scan-assembler-not "stxvd2x" } } */

16733

+

16734

+#include <altivec.h>

16735

+

16736

+#if __LITTLE_ENDIAN__

16737

+#define OFFSET 1

16738

+#else

16739

+#define OFFSET 0

16740

+#endif

16741

+

16742

+long foos (vector signed char a, vector signed char b)

16743

+{

16744

+ return vec_extract (vec_vbpermq (a, b), OFFSET);

16745

+}

16746

+

16747

+long foou (vector unsigned char a, vector unsigned char b)

16748

+{

16749

+ return vec_extract (vec_vbpermq (a, b), OFFSET);

16750

+}

16751

+

16752

Index: gcc/testsuite/gcc.target/powerpc/bcd-1.c

16753

===================================================================

16754

--- a/src/gcc/testsuite/gcc.target/powerpc/bcd-1.c (.../tags/gcc_4_8_2_release)

16755

+++ b/src/gcc/testsuite/gcc.target/powerpc/bcd-1.c (.../branches/gcc-4_8-branch)

16756

@@ -0,0 +1,27 @@

16757

+/* { dg-do compile { target { powerpc*-*-linux* } } } */

16758

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

16759

+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */

16760

+/* { dg-require-effective-target powerpc_vsx_ok } */

16761

+/* { dg-options "-mcpu=power7 -O2" } */

16762

+/* { dg-final { scan-assembler-times "cdtbcd " 1 } } */

16763

+/* { dg-final { scan-assembler-times "cbcdtd " 1 } } */

16764

+/* { dg-final { scan-assembler-times "addg6s " 1 } } */

16765

+/* { dg-final { scan-assembler-not "bl __builtin" } } */

16766

+

16767

+unsigned int

16768

+to_bcd (unsigned int a)

16769

+{

16770

+ return __builtin_cdtbcd (a);

16771

+}

16772

+

16773

+unsigned int

16774

+from_bcd (unsigned int a)

16775

+{

16776

+ return __builtin_cbcdtd (a);

16777

+}

16778

+

16779

+unsigned int

16780

+bcd_arith (unsigned int a, unsigned int b)

16781

+{

16782

+ return __builtin_addg6s (a, b);

16783

+}

16784

Index: gcc/testsuite/gcc.target/powerpc/pr60735.c

16785

===================================================================

16786

--- a/src/gcc/testsuite/gcc.target/powerpc/pr60735.c (.../tags/gcc_4_8_2_release)

16787

+++ b/src/gcc/testsuite/gcc.target/powerpc/pr60735.c (.../branches/gcc-4_8-branch)

16788

@@ -0,0 +1,11 @@

16789

+/* { dg-do compile } */

16790

+/* { dg-options "-mcpu=8548 -mspe -mabi=spe -O2" } */

16791

+/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */

16792

+

16793

+/* In PR60735, the type _Decimal64 generated an insn not found message. */

16794

+

16795

+void

16796

+pr60735 (_Decimal64 *p, _Decimal64 *q)

16797

+{

16798

+ *p = *q;

16799

+}

16800

Index: gcc/testsuite/gcc.target/powerpc/extend-divide-1.c

16801

===================================================================

16802

--- a/src/gcc/testsuite/gcc.target/powerpc/extend-divide-1.c (.../tags/gcc_4_8_2_release)

16803

+++ b/src/gcc/testsuite/gcc.target/powerpc/extend-divide-1.c (.../branches/gcc-4_8-branch)

16804

@@ -0,0 +1,34 @@

16805

+/* { dg-do compile { target { powerpc*-*-linux* } } } */

16806

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

16807

+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */

16808

+/* { dg-require-effective-target powerpc_vsx_ok } */

16809

+/* { dg-options "-mcpu=power7 -O2" } */

16810

+/* { dg-final { scan-assembler-times "divwe " 1 } } */

16811

+/* { dg-final { scan-assembler-times "divweo " 1 } } */

16812

+/* { dg-final { scan-assembler-times "divweu " 1 } } */

16813

+/* { dg-final { scan-assembler-times "divweuo " 1 } } */

16814

+/* { dg-final { scan-assembler-not "bl __builtin" } } */

16815

+

16816

+int

16817

+div_we (int a, int b)

16818

+{

16819

+ return __builtin_divwe (a, b);

16820

+}

16821

+

16822

+int

16823

+div_weo (int a, int b)

16824

+{

16825

+ return __builtin_divweo (a, b);

16826

+}

16827

+

16828

+unsigned int

16829

+div_weu (unsigned int a, unsigned int b)

16830

+{

16831

+ return __builtin_divweu (a, b);

16832

+}

16833

+

16834

+unsigned int

16835

+div_weuo (unsigned int a, unsigned int b)

16836

+{

16837

+ return __builtin_divweuo (a, b);

16838

+}

16839

Index: gcc/testsuite/gcc.target/powerpc/altivec-perm-3.c

16840

===================================================================

16841

--- a/src/gcc/testsuite/gcc.target/powerpc/altivec-perm-3.c (.../tags/gcc_4_8_2_release)

16842

+++ b/src/gcc/testsuite/gcc.target/powerpc/altivec-perm-3.c (.../branches/gcc-4_8-branch)

16843

@@ -0,0 +1,23 @@

16844

+/* { dg-do compile } */

16845

+/* { dg-require-effective-target powerpc_altivec_ok } */

16846

+/* { dg-skip-if "" { powerpc*le-*-* } { "*" } { "" } } */

16847

+/* { dg-options "-O -maltivec -mno-vsx" } */

16848

+

16849

+typedef unsigned char V __attribute__((vector_size(16)));

16850

+

16851

+V p2(V x, V y)

16852

+{

16853

+ return __builtin_shuffle(x, y,

16854

+ (V){ 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 });

16855

+

16856

+}

16857

+

16858

+V p4(V x, V y)

16859

+{

16860

+ return __builtin_shuffle(x, y,

16861

+ (V){ 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 });

16862

+}

16863

+

16864

+/* { dg-final { scan-assembler-not "vperm" } } */

16865

+/* { dg-final { scan-assembler "vpkuhum" } } */

16866

+/* { dg-final { scan-assembler "vpkuwum" } } */

16867

Index: gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c

16868

===================================================================

16869

--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c (.../tags/gcc_4_8_2_release)

16870

+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c (.../branches/gcc-4_8-branch)

16871

@@ -0,0 +1,85 @@

16872

+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */

16873

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

16874

+/* { dg-require-effective-target powerpc_p8vector_ok } */

16875

+/* { dg-options "-mcpu=power8 -O3 -mvsx-timode" } */

16876

+

16877

+#include <altivec.h>

16878

+

16879

+#ifndef TYPE

16880

+#define TYPE vector __int128_t

16881

+#endif

16882

+

16883

+TYPE

16884

+do_addcuq (TYPE p, TYPE q)

16885

+{

16886

+ return __builtin_vec_vaddcuq (p, q);

16887

+}

16888

+

16889

+TYPE

16890

+do_adduqm (TYPE p, TYPE q)

16891

+{

16892

+ return __builtin_vec_add (p, q);

16893

+}

16894

+

16895

+TYPE

16896

+do_addeuqm (TYPE p, TYPE q, TYPE r)

16897

+{

16898

+ return __builtin_vec_vaddeuqm (p, q, r);

16899

+}

16900

+

16901

+TYPE

16902

+do_addecuq (TYPE p, TYPE q, TYPE r)

16903

+{

16904

+ return __builtin_vec_vaddecuq (p, q, r);

16905

+}

16906

+

16907

+TYPE

16908

+do_subeuqm (TYPE p, TYPE q, TYPE r)

16909

+{

16910

+ return __builtin_vec_vsubeuqm (p, q, r);

16911

+}

16912

+

16913

+TYPE

16914

+do_subecuq (TYPE p, TYPE q, TYPE r)

16915

+{

16916

+ return __builtin_vec_vsubecuq (p, q, r);

16917

+}

16918

+

16919

+TYPE

16920

+do_subcuq (TYPE p, TYPE q)

16921

+{

16922

+ return __builtin_vec_vsubcuq (p, q);

16923

+}

16924

+

16925

+TYPE

16926

+do_subuqm (TYPE p, TYPE q)

16927

+{

16928

+ return __builtin_vec_vsubuqm (p, q);

16929

+}

16930

+

16931

+TYPE

16932

+do_zero (void)

16933

+{

16934

+ return (TYPE) { 0 };

16935

+}

16936

+

16937

+TYPE

16938

+do_minus_one (void)

16939

+{

16940

+ return (TYPE) { -1 };

16941

+}

16942

+

16943

+/* { dg-final { scan-assembler "vaddcuq" } } */

16944

+/* { dg-final { scan-assembler "vadduqm" } } */

16945

+/* { dg-final { scan-assembler "vaddecuq" } } */

16946

+/* { dg-final { scan-assembler "vaddeuqm" } } */

16947

+/* { dg-final { scan-assembler "vsubecuq" } } */

16948

+/* { dg-final { scan-assembler "vsubeuqm" } } */

16949

+/* { dg-final { scan-assembler "vsubcuq" } } */

16950

+/* { dg-final { scan-assembler "vsubuqm" } } */

16951

+/* { dg-final { scan-assembler-not "mtvsrd" } } */

16952

+/* { dg-final { scan-assembler-not "mfvsrd" } } */

16953

+/* { dg-final { scan-assembler-not "ori 2,2,0" } } */

16954

+/* { dg-final { scan-assembler-not "xxpermdi" } } */

16955

+/* { dg-final { scan-assembler-not "stxvd2x" } } */

16956

+/* { dg-final { scan-assembler-not "stxvw4x" } } */

16957

Index: gcc/testsuite/gcc.target/powerpc/pr58673-1.c

16958

===================================================================

16959

--- a/src/gcc/testsuite/gcc.target/powerpc/pr58673-1.c (.../tags/gcc_4_8_2_release)

16960

+++ b/src/gcc/testsuite/gcc.target/powerpc/pr58673-1.c (.../branches/gcc-4_8-branch)

16961

@@ -0,0 +1,78 @@

16962

+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */

16963

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

16964

+/* { dg-require-effective-target powerpc_p8vector_ok } */

16965

+/* { dg-options "-mcpu=power8 -m64 -O1" } */

16966

+

16967

+enum typecode

16968

+{

16969

+ QIcode, QUcode, HIcode, HUcode, SIcode, SUcode, DIcode, DUcode, SFcode,

16970

+ DFcode, XFcode, Pcode, Tcode, LAST_AND_UNUSED_TYPECODE

16971

+};

16972

+enum bytecode_opcode

16973

+{

16974

+ neverneverland, drop, duplicate, over, setstackSI, adjstackSI, constQI,

16975

+ constHI, constSI, constDI, constSF, constDF, constXF, constP, loadQI,

16976

+ loadHI, loadSI, loadDI, loadSF, loadDF, loadXF, loadP, storeQI, storeHI,

16977

+ storeSI, storeDI, storeSF, storeDF, storeXF, storeP, storeBLK, clearBLK,

16978

+ addconstPSI, newlocalSI, localP, argP, convertQIHI, convertHISI,

16979

+ convertSIDI, convertQISI, convertQUHU, convertHUSU, convertSUDU,

16980

+ convertQUSU, convertSFDF, convertDFXF, convertHIQI, convertSIHI,

16981

+ convertDISI, convertSIQI, convertSUQU, convertDFSF, convertXFDF,

16982

+ convertSISF, convertSIDF, convertSIXF, convertSUSF, convertSUDF,

16983

+ convertSUXF, convertDISF, convertDIDF, convertDIXF, convertDUSF,

16984

+ convertDUDF, convertDUXF, convertSFSI, convertDFSI, convertXFSI,

16985

+ convertSFSU, convertDFSU, convertXFSU, convertSFDI, convertDFDI,

16986

+ convertXFDI, convertSFDU, convertDFDU, convertXFDU, convertPSI,

16987

+ convertSIP, convertSIT, convertDIT, convertSFT, convertDFT, convertXFT,

16988

+ convertPT, zxloadBI, sxloadBI, sstoreBI, addSI, addDI, addSF, addDF,

16989

+ addXF, addPSI, subSI, subDI, subSF, subDF, subXF, subPP, mulSI, mulDI,

16990

+ mulSU, mulDU, mulSF, mulDF, mulXF, divSI, divDI, divSU, divDU, divSF,

16991

+ divDF, divXF, modSI, modDI, modSU, modDU, andSI, andDI, iorSI, iorDI,

16992

+ xorSI, xorDI, lshiftSI, lshiftSU, lshiftDI, lshiftDU, rshiftSI, rshiftSU,

16993

+ rshiftDI, rshiftDU, ltSI, ltSU, ltDI, ltDU, ltSF, ltDF, ltXF, ltP, leSI,

16994

+ leSU, leDI, leDU, leSF, leDF, leXF, leP, geSI, geSU, geDI, geDU, geSF,

16995

+ geDF, geXF, geP, gtSI, gtSU, gtDI, gtDU, gtSF, gtDF, gtXF, gtP, eqSI,

16996

+ eqDI, eqSF, eqDF, eqXF, eqP, neSI, neDI, neSF, neDF, neXF, neP, negSI,

16997

+ negDI, negSF, negDF, negXF, notSI, notDI, notT, predecQI, predecHI,

16998

+ predecSI, predecDI, predecP, predecSF, predecDF, predecXF, predecBI,

16999

+ preincQI, preincHI, preincSI, preincDI, preincP, preincSF, preincDF,

17000

+ preincXF, preincBI, postdecQI, postdecHI, postdecSI, postdecDI, postdecP,

17001

+ postdecSF, postdecDF, postdecXF, postdecBI, postincQI, postincHI,

17002

+ postincSI, postincDI, postincP, postincSF, postincDF, postincXF,

17003

+ postincBI, xjumpif, xjumpifnot, jump, jumpP, caseSI, caseSU, caseDI,

17004

+ caseDU, call, returnP, ret, linenote, LAST_AND_UNUSED_OPCODE

17005

+};

17006

+struct binary_operator

17007

+{

17008

+ enum bytecode_opcode opcode;

17009

+ enum typecode arg0;

17010

+};

17011

+static struct conversion_recipe

17012

+{

17013

+ unsigned char *opcodes;

17014

+ int cost;

17015

+}

17016

+conversion_recipe[((int) LAST_AND_UNUSED_TYPECODE)][((int)

17017

+ LAST_AND_UNUSED_TYPECODE)];

17018

+static struct conversion_recipe

17019

+deduce_conversion (from, to)

17020

+ enum typecode from, to;

17021

+{

17022

+ (conversion_recipe[(int) from][(int) to].

17023

+ opcodes ? 0 : (conversion_recipe[(int) from][(int) to] =

17024

+ deduce_conversion (from, to), 0));

17025

+}

17026

+

17027

+void

17028

+bc_expand_binary_operation (optab, resulttype, arg0, arg1)

17029

+ struct binary_operator optab[];

17030

+{

17031

+ int i, besti, cost, bestcost;

17032

+ enum typecode resultcode, arg0code;

17033

+ for (i = 0; optab[i].opcode != -1; ++i)

17034

+ {

17035

+ (conversion_recipe[(int) arg0code][(int) optab[i].arg0].

17036

+ opcodes ? 0 : (conversion_recipe[(int) arg0code][(int) optab[i].arg0] =

17037

+ deduce_conversion (arg0code, optab[i].arg0), 0));

17038

+ }

17039

+}

17040

Index: gcc/testsuite/gcc.target/powerpc/no-r11-1.c

17041

===================================================================

17042

--- a/src/gcc/testsuite/gcc.target/powerpc/no-r11-1.c (.../tags/gcc_4_8_2_release)

17043

+++ b/src/gcc/testsuite/gcc.target/powerpc/no-r11-1.c (.../branches/gcc-4_8-branch)

17044

@@ -1,5 +1,6 @@

17045

/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */

17046

/* { dg-skip-if "" { *-*-darwin* } { "*" } { "" } } */

17047

+/* { dg-skip-if "" { powerpc_elfv2 } { "*" } { "" } } */

17048

/* { dg-options "-O2 -mno-pointers-to-nested-functions" } */

17049

17050

int

17051

Index: gcc/testsuite/gcc.target/powerpc/p8vector-fp.c

17052

===================================================================

17053

--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-fp.c (.../tags/gcc_4_8_2_release)

17054

+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-fp.c (.../branches/gcc-4_8-branch)

17055

@@ -0,0 +1,139 @@

17056

+/* { dg-do compile { target { powerpc*-*-* } } } */

17057

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

17058

+/* { dg-require-effective-target powerpc_p8vector_ok } */

17059

+/* { dg-options "-mcpu=power8 -O2 -mupper-regs-df -mupper-regs-sf -fno-math-errno" } */

17060

+

17061

+float abs_sf (float *p)

17062

+{

17063

+ float f = *p;

17064

+ __asm__ ("# reg %x0" : "+v" (f));

17065

+ return __builtin_fabsf (f);

17066

+}

17067

+

17068

+float nabs_sf (float *p)

17069

+{

17070

+ float f = *p;

17071

+ __asm__ ("# reg %x0" : "+v" (f));

17072

+ return - __builtin_fabsf (f);

17073

+}

17074

+

17075

+float neg_sf (float *p)

17076

+{

17077

+ float f = *p;

17078

+ __asm__ ("# reg %x0" : "+v" (f));

17079

+ return - f;

17080

+}

17081

+

17082

+float add_sf (float *p, float *q)

17083

+{

17084

+ float f1 = *p;

17085

+ float f2 = *q;

17086

+ __asm__ ("# reg %x0, %x1" : "+v" (f1), "+v" (f2));

17087

+ return f1 + f2;

17088

+}

17089

+

17090

+float sub_sf (float *p, float *q)

17091

+{

17092

+ float f1 = *p;

17093

+ float f2 = *q;

17094

+ __asm__ ("# reg %x0, %x1" : "+v" (f1), "+v" (f2));

17095

+ return f1 - f2;

17096

+}

17097

+

17098

+float mul_sf (float *p, float *q)

17099

+{

17100

+ float f1 = *p;

17101

+ float f2 = *q;

17102

+ __asm__ ("# reg %x0, %x1" : "+v" (f1), "+v" (f2));

17103

+ return f1 * f2;

17104

+}

17105

+

17106

+float div_sf (float *p, float *q)

17107

+{

17108

+ float f1 = *p;

17109

+ float f2 = *q;

17110

+ __asm__ ("# reg %x0, %x1" : "+v" (f1), "+v" (f2));

17111

+ return f1 / f2;

17112

+}

17113

+

17114

+float sqrt_sf (float *p)

17115

+{

17116

+ float f = *p;

17117

+ __asm__ ("# reg %x0" : "+v" (f));

17118

+ return __builtin_sqrtf (f);

17119

+}

17120

+

17121

+

17122

+double abs_df (double *p)

17123

+{

17124

+ double d = *p;

17125

+ __asm__ ("# reg %x0" : "+v" (d));

17126

+ return __builtin_fabs (d);

17127

+}

17128

+

17129

+double nabs_df (double *p)

17130

+{

17131

+ double d = *p;

17132

+ __asm__ ("# reg %x0" : "+v" (d));

17133

+ return - __builtin_fabs (d);

17134

+}

17135

+

17136

+double neg_df (double *p)

17137

+{

17138

+ double d = *p;

17139

+ __asm__ ("# reg %x0" : "+v" (d));

17140

+ return - d;

17141

+}

17142

+

17143

+double add_df (double *p, double *q)

17144

+{

17145

+ double d1 = *p;

17146

+ double d2 = *q;

17147

+ __asm__ ("# reg %x0, %x1" : "+v" (d1), "+v" (d2));

17148

+ return d1 + d2;

17149

+}

17150

+

17151

+double sub_df (double *p, double *q)

17152

+{

17153

+ double d1 = *p;

17154

+ double d2 = *q;

17155

+ __asm__ ("# reg %x0, %x1" : "+v" (d1), "+v" (d2));

17156

+ return d1 - d2;

17157

+}

17158

+

17159

+double mul_df (double *p, double *q)

17160

+{

17161

+ double d1 = *p;

17162

+ double d2 = *q;

17163

+ __asm__ ("# reg %x0, %x1" : "+v" (d1), "+v" (d2));

17164

+ return d1 * d2;

17165

+}

17166

+

17167

+double div_df (double *p, double *q)

17168

+{

17169

+ double d1 = *p;

17170

+ double d2 = *q;

17171

+ __asm__ ("# reg %x0, %x1" : "+v" (d1), "+v" (d2));

17172

+ return d1 / d2;

17173

+}

17174

+

17175

+double sqrt_df (float *p)

17176

+{

17177

+ double d = *p;

17178

+ __asm__ ("# reg %x0" : "+v" (d));

17179

+ return __builtin_sqrt (d);

17180

+}

17181

+

17182

+/* { dg-final { scan-assembler "xsabsdp" } } */

17183

+/* { dg-final { scan-assembler "xsadddp" } } */

17184

+/* { dg-final { scan-assembler "xsaddsp" } } */

17185

+/* { dg-final { scan-assembler "xsdivdp" } } */

17186

+/* { dg-final { scan-assembler "xsdivsp" } } */

17187

+/* { dg-final { scan-assembler "xsmuldp" } } */

17188

+/* { dg-final { scan-assembler "xsmulsp" } } */

17189

+/* { dg-final { scan-assembler "xsnabsdp" } } */

17190

+/* { dg-final { scan-assembler "xsnegdp" } } */

17191

+/* { dg-final { scan-assembler "xssqrtdp" } } */

17192

+/* { dg-final { scan-assembler "xssqrtsp" } } */

17193

+/* { dg-final { scan-assembler "xssubdp" } } */

17194

+/* { dg-final { scan-assembler "xssubsp" } } */

17195

Index: gcc/testsuite/gcc.target/powerpc/direct-move-vint2.c

17196

===================================================================

17197

--- a/src/gcc/testsuite/gcc.target/powerpc/direct-move-vint2.c (.../tags/gcc_4_8_2_release)

17198

+++ b/src/gcc/testsuite/gcc.target/powerpc/direct-move-vint2.c (.../branches/gcc-4_8-branch)

17199

@@ -0,0 +1,13 @@

17200

+/* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */

17201

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

17202

+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */

17203

+/* { dg-require-effective-target p8vector_hw } */

17204

+/* { dg-options "-mcpu=power8 -O2" } */

17205

+

17206

+/* Check whether we get the right bits for direct move at runtime. */

17207

+

17208

+#define TYPE vector int

17209

+#define DO_MAIN

17210

+#define VSX_REG_ATTR "wa"

17211

+

17212

+#include "direct-move.h"

17213

Index: gcc/testsuite/gcc.target/powerpc/bool3-p7.c

17214

===================================================================

17215

--- a/src/gcc/testsuite/gcc.target/powerpc/bool3-p7.c (.../tags/gcc_4_8_2_release)

17216

+++ b/src/gcc/testsuite/gcc.target/powerpc/bool3-p7.c (.../branches/gcc-4_8-branch)

17217

@@ -0,0 +1,37 @@

17218

+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */

17219

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

17220

+/* { dg-require-effective-target powerpc_vsx_ok } */

17221

+/* { dg-options "-O2 -mcpu=power7" } */

17222

+/* { dg-final { scan-assembler "\[ \t\]and " } } */

17223

+/* { dg-final { scan-assembler "\[ \t\]or " } } */

17224

+/* { dg-final { scan-assembler "\[ \t\]xor " } } */

17225

+/* { dg-final { scan-assembler "\[ \t\]nor " } } */

17226

+/* { dg-final { scan-assembler "\[ \t\]andc " } } */

17227

+/* { dg-final { scan-assembler-not "\[ \t\]vand " } } */

17228

+/* { dg-final { scan-assembler-not "\[ \t\]vandc " } } */

17229

+/* { dg-final { scan-assembler-not "\[ \t\]vor " } } */

17230

+/* { dg-final { scan-assembler-not "\[ \t\]vxor " } } */

17231

+/* { dg-final { scan-assembler-not "\[ \t\]vnor " } } */

17232

+/* { dg-final { scan-assembler-not "\[ \t\]xxland " } } */

17233

+/* { dg-final { scan-assembler-not "\[ \t\]xxlor " } } */

17234

+/* { dg-final { scan-assembler-not "\[ \t\]xxlxor " } } */

17235

+/* { dg-final { scan-assembler-not "\[ \t\]xxlnor " } } */

17236

+/* { dg-final { scan-assembler-not "\[ \t\]xxlandc " } } */

17237

+/* { dg-final { scan-assembler-not "\[ \t\]xxleqv " } } */

17238

+/* { dg-final { scan-assembler-not "\[ \t\]xxlorc " } } */

17239

+/* { dg-final { scan-assembler-not "\[ \t\]xxlnand " } } */

17240

+

17241

+/* On power7, for 128-bit types, ORC/ANDC/EQV might not show up, since the

17242

+ vector unit doesn't support these, so the appropriate combine patterns may

17243

+ not be generated. */

17244

+

17245

+#ifndef TYPE

17246

+#ifdef _ARCH_PPC64

17247

+#define TYPE __int128_t

17248

+#else

17249

+typedef int v4si __attribute__ ((vector_size (16)));

17250

+#define TYPE v4si

17251

+#endif

17252

+#endif

17253

+

17254

+#include "bool3.h"

17255

Index: gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c

17256

===================================================================

17257

--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c (.../tags/gcc_4_8_2_release)

17258

+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c (.../branches/gcc-4_8-branch)

17259

@@ -0,0 +1,104 @@

17260

+/* { dg-do compile { target { powerpc*-*-* } } } */

17261

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

17262

+/* { dg-require-effective-target powerpc_p8vector_ok } */

17263

+/* { dg-options "-mcpu=power8 -O3 -ftree-vectorize -fvect-cost-model" } */

17264

+

17265

+#include <altivec.h>

17266

+

17267

+typedef vector long long vll_sign;

17268

+typedef vector unsigned long long vll_uns;

17269

+typedef vector bool long long vll_bool;

17270

+

17271

+typedef vector int vi_sign;

17272

+typedef vector unsigned int vi_uns;

17273

+typedef vector bool int vi_bool;

17274

+

17275

+typedef vector short vs_sign;

17276

+typedef vector unsigned short vs_uns;

17277

+typedef vector bool short vs_bool;

17278

+

17279

+typedef vector signed char vc_sign;

17280

+typedef vector unsigned char vc_uns;

17281

+typedef vector bool char vc_bool;

17282

+

17283

+

17284

+vi_sign vi_pack_1 (vll_sign a, vll_sign b)

17285

+{

17286

+ return __builtin_altivec_vpkudum (a, b);

17287

+}

17288

+

17289

+vi_sign vi_pack_2 (vll_sign a, vll_sign b)

17290

+{

17291

+ return vec_pack (a, b);

17292

+}

17293

+

17294

+vi_sign vi_pack_3 (vll_sign a, vll_sign b)

17295

+{

17296

+ return vec_vpkudum (a, b);

17297

+}

17298

+

17299

+vs_sign vs_pack_1 (vi_sign a, vi_sign b)

17300

+{

17301

+ return __builtin_altivec_vpkuwum (a, b);

17302

+}

17303

+

17304

+vs_sign vs_pack_2 (vi_sign a, vi_sign b)

17305

+{

17306

+ return vec_pack (a, b);

17307

+}

17308

+

17309

+vs_sign vs_pack_3 (vi_sign a, vi_sign b)

17310

+{

17311

+ return vec_vpkuwum (a, b);

17312

+}

17313

+

17314

+vc_sign vc_pack_1 (vs_sign a, vs_sign b)

17315

+{

17316

+ return __builtin_altivec_vpkuhum (a, b);

17317

+}

17318

+

17319

+vc_sign vc_pack_2 (vs_sign a, vs_sign b)

17320

+{

17321

+ return vec_pack (a, b);

17322

+}

17323

+

17324

+vc_sign vc_pack_3 (vs_sign a, vs_sign b)

17325

+{

17326

+ return vec_vpkuhum (a, b);

17327

+}

17328

+

17329

+vll_sign vll_unpack_hi_1 (vi_sign a)

17330

+{

17331

+ return __builtin_altivec_vupkhsw (a);

17332

+}

17333

+

17334

+vll_sign vll_unpack_hi_2 (vi_sign a)

17335

+{

17336

+ return vec_unpackh (a);

17337

+}

17338

+

17339

+vll_sign vll_unpack_hi_3 (vi_sign a)

17340

+{

17341

+ return __builtin_vec_vupkhsw (a);

17342

+}

17343

+

17344

+vll_sign vll_unpack_lo_1 (vi_sign a)

17345

+{

17346

+ return vec_vupklsw (a);

17347

+}

17348

+

17349

+vll_sign vll_unpack_lo_2 (vi_sign a)

17350

+{

17351

+ return vec_unpackl (a);

17352

+}

17353

+

17354

+vll_sign vll_unpack_lo_3 (vi_sign a)

17355

+{

17356

+ return vec_vupklsw (a);

17357

+}

17358

+

17359

+/* { dg-final { scan-assembler-times "vpkudum" 3 } } */

17360

+/* { dg-final { scan-assembler-times "vpkuwum" 3 } } */

17361

+/* { dg-final { scan-assembler-times "vpkuhum" 3 } } */

17362

+/* { dg-final { scan-assembler-times "vupklsw" 3 } } */

17363

+/* { dg-final { scan-assembler-times "vupkhsw" 3 } } */

17364

Index: gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-3.c

17365

===================================================================

17366

--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-3.c (.../tags/gcc_4_8_2_release)

17367

+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-3.c (.../branches/gcc-4_8-branch)

17368

@@ -0,0 +1,29 @@

17369

+/* { dg-do compile { target { powerpc*-*-* } } } */

17370

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

17371

+/* { dg-require-effective-target powerpc_p8vector_ok } */

17372

+/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model" } */

17373

+

17374

+#include <stddef.h>

17375

+

17376

+#ifndef SIZE

17377

+#define SIZE 1024

17378

+#endif

17379

+

17380

+#ifndef ALIGN

17381

+#define ALIGN 32

17382

+#endif

17383

+

17384

+#define ALIGN_ATTR __attribute__((__aligned__(ALIGN)))

17385

+

17386

+long long sign_ll[SIZE] ALIGN_ATTR;

17387

+int sign_i [SIZE] ALIGN_ATTR;

17388

+

17389

+void copy_long_long_to_int (void)

17390

+{

17391

+ size_t i;

17392

+

17393

+ for (i = 0; i < SIZE; i++)

17394

+ sign_i[i] = sign_ll[i];

17395

+}

17396

+

17397

+/* { dg-final { scan-assembler "vpkudum" } } */

17398

Index: gcc/testsuite/gcc.target/powerpc/direct-move.h

17399

===================================================================

17400

--- a/src/gcc/testsuite/gcc.target/powerpc/direct-move.h (.../tags/gcc_4_8_2_release)

17401

+++ b/src/gcc/testsuite/gcc.target/powerpc/direct-move.h (.../branches/gcc-4_8-branch)

17402

@@ -0,0 +1,188 @@

17403

+/* Test functions for direct move support. */

17404

+

17405

+#include <math.h>

17406

+extern void abort (void);

17407

+

17408

+#ifndef VSX_REG_ATTR

17409

+#define VSX_REG_ATTR "wa"

17410

+#endif

17411

+

17412

+void __attribute__((__noinline__))

17413

+copy (TYPE *a, TYPE *b)

17414

+{

17415

+ *b = *a;

17416

+}

17417

+

17418

+#ifndef NO_GPR

17419

+void __attribute__((__noinline__))

17420

+load_gpr (TYPE *a, TYPE *b)

17421

+{

17422

+ TYPE c = *a;

17423

+ __asm__ ("# gpr, reg = %0" : "+b" (c));

17424

+ *b = c;

17425

+}

17426

+#endif

17427

+

17428

+#ifndef NO_FPR

17429

+void __attribute__((__noinline__))

17430

+load_fpr (TYPE *a, TYPE *b)

17431

+{

17432

+ TYPE c = *a;

17433

+ __asm__ ("# fpr, reg = %0" : "+d" (c));

17434

+ *b = c;

17435

+}

17436

+#endif

17437

+

17438

+#ifndef NO_ALTIVEC

17439

+void __attribute__((__noinline__))

17440

+load_altivec (TYPE *a, TYPE *b)

17441

+{

17442

+ TYPE c = *a;

17443

+ __asm__ ("# altivec, reg = %0" : "+v" (c));

17444

+ *b = c;

17445

+}

17446

+#endif

17447

+

17448

+#ifndef NO_VSX

17449

+void __attribute__((__noinline__))

17450

+load_vsx (TYPE *a, TYPE *b)

17451

+{

17452

+ TYPE c = *a;

17453

+ __asm__ ("# vsx, reg = %x0" : "+" VSX_REG_ATTR (c));

17454

+ *b = c;

17455

+}

17456

+#endif

17457

+

17458

+#ifndef NO_GPR_TO_VSX

17459

+void __attribute__((__noinline__))

17460

+load_gpr_to_vsx (TYPE *a, TYPE *b)

17461

+{

17462

+ TYPE c = *a;

17463

+ TYPE d;

17464

+ __asm__ ("# gpr, reg = %0" : "+b" (c));

17465

+ d = c;

17466

+ __asm__ ("# vsx, reg = %x0" : "+" VSX_REG_ATTR (d));

17467

+ *b = d;

17468

+}

17469

+#endif

17470

+

17471

+#ifndef NO_VSX_TO_GPR

17472

+void __attribute__((__noinline__))

17473

+load_vsx_to_gpr (TYPE *a, TYPE *b)

17474

+{

17475

+ TYPE c = *a;

17476

+ TYPE d;

17477

+ __asm__ ("# vsx, reg = %x0" : "+" VSX_REG_ATTR (c));

17478

+ d = c;

17479

+ __asm__ ("# gpr, reg = %0" : "+b" (d));

17480

+ *b = d;

17481

+}

17482

+#endif

17483

+

17484

+#ifdef DO_MAIN

17485

+typedef void (fn_type (TYPE *, TYPE *));

17486

+

17487

+struct test_struct {

17488

+ fn_type *func;

17489

+ const char *name;

17490

+};

17491

+

17492

+const struct test_struct test_functions[] = {

17493

+ { copy, "copy" },

17494

+#ifndef NO_GPR

17495

+ { load_gpr, "load_gpr" },

17496

+#endif

17497

+#ifndef NO_FPR

17498

+ { load_fpr, "load_fpr" },

17499

+#endif

17500

+#ifndef NO_ALTIVEC

17501

+ { load_altivec, "load_altivec" },

17502

+#endif

17503

+#ifndef NO_VSX

17504

+ { load_vsx, "load_vsx" },

17505

+#endif

17506

+#ifndef NO_GPR_TO_VSX

17507

+ { load_gpr_to_vsx, "load_gpr_to_vsx" },

17508

+#endif

17509

+#ifndef NO_VSX_TO_GPR

17510

+ { load_vsx_to_gpr, "load_vsx_to_gpr" },

17511

+#endif

17512

+};

17513

+

17514

+/* Test a given value for each of the functions. */

17515

+void __attribute__((__noinline__))

17516

+test_value (TYPE a)

17517

+{

17518

+ long i;

17519

+

17520

+ for (i = 0; i < sizeof (test_functions) / sizeof (test_functions[0]); i++)

17521

+ {

17522

+ TYPE b;

17523

+

17524

+ test_functions[i].func (&a, &b);

17525

+ if (memcmp ((void *)&a, (void *)&b, sizeof (TYPE)) != 0)

17526

+ abort ();

17527

+ }

17528

+}

17529

+

17530

+/* Main program. */

17531

+int

17532

+main (void)

17533

+{

17534

+ long i,j;

17535

+ union {

17536

+ TYPE value;

17537

+ unsigned char bytes[sizeof (TYPE)];

17538

+ } u;

17539

+

17540

+#if IS_INT

17541

+ TYPE value = (TYPE)-5;

17542

+ for (i = 0; i < 12; i++)

17543

+ {

17544

+ test_value (value);

17545

+ value++;

17546

+ }

17547

+

17548

+ for (i = 0; i < 8*sizeof (TYPE); i++)

17549

+ test_value (((TYPE)1) << i);

17550

+

17551

+#elif IS_UNS

17552

+ TYPE value = (TYPE)0;

17553

+ for (i = 0; i < 10; i++)

17554

+ {

17555

+ test_value (value);

17556

+ test_value (~ value);

17557

+ value++;

17558

+ }

17559

+

17560

+ for (i = 0; i < 8*sizeof (TYPE); i++)

17561

+ test_value (((TYPE)1) << i);

17562

+

17563

+#elif IS_FLOAT

17564

+ TYPE value = (TYPE)-5;

17565

+ for (i = 0; i < 12; i++)

17566

+ {

17567

+ test_value (value);

17568

+ value++;

17569

+ }

17570

+

17571

+ test_value ((TYPE)3.1415926535);

17572

+ test_value ((TYPE)1.23456);

17573

+ test_value ((TYPE)(-0.0));

17574

+ test_value ((TYPE)NAN);

17575

+ test_value ((TYPE)+INFINITY);

17576

+ test_value ((TYPE)-INFINITY);

17577

+#else

17578

+

17579

+ for (j = 0; j < 10; j++)

17580

+ {

17581

+ for (i = 0; i < sizeof (TYPE); i++)

17582

+ u.bytes[i] = (unsigned char) (random () >> 4);

17583

+

17584

+ test_value (u.value);

17585

+ }

17586

+#endif

17587

+

17588

+ return 0;

17589

+}

17590

+#endif

17591

Index: gcc/testsuite/gcc.target/powerpc/sd-vsx.c

17592

===================================================================

17593

--- a/src/gcc/testsuite/gcc.target/powerpc/sd-vsx.c (.../tags/gcc_4_8_2_release)

17594

+++ b/src/gcc/testsuite/gcc.target/powerpc/sd-vsx.c (.../branches/gcc-4_8-branch)

17595

@@ -0,0 +1,20 @@

17596

+/* { dg-do compile { target { powerpc*-*-* } } } */

17597

+/* { dg-skip-if "" { powerpc*-*-darwin* powerpc-ibm-aix* } { "*" } { "" } } */

17598

+/* { dg-require-effective-target powerpc_vsx_ok } */

17599

+/* { dg-options "-O2 -mcpu=power7 -mhard-dfp" } */

17600

+/* { dg-final { scan-assembler-times "lfiwzx" 2 } } */

17601

+/* { dg-final { scan-assembler-times "stfiwx" 1 } } */

17602

+/* { dg-final { scan-assembler-not "lfd" } } */

17603

+/* { dg-final { scan-assembler-not "stfd" } } */

17604

+/* { dg-final { scan-assembler-times "dctdp" 2 } } */

17605

+/* { dg-final { scan-assembler-times "dadd" 1 } } */

17606

+/* { dg-final { scan-assembler-times "drsp" 1 } } */

17607

+

17608

+/* Test that power7 can directly load/store SDmode variables without using a

17609

+ bounce buffer. */

17610

+_Decimal32 a;

17611

+

17612

+void inc_dec32 (void)

17613

+{

17614

+ a += (_Decimal32) 1.0;

17615

+}

17616

Index: gcc/testsuite/gcc.target/powerpc/bcd-2.c

17617

===================================================================

17618

--- a/src/gcc/testsuite/gcc.target/powerpc/bcd-2.c (.../tags/gcc_4_8_2_release)

17619

+++ b/src/gcc/testsuite/gcc.target/powerpc/bcd-2.c (.../branches/gcc-4_8-branch)

17620

@@ -0,0 +1,44 @@

17621

+/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */

17622

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

17623

+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */

17624

+/* { dg-require-effective-target powerpc_p8vector_ok } */

17625

+/* { dg-options "-mcpu=power8 -O2" } */

17626

+/* { dg-final { scan-assembler-times "bcdadd\[.\] " 2 } } */

17627

+/* { dg-final { scan-assembler-times "bcdsub\[.\] " 2 } } */

17628

+/* { dg-final { scan-assembler-not "bl __builtin" } } */

17629

+/* { dg-final { scan-assembler-not "mtvsr" } } */

17630

+/* { dg-final { scan-assembler-not "mfvsr" } } */

17631

+/* { dg-final { scan-assembler-not "lvx" } } */

17632

+/* { dg-final { scan-assembler-not "lxvw4x" } } */

17633

+/* { dg-final { scan-assembler-not "lxvd2x" } } */

17634

+/* { dg-final { scan-assembler-not "stvx" } } */

17635

+/* { dg-final { scan-assembler-not "stxvw4x" } } */

17636

+/* { dg-final { scan-assembler-not "stxvd2x" } } */

17637

+

17638

+typedef __int128_t __attribute__((__vector_size__(16))) vector_128_t;

17639

+typedef __int128_t scalar_128_t;

17640

+typedef unsigned long long scalar_64_t;

17641

+

17642

+vector_128_t

17643

+do_add_0 (vector_128_t a, vector_128_t b)

17644

+{

17645

+ return __builtin_bcdadd (a, b, 0);

17646

+}

17647

+

17648

+vector_128_t

17649

+do_add_1 (vector_128_t a, vector_128_t b)

17650

+{

17651

+ return __builtin_bcdadd (a, b, 1);

17652

+}

17653

+

17654

+vector_128_t

17655

+do_sub_0 (vector_128_t a, vector_128_t b)

17656

+{

17657

+ return __builtin_bcdsub (a, b, 0);

17658

+}

17659

+

17660

+vector_128_t

17661

+do_sub_1 (vector_128_t a, vector_128_t b)

17662

+{

17663

+ return __builtin_bcdsub (a, b, 1);

17664

+}

17665

Index: gcc/testsuite/gcc.target/powerpc/extend-divide-2.c

17666

===================================================================

17667

--- a/src/gcc/testsuite/gcc.target/powerpc/extend-divide-2.c (.../tags/gcc_4_8_2_release)

17668

+++ b/src/gcc/testsuite/gcc.target/powerpc/extend-divide-2.c (.../branches/gcc-4_8-branch)

17669

@@ -0,0 +1,34 @@

17670

+/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */

17671

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

17672

+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */

17673

+/* { dg-require-effective-target powerpc_vsx_ok } */

17674

+/* { dg-options "-mcpu=power7 -O2" } */

17675

+/* { dg-final { scan-assembler-times "divde " 1 } } */

17676

+/* { dg-final { scan-assembler-times "divdeo " 1 } } */

17677

+/* { dg-final { scan-assembler-times "divdeu " 1 } } */

17678

+/* { dg-final { scan-assembler-times "divdeuo " 1 } } */

17679

+/* { dg-final { scan-assembler-not "bl __builtin" } } */

17680

+

17681

+long

17682

+div_de (long a, long b)

17683

+{

17684

+ return __builtin_divde (a, b);

17685

+}

17686

+

17687

+long

17688

+div_deo (long a, long b)

17689

+{

17690

+ return __builtin_divdeo (a, b);

17691

+}

17692

+

17693

+unsigned long

17694

+div_deu (unsigned long a, unsigned long b)

17695

+{

17696

+ return __builtin_divdeu (a, b);

17697

+}

17698

+

17699

+unsigned long

17700

+div_deuo (unsigned long a, unsigned long b)

17701

+{

17702

+ return __builtin_divdeuo (a, b);

17703

+}

17704

Index: gcc/testsuite/gcc.target/powerpc/p8vector-int128-2.c

17705

===================================================================

17706

--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-int128-2.c (.../tags/gcc_4_8_2_release)

17707

+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-int128-2.c (.../branches/gcc-4_8-branch)

17708

@@ -0,0 +1,177 @@

17709

+/* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */

17710

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

17711

+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */

17712

+/* { dg-require-effective-target p8vector_hw } */

17713

+/* { dg-options "-mcpu=power8 -O2" } */

17714

+

17715

+#include <stddef.h>

17716

+#include <stdlib.h>

17717

+#include <altivec.h>

17718

+

17719

+#ifdef DEBUG

17720

+#include <stdio.h>

17721

+#define UNUSED

17722

+

17723

+#ifdef __LITTLE_ENDIAN__

17724

+#define HI_WORD 1

17725

+#define LO_WORD 0

17726

+#else

17727

+#define HI_WORD 0

17728

+#define LO_WORD 1

17729

+#endif

17730

+

17731

+#else

17732

+#define UNUSED __attribute__((__unused__))

17733

+#endif

17734

+

17735

+#ifndef S_TYPE

17736

+#define S_TYPE __uint128_t

17737

+#endif

17738

+

17739

+#ifndef V_TYPE

17740

+#define V_TYPE vector S_TYPE

17741

+#endif

17742

+

17743

+static int compare (S_TYPE, V_TYPE, const char *, const char *)

17744

+ __attribute__((__noinline__));

17745

+

17746

+static int

17747

+compare (S_TYPE scalar,

17748

+ V_TYPE vect,

17749

+ const char *nl UNUSED,

17750

+ const char *which UNUSED)

17751

+{

17752

+ unsigned long scalar_lo = (unsigned long) scalar;

17753

+ unsigned long scalar_hi = (unsigned long) (scalar >> 64);

17754

+ unsigned long vect_lo;

17755

+ unsigned long vect_hi;

17756

+ vector long long tmp;

17757

+ int ret;

17758

+

17759

+ __asm__ ("mfvsrd %0,%x3\n\t"

17760

+ "xxpermdi %x2,%x3,%x3,3\n\t"

17761

+ "mfvsrd %1,%x2"

17762

+ : "=r" (vect_hi),

17763

+ "=r" (vect_lo),

17764

+ "=wa" (tmp)

17765

+ : "wa" (vect));

17766

+

17767

+ ret = (scalar_lo != vect_lo) || (scalar_hi != vect_hi);

17768

+

17769

+#ifdef DEBUG

17770

+ printf ("%s%s: 0x%.16lx %.16lx %s 0x%.16lx %.16lx\n",

17771

+ nl, which,

17772

+ scalar_hi, scalar_lo,

17773

+ (ret) ? "!=" : "==",

17774

+ vect_hi, vect_lo);

17775

+

17776

+ fflush (stdout);

17777

+#endif

17778

+

17779

+ return ret;

17780

+}

17781

+

17782

+static void convert_via_mem (V_TYPE *, S_TYPE *)

17783

+ __attribute__((__noinline__));

17784

+

17785

+static void

17786

+convert_via_mem (V_TYPE *v, S_TYPE *s)

17787

+{

17788

+ *v = (V_TYPE) { *s };

17789

+ __asm__ volatile ("nop"

17790

+ : "+m" (*s), "+m" (*v)

17791

+ :

17792

+ : "memory");

17793

+

17794

+}

17795

+

17796

+

17797

+/* Check if vadduqm returns the same values as normal 128-bit add. */

17798

+

17799

+/* Values to add together. */

17800

+const static struct {

17801

+ unsigned long hi_1;

17802

+ unsigned long lo_1;

17803

+ unsigned long hi_2;

17804

+ unsigned long lo_2;

17805

+} values[] = {

17806

+ { 0x0000000000000000UL, 0xfffffffffffffffeUL,

17807

+ 0x0000000000000000UL, 0x0000000000000002UL },

17808

+ { 0x0000000000000000UL, 0x0000000000000002UL,

17809

+ 0x0000000000000000UL, 0xfffffffffffffffeUL },

17810

+ { 0xffffffffffffffffUL, 0xfffffffffffffffeUL,

17811

+ 0x0000000000000000UL, 0x0000000000000002UL },

17812

+ { 0xfffffffffffffff2UL, 0xffffffffffffffffUL,

17813

+ 0x0000000000000002UL, 0x0000000000000000UL },

17814

+ { 0x7fffffffffffffffUL, 0xfffffffffffffffeUL,

17815

+ 0x0000000000000000UL, 0x0000000000000002UL },

17816

+ { 0x7ffffffffffffff2UL, 0xffffffffffffffffUL,

17817

+ 0x0000000000000002UL, 0x0000000000000000UL },

17818

+};

17819

+

17820

+int

17821

+main (void)

17822

+{

17823

+ int reg_errors = 0;

17824

+ int mem_errors = 0;

17825

+ size_t i;

17826

+ const char *nl = "";

17827

+

17828

+ for (i = 0; i < sizeof (values) / sizeof (values[0]); i++)

17829

+ {

17830

+ S_TYPE s_reg_res, s_reg_in1, s_reg_in2, s_mem_res, s_mem_in1, s_mem_in2;

17831

+ V_TYPE v_reg_res, v_reg_in1, v_reg_in2, v_mem_res, v_mem_in1, v_mem_in2;

17832

+

17833

+ s_reg_in1 = ((((S_TYPE)values[i].hi_1 << 64)) + ((S_TYPE)values[i].lo_1));

17834

+ reg_errors += compare (s_reg_in1, (V_TYPE) { s_reg_in1 }, nl, "reg, in1");

17835

+

17836

+ s_reg_in2 = ((((S_TYPE)values[i].hi_2 << 64)) + ((S_TYPE)values[i].lo_2));

17837

+ reg_errors += compare (s_reg_in2, (V_TYPE) { s_reg_in2 }, "", "reg, in2");

17838

+

17839

+ s_reg_res = s_reg_in1 + s_reg_in2;

17840

+

17841

+ v_reg_in1 = (V_TYPE) { s_reg_in1 };

17842

+ v_reg_in2 = (V_TYPE) { s_reg_in2 };

17843

+ v_reg_res = vec_vadduqm (v_reg_in1, v_reg_in2);

17844

+ reg_errors += compare (s_reg_res, v_reg_res, "", "reg, res");

17845

+

17846

+ s_mem_in1 = s_reg_in1;

17847

+ convert_via_mem (&v_mem_in1, &s_mem_in1);

17848

+ mem_errors += compare (s_mem_in1, (V_TYPE) { s_mem_in1 }, "\n", "mem, in1");

17849

+

17850

+ s_mem_in2 = s_reg_in2;

17851

+ convert_via_mem (&v_mem_in2, &s_mem_in2);

17852

+ mem_errors += compare (s_mem_in2, (V_TYPE) { s_mem_in2 }, "", "mem, in2");

17853

+

17854

+ s_mem_res = s_mem_in1 + s_mem_in2;

17855

+ v_mem_res = vec_vadduqm (v_mem_in1, v_mem_in2);

17856

+ mem_errors += compare (s_mem_res, v_mem_res, "", "mem, res");

17857

+

17858

+ nl = "\n";

17859

+ }

17860

+

17861

+#ifdef DEBUG

17862

+ putchar ('\n');

17863

+

17864

+ if (!reg_errors)

17865

+ fputs ("no errors found on register operations\n", stdout);

17866

+ else

17867

+ printf ("%d error%s found on register operations\n",

17868

+ reg_errors,

17869

+ (reg_errors == 1) ? "s" : "");

17870

+

17871

+ if (!mem_errors)

17872

+ fputs ("no errors found on memory operations\n", stdout);

17873

+ else

17874

+ printf ("%d error%s found on memory operations\n",

17875

+ mem_errors,

17876

+ (mem_errors == 1) ? "s" : "");

17877

+

17878

+ fflush (stdout);

17879

+#endif

17880

+

17881

+ if ((reg_errors + mem_errors) != 0)

17882

+ abort ();

17883

+

17884

+ return 0;

17885

+}

17886

Index: gcc/testsuite/gcc.target/powerpc/pr58673-2.c

17887

===================================================================

17888

--- a/src/gcc/testsuite/gcc.target/powerpc/pr58673-2.c (.../tags/gcc_4_8_2_release)

17889

+++ b/src/gcc/testsuite/gcc.target/powerpc/pr58673-2.c (.../branches/gcc-4_8-branch)

17890

@@ -0,0 +1,217 @@

17891

+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */

17892

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

17893

+/* { dg-require-effective-target powerpc_p8vector_ok } */

17894

+/* { dg-options "-mcpu=power8 -O3 -m64 -funroll-loops" } */

17895

+

17896

+#include <stddef.h>

17897

+#include <stdlib.h>

17898

+#include <math.h>

17899

+#include <string.h>

17900

+

17901

+typedef long unsigned int size_t;

17902

+typedef struct _IO_FILE FILE;

17903

+typedef float real;

17904

+typedef real rvec[3];

17905

+typedef real matrix[3][3];

17906

+typedef real tensor[3][3];

17907

+enum

17908

+{

17909

+ F_BONDS, F_G96BONDS, F_MORSE, F_CUBICBONDS, F_CONNBONDS, F_HARMONIC,

17910

+ F_ANGLES, F_G96ANGLES, F_PDIHS, F_RBDIHS, F_IDIHS, F_LJ14, F_COUL14, F_LJ,

17911

+ F_BHAM, F_LJLR, F_DISPCORR, F_SR, F_LR, F_WPOL, F_POSRES, F_DISRES,

17912

+ F_DISRESVIOL, F_ORIRES, F_ORIRESDEV, F_ANGRES, F_ANGRESZ, F_SHAKE,

17913

+ F_SHAKENC, F_SETTLE, F_DUMMY2, F_DUMMY3, F_DUMMY3FD, F_DUMMY3FAD,

17914

+ F_DUMMY3OUT, F_DUMMY4FD, F_EQM, F_EPOT, F_EKIN, F_ETOT, F_TEMP, F_PRES,

17915

+ F_DVDL, F_DVDLKIN, F_NRE

17916

+};

17917

+typedef union

17918

+{

17919

+ struct

17920

+ {

17921

+ }

17922

+ bham;

17923

+ struct

17924

+ {

17925

+ real rA, krA, rB, krB;

17926

+ }

17927

+ harmonic;

17928

+}

17929

+t_iparams;

17930

+typedef struct

17931

+{

17932

+ t_iparams *iparams;

17933

+}

17934

+t_idef;

17935

+typedef struct

17936

+{

17937

+}

17938

+t_inputrec;

17939

+typedef struct

17940

+{

17941

+}

17942

+t_commrec;

17943

+typedef struct

17944

+{

17945

+}

17946

+t_forcerec;

17947

+typedef struct

17948

+{

17949

+}

17950

+t_mdatoms;

17951

+typedef struct

17952

+{

17953

+}

17954

+t_filenm;

17955

+enum

17956

+{

17957

+ eoPres, eoEpot, eoVir, eoDist, eoMu, eoForce, eoFx, eoFy, eoFz, eoPx, eoPy,

17958

+ eoPz, eoPolarizability, eoDipole, eoObsNR, eoMemory =

17959

+ eoObsNR, eoInter, eoUseVirial, eoNR

17960

+};

17961

+extern char *eoNames[eoNR];

17962

+typedef struct

17963

+{

17964

+ int bPrint;

17965

+}

17966

+t_coupl_LJ;

17967

+typedef struct

17968

+{

17969

+ int eObs;

17970

+ t_iparams xi;

17971

+}

17972

+t_coupl_iparams;

17973

+typedef struct

17974

+{

17975

+ real act_value[eoObsNR];

17976

+ real av_value[eoObsNR];

17977

+ real ref_value[eoObsNR];

17978

+ int bObsUsed[eoObsNR];

17979

+ int nLJ, nBU, nQ, nIP;

17980

+ t_coupl_LJ *tcLJ;

17981

+}

17982

+t_coupl_rec;

17983

+static void

17984

+pr_ff (t_coupl_rec * tcr, real time, t_idef * idef, t_commrec * cr, int nfile,

17985

+ t_filenm fnm[])

17986

+{

17987

+ static FILE *prop;

17988

+ static FILE **out = ((void *) 0);

17989

+ static FILE **qq = ((void *) 0);

17990

+ static FILE **ip = ((void *) 0);

17991

+ char buf[256];

17992

+ char *leg[] = {

17993

+ "C12", "C6"

17994

+ };

17995

+ char **raleg;

17996

+ int i, j, index;

17997

+ if ((prop == ((void *) 0)) && (out == ((void *) 0)) && (qq == ((void *) 0))

17998

+ && (ip == ((void *) 0)))

17999

+ {

18000

+ for (i = j = 0; (i < eoObsNR); i++)

18001

+ {

18002

+ if (tcr->bObsUsed[i])

18003

+ {

18004

+ raleg[j++] =

18005

+ (__extension__

18006

+ (__builtin_constant_p (eoNames[i])

18007

+ && ((size_t) (const void *) ((eoNames[i]) + 1) -

18008

+ (size_t) (const void *) (eoNames[i]) ==

18009

+ 1) ? (((const char *) (eoNames[i]))[0] ==

18010

+ '\0' ? (char *) calloc ((size_t) 1,

18011

+ (size_t) 1) : (

18012

+ {

18013

+ size_t

18014

+ __len

18015

+ =

18016

+ strlen

18017

+ (eoNames

18018

+ [i])

18019

+ +

18020

+ 1;

18021

+ char

18022

+ *__retval

18023

+ =

18024

+ (char

18025

+ *)

18026

+ malloc

18027

+ (__len);

18028

+ __retval;}

18029

+ )): __strdup (eoNames[i])));

18030

+ raleg[j++] =

18031

+ (__extension__

18032

+ (__builtin_constant_p (buf)

18033

+ && ((size_t) (const void *) ((buf) + 1) -

18034

+ (size_t) (const void *) (buf) ==

18035

+ 1) ? (((const char *) (buf))[0] ==

18036

+ '\0' ? (char *) calloc ((size_t) 1,

18037

+ (size_t) 1) : (

18038

+ {

18039

+ size_t

18040

+ __len

18041

+ =

18042

+ strlen

18043

+ (buf)

18044

+ +

18045

+ 1;

18046

+ char

18047

+ *__retval

18048

+ =

18049

+ (char

18050

+ *)

18051

+ malloc

18052

+ (__len);

18053

+ __retval;}

18054

+ )): __strdup (buf)));

18055

+ }

18056

+ }

18057

+ if (tcr->nLJ)

18058

+ {

18059

+ for (i = 0; (i < tcr->nLJ); i++)

18060

+ {

18061

+ if (tcr->tcLJ[i].bPrint)

18062

+ {

18063

+ xvgr_legend (out[i], (sizeof (leg) / sizeof ((leg)[0])),

18064

+ leg);

18065

+ }

18066

+ }

18067

+ }

18068

+ }

18069

+}

18070

+

18071

+void

18072

+do_coupling (FILE * log, int nfile, t_filenm fnm[], t_coupl_rec * tcr, real t,

18073

+ int step, real ener[], t_forcerec * fr, t_inputrec * ir,

18074

+ int bMaster, t_mdatoms * md, t_idef * idef, real mu_aver,

18075

+ int nmols, t_commrec * cr, matrix box, tensor virial,

18076

+ tensor pres, rvec mu_tot, rvec x[], rvec f[], int bDoIt)

18077

+{

18078

+ int i, j, ati, atj, atnr2, type, ftype;

18079

+ real deviation[eoObsNR], prdev[eoObsNR], epot0, dist, rmsf;

18080

+ real ff6, ff12, ffa, ffb, ffc, ffq, factor, dt, mu_ind;

18081

+ int bTest, bPrint;

18082

+ t_coupl_iparams *tip;

18083

+ if (bPrint)

18084

+ {

18085

+ pr_ff (tcr, t, idef, cr, nfile, fnm);

18086

+ }

18087

+ for (i = 0; (i < eoObsNR); i++)

18088

+ {

18089

+ deviation[i] =

18090

+ calc_deviation (tcr->av_value[i], tcr->act_value[i],

18091

+ tcr->ref_value[i]);

18092

+ prdev[i] = tcr->ref_value[i] - tcr->act_value[i];

18093

+ }

18094

+ if (bPrint)

18095

+ pr_dev (tcr, t, prdev, cr, nfile, fnm);

18096

+ for (i = 0; (i < atnr2); i++)

18097

+ {

18098

+ factor = dt * deviation[tip->eObs];

18099

+ switch (ftype)

18100

+ {

18101

+ case F_BONDS:

18102

+ if (fabs (tip->xi.harmonic.krA) > 1.2e-38)

18103

+ idef->iparams[type].harmonic.krA *=

18104

+ (1 + factor / tip->xi.harmonic.krA);

18105

+ }

18106

+ }

18107

+}

18108

Index: gcc/testsuite/gcc.target/powerpc/atomic-p7.c

18109

===================================================================

18110

--- a/src/gcc/testsuite/gcc.target/powerpc/atomic-p7.c (.../tags/gcc_4_8_2_release)

18111

+++ b/src/gcc/testsuite/gcc.target/powerpc/atomic-p7.c (.../branches/gcc-4_8-branch)

18112

@@ -0,0 +1,207 @@

18113

+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */

18114

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

18115

+/* { dg-require-effective-target powerpc_vsx_ok } */

18116

+/* { dg-options "-mcpu=power7 -O2" } */

18117

+/* { dg-final { scan-assembler-not "lbarx" } } */

18118

+/* { dg-final { scan-assembler-not "lharx" } } */

18119

+/* { dg-final { scan-assembler-times "lwarx" 18 } } */

18120

+/* { dg-final { scan-assembler-times "ldarx" 6 } } */

18121

+/* { dg-final { scan-assembler-not "lqarx" } } */

18122

+/* { dg-final { scan-assembler-not "stbcx" } } */

18123

+/* { dg-final { scan-assembler-not "sthcx" } } */

18124

+/* { dg-final { scan-assembler-times "stwcx" 18 } } */

18125

+/* { dg-final { scan-assembler-times "stdcx" 6 } } */

18126

+/* { dg-final { scan-assembler-not "stqcx" } } */

18127

+/* { dg-final { scan-assembler-times "bl __atomic" 6 } } */

18128

+/* { dg-final { scan-assembler-times "isync" 12 } } */

18129

+/* { dg-final { scan-assembler-times "lwsync" 8 } } */

18130

+/* { dg-final { scan-assembler-not "mtvsrd" } } */

18131

+/* { dg-final { scan-assembler-not "mtvsrwa" } } */

18132

+/* { dg-final { scan-assembler-not "mtvsrwz" } } */

18133

+/* { dg-final { scan-assembler-not "mfvsrd" } } */

18134

+/* { dg-final { scan-assembler-not "mfvsrwz" } } */

18135

+

18136

+/* Test for the byte atomic operations on power8 using lbarx/stbcx. */

18137

+char

18138

+char_fetch_add_relaxed (char *ptr, int value)

18139

+{

18140

+ return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED);

18141

+}

18142

+

18143

+char

18144

+char_fetch_sub_consume (char *ptr, int value)

18145

+{

18146

+ return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME);

18147

+}

18148

+

18149

+char

18150

+char_fetch_and_acquire (char *ptr, int value)

18151

+{

18152

+ return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE);

18153

+}

18154

+

18155

+char

18156

+char_fetch_ior_release (char *ptr, int value)

18157

+{

18158

+ return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE);

18159

+}

18160

+

18161

+char

18162

+char_fetch_xor_acq_rel (char *ptr, int value)

18163

+{

18164

+ return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL);

18165

+}

18166

+

18167

+char

18168

+char_fetch_nand_seq_cst (char *ptr, int value)

18169

+{

18170

+ return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST);

18171

+}

18172

+

18173

+/* Test for the half word atomic operations on power8 using lharx/sthcx. */

18174

+short

18175

+short_fetch_add_relaxed (short *ptr, int value)

18176

+{

18177

+ return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED);

18178

+}

18179

+

18180

+short

18181

+short_fetch_sub_consume (short *ptr, int value)

18182

+{

18183

+ return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME);

18184

+}

18185

+

18186

+short

18187

+short_fetch_and_acquire (short *ptr, int value)

18188

+{

18189

+ return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE);

18190

+}

18191

+

18192

+short

18193

+short_fetch_ior_release (short *ptr, int value)

18194

+{

18195

+ return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE);

18196

+}

18197

+

18198

+short

18199

+short_fetch_xor_acq_rel (short *ptr, int value)

18200

+{

18201

+ return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL);

18202

+}

18203

+

18204

+short

18205

+short_fetch_nand_seq_cst (short *ptr, int value)

18206

+{

18207

+ return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST);

18208

+}

18209

+

18210

+/* Test for the word atomic operations on power8 using lwarx/stwcx. */

18211

+int

18212

+int_fetch_add_relaxed (int *ptr, int value)

18213

+{

18214

+ return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED);

18215

+}

18216

+

18217

+int

18218

+int_fetch_sub_consume (int *ptr, int value)

18219

+{

18220

+ return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME);

18221

+}

18222

+

18223

+int

18224

+int_fetch_and_acquire (int *ptr, int value)

18225

+{

18226

+ return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE);

18227

+}

18228

+

18229

+int

18230

+int_fetch_ior_release (int *ptr, int value)

18231

+{

18232

+ return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE);

18233

+}

18234

+

18235

+int

18236

+int_fetch_xor_acq_rel (int *ptr, int value)

18237

+{

18238

+ return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL);

18239

+}

18240

+

18241

+int

18242

+int_fetch_nand_seq_cst (int *ptr, int value)

18243

+{

18244

+ return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST);

18245

+}

18246

+

18247

+/* Test for the double word atomic operations on power8 using ldarx/stdcx. */

18248

+long

18249

+long_fetch_add_relaxed (long *ptr, long value)

18250

+{

18251

+ return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED);

18252

+}

18253

+

18254

+long

18255

+long_fetch_sub_consume (long *ptr, long value)

18256

+{

18257

+ return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME);

18258

+}

18259

+

18260

+long

18261

+long_fetch_and_acquire (long *ptr, long value)

18262

+{

18263

+ return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE);

18264

+}

18265

+

18266

+long

18267

+long_fetch_ior_release (long *ptr, long value)

18268

+{

18269

+ return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE);

18270

+}

18271

+

18272

+long

18273

+long_fetch_xor_acq_rel (long *ptr, long value)

18274

+{

18275

+ return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL);

18276

+}

18277

+

18278

+long

18279

+long_fetch_nand_seq_cst (long *ptr, long value)

18280

+{

18281

+ return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST);

18282

+}

18283

+

18284

+/* Test for the quad word atomic operations on power8 using ldarx/stdcx. */

18285

+__int128_t

18286

+quad_fetch_add_relaxed (__int128_t *ptr, __int128_t value)

18287

+{

18288

+ return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED);

18289

+}

18290

+

18291

+__int128_t

18292

+quad_fetch_sub_consume (__int128_t *ptr, __int128_t value)

18293

+{

18294

+ return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME);

18295

+}

18296

+

18297

+__int128_t

18298

+quad_fetch_and_acquire (__int128_t *ptr, __int128_t value)

18299

+{

18300

+ return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE);

18301

+}

18302

+

18303

+__int128_t

18304

+quad_fetch_ior_release (__int128_t *ptr, __int128_t value)

18305

+{

18306

+ return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE);

18307

+}

18308

+

18309

+__int128_t

18310

+quad_fetch_xor_acq_rel (__int128_t *ptr, __int128_t value)

18311

+{

18312

+ return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL);

18313

+}

18314

+

18315

+__int128_t

18316

+quad_fetch_nand_seq_cst (__int128_t *ptr, __int128_t value)

18317

+{

18318

+ return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST);

18319

+}

18320

Index: gcc/testsuite/gcc.target/powerpc/recip-3.c

18321

===================================================================

18322

--- a/src/gcc/testsuite/gcc.target/powerpc/recip-3.c (.../tags/gcc_4_8_2_release)

18323

+++ b/src/gcc/testsuite/gcc.target/powerpc/recip-3.c (.../branches/gcc-4_8-branch)

18324

@@ -1,14 +1,14 @@

18325

/* { dg-do compile { target { { powerpc*-*-* } && { ! powerpc*-apple-darwin* } } } } */

18326

/* { dg-require-effective-target powerpc_fprs } */

18327

/* { dg-options "-O2 -mrecip -ffast-math -mcpu=power7" } */

18328

-/* { dg-final { scan-assembler-times "xsrsqrtedp" 1 } } */

18329

+/* { dg-final { scan-assembler-times "xsrsqrtedp\|frsqrte\ " 1 } } */

18330

/* { dg-final { scan-assembler-times "xsmsub.dp\|fmsub\ " 1 } } */

18331

-/* { dg-final { scan-assembler-times "xsmuldp" 4 } } */

18332

+/* { dg-final { scan-assembler-times "xsmuldp\|fmul\ " 4 } } */

18333

/* { dg-final { scan-assembler-times "xsnmsub.dp\|fnmsub\ " 2 } } */

18334

-/* { dg-final { scan-assembler-times "frsqrtes" 1 } } */

18335

-/* { dg-final { scan-assembler-times "fmsubs" 1 } } */

18336

-/* { dg-final { scan-assembler-times "fmuls" 4 } } */

18337

-/* { dg-final { scan-assembler-times "fnmsubs" 2 } } */

18338

+/* { dg-final { scan-assembler-times "xsrsqrtesp\|frsqrtes" 1 } } */

18339

+/* { dg-final { scan-assembler-times "xsmsub.sp\|fmsubs" 1 } } */

18340

+/* { dg-final { scan-assembler-times "xsmulsp\|fmuls" 2 } } */

18341

+/* { dg-final { scan-assembler-times "xsnmsub.sp\|fnmsubs" 1 } } */

18342

18343

double

18344

rsqrt_d (double a)

18345

Index: gcc/testsuite/gcc.target/powerpc/timode_off.c

18346

===================================================================

18347

--- a/src/gcc/testsuite/gcc.target/powerpc/timode_off.c (.../tags/gcc_4_8_2_release)

18348

+++ b/src/gcc/testsuite/gcc.target/powerpc/timode_off.c (.../branches/gcc-4_8-branch)

18349

@@ -1,5 +1,5 @@

18350

/* { dg-do assemble { target { lp64 } } } */

18351

-/* { dg-options "-O2 -fno-align-functions -mtraceback=no -save-temps" } */

18352

+/* { dg-options "-O2 -fno-align-functions -mtraceback=no -save-temps -mcpu=power5" } */

18353

18354

typedef int TImode __attribute__ ((mode (TI)));

18355

18356

@@ -46,6 +46,12 @@

18357

TImode r20 (void *x) { return *(TImode *) (x + 32748); }

18358

18359

/* test should really be == 616, see pr54110 */

18360

+/* When TImode is allowed in VSX registers, the allowable address modes for

18361

+ TImode is just a single indirect address in order for the value to be loaded

18362

+ and store in either GPR or VSX registers. This affects the generated code,

18363

+ and it would cause this test to fail, when such an option is used. Fall

18364

+ back to power5 to test the code. */

18365

+

18366

/* { dg-final { object-size text <= 700 } } */

18367

/* { dg-final { scan-assembler-not "(st|l)fd" } } */

18368

/* { dg-final { cleanup-saved-temps "timode_off" } } */

18369

Index: gcc/testsuite/gcc.target/powerpc/no-r11-2.c

18370

===================================================================

18371

--- a/src/gcc/testsuite/gcc.target/powerpc/no-r11-2.c (.../tags/gcc_4_8_2_release)

18372

+++ b/src/gcc/testsuite/gcc.target/powerpc/no-r11-2.c (.../branches/gcc-4_8-branch)

18373

@@ -1,5 +1,6 @@

18374

/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */

18375

/* { dg-skip-if "" { *-*-darwin* } { "*" } { "" } } */

18376

+/* { dg-skip-if "" { powerpc_elfv2 } { "*" } { "" } } */

18377

/* { dg-options "-O2 -mpointers-to-nested-functions" } */

18378

18379

int

18380

Index: gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c

18381

===================================================================

18382

--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c (.../tags/gcc_4_8_2_release)

18383

+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c (.../branches/gcc-4_8-branch)

18384

@@ -0,0 +1,42 @@

18385

+/* { dg-do compile { target { powerpc*-*-* } } } */

18386

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

18387

+/* { dg-require-effective-target powerpc_p8vector_ok } */

18388

+/* { dg-options "-mcpu=power8 -O2 -mupper-regs-df -mupper-regs-sf" } */

18389

+

18390

+float load_sf (float *p)

18391

+{

18392

+ float f = *p;

18393

+ __asm__ ("# reg %x0" : "+v" (f));

18394

+ return f;

18395

+}

18396

+

18397

+double load_df (double *p)

18398

+{

18399

+ double d = *p;

18400

+ __asm__ ("# reg %x0" : "+v" (d));

18401

+ return d;

18402

+}

18403

+

18404

+double load_dfsf (float *p)

18405

+{

18406

+ double d = (double) *p;

18407

+ __asm__ ("# reg %x0" : "+v" (d));

18408

+ return d;

18409

+}

18410

+

18411

+void store_sf (float *p, float f)

18412

+{

18413

+ __asm__ ("# reg %x0" : "+v" (f));

18414

+ *p = f;

18415

+}

18416

+

18417

+void store_df (double *p, double d)

18418

+{

18419

+ __asm__ ("# reg %x0" : "+v" (d));

18420

+ *p = d;

18421

+}

18422

+

18423

+/* { dg-final { scan-assembler "lxsspx" } } */

18424

+/* { dg-final { scan-assembler "lxsdx" } } */

18425

+/* { dg-final { scan-assembler "stxsspx" } } */

18426

+/* { dg-final { scan-assembler "stxsdx" } } */

18427

Index: gcc/testsuite/gcc.target/powerpc/pack01.c

18428

===================================================================

18429

--- a/src/gcc/testsuite/gcc.target/powerpc/pack01.c (.../tags/gcc_4_8_2_release)

18430

+++ b/src/gcc/testsuite/gcc.target/powerpc/pack01.c (.../branches/gcc-4_8-branch)

18431

@@ -0,0 +1,91 @@

18432

+/* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */

18433

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

18434

+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */

18435

+/* { dg-require-effective-target p8vector_hw } */

18436

+/* { dg-options "-mcpu=power8 -O2" } */

18437

+

18438

+#include <stddef.h>

18439

+#include <stdlib.h>

18440

+#include <altivec.h>

18441

+

18442

+#ifdef DEBUG

18443

+#include <stdio.h>

18444

+#endif

18445

+

18446

+typedef __int128_t __attribute__((__vector_size__(16))) vector_128_t;

18447

+typedef __int128_t scalar_128_t;

18448

+typedef unsigned long long scalar_64_t;

18449

+

18450

+volatile scalar_64_t one = 1;

18451

+volatile scalar_64_t two = 2;

18452

+

18453

+int

18454

+main (void)

18455

+{

18456

+ scalar_128_t a = (((scalar_128_t)one) << 64) | ((scalar_128_t)two);

18457

+ vector_128_t v1 = (vector_128_t) { a };

18458

+ vector_128_t v2 = __builtin_pack_vector_int128 (one, two);

18459

+ scalar_64_t x0 = __builtin_unpack_vector_int128 (v1, 0);

18460

+ scalar_64_t x1 = __builtin_unpack_vector_int128 (v1, 1);

18461

+ vector_128_t v3 = __builtin_pack_vector_int128 (x0, x1);

18462

+

18463

+ size_t i;

18464

+ union {

18465

+ scalar_128_t i128;

18466

+ vector_128_t v128;

18467

+ scalar_64_t u64;

18468

+ unsigned char uc[sizeof (scalar_128_t)];

18469

+ char c[sizeof (scalar_128_t)];

18470

+ } u, u2;

18471

+

18472

+#ifdef DEBUG

18473

+ {

18474

+ printf ("a = 0x");

18475

+ u.i128 = a;

18476

+ for (i = 0; i < sizeof (scalar_128_t); i++)

18477

+ printf ("%.2x", u.uc[i]);

18478

+

18479

+ printf ("\nv1 = 0x");

18480

+ u.v128 = v1;

18481

+ for (i = 0; i < sizeof (scalar_128_t); i++)

18482

+ printf ("%.2x", u.uc[i]);

18483

+

18484

+ printf ("\nv2 = 0x");

18485

+ u.v128 = v2;

18486

+ for (i = 0; i < sizeof (scalar_128_t); i++)

18487

+ printf ("%.2x", u.uc[i]);

18488

+

18489

+ printf ("\nv3 = 0x");

18490

+ u.v128 = v3;

18491

+ for (i = 0; i < sizeof (scalar_128_t); i++)

18492

+ printf ("%.2x", u.uc[i]);

18493

+

18494

+ printf ("\nx0 = 0x");

18495

+ u.u64 = x0;

18496

+ for (i = 0; i < sizeof (scalar_64_t); i++)

18497

+ printf ("%.2x", u.uc[i]);

18498

+

18499

+ printf ("\nx1 = 0x");

18500

+ u.u64 = x1;

18501

+ for (i = 0; i < sizeof (scalar_64_t); i++)

18502

+ printf ("%.2x", u.uc[i]);

18503

+

18504

+ printf ("\n");

18505

+ }

18506

+#endif

18507

+

18508

+ u2.i128 = a;

18509

+ u.v128 = v1;

18510

+ if (memcmp (u.c, u2.c, sizeof (scalar_128_t)) != 0)

18511

+ abort ();

18512

+

18513

+ u.v128 = v2;

18514

+ if (memcmp (u.c, u2.c, sizeof (scalar_128_t)) != 0)

18515

+ abort ();

18516

+

18517

+ u.v128 = v3;

18518

+ if (memcmp (u.c, u2.c, sizeof (scalar_128_t)) != 0)

18519

+ abort ();

18520

+

18521

+ return 0;

18522

+}

18523

Index: gcc/testsuite/gcc.target/powerpc/bool3-p8.c

18524

===================================================================

18525

--- a/src/gcc/testsuite/gcc.target/powerpc/bool3-p8.c (.../tags/gcc_4_8_2_release)

18526

+++ b/src/gcc/testsuite/gcc.target/powerpc/bool3-p8.c (.../branches/gcc-4_8-branch)

18527

@@ -0,0 +1,36 @@

18528

+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */

18529

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

18530

+/* { dg-require-effective-target powerpc_p8vector_ok } */

18531

+/* { dg-options "-O2 -mcpu=power8" } */

18532

+/* { dg-final { scan-assembler "\[ \t\]and " } } */

18533

+/* { dg-final { scan-assembler "\[ \t\]or " } } */

18534

+/* { dg-final { scan-assembler "\[ \t\]xor " } } */

18535

+/* { dg-final { scan-assembler "\[ \t\]nor " } } */

18536

+/* { dg-final { scan-assembler "\[ \t\]andc " } } */

18537

+/* { dg-final { scan-assembler "\[ \t\]eqv " } } */

18538

+/* { dg-final { scan-assembler "\[ \t\]orc " } } */

18539

+/* { dg-final { scan-assembler "\[ \t\]nand " } } */

18540

+/* { dg-final { scan-assembler-not "\[ \t\]vand " } } */

18541

+/* { dg-final { scan-assembler-not "\[ \t\]vandc " } } */

18542

+/* { dg-final { scan-assembler-not "\[ \t\]vor " } } */

18543

+/* { dg-final { scan-assembler-not "\[ \t\]vxor " } } */

18544

+/* { dg-final { scan-assembler-not "\[ \t\]vnor " } } */

18545

+/* { dg-final { scan-assembler-not "\[ \t\]xxland " } } */

18546

+/* { dg-final { scan-assembler-not "\[ \t\]xxlor " } } */

18547

+/* { dg-final { scan-assembler-not "\[ \t\]xxlxor " } } */

18548

+/* { dg-final { scan-assembler-not "\[ \t\]xxlnor " } } */

18549

+/* { dg-final { scan-assembler-not "\[ \t\]xxlandc " } } */

18550

+/* { dg-final { scan-assembler-not "\[ \t\]xxleqv " } } */

18551

+/* { dg-final { scan-assembler-not "\[ \t\]xxlorc " } } */

18552

+/* { dg-final { scan-assembler-not "\[ \t\]xxlnand " } } */

18553

+

18554

+#ifndef TYPE

18555

+#ifdef _ARCH_PPC64

18556

+#define TYPE __int128_t

18557

+#else

18558

+typedef int v4si __attribute__ ((vector_size (16)));

18559

+#define TYPE v4si

18560

+#endif

18561

+#endif

18562

+

18563

+#include "bool3.h"

18564

Index: gcc/testsuite/gcc.target/powerpc/htm-xl-intrin-1.c

18565

===================================================================

18566

--- a/src/gcc/testsuite/gcc.target/powerpc/htm-xl-intrin-1.c (.../tags/gcc_4_8_2_release)

18567

+++ b/src/gcc/testsuite/gcc.target/powerpc/htm-xl-intrin-1.c (.../branches/gcc-4_8-branch)

18568

@@ -0,0 +1,32 @@

18569

+/* This checks the availability of the XL compiler intrinsics for

18570

+ transactional execution with the expected prototypes. */

18571

+

18572

+/* { dg-do compile { target { powerpc*-*-* } } } */

18573

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

18574

+/* { dg-require-effective-target powerpc_htm_ok } */

18575

+/* { dg-options "-O2 -mhtm" } */

18576

+

18577

+#include <htmxlintrin.h>

18578

+

18579

+void

18580

+foo (void *TM_buff, long *result, unsigned char *code)

18581

+{

18582

+ *result++ = __TM_simple_begin ();

18583

+ *result++ = __TM_begin (TM_buff);

18584

+ *result++ = __TM_end ();

18585

+ __TM_abort ();

18586

+ __TM_named_abort (*code);

18587

+ __TM_resume ();

18588

+ __TM_suspend ();

18589

+ *result++ = __TM_is_user_abort (TM_buff);

18590

+ *result++ = __TM_is_named_user_abort (TM_buff, code);

18591

+ *result++ = __TM_is_illegal (TM_buff);

18592

+ *result++ = __TM_is_footprint_exceeded (TM_buff);

18593

+ *result++ = __TM_nesting_depth (TM_buff);

18594

+ *result++ = __TM_is_nested_too_deep (TM_buff);

18595

+ *result++ = __TM_is_conflict (TM_buff);

18596

+ *result++ = __TM_is_failure_persistent (TM_buff);

18597

+ *result++ = __TM_failure_address (TM_buff);

18598

+ *result++ = __TM_failure_code (TM_buff);

18599

+}

18600

+

18601

Index: gcc/testsuite/gcc.target/powerpc/rs6000-ldouble-3.c

18602

===================================================================

18603

--- a/src/gcc/testsuite/gcc.target/powerpc/rs6000-ldouble-3.c (.../tags/gcc_4_8_2_release)

18604

+++ b/src/gcc/testsuite/gcc.target/powerpc/rs6000-ldouble-3.c (.../branches/gcc-4_8-branch)

18605

@@ -0,0 +1,21 @@

18606

+/* Test accuracy of long double division (glibc bug 15396). */

18607

+/* { dg-do run { target powerpc*-*-linux* powerpc*-*-darwin* powerpc*-*-aix* rs6000-*-* } } */

18608

+/* { dg-options "-mlong-double-128" } */

18609

+

18610

+extern void exit (int);

18611

+extern void abort (void);

18612

+

18613

+volatile long double a = 0x1p-1024L;

18614

+volatile long double b = 0x3p-53L;

18615

+volatile long double r;

18616

+volatile long double expected = 0x1.55555555555555555555555555p-973L;

18617

+

18618

+int

18619

+main (void)

18620

+{

18621

+ r = a / b;

18622

+ /* Allow error up to 2ulp. */

18623

+ if (__builtin_fabsl (r - expected) > 0x1p-1073L)

18624

+ abort ();

18625

+ exit (0);

18626

+}

18627

Index: gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c

18628

===================================================================

18629

--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c (.../tags/gcc_4_8_2_release)

18630

+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c (.../branches/gcc-4_8-branch)

18631

@@ -0,0 +1,249 @@

18632

+/* { dg-do compile { target { powerpc*-*-* } } } */

18633

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

18634

+/* { dg-require-effective-target powerpc_p8vector_ok } */

18635

+/* { dg-options "-mcpu=power8 -O3 -ftree-vectorize -fvect-cost-model" } */

18636

+

18637

+#include <altivec.h>

18638

+

18639

+typedef vector long long vll_sign;

18640

+typedef vector unsigned long long vll_uns;

18641

+typedef vector bool long long vll_bool;

18642

+

18643

+typedef vector int vi_sign;

18644

+typedef vector unsigned int vi_uns;

18645

+typedef vector bool int vi_bool;

18646

+

18647

+typedef vector short vs_sign;

18648

+typedef vector unsigned short vs_uns;

18649

+typedef vector bool short vs_bool;

18650

+

18651

+typedef vector signed char vc_sign;

18652

+typedef vector unsigned char vc_uns;

18653

+typedef vector bool char vc_bool;

18654

+

18655

+vll_sign vll_clz_1 (vll_sign a)

18656

+{

18657

+ return __builtin_altivec_vclzd (a);

18658

+}

18659

+

18660

+vll_sign vll_clz_2 (vll_sign a)

18661

+{

18662

+ return vec_vclz (a);

18663

+}

18664

+

18665

+vll_sign vll_clz_3 (vll_sign a)

18666

+{

18667

+ return vec_vclzd (a);

18668

+}

18669

+

18670

+vll_uns vll_clz_4 (vll_uns a)

18671

+{

18672

+ return vec_vclz (a);

18673

+}

18674

+

18675

+vll_uns vll_clz_5 (vll_uns a)

18676

+{

18677

+ return vec_vclzd (a);

18678

+}

18679

+

18680

+vi_sign vi_clz_1 (vi_sign a)

18681

+{

18682

+ return __builtin_altivec_vclzw (a);

18683

+}

18684

+

18685

+vi_sign vi_clz_2 (vi_sign a)

18686

+{

18687

+ return vec_vclz (a);

18688

+}

18689

+

18690

+vi_sign vi_clz_3 (vi_sign a)

18691

+{

18692

+ return vec_vclzw (a);

18693

+}

18694

+

18695

+vi_uns vi_clz_4 (vi_uns a)

18696

+{

18697

+ return vec_vclz (a);

18698

+}

18699

+

18700

+vi_uns vi_clz_5 (vi_uns a)

18701

+{

18702

+ return vec_vclzw (a);

18703

+}

18704

+

18705

+vs_sign vs_clz_1 (vs_sign a)

18706

+{

18707

+ return __builtin_altivec_vclzh (a);

18708

+}

18709

+

18710

+vs_sign vs_clz_2 (vs_sign a)

18711

+{

18712

+ return vec_vclz (a);

18713

+}

18714

+

18715

+vs_sign vs_clz_3 (vs_sign a)

18716

+{

18717

+ return vec_vclzh (a);

18718

+}

18719

+

18720

+vs_uns vs_clz_4 (vs_uns a)

18721

+{

18722

+ return vec_vclz (a);

18723

+}

18724

+

18725

+vs_uns vs_clz_5 (vs_uns a)

18726

+{

18727

+ return vec_vclzh (a);

18728

+}

18729

+

18730

+vc_sign vc_clz_1 (vc_sign a)

18731

+{

18732

+ return __builtin_altivec_vclzb (a);

18733

+}

18734

+

18735

+vc_sign vc_clz_2 (vc_sign a)

18736

+{

18737

+ return vec_vclz (a);

18738

+}

18739

+

18740

+vc_sign vc_clz_3 (vc_sign a)

18741

+{

18742

+ return vec_vclzb (a);

18743

+}

18744

+

18745

+vc_uns vc_clz_4 (vc_uns a)

18746

+{

18747

+ return vec_vclz (a);

18748

+}

18749

+

18750

+vc_uns vc_clz_5 (vc_uns a)

18751

+{

18752

+ return vec_vclzb (a);

18753

+}

18754

+

18755

+vll_sign vll_popcnt_1 (vll_sign a)

18756

+{

18757

+ return __builtin_altivec_vpopcntd (a);

18758

+}

18759

+

18760

+vll_sign vll_popcnt_2 (vll_sign a)

18761

+{

18762

+ return vec_vpopcnt (a);

18763

+}

18764

+

18765

+vll_sign vll_popcnt_3 (vll_sign a)

18766

+{

18767

+ return vec_vpopcntd (a);

18768

+}

18769

+

18770

+vll_uns vll_popcnt_4 (vll_uns a)

18771

+{

18772

+ return vec_vpopcnt (a);

18773

+}

18774

+

18775

+vll_uns vll_popcnt_5 (vll_uns a)

18776

+{

18777

+ return vec_vpopcntd (a);

18778

+}

18779

+

18780

+vi_sign vi_popcnt_1 (vi_sign a)

18781

+{

18782

+ return __builtin_altivec_vpopcntw (a);

18783

+}

18784

+

18785

+vi_sign vi_popcnt_2 (vi_sign a)

18786

+{

18787

+ return vec_vpopcnt (a);

18788

+}

18789

+

18790

+vi_sign vi_popcnt_3 (vi_sign a)

18791

+{

18792

+ return vec_vpopcntw (a);

18793

+}

18794

+

18795

+vi_uns vi_popcnt_4 (vi_uns a)

18796

+{

18797

+ return vec_vpopcnt (a);

18798

+}

18799

+

18800

+vi_uns vi_popcnt_5 (vi_uns a)

18801

+{

18802

+ return vec_vpopcntw (a);

18803

+}

18804

+

18805

+vs_sign vs_popcnt_1 (vs_sign a)

18806

+{

18807

+ return __builtin_altivec_vpopcnth (a);

18808

+}

18809

+

18810

+vs_sign vs_popcnt_2 (vs_sign a)

18811

+{

18812

+ return vec_vpopcnt (a);

18813

+}

18814

+

18815

+vs_sign vs_popcnt_3 (vs_sign a)

18816

+{

18817

+ return vec_vpopcnth (a);

18818

+}

18819

+

18820

+vs_uns vs_popcnt_4 (vs_uns a)

18821

+{

18822

+ return vec_vpopcnt (a);

18823

+}

18824

+

18825

+vs_uns vs_popcnt_5 (vs_uns a)

18826

+{

18827

+ return vec_vpopcnth (a);

18828

+}

18829

+

18830

+vc_sign vc_popcnt_1 (vc_sign a)

18831

+{

18832

+ return __builtin_altivec_vpopcntb (a);

18833

+}

18834

+

18835

+vc_sign vc_popcnt_2 (vc_sign a)

18836

+{

18837

+ return vec_vpopcnt (a);

18838

+}

18839

+

18840

+vc_sign vc_popcnt_3 (vc_sign a)

18841

+{

18842

+ return vec_vpopcntb (a);

18843

+}

18844

+

18845

+vc_uns vc_popcnt_4 (vc_uns a)

18846

+{

18847

+ return vec_vpopcnt (a);

18848

+}

18849

+

18850

+vc_uns vc_popcnt_5 (vc_uns a)

18851

+{

18852

+ return vec_vpopcntb (a);

18853

+}

18854

+

18855

+vc_uns vc_gbb_1 (vc_uns a)

18856

+{

18857

+ return __builtin_altivec_vgbbd (a);

18858

+}

18859

+

18860

+vc_sign vc_gbb_2 (vc_sign a)

18861

+{

18862

+ return vec_vgbbd (a);

18863

+}

18864

+

18865

+vc_uns vc_gbb_3 (vc_uns a)

18866

+{

18867

+ return vec_vgbbd (a);

18868

+}

18869

+

18870

+/* { dg-final { scan-assembler-times "vclzd" 5 } } */

18871

+/* { dg-final { scan-assembler-times "vclzw" 5 } } */

18872

+/* { dg-final { scan-assembler-times "vclzh" 5 } } */

18873

+/* { dg-final { scan-assembler-times "vclzb" 5 } } */

18874

+

18875

+/* { dg-final { scan-assembler-times "vpopcntd" 5 } } */

18876

+/* { dg-final { scan-assembler-times "vpopcntw" 5 } } */

18877

+/* { dg-final { scan-assembler-times "vpopcnth" 5 } } */

18878

+/* { dg-final { scan-assembler-times "vpopcntb" 5 } } */

18879

+

18880

+/* { dg-final { scan-assembler-times "vgbbd" 3 } } */

18881

Index: gcc/testsuite/gcc.target/powerpc/bool3-av.c

18882

===================================================================

18883

--- a/src/gcc/testsuite/gcc.target/powerpc/bool3-av.c (.../tags/gcc_4_8_2_release)

18884

+++ b/src/gcc/testsuite/gcc.target/powerpc/bool3-av.c (.../branches/gcc-4_8-branch)

18885

@@ -0,0 +1,37 @@

18886

+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */

18887

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

18888

+/* { dg-require-effective-target powerpc_altivec_ok } */

18889

+/* { dg-options "-O2 -mcpu=power6 -mabi=altivec -maltivec -mno-vsx" } */

18890

+/* { dg-final { scan-assembler "\[ \t\]and " } } */

18891

+/* { dg-final { scan-assembler "\[ \t\]or " } } */

18892

+/* { dg-final { scan-assembler "\[ \t\]xor " } } */

18893

+/* { dg-final { scan-assembler "\[ \t\]nor " } } */

18894

+/* { dg-final { scan-assembler "\[ \t\]andc " } } */

18895

+/* { dg-final { scan-assembler-not "\[ \t\]vand " } } */

18896

+/* { dg-final { scan-assembler-not "\[ \t\]vandc " } } */

18897

+/* { dg-final { scan-assembler-not "\[ \t\]vor " } } */

18898

+/* { dg-final { scan-assembler-not "\[ \t\]vxor " } } */

18899

+/* { dg-final { scan-assembler-not "\[ \t\]vnor " } } */

18900

+/* { dg-final { scan-assembler-not "\[ \t\]xxland " } } */

18901

+/* { dg-final { scan-assembler-not "\[ \t\]xxlor " } } */

18902

+/* { dg-final { scan-assembler-not "\[ \t\]xxlxor " } } */

18903

+/* { dg-final { scan-assembler-not "\[ \t\]xxlnor " } } */

18904

+/* { dg-final { scan-assembler-not "\[ \t\]xxlandc " } } */

18905

+/* { dg-final { scan-assembler-not "\[ \t\]xxleqv " } } */

18906

+/* { dg-final { scan-assembler-not "\[ \t\]xxlorc " } } */

18907

+/* { dg-final { scan-assembler-not "\[ \t\]xxlnand " } } */

18908

+

18909

+/* On altivec, for 128-bit types, ORC/ANDC/EQV might not show up, since the

18910

+ vector unit doesn't support these, so the appropriate combine patterns may

18911

+ not be generated. */

18912

+

18913

+#ifndef TYPE

18914

+#ifdef _ARCH_PPC64

18915

+#define TYPE __int128_t

18916

+#else

18917

+typedef int v4si __attribute__ ((vector_size (16)));

18918

+#define TYPE v4si

18919

+#endif

18920

+#endif

18921

+

18922

+#include "bool3.h"

18923

Index: gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-4.c

18924

===================================================================

18925

--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-4.c (.../tags/gcc_4_8_2_release)

18926

+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-4.c (.../branches/gcc-4_8-branch)

18927

@@ -0,0 +1,69 @@

18928

+/* { dg-do compile { target { powerpc*-*-* } } } */

18929

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

18930

+/* { dg-require-effective-target powerpc_p8vector_ok } */

18931

+/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model -fno-unroll-loops -fno-unroll-all-loops" } */

18932

+

18933

+#ifndef SIZE

18934

+#define SIZE 1024

18935

+#endif

18936

+

18937

+#ifndef ALIGN

18938

+#define ALIGN 32

18939

+#endif

18940

+

18941

+#define ALIGN_ATTR __attribute__((__aligned__(ALIGN)))

18942

+

18943

+#define DO_BUILTIN(PREFIX, TYPE, CLZ, POPCNT) \

18944

+TYPE PREFIX ## _a[SIZE] ALIGN_ATTR; \

18945

+TYPE PREFIX ## _b[SIZE] ALIGN_ATTR; \

18946

+ \

18947

+void \

18948

+PREFIX ## _clz (void) \

18949

+{ \

18950

+ unsigned long i; \

18951

+ \

18952

+ for (i = 0; i < SIZE; i++) \

18953

+ PREFIX ## _a[i] = CLZ (PREFIX ## _b[i]); \

18954

+} \

18955

+ \

18956

+void \

18957

+PREFIX ## _popcnt (void) \

18958

+{ \

18959

+ unsigned long i; \

18960

+ \

18961

+ for (i = 0; i < SIZE; i++) \

18962

+ PREFIX ## _a[i] = POPCNT (PREFIX ## _b[i]); \

18963

+}

18964

+

18965

+#if !defined(DO_LONG_LONG) && !defined(DO_LONG) && !defined(DO_INT) && !defined(DO_SHORT) && !defined(DO_CHAR)

18966

+#define DO_INT 1

18967

+#endif

18968

+

18969

+#if DO_LONG_LONG

18970

+/* At the moment, only int is auto vectorized. */

18971

+DO_BUILTIN (sll, long long, __builtin_clzll, __builtin_popcountll)

18972

+DO_BUILTIN (ull, unsigned long long, __builtin_clzll, __builtin_popcountll)

18973

+#endif

18974

+

18975

+#if defined(_ARCH_PPC64) && DO_LONG

18976

+DO_BUILTIN (sl, long, __builtin_clzl, __builtin_popcountl)

18977

+DO_BUILTIN (ul, unsigned long, __builtin_clzl, __builtin_popcountl)

18978

+#endif

18979

+

18980

+#if DO_INT

18981

+DO_BUILTIN (si, int, __builtin_clz, __builtin_popcount)

18982

+DO_BUILTIN (ui, unsigned int, __builtin_clz, __builtin_popcount)

18983

+#endif

18984

+

18985

+#if DO_SHORT

18986

+DO_BUILTIN (ss, short, __builtin_clz, __builtin_popcount)

18987

+DO_BUILTIN (us, unsigned short, __builtin_clz, __builtin_popcount)

18988

+#endif

18989

+

18990

+#if DO_CHAR

18991

+DO_BUILTIN (sc, signed char, __builtin_clz, __builtin_popcount)

18992

+DO_BUILTIN (uc, unsigned char, __builtin_clz, __builtin_popcount)

18993

+#endif

18994

+

18995

+/* { dg-final { scan-assembler-times "vclzw" 2 } } */

18996

+/* { dg-final { scan-assembler-times "vpopcntw" 2 } } */

18997

Index: gcc/testsuite/gcc.target/powerpc/bcd-3.c

18998

===================================================================

18999

--- a/src/gcc/testsuite/gcc.target/powerpc/bcd-3.c (.../tags/gcc_4_8_2_release)

19000

+++ b/src/gcc/testsuite/gcc.target/powerpc/bcd-3.c (.../branches/gcc-4_8-branch)

19001

@@ -0,0 +1,103 @@

19002

+/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */

19003

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

19004

+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */

19005

+/* { dg-require-effective-target powerpc_p8vector_ok } */

19006

+/* { dg-options "-mcpu=power8 -O2" } */

19007

+/* { dg-final { scan-assembler-times "bcdadd\[.\] " 4 } } */

19008

+/* { dg-final { scan-assembler-times "bcdsub\[.\] " 4 } } */

19009

+/* { dg-final { scan-assembler-not "bl __builtin" } } */

19010

+/* { dg-final { scan-assembler-not "mtvsr" } } */

19011

+/* { dg-final { scan-assembler-not "mfvsr" } } */

19012

+/* { dg-final { scan-assembler-not "lvx" } } */

19013

+/* { dg-final { scan-assembler-not "lxvw4x" } } */

19014

+/* { dg-final { scan-assembler-not "lxvd2x" } } */

19015

+/* { dg-final { scan-assembler-not "stvx" } } */

19016

+/* { dg-final { scan-assembler-not "stxvw4x" } } */

19017

+/* { dg-final { scan-assembler-not "stxvd2x" } } */

19018

+

19019

+typedef __int128_t __attribute__((__vector_size__(16))) vector_128_t;

19020

+typedef __int128_t scalar_128_t;

19021

+typedef unsigned long long scalar_64_t;

19022

+

19023

+/* Test whether the peephole works to allow folding a bcdadd, with a

19024

+ bcdadd_<test> into a single instruction. */

19025

+

19026

+vector_128_t

19027

+do_add_lt (vector_128_t a, vector_128_t b, int *p)

19028

+{

19029

+ vector_128_t ret = __builtin_bcdadd (a, b, 0);

19030

+ if (__builtin_bcdadd_lt (a, b, 0))

19031

+ *p = 1;

19032

+

19033

+ return ret;

19034

+}

19035

+

19036

+vector_128_t

19037

+do_add_eq (vector_128_t a, vector_128_t b, int *p)

19038

+{

19039

+ vector_128_t ret = __builtin_bcdadd (a, b, 0);

19040

+ if (__builtin_bcdadd_eq (a, b, 0))

19041

+ *p = 1;

19042

+

19043

+ return ret;

19044

+}

19045

+

19046

+vector_128_t

19047

+do_add_gt (vector_128_t a, vector_128_t b, int *p)

19048

+{

19049

+ vector_128_t ret = __builtin_bcdadd (a, b, 0);

19050

+ if (__builtin_bcdadd_gt (a, b, 0))

19051

+ *p = 1;

19052

+

19053

+ return ret;

19054

+}

19055

+

19056

+vector_128_t

19057

+do_add_ov (vector_128_t a, vector_128_t b, int *p)

19058

+{

19059

+ vector_128_t ret = __builtin_bcdadd (a, b, 0);

19060

+ if (__builtin_bcdadd_ov (a, b, 0))

19061

+ *p = 1;

19062

+

19063

+ return ret;

19064

+}

19065

+

19066

+vector_128_t

19067

+do_sub_lt (vector_128_t a, vector_128_t b, int *p)

19068

+{

19069

+ vector_128_t ret = __builtin_bcdsub (a, b, 0);

19070

+ if (__builtin_bcdsub_lt (a, b, 0))

19071

+ *p = 1;

19072

+

19073

+ return ret;

19074

+}

19075

+

19076

+vector_128_t

19077

+do_sub_eq (vector_128_t a, vector_128_t b, int *p)

19078

+{

19079

+ vector_128_t ret = __builtin_bcdsub (a, b, 0);

19080

+ if (__builtin_bcdsub_eq (a, b, 0))

19081

+ *p = 1;

19082

+

19083

+ return ret;

19084

+}

19085

+

19086

+vector_128_t

19087

+do_sub_gt (vector_128_t a, vector_128_t b, int *p)

19088

+{

19089

+ vector_128_t ret = __builtin_bcdsub (a, b, 0);

19090

+ if (__builtin_bcdsub_gt (a, b, 0))

19091

+ *p = 1;

19092

+

19093

+ return ret;

19094

+}

19095

+

19096

+vector_128_t

19097

+do_sub_ov (vector_128_t a, vector_128_t b, int *p)

19098

+{

19099

+ vector_128_t ret = __builtin_bcdsub (a, b, 0);

19100

+ if (__builtin_bcdsub_ov (a, b, 0))

19101

+ *p = 1;

19102

+

19103

+ return ret;

19104

+}

19105

Index: gcc/testsuite/gcc.target/powerpc/pr57949-1.c

19106

===================================================================

19107

--- a/src/gcc/testsuite/gcc.target/powerpc/pr57949-1.c (.../tags/gcc_4_8_2_release)

19108

+++ b/src/gcc/testsuite/gcc.target/powerpc/pr57949-1.c (.../branches/gcc-4_8-branch)

19109

@@ -0,0 +1,20 @@

19110

+/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */

19111

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

19112

+/* { dg-skip-if "" { powerpc_elfv2 } { "*" } { "" } } */

19113

+/* { dg-options "-O2 -mcpu=power7 -mno-compat-align-parm" } */

19114

+

19115

+/* Verify that vs is 16-byte aligned with -mcompat-align-parm. */

19116

+

19117

+typedef float v4sf __attribute__ ((vector_size (16)));

19118

+struct s { long m; v4sf v; };

19119

+long n;

19120

+v4sf ve;

19121

+

19122

+void pr57949 (long d1, long d2, long d3, long d4, long d5, long d6,

19123

+ long d7, long d8, long d9, struct s vs) {

19124

+ n = vs.m;

19125

+ ve = vs.v;

19126

+}

19127

+

19128

+/* { dg-final { scan-assembler "li \.\*,144" } } */

19129

+/* { dg-final { scan-assembler "ld \.\*,128\$1\$" } } */

19130

Index: gcc/testsuite/gcc.target/powerpc/atomic-p8.c

19131

===================================================================

19132

--- a/src/gcc/testsuite/gcc.target/powerpc/atomic-p8.c (.../tags/gcc_4_8_2_release)

19133

+++ b/src/gcc/testsuite/gcc.target/powerpc/atomic-p8.c (.../branches/gcc-4_8-branch)

19134

@@ -0,0 +1,237 @@

19135

+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */

19136

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

19137

+/* { dg-require-effective-target powerpc_p8vector_ok } */

19138

+/* { dg-options "-mcpu=power8 -O2" } */

19139

+/* { dg-final { scan-assembler-times "lbarx" 7 } } */

19140

+/* { dg-final { scan-assembler-times "lharx" 7 } } */

19141

+/* { dg-final { scan-assembler-times "lwarx" 7 } } */

19142

+/* { dg-final { scan-assembler-times "ldarx" 7 } } */

19143

+/* { dg-final { scan-assembler-times "lqarx" 7 } } */

19144

+/* { dg-final { scan-assembler-times "stbcx" 7 } } */

19145

+/* { dg-final { scan-assembler-times "sthcx" 7 } } */

19146

+/* { dg-final { scan-assembler-times "stwcx" 7 } } */

19147

+/* { dg-final { scan-assembler-times "stdcx" 7 } } */

19148

+/* { dg-final { scan-assembler-times "stqcx" 7 } } */

19149

+/* { dg-final { scan-assembler-not "bl __atomic" } } */

19150

+/* { dg-final { scan-assembler-times "isync" 20 } } */

19151

+/* { dg-final { scan-assembler-times "lwsync" 10 } } */

19152

+/* { dg-final { scan-assembler-not "mtvsrd" } } */

19153

+/* { dg-final { scan-assembler-not "mtvsrwa" } } */

19154

+/* { dg-final { scan-assembler-not "mtvsrwz" } } */

19155

+/* { dg-final { scan-assembler-not "mfvsrd" } } */

19156

+/* { dg-final { scan-assembler-not "mfvsrwz" } } */

19157

+

19158

+/* Test for the byte atomic operations on power8 using lbarx/stbcx. */

19159

+char

19160

+char_fetch_add_relaxed (char *ptr, int value)

19161

+{

19162

+ return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED);

19163

+}

19164

+

19165

+char

19166

+char_fetch_sub_consume (char *ptr, int value)

19167

+{

19168

+ return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME);

19169

+}

19170

+

19171

+char

19172

+char_fetch_and_acquire (char *ptr, int value)

19173

+{

19174

+ return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE);

19175

+}

19176

+

19177

+char

19178

+char_fetch_ior_release (char *ptr, int value)

19179

+{

19180

+ return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE);

19181

+}

19182

+

19183

+char

19184

+char_fetch_xor_acq_rel (char *ptr, int value)

19185

+{

19186

+ return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL);

19187

+}

19188

+

19189

+char

19190

+char_fetch_nand_seq_cst (char *ptr, int value)

19191

+{

19192

+ return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST);

19193

+}

19194

+

19195

+void

19196

+char_val_compare_and_swap (char *p, int i, int j, char *q)

19197

+{

19198

+ *q = __sync_val_compare_and_swap (p, i, j);

19199

+}

19200

+

19201

+/* Test for the half word atomic operations on power8 using lharx/sthcx. */

19202

+short

19203

+short_fetch_add_relaxed (short *ptr, int value)

19204

+{

19205

+ return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED);

19206

+}

19207

+

19208

+short

19209

+short_fetch_sub_consume (short *ptr, int value)

19210

+{

19211

+ return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME);

19212

+}

19213

+

19214

+short

19215

+short_fetch_and_acquire (short *ptr, int value)

19216

+{

19217

+ return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE);

19218

+}

19219

+

19220

+short

19221

+short_fetch_ior_release (short *ptr, int value)

19222

+{

19223

+ return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE);

19224

+}

19225

+

19226

+short

19227

+short_fetch_xor_acq_rel (short *ptr, int value)

19228

+{

19229

+ return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL);

19230

+}

19231

+

19232

+short

19233

+short_fetch_nand_seq_cst (short *ptr, int value)

19234

+{

19235

+ return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST);

19236

+}

19237

+

19238

+void

19239

+short_val_compare_and_swap (short *p, int i, int j, short *q)

19240

+{

19241

+ *q = __sync_val_compare_and_swap (p, i, j);

19242

+}

19243

+

19244

+/* Test for the word atomic operations on power8 using lwarx/stwcx. */

19245

+int

19246

+int_fetch_add_relaxed (int *ptr, int value)

19247

+{

19248

+ return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED);

19249

+}

19250

+

19251

+int

19252

+int_fetch_sub_consume (int *ptr, int value)

19253

+{

19254

+ return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME);

19255

+}

19256

+

19257

+int

19258

+int_fetch_and_acquire (int *ptr, int value)

19259

+{

19260

+ return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE);

19261

+}

19262

+

19263

+int

19264

+int_fetch_ior_release (int *ptr, int value)

19265

+{

19266

+ return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE);

19267

+}

19268

+

19269

+int

19270

+int_fetch_xor_acq_rel (int *ptr, int value)

19271

+{

19272

+ return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL);

19273

+}

19274

+

19275

+int

19276

+int_fetch_nand_seq_cst (int *ptr, int value)

19277

+{

19278

+ return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST);

19279

+}

19280

+

19281

+void

19282

+int_val_compare_and_swap (int *p, int i, int j, int *q)

19283

+{

19284

+ *q = __sync_val_compare_and_swap (p, i, j);

19285

+}

19286

+

19287

+/* Test for the double word atomic operations on power8 using ldarx/stdcx. */

19288

+long

19289

+long_fetch_add_relaxed (long *ptr, long value)

19290

+{

19291

+ return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED);

19292

+}

19293

+

19294

+long

19295

+long_fetch_sub_consume (long *ptr, long value)

19296

+{

19297

+ return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME);

19298

+}

19299

+

19300

+long

19301

+long_fetch_and_acquire (long *ptr, long value)

19302

+{

19303

+ return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE);

19304

+}

19305

+

19306

+long

19307

+long_fetch_ior_release (long *ptr, long value)

19308

+{

19309

+ return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE);

19310

+}

19311

+

19312

+long

19313

+long_fetch_xor_acq_rel (long *ptr, long value)

19314

+{

19315

+ return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL);

19316

+}

19317

+

19318

+long

19319

+long_fetch_nand_seq_cst (long *ptr, long value)

19320

+{

19321

+ return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST);

19322

+}

19323

+

19324

+void

19325

+long_val_compare_and_swap (long *p, long i, long j, long *q)

19326

+{

19327

+ *q = __sync_val_compare_and_swap (p, i, j);

19328

+}

19329

+

19330

+/* Test for the quad word atomic operations on power8 using ldarx/stdcx. */

19331

+__int128_t

19332

+quad_fetch_add_relaxed (__int128_t *ptr, __int128_t value)

19333

+{

19334

+ return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED);

19335

+}

19336

+

19337

+__int128_t

19338

+quad_fetch_sub_consume (__int128_t *ptr, __int128_t value)

19339

+{

19340

+ return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME);

19341

+}

19342

+

19343

+__int128_t

19344

+quad_fetch_and_acquire (__int128_t *ptr, __int128_t value)

19345

+{

19346

+ return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE);

19347

+}

19348

+

19349

+__int128_t

19350

+quad_fetch_ior_release (__int128_t *ptr, __int128_t value)

19351

+{

19352

+ return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE);

19353

+}

19354

+

19355

+__int128_t

19356

+quad_fetch_xor_acq_rel (__int128_t *ptr, __int128_t value)

19357

+{

19358

+ return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL);

19359

+}

19360

+

19361

+__int128_t

19362

+quad_fetch_nand_seq_cst (__int128_t *ptr, __int128_t value)

19363

+{

19364

+ return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST);

19365

+}

19366

+

19367

+void

19368

+quad_val_compare_and_swap (__int128_t *p, __int128_t i, __int128_t j, __int128_t *q)

19369

+{

19370

+ *q = __sync_val_compare_and_swap (p, i, j);

19371

+}

19372

Index: gcc/testsuite/gcc.target/powerpc/sd-pwr6.c

19373

===================================================================

19374

--- a/src/gcc/testsuite/gcc.target/powerpc/sd-pwr6.c (.../tags/gcc_4_8_2_release)

19375

+++ b/src/gcc/testsuite/gcc.target/powerpc/sd-pwr6.c (.../branches/gcc-4_8-branch)

19376

@@ -0,0 +1,19 @@

19377

+/* { dg-do compile { target { powerpc*-*-* } } } */

19378

+/* { dg-skip-if "" { powerpc*-*-darwin* powerpc-ibm-aix* } { "*" } { "" } } */

19379

+/* { dg-require-effective-target powerpc_vsx_ok } */

19380

+/* { dg-options "-O2 -mcpu=power6 -mhard-dfp" } */

19381

+/* { dg-final { scan-assembler-not "lfiwzx" } } */

19382

+/* { dg-final { scan-assembler-times "lfd" 2 } } */

19383

+/* { dg-final { scan-assembler-times "dctdp" 2 } } */

19384

+/* { dg-final { scan-assembler-times "dadd" 1 } } */

19385

+/* { dg-final { scan-assembler-times "drsp" 1 } } */

19386

+

19387

+/* Test that for power6 we need to use a bounce buffer on the stack to load

19388

+ SDmode variables because the power6 does not have a way to directly load

19389

+ 32-bit values from memory. */

19390

+_Decimal32 a;

19391

+

19392

+void inc_dec32 (void)

19393

+{

19394

+ a += (_Decimal32) 1.0;

19395

+}

19396

Index: gcc/testsuite/gcc.target/powerpc/recip-4.c

19397

===================================================================

19398

--- a/src/gcc/testsuite/gcc.target/powerpc/recip-4.c (.../tags/gcc_4_8_2_release)

19399

+++ b/src/gcc/testsuite/gcc.target/powerpc/recip-4.c (.../branches/gcc-4_8-branch)

19400

@@ -7,8 +7,8 @@

19401

/* { dg-final { scan-assembler-times "xvnmsub.dp" 2 } } */

19402

/* { dg-final { scan-assembler-times "xvrsqrtesp" 1 } } */

19403

/* { dg-final { scan-assembler-times "xvmsub.sp" 1 } } */

19404

-/* { dg-final { scan-assembler-times "xvmulsp" 4 } } */

19405

-/* { dg-final { scan-assembler-times "xvnmsub.sp" 2 } } */

19406

+/* { dg-final { scan-assembler-times "xvmulsp" 2 } } */

19407

+/* { dg-final { scan-assembler-times "xvnmsub.sp" 1 } } */

19408

19409

#define SIZE 1024

19410

19411

Index: gcc/testsuite/gcc.target/powerpc/no-r11-3.c

19412

===================================================================

19413

--- a/src/gcc/testsuite/gcc.target/powerpc/no-r11-3.c (.../tags/gcc_4_8_2_release)

19414

+++ b/src/gcc/testsuite/gcc.target/powerpc/no-r11-3.c (.../branches/gcc-4_8-branch)

19415

@@ -1,5 +1,6 @@

19416

/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */

19417

/* { dg-skip-if "" { *-*-darwin* } { "*" } { "" } } */

19418

+/* { dg-skip-if "" { powerpc_elfv2 } { "*" } { "" } } */

19419

/* { dg-options "-O2 -mno-pointers-to-nested-functions" } */

19420

19421

extern void ext_call (int (func) (void));

19422

Index: gcc/testsuite/gcc.target/powerpc/pack02.c

19423

===================================================================

19424

--- a/src/gcc/testsuite/gcc.target/powerpc/pack02.c (.../tags/gcc_4_8_2_release)

19425

+++ b/src/gcc/testsuite/gcc.target/powerpc/pack02.c (.../branches/gcc-4_8-branch)

19426

@@ -0,0 +1,95 @@

19427

+/* { dg-do run { target { powerpc*-*-linux* } } } */

19428

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

19429

+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */

19430

+/* { dg-require-effective-target powerpc_fprs } */

19431

+/* { dg-options "-O2 -mhard-float" } */

19432

+

19433

+#include <stddef.h>

19434

+#include <stdlib.h>

19435

+#include <math.h>

19436

+

19437

+#ifdef DEBUG

19438

+#include <stdio.h>

19439

+#endif

19440

+

19441

+int

19442

+main (void)

19443

+{

19444

+ double high = pow (2.0, 60);

19445

+ double low = 2.0;

19446

+ long double a = ((long double)high) + ((long double)low);

19447

+ double x0 = __builtin_unpack_longdouble (a, 0);

19448

+ double x1 = __builtin_unpack_longdouble (a, 1);

19449

+ long double b = __builtin_pack_longdouble (x0, x1);

19450

+

19451

+#ifdef DEBUG

19452

+ {

19453

+ size_t i;

19454

+ union {

19455

+ long double ld;

19456

+ double d;

19457

+ unsigned char uc[sizeof (long double)];

19458

+ char c[sizeof (long double)];

19459

+ } u;

19460

+

19461

+ printf ("a = 0x");

19462

+ u.ld = a;

19463

+ for (i = 0; i < sizeof (long double); i++)

19464

+ printf ("%.2x", u.uc[i]);

19465

+

19466

+ printf (", %Lg\n", a);

19467

+

19468

+ printf ("b = 0x");

19469

+ u.ld = b;

19470

+ for (i = 0; i < sizeof (long double); i++)

19471

+ printf ("%.2x", u.uc[i]);

19472

+

19473

+ printf (", %Lg\n", b);

19474

+

19475

+ printf ("hi = 0x");

19476

+ u.d = high;

19477

+ for (i = 0; i < sizeof (double); i++)

19478

+ printf ("%.2x", u.uc[i]);

19479

+

19480

+ printf (",%*s %g\n", (int)(2 * (sizeof (long double) - sizeof (double))), "", high);

19481

+

19482

+ printf ("lo = 0x");

19483

+ u.d = low;

19484

+ for (i = 0; i < sizeof (double); i++)

19485

+ printf ("%.2x", u.uc[i]);

19486

+

19487

+ printf (",%*s %g\n", (int)(2 * (sizeof (long double) - sizeof (double))), "", low);

19488

+

19489

+ printf ("x0 = 0x");

19490

+ u.d = x0;

19491

+ for (i = 0; i < sizeof (double); i++)

19492

+ printf ("%.2x", u.uc[i]);

19493

+

19494

+ printf (",%*s %g\n", (int)(2 * (sizeof (long double) - sizeof (double))), "", x0);

19495

+

19496

+ printf ("x1 = 0x");

19497

+ u.d = x1;

19498

+ for (i = 0; i < sizeof (double); i++)

19499

+ printf ("%.2x", u.uc[i]);

19500

+

19501

+ printf (",%*s %g\n", (int)(2 * (sizeof (long double) - sizeof (double))), "", x1);

19502

+ }

19503

+#endif

19504

+

19505

+ if (high != x0)

19506

+ abort ();

19507

+

19508

+ if (low != x1)

19509

+ abort ();

19510

+

19511

+ if (a != b)

19512

+ abort ();

19513

+

19514

+ if (x0 != high)

19515

+ abort ();

19516

+

19517

+ if (x1 != low)

19518

+ abort ();

19519

+

19520

+ return 0;

19521

+}

19522

Index: gcc/testsuite/gcc.target/powerpc/crypto-builtin-1.c

19523

===================================================================

19524

--- a/src/gcc/testsuite/gcc.target/powerpc/crypto-builtin-1.c (.../tags/gcc_4_8_2_release)

19525

+++ b/src/gcc/testsuite/gcc.target/powerpc/crypto-builtin-1.c (.../branches/gcc-4_8-branch)

19526

@@ -0,0 +1,130 @@

19527

+/* { dg-do compile { target { powerpc*-*-* } } } */

19528

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

19529

+/* { dg-require-effective-target powerpc_p8vector_ok } */

19530

+/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model -fno-unroll-loops -fno-unroll-all-loops" } */

19531

+

19532

+typedef vector unsigned long long crypto_t;

19533

+typedef vector unsigned long long v2di_t;

19534

+typedef vector unsigned int v4si_t;

19535

+typedef vector unsigned short v8hi_t;

19536

+typedef vector unsigned char v16qi_t;

19537

+

19538

+crypto_t crpyto1 (crypto_t a)

19539

+{

19540

+ return __builtin_crypto_vsbox (a);

19541

+}

19542

+

19543

+crypto_t crypto2 (crypto_t a, crypto_t b)

19544

+{

19545

+ return __builtin_crypto_vcipher (a, b);

19546

+}

19547

+

19548

+crypto_t crypto3 (crypto_t a, crypto_t b)

19549

+{

19550

+ return __builtin_crypto_vcipherlast (a, b);

19551

+}

19552

+

19553

+crypto_t crypto4 (crypto_t a, crypto_t b)

19554

+{

19555

+ return __builtin_crypto_vncipher (a, b);

19556

+}

19557

+

19558

+crypto_t crypto5 (crypto_t a, crypto_t b)

19559

+{

19560

+ return __builtin_crypto_vncipherlast (a, b);

19561

+}

19562

+

19563

+v16qi_t crypto6a (v16qi_t a, v16qi_t b, v16qi_t c)

19564

+{

19565

+ return __builtin_crypto_vpermxor (a, b, c);

19566

+}

19567

+

19568

+v8hi_t crypto6b (v8hi_t a, v8hi_t b, v8hi_t c)

19569

+{

19570

+ return __builtin_crypto_vpermxor (a, b, c);

19571

+}

19572

+

19573

+v4si_t crypto6c (v4si_t a, v4si_t b, v4si_t c)

19574

+{

19575

+ return __builtin_crypto_vpermxor (a, b, c);

19576

+}

19577

+

19578

+v2di_t crypto6d (v2di_t a, v2di_t b, v2di_t c)

19579

+{

19580

+ return __builtin_crypto_vpermxor (a, b, c);

19581

+}

19582

+

19583

+v16qi_t crypto7a (v16qi_t a, v16qi_t b)

19584

+{

19585

+ return __builtin_crypto_vpmsumb (a, b);

19586

+}

19587

+

19588

+v16qi_t crypto7b (v16qi_t a, v16qi_t b)

19589

+{

19590

+ return __builtin_crypto_vpmsum (a, b);

19591

+}

19592

+

19593

+v8hi_t crypto7c (v8hi_t a, v8hi_t b)

19594

+{

19595

+ return __builtin_crypto_vpmsumh (a, b);

19596

+}

19597

+

19598

+v8hi_t crypto7d (v8hi_t a, v8hi_t b)

19599

+{

19600

+ return __builtin_crypto_vpmsum (a, b);

19601

+}

19602

+

19603

+v4si_t crypto7e (v4si_t a, v4si_t b)

19604

+{

19605

+ return __builtin_crypto_vpmsumw (a, b);

19606

+}

19607

+

19608

+v4si_t crypto7f (v4si_t a, v4si_t b)

19609

+{

19610

+ return __builtin_crypto_vpmsum (a, b);

19611

+}

19612

+

19613

+v2di_t crypto7g (v2di_t a, v2di_t b)

19614

+{

19615

+ return __builtin_crypto_vpmsumd (a, b);

19616

+}

19617

+

19618

+v2di_t crypto7h (v2di_t a, v2di_t b)

19619

+{

19620

+ return __builtin_crypto_vpmsum (a, b);

19621

+}

19622

+

19623

+v2di_t crypto8a (v2di_t a)

19624

+{

19625

+ return __builtin_crypto_vshasigmad (a, 0, 8);

19626

+}

19627

+

19628

+v2di_t crypto8b (v2di_t a)

19629

+{

19630

+ return __builtin_crypto_vshasigma (a, 0, 8);

19631

+}

19632

+

19633

+v4si_t crypto8c (v4si_t a)

19634

+{

19635

+ return __builtin_crypto_vshasigmaw (a, 1, 15);

19636

+}

19637

+

19638

+v4si_t crypto8d (v4si_t a)

19639

+{

19640

+ return __builtin_crypto_vshasigma (a, 1, 15);

19641

+}

19642

+

19643

+/* Note space is used after the instruction so that vcipherlast does not match

19644

+ vcipher. */

19645

+/* { dg-final { scan-assembler-times "vcipher " 1 } } */

19646

+/* { dg-final { scan-assembler-times "vcipherlast " 1 } } */

19647

+/* { dg-final { scan-assembler-times "vncipher " 1 } } */

19648

+/* { dg-final { scan-assembler-times "vncipherlast " 1 } } */

19649

+/* { dg-final { scan-assembler-times "vpermxor " 4 } } */

19650

+/* { dg-final { scan-assembler-times "vpmsumb " 2 } } */

19651

+/* { dg-final { scan-assembler-times "vpmsumd " 2 } } */

19652

+/* { dg-final { scan-assembler-times "vpmsumh " 2 } } */

19653

+/* { dg-final { scan-assembler-times "vpmsumw " 2 } } */

19654

+/* { dg-final { scan-assembler-times "vsbox " 1 } } */

19655

+/* { dg-final { scan-assembler-times "vshasigmad " 2 } } */

19656

+/* { dg-final { scan-assembler-times "vshasigmaw " 2 } } */

19657

Index: gcc/testsuite/gcc.target/powerpc/pr42747.c

19658

===================================================================

19659

--- a/src/gcc/testsuite/gcc.target/powerpc/pr42747.c (.../tags/gcc_4_8_2_release)

19660

+++ b/src/gcc/testsuite/gcc.target/powerpc/pr42747.c (.../branches/gcc-4_8-branch)

19661

@@ -5,4 +5,4 @@

19662

19663

double foo (double x) { return __builtin_sqrt (x); }

19664

19665

-/* { dg-final { scan-assembler "xssqrtdp" } } */

19666

+/* { dg-final { scan-assembler "xssqrtdp\|fsqrt" } } */

19667

Index: gcc/testsuite/gcc.target/powerpc/dfp-dd-2.c

19668

===================================================================

19669

--- a/src/gcc/testsuite/gcc.target/powerpc/dfp-dd-2.c (.../tags/gcc_4_8_2_release)

19670

+++ b/src/gcc/testsuite/gcc.target/powerpc/dfp-dd-2.c (.../branches/gcc-4_8-branch)

19671

@@ -0,0 +1,26 @@

19672

+/* Test generation of DFP instructions for POWER6. */

19673

+/* { dg-do compile { target { powerpc*-*-linux* && powerpc_fprs } } } */

19674

+/* { dg-options "-std=gnu99 -O1 -mcpu=power6" } */

19675

+

19676

+/* { dg-final { scan-assembler-times "fneg" 1 } } */

19677

+/* { dg-final { scan-assembler-times "fabs" 1 } } */

19678

+/* { dg-final { scan-assembler-times "fnabs" 1 } } */

19679

+/* { dg-final { scan-assembler-times "fmr" 0 } } */

19680

+

19681

+_Decimal64

19682

+func1 (_Decimal64 a, _Decimal64 b)

19683

+{

19684

+ return -b;

19685

+}

19686

+

19687

+_Decimal64

19688

+func2 (_Decimal64 a, _Decimal64 b)

19689

+{

19690

+ return __builtin_fabsd64 (b);

19691

+}

19692

+

19693

+_Decimal64

19694

+func3 (_Decimal64 a, _Decimal64 b)

19695

+{

19696

+ return - __builtin_fabsd64 (b);

19697

+}

19698

Index: gcc/testsuite/gcc.target/powerpc/direct-move-float1.c

19699

===================================================================

19700

--- a/src/gcc/testsuite/gcc.target/powerpc/direct-move-float1.c (.../tags/gcc_4_8_2_release)

19701

+++ b/src/gcc/testsuite/gcc.target/powerpc/direct-move-float1.c (.../branches/gcc-4_8-branch)

19702

@@ -0,0 +1,18 @@

19703

+/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */

19704

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

19705

+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */

19706

+/* { dg-require-effective-target powerpc_p8vector_ok } */

19707

+/* { dg-options "-mcpu=power8 -O2" } */

19708

+/* { dg-final { scan-assembler "mtvsrd" } } */

19709

+/* { dg-final { scan-assembler "mfvsrd" } } */

19710

+/* { dg-final { scan-assembler "xscvdpspn" } } */

19711

+/* { dg-final { scan-assembler "xscvspdpn" } } */

19712

+

19713

+/* Check code generation for direct move for float types. */

19714

+

19715

+#define TYPE float

19716

+#define IS_FLOAT 1

19717

+#define NO_ALTIVEC 1

19718

+#define VSX_REG_ATTR "ww"

19719

+

19720

+#include "direct-move.h"

19721

Index: gcc/testsuite/gcc.target/powerpc/dfp-td-2.c

19722

===================================================================

19723

--- a/src/gcc/testsuite/gcc.target/powerpc/dfp-td-2.c (.../tags/gcc_4_8_2_release)

19724

+++ b/src/gcc/testsuite/gcc.target/powerpc/dfp-td-2.c (.../branches/gcc-4_8-branch)

19725

@@ -0,0 +1,29 @@

19726

+/* Test generation of DFP instructions for POWER6. */

19727

+/* { dg-do compile { target { powerpc*-*-linux* && powerpc_fprs } } } */

19728

+/* { dg-options "-std=gnu99 -O1 -mcpu=power6" } */

19729

+

19730

+/* { dg-final { scan-assembler-times "fneg" 1 } } */

19731

+/* { dg-final { scan-assembler-times "fabs" 1 } } */

19732

+/* { dg-final { scan-assembler-times "fnabs" 1 } } */

19733

+/* { dg-final { scan-assembler-times "fmr" 0 } } */

19734

+

19735

+/* These tests verify we only generate fneg, fabs and fnabs

19736

+ instructions and no fmr's since these are done in place. */

19737

+

19738

+_Decimal128

19739

+func1 (_Decimal128 a)

19740

+{

19741

+ return -a;

19742

+}

19743

+

19744

+_Decimal128

19745

+func2 (_Decimal128 a)

19746

+{

19747

+ return __builtin_fabsd128 (a);

19748

+}

19749

+

19750

+_Decimal128

19751

+func3 (_Decimal128 a)

19752

+{

19753

+ return - __builtin_fabsd128 (a);

19754

+}

19755

Index: gcc/testsuite/gcc.target/powerpc/p8vector-builtin-5.c

19756

===================================================================

19757

--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-5.c (.../tags/gcc_4_8_2_release)

19758

+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-5.c (.../branches/gcc-4_8-branch)

19759

@@ -0,0 +1,105 @@

19760

+/* { dg-do compile { target { powerpc*-*-* } } } */

19761

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

19762

+/* { dg-require-effective-target powerpc_p8vector_ok } */

19763

+/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model -fno-unroll-loops -fno-unroll-all-loops" } */

19764

+

19765

+#include <altivec.h>

19766

+

19767

+#ifndef SIZE

19768

+#define SIZE 1024

19769

+#endif

19770

+

19771

+#ifndef ALIGN

19772

+#define ALIGN 32

19773

+#endif

19774

+

19775

+#ifndef ATTR_ALIGN

19776

+#define ATTR_ALIGN __attribute__((__aligned__(ALIGN)))

19777

+#endif

19778

+

19779

+#define DOIT(TYPE, PREFIX) \

19780

+TYPE PREFIX ## _eqv_builtin (TYPE a, TYPE b) \

19781

+{ \

19782

+ return vec_eqv (a, b); \

19783

+} \

19784

+ \

19785

+TYPE PREFIX ## _eqv_arith (TYPE a, TYPE b) \

19786

+{ \

19787

+ return ~(a ^ b); \

19788

+} \

19789

+ \

19790

+TYPE PREFIX ## _nand_builtin (TYPE a, TYPE b) \

19791

+{ \

19792

+ return vec_nand (a, b); \

19793

+} \

19794

+ \

19795

+TYPE PREFIX ## _nand_arith1 (TYPE a, TYPE b) \

19796

+{ \

19797

+ return ~(a & b); \

19798

+} \

19799

+ \

19800

+TYPE PREFIX ## _nand_arith2 (TYPE a, TYPE b) \

19801

+{ \

19802

+ return (~a) | (~b); \

19803

+} \

19804

+ \

19805

+TYPE PREFIX ## _orc_builtin (TYPE a, TYPE b) \

19806

+{ \

19807

+ return vec_orc (a, b); \

19808

+} \

19809

+ \

19810

+TYPE PREFIX ## _orc_arith1 (TYPE a, TYPE b) \

19811

+{ \

19812

+ return (~ a) | b; \

19813

+} \

19814

+ \

19815

+TYPE PREFIX ## _orc_arith2 (TYPE a, TYPE b) \

19816

+{ \

19817

+ return a | (~ b); \

19818

+}

19819

+

19820

+#define DOIT_FLOAT(TYPE, PREFIX) \

19821

+TYPE PREFIX ## _eqv_builtin (TYPE a, TYPE b) \

19822

+{ \

19823

+ return vec_eqv (a, b); \

19824

+} \

19825

+ \

19826

+TYPE PREFIX ## _nand_builtin (TYPE a, TYPE b) \

19827

+{ \

19828

+ return vec_nand (a, b); \

19829

+} \

19830

+ \

19831

+TYPE PREFIX ## _orc_builtin (TYPE a, TYPE b) \

19832

+{ \

19833

+ return vec_orc (a, b); \

19834

+}

19835

+

19836

+typedef vector signed char sign_char_vec;

19837

+typedef vector short sign_short_vec;

19838

+typedef vector int sign_int_vec;

19839

+typedef vector long long sign_llong_vec;

19840

+

19841

+typedef vector unsigned char uns_char_vec;

19842

+typedef vector unsigned short uns_short_vec;

19843

+typedef vector unsigned int uns_int_vec;

19844

+typedef vector unsigned long long uns_llong_vec;

19845

+

19846

+typedef vector float float_vec;

19847

+typedef vector double double_vec;

19848

+

19849

+DOIT(sign_char_vec, sign_char)

19850

+DOIT(sign_short_vec, sign_short)

19851

+DOIT(sign_int_vec, sign_int)

19852

+DOIT(sign_llong_vec, sign_llong)

19853

+

19854

+DOIT(uns_char_vec, uns_char)

19855

+DOIT(uns_short_vec, uns_short)

19856

+DOIT(uns_int_vec, uns_int)

19857

+DOIT(uns_llong_vec, uns_llong)

19858

+

19859

+DOIT_FLOAT(float_vec, float)

19860

+DOIT_FLOAT(double_vec, double)

19861

+

19862

+/* { dg-final { scan-assembler-times "xxleqv" 18 } } */

19863

+/* { dg-final { scan-assembler-times "xxlnand" 26 } } */

19864

+/* { dg-final { scan-assembler-times "xxlorc" 26 } } */

19865

Index: gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-5.c

19866

===================================================================

19867

--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-5.c (.../tags/gcc_4_8_2_release)

19868

+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-5.c (.../branches/gcc-4_8-branch)

19869

@@ -0,0 +1,87 @@

19870

+/* { dg-do compile { target { powerpc*-*-* } } } */

19871

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

19872

+/* { dg-require-effective-target powerpc_p8vector_ok } */

19873

+/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model -fno-unroll-loops -fno-unroll-all-loops" } */

19874

+

19875

+#ifndef SIZE

19876

+#define SIZE 1024

19877

+#endif

19878

+

19879

+#ifndef ALIGN

19880

+#define ALIGN 32

19881

+#endif

19882

+

19883

+#ifndef ATTR_ALIGN

19884

+#define ATTR_ALIGN __attribute__((__aligned__(ALIGN)))

19885

+#endif

19886

+

19887

+#ifndef TYPE

19888

+#define TYPE unsigned int

19889

+#endif

19890

+

19891

+TYPE in1 [SIZE] ATTR_ALIGN;

19892

+TYPE in2 [SIZE] ATTR_ALIGN;

19893

+TYPE eqv [SIZE] ATTR_ALIGN;

19894

+TYPE nand1[SIZE] ATTR_ALIGN;

19895

+TYPE nand2[SIZE] ATTR_ALIGN;

19896

+TYPE orc1 [SIZE] ATTR_ALIGN;

19897

+TYPE orc2 [SIZE] ATTR_ALIGN;

19898

+

19899

+void

19900

+do_eqv (void)

19901

+{

19902

+ unsigned long i;

19903

+

19904

+ for (i = 0; i < SIZE; i++)

19905

+ {

19906

+ eqv[i] = ~(in1[i] ^ in2[i]);

19907

+ }

19908

+}

19909

+

19910

+void

19911

+do_nand1 (void)

19912

+{

19913

+ unsigned long i;

19914

+

19915

+ for (i = 0; i < SIZE; i++)

19916

+ {

19917

+ nand1[i] = ~(in1[i] & in2[i]);

19918

+ }

19919

+}

19920

+

19921

+void

19922

+do_nand2 (void)

19923

+{

19924

+ unsigned long i;

19925

+

19926

+ for (i = 0; i < SIZE; i++)

19927

+ {

19928

+ nand2[i] = (~in1[i]) | (~in2[i]);

19929

+ }

19930

+}

19931

+

19932

+void

19933

+do_orc1 (void)

19934

+{

19935

+ unsigned long i;

19936

+

19937

+ for (i = 0; i < SIZE; i++)

19938

+ {

19939

+ orc1[i] = (~in1[i]) | in2[i];

19940

+ }

19941

+}

19942

+

19943

+void

19944

+do_orc2 (void)

19945

+{

19946

+ unsigned long i;

19947

+

19948

+ for (i = 0; i < SIZE; i++)

19949

+ {

19950

+ orc1[i] = in1[i] | (~in2[i]);

19951

+ }

19952

+}

19953

+

19954

+/* { dg-final { scan-assembler-times "xxleqv" 1 } } */

19955

+/* { dg-final { scan-assembler-times "xxlnand" 2 } } */

19956

+/* { dg-final { scan-assembler-times "xxlorc" 2 } } */

19957

Index: gcc/testsuite/gcc.target/powerpc/pr57949-2.c

19958

===================================================================

19959

--- a/src/gcc/testsuite/gcc.target/powerpc/pr57949-2.c (.../tags/gcc_4_8_2_release)

19960

+++ b/src/gcc/testsuite/gcc.target/powerpc/pr57949-2.c (.../branches/gcc-4_8-branch)

19961

@@ -0,0 +1,20 @@

19962

+/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */

19963

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

19964

+/* { dg-skip-if "" { powerpc_elfv2 } { "*" } { "" } } */

19965

+/* { dg-options "-O2 -mcpu=power7" } */

19966

+

19967

+/* Verify that vs is not 16-byte aligned in the absence of -mno-compat-align-parm. */

19968

+

19969

+typedef float v4sf __attribute__ ((vector_size (16)));

19970

+struct s { long m; v4sf v; };

19971

+long n;

19972

+v4sf ve;

19973

+

19974

+void pr57949 (long d1, long d2, long d3, long d4, long d5, long d6,

19975

+ long d7, long d8, long d9, struct s vs) {

19976

+ n = vs.m;

19977

+ ve = vs.v;

19978

+}

19979

+

19980

+/* { dg-final { scan-assembler "ld .\*,136\$1\$" } } */

19981

+/* { dg-final { scan-assembler "ld .\*,120\$1\$" } } */

19982

Index: gcc/testsuite/gcc.target/powerpc/recip-5.c

19983

===================================================================

19984

--- a/src/gcc/testsuite/gcc.target/powerpc/recip-5.c (.../tags/gcc_4_8_2_release)

19985

+++ b/src/gcc/testsuite/gcc.target/powerpc/recip-5.c (.../branches/gcc-4_8-branch)

19986

@@ -4,8 +4,16 @@

19987

/* { dg-options "-O3 -ftree-vectorize -mrecip=all -ffast-math -mcpu=power7 -fno-unroll-loops" } */

19988

/* { dg-final { scan-assembler-times "xvredp" 4 } } */

19989

/* { dg-final { scan-assembler-times "xvresp" 5 } } */

19990

-/* { dg-final { scan-assembler-times "xsredp" 2 } } */

19991

-/* { dg-final { scan-assembler-times "fres" 2 } } */

19992

+/* { dg-final { scan-assembler-times "xsredp\|fre\ " 2 } } */

19993

+/* { dg-final { scan-assembler-times "xsresp\|fres" 2 } } */

19994

+/* { dg-final { scan-assembler-times "xsmulsp\|fmuls" 2 } } */

19995

+/* { dg-final { scan-assembler-times "xsnmsub.sp\|fnmsubs" 2 } } */

19996

+/* { dg-final { scan-assembler-times "xsmuldp\|fmul\ " 2 } } */

19997

+/* { dg-final { scan-assembler-times "xsnmsub.dp\|fnmsub\ " 4 } } */

19998

+/* { dg-final { scan-assembler-times "xvmulsp" 7 } } */

19999

+/* { dg-final { scan-assembler-times "xvnmsub.sp" 5 } } */

20000

+/* { dg-final { scan-assembler-times "xvmuldp" 6 } } */

20001

+/* { dg-final { scan-assembler-times "xvnmsub.dp" 8 } } */

20002

20003

#include <altivec.h>

20004

20005

Index: gcc/testsuite/gcc.target/powerpc/pack03.c

20006

===================================================================

20007

--- a/src/gcc/testsuite/gcc.target/powerpc/pack03.c (.../tags/gcc_4_8_2_release)

20008

+++ b/src/gcc/testsuite/gcc.target/powerpc/pack03.c (.../branches/gcc-4_8-branch)

20009

@@ -0,0 +1,88 @@

20010

+/* { dg-do run { target { powerpc*-*-linux* } } } */

20011

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

20012

+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */

20013

+/* { dg-require-effective-target dfprt } */

20014

+/* { dg-options "-O2 -mhard-dfp" } */

20015

+

20016

+#include <stddef.h>

20017

+#include <stdlib.h>

20018

+#include <math.h>

20019

+

20020

+#ifdef DEBUG

20021

+#include <stdio.h>

20022

+#endif

20023

+

20024

+int

20025

+main (void)

20026

+{

20027

+ _Decimal128 one = (_Decimal128)1.0;

20028

+ _Decimal128 two = (_Decimal128)2.0;

20029

+ _Decimal128 ten = (_Decimal128)10.0;

20030

+ _Decimal128 a = one;

20031

+ _Decimal128 b;

20032

+ _Decimal128 c;

20033

+ unsigned long long x0;

20034

+ unsigned long long x1;

20035

+ size_t i;

20036

+

20037

+ for (i = 0; i < 25; i++)

20038

+ a *= ten;

20039

+

20040

+ a += two;

20041

+

20042

+ x0 = __builtin_unpack_dec128 (a, 0);

20043

+ x1 = __builtin_unpack_dec128 (a, 1);

20044

+ b = __builtin_pack_dec128 (x0, x1);

20045

+ c = __builtin_dscliq (one, 25) + two;

20046

+

20047

+#ifdef DEBUG

20048

+ {

20049

+ union {

20050

+ _Decimal128 d;

20051

+ unsigned long long ull;

20052

+ unsigned char uc[sizeof (_Decimal128)];

20053

+ } u;

20054

+

20055

+ printf ("a = 0x");

20056

+ u.d = a;

20057

+ for (i = 0; i < sizeof (_Decimal128); i++)

20058

+ printf ("%.2x", u.uc[i]);

20059

+

20060

+ printf (", %Lg\n", (long double)a);

20061

+

20062

+ printf ("b = 0x");

20063

+ u.d = b;

20064

+ for (i = 0; i < sizeof (_Decimal128); i++)

20065

+ printf ("%.2x", u.uc[i]);

20066

+

20067

+ printf (", %Lg\n", (long double)b);

20068

+

20069

+ printf ("c = 0x");

20070

+ u.d = c;

20071

+ for (i = 0; i < sizeof (_Decimal128); i++)

20072

+ printf ("%.2x", u.uc[i]);

20073

+

20074

+ printf (", %Lg\n", (long double)c);

20075

+

20076

+ printf ("x0 = 0x");

20077

+ u.ull = x0;

20078

+ for (i = 0; i < sizeof (unsigned long long); i++)

20079

+ printf ("%.2x", u.uc[i]);

20080

+

20081

+ printf ("\nx1 = 0x");

20082

+ u.ull = x1;

20083

+ for (i = 0; i < sizeof (unsigned long long); i++)

20084

+ printf ("%.2x", u.uc[i]);

20085

+

20086

+ printf ("\n");

20087

+ }

20088

+#endif

20089

+

20090

+ if (a != b)

20091

+ abort ();

20092

+

20093

+ if (a != c)

20094

+ abort ();

20095

+

20096

+ return 0;

20097

+}

20098

Index: gcc/testsuite/gcc.target/powerpc/ppc64-abi-1.c

20099

===================================================================

20100

--- a/src/gcc/testsuite/gcc.target/powerpc/ppc64-abi-1.c (.../tags/gcc_4_8_2_release)

20101

+++ b/src/gcc/testsuite/gcc.target/powerpc/ppc64-abi-1.c (.../branches/gcc-4_8-branch)

20102

@@ -89,8 +89,10 @@

20103

long a1;

20104

long a2;

20105

long a3;

20106

+#if _CALL_ELF != 2

20107

long a4;

20108

long a5;

20109

+#endif

20110

parm_t slot[100];

20111

} stack_frame_t;

20112

20113

Index: gcc/testsuite/gcc.target/powerpc/direct-move-float2.c

20114

===================================================================

20115

--- a/src/gcc/testsuite/gcc.target/powerpc/direct-move-float2.c (.../tags/gcc_4_8_2_release)

20116

+++ b/src/gcc/testsuite/gcc.target/powerpc/direct-move-float2.c (.../branches/gcc-4_8-branch)

20117

@@ -0,0 +1,15 @@

20118

+/* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */

20119

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

20120

+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */

20121

+/* { dg-require-effective-target p8vector_hw } */

20122

+/* { dg-options "-mcpu=power8 -O2" } */

20123

+

20124

+/* Check whether we get the right bits for direct move at runtime. */

20125

+

20126

+#define TYPE float

20127

+#define IS_FLOAT 1

20128

+#define NO_ALTIVEC 1

20129

+#define DO_MAIN

20130

+#define VSX_REG_ATTR "ww"

20131

+

20132

+#include "direct-move.h"

20133

Index: gcc/testsuite/gcc.target/powerpc/direct-move-double1.c

20134

===================================================================

20135

--- a/src/gcc/testsuite/gcc.target/powerpc/direct-move-double1.c (.../tags/gcc_4_8_2_release)

20136

+++ b/src/gcc/testsuite/gcc.target/powerpc/direct-move-double1.c (.../branches/gcc-4_8-branch)

20137

@@ -0,0 +1,16 @@

20138

+/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */

20139

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

20140

+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */

20141

+/* { dg-require-effective-target powerpc_p8vector_ok } */

20142

+/* { dg-options "-mcpu=power8 -O2" } */

20143

+/* { dg-final { scan-assembler "mtvsrd" } } */

20144

+/* { dg-final { scan-assembler "mfvsrd" } } */

20145

+

20146

+/* Check code generation for direct move for double types. */

20147

+

20148

+#define TYPE double

20149

+#define IS_FLOAT 1

20150

+#define NO_ALTIVEC 1

20151

+#define VSX_REG_ATTR "ws"

20152

+

20153

+#include "direct-move.h"

20154

Index: gcc/testsuite/gcc.target/powerpc/dfp-td-3.c

20155

===================================================================

20156

--- a/src/gcc/testsuite/gcc.target/powerpc/dfp-td-3.c (.../tags/gcc_4_8_2_release)

20157

+++ b/src/gcc/testsuite/gcc.target/powerpc/dfp-td-3.c (.../branches/gcc-4_8-branch)

20158

@@ -0,0 +1,29 @@

20159

+/* Test generation of DFP instructions for POWER6. */

20160

+/* { dg-do compile { target { powerpc*-*-linux* && powerpc_fprs } } } */

20161

+/* { dg-options "-std=gnu99 -O1 -mcpu=power6" } */

20162

+

20163

+/* { dg-final { scan-assembler-times "fneg" 1 } } */

20164

+/* { dg-final { scan-assembler-times "fabs" 1 } } */

20165

+/* { dg-final { scan-assembler-times "fnabs" 1 } } */

20166

+/* { dg-final { scan-assembler-times "fmr" 3 } } */

20167

+

20168

+/* These tests verify we generate fneg, fabs and fnabs and

20169

+ associated fmr's since these are not done in place. */

20170

+

20171

+_Decimal128

20172

+func1 (_Decimal128 a, _Decimal128 b)

20173

+{

20174

+ return -b;

20175

+}

20176

+

20177

+_Decimal128

20178

+func2 (_Decimal128 a, _Decimal128 b)

20179

+{

20180

+ return __builtin_fabsd128 (b);

20181

+}

20182

+

20183

+_Decimal128

20184

+func3 (_Decimal128 a, _Decimal128 b)

20185

+{

20186

+ return - __builtin_fabsd128 (b);

20187

+}

20188

Index: gcc/testsuite/gcc.target/powerpc/p8vector-builtin-6.c

20189

===================================================================

20190

--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-6.c (.../tags/gcc_4_8_2_release)

20191

+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-6.c (.../branches/gcc-4_8-branch)

20192

@@ -0,0 +1,10 @@

20193

+/* { dg-do compile { target { powerpc*-*-* } } } */

20194

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

20195

+/* { dg-require-effective-target powerpc_p8vector_ok } */

20196

+/* { dg-options "-mcpu=power8 -O2" } */

20197

+

20198

+vector float dbl_to_float_p8 (double x) { return __builtin_vsx_xscvdpspn (x); }

20199

+double float_to_dbl_p8 (vector float x) { return __builtin_vsx_xscvspdpn (x); }

20200

+

20201

+/* { dg-final { scan-assembler "xscvdpspn" } } */

20202

+/* { dg-final { scan-assembler "xscvspdpn" } } */

20203

Index: gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c

20204

===================================================================

20205

--- a/src/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c (.../tags/gcc_4_8_2_release)

20206

+++ b/src/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c (.../branches/gcc-4_8-branch)

20207

@@ -16,9 +16,9 @@

20208

/* { dg-final { scan-assembler "xvrspiz" } } */

20209

/* { dg-final { scan-assembler "xsrdpi" } } */

20210

/* { dg-final { scan-assembler "xsrdpic" } } */

20211

-/* { dg-final { scan-assembler "xsrdpim" } } */

20212

-/* { dg-final { scan-assembler "xsrdpip" } } */

20213

-/* { dg-final { scan-assembler "xsrdpiz" } } */

20214

+/* { dg-final { scan-assembler "xsrdpim\|frim" } } */

20215

+/* { dg-final { scan-assembler "xsrdpip\|frip" } } */

20216

+/* { dg-final { scan-assembler "xsrdpiz\|friz" } } */

20217

/* { dg-final { scan-assembler "xsmaxdp" } } */

20218

/* { dg-final { scan-assembler "xsmindp" } } */

20219

/* { dg-final { scan-assembler "xxland" } } */

20220

Index: gcc/testsuite/gcc.target/powerpc/htm-builtin-1.c

20221

===================================================================

20222

--- a/src/gcc/testsuite/gcc.target/powerpc/htm-builtin-1.c (.../tags/gcc_4_8_2_release)

20223

+++ b/src/gcc/testsuite/gcc.target/powerpc/htm-builtin-1.c (.../branches/gcc-4_8-branch)

20224

@@ -0,0 +1,51 @@

20225

+/* { dg-do compile { target { powerpc*-*-* } } } */

20226

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

20227

+/* { dg-require-effective-target powerpc_htm_ok } */

20228

+/* { dg-options "-O2 -mhtm" } */

20229

+

20230

+/* { dg-final { scan-assembler-times "tbegin\\." 1 } } */

20231

+/* { dg-final { scan-assembler-times "tend\\." 2 } } */

20232

+/* { dg-final { scan-assembler-times "tabort\\." 2 } } */

20233

+/* { dg-final { scan-assembler-times "tabortdc\\." 1 } } */

20234

+/* { dg-final { scan-assembler-times "tabortdci\\." 1 } } */

20235

+/* { dg-final { scan-assembler-times "tabortwc\\." 1 } } */

20236

+/* { dg-final { scan-assembler-times "tabortwci\\." 2 } } */

20237

+/* { dg-final { scan-assembler-times "tcheck\\." 1 } } */

20238

+/* { dg-final { scan-assembler-times "trechkpt\\." 1 } } */

20239

+/* { dg-final { scan-assembler-times "treclaim\\." 1 } } */

20240

+/* { dg-final { scan-assembler-times "tsr\\." 3 } } */

20241

+/* { dg-final { scan-assembler-times "mfspr" 4 } } */

20242

+/* { dg-final { scan-assembler-times "mtspr" 4 } } */

20243

+

20244

+void use_builtins (long *p, char code, long *a, long *b)

20245

+{

20246

+ p[0] = __builtin_tbegin (0);

20247

+ p[1] = __builtin_tend (0);

20248

+ p[2] = __builtin_tendall ();

20249

+ p[3] = __builtin_tabort (0);

20250

+ p[4] = __builtin_tabort (code);

20251

+

20252

+ p[5] = __builtin_tabortdc (0xf, a[5], b[5]);

20253

+ p[6] = __builtin_tabortdci (0xf, a[6], 13);

20254

+ p[7] = __builtin_tabortwc (0xf, a[7], b[7]);

20255

+ p[8] = __builtin_tabortwci (0xf, a[8], 13);

20256

+

20257

+ p[9] = __builtin_tcheck (5);

20258

+ p[10] = __builtin_trechkpt ();

20259

+ p[11] = __builtin_treclaim (0);

20260

+ p[12] = __builtin_tresume ();

20261

+ p[13] = __builtin_tsuspend ();

20262

+ p[14] = __builtin_tsr (0);

20263

+ p[15] = __builtin_ttest (); /* This expands to a tabortwci. */

20264

+

20265

+

20266

+ p[16] = __builtin_get_texasr ();

20267

+ p[17] = __builtin_get_texasru ();

20268

+ p[18] = __builtin_get_tfhar ();

20269

+ p[19] = __builtin_get_tfiar ();

20270

+

20271

+ __builtin_set_texasr (a[20]);

20272

+ __builtin_set_texasru (a[21]);

20273

+ __builtin_set_tfhar (a[22]);

20274

+ __builtin_set_tfiar (a[23]);

20275

+}

20276

Index: gcc/testsuite/gcc.target/powerpc/bool.c

20277

===================================================================

20278

--- a/src/gcc/testsuite/gcc.target/powerpc/bool.c (.../tags/gcc_4_8_2_release)

20279

+++ b/src/gcc/testsuite/gcc.target/powerpc/bool.c (.../branches/gcc-4_8-branch)

20280

@@ -0,0 +1,14 @@

20281

+/* { dg-do compile { target { powerpc*-*-* } } } */

20282

+/* { dg-options "-O2" } */

20283

+/* { dg-final { scan-assembler "eqv" } } */

20284

+/* { dg-final { scan-assembler "nand" } } */

20285

+/* { dg-final { scan-assembler "nor" } } */

20286

+

20287

+#ifndef TYPE

20288

+#define TYPE unsigned long

20289

+#endif

20290

+

20291

+TYPE op1 (TYPE a, TYPE b) { return ~(a ^ b); } /* eqv */

20292

+TYPE op2 (TYPE a, TYPE b) { return ~(a & b); } /* nand */

20293

+TYPE op3 (TYPE a, TYPE b) { return ~(a | b); } /* nor */

20294

+

20295

Index: gcc/testsuite/gcc.target/powerpc/bool2-p5.c

20296

===================================================================

20297

--- a/src/gcc/testsuite/gcc.target/powerpc/bool2-p5.c (.../tags/gcc_4_8_2_release)

20298

+++ b/src/gcc/testsuite/gcc.target/powerpc/bool2-p5.c (.../branches/gcc-4_8-branch)

20299

@@ -0,0 +1,32 @@

20300

+/* { dg-do compile { target { powerpc*-*-* } } } */

20301

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

20302

+/* { dg-require-effective-target powerpc_altivec_ok } */

20303

+/* { dg-options "-O2 -mcpu=power5 -mabi=altivec -mno-altivec -mno-vsx" } */

20304

+/* { dg-final { scan-assembler "\[ \t\]and " } } */

20305

+/* { dg-final { scan-assembler "\[ \t\]or " } } */

20306

+/* { dg-final { scan-assembler "\[ \t\]xor " } } */

20307

+/* { dg-final { scan-assembler "\[ \t\]nor " } } */

20308

+/* { dg-final { scan-assembler "\[ \t\]andc " } } */

20309

+/* { dg-final { scan-assembler "\[ \t\]eqv " } } */

20310

+/* { dg-final { scan-assembler "\[ \t\]orc " } } */

20311

+/* { dg-final { scan-assembler "\[ \t\]nand " } } */

20312

+/* { dg-final { scan-assembler-not "\[ \t\]vand " } } */

20313

+/* { dg-final { scan-assembler-not "\[ \t\]vandc " } } */

20314

+/* { dg-final { scan-assembler-not "\[ \t\]vor " } } */

20315

+/* { dg-final { scan-assembler-not "\[ \t\]vxor " } } */

20316

+/* { dg-final { scan-assembler-not "\[ \t\]vnor " } } */

20317

+/* { dg-final { scan-assembler-not "\[ \t\]xxland " } } */

20318

+/* { dg-final { scan-assembler-not "\[ \t\]xxlor " } } */

20319

+/* { dg-final { scan-assembler-not "\[ \t\]xxlxor " } } */

20320

+/* { dg-final { scan-assembler-not "\[ \t\]xxlnor " } } */

20321

+/* { dg-final { scan-assembler-not "\[ \t\]xxlandc " } } */

20322

+/* { dg-final { scan-assembler-not "\[ \t\]xxleqv " } } */

20323

+/* { dg-final { scan-assembler-not "\[ \t\]xxlorc " } } */

20324

+/* { dg-final { scan-assembler-not "\[ \t\]xxlnand " } } */

20325

+

20326

+#ifndef TYPE

20327

+typedef int v4si __attribute__ ((vector_size (16)));

20328

+#define TYPE v4si

20329

+#endif

20330

+

20331

+#include "bool2.h"

20332

Index: gcc/testsuite/gcc.target/powerpc/fusion.c

20333

===================================================================

20334

--- a/src/gcc/testsuite/gcc.target/powerpc/fusion.c (.../tags/gcc_4_8_2_release)

20335

+++ b/src/gcc/testsuite/gcc.target/powerpc/fusion.c (.../branches/gcc-4_8-branch)

20336

@@ -0,0 +1,24 @@

20337

+/* { dg-do compile { target { powerpc*-*-* } } } */

20338

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

20339

+/* { dg-skip-if "" { powerpc*le-*-* } { "*" } { "" } } */

20340

+/* { dg-require-effective-target powerpc_p8vector_ok } */

20341

+/* { dg-options "-mcpu=power7 -mtune=power8 -O3" } */

20342

+

20343

+#define LARGE 0x12345

20344

+

20345

+int fusion_uchar (unsigned char *p){ return p[LARGE]; }

20346

+int fusion_schar (signed char *p){ return p[LARGE]; }

20347

+int fusion_ushort (unsigned short *p){ return p[LARGE]; }

20348

+int fusion_short (short *p){ return p[LARGE]; }

20349

+int fusion_int (int *p){ return p[LARGE]; }

20350

+unsigned fusion_uns (unsigned *p){ return p[LARGE]; }

20351

+

20352

+vector double fusion_vector (vector double *p) { return p[2]; }

20353

+

20354

+/* { dg-final { scan-assembler-times "gpr load fusion" 6 } } */

20355

+/* { dg-final { scan-assembler-times "vector load fusion" 1 } } */

20356

+/* { dg-final { scan-assembler-times "lbz" 2 } } */

20357

+/* { dg-final { scan-assembler-times "extsb" 1 } } */

20358

+/* { dg-final { scan-assembler-times "lhz" 2 } } */

20359

+/* { dg-final { scan-assembler-times "extsh" 1 } } */

20360

+/* { dg-final { scan-assembler-times "lwz" 2 } } */

20361

Index: gcc/testsuite/gcc.target/powerpc/ppc64-abi-2.c

20362

===================================================================

20363

--- a/src/gcc/testsuite/gcc.target/powerpc/ppc64-abi-2.c (.../tags/gcc_4_8_2_release)

20364

+++ b/src/gcc/testsuite/gcc.target/powerpc/ppc64-abi-2.c (.../branches/gcc-4_8-branch)

20365

@@ -107,8 +107,10 @@

20366

long a1;

20367

long a2;

20368

long a3;

20369

+#if _CALL_ELF != 2

20370

long a4;

20371

long a5;

20372

+#endif

20373

parm_t slot[100];

20374

} stack_frame_t;

20375

20376

@@ -119,6 +121,12 @@

20377

vector int v;

20378

} vector_int_t;

20379

20380

+#ifdef __LITTLE_ENDIAN__

20381

+#define MAKE_SLOT(x, y) ((long)x | ((long)y << 32))

20382

+#else

20383

+#define MAKE_SLOT(x, y) ((long)y | ((long)x << 32))

20384

+#endif

20385

+

20386

/* Paramter passing.

20387

s : gpr 3

20388

v : vpr 2

20389

@@ -226,8 +234,8 @@

20390

sp = __builtin_frame_address(0);

20391

sp = sp->backchain;

20392

20393

- if (sp->slot[2].l != 0x100000002ULL

20394

- || sp->slot[4].l != 0x500000006ULL)

20395

+ if (sp->slot[2].l != MAKE_SLOT (1, 2)

20396

+ || sp->slot[4].l != MAKE_SLOT (5, 6))

20397

abort();

20398

}

20399

20400

@@ -268,8 +276,8 @@

20401

sp = __builtin_frame_address(0);

20402

sp = sp->backchain;

20403

20404

- if (sp->slot[4].l != 0x100000002ULL

20405

- || sp->slot[6].l != 0x500000006ULL)

20406

+ if (sp->slot[4].l != MAKE_SLOT (1, 2)

20407

+ || sp->slot[6].l != MAKE_SLOT (5, 6))

20408

abort();

20409

}

20410

20411

@@ -296,8 +304,8 @@

20412

sp = __builtin_frame_address(0);

20413

sp = sp->backchain;

20414

20415

- if (sp->slot[4].l != 0x100000002ULL

20416

- || sp->slot[6].l != 0x500000006ULL)

20417

+ if (sp->slot[4].l != MAKE_SLOT (1, 2)

20418

+ || sp->slot[6].l != MAKE_SLOT (5, 6))

20419

abort();

20420

}

20421

20422

Index: gcc/testsuite/gcc.target/powerpc/direct-move-long1.c

20423

===================================================================

20424

--- a/src/gcc/testsuite/gcc.target/powerpc/direct-move-long1.c (.../tags/gcc_4_8_2_release)

20425

+++ b/src/gcc/testsuite/gcc.target/powerpc/direct-move-long1.c (.../branches/gcc-4_8-branch)

20426

@@ -0,0 +1,16 @@

20427

+/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */

20428

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

20429

+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */

20430

+/* { dg-require-effective-target powerpc_p8vector_ok } */

20431

+/* { dg-options "-mcpu=power8 -O2" } */

20432

+/* { dg-final { scan-assembler "mtvsrd" } } */

20433

+/* { dg-final { scan-assembler "mfvsrd" } } */

20434

+

20435

+/* Check code generation for direct move for long types. */

20436

+

20437

+#define TYPE long

20438

+#define IS_INT 1

20439

+#define NO_ALTIVEC 1

20440

+#define VSX_REG_ATTR "d"

20441

+

20442

+#include "direct-move.h"

20443

Index: gcc/testsuite/gcc.target/powerpc/direct-move-double2.c

20444

===================================================================

20445

--- a/src/gcc/testsuite/gcc.target/powerpc/direct-move-double2.c (.../tags/gcc_4_8_2_release)

20446

+++ b/src/gcc/testsuite/gcc.target/powerpc/direct-move-double2.c (.../branches/gcc-4_8-branch)

20447

@@ -0,0 +1,15 @@

20448

+/* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */

20449

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

20450

+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */

20451

+/* { dg-require-effective-target p8vector_hw } */

20452

+/* { dg-options "-mcpu=power8 -O2" } */

20453

+

20454

+/* Check whether we get the right bits for direct move at runtime. */

20455

+

20456

+#define TYPE double

20457

+#define IS_FLOAT 1

20458

+#define NO_ALTIVEC 1

20459

+#define DO_MAIN

20460

+#define VSX_REG_ATTR "ws"

20461

+

20462

+#include "direct-move.h"

20463

Index: gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c

20464

===================================================================

20465

--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c (.../tags/gcc_4_8_2_release)

20466

+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c (.../branches/gcc-4_8-branch)

20467

@@ -0,0 +1,32 @@

20468

+/* { dg-do compile { target { powerpc*-*-* } } } */

20469

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

20470

+/* { dg-require-effective-target powerpc_p8vector_ok } */

20471

+/* { dg-options "-mcpu=power8 -O2" } */

20472

+

20473

+#include <altivec.h>

20474

+

20475

+typedef vector int v_sign;

20476

+typedef vector unsigned int v_uns;

20477

+

20478

+v_sign even_sign (v_sign a, v_sign b)

20479

+{

20480

+ return vec_vmrgew (a, b);

20481

+}

20482

+

20483

+v_uns even_uns (v_uns a, v_uns b)

20484

+{

20485

+ return vec_vmrgew (a, b);

20486

+}

20487

+

20488

+v_sign odd_sign (v_sign a, v_sign b)

20489

+{

20490

+ return vec_vmrgow (a, b);

20491

+}

20492

+

20493

+v_uns odd_uns (v_uns a, v_uns b)

20494

+{

20495

+ return vec_vmrgow (a, b);

20496

+}

20497

+

20498

+/* { dg-final { scan-assembler-times "vmrgew" 2 } } */

20499

+/* { dg-final { scan-assembler-times "vmrgow" 2 } } */

20500

Index: gcc/testsuite/gcc.target/powerpc/bool2.h

20501

===================================================================

20502

--- a/src/gcc/testsuite/gcc.target/powerpc/bool2.h (.../tags/gcc_4_8_2_release)

20503

+++ b/src/gcc/testsuite/gcc.target/powerpc/bool2.h (.../branches/gcc-4_8-branch)

20504

@@ -0,0 +1,29 @@

20505

+/* Test various logical operations. */

20506

+

20507

+TYPE arg1 (TYPE p, TYPE q) { return p & q; } /* AND */

20508

+TYPE arg2 (TYPE p, TYPE q) { return p | q; } /* OR */

20509

+TYPE arg3 (TYPE p, TYPE q) { return p ^ q; } /* XOR */

20510

+TYPE arg4 (TYPE p) { return ~ p; } /* NOR */

20511

+TYPE arg5 (TYPE p, TYPE q) { return ~(p & q); } /* NAND */

20512

+TYPE arg6 (TYPE p, TYPE q) { return ~(p | q); } /* NOR */

20513

+TYPE arg7 (TYPE p, TYPE q) { return ~(p ^ q); } /* EQV */

20514

+TYPE arg8 (TYPE p, TYPE q) { return (~p) & q; } /* ANDC */

20515

+TYPE arg9 (TYPE p, TYPE q) { return (~p) | q; } /* ORC */

20516

+TYPE arg10(TYPE p, TYPE q) { return (~p) ^ q; } /* EQV */

20517

+TYPE arg11(TYPE p, TYPE q) { return p & (~q); } /* ANDC */

20518

+TYPE arg12(TYPE p, TYPE q) { return p | (~q); } /* ORC */

20519

+TYPE arg13(TYPE p, TYPE q) { return p ^ (~q); } /* EQV */

20520

+

20521

+void ptr1 (TYPE *p) { p[0] = p[1] & p[2]; } /* AND */

20522

+void ptr2 (TYPE *p) { p[0] = p[1] | p[2]; } /* OR */

20523

+void ptr3 (TYPE *p) { p[0] = p[1] ^ p[2]; } /* XOR */

20524

+void ptr4 (TYPE *p) { p[0] = ~p[1]; } /* NOR */

20525

+void ptr5 (TYPE *p) { p[0] = ~(p[1] & p[2]); } /* NAND */

20526

+void ptr6 (TYPE *p) { p[0] = ~(p[1] | p[2]); } /* NOR */

20527

+void ptr7 (TYPE *p) { p[0] = ~(p[1] ^ p[2]); } /* EQV */

20528

+void ptr8 (TYPE *p) { p[0] = ~(p[1]) & p[2]; } /* ANDC */

20529

+void ptr9 (TYPE *p) { p[0] = (~p[1]) | p[2]; } /* ORC */

20530

+void ptr10(TYPE *p) { p[0] = (~p[1]) ^ p[2]; } /* EQV */

20531

+void ptr11(TYPE *p) { p[0] = p[1] & (~p[2]); } /* ANDC */

20532

+void ptr12(TYPE *p) { p[0] = p[1] | (~p[2]); } /* ORC */

20533

+void ptr13(TYPE *p) { p[0] = p[1] ^ (~p[2]); } /* EQV */

20534

Index: gcc/testsuite/gcc.target/powerpc/pr48258-1.c

20535

===================================================================

20536

--- a/src/gcc/testsuite/gcc.target/powerpc/pr48258-1.c (.../tags/gcc_4_8_2_release)

20537

+++ b/src/gcc/testsuite/gcc.target/powerpc/pr48258-1.c (.../branches/gcc-4_8-branch)

20538

@@ -1,5 +1,6 @@

20539

/* { dg-do compile } */

20540

/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

20541

+/* { dg-skip-if "" { powerpc*le-*-* } { "*" } { "" } } */

20542

/* { dg-require-effective-target powerpc_vsx_ok } */

20543

/* { dg-options "-O3 -mcpu=power7 -mabi=altivec -ffast-math -fno-unroll-loops" } */

20544

/* { dg-final { scan-assembler-times "xvaddsp" 3 } } */

20545

Index: gcc/testsuite/gcc.target/powerpc/quad-atomic.c

20546

===================================================================

20547

--- a/src/gcc/testsuite/gcc.target/powerpc/quad-atomic.c (.../tags/gcc_4_8_2_release)

20548

+++ b/src/gcc/testsuite/gcc.target/powerpc/quad-atomic.c (.../branches/gcc-4_8-branch)

20549

@@ -0,0 +1,67 @@

20550

+/* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */

20551

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

20552

+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */

20553

+/* { dg-require-effective-target p8vector_hw } */

20554

+/* { dg-options "-mcpu=power8 -O2" } */

20555

+

20556

+/* Test whether we get the right bits for quad word atomic instructions. */

20557

+#include <stdlib.h>

20558

+

20559

+static __int128_t quad_fetch_and (__int128_t *, __int128_t value) __attribute__((__noinline__));

20560

+static __int128_t quad_fetch_or (__int128_t *, __int128_t value) __attribute__((__noinline__));

20561

+static __int128_t quad_fetch_add (__int128_t *, __int128_t value) __attribute__((__noinline__));

20562

+

20563

+static __int128_t

20564

+quad_fetch_and (__int128_t *ptr, __int128_t value)

20565

+{

20566

+ return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE);

20567

+}

20568

+

20569

+static __int128_t

20570

+quad_fetch_or (__int128_t *ptr, __int128_t value)

20571

+{

20572

+ return __atomic_fetch_or (ptr, value, __ATOMIC_ACQUIRE);

20573

+}

20574

+

20575

+static __int128_t

20576

+quad_fetch_add (__int128_t *ptr, __int128_t value)

20577

+{

20578

+ return __atomic_fetch_add (ptr, value, __ATOMIC_ACQUIRE);

20579

+}

20580

+

20581

+int

20582

+main (void)

20583

+{

20584

+ __int128_t result;

20585

+ __int128_t value;

20586

+ __int128_t and_input = ((((__int128_t) 0x1234567890abcdefULL) << 64) | ((__int128_t) 0xfedcba0987654321ULL));

20587

+ __int128_t and_value = ((((__int128_t) 0xfffffffffffffff0ULL) << 64) | ((__int128_t) 0xfffffffffffffff0ULL));

20588

+ __int128_t and_exp = ((((__int128_t) 0x1234567890abcde0ULL) << 64) | ((__int128_t) 0xfedcba0987654320ULL));

20589

+

20590

+ __int128_t or_input = ((((__int128_t) 0x1234567890abcdefULL) << 64) | ((__int128_t) 0xfedcba0987654321ULL));

20591

+ __int128_t or_value = ((((__int128_t) 0x0000000000000010ULL) << 64) | ((__int128_t) 0x000000000000000eULL));

20592

+ __int128_t or_exp = ((((__int128_t) 0x1234567890abcdffULL) << 64) | ((__int128_t) 0xfedcba098765432fULL));

20593

+

20594

+ __int128_t add_input = ((((__int128_t) 0x1234567890abcdefULL) << 64) | ((__int128_t) 0xfedcba0987654321ULL));

20595

+ __int128_t add_value = ((((__int128_t) 0x0000000001000000ULL) << 64) | ((__int128_t) 0x0000001000000000ULL));

20596

+ __int128_t add_exp = ((((__int128_t) 0x1234567891abcdefULL) << 64) | ((__int128_t) 0xfedcba1987654321ULL));

20597

+

20598

+

20599

+ value = and_input;

20600

+ result = quad_fetch_and (&value, and_value);

20601

+ if (result != and_input || value != and_exp)

20602

+ abort ();

20603

+

20604

+ value = or_input;

20605

+ result = quad_fetch_or (&value, or_value);

20606

+ if (result != or_input || value != or_exp)

20607

+ abort ();

20608

+

20609

+ value = add_input;

20610

+ result = quad_fetch_add (&value, add_value);

20611

+ if (result != add_input || value != add_exp)

20612

+ abort ();

20613

+

20614

+ return 0;

20615

+}

20616

+

20617

Index: gcc/testsuite/gcc.target/powerpc/ti_math1.c

20618

===================================================================

20619

--- a/src/gcc/testsuite/gcc.target/powerpc/ti_math1.c (.../tags/gcc_4_8_2_release)

20620

+++ b/src/gcc/testsuite/gcc.target/powerpc/ti_math1.c (.../branches/gcc-4_8-branch)

20621

@@ -0,0 +1,20 @@

20622

+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */

20623

+/* { dg-options "-O2" } */

20624

+/* { dg-final { scan-assembler-times "addc" 1 } } */

20625

+/* { dg-final { scan-assembler-times "adde" 1 } } */

20626

+/* { dg-final { scan-assembler-times "subfc" 1 } } */

20627

+/* { dg-final { scan-assembler-times "subfe" 1 } } */

20628

+/* { dg-final { scan-assembler-not "subf " } } */

20629

+

20630

+__int128

20631

+add_128 (__int128 *ptr, __int128 val)

20632

+{

20633

+ return (*ptr + val);

20634

+}

20635

+

20636

+__int128

20637

+sub_128 (__int128 *ptr, __int128 val)

20638

+{

20639

+ return (*ptr - val);

20640

+}

20641

+

20642

Index: gcc/testsuite/gcc.target/powerpc/atomic_load_store-p8.c

20643

===================================================================

20644

--- a/src/gcc/testsuite/gcc.target/powerpc/atomic_load_store-p8.c (.../tags/gcc_4_8_2_release)

20645

+++ b/src/gcc/testsuite/gcc.target/powerpc/atomic_load_store-p8.c (.../branches/gcc-4_8-branch)

20646

@@ -0,0 +1,22 @@

20647

+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */

20648

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

20649

+/* { dg-require-effective-target powerpc_p8vector_ok } */

20650

+/* { dg-options "-mcpu=power8 -O2" } */

20651

+/* { dg-final { scan-assembler-times "lq" 1 } } */

20652

+/* { dg-final { scan-assembler-times "stq" 1 } } */

20653

+/* { dg-final { scan-assembler-not "bl __atomic" } } */

20654

+/* { dg-final { scan-assembler-not "lqarx" } } */

20655

+/* { dg-final { scan-assembler-not "stqcx" } } */

20656

+

20657

+__int128

20658

+atomic_load_128_relaxed (__int128 *ptr)

20659

+{

20660

+ return __atomic_load_n (ptr, __ATOMIC_RELAXED);

20661

+}

20662

+

20663

+void

20664

+atomic_store_128_relaxed (__int128 *ptr, __int128 val)

20665

+{

20666

+ __atomic_store_n (ptr, val, __ATOMIC_RELAXED);

20667

+}

20668

+

20669

Index: gcc/testsuite/gcc.target/powerpc/ppc64-abi-dfp-1.c

20670

===================================================================

20671

--- a/src/gcc/testsuite/gcc.target/powerpc/ppc64-abi-dfp-1.c (.../tags/gcc_4_8_2_release)

20672

+++ b/src/gcc/testsuite/gcc.target/powerpc/ppc64-abi-dfp-1.c (.../branches/gcc-4_8-branch)

20673

@@ -33,15 +33,27 @@

20674

20675

20676

/* Wrapper to save the GPRs and FPRs and then jump to the real function. */

20677

+#if _CALL_ELF != 2

20678

+#define FUNC_START(NAME) \

20679

+ "\t.globl\t" NAME "\n\t" \

20680

+ ".section \".opd\",\"aw\"\n\t" \

20681

+ ".align 3\n" \

20682

+ NAME ":\n\t" \

20683

+ ".quad .L." NAME ",.TOC.@tocbase,0\n\t" \

20684

+ ".text\n\t" \

20685

+ ".type " NAME ", @function\n" \

20686

+ ".L." NAME ":\n\t"

20687

+#else

20688

+#define FUNC_START(NAME) \

20689

+ "\t.globl\t" NAME "\n\t" \

20690

+ ".text\n\t" \

20691

+ NAME ":\n" \

20692

+ "0:\taddis 2,12,(.TOC.-0b)@ha\n\t" \

20693

+ "addi 2,2,(.TOC.-0b)@l\n\t" \

20694

+ ".localentry " NAME ",.-" NAME "\n\t"

20695

+#endif

20696

#define WRAPPER(NAME) \

20697

-__asm__ ("\t.globl\t" #NAME "_asm\n\t" \

20698

- ".section \".opd\",\"aw\"\n\t" \

20699

- ".align 3\n" \

20700

- #NAME "_asm:\n\t" \

20701

- ".quad .L." #NAME "_asm,.TOC.@tocbase,0\n\t" \

20702

- ".text\n\t" \

20703

- ".type " #NAME "_asm, @function\n" \

20704

- ".L." #NAME "_asm:\n\t" \

20705

+__asm__ (FUNC_START (#NAME "_asm") \

20706

"ld 11,gparms@got(2)\n\t" \

20707

"std 3,0(11)\n\t" \

20708

"std 4,8(11)\n\t" \

20709

@@ -75,8 +87,10 @@

20710

long a1;

20711

long a2;

20712

long a3;

20713

+#if _CALL_ELF != 2

20714

long a4;

20715

long a5;

20716

+#endif

20717

unsigned long slot[100];

20718

} stack_frame_t;

20719

20720

Index: gcc/testsuite/gcc.target/powerpc/direct-move-long2.c

20721

===================================================================

20722

--- a/src/gcc/testsuite/gcc.target/powerpc/direct-move-long2.c (.../tags/gcc_4_8_2_release)

20723

+++ b/src/gcc/testsuite/gcc.target/powerpc/direct-move-long2.c (.../branches/gcc-4_8-branch)

20724

@@ -0,0 +1,15 @@

20725

+/* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */

20726

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

20727

+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */

20728

+/* { dg-require-effective-target p8vector_hw } */

20729

+/* { dg-options "-mcpu=power8 -O2" } */

20730

+

20731

+/* Check whether we get the right bits for direct move at runtime. */

20732

+

20733

+#define TYPE long

20734

+#define IS_INT 1

20735

+#define NO_ALTIVEC 1

20736

+#define DO_MAIN

20737

+#define VSX_REG_ATTR "d"

20738

+

20739

+#include "direct-move.h"

20740

Index: gcc/testsuite/gcc.target/powerpc/vsx-float0.c

20741

===================================================================

20742

--- a/src/gcc/testsuite/gcc.target/powerpc/vsx-float0.c (.../tags/gcc_4_8_2_release)

20743

+++ b/src/gcc/testsuite/gcc.target/powerpc/vsx-float0.c (.../branches/gcc-4_8-branch)

20744

@@ -0,0 +1,16 @@

20745

+/* { dg-do compile { target { powerpc*-*-* } } } */

20746

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

20747

+/* { dg-require-effective-target powerpc_vsx_ok } */

20748

+/* { dg-options "-O2 -mcpu=power7" } */

20749

+/* { dg-final { scan-assembler "xxlxor" } } */

20750

+

20751

+/* Test that we generate xxlor to clear a SFmode register. */

20752

+

20753

+float sum (float *p, unsigned long n)

20754

+{

20755

+ float sum = 0.0f; /* generate xxlxor instead of load */

20756

+ while (n-- > 0)

20757

+ sum += *p++;

20758

+

20759

+ return sum;

20760

+}

20761

Index: gcc/testsuite/gcc.target/powerpc/ppc-target-1.c

20762

===================================================================

20763

--- a/src/gcc/testsuite/gcc.target/powerpc/ppc-target-1.c (.../tags/gcc_4_8_2_release)

20764

+++ b/src/gcc/testsuite/gcc.target/powerpc/ppc-target-1.c (.../branches/gcc-4_8-branch)

20765

@@ -5,8 +5,7 @@

20766

/* { dg-final { scan-assembler-times "fabs" 3 } } */

20767

/* { dg-final { scan-assembler-times "fnabs" 3 } } */

20768

/* { dg-final { scan-assembler-times "fsel" 3 } } */

20769

-/* { dg-final { scan-assembler-times "fcpsgn" 3 } } */

20770

-/* { dg-final { scan-assembler-times "xscpsgndp" 1 } } */

20771

+/* { dg-final { scan-assembler-times "fcpsgn\|xscpsgndp" 4 } } */

20772

20773

double normal1 (double, double);

20774

double power5 (double, double) __attribute__((__target__("cpu=power5")));

20775

Index: gcc/testsuite/gcc.target/powerpc/pr60137.c

20776

===================================================================

20777

--- a/src/gcc/testsuite/gcc.target/powerpc/pr60137.c (.../tags/gcc_4_8_2_release)

20778

+++ b/src/gcc/testsuite/gcc.target/powerpc/pr60137.c (.../branches/gcc-4_8-branch)

20779

@@ -0,0 +1,17 @@

20780

+/* { dg-do compile { target { powerpc*-*-* } } } */

20781

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

20782

+/* { dg-require-effective-target powerpc_p8vector_ok } */

20783

+/* { dg-options "-mcpu=power8 -O3 -mno-vsx" } */

20784

+

20785

+/* target/60137, compiler got a 'could not split insn error'. */

20786

+

20787

+extern int target_flags;

20788

+extern char fixed_regs[53];

20789

+extern char call_used_regs[53];

20790

+

20791

+void init_reg_sets_1(void)

20792

+{

20793

+ int i;

20794

+ for (i = 0; i < 53; i++)

20795

+ fixed_regs[i] = call_used_regs[i] = (call_used_regs[i] &((target_flags & 0x02000000) ? 2 : 1)) != 0;

20796

+}

20797

Index: gcc/testsuite/gcc.target/powerpc/bool3.h

20798

===================================================================

20799

--- a/src/gcc/testsuite/gcc.target/powerpc/bool3.h (.../tags/gcc_4_8_2_release)

20800

+++ b/src/gcc/testsuite/gcc.target/powerpc/bool3.h (.../branches/gcc-4_8-branch)

20801

@@ -0,0 +1,186 @@

20802

+/* Test forcing 128-bit logical types into GPR registers. */

20803

+

20804

+#if defined(NO_ASM)

20805

+#define FORCE_REG1(X)

20806

+#define FORCE_REG2(X,Y)

20807

+

20808

+#else

20809

+#if defined(USE_ALTIVEC)

20810

+#define REG_CLASS "+v"

20811

+#define PRINT_REG1 "# altivec reg %0"

20812

+#define PRINT_REG2 "# altivec reg %0, %1"

20813

+

20814

+#elif defined(USE_FPR)

20815

+#define REG_CLASS "+d"

20816

+#define PRINT_REG1 "# fpr reg %0"

20817

+#define PRINT_REG2 "# fpr reg %0, %1"

20818

+

20819

+#elif defined(USE_VSX)

20820

+#define REG_CLASS "+wa"

20821

+#define PRINT_REG1 "# vsx reg %x0"

20822

+#define PRINT_REG2 "# vsx reg %x0, %x1"

20823

+

20824

+#else

20825

+#define REG_CLASS "+r"

20826

+#define PRINT_REG1 "# gpr reg %0"

20827

+#define PRINT_REG2 "# gpr reg %0, %1"

20828

+#endif

20829

+

20830

+#define FORCE_REG1(X) __asm__ (PRINT_REG1 : REG_CLASS (X))

20831

+#define FORCE_REG2(X,Y) __asm__ (PRINT_REG2 : REG_CLASS (X), REG_CLASS (Y))

20832

+#endif

20833

+

20834

+void ptr1 (TYPE *p)

20835

+{

20836

+ TYPE a = p[1];

20837

+ TYPE b = p[2];

20838

+ TYPE c;

20839

+

20840

+ FORCE_REG2 (a, b);

20841

+ c = a & b; /* AND */

20842

+ FORCE_REG1 (c);

20843

+ p[0] = c;

20844

+}

20845

+

20846

+void ptr2 (TYPE *p)

20847

+{

20848

+ TYPE a = p[1];

20849

+ TYPE b = p[2];

20850

+ TYPE c;

20851

+

20852

+ FORCE_REG2 (a, b);

20853

+ c = a | b; /* OR */

20854

+ FORCE_REG1 (c);

20855

+ p[0] = c;

20856

+}

20857

+

20858

+void ptr3 (TYPE *p)

20859

+{

20860

+ TYPE a = p[1];

20861

+ TYPE b = p[2];

20862

+ TYPE c;

20863

+

20864

+ FORCE_REG2 (a, b);

20865

+ c = a ^ b; /* XOR */

20866

+ FORCE_REG1 (c);

20867

+ p[0] = c;

20868

+}

20869

+

20870

+void ptr4 (TYPE *p)

20871

+{

20872

+ TYPE a = p[1];

20873

+ TYPE b;

20874

+

20875

+ FORCE_REG1 (a);

20876

+ b = ~a; /* NOR */

20877

+ FORCE_REG1 (b);

20878

+ p[0] = b;

20879

+}

20880

+

20881

+void ptr5 (TYPE *p)

20882

+{

20883

+ TYPE a = p[1];

20884

+ TYPE b = p[2];

20885

+ TYPE c;

20886

+

20887

+ FORCE_REG2 (a, b);

20888

+ c = ~(a & b); /* NAND */

20889

+ FORCE_REG1 (c);

20890

+ p[0] = c;

20891

+}

20892

+

20893

+void ptr6 (TYPE *p)

20894

+{

20895

+ TYPE a = p[1];

20896

+ TYPE b = p[2];

20897

+ TYPE c;

20898

+

20899

+ FORCE_REG2 (a, b);

20900

+ c = ~(a | b); /* AND */

20901

+ FORCE_REG1 (c);

20902

+ p[0] = c;

20903

+}

20904

+

20905

+void ptr7 (TYPE *p)

20906

+{

20907

+ TYPE a = p[1];

20908

+ TYPE b = p[2];

20909

+ TYPE c;

20910

+

20911

+ FORCE_REG2 (a, b);

20912

+ c = ~(a ^ b); /* EQV */

20913

+ FORCE_REG1 (c);

20914

+ p[0] = c;

20915

+}

20916

+

20917

+void ptr8 (TYPE *p)

20918

+{

20919

+ TYPE a = p[1];

20920

+ TYPE b = p[2];

20921

+ TYPE c;

20922

+

20923

+ FORCE_REG2 (a, b);

20924

+ c = (~a) & b; /* ANDC */

20925

+ FORCE_REG1 (c);

20926

+ p[0] = c;

20927

+}

20928

+

20929

+void ptr9 (TYPE *p)

20930

+{

20931

+ TYPE a = p[1];

20932

+ TYPE b = p[2];

20933

+ TYPE c;

20934

+

20935

+ FORCE_REG2 (a, b);

20936

+ c = (~a) | b; /* ORC */

20937

+ FORCE_REG1 (c);

20938

+ p[0] = c;

20939

+}

20940

+

20941

+void ptr10 (TYPE *p)

20942

+{

20943

+ TYPE a = p[1];

20944

+ TYPE b = p[2];

20945

+ TYPE c;

20946

+

20947

+ FORCE_REG2 (a, b);

20948

+ c = (~a) ^ b; /* EQV */

20949

+ FORCE_REG1 (c);

20950

+ p[0] = c;

20951

+}

20952

+

20953

+void ptr11 (TYPE *p)

20954

+{

20955

+ TYPE a = p[1];

20956

+ TYPE b = p[2];

20957

+ TYPE c;

20958

+

20959

+ FORCE_REG2 (a, b);

20960

+ c = a & (~b); /* ANDC */

20961

+ FORCE_REG1 (c);

20962

+ p[0] = c;

20963

+}

20964

+

20965

+void ptr12 (TYPE *p)

20966

+{

20967

+ TYPE a = p[1];

20968

+ TYPE b = p[2];

20969

+ TYPE c;

20970

+

20971

+ FORCE_REG2 (a, b);

20972

+ c = a | (~b); /* ORC */

20973

+ FORCE_REG1 (c);

20974

+ p[0] = c;

20975

+}

20976

+

20977

+void ptr13 (TYPE *p)

20978

+{

20979

+ TYPE a = p[1];

20980

+ TYPE b = p[2];

20981

+ TYPE c;

20982

+

20983

+ FORCE_REG2 (a, b);

20984

+ c = a ^ (~b); /* AND */

20985

+ FORCE_REG1 (c);

20986

+ p[0] = c;

20987

+}

20988

Index: gcc/testsuite/gcc.target/powerpc/altivec-perm-1.c

20989

===================================================================

20990

--- a/src/gcc/testsuite/gcc.target/powerpc/altivec-perm-1.c (.../tags/gcc_4_8_2_release)

20991

+++ b/src/gcc/testsuite/gcc.target/powerpc/altivec-perm-1.c (.../branches/gcc-4_8-branch)

20992

@@ -19,19 +19,6 @@

20993

return __builtin_shuffle(x, (V){ 4,5,6,7, 4,5,6,7, 4,5,6,7, 4,5,6,7, });

20994

}

20995

20996

-V p2(V x, V y)

20997

-{

20998

- return __builtin_shuffle(x, y,

20999

- (V){ 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 });

21000

-

21001

-}

21002

-

21003

-V p4(V x, V y)

21004

-{

21005

- return __builtin_shuffle(x, y,

21006

- (V){ 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 });

21007

-}

21008

-

21009

V h1(V x, V y)

21010

{

21011

return __builtin_shuffle(x, y,

21012

@@ -72,5 +59,3 @@

21013

/* { dg-final { scan-assembler "vspltb" } } */

21014

/* { dg-final { scan-assembler "vsplth" } } */

21015

/* { dg-final { scan-assembler "vspltw" } } */

21016

-/* { dg-final { scan-assembler "vpkuhum" } } */

21017

-/* { dg-final { scan-assembler "vpkuwum" } } */

21018

Index: gcc/testsuite/gcc.target/powerpc/bool2-p7.c

21019

===================================================================

21020

--- a/src/gcc/testsuite/gcc.target/powerpc/bool2-p7.c (.../tags/gcc_4_8_2_release)

21021

+++ b/src/gcc/testsuite/gcc.target/powerpc/bool2-p7.c (.../branches/gcc-4_8-branch)

21022

@@ -0,0 +1,31 @@

21023

+/* { dg-do compile { target { powerpc*-*-* } } } */

21024

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

21025

+/* { dg-require-effective-target powerpc_vsx_ok } */

21026

+/* { dg-options "-O2 -mcpu=power7" } */

21027

+/* { dg-final { scan-assembler-not "\[ \t\]and " } } */

21028

+/* { dg-final { scan-assembler-not "\[ \t\]or " } } */

21029

+/* { dg-final { scan-assembler-not "\[ \t\]xor " } } */

21030

+/* { dg-final { scan-assembler-not "\[ \t\]nor " } } */

21031

+/* { dg-final { scan-assembler-not "\[ \t\]eqv " } } */

21032

+/* { dg-final { scan-assembler-not "\[ \t\]andc " } } */

21033

+/* { dg-final { scan-assembler-not "\[ \t\]orc " } } */

21034

+/* { dg-final { scan-assembler-not "\[ \t\]nand " } } */

21035

+/* { dg-final { scan-assembler-not "\[ \t\]vand " } } */

21036

+/* { dg-final { scan-assembler-not "\[ \t\]vor " } } */

21037

+/* { dg-final { scan-assembler-not "\[ \t\]vxor " } } */

21038

+/* { dg-final { scan-assembler-not "\[ \t\]vnor " } } */

21039

+/* { dg-final { scan-assembler "\[ \t\]xxland " } } */

21040

+/* { dg-final { scan-assembler "\[ \t\]xxlor " } } */

21041

+/* { dg-final { scan-assembler "\[ \t\]xxlxor " } } */

21042

+/* { dg-final { scan-assembler "\[ \t\]xxlnor " } } */

21043

+/* { dg-final { scan-assembler "\[ \t\]xxlandc " } } */

21044

+/* { dg-final { scan-assembler-not "\[ \t\]xxleqv " } } */

21045

+/* { dg-final { scan-assembler-not "\[ \t\]xxlorc " } } */

21046

+/* { dg-final { scan-assembler-not "\[ \t\]xxlnand " } } */

21047

+

21048

+#ifndef TYPE

21049

+typedef int v4si __attribute__ ((vector_size (16)));

21050

+#define TYPE v4si

21051

+#endif

21052

+

21053

+#include "bool2.h"

21054

Index: gcc/testsuite/gcc.target/powerpc/ti_math2.c

21055

===================================================================

21056

--- a/src/gcc/testsuite/gcc.target/powerpc/ti_math2.c (.../tags/gcc_4_8_2_release)

21057

+++ b/src/gcc/testsuite/gcc.target/powerpc/ti_math2.c (.../branches/gcc-4_8-branch)

21058

@@ -0,0 +1,73 @@

21059

+/* { dg-do run { target { powerpc*-*-* && lp64 } } } */

21060

+/* { dg-options "-O2 -fno-inline" } */

21061

+

21062

+union U {

21063

+ __int128 i128;

21064

+ struct {

21065

+ long l1;

21066

+ long l2;

21067

+ } s;

21068

+};

21069

+

21070

+union U u1,u2;

21071

+

21072

+__int128

21073

+create_128 (long most_sig, long least_sig)

21074

+{

21075

+ union U u;

21076

+

21077

+#if __LITTLE_ENDIAN__

21078

+ u.s.l1 = least_sig;

21079

+ u.s.l2 = most_sig;

21080

+#else

21081

+ u.s.l1 = most_sig;

21082

+ u.s.l2 = least_sig;

21083

+#endif

21084

+ return u.i128;

21085

+}

21086

+

21087

+long most_sig (union U * u)

21088

+{

21089

+#if __LITTLE_ENDIAN__

21090

+ return (*u).s.l2;

21091

+#else

21092

+ return (*u).s.l1;

21093

+#endif

21094

+}

21095

+

21096

+long least_sig (union U * u)

21097

+{

21098

+#if __LITTLE_ENDIAN__

21099

+ return (*u).s.l1;

21100

+#else

21101

+ return (*u).s.l2;

21102

+#endif

21103

+}

21104

+

21105

+__int128

21106

+add_128 (__int128 *ptr, __int128 val)

21107

+{

21108

+ return (*ptr + val);

21109

+}

21110

+

21111

+__int128

21112

+sub_128 (__int128 *ptr, __int128 val)

21113

+{

21114

+ return (*ptr - val);

21115

+}

21116

+

21117

+int

21118

+main (void)

21119

+{

21120

+ /* Do a simple add/sub to make sure carry is happening between the dwords

21121

+ and that dwords are in correct endian order. */

21122

+ u1.i128 = create_128 (1, -1);

21123

+ u2.i128 = add_128 (&u1.i128, 1);

21124

+ if ((most_sig (&u2) != 2) || (least_sig (&u2) != 0))

21125

+ __builtin_abort ();

21126

+ u2.i128 = sub_128 (&u2.i128, 1);

21127

+ if ((most_sig (&u2) != 1) || (least_sig (&u2) != -1))

21128

+ __builtin_abort ();

21129

+ return 0;

21130

+}

21131

+

21132

Index: gcc/testsuite/gcc.target/microblaze/others/mem_reload.c

21133

===================================================================

21134

--- a/src/gcc/testsuite/gcc.target/microblaze/others/mem_reload.c (.../tags/gcc_4_8_2_release)

21135

+++ b/src/gcc/testsuite/gcc.target/microblaze/others/mem_reload.c (.../branches/gcc-4_8-branch)

21136

@@ -0,0 +1,74 @@

21137

+/* { dg-options "-O2 -fPIC" } */

21138

+

21139

+typedef struct test_struct

21140

+{

21141

+ unsigned long long h[8];

21142

+ unsigned long long Nl,Nh;

21143

+ union {

21144

+ unsigned long long d[16];

21145

+ unsigned char p[(16*8)];

21146

+ } u;

21147

+ unsigned int num,md_len;

21148

+} TEST_STRUCT;

21149

+

21150

+static const unsigned long long K512[12] = {

21151

+ 0x428a2f98d728ae22,0x7137449123ef65cd,

21152

+ 0xb5c0fbcfec4d3b2f,0xe9b5dba58189dbbc,

21153

+ 0x3956c25bf348b538,0x59f111f1b605d019,

21154

+ 0x923f82a4af194f9b,0xab1c5ed5da6d8118,

21155

+ 0xd807aa98a3030242,0x12835b0145706fbe,

21156

+ 0x243185be4ee4b28c,0x550c7dc3d5ffb4e2};

21157

+

21158

+#define ROTR(x,s) (((x)>>s) | (x)<<(64-s))

21159

+#define Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39))

21160

+#define Sigma1(x) (ROTR((x),14) ^ ROTR((x),18) ^ ROTR((x),41))

21161

+#define Ch(x,y,z) (((x) & (y)) ^ ((~(x)) & (z)))

21162

+#define Maj(x,y,z) (((x) & (y)) ^ ((x) & (z)) ^ ((y) & (z)))

21163

+

21164

+#define ROUND_00_15(i,a,b,c,d,e,f,g,h) do { \

21165

+ T1 += h + Sigma1(e) + Ch(e,f,g) + K512[i]; \

21166

+ h = Sigma0(a) + Maj(a,b,c); \

21167

+ d += T1; h += T1; } while (0)

21168

+

21169

+#define ROUND_16_80(i,a,b,c,d,e,f,g,h,X) do { \

21170

+ T1 = X[(i)&0x0f] += s0 + s1 + X[(i+9)&0x0f]; \

21171

+ ROUND_00_15(i,a,b,c,d,e,f,g,h); } while (0)

21172

+

21173

+static void testfunc1 (TEST_STRUCT *ctx, const void *in, unsigned int num)

21174

+{

21175

+ const unsigned long long *W=in;

21176

+ unsigned long long a,b,c,d,e,f,g,h,s0,s1,T1;

21177

+ unsigned long long X[16];

21178

+ int i;

21179

+

21180

+ while (num--) {

21181

+

21182

+ T1 = X[0] = W[0]; ROUND_00_15(0,a,b,c,d,e,f,g,h);

21183

+ T1 = X[1] = W[1]; ROUND_00_15(1,h,a,b,c,d,e,f,g);

21184

+ T1 = X[2] = W[2]; ROUND_00_15(2,g,h,a,b,c,d,e,f);

21185

+ T1 = X[3] = W[3]; ROUND_00_15(3,f,g,h,a,b,c,d,e);

21186

+ T1 = X[4] = W[4]; ROUND_00_15(4,e,f,g,h,a,b,c,d);

21187

+ T1 = X[5] = W[5]; ROUND_00_15(5,d,e,f,g,h,a,b,c);

21188

+ T1 = X[6] = W[6]; ROUND_00_15(6,c,d,e,f,g,h,a,b);

21189

+ T1 = X[7] = W[7]; ROUND_00_15(7,b,c,d,e,f,g,h,a);

21190

+ T1 = X[8] = W[8]; ROUND_00_15(8,a,b,c,d,e,f,g,h);

21191

+ T1 = X[9] = W[9]; ROUND_00_15(9,h,a,b,c,d,e,f,g);

21192

+

21193

+ for (i=16;i<80;i+=8)

21194

+ {

21195

+ ROUND_16_80(i+0,a,b,c,d,e,f,g,h,X);

21196

+ }

21197

+

21198

+ ctx->h[4] += e; ctx->h[5] += f; ctx->h[6] += g; ctx->h[7] += h;

21199

+ }

21200

+}

21201

+

21202

+int testfunc2 (TEST_STRUCT *c, const void *_data, unsigned int len)

21203

+{

21204

+ const unsigned char *data=(const unsigned char *)_data;

21205

+

21206

+ unsigned char *p=(unsigned char *)c->u.p;

21207

+

21208

+ testfunc1 (c,p,0);

21209

+ testfunc1 (c,data,len/sizeof(c->u));

21210

+}

21211

Index: gcc/testsuite/gcc.target/microblaze/others/builtin-trap.c

21212

===================================================================

21213

--- a/src/gcc/testsuite/gcc.target/microblaze/others/builtin-trap.c (.../tags/gcc_4_8_2_release)

21214

+++ b/src/gcc/testsuite/gcc.target/microblaze/others/builtin-trap.c (.../branches/gcc-4_8-branch)

21215

@@ -0,0 +1,8 @@

21216

+/* { dg-do compile } */

21217

+

21218

+void trap ()

21219

+{

21220

+ __builtin_trap ();

21221

+}

21222

+

21223

+/* { dg-final { scan-assembler "brki\tr0,-1" } } */

21224

\ No newline at end of file

21225

Index: gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c

21226

===================================================================

21227

--- a/src/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c (.../tags/gcc_4_8_2_release)

21228

+++ b/src/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c (.../branches/gcc-4_8-branch)

21229

@@ -0,0 +1,9 @@

21230

+/* { dg-options "-O3 -mcpu=v6.00.a -mhard-float" } */

21231

+

21232

+void float_func(float f1, float f2, float f3)

21233

+{

21234

+ /* { dg-final { scan-assembler "fcmp\.eq\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */

21235

+ /* { dg-final { scan-assembler "fcmp\.le\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */

21236

+ if(f1==f2 && f1<=f3)

21237

+ print ("f1 eq f2 && f1 le f3");

21238

+}

21239

Index: gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c

21240

===================================================================

21241

--- a/src/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c (.../tags/gcc_4_8_2_release)

21242

+++ b/src/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c (.../branches/gcc-4_8-branch)

21243

@@ -1,8 +1,14 @@

21244

/* { dg-do compile } */

21245

/* { dg-options "-O2" } */

21246

21247

-#include "../../../config/aarch64/arm_neon.h"

21248

+#include <arm_neon.h>

21249

21250

+/* Used to force a variable to a SIMD register. */

21251

+#define force_simd(V1) asm volatile ("mov %d0, %1.d[0]" \

21252

+ : "=w"(V1) \

21253

+ : "w"(V1) \

21254

+ : /* No clobbers */);

21255

+

21256

/* { dg-final { scan-assembler-times "\\tadd\\tx\[0-9\]+" 2 } } */

21257

21258

uint64x1_t

21259

@@ -31,7 +37,12 @@

21260

uint64x1_t

21261

test_vceqd_s64 (int64x1_t a, int64x1_t b)

21262

{

21263

- return vceqd_s64 (a, b);

21264

+ uint64x1_t res;

21265

+ force_simd (a);

21266

+ force_simd (b);

21267

+ res = vceqd_s64 (a, b);

21268

+ force_simd (res);

21269

+ return res;

21270

}

21271

21272

/* { dg-final { scan-assembler-times "\\tcmeq\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */

21273

@@ -39,7 +50,11 @@

21274

uint64x1_t

21275

test_vceqzd_s64 (int64x1_t a)

21276

{

21277

- return vceqzd_s64 (a);

21278

+ uint64x1_t res;

21279

+ force_simd (a);

21280

+ res = vceqzd_s64 (a);

21281

+ force_simd (res);

21282

+ return res;

21283

}

21284

21285

/* { dg-final { scan-assembler-times "\\tcmge\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 2 } } */

21286

@@ -47,21 +62,36 @@

21287

uint64x1_t

21288

test_vcged_s64 (int64x1_t a, int64x1_t b)

21289

{

21290

- return vcged_s64 (a, b);

21291

+ uint64x1_t res;

21292

+ force_simd (a);

21293

+ force_simd (b);

21294

+ res = vcged_s64 (a, b);

21295

+ force_simd (res);

21296

+ return res;

21297

}

21298

21299

uint64x1_t

21300

test_vcled_s64 (int64x1_t a, int64x1_t b)

21301

{

21302

- return vcled_s64 (a, b);

21303

+ uint64x1_t res;

21304

+ force_simd (a);

21305

+ force_simd (b);

21306

+ res = vcled_s64 (a, b);

21307

+ force_simd (res);

21308

+ return res;

21309

}

21310

21311

-/* { dg-final { scan-assembler-times "\\tcmge\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */

21312

+/* Idiom recognition will cause this testcase not to generate

21313

+ the expected cmge instruction, so do not check for it. */

21314

21315

uint64x1_t

21316

test_vcgezd_s64 (int64x1_t a)

21317

{

21318

- return vcgezd_s64 (a);

21319

+ uint64x1_t res;

21320

+ force_simd (a);

21321

+ res = vcgezd_s64 (a);

21322

+ force_simd (res);

21323

+ return res;

21324

}

21325

21326

/* { dg-final { scan-assembler-times "\\tcmhs\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */

21327

@@ -69,7 +99,12 @@

21328

uint64x1_t

21329

test_vcged_u64 (uint64x1_t a, uint64x1_t b)

21330

{

21331

- return vcged_u64 (a, b);

21332

+ uint64x1_t res;

21333

+ force_simd (a);

21334

+ force_simd (b);

21335

+ res = vcged_u64 (a, b);

21336

+ force_simd (res);

21337

+ return res;

21338

}

21339

21340

/* { dg-final { scan-assembler-times "\\tcmgt\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 2 } } */

21341

@@ -77,13 +112,23 @@

21342

uint64x1_t

21343

test_vcgtd_s64 (int64x1_t a, int64x1_t b)

21344

{

21345

- return vcgtd_s64 (a, b);

21346

+ uint64x1_t res;

21347

+ force_simd (a);

21348

+ force_simd (b);

21349

+ res = vcgtd_s64 (a, b);

21350

+ force_simd (res);

21351

+ return res;

21352

}

21353

21354

uint64x1_t

21355

test_vcltd_s64 (int64x1_t a, int64x1_t b)

21356

{

21357

- return vcltd_s64 (a, b);

21358

+ uint64x1_t res;

21359

+ force_simd (a);

21360

+ force_simd (b);

21361

+ res = vcltd_s64 (a, b);

21362

+ force_simd (res);

21363

+ return res;

21364

}

21365

21366

/* { dg-final { scan-assembler-times "\\tcmgt\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */

21367

@@ -91,7 +136,11 @@

21368

uint64x1_t

21369

test_vcgtzd_s64 (int64x1_t a)

21370

{

21371

- return vcgtzd_s64 (a);

21372

+ uint64x1_t res;

21373

+ force_simd (a);

21374

+ res = vcgtzd_s64 (a);

21375

+ force_simd (res);

21376

+ return res;

21377

}

21378

21379

/* { dg-final { scan-assembler-times "\\tcmhi\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */

21380

@@ -99,7 +148,12 @@

21381

uint64x1_t

21382

test_vcgtd_u64 (uint64x1_t a, uint64x1_t b)

21383

{

21384

- return vcgtd_u64 (a, b);

21385

+ uint64x1_t res;

21386

+ force_simd (a);

21387

+ force_simd (b);

21388

+ res = vcgtd_u64 (a, b);

21389

+ force_simd (res);

21390

+ return res;

21391

}

21392

21393

/* { dg-final { scan-assembler-times "\\tcmle\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */

21394

@@ -107,15 +161,24 @@

21395

uint64x1_t

21396

test_vclezd_s64 (int64x1_t a)

21397

{

21398

- return vclezd_s64 (a);

21399

+ uint64x1_t res;

21400

+ force_simd (a);

21401

+ res = vclezd_s64 (a);

21402

+ force_simd (res);

21403

+ return res;

21404

}

21405

21406

-/* { dg-final { scan-assembler-times "\\tcmlt\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */

21407

+/* Idiom recognition will cause this testcase not to generate

21408

+ the expected cmlt instruction, so do not check for it. */

21409

21410

uint64x1_t

21411

test_vcltzd_s64 (int64x1_t a)

21412

{

21413

- return vcltzd_s64 (a);

21414

+ uint64x1_t res;

21415

+ force_simd (a);

21416

+ res = vcltzd_s64 (a);

21417

+ force_simd (res);

21418

+ return res;

21419

}

21420

21421

/* { dg-final { scan-assembler-times "\\tdup\\tb\[0-9\]+, v\[0-9\]+\.b" 2 } } */

21422

@@ -179,13 +242,23 @@

21423

int64x1_t

21424

test_vtst_s64 (int64x1_t a, int64x1_t b)

21425

{

21426

- return vtstd_s64 (a, b);

21427

+ uint64x1_t res;

21428

+ force_simd (a);

21429

+ force_simd (b);

21430

+ res = vtstd_s64 (a, b);

21431

+ force_simd (res);

21432

+ return res;

21433

}

21434

21435

uint64x1_t

21436

test_vtst_u64 (uint64x1_t a, uint64x1_t b)

21437

{

21438

- return vtstd_u64 (a, b);

21439

+ uint64x1_t res;

21440

+ force_simd (a);

21441

+ force_simd (b);

21442

+ res = vtstd_s64 (a, b);

21443

+ force_simd (res);

21444

+ return res;

21445

}

21446

21447

/* { dg-final { scan-assembler-times "\\taddp\\td\[0-9\]+, v\[0-9\]+\.2d" 1 } } */

21448

@@ -722,8 +795,11 @@

21449

return vrshld_u64 (a, b);

21450

}

21451

21452

-/* { dg-final { scan-assembler-times "\\tasr\\tx\[0-9\]+" 1 } } */

21453

+/* Other intrinsics can generate an asr instruction (vcltzd, vcgezd),

21454

+ so we cannot check scan-assembler-times. */

21455

21456

+/* { dg-final { scan-assembler "\\tasr\\tx\[0-9\]+" } } */

21457

+

21458

int64x1_t

21459

test_vshrd_n_s64 (int64x1_t a)

21460

{

21461

Index: gcc/testsuite/gcc.target/i386/pr59405.c

21462

===================================================================

21463

--- a/src/gcc/testsuite/gcc.target/i386/pr59405.c (.../tags/gcc_4_8_2_release)

21464

+++ b/src/gcc/testsuite/gcc.target/i386/pr59405.c (.../branches/gcc-4_8-branch)

21465

@@ -0,0 +1,24 @@

21466

+/* { dg-do run } */

21467

+/* { dg-options "-mmmx -mfpmath=387" } */

21468

+

21469

+#include "mmx-check.h"

21470

+

21471

+#include <mmintrin.h>

21472

+

21473

+typedef float float32x2_t __attribute__ ((vector_size (8)));

21474

+

21475

+float

21476

+foo32x2_be (float32x2_t x)

21477

+{

21478

+ _mm_empty ();

21479

+ return x[1];

21480

+}

21481

+

21482

+static void

21483

+mmx_test (void)

21484

+{

21485

+ float32x2_t b = { 0.0f, 1.0f };

21486

+

21487

+ if (foo32x2_be (b) != 1.0f)

21488

+ abort ();

21489

+}

21490

Index: gcc/testsuite/gcc.target/i386/pr59794-5.c

21491

===================================================================

21492

--- a/src/gcc/testsuite/gcc.target/i386/pr59794-5.c (.../tags/gcc_4_8_2_release)

21493

+++ b/src/gcc/testsuite/gcc.target/i386/pr59794-5.c (.../branches/gcc-4_8-branch)

21494

@@ -0,0 +1,14 @@

21495

+/* PR target/59794 */

21496

+/* { dg-do compile { target { ia32 } } } */

21497

+/* { dg-options "-O2 -mno-sse" } */

21498

+/* { dg-skip-if "no SSE vector" { *-*-mingw* } } */

21499

+

21500

+typedef int __v4si __attribute__ ((__vector_size__ (16)));

21501

+

21502

+extern __v4si x;

21503

+

21504

+__v4si

21505

+foo (void)

21506

+{ /* { dg-warning "SSE vector return without SSE enabled changes the ABI" } */

21507

+ return x;

21508

+}

21509

Index: gcc/testsuite/gcc.target/i386/avx-vzeroupper-17.c

21510

===================================================================

21511

--- a/src/gcc/testsuite/gcc.target/i386/avx-vzeroupper-17.c (.../tags/gcc_4_8_2_release)

21512

+++ b/src/gcc/testsuite/gcc.target/i386/avx-vzeroupper-17.c (.../branches/gcc-4_8-branch)

21513

@@ -1,5 +1,5 @@

21514

/* { dg-do compile { target lp64 } } */

21515

-/* { dg-options "-O2 -mavx -mabi=ms -mtune=generic -dp" } */

21516

+/* { dg-options "-O2 -mavx -mabi=ms -maccumulate-outgoing-args -dp" } */

21517

21518

typedef float __m256 __attribute__ ((__vector_size__ (32), __may_alias__));

21519

21520

Index: gcc/testsuite/gcc.target/i386/pr54694.c

21521

===================================================================

21522

--- a/src/gcc/testsuite/gcc.target/i386/pr54694.c (.../tags/gcc_4_8_2_release)

21523

+++ b/src/gcc/testsuite/gcc.target/i386/pr54694.c (.../branches/gcc-4_8-branch)

21524

@@ -0,0 +1,11 @@

21525

+/* { dg-do compile } */

21526

+/* { dg-options "-O" } */

21527

+

21528

+register void *hfp __asm__("%ebp"); /* { dg-message "note: for" } */

21529

+

21530

+extern void g(void *);

21531

+

21532

+void f(int x) /* { dg-error "frame pointer required" } */

21533

+{

21534

+ g(__builtin_alloca(x));

21535

+}

21536

Index: gcc/testsuite/gcc.target/i386/pr59470.c

21537

===================================================================

21538

--- a/src/gcc/testsuite/gcc.target/i386/pr59470.c (.../tags/gcc_4_8_2_release)

21539

+++ b/src/gcc/testsuite/gcc.target/i386/pr59470.c (.../branches/gcc-4_8-branch)

21540

@@ -0,0 +1,17 @@

21541

+/* PR middle-end/58956 */

21542

+/* PR middle-end/59470 */

21543

+/* { dg-do run } */

21544

+/* { dg-options "-O2" } */

21545

+

21546

+int a, b, d[1024];

21547

+

21548

+int

21549

+main ()

21550

+{

21551

+ int c = a;

21552

+ asm ("{movl $6, (%2); movl $1, %0|mov dword ptr [%2], 6; mov %0, 1}"

21553

+ : "=r" (d[c]) : "rm" (b), "r" (&a) : "memory");

21554

+ if (d[0] != 1 || d[6] != 0)

21555

+ __builtin_abort ();

21556

+ return 0;

21557

+}

21558

Index: gcc/testsuite/gcc.target/i386/pr59034-1.c

21559

===================================================================

21560

--- a/src/gcc/testsuite/gcc.target/i386/pr59034-1.c (.../tags/gcc_4_8_2_release)

21561

+++ b/src/gcc/testsuite/gcc.target/i386/pr59034-1.c (.../branches/gcc-4_8-branch)

21562

@@ -0,0 +1,10 @@

21563

+/* { dg-do compile { target { ! { ia32 } } } } */

21564

+/* { dg-require-effective-target maybe_x32 } */

21565

+/* { dg-options "-O -mx32 -mtune=corei7 -maddress-mode=short" } */

21566

+

21567

+extern int foo(int, ...);

21568

+int bar(void) {

21569

+ long double l = 1.2345E6;

21570

+ foo(0, l);

21571

+ return 0;

21572

+}

21573

Index: gcc/testsuite/gcc.target/i386/pr58690.c

21574

===================================================================

21575

--- a/src/gcc/testsuite/gcc.target/i386/pr58690.c (.../tags/gcc_4_8_2_release)

21576

+++ b/src/gcc/testsuite/gcc.target/i386/pr58690.c (.../branches/gcc-4_8-branch)

21577

@@ -0,0 +1,14 @@

21578

+/* { dg-do compile { target { ! { ia32 } } } } */

21579

+/* { dg-require-effective-target maybe_x32 } */

21580

+/* { dg-options "-O2 -mx32 -maddress-mode=short" } */

21581

+

21582

+struct gomp_thread

21583

+{

21584

+ char foo[41];

21585

+};

21586

+extern __thread struct gomp_thread gomp_tls_data;

21587

+void

21588

+foo (void)

21589

+{

21590

+ __builtin_memset (&gomp_tls_data, '\0', sizeof (gomp_tls_data));

21591

+}

21592

Index: gcc/testsuite/gcc.target/i386/avx-vmovapd-256-2.c

21593

===================================================================

21594

--- a/src/gcc/testsuite/gcc.target/i386/avx-vmovapd-256-2.c (.../tags/gcc_4_8_2_release)

21595

+++ b/src/gcc/testsuite/gcc.target/i386/avx-vmovapd-256-2.c (.../branches/gcc-4_8-branch)

21596

@@ -15,7 +15,7 @@

21597

avx_test (void)

21598

{

21599

union256d u;

21600

- double e [4] __attribute__ ((aligned (8))) = {0.0};

21601

+ double e [4] __attribute__ ((aligned (32))) = {0.0};

21602

21603

u.x = _mm256_set_pd (39578.467285, 7856.342941, 85632.783567, 47563.234215);

21604

21605

Index: gcc/testsuite/gcc.target/i386/pr9771-1.c

21606

===================================================================

21607

--- a/src/gcc/testsuite/gcc.target/i386/pr9771-1.c (.../tags/gcc_4_8_2_release)

21608

+++ b/src/gcc/testsuite/gcc.target/i386/pr9771-1.c (.../branches/gcc-4_8-branch)

21609

@@ -45,7 +45,17 @@

21610

exit(0);

21611

}

21612

21613

-int main()

21614

+/* main usually performs dynamic realignment of the stack in case

21615

+ _start would fail to properly align the stack, but for dynamic

21616

+ stack realignment we need frame pointer which is incompatible

21617

+ with -ffixed-ebp and the global register var. So, cheat here

21618

+ and hide from the compiler that main is really main. */

21619

+#define ASMNAME(cname) ASMNAME2 (__USER_LABEL_PREFIX__, cname)

21620

+#define ASMNAME2(prefix, cname) STRING (prefix) cname

21621

+#define STRING(x) #x

21622

+int real_main() __asm (ASMNAME ("main"));

21623

+

21624

+int real_main()

21625

{

21626

test();

21627

return 0;

21628

Index: gcc/testsuite/gcc.target/i386/pr60700.c

21629

===================================================================

21630

--- a/src/gcc/testsuite/gcc.target/i386/pr60700.c (.../tags/gcc_4_8_2_release)

21631

+++ b/src/gcc/testsuite/gcc.target/i386/pr60700.c (.../branches/gcc-4_8-branch)

21632

@@ -0,0 +1,59 @@

21633

+/* PR rtl-optimization/60700 */

21634

+/* { dg-do run { target ia32 } } */

21635

+/* { dg-options "-O3 -march=i686" } */

21636

+

21637

+int

21638

+__attribute__((noinline))

21639

+foo (void)

21640

+{

21641

+ return 0;

21642

+}

21643

+

21644

+void *g = (void *)1;

21645

+

21646

+struct st {

21647

+ char data[36]; /* must be greater than 32. */

21648

+};

21649

+

21650

+int

21651

+__attribute__((noinline))

21652

+repro(struct st **out)

21653

+{

21654

+ int status = 0;

21655

+

21656

+ *out = 0;

21657

+

21658

+ status = foo();

21659

+ if (status != 0) {

21660

+ return status;

21661

+ }

21662

+

21663

+ if (0 == g) {

21664

+ status = 999;

21665

+ return status;

21666

+ }

21667

+

21668

+ *out = (struct st *)__builtin_malloc(sizeof(struct st));

21669

+ if (0 == *out) {

21670

+ status = 42;

21671

+ return status;

21672

+ }

21673

+

21674

+ __builtin_memset(*out, 0, sizeof(struct st));

21675

+

21676

+ return status;

21677

+}

21678

+

21679

+int

21680

+main ()

21681

+{

21682

+ struct st *p;

21683

+ int ret = repro (&p);

21684

+ unsigned int i;

21685

+

21686

+ for (i = 0; i < sizeof (p->data)/sizeof (p->data[0]); i++)

21687

+ if (p->data[i] != 0)

21688

+ __builtin_abort ();

21689

+

21690

+ return ret;

21691

+}

21692

Index: gcc/testsuite/gcc.target/i386/pr59794-2.c

21693

===================================================================

21694

--- a/src/gcc/testsuite/gcc.target/i386/pr59794-2.c (.../tags/gcc_4_8_2_release)

21695

+++ b/src/gcc/testsuite/gcc.target/i386/pr59794-2.c (.../branches/gcc-4_8-branch)

21696

@@ -0,0 +1,15 @@

21697

+/* PR target/59794 */

21698

+/* { dg-prune-output "ABI for passing parameters" } */

21699

+/* { dg-options "-O2 -mno-sse" } */

21700

+/* { dg-skip-if "no SSE vector" { *-*-mingw* } } */

21701

+

21702

+typedef double __v2df __attribute__ ((__vector_size__ (16)));

21703

+

21704

+extern __v2df x;

21705

+

21706

+extern void bar (__v2df);

21707

+void

21708

+foo (void)

21709

+{

21710

+ bar (x); /* { dg-message "warning: SSE vector argument without SSE enabled changes the ABI" } */

21711

+}

21712

Index: gcc/testsuite/gcc.target/i386/pr57003.c

21713

===================================================================

21714

--- a/src/gcc/testsuite/gcc.target/i386/pr57003.c (.../tags/gcc_4_8_2_release)

21715

+++ b/src/gcc/testsuite/gcc.target/i386/pr57003.c (.../branches/gcc-4_8-branch)

21716

@@ -1,6 +1,6 @@

21717

/* PR rtl-optimization/57003 */

21718

/* { dg-do run } */

21719

-/* { dg-options "-O2" } */

21720

+/* { dg-options "-O2 -maccumulate-outgoing-args" } */

21721

21722

#define N 2001

21723

unsigned short *b, *c, *d;

21724

Index: gcc/testsuite/gcc.target/i386/pr59929.c

21725

===================================================================

21726

--- a/src/gcc/testsuite/gcc.target/i386/pr59929.c (.../tags/gcc_4_8_2_release)

21727

+++ b/src/gcc/testsuite/gcc.target/i386/pr59929.c (.../branches/gcc-4_8-branch)

21728

@@ -0,0 +1,55 @@

21729

+/* { dg-do run } */

21730

+/* { dg-options "-O0 -mno-accumulate-outgoing-args" } */

21731

+/* { dg-options "-O0 -mno-accumulate-outgoing-args -mx32 -maddress-mode=short" { target x32 } } */

21732

+

21733

+void

21734

+__attribute__ ((noinline))

21735

+test (float x1, float x2, float x3, float x4, float x5, float x6,

21736

+ float x7, float x8, float x9, float x10, float x11, float x12,

21737

+ float x13, float x14, float x15, float x16)

21738

+{

21739

+ if (x1 != 91

21740

+ || x2 != 92

21741

+ || x3 != 93

21742

+ || x4 != 94

21743

+ || x5 != 95

21744

+ || x6 != 96

21745

+ || x7 != 97

21746

+ || x8 != 98

21747

+ || x9 != 99

21748

+ || x10 != 100

21749

+ || x11 != 101

21750

+ || x12 != 102

21751

+ || x13 != 103

21752

+ || x14 != 104

21753

+ || x15 != 105

21754

+ || x16 != 106)

21755

+ __builtin_abort ();

21756

+}

21757

+

21758

+float x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13,

21759

+ x14, x15, x16;

21760

+

21761

+int

21762

+main ()

21763

+{

21764

+ x1 = 91;

21765

+ x2 = 92;

21766

+ x3 = 93;

21767

+ x4 = 94;

21768

+ x5 = 95;

21769

+ x6 = 96;

21770

+ x7 = 97;

21771

+ x8 = 98;

21772

+ x9 = 99;

21773

+ x10 = 100;

21774

+ x11 = 101;

21775

+ x12 = 102;

21776

+ x13 = 103;

21777

+ x14 = 104;

21778

+ x15 = 105;

21779

+ x16 = 106;

21780

+ test (x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13,

21781

+ x14, x15, x16);

21782

+ return 0;

21783

+}

21784

Index: gcc/testsuite/gcc.target/i386/pr59794-6.c

21785

===================================================================

21786

--- a/src/gcc/testsuite/gcc.target/i386/pr59794-6.c (.../tags/gcc_4_8_2_release)

21787

+++ b/src/gcc/testsuite/gcc.target/i386/pr59794-6.c (.../branches/gcc-4_8-branch)

21788

@@ -0,0 +1,14 @@

21789

+/* PR target/59794 */

21790

+/* { dg-do compile { target { ! ia32 } } } */

21791

+/* { dg-options "-O2 -mno-sse" } */

21792

+/* { dg-skip-if "no SSE vector" { *-*-mingw* } } */

21793

+

21794

+typedef int __v4si __attribute__ ((__vector_size__ (16)));

21795

+

21796

+extern __v4si x;

21797

+

21798

+__v4si

21799

+foo (void)

21800

+{ /* { dg-error "SSE register return with SSE disabled" } */

21801

+ return x;

21802

+}

21803

Index: gcc/testsuite/gcc.target/i386/avx-vzeroupper-18.c

21804

===================================================================

21805

--- a/src/gcc/testsuite/gcc.target/i386/avx-vzeroupper-18.c (.../tags/gcc_4_8_2_release)

21806

+++ b/src/gcc/testsuite/gcc.target/i386/avx-vzeroupper-18.c (.../branches/gcc-4_8-branch)

21807

@@ -1,5 +1,5 @@

21808

/* { dg-do compile { target lp64 } } */

21809

-/* { dg-options "-O0 -mavx -mabi=ms -mtune=generic -dp" } */

21810

+/* { dg-options "-O0 -mavx -mabi=ms -maccumulate-outgoing-args -dp" } */

21811

21812

typedef float __m256 __attribute__ ((__vector_size__ (32), __may_alias__));

21813

21814

Index: gcc/testsuite/gcc.target/i386/sse2-movapd-1.c

21815

===================================================================

21816

--- a/src/gcc/testsuite/gcc.target/i386/sse2-movapd-1.c (.../tags/gcc_4_8_2_release)

21817

+++ b/src/gcc/testsuite/gcc.target/i386/sse2-movapd-1.c (.../branches/gcc-4_8-branch)

21818

@@ -25,7 +25,7 @@

21819

TEST (void)

21820

{

21821

union128d u;

21822

- double e[2] __attribute__ ((aligned (8))) = {2134.3343,1234.635654};

21823

+ double e[2] __attribute__ ((aligned (16))) = {2134.3343,1234.635654};

21824

21825

u.x = test (e);

21826

21827

Index: gcc/testsuite/gcc.target/i386/pr59021.c

21828

===================================================================

21829

--- a/src/gcc/testsuite/gcc.target/i386/pr59021.c (.../tags/gcc_4_8_2_release)

21830

+++ b/src/gcc/testsuite/gcc.target/i386/pr59021.c (.../branches/gcc-4_8-branch)

21831

@@ -0,0 +1,23 @@

21832

+/* { dg-do compile } */

21833

+/* { dg-options "-O2 -mavx -mvzeroupper" } */

21834

+

21835

+extern void abort (void);

21836

+

21837

+struct S {

21838

+ int i1;

21839

+ int i2;

21840

+ int i3;

21841

+};

21842

+

21843

+typedef double v4df __attribute__ ((vector_size (32)));

21844

+

21845

+extern int foo (v4df, int i1, int i2, int i3, int i4, int i5, struct S s);

21846

+

21847

+void bar (v4df v, struct S s)

21848

+{

21849

+ int r = foo (v, 1, 2, 3, 4, 5, s);

21850

+ if (r)

21851

+ abort ();

21852

+}

21853

+

21854

+/* { dg-final { scan-assembler-not "vzeroupper" } } */

21855

Index: gcc/testsuite/gcc.target/i386/pr59034-2.c

21856

===================================================================

21857

--- a/src/gcc/testsuite/gcc.target/i386/pr59034-2.c (.../tags/gcc_4_8_2_release)

21858

+++ b/src/gcc/testsuite/gcc.target/i386/pr59034-2.c (.../branches/gcc-4_8-branch)

21859

@@ -0,0 +1,10 @@

21860

+/* { dg-do compile { target { ! { ia32 } } } } */

21861

+/* { dg-require-effective-target maybe_x32 } */

21862

+/* { dg-options "-O -mx32 -mtune=corei7 -maddress-mode=long" } */

21863

+

21864

+extern int foo(int, ...);

21865

+int bar(void) {

21866

+ long double l = 1.2345E6;

21867

+ foo(0, l);

21868

+ return 0;

21869

+}

21870

Index: gcc/testsuite/gcc.target/i386/pr60693.c

21871

===================================================================

21872

--- a/src/gcc/testsuite/gcc.target/i386/pr60693.c (.../tags/gcc_4_8_2_release)

21873

+++ b/src/gcc/testsuite/gcc.target/i386/pr60693.c (.../branches/gcc-4_8-branch)

21874

@@ -0,0 +1,13 @@

21875

+/* PR target/60693 */

21876

+/* { dg-do compile } */

21877

+/* { dg-options "-O0" } */

21878

+

21879

+void bar (char *);

21880

+

21881

+void

21882

+foo (void)

21883

+{

21884

+ char buf[4096];

21885

+ __builtin_memcpy (buf, (void *) 0x8000, 4096);

21886

+ bar (buf);

21887

+}

21888

Index: gcc/testsuite/gcc.target/i386/pr59794-3.c

21889

===================================================================

21890

--- a/src/gcc/testsuite/gcc.target/i386/pr59794-3.c (.../tags/gcc_4_8_2_release)

21891

+++ b/src/gcc/testsuite/gcc.target/i386/pr59794-3.c (.../branches/gcc-4_8-branch)

21892

@@ -0,0 +1,15 @@

21893

+/* PR target/59794 */

21894

+/* { dg-prune-output "ABI for passing parameters" } */

21895

+/* { dg-options "-O2 -mno-avx" } */

21896

+/* { dg-skip-if "no AVX vector" { *-*-mingw* } } */

21897

+

21898

+typedef int __v8si __attribute__ ((__vector_size__ (32)));

21899

+

21900

+extern __v8si x;

21901

+

21902

+extern void bar (__v8si);

21903

+void

21904

+foo (void)

21905

+{

21906

+ bar (x); /* { dg-message "warning: AVX vector argument without AVX enabled changes the ABI" } */

21907

+}

21908

Index: gcc/testsuite/gcc.target/i386/pr59839.c

21909

===================================================================

21910

--- a/src/gcc/testsuite/gcc.target/i386/pr59839.c (.../tags/gcc_4_8_2_release)

21911

+++ b/src/gcc/testsuite/gcc.target/i386/pr59839.c (.../branches/gcc-4_8-branch)

21912

@@ -0,0 +1,12 @@

21913

+/* PR target/59839 */

21914

+/* { dg-do compile } */

21915

+/* { dg-options "-O0 -mavx2" } */

21916

+

21917

+#include <x86intrin.h>

21918

+

21919

+void

21920

+test (const float *x)

21921

+{

21922

+ __m256i i = _mm256_set1_epi32 (1);

21923

+ __m256 d = _mm256_i32gather_ps (x, i, 1);

21924

+}

21925

Index: gcc/testsuite/gcc.target/i386/pr60516.c

21926

===================================================================

21927

--- a/src/gcc/testsuite/gcc.target/i386/pr60516.c (.../tags/gcc_4_8_2_release)

21928

+++ b/src/gcc/testsuite/gcc.target/i386/pr60516.c (.../branches/gcc-4_8-branch)

21929

@@ -0,0 +1,20 @@

21930

+/* PR target/60516 */

21931

+/* { dg-do compile } */

21932

+/* { dg-options "-O2" } */

21933

+

21934

+struct S { char c[65536]; };

21935

+

21936

+__attribute__((ms_abi, thiscall)) void

21937

+foo (void *x, struct S y)

21938

+{

21939

+}

21940

+

21941

+__attribute__((ms_abi, fastcall)) void

21942

+bar (void *x, void *y, struct S z)

21943

+{

21944

+}

21945

+

21946

+__attribute__((ms_abi, stdcall)) void

21947

+baz (struct S x)

21948

+{

21949

+}

21950

Index: gcc/testsuite/gcc.target/i386/xop-frczX.c

21951

===================================================================

21952

--- a/src/gcc/testsuite/gcc.target/i386/xop-frczX.c (.../tags/gcc_4_8_2_release)

21953

+++ b/src/gcc/testsuite/gcc.target/i386/xop-frczX.c (.../branches/gcc-4_8-branch)

21954

@@ -0,0 +1,60 @@

21955

+/* { dg-do run } */

21956

+/* { dg-require-effective-target xop } */

21957

+/* { dg-options "-O2 -mxop" } */

21958

+

21959

+#include "xop-check.h"

21960

+

21961

+#include <x86intrin.h>

21962

+

21963

+void

21964

+check_mm_vmfrcz_sd (__m128d __A, __m128d __B)

21965

+{

21966

+ union128d a, b, c;

21967

+ double d[2];

21968

+

21969

+ a.x = __A;

21970

+ b.x = __B;

21971

+ c.x = _mm_frcz_sd (__A, __B);

21972

+ d[0] = b.a[0] - (int)b.a[0] ;

21973

+ d[1] = a.a[1];

21974

+ if (check_union128d (c, d))

21975

+ abort ();

21976

+}

21977

+

21978

+void

21979

+check_mm_vmfrcz_ss (__m128 __A, __m128 __B)

21980

+{

21981

+ union128 a, b, c;

21982

+ float f[4];

21983

+

21984

+ a.x = __A;

21985

+ b.x = __B;

21986

+ c.x = _mm_frcz_ss (__A, __B);

21987

+ f[0] = b.a[0] - (int)b.a[0] ;

21988

+ f[1] = a.a[1];

21989

+ f[2] = a.a[2];

21990

+ f[3] = a.a[3];

21991

+ if (check_union128 (c, f))

21992

+ abort ();

21993

+}

21994

+

21995

+static void

21996

+xop_test (void)

21997

+{

21998

+ union128 a, b;

21999

+ union128d c,d;

22000

+ int i;

22001

+

22002

+ for (i = 0; i < 4; i++)

22003

+ {

22004

+ a.a[i] = i + 3.5;

22005

+ b.a[i] = i + 7.9;

22006

+ }

22007

+ for (i = 0; i < 2; i++)

22008

+ {

22009

+ c.a[i] = i + 3.5;

22010

+ d.a[i] = i + 7.987654321;

22011

+ }

22012

+ check_mm_vmfrcz_ss (a.x, b.x);

22013

+ check_mm_vmfrcz_sd (c.x, d.x);

22014

+}

22015

Index: gcc/testsuite/gcc.target/i386/pr59794-7.c

22016

===================================================================

22017

--- a/src/gcc/testsuite/gcc.target/i386/pr59794-7.c (.../tags/gcc_4_8_2_release)

22018

+++ b/src/gcc/testsuite/gcc.target/i386/pr59794-7.c (.../branches/gcc-4_8-branch)

22019

@@ -0,0 +1,13 @@

22020

+/* PR target/59794 */

22021

+/* { dg-options "-O2 -mno-avx" } */

22022

+/* { dg-skip-if "no AVX vector" { *-*-mingw* } } */

22023

+

22024

+typedef int __v8si __attribute__ ((__vector_size__ (32)));

22025

+

22026

+extern __v8si x;

22027

+

22028

+__v8si

22029

+foo (void)

22030

+{ /* { dg-warning "AVX vector return without AVX enabled changes the ABI" } */

22031

+ return x;

22032

+}

22033

Index: gcc/testsuite/gcc.target/i386/pr59625.c

22034

===================================================================

22035

--- a/src/gcc/testsuite/gcc.target/i386/pr59625.c (.../tags/gcc_4_8_2_release)

22036

+++ b/src/gcc/testsuite/gcc.target/i386/pr59625.c (.../branches/gcc-4_8-branch)

22037

@@ -0,0 +1,36 @@

22038

+/* PR target/59625 */

22039

+/* { dg-do compile } */

22040

+/* { dg-options "-O2 -mtune=atom" } */

22041

+

22042

+int

22043

+foo (void)

22044

+{

22045

+ asm goto ("" : : : : lab);

22046

+ asm goto ("" : : : : lab);

22047

+ asm goto ("" : : : : lab);

22048

+ asm goto ("" : : : : lab);

22049

+ asm goto ("" : : : : lab);

22050

+ asm goto ("" : : : : lab);

22051

+ asm goto ("" : : : : lab);

22052

+ asm goto ("" : : : : lab);

22053

+ asm goto ("" : : : : lab);

22054

+ asm goto ("" : : : : lab);

22055

+ asm goto ("" : : : : lab);

22056

+ asm goto ("" : : : : lab);

22057

+ asm goto ("" : : : : lab);

22058

+ asm goto ("" : : : : lab);

22059

+ asm goto ("" : : : : lab);

22060

+ asm goto ("" : : : : lab);

22061

+ asm goto ("" : : : : lab);

22062

+ asm goto ("" : : : : lab);

22063

+ asm goto ("" : : : : lab);

22064

+ asm goto ("" : : : : lab);

22065

+ return 0;

22066

+lab:

22067

+ return 1;

22068

+}

22069

+

22070

+/* Verify we don't consider asm goto as a jump for four jumps limit

22071

+ optimization. asm goto doesn't have to contain a jump at all,

22072

+ the branching to labels can happen through different means. */

22073

+/* { dg-final { scan-assembler-not "(p2align\[^\n\r\]*\[\n\r]*\[^\n\r\]*){8}p2align" } } */

22074

Index: gcc/testsuite/gcc.target/i386/sse2-movapd-2.c

22075

===================================================================

22076

--- a/src/gcc/testsuite/gcc.target/i386/sse2-movapd-2.c (.../tags/gcc_4_8_2_release)

22077

+++ b/src/gcc/testsuite/gcc.target/i386/sse2-movapd-2.c (.../branches/gcc-4_8-branch)

22078

@@ -25,7 +25,7 @@

22079

TEST (void)

22080

{

22081

union128d u;

22082

- double e[2] __attribute__ ((aligned (8))) = {0.0};

22083

+ double e[2] __attribute__ ((aligned (16))) = {0.0};

22084

22085

u.x = _mm_set_pd (2134.3343,1234.635654);

22086

22087

Index: gcc/testsuite/gcc.target/i386/sse-5.c

22088

===================================================================

22089

--- a/src/gcc/testsuite/gcc.target/i386/sse-5.c (.../tags/gcc_4_8_2_release)

22090

+++ b/src/gcc/testsuite/gcc.target/i386/sse-5.c (.../branches/gcc-4_8-branch)

22091

@@ -1,6 +1,7 @@

22092

/* { dg-do compile } */

22093

/* { dg-require-effective-target ia32 } */

22094

-/* { dg-options "-Winline -Wno-psabi -O2 -mno-sse" } */

22095

+/* { dg-prune-output "ABI for passing parameters" } */

22096

+/* { dg-options "-Winline -O2 -mno-sse" } */

22097

22098

typedef double v2df __attribute__ ((vector_size (16)));

22099

v2df p;

22100

Index: gcc/testsuite/gcc.target/i386/pr39162.c

22101

===================================================================

22102

--- a/src/gcc/testsuite/gcc.target/i386/pr39162.c (.../tags/gcc_4_8_2_release)

22103

+++ b/src/gcc/testsuite/gcc.target/i386/pr39162.c (.../branches/gcc-4_8-branch)

22104

@@ -1,11 +1,14 @@

22105

/* { dg-do compile } */

22106

-/* { dg-options "-O2 -Wno-psabi -msse2 -mno-avx" } */

22107

+/* { dg-prune-output "ABI for passing parameters" } */

22108

+/* { dg-options "-O2 -msse2 -mno-avx" } */

22109

/* { dg-additional-options "-mabi=sysv" { target x86_64-*-mingw* } } */

22110

22111

typedef long long __m256i __attribute__ ((__vector_size__ (32), __may_alias__));

22112

22113

-__m256i

22114

+extern __m256i y;

22115

+

22116

+void

22117

bar (__m256i x) /* { dg-warning "AVX" "" } */

22118

{

22119

- return x;

22120

+ y = x;

22121

}

22122

Index: gcc/testsuite/gcc.target/i386/pr60909-1.c

22123

===================================================================

22124

--- a/src/gcc/testsuite/gcc.target/i386/pr60909-1.c (.../tags/gcc_4_8_2_release)

22125

+++ b/src/gcc/testsuite/gcc.target/i386/pr60909-1.c (.../branches/gcc-4_8-branch)

22126

@@ -0,0 +1,11 @@

22127

+/* { dg-do compile } */

22128

+/* { dg-options "-mrdrnd" } */

22129

+

22130

+extern void bar (int);

22131

+

22132

+void

22133

+foo (unsigned *u)

22134

+{

22135

+ int i = __builtin_ia32_rdrand32_step (u);

22136

+ bar (i);

22137

+}

22138

Index: gcc/testsuite/gcc.target/i386/pr58137.c

22139

===================================================================

22140

--- a/src/gcc/testsuite/gcc.target/i386/pr58137.c (.../tags/gcc_4_8_2_release)

22141

+++ b/src/gcc/testsuite/gcc.target/i386/pr58137.c (.../branches/gcc-4_8-branch)

22142

@@ -0,0 +1,33 @@

22143

+/* { dg-do compile } */

22144

+/* { dg-options "-O3 -mavx2" } */

22145

+

22146

+typedef unsigned int U32;

22147

+

22148

+struct sv {

22149

+ void* sv_any;

22150

+ U32 sv_refcnt;

22151

+ U32 sv_flags;

22152

+};

22153

+typedef struct sv SV;

22154

+

22155

+struct xrv {

22156

+ SV * xrv_rv;

22157

+};

22158

+typedef struct xrv XRV;

22159

+

22160

+extern XRV * PL_xrv_root;

22161

+

22162

+void

22163

+more_xrv (void)

22164

+{

22165

+ register XRV* xrv;

22166

+ register XRV* xrvend;

22167

+ xrv = PL_xrv_root;

22168

+ xrvend = &xrv[200 / sizeof (XRV) - 1];

22169

+ while (xrv < xrvend)

22170

+ {

22171

+ xrv->xrv_rv = (SV*)(xrv + 1);

22172

+ xrv++;

22173

+ }

22174

+ xrv->xrv_rv = 0;

22175

+}

22176

Index: gcc/testsuite/gcc.target/i386/pr59794-4.c

22177

===================================================================

22178

--- a/src/gcc/testsuite/gcc.target/i386/pr59794-4.c (.../tags/gcc_4_8_2_release)

22179

+++ b/src/gcc/testsuite/gcc.target/i386/pr59794-4.c (.../branches/gcc-4_8-branch)

22180

@@ -0,0 +1,14 @@

22181

+/* PR target/59794 */

22182

+/* { dg-do compile { target { ia32 } } } */

22183

+/* { dg-options "-O2 -mno-mmx" } */

22184

+/* { dg-skip-if "no MMX vector" { *-*-mingw* } } */

22185

+

22186

+typedef int __v2si __attribute__ ((__vector_size__ (8)));

22187

+

22188

+extern __v2si x;

22189

+

22190

+__v2si

22191

+foo (void)

22192

+{ /* { dg-warning "MMX vector return without MMX enabled changes the ABI" } */

22193

+ return x;

22194

+}

22195

Index: gcc/testsuite/gcc.target/i386/avx-vzeroupper-16.c

22196

===================================================================

22197

--- a/src/gcc/testsuite/gcc.target/i386/avx-vzeroupper-16.c (.../tags/gcc_4_8_2_release)

22198

+++ b/src/gcc/testsuite/gcc.target/i386/avx-vzeroupper-16.c (.../branches/gcc-4_8-branch)

22199

@@ -1,5 +1,5 @@

22200

/* { dg-do compile { target lp64 } } */

22201

-/* { dg-options "-O2 -mavx -mabi=ms -mtune=generic -dp" } */

22202

+/* { dg-options "-O2 -mavx -mabi=ms -maccumulate-outgoing-args -dp" } */

22203

22204

typedef float __m256 __attribute__ ((__vector_size__ (32), __may_alias__));

22205

22206

Index: gcc/testsuite/gcc.target/i386/pr30315.c

22207

===================================================================

22208

--- a/src/gcc/testsuite/gcc.target/i386/pr30315.c (.../tags/gcc_4_8_2_release)

22209

+++ b/src/gcc/testsuite/gcc.target/i386/pr30315.c (.../branches/gcc-4_8-branch)

22210

@@ -1,6 +1,6 @@

22211

/* { dg-do compile } */

22212

/* { dg-options "-O2" } */

22213

-/* { dg-final { scan-assembler-times "cmp" 4 } } */

22214

+/* { dg-final { scan-assembler-not "cmp" } } */

22215

22216

extern void abort (void);

22217

int c;

22218

@@ -34,39 +34,10 @@

22219

}

22220

#define PLUSCCONLY(T, t) PLUSCCONLY1(T, t, a) PLUSCCONLY1(T, t, b)

22221

22222

-#define MINUSCC(T, t) \

22223

-T minuscc##t (T a, T b) \

22224

-{ \

22225

- T difference = a - b; \

22226

- if (difference > a) \

22227

- abort (); \

22228

- return difference; \

22229

-}

22230

-

22231

-#define DECCC(T, t) \

22232

-T deccc##t (T a, T b) \

22233

-{ \

22234

- T difference = a - b; \

22235

- if (difference > a) \

22236

- c --; \

22237

- return difference; \

22238

-}

22239

-

22240

-#define MINUSCCONLY(T, t) \

22241

-void minuscconly##t (T a, T b) \

22242

-{ \

22243

- T difference = a - b; \

22244

- if (difference > a) \

22245

- abort (); \

22246

-}

22247

-

22248

#define TEST(T, t) \

22249

PLUSCC(T, t) \

22250

PLUSCCONLY(T, t) \

22251

- INCCC(T, t) \

22252

- MINUSCC(T, t) \

22253

- MINUSCCONLY(T, t) \

22254

- DECCC(T, t)

22255

+ INCCC(T, t)

22256

22257

TEST (unsigned long, l)

22258

TEST (unsigned int, i)

22259

@@ -84,14 +55,3 @@

22260

22261

PLUSCCZEXT(a)

22262

PLUSCCZEXT(b)

22263

-

22264

-#define MINUSCCZEXT \

22265

-unsigned long minuscczext (unsigned int a, unsigned int b) \

22266

-{ \

22267

- unsigned int difference = a - b; \

22268

- if (difference > a) \

22269

- abort (); \

22270

- return difference; \

22271

-}

22272

-

22273

-MINUSCCZEXT

22274

Index: gcc/testsuite/gcc.target/i386/pr43869.c

22275

===================================================================

22276

--- a/src/gcc/testsuite/gcc.target/i386/pr43869.c (.../tags/gcc_4_8_2_release)

22277

+++ b/src/gcc/testsuite/gcc.target/i386/pr43869.c (.../branches/gcc-4_8-branch)

22278

@@ -1,4 +1,5 @@

22279

/* { dg-do compile { target lp64 } } */

22280

+/* { dg-options "-maccumulate-outgoing-args" } */

22281

22282

int __attribute__((__noinline__))

22283

bugged(float f1, float f2, float f3, float f4,

22284

Index: gcc/testsuite/gcc.target/i386/pr43546.c

22285

===================================================================

22286

--- a/src/gcc/testsuite/gcc.target/i386/pr43546.c (.../tags/gcc_4_8_2_release)

22287

+++ b/src/gcc/testsuite/gcc.target/i386/pr43546.c (.../branches/gcc-4_8-branch)

22288

@@ -0,0 +1,12 @@

22289

+/* PR target/43546 */

22290

+/* { dg-do compile } */

22291

+/* { dg-options "-O1" } */

22292

+/* { dg-additional-options "-mpreferred-stack-boundary=2 -msseregparm -msse" { target ia32 } } */

22293

+

22294

+extern void bar (double);

22295

+

22296

+void

22297

+foo (void)

22298

+{

22299

+ bar (1.0);

22300

+}

22301

Index: gcc/testsuite/gcc.target/i386/pr43662.c

22302

===================================================================

22303

--- a/src/gcc/testsuite/gcc.target/i386/pr43662.c (.../tags/gcc_4_8_2_release)

22304

+++ b/src/gcc/testsuite/gcc.target/i386/pr43662.c (.../branches/gcc-4_8-branch)

22305

@@ -1,5 +1,5 @@

22306

/* { dg-do compile { target lp64 } } */

22307

-/* { dg-options "-O2" } */

22308

+/* { dg-options "-O2 -maccumulate-outgoing-args" } */

22309

22310

void __attribute__ ((ms_abi)) foo (void)

22311

{

22312

Index: gcc/testsuite/gcc.target/i386/avx-vmovapd-256-1.c

22313

===================================================================

22314

--- a/src/gcc/testsuite/gcc.target/i386/avx-vmovapd-256-1.c (.../tags/gcc_4_8_2_release)

22315

+++ b/src/gcc/testsuite/gcc.target/i386/avx-vmovapd-256-1.c (.../branches/gcc-4_8-branch)

22316

@@ -15,7 +15,7 @@

22317

avx_test (void)

22318

{

22319

union256d u;

22320

- double e [4] __attribute__ ((aligned (8))) = {41124.234,2344.2354,8653.65635,856.43576};

22321

+ double e [4] __attribute__ ((aligned (32))) = {41124.234,2344.2354,8653.65635,856.43576};

22322

22323

u.x = test (e);

22324

22325

Index: gcc/testsuite/gcc.target/i386/nest-1.c

22326

===================================================================

22327

--- a/src/gcc/testsuite/gcc.target/i386/nest-1.c (.../tags/gcc_4_8_2_release)

22328

+++ b/src/gcc/testsuite/gcc.target/i386/nest-1.c (.../branches/gcc-4_8-branch)

22329

@@ -0,0 +1,14 @@

22330

+/* { dg-do compile { target llp64 } } */

22331

+/* { dg-options "" } */

22332

+

22333

+void foo (int i)

22334

+{

22335

+ void nested (void)

22336

+ {

22337

+ char arr[(1U << 31) + 4U];

22338

+ arr[i] = 0;

22339

+ }

22340

+

22341

+ nested ();

22342

+}

22343

+

22344

Index: gcc/testsuite/gcc.target/i386/pr60909-2.c

22345

===================================================================

22346

--- a/src/gcc/testsuite/gcc.target/i386/pr60909-2.c (.../tags/gcc_4_8_2_release)

22347

+++ b/src/gcc/testsuite/gcc.target/i386/pr60909-2.c (.../branches/gcc-4_8-branch)

22348

@@ -0,0 +1,11 @@

22349

+/* { dg-do compile } */

22350

+/* { dg-options "-mrdseed" } */

22351

+

22352

+extern void bar (int);

22353

+

22354

+void

22355

+foo (unsigned *u)

22356

+{

22357

+ int i = __builtin_ia32_rdseed_si_step (u);

22358

+ bar (i);

22359

+}

22360

Index: gcc/testsuite/gcc.target/i386/pr59794-1.c

22361

===================================================================

22362

--- a/src/gcc/testsuite/gcc.target/i386/pr59794-1.c (.../tags/gcc_4_8_2_release)

22363

+++ b/src/gcc/testsuite/gcc.target/i386/pr59794-1.c (.../branches/gcc-4_8-branch)

22364

@@ -0,0 +1,15 @@

22365

+/* PR target/59794 */

22366

+/* { dg-do compile { target { ia32 } } } */

22367

+/* { dg-options "-O2 -mno-mmx" } */

22368

+/* { dg-skip-if "no MMX vector" { *-*-mingw* } } */

22369

+

22370

+typedef int __v2si __attribute__ ((__vector_size__ (8)));

22371

+

22372

+extern __v2si x;

22373

+

22374

+extern void bar (__v2si);

22375

+void

22376

+foo (void)

22377

+{

22378

+ bar (x); /* { dg-message "warning: MMX vector argument without MMX enabled changes the ABI" } */

22379

+}

22380

Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/pr38891.c

22381

===================================================================

22382

--- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/pr38891.c (.../tags/gcc_4_8_2_release)

22383

+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/pr38891.c (.../branches/gcc-4_8-branch)

22384

@@ -1,7 +1,7 @@

22385

/* Test for cross x86_64<->w64 abi standard calls.

22386

*/

22387

/* { dg-do compile } */

22388

-/* { dg-options "-mno-sse" } */

22389

+/* { dg-options "-mno-sse -maccumulate-outgoing-args" } */

22390

#include "callabi.h"

22391

22392

long double

22393

Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-1.c

22394

===================================================================

22395

--- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-1.c (.../tags/gcc_4_8_2_release)

22396

+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-1.c (.../branches/gcc-4_8-branch)

22397

@@ -2,7 +2,7 @@

22398

*/

22399

/* Origin: Kai Tietz <kai.tietz@onevision.com> */

22400

/* { dg-do run } */

22401

-/* { dg-options "-std=gnu99" } */

22402

+/* { dg-options "-std=gnu99 -maccumulate-outgoing-args" } */

22403

#include "callabi.h"

22404

22405

extern __SIZE_TYPE__ strlen (const char *);

22406

Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-2.c

22407

===================================================================

22408

--- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-2.c (.../tags/gcc_4_8_2_release)

22409

+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-2.c (.../branches/gcc-4_8-branch)

22410

@@ -2,7 +2,7 @@

22411

*/

22412

/* Origin: Kai Tietz <kai.tietz@onevision.com> */

22413

/* { dg-do run } */

22414

-/* { dg-options "-std=gnu99" } */

22415

+/* { dg-options "-std=gnu99 -maccumulate-outgoing-args" } */

22416

#include "callabi.h"

22417

22418

extern void abort (void);

22419

Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-3.c

22420

===================================================================

22421

--- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-3.c (.../tags/gcc_4_8_2_release)

22422

+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-3.c (.../branches/gcc-4_8-branch)

22423

@@ -2,7 +2,7 @@

22424

*/

22425

/* Origin: Kai Tietz <kai.tietz@onevision.com> */

22426

/* { dg-do run } */

22427

-/* { dg-options "-std=gnu99" } */

22428

+/* { dg-options "-std=gnu99 -maccumulate-outgoing-args" } */

22429

#include "callabi.h"

22430

22431

extern void abort (void);

22432

Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-4a.c

22433

===================================================================

22434

--- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-4a.c (.../tags/gcc_4_8_2_release)

22435

+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-4a.c (.../branches/gcc-4_8-branch)

22436

@@ -1,6 +1,6 @@

22437

/* Test for cross x86_64<->w64 abi va_list calls. */

22438

/* { dg-do run { target i?86-*-linux* x86_64-*-linux* } } */

22439

-/* { dg-options "-O2 -mabi=ms -std=gnu99 -fno-builtin" } */

22440

+/* { dg-options "-O2 -mabi=ms -std=gnu99 -fno-builtin -maccumulate-outgoing-args" } */

22441

/* { dg-additional-sources "vaarg-4b.c" } */

22442

22443

extern __SIZE_TYPE__ __attribute__ ((sysv_abi)) strlen (const char *);

22444

Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-5a.c

22445

===================================================================

22446

--- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-5a.c (.../tags/gcc_4_8_2_release)

22447

+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-5a.c (.../branches/gcc-4_8-branch)

22448

@@ -1,6 +1,6 @@

22449

/* Test for cross x86_64<->w64 abi va_list calls. */

22450

/* { dg-do run { target i?86-*-linux* x86_64-*-linux* } } */

22451

-/* { dg-options "-O2 -mabi=ms -std=gnu99 -fno-builtin" } */

22452

+/* { dg-options "-O2 -mabi=ms -std=gnu99 -fno-builtin -maccumulate-outgoing-args" } */

22453

/* { dg-additional-sources "vaarg-5b.c" } */

22454

22455

extern void __attribute__ ((sysv_abi)) abort (void);

22456

Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-4b.c

22457

===================================================================

22458

--- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-4b.c (.../tags/gcc_4_8_2_release)

22459

+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-4b.c (.../branches/gcc-4_8-branch)

22460

@@ -1,5 +1,5 @@

22461

/* Test for cross x86_64<->w64 abi va_list calls. */

22462

-/* { dg-options "-O2 -mabi=ms -std=gnu99 -fno-builtin" } */

22463

+/* { dg-options "-O2 -mabi=ms -std=gnu99 -fno-builtin -maccumulate-outgoing-args" } */

22464

22465

#include <stdarg.h>

22466

22467

Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-5b.c

22468

===================================================================

22469

--- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-5b.c (.../tags/gcc_4_8_2_release)

22470

+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-5b.c (.../branches/gcc-4_8-branch)

22471

@@ -1,5 +1,5 @@

22472

/* Test for cross x86_64<->w64 abi va_list calls. */

22473

-/* { dg-options "-O2 -mabi=ms -std=gnu99 -fno-builtin" } */

22474

+/* { dg-options "-O2 -mabi=ms -std=gnu99 -fno-builtin -maccumulate-outgoing-args" } */

22475

22476

#include <stdarg.h>

22477

22478

Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/leaf-1.c

22479

===================================================================

22480

--- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/leaf-1.c (.../tags/gcc_4_8_2_release)

22481

+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/leaf-1.c (.../branches/gcc-4_8-branch)

22482

@@ -1,5 +1,5 @@

22483

/* { dg-do compile } */

22484

-/* { dg-options "-O2 -mabi=sysv" } */

22485

+/* { dg-options "-O2 -mabi=sysv -maccumulate-outgoing-args" } */

22486

22487

__attribute__ ((ms_abi))

22488

int foo (void)

22489

Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/leaf-2.c

22490

===================================================================

22491

--- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/leaf-2.c (.../tags/gcc_4_8_2_release)

22492

+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/leaf-2.c (.../branches/gcc-4_8-branch)

22493

@@ -1,5 +1,5 @@

22494

/* { dg-do compile } */

22495

-/* { dg-options "-O2 -mabi=sysv" } */

22496

+/* { dg-options "-O2 -mabi=sysv -maccumulate-outgoing-args" } */

22497

22498

extern int glb1, gbl2, gbl3;

22499

22500

Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/func-1.c

22501

===================================================================

22502

--- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-1.c (.../tags/gcc_4_8_2_release)

22503

+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-1.c (.../branches/gcc-4_8-branch)

22504

@@ -2,7 +2,7 @@

22505

*/

22506

/* Origin: Kai Tietz <kai.tietz@onevision.com> */

22507

/* { dg-do run } */

22508

-/* { dg-options "-std=gnu99 -ffast-math" } */

22509

+/* { dg-options "-std=gnu99 -ffast-math -maccumulate-outgoing-args" } */

22510

#include "callabi.h"

22511

22512

extern void abort (void);

22513

Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect-2a.c

22514

===================================================================

22515

--- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect-2a.c (.../tags/gcc_4_8_2_release)

22516

+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect-2a.c (.../branches/gcc-4_8-branch)

22517

@@ -1,6 +1,6 @@

22518

/* Test for cross x86_64<->w64 abi standard calls via variable. */

22519

/* { dg-do run { target i?86-*-linux* x86_64-*-linux* } } */

22520

-/* { dg-options "-O2 -mabi=ms -std=gnu99 -ffast-math -fno-builtin" } */

22521

+/* { dg-options "-O2 -mabi=ms -std=gnu99 -ffast-math -fno-builtin -maccumulate-outgoing-args" } */

22522

/* { dg-additional-sources "func-indirect-2b.c" } */

22523

22524

extern void __attribute__ ((sysv_abi)) abort (void);

22525

Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect.c

22526

===================================================================

22527

--- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect.c (.../tags/gcc_4_8_2_release)

22528

+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect.c (.../branches/gcc-4_8-branch)

22529

@@ -2,7 +2,7 @@

22530

*/

22531

/* Origin: Kai Tietz <kai.tietz@onevision.com> */

22532

/* { dg-do run } */

22533

-/* { dg-options "-std=gnu99 -ffast-math" } */

22534

+/* { dg-options "-std=gnu99 -ffast-math -maccumulate-outgoing-args" } */

22535

#include "callabi.h"

22536

22537

extern void abort (void);

22538

Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/func-2a.c

22539

===================================================================

22540

--- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-2a.c (.../tags/gcc_4_8_2_release)

22541

+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-2a.c (.../branches/gcc-4_8-branch)

22542

@@ -1,6 +1,6 @@

22543

/* Test for cross x86_64<->w64 abi standard calls. */

22544

/* { dg-do run { target i?86-*-linux* x86_64-*-linux* } } */

22545

-/* { dg-options "-O2 -mabi=ms -std=gnu99 -ffast-math -fno-builtin" } */

22546

+/* { dg-options "-O2 -mabi=ms -std=gnu99 -ffast-math -fno-builtin -maccumulate-outgoing-args" } */

22547

/* { dg-additional-sources "func-2b.c" } */

22548

22549

extern void __attribute__ ((sysv_abi)) abort (void);

22550

Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect-2b.c

22551

===================================================================

22552

--- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect-2b.c (.../tags/gcc_4_8_2_release)

22553

+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect-2b.c (.../branches/gcc-4_8-branch)

22554

@@ -1,5 +1,5 @@

22555

/* Test for cross x86_64<->w64 abi standard calls via variable. */

22556

-/* { dg-options "-O2 -mabi=ms -std=gnu99 -ffast-math -fno-builtin" } */

22557

+/* { dg-options "-O2 -mabi=ms -std=gnu99 -ffast-math -fno-builtin -maccumulate-outgoing-args" } */

22558

22559

typedef int (*func)(void *, char *, char *, short, long long);

22560

22561

Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/func-2b.c

22562

===================================================================

22563

--- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-2b.c (.../tags/gcc_4_8_2_release)

22564

+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-2b.c (.../branches/gcc-4_8-branch)

22565

@@ -1,5 +1,5 @@

22566

/* Test for cross x86_64<->w64 abi standard calls. */

22567

-/* { dg-options "-mabi=ms -std=gnu99 -ffast-math -fno-builtin" } */

22568

+/* { dg-options "-mabi=ms -std=gnu99 -ffast-math -fno-builtin -maccumulate-outgoing-args" } */

22569

22570

long double func_cross (long double a, double b, float c, long d, int e,

22571

char f)

22572

Index: gcc/testsuite/gcc.target/s390/htm-xl-intrin-1.c

22573

===================================================================

22574

--- a/src/gcc/testsuite/gcc.target/s390/htm-xl-intrin-1.c (.../tags/gcc_4_8_2_release)

22575

+++ b/src/gcc/testsuite/gcc.target/s390/htm-xl-intrin-1.c (.../branches/gcc-4_8-branch)

22576

@@ -1,37 +0,0 @@

22577

-/* This checks the availability of the XL compiler intrinsics for

22578

- transactional execution with the expected prototypes. */

22579

-

22580

-/* { dg-do compile } */

22581

-/* { dg-options "-O3 -march=zEC12 -mzarch" } */

22582

-

22583

-#include <htmxlintrin.h>

22584

-

22585

-int a = 0;

22586

-unsigned long g;

22587

-

22588

-int

22589

-foo ()

22590

-{

22591

- struct __htm_tdb *tdb_struct;

22592

- void * const tdb = tdb_struct;

22593

- long result;

22594

- unsigned char code;

22595

-

22596

- result = __TM_simple_begin ();

22597

- result = __TM_begin (tdb);

22598

- result = __TM_end ();

22599

- __TM_abort ();

22600

- __TM_named_abort (42);

22601

- __TM_non_transactional_store (&g, 42);

22602

- result = __TM_nesting_depth (tdb);

22603

-

22604

- result = __TM_is_user_abort (tdb);

22605

- result = __TM_is_named_user_abort (tdb, &code);

22606

- result = __TM_is_illegal (tdb);

22607

- result = __TM_is_footprint_exceeded (tdb);

22608

- result = __TM_is_nested_too_deep (tdb);

22609

- result = __TM_is_conflict (tdb);

22610

- result = __TM_is_failure_persistent (result);

22611

- result = __TM_failure_address (tdb);

22612

- result = __TM_failure_code (tdb);

22613

-}

22614

Index: gcc/testsuite/gcc.target/s390/htm-1.c

22615

===================================================================

22616

--- a/src/gcc/testsuite/gcc.target/s390/htm-1.c (.../tags/gcc_4_8_2_release)

22617

+++ b/src/gcc/testsuite/gcc.target/s390/htm-1.c (.../branches/gcc-4_8-branch)

22618

@@ -1,73 +0,0 @@

22619

-/* This checks the availability of the low-level builtins introduced

22620

- for transactional execution. */

22621

-

22622

-/* { dg-do compile } */

22623

-/* { dg-options "-O3 -march=zEC12 -mzarch" } */

22624

-

22625

-#include <stdint.h>

22626

-#include <htmintrin.h>

22627

-

22628

-int global = 0;

22629

-uint64_t g;

22630

-struct __htm_tdb global_tdb;

22631

-

22632

-int

22633

-foo (struct __htm_tdb* tdb, int reg, int *mem, uint64_t *mem64)

22634

-{

22635

-

22636

- int cc;

22637

- int n;

22638

-

22639

- cc = __builtin_tbegin (0);

22640

- cc = __builtin_tbegin (tdb);

22641

- cc = __builtin_tbegin (&global_tdb);

22642

-

22643

- cc = __builtin_tbegin_nofloat (0);

22644

- cc = __builtin_tbegin_nofloat (&global_tdb);

22645

-

22646

- cc = __builtin_tbegin_retry (0, 42);

22647

- cc = __builtin_tbegin_retry (0, reg);

22648

- cc = __builtin_tbegin_retry (0, *mem);

22649

- cc = __builtin_tbegin_retry (0, global);

22650

- cc = __builtin_tbegin_retry (tdb, 42);

22651

- cc = __builtin_tbegin_retry (&global_tdb, 42);

22652

-

22653

- cc = __builtin_tbegin_retry_nofloat (0, 42);

22654

- cc = __builtin_tbegin_retry_nofloat (0, reg);

22655

- cc = __builtin_tbegin_retry_nofloat (0, *mem);

22656

- cc = __builtin_tbegin_retry_nofloat (0, global);

22657

- cc = __builtin_tbegin_retry_nofloat (&global_tdb, 42);

22658

-

22659

- __builtin_tbeginc ();

22660

-

22661

- n = __builtin_tx_nesting_depth();

22662

-

22663

- __builtin_non_tx_store(&g, 23);

22664

- __builtin_non_tx_store(mem64, 23);

22665

- __builtin_non_tx_store(&g, reg);

22666

- __builtin_non_tx_store(&g, *mem);

22667

- __builtin_non_tx_store(&g, global);

22668

-

22669

- __builtin_tabort (42 + 255);

22670

- __builtin_tabort (reg);

22671

- /* { dg-final { scan-assembler-times "tabort\t255" 1 } } */

22672

- __builtin_tabort (reg + 255);

22673

- __builtin_tabort (*mem);

22674

- __builtin_tabort (global);

22675

- /* Here global + 255 gets reloaded into a reg. Better would be to

22676

- just reload global or *mem and get the +255 for free as address

22677

- arithmetic. */

22678

- __builtin_tabort (*mem + 255);

22679

- __builtin_tabort (global + 255);

22680

-

22681

- __builtin_tend();

22682

-

22683

- __builtin_tx_assist (23);

22684

- __builtin_tx_assist (reg);

22685

- __builtin_tx_assist (*mem);

22686

- __builtin_tx_assist (global);

22687

-}

22688

-

22689

-/* Make sure the tdb NULL argument ends up as immediate value in the

22690

- instruction. */

22691

-/* { dg-final { scan-assembler-times "tbegin\t0," 10 } } */

22692

Index: gcc/testsuite/gcc.target/s390/htm-nofloat-2.c

22693

===================================================================

22694

--- a/src/gcc/testsuite/gcc.target/s390/htm-nofloat-2.c (.../tags/gcc_4_8_2_release)

22695

+++ b/src/gcc/testsuite/gcc.target/s390/htm-nofloat-2.c (.../branches/gcc-4_8-branch)

22696

@@ -1,55 +0,0 @@

22697

-/* { dg-do run } */

22698

-/* { dg-options "-O3 -mhtm -Wa,-march=zEC12,-mzarch --save-temps" } */

22699

-

22700

-/* __builtin_tbegin has to emit clobbers for all FPRs since the tbegin

22701

- instruction does not automatically preserves them. If the

22702

- transaction body is fully contained in a function the backend tries

22703

- after reload to get rid of the FPR save/restore operations

22704

- triggered by the clobbers. This testcase failed since the backend

22705

- was able to get rid of all FPR saves/restores and since these were

22706

- the only stack operations also of the entire stack space. So even

22707

- the save/restore of the stack pointer was omitted in the end.

22708

- However, since the frame layout has been fixed before, the prologue

22709

- still generated the stack pointer decrement making foo return with

22710

- a modified stack pointer. */

22711

-

22712

-void abort(void);

22713

-

22714

-void __attribute__((noinline))

22715

-foo (int a)

22716

-{

22717

- /* This is just to prevent the tbegin code from actually being

22718

- executed. That way the test may even run on machines prior to

22719

- zEC12. */

22720

- if (a == 42)

22721

- return;

22722

-

22723

- if (__builtin_tbegin (0) == 0)

22724

- __builtin_tend ();

22725

-}

22726

-

22727

-#ifdef __s390x__

22728

-#define GET_STACK_POINTER(SP) \

22729

- asm volatile ("stg %%r15, %0" : "=QRST" (SP));

22730

-#else

22731

-#define GET_STACK_POINTER(SP) \

22732

- asm volatile ("st %%r15, %0" : "=QR" (SP));

22733

-#endif

22734

-

22735

-int main(void)

22736

-{

22737

- unsigned long new_sp, old_sp;

22738

-

22739

- GET_STACK_POINTER (old_sp);

22740

- foo(42);

22741

- GET_STACK_POINTER (new_sp);

22742

-

22743

- if (old_sp != new_sp)

22744

- abort ();

22745

-

22746

- return 0;

22747

-}

22748

-

22749

-/* Make sure no FPR saves/restores are emitted. */

22750

-/* { dg-final { scan-assembler-not "\tstd\t" } } */

22751

-/* { dg-final { scan-assembler-not "\tld\t" } } */

22752

Index: gcc/testsuite/gcc.target/s390/hotpatch-compile-1.c

22753

===================================================================

22754

--- a/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-1.c (.../tags/gcc_4_8_2_release)

22755

+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-1.c (.../branches/gcc-4_8-branch)

22756

@@ -0,0 +1,27 @@

22757

+/* Functional tests for the function hotpatching feature. */

22758

+

22759

+/* { dg-do run } */

22760

+/* { dg-options "-O3 -mzarch -mhotpatch" } */

22761

+

22762

+#include <stdio.h>

22763

+

22764

+void hp1(void)

22765

+{

22766

+ printf("hello, world!\n");

22767

+}

22768

+

22769

+inline void hp2(void)

22770

+{

22771

+ printf("hello, world!\n");

22772

+}

22773

+

22774

+__attribute__ ((always_inline))

22775

+void hp3(void) /* { dg-warning "always_inline function might not be inlinable" } */

22776

+{

22777

+ printf("hello, world!\n");

22778

+} /* { dg-warning "function 'hp3' with the 'always_inline' attribute is not hotpatchable" } */

22779

+

22780

+int main (void)

22781

+{

22782

+ return 0;

22783

+}

22784

Index: gcc/testsuite/gcc.target/s390/hotpatch-compile-2.c

22785

===================================================================

22786

--- a/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-2.c (.../tags/gcc_4_8_2_release)

22787

+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-2.c (.../branches/gcc-4_8-branch)

22788

@@ -0,0 +1,27 @@

22789

+/* Functional tests for the function hotpatching feature. */

22790

+

22791

+/* { dg-do run } */

22792

+/* { dg-options "-O3 -mzarch -mhotpatch=0" } */

22793

+

22794

+#include <stdio.h>

22795

+

22796

+void hp1(void)

22797

+{

22798

+ printf("hello, world!\n");

22799

+}

22800

+

22801

+inline void hp2(void)

22802

+{

22803

+ printf("hello, world!\n");

22804

+}

22805

+

22806

+__attribute__ ((always_inline))

22807

+void hp3(void) /* { dg-warning "always_inline function might not be inlinable" } */

22808

+{

22809

+ printf("hello, world!\n");

22810

+} /* { dg-warning "function 'hp3' with the 'always_inline' attribute is not hotpatchable" } */

22811

+

22812

+int main (void)

22813

+{

22814

+ return 0;

22815

+}

22816

Index: gcc/testsuite/gcc.target/s390/hotpatch-compile-3.c

22817

===================================================================

22818

--- a/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-3.c (.../tags/gcc_4_8_2_release)

22819

+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-3.c (.../branches/gcc-4_8-branch)

22820

@@ -0,0 +1,27 @@

22821

+/* Functional tests for the function hotpatching feature. */

22822

+

22823

+/* { dg-do run } */

22824

+/* { dg-options "-O3 -mzarch -mhotpatch=1" } */

22825

+

22826

+#include <stdio.h>

22827

+

22828

+void hp1(void)

22829

+{

22830

+ printf("hello, world!\n");

22831

+}

22832

+

22833

+inline void hp2(void)

22834

+{

22835

+ printf("hello, world!\n");

22836

+}

22837

+

22838

+__attribute__ ((always_inline))

22839

+void hp3(void) /* { dg-warning "always_inline function might not be inlinable" } */

22840

+{

22841

+ printf("hello, world!\n");

22842

+} /* { dg-warning "function 'hp3' with the 'always_inline' attribute is not hotpatchable" } */

22843

+

22844

+int main (void)

22845

+{

22846

+ return 0;

22847

+}

22848

Index: gcc/testsuite/gcc.target/s390/hotpatch-compile-4.c

22849

===================================================================

22850

--- a/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-4.c (.../tags/gcc_4_8_2_release)

22851

+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-4.c (.../branches/gcc-4_8-branch)

22852

@@ -0,0 +1,11 @@

22853

+/* Functional tests for the function hotpatching feature. */

22854

+

22855

+/* { dg-do compile } */

22856

+/* { dg-options "-O3 -mzarch -mhotpatch=-1" } */

22857

+

22858

+int main (void)

22859

+{

22860

+ return 0;

22861

+}

22862

+

22863

+/* { dg-excess-errors "argument to '-mhotpatch=' should be a non-negative integer" } */

22864

Index: gcc/testsuite/gcc.target/s390/hotpatch-compile-5.c

22865

===================================================================

22866

--- a/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-5.c (.../tags/gcc_4_8_2_release)

22867

+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-5.c (.../branches/gcc-4_8-branch)

22868

@@ -0,0 +1,28 @@

22869

+/* Functional tests for the function hotpatching feature. */

22870

+

22871

+/* { dg-do compile } */

22872

+/* { dg-options "-O3 -mzarch -mhotpatch=1000000" } */

22873

+

22874

+#include <stdio.h>

22875

+

22876

+void hp1(void)

22877

+{

22878

+ printf("hello, world!\n");

22879

+}

22880

+

22881

+__attribute__ ((hotpatch(1000000)))

22882

+void hp2(void)

22883

+{

22884

+ printf("hello, world!\n");

22885

+}

22886

+

22887

+__attribute__ ((hotpatch(1000001)))

22888

+void hp3(void)

22889

+{ /* { dg-error "requested 'hotpatch' attribute is not a non-negative integer constant or too large .max. 1000000." } */

22890

+ printf("hello, world!\n");

22891

+}

22892

+

22893

+int main (void)

22894

+{

22895

+ return 0;

22896

+}

22897

Index: gcc/testsuite/gcc.target/s390/hotpatch-compile-6.c

22898

===================================================================

22899

--- a/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-6.c (.../tags/gcc_4_8_2_release)

22900

+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-6.c (.../branches/gcc-4_8-branch)

22901

@@ -0,0 +1,11 @@

22902

+/* Functional tests for the function hotpatching feature. */

22903

+

22904

+/* { dg-do compile } */

22905

+/* { dg-options "-O3 -mzarch -mhotpatch=1000001" } */

22906

+

22907

+int main (void)

22908

+{

22909

+ return 0;

22910

+}

22911

+

22912

+/* { dg-excess-errors "argument to '-mhotpatch=' is too large .max. 1000000." } */

22913

Index: gcc/testsuite/gcc.target/s390/htm-builtins-compile-1.c

22914

===================================================================

22915

--- a/src/gcc/testsuite/gcc.target/s390/htm-builtins-compile-1.c (.../tags/gcc_4_8_2_release)

22916

+++ b/src/gcc/testsuite/gcc.target/s390/htm-builtins-compile-1.c (.../branches/gcc-4_8-branch)

22917

@@ -0,0 +1,164 @@

22918

+/* This checks the availability of the low-level builtins introduced

22919

+ for transactional execution. */

22920

+

22921

+/* { dg-do compile } */

22922

+/* { dg-options "-O3 -march=zEC12 -mzarch" } */

22923

+

22924

+#include <stdint.h>

22925

+#include <htmintrin.h>

22926

+

22927

+int global = 0;

22928

+uint64_t g;

22929

+struct __htm_tdb global_tdb;

22930

+

22931

+int

22932

+foo (struct __htm_tdb* tdb, int reg, int *mem, uint64_t *mem64)

22933

+{

22934

+

22935

+ int cc;

22936

+ int n;

22937

+

22938

+ __builtin_tbegin ((void *)0);

22939

+ __builtin_tbegin ((void *)-99999);

22940

+ __builtin_tbegin ((void *)99999);

22941

+ while (__builtin_tbegin ((void *)0) != 0)

22942

+ {

22943

+ }

22944

+ cc = __builtin_tbegin ((void *)0x12345678);

22945

+ cc = __builtin_tbegin (tdb);

22946

+ cc = __builtin_tbegin (&global_tdb);

22947

+ cc = __builtin_tbegin ((void *)(long)(reg + 0x12345678));

22948

+ cc = __builtin_tbegin ((void *)(long)(reg));

22949

+

22950

+ __builtin_tbegin_nofloat ((void *)0);

22951

+ __builtin_tbegin_nofloat ((void *)-99999);

22952

+ __builtin_tbegin_nofloat ((void *)99999);

22953

+ cc = __builtin_tbegin_nofloat ((void *)0x12345678);

22954

+ cc = __builtin_tbegin_nofloat (tdb);

22955

+ cc = __builtin_tbegin_nofloat (&global_tdb);

22956

+ cc = __builtin_tbegin_nofloat ((void *)(long)(reg + 0x12345678));

22957

+ cc = __builtin_tbegin_nofloat ((void *)(long)(reg));

22958

+

22959

+ __builtin_tbegin_retry ((void *)0, 0);

22960

+ cc = __builtin_tbegin_retry ((void *)0, 1);

22961

+ cc = __builtin_tbegin_retry ((void *)0, -1);

22962

+ cc = __builtin_tbegin_retry ((void *)0, 42);

22963

+ cc = __builtin_tbegin_retry ((void *)0, reg);

22964

+ cc = __builtin_tbegin_retry ((void *)0, *mem);

22965

+ cc = __builtin_tbegin_retry ((void *)0, global);

22966

+ cc = __builtin_tbegin_retry (tdb, 42);

22967

+ cc = __builtin_tbegin_retry (&global_tdb, 42);

22968

+ cc = __builtin_tbegin_retry ((void *)0x12345678, global);

22969

+ cc = __builtin_tbegin_retry (

22970

+ (void *)(long) (reg + 0x12345678), global + 1);

22971

+ cc = __builtin_tbegin_retry (

22972

+ (void *)(long)(reg), global - 1);

22973

+

22974

+ __builtin_tbegin_retry_nofloat ((void *)0, 0);

22975

+ cc = __builtin_tbegin_retry_nofloat ((void *)0, 1);

22976

+ cc = __builtin_tbegin_retry_nofloat ((void *)0, -1);

22977

+ cc = __builtin_tbegin_retry_nofloat ((void *)0, 42);

22978

+ cc = __builtin_tbegin_retry_nofloat ((void *)0, reg);

22979

+ cc = __builtin_tbegin_retry_nofloat ((void *)0, *mem);

22980

+ cc = __builtin_tbegin_retry_nofloat ((void *)0, global);

22981

+ cc = __builtin_tbegin_retry_nofloat (tdb, 42);

22982

+ cc = __builtin_tbegin_retry_nofloat (&global_tdb, 42);

22983

+ cc = __builtin_tbegin_retry_nofloat ((void *)0x12345678, global);

22984

+ cc = __builtin_tbegin_retry_nofloat (

22985

+ (void *)(long) (reg + 0x12345678), global + 1);

22986

+ cc = __builtin_tbegin_retry_nofloat (

22987

+ (void *)(long)(reg), global - 1);

22988

+

22989

+ __builtin_tbeginc ();

22990

+

22991

+ __builtin_tx_nesting_depth ();

22992

+ n = __builtin_tx_nesting_depth ();

22993

+

22994

+ __builtin_non_tx_store (mem64, 0);

22995

+ {

22996

+ const uint64_t val_var = 0x1122334455667788;

22997

+

22998

+ __builtin_non_tx_store (mem64, val_var);

22999

+ }

23000

+ __builtin_non_tx_store (mem64, (uint64_t)reg);

23001

+ __builtin_non_tx_store (mem64, g);

23002

+ __builtin_non_tx_store ((uint64_t *)0, 0);

23003

+ __builtin_non_tx_store ((uint64_t *)0x12345678, 0);

23004

+ __builtin_non_tx_store (&g, 23);

23005

+ __builtin_non_tx_store (&g, reg);

23006

+ __builtin_non_tx_store (&g, *mem);

23007

+ __builtin_non_tx_store (&g, global);

23008

+

23009

+ __builtin_tend();

23010

+

23011

+ __builtin_tx_assist (0);

23012

+ __builtin_tx_assist (1);

23013

+ __builtin_tx_assist (reg);

23014

+ __builtin_tx_assist (*mem);

23015

+ __builtin_tx_assist (global);

23016

+}

23017

+

23018

+/* The taborts must go into separate function since they are

23019

+ "noreturn". */

23020

+

23021

+void

23022

+tabort1 ()

23023

+{

23024

+ __builtin_tabort (256);

23025

+}

23026

+

23027

+void

23028

+tabort2 (int reg)

23029

+{

23030

+ __builtin_tabort (reg);

23031

+}

23032

+

23033

+void

23034

+tabort3 (int reg)

23035

+{

23036

+ /* { dg-final { scan-assembler-times "tabort\t255" 1 } } */

23037

+ __builtin_tabort (reg + 255);

23038

+}

23039

+

23040

+void

23041

+tabort4 (int *mem)

23042

+{

23043

+ __builtin_tabort (*mem);

23044

+}

23045

+

23046

+void

23047

+tabort5 ()

23048

+{

23049

+ __builtin_tabort (global);

23050

+}

23051

+

23052

+void

23053

+tabort6 (int *mem)

23054

+{

23055

+ /* Here global + 255 gets reloaded into a reg. Better would be to

23056

+ just reload global or *mem and get the +255 for free as address

23057

+ arithmetic. */

23058

+ __builtin_tabort (*mem + 255);

23059

+}

23060

+

23061

+void

23062

+tabort7 ()

23063

+{

23064

+ __builtin_tabort (global + 255);

23065

+}

23066

+

23067

+void

23068

+tabort8 ()

23069

+{

23070

+ __builtin_tabort (-1);

23071

+}

23072

+

23073

+

23074

+/* Make sure the tdb NULL argument ends up as immediate value in the

23075

+ instruction. */

23076

+/* { dg-final { scan-assembler-times "tbegin\t0," 17 } } */

23077

+/* { dg-final { scan-assembler-times "tbegin\t" 41 } } */

23078

+/* Check number of occurences of certain instructions. */

23079

+/* { dg-final { scan-assembler-times "tbeginc\t" 1 } } */

23080

+/* { dg-final { scan-assembler-times "tabort\t" 8 } } */

23081

+/* { dg-final { scan-assembler "ppa\t" } } */

23082

Index: gcc/testsuite/gcc.target/s390/hotpatch-compile-7.c

23083

===================================================================

23084

--- a/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-7.c (.../tags/gcc_4_8_2_release)

23085

+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-7.c (.../branches/gcc-4_8-branch)

23086

@@ -0,0 +1,68 @@

23087

+/* Functional tests for the function hotpatching feature. */

23088

+

23089

+/* { dg-do run } */

23090

+/* { dg-options "-O3 -mzarch -mno-hotpatch" } */

23091

+

23092

+#include <stdio.h>

23093

+

23094

+__attribute__ ((hotpatch))

23095

+void hp1(void)

23096

+{

23097

+ printf("hello, world!\n");

23098

+}

23099

+

23100

+__attribute__ ((hotpatch))

23101

+inline void hp2(void)

23102

+{

23103

+ printf("hello, world!\n");

23104

+}

23105

+

23106

+__attribute__ ((hotpatch))

23107

+__attribute__ ((always_inline))

23108

+void hp3(void) /* { dg-warning "always_inline function might not be inlinable" } */

23109

+{

23110

+ printf("hello, world!\n");

23111

+} /* { dg-warning "function 'hp3' with the 'always_inline' attribute is not hotpatchable" } */

23112

+

23113

+__attribute__ ((hotpatch(0)))

23114

+void hp4(void)

23115

+{

23116

+ printf("hello, world!\n");

23117

+}

23118

+

23119

+__attribute__ ((hotpatch(0)))

23120

+inline void hp5(void)

23121

+{

23122

+ printf("hello, world!\n");

23123

+}

23124

+

23125

+__attribute__ ((hotpatch(0)))

23126

+__attribute__ ((always_inline))

23127

+void hp6(void) /* { dg-warning "always_inline function might not be inlinable" } */

23128

+{

23129

+ printf("hello, world!\n");

23130

+} /* { dg-warning "function 'hp6' with the 'always_inline' attribute is not hotpatchable" } */

23131

+

23132

+__attribute__ ((hotpatch(1)))

23133

+void hp7(void)

23134

+{

23135

+ printf("hello, world!\n");

23136

+}

23137

+

23138

+__attribute__ ((hotpatch(1)))

23139

+inline void hp8(void)

23140

+{

23141

+ printf("hello, world!\n");

23142

+}

23143

+

23144

+__attribute__ ((hotpatch(1)))

23145

+__attribute__ ((always_inline))

23146

+void hp9(void) /* { dg-warning "always_inline function might not be inlinable" } */

23147

+{

23148

+ printf("hello, world!\n");

23149

+} /* { dg-warning "function 'hp9' with the 'always_inline' attribute is not hotpatchable" } */

23150

+

23151

+int main (void)

23152

+{

23153

+ return 0;

23154

+}

23155

Index: gcc/testsuite/gcc.target/s390/htm-builtins-compile-2.c

23156

===================================================================

23157

--- a/src/gcc/testsuite/gcc.target/s390/htm-builtins-compile-2.c (.../tags/gcc_4_8_2_release)

23158

+++ b/src/gcc/testsuite/gcc.target/s390/htm-builtins-compile-2.c (.../branches/gcc-4_8-branch)

23159

@@ -0,0 +1,12 @@

23160

+/* { dg-do compile } */

23161

+/* { dg-options "-O3 -march=zEC12 -mzarch" } */

23162

+

23163

+void must_not_compile1 (void)

23164

+{

23165

+ __builtin_tabort (0); /* { dg-error "Invalid transaction abort code:" } */

23166

+}

23167

+

23168

+void must_not_compile2 (void)

23169

+{

23170

+ __builtin_tabort (255); /* { dg-error "Invalid transaction abort code:" } */

23171

+}

23172

Index: gcc/testsuite/gcc.target/s390/hotpatch-compile-8.c

23173

===================================================================

23174

--- a/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-8.c (.../tags/gcc_4_8_2_release)

23175

+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-8.c (.../branches/gcc-4_8-branch)

23176

@@ -0,0 +1,23 @@

23177

+/* Functional tests for the function hotpatching feature. */

23178

+

23179

+/* { dg-do run } */

23180

+/* { dg-options "-O3 -mzarch -mhotpatch" } */

23181

+

23182

+#include <stdio.h>

23183

+

23184

+int hp1(void)

23185

+{

23186

+ int nested1(void) /* { dg-warning "hotpatching is not compatible with nested functions" } */

23187

+ { return 1; }

23188

+

23189

+ __attribute__ ((hotpatch))

23190

+ int nested2(void) /* { dg-warning "hotpatching is not compatible with nested functions" } */

23191

+ { return 1; }

23192

+

23193

+ return nested1() - nested2();

23194

+}

23195

+

23196

+int main (void)

23197

+{

23198

+ return hp1();

23199

+}

23200

Index: gcc/testsuite/gcc.target/s390/htm-builtins-compile-3.c

23201

===================================================================

23202

--- a/src/gcc/testsuite/gcc.target/s390/htm-builtins-compile-3.c (.../tags/gcc_4_8_2_release)

23203

+++ b/src/gcc/testsuite/gcc.target/s390/htm-builtins-compile-3.c (.../branches/gcc-4_8-branch)

23204

@@ -0,0 +1,37 @@

23205

+/* This checks the availability of the XL compiler intrinsics for

23206

+ transactional execution with the expected prototypes. */

23207

+

23208

+/* { dg-do compile } */

23209

+/* { dg-options "-O3 -march=zEC12 -mzarch" } */

23210

+

23211

+#include <htmxlintrin.h>

23212

+

23213

+int a = 0;

23214

+unsigned long g;

23215

+

23216

+int

23217

+foo ()

23218

+{

23219

+ struct __htm_tdb *tdb_struct;

23220

+ void * const tdb = tdb_struct;

23221

+ long result;

23222

+ unsigned char code;

23223

+

23224

+ result = __TM_simple_begin ();

23225

+ result = __TM_begin (tdb);

23226

+ result = __TM_end ();

23227

+ __TM_abort ();

23228

+ __TM_named_abort (42);

23229

+ __TM_non_transactional_store (&g, 42);

23230

+ result = __TM_nesting_depth (tdb);

23231

+

23232

+ result = __TM_is_user_abort (tdb);

23233

+ result = __TM_is_named_user_abort (tdb, &code);

23234

+ result = __TM_is_illegal (tdb);

23235

+ result = __TM_is_footprint_exceeded (tdb);

23236

+ result = __TM_is_nested_too_deep (tdb);

23237

+ result = __TM_is_conflict (tdb);

23238

+ result = __TM_is_failure_persistent (result);

23239

+ result = __TM_failure_address (tdb);

23240

+ result = __TM_failure_code (tdb);

23241

+}

23242

Index: gcc/testsuite/gcc.target/s390/s390.exp

23243

===================================================================

23244

--- a/src/gcc/testsuite/gcc.target/s390/s390.exp (.../tags/gcc_4_8_2_release)

23245

+++ b/src/gcc/testsuite/gcc.target/s390/s390.exp (.../branches/gcc-4_8-branch)

23246

@@ -24,6 +24,19 @@

23247

# Load support procs.

23248

load_lib gcc-dg.exp

23249

23250

+# Return 1 if htm (etnd - extract nesting depth) instructions are

23251

+# understood by the assembler and can be executed.

23252

+proc check_effective_target_htm { } {

23253

+ if { ![check_runtime s390_check_htm [subst {

23254

+ int main (void)

23255

+ {

23256

+ unsigned int nd;

23257

+ asm ("etnd %0" : "=d" (nd));

23258

+ return nd;

23259

+ }

23260

+ }] "-march=zEC12 -mzarch" ] } { return 0 } else { return 1 }

23261

+}

23262

+

23263

# If a testcase doesn't have special options, use these.

23264

global DEFAULT_CFLAGS

23265

if ![info exists DEFAULT_CFLAGS] then {

23266

Index: gcc/testsuite/gcc.target/s390/htm-nofloat-1.c

23267

===================================================================

23268

--- a/src/gcc/testsuite/gcc.target/s390/htm-nofloat-1.c (.../tags/gcc_4_8_2_release)

23269

+++ b/src/gcc/testsuite/gcc.target/s390/htm-nofloat-1.c (.../branches/gcc-4_8-branch)

23270

@@ -1,12 +1,50 @@

23271

-/* { dg-do compile } */

23272

-/* { dg-options "-O3 -march=zEC12 -mzarch" } */

23273

+/* { dg-do run } */

23274

+/* { dg-require-effective-target htm } */

23275

+/* { dg-options "-O3 -march=zEC12 -mzarch --save-temps" } */

23276

23277

-int

23278

-foo ()

23279

+/* __builtin_tbegin has to emit clobbers for all FPRs since the tbegin

23280

+ instruction does not automatically preserves them. If the

23281

+ transaction body is fully contained in a function the backend tries

23282

+ after reload to get rid of the FPR save/restore operations

23283

+ triggered by the clobbers. This testcase failed since the backend

23284

+ was able to get rid of all FPR saves/restores and since these were

23285

+ the only stack operations also of the entire stack space. So even

23286

+ the save/restore of the stack pointer was omitted in the end.

23287

+ However, since the frame layout has been fixed before, the prologue

23288

+ still generated the stack pointer decrement making foo return with

23289

+ a modified stack pointer. */

23290

+

23291

+void abort(void);

23292

+

23293

+void __attribute__((noinline))

23294

+foo (int a)

23295

{

23296

- __builtin_tbegin_nofloat (0);

23297

- __builtin_tbegin_retry_nofloat (0, 42);

23298

+ if (__builtin_tbegin (0) == 0)

23299

+ __builtin_tend ();

23300

}

23301

+

23302

+#ifdef __s390x__

23303

+#define GET_STACK_POINTER(SP) \

23304

+ asm volatile ("stg %%r15, %0" : "=QRST" (SP));

23305

+#else

23306

+#define GET_STACK_POINTER(SP) \

23307

+ asm volatile ("st %%r15, %0" : "=QR" (SP));

23308

+#endif

23309

+

23310

+int main(void)

23311

+{

23312

+ unsigned long new_sp, old_sp;

23313

+

23314

+ GET_STACK_POINTER (old_sp);

23315

+ foo(42);

23316

+ GET_STACK_POINTER (new_sp);

23317

+

23318

+ if (old_sp != new_sp)

23319

+ abort ();

23320

+

23321

+ return 0;

23322

+}

23323

+

23324

/* Make sure no FPR saves/restores are emitted. */

23325

-/* { dg-final { scan-assembler-not "std" } } */

23326

-/* { dg-final { scan-assembler-not "ld" } } */

23327

+/* { dg-final { scan-assembler-not "\tstd\t" } } */

23328

+/* { dg-final { scan-assembler-not "\tld\t" } } */

23329

Index: gcc/testsuite/gcc.target/s390/hotpatch-1.c

23330

===================================================================

23331

--- a/src/gcc/testsuite/gcc.target/s390/hotpatch-1.c (.../tags/gcc_4_8_2_release)

23332

+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-1.c (.../branches/gcc-4_8-branch)

23333

@@ -0,0 +1,20 @@

23334

+/* Functional tests for the function hotpatching feature. */

23335

+

23336

+/* { dg-do run } */

23337

+/* { dg-options "-O3 -mzarch -mhotpatch --save-temps" } */

23338

+

23339

+#include <stdio.h>

23340

+

23341

+void hp1(void)

23342

+{

23343

+ printf("hello, world!\n");

23344

+}

23345

+

23346

+int main (void)

23347

+{

23348

+ return 0;

23349

+}

23350

+

23351

+/* Check number of occurences of certain instructions. */

23352

+/* { dg-final { scan-assembler-times "nopr\t%r7" 12 } } */

23353

+/* { dg-final { scan-assembler-times "nop\t0" 1 } } */

23354

Index: gcc/testsuite/gcc.target/s390/hotpatch-2.c

23355

===================================================================

23356

--- a/src/gcc/testsuite/gcc.target/s390/hotpatch-2.c (.../tags/gcc_4_8_2_release)

23357

+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-2.c (.../branches/gcc-4_8-branch)

23358

@@ -0,0 +1,20 @@

23359

+/* Functional tests for the function hotpatching feature. */

23360

+

23361

+/* { dg-do run } */

23362

+/* { dg-options "-O3 -mzarch -mhotpatch=1 --save-temps" } */

23363

+

23364

+#include <stdio.h>

23365

+

23366

+void hp1(void)

23367

+{

23368

+ printf("hello, world!\n");

23369

+}

23370

+

23371

+int main (void)

23372

+{

23373

+ return 0;

23374

+}

23375

+

23376

+/* Check number of occurences of certain instructions. */

23377

+/* { dg-final { scan-assembler-times "nopr\t%r7" 1 } } */

23378

+/* { dg-final { scan-assembler-times "nop\t0" 1 } } */

23379

Index: gcc/testsuite/gcc.target/s390/hotpatch-3.c

23380

===================================================================

23381

--- a/src/gcc/testsuite/gcc.target/s390/hotpatch-3.c (.../tags/gcc_4_8_2_release)

23382

+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-3.c (.../branches/gcc-4_8-branch)

23383

@@ -0,0 +1,20 @@

23384

+/* Functional tests for the function hotpatching feature. */

23385

+

23386

+/* { dg-do run } */

23387

+/* { dg-options "-O3 -mzarch -mhotpatch=0 --save-temps" } */

23388

+

23389

+#include <stdio.h>

23390

+

23391

+void hp1(void)

23392

+{

23393

+ printf("hello, world!\n");

23394

+}

23395

+

23396

+int main (void)

23397

+{

23398

+ return 0;

23399

+}

23400

+

23401

+/* Check number of occurences of certain instructions. */

23402

+/* { dg-final { scan-assembler-not "nopr\t%r7" } } */

23403

+/* { dg-final { scan-assembler-times "nop\t0" 1 } } */

23404

Index: gcc/testsuite/gcc.target/s390/hotpatch-4.c

23405

===================================================================

23406

--- a/src/gcc/testsuite/gcc.target/s390/hotpatch-4.c (.../tags/gcc_4_8_2_release)

23407

+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-4.c (.../branches/gcc-4_8-branch)

23408

@@ -0,0 +1,26 @@

23409

+/* Functional tests for the function hotpatching feature. */

23410

+

23411

+/* { dg-do run } */

23412

+/* { dg-options "-O3 -mzarch -mhotpatch --save-temps" } */

23413

+

23414

+#include <stdio.h>

23415

+

23416

+inline void hp1(void)

23417

+{

23418

+ printf("hello, world!\n");

23419

+}

23420

+

23421

+__attribute__ ((always_inline))

23422

+void hp2(void) /* { dg-warning "always_inline function might not be inlinable" } */

23423

+{

23424

+ printf("hello, world!\n");

23425

+} /* { dg-warning "function 'hp2' with the 'always_inline' attribute is not hotpatchable" } */

23426

+

23427

+int main (void)

23428

+{

23429

+ return 0;

23430

+}

23431

+

23432

+/* Check number of occurences of certain instructions. */

23433

+/* { dg-final { scan-assembler-not "nopr\t%r7" } } */

23434

+/* { dg-final { scan-assembler-not "nop\t0" } } */

23435

Index: gcc/testsuite/gcc.target/s390/hotpatch-5.c

23436

===================================================================

23437

--- a/src/gcc/testsuite/gcc.target/s390/hotpatch-5.c (.../tags/gcc_4_8_2_release)

23438

+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-5.c (.../branches/gcc-4_8-branch)

23439

@@ -0,0 +1,21 @@

23440

+/* Functional tests for the function hotpatching feature. */

23441

+

23442

+/* { dg-do run } */

23443

+/* { dg-options "-O3 -mzarch -mhotpatch --save-temps" } */

23444

+

23445

+#include <stdio.h>

23446

+

23447

+__attribute__ ((hotpatch))

23448

+void hp1(void)

23449

+{

23450

+ printf("hello, world!\n");

23451

+}

23452

+

23453

+int main (void)

23454

+{

23455

+ return 0;

23456

+}

23457

+

23458

+/* Check number of occurences of certain instructions. */

23459

+/* { dg-final { scan-assembler-times "nopr\t%r7" 12 } } */

23460

+/* { dg-final { scan-assembler-times "nop\t0" 1 } } */

23461

Index: gcc/testsuite/gcc.target/s390/htm-nofloat-compile-1.c

23462

===================================================================

23463

--- a/src/gcc/testsuite/gcc.target/s390/htm-nofloat-compile-1.c (.../tags/gcc_4_8_2_release)

23464

+++ b/src/gcc/testsuite/gcc.target/s390/htm-nofloat-compile-1.c (.../branches/gcc-4_8-branch)

23465

@@ -0,0 +1,12 @@

23466

+/* { dg-do compile } */

23467

+/* { dg-options "-O3 -march=zEC12 -mzarch" } */

23468

+

23469

+int

23470

+foo ()

23471

+{

23472

+ __builtin_tbegin_nofloat (0);

23473

+ __builtin_tbegin_retry_nofloat (0, 42);

23474

+}

23475

+/* Make sure no FPR saves/restores are emitted. */

23476

+/* { dg-final { scan-assembler-not "std" } } */

23477

+/* { dg-final { scan-assembler-not "ld" } } */

23478

Index: gcc/testsuite/gcc.target/s390/hotpatch-6.c

23479

===================================================================

23480

--- a/src/gcc/testsuite/gcc.target/s390/hotpatch-6.c (.../tags/gcc_4_8_2_release)

23481

+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-6.c (.../branches/gcc-4_8-branch)

23482

@@ -0,0 +1,21 @@

23483

+/* Functional tests for the function hotpatching feature. */

23484

+

23485

+/* { dg-do run } */

23486

+/* { dg-options "-O3 -mzarch -mhotpatch --save-temps" } */

23487

+

23488

+#include <stdio.h>

23489

+

23490

+__attribute__ ((hotpatch(1)))

23491

+void hp1(void)

23492

+{

23493

+ printf("hello, world!\n");

23494

+}

23495

+

23496

+int main (void)

23497

+{

23498

+ return 0;

23499

+}

23500

+

23501

+/* Check number of occurences of certain instructions. */

23502

+/* { dg-final { scan-assembler-times "nopr\t%r7" 1 } } */

23503

+/* { dg-final { scan-assembler-times "nop\t0" 1 } } */

23504

Index: gcc/testsuite/gcc.target/s390/htm-builtins-1.c

23505

===================================================================

23506

--- a/src/gcc/testsuite/gcc.target/s390/htm-builtins-1.c (.../tags/gcc_4_8_2_release)

23507

+++ b/src/gcc/testsuite/gcc.target/s390/htm-builtins-1.c (.../branches/gcc-4_8-branch)

23508

@@ -0,0 +1,1073 @@

23509

+/* Functional tests of the htm __builtin_... macros. */

23510

+

23511

+/* { dg-do run } */

23512

+/* { dg-require-effective-target htm } */

23513

+/* { dg-options "-O3 -march=zEC12 -mzarch" } */

23514

+

23515

+/* ---------------------------- included header files ---------------------- */

23516

+

23517

+#include <stdio.h>

23518

+#include <string.h>

23519

+#include <stdint.h>

23520

+#include <htmintrin.h>

23521

+

23522

+/* ---------------------------- local definitions -------------------------- */

23523

+

23524

+#define DEFAULT_MAX_REPETITIONS 5

23525

+#define DEFAULT_REQUIRED_QUORUM ((DEFAULT_MAX_REPETITIONS) - 1)

23526

+#define NUM_WARMUP_RUNS 10

23527

+

23528

+/* ---------------------------- local macros ------------------------------- */

23529

+

23530

+#define TEST_DF_REP(name) \

23531

+ { #name, name, DEFAULT_MAX_REPETITIONS, DEFAULT_REQUIRED_QUORUM }

23532

+#define TEST_NO_REP(name) { #name, name, 1, 1 }

23533

+

23534

+/* ---------------------------- local types -------------------------------- */

23535

+

23536

+typedef int (*test_func_t)(void);

23537

+

23538

+typedef struct

23539

+{

23540

+ const char *name;

23541

+ test_func_t test_func;

23542

+ int max_repetitions;

23543

+ int required_quorum;

23544

+} test_table_entry_t;

23545

+

23546

+/* ---------------------------- local variables ---------------------------- */

23547

+

23548

+__attribute__ ((aligned(256))) static struct __htm_tdb local_tdb256;

23549

+static struct __htm_tdb local_tdb;

23550

+static int do_dump_tdb = 0;

23551

+

23552

+/* ---------------------------- exported variables (globals) --------------- */

23553

+

23554

+__attribute__ ((aligned(256))) struct

23555

+{

23556

+ float float_1;

23557

+ float float_2;

23558

+ float float_3;

23559

+} global = { 1.0, 2.5, 0.0 };

23560

+

23561

+__attribute__ ((aligned(256))) struct

23562

+{

23563

+ volatile uint64_t c1;

23564

+ volatile uint64_t c2;

23565

+ volatile uint64_t c3;

23566

+} counters = { 0, 0, 0 };

23567

+

23568

+/* ---------------------------- local helper functions --------------------- */

23569

+

23570

+static void dump_tdb (struct __htm_tdb *tdb)

23571

+{

23572

+ unsigned char *p;

23573

+ int i;

23574

+ int j;

23575

+

23576

+ if (do_dump_tdb == 0)

23577

+ {

23578

+ return;

23579

+ }

23580

+ p = (unsigned char *)tdb;

23581

+ for (i = 0; i < 16; i++)

23582

+ {

23583

+ fprintf (stderr, "0x%02x ", i * 16);

23584

+ for (j = 0; j < 16; j++)

23585

+ {

23586

+ fprintf (stderr, "%02x", (int)p[i * 16 + j]);

23587

+ if (j < 15)

23588

+ {

23589

+ fprintf (stderr, " ");

23590

+ }

23591

+ if (j == 7)

23592

+ {

23593

+ fprintf (stderr, " ");

23594

+ }

23595

+ }

23596

+ fprintf (stderr, "\n");

23597

+ }

23598

+

23599

+ return;

23600

+}

23601

+

23602

+/* ---------------------------- local test functions ----------------------- */

23603

+

23604

+/* Check values of the constants defined in htmintrin.h. */

23605

+static int test_constants (void)

23606

+{

23607

+ if (_HTM_TBEGIN_STARTED != 0)

23608

+ {

23609

+ return 100 * _HTM_TBEGIN_STARTED + 1;

23610

+ }

23611

+ if (_HTM_TBEGIN_INDETERMINATE != 1)

23612

+ {

23613

+ return 100 * _HTM_TBEGIN_INDETERMINATE + 2;

23614

+ }

23615

+ if (_HTM_TBEGIN_TRANSIENT != 2)

23616

+ {

23617

+ return 100 * _HTM_TBEGIN_TRANSIENT + 3;

23618

+ }

23619

+ if (_HTM_TBEGIN_PERSISTENT != 3)

23620

+ {

23621

+ return 100 * _HTM_TBEGIN_PERSISTENT + 4;

23622

+ }

23623

+

23624

+ return 0;

23625

+}

23626

+

23627

+static int test_tbegin_ntstg_tend (void)

23628

+{

23629

+ int rc;

23630

+

23631

+ counters.c1 = 0;

23632

+ counters.c2 = 0;

23633

+ if ((rc = __builtin_tbegin ((void *)0)) == 0)

23634

+ {

23635

+ __builtin_non_tx_store ((uint64_t *)&counters.c1, 1);

23636

+ counters.c2 = 2;

23637

+ rc = __builtin_tend ();

23638

+ if (rc != 0)

23639

+ {

23640

+ return 100 * rc + 5;

23641

+ }

23642

+ if (counters.c1 != 1)

23643

+ {

23644

+ return 100 * counters.c1 + 2;

23645

+ }

23646

+ if (counters.c2 != 2)

23647

+ {

23648

+ return 100 * counters.c2 + 3;

23649

+ }

23650

+ }

23651

+ else

23652

+ {

23653

+ return 100 * rc + 4;

23654

+ }

23655

+

23656

+ return 0;

23657

+}

23658

+

23659

+static int test_tbegin_ntstg_tabort (void)

23660

+{

23661

+ float f;

23662

+

23663

+ counters.c1 = 0;

23664

+ counters.c2 = 0;

23665

+ f = 0;

23666

+ if (__builtin_tbegin ((void *)0) == 0)

23667

+ {

23668

+ __builtin_non_tx_store ((uint64_t *)&counters.c1, 1);

23669

+ counters.c2 = 2;

23670

+ f = 1;

23671

+ __builtin_tabort (256);

23672

+ return 1;

23673

+ }

23674

+ if (counters.c1 != 1)

23675

+ {

23676

+ return 100 * counters.c1 + 2;

23677

+ }

23678

+ if (counters.c2 != 0)

23679

+ {

23680

+ return 100 * counters.c2 + 3;

23681

+ }

23682

+ if (f != 0)

23683

+ {

23684

+ return 100 * f + 4;

23685

+ }

23686

+

23687

+ return 0;

23688

+}

23689

+

23690

+static int test_tbegin_nofloat (void)

23691

+{

23692

+ int rc;

23693

+

23694

+ counters.c1 = 0;

23695

+ counters.c2 = 0;

23696

+ if ((rc = __builtin_tbegin_nofloat ((void *)0)) == 0)

23697

+ {

23698

+ __builtin_non_tx_store ((uint64_t *)&counters.c1, 1);

23699

+ counters.c2 = 2;

23700

+ rc = __builtin_tend ();

23701

+ if (rc != 0)

23702

+ {

23703

+ return 100 * rc + 5;

23704

+ }

23705

+ if (counters.c1 != 1)

23706

+ {

23707

+ return 100 * counters.c1 + 2;

23708

+ }

23709

+ if (counters.c2 != 2)

23710

+ {

23711

+ return 100 * counters.c2 + 3;

23712

+ }

23713

+ }

23714

+ else

23715

+ {

23716

+ return 100 * rc + 4;

23717

+ }

23718

+

23719

+ return 0;

23720

+}

23721

+

23722

+static int test_tbegin_retry (void)

23723

+{

23724

+ int rc;

23725

+

23726

+ counters.c1 = 0;

23727

+ counters.c2 = 0;

23728

+ counters.c3 = 0;

23729

+ if ((rc = __builtin_tbegin_retry ((void *)0, 5)) == 0)

23730

+ {

23731

+ int do_abort;

23732

+

23733

+ do_abort = (counters.c1 == 0) ? 1 : 0;

23734

+ __builtin_non_tx_store (

23735

+ (uint64_t *)&counters.c1, counters.c1 + 1);

23736

+ if (do_abort == 1)

23737

+ {

23738

+ __builtin_tabort (256);

23739

+ }

23740

+ counters.c2 = counters.c2 + 10;

23741

+ __builtin_non_tx_store ((uint64_t *)&counters.c3, 3);

23742

+ rc = __builtin_tend ();

23743

+ if (rc != 0)

23744

+ {

23745

+ return 100 * rc + 5;

23746

+ }

23747

+ if (counters.c1 != 2)

23748

+ {

23749

+ return 100 * counters.c1 + 2;

23750

+ }

23751

+ if (counters.c2 != 10)

23752

+ {

23753

+ return 100 * counters.c2 + 3;

23754

+ }

23755

+ if (counters.c3 != 3)

23756

+ {

23757

+ return 100 * counters.c3 + 6;

23758

+ }

23759

+ }

23760

+ else

23761

+ {

23762

+ return 100 * rc + 4;

23763

+ }

23764

+

23765

+ return 0;

23766

+}

23767

+

23768

+static int test_tbegin_retry_nofloat (void)

23769

+{

23770

+ int rc;

23771

+

23772

+ counters.c1 = 0;

23773

+ counters.c2 = 0;

23774

+ counters.c3 = 0;

23775

+ if ((rc = __builtin_tbegin_retry_nofloat ((void *)0, 5)) == 0)

23776

+ {

23777

+ int do_abort;

23778

+

23779

+ do_abort = (counters.c1 == 0) ? 1 : 0;

23780

+ __builtin_non_tx_store (

23781

+ (uint64_t *)&counters.c1, counters.c1 + 1);

23782

+ if (do_abort == 1)

23783

+ {

23784

+ __builtin_tabort (256);

23785

+ }

23786

+ counters.c2 = counters.c2 + 10;

23787

+ __builtin_non_tx_store ((uint64_t *)&counters.c3, 3);

23788

+ rc = __builtin_tend ();

23789

+ if (rc != 0)

23790

+ {

23791

+ return 100 * rc + 5;

23792

+ }

23793

+ if (counters.c1 != 2)

23794

+ {

23795

+ return 100 * counters.c1 + 2;

23796

+ }

23797

+ if (counters.c2 != 10)

23798

+ {

23799

+ return 100 * counters.c2 + 3;

23800

+ }

23801

+ if (counters.c3 != 3)

23802

+ {

23803

+ return 100 * counters.c3 + 6;

23804

+ }

23805

+ }

23806

+ else

23807

+ {

23808

+ return 100 * rc + 4;

23809

+ }

23810

+

23811

+ return 0;

23812

+}

23813

+

23814

+static int test_tbegin_aborts (void)

23815

+{

23816

+ float f;

23817

+ int rc;

23818

+

23819

+ f = 77;

23820

+ if ((rc = __builtin_tbegin ((void *)0)) == 0)

23821

+ {

23822

+ f = 88;

23823

+ __builtin_tabort (256);

23824

+ return 2;

23825

+ }

23826

+ else if (rc != 2)

23827

+ {

23828

+ return 3;

23829

+ }

23830

+ if (f != 77)

23831

+ {

23832

+ return 4;

23833

+ }

23834

+ f = 66;

23835

+ if ((rc = __builtin_tbegin ((void *)0)) == 0)

23836

+ {

23837

+ f = 99;

23838

+ __builtin_tabort (257);

23839

+ return 5;

23840

+ }

23841

+ else if (rc != 3)

23842

+ {

23843

+ return 100 * rc + 6;

23844

+ }

23845

+ if (f != 66)

23846

+ {

23847

+ return 100 * f + 7;

23848

+ }

23849

+ if ((rc = __builtin_tbegin ((void *)0)) == 0)

23850

+ {

23851

+ global.float_3 = global.float_1 + global.float_2;

23852

+ rc = __builtin_tend ();

23853

+ if (rc != 0)

23854

+ {

23855

+ return 100 * rc + 8;

23856

+ }

23857

+ }

23858

+ else

23859

+ {

23860

+ return 100 * rc + 9;

23861

+ }

23862

+ if (global.float_3 != global.float_1 + global.float_2)

23863

+ {

23864

+ return 100 * rc + 10;

23865

+ }

23866

+

23867

+ return 0;

23868

+}

23869

+

23870

+static __attribute__((noinline)) void indirect_abort(int abort_code)

23871

+{

23872

+ __builtin_tabort (abort_code);

23873

+

23874

+ return;

23875

+}

23876

+

23877

+static int test_tbegin_indirect_aborts (void)

23878

+{

23879

+ float f;

23880

+ int rc;

23881

+

23882

+ f = 77;

23883

+ if ((rc = __builtin_tbegin ((void *)0)) == 0)

23884

+ {

23885

+ f = 88;

23886

+ indirect_abort(256);

23887

+ return 2;

23888

+ }

23889

+ else if (rc != 2)

23890

+ {

23891

+ return 100 * rc + 3;

23892

+ }

23893

+ if (f != 77)

23894

+ {

23895

+ return 100 * rc + 4;

23896

+ }

23897

+ f = 66;

23898

+ if ((rc = __builtin_tbegin ((void *)0)) == 0)

23899

+ {

23900

+ f = 99;

23901

+ indirect_abort(257);

23902

+ return 5;

23903

+ }

23904

+ else if (rc != 3)

23905

+ {

23906

+ return 100 * rc + 6;

23907

+ }

23908

+ if (f != 66)

23909

+ {

23910

+ return 100 * f + 7;

23911

+ }

23912

+

23913

+ return 0;

23914

+}

23915

+

23916

+static int test_tbegin_nofloat_aborts (void)

23917

+{

23918

+ int rc;

23919

+

23920

+ if ((rc = __builtin_tbegin_nofloat ((void *)0)) == 0)

23921

+ {

23922

+ __builtin_tabort (256);

23923

+ return 2;

23924

+ }

23925

+ if ((rc = __builtin_tbegin_nofloat ((void *)0)) == 0)

23926

+ {

23927

+ __builtin_tabort (257);

23928

+ return 1005;

23929

+ }

23930

+ else if (rc != 3)

23931

+ {

23932

+ return 1000 * rc + 6;

23933

+ }

23934

+

23935

+ return 0;

23936

+}

23937

+

23938

+static int test_tbegin_nofloat_indirect_aborts (void)

23939

+{

23940

+ int rc;

23941

+

23942

+ if ((rc = __builtin_tbegin_nofloat ((void *)0)) == 0)

23943

+ {

23944

+ indirect_abort (256);

23945

+ return 2;

23946

+ }

23947

+ if ((rc = __builtin_tbegin_nofloat ((void *)0)) == 0)

23948

+ {

23949

+ indirect_abort (257);

23950

+ return 1005;

23951

+ }

23952

+ else if (rc != 3)

23953

+ {

23954

+ return 1000 * rc + 6;

23955

+ }

23956

+

23957

+ return 0;

23958

+}

23959

+

23960

+static

23961

+int _test_tbegin_retry_aborts (int retries, uint64_t abort_code)

23962

+{

23963

+ int rc;

23964

+

23965

+ counters.c1 = 0;

23966

+ if ((rc = __builtin_tbegin_retry ((void *)0, retries)) == 0)

23967

+ {

23968

+ __builtin_non_tx_store ((uint64_t *)&counters.c1, counters.c1 + 1);

23969

+ __builtin_tabort (abort_code);

23970

+ return 2;

23971

+ }

23972

+ else

23973

+ {

23974

+ if ((abort_code & 1) == 0)

23975

+ {

23976

+ if (rc != 2)

23977

+ {

23978

+ return 100 * rc + 2003;

23979

+ }

23980

+ else if (counters.c1 != (uint64_t)retries + 1)

23981

+ {

23982

+ return 1000 * counters.c1 + 100 * retries + 4;

23983

+ }

23984

+ }

23985

+ else

23986

+ {

23987

+ if (rc != 3)

23988

+ {

23989

+ return 100 * rc + 3005;

23990

+ }

23991

+ else if (counters.c1 != 1)

23992

+ {

23993

+ return 1000 * counters.c1 + 100 * retries + 6;

23994

+ }

23995

+ }

23996

+ }

23997

+

23998

+ return 0;

23999

+}

24000

+

24001

+static int test_tbegin_retry_aborts (void)

24002

+{

24003

+ int rc;

24004

+ int retries;

24005

+

24006

+ for (retries = 1; retries <= 3; retries++)

24007

+ {

24008

+ rc = _test_tbegin_retry_aborts (retries, 256);

24009

+ if (rc != 0)

24010

+ {

24011

+ return 10000 + rc;

24012

+ }

24013

+ }

24014

+ for (retries = 1; retries <= 3; retries++)

24015

+ {

24016

+ rc = _test_tbegin_retry_aborts (retries, 257);

24017

+ if (rc != 0)

24018

+ {

24019

+ return 20000 + rc;

24020

+ }

24021

+ }

24022

+ if ((rc = __builtin_tbegin_retry ((void *)0, 5)) == 0)

24023

+ {

24024

+ global.float_3 = global.float_1 + global.float_2;

24025

+ rc = __builtin_tend ();

24026

+ if (rc != 0)

24027

+ {

24028

+ return 30000 + 100 * rc + 6;

24029

+ }

24030

+ }

24031

+ else

24032

+ {

24033

+ return 30000 + 100 * rc + 7;

24034

+ }

24035

+

24036

+ return 0;

24037

+}

24038

+

24039

+static int _test_tbegin_retry_nofloat_aborts (int retries, uint64_t abort_code)

24040

+{

24041

+ int rc;

24042

+

24043

+ counters.c1 = 0;

24044

+ if ((rc = __builtin_tbegin_retry_nofloat ((void *)0, retries)) == 0)

24045

+ {

24046

+ __builtin_non_tx_store ((uint64_t *)&counters.c1, counters.c1 + 1);

24047

+ __builtin_tabort (abort_code);

24048

+ return 2;

24049

+ }

24050

+ else

24051

+ {

24052

+ if ((abort_code & 1) == 0)

24053

+ {

24054

+ if (rc != 2)

24055

+ {

24056

+ return 100 * rc + 2003;

24057

+ }

24058

+ else if (counters.c1 != (uint64_t)retries + 1)

24059

+ {

24060

+ return 1000 * counters.c1 + 100 * retries + 4;

24061

+ }

24062

+ }

24063

+ else

24064

+ {

24065

+ if (rc != 3)

24066

+ {

24067

+ return 100 * rc + 3005;

24068

+ }

24069

+ else if (counters.c1 != 1)

24070

+ {

24071

+ return 1000 * counters.c1 + 100 * retries + 6;

24072

+ }

24073

+ }

24074

+ }

24075

+

24076

+ return 0;

24077

+}

24078

+

24079

+static int test_tbegin_retry_nofloat_aborts (void)

24080

+{

24081

+ int rc;

24082

+ int retries;

24083

+

24084

+ for (retries = 1; retries <= 3; retries++)

24085

+ {

24086

+ rc = _test_tbegin_retry_nofloat_aborts (retries, 256);

24087

+ if (rc != 0)

24088

+ {

24089

+ return 10 * retries + rc;

24090

+ }

24091

+ }

24092

+ for (retries = 1; retries <= 3; retries++)

24093

+ {

24094

+ rc = _test_tbegin_retry_nofloat_aborts (retries, 257);

24095

+ if (rc != 0)

24096

+ {

24097

+ return 10000 + 10 * retries + rc;

24098

+ }

24099

+ }

24100

+

24101

+ return 0;

24102

+}

24103

+

24104

+static int test_tbegin_tdb (void)

24105

+{

24106

+ int rc;

24107

+

24108

+ local_tdb.format = 0;

24109

+ if ((rc = __builtin_tbegin (&local_tdb)) == 0)

24110

+ {

24111

+ rc = __builtin_tend ();

24112

+ if (rc != 0)

24113

+ {

24114

+ return 100 * rc + 1;

24115

+ }

24116

+ if (local_tdb.format != 0)

24117

+ {

24118

+ dump_tdb (&local_tdb);

24119

+ return 100 * local_tdb.format + 2;

24120

+ }

24121

+ }

24122

+ else

24123

+ {

24124

+ return 100 * rc + 3;

24125

+ }

24126

+ local_tdb.format = 0;

24127

+ if ((rc = __builtin_tbegin (&local_tdb)) == 0)

24128

+ {

24129

+ __builtin_tabort (257);

24130

+ return 4;

24131

+ }

24132

+ else

24133

+ {

24134

+ if (rc != 3)

24135

+ {

24136

+ return 100 * rc + 5;

24137

+ }

24138

+ if (local_tdb.format != 1)

24139

+ {

24140

+ dump_tdb (&local_tdb);

24141

+ return 100 * local_tdb.format + 6;

24142

+ }

24143

+ }

24144

+ local_tdb256.format = 0;

24145

+ if ((rc = __builtin_tbegin (&local_tdb256)) == 0)

24146

+ {

24147

+ rc = __builtin_tend ();

24148

+ if (rc != 0)

24149

+ {

24150

+ return 1100 * rc + 1;

24151

+ }

24152

+ if (local_tdb256.format != 0)

24153

+ {

24154

+ dump_tdb (&local_tdb256);

24155

+ return 1100 * local_tdb256.format + 2;

24156

+ }

24157

+ }

24158

+ else

24159

+ {

24160

+ return 1100 * rc + 3;

24161

+ }

24162

+ local_tdb256.format = 0;

24163

+ if ((rc = __builtin_tbegin (&local_tdb256)) == 0)

24164

+ {

24165

+ __builtin_tabort (257);

24166

+ return 2004;

24167

+ }

24168

+ else

24169

+ {

24170

+ if (rc != 3)

24171

+ {

24172

+ return 2100 * rc + 5;

24173

+ }

24174

+ if (local_tdb256.format != 1)

24175

+ {

24176

+ dump_tdb (&local_tdb256);

24177

+ return 2100 * local_tdb256.format + 6;

24178

+ }

24179

+ }

24180

+

24181

+ return 0;

24182

+}

24183

+

24184

+static int test_tbegin_nofloat_tdb (void)

24185

+{

24186

+ int rc;

24187

+

24188

+ local_tdb.format = 0;

24189

+ if ((rc = __builtin_tbegin_nofloat (&local_tdb)) == 0)

24190

+ {

24191

+ rc = __builtin_tend ();

24192

+ if (rc != 0)

24193

+ {

24194

+ return 100 * rc + 1;

24195

+ }

24196

+ if (local_tdb.format != 0)

24197

+ {

24198

+ dump_tdb (&local_tdb);

24199

+ return 100 * local_tdb.format + 2;

24200

+ }

24201

+ }

24202

+ else

24203

+ {

24204

+ return 3;

24205

+ }

24206

+ local_tdb.format = 0;

24207

+ if ((rc = __builtin_tbegin_nofloat (&local_tdb)) == 0)

24208

+ {

24209

+ __builtin_tabort (257);

24210

+ return 4;

24211

+ }

24212

+ else

24213

+ {

24214

+ if (rc != 3)

24215

+ {

24216

+ return 100 * rc + 5;

24217

+ }

24218

+ if (local_tdb.format != 1)

24219

+ {

24220

+ dump_tdb (&local_tdb);

24221

+ return 100 * local_tdb.format + 6;

24222

+ }

24223

+ }

24224

+ local_tdb256.format = 0;

24225

+ if ((rc = __builtin_tbegin_nofloat (&local_tdb256)) == 0)

24226

+ {

24227

+ rc = __builtin_tend ();

24228

+ if (rc != 0)

24229

+ {

24230

+ return 1100 * rc + 1;

24231

+ }

24232

+ if (local_tdb256.format != 0)

24233

+ {

24234

+ dump_tdb (&local_tdb256);

24235

+ return 1100 * local_tdb256.format + 2;

24236

+ }

24237

+ }

24238

+ else

24239

+ {

24240

+ return 1003;

24241

+ }

24242

+ local_tdb256.format = 0;

24243

+ if ((rc = __builtin_tbegin_nofloat (&local_tdb256)) == 0)

24244

+ {

24245

+ __builtin_tabort (257);

24246

+ return 2004;

24247

+ }

24248

+ else

24249

+ {

24250

+ if (rc != 3)

24251

+ {

24252

+ return 2100 * rc + 5;

24253

+ }

24254

+ if (local_tdb256.format != 1)

24255

+ {

24256

+ dump_tdb (&local_tdb256);

24257

+ return 2100 * local_tdb256.format + 6;

24258

+ }

24259

+ }

24260

+

24261

+ return 0;

24262

+}

24263

+

24264

+static int test_tbegin_retry_tdb (void)

24265

+{

24266

+ int rc;

24267

+

24268

+ local_tdb256.format = 0;

24269

+ if ((rc = __builtin_tbegin_retry (&local_tdb256, 2)) == 0)

24270

+ {

24271

+ rc = __builtin_tend ();

24272

+ if (rc != 0)

24273

+ {

24274

+ return 1100 * rc + 1;

24275

+ }

24276

+ if (local_tdb256.format != 0)

24277

+ {

24278

+ dump_tdb (&local_tdb256);

24279

+ return 1100 * local_tdb256.format + 2;

24280

+ }

24281

+ }

24282

+ else

24283

+ {

24284

+ return 1003;

24285

+ }

24286

+ local_tdb256.format = 0;

24287

+ if ((rc = __builtin_tbegin_retry (&local_tdb256, 2)) == 0)

24288

+ {

24289

+ __builtin_tabort (257);

24290

+ return 2004;

24291

+ }

24292

+ else

24293

+ {

24294

+ if (rc != 3)

24295

+ {

24296

+ return 2100 * rc + 5;

24297

+ }

24298

+ if (local_tdb256.format != 1)

24299

+ {

24300

+ dump_tdb (&local_tdb256);

24301

+ return 2100 * local_tdb256.format + 6;

24302

+ }

24303

+ }

24304

+

24305

+ return 0;

24306

+}

24307

+

24308

+static int test_tbegin_retry_nofloat_tdb (void)

24309

+{

24310

+ int rc;

24311

+

24312

+ local_tdb.format = 0;

24313

+ if ((rc = __builtin_tbegin_retry_nofloat (&local_tdb, 2)) == 0)

24314

+ {

24315

+ rc = __builtin_tend ();

24316

+ if (rc != 0)

24317

+ {

24318

+ return 100 * rc + 1;

24319

+ }

24320

+ if (local_tdb.format != 0)

24321

+ {

24322

+ dump_tdb (&local_tdb);

24323

+ return 100 * local_tdb.format + 2;

24324

+ }

24325

+ }

24326

+ else

24327

+ {

24328

+ return 100 * rc + 3;

24329

+ }

24330

+ local_tdb.format = 0;

24331

+ if ((rc = __builtin_tbegin_retry_nofloat (&local_tdb, 2)) == 0)

24332

+ {

24333

+ __builtin_tabort (257);

24334

+ return 4;

24335

+ }

24336

+ else

24337

+ {

24338

+ if (rc != 3)

24339

+ {

24340

+ return 100 * rc + 5;

24341

+ }

24342

+ if (local_tdb.format != 1)

24343

+ {

24344

+ dump_tdb (&local_tdb);

24345

+ return 100 * local_tdb.format + 6;

24346

+ }

24347

+ }

24348

+ local_tdb256.format = 0;

24349

+ if ((rc = __builtin_tbegin_retry_nofloat (&local_tdb256, 2)) == 0)

24350

+ {

24351

+ rc = __builtin_tend ();

24352

+ if (rc != 0)

24353

+ {

24354

+ return 1100 * rc + 1;

24355

+ }

24356

+ if (local_tdb256.format != 0)

24357

+ {

24358

+ dump_tdb (&local_tdb256);

24359

+ return 1100 * local_tdb256.format + 2;

24360

+ }

24361

+ }

24362

+ else

24363

+ {

24364

+ return 1100 * rc + 3;

24365

+ }

24366

+ local_tdb256.format = 0;

24367

+ if ((rc = __builtin_tbegin_retry_nofloat (&local_tdb256, 2)) == 0)

24368

+ {

24369

+ __builtin_tabort (257);

24370

+ return 2004;

24371

+ }

24372

+ else

24373

+ {

24374

+ if (rc != 3)

24375

+ {

24376

+ return 2100 * rc + 5;

24377

+ }

24378

+ if (local_tdb256.format != 1)

24379

+ {

24380

+ dump_tdb (&local_tdb256);

24381

+ return 2100 * local_tdb256.format + 6;

24382

+ }

24383

+ }

24384

+

24385

+ return 0;

24386

+}

24387

+

24388

+static int test_etnd (void)

24389

+{

24390

+ int rc;

24391

+

24392

+ counters.c1 = 0;

24393

+ counters.c2 = 0;

24394

+ counters.c3 = 0;

24395

+ if ((rc = __builtin_tbegin ((void *)0)) == 0)

24396

+ {

24397

+ counters.c1 = __builtin_tx_nesting_depth ();

24398

+ if (__builtin_tbegin ((void *)0) == 0)

24399

+ {

24400

+ counters.c2 = __builtin_tx_nesting_depth ();

24401

+ if (__builtin_tbegin ((void *)0) == 0)

24402

+ {

24403

+ counters.c3 = __builtin_tx_nesting_depth ();

24404

+ __builtin_tend ();

24405

+ }

24406

+ __builtin_tend ();

24407

+ }

24408

+ __builtin_tend ();

24409

+ }

24410

+ else

24411

+ {

24412

+ return 100 * rc + 1;

24413

+ }

24414

+ if (counters.c1 != 1)

24415

+ {

24416

+ return 100 * counters.c1 + 2;

24417

+ }

24418

+ if (counters.c2 != 2)

24419

+ {

24420

+ return 100 * counters.c2 + 3;

24421

+ }

24422

+ if (counters.c3 != 3)

24423

+ {

24424

+ return 100 * counters.c3 + 4;

24425

+ }

24426

+

24427

+ return 0;

24428

+}

24429

+

24430

+static int test_tbeginc (void)

24431

+{

24432

+ int rc;

24433

+

24434

+ counters.c1 = 0;

24435

+ __builtin_tbeginc ();

24436

+ counters.c1 = 1;

24437

+ rc = __builtin_tend ();

24438

+ if (rc != 0)

24439

+ {

24440

+ return 10000 * rc + 1;

24441

+ }

24442

+ if (counters.c1 != 1)

24443

+ {

24444

+ return 100000 * counters.c1 + 3;

24445

+ }

24446

+

24447

+ return 0;

24448

+}

24449

+

24450

+/* ---------------------------- local testing framework functions ---------- */

24451

+

24452

+static int run_one_test (const test_table_entry_t *test_entry)

24453

+{

24454

+ int do_print_passes;

24455

+ int succeeded;

24456

+ int rc;

24457

+ int i;

24458

+

24459

+ /* Warmup run to get all necessary data and instruction pages into the page

24460

+ * tables. */

24461

+ {

24462

+ int run;

24463

+

24464

+ do_dump_tdb = 0;

24465

+ for (run = 0; run < NUM_WARMUP_RUNS; run++)

24466

+ {

24467

+ test_entry->test_func ();

24468

+ }

24469

+ do_dump_tdb = 1;

24470

+ }

24471

+ do_print_passes = (

24472

+ test_entry->required_quorum != 1 ||

24473

+ test_entry->max_repetitions != 1);

24474

+ printf ("RRR RUN %s\n", test_entry->name);

24475

+ if (do_print_passes == 1)

24476

+ {

24477

+ printf (

24478

+ " (requires %d successful out of %d runs)\n",

24479

+ test_entry->required_quorum,

24480

+ test_entry->max_repetitions);

24481

+ }

24482

+ succeeded = 0;

24483

+ rc = 0;

24484

+ for (rc = 0, i = 0; i < test_entry->max_repetitions; i++)

24485

+ {

24486

+ if (do_print_passes == 1)

24487

+ {

24488

+ if (i == 0)

24489

+ {

24490

+ printf (" ");

24491

+ }

24492

+ else

24493

+ {

24494

+ printf (",");

24495

+ }

24496

+ }

24497

+ rc = test_entry->test_func ();

24498

+ if (rc == 0)

24499

+ {

24500

+ if (do_print_passes == 1)

24501

+ {

24502

+ printf (" success");

24503

+ }

24504

+ succeeded++;

24505

+ if (succeeded >= test_entry->required_quorum)

24506

+ {

24507

+ break;

24508

+ }

24509

+ }

24510

+ else

24511

+ {

24512

+ printf (" failed (rc = %d)", rc);

24513

+ }

24514

+ }

24515

+ if (do_print_passes == 1 || rc != 0)

24516

+ {

24517

+ printf ("\n");

24518

+ }

24519

+ if (succeeded >= test_entry->required_quorum)

24520

+ {

24521

+ printf ("+++ OK %s\n", test_entry->name);

24522

+

24523

+ return 0;

24524

+ }

24525

+ else

24526

+ {

24527

+ printf ("--- FAIL %s\n", test_entry->name);

24528

+

24529

+ return (rc != 0) ? rc : -1;

24530

+ }

24531

+}

24532

+

24533

+static int run_all_tests (const test_table_entry_t *test_table)

24534

+{

24535

+ const test_table_entry_t *test;

24536

+ int rc;

24537

+

24538

+ for (

24539

+ rc = 0, test = &test_table[0];

24540

+ test->test_func != NULL && rc == 0; test++)

24541

+ {

24542

+ rc = run_one_test (test);

24543

+ }

24544

+

24545

+ return rc;

24546

+}

24547

+

24548

+/* ---------------------------- interface functions ------------------------ */

24549

+

24550

+int main (void)

24551

+{

24552

+ const test_table_entry_t test_table[] = {

24553

+ TEST_NO_REP (test_constants),

24554

+ TEST_DF_REP (test_tbegin_ntstg_tend),

24555

+ TEST_DF_REP (test_tbegin_ntstg_tabort),

24556

+ TEST_DF_REP (test_tbegin_nofloat),

24557

+ TEST_NO_REP (test_tbegin_retry),

24558

+ TEST_NO_REP (test_tbegin_retry_nofloat),

24559

+ TEST_DF_REP (test_tbegin_aborts),

24560

+ TEST_DF_REP (test_tbegin_indirect_aborts),

24561

+ TEST_DF_REP (test_tbegin_nofloat_aborts),

24562

+ TEST_DF_REP (test_tbegin_nofloat_indirect_aborts),

24563

+ TEST_NO_REP (test_tbegin_retry_aborts),

24564

+ TEST_NO_REP (test_tbegin_retry_nofloat_aborts),

24565

+ TEST_DF_REP (test_tbegin_tdb),

24566

+ TEST_DF_REP (test_tbegin_nofloat_tdb),

24567

+ TEST_NO_REP (test_tbegin_retry_tdb),

24568

+ TEST_NO_REP (test_tbegin_retry_nofloat_tdb),

24569

+ TEST_DF_REP (test_etnd),

24570

+ TEST_DF_REP (test_tbeginc),

24571

+ { (void *)0, 0, 0 }

24572

+ };

24573

+

24574

+ {

24575

+ int rc;

24576

+

24577

+ rc = run_all_tests (test_table);

24578

+

24579

+ return rc;

24580

+ }

24581

+}

24582

Index: gcc/testsuite/gcc.target/s390/hotpatch-7.c

24583

===================================================================

24584

--- a/src/gcc/testsuite/gcc.target/s390/hotpatch-7.c (.../tags/gcc_4_8_2_release)

24585

+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-7.c (.../branches/gcc-4_8-branch)

24586

@@ -0,0 +1,21 @@

24587

+/* Functional tests for the function hotpatching feature. */

24588

+

24589

+/* { dg-do run } */

24590

+/* { dg-options "-O3 -mzarch -mhotpatch --save-temps" } */

24591

+

24592

+#include <stdio.h>

24593

+

24594

+__attribute__ ((hotpatch(0)))

24595

+void hp1(void)

24596

+{

24597

+ printf("hello, world!\n");

24598

+}

24599

+

24600

+int main (void)

24601

+{

24602

+ return 0;

24603

+}

24604

+

24605

+/* Check number of occurences of certain instructions. */

24606

+/* { dg-final { scan-assembler-not "nopr\t%r7" } } */

24607

+/* { dg-final { scan-assembler-times "nop\t0" 1 } } */

24608

Index: gcc/testsuite/gcc.target/s390/htm-builtins-2.c

24609

===================================================================

24610

--- a/src/gcc/testsuite/gcc.target/s390/htm-builtins-2.c (.../tags/gcc_4_8_2_release)

24611

+++ b/src/gcc/testsuite/gcc.target/s390/htm-builtins-2.c (.../branches/gcc-4_8-branch)

24612

@@ -0,0 +1,682 @@

24613

+/* Functional tests of the htm __TM_... macros. */

24614

+

24615

+/* { dg-do run } */

24616

+/* { dg-require-effective-target htm } */

24617

+/* { dg-options "-O3 -march=zEC12 -mzarch" } */

24618

+

24619

+/* ---------------------------- included header files ---------------------- */

24620

+

24621

+#include <stdio.h>

24622

+#include <string.h>

24623

+#include <inttypes.h>

24624

+#include <htmxlintrin.h>

24625

+

24626

+/* ---------------------------- local definitions -------------------------- */

24627

+

24628

+#define DEFAULT_MAX_REPETITIONS 5

24629

+#define DEFAULT_REQUIRED_QUORUM ((DEFAULT_MAX_REPETITIONS) - 1)

24630

+#define DEFAULT_ABORT_ADDRESS (0x12345678u)

24631

+

24632

+/* ---------------------------- local macros ------------------------------- */

24633

+

24634

+#define TEST_DF_REP(name) \

24635

+ { #name, name, DEFAULT_MAX_REPETITIONS, DEFAULT_REQUIRED_QUORUM }

24636

+#define TEST_NO_REP(name) { #name, name, 1, 1 }

24637

+

24638

+/* ---------------------------- local types -------------------------------- */

24639

+

24640

+typedef int (*test_func_t)(void);

24641

+

24642

+typedef struct

24643

+{

24644

+ const char *name;

24645

+ test_func_t test_func;

24646

+ int max_repetitions;

24647

+ int required_quorum;

24648

+} test_table_entry_t;

24649

+

24650

+typedef enum

24651

+{

24652

+ ABORT_T_SYSTEM = 0,

24653

+ ABORT_T_USER = 1,

24654

+} abort_user_t;

24655

+

24656

+typedef enum

24657

+{

24658

+ ABORT_T_NONE = 0,

24659

+ ABORT_T_ILLEGAL,

24660

+ ABORT_T_FOOTPRINT_EXCEEDED,

24661

+ ABORT_T_NESTED_TOO_DEEP,

24662

+ ABORT_T_CONFLICT,

24663

+

24664

+ ABORT_T_INVALID_ABORT_CODE

24665

+} abort_t;

24666

+

24667

+/* ---------------------------- local variables ---------------------------- */

24668

+

24669

+__attribute__ ((aligned(256))) static struct __htm_tdb local_tdb256;

24670

+static struct __htm_tdb local_tdb;

24671

+

24672

+static abort_t const abort_classes[] =

24673

+{

24674

+ ABORT_T_INVALID_ABORT_CODE,

24675

+ ABORT_T_NONE,

24676

+ ABORT_T_NONE,

24677

+ ABORT_T_NONE,

24678

+

24679

+ ABORT_T_ILLEGAL,

24680

+ ABORT_T_NONE,

24681

+ ABORT_T_NONE,

24682

+ ABORT_T_FOOTPRINT_EXCEEDED,

24683

+

24684

+ ABORT_T_FOOTPRINT_EXCEEDED,

24685

+ ABORT_T_CONFLICT,

24686

+ ABORT_T_CONFLICT,

24687

+ ABORT_T_ILLEGAL,

24688

+

24689

+ ABORT_T_NONE,

24690

+ ABORT_T_NESTED_TOO_DEEP,

24691

+ ABORT_T_NONE,

24692

+ ABORT_T_NONE,

24693

+

24694

+ ABORT_T_NONE

24695

+};

24696

+

24697

+static size_t num_abort_classes = sizeof(abort_classes) / sizeof(abort_t);

24698

+

24699

+/* ---------------------------- exported variables (globals) --------------- */

24700

+

24701

+int global_int = 0;

24702

+uint64_t global_u64 = 0;

24703

+float global_float_1 = 1.0;

24704

+float global_float_2 = 2.5;

24705

+float global_float_3 = 0.0;

24706

+__attribute__ ((aligned(256))) struct

24707

+{

24708

+ volatile uint64_t c1;

24709

+ volatile uint64_t c2;

24710

+ volatile uint64_t c3;

24711

+} counters = { 0, 0, 0 };

24712

+

24713

+/* ---------------------------- local helper functions --------------------- */

24714

+

24715

+static void dump_tdb(struct __htm_tdb *tdb)

24716

+{

24717

+ unsigned char *p;

24718

+ int i;

24719

+ int j;

24720

+

24721

+ p = (unsigned char *)tdb;

24722

+ for (i = 0; i < 16; i++)

24723

+ {

24724

+ fprintf(stderr, "0x%02x ", i * 16);

24725

+ for (j = 0; j < 16; j++)

24726

+ {

24727

+ fprintf(stderr, "%02x", (int)p[i * 16 + j]);

24728

+ if (j < 15)

24729

+ {

24730

+ fprintf(stderr, " ");

24731

+ }

24732

+ if (j == 7)

24733

+ {

24734

+ fprintf(stderr, " ");

24735

+ }

24736

+ }

24737

+ fprintf(stderr, "\n");

24738

+ }

24739

+

24740

+ return;

24741

+}

24742

+

24743

+static void make_fake_tdb(struct __htm_tdb *tdb)

24744

+{

24745

+ memset(tdb, 0, sizeof(*tdb));

24746

+ tdb->format = 1;

24747

+ tdb->nesting_depth = 1;

24748

+ tdb->atia = DEFAULT_ABORT_ADDRESS;

24749

+ tdb->abort_code = 11;

24750

+

24751

+ return;

24752

+}

24753

+

24754

+static int check_abort_code_in_tdb(struct __htm_tdb *tdb, uint64_t abort_code)

24755

+{

24756

+ long expect_rc;

24757

+ long rc;

24758

+

24759

+ if (abort_code != 0)

24760

+ {

24761

+ long addr;

24762

+

24763

+ addr = __TM_failure_address(&local_tdb);

24764

+ if (addr != DEFAULT_ABORT_ADDRESS)

24765

+ {

24766

+ return 11;

24767

+ }

24768

+ }

24769

+ {

24770

+ long long tdb_abort_code;

24771

+

24772

+ tdb_abort_code = __TM_failure_code(tdb);

24773

+ if ((uint64_t)tdb_abort_code != abort_code)

24774

+ {

24775

+ fprintf(

24776

+ stderr, "tm_ac %" PRIu64 ", ac %" PRIu64

24777

+ ", tdb_ac %" PRIu64 "\n",

24778

+ (uint64_t)tdb_abort_code, abort_code,

24779

+ (uint64_t)tdb->abort_code);

24780

+ return 10;

24781

+ }

24782

+ }

24783

+ expect_rc = (abort_code >= 256) ? 1 : 0;

24784

+ rc = __TM_is_user_abort(tdb);

24785

+ if (rc != expect_rc)

24786

+ {

24787

+ fprintf(stderr, "rc %ld, expect_rc %ld\n", rc, expect_rc);

24788

+ return 1;

24789

+ }

24790

+ {

24791

+ unsigned char code;

24792

+

24793

+ code = 0xffu;

24794

+ rc = __TM_is_named_user_abort(tdb, &code);

24795

+ if (rc != expect_rc)

24796

+ {

24797

+ fprintf(

24798

+ stderr, "rc %ld, expect_rc %ld\n", rc,

24799

+ expect_rc);

24800

+ return 2;

24801

+ }

24802

+ if (expect_rc == 1 && code != abort_code - 256)

24803

+ {

24804

+ return 3;

24805

+ }

24806

+ }

24807

+ if (abort_code > (uint64_t)num_abort_classes)

24808

+ {

24809

+ abort_code = (uint64_t)num_abort_classes;

24810

+ }

24811

+ expect_rc = (abort_classes[abort_code] == ABORT_T_ILLEGAL) ? 1 : 0;

24812

+ rc = __TM_is_illegal(tdb);

24813

+ if (rc != expect_rc)

24814

+ {

24815

+ dump_tdb(tdb);

24816

+ fprintf(stderr, "rc %ld, expect_rc %ld\n", rc, expect_rc);

24817

+ return 4;

24818

+ }

24819

+ expect_rc =

24820

+ (abort_classes[abort_code] == ABORT_T_FOOTPRINT_EXCEEDED) ?

24821

+ 1 : 0;

24822

+ rc = __TM_is_footprint_exceeded(tdb);

24823

+ if (rc != expect_rc)

24824

+ {

24825

+ dump_tdb(tdb);

24826

+ fprintf(stderr, "rc %ld, expect_rc %ld\n", rc, expect_rc);

24827

+ return 5;

24828

+ }

24829

+ expect_rc =

24830

+ (abort_classes[abort_code] == ABORT_T_NESTED_TOO_DEEP) ? 1 : 0;

24831

+ rc = __TM_is_nested_too_deep(tdb);

24832

+ if (rc != expect_rc)

24833

+ {

24834

+ dump_tdb(tdb);

24835

+ fprintf(stderr, "rc %ld, expect_rc %ld\n", rc, expect_rc);

24836

+ return 6;

24837

+ }

24838

+ expect_rc = (abort_classes[abort_code] == ABORT_T_CONFLICT) ? 1 : 0;

24839

+ rc = __TM_is_conflict(tdb);

24840

+ if (rc != expect_rc)

24841

+ {

24842

+ dump_tdb(tdb);

24843

+ fprintf(stderr, "rc %ld, expect_rc %ld\n", rc, expect_rc);

24844

+ return 7;

24845

+ }

24846

+

24847

+ return 0;

24848

+}

24849

+

24850

+/* ---------------------------- local test functions ----------------------- */

24851

+

24852

+/* Not a test; make sure that the involved global cachelines are reserved for

24853

+ * writing. */

24854

+static int init_cache(void)

24855

+{

24856

+ make_fake_tdb(&local_tdb);

24857

+ make_fake_tdb(&local_tdb256);

24858

+ global_int = 0;

24859

+ global_u64 = 0;

24860

+ global_float_1 = 1.0;

24861

+ global_float_2 = 2.5;

24862

+ global_float_3 = 0.0;

24863

+ counters.c1 = 0;

24864

+ counters.c2 = 0;

24865

+ counters.c3 = 0;

24866

+

24867

+ return 0;

24868

+}

24869

+

24870

+static int test_abort_classification(void)

24871

+{

24872

+ int i;

24873

+

24874

+ make_fake_tdb(&local_tdb);

24875

+ for (i = 0; i <= 256; i++)

24876

+ {

24877

+ int rc;

24878

+

24879

+ local_tdb.abort_code = (uint64_t)i;

24880

+ rc = check_abort_code_in_tdb(&local_tdb, (uint64_t)i);

24881

+ if (rc != 0)

24882

+ {

24883

+ return 100 * i + rc;

24884

+ }

24885

+ }

24886

+

24887

+ return 0;

24888

+}

24889

+

24890

+static int test_cc_classification(void)

24891

+{

24892

+ long rc;

24893

+

24894

+ rc = __TM_is_failure_persistent(0);

24895

+ if (rc != 0)

24896

+ {

24897

+ return 1;

24898

+ }

24899

+ rc = __TM_is_failure_persistent(1);

24900

+ if (rc != 0)

24901

+ {

24902

+ return 2;

24903

+ }

24904

+ rc = __TM_is_failure_persistent(2);

24905

+ if (rc != 0)

24906

+ {

24907

+ return 3;

24908

+ }

24909

+ rc = __TM_is_failure_persistent(3);

24910

+ if (rc != 1)

24911

+ {

24912

+ return 4;

24913

+ }

24914

+

24915

+ return 0;

24916

+}

24917

+

24918

+static int test_tbegin_ntstg_tend(void)

24919

+{

24920

+ long rc;

24921

+

24922

+ counters.c1 = 0;

24923

+ counters.c2 = 0;

24924

+ if ((rc = __TM_simple_begin()) == 0)

24925

+ {

24926

+ __TM_non_transactional_store((uint64_t *)&counters.c1, 1);

24927

+ counters.c2 = 2;

24928

+ rc = __TM_end();

24929

+ if (rc != 0)

24930

+ {

24931

+ return 100 * rc + 5;

24932

+ }

24933

+ if (counters.c1 != 1)

24934

+ {

24935

+ return 100 * counters.c1 + 2;

24936

+ }

24937

+ if (counters.c2 != 2)

24938

+ {

24939

+ return 100 * counters.c2 + 3;

24940

+ }

24941

+ }

24942

+ else

24943

+ {

24944

+ return 100 * rc + 4;

24945

+ }

24946

+

24947

+ return 0;

24948

+}

24949

+

24950

+static int test_tbegin_ntstg_tabort(void)

24951

+{

24952

+ register float f;

24953

+

24954

+ counters.c1 = 0;

24955

+ counters.c2 = 0;

24956

+ f = 0;

24957

+ if (__TM_simple_begin() == 0)

24958

+ {

24959

+ __TM_non_transactional_store((uint64_t *)&counters.c1, 1);

24960

+ counters.c2 = 2;

24961

+ f = 1;

24962

+ __TM_named_abort(0);

24963

+ return 1;

24964

+ }

24965

+ if (counters.c1 != 1)

24966

+ {

24967

+ return 100 * counters.c1 + 2;

24968

+ }

24969

+ if (counters.c2 != 0)

24970

+ {

24971

+ return 100 * counters.c2 + 3;

24972

+ }

24973

+ if (f != 0)

24974

+ {

24975

+ return 100 * f + 4;

24976

+ }

24977

+

24978

+ return 0;

24979

+}

24980

+

24981

+static int test_tbegin_aborts(void)

24982

+{

24983

+ float f;

24984

+ long rc;

24985

+

24986

+ f = 77;

24987

+ if ((rc = __TM_simple_begin()) == 0)

24988

+ {

24989

+ f = 88;

24990

+ __TM_abort();

24991

+ return 2;

24992

+ }

24993

+ else if (rc != 2)

24994

+ {

24995

+ return 3;

24996

+ }

24997

+ if (f != 77)

24998

+ {

24999

+ return 4;

25000

+ }

25001

+ f = 66;

25002

+ if ((rc = __TM_simple_begin()) == 0)

25003

+ {

25004

+ f = 99;

25005

+ __TM_named_abort(3);

25006

+ return 5;

25007

+ }

25008

+ else if (rc != 3)

25009

+ {

25010

+ return 100 * rc + 6;

25011

+ }

25012

+ if (f != 66)

25013

+ {

25014

+ return 100 * f + 7;

25015

+ }

25016

+ if ((rc = __TM_simple_begin()) == 0)

25017

+ {

25018

+ global_float_3 = global_float_1 + global_float_2;

25019

+ rc = __TM_end();

25020

+ if (rc != 0)

25021

+ {

25022

+ return 100 * rc + 8;

25023

+ }

25024

+ }

25025

+ else

25026

+ {

25027

+ return 100 * rc + 9;

25028

+ }

25029

+ if (global_float_3 != global_float_1 + global_float_2)

25030

+ {

25031

+ return 100 * rc + 10;

25032

+ }

25033

+

25034

+ return 0;

25035

+}

25036

+

25037

+static int test_tbegin_tdb(void)

25038

+{

25039

+ long rc;

25040

+

25041

+ local_tdb.format = 0;

25042

+ if ((rc = __TM_begin(&local_tdb)) == 0)

25043

+ {

25044

+ rc = __TM_end();

25045

+ if (rc != 0)

25046

+ {

25047

+ return 100 * rc + 1;

25048

+ }

25049

+ if (local_tdb.format != 0)

25050

+ {

25051

+ dump_tdb(&local_tdb);

25052

+ return 100 * local_tdb.format + 2;

25053

+ }

25054

+ }

25055

+ else

25056

+ {

25057

+ return 100 * rc + 3;

25058

+ }

25059

+ local_tdb.format = 0;

25060

+ if ((rc = __TM_begin(&local_tdb)) == 0)

25061

+ {

25062

+ __TM_named_abort(1);

25063

+ return 4;

25064

+ }

25065

+ else

25066

+ {

25067

+ if (rc != 3)

25068

+ {

25069

+ return 100 * rc + 5;

25070

+ }

25071

+ if (local_tdb.format != 1)

25072

+ {

25073

+ dump_tdb(&local_tdb);

25074

+ return 100 * local_tdb.format + 6;

25075

+ }

25076

+ }

25077

+ local_tdb256.format = 0;

25078

+ if ((rc = __TM_begin(&local_tdb256)) == 0)

25079

+ {

25080

+ rc = __TM_end();

25081

+ if (rc != 0)

25082

+ {

25083

+ return 1100 * rc + 1;

25084

+ }

25085

+ if (local_tdb256.format != 0)

25086

+ {

25087

+ dump_tdb(&local_tdb256);

25088

+ return 1100 * local_tdb256.format + 2;

25089

+ }

25090

+ }

25091

+ else

25092

+ {

25093

+ return 1100 * rc + 3;

25094

+ }

25095

+#if 1 /*!!!does not work*/

25096

+ local_tdb256.format = 0;

25097

+ if ((rc = __TM_begin(&local_tdb256)) == 0)

25098

+ {

25099

+ __TM_named_abort(1);

25100

+ return 2004;

25101

+ }

25102

+ else

25103

+ {

25104

+ if (rc != 3)

25105

+ {

25106

+ return 2100 * rc + 5;

25107

+ }

25108

+ if (local_tdb256.format != 1)

25109

+ {

25110

+ dump_tdb(&local_tdb256);

25111

+ return 2100 * local_tdb256.format + 6;

25112

+ }

25113

+ }

25114

+#endif

25115

+

25116

+ return 0;

25117

+}

25118

+

25119

+static int test_etnd(void)

25120

+{

25121

+ long rc;

25122

+

25123

+ {

25124

+ long nd;

25125

+

25126

+ make_fake_tdb(&local_tdb);

25127

+ local_tdb.nesting_depth = 0;

25128

+ nd = __TM_nesting_depth(&local_tdb);

25129

+ if (nd != 0)

25130

+ {

25131

+ return 1;

25132

+ }

25133

+ local_tdb.nesting_depth = 7;

25134

+ nd = __TM_nesting_depth(&local_tdb);

25135

+ if (nd != 7)

25136

+ {

25137

+ return 7;

25138

+ }

25139

+ local_tdb.format = 0;

25140

+ nd = __TM_nesting_depth(&local_tdb);

25141

+ if (nd != 0)

25142

+ {

25143

+ return 2;

25144

+ }

25145

+ }

25146

+ counters.c1 = 0;

25147

+ counters.c1 = 0;

25148

+ counters.c2 = 0;

25149

+ counters.c3 = 0;

25150

+ if ((rc = __TM_simple_begin()) == 0)

25151

+ {

25152

+ counters.c1 = __TM_nesting_depth(0);

25153

+ if (__TM_simple_begin() == 0)

25154

+ {

25155

+ counters.c2 = __TM_nesting_depth(0);

25156

+ if (__TM_simple_begin() == 0)

25157

+ {

25158

+ counters.c3 = __TM_nesting_depth(0);

25159

+ __TM_end();

25160

+ }

25161

+ __TM_end();

25162

+ }

25163

+ __TM_end();

25164

+ }

25165

+ else

25166

+ {

25167

+ return 100 * rc + 1;

25168

+ }

25169

+ if (counters.c1 != 1)

25170

+ {

25171

+ return 100 * counters.c1 + 2;

25172

+ }

25173

+ if (counters.c2 != 2)

25174

+ {

25175

+ return 100 * counters.c2 + 3;

25176

+ }

25177

+ if (counters.c3 != 3)

25178

+ {

25179

+ return 100 * counters.c3 + 4;

25180

+ }

25181

+

25182

+ return 0;

25183

+}

25184

+

25185

+/* ---------------------------- local testing framework functions ---------- */

25186

+

25187

+static int run_one_test(const test_table_entry_t *test_entry)

25188

+{

25189

+ int do_print_passes;

25190

+ int succeeded;

25191

+ int rc;

25192

+ int i;

25193

+

25194

+ do_print_passes = (

25195

+ test_entry->required_quorum != 1 ||

25196

+ test_entry->max_repetitions != 1);

25197

+ printf("RRR RUN %s\n", test_entry->name);

25198

+ if (do_print_passes == 1)

25199

+ {

25200

+ printf(

25201

+ " (requires %d successful out of %d runs)\n",

25202

+ test_entry->required_quorum,

25203

+ test_entry->max_repetitions);

25204

+ }

25205

+ succeeded = 0;

25206

+ rc = 0;

25207

+ for (rc = 0, i = 0; i < test_entry->max_repetitions; i++)

25208

+ {

25209

+ if (do_print_passes == 1)

25210

+ {

25211

+ if (i == 0)

25212

+ {

25213

+ printf(" ");

25214

+ }

25215

+ else

25216

+ {

25217

+ printf(",");

25218

+ }

25219

+ }

25220

+ rc = test_entry->test_func();

25221

+ if (rc == 0)

25222

+ {

25223

+ if (do_print_passes == 1)

25224

+ {

25225

+ printf(" success");

25226

+ }

25227

+ succeeded++;

25228

+ if (succeeded >= test_entry->required_quorum)

25229

+ {

25230

+ break;

25231

+ }

25232

+ }

25233

+ else

25234

+ {

25235

+ printf(" failed (rc = %d)", rc);

25236

+ }

25237

+ }

25238

+ if (do_print_passes == 1 || rc != 0)

25239

+ {

25240

+ printf("\n");

25241

+ }

25242

+ if (succeeded >= test_entry->required_quorum)

25243

+ {

25244

+ printf("+++ OK %s\n", test_entry->name);

25245

+

25246

+ return 0;

25247

+ }

25248

+ else

25249

+ {

25250

+ printf("--- FAIL %s\n", test_entry->name);

25251

+

25252

+ return (rc != 0) ? rc : -1;

25253

+ }

25254

+}

25255

+

25256

+static int run_all_tests(const test_table_entry_t *test_table)

25257

+{

25258

+ const test_table_entry_t *test;

25259

+ int rc;

25260

+

25261

+ for (

25262

+ rc = 0, test = &test_table[0];

25263

+ test->test_func != NULL && rc == 0; test++)

25264

+ {

25265

+ rc = run_one_test(test);

25266

+ }

25267

+

25268

+ return rc;

25269

+}

25270

+

25271

+/* ---------------------------- interface functions ------------------------ */

25272

+

25273

+int main(void)

25274

+{

25275

+ const test_table_entry_t test_table[] = {

25276

+ TEST_NO_REP(init_cache),

25277

+ TEST_NO_REP(test_abort_classification),

25278

+ TEST_NO_REP(test_cc_classification),

25279

+ TEST_DF_REP(test_tbegin_ntstg_tend),

25280

+ TEST_DF_REP(test_tbegin_ntstg_tabort),

25281

+ TEST_DF_REP(test_tbegin_aborts),

25282

+ TEST_DF_REP(test_tbegin_tdb),

25283

+ TEST_DF_REP(test_etnd),

25284

+ { (void *)0, 0, 0 }

25285

+ };

25286

+

25287

+ {

25288

+ int rc;

25289

+

25290

+ rc = run_all_tests(test_table);

25291

+

25292

+ return rc;

25293

+ }

25294

+}

25295

Index: gcc/testsuite/gcc.target/s390/hotpatch-8.c

25296

===================================================================

25297

--- a/src/gcc/testsuite/gcc.target/s390/hotpatch-8.c (.../tags/gcc_4_8_2_release)

25298

+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-8.c (.../branches/gcc-4_8-branch)

25299

@@ -0,0 +1,28 @@

25300

+/* Functional tests for the function hotpatching feature. */

25301

+

25302

+/* { dg-do run } */

25303

+/* { dg-options "-O3 -mzarch -mhotpatch --save-temps" } */

25304

+

25305

+#include <stdio.h>

25306

+

25307

+__attribute__ ((hotpatch))

25308

+inline void hp1(void)

25309

+{

25310

+ printf("hello, world!\n");

25311

+}

25312

+

25313

+__attribute__ ((hotpatch))

25314

+__attribute__ ((always_inline))

25315

+void hp2(void) /* { dg-warning "always_inline function might not be inlinable" } */

25316

+{

25317

+ printf("hello, world!\n");

25318

+} /* { dg-warning "function 'hp2' with the 'always_inline' attribute is not hotpatchable" } */

25319

+

25320

+int main (void)

25321

+{

25322

+ return 0;

25323

+}

25324

+

25325

+/* Check number of occurences of certain instructions. */

25326

+/* { dg-final { scan-assembler-not "nopr\t%r7" } } */

25327

+/* { dg-final { scan-assembler-not "nop\t0" } } */

25328

Index: gcc/testsuite/gcc.target/s390/hotpatch-9.c

25329

===================================================================

25330

--- a/src/gcc/testsuite/gcc.target/s390/hotpatch-9.c (.../tags/gcc_4_8_2_release)

25331

+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-9.c (.../branches/gcc-4_8-branch)

25332

@@ -0,0 +1,21 @@

25333

+/* Functional tests for the function hotpatching feature. */

25334

+

25335

+/* { dg-do run } */

25336

+/* { dg-options "-O3 -mzarch -mhotpatch=1 --save-temps" } */

25337

+

25338

+#include <stdio.h>

25339

+

25340

+__attribute__ ((hotpatch(2)))

25341

+void hp1(void)

25342

+{

25343

+ printf("hello, world!\n");

25344

+}

25345

+

25346

+int main (void)

25347

+{

25348

+ return 0;

25349

+}

25350

+

25351

+/* Check number of occurences of certain instructions. */

25352

+/* { dg-final { scan-assembler-times "nopr\t%r7" 2 } } */

25353

+/* { dg-final { scan-assembler-times "nop\t0" 1 } } */

25354

Index: gcc/testsuite/gcc.target/s390/hotpatch-10.c

25355

===================================================================

25356

--- a/src/gcc/testsuite/gcc.target/s390/hotpatch-10.c (.../tags/gcc_4_8_2_release)

25357

+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-10.c (.../branches/gcc-4_8-branch)

25358

@@ -0,0 +1,21 @@

25359

+/* Functional tests for the function hotpatching feature. */

25360

+

25361

+/* { dg-do run } */

25362

+/* { dg-options "-O3 -mzarch -mno-hotpatch --save-temps" } */

25363

+

25364

+#include <stdio.h>

25365

+

25366

+__attribute__ ((hotpatch(2)))

25367

+void hp1(void)

25368

+{

25369

+ printf("hello, world!\n");

25370

+}

25371

+

25372

+int main (void)

25373

+{

25374

+ return 0;

25375

+}

25376

+

25377

+/* Check number of occurences of certain instructions. */

25378

+/* { dg-final { scan-assembler-times "nopr\t%r7" 2 } } */

25379

+/* { dg-final { scan-assembler-times "nop\t0" 1 } } */

25380

Index: gcc/testsuite/gcc.target/s390/hotpatch-11.c

25381

===================================================================

25382

--- a/src/gcc/testsuite/gcc.target/s390/hotpatch-11.c (.../tags/gcc_4_8_2_release)

25383

+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-11.c (.../branches/gcc-4_8-branch)

25384

@@ -0,0 +1,20 @@

25385

+/* Functional tests for the function hotpatching feature. */

25386

+

25387

+/* { dg-do run } */

25388

+/* { dg-options "-O3 -mzarch -mhotpatch -mno-hotpatch --save-temps" } */

25389

+

25390

+#include <stdio.h>

25391

+

25392

+void hp1(void)

25393

+{

25394

+ printf("hello, world!\n");

25395

+}

25396

+

25397

+int main (void)

25398

+{

25399

+ return 0;

25400

+}

25401

+

25402

+/* Check number of occurences of certain instructions. */

25403

+/* { dg-final { scan-assembler-not "nopr\t%r7" } } */

25404

+/* { dg-final { scan-assembler-not "nop\t0" } } */

25405

Index: gcc/testsuite/gcc.target/s390/hotpatch-12.c

25406

===================================================================

25407

--- a/src/gcc/testsuite/gcc.target/s390/hotpatch-12.c (.../tags/gcc_4_8_2_release)

25408

+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-12.c (.../branches/gcc-4_8-branch)

25409

@@ -0,0 +1,20 @@

25410

+/* Functional tests for the function hotpatching feature. */

25411

+

25412

+/* { dg-do run } */

25413

+/* { dg-options "-O3 -mzarch -mno-hotpatch -mhotpatch=1 --save-temps" } */

25414

+

25415

+#include <stdio.h>

25416

+

25417

+void hp1(void)

25418

+{

25419

+ printf("hello, world!\n");

25420

+}

25421

+

25422

+int main (void)

25423

+{

25424

+ return 0;

25425

+}

25426

+

25427

+/* Check number of occurences of certain instructions. */

25428

+/* { dg-final { scan-assembler-times "nopr\t%r7" 1 } } */

25429

+/* { dg-final { scan-assembler-times "nop\t0" 1 } } */

25430

Index: gcc/testsuite/gcc.target/mips/bswap-1.c

25431

===================================================================

25432

--- a/src/gcc/testsuite/gcc.target/mips/bswap-1.c (.../tags/gcc_4_8_2_release)

25433

+++ b/src/gcc/testsuite/gcc.target/mips/bswap-1.c (.../branches/gcc-4_8-branch)

25434

@@ -0,0 +1,10 @@

25435

+/* { dg-options "isa_rev>=2" } */

25436

+/* { dg-skip-if "bswap recognition needs expensive optimizations" { *-*-* } { "-O0" "-O1" } { "" } } */

25437

+

25438

+NOMIPS16 unsigned short

25439

+foo (unsigned short x)

25440

+{

25441

+ return ((x << 8) & 0xff00) | ((x >> 8) & 0xff);

25442

+}

25443

+

25444

+/* { dg-final { scan-assembler "\twsbh\t" } } */

25445

Index: gcc/testsuite/gcc.target/mips/bswap-2.c

25446

===================================================================

25447

--- a/src/gcc/testsuite/gcc.target/mips/bswap-2.c (.../tags/gcc_4_8_2_release)

25448

+++ b/src/gcc/testsuite/gcc.target/mips/bswap-2.c (.../branches/gcc-4_8-branch)

25449

@@ -0,0 +1,9 @@

25450

+/* { dg-options "isa_rev>=2" } */

25451

+

25452

+NOMIPS16 unsigned short

25453

+foo (unsigned short x)

25454

+{

25455

+ return __builtin_bswap16 (x);

25456

+}

25457

+

25458

+/* { dg-final { scan-assembler "\twsbh\t" } } */

25459

Index: gcc/testsuite/gcc.target/mips/pr59137.c

25460

===================================================================

25461

--- a/src/gcc/testsuite/gcc.target/mips/pr59137.c (.../tags/gcc_4_8_2_release)

25462

+++ b/src/gcc/testsuite/gcc.target/mips/pr59137.c (.../branches/gcc-4_8-branch)

25463

@@ -0,0 +1,34 @@

25464

+/* { dg-do run } */

25465

+/* { dg-options "-mno-plt" } */

25466

+

25467

+extern void abort (void);

25468

+

25469

+struct lispstruct

25470

+{

25471

+ int e;

25472

+ int t;

25473

+};

25474

+

25475

+struct lispstruct Cnil_body;

25476

+struct lispstruct Ct_body;

25477

+int nvalues;

25478

+

25479

+struct lispstruct * __attribute__ ((noinline))

25480

+fLlistp (struct lispstruct *x0)

25481

+{

25482

+ if (x0 == &Cnil_body

25483

+ || (((unsigned long) x0 >= 0x80000000) ? 0

25484

+ : (!x0->e ? (x0 != &Cnil_body) : x0->t)))

25485

+ x0 = &Ct_body;

25486

+ else

25487

+ x0 = &Cnil_body;

25488

+ nvalues = 1;

25489

+ return x0;

25490

+}

25491

+

25492

+int main ()

25493

+{

25494

+ if (fLlistp ((struct lispstruct *) 0xa0000001) != &Cnil_body)

25495

+ abort ();

25496

+ return 0;

25497

+}

25498

Index: gcc/testsuite/gcc.target/mips/bswap-3.c

25499

===================================================================

25500

--- a/src/gcc/testsuite/gcc.target/mips/bswap-3.c (.../tags/gcc_4_8_2_release)

25501

+++ b/src/gcc/testsuite/gcc.target/mips/bswap-3.c (.../branches/gcc-4_8-branch)

25502

@@ -0,0 +1,14 @@

25503

+/* { dg-options "isa_rev>=2" } */

25504

+/* { dg-skip-if "bswap recognition needs expensive optimizations" { *-*-* } { "-O0" "-O1" } { "" } } */

25505

+

25506

+NOMIPS16 unsigned int

25507

+foo (unsigned int x)

25508

+{

25509

+ return (((x << 24) & 0xff000000)

25510

+ | ((x << 8) & 0xff0000)

25511

+ | ((x >> 8) & 0xff00)

25512

+ | ((x >> 24) & 0xff));

25513

+}

25514

+

25515

+/* { dg-final { scan-assembler "\twsbh\t" } } */

25516

+/* { dg-final { scan-assembler "\tror\t" } } */

25517

Index: gcc/testsuite/gcc.target/mips/bswap-4.c

25518

===================================================================

25519

--- a/src/gcc/testsuite/gcc.target/mips/bswap-4.c (.../tags/gcc_4_8_2_release)

25520

+++ b/src/gcc/testsuite/gcc.target/mips/bswap-4.c (.../branches/gcc-4_8-branch)

25521

@@ -0,0 +1,10 @@

25522

+/* { dg-options "isa_rev>=2" } */

25523

+

25524

+NOMIPS16 unsigned int

25525

+foo (unsigned int x)

25526

+{

25527

+ return __builtin_bswap32 (x);

25528

+}

25529

+

25530

+/* { dg-final { scan-assembler "\twsbh\t" } } */

25531

+/* { dg-final { scan-assembler "\tror\t" } } */

25532

Index: gcc/testsuite/gcc.target/mips/bswap-5.c

25533

===================================================================

25534

--- a/src/gcc/testsuite/gcc.target/mips/bswap-5.c (.../tags/gcc_4_8_2_release)

25535

+++ b/src/gcc/testsuite/gcc.target/mips/bswap-5.c (.../branches/gcc-4_8-branch)

25536

@@ -0,0 +1,20 @@

25537

+/* { dg-options "isa_rev>=2 -mgp64" } */

25538

+/* { dg-skip-if "bswap recognition needs expensive optimizations" { *-*-* } { "-O0" "-O1" } { "" } } */

25539

+

25540

+typedef unsigned long long uint64_t;

25541

+

25542

+NOMIPS16 uint64_t

25543

+foo (uint64_t x)

25544

+{

25545

+ return (((x << 56) & 0xff00000000000000ull)

25546

+ | ((x << 40) & 0xff000000000000ull)

25547

+ | ((x << 24) & 0xff0000000000ull)

25548

+ | ((x << 8) & 0xff00000000ull)

25549

+ | ((x >> 8) & 0xff000000)

25550

+ | ((x >> 24) & 0xff0000)

25551

+ | ((x >> 40) & 0xff00)

25552

+ | ((x >> 56) & 0xff));

25553

+}

25554

+

25555

+/* { dg-final { scan-assembler "\tdsbh\t" } } */

25556

+/* { dg-final { scan-assembler "\tdshd\t" } } */

25557

Index: gcc/testsuite/gcc.target/mips/bswap-6.c

25558

===================================================================

25559

--- a/src/gcc/testsuite/gcc.target/mips/bswap-6.c (.../tags/gcc_4_8_2_release)

25560

+++ b/src/gcc/testsuite/gcc.target/mips/bswap-6.c (.../branches/gcc-4_8-branch)

25561

@@ -0,0 +1,12 @@

25562

+/* { dg-options "isa_rev>=2 -mgp64" } */

25563

+

25564

+typedef unsigned long long uint64_t;

25565

+

25566

+NOMIPS16 uint64_t

25567

+foo (uint64_t x)

25568

+{

25569

+ return __builtin_bswap64 (x);

25570

+}

25571

+

25572

+/* { dg-final { scan-assembler "\tdsbh\t" } } */

25573

+/* { dg-final { scan-assembler "\tdshd\t" } } */

25574

Index: gcc/testsuite/gcc.target/sh/pr51244-19.c

25575

===================================================================

25576

--- a/src/gcc/testsuite/gcc.target/sh/pr51244-19.c (.../tags/gcc_4_8_2_release)

25577

+++ b/src/gcc/testsuite/gcc.target/sh/pr51244-19.c (.../branches/gcc-4_8-branch)

25578

@@ -22,11 +22,16 @@

25579

unwanted sequences. Thus, if we see any movt insns, something is not

25580

working as expected. This test requires -O2 because the T bit stores

25581

in question will be eliminated in additional insn split passes after

25582

- reload. */

25583

+ reload.

25584

+

25585

+ Notice: When this test case was initially added, the T bit optimization

25586

+ was buggy and this test case resulted in wrong code. The movt

25587

+ instructions actually have to be present in this case to get

25588

+ correct code. */

25589

/* { dg-do compile { target "sh*-*-*" } } */

25590

/* { dg-options "-O2" } */

25591

/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */

25592

-/* { dg-final { scan-assembler-not "movt" } } */

25593

+/* { dg-final { scan-assembler "movt" } } */

25594

25595

struct request

25596

{

25597

Index: gcc/testsuite/gcc.target/sh/pr54089-3.c

25598

===================================================================

25599

--- a/src/gcc/testsuite/gcc.target/sh/pr54089-3.c (.../tags/gcc_4_8_2_release)

25600

+++ b/src/gcc/testsuite/gcc.target/sh/pr54089-3.c (.../branches/gcc-4_8-branch)

25601

@@ -5,7 +5,7 @@

25602

/* { dg-options "-O1" } */

25603

/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m1*" "-m2" "-m2e*" } } */

25604

/* { dg-final { scan-assembler-not "and" } } */

25605

-/* { dg-final { scan-assembler-not "31" } } */

25606

+/* { dg-final { scan-assembler-not "#31" } } */

25607

25608

int

25609

test00 (unsigned int a, int* b, int c, int* d, unsigned int e)

25610

Index: gcc/testsuite/go.test/go-test.exp

25611

===================================================================

25612

--- a/src/gcc/testsuite/go.test/go-test.exp (.../tags/gcc_4_8_2_release)

25613

+++ b/src/gcc/testsuite/go.test/go-test.exp (.../branches/gcc-4_8-branch)

25614

@@ -333,17 +333,16 @@

25615

}

25616

25617

if { ( [file tail $test] == "select2.go" \

25618

- || [file tail $test] == "stack.go" ) \

25619

+ || [file tail $test] == "stack.go" \

25620

+ || [file tail $test] == "peano.go" ) \

25621

&& ! [check_effective_target_split_stack] } {

25622

- # chan/select2.go fails on targets without split stack,

25623

- # because they allocate a large stack segment that blows

25624

- # out the memory calculations.

25625

+ # These tests fails on targets without split stack.

25626

untested $name

25627

continue

25628

}

25629

25630

- if { [file tail $test] == "rotate.go" } {

25631

- # This test produces a temporary file that takes too long

25632

+ if [string match "*go.test/test/rotate\[0123\].go" $test] {

25633

+ # These tests produces a temporary file that takes too long

25634

# to compile--5 minutes on my laptop without optimization.

25635

# When compiling without optimization it tests nothing

25636

# useful, since the point of the test is to see whether

25637

Index: gcc/testsuite/lib/target-supports.exp

25638

===================================================================

25639

--- a/src/gcc/testsuite/lib/target-supports.exp (.../tags/gcc_4_8_2_release)

25640

+++ b/src/gcc/testsuite/lib/target-supports.exp (.../branches/gcc-4_8-branch)

25641

@@ -1311,6 +1311,32 @@

25642

return 0

25643

}

25644

25645

+# Return 1 if the target supports executing power8 vector instructions, 0

25646

+# otherwise. Cache the result.

25647

+

25648

+proc check_p8vector_hw_available { } {

25649

+ return [check_cached_effective_target p8vector_hw_available {

25650

+ # Some simulators are known to not support VSX/power8 instructions.

25651

+ # For now, disable on Darwin

25652

+ if { [istarget powerpc-*-eabi] || [istarget powerpc*-*-eabispe] || [istarget *-*-darwin*]} {

25653

+ expr 0

25654

+ } else {

25655

+ set options "-mpower8-vector"

25656

+ check_runtime_nocache p8vector_hw_available {

25657

+ int main()

25658

+ {

25659

+ #ifdef __MACH__

25660

+ asm volatile ("xxlorc vs0,vs0,vs0");

25661

+ #else

25662

+ asm volatile ("xxlorc 0,0,0");

25663

+ #endif

25664

+ return 0;

25665

+ }

25666

+ } $options

25667

+ }

25668

+ }]

25669

+}

25670

+

25671

# Return 1 if the target supports executing VSX instructions, 0

25672

# otherwise. Cache the result.

25673

25674

@@ -2672,6 +2698,33 @@

25675

}

25676

}

25677

25678

+# Return 1 if this is a PowerPC target supporting -mpower8-vector

25679

+

25680

+proc check_effective_target_powerpc_p8vector_ok { } {

25681

+ if { ([istarget powerpc*-*-*]

25682

+ && ![istarget powerpc-*-linux*paired*])

25683

+ || [istarget rs6000-*-*] } {

25684

+ # AltiVec is not supported on AIX before 5.3.

25685

+ if { [istarget powerpc*-*-aix4*]

25686

+ || [istarget powerpc*-*-aix5.1*]

25687

+ || [istarget powerpc*-*-aix5.2*] } {

25688

+ return 0

25689

+ }

25690

+ return [check_no_compiler_messages powerpc_p8vector_ok object {

25691

+ int main (void) {

25692

+#ifdef __MACH__

25693

+ asm volatile ("xxlorc vs0,vs0,vs0");

25694

+#else

25695

+ asm volatile ("xxlorc 0,0,0");

25696

+#endif

25697

+ return 0;

25698

+ }

25699

+ } "-mpower8-vector"]

25700

+ } else {

25701

+ return 0

25702

+ }

25703

+}

25704

+

25705

# Return 1 if this is a PowerPC target supporting -mvsx

25706

25707

proc check_effective_target_powerpc_vsx_ok { } {

25708

@@ -2699,6 +2752,27 @@

25709

}

25710

}

25711

25712

+# Return 1 if this is a PowerPC target supporting -mhtm

25713

+

25714

+proc check_effective_target_powerpc_htm_ok { } {

25715

+ if { ([istarget powerpc*-*-*]

25716

+ && ![istarget powerpc-*-linux*paired*])

25717

+ || [istarget rs6000-*-*] } {

25718

+ # HTM is not supported on AIX yet.

25719

+ if { [istarget powerpc*-*-aix*] } {

25720

+ return 0

25721

+ }

25722

+ return [check_no_compiler_messages powerpc_htm_ok object {

25723

+ int main (void) {

25724

+ asm volatile ("tbegin. 0");

25725

+ return 0;

25726

+ }

25727

+ } "-mhtm"]

25728

+ } else {

25729

+ return 0

25730

+ }

25731

+}

25732

+

25733

# Return 1 if this is a PowerPC target supporting -mcpu=cell.

25734

25735

proc check_effective_target_powerpc_ppu_ok { } {

25736

@@ -2794,6 +2868,22 @@

25737

}

25738

}

25739

25740

+# Return 1 if this is a PowerPC target using the ELFv2 ABI.

25741

+

25742

+proc check_effective_target_powerpc_elfv2 { } {

25743

+ if { [istarget powerpc*-*-*] } {

25744

+ return [check_no_compiler_messages powerpc_elfv2 object {

25745

+ #if _CALL_ELF != 2

25746

+ #error not ELF v2 ABI

25747

+ #else

25748

+ int dummy;

25749

+ #endif

25750

+ }]

25751

+ } else {

25752

+ return 0

25753

+ }

25754

+}

25755

+

25756

# Return 1 if this is a SPU target with a toolchain that

25757

# supports automatic overlay generation.

25758

25759

@@ -4499,6 +4589,7 @@

25760

switch $arg {

25761

"vmx_hw" { set selected [check_vmx_hw_available] }

25762

"vsx_hw" { set selected [check_vsx_hw_available] }

25763

+ "p8vector_hw" { set selected [check_p8vector_hw_available] }

25764

"ppc_recip_hw" { set selected [check_ppc_recip_hw_available] }

25765

"named_sections" { set selected [check_named_sections_available] }

25766

"gc_sections" { set selected [check_gc_sections_available] }

25767

@@ -4520,6 +4611,7 @@

25768

switch $arg {

25769

"vmx_hw" { return 1 }

25770

"vsx_hw" { return 1 }

25771

+ "p8vector_hw" { return 1 }

25772

"ppc_recip_hw" { return 1 }

25773

"named_sections" { return 1 }

25774

"gc_sections" { return 1 }

25775

@@ -5077,7 +5169,9 @@

25776

}

25777

25778

lappend DEFAULT_VECTCFLAGS "-maltivec"

25779

- if [check_vsx_hw_available] {

25780

+ if [check_p8vector_hw_available] {

25781

+ lappend DEFAULT_VECTCFLAGS "-mpower8-vector" "-mno-allow-movmisalign"

25782

+ } elseif [check_vsx_hw_available] {

25783

lappend DEFAULT_VECTCFLAGS "-mvsx" "-mno-allow-movmisalign"

25784

}

25785

25786

Index: gcc/testsuite/gfortran.dg/shape_8.f90

25787

===================================================================

25788

--- a/src/gcc/testsuite/gfortran.dg/shape_8.f90 (.../tags/gcc_4_8_2_release)

25789

+++ b/src/gcc/testsuite/gfortran.dg/shape_8.f90 (.../branches/gcc-4_8-branch)

25790

@@ -0,0 +1,10 @@

25791

+! { dg-do compile }

25792

+!

25793

+! PR 60450: [4.7/4.8 Regression] ICE with SHAPE intrinsic

25794

+!

25795

+! Contributed by Dave Allured <dave.allured@noaa.gov>

25796

+

25797

+ real, allocatable :: x(:,:)

25798

+ allocate (x(3,2), source=99.)

25799

+ print *, shape (x / 10.0)

25800

+end

25801

Index: gcc/testsuite/gfortran.dg/proc_ptr_comp_38.f90

25802

===================================================================

25803

--- a/src/gcc/testsuite/gfortran.dg/proc_ptr_comp_38.f90 (.../tags/gcc_4_8_2_release)

25804

+++ b/src/gcc/testsuite/gfortran.dg/proc_ptr_comp_38.f90 (.../branches/gcc-4_8-branch)

25805

@@ -0,0 +1,12 @@

25806

+! { dg-do compile }

25807

+!

25808

+! PR fortran/58803

25809

+!

25810

+! Contributed by Vittorio Zecca

25811

+!

25812

+! Was before ICEing due to a double free

25813

+!

25814

+ type t

25815

+ procedure(real), pointer, nopass :: f1, f2

25816

+ end type

25817

+ end

25818

Index: gcc/testsuite/gfortran.dg/where_4.f90

25819

===================================================================

25820

--- a/src/gcc/testsuite/gfortran.dg/where_4.f90 (.../tags/gcc_4_8_2_release)

25821

+++ b/src/gcc/testsuite/gfortran.dg/where_4.f90 (.../branches/gcc-4_8-branch)

25822

@@ -0,0 +1,18 @@

25823

+! { dg-do compile }

25824

+! PR 60522 - this used to ICE.

25825

+! Original test case Roger Ferrer Ibanez

25826

+subroutine foo(a, b)

25827

+ implicit none

25828

+ integer, dimension(:), intent(inout) :: a

25829

+ integer, dimension(:), intent(in) :: b

25830

+

25831

+ where (b(:) > 0)

25832

+ where (b(:) > 100)

25833

+ a(lbound(a, 1):ubound(a, 1)) = b(lbound(b, 1):ubound(b, 1)) * b(lbound(b, 1):ubound(b, 1)) - 100

25834

+ elsewhere

25835

+ a(lbound(a, 1):ubound(a, 1)) = b(lbound(b, 1):ubound(b, 1)) * b(lbound(b, 1):ubound(b, 1))

25836

+ end where

25837

+ elsewhere

25838

+ a(lbound(a, 1):ubound(a, 1)) = - b(lbound(b, 1):ubound(b, 1)) * b(lbound(b, 1):ubound(b, 1))

25839

+ end where

25840

+end subroutine foo

25841

Index: gcc/testsuite/gfortran.dg/gomp/pr59467.f90

25842

===================================================================

25843

--- a/src/gcc/testsuite/gfortran.dg/gomp/pr59467.f90 (.../tags/gcc_4_8_2_release)

25844

+++ b/src/gcc/testsuite/gfortran.dg/gomp/pr59467.f90 (.../branches/gcc-4_8-branch)

25845

@@ -0,0 +1,24 @@

25846

+! PR libgomp/59467

25847

+! { dg-do compile }

25848

+! { dg-options "-fopenmp" }

25849

+ FUNCTION t()

25850

+ INTEGER :: a, b, t

25851

+ a = 0

25852

+ b = 0

25853

+ !$OMP PARALLEL REDUCTION(+:b)

25854

+ !$OMP SINGLE ! { dg-error "is not threadprivate or private in outer context" }

25855

+ !$OMP ATOMIC WRITE

25856

+ a = 6

25857

+ !$OMP END SINGLE COPYPRIVATE (a)

25858

+ b = a

25859

+ !$OMP END PARALLEL

25860

+ t = b

25861

+ b = 0

25862

+ !$OMP PARALLEL REDUCTION(+:b)

25863

+ !$OMP SINGLE

25864

+ !$OMP ATOMIC WRITE

25865

+ b = 6

25866

+ !$OMP END SINGLE COPYPRIVATE (b)

25867

+ !$OMP END PARALLEL

25868

+ t = t + b

25869

+ END FUNCTION

25870

Index: gcc/testsuite/gfortran.dg/allocate_class_3.f90

25871

===================================================================

25872

--- a/src/gcc/testsuite/gfortran.dg/allocate_class_3.f90 (.../tags/gcc_4_8_2_release)

25873

+++ b/src/gcc/testsuite/gfortran.dg/allocate_class_3.f90 (.../branches/gcc-4_8-branch)

25874

@@ -0,0 +1,107 @@

25875

+! { dg-do run }

25876

+! Tests the fix for PR59414, comment #3, in which the allocate

25877

+! expressions were not correctly being stripped to provide the

25878

+! vpointer as an lhs to the pointer assignment of the vptr from

25879

+! the SOURCE expression.

25880

+!

25881

+! Contributed by Antony Lewis <antony@cosmologist.info>

25882

+!

25883

+module ObjectLists

25884

+ implicit none

25885

+

25886

+ type :: t

25887

+ integer :: i

25888

+ end type

25889

+

25890

+ type Object_array_pointer

25891

+ class(t), pointer :: p(:)

25892

+ end type

25893

+

25894

+contains

25895

+

25896

+ subroutine AddArray1 (P, Pt)

25897

+ class(t) :: P(:)

25898

+ class(Object_array_pointer) :: Pt

25899

+

25900

+ select type (Pt)

25901

+ class is (Object_array_pointer)

25902

+ if (associated (Pt%P)) deallocate (Pt%P)

25903

+ allocate(Pt%P(1:SIZE(P)), source=P)

25904

+ end select

25905

+ end subroutine

25906

+

25907

+ subroutine AddArray2 (P, Pt)

25908

+ class(t) :: P(:)

25909

+ class(Object_array_pointer) :: Pt

25910

+

25911

+ select type (Pt)

25912

+ type is (Object_array_pointer)

25913

+ if (associated (Pt%P)) deallocate (Pt%P)

25914

+ allocate(Pt%P(1:SIZE(P)), source=P)

25915

+ end select

25916

+ end subroutine

25917

+

25918

+ subroutine AddArray3 (P, Pt)

25919

+ class(t) :: P

25920

+ class(Object_array_pointer) :: Pt

25921

+

25922

+ select type (Pt)

25923

+ class is (Object_array_pointer)

25924

+ if (associated (Pt%P)) deallocate (Pt%P)

25925

+ allocate(Pt%P(1:4), source=P)

25926

+ end select

25927

+ end subroutine

25928

+

25929

+ subroutine AddArray4 (P, Pt)

25930

+ type(t) :: P(:)

25931

+ class(Object_array_pointer) :: Pt

25932

+

25933

+ select type (Pt)

25934

+ class is (Object_array_pointer)

25935

+ if (associated (Pt%P)) deallocate (Pt%P)

25936

+ allocate(Pt%P(1:SIZE(P)), source=P)

25937

+ end select

25938

+ end subroutine

25939

+end module

25940

+

25941

+ use ObjectLists

25942

+ type(Object_array_pointer), pointer :: Pt

25943

+ class(t), pointer :: P(:)

25944

+

25945

+ allocate (P(2), source = [t(1),t(2)])

25946

+ allocate (Pt, source = Object_array_pointer(NULL()))

25947

+ call AddArray1 (P, Pt)

25948

+ select type (x => Pt%p)

25949

+ type is (t)

25950

+ if (any (x%i .ne. [1,2])) call abort

25951

+ end select

25952

+ deallocate (P)

25953

+ deallocate (pt)

25954

+

25955

+ allocate (P(3), source = [t(3),t(4),t(5)])

25956

+ allocate (Pt, source = Object_array_pointer(NULL()))

25957

+ call AddArray2 (P, Pt)

25958

+ select type (x => Pt%p)

25959

+ type is (t)

25960

+ if (any (x%i .ne. [3,4,5])) call abort

25961

+ end select

25962

+ deallocate (P)

25963

+ deallocate (pt)

25964

+

25965

+ allocate (Pt, source = Object_array_pointer(NULL()))

25966

+ call AddArray3 (t(6), Pt)

25967

+ select type (x => Pt%p)

25968

+ type is (t)

25969

+ if (any (x%i .ne. [6,6,6,6])) call abort

25970

+ end select

25971

+ deallocate (pt)

25972

+

25973

+ allocate (Pt, source = Object_array_pointer(NULL()))

25974

+ call AddArray4 ([t(7), t(8)], Pt)

25975

+ select type (x => Pt%p)

25976

+ type is (t)

25977

+ if (any (x%i .ne. [7,8])) call abort

25978

+ end select

25979

+ deallocate (pt)

25980

+ end

25981

+

25982

Index: gcc/testsuite/gfortran.dg/reshape_6.f90

25983

===================================================================

25984

--- a/src/gcc/testsuite/gfortran.dg/reshape_6.f90 (.../tags/gcc_4_8_2_release)

25985

+++ b/src/gcc/testsuite/gfortran.dg/reshape_6.f90 (.../branches/gcc-4_8-branch)

25986

@@ -0,0 +1,19 @@

25987

+! { dg-do compile }

25988

+! PR fortran/58989

25989

+!

25990

+program test

25991

+

25992

+ real(8), dimension(4,4) :: fluxes

25993

+ real(8), dimension(2,2,2,2) :: f

25994

+ integer, dimension(3) :: dmmy

25995

+ integer, parameter :: indx(4)=(/2,2,2,2/)

25996

+

25997

+ fluxes = 1

25998

+

25999

+ dmmy = (/2,2,2/)

26000

+

26001

+ f = reshape(fluxes,(/dmmy,2/)) ! Caused an ICE

26002

+ f = reshape(fluxes,(/2,2,2,2/)) ! Works as expected

26003

+ f = reshape(fluxes,indx) ! Works as expected

26004

+

26005

+end program test

26006

Index: gcc/testsuite/gfortran.dg/unresolved_fixup_2.f90

26007

===================================================================

26008

--- a/src/gcc/testsuite/gfortran.dg/unresolved_fixup_2.f90 (.../tags/gcc_4_8_2_release)

26009

+++ b/src/gcc/testsuite/gfortran.dg/unresolved_fixup_2.f90 (.../branches/gcc-4_8-branch)

26010

@@ -0,0 +1,36 @@

26011

+! { dg-do compile }

26012

+!

26013

+! PR fortran/58007

26014

+! Unresolved fiixup while loading a module.

26015

+!

26016

+! This tests that the specification expression A%MAX_DEGREE in module BSR is

26017

+! correctly loaded and resolved in program MAIN.

26018

+!

26019

+! Original testcase from Daniel Shapiro <shapero@uw.edu>

26020

+

26021

+module matrix

26022

+ type :: sparse_matrix

26023

+ integer :: max_degree

26024

+ end type

26025

+end module

26026

+

26027

+module bsr

26028

+ use matrix

26029

+

26030

+ type, extends(sparse_matrix) :: bsr_matrix

26031

+ end type

26032

+

26033

+ integer :: i1

26034

+ integer :: i2

26035

+ integer :: i3

26036

+contains

26037

+ function get_neighbors (A)

26038

+ type(bsr_matrix), intent(in) :: A

26039

+ integer :: get_neighbors(A%max_degree)

26040

+ end function

26041

+end module

26042

+

26043

+program main

26044

+ use matrix

26045

+ use bsr

26046

+end

26047

Index: gcc/testsuite/gfortran.dg/init_flag_12.f90

26048

===================================================================

26049

--- a/src/gcc/testsuite/gfortran.dg/init_flag_12.f90 (.../tags/gcc_4_8_2_release)

26050

+++ b/src/gcc/testsuite/gfortran.dg/init_flag_12.f90 (.../branches/gcc-4_8-branch)

26051

@@ -0,0 +1,13 @@

26052

+! { dg-do compile }

26053

+! { dg-options "-fno-automatic -finit-local-zero" }

26054

+!

26055

+! PR 55907: [4.7/4.8/4.9 Regression] ICE with -fno-automatic -finit-local-zero

26056

+!

26057

+! Contributed by J.R. Garcia <garcia.espinosa.jr@gmail.com>

26058

+

26059

+subroutine cchaine (i)

26060

+ implicit none

26061

+ integer :: i

26062

+ character(len=i) :: chaine

26063

+ write(*,*) chaine

26064

+end subroutine

26065

Index: gcc/testsuite/gfortran.dg/derived_external_function_1.f90

26066

===================================================================

26067

--- a/src/gcc/testsuite/gfortran.dg/derived_external_function_1.f90 (.../tags/gcc_4_8_2_release)

26068

+++ b/src/gcc/testsuite/gfortran.dg/derived_external_function_1.f90 (.../branches/gcc-4_8-branch)

26069

@@ -0,0 +1,27 @@

26070

+! { dg-do run }

26071

+!

26072

+! PR fortran/58771

26073

+!

26074

+! Contributed by Vittorio Secca <zeccav@gmail.com>

26075

+!

26076

+! ICEd on the write statement with f() because the derived type backend

26077

+! declaration not built.

26078

+!

26079

+module m

26080

+ type t

26081

+ integer(4) g

26082

+ end type

26083

+end

26084

+

26085

+type(t) function f() result(ff)

26086

+ use m

26087

+ ff%g = 42

26088

+end

26089

+

26090

+ use m

26091

+ character (20) :: line1, line2

26092

+ type(t) f

26093

+ write (line1, *) f()

26094

+ write (line2, *) 42_4

26095

+ if (line1 .ne. line2) call abort

26096

+end

26097

Index: gcc/testsuite/gfortran.dg/implicit_pure_4.f90

26098

===================================================================

26099

--- a/src/gcc/testsuite/gfortran.dg/implicit_pure_4.f90 (.../tags/gcc_4_8_2_release)

26100

+++ b/src/gcc/testsuite/gfortran.dg/implicit_pure_4.f90 (.../branches/gcc-4_8-branch)

26101

@@ -0,0 +1,22 @@

26102

+! { dg-do compile }

26103

+!

26104

+! PR fortran/60543

26105

+! PR fortran/60283

26106

+!

26107

+module m

26108

+contains

26109

+ REAL(8) FUNCTION random()

26110

+ CALL RANDOM_NUMBER(random)

26111

+ END FUNCTION random

26112

+ REAL(8) FUNCTION random2()

26113

+ block

26114

+ block

26115

+ block

26116

+ CALL RANDOM_NUMBER(random2)

26117

+ end block

26118

+ end block

26119

+ end block

26120

+ END FUNCTION random2

26121

+end module m

26122

+

26123

+! { dg-final { scan-module-absence "m" "IMPLICIT_PURE" } }

26124

Index: gcc/testsuite/gfortran.dg/null_6.f90

26125

===================================================================

26126

--- a/src/gcc/testsuite/gfortran.dg/null_6.f90 (.../tags/gcc_4_8_2_release)

26127

+++ b/src/gcc/testsuite/gfortran.dg/null_6.f90 (.../branches/gcc-4_8-branch)

26128

@@ -30,5 +30,5 @@

26129

26130

subroutine test_PR34547_3 ()

26131

integer, allocatable :: i(:)

26132

- print *, NULL(i)

26133

+ print *, NULL(i) ! { dg-error "Invalid context for NULL" }

26134

end subroutine test_PR34547_3

26135

Index: gcc/testsuite/gfortran.dg/fmt_en.f90

26136

===================================================================

26137

--- a/src/gcc/testsuite/gfortran.dg/fmt_en.f90 (.../tags/gcc_4_8_2_release)

26138

+++ b/src/gcc/testsuite/gfortran.dg/fmt_en.f90 (.../branches/gcc-4_8-branch)

26139

@@ -0,0 +1,186 @@

26140

+! { dg-do run { target fd_truncate } }

26141

+! PR60128 Invalid outputs with EN descriptors

26142

+! Test case provided by Walt Brainerd.

26143

+program pr60128

26144

+use ISO_FORTRAN_ENV

26145

+ implicit none

26146

+ integer, parameter :: j(size(real_kinds)+4)=[REAL_KINDS, [4, 4, 4, 4]]

26147

+ logical :: l_skip(4) = .false.

26148

+ integer :: i

26149

+ integer :: n_tst = 0, n_cnt = 0, n_skip = 0

26150

+ character(len=20) :: s, s1

26151

+

26152

+ open (unit = 10, file = 'fmt_en.res')

26153

+! Check that the default rounding mode is to nearest and to even on tie.

26154

+ do i=1,size(real_kinds)

26155

+ if (i == 1) then

26156

+ write(s, '(2F4.1,2F4.0)') real(-9.49999905,kind=j(1)), &

26157

+ real(9.49999905,kind=j(1)), &

26158

+ real(9.5,kind=j(1)), real(8.5,kind=j(1))

26159

+ write(s1, '(3PE10.3,2PE10.3)') real(987350.,kind=j(1)), &

26160

+ real(98765.0,kind=j(1))

26161

+ else if (i == 2) then

26162

+ write(s, '(2F4.1,2F4.0)') real(-9.49999905,kind=j(2)), &

26163

+ real(9.49999905,kind=j(2)), &

26164

+ real(9.5,kind=j(2)), real(8.5,kind=j(2))

26165

+ write(s1, '(3PE10.3,2PE10.3)') real(987350.,kind=j(2)), &

26166

+ real(98765.0,kind=j(2))

26167

+ else if (i == 3) then

26168

+ write(s, '(2F4.1,2F4.0)') real(-9.49999905,kind=j(3)), &

26169

+ real(9.49999905,kind=j(3)), &

26170

+ real(9.5,kind=j(3)), real(8.5,kind=j(3))

26171

+ write(s1, '(3PE10.3,2PE10.3)') real(987350.,kind=j(3)), &

26172

+ real(98765.0,kind=j(3))

26173

+ else if (i == 4) then

26174

+ write(s, '(2F4.1,2F4.0)') real(-9.49999905,kind=j(4)), &

26175

+ real(9.49999905,kind=j(4)), &

26176

+ real(9.5,kind=j(4)), real(8.5,kind=j(4))

26177

+ write(s1, '(3PE10.3,2PE10.3)') real(987350.,kind=j(4)), &

26178

+ real(98765.0,kind=j(4))

26179

+ end if

26180

+ if (s /= '-9.5 9.5 10. 8.' .or. s1 /= ' 987.4E+03 98.76E+03') then

26181

+ l_skip(i) = .true.

26182

+! print "('Unsupported rounding for real(',i0,')')", j(i)

26183

+ end if

26184

+ end do

26185

+

26186

+

26187

+! Original test.

26188

+ call checkfmt("(en15.2)", -.44444, " -444.44E-03")

26189

+

26190

+! Test for the bug in comment 6.

26191

+ call checkfmt("(en15.0)", 1.0, " 1.E+00")

26192

+ call checkfmt("(en15.0)", 1.00000012, " 1.E+00")

26193

+ call checkfmt("(en15.0)", 0.99999994, " 1.E+00")

26194

+ call checkfmt("(en15.0)", 10.0, " 10.E+00")

26195

+ call checkfmt("(en15.0)", 10.0000010, " 10.E+00")

26196

+ call checkfmt("(en15.0)", 9.99999905, " 10.E+00")

26197

+ call checkfmt("(en15.0)", 100.0, " 100.E+00")

26198

+ call checkfmt("(en15.0)", 100.000008, " 100.E+00")

26199

+ call checkfmt("(en15.0)", 99.9999924, " 100.E+00")

26200

+ call checkfmt("(en15.0)", 1000.0, " 1.E+03")

26201

+ call checkfmt("(en15.0)", 1000.00006, " 1.E+03")

26202

+ call checkfmt("(en15.0)", 999.999939, " 1.E+03")

26203

+ call checkfmt("(en15.0)", 9.5, " 10.E+00")

26204

+ call checkfmt("(en15.0)", 9.50000095, " 10.E+00")

26205

+ call checkfmt("(en15.0)", 9.49999905, " 9.E+00")

26206

+ call checkfmt("(en15.0)", 99.5, " 100.E+00")

26207

+ call checkfmt("(en15.0)", 99.5000076, " 100.E+00")

26208

+ call checkfmt("(en15.0)", 99.4999924, " 99.E+00")

26209

+ call checkfmt("(en15.0)", 999.5, " 1.E+03")

26210

+ call checkfmt("(en15.0)", 999.500061, " 1.E+03")

26211

+ call checkfmt("(en15.0)", 999.499939, " 999.E+00")

26212

+ call checkfmt("(en15.0)", 9500.0, " 10.E+03")

26213

+ call checkfmt("(en15.0)", 9500.00098, " 10.E+03")

26214

+ call checkfmt("(en15.0)", 9499.99902, " 9.E+03")

26215

+ call checkfmt("(en15.1)", 9950.0, " 10.0E+03")

26216

+ call checkfmt("(en15.2)", 9995.0, " 10.00E+03")

26217

+ call checkfmt("(en15.3)", 9999.5, " 10.000E+03")

26218

+ call checkfmt("(en15.1)", 9.5, " 9.5E+00")

26219

+ call checkfmt("(en15.1)", 9.50000095, " 9.5E+00")

26220

+ call checkfmt("(en15.1)", 9.49999905, " 9.5E+00")

26221

+ call checkfmt("(en15.1)", 0.099951, " 100.0E-03")

26222

+ call checkfmt("(en15.1)", 0.009951, " 10.0E-03")

26223

+ call checkfmt("(en15.1)", 0.000999951," 1.0E-03")

26224

+

26225

+ call checkfmt("(en15.0)", -1.0, " -1.E+00")

26226

+ call checkfmt("(en15.0)", -1.00000012, " -1.E+00")

26227

+ call checkfmt("(en15.0)", -0.99999994, " -1.E+00")

26228

+ call checkfmt("(en15.0)", -10.0, " -10.E+00")

26229

+ call checkfmt("(en15.0)", -10.0000010, " -10.E+00")

26230

+ call checkfmt("(en15.0)", -9.99999905, " -10.E+00")

26231

+ call checkfmt("(en15.0)", -100.0, " -100.E+00")

26232

+ call checkfmt("(en15.0)", -100.000008, " -100.E+00")

26233

+ call checkfmt("(en15.0)", -99.9999924, " -100.E+00")

26234

+ call checkfmt("(en15.0)", -1000.0, " -1.E+03")

26235

+ call checkfmt("(en15.0)", -1000.00006, " -1.E+03")

26236

+ call checkfmt("(en15.0)", -999.999939, " -1.E+03")

26237

+ call checkfmt("(en15.0)", -9.5, " -10.E+00")

26238

+ call checkfmt("(en15.0)", -9.50000095, " -10.E+00")

26239

+ call checkfmt("(en15.0)", -9.49999905, " -9.E+00")

26240

+ call checkfmt("(en15.0)", -99.5, " -100.E+00")

26241

+ call checkfmt("(en15.0)", -99.5000076, " -100.E+00")

26242

+ call checkfmt("(en15.0)", -99.4999924, " -99.E+00")

26243

+ call checkfmt("(en15.0)", -999.5, " -1.E+03")

26244

+ call checkfmt("(en15.0)", -999.500061, " -1.E+03")

26245

+ call checkfmt("(en15.0)", -999.499939, " -999.E+00")

26246

+ call checkfmt("(en15.0)", -9500.0, " -10.E+03")

26247

+ call checkfmt("(en15.0)", -9500.00098, " -10.E+03")

26248

+ call checkfmt("(en15.0)", -9499.99902, " -9.E+03")

26249

+ call checkfmt("(en15.1)", -9950.0, " -10.0E+03")

26250

+ call checkfmt("(en15.2)", -9995.0, " -10.00E+03")

26251

+ call checkfmt("(en15.3)", -9999.5, " -10.000E+03")

26252

+ call checkfmt("(en15.1)", -9.5, " -9.5E+00")

26253

+ call checkfmt("(en15.1)", -9.50000095, " -9.5E+00")

26254

+ call checkfmt("(en15.1)", -9.49999905, " -9.5E+00")

26255

+ call checkfmt("(en15.1)", -0.099951, " -100.0E-03")

26256

+ call checkfmt("(en15.1)", -0.009951, " -10.0E-03")

26257

+ call checkfmt("(en15.1)", -0.000999951," -1.0E-03")

26258

+

26259

+ call checkfmt("(en15.1)", 987350., " 987.4E+03")

26260

+ call checkfmt("(en15.2)", 98735., " 98.74E+03")

26261

+ call checkfmt("(en15.3)", 9873.5, " 9.874E+03")

26262

+ call checkfmt("(en15.1)", 987650., " 987.6E+03")

26263

+ call checkfmt("(en15.2)", 98765., " 98.76E+03")

26264

+ call checkfmt("(en15.3)", 9876.5, " 9.876E+03")

26265

+ call checkfmt("(en15.1)", 3.125E-02, " 31.2E-03")

26266

+ call checkfmt("(en15.1)", 9.375E-02, " 93.8E-03")

26267

+ call checkfmt("(en15.2)", 1.5625E-02, " 15.62E-03")

26268

+ call checkfmt("(en15.2)", 4.6875E-02, " 46.88E-03")

26269

+ call checkfmt("(en15.3)", 7.8125E-03, " 7.812E-03")

26270

+ call checkfmt("(en15.3)", 2.34375E-02, " 23.438E-03")

26271

+ call checkfmt("(en15.3)", 9.765625E-04," 976.562E-06")

26272

+ call checkfmt("(en15.6)", 2.9296875E-03," 2.929688E-03")

26273

+

26274

+ call checkfmt("(en15.1)", -987350., " -987.4E+03")

26275

+ call checkfmt("(en15.2)", -98735., " -98.74E+03")

26276

+ call checkfmt("(en15.3)", -9873.5, " -9.874E+03")

26277

+ call checkfmt("(en15.1)", -987650., " -987.6E+03")

26278

+ call checkfmt("(en15.2)", -98765., " -98.76E+03")

26279

+ call checkfmt("(en15.3)", -9876.5, " -9.876E+03")

26280

+ call checkfmt("(en15.1)", -3.125E-02, " -31.2E-03")

26281

+ call checkfmt("(en15.1)", -9.375E-02, " -93.8E-03")

26282

+ call checkfmt("(en15.2)", -1.5625E-02, " -15.62E-03")

26283

+ call checkfmt("(en15.2)", -4.6875E-02, " -46.88E-03")

26284

+ call checkfmt("(en15.3)", -7.8125E-03, " -7.812E-03")

26285

+ call checkfmt("(en15.3)", -2.34375E-02, " -23.438E-03")

26286

+ call checkfmt("(en15.3)", -9.765625E-04," -976.562E-06")

26287

+ call checkfmt("(en15.6)", -2.9296875E-03," -2.929688E-03")

26288

+

26289

+ ! print *, n_tst, n_cnt, n_skip

26290

+ if (n_cnt /= 0) call abort

26291

+ if (all(.not. l_skip)) write (10, *) "All kinds rounded to nearest"

26292

+ close (10)

26293

+

26294

+contains

26295

+ subroutine checkfmt(fmt, x, cmp)

26296

+ implicit none

26297

+ integer :: i

26298

+ character(len=*), intent(in) :: fmt

26299

+ real, intent(in) :: x

26300

+ character(len=*), intent(in) :: cmp

26301

+ do i=1,size(real_kinds)

26302

+ if (i == 1) then

26303

+ write(s, fmt) real(x,kind=j(1))

26304

+ else if (i == 2) then

26305

+ write(s, fmt) real(x,kind=j(2))

26306

+ else if (i == 3) then

26307

+ write(s, fmt) real(x,kind=j(3))

26308

+ else if (i == 4) then

26309

+ write(s, fmt) real(x,kind=j(4))

26310

+ end if

26311

+ n_tst = n_tst + 1

26312

+ if (s /= cmp) then

26313

+ if (l_skip(i)) then

26314

+ n_skip = n_skip + 1

26315

+ else

26316

+ print "(a,1x,a,' expected: ',1x,a)", fmt, s, cmp

26317

+ n_cnt = n_cnt + 1

26318

+ end if

26319

+ end if

26320

+ end do

26321

+

26322

+ end subroutine

26323

+end program

26324

+! { dg-final { scan-file fmt_en.res "All kinds rounded to nearest" { xfail { i?86-*-solaris2.9* hppa*-*-hpux* } } } }

26325

+! { dg-final { cleanup-saved-temps } }

26326

Index: gcc/testsuite/gfortran.dg/constructor_9.f90

26327

===================================================================

26328

--- a/src/gcc/testsuite/gfortran.dg/constructor_9.f90 (.../tags/gcc_4_8_2_release)

26329

+++ b/src/gcc/testsuite/gfortran.dg/constructor_9.f90 (.../branches/gcc-4_8-branch)

26330

@@ -0,0 +1,22 @@

26331

+! { dg-do compile }

26332

+! { dg-options "-Wall" }

26333

+!

26334

+! PR 58471: [4.8/4.9 Regression] ICE on invalid with missing type constructor and -Wall

26335

+!

26336

+! Contributed by Andrew Benson <abensonca@gmail.com>

26337

+

26338

+module cf

26339

+ implicit none

26340

+ type :: cfmde

26341

+ end type

26342

+ interface cfmde

26343

+ module procedure mdedc ! { dg-error "is neither function nor subroutine" }

26344

+ end interface

26345

+contains

26346

+ subroutine cfi()

26347

+ type(cfmde), pointer :: cfd

26348

+ cfd=cfmde() ! { dg-error "Can't convert" }

26349

+ end subroutine

26350

+end module

26351

+

26352

+! { dg-final { cleanup-modules "cf" } }

26353

Index: gcc/testsuite/gfortran.dg/round_3.f08

26354

===================================================================

26355

--- a/src/gcc/testsuite/gfortran.dg/round_3.f08 (.../tags/gcc_4_8_2_release)

26356

+++ b/src/gcc/testsuite/gfortran.dg/round_3.f08 (.../branches/gcc-4_8-branch)

26357

@@ -16,19 +16,44 @@

26358

call checkfmt("(RU,1P,G6.0E2)", 2.0, "2.E+00")

26359

call checkfmt("(RU,1P,G10.4E2)", 2.3456e5, "2.3456E+05")

26360

26361

- call checkfmt("(RU,F2.0)", 0.09, "1.") ! 0.

26362

+ call checkfmt("(RC,G10.2)", 99.5, " 0.10E+03") ! pr59774

26363

+ call checkfmt("(RC,G10.2)", 995., " 0.10E+04") ! pr59774

26364

+ call checkfmt("(RC,G10.3)", 999.5, " 0.100E+04") ! pr59774

26365

+ call checkfmt("(RC,G10.3)", 9995., " 0.100E+05") ! pr59774

26366

+ call checkfmt("(RU,G10.2)", .099, " 0.10 ") ! pr59774

26367

+ call checkfmt("(RC,G10.1)", .095, " 0.1 ") ! pr59774

26368

+ call checkfmt("(RU,G10.3)", .0999, " 0.100 ") ! pr59774

26369

+ call checkfmt("(RC,G10.2)", .0995, " 0.10 ") ! pr59774

26370

+

26371

+ call checkfmt("(RU,G9.3)", 891.1, " 892.") ! pr59836

26372

+ call checkfmt("(RD,G9.3)", -891.1, "-892.") ! pr59836

26373

+

26374

+ call checkfmt("(RU,F6.4)", 0.00006, "0.0001")! 0.

26375

+ call checkfmt("(RU,F5.3)", 0.0007, "0.001") ! 0.

26376

+ call checkfmt("(RU,F4.2)", 0.008, "0.01") ! 0.

26377

+ call checkfmt("(RU,F3.1)", 0.09, "0.1") ! 0.

26378

+

26379

+ call checkfmt("(RU,F2.0)", 0.09, "1.") ! 0.

26380

call checkfmt("(RD,F3.0)", -0.09, "-1.") ! -0.

26381

- call checkfmt("(RU,F2.0)", 2.0, "2.") ! 3.

26382

- call checkfmt("(RD,F3.0)", -2.0, "-2.") ! -3.

26383

- call checkfmt("(RU,F6.4)", 2.0, "2.0000") ! 2.0001

26384

- call checkfmt("(RD,F7.4)", -2.0, "-2.0000") ! -2.0001

26385

- call checkfmt("(RU,1P,E6.0E2)", 2.0, "2.E+00") ! 3.E+00

26386

+ call checkfmt("(RU,F2.0)", 0.9, "1.") ! pr59836

26387

+ call checkfmt("(RC,F2.0)", 0.4, "0.") ! pr59836

26388

+ call checkfmt("(RC,F2.0)", 0.5, "1.") ! pr59836

26389

+ call checkfmt("(RC,F2.0)", 0.6, "1.") ! pr59836

26390

+ call checkfmt("(RD,F3.0)", -0.9, "-1.") ! pr59836

26391

+ call checkfmt("(RC,F3.0)", -0.4, "-0.") ! pr59836

26392

+ call checkfmt("(RC,F3.0)", -0.5, "-1.") ! pr59836

26393

+ call checkfmt("(RC,F3.0)", -0.6, "-1.") ! pr59836

26394

+ call checkfmt("(RU,F2.0)", 2.0, "2.") ! 3.

26395

+ call checkfmt("(RD,F3.0)", -2.0, "-2.") ! -3.

26396

+ call checkfmt("(RU,F6.4)", 2.0, "2.0000") ! 2.0001

26397

+ call checkfmt("(RD,F7.4)", -2.0, "-2.0000") ! -2.0001

26398

+ call checkfmt("(RU,1P,E6.0E2)", 2.0, "2.E+00") ! 3.E+00

26399

call checkfmt("(RD,1P,E7.0E2)", -2.0, "-2.E+00") ! -3.E+00

26400

- call checkfmt("(RU,1P,E7.1E2)", 2.5, "2.5E+00") ! 2.6E+00

26401

+ call checkfmt("(RU,1P,E7.1E2)", 2.5, "2.5E+00") ! 2.6E+00

26402

call checkfmt("(RD,1P,E8.1E2)", -2.5, "-2.5E+00") ! -2.6E+00

26403

call checkfmt("(RU,1P,E10.4E2)", 2.5, "2.5000E+00") ! 2.5001E+00

26404

call checkfmt("(RD,1P,E11.4E2)", -2.5, "-2.5000E+00") ! -2.5001E+00

26405

- call checkfmt("(RU,1P,G6.0E2)", 2.0, "2.E+00") ! 3.E+00

26406

+ call checkfmt("(RU,1P,G6.0E2)", 2.0, "2.E+00") ! 3.E+00

26407

call checkfmt("(RD,1P,G7.0E2)", -2.0, "-2.E+00") ! -3.E+00

26408

call checkfmt("(RU,1P,G10.4E2)", 2.3456e5, "2.3456E+05") ! 2.3457E+05

26409

call checkfmt("(RD,1P,G11.4E2)", -2.3456e5, "-2.3456E+05") ! -2.3457E+05

26410

Index: gcc/testsuite/gfortran.dg/default_initialization_7.f90

26411

===================================================================

26412

--- a/src/gcc/testsuite/gfortran.dg/default_initialization_7.f90 (.../tags/gcc_4_8_2_release)

26413

+++ b/src/gcc/testsuite/gfortran.dg/default_initialization_7.f90 (.../branches/gcc-4_8-branch)

26414

@@ -0,0 +1,22 @@

26415

+! { dg-do compile }

26416

+!

26417

+! PR fortran/57033

26418

+! ICE on a structure constructor of an extended derived type whose parent

26419

+! type last component has a default initializer

26420

+!

26421

+! Contributed by Tilo Schwarz <tilo@tilo-schwarz.de>

26422

+

26423

+program ice

26424

+

26425

+type m

26426

+ integer i

26427

+ logical :: f = .false.

26428

+end type m

26429

+

26430

+type, extends(m) :: me

26431

+end type me

26432

+

26433

+type(me) meo

26434

+

26435

+meo = me(1) ! ICE

26436

+end program ice

26437

Index: gcc/testsuite/gfortran.dg/proc_ptr_46.f90

26438

===================================================================

26439

--- a/src/gcc/testsuite/gfortran.dg/proc_ptr_46.f90 (.../tags/gcc_4_8_2_release)

26440

+++ b/src/gcc/testsuite/gfortran.dg/proc_ptr_46.f90 (.../branches/gcc-4_8-branch)

26441

@@ -0,0 +1,14 @@

26442

+! { dg-do compile }

26443

+!

26444

+! PR fortran/49397

26445

+!

26446

+! Invalid per IR F08/0060 and F2008Corr2, C729

26447

+!

26448

+

26449

+! Print *,f() ! << Valid when uncommented

26450

+Contains

26451

+ Subroutine s

26452

+ Procedure(Real),Pointer :: p

26453

+ p => f ! { dg-error "Procedure pointer target 'f' at .1. must be either an intrinsic, host or use associated, referenced or have the EXTERNAL attribute" }

26454

+ End Subroutine

26455

+End

26456

Index: gcc/testsuite/gfortran.dg/pr52370.f90

26457

===================================================================

26458

--- a/src/gcc/testsuite/gfortran.dg/pr52370.f90 (.../tags/gcc_4_8_2_release)

26459

+++ b/src/gcc/testsuite/gfortran.dg/pr52370.f90 (.../branches/gcc-4_8-branch)

26460

@@ -0,0 +1,21 @@

26461

+! PR fortran/52370

26462

+! { dg-do compile }

26463

+! { dg-options "-O1 -Wall" }

26464

+

26465

+module pr52370

26466

+contains

26467

+ subroutine foo(a,b)

26468

+ real, intent(out) :: a

26469

+ real, dimension(:), optional, intent(out) :: b

26470

+ a=0.5

26471

+ if (present(b)) then

26472

+ b=1.0

26473

+ end if

26474

+ end subroutine foo

26475

+end module pr52370

26476

+

26477

+program prg52370

26478

+ use pr52370

26479

+ real :: a

26480

+ call foo(a)

26481

+end program prg52370

26482

Index: gcc/testsuite/gfortran.dg/graphite/pr59817.f

26483

===================================================================

26484

--- a/src/gcc/testsuite/gfortran.dg/graphite/pr59817.f (.../tags/gcc_4_8_2_release)

26485

+++ b/src/gcc/testsuite/gfortran.dg/graphite/pr59817.f (.../branches/gcc-4_8-branch)

26486

@@ -0,0 +1,14 @@

26487

+! { dg-do compile }

26488

+! { dg-options "-O2 -floop-interchange" }

26489

+ SUBROUTINE PREPD(ICAST,ICAS,ICASX,ICAS1,ICAS2,NDET,NM,III,IMP,

26490

+ * CASMIN)

26491

+ LOGICAL CASMIN

26492

+ DIMENSION ICAST(NDET,NM),IMP(NM)

26493

+ IF(CASMIN) THEN

26494

+ DO K=1,NDET

26495

+ DO L=1,NM

26496

+ IF(L.EQ.K-1) ICAST(K,L) = 1

26497

+ END DO

26498

+ END DO

26499

+ END IF

26500

+ END SUBROUTINE

26501

Index: gcc/testsuite/gfortran.dg/str_comp_optimize_1.f90

26502

===================================================================

26503

--- a/src/gcc/testsuite/gfortran.dg/str_comp_optimize_1.f90 (.../tags/gcc_4_8_2_release)

26504

+++ b/src/gcc/testsuite/gfortran.dg/str_comp_optimize_1.f90 (.../branches/gcc-4_8-branch)

26505

@@ -0,0 +1,22 @@

26506

+! { dg-do compile }

26507

+! { dg-options "-ffrontend-optimize" }

26508

+!

26509

+! PR fortran/60341

26510

+! An unguarded union access was wrongly enabling a frontend optimization on a

26511

+! string comparison, leading to an ICE.

26512

+!

26513

+! Original testcase from Steve Chapel <steve.chapel@a2pg.com>.

26514

+! Reduced by Steven G. Kargl <kargl@gcc.gnu.org>.

26515

+!

26516

+

26517

+ subroutine modelg(ncm)

26518

+ implicit none

26519

+ integer, parameter :: pc = 30, pm = pc - 1

26520

+ integer i

26521

+ character*4 catt(pm,2)

26522

+ integer ncm,iatt(pm,pc)

26523

+ do i=1,ncm

26524

+ if (catt(i,1)//catt(i,2).eq.'central') exit

26525

+ end do

26526

+ iatt(i,4)=1

26527

+ end

26528

Index: gcc/testsuite/gfortran.dg/list_read_12.f90

26529

===================================================================

26530

--- a/src/gcc/testsuite/gfortran.dg/list_read_12.f90 (.../tags/gcc_4_8_2_release)

26531

+++ b/src/gcc/testsuite/gfortran.dg/list_read_12.f90 (.../branches/gcc-4_8-branch)

26532

@@ -0,0 +1,11 @@

26533

+! { dg-do run }

26534

+! PR58324 Bogus end of file condition

26535

+integer :: i, ios

26536

+open(99, access='stream', form='unformatted')

26537

+write(99) "5 a"

26538

+close(99)

26539

+

26540

+open(99, access='sequential', form='formatted')

26541

+read(99, *, iostat=ios) i

26542

+if (ios /= 0) call abort

26543

+end

26544

Index: gcc/testsuite/gfortran.dg/generic_28.f90

26545

===================================================================

26546

--- a/src/gcc/testsuite/gfortran.dg/generic_28.f90 (.../tags/gcc_4_8_2_release)

26547

+++ b/src/gcc/testsuite/gfortran.dg/generic_28.f90 (.../branches/gcc-4_8-branch)

26548

@@ -0,0 +1,18 @@

26549

+! { dg-do compile }

26550

+!

26551

+! PR 58998: [4.8/4.9 Regression] Generic interface problem with gfortran

26552

+!

26553

+! Contributed by Paul van Delst

26554

+

26555

+ interface iargc

26556

+ procedure iargc_8

26557

+ end interface

26558

+

26559

+contains

26560

+

26561

+ integer(8) function iargc_8()

26562

+ integer(4) iargc

26563

+ iargc_8 = iargc()

26564

+ end function

26565

+

26566

+end

26567

Index: gcc/testsuite/gfortran.dg/unresolved_fixup_1.f90

26568

===================================================================

26569

--- a/src/gcc/testsuite/gfortran.dg/unresolved_fixup_1.f90 (.../tags/gcc_4_8_2_release)

26570

+++ b/src/gcc/testsuite/gfortran.dg/unresolved_fixup_1.f90 (.../branches/gcc-4_8-branch)

26571

@@ -0,0 +1,44 @@

26572

+! { dg-do compile }

26573

+!

26574

+! PR fortran/58007

26575

+! Unresolved fixup while loading a module.

26576

+!

26577

+! This tests that the specification expression A%MAX_DEGREE in module BSR is

26578

+! correctly loaded and resolved in program MAIN.

26579

+!

26580

+! Original testcase from Daniel Shapiro <shapero@uw.edu>

26581

+! Reduced by Tobias Burnus <burnus@net-b.de> and Janus Weil <janus@gcc.gnu.org>

26582

+

26583

+module matrix

26584

+ type :: sparse_matrix

26585

+ integer :: max_degree

26586

+ end type

26587

+contains

26588

+ subroutine init_interface (A)

26589

+ class(sparse_matrix), intent(in) :: A

26590

+ end subroutine

26591

+ real function get_value_interface()

26592

+ end function

26593

+end module

26594

+

26595

+module ellpack

26596

+ use matrix

26597

+end module

26598

+

26599

+module bsr

26600

+ use matrix

26601

+ type, extends(sparse_matrix) :: bsr_matrix

26602

+ contains

26603

+ procedure :: get_neighbors

26604

+ end type

26605

+contains

26606

+ function get_neighbors (A)

26607

+ class(bsr_matrix), intent(in) :: A

26608

+ integer :: get_neighbors(A%max_degree)

26609

+ end function

26610

+end module

26611

+

26612

+program main

26613

+ use ellpack

26614

+ use bsr

26615

+end

26616

Index: gcc/testsuite/gfortran.dg/lto/pr60635_1.c

26617

===================================================================

26618

--- a/src/gcc/testsuite/gfortran.dg/lto/pr60635_1.c (.../tags/gcc_4_8_2_release)

26619

+++ b/src/gcc/testsuite/gfortran.dg/lto/pr60635_1.c (.../branches/gcc-4_8-branch)

26620

@@ -0,0 +1,14 @@

26621

+#include <stdint.h>

26622

+#include <stdbool.h>

26623

+

26624

+static bool littleendian=true;

26625

+

26626

+uint16_t bigendc16(union{uint16_t * n;uint8_t* b;}x){

26627

+

26628

+ if (!littleendian) return *x.n;

26629

+

26630

+ uint16_t res = ((uint16_t)(x.b[1])<<0) |

26631

+ ((uint16_t)(x.b[0])<<8);

26632

+ return res;

26633

+}

26634

+

26635

Index: gcc/testsuite/gfortran.dg/lto/pr60635_0.f90

26636

===================================================================

26637

--- a/src/gcc/testsuite/gfortran.dg/lto/pr60635_0.f90 (.../tags/gcc_4_8_2_release)

26638

+++ b/src/gcc/testsuite/gfortran.dg/lto/pr60635_0.f90 (.../branches/gcc-4_8-branch)

26639

@@ -0,0 +1,16 @@

26640

+! { dg-lto-do link }

26641

+program test

26642

+ use iso_fortran_env

26643

+

26644

+ interface

26645

+ integer(int16) function bigendc16(x) bind(C)

26646

+ import

26647

+ integer(int16), intent(in) :: x

26648

+ end function

26649

+ end interface

26650

+

26651

+ integer(int16) :: x16 = 12345

26652

+ x16 = bigendc16(x16)

26653

+ print *,x16

26654

+end program

26655

+

26656

Index: gcc/testsuite/gfortran.dg/arrayio_13.f90

26657

===================================================================

26658

--- a/src/gcc/testsuite/gfortran.dg/arrayio_13.f90 (.../tags/gcc_4_8_2_release)

26659

+++ b/src/gcc/testsuite/gfortran.dg/arrayio_13.f90 (.../branches/gcc-4_8-branch)

26660

@@ -0,0 +1,14 @@

26661

+! { dg-do run }

26662

+! PR60810 Bogus end-of-file

26663

+program readstrlist

26664

+ character(len=80), dimension(2) :: ver

26665

+ integer :: a, b, c

26666

+ a = 1

26667

+ b = 2

26668

+ c = 3

26669

+ ver(1) = '285 383'

26670

+ ver(2) = '985'

26671

+ read( ver, *) a, b, c

26672

+ if (a /= 285 .or. b /= 383 .or. c /= 985) call abort

26673

+ !write ( *, *) a, b, c

26674

+end

26675

Index: gcc/testsuite/gfortran.dg/null_5.f90

26676

===================================================================

26677

--- a/src/gcc/testsuite/gfortran.dg/null_5.f90 (.../tags/gcc_4_8_2_release)

26678

+++ b/src/gcc/testsuite/gfortran.dg/null_5.f90 (.../branches/gcc-4_8-branch)

26679

@@ -34,7 +34,7 @@

26680

end subroutine test_PR34547_1

26681

26682

subroutine test_PR34547_2 ()

26683

- print *, null () ! { dg-error "in data transfer statement requires MOLD" }

26684

+ print *, null () ! { dg-error "Invalid context" }

26685

end subroutine test_PR34547_2

26686

26687

subroutine test_PR34547_3 ()

26688

Index: gcc/testsuite/gfortran.dg/proc_ptr_43.f90

26689

===================================================================

26690

--- a/src/gcc/testsuite/gfortran.dg/proc_ptr_43.f90 (.../tags/gcc_4_8_2_release)

26691

+++ b/src/gcc/testsuite/gfortran.dg/proc_ptr_43.f90 (.../branches/gcc-4_8-branch)

26692

@@ -0,0 +1,19 @@

26693

+! { dg-do compile }

26694

+!

26695

+! PR 58099: [4.8/4.9 Regression] [F03] over-zealous procedure-pointer error checking

26696

+!

26697

+! Contributed by Daniel Price <daniel.price@monash.edu>

26698

+

26699

+ implicit none

26700

+ procedure(real), pointer :: wfunc

26701

+

26702

+ wfunc => w_cubic

26703

+

26704

+contains

26705

+

26706

+ pure real function w_cubic(q2)

26707

+ real, intent(in) :: q2

26708

+ w_cubic = 0.

26709

+ end function

26710

+

26711

+end

26712

Index: gcc/testsuite/gfortran.dg/nan_7.f90

26713

===================================================================

26714

--- a/src/gcc/testsuite/gfortran.dg/nan_7.f90 (.../tags/gcc_4_8_2_release)

26715

+++ b/src/gcc/testsuite/gfortran.dg/nan_7.f90 (.../branches/gcc-4_8-branch)

26716

@@ -2,6 +2,7 @@

26717

! { dg-options "-fno-range-check" }

26718

! { dg-require-effective-target fortran_real_16 }

26719

! { dg-require-effective-target fortran_integer_16 }

26720

+! { dg-skip-if "" { "powerpc*le-*-*" } { "*" } { "" } }

26721

! PR47293 NAN not correctly read

26722

character(len=200) :: str

26723

real(16) :: r

26724

Index: gcc/testsuite/gfortran.dg/typebound_generic_15.f90

26725

===================================================================

26726

--- a/src/gcc/testsuite/gfortran.dg/typebound_generic_15.f90 (.../tags/gcc_4_8_2_release)

26727

+++ b/src/gcc/testsuite/gfortran.dg/typebound_generic_15.f90 (.../branches/gcc-4_8-branch)

26728

@@ -0,0 +1,18 @@

26729

+! { dg-do compile }

26730

+!

26731

+! PR 60231: [4.8/4.9 Regression] ICE on undefined generic

26732

+!

26733

+! Contributed by Antony Lewis <antony@cosmologist.info>

26734

+

26735

+module Objects

26736

+

26737

+ Type TObjectList

26738

+ contains

26739

+ procedure :: Add1 ! { dg-error "must be a module procedure" }

26740

+ procedure :: Add2 ! { dg-error "must be a module procedure" }

26741

+ generic :: Add => Add1, Add2 ! { dg-error "are ambiguous" }

26742

+ end Type

26743

+

26744

+end module

26745

+

26746

+! { dg-final { cleanup-modules "Objects" } }

26747

Index: gcc/testsuite/gfortran.dg/extends_15.f90

26748

===================================================================

26749

--- a/src/gcc/testsuite/gfortran.dg/extends_15.f90 (.../tags/gcc_4_8_2_release)

26750

+++ b/src/gcc/testsuite/gfortran.dg/extends_15.f90 (.../branches/gcc-4_8-branch)

26751

@@ -0,0 +1,16 @@

26752

+! { dg-do compile }

26753

+!

26754

+! PR 58355: [4.7/4.8/4.9 Regression] [F03] ICE with TYPE, EXTENDS before parent TYPE defined

26755

+!

26756

+! Contributed by Andrew Benson <abensonca@gmail.com>

26757

+

26758

+module ct

26759

+ public :: t1

26760

+

26761

+ type, extends(t1) :: t2 ! { dg-error "has not been previously defined" }

26762

+

26763

+ type :: t1

26764

+ end type

26765

+end

26766

+

26767

+! { dg-final { cleanup-modules "ct" } }

26768

Index: gcc/testsuite/gfortran.dg/optional_class_1.f90

26769

===================================================================

26770

--- a/src/gcc/testsuite/gfortran.dg/optional_class_1.f90 (.../tags/gcc_4_8_2_release)

26771

+++ b/src/gcc/testsuite/gfortran.dg/optional_class_1.f90 (.../branches/gcc-4_8-branch)

26772

@@ -0,0 +1,45 @@

26773

+! { dg-do run }

26774

+!

26775

+! PR fortran/57445

26776

+!

26777

+! Contributed by Tobias Burnus <burnus@gcc.gnu.org>

26778

+!

26779

+! Spurious assert was added at revision 192495

26780

+!

26781

+module m

26782

+ implicit none

26783

+ type t

26784

+ integer :: i

26785

+ end type t

26786

+contains

26787

+ subroutine opt(xa, xc, xaa, xca)

26788

+ type(t), allocatable, intent(out), optional :: xa

26789

+ class(t), allocatable, intent(out), optional :: xc

26790

+ type(t), allocatable, intent(out), optional :: xaa(:)

26791

+ class(t), allocatable, intent(out), optional :: xca(:)

26792

+ if (present (xca)) call foo_opt(xca=xca)

26793

+ end subroutine opt

26794

+ subroutine foo_opt(xa, xc, xaa, xca)

26795

+ type(t), allocatable, intent(out), optional :: xa

26796

+ class(t), allocatable, intent(out), optional :: xc

26797

+ type(t), allocatable, intent(out), optional :: xaa(:)

26798

+ class(t), allocatable, intent(out), optional :: xca(:)

26799

+ if (present (xca)) then

26800

+ if (allocated (xca)) deallocate (xca)

26801

+ allocate (xca(3), source = [t(9),t(99),t(999)])

26802

+ end if

26803

+ end subroutine foo_opt

26804

+end module m

26805

+ use m

26806

+ class(t), allocatable :: xca(:)

26807

+ allocate (xca(1), source = t(42))

26808

+ select type (xca)

26809

+ type is (t)

26810

+ if (any (xca%i .ne. [42])) call abort

26811

+ end select

26812

+ call opt (xca = xca)

26813

+ select type (xca)

26814

+ type is (t)

26815

+ if (any (xca%i .ne. [9,99,999])) call abort

26816

+ end select

26817

+end

26818

Index: gcc/testsuite/gfortran.dg/dynamic_dispatch_12.f90

26819

===================================================================

26820

--- a/src/gcc/testsuite/gfortran.dg/dynamic_dispatch_12.f90 (.../tags/gcc_4_8_2_release)

26821

+++ b/src/gcc/testsuite/gfortran.dg/dynamic_dispatch_12.f90 (.../branches/gcc-4_8-branch)

26822

@@ -0,0 +1,74 @@

26823

+! { dg-do run }

26824

+!

26825

+! PR 59654: [4.8/4.9 Regression] [OOP] Broken function table with complex OO use case

26826

+!

26827

+! Contributed by Thomas Clune <Thomas.L.Clune@nasa.gov>

26828

+

26829

+module TestResult_mod

26830

+ implicit none

26831

+

26832

+ type TestResult

26833

+ integer :: numRun = 0

26834

+ contains

26835

+ procedure :: run

26836

+ procedure, nopass :: getNumRun

26837

+ end type

26838

+

26839

+contains

26840

+

26841

+ subroutine run (this)

26842

+ class (TestResult) :: this

26843

+ this%numRun = this%numRun + 1

26844

+ end subroutine

26845

+

26846

+ subroutine getNumRun()

26847

+ end subroutine

26848

+

26849

+end module

26850

+

26851

+

26852

+module BaseTestRunner_mod

26853

+ implicit none

26854

+

26855

+ type :: BaseTestRunner

26856

+ contains

26857

+ procedure, nopass :: norun

26858

+ end type

26859

+

26860

+contains

26861

+

26862

+ function norun () result(result)

26863

+ use TestResult_mod, only: TestResult

26864

+ type (TestResult) :: result

26865

+ end function

26866

+

26867

+end module

26868

+

26869

+

26870

+module TestRunner_mod

26871

+ use BaseTestRunner_mod, only: BaseTestRunner

26872

+ implicit none

26873

+end module

26874

+

26875

+

26876

+program main

26877

+ use TestRunner_mod, only: BaseTestRunner

26878

+ use TestResult_mod, only: TestResult

26879

+ implicit none

26880

+

26881

+ type (TestResult) :: result

26882

+

26883

+ call runtest (result)

26884

+

26885

+contains

26886

+

26887

+ subroutine runtest (result)

26888

+ use TestResult_mod, only: TestResult

26889

+ class (TestResult) :: result

26890

+ call result%run()

26891

+ if (result%numRun /= 1) call abort()

26892

+ end subroutine

26893

+

26894

+end

26895

+

26896

+! { dg-final { cleanup-modules "TestResult_mod BaseTestRunner_mod TestRunner_mod" } }

26897

Index: gcc/testsuite/gfortran.dg/proc_ptr_45.f90

26898

===================================================================

26899

--- a/src/gcc/testsuite/gfortran.dg/proc_ptr_45.f90 (.../tags/gcc_4_8_2_release)

26900

+++ b/src/gcc/testsuite/gfortran.dg/proc_ptr_45.f90 (.../branches/gcc-4_8-branch)

26901

@@ -0,0 +1,24 @@

26902

+! { dg-do compile }

26903

+!

26904

+! PR fortran/49397

26905

+!

26906

+! Valid per IR F08/0060 and F2008Corr2, C729

26907

+!

26908

+Program m5

26909

+ Print *,f()

26910

+Contains

26911

+ Subroutine s

26912

+ Procedure(Real),Pointer :: p

26913

+ Print *,g()

26914

+ p => f ! (1)

26915

+ Print *,p()

26916

+ p => g ! (2)

26917

+ Print *,p()

26918

+ End Subroutine

26919

+End Program

26920

+Function f()

26921

+ f = 1

26922

+End Function

26923

+Function g()

26924

+ g = 2

26925

+End Function

26926

Index: gcc/testsuite/gfortran.dg/pr59700.f90

26927

===================================================================

26928

--- a/src/gcc/testsuite/gfortran.dg/pr59700.f90 (.../tags/gcc_4_8_2_release)

26929

+++ b/src/gcc/testsuite/gfortran.dg/pr59700.f90 (.../branches/gcc-4_8-branch)

26930

@@ -0,0 +1,40 @@

26931

+! { dg-do run }

26932

+! PR59700 Test case by Steve Kargl

26933

+program foo

26934

+

26935

+ implicit none

26936

+

26937

+ character(len=80) msg

26938

+ integer, parameter :: fd = 10

26939

+ integer i1, i2, i3, i4

26940

+ real x1, x2, x3, x4

26941

+ complex c1, c2

26942

+ logical a

26943

+

26944

+ open(unit=fd, status='scratch')

26945

+ write(fd, '(A)') '1 2 3.4 q'

26946

+

26947

+ rewind(fd)

26948

+ msg = 'ok'

26949

+ read(fd, *, err=10, iomsg=msg) i1, i2, i3, i4

26950

+10 if (msg /= 'Bad integer for item 3 in list input') call abort

26951

+ rewind(fd)

26952

+ msg = 'ok'

26953

+ read(fd, *, err=20, iomsg=msg) x1, x2, x3, x4

26954

+20 if (msg /= 'Bad real number in item 4 of list input') call abort

26955

+ rewind(fd)

26956

+ msg = 'ok'

26957

+ read(fd, *, err=30, iomsg=msg) i1, x2, x1, a

26958

+30 if (msg /= 'Bad logical value while reading item 4') call abort

26959

+ rewind(fd)

26960

+ read(fd, *, err=31, iomsg=msg) i1, x2, a, x1

26961

+31 if (msg /= 'Bad repeat count in item 3 of list input') call abort

26962

+ close(fd)

26963

+ open(unit=fd, status='scratch')

26964

+ write(fd, '(A)') '(1, 2) (3.4, q)'

26965

+ rewind(fd)

26966

+ msg = 'ok'

26967

+ read(fd, *, err=40, iomsg=msg) c1, c2

26968

+40 if (msg /= 'Bad floating point number for item 2') call abort

26969

+ close(fd)

26970

+end program foo

26971

Index: gcc/testsuite/gfortran.dg/ichar_3.f90

26972

===================================================================

26973

--- a/src/gcc/testsuite/gfortran.dg/ichar_3.f90 (.../tags/gcc_4_8_2_release)

26974

+++ b/src/gcc/testsuite/gfortran.dg/ichar_3.f90 (.../branches/gcc-4_8-branch)

26975

@@ -0,0 +1,13 @@

26976

+! { dg-do compile }

26977

+!

26978

+! PR fortran/59599

26979

+! The call to ichar was triggering an ICE.

26980

+!

26981

+! Original testcase from Fran Martinez Fadrique <fmartinez@gmv.com>

26982

+

26983

+character(1) cpk(2)

26984

+integer res(2)

26985

+cpk = 'a'

26986

+res = ichar( cpk, kind=1 )

26987

+print *, ichar( cpk, kind=1 )

26988

+end

26989

Index: gcc/testsuite/gfortran.dg/unlimited_polymorphic_15.f90

26990

===================================================================

26991

--- a/src/gcc/testsuite/gfortran.dg/unlimited_polymorphic_15.f90 (.../tags/gcc_4_8_2_release)

26992

+++ b/src/gcc/testsuite/gfortran.dg/unlimited_polymorphic_15.f90 (.../branches/gcc-4_8-branch)

26993

@@ -0,0 +1,17 @@

26994

+! { dg-do compile }

26995

+!

26996

+! PR 59493: [OOP] ICE: Segfault on Class(*) pointer association

26997

+!

26998

+! Contributed by Hossein Talebi <talebi.hossein@gmail.com>

26999

+

27000

+ implicit none

27001

+

27002

+ type ty_mytype1

27003

+ end type

27004

+

27005

+ class(ty_mytype1), allocatable, target:: cla1

27006

+ class(*), pointer :: ptr

27007

+

27008

+ ptr => cla1

27009

+

27010

+end

27011

Index: gcc/testsuite/gfortran.dg/fmt_g_1.f90

27012

===================================================================

27013

--- a/src/gcc/testsuite/gfortran.dg/fmt_g_1.f90 (.../tags/gcc_4_8_2_release)

27014

+++ b/src/gcc/testsuite/gfortran.dg/fmt_g_1.f90 (.../branches/gcc-4_8-branch)

27015

@@ -0,0 +1,11 @@

27016

+! { dg-do run }

27017

+! PR59771 Cleanup handling of Gw.0 and Gw.0Ee format

27018

+! Test case prepared by Dominique d'Humieres <dominiq@lps.ens.fr>

27019

+ PROGRAM FOO

27020

+ character(len=60) :: buffer, buffer1

27021

+

27022

+ write (buffer ,'(6(1X,1PG9.0e2))') 0.0, 0.04, 0.06, 0.4, 0.6, 243.0

27023

+ write (buffer1,'(6(1X,1PE9.0e2))') 0.0, 0.04, 0.06, 0.4, 0.6, 243.0

27024

+

27025

+ if (buffer /= buffer1) call abort

27026

+ end

27027

Index: gcc/testsuite/gfortran.dg/elemental_subroutine_9.f90

27028

===================================================================

27029

--- a/src/gcc/testsuite/gfortran.dg/elemental_subroutine_9.f90 (.../tags/gcc_4_8_2_release)

27030

+++ b/src/gcc/testsuite/gfortran.dg/elemental_subroutine_9.f90 (.../branches/gcc-4_8-branch)

27031

@@ -0,0 +1,39 @@

27032

+! { dg-do run }

27033

+!

27034

+! PR fortran/59906

27035

+!

27036

+! Contributed by H Anlauf <anlauf@gmx.de>

27037

+!

27038

+! Failed generate character scalar for scalarized loop for elemantal call.

27039

+!

27040

+program x

27041

+ implicit none

27042

+ call y('bbb')

27043

+contains

27044

+

27045

+ subroutine y(str)

27046

+ character(len=*), intent(in) :: str

27047

+ character(len=len_trim(str)) :: str_aux

27048

+ character(len=3) :: str3 = 'abc'

27049

+

27050

+ str_aux = str

27051

+

27052

+ ! Compiled but did not give correct result

27053

+ if (any (str_cmp((/'aaa','bbb'/), str) .neqv. [.FALSE.,.TRUE.])) call abort

27054

+

27055

+ ! Did not compile

27056

+ if (any (str_cmp((/'bbb', 'aaa'/), str_aux) .neqv. [.TRUE.,.FALSE.])) call abort

27057

+

27058

+ ! Verify patch

27059

+ if (any (str_cmp((/'bbb', 'aaa'/), str3) .neqv. [.FALSE.,.FALSE.])) call abort

27060

+ if (any (str_cmp((/'bbb', 'aaa'/), 'aaa') .neqv. [.FALSE.,.TRUE.])) call abort

27061

+

27062

+ end subroutine y

27063

+

27064

+ elemental logical function str_cmp(str1, str2)

27065

+ character(len=*), intent(in) :: str1

27066

+ character(len=*), intent(in) :: str2

27067

+ str_cmp = (str1 == str2)

27068

+ end function str_cmp

27069

+

27070

+end program x

27071

Index: gcc/testsuite/gcc.c-torture/execute/20140212-1.c

27072

===================================================================

27073

--- a/src/gcc/testsuite/gcc.c-torture/execute/20140212-1.c (.../tags/gcc_4_8_2_release)

27074

+++ b/src/gcc/testsuite/gcc.c-torture/execute/20140212-1.c (.../branches/gcc-4_8-branch)

27075

@@ -0,0 +1,37 @@

27076

+/* PR rtl-optimization/60116 */

27077

+/* Reported by Zhendong Su <su@cs.ucdavis.edu> */

27078

+

27079

+extern void abort (void);

27080

+

27081

+int a, b, c, d = 1, e, f = 1, h, i, k;

27082

+char g, j;

27083

+

27084

+void

27085

+fn1 (void)

27086

+{

27087

+ int l;

27088

+ e = 0;

27089

+ c = 0;

27090

+ for (;;)

27091

+ {

27092

+ k = a && b;

27093

+ j = k * 54;

27094

+ g = j * 147;

27095

+ l = ~g + (long long) e && 1;

27096

+ if (d)

27097

+ c = l;

27098

+ else

27099

+ h = i = l * 9UL;

27100

+ if (f)

27101

+ return;

27102

+ }

27103

+}

27104

+

27105

+int

27106

+main (void)

27107

+{

27108

+ fn1 ();

27109

+ if (c != 1)

27110

+ abort ();

27111

+ return 0;

27112

+}

27113

Index: gcc/testsuite/gcc.c-torture/execute/pr58984.c

27114

===================================================================

27115

--- a/src/gcc/testsuite/gcc.c-torture/execute/pr58984.c (.../tags/gcc_4_8_2_release)

27116

+++ b/src/gcc/testsuite/gcc.c-torture/execute/pr58984.c (.../branches/gcc-4_8-branch)

27117

@@ -0,0 +1,57 @@

27118

+/* PR tree-optimization/58984 */

27119

+

27120

+struct S { int f0 : 8; int : 6; int f1 : 5; };

27121

+struct T { char f0; int : 6; int f1 : 5; };

27122

+

27123

+int a, *c = &a, e, n, b, m;

27124

+

27125

+static int

27126

+foo (struct S p)

27127

+{

27128

+ const unsigned short *f[36];

27129

+ for (; e < 2; e++)

27130

+ {

27131

+ const unsigned short **i = &f[0];

27132

+ *c ^= 1;

27133

+ if (p.f1)

27134

+ {

27135

+ *i = 0;

27136

+ return b;

27137

+ }

27138

+ }

27139

+ return 0;

27140

+}

27141

+

27142

+static int

27143

+bar (struct T p)

27144

+{

27145

+ const unsigned short *f[36];

27146

+ for (; e < 2; e++)

27147

+ {

27148

+ const unsigned short **i = &f[0];

27149

+ *c ^= 1;

27150

+ if (p.f1)

27151

+ {

27152

+ *i = 0;

27153

+ return b;

27154

+ }

27155

+ }

27156

+ return 0;

27157

+}

27158

+

27159

+int

27160

+main ()

27161

+{

27162

+ struct S o = { 1, 1 };

27163

+ foo (o);

27164

+ m = n || o.f0;

27165

+ if (a != 1)

27166

+ __builtin_abort ();

27167

+ e = 0;

27168

+ struct T p = { 1, 1 };

27169

+ bar (p);

27170

+ m |= n || p.f0;

27171

+ if (a != 0)

27172

+ __builtin_abort ();

27173

+ return 0;

27174

+}

27175

Index: gcc/testsuite/gcc.c-torture/execute/pr60454.c

27176

===================================================================

27177

--- a/src/gcc/testsuite/gcc.c-torture/execute/pr60454.c (.../tags/gcc_4_8_2_release)

27178

+++ b/src/gcc/testsuite/gcc.c-torture/execute/pr60454.c (.../branches/gcc-4_8-branch)

27179

@@ -0,0 +1,31 @@

27180

+#ifdef __UINT32_TYPE__

27181

+typedef __UINT32_TYPE__ uint32_t;

27182

+#else

27183

+typedef unsigned uint32_t;

27184

+#endif

27185

+

27186

+#define __fake_const_swab32(x) ((uint32_t)( \

27187

+ (((uint32_t)(x) & (uint32_t)0x000000ffUL) << 24) | \

27188

+ (((uint32_t)(x) & (uint32_t)0x0000ff00UL) << 8) | \

27189

+ (((uint32_t)(x) & (uint32_t)0x000000ffUL) << 8) | \

27190

+ (((uint32_t)(x) & (uint32_t)0x0000ff00UL) ) | \

27191

+ (((uint32_t)(x) & (uint32_t)0xff000000UL) >> 24)))

27192

+

27193

+/* Previous version of bswap optimization would detect byte swap when none

27194

+ happen. This test aims at catching such wrong detection to avoid

27195

+ regressions. */

27196

+

27197

+__attribute__ ((noinline, noclone)) uint32_t

27198

+fake_swap32 (uint32_t in)

27199

+{

27200

+ return __fake_const_swab32 (in);

27201

+}

27202

+

27203

+int main(void)

27204

+{

27205

+ if (sizeof (uint32_t) * __CHAR_BIT__ != 32)

27206

+ return 0;

27207

+ if (fake_swap32 (0x12345678UL) != 0x78567E12UL)

27208

+ __builtin_abort ();

27209

+ return 0;

27210

+}

27211

Index: gcc/testsuite/gcc.c-torture/execute/pr60017.c

27212

===================================================================

27213

--- a/src/gcc/testsuite/gcc.c-torture/execute/pr60017.c (.../tags/gcc_4_8_2_release)

27214

+++ b/src/gcc/testsuite/gcc.c-torture/execute/pr60017.c (.../branches/gcc-4_8-branch)

27215

@@ -0,0 +1,33 @@

27216

+/* PR target/60017 */

27217

+

27218

+extern void abort (void);

27219

+

27220

+struct S0

27221

+{

27222

+ short m0;

27223

+ short m1;

27224

+};

27225

+

27226

+struct S1

27227

+{

27228

+ unsigned m0:1;

27229

+ char m1[2][2];

27230

+ struct S0 m2[2];

27231

+};

27232

+

27233

+struct S1 x = { 1, {{2, 3}, {4, 5}}, {{6, 7}, {8, 9}} };

27234

+

27235

+struct S1 func (void)

27236

+{

27237

+ return x;

27238

+}

27239

+

27240

+int main (void)

27241

+{

27242

+ struct S1 ret = func ();

27243

+

27244

+ if (ret.m2[1].m1 != 9)

27245

+ abort ();

27246

+

27247

+ return 0;

27248

+}

27249

Index: gcc/testsuite/gcc.c-torture/execute/20131127-1.c

27250

===================================================================

27251

--- a/src/gcc/testsuite/gcc.c-torture/execute/20131127-1.c (.../tags/gcc_4_8_2_release)

27252

+++ b/src/gcc/testsuite/gcc.c-torture/execute/20131127-1.c (.../branches/gcc-4_8-branch)

27253

@@ -0,0 +1,34 @@

27254

+/* PR middle-end/59138 */

27255

+/* Testcase by John Regehr <regehr@cs.utah.edu> */

27256

+

27257

+extern void abort (void);

27258

+

27259

+#pragma pack(1)

27260

+

27261

+struct S0 {

27262

+ int f0;

27263

+ int f1;

27264

+ int f2;

27265

+ short f3;

27266

+};

27267

+

27268

+short a = 1;

27269

+

27270

+struct S0 b = { 1 }, c, d, e;

27271

+

27272

+struct S0 fn1() { return c; }

27273

+

27274

+void fn2 (void)

27275

+{

27276

+ b = fn1 ();

27277

+ a = 0;

27278

+ d = e;

27279

+}

27280

+

27281

+int main (void)

27282

+{

27283

+ fn2 ();

27284

+ if (a != 0)

27285

+ abort ();

27286

+ return 0;

27287

+}

27288

Index: gcc/testsuite/gcc.c-torture/execute/pr59358.c

27289

===================================================================

27290

--- a/src/gcc/testsuite/gcc.c-torture/execute/pr59358.c (.../tags/gcc_4_8_2_release)

27291

+++ b/src/gcc/testsuite/gcc.c-torture/execute/pr59358.c (.../branches/gcc-4_8-branch)

27292

@@ -0,0 +1,44 @@

27293

+/* PR tree-optimization/59358 */

27294

+

27295

+__attribute__((noinline, noclone)) int

27296

+foo (int *x, int y)

27297

+{

27298

+ int z = *x;

27299

+ if (y > z && y <= 16)

27300

+ while (y > z)

27301

+ z *= 2;

27302

+ return z;

27303

+}

27304

+

27305

+int

27306

+main ()

27307

+{

27308

+ int i;

27309

+ for (i = 1; i < 17; i++)

27310

+ {

27311

+ int j = foo (&i, 16);

27312

+ int k;

27313

+ if (i >= 8 && i <= 15)

27314

+ k = 16 + (i - 8) * 2;

27315

+ else if (i >= 4 && i <= 7)

27316

+ k = 16 + (i - 4) * 4;

27317

+ else if (i == 3)

27318

+ k = 24;

27319

+ else

27320

+ k = 16;

27321

+ if (j != k)

27322

+ __builtin_abort ();

27323

+ j = foo (&i, 7);

27324

+ if (i >= 7)

27325

+ k = i;

27326

+ else if (i >= 4)

27327

+ k = 8 + (i - 4) * 2;

27328

+ else if (i == 3)

27329

+ k = 12;

27330

+ else

27331

+ k = 8;

27332

+ if (j != k)

27333

+ __builtin_abort ();

27334

+ }

27335

+ return 0;

27336

+}

27337

Index: gcc/testsuite/gcc.c-torture/execute/pr60062.c

27338

===================================================================

27339

--- a/src/gcc/testsuite/gcc.c-torture/execute/pr60062.c (.../tags/gcc_4_8_2_release)

27340

+++ b/src/gcc/testsuite/gcc.c-torture/execute/pr60062.c (.../branches/gcc-4_8-branch)

27341

@@ -0,0 +1,25 @@

27342

+/* PR target/60062 */

27343

+

27344

+int a;

27345

+

27346

+static void

27347

+foo (const char *p1, int p2)

27348

+{

27349

+ if (__builtin_strcmp (p1, "hello") != 0)

27350

+ __builtin_abort ();

27351

+}

27352

+

27353

+static void

27354

+bar (const char *p1)

27355

+{

27356

+ if (__builtin_strcmp (p1, "hello") != 0)

27357

+ __builtin_abort ();

27358

+}

27359

+

27360

+__attribute__((optimize (0))) int

27361

+main ()

27362

+{

27363

+ foo ("hello", a);

27364

+ bar ("hello");

27365

+ return 0;

27366

+}

27367

Index: gcc/testsuite/gcc.c-torture/execute/20140425-1.c

27368

===================================================================

27369

--- a/src/gcc/testsuite/gcc.c-torture/execute/20140425-1.c (.../tags/gcc_4_8_2_release)

27370

+++ b/src/gcc/testsuite/gcc.c-torture/execute/20140425-1.c (.../branches/gcc-4_8-branch)

27371

@@ -0,0 +1,23 @@

27372

+/* PR target/60941 */

27373

+/* Reported by Martin Husemann <martin@netbsd.org> */

27374

+

27375

+extern void abort (void);

27376

+

27377

+static void __attribute__((noinline))

27378

+set (unsigned long *l)

27379

+{

27380

+ *l = 31;

27381

+}

27382

+

27383

+int main (void)

27384

+{

27385

+ unsigned long l;

27386

+ int i;

27387

+

27388

+ set (&l);

27389

+ i = (int) l;

27390

+ l = (unsigned long)(2U << i);

27391

+ if (l != 0)

27392

+ abort ();

27393

+ return 0;

27394

+}

27395

Index: gcc/testsuite/gcc.c-torture/execute/pr59014-2.c

27396

===================================================================

27397

--- a/src/gcc/testsuite/gcc.c-torture/execute/pr59014-2.c (.../tags/gcc_4_8_2_release)

27398

+++ b/src/gcc/testsuite/gcc.c-torture/execute/pr59014-2.c (.../branches/gcc-4_8-branch)

27399

@@ -0,0 +1,23 @@

27400

+/* PR tree-optimization/59014 */

27401

+

27402

+__attribute__((noinline, noclone)) long long int

27403

+foo (long long int x, long long int y)

27404

+{

27405

+ if (((int) x | (int) y) != 0)

27406

+ return 6;

27407

+ return x + y;

27408

+}

27409

+

27410

+int

27411

+main ()

27412

+{

27413

+ if (sizeof (long long) == sizeof (int))

27414

+ return 0;

27415

+ int shift_half = sizeof (int) * __CHAR_BIT__ / 2;

27416

+ long long int x = (3LL << shift_half) << shift_half;

27417

+ long long int y = (5LL << shift_half) << shift_half;

27418

+ long long int z = foo (x, y);

27419

+ if (z != ((8LL << shift_half) << shift_half))

27420

+ __builtin_abort ();

27421

+ return 0;

27422

+}

27423

Index: gcc/testsuite/gcc.c-torture/execute/pr59101.c

27424

===================================================================

27425

--- a/src/gcc/testsuite/gcc.c-torture/execute/pr59101.c (.../tags/gcc_4_8_2_release)

27426

+++ b/src/gcc/testsuite/gcc.c-torture/execute/pr59101.c (.../branches/gcc-4_8-branch)

27427

@@ -0,0 +1,15 @@

27428

+/* PR target/59101 */

27429

+

27430

+__attribute__((noinline, noclone)) int

27431

+foo (int a)

27432

+{

27433

+ return (~a & 4102790424LL) > 0 | 6;

27434

+}

27435

+

27436

+int

27437

+main ()

27438

+{

27439

+ if (foo (0) != 7)

27440

+ __builtin_abort ();

27441

+ return 0;

27442

+}

27443

Index: gcc/testsuite/gcc.c-torture/execute/pr58831.c

27444

===================================================================

27445

--- a/src/gcc/testsuite/gcc.c-torture/execute/pr58831.c (.../tags/gcc_4_8_2_release)

27446

+++ b/src/gcc/testsuite/gcc.c-torture/execute/pr58831.c (.../branches/gcc-4_8-branch)

27447

@@ -0,0 +1,40 @@

27448

+#include <assert.h>

27449

+

27450

+int a, *b, c, d, f, **i, p, q, *r;

27451

+short o, j;

27452

+

27453

+static int __attribute__((noinline, noclone))

27454

+fn1 (int *p1, int **p2)

27455

+{

27456

+ int **e = &b;

27457

+ for (; p; p++)

27458

+ *p1 = 1;

27459

+ *e = *p2 = &d;

27460

+

27461

+ assert (r);

27462

+

27463

+ return c;

27464

+}

27465

+

27466

+static int ** __attribute__((noinline, noclone))

27467

+fn2 (void)

27468

+{

27469

+ for (f = 0; f != 42; f++)

27470

+ {

27471

+ int *g[3] = {0, 0, 0};

27472

+ for (o = 0; o; o--)

27473

+ for (; a > 1;)

27474

+ {

27475

+ int **h[1] = { &g[2] };

27476

+ }

27477

+ }

27478

+ return &r;

27479

+}

27480

+

27481

+int

27482

+main (void)

27483

+{

27484

+ i = fn2 ();

27485

+ fn1 (b, i);

27486

+ return 0;

27487

+}

27488

Index: gcc/testsuite/gcc.c-torture/execute/pr58726.c

27489

===================================================================

27490

--- a/src/gcc/testsuite/gcc.c-torture/execute/pr58726.c (.../tags/gcc_4_8_2_release)

27491

+++ b/src/gcc/testsuite/gcc.c-torture/execute/pr58726.c (.../branches/gcc-4_8-branch)

27492

@@ -0,0 +1,26 @@

27493

+/* PR rtl-optimization/58726 */

27494

+

27495

+int a, c;

27496

+union { int f1; int f2 : 1; } b;

27497

+

27498

+short

27499

+foo (short p)

27500

+{

27501

+ return p < 0 ? p : a;

27502

+}

27503

+

27504

+int

27505

+main ()

27506

+{

27507

+ if (sizeof (short) * __CHAR_BIT__ != 16

27508

+ || sizeof (int) * __CHAR_BIT__ != 32)

27509

+ return 0;

27510

+ b.f1 = 56374;

27511

+ unsigned short d;

27512

+ int e = b.f2;

27513

+ d = e == 0 ? b.f1 : 0;

27514

+ c = foo (d);

27515

+ if (c != (short) 56374)

27516

+ __builtin_abort ();

27517

+ return 0;

27518

+}

27519

Index: gcc/testsuite/gcc.c-torture/execute/pr59014.c

27520

===================================================================

27521

--- a/src/gcc/testsuite/gcc.c-torture/execute/pr59014.c (.../tags/gcc_4_8_2_release)

27522

+++ b/src/gcc/testsuite/gcc.c-torture/execute/pr59014.c (.../branches/gcc-4_8-branch)

27523

@@ -0,0 +1,25 @@

27524

+/* PR tree-optimization/59014 */

27525

+

27526

+int a = 2, b, c, d;

27527

+

27528

+int

27529

+foo ()

27530

+{

27531

+ for (;; c++)

27532

+ if ((b > 0) | (a & 1))

27533

+ ;

27534

+ else

27535

+ {

27536

+ d = a;

27537

+ return 0;

27538

+ }

27539

+}

27540

+

27541

+int

27542

+main ()

27543

+{

27544

+ foo ();

27545

+ if (d != 2)

27546

+ __builtin_abort ();

27547

+ return 0;

27548

+}

27549

Index: gcc/testsuite/gcc.c-torture/execute/pr60960.c

27550

===================================================================

27551

--- a/src/gcc/testsuite/gcc.c-torture/execute/pr60960.c (.../tags/gcc_4_8_2_release)

27552

+++ b/src/gcc/testsuite/gcc.c-torture/execute/pr60960.c (.../branches/gcc-4_8-branch)

27553

@@ -0,0 +1,38 @@

27554

+/* PR tree-optimization/60960 */

27555

+

27556

+typedef unsigned char v4qi __attribute__ ((vector_size (4)));

27557

+

27558

+__attribute__((noinline, noclone)) v4qi

27559

+f1 (v4qi v)

27560

+{

27561

+ return v / 2;

27562

+}

27563

+

27564

+__attribute__((noinline, noclone)) v4qi

27565

+f2 (v4qi v)

27566

+{

27567

+ return v / (v4qi) { 2, 2, 2, 2 };

27568

+}

27569

+

27570

+__attribute__((noinline, noclone)) v4qi

27571

+f3 (v4qi x, v4qi y)

27572

+{

27573

+ return x / y;

27574

+}

27575

+

27576

+int

27577

+main ()

27578

+{

27579

+ v4qi x = { 5, 5, 5, 5 };

27580

+ v4qi y = { 2, 2, 2, 2 };

27581

+ v4qi z = f1 (x);

27582

+ if (__builtin_memcmp (&y, &z, sizeof (y)) != 0)

27583

+ __builtin_abort ();

27584

+ z = f2 (x);

27585

+ if (__builtin_memcmp (&y, &z, sizeof (y)) != 0)

27586

+ __builtin_abort ();

27587

+ z = f3 (x, y);

27588

+ if (__builtin_memcmp (&y, &z, sizeof (y)) != 0)

27589

+ __builtin_abort ();

27590

+ return 0;

27591

+}

27592

Index: gcc/testsuite/gcc.c-torture/execute/pr60072.c

27593

===================================================================

27594

--- a/src/gcc/testsuite/gcc.c-torture/execute/pr60072.c (.../tags/gcc_4_8_2_release)

27595

+++ b/src/gcc/testsuite/gcc.c-torture/execute/pr60072.c (.../branches/gcc-4_8-branch)

27596

@@ -0,0 +1,16 @@

27597

+/* PR target/60072 */

27598

+

27599

+int c = 1;

27600

+

27601

+__attribute__ ((optimize (1)))

27602

+static int *foo (int *p)

27603

+{

27604

+ return p;

27605

+}

27606

+

27607

+int

27608

+main ()

27609

+{

27610

+ *foo (&c) = 2;

27611

+ return c - 2;

27612

+}

27613

Index: gcc/testsuite/gcc.c-torture/execute/20140326-1.c

27614

===================================================================

27615

--- a/src/gcc/testsuite/gcc.c-torture/execute/20140326-1.c (.../tags/gcc_4_8_2_release)

27616

+++ b/src/gcc/testsuite/gcc.c-torture/execute/20140326-1.c (.../branches/gcc-4_8-branch)

27617

@@ -0,0 +1,10 @@

27618

+int a;

27619

+

27620

+int

27621

+main (void)

27622

+{

27623

+ char e[2] = { 0, 0 }, f = 0;

27624

+ if (a == 131072)

27625

+ f = e[a];

27626

+ return f;

27627

+}

27628

Index: gcc/testsuite/gcc.c-torture/execute/pr59388.c

27629

===================================================================

27630

--- a/src/gcc/testsuite/gcc.c-torture/execute/pr59388.c (.../tags/gcc_4_8_2_release)

27631

+++ b/src/gcc/testsuite/gcc.c-torture/execute/pr59388.c (.../branches/gcc-4_8-branch)

27632

@@ -0,0 +1,11 @@

27633

+/* PR tree-optimization/59388 */

27634

+

27635

+int a;

27636

+struct S { unsigned int f:1; } b;

27637

+

27638

+int

27639

+main ()

27640

+{

27641

+ a = (0 < b.f) | b.f;

27642

+ return a;

27643

+}

27644

Index: gcc/testsuite/gcc.c-torture/compile/pr58970-1.c

27645

===================================================================

27646

--- a/src/gcc/testsuite/gcc.c-torture/compile/pr58970-1.c (.../tags/gcc_4_8_2_release)

27647

+++ b/src/gcc/testsuite/gcc.c-torture/compile/pr58970-1.c (.../branches/gcc-4_8-branch)

27648

@@ -0,0 +1,11 @@

27649

+/* PR middle-end/58970 */

27650

+

27651

+struct T { int b : 1; };

27652

+struct S { struct T t[1]; };

27653

+

27654

+void

27655

+foo (int x, struct S *s)

27656

+{

27657

+ if (x == -1)

27658

+ s->t[x].b = 0;

27659

+}

27660

Index: gcc/testsuite/gcc.c-torture/compile/pr59803.c

27661

===================================================================

27662

--- a/src/gcc/testsuite/gcc.c-torture/compile/pr59803.c (.../tags/gcc_4_8_2_release)

27663

+++ b/src/gcc/testsuite/gcc.c-torture/compile/pr59803.c (.../branches/gcc-4_8-branch)

27664

@@ -0,0 +1,27 @@

27665

+/* PR target/59803 */

27666

+

27667

+extern void baz (void) __attribute__ ((__noreturn__));

27668

+struct A { int g, h; };

27669

+extern struct A a;

27670

+struct B { unsigned char i, j, k, l, m; };

27671

+int c, d, e;

27672

+static int f;

27673

+

27674

+void

27675

+foo (void)

27676

+{

27677

+ f = 1;

27678

+}

27679

+

27680

+void

27681

+bar (struct B *x)

27682

+{

27683

+ x->i = e;

27684

+ x->k = c;

27685

+ x->l = d;

27686

+ x->j = a.h;

27687

+ x->m = f;

27688

+ if (x->i != e) baz ();

27689

+ if (x->k != c) baz ();

27690

+ if (x->j != a.h) baz ();

27691

+}

27692

Index: gcc/testsuite/gcc.c-torture/compile/pr58997.c

27693

===================================================================

27694

--- a/src/gcc/testsuite/gcc.c-torture/compile/pr58997.c (.../tags/gcc_4_8_2_release)

27695

+++ b/src/gcc/testsuite/gcc.c-torture/compile/pr58997.c (.../branches/gcc-4_8-branch)

27696

@@ -0,0 +1,19 @@

27697

+/* PR rtl-optimization/58997 */

27698

+

27699

+int a, b, c, e;

27700

+short d;

27701

+char h;

27702

+

27703

+void

27704

+foo ()

27705

+{

27706

+ while (b)

27707

+ {

27708

+ d = a ? c : 1 % a;

27709

+ c = d;

27710

+ h = d;

27711

+ if (!h)

27712

+ while (e)

27713

+ ;

27714

+ }

27715

+}

27716

Index: gcc/testsuite/gcc.c-torture/compile/pr60502.c

27717

===================================================================

27718

--- a/src/gcc/testsuite/gcc.c-torture/compile/pr60502.c (.../tags/gcc_4_8_2_release)

27719

+++ b/src/gcc/testsuite/gcc.c-torture/compile/pr60502.c (.../branches/gcc-4_8-branch)

27720

@@ -0,0 +1,18 @@

27721

+/* PR tree-optimization/60502 */

27722

+

27723

+typedef signed char v16i8 __attribute__ ((vector_size (16)));

27724

+typedef unsigned char v16u8 __attribute__ ((vector_size (16)));

27725

+

27726

+void

27727

+foo (v16i8 *x)

27728

+{

27729

+ v16i8 m1 = { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 };

27730

+ *x |= *x ^ m1;

27731

+}

27732

+

27733

+void

27734

+bar (v16u8 *x)

27735

+{

27736

+ v16u8 m1 = { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 };

27737

+ *x |= *x ^ m1;

27738

+}

27739

Index: gcc/testsuite/gcc.c-torture/compile/pr58970-2.c

27740

===================================================================

27741

--- a/src/gcc/testsuite/gcc.c-torture/compile/pr58970-2.c (.../tags/gcc_4_8_2_release)

27742

+++ b/src/gcc/testsuite/gcc.c-torture/compile/pr58970-2.c (.../branches/gcc-4_8-branch)

27743

@@ -0,0 +1,11 @@

27744

+/* PR middle-end/58970 */

27745

+

27746

+struct T { char a : 8; char b : 1; };

27747

+struct S { char x; struct T t[1]; };

27748

+

27749

+void

27750

+foo (int x, struct S *s)

27751

+{

27752

+ if (x == -1)

27753

+ s->t[x].b = 0;

27754

+}

27755

Index: gcc/testsuite/gcc.c-torture/compile/pr59362.c

27756

===================================================================

27757

--- a/src/gcc/testsuite/gcc.c-torture/compile/pr59362.c (.../tags/gcc_4_8_2_release)

27758

+++ b/src/gcc/testsuite/gcc.c-torture/compile/pr59362.c (.../branches/gcc-4_8-branch)

27759

@@ -0,0 +1,21 @@

27760

+/* PR tree-optimization/59362 */

27761

+

27762

+char *

27763

+foo (char *r, int s)

27764

+{

27765

+ r = __builtin___stpcpy_chk (r, "abc", __builtin_object_size (r, 1));

27766

+ if (s)

27767

+ r = __builtin___stpcpy_chk (r, "d", __builtin_object_size (r, 1));

27768

+ return r;

27769

+}

27770

+

27771

+char *a;

27772

+long int b;

27773

+

27774

+void

27775

+bar (void)

27776

+{

27777

+ b = __builtin_object_size (0, 0);

27778

+ a = __builtin___stpcpy_chk (0, "", b);

27779

+ b = __builtin_object_size (a, 0);

27780

+}

27781

Index: gcc/testsuite/gnat.dg/opt32.adb

27782

===================================================================

27783

--- a/src/gcc/testsuite/gnat.dg/opt32.adb (.../tags/gcc_4_8_2_release)

27784

+++ b/src/gcc/testsuite/gnat.dg/opt32.adb (.../branches/gcc-4_8-branch)

27785

@@ -0,0 +1,37 @@

27786

+-- { dg-do compile }

27787

+-- { dg-options "-O2" }

27788

+

27789

+with Ada.Containers; use Ada.Containers;

27790

+with Ada.Containers.Vectors;

27791

+

27792

+function Opt32 return Natural is

27793

+

27794

+ package My_Vectors

27795

+ is new Vectors (Index_Type => Natural, Element_Type => Integer);

27796

+ use My_Vectors;

27797

+

27798

+ V : Vector;

27799

+

27800

+ function Sign_Changes return Natural is

27801

+ Cur : Cursor := To_Cursor (V, 0);

27802

+ R : Natural := 0;

27803

+ Negative : Boolean;

27804

+ begin

27805

+ Negative := Element (Cur) < 0;

27806

+

27807

+ loop

27808

+ Cur := Next (Cur);

27809

+ exit when R > 100;

27810

+

27811

+ if (Element (Cur) < 0) /= Negative then

27812

+ Negative := not Negative;

27813

+ R := R + 1;

27814

+ end if;

27815

+ end loop;

27816

+

27817

+ return R;

27818

+ end;

27819

+

27820

+begin

27821

+ return Sign_Changes;

27822

+end;

27823

Index: gcc/testsuite/gcc.dg/pr58668.c

27824

===================================================================

27825

--- a/src/gcc/testsuite/gcc.dg/pr58668.c (.../tags/gcc_4_8_2_release)

27826

+++ b/src/gcc/testsuite/gcc.dg/pr58668.c (.../branches/gcc-4_8-branch)

27827

@@ -0,0 +1,25 @@

27828

+/* PR rtl-optimization/58668 */

27829

+/* { dg-do compile } */

27830

+/* { dg-options "-O2" } */

27831

+/* { dg-additional-options "-mthumb" { target { { arm*-*-* } && arm_thumb2_ok } } } */

27832

+

27833

+void *fn1 (void *);

27834

+void *fn2 (void *, const char *);

27835

+void fn3 (void *);

27836

+void fn4 (void *, int);

27837

+

27838

+void *

27839

+test (void *x)

27840

+{

27841

+ void *a, *b;

27842

+ if (!(a = fn1 (x)))

27843

+ return (void *) 0;

27844

+ if (!(b = fn2 (a, "w")))

27845

+ {

27846

+ fn3 (a);

27847

+ return (void *) 0;

27848

+ }

27849

+ fn3 (a);

27850

+ fn4 (b, 1);

27851

+ return b;

27852

+}

27853

Index: gcc/testsuite/gcc.dg/pr57518.c

27854

===================================================================

27855

--- a/src/gcc/testsuite/gcc.dg/pr57518.c (.../tags/gcc_4_8_2_release)

27856

+++ b/src/gcc/testsuite/gcc.dg/pr57518.c (.../branches/gcc-4_8-branch)

27857

@@ -1,8 +1,8 @@

27858

-/* PR rtl-optimization/57130 */

27859

+/* PR rtl-optimization/57518 */

27860

27861

/* { dg-do compile } */

27862

/* { dg-options "-O2 -fdump-rtl-ira" } */

27863

-/* { dg-final { scan-rtl-dump-not "REG_EQUIV.*mem.*\"ip\"" "ira" } } */

27864

+/* { dg-final { scan-rtl-dump-not "REG_EQUIV\[^\n\]*mem\[^\n\]*\"ip\".*subreg" "ira" } } */

27865

27866

char ip[10];

27867

int total;

27868

Index: gcc/testsuite/gcc.dg/builtin-object-size-14.c

27869

===================================================================

27870

--- a/src/gcc/testsuite/gcc.dg/builtin-object-size-14.c (.../tags/gcc_4_8_2_release)

27871

+++ b/src/gcc/testsuite/gcc.dg/builtin-object-size-14.c (.../branches/gcc-4_8-branch)

27872

@@ -0,0 +1,28 @@

27873

+/* { dg-do run } */

27874

+/* { dg-options "-O2" } */

27875

+

27876

+extern void abort (void);

27877

+extern char *strncpy(char *, const char *, __SIZE_TYPE__);

27878

+

27879

+union u {

27880

+ struct {

27881

+ char vi[8];

27882

+ char pi[16];

27883

+ };

27884

+ char all[8+16+4];

27885

+};

27886

+

27887

+void __attribute__((noinline,noclone))

27888

+f(union u *u)

27889

+{

27890

+ char vi[8+1];

27891

+ __builtin_strncpy(vi, u->vi, sizeof(u->vi));

27892

+ if (__builtin_object_size (u->all, 1) != -1)

27893

+ abort ();

27894

+}

27895

+int main()

27896

+{

27897

+ union u u;

27898

+ f (&u);

27899

+ return 0;

27900

+}

27901

Index: gcc/testsuite/gcc.dg/gomp/pr58809.c

27902

===================================================================

27903

--- a/src/gcc/testsuite/gcc.dg/gomp/pr58809.c (.../tags/gcc_4_8_2_release)

27904

+++ b/src/gcc/testsuite/gcc.dg/gomp/pr58809.c (.../branches/gcc-4_8-branch)

27905

@@ -0,0 +1,13 @@

27906

+/* PR middle-end/58809 */

27907

+/* { dg-do compile } */

27908

+/* { dg-options "-fopenmp -O" } */

27909

+

27910

+int i;

27911

+#pragma omp threadprivate (i)

27912

+

27913

+void foo()

27914

+{

27915

+ _Complex int j;

27916

+#pragma omp parallel copyin (i) reduction (&&:j)

27917

+ ;

27918

+}

27919

Index: gcc/testsuite/gcc.dg/20050922-1.c

27920

===================================================================

27921

--- a/src/gcc/testsuite/gcc.dg/20050922-1.c (.../tags/gcc_4_8_2_release)

27922

+++ b/src/gcc/testsuite/gcc.dg/20050922-1.c (.../branches/gcc-4_8-branch)

27923

@@ -4,7 +4,7 @@

27924

/* { dg-do run } */

27925

/* { dg-options "-O1 -std=c99" } */

27926

27927

-#include <stdlib.h>

27928

+extern void abort (void);

27929

27930

#if __INT_MAX__ == 2147483647

27931

typedef unsigned int uint32_t;

27932

Index: gcc/testsuite/gcc.dg/pr46309.c

27933

===================================================================

27934

--- a/src/gcc/testsuite/gcc.dg/pr46309.c (.../tags/gcc_4_8_2_release)

27935

+++ b/src/gcc/testsuite/gcc.dg/pr46309.c (.../branches/gcc-4_8-branch)

27936

@@ -1,5 +1,5 @@

27937

/* PR tree-optimization/46309 */

27938

-/* { dg-do compile } */

27939

+/* { dg-do compile { target { ! { cris*-*-* } } } } */

27940

/* { dg-options "-O2 -fdump-tree-reassoc-details" } */

27941

/* The transformation depends on BRANCH_COST being greater than 1

27942

(see the notes in the PR), so try to force that. */

27943

Index: gcc/testsuite/gcc.dg/pr60485-2.c

27944

===================================================================

27945

--- a/src/gcc/testsuite/gcc.dg/pr60485-2.c (.../tags/gcc_4_8_2_release)

27946

+++ b/src/gcc/testsuite/gcc.dg/pr60485-2.c (.../branches/gcc-4_8-branch)

27947

@@ -0,0 +1,38 @@

27948

+/* { dg-do run } */

27949

+/* { dg-options "-O2" } */

27950

+

27951

+extern void abort (void);

27952

+struct S {

27953

+ int *i[4];

27954

+ int *p1;

27955

+ int *p2;

27956

+ int *p3;

27957

+ int *p4;

27958

+ int **x;

27959

+};

27960

+int **b;

27961

+int main()

27962

+{

27963

+ int i = 1;

27964

+ struct S s;

27965

+ s.p3 = &i;

27966

+ int **p;

27967

+ if (b)

27968

+ p = b;

27969

+ else

27970

+ p = &s.i[2];

27971

+ p += 4;

27972

+ /* prevert fowrprop from creating an offsetted sd constraint and

27973

+ preserve the pointer offsetting constraint. */

27974

+ s.x = p;

27975

+ p = s.x;

27976

+ if (!b)

27977

+ {

27978

+ int *z = *p;

27979

+ /* z should point to i (and non-local/escaped). */

27980

+ *z = 0;

27981

+ }

27982

+ if (i != 0)

27983

+ abort ();

27984

+ return i;

27985

+}

27986

Index: gcc/testsuite/gcc.dg/atomic-store-6.c

27987

===================================================================

27988

--- a/src/gcc/testsuite/gcc.dg/atomic-store-6.c (.../tags/gcc_4_8_2_release)

27989

+++ b/src/gcc/testsuite/gcc.dg/atomic-store-6.c (.../branches/gcc-4_8-branch)

27990

@@ -0,0 +1,13 @@

27991

+/* { dg-do run } */

27992

+/* { dg-require-effective-target sync_int_128_runtime } */

27993

+/* { dg-options "-mcx16" { target { i?86-*-* x86_64-*-* } } } */

27994

+

27995

+__int128_t i;

27996

+

27997

+int main()

27998

+{

27999

+ __atomic_store_16(&i, -1, 0);

28000

+ if (i != -1)

28001

+ __builtin_abort();

28002

+ return 0;

28003

+}

28004

Index: gcc/testsuite/gcc.dg/guality/pr59776.c

28005

===================================================================

28006

--- a/src/gcc/testsuite/gcc.dg/guality/pr59776.c (.../tags/gcc_4_8_2_release)

28007

+++ b/src/gcc/testsuite/gcc.dg/guality/pr59776.c (.../branches/gcc-4_8-branch)

28008

@@ -0,0 +1,29 @@

28009

+/* PR debug/59776 */

28010

+/* { dg-do run } */

28011

+/* { dg-options "-g" } */

28012

+

28013

+#include "../nop.h"

28014

+

28015

+struct S { float f, g; };

28016

+

28017

+__attribute__((noinline, noclone)) void

28018

+foo (struct S *p)

28019

+{

28020

+ struct S s1, s2; /* { dg-final { gdb-test pr59776.c:17 "s1.f" "5.0" } } */

28021

+ s1 = *p; /* { dg-final { gdb-test pr59776.c:17 "s1.g" "6.0" } } */

28022

+ s2 = s1; /* { dg-final { gdb-test pr59776.c:17 "s2.f" "0.0" } } */

28023

+ *(int *) &s2.f = 0; /* { dg-final { gdb-test pr59776.c:17 "s2.g" "6.0" } } */

28024

+ asm volatile (NOP : : : "memory"); /* { dg-final { gdb-test pr59776.c:20 "s1.f" "5.0" } } */

28025

+ asm volatile (NOP : : : "memory"); /* { dg-final { gdb-test pr59776.c:20 "s1.g" "6.0" } } */

28026

+ s2 = s1; /* { dg-final { gdb-test pr59776.c:20 "s2.f" "5.0" } } */

28027

+ asm volatile (NOP : : : "memory"); /* { dg-final { gdb-test pr59776.c:20 "s2.g" "6.0" } } */

28028

+ asm volatile (NOP : : : "memory");

28029

+}

28030

+

28031

+int

28032

+main ()

28033

+{

28034

+ struct S x = { 5.0f, 6.0f };

28035

+ foo (&x);

28036

+ return 0;

28037

+}

28038

Index: gcc/testsuite/gcc.dg/attr-weakref-1.c

28039

===================================================================

28040

--- a/src/gcc/testsuite/gcc.dg/attr-weakref-1.c (.../tags/gcc_4_8_2_release)

28041

+++ b/src/gcc/testsuite/gcc.dg/attr-weakref-1.c (.../branches/gcc-4_8-branch)

28042

@@ -4,12 +4,14 @@

28043

// This test requires support for undefined weak symbols. This support

28044

// is not available on hppa*-*-hpux*. The test is skipped rather than

28045

// xfailed to suppress the warning that would otherwise arise.

28046

-// { dg-skip-if "" { "*-*-darwin*" "hppa*-*-hpux*" } "*" { "" } }

28047

+// { dg-skip-if "" { "hppa*-*-hpux*" } "*" { "" } }

28048

// For kernel modules and static RTPs, the loader treats undefined weak

28049

// symbols in the same way as undefined strong symbols. The test

28050

// therefore fails to load, so skip it.

28051

// { dg-skip-if "" { "*-*-vxworks*" && nonpic } "*" { "-non-static" } }

28052

// { dg-options "-O2" }

28053

+// { dg-additional-options "-Wl,-undefined,dynamic_lookup" { target *-*-darwin* } }

28054

+// { dg-additional-options "-Wl,-flat_namespace" { target *-*-darwin[89]* } }

28055

// { dg-additional-sources "attr-weakref-1a.c" }

28056

28057

28058

Index: gcc/testsuite/gcc.dg/pr59827.c

28059

===================================================================

28060

--- a/src/gcc/testsuite/gcc.dg/pr59827.c (.../tags/gcc_4_8_2_release)

28061

+++ b/src/gcc/testsuite/gcc.dg/pr59827.c (.../branches/gcc-4_8-branch)

28062

@@ -0,0 +1,15 @@

28063

+/* PR middle-end/59827 */

28064

+/* { dg-do compile } */

28065

+

28066

+int

28067

+foo (int p[2][]) /* { dg-error "array type has incomplete element type" } */

28068

+{

28069

+ return p[0][0];

28070

+}

28071

+

28072

+void

28073

+bar (void)

28074

+{

28075

+ int p[2][1];

28076

+ foo (p); /* { dg-error "type of formal parameter 1 is incomplete" } */

28077

+}

28078

Index: gcc/testsuite/gcc.dg/vmx/stl-be-order.c

28079

===================================================================

28080

--- a/src/gcc/testsuite/gcc.dg/vmx/stl-be-order.c (.../tags/gcc_4_8_2_release)

28081

+++ b/src/gcc/testsuite/gcc.dg/vmx/stl-be-order.c (.../branches/gcc-4_8-branch)

28082

@@ -0,0 +1,83 @@

28083

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */

28084

+

28085

+#include "harness.h"

28086

+

28087

+static unsigned char svuc[16] __attribute__ ((aligned (16)));

28088

+static signed char svsc[16] __attribute__ ((aligned (16)));

28089

+static unsigned char svbc[16] __attribute__ ((aligned (16)));

28090

+static unsigned short svus[8] __attribute__ ((aligned (16)));

28091

+static signed short svss[8] __attribute__ ((aligned (16)));

28092

+static unsigned short svbs[8] __attribute__ ((aligned (16)));

28093

+static unsigned short svp[8] __attribute__ ((aligned (16)));

28094

+static unsigned int svui[4] __attribute__ ((aligned (16)));

28095

+static signed int svsi[4] __attribute__ ((aligned (16)));

28096

+static unsigned int svbi[4] __attribute__ ((aligned (16)));

28097

+static float svf[4] __attribute__ ((aligned (16)));

28098

+

28099

+static void check_arrays ()

28100

+{

28101

+ unsigned int i;

28102

+ for (i = 0; i < 16; ++i)

28103

+ {

28104

+ check (svuc[i] == i, "svuc");

28105

+ check (svsc[i] == i - 8, "svsc");

28106

+ check (svbc[i] == ((i % 2) ? 0xff : 0), "svbc");

28107

+ }

28108

+ for (i = 0; i < 8; ++i)

28109

+ {

28110

+ check (svus[i] == i, "svus");

28111

+ check (svss[i] == i - 4, "svss");

28112

+ check (svbs[i] == ((i % 2) ? 0xffff : 0), "svbs");

28113

+ check (svp[i] == i, "svp");

28114

+ }

28115

+ for (i = 0; i < 4; ++i)

28116

+ {

28117

+ check (svui[i] == i, "svui");

28118

+ check (svsi[i] == i - 2, "svsi");

28119

+ check (svbi[i] == ((i % 2) ? 0xffffffff : 0), "svbi");

28120

+ check (svf[i] == i * 1.0f, "svf");

28121

+ }

28122

+}

28123

+

28124

+static void test ()

28125

+{

28126

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

28127

+ vector unsigned char vuc = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};

28128

+ vector signed char vsc = {7,6,5,4,3,2,1,0,-1,-2,-3,-4,-5,-6,-7,-8};

28129

+ vector bool char vbc = {255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0};

28130

+ vector unsigned short vus = {7,6,5,4,3,2,1,0};

28131

+ vector signed short vss = {3,2,1,0,-1,-2,-3,-4};

28132

+ vector bool short vbs = {65535,0,65535,0,65535,0,65535,0};

28133

+ vector pixel vp = {7,6,5,4,3,2,1,0};

28134

+ vector unsigned int vui = {3,2,1,0};

28135

+ vector signed int vsi = {1,0,-1,-2};

28136

+ vector bool int vbi = {0xffffffff,0,0xffffffff,0};

28137

+ vector float vf = {3.0,2.0,1.0,0.0};

28138

+#else

28139

+ vector unsigned char vuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

28140

+ vector signed char vsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};

28141

+ vector bool char vbc = {0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255};

28142

+ vector unsigned short vus = {0,1,2,3,4,5,6,7};

28143

+ vector signed short vss = {-4,-3,-2,-1,0,1,2,3};

28144

+ vector bool short vbs = {0,65535,0,65535,0,65535,0,65535};

28145

+ vector pixel vp = {0,1,2,3,4,5,6,7};

28146

+ vector unsigned int vui = {0,1,2,3};

28147

+ vector signed int vsi = {-2,-1,0,1};

28148

+ vector bool int vbi = {0,0xffffffff,0,0xffffffff};

28149

+ vector float vf = {0.0,1.0,2.0,3.0};

28150

+#endif

28151

+

28152

+ vec_stl (vuc, 0, (vector unsigned char *)svuc);

28153

+ vec_stl (vsc, 0, (vector signed char *)svsc);

28154

+ vec_stl (vbc, 0, (vector bool char *)svbc);

28155

+ vec_stl (vus, 0, (vector unsigned short *)svus);

28156

+ vec_stl (vss, 0, (vector signed short *)svss);

28157

+ vec_stl (vbs, 0, (vector bool short *)svbs);

28158

+ vec_stl (vp, 0, (vector pixel *)svp);

28159

+ vec_stl (vui, 0, (vector unsigned int *)svui);

28160

+ vec_stl (vsi, 0, (vector signed int *)svsi);

28161

+ vec_stl (vbi, 0, (vector bool int *)svbi);

28162

+ vec_stl (vf, 0, (vector float *)svf);

28163

+

28164

+ check_arrays ();

28165

+}

28166

Index: gcc/testsuite/gcc.dg/vmx/perm-be-order.c

28167

===================================================================

28168

--- a/src/gcc/testsuite/gcc.dg/vmx/perm-be-order.c (.../tags/gcc_4_8_2_release)

28169

+++ b/src/gcc/testsuite/gcc.dg/vmx/perm-be-order.c (.../branches/gcc-4_8-branch)

28170

@@ -0,0 +1,74 @@

28171

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */

28172

+

28173

+#include "harness.h"

28174

+

28175

+static void test()

28176

+{

28177

+ /* Input vectors. */

28178

+ vector unsigned char vuca = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

28179

+ vector unsigned char vucb = {16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31};

28180

+ vector signed char vsca = {-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1};

28181

+ vector signed char vscb = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

28182

+ vector unsigned short vusa = {0,1,2,3,4,5,6,7};

28183

+ vector unsigned short vusb = {8,9,10,11,12,13,14,15};

28184

+ vector signed short vssa = {-8,-7,-6,-5,-4,-3,-2,-1};

28185

+ vector signed short vssb = {0,1,2,3,4,5,6,7};

28186

+ vector unsigned int vuia = {0,1,2,3};

28187

+ vector unsigned int vuib = {4,5,6,7};

28188

+ vector signed int vsia = {-4,-3,-2,-1};

28189

+ vector signed int vsib = {0,1,2,3};

28190

+ vector float vfa = {-4.0,-3.0,-2.0,-1.0};

28191

+ vector float vfb = {0.0,1.0,2.0,3.0};

28192

+

28193

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

28194

+ vector unsigned char vucp = {15,16,14,17,13,18,12,19,11,20,10,21,9,22,8,23};

28195

+ vector unsigned char vscp = {15,16,14,17,13,18,12,19,11,20,10,21,9,22,8,23};

28196

+ vector unsigned char vusp = {15,14,17,16,13,12,19,18,11,10,21,20,9,8,23,22};

28197

+ vector unsigned char vssp = {15,14,17,16,13,12,19,18,11,10,21,20,9,8,23,22};

28198

+ vector unsigned char vuip = {15,14,13,12,19,18,17,16,11,10,9,8,23,22,21,20};

28199

+ vector unsigned char vsip = {15,14,13,12,19,18,17,16,11,10,9,8,23,22,21,20};

28200

+ vector unsigned char vfp = {15,14,13,12,19,18,17,16,11,10,9,8,23,22,21,20};

28201

+#else

28202

+ vector unsigned char vucp = {0,31,1,30,2,29,3,28,4,27,5,26,6,25,7,24};

28203

+ vector unsigned char vscp = {0,31,1,30,2,29,3,28,4,27,5,26,6,25,7,24};

28204

+ vector unsigned char vusp = {0,1,30,31,2,3,28,29,4,5,26,27,6,7,24,25};

28205

+ vector unsigned char vssp = {0,1,30,31,2,3,28,29,4,5,26,27,6,7,24,25};

28206

+ vector unsigned char vuip = {0,1,2,3,28,29,30,31,4,5,6,7,24,25,26,27};

28207

+ vector unsigned char vsip = {0,1,2,3,28,29,30,31,4,5,6,7,24,25,26,27};

28208

+ vector unsigned char vfp = {0,1,2,3,28,29,30,31,4,5,6,7,24,25,26,27};

28209

+#endif

28210

+

28211

+ /* Result vectors. */

28212

+ vector unsigned char vuc;

28213

+ vector signed char vsc;

28214

+ vector unsigned short vus;

28215

+ vector signed short vss;

28216

+ vector unsigned int vui;

28217

+ vector signed int vsi;

28218

+ vector float vf;

28219

+

28220

+ /* Expected result vectors. */

28221

+ vector unsigned char vucr = {0,31,1,30,2,29,3,28,4,27,5,26,6,25,7,24};

28222

+ vector signed char vscr = {-16,15,-15,14,-14,13,-13,12,-12,11,-11,10,-10,9,-9,8};

28223

+ vector unsigned short vusr = {0,15,1,14,2,13,3,12};

28224

+ vector signed short vssr = {-8,7,-7,6,-6,5,-5,4};

28225

+ vector unsigned int vuir = {0,7,1,6};

28226

+ vector signed int vsir = {-4,3,-3,2};

28227

+ vector float vfr = {-4.0,3.0,-3.0,2.0};

28228

+

28229

+ vuc = vec_perm (vuca, vucb, vucp);

28230

+ vsc = vec_perm (vsca, vscb, vscp);

28231

+ vus = vec_perm (vusa, vusb, vusp);

28232

+ vss = vec_perm (vssa, vssb, vssp);

28233

+ vui = vec_perm (vuia, vuib, vuip);

28234

+ vsi = vec_perm (vsia, vsib, vsip);

28235

+ vf = vec_perm (vfa, vfb, vfp );

28236

+

28237

+ check (vec_all_eq (vuc, vucr), "vuc");

28238

+ check (vec_all_eq (vsc, vscr), "vsc");

28239

+ check (vec_all_eq (vus, vusr), "vus");

28240

+ check (vec_all_eq (vss, vssr), "vss");

28241

+ check (vec_all_eq (vui, vuir), "vui");

28242

+ check (vec_all_eq (vsi, vsir), "vsi");

28243

+ check (vec_all_eq (vf, vfr), "vf" );

28244

+}

28245

Index: gcc/testsuite/gcc.dg/vmx/insert-be-order.c

28246

===================================================================

28247

--- a/src/gcc/testsuite/gcc.dg/vmx/insert-be-order.c (.../tags/gcc_4_8_2_release)

28248

+++ b/src/gcc/testsuite/gcc.dg/vmx/insert-be-order.c (.../branches/gcc-4_8-branch)

28249

@@ -0,0 +1,65 @@

28250

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */

28251

+

28252

+#include "harness.h"

28253

+

28254

+static void test()

28255

+{

28256

+ vector unsigned char va = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

28257

+ vector signed char vb = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};

28258

+ vector unsigned short vc = {0,1,2,3,4,5,6,7};

28259

+ vector signed short vd = {-4,-3,-2,-1,0,1,2,3};

28260

+ vector unsigned int ve = {0,1,2,3};

28261

+ vector signed int vf = {-2,-1,0,1};

28262

+ vector float vg = {-2.0f,-1.0f,0.0f,1.0f};

28263

+

28264

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

28265

+ check (vec_all_eq (vec_insert (16, va, 5),

28266

+ ((vector unsigned char)

28267

+ {0,1,2,3,4,5,6,7,8,9,16,11,12,13,14,15})),

28268

+ "vec_insert (va LE)");

28269

+ check (vec_all_eq (vec_insert (-16, vb, 0),

28270

+ ((vector signed char)

28271

+ {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,-16})),

28272

+ "vec_insert (vb LE)");

28273

+ check (vec_all_eq (vec_insert (16, vc, 7),

28274

+ ((vector unsigned short){16,1,2,3,4,5,6,7})),

28275

+ "vec_insert (vc LE)");

28276

+ check (vec_all_eq (vec_insert (-16, vd, 3),

28277

+ ((vector signed short){-4,-3,-2,-1,-16,1,2,3})),

28278

+ "vec_insert (vd LE)");

28279

+ check (vec_all_eq (vec_insert (16, ve, 2),

28280

+ ((vector unsigned int){0,16,2,3})),

28281

+ "vec_insert (ve LE)");

28282

+ check (vec_all_eq (vec_insert (-16, vf, 1),

28283

+ ((vector signed int){-2,-1,-16,1})),

28284

+ "vec_insert (vf LE)");

28285

+ check (vec_all_eq (vec_insert (-16.0f, vg, 0),

28286

+ ((vector float){-2.0f,-1.0f,0.0f,-16.0f})),

28287

+ "vec_insert (vg LE)");

28288

+#else

28289

+ check (vec_all_eq (vec_insert (16, va, 5),

28290

+ ((vector unsigned char)

28291

+ {0,1,2,3,4,16,6,7,8,9,10,11,12,13,14,15})),

28292

+ "vec_insert (va BE)");

28293

+ check (vec_all_eq (vec_insert (-16, vb, 0),

28294

+ ((vector signed char)

28295

+ {-16,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7})),

28296

+ "vec_insert (vb BE)");

28297

+ check (vec_all_eq (vec_insert (16, vc, 7),

28298

+ ((vector unsigned short){0,1,2,3,4,5,6,16})),

28299

+ "vec_insert (vc BE)");

28300

+ check (vec_all_eq (vec_insert (-16, vd, 3),

28301

+ ((vector signed short){-4,-3,-2,-16,0,1,2,3})),

28302

+ "vec_insert (vd BE)");

28303

+ check (vec_all_eq (vec_insert (16, ve, 2),

28304

+ ((vector unsigned int){0,1,16,3})),

28305

+ "vec_insert (ve BE)");

28306

+ check (vec_all_eq (vec_insert (-16, vf, 1),

28307

+ ((vector signed int){-2,-16,0,1})),

28308

+ "vec_insert (vf BE)");

28309

+ check (vec_all_eq (vec_insert (-16.0f, vg, 0),

28310

+ ((vector float){-16.0f,-1.0f,0.0f,1.0f})),

28311

+ "vec_insert (vg BE)");

28312

+#endif

28313

+}

28314

+

28315

Index: gcc/testsuite/gcc.dg/vmx/ldl.c

28316

===================================================================

28317

--- a/src/gcc/testsuite/gcc.dg/vmx/ldl.c (.../tags/gcc_4_8_2_release)

28318

+++ b/src/gcc/testsuite/gcc.dg/vmx/ldl.c (.../branches/gcc-4_8-branch)

28319

@@ -0,0 +1,91 @@

28320

+#include "harness.h"

28321

+

28322

+static unsigned char svuc[16] __attribute__ ((aligned (16)));

28323

+static signed char svsc[16] __attribute__ ((aligned (16)));

28324

+static unsigned char svbc[16] __attribute__ ((aligned (16)));

28325

+static unsigned short svus[8] __attribute__ ((aligned (16)));

28326

+static signed short svss[8] __attribute__ ((aligned (16)));

28327

+static unsigned short svbs[8] __attribute__ ((aligned (16)));

28328

+static unsigned short svp[8] __attribute__ ((aligned (16)));

28329

+static unsigned int svui[4] __attribute__ ((aligned (16)));

28330

+static signed int svsi[4] __attribute__ ((aligned (16)));

28331

+static unsigned int svbi[4] __attribute__ ((aligned (16)));

28332

+static float svf[4] __attribute__ ((aligned (16)));

28333

+

28334

+static void init ()

28335

+{

28336

+ unsigned int i;

28337

+ for (i = 0; i < 16; ++i)

28338

+ {

28339

+ svuc[i] = i;

28340

+ svsc[i] = i - 8;

28341

+ svbc[i] = (i % 2) ? 0xff : 0;

28342

+ }

28343

+ for (i = 0; i < 8; ++i)

28344

+ {

28345

+ svus[i] = i;

28346

+ svss[i] = i - 4;

28347

+ svbs[i] = (i % 2) ? 0xffff : 0;

28348

+ svp[i] = i;

28349

+ }

28350

+ for (i = 0; i < 4; ++i)

28351

+ {

28352

+ svui[i] = i;

28353

+ svsi[i] = i - 2;

28354

+ svbi[i] = (i % 2) ? 0xffffffff : 0;

28355

+ svf[i] = i * 1.0f;

28356

+ }

28357

+}

28358

+

28359

+static void test ()

28360

+{

28361

+ vector unsigned char evuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

28362

+ vector signed char evsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};

28363

+ vector bool char evbc = {0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255};

28364

+ vector unsigned short evus = {0,1,2,3,4,5,6,7};

28365

+ vector signed short evss = {-4,-3,-2,-1,0,1,2,3};

28366

+ vector bool short evbs = {0,65535,0,65535,0,65535,0,65535};

28367

+ vector pixel evp = {0,1,2,3,4,5,6,7};

28368

+ vector unsigned int evui = {0,1,2,3};

28369

+ vector signed int evsi = {-2,-1,0,1};

28370

+ vector bool int evbi = {0,0xffffffff,0,0xffffffff};

28371

+ vector float evf = {0.0,1.0,2.0,3.0};

28372

+

28373

+ vector unsigned char vuc;

28374

+ vector signed char vsc;

28375

+ vector bool char vbc;

28376

+ vector unsigned short vus;

28377

+ vector signed short vss;

28378

+ vector bool short vbs;

28379

+ vector pixel vp;

28380

+ vector unsigned int vui;

28381

+ vector signed int vsi;

28382

+ vector bool int vbi;

28383

+ vector float vf;

28384

+

28385

+ init ();

28386

+

28387

+ vuc = vec_ldl (0, (vector unsigned char *)svuc);

28388

+ vsc = vec_ldl (0, (vector signed char *)svsc);

28389

+ vbc = vec_ldl (0, (vector bool char *)svbc);

28390

+ vus = vec_ldl (0, (vector unsigned short *)svus);

28391

+ vss = vec_ldl (0, (vector signed short *)svss);

28392

+ vbs = vec_ldl (0, (vector bool short *)svbs);

28393

+ vp = vec_ldl (0, (vector pixel *)svp);

28394

+ vui = vec_ldl (0, (vector unsigned int *)svui);

28395

+ vsi = vec_ldl (0, (vector signed int *)svsi);

28396

+ vbi = vec_ldl (0, (vector bool int *)svbi);

28397

+ vf = vec_ldl (0, (vector float *)svf);

28398

+

28399

+ check (vec_all_eq (vuc, evuc), "vuc");

28400

+ check (vec_all_eq (vsc, evsc), "vsc");

28401

+ check (vec_all_eq (vbc, evbc), "vbc");

28402

+ check (vec_all_eq (vus, evus), "vus");

28403

+ check (vec_all_eq (vss, evss), "vss");

28404

+ check (vec_all_eq (vbs, evbs), "vbs");

28405

+ check (vec_all_eq (vp, evp ), "vp" );

28406

+ check (vec_all_eq (vui, evui), "vui");

28407

+ check (vec_all_eq (vsi, evsi), "vsi");

28408

+ check (vec_all_eq (vbi, evbi), "vbi");

28409

+ check (vec_all_eq (vf, evf ), "vf" );

28410

+}

28411

Index: gcc/testsuite/gcc.dg/vmx/stl-vsx-be-order.c

28412

===================================================================

28413

--- a/src/gcc/testsuite/gcc.dg/vmx/stl-vsx-be-order.c (.../tags/gcc_4_8_2_release)

28414

+++ b/src/gcc/testsuite/gcc.dg/vmx/stl-vsx-be-order.c (.../branches/gcc-4_8-branch)

28415

@@ -0,0 +1,34 @@

28416

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

28417

+/* { dg-require-effective-target powerpc_vsx_ok } */

28418

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mvsx" } */

28419

+

28420

+#include "harness.h"

28421

+

28422

+static unsigned long long svul[2] __attribute__ ((aligned (16)));

28423

+static double svd[2] __attribute__ ((aligned (16)));

28424

+

28425

+static void check_arrays ()

28426

+{

28427

+ unsigned int i;

28428

+ for (i = 0; i < 2; ++i)

28429

+ {

28430

+ check (svul[i] == i, "svul");

28431

+ check (svd[i] == i * 1.0, "svd");

28432

+ }

28433

+}

28434

+

28435

+static void test ()

28436

+{

28437

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

28438

+ vector unsigned long long vul = {1,0};

28439

+ vector double vd = {1.0,0.0};

28440

+#else

28441

+ vector unsigned long long vul = {0,1};

28442

+ vector double vd = {0.0,1.0};

28443

+#endif

28444

+

28445

+ vec_stl (vul, 0, (vector unsigned long long *)svul);

28446

+ vec_stl (vd, 0, (vector double *)svd);

28447

+

28448

+ check_arrays ();

28449

+}

28450

Index: gcc/testsuite/gcc.dg/vmx/vsums.c

28451

===================================================================

28452

--- a/src/gcc/testsuite/gcc.dg/vmx/vsums.c (.../tags/gcc_4_8_2_release)

28453

+++ b/src/gcc/testsuite/gcc.dg/vmx/vsums.c (.../branches/gcc-4_8-branch)

28454

@@ -0,0 +1,12 @@

28455

+#include "harness.h"

28456

+

28457

+static void test()

28458

+{

28459

+ vector signed int va = {-7,11,-13,17};

28460

+ vector signed int vb = {0,0,0,128};

28461

+ vector signed int evd = {0,0,0,136};

28462

+

28463

+ vector signed int vd = vec_sums (va, vb);

28464

+

28465

+ check (vec_all_eq (vd, evd), "sums");

28466

+}

28467

Index: gcc/testsuite/gcc.dg/vmx/insert-vsx-be-order.c

28468

===================================================================

28469

--- a/src/gcc/testsuite/gcc.dg/vmx/insert-vsx-be-order.c (.../tags/gcc_4_8_2_release)

28470

+++ b/src/gcc/testsuite/gcc.dg/vmx/insert-vsx-be-order.c (.../branches/gcc-4_8-branch)

28471

@@ -0,0 +1,34 @@

28472

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

28473

+/* { dg-require-effective-target powerpc_vsx_ok } */

28474

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mvsx" } */

28475

+

28476

+#include "harness.h"

28477

+

28478

+static int vec_long_long_eq (vector long long x, vector long long y)

28479

+{

28480

+ return (x[0] == y[0] && x[1] == y[1]);

28481

+}

28482

+

28483

+static int vec_dbl_eq (vector double x, vector double y)

28484

+{

28485

+ return (x[0] == y[0] && x[1] == y[1]);

28486

+}

28487

+

28488

+static void test()

28489

+{

28490

+ vector long long vl = {0, 1};

28491

+ vector double vd = {0.0, 1.0};

28492

+ vector long long vlr = vec_insert (2, vl, 0);

28493

+ vector double vdr = vec_insert (2.0, vd, 1);

28494

+

28495

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

28496

+ vector long long vler = {0, 2};

28497

+ vector double vder = {2.0, 1.0};

28498

+#else

28499

+ vector long long vler = {2, 1};

28500

+ vector double vder = {0.0, 2.0};

28501

+#endif

28502

+

28503

+ check (vec_long_long_eq (vlr, vler), "vl");

28504

+ check (vec_dbl_eq (vdr, vder), "vd");

28505

+}

28506

Index: gcc/testsuite/gcc.dg/vmx/unpack.c

28507

===================================================================

28508

--- a/src/gcc/testsuite/gcc.dg/vmx/unpack.c (.../tags/gcc_4_8_2_release)

28509

+++ b/src/gcc/testsuite/gcc.dg/vmx/unpack.c (.../branches/gcc-4_8-branch)

28510

@@ -0,0 +1,67 @@

28511

+#include "harness.h"

28512

+

28513

+#define BIG 4294967295

28514

+

28515

+static void test()

28516

+{

28517

+ /* Input vectors. */

28518

+ vector signed char vsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};

28519

+ vector bool char vbc = {0,255,255,0,0,0,255,0,255,0,0,255,255,255,0,255};

28520

+ vector pixel vp = {(0<<15) + (1<<10) + (2<<5) + 3,

28521

+ (1<<15) + (4<<10) + (5<<5) + 6,

28522

+ (0<<15) + (7<<10) + (8<<5) + 9,

28523

+ (1<<15) + (10<<10) + (11<<5) + 12,

28524

+ (1<<15) + (13<<10) + (14<<5) + 15,

28525

+ (0<<15) + (16<<10) + (17<<5) + 18,

28526

+ (1<<15) + (19<<10) + (20<<5) + 21,

28527

+ (0<<15) + (22<<10) + (23<<5) + 24};

28528

+ vector signed short vss = {-4,-3,-2,-1,0,1,2,3};

28529

+ vector bool short vbs = {0,65535,65535,0,0,0,65535,0};

28530

+

28531

+ /* Result vectors. */

28532

+ vector signed short vsch, vscl;

28533

+ vector bool short vbsh, vbsl;

28534

+ vector unsigned int vuih, vuil;

28535

+ vector signed int vsih, vsil;

28536

+ vector bool int vbih, vbil;

28537

+

28538

+ /* Expected result vectors. */

28539

+ vector signed short vschr = {-8,-7,-6,-5,-4,-3,-2,-1};

28540

+ vector signed short vsclr = {0,1,2,3,4,5,6,7};

28541

+ vector bool short vbshr = {0,65535,65535,0,0,0,65535,0};

28542

+ vector bool short vbslr = {65535,0,0,65535,65535,65535,0,65535};

28543

+ vector unsigned int vuihr = {(0<<24) + (1<<16) + (2<<8) + 3,

28544

+ (65535<<24) + (4<<16) + (5<<8) + 6,

28545

+ (0<<24) + (7<<16) + (8<<8) + 9,

28546

+ (65535<<24) + (10<<16) + (11<<8) + 12};

28547

+ vector unsigned int vuilr = {(65535<<24) + (13<<16) + (14<<8) + 15,

28548

+ (0<<24) + (16<<16) + (17<<8) + 18,

28549

+ (65535<<24) + (19<<16) + (20<<8) + 21,

28550

+ (0<<24) + (22<<16) + (23<<8) + 24};

28551

+ vector signed int vsihr = {-4,-3,-2,-1};

28552

+ vector signed int vsilr = {0,1,2,3};

28553

+ vector bool int vbihr = {0,BIG,BIG,0};

28554

+ vector bool int vbilr = {0,0,BIG,0};

28555

+

28556

+ vsch = vec_unpackh (vsc);

28557

+ vscl = vec_unpackl (vsc);

28558

+ vbsh = vec_unpackh (vbc);

28559

+ vbsl = vec_unpackl (vbc);

28560

+ vuih = vec_unpackh (vp);

28561

+ vuil = vec_unpackl (vp);

28562

+ vsih = vec_unpackh (vss);

28563

+ vsil = vec_unpackl (vss);

28564

+ vbih = vec_unpackh (vbs);

28565

+ vbil = vec_unpackl (vbs);

28566

+

28567

+ check (vec_all_eq (vsch, vschr), "vsch");

28568

+ check (vec_all_eq (vscl, vsclr), "vscl");

28569

+ check (vec_all_eq (vbsh, vbshr), "vbsh");

28570

+ check (vec_all_eq (vbsl, vbslr), "vbsl");

28571

+ check (vec_all_eq (vuih, vuihr), "vuih");

28572

+ check (vec_all_eq (vuil, vuilr), "vuil");

28573

+ check (vec_all_eq (vsih, vsihr), "vsih");

28574

+ check (vec_all_eq (vsil, vsilr), "vsil");

28575

+ check (vec_all_eq (vbih, vbihr), "vbih");

28576

+ check (vec_all_eq (vbil, vbilr), "vbil");

28577

+}

28578

Index: gcc/testsuite/gcc.dg/vmx/splat.c

28579

===================================================================

28580

--- a/src/gcc/testsuite/gcc.dg/vmx/splat.c (.../tags/gcc_4_8_2_release)

28581

+++ b/src/gcc/testsuite/gcc.dg/vmx/splat.c (.../branches/gcc-4_8-branch)

28582

@@ -0,0 +1,47 @@

28583

+#include "harness.h"

28584

+

28585

+static void test()

28586

+{

28587

+ /* Input vectors. */

28588

+ vector unsigned char vuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

28589

+ vector signed char vsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};

28590

+ vector unsigned short vus = {0,1,2,3,4,5,6,7};

28591

+ vector signed short vss = {-4,-3,-2,-1,0,1,2,3};

28592

+ vector unsigned int vui = {0,1,2,3};

28593

+ vector signed int vsi = {-2,-1,0,1};

28594

+ vector float vf = {-2.0,-1.0,0.0,1.0};

28595

+

28596

+ /* Result vectors. */

28597

+ vector unsigned char vucr;

28598

+ vector signed char vscr;

28599

+ vector unsigned short vusr;

28600

+ vector signed short vssr;

28601

+ vector unsigned int vuir;

28602

+ vector signed int vsir;

28603

+ vector float vfr;

28604

+

28605

+ /* Expected result vectors. */

28606

+ vector unsigned char vucer = {1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1};

28607

+ vector signed char vscer = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};

28608

+ vector unsigned short vuser = {7,7,7,7,7,7,7,7};

28609

+ vector signed short vsser = {-4,-4,-4,-4,-4,-4,-4,-4};

28610

+ vector unsigned int vuier = {2,2,2,2};

28611

+ vector signed int vsier = {1,1,1,1};

28612

+ vector float vfer = {-1.0,-1.0,-1.0,-1.0};

28613

+

28614

+ vucr = vec_splat (vuc, 1);

28615

+ vscr = vec_splat (vsc, 8);

28616

+ vusr = vec_splat (vus, 7);

28617

+ vssr = vec_splat (vss, 0);

28618

+ vuir = vec_splat (vui, 2);

28619

+ vsir = vec_splat (vsi, 3);

28620

+ vfr = vec_splat (vf, 1);

28621

+

28622

+ check (vec_all_eq (vucr, vucer), "vuc");

28623

+ check (vec_all_eq (vscr, vscer), "vsc");

28624

+ check (vec_all_eq (vusr, vuser), "vus");

28625

+ check (vec_all_eq (vssr, vsser), "vss");

28626

+ check (vec_all_eq (vuir, vuier), "vui");

28627

+ check (vec_all_eq (vsir, vsier), "vsi");

28628

+ check (vec_all_eq (vfr, vfer ), "vf");

28629

+}

28630

Index: gcc/testsuite/gcc.dg/vmx/ldl-vsx-be-order.c

28631

===================================================================

28632

--- a/src/gcc/testsuite/gcc.dg/vmx/ldl-vsx-be-order.c (.../tags/gcc_4_8_2_release)

28633

+++ b/src/gcc/testsuite/gcc.dg/vmx/ldl-vsx-be-order.c (.../branches/gcc-4_8-branch)

28634

@@ -0,0 +1,44 @@

28635

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

28636

+/* { dg-require-effective-target powerpc_vsx_ok } */

28637

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mvsx" } */

28638

+

28639

+#include "harness.h"

28640

+

28641

+static unsigned long long svul[2] __attribute__ ((aligned (16)));

28642

+static double svd[2] __attribute__ ((aligned (16)));

28643

+

28644

+static void init ()

28645

+{

28646

+ unsigned int i;

28647

+ for (i = 0; i < 2; ++i)

28648

+ {

28649

+ svul[i] = i;

28650

+ svd[i] = i * 1.0;

28651

+ }

28652

+}

28653

+

28654

+static void test ()

28655

+{

28656

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

28657

+ vector unsigned long long evul = {1,0};

28658

+ vector double evd = {1.0,0.0};

28659

+#else

28660

+ vector unsigned long long evul = {0,1};

28661

+ vector double evd = {0.0,1.0};

28662

+#endif

28663

+

28664

+ vector unsigned long long vul;

28665

+ vector double vd;

28666

+ unsigned i;

28667

+

28668

+ init ();

28669

+

28670

+ vul = vec_ldl (0, (vector unsigned long long *)svul);

28671

+ vd = vec_ldl (0, (vector double *)svd);

28672

+

28673

+ for (i = 0; i < 2; ++i)

28674

+ {

28675

+ check (vul[i] == evul[i], "vul");

28676

+ check (vd[i] == evd[i], "vd" );

28677

+ }

28678

+}

28679

Index: gcc/testsuite/gcc.dg/vmx/merge-be-order.c

28680

===================================================================

28681

--- a/src/gcc/testsuite/gcc.dg/vmx/merge-be-order.c (.../tags/gcc_4_8_2_release)

28682

+++ b/src/gcc/testsuite/gcc.dg/vmx/merge-be-order.c (.../branches/gcc-4_8-branch)

28683

@@ -0,0 +1,96 @@

28684

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */

28685

+

28686

+#include "harness.h"

28687

+

28688

+static void test()

28689

+{

28690

+ /* Input vectors. */

28691

+ vector unsigned char vuca = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

28692

+ vector unsigned char vucb

28693

+ = {16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31};

28694

+ vector signed char vsca

28695

+ = {-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1};

28696

+ vector signed char vscb = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

28697

+ vector unsigned short vusa = {0,1,2,3,4,5,6,7};

28698

+ vector unsigned short vusb = {8,9,10,11,12,13,14,15};

28699

+ vector signed short vssa = {-8,-7,-6,-5,-4,-3,-2,-1};

28700

+ vector signed short vssb = {0,1,2,3,4,5,6,7};

28701

+ vector unsigned int vuia = {0,1,2,3};

28702

+ vector unsigned int vuib = {4,5,6,7};

28703

+ vector signed int vsia = {-4,-3,-2,-1};

28704

+ vector signed int vsib = {0,1,2,3};

28705

+ vector float vfa = {-4.0,-3.0,-2.0,-1.0};

28706

+ vector float vfb = {0.0,1.0,2.0,3.0};

28707

+

28708

+ /* Result vectors. */

28709

+ vector unsigned char vuch, vucl;

28710

+ vector signed char vsch, vscl;

28711

+ vector unsigned short vush, vusl;

28712

+ vector signed short vssh, vssl;

28713

+ vector unsigned int vuih, vuil;

28714

+ vector signed int vsih, vsil;

28715

+ vector float vfh, vfl;

28716

+

28717

+ /* Expected result vectors. */

28718

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

28719

+ vector unsigned char vucrh = {24,8,25,9,26,10,27,11,28,12,29,13,30,14,31,15};

28720

+ vector unsigned char vucrl = {16,0,17,1,18,2,19,3,20,4,21,5,22,6,23,7};

28721

+ vector signed char vscrh = {8,-8,9,-7,10,-6,11,-5,12,-4,13,-3,14,-2,15,-1};

28722

+ vector signed char vscrl = {0,-16,1,-15,2,-14,3,-13,4,-12,5,-11,6,-10,7,-9};

28723

+ vector unsigned short vusrh = {12,4,13,5,14,6,15,7};

28724

+ vector unsigned short vusrl = {8,0,9,1,10,2,11,3};

28725

+ vector signed short vssrh = {4,-4,5,-3,6,-2,7,-1};

28726

+ vector signed short vssrl = {0,-8,1,-7,2,-6,3,-5};

28727

+ vector unsigned int vuirh = {6,2,7,3};

28728

+ vector unsigned int vuirl = {4,0,5,1};

28729

+ vector signed int vsirh = {2,-2,3,-1};

28730

+ vector signed int vsirl = {0,-4,1,-3};

28731

+ vector float vfrh = {2.0,-2.0,3.0,-1.0};

28732

+ vector float vfrl = {0.0,-4.0,1.0,-3.0};

28733

+#else

28734

+ vector unsigned char vucrh = {0,16,1,17,2,18,3,19,4,20,5,21,6,22,7,23};

28735

+ vector unsigned char vucrl = {8,24,9,25,10,26,11,27,12,28,13,29,14,30,15,31};

28736

+ vector signed char vscrh = {-16,0,-15,1,-14,2,-13,3,-12,4,-11,5,-10,6,-9,7};

28737

+ vector signed char vscrl = {-8,8,-7,9,-6,10,-5,11,-4,12,-3,13,-2,14,-1,15};

28738

+ vector unsigned short vusrh = {0,8,1,9,2,10,3,11};

28739

+ vector unsigned short vusrl = {4,12,5,13,6,14,7,15};

28740

+ vector signed short vssrh = {-8,0,-7,1,-6,2,-5,3};

28741

+ vector signed short vssrl = {-4,4,-3,5,-2,6,-1,7};

28742

+ vector unsigned int vuirh = {0,4,1,5};

28743

+ vector unsigned int vuirl = {2,6,3,7};

28744

+ vector signed int vsirh = {-4,0,-3,1};

28745

+ vector signed int vsirl = {-2,2,-1,3};

28746

+ vector float vfrh = {-4.0,0.0,-3.0,1.0};

28747

+ vector float vfrl = {-2.0,2.0,-1.0,3.0};

28748

+#endif

28749

+

28750

+ vuch = vec_mergeh (vuca, vucb);

28751

+ vucl = vec_mergel (vuca, vucb);

28752

+ vsch = vec_mergeh (vsca, vscb);

28753

+ vscl = vec_mergel (vsca, vscb);

28754

+ vush = vec_mergeh (vusa, vusb);

28755

+ vusl = vec_mergel (vusa, vusb);

28756

+ vssh = vec_mergeh (vssa, vssb);

28757

+ vssl = vec_mergel (vssa, vssb);

28758

+ vuih = vec_mergeh (vuia, vuib);

28759

+ vuil = vec_mergel (vuia, vuib);

28760

+ vsih = vec_mergeh (vsia, vsib);

28761

+ vsil = vec_mergel (vsia, vsib);

28762

+ vfh = vec_mergeh (vfa, vfb );

28763

+ vfl = vec_mergel (vfa, vfb );

28764

+

28765

+ check (vec_all_eq (vuch, vucrh), "vuch");

28766

+ check (vec_all_eq (vucl, vucrl), "vucl");

28767

+ check (vec_all_eq (vsch, vscrh), "vsch");

28768

+ check (vec_all_eq (vscl, vscrl), "vscl");

28769

+ check (vec_all_eq (vush, vusrh), "vush");

28770

+ check (vec_all_eq (vusl, vusrl), "vusl");

28771

+ check (vec_all_eq (vssh, vssrh), "vssh");

28772

+ check (vec_all_eq (vssl, vssrl), "vssl");

28773

+ check (vec_all_eq (vuih, vuirh), "vuih");

28774

+ check (vec_all_eq (vuil, vuirl), "vuil");

28775

+ check (vec_all_eq (vsih, vsirh), "vsih");

28776

+ check (vec_all_eq (vsil, vsirl), "vsil");

28777

+ check (vec_all_eq (vfh, vfrh), "vfh");

28778

+ check (vec_all_eq (vfl, vfrl), "vfl");

28779

+}

28780

Index: gcc/testsuite/gcc.dg/vmx/splat-vsx-be-order.c

28781

===================================================================

28782

--- a/src/gcc/testsuite/gcc.dg/vmx/splat-vsx-be-order.c (.../tags/gcc_4_8_2_release)

28783

+++ b/src/gcc/testsuite/gcc.dg/vmx/splat-vsx-be-order.c (.../branches/gcc-4_8-branch)

28784

@@ -0,0 +1,37 @@

28785

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

28786

+/* { dg-require-effective-target powerpc_vsx_ok } */

28787

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mvsx" } */

28788

+

28789

+#include "harness.h"

28790

+

28791

+static void test()

28792

+{

28793

+ /* Input vectors. */

28794

+ vector unsigned int vui = {0,1,2,3};

28795

+ vector signed int vsi = {-2,-1,0,1};

28796

+ vector float vf = {-2.0,-1.0,0.0,1.0};

28797

+

28798

+ /* Result vectors. */

28799

+ vector unsigned int vuir;

28800

+ vector signed int vsir;

28801

+ vector float vfr;

28802

+

28803

+ /* Expected result vectors. */

28804

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

28805

+ vector unsigned int vuier = {1,1,1,1};

28806

+ vector signed int vsier = {-2,-2,-2,-2};

28807

+ vector float vfer = {0.0,0.0,0.0,0.0};

28808

+#else

28809

+ vector unsigned int vuier = {2,2,2,2};

28810

+ vector signed int vsier = {1,1,1,1};

28811

+ vector float vfer = {-1.0,-1.0,-1.0,-1.0};

28812

+#endif

28813

+

28814

+ vuir = vec_splat (vui, 2);

28815

+ vsir = vec_splat (vsi, 3);

28816

+ vfr = vec_splat (vf, 1);

28817

+

28818

+ check (vec_all_eq (vuir, vuier), "vui");

28819

+ check (vec_all_eq (vsir, vsier), "vsi");

28820

+ check (vec_all_eq (vfr, vfer ), "vf");

28821

+}

28822

Index: gcc/testsuite/gcc.dg/vmx/merge.c

28823

===================================================================

28824

--- a/src/gcc/testsuite/gcc.dg/vmx/merge.c (.../tags/gcc_4_8_2_release)

28825

+++ b/src/gcc/testsuite/gcc.dg/vmx/merge.c (.../branches/gcc-4_8-branch)

28826

@@ -0,0 +1,77 @@

28827

+#include "harness.h"

28828

+

28829

+static void test()

28830

+{

28831

+ /* Input vectors. */

28832

+ vector unsigned char vuca = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

28833

+ vector unsigned char vucb

28834

+ = {16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31};

28835

+ vector signed char vsca

28836

+ = {-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1};

28837

+ vector signed char vscb = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

28838

+ vector unsigned short vusa = {0,1,2,3,4,5,6,7};

28839

+ vector unsigned short vusb = {8,9,10,11,12,13,14,15};

28840

+ vector signed short vssa = {-8,-7,-6,-5,-4,-3,-2,-1};

28841

+ vector signed short vssb = {0,1,2,3,4,5,6,7};

28842

+ vector unsigned int vuia = {0,1,2,3};

28843

+ vector unsigned int vuib = {4,5,6,7};

28844

+ vector signed int vsia = {-4,-3,-2,-1};

28845

+ vector signed int vsib = {0,1,2,3};

28846

+ vector float vfa = {-4.0,-3.0,-2.0,-1.0};

28847

+ vector float vfb = {0.0,1.0,2.0,3.0};

28848

+

28849

+ /* Result vectors. */

28850

+ vector unsigned char vuch, vucl;

28851

+ vector signed char vsch, vscl;

28852

+ vector unsigned short vush, vusl;

28853

+ vector signed short vssh, vssl;

28854

+ vector unsigned int vuih, vuil;

28855

+ vector signed int vsih, vsil;

28856

+ vector float vfh, vfl;

28857

+

28858

+ /* Expected result vectors. */

28859

+ vector unsigned char vucrh = {0,16,1,17,2,18,3,19,4,20,5,21,6,22,7,23};

28860

+ vector unsigned char vucrl = {8,24,9,25,10,26,11,27,12,28,13,29,14,30,15,31};

28861

+ vector signed char vscrh = {-16,0,-15,1,-14,2,-13,3,-12,4,-11,5,-10,6,-9,7};

28862

+ vector signed char vscrl = {-8,8,-7,9,-6,10,-5,11,-4,12,-3,13,-2,14,-1,15};

28863

+ vector unsigned short vusrh = {0,8,1,9,2,10,3,11};

28864

+ vector unsigned short vusrl = {4,12,5,13,6,14,7,15};

28865

+ vector signed short vssrh = {-8,0,-7,1,-6,2,-5,3};

28866

+ vector signed short vssrl = {-4,4,-3,5,-2,6,-1,7};

28867

+ vector unsigned int vuirh = {0,4,1,5};

28868

+ vector unsigned int vuirl = {2,6,3,7};

28869

+ vector signed int vsirh = {-4,0,-3,1};

28870

+ vector signed int vsirl = {-2,2,-1,3};

28871

+ vector float vfrh = {-4.0,0.0,-3.0,1.0};

28872

+ vector float vfrl = {-2.0,2.0,-1.0,3.0};

28873

+

28874

+ vuch = vec_mergeh (vuca, vucb);

28875

+ vucl = vec_mergel (vuca, vucb);

28876

+ vsch = vec_mergeh (vsca, vscb);

28877

+ vscl = vec_mergel (vsca, vscb);

28878

+ vush = vec_mergeh (vusa, vusb);

28879

+ vusl = vec_mergel (vusa, vusb);

28880

+ vssh = vec_mergeh (vssa, vssb);

28881

+ vssl = vec_mergel (vssa, vssb);

28882

+ vuih = vec_mergeh (vuia, vuib);

28883

+ vuil = vec_mergel (vuia, vuib);

28884

+ vsih = vec_mergeh (vsia, vsib);

28885

+ vsil = vec_mergel (vsia, vsib);

28886

+ vfh = vec_mergeh (vfa, vfb );

28887

+ vfl = vec_mergel (vfa, vfb );

28888

+

28889

+ check (vec_all_eq (vuch, vucrh), "vuch");

28890

+ check (vec_all_eq (vucl, vucrl), "vucl");

28891

+ check (vec_all_eq (vsch, vscrh), "vsch");

28892

+ check (vec_all_eq (vscl, vscrl), "vscl");

28893

+ check (vec_all_eq (vush, vusrh), "vush");

28894

+ check (vec_all_eq (vusl, vusrl), "vusl");

28895

+ check (vec_all_eq (vssh, vssrh), "vssh");

28896

+ check (vec_all_eq (vssl, vssrl), "vssl");

28897

+ check (vec_all_eq (vuih, vuirh), "vuih");

28898

+ check (vec_all_eq (vuil, vuirl), "vuil");

28899

+ check (vec_all_eq (vsih, vsirh), "vsih");

28900

+ check (vec_all_eq (vsil, vsirl), "vsil");

28901

+ check (vec_all_eq (vfh, vfrh), "vfh");

28902

+ check (vec_all_eq (vfl, vfrl), "vfl");

28903

+}

28904

Index: gcc/testsuite/gcc.dg/vmx/vec-set.c

28905

===================================================================

28906

--- a/src/gcc/testsuite/gcc.dg/vmx/vec-set.c (.../tags/gcc_4_8_2_release)

28907

+++ b/src/gcc/testsuite/gcc.dg/vmx/vec-set.c (.../branches/gcc-4_8-branch)

28908

@@ -0,0 +1,14 @@

28909

+#include "harness.h"

28910

+

28911

+vector short

28912

+vec_set (short m)

28913

+{

28914

+ return (vector short){m, 0, 0, 0, 0, 0, 0, 0};

28915

+}

28916

+

28917

+static void test()

28918

+{

28919

+ check (vec_all_eq (vec_set (7),

28920

+ ((vector short){7, 0, 0, 0, 0, 0, 0, 0})),

28921

+ "vec_set");

28922

+}

28923

Index: gcc/testsuite/gcc.dg/vmx/ld-vsx-be-order.c

28924

===================================================================

28925

--- a/src/gcc/testsuite/gcc.dg/vmx/ld-vsx-be-order.c (.../tags/gcc_4_8_2_release)

28926

+++ b/src/gcc/testsuite/gcc.dg/vmx/ld-vsx-be-order.c (.../branches/gcc-4_8-branch)

28927

@@ -0,0 +1,44 @@

28928

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

28929

+/* { dg-require-effective-target powerpc_vsx_ok } */

28930

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mvsx" } */

28931

+

28932

+#include "harness.h"

28933

+

28934

+static unsigned long long svul[2] __attribute__ ((aligned (16)));

28935

+static double svd[2] __attribute__ ((aligned (16)));

28936

+

28937

+static void init ()

28938

+{

28939

+ unsigned int i;

28940

+ for (i = 0; i < 2; ++i)

28941

+ {

28942

+ svul[i] = i;

28943

+ svd[i] = i * 1.0;

28944

+ }

28945

+}

28946

+

28947

+static void test ()

28948

+{

28949

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

28950

+ vector unsigned long long evul = {1,0};

28951

+ vector double evd = {1.0,0.0};

28952

+#else

28953

+ vector unsigned long long evul = {0,1};

28954

+ vector double evd = {0.0,1.0};

28955

+#endif

28956

+

28957

+ vector unsigned long long vul;

28958

+ vector double vd;

28959

+ unsigned i;

28960

+

28961

+ init ();

28962

+

28963

+ vul = vec_ld (0, (vector unsigned long long *)svul);

28964

+ vd = vec_ld (0, (vector double *)svd);

28965

+

28966

+ for (i = 0; i < 2; ++i)

28967

+ {

28968

+ check (vul[i] == evul[i], "vul");

28969

+ check (vd[i] == evd[i], "vd" );

28970

+ }

28971

+}

28972

Index: gcc/testsuite/gcc.dg/vmx/extract.c

28973

===================================================================

28974

--- a/src/gcc/testsuite/gcc.dg/vmx/extract.c (.../tags/gcc_4_8_2_release)

28975

+++ b/src/gcc/testsuite/gcc.dg/vmx/extract.c (.../branches/gcc-4_8-branch)

28976

@@ -0,0 +1,21 @@

28977

+#include "harness.h"

28978

+

28979

+static void test()

28980

+{

28981

+ vector unsigned char va = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

28982

+ vector signed char vb = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};

28983

+ vector unsigned short vc = {0,1,2,3,4,5,6,7};

28984

+ vector signed short vd = {-4,-3,-2,-1,0,1,2,3};

28985

+ vector unsigned int ve = {0,1,2,3};

28986

+ vector signed int vf = {-2,-1,0,1};

28987

+ vector float vg = {-2.0f,-1.0f,0.0f,1.0f};

28988

+

28989

+ check (vec_extract (va, 5) == 5, "vec_extract (va, 5)");

28990

+ check (vec_extract (vb, 0) == -8, "vec_extract (vb, 0)");

28991

+ check (vec_extract (vc, 7) == 7, "vec_extract (vc, 7)");

28992

+ check (vec_extract (vd, 3) == -1, "vec_extract (vd, 3)");

28993

+ check (vec_extract (ve, 2) == 2, "vec_extract (ve, 2)");

28994

+ check (vec_extract (vf, 1) == -1, "vec_extract (vf, 1)");

28995

+ check (vec_extract (vg, 0) == -2.0f, "vec_extract (vg, 0)");

28996

+}

28997

+

28998

Index: gcc/testsuite/gcc.dg/vmx/pack-be-order.c

28999

===================================================================

29000

--- a/src/gcc/testsuite/gcc.dg/vmx/pack-be-order.c (.../tags/gcc_4_8_2_release)

29001

+++ b/src/gcc/testsuite/gcc.dg/vmx/pack-be-order.c (.../branches/gcc-4_8-branch)

29002

@@ -0,0 +1,136 @@

29003

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */

29004

+

29005

+#include "harness.h"

29006

+

29007

+#define BIG 4294967295

29008

+

29009

+static void test()

29010

+{

29011

+ /* Input vectors. */

29012

+ vector unsigned short vusa = {0,1,2,3,4,5,6,7};

29013

+ vector unsigned short vusb = {8,9,10,11,12,13,14,15};

29014

+ vector signed short vssa = {-8,-7,-6,-5,-4,-3,-2,-1};

29015

+ vector signed short vssb = {0,1,2,3,4,5,6,7};

29016

+ vector bool short vbsa = {0,65535,65535,0,0,0,65535,0};

29017

+ vector bool short vbsb = {65535,0,0,65535,65535,65535,0,65535};

29018

+ vector unsigned int vuia = {0,1,2,3};

29019

+ vector unsigned int vuib = {4,5,6,7};

29020

+ vector signed int vsia = {-4,-3,-2,-1};

29021

+ vector signed int vsib = {0,1,2,3};

29022

+ vector bool int vbia = {0,BIG,BIG,BIG};

29023

+ vector bool int vbib = {BIG,0,0,0};

29024

+ vector unsigned int vipa = {(0<<24) + (2<<19) + (3<<11) + (4<<3),

29025

+ (1<<24) + (5<<19) + (6<<11) + (7<<3),

29026

+ (0<<24) + (8<<19) + (9<<11) + (10<<3),

29027

+ (1<<24) + (11<<19) + (12<<11) + (13<<3)};

29028

+ vector unsigned int vipb = {(1<<24) + (14<<19) + (15<<11) + (16<<3),

29029

+ (0<<24) + (17<<19) + (18<<11) + (19<<3),

29030

+ (1<<24) + (20<<19) + (21<<11) + (22<<3),

29031

+ (0<<24) + (23<<19) + (24<<11) + (25<<3)};

29032

+ vector unsigned short vusc = {0,256,1,257,2,258,3,259};

29033

+ vector unsigned short vusd = {4,260,5,261,6,262,7,263};

29034

+ vector signed short vssc = {-1,-128,0,127,-2,-129,1,128};

29035

+ vector signed short vssd = {-3,-130,2,129,-4,-131,3,130};

29036

+ vector unsigned int vuic = {0,65536,1,65537};

29037

+ vector unsigned int vuid = {2,65538,3,65539};

29038

+ vector signed int vsic = {-1,-32768,0,32767};

29039

+ vector signed int vsid = {-2,-32769,1,32768};

29040

+

29041

+ /* Result vectors. */

29042

+ vector unsigned char vucr;

29043

+ vector signed char vscr;

29044

+ vector bool char vbcr;

29045

+ vector unsigned short vusr;

29046

+ vector signed short vssr;

29047

+ vector bool short vbsr;

29048

+ vector pixel vpr;

29049

+ vector unsigned char vucsr;

29050

+ vector signed char vscsr;

29051

+ vector unsigned short vussr;

29052

+ vector signed short vsssr;

29053

+ vector unsigned char vucsur1, vucsur2;

29054

+ vector unsigned short vussur1, vussur2;

29055

+

29056

+ /* Expected result vectors. */

29057

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

29058

+ vector unsigned char vucer = {8,9,10,11,12,13,14,15,0,1,2,3,4,5,6,7};

29059

+ vector signed char vscer = {0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1};

29060

+ vector bool char vbcer = {255,0,0,255,255,255,0,255,0,255,255,0,0,0,255,0};

29061

+ vector unsigned short vuser = {4,5,6,7,0,1,2,3};

29062

+ vector signed short vsser = {0,1,2,3,-4,-3,-2,-1};

29063

+ vector bool short vbser = {65535,0,0,0,0,65535,65535,65535};

29064

+ vector pixel vper = {(1<<15) + (14<<10) + (15<<5) + 16,

29065

+ (0<<15) + (17<<10) + (18<<5) + 19,

29066

+ (1<<15) + (20<<10) + (21<<5) + 22,

29067

+ (0<<15) + (23<<10) + (24<<5) + 25,

29068

+ (0<<15) + (2<<10) + (3<<5) + 4,

29069

+ (1<<15) + (5<<10) + (6<<5) + 7,

29070

+ (0<<15) + (8<<10) + (9<<5) + 10,

29071

+ (1<<15) + (11<<10) + (12<<5) + 13};

29072

+ vector unsigned char vucser = {4,255,5,255,6,255,7,255,0,255,1,255,2,255,3,255};

29073

+ vector signed char vscser = {-3,-128,2,127,-4,-128,3,127,

29074

+ -1,-128,0,127,-2,-128,1,127};

29075

+ vector unsigned short vusser = {2,65535,3,65535,0,65535,1,65535};

29076

+ vector signed short vssser = {-2,-32768,1,32767,-1,-32768,0,32767};

29077

+ vector unsigned char vucsuer1 = {4,255,5,255,6,255,7,255,0,255,1,255,2,255,3,255};

29078

+ vector unsigned char vucsuer2 = {0,0,2,129,0,0,3,130,0,0,0,127,0,0,1,128};

29079

+ vector unsigned short vussuer1 = {2,65535,3,65535,0,65535,1,65535};

29080

+ vector unsigned short vussuer2 = {0,0,1,32768,0,0,0,32767};

29081

+#else

29082

+ vector unsigned char vucer = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

29083

+ vector signed char vscer = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};

29084

+ vector bool char vbcer = {0,255,255,0,0,0,255,0,255,0,0,255,255,255,0,255};

29085

+ vector unsigned short vuser = {0,1,2,3,4,5,6,7};

29086

+ vector signed short vsser = {-4,-3,-2,-1,0,1,2,3};

29087

+ vector bool short vbser = {0,65535,65535,65535,65535,0,0,0};

29088

+ vector pixel vper = {(0<<15) + (2<<10) + (3<<5) + 4,

29089

+ (1<<15) + (5<<10) + (6<<5) + 7,

29090

+ (0<<15) + (8<<10) + (9<<5) + 10,

29091

+ (1<<15) + (11<<10) + (12<<5) + 13,

29092

+ (1<<15) + (14<<10) + (15<<5) + 16,

29093

+ (0<<15) + (17<<10) + (18<<5) + 19,

29094

+ (1<<15) + (20<<10) + (21<<5) + 22,

29095

+ (0<<15) + (23<<10) + (24<<5) + 25};

29096

+ vector unsigned char vucser = {0,255,1,255,2,255,3,255,4,255,5,255,6,255,7,255};

29097

+ vector signed char vscser = {-1,-128,0,127,-2,-128,1,127,

29098

+ -3,-128,2,127,-4,-128,3,127};

29099

+ vector unsigned short vusser = {0,65535,1,65535,2,65535,3,65535};

29100

+ vector signed short vssser = {-1,-32768,0,32767,-2,-32768,1,32767};

29101

+ vector unsigned char vucsuer1 = {0,255,1,255,2,255,3,255,4,255,5,255,6,255,7,255};

29102

+ vector unsigned char vucsuer2 = {0,0,0,127,0,0,1,128,0,0,2,129,0,0,3,130};

29103

+ vector unsigned short vussuer1 = {0,65535,1,65535,2,65535,3,65535};

29104

+ vector unsigned short vussuer2 = {0,0,0,32767,0,0,1,32768};

29105

+#endif

29106

+

29107

+ vucr = vec_pack (vusa, vusb);

29108

+ vscr = vec_pack (vssa, vssb);

29109

+ vbcr = vec_pack (vbsa, vbsb);

29110

+ vusr = vec_pack (vuia, vuib);

29111

+ vssr = vec_pack (vsia, vsib);

29112

+ vbsr = vec_pack (vbia, vbib);

29113

+ vpr = vec_packpx (vipa, vipb);

29114

+ vucsr = vec_packs (vusc, vusd);

29115

+ vscsr = vec_packs (vssc, vssd);

29116

+ vussr = vec_packs (vuic, vuid);

29117

+ vsssr = vec_packs (vsic, vsid);

29118

+ vucsur1 = vec_packsu (vusc, vusd);

29119

+ vucsur2 = vec_packsu (vssc, vssd);

29120

+ vussur1 = vec_packsu (vuic, vuid);

29121

+ vussur2 = vec_packsu (vsic, vsid);

29122

+

29123

+ check (vec_all_eq (vucr, vucer), "vucr");

29124

+ check (vec_all_eq (vscr, vscer), "vscr");

29125

+ check (vec_all_eq (vbcr, vbcer), "vbcr");

29126

+ check (vec_all_eq (vusr, vuser), "vusr");

29127

+ check (vec_all_eq (vssr, vsser), "vssr");

29128

+ check (vec_all_eq (vbsr, vbser), "vbsr");

29129

+ check (vec_all_eq (vpr, vper ), "vpr" );

29130

+ check (vec_all_eq (vucsr, vucser), "vucsr");

29131

+ check (vec_all_eq (vscsr, vscser), "vscsr");

29132

+ check (vec_all_eq (vussr, vusser), "vussr");

29133

+ check (vec_all_eq (vsssr, vssser), "vsssr");

29134

+ check (vec_all_eq (vucsur1, vucsuer1), "vucsur1");

29135

+ check (vec_all_eq (vucsur2, vucsuer2), "vucsur2");

29136

+ check (vec_all_eq (vussur1, vussuer1), "vussur1");

29137

+ check (vec_all_eq (vussur2, vussuer2), "vussur2");

29138

+}

29139

Index: gcc/testsuite/gcc.dg/vmx/st-be-order.c

29140

===================================================================

29141

--- a/src/gcc/testsuite/gcc.dg/vmx/st-be-order.c (.../tags/gcc_4_8_2_release)

29142

+++ b/src/gcc/testsuite/gcc.dg/vmx/st-be-order.c (.../branches/gcc-4_8-branch)

29143

@@ -0,0 +1,83 @@

29144

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */

29145

+

29146

+#include "harness.h"

29147

+

29148

+static unsigned char svuc[16] __attribute__ ((aligned (16)));

29149

+static signed char svsc[16] __attribute__ ((aligned (16)));

29150

+static unsigned char svbc[16] __attribute__ ((aligned (16)));

29151

+static unsigned short svus[8] __attribute__ ((aligned (16)));

29152

+static signed short svss[8] __attribute__ ((aligned (16)));

29153

+static unsigned short svbs[8] __attribute__ ((aligned (16)));

29154

+static unsigned short svp[8] __attribute__ ((aligned (16)));

29155

+static unsigned int svui[4] __attribute__ ((aligned (16)));

29156

+static signed int svsi[4] __attribute__ ((aligned (16)));

29157

+static unsigned int svbi[4] __attribute__ ((aligned (16)));

29158

+static float svf[4] __attribute__ ((aligned (16)));

29159

+

29160

+static void check_arrays ()

29161

+{

29162

+ unsigned int i;

29163

+ for (i = 0; i < 16; ++i)

29164

+ {

29165

+ check (svuc[i] == i, "svuc");

29166

+ check (svsc[i] == i - 8, "svsc");

29167

+ check (svbc[i] == ((i % 2) ? 0xff : 0), "svbc");

29168

+ }

29169

+ for (i = 0; i < 8; ++i)

29170

+ {

29171

+ check (svus[i] == i, "svus");

29172

+ check (svss[i] == i - 4, "svss");

29173

+ check (svbs[i] == ((i % 2) ? 0xffff : 0), "svbs");

29174

+ check (svp[i] == i, "svp");

29175

+ }

29176

+ for (i = 0; i < 4; ++i)

29177

+ {

29178

+ check (svui[i] == i, "svui");

29179

+ check (svsi[i] == i - 2, "svsi");

29180

+ check (svbi[i] == ((i % 2) ? 0xffffffff : 0), "svbi");

29181

+ check (svf[i] == i * 1.0f, "svf");

29182

+ }

29183

+}

29184

+

29185

+static void test ()

29186

+{

29187

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

29188

+ vector unsigned char vuc = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};

29189

+ vector signed char vsc = {7,6,5,4,3,2,1,0,-1,-2,-3,-4,-5,-6,-7,-8};

29190

+ vector bool char vbc = {255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0};

29191

+ vector unsigned short vus = {7,6,5,4,3,2,1,0};

29192

+ vector signed short vss = {3,2,1,0,-1,-2,-3,-4};

29193

+ vector bool short vbs = {65535,0,65535,0,65535,0,65535,0};

29194

+ vector pixel vp = {7,6,5,4,3,2,1,0};

29195

+ vector unsigned int vui = {3,2,1,0};

29196

+ vector signed int vsi = {1,0,-1,-2};

29197

+ vector bool int vbi = {0xffffffff,0,0xffffffff,0};

29198

+ vector float vf = {3.0,2.0,1.0,0.0};

29199

+#else

29200

+ vector unsigned char vuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

29201

+ vector signed char vsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};

29202

+ vector bool char vbc = {0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255};

29203

+ vector unsigned short vus = {0,1,2,3,4,5,6,7};

29204

+ vector signed short vss = {-4,-3,-2,-1,0,1,2,3};

29205

+ vector bool short vbs = {0,65535,0,65535,0,65535,0,65535};

29206

+ vector pixel vp = {0,1,2,3,4,5,6,7};

29207

+ vector unsigned int vui = {0,1,2,3};

29208

+ vector signed int vsi = {-2,-1,0,1};

29209

+ vector bool int vbi = {0,0xffffffff,0,0xffffffff};

29210

+ vector float vf = {0.0,1.0,2.0,3.0};

29211

+#endif

29212

+

29213

+ vec_st (vuc, 0, (vector unsigned char *)svuc);

29214

+ vec_st (vsc, 0, (vector signed char *)svsc);

29215

+ vec_st (vbc, 0, (vector bool char *)svbc);

29216

+ vec_st (vus, 0, (vector unsigned short *)svus);

29217

+ vec_st (vss, 0, (vector signed short *)svss);

29218

+ vec_st (vbs, 0, (vector bool short *)svbs);

29219

+ vec_st (vp, 0, (vector pixel *)svp);

29220

+ vec_st (vui, 0, (vector unsigned int *)svui);

29221

+ vec_st (vsi, 0, (vector signed int *)svsi);

29222

+ vec_st (vbi, 0, (vector bool int *)svbi);

29223

+ vec_st (vf, 0, (vector float *)svf);

29224

+

29225

+ check_arrays ();

29226

+}

29227

Index: gcc/testsuite/gcc.dg/vmx/gcc-bug-i.c

29228

===================================================================

29229

--- a/src/gcc/testsuite/gcc.dg/vmx/gcc-bug-i.c (.../tags/gcc_4_8_2_release)

29230

+++ b/src/gcc/testsuite/gcc.dg/vmx/gcc-bug-i.c (.../branches/gcc-4_8-branch)

29231

@@ -13,6 +13,20 @@

29232

#define DO_INLINE __attribute__ ((always_inline))

29233

#define DONT_INLINE __attribute__ ((noinline))

29234

29235

+#ifdef __LITTLE_ENDIAN__

29236

+static inline DO_INLINE int inline_me(vector signed short data)

29237

+{

29238

+ union {vector signed short v; signed short s[8];} u;

29239

+ signed short x;

29240

+ unsigned char x1, x2;

29241

+

29242

+ u.v = data;

29243

+ x = u.s[7];

29244

+ x1 = (x >> 8) & 0xff;

29245

+ x2 = x & 0xff;

29246

+ return ((x2 << 8) | x1);

29247

+}

29248

+#else

29249

static inline DO_INLINE int inline_me(vector signed short data)

29250

{

29251

union {vector signed short v; signed short s[8];} u;

29252

@@ -19,6 +33,7 @@

29253

u.v = data;

29254

return u.s[7];

29255

}

29256

+#endif

29257

29258

static DONT_INLINE int foo(vector signed short data)

29259

{

29260

Index: gcc/testsuite/gcc.dg/vmx/eg-5.c

29261

===================================================================

29262

--- a/src/gcc/testsuite/gcc.dg/vmx/eg-5.c (.../tags/gcc_4_8_2_release)

29263

+++ b/src/gcc/testsuite/gcc.dg/vmx/eg-5.c (.../branches/gcc-4_8-branch)

29264

@@ -6,12 +6,10 @@

29265

{

29266

/* Set result to a vector of f32 0's */

29267

vector float result = ((vector float){0.,0.,0.,0.});

29268

-

29269

result = vec_madd (c0, vec_splat (v, 0), result);

29270

result = vec_madd (c1, vec_splat (v, 1), result);

29271

result = vec_madd (c2, vec_splat (v, 2), result);

29272

result = vec_madd (c3, vec_splat (v, 3), result);

29273

-

29274

return result;

29275

}

29276

29277

Index: gcc/testsuite/gcc.dg/vmx/st-vsx-be-order.c

29278

===================================================================

29279

--- a/src/gcc/testsuite/gcc.dg/vmx/st-vsx-be-order.c (.../tags/gcc_4_8_2_release)

29280

+++ b/src/gcc/testsuite/gcc.dg/vmx/st-vsx-be-order.c (.../branches/gcc-4_8-branch)

29281

@@ -0,0 +1,34 @@

29282

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

29283

+/* { dg-require-effective-target powerpc_vsx_ok } */

29284

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mvsx" } */

29285

+

29286

+#include "harness.h"

29287

+

29288

+static unsigned long long svul[2] __attribute__ ((aligned (16)));

29289

+static double svd[2] __attribute__ ((aligned (16)));

29290

+

29291

+static void check_arrays ()

29292

+{

29293

+ unsigned int i;

29294

+ for (i = 0; i < 2; ++i)

29295

+ {

29296

+ check (svul[i] == i, "svul");

29297

+ check (svd[i] == i * 1.0, "svd");

29298

+ }

29299

+}

29300

+

29301

+static void test ()

29302

+{

29303

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

29304

+ vector unsigned long long vul = {1,0};

29305

+ vector double vd = {1.0,0.0};

29306

+#else

29307

+ vector unsigned long long vul = {0,1};

29308

+ vector double vd = {0.0,1.0};

29309

+#endif

29310

+

29311

+ vec_st (vul, 0, (vector unsigned long long *)svul);

29312

+ vec_st (vd, 0, (vector double *)svd);

29313

+

29314

+ check_arrays ();

29315

+}

29316

Index: gcc/testsuite/gcc.dg/vmx/lde.c

29317

===================================================================

29318

--- a/src/gcc/testsuite/gcc.dg/vmx/lde.c (.../tags/gcc_4_8_2_release)

29319

+++ b/src/gcc/testsuite/gcc.dg/vmx/lde.c (.../branches/gcc-4_8-branch)

29320

@@ -0,0 +1,59 @@

29321

+#include "harness.h"

29322

+

29323

+static unsigned char svuc[16] __attribute__ ((aligned (16)));

29324

+static signed char svsc[16] __attribute__ ((aligned (16)));

29325

+static unsigned short svus[8] __attribute__ ((aligned (16)));

29326

+static signed short svss[8] __attribute__ ((aligned (16)));

29327

+static unsigned int svui[4] __attribute__ ((aligned (16)));

29328

+static signed int svsi[4] __attribute__ ((aligned (16)));

29329

+static float svf[4] __attribute__ ((aligned (16)));

29330

+

29331

+static void init ()

29332

+{

29333

+ unsigned int i;

29334

+ for (i = 0; i < 16; ++i)

29335

+ {

29336

+ svuc[i] = i;

29337

+ svsc[i] = i - 8;

29338

+ }

29339

+ for (i = 0; i < 8; ++i)

29340

+ {

29341

+ svus[i] = i;

29342

+ svss[i] = i - 4;

29343

+ }

29344

+ for (i = 0; i < 4; ++i)

29345

+ {

29346

+ svui[i] = i;

29347

+ svsi[i] = i - 2;

29348

+ svf[i] = i * 1.0f;

29349

+ }

29350

+}

29351

+

29352

+static void test ()

29353

+{

29354

+ vector unsigned char vuc;

29355

+ vector signed char vsc;

29356

+ vector unsigned short vus;

29357

+ vector signed short vss;

29358

+ vector unsigned int vui;

29359

+ vector signed int vsi;

29360

+ vector float vf;

29361

+

29362

+ init ();

29363

+

29364

+ vuc = vec_lde (9*1, (unsigned char *)svuc);

29365

+ vsc = vec_lde (14*1, (signed char *)svsc);

29366

+ vus = vec_lde (7*2, (unsigned short *)svus);

29367

+ vss = vec_lde (1*2, (signed short *)svss);

29368

+ vui = vec_lde (3*4, (unsigned int *)svui);

29369

+ vsi = vec_lde (2*4, (signed int *)svsi);

29370

+ vf = vec_lde (0*4, (float *)svf);

29371

+

29372

+ check (vec_extract (vuc, 9) == 9, "vuc");

29373

+ check (vec_extract (vsc, 14) == 6, "vsc");

29374

+ check (vec_extract (vus, 7) == 7, "vus");

29375

+ check (vec_extract (vss, 1) == -3, "vss");

29376

+ check (vec_extract (vui, 3) == 3, "vui");

29377

+ check (vec_extract (vsi, 2) == 0, "vsi");

29378

+ check (vec_extract (vf, 0) == 0.0, "vf");

29379

+}

29380

Index: gcc/testsuite/gcc.dg/vmx/pack.c

29381

===================================================================

29382

--- a/src/gcc/testsuite/gcc.dg/vmx/pack.c (.../tags/gcc_4_8_2_release)

29383

+++ b/src/gcc/testsuite/gcc.dg/vmx/pack.c (.../branches/gcc-4_8-branch)

29384

@@ -0,0 +1,108 @@

29385

+#include "harness.h"

29386

+

29387

+#define BIG 4294967295

29388

+

29389

+static void test()

29390

+{

29391

+ /* Input vectors. */

29392

+ vector unsigned short vusa = {0,1,2,3,4,5,6,7};

29393

+ vector unsigned short vusb = {8,9,10,11,12,13,14,15};

29394

+ vector signed short vssa = {-8,-7,-6,-5,-4,-3,-2,-1};

29395

+ vector signed short vssb = {0,1,2,3,4,5,6,7};

29396

+ vector bool short vbsa = {0,65535,65535,0,0,0,65535,0};

29397

+ vector bool short vbsb = {65535,0,0,65535,65535,65535,0,65535};

29398

+ vector unsigned int vuia = {0,1,2,3};

29399

+ vector unsigned int vuib = {4,5,6,7};

29400

+ vector signed int vsia = {-4,-3,-2,-1};

29401

+ vector signed int vsib = {0,1,2,3};

29402

+ vector bool int vbia = {0,BIG,BIG,BIG};

29403

+ vector bool int vbib = {BIG,0,0,0};

29404

+ vector unsigned int vipa = {(0<<24) + (2<<19) + (3<<11) + (4<<3),

29405

+ (1<<24) + (5<<19) + (6<<11) + (7<<3),

29406

+ (0<<24) + (8<<19) + (9<<11) + (10<<3),

29407

+ (1<<24) + (11<<19) + (12<<11) + (13<<3)};

29408

+ vector unsigned int vipb = {(1<<24) + (14<<19) + (15<<11) + (16<<3),

29409

+ (0<<24) + (17<<19) + (18<<11) + (19<<3),

29410

+ (1<<24) + (20<<19) + (21<<11) + (22<<3),

29411

+ (0<<24) + (23<<19) + (24<<11) + (25<<3)};

29412

+ vector unsigned short vusc = {0,256,1,257,2,258,3,259};

29413

+ vector unsigned short vusd = {4,260,5,261,6,262,7,263};

29414

+ vector signed short vssc = {-1,-128,0,127,-2,-129,1,128};

29415

+ vector signed short vssd = {-3,-130,2,129,-4,-131,3,130};

29416

+ vector unsigned int vuic = {0,65536,1,65537};

29417

+ vector unsigned int vuid = {2,65538,3,65539};

29418

+ vector signed int vsic = {-1,-32768,0,32767};

29419

+ vector signed int vsid = {-2,-32769,1,32768};

29420

+

29421

+ /* Result vectors. */

29422

+ vector unsigned char vucr;

29423

+ vector signed char vscr;

29424

+ vector bool char vbcr;

29425

+ vector unsigned short vusr;

29426

+ vector signed short vssr;

29427

+ vector bool short vbsr;

29428

+ vector pixel vpr;

29429

+ vector unsigned char vucsr;

29430

+ vector signed char vscsr;

29431

+ vector unsigned short vussr;

29432

+ vector signed short vsssr;

29433

+ vector unsigned char vucsur1, vucsur2;

29434

+ vector unsigned short vussur1, vussur2;

29435

+

29436

+ /* Expected result vectors. */

29437

+ vector unsigned char vucer = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

29438

+ vector signed char vscer = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};

29439

+ vector bool char vbcer = {0,255,255,0,0,0,255,0,255,0,0,255,255,255,0,255};

29440

+ vector unsigned short vuser = {0,1,2,3,4,5,6,7};

29441

+ vector signed short vsser = {-4,-3,-2,-1,0,1,2,3};

29442

+ vector bool short vbser = {0,65535,65535,65535,65535,0,0,0};

29443

+ vector pixel vper = {(0<<15) + (2<<10) + (3<<5) + 4,

29444

+ (1<<15) + (5<<10) + (6<<5) + 7,

29445

+ (0<<15) + (8<<10) + (9<<5) + 10,

29446

+ (1<<15) + (11<<10) + (12<<5) + 13,

29447

+ (1<<15) + (14<<10) + (15<<5) + 16,

29448

+ (0<<15) + (17<<10) + (18<<5) + 19,

29449

+ (1<<15) + (20<<10) + (21<<5) + 22,

29450

+ (0<<15) + (23<<10) + (24<<5) + 25};

29451

+ vector unsigned char vucser = {0,255,1,255,2,255,3,255,4,255,5,255,6,255,7,255};

29452

+ vector signed char vscser = {-1,-128,0,127,-2,-128,1,127,

29453

+ -3,-128,2,127,-4,-128,3,127};

29454

+ vector unsigned short vusser = {0,65535,1,65535,2,65535,3,65535};

29455

+ vector signed short vssser = {-1,-32768,0,32767,-2,-32768,1,32767};

29456

+ vector unsigned char vucsuer1 = {0,255,1,255,2,255,3,255,4,255,5,255,6,255,7,255};

29457

+ vector unsigned char vucsuer2 = {0,0,0,127,0,0,1,128,0,0,2,129,0,0,3,130};

29458

+ vector unsigned short vussuer1 = {0,65535,1,65535,2,65535,3,65535};

29459

+ vector unsigned short vussuer2 = {0,0,0,32767,0,0,1,32768};

29460

+

29461

+ vucr = vec_pack (vusa, vusb);

29462

+ vscr = vec_pack (vssa, vssb);

29463

+ vbcr = vec_pack (vbsa, vbsb);

29464

+ vusr = vec_pack (vuia, vuib);

29465

+ vssr = vec_pack (vsia, vsib);

29466

+ vbsr = vec_pack (vbia, vbib);

29467

+ vpr = vec_packpx (vipa, vipb);

29468

+ vucsr = vec_packs (vusc, vusd);

29469

+ vscsr = vec_packs (vssc, vssd);

29470

+ vussr = vec_packs (vuic, vuid);

29471

+ vsssr = vec_packs (vsic, vsid);

29472

+ vucsur1 = vec_packsu (vusc, vusd);

29473

+ vucsur2 = vec_packsu (vssc, vssd);

29474

+ vussur1 = vec_packsu (vuic, vuid);

29475

+ vussur2 = vec_packsu (vsic, vsid);

29476

+

29477

+ check (vec_all_eq (vucr, vucer), "vucr");

29478

+ check (vec_all_eq (vscr, vscer), "vscr");

29479

+ check (vec_all_eq (vbcr, vbcer), "vbcr");

29480

+ check (vec_all_eq (vusr, vuser), "vusr");

29481

+ check (vec_all_eq (vssr, vsser), "vssr");

29482

+ check (vec_all_eq (vbsr, vbser), "vbsr");

29483

+ check (vec_all_eq (vpr, vper ), "vpr" );

29484

+ check (vec_all_eq (vucsr, vucser), "vucsr");

29485

+ check (vec_all_eq (vscsr, vscser), "vscsr");

29486

+ check (vec_all_eq (vussr, vusser), "vussr");

29487

+ check (vec_all_eq (vsssr, vssser), "vsssr");

29488

+ check (vec_all_eq (vucsur1, vucsuer1), "vucsur1");

29489

+ check (vec_all_eq (vucsur2, vucsuer2), "vucsur2");

29490

+ check (vec_all_eq (vussur1, vussuer1), "vussur1");

29491

+ check (vec_all_eq (vussur2, vussuer2), "vussur2");

29492

+}

29493

Index: gcc/testsuite/gcc.dg/vmx/unpack-be-order.c

29494

===================================================================

29495

--- a/src/gcc/testsuite/gcc.dg/vmx/unpack-be-order.c (.../tags/gcc_4_8_2_release)

29496

+++ b/src/gcc/testsuite/gcc.dg/vmx/unpack-be-order.c (.../branches/gcc-4_8-branch)

29497

@@ -0,0 +1,88 @@

29498

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */

29499

+

29500

+#include "harness.h"

29501

+

29502

+#define BIG 4294967295

29503

+

29504

+static void test()

29505

+{

29506

+ /* Input vectors. */

29507

+ vector signed char vsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};

29508

+ vector bool char vbc = {0,255,255,0,0,0,255,0,255,0,0,255,255,255,0,255};

29509

+ vector pixel vp = {(0<<15) + (1<<10) + (2<<5) + 3,

29510

+ (1<<15) + (4<<10) + (5<<5) + 6,

29511

+ (0<<15) + (7<<10) + (8<<5) + 9,

29512

+ (1<<15) + (10<<10) + (11<<5) + 12,

29513

+ (1<<15) + (13<<10) + (14<<5) + 15,

29514

+ (0<<15) + (16<<10) + (17<<5) + 18,

29515

+ (1<<15) + (19<<10) + (20<<5) + 21,

29516

+ (0<<15) + (22<<10) + (23<<5) + 24};

29517

+ vector signed short vss = {-4,-3,-2,-1,0,1,2,3};

29518

+ vector bool short vbs = {0,65535,65535,0,0,0,65535,0};

29519

+

29520

+ /* Result vectors. */

29521

+ vector signed short vsch, vscl;

29522

+ vector bool short vbsh, vbsl;

29523

+ vector unsigned int vuih, vuil;

29524

+ vector signed int vsih, vsil;

29525

+ vector bool int vbih, vbil;

29526

+

29527

+ /* Expected result vectors. */

29528

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

29529

+ vector signed short vschr = {0,1,2,3,4,5,6,7};

29530

+ vector signed short vsclr = {-8,-7,-6,-5,-4,-3,-2,-1};

29531

+ vector bool short vbshr = {65535,0,0,65535,65535,65535,0,65535};

29532

+ vector bool short vbslr = {0,65535,65535,0,0,0,65535,0};

29533

+ vector unsigned int vuihr = {(65535<<24) + (13<<16) + (14<<8) + 15,

29534

+ (0<<24) + (16<<16) + (17<<8) + 18,

29535

+ (65535<<24) + (19<<16) + (20<<8) + 21,

29536

+ (0<<24) + (22<<16) + (23<<8) + 24};

29537

+ vector unsigned int vuilr = {(0<<24) + (1<<16) + (2<<8) + 3,

29538

+ (65535<<24) + (4<<16) + (5<<8) + 6,

29539

+ (0<<24) + (7<<16) + (8<<8) + 9,

29540

+ (65535<<24) + (10<<16) + (11<<8) + 12};

29541

+ vector signed int vsihr = {0,1,2,3};

29542

+ vector signed int vsilr = {-4,-3,-2,-1};

29543

+ vector bool int vbihr = {0,0,BIG,0};

29544

+ vector bool int vbilr = {0,BIG,BIG,0};

29545

+#else

29546

+ vector signed short vschr = {-8,-7,-6,-5,-4,-3,-2,-1};

29547

+ vector signed short vsclr = {0,1,2,3,4,5,6,7};

29548

+ vector bool short vbshr = {0,65535,65535,0,0,0,65535,0};

29549

+ vector bool short vbslr = {65535,0,0,65535,65535,65535,0,65535};

29550

+ vector unsigned int vuihr = {(0<<24) + (1<<16) + (2<<8) + 3,

29551

+ (65535<<24) + (4<<16) + (5<<8) + 6,

29552

+ (0<<24) + (7<<16) + (8<<8) + 9,

29553

+ (65535<<24) + (10<<16) + (11<<8) + 12};

29554

+ vector unsigned int vuilr = {(65535<<24) + (13<<16) + (14<<8) + 15,

29555

+ (0<<24) + (16<<16) + (17<<8) + 18,

29556

+ (65535<<24) + (19<<16) + (20<<8) + 21,

29557

+ (0<<24) + (22<<16) + (23<<8) + 24};

29558

+ vector signed int vsihr = {-4,-3,-2,-1};

29559

+ vector signed int vsilr = {0,1,2,3};

29560

+ vector bool int vbihr = {0,BIG,BIG,0};

29561

+ vector bool int vbilr = {0,0,BIG,0};

29562

+#endif

29563

+

29564

+ vsch = vec_unpackh (vsc);

29565

+ vscl = vec_unpackl (vsc);

29566

+ vbsh = vec_unpackh (vbc);

29567

+ vbsl = vec_unpackl (vbc);

29568

+ vuih = vec_unpackh (vp);

29569

+ vuil = vec_unpackl (vp);

29570

+ vsih = vec_unpackh (vss);

29571

+ vsil = vec_unpackl (vss);

29572

+ vbih = vec_unpackh (vbs);

29573

+ vbil = vec_unpackl (vbs);

29574

+

29575

+ check (vec_all_eq (vsch, vschr), "vsch");

29576

+ check (vec_all_eq (vscl, vsclr), "vscl");

29577

+ check (vec_all_eq (vbsh, vbshr), "vbsh");

29578

+ check (vec_all_eq (vbsl, vbslr), "vbsl");

29579

+ check (vec_all_eq (vuih, vuihr), "vuih");

29580

+ check (vec_all_eq (vuil, vuilr), "vuil");

29581

+ check (vec_all_eq (vsih, vsihr), "vsih");

29582

+ check (vec_all_eq (vsil, vsilr), "vsil");

29583

+ check (vec_all_eq (vbih, vbihr), "vbih");

29584

+ check (vec_all_eq (vbil, vbilr), "vbil");

29585

+}

29586

Index: gcc/testsuite/gcc.dg/vmx/st.c

29587

===================================================================

29588

--- a/src/gcc/testsuite/gcc.dg/vmx/st.c (.../tags/gcc_4_8_2_release)

29589

+++ b/src/gcc/testsuite/gcc.dg/vmx/st.c (.../branches/gcc-4_8-branch)

29590

@@ -0,0 +1,67 @@

29591

+#include "harness.h"

29592

+

29593

+static unsigned char svuc[16] __attribute__ ((aligned (16)));

29594

+static signed char svsc[16] __attribute__ ((aligned (16)));

29595

+static unsigned char svbc[16] __attribute__ ((aligned (16)));

29596

+static unsigned short svus[8] __attribute__ ((aligned (16)));

29597

+static signed short svss[8] __attribute__ ((aligned (16)));

29598

+static unsigned short svbs[8] __attribute__ ((aligned (16)));

29599

+static unsigned short svp[8] __attribute__ ((aligned (16)));

29600

+static unsigned int svui[4] __attribute__ ((aligned (16)));

29601

+static signed int svsi[4] __attribute__ ((aligned (16)));

29602

+static unsigned int svbi[4] __attribute__ ((aligned (16)));

29603

+static float svf[4] __attribute__ ((aligned (16)));

29604

+

29605

+static void check_arrays ()

29606

+{

29607

+ unsigned int i;

29608

+ for (i = 0; i < 16; ++i)

29609

+ {

29610

+ check (svuc[i] == i, "svuc");

29611

+ check (svsc[i] == i - 8, "svsc");

29612

+ check (svbc[i] == ((i % 2) ? 0xff : 0), "svbc");

29613

+ }

29614

+ for (i = 0; i < 8; ++i)

29615

+ {

29616

+ check (svus[i] == i, "svus");

29617

+ check (svss[i] == i - 4, "svss");

29618

+ check (svbs[i] == ((i % 2) ? 0xffff : 0), "svbs");

29619

+ check (svp[i] == i, "svp");

29620

+ }

29621

+ for (i = 0; i < 4; ++i)

29622

+ {

29623

+ check (svui[i] == i, "svui");

29624

+ check (svsi[i] == i - 2, "svsi");

29625

+ check (svbi[i] == ((i % 2) ? 0xffffffff : 0), "svbi");

29626

+ check (svf[i] == i * 1.0f, "svf");

29627

+ }

29628

+}

29629

+

29630

+static void test ()

29631

+{

29632

+ vector unsigned char vuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

29633

+ vector signed char vsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};

29634

+ vector bool char vbc = {0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255};

29635

+ vector unsigned short vus = {0,1,2,3,4,5,6,7};

29636

+ vector signed short vss = {-4,-3,-2,-1,0,1,2,3};

29637

+ vector bool short vbs = {0,65535,0,65535,0,65535,0,65535};

29638

+ vector pixel vp = {0,1,2,3,4,5,6,7};

29639

+ vector unsigned int vui = {0,1,2,3};

29640

+ vector signed int vsi = {-2,-1,0,1};

29641

+ vector bool int vbi = {0,0xffffffff,0,0xffffffff};

29642

+ vector float vf = {0.0,1.0,2.0,3.0};

29643

+

29644

+ vec_st (vuc, 0, (vector unsigned char *)svuc);

29645

+ vec_st (vsc, 0, (vector signed char *)svsc);

29646

+ vec_st (vbc, 0, (vector bool char *)svbc);

29647

+ vec_st (vus, 0, (vector unsigned short *)svus);

29648

+ vec_st (vss, 0, (vector signed short *)svss);

29649

+ vec_st (vbs, 0, (vector bool short *)svbs);

29650

+ vec_st (vp, 0, (vector pixel *)svp);

29651

+ vec_st (vui, 0, (vector unsigned int *)svui);

29652

+ vec_st (vsi, 0, (vector signed int *)svsi);

29653

+ vec_st (vbi, 0, (vector bool int *)svbi);

29654

+ vec_st (vf, 0, (vector float *)svf);

29655

+

29656

+ check_arrays ();

29657

+}

29658

Index: gcc/testsuite/gcc.dg/vmx/ste-be-order.c

29659

===================================================================

29660

--- a/src/gcc/testsuite/gcc.dg/vmx/ste-be-order.c (.../tags/gcc_4_8_2_release)

29661

+++ b/src/gcc/testsuite/gcc.dg/vmx/ste-be-order.c (.../branches/gcc-4_8-branch)

29662

@@ -0,0 +1,53 @@

29663

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */

29664

+

29665

+#include "harness.h"

29666

+

29667

+static unsigned char svuc[16] __attribute__ ((aligned (16)));

29668

+static signed char svsc[16] __attribute__ ((aligned (16)));

29669

+static unsigned short svus[8] __attribute__ ((aligned (16)));

29670

+static signed short svss[8] __attribute__ ((aligned (16)));

29671

+static unsigned int svui[4] __attribute__ ((aligned (16)));

29672

+static signed int svsi[4] __attribute__ ((aligned (16)));

29673

+static float svf[4] __attribute__ ((aligned (16)));

29674

+

29675

+static void check_arrays ()

29676

+{

29677

+ check (svuc[9] == 9, "svuc");

29678

+ check (svsc[14] == 6, "svsc");

29679

+ check (svus[7] == 7, "svus");

29680

+ check (svss[1] == -3, "svss");

29681

+ check (svui[3] == 3, "svui");

29682

+ check (svsi[2] == 0, "svsi");

29683

+ check (svf[0] == 0.0, "svf");

29684

+}

29685

+

29686

+static void test ()

29687

+{

29688

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

29689

+ vector unsigned char vuc = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};

29690

+ vector signed char vsc = {7,6,5,4,3,2,1,0,-1,-2,-3,-4,-5,-6,-7,-8};

29691

+ vector unsigned short vus = {7,6,5,4,3,2,1,0};

29692

+ vector signed short vss = {3,2,1,0,-1,-2,-3,-4};

29693

+ vector unsigned int vui = {3,2,1,0};

29694

+ vector signed int vsi = {1,0,-1,-2};

29695

+ vector float vf = {3.0,2.0,1.0,0.0};

29696

+#else

29697

+ vector unsigned char vuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

29698

+ vector signed char vsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};

29699

+ vector unsigned short vus = {0,1,2,3,4,5,6,7};

29700

+ vector signed short vss = {-4,-3,-2,-1,0,1,2,3};

29701

+ vector unsigned int vui = {0,1,2,3};

29702

+ vector signed int vsi = {-2,-1,0,1};

29703

+ vector float vf = {0.0,1.0,2.0,3.0};

29704

+#endif

29705

+

29706

+ vec_ste (vuc, 9*1, (unsigned char *)svuc);

29707

+ vec_ste (vsc, 14*1, (signed char *)svsc);

29708

+ vec_ste (vus, 7*2, (unsigned short *)svus);

29709

+ vec_ste (vss, 1*2, (signed short *)svss);

29710

+ vec_ste (vui, 3*4, (unsigned int *)svui);

29711

+ vec_ste (vsi, 2*4, (signed int *)svsi);

29712

+ vec_ste (vf, 0*4, (float *)svf);

29713

+

29714

+ check_arrays ();

29715

+}

29716

Index: gcc/testsuite/gcc.dg/vmx/insert.c

29717

===================================================================

29718

--- a/src/gcc/testsuite/gcc.dg/vmx/insert.c (.../tags/gcc_4_8_2_release)

29719

+++ b/src/gcc/testsuite/gcc.dg/vmx/insert.c (.../branches/gcc-4_8-branch)

29720

@@ -0,0 +1,37 @@

29721

+#include "harness.h"

29722

+

29723

+static void test()

29724

+{

29725

+ vector unsigned char va = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

29726

+ vector signed char vb = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};

29727

+ vector unsigned short vc = {0,1,2,3,4,5,6,7};

29728

+ vector signed short vd = {-4,-3,-2,-1,0,1,2,3};

29729

+ vector unsigned int ve = {0,1,2,3};

29730

+ vector signed int vf = {-2,-1,0,1};

29731

+ vector float vg = {-2.0f,-1.0f,0.0f,1.0f};

29732

+

29733

+ check (vec_all_eq (vec_insert (16, va, 5),

29734

+ ((vector unsigned char)

29735

+ {0,1,2,3,4,16,6,7,8,9,10,11,12,13,14,15})),

29736

+ "vec_insert (va)");

29737

+ check (vec_all_eq (vec_insert (-16, vb, 0),

29738

+ ((vector signed char)

29739

+ {-16,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7})),

29740

+ "vec_insert (vb)");

29741

+ check (vec_all_eq (vec_insert (16, vc, 7),

29742

+ ((vector unsigned short){0,1,2,3,4,5,6,16})),

29743

+ "vec_insert (vc)");

29744

+ check (vec_all_eq (vec_insert (-16, vd, 3),

29745

+ ((vector signed short){-4,-3,-2,-16,0,1,2,3})),

29746

+ "vec_insert (vd)");

29747

+ check (vec_all_eq (vec_insert (16, ve, 2),

29748

+ ((vector unsigned int){0,1,16,3})),

29749

+ "vec_insert (ve)");

29750

+ check (vec_all_eq (vec_insert (-16, vf, 1),

29751

+ ((vector signed int){-2,-16,0,1})),

29752

+ "vec_insert (vf)");

29753

+ check (vec_all_eq (vec_insert (-16.0f, vg, 0),

29754

+ ((vector float){-16.0f,-1.0f,0.0f,1.0f})),

29755

+ "vec_insert (vg)");

29756

+}

29757

+

29758

Index: gcc/testsuite/gcc.dg/vmx/ld-vsx.c

29759

===================================================================

29760

--- a/src/gcc/testsuite/gcc.dg/vmx/ld-vsx.c (.../tags/gcc_4_8_2_release)

29761

+++ b/src/gcc/testsuite/gcc.dg/vmx/ld-vsx.c (.../branches/gcc-4_8-branch)

29762

@@ -0,0 +1,39 @@

29763

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

29764

+/* { dg-require-effective-target powerpc_vsx_ok } */

29765

+/* { dg-options "-maltivec -mabi=altivec -std=gnu99 -mvsx" } */

29766

+

29767

+#include "harness.h"

29768

+

29769

+static unsigned long long svul[2] __attribute__ ((aligned (16)));

29770

+static double svd[2] __attribute__ ((aligned (16)));

29771

+

29772

+static void init ()

29773

+{

29774

+ unsigned int i;

29775

+ for (i = 0; i < 2; ++i)

29776

+ {

29777

+ svul[i] = i;

29778

+ svd[i] = i * 1.0;

29779

+ }

29780

+}

29781

+

29782

+static void test ()

29783

+{

29784

+ vector unsigned long long evul = {0,1};

29785

+ vector double evd = {0.0,1.0};

29786

+

29787

+ vector unsigned long long vul;

29788

+ vector double vd;

29789

+ unsigned i;

29790

+

29791

+ init ();

29792

+

29793

+ vul = vec_ld (0, (vector unsigned long long *)svul);

29794

+ vd = vec_ld (0, (vector double *)svd);

29795

+

29796

+ for (i = 0; i < 2; ++i)

29797

+ {

29798

+ check (vul[i] == evul[i], "vul");

29799

+ check (vd[i] == evd[i], "vd" );

29800

+ }

29801

+}

29802

Index: gcc/testsuite/gcc.dg/vmx/extract-vsx.c

29803

===================================================================

29804

--- a/src/gcc/testsuite/gcc.dg/vmx/extract-vsx.c (.../tags/gcc_4_8_2_release)

29805

+++ b/src/gcc/testsuite/gcc.dg/vmx/extract-vsx.c (.../branches/gcc-4_8-branch)

29806

@@ -0,0 +1,16 @@

29807

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

29808

+/* { dg-require-effective-target powerpc_vsx_ok } */

29809

+/* { dg-options "-maltivec -mabi=altivec -std=gnu99 -mvsx" } */

29810

+

29811

+#include "harness.h"

29812

+

29813

+static void test()

29814

+{

29815

+ vector long long vl = {0, 1};

29816

+ vector double vd = {0.0, 1.0};

29817

+

29818

+ check (vec_extract (vl, 0) == 0, "vec_extract, vl, 0");

29819

+ check (vec_extract (vd, 1) == 1.0, "vec_extract, vd, 1");

29820

+ check (vl[0] == 0, "[], vl, 0");

29821

+ check (vd[1] == 1.0, "[], vd, 0");

29822

+}

29823

Index: gcc/testsuite/gcc.dg/vmx/perm.c

29824

===================================================================

29825

--- a/src/gcc/testsuite/gcc.dg/vmx/perm.c (.../tags/gcc_4_8_2_release)

29826

+++ b/src/gcc/testsuite/gcc.dg/vmx/perm.c (.../branches/gcc-4_8-branch)

29827

@@ -0,0 +1,69 @@

29828

+#include "harness.h"

29829

+

29830

+static void test()

29831

+{

29832

+ /* Input vectors. */

29833

+ vector unsigned char vuca = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

29834

+ vector unsigned char vucb

29835

+ = {16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31};

29836

+ vector unsigned char vucp = {0,31,1,30,2,29,3,28,4,27,5,26,6,25,7,24};

29837

+

29838

+ vector signed char vsca

29839

+ = {-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1};

29840

+ vector signed char vscb = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

29841

+ vector unsigned char vscp = {0,31,1,30,2,29,3,28,4,27,5,26,6,25,7,24};

29842

+

29843

+ vector unsigned short vusa = {0,1,2,3,4,5,6,7};

29844

+ vector unsigned short vusb = {8,9,10,11,12,13,14,15};

29845

+ vector unsigned char vusp = {0,1,30,31,2,3,28,29,4,5,26,27,6,7,24,25};

29846

+

29847

+ vector signed short vssa = {-8,-7,-6,-5,-4,-3,-2,-1};

29848

+ vector signed short vssb = {0,1,2,3,4,5,6,7};

29849

+ vector unsigned char vssp = {0,1,30,31,2,3,28,29,4,5,26,27,6,7,24,25};

29850

+

29851

+ vector unsigned int vuia = {0,1,2,3};

29852

+ vector unsigned int vuib = {4,5,6,7};

29853

+ vector unsigned char vuip = {0,1,2,3,28,29,30,31,4,5,6,7,24,25,26,27};

29854

+

29855

+ vector signed int vsia = {-4,-3,-2,-1};

29856

+ vector signed int vsib = {0,1,2,3};

29857

+ vector unsigned char vsip = {0,1,2,3,28,29,30,31,4,5,6,7,24,25,26,27};

29858

+

29859

+ vector float vfa = {-4.0,-3.0,-2.0,-1.0};

29860

+ vector float vfb = {0.0,1.0,2.0,3.0};

29861

+ vector unsigned char vfp = {0,1,2,3,28,29,30,31,4,5,6,7,24,25,26,27};

29862

+

29863

+ /* Result vectors. */

29864

+ vector unsigned char vuc;

29865

+ vector signed char vsc;

29866

+ vector unsigned short vus;

29867

+ vector signed short vss;

29868

+ vector unsigned int vui;

29869

+ vector signed int vsi;

29870

+ vector float vf;

29871

+

29872

+ /* Expected result vectors. */

29873

+ vector unsigned char vucr = {0,31,1,30,2,29,3,28,4,27,5,26,6,25,7,24};

29874

+ vector signed char vscr = {-16,15,-15,14,-14,13,-13,12,-12,11,-11,10,-10,9,-9,8};

29875

+ vector unsigned short vusr = {0,15,1,14,2,13,3,12};

29876

+ vector signed short vssr = {-8,7,-7,6,-6,5,-5,4};

29877

+ vector unsigned int vuir = {0,7,1,6};

29878

+ vector signed int vsir = {-4,3,-3,2};

29879

+ vector float vfr = {-4.0,3.0,-3.0,2.0};

29880

+

29881

+ vuc = vec_perm (vuca, vucb, vucp);

29882

+ vsc = vec_perm (vsca, vscb, vscp);

29883

+ vus = vec_perm (vusa, vusb, vusp);

29884

+ vss = vec_perm (vssa, vssb, vssp);

29885

+ vui = vec_perm (vuia, vuib, vuip);

29886

+ vsi = vec_perm (vsia, vsib, vsip);

29887

+ vf = vec_perm (vfa, vfb, vfp );

29888

+

29889

+ check (vec_all_eq (vuc, vucr), "vuc");

29890

+ check (vec_all_eq (vsc, vscr), "vsc");

29891

+ check (vec_all_eq (vus, vusr), "vus");

29892

+ check (vec_all_eq (vss, vssr), "vss");

29893

+ check (vec_all_eq (vui, vuir), "vui");

29894

+ check (vec_all_eq (vsi, vsir), "vsi");

29895

+ check (vec_all_eq (vf, vfr), "vf" );

29896

+}

29897

Index: gcc/testsuite/gcc.dg/vmx/extract-be-order.c

29898

===================================================================

29899

--- a/src/gcc/testsuite/gcc.dg/vmx/extract-be-order.c (.../tags/gcc_4_8_2_release)

29900

+++ b/src/gcc/testsuite/gcc.dg/vmx/extract-be-order.c (.../branches/gcc-4_8-branch)

29901

@@ -0,0 +1,33 @@

29902

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */

29903

+

29904

+#include "harness.h"

29905

+

29906

+static void test()

29907

+{

29908

+ vector unsigned char va = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

29909

+ vector signed char vb = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};

29910

+ vector unsigned short vc = {0,1,2,3,4,5,6,7};

29911

+ vector signed short vd = {-4,-3,-2,-1,0,1,2,3};

29912

+ vector unsigned int ve = {0,1,2,3};

29913

+ vector signed int vf = {-2,-1,0,1};

29914

+ vector float vg = {-2.0f,-1.0f,0.0f,1.0f};

29915

+

29916

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

29917

+ check (vec_extract (va, 5) == 10, "vec_extract (va, 5)");

29918

+ check (vec_extract (vb, 0) == 7, "vec_extract (vb, 0)");

29919

+ check (vec_extract (vc, 7) == 0, "vec_extract (vc, 7)");

29920

+ check (vec_extract (vd, 3) == 0, "vec_extract (vd, 3)");

29921

+ check (vec_extract (ve, 2) == 1, "vec_extract (ve, 2)");

29922

+ check (vec_extract (vf, 1) == 0, "vec_extract (vf, 1)");

29923

+ check (vec_extract (vg, 0) == 1.0f, "vec_extract (vg, 0)");

29924

+#else

29925

+ check (vec_extract (va, 5) == 5, "vec_extract (va, 5)");

29926

+ check (vec_extract (vb, 0) == -8, "vec_extract (vb, 0)");

29927

+ check (vec_extract (vc, 7) == 7, "vec_extract (vc, 7)");

29928

+ check (vec_extract (vd, 3) == -1, "vec_extract (vd, 3)");

29929

+ check (vec_extract (ve, 2) == 2, "vec_extract (ve, 2)");

29930

+ check (vec_extract (vf, 1) == -1, "vec_extract (vf, 1)");

29931

+ check (vec_extract (vg, 0) == -2.0f, "vec_extract (vg, 0)");

29932

+#endif

29933

+}

29934

+

29935

Index: gcc/testsuite/gcc.dg/vmx/ldl-be-order.c

29936

===================================================================

29937

--- a/src/gcc/testsuite/gcc.dg/vmx/ldl-be-order.c (.../tags/gcc_4_8_2_release)

29938

+++ b/src/gcc/testsuite/gcc.dg/vmx/ldl-be-order.c (.../branches/gcc-4_8-branch)

29939

@@ -0,0 +1,107 @@

29940

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */

29941

+

29942

+#include "harness.h"

29943

+

29944

+static unsigned char svuc[16] __attribute__ ((aligned (16)));

29945

+static signed char svsc[16] __attribute__ ((aligned (16)));

29946

+static unsigned char svbc[16] __attribute__ ((aligned (16)));

29947

+static unsigned short svus[8] __attribute__ ((aligned (16)));

29948

+static signed short svss[8] __attribute__ ((aligned (16)));

29949

+static unsigned short svbs[8] __attribute__ ((aligned (16)));

29950

+static unsigned short svp[8] __attribute__ ((aligned (16)));

29951

+static unsigned int svui[4] __attribute__ ((aligned (16)));

29952

+static signed int svsi[4] __attribute__ ((aligned (16)));

29953

+static unsigned int svbi[4] __attribute__ ((aligned (16)));

29954

+static float svf[4] __attribute__ ((aligned (16)));

29955

+

29956

+static void init ()

29957

+{

29958

+ unsigned int i;

29959

+ for (i = 0; i < 16; ++i)

29960

+ {

29961

+ svuc[i] = i;

29962

+ svsc[i] = i - 8;

29963

+ svbc[i] = (i % 2) ? 0xff : 0;

29964

+ }

29965

+ for (i = 0; i < 8; ++i)

29966

+ {

29967

+ svus[i] = i;

29968

+ svss[i] = i - 4;

29969

+ svbs[i] = (i % 2) ? 0xffff : 0;

29970

+ svp[i] = i;

29971

+ }

29972

+ for (i = 0; i < 4; ++i)

29973

+ {

29974

+ svui[i] = i;

29975

+ svsi[i] = i - 2;

29976

+ svbi[i] = (i % 2) ? 0xffffffff : 0;

29977

+ svf[i] = i * 1.0f;

29978

+ }

29979

+}

29980

+

29981

+static void test ()

29982

+{

29983

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

29984

+ vector unsigned char evuc = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};

29985

+ vector signed char evsc = {7,6,5,4,3,2,1,0,-1,-2,-3,-4,-5,-6,-7,-8};

29986

+ vector bool char evbc = {255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0};

29987

+ vector unsigned short evus = {7,6,5,4,3,2,1,0};

29988

+ vector signed short evss = {3,2,1,0,-1,-2,-3,-4};

29989

+ vector bool short evbs = {65535,0,65535,0,65535,0,65535,0};

29990

+ vector pixel evp = {7,6,5,4,3,2,1,0};

29991

+ vector unsigned int evui = {3,2,1,0};

29992

+ vector signed int evsi = {1,0,-1,-2};

29993

+ vector bool int evbi = {0xffffffff,0,0xffffffff,0};

29994

+ vector float evf = {3.0,2.0,1.0,0.0};

29995

+#else

29996

+ vector unsigned char evuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

29997

+ vector signed char evsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};

29998

+ vector bool char evbc = {0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255};

29999

+ vector unsigned short evus = {0,1,2,3,4,5,6,7};

30000

+ vector signed short evss = {-4,-3,-2,-1,0,1,2,3};

30001

+ vector bool short evbs = {0,65535,0,65535,0,65535,0,65535};

30002

+ vector pixel evp = {0,1,2,3,4,5,6,7};

30003

+ vector unsigned int evui = {0,1,2,3};

30004

+ vector signed int evsi = {-2,-1,0,1};

30005

+ vector bool int evbi = {0,0xffffffff,0,0xffffffff};

30006

+ vector float evf = {0.0,1.0,2.0,3.0};

30007

+#endif

30008

+

30009

+ vector unsigned char vuc;

30010

+ vector signed char vsc;

30011

+ vector bool char vbc;

30012

+ vector unsigned short vus;

30013

+ vector signed short vss;

30014

+ vector bool short vbs;

30015

+ vector pixel vp;

30016

+ vector unsigned int vui;

30017

+ vector signed int vsi;

30018

+ vector bool int vbi;

30019

+ vector float vf;

30020

+

30021

+ init ();

30022

+

30023

+ vuc = vec_ldl (0, (vector unsigned char *)svuc);

30024

+ vsc = vec_ldl (0, (vector signed char *)svsc);

30025

+ vbc = vec_ldl (0, (vector bool char *)svbc);

30026

+ vus = vec_ldl (0, (vector unsigned short *)svus);

30027

+ vss = vec_ldl (0, (vector signed short *)svss);

30028

+ vbs = vec_ldl (0, (vector bool short *)svbs);

30029

+ vp = vec_ldl (0, (vector pixel *)svp);

30030

+ vui = vec_ldl (0, (vector unsigned int *)svui);

30031

+ vsi = vec_ldl (0, (vector signed int *)svsi);

30032

+ vbi = vec_ldl (0, (vector bool int *)svbi);

30033

+ vf = vec_ldl (0, (vector float *)svf);

30034

+

30035

+ check (vec_all_eq (vuc, evuc), "vuc");

30036

+ check (vec_all_eq (vsc, evsc), "vsc");

30037

+ check (vec_all_eq (vbc, evbc), "vbc");

30038

+ check (vec_all_eq (vus, evus), "vus");

30039

+ check (vec_all_eq (vss, evss), "vss");

30040

+ check (vec_all_eq (vbs, evbs), "vbs");

30041

+ check (vec_all_eq (vp, evp ), "vp" );

30042

+ check (vec_all_eq (vui, evui), "vui");

30043

+ check (vec_all_eq (vsi, evsi), "vsi");

30044

+ check (vec_all_eq (vbi, evbi), "vbi");

30045

+ check (vec_all_eq (vf, evf ), "vf" );

30046

+}

30047

Index: gcc/testsuite/gcc.dg/vmx/mult-even-odd.c

30048

===================================================================

30049

--- a/src/gcc/testsuite/gcc.dg/vmx/mult-even-odd.c (.../tags/gcc_4_8_2_release)

30050

+++ b/src/gcc/testsuite/gcc.dg/vmx/mult-even-odd.c (.../branches/gcc-4_8-branch)

30051

@@ -0,0 +1,43 @@

30052

+#include "harness.h"

30053

+

30054

+static void test()

30055

+{

30056

+ vector unsigned char vuca = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

30057

+ vector unsigned char vucb = {2,3,2,3,2,3,2,3,2,3,2,3,2,3,2,3};

30058

+ vector signed char vsca = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};

30059

+ vector signed char vscb = {2,-3,2,-3,2,-3,2,-3,2,-3,2,-3,2,-3,2,-3};

30060

+ vector unsigned short vusa = {0,1,2,3,4,5,6,7};

30061

+ vector unsigned short vusb = {2,3,2,3,2,3,2,3};

30062

+ vector signed short vssa = {-4,-3,-2,-1,0,1,2,3};

30063

+ vector signed short vssb = {2,-3,2,-3,2,-3,2,-3};

30064

+ vector unsigned short vuse, vuso;

30065

+ vector signed short vsse, vsso;

30066

+ vector unsigned int vuie, vuio;

30067

+ vector signed int vsie, vsio;

30068

+

30069

+ vuse = vec_mule (vuca, vucb);

30070

+ vuso = vec_mulo (vuca, vucb);

30071

+ vsse = vec_mule (vsca, vscb);

30072

+ vsso = vec_mulo (vsca, vscb);

30073

+ vuie = vec_mule (vusa, vusb);

30074

+ vuio = vec_mulo (vusa, vusb);

30075

+ vsie = vec_mule (vssa, vssb);

30076

+ vsio = vec_mulo (vssa, vssb);

30077

+

30078

+ check (vec_all_eq (vuse,

30079

+ ((vector unsigned short){0,4,8,12,16,20,24,28})),

30080

+ "vuse");

30081

+ check (vec_all_eq (vuso,

30082

+ ((vector unsigned short){3,9,15,21,27,33,39,45})),

30083

+ "vuso");

30084

+ check (vec_all_eq (vsse,

30085

+ ((vector signed short){-16,-12,-8,-4,0,4,8,12})),

30086

+ "vsse");

30087

+ check (vec_all_eq (vsso,

30088

+ ((vector signed short){21,15,9,3,-3,-9,-15,-21})),

30089

+ "vsso");

30090

+ check (vec_all_eq (vuie, ((vector unsigned int){0,4,8,12})), "vuie");

30091

+ check (vec_all_eq (vuio, ((vector unsigned int){3,9,15,21})), "vuio");

30092

+ check (vec_all_eq (vsie, ((vector signed int){-8,-4,0,4})), "vsie");

30093

+ check (vec_all_eq (vsio, ((vector signed int){9,3,-3,-9})), "vsio");

30094

+}

30095

Index: gcc/testsuite/gcc.dg/vmx/splat-be-order.c

30096

===================================================================

30097

--- a/src/gcc/testsuite/gcc.dg/vmx/splat-be-order.c (.../tags/gcc_4_8_2_release)

30098

+++ b/src/gcc/testsuite/gcc.dg/vmx/splat-be-order.c (.../branches/gcc-4_8-branch)

30099

@@ -0,0 +1,59 @@

30100

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */

30101

+

30102

+#include "harness.h"

30103

+

30104

+static void test()

30105

+{

30106

+ /* Input vectors. */

30107

+ vector unsigned char vuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

30108

+ vector signed char vsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};

30109

+ vector unsigned short vus = {0,1,2,3,4,5,6,7};

30110

+ vector signed short vss = {-4,-3,-2,-1,0,1,2,3};

30111

+ vector unsigned int vui = {0,1,2,3};

30112

+ vector signed int vsi = {-2,-1,0,1};

30113

+ vector float vf = {-2.0,-1.0,0.0,1.0};

30114

+

30115

+ /* Result vectors. */

30116

+ vector unsigned char vucr;

30117

+ vector signed char vscr;

30118

+ vector unsigned short vusr;

30119

+ vector signed short vssr;

30120

+ vector unsigned int vuir;

30121

+ vector signed int vsir;

30122

+ vector float vfr;

30123

+

30124

+ /* Expected result vectors. */

30125

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

30126

+ vector unsigned char vucer = {14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14};

30127

+ vector signed char vscer = {-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1};

30128

+ vector unsigned short vuser = {0,0,0,0,0,0,0,0};

30129

+ vector signed short vsser = {3,3,3,3,3,3,3,3};

30130

+ vector unsigned int vuier = {1,1,1,1};

30131

+ vector signed int vsier = {-2,-2,-2,-2};

30132

+ vector float vfer = {0.0,0.0,0.0,0.0};

30133

+#else

30134

+ vector unsigned char vucer = {1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1};

30135

+ vector signed char vscer = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};

30136

+ vector unsigned short vuser = {7,7,7,7,7,7,7,7};

30137

+ vector signed short vsser = {-4,-4,-4,-4,-4,-4,-4,-4};

30138

+ vector unsigned int vuier = {2,2,2,2};

30139

+ vector signed int vsier = {1,1,1,1};

30140

+ vector float vfer = {-1.0,-1.0,-1.0,-1.0};

30141

+#endif

30142

+

30143

+ vucr = vec_splat (vuc, 1);

30144

+ vscr = vec_splat (vsc, 8);

30145

+ vusr = vec_splat (vus, 7);

30146

+ vssr = vec_splat (vss, 0);

30147

+ vuir = vec_splat (vui, 2);

30148

+ vsir = vec_splat (vsi, 3);

30149

+ vfr = vec_splat (vf, 1);

30150

+

30151

+ check (vec_all_eq (vucr, vucer), "vuc");

30152

+ check (vec_all_eq (vscr, vscer), "vsc");

30153

+ check (vec_all_eq (vusr, vuser), "vus");

30154

+ check (vec_all_eq (vssr, vsser), "vss");

30155

+ check (vec_all_eq (vuir, vuier), "vui");

30156

+ check (vec_all_eq (vsir, vsier), "vsi");

30157

+ check (vec_all_eq (vfr, vfer ), "vf");

30158

+}

30159

Index: gcc/testsuite/gcc.dg/vmx/extract-vsx-be-order.c

30160

===================================================================

30161

--- a/src/gcc/testsuite/gcc.dg/vmx/extract-vsx-be-order.c (.../tags/gcc_4_8_2_release)

30162

+++ b/src/gcc/testsuite/gcc.dg/vmx/extract-vsx-be-order.c (.../branches/gcc-4_8-branch)

30163

@@ -0,0 +1,19 @@

30164

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

30165

+/* { dg-require-effective-target powerpc_vsx_ok } */

30166

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mvsx" } */

30167

+

30168

+#include "harness.h"

30169

+

30170

+static void test()

30171

+{

30172

+ vector long long vl = {0, 1};

30173

+ vector double vd = {0.0, 1.0};

30174

+

30175

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

30176

+ check (vec_extract (vl, 0) == 1, "vl, 0");

30177

+ check (vec_extract (vd, 1) == 0.0, "vd, 1");

30178

+#else

30179

+ check (vec_extract (vl, 0) == 0, "vl, 0");

30180

+ check (vec_extract (vd, 1) == 1.0, "vd, 1");

30181

+#endif

30182

+}

30183

Index: gcc/testsuite/gcc.dg/vmx/ld-be-order.c

30184

===================================================================

30185

--- a/src/gcc/testsuite/gcc.dg/vmx/ld-be-order.c (.../tags/gcc_4_8_2_release)

30186

+++ b/src/gcc/testsuite/gcc.dg/vmx/ld-be-order.c (.../branches/gcc-4_8-branch)

30187

@@ -0,0 +1,107 @@

30188

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */

30189

+

30190

+#include "harness.h"

30191

+

30192

+static unsigned char svuc[16] __attribute__ ((aligned (16)));

30193

+static signed char svsc[16] __attribute__ ((aligned (16)));

30194

+static unsigned char svbc[16] __attribute__ ((aligned (16)));

30195

+static unsigned short svus[8] __attribute__ ((aligned (16)));

30196

+static signed short svss[8] __attribute__ ((aligned (16)));

30197

+static unsigned short svbs[8] __attribute__ ((aligned (16)));

30198

+static unsigned short svp[8] __attribute__ ((aligned (16)));

30199

+static unsigned int svui[4] __attribute__ ((aligned (16)));

30200

+static signed int svsi[4] __attribute__ ((aligned (16)));

30201

+static unsigned int svbi[4] __attribute__ ((aligned (16)));

30202

+static float svf[4] __attribute__ ((aligned (16)));

30203

+

30204

+static void init ()

30205

+{

30206

+ unsigned int i;

30207

+ for (i = 0; i < 16; ++i)

30208

+ {

30209

+ svuc[i] = i;

30210

+ svsc[i] = i - 8;

30211

+ svbc[i] = (i % 2) ? 0xff : 0;

30212

+ }

30213

+ for (i = 0; i < 8; ++i)

30214

+ {

30215

+ svus[i] = i;

30216

+ svss[i] = i - 4;

30217

+ svbs[i] = (i % 2) ? 0xffff : 0;

30218

+ svp[i] = i;

30219

+ }

30220

+ for (i = 0; i < 4; ++i)

30221

+ {

30222

+ svui[i] = i;

30223

+ svsi[i] = i - 2;

30224

+ svbi[i] = (i % 2) ? 0xffffffff : 0;

30225

+ svf[i] = i * 1.0f;

30226

+ }

30227

+}

30228

+

30229

+static void test ()

30230

+{

30231

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

30232

+ vector unsigned char evuc = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};

30233

+ vector signed char evsc = {7,6,5,4,3,2,1,0,-1,-2,-3,-4,-5,-6,-7,-8};

30234

+ vector bool char evbc = {255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0};

30235

+ vector unsigned short evus = {7,6,5,4,3,2,1,0};

30236

+ vector signed short evss = {3,2,1,0,-1,-2,-3,-4};

30237

+ vector bool short evbs = {65535,0,65535,0,65535,0,65535,0};

30238

+ vector pixel evp = {7,6,5,4,3,2,1,0};

30239

+ vector unsigned int evui = {3,2,1,0};

30240

+ vector signed int evsi = {1,0,-1,-2};

30241

+ vector bool int evbi = {0xffffffff,0,0xffffffff,0};

30242

+ vector float evf = {3.0,2.0,1.0,0.0};

30243

+#else

30244

+ vector unsigned char evuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

30245

+ vector signed char evsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};

30246

+ vector bool char evbc = {0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255};

30247

+ vector unsigned short evus = {0,1,2,3,4,5,6,7};

30248

+ vector signed short evss = {-4,-3,-2,-1,0,1,2,3};

30249

+ vector bool short evbs = {0,65535,0,65535,0,65535,0,65535};

30250

+ vector pixel evp = {0,1,2,3,4,5,6,7};

30251

+ vector unsigned int evui = {0,1,2,3};

30252

+ vector signed int evsi = {-2,-1,0,1};

30253

+ vector bool int evbi = {0,0xffffffff,0,0xffffffff};

30254

+ vector float evf = {0.0,1.0,2.0,3.0};

30255

+#endif

30256

+

30257

+ vector unsigned char vuc;

30258

+ vector signed char vsc;

30259

+ vector bool char vbc;

30260

+ vector unsigned short vus;

30261

+ vector signed short vss;

30262

+ vector bool short vbs;

30263

+ vector pixel vp;

30264

+ vector unsigned int vui;

30265

+ vector signed int vsi;

30266

+ vector bool int vbi;

30267

+ vector float vf;

30268

+

30269

+ init ();

30270

+

30271

+ vuc = vec_ld (0, (vector unsigned char *)svuc);

30272

+ vsc = vec_ld (0, (vector signed char *)svsc);

30273

+ vbc = vec_ld (0, (vector bool char *)svbc);

30274

+ vus = vec_ld (0, (vector unsigned short *)svus);

30275

+ vss = vec_ld (0, (vector signed short *)svss);

30276

+ vbs = vec_ld (0, (vector bool short *)svbs);

30277

+ vp = vec_ld (0, (vector pixel *)svp);

30278

+ vui = vec_ld (0, (vector unsigned int *)svui);

30279

+ vsi = vec_ld (0, (vector signed int *)svsi);

30280

+ vbi = vec_ld (0, (vector bool int *)svbi);

30281

+ vf = vec_ld (0, (vector float *)svf);

30282

+

30283

+ check (vec_all_eq (vuc, evuc), "vuc");

30284

+ check (vec_all_eq (vsc, evsc), "vsc");

30285

+ check (vec_all_eq (vbc, evbc), "vbc");

30286

+ check (vec_all_eq (vus, evus), "vus");

30287

+ check (vec_all_eq (vss, evss), "vss");

30288

+ check (vec_all_eq (vbs, evbs), "vbs");

30289

+ check (vec_all_eq (vp, evp ), "vp" );

30290

+ check (vec_all_eq (vui, evui), "vui");

30291

+ check (vec_all_eq (vsi, evsi), "vsi");

30292

+ check (vec_all_eq (vbi, evbi), "vbi");

30293

+ check (vec_all_eq (vf, evf ), "vf" );

30294

+}

30295

Index: gcc/testsuite/gcc.dg/vmx/ld.c

30296

===================================================================

30297

--- a/src/gcc/testsuite/gcc.dg/vmx/ld.c (.../tags/gcc_4_8_2_release)

30298

+++ b/src/gcc/testsuite/gcc.dg/vmx/ld.c (.../branches/gcc-4_8-branch)

30299

@@ -0,0 +1,91 @@

30300

+#include "harness.h"

30301

+

30302

+static unsigned char svuc[16] __attribute__ ((aligned (16)));

30303

+static signed char svsc[16] __attribute__ ((aligned (16)));

30304

+static unsigned char svbc[16] __attribute__ ((aligned (16)));

30305

+static unsigned short svus[8] __attribute__ ((aligned (16)));

30306

+static signed short svss[8] __attribute__ ((aligned (16)));

30307

+static unsigned short svbs[8] __attribute__ ((aligned (16)));

30308

+static unsigned short svp[8] __attribute__ ((aligned (16)));

30309

+static unsigned int svui[4] __attribute__ ((aligned (16)));

30310

+static signed int svsi[4] __attribute__ ((aligned (16)));

30311

+static unsigned int svbi[4] __attribute__ ((aligned (16)));

30312

+static float svf[4] __attribute__ ((aligned (16)));

30313

+

30314

+static void init ()

30315

+{

30316

+ unsigned int i;

30317

+ for (i = 0; i < 16; ++i)

30318

+ {

30319

+ svuc[i] = i;

30320

+ svsc[i] = i - 8;

30321

+ svbc[i] = (i % 2) ? 0xff : 0;

30322

+ }

30323

+ for (i = 0; i < 8; ++i)

30324

+ {

30325

+ svus[i] = i;

30326

+ svss[i] = i - 4;

30327

+ svbs[i] = (i % 2) ? 0xffff : 0;

30328

+ svp[i] = i;

30329

+ }

30330

+ for (i = 0; i < 4; ++i)

30331

+ {

30332

+ svui[i] = i;

30333

+ svsi[i] = i - 2;

30334

+ svbi[i] = (i % 2) ? 0xffffffff : 0;

30335

+ svf[i] = i * 1.0f;

30336

+ }

30337

+}

30338

+

30339

+static void test ()

30340

+{

30341

+ vector unsigned char evuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

30342

+ vector signed char evsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};

30343

+ vector bool char evbc = {0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255};

30344

+ vector unsigned short evus = {0,1,2,3,4,5,6,7};

30345

+ vector signed short evss = {-4,-3,-2,-1,0,1,2,3};

30346

+ vector bool short evbs = {0,65535,0,65535,0,65535,0,65535};

30347

+ vector pixel evp = {0,1,2,3,4,5,6,7};

30348

+ vector unsigned int evui = {0,1,2,3};

30349

+ vector signed int evsi = {-2,-1,0,1};

30350

+ vector bool int evbi = {0,0xffffffff,0,0xffffffff};

30351

+ vector float evf = {0.0,1.0,2.0,3.0};

30352

+

30353

+ vector unsigned char vuc;

30354

+ vector signed char vsc;

30355

+ vector bool char vbc;

30356

+ vector unsigned short vus;

30357

+ vector signed short vss;

30358

+ vector bool short vbs;

30359

+ vector pixel vp;

30360

+ vector unsigned int vui;

30361

+ vector signed int vsi;

30362

+ vector bool int vbi;

30363

+ vector float vf;

30364

+

30365

+ init ();

30366

+

30367

+ vuc = vec_ld (0, (vector unsigned char *)svuc);

30368

+ vsc = vec_ld (0, (vector signed char *)svsc);

30369

+ vbc = vec_ld (0, (vector bool char *)svbc);

30370

+ vus = vec_ld (0, (vector unsigned short *)svus);

30371

+ vss = vec_ld (0, (vector signed short *)svss);

30372

+ vbs = vec_ld (0, (vector bool short *)svbs);

30373

+ vp = vec_ld (0, (vector pixel *)svp);

30374

+ vui = vec_ld (0, (vector unsigned int *)svui);

30375

+ vsi = vec_ld (0, (vector signed int *)svsi);

30376

+ vbi = vec_ld (0, (vector bool int *)svbi);

30377

+ vf = vec_ld (0, (vector float *)svf);

30378

+

30379

+ check (vec_all_eq (vuc, evuc), "vuc");

30380

+ check (vec_all_eq (vsc, evsc), "vsc");

30381

+ check (vec_all_eq (vbc, evbc), "vbc");

30382

+ check (vec_all_eq (vus, evus), "vus");

30383

+ check (vec_all_eq (vss, evss), "vss");

30384

+ check (vec_all_eq (vbs, evbs), "vbs");

30385

+ check (vec_all_eq (vp, evp ), "vp" );

30386

+ check (vec_all_eq (vui, evui), "vui");

30387

+ check (vec_all_eq (vsi, evsi), "vsi");

30388

+ check (vec_all_eq (vbi, evbi), "vbi");

30389

+ check (vec_all_eq (vf, evf ), "vf" );

30390

+}

30391

Index: gcc/testsuite/gcc.dg/vmx/sn7153.c

30392

===================================================================

30393

--- a/src/gcc/testsuite/gcc.dg/vmx/sn7153.c (.../tags/gcc_4_8_2_release)

30394

+++ b/src/gcc/testsuite/gcc.dg/vmx/sn7153.c (.../branches/gcc-4_8-branch)

30395

@@ -34,7 +34,11 @@

30396

30397

void validate_sat()

30398

{

30399

+#ifdef __LITTLE_ENDIAN__

30400

+ if (vec_any_ne(vec_splat(vec_mfvscr(), 0), ((vector unsigned short){1,1,1,1,1,1,1,1})))

30401

+#else

30402

if (vec_any_ne(vec_splat(vec_mfvscr(), 7), ((vector unsigned short){1,1,1,1,1,1,1,1})))

30403

+#endif

30404

{

30405

union {vector unsigned short v; unsigned short s[8];} u;

30406

u.v = vec_mfvscr();

30407

Index: gcc/testsuite/gcc.dg/vmx/stl.c

30408

===================================================================

30409

--- a/src/gcc/testsuite/gcc.dg/vmx/stl.c (.../tags/gcc_4_8_2_release)

30410

+++ b/src/gcc/testsuite/gcc.dg/vmx/stl.c (.../branches/gcc-4_8-branch)

30411

@@ -0,0 +1,67 @@

30412

+#include "harness.h"

30413

+

30414

+static unsigned char svuc[16] __attribute__ ((aligned (16)));

30415

+static signed char svsc[16] __attribute__ ((aligned (16)));

30416

+static unsigned char svbc[16] __attribute__ ((aligned (16)));

30417

+static unsigned short svus[8] __attribute__ ((aligned (16)));

30418

+static signed short svss[8] __attribute__ ((aligned (16)));

30419

+static unsigned short svbs[8] __attribute__ ((aligned (16)));

30420

+static unsigned short svp[8] __attribute__ ((aligned (16)));

30421

+static unsigned int svui[4] __attribute__ ((aligned (16)));

30422

+static signed int svsi[4] __attribute__ ((aligned (16)));

30423

+static unsigned int svbi[4] __attribute__ ((aligned (16)));

30424

+static float svf[4] __attribute__ ((aligned (16)));

30425

+

30426

+static void check_arrays ()

30427

+{

30428

+ unsigned int i;

30429

+ for (i = 0; i < 16; ++i)

30430

+ {

30431

+ check (svuc[i] == i, "svuc");

30432

+ check (svsc[i] == i - 8, "svsc");

30433

+ check (svbc[i] == ((i % 2) ? 0xff : 0), "svbc");

30434

+ }

30435

+ for (i = 0; i < 8; ++i)

30436

+ {

30437

+ check (svus[i] == i, "svus");

30438

+ check (svss[i] == i - 4, "svss");

30439

+ check (svbs[i] == ((i % 2) ? 0xffff : 0), "svbs");

30440

+ check (svp[i] == i, "svp");

30441

+ }

30442

+ for (i = 0; i < 4; ++i)

30443

+ {

30444

+ check (svui[i] == i, "svui");

30445

+ check (svsi[i] == i - 2, "svsi");

30446

+ check (svbi[i] == ((i % 2) ? 0xffffffff : 0), "svbi");

30447

+ check (svf[i] == i * 1.0f, "svf");

30448

+ }

30449

+}

30450

+

30451

+static void test ()

30452

+{

30453

+ vector unsigned char vuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

30454

+ vector signed char vsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};

30455

+ vector bool char vbc = {0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255};

30456

+ vector unsigned short vus = {0,1,2,3,4,5,6,7};

30457

+ vector signed short vss = {-4,-3,-2,-1,0,1,2,3};

30458

+ vector bool short vbs = {0,65535,0,65535,0,65535,0,65535};

30459

+ vector pixel vp = {0,1,2,3,4,5,6,7};

30460

+ vector unsigned int vui = {0,1,2,3};

30461

+ vector signed int vsi = {-2,-1,0,1};

30462

+ vector bool int vbi = {0,0xffffffff,0,0xffffffff};

30463

+ vector float vf = {0.0,1.0,2.0,3.0};

30464

+

30465

+ vec_stl (vuc, 0, (vector unsigned char *)svuc);

30466

+ vec_stl (vsc, 0, (vector signed char *)svsc);

30467

+ vec_stl (vbc, 0, (vector bool char *)svbc);

30468

+ vec_stl (vus, 0, (vector unsigned short *)svus);

30469

+ vec_stl (vss, 0, (vector signed short *)svss);

30470

+ vec_stl (vbs, 0, (vector bool short *)svbs);

30471

+ vec_stl (vp, 0, (vector pixel *)svp);

30472

+ vec_stl (vui, 0, (vector unsigned int *)svui);

30473

+ vec_stl (vsi, 0, (vector signed int *)svsi);

30474

+ vec_stl (vbi, 0, (vector bool int *)svbi);

30475

+ vec_stl (vf, 0, (vector float *)svf);

30476

+

30477

+ check_arrays ();

30478

+}

30479

Index: gcc/testsuite/gcc.dg/vmx/st-vsx.c

30480

===================================================================

30481

--- a/src/gcc/testsuite/gcc.dg/vmx/st-vsx.c (.../tags/gcc_4_8_2_release)

30482

+++ b/src/gcc/testsuite/gcc.dg/vmx/st-vsx.c (.../branches/gcc-4_8-branch)

30483

@@ -0,0 +1,29 @@

30484

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

30485

+/* { dg-require-effective-target powerpc_vsx_ok } */

30486

+/* { dg-options "-maltivec -mabi=altivec -std=gnu99 -mvsx" } */

30487

+

30488

+#include "harness.h"

30489

+

30490

+static unsigned long long svul[2] __attribute__ ((aligned (16)));

30491

+static double svd[2] __attribute__ ((aligned (16)));

30492

+

30493

+static void check_arrays ()

30494

+{

30495

+ unsigned int i;

30496

+ for (i = 0; i < 2; ++i)

30497

+ {

30498

+ check (svul[i] == i, "svul");

30499

+ check (svd[i] == i * 1.0, "svd");

30500

+ }

30501

+}

30502

+

30503

+static void test ()

30504

+{

30505

+ vector unsigned long long vul = {0,1};

30506

+ vector double vd = {0.0,1.0};

30507

+

30508

+ vec_st (vul, 0, (vector unsigned long long *)svul);

30509

+ vec_st (vd, 0, (vector double *)svd);

30510

+

30511

+ check_arrays ();

30512

+}

30513

Index: gcc/testsuite/gcc.dg/vmx/sum2s.c

30514

===================================================================

30515

--- a/src/gcc/testsuite/gcc.dg/vmx/sum2s.c (.../tags/gcc_4_8_2_release)

30516

+++ b/src/gcc/testsuite/gcc.dg/vmx/sum2s.c (.../branches/gcc-4_8-branch)

30517

@@ -0,0 +1,13 @@

30518

+#include "harness.h"

30519

+

30520

+static void test()

30521

+{

30522

+ vector signed int vsia = {-10,1,2,3};

30523

+ vector signed int vsib = {100,101,102,-103};

30524

+ vector signed int vsir;

30525

+ vector signed int vsier = {0,92,0,-98};

30526

+

30527

+ vsir = vec_sum2s (vsia, vsib);

30528

+

30529

+ check (vec_all_eq (vsir, vsier), "vsir");

30530

+}

30531

Index: gcc/testsuite/gcc.dg/vmx/merge-vsx-be-order.c

30532

===================================================================

30533

--- a/src/gcc/testsuite/gcc.dg/vmx/merge-vsx-be-order.c (.../tags/gcc_4_8_2_release)

30534

+++ b/src/gcc/testsuite/gcc.dg/vmx/merge-vsx-be-order.c (.../branches/gcc-4_8-branch)

30535

@@ -0,0 +1,84 @@

30536

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

30537

+/* { dg-require-effective-target powerpc_vsx_ok } */

30538

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mvsx" } */

30539

+

30540

+#include "harness.h"

30541

+

30542

+static int vec_long_long_eq (vector long long x, vector long long y)

30543

+{

30544

+ return (x[0] == y[0] && x[1] == y[1]);

30545

+}

30546

+

30547

+static int vec_double_eq (vector double x, vector double y)

30548

+{

30549

+ return (x[0] == y[0] && x[1] == y[1]);

30550

+}

30551

+

30552

+static void test()

30553

+{

30554

+ /* Input vectors. */

30555

+ vector long long vla = {-2,-1};

30556

+ vector long long vlb = {0,1};

30557

+ vector double vda = {-2.0,-1.0};

30558

+ vector double vdb = {0.0,1.0};

30559

+ vector unsigned int vuia = {0,1,2,3};

30560

+ vector unsigned int vuib = {4,5,6,7};

30561

+ vector signed int vsia = {-4,-3,-2,-1};

30562

+ vector signed int vsib = {0,1,2,3};

30563

+ vector float vfa = {-4.0,-3.0,-2.0,-1.0};

30564

+ vector float vfb = {0.0,1.0,2.0,3.0};

30565

+

30566

+ /* Result vectors. */

30567

+ vector long long vlh, vll;

30568

+ vector double vdh, vdl;

30569

+ vector unsigned int vuih, vuil;

30570

+ vector signed int vsih, vsil;

30571

+ vector float vfh, vfl;

30572

+

30573

+ /* Expected result vectors. */

30574

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

30575

+ vector long long vlrh = {1,-1};

30576

+ vector long long vlrl = {0,-2};

30577

+ vector double vdrh = {1.0,-1.0};

30578

+ vector double vdrl = {0.0,-2.0};

30579

+ vector unsigned int vuirh = {6,2,7,3};

30580

+ vector unsigned int vuirl = {4,0,5,1};

30581

+ vector signed int vsirh = {2,-2,3,-1};

30582

+ vector signed int vsirl = {0,-4,1,-3};

30583

+ vector float vfrh = {2.0,-2.0,3.0,-1.0};

30584

+ vector float vfrl = {0.0,-4.0,1.0,-3.0};

30585

+#else

30586

+ vector long long vlrh = {-2,0};

30587

+ vector long long vlrl = {-1,1};

30588

+ vector double vdrh = {-2.0,0.0};

30589

+ vector double vdrl = {-1.0,1.0};

30590

+ vector unsigned int vuirh = {0,4,1,5};

30591

+ vector unsigned int vuirl = {2,6,3,7};

30592

+ vector signed int vsirh = {-4,0,-3,1};

30593

+ vector signed int vsirl = {-2,2,-1,3};

30594

+ vector float vfrh = {-4.0,0.0,-3.0,1.0};

30595

+ vector float vfrl = {-2.0,2.0,-1.0,3.0};

30596

+#endif

30597

+

30598

+ vlh = vec_mergeh (vla, vlb);

30599

+ vll = vec_mergel (vla, vlb);

30600

+ vdh = vec_mergeh (vda, vdb);

30601

+ vdl = vec_mergel (vda, vdb);

30602

+ vuih = vec_mergeh (vuia, vuib);

30603

+ vuil = vec_mergel (vuia, vuib);

30604

+ vsih = vec_mergeh (vsia, vsib);

30605

+ vsil = vec_mergel (vsia, vsib);

30606

+ vfh = vec_mergeh (vfa, vfb );

30607

+ vfl = vec_mergel (vfa, vfb );

30608

+

30609

+ check (vec_long_long_eq (vlh, vlrh), "vlh");

30610

+ check (vec_long_long_eq (vll, vlrl), "vll");

30611

+ check (vec_double_eq (vdh, vdrh), "vdh" );

30612

+ check (vec_double_eq (vdl, vdrl), "vdl" );

30613

+ check (vec_all_eq (vuih, vuirh), "vuih");

30614

+ check (vec_all_eq (vuil, vuirl), "vuil");

30615

+ check (vec_all_eq (vsih, vsirh), "vsih");

30616

+ check (vec_all_eq (vsil, vsirl), "vsil");

30617

+ check (vec_all_eq (vfh, vfrh), "vfh");

30618

+ check (vec_all_eq (vfl, vfrl), "vfl");

30619

+}

30620

Index: gcc/testsuite/gcc.dg/vmx/mult-even-odd-be-order.c

30621

===================================================================

30622

--- a/src/gcc/testsuite/gcc.dg/vmx/mult-even-odd-be-order.c (.../tags/gcc_4_8_2_release)

30623

+++ b/src/gcc/testsuite/gcc.dg/vmx/mult-even-odd-be-order.c (.../branches/gcc-4_8-branch)

30624

@@ -0,0 +1,64 @@

30625

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */

30626

+

30627

+#include "harness.h"

30628

+

30629

+static void test()

30630

+{

30631

+ vector unsigned char vuca = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

30632

+ vector unsigned char vucb = {2,3,2,3,2,3,2,3,2,3,2,3,2,3,2,3};

30633

+ vector signed char vsca = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};

30634

+ vector signed char vscb = {2,-3,2,-3,2,-3,2,-3,2,-3,2,-3,2,-3,2,-3};

30635

+ vector unsigned short vusa = {0,1,2,3,4,5,6,7};

30636

+ vector unsigned short vusb = {2,3,2,3,2,3,2,3};

30637

+ vector signed short vssa = {-4,-3,-2,-1,0,1,2,3};

30638

+ vector signed short vssb = {2,-3,2,-3,2,-3,2,-3};

30639

+ vector unsigned short vuse, vuso;

30640

+ vector signed short vsse, vsso;

30641

+ vector unsigned int vuie, vuio;

30642

+ vector signed int vsie, vsio;

30643

+

30644

+ vuse = vec_mule (vuca, vucb);

30645

+ vuso = vec_mulo (vuca, vucb);

30646

+ vsse = vec_mule (vsca, vscb);

30647

+ vsso = vec_mulo (vsca, vscb);

30648

+ vuie = vec_mule (vusa, vusb);

30649

+ vuio = vec_mulo (vusa, vusb);

30650

+ vsie = vec_mule (vssa, vssb);

30651

+ vsio = vec_mulo (vssa, vssb);

30652

+

30653

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

30654

+ check (vec_all_eq (vuse,

30655

+ ((vector unsigned short){3,9,15,21,27,33,39,45})),

30656

+ "vuse");

30657

+ check (vec_all_eq (vuso,

30658

+ ((vector unsigned short){0,4,8,12,16,20,24,28})),

30659

+ "vuso");

30660

+ check (vec_all_eq (vsse,

30661

+ ((vector signed short){21,15,9,3,-3,-9,-15,-21})),

30662

+ "vsse");

30663

+ check (vec_all_eq (vsso,

30664

+ ((vector signed short){-16,-12,-8,-4,0,4,8,12})),

30665

+ "vsso");

30666

+ check (vec_all_eq (vuie, ((vector unsigned int){3,9,15,21})), "vuie");

30667

+ check (vec_all_eq (vuio, ((vector unsigned int){0,4,8,12})), "vuio");

30668

+ check (vec_all_eq (vsie, ((vector signed int){9,3,-3,-9})), "vsie");

30669

+ check (vec_all_eq (vsio, ((vector signed int){-8,-4,0,4})), "vsio");

30670

+#else

30671

+ check (vec_all_eq (vuse,

30672

+ ((vector unsigned short){0,4,8,12,16,20,24,28})),

30673

+ "vuse");

30674

+ check (vec_all_eq (vuso,

30675

+ ((vector unsigned short){3,9,15,21,27,33,39,45})),

30676

+ "vuso");

30677

+ check (vec_all_eq (vsse,

30678

+ ((vector signed short){-16,-12,-8,-4,0,4,8,12})),

30679

+ "vsse");

30680

+ check (vec_all_eq (vsso,

30681

+ ((vector signed short){21,15,9,3,-3,-9,-15,-21})),

30682

+ "vsso");

30683

+ check (vec_all_eq (vuie, ((vector unsigned int){0,4,8,12})), "vuie");

30684

+ check (vec_all_eq (vuio, ((vector unsigned int){3,9,15,21})), "vuio");

30685

+ check (vec_all_eq (vsie, ((vector signed int){-8,-4,0,4})), "vsie");

30686

+ check (vec_all_eq (vsio, ((vector signed int){9,3,-3,-9})), "vsio");

30687

+#endif

30688

+}

30689

Index: gcc/testsuite/gcc.dg/vmx/insert-vsx.c

30690

===================================================================

30691

--- a/src/gcc/testsuite/gcc.dg/vmx/insert-vsx.c (.../tags/gcc_4_8_2_release)

30692

+++ b/src/gcc/testsuite/gcc.dg/vmx/insert-vsx.c (.../branches/gcc-4_8-branch)

30693

@@ -0,0 +1,28 @@

30694

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

30695

+/* { dg-require-effective-target powerpc_vsx_ok } */

30696

+/* { dg-options "-maltivec -mabi=altivec -std=gnu99 -mvsx" } */

30697

+

30698

+#include "harness.h"

30699

+

30700

+static int vec_long_long_eq (vector long long x, vector long long y)

30701

+{

30702

+ return (x[0] == y[0] && x[1] == y[1]);

30703

+}

30704

+

30705

+static int vec_dbl_eq (vector double x, vector double y)

30706

+{

30707

+ return (x[0] == y[0] && x[1] == y[1]);

30708

+}

30709

+

30710

+static void test()

30711

+{

30712

+ vector long long vl = {0, 1};

30713

+ vector double vd = {0.0, 1.0};

30714

+ vector long long vlr = vec_insert (2, vl, 0);

30715

+ vector double vdr = vec_insert (2.0, vd, 1);

30716

+ vector long long vler = {2, 1};

30717

+ vector double vder = {0.0, 2.0};

30718

+

30719

+ check (vec_long_long_eq (vlr, vler), "vl");

30720

+ check (vec_dbl_eq (vdr, vder), "vd");

30721

+}

30722

Index: gcc/testsuite/gcc.dg/vmx/vsums-be-order.c

30723

===================================================================

30724

--- a/src/gcc/testsuite/gcc.dg/vmx/vsums-be-order.c (.../tags/gcc_4_8_2_release)

30725

+++ b/src/gcc/testsuite/gcc.dg/vmx/vsums-be-order.c (.../branches/gcc-4_8-branch)

30726

@@ -0,0 +1,20 @@

30727

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */

30728

+

30729

+#include "harness.h"

30730

+

30731

+static void test()

30732

+{

30733

+ vector signed int va = {-7,11,-13,17};

30734

+

30735

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

30736

+ vector signed int vb = {128,0,0,0};

30737

+ vector signed int evd = {136,0,0,0};

30738

+#else

30739

+ vector signed int vb = {0,0,0,128};

30740

+ vector signed int evd = {0,0,0,136};

30741

+#endif

30742

+

30743

+ vector signed int vd = vec_sums (va, vb);

30744

+

30745

+ check (vec_all_eq (vd, evd), "sums");

30746

+}

30747

Index: gcc/testsuite/gcc.dg/vmx/ldl-vsx.c

30748

===================================================================

30749

--- a/src/gcc/testsuite/gcc.dg/vmx/ldl-vsx.c (.../tags/gcc_4_8_2_release)

30750

+++ b/src/gcc/testsuite/gcc.dg/vmx/ldl-vsx.c (.../branches/gcc-4_8-branch)

30751

@@ -0,0 +1,39 @@

30752

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

30753

+/* { dg-require-effective-target powerpc_vsx_ok } */

30754

+/* { dg-options "-maltivec -mabi=altivec -std=gnu99 -mvsx" } */

30755

+

30756

+#include "harness.h"

30757

+

30758

+static unsigned long long svul[2] __attribute__ ((aligned (16)));

30759

+static double svd[2] __attribute__ ((aligned (16)));

30760

+

30761

+static void init ()

30762

+{

30763

+ unsigned int i;

30764

+ for (i = 0; i < 2; ++i)

30765

+ {

30766

+ svul[i] = i;

30767

+ svd[i] = i * 1.0;

30768

+ }

30769

+}

30770

+

30771

+static void test ()

30772

+{

30773

+ vector unsigned long long evul = {0,1};

30774

+ vector double evd = {0.0,1.0};

30775

+

30776

+ vector unsigned long long vul;

30777

+ vector double vd;

30778

+ unsigned i;

30779

+

30780

+ init ();

30781

+

30782

+ vul = vec_ldl (0, (vector unsigned long long *)svul);

30783

+ vd = vec_ldl (0, (vector double *)svd);

30784

+

30785

+ for (i = 0; i < 2; ++i)

30786

+ {

30787

+ check (vul[i] == evul[i], "vul");

30788

+ check (vd[i] == evd[i], "vd" );

30789

+ }

30790

+}

30791

Index: gcc/testsuite/gcc.dg/vmx/ste.c

30792

===================================================================

30793

--- a/src/gcc/testsuite/gcc.dg/vmx/ste.c (.../tags/gcc_4_8_2_release)

30794

+++ b/src/gcc/testsuite/gcc.dg/vmx/ste.c (.../branches/gcc-4_8-branch)

30795

@@ -0,0 +1,41 @@

30796

+#include "harness.h"

30797

+

30798

+static unsigned char svuc[16] __attribute__ ((aligned (16)));

30799

+static signed char svsc[16] __attribute__ ((aligned (16)));

30800

+static unsigned short svus[8] __attribute__ ((aligned (16)));

30801

+static signed short svss[8] __attribute__ ((aligned (16)));

30802

+static unsigned int svui[4] __attribute__ ((aligned (16)));

30803

+static signed int svsi[4] __attribute__ ((aligned (16)));

30804

+static float svf[4] __attribute__ ((aligned (16)));

30805

+

30806

+static void check_arrays ()

30807

+{

30808

+ check (svuc[9] == 9, "svuc");

30809

+ check (svsc[14] == 6, "svsc");

30810

+ check (svus[7] == 7, "svus");

30811

+ check (svss[1] == -3, "svss");

30812

+ check (svui[3] == 3, "svui");

30813

+ check (svsi[2] == 0, "svsi");

30814

+ check (svf[0] == 0.0, "svf");

30815

+}

30816

+

30817

+static void test ()

30818

+{

30819

+ vector unsigned char vuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

30820

+ vector signed char vsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};

30821

+ vector unsigned short vus = {0,1,2,3,4,5,6,7};

30822

+ vector signed short vss = {-4,-3,-2,-1,0,1,2,3};

30823

+ vector unsigned int vui = {0,1,2,3};

30824

+ vector signed int vsi = {-2,-1,0,1};

30825

+ vector float vf = {0.0,1.0,2.0,3.0};

30826

+

30827

+ vec_ste (vuc, 9*1, (unsigned char *)svuc);

30828

+ vec_ste (vsc, 14*1, (signed char *)svsc);

30829

+ vec_ste (vus, 7*2, (unsigned short *)svus);

30830

+ vec_ste (vss, 1*2, (signed short *)svss);

30831

+ vec_ste (vui, 3*4, (unsigned int *)svui);

30832

+ vec_ste (vsi, 2*4, (signed int *)svsi);

30833

+ vec_ste (vf, 0*4, (float *)svf);

30834

+

30835

+ check_arrays ();

30836

+}

30837

Index: gcc/testsuite/gcc.dg/vmx/lde-be-order.c

30838

===================================================================

30839

--- a/src/gcc/testsuite/gcc.dg/vmx/lde-be-order.c (.../tags/gcc_4_8_2_release)

30840

+++ b/src/gcc/testsuite/gcc.dg/vmx/lde-be-order.c (.../branches/gcc-4_8-branch)

30841

@@ -0,0 +1,73 @@

30842

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */

30843

+

30844

+#include "harness.h"

30845

+

30846

+static unsigned char svuc[16] __attribute__ ((aligned (16)));

30847

+static signed char svsc[16] __attribute__ ((aligned (16)));

30848

+static unsigned short svus[8] __attribute__ ((aligned (16)));

30849

+static signed short svss[8] __attribute__ ((aligned (16)));

30850

+static unsigned int svui[4] __attribute__ ((aligned (16)));

30851

+static signed int svsi[4] __attribute__ ((aligned (16)));

30852

+static float svf[4] __attribute__ ((aligned (16)));

30853

+

30854

+static void init ()

30855

+{

30856

+ int i;

30857

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

30858

+ for (i = 15; i >= 0; --i)

30859

+#else

30860

+ for (i = 0; i < 16; ++i)

30861

+#endif

30862

+ {

30863

+ svuc[i] = i;

30864

+ svsc[i] = i - 8;

30865

+ }

30866

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

30867

+ for (i = 7; i >= 0; --i)

30868

+#else

30869

+ for (i = 0; i < 8; ++i)

30870

+#endif

30871

+ {

30872

+ svus[i] = i;

30873

+ svss[i] = i - 4;

30874

+ }

30875

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

30876

+ for (i = 3; i >= 0; --i)

30877

+#else

30878

+ for (i = 0; i < 4; ++i)

30879

+#endif

30880

+ {

30881

+ svui[i] = i;

30882

+ svsi[i] = i - 2;

30883

+ svf[i] = i * 1.0f;

30884

+ }

30885

+}

30886

+

30887

+static void test ()

30888

+{

30889

+ vector unsigned char vuc;

30890

+ vector signed char vsc;

30891

+ vector unsigned short vus;

30892

+ vector signed short vss;

30893

+ vector unsigned int vui;

30894

+ vector signed int vsi;

30895

+ vector float vf;

30896

+

30897

+ init ();

30898

+

30899

+ vuc = vec_lde (9*1, (unsigned char *)svuc);

30900

+ vsc = vec_lde (14*1, (signed char *)svsc);

30901

+ vus = vec_lde (7*2, (unsigned short *)svus);

30902

+ vss = vec_lde (1*2, (signed short *)svss);

30903

+ vui = vec_lde (3*4, (unsigned int *)svui);

30904

+ vsi = vec_lde (2*4, (signed int *)svsi);

30905

+ vf = vec_lde (0*4, (float *)svf);

30906

+

30907

+ check (vec_extract (vuc, 9) == 9, "vuc");

30908

+ check (vec_extract (vsc, 14) == 6, "vsc");

30909

+ check (vec_extract (vus, 7) == 7, "vus");

30910

+ check (vec_extract (vss, 1) == -3, "vss");

30911

+ check (vec_extract (vui, 3) == 3, "vui");

30912

+ check (vec_extract (vsi, 2) == 0, "vsi");

30913

+ check (vec_extract (vf, 0) == 0.0, "vf");

30914

+}

30915

Index: gcc/testsuite/gcc.dg/vmx/splat-vsx.c

30916

===================================================================

30917

--- a/src/gcc/testsuite/gcc.dg/vmx/splat-vsx.c (.../tags/gcc_4_8_2_release)

30918

+++ b/src/gcc/testsuite/gcc.dg/vmx/splat-vsx.c (.../branches/gcc-4_8-branch)

30919

@@ -0,0 +1,31 @@

30920

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

30921

+/* { dg-require-effective-target powerpc_vsx_ok } */

30922

+/* { dg-options "-maltivec -mabi=altivec -std=gnu99 -mvsx" } */

30923

+

30924

+#include "harness.h"

30925

+

30926

+static void test()

30927

+{

30928

+ /* Input vectors. */

30929

+ vector unsigned int vui = {0,1,2,3};

30930

+ vector signed int vsi = {-2,-1,0,1};

30931

+ vector float vf = {-2.0,-1.0,0.0,1.0};

30932

+

30933

+ /* Result vectors. */

30934

+ vector unsigned int vuir;

30935

+ vector signed int vsir;

30936

+ vector float vfr;

30937

+

30938

+ /* Expected result vectors. */

30939

+ vector unsigned int vuier = {2,2,2,2};

30940

+ vector signed int vsier = {1,1,1,1};

30941

+ vector float vfer = {-1.0,-1.0,-1.0,-1.0};

30942

+

30943

+ vuir = vec_splat (vui, 2);

30944

+ vsir = vec_splat (vsi, 3);

30945

+ vfr = vec_splat (vf, 1);

30946

+

30947

+ check (vec_all_eq (vuir, vuier), "vui");

30948

+ check (vec_all_eq (vsir, vsier), "vsi");

30949

+ check (vec_all_eq (vfr, vfer ), "vf");

30950

+}

30951

Index: gcc/testsuite/gcc.dg/vmx/sum2s-be-order.c

30952

===================================================================

30953

--- a/src/gcc/testsuite/gcc.dg/vmx/sum2s-be-order.c (.../tags/gcc_4_8_2_release)

30954

+++ b/src/gcc/testsuite/gcc.dg/vmx/sum2s-be-order.c (.../branches/gcc-4_8-branch)

30955

@@ -0,0 +1,19 @@

30956

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */

30957

+

30958

+#include "harness.h"

30959

+

30960

+static void test()

30961

+{

30962

+ vector signed int vsia = {-10,1,2,3};

30963

+ vector signed int vsib = {100,101,102,-103};

30964

+ vector signed int vsir;

30965

+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__

30966

+ vector signed int vsier = {91,0,107,0};

30967

+#else

30968

+ vector signed int vsier = {0,92,0,-98};

30969

+#endif

30970

+

30971

+ vsir = vec_sum2s (vsia, vsib);

30972

+

30973

+ check (vec_all_eq (vsir, vsier), "vsir");

30974

+}

30975

Index: gcc/testsuite/gcc.dg/vmx/merge-vsx.c

30976

===================================================================

30977

--- a/src/gcc/testsuite/gcc.dg/vmx/merge-vsx.c (.../tags/gcc_4_8_2_release)

30978

+++ b/src/gcc/testsuite/gcc.dg/vmx/merge-vsx.c (.../branches/gcc-4_8-branch)

30979

@@ -0,0 +1,71 @@

30980

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

30981

+/* { dg-require-effective-target powerpc_vsx_ok } */

30982

+/* { dg-options "-maltivec -mabi=altivec -std=gnu99 -mvsx" } */

30983

+

30984

+#include "harness.h"

30985

+

30986

+static int vec_long_long_eq (vector long long x, vector long long y)

30987

+{

30988

+ return (x[0] == y[0] && x[1] == y[1]);

30989

+}

30990

+

30991

+static int vec_double_eq (vector double x, vector double y)

30992

+{

30993

+ return (x[0] == y[0] && x[1] == y[1]);

30994

+}

30995

+

30996

+static void test()

30997

+{

30998

+ /* Input vectors. */

30999

+ vector long long vla = {-2,-1};

31000

+ vector long long vlb = {0,1};

31001

+ vector double vda = {-2.0,-1.0};

31002

+ vector double vdb = {0.0,1.0};

31003

+ vector unsigned int vuia = {0,1,2,3};

31004

+ vector unsigned int vuib = {4,5,6,7};

31005

+ vector signed int vsia = {-4,-3,-2,-1};

31006

+ vector signed int vsib = {0,1,2,3};

31007

+ vector float vfa = {-4.0,-3.0,-2.0,-1.0};

31008

+ vector float vfb = {0.0,1.0,2.0,3.0};

31009

+

31010

+ /* Result vectors. */

31011

+ vector long long vlh, vll;

31012

+ vector double vdh, vdl;

31013

+ vector unsigned int vuih, vuil;

31014

+ vector signed int vsih, vsil;

31015

+ vector float vfh, vfl;

31016

+

31017

+ /* Expected result vectors. */

31018

+ vector long long vlrh = {-2,0};

31019

+ vector long long vlrl = {-1,1};

31020

+ vector double vdrh = {-2.0,0.0};

31021

+ vector double vdrl = {-1.0,1.0};

31022

+ vector unsigned int vuirh = {0,4,1,5};

31023

+ vector unsigned int vuirl = {2,6,3,7};

31024

+ vector signed int vsirh = {-4,0,-3,1};

31025

+ vector signed int vsirl = {-2,2,-1,3};

31026

+ vector float vfrh = {-4.0,0.0,-3.0,1.0};

31027

+ vector float vfrl = {-2.0,2.0,-1.0,3.0};

31028

+

31029

+ vlh = vec_mergeh (vla, vlb);

31030

+ vll = vec_mergel (vla, vlb);

31031

+ vdh = vec_mergeh (vda, vdb);

31032

+ vdl = vec_mergel (vda, vdb);

31033

+ vuih = vec_mergeh (vuia, vuib);

31034

+ vuil = vec_mergel (vuia, vuib);

31035

+ vsih = vec_mergeh (vsia, vsib);

31036

+ vsil = vec_mergel (vsia, vsib);

31037

+ vfh = vec_mergeh (vfa, vfb );

31038

+ vfl = vec_mergel (vfa, vfb );

31039

+

31040

+ check (vec_long_long_eq (vlh, vlrh), "vlh");

31041

+ check (vec_long_long_eq (vll, vlrl), "vll");

31042

+ check (vec_double_eq (vdh, vdrh), "vdh" );

31043

+ check (vec_double_eq (vdl, vdrl), "vdl" );

31044

+ check (vec_all_eq (vuih, vuirh), "vuih");

31045

+ check (vec_all_eq (vuil, vuirl), "vuil");

31046

+ check (vec_all_eq (vsih, vsirh), "vsih");

31047

+ check (vec_all_eq (vsil, vsirl), "vsil");

31048

+ check (vec_all_eq (vfh, vfrh), "vfh");

31049

+ check (vec_all_eq (vfl, vfrl), "vfl");

31050

+}

31051

Index: gcc/testsuite/gcc.dg/vmx/stl-vsx.c

31052

===================================================================

31053

--- a/src/gcc/testsuite/gcc.dg/vmx/stl-vsx.c (.../tags/gcc_4_8_2_release)

31054

+++ b/src/gcc/testsuite/gcc.dg/vmx/stl-vsx.c (.../branches/gcc-4_8-branch)

31055

@@ -0,0 +1,29 @@

31056

+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */

31057

+/* { dg-require-effective-target powerpc_vsx_ok } */

31058

+/* { dg-options "-maltivec -mabi=altivec -std=gnu99 -mvsx" } */

31059

+

31060

+#include "harness.h"

31061

+

31062

+static unsigned long long svul[2] __attribute__ ((aligned (16)));

31063

+static double svd[2] __attribute__ ((aligned (16)));

31064

+

31065

+static void check_arrays ()

31066

+{

31067

+ unsigned int i;

31068

+ for (i = 0; i < 2; ++i)

31069

+ {

31070

+ check (svul[i] == i, "svul");

31071

+ check (svd[i] == i * 1.0, "svd");

31072

+ }

31073

+}

31074

+

31075

+static void test ()

31076

+{

31077

+ vector unsigned long long vul = {0,1};

31078

+ vector double vd = {0.0,1.0};

31079

+

31080

+ vec_stl (vul, 0, (vector unsigned long long *)svul);

31081

+ vec_stl (vd, 0, (vector double *)svd);

31082

+

31083

+ check_arrays ();

31084

+}

31085

Index: gcc/testsuite/gcc.dg/strlenopt-4gf.c

31086

===================================================================

31087

--- a/src/gcc/testsuite/gcc.dg/strlenopt-4gf.c (.../tags/gcc_4_8_2_release)

31088

+++ b/src/gcc/testsuite/gcc.dg/strlenopt-4gf.c (.../branches/gcc-4_8-branch)

31089

@@ -7,13 +7,13 @@

31090

#include "strlenopt-4.c"

31091

31092

/* { dg-final { scan-tree-dump-times "strlen \\(" 1 "strlen" } } */

31093

-/* { dg-final { scan-tree-dump-times "__memcpy_chk \\(" 4 "strlen" } } */

31094

-/* { dg-final { scan-tree-dump-times "__strcpy_chk \\(" 1 "strlen" } } */

31095

+/* { dg-final { scan-tree-dump-times "__memcpy_chk \\(" 0 "strlen" } } */

31096

+/* { dg-final { scan-tree-dump-times "__strcpy_chk \\(" 0 "strlen" } } */

31097

/* { dg-final { scan-tree-dump-times "__strcat_chk \\(" 0 "strlen" } } */

31098

/* { dg-final { scan-tree-dump-times "strchr \\(" 0 "strlen" } } */

31099

-/* { dg-final { scan-tree-dump-times "__stpcpy_chk \\(" 5 "strlen" } } */

31100

-/* { dg-final { scan-tree-dump-times "memcpy \\(" 0 "strlen" } } */

31101

-/* { dg-final { scan-tree-dump-times "strcpy \\(" 0 "strlen" } } */

31102

+/* { dg-final { scan-tree-dump-times "__stpcpy_chk \\(" 0 "strlen" } } */

31103

+/* { dg-final { scan-tree-dump-times "memcpy \\(" 4 "strlen" } } */

31104

+/* { dg-final { scan-tree-dump-times "strcpy \\(" 1 "strlen" } } */

31105

/* { dg-final { scan-tree-dump-times "strcat \\(" 0 "strlen" } } */

31106

-/* { dg-final { scan-tree-dump-times "stpcpy \\(" 0 "strlen" } } */

31107

+/* { dg-final { scan-tree-dump-times "stpcpy \\(" 5 "strlen" } } */

31108

/* { dg-final { cleanup-tree-dump "strlen" } } */

31109

Index: gcc/testsuite/gcc.dg/pr59351.c

31110

===================================================================

31111

--- a/src/gcc/testsuite/gcc.dg/pr59351.c (.../tags/gcc_4_8_2_release)

31112

+++ b/src/gcc/testsuite/gcc.dg/pr59351.c (.../branches/gcc-4_8-branch)

31113

@@ -0,0 +1,8 @@

31114

+/* { dg-do compile } */

31115

+/* { dg-options "-std=c99 -Wpedantic" } */

31116

+

31117

+unsigned int

31118

+foo (void)

31119

+{

31120

+ return sizeof ((int[]) {}); /* { dg-warning "ISO C forbids empty initializer braces" } */

31121

+}

31122

Index: gcc/testsuite/gcc.dg/debug/dwarf2/dwarf2-macro2.c

31123

===================================================================

31124

--- a/src/gcc/testsuite/gcc.dg/debug/dwarf2/dwarf2-macro2.c (.../tags/gcc_4_8_2_release)

31125

+++ b/src/gcc/testsuite/gcc.dg/debug/dwarf2/dwarf2-macro2.c (.../branches/gcc-4_8-branch)

31126

@@ -0,0 +1,7 @@

31127

+/* Test to make sure the macro info includes the predefined macros with line number 0. */

31128

+/* { dg-do compile } */

31129

+/* { dg-options "-g3 -gdwarf-2 -dA -fverbose-asm" } */

31130

+/* { dg-final { scan-assembler "At line number 0" } } */

31131

+

31132

+#define FOO 1

31133

+int i;

31134

Index: gcc/testsuite/gcc.dg/Wstrict-aliasing-bogus-ref-all-2.c

31135

===================================================================

31136

--- a/src/gcc/testsuite/gcc.dg/Wstrict-aliasing-bogus-ref-all-2.c (.../tags/gcc_4_8_2_release)

31137

+++ b/src/gcc/testsuite/gcc.dg/Wstrict-aliasing-bogus-ref-all-2.c (.../branches/gcc-4_8-branch)

31138

@@ -1,6 +1,7 @@

31139

/* { dg-do compile } */

31140

/* { dg-options "-O2 -Wall" } */

31141

/* { dg-options "-O2 -Wall -mabi=altivec" { target { { powerpc*-*-linux* } && ilp32 } } } */

31142

+/* { dg-options "-O2 -Wall -msse2" { target { i?86-*-* x86_64-*-* } } } */

31143

31144

typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));

31145

31146

Index: gcc/testsuite/gcc.dg/builtin-object-size-8.c

31147

===================================================================

31148

--- a/src/gcc/testsuite/gcc.dg/builtin-object-size-8.c (.../tags/gcc_4_8_2_release)

31149

+++ b/src/gcc/testsuite/gcc.dg/builtin-object-size-8.c (.../branches/gcc-4_8-branch)

31150

@@ -1,4 +1,4 @@

31151

-/* { dg-do run { xfail *-*-* } } */

31152

+/* { dg-do run } */

31153

/* { dg-options "-O2" } */

31154

31155

typedef __SIZE_TYPE__ size_t;

31156

Index: gcc/testsuite/gcc.dg/20050922-2.c

31157

===================================================================

31158

--- a/src/gcc/testsuite/gcc.dg/20050922-2.c (.../tags/gcc_4_8_2_release)

31159

+++ b/src/gcc/testsuite/gcc.dg/20050922-2.c (.../branches/gcc-4_8-branch)

31160

@@ -4,7 +4,8 @@

31161

/* { dg-do run } */

31162

/* { dg-options "-O1 -std=c99" } */

31163

31164

-#include <stdlib.h>

31165

+extern void abort (void);

31166

+extern void exit (int);

31167

31168

#if __INT_MAX__ == 2147483647

31169

typedef unsigned int uint32_t;

31170

Index: gcc/testsuite/gcc.dg/graphite/pr59817-2.c

31171

===================================================================

31172

--- a/src/gcc/testsuite/gcc.dg/graphite/pr59817-2.c (.../tags/gcc_4_8_2_release)

31173

+++ b/src/gcc/testsuite/gcc.dg/graphite/pr59817-2.c (.../branches/gcc-4_8-branch)

31174

@@ -0,0 +1,15 @@

31175

+/* { dg-do compile } */

31176

+/* { dg-options "-O2 -floop-interchange" } */

31177

+

31178

+void

31179

+xl(void)

31180

+{

31181

+ static int j3;

31182

+ for (j3 = 0; j3 < 1; ++j3) {

31183

+ static int f2;

31184

+ static int w7;

31185

+ short int b5;

31186

+ int ok;

31187

+ f2 = (b5 += ok) ? (w7 = 0): (w7 ? 0 : (f2 = ok));

31188

+ }

31189

+}

31190

Index: gcc/testsuite/gcc.dg/graphite/pr60740.c

31191

===================================================================

31192

--- a/src/gcc/testsuite/gcc.dg/graphite/pr60740.c (.../tags/gcc_4_8_2_release)

31193

+++ b/src/gcc/testsuite/gcc.dg/graphite/pr60740.c (.../branches/gcc-4_8-branch)

31194

@@ -0,0 +1,16 @@

31195

+/* { dg-options "-O2 -floop-interchange" } */

31196

+

31197

+int **db6 = 0;

31198

+

31199

+void

31200

+k26(void)

31201

+{

31202

+ static int geb = 0;

31203

+ int *a22 = &geb;

31204

+ int **l30 = &a22;

31205

+ int *c4b;

31206

+ int ndf;

31207

+ for (ndf = 0; ndf <= 1; ++ndf)

31208

+ *c4b = (db6 == l30) && (*a22)--;

31209

+}

31210

+

31211

Index: gcc/testsuite/gcc.dg/graphite/pr59817-1.c

31212

===================================================================

31213

--- a/src/gcc/testsuite/gcc.dg/graphite/pr59817-1.c (.../tags/gcc_4_8_2_release)

31214

+++ b/src/gcc/testsuite/gcc.dg/graphite/pr59817-1.c (.../branches/gcc-4_8-branch)

31215

@@ -0,0 +1,16 @@

31216

+/* { dg-do compile } */

31217

+/* { dg-options "-O2 -floop-interchange" } */

31218

+

31219

+int kd;

31220

+

31221

+void

31222

+n2(void)

31223

+{

31224

+ static int so;

31225

+ static short int i5;

31226

+ int wj;

31227

+ int *il;

31228

+ int *nk = &so;

31229

+ for (wj = 0; wj < 2; ++wj)

31230

+ *nk = ((i5 += *il) || kd );

31231

+}

31232

Index: gcc/testsuite/gcc.dg/pr59860.c

31233

===================================================================

31234

--- a/src/gcc/testsuite/gcc.dg/pr59860.c (.../tags/gcc_4_8_2_release)

31235

+++ b/src/gcc/testsuite/gcc.dg/pr59860.c (.../branches/gcc-4_8-branch)

31236

@@ -0,0 +1,15 @@

31237

+/* { dg-do compile } */

31238

+/* { dg-options "-O" } */

31239

+

31240

+extern __inline __attribute__ ((__always_inline__)) __attribute__ ((__gnu_inline__)) __attribute__ ((__artificial__)) char * __attribute__ ((__nothrow__ , __leaf__))

31241

+strcat (char *__restrict __dest, const char *__restrict __src)

31242

+{

31243

+ return __builtin___strcat_chk (__dest, __src, __builtin_object_size (__dest, 2 > 1));

31244

+}

31245

+static char raw_decode;

31246

+void foo (char **argv, char *outfilename)

31247

+{

31248

+ if (**argv == 'r')

31249

+ raw_decode = 1;

31250

+ strcat (outfilename, raw_decode ? ".raw" : ".wav");

31251

+}

31252

Index: gcc/testsuite/gcc.dg/stack-usage-1.c

31253

===================================================================

31254

--- a/src/gcc/testsuite/gcc.dg/stack-usage-1.c (.../tags/gcc_4_8_2_release)

31255

+++ b/src/gcc/testsuite/gcc.dg/stack-usage-1.c (.../branches/gcc-4_8-branch)

31256

@@ -38,7 +38,11 @@

31257

# endif

31258

#elif defined (__powerpc64__) || defined (__ppc64__) || defined (__POWERPC64__) \

31259

|| defined (__PPC64__)

31260

-# define SIZE 180

31261

+# if _CALL_ELF == 2

31262

+# define SIZE 208

31263

+# else

31264

+# define SIZE 180

31265

+# endif

31266

#elif defined (__powerpc__) || defined (__PPC__) || defined (__ppc__) \

31267

|| defined (__POWERPC__) || defined (PPC) || defined (_IBMR2)

31268

# if defined (__ALTIVEC__)

31269

Index: gcc/testsuite/gcc.dg/pr59011.c

31270

===================================================================

31271

--- a/src/gcc/testsuite/gcc.dg/pr59011.c (.../tags/gcc_4_8_2_release)

31272

+++ b/src/gcc/testsuite/gcc.dg/pr59011.c (.../branches/gcc-4_8-branch)

31273

@@ -0,0 +1,22 @@

31274

+/* PR middle-end/59011 */

31275

+/* { dg-do compile } */

31276

+/* { dg-options "-std=gnu99" } */

31277

+

31278

+void

31279

+foo (int m)

31280

+{

31281

+ int a[m];

31282

+ void

31283

+ bar (void)

31284

+ {

31285

+ {

31286

+ int

31287

+ baz (void)

31288

+ {

31289

+ return a[0];

31290

+ }

31291

+ }

31292

+ a[0] = 42;

31293

+ }

31294

+ bar ();

31295

+}

31296

Index: gcc/testsuite/gcc.dg/pr58805.c

31297

===================================================================

31298

--- a/src/gcc/testsuite/gcc.dg/pr58805.c (.../tags/gcc_4_8_2_release)

31299

+++ b/src/gcc/testsuite/gcc.dg/pr58805.c (.../branches/gcc-4_8-branch)

31300

@@ -0,0 +1,24 @@

31301

+/* { dg-do compile } */

31302

+/* { dg-options "-O2 -ftree-tail-merge -fdump-tree-pre" } */

31303

+

31304

+/* Type that matches the 'p' constraint. */

31305

+#define TYPE void *

31306

+

31307

+static inline

31308

+void bar (TYPE *r)

31309

+{

31310

+ TYPE t;

31311

+ __asm__ ("" : "=&p" (t), "=p" (*r));

31312

+}

31313

+

31314

+void

31315

+foo (int n, TYPE *x, TYPE *y)

31316

+{

31317

+ if (n == 0)

31318

+ bar (x);

31319

+ else

31320

+ bar (y);

31321

+}

31322

+

31323

+/* { dg-final { scan-tree-dump-times "__asm__" 2 "pre"} } */

31324

+/* { dg-final { cleanup-tree-dump "pre" } } */

31325

Index: gcc/testsuite/gcc.dg/strlenopt-14gf.c

31326

===================================================================

31327

--- a/src/gcc/testsuite/gcc.dg/strlenopt-14gf.c (.../tags/gcc_4_8_2_release)

31328

+++ b/src/gcc/testsuite/gcc.dg/strlenopt-14gf.c (.../branches/gcc-4_8-branch)

31329

@@ -11,14 +11,14 @@

31330

memcpy. */

31331

/* { dg-final { scan-tree-dump-times "strlen \\(" 4 "strlen" } } */

31332

/* { dg-final { scan-tree-dump-times "__memcpy_chk \\(" 0 "strlen" } } */

31333

-/* { dg-final { scan-tree-dump-times "__mempcpy_chk \\(" 2 "strlen" } } */

31334

+/* { dg-final { scan-tree-dump-times "__mempcpy_chk \\(" 0 "strlen" } } */

31335

/* { dg-final { scan-tree-dump-times "__strcpy_chk \\(" 0 "strlen" } } */

31336

/* { dg-final { scan-tree-dump-times "__strcat_chk \\(" 0 "strlen" } } */

31337

/* { dg-final { scan-tree-dump-times "strchr \\(" 0 "strlen" } } */

31338

-/* { dg-final { scan-tree-dump-times "__stpcpy_chk \\(" 3 "strlen" } } */

31339

-/* { dg-final { scan-tree-dump-times "memcpy \\(" 0 "strlen" } } */

31340

-/* { dg-final { scan-tree-dump-times "mempcpy \\(" 0 "strlen" } } */

31341

+/* { dg-final { scan-tree-dump-times "__stpcpy_chk \\(" 0 "strlen" } } */

31342

+/* { dg-final { scan-tree-dump-times "memcpy \\(" 1 "strlen" } } */

31343

+/* { dg-final { scan-tree-dump-times "mempcpy \\(" 2 "strlen" } } */

31344

/* { dg-final { scan-tree-dump-times "strcpy \\(" 0 "strlen" } } */

31345

/* { dg-final { scan-tree-dump-times "strcat \\(" 0 "strlen" } } */

31346

-/* { dg-final { scan-tree-dump-times "stpcpy \\(" 0 "strlen" } } */

31347

+/* { dg-final { scan-tree-dump-times "stpcpy \\(" 2 "strlen" } } */

31348

/* { dg-final { cleanup-tree-dump "strlen" } } */

31349

Index: gcc/testsuite/gcc.dg/torture/pr57425-2.c

31350

===================================================================

31351

--- a/src/gcc/testsuite/gcc.dg/torture/pr57425-2.c (.../tags/gcc_4_8_2_release)

31352

+++ b/src/gcc/testsuite/gcc.dg/torture/pr57425-2.c (.../branches/gcc-4_8-branch)

31353

@@ -0,0 +1,31 @@

31354

+/* { dg-do run } */

31355

+

31356

+extern void abort (void) __attribute__((noreturn));

31357

+

31358

+int

31359

+main ()

31360

+{

31361

+ int sum = 0;

31362

+ {

31363

+ int a[20];

31364

+ int *c;

31365

+ c = a;

31366

+ asm ("": "=r" (c):"0" (c));

31367

+ *c = 0;

31368

+ asm ("": "=r" (c):"0" (c));

31369

+ sum += *c;

31370

+ }

31371

+ {

31372

+ long b[10];

31373

+ long *c;

31374

+ c = b;

31375

+ asm ("": "=r" (c):"0" (c));

31376

+ *c = 1;

31377

+ asm ("": "=r" (c):"0" (c));

31378

+ sum += *c;

31379

+ }

31380

+

31381

+ if (sum != 1)

31382

+ abort();

31383

+ return 0;

31384

+}

31385

Index: gcc/testsuite/gcc.dg/torture/pr57425-3.c

31386

===================================================================

31387

--- a/src/gcc/testsuite/gcc.dg/torture/pr57425-3.c (.../tags/gcc_4_8_2_release)

31388

+++ b/src/gcc/testsuite/gcc.dg/torture/pr57425-3.c (.../branches/gcc-4_8-branch)

31389

@@ -0,0 +1,31 @@

31390

+/* { dg-do run } */

31391

+

31392

+extern void abort (void) __attribute__((noreturn));

31393

+

31394

+int

31395

+main ()

31396

+{

31397

+ int sum = 0;

31398

+ {

31399

+ long a[20];

31400

+ long *c;

31401

+ c = a;

31402

+ asm ("": "=r" (c):"0" (c));

31403

+ *c = 0;

31404

+ asm ("": "=r" (c):"0" (c));

31405

+ sum += *c;

31406

+ }

31407

+ {

31408

+ long long b[10];

31409

+ long long *c;

31410

+ c = b;

31411

+ asm ("": "=r" (c):"0" (c));

31412

+ *c = 1;

31413

+ asm ("": "=r" (c):"0" (c));

31414

+ sum += *c;

31415

+ }

31416

+

31417

+ if (sum != 1)

31418

+ abort();

31419

+ return 0;

31420

+}

31421

Index: gcc/testsuite/gcc.dg/torture/pr59047.c

31422

===================================================================

31423

--- a/src/gcc/testsuite/gcc.dg/torture/pr59047.c (.../tags/gcc_4_8_2_release)

31424

+++ b/src/gcc/testsuite/gcc.dg/torture/pr59047.c (.../branches/gcc-4_8-branch)

31425

@@ -0,0 +1,39 @@

31426

+/* { dg-do run } */

31427

+

31428

+extern void abort (void);

31429

+

31430

+struct

31431

+{

31432

+ int f0;

31433

+ int f1:1;

31434

+ int f2:2;

31435

+} a = {0, 0, 1};

31436

+

31437

+int b, c, *d, e, f;

31438

+

31439

+int

31440

+fn1 ()

31441

+{

31442

+ for (; b < 1; ++b)

31443

+ {

31444

+ for (e = 0; e < 1; e = 1)

31445

+ {

31446

+ int **g = &d;

31447

+ *g = &c;

31448

+ }

31449

+ *d = 0;

31450

+ f = a.f1;

31451

+ if (f)

31452

+ return 0;

31453

+ }

31454

+ return 0;

31455

+}

31456

+

31457

+int

31458

+main ()

31459

+{

31460

+ fn1 ();

31461

+ if (b != 1)

31462

+ abort ();

31463

+ return 0;

31464

+}

31465

Index: gcc/testsuite/gcc.dg/torture/pr58956.c

31466

===================================================================

31467

--- a/src/gcc/testsuite/gcc.dg/torture/pr58956.c (.../tags/gcc_4_8_2_release)

31468

+++ b/src/gcc/testsuite/gcc.dg/torture/pr58956.c (.../branches/gcc-4_8-branch)

31469

@@ -0,0 +1,30 @@

31470

+/* { dg-do run } */

31471

+

31472

+extern void abort (void);

31473

+

31474

+struct S

31475

+{

31476

+ int f0;

31477

+} a = {1}, b, g, *c = &b, **f = &c;

31478

+

31479

+int *d, **e = &d, h;

31480

+

31481

+struct S

31482

+foo ()

31483

+{

31484

+ *e = &h;

31485

+ if (!d)

31486

+ __builtin_unreachable ();

31487

+ *f = &g;

31488

+ return a;

31489

+}

31490

+

31491

+int

31492

+main ()

31493

+{

31494

+ struct S *i = c;

31495

+ *i = foo ();

31496

+ if (b.f0 != 1)

31497

+ abort ();

31498

+ return 0;

31499

+}

31500

Index: gcc/testsuite/gcc.dg/torture/pr60183.c

31501

===================================================================

31502

--- a/src/gcc/testsuite/gcc.dg/torture/pr60183.c (.../tags/gcc_4_8_2_release)

31503

+++ b/src/gcc/testsuite/gcc.dg/torture/pr60183.c (.../branches/gcc-4_8-branch)

31504

@@ -0,0 +1,38 @@

31505

+/* { dg-do run } */

31506

+

31507

+/* Large so an out-of-bound read will crash. */

31508

+unsigned char c[0x30001] = { 1 };

31509

+int j = 2;

31510

+

31511

+static void

31512

+foo (unsigned long *x, unsigned char *y)

31513

+{

31514

+ int i;

31515

+ unsigned long w = x[0];

31516

+ for (i = 0; i < j; i++)

31517

+ {

31518

+ w += *y;

31519

+ y += 0x10000;

31520

+ w += *y;

31521

+ y += 0x10000;

31522

+ }

31523

+ x[1] = w;

31524

+}

31525

+

31526

+__attribute__ ((noinline, noclone)) void

31527

+bar (unsigned long *x)

31528

+{

31529

+ foo (x, c);

31530

+}

31531

+

31532

+int

31533

+main ()

31534

+{

31535

+ unsigned long a[2] = { 0, -1UL };

31536

+ asm volatile (""::"r" (c):"memory");

31537

+ c[0] = 0;

31538

+ bar (a);

31539

+ if (a[1] != 0)

31540

+ __builtin_abort ();

31541

+ return 0;

31542

+}

31543

Index: gcc/testsuite/gcc.dg/torture/pr57517.c

31544

===================================================================

31545

--- a/src/gcc/testsuite/gcc.dg/torture/pr57517.c (.../tags/gcc_4_8_2_release)

31546

+++ b/src/gcc/testsuite/gcc.dg/torture/pr57517.c (.../branches/gcc-4_8-branch)

31547

@@ -0,0 +1,16 @@

31548

+/* { dg-do compile } */

31549

+

31550

+int x[1024], y[1024], z[1024], w[1024];

31551

+void foo (void)

31552

+{

31553

+ int i;

31554

+ for (i = 1; i < 1024; ++i)

31555

+ {

31556

+ int a = x[i];

31557

+ int b = y[i];

31558

+ int c = x[i-1];

31559

+ int d = y[i-1];

31560

+ if (w[i])

31561

+ z[i] = (a + b) + (c + d);

31562

+ }

31563

+}

31564

Index: gcc/testsuite/gcc.dg/torture/pr59891.c

31565

===================================================================

31566

--- a/src/gcc/testsuite/gcc.dg/torture/pr59891.c (.../tags/gcc_4_8_2_release)

31567

+++ b/src/gcc/testsuite/gcc.dg/torture/pr59891.c (.../branches/gcc-4_8-branch)

31568

@@ -0,0 +1,9 @@

31569

+/* PR c/59891 */

31570

+

31571

+unsigned int a;

31572

+

31573

+int

31574

+main ()

31575

+{

31576

+ return (0 ? a : 0) ? : 0 % 0; /* { dg-warning "division by zero" } */

31577

+}

31578

Index: gcc/testsuite/gcc.dg/torture/pr59164.c

31579

===================================================================

31580

--- a/src/gcc/testsuite/gcc.dg/torture/pr59164.c (.../tags/gcc_4_8_2_release)

31581

+++ b/src/gcc/testsuite/gcc.dg/torture/pr59164.c (.../branches/gcc-4_8-branch)

31582

@@ -0,0 +1,21 @@

31583

+/* { dg-do compile } */

31584

+

31585

+int a, d, e;

31586

+long b[10];

31587

+int c[10][8];

31588

+

31589

+int fn1(p1)

31590

+{

31591

+ return 1 >> p1;

31592

+}

31593

+

31594

+void fn2(void)

31595

+{

31596

+ int f;

31597

+ for (a=1; a <= 4; a++)

31598

+ {

31599

+ f = fn1(0 < c[a][0]);

31600

+ if (f || d)

31601

+ e = b[a] = 1;

31602

+ }

31603

+}

31604

Index: gcc/testsuite/gcc.dg/torture/pr58779.c

31605

===================================================================

31606

--- a/src/gcc/testsuite/gcc.dg/torture/pr58779.c (.../tags/gcc_4_8_2_release)

31607

+++ b/src/gcc/testsuite/gcc.dg/torture/pr58779.c (.../branches/gcc-4_8-branch)

31608

@@ -0,0 +1,12 @@

31609

+/* { dg-do run } */

31610

+

31611

+int a, c;

31612

+

31613

+int main ()

31614

+{

31615

+ int e = -1;

31616

+ short d = (c <= 0) ^ e;

31617

+ if ((unsigned int) a - (a || d) <= (unsigned int) a)

31618

+ __builtin_abort ();

31619

+ return 0;

31620

+}

31621

Index: gcc/testsuite/gcc.dg/torture/pr59139.c

31622

===================================================================

31623

--- a/src/gcc/testsuite/gcc.dg/torture/pr59139.c (.../tags/gcc_4_8_2_release)

31624

+++ b/src/gcc/testsuite/gcc.dg/torture/pr59139.c (.../branches/gcc-4_8-branch)

31625

@@ -0,0 +1,20 @@

31626

+/* { dg-do compile } */

31627

+

31628

+int a, b, c, d, e;

31629

+int fn1(p1, p2) { return p2 == 0 ? p1 : 1 % p2; }

31630

+

31631

+void fn2()

31632

+{

31633

+ c = 0;

31634

+ for (;; c = (unsigned short)c)

31635

+ {

31636

+ b = 2;

31637

+ for (; b; b = a)

31638

+ {

31639

+ e = fn1(2, c && 1);

31640

+ d = c == 0 ? e : c;

31641

+ if (d)

31642

+ return;

31643

+ }

31644

+ }

31645

+}

31646

Index: gcc/testsuite/gcc.dg/torture/pr58079.c

31647

===================================================================

31648

--- a/src/gcc/testsuite/gcc.dg/torture/pr58079.c (.../tags/gcc_4_8_2_release)

31649

+++ b/src/gcc/testsuite/gcc.dg/torture/pr58079.c (.../branches/gcc-4_8-branch)

31650

@@ -0,0 +1,107 @@

31651

+/* { dg-options "-mlong-calls" { target mips*-*-* } } */

31652

+

31653

+typedef unsigned char u8;

31654

+typedef unsigned short u16;

31655

+typedef unsigned int __kernel_size_t;

31656

+typedef __kernel_size_t size_t;

31657

+struct list_head {

31658

+ struct list_head *next;

31659

+};

31660

+

31661

+struct dmx_ts_feed {

31662

+ int is_filtering;

31663

+};

31664

+struct dmx_section_feed {

31665

+ u16 secbufp;

31666

+ u16 seclen;

31667

+ u16 tsfeedp;

31668

+};

31669

+

31670

+typedef int (*dmx_ts_cb) (

31671

+ const u8 * buffer1,

31672

+ size_t buffer1_length,

31673

+ const u8 * buffer2,

31674

+ size_t buffer2_length

31675

+);

31676

+

31677

+struct dvb_demux_feed {

31678

+ union {

31679

+ struct dmx_ts_feed ts;

31680

+ struct dmx_section_feed sec;

31681

+ } feed;

31682

+ union {

31683

+ dmx_ts_cb ts;

31684

+ } cb;

31685

+ int type;

31686

+ u16 pid;

31687

+ int ts_type;

31688

+ struct list_head list_head;

31689

+};

31690

+

31691

+struct dvb_demux {

31692

+ int (*stop_feed)(struct dvb_demux_feed *feed);

31693

+ struct list_head feed_list;

31694

+};

31695

+

31696

+

31697

+static

31698

+inline

31699

+__attribute__((always_inline))

31700

+u8

31701

+payload(const u8 *tsp)

31702

+{

31703

+ if (tsp[3] & 0x20) {

31704

+ return 184 - 1 - tsp[4];

31705

+ }

31706

+ return 184;

31707

+}

31708

+

31709

+static

31710

+inline

31711

+__attribute__((always_inline))

31712

+int

31713

+dvb_dmx_swfilter_payload(struct dvb_demux_feed *feed, const u8 *buf)

31714

+{

31715

+ int count = payload(buf);

31716

+ int p;

31717

+ if (count == 0)

31718

+ return -1;

31719

+ return feed->cb.ts(&buf[p], count, ((void *)0), 0);

31720

+}

31721

+

31722

+static

31723

+inline

31724

+__attribute__((always_inline))

31725

+void

31726

+dvb_dmx_swfilter_packet_type(struct dvb_demux_feed *feed, const u8 *buf)

31727

+{

31728

+ switch (feed->type) {

31729

+ case 0:

31730

+ if (feed->ts_type & 1) {

31731

+ dvb_dmx_swfilter_payload(feed, buf);

31732

+ }

31733

+ if (dvb_dmx_swfilter_section_packet(feed, buf) < 0)

31734

+ feed->feed.sec.seclen = feed->feed.sec.secbufp = 0;

31735

+ }

31736

+}

31737

+

31738

+static

31739

+void

31740

+dvb_dmx_swfilter_packet(struct dvb_demux *demux, const u8 *buf)

31741

+{

31742

+ struct dvb_demux_feed *feed;

31743

+ int dvr_done = 0;

31744

+

31745

+ for (feed = ({ const typeof( ((typeof(*feed) *)0)->list_head ) *__mptr = ((&demux->feed_list)->next); (typeof(*feed) *)( (char *)__mptr - __builtin_offsetof(typeof(*feed),list_head) );}); __builtin_prefetch(feed->list_head.next), &feed->list_head != (&demux->feed_list); feed = ({ const typeof( ((typeof(*feed) *)0)->list_head ) *__mptr = (feed->list_head.next); (typeof(*feed) *)( (char *)__mptr - __builtin_offsetof(typeof(*feed),list_head) );})) {

31746

+ if (((((feed)->type == 0) && ((feed)->feed.ts.is_filtering) && (((feed)->ts_type & (1 | 8)) == 1))) && (dvr_done++))

31747

+ dvb_dmx_swfilter_packet_type(feed, buf);

31748

+ else if (feed->pid == 0x2000)

31749

+ feed->cb.ts(buf, 188, ((void *)0), 0);

31750

+ }

31751

+}

31752

+void dvb_dmx_swfilter_packets(struct dvb_demux *demux, const u8 *buf, size_t count)

31753

+{

31754

+ while (count--) {

31755

+ dvb_dmx_swfilter_packet(demux, buf);

31756

+ }

31757

+}

31758

Index: gcc/testsuite/gcc.dg/torture/pr58830.c

31759

===================================================================

31760

--- a/src/gcc/testsuite/gcc.dg/torture/pr58830.c (.../tags/gcc_4_8_2_release)

31761

+++ b/src/gcc/testsuite/gcc.dg/torture/pr58830.c (.../branches/gcc-4_8-branch)

31762

@@ -0,0 +1,42 @@

31763

+/* { dg-do run } */

31764

+/* { dg-additional-options "-ftree-pre -ftree-partial-pre" } */

31765

+

31766

+extern void abort (void);

31767

+

31768

+int b, c, d, f, g, h, i, j[6], *l = &b, *m, n, *o, r;

31769

+char k;

31770

+

31771

+static int

31772

+foo ()

31773

+{

31774

+ char *p = &k;

31775

+

31776

+ for (; d; d++)

31777

+ if (i)

31778

+ h = 0;

31779

+ else

31780

+ h = c || (r = 0);

31781

+

31782

+ for (f = 0; f < 2; f++)

31783

+ {

31784

+ unsigned int q;

31785

+ *l = 0;

31786

+ if (n)

31787

+ *m = g;

31788

+ if (g)

31789

+ o = 0;

31790

+ for (q = -8; q >= 5; q++)

31791

+ (*p)--;

31792

+ }

31793

+

31794

+ return 0;

31795

+}

31796

+

31797

+int

31798

+main ()

31799

+{

31800

+ foo ();

31801

+ if (j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[0]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]] ^ (k & 15)] != 0)

31802

+ abort ();

31803

+ return 0;

31804

+}

31805

Index: gcc/testsuite/gcc.dg/torture/pr60930.c

31806

===================================================================

31807

--- a/src/gcc/testsuite/gcc.dg/torture/pr60930.c (.../tags/gcc_4_8_2_release)

31808

+++ b/src/gcc/testsuite/gcc.dg/torture/pr60930.c (.../branches/gcc-4_8-branch)

31809

@@ -0,0 +1,22 @@

31810

+/* { dg-do run } */

31811

+

31812

+int x = 1;

31813

+

31814

+__attribute__((noinline, noclone)) void

31815

+foo (unsigned long long t)

31816

+{

31817

+ asm volatile ("" : : "r" (&t));

31818

+ if (t == 1)

31819

+ __builtin_abort ();

31820

+}

31821

+

31822

+int

31823

+main ()

31824

+{

31825

+#if __SIZEOF_LONG_LONG__ >= 8

31826

+ unsigned long long t = 0xffffffffffffffffULL * (0xffffffffUL * x);

31827

+ if (t != 0xffffffff00000001ULL)

31828

+ foo (t);;

31829

+#endif

31830

+ return 0;

31831

+}

31832

Index: gcc/testsuite/gcc.dg/torture/pr59715.c

31833

===================================================================

31834

--- a/src/gcc/testsuite/gcc.dg/torture/pr59715.c (.../tags/gcc_4_8_2_release)

31835

+++ b/src/gcc/testsuite/gcc.dg/torture/pr59715.c (.../branches/gcc-4_8-branch)

31836

@@ -0,0 +1,21 @@

31837

+/* { dg-do run } */

31838

+

31839

+extern void abort (void);

31840

+

31841

+int a = 2, b;

31842

+

31843

+int

31844

+main ()

31845

+{

31846

+ int c;

31847

+ if (!b)

31848

+ {

31849

+ b = a;

31850

+ c = a == 0 ? 1 : 1 % a;

31851

+ if (c)

31852

+ b = 0;

31853

+ }

31854

+ if (b != 0)

31855

+ abort ();

31856

+ return 0;

31857

+}

31858

Index: gcc/testsuite/gcc.dg/torture/pr60115.c

31859

===================================================================

31860

--- a/src/gcc/testsuite/gcc.dg/torture/pr60115.c (.../tags/gcc_4_8_2_release)

31861

+++ b/src/gcc/testsuite/gcc.dg/torture/pr60115.c (.../branches/gcc-4_8-branch)

31862

@@ -0,0 +1,14 @@

31863

+/* { dg-do run } */

31864

+

31865

+int a, b[2];

31866

+

31867

+int

31868

+main ()

31869

+{

31870

+lbl:

31871

+ for (; a; a--)

31872

+ if (b[10000])

31873

+ goto lbl;

31874

+

31875

+ return 0;

31876

+}

31877

Index: gcc/testsuite/gcc.dg/torture/pr59903.c

31878

===================================================================

31879

--- a/src/gcc/testsuite/gcc.dg/torture/pr59903.c (.../tags/gcc_4_8_2_release)

31880

+++ b/src/gcc/testsuite/gcc.dg/torture/pr59903.c (.../branches/gcc-4_8-branch)

31881

@@ -0,0 +1,56 @@

31882

+/* { dg-do compile } */

31883

+

31884

+int a, b, c, d, e, f, g, h, i[3], l, m, n, o, p, q, r;

31885

+

31886

+struct S0

31887

+{

31888

+ int f0;

31889

+ int f1;

31890

+ int f2;

31891

+ int f3;

31892

+} j;

31893

+

31894

+static int

31895

+fn1 (int p1)

31896

+{

31897

+ return p1 || ((p1 > 0) > (e << 1));

31898

+}

31899

+

31900

+static struct S0

31901

+fn2 (struct S0 p1)

31902

+{

31903

+ char s;

31904

+ struct S0 t = {0,0,0,0};

31905

+ int u = 2;

31906

+ for (;;)

31907

+ {

31908

+ if (i[0])

31909

+ break;

31910

+ for (m = 0; m < 4; m++)

31911

+ for (p1.f0 = 0; p1.f0 < 3; p1.f0++)

31912

+ {

31913

+ j = t;

31914

+ t.f3 = i[p1.f0];

31915

+ o = b || 1 >> b ? 0 : a < 0;

31916

+ q = 1 % d;

31917

+ if ((g < fn1 ((1 ^ (q & 1)) | n)) ^ u)

31918

+ j.f3 |= p % 2;

31919

+ s = j.f3 > 0 ? j.f3 : j.f3 << 1;

31920

+ r = l = s && p1.f1 * c;

31921

+ h = p1.f1;

31922

+ }

31923

+ }

31924

+ return p1;

31925

+}

31926

+

31927

+int

31928

+main ()

31929

+{

31930

+ for (;f;)

31931

+ {

31932

+ struct S0 v = {0,0,0,0};

31933

+ fn2 (v);

31934

+ j.f3 = 0;

31935

+ }

31936

+ return 0;

31937

+}

31938

Index: gcc/testsuite/gcc.dg/torture/pr58143-1.c

31939

===================================================================

31940

--- a/src/gcc/testsuite/gcc.dg/torture/pr58143-1.c (.../tags/gcc_4_8_2_release)

31941

+++ b/src/gcc/testsuite/gcc.dg/torture/pr58143-1.c (.../branches/gcc-4_8-branch)

31942

@@ -0,0 +1,51 @@

31943

+/* { dg-do run } */

31944

+/* { dg-additional-options "-fstrict-overflow" } */

31945

+

31946

+extern void abort (void);

31947

+

31948

+int a, b, c, d, e, f, g, h = 1, i;

31949

+

31950

+int foo (int p)

31951

+{

31952

+ return p < 0 && a < - __INT_MAX__ - 1 - p ? 0 : 1;

31953

+}

31954

+

31955

+int *bar ()

31956

+{

31957

+ int j;

31958

+ i = h ? 0 : 1 % h;

31959

+ for (j = 0; j < 1; j++)

31960

+ for (d = 0; d; d++)

31961

+ for (e = 1; e;)

31962

+ return 0;

31963

+ return 0;

31964

+}

31965

+

31966

+int baz ()

31967

+{

31968

+ for (; b >= 0; b--)

31969

+ for (c = 1; c >= 0; c--)

31970

+ {

31971

+ int *k = &c;

31972

+ for (;;)

31973

+ {

31974

+ for (f = 0; f < 1; f++)

31975

+ {

31976

+ g = foo (*k);

31977

+ bar ();

31978

+ }

31979

+ if (*k)

31980

+ break;

31981

+ return 0;

31982

+ }

31983

+ }

31984

+ return 0;

31985

+}

31986

+

31987

+int main ()

31988

+{

31989

+ baz ();

31990

+ if (b != 0)

31991

+ abort ();

31992

+ return 0;

31993

+}

31994

Index: gcc/testsuite/gcc.dg/torture/pr58143-2.c

31995

===================================================================

31996

--- a/src/gcc/testsuite/gcc.dg/torture/pr58143-2.c (.../tags/gcc_4_8_2_release)

31997

+++ b/src/gcc/testsuite/gcc.dg/torture/pr58143-2.c (.../branches/gcc-4_8-branch)

31998

@@ -0,0 +1,34 @@

31999

+/* { dg-do run } */

32000

+/* { dg-additional-options "-fstrict-overflow" } */

32001

+

32002

+int a, b, d, e, f, *g, h, i;

32003

+volatile int c;

32004

+

32005

+char foo (unsigned char p)

32006

+{

32007

+ return p + 1;

32008

+}

32009

+

32010

+int bar ()

32011

+{

32012

+ for (h = 0; h < 3; h = foo (h))

32013

+ {

32014

+ c;

32015

+ for (f = 0; f < 1; f++)

32016

+ {

32017

+ i = a && 0 < -__INT_MAX__ - h ? 0 : 1;

32018

+ if (e)

32019

+ for (; d;)

32020

+ b = 0;

32021

+ else

32022

+ g = 0;

32023

+ }

32024

+ }

32025

+ return 0;

32026

+}

32027

+

32028

+int main ()

32029

+{

32030

+ bar ();

32031

+ return 0;

32032

+}

32033

Index: gcc/testsuite/gcc.dg/torture/pr58941.c

32034

===================================================================

32035

--- a/src/gcc/testsuite/gcc.dg/torture/pr58941.c (.../tags/gcc_4_8_2_release)

32036

+++ b/src/gcc/testsuite/gcc.dg/torture/pr58941.c (.../branches/gcc-4_8-branch)

32037

@@ -0,0 +1,33 @@

32038

+/* { dg-do run } */

32039

+

32040

+extern void abort (void);

32041

+

32042

+typedef struct {

32043

+ int msgLength;

32044

+ unsigned char data[1000];

32045

+} SMsg;

32046

+

32047

+typedef struct {

32048

+ int dummy;

32049

+ int d[0];

32050

+} SData;

32051

+

32052

+int condition = 3;

32053

+

32054

+int main()

32055

+{

32056

+ SMsg msg;

32057

+ SData *pData = (SData*)(msg.data);

32058

+ unsigned int i = 0;

32059

+ for (i = 0; i < 1; i++)

32060

+ {

32061

+ pData->d[i] = 0;

32062

+ if(condition & 1)

32063

+ pData->d[i] |= 0x55;

32064

+ if(condition & 2)

32065

+ pData->d[i] |= 0xaa;

32066

+ }

32067

+ if (pData->d[0] != 0xff)

32068

+ abort ();

32069

+ return 0;

32070

+}

32071

Index: gcc/testsuite/gcc.dg/torture/pr57488.c

32072

===================================================================

32073

--- a/src/gcc/testsuite/gcc.dg/torture/pr57488.c (.../tags/gcc_4_8_2_release)

32074

+++ b/src/gcc/testsuite/gcc.dg/torture/pr57488.c (.../branches/gcc-4_8-branch)

32075

@@ -0,0 +1,58 @@

32076

+/* { dg-do run } */

32077

+

32078

+extern void abort (void);

32079

+

32080

+int i, j, *pj = &j, **ppj = &pj;

32081

+int x, *px = &x;

32082

+

32083

+short s, *ps = &s, k;

32084

+

32085

+unsigned short u, *pu = &u, **ppu = &pu;

32086

+

32087

+char c, *pc = &c;

32088

+

32089

+unsigned char v = 48;

32090

+

32091

+static int

32092

+bar (int p)

32093

+{

32094

+ p = k;

32095

+ *px = **ppu = i;

32096

+ *ppj = &p;

32097

+ if (**ppj)

32098

+ *pj = p;

32099

+ return p;

32100

+}

32101

+

32102

+void __attribute__((noinline))

32103

+foo ()

32104

+{

32105

+ for (; i <= 3; i++)

32106

+ for (; j; j--);

32107

+

32108

+ u ^= bar (*pj);

32109

+

32110

+ for (k = 1; k >= 0; k--)

32111

+ {

32112

+ int l;

32113

+ bar (0);

32114

+ for (l = 1; l < 5; l++)

32115

+ {

32116

+ int m;

32117

+ for (m = 6; m; m--)

32118

+ {

32119

+ v--;

32120

+ *ps = *pc;

32121

+ }

32122

+ }

32123

+ }

32124

+}

32125

+

32126

+int

32127

+main ()

32128

+{

32129

+ foo ();

32130

+ if (v != 0)

32131

+ abort ();

32132

+ return 0;

32133

+}

32134

Index: gcc/testsuite/gcc.dg/torture/pr57569.c

32135

===================================================================

32136

--- a/src/gcc/testsuite/gcc.dg/torture/pr57569.c (.../tags/gcc_4_8_2_release)

32137

+++ b/src/gcc/testsuite/gcc.dg/torture/pr57569.c (.../branches/gcc-4_8-branch)

32138

@@ -0,0 +1,37 @@

32139

+/* { dg-do run } */

32140

+

32141

+extern void abort (void) __attribute__((noreturn));

32142

+

32143

+struct S { int f0; } a;

32144

+

32145

+int b, e, *d = &b, f;

32146

+

32147

+void

32148

+fn1 ()

32149

+{

32150

+ int **g[9][6];

32151

+ int ***h = &g[6][3];

32152

+ for (; e < 9; e++) {

32153

+ f = 0;

32154

+ for (; f < 6; f++)

32155

+ g[e][f] = &d;

32156

+ }

32157

+ ***h = 0;

32158

+}

32159

+

32160

+void

32161

+fn2 ()

32162

+{

32163

+ fn1 ();

32164

+ struct S c[4][10] = {};

32165

+ a = c[3][9];

32166

+}

32167

+

32168

+int

32169

+main ()

32170

+{

32171

+ fn2 ();

32172

+ if (a.f0 != 0)

32173

+ abort ();

32174

+ return 0;

32175

+}

32176

Index: gcc/testsuite/gcc.dg/torture/pr58143-3.c

32177

===================================================================

32178

--- a/src/gcc/testsuite/gcc.dg/torture/pr58143-3.c (.../tags/gcc_4_8_2_release)

32179

+++ b/src/gcc/testsuite/gcc.dg/torture/pr58143-3.c (.../branches/gcc-4_8-branch)

32180

@@ -0,0 +1,18 @@

32181

+/* { dg-do run } */

32182

+/* { dg-additional-options "-fstrict-overflow" } */

32183

+

32184

+int a, b, c, d, e;

32185

+

32186

+int

32187

+main ()

32188

+{

32189

+ for (b = 4; b > -30; b--)

32190

+ for (; c;)

32191

+ for (;;)

32192

+ {

32193

+ e = a > __INT_MAX__ - b;

32194

+ if (d)

32195

+ break;

32196

+ }

32197

+ return 0;

32198

+}

32199

Index: gcc/testsuite/gcc.dg/torture/pr53922.c

32200

===================================================================

32201

--- a/src/gcc/testsuite/gcc.dg/torture/pr53922.c (.../tags/gcc_4_8_2_release)

32202

+++ b/src/gcc/testsuite/gcc.dg/torture/pr53922.c (.../branches/gcc-4_8-branch)

32203

@@ -3,6 +3,7 @@

32204

/* { dg-skip-if "No undefined" { *-*-mingw* } { "*" } { "" } } */

32205

/* { dg-skip-if "No undefined weak" { hppa*-*-hpux* && { ! lp64 } } { "*" } { "" } } */

32206

/* { dg-options "-Wl,-undefined,dynamic_lookup" { target *-*-darwin* } } */

32207

+/* { dg-additional-options "-Wl,-flat_namespace" { target *-*-darwin[89]* } } */

32208

32209

int x(int a)

32210

{

32211

Index: gcc/testsuite/gcc.dg/torture/pr59288.c

32212

===================================================================

32213

--- a/src/gcc/testsuite/gcc.dg/torture/pr59288.c (.../tags/gcc_4_8_2_release)

32214

+++ b/src/gcc/testsuite/gcc.dg/torture/pr59288.c (.../branches/gcc-4_8-branch)

32215

@@ -0,0 +1,9 @@

32216

+/* { dg-do compile } */

32217

+

32218

+void

32219

+baz (int *d)

32220

+{

32221

+ long int i, j, k;

32222

+ for (i = 0, j = 0, k = 0; i < 512; i = (int) i + 1, j = (int) j + 1, k = (int) k + 3)

32223

+ d[i] = j ^ (i * 3) ^ (2 * k + 2);

32224

+}

32225

Index: gcc/testsuite/gcc.dg/torture/pr57425-1.c

32226

===================================================================

32227

--- a/src/gcc/testsuite/gcc.dg/torture/pr57425-1.c (.../tags/gcc_4_8_2_release)

32228

+++ b/src/gcc/testsuite/gcc.dg/torture/pr57425-1.c (.../branches/gcc-4_8-branch)

32229

@@ -0,0 +1,37 @@

32230

+/* { dg-do run } */

32231

+

32232

+extern void abort (void) __attribute__((noreturn));

32233

+

32234

+union setconflict

32235

+{

32236

+ int a[20];

32237

+ long b[10];

32238

+};

32239

+

32240

+int

32241

+main ()

32242

+{

32243

+ int sum = 0;

32244

+ {

32245

+ union setconflict a;

32246

+ int *c;

32247

+ c = a.a;

32248

+ asm ("": "=r" (c):"0" (c));

32249

+ *c = 0;

32250

+ asm ("": "=r" (c):"0" (c));

32251

+ sum += *c;

32252

+ }

32253

+ {

32254

+ union setconflict a;

32255

+ long *c;

32256

+ c = a.b;

32257

+ asm ("": "=r" (c):"0" (c));

32258

+ *c = 1;

32259

+ asm ("": "=r" (c):"0" (c));

32260

+ sum += *c;

32261

+ }

32262

+

32263

+ if (sum != 1)

32264

+ abort();

32265

+ return 0;

32266

+}

32267

Index: gcc/testsuite/gcc.dg/torture/pr59330.c

32268

===================================================================

32269

--- a/src/gcc/testsuite/gcc.dg/torture/pr59330.c (.../tags/gcc_4_8_2_release)

32270

+++ b/src/gcc/testsuite/gcc.dg/torture/pr59330.c (.../branches/gcc-4_8-branch)

32271

@@ -0,0 +1,17 @@

32272

+/* { dg-do run } */

32273

+

32274

+void free(void *ptr)

32275

+{

32276

+}

32277

+

32278

+void *foo(void)

32279

+{

32280

+ return 0;

32281

+}

32282

+

32283

+int main(void)

32284

+{

32285

+ void *p = foo();

32286

+ free(p);

32287

+ return 0;

32288

+}

32289

Index: gcc/testsuite/gcc.dg/tree-ssa/20040517-1.c

32290

===================================================================

32291

--- a/src/gcc/testsuite/gcc.dg/tree-ssa/20040517-1.c (.../tags/gcc_4_8_2_release)

32292

+++ b/src/gcc/testsuite/gcc.dg/tree-ssa/20040517-1.c (.../branches/gcc-4_8-branch)

32293

@@ -16,6 +16,7 @@

32294

/* We used to treat malloc functions like pure and const functions, but

32295

malloc functions may clobber global memory. Only the function result

32296

does not alias any other pointer.

32297

- Hence, we must have a VDEF for a before and after the call to foo(). */

32298

-/* { dg-final { scan-tree-dump-times "VDEF" 2 "alias"} } */

32299

+ Hence, we must have a VDEF for a before and after the call to foo().

32300

+ And one after the call to abort(). */

32301

+/* { dg-final { scan-tree-dump-times "VDEF" 3 "alias"} } */

32302

/* { dg-final { cleanup-tree-dump "alias" } } */

32303

Index: gcc/testsuite/gcc.dg/tree-ssa/predcom-6.c

32304

===================================================================

32305

--- a/src/gcc/testsuite/gcc.dg/tree-ssa/predcom-6.c (.../tags/gcc_4_8_2_release)

32306

+++ b/src/gcc/testsuite/gcc.dg/tree-ssa/predcom-6.c (.../branches/gcc-4_8-branch)

32307

@@ -0,0 +1,14 @@

32308

+/* { dg-do run } */

32309

+/* { dg-options "-O3" } */

32310

+

32311

+int a, c, e[5][2];

32312

+unsigned int d;

32313

+

32314

+int

32315

+main ()

32316

+{

32317

+ for (d = 0; d < 2; d++)

32318

+ if (a ? 0 : e[c + 3][d] & e[c + 4][d])

32319

+ break;

32320

+ return 0;

32321

+}

32322

Index: gcc/testsuite/gcc.dg/tree-ssa/predcom-7.c

32323

===================================================================

32324

--- a/src/gcc/testsuite/gcc.dg/tree-ssa/predcom-7.c (.../tags/gcc_4_8_2_release)

32325

+++ b/src/gcc/testsuite/gcc.dg/tree-ssa/predcom-7.c (.../branches/gcc-4_8-branch)

32326

@@ -0,0 +1,18 @@

32327

+/* { dg-do run } */

32328

+/* { dg-options "-O3 -fdump-tree-pcom-details" } */

32329

+

32330

+int b, f, d[5][2];

32331

+unsigned int c;

32332

+

32333

+int

32334

+main ()

32335

+{

32336

+ for (c = 0; c < 2; c++)

32337

+ if (d[b + 3][c] & d[b + 4][c])

32338

+ if (f)

32339

+ break;

32340

+ return 0;

32341

+}

32342

+

32343

+/* { dg-final { scan-tree-dump "Executing predictive commoning" "pcom" } } */

32344

+/* { dg-final { cleanup-tree-dump "pcom" } } */

32345

Index: gcc/testsuite/gcc.dg/tls/pr58595.c

32346

===================================================================

32347

--- a/src/gcc/testsuite/gcc.dg/tls/pr58595.c (.../tags/gcc_4_8_2_release)

32348

+++ b/src/gcc/testsuite/gcc.dg/tls/pr58595.c (.../branches/gcc-4_8-branch)

32349

@@ -0,0 +1,28 @@

32350

+/* PR target/58595 */

32351

+/* { dg-do run } */

32352

+/* { dg-options "-O2" } */

32353

+/* { dg-additional-options "-fpic" { target fpic } } */

32354

+/* { dg-require-effective-target tls } */

32355

+/* { dg-require-effective-target sync_int_long } */

32356

+

32357

+struct S { unsigned long a, b; };

32358

+__thread struct S s;

32359

+void bar (unsigned long *);

32360

+

32361

+__attribute__((noinline)) void

32362

+foo (void)

32363

+{

32364

+ int i;

32365

+ for (i = 0; i < 10; i++)

32366

+ __sync_fetch_and_add (&s.b, 1L);

32367

+}

32368

+

32369

+int

32370

+main ()

32371

+{

32372

+ s.b = 12;

32373

+ foo ();

32374

+ if (s.b != 22)

32375

+ __builtin_abort ();

32376

+ return 0;

32377

+}

32378

Index: gcc/testsuite/gcc.dg/strlenopt-4.c

32379

===================================================================

32380

--- a/src/gcc/testsuite/gcc.dg/strlenopt-4.c (.../tags/gcc_4_8_2_release)

32381

+++ b/src/gcc/testsuite/gcc.dg/strlenopt-4.c (.../branches/gcc-4_8-branch)

32382

@@ -66,16 +66,10 @@

32383

return 0;

32384

}

32385

32386

-/* For targets providing a movstr pattern strcat is already decomposed

32387

- into strlen + strcpy by fold_builtin_strcat. */

32388

-

32389

-/* { dg-final { scan-tree-dump-times "strlen \\(" 3 "strlen" { target { ! s390*-*-* } } } } */

32390

-/* { dg-final { scan-tree-dump-times "strlen \\(" 6 "strlen" { target s390*-*-* } } } */

32391

+/* { dg-final { scan-tree-dump-times "strlen \\(" 3 "strlen" } } */

32392

/* { dg-final { scan-tree-dump-times "memcpy \\(" 4 "strlen" } } */

32393

-/* { dg-final { scan-tree-dump-times "strcpy \\(" 3 "strlen" { target { ! s390*-*-* } } } } */

32394

-/* { dg-final { scan-tree-dump-times "strcpy \\(" 6 "strlen" { target s390*-*-* } } } */

32395

-/* { dg-final { scan-tree-dump-times "strcat \\(" 3 "strlen" { target { ! s390*-*-* } } } } */

32396

-/* { dg-final { scan-tree-dump-times "strcat \\(" 0 "strlen" { target s390*-*-* } } } */

32397

+/* { dg-final { scan-tree-dump-times "strcpy \\(" 3 "strlen" } } */

32398

+/* { dg-final { scan-tree-dump-times "strcat \\(" 3 "strlen" } } */

32399

/* { dg-final { scan-tree-dump-times "strchr \\(" 0 "strlen" } } */

32400

/* { dg-final { scan-tree-dump-times "stpcpy \\(" 0 "strlen" } } */

32401

/* { dg-final { cleanup-tree-dump "strlen" } } */

32402

Index: gcc/testsuite/gcc.dg/pr56824.c

32403

===================================================================

32404

--- a/src/gcc/testsuite/gcc.dg/pr56824.c (.../tags/gcc_4_8_2_release)

32405

+++ b/src/gcc/testsuite/gcc.dg/pr56824.c (.../branches/gcc-4_8-branch)

32406

@@ -0,0 +1,18 @@

32407

+/* PR preprocessor/56824 */

32408

+/* { dg-do compile } */

32409

+/* { dg-options "-Waggregate-return" } */

32410

+

32411

+struct S { int i; };

32412

+struct S foo (void);

32413

+

32414

+#pragma GCC diagnostic push

32415

+#pragma GCC diagnostic ignored "-Waggregate-return"

32416

+

32417

+int

32418

+main ()

32419

+{

32420

+ foo ();

32421

+ return 0;

32422

+}

32423

+

32424

+#pragma GCC diagnostic pop

32425

Index: gcc/testsuite/gcc.dg/ipa/pr55260.c

32426

===================================================================

32427

--- a/src/gcc/testsuite/gcc.dg/ipa/pr55260.c (.../tags/gcc_4_8_2_release)

32428

+++ b/src/gcc/testsuite/gcc.dg/ipa/pr55260.c (.../branches/gcc-4_8-branch)

32429

@@ -0,0 +1,38 @@

32430

+/* { dg-do compile } */

32431

+/* { dg-options "-O2 -fno-inline -fipa-cp-clone" } */

32432

+

32433

+typedef struct {

32434

+ int *ptr;

32435

+ int len;

32436

+} string;

32437

+typedef struct {

32438

+ string nantstr;

32439

+ int *nant;

32440

+} malv;

32441

+typedef struct {

32442

+ int *nor;

32443

+} list_heads;

32444

+int b;

32445

+list_heads *fn1(string, int *, unsigned);

32446

+void fn2(malv *p1, list_heads *p2, unsigned p3) {

32447

+ string a = p1->nantstr;

32448

+ fn1(a, p1->nant, p3);

32449

+}

32450

+

32451

+void fn3(unsigned p1) { fn2(0, 0, p1); }

32452

+

32453

+list_heads *fn1(string p1, int *p2, unsigned p3) {

32454

+ while (1) {

32455

+ if (p3)

32456

+ fn3(1);

32457

+ if (b)

32458

+ return 0;

32459

+ fn3(1);

32460

+ }

32461

+}

32462

+

32463

+void fn5() {

32464

+ list_heads c;

32465

+ c.nor = 0;

32466

+ fn2(0, &c, 1);

32467

+}

32468

Index: gcc/testsuite/gcc.dg/ipa/pr59610.c

32469

===================================================================

32470

--- a/src/gcc/testsuite/gcc.dg/ipa/pr59610.c (.../tags/gcc_4_8_2_release)

32471

+++ b/src/gcc/testsuite/gcc.dg/ipa/pr59610.c (.../branches/gcc-4_8-branch)

32472

@@ -0,0 +1,11 @@

32473

+/* { dg-do compile } */

32474

+/* { dg-options "-O2" } */

32475

+

32476

+struct A { int a; };

32477

+extern void *y;

32478

+

32479

+__attribute__((optimize (0))) void

32480

+foo (void *p, struct A x)

32481

+{

32482

+ foo (y, x);

32483

+}

32484

Index: gcc/testsuite/gcc.dg/pr60485-1.c

32485

===================================================================

32486

--- a/src/gcc/testsuite/gcc.dg/pr60485-1.c (.../tags/gcc_4_8_2_release)

32487

+++ b/src/gcc/testsuite/gcc.dg/pr60485-1.c (.../branches/gcc-4_8-branch)

32488

@@ -0,0 +1,29 @@

32489

+/* { dg-do run } */

32490

+/* { dg-options "-O2" } */

32491

+

32492

+extern void abort (void);

32493

+struct S {

32494

+ int *i[4];

32495

+ int *p1;

32496

+ int *p2;

32497

+ int *p3;

32498

+ int *p4;

32499

+};

32500

+int **b;

32501

+int main()

32502

+{

32503

+ int i = 1;

32504

+ struct S s;

32505

+ s.p3 = &i;

32506

+ int **p;

32507

+ if (b)

32508

+ p = b;

32509

+ else

32510

+ p = &s.i[2];

32511

+ p += 4;

32512

+ if (!b)

32513

+ **p = 0;

32514

+ if (i != 0)

32515

+ abort ();

32516

+ return i;

32517

+}

32518

Index: gcc/testsuite/gcc.dg/strlenopt-1f.c

32519

===================================================================

32520

--- a/src/gcc/testsuite/gcc.dg/strlenopt-1f.c (.../tags/gcc_4_8_2_release)

32521

+++ b/src/gcc/testsuite/gcc.dg/strlenopt-1f.c (.../branches/gcc-4_8-branch)

32522

@@ -6,13 +6,13 @@

32523

#include "strlenopt-1.c"

32524

32525

/* { dg-final { scan-tree-dump-times "strlen \\(" 2 "strlen" } } */

32526

-/* { dg-final { scan-tree-dump-times "__memcpy_chk \\(" 3 "strlen" } } */

32527

-/* { dg-final { scan-tree-dump-times "__strcpy_chk \\(" 1 "strlen" } } */

32528

+/* { dg-final { scan-tree-dump-times "__memcpy_chk \\(" 0 "strlen" } } */

32529

+/* { dg-final { scan-tree-dump-times "__strcpy_chk \\(" 0 "strlen" } } */

32530

/* { dg-final { scan-tree-dump-times "__strcat_chk \\(" 0 "strlen" } } */

32531

/* { dg-final { scan-tree-dump-times "strchr \\(" 0 "strlen" } } */

32532

/* { dg-final { scan-tree-dump-times "__stpcpy_chk \\(" 0 "strlen" } } */

32533

-/* { dg-final { scan-tree-dump-times "memcpy \\(" 0 "strlen" } } */

32534

-/* { dg-final { scan-tree-dump-times "strcpy \\(" 0 "strlen" } } */

32535

+/* { dg-final { scan-tree-dump-times "memcpy \\(" 3 "strlen" } } */

32536

+/* { dg-final { scan-tree-dump-times "strcpy \\(" 1 "strlen" } } */

32537

/* { dg-final { scan-tree-dump-times "strcat \\(" 0 "strlen" } } */

32538

/* { dg-final { scan-tree-dump-times "stpcpy \\(" 0 "strlen" } } */

32539

/* { dg-final { cleanup-tree-dump "strlen" } } */

32540

Index: gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-slp-34.c

32541

===================================================================

32542

--- a/src/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-slp-34.c (.../tags/gcc_4_8_2_release)

32543

+++ b/src/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-slp-34.c (.../branches/gcc-4_8-branch)

32544

@@ -1,4 +1,5 @@

32545

/* { dg-require-effective-target vect_int } */

32546

+/* { dg-skip-if "cost too high" { powerpc*le-*-* } { "*" } { "" } } */

32547

32548

#include <stdarg.h>

32549

#include "../../tree-vect.h"

32550

Index: gcc/testsuite/gcc.dg/vect/pr60382.c

32551

===================================================================

32552

--- a/src/gcc/testsuite/gcc.dg/vect/pr60382.c (.../tags/gcc_4_8_2_release)

32553

+++ b/src/gcc/testsuite/gcc.dg/vect/pr60382.c (.../branches/gcc-4_8-branch)

32554

@@ -0,0 +1,32 @@

32555

+#include "tree-vect.h"

32556

+

32557

+int a, b, c, e, f;

32558

+

32559

+void

32560

+foo ()

32561

+{

32562

+ for (b = 0; b < 3; b++)

32563

+ if (e)

32564

+ {

32565

+ for (c = 0; c < 4; c++)

32566

+ {

32567

+ if (b)

32568

+ continue;

32569

+ f = 1;

32570

+ for (a = 0; a < 2; a++)

32571

+ f |= 1;

32572

+ }

32573

+ for (;;)

32574

+ ;

32575

+ }

32576

+}

32577

+

32578

+int

32579

+main ()

32580

+{

32581

+ check_vect ();

32582

+ foo ();

32583

+ return 0;

32584

+}

32585

+

32586

+/* { dg-final { cleanup-tree-dump "vect" } } */

32587

Index: gcc/testsuite/gcc.dg/vect/pr60276.c

32588

===================================================================

32589

--- a/src/gcc/testsuite/gcc.dg/vect/pr60276.c (.../tags/gcc_4_8_2_release)

32590

+++ b/src/gcc/testsuite/gcc.dg/vect/pr60276.c (.../branches/gcc-4_8-branch)

32591

@@ -0,0 +1,52 @@

32592

+/* { dg-do run } */

32593

+

32594

+extern void abort (void);

32595

+

32596

+static void

32597

+foo (int *out, const int *lp, unsigned samples)

32598

+{

32599

+ int x, target;

32600

+ for (x = 0, target = 0; x < (int)samples; x += 2, target++)

32601

+ {

32602

+ out[x] = lp[target];

32603

+ out[x - 1] = out[x - 2] + out[x];

32604

+ }

32605

+}

32606

+

32607

+static void

32608

+foo_novec (int *out, const int *lp, unsigned samples)

32609

+{

32610

+ int x, target;

32611

+ for (x = 0, target = 0; x < (int)samples; x += 2, target++)

32612

+ {

32613

+ out[x] = lp[target];

32614

+ out[x - 1] = out[x - 2] + out[x];

32615

+ __asm__ volatile ("" : : : "memory");

32616

+ }

32617

+}

32618

+

32619

+int main(void)

32620

+{

32621

+ const int lp[25] = {

32622

+ 0, 2, 4, 6, 8,

32623

+ 10, 12, 14, 16,

32624

+ 18, 20, 22, 24,

32625

+ 26, 28, 30, 32,

32626

+ 34, 36, 38, 40,

32627

+ 42, 44, 46, 48,

32628

+ };

32629

+ int out[49] = {0};

32630

+ int out2[49] = {0};

32631

+ int s;

32632

+

32633

+ foo (out + 2, lp + 1, 48);

32634

+ foo_novec (out2 + 2, lp + 1, 48);

32635

+

32636

+ for (s = 0; s < 49; s++)

32637

+ if (out[s] != out2[s])

32638

+ abort ();

32639

+

32640

+ return 0;

32641

+}

32642

+

32643

+/* { dg-final { cleanup-tree-dump "vect" } } */

32644

Index: gcc/testsuite/gcc.dg/pr53060.c

32645

===================================================================

32646

--- a/src/gcc/testsuite/gcc.dg/pr53060.c (.../tags/gcc_4_8_2_release)

32647

+++ b/src/gcc/testsuite/gcc.dg/pr53060.c (.../branches/gcc-4_8-branch)

32648

@@ -25,3 +25,4 @@

32649

32650

/* Ignore a warning that is irrelevant to the purpose of this test. */

32651

/* { dg-prune-output ".*GCC vector returned by reference.*" } */

32652

+/* { dg-prune-output "changes the ABI" } */

32653

Index: gcc/testsuite/ChangeLog

32654

===================================================================

32655

--- a/src/gcc/testsuite/ChangeLog (.../tags/gcc_4_8_2_release)

32656

+++ b/src/gcc/testsuite/ChangeLog (.../branches/gcc-4_8-branch)

32657

@@ -1,3 +1,1796 @@

32658

+2014-05-05 Richard Biener <rguenther@suse.de>

32659

+

32660

+ Backport from mainline

32661

+ 2014-04-23 Richard Biener <rguenther@suse.de>

32662

+

32663

+ PR middle-end/60895

32664

+ * g++.dg/torture/pr60895.C: New testcase.

32665

+

32666

+ 2014-04-07 Richard Biener <rguenther@suse.de>

32667

+

32668

+ PR middle-end/60750

32669

+ * g++.dg/torture/pr60750.C: New testcase.

32670

+ * gcc.dg/tree-ssa/20040517-1.c: Adjust.

32671

+

32672

+ 2014-04-14 Richard Biener <rguenther@suse.de>

32673

+

32674

+ PR tree-optimization/59817

32675

+ PR tree-optimization/60453

32676

+ * gfortran.dg/graphite/pr59817.f: New testcase.

32677

+ * gcc.dg/graphite/pr59817-1.c: Likewise.

32678

+ * gcc.dg/graphite/pr59817-2.c: Likewise.

32679

+

32680

+ 2014-04-17 Richard Biener <rguenther@suse.de>

32681

+

32682

+ PR tree-optimization/60836

32683

+ * g++.dg/vect/pr60836.cc: New testcase.

32684

+

32685

+2014-05-05 Jakub Jelinek <jakub@redhat.com>

32686

+

32687

+ Backported from mainline

32688

+ 2014-04-25 Jakub Jelinek <jakub@redhat.com>

32689

+

32690

+ PR tree-optimization/60960

32691

+ * gcc.c-torture/execute/pr60960.c: New test.

32692

+

32693

+2014-05-04 Peter Bergner <bergner@vnet.ibm.com>

32694

+

32695

+ * gcc.target/powerpc/pack02.c (dg-options): Add -mhard-float.

32696

+ (dg-require-effective-target): Change target to powerpc_fprs.

32697

+ * gcc.target/powerpc/pack03.c (dg-options): Add -mhard-dfp.

32698

+ (dg-require-effective-target): Change target to dfprt.

32699

+

32700

+2014-05-02 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

32701

+

32702

+ PR tree-optimization/60930

32703

+ * gcc.dg/torture/pr60930.c: New test.

32704

+

32705

+2014-04-30 Michael Meissner <meissner@linux.vnet.ibm.com>

32706

+

32707

+ Back port from mainline

32708

+ 2014-04-24 Michael Meissner <meissner@linux.vnet.ibm.com>

32709

+

32710

+ * gcc.target/powerpc/pack01.c: New test to test the new pack and

32711

+ unpack builtin functionss for 128-bit types.

32712

+ * gcc.target/powerpc/pack02.c: Likewise.

32713

+ * gcc.target/powerpc/pack03.c: Likewise.

32714

+ * gcc.target/powerpc/extend-divide-1.c: New test to test extended

32715

+ divide builtin functionss.

32716

+ * gcc.target/powerpc/extend-divide-2.c: Likewise.

32717

+ * gcc.target/powerpc/bcd-1.c: New test for the new BCD builtin

32718

+ functions.

32719

+ * gcc.target/powerpc/bcd-2.c: Likewise.

32720

+ * gcc.target/powerpc/bcd-3.c: Likewise.

32721

+ * gcc.target/powerpc/dfp-builtin-1.c: New test for the new DFP

32722

+ builtin functionss.

32723

+ * gcc.target/powerpc/dfp-builtin-2.c: Likewise.

32724

+

32725

+2014-04-29 Pat Haugen <pthaugen@us.ibm.com>

32726

+

32727

+ Backport from mainline

32728

+ 2014-04-17 Pat Haugen <pthaugen@us.ibm.com>

32729

+

32730

+ * gcc.target/powerpc/ti_math1.c: New.

32731

+ * gcc.target/powerpc/ti_math2.c: New.

32732

+

32733

+2014-04-25 Eric Botcazou <ebotcazou@adacore.com>

32734

+

32735

+ * gcc.c-torture/execute/20140425-1.c: New test.

32736

+

32737

+2014-04-23 Michael Meissner <meissner@linux.vnet.ibm.com>

32738

+

32739

+ Back port from main line:

32740

+ 2014-03-27 Michael Meissner <meissner@linux.vnet.ibm.com>

32741

+

32742

+ * gcc.target/powerpc/p8vector-vbpermq.c: New test to test the

32743

+ vbpermq builtin.

32744

+

32745

+2014-04-23 Uros Bizjak <ubizjak@gmail.com>

32746

+

32747

+ Backport from mainline

32748

+ 2014-04-21 Uros Bizjak <ubizjak@gmail.com>

32749

+

32750

+ PR target/60909

32751

+ * gcc.target/i386/pr60909-1.c: New test.

32752

+ * gcc.target/i386/pr60909-2.c: Ditto.

32753

+

32754

+2014-04-23 Richard Biener <rguenther@suse.de>

32755

+

32756

+ Backport from mainline

32757

+ 2014-04-02 Richard Biener <rguenther@suse.de>

32758

+

32759

+ PR middle-end/60729

32760

+ * g++.dg/vect/pr60729.cc: New testcase.

32761

+

32762

+ 2014-04-03 Richard Biener <rguenther@suse.de>

32763

+

32764

+ PR tree-optimization/60740

32765

+ * gcc.dg/graphite/pr60740.c: New testcase.

32766

+

32767

+2014-04-23 Richard Biener <rguenther@suse.de>

32768

+

32769

+ PR middle-end/60635

32770

+ * gfortran.dg/lto/pr60635_0.f90: New testcase.

32771

+ * gfortran.dg/lto/pr60635_1.c: Likewise.

32772

+

32773

+2014-04-21 Michael Meissner <meissner@linux.vnet.ibm.com>

32774

+

32775

+ Back port from the trunk, subversion id 209546.

32776

+

32777

+ 2014-04-21 Michael Meissner <meissner@linux.vnet.ibm.com>

32778

+

32779

+ PR target/60735

32780

+ * gcc.target/powerpc/pr60735.c: New test. Insure _Decimal64 does

32781

+ not cause errors if -mspe.

32782

+

32783

+2014-04-17 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

32784

+

32785

+ * gcc.dg/vmx/merge-vsx.c: Add V4SI and V4SF tests.

32786

+ * gcc.dg/vmx/merge-vsx-be-order.c: Likewise.

32787

+

32788

+2014-04-12 Jerry DeLisle <jvdelisle@gcc.gnu>

32789

+

32790

+ Backport from mainline

32791

+ PR libfortran/60810

32792

+ gfortran.dg/arrayio_13.f90: New test.

32793

+

32794

+2014-04-11 Hans-Peter Nilsson <hp@axis.com>

32795

+

32796

+ * gfortran.dg/fmt_en.f90: Gate test on effective_target

32797

+ fd_truncate.

32798

+

32799

+2014-04-11 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>

32800

+

32801

+ * gcc.target/s390/htm-nofloat-1.c: Rename to ...

32802

+ * gcc.target/s390/htm-nofloat-compile-1.c: ... this one.

32803

+ * gcc.target/s390/htm-nofloat-2.c: Add check for htm target and

32804

+ rename to ...

32805

+ * gcc.target/s390/htm-nofloat-1.c: ... this one.

32806

+ * gcc.target/s390/s390.exp: Make sure the assembler supports htm

32807

+ instructions as well.

32808

+

32809

+2014-04-11 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>

32810

+

32811

+ * gcc.target/s390/htm-builtins-compile-1.c: Replace long long with

32812

+ long.

32813

+

32814

+2014-04-11 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>

32815

+

32816

+ * gcc.target/s390/htm-builtins-compile-1.c: Remove htm check.

32817

+ * gcc.target/s390/htm-builtins-compile-2.c: Remove htm check.

32818

+

32819

+2014-04-10 Vladimir Makarov <vmakarov@redhat.com>

32820

+

32821

+ PR rtl-optimization/60769

32822

+ * g++.dg/pr60769.C: New.

32823

+

32824

+2014-04-10 Jakub Jelinek <jakub@redhat.com>

32825

+

32826

+ Backport from mainline

32827

+ 2014-03-12 Jakub Jelinek <jakub@redhat.com>

32828

+ Marc Glisse <marc.glisse@inria.fr>

32829

+

32830

+ PR tree-optimization/60502

32831

+ * gcc.c-torture/compile/pr60502.c: New test.

32832

+

32833

+ 2014-03-28 Jakub Jelinek <jakub@redhat.com>

32834

+

32835

+ PR target/60693

32836

+ * gcc.target/i386/pr60693.c: New test.

32837

+

32838

+ PR c++/60689

32839

+ * c-c++-common/pr60689.c: New test.

32840

+

32841

+ 2014-03-22 Jakub Jelinek <jakub@redhat.com>

32842

+

32843

+ PR debug/60603

32844

+ * gcc.dg/debug/dwarf2/dwarf2-macro2.c: New test.

32845

+

32846

+ 2014-03-17 Jakub Jelinek <jakub@redhat.com>

32847

+

32848

+ PR target/60516

32849

+ * gcc.target/i386/pr60516.c: New test.

32850

+

32851

+ 2014-03-13 Jakub Jelinek <jakub@redhat.com>

32852

+

32853

+ PR middle-end/36282

32854

+ * c-c++-common/pr36282-1.c: New test.

32855

+ * c-c++-common/pr36282-2.c: New test.

32856

+ * c-c++-common/pr36282-3.c: New test.

32857

+ * c-c++-common/pr36282-4.c: New test.

32858

+

32859

+ 2014-03-06 Jakub Jelinek <jakub@redhat.com>

32860

+

32861

+ PR target/58595

32862

+ * gcc.dg/tls/pr58595.c: New test.

32863

+

32864

+2014-04-07 Martin Jambor <mjambor@suse.cz>

32865

+

32866

+ PR ipa/60640

32867

+ * g++.dg/ipa/pr60640-1.C: New test.

32868

+ * g++.dg/ipa/pr60640-2.C: Likewise.

32869

+ * g++.dg/ipa/pr60640-3.C: Likewise.

32870

+

32871

+2014-04-06 Dominique d'Humieres <dominiq@lps.ens.fr>

32872

+ Iain Sandoe <iain@codesourcery.com>

32873

+

32874

+ PR target/54083

32875

+ * gcc.dg/attr-weakref-1.c: Allow the test on darwin with

32876

+ the additional options -Wl,-undefined,dynamic_lookup and

32877

+ -Wl,-flat_namespace

32878

+ * gcc.dg/torture/pr53922.c: Additional option

32879

+ -Wl,-flat_namespace for darwin[89].

32880

+

32881

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

32882

+

32883

+ Backport from mainline

32884

+ 2013-04-05 David Edelsohn <dje.gcc@gmail.com>

32885

+

32886

+ * gcc.target/powerpc/sd-vsx.c: Skip on AIX.

32887

+ * gcc.target/powerpc/sd-pwr6.c: Same.

32888

+

32889

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

32890

+

32891

+ Back port from trunk

32892

+ 2014-03-12 Michael Meissner <meissner@linux.vnet.ibm.com>

32893

+

32894

+ * gcc.target/powerpc/p8vector-int128-1.c: New test to test ISA

32895

+ 2.07 128-bit arithmetic.

32896

+ * gcc.target/powerpc/p8vector-int128-2.c: Likewise.

32897

+

32898

+ * gcc.target/powerpc/timode_off.c: Restrict cpu type to power5,

32899

+ due to when TImode is allowed in VSX registers, the allowable

32900

+ address modes for TImode is just a single indirect address in

32901

+ order for the value to be loaded and store in either GPR or VSX

32902

+ registers. This affects the generated code, and it would cause

32903

+ this test to fail, when such an option is used.

32904

+

32905

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

32906

+

32907

+ Backport from mainline r207699.

32908

+ 2014-02-11 Michael Meissner <meissner@linux.vnet.ibm.com>

32909

+

32910

+ PR target/60137

32911

+ * gcc.target/powerpc/pr60137.c: New file.

32912

+

32913

+ Backport from mainline r207808.

32914

+ 2014-02-15 Michael Meissner <meissner@linux.vnet.ibm.com>

32915

+

32916

+ PR target/60203

32917

+ * gcc.target/powerpc/pr60203.c: New testsuite.

32918

+

32919

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

32920

+

32921

+ Little Endian Vector API Support

32922

+ Backport from mainline r206590

32923

+ 2014-01-13 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

32924

+

32925

+ * gcc.dg/vmx/insert.c: New.

32926

+ * gcc.dg/vmx/insert-be-order.c: New.

32927

+ * gcc.dg/vmx/extract.c: New.

32928

+ * gcc.dg/vmx/extract-be-order.c: New.

32929

+

32930

+ Backport from mainline r206641

32931

+ 2014-01-15 Bill Schmidt <wschmidt@vnet.linux.ibm.com>

32932

+

32933

+ * gcc.dg/vmx/mult-even-odd.c: New.

32934

+ * gcc.dg/vmx/mult-even-odd-be-order.c: New.

32935

+

32936

+ Backport from mainline r206926

32937

+ 2014-01-22 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

32938

+

32939

+ * gcc.dg/vmx/insert-vsx-be-order.c: New.

32940

+ * gcc.dg/vmx/extract-vsx.c: New.

32941

+ * gcc.dg/vmx/extract-vsx-be-order.c: New.

32942

+ * gcc.dg/vmx/insert-vsx.c: New.

32943

+

32944

+ Backport from mainline r207262

32945

+ 2014-01-29 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

32946

+

32947

+ * gcc.dg/vmx/merge-be-order.c: New.

32948

+ * gcc.dg/vmx/merge.c: New.

32949

+ * gcc.dg/vmx/merge-vsx-be-order.c: New.

32950

+ * gcc.dg/vmx/merge-vsx.c: New.

32951

+

32952

+ Backport from mainline r207318

32953

+ 2014-01-30 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

32954

+

32955

+ * gcc.dg/vmx/splat.c: New.

32956

+ * gcc.dg/vmx/splat-vsx.c: New.

32957

+ * gcc.dg/vmx/splat-be-order.c: New.

32958

+ * gcc.dg/vmx/splat-vsx-be-order.c: New.

32959

+ * gcc.dg/vmx/eg-5.c: Remove special casing for little endian.

32960

+ * gcc.dg/vmx/sn7153.c: Add special casing for little endian.

32961

+

32962

+ Backport from mainline r207414

32963

+ 2014-02-02 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

32964

+

32965

+ * gcc.dg/vmx/vsums.c: New.

32966

+ * gcc.dg/vmx/vsums-be-order.c: New.

32967

+

32968

+ Backport from mainline r207415

32969

+ 2014-02-02 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

32970

+

32971

+ * gcc.dg/vmx/3b-15.c: Remove special handling for little endian.

32972

+ * gcc.dg/vmx/perm.c: New.

32973

+ * gcc.dg/vmx/perm-be-order.c: New.

32974

+

32975

+ Backport from mainline r207520

32976

+ 2014-02-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

32977

+

32978

+ * gcc.dg/vmx/pack.c: New.

32979

+ * gcc.dg/vmx/pack-be-order.c: New.

32980

+ * gcc.dg/vmx/unpack.c: New.

32981

+ * gcc.dg/vmx/unpack-be-order.c: New.

32982

+

32983

+ Backport from mainline r207521

32984

+ 2014-02-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

32985

+

32986

+ * gcc.dg/vmx/sum2s.c: New.

32987

+ * gcc.dg/vmx/sum2s-be-order.c: New.

32988

+

32989

+ Backport from mainline 208019

32990

+ 2014-02-21 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

32991

+

32992

+ * gcc.dg/vmx/ld.c: New test.

32993

+ * gcc.dg/vmx/ld-be-order.c: New test.

32994

+ * gcc.dg/vmx/ld-vsx.c: New test.

32995

+ * gcc.dg/vmx/ld-vsx-be-order.c: New test.

32996

+ * gcc.dg/vmx/ldl.c: New test.

32997

+ * gcc.dg/vmx/ldl-be-order.c: New test.

32998

+ * gcc.dg/vmx/ldl-vsx.c: New test.

32999

+ * gcc.dg/vmx/ldl-vsx-be-order.c: New test.

33000

+ * gcc.dg/vmx/st.c: New test.

33001

+ * gcc.dg/vmx/st-be-order.c: New test.

33002

+ * gcc.dg/vmx/st-vsx.c: New test.

33003

+ * gcc.dg/vmx/st-vsx-be-order.c: New test.

33004

+ * gcc.dg/vmx/stl.c: New test.

33005

+ * gcc.dg/vmx/stl-be-order.c: New test.

33006

+ * gcc.dg/vmx/stl-vsx.c: New test.

33007

+ * gcc.dg/vmx/stl-vsx-be-order.c: New test.

33008

+

33009

+ Backport from mainline 208021

33010

+ 2014-02-21 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33011

+

33012

+ * gcc.dg/vmx/vsums.c: Check entire result vector.

33013

+ * gcc.dg/vmx/vsums-be-order.c: Likewise.

33014

+

33015

+ Backport from mainline 208049

33016

+ 2014-02-23 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33017

+

33018

+ * gcc.dg/vmx/lde.c: New test.

33019

+ * gcc.dg/vmx/lde-be-order.c: New test.

33020

+ * gcc.dg/vmx/ste.c: New test.

33021

+ * gcc.dg/vmx/ste-be-order.c: New test.

33022

+

33023

+ Backport from mainline 208120

33024

+ 2014-02-25 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33025

+

33026

+ * gcc.dg/vmx/ld-vsx.c: Don't use vec_all_eq.

33027

+ * gcc.dg/vmx/ld-vsx-be-order.c: Likewise.

33028

+ * gcc.dg/vmx/ldl-vsx.c: Likewise.

33029

+ * gcc.dg/vmx/ldl-vsx-be-order.c: Likewise.

33030

+ * gcc.dg/vmx/merge-vsx.c: Likewise.

33031

+ * gcc.dg/vmx/merge-vsx-be-order.c: Likewise.

33032

+

33033

+ Backport from mainline 208321

33034

+ 2014-03-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33035

+

33036

+ * gcc.dg/vmx/extract-vsx.c: Replace "vector long" with "vector

33037

+ long long" throughout.

33038

+ * gcc.dg/vmx/extract-vsx-be-order.c: Likewise.

33039

+ * gcc.dg/vmx/insert-vsx.c: Likewise.

33040

+ * gcc.dg/vmx/insert-vsx-be-order.c: Likewise.

33041

+ * gcc.dg/vmx/ld-vsx.c: Likewise.

33042

+ * gcc.dg/vmx/ld-vsx-be-order.c: Likewise.

33043

+ * gcc.dg/vmx/ldl-vsx.c: Likewise.

33044

+ * gcc.dg/vmx/ldl-vsx-be-order.c: Likewise.

33045

+ * gcc.dg/vmx/merge-vsx.c: Likewise.

33046

+ * gcc.dg/vmx/merge-vsx-be-order.c: Likewise.

33047

+ * gcc.dg/vmx/st-vsx.c: Likewise.

33048

+ * gcc.dg/vmx/st-vsx-be-order.c: Likewise.

33049

+ * gcc.dg/vmx/stl-vsx.c: Likewise.

33050

+ * gcc.dg/vmx/stl-vsx-be-order.c: Likewise.

33051

+

33052

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33053

+

33054

+ Back port from mainline

33055

+ 2014-01-23 Michael Meissner <meissner@linux.vnet.ibm.com>

33056

+

33057

+ PR target/59909

33058

+ * gcc.target/powerpc/quad-atomic.c: New file to test power8 quad

33059

+ word atomic functions at runtime.

33060

+

33061

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33062

+

33063

+ Backport from mainline

33064

+ 2013-10-23 Pat Haugen <pthaugen@us.ibm.com>

33065

+

33066

+ * gcc.target/powerpc/direct-move.h: Fix header for executable tests.

33067

+

33068

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33069

+

33070

+ Backport from mainline

33071

+ 2013-04-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33072

+

33073

+ PR target/56843

33074

+ * gcc.target/powerpc/recip-1.c: Modify expected output.

33075

+ * gcc.target/powerpc/recip-3.c: Likewise.

33076

+ * gcc.target/powerpc/recip-4.c: Likewise.

33077

+ * gcc.target/powerpc/recip-5.c: Add expected output for iterations.

33078

+

33079

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33080

+

33081

+ Backport from mainline

33082

+ 2013-08-19 Peter Bergner <bergner@vnet.ibm.com>

33083

+

33084

+ * gcc.target/powerpc/dfp-dd-2.c: New test.

33085

+ * gcc.target/powerpc/dfp-td-2.c: Likewise.

33086

+ * gcc.target/powerpc/dfp-td-3.c: Likewise.

33087

+

33088

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33089

+

33090

+ ELFv2 ABI Support

33091

+ Backport from mainline r204808:

33092

+

33093

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

33094

+

33095

+ * gcc.target/powerpc/ppc64-abi-1.c (stack_frame_t): Remove

33096

+ compiler and linker field if _CALL_ELF == 2.

33097

+ * gcc.target/powerpc/ppc64-abi-2.c (stack_frame_t): Likewise.

33098

+ * gcc.target/powerpc/ppc64-abi-dfp-1.c (stack_frame_t): Likewise.

33099

+ * gcc.dg/stack-usage-1.c (SIZE): Update value for _CALL_ELF == 2.

33100

+

33101

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

33102

+

33103

+ * gcc.target/powerpc/ppc64-abi-dfp-1.c (FUNC_START): New macro.

33104

+ (WRAPPER): Use it.

33105

+ * gcc.target/powerpc/no-r11-1.c: Skip on powerpc_elfv2.

33106

+ * gcc.target/powerpc/no-r11-2.c: Skip on powerpc_elfv2.

33107

+ * gcc.target/powerpc/no-r11-3.c: Skip on powerpc_elfv2.

33108

+

33109

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

33110

+

33111

+ * lib/target-supports.exp (check_effective_target_powerpc_elfv2):

33112

+ New function.

33113

+ * gcc.target/powerpc/pr57949-1.c: Disable for powerpc_elfv2.

33114

+ * gcc.target/powerpc/pr57949-2.c: Likewise.

33115

+

33116

+ Backport from mainline r204799:

33117

+

33118

+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

33119

+

33120

+ * g++.dg/eh/ppc64-sighandle-cr.C: New test.

33121

+

33122

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33123

+

33124

+ Backport from mainline r201750.

33125

+ Note: Default setting of -mcompat-align-parm inverted!

33126

+

33127

+ 2013-08-14 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33128

+

33129

+ PR target/57949

33130

+ * gcc.target/powerpc/pr57949-1.c: New.

33131

+ * gcc.target/powerpc/pr57949-2.c: New.

33132

+

33133

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33134

+

33135

+ Little Endian Vector Support

33136

+ Backport from mainline r205638

33137

+ 2013-12-03 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33138

+

33139

+ * gcc.dg/vect/costmodel/ppc/costmodel-slp-34.c: Skip for little

33140

+ endian.

33141

+

33142

+ Backport from mainline r205146

33143

+ 2013-11-20 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33144

+

33145

+ * gcc.target/powerpc/pr48258-1.c: Skip for little endian.

33146

+

33147

+ Backport from mainline r204862

33148

+ 2013-11-15 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33149

+

33150

+ * gcc.dg/vmx/3b-15.c: Revise for little endian.

33151

+

33152

+ Backport from mainline r204321

33153

+ 2013-11-02 Bill Schmidt <wschmidt@vnet.linux.ibm.com>

33154

+

33155

+ * gcc.dg/vmx/vec-set.c: New.

33156

+

33157

+ Backport from mainline r204138

33158

+ 2013-10-28 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33159

+

33160

+ * gcc.dg/vmx/gcc-bug-i.c: Add little endian variant.

33161

+ * gcc.dg/vmx/eg-5.c: Likewise.

33162

+

33163

+ Backport from mainline r203930

33164

+ 2013-10-22 Bill Schmidt <wschmidt@vnet.ibm.com>

33165

+

33166

+ * gcc.target/powerpc/altivec-perm-1.c: Move the two vector pack

33167

+ tests into...

33168

+ * gcc.target/powerpc/altivec-perm-3.c: ...this new test, which is

33169

+ restricted to big-endian targets.

33170

+

33171

+ Backport from mainline r203246

33172

+ 2013-10-07 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33173

+

33174

+ * gcc.target/powerpc/pr43154.c: Skip for ppc64 little endian.

33175

+ * gcc.target/powerpc/fusion.c: Likewise.

33176

+

33177

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33178

+

33179

+ Backport from mainline

33180

+ 2013-11-27 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33181

+

33182

+ * gfortran.dg/nan_7.f90: Disable for little endian PowerPC.

33183

+

33184

+ Backport from mainline r205106:

33185

+

33186

+ 2013-11-20 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

33187

+

33188

+ * gcc.target/powerpc/darwin-longlong.c (msw): Make endian-safe.

33189

+

33190

+ Backport from mainline r205046:

33191

+

33192

+ 2013-11-19 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

33193

+

33194

+ * gcc.target/powerpc/ppc64-abi-2.c (MAKE_SLOT): New macro to

33195

+ construct parameter slot value in endian-independent way.

33196

+ (fcevv, fciievv, fcvevv): Use it.

33197

+

33198

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33199

+

33200

+ Power8 HTM Support

33201

+ Backport from mainline

33202

+ * lib/target-supports.exp (check_effective_target_powerpc_htm_ok): New

33203

+ function to test if HTM is available.

33204

+ * gcc.target/powerpc/htm-xl-intrin-1.c: New test.

33205

+ * gcc.target/powerpc/htm-builtin-1.c: New test.

33206

+

33207

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33208

+

33209

+ Power8 Base Support

33210

+ Backport from mainline

33211

+ 2013-11-22 Michael Meissner <meissner@linux.vnet.ibm.com>

33212

+

33213

+ PR target/59054

33214

+ * gcc.target/powerpc/direct-move.h (VSX_REG_ATTR): Allow test to

33215

+ specify an appropriate register class for VSX operations.

33216

+ (load_vsx): Use it.

33217

+ (load_gpr_to_vsx): Likewise.

33218

+ (load_vsx_to_gpr): Likewise.

33219

+ * gcc.target/powerpc/direct-move-vint1.c: Use an appropriate

33220

+ register class for VSX registers that the type can handle. Remove

33221

+ checks for explicit number of instructions generated, just check

33222

+ if the instruction is generated.

33223

+ * gcc.target/powerpc/direct-move-vint2.c: Likewise.

33224

+ * gcc.target/powerpc/direct-move-float1.c: Likewise.

33225

+ * gcc.target/powerpc/direct-move-float2.c: Likewise.

33226

+ * gcc.target/powerpc/direct-move-double1.c: Likewise.

33227

+ * gcc.target/powerpc/direct-move-double2.c: Likewise.

33228

+ * gcc.target/powerpc/direct-move-long1.c: Likewise.

33229

+ * gcc.target/powerpc/direct-move-long2.c: Likewise.

33230

+

33231

+ * gcc.target/powerpc/bool3-av.c: Limit to 64-bit mode for now.

33232

+ * gcc.target/powerpc/bool3-p7.c: Likewise.

33233

+ * gcc.target/powerpc/bool3-p8.c: Likewise.

33234

+

33235

+ * gcc.target/powerpc/p8vector-ldst.c: Just check that the

33236

+ appropriate instructions are generated, don't check the count.

33237

+

33238

+ 2013-11-12 Michael Meissner <meissner@linux.vnet.ibm.com>

33239

+

33240

+ PR target/59054

33241

+ * gcc.target/powerpc/pr59054.c: New test.

33242

+

33243

+ 2013-08-22 Michael Meissner <meissner@linux.vnet.ibm.com>

33244

+

33245

+ * gcc.target/powerpc/pr57744.c: Declare abort.

33246

+

33247

+ 2013-07-18 Pat Haugen <pthaugen@us.ibm.com>

33248

+

33249

+ * gcc.target/powerpc/pr57744.c: Fix typo.

33250

+

33251

+ Back port from mainline

33252

+ 2013-10-03 Michael Meissner <meissner@linux.vnet.ibm.com>

33253

+

33254

+ * gcc.target/powerpc/p8vector-fp.c: New test for floating point

33255

+ scalar operations when using -mupper-regs-sf and -mupper-regs-df.

33256

+ * gcc.target/powerpc/ppc-target-1.c: Update tests to allow either

33257

+ VSX scalar operations or the traditional floating point form of

33258

+ the instruction.

33259

+ * gcc.target/powerpc/ppc-target-2.c: Likewise.

33260

+ * gcc.target/powerpc/recip-3.c: Likewise.

33261

+ * gcc.target/powerpc/recip-5.c: Likewise.

33262

+ * gcc.target/powerpc/pr72747.c: Likewise.

33263

+ * gcc.target/powerpc/vsx-builtin-3.c: Likewise.

33264

+

33265

+ Back port from mainline

33266

+ 2013-09-27 Michael Meissner <meissner@linux.vnet.ibm.com>

33267

+

33268

+ * gcc.target/powerpc/p8vector-ldst.c: New test for -mupper-regs-sf

33269

+ and -mupper-regs-df.

33270

+

33271

+ Back port from mainline

33272

+ 2013-10-17 Michael Meissner <meissner@linux.vnet.ibm.com>

33273

+

33274

+ PR target/58673

33275

+ * gcc.target/powerpc/pr58673-1.c: New file to test whether

33276

+ -mquad-word + -mno-vsx-timode causes errors.

33277

+ * gcc.target/powerpc/pr58673-2.c: Likewise.

33278

+

33279

+

33280

+ Backport from trunk.

33281

+ 2013-07-23 Michael Meissner <meissner@linux.vnet.ibm.com>

33282

+

33283

+ * gcc.target/powerpc/bool2.h: New file, test the code generation

33284

+ of logical operations for power5, altivec, power7, and power8 systems.

33285

+ * gcc.target/powerpc/bool2-p5.c: Likewise.

33286

+ * gcc.target/powerpc/bool2-av.c: Likewise.

33287

+ * gcc.target/powerpc/bool2-p7.c: Likewise.

33288

+ * gcc.target/powerpc/bool2-p8.c: Likewise.

33289

+ * gcc.target/powerpc/bool3.h: Likewise.

33290

+ * gcc.target/powerpc/bool3-av.c: Likewise.

33291

+ * gcc.target/powerpc/bool2-p7.c: Likewise.

33292

+ * gcc.target/powerpc/bool2-p8.c: Likewise.

33293

+

33294

+ Backport from trunk.

33295

+ 2013-07-31 Michael Meissner <meissner@linux.vnet.ibm.com>

33296

+

33297

+ * gcc.target/powerpc/fusion.c: New file, test power8 fusion support.

33298

+

33299

+ Back port from the trunk

33300

+ 2013-06-28 Michael Meissner <meissner@linux.vnet.ibm.com>

33301

+

33302

+ PR target/57744

33303

+ * gcc.target/powerpc/pr57744.c: New test to make sure lqarx and

33304

+ stqcx. get even registers.

33305

+

33306

+ Back port from the trunk

33307

+

33308

+ 2013-06-12 Michael Meissner <meissner@linux.vnet.ibm.com>

33309

+ Pat Haugen <pthaugen@us.ibm.com>

33310

+ Peter Bergner <bergner@vnet.ibm.com>

33311

+

33312

+ * gcc.target/powerpc/atomic-p7.c: New file, add tests for atomic

33313

+ load/store instructions on power7, power8.

33314

+ * gcc.target/powerpc/atomic-p8.c: Likewise.

33315

+

33316

+ Back port from the trunk

33317

+

33318

+ 2013-06-10 Michael Meissner <meissner@linux.vnet.ibm.com>

33319

+ Pat Haugen <pthaugen@us.ibm.com>

33320

+ Peter Bergner <bergner@vnet.ibm.com>

33321

+

33322

+ * gcc.target/powerpc/direct-move-vint1.c: New tests for power8

33323

+ direct move instructions.

33324

+ * gcc.target/powerpc/direct-move-vint2.c: Likewise.

33325

+ * gcc.target/powerpc/direct-move.h: Likewise.

33326

+ * gcc.target/powerpc/direct-move-float1.c: Likewise.

33327

+ * gcc.target/powerpc/direct-move-float2.c: Likewise.

33328

+ * gcc.target/powerpc/direct-move-double1.c: Likewise.

33329

+ * gcc.target/powerpc/direct-move-double2.c: Likewise.

33330

+ * gcc.target/powerpc/direct-move-long1.c: Likewise.

33331

+ * gcc.target/powerpc/direct-move-long2.c: Likewise.

33332

+

33333

+ Backport from the trunk

33334

+

33335

+ 2013-06-06 Michael Meissner <meissner@linux.vnet.ibm.com>

33336

+ Pat Haugen <pthaugen@us.ibm.com>

33337

+ Peter Bergner <bergner@vnet.ibm.com>

33338

+

33339

+ * gcc.target/powerpc/p8vector-builtin-1.c: New test to test

33340

+ power8 builtin functions.

33341

+ * gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c: Likewise.

33342

+ * gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c: Likewise.

33343

+ * gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c: Likewise.

33344

+ * gcc/testsuite/gcc.target/powerpc/p8vector-builtin-5.c: Likewise.

33345

+ * gcc/testsuite/gcc.target/powerpc/p8vector-builtin-6.c: Likewise.

33346

+ * gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c: Likewise.

33347

+ * gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-1.c: New

33348

+ tests to test power8 auto-vectorization.

33349

+ * gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-2.c: Likewise.

33350

+ * gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-3.c: Likewise.

33351

+ * gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-4.c: Likewise.

33352

+ * gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-5.c: Likewise.

33353

+

33354

+ * gcc.target/powerpc/crypto-builtin-1.c: Use effective target

33355

+ powerpc_p8vector_ok instead of powerpc_vsx_ok.

33356

+

33357

+ * gcc.target/powerpc/bool.c: New file, add eqv, nand, nor tests.

33358

+

33359

+ * lib/target-supports.exp (check_p8vector_hw_available) Add power8

33360

+ support.

33361

+ (check_effective_target_powerpc_p8vector_ok): Likewise.

33362

+ (is-effective-target): Likewise.

33363

+ (check_vect_support_and_set_flags): Likewise.

33364

+

33365

+ Backport from trunk

33366

+

33367

+ 2013-05-22 Michael Meissner <meissner@linux.vnet.ibm.com>

33368

+ Pat Haugen <pthaugen@us.ibm.com>

33369

+ Peter Bergner <bergner@vnet.ibm.com>

33370

+

33371

+ * gcc.target/powerpc/crypto-builtin-1.c: New file, test for power8

33372

+ crypto builtins.

33373

+

33374

+ Backport from mainline

33375

+ 2013-03-20 Michael Meissner <meissner@linux.vnet.ibm.com>

33376

+

33377

+ * gcc.target/powerpc/mmfpgpr.c: New test.

33378

+ * gcc.target/powerpc/sd-vsx.c: Likewise.

33379

+ * gcc.target/powerpc/sd-pwr6.c: Likewise.

33380

+ * gcc.target/powerpc/vsx-float0.c: Likewise.

33381

+

33382

+2014-04-01 Dominique d'Humieres <dominiq@lps.ens.fr>

33383

+

33384

+ PR libfortran/60128

33385

+ * gfortran.dg/fmt_en.f90: Skip unsupported rounding tests.

33386

+ XFAIL for i?86-*-solaris2.9* and hppa*-*-hpux*.

33387

+

33388

+2014-03-31 H.J. Lu <hongjiu.lu@intel.com>

33389

+

33390

+ Backport from mainline

33391

+ 2014-03-31 H.J. Lu <hongjiu.lu@intel.com>

33392

+

33393

+ PR rtl-optimization/60700

33394

+ * gcc.target/i386/pr60700.c: New test.

33395

+

33396

+2014-03-28 H.J. Lu <hongjiu.lu@intel.com>

33397

+

33398

+ PR rtl-optimization/60700

33399

+ Backport from mainline

33400

+ 2013-07-30 Zhenqiang Chen <zhenqiang.chen@linaro.org>

33401

+

33402

+ * gcc.target/arm/pr57637.c: New testcase.

33403

+

33404

+2014-04-28 Thomas Koenig <tkoenig@gcc.gnu.org>

33405

+

33406

+ PR fortran/60522

33407

+ * gfortran.dg/where_4.f90: New test case.

33408

+

33409

+2014-03-26 Martin Jambor <mjambor@suse.cz>

33410

+

33411

+ PR ipa/60419

33412

+ * g++.dg/ipa/pr60419.C: New test.

33413

+

33414

+2014-03-26 Eric Botcazou <ebotcazou@adacore.com>

33415

+

33416

+ * gcc.c-torture/execute/20140326-1.c: New test.

33417

+

33418

+2014-03-20 Tobias Burnus <burnus@net-b.de>

33419

+

33420

+ PR fortran/60543

33421

+ PR fortran/60283

33422

+ * gfortran.dg/implicit_pure_4.f90: New.

33423

+

33424

+2014-03-17 Mikael Pettersson <mikpelinux@gmail.com>

33425

+ Committed by Bill Schmidt <wschmidt@linux.vnet.ibm.com>

33426

+

33427

+ Backport from mainline:

33428

+

33429

+ 2013-06-16 Joern Rennecke <joern.rennecke@embecosm.com>

33430

+

33431

+ PR rtl-optimization/57425

33432

+ PR rtl-optimization/57569

33433

+ * gcc.dg/torture/pr57425-1.c, gcc.dg/torture/pr57425-2.c: New files.

33434

+ * gcc.dg/torture/pr57425-3.c, gcc.dg/torture/pr57569.c: Likewise.

33435

+

33436

+2014-03-17 Richard Biener <rguenther@suse.de>

33437

+

33438

+ Backport from mainline

33439

+ 2014-03-11 Richard Biener <rguenther@suse.de>

33440

+

33441

+ PR tree-optimization/60429

33442

+ PR tree-optimization/60485

33443

+ * gcc.dg/pr60485-1.c: New testcase.

33444

+ * gcc.dg/pr60485-2.c: Likewise.

33445

+

33446

+2014-03-15 Dominique d'Humieres <dominiq@lps.ens.fr>

33447

+

33448

+ Backport from mainline

33449

+ PR libfortran/60128

33450

+ * gfortran.dg/fmt_en.f90: New test.

33451

+

33452

+2014-03-15 Jerry DeLisle <jvdelisle@gcc.gnu>

33453

+

33454

+ Backport from mainline

33455

+ PR libfortran/58324

33456

+ * gfortran.dg/list_read_12.f90: New test.

33457

+

33458

+2014-03-13 Joey Ye <joey.ye@arm.com>

33459

+

33460

+ Backport from mainline

33461

+ 2014-03-12 Thomas Preud'homme <thomas.preudhomme@arm.com>

33462

+

33463

+ PR tree-optimization/60454

33464

+ * gcc.c-torture/execute/pr60454.c: New test.

33465

+

33466

+2014-03-08 Janus Weil <janus@gcc.gnu.org>

33467

+

33468

+ PR fortran/60450

33469

+ * gfortran.dg/shape_8.f90: New.

33470

+

33471

+2014-03-06 Jakub Jelinek <jakub@redhat.com>

33472

+

33473

+ Backport from mainline

33474

+ 2014-02-19 Jakub Jelinek <jakub@redhat.com>

33475

+

33476

+ PR c/37743

33477

+ * g++.dg/ext/builtin-bswap1.C: New test.

33478

+ * c-c++-common/pr37743.c: New test.

33479

+

33480

+ PR preprocessor/58844

33481

+ * c-c++-common/cpp/pr58844-1.c: New test.

33482

+ * c-c++-common/cpp/pr58844-2.c: New test.

33483

+

33484

+ 2014-02-13 Jakub Jelinek <jakub@redhat.com>

33485

+

33486

+ PR target/43546

33487

+ * gcc.target/i386/pr43546.c: New test.

33488

+

33489

+ 2014-02-12 Jakub Jelinek <jakub@redhat.com>

33490

+

33491

+ PR c/60101

33492

+ * c-c++-common/pr60101.c: New test.

33493

+

33494

+ 2014-02-11 Jakub Jelinek <jakub@redhat.com>

33495

+

33496

+ PR fortran/52370

33497

+ * gfortran.dg/pr52370.f90: New test.

33498

+

33499

+ PR debug/59776

33500

+ * gcc.dg/guality/pr59776.c: New test.

33501

+

33502

+ 2014-02-07 Jakub Jelinek <jakub@redhat.com>

33503

+

33504

+ PR preprocessor/56824

33505

+ * gcc.dg/pr56824.c: New test.

33506

+

33507

+ 2014-02-06 Jakub Jelinek <jakub@redhat.com>

33508

+

33509

+ PR target/60062

33510

+ * gcc.c-torture/execute/pr60062.c: New test.

33511

+ * gcc.c-torture/execute/pr60072.c: New test.

33512

+

33513

+ 2014-02-04 Jakub Jelinek <jakub@redhat.com>

33514

+

33515

+ PR ipa/60026

33516

+ * c-c++-common/torture/pr60026.c: New test.

33517

+

33518

+ 2014-02-05 Jakub Jelinek <jakub@redhat.com>

33519

+

33520

+ PR middle-end/57499

33521

+ * g++.dg/torture/pr57499.C: New test.

33522

+

33523

+ 2014-03-03 Jakub Jelinek <jakub@redhat.com>

33524

+

33525

+ PR preprocessor/60400

33526

+ * c-c++-common/cpp/pr60400.c: New test.

33527

+ * c-c++-common/cpp/pr60400-1.h: New file.

33528

+ * c-c++-common/cpp/pr60400-2.h: New file.

33529

+

33530

+2014-03-04 Richard Biener <rguenther@suse.de>

33531

+

33532

+ PR tree-optimization/60382

33533

+ * gcc.dg/vect/pr60382.c: New testcase.

33534

+

33535

+2014-03-02 Mikael Morin <mikael@gcc.gnu.org>

33536

+

33537

+ PR fortran/60341

33538

+ * gfortran.dg/str_comp_optimize_1.f90: New test.

33539

+

33540

+2014-02-25 Richard Biener <rguenther@suse.de>

33541

+

33542

+ Backport from mainline

33543

+ 2014-02-21 Richard Biener <rguenther@suse.de>

33544

+

33545

+ PR tree-optimization/60276

33546

+ * gcc.dg/vect/pr60276.c: New testcase.

33547

+

33548

+2014-02-25 Richard Biener <rguenther@suse.de>

33549

+

33550

+ Backport from mainline

33551

+ 2014-02-14 Richard Biener <rguenther@suse.de>

33552

+

33553

+ PR tree-optimization/60183

33554

+ * gcc.dg/torture/pr60183.c: New testcase.

33555

+

33556

+2014-02-24 Fabien Chêne <fabien@gcc.gnu.org>

33557

+

33558

+ PR c++/37140

33559

+ * g++.dg/template/using27.C: New.

33560

+ * g++.dg/template/using28.C: New.

33561

+ * g++.dg/template/using29.C: New.

33562

+

33563

+2014-02-23 David Holsgrove <david.holsgrove@xilinx.com>

33564

+

33565

+ * gcc/testsuite/gcc.target/microblaze/others/mem_reload.c: New test.

33566

+

33567

+2014-02-22 Mikael Morin <mikael@gcc.gnu.org>

33568

+

33569

+ PR fortran/59599

33570

+ * gfortran.dg/ichar_3.f90: New test.

33571

+

33572

+2014-02-21 Steven G. Kargl <kargl@gcc.gnu.org>

33573

+

33574

+ Backport from mainline

33575

+ PR fortran/59700

33576

+ * gfortran.dg/pr59700.f90: New test.

33577

+

33578

+2014-02-21 Martin Jambor <mjambor@suse.cz>

33579

+

33580

+ PR ipa/55260

33581

+ * gcc.dg/ipa/pr55260.c: New test.

33582

+

33583

+2014-02-19 Tobias Burnus <burnus@net-b.de>

33584

+

33585

+ PR fortran/49397

33586

+ * gfortran.dg/proc_ptr_45.f90: New.

33587

+ * gfortran.dg/proc_ptr_46.f90: New.

33588

+

33589

+2014-02-19 Uros Bizjak <ubizjak@gmail.com>

33590

+

33591

+ Backport from mainline

33592

+ 2014-02-19 Uros Bizjak <ubizjak@gmail.com>

33593

+

33594

+ PR target/59794

33595

+ * gcc.target/i386/pr39162.c: Add dg-prune-output.

33596

+ (dg-options): Remove -Wno-psabi.

33597

+ * gcc.target/i386/pr59794-2.c: Ditto.

33598

+ * gcc.target/i386/sse-5.c: Ditto.

33599

+

33600

+2014-02-19 Janus Weil <janus@gcc.gnu.org>

33601

+

33602

+ Backports from mainline:

33603

+ 2014-02-17 Janus Weil <janus@gcc.gnu.org>

33604

+

33605

+ PR fortran/55907

33606

+ * gfortran.dg/init_flag_12.f90: New.

33607

+

33608

+ 2014-02-18 Janus Weil <janus@gcc.gnu.org>

33609

+

33610

+ PR fortran/60231

33611

+ * gfortran.dg/typebound_generic_15.f90: New.

33612

+

33613

+2014-02-18 Kai Tietz <ktietz@redhat.com>

33614

+

33615

+ PR target/60193

33616

+ * gcc.target/i386/nest-1.c: New testcase.

33617

+

33618

+2014-02-18 Eric Botcazou <ebotcazou@adacore.com>

33619

+

33620

+ * gnat.dg/opt32.adb: New test.

33621

+

33622

+2014-02-15 Jerry DeLisle <jvdelisle@gcc.gnu>

33623

+ Dominique d'Humieres <dominiq@lps.ens.fr>

33624

+

33625

+ Backport from mainline

33626

+ PR libfortran/59771

33627

+ PR libfortran/59774

33628

+ PR libfortran/59836

33629

+ * gfortran.dg/fmt_g_1.f90: New test.

33630

+ * gfortran.dg/round_3.f08: New cases added.

33631

+

33632

+2014-02-13 Dominik Vogt <vogt@linux.vnet.ibm.com>

33633

+

33634

+ * gcc.target/s390/hotpatch-compile-8.c: New test.

33635

+

33636

+2014-02-12 Eric Botcazou <ebotcazou@adacore.com>

33637

+

33638

+ * gcc.c-torture/execute/20140212-1.c: New test.

33639

+

33640

+2014-02-10 Richard Biener <rguenther@suse.de>

33641

+

33642

+ Backport from mainline

33643

+ 2014-01-30 Richard Biener <rguenther@suse.de>

33644

+

33645

+ PR tree-optimization/59903

33646

+ * gcc.dg/torture/pr59903.c: New testcase.

33647

+

33648

+ 2014-02-10 Richard Biener <rguenther@suse.de>

33649

+

33650

+ PR tree-optimization/60115

33651

+ * gcc.dg/torture/pr60115.c: New testcase.

33652

+

33653

+2014-02-09 Janus Weil <janus@gcc.gnu.org>

33654

+

33655

+ Backport from mainline

33656

+ 2013-10-21 Tobias Burnus <burnus@net-b.de>

33657

+

33658

+ PR fortran/58803

33659

+ PR fortran/59395

33660

+ * gfortran.dg/proc_ptr_comp_38.f90: New.

33661

+

33662

+2014-02-08 Mikael Morin <mikael@gcc.gnu.org>

33663

+

33664

+ PR fortran/57033

33665

+ * gfortran.dg/default_initialization_7.f90: New test.

33666

+

33667

+2014-02-07 Paul Thomas <pault@gcc.gnu.org>

33668

+

33669

+ PR fortran/59906

33670

+ * gfortran.dg/elemental_subroutine_9.f90 : New test

33671

+

33672

+2014-02-04 Uros Bizjak <ubizjak@gmail.com>

33673

+

33674

+ Backport from mainline

33675

+ 2014-02-02 Uros Bizjak <ubizjak@gmail.com>

33676

+

33677

+ PR target/60017

33678

+ * gcc.c-torture/execute/pr60017.c: New test.

33679

+

33680

+2014-02-01 Paul Thomas <pault@gcc.gnu.org>

33681

+

33682

+ PR fortran/59414

33683

+ * gfortran.dg/allocate_class_3.f90 : New test

33684

+

33685

+2014-01-30 David Holsgrove <david.holsgrove@xilinx.com>

33686

+

33687

+ Backport from mainline.

33688

+ * gcc.target/microblaze/isa/fcmp4.c: New.

33689

+

33690

+2014-01-26 Mikael Morin <mikael@gcc.gnu.org>

33691

+

33692

+ PR fortran/58007

33693

+ * gfortran.dg/unresolved_fixup_1.f90: New test.

33694

+ * gfortran.dg/unresolved_fixup_2.f90: New test.

33695

+

33696

+2014-01-24 H.J. Lu <hongjiu.lu@intel.com>

33697

+

33698

+ Backport from mainline.

33699

+ 2014-01-23 H.J. Lu <hongjiu.lu@intel.com>

33700

+

33701

+ PR target/59929

33702

+ * gcc.target/i386/pr59929.c: New test.

33703

+

33704

+2014-01-24 Paolo Carlini <paolo.carlini@oracle.com>

33705

+

33706

+ PR c++/57524

33707

+ * g++.dg/ext/timevar2.C: New.

33708

+

33709

+2014-01-23 David Holsgrove <david.holsgrove@xilinx.com>

33710

+

33711

+ Backport from mainline.

33712

+ * gcc.target/microblaze/others/builtin-trap.c: New test.

33713

+

33714

+2014-01-23 Marek Polacek <polacek@redhat.com>

33715

+

33716

+ Backport from mainline

33717

+ 2013-10-21 Marek Polacek <polacek@redhat.com>

33718

+

33719

+ PR middle-end/58809

33720

+ * gcc.dg/gomp/pr58809.c: New test.

33721

+

33722

+2014-01-23 Jakub Jelinek <jakub@redhat.com>

33723

+

33724

+ PR middle-end/58809

33725

+ * c-c++-common/gomp/pr58809.c: New test.

33726

+

33727

+2014-01-22 Marek Polacek <polacek@redhat.com>

33728

+

33729

+ Backport from mainline

33730

+ 2014-01-22 Marek Polacek <polacek@redhat.com>

33731

+

33732

+ PR c/59891

33733

+ * gcc.dg/torture/pr59891.c: New test.

33734

+

33735

+2014-01-21 Jakub Jelinek <jakub@redhat.com>

33736

+

33737

+ PR middle-end/59860

33738

+ * gcc.dg/strlenopt-4.c: Expect the same counts on s390*-* as on all

33739

+ other targets.

33740

+

33741

+2014-01-20 Richard Biener <rguenther@suse.de>

33742

+

33743

+ PR middle-end/59860

33744

+ * gcc.dg/pr59860.c: New testcase.

33745

+

33746

+2014-01-20 Marek Polacek <polacek@redhat.com>

33747

+

33748

+ Backported from mainline

33749

+ 2014-01-17 Marek Polacek <polacek@redhat.com>

33750

+

33751

+ PR c++/59838

33752

+ * g++.dg/diagnostic/pr59838.C: New test.

33753

+

33754

+2014-01-19 Paul Thomas <pault@gcc.gnu.org>

33755

+

33756

+ Backport from mainline

33757

+ 2013-12-01 Paul Thomas <pault@gcc.gnu.org>

33758

+

33759

+ PR fortran/34547

33760

+ * gfortran.dg/null_5.f90 : Include new error.

33761

+ * gfortran.dg/null_6.f90 : Include new error.

33762

+

33763

+2014-01-17 H.J. Lu <hongjiu.lu@intel.com>

33764

+

33765

+ Backport from mainline

33766

+ 2014-01-15 H.J. Lu <hongjiu.lu@intel.com>

33767

+

33768

+ PR target/59794

33769

+ * c-c++-common/convert-vec-1.c: Also prune ABI change for

33770

+ Linux/x86.

33771

+ * g++.dg/cpp0x/constexpr-53094-2.C: Likewise.

33772

+ * g++.dg/ext/attribute-test-1.C: Likewise.

33773

+ * g++.dg/ext/attribute-test-2.C: Likewise.

33774

+ * g++.dg/ext/attribute-test-3.C: Likewise.

33775

+ * g++.dg/ext/attribute-test-4.C: Likewise.

33776

+ * g++.dg/torture/pr38565.C: Likewise.

33777

+ * gcc.dg/pr53060.c: Likewise.

33778

+ * c-c++-common/scal-to-vec2.c: Add -msse2 for x86.

33779

+ * c-c++-common/vector-compare-2.c: Likewise.

33780

+ * gcc.dg/Wstrict-aliasing-bogus-ref-all-2.c: Likewise.

33781

+ * g++.dg/conversion/simd1.C: Add -msse2 for x86. Adjust

33782

+ dg-message line number.

33783

+

33784

+2014-01-17 H.J. Lu <hongjiu.lu@intel.com>

33785

+

33786

+ Backport from mainline

33787

+ 2014-01-14 H.J. Lu <hongjiu.lu@intel.com>

33788

+

33789

+ PR target/59794

33790

+ * gcc.target/i386/pr39162.c (y): New __m256i variable.

33791

+ (bar): Change return type to void. Set y to x.

33792

+ * gcc.target/i386/pr59794-1.c: New testcase.

33793

+ * gcc.target/i386/pr59794-2.c: Likewise.

33794

+ * gcc.target/i386/pr59794-3.c: Likewise.

33795

+ * gcc.target/i386/pr59794-4.c: Likewise.

33796

+ * gcc.target/i386/pr59794-5.c: Likewise.

33797

+ * gcc.target/i386/pr59794-6.c: Likewise.

33798

+ * gcc.target/i386/pr59794-7.c: Likewise.

33799

+

33800

+2014-01-17 Matthias Klose <doko@ubuntu.com>

33801

+

33802

+ Backport from the trunk:

33803

+ 2014-01-09 Uros Bizjak <ubizjak@gmail.com>

33804

+ * go.test/go-test.exp (go-gc-tests): Don't run peano.go on systems

33805

+ which don't support -fsplit-stack. Skip rotate[0123].go tests.

33806

+

33807

+2014-01-15 Kugan Vivekanandarajah <kuganv@linaro.org>

33808

+

33809

+ Backport from mainline

33810

+ 2014-01-15 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org>

33811

+ Kugan Vivekanandarajah <kuganv@linaro.org>

33812

+

33813

+ PR target/59695

33814

+ * g++.dg/pr59695.C: New testcase.

33815

+

33816

+2014-01-17 Terry Guo <terry.guo@arm.com>

33817

+

33818

+ * gcc.target/arm/pr59826.c: New test.

33819

+

33820

+2014-01-16 Jakub Jelinek <jakub@redhat.com>

33821

+

33822

+ PR target/59839

33823

+ * gcc.target/i386/pr59839.c: New test.

33824

+

33825

+ PR debug/54694

33826

+ * gcc.target/i386/pr9771-1.c (main): Rename to...

33827

+ (real_main): ... this. Add __asm name "main".

33828

+ (ASMNAME, ASMNAME2, STRING): Define.

33829

+

33830

+2014-01-16 Marek Polacek <polacek@redhat.com>

33831

+

33832

+ Backported from mainline

33833

+ 2014-01-16 Marek Polacek <polacek@redhat.com>

33834

+

33835

+ PR middle-end/59827

33836

+ * gcc.dg/pr59827.c: New test.

33837

+

33838

+2014-01-15 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>

33839

+

33840

+ PR target/59803

33841

+ * gcc.c-torture/compile/pr59803.c: New testcase.

33842

+

33843

+2014-01-10 Yufeng Zhang <yufeng.zhang@arm.com>

33844

+

33845

+ * gcc.target/arm/neon/vst1Q_laneu64-1.c: New test.

33846

+

33847

+2014-01-10 Hans-Peter Nilsson <hp@axis.com>

33848

+

33849

+ * gcc.dg/pr46309.c: Disable for cris*-*-*.

33850

+

33851

+2014-01-10 Paolo Carlini <paolo.carlini@oracle.com>

33852

+

33853

+ PR c++/56060

33854

+ PR c++/59730

33855

+ * g++.dg/cpp0x/variadic144.C: New.

33856

+ * g++.dg/cpp0x/variadic145.C: Likewise.

33857

+

33858

+2014-01-10 Richard Biener <rguenther@suse.de>

33859

+

33860

+ PR tree-optimization/59715

33861

+ * gcc.dg/torture/pr59715.c: New testcase.

33862

+

33863

+2014-01-09 Richard Sandiford <rdsandiford@googlemail.com>

33864

+

33865

+ * gcc.target/mips/bswap-1.c, gcc.target/mips/bswap-2.c,

33866

+ gcc.target/mips/bswap-3.c, gcc.target/mips/bswap-4.c,

33867

+ gcc.target/mips/bswap-5.c, gcc.target/mips/bswap-6.c: New tests.

33868

+

33869

+2014-01-09 Richard Sandiford <rdsandiford@googlemail.com>

33870

+

33871

+ PR rtl-optimization/59137

33872

+ * gcc.target/mips/pr59137.c: New test.

33873

+

33874

+2014-01-09 Richard Biener <rguenther@suse.de>

33875

+

33876

+ Backport from mainline

33877

+ 2013-11-18 Richard Biener <rguenther@suse.de>

33878

+

33879

+ PR tree-optimization/59125

33880

+ PR tree-optimization/54570

33881

+ * gcc.dg/builtin-object-size-8.c: Un-xfail.

33882

+ * gcc.dg/builtin-object-size-14.c: New testcase.

33883

+ * gcc.dg/strlenopt-14gf.c: Adjust.

33884

+ * gcc.dg/strlenopt-1f.c: Likewise.

33885

+ * gcc.dg/strlenopt-4gf.c: Likewise.

33886

+

33887

+ 2013-12-03 Jakub Jelinek <jakub@redhat.com>

33888

+

33889

+ PR tree-optimization/59362

33890

+ * gcc.c-torture/compile/pr59362.c: New test.

33891

+

33892

+2014-01-09 Richard Earnshaw <rearnsha@arm.com>

33893

+

33894

+ PR rtl-optimization/54300

33895

+ * gcc.target/arm/pr54300.C: New test.

33896

+

33897

+2014-01-08 Martin Jambor <mjambor@suse.cz>

33898

+

33899

+ PR ipa/59610

33900

+ * gcc.dg/ipa/pr59610.c: New test.

33901

+

33902

+2014-01-07 Jakub Jelinek <jakub@redhat.com>

33903

+

33904

+ PR rtl-optimization/58668

33905

+ * gcc.dg/pr58668.c: New test.

33906

+

33907

+ Backported from mainline

33908

+ 2013-12-16 Jakub Jelinek <jakub@redhat.com>

33909

+

33910

+ PR middle-end/58956

33911

+ PR middle-end/59470

33912

+ * gcc.target/i386/pr59470.c: New test.

33913

+

33914

+2014-01-04 Janus Weil <janus@gcc.gnu.org>

33915

+

33916

+ Backport from mainline

33917

+ 2014-01-02 Janus Weil <janus@gcc.gnu.org>

33918

+

33919

+ PR fortran/59654

33920

+ * gfortran.dg/dynamic_dispatch_12.f90: New.

33921

+

33922

+2014-01-03 Joseph Myers <joseph@codesourcery.com>

33923

+

33924

+ * gcc.target/powerpc/rs6000-ldouble-3.c: New test.

33925

+

33926

+2014-01-03 Jakub Jelinek <jakub@redhat.com>

33927

+

33928

+ PR target/59625

33929

+ * gcc.target/i386/pr59625.c: New test.

33930

+

33931

+2014-01-01 Jakub Jelinek <jakub@redhat.com>

33932

+

33933

+ PR rtl-optimization/59647

33934

+ * g++.dg/opt/pr59647.C: New test.

33935

+

33936

+2013-12-31 Janus Weil <janus@gcc.gnu.org>

33937

+

33938

+ Backport from mainline

33939

+ 2013-12-30 Janus Weil <janus@gcc.gnu.org>

33940

+

33941

+ PR fortran/58998

33942

+ * gfortran.dg/generic_28.f90: New.

33943

+

33944

+2013-12-20 Jakub Jelinek <jakub@redhat.com>

33945

+

33946

+ PR c++/59255

33947

+ * g++.dg/tree-prof/pr59255.C: New test.

33948

+

33949

+2013-12-19 James Greenhalgh <james.greenhalgh@arm.com>

33950

+

33951

+ Backport from Mainline

33952

+ 2013-05-01 James Greenhalgh <james.greenhalgh@arm.com>

33953

+

33954

+ * gcc.target/aarch64/scalar_intrinsics.c (force_simd): New.

33955

+ (test_vceqd_s64): Force arguments to SIMD registers.

33956

+ (test_vceqzd_s64): Likewise.

33957

+ (test_vcged_s64): Likewise.

33958

+ (test_vcled_s64): Likewise.

33959

+ (test_vcgezd_s64): Likewise.

33960

+ (test_vcged_u64): Likewise.

33961

+ (test_vcgtd_s64): Likewise.

33962

+ (test_vcltd_s64): Likewise.

33963

+ (test_vcgtzd_s64): Likewise.

33964

+ (test_vcgtd_u64): Likewise.

33965

+ (test_vclezd_s64): Likewise.

33966

+ (test_vcltzd_s64): Likewise.

33967

+ (test_vtst_s64): Likewise.

33968

+ (test_vtst_u64): Likewise.

33969

+

33970

+2013-12-19 Dominik Vogt <vogt@linux.vnet.ibm.com>

33971

+ Andreas Krebbel <Andreas.Krebbel@de.ibm.com>

33972

+

33973

+ Backport from mainline

33974

+ 2013-12-19 Dominik Vogt <vogt@linux.vnet.ibm.com>

33975

+ * gcc/testsuite/gcc.target/s390/hotpatch-1.c: New test

33976

+ * gcc/testsuite/gcc.target/s390/hotpatch-2.c: New test

33977

+ * gcc/testsuite/gcc.target/s390/hotpatch-3.c: New test

33978

+ * gcc/testsuite/gcc.target/s390/hotpatch-4.c: New test

33979

+ * gcc/testsuite/gcc.target/s390/hotpatch-5.c: New test

33980

+ * gcc/testsuite/gcc.target/s390/hotpatch-6.c: New test

33981

+ * gcc/testsuite/gcc.target/s390/hotpatch-7.c: New test

33982

+ * gcc/testsuite/gcc.target/s390/hotpatch-8.c: New test

33983

+ * gcc/testsuite/gcc.target/s390/hotpatch-9.c: New test

33984

+ * gcc/testsuite/gcc.target/s390/hotpatch-10.c: New test

33985

+ * gcc/testsuite/gcc.target/s390/hotpatch-11.c: New test

33986

+ * gcc/testsuite/gcc.target/s390/hotpatch-12.c: New test

33987

+ * gcc/testsuite/gcc.target/s390/hotpatch-compile-1.c: New test

33988

+ * gcc/testsuite/gcc.target/s390/hotpatch-compile-2.c: New test

33989

+ * gcc/testsuite/gcc.target/s390/hotpatch-compile-3.c: New test

33990

+ * gcc/testsuite/gcc.target/s390/hotpatch-compile-4.c: New test

33991

+ * gcc/testsuite/gcc.target/s390/hotpatch-compile-5.c: New test

33992

+ * gcc/testsuite/gcc.target/s390/hotpatch-compile-6.c: New test

33993

+ * gcc/testsuite/gcc.target/s390/hotpatch-compile-7.c: New test

33994

+

33995

+2013-12-18 Janus Weil <janus@gcc.gnu.org>

33996

+

33997

+ Backport from mainline

33998

+ 2013-12-15 Janus Weil <janus@gcc.gnu.org>

33999

+

34000

+ PR fortran/59493

34001

+ * gfortran.dg/unlimited_polymorphic_15.f90: New.

34002

+

34003

+2013-12-15 Uros Bizjak <ubizjak@gmail.com>

34004

+

34005

+ PR testsuite/58630

34006

+ * gcc.target/i386/pr43662.c (dg-options):

34007

+ Add -maccumulate-outgoing-args.

34008

+ * gcc.target/i386/pr43869.c (dg-options): Ditto.

34009

+ * gcc.target/i386/pr57003.c (dg-options): Ditto.

34010

+ * gcc.target/i386/avx-vzeroupper-16.c (dg-options):

34011

+ Remove -mtune=generic and add -maccumulate-outgoing-args instead.

34012

+ * gcc.target/i386/avx-vzeroupper-17.c (dg-options): Ditto.

34013

+ * gcc.target/i386/avx-vzeroupper-18.c (dg-options): Ditto.

34014

+ * gcc.target/x86_64/abi/callabi/func-1.c (dg-options):

34015

+ Add -maccumulate-outgoing-args.

34016

+ * gcc.target/x86_64/abi/callabi/func-2a.c (dg-options): Ditto.

34017

+ * gcc.target/x86_64/abi/callabi/func-2b.c (dg-options): Ditto.

34018

+ * gcc.target/x86_64/abi/callabi/func-indirect.c (dg-options): Ditto.

34019

+ * gcc.target/x86_64/abi/callabi/func-indirect-2a.c (dg-options): Ditto.

34020

+ * gcc.target/x86_64/abi/callabi/func-indirect-2b.c (dg-options): Ditto.

34021

+ * gcc.target/x86_64/abi/callabi/leaf-1.c (dg-options): Ditto.

34022

+ * gcc.target/x86_64/abi/callabi/leaf-2.c (dg-options): Ditto.

34023

+ * gcc.target/x86_64/abi/callabi/pr38891.c (dg-options): Ditto.

34024

+ * gcc.target/x86_64/abi/callabi/vaarg-1.c (dg-options): Ditto.

34025

+ * gcc.target/x86_64/abi/callabi/vaarg-2.c (dg-options): Ditto.

34026

+ * gcc.target/x86_64/abi/callabi/vaarg-3.c (dg-options): Ditto.

34027

+ * gcc.target/x86_64/abi/callabi/vaarg-4a.c (dg-options): Ditto.

34028

+ * gcc.target/x86_64/abi/callabi/vaarg-4b.c (dg-options): Ditto.

34029

+ * gcc.target/x86_64/abi/callabi/vaarg-5a.c (dg-options): Ditto.

34030

+ * gcc.target/x86_64/abi/callabi/vaarg-5b.c (dg-options): Ditto.

34031

+

34032

+2013-12-12 Jakub Jelinek <jakub@redhat.com>

34033

+

34034

+ PR middle-end/59470

34035

+ * g++.dg/opt/pr59470.C: New test.

34036

+

34037

+ PR libgomp/59467

34038

+ * gfortran.dg/gomp/pr59467.f90: New test.

34039

+ * c-c++-common/gomp/pr59467.c: New test.

34040

+

34041

+2013-12-12 Uros Bizjak <ubizjak@gmail.com>

34042

+

34043

+ Backport from mainline

34044

+ 2013-12-12 Ryan Mansfield <rmansfield@qnx.com>

34045

+

34046

+ PR testsuite/59442

34047

+ * gcc.target/i386/sse2-movapd-1.c: Fix alignment attributes.

34048

+ * gcc.target/i386/sse2-movapd-2.c: Likewise.

34049

+ * gcc.target/i386/avx-vmovapd-256-1.c: Likewise.

34050

+ * gcc.target/i386/avx-vmovapd-256-2.c: Likewise.

34051

+

34052

+2013-12-08 Uros Bizjak <ubizjak@gmail.com>

34053

+

34054

+ Backport from mainline

34055

+ 2013-12-06 Uros Bizjak <ubizjak@gmail.com>

34056

+

34057

+ PR target/59405

34058

+ * gcc.target/i386/pr59405.c: New test.

34059

+

34060

+2013-12-06 Jakub Jelinek <jakub@redhat.com>

34061

+

34062

+ PR tree-optimization/59388

34063

+ * gcc.c-torture/execute/pr59388.c: New test.

34064

+

34065

+2013-12-06 Richard Biener <rguenther@suse.de>

34066

+

34067

+ Backport from mainline

34068

+ 2013-11-28 Richard Biener <rguenther@suse.de>

34069

+

34070

+ PR tree-optimization/59330

34071

+ * gcc.dg/torture/pr59330.c: New testcase.

34072

+

34073

+2013-12-06 Richard Biener <rguenther@suse.de>

34074

+

34075

+ Backport from mainline

34076

+ 2013-11-27 Richard Biener <rguenther@suse.de>

34077

+

34078

+ PR tree-optimization/59288

34079

+ * gcc.dg/torture/pr59288.c: New testcase.

34080

+

34081

+ 2013-11-19 Richard Biener <rguenther@suse.de>

34082

+

34083

+ PR tree-optimization/59164

34084

+ * gcc.dg/torture/pr59164.c: New testcase.

34085

+

34086

+ 2013-09-05 Richard Biener <rguenther@suse.de>

34087

+

34088

+ PR tree-optimization/58137

34089

+ * gcc.target/i386/pr58137.c: New testcase.

34090

+

34091

+2013-12-06 Oleg Endo <olegendo@gcc.gnu.org>

34092

+

34093

+ PR target/51244

34094

+ PR target/59343

34095

+ * gcc.target/sh/pr51244-19.c: Adjust test case.

34096

+

34097

+2013-12-05 Richard Biener <rguenther@suse.de>

34098

+

34099

+ Backport from mainline

34100

+ 2013-11-19 Richard Biener <rguenther@suse.de>

34101

+

34102

+ PR middle-end/58956

34103

+ * gcc.dg/torture/pr58956.c: New testcase.

34104

+

34105

+2013-12-04 Jakub Jelinek <jakub@redhat.com>

34106

+

34107

+ PR c++/59268

34108

+ * g++.dg/cpp0x/constexpr-template6.C: New test.

34109

+

34110

+ PR rtl-optimization/58726

34111

+ * gcc.c-torture/execute/pr58726.c: New test.

34112

+

34113

+ PR target/59163

34114

+ * g++.dg/torture/pr59163.C: New test.

34115

+

34116

+2013-12-03 Marek Polacek <polacek@redhat.com>

34117

+

34118

+ Backport from mainline

34119

+ 2013-12-03 Marek Polacek <polacek@redhat.com>

34120

+

34121

+ PR c/59351

34122

+ * gcc.dg/pr59351.c: New test.

34123

+

34124

+2013-12-03 Jakub Jelinek <jakub@redhat.com>

34125

+

34126

+ PR middle-end/59011

34127

+ * gcc.dg/pr59011.c: New test.

34128

+

34129

+ PR target/58864

34130

+ * g++.dg/opt/pr58864.C: New test.

34131

+

34132

+2013-12-02 Jakub Jelinek <jakub@redhat.com>

34133

+

34134

+ PR tree-optimization/59358

34135

+ * gcc.c-torture/execute/pr59358.c: New test.

34136

+

34137

+2013-12-02 Richard Biener <rguenther@suse.de>

34138

+

34139

+ PR tree-optimization/59139

34140

+ * gcc.dg/torture/pr59139.c: New testcase.

34141

+

34142

+2013-11-27 Tom de Vries <tom@codesourcery.com>

34143

+ Marc Glisse <marc.glisse@inria.fr>

34144

+

34145

+ PR c++/59032

34146

+ * c-c++-common/pr59032.c: New testcase.

34147

+

34148

+2013-11-27 Tom de Vries <tom@codesourcery.com>

34149

+ Marc Glisse <marc.glisse@inria.fr>

34150

+

34151

+ PR middle-end/59037

34152

+ * c-c++-common/pr59037.c: New testcase.

34153

+

34154

+2013-11-30 Paul Thomas <pault@gcc.gnu.org>

34155

+

34156

+ Backport from mainline

34157

+ 2013-11-04 Paul Thomas <pault@gcc.gnu.org>

34158

+

34159

+ PR fortran/57445

34160

+ * gfortran.dg/optional_class_1.f90 : New test

34161

+

34162

+2013-11-29 Jakub Jelinek <jakub@redhat.com>

34163

+

34164

+ PR c/59280

34165

+ * c-c++-common/pr59280.c: New test.

34166

+

34167

+2013-11-28 Jakub Jelinek <jakub@redhat.com>

34168

+

34169

+ PR c++/59297

34170

+ * g++.dg/gomp/pr59297.C: New test.

34171

+

34172

+2013-11-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com>

34173

+

34174

+ Backport from mainline

34175

+ 2013-11-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com>

34176

+

34177

+ * gcc.target/arm/vrinta-ce.c: New testcase.

34178

+

34179

+2013-11-28 Uros Bizjak <ubizjak@gmail.com>

34180

+

34181

+ Backport from mainline

34182

+ 2013-11-23 Uros Bizjak <ubizjak@gmail.com>

34183

+

34184

+ PR target/56788

34185

+ * config/i386/i386.c (bdesc_multi_arg) <IX86_BUILTIN_VFRCZSS>:

34186

+ Declare as MULTI_ARG_1_SF instruction.

34187

+ <IX86_BUILTIN_VFRCZSD>: Decleare as MULTI_ARG_1_DF instruction.

34188

+ * config/i386/sse.md (*xop_vmfrcz<mode>2): Rename

34189

+ from *xop_vmfrcz_<mode>.

34190

+ * config/i386/xopintrin.h (_mm_frcz_ss): Use __builtin_ia32_movss

34191

+ to merge scalar result with __A.

34192

+ (_mm_frcz_sd): Use __builtin_ia32_movsd to merge scalar

34193

+ result with __A.

34194

+

34195

+2013-11-28 Terry Guo <terry.guo@arm.com>

34196

+

34197

+ Backport mainline r205391

34198

+ 2013-11-26 Terry Guo <terry.guo@arm.com>

34199

+

34200

+ * gcc.target/arm/thumb1-pic-high-reg.c: New case.

34201

+ * gcc.target/arm/thumb1-pic-single-base.c: New case.

34202

+

34203

+2013-11-27 Jakub Jelinek <jakub@redhat.com>

34204

+

34205

+ Backported from mainline

34206

+ 2013-11-27 Jakub Jelinek <jakub@redhat.com>

34207

+

34208

+ PR tree-optimization/59014

34209

+ * gcc.c-torture/execute/pr59014-2.c: New test.

34210

+

34211

+ 2013-11-26 Jakub Jelinek <jakub@redhat.com>

34212

+

34213

+ PR tree-optimization/59014

34214

+ * gcc.c-torture/execute/pr59014.c: New test.

34215

+

34216

+2013-11-27 Eric Botcazou <ebotcazou@adacore.com>

34217

+

34218

+ * gcc.c-torture/execute/20131127-1.c: New test.

34219

+

34220

+2013-11-25 Vidya Praveen <vidyapraveen@arm.com>

34221

+

34222

+ Backport from mainline

34223

+ 2013-10-21 Vidya Praveen <vidyapraveen@arm.com>

34224

+

34225

+ * gcc.dg/20050922-1.c: Remove stdlib.h and declare abort().

34226

+ * gcc.dg/20050922-1.c: Remove stdlib.h and declare abort() and exit().

34227

+

34228

+2013-11-20 Dominik Vogt <vogt@linux.vnet.ibm.com>

34229

+

34230

+ Backport from mainline

34231

+ * gcc.target/s390/htm-1.c: Rename to ...

34232

+ * gcc/testsuite/gcc.target/s390/htm-builtins-compile-1.c: ... this

34233

+ one.

34234

+ * gcc.target/s390/htm-xl-intrin-1.c: Rename to ...

34235

+ * gcc.target/s390/htm-builtins-compile-3.c: ... this one.

34236

+ * gcc.target/s390/htm-builtins-compile-2.c: New testcase.

34237

+ * gcc.target/s390/htm-builtins-1.c: New testcase.

34238

+ * gcc.target/s390/htm-builtins-2.c: New testcase.

34239

+ * gcc.target/s390/s390.exp: Add check for htm machine.

34240

+

34241

+2013-11-19 Richard Biener <rguenther@suse.de>

34242

+

34243

+ PR tree-optimization/57517

34244

+ * gfortran.fortran-torture/compile/pr57517.f90: New testcase.

34245

+ * gcc.dg/torture/pr57517.c: Likewise.

34246

+

34247

+2013-11-19 Richard Biener <rguenther@suse.de>

34248

+

34249

+ Backport from mainline

34250

+ 2013-11-05 Richard Biener <rguenther@suse.de>

34251

+

34252

+ PR middle-end/58941

34253

+ * gcc.dg/torture/pr58941.c: New testcase.

34254

+

34255

+2013-11-18 Richard Biener <rguenther@suse.de>

34256

+

34257

+ Backport from mainline

34258

+ 2013-10-21 Richard Biener <rguenther@suse.de>

34259

+

34260

+ PR tree-optimization/58794

34261

+ * c-c++-common/torture/pr58794-1.c: New testcase.

34262

+ * c-c++-common/torture/pr58794-2.c: Likewise.

34263

+

34264

+ 2013-10-21 Richard Biener <rguenther@suse.de>

34265

+

34266

+ PR middle-end/58742

34267

+ * c-c++-common/fold-divmul-1.c: New testcase.

34268

+

34269

+ 2013-11-06 Richard Biener <rguenther@suse.de>

34270

+

34271

+ PR tree-optimization/58653

34272

+ * gcc.dg/tree-ssa/predcom-6.c: New testcase.

34273

+ * gcc.dg/tree-ssa/predcom-7.c: Likewise.

34274

+

34275

+ PR tree-optimization/59047

34276

+ * gcc.dg/torture/pr59047.c: New testcase.

34277

+

34278

+ 2013-10-15 Richard Biener <rguenther@suse.de>

34279

+

34280

+ PR tree-optimization/58143

34281

+ * gcc.dg/torture/pr58143-1.c: New testcase.

34282

+ * gcc.dg/torture/pr58143-2.c: Likewise.

34283

+ * gcc.dg/torture/pr58143-3.c: Likewise.

34284

+

34285

+2013-11-17 Janus Weil <janus@gcc.gnu.org>

34286

+

34287

+ Backport from mainline

34288

+ 2013-11-07 Janus Weil <janus@gcc.gnu.org>

34289

+

34290

+ PR fortran/58471

34291

+ * gfortran.dg/constructor_9.f90: New.

34292

+

34293

+2013-11-16 Janus Weil <janus@gcc.gnu.org>

34294

+

34295

+ Backport from mainline

34296

+ 2013-09-20 Janus Weil <janus@gcc.gnu.org>

34297

+

34298

+ PR fortran/58099

34299

+ * gfortran.dg/proc_ptr_43.f90: New.

34300

+

34301

+2013-11-16 Paul Thomas <pault@gcc.gnu.org>

34302

+

34303

+ PR fortran/58771

34304

+ * gfortran.dg/derived_external_function_1.f90 : New test

34305

+

34306

+2013-11-14 Uros Bizjak <ubizjak@gmail.com>

34307

+

34308

+ Backport from mainline

34309

+ 2013-11-06 Uros Bizjak <ubizjak@gmail.com>

34310

+

34311

+ PR target/59021

34312

+ * gcc.target/i386/pr59021.c: New test.

34313

+

34314

+2013-11-14 Jakub Jelinek <jakub@redhat.com>

34315

+

34316

+ PR target/59101

34317

+ * gcc.c-torture/execute/pr59101.c: New test.

34318

+

34319

+2013-11-11 Jakub Jelinek <jakub@redhat.com>

34320

+

34321

+ Backported from mainline

34322

+ 2013-11-06 Jakub Jelinek <jakub@redhat.com>

34323

+

34324

+ PR middle-end/58970

34325

+ * gcc.c-torture/compile/pr58970-1.c: New test.

34326

+ * gcc.c-torture/compile/pr58970-2.c: New test.

34327

+

34328

+ 2013-11-05 Jakub Jelinek <jakub@redhat.com>

34329

+

34330

+ PR rtl-optimization/58997

34331

+ * gcc.c-torture/compile/pr58997.c: New test.

34332

+

34333

+2013-11-10 Wei Mi <wmi@google.com>

34334

+

34335

+ * gcc.dg/pr57518.c: Backport regex fix from r200720.

34336

+

34337

+2013-11-07 H.J. Lu <hongjiu.lu@intel.com>

34338

+

34339

+ Backport from mainline

34340

+ 2013-11-07 H.J. Lu <hongjiu.lu@intel.com>

34341

+

34342

+ PR target/59034

34343

+ * gcc.target/i386/pr59034-1.c: New test.

34344

+ * gcc.target/i386/pr59034-2.c: Likewise.

34345

+

34346

+2013-11-06 Wei Mi <wmi@google.com>

34347

+

34348

+ PR regression/58985

34349

+ * gcc.dg/pr57518.c: Add subreg in regexp pattern.

34350

+

34351

+2013-11-05 Steven G. Kargl <kargl@gcc.gnu.org>

34352

+

34353

+ PR fortran/58989

34354

+ * gfortran.dg/reshape_6.f90: New test.

34355

+

34356

+2013-11-05 Jakub Jelinek <jakub@redhat.com>

34357

+

34358

+ PR tree-optimization/58984

34359

+ * gcc.c-torture/execute/pr58984.c: New test.

34360

+

34361

+2013-11-04 Marek Polacek <polacek@redhat.com>

34362

+

34363

+ Backport from mainline

34364

+ 2013-11-04 Marek Polacek <polacek@redhat.com>

34365

+

34366

+ PR c++/58979

34367

+ * g++.dg/diagnostic/pr58979.C: New test.

34368

+

34369

+2013-11-03 H.J. Lu <hongjiu.lu@intel.com>

34370

+

34371

+ Backport from mainline

34372

+ 2013-10-12 H.J. Lu <hongjiu.lu@intel.com>

34373

+

34374

+ PR target/58690

34375

+ * gcc.target/i386/pr58690.c: New test

34376

+

34377

+2013-11-02 Janus Weil <janus@gcc.gnu.org>

34378

+

34379

+ Backport from mainline

34380

+ 2013-09-23 Janus Weil <janus@gcc.gnu.org>

34381

+

34382

+ PR fortran/58355

34383

+ * gfortran.dg/extends_15.f90: New.

34384

+

34385

+2013-10-29 Uros Bizjak <ubizjak@gmail.com>

34386

+

34387

+ Backport from mainline

34388

+ 2013-08-08 Richard Sandiford <rdsandiford@googlemail.com>

34389

+

34390

+ PR rtl-optimization/58079

34391

+ * gcc.dg/torture/pr58079.c: New test.

34392

+

34393

+2013-10-28 Tom de Vries <tom@codesourcery.com>

34394

+

34395

+ * gcc.target/arm/require-pic-register-loc.c: New test.

34396

+

34397

+2013-10-26 Uros Bizjak <ubizjak@gmail.com>

34398

+

34399

+ Backport from mainline

34400

+ 2013-10-22 Uros Bizjak <ubizjak@gmail.com>

34401

+

34402

+ PR target/58779

34403

+ * gcc.target/i386/pr30315.c: Remove MINUSCC, DECCC, MINUSCCONLY

34404

+ and MINUSCCZEXT defines. Update scan-assembler dg directive.

34405

+ * gcc.dg/torture/pr58779.c: New test.

34406

+

34407

+2013-10-25 Richard Henderson <rth@redhat.com>

34408

+

34409

+ PR rtl/58542

34410

+ * gcc.dg/atomic-store-6.c: New.

34411

+

34412

+2013-10-25 Tom de Vries <tom@codesourcery.com>

34413

+

34414

+ PR c++/58282

34415

+ * g++.dg/tm/noexcept-6.C: New test.

34416

+

34417

+2013-10-25 Eric Botcazou <ebotcazou@adacore.com>

34418

+

34419

+ * gcc.c-torture/execute/pr58831.c: New test.

34420

+

34421

+2013-10-23 Tom de Vries <tom@codesourcery.com>

34422

+

34423

+ PR tree-optimization/58805

34424

+ * gcc.dg/pr58805.c: New test.

34425

+

34426

+2013-10-23 Richard Biener <rguenther@suse.de>

34427

+

34428

+ * gcc.dg/torture/pr58830.c: New testcase.

34429

+

34430

+ Backport from mainline

34431

+ 2013-06-24 Richard Biener <rguenther@suse.de>

34432

+

34433

+ PR tree-optimization/57488

34434

+ * gcc.dg/torture/pr57488.c: New testcase.

34435

+

34436

+2013-10-19 Oleg Endo <olegendo@gcc.gnu.org>

34437

+

34438

+ * gcc.target/sh/pr54089-3.c: Fix test for load of constant 31.

34439

+

34440

+2013-10-17 Paolo Carlini <paolo.carlini@oracle.com>

34441

+

34442

+ PR c++/58596

34443

+ * g++.dg/cpp0x/lambda/lambda-nsdmi5.C: New

34444

+

34445

+2013-10-16 Paolo Carlini <paolo.carlini@oracle.com>

34446

+

34447

+ PR c++/58633

34448

+ * g++.dg/cpp0x/decltype57.C: New.

34449

+ * g++.dg/cpp0x/enum18.C: Revert r174385 changes.

34450

+

34451

2013-10-16 Release Manager

34452

34453

* GCC 4.8.2 released.

34454

@@ -39,9 +1832,9 @@

34455

Backport from mainline

34456

2013-06-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>

34457

34458

- * gcc.target/s390/htm-1.c: New file.

34459

- * gcc.target/s390/htm-nofloat-1.c: New file.

34460

- * gcc.target/s390/htm-xl-intrin-1.c: New file.

34461

+ * gcc.target/s390/htm-1.c: New file.

34462

+ * gcc.target/s390/htm-nofloat-1.c: New file.

34463

+ * gcc.target/s390/htm-xl-intrin-1.c: New file.

34464

34465

2013-10-04 Tobias Burnus <burnus@net-b.de>

34466

34467

@@ -307,8 +2100,8 @@

34468

Backport from mainline

34469

2013-08-12 Perez Read <netfirewall@gmail.com>

34470

34471

- PR target/58132

34472

- * gcc.target/i386/movabs-1.c: New test.

34473

+ PR target/58132

34474

+ * gcc.target/i386/movabs-1.c: New test.

34475

34476

2013-08-11 Janus Weil <janus@gcc.gnu.org>

34477

34478

@@ -494,7 +2287,7 @@

34479

2013-06-19 Wei Mi <wmi@google.com>

34480

34481

PR rtl-optimization/57518

34482

- * testsuite/gcc.dg/pr57518.c: New test.

34483

+ * gcc.dg/pr57518.c: New test.

34484

34485

2013-06-11 Tobias Burnus <burnus@net-b.de>

34486

34487

@@ -623,8 +2416,8 @@

34488

34489

2013-05-09 Martin Jambor <mjambor@suse.cz>

34490

34491

- PR middle-end/56988

34492

- * gcc.dg/ipa/pr56988.c: New test.

34493

+ PR middle-end/56988

34494

+ * gcc.dg/ipa/pr56988.c: New test.

34495

34496

2013-05-08 Marc Glisse <marc.glisse@inria.fr>

34497

34498

@@ -701,7 +2494,7 @@

34499

2013-04-25 Marek Polacek <polacek@redhat.com>

34500

34501

PR tree-optimization/57066

34502

- * gcc.dg/torture/builtin-logb-1.c: Adjust testcase.

34503

+ * gcc.dg/torture/builtin-logb-1.c: Adjust testcase.

34504

34505

2013-05-02 Jakub Jelinek <jakub@redhat.com>

34506

34507

@@ -727,8 +2520,8 @@

34508

Backport from mainline

34509

2013-04-24 Vladimir Makarov <vmakarov@redhat.com>

34510

34511

- PR rtl-optimizations/57046

34512

- * gcc.target/i386/pr57046.c: New test.

34513

+ PR rtl-optimizations/57046

34514

+ * gcc.target/i386/pr57046.c: New test.

34515

34516

2013-05-02 Vladimir Makarov <vmakarov@redhat.com>

34517

34518

@@ -735,8 +2528,8 @@

34519

Backport from mainline

34520

2013-04-22 Vladimir Makarov <vmakarov@redhat.com>

34521

34522

- PR target/57018

34523

- * gcc.target/i386/pr57018.c: New test.

34524

+ PR target/57018

34525

+ * gcc.target/i386/pr57018.c: New test.

34526

34527

2013-05-02 Vladimir Makarov <vmakarov@redhat.com>

34528

34529

@@ -743,8 +2536,8 @@

34530

Backport from mainline

34531

2013-04-18 Jakub Jelinek <jakub@redhat.com>

34532

34533

- PR rtl-optimization/56999

34534

- * g++.dg/opt/pr56999.C: New test.

34535

+ PR rtl-optimization/56999

34536

+ * g++.dg/opt/pr56999.C: New test.

34537

34538

2013-05-02 Vladimir Makarov <vmakarov@redhat.com>

34539

34540

@@ -751,8 +2544,8 @@

34541

Backport from mainline

34542

2013-04-19 Vladimir Makarov <vmakarov@redhat.com>

34543

34544

- PR rtl-optimization/56847

34545

- * gcc.dg/pr56847.c: New test.

34546

+ PR rtl-optimization/56847

34547

+ * gcc.dg/pr56847.c: New test.

34548

34549

2013-05-02 Ian Bolton <ian.bolton@arm.com>

34550

34551

@@ -1102,7 +2895,7 @@

34552

2013-03-29 Tobias Burnus <burnus@net-b.de>

34553

34554

PR fortran/56737

34555

- * testsuite/gfortran.dg/fmt_cache_3.f90: New.

34556

+ * gfortran.dg/fmt_cache_3.f90: New.

34557

34558

2013-04-02 Richard Biener <rguenther@suse.de>

34559

34560

@@ -1636,7 +3429,7 @@

34561

2013-02-20 Jan Hubicka <jh@suse.cz>

34562

34563

PR tree-optimization/56265

34564

- * testsuite/g++.dg/ipa/devirt-11.C: New testcase.

34565

+ * g++.dg/ipa/devirt-11.C: New testcase.

34566

34567

2013-02-20 Richard Biener <rguenther@suse.de>

34568

34569

@@ -1823,11 +3616,9 @@

34570

34571

Avoid instrumenting duplicated memory access in the same basic block

34572

* c-c++-common/asan/no-redundant-instrumentation-1.c: New test.

34573

- * testsuite/c-c++-common/asan/no-redundant-instrumentation-2.c:

34574

- Likewise.

34575

- * testsuite/c-c++-common/asan/no-redundant-instrumentation-3.c:

34576

- Likewise.

34577

- * testsuite/c-c++-common/asan/inc.c: Likewise.

34578

+ * c-c++-common/asan/no-redundant-instrumentation-2.c: Likewise.

34579

+ * c-c++-common/asan/no-redundant-instrumentation-3.c: Likewise.

34580

+ * c-c++-common/asan/inc.c: Likewise.

34581

34582

2013-02-12 Vladimir Makarov <vmakarov@redhat.com>

34583

34584

Index: gcc/testsuite/gfortran.fortran-torture/compile/pr57517.f90

34585

===================================================================

34586

--- a/src/gcc/testsuite/gfortran.fortran-torture/compile/pr57517.f90 (.../tags/gcc_4_8_2_release)

34587

+++ b/src/gcc/testsuite/gfortran.fortran-torture/compile/pr57517.f90 (.../branches/gcc-4_8-branch)

34588

@@ -0,0 +1,13 @@

34589

+SUBROUTINE cal_helicity (uh, ph, phb, wavg, ims, ime, its, ite)

34590

+ INTEGER, INTENT( IN ) :: ims, ime, its, ite

34591

+ REAL, DIMENSION( ims:ime), INTENT( IN ) :: ph, phb, wavg

34592

+ REAL, DIMENSION( ims:ime), INTENT( INOUT ) :: uh

34593

+ INTEGER :: i

34594

+ REAL :: zu

34595

+ DO i = its, ite

34596

+ zu = (ph(i ) + phb(i)) + (ph(i-1) + phb(i-1))

34597

+ IF (wavg(i) .GT. 0) THEN

34598

+ uh(i) = uh(i) + zu

34599

+ ENDIF

34600

+ END DO

34601

+END SUBROUTINE cal_helicity

34602

Index: gcc/testsuite/g++.dg/ext/attribute-test-2.C

34603

===================================================================

34604

--- a/src/gcc/testsuite/g++.dg/ext/attribute-test-2.C (.../tags/gcc_4_8_2_release)

34605

+++ b/src/gcc/testsuite/g++.dg/ext/attribute-test-2.C (.../branches/gcc-4_8-branch)

34606

@@ -50,3 +50,4 @@

34607

34608

/* Ignore a warning that is irrelevant to the purpose of this test. */

34609

/* { dg-prune-output ".*GCC vector returned by reference.*" } */

34610

+/* { dg-prune-output "changes the ABI" } */

34611

Index: gcc/testsuite/g++.dg/ext/attribute-test-3.C

34612

===================================================================

34613

--- a/src/gcc/testsuite/g++.dg/ext/attribute-test-3.C (.../tags/gcc_4_8_2_release)

34614

+++ b/src/gcc/testsuite/g++.dg/ext/attribute-test-3.C (.../branches/gcc-4_8-branch)

34615

@@ -52,3 +52,4 @@

34616

34617

/* Ignore a warning that is irrelevant to the purpose of this test. */

34618

/* { dg-prune-output ".*GCC vector returned by reference.*" } */

34619

+/* { dg-prune-output "changes the ABI" } */

34620

Index: gcc/testsuite/g++.dg/ext/traits1.C

34621

===================================================================

34622

--- a/src/gcc/testsuite/g++.dg/ext/traits1.C (.../tags/gcc_4_8_2_release)

34623

+++ b/src/gcc/testsuite/g++.dg/ext/traits1.C (.../branches/gcc-4_8-branch)

34624

@@ -0,0 +1,4 @@

34625

+// PR c++/58504

34626

+

34627

+template<bool = __has_nothrow_assign(void)> struct A {};

34628

+A<> a;

34629

Index: gcc/testsuite/g++.dg/ext/attribute-test-4.C

34630

===================================================================

34631

--- a/src/gcc/testsuite/g++.dg/ext/attribute-test-4.C (.../tags/gcc_4_8_2_release)

34632

+++ b/src/gcc/testsuite/g++.dg/ext/attribute-test-4.C (.../branches/gcc-4_8-branch)

34633

@@ -49,3 +49,4 @@

34634

34635

/* Ignore a warning that is irrelevant to the purpose of this test. */

34636

/* { dg-prune-output ".*GCC vector returned by reference.*" } */

34637

+/* { dg-prune-output "changes the ABI" } */

34638

Index: gcc/testsuite/g++.dg/ext/stmtexpr15.C

34639

===================================================================

34640

--- a/src/gcc/testsuite/g++.dg/ext/stmtexpr15.C (.../tags/gcc_4_8_2_release)

34641

+++ b/src/gcc/testsuite/g++.dg/ext/stmtexpr15.C (.../branches/gcc-4_8-branch)

34642

@@ -0,0 +1,7 @@

34643

+// PR c++/59097

34644

+// { dg-options "" }

34645

+

34646

+void foo()

34647

+{

34648

+ int x[({ return; })]; // { dg-error "non-integral" }

34649

+}

34650

Index: gcc/testsuite/g++.dg/ext/vector25.C

34651

===================================================================

34652

--- a/src/gcc/testsuite/g++.dg/ext/vector25.C (.../tags/gcc_4_8_2_release)

34653

+++ b/src/gcc/testsuite/g++.dg/ext/vector25.C (.../branches/gcc-4_8-branch)

34654

@@ -0,0 +1,6 @@

34655

+volatile int i __attribute__((vector_size(8)));

34656

+

34657

+void foo()

34658

+{

34659

+ i += i;

34660

+}

34661

Index: gcc/testsuite/g++.dg/ext/builtin-bswap1.C

34662

===================================================================

34663

--- a/src/gcc/testsuite/g++.dg/ext/builtin-bswap1.C (.../tags/gcc_4_8_2_release)

34664

+++ b/src/gcc/testsuite/g++.dg/ext/builtin-bswap1.C (.../branches/gcc-4_8-branch)

34665

@@ -0,0 +1,22 @@

34666

+// PR c/37743

34667

+// { dg-do compile }

34668

+

34669

+#if defined(__UINT32_TYPE__) && defined(__INT32_TYPE__)

34670

+

34671

+void foo (__UINT32_TYPE__);

34672

+void foo (__INT32_TYPE__);

34673

+

34674

+void

34675

+bar (__UINT32_TYPE__ x)

34676

+{

34677

+ foo (__builtin_bswap32 (x));

34678

+}

34679

+

34680

+#else

34681

+

34682

+void

34683

+bar ()

34684

+{

34685

+}

34686

+

34687

+#endif

34688

Index: gcc/testsuite/g++.dg/ext/attrib48.C

34689

===================================================================

34690

--- a/src/gcc/testsuite/g++.dg/ext/attrib48.C (.../tags/gcc_4_8_2_release)

34691

+++ b/src/gcc/testsuite/g++.dg/ext/attrib48.C (.../branches/gcc-4_8-branch)

34692

@@ -0,0 +1,6 @@

34693

+// PR c++/54652

34694

+

34695

+typedef unsigned L __attribute__ ((aligned));

34696

+typedef unsigned L __attribute__ ((aligned));

34697

+

34698

+L l;

34699

Index: gcc/testsuite/g++.dg/ext/vector27.C

34700

===================================================================

34701

--- a/src/gcc/testsuite/g++.dg/ext/vector27.C (.../tags/gcc_4_8_2_release)

34702

+++ b/src/gcc/testsuite/g++.dg/ext/vector27.C (.../branches/gcc-4_8-branch)

34703

@@ -0,0 +1,7 @@

34704

+// PR c++/58845

34705

+

34706

+void foo()

34707

+{

34708

+ int v __attribute__((vector_size(8)));

34709

+ v = v || v; // { dg-bogus "" "" { xfail *-*-* } }

34710

+}

34711

Index: gcc/testsuite/g++.dg/ext/timevar2.C

34712

===================================================================

34713

--- a/src/gcc/testsuite/g++.dg/ext/timevar2.C (.../tags/gcc_4_8_2_release)

34714

+++ b/src/gcc/testsuite/g++.dg/ext/timevar2.C (.../branches/gcc-4_8-branch)

34715

@@ -0,0 +1,14 @@

34716

+// PR c++/57524

34717

+// { dg-options "-ftime-report" }

34718

+// { dg-prune-output "wall" }

34719

+// { dg-prune-output "times" }

34720

+// { dg-prune-output "TOTAL" }

34721

+// { dg-prune-output "checks" }

34722

+

34723

+namespace detail {

34724

+namespace indirect_traits {}

34725

+using namespace indirect_traits;

34726

+void fn1() {

34727

+using namespace detail;

34728

+}

34729

+}

34730

Index: gcc/testsuite/g++.dg/ext/attribute-test-1.C

34731

===================================================================

34732

--- a/src/gcc/testsuite/g++.dg/ext/attribute-test-1.C (.../tags/gcc_4_8_2_release)

34733

+++ b/src/gcc/testsuite/g++.dg/ext/attribute-test-1.C (.../branches/gcc-4_8-branch)

34734

@@ -36,3 +36,4 @@

34735

34736

/* Ignore a warning that is irrelevant to the purpose of this test. */

34737

/* { dg-prune-output ".*GCC vector returned by reference.*" } */

34738

+/* { dg-prune-output "changes the ABI" } */

34739

Index: gcc/testsuite/g++.dg/vect/pr60836.cc

34740

===================================================================

34741

--- a/src/gcc/testsuite/g++.dg/vect/pr60836.cc (.../tags/gcc_4_8_2_release)

34742

+++ b/src/gcc/testsuite/g++.dg/vect/pr60836.cc (.../branches/gcc-4_8-branch)

34743

@@ -0,0 +1,39 @@

34744

+// { dg-do compile }

34745

+

34746

+int a, b;

34747

+typedef double (*NormFunc) (const int &);

34748

+int &

34749

+max (int &p1, int &p2)

34750

+{

34751

+ if (p1 < p2)

34752

+ return p2;

34753

+ return p1;

34754

+}

34755

+

34756

+struct A

34757

+{

34758

+ int operator () (int p1, int p2)

34759

+ {

34760

+ return max (p1, p2);

34761

+ }

34762

+};

34763

+template < class, class > double

34764

+norm_ (const int &)

34765

+{

34766

+ char c, d;

34767

+ A e;

34768

+ for (; a; a++)

34769

+ {

34770

+ b = e (b, d);

34771

+ b = e (b, c);

34772

+ }

34773

+}

34774

+

34775

+void

34776

+norm ()

34777

+{

34778

+ static NormFunc f = norm_ < int, A >;

34779

+ f = 0;

34780

+}

34781

+

34782

+// { dg-final { cleanup-tree-dump "vect" } }

34783

Index: gcc/testsuite/g++.dg/vect/pr60729.cc

34784

===================================================================

34785

--- a/src/gcc/testsuite/g++.dg/vect/pr60729.cc (.../tags/gcc_4_8_2_release)

34786

+++ b/src/gcc/testsuite/g++.dg/vect/pr60729.cc (.../branches/gcc-4_8-branch)

34787

@@ -0,0 +1,10 @@

34788

+// { dg-do compile }

34789

+// { dg-additional-options "-ftrapv" }

34790

+

34791

+void doSomething(int dim, double *Y, double *A)

34792

+{

34793

+ for (int k=0; k<dim; k++)

34794

+ Y[k] += __builtin_fabs (A[k]);

34795

+}

34796

+

34797

+// { dg-final { cleanup-tree-dump "vect" } }

34798

Index: gcc/testsuite/g++.dg/opt/pr59647.C

34799

===================================================================

34800

--- a/src/gcc/testsuite/g++.dg/opt/pr59647.C (.../tags/gcc_4_8_2_release)

34801

+++ b/src/gcc/testsuite/g++.dg/opt/pr59647.C (.../branches/gcc-4_8-branch)

34802

@@ -0,0 +1,32 @@

34803

+// PR rtl-optimization/59647

34804

+// { dg-do compile }

34805

+// { dg-options "-O2 -fno-tree-vrp" }

34806

+// { dg-additional-options "-msse2 -mfpmath=sse" { target { { i?86-*-* x86_64-*-* } && ia32 } } }

34807

+

34808

+void f1 (int);

34809

+void f2 ();

34810

+double f3 (int);

34811

+

34812

+struct A

34813

+{

34814

+ int f4 () const

34815

+ {

34816

+ if (a == 0)

34817

+ return 1;

34818

+ return 0;

34819

+ }

34820

+ unsigned f5 ()

34821

+ {

34822

+ if (!f4 ())

34823

+ f2 ();

34824

+ return a;

34825

+ }

34826

+ int a;

34827

+};

34828

+

34829

+void

34830

+f6 (A *x)

34831

+{

34832

+ unsigned b = x->f5 ();

34833

+ f1 (b - 1 - f3 (x->f5 () - 1U));

34834

+}

34835

Index: gcc/testsuite/g++.dg/opt/pr59470.C

34836

===================================================================

34837

--- a/src/gcc/testsuite/g++.dg/opt/pr59470.C (.../tags/gcc_4_8_2_release)

34838

+++ b/src/gcc/testsuite/g++.dg/opt/pr59470.C (.../branches/gcc-4_8-branch)

34839

@@ -0,0 +1,188 @@

34840

+// PR middle-end/59470

34841

+// { dg-do run }

34842

+// { dg-options "-O2 -fstack-protector" }

34843

+// { dg-additional-options "-fPIC" { target fpic } }

34844

+// { dg-require-effective-target fstack_protector }

34845

+

34846

+struct A

34847

+{

34848

+ int a1;

34849

+ A () throw () : a1 (0) {}

34850

+};

34851

+

34852

+struct B

34853

+{

34854

+ unsigned int b1 () throw ();

34855

+};

34856

+

34857

+__attribute__((noinline, noclone)) unsigned int

34858

+B::b1 () throw ()

34859

+{

34860

+ asm volatile ("" : : : "memory");

34861

+ return 0;

34862

+}

34863

+

34864

+struct C

34865

+{

34866

+ const A **c1;

34867

+ void c2 (const A *, unsigned int);

34868

+};

34869

+

34870

+__attribute__((noinline, noclone)) void

34871

+C::c2 (const A *, unsigned int)

34872

+{

34873

+ asm volatile ("" : : : "memory");

34874

+}

34875

+

34876

+struct D

34877

+{

34878

+ C *d1;

34879

+};

34880

+

34881

+struct E

34882

+{

34883

+ int e1;

34884

+ int e2;

34885

+ D e3;

34886

+};

34887

+

34888

+struct F

34889

+{

34890

+ virtual int f1 (const char * s, int n);

34891

+};

34892

+

34893

+struct G

34894

+{

34895

+ F *g1;

34896

+ bool g2;

34897

+ G & g3 (const char * ws, int len)

34898

+ {

34899

+ if (__builtin_expect (!g2, true)

34900

+ && __builtin_expect (this->g1->f1 (ws, len) != len, false))

34901

+ g2 = true;

34902

+ return *this;

34903

+ }

34904

+};

34905

+

34906

+struct H : public A

34907

+{

34908

+ const char *h1;

34909

+ unsigned int h2;

34910

+ bool h3;

34911

+ const char *h4;

34912

+ char h5;

34913

+ char h6;

34914

+ char h7[31];

34915

+ bool h8;

34916

+ H () : h1 (0), h2 (0), h4 (0), h5 (0), h6 (0), h8 (false) {}

34917

+ void h9 (const D &) __attribute__((noinline, noclone));

34918

+};

34919

+

34920

+void

34921

+H::h9 (const D &)

34922

+{

34923

+ h3 = true;

34924

+ __builtin_memset (h7, 0, sizeof (h7));

34925

+ asm volatile ("" : : : "memory");

34926

+};

34927

+

34928

+B b;

34929

+

34930

+inline const H *

34931

+foo (const D &x)

34932

+{

34933

+ const unsigned int i = b.b1 ();

34934

+ const A **j = x.d1->c1;

34935

+ if (!j[i])

34936

+ {

34937

+ H *k = 0;

34938

+ try

34939

+ {

34940

+ k = new H;

34941

+ k->h9 (x);

34942

+ }

34943

+ catch (...)

34944

+ {

34945

+ }

34946

+ x.d1->c2 (k, i);

34947

+ }

34948

+ return static_cast <const H *>(j[i]);

34949

+}

34950

+

34951

+__attribute__((noinline, noclone)) int

34952

+bar (char *x, unsigned long v, const char *y, int z, bool w)

34953

+{

34954

+ asm volatile ("" : : "r" (x), "r" (v), "r" (y) : "memory");

34955

+ asm volatile ("" : : "r" (z), "r" (w) : "memory");

34956

+ return 8;

34957

+}

34958

+

34959

+__attribute__((noinline, noclone)) void

34960

+baz (void *z, const char *g, unsigned int h, char s, E &e, char *n, char *c, int &l)

34961

+{

34962

+ asm volatile ("" : : "r" (z), "r" (g), "r" (h) : "memory");

34963

+ asm volatile ("" : : "r" (s), "r" (&e), "r" (n) : "memory");

34964

+ asm volatile ("" : : "r" (c), "r" (&l) : "memory");

34965

+ if (n == c)

34966

+ __builtin_abort ();

34967

+ int i = 0;

34968

+ asm ("" : "+r" (i));

34969

+ if (i == 0)

34970

+ __builtin_exit (0);

34971

+}

34972

+

34973

+__attribute__((noinline, noclone)) G

34974

+test (void *z, G s, E &x, char, long v)

34975

+{

34976

+ const D &d = x.e3;

34977

+ const H *h = foo (d);

34978

+ const char *q = h->h7;

34979

+ const int f = x.e2;

34980

+ const int i = 5 * sizeof (long);

34981

+ char *c = static_cast <char *>(__builtin_alloca (i));

34982

+ const int b = f & 74;

34983

+ const bool e = (b != 64 && b != 8);

34984

+ const unsigned long u = ((v > 0 || !e) ? (unsigned long) v : -(unsigned long) v);

34985

+ int l = bar (c + i, u, q, f, e);

34986

+ c += i - l;

34987

+ if (h->h3)

34988

+ {

34989

+ char *c2 = static_cast <char *>(__builtin_alloca ((l + 1) * 2));

34990

+ baz (z, h->h1, h->h2, h->h6, x, c2 + 2, c, l);

34991

+ c = c2 + 2;

34992

+ }

34993

+ if (__builtin_expect (e, true))

34994

+ {

34995

+ }

34996

+ else if ((f & 4096) && v)

34997

+ {

34998

+ {

34999

+ const bool m = f & 176;

35000

+ *--c = q[m];

35001

+ *--c = q[1];

35002

+ }

35003

+ }

35004

+ const int w = x.e1;

35005

+ if (w > l)

35006

+ {

35007

+ char * c3 = static_cast <char *>(__builtin_alloca (w));

35008

+ c = c3;

35009

+ }

35010

+ return s.g3 (c, l);

35011

+}

35012

+

35013

+int

35014

+main ()

35015

+{

35016

+ H h;

35017

+ const A *j[1];

35018

+ C c;

35019

+ G g;

35020

+ E e;

35021

+ h.h9 (e.e3);

35022

+ j[0] = &h;

35023

+ c.c1 = j;

35024

+ e.e3.d1 = &c;

35025

+ test (0, g, e, 0, 0);

35026

+ __builtin_abort ();

35027

+}

35028

Index: gcc/testsuite/g++.dg/opt/pr58864.C

35029

===================================================================

35030

--- a/src/gcc/testsuite/g++.dg/opt/pr58864.C (.../tags/gcc_4_8_2_release)

35031

+++ b/src/gcc/testsuite/g++.dg/opt/pr58864.C (.../branches/gcc-4_8-branch)

35032

@@ -0,0 +1,21 @@

35033

+// PR target/58864

35034

+// { dg-do compile }

35035

+// { dg-options "-Os" }

35036

+// { dg-additional-options "-march=i686" { target { { i?86-*-* x86_64-*-* } && ia32 } } }

35037

+

35038

+struct A { A (); ~A (); };

35039

+struct B { B (); };

35040

+

35041

+float d, e;

35042

+

35043

+void

35044

+foo ()

35045

+{

35046

+ A a;

35047

+ float c = d;

35048

+ while (1)

35049

+ {

35050

+ B b;

35051

+ e = c ? -c : 0;

35052

+ }

35053

+}

35054

Index: gcc/testsuite/g++.dg/tree-prof/pr59255.C

35055

===================================================================

35056

--- a/src/gcc/testsuite/g++.dg/tree-prof/pr59255.C (.../tags/gcc_4_8_2_release)

35057

+++ b/src/gcc/testsuite/g++.dg/tree-prof/pr59255.C (.../branches/gcc-4_8-branch)

35058

@@ -0,0 +1,29 @@

35059

+// PR c++/59255

35060

+// { dg-options "-O2 -std=c++11" }

35061

+

35062

+struct S

35063

+{

35064

+ __attribute__((noinline, noclone)) ~S () noexcept (true)

35065

+ {

35066

+ if (fn)

35067

+ fn (1);

35068

+ }

35069

+ void (*fn) (int);

35070

+};

35071

+

35072

+__attribute__((noinline, noclone)) void

35073

+foo (int x)

35074

+{

35075

+ if (x != 1)

35076

+ throw 1;

35077

+}

35078

+

35079

+int

35080

+main ()

35081

+{

35082

+ for (int i = 0; i < 100; i++)

35083

+ {

35084

+ S s;

35085

+ s.fn = foo;

35086

+ }

35087

+}

35088

Index: gcc/testsuite/g++.dg/gomp/for-20.C

35089

===================================================================

35090

--- a/src/gcc/testsuite/g++.dg/gomp/for-20.C (.../tags/gcc_4_8_2_release)

35091

+++ b/src/gcc/testsuite/g++.dg/gomp/for-20.C (.../branches/gcc-4_8-branch)

35092

@@ -0,0 +1,16 @@

35093

+// PR c++/60146

35094

+// { dg-do compile }

35095

+// { dg-options -fopenmp }

35096

+

35097

+int foo() { return 0; }

35098

+

35099

+template<typename T> void bar()

35100

+{

35101

+#pragma omp parallel for

35102

+ for (T i = foo(); i < 8; ++i) {}

35103

+}

35104

+

35105

+void baz()

35106

+{

35107

+ bar<int>();

35108

+}

35109

Index: gcc/testsuite/g++.dg/gomp/pr59297.C

35110

===================================================================

35111

--- a/src/gcc/testsuite/g++.dg/gomp/pr59297.C (.../tags/gcc_4_8_2_release)

35112

+++ b/src/gcc/testsuite/g++.dg/gomp/pr59297.C (.../branches/gcc-4_8-branch)

35113

@@ -0,0 +1,25 @@

35114

+// PR c++/59297

35115

+// { dg-do compile }

35116

+// { dg-options "-fopenmp" }

35117

+

35118

+template <typename T>

35119

+struct A

35120

+{

35121

+ ~A ();

35122

+ const T &operator[] (int) const;

35123

+};

35124

+

35125

+struct B

35126

+{

35127

+ int &operator () (A <int>);

35128

+};

35129

+

35130

+void

35131

+foo (B &x, int &z)

35132

+{

35133

+ A<A<int> > y;

35134

+ #pragma omp atomic

35135

+ x (y[0]) += 1;

35136

+ #pragma omp atomic

35137

+ z += x(y[1]);

35138

+}

35139

Index: gcc/testsuite/g++.dg/diagnostic/pr59838.C

35140

===================================================================

35141

--- a/src/gcc/testsuite/g++.dg/diagnostic/pr59838.C (.../tags/gcc_4_8_2_release)

35142

+++ b/src/gcc/testsuite/g++.dg/diagnostic/pr59838.C (.../branches/gcc-4_8-branch)

35143

@@ -0,0 +1,4 @@

35144

+// PR c++/59838

35145

+// { dg-do compile }

35146

+

35147

+enum E { a, b = (E) a }; // { dg-error "conversion to incomplete type" }

35148

Index: gcc/testsuite/g++.dg/diagnostic/pedantic.C

35149

===================================================================

35150

--- a/src/gcc/testsuite/g++.dg/diagnostic/pedantic.C (.../tags/gcc_4_8_2_release)

35151

+++ b/src/gcc/testsuite/g++.dg/diagnostic/pedantic.C (.../branches/gcc-4_8-branch)

35152

@@ -0,0 +1,11 @@

35153

+// { dg-do compile }

35154

+// { dg-options "-pedantic" }

35155

+typedef void F(void);

35156

+

35157

+void foo()

35158

+{

35159

+ void* p = 0;

35160

+ F* f1 = reinterpret_cast<F*>(p); // { dg-warning "ISO" }

35161

+#pragma GCC diagnostic ignored "-pedantic"

35162

+ F* f2 = reinterpret_cast<F*>(p);

35163

+}

35164

Index: gcc/testsuite/g++.dg/diagnostic/pr58979.C

35165

===================================================================

35166

--- a/src/gcc/testsuite/g++.dg/diagnostic/pr58979.C (.../tags/gcc_4_8_2_release)

35167

+++ b/src/gcc/testsuite/g++.dg/diagnostic/pr58979.C (.../branches/gcc-4_8-branch)

35168

@@ -0,0 +1,4 @@

35169

+// PR c++/58979

35170

+// { dg-do compile }

35171

+

35172

+int i = 0->*0; // { dg-error "invalid type argument of" }

35173

Index: gcc/testsuite/g++.dg/conversion/simd1.C

35174

===================================================================

35175

--- a/src/gcc/testsuite/g++.dg/conversion/simd1.C (.../tags/gcc_4_8_2_release)

35176

+++ b/src/gcc/testsuite/g++.dg/conversion/simd1.C (.../branches/gcc-4_8-branch)

35177

@@ -1,4 +1,5 @@

35178

/* { dg-do compile } */

35179

+/* { dg-options "-msse2" { target { i?86-*-* x86_64-*-* } } } */

35180

35181

/* Test overload resolution of vector types.

35182

From Janis Johnson and Paolo Bonzini, based on PR/16882 */

35183

@@ -17,7 +18,7 @@

35184

void foo ()

35185

{

35186

vss = vld(i, vscp); /* { dg-error "no matching function for call" } */

35187

- // { dg-message "candidate" "candidate note" { target *-*-* } 19 }

35188

+ // { dg-message "candidate" "candidate note" { target *-*-* } 20 }

35189

vss = vld(i, vssp);

35190

vss = vld(i, cvssp);

35191

}

35192

Index: gcc/testsuite/g++.dg/tls/thread_local8.C

35193

===================================================================

35194

--- a/src/gcc/testsuite/g++.dg/tls/thread_local8.C (.../tags/gcc_4_8_2_release)

35195

+++ b/src/gcc/testsuite/g++.dg/tls/thread_local8.C (.../branches/gcc-4_8-branch)

35196

@@ -0,0 +1,12 @@

35197

+// PR c++/55800

35198

+// { dg-options "-std=c++11" }

35199

+// { dg-require-alias "" }

35200

+// { dg-require-effective-target tls }

35201

+// { dg-final { scan-assembler "_ZTH12foo_instance" { target tls_native } } }

35202

+

35203

+struct foo

35204

+{

35205

+ foo();

35206

+};

35207

+

35208

+thread_local foo foo_instance;

35209

Index: gcc/testsuite/g++.dg/tls/thread_local-ice2.C

35210

===================================================================

35211

--- a/src/gcc/testsuite/g++.dg/tls/thread_local-ice2.C (.../tags/gcc_4_8_2_release)

35212

+++ b/src/gcc/testsuite/g++.dg/tls/thread_local-ice2.C (.../branches/gcc-4_8-branch)

35213

@@ -0,0 +1,11 @@

35214

+// PR c++/58672

35215

+// { dg-options "-std=c++11" }

35216

+// { dg-require-effective-target tls }

35217

+

35218

+struct A

35219

+{

35220

+ A(int);

35221

+ i; // { dg-error "" }

35222

+};

35223

+

35224

+thread_local A a(0);

35225

Index: gcc/testsuite/g++.dg/pr60769.C

35226

===================================================================

35227

--- a/src/gcc/testsuite/g++.dg/pr60769.C (.../tags/gcc_4_8_2_release)

35228

+++ b/src/gcc/testsuite/g++.dg/pr60769.C (.../branches/gcc-4_8-branch)

35229

@@ -0,0 +1,43 @@

35230

+/* { dg-do compile } */

35231

+/* { dg-options "-O" } */

35232

+

35233

+template <class T> void fun(T);

35234

+struct B {};

35235

+struct R {

35236

+ int *x;

35237

+ B f;

35238

+};

35239

+R v(int &, R);

35240

+void rfun(R &);

35241

+struct A {

35242

+ void m_fn2(R p1) {

35243

+ R a = p1;

35244

+ rfun(p1);

35245

+ fun(this);

35246

+ fun(a);

35247

+ }

35248

+};

35249

+struct J {

35250

+ A ep;

35251

+ A ap;

35252

+ int c2a;

35253

+ void m_fn1(R &p2) {

35254

+ R d, e, b;

35255

+ v(c2a, p2);

35256

+ e = v(c2a, b);

35257

+ ap.m_fn2(e);

35258

+ v(c2a, p2);

35259

+ d = v(c2a, b);

35260

+ ep.m_fn2(d);

35261

+ }

35262

+};

35263

+struct N {

35264

+ int &p_;

35265

+ J cfo;

35266

+};

35267

+void fn3(N&n) {

35268

+ R h;

35269

+ n.cfo.m_fn1(h);

35270

+}

35271

+extern N &c;

35272

+void fn1() { fn3(c); }

35273

Index: gcc/testsuite/g++.dg/tm/pr60004.C

35274

===================================================================

35275

--- a/src/gcc/testsuite/g++.dg/tm/pr60004.C (.../tags/gcc_4_8_2_release)

35276

+++ b/src/gcc/testsuite/g++.dg/tm/pr60004.C (.../branches/gcc-4_8-branch)

35277

@@ -0,0 +1,10 @@

35278

+// { dg-do compile }

35279

+// { dg-options "-fgnu-tm" }

35280

+

35281

+int a;

35282

+int f() {

35283

+ __transaction_atomic {

35284

+ if (a == 5)

35285

+ return 1;

35286

+ }

35287

+}

35288

Index: gcc/testsuite/g++.dg/tm/noexcept-6.C

35289

===================================================================

35290

--- a/src/gcc/testsuite/g++.dg/tm/noexcept-6.C (.../tags/gcc_4_8_2_release)

35291

+++ b/src/gcc/testsuite/g++.dg/tm/noexcept-6.C (.../branches/gcc-4_8-branch)

35292

@@ -0,0 +1,23 @@

35293

+// { dg-do compile }

35294

+// { dg-options "-fno-exceptions -fgnu-tm -O -std=c++0x -fdump-tree-tmlower" }

35295

+

35296

+struct TrueFalse

35297

+{

35298

+ static constexpr bool v() { return true; }

35299

+};

35300

+

35301

+int global;

35302

+

35303

+template<typename T> int foo()

35304

+{

35305

+ return __transaction_atomic noexcept(T::v()) (global + 1);

35306

+}

35307

+

35308

+int f1()

35309

+{

35310

+ return foo<TrueFalse>();

35311

+}

35312

+

35313

+/* { dg-final { scan-tree-dump-times "eh_must_not_throw" 0 "tmlower" } } */

35314

+/* { dg-final { scan-tree-dump-times "__transaction_atomic" 1 "tmlower" } } */

35315

+/* { dg-final { cleanup-tree-dump "tmlower" } } */

35316

Index: gcc/testsuite/g++.dg/pr59695.C

35317

===================================================================

35318

--- a/src/gcc/testsuite/g++.dg/pr59695.C (.../tags/gcc_4_8_2_release)

35319

+++ b/src/gcc/testsuite/g++.dg/pr59695.C (.../branches/gcc-4_8-branch)

35320

@@ -0,0 +1,125 @@

35321

+

35322

+/* PR target/59695 */

35323

+/* { dg-do run } */

35324

+/* { dg-options "-O0" } */

35325

+

35326

+#define DEFINE_VIRTUALS_FNS(i) virtual void xxx##i () {} \

35327

+ virtual void foo1_##i () {}\

35328

+ virtual void foo2_##i () {}\

35329

+ virtual void foo3_##i () {}\

35330

+ virtual void foo4_##i () {}\

35331

+ virtual void foo5_##i () {}\

35332

+ virtual void foo6_##i () {}\

35333

+ virtual void foo7_##i () {}\

35334

+ virtual void foo8_##i () {}\

35335

+ virtual void foo9_##i () {}\

35336

+ virtual void foo10_##i () {}\

35337

+ virtual void foo11_##i () {}\

35338

+ virtual void foo12_##i () {}\

35339

+ virtual void foo13_##i () {}\

35340

+ virtual void foo14_##i () {}\

35341

+ virtual void foo15_##i () {}\

35342

+ virtual void foo16_##i () {}\

35343

+ virtual void foo17_##i () {}\

35344

+ virtual void foo18_##i () {}\

35345

+ virtual void foo19_##i () {}\

35346

+ virtual void foo20_##i () {}\

35347

+ virtual void foo21_##i () {}\

35348

+ virtual void foo22_##i () {}\

35349

+

35350

+class base_class_2

35351

+{

35352

+

35353

+public:

35354

+ /* Define lots of virtual functions */

35355

+ DEFINE_VIRTUALS_FNS (1)

35356

+ DEFINE_VIRTUALS_FNS (2)

35357

+ DEFINE_VIRTUALS_FNS (3)

35358

+ DEFINE_VIRTUALS_FNS (4)

35359

+ DEFINE_VIRTUALS_FNS (5)

35360

+ DEFINE_VIRTUALS_FNS (6)

35361

+ DEFINE_VIRTUALS_FNS (7)

35362

+ DEFINE_VIRTUALS_FNS (8)

35363

+ DEFINE_VIRTUALS_FNS (9)

35364

+ DEFINE_VIRTUALS_FNS (10)

35365

+ DEFINE_VIRTUALS_FNS (11)

35366

+ DEFINE_VIRTUALS_FNS (12)

35367

+ DEFINE_VIRTUALS_FNS (13)

35368

+ DEFINE_VIRTUALS_FNS (14)

35369

+ DEFINE_VIRTUALS_FNS (15)

35370

+ DEFINE_VIRTUALS_FNS (16)

35371

+ DEFINE_VIRTUALS_FNS (17)

35372

+ DEFINE_VIRTUALS_FNS (18)

35373

+ DEFINE_VIRTUALS_FNS (19)

35374

+ DEFINE_VIRTUALS_FNS (20)

35375

+

35376

+ base_class_2();

35377

+ virtual ~base_class_2 ();

35378

+};

35379

+

35380

+base_class_2::base_class_2()

35381

+{

35382

+}

35383

+

35384

+base_class_2::~base_class_2 ()

35385

+{

35386

+}

35387

+

35388

+class base_class_1

35389

+{

35390

+public:

35391

+ virtual ~base_class_1();

35392

+ base_class_1();

35393

+};

35394

+

35395

+base_class_1::base_class_1()

35396

+{

35397

+}

35398

+

35399

+base_class_1::~base_class_1()

35400

+{

35401

+}

35402

+

35403

+class base_Impl_class :

35404

+ virtual public base_class_2, public base_class_1

35405

+{

35406

+public:

35407

+ base_Impl_class ();

35408

+ virtual ~base_Impl_class ();

35409

+};

35410

+

35411

+base_Impl_class::base_Impl_class ()

35412

+{

35413

+}

35414

+

35415

+base_Impl_class::~base_Impl_class ()

35416

+{

35417

+}

35418

+

35419

+

35420

+class test_cls : public base_Impl_class

35421

+{

35422

+public:

35423

+ test_cls();

35424

+ virtual ~test_cls();

35425

+};

35426

+

35427

+test_cls::test_cls()

35428

+{

35429

+}

35430

+

35431

+test_cls::~test_cls()

35432

+{

35433

+}

35434

+

35435

+int main()

35436

+{

35437

+ test_cls *test = new test_cls;

35438

+ base_class_2 *p1 = test;

35439

+

35440

+ /* PR59695 destructor thunk offsets are not setup

35441

+ correctly resulting in crash. */

35442

+ delete p1;

35443

+ return 0;

35444

+}

35445

+

35446

Index: gcc/testsuite/g++.dg/cpp0x/initlist79.C

35447

===================================================================

35448

--- a/src/gcc/testsuite/g++.dg/cpp0x/initlist79.C (.../tags/gcc_4_8_2_release)

35449

+++ b/src/gcc/testsuite/g++.dg/cpp0x/initlist79.C (.../branches/gcc-4_8-branch)

35450

@@ -0,0 +1,8 @@

35451

+// PR c++/59646

35452

+// { dg-require-effective-target c++11 }

35453

+

35454

+#include <initializer_list>

35455

+

35456

+struct A {};

35457

+

35458

+std::initializer_list<volatile A> x = {{}};

35459

Index: gcc/testsuite/g++.dg/cpp0x/enum_base2.C

35460

===================================================================

35461

--- a/src/gcc/testsuite/g++.dg/cpp0x/enum_base2.C (.../tags/gcc_4_8_2_release)

35462

+++ b/src/gcc/testsuite/g++.dg/cpp0x/enum_base2.C (.../branches/gcc-4_8-branch)

35463

@@ -0,0 +1,9 @@

35464

+// PR c++/60187

35465

+// { dg-require-effective-target c++11 }

35466

+

35467

+template<typename... T> struct A

35468

+{

35469

+ enum E : T {}; // { dg-error "parameter pack" }

35470

+};

35471

+

35472

+A<int> a;

35473

Index: gcc/testsuite/g++.dg/cpp0x/lambda/lambda-nsdmi5.C

35474

===================================================================

35475

--- a/src/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-nsdmi5.C (.../tags/gcc_4_8_2_release)

35476

+++ b/src/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-nsdmi5.C (.../branches/gcc-4_8-branch)

35477

@@ -0,0 +1,7 @@

35478

+// PR c++/58596

35479

+// { dg-do compile { target c++11 } }

35480

+

35481

+struct A

35482

+{

35483

+ int i = [] { return decltype(i)(); }();

35484

+};

35485

Index: gcc/testsuite/g++.dg/cpp0x/variadic149.C

35486

===================================================================

35487

--- a/src/gcc/testsuite/g++.dg/cpp0x/variadic149.C (.../tags/gcc_4_8_2_release)

35488

+++ b/src/gcc/testsuite/g++.dg/cpp0x/variadic149.C (.../branches/gcc-4_8-branch)

35489

@@ -0,0 +1,11 @@

35490

+// PR c++/60248

35491

+// { dg-options "-std=c++11 -g -fabi-version=2" }

35492

+

35493

+template<int...> struct A {};

35494

+

35495

+template<> struct A<0>

35496

+{

35497

+ typedef enum { e } B;

35498

+};

35499

+

35500

+A<0> a;

35501

Index: gcc/testsuite/g++.dg/cpp0x/constexpr-53094-2.C

35502

===================================================================

35503

--- a/src/gcc/testsuite/g++.dg/cpp0x/constexpr-53094-2.C (.../tags/gcc_4_8_2_release)

35504

+++ b/src/gcc/testsuite/g++.dg/cpp0x/constexpr-53094-2.C (.../branches/gcc-4_8-branch)

35505

@@ -2,6 +2,7 @@

35506

// { dg-options "-std=gnu++11" }

35507

// Ignore warning on some powerpc-ibm-aix configurations.

35508

// { dg-prune-output "non-standard ABI extension" }

35509

+// { dg-prune-output "changes the ABI" }

35510

35511

typedef float __attribute__ ((vector_size (4 * sizeof (float)))) V4;

35512

constexpr V4 build (float x, float y, float z) { return (V4){ x, y, z, 0 };}

35513

Index: gcc/testsuite/g++.dg/cpp0x/defaulted48.C

35514

===================================================================

35515

--- a/src/gcc/testsuite/g++.dg/cpp0x/defaulted48.C (.../tags/gcc_4_8_2_release)

35516

+++ b/src/gcc/testsuite/g++.dg/cpp0x/defaulted48.C (.../branches/gcc-4_8-branch)

35517

@@ -0,0 +1,17 @@

35518

+// PR c++/60108

35519

+// { dg-require-effective-target c++11 }

35520

+

35521

+template<int> struct A

35522

+{

35523

+ virtual ~A();

35524

+};

35525

+

35526

+template<typename> struct B : A<0>, A<1>

35527

+{

35528

+ ~B() = default;

35529

+};

35530

+

35531

+struct C : B<bool>

35532

+{

35533

+ C() {}

35534

+};

35535

Index: gcc/testsuite/g++.dg/cpp0x/alias-decl-41.C

35536

===================================================================

35537

--- a/src/gcc/testsuite/g++.dg/cpp0x/alias-decl-41.C (.../tags/gcc_4_8_2_release)

35538

+++ b/src/gcc/testsuite/g++.dg/cpp0x/alias-decl-41.C (.../branches/gcc-4_8-branch)

35539

@@ -0,0 +1,18 @@

35540

+// PR c++/60182

35541

+// { dg-require-effective-target c++11 }

35542

+

35543

+class B {};

35544

+template <typename> using __allocator_base = B;

35545

+template <typename> class F : __allocator_base<int> {};

35546

+class C {};

35547

+template <typename, typename = F<int> > class G : C {};

35548

+template <typename> class D;

35549

+class A {

35550

+ using Container = G<D<char>>;

35551

+ A();

35552

+ A(D<char> const &);

35553

+ Container m_elements;

35554

+};

35555

+template <template <class, class> class C, class A = F<D<int>>>

35556

+void doSomething(C<D<char>, A> &);

35557

+A::A(D<char> const &) : A() { doSomething(m_elements); }

35558

Index: gcc/testsuite/g++.dg/cpp0x/nsdmi-union3.C

35559

===================================================================

35560

--- a/src/gcc/testsuite/g++.dg/cpp0x/nsdmi-union3.C (.../tags/gcc_4_8_2_release)

35561

+++ b/src/gcc/testsuite/g++.dg/cpp0x/nsdmi-union3.C (.../branches/gcc-4_8-branch)

35562

@@ -0,0 +1,10 @@

35563

+// PR c++/58965

35564

+// { dg-require-effective-target c++11 }

35565

+

35566

+void foo()

35567

+{

35568

+ static union

35569

+ {

35570

+ int i = i;

35571

+ };

35572

+}

35573

Index: gcc/testsuite/g++.dg/cpp0x/variadic144.C

35574

===================================================================

35575

--- a/src/gcc/testsuite/g++.dg/cpp0x/variadic144.C (.../tags/gcc_4_8_2_release)

35576

+++ b/src/gcc/testsuite/g++.dg/cpp0x/variadic144.C (.../branches/gcc-4_8-branch)

35577

@@ -0,0 +1,15 @@

35578

+// PR c++/56060

35579

+// { dg-do compile { target c++11 } }

35580

+

35581

+template<typename T> struct baz { };

35582

+template<typename T> T bar();

35583

+

35584

+template<typename T, typename ... U>

35585

+baz<decltype(bar<T>()(bar<U> ...))> // { dg-error "cannot be used" }

35586

+foo();

35587

+

35588

+int main()

35589

+{

35590

+ foo<int>(); // { dg-error "no matching" }

35591

+ return 0;

35592

+}

35593

Index: gcc/testsuite/g++.dg/cpp0x/enum18.C

35594

===================================================================

35595

--- a/src/gcc/testsuite/g++.dg/cpp0x/enum18.C (.../tags/gcc_4_8_2_release)

35596

+++ b/src/gcc/testsuite/g++.dg/cpp0x/enum18.C (.../branches/gcc-4_8-branch)

35597

@@ -4,5 +4,5 @@

35598

int main(void) {

35599

enum e {};

35600

e ev;

35601

- ev.e::~e_u(); // { dg-error "e_u. has not been declared" }

35602

+ ev.e::~e_u(); // { dg-error "" }

35603

}

35604

Index: gcc/testsuite/g++.dg/cpp0x/noexcept22.C

35605

===================================================================

35606

--- a/src/gcc/testsuite/g++.dg/cpp0x/noexcept22.C (.../tags/gcc_4_8_2_release)

35607

+++ b/src/gcc/testsuite/g++.dg/cpp0x/noexcept22.C (.../branches/gcc-4_8-branch)

35608

@@ -0,0 +1,21 @@

35609

+// PR c++/60046

35610

+// { dg-require-effective-target c++11 }

35611

+

35612

+constexpr bool foo () { return noexcept (true); }

35613

+template <typename T>

35614

+struct V

35615

+{

35616

+ void bar (V &) noexcept (foo ()) {}

35617

+};

35618

+template <typename T>

35619

+struct W : public V <int>

35620

+{

35621

+ void bar (W &x) { V <int>::bar (x); }

35622

+};

35623

+

35624

+int

35625

+main ()

35626

+{

35627

+ W <int> a, b;

35628

+ a.bar (b);

35629

+}

35630

Index: gcc/testsuite/g++.dg/cpp0x/initlist76.C

35631

===================================================================

35632

--- a/src/gcc/testsuite/g++.dg/cpp0x/initlist76.C (.../tags/gcc_4_8_2_release)

35633

+++ b/src/gcc/testsuite/g++.dg/cpp0x/initlist76.C (.../branches/gcc-4_8-branch)

35634

@@ -0,0 +1,5 @@

35635

+// PR c++/58812

35636

+// { dg-require-effective-target c++11 }

35637

+

35638

+int i;

35639

+int&& j{{ i }}; // { dg-error "too many braces" }

35640

Index: gcc/testsuite/g++.dg/cpp0x/access02.C

35641

===================================================================

35642

--- a/src/gcc/testsuite/g++.dg/cpp0x/access02.C (.../tags/gcc_4_8_2_release)

35643

+++ b/src/gcc/testsuite/g++.dg/cpp0x/access02.C (.../branches/gcc-4_8-branch)

35644

@@ -0,0 +1,39 @@

35645

+// PR c++/58954

35646

+// { dg-require-effective-target c++11 }

35647

+

35648

+template<class T>

35649

+T&& declval();

35650

+

35651

+template<class T>

35652

+struct foo_argument

35653

+{

35654

+ template<class Ret, class C, class Arg>

35655

+ static Arg test(Ret (C::*)(Arg));

35656

+

35657

+ typedef decltype(test(&T::template foo<>)) type;

35658

+};

35659

+

35660

+template<class T, class>

35661

+struct dependent { typedef T type; };

35662

+

35663

+template<class T>

35664

+struct base

35665

+{

35666

+ template<class Ignore = void>

35667

+ auto foo(int i) -> decltype(declval<

35668

+ typename dependent<T&, Ignore>::type

35669

+ >().foo_impl(i));

35670

+};

35671

+

35672

+struct derived : base<derived>

35673

+{

35674

+ friend struct base<derived>;

35675

+private:

35676

+ int foo_impl(int i);

35677

+};

35678

+

35679

+int main()

35680

+{

35681

+ foo_argument<derived>::type var = 0;

35682

+ return var;

35683

+}

35684

Index: gcc/testsuite/g++.dg/cpp0x/constexpr-template6.C

35685

===================================================================

35686

--- a/src/gcc/testsuite/g++.dg/cpp0x/constexpr-template6.C (.../tags/gcc_4_8_2_release)

35687

+++ b/src/gcc/testsuite/g++.dg/cpp0x/constexpr-template6.C (.../branches/gcc-4_8-branch)

35688

@@ -0,0 +1,20 @@

35689

+// PR c++/59268

35690

+// { dg-do compile }

35691

+// { dg-options "-std=c++11" }

35692

+

35693

+template <typename>

35694

+struct A

35695

+{

35696

+ constexpr A (int) {}

35697

+ virtual void foo ()

35698

+ {

35699

+ constexpr A<void> a (0);

35700

+ }

35701

+};

35702

+

35703

+void

35704

+bar ()

35705

+{

35706

+ A<int> a (3);

35707

+ a.foo ();

35708

+}

35709

Index: gcc/testsuite/g++.dg/cpp0x/initlist78.C

35710

===================================================================

35711

--- a/src/gcc/testsuite/g++.dg/cpp0x/initlist78.C (.../tags/gcc_4_8_2_release)

35712

+++ b/src/gcc/testsuite/g++.dg/cpp0x/initlist78.C (.../branches/gcc-4_8-branch)

35713

@@ -0,0 +1,12 @@

35714

+// PR c++/58639

35715

+// { dg-require-effective-target c++11 }

35716

+

35717

+struct node {

35718

+ node &parent;

35719

+};

35720

+

35721

+struct vector {

35722

+ node n;

35723

+};

35724

+

35725

+vector v({}); // { dg-error "" }

35726

Index: gcc/testsuite/g++.dg/cpp0x/variadic148.C

35727

===================================================================

35728

--- a/src/gcc/testsuite/g++.dg/cpp0x/variadic148.C (.../tags/gcc_4_8_2_release)

35729

+++ b/src/gcc/testsuite/g++.dg/cpp0x/variadic148.C (.../branches/gcc-4_8-branch)

35730

@@ -0,0 +1,6 @@

35731

+// PR c++/59989

35732

+// { dg-require-effective-target c++11 }

35733

+

35734

+template<typename T> struct X {};

35735

+template<template<typename...> class D, typename ...U> int test(D<U...>*);

35736

+int n = test<X, int>(0); // { dg-error "no match" }

35737

Index: gcc/testsuite/g++.dg/cpp0x/nsdmi9.C

35738

===================================================================

35739

--- a/src/gcc/testsuite/g++.dg/cpp0x/nsdmi9.C (.../tags/gcc_4_8_2_release)

35740

+++ b/src/gcc/testsuite/g++.dg/cpp0x/nsdmi9.C (.../branches/gcc-4_8-branch)

35741

@@ -0,0 +1,13 @@

35742

+// PR c++/58162

35743

+// { dg-require-effective-target c++11 }

35744

+

35745

+struct A {

35746

+ A();

35747

+ A(A&&);

35748

+};

35749

+

35750

+struct B {

35751

+ A const a = A();

35752

+};

35753

+

35754

+B b;

35755

Index: gcc/testsuite/g++.dg/cpp0x/deleted3.C

35756

===================================================================

35757

--- a/src/gcc/testsuite/g++.dg/cpp0x/deleted3.C (.../tags/gcc_4_8_2_release)

35758

+++ b/src/gcc/testsuite/g++.dg/cpp0x/deleted3.C (.../branches/gcc-4_8-branch)

35759

@@ -0,0 +1,11 @@

35760

+// PR c++/60216

35761

+// { dg-require-effective-target c++11 }

35762

+

35763

+struct A

35764

+{

35765

+ template<typename T> A(T) = delete;

35766

+};

35767

+

35768

+template<> A::A<int>(int) {}

35769

+

35770

+A a(0);

35771

Index: gcc/testsuite/g++.dg/cpp0x/variadic150.C

35772

===================================================================

35773

--- a/src/gcc/testsuite/g++.dg/cpp0x/variadic150.C (.../tags/gcc_4_8_2_release)

35774

+++ b/src/gcc/testsuite/g++.dg/cpp0x/variadic150.C (.../branches/gcc-4_8-branch)

35775

@@ -0,0 +1,9 @@

35776

+// PR c++/60219

35777

+// { dg-require-effective-target c++11 }

35778

+

35779

+template<typename..., int> void foo();

35780

+

35781

+void bar()

35782

+{

35783

+ foo<0>; // { dg-error "" }

35784

+}

35785

Index: gcc/testsuite/g++.dg/cpp0x/static_assert9.C

35786

===================================================================

35787

--- a/src/gcc/testsuite/g++.dg/cpp0x/static_assert9.C (.../tags/gcc_4_8_2_release)

35788

+++ b/src/gcc/testsuite/g++.dg/cpp0x/static_assert9.C (.../branches/gcc-4_8-branch)

35789

@@ -0,0 +1,7 @@

35790

+// PR c++/58837

35791

+// { dg-require-effective-target c++11 }

35792

+

35793

+void f();

35794

+static_assert(f, "");

35795

+struct A {};

35796

+static_assert(A::~A, ""); // { dg-error "non-static member function" }

35797

Index: gcc/testsuite/g++.dg/cpp0x/variadic145.C

35798

===================================================================

35799

--- a/src/gcc/testsuite/g++.dg/cpp0x/variadic145.C (.../tags/gcc_4_8_2_release)

35800

+++ b/src/gcc/testsuite/g++.dg/cpp0x/variadic145.C (.../branches/gcc-4_8-branch)

35801

@@ -0,0 +1,13 @@

35802

+// PR c++/59730

35803

+// { dg-do compile { target c++11 } }

35804

+

35805

+template <typename> void declval();

35806

+template <typename> void forward();

35807

+template <typename> class D;

35808

+template <typename _Functor, typename... _Bound_args>

35809

+class D <_Functor(_Bound_args...)> {

35810

+ template <typename... _Args, decltype(declval<_Functor>)>

35811

+ void operator()(...) {

35812

+ 0(forward<_Args>...);

35813

+ }

35814

+};

35815

Index: gcc/testsuite/g++.dg/cpp0x/decltype57.C

35816

===================================================================

35817

--- a/src/gcc/testsuite/g++.dg/cpp0x/decltype57.C (.../tags/gcc_4_8_2_release)

35818

+++ b/src/gcc/testsuite/g++.dg/cpp0x/decltype57.C (.../branches/gcc-4_8-branch)

35819

@@ -0,0 +1,8 @@

35820

+// PR c++/58633

35821

+// { dg-do compile { target c++11 } }

35822

+

35823

+void foo(int i)

35824

+{

35825

+ typedef int I;

35826

+ decltype(i.I::~I())* p;

35827

+}

35828

Index: gcc/testsuite/g++.dg/cpp0x/variadic147.C

35829

===================================================================

35830

--- a/src/gcc/testsuite/g++.dg/cpp0x/variadic147.C (.../tags/gcc_4_8_2_release)

35831

+++ b/src/gcc/testsuite/g++.dg/cpp0x/variadic147.C (.../branches/gcc-4_8-branch)

35832

@@ -0,0 +1,10 @@

35833

+// PR c++/58466

35834

+// { dg-require-effective-target c++11 }

35835

+

35836

+template<char, char...> struct A;

35837

+

35838

+template<typename> struct B;

35839

+

35840

+template<char... C> struct B<A<C...>> {};

35841

+

35842

+B<A<'X'>> b;

35843

Index: gcc/testsuite/g++.dg/eh/uncaught1.C

35844

===================================================================

35845

--- a/src/gcc/testsuite/g++.dg/eh/uncaught1.C (.../tags/gcc_4_8_2_release)

35846

+++ b/src/gcc/testsuite/g++.dg/eh/uncaught1.C (.../branches/gcc-4_8-branch)

35847

@@ -13,7 +13,7 @@

35848

35849

static Check const data[] = {

35850

{ 0, 0, false }, // construct [0]

35851

- { 1, 0, true }, // [1] = [0]

35852

+ { 1, 0, false }, // [1] = [0]

35853

{ 0, 0, true }, // destruct [0]

35854

{ 2, 1, true }, // [2] = [1]

35855

{ 2, 2, true }, // destruct [2]

35856

Index: gcc/testsuite/g++.dg/eh/ppc64-sighandle-cr.C

35857

===================================================================

35858

--- a/src/gcc/testsuite/g++.dg/eh/ppc64-sighandle-cr.C (.../tags/gcc_4_8_2_release)

35859

+++ b/src/gcc/testsuite/g++.dg/eh/ppc64-sighandle-cr.C (.../branches/gcc-4_8-branch)

35860

@@ -0,0 +1,54 @@

35861

+// { dg-do run { target { powerpc64*-*-linux* } } }

35862

+// { dg-options "-fexceptions -fnon-call-exceptions" }

35863

+

35864

+#include <signal.h>

35865

+#include <stdlib.h>

35866

+#include <fenv.h>

35867

+

35868

+#define SET_CR(R,V) __asm__ __volatile__ ("mtcrf %0,%1" : : "n" (1<<(7-R)), "r" (V<<(4*(7-R))) : "cr" #R)

35869

+#define GET_CR(R) ({ int tmp; __asm__ __volatile__ ("mfcr %0" : "=r" (tmp)); (tmp >> 4*(7-R)) & 15; })

35870

+

35871

+void sighandler (int signo, siginfo_t * si, void * uc)

35872

+{

35873

+ SET_CR(2, 3);

35874

+ SET_CR(3, 2);

35875

+ SET_CR(4, 1);

35876

+

35877

+ throw 0;

35878

+}

35879

+

35880

+float test (float a, float b) __attribute__ ((__noinline__));

35881

+float test (float a, float b)

35882

+{

35883

+ float x;

35884

+ asm ("mtcrf %1,%2" : "=f" (x) : "n" (1 << (7-3)), "r" (0), "0" (b) : "cr3");

35885

+ return a / x;

35886

+}

35887

+

35888

+int main ()

35889

+{

35890

+ struct sigaction sa;

35891

+ int status;

35892

+

35893

+ sa.sa_sigaction = sighandler;

35894

+ sa.sa_flags = SA_SIGINFO;

35895

+

35896

+ status = sigaction (SIGFPE, & sa, NULL);

35897

+

35898

+ feenableexcept (FE_DIVBYZERO);

35899

+

35900

+ SET_CR(2, 6);

35901

+ SET_CR(3, 9);

35902

+ SET_CR(4, 12);

35903

+

35904

+ try {

35905

+ test (1, 0);

35906

+ }

35907

+ catch (...) {

35908

+ return GET_CR(2) != 6 || GET_CR(3) != 9 || GET_CR(4) != 12;

35909

+ }

35910

+

35911

+ return 1;

35912

+}

35913

+

35914

+

35915

Index: gcc/testsuite/g++.dg/eh/uncaught4.C

35916

===================================================================

35917

--- a/src/gcc/testsuite/g++.dg/eh/uncaught4.C (.../tags/gcc_4_8_2_release)

35918

+++ b/src/gcc/testsuite/g++.dg/eh/uncaught4.C (.../branches/gcc-4_8-branch)

35919

@@ -0,0 +1,29 @@

35920

+// PR c++/41174

35921

+// { dg-do run }

35922

+

35923

+#include <exception>

35924

+

35925

+#define assert(E) if (!(E)) __builtin_abort();

35926

+

35927

+struct e {

35928

+ e()

35929

+ {

35930

+ assert( !std::uncaught_exception() );

35931

+ try {

35932

+ throw 1;

35933

+ } catch (int i) {

35934

+ assert( !std::uncaught_exception() );

35935

+ throw;

35936

+ }

35937

+ }

35938

+};

35939

+

35940

+int main()

35941

+{

35942

+ try {

35943

+ throw e();

35944

+ } catch (int i) {

35945

+ assert( !std::uncaught_exception() );

35946

+ }

35947

+ assert( !std::uncaught_exception() );

35948

+}

35949

Index: gcc/testsuite/g++.dg/inherit/virtual11.C

35950

===================================================================

35951

--- a/src/gcc/testsuite/g++.dg/inherit/virtual11.C (.../tags/gcc_4_8_2_release)

35952

+++ b/src/gcc/testsuite/g++.dg/inherit/virtual11.C (.../branches/gcc-4_8-branch)

35953

@@ -0,0 +1,17 @@

35954

+// PR c++/59031

35955

+// { dg-do compile }

35956

+// { dg-options "-fdump-tree-gimple " }

35957

+class B {

35958

+ public:

35959

+ virtual int add (int a, int b) {return a+ b;}

35960

+};

35961

+

35962

+class D : public B {

35963

+};

35964

+

35965

+int foo (int a, int b) {

35966

+ D d;

35967

+ return d.add(a, b);

35968

+}

35969

+// { dg-final { scan-tree-dump-not "OBJ_TYPE_REF" "gimple" } }

35970

+// { dg-final { cleanup-tree-dump "gimple" } }

35971

Index: gcc/testsuite/g++.dg/torture/pr38565.C

35972

===================================================================

35973

--- a/src/gcc/testsuite/g++.dg/torture/pr38565.C (.../tags/gcc_4_8_2_release)

35974

+++ b/src/gcc/testsuite/g++.dg/torture/pr38565.C (.../branches/gcc-4_8-branch)

35975

@@ -1,6 +1,7 @@

35976

// { dg-do compile }

35977

// Ignore warning on some powerpc-linux configurations.

35978

// { dg-prune-output "non-standard ABI extension" }

35979

+// { dg-prune-output "changes the ABI" }

35980

#define vector __attribute__((vector_size(16) ))

35981

vector unsigned int f(int a)

35982

{

35983

Index: gcc/testsuite/g++.dg/torture/pr57499.C

35984

===================================================================

35985

--- a/src/gcc/testsuite/g++.dg/torture/pr57499.C (.../tags/gcc_4_8_2_release)

35986

+++ b/src/gcc/testsuite/g++.dg/torture/pr57499.C (.../branches/gcc-4_8-branch)

35987

@@ -0,0 +1,14 @@

35988

+// PR middle-end/57499

35989

+// { dg-do compile }

35990

+

35991

+struct S

35992

+{

35993

+ ~S () __attribute__ ((noreturn)) {} // { dg-warning "function does return" }

35994

+};

35995

+

35996

+void

35997

+foo ()

35998

+{

35999

+ S s;

36000

+ throw 1;

36001

+}

36002

Index: gcc/testsuite/g++.dg/torture/pr60750.C

36003

===================================================================

36004

--- a/src/gcc/testsuite/g++.dg/torture/pr60750.C (.../tags/gcc_4_8_2_release)

36005

+++ b/src/gcc/testsuite/g++.dg/torture/pr60750.C (.../branches/gcc-4_8-branch)

36006

@@ -0,0 +1,21 @@

36007

+// { dg-do run }

36008

+// { dg-options "-std=c++11" }

36009

+

36010

+#include <string>

36011

+#include <stdexcept>

36012

+

36013

+const std::string err_prefix = "Problem: ";

36014

+void thrower (std::string msg)

36015

+{

36016

+ throw std::runtime_error(err_prefix + std::move(msg));

36017

+}

36018

+

36019

+int main(int argc, char **argv)

36020

+{

36021

+ try {

36022

+ std::string base = "hello";

36023

+ thrower(std::move(base));

36024

+ } catch (const std::runtime_error &e) {

36025

+ }

36026

+ return 0;

36027

+}

36028

Index: gcc/testsuite/g++.dg/torture/pr59163.C

36029

===================================================================

36030

--- a/src/gcc/testsuite/g++.dg/torture/pr59163.C (.../tags/gcc_4_8_2_release)

36031

+++ b/src/gcc/testsuite/g++.dg/torture/pr59163.C (.../branches/gcc-4_8-branch)

36032

@@ -0,0 +1,30 @@

36033

+// PR target/59163

36034

+// { dg-do run }

36035

+

36036

+struct A { float a[4]; };

36037

+struct B { int b; A a; };

36038

+

36039

+__attribute__((noinline, noclone)) void

36040

+bar (A &a)

36041

+{

36042

+ if (a.a[0] != 36.0f || a.a[1] != 42.0f || a.a[2] != 48.0f || a.a[3] != 54.0f)

36043

+ __builtin_abort ();

36044

+}

36045

+

36046

+__attribute__((noinline, noclone)) void

36047

+foo (A &a)

36048

+{

36049

+ int i;

36050

+ A c = a;

36051

+ for (i = 0; i < 4; i++)

36052

+ c.a[i] *= 6.0f;

36053

+ a = c;

36054

+ bar (a);

36055

+}

36056

+

36057

+int

36058

+main ()

36059

+{

36060

+ B b = { 5, { 6, 7, 8, 9 } };

36061

+ foo (b.a);

36062

+}

36063

Index: gcc/testsuite/g++.dg/torture/pr60895.C

36064

===================================================================

36065

--- a/src/gcc/testsuite/g++.dg/torture/pr60895.C (.../tags/gcc_4_8_2_release)

36066

+++ b/src/gcc/testsuite/g++.dg/torture/pr60895.C (.../branches/gcc-4_8-branch)

36067

@@ -0,0 +1,32 @@

36068

+// { dg-do compile }

36069

+

36070

+struct C

36071

+{

36072

+ double elems[3];

36073

+};

36074

+

36075

+C

36076

+foo ()

36077

+{

36078

+ C a;

36079

+ double *f = a.elems;

36080

+ int b;

36081

+ for (; b;)

36082

+ {

36083

+ *f = 0;

36084

+ ++f;

36085

+ }

36086

+ return a;

36087

+}

36088

+

36089

+struct J

36090

+{

36091

+ C c;

36092

+ __attribute__((always_inline)) J () : c (foo ()) {}

36093

+};

36094

+

36095

+void

36096

+bar ()

36097

+{

36098

+ J ();

36099

+}

36100

Index: gcc/testsuite/g++.dg/ipa/pr60640-1.C

36101

===================================================================

36102

--- a/src/gcc/testsuite/g++.dg/ipa/pr60640-1.C (.../tags/gcc_4_8_2_release)

36103

+++ b/src/gcc/testsuite/g++.dg/ipa/pr60640-1.C (.../branches/gcc-4_8-branch)

36104

@@ -0,0 +1,50 @@

36105

+// { dg-do compile }

36106

+// { dg-options "-O3" }

36107

+

36108

+class ASN1Object

36109

+{

36110

+public:

36111

+ virtual ~ASN1Object ();

36112

+};

36113

+class A

36114

+{

36115

+ virtual unsigned m_fn1 () const;

36116

+};

36117

+class B

36118

+{

36119

+public:

36120

+ ASN1Object Element;

36121

+ virtual unsigned m_fn1 (bool) const;

36122

+};

36123

+template <class BASE> class C : public BASE

36124

+{

36125

+};

36126

+

36127

+class D : ASN1Object, public B

36128

+{

36129

+};

36130

+class G : public D

36131

+{

36132

+ unsigned m_fn1 (bool) const {}

36133

+};

36134

+class F : A

36135

+{

36136

+public:

36137

+ F (A);

36138

+ unsigned m_fn1 () const

36139

+ {

36140

+ int a;

36141

+ a = m_fn2 ().m_fn1 (0);

36142

+ return a;

36143

+ }

36144

+ const B &m_fn2 () const { return m_groupParameters; }

36145

+ C<G> m_groupParameters;

36146

+};

36147

+template <class D> void BenchMarkKeyAgreement (int *, int *, int)

36148

+{

36149

+ A f;

36150

+ D d (f);

36151

+}

36152

+

36153

+void BenchmarkAll2 () { BenchMarkKeyAgreement<F>(0, 0, 0); }

36154

+

36155

Index: gcc/testsuite/g++.dg/ipa/pr60640-2.C

36156

===================================================================

36157

--- a/src/gcc/testsuite/g++.dg/ipa/pr60640-2.C (.../tags/gcc_4_8_2_release)

36158

+++ b/src/gcc/testsuite/g++.dg/ipa/pr60640-2.C (.../branches/gcc-4_8-branch)

36159

@@ -0,0 +1,15 @@

36160

+// { dg-do compile }

36161

+// { dg-options "-O3" }

36162

+

36163

+struct B { virtual unsigned f () const; };

36164

+struct C { virtual void f (); };

36165

+struct F { virtual unsigned f (bool) const; ~F (); };

36166

+struct J : C, F {};

36167

+struct G : J { unsigned f (bool) const { return 0; } };

36168

+struct H : B

36169

+{

36170

+ H (int);

36171

+ unsigned f () const { return ((const F &) h).f (0); }

36172

+ G h;

36173

+};

36174

+H h (0);

36175

Index: gcc/testsuite/g++.dg/ipa/pr60640-3.C

36176

===================================================================

36177

--- a/src/gcc/testsuite/g++.dg/ipa/pr60640-3.C (.../tags/gcc_4_8_2_release)

36178

+++ b/src/gcc/testsuite/g++.dg/ipa/pr60640-3.C (.../branches/gcc-4_8-branch)

36179

@@ -0,0 +1,81 @@

36180

+// { dg-do run }

36181

+// { dg-options "-O3" }

36182

+

36183

+struct Distraction

36184

+{

36185

+ char fc[8];

36186

+ virtual Distraction * return_self ()

36187

+ { return this; }

36188

+};

36189

+

36190

+namespace {

36191

+

36192

+struct A;

36193

+static A * __attribute__ ((noinline, noclone)) get_an_A ();

36194

+

36195

+static int go;

36196

+

36197

+struct A

36198

+{

36199

+ int fi;

36200

+

36201

+ A () : fi(777) {}

36202

+ A (int pi) : fi (pi) {}

36203

+ virtual A * foo (int p) = 0;

36204

+};

36205

+

36206

+struct B;

36207

+static B * __attribute__ ((noinline, noclone)) get_a_B ();

36208

+

36209

+struct B : public Distraction, A

36210

+{

36211

+ B () : Distraction(), A() { }

36212

+ B (int pi) : Distraction (), A (pi) {}

36213

+ virtual B * foo (int p)

36214

+ {

36215

+ int o = fi;

36216

+ for (int i = 0; i < p; i++)

36217

+ o += i + i * i;

36218

+ go = o;

36219

+

36220

+ return get_a_B ();

36221

+ }

36222

+};

36223

+

36224

+

36225

+struct B gb1 (1111), gb2 (2);

36226

+static B * __attribute__ ((noinline, noclone))

36227

+get_a_B ()

36228

+{

36229

+ return &gb1;

36230

+}

36231

+

36232

+static A * __attribute__ ((noinline, noclone))

36233

+get_an_A ()

36234

+{

36235

+ return &gb2;

36236

+}

36237

+

36238

+}

36239

+

36240

+static int __attribute__ ((noinline, noclone))

36241

+get_a_number ()

36242

+{

36243

+ return 5;

36244

+}

36245

+

36246

+extern "C" void abort (void);

36247

+

36248

+int main (int argc, char *argv[])

36249

+{

36250

+ for (int i = 0; i < get_a_number (); i++)

36251

+ {

36252

+ struct A *p = get_an_A ();

36253

+ struct A *r = p->foo (4);

36254

+ if (r->fi != 1111)

36255

+ abort ();

36256

+ if (go != 22)

36257

+ abort ();

36258

+ }

36259

+ return 0;

36260

+}

36261

Index: gcc/testsuite/g++.dg/ipa/pr60419.C

36262

===================================================================

36263

--- a/src/gcc/testsuite/g++.dg/ipa/pr60419.C (.../tags/gcc_4_8_2_release)

36264

+++ b/src/gcc/testsuite/g++.dg/ipa/pr60419.C (.../branches/gcc-4_8-branch)

36265

@@ -0,0 +1,80 @@

36266

+// PR middle-end/60419

36267

+// { dg-do compile }

36268

+// { dg-options "-O2" }

36269

+

36270

+struct C

36271

+{

36272

+};

36273

+

36274

+struct I : C

36275

+{

36276

+ I ();

36277

+};

36278

+

36279

+struct J

36280

+{

36281

+ void foo ();

36282

+ J ();

36283

+ virtual void foo (int &, int);

36284

+};

36285

+

36286

+template <class>

36287

+struct D

36288

+{

36289

+ virtual void foo (I &) const;

36290

+ void bar ()

36291

+ {

36292

+ I p;

36293

+ foo (p);

36294

+ }

36295

+};

36296

+

36297

+struct K : J, public D<int>

36298

+{

36299

+};

36300

+

36301

+struct F

36302

+{

36303

+ K *operator->();

36304

+};

36305

+

36306

+struct N : public K

36307

+{

36308

+ void foo (int &, int);

36309

+ I n;

36310

+ void foo (I &) const {}

36311

+};

36312

+

36313

+struct L : J

36314

+{

36315

+ F l;

36316

+};

36317

+

36318

+struct M : F

36319

+{

36320

+ L *operator->();

36321

+};

36322

+

36323

+struct G

36324

+{

36325

+ G ();

36326

+};

36327

+

36328

+M h;

36329

+

36330

+G::G ()

36331

+try

36332

+{

36333

+ N f;

36334

+ f.bar ();

36335

+ throw;

36336

+}

36337

+catch (int)

36338

+{

36339

+}

36340

+

36341

+void

36342

+baz ()

36343

+{

36344

+ h->l->bar ();

36345

+}

36346

Index: gcc/testsuite/g++.dg/template/ref7.C

36347

===================================================================

36348

--- a/src/gcc/testsuite/g++.dg/template/ref7.C (.../tags/gcc_4_8_2_release)

36349

+++ b/src/gcc/testsuite/g++.dg/template/ref7.C (.../branches/gcc-4_8-branch)

36350

@@ -0,0 +1,16 @@

36351

+// PR c++/60274

36352

+

36353

+typedef const char *const& ProtocolIdType;

36354

+

36355

+template <ProtocolIdType protocolId>

36356

+struct C {

36357

+ typedef int ProtocolVersion;

36358

+ struct D {

36359

+ ProtocolVersion GetProtocolVersion();

36360

+ };

36361

+};

36362

+template <ProtocolIdType protocolId>

36363

+typename C<protocolId>::ProtocolVersion C<protocolId>::D::GetProtocolVersion()

36364

+{

36365

+ return 1;

36366

+}

36367

Index: gcc/testsuite/g++.dg/template/using28.C

36368

===================================================================

36369

--- a/src/gcc/testsuite/g++.dg/template/using28.C (.../tags/gcc_4_8_2_release)

36370

+++ b/src/gcc/testsuite/g++.dg/template/using28.C (.../branches/gcc-4_8-branch)

36371

@@ -0,0 +1,17 @@

36372

+// PR c++/37140

36373

+

36374

+struct C

36375

+{

36376

+ static const int block_size = 1;

36377

+};

36378

+

36379

+template <typename T> struct A {

36380

+ typedef C type;

36381

+};

36382

+

36383

+template <typename T> struct B : public A<T> {

36384

+ using typename A<T>::type;

36385

+ static const int block_size = type::block_size;

36386

+};

36387

+

36388

+template class B<int>;

36389

Index: gcc/testsuite/g++.dg/template/shadow1.C

36390

===================================================================

36391

--- a/src/gcc/testsuite/g++.dg/template/shadow1.C (.../tags/gcc_4_8_2_release)

36392

+++ b/src/gcc/testsuite/g++.dg/template/shadow1.C (.../branches/gcc-4_8-branch)

36393

@@ -0,0 +1,4 @@

36394

+// PR c++/58632

36395

+

36396

+template<template<int I> class A> // { dg-message "shadows" }

36397

+class A {}; // { dg-error "declaration" }

36398

Index: gcc/testsuite/g++.dg/template/partial14.C

36399

===================================================================

36400

--- a/src/gcc/testsuite/g++.dg/template/partial14.C (.../tags/gcc_4_8_2_release)

36401

+++ b/src/gcc/testsuite/g++.dg/template/partial14.C (.../branches/gcc-4_8-branch)

36402

@@ -0,0 +1,16 @@

36403

+// PR c++/59044

36404

+

36405

+template <class T>

36406

+class C {

36407

+private:

36408

+ template <T a, T b>

36409

+ struct Implementation {};

36410

+public:

36411

+ typedef typename Implementation<0, 0>::Typedef Type;

36412

+};

36413

+

36414

+template <class T>

36415

+template <T b>

36416

+struct C<T>::Implementation<0, b> { typedef void Typedef; };

36417

+

36418

+template class C<unsigned>;

36419

Index: gcc/testsuite/g++.dg/template/using27.C

36420

===================================================================

36421

--- a/src/gcc/testsuite/g++.dg/template/using27.C (.../tags/gcc_4_8_2_release)

36422

+++ b/src/gcc/testsuite/g++.dg/template/using27.C (.../branches/gcc-4_8-branch)

36423

@@ -0,0 +1,33 @@

36424

+// PR c++/37140

36425

+

36426

+struct X

36427

+{

36428

+ typedef int nested_type;

36429

+};

36430

+

36431

+template <class T>

36432

+struct A

36433

+{

36434

+ typedef X type;

36435

+};

36436

+

36437

+template <class T>

36438

+struct B : A<T>

36439

+{

36440

+ using typename A<T>::type;

36441

+ typename type::nested_type x;

36442

+};

36443

+

36444

+template <class T>

36445

+struct C : B<T>

36446

+{

36447

+ using typename B<T>::type;

36448

+ typename type::nested_type y;

36449

+};

36450

+

36451

+struct D : C<int>

36452

+{

36453

+ using C<int>::type;

36454

+ type::nested_type z;

36455

+};

36456

+

36457

Index: gcc/testsuite/g++.dg/template/using29.C

36458

===================================================================

36459

--- a/src/gcc/testsuite/g++.dg/template/using29.C (.../tags/gcc_4_8_2_release)

36460

+++ b/src/gcc/testsuite/g++.dg/template/using29.C (.../branches/gcc-4_8-branch)

36461

@@ -0,0 +1,21 @@

36462

+// PR c++/58047

36463

+

36464

+template <int N>

36465

+struct print_arg { };

36466

+

36467

+struct const_holder {

36468

+ static const int CONSTANT = 42;

36469

+};

36470

+

36471

+template <typename T>

36472

+struct identity {

36473

+ typedef T type;

36474

+};

36475

+

36476

+template <class T>

36477

+struct test_case : public identity<T> {

36478

+ using typename identity<T>::type;

36479

+ print_arg<type::CONSTANT> printer;

36480

+};

36481

+

36482

+template struct test_case<const_holder>;

36483

Index: gcc/testsuite/g++.dg/template/partial15.C

36484

===================================================================

36485

--- a/src/gcc/testsuite/g++.dg/template/partial15.C (.../tags/gcc_4_8_2_release)

36486

+++ b/src/gcc/testsuite/g++.dg/template/partial15.C (.../branches/gcc-4_8-branch)

36487

@@ -0,0 +1,19 @@

36488

+// PR c++/57043

36489

+// { dg-do link }

36490

+

36491

+template<typename D> struct complex { };

36492

+

36493

+template<typename Tp>

36494

+complex<Tp>

36495

+pow(const complex<Tp>& x, const complex<Tp>& y) { return complex<Tp>(); }

36496

+

36497

+template<typename T, typename U>

36498

+struct promote_2 { typedef T type; };

36499

+

36500

+template<typename Tp, typename Up>

36501

+complex<typename promote_2<Tp, Up>::type>

36502

+pow(const complex<Tp>& x, const complex<Up>& y);

36503

+

36504

+complex<double> (*powcc)(const complex<double>&, const complex<double>&) = pow;

36505

+

36506

+int main() {}

36507

Index: gcc/testsuite/c-c++-common/cpp/pr60400-1.h

36508

===================================================================

36509

--- a/src/gcc/testsuite/c-c++-common/cpp/pr60400-1.h (.../tags/gcc_4_8_2_release)

36510

+++ b/src/gcc/testsuite/c-c++-common/cpp/pr60400-1.h (.../branches/gcc-4_8-branch)

36511

@@ -0,0 +1,3 @@

36512

+??=ifndef PR60400_1_H

36513

+??=define PR60400_1_H

36514

+??=endif

36515

Index: gcc/testsuite/c-c++-common/cpp/pr60400-2.h

36516

===================================================================

36517

--- a/src/gcc/testsuite/c-c++-common/cpp/pr60400-2.h (.../tags/gcc_4_8_2_release)

36518

+++ b/src/gcc/testsuite/c-c++-common/cpp/pr60400-2.h (.../branches/gcc-4_8-branch)

36519

@@ -0,0 +1,4 @@

36520

+??=ifndef PR60400_2_H

36521

+??=define PR60400_2_H

36522

+??=include "pr60400-1.h"

36523

+??=endif

36524

Index: gcc/testsuite/c-c++-common/cpp/pr60400.c

36525

===================================================================

36526

--- a/src/gcc/testsuite/c-c++-common/cpp/pr60400.c (.../tags/gcc_4_8_2_release)

36527

+++ b/src/gcc/testsuite/c-c++-common/cpp/pr60400.c (.../branches/gcc-4_8-branch)

36528

@@ -0,0 +1,13 @@

36529

+/* PR preprocessor/60400 */

36530

+/* { dg-do compile } */

36531

+/* { dg-options "-trigraphs -Wtrigraphs" } */

36532

+

36533

+??=include "pr60400-1.h"

36534

+??=include "pr60400-2.h"

36535

+

36536

+/* { dg-warning "trigraph" "" { target *-*-* } 1 } */

36537

+/* { dg-warning "trigraph" "" { target *-*-* } 2 } */

36538

+/* { dg-warning "trigraph" "" { target *-*-* } 3 } */

36539

+/* { dg-warning "trigraph" "" { target *-*-* } 4 } */

36540

+/* { dg-warning "trigraph" "" { target *-*-* } 5 } */

36541

+/* { dg-warning "trigraph" "" { target *-*-* } 6 } */

36542

Index: gcc/testsuite/c-c++-common/cpp/pr58844-1.c

36543

===================================================================

36544

--- a/src/gcc/testsuite/c-c++-common/cpp/pr58844-1.c (.../tags/gcc_4_8_2_release)

36545

+++ b/src/gcc/testsuite/c-c++-common/cpp/pr58844-1.c (.../branches/gcc-4_8-branch)

36546

@@ -0,0 +1,8 @@

36547

+/* PR preprocessor/58844 */

36548

+/* { dg-do compile } */

36549

+/* { dg-options "-ftrack-macro-expansion=0" } */

36550

+

36551

+#define A x######x

36552

+int A = 1;

36553

+#define A x######x /* { dg-message "previous definition" } */

36554

+#define A x##x /* { dg-warning "redefined" } */

36555

Index: gcc/testsuite/c-c++-common/cpp/pr58844-2.c

36556

===================================================================

36557

--- a/src/gcc/testsuite/c-c++-common/cpp/pr58844-2.c (.../tags/gcc_4_8_2_release)

36558

+++ b/src/gcc/testsuite/c-c++-common/cpp/pr58844-2.c (.../branches/gcc-4_8-branch)

36559

@@ -0,0 +1,8 @@

36560

+/* PR preprocessor/58844 */

36561

+/* { dg-do compile } */

36562

+/* { dg-options "-ftrack-macro-expansion=2" } */

36563

+

36564

+#define A x######x

36565

+int A = 1;

36566

+#define A x######x /* { dg-message "previous definition" } */

36567

+#define A x##x /* { dg-warning "redefined" } */

36568

Index: gcc/testsuite/c-c++-common/convert-vec-1.c

36569

===================================================================

36570

--- a/src/gcc/testsuite/c-c++-common/convert-vec-1.c (.../tags/gcc_4_8_2_release)

36571

+++ b/src/gcc/testsuite/c-c++-common/convert-vec-1.c (.../branches/gcc-4_8-branch)

36572

@@ -1,3 +1,4 @@

36573

/* { dg-do compile } */

36574

+/* { dg-prune-output "changes the ABI" } */

36575

typedef float v2sf __attribute__ ((vector_size (8)));

36576

v2sf sub (void) { return (v2sf) 0.0; } /* { dg-error "can't convert" } */

36577

Index: gcc/testsuite/c-c++-common/pr60101.c

36578

===================================================================

36579

--- a/src/gcc/testsuite/c-c++-common/pr60101.c (.../tags/gcc_4_8_2_release)

36580

+++ b/src/gcc/testsuite/c-c++-common/pr60101.c (.../branches/gcc-4_8-branch)

36581

@@ -0,0 +1,112 @@

36582

+/* PR c/60101 */

36583

+/* { dg-do compile } */

36584

+/* { dg-options "-O2 -Wall" } */

36585

+

36586

+extern int *a, b, *c, *d;

36587

+

36588

+void

36589

+foo (double _Complex *x, double _Complex *y, double _Complex *z, unsigned int l, int w)

36590

+{

36591

+ unsigned int e = (unsigned int) a[3];

36592

+ double _Complex (*v)[l][4][e][l][4] = (double _Complex (*)[l][4][e][l][4]) z;

36593

+ double _Complex (*f)[l][b][l] = (double _Complex (*)[l][b][l]) y;

36594

+ unsigned int g = c[0] * c[1] * c[2];

36595

+ unsigned int h = d[0] + c[0] * (d[1] + c[1] * d[2]);

36596

+ unsigned int i;

36597

+

36598

+ for (i = 0; i < e; i++)

36599

+ {

36600

+ int j = e * d[3] + i;

36601

+

36602

+ unsigned int n0, n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11;

36603

+ float _Complex s = 0.;

36604

+ unsigned int t = 0;

36605

+

36606

+ for (n0 = 0; n0 < l; n0++)

36607

+ for (n1 = 0; n1 < l; n1++)

36608

+ for (n2 = 0; n2 < l; n2++)

36609

+ for (n3 = 0; n3 < l; n3++)

36610

+ for (n4 = 0; n4 < l; n4++)

36611

+ for (n5 = 0; n5 < l; n5++)

36612

+ for (n6 = 0; n6 < l; n6++)

36613

+ for (n7 = 0; n7 < l; n7++)

36614

+ for (n8 = 0; n8 < l; n8++)

36615

+ for (n9 = 0; n9 < l; n9++)

36616

+ for (n10 = 0; n10 < l; n10++)

36617

+ for (n11 = 0; n11 < l; n11++)

36618

+ {

36619

+ if (t % g == h)

36620

+ s

36621

+ += f[n0][n4][j][n8] * f[n1][n5][j][n9] * ~(f[n2][n6][w][n10]) * ~(f[n3][n7][w][n11])

36622

+ * (+0.25 * v[0][n2][0][i][n9][1] * v[0][n3][0][i][n5][1] * v[0][n10][0][i][n4][1]

36623

+ * v[0][n7][1][i][n8][0] * v[0][n11][1][i][n1][0] * v[0][n6][1][i][n0][0]

36624

+ + 0.25 * v[0][n2][0][i][n9][1] * v[0][n3][0][i][n5][1] * v[0][n10][0][i][n4][1]

36625

+ * v[0][n11][1][i][n8][0] * v[0][n6][1][i][n1][0] * v[0][n7][1][i][n0][0]

36626

+ - 0.5 * v[0][n2][0][i][n9][1] * v[0][n3][0][i][n5][1] * v[0][n10][0][i][n4][1]

36627

+ * v[0][n11][1][i][n8][0] * v[0][n7][1][i][n1][0] * v[0][n6][1][i][n0][0]

36628

+ + 0.25 * v[0][n2][0][i][n9][1] * v[0][n10][0][i][n5][1] * v[0][n3][0][i][n4][1]

36629

+ * v[0][n7][1][i][n8][0] * v[0][n6][1][i][n1][0] * v[0][n11][1][i][n0][0]

36630

+ - 0.5 * v[0][n2][0][i][n9][1] * v[0][n10][0][i][n5][1] * v[0][n3][0][i][n4][1]

36631

+ * v[0][n11][1][i][n8][0] * v[0][n6][1][i][n1][0] * v[0][n7][1][i][n0][0]

36632

+ + 0.25 * v[0][n2][0][i][n9][1] * v[0][n10][0][i][n5][1] * v[0][n3][0][i][n4][1]

36633

+ * v[0][n11][1][i][n8][0] * v[0][n7][1][i][n1][0] * v[0][n6][1][i][n0][0]

36634

+ + 0.25 * v[0][n3][0][i][n9][1] * v[0][n2][0][i][n5][1] * v[0][n10][0][i][n4][1]

36635

+ * v[0][n6][1][i][n8][0] * v[0][n11][1][i][n1][0] * v[0][n7][1][i][n0][0]

36636

+ - 0.5 * v[0][n3][0][i][n9][1] * v[0][n2][0][i][n5][1] * v[0][n10][0][i][n4][1]

36637

+ * v[0][n11][1][i][n8][0] * v[0][n6][1][i][n1][0] * v[0][n7][1][i][n0][0]

36638

+ + 0.25 * v[0][n3][0][i][n9][1] * v[0][n2][0][i][n5][1] * v[0][n10][0][i][n4][1]

36639

+ * v[0][n11][1][i][n8][0] * v[0][n7][1][i][n1][0] * v[0][n6][1][i][n0][0]

36640

+ + 0.25 * v[0][n3][0][i][n9][1] * v[0][n10][0][i][n5][1] * v[0][n2][0][i][n4][1]

36641

+ * v[0][n6][1][i][n8][0] * v[0][n7][1][i][n1][0] * v[0][n11][1][i][n0][0]

36642

+ + 0.25 * v[0][n3][0][i][n9][1] * v[0][n10][0][i][n5][1] * v[0][n2][0][i][n4][1]

36643

+ * v[0][n11][1][i][n8][0] * v[0][n6][1][i][n1][0] * v[0][n7][1][i][n0][0]

36644

+ - 0.5 * v[0][n3][0][i][n9][1] * v[0][n10][0][i][n5][1] * v[0][n2][0][i][n4][1]

36645

+ * v[0][n11][1][i][n8][0] * v[0][n7][1][i][n1][0] * v[0][n6][1][i][n0][0]

36646

+ + 0.25 * v[0][n10][0][i][n9][1] * v[0][n2][0][i][n5][1] * v[0][n3][0][i][n4][1]

36647

+ * v[0][n6][1][i][n8][0] * v[0][n7][1][i][n1][0] * v[0][n11][1][i][n0][0]

36648

+ - 0.5 * v[0][n10][0][i][n9][1] * v[0][n2][0][i][n5][1] * v[0][n3][0][i][n4][1]

36649

+ * v[0][n6][1][i][n8][0] * v[0][n11][1][i][n1][0] * v[0][n7][1][i][n0][0]

36650

+ - 0.5 * v[0][n10][0][i][n9][1] * v[0][n2][0][i][n5][1] * v[0][n3][0][i][n4][1]

36651

+ * v[0][n7][1][i][n8][0] * v[0][n6][1][i][n1][0] * v[0][n11][1][i][n0][0]

36652

+ + 0.25 * v[0][n10][0][i][n9][1] * v[0][n2][0][i][n5][1] * v[0][n3][0][i][n4][1]

36653

+ * v[0][n7][1][i][n8][0] * v[0][n11][1][i][n1][0] * v[0][n6][1][i][n0][0]

36654

+ + 1. * v[0][n10][0][i][n9][1] * v[0][n2][0][i][n5][1] * v[0][n3][0][i][n4][1]

36655

+ * v[0][n11][1][i][n8][0] * v[0][n6][1][i][n1][0] * v[0][n7][1][i][n0][0]

36656

+ - 0.5 * v[0][n10][0][i][n9][1] * v[0][n2][0][i][n5][1] * v[0][n3][0][i][n4][1]

36657

+ * v[0][n11][1][i][n8][0] * v[0][n7][1][i][n1][0] * v[0][n6][1][i][n0][0]

36658

+ - 0.5 * v[0][n10][0][i][n9][1] * v[0][n3][0][i][n5][1] * v[0][n2][0][i][n4][1]

36659

+ * v[0][n6][1][i][n8][0] * v[0][n7][1][i][n1][0] * v[0][n11][1][i][n0][0]

36660

+ + 0.25 * v[0][n10][0][i][n9][1] * v[0][n3][0][i][n5][1] * v[0][n2][0][i][n4][1]

36661

+ * v[0][n6][1][i][n8][0] * v[0][n11][1][i][n1][0] * v[0][n7][1][i][n0][0]

36662

+ + 0.25 * v[0][n10][0][i][n9][1] * v[0][n3][0][i][n5][1] * v[0][n2][0][i][n4][1]

36663

+ * v[0][n7][1][i][n8][0] * v[0][n6][1][i][n1][0] * v[0][n11][1][i][n0][0]

36664

+ - 0.5 * v[0][n10][0][i][n9][1] * v[0][n3][0][i][n5][1] * v[0][n2][0][i][n4][1]

36665

+ * v[0][n7][1][i][n8][0] * v[0][n11][1][i][n1][0] * v[0][n6][1][i][n0][0]

36666

+ - 0.5 * v[0][n10][0][i][n9][1] * v[0][n3][0][i][n5][1] * v[0][n2][0][i][n4][1]

36667

+ * v[0][n11][1][i][n8][0] * v[0][n6][1][i][n1][0] * v[0][n7][1][i][n0][0]

36668

+ + 1. * v[0][n10][0][i][n9][1] * v[0][n3][0][i][n5][1] * v[0][n2][0][i][n4][1]

36669

+ * v[0][n11][1][i][n8][0] * v[0][n7][1][i][n1][0] * v[0][n6][1][i][n0][0]

36670

+ + 0.5 * v[0][n6][1][i][n4][1] * v[0][n2][0][i][n9][1] * v[0][n3][0][i][n5][1]

36671

+ * v[0][n7][1][i][n1][0] * v[0][n11][1][i][n0][0] * v[0][n10][0][i][n8][0]

36672

+ - 0.25 * v[0][n6][1][i][n4][1] * v[0][n2][0][i][n9][1] * v[0][n3][0][i][n5][1]

36673

+ * v[0][n11][1][i][n1][0] * v[0][n7][1][i][n0][0] * v[0][n10][0][i][n8][0]

36674

+ - 0.25 * v[0][n6][1][i][n4][1] * v[0][n2][0][i][n9][1] * v[0][n3][0][i][n5][1]

36675

+ * v[0][n7][1][i][n8][0] * v[0][n11][1][i][n0][0] * v[0][n10][0][i][n1][0]

36676

+ + 0.25 * v[0][n6][1][i][n4][1] * v[0][n2][0][i][n9][1] * v[0][n3][0][i][n5][1]

36677

+ * v[0][n7][1][i][n8][0] * v[0][n11][1][i][n1][0] * v[0][n10][0][i][n0][0]

36678

+ + 0.25 * v[0][n6][1][i][n4][1] * v[0][n2][0][i][n9][1] * v[0][n3][0][i][n5][1]

36679

+ * v[0][n11][1][i][n8][0] * v[0][n7][1][i][n0][0] * v[0][n10][0][i][n1][0]

36680

+ - 0.5 * v[0][n6][1][i][n4][1] * v[0][n2][0][i][n9][1] * v[0][n3][0][i][n5][1]

36681

+ * v[0][n11][1][i][n8][0] * v[0][n7][1][i][n1][0] * v[0][n10][0][i][n0][0]

36682

+ - 0.25 * v[0][n6][1][i][n4][1] * v[0][n2][0][i][n9][1] * v[0][n10][0][i][n5][1]

36683

+ * v[0][n7][1][i][n1][0] * v[0][n11][1][i][n0][0] * v[0][n3][0][i][n8][0]

36684

+ - 0.25 * v[0][n6][1][i][n4][1] * v[0][n2][0][i][n9][1] * v[0][n10][0][i][n5][1]

36685

+ * v[0][n7][1][i][n8][0] * v[0][n11][1][i][n0][0] * v[0][n3][0][i][n1][0]);

36686

+ t++;

36687

+ }

36688

+ int u = (j - w + b) % b;

36689

+ int q = (j >= w ? +1 : -1);

36690

+ int r = q;

36691

+ x[u] += r * s;

36692

+ }

36693

+}

36694

Index: gcc/testsuite/c-c++-common/pr36282-3.c

36695

===================================================================

36696

--- a/src/gcc/testsuite/c-c++-common/pr36282-3.c (.../tags/gcc_4_8_2_release)

36697

+++ b/src/gcc/testsuite/c-c++-common/pr36282-3.c (.../branches/gcc-4_8-branch)

36698

@@ -0,0 +1,13 @@

36699

+/* PR middle-end/36282 */

36700

+/* { dg-do compile } */

36701

+

36702

+void bar (void);

36703

+#pragma weak bar

36704

+

36705

+extern void *baz (void *dest, const void *src, __SIZE_TYPE__ n);

36706

+extern __typeof (baz) baz __asm("bazfn"); /* { dg-bogus "asm declaration ignored due to conflict with previous rename" } */

36707

+

36708

+void

36709

+foo (void)

36710

+{

36711

+}

36712

Index: gcc/testsuite/c-c++-common/pr59037.c

36713

===================================================================

36714

--- a/src/gcc/testsuite/c-c++-common/pr59037.c (.../tags/gcc_4_8_2_release)

36715

+++ b/src/gcc/testsuite/c-c++-common/pr59037.c (.../branches/gcc-4_8-branch)

36716

@@ -0,0 +1,12 @@

36717

+/* { dg-do compile } */

36718

+/* { dg-options "-O3" } */

36719

+

36720

+typedef int v4si __attribute__ ((vector_size (16)));

36721

+

36722

+int

36723

+main (int argc, char** argv)

36724

+{

36725

+ v4si x = {0,1,2,3};

36726

+ x = (v4si) {(x)[3], (x)[2], (x)[1], (x)[0]};

36727

+ return x[4];

36728

+}

36729

Index: gcc/testsuite/c-c++-common/pr59280.c

36730

===================================================================

36731

--- a/src/gcc/testsuite/c-c++-common/pr59280.c (.../tags/gcc_4_8_2_release)

36732

+++ b/src/gcc/testsuite/c-c++-common/pr59280.c (.../branches/gcc-4_8-branch)

36733

@@ -0,0 +1,4 @@

36734

+/* PR c/59280 */

36735

+/* { dg-do compile } */

36736

+

36737

+void bar (char *) __attribute__((constructor(foo))); /* { dg-error "constructor priorities must be integers|was not declared|constructor priorities are not supported" } */

36738

Index: gcc/testsuite/c-c++-common/pr37743.c

36739

===================================================================

36740

--- a/src/gcc/testsuite/c-c++-common/pr37743.c (.../tags/gcc_4_8_2_release)

36741

+++ b/src/gcc/testsuite/c-c++-common/pr37743.c (.../branches/gcc-4_8-branch)

36742

@@ -0,0 +1,13 @@

36743

+/* PR c/37743 */

36744

+/* This needs to be run only on targets where __UINT32_TYPE__ is defined

36745

+ to unsigned int. */

36746

+/* { dg-do compile { target *-*-linux-gnu* } } */

36747

+/* { dg-options "-Wformat" } */

36748

+

36749

+int foo (const char *, ...) __attribute__ ((format (printf, 1, 2)));

36750

+

36751

+void

36752

+bar (unsigned int x)

36753

+{

36754

+ foo ("%x", __builtin_bswap32 (x));

36755

+}

36756

Index: gcc/testsuite/c-c++-common/fold-divmul-1.c

36757

===================================================================

36758

--- a/src/gcc/testsuite/c-c++-common/fold-divmul-1.c (.../tags/gcc_4_8_2_release)

36759

+++ b/src/gcc/testsuite/c-c++-common/fold-divmul-1.c (.../branches/gcc-4_8-branch)

36760

@@ -0,0 +1,11 @@

36761

+/* { dg-do compile } */

36762

+/* { dg-options "-fdump-tree-original" } */

36763

+

36764

+int *

36765

+fx (int *b, int *e)

36766

+{

36767

+ return b + (e - b);

36768

+}

36769

+

36770

+/* { dg-final { scan-tree-dump-not "/\\\[ex\\\]" "original" } } */

36771

+/* { dg-final { cleanup-tree-dump "original" } } */

36772

Index: gcc/testsuite/c-c++-common/torture/pr58794-1.c

36773

===================================================================

36774

--- a/src/gcc/testsuite/c-c++-common/torture/pr58794-1.c (.../tags/gcc_4_8_2_release)

36775

+++ b/src/gcc/testsuite/c-c++-common/torture/pr58794-1.c (.../branches/gcc-4_8-branch)

36776

@@ -0,0 +1,29 @@

36777

+/* { dg-do compile } */

36778

+

36779

+struct S0

36780

+{

36781

+ int f;

36782

+};

36783

+

36784

+struct S1

36785

+{

36786

+ struct S0 f1;

36787

+ volatile int f2;

36788

+};

36789

+

36790

+struct S2

36791

+{

36792

+ struct S1 g;

36793

+} a, b;

36794

+

36795

+static int *c[1][2] = {{0, (int *)&a.g.f2}};

36796

+static int d;

36797

+

36798

+int

36799

+main ()

36800

+{

36801

+ for (d = 0; d < 1; d++)

36802

+ for (b.g.f1.f = 0; b.g.f1.f < 1; b.g.f1.f++)

36803

+ *c[b.g.f1.f][d + 1] = 0;

36804

+ return 0;

36805

+}

36806

Index: gcc/testsuite/c-c++-common/torture/pr58794-2.c

36807

===================================================================

36808

--- a/src/gcc/testsuite/c-c++-common/torture/pr58794-2.c (.../tags/gcc_4_8_2_release)

36809

+++ b/src/gcc/testsuite/c-c++-common/torture/pr58794-2.c (.../branches/gcc-4_8-branch)

36810

@@ -0,0 +1,21 @@

36811

+/* { dg-do compile } */

36812

+

36813

+struct S

36814

+{

36815

+ volatile int f;

36816

+} a;

36817

+

36818

+unsigned int b;

36819

+

36820

+static int *c[1][2] = {{0, (int *)&a.f}};

36821

+static unsigned int d;

36822

+

36823

+int

36824

+main ()

36825

+{

36826

+ for (; d < 1; d++)

36827

+ for (; b < 1; b++)

36828

+ *c[b][d + 1] = 0;

36829

+

36830

+ return 0;

36831

+}

36832

Index: gcc/testsuite/c-c++-common/torture/pr60026.c

36833

===================================================================

36834

--- a/src/gcc/testsuite/c-c++-common/torture/pr60026.c (.../tags/gcc_4_8_2_release)

36835

+++ b/src/gcc/testsuite/c-c++-common/torture/pr60026.c (.../branches/gcc-4_8-branch)

36836

@@ -0,0 +1,28 @@

36837

+/* PR ipa/60026 */

36838

+/* { dg-do compile } */

36839

+

36840

+struct S { int f; } a;

36841

+

36842

+__attribute__((optimize (0)))

36843

+struct S foo (int x, struct S y)

36844

+{

36845

+ int b = y.f;

36846

+ return a;

36847

+}

36848

+

36849

+void

36850

+bar ()

36851

+{

36852

+ while (a.f)

36853

+ {

36854

+ struct S c = {0};

36855

+ foo (0, c);

36856

+ }

36857

+}

36858

+

36859

+int

36860

+main ()

36861

+{

36862

+ bar ();

36863

+ return 0;

36864

+}

36865

Index: gcc/testsuite/c-c++-common/vector-compare-2.c

36866

===================================================================

36867

--- a/src/gcc/testsuite/c-c++-common/vector-compare-2.c (.../tags/gcc_4_8_2_release)

36868

+++ b/src/gcc/testsuite/c-c++-common/vector-compare-2.c (.../branches/gcc-4_8-branch)

36869

@@ -1,6 +1,7 @@

36870

/* { dg-do compile } */

36871

/* { dg-options "-fno-common" { target hppa*-*-hpux* } } */

36872

/* { dg-options "-mabi=altivec" { target { { powerpc*-*-linux* } && ilp32 } } } */

36873

+/* { dg-options "-msse2" { target { i?86-*-* x86_64-*-* } } } */

36874

/* Ignore warning on some powerpc-ibm-aix configurations. */

36875

/* { dg-prune-output "non-standard ABI extension" } */

36876

36877

Index: gcc/testsuite/c-c++-common/pr36282-4.c

36878

===================================================================

36879

--- a/src/gcc/testsuite/c-c++-common/pr36282-4.c (.../tags/gcc_4_8_2_release)

36880

+++ b/src/gcc/testsuite/c-c++-common/pr36282-4.c (.../branches/gcc-4_8-branch)

36881

@@ -0,0 +1,13 @@

36882

+/* PR middle-end/36282 */

36883

+/* { dg-do compile } */

36884

+

36885

+#pragma weak bar

36886

+void bar (void);

36887

+

36888

+extern void *baz (void *dest, const void *src, __SIZE_TYPE__ n);

36889

+extern __typeof (baz) baz __asm("bazfn"); /* { dg-bogus "asm declaration ignored due to conflict with previous rename" } */

36890

+

36891

+void

36892

+foo (void)

36893

+{

36894

+}

36895

Index: gcc/testsuite/c-c++-common/gomp/pr58809.c

36896

===================================================================

36897

--- a/src/gcc/testsuite/c-c++-common/gomp/pr58809.c (.../tags/gcc_4_8_2_release)

36898

+++ b/src/gcc/testsuite/c-c++-common/gomp/pr58809.c (.../branches/gcc-4_8-branch)

36899

@@ -0,0 +1,31 @@

36900

+/* PR middle-end/58809 */

36901

+/* { dg-do compile } */

36902

+/* { dg-options "-fopenmp" } */

36903

+

36904

+_Complex int j;

36905

+_Complex double d;

36906

+

36907

+void

36908

+foo (void)

36909

+{

36910

+ #pragma omp parallel reduction (&:j) /* { dg-error "has invalid type for" } */

36911

+ ;

36912

+ #pragma omp parallel reduction (|:j) /* { dg-error "has invalid type for" } */

36913

+ ;

36914

+ #pragma omp parallel reduction (^:j) /* { dg-error "has invalid type for" } */

36915

+ ;

36916

+ #pragma omp parallel reduction (min:j) /* { dg-error "has invalid type for" } */

36917

+ ;

36918

+ #pragma omp parallel reduction (max:j) /* { dg-error "has invalid type for" } */

36919

+ ;

36920

+ #pragma omp parallel reduction (&:d) /* { dg-error "has invalid type for" } */

36921

+ ;

36922

+ #pragma omp parallel reduction (|:d) /* { dg-error "has invalid type for" } */

36923

+ ;

36924

+ #pragma omp parallel reduction (^:d) /* { dg-error "has invalid type for" } */

36925

+ ;

36926

+ #pragma omp parallel reduction (min:d) /* { dg-error "has invalid type for" } */

36927

+ ;

36928

+ #pragma omp parallel reduction (max:d) /* { dg-error "has invalid type for" } */

36929

+ ;

36930

+}

36931

Index: gcc/testsuite/c-c++-common/gomp/pr59467.c

36932

===================================================================

36933

--- a/src/gcc/testsuite/c-c++-common/gomp/pr59467.c (.../tags/gcc_4_8_2_release)

36934

+++ b/src/gcc/testsuite/c-c++-common/gomp/pr59467.c (.../branches/gcc-4_8-branch)

36935

@@ -0,0 +1,68 @@

36936

+/* PR libgomp/59467 */

36937

+

36938

+int v;

36939

+

36940

+void

36941

+foo (void)

36942

+{

36943

+ int x = 0, y = 0;

36944

+ #pragma omp parallel

36945

+ {

36946

+ int z;

36947

+ #pragma omp single copyprivate (x) /* { dg-error "is not threadprivate or private in outer context" } */

36948

+ {

36949

+ #pragma omp atomic write

36950

+ x = 6;

36951

+ }

36952

+ #pragma omp atomic read

36953

+ z = x;

36954

+ #pragma omp atomic

36955

+ y += z;

36956

+ }

36957

+ #pragma omp parallel

36958

+ {

36959

+ int z;

36960

+ #pragma omp single copyprivate (v) /* { dg-error "is not threadprivate or private in outer context" } */

36961

+ {

36962

+ #pragma omp atomic write

36963

+ v = 6;

36964

+ }

36965

+ #pragma omp atomic read

36966

+ z = v;

36967

+ #pragma omp atomic

36968

+ y += z;

36969

+ }

36970

+ #pragma omp parallel private (x)

36971

+ {

36972

+ int z;

36973

+ #pragma omp single copyprivate (x)

36974

+ {

36975

+ #pragma omp atomic write

36976

+ x = 6;

36977

+ }

36978

+ #pragma omp atomic read

36979

+ z = x;

36980

+ #pragma omp atomic

36981

+ y += z;

36982

+ }

36983

+ x = 0;

36984

+ #pragma omp parallel reduction (+:x)

36985

+ {

36986

+ #pragma omp single copyprivate (x)

36987

+ {

36988

+ #pragma omp atomic write

36989

+ x = 6;

36990

+ }

36991

+ #pragma omp atomic

36992

+ y += x;

36993

+ }

36994

+ #pragma omp single copyprivate (x)

36995

+ {

36996

+ x = 7;

36997

+ }

36998

+ #pragma omp single copyprivate (v) /* { dg-error "is not threadprivate or private in outer context" } */

36999

+ {

37000

+ #pragma omp atomic write

37001

+ v = 6;

37002

+ }

37003

+}

37004

Index: gcc/testsuite/c-c++-common/pr36282-1.c

37005

===================================================================

37006

--- a/src/gcc/testsuite/c-c++-common/pr36282-1.c (.../tags/gcc_4_8_2_release)

37007

+++ b/src/gcc/testsuite/c-c++-common/pr36282-1.c (.../branches/gcc-4_8-branch)

37008

@@ -0,0 +1,12 @@

37009

+/* PR middle-end/36282 */

37010

+/* { dg-do compile } */

37011

+

37012

+#pragma weak bar

37013

+

37014

+extern void *baz (void *dest, const void *src, __SIZE_TYPE__ n);

37015

+extern __typeof (baz) baz __asm("bazfn"); /* { dg-bogus "asm declaration ignored due to conflict with previous rename" } */

37016

+

37017

+void

37018

+foo (void)

37019

+{

37020

+}

37021

Index: gcc/testsuite/c-c++-common/pr60689.c

37022

===================================================================

37023

--- a/src/gcc/testsuite/c-c++-common/pr60689.c (.../tags/gcc_4_8_2_release)

37024

+++ b/src/gcc/testsuite/c-c++-common/pr60689.c (.../branches/gcc-4_8-branch)

37025

@@ -0,0 +1,10 @@

37026

+/* PR c++/60689 */

37027

+/* { dg-do compile } */

37028

+

37029

+struct S { char x[9]; };

37030

+

37031

+void

37032

+foo (struct S *x, struct S *y, struct S *z)

37033

+{

37034

+ __atomic_exchange (x, y, z, __ATOMIC_SEQ_CST);

37035

+}

37036

Index: gcc/testsuite/c-c++-common/scal-to-vec2.c

37037

===================================================================

37038

--- a/src/gcc/testsuite/c-c++-common/scal-to-vec2.c (.../tags/gcc_4_8_2_release)

37039

+++ b/src/gcc/testsuite/c-c++-common/scal-to-vec2.c (.../branches/gcc-4_8-branch)

37040

@@ -1,6 +1,7 @@

37041

/* { dg-do compile } */

37042

/* { dg-options "-fno-common" { target hppa*-*-hpux* } } */

37043

/* { dg-options "-mabi=altivec" { target { { powerpc*-*-linux* } && ilp32 } } } */

37044

+/* { dg-options "-msse2" { target { i?86-*-* x86_64-*-* } } } */

37045

/* Ignore warning on some powerpc-ibm-aix configurations. */

37046

/* { dg-prune-output "non-standard ABI extension" } */

37047

37048

Index: gcc/testsuite/c-c++-common/pr59032.c

37049

===================================================================

37050

--- a/src/gcc/testsuite/c-c++-common/pr59032.c (.../tags/gcc_4_8_2_release)

37051

+++ b/src/gcc/testsuite/c-c++-common/pr59032.c (.../branches/gcc-4_8-branch)

37052

@@ -0,0 +1,30 @@

37053

+/* { dg-do compile } */

37054

+/* { dg-options "-O2" } */

37055

+

37056

+void

37057

+foo()

37058

+{

37059

+ float v __attribute__((vector_size(8)));

37060

+ v++;

37061

+}

37062

+

37063

+void

37064

+foo2 ()

37065

+{

37066

+ float v __attribute__((vector_size(8)));

37067

+ ++v;

37068

+}

37069

+

37070

+void

37071

+foo3 ()

37072

+{

37073

+ float v __attribute__((vector_size(8)));

37074

+ v--;

37075

+}

37076

+

37077

+void

37078

+foo4 ()

37079

+{

37080

+ float v __attribute__((vector_size(8)));

37081

+ --v;

37082

+}

37083

Index: gcc/testsuite/c-c++-common/pr36282-2.c

37084

===================================================================

37085

--- a/src/gcc/testsuite/c-c++-common/pr36282-2.c (.../tags/gcc_4_8_2_release)

37086

+++ b/src/gcc/testsuite/c-c++-common/pr36282-2.c (.../branches/gcc-4_8-branch)

37087

@@ -0,0 +1,10 @@

37088

+/* PR middle-end/36282 */

37089

+/* { dg-do compile } */

37090

+

37091

+extern void *baz (void *dest, const void *src, __SIZE_TYPE__ n);

37092

+extern __typeof (baz) baz __asm("bazfn"); /* { dg-bogus "asm declaration ignored due to conflict with previous rename" } */

37093

+

37094

+void

37095

+foo (void)

37096

+{

37097

+}

37098

Index: gcc/cp/typeck.c

37099

===================================================================

37100

--- a/src/gcc/cp/typeck.c (.../tags/gcc_4_8_2_release)

37101

+++ b/src/gcc/cp/typeck.c (.../branches/gcc-4_8-branch)

37102

@@ -4103,6 +4103,11 @@

37103

case TRUTH_ORIF_EXPR:

37104

case TRUTH_AND_EXPR:

37105

case TRUTH_OR_EXPR:

37106

+ if (TREE_CODE (type0) == VECTOR_TYPE || TREE_CODE (type1) == VECTOR_TYPE)

37107

+ {

37108

+ sorry ("logical operation on vector type");

37109

+ return error_mark_node;

37110

+ }

37111

result_type = boolean_type_node;

37112

break;

37113

37114

@@ -5010,7 +5015,10 @@

37115

cp_truthvalue_conversion (tree expr)

37116

{

37117

tree type = TREE_TYPE (expr);

37118

- if (TYPE_PTRDATAMEM_P (type))

37119

+ if (TYPE_PTRDATAMEM_P (type)

37120

+ /* Avoid ICE on invalid use of non-static member function. */

37121

+ || (TREE_CODE (expr) == FUNCTION_DECL

37122

+ && DECL_NONSTATIC_MEMBER_FUNCTION_P (expr)))

37123

return build_binary_op (EXPR_LOCATION (expr),

37124

NE_EXPR, expr, nullptr_node, 1);

37125

else if (TYPE_PTR_P (type) || TYPE_PTRMEMFUNC_P (type))

37126

@@ -5588,7 +5596,9 @@

37127

inc = cxx_sizeof_nowarn (TREE_TYPE (argtype));

37128

}

37129

else

37130

- inc = integer_one_node;

37131

+ inc = (TREE_CODE (argtype) == VECTOR_TYPE

37132

+ ? build_one_cst (argtype)

37133

+ : integer_one_node);

37134

37135

inc = cp_convert (argtype, inc, complain);

37136

37137

@@ -6639,7 +6649,7 @@

37138

where possible, and it is necessary in some cases. DR 195

37139

addresses this issue, but as of 2004/10/26 is still in

37140

drafting. */

37141

- warning (0, "ISO C++ forbids casting between pointer-to-function and pointer-to-object");

37142

+ warning (OPT_Wpedantic, "ISO C++ forbids casting between pointer-to-function and pointer-to-object");

37143

return fold_if_not_in_template (build_nop (type, expr));

37144

}

37145

else if (TREE_CODE (type) == VECTOR_TYPE)

37146

@@ -7194,8 +7204,7 @@

37147

side effect associated with any single compound assignment

37148

operator. -- end note ] */

37149

lhs = stabilize_reference (lhs);

37150

- if (TREE_SIDE_EFFECTS (rhs))

37151

- rhs = mark_rvalue_use (rhs);

37152

+ rhs = rvalue (rhs);

37153

rhs = stabilize_expr (rhs, &init);

37154

newrhs = cp_build_binary_op (input_location,

37155

modifycode, lhs, rhs,

37156

@@ -7611,7 +7620,7 @@

37157

/* Handle null pointer to member function conversions. */

37158

if (null_ptr_cst_p (pfn))

37159

{

37160

- pfn = build_c_cast (input_location, type, pfn);

37161

+ pfn = cp_build_c_cast (type, pfn, complain);

37162

return build_ptrmemfunc1 (to_type,

37163

integer_zero_node,

37164

pfn);

37165

Index: gcc/cp/decl.c

37166

===================================================================

37167

--- a/src/gcc/cp/decl.c (.../tags/gcc_4_8_2_release)

37168

+++ b/src/gcc/cp/decl.c (.../branches/gcc-4_8-branch)

37169

@@ -1867,9 +1867,9 @@

37170

/* Merge the data types specified in the two decls. */

37171

newtype = merge_types (TREE_TYPE (newdecl), TREE_TYPE (olddecl));

37172

37173

- /* If merge_types produces a non-typedef type, just use the old type. */

37174

- if (TREE_CODE (newdecl) == TYPE_DECL

37175

- && newtype == DECL_ORIGINAL_TYPE (newdecl))

37176

+ /* For typedefs use the old type, as the new type's DECL_NAME points

37177

+ at newdecl, which will be ggc_freed. */

37178

+ if (TREE_CODE (newdecl) == TYPE_DECL)

37179

newtype = oldtype;

37180

37181

if (TREE_CODE (newdecl) == VAR_DECL)

37182

@@ -8193,7 +8193,9 @@

37183

abi_1_itype = error_mark_node;

37184

}

37185

37186

- size = maybe_constant_value (size);

37187

+ if (INTEGRAL_OR_UNSCOPED_ENUMERATION_TYPE_P (type))

37188

+ size = maybe_constant_value (size);

37189

+

37190

if (!TREE_CONSTANT (size))

37191

size = osize;

37192

}

37193

@@ -11891,7 +11893,10 @@

37194

37195

if (decl

37196

&& (DECL_CLASS_TEMPLATE_P (decl)

37197

- || DECL_TEMPLATE_TEMPLATE_PARM_P (decl)))

37198

+ /* If scope is ts_current we're defining a class, so ignore a

37199

+ template template parameter. */

37200

+ || (scope != ts_current

37201

+ && DECL_TEMPLATE_TEMPLATE_PARM_P (decl))))

37202

decl = DECL_TEMPLATE_RESULT (decl);

37203

37204

if (decl && TREE_CODE (decl) == TYPE_DECL)

37205

Index: gcc/cp/except.c

37206

===================================================================

37207

--- a/src/gcc/cp/except.c (.../tags/gcc_4_8_2_release)

37208

+++ b/src/gcc/cp/except.c (.../branches/gcc-4_8-branch)

37209

@@ -380,6 +380,9 @@

37210

{

37211

tree type = body ? TREE_TYPE (body) : void_type_node;

37212

37213

+ if (!flag_exceptions)

37214

+ return body;

37215

+

37216

if (cond && !value_dependent_expression_p (cond))

37217

{

37218

cond = cxx_constant_value (cond);

37219

Index: gcc/cp/ChangeLog

37220

===================================================================

37221

--- a/src/gcc/cp/ChangeLog (.../tags/gcc_4_8_2_release)

37222

+++ b/src/gcc/cp/ChangeLog (.../branches/gcc-4_8-branch)

37223

@@ -1,3 +1,251 @@

37224

+2014-04-28 Daniel Gutson <daniel.gutson@tallertechnologies.com>

37225

+

37226

+ * typeck.c (build_reinterpret_cast_1): Pass proper argument to

37227

+ warn() in pedantic.

37228

+

37229

+2014-02-28 Jason Merrill <jason@redhat.com>

37230

+

37231

+ PR c++/58845

37232

+ * typeck.c (cp_build_binary_op): Sorry on vector&&vector.

37233

+

37234

+2014-02-26 Jason Merrill <jason@redhat.com>

37235

+

37236

+ PR c++/60182

37237

+ * pt.c (unify): Ignore alias templates when deducing a template

37238

+ template parameter.

37239

+

37240

+2014-02-24 Jason Merrill <jason@redhat.com>

37241

+

37242

+ PR c++/60146

37243

+ * pt.c (tsubst_omp_for_iterator): Don't let substitution of the

37244

+ DECL_EXPR initialize a non-class iterator.

37245

+

37246

+2014-02-24 Fabien Chêne <fabien@gcc.gnu.org>

37247

+ PR c++/37140

37248

+ * parser.c (cp_parser_nonclass_name): Call strip_using_decl and

37249

+ move the code handling dependent USING_DECLs...

37250

+ * name-lookup.c (strip_using_decl): ...Here.

37251

+

37252

+2014-02-21 Jason Merrill <jason@redhat.com>

37253

+

37254

+ PR c++/60108

37255

+ * semantics.c (expand_or_defer_fn_1): Check DECL_DEFAULTED_FN.

37256

+

37257

+ PR c++/60187

37258

+ * parser.c (cp_parser_enum_specifier): Call

37259

+ check_for_bare_parameter_packs.

37260

+

37261

+ PR c++/60216

37262

+ * pt.c (register_specialization): Copy DECL_DELETED_FN to clones.

37263

+

37264

+ PR c++/60219

37265

+ * pt.c (coerce_template_parms): Bail if argument packing fails.

37266

+

37267

+ PR c++/60248

37268

+ * mangle.c (mangle_decl): Don't make an alias for a TYPE_DECL.

37269

+

37270

+2014-02-20 Jason Merrill <jason@redhat.com>

37271

+

37272

+ PR c++/60274

37273

+ Revert:

37274

+ PR c++/58606

37275

+ * pt.c (template_parm_to_arg): Call convert_from_reference.

37276

+ (tsubst_template_arg): Don't strip reference refs.

37277

+

37278

+2014-02-20 Kai Tietz <ktietz@redhat.com>

37279

+

37280

+ PR c++/58873

37281

+ * parser.c (cp_parser_functional_cast): Treat NULL_TREE

37282

+ valued type argument as error_mark_node.

37283

+

37284

+ PR c++/58835

37285

+ * semantics.c (finish_fname): Handle error_mark_node.

37286

+

37287

+2014-02-19 Jason Merrill <jason@redhat.com>

37288

+

37289

+ PR c++/60046

37290

+ * pt.c (maybe_instantiate_noexcept): Don't instantiate exception

37291

+ spec from template context.

37292

+

37293

+2014-01-31 Jason Merrill <jason@redhat.com>

37294

+

37295

+ PR c++/58672

37296

+ * decl2.c (handle_tls_init): Handle null init fn.

37297

+

37298

+ PR c++/55800

37299

+ * decl2.c (get_tls_init_fn): Copy DECL_EXTERNAL from the variable.

37300

+

37301

+ PR c++/59646

37302

+ * call.c (convert_like_real) [ck_aggr]: Set TARGET_EXPR_LIST_INIT_P.

37303

+ [ck_list]: Check for error_mark_node.

37304

+

37305

+ PR c++/57043

37306

+ * pt.c (fn_type_unification): Don't do DEDUCE_EXACT check

37307

+ during partial ordering.

37308

+

37309

+2014-01-30 Jason Merrill <jason@redhat.com>

37310

+

37311

+ PR c++/57899

37312

+ * pt.c (instantiate_template_1): Save/restore local_specializations.

37313

+

37314

+2014-01-29 Jason Merrill <jason@redhat.com>

37315

+

37316

+ PR c++/59989

37317

+ * pt.c (expand_template_argument_pack): Correct

37318

+ non_default_args_count calculation.

37319

+

37320

+ PR c++/58466

37321

+ * pt.c (unify_pack_expansion): Call expand_template_argument_pack.

37322

+

37323

+2014-01-28 Jason Merrill <jason@redhat.com>

37324

+

37325

+ PR c++/58632

37326

+ * decl.c (lookup_and_check_tag): Ignore template parameters if

37327

+ scope == ts_current.

37328

+ * pt.c (check_template_shadow): Don't complain about the injected

37329

+ class name.

37330

+

37331

+2014-01-27 Jason Merrill <jason@redhat.com>

37332

+

37333

+ PR c++/54652

37334

+ * decl.c (duplicate_decls): Always use oldtype for TYPE_DECL.

37335

+

37336

+ PR c++/58504

37337

+ * pt.c (tsubst_copy_and_build) [TRAIT_EXPR]: Use tsubst for

37338

+ types.

37339

+

37340

+ PR c++/58606

37341

+ * pt.c (template_parm_to_arg): Call convert_from_reference.

37342

+ (tsubst_template_arg): Don't strip reference refs.

37343

+

37344

+ PR c++/58639

37345

+ * call.c (build_aggr_conv): Reject value-initialization of reference.

37346

+

37347

+ PR c++/58812

37348

+ * call.c (convert_like_real): Give helpful error about excess braces

37349

+ for reference binding, too.

37350

+

37351

+ PR c++/58814

37352

+ * typeck.c (cp_build_modify_expr): Make the RHS an rvalue before

37353

+ stabilizing.

37354

+

37355

+ PR c++/58837

37356

+ * typeck.c (cp_truthvalue_conversion): Use explicit comparison for

37357

+ FUNCTION_DECL.

37358

+

37359

+ PR c++/59097

37360

+ * decl.c (compute_array_index_type): Don't call

37361

+ maybe_constant_value for a non-integral expression.

37362

+

37363

+ PR c++/58965

37364

+ * mangle.c (write_guarded_var_name): Handle null DECL_NAME.

37365

+

37366

+2014-01-24 Paolo Carlini <paolo.carlini@oracle.com>

37367

+

37368

+ PR c++/57524

37369

+ * name-lookup.c (push_using_directive): Use timevar_cond_start.

37370

+

37371

+2014-01-23 Jakub Jelinek <jakub@redhat.com>

37372

+

37373

+ PR middle-end/58809

37374

+ * semantics.c (finish_omp_clauses): Reject MIN_EXPR, MAX_EXPR,

37375

+ BIT_AND_EXPR, BIT_IOR_EXPR and BIT_XOR_EXPR on COMPLEX_TYPEs.

37376

+

37377

+2014-01-20 Marek Polacek <polacek@redhat.com>

37378

+

37379

+ Backported from mainline

37380

+ 2014-01-17 Marek Polacek <polacek@redhat.com>

37381

+

37382

+ PR c++/59838

37383

+ * cvt.c (ocp_convert): Don't segfault on non-existing

37384

+ ENUM_UNDERLYING_TYPE.

37385

+

37386

+2014-01-10 Paolo Carlini <paolo.carlini@oracle.com>

37387

+

37388

+ PR c++/56060

37389

+ PR c++/59730

37390

+ * pt.c (type_dependent_expression_p): Handle EXPR_PACK_EXPANSION.

37391

+

37392

+2013-12-12 Jason Merrill <jason@redhat.com>

37393

+

37394

+ PR c++/58954

37395

+ * pt.c (resolve_overloaded_unification): Discard access checks.

37396

+

37397

+2013-12-05 Jason Merrill <jason@redhat.com>

37398

+

37399

+ PR c++/59044

37400

+ PR c++/59052

37401

+ * pt.c (most_specialized_class): Use the partially instantiated

37402

+ template for deduction. Drop the TMPL parameter.

37403

+

37404

+2013-12-04 Jakub Jelinek <jakub@redhat.com>

37405

+

37406

+ PR c++/59268

37407

+ * pt.c (tsubst_copy_and_build): Handle POINTER_PLUS_EXPR.

37408

+

37409

+2013-11-27 Tom de Vries <tom@codesourcery.com>

37410

+ Marc Glisse <marc.glisse@inria.fr>

37411

+

37412

+ PR c++/59032

37413

+ * typeck.c (cp_build_unary_op): Allow vector increment and decrement.

37414

+

37415

+2013-11-27 Tom de Vries <tom@codesourcery.com>

37416

+ Marc Glisse <marc.glisse@inria.fr>

37417

+

37418

+ PR middle-end/59037

37419

+ * semantics.c (cxx_fold_indirect_ref): Don't create out-of-bounds

37420

+ BIT_FIELD_REF.

37421

+

37422

+2013-11-28 Jakub Jelinek <jakub@redhat.com>

37423

+

37424

+ PR c++/59297

37425

+ * semantics.c (finish_omp_atomic): Call finish_expr_stmt

37426

+ rather than add_stmt.

37427

+

37428

+2013-11-23 Easwaran Raman <eraman@google.com>

37429

+

37430

+ PR c++/59031

37431

+ * call.c (build_new_method_call_1): Comnpare function context

37432

+ with BASELINK_BINFO type rather than instance type before

37433

+ marking the call with LOOKUP_NONVIRTUAL.

37434

+

37435

+2013-10-31 Jason Merrill <jason@redhat.com>

37436

+

37437

+ PR c++/58162

37438

+ * parser.c (cp_parser_late_parse_one_default_arg): Set

37439

+ TARGET_EXPR_DIRECT_INIT_P.

37440

+

37441

+2013-11-11 Paolo Carlini <paolo.carlini@oracle.com>

37442

+

37443

+ * cvt.c (cp_convert_to_pointer): Call build_ptrmemfunc before

37444

+ maybe_warn_zero_as_null_pointer_constant to avoid duplicate

37445

+ -Wzero-as-null-pointer-constant diagnostics.

37446

+

37447

+ * typeck.c (build_ptrmemfunc): Use cp_build_c_cast.

37448

+

37449

+2013-10-25 Tom de Vries <tom@codesourcery.com>

37450

+

37451

+ PR c++/58282

37452

+ * except.c (build_must_not_throw_expr): Handle

37453

+ flag_exceptions.

37454

+

37455

+2013-10-17 Paolo Carlini <paolo.carlini@oracle.com>

37456

+

37457

+ PR c++/58596

37458

+ * semantics.c (lambda_expr_this_capture): Handle NSDMIs in the

37459

+ cp_unevaluated_operand case.

37460

+

37461

+2013-10-16 Paolo Carlini <paolo.carlini@oracle.com>

37462

+

37463

+ PR c++/58633

37464

+ * parser.c (cp_parser_pseudo_destructor_name): Revert r174385 changes.

37465

+

37466

+2013-10-16 Jason Merrill <jason@redhat.com>

37467

+

37468

+ PR c++/57850

37469

+ * decl2.c (dump_tu): Split out from...

37470

+ (cp_write_global_declarations): ...here. Call it in PCH mode.

37471

+

37472

2013-10-16 Release Manager

37473

37474

* GCC 4.8.2 released.

37475

Index: gcc/cp/pt.c

37476

===================================================================

37477

--- a/src/gcc/cp/pt.c (.../tags/gcc_4_8_2_release)

37478

+++ b/src/gcc/cp/pt.c (.../branches/gcc-4_8-branch)

37479

@@ -170,7 +170,7 @@

37480

static tree tsubst_template_args (tree, tree, tsubst_flags_t, tree);

37481

static tree tsubst_template_parms (tree, tree, tsubst_flags_t);

37482

static void regenerate_decl_from_template (tree, tree);

37483

-static tree most_specialized_class (tree, tree, tsubst_flags_t);

37484

+static tree most_specialized_class (tree, tsubst_flags_t);

37485

static tree tsubst_aggr_type (tree, tree, tsubst_flags_t, tree, int);

37486

static tree tsubst_arg_types (tree, tree, tree, tsubst_flags_t, tree);

37487

static tree tsubst_function_type (tree, tree, tsubst_flags_t, tree);

37488

@@ -1419,6 +1419,8 @@

37489

= DECL_DECLARED_INLINE_P (fn);

37490

DECL_SOURCE_LOCATION (clone)

37491

= DECL_SOURCE_LOCATION (fn);

37492

+ DECL_DELETED_FN (clone)

37493

+ = DECL_DELETED_FN (fn);

37494

}

37495

check_specialization_namespace (tmpl);

37496

37497

@@ -3436,7 +3438,7 @@

37498

for (i = 0; i < num_packed; ++i, ++out_arg)

37499

TREE_VEC_ELT (result_args, out_arg) = TREE_VEC_ELT(packed, i);

37500

if (non_default_args_count > 0)

37501

- non_default_args_count += num_packed;

37502

+ non_default_args_count += num_packed - 1;

37503

}

37504

else

37505

{

37506

@@ -3491,6 +3493,11 @@

37507

|| TEMPLATE_PARMS_FOR_INLINE (current_template_parms))

37508

return true;

37509

37510

+ /* Don't complain about the injected class name, as we've already

37511

+ complained about the class itself. */

37512

+ if (DECL_SELF_REFERENCE_P (decl))

37513

+ return false;

37514

+

37515

error ("declaration of %q+#D", decl);

37516

error (" shadows template parm %q+#D", olddecl);

37517

return false;

37518

@@ -4261,7 +4268,7 @@

37519

if (COMPLETE_TYPE_P (inst_type)

37520

&& CLASSTYPE_IMPLICIT_INSTANTIATION (inst_type))

37521

{

37522

- tree spec = most_specialized_class (inst_type, maintmpl, tf_none);

37523

+ tree spec = most_specialized_class (inst_type, tf_none);

37524

if (spec && TREE_TYPE (spec) == type)

37525

permerror (input_location,

37526

"partial specialization of %qT after instantiation "

37527

@@ -6672,6 +6679,8 @@

37528

/* Store this argument. */

37529

if (arg == error_mark_node)

37530

lost++;

37531

+ if (lost)

37532

+ break;

37533

TREE_VEC_ELT (new_inner_args, parm_idx) = arg;

37534

37535

/* We are done with all of the arguments. */

37536

@@ -8572,7 +8581,7 @@

37537

37538

/* Determine what specialization of the original template to

37539

instantiate. */

37540

- t = most_specialized_class (type, templ, tf_warning_or_error);

37541

+ t = most_specialized_class (type, tf_warning_or_error);

37542

if (t == error_mark_node)

37543

{

37544

TYPE_BEING_DEFINED (type) = 1;

37545

@@ -12694,27 +12703,43 @@

37546

tsubst_expr ((NODE), args, complain, in_decl, \

37547

integral_constant_expression_p)

37548

tree decl, init, cond, incr;

37549

- bool init_decl;

37550

37551

init = TREE_VEC_ELT (OMP_FOR_INIT (t), i);

37552

gcc_assert (TREE_CODE (init) == MODIFY_EXPR);

37553

decl = TREE_OPERAND (init, 0);

37554

init = TREE_OPERAND (init, 1);

37555

- /* Do this before substituting into decl to handle 'auto'. */

37556

- init_decl = (init && TREE_CODE (init) == DECL_EXPR);

37557

- init = RECUR (init);

37558

- decl = RECUR (decl);

37559

- if (init_decl)

37560

+ tree decl_expr = NULL_TREE;

37561

+ if (init && TREE_CODE (init) == DECL_EXPR)

37562

{

37563

- gcc_assert (!processing_template_decl);

37564

- init = DECL_INITIAL (decl);

37565

- DECL_INITIAL (decl) = NULL_TREE;

37566

+ /* We need to jump through some hoops to handle declarations in the

37567

+ for-init-statement, since we might need to handle auto deduction,

37568

+ but we need to keep control of initialization. */

37569

+ decl_expr = init;

37570

+ init = DECL_INITIAL (DECL_EXPR_DECL (init));

37571

+ decl = tsubst_decl (decl, args, complain);

37572

}

37573

+ else

37574

+ decl = RECUR (decl);

37575

+ init = RECUR (init);

37576

37577

+ tree auto_node = type_uses_auto (TREE_TYPE (decl));

37578

+ if (auto_node && init)

37579

+ TREE_TYPE (decl)

37580

+ = do_auto_deduction (TREE_TYPE (decl), init, auto_node);

37581

+

37582

gcc_assert (!type_dependent_expression_p (decl));

37583

37584

if (!CLASS_TYPE_P (TREE_TYPE (decl)))

37585

{

37586

+ if (decl_expr)

37587

+ {

37588

+ /* Declare the variable, but don't let that initialize it. */

37589

+ tree init_sav = DECL_INITIAL (DECL_EXPR_DECL (decl_expr));

37590

+ DECL_INITIAL (DECL_EXPR_DECL (decl_expr)) = NULL_TREE;

37591

+ RECUR (decl_expr);

37592

+ DECL_INITIAL (DECL_EXPR_DECL (decl_expr)) = init_sav;

37593

+ }

37594

+

37595

cond = RECUR (TREE_VEC_ELT (OMP_FOR_COND (t), i));

37596

incr = TREE_VEC_ELT (OMP_FOR_INCR (t), i);

37597

if (TREE_CODE (incr) == MODIFY_EXPR)

37598

@@ -12731,8 +12756,14 @@

37599

return;

37600

}

37601

37602

- if (init && !init_decl)

37603

+ if (decl_expr)

37604

{

37605

+ /* Declare and initialize the variable. */

37606

+ RECUR (decl_expr);

37607

+ init = NULL_TREE;

37608

+ }

37609

+ else if (init)

37610

+ {

37611

tree c;

37612

for (c = *clauses; c ; c = OMP_CLAUSE_CHAIN (c))

37613

{

37614

@@ -13710,6 +13741,10 @@

37615

RETURN (r);

37616

}

37617

37618

+ case POINTER_PLUS_EXPR:

37619

+ return fold_build_pointer_plus (RECUR (TREE_OPERAND (t, 0)),

37620

+ RECUR (TREE_OPERAND (t, 1)));

37621

+

37622

case SCOPE_REF:

37623

RETURN (tsubst_qualified_id (t, args, complain, in_decl, /*done=*/true,

37624

/*address_p=*/false));

37625

@@ -14471,12 +14506,12 @@

37626

37627

case TRAIT_EXPR:

37628

{

37629

- tree type1 = tsubst_copy (TRAIT_EXPR_TYPE1 (t), args,

37630

- complain, in_decl);

37631

+ tree type1 = tsubst (TRAIT_EXPR_TYPE1 (t), args,

37632

+ complain, in_decl);

37633

37634

tree type2 = TRAIT_EXPR_TYPE2 (t);

37635

if (type2)

37636

- type2 = tsubst_copy (type2, args, complain, in_decl);

37637

+ type2 = tsubst (type2, args, complain, in_decl);

37638

37639

RETURN (finish_trait_expr (TRAIT_EXPR_KIND (t), type1, type2));

37640

}

37641

@@ -14778,6 +14813,8 @@

37642

/* Instantiation of the function happens in the context of the function

37643

template, not the context of the overload resolution we're doing. */

37644

push_to_top_level ();

37645

+ struct pointer_map_t *saved_local_specializations = local_specializations;

37646

+ local_specializations = NULL;

37647

/* If there are dependent arguments, e.g. because we're doing partial

37648

ordering, make sure processing_template_decl stays set. */

37649

if (uses_template_parms (targ_ptr))

37650

@@ -14793,6 +14830,7 @@

37651

targ_ptr, complain, gen_tmpl);

37652

if (DECL_CLASS_SCOPE_P (gen_tmpl))

37653

pop_nested_class ();

37654

+ local_specializations = saved_local_specializations;

37655

pop_from_top_level ();

37656

37657

if (fndecl == error_mark_node)

37658

@@ -15192,8 +15230,11 @@

37659

37660

/* If we're looking for an exact match, check that what we got

37661

is indeed an exact match. It might not be if some template

37662

- parameters are used in non-deduced contexts. */

37663

- if (strict == DEDUCE_EXACT)

37664

+ parameters are used in non-deduced contexts. But don't check

37665

+ for an exact match if we have dependent template arguments;

37666

+ in that case we're doing partial ordering, and we already know

37667

+ that we have two candidates that will provide the actual type. */

37668

+ if (strict == DEDUCE_EXACT && !any_dependent_template_arguments_p (targs))

37669

{

37670

tree substed = TREE_TYPE (decl);

37671

unsigned int i;

37672

@@ -15749,7 +15790,7 @@

37673

if (subargs != error_mark_node

37674

&& !any_dependent_template_arguments_p (subargs))

37675

{

37676

- elem = tsubst (TREE_TYPE (fn), subargs, tf_none, NULL_TREE);

37677

+ elem = TREE_TYPE (instantiate_template (fn, subargs, tf_none));

37678

if (try_one_overload (tparms, targs, tempargs, parm,

37679

elem, strict, sub_strict, addr_p, explain_p)

37680

&& (!goodfn || !same_type_p (goodfn, elem)))

37681

@@ -16207,6 +16248,9 @@

37682

tree pattern = PACK_EXPANSION_PATTERN (parm);

37683

tree pack, packs = NULL_TREE;

37684

int i, start = TREE_VEC_LENGTH (packed_parms) - 1;

37685

+

37686

+ packed_args = expand_template_argument_pack (packed_args);

37687

+

37688

int len = TREE_VEC_LENGTH (packed_args);

37689

37690

/* Determine the parameter packs we will be deducing from the

37691

@@ -16574,9 +16618,11 @@

37692

if (TREE_CODE (arg) != BOUND_TEMPLATE_TEMPLATE_PARM

37693

&& !CLASSTYPE_SPECIALIZATION_OF_PRIMARY_TEMPLATE_P (arg))

37694

return unify_template_deduction_failure (explain_p, parm, arg);

37695

-

37696

{

37697

tree parmvec = TYPE_TI_ARGS (parm);

37698

+ /* An alias template name is never deduced. */

37699

+ if (TYPE_ALIAS_P (arg))

37700

+ arg = strip_typedefs (arg);

37701

tree argvec = INNERMOST_TEMPLATE_ARGS (TYPE_TI_ARGS (arg));

37702

tree full_argvec = add_to_template_args (targs, argvec);

37703

tree parm_parms

37704

@@ -17553,7 +17599,7 @@

37705

return -1;

37706

}

37707

37708

-/* Determine which of two partial specializations of MAIN_TMPL is more

37709

+/* Determine which of two partial specializations of TMPL is more

37710

specialized.

37711

37712

PAT1 is a TREE_LIST whose TREE_TYPE is the _TYPE node corresponding

37713

@@ -17569,7 +17615,7 @@

37714

two templates is more specialized. */

37715

37716

static int

37717

-more_specialized_class (tree main_tmpl, tree pat1, tree pat2)

37718

+more_specialized_class (tree tmpl, tree pat1, tree pat2)

37719

{

37720

tree targs;

37721

tree tmpl1, tmpl2;

37722

@@ -17584,7 +17630,7 @@

37723

types in the arguments, and we need our dependency check functions

37724

to behave correctly. */

37725

++processing_template_decl;

37726

- targs = get_class_bindings (main_tmpl, TREE_VALUE (pat1),

37727

+ targs = get_class_bindings (tmpl, TREE_VALUE (pat1),

37728

CLASSTYPE_TI_ARGS (tmpl1),

37729

CLASSTYPE_TI_ARGS (tmpl2));

37730

if (targs)

37731

@@ -17593,7 +17639,7 @@

37732

any_deductions = true;

37733

}

37734

37735

- targs = get_class_bindings (main_tmpl, TREE_VALUE (pat2),

37736

+ targs = get_class_bindings (tmpl, TREE_VALUE (pat2),

37737

CLASSTYPE_TI_ARGS (tmpl2),

37738

CLASSTYPE_TI_ARGS (tmpl1));

37739

if (targs)

37740

@@ -17673,7 +17719,7 @@

37741

}

37742

37743

/* Return the innermost template arguments that, when applied to a partial

37744

- specialization of MAIN_TMPL whose innermost template parameters are

37745

+ specialization of TMPL whose innermost template parameters are

37746

TPARMS, and whose specialization arguments are SPEC_ARGS, yield the

37747

ARGS.

37748

37749

@@ -17688,7 +17734,7 @@

37750

is bound to `double'. */

37751

37752

static tree

37753

-get_class_bindings (tree main_tmpl, tree tparms, tree spec_args, tree args)

37754

+get_class_bindings (tree tmpl, tree tparms, tree spec_args, tree args)

37755

{

37756

int i, ntparms = TREE_VEC_LENGTH (tparms);

37757

tree deduced_args;

37758

@@ -17728,8 +17774,8 @@

37759

`T' is `A' but unify () does not check whether `typename T::X'

37760

is `int'. */

37761

spec_args = tsubst (spec_args, deduced_args, tf_none, NULL_TREE);

37762

- spec_args = coerce_template_parms (DECL_INNERMOST_TEMPLATE_PARMS (main_tmpl),

37763

- spec_args, main_tmpl,

37764

+ spec_args = coerce_template_parms (DECL_INNERMOST_TEMPLATE_PARMS (tmpl),

37765

+ spec_args, tmpl,

37766

tf_none, false, false);

37767

if (spec_args == error_mark_node

37768

/* We only need to check the innermost arguments; the other

37769

@@ -17877,8 +17923,8 @@

37770

}

37771

37772

/* Return the most specialized of the class template partial

37773

- specializations of TMPL which can produce TYPE, a specialization of

37774

- TMPL. The value returned is actually a TREE_LIST; the TREE_TYPE is

37775

+ specializations which can produce TYPE, a specialization of some class

37776

+ template. The value returned is actually a TREE_LIST; the TREE_TYPE is

37777

a _TYPE node corresponding to the partial specialization, while the

37778

TREE_PURPOSE is the set of template arguments that must be

37779

substituted into the TREE_TYPE in order to generate TYPE.

37780

@@ -17885,11 +17931,11 @@

37781

37782

If the choice of partial specialization is ambiguous, a diagnostic

37783

is issued, and the error_mark_node is returned. If there are no

37784

- partial specializations of TMPL matching TYPE, then NULL_TREE is

37785

- returned. */

37786

+ partial specializations matching TYPE, then NULL_TREE is

37787

+ returned, indicating that the primary template should be used. */

37788

37789

static tree

37790

-most_specialized_class (tree type, tree tmpl, tsubst_flags_t complain)

37791

+most_specialized_class (tree type, tsubst_flags_t complain)

37792

{

37793

tree list = NULL_TREE;

37794

tree t;

37795

@@ -17896,11 +17942,11 @@

37796

tree champ;

37797

int fate;

37798

bool ambiguous_p;

37799

- tree args;

37800

tree outer_args = NULL_TREE;

37801

37802

- tmpl = most_general_template (tmpl);

37803

- args = CLASSTYPE_TI_ARGS (type);

37804

+ tree tmpl = CLASSTYPE_TI_TEMPLATE (type);

37805

+ tree main_tmpl = most_general_template (tmpl);

37806

+ tree args = CLASSTYPE_TI_ARGS (type);

37807

37808

/* For determining which partial specialization to use, only the

37809

innermost args are interesting. */

37810

@@ -17910,7 +17956,7 @@

37811

args = INNERMOST_TEMPLATE_ARGS (args);

37812

}

37813

37814

- for (t = DECL_TEMPLATE_SPECIALIZATIONS (tmpl); t; t = TREE_CHAIN (t))

37815

+ for (t = DECL_TEMPLATE_SPECIALIZATIONS (main_tmpl); t; t = TREE_CHAIN (t))

37816

{

37817

tree partial_spec_args;

37818

tree spec_args;

37819

@@ -17944,8 +17990,7 @@

37820

37821

partial_spec_args =

37822

coerce_template_parms (DECL_INNERMOST_TEMPLATE_PARMS (tmpl),

37823

- add_to_template_args (outer_args,

37824

- partial_spec_args),

37825

+ partial_spec_args,

37826

tmpl, tf_none,

37827

/*require_all_args=*/true,

37828

/*use_default_args=*/true);

37829

@@ -18553,6 +18598,10 @@

37830

{

37831

tree fntype, spec, noex, clone;

37832

37833

+ /* Don't instantiate a noexcept-specification from template context. */

37834

+ if (processing_template_decl)

37835

+ return;

37836

+

37837

if (DECL_CLONED_FUNCTION_P (fn))

37838

fn = DECL_CLONED_FUNCTION (fn);

37839

fntype = TREE_TYPE (fn);

37840

@@ -19955,6 +20004,10 @@

37841

if (TREE_CODE (expression) == SCOPE_REF)

37842

return false;

37843

37844

+ /* Always dependent, on the number of arguments if nothing else. */

37845

+ if (TREE_CODE (expression) == EXPR_PACK_EXPANSION)

37846

+ return true;

37847

+

37848

if (BASELINK_P (expression))

37849

expression = BASELINK_FUNCTIONS (expression);

37850

37851

Index: gcc/cp/semantics.c

37852

===================================================================

37853

--- a/src/gcc/cp/semantics.c (.../tags/gcc_4_8_2_release)

37854

+++ b/src/gcc/cp/semantics.c (.../branches/gcc-4_8-branch)

37855

@@ -2501,7 +2501,8 @@

37856

tree decl;

37857

37858

decl = fname_decl (input_location, C_RID_CODE (id), id);

37859

- if (processing_template_decl && current_function_decl)

37860

+ if (processing_template_decl && current_function_decl

37861

+ && decl != error_mark_node)

37862

decl = DECL_NAME (decl);

37863

return decl;

37864

}

37865

@@ -3853,7 +3854,7 @@

37866

linkage of all functions, and as that causes writes to

37867

the data mapped in from the PCH file, it's advantageous

37868

to mark the functions at this point. */

37869

- if (!DECL_IMPLICIT_INSTANTIATION (fn))

37870

+ if (!DECL_IMPLICIT_INSTANTIATION (fn) || DECL_DEFAULTED_FN (fn))

37871

{

37872

/* This function must have external linkage, as

37873

otherwise DECL_INTERFACE_KNOWN would have been

37874

@@ -4291,7 +4292,8 @@

37875

error ("%qE has invalid type for %<reduction%>", t);

37876

remove = true;

37877

}

37878

- else if (FLOAT_TYPE_P (TREE_TYPE (t)))

37879

+ else if (FLOAT_TYPE_P (TREE_TYPE (t))

37880

+ || TREE_CODE (TREE_TYPE (t)) == COMPLEX_TYPE)

37881

{

37882

enum tree_code r_code = OMP_CLAUSE_REDUCTION_CODE (c);

37883

switch (r_code)

37884

@@ -4299,10 +4301,26 @@

37885

case PLUS_EXPR:

37886

case MULT_EXPR:

37887

case MINUS_EXPR:

37888

+ break;

37889

case MIN_EXPR:

37890

case MAX_EXPR:

37891

+ if (TREE_CODE (TREE_TYPE (t)) == COMPLEX_TYPE)

37892

+ r_code = ERROR_MARK;

37893

break;

37894

+ case BIT_AND_EXPR:

37895

+ case BIT_XOR_EXPR:

37896

+ case BIT_IOR_EXPR:

37897

default:

37898

+ r_code = ERROR_MARK;

37899

+ break;

37900

+ case TRUTH_ANDIF_EXPR:

37901

+ case TRUTH_ORIF_EXPR:

37902

+ if (FLOAT_TYPE_P (TREE_TYPE (t)))

37903

+ r_code = ERROR_MARK;

37904

+ break;

37905

+ }

37906

+ if (r_code == ERROR_MARK)

37907

+ {

37908

error ("%qE has invalid type for %<reduction(%s)%>",

37909

t, operator_name_info[r_code].name);

37910

remove = true;

37911

@@ -5059,7 +5077,7 @@

37912

}

37913

stmt = build2 (OMP_ATOMIC, void_type_node, integer_zero_node, stmt);

37914

}

37915

- add_stmt (stmt);

37916

+ finish_expr_stmt (stmt);

37917

}

37918

37919

void

37920

@@ -7543,7 +7561,7 @@

37921

unsigned HOST_WIDE_INT indexi = offset * BITS_PER_UNIT;

37922

tree index = bitsize_int (indexi);

37923

37924

- if (offset/part_widthi <= TYPE_VECTOR_SUBPARTS (op00type))

37925

+ if (offset / part_widthi < TYPE_VECTOR_SUBPARTS (op00type))

37926

return fold_build3_loc (loc,

37927

BIT_FIELD_REF, type, op00,

37928

part_width, index);

37929

@@ -9481,7 +9499,14 @@

37930

/* In unevaluated context this isn't an odr-use, so just return the

37931

nearest 'this'. */

37932

if (cp_unevaluated_operand)

37933

- return lookup_name (this_identifier);

37934

+ {

37935

+ /* In an NSDMI the fake 'this' pointer that we're using for

37936

+ parsing is in scope_chain. */

37937

+ if (LAMBDA_EXPR_EXTRA_SCOPE (lambda)

37938

+ && TREE_CODE (LAMBDA_EXPR_EXTRA_SCOPE (lambda)) == FIELD_DECL)

37939

+ return scope_chain->x_current_class_ptr;

37940

+ return lookup_name (this_identifier);

37941

+ }

37942

37943

/* Try to default capture 'this' if we can. */

37944

if (!this_capture

37945

Index: gcc/cp/decl2.c

37946

===================================================================

37947

--- a/src/gcc/cp/decl2.c (.../tags/gcc_4_8_2_release)

37948

+++ b/src/gcc/cp/decl2.c (.../branches/gcc-4_8-branch)

37949

@@ -2884,7 +2884,7 @@

37950

TREE_PUBLIC (fn) = TREE_PUBLIC (var);

37951

DECL_ARTIFICIAL (fn) = true;

37952

DECL_COMDAT (fn) = DECL_COMDAT (var);

37953

- DECL_EXTERNAL (fn) = true;

37954

+ DECL_EXTERNAL (fn) = DECL_EXTERNAL (var);

37955

if (DECL_ONE_ONLY (var))

37956

make_decl_one_only (fn, cxx_comdat_group (fn));

37957

if (TREE_PUBLIC (var))

37958

@@ -3946,6 +3946,8 @@

37959

if (TREE_PUBLIC (var))

37960

{

37961

tree single_init_fn = get_tls_init_fn (var);

37962

+ if (single_init_fn == NULL_TREE)

37963

+ continue;

37964

cgraph_node *alias

37965

= cgraph_same_body_alias (cgraph_get_create_node (fn),

37966

single_init_fn, fn);

37967

@@ -3960,6 +3962,22 @@

37968

expand_or_defer_fn (finish_function (0));

37969

}

37970

37971

+/* The entire file is now complete. If requested, dump everything

37972

+ to a file. */

37973

+

37974

+static void

37975

+dump_tu (void)

37976

+{

37977

+ int flags;

37978

+ FILE *stream = dump_begin (TDI_tu, &flags);

37979

+

37980

+ if (stream)

37981

+ {

37982

+ dump_node (global_namespace, flags & ~TDF_SLIM, stream);

37983

+ dump_end (TDI_tu, stream);

37984

+ }

37985

+}

37986

+

37987

/* This routine is called at the end of compilation.

37988

Its job is to create all the code needed to initialize and

37989

destroy the global aggregates. We do the destruction

37990

@@ -3990,6 +4008,7 @@

37991

if (pch_file)

37992

{

37993

c_common_write_pch ();

37994

+ dump_tu ();

37995

return;

37996

}

37997

37998

@@ -4359,17 +4378,8 @@

37999

38000

/* The entire file is now complete. If requested, dump everything

38001

to a file. */

38002

- {

38003

- int flags;

38004

- FILE *stream = dump_begin (TDI_tu, &flags);

38005

+ dump_tu ();

38006

38007

- if (stream)

38008

- {

38009

- dump_node (global_namespace, flags & ~TDF_SLIM, stream);

38010

- dump_end (TDI_tu, stream);

38011

- }

38012

- }

38013

-

38014

if (flag_detailed_statistics)

38015

{

38016

dump_tree_statistics ();

38017

Index: gcc/cp/parser.c

38018

===================================================================

38019

--- a/src/gcc/cp/parser.c (.../tags/gcc_4_8_2_release)

38020

+++ b/src/gcc/cp/parser.c (.../branches/gcc-4_8-branch)

38021

@@ -6421,10 +6421,6 @@

38022

/* Look for the `~'. */

38023

cp_parser_require (parser, CPP_COMPL, RT_COMPL);

38024

38025

- /* Once we see the ~, this has to be a pseudo-destructor. */

38026

- if (!processing_template_decl && !cp_parser_error_occurred (parser))

38027

- cp_parser_commit_to_tentative_parse (parser);

38028

-

38029

/* Look for the type-name again. We are not responsible for

38030

checking that it matches the first type-name. */

38031

*type = cp_parser_nonclass_name (parser);

38032

@@ -14168,25 +14164,7 @@

38033

/* Look up the type-name. */

38034

type_decl = cp_parser_lookup_name_simple (parser, identifier, token->location);

38035

38036

- if (TREE_CODE (type_decl) == USING_DECL)

38037

- {

38038

- if (!DECL_DEPENDENT_P (type_decl))

38039

- type_decl = strip_using_decl (type_decl);

38040

- else if (USING_DECL_TYPENAME_P (type_decl))

38041

- {

38042

- /* We have found a type introduced by a using

38043

- declaration at class scope that refers to a dependent

38044

- type.

38045

-

38046

- using typename :: [opt] nested-name-specifier unqualified-id ;

38047

- */

38048

- type_decl = make_typename_type (TREE_TYPE (type_decl),

38049

- DECL_NAME (type_decl),

38050

- typename_type, tf_error);

38051

- if (type_decl != error_mark_node)

38052

- type_decl = TYPE_NAME (type_decl);

38053

- }

38054

- }

38055

+ type_decl = strip_using_decl (type_decl);

38056

38057

if (TREE_CODE (type_decl) != TYPE_DECL

38058

&& (objc_is_id (identifier) || objc_is_class_name (identifier)))

38059

@@ -14742,7 +14720,8 @@

38060

{

38061

underlying_type = grokdeclarator (NULL, &type_specifiers, TYPENAME,

38062

/*initialized=*/0, NULL);

38063

- if (underlying_type == error_mark_node)

38064

+ if (underlying_type == error_mark_node

38065

+ || check_for_bare_parameter_packs (underlying_type))

38066

underlying_type = NULL_TREE;

38067

}

38068

}

38069

@@ -22209,6 +22188,9 @@

38070

tree cast;

38071

bool nonconst_p;

38072

38073

+ if (!type)

38074

+ type = error_mark_node;

38075

+

38076

if (cp_lexer_next_token_is (parser->lexer, CPP_OPEN_BRACE))

38077

{

38078

maybe_warn_cpp0x (CPP0X_INITIALIZER_LISTS);

38079

@@ -22576,6 +22558,9 @@

38080

&& CONSTRUCTOR_IS_DIRECT_INIT (parsed_arg))

38081

flags = LOOKUP_NORMAL;

38082

parsed_arg = digest_init_flags (TREE_TYPE (decl), parsed_arg, flags);

38083

+ if (TREE_CODE (parsed_arg) == TARGET_EXPR)

38084

+ /* This represents the whole initialization. */

38085

+ TARGET_EXPR_DIRECT_INIT_P (parsed_arg) = true;

38086

}

38087

}

38088

38089

Index: gcc/cp/call.c

38090

===================================================================

38091

--- a/src/gcc/cp/call.c (.../tags/gcc_4_8_2_release)

38092

+++ b/src/gcc/cp/call.c (.../branches/gcc-4_8-branch)

38093

@@ -892,6 +892,9 @@

38094

38095

if (i < CONSTRUCTOR_NELTS (ctor))

38096

val = CONSTRUCTOR_ELT (ctor, i)->value;

38097

+ else if (TREE_CODE (ftype) == REFERENCE_TYPE)

38098

+ /* Value-initialization of reference is ill-formed. */

38099

+ return NULL;

38100

else

38101

{

38102

if (empty_ctor == NULL_TREE)

38103

@@ -5806,9 +5809,11 @@

38104

&& convs->kind != ck_ambig

38105

&& (convs->kind != ck_ref_bind

38106

|| convs->user_conv_p)

38107

- && convs->kind != ck_rvalue

38108

+ && (convs->kind != ck_rvalue

38109

+ || SCALAR_TYPE_P (totype))

38110

&& convs->kind != ck_base)

38111

{

38112

+ bool complained = false;

38113

conversion *t = convs;

38114

38115

/* Give a helpful error if this is bad because of excess braces. */

38116

@@ -5816,7 +5821,14 @@

38117

&& SCALAR_TYPE_P (totype)

38118

&& CONSTRUCTOR_NELTS (expr) > 0

38119

&& BRACE_ENCLOSED_INITIALIZER_P (CONSTRUCTOR_ELT (expr, 0)->value))

38120

- permerror (loc, "too many braces around initializer for %qT", totype);

38121

+ {

38122

+ complained = true;

38123

+ permerror (loc, "too many braces around initializer "

38124

+ "for %qT", totype);

38125

+ while (BRACE_ENCLOSED_INITIALIZER_P (expr)

38126

+ && CONSTRUCTOR_NELTS (expr) == 1)

38127

+ expr = CONSTRUCTOR_ELT (expr, 0)->value;

38128

+ }

38129

38130

for (; t ; t = next_conversion (t))

38131

{

38132

@@ -5853,8 +5865,9 @@

38133

break;

38134

}

38135

38136

- permerror (loc, "invalid conversion from %qT to %qT",

38137

- TREE_TYPE (expr), totype);

38138

+ if (!complained)

38139

+ permerror (loc, "invalid conversion from %qT to %qT",

38140

+ TREE_TYPE (expr), totype);

38141

if (fn)

38142

permerror (DECL_SOURCE_LOCATION (fn),

38143

" initializing argument %P of %qD", argnum, fn);

38144

@@ -5999,6 +6012,8 @@

38145

to avoid the error about taking the address of a temporary. */

38146

array = cp_build_addr_expr (array, complain);

38147

array = cp_convert (build_pointer_type (elttype), array, complain);

38148

+ if (array == error_mark_node)

38149

+ return error_mark_node;

38150

38151

/* Build up the initializer_list object. */

38152

totype = complete_type (totype);

38153

@@ -6023,8 +6038,11 @@

38154

return fold_if_not_in_template (expr);

38155

}

38156

expr = reshape_init (totype, expr, complain);

38157

- return get_target_expr_sfinae (digest_init (totype, expr, complain),

38158

+ expr = get_target_expr_sfinae (digest_init (totype, expr, complain),

38159

complain);

38160

+ if (expr != error_mark_node)

38161

+ TARGET_EXPR_LIST_INIT_P (expr) = true;

38162

+ return expr;

38163

38164

default:

38165

break;

38166

@@ -7414,7 +7432,7 @@

38167

struct z_candidate *candidates = 0, *cand;

38168

tree explicit_targs = NULL_TREE;

38169

tree basetype = NULL_TREE;

38170

- tree access_binfo;

38171

+ tree access_binfo, binfo;

38172

tree optype;

38173

tree first_mem_arg = NULL_TREE;

38174

tree instance_ptr;

38175

@@ -7454,6 +7472,7 @@

38176

if (!conversion_path)

38177

conversion_path = BASELINK_BINFO (fns);

38178

access_binfo = BASELINK_ACCESS_BINFO (fns);

38179

+ binfo = BASELINK_BINFO (fns);

38180

optype = BASELINK_OPTYPE (fns);

38181

fns = BASELINK_FUNCTIONS (fns);

38182

if (TREE_CODE (fns) == TEMPLATE_ID_EXPR)

38183

@@ -7697,13 +7716,13 @@

38184

{

38185

/* Optimize away vtable lookup if we know that this

38186

function can't be overridden. We need to check if

38187

- the context and the instance type are the same,

38188

+ the context and the type where we found fn are the same,

38189

actually FN might be defined in a different class

38190

type because of a using-declaration. In this case, we

38191

do not want to perform a non-virtual call. */

38192

if (DECL_VINDEX (fn) && ! (flags & LOOKUP_NONVIRTUAL)

38193

&& same_type_ignoring_top_level_qualifiers_p

38194

- (DECL_CONTEXT (fn), TREE_TYPE (instance))

38195

+ (DECL_CONTEXT (fn), BINFO_TYPE (binfo))

38196

&& resolves_to_fixed_type_p (instance, 0))

38197

flags |= LOOKUP_NONVIRTUAL;

38198

if (explicit_targs)

38199

Index: gcc/cp/cvt.c

38200

===================================================================

38201

--- a/src/gcc/cp/cvt.c (.../tags/gcc_4_8_2_release)

38202

+++ b/src/gcc/cp/cvt.c (.../branches/gcc-4_8-branch)

38203

@@ -203,13 +203,13 @@

38204

38205

if (null_ptr_cst_p (expr))

38206

{

38207

- if (complain & tf_warning)

38208

- maybe_warn_zero_as_null_pointer_constant (expr, loc);

38209

-

38210

if (TYPE_PTRMEMFUNC_P (type))

38211

return build_ptrmemfunc (TYPE_PTRMEMFUNC_FN_TYPE (type), expr, 0,

38212

/*c_cast_p=*/false, complain);

38213

38214

+ if (complain & tf_warning)

38215

+ maybe_warn_zero_as_null_pointer_constant (expr, loc);

38216

+

38217

/* A NULL pointer-to-data-member is represented by -1, not by

38218

zero. */

38219

tree val = (TYPE_PTRDATAMEM_P (type)

38220

@@ -743,6 +743,7 @@

38221

unspecified. */

38222

if ((complain & tf_warning)

38223

&& TREE_CODE (e) == INTEGER_CST

38224

+ && ENUM_UNDERLYING_TYPE (type)

38225

&& !int_fits_type_p (e, ENUM_UNDERLYING_TYPE (type)))

38226

warning_at (loc, OPT_Wconversion,

38227

"the result of the conversion is unspecified because "

38228

Index: gcc/cp/mangle.c

38229

===================================================================

38230

--- a/src/gcc/cp/mangle.c (.../tags/gcc_4_8_2_release)

38231

+++ b/src/gcc/cp/mangle.c (.../branches/gcc-4_8-branch)

38232

@@ -3478,6 +3478,7 @@

38233

38234

if (G.need_abi_warning

38235

/* Don't do this for a fake symbol we aren't going to emit anyway. */

38236

+ && TREE_CODE (decl) != TYPE_DECL

38237

&& !DECL_MAYBE_IN_CHARGE_CONSTRUCTOR_P (decl)

38238

&& !DECL_MAYBE_IN_CHARGE_DESTRUCTOR_P (decl))

38239

{

38240

@@ -3773,7 +3774,8 @@

38241

static void

38242

write_guarded_var_name (const tree variable)

38243

{

38244

- if (strncmp (IDENTIFIER_POINTER (DECL_NAME (variable)), "_ZGR", 4) == 0)

38245

+ if (DECL_NAME (variable)

38246

+ && strncmp (IDENTIFIER_POINTER (DECL_NAME (variable)), "_ZGR", 4) == 0)

38247

/* The name of a guard variable for a reference temporary should refer

38248

to the reference, not the temporary. */

38249

write_string (IDENTIFIER_POINTER (DECL_NAME (variable)) + 4);

38250

Index: gcc/cp/cp-tree.h

38251

===================================================================

38252

--- a/src/gcc/cp/cp-tree.h (.../tags/gcc_4_8_2_release)

38253

+++ b/src/gcc/cp/cp-tree.h (.../branches/gcc-4_8-branch)

38254

@@ -344,7 +344,8 @@

38255

/* Returns true iff NODE is a BASELINK. */

38256

#define BASELINK_P(NODE) \

38257

(TREE_CODE (NODE) == BASELINK)

38258

-/* The BINFO indicating the base from which the BASELINK_FUNCTIONS came. */

38259

+/* The BINFO indicating the base in which lookup found the

38260

+ BASELINK_FUNCTIONS. */

38261

#define BASELINK_BINFO(NODE) \

38262

(((struct tree_baselink*) BASELINK_CHECK (NODE))->binfo)

38263

/* The functions referred to by the BASELINK; either a FUNCTION_DECL,

38264

Index: gcc/cp/name-lookup.c

38265

===================================================================

38266

--- a/src/gcc/cp/name-lookup.c (.../tags/gcc_4_8_2_release)

38267

+++ b/src/gcc/cp/name-lookup.c (.../branches/gcc-4_8-branch)

38268

@@ -394,7 +394,8 @@

38269

}

38270

}

38271

38272

-/* Strip non dependent using declarations. */

38273

+/* Strip non dependent using declarations. If DECL is dependent,

38274

+ surreptitiously create a typename_type and return it. */

38275

38276

tree

38277

strip_using_decl (tree decl)

38278

@@ -404,6 +405,23 @@

38279

38280

while (TREE_CODE (decl) == USING_DECL && !DECL_DEPENDENT_P (decl))

38281

decl = USING_DECL_DECLS (decl);

38282

+

38283

+ if (TREE_CODE (decl) == USING_DECL && DECL_DEPENDENT_P (decl)

38284

+ && USING_DECL_TYPENAME_P (decl))

38285

+ {

38286

+ /* We have found a type introduced by a using

38287

+ declaration at class scope that refers to a dependent

38288

+ type.

38289

+

38290

+ using typename :: [opt] nested-name-specifier unqualified-id ;

38291

+ */

38292

+ decl = make_typename_type (TREE_TYPE (decl),

38293

+ DECL_NAME (decl),

38294

+ typename_type, tf_error);

38295

+ if (decl != error_mark_node)

38296

+ decl = TYPE_NAME (decl);

38297

+ }

38298

+

38299

return decl;

38300

}

38301

38302

@@ -5605,9 +5623,9 @@

38303

push_using_directive (tree used)

38304

{

38305

tree ret;

38306

- timevar_start (TV_NAME_LOOKUP);

38307

+ bool subtime = timevar_cond_start (TV_NAME_LOOKUP);

38308

ret = push_using_directive_1 (used);

38309

- timevar_stop (TV_NAME_LOOKUP);

38310

+ timevar_cond_stop (TV_NAME_LOOKUP, subtime);

38311

return ret;

38312

}

38313

38314

Index: gcc/builtins.def

38315

===================================================================

38316

--- a/src/gcc/builtins.def (.../tags/gcc_4_8_2_release)

38317

+++ b/src/gcc/builtins.def (.../branches/gcc-4_8-branch)

38318

@@ -252,6 +252,9 @@

38319

DEF_LIB_BUILTIN (BUILT_IN_FABS, "fabs", BT_FN_DOUBLE_DOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST)

38320

DEF_C99_C90RES_BUILTIN (BUILT_IN_FABSF, "fabsf", BT_FN_FLOAT_FLOAT, ATTR_CONST_NOTHROW_LEAF_LIST)

38321

DEF_C99_C90RES_BUILTIN (BUILT_IN_FABSL, "fabsl", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST)

38322

+DEF_GCC_BUILTIN (BUILT_IN_FABSD32, "fabsd32", BT_FN_DFLOAT32_DFLOAT32, ATTR_CONST_NOTHROW_LEAF_LIST)

38323

+DEF_GCC_BUILTIN (BUILT_IN_FABSD64, "fabsd64", BT_FN_DFLOAT64_DFLOAT64, ATTR_CONST_NOTHROW_LEAF_LIST)

38324

+DEF_GCC_BUILTIN (BUILT_IN_FABSD128, "fabsd128", BT_FN_DFLOAT128_DFLOAT128, ATTR_CONST_NOTHROW_LEAF_LIST)

38325

DEF_C99_BUILTIN (BUILT_IN_FDIM, "fdim", BT_FN_DOUBLE_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO)

38326

DEF_C99_BUILTIN (BUILT_IN_FDIMF, "fdimf", BT_FN_FLOAT_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO)

38327

DEF_C99_BUILTIN (BUILT_IN_FDIML, "fdiml", BT_FN_LONGDOUBLE_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO)

38328

Index: gcc/mode-switching.c

38329

===================================================================

38330

--- a/src/gcc/mode-switching.c (.../tags/gcc_4_8_2_release)

38331

+++ b/src/gcc/mode-switching.c (.../branches/gcc-4_8-branch)

38332

@@ -568,12 +568,15 @@

38333

38334

info[bb->index].computing = last_mode;

38335

/* Check for blocks without ANY mode requirements.

38336

- N.B. because of MODE_AFTER, last_mode might still be different

38337

- from no_mode. */

38338

+ N.B. because of MODE_AFTER, last_mode might still

38339

+ be different from no_mode, in which case we need to

38340

+ mark the block as nontransparent. */

38341

if (!any_set_required)

38342

{

38343

ptr = new_seginfo (no_mode, BB_END (bb), bb->index, live_now);

38344

add_seginfo (info + bb->index, ptr);

38345

+ if (last_mode != no_mode)

38346

+ bitmap_clear_bit (transp[bb->index], j);

38347

}

38348

}

38349

#if defined (MODE_ENTRY) && defined (MODE_EXIT)

38350

Index: gcc/ipa-pure-const.c

38351

===================================================================

38352

--- a/src/gcc/ipa-pure-const.c (.../tags/gcc_4_8_2_release)

38353

+++ b/src/gcc/ipa-pure-const.c (.../branches/gcc-4_8-branch)

38354

@@ -588,7 +588,7 @@

38355

/* Wrapper around check_decl for loads in local more. */

38356

38357

static bool

38358

-check_load (gimple stmt ATTRIBUTE_UNUSED, tree op, void *data)

38359

+check_load (gimple, tree op, tree, void *data)

38360

{

38361

if (DECL_P (op))

38362

check_decl ((funct_state)data, op, false, false);

38363

@@ -600,7 +600,7 @@

38364

/* Wrapper around check_decl for stores in local more. */

38365

38366

static bool

38367

-check_store (gimple stmt ATTRIBUTE_UNUSED, tree op, void *data)

38368

+check_store (gimple, tree op, tree, void *data)

38369

{

38370

if (DECL_P (op))

38371

check_decl ((funct_state)data, op, true, false);

38372

@@ -612,7 +612,7 @@

38373

/* Wrapper around check_decl for loads in ipa mode. */

38374

38375

static bool

38376

-check_ipa_load (gimple stmt ATTRIBUTE_UNUSED, tree op, void *data)

38377

+check_ipa_load (gimple, tree op, tree, void *data)

38378

{

38379

if (DECL_P (op))

38380

check_decl ((funct_state)data, op, false, true);

38381

@@ -624,7 +624,7 @@

38382

/* Wrapper around check_decl for stores in ipa mode. */

38383

38384

static bool

38385

-check_ipa_store (gimple stmt ATTRIBUTE_UNUSED, tree op, void *data)

38386

+check_ipa_store (gimple, tree op, tree, void *data)

38387

{

38388

if (DECL_P (op))

38389

check_decl ((funct_state)data, op, true, true);

38390

Index: gcc/cse.c

38391

===================================================================

38392

--- a/src/gcc/cse.c (.../tags/gcc_4_8_2_release)

38393

+++ b/src/gcc/cse.c (.../branches/gcc-4_8-branch)

38394

@@ -1824,7 +1824,7 @@

38395

}

38396

}

38397

38398

-/* Function called for each rtx to check whether true dependence exist. */

38399

+/* Function called for each rtx to check whether an anti dependence exist. */

38400

struct check_dependence_data

38401

{

38402

enum machine_mode mode;

38403

@@ -1837,7 +1837,7 @@

38404

{

38405

struct check_dependence_data *d = (struct check_dependence_data *) data;

38406

if (*x && MEM_P (*x))

38407

- return canon_true_dependence (d->exp, d->mode, d->addr, *x, NULL_RTX);

38408

+ return canon_anti_dependence (*x, true, d->exp, d->mode, d->addr);

38409

else

38410

return 0;

38411

}

38412

@@ -6082,6 +6082,18 @@

38413

return x;

38414

}

38415

38416

+ case UNSIGNED_FLOAT:

38417

+ {

38418

+ rtx new_rtx = cse_process_notes (XEXP (x, 0), object, changed);

38419

+ /* We don't substitute negative VOIDmode constants into these rtx,

38420

+ since they would impede folding. */

38421

+ if (GET_MODE (new_rtx) != VOIDmode

38422

+ || (CONST_INT_P (new_rtx) && INTVAL (new_rtx) >= 0)

38423

+ || (CONST_DOUBLE_P (new_rtx) && CONST_DOUBLE_HIGH (new_rtx) >= 0))

38424

+ validate_change (object, &XEXP (x, 0), new_rtx, 0);

38425

+ return x;

38426

+ }

38427

+

38428

case REG:

38429

i = REG_QTY (REGNO (x));

38430

38431

Index: gcc/tree-ssa-math-opts.c

38432

===================================================================

38433

--- a/src/gcc/tree-ssa-math-opts.c (.../tags/gcc_4_8_2_release)

38434

+++ b/src/gcc/tree-ssa-math-opts.c (.../branches/gcc-4_8-branch)

38435

@@ -1718,7 +1718,9 @@

38436

38437

if (rhs_class == GIMPLE_BINARY_RHS)

38438

{

38439

+ int i;

38440

struct symbolic_number n1, n2;

38441

+ unsigned HOST_WIDEST_INT mask;

38442

tree source_expr2;

38443

38444

if (code != BIT_IOR_EXPR)

38445

@@ -1744,6 +1746,15 @@

38446

return NULL_TREE;

38447

38448

n->size = n1.size;

38449

+ for (i = 0, mask = 0xff; i < n->size; i++, mask <<= BITS_PER_UNIT)

38450

+ {

38451

+ unsigned HOST_WIDEST_INT masked1, masked2;

38452

+

38453

+ masked1 = n1.n & mask;

38454

+ masked2 = n2.n & mask;

38455

+ if (masked1 && masked2 && masked1 != masked2)

38456

+ return NULL_TREE;

38457

+ }

38458

n->n = n1.n | n2.n;

38459

38460

if (!verify_symbolic_number_p (n, stmt))

38461

Index: gcc/sel-sched.c

38462

===================================================================

38463

--- a/src/gcc/sel-sched.c (.../tags/gcc_4_8_2_release)

38464

+++ b/src/gcc/sel-sched.c (.../branches/gcc-4_8-branch)

38465

@@ -1253,7 +1253,7 @@

38466

38467

if (!HARD_FRAME_POINTER_IS_FRAME_POINTER)

38468

add_to_hard_reg_set (&reg_rename_p->unavailable_hard_regs,

38469

- Pmode, HARD_FRAME_POINTER_IS_FRAME_POINTER);

38470

+ Pmode, HARD_FRAME_POINTER_REGNUM);

38471

}

38472

38473

#ifdef STACK_REGS

38474

Index: gcc/gimple-low.c

38475

===================================================================

38476

--- a/src/gcc/gimple-low.c (.../tags/gcc_4_8_2_release)

38477

+++ b/src/gcc/gimple-low.c (.../branches/gcc-4_8-branch)

38478

@@ -238,6 +238,7 @@

38479

break;

38480

arg = gimple_call_arg (stmt, i);

38481

if (p == error_mark_node

38482

+ || DECL_ARG_TYPE (p) == error_mark_node

38483

|| arg == error_mark_node

38484

|| (!types_compatible_p (DECL_ARG_TYPE (p), TREE_TYPE (arg))

38485

&& !fold_convertible_p (DECL_ARG_TYPE (p), arg)))

38486

Index: gcc/tree-ssa-sink.c

38487

===================================================================

38488

--- a/src/gcc/tree-ssa-sink.c (.../tags/gcc_4_8_2_release)

38489

+++ b/src/gcc/tree-ssa-sink.c (.../branches/gcc-4_8-branch)

38490

@@ -559,7 +559,7 @@

38491

execute_sink_code (void)

38492

{

38493

loop_optimizer_init (LOOPS_NORMAL);

38494

-

38495

+ split_critical_edges ();

38496

connect_infinite_loops_to_exit ();

38497

memset (&sink_stats, 0, sizeof (sink_stats));

38498

calculate_dominance_info (CDI_DOMINATORS);

38499

Index: gcc/config.in

38500

===================================================================

38501

--- a/src/gcc/config.in (.../tags/gcc_4_8_2_release)

38502

+++ b/src/gcc/config.in (.../branches/gcc-4_8-branch)

38503

@@ -363,6 +363,12 @@

38504

#endif

38505

38506

38507

+/* Define if your assembler supports the 'ud2' mnemonic. */

38508

+#ifndef USED_FOR_TARGET

38509

+#undef HAVE_AS_IX86_UD2

38510

+#endif

38511

+

38512

+

38513

/* Define if your assembler supports the lituse_jsrdirect relocation. */

38514

#ifndef USED_FOR_TARGET

38515

#undef HAVE_AS_JSRDIRECT_RELOCS

38516

@@ -375,6 +381,12 @@

38517

#endif

38518

38519

38520

+/* Define if your assembler supports LEON instructions. */

38521

+#ifndef USED_FOR_TARGET

38522

+#undef HAVE_AS_LEON

38523

+#endif

38524

+

38525

+

38526

/* Define if the assembler won't complain about a line such as # 0 "" 2. */

38527

#ifndef USED_FOR_TARGET

38528

#undef HAVE_AS_LINE_ZERO

38529

Index: gcc/ifcvt.c

38530

===================================================================

38531

--- a/src/gcc/ifcvt.c (.../tags/gcc_4_8_2_release)

38532

+++ b/src/gcc/ifcvt.c (.../branches/gcc-4_8-branch)

38533

@@ -115,7 +115,11 @@

38534

38535

while (1)

38536

{

38537

- if (CALL_P (insn) || NONJUMP_INSN_P (insn))

38538

+ if ((CALL_P (insn) || NONJUMP_INSN_P (insn))

38539

+ /* Don't count USE/CLOBBER insns, flow_find_cross_jump etc.

38540

+ don't count them either and we need consistency. */

38541

+ && GET_CODE (PATTERN (insn)) != USE

38542

+ && GET_CODE (PATTERN (insn)) != CLOBBER)

38543

count++;

38544

38545

if (insn == BB_END (bb))

38546

@@ -505,7 +509,10 @@

38547

n_insns -= 2 * n_matching;

38548

}

38549

38550

- if (then_start && else_start)

38551

+ if (then_start

38552

+ && else_start

38553

+ && then_n_insns > n_matching

38554

+ && else_n_insns > n_matching)

38555

{

38556

int longest_match = MIN (then_n_insns - n_matching,

38557

else_n_insns - n_matching);

38558

Index: gcc/expr.c

38559

===================================================================

38560

--- a/src/gcc/expr.c (.../tags/gcc_4_8_2_release)

38561

+++ b/src/gcc/expr.c (.../branches/gcc-4_8-branch)

38562

@@ -1994,12 +1994,14 @@

38563

HOST_WIDE_INT bytepos = INTVAL (XEXP (XVECEXP (src, 0, i), 1));

38564

enum machine_mode mode = GET_MODE (tmps[i]);

38565

unsigned int bytelen = GET_MODE_SIZE (mode);

38566

- unsigned int adj_bytelen = bytelen;

38567

+ unsigned int adj_bytelen;

38568

rtx dest = dst;

38569

38570

/* Handle trailing fragments that run over the size of the struct. */

38571

if (ssize >= 0 && bytepos + (HOST_WIDE_INT) bytelen > ssize)

38572

adj_bytelen = ssize - bytepos;

38573

+ else

38574

+ adj_bytelen = bytelen;

38575

38576

if (GET_CODE (dst) == CONCAT)

38577

{

38578

@@ -2040,6 +2042,7 @@

38579

}

38580

}

38581

38582

+ /* Handle trailing fragments that run over the size of the struct. */

38583

if (ssize >= 0 && bytepos + (HOST_WIDE_INT) bytelen > ssize)

38584

{

38585

/* store_bit_field always takes its value from the lsb.

38586

@@ -2057,16 +2060,22 @@

38587

tmps[i] = expand_shift (RSHIFT_EXPR, mode, tmps[i],

38588

shift, tmps[i], 0);

38589

}

38590

- bytelen = adj_bytelen;

38591

+

38592

+ /* Make sure not to write past the end of the struct. */

38593

+ store_bit_field (dest,

38594

+ adj_bytelen * BITS_PER_UNIT, bytepos * BITS_PER_UNIT,

38595

+ bytepos * BITS_PER_UNIT, ssize * BITS_PER_UNIT - 1,

38596

+ VOIDmode, tmps[i]);

38597

}

38598

38599

/* Optimize the access just a bit. */

38600

- if (MEM_P (dest)

38601

- && (! SLOW_UNALIGNED_ACCESS (mode, MEM_ALIGN (dest))

38602

- || MEM_ALIGN (dest) >= GET_MODE_ALIGNMENT (mode))

38603

- && bytepos * BITS_PER_UNIT % GET_MODE_ALIGNMENT (mode) == 0

38604

- && bytelen == GET_MODE_SIZE (mode))

38605

+ else if (MEM_P (dest)

38606

+ && (!SLOW_UNALIGNED_ACCESS (mode, MEM_ALIGN (dest))

38607

+ || MEM_ALIGN (dest) >= GET_MODE_ALIGNMENT (mode))

38608

+ && bytepos * BITS_PER_UNIT % GET_MODE_ALIGNMENT (mode) == 0

38609

+ && bytelen == GET_MODE_SIZE (mode))

38610

emit_move_insn (adjust_address (dest, mode, bytepos), tmps[i]);

38611

+

38612

else

38613

store_bit_field (dest, bytelen * BITS_PER_UNIT, bytepos * BITS_PER_UNIT,

38614

0, 0, mode, tmps[i]);

38615

@@ -3602,12 +3611,21 @@

38616

into a new pseudo. This constant may be used in different modes,

38617

and if not, combine will put things back together for us. */

38618

trunc_y = force_reg (srcmode, trunc_y);

38619

- emit_unop_insn (ic, x, trunc_y, UNKNOWN);

38620

+

38621

+ /* If x is a hard register, perform the extension into a pseudo,

38622

+ so that e.g. stack realignment code is aware of it. */

38623

+ rtx target = x;

38624

+ if (REG_P (x) && HARD_REGISTER_P (x))

38625

+ target = gen_reg_rtx (dstmode);

38626

+

38627

+ emit_unop_insn (ic, target, trunc_y, UNKNOWN);

38628

last_insn = get_last_insn ();

38629

38630

- if (REG_P (x))

38631

+ if (REG_P (target))

38632

set_unique_reg_note (last_insn, REG_EQUAL, y);

38633

38634

+ if (target != x)

38635

+ return emit_move_insn (x, target);

38636

return last_insn;

38637

}

38638

38639

@@ -4551,19 +4569,19 @@

38640

- tree_low_cst (DECL_FIELD_BIT_OFFSET (repr), 1));

38641

38642

/* If the adjustment is larger than bitpos, we would have a negative bit

38643

- position for the lower bound and this may wreak havoc later. This can

38644

- occur only if we have a non-null offset, so adjust offset and bitpos

38645

- to make the lower bound non-negative. */

38646

+ position for the lower bound and this may wreak havoc later. Adjust

38647

+ offset and bitpos to make the lower bound non-negative in that case. */

38648

if (bitoffset > *bitpos)

38649

{

38650

HOST_WIDE_INT adjust = bitoffset - *bitpos;

38651

-

38652

gcc_assert ((adjust % BITS_PER_UNIT) == 0);

38653

- gcc_assert (*offset != NULL_TREE);

38654

38655

*bitpos += adjust;

38656

- *offset

38657

- = size_binop (MINUS_EXPR, *offset, size_int (adjust / BITS_PER_UNIT));

38658

+ if (*offset == NULL_TREE)

38659

+ *offset = size_int (-adjust / BITS_PER_UNIT);

38660

+ else

38661

+ *offset

38662

+ = size_binop (MINUS_EXPR, *offset, size_int (adjust / BITS_PER_UNIT));

38663

*bitstart = 0;

38664

}

38665

else

38666

@@ -4668,8 +4686,7 @@

38667

expand_insn (icode, 2, ops);

38668

}

38669

else

38670

- store_bit_field (mem, GET_MODE_BITSIZE (mode),

38671

- 0, 0, 0, mode, reg);

38672

+ store_bit_field (mem, GET_MODE_BITSIZE (mode), 0, 0, 0, mode, reg);

38673

return;

38674

}

38675

38676

@@ -4698,6 +4715,15 @@

38677

tem = get_inner_reference (to, &bitsize, &bitpos, &offset, &mode1,

38678

&unsignedp, &volatilep, true);

38679

38680

+ /* Make sure bitpos is not negative, it can wreak havoc later. */

38681

+ if (bitpos < 0)

38682

+ {

38683

+ gcc_assert (offset == NULL_TREE);

38684

+ offset = size_int (bitpos >> (BITS_PER_UNIT == 8

38685

+ ? 3 : exact_log2 (BITS_PER_UNIT)));

38686

+ bitpos &= BITS_PER_UNIT - 1;

38687

+ }

38688

+

38689

if (TREE_CODE (to) == COMPONENT_REF

38690

&& DECL_BIT_FIELD_TYPE (TREE_OPERAND (to, 1)))

38691

get_bit_range (&bitregion_start, &bitregion_end, to, &bitpos, &offset);

38692

Index: gcc/expr.h

38693

===================================================================

38694

--- a/src/gcc/expr.h (.../tags/gcc_4_8_2_release)

38695

+++ b/src/gcc/expr.h (.../branches/gcc-4_8-branch)

38696

@@ -521,8 +521,8 @@

38697

rtx, int);

38698

#endif

38699

38700

-extern void locate_and_pad_parm (enum machine_mode, tree, int, int, tree,

38701

- struct args_size *,

38702

+extern void locate_and_pad_parm (enum machine_mode, tree, int, int, int,

38703

+ tree, struct args_size *,

38704

struct locate_and_pad_arg_data *);

38705

38706

/* Return the CODE_LABEL rtx for a LABEL_DECL, creating it if necessary. */

38707

Index: gcc/go/go-gcc.cc

38708

===================================================================

38709

--- a/src/gcc/go/go-gcc.cc (.../tags/gcc_4_8_2_release)

38710

+++ b/src/gcc/go/go-gcc.cc (.../branches/gcc-4_8-branch)

38711

@@ -232,6 +232,9 @@

38712

Bexpression*

38713

convert_expression(Btype* type, Bexpression* expr, Location);

38714

38715

+ Bexpression*

38716

+ function_code_expression(Bfunction*, Location);

38717

+

38718

// Statements.

38719

38720

Bstatement*

38721

@@ -334,6 +337,17 @@

38722

Bexpression*

38723

label_address(Blabel*, Location);

38724

38725

+ // Functions.

38726

+

38727

+ Bfunction*

38728

+ error_function()

38729

+ { return this->make_function(error_mark_node); }

38730

+

38731

+ Bfunction*

38732

+ function(Btype* fntype, const std::string& name, const std::string& asm_name,

38733

+ bool is_visible, bool is_declaration, bool is_inlinable,

38734

+ bool disable_split_stack, bool in_unique_section, Location);

38735

+

38736

private:

38737

// Make a Bexpression from a tree.

38738

Bexpression*

38739

@@ -350,6 +364,10 @@

38740

make_type(tree t)

38741

{ return new Btype(t); }

38742

38743

+ Bfunction*

38744

+ make_function(tree t)

38745

+ { return new Bfunction(t); }

38746

+

38747

Btype*

38748

fill_in_struct(Btype*, const std::vector<Btyped_identifier>&);

38749

38750

@@ -966,6 +984,19 @@

38751

return tree_to_expr(ret);

38752

}

38753

38754

+// Get the address of a function.

38755

+

38756

+Bexpression*

38757

+Gcc_backend::function_code_expression(Bfunction* bfunc, Location location)

38758

+{

38759

+ tree func = bfunc->get_tree();

38760

+ if (func == error_mark_node)

38761

+ return this->error_expression();

38762

+

38763

+ tree ret = build_fold_addr_expr_loc(location.gcc_location(), func);

38764

+ return this->make_expression(ret);

38765

+}

38766

+

38767

// An expression as a statement.

38768

38769

Bstatement*

38770

@@ -1724,6 +1755,56 @@

38771

return this->make_expression(ret);

38772

}

38773

38774

+// Declare or define a new function.

38775

+

38776

+Bfunction*

38777

+Gcc_backend::function(Btype* fntype, const std::string& name,

38778

+ const std::string& asm_name, bool is_visible,

38779

+ bool is_declaration, bool is_inlinable,

38780

+ bool disable_split_stack, bool in_unique_section,

38781

+ Location location)

38782

+{

38783

+ tree functype = fntype->get_tree();

38784

+ if (functype != error_mark_node)

38785

+ {

38786

+ gcc_assert(FUNCTION_POINTER_TYPE_P(functype));

38787

+ functype = TREE_TYPE(functype);

38788

+ }

38789

+ tree id = get_identifier_from_string(name);

38790

+ if (functype == error_mark_node || id == error_mark_node)

38791

+ return this->error_function();

38792

+

38793

+ tree decl = build_decl(location.gcc_location(), FUNCTION_DECL, id, functype);

38794

+ if (!asm_name.empty())

38795

+ SET_DECL_ASSEMBLER_NAME(decl, get_identifier_from_string(asm_name));

38796

+ if (is_visible)

38797

+ TREE_PUBLIC(decl) = 1;

38798

+ if (is_declaration)

38799

+ DECL_EXTERNAL(decl) = 1;

38800

+ else

38801

+ {

38802

+ tree restype = TREE_TYPE(functype);

38803

+ tree resdecl =

38804

+ build_decl(location.gcc_location(), RESULT_DECL, NULL_TREE, restype);

38805

+ DECL_ARTIFICIAL(resdecl) = 1;

38806

+ DECL_IGNORED_P(resdecl) = 1;

38807

+ DECL_CONTEXT(resdecl) = decl;

38808

+ DECL_RESULT(decl) = resdecl;

38809

+ }

38810

+ if (!is_inlinable)

38811

+ DECL_UNINLINABLE(decl) = 1;

38812

+ if (disable_split_stack)

38813

+ {

38814

+ tree attr = get_identifier("__no_split_stack__");

38815

+ DECL_ATTRIBUTES(decl) = tree_cons(attr, NULL_TREE, NULL_TREE);

38816

+ }

38817

+ if (in_unique_section)

38818

+ resolve_unique_section(decl, 0, 1);

38819

+

38820

+ go_preserve_from_gc(decl);

38821

+ return new Bfunction(decl);

38822

+}

38823

+

38824

// The single backend.

38825

38826

static Gcc_backend gcc_backend;

38827

@@ -1799,3 +1880,9 @@

38828

{

38829

return bv->get_tree();

38830

}

38831

+

38832

+tree

38833

+function_to_tree(Bfunction* bf)

38834

+{

38835

+ return bf->get_tree();

38836

+}

38837

Index: gcc/go/ChangeLog

38838

===================================================================

38839

--- a/src/gcc/go/ChangeLog (.../tags/gcc_4_8_2_release)

38840

+++ b/src/gcc/go/ChangeLog (.../branches/gcc-4_8-branch)

38841

@@ -1,3 +1,22 @@

38842

+2013-12-11 Ian Lance Taylor <iant@google.com>

38843

+

38844

+ * go-lang.c (go_langhook_post_options): Disable sibling calls by

38845

+ default.

38846

+

38847

+2013-10-16 Ian Lance Taylor <iant@google.com>

38848

+

38849

+ Bring in from mainline:

38850

+

38851

+ 2013-10-11 Chris Manghane <cmang@google.com>

38852

+ * go-gcc.cc (Gcc_backend::function_code_expression): New

38853

+ function.

38854

+

38855

+ 2013-10-10 Chris Manghane <cmang@google.com>

38856

+ * go-gcc.cc (Backend::error_function): New function.

38857

+ (Backend::function): New function.

38858

+ (Backend::make_function): New function.

38859

+ (function_to_tree): New function.

38860

+

38861

2013-10-16 Release Manager

38862

38863

* GCC 4.8.2 released.

38864

Index: gcc/go/go-lang.c

38865

===================================================================

38866

--- a/src/gcc/go/go-lang.c (.../tags/gcc_4_8_2_release)

38867

+++ b/src/gcc/go/go-lang.c (.../branches/gcc-4_8-branch)

38868

@@ -269,6 +269,10 @@

38869

if (flag_excess_precision_cmdline == EXCESS_PRECISION_DEFAULT)

38870

flag_excess_precision_cmdline = EXCESS_PRECISION_STANDARD;

38871

38872

+ /* Tail call optimizations can confuse uses of runtime.Callers. */

38873

+ if (!global_options_set.x_flag_optimize_sibling_calls)

38874

+ global_options.x_flag_optimize_sibling_calls = 0;

38875

+

38876

/* Returning false means that the backend should be used. */

38877

return false;

38878

}

38879

Index: gcc/go/gofrontend/gogo.cc

38880

===================================================================

38881

--- a/src/gcc/go/gofrontend/gogo.cc (.../tags/gcc_4_8_2_release)

38882

+++ b/src/gcc/go/gofrontend/gogo.cc (.../branches/gcc-4_8-branch)

38883

@@ -2822,7 +2822,10 @@

38884

if (orig_fntype->is_varargs())

38885

new_fntype->set_is_varargs();

38886

38887

- std::string name = orig_no->name() + "$recover";

38888

+ std::string name = orig_no->name();

38889

+ if (orig_fntype->is_method())

38890

+ name += "$" + orig_fntype->receiver()->type()->mangled_name(gogo);

38891

+ name += "$recover";

38892

Named_object *new_no = gogo->start_function(name, new_fntype, false,

38893

location);

38894

Function *new_func = new_no->func_value();

38895

@@ -2916,7 +2919,25 @@

38896

&& !orig_rec_no->var_value()->is_receiver());

38897

orig_rec_no->var_value()->set_is_receiver();

38898

38899

- const std::string& new_receiver_name(orig_fntype->receiver()->name());

38900

+ std::string new_receiver_name(orig_fntype->receiver()->name());

38901

+ if (new_receiver_name.empty())

38902

+ {

38903

+ // Find the receiver. It was named "r.NNN" in

38904

+ // Gogo::start_function.

38905

+ for (Bindings::const_definitions_iterator p =

38906

+ new_bindings->begin_definitions();

38907

+ p != new_bindings->end_definitions();

38908

+ ++p)

38909

+ {

38910

+ const std::string& pname((*p)->name());

38911

+ if (pname[0] == 'r' && pname[1] == '.')

38912

+ {

38913

+ new_receiver_name = pname;

38914

+ break;

38915

+ }

38916

+ }

38917

+ go_assert(!new_receiver_name.empty());

38918

+ }

38919

Named_object* new_rec_no = new_bindings->lookup_local(new_receiver_name);

38920

if (new_rec_no == NULL)

38921

go_assert(saw_errors());

38922

@@ -3320,7 +3341,8 @@

38923

closure_var_(NULL), block_(block), location_(location), labels_(),

38924

local_type_count_(0), descriptor_(NULL), fndecl_(NULL), defer_stack_(NULL),

38925

is_sink_(false), results_are_named_(false), nointerface_(false),

38926

- calls_recover_(false), is_recover_thunk_(false), has_recover_thunk_(false),

38927

+ is_unnamed_type_stub_method_(false), calls_recover_(false),

38928

+ is_recover_thunk_(false), has_recover_thunk_(false),

38929

in_unique_section_(false)

38930

{

38931

}

38932

@@ -3819,6 +3841,81 @@

38933

*presults = results;

38934

}

38935

38936

+// Get the backend representation.

38937

+

38938

+Bfunction*

38939

+Function::get_or_make_decl(Gogo* gogo, Named_object* no)

38940

+{

38941

+ if (this->fndecl_ == NULL)

38942

+ {

38943

+ std::string asm_name;

38944

+ bool is_visible = false;

38945

+ if (no->package() != NULL)

38946

+ ;

38947

+ else if (this->enclosing_ != NULL || Gogo::is_thunk(no))

38948

+ ;

38949

+ else if (Gogo::unpack_hidden_name(no->name()) == "init"

38950

+ && !this->type_->is_method())

38951

+ ;

38952

+ else if (Gogo::unpack_hidden_name(no->name()) == "main"

38953

+ && gogo->is_main_package())

38954

+ is_visible = true;

38955

+ // Methods have to be public even if they are hidden because

38956

+ // they can be pulled into type descriptors when using

38957

+ // anonymous fields.

38958

+ else if (!Gogo::is_hidden_name(no->name())

38959

+ || this->type_->is_method())

38960

+ {

38961

+ if (!this->is_unnamed_type_stub_method_)

38962

+ is_visible = true;

38963

+ std::string pkgpath = gogo->pkgpath_symbol();

38964

+ if (this->type_->is_method()

38965

+ && Gogo::is_hidden_name(no->name())

38966

+ && Gogo::hidden_name_pkgpath(no->name()) != gogo->pkgpath())

38967

+ {

38968

+ // This is a method we created for an unexported

38969

+ // method of an imported embedded type. We need to

38970

+ // use the pkgpath of the imported package to avoid

38971

+ // a possible name collision. See bug478 for a test

38972

+ // case.

38973

+ pkgpath = Gogo::hidden_name_pkgpath(no->name());

38974

+ pkgpath = Gogo::pkgpath_for_symbol(pkgpath);

38975

+ }

38976

+

38977

+ asm_name = pkgpath;

38978

+ asm_name.append(1, '.');

38979

+ asm_name.append(Gogo::unpack_hidden_name(no->name()));

38980

+ if (this->type_->is_method())

38981

+ {

38982

+ asm_name.append(1, '.');

38983

+ Type* rtype = this->type_->receiver()->type();

38984

+ asm_name.append(rtype->mangled_name(gogo));

38985

+ }

38986

+ }

38987

+

38988

+ // If a function calls the predeclared recover function, we

38989

+ // can't inline it, because recover behaves differently in a

38990

+ // function passed directly to defer. If this is a recover

38991

+ // thunk that we built to test whether a function can be

38992

+ // recovered, we can't inline it, because that will mess up

38993

+ // our return address comparison.

38994

+ bool is_inlinable = !(this->calls_recover_ || this->is_recover_thunk_);

38995

+

38996

+ // If this is a thunk created to call a function which calls

38997

+ // the predeclared recover function, we need to disable

38998

+ // stack splitting for the thunk.

38999

+ bool disable_split_stack = this->is_recover_thunk_;

39000

+

39001

+ Btype* functype = this->type_->get_backend_fntype(gogo);

39002

+ this->fndecl_ =

39003

+ gogo->backend()->function(functype, no->get_id(gogo), asm_name,

39004

+ is_visible, false, is_inlinable,

39005

+ disable_split_stack,

39006

+ this->in_unique_section_, this->location());

39007

+ }

39008

+ return this->fndecl_;

39009

+}

39010

+

39011

// Class Block.

39012

39013

Block::Block(Block* enclosing, Location location)

39014

@@ -5110,6 +5207,75 @@

39015

go_unreachable();

39016

}

39017

39018

+

39019

+// Return the external identifier for this object.

39020

+

39021

+std::string

39022

+Named_object::get_id(Gogo* gogo)

39023

+{

39024

+ go_assert(!this->is_variable() && !this->is_result_variable());

39025

+ std::string decl_name;

39026

+ if (this->is_function_declaration()

39027

+ && !this->func_declaration_value()->asm_name().empty())

39028

+ decl_name = this->func_declaration_value()->asm_name();

39029

+ else if (this->is_type()

39030

+ && Linemap::is_predeclared_location(this->type_value()->location()))

39031

+ {

39032

+ // We don't need the package name for builtin types.

39033

+ decl_name = Gogo::unpack_hidden_name(this->name_);

39034

+ }

39035

+ else

39036

+ {

39037

+ std::string package_name;

39038

+ if (this->package_ == NULL)

39039

+ package_name = gogo->package_name();

39040

+ else

39041

+ package_name = this->package_->package_name();

39042

+

39043

+ // Note that this will be misleading if this is an unexported

39044

+ // method generated for an embedded imported type. In that case

39045

+ // the unexported method should have the package name of the

39046

+ // package from which it is imported, but we are going to give

39047

+ // it our package name. Fixing this would require knowing the

39048

+ // package name, but we only know the package path. It might be

39049

+ // better to use package paths here anyhow. This doesn't affect

39050

+ // the assembler code, because we always set that name in

39051

+ // Function::get_or_make_decl anyhow. FIXME.

39052

+

39053

+ decl_name = package_name + '.' + Gogo::unpack_hidden_name(this->name_);

39054

+

39055

+ Function_type* fntype;

39056

+ if (this->is_function())

39057

+ fntype = this->func_value()->type();

39058

+ else if (this->is_function_declaration())

39059

+ fntype = this->func_declaration_value()->type();

39060

+ else

39061

+ fntype = NULL;

39062

+ if (fntype != NULL && fntype->is_method())

39063

+ {

39064

+ decl_name.push_back('.');

39065

+ decl_name.append(fntype->receiver()->type()->mangled_name(gogo));

39066

+ }

39067

+ }

39068

+ if (this->is_type())

39069

+ {

39070

+ unsigned int index;

39071

+ const Named_object* in_function = this->type_value()->in_function(&index);

39072

+ if (in_function != NULL)

39073

+ {

39074

+ decl_name += '$' + Gogo::unpack_hidden_name(in_function->name());

39075

+ if (index > 0)

39076

+ {

39077

+ char buf[30];

39078

+ snprintf(buf, sizeof buf, "%u", index);

39079

+ decl_name += '$';

39080

+ decl_name += buf;

39081

+ }

39082

+ }

39083

+ }

39084

+ return decl_name;

39085

+}

39086

+

39087

// Class Bindings.

39088

39089

Bindings::Bindings(Bindings* enclosing)

39090

Index: gcc/go/gofrontend/runtime.def

39091

===================================================================

39092

--- a/src/gcc/go/gofrontend/runtime.def (.../tags/gcc_4_8_2_release)

39093

+++ b/src/gcc/go/gofrontend/runtime.def (.../branches/gcc-4_8-branch)

39094

@@ -68,6 +68,12 @@

39095

P1(STRING), R1(SLICE))

39096

39097

39098

+// Complex division.

39099

+DEF_GO_RUNTIME(COMPLEX64_DIV, "__go_complex64_div",

39100

+ P2(COMPLEX64, COMPLEX64), R1(COMPLEX64))

39101

+DEF_GO_RUNTIME(COMPLEX128_DIV, "__go_complex128_div",

39102

+ P2(COMPLEX128, COMPLEX128), R1(COMPLEX128))

39103

+

39104

// Make a slice.

39105

DEF_GO_RUNTIME(MAKESLICE1, "__go_make_slice1", P2(TYPE, UINTPTR), R1(SLICE))

39106

DEF_GO_RUNTIME(MAKESLICE2, "__go_make_slice2", P3(TYPE, UINTPTR, UINTPTR),

39107

Index: gcc/go/gofrontend/gogo.h

39108

===================================================================

39109

--- a/src/gcc/go/gofrontend/gogo.h (.../tags/gcc_4_8_2_release)

39110

+++ b/src/gcc/go/gofrontend/gogo.h (.../branches/gcc-4_8-branch)

39111

@@ -48,6 +48,7 @@

39112

class Bblock;

39113

class Bvariable;

39114

class Blabel;

39115

+class Bfunction;

39116

39117

// This file declares the basic classes used to hold the internal

39118

// representation of Go which is built by the parser.

39119

@@ -952,6 +953,15 @@

39120

this->nointerface_ = true;

39121

}

39122

39123

+ // Record that this function is a stub method created for an unnamed

39124

+ // type.

39125

+ void

39126

+ set_is_unnamed_type_stub_method()

39127

+ {

39128

+ go_assert(this->is_method());

39129

+ this->is_unnamed_type_stub_method_ = true;

39130

+ }

39131

+

39132

// Add a new field to the closure variable.

39133

void

39134

add_closure_field(Named_object* var, Location loc)

39135

@@ -1089,17 +1099,13 @@

39136

this->descriptor_ = descriptor;

39137

}

39138

39139

- // Return the function's decl given an identifier.

39140

- tree

39141

- get_or_make_decl(Gogo*, Named_object*, tree id);

39142

+ // Return the backend representation.

39143

+ Bfunction*

39144

+ get_or_make_decl(Gogo*, Named_object*);

39145

39146

// Return the function's decl after it has been built.

39147

tree

39148

- get_decl() const

39149

- {

39150

- go_assert(this->fndecl_ != NULL);

39151

- return this->fndecl_;

39152

- }

39153

+ get_decl() const;

39154

39155

// Set the function decl to hold a tree of the function code.

39156

void

39157

@@ -1170,7 +1176,7 @@

39158

// The function descriptor, if any.

39159

Expression* descriptor_;

39160

// The function decl.

39161

- tree fndecl_;

39162

+ Bfunction* fndecl_;

39163

// The defer stack variable. A pointer to this variable is used to

39164

// distinguish the defer stack for one function from another. This

39165

// is NULL unless we actually need a defer stack.

39166

@@ -1181,6 +1187,9 @@

39167

bool results_are_named_ : 1;

39168

// True if this method should not be included in the type descriptor.

39169

bool nointerface_ : 1;

39170

+ // True if this function is a stub method created for an unnamed

39171

+ // type.

39172

+ bool is_unnamed_type_stub_method_ : 1;

39173

// True if this function calls the predeclared recover function.

39174

bool calls_recover_ : 1;

39175

// True if this a thunk built for a function which calls recover.

39176

@@ -1265,9 +1274,9 @@

39177

has_descriptor() const

39178

{ return this->descriptor_ != NULL; }

39179

39180

- // Return a decl for the function given an identifier.

39181

- tree

39182

- get_or_make_decl(Gogo*, Named_object*, tree id);

39183

+ // Return a backend representation.

39184

+ Bfunction*

39185

+ get_or_make_decl(Gogo*, Named_object*);

39186

39187

// If there is a descriptor, build it into the backend

39188

// representation.

39189

@@ -1290,7 +1299,7 @@

39190

// The function descriptor, if any.

39191

Expression* descriptor_;

39192

// The function decl if needed.

39193

- tree fndecl_;

39194

+ Bfunction* fndecl_;

39195

};

39196

39197

// A variable.

39198

@@ -2181,8 +2190,8 @@

39199

Bvariable*

39200

get_backend_variable(Gogo*, Named_object* function);

39201

39202

- // Return a tree for the external identifier for this object.

39203

- tree

39204

+ // Return the external identifier for this object.

39205

+ std::string

39206

get_id(Gogo*);

39207

39208

// Return a tree representing this object.

39209

Index: gcc/go/gofrontend/types.h

39210

===================================================================

39211

--- a/src/gcc/go/gofrontend/types.h (.../tags/gcc_4_8_2_release)

39212

+++ b/src/gcc/go/gofrontend/types.h (.../branches/gcc-4_8-branch)

39213

@@ -1138,6 +1138,13 @@

39214

Function_type* equal_fntype, Named_object** hash_fn,

39215

Named_object** equal_fn);

39216

39217

+ void

39218

+ write_named_hash(Gogo*, Named_type*, Function_type* hash_fntype,

39219

+ Function_type* equal_fntype);

39220

+

39221

+ void

39222

+ write_named_equal(Gogo*, Named_type*);

39223

+

39224

// Build a composite literal for the uncommon type information.

39225

Expression*

39226

uncommon_type_constructor(Gogo*, Type* uncommon_type,

39227

@@ -1717,7 +1724,8 @@

39228

Typed_identifier_list* results, Location location)

39229

: Type(TYPE_FUNCTION),

39230

receiver_(receiver), parameters_(parameters), results_(results),

39231

- location_(location), is_varargs_(false), is_builtin_(false)

39232

+ location_(location), is_varargs_(false), is_builtin_(false),

39233

+ fnbtype_(NULL)

39234

{ }

39235

39236

// Get the receiver.

39237

@@ -1789,6 +1797,12 @@

39238

Function_type*

39239

copy_with_receiver(Type*) const;

39240

39241

+ // Return a copy of this type with the receiver treated as the first

39242

+ // parameter. If WANT_POINTER_RECEIVER is true, the receiver is

39243

+ // forced to be a pointer.

39244

+ Function_type*

39245

+ copy_with_receiver_as_param(bool want_pointer_receiver) const;

39246

+

39247

// Return a copy of this type ignoring any receiver and using dummy

39248

// names for all parameters. This is used for thunks for method

39249

// values.

39250

@@ -1798,6 +1812,11 @@

39251

static Type*

39252

make_function_type_descriptor_type();

39253

39254

+ // Return the backend representation of this function type. This is used

39255

+ // as the real type of a backend function declaration or defintion.

39256

+ Btype*

39257

+ get_backend_fntype(Gogo*);

39258

+

39259

protected:

39260

int

39261

do_traverse(Traverse*);

39262

@@ -1851,6 +1870,9 @@

39263

// Whether this is a special builtin function which can not simply

39264

// be called. This is used for len, cap, etc.

39265

bool is_builtin_;

39266

+ // The backend representation of this type for backend function

39267

+ // declarations and definitions.

39268

+ Btype* fnbtype_;

39269

};

39270

39271

// The type of a pointer.

39272

@@ -1915,7 +1937,7 @@

39273

{

39274

public:

39275

explicit Struct_field(const Typed_identifier& typed_identifier)

39276

- : typed_identifier_(typed_identifier), tag_(NULL)

39277

+ : typed_identifier_(typed_identifier), tag_(NULL), is_imported_(false)

39278

{ }

39279

39280

// The field name.

39281

@@ -1926,6 +1948,10 @@

39282

bool

39283

is_field_name(const std::string& name) const;

39284

39285

+ // Return whether this struct field is an unexported field named NAME.

39286

+ bool

39287

+ is_unexported_field_name(Gogo*, const std::string& name) const;

39288

+

39289

// Return whether this struct field is an embedded built-in type.

39290

bool

39291

is_embedded_builtin(Gogo*) const;

39292

@@ -1963,6 +1989,11 @@

39293

set_tag(const std::string& tag)

39294

{ this->tag_ = new std::string(tag); }

39295

39296

+ // Record that this field is defined in an imported struct.

39297

+ void

39298

+ set_is_imported()

39299

+ { this->is_imported_ = true; }

39300

+

39301

// Set the type. This is only used in error cases.

39302

void

39303

set_type(Type* type)

39304

@@ -1973,6 +2004,8 @@

39305

Typed_identifier typed_identifier_;

39306

// The field tag. This is NULL if the field has no tag.

39307

std::string* tag_;

39308

+ // Whether this field is defined in an imported struct.

39309

+ bool is_imported_;

39310

};

39311

39312

// A list of struct fields.

39313

Index: gcc/go/gofrontend/parse.cc

39314

===================================================================

39315

--- a/src/gcc/go/gofrontend/parse.cc (.../tags/gcc_4_8_2_release)

39316

+++ b/src/gcc/go/gofrontend/parse.cc (.../branches/gcc-4_8-branch)

39317

@@ -744,6 +744,8 @@

39318

return NULL;

39319

39320

Parse::Names names;

39321

+ if (receiver != NULL)

39322

+ names[receiver->name()] = receiver;

39323

if (params != NULL)

39324

this->check_signature_names(params, &names);

39325

if (results != NULL)

39326

Index: gcc/go/gofrontend/import.h

39327

===================================================================

39328

--- a/src/gcc/go/gofrontend/import.h (.../tags/gcc_4_8_2_release)

39329

+++ b/src/gcc/go/gofrontend/import.h (.../branches/gcc-4_8-branch)

39330

@@ -149,6 +149,11 @@

39331

location() const

39332

{ return this->location_; }

39333

39334

+ // Return the package we are importing.

39335

+ Package*

39336

+ package() const

39337

+ { return this->package_; }

39338

+

39339

// Return the next character.

39340

int

39341

peek_char()

39342

Index: gcc/go/gofrontend/runtime.cc

39343

===================================================================

39344

--- a/src/gcc/go/gofrontend/runtime.cc (.../tags/gcc_4_8_2_release)

39345

+++ b/src/gcc/go/gofrontend/runtime.cc (.../branches/gcc-4_8-branch)

39346

@@ -42,6 +42,8 @@

39347

RFT_RUNE,

39348

// Go type float64, C type double.

39349

RFT_FLOAT64,

39350

+ // Go type complex64, C type __complex float.

39351

+ RFT_COMPLEX64,

39352

// Go type complex128, C type __complex double.

39353

RFT_COMPLEX128,

39354

// Go type string, C type struct __go_string.

39355

@@ -126,6 +128,10 @@

39356

t = Type::lookup_float_type("float64");

39357

break;

39358

39359

+ case RFT_COMPLEX64:

39360

+ t = Type::lookup_complex_type("complex64");

39361

+ break;

39362

+

39363

case RFT_COMPLEX128:

39364

t = Type::lookup_complex_type("complex128");

39365

break;

39366

@@ -216,6 +222,7 @@

39367

case RFT_UINTPTR:

39368

case RFT_RUNE:

39369

case RFT_FLOAT64:

39370

+ case RFT_COMPLEX64:

39371

case RFT_COMPLEX128:

39372

case RFT_STRING:

39373

case RFT_POINTER:

39374

Index: gcc/go/gofrontend/expressions.h

39375

===================================================================

39376

--- a/src/gcc/go/gofrontend/expressions.h (.../tags/gcc_4_8_2_release)

39377

+++ b/src/gcc/go/gofrontend/expressions.h (.../branches/gcc-4_8-branch)

39378

@@ -1514,8 +1514,8 @@

39379

closure()

39380

{ return this->closure_; }

39381

39382

- // Return a tree for the code for a function.

39383

- static tree

39384

+ // Return a backend expression for the code of a function.

39385

+ static Bexpression*

39386

get_code_pointer(Gogo*, Named_object* function, Location loc);

39387

39388

protected:

39389

Index: gcc/go/gofrontend/gogo-tree.cc

39390

===================================================================

39391

--- a/src/gcc/go/gofrontend/gogo-tree.cc (.../tags/gcc_4_8_2_release)

39392

+++ b/src/gcc/go/gofrontend/gogo-tree.cc (.../branches/gcc-4_8-branch)

39393

@@ -985,74 +985,6 @@

39394

delete[] vec;

39395

}

39396

39397

-// Get a tree for the identifier for a named object.

39398

-

39399

-tree

39400

-Named_object::get_id(Gogo* gogo)

39401

-{

39402

- go_assert(!this->is_variable() && !this->is_result_variable());

39403

- std::string decl_name;

39404

- if (this->is_function_declaration()

39405

- && !this->func_declaration_value()->asm_name().empty())

39406

- decl_name = this->func_declaration_value()->asm_name();

39407

- else if (this->is_type()

39408

- && Linemap::is_predeclared_location(this->type_value()->location()))

39409

- {

39410

- // We don't need the package name for builtin types.

39411

- decl_name = Gogo::unpack_hidden_name(this->name_);

39412

- }

39413

- else

39414

- {

39415

- std::string package_name;

39416

- if (this->package_ == NULL)

39417

- package_name = gogo->package_name();

39418

- else

39419

- package_name = this->package_->package_name();

39420

-

39421

- // Note that this will be misleading if this is an unexported

39422

- // method generated for an embedded imported type. In that case

39423

- // the unexported method should have the package name of the

39424

- // package from which it is imported, but we are going to give

39425

- // it our package name. Fixing this would require knowing the

39426

- // package name, but we only know the package path. It might be

39427

- // better to use package paths here anyhow. This doesn't affect

39428

- // the assembler code, because we always set that name in

39429

- // Function::get_or_make_decl anyhow. FIXME.

39430

-

39431

- decl_name = package_name + '.' + Gogo::unpack_hidden_name(this->name_);

39432

-

39433

- Function_type* fntype;

39434

- if (this->is_function())

39435

- fntype = this->func_value()->type();

39436

- else if (this->is_function_declaration())

39437

- fntype = this->func_declaration_value()->type();

39438

- else

39439

- fntype = NULL;

39440

- if (fntype != NULL && fntype->is_method())

39441

- {

39442

- decl_name.push_back('.');

39443

- decl_name.append(fntype->receiver()->type()->mangled_name(gogo));

39444

- }

39445

- }

39446

- if (this->is_type())

39447

- {

39448

- unsigned int index;

39449

- const Named_object* in_function = this->type_value()->in_function(&index);

39450

- if (in_function != NULL)

39451

- {

39452

- decl_name += '$' + Gogo::unpack_hidden_name(in_function->name());

39453

- if (index > 0)

39454

- {

39455

- char buf[30];

39456

- snprintf(buf, sizeof buf, "%u", index);

39457

- decl_name += '$';

39458

- decl_name += buf;

39459

- }

39460

- }

39461

- }

39462

- return get_identifier_from_string(decl_name);

39463

-}

39464

-

39465

// Get a tree for a named object.

39466

39467

tree

39468

@@ -1067,11 +999,6 @@

39469

return error_mark_node;

39470

}

39471

39472

- tree name;

39473

- if (this->classification_ == NAMED_OBJECT_TYPE)

39474

- name = NULL_TREE;

39475

- else

39476

- name = this->get_id(gogo);

39477

tree decl;

39478

switch (this->classification_)

39479

{

39480

@@ -1099,6 +1026,7 @@

39481

decl = error_mark_node;

39482

else if (INTEGRAL_TYPE_P(TREE_TYPE(expr_tree)))

39483

{

39484

+ tree name = get_identifier_from_string(this->get_id(gogo));

39485

decl = build_decl(named_constant->location().gcc_location(),

39486

CONST_DECL, name, TREE_TYPE(expr_tree));

39487

DECL_INITIAL(decl) = expr_tree;

39488

@@ -1161,7 +1089,7 @@

39489

case NAMED_OBJECT_FUNC:

39490

{

39491

Function* func = this->u_.func_value;

39492

- decl = func->get_or_make_decl(gogo, this, name);

39493

+ decl = function_to_tree(func->get_or_make_decl(gogo, this));

39494

if (decl != error_mark_node)

39495

{

39496

if (func->block() != NULL)

39497

@@ -1286,124 +1214,13 @@

39498

return block_tree;

39499

}

39500

39501

-// Get a tree for a function decl.

39502

+// Get the backend representation.

39503

39504

-tree

39505

-Function::get_or_make_decl(Gogo* gogo, Named_object* no, tree id)

39506

+Bfunction*

39507

+Function_declaration::get_or_make_decl(Gogo* gogo, Named_object* no)

39508

{

39509

- if (this->fndecl_ == NULL_TREE)

39510

+ if (this->fndecl_ == NULL)

39511

{

39512

- tree functype = type_to_tree(this->type_->get_backend(gogo));

39513

-

39514

- if (functype != error_mark_node)

39515

- {

39516

- // The type of a function comes back as a pointer to a

39517

- // struct whose first field is the function, but we want the

39518

- // real function type for a function declaration.

39519

- go_assert(POINTER_TYPE_P(functype)

39520

- && TREE_CODE(TREE_TYPE(functype)) == RECORD_TYPE);

39521

- functype = TREE_TYPE(TYPE_FIELDS(TREE_TYPE(functype)));

39522

- go_assert(FUNCTION_POINTER_TYPE_P(functype));

39523

- functype = TREE_TYPE(functype);

39524

- }

39525

-

39526

- if (functype == error_mark_node)

39527

- this->fndecl_ = error_mark_node;

39528

- else

39529

- {

39530

- tree decl = build_decl(this->location().gcc_location(), FUNCTION_DECL,

39531

- id, functype);

39532

-

39533

- this->fndecl_ = decl;

39534

-

39535

- if (no->package() != NULL)

39536

- ;

39537

- else if (this->enclosing_ != NULL || Gogo::is_thunk(no))

39538

- ;

39539

- else if (Gogo::unpack_hidden_name(no->name()) == "init"

39540

- && !this->type_->is_method())

39541

- ;

39542

- else if (Gogo::unpack_hidden_name(no->name()) == "main"

39543

- && gogo->is_main_package())

39544

- TREE_PUBLIC(decl) = 1;

39545

- // Methods have to be public even if they are hidden because

39546

- // they can be pulled into type descriptors when using

39547

- // anonymous fields.

39548

- else if (!Gogo::is_hidden_name(no->name())

39549

- || this->type_->is_method())

39550

- {

39551

- TREE_PUBLIC(decl) = 1;

39552

- std::string pkgpath = gogo->pkgpath_symbol();

39553

- if (this->type_->is_method()

39554

- && Gogo::is_hidden_name(no->name())

39555

- && Gogo::hidden_name_pkgpath(no->name()) != gogo->pkgpath())

39556

- {

39557

- // This is a method we created for an unexported

39558

- // method of an imported embedded type. We need to

39559

- // use the pkgpath of the imported package to avoid

39560

- // a possible name collision. See bug478 for a test

39561

- // case.

39562

- pkgpath = Gogo::hidden_name_pkgpath(no->name());

39563

- pkgpath = Gogo::pkgpath_for_symbol(pkgpath);

39564

- }

39565

-

39566

- std::string asm_name = pkgpath;

39567

- asm_name.append(1, '.');

39568

- asm_name.append(Gogo::unpack_hidden_name(no->name()));

39569

- if (this->type_->is_method())

39570

- {

39571

- asm_name.append(1, '.');

39572

- Type* rtype = this->type_->receiver()->type();

39573

- asm_name.append(rtype->mangled_name(gogo));

39574

- }

39575

- SET_DECL_ASSEMBLER_NAME(decl,

39576

- get_identifier_from_string(asm_name));

39577

- }

39578

-

39579

- // Why do we have to do this in the frontend?

39580

- tree restype = TREE_TYPE(functype);

39581

- tree resdecl =

39582

- build_decl(this->location().gcc_location(), RESULT_DECL, NULL_TREE,

39583

- restype);

39584

- DECL_ARTIFICIAL(resdecl) = 1;

39585

- DECL_IGNORED_P(resdecl) = 1;

39586

- DECL_CONTEXT(resdecl) = decl;

39587

- DECL_RESULT(decl) = resdecl;

39588

-

39589

- // If a function calls the predeclared recover function, we

39590

- // can't inline it, because recover behaves differently in a

39591

- // function passed directly to defer. If this is a recover

39592

- // thunk that we built to test whether a function can be

39593

- // recovered, we can't inline it, because that will mess up

39594

- // our return address comparison.

39595

- if (this->calls_recover_ || this->is_recover_thunk_)

39596

- DECL_UNINLINABLE(decl) = 1;

39597

-

39598

- // If this is a thunk created to call a function which calls

39599

- // the predeclared recover function, we need to disable

39600

- // stack splitting for the thunk.

39601

- if (this->is_recover_thunk_)

39602

- {

39603

- tree attr = get_identifier("__no_split_stack__");

39604

- DECL_ATTRIBUTES(decl) = tree_cons(attr, NULL_TREE, NULL_TREE);

39605

- }

39606

-

39607

- if (this->in_unique_section_)

39608

- resolve_unique_section (decl, 0, 1);

39609

-

39610

- go_preserve_from_gc(decl);

39611

- }

39612

- }

39613

- return this->fndecl_;

39614

-}

39615

-

39616

-// Get a tree for a function declaration.

39617

-

39618

-tree

39619

-Function_declaration::get_or_make_decl(Gogo* gogo, Named_object* no, tree id)

39620

-{

39621

- if (this->fndecl_ == NULL_TREE)

39622

- {

39623

// Let Go code use an asm declaration to pick up a builtin

39624

// function.

39625

if (!this->asm_name_.empty())

39626

@@ -1412,58 +1229,46 @@

39627

builtin_functions.find(this->asm_name_);

39628

if (p != builtin_functions.end())

39629

{

39630

- this->fndecl_ = p->second;

39631

+ this->fndecl_ = tree_to_function(p->second);

39632

return this->fndecl_;

39633

}

39634

}

39635

39636

- tree functype = type_to_tree(this->fntype_->get_backend(gogo));

39637

+ std::string asm_name;

39638

+ if (this->asm_name_.empty())

39639

+ {

39640

+ asm_name = (no->package() == NULL

39641

+ ? gogo->pkgpath_symbol()

39642

+ : no->package()->pkgpath_symbol());

39643

+ asm_name.append(1, '.');

39644

+ asm_name.append(Gogo::unpack_hidden_name(no->name()));

39645

+ if (this->fntype_->is_method())

39646

+ {

39647

+ asm_name.append(1, '.');

39648

+ Type* rtype = this->fntype_->receiver()->type();

39649

+ asm_name.append(rtype->mangled_name(gogo));

39650

+ }

39651

+ }

39652

39653

- if (functype != error_mark_node)

39654

- {

39655

- // The type of a function comes back as a pointer to a

39656

- // struct whose first field is the function, but we want the

39657

- // real function type for a function declaration.

39658

- go_assert(POINTER_TYPE_P(functype)

39659

- && TREE_CODE(TREE_TYPE(functype)) == RECORD_TYPE);

39660

- functype = TREE_TYPE(TYPE_FIELDS(TREE_TYPE(functype)));

39661

- go_assert(FUNCTION_POINTER_TYPE_P(functype));

39662

- functype = TREE_TYPE(functype);

39663

- }

39664

+ Btype* functype = this->fntype_->get_backend_fntype(gogo);

39665

+ this->fndecl_ =

39666

+ gogo->backend()->function(functype, no->get_id(gogo), asm_name,

39667

+ true, true, true, false, false,

39668

+ this->location());

39669

+ }

39670

39671

- tree decl;

39672

- if (functype == error_mark_node)

39673

- decl = error_mark_node;

39674

- else

39675

- {

39676

- decl = build_decl(this->location().gcc_location(), FUNCTION_DECL, id,

39677

- functype);

39678

- TREE_PUBLIC(decl) = 1;

39679

- DECL_EXTERNAL(decl) = 1;

39680

-

39681

- if (this->asm_name_.empty())

39682

- {

39683

- std::string asm_name = (no->package() == NULL

39684

- ? gogo->pkgpath_symbol()

39685

- : no->package()->pkgpath_symbol());

39686

- asm_name.append(1, '.');

39687

- asm_name.append(Gogo::unpack_hidden_name(no->name()));

39688

- if (this->fntype_->is_method())

39689

- {

39690

- asm_name.append(1, '.');

39691

- Type* rtype = this->fntype_->receiver()->type();

39692

- asm_name.append(rtype->mangled_name(gogo));

39693

- }

39694

- SET_DECL_ASSEMBLER_NAME(decl,

39695

- get_identifier_from_string(asm_name));

39696

- }

39697

- }

39698

- this->fndecl_ = decl;

39699

- go_preserve_from_gc(decl);

39700

- }

39701

return this->fndecl_;

39702

}

39703

39704

+// Return the function's decl after it has been built.

39705

+

39706

+tree

39707

+Function::get_decl() const

39708

+{

39709

+ go_assert(this->fndecl_ != NULL);

39710

+ return function_to_tree(this->fndecl_);

39711

+}

39712

+

39713

// We always pass the receiver to a method as a pointer. If the

39714

// receiver is actually declared as a non-pointer type, then we copy

39715

// the value into a local variable, so that it has the right type. In

39716

@@ -1558,7 +1363,7 @@

39717

void

39718

Function::build_tree(Gogo* gogo, Named_object* named_function)

39719

{

39720

- tree fndecl = this->fndecl_;

39721

+ tree fndecl = this->get_decl();

39722

go_assert(fndecl != NULL_TREE);

39723

39724

tree params = NULL_TREE;

39725

@@ -1796,7 +1601,7 @@

39726

set = NULL_TREE;

39727

else

39728

set = fold_build2_loc(end_loc.gcc_location(), MODIFY_EXPR, void_type_node,

39729

- DECL_RESULT(this->fndecl_), retval);

39730

+ DECL_RESULT(this->get_decl()), retval);

39731

tree ret_stmt = fold_build1_loc(end_loc.gcc_location(), RETURN_EXPR,

39732

void_type_node, set);

39733

append_to_statement_list(ret_stmt, &stmt_list);

39734

@@ -1851,7 +1656,7 @@

39735

retval = this->return_value(gogo, named_function, end_loc,

39736

&stmt_list);

39737

set = fold_build2_loc(end_loc.gcc_location(), MODIFY_EXPR, void_type_node,

39738

- DECL_RESULT(this->fndecl_), retval);

39739

+ DECL_RESULT(this->get_decl()), retval);

39740

ret_stmt = fold_build1_loc(end_loc.gcc_location(), RETURN_EXPR,

39741

void_type_node, set);

39742

39743

@@ -1869,7 +1674,7 @@

39744

*fini = stmt_list;

39745

}

39746

39747

-// Return the value to assign to DECL_RESULT(this->fndecl_). This may

39748

+// Return the value to assign to DECL_RESULT(this->get_decl()). This may

39749

// also add statements to STMT_LIST, which need to be executed before

39750

// the assignment. This is used for a return statement with no

39751

// explicit values.

39752

@@ -1902,7 +1707,7 @@

39753

}

39754

else

39755

{

39756

- tree rettype = TREE_TYPE(DECL_RESULT(this->fndecl_));

39757

+ tree rettype = TREE_TYPE(DECL_RESULT(this->get_decl()));

39758

retval = create_tmp_var(rettype, "RESULT");

39759

tree field = TYPE_FIELDS(rettype);

39760

int index = 0;

39761

@@ -2323,18 +2128,14 @@

39762

go_assert(m != NULL);

39763

39764

Named_object* no = m->named_object();

39765

-

39766

- tree fnid = no->get_id(this);

39767

-

39768

- tree fndecl;

39769

+ Bfunction* bf;

39770

if (no->is_function())

39771

- fndecl = no->func_value()->get_or_make_decl(this, no, fnid);

39772

+ bf = no->func_value()->get_or_make_decl(this, no);

39773

else if (no->is_function_declaration())

39774

- fndecl = no->func_declaration_value()->get_or_make_decl(this, no,

39775

- fnid);

39776

+ bf = no->func_declaration_value()->get_or_make_decl(this, no);

39777

else

39778

go_unreachable();

39779

- fndecl = build_fold_addr_expr(fndecl);

39780

+ tree fndecl = build_fold_addr_expr(function_to_tree(bf));

39781

39782

elt = pointers->quick_push(empty);

39783

elt->index = size_int(i);

39784

@@ -2353,10 +2154,11 @@

39785

TREE_CONSTANT(decl) = 1;

39786

DECL_INITIAL(decl) = constructor;

39787

39788

- // If the interface type has hidden methods, then this is the only

39789

- // definition of the table. Otherwise it is a comdat table which

39790

- // may be defined in multiple packages.

39791

- if (has_hidden_methods)

39792

+ // If the interface type has hidden methods, and the table is for a

39793

+ // named type, then this is the only definition of the table.

39794

+ // Otherwise it is a comdat table which may be defined in multiple

39795

+ // packages.

39796

+ if (has_hidden_methods && type->named_type() != NULL)

39797

TREE_PUBLIC(decl) = 1;

39798

else

39799

{

39800

Index: gcc/go/gofrontend/lex.cc

39801

===================================================================

39802

--- a/src/gcc/go/gofrontend/lex.cc (.../tags/gcc_4_8_2_release)

39803

+++ b/src/gcc/go/gofrontend/lex.cc (.../branches/gcc-4_8-branch)

39804

@@ -873,7 +873,28 @@

39805

&& (cc < 'a' || cc > 'z')

39806

&& cc != '_'

39807

&& (cc < '0' || cc > '9'))

39808

- break;

39809

+ {

39810

+ // Check for an invalid character here, as we get better

39811

+ // error behaviour if we swallow them as part of the

39812

+ // identifier we are building.

39813

+ if ((cc >= ' ' && cc < 0x7f)

39814

+ || cc == '\t'

39815

+ || cc == '\r'

39816

+ || cc == '\n')

39817

+ break;

39818

+

39819

+ this->lineoff_ = p - this->linebuf_;

39820

+ error_at(this->location(),

39821

+ "invalid character 0x%x in identifier",

39822

+ cc);

39823

+ if (!has_non_ascii_char)

39824

+ {

39825

+ buf.assign(pstart, p - pstart);

39826

+ has_non_ascii_char = true;

39827

+ }

39828

+ if (!Lex::is_invalid_identifier(buf))

39829

+ buf.append("$INVALID$");

39830

+ }

39831

++p;

39832

if (is_first)

39833

{

39834

Index: gcc/go/gofrontend/backend.h

39835

===================================================================

39836

--- a/src/gcc/go/gofrontend/backend.h (.../tags/gcc_4_8_2_release)

39837

+++ b/src/gcc/go/gofrontend/backend.h (.../branches/gcc-4_8-branch)

39838

@@ -23,7 +23,7 @@

39839

// The backend representation of a statement.

39840

class Bstatement;

39841

39842

-// The backend representation of a function definition.

39843

+// The backend representation of a function definition or declaration.

39844

class Bfunction;

39845

39846

// The backend representation of a block.

39847

@@ -266,6 +266,11 @@

39848

virtual Bexpression*

39849

convert_expression(Btype* type, Bexpression* expr, Location) = 0;

39850

39851

+ // Create an expression for the address of a function. This is used to

39852

+ // get the address of the code for a function.

39853

+ virtual Bexpression*

39854

+ function_code_expression(Bfunction*, Location) = 0;

39855

+

39856

// Statements.

39857

39858

// Create an error statement. This is used for cases which should

39859

@@ -498,6 +503,32 @@

39860

// recover.

39861

virtual Bexpression*

39862

label_address(Blabel*, Location) = 0;

39863

+

39864

+ // Functions.

39865

+

39866

+ // Create an error function. This is used for cases which should

39867

+ // not occur in a correct program, in order to keep the compilation

39868

+ // going without crashing.

39869

+ virtual Bfunction*

39870

+ error_function() = 0;

39871

+

39872

+ // Declare or define a function of FNTYPE.

39873

+ // NAME is the Go name of the function. ASM_NAME, if not the empty string, is

39874

+ // the name that should be used in the symbol table; this will be non-empty if

39875

+ // a magic extern comment is used.

39876

+ // IS_VISIBLE is true if this function should be visible outside of the

39877

+ // current compilation unit. IS_DECLARATION is true if this is a function

39878

+ // declaration rather than a definition; the function definition will be in

39879

+ // another compilation unit.

39880

+ // IS_INLINABLE is true if the function can be inlined.

39881

+ // DISABLE_SPLIT_STACK is true if this function may not split the stack; this

39882

+ // is used for the implementation of recover.

39883

+ // IN_UNIQUE_SECTION is true if this function should be put into a unique

39884

+ // location if possible; this is used for field tracking.

39885

+ virtual Bfunction*

39886

+ function(Btype* fntype, const std::string& name, const std::string& asm_name,

39887

+ bool is_visible, bool is_declaration, bool is_inlinable,

39888

+ bool disable_split_stack, bool in_unique_section, Location) = 0;

39889

};

39890

39891

// The backend interface has to define this function.

39892

@@ -517,5 +548,6 @@

39893

extern tree stat_to_tree(Bstatement*);

39894

extern tree block_to_tree(Bblock*);

39895

extern tree var_to_tree(Bvariable*);

39896

+extern tree function_to_tree(Bfunction*);

39897

39898

#endif // !defined(GO_BACKEND_H)

39899

Index: gcc/go/gofrontend/types.cc

39900

===================================================================

39901

--- a/src/gcc/go/gofrontend/types.cc (.../tags/gcc_4_8_2_release)

39902

+++ b/src/gcc/go/gofrontend/types.cc (.../branches/gcc-4_8-branch)

39903

@@ -1834,7 +1834,9 @@

39904

bloc);

39905

gogo->start_block(bloc);

39906

39907

- if (this->struct_type() != NULL)

39908

+ if (name != NULL && name->real_type()->named_type() != NULL)

39909

+ this->write_named_hash(gogo, name, hash_fntype, equal_fntype);

39910

+ else if (this->struct_type() != NULL)

39911

this->struct_type()->write_hash_function(gogo, name, hash_fntype,

39912

equal_fntype);

39913

else if (this->array_type() != NULL)

39914

@@ -1852,7 +1854,9 @@

39915

false, bloc);

39916

gogo->start_block(bloc);

39917

39918

- if (this->struct_type() != NULL)

39919

+ if (name != NULL && name->real_type()->named_type() != NULL)

39920

+ this->write_named_equal(gogo, name);

39921

+ else if (this->struct_type() != NULL)

39922

this->struct_type()->write_equal_function(gogo, name);

39923

else if (this->array_type() != NULL)

39924

this->array_type()->write_equal_function(gogo, name);

39925

@@ -1865,6 +1869,100 @@

39926

gogo->finish_function(bloc);

39927

}

39928

39929

+// Write a hash function that simply calls the hash function for a

39930

+// named type. This is used when one named type is defined as

39931

+// another. This ensures that this case works when the other named

39932

+// type is defined in another package and relies on calling hash

39933

+// functions defined only in that package.

39934

+

39935

+void

39936

+Type::write_named_hash(Gogo* gogo, Named_type* name,

39937

+ Function_type* hash_fntype, Function_type* equal_fntype)

39938

+{

39939

+ Location bloc = Linemap::predeclared_location();

39940

+

39941

+ Named_type* base_type = name->real_type()->named_type();

39942

+ go_assert(base_type != NULL);

39943

+

39944

+ // The pointer to the type we are going to hash. This is an

39945

+ // unsafe.Pointer.

39946

+ Named_object* key_arg = gogo->lookup("key", NULL);

39947

+ go_assert(key_arg != NULL);

39948

+

39949

+ // The size of the type we are going to hash.

39950

+ Named_object* keysz_arg = gogo->lookup("key_size", NULL);

39951

+ go_assert(keysz_arg != NULL);

39952

+

39953

+ Named_object* hash_fn;

39954

+ Named_object* equal_fn;

39955

+ name->real_type()->type_functions(gogo, base_type, hash_fntype, equal_fntype,

39956

+ &hash_fn, &equal_fn);

39957

+

39958

+ // Call the hash function for the base type.

39959

+ Expression* key_ref = Expression::make_var_reference(key_arg, bloc);

39960

+ Expression* keysz_ref = Expression::make_var_reference(keysz_arg, bloc);

39961

+ Expression_list* args = new Expression_list();

39962

+ args->push_back(key_ref);

39963

+ args->push_back(keysz_ref);

39964

+ Expression* func = Expression::make_func_reference(hash_fn, NULL, bloc);

39965

+ Expression* call = Expression::make_call(func, args, false, bloc);

39966

+

39967

+ // Return the hash of the base type.

39968

+ Expression_list* vals = new Expression_list();

39969

+ vals->push_back(call);

39970

+ Statement* s = Statement::make_return_statement(vals, bloc);

39971

+ gogo->add_statement(s);

39972

+}

39973

+

39974

+// Write an equality function that simply calls the equality function

39975

+// for a named type. This is used when one named type is defined as

39976

+// another. This ensures that this case works when the other named

39977

+// type is defined in another package and relies on calling equality

39978

+// functions defined only in that package.

39979

+

39980

+void

39981

+Type::write_named_equal(Gogo* gogo, Named_type* name)

39982

+{

39983

+ Location bloc = Linemap::predeclared_location();

39984

+

39985

+ // The pointers to the types we are going to compare. These have

39986

+ // type unsafe.Pointer.

39987

+ Named_object* key1_arg = gogo->lookup("key1", NULL);

39988

+ Named_object* key2_arg = gogo->lookup("key2", NULL);

39989

+ go_assert(key1_arg != NULL && key2_arg != NULL);

39990

+

39991

+ Named_type* base_type = name->real_type()->named_type();

39992

+ go_assert(base_type != NULL);

39993

+

39994

+ // Build temporaries with the base type.

39995

+ Type* pt = Type::make_pointer_type(base_type);

39996

+

39997

+ Expression* ref = Expression::make_var_reference(key1_arg, bloc);

39998

+ ref = Expression::make_cast(pt, ref, bloc);

39999

+ Temporary_statement* p1 = Statement::make_temporary(pt, ref, bloc);

40000

+ gogo->add_statement(p1);

40001

+

40002

+ ref = Expression::make_var_reference(key2_arg, bloc);

40003

+ ref = Expression::make_cast(pt, ref, bloc);

40004

+ Temporary_statement* p2 = Statement::make_temporary(pt, ref, bloc);

40005

+ gogo->add_statement(p2);

40006

+

40007

+ // Compare the values for equality.

40008

+ Expression* t1 = Expression::make_temporary_reference(p1, bloc);

40009

+ t1 = Expression::make_unary(OPERATOR_MULT, t1, bloc);

40010

+

40011

+ Expression* t2 = Expression::make_temporary_reference(p2, bloc);

40012

+ t2 = Expression::make_unary(OPERATOR_MULT, t2, bloc);

40013

+

40014

+ Expression* cond = Expression::make_binary(OPERATOR_EQEQ, t1, t2, bloc);

40015

+

40016

+ // Return the equality comparison.

40017

+ Expression_list* vals = new Expression_list();

40018

+ vals->push_back(cond);

40019

+ Statement* s = Statement::make_return_statement(vals, bloc);

40020

+ gogo->add_statement(s);

40021

+}

40022

+

40023

// Return a composite literal for the type descriptor for a plain type

40024

// of kind RUNTIME_TYPE_KIND named NAME.

40025

40026

@@ -2164,26 +2262,9 @@

40027

40028

++p;

40029

go_assert(p->is_field_name("typ"));

40030

- if (!only_value_methods && m->is_value_method())

40031

- {

40032

- // This is a value method on a pointer type. Change the type of

40033

- // the method to use a pointer receiver. The implementation

40034

- // always uses a pointer receiver anyhow.

40035

- Type* rtype = mtype->receiver()->type();

40036

- Type* prtype = Type::make_pointer_type(rtype);

40037

- Typed_identifier* receiver =

40038

- new Typed_identifier(mtype->receiver()->name(), prtype,

40039

- mtype->receiver()->location());

40040

- mtype = Type::make_function_type(receiver,

40041

- (mtype->parameters() == NULL

40042

- ? NULL

40043

- : mtype->parameters()->copy()),

40044

- (mtype->results() == NULL

40045

- ? NULL

40046

- : mtype->results()->copy()),

40047

- mtype->location());

40048

- }

40049

- vals->push_back(Expression::make_type_descriptor(mtype, bloc));

40050

+ bool want_pointer_receiver = !only_value_methods && m->is_value_method();

40051

+ nonmethod_type = mtype->copy_with_receiver_as_param(want_pointer_receiver);

40052

+ vals->push_back(Expression::make_type_descriptor(nonmethod_type, bloc));

40053

40054

++p;

40055

go_assert(p->is_field_name("tfn"));

40056

@@ -3383,6 +3464,68 @@

40057

// Get the backend representation for a function type.

40058

40059

Btype*

40060

+Function_type::get_backend_fntype(Gogo* gogo)

40061

+{

40062

+ if (this->fnbtype_ == NULL)

40063

+ {

40064

+ Backend::Btyped_identifier breceiver;

40065

+ if (this->receiver_ != NULL)

40066

+ {

40067

+ breceiver.name = Gogo::unpack_hidden_name(this->receiver_->name());

40068

+

40069

+ // We always pass the address of the receiver parameter, in

40070

+ // order to make interface calls work with unknown types.

40071

+ Type* rtype = this->receiver_->type();

40072

+ if (rtype->points_to() == NULL)

40073

+ rtype = Type::make_pointer_type(rtype);

40074

+ breceiver.btype = rtype->get_backend(gogo);

40075

+ breceiver.location = this->receiver_->location();

40076

+ }

40077

+

40078

+ std::vector<Backend::Btyped_identifier> bparameters;

40079

+ if (this->parameters_ != NULL)

40080

+ {

40081

+ bparameters.resize(this->parameters_->size());

40082

+ size_t i = 0;

40083

+ for (Typed_identifier_list::const_iterator p =

40084

+ this->parameters_->begin(); p != this->parameters_->end();

40085

+ ++p, ++i)

40086

+ {

40087

+ bparameters[i].name = Gogo::unpack_hidden_name(p->name());

40088

+ bparameters[i].btype = p->type()->get_backend(gogo);

40089

+ bparameters[i].location = p->location();

40090

+ }

40091

+ go_assert(i == bparameters.size());

40092

+ }

40093

+

40094

+ std::vector<Backend::Btyped_identifier> bresults;

40095

+ if (this->results_ != NULL)

40096

+ {

40097

+ bresults.resize(this->results_->size());

40098

+ size_t i = 0;

40099

+ for (Typed_identifier_list::const_iterator p =

40100

+ this->results_->begin(); p != this->results_->end();

40101

+ ++p, ++i)

40102

+ {

40103

+ bresults[i].name = Gogo::unpack_hidden_name(p->name());

40104

+ bresults[i].btype = p->type()->get_backend(gogo);

40105

+ bresults[i].location = p->location();

40106

+ }

40107

+ go_assert(i == bresults.size());

40108

+ }

40109

+

40110

+ this->fnbtype_ = gogo->backend()->function_type(breceiver, bparameters,

40111

+ bresults,

40112

+ this->location());

40113

+

40114

+ }

40115

+

40116

+ return this->fnbtype_;

40117

+}

40118

+

40119

+// Get the backend representation for a Go function type.

40120

+

40121

+Btype*

40122

Function_type::do_get_backend(Gogo* gogo)

40123

{

40124

// When we do anything with a function value other than call it, it

40125

@@ -3395,57 +3538,9 @@

40126

gogo->backend()->placeholder_struct_type("__go_descriptor", loc);

40127

Btype* ptr_struct_type = gogo->backend()->pointer_type(struct_type);

40128

40129

- Backend::Btyped_identifier breceiver;

40130

- if (this->receiver_ != NULL)

40131

- {

40132

- breceiver.name = Gogo::unpack_hidden_name(this->receiver_->name());

40133

-

40134

- // We always pass the address of the receiver parameter, in

40135

- // order to make interface calls work with unknown types.

40136

- Type* rtype = this->receiver_->type();

40137

- if (rtype->points_to() == NULL)

40138

- rtype = Type::make_pointer_type(rtype);

40139

- breceiver.btype = rtype->get_backend(gogo);

40140

- breceiver.location = this->receiver_->location();

40141

- }

40142

-

40143

- std::vector<Backend::Btyped_identifier> bparameters;

40144

- if (this->parameters_ != NULL)

40145

- {

40146

- bparameters.resize(this->parameters_->size());

40147

- size_t i = 0;

40148

- for (Typed_identifier_list::const_iterator p = this->parameters_->begin();

40149

- p != this->parameters_->end();

40150

- ++p, ++i)

40151

- {

40152

- bparameters[i].name = Gogo::unpack_hidden_name(p->name());

40153

- bparameters[i].btype = p->type()->get_backend(gogo);

40154

- bparameters[i].location = p->location();

40155

- }

40156

- go_assert(i == bparameters.size());

40157

- }

40158

-

40159

- std::vector<Backend::Btyped_identifier> bresults;

40160

- if (this->results_ != NULL)

40161

- {

40162

- bresults.resize(this->results_->size());

40163

- size_t i = 0;

40164

- for (Typed_identifier_list::const_iterator p = this->results_->begin();

40165

- p != this->results_->end();

40166

- ++p, ++i)

40167

- {

40168

- bresults[i].name = Gogo::unpack_hidden_name(p->name());

40169

- bresults[i].btype = p->type()->get_backend(gogo);

40170

- bresults[i].location = p->location();

40171

- }

40172

- go_assert(i == bresults.size());

40173

- }

40174

-

40175

- Btype* fntype = gogo->backend()->function_type(breceiver, bparameters,

40176

- bresults, loc);

40177

std::vector<Backend::Btyped_identifier> fields(1);

40178

fields[0].name = "code";

40179

- fields[0].btype = fntype;

40180

+ fields[0].btype = this->get_backend_fntype(gogo);

40181

fields[0].location = loc;

40182

if (!gogo->backend()->set_placeholder_struct_type(struct_type, fields))

40183

return gogo->backend()->error_type();

40184

@@ -3821,6 +3916,32 @@

40185

return ret;

40186

}

40187

40188

+// Make a copy of a function type with the receiver as the first

40189

+// parameter.

40190

+

40191

+Function_type*

40192

+Function_type::copy_with_receiver_as_param(bool want_pointer_receiver) const

40193

+{

40194

+ go_assert(this->is_method());

40195

+ Typed_identifier_list* new_params = new Typed_identifier_list();

40196

+ Type* rtype = this->receiver_->type();

40197

+ if (want_pointer_receiver)

40198

+ rtype = Type::make_pointer_type(rtype);

40199

+ Typed_identifier receiver(this->receiver_->name(), rtype,

40200

+ this->receiver_->location());

40201

+ new_params->push_back(receiver);

40202

+ const Typed_identifier_list* orig_params = this->parameters_;

40203

+ if (orig_params != NULL && !orig_params->empty())

40204

+ {

40205

+ for (Typed_identifier_list::const_iterator p = orig_params->begin();

40206

+ p != orig_params->end();

40207

+ ++p)

40208

+ new_params->push_back(*p);

40209

+ }

40210

+ return Type::make_function_type(NULL, new_params, this->results_,

40211

+ this->location_);

40212

+}

40213

+

40214

// Make a copy of a function type ignoring any receiver and adding a

40215

// closure parameter.

40216

40217

@@ -4195,7 +4316,8 @@

40218

40219

// This is a horrible hack caused by the fact that we don't pack

40220

// the names of builtin types. FIXME.

40221

- if (nt != NULL

40222

+ if (!this->is_imported_

40223

+ && nt != NULL

40224

&& nt->is_builtin()

40225

&& nt->name() == Gogo::unpack_hidden_name(name))

40226

return true;

40227

@@ -4204,6 +4326,36 @@

40228

}

40229

}

40230

40231

+// Return whether this field is an unexported field named NAME.

40232

+

40233

+bool

40234

+Struct_field::is_unexported_field_name(Gogo* gogo,

40235

+ const std::string& name) const

40236

+{

40237

+ const std::string& field_name(this->field_name());

40238

+ if (Gogo::is_hidden_name(field_name)

40239

+ && name == Gogo::unpack_hidden_name(field_name)

40240

+ && gogo->pack_hidden_name(name, false) != field_name)

40241

+ return true;

40242

+

40243

+ // Check for the name of a builtin type. This is like the test in

40244

+ // is_field_name, only there we return false if this->is_imported_,

40245

+ // and here we return true.

40246

+ if (this->is_imported_ && this->is_anonymous())

40247

+ {

40248

+ Type* t = this->typed_identifier_.type();

40249

+ if (t->points_to() != NULL)

40250

+ t = t->points_to();

40251

+ Named_type* nt = t->named_type();

40252

+ if (nt != NULL

40253

+ && nt->is_builtin()

40254

+ && nt->name() == Gogo::unpack_hidden_name(name))

40255

+ return true;

40256

+ }

40257

+

40258

+ return false;

40259

+}

40260

+

40261

// Return whether this field is an embedded built-in type.

40262

40263

bool

40264

@@ -4264,13 +4416,8 @@

40265

++p)

40266

{

40267

Type* t = p->type();

40268

- if (t->is_undefined())

40269

+ if (p->is_anonymous())

40270

{

40271

- error_at(p->location(), "struct field type is incomplete");

40272

- p->set_type(Type::make_error_type());

40273

- }

40274

- else if (p->is_anonymous())

40275

- {

40276

if (t->named_type() != NULL && t->points_to() != NULL)

40277

{

40278

error_at(p->location(), "embedded type may not be a pointer");

40279

@@ -4641,13 +4788,8 @@

40280

for (Struct_field_list::const_iterator pf = fields->begin();

40281

pf != fields->end();

40282

++pf)

40283

- {

40284

- const std::string& field_name(pf->field_name());

40285

- if (Gogo::is_hidden_name(field_name)

40286

- && name == Gogo::unpack_hidden_name(field_name)

40287

- && gogo->pack_hidden_name(name, false) != field_name)

40288

- return true;

40289

- }

40290

+ if (pf->is_unexported_field_name(gogo, name))

40291

+ return true;

40292

}

40293

return false;

40294

}

40295

@@ -5250,6 +5392,7 @@

40296

Type* ftype = imp->read_type();

40297

40298

Struct_field sf(Typed_identifier(name, ftype, imp->location()));

40299

+ sf.set_is_imported();

40300

40301

if (imp->peek_char() == ' ')

40302

{

40303

@@ -9022,6 +9165,8 @@

40304

fntype->is_varargs(), location);

40305

gogo->finish_function(fntype->location());

40306

40307

+ if (type->named_type() == NULL && stub->is_function())

40308

+ stub->func_value()->set_is_unnamed_type_stub_method();

40309

if (m->nointerface() && stub->is_function())

40310

stub->func_value()->set_nointerface();

40311

}

40312

@@ -9289,7 +9434,9 @@

40313

else

40314

{

40315

bool is_unexported;

40316

- if (!Gogo::is_hidden_name(name))

40317

+ // The test for 'a' and 'z' is to handle builtin names,

40318

+ // which are not hidden.

40319

+ if (!Gogo::is_hidden_name(name) && (name[0] < 'a' || name[0] > 'z'))

40320

is_unexported = false;

40321

else

40322

{

40323

Index: gcc/go/gofrontend/expressions.cc

40324

===================================================================

40325

--- a/src/gcc/go/gofrontend/expressions.cc (.../tags/gcc_4_8_2_release)

40326

+++ b/src/gcc/go/gofrontend/expressions.cc (.../branches/gcc-4_8-branch)

40327

@@ -1219,7 +1219,7 @@

40328

40329

// Get the tree for the code of a function expression.

40330

40331

-tree

40332

+Bexpression*

40333

Func_expression::get_code_pointer(Gogo* gogo, Named_object* no, Location loc)

40334

{

40335

Function_type* fntype;

40336

@@ -1237,25 +1237,18 @@

40337

error_at(loc,

40338

"invalid use of special builtin function %qs; must be called",

40339

no->message_name().c_str());

40340

- return error_mark_node;

40341

+ return gogo->backend()->error_expression();

40342

}

40343

40344

- tree id = no->get_id(gogo);

40345

- if (id == error_mark_node)

40346

- return error_mark_node;

40347

-

40348

- tree fndecl;

40349

+ Bfunction* fndecl;

40350

if (no->is_function())

40351

- fndecl = no->func_value()->get_or_make_decl(gogo, no, id);

40352

+ fndecl = no->func_value()->get_or_make_decl(gogo, no);

40353

else if (no->is_function_declaration())

40354

- fndecl = no->func_declaration_value()->get_or_make_decl(gogo, no, id);

40355

+ fndecl = no->func_declaration_value()->get_or_make_decl(gogo, no);

40356

else

40357

go_unreachable();

40358

40359

- if (fndecl == error_mark_node)

40360

- return error_mark_node;

40361

-

40362

- return build_fold_addr_expr_loc(loc.gcc_location(), fndecl);

40363

+ return gogo->backend()->function_code_expression(fndecl, loc);

40364

}

40365

40366

// Get the tree for a function expression. This is used when we take

40367

@@ -1492,8 +1485,10 @@

40368

tree

40369

Func_code_reference_expression::do_get_tree(Translate_context* context)

40370

{

40371

- return Func_expression::get_code_pointer(context->gogo(), this->function_,

40372

- this->location());

40373

+ Bexpression* ret =

40374

+ Func_expression::get_code_pointer(context->gogo(), this->function_,

40375

+ this->location());

40376

+ return expr_to_tree(ret);

40377

}

40378

40379

// Make a reference to the code of a function.

40380

@@ -3055,8 +3050,7 @@

40381

do_lower(Gogo*, Named_object*, Statement_inserter*, int);

40382

40383

bool

40384

- do_is_constant() const

40385

- { return this->expr_->is_constant(); }

40386

+ do_is_constant() const;

40387

40388

bool

40389

do_numeric_constant_value(Numeric_constant*) const;

40390

@@ -3198,6 +3192,27 @@

40391

return this;

40392

}

40393

40394

+// Return whether a type conversion is a constant.

40395

+

40396

+bool

40397

+Type_conversion_expression::do_is_constant() const

40398

+{

40399

+ if (!this->expr_->is_constant())

40400

+ return false;

40401

+

40402

+ // A conversion to a type that may not be used as a constant is not

40403

+ // a constant. For example, []byte(nil).

40404

+ Type* type = this->type_;

40405

+ if (type->integer_type() == NULL

40406

+ && type->float_type() == NULL

40407

+ && type->complex_type() == NULL

40408

+ && !type->is_boolean_type()

40409

+ && !type->is_string_type())

40410

+ return false;

40411

+

40412

+ return true;

40413

+}

40414

+

40415

// Return the constant numeric value if there is one.

40416

40417

bool

40418

@@ -5586,6 +5601,15 @@

40419

subcontext.type = NULL;

40420

}

40421

40422

+ if (this->op_ == OPERATOR_ANDAND || this->op_ == OPERATOR_OROR)

40423

+ {

40424

+ // For a logical operation, the context does not determine the

40425

+ // types of the operands. The operands must be some boolean

40426

+ // type but if the context has a boolean type they do not

40427

+ // inherit it. See http://golang.org/issue/3924.

40428

+ subcontext.type = NULL;

40429

+ }

40430

+

40431

// Set the context for the left hand operand.

40432

if (is_shift_op)

40433

{

40434

@@ -5967,6 +5991,43 @@

40435

right);

40436

}

40437

40438

+ // For complex division Go wants slightly different results than the

40439

+ // GCC library provides, so we have our own runtime routine.

40440

+ if (this->op_ == OPERATOR_DIV && this->left_->type()->complex_type() != NULL)

40441

+ {

40442

+ const char *name;

40443

+ tree *pdecl;

40444

+ Type* ctype;

40445

+ static tree complex64_div_decl;

40446

+ static tree complex128_div_decl;

40447

+ switch (this->left_->type()->complex_type()->bits())

40448

+ {

40449

+ case 64:

40450

+ name = "__go_complex64_div";

40451

+ pdecl = &complex64_div_decl;

40452

+ ctype = Type::lookup_complex_type("complex64");

40453

+ break;

40454

+ case 128:

40455

+ name = "__go_complex128_div";

40456

+ pdecl = &complex128_div_decl;

40457

+ ctype = Type::lookup_complex_type("complex128");

40458

+ break;

40459

+ default:

40460

+ go_unreachable();

40461

+ }

40462

+ Btype* cbtype = ctype->get_backend(gogo);

40463

+ tree ctype_tree = type_to_tree(cbtype);

40464

+ return Gogo::call_builtin(pdecl,

40465

+ this->location(),

40466

+ name,

40467

+ 2,

40468

+ ctype_tree,

40469

+ ctype_tree,

40470

+ fold_convert_loc(gccloc, ctype_tree, left),

40471

+ type,

40472

+ fold_convert_loc(gccloc, ctype_tree, right));

40473

+ }

40474

+

40475

tree compute_type = excess_precision_type(type);

40476

if (compute_type != NULL_TREE)

40477

{

40478

@@ -7191,6 +7252,15 @@

40479

if (this->code_ == BUILTIN_OFFSETOF)

40480

{

40481

Expression* arg = this->one_arg();

40482

+

40483

+ if (arg->bound_method_expression() != NULL

40484

+ || arg->interface_field_reference_expression() != NULL)

40485

+ {

40486

+ this->report_error(_("invalid use of method value as argument "

40487

+ "of Offsetof"));

40488

+ return this;

40489

+ }

40490

+

40491

Field_reference_expression* farg = arg->field_reference_expression();

40492

while (farg != NULL)

40493

{

40494

@@ -7200,7 +7270,8 @@

40495

// it must not be reached through pointer indirections.

40496

if (farg->expr()->deref() != farg->expr())

40497

{

40498

- this->report_error(_("argument of Offsetof implies indirection of an embedded field"));

40499

+ this->report_error(_("argument of Offsetof implies "

40500

+ "indirection of an embedded field"));

40501

return this;

40502

}

40503

// Go up until we reach the original base.

40504

@@ -7476,7 +7547,7 @@

40505

switch (nc.to_unsigned_long(&v))

40506

{

40507

case Numeric_constant::NC_UL_VALID:

40508

- return true;

40509

+ break;

40510

case Numeric_constant::NC_UL_NOTINT:

40511

error_at(e->location(), "non-integer %s argument to make",

40512

is_length ? "len" : "cap");

40513

@@ -7488,8 +7559,23 @@

40514

case Numeric_constant::NC_UL_BIG:

40515

// We don't want to give a compile-time error for a 64-bit

40516

// value on a 32-bit target.

40517

- return true;

40518

+ break;

40519

}

40520

+

40521

+ mpz_t val;

40522

+ if (!nc.to_int(&val))

40523

+ go_unreachable();

40524

+ int bits = mpz_sizeinbase(val, 2);

40525

+ mpz_clear(val);

40526

+ Type* int_type = Type::lookup_integer_type("int");

40527

+ if (bits >= int_type->integer_type()->bits())

40528

+ {

40529

+ error_at(e->location(), "%s argument too large for make",

40530

+ is_length ? "len" : "cap");

40531

+ return false;

40532

+ }

40533

+

40534

+ return true;

40535

}

40536

40537

if (e->type()->integer_type() != NULL)

40538

@@ -7595,6 +7681,8 @@

40539

bool

40540

Builtin_call_expression::do_is_constant() const

40541

{

40542

+ if (this->is_error_expression())

40543

+ return true;

40544

switch (this->code_)

40545

{

40546

case BUILTIN_LEN:

40547

@@ -9744,15 +9832,9 @@

40548

}

40549

40550

tree fntype_tree = type_to_tree(fntype->get_backend(gogo));

40551

- if (fntype_tree == error_mark_node)

40552

+ tree fnfield_type = type_to_tree(fntype->get_backend_fntype(gogo));

40553

+ if (fntype_tree == error_mark_node || fnfield_type == error_mark_node)

40554

return error_mark_node;

40555

- go_assert(POINTER_TYPE_P(fntype_tree));

40556

- if (TREE_TYPE(fntype_tree) == error_mark_node)

40557

- return error_mark_node;

40558

- go_assert(TREE_CODE(TREE_TYPE(fntype_tree)) == RECORD_TYPE);

40559

- tree fnfield_type = TREE_TYPE(TYPE_FIELDS(TREE_TYPE(fntype_tree)));

40560

- if (fnfield_type == error_mark_node)

40561

- return error_mark_node;

40562

go_assert(FUNCTION_POINTER_TYPE_P(fnfield_type));

40563

tree rettype = TREE_TYPE(TREE_TYPE(fnfield_type));

40564

if (rettype == error_mark_node)

40565

@@ -9763,7 +9845,7 @@

40566

if (func != NULL)

40567

{

40568

Named_object* no = func->named_object();

40569

- fn = Func_expression::get_code_pointer(gogo, no, location);

40570

+ fn = expr_to_tree(Func_expression::get_code_pointer(gogo, no, location));

40571

if (!has_closure)

40572

closure_tree = NULL_TREE;

40573

else

40574

@@ -10817,11 +10899,20 @@

40575

void

40576

String_index_expression::do_check_types(Gogo*)

40577

{

40578

- if (this->start_->type()->integer_type() == NULL)

40579

+ Numeric_constant nc;

40580

+ unsigned long v;

40581

+ if (this->start_->type()->integer_type() == NULL

40582

+ && !this->start_->type()->is_error()

40583

+ && (!this->start_->numeric_constant_value(&nc)

40584

+ || nc.to_unsigned_long(&v) == Numeric_constant::NC_UL_NOTINT))

40585

this->report_error(_("index must be integer"));

40586

if (this->end_ != NULL

40587

&& this->end_->type()->integer_type() == NULL

40588

- && !this->end_->is_nil_expression())

40589

+ && !this->end_->type()->is_error()

40590

+ && !this->end_->is_nil_expression()

40591

+ && !this->end_->is_error_expression()

40592

+ && (!this->end_->numeric_constant_value(&nc)

40593

+ || nc.to_unsigned_long(&v) == Numeric_constant::NC_UL_NOTINT))

40594

this->report_error(_("slice end must be integer"));

40595

40596

std::string sval;

40597

Index: gcc/opts.c

40598

===================================================================

40599

--- a/src/gcc/opts.c (.../tags/gcc_4_8_2_release)

40600

+++ b/src/gcc/opts.c (.../branches/gcc-4_8-branch)

40601

@@ -425,8 +425,8 @@

40602

{ OPT_LEVELS_1_PLUS, OPT_fguess_branch_probability, NULL, 1 },

40603

{ OPT_LEVELS_1_PLUS, OPT_fcprop_registers, NULL, 1 },

40604

{ OPT_LEVELS_1_PLUS, OPT_fforward_propagate, NULL, 1 },

40605

- { OPT_LEVELS_1_PLUS, OPT_fif_conversion, NULL, 1 },

40606

- { OPT_LEVELS_1_PLUS, OPT_fif_conversion2, NULL, 1 },

40607

+ { OPT_LEVELS_1_PLUS_NOT_DEBUG, OPT_fif_conversion, NULL, 1 },

40608

+ { OPT_LEVELS_1_PLUS_NOT_DEBUG, OPT_fif_conversion2, NULL, 1 },

40609

{ OPT_LEVELS_1_PLUS, OPT_fipa_pure_const, NULL, 1 },

40610

{ OPT_LEVELS_1_PLUS, OPT_fipa_reference, NULL, 1 },

40611

{ OPT_LEVELS_1_PLUS, OPT_fipa_profile, NULL, 1 },

40612

Index: gcc/recog.c

40613

===================================================================

40614

--- a/src/gcc/recog.c (.../tags/gcc_4_8_2_release)

40615

+++ b/src/gcc/recog.c (.../branches/gcc-4_8-branch)

40616

@@ -3061,6 +3061,9 @@

40617

return 1;

40618

}

40619

40620

+/* Regno offset to be used in the register search. */

40621

+static int search_ofs;

40622

+

40623

/* Try to find a hard register of mode MODE, matching the register class in

40624

CLASS_STR, which is available at the beginning of insn CURRENT_INSN and

40625

remains available until the end of LAST_INSN. LAST_INSN may be NULL_RTX,

40626

@@ -3076,7 +3079,6 @@

40627

peep2_find_free_register (int from, int to, const char *class_str,

40628

enum machine_mode mode, HARD_REG_SET *reg_set)

40629

{

40630

- static int search_ofs;

40631

enum reg_class cl;

40632

HARD_REG_SET live;

40633

df_ref *def_rec;

40634

@@ -3541,6 +3543,7 @@

40635

/* Initialize the regsets we're going to use. */

40636

for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)

40637

peep2_insn_data[i].live_before = BITMAP_ALLOC (&reg_obstack);

40638

+ search_ofs = 0;

40639

live = BITMAP_ALLOC (&reg_obstack);

40640

40641

FOR_EACH_BB_REVERSE (bb)

40642

Index: gcc/ada/system-linux-s390x.ads

40643

===================================================================

40644

--- a/src/gcc/ada/system-linux-s390x.ads (.../tags/gcc_4_8_2_release)

40645

+++ b/src/gcc/ada/system-linux-s390x.ads (.../branches/gcc-4_8-branch)

40646

@@ -7,7 +7,7 @@

40647

-- S p e c --

40648

-- (GNU-Linux/s390x Version) --

40649

-- --

40650

40651

40652

-- --

40653

-- This specification is derived from the Ada Reference Manual for use with --

40654

-- GNAT. The copyright notice above, and the license provisions that follow --

40655

@@ -35,9 +35,10 @@

40656

------------------------------------------------------------------------------

40657

40658

package System is

40659

-pragma Pure (System);

40660

--- Note that we take advantage of the implementation permission to

40661

--- make this unit Pure instead of Preelaborable, see RM 13.7(36)

40662

+ pragma Pure;

40663

+ -- Note that we take advantage of the implementation permission to make

40664

+ -- this unit Pure instead of Preelaborable; see RM 13.7.1(15). In Ada

40665

+ -- 2005, this is Pure in any case (AI-362).

40666

40667

type Name is (SYSTEM_NAME_GNAT);

40668

System_Name : constant Name := SYSTEM_NAME_GNAT;

40669

@@ -61,6 +62,7 @@

40670

-- Storage-related Declarations

40671

40672

type Address is private;

40673

+ pragma Preelaborable_Initialization (Address);

40674

Null_Address : constant Address;

40675

40676

Storage_Unit : constant := 8;

40677

Index: gcc/ada/system-linux-alpha.ads

40678

===================================================================

40679

--- a/src/gcc/ada/system-linux-alpha.ads (.../tags/gcc_4_8_2_release)

40680

+++ b/src/gcc/ada/system-linux-alpha.ads (.../branches/gcc-4_8-branch)

40681

@@ -7,7 +7,7 @@

40682

-- S p e c --

40683

-- (GNU-Linux/alpha Version) --

40684

-- --

40685

40686

40687

-- --

40688

-- This specification is derived from the Ada Reference Manual for use with --

40689

-- GNAT. The copyright notice above, and the license provisions that follow --

40690

@@ -35,9 +35,10 @@

40691

------------------------------------------------------------------------------

40692

40693

package System is

40694

-pragma Pure (System);

40695

--- Note that we take advantage of the implementation permission to

40696

--- make this unit Pure instead of Preelaborable, see RM 13.7(36)

40697

+ pragma Pure;

40698

+ -- Note that we take advantage of the implementation permission to make

40699

+ -- this unit Pure instead of Preelaborable; see RM 13.7.1(15). In Ada

40700

+ -- 2005, this is Pure in any case (AI-362).

40701

40702

type Name is (SYSTEM_NAME_GNAT);

40703

System_Name : constant Name := SYSTEM_NAME_GNAT;

40704

@@ -61,6 +62,7 @@

40705

-- Storage-related Declarations

40706

40707

type Address is private;

40708

+ pragma Preelaborable_Initialization (Address);

40709

Null_Address : constant Address;

40710

40711

Storage_Unit : constant := 8;

40712

Index: gcc/ada/system-vxworks-arm.ads

40713

===================================================================

40714

--- a/src/gcc/ada/system-vxworks-arm.ads (.../tags/gcc_4_8_2_release)

40715

+++ b/src/gcc/ada/system-vxworks-arm.ads (.../branches/gcc-4_8-branch)

40716

@@ -7,7 +7,7 @@

40717

-- S p e c --

40718

-- (VxWorks Version ARM) --

40719

-- --

40720

40721

40722

-- --

40723

-- This specification is derived from the Ada Reference Manual for use with --

40724

-- GNAT. The copyright notice above, and the license provisions that follow --

40725

@@ -35,10 +35,10 @@

40726

------------------------------------------------------------------------------

40727

40728

package System is

40729

-pragma Pure (System);

40730

--- Note that we take advantage of the implementation permission to make this

40731

--- unit Pure instead of Preelaborable; see RM 13.7.1(15). In Ada 2005, this is

40732

--- Pure in any case (AI-362).

40733

+ pragma Pure;

40734

+ -- Note that we take advantage of the implementation permission to make

40735

+ -- this unit Pure instead of Preelaborable; see RM 13.7.1(15). In Ada

40736

+ -- 2005, this is Pure in any case (AI-362).

40737

40738

type Name is (SYSTEM_NAME_GNAT);

40739

System_Name : constant Name := SYSTEM_NAME_GNAT;

40740

Index: gcc/ada/system-linux-s390.ads

40741

===================================================================

40742

--- a/src/gcc/ada/system-linux-s390.ads (.../tags/gcc_4_8_2_release)

40743

+++ b/src/gcc/ada/system-linux-s390.ads (.../branches/gcc-4_8-branch)

40744

@@ -7,7 +7,7 @@

40745

-- S p e c --

40746

-- (GNU-Linux/s390 Version) --

40747

-- --

40748

40749

40750

-- --

40751

-- This specification is derived from the Ada Reference Manual for use with --

40752

-- GNAT. The copyright notice above, and the license provisions that follow --

40753

@@ -35,9 +35,10 @@

40754

------------------------------------------------------------------------------

40755

40756

package System is

40757

-pragma Pure (System);

40758

--- Note that we take advantage of the implementation permission to

40759

--- make this unit Pure instead of Preelaborable, see RM 13.7(36)

40760

+ pragma Pure;

40761

+ -- Note that we take advantage of the implementation permission to make

40762

+ -- this unit Pure instead of Preelaborable; see RM 13.7.1(15). In Ada

40763

+ -- 2005, this is Pure in any case (AI-362).

40764

40765

type Name is (SYSTEM_NAME_GNAT);

40766

System_Name : constant Name := SYSTEM_NAME_GNAT;

40767

@@ -61,6 +62,7 @@

40768

-- Storage-related Declarations

40769

40770

type Address is private;

40771

+ pragma Preelaborable_Initialization (Address);

40772

Null_Address : constant Address;

40773

40774

Storage_Unit : constant := 8;

40775

Index: gcc/ada/indepsw-darwin.adb

40776

===================================================================

40777

--- a/src/gcc/ada/indepsw-darwin.adb (.../tags/gcc_4_8_2_release)

40778

+++ b/src/gcc/ada/indepsw-darwin.adb (.../branches/gcc-4_8-branch)

40779

@@ -0,0 +1,67 @@

40780

+------------------------------------------------------------------------------

40781

+-- --

40782

+-- GNAT COMPILER COMPONENTS --

40783

+-- --

40784

+-- I N D E P S W --

40785

+-- --

40786

+-- B o d y --

40787

+-- (Darwin version) --

40788

+-- --

40789

40790

+-- --

40791

+-- GNAT is free software; you can redistribute it and/or modify it under --

40792

+-- terms of the GNU General Public License as published by the Free Soft- --

40793

+-- ware Foundation; either version 3, or (at your option) any later ver- --

40794

+-- sion. GNAT is distributed in the hope that it will be useful, but WITH- --

40795

+-- OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY --

40796

+-- or FITNESS FOR A PARTICULAR PURPOSE. --

40797

+-- --

40798

+-- As a special exception under Section 7 of GPL version 3, you are granted --

40799

+-- additional permissions described in the GCC Runtime Library Exception, --

40800

+-- version 3.1, as published by the Free Software Foundation. --

40801

+-- --

40802

+-- You should have received a copy of the GNU General Public License and --

40803

+-- a copy of the GCC Runtime Library Exception along with this program; --

40804

+-- see the files COPYING3 and COPYING.RUNTIME respectively. If not, see --

40805

+-- <http://www.gnu.org/licenses/>. --

40806

+-- --

40807

+-- GNAT was originally developed by the GNAT team at New York University. --

40808

+-- Extensive contributions were provided by Ada Core Technologies Inc. --

40809

+-- --

40810

+------------------------------------------------------------------------------

40811

+

40812

+-- This is the Darwin version

40813

+

40814

+package body Indepsw is

40815

+

40816

+ Map_Switch : aliased constant String := "-Wl,-map,";

40817

+

40818

+ -------------

40819

+ -- Convert --

40820

+ -------------

40821

+

40822

+ procedure Convert

40823

+ (Switch : Switch_Kind;

40824

+ Argument : String;

40825

+ To : out String_List_Access)

40826

+ is

40827

+ begin

40828

+ case Switch is

40829

+ when Map_File =>

40830

+ To := new Argument_List'(1 => new String'(Map_Switch & Argument));

40831

+ end case;

40832

+ end Convert;

40833

+

40834

+ ------------------

40835

+ -- Is_Supported --

40836

+ ------------------

40837

+

40838

+ function Is_Supported (Switch : Switch_Kind) return Boolean is

40839

+ begin

40840

+ case Switch is

40841

+ when Map_File =>

40842

+ return True;

40843

+ end case;

40844

+ end Is_Supported;

40845

+

40846

+end Indepsw;

40847

Index: gcc/ada/system-linux-sparcv9.ads

40848

===================================================================

40849

--- a/src/gcc/ada/system-linux-sparcv9.ads (.../tags/gcc_4_8_2_release)

40850

+++ b/src/gcc/ada/system-linux-sparcv9.ads (.../branches/gcc-4_8-branch)

40851

@@ -7,7 +7,7 @@

40852

-- S p e c --

40853

-- (GNU/Linux-SPARCV9 Version) --

40854

-- --

40855

40856

40857

-- --

40858

-- This specification is derived from the Ada Reference Manual for use with --

40859

-- GNAT. The copyright notice above, and the license provisions that follow --

40860

@@ -35,9 +35,10 @@

40861

------------------------------------------------------------------------------

40862

40863

package System is

40864

-pragma Pure (System);

40865

--- Note that we take advantage of the implementation permission to

40866

--- make this unit Pure instead of Preelaborable, see RM 13.7(36)

40867

+ pragma Pure;

40868

+ -- Note that we take advantage of the implementation permission to make

40869

+ -- this unit Pure instead of Preelaborable; see RM 13.7.1(15). In Ada

40870

+ -- 2005, this is Pure in any case (AI-362).

40871

40872

type Name is (SYSTEM_NAME_GNAT);

40873

System_Name : constant Name := SYSTEM_NAME_GNAT;

40874

@@ -61,6 +62,7 @@

40875

-- Storage-related Declarations

40876

40877

type Address is private;

40878

+ pragma Preelaborable_Initialization (Address);

40879

Null_Address : constant Address;

40880

40881

Storage_Unit : constant := 8;

40882

Index: gcc/ada/ChangeLog

40883

===================================================================

40884

--- a/src/gcc/ada/ChangeLog (.../tags/gcc_4_8_2_release)

40885

+++ b/src/gcc/ada/ChangeLog (.../branches/gcc-4_8-branch)

40886

@@ -1,3 +1,60 @@

40887

+2014-03-30 Eric Botcazou <ebotcazou@adacore.com>

40888

+

40889

+ PR ada/60703

40890

+ * system-linux-alpha.ads: Adjust for Ada 2005.

40891

+ * system-linux-mips.ads: Likewise.

40892

+ * system-linux-mips64el.ads: Likewise.

40893

+ * system-linux-mipsel.ads: Likewise.

40894

+ * system-linux-s390.ads: Likewise.

40895

+ * system-linux-s390x.ads: Likewise.

40896

+ * system-linux-sparc.ads: Likewise.

40897

+ * system-linux-sparcv9.ads: Likewise.

40898

+ * system-rtems.ads: Likewise.

40899

+ * system-vxworks-arm.ads: Likewise.

40900

+

40901

+2014-03-13 Eric Botcazou <ebotcazou@adacore.com>

40902

+

40903

+ PR ada/51483

40904

+ * back_end.ads (Register_Type_Proc): Add 'precision' parameter.

40905

+ * cstand.adb (Register_Float_Type): Add 'precision' parameter and use

40906

+ it to set the RM size. Use directly 'size' for the Esize.

40907

+ * gcc-interface/gigi.h (enumerate_modes): Add integer parameter.

40908

+ * gcc-interface/misc.c (enumerate_modes): Likewise. Do not register

40909

+ types for vector modes, pass the size in addition to the precision.

40910

+

40911

+2014-01-12 Eric Botcazou <ebotcazou@adacore.com>

40912

+

40913

+ PR ada/59772

40914

+ * gcc-interface/cuintp.c (build_cst_from_int): Use 32-bit integer type

40915

+ as intermediate type.

40916

+ (UI_To_gnu): Likewise.

40917

+

40918

+2013-12-12 Eric Botcazou <ebotcazou@adacore.com>

40919

+ Iain Sandoe <iain@codesourcery.com>

40920

+

40921

+ PR ada/55946

40922

+ * gcc-interface/Make-lang.in (ada/doctools/xgnatugn): Use gnatmake.

40923

+ * gcc-interface/Makefile.in (GCC_LINK): Add LDFLAGS.

40924

+ (../../gnatmake): Remove LDFLAGS.

40925

+ (../../gnatlink): Likewise.

40926

+

40927

+2013-12-04 Eric Botcazou <ebotcazou@adacore.com>

40928

+

40929

+ PR ada/59382

40930

+ * indepsw-darwin.adb: New file.

40931

+

40932

+2013-10-19 Eric Botcazou <ebotcazou@adacore.com>

40933

+

40934

+ * gcc-interface/utils.c (scale_by_factor_of): New function.

40935

+ (rest_of_record_type_compilation): Use scale_by_factor_of in order to

40936

+ scale the original offset for both rounding cases; in the second case,

40937

+ take into accout the addend to compute the alignment. Tidy up.

40938

+

40939

+2013-10-19 Eric Botcazou <ebotcazou@adacore.com>

40940

+

40941

+ * gcc-interface/utils.c (gnat_set_type_context): New function.

40942

+ (gnat_pushdecl): Use it to set the context of the type.

40943

+

40944

2013-10-16 Release Manager

40945

40946

* GCC 4.8.2 released.

40947

Index: gcc/ada/cstand.adb

40948

===================================================================

40949

--- a/src/gcc/ada/cstand.adb (.../tags/gcc_4_8_2_release)

40950

+++ b/src/gcc/ada/cstand.adb (.../branches/gcc-4_8-branch)

40951

@@ -151,6 +151,7 @@

40952

Complex : Boolean; -- True iff type has real and imaginary parts

40953

Count : Natural; -- Number of elements in vector, 0 otherwise

40954

Float_Rep : Float_Rep_Kind; -- Representation used for fpt type

40955

+ Precision : Positive; -- Precision of representation in bits

40956

Size : Positive; -- Size of representation in bits

40957

Alignment : Natural); -- Required alignment in bits

40958

pragma Convention (C, Register_Float_Type);

40959

@@ -2014,6 +2015,7 @@

40960

Complex : Boolean;

40961

Count : Natural;

40962

Float_Rep : Float_Rep_Kind;

40963

+ Precision : Positive;

40964

Size : Positive;

40965

Alignment : Natural)

40966

is

40967

@@ -2063,14 +2065,25 @@

40968

40969

else

40970

Write_Str ("mod 2**");

40971

- Write_Int (Int (Size / Positive'Max (1, Count)));

40972

+ Write_Int (Int (Precision / Positive'Max (1, Count)));

40973

Write_Line (";");

40974

end if;

40975

40976

- Write_Str ("for " & T & "'Size use ");

40977

- Write_Int (Int (Size));

40978

- Write_Line (";");

40979

+ if Precision = Size then

40980

+ Write_Str ("for " & T (1 .. Last) & "'Size use ");

40981

+ Write_Int (Int (Size));

40982

+ Write_Line (";");

40983

40984

+ else

40985

+ Write_Str ("for " & T (1 .. Last) & "'Value_Size use ");

40986

+ Write_Int (Int (Precision));

40987

+ Write_Line (";");

40988

+

40989

+ Write_Str ("for " & T (1 .. Last) & "'Object_Size use ");

40990

+ Write_Int (Int (Size));

40991

+ Write_Line (";");

40992

+ end if;

40993

+

40994

Write_Str ("for " & T & "'Alignment use ");

40995

Write_Int (Int (Alignment / 8));

40996

Write_Line (";");

40997

@@ -2092,15 +2105,13 @@

40998

if Digs > 0 and then not Complex and then Count = 0 then

40999

declare

41000

Ent : constant Entity_Id := New_Standard_Entity;

41001

- Esize : constant Pos := Pos ((Size + Alignment - 1)

41002

- / Alignment * Alignment);

41003

begin

41004

Set_Defining_Identifier

41005

(New_Node (N_Full_Type_Declaration, Stloc), Ent);

41006

Make_Name (Ent, T (1 .. Last));

41007

Set_Scope (Ent, Standard_Standard);

41008

- Build_Float_Type (Ent, Esize, Float_Rep, Pos (Digs));

41009

- Set_RM_Size (Ent, UI_From_Int (Int (Size)));

41010

+ Build_Float_Type (Ent, Int (Size), Float_Rep, Pos (Digs));

41011

+ Set_RM_Size (Ent, UI_From_Int (Int (Precision)));

41012

Set_Alignment (Ent, UI_From_Int (Int (Alignment / 8)));

41013

41014

if No (Back_End_Float_Types) then

41015

Index: gcc/ada/back_end.ads

41016

===================================================================

41017

--- a/src/gcc/ada/back_end.ads (.../tags/gcc_4_8_2_release)

41018

+++ b/src/gcc/ada/back_end.ads (.../branches/gcc-4_8-branch)

41019

@@ -55,6 +55,7 @@

41020

Complex : Boolean; -- True iff type has real and imaginary parts

41021

Count : Natural; -- Number of elements in vector, 0 otherwise

41022

Float_Rep : Float_Rep_Kind; -- Representation used for fpt type

41023

+ Precision : Positive; -- Precision of representation in bits

41024

Size : Positive; -- Size of representation in bits

41025

Alignment : Natural); -- Required alignment in bits

41026

pragma Convention (C, Register_Type_Proc);

41027

Index: gcc/ada/system-linux-mipsel.ads

41028

===================================================================

41029

--- a/src/gcc/ada/system-linux-mipsel.ads (.../tags/gcc_4_8_2_release)

41030

+++ b/src/gcc/ada/system-linux-mipsel.ads (.../branches/gcc-4_8-branch)

41031

@@ -7,7 +7,7 @@

41032

-- S p e c --

41033

-- (GNU-Linux/MIPSEL Version) --

41034

-- --

41035

41036

41037

-- --

41038

-- This specification is derived from the Ada Reference Manual for use with --

41039

-- GNAT. The copyright notice above, and the license provisions that follow --

41040

@@ -62,6 +62,7 @@

41041

-- Storage-related Declarations

41042

41043

type Address is private;

41044

+ pragma Preelaborable_Initialization (Address);

41045

Null_Address : constant Address;

41046

41047

Storage_Unit : constant := 8;

41048

Index: gcc/ada/system-linux-mips.ads

41049

===================================================================

41050

--- a/src/gcc/ada/system-linux-mips.ads (.../tags/gcc_4_8_2_release)

41051

+++ b/src/gcc/ada/system-linux-mips.ads (.../branches/gcc-4_8-branch)

41052

@@ -7,7 +7,7 @@

41053

-- S p e c --

41054

-- (GNU-Linux/MIPS Version) --

41055

-- --

41056

41057

41058

-- --

41059

-- This specification is derived from the Ada Reference Manual for use with --

41060

-- GNAT. The copyright notice above, and the license provisions that follow --

41061

@@ -62,6 +62,7 @@

41062

-- Storage-related Declarations

41063

41064

type Address is private;

41065

+ pragma Preelaborable_Initialization (Address);

41066

Null_Address : constant Address;

41067

41068

Storage_Unit : constant := 8;

41069

Index: gcc/ada/system-linux-mips64el.ads

41070

===================================================================

41071

--- a/src/gcc/ada/system-linux-mips64el.ads (.../tags/gcc_4_8_2_release)

41072

+++ b/src/gcc/ada/system-linux-mips64el.ads (.../branches/gcc-4_8-branch)

41073

@@ -7,7 +7,7 @@

41074

-- S p e c --

41075

-- (GNU-Linux/MIPS64EL Version) --

41076

-- --

41077

41078

41079

-- --

41080

-- This specification is derived from the Ada Reference Manual for use with --

41081

-- GNAT. The copyright notice above, and the license provisions that follow --

41082

@@ -62,6 +62,7 @@

41083

-- Storage-related Declarations

41084

41085

type Address is private;

41086

+ pragma Preelaborable_Initialization (Address);

41087

Null_Address : constant Address;

41088

41089

Storage_Unit : constant := 8;

41090

Index: gcc/ada/gcc-interface/utils.c

41091

===================================================================

41092

--- a/src/gcc/ada/gcc-interface/utils.c (.../tags/gcc_4_8_2_release)

41093

+++ b/src/gcc/ada/gcc-interface/utils.c (.../branches/gcc-4_8-branch)

41094

@@ -232,6 +232,7 @@

41095

static tree split_plus (tree, tree *);

41096

static tree float_type_for_precision (int, enum machine_mode);

41097

static tree convert_to_fat_pointer (tree, tree);

41098

+static unsigned int scale_by_factor_of (tree, unsigned int);

41099

static bool potential_alignment_gap (tree, tree, tree);

41100

static void process_attributes (tree, struct attrib *);

41101

41102

@@ -532,6 +533,22 @@

41103

free_binding_level = level;

41104

}

41105

41106

+/* Set the context of TYPE and its parallel types (if any) to CONTEXT. */

41107

+

41108

+static void

41109

+gnat_set_type_context (tree type, tree context)

41110

+{

41111

+ tree decl = TYPE_STUB_DECL (type);

41112

+

41113

+ TYPE_CONTEXT (type) = context;

41114

+

41115

+ while (decl && DECL_PARALLEL_TYPE (decl))

41116

+ {

41117

+ TYPE_CONTEXT (DECL_PARALLEL_TYPE (decl)) = context;

41118

+ decl = TYPE_STUB_DECL (DECL_PARALLEL_TYPE (decl));

41119

+ }

41120

+}

41121

+

41122

/* Record DECL as belonging to the current lexical scope and use GNAT_NODE

41123

for location information and flag propagation. */

41124

41125

@@ -613,7 +630,7 @@

41126

if (TREE_CODE (t) == POINTER_TYPE)

41127

TYPE_NEXT_PTR_TO (t) = tt;

41128

TYPE_NAME (tt) = DECL_NAME (decl);

41129

- TYPE_CONTEXT (tt) = DECL_CONTEXT (decl);

41130

+ gnat_set_type_context (tt, DECL_CONTEXT (decl));

41131

TYPE_STUB_DECL (tt) = TYPE_STUB_DECL (t);

41132

DECL_ORIGINAL_TYPE (decl) = tt;

41133

}

41134

@@ -623,7 +640,7 @@

41135

/* We need a variant for the placeholder machinery to work. */

41136

tree tt = build_variant_type_copy (t);

41137

TYPE_NAME (tt) = decl;

41138

- TYPE_CONTEXT (tt) = DECL_CONTEXT (decl);

41139

+ gnat_set_type_context (tt, DECL_CONTEXT (decl));

41140

TREE_USED (tt) = TREE_USED (t);

41141

TREE_TYPE (decl) = tt;

41142

if (DECL_ORIGINAL_TYPE (TYPE_NAME (t)))

41143

@@ -645,7 +662,7 @@

41144

if (!(TYPE_NAME (t) && TREE_CODE (TYPE_NAME (t)) == TYPE_DECL))

41145

{

41146

TYPE_NAME (t) = decl;

41147

- TYPE_CONTEXT (t) = DECL_CONTEXT (decl);

41148

+ gnat_set_type_context (t, DECL_CONTEXT (decl));

41149

}

41150

}

41151

}

41152

@@ -1692,93 +1709,74 @@

41153

TYPE_SIZE_UNIT (new_record_type)

41154

= size_int (TYPE_ALIGN (record_type) / BITS_PER_UNIT);

41155

41156

- /* Now scan all the fields, replacing each field with a new

41157

- field corresponding to the new encoding. */

41158

+ /* Now scan all the fields, replacing each field with a new field

41159

+ corresponding to the new encoding. */

41160

for (old_field = TYPE_FIELDS (record_type); old_field;

41161

old_field = DECL_CHAIN (old_field))

41162

{

41163

tree field_type = TREE_TYPE (old_field);

41164

tree field_name = DECL_NAME (old_field);

41165

- tree new_field;

41166

tree curpos = bit_position (old_field);

41167

+ tree pos, new_field;

41168

bool var = false;

41169

unsigned int align = 0;

41170

- tree pos;

41171

41172

+ /* We're going to do some pattern matching below so remove as many

41173

+ conversions as possible. */

41174

+ curpos = remove_conversions (curpos, true);

41175

+

41176

/* See how the position was modified from the last position.

41177

41178

- There are two basic cases we support: a value was added

41179

- to the last position or the last position was rounded to

41180

- a boundary and they something was added. Check for the

41181

- first case first. If not, see if there is any evidence

41182

- of rounding. If so, round the last position and try

41183

- again.

41184

+ There are two basic cases we support: a value was added

41185

+ to the last position or the last position was rounded to

41186

+ a boundary and they something was added. Check for the

41187

+ first case first. If not, see if there is any evidence

41188

+ of rounding. If so, round the last position and retry.

41189

41190

- If this is a union, the position can be taken as zero. */

41191

-

41192

- /* Some computations depend on the shape of the position expression,

41193

- so strip conversions to make sure it's exposed. */

41194

- curpos = remove_conversions (curpos, true);

41195

-

41196

+ If this is a union, the position can be taken as zero. */

41197

if (TREE_CODE (new_record_type) == UNION_TYPE)

41198

- pos = bitsize_zero_node, align = 0;

41199

+ pos = bitsize_zero_node;

41200

else

41201

pos = compute_related_constant (curpos, last_pos);

41202

41203

- if (!pos && TREE_CODE (curpos) == MULT_EXPR

41204

+ if (!pos

41205

+ && TREE_CODE (curpos) == MULT_EXPR

41206

&& host_integerp (TREE_OPERAND (curpos, 1), 1))

41207

{

41208

tree offset = TREE_OPERAND (curpos, 0);

41209

align = tree_low_cst (TREE_OPERAND (curpos, 1), 1);

41210

-

41211

- /* An offset which is a bitwise AND with a mask increases the

41212

- alignment according to the number of trailing zeros. */

41213

- offset = remove_conversions (offset, true);

41214

- if (TREE_CODE (offset) == BIT_AND_EXPR

41215

- && TREE_CODE (TREE_OPERAND (offset, 1)) == INTEGER_CST)

41216

- {

41217

- unsigned HOST_WIDE_INT mask

41218

- = TREE_INT_CST_LOW (TREE_OPERAND (offset, 1));

41219

- unsigned int i;

41220

-

41221

- for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)

41222

- {

41223

- if (mask & 1)

41224

- break;

41225

- mask >>= 1;

41226

- align *= 2;

41227

- }

41228

- }

41229

-

41230

- pos = compute_related_constant (curpos,

41231

- round_up (last_pos, align));

41232

+ align = scale_by_factor_of (offset, align);

41233

+ last_pos = round_up (last_pos, align);

41234

+ pos = compute_related_constant (curpos, last_pos);

41235

}

41236

- else if (!pos && TREE_CODE (curpos) == PLUS_EXPR

41237

- && TREE_CODE (TREE_OPERAND (curpos, 1)) == INTEGER_CST

41238

+ else if (!pos

41239

+ && TREE_CODE (curpos) == PLUS_EXPR

41240

+ && host_integerp (TREE_OPERAND (curpos, 1), 1)

41241

&& TREE_CODE (TREE_OPERAND (curpos, 0)) == MULT_EXPR

41242

- && host_integerp (TREE_OPERAND

41243

- (TREE_OPERAND (curpos, 0), 1),

41244

- 1))

41245

+ && host_integerp

41246

+ (TREE_OPERAND (TREE_OPERAND (curpos, 0), 1), 1))

41247

{

41248

+ tree offset = TREE_OPERAND (TREE_OPERAND (curpos, 0), 0);

41249

+ unsigned HOST_WIDE_INT addend

41250

+ = tree_low_cst (TREE_OPERAND (curpos, 1), 1);

41251

align

41252

- = tree_low_cst

41253

- (TREE_OPERAND (TREE_OPERAND (curpos, 0), 1), 1);

41254

- pos = compute_related_constant (curpos,

41255

- round_up (last_pos, align));

41256

+ = tree_low_cst (TREE_OPERAND (TREE_OPERAND (curpos, 0), 1), 1);

41257

+ align = scale_by_factor_of (offset, align);

41258

+ align = MIN (align, addend & -addend);

41259

+ last_pos = round_up (last_pos, align);

41260

+ pos = compute_related_constant (curpos, last_pos);

41261

}

41262

- else if (potential_alignment_gap (prev_old_field, old_field,

41263

- pos))

41264

+ else if (potential_alignment_gap (prev_old_field, old_field, pos))

41265

{

41266

align = TYPE_ALIGN (field_type);

41267

- pos = compute_related_constant (curpos,

41268

- round_up (last_pos, align));

41269

+ last_pos = round_up (last_pos, align);

41270

+ pos = compute_related_constant (curpos, last_pos);

41271

}

41272

41273

/* If we can't compute a position, set it to zero.

41274

41275

- ??? We really should abort here, but it's too much work

41276

- to get this correct for all cases. */

41277

-

41278

+ ??? We really should abort here, but it's too much work

41279

+ to get this correct for all cases. */

41280

if (!pos)

41281

pos = bitsize_zero_node;

41282

41283

@@ -2553,6 +2551,32 @@

41284

return false;

41285

}

41286

41287

+/* Return VALUE scaled by the biggest power-of-2 factor of EXPR. */

41288

+

41289

+static unsigned int

41290

+scale_by_factor_of (tree expr, unsigned int value)

41291

+{

41292

+ expr = remove_conversions (expr, true);

41293

+

41294

+ /* An expression which is a bitwise AND with a mask has a power-of-2 factor

41295

+ corresponding to the number of trailing zeros of the mask. */

41296

+ if (TREE_CODE (expr) == BIT_AND_EXPR

41297

+ && TREE_CODE (TREE_OPERAND (expr, 1)) == INTEGER_CST)

41298

+ {

41299

+ unsigned HOST_WIDE_INT mask = TREE_INT_CST_LOW (TREE_OPERAND (expr, 1));

41300

+ unsigned int i = 0;

41301

+

41302

+ while ((mask & 1) == 0 && i < HOST_BITS_PER_WIDE_INT)

41303

+ {

41304

+ mask >>= 1;

41305

+ value *= 2;

41306

+ i++;

41307

+ }

41308

+ }

41309

+

41310

+ return value;

41311

+}

41312

+

41313

/* Given two consecutive field decls PREV_FIELD and CURR_FIELD, return true

41314

unless we can prove these 2 fields are laid out in such a way that no gap

41315

exist between the end of PREV_FIELD and the beginning of CURR_FIELD. OFFSET

41316

Index: gcc/ada/gcc-interface/Makefile.in

41317

===================================================================

41318

--- a/src/gcc/ada/gcc-interface/Makefile.in (.../tags/gcc_4_8_2_release)

41319

+++ b/src/gcc/ada/gcc-interface/Makefile.in (.../branches/gcc-4_8-branch)

41320

@@ -2397,7 +2397,7 @@

41321

"GNATLINK=$(GNATLINK)" \

41322

"GNATBIND=$(GNATBIND)"

41323

41324

-GCC_LINK=$(CC) $(GCC_LINK_FLAGS) $(ADA_INCLUDES)

41325

+GCC_LINK=$(CC) $(GCC_LINK_FLAGS) $(ADA_INCLUDES) $(LDFLAGS)

41326

41327

# Build directory for the tools. Let's copy the target-dependent

41328

# sources using the same mechanism as for gnatlib. The other sources are

41329

@@ -2519,12 +2519,10 @@

41330

41331

# Likewise for the tools

41332

../../gnatmake$(exeext): $(P) b_gnatm.o link.o targext.o $(GNATMAKE_OBJS)

41333

- $(GCC_LINK) $(ALL_CFLAGS) $(LDFLAGS) -o $@ b_gnatm.o $(GNATMAKE_OBJS) \

41334

- $(TOOLS_LIBS)

41335

+ +$(GCC_LINK) $(ALL_CFLAGS) -o $@ b_gnatm.o $(GNATMAKE_OBJS) $(TOOLS_LIBS)

41336

41337

../../gnatlink$(exeext): $(P) b_gnatl.o link.o targext.o $(GNATLINK_OBJS)

41338

- $(GCC_LINK) $(ALL_CFLAGS) $(LDFLAGS) -o $@ b_gnatl.o $(GNATLINK_OBJS) \

41339

- $(TOOLS_LIBS)

41340

+ +$(GCC_LINK) $(ALL_CFLAGS) -o $@ b_gnatl.o $(GNATLINK_OBJS) $(TOOLS_LIBS)

41341

41342

../stamp-gnatlib-$(RTSDIR):

41343

@if [ ! -f stamp-gnatlib-$(RTSDIR) ] ; \

41344

Index: gcc/ada/gcc-interface/cuintp.c

41345

===================================================================

41346

--- a/src/gcc/ada/gcc-interface/cuintp.c (.../tags/gcc_4_8_2_release)

41347

+++ b/src/gcc/ada/gcc-interface/cuintp.c (.../branches/gcc-4_8-branch)

41348

@@ -6,7 +6,7 @@

41349

* *

41350

* C Implementation File *

41351

* *

41352

41353

41354

* *

41355

* GNAT is free software; you can redistribute it and/or modify it under *

41356

* terms of the GNU General Public License as published by the Free Soft- *

41357

@@ -59,8 +59,8 @@

41358

static tree

41359

build_cst_from_int (tree type, HOST_WIDE_INT low)

41360

{

41361

- if (TREE_CODE (type) == REAL_TYPE)

41362

- return convert (type, build_int_cst (NULL_TREE, low));

41363

+ if (SCALAR_FLOAT_TYPE_P (type))

41364

+ return convert (type, build_int_cst (gnat_type_for_size (32, 0), low));

41365

else

41366

return build_int_cst_type (type, low);

41367

}

41368

@@ -99,20 +99,13 @@

41369

gcc_assert (Length > 0);

41370

41371

/* The computations we perform below always require a type at least as

41372

- large as an integer not to overflow. REAL types are always fine, but

41373

+ large as an integer not to overflow. FP types are always fine, but

41374

INTEGER or ENUMERAL types we are handed may be too short. We use a

41375

base integer type node for the computations in this case and will

41376

- convert the final result back to the incoming type later on.

41377

- The base integer precision must be superior than 16. */

41378

+ convert the final result back to the incoming type later on. */

41379

+ if (!SCALAR_FLOAT_TYPE_P (comp_type) && TYPE_PRECISION (comp_type) < 32)

41380

+ comp_type = gnat_type_for_size (32, 0);

41381

41382

- if (TREE_CODE (comp_type) != REAL_TYPE

41383

- && TYPE_PRECISION (comp_type)

41384

- < TYPE_PRECISION (long_integer_type_node))

41385

- {

41386

- comp_type = long_integer_type_node;

41387

- gcc_assert (TYPE_PRECISION (comp_type) > 16);

41388

- }

41389

-

41390

gnu_base = build_cst_from_int (comp_type, Base);

41391

41392

gnu_ret = build_cst_from_int (comp_type, First);

41393

Index: gcc/ada/gcc-interface/Make-lang.in

41394

===================================================================

41395

--- a/src/gcc/ada/gcc-interface/Make-lang.in (.../tags/gcc_4_8_2_release)

41396

+++ b/src/gcc/ada/gcc-interface/Make-lang.in (.../branches/gcc-4_8-branch)

41397

@@ -625,7 +625,7 @@

41398

ada/doctools/xgnatugn$(build_exeext): ada/xgnatugn.adb

41399

-$(MKDIR) ada/doctools

41400

$(CP) $^ ada/doctools

41401

- cd ada/doctools && $(GNATMAKE) -q xgnatugn

41402

+ cd ada/doctools && gnatmake -q xgnatugn

41403

41404

# Note that doc/gnat_ugn.texi and doc/projects.texi do not depend on

41405

# xgnatugn being built so we can distribute a pregenerated doc/gnat_ugn.info

41406

Index: gcc/ada/gcc-interface/gigi.h

41407

===================================================================

41408

--- a/src/gcc/ada/gcc-interface/gigi.h (.../tags/gcc_4_8_2_release)

41409

+++ b/src/gcc/ada/gcc-interface/gigi.h (.../branches/gcc-4_8-branch)

41410

@@ -1014,7 +1014,7 @@

41411

/* This function is called by the front-end to enumerate all the supported

41412

modes for the machine, as well as some predefined C types. */

41413

extern void enumerate_modes (void (*f) (const char *, int, int, int, int, int,

41414

- int));

41415

+ int, int));

41416

41417

#ifdef __cplusplus

41418

}

41419

Index: gcc/ada/gcc-interface/misc.c

41420

===================================================================

41421

--- a/src/gcc/ada/gcc-interface/misc.c (.../tags/gcc_4_8_2_release)

41422

+++ b/src/gcc/ada/gcc-interface/misc.c (.../branches/gcc-4_8-branch)

41423

@@ -648,7 +648,7 @@

41424

/* This function is called by the front-end to enumerate all the supported

41425

modes for the machine, as well as some predefined C types. F is a function

41426

which is called back with the parameters as listed below, first a string,

41427

- then six ints. The name is any arbitrary null-terminated string and has

41428

+ then seven ints. The name is any arbitrary null-terminated string and has

41429

no particular significance, except for the case of predefined C types, where

41430

it should be the name of the C type. For integer types, only signed types

41431

should be listed, unsigned versions are assumed. The order of types should

41432

@@ -664,11 +664,12 @@

41433

COMPLEX_P nonzero is this represents a complex mode

41434

COUNT count of number of items, nonzero for vector mode

41435

FLOAT_REP Float_Rep_Kind for FP, otherwise undefined

41436

- SIZE number of bits used to store data

41437

+ PRECISION number of bits used to store data

41438

+ SIZE number of bits occupied by the mode

41439

ALIGN number of bits to which mode is aligned. */

41440

41441

void

41442

-enumerate_modes (void (*f) (const char *, int, int, int, int, int, int))

41443

+enumerate_modes (void (*f) (const char *, int, int, int, int, int, int, int))

41444

{

41445

const tree c_types[]

41446

= { float_type_node, double_type_node, long_double_type_node };

41447

@@ -742,28 +743,26 @@

41448

41449

/* First register any C types for this mode that the front end

41450

may need to know about, unless the mode should be skipped. */

41451

-

41452

- if (!skip_p)

41453

+ if (!skip_p && !vector_p)

41454

for (nameloop = 0; nameloop < ARRAY_SIZE (c_types); nameloop++)

41455

{

41456

- tree typ = c_types[nameloop];

41457

- const char *nam = c_names[nameloop];

41458

+ tree type = c_types[nameloop];

41459

+ const char *name = c_names[nameloop];

41460

41461

- if (TYPE_MODE (typ) == i)

41462

+ if (TYPE_MODE (type) == i)

41463

{

41464

- f (nam, digs, complex_p,

41465

- vector_p ? GET_MODE_NUNITS (i) : 0, float_rep,

41466

- TYPE_PRECISION (typ), TYPE_ALIGN (typ));

41467

+ f (name, digs, complex_p, 0, float_rep, TYPE_PRECISION (type),

41468

+ TREE_INT_CST_LOW (TYPE_SIZE (type)), TYPE_ALIGN (type));

41469

skip_p = true;

41470

}

41471

}

41472

41473

/* If no predefined C types were found, register the mode itself. */

41474

-

41475

if (!skip_p)

41476

f (GET_MODE_NAME (i), digs, complex_p,

41477

vector_p ? GET_MODE_NUNITS (i) : 0, float_rep,

41478

- GET_MODE_PRECISION (i), GET_MODE_ALIGNMENT (i));

41479

+ GET_MODE_PRECISION (i), GET_MODE_BITSIZE (i),

41480

+ GET_MODE_ALIGNMENT (i));

41481

}

41482

}

41483

41484

Index: gcc/ada/system-linux-sparc.ads

41485

===================================================================

41486

--- a/src/gcc/ada/system-linux-sparc.ads (.../tags/gcc_4_8_2_release)

41487

+++ b/src/gcc/ada/system-linux-sparc.ads (.../branches/gcc-4_8-branch)

41488

@@ -7,7 +7,7 @@

41489

-- S p e c --

41490

-- (GNU/Linux-SPARC Version) --

41491

-- --

41492

41493

41494

-- --

41495

-- This specification is derived from the Ada Reference Manual for use with --

41496

-- GNAT. The copyright notice above, and the license provisions that follow --

41497

@@ -35,9 +35,10 @@

41498

------------------------------------------------------------------------------

41499

41500

package System is

41501

-pragma Pure (System);

41502

--- Note that we take advantage of the implementation permission to

41503

--- make this unit Pure instead of Preelaborable, see RM 13.7(36)

41504

+ pragma Pure;

41505

+ -- Note that we take advantage of the implementation permission to make

41506

+ -- this unit Pure instead of Preelaborable; see RM 13.7.1(15). In Ada

41507

+ -- 2005, this is Pure in any case (AI-362).

41508

41509

type Name is (SYSTEM_NAME_GNAT);

41510

System_Name : constant Name := SYSTEM_NAME_GNAT;

41511

@@ -61,6 +62,7 @@

41512

-- Storage-related Declarations

41513

41514

type Address is private;

41515

+ pragma Preelaborable_Initialization (Address);

41516

Null_Address : constant Address;

41517

41518

Storage_Unit : constant := 8;

41519

Index: gcc/ada/system-rtems.ads

41520

===================================================================

41521

--- a/src/gcc/ada/system-rtems.ads (.../tags/gcc_4_8_2_release)

41522

+++ b/src/gcc/ada/system-rtems.ads (.../branches/gcc-4_8-branch)

41523

@@ -7,7 +7,7 @@

41524

-- S p e c --

41525

-- (Compiler Version) --

41526

-- --

41527

41528

41529

-- --

41530

-- This specification is derived from the Ada Reference Manual for use with --

41531

-- GNAT. The copyright notice above, and the license provisions that follow --

41532

@@ -34,9 +34,8 @@

41533

-- --

41534

------------------------------------------------------------------------------

41535

41536

--- This version of System is a RTEMS version that is used in building

41537

--- the compiler. This is based as closely as possible on the generic

41538

--- version with the following exceptions:

41539

+-- This version is for RTEMS. It is based as closely as possible on the

41540

+-- generic version with the following exceptions:

41541

-- + priority definitions

41542

41543

package System is

41544

@@ -67,6 +66,7 @@

41545

-- Storage-related Declarations

41546

41547

type Address is private;

41548

+ pragma Preelaborable_Initialization (Address);

41549

Null_Address : constant Address;

41550

41551

Storage_Unit : constant := Standard'Storage_Unit;

41552

Index: gcc/gimple-ssa-strength-reduction.c

41553

===================================================================

41554

--- a/src/gcc/gimple-ssa-strength-reduction.c (.../tags/gcc_4_8_2_release)

41555

+++ b/src/gcc/gimple-ssa-strength-reduction.c (.../branches/gcc-4_8-branch)

41556

@@ -735,15 +735,18 @@

41557

X = Y * c

41558

============================

41559

X = (B + i') * (S * c) */

41560

- base = base_cand->base_expr;

41561

- index = base_cand->index;

41562

temp = tree_to_double_int (base_cand->stride)

41563

* tree_to_double_int (stride_in);

41564

- stride = double_int_to_tree (TREE_TYPE (stride_in), temp);

41565

- ctype = base_cand->cand_type;

41566

- if (has_single_use (base_in))

41567

- savings = (base_cand->dead_savings

41568

- + stmt_cost (base_cand->cand_stmt, speed));

41569

+ if (double_int_fits_to_tree_p (TREE_TYPE (stride_in), temp))

41570

+ {

41571

+ base = base_cand->base_expr;

41572

+ index = base_cand->index;

41573

+ stride = double_int_to_tree (TREE_TYPE (stride_in), temp);

41574

+ ctype = base_cand->cand_type;

41575

+ if (has_single_use (base_in))

41576

+ savings = (base_cand->dead_savings

41577

+ + stmt_cost (base_cand->cand_stmt, speed));

41578

+ }

41579

}

41580

else if (base_cand->kind == CAND_ADD

41581

&& operand_equal_p (base_cand->stride, integer_one_node, 0))

41582

Index: gcc/tree-eh.c

41583

===================================================================

41584

--- a/src/gcc/tree-eh.c (.../tags/gcc_4_8_2_release)

41585

+++ b/src/gcc/tree-eh.c (.../branches/gcc-4_8-branch)

41586

@@ -1357,9 +1357,6 @@

41587

x = gimple_seq_last_stmt (finally);

41588

finally_loc = x ? gimple_location (x) : tf_loc;

41589

41590

- /* Lower the finally block itself. */

41591

- lower_eh_constructs_1 (state, &finally);

41592

-

41593

/* Prepare for switch statement generation. */

41594

nlabels = tf->dest_array.length ();

41595

return_index = nlabels;

41596

@@ -1445,6 +1442,7 @@

41597

x = gimple_build_label (finally_label);

41598

gimple_seq_add_stmt (&tf->top_p_seq, x);

41599

41600

+ lower_eh_constructs_1 (state, &finally);

41601

gimple_seq_add_seq (&tf->top_p_seq, finally);

41602

41603

/* Redirect each incoming goto edge. */

41604

@@ -2502,12 +2500,6 @@

41605

restart:

41606

switch (code)

41607

{

41608

- case TARGET_MEM_REF:

41609

- if (TREE_CODE (TMR_BASE (expr)) == ADDR_EXPR

41610

- && !TMR_INDEX (expr) && !TMR_INDEX2 (expr))

41611

- return false;

41612

- return !TREE_THIS_NOTRAP (expr);

41613

-

41614

case COMPONENT_REF:

41615

case REALPART_EXPR:

41616

case IMAGPART_EXPR:

41617

@@ -2534,10 +2526,36 @@

41618

return false;

41619

return !in_array_bounds_p (expr);

41620

41621

+ case TARGET_MEM_REF:

41622

case MEM_REF:

41623

+ if (TREE_CODE (TREE_OPERAND (expr, 0)) == ADDR_EXPR

41624

+ && tree_could_trap_p (TREE_OPERAND (TREE_OPERAND (expr, 0), 0)))

41625

+ return true;

41626

+ if (TREE_THIS_NOTRAP (expr))

41627

+ return false;

41628

+ /* We cannot prove that the access is in-bounds when we have

41629

+ variable-index TARGET_MEM_REFs. */

41630

+ if (code == TARGET_MEM_REF

41631

+ && (TMR_INDEX (expr) || TMR_INDEX2 (expr)))

41632

+ return true;

41633

if (TREE_CODE (TREE_OPERAND (expr, 0)) == ADDR_EXPR)

41634

- return false;

41635

- /* Fallthru. */

41636

+ {

41637

+ tree base = TREE_OPERAND (TREE_OPERAND (expr, 0), 0);

41638

+ double_int off = mem_ref_offset (expr);

41639

+ if (off.is_negative ())

41640

+ return true;

41641

+ if (TREE_CODE (base) == STRING_CST)

41642

+ return double_int::from_uhwi (TREE_STRING_LENGTH (base)).ule (off);

41643

+ else if (DECL_SIZE_UNIT (base) == NULL_TREE

41644

+ || TREE_CODE (DECL_SIZE_UNIT (base)) != INTEGER_CST

41645

+ || tree_to_double_int (DECL_SIZE_UNIT (base)).ule (off))

41646

+ return true;

41647

+ /* Now we are sure the first byte of the access is inside

41648

+ the object. */

41649

+ return false;

41650

+ }

41651

+ return true;

41652

+

41653

case INDIRECT_REF:

41654

return !TREE_THIS_NOTRAP (expr);

41655

41656

@@ -4166,8 +4184,11 @@

41657

/* If the block is totally empty, look for more unsplitting cases. */

41658

if (gsi_end_p (gsi))

41659

{

41660

- /* For the degenerate case of an infinite loop bail out. */

41661

- if (infinite_empty_loop_p (e_out))

41662

+ /* For the degenerate case of an infinite loop bail out.

41663

+ If bb has no successors and is totally empty, which can happen e.g.

41664

+ because of incorrect noreturn attribute, bail out too. */

41665

+ if (e_out == NULL

41666

+ || infinite_empty_loop_p (e_out))

41667

return ret;

41668

41669

return ret | cleanup_empty_eh_unsplit (bb, e_out, lp);

41670

@@ -4304,11 +4325,12 @@

41671

remove_unreachable_handlers ();

41672

41673

/* Watch out for the region tree vanishing due to all unreachable. */

41674

- if (cfun->eh->region_tree && optimize)

41675

+ if (cfun->eh->region_tree)

41676

{

41677

bool changed = false;

41678

41679

- changed |= unsplit_all_eh ();

41680

+ if (optimize)

41681

+ changed |= unsplit_all_eh ();

41682

changed |= cleanup_all_empty_eh ();

41683

41684

if (changed)

41685

Index: gcc/fortran/interface.c

41686

===================================================================

41687

--- a/src/gcc/fortran/interface.c (.../tags/gcc_4_8_2_release)

41688

+++ b/src/gcc/fortran/interface.c (.../branches/gcc-4_8-branch)

41689

@@ -1245,7 +1245,8 @@

41690

return FAILURE;

41691

}

41692

41693

- if (r1->ts.u.cl->length)

41694

+ if (s1->ts.u.cl && s1->ts.u.cl->length

41695

+ && s2->ts.u.cl && s2->ts.u.cl->length)

41696

{

41697

int compval = gfc_dep_compare_expr (r1->ts.u.cl->length,

41698

r2->ts.u.cl->length);

41699

@@ -1367,8 +1368,8 @@

41700

if (s1->attr.function && s2->attr.function)

41701

{

41702

/* If both are functions, check result characteristics. */

41703

- if (check_result_characteristics (s1, s2, errmsg, err_len)

41704

- == FAILURE)

41705

+ if (check_result_characteristics (s1, s2, errmsg, err_len) == FAILURE

41706

+ || check_result_characteristics (s2, s1, errmsg, err_len) == FAILURE)

41707

return 0;

41708

}

41709

41710

Index: gcc/fortran/intrinsic.c

41711

===================================================================

41712

--- a/src/gcc/fortran/intrinsic.c (.../tags/gcc_4_8_2_release)

41713

+++ b/src/gcc/fortran/intrinsic.c (.../branches/gcc-4_8-branch)

41714

@@ -4229,7 +4229,7 @@

41715

c->resolved_sym->attr.elemental = isym->elemental;

41716

}

41717

41718

- if (gfc_pure (NULL) && !isym->pure)

41719

+ if (!isym->pure && gfc_pure (NULL))

41720

{

41721

gfc_error ("Subroutine call to intrinsic '%s' at %L is not PURE", name,

41722

&c->loc);

41723

@@ -4236,6 +4236,9 @@

41724

return MATCH_ERROR;

41725

}

41726

41727

+ if (!isym->pure)

41728

+ gfc_unset_implicit_pure (NULL);

41729

+

41730

c->resolved_sym->attr.noreturn = isym->noreturn;

41731

41732

return MATCH_YES;

41733

Index: gcc/fortran/trans-expr.c

41734

===================================================================

41735

--- a/src/gcc/fortran/trans-expr.c (.../tags/gcc_4_8_2_release)

41736

+++ b/src/gcc/fortran/trans-expr.c (.../branches/gcc-4_8-branch)

41737

@@ -355,7 +355,11 @@

41738

gfc_conv_expr_descriptor (parmse, e);

41739

41740

if (e->rank != class_ts.u.derived->components->as->rank)

41741

- class_array_data_assign (&block, ctree, parmse->expr, true);

41742

+ {

41743

+ gcc_assert (class_ts.u.derived->components->as->type

41744

+ == AS_ASSUMED_RANK);

41745

+ class_array_data_assign (&block, ctree, parmse->expr, false);

41746

+ }

41747

else

41748

{

41749

if (gfc_expr_attr (e).codimension)

41750

@@ -670,7 +674,6 @@

41751

gfc_add_modify (&parmse->post, vptr,

41752

fold_convert (TREE_TYPE (vptr), ctree));

41753

41754

- gcc_assert (!optional || (optional && !copyback));

41755

if (optional)

41756

{

41757

tree tmp2;

41758

@@ -6343,7 +6346,13 @@

41759

/* Returns a reference to the scalar evaluated outside the loop

41760

for this case. */

41761

gfc_conv_expr (se, expr);

41762

- se->expr = gfc_build_addr_expr (NULL_TREE, se->expr);

41763

+

41764

+ if (expr->ts.type == BT_CHARACTER

41765

+ && expr->expr_type != EXPR_FUNCTION)

41766

+ gfc_conv_string_parameter (se);

41767

+ else

41768

+ se->expr = gfc_build_addr_expr (NULL_TREE, se->expr);

41769

+

41770

return;

41771

}

41772

41773

Index: gcc/fortran/trans-array.c

41774

===================================================================

41775

--- a/src/gcc/fortran/trans-array.c (.../tags/gcc_4_8_2_release)

41776

+++ b/src/gcc/fortran/trans-array.c (.../branches/gcc-4_8-branch)

41777

@@ -1,5 +1,5 @@

41778

/* Array translation routines

41779

41780

41781

Contributed by Paul Brook <paul@nowt.org>

41782

and Steven Bosscher <s.bosscher@student.tudelft.nl>

41783

41784

@@ -2487,6 +2487,11 @@

41785

a reference to the value. */

41786

gfc_conv_expr (&se, expr);

41787

}

41788

+

41789

+ /* Ensure that a pointer to the string is stored. */

41790

+ if (expr->ts.type == BT_CHARACTER)

41791

+ gfc_conv_string_parameter (&se);

41792

+

41793

gfc_add_block_to_block (&outer_loop->pre, &se.pre);

41794

gfc_add_block_to_block (&outer_loop->post, &se.post);

41795

if (gfc_is_class_scalar_expr (expr))

41796

@@ -7940,6 +7945,7 @@

41797

tree size1;

41798

tree size2;

41799

tree array1;

41800

+ tree cond_null;

41801

tree cond;

41802

tree tmp;

41803

tree tmp2;

41804

@@ -8015,9 +8021,9 @@

41805

jump_label2 = gfc_build_label_decl (NULL_TREE);

41806

41807

/* Allocate if data is NULL. */

41808

- cond = fold_build2_loc (input_location, EQ_EXPR, boolean_type_node,

41809

+ cond_null = fold_build2_loc (input_location, EQ_EXPR, boolean_type_node,

41810

array1, build_int_cst (TREE_TYPE (array1), 0));

41811

- tmp = build3_v (COND_EXPR, cond,

41812

+ tmp = build3_v (COND_EXPR, cond_null,

41813

build1_v (GOTO_EXPR, jump_label1),

41814

build_empty_stmt (input_location));

41815

gfc_add_expr_to_block (&fblock, tmp);

41816

@@ -8069,13 +8075,25 @@

41817

tmp = build1_v (LABEL_EXPR, jump_label1);

41818

gfc_add_expr_to_block (&fblock, tmp);

41819

41820

- size1 = gfc_conv_descriptor_size (desc, expr1->rank);

41821

+ /* If the lhs has not been allocated, its bounds will not have been

41822

+ initialized and so its size is set to zero. */

41823

+ size1 = gfc_create_var (gfc_array_index_type, NULL);

41824

+ gfc_init_block (&alloc_block);

41825

+ gfc_add_modify (&alloc_block, size1, gfc_index_zero_node);

41826

+ gfc_init_block (&realloc_block);

41827

+ gfc_add_modify (&realloc_block, size1,

41828

+ gfc_conv_descriptor_size (desc, expr1->rank));

41829

+ tmp = build3_v (COND_EXPR, cond_null,

41830

+ gfc_finish_block (&alloc_block),

41831

+ gfc_finish_block (&realloc_block));

41832

+ gfc_add_expr_to_block (&fblock, tmp);

41833

41834

- /* Get the rhs size. Fix both sizes. */

41835

+ /* Get the rhs size and fix it. */

41836

if (expr2)

41837

desc2 = rss->info->data.array.descriptor;

41838

else

41839

desc2 = NULL_TREE;

41840

+

41841

size2 = gfc_index_one_node;

41842

for (n = 0; n < expr2->rank; n++)

41843

{

41844

@@ -8089,8 +8107,6 @@

41845

gfc_array_index_type,

41846

tmp, size2);

41847

}

41848

-

41849

- size1 = gfc_evaluate_now (size1, &fblock);

41850

size2 = gfc_evaluate_now (size2, &fblock);

41851

41852

cond = fold_build2_loc (input_location, NE_EXPR, boolean_type_node,

41853

Index: gcc/fortran/symbol.c

41854

===================================================================

41855

--- a/src/gcc/fortran/symbol.c (.../tags/gcc_4_8_2_release)

41856

+++ b/src/gcc/fortran/symbol.c (.../branches/gcc-4_8-branch)

41857

@@ -1110,8 +1110,8 @@

41858

return FAILURE;

41859

}

41860

41861

- if (s == SAVE_EXPLICIT && gfc_implicit_pure (NULL))

41862

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

41863

+ if (s == SAVE_EXPLICIT)

41864

+ gfc_unset_implicit_pure (NULL);

41865

41866

if (s == SAVE_EXPLICIT && attr->save == SAVE_EXPLICIT)

41867

{

41868

Index: gcc/fortran/class.c

41869

===================================================================

41870

--- a/src/gcc/fortran/class.c (.../tags/gcc_4_8_2_release)

41871

+++ b/src/gcc/fortran/class.c (.../branches/gcc-4_8-branch)

41872

@@ -2486,7 +2486,7 @@

41873

return NULL;

41874

41875

/* Sometimes the typespec is passed from a single call. */

41876

- if (ts->type == BT_DERIVED)

41877

+ if (ts->type == BT_DERIVED || ts->type == BT_CLASS)

41878

return gfc_find_derived_vtab (ts->u.derived);

41879

41880

/* Find the top-level namespace. */

41881

Index: gcc/fortran/decl.c

41882

===================================================================

41883

--- a/src/gcc/fortran/decl.c (.../tags/gcc_4_8_2_release)

41884

+++ b/src/gcc/fortran/decl.c (.../branches/gcc-4_8-branch)

41885

@@ -510,10 +510,8 @@

41886

free (newdata);

41887

return MATCH_ERROR;

41888

}

41889

+ gfc_unset_implicit_pure (gfc_current_ns->proc_name);

41890

41891

- if (gfc_implicit_pure (NULL))

41892

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

41893

-

41894

/* Mark the variable as having appeared in a data statement. */

41895

if (gfc_add_data (&sym->attr, sym->name, &sym->declared_at) == FAILURE)

41896

{

41897

@@ -571,10 +569,8 @@

41898

gfc_error ("DATA statement at %C is not allowed in a PURE procedure");

41899

return MATCH_ERROR;

41900

}

41901

+ gfc_unset_implicit_pure (gfc_current_ns->proc_name);

41902

41903

- if (gfc_implicit_pure (NULL))

41904

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

41905

-

41906

return MATCH_YES;

41907

41908

cleanup:

41909

@@ -1737,6 +1733,7 @@

41910

"a PURE procedure");

41911

return MATCH_ERROR;

41912

}

41913

+ gfc_unset_implicit_pure (gfc_current_ns->proc_name);

41914

41915

/* Match NULL() initialization. */

41916

m = gfc_match_null (init);

41917

@@ -2045,6 +2042,10 @@

41918

m = MATCH_ERROR;

41919

}

41920

41921

+ if (current_attr.flavor != FL_PARAMETER

41922

+ && gfc_state_stack->state != COMP_DERIVED)

41923

+ gfc_unset_implicit_pure (gfc_current_ns->proc_name);

41924

+

41925

if (m != MATCH_YES)

41926

goto cleanup;

41927

}

41928

@@ -5069,7 +5070,14 @@

41929

if (gfc_add_proc (&c->attr, name, NULL) == FAILURE)

41930

return MATCH_ERROR;

41931

41932

- c->tb = tb;

41933

+ if (num == 1)

41934

+ c->tb = tb;

41935

+ else

41936

+ {

41937

+ c->tb = XCNEW (gfc_typebound_proc);

41938

+ c->tb->where = gfc_current_locus;

41939

+ *c->tb = *tb;

41940

+ }

41941

41942

/* Set interface. */

41943

if (proc_if != NULL)

41944

@@ -7384,6 +7392,7 @@

41945

41946

41947

/* Check a derived type that is being extended. */

41948

+

41949

static gfc_symbol*

41950

check_extended_derived_type (char *name)

41951

{

41952

@@ -7395,14 +7404,15 @@

41953

return NULL;

41954

}

41955

41956

+ extended = gfc_find_dt_in_generic (extended);

41957

+

41958

+ /* F08:C428. */

41959

if (!extended)

41960

{

41961

- gfc_error ("No such symbol in TYPE definition at %C");

41962

+ gfc_error ("Symbol '%s' at %C has not been previously defined", name);

41963

return NULL;

41964

}

41965

41966

- extended = gfc_find_dt_in_generic (extended);

41967

-

41968

if (extended->attr.flavor != FL_DERIVED)

41969

{

41970

gfc_error ("'%s' in EXTENDS expression at %C is not a "

41971

Index: gcc/fortran/dump-parse-tree.c

41972

===================================================================

41973

--- a/src/gcc/fortran/dump-parse-tree.c (.../tags/gcc_4_8_2_release)

41974

+++ b/src/gcc/fortran/dump-parse-tree.c (.../branches/gcc-4_8-branch)

41975

@@ -110,7 +110,8 @@

41976

break;

41977

41978

case BT_CHARACTER:

41979

- show_expr (ts->u.cl->length);

41980

+ if (ts->u.cl)

41981

+ show_expr (ts->u.cl->length);

41982

fprintf(dumpfile, " %d", ts->kind);

41983

break;

41984

41985

Index: gcc/fortran/cpp.c

41986

===================================================================

41987

--- a/src/gcc/fortran/cpp.c (.../tags/gcc_4_8_2_release)

41988

+++ b/src/gcc/fortran/cpp.c (.../branches/gcc-4_8-branch)

41989

@@ -569,6 +569,7 @@

41990

if (gfc_option.flag_preprocessed)

41991

return;

41992

41993

+ cpp_change_file (cpp_in, LC_RENAME, _("<built-in>"));

41994

if (!gfc_cpp_option.no_predefined)

41995

{

41996

/* Make sure all of the builtins about to be declared have

41997

Index: gcc/fortran/gfortran.h

41998

===================================================================

41999

--- a/src/gcc/fortran/gfortran.h (.../tags/gcc_4_8_2_release)

42000

+++ b/src/gcc/fortran/gfortran.h (.../branches/gcc-4_8-branch)

42001

@@ -2830,6 +2830,7 @@

42002

int gfc_impure_variable (gfc_symbol *);

42003

int gfc_pure (gfc_symbol *);

42004

int gfc_implicit_pure (gfc_symbol *);

42005

+void gfc_unset_implicit_pure (gfc_symbol *);

42006

int gfc_elemental (gfc_symbol *);

42007

gfc_try gfc_resolve_iterator (gfc_iterator *, bool, bool);

42008

gfc_try find_forall_index (gfc_expr *, gfc_symbol *, int);

42009

Index: gcc/fortran/ChangeLog

42010

===================================================================

42011

--- a/src/gcc/fortran/ChangeLog (.../tags/gcc_4_8_2_release)

42012

+++ b/src/gcc/fortran/ChangeLog (.../branches/gcc-4_8-branch)

42013

@@ -1,3 +1,259 @@

42014

+2014-04-11 Janne Blomqvist <jb@gcc.gnu.org>

42015

+

42016

+ * intrinsic.texi (RANDOM_SEED): Improve example.

42017

+

42018

+2014-04-10 Jakub Jelinek <jakub@redhat.com>

42019

+

42020

+ Backport from mainline

42021

+ 2014-03-22 Jakub Jelinek <jakub@redhat.com>

42022

+

42023

+ PR debug/60603

42024

+ * cpp.c (gfc_cpp_init): Restore cb_change_file call to

42025

+ <built-in>.

42026

+

42027

+2014-03-29 Mikael Morin <mikael@gcc.gnu.org>

42028

+

42029

+ PR fortran/60677

42030

+ * trans-intrinsic.c (gfc_conv_intrinsic_ichar): Enlarge argument

42031

+ list buffer.

42032

+

42033

+2014-03-28 Mikael Morin <mikael@gcc.gnu.org>

42034

+ Tobias Burnus <burnus@net-b.de>

42035

+

42036

+ PR fortran/60576

42037

+ * trans-expr.c (gfc_conv_derived_to_class): Avoid

42038

+ generation of out-of-bounds range expr.

42039

+

42040

+2014-03-28 Thomas Koenig <tkoenig@gcc.gnu.org>

42041

+

42042

+ PR fortran/60522

42043

+ * frontend-passes.c (cfe_code): Do not walk subtrees

42044

+ for WHERE.

42045

+

42046

+2014-03-20 Tobias Burnus <burnus@net-b.de>

42047

+

42048

+ PR fortran/60543

42049

+ PR fortran/60283

42050

+ * gfortran.h (gfc_unset_implicit_pure): New prototype.

42051

+ * resolve.c (gfc_unset_implicit_pure): New.

42052

+ (resolve_structure_cons, resolve_function,

42053

+ pure_subroutine, resolve_ordinary_assign): Use it.

42054

+ * decl.c (match_old_style_init, gfc_match_data,

42055

+ match_pointer_init, variable_decl): Ditto.

42056

+ * expr.c (gfc_check_pointer_assign): Ditto.

42057

+ * intrinsic.c (gfc_intrinsic_sub_interface): Ditto.

42058

+ * io.c (match_vtag, gfc_match_open, gfc_match_close,

42059

+ match_filepos, gfc_match_inquire, gfc_match_print,

42060

+ gfc_match_wait, check_io_constraints): Ditto.

42061

+ * match.c (gfc_match_critical, gfc_match_stopcode,

42062

+ lock_unlock_statement, sync_statement, gfc_match_allocate,

42063

+ gfc_match_deallocate): Ditto.

42064

+ * parse.c (decode_omp_directive): Ditto.

42065

+ * symbol.c (gfc_add_save): Ditto.

42066

+

42067

+2014-03-08 Janus Weil <janus@gcc.gnu.org>

42068

+

42069

+ PR fortran/60450

42070

+ * simplify.c (gfc_simplify_shape): Only clear shape if it was really

42071

+ created successfully.

42072

+

42073

+2014-03-06 Jakub Jelinek <jakub@redhat.com>

42074

+

42075

+ Backport from mainline

42076

+ 2014-02-11 Jakub Jelinek <jakub@redhat.com>

42077

+

42078

+ PR fortran/52370

42079

+ * trans-decl.c (gfc_build_dummy_array_decl): Set TREE_NO_WARNING

42080

+ on decl if sym->attr.optional.

42081

+

42082

+2014-03-02 Mikael Morin <mikael@gcc.gnu.org>

42083

+

42084

+ PR fortran/60341

42085

+ * frontend-passes.c (optimize_comparison): Guard two union accesses

42086

+ with the corresponding tag checks.

42087

+

42088

+2014-02-22 Mikael Morin <mikael@gcc.gnu.org>

42089

+

42090

+ PR fortran/59599

42091

+ * trans-intrinsic.c (gfc_conv_intrinsic_ichar): Calculate the

42092

+ number of arguments.

42093

+

42094

+2014-02-19 Tobias Burnus <burnus@net-b.de>

42095

+

42096

+ PR fortran/49397

42097

+ * expr.c (gfc_check_pointer_assign): Add check for

42098

+ F2008Cor2, C729.

42099

+ * trans-decl.c (gfc_get_symbol_decl): Correctly generate

42100

+ external decl in a corner case.

42101

+

42102

+2014-02-19 Janus Weil <janus@gcc.gnu.org>

42103

+

42104

+ Backports from mainline:

42105

+ 2014-02-17 Janus Weil <janus@gcc.gnu.org>

42106

+

42107

+ PR fortran/55907

42108

+ * resolve.c (build_default_init_expr): Don't initialize character

42109

+ variable if -fno-automatic is given.

42110

+

42111

+ 2014-02-18 Janus Weil <janus@gcc.gnu.org>

42112

+

42113

+ PR fortran/60231

42114

+ * resolve.c (check_generic_tbp_ambiguity): Check for presence of dummy

42115

+ arguments to prevent ICE.

42116

+

42117

+2014-02-09 Janus Weil <janus@gcc.gnu.org>

42118

+

42119

+ Backport from mainline

42120

+ 2013-10-21 Tobias Burnus <burnus@net-b.de>

42121

+

42122

+ PR fortran/58803

42123

+ PR fortran/59395

42124

+ * decl.c (match_ppc_decl): Prevent later double free.

42125

+

42126

+2014-02-08 Mikael Morin <mikael@gcc.gnu.org>

42127

+

42128

+ PR fortran/57033

42129

+ * primary.c (gfc_convert_to_structure_constructor): Avoid null pointer

42130

+ dereference.

42131

+

42132

+2014-02-07 Paul Thomas <pault@gcc.gnu.org>

42133

+

42134

+ PR fortran/59906

42135

+ * trans-stmt.c (gfc_add_loop_ss_code): In the case of character

42136

+ SS_REFERENCE, use gfc_conv_string_parameter to ensure that a

42137

+ pointer to the string is stored.

42138

+ * trans-expr.c (gfc_conv_expr_reference): Likewise, use

42139

+ gfc_conv_string_parameter to ensure that a pointer to is passed

42140

+ to the elemental function.

42141

+

42142

+2014-02-01 Paul Thomas <pault@gcc.gnu.org>

42143

+

42144

+ PR fortran/59414

42145

+ * trans-stmt.c (gfc_trans_allocate): Before the pointer

42146

+ assignment to transfer the source _vptr to a class allocate

42147

+ expression, the final class reference should be exposed. The

42148

+ tail that includes the _data and array references is stored.

42149

+ This reduced expression is transferred to 'lhs' and the _vptr

42150

+ added. Then the tail is restored to the allocate expression.

42151

+

42152

+2014-01-26 Mikael Morin <mikael@gcc.gnu.org>

42153

+

42154

+ PR fortran/58007

42155

+ * module.c

42156

+ (fp2, find_pointer2): Remove.

42157

+ (mio_component_ref): Don't forcedfully set the containing derived type

42158

+ symbol for loading. Remove unused argument.

42159

+ (mio_ref): Update caller

42160

+ (skip_list): New argument nest_level. Initialize level with the new

42161

+ argument.

42162

+ (read_module): Add forced pointer components association for derived

42163

+ type symbols.

42164

+

42165

+2014-01-19 Paul Thomas <pault@gcc.gnu.org>

42166

+

42167

+ Backport from mainline

42168

+ 2013-12-01 Paul Thomas <pault@gcc.gnu.org>

42169

+

42170

+ PR fortran/58410

42171

+ * trans-array.c (gfc_alloc_allocatable_for_assignment): Do not

42172

+ use the array bounds of an unallocated array but set its size

42173

+ to zero instead.

42174

+

42175

+2014-01-19 Paul Thomas <pault@gcc.gnu.org>

42176

+

42177

+ Backport from mainline

42178

+ 2013-12-01 Paul Thomas <pault@gcc.gnu.org>

42179

+

42180

+ PR fortran/34547

42181

+ * resolve.c (resolve_transfer): EXPR_NULL is always in an

42182

+ invalid context in a transfer statement.

42183

+

42184

+2014-01-11 Janus Weil <janus@gcc.gnu.org>

42185

+

42186

+ Backport from mainline

42187

+ 2013-12-29 Janus Weil <janus@gcc.gnu.org>

42188

+

42189

+ PR fortran/59612

42190

+ PR fortran/57042

42191

+ * dump-parse-tree.c (show_typespec): Check for charlen.

42192

+ * invoke.texi: Fix documentation of -fdump-fortran-optimized and

42193

+ -fdump-parse-tree.

42194

+

42195

+2014-01-04 Janus Weil <janus@gcc.gnu.org>

42196

+

42197

+ Backport from mainline

42198

+ 2014-01-02 Janus Weil <janus@gcc.gnu.org>

42199

+

42200

+ PR fortran/59654

42201

+ * resolve.c (resolve_typebound_procedures): No need to create the vtab

42202

+ here.

42203

+

42204

+2013-12-31 Janus Weil <janus@gcc.gnu.org>

42205

+

42206

+ Backport from mainline

42207

+ 2013-12-30 Janus Weil <janus@gcc.gnu.org>

42208

+

42209

+ PR fortran/58998

42210

+ * resolve.c (resolve_symbol): Check that symbol is not only flavorless

42211

+ but also untyped.

42212

+

42213

+2013-12-18 Janus Weil <janus@gcc.gnu.org>

42214

+

42215

+ Backport from mainline

42216

+ 2013-12-15 Janus Weil <janus@gcc.gnu.org>

42217

+

42218

+ PR fortran/59493

42219

+ * class.c (gfc_find_intrinsic_vtab): Handle BT_CLASS.

42220

+

42221

+2013-11-30 Paul Thomas <pault@gcc.gnu.org>

42222

+

42223

+ Backport from mainline

42224

+ 2013-11-04 Paul Thomas <pault@gcc.gnu.org>

42225

+

42226

+ PR fortran/57445

42227

+ * trans-expr.c (gfc_conv_class_to_class): Remove spurious

42228

+ assert.

42229

+

42230

+2013-11-17 Janus Weil <janus@gcc.gnu.org>

42231

+

42232

+ Backport from mainline

42233

+ 2013-11-07 Janus Weil <janus@gcc.gnu.org>

42234

+

42235

+ PR fortran/58471

42236

+ * primary.c (gfc_expr_attr): Check for result symbol.

42237

+

42238

+2013-11-16 Janus Weil <janus@gcc.gnu.org>

42239

+

42240

+ Backport from mainline

42241

+ 2013-09-20 Janus Weil <janus@gcc.gnu.org>

42242

+

42243

+ PR fortran/58099

42244

+ * expr.c (gfc_check_pointer_assign): Remove second call to

42245

+ 'gfc_compare_interfaces' with swapped arguments.

42246

+ * interface.c (gfc_compare_interfaces): Symmetrize the call to

42247

+ 'check_result_characteristics' by calling it with swapped arguments.

42248

+

42249

+2013-11-16 Paul Thomas <pault@gcc.gnu.org>

42250

+

42251

+ PR fortran/58771

42252

+ * trans-io.c (transfer_expr): If the backend_decl for a derived

42253

+ type is missing, build it with gfc_typenode_for_spec.

42254

+

42255

+2013-11-05 Steven G. Kargl <kargl@gcc.gnu.org>

42256

+

42257

+ PR fortran/58989

42258

+ * check.c (gfc_check_reshape): ensure that shape is a constant

42259

+ expression.

42260

+

42261

+2013-11-02 Janus Weil <janus@gcc.gnu.org>

42262

+

42263

+ Backport from mainline

42264

+ 2013-09-23 Janus Weil <janus@gcc.gnu.org>

42265

+

42266

+ PR fortran/58355

42267

+ * decl.c (check_extended_derived_type): Prevent segfault, modify error

42268

+ message.

42269

+

42270

2013-10-16 Release Manager

42271

42272

* GCC 4.8.2 released.

42273

Index: gcc/fortran/trans-stmt.c

42274

===================================================================

42275

--- a/src/gcc/fortran/trans-stmt.c (.../tags/gcc_4_8_2_release)

42276

+++ b/src/gcc/fortran/trans-stmt.c (.../branches/gcc-4_8-branch)

42277

@@ -5104,10 +5104,49 @@

42278

{

42279

gfc_expr *lhs, *rhs;

42280

gfc_se lse;

42281

+ gfc_ref *ref, *class_ref, *tail;

42282

42283

+ /* Find the last class reference. */

42284

+ class_ref = NULL;

42285

+ for (ref = e->ref; ref; ref = ref->next)

42286

+ {

42287

+ if (ref->type == REF_COMPONENT

42288

+ && ref->u.c.component->ts.type == BT_CLASS)

42289

+ class_ref = ref;

42290

+

42291

+ if (ref->next == NULL)

42292

+ break;

42293

+ }

42294

+

42295

+ /* Remove and store all subsequent references after the

42296

+ CLASS reference. */

42297

+ if (class_ref)

42298

+ {

42299

+ tail = class_ref->next;

42300

+ class_ref->next = NULL;

42301

+ }

42302

+ else

42303

+ {

42304

+ tail = e->ref;

42305

+ e->ref = NULL;

42306

+ }

42307

+

42308

lhs = gfc_expr_to_initialize (e);

42309

gfc_add_vptr_component (lhs);

42310

42311

+ /* Remove the _vptr component and restore the original tail

42312

+ references. */

42313

+ if (class_ref)

42314

+ {

42315

+ gfc_free_ref_list (class_ref->next);

42316

+ class_ref->next = tail;

42317

+ }

42318

+ else

42319

+ {

42320

+ gfc_free_ref_list (e->ref);

42321

+ e->ref = tail;

42322

+ }

42323

+

42324

if (class_expr != NULL_TREE)

42325

{

42326

/* Polymorphic SOURCE: VPTR must be determined at run time. */

42327

Index: gcc/fortran/expr.c

42328

===================================================================

42329

--- a/src/gcc/fortran/expr.c (.../tags/gcc_4_8_2_release)

42330

+++ b/src/gcc/fortran/expr.c (.../branches/gcc-4_8-branch)

42331

@@ -3555,11 +3555,13 @@

42332

return FAILURE;

42333

}

42334

42335

- if (!gfc_compare_interfaces (s2, s1, name, 0, 1,

42336

- err, sizeof(err), NULL, NULL))

42337

+ /* Check F2008Cor2, C729. */

42338

+ if (!s2->attr.intrinsic && s2->attr.if_source == IFSRC_UNKNOWN

42339

+ && !s2->attr.external && !s2->attr.subroutine && !s2->attr.function)

42340

{

42341

- gfc_error ("Interface mismatch in procedure pointer assignment "

42342

- "at %L: %s", &rvalue->where, err);

42343

+ gfc_error ("Procedure pointer target '%s' at %L must be either an "

42344

+ "intrinsic, host or use associated, referenced or have "

42345

+ "the EXTERNAL attribute", s2->name, &rvalue->where);

42346

return FAILURE;

42347

}

42348

42349

@@ -3679,9 +3681,8 @@

42350

}

42351

42352

if (is_implicit_pure && gfc_impure_variable (rvalue->symtree->n.sym))

42353

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

42354

+ gfc_unset_implicit_pure (gfc_current_ns->proc_name);

42355

42356

-

42357

if (gfc_has_vector_index (rvalue))

42358

{

42359

gfc_error ("Pointer assignment with vector subscript "

42360

Index: gcc/fortran/module.c

42361

===================================================================

42362

--- a/src/gcc/fortran/module.c (.../tags/gcc_4_8_2_release)

42363

+++ b/src/gcc/fortran/module.c (.../branches/gcc-4_8-branch)

42364

@@ -386,37 +386,6 @@

42365

}

42366

42367

42368

-/* Recursive function to find a pointer within a tree by brute force. */

42369

-

42370

-static pointer_info *

42371

-fp2 (pointer_info *p, const void *target)

42372

-{

42373

- pointer_info *q;

42374

-

42375

- if (p == NULL)

42376

- return NULL;

42377

-

42378

- if (p->u.pointer == target)

42379

- return p;

42380

-

42381

- q = fp2 (p->left, target);

42382

- if (q != NULL)

42383

- return q;

42384

-

42385

- return fp2 (p->right, target);

42386

-}

42387

-

42388

-

42389

-/* During reading, find a pointer_info node from the pointer value.

42390

- This amounts to a brute-force search. */

42391

-

42392

-static pointer_info *

42393

-find_pointer2 (void *p)

42394

-{

42395

- return fp2 (pi_root, p);

42396

-}

42397

-

42398

-

42399

/* Resolve any fixups using a known pointer. */

42400

42401

static void

42402

@@ -2522,45 +2491,13 @@

42403

the namespace and is not loaded again. */

42404

42405

static void

42406

-mio_component_ref (gfc_component **cp, gfc_symbol *sym)

42407

+mio_component_ref (gfc_component **cp)

42408

{

42409

- char name[GFC_MAX_SYMBOL_LEN + 1];

42410

- gfc_component *q;

42411

pointer_info *p;

42412

42413

p = mio_pointer_ref (cp);

42414

if (p->type == P_UNKNOWN)

42415

p->type = P_COMPONENT;

42416

-

42417

- if (iomode == IO_OUTPUT)

42418

- mio_pool_string (&(*cp)->name);

42419

- else

42420

- {

42421

- mio_internal_string (name);

42422

-

42423

- if (sym && sym->attr.is_class)

42424

- sym = sym->components->ts.u.derived;

42425

-

42426

- /* It can happen that a component reference can be read before the

42427

- associated derived type symbol has been loaded. Return now and

42428

- wait for a later iteration of load_needed. */

42429

- if (sym == NULL)

42430

- return;

42431

-

42432

- if (sym->components != NULL && p->u.pointer == NULL)

42433

- {

42434

- /* Symbol already loaded, so search by name. */

42435

- q = gfc_find_component (sym, name, true, true);

42436

-

42437

- if (q)

42438

- associate_integer_pointer (p, q);

42439

- }

42440

-

42441

- /* Make sure this symbol will eventually be loaded. */

42442

- p = find_pointer2 (sym);

42443

- if (p->u.rsym.state == UNUSED)

42444

- p->u.rsym.state = NEEDED;

42445

- }

42446

}

42447

42448

42449

@@ -2917,7 +2854,7 @@

42450

42451

case REF_COMPONENT:

42452

mio_symbol_ref (&r->u.c.sym);

42453

- mio_component_ref (&r->u.c.component, r->u.c.sym);

42454

+ mio_component_ref (&r->u.c.component);

42455

break;

42456

42457

case REF_SUBSTRING:

42458

@@ -3772,7 +3709,9 @@

42459

42460

42461

/* Unlike most other routines, the address of the symbol node is already

42462

- fixed on input and the name/module has already been filled in. */

42463

+ fixed on input and the name/module has already been filled in.

42464

+ If you update the symbol format here, don't forget to update read_module

42465

+ as well (look for "seek to the symbol's component list"). */

42466

42467

static void

42468

mio_symbol (gfc_symbol *sym)

42469

@@ -3782,6 +3721,7 @@

42470

mio_lparen ();

42471

42472

mio_symbol_attribute (&sym->attr);

42473

+

42474

mio_typespec (&sym->ts);

42475

if (sym->ts.type == BT_CLASS)

42476

sym->attr.class_ok = 1;

42477

@@ -3812,7 +3752,6 @@

42478

42479

/* Note that components are always saved, even if they are supposed

42480

to be private. Component access is checked during searching. */

42481

-

42482

mio_component_list (&sym->components, sym->attr.vtype);

42483

42484

if (sym->components != NULL)

42485

@@ -3914,14 +3853,17 @@

42486

}

42487

42488

42489

-/* Skip a list between balanced left and right parens. */

42490

+/* Skip a list between balanced left and right parens.

42491

+ By setting NEST_LEVEL one assumes that a number of NEST_LEVEL opening parens

42492

+ have been already parsed by hand, and the remaining of the content is to be

42493

+ skipped here. The default value is 0 (balanced parens). */

42494

42495

static void

42496

-skip_list (void)

42497

+skip_list (int nest_level = 0)

42498

{

42499

int level;

42500

42501

- level = 0;

42502

+ level = nest_level;

42503

do

42504

{

42505

switch (parse_atom ())

42506

@@ -4555,7 +4497,6 @@

42507

info->u.rsym.ns = atom_int;

42508

42509

get_module_locus (&info->u.rsym.where);

42510

- skip_list ();

42511

42512

/* See if the symbol has already been loaded by a previous module.

42513

If so, we reference the existing symbol and prevent it from

42514

@@ -4566,11 +4507,57 @@

42515

42516

if (sym == NULL

42517

|| (sym->attr.flavor == FL_VARIABLE && info->u.rsym.ns !=1))

42518

- continue;

42519

+ {

42520

+ skip_list ();

42521

+ continue;

42522

+ }

42523

42524

info->u.rsym.state = USED;

42525

info->u.rsym.sym = sym;

42526

+ /* The current symbol has already been loaded, so we can avoid loading

42527

+ it again. However, if it is a derived type, some of its components

42528

+ can be used in expressions in the module. To avoid the module loading

42529

+ failing, we need to associate the module's component pointer indexes

42530

+ with the existing symbol's component pointers. */

42531

+ if (sym->attr.flavor == FL_DERIVED)

42532

+ {

42533

+ gfc_component *c;

42534

42535

+ /* First seek to the symbol's component list. */

42536

+ mio_lparen (); /* symbol opening. */

42537

+ skip_list (); /* skip symbol attribute. */

42538

+ skip_list (); /* typespec. */

42539

+ require_atom (ATOM_INTEGER); /* namespace ref. */

42540

+ require_atom (ATOM_INTEGER); /* common ref. */

42541

+ skip_list (); /* formal args. */

42542

+ /* no value. */

42543

+ skip_list (); /* array_spec. */

42544

+ require_atom (ATOM_INTEGER); /* result. */

42545

+ /* not a cray pointer. */

42546

+

42547

+ mio_lparen (); /* component list opening. */

42548

+ for (c = sym->components; c; c = c->next)

42549

+ {

42550

+ pointer_info *p;

42551

+ const char *comp_name;

42552

+ int n;

42553

+

42554

+ mio_lparen (); /* component opening. */

42555

+ mio_integer (&n);

42556

+ p = get_integer (n);

42557

+ if (p->u.pointer == NULL)

42558

+ associate_integer_pointer (p, c);

42559

+ mio_pool_string (&comp_name);

42560

+ gcc_assert (comp_name == c->name);

42561

+ skip_list (1); /* component end. */

42562

+ }

42563

+ mio_rparen (); /* component list closing. */

42564

+

42565

+ skip_list (1); /* symbol end. */

42566

+ }

42567

+ else

42568

+ skip_list ();

42569

+

42570

/* Some symbols do not have a namespace (eg. formal arguments),

42571

so the automatic "unique symtree" mechanism must be suppressed

42572

by marking them as referenced. */

42573

Index: gcc/fortran/io.c

42574

===================================================================

42575

--- a/src/gcc/fortran/io.c (.../tags/gcc_4_8_2_release)

42576

+++ b/src/gcc/fortran/io.c (.../branches/gcc-4_8-branch)

42577

@@ -1309,7 +1309,8 @@

42578

return MATCH_ERROR;

42579

}

42580

42581

- if (gfc_pure (NULL) && gfc_impure_variable (result->symtree->n.sym))

42582

+ bool impure = gfc_impure_variable (result->symtree->n.sym);

42583

+ if (impure && gfc_pure (NULL))

42584

{

42585

gfc_error ("Variable %s cannot be assigned in PURE procedure at %C",

42586

tag->name);

42587

@@ -1317,8 +1318,8 @@

42588

return MATCH_ERROR;

42589

}

42590

42591

- if (gfc_implicit_pure (NULL) && gfc_impure_variable (result->symtree->n.sym))

42592

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

42593

+ if (impure)

42594

+ gfc_unset_implicit_pure (NULL);

42595

42596

*v = result;

42597

return MATCH_YES;

42598

@@ -1838,8 +1839,7 @@

42599

goto cleanup;

42600

}

42601

42602

- if (gfc_implicit_pure (NULL))

42603

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

42604

+ gfc_unset_implicit_pure (NULL);

42605

42606

warn = (open->err || open->iostat) ? true : false;

42607

42608

@@ -2251,8 +2251,7 @@

42609

goto cleanup;

42610

}

42611

42612

- if (gfc_implicit_pure (NULL))

42613

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

42614

+ gfc_unset_implicit_pure (NULL);

42615

42616

warn = (close->iostat || close->err) ? true : false;

42617

42618

@@ -2419,8 +2418,7 @@

42619

goto cleanup;

42620

}

42621

42622

- if (gfc_implicit_pure (NULL))

42623

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

42624

+ gfc_unset_implicit_pure (NULL);

42625

42626

new_st.op = op;

42627

new_st.ext.filepos = fp;

42628

@@ -3276,9 +3274,8 @@

42629

"an internal file in a PURE procedure",

42630

io_kind_name (k));

42631

42632

- if (gfc_implicit_pure (NULL) && (k == M_READ || k == M_WRITE))

42633

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

42634

-

42635

+ if (k == M_READ || k == M_WRITE)

42636

+ gfc_unset_implicit_pure (NULL);

42637

}

42638

42639

if (k != M_READ)

42640

@@ -3809,8 +3806,7 @@

42641

return MATCH_ERROR;

42642

}

42643

42644

- if (gfc_implicit_pure (NULL))

42645

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

42646

+ gfc_unset_implicit_pure (NULL);

42647

42648

return MATCH_YES;

42649

}

42650

@@ -3969,8 +3965,7 @@

42651

return MATCH_ERROR;

42652

}

42653

42654

- if (gfc_implicit_pure (NULL))

42655

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

42656

+ gfc_unset_implicit_pure (NULL);

42657

42658

new_st.block = gfc_get_code ();

42659

new_st.block->op = EXEC_IOLENGTH;

42660

@@ -4023,8 +4018,7 @@

42661

goto cleanup;

42662

}

42663

42664

- if (gfc_implicit_pure (NULL))

42665

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

42666

+ gfc_unset_implicit_pure (NULL);

42667

42668

if (inquire->id != NULL && inquire->pending == NULL)

42669

{

42670

@@ -4212,8 +4206,7 @@

42671

goto cleanup;

42672

}

42673

42674

- if (gfc_implicit_pure (NULL))

42675

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

42676

+ gfc_unset_implicit_pure (NULL);

42677

42678

new_st.op = EXEC_WAIT;

42679

new_st.ext.wait = wait;

42680

Index: gcc/fortran/frontend-passes.c

42681

===================================================================

42682

--- a/src/gcc/fortran/frontend-passes.c (.../tags/gcc_4_8_2_release)

42683

+++ b/src/gcc/fortran/frontend-passes.c (.../branches/gcc-4_8-branch)

42684

@@ -623,12 +623,35 @@

42685

to insert statements as needed. */

42686

42687

static int

42688

-cfe_code (gfc_code **c, int *walk_subtrees ATTRIBUTE_UNUSED,

42689

- void *data ATTRIBUTE_UNUSED)

42690

+cfe_code (gfc_code **c, int *walk_subtrees, void *data ATTRIBUTE_UNUSED)

42691

{

42692

current_code = c;

42693

inserted_block = NULL;

42694

changed_statement = NULL;

42695

+

42696

+ /* Do not do anything inside a WHERE statement; scalar assignments, BLOCKs

42697

+ and allocation on assigment are prohibited inside WHERE, and finally

42698

+ masking an expression would lead to wrong-code when replacing

42699

+

42700

+ WHERE (a>0)

42701

+ b = sum(foo(a) + foo(a))

42702

+ END WHERE

42703

+

42704

+ with

42705

+

42706

+ WHERE (a > 0)

42707

+ tmp = foo(a)

42708

+ b = sum(tmp + tmp)

42709

+ END WHERE

42710

+*/

42711

+

42712

+ if ((*c)->op == EXEC_WHERE)

42713

+ {

42714

+ *walk_subtrees = 0;

42715

+ return 0;

42716

+ }

42717

+

42718

+

42719

return 0;

42720

}

42721

42722

@@ -1214,7 +1237,9 @@

42723

/* Replace A // B < A // C with B < C, and A // B < C // B

42724

with A < C. */

42725

if (op1->ts.type == BT_CHARACTER && op2->ts.type == BT_CHARACTER

42726

+ && op1->expr_type == EXPR_OP

42727

&& op1->value.op.op == INTRINSIC_CONCAT

42728

+ && op2->expr_type == EXPR_OP

42729

&& op2->value.op.op == INTRINSIC_CONCAT)

42730

{

42731

gfc_expr *op1_left = op1->value.op.op1;

42732

Index: gcc/fortran/resolve.c

42733

===================================================================

42734

--- a/src/gcc/fortran/resolve.c (.../tags/gcc_4_8_2_release)

42735

+++ b/src/gcc/fortran/resolve.c (.../branches/gcc-4_8-branch)

42736

@@ -1,5 +1,5 @@

42737

/* Perform type resolution on the various structures.

42738

42739

42740

Contributed by Andy Vaught

42741

42742

This file is part of GCC.

42743

@@ -1259,9 +1259,10 @@

42744

}

42745

42746

/* F2003, C1272 (3). */

42747

- if (gfc_pure (NULL) && cons->expr->expr_type == EXPR_VARIABLE

42748

- && (gfc_impure_variable (cons->expr->symtree->n.sym)

42749

- || gfc_is_coindexed (cons->expr)))

42750

+ bool impure = cons->expr->expr_type == EXPR_VARIABLE

42751

+ && (gfc_impure_variable (cons->expr->symtree->n.sym)

42752

+ || gfc_is_coindexed (cons->expr));

42753

+ if (impure && gfc_pure (NULL))

42754

{

42755

t = FAILURE;

42756

gfc_error ("Invalid expression in the structure constructor for "

42757

@@ -1269,12 +1270,8 @@

42758

comp->name, &cons->expr->where);

42759

}

42760

42761

- if (gfc_implicit_pure (NULL)

42762

- && cons->expr->expr_type == EXPR_VARIABLE

42763

- && (gfc_impure_variable (cons->expr->symtree->n.sym)

42764

- || gfc_is_coindexed (cons->expr)))

42765

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

42766

-

42767

+ if (impure)

42768

+ gfc_unset_implicit_pure (NULL);

42769

}

42770

42771

return t;

42772

@@ -3295,8 +3292,7 @@

42773

t = FAILURE;

42774

}

42775

42776

- if (gfc_implicit_pure (NULL))

42777

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

42778

+ gfc_unset_implicit_pure (NULL);

42779

}

42780

42781

/* Functions without the RECURSIVE attribution are not allowed to

42782

@@ -3361,8 +3357,7 @@

42783

gfc_error ("Subroutine call to '%s' at %L is not PURE", sym->name,

42784

&c->loc);

42785

42786

- if (gfc_implicit_pure (NULL))

42787

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

42788

+ gfc_unset_implicit_pure (NULL);

42789

}

42790

42791

42792

@@ -8705,10 +8700,11 @@

42793

&& exp->value.op.op == INTRINSIC_PARENTHESES)

42794

exp = exp->value.op.op1;

42795

42796

- if (exp && exp->expr_type == EXPR_NULL && exp->ts.type == BT_UNKNOWN)

42797

+ if (exp && exp->expr_type == EXPR_NULL

42798

+ && code->ext.dt)

42799

{

42800

- gfc_error ("NULL intrinsic at %L in data transfer statement requires "

42801

- "MOLD=", &exp->where);

42802

+ gfc_error ("Invalid context for NULL () intrinsic at %L",

42803

+ &exp->where);

42804

return;

42805

}

42806

42807

@@ -9612,7 +9608,7 @@

42808

if (lhs->expr_type == EXPR_VARIABLE

42809

&& lhs->symtree->n.sym != gfc_current_ns->proc_name

42810

&& lhs->symtree->n.sym->ns != gfc_current_ns)

42811

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

42812

+ gfc_unset_implicit_pure (NULL);

42813

42814

if (lhs->ts.type == BT_DERIVED

42815

&& lhs->expr_type == EXPR_VARIABLE

42816

@@ -9620,11 +9616,11 @@

42817

&& rhs->expr_type == EXPR_VARIABLE

42818

&& (gfc_impure_variable (rhs->symtree->n.sym)

42819

|| gfc_is_coindexed (rhs)))

42820

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

42821

+ gfc_unset_implicit_pure (NULL);

42822

42823

/* Fortran 2008, C1283. */

42824

if (gfc_is_coindexed (lhs))

42825

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

42826

+ gfc_unset_implicit_pure (NULL);

42827

}

42828

42829

/* F03:7.4.1.2. */

42830

@@ -11057,7 +11053,7 @@

42831

init_expr = NULL;

42832

}

42833

if (!init_expr && gfc_option.flag_init_character == GFC_INIT_CHARACTER_ON

42834

- && sym->ts.u.cl->length)

42835

+ && sym->ts.u.cl->length && gfc_option.flag_max_stack_var_size != 0)

42836

{

42837

gfc_actual_arglist *arg;

42838

init_expr = gfc_get_expr ();

42839

@@ -11877,6 +11873,7 @@

42840

{

42841

gfc_symbol *sym1, *sym2;

42842

const char *pass1, *pass2;

42843

+ gfc_formal_arglist *dummy_args;

42844

42845

gcc_assert (t1->specific && t2->specific);

42846

gcc_assert (!t1->specific->is_generic);

42847

@@ -11899,19 +11896,33 @@

42848

return FAILURE;

42849

}

42850

42851

- /* Compare the interfaces. */

42852

+ /* Determine PASS arguments. */

42853

if (t1->specific->nopass)

42854

pass1 = NULL;

42855

else if (t1->specific->pass_arg)

42856

pass1 = t1->specific->pass_arg;

42857

else

42858

- pass1 = gfc_sym_get_dummy_args (t1->specific->u.specific->n.sym)->sym->name;

42859

+ {

42860

+ dummy_args = gfc_sym_get_dummy_args (t1->specific->u.specific->n.sym);

42861

+ if (dummy_args)

42862

+ pass1 = dummy_args->sym->name;

42863

+ else

42864

+ pass1 = NULL;

42865

+ }

42866

if (t2->specific->nopass)

42867

pass2 = NULL;

42868

else if (t2->specific->pass_arg)

42869

pass2 = t2->specific->pass_arg;

42870

else

42871

- pass2 = gfc_sym_get_dummy_args (t2->specific->u.specific->n.sym)->sym->name;

42872

+ {

42873

+ dummy_args = gfc_sym_get_dummy_args (t2->specific->u.specific->n.sym);

42874

+ if (dummy_args)

42875

+ pass2 = dummy_args->sym->name;

42876

+ else

42877

+ pass2 = NULL;

42878

+ }

42879

+

42880

+ /* Compare the interfaces. */

42881

if (gfc_compare_interfaces (sym1, sym2, sym2->name, !t1->is_operator, 0,

42882

NULL, 0, pass1, pass2))

42883

{

42884

@@ -12425,9 +12436,6 @@

42885

resolve_bindings_derived = derived;

42886

resolve_bindings_result = SUCCESS;

42887

42888

- /* Make sure the vtab has been generated. */

42889

- gfc_find_derived_vtab (derived);

42890

-

42891

if (derived->f2k_derived->tb_sym_root)

42892

gfc_traverse_symtree (derived->f2k_derived->tb_sym_root,

42893

&resolve_typebound_procedure);

42894

@@ -13256,7 +13264,8 @@

42895

if (sym->attr.flavor == FL_UNKNOWN

42896

|| (sym->attr.flavor == FL_PROCEDURE && !sym->attr.intrinsic

42897

&& !sym->attr.generic && !sym->attr.external

42898

- && sym->attr.if_source == IFSRC_UNKNOWN))

42899

+ && sym->attr.if_source == IFSRC_UNKNOWN

42900

+ && sym->ts.type == BT_UNKNOWN))

42901

{

42902

42903

/* If we find that a flavorless symbol is an interface in one of the

42904

@@ -14376,6 +14385,33 @@

42905

}

42906

42907

42908

+void

42909

+gfc_unset_implicit_pure (gfc_symbol *sym)

42910

+{

42911

+ gfc_namespace *ns;

42912

+

42913

+ if (sym == NULL)

42914

+ {

42915

+ /* Check if the current procedure is implicit_pure. Walk up

42916

+ the procedure list until we find a procedure. */

42917

+ for (ns = gfc_current_ns; ns; ns = ns->parent)

42918

+ {

42919

+ sym = ns->proc_name;

42920

+ if (sym == NULL)

42921

+ return;

42922

+

42923

+ if (sym->attr.flavor == FL_PROCEDURE)

42924

+ break;

42925

+ }

42926

+ }

42927

+

42928

+ if (sym->attr.flavor == FL_PROCEDURE)

42929

+ sym->attr.implicit_pure = 0;

42930

+ else

42931

+ sym->attr.pure = 0;

42932

+}

42933

+

42934

+

42935

/* Test whether the current procedure is elemental or not. */

42936

42937

int

42938

Index: gcc/fortran/trans-io.c

42939

===================================================================

42940

--- a/src/gcc/fortran/trans-io.c (.../tags/gcc_4_8_2_release)

42941

+++ b/src/gcc/fortran/trans-io.c (.../branches/gcc-4_8-branch)

42942

@@ -243,16 +243,16 @@

42943

42944

/* The code to generate the error. */

42945

gfc_start_block (&block);

42946

-

42947

+

42948

arg1 = gfc_build_addr_expr (NULL_TREE, var);

42949

-

42950

+

42951

arg2 = build_int_cst (integer_type_node, error_code),

42952

-

42953

+

42954

asprintf (&message, "%s", _(msgid));

42955

arg3 = gfc_build_addr_expr (pchar_type_node,

42956

gfc_build_localized_cstring_const (message));

42957

free (message);

42958

-

42959

+

42960

tmp = build_call_expr_loc (input_location,

42961

gfor_fndecl_generate_error, 3, arg1, arg2, arg3);

42962

42963

@@ -521,7 +521,7 @@

42964

gfc_trans_io_runtime_check (cond, var, LIBERROR_BAD_UNIT,

42965

"Unit number in I/O statement too small",

42966

&se.pre);

42967

-

42968

+

42969

/* UNIT numbers should be less than the max. */

42970

val = gfc_conv_mpz_to_tree (gfc_integer_kinds[i].huge, 4);

42971

cond = fold_build2_loc (input_location, GT_EXPR, boolean_type_node,

42972

@@ -1000,7 +1000,7 @@

42973

if (p->convert)

42974

mask |= set_string (&block, &post_block, var, IOPARM_open_convert,

42975

p->convert);

42976

-

42977

+

42978

if (p->newunit)

42979

mask |= set_parameter_ref (&block, &post_block, var, IOPARM_open_newunit,

42980

p->newunit);

42981

@@ -1234,7 +1234,7 @@

42982

{

42983

mask |= set_parameter_ref (&block, &post_block, var, IOPARM_inquire_exist,

42984

p->exist);

42985

-

42986

+

42987

if (p->unit && !p->iostat)

42988

{

42989

p->iostat = create_dummy_iostat ();

42990

@@ -1322,7 +1322,7 @@

42991

if (p->pad)

42992

mask |= set_string (&block, &post_block, var, IOPARM_inquire_pad,

42993

p->pad);

42994

-

42995

+

42996

if (p->convert)

42997

mask |= set_string (&block, &post_block, var, IOPARM_inquire_convert,

42998

p->convert);

42999

@@ -1547,7 +1547,7 @@

43000

tree dtype;

43001

tree dt_parm_addr;

43002

tree decl = NULL_TREE;

43003

- int n_dim;

43004

+ int n_dim;

43005

int itype;

43006

int rank = 0;

43007

43008

@@ -2032,7 +2032,7 @@

43009

if (gfc_notification_std (GFC_STD_GNU) != SILENT)

43010

{

43011

gfc_error_now ("Derived type '%s' at %L has PRIVATE components",

43012

- ts->u.derived->name, code != NULL ? &(code->loc) :

43013

+ ts->u.derived->name, code != NULL ? &(code->loc) :

43014

&gfc_current_locus);

43015

return;

43016

}

43017

@@ -2041,7 +2041,7 @@

43018

ts->kind = ts->u.derived->ts.kind;

43019

ts->f90_type = ts->u.derived->ts.f90_type;

43020

}

43021

-

43022

+

43023

kind = ts->kind;

43024

function = NULL;

43025

arg2 = NULL;

43026

@@ -2123,7 +2123,7 @@

43027

function = iocall[IOCALL_X_CHARACTER_WIDE];

43028

else

43029

function = iocall[IOCALL_X_CHARACTER_WIDE_WRITE];

43030

-

43031

+

43032

tmp = gfc_build_addr_expr (NULL_TREE, dt_parm);

43033

tmp = build_call_expr_loc (input_location,

43034

function, 4, tmp, addr_expr, arg2, arg3);

43035

@@ -2158,6 +2158,12 @@

43036

expr = build_fold_indirect_ref_loc (input_location,

43037

expr);

43038

43039

+ /* Make sure that the derived type has been built. An external

43040

+ function, if only referenced in an io statement requires this

43041

+ check (see PR58771). */

43042

+ if (ts->u.derived->backend_decl == NULL_TREE)

43043

+ tmp = gfc_typenode_for_spec (ts);

43044

+

43045

for (c = ts->u.derived->components; c; c = c->next)

43046

{

43047

field = c->backend_decl;

43048

Index: gcc/fortran/trans-decl.c

43049

===================================================================

43050

--- a/src/gcc/fortran/trans-decl.c (.../tags/gcc_4_8_2_release)

43051

+++ b/src/gcc/fortran/trans-decl.c (.../branches/gcc-4_8-branch)

43052

@@ -1013,6 +1013,10 @@

43053

TREE_STATIC (decl) = 0;

43054

DECL_EXTERNAL (decl) = 0;

43055

43056

+ /* Avoid uninitialized warnings for optional dummy arguments. */

43057

+ if (sym->attr.optional)

43058

+ TREE_NO_WARNING (decl) = 1;

43059

+

43060

/* We should never get deferred shape arrays here. We used to because of

43061

frontend bugs. */

43062

gcc_assert (sym->as->type != AS_DEFERRED);

43063

@@ -1358,9 +1362,10 @@

43064

43065

if (sym->attr.flavor == FL_PROCEDURE)

43066

{

43067

- /* Catch function declarations. Only used for actual parameters,

43068

+ /* Catch functions. Only used for actual parameters,

43069

procedure pointers and procptr initialization targets. */

43070

- if (sym->attr.external || sym->attr.use_assoc || sym->attr.intrinsic)

43071

+ if (sym->attr.external || sym->attr.use_assoc || sym->attr.intrinsic

43072

+ || sym->attr.if_source != IFSRC_DECL)

43073

{

43074

decl = gfc_get_extern_function_decl (sym);

43075

gfc_set_decl_location (decl, &sym->declared_at);

43076

Index: gcc/fortran/match.c

43077

===================================================================

43078

--- a/src/gcc/fortran/match.c (.../tags/gcc_4_8_2_release)

43079

+++ b/src/gcc/fortran/match.c (.../branches/gcc-4_8-branch)

43080

@@ -1753,8 +1753,7 @@

43081

return MATCH_ERROR;

43082

}

43083

43084

- if (gfc_implicit_pure (NULL))

43085

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

43086

+ gfc_unset_implicit_pure (NULL);

43087

43088

if (gfc_notify_std (GFC_STD_F2008, "CRITICAL statement at %C")

43089

== FAILURE)

43090

@@ -2683,8 +2682,7 @@

43091

goto cleanup;

43092

}

43093

43094

- if (gfc_implicit_pure (NULL))

43095

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

43096

+ gfc_unset_implicit_pure (NULL);

43097

43098

if (st == ST_STOP && gfc_find_state (COMP_CRITICAL) == SUCCESS)

43099

{

43100

@@ -2824,8 +2822,7 @@

43101

return MATCH_ERROR;

43102

}

43103

43104

- if (gfc_implicit_pure (NULL))

43105

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

43106

+ gfc_unset_implicit_pure (NULL);

43107

43108

if (gfc_option.coarray == GFC_FCOARRAY_NONE)

43109

{

43110

@@ -3020,8 +3017,7 @@

43111

return MATCH_ERROR;

43112

}

43113

43114

- if (gfc_implicit_pure (NULL))

43115

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

43116

+ gfc_unset_implicit_pure (NULL);

43117

43118

if (gfc_notify_std (GFC_STD_F2008, "SYNC statement at %C")

43119

== FAILURE)

43120

@@ -3500,15 +3496,15 @@

43121

if (gfc_check_do_variable (tail->expr->symtree))

43122

goto cleanup;

43123

43124

- if (gfc_pure (NULL) && gfc_impure_variable (tail->expr->symtree->n.sym))

43125

+ bool impure = gfc_impure_variable (tail->expr->symtree->n.sym);

43126

+ if (impure && gfc_pure (NULL))

43127

{

43128

gfc_error ("Bad allocate-object at %C for a PURE procedure");

43129

goto cleanup;

43130

}

43131

43132

- if (gfc_implicit_pure (NULL)

43133

- && gfc_impure_variable (tail->expr->symtree->n.sym))

43134

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

43135

+ if (impure)

43136

+ gfc_unset_implicit_pure (NULL);

43137

43138

if (tail->expr->ts.deferred)

43139

{

43140

@@ -3890,14 +3886,15 @@

43141

43142

sym = tail->expr->symtree->n.sym;

43143

43144

- if (gfc_pure (NULL) && gfc_impure_variable (sym))

43145

+ bool impure = gfc_impure_variable (sym);

43146

+ if (impure && gfc_pure (NULL))

43147

{

43148

gfc_error ("Illegal allocate-object at %C for a PURE procedure");

43149

goto cleanup;

43150

}

43151

43152

- if (gfc_implicit_pure (NULL) && gfc_impure_variable (sym))

43153

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

43154

+ if (impure)

43155

+ gfc_unset_implicit_pure (NULL);

43156

43157

if (gfc_is_coarray (tail->expr)

43158

&& gfc_find_state (COMP_DO_CONCURRENT) == SUCCESS)

43159

Index: gcc/fortran/parse.c

43160

===================================================================

43161

--- a/src/gcc/fortran/parse.c (.../tags/gcc_4_8_2_release)

43162

+++ b/src/gcc/fortran/parse.c (.../branches/gcc-4_8-branch)

43163

@@ -550,8 +550,7 @@

43164

return ST_NONE;

43165

}

43166

43167

- if (gfc_implicit_pure (NULL))

43168

- gfc_current_ns->proc_name->attr.implicit_pure = 0;

43169

+ gfc_unset_implicit_pure (NULL);

43170

43171

old_locus = gfc_current_locus;

43172

43173

Index: gcc/fortran/check.c

43174

===================================================================

43175

--- a/src/gcc/fortran/check.c (.../tags/gcc_4_8_2_release)

43176

+++ b/src/gcc/fortran/check.c (.../branches/gcc-4_8-branch)

43177

@@ -3208,7 +3208,7 @@

43178

"than %d elements", &shape->where, GFC_MAX_DIMENSIONS);

43179

return FAILURE;

43180

}

43181

- else if (shape->expr_type == EXPR_ARRAY)

43182

+ else if (shape->expr_type == EXPR_ARRAY && gfc_is_constant_expr (shape))

43183

{

43184

gfc_expr *e;

43185

int i, extent;

43186

Index: gcc/fortran/primary.c

43187

===================================================================

43188

--- a/src/gcc/fortran/primary.c (.../tags/gcc_4_8_2_release)

43189

+++ b/src/gcc/fortran/primary.c (.../branches/gcc-4_8-branch)

43190

@@ -2252,7 +2252,7 @@

43191

case EXPR_FUNCTION:

43192

gfc_clear_attr (&attr);

43193

43194

- if (e->value.function.esym != NULL)

43195

+ if (e->value.function.esym && e->value.function.esym->result)

43196

{

43197

gfc_symbol *sym = e->value.function.esym->result;

43198

attr = sym->attr;

43199

@@ -2540,7 +2540,8 @@

43200

if (parent && !comp)

43201

break;

43202

43203

- actual = actual->next;

43204

+ if (actual)

43205

+ actual = actual->next;

43206

}

43207

43208

if (build_actual_constructor (&comp_head, &ctor_head, sym) == FAILURE)

43209

Index: gcc/fortran/trans-intrinsic.c

43210

===================================================================

43211

--- a/src/gcc/fortran/trans-intrinsic.c (.../tags/gcc_4_8_2_release)

43212

+++ b/src/gcc/fortran/trans-intrinsic.c (.../branches/gcc-4_8-branch)

43213

@@ -4684,9 +4684,11 @@

43214

static void

43215

gfc_conv_intrinsic_ichar (gfc_se * se, gfc_expr * expr)

43216

{

43217

- tree args[2], type, pchartype;

43218

+ tree args[3], type, pchartype;

43219

+ int nargs;

43220

43221

- gfc_conv_intrinsic_function_args (se, expr, args, 2);

43222

+ nargs = gfc_intrinsic_argument_list_length (expr);

43223

+ gfc_conv_intrinsic_function_args (se, expr, args, nargs);

43224

gcc_assert (POINTER_TYPE_P (TREE_TYPE (args[1])));

43225

pchartype = gfc_get_pchar_type (expr->value.function.actual->expr->ts.kind);

43226

args[1] = fold_build1_loc (input_location, NOP_EXPR, pchartype, args[1]);

43227

Index: gcc/fortran/simplify.c

43228

===================================================================

43229

--- a/src/gcc/fortran/simplify.c (.../tags/gcc_4_8_2_release)

43230

+++ b/src/gcc/fortran/simplify.c (.../branches/gcc-4_8-branch)

43231

@@ -5528,7 +5528,7 @@

43232

if (e == &gfc_bad_expr || range_check (e, "SHAPE") == &gfc_bad_expr)

43233

{

43234

gfc_free_expr (result);

43235

- if (t)

43236

+ if (t == SUCCESS)

43237

gfc_clear_shape (shape, source->rank);

43238

return &gfc_bad_expr;

43239

}

43240

@@ -5536,7 +5536,7 @@

43241

gfc_constructor_append_expr (&result->value.constructor, e, NULL);

43242

}

43243

43244

- if (t)

43245

+ if (t == SUCCESS)

43246

gfc_clear_shape (shape, source->rank);

43247

43248

return result;

43249

Index: gcc/configure.ac

43250

===================================================================

43251

--- a/src/gcc/configure.ac (.../tags/gcc_4_8_2_release)

43252

+++ b/src/gcc/configure.ac (.../branches/gcc-4_8-branch)

43253

@@ -1516,13 +1516,16 @@

43254

/* | [A-Za-z]:[\\/]* ) realsrcdir=${srcdir};;

43255

*) realsrcdir=../${srcdir};;

43256

esac

43257

- saved_CFLAGS="${CFLAGS}"

43258

+ # Clearing GMPINC is necessary to prevent host headers being

43259

+ # used by the build compiler. Defining GENERATOR_FILE stops

43260

+ # system.h from including gmp.h.

43261

CC="${CC_FOR_BUILD}" CFLAGS="${CFLAGS_FOR_BUILD}" \

43262

- LDFLAGS="${LDFLAGS_FOR_BUILD}" \

43263

+ CXX="${CXX_FOR_BUILD}" CXXFLAGS="${CXXFLAGS_FOR_BUILD}" \

43264

+ LD="${LD_FOR_BUILD}" LDFLAGS="${LDFLAGS_FOR_BUILD}" \

43265

+ GMPINC="" CPPFLAGS="${CPPFLAGS} -DGENERATOR_FILE" \

43266

${realsrcdir}/configure \

43267

--enable-languages=${enable_languages-all} \

43268

--target=$target_alias --host=$build_alias --build=$build_alias

43269

- CFLAGS="${saved_CFLAGS}"

43270

43271

# We just finished tests for the build machine, so rename

43272

# the file auto-build.h in the gcc directory.

43273

@@ -1887,6 +1890,7 @@

43274

if test x$build != x$host || test "x$coverage_flags" != x

43275

then

43276

BUILD_CFLAGS='$(INTERNAL_CFLAGS) $(T_CFLAGS) $(CFLAGS_FOR_BUILD)'

43277

+ BUILD_CXXFLAGS='$(INTERNAL_CFLAGS) $(T_CFLAGS) $(CXXFLAGS_FOR_BUILD)'

43278

BUILD_LDFLAGS='$(LDFLAGS_FOR_BUILD)'

43279

fi

43280

43281

@@ -3611,6 +3615,19 @@

43282

kasumi_fi_xor %f46, %f48, %f50, %f52],,

43283

[AC_DEFINE(HAVE_AS_SPARC4, 1,

43284

[Define if your assembler supports SPARC4 instructions.])])

43285

+

43286

+ gcc_GAS_CHECK_FEATURE([LEON instructions],

43287

+ gcc_cv_as_sparc_leon,,

43288

+ [-Aleon],

43289

+ [.text

43290

+ .register %g2, #scratch

43291

+ .register %g3, #scratch

43292

+ .align 4

43293

+ smac %g2, %g3, %g1

43294

+ umac %g2, %g3, %g1

43295

+ casa [[%g2]] 0xb, %g3, %g1],,

43296

+ [AC_DEFINE(HAVE_AS_LEON, 1,

43297

+ [Define if your assembler supports LEON instructions.])])

43298

;;

43299

43300

changequote(,)dnl

43301

@@ -3749,8 +3766,13 @@

43302

43303

# These two are used unconditionally by i386.[ch]; it is to be defined

43304

# to 1 if the feature is present, 0 otherwise.

43305

+ as_ix86_gotoff_in_data_opt=

43306

+ if test x$gas = xyes; then

43307

+ as_ix86_gotoff_in_data_opt="--32"

43308

+ fi

43309

gcc_GAS_CHECK_FEATURE([GOTOFF in data],

43310

- gcc_cv_as_ix86_gotoff_in_data, [2,11,0],,

43311

+ gcc_cv_as_ix86_gotoff_in_data, [2,11,0],

43312

+ [$as_ix86_gotoff_in_data_opt],

43313

[ .text

43314

.L0:

43315

nop

43316

@@ -3772,6 +3794,12 @@

43317

[AC_DEFINE(HAVE_AS_IX86_REP_LOCK_PREFIX, 1,

43318

[Define if the assembler supports 'rep <insn>, lock <insn>'.])])

43319

43320

+ gcc_GAS_CHECK_FEATURE([ud2 mnemonic],

43321

+ gcc_cv_as_ix86_ud2,,,

43322

+ [ud2],,

43323

+ [AC_DEFINE(HAVE_AS_IX86_UD2, 1,

43324

+ [Define if your assembler supports the 'ud2' mnemonic.])])

43325

+

43326

gcc_GAS_CHECK_FEATURE([R_386_TLS_GD_PLT reloc],

43327

gcc_cv_as_ix86_tlsgdplt,,,

43328

[call tls_gd@tlsgdplt],

43329

@@ -5193,15 +5221,15 @@

43330

AC_MSG_CHECKING([for exported symbols])

43331

if test "x$export_sym_check" != x; then

43332

echo "int main() {return 0;} int foobar() {return 0;}" > conftest.c

43333

- ${CC} ${CFLAGS} ${LDFLAGS} conftest.c -o conftest > /dev/null 2>&1

43334

- if $export_sym_check conftest | grep foobar > /dev/null; then

43335

+ ${CC} ${CFLAGS} ${LDFLAGS} conftest.c -o conftest$ac_exeext > /dev/null 2>&1

43336

+ if $export_sym_check conftest$ac_exeext | grep -q foobar > /dev/null; then

43337

: # No need to use a flag

43338

AC_MSG_RESULT([yes])

43339

else

43340

AC_MSG_RESULT([yes])

43341

AC_MSG_CHECKING([for -rdynamic])

43342

- ${CC} ${CFLAGS} ${LDFLAGS} -rdynamic conftest.c -o conftest > /dev/null 2>&1

43343

- if $export_sym_check conftest | grep foobar > /dev/null; then

43344

+ ${CC} ${CFLAGS} ${LDFLAGS} -rdynamic conftest.c -o conftest$ac_exeext > /dev/null 2>&1

43345

+ if $export_sym_check conftest$ac_exeext | grep -q foobar > /dev/null; then

43346

plugin_rdynamic=yes

43347

pluginlibs="-rdynamic"

43348

else

43349

Index: gcc/function.c

43350

===================================================================

43351

--- a/src/gcc/function.c (.../tags/gcc_4_8_2_release)

43352

+++ b/src/gcc/function.c (.../branches/gcc-4_8-branch)

43353

@@ -2507,6 +2507,7 @@

43354

}

43355

43356

locate_and_pad_parm (data->promoted_mode, data->passed_type, in_regs,

43357

+ all->reg_parm_stack_space,

43358

entry_parm ? data->partial : 0, current_function_decl,

43359

&all->stack_args_size, &data->locate);

43360

43361

@@ -3485,11 +3486,7 @@

43362

/* Adjust function incoming argument size for alignment and

43363

minimum length. */

43364

43365

-#ifdef REG_PARM_STACK_SPACE

43366

- crtl->args.size = MAX (crtl->args.size,

43367

- REG_PARM_STACK_SPACE (fndecl));

43368

-#endif

43369

-

43370

+ crtl->args.size = MAX (crtl->args.size, all.reg_parm_stack_space);

43371

crtl->args.size = CEIL_ROUND (crtl->args.size,

43372

PARM_BOUNDARY / BITS_PER_UNIT);

43373

43374

@@ -3693,6 +3690,9 @@

43375

IN_REGS is nonzero if the argument will be passed in registers. It will

43376

never be set if REG_PARM_STACK_SPACE is not defined.

43377

43378

+ REG_PARM_STACK_SPACE is the number of bytes of stack space reserved

43379

+ for arguments which are passed in registers.

43380

+

43381

FNDECL is the function in which the argument was defined.

43382

43383

There are two types of rounding that are done. The first, controlled by

43384

@@ -3713,7 +3713,8 @@

43385

43386

void

43387

locate_and_pad_parm (enum machine_mode passed_mode, tree type, int in_regs,

43388

- int partial, tree fndecl ATTRIBUTE_UNUSED,

43389

+ int reg_parm_stack_space, int partial,

43390

+ tree fndecl ATTRIBUTE_UNUSED,

43391

struct args_size *initial_offset_ptr,

43392

struct locate_and_pad_arg_data *locate)

43393

{

43394

@@ -3720,12 +3721,8 @@

43395

tree sizetree;

43396

enum direction where_pad;

43397

unsigned int boundary, round_boundary;

43398

- int reg_parm_stack_space = 0;

43399

int part_size_in_regs;

43400

43401

-#ifdef REG_PARM_STACK_SPACE

43402

- reg_parm_stack_space = REG_PARM_STACK_SPACE (fndecl);

43403

-

43404

/* If we have found a stack parm before we reach the end of the

43405

area reserved for registers, skip that area. */

43406

if (! in_regs)

43407

@@ -3743,7 +3740,6 @@

43408

initial_offset_ptr->constant = reg_parm_stack_space;

43409

}

43410

}

43411

-#endif /* REG_PARM_STACK_SPACE */

43412

43413

part_size_in_regs = (reg_parm_stack_space == 0 ? partial : 0);

43414

43415

@@ -3806,11 +3802,7 @@

43416

43417

locate->slot_offset.constant += part_size_in_regs;

43418

43419

- if (!in_regs

43420

-#ifdef REG_PARM_STACK_SPACE

43421

- || REG_PARM_STACK_SPACE (fndecl) > 0

43422

-#endif

43423

- )

43424

+ if (!in_regs || reg_parm_stack_space > 0)

43425

pad_to_arg_alignment (&locate->slot_offset, boundary,

43426

&locate->alignment_pad);

43427

43428

@@ -3830,11 +3822,7 @@

43429

pad_below (&locate->offset, passed_mode, sizetree);

43430

43431

#else /* !ARGS_GROW_DOWNWARD */

43432

- if (!in_regs

43433

-#ifdef REG_PARM_STACK_SPACE

43434

- || REG_PARM_STACK_SPACE (fndecl) > 0

43435

-#endif

43436

- )

43437

+ if (!in_regs || reg_parm_stack_space > 0)

43438

pad_to_arg_alignment (initial_offset_ptr, boundary,

43439

&locate->alignment_pad);

43440

locate->slot_offset = *initial_offset_ptr;

43441

@@ -5093,6 +5081,7 @@

43442

amount. BLKmode results are handled using the group load/store

43443

machinery. */

43444

if (TYPE_MODE (TREE_TYPE (decl_result)) != BLKmode

43445

+ && REG_P (real_decl_rtl)

43446

&& targetm.calls.return_in_msb (TREE_TYPE (decl_result)))

43447

{

43448

emit_move_insn (gen_rtx_REG (GET_MODE (decl_rtl),

43449

@@ -5509,22 +5498,45 @@

43450

except for any part that overlaps SRC (next loop). */

43451

bb_uses = &DF_LR_BB_INFO (bb)->use;

43452

bb_defs = &DF_LR_BB_INFO (bb)->def;

43453

- for (i = dregno; i < end_dregno; i++)

43454

+ if (df_live)

43455

{

43456

- if (REGNO_REG_SET_P (bb_uses, i) || REGNO_REG_SET_P (bb_defs, i))

43457

- next_block = NULL;

43458

- CLEAR_REGNO_REG_SET (live_out, i);

43459

- CLEAR_REGNO_REG_SET (live_in, i);

43460

+ for (i = dregno; i < end_dregno; i++)

43461

+ {

43462

+ if (REGNO_REG_SET_P (bb_uses, i) || REGNO_REG_SET_P (bb_defs, i)

43463

+ || REGNO_REG_SET_P (&DF_LIVE_BB_INFO (bb)->gen, i))

43464

+ next_block = NULL;

43465

+ CLEAR_REGNO_REG_SET (live_out, i);

43466

+ CLEAR_REGNO_REG_SET (live_in, i);

43467

+ }

43468

+

43469

+ /* Check whether BB clobbers SRC. We need to add INSN to BB if so.

43470

+ Either way, SRC is now live on entry. */

43471

+ for (i = sregno; i < end_sregno; i++)

43472

+ {

43473

+ if (REGNO_REG_SET_P (bb_defs, i)

43474

+ || REGNO_REG_SET_P (&DF_LIVE_BB_INFO (bb)->gen, i))

43475

+ next_block = NULL;

43476

+ SET_REGNO_REG_SET (live_out, i);

43477

+ SET_REGNO_REG_SET (live_in, i);

43478

+ }

43479

}

43480

+ else

43481

+ {

43482

+ /* DF_LR_BB_INFO (bb)->def does not comprise the DF_REF_PARTIAL and

43483

+ DF_REF_CONDITIONAL defs. So if DF_LIVE doesn't exist, i.e.

43484

+ at -O1, just give up searching NEXT_BLOCK. */

43485

+ next_block = NULL;

43486

+ for (i = dregno; i < end_dregno; i++)

43487

+ {

43488

+ CLEAR_REGNO_REG_SET (live_out, i);

43489

+ CLEAR_REGNO_REG_SET (live_in, i);

43490

+ }

43491

43492

- /* Check whether BB clobbers SRC. We need to add INSN to BB if so.

43493

- Either way, SRC is now live on entry. */

43494

- for (i = sregno; i < end_sregno; i++)

43495

- {

43496

- if (REGNO_REG_SET_P (bb_defs, i))

43497

- next_block = NULL;

43498

- SET_REGNO_REG_SET (live_out, i);

43499

- SET_REGNO_REG_SET (live_in, i);

43500

+ for (i = sregno; i < end_sregno; i++)

43501

+ {

43502

+ SET_REGNO_REG_SET (live_out, i);

43503

+ SET_REGNO_REG_SET (live_in, i);

43504

+ }

43505

}

43506

43507

/* If we don't need to add the move to BB, look for a single

43508

Index: gcc/print-rtl.c

43509

===================================================================

43510

--- a/src/gcc/print-rtl.c (.../tags/gcc_4_8_2_release)

43511

+++ b/src/gcc/print-rtl.c (.../branches/gcc-4_8-branch)

43512

@@ -582,6 +582,8 @@

43513

43514

if (MEM_EXPR (in_rtx))

43515

print_mem_expr (outfile, MEM_EXPR (in_rtx));

43516

+ else

43517

+ fputc (' ', outfile);

43518

43519

if (MEM_OFFSET_KNOWN_P (in_rtx))

43520

fprintf (outfile, "+" HOST_WIDE_INT_PRINT_DEC, MEM_OFFSET (in_rtx));

43521

Index: gcc/tree-vectorizer.h

43522

===================================================================

43523

--- a/src/gcc/tree-vectorizer.h (.../tags/gcc_4_8_2_release)

43524

+++ b/src/gcc/tree-vectorizer.h (.../branches/gcc-4_8-branch)

43525

@@ -542,6 +542,10 @@

43526

is 1. */

43527

unsigned int gap;

43528

43529

+ /* The minimum negative dependence distance this stmt participates in

43530

+ or zero if none. */

43531

+ unsigned int min_neg_dist;

43532

+

43533

/* Not all stmts in the loop need to be vectorized. e.g, the increment

43534

of the loop induction variable and computation of array indexes. relevant

43535

indicates whether the stmt needs to be vectorized. */

43536

@@ -593,6 +597,7 @@

43537

#define STMT_VINFO_GROUP_READ_WRITE_DEPENDENCE(S) (S)->read_write_dep

43538

#define STMT_VINFO_GROUPED_ACCESS(S) ((S)->first_element != NULL && (S)->data_ref_info)

43539

#define STMT_VINFO_LOOP_PHI_EVOLUTION_PART(S) (S)->loop_phi_evolution_part

43540

+#define STMT_VINFO_MIN_NEG_DIST(S) (S)->min_neg_dist

43541

43542

#define GROUP_FIRST_ELEMENT(S) (S)->first_element

43543

#define GROUP_NEXT_ELEMENT(S) (S)->next_element

43544

Index: gcc/sdbout.c

43545

===================================================================

43546

--- a/src/gcc/sdbout.c (.../tags/gcc_4_8_2_release)

43547

+++ b/src/gcc/sdbout.c (.../branches/gcc-4_8-branch)

43548

@@ -1226,7 +1226,10 @@

43549

sdbout_parms (tree parms)

43550

{

43551

for (; parms; parms = TREE_CHAIN (parms))

43552

- if (DECL_NAME (parms))

43553

+ if (DECL_NAME (parms)

43554

+ && TREE_TYPE (parms) != error_mark_node

43555

+ && DECL_RTL_SET_P (parms)

43556

+ && DECL_INCOMING_RTL (parms))

43557

{

43558

int current_sym_value = 0;

43559

const char *name = IDENTIFIER_POINTER (DECL_NAME (parms));

43560

@@ -1358,7 +1361,10 @@

43561

sdbout_reg_parms (tree parms)

43562

{

43563

for (; parms; parms = TREE_CHAIN (parms))

43564

- if (DECL_NAME (parms))

43565

+ if (DECL_NAME (parms)

43566

+ && TREE_TYPE (parms) != error_mark_node

43567

+ && DECL_RTL_SET_P (parms)

43568

+ && DECL_INCOMING_RTL (parms))

43569

{

43570

const char *name = IDENTIFIER_POINTER (DECL_NAME (parms));

43571

43572

Index: gcc/ipa-split.c

43573

===================================================================

43574

--- a/src/gcc/ipa-split.c (.../tags/gcc_4_8_2_release)

43575

+++ b/src/gcc/ipa-split.c (.../branches/gcc-4_8-branch)

43576

@@ -136,7 +136,7 @@

43577

variable, check it if it is present in bitmap passed via DATA. */

43578

43579

static bool

43580

-test_nonssa_use (gimple stmt ATTRIBUTE_UNUSED, tree t, void *data)

43581

+test_nonssa_use (gimple, tree t, tree, void *data)

43582

{

43583

t = get_base_address (t);

43584

43585

@@ -229,7 +229,7 @@

43586

}

43587

if (gimple_code (stmt) == GIMPLE_LABEL

43588

&& test_nonssa_use (stmt, gimple_label_label (stmt),

43589

- non_ssa_vars))

43590

+ NULL_TREE, non_ssa_vars))

43591

{

43592

ok = false;

43593

goto done;

43594

@@ -258,7 +258,7 @@

43595

if (virtual_operand_p (gimple_phi_result (stmt)))

43596

continue;

43597

if (TREE_CODE (op) != SSA_NAME

43598

- && test_nonssa_use (stmt, op, non_ssa_vars))

43599

+ && test_nonssa_use (stmt, op, op, non_ssa_vars))

43600

{

43601

ok = false;

43602

goto done;

43603

@@ -670,7 +670,7 @@

43604

Return true when access to T prevents splitting the function. */

43605

43606

static bool

43607

-mark_nonssa_use (gimple stmt ATTRIBUTE_UNUSED, tree t, void *data)

43608

+mark_nonssa_use (gimple, tree t, tree, void *data)

43609

{

43610

t = get_base_address (t);

43611

43612

@@ -830,7 +830,7 @@

43613

if (TREE_CODE (op) == SSA_NAME)

43614

bitmap_set_bit (used_ssa_names, SSA_NAME_VERSION (op));

43615

else

43616

- can_split &= !mark_nonssa_use (stmt, op, non_ssa_vars);

43617

+ can_split &= !mark_nonssa_use (stmt, op, op, non_ssa_vars);

43618

}

43619

}

43620

return can_split;

43621

Index: gcc/alias.c

43622

===================================================================

43623

--- a/src/gcc/alias.c (.../tags/gcc_4_8_2_release)

43624

+++ b/src/gcc/alias.c (.../branches/gcc-4_8-branch)

43625

@@ -156,7 +156,9 @@

43626

static alias_set_entry get_alias_set_entry (alias_set_type);

43627

static bool nonoverlapping_component_refs_p (const_rtx, const_rtx);

43628

static tree decl_for_component_ref (tree);

43629

-static int write_dependence_p (const_rtx, const_rtx, int);

43630

+static int write_dependence_p (const_rtx,

43631

+ const_rtx, enum machine_mode, rtx,

43632

+ bool, bool, bool);

43633

43634

static void memory_modified_1 (rtx, const_rtx, void *);

43635

43636

@@ -2558,15 +2560,24 @@

43637

}

43638

43639

/* Returns nonzero if a write to X might alias a previous read from

43640

- (or, if WRITEP is nonzero, a write to) MEM. */

43641

+ (or, if WRITEP is true, a write to) MEM.

43642

+ If X_CANONCALIZED is true, then X_ADDR is the canonicalized address of X,

43643

+ and X_MODE the mode for that access.

43644

+ If MEM_CANONICALIZED is true, MEM is canonicalized. */

43645

43646

static int

43647

-write_dependence_p (const_rtx mem, const_rtx x, int writep)

43648

+write_dependence_p (const_rtx mem,

43649

+ const_rtx x, enum machine_mode x_mode, rtx x_addr,

43650

+ bool mem_canonicalized, bool x_canonicalized, bool writep)

43651

{

43652

- rtx x_addr, mem_addr;

43653

+ rtx mem_addr;

43654

rtx base;

43655

int ret;

43656

43657

+ gcc_checking_assert (x_canonicalized

43658

+ ? (x_addr != NULL_RTX && x_mode != VOIDmode)

43659

+ : (x_addr == NULL_RTX && x_mode == VOIDmode));

43660

+

43661

if (MEM_VOLATILE_P (x) && MEM_VOLATILE_P (mem))

43662

return 1;

43663

43664

@@ -2590,17 +2601,21 @@

43665

if (MEM_ADDR_SPACE (mem) != MEM_ADDR_SPACE (x))

43666

return 1;

43667

43668

- x_addr = XEXP (x, 0);

43669

mem_addr = XEXP (mem, 0);

43670

- if (!((GET_CODE (x_addr) == VALUE

43671

- && GET_CODE (mem_addr) != VALUE

43672

- && reg_mentioned_p (x_addr, mem_addr))

43673

- || (GET_CODE (x_addr) != VALUE

43674

- && GET_CODE (mem_addr) == VALUE

43675

- && reg_mentioned_p (mem_addr, x_addr))))

43676

+ if (!x_addr)

43677

{

43678

- x_addr = get_addr (x_addr);

43679

- mem_addr = get_addr (mem_addr);

43680

+ x_addr = XEXP (x, 0);

43681

+ if (!((GET_CODE (x_addr) == VALUE

43682

+ && GET_CODE (mem_addr) != VALUE

43683

+ && reg_mentioned_p (x_addr, mem_addr))

43684

+ || (GET_CODE (x_addr) != VALUE

43685

+ && GET_CODE (mem_addr) == VALUE

43686

+ && reg_mentioned_p (mem_addr, x_addr))))

43687

+ {

43688

+ x_addr = get_addr (x_addr);

43689

+ if (!mem_canonicalized)

43690

+ mem_addr = get_addr (mem_addr);

43691

+ }

43692

}

43693

43694

if (! writep)

43695

@@ -2616,11 +2631,16 @@

43696

GET_MODE (mem)))

43697

return 0;

43698

43699

- x_addr = canon_rtx (x_addr);

43700

- mem_addr = canon_rtx (mem_addr);

43701

+ if (!x_canonicalized)

43702

+ {

43703

+ x_addr = canon_rtx (x_addr);

43704

+ x_mode = GET_MODE (x);

43705

+ }

43706

+ if (!mem_canonicalized)

43707

+ mem_addr = canon_rtx (mem_addr);

43708

43709

if ((ret = memrefs_conflict_p (SIZE_FOR_MODE (mem), mem_addr,

43710

- SIZE_FOR_MODE (x), x_addr, 0)) != -1)

43711

+ GET_MODE_SIZE (x_mode), x_addr, 0)) != -1)

43712

return ret;

43713

43714

if (nonoverlapping_memrefs_p (x, mem, false))

43715

@@ -2634,15 +2654,33 @@

43716

int

43717

anti_dependence (const_rtx mem, const_rtx x)

43718

{

43719

- return write_dependence_p (mem, x, /*writep=*/0);

43720

+ return write_dependence_p (mem, x, VOIDmode, NULL_RTX,

43721

+ /*mem_canonicalized=*/false,

43722

+ /*x_canonicalized*/false, /*writep=*/false);

43723

}

43724

43725

+/* Likewise, but we already have a canonicalized MEM, and X_ADDR for X.

43726

+ Also, consider X in X_MODE (which might be from an enclosing

43727

+ STRICT_LOW_PART / ZERO_EXTRACT).

43728

+ If MEM_CANONICALIZED is true, MEM is canonicalized. */

43729

+

43730

+int

43731

+canon_anti_dependence (const_rtx mem, bool mem_canonicalized,

43732

+ const_rtx x, enum machine_mode x_mode, rtx x_addr)

43733

+{

43734

+ return write_dependence_p (mem, x, x_mode, x_addr,

43735

+ mem_canonicalized, /*x_canonicalized=*/true,

43736

+ /*writep=*/false);

43737

+}

43738

+

43739

/* Output dependence: X is written after store in MEM takes place. */

43740

43741

int

43742

output_dependence (const_rtx mem, const_rtx x)

43743

{

43744

- return write_dependence_p (mem, x, /*writep=*/1);

43745

+ return write_dependence_p (mem, x, VOIDmode, NULL_RTX,

43746

+ /*mem_canonicalized=*/false,

43747

+ /*x_canonicalized*/false, /*writep=*/true);

43748

}

43749

43750

43751

@@ -2871,17 +2909,14 @@

43752

/* Wipe the reg_seen array clean. */

43753

bitmap_clear (reg_seen);

43754

43755

- /* Mark all hard registers which may contain an address.

43756

- The stack, frame and argument pointers may contain an address.

43757

- An argument register which can hold a Pmode value may contain

43758

- an address even if it is not in BASE_REGS.

43759

+ /* Initialize the alias information for this pass. */

43760

+ for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)

43761

+ if (static_reg_base_value[i])

43762

+ {

43763

+ new_reg_base_value[i] = static_reg_base_value[i];

43764

+ bitmap_set_bit (reg_seen, i);

43765

+ }

43766

43767

- The address expression is VOIDmode for an argument and

43768

- Pmode for other registers. */

43769

-

43770

- memcpy (new_reg_base_value, static_reg_base_value,

43771

- FIRST_PSEUDO_REGISTER * sizeof (rtx));

43772

-

43773

/* Walk the insns adding values to the new_reg_base_value array. */

43774

for (i = 0; i < rpo_cnt; i++)

43775

{

43776

Index: gcc/tree-vect-loop.c

43777

===================================================================

43778

--- a/src/gcc/tree-vect-loop.c (.../tags/gcc_4_8_2_release)

43779

+++ b/src/gcc/tree-vect-loop.c (.../branches/gcc-4_8-branch)

43780

@@ -1537,7 +1537,7 @@

43781

43782

if (!LOOP_VINFO_NITERS_KNOWN_P (loop_vinfo)

43783

|| LOOP_VINFO_INT_NITERS (loop_vinfo) % vectorization_factor != 0

43784

- || LOOP_PEELING_FOR_ALIGNMENT (loop_vinfo))

43785

+ || LOOP_VINFO_PEELING_FOR_GAPS (loop_vinfo))

43786

{

43787

if (dump_enabled_p ())

43788

dump_printf_loc (MSG_NOTE, vect_location, "epilog loop required.");

43789

@@ -2097,6 +2097,12 @@

43790

|| (!check_reduction && flow_loop_nested_p (vect_loop, loop)));

43791

43792

name = PHI_RESULT (phi);

43793

+ /* ??? If there are no uses of the PHI result the inner loop reduction

43794

+ won't be detected as possibly double-reduction by vectorizable_reduction

43795

+ because that tries to walk the PHI arg from the preheader edge which

43796

+ can be constant. See PR60382. */

43797

+ if (has_zero_uses (name))

43798

+ return NULL;

43799

nloop_uses = 0;

43800

FOR_EACH_IMM_USE_FAST (use_p, imm_iter, name)

43801

{

43802

@@ -3115,7 +3121,6 @@

43803

stmt_vec_info stmt_vinfo = vinfo_for_stmt (iv_phi);

43804

loop_vec_info loop_vinfo = STMT_VINFO_LOOP_VINFO (stmt_vinfo);

43805

struct loop *loop = LOOP_VINFO_LOOP (loop_vinfo);

43806

- tree scalar_type;

43807

tree vectype;

43808

int nunits;

43809

edge pe = loop_preheader_edge (loop);

43810

@@ -3122,7 +3127,6 @@

43811

struct loop *iv_loop;

43812

basic_block new_bb;

43813

tree new_vec, vec_init, vec_step, t;

43814

- tree access_fn;

43815

tree new_var;

43816

tree new_name;

43817

gimple init_stmt, induction_phi, new_stmt;

43818

@@ -3130,7 +3134,6 @@

43819

tree init_expr, step_expr;

43820

int vf = LOOP_VINFO_VECT_FACTOR (loop_vinfo);

43821

int i;

43822

- bool ok;

43823

int ncopies;

43824

tree expr;

43825

stmt_vec_info phi_info = vinfo_for_stmt (iv_phi);

43826

@@ -3159,16 +3162,14 @@

43827

latch_e = loop_latch_edge (iv_loop);

43828

loop_arg = PHI_ARG_DEF_FROM_EDGE (iv_phi, latch_e);

43829

43830

- access_fn = analyze_scalar_evolution (iv_loop, PHI_RESULT (iv_phi));

43831

- gcc_assert (access_fn);

43832

- STRIP_NOPS (access_fn);

43833

- ok = vect_is_simple_iv_evolution (iv_loop->num, access_fn,

43834

- &init_expr, &step_expr);

43835

- gcc_assert (ok);

43836

+ step_expr = STMT_VINFO_LOOP_PHI_EVOLUTION_PART (phi_info);

43837

+ gcc_assert (step_expr != NULL_TREE);

43838

+

43839

pe = loop_preheader_edge (iv_loop);

43840

+ init_expr = PHI_ARG_DEF_FROM_EDGE (iv_phi,

43841

+ loop_preheader_edge (iv_loop));

43842

43843

- scalar_type = TREE_TYPE (init_expr);

43844

- vectype = get_vectype_for_scalar_type (scalar_type);

43845

+ vectype = get_vectype_for_scalar_type (TREE_TYPE (init_expr));

43846

resvectype = get_vectype_for_scalar_type (TREE_TYPE (PHI_RESULT (iv_phi)));

43847

gcc_assert (vectype);

43848

nunits = TYPE_VECTOR_SUBPARTS (vectype);

43849

@@ -3177,6 +3178,16 @@

43850

gcc_assert (phi_info);

43851

gcc_assert (ncopies >= 1);

43852

43853

+ /* Convert the step to the desired type. */

43854

+ step_expr = force_gimple_operand (fold_convert (TREE_TYPE (vectype),

43855

+ step_expr),

43856

+ &stmts, true, NULL_TREE);

43857

+ if (stmts)

43858

+ {

43859

+ new_bb = gsi_insert_seq_on_edge_immediate (pe, stmts);

43860

+ gcc_assert (!new_bb);

43861

+ }

43862

+

43863

/* Find the first insertion point in the BB. */

43864

si = gsi_after_labels (bb);

43865

43866

@@ -3186,9 +3197,7 @@

43867

/* iv_loop is nested in the loop to be vectorized. init_expr had already

43868

been created during vectorization of previous stmts. We obtain it

43869

from the STMT_VINFO_VEC_STMT of the defining stmt. */

43870

- tree iv_def = PHI_ARG_DEF_FROM_EDGE (iv_phi,

43871

- loop_preheader_edge (iv_loop));

43872

- vec_init = vect_get_vec_def_for_operand (iv_def, iv_phi, NULL);

43873

+ vec_init = vect_get_vec_def_for_operand (init_expr, iv_phi, NULL);

43874

/* If the initial value is not of proper type, convert it. */

43875

if (!useless_type_conversion_p (vectype, TREE_TYPE (vec_init)))

43876

{

43877

@@ -3211,8 +3220,11 @@

43878

43879

/* iv_loop is the loop to be vectorized. Create:

43880

vec_init = [X, X+S, X+2*S, X+3*S] (S = step_expr, X = init_expr) */

43881

- new_var = vect_get_new_vect_var (scalar_type, vect_scalar_var, "var_");

43882

- new_name = force_gimple_operand (init_expr, &stmts, false, new_var);

43883

+ new_var = vect_get_new_vect_var (TREE_TYPE (vectype),

43884

+ vect_scalar_var, "var_");

43885

+ new_name = force_gimple_operand (fold_convert (TREE_TYPE (vectype),

43886

+ init_expr),

43887

+ &stmts, false, new_var);

43888

if (stmts)

43889

{

43890

new_bb = gsi_insert_seq_on_edge_immediate (pe, stmts);

43891

@@ -3224,9 +3236,7 @@

43892

for (i = 1; i < nunits; i++)

43893

{

43894

/* Create: new_name_i = new_name + step_expr */

43895

- enum tree_code code = POINTER_TYPE_P (scalar_type)

43896

- ? POINTER_PLUS_EXPR : PLUS_EXPR;

43897

- init_stmt = gimple_build_assign_with_ops (code, new_var,

43898

+ init_stmt = gimple_build_assign_with_ops (PLUS_EXPR, new_var,

43899

new_name, step_expr);

43900

new_name = make_ssa_name (new_var, init_stmt);

43901

gimple_assign_set_lhs (init_stmt, new_name);

43902

@@ -3781,8 +3791,12 @@

43903

/* Set phi nodes arguments. */

43904

FOR_EACH_VEC_ELT (reduction_phis, i, phi)

43905

{

43906

- tree vec_init_def = vec_initial_defs[i];

43907

- tree def = vect_defs[i];

43908

+ tree vec_init_def, def;

43909

+ gimple_seq stmts;

43910

+ vec_init_def = force_gimple_operand (vec_initial_defs[i], &stmts,

43911

+ true, NULL_TREE);

43912

+ gsi_insert_seq_on_edge_immediate (loop_preheader_edge (loop), stmts);

43913

+ def = vect_defs[i];

43914

for (j = 0; j < ncopies; j++)

43915

{

43916

/* Set the loop-entry arg of the reduction-phi. */

43917

@@ -5564,8 +5578,9 @@

43918

&& !STMT_VINFO_LIVE_P (stmt_info))

43919

continue;

43920

43921

- if ((TYPE_VECTOR_SUBPARTS (STMT_VINFO_VECTYPE (stmt_info))

43922

- != (unsigned HOST_WIDE_INT) vectorization_factor)

43923

+ if (STMT_VINFO_VECTYPE (stmt_info)

43924

+ && (TYPE_VECTOR_SUBPARTS (STMT_VINFO_VECTYPE (stmt_info))

43925

+ != (unsigned HOST_WIDE_INT) vectorization_factor)

43926

&& dump_enabled_p ())

43927

dump_printf_loc (MSG_NOTE, vect_location, "multiple-types.");

43928

43929

Index: gcc/ipa.c

43930

===================================================================

43931

--- a/src/gcc/ipa.c (.../tags/gcc_4_8_2_release)

43932

+++ b/src/gcc/ipa.c (.../branches/gcc-4_8-branch)

43933

@@ -359,6 +359,8 @@

43934

{

43935

if (file)

43936

fprintf (file, " %s", cgraph_node_name (node));

43937

+ node->alias = false;

43938

+ node->thunk.thunk_p = false;

43939

cgraph_node_remove_callees (node);

43940

ipa_remove_all_references (&node->symbol.ref_list);

43941

changed = true;

43942

Index: gcc/lra-coalesce.c

43943

===================================================================

43944

--- a/src/gcc/lra-coalesce.c (.../tags/gcc_4_8_2_release)

43945

+++ b/src/gcc/lra-coalesce.c (.../branches/gcc-4_8-branch)

43946

@@ -221,9 +221,12 @@

43947

basic_block bb;

43948

rtx mv, set, insn, next, *sorted_moves;

43949

int i, mv_num, sregno, dregno;

43950

+ unsigned int regno;

43951

int coalesced_moves;

43952

int max_regno = max_reg_num ();

43953

bitmap_head involved_insns_bitmap;

43954

+ bitmap_head result_pseudo_vals_bitmap;

43955

+ bitmap_iterator bi;

43956

43957

timevar_push (TV_LRA_COALESCE);

43958

43959

@@ -318,6 +321,34 @@

43960

}

43961

}

43962

}

43963

+ /* If we have situation after inheritance pass:

43964

+

43965

+ r1 <- ... insn originally setting p1

43966

+ i1 <- r1 setting inheritance i1 from reload r1

43967

+ ...

43968

+ ... <- ... p2 ... dead p2

43969

+ ..

43970

+ p1 <- i1

43971

+ r2 <- i1

43972

+ ...<- ... r2 ...

43973

+

43974

+ And we are coalescing p1 and p2 using p1. In this case i1 and p1

43975

+ should have different values, otherwise they can get the same

43976

+ hard reg and this is wrong for insn using p2 before coalescing.

43977

+ So invalidate such inheritance pseudo values. */

43978

+ bitmap_initialize (&result_pseudo_vals_bitmap, &reg_obstack);

43979

+ EXECUTE_IF_SET_IN_BITMAP (&coalesced_pseudos_bitmap, 0, regno, bi)

43980

+ bitmap_set_bit (&result_pseudo_vals_bitmap,

43981

+ lra_reg_info[first_coalesced_pseudo[regno]].val);

43982

+ EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi)

43983

+ if (bitmap_bit_p (&result_pseudo_vals_bitmap, lra_reg_info[regno].val))

43984

+ {

43985

+ lra_set_regno_unique_value (regno);

43986

+ if (lra_dump_file != NULL)

43987

+ fprintf (lra_dump_file,

43988

+ " Make unique value for inheritance r%d\n", regno);

43989

+ }

43990

+ bitmap_clear (&result_pseudo_vals_bitmap);

43991

bitmap_clear (&used_pseudos_bitmap);

43992

bitmap_clear (&involved_insns_bitmap);

43993

bitmap_clear (&coalesced_pseudos_bitmap);

43994

Index: gcc/tree-vect-data-refs.c

43995

===================================================================

43996

--- a/src/gcc/tree-vect-data-refs.c (.../tags/gcc_4_8_2_release)

43997

+++ b/src/gcc/tree-vect-data-refs.c (.../branches/gcc-4_8-branch)

43998

@@ -739,6 +739,13 @@

43999

if (dump_enabled_p ())

44000

dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location,

44001

"dependence distance negative.");

44002

+ /* Record a negative dependence distance to later limit the

44003

+ amount of stmt copying / unrolling we can perform.

44004

+ Only need to handle read-after-write dependence. */

44005

+ if (DR_IS_READ (drb)

44006

+ && (STMT_VINFO_MIN_NEG_DIST (stmtinfo_b) == 0

44007

+ || STMT_VINFO_MIN_NEG_DIST (stmtinfo_b) > (unsigned)dist))

44008

+ STMT_VINFO_MIN_NEG_DIST (stmtinfo_b) = dist;

44009

continue;

44010

}

44011

44012

Index: gcc/gimplify.c

44013

===================================================================

44014

--- a/src/gcc/gimplify.c (.../tags/gcc_4_8_2_release)

44015

+++ b/src/gcc/gimplify.c (.../branches/gcc-4_8-branch)

44016

@@ -2060,6 +2060,9 @@

44017

/* Nonlocal VLAs seen in the current function. */

44018

static struct pointer_set_t *nonlocal_vlas;

44019

44020

+/* The VAR_DECLs created for nonlocal VLAs for debug info purposes. */

44021

+static tree nonlocal_vla_vars;

44022

+

44023

/* Gimplify a VAR_DECL or PARM_DECL. Return GS_OK if we expanded a

44024

DECL_VALUE_EXPR, and it's worth re-examining things. */

44025

44026

@@ -2106,14 +2109,13 @@

44027

ctx = ctx->outer_context;

44028

if (!ctx && !pointer_set_insert (nonlocal_vlas, decl))

44029

{

44030

- tree copy = copy_node (decl), block;

44031

+ tree copy = copy_node (decl);

44032

44033

lang_hooks.dup_lang_specific_decl (copy);

44034

SET_DECL_RTL (copy, 0);

44035

TREE_USED (copy) = 1;

44036

- block = DECL_INITIAL (current_function_decl);

44037

- DECL_CHAIN (copy) = BLOCK_VARS (block);

44038

- BLOCK_VARS (block) = copy;

44039

+ DECL_CHAIN (copy) = nonlocal_vla_vars;

44040

+ nonlocal_vla_vars = copy;

44041

SET_DECL_VALUE_EXPR (copy, unshare_expr (value_expr));

44042

DECL_HAS_VALUE_EXPR_P (copy) = 1;

44043

}

44044

@@ -4369,7 +4371,7 @@

44045

unsigned HOST_WIDE_INT indexi = offset * BITS_PER_UNIT;

44046

tree index = bitsize_int (indexi);

44047

if (offset / part_widthi

44048

- <= TYPE_VECTOR_SUBPARTS (TREE_TYPE (addrtype)))

44049

+ < TYPE_VECTOR_SUBPARTS (TREE_TYPE (addrtype)))

44050

return fold_build3 (BIT_FIELD_REF, type, TREE_OPERAND (addr, 0),

44051

part_width, index);

44052

}

44053

@@ -6131,7 +6133,7 @@

44054

region's REDUCTION clause. */

44055

44056

static bool

44057

-omp_check_private (struct gimplify_omp_ctx *ctx, tree decl)

44058

+omp_check_private (struct gimplify_omp_ctx *ctx, tree decl, bool copyprivate)

44059

{

44060

splay_tree_node n;

44061

44062

@@ -6140,8 +6142,11 @@

44063

ctx = ctx->outer_context;

44064

if (ctx == NULL)

44065

return !(is_global_var (decl)

44066

- /* References might be private, but might be shared too. */

44067

- || lang_hooks.decls.omp_privatize_by_reference (decl));

44068

+ /* References might be private, but might be shared too,

44069

+ when checking for copyprivate, assume they might be

44070

+ private, otherwise assume they might be shared. */

44071

+ || (!copyprivate

44072

+ && lang_hooks.decls.omp_privatize_by_reference (decl)));

44073

44074

n = splay_tree_lookup (ctx->variables, (splay_tree_key) decl);

44075

if (n != NULL)

44076

@@ -6267,12 +6272,36 @@

44077

remove = true;

44078

break;

44079

}

44080

+ if (OMP_CLAUSE_CODE (c) == OMP_CLAUSE_COPYPRIVATE

44081

+ && !remove

44082

+ && !omp_check_private (ctx, decl, true))

44083

+ {

44084

+ remove = true;

44085

+ if (is_global_var (decl))

44086

+ {

44087

+ if (DECL_THREAD_LOCAL_P (decl))

44088

+ remove = false;

44089

+ else if (DECL_HAS_VALUE_EXPR_P (decl))

44090

+ {

44091

+ tree value = get_base_address (DECL_VALUE_EXPR (decl));

44092

+

44093

+ if (value

44094

+ && DECL_P (value)

44095

+ && DECL_THREAD_LOCAL_P (value))

44096

+ remove = false;

44097

+ }

44098

+ }

44099

+ if (remove)

44100

+ error_at (OMP_CLAUSE_LOCATION (c),

44101

+ "copyprivate variable %qE is not threadprivate"

44102

+ " or private in outer context", DECL_NAME (decl));

44103

+ }

44104

do_notice:

44105

if (outer_ctx)

44106

omp_notice_variable (outer_ctx, decl, true);

44107

if (check_non_private

44108

&& region_type == ORT_WORKSHARE

44109

- && omp_check_private (ctx, decl))

44110

+ && omp_check_private (ctx, decl, false))

44111

{

44112

error ("%s variable %qE is private in outer context",

44113

check_non_private, DECL_NAME (decl));

44114

@@ -8261,6 +8290,21 @@

44115

44116

if (nonlocal_vlas)

44117

{

44118

+ if (nonlocal_vla_vars)

44119

+ {

44120

+ /* tree-nested.c may later on call declare_vars (..., true);

44121

+ which relies on BLOCK_VARS chain to be the tail of the

44122

+ gimple_bind_vars chain. Ensure we don't violate that

44123

+ assumption. */

44124

+ if (gimple_bind_block (outer_bind)

44125

+ == DECL_INITIAL (current_function_decl))

44126

+ declare_vars (nonlocal_vla_vars, outer_bind, true);

44127

+ else

44128

+ BLOCK_VARS (DECL_INITIAL (current_function_decl))

44129

+ = chainon (BLOCK_VARS (DECL_INITIAL (current_function_decl)),

44130

+ nonlocal_vla_vars);

44131

+ nonlocal_vla_vars = NULL_TREE;

44132

+ }

44133

pointer_set_destroy (nonlocal_vlas);

44134

nonlocal_vlas = NULL;

44135

}

44136

@@ -8588,6 +8632,8 @@

44137

gsi_insert_after (gsi_p, post_stmt, GSI_NEW_STMT);

44138

44139

pop_gimplify_context (NULL);

44140

+

44141

+ update_stmt (stmt);

44142

}

44143

44144

/* Expand EXPR to list of gimple statements STMTS. GIMPLE_TEST_F specifies

44145

Index: gcc/graphite-scop-detection.c

44146

===================================================================

44147

--- a/src/gcc/graphite-scop-detection.c (.../tags/gcc_4_8_2_release)

44148

+++ b/src/gcc/graphite-scop-detection.c (.../branches/gcc-4_8-branch)

44149

@@ -203,7 +203,14 @@

44150

44151

switch (TREE_CODE (scev))

44152

{

44153

+ case NEGATE_EXPR:

44154

+ case BIT_NOT_EXPR:

44155

+ CASE_CONVERT:

44156

+ case NON_LVALUE_EXPR:

44157

+ return graphite_can_represent_scev (TREE_OPERAND (scev, 0));

44158

+

44159

case PLUS_EXPR:

44160

+ case POINTER_PLUS_EXPR:

44161

case MINUS_EXPR:

44162

return graphite_can_represent_scev (TREE_OPERAND (scev, 0))

44163

&& graphite_can_represent_scev (TREE_OPERAND (scev, 1));

44164

@@ -225,6 +232,7 @@

44165

if (!evolution_function_right_is_integer_cst (scev)

44166

|| !graphite_can_represent_init (scev))

44167

return false;

44168

+ return graphite_can_represent_scev (CHREC_LEFT (scev));

44169

44170

default:

44171

break;

44172

@@ -231,7 +239,8 @@

44173

}

44174

44175

/* Only affine functions can be represented. */

44176

- if (!scev_is_linear_expression (scev))

44177

+ if (tree_contains_chrecs (scev, NULL)

44178

+ || !scev_is_linear_expression (scev))

44179

return false;

44180

44181

return true;

44182

@@ -330,13 +339,10 @@

44183

44184

case GIMPLE_COND:

44185

{

44186

- tree op;

44187

- ssa_op_iter op_iter;

44188

- enum tree_code code = gimple_cond_code (stmt);

44189

-

44190

/* We can handle all binary comparisons. Inequalities are

44191

also supported as they can be represented with union of

44192

polyhedra. */

44193

+ enum tree_code code = gimple_cond_code (stmt);

44194

if (!(code == LT_EXPR

44195

|| code == GT_EXPR

44196

|| code == LE_EXPR

44197

@@ -345,11 +351,14 @@

44198

|| code == NE_EXPR))

44199

return false;

44200

44201

- FOR_EACH_SSA_TREE_OPERAND (op, stmt, op_iter, SSA_OP_ALL_USES)

44202

- if (!graphite_can_represent_expr (scop_entry, loop, op)

44203

- /* We can not handle REAL_TYPE. Failed for pr39260. */

44204

- || TREE_CODE (TREE_TYPE (op)) == REAL_TYPE)

44205

- return false;

44206

+ for (unsigned i = 0; i < 2; ++i)

44207

+ {

44208

+ tree op = gimple_op (stmt, i);

44209

+ if (!graphite_can_represent_expr (scop_entry, loop, op)

44210

+ /* We can not handle REAL_TYPE. Failed for pr39260. */

44211

+ || TREE_CODE (TREE_TYPE (op)) == REAL_TYPE)

44212

+ return false;

44213

+ }

44214

44215

return true;

44216

}

44217

Index: gcc/lra-constraints.c

44218

===================================================================

44219

--- a/src/gcc/lra-constraints.c (.../tags/gcc_4_8_2_release)

44220

+++ b/src/gcc/lra-constraints.c (.../branches/gcc-4_8-branch)

44221

@@ -1156,6 +1156,8 @@

44222

enum machine_mode mode;

44223

rtx reg, new_reg;

44224

rtx operand = *curr_id->operand_loc[nop];

44225

+ enum reg_class regclass;

44226

+ enum op_type type;

44227

44228

before = after = NULL_RTX;

44229

44230

@@ -1164,6 +1166,7 @@

44231

44232

mode = GET_MODE (operand);

44233

reg = SUBREG_REG (operand);

44234

+ type = curr_static_id->operand[nop].type;

44235

/* If we change address for paradoxical subreg of memory, the

44236

address might violate the necessary alignment or the access might

44237

be slow. So take this into consideration. We should not worry

44238

@@ -1236,6 +1239,55 @@

44239

"Inserting subreg reload");

44240

return true;

44241

}

44242

+ /* Force a reload for a paradoxical subreg. For paradoxical subreg,

44243

+ IRA allocates hardreg to the inner pseudo reg according to its mode

44244

+ instead of the outermode, so the size of the hardreg may not be enough

44245

+ to contain the outermode operand, in that case we may need to insert

44246

+ reload for the reg. For the following two types of paradoxical subreg,

44247

+ we need to insert reload:

44248

+ 1. If the op_type is OP_IN, and the hardreg could not be paired with

44249

+ other hardreg to contain the outermode operand

44250

+ (checked by in_hard_reg_set_p), we need to insert the reload.

44251

+ 2. If the op_type is OP_OUT or OP_INOUT. */

44252

+ else if (REG_P (reg)

44253

+ && REGNO (reg) >= FIRST_PSEUDO_REGISTER

44254

+ && (hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0

44255

+ && (hard_regno_nregs[hard_regno][GET_MODE (reg)]

44256

+ < hard_regno_nregs[hard_regno][mode])

44257

+ && (regclass = lra_get_allocno_class (REGNO (reg)))

44258

+ && (type != OP_IN

44259

+ || !in_hard_reg_set_p (reg_class_contents[regclass],

44260

+ mode, hard_regno)))

44261

+ {

44262

+ /* The class will be defined later in curr_insn_transform. */

44263

+ enum reg_class rclass

44264

+ = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS);

44265

+ rtx subreg;

44266

+

44267

+ new_reg = lra_create_new_reg_with_unique_value (mode, reg, rclass,

44268

+ "paradoxical subreg");

44269

+ PUT_MODE (new_reg, mode);

44270

+ subreg = simplify_gen_subreg (GET_MODE (reg), new_reg, mode, 0);

44271

+ if (type != OP_OUT)

44272

+ {

44273

+ push_to_sequence (before);

44274

+ lra_emit_move (subreg, reg);

44275

+ before = get_insns ();

44276

+ end_sequence ();

44277

+ }

44278

+ if (type != OP_IN)

44279

+ {

44280

+ start_sequence ();

44281

+ lra_emit_move (reg, subreg);

44282

+ emit_insn (after);

44283

+ after = get_insns ();

44284

+ end_sequence ();

44285

+ }

44286

+ SUBREG_REG (operand) = new_reg;

44287

+ lra_process_new_insns (curr_insn, before, after,

44288

+ "Inserting paradoxical subreg reload");

44289

+ return true;

44290

+ }

44291

return false;

44292

}

44293

44294

Index: gcc/calls.c

44295

===================================================================

44296

--- a/src/gcc/calls.c (.../tags/gcc_4_8_2_release)

44297

+++ b/src/gcc/calls.c (.../branches/gcc-4_8-branch)

44298

@@ -983,6 +983,7 @@

44299

44300

for (i = 0; i < num_actuals; i++)

44301

if (args[i].reg != 0 && ! args[i].pass_on_stack

44302

+ && GET_CODE (args[i].reg) != PARALLEL

44303

&& args[i].mode == BLKmode

44304

&& MEM_P (args[i].value)

44305

&& (MEM_ALIGN (args[i].value)

44306

@@ -1327,6 +1328,7 @@

44307

#else

44308

args[i].reg != 0,

44309

#endif

44310

+ reg_parm_stack_space,

44311

args[i].pass_on_stack ? 0 : args[i].partial,

44312

fndecl, args_size, &args[i].locate);

44313

#ifdef BLOCK_REG_PADDING

44314

@@ -3171,7 +3173,9 @@

44315

group load/store machinery below. */

44316

if (!structure_value_addr

44317

&& !pcc_struct_value

44318

+ && TYPE_MODE (rettype) != VOIDmode

44319

&& TYPE_MODE (rettype) != BLKmode

44320

+ && REG_P (valreg)

44321

&& targetm.calls.return_in_msb (rettype))

44322

{

44323

if (shift_return_value (TYPE_MODE (rettype), false, valreg))

44324

@@ -3734,7 +3738,8 @@

44325

#else

44326

argvec[count].reg != 0,

44327

#endif

44328

- 0, NULL_TREE, &args_size, &argvec[count].locate);

44329

+ reg_parm_stack_space, 0,

44330

+ NULL_TREE, &args_size, &argvec[count].locate);

44331

44332

if (argvec[count].reg == 0 || argvec[count].partial != 0

44333

|| reg_parm_stack_space > 0)

44334

@@ -3821,7 +3826,7 @@

44335

#else

44336

argvec[count].reg != 0,

44337

#endif

44338

- argvec[count].partial,

44339

+ reg_parm_stack_space, argvec[count].partial,

44340

NULL_TREE, &args_size, &argvec[count].locate);

44341

args_size.constant += argvec[count].locate.size.constant;

44342

gcc_assert (!argvec[count].locate.size.var);

44343

Index: gcc/tree-dfa.c

44344

===================================================================

44345

--- a/src/gcc/tree-dfa.c (.../tags/gcc_4_8_2_release)

44346

+++ b/src/gcc/tree-dfa.c (.../branches/gcc-4_8-branch)

44347

@@ -386,7 +386,6 @@

44348

double_int bit_offset = double_int_zero;

44349

HOST_WIDE_INT hbit_offset;

44350

bool seen_variable_array_ref = false;

44351

- tree base_type;

44352

44353

/* First get the final access size from just the outermost expression. */

44354

if (TREE_CODE (exp) == COMPONENT_REF)

44355

@@ -417,8 +416,6 @@

44356

and find the ultimate containing object. */

44357

while (1)

44358

{

44359

- base_type = TREE_TYPE (exp);

44360

-

44361

switch (TREE_CODE (exp))

44362

{

44363

case BIT_FIELD_REF:

44364

@@ -543,7 +540,38 @@

44365

case VIEW_CONVERT_EXPR:

44366

break;

44367

44368

+ case TARGET_MEM_REF:

44369

+ /* Via the variable index or index2 we can reach the

44370

+ whole object. Still hand back the decl here. */

44371

+ if (TREE_CODE (TMR_BASE (exp)) == ADDR_EXPR

44372

+ && (TMR_INDEX (exp) || TMR_INDEX2 (exp)))

44373

+ {

44374

+ exp = TREE_OPERAND (TMR_BASE (exp), 0);

44375

+ bit_offset = double_int_zero;

44376

+ maxsize = -1;

44377

+ goto done;

44378

+ }

44379

+ /* Fallthru. */

44380

case MEM_REF:

44381

+ /* We need to deal with variable arrays ending structures such as

44382

+ struct { int length; int a[1]; } x; x.a[d]

44383

+ struct { struct { int a; int b; } a[1]; } x; x.a[d].a

44384

+ struct { struct { int a[1]; } a[1]; } x; x.a[0][d], x.a[d][0]

44385

+ struct { int len; union { int a[1]; struct X x; } u; } x; x.u.a[d]

44386

+ where we do not know maxsize for variable index accesses to

44387

+ the array. The simplest way to conservatively deal with this

44388

+ is to punt in the case that offset + maxsize reaches the

44389

+ base type boundary. This needs to include possible trailing

44390

+ padding that is there for alignment purposes. */

44391

+ if (seen_variable_array_ref

44392

+ && maxsize != -1

44393

+ && (!bit_offset.fits_shwi ()

44394

+ || !host_integerp (TYPE_SIZE (TREE_TYPE (exp)), 1)

44395

+ || (bit_offset.to_shwi () + maxsize

44396

+ == (HOST_WIDE_INT) TREE_INT_CST_LOW

44397

+ (TYPE_SIZE (TREE_TYPE (exp))))))

44398

+ maxsize = -1;

44399

+

44400

/* Hand back the decl for MEM[&decl, off]. */

44401

if (TREE_CODE (TREE_OPERAND (exp, 0)) == ADDR_EXPR)

44402

{

44403

@@ -565,37 +593,6 @@

44404

}

44405

goto done;

44406

44407

- case TARGET_MEM_REF:

44408

- /* Hand back the decl for MEM[&decl, off]. */

44409

- if (TREE_CODE (TMR_BASE (exp)) == ADDR_EXPR)

44410

- {

44411

- /* Via the variable index or index2 we can reach the

44412

- whole object. */

44413

- if (TMR_INDEX (exp) || TMR_INDEX2 (exp))

44414

- {

44415

- exp = TREE_OPERAND (TMR_BASE (exp), 0);

44416

- bit_offset = double_int_zero;

44417

- maxsize = -1;

44418

- goto done;

44419

- }

44420

- if (integer_zerop (TMR_OFFSET (exp)))

44421

- exp = TREE_OPERAND (TMR_BASE (exp), 0);

44422

- else

44423

- {

44424

- double_int off = mem_ref_offset (exp);

44425

- off = off.alshift (BITS_PER_UNIT == 8

44426

- ? 3 : exact_log2 (BITS_PER_UNIT),

44427

- HOST_BITS_PER_DOUBLE_INT);

44428

- off += bit_offset;

44429

- if (off.fits_shwi ())

44430

- {

44431

- bit_offset = off;

44432

- exp = TREE_OPERAND (TMR_BASE (exp), 0);

44433

- }

44434

- }

44435

- }

44436

- goto done;

44437

-

44438

default:

44439

goto done;

44440

}

44441

@@ -602,8 +599,18 @@

44442

44443

exp = TREE_OPERAND (exp, 0);

44444

}

44445

+

44446

+ /* We need to deal with variable arrays ending structures. */

44447

+ if (seen_variable_array_ref

44448

+ && maxsize != -1

44449

+ && (!bit_offset.fits_shwi ()

44450

+ || !host_integerp (TYPE_SIZE (TREE_TYPE (exp)), 1)

44451

+ || (bit_offset.to_shwi () + maxsize

44452

+ == (HOST_WIDE_INT)

44453

+ TREE_INT_CST_LOW (TYPE_SIZE (TREE_TYPE (exp))))))

44454

+ maxsize = -1;

44455

+

44456

done:

44457

-

44458

if (!bit_offset.fits_shwi ())

44459

{

44460

*poffset = 0;

44461

@@ -615,24 +622,6 @@

44462

44463

hbit_offset = bit_offset.to_shwi ();

44464

44465

- /* We need to deal with variable arrays ending structures such as

44466

- struct { int length; int a[1]; } x; x.a[d]

44467

- struct { struct { int a; int b; } a[1]; } x; x.a[d].a

44468

- struct { struct { int a[1]; } a[1]; } x; x.a[0][d], x.a[d][0]

44469

- struct { int len; union { int a[1]; struct X x; } u; } x; x.u.a[d]

44470

- where we do not know maxsize for variable index accesses to

44471

- the array. The simplest way to conservatively deal with this

44472

- is to punt in the case that offset + maxsize reaches the

44473

- base type boundary. This needs to include possible trailing padding

44474

- that is there for alignment purposes. */

44475

-

44476

- if (seen_variable_array_ref

44477

- && maxsize != -1

44478

- && (!host_integerp (TYPE_SIZE (base_type), 1)

44479

- || (hbit_offset + maxsize

44480

- == (signed) TREE_INT_CST_LOW (TYPE_SIZE (base_type)))))

44481

- maxsize = -1;

44482

-

44483

/* In case of a decl or constant base object we can do better. */

44484

44485

if (DECL_P (exp))

44486

Index: gcc/gimple-fold.c

44487

===================================================================

44488

--- a/src/gcc/gimple-fold.c (.../tags/gcc_4_8_2_release)

44489

+++ b/src/gcc/gimple-fold.c (.../branches/gcc-4_8-branch)

44490

@@ -178,7 +178,7 @@

44491

/* Make sure we create a cgraph node for functions we'll reference.

44492

They can be non-existent if the reference comes from an entry

44493

of an external vtable for example. */

44494

- cgraph_get_create_node (base);

44495

+ cgraph_get_create_real_symbol_node (base);

44496

}

44497

/* Fixup types in global initializers. */

44498

if (TREE_TYPE (TREE_TYPE (cval)) != TREE_TYPE (TREE_OPERAND (cval, 0)))

44499

@@ -866,6 +866,7 @@

44500

break;

44501

case BUILT_IN_STRCPY:

44502

case BUILT_IN_STRNCPY:

44503

+ case BUILT_IN_STRCAT:

44504

arg_idx = 1;

44505

type = 0;

44506

break;

44507

@@ -941,6 +942,13 @@

44508

val[1]);

44509

break;

44510

44511

+ case BUILT_IN_STRCAT:

44512

+ if (val[1] && is_gimple_val (val[1]) && nargs == 2)

44513

+ result = fold_builtin_strcat (loc, gimple_call_arg (stmt, 0),

44514

+ gimple_call_arg (stmt, 1),

44515

+ val[1]);

44516

+ break;

44517

+

44518

case BUILT_IN_FPUTS:

44519

if (nargs == 2)

44520

result = fold_builtin_fputs (loc, gimple_call_arg (stmt, 0),

44521

Index: gcc/cfgexpand.c

44522

===================================================================

44523

--- a/src/gcc/cfgexpand.c (.../tags/gcc_4_8_2_release)

44524

+++ b/src/gcc/cfgexpand.c (.../branches/gcc-4_8-branch)

44525

@@ -331,7 +331,7 @@

44526

enter its partition number into bitmap DATA. */

44527

44528

static bool

44529

-visit_op (gimple stmt ATTRIBUTE_UNUSED, tree op, void *data)

44530

+visit_op (gimple, tree op, tree, void *data)

44531

{

44532

bitmap active = (bitmap)data;

44533

op = get_base_address (op);

44534

@@ -351,7 +351,7 @@

44535

from bitmap DATA. */

44536

44537

static bool

44538

-visit_conflict (gimple stmt ATTRIBUTE_UNUSED, tree op, void *data)

44539

+visit_conflict (gimple, tree op, tree, void *data)

44540

{

44541

bitmap active = (bitmap)data;

44542

op = get_base_address (op);

44543

@@ -385,7 +385,7 @@

44544

edge e;

44545

edge_iterator ei;

44546

gimple_stmt_iterator gsi;

44547

- bool (*visit)(gimple, tree, void *);

44548

+ walk_stmt_load_store_addr_fn visit;

44549

44550

bitmap_clear (work);

44551

FOR_EACH_EDGE (e, ei, bb->preds)

44552

@@ -4707,14 +4707,18 @@

44553

if (e->insns.r)

44554

{

44555

rebuild_jump_labels_chain (e->insns.r);

44556

- /* Avoid putting insns before parm_birth_insn. */

44557

+ /* Put insns after parm birth, but before

44558

+ NOTE_INSNS_FUNCTION_BEG. */

44559

if (e->src == ENTRY_BLOCK_PTR

44560

- && single_succ_p (ENTRY_BLOCK_PTR)

44561

- && parm_birth_insn)

44562

+ && single_succ_p (ENTRY_BLOCK_PTR))

44563

{

44564

rtx insns = e->insns.r;

44565

e->insns.r = NULL_RTX;

44566

- emit_insn_after_noloc (insns, parm_birth_insn, e->dest);

44567

+ if (NOTE_P (parm_birth_insn)

44568

+ && NOTE_KIND (parm_birth_insn) == NOTE_INSN_FUNCTION_BEG)

44569

+ emit_insn_before_noloc (insns, parm_birth_insn, e->dest);

44570

+ else

44571

+ emit_insn_after_noloc (insns, parm_birth_insn, e->dest);

44572

}

44573

else

44574

commit_one_edge_insertion (e);

44575

Index: gcc/cselib.c

44576

===================================================================

44577

--- a/src/gcc/cselib.c (.../tags/gcc_4_8_2_release)

44578

+++ b/src/gcc/cselib.c (.../branches/gcc-4_8-branch)

44579

@@ -2260,8 +2260,8 @@

44580

continue;

44581

}

44582

if (num_mems < PARAM_VALUE (PARAM_MAX_CSELIB_MEMORY_LOCATIONS)

44583

- && ! canon_true_dependence (mem_rtx, GET_MODE (mem_rtx),

44584

- mem_addr, x, NULL_RTX))

44585

+ && ! canon_anti_dependence (x, false, mem_rtx,

44586

+ GET_MODE (mem_rtx), mem_addr))

44587

{

44588

has_mem = true;

44589

num_mems++;

44590

Index: gcc/tree-cfgcleanup.c

44591

===================================================================

44592

--- a/src/gcc/tree-cfgcleanup.c (.../tags/gcc_4_8_2_release)

44593

+++ b/src/gcc/tree-cfgcleanup.c (.../branches/gcc-4_8-branch)

44594

@@ -539,9 +539,6 @@

44595

update_stmt (stmt);

44596

changed = true;

44597

}

44598

- /* Similarly remove VDEF if there is any. */

44599

- else if (gimple_vdef (stmt))

44600

- update_stmt (stmt);

44601

return changed;

44602

}

44603

44604

Index: gcc/tree-ssa-pre.c

44605

===================================================================

44606

--- a/src/gcc/tree-ssa-pre.c (.../tags/gcc_4_8_2_release)

44607

+++ b/src/gcc/tree-ssa-pre.c (.../branches/gcc-4_8-branch)

44608

@@ -3664,6 +3664,12 @@

44609

if (dump_file && dump_flags & TDF_DETAILS)

44610

fprintf (dump_file, "Starting insert iteration %d\n", num_iterations);

44611

new_stuff = insert_aux (ENTRY_BLOCK_PTR);

44612

+

44613

+ /* Clear the NEW sets before the next iteration. We have already

44614

+ fully propagated its contents. */

44615

+ if (new_stuff)

44616

+ FOR_ALL_BB (bb)

44617

+ bitmap_set_free (NEW_SETS (bb));

44618

}

44619

statistics_histogram_event (cfun, "insert iterations", num_iterations);

44620

}

44621

Index: gcc/cfgcleanup.c

44622

===================================================================

44623

--- a/src/gcc/cfgcleanup.c (.../tags/gcc_4_8_2_release)

44624

+++ b/src/gcc/cfgcleanup.c (.../branches/gcc-4_8-branch)

44625

@@ -1293,7 +1293,6 @@

44626

{

44627

rtx i1, i2, last1, last2, afterlast1, afterlast2;

44628

int ninsns = 0;

44629

- rtx p1;

44630

enum replace_direction dir, last_dir, afterlast_dir;

44631

bool follow_fallthru, did_fallthru;

44632

44633

@@ -1321,8 +1320,9 @@

44634

|| (returnjump_p (i2) && !side_effects_p (PATTERN (i2))))

44635

{

44636

last2 = i2;

44637

- /* Count everything except for unconditional jump as insn. */

44638

- if (!simplejump_p (i2) && !returnjump_p (i2) && last1)

44639

+ /* Count everything except for unconditional jump as insn.

44640

+ Don't count any jumps if dir_p is NULL. */

44641

+ if (!simplejump_p (i2) && !returnjump_p (i2) && last1 && dir_p)

44642

ninsns++;

44643

i2 = PREV_INSN (i2);

44644

}

44645

@@ -1373,8 +1373,8 @@

44646

last1 = i1, last2 = i2;

44647

afterlast_dir = last_dir;

44648

last_dir = dir;

44649

- p1 = PATTERN (i1);

44650

- if (!(GET_CODE (p1) == USE || GET_CODE (p1) == CLOBBER))

44651

+ if (GET_CODE (PATTERN (i1)) != USE

44652

+ && GET_CODE (PATTERN (i1)) != CLOBBER)

44653

ninsns++;

44654

}

44655

44656

@@ -1420,7 +1420,8 @@

44657

/* Like flow_find_cross_jump, except start looking for a matching sequence from

44658

the head of the two blocks. Do not include jumps at the end.

44659

If STOP_AFTER is nonzero, stop after finding that many matching

44660

- instructions. */

44661

+ instructions. If STOP_AFTER is zero, count all INSN_P insns, if it is

44662

+ non-zero, only count active insns. */

44663

44664

int

44665

flow_find_head_matching_sequence (basic_block bb1, basic_block bb2, rtx *f1,

44666

@@ -1492,7 +1493,10 @@

44667

44668

beforelast1 = last1, beforelast2 = last2;

44669

last1 = i1, last2 = i2;

44670

- ninsns++;

44671

+ if (!stop_after

44672

+ || (GET_CODE (PATTERN (i1)) != USE

44673

+ && GET_CODE (PATTERN (i1)) != CLOBBER))

44674

+ ninsns++;

44675

}

44676

44677

if (i1 == BB_END (bb1) || i2 == BB_END (bb2)

44678

Index: gcc/simplify-rtx.c

44679

===================================================================

44680

--- a/src/gcc/simplify-rtx.c (.../tags/gcc_4_8_2_release)

44681

+++ b/src/gcc/simplify-rtx.c (.../branches/gcc-4_8-branch)

44682

@@ -639,11 +639,16 @@

44683

XEXP (op, 0), origmode);

44684

}

44685

44686

- /* Simplify (truncate:SI (op:DI (x:DI) (y:DI)))

44687

- to (op:SI (truncate:SI (x:DI)) (truncate:SI (x:DI))). */

44688

- if (GET_CODE (op) == PLUS

44689

- || GET_CODE (op) == MINUS

44690

- || GET_CODE (op) == MULT)

44691

+ /* If the machine can perform operations in the truncated mode, distribute

44692

+ the truncation, i.e. simplify (truncate:QI (op:SI (x:SI) (y:SI))) into

44693

+ (op:QI (truncate:QI (x:SI)) (truncate:QI (y:SI))). */

44694

+ if (1

44695

+#ifdef WORD_REGISTER_OPERATIONS

44696

+ && precision >= BITS_PER_WORD

44697

+#endif

44698

+ && (GET_CODE (op) == PLUS

44699

+ || GET_CODE (op) == MINUS

44700

+ || GET_CODE (op) == MULT))

44701

{

44702

rtx op0 = simplify_gen_unary (TRUNCATE, mode, XEXP (op, 0), op_mode);

44703

if (op0)

44704

Index: gcc/tree-ssa-live.c

44705

===================================================================

44706

--- a/src/gcc/tree-ssa-live.c (.../tags/gcc_4_8_2_release)

44707

+++ b/src/gcc/tree-ssa-live.c (.../branches/gcc-4_8-branch)

44708

@@ -394,7 +394,8 @@

44709

{

44710

/* When a global var becomes used for the first time also walk its

44711

initializer (non global ones don't have any). */

44712

- if (set_is_used (t) && is_global_var (t))

44713

+ if (set_is_used (t) && is_global_var (t)

44714

+ && DECL_CONTEXT (t) == current_function_decl)

44715

mark_all_vars_used (&DECL_INITIAL (t));

44716

}

44717

/* remove_unused_scope_block_p requires information about labels

44718

Index: gcc/tree-sra.c

44719

===================================================================

44720

--- a/src/gcc/tree-sra.c (.../tags/gcc_4_8_2_release)

44721

+++ b/src/gcc/tree-sra.c (.../branches/gcc-4_8-branch)

44722

@@ -1161,8 +1161,7 @@

44723

GIMPLE_ASM operands with memory constrains which cannot be scalarized. */

44724

44725

static bool

44726

-asm_visit_addr (gimple stmt ATTRIBUTE_UNUSED, tree op,

44727

- void *data ATTRIBUTE_UNUSED)

44728

+asm_visit_addr (gimple, tree op, tree, void *)

44729

{

44730

op = get_base_address (op);

44731

if (op

44732

@@ -2890,6 +2889,10 @@

44733

lacc);

44734

else

44735

drhs = NULL_TREE;

44736

+ if (drhs

44737

+ && !useless_type_conversion_p (lacc->type, TREE_TYPE (drhs)))

44738

+ drhs = fold_build1_loc (loc, VIEW_CONVERT_EXPR,

44739

+ lacc->type, drhs);

44740

ds = gimple_build_debug_bind (get_access_replacement (lacc),

44741

drhs, gsi_stmt (*old_gsi));

44742

gsi_insert_after (new_gsi, ds, GSI_NEW_STMT);

44743

@@ -4868,6 +4871,14 @@

44744

return false;

44745

}

44746

44747

+ if (!opt_for_fn (node->symbol.decl, optimize)

44748

+ || !opt_for_fn (node->symbol.decl, flag_ipa_sra))

44749

+ {

44750

+ if (dump_file)

44751

+ fprintf (dump_file, "Function not optimized.\n");

44752

+ return false;

44753

+ }

44754

+

44755

if (DECL_VIRTUAL_P (current_function_decl))

44756

{

44757

if (dump_file)

44758

Index: gcc/tree-predcom.c

44759

===================================================================

44760

--- a/src/gcc/tree-predcom.c (.../tags/gcc_4_8_2_release)

44761

+++ b/src/gcc/tree-predcom.c (.../branches/gcc-4_8-branch)

44762

@@ -1323,90 +1323,43 @@

44763

gsi_insert_after (&bsi, new_stmt, GSI_NEW_STMT);

44764

}

44765

44766

-/* Returns the reference to the address of REF in the ITER-th iteration of

44767

- LOOP, or NULL if we fail to determine it (ITER may be negative). We

44768

- try to preserve the original shape of the reference (not rewrite it

44769

- as an indirect ref to the address), to make tree_could_trap_p in

44770

- prepare_initializers_chain return false more often. */

44771

+/* Returns a memory reference to DR in the ITER-th iteration of

44772

+ the loop it was analyzed in. Append init stmts to STMTS. */

44773

44774

-static tree

44775

-ref_at_iteration (struct loop *loop, tree ref, int iter)

44776

+static tree

44777

+ref_at_iteration (data_reference_p dr, int iter, gimple_seq *stmts)

44778

{

44779

- tree idx, *idx_p, type, val, op0 = NULL_TREE, ret;

44780

- affine_iv iv;

44781

- bool ok;

44782

-

44783

- if (handled_component_p (ref))

44784

+ tree off = DR_OFFSET (dr);

44785

+ tree coff = DR_INIT (dr);

44786

+ if (iter == 0)

44787

+ ;

44788

+ else if (TREE_CODE (DR_STEP (dr)) == INTEGER_CST)

44789

+ coff = size_binop (PLUS_EXPR, coff,

44790

+ size_binop (MULT_EXPR, DR_STEP (dr), ssize_int (iter)));

44791

+ else

44792

+ off = size_binop (PLUS_EXPR, off,

44793

+ size_binop (MULT_EXPR, DR_STEP (dr), ssize_int (iter)));

44794

+ tree addr = fold_build_pointer_plus (DR_BASE_ADDRESS (dr), off);

44795

+ addr = force_gimple_operand_1 (addr, stmts, is_gimple_mem_ref_addr,

44796

+ NULL_TREE);

44797

+ tree alias_ptr = fold_convert (reference_alias_ptr_type (DR_REF (dr)), coff);

44798

+ /* While data-ref analysis punts on bit offsets it still handles

44799

+ bitfield accesses at byte boundaries. Cope with that. Note that

44800

+ we cannot simply re-apply the outer COMPONENT_REF because the

44801

+ byte-granular portion of it is already applied via DR_INIT and

44802

+ DR_OFFSET, so simply build a BIT_FIELD_REF knowing that the bits

44803

+ start at offset zero. */

44804

+ if (TREE_CODE (DR_REF (dr)) == COMPONENT_REF

44805

+ && DECL_BIT_FIELD (TREE_OPERAND (DR_REF (dr), 1)))

44806

{

44807

- op0 = ref_at_iteration (loop, TREE_OPERAND (ref, 0), iter);

44808

- if (!op0)

44809

- return NULL_TREE;

44810

+ tree field = TREE_OPERAND (DR_REF (dr), 1);

44811

+ return build3 (BIT_FIELD_REF, TREE_TYPE (DR_REF (dr)),

44812

+ build2 (MEM_REF, DECL_BIT_FIELD_TYPE (field),

44813

+ addr, alias_ptr),

44814

+ DECL_SIZE (field), bitsize_zero_node);

44815

}

44816

- else if (!INDIRECT_REF_P (ref)

44817

- && TREE_CODE (ref) != MEM_REF)

44818

- return unshare_expr (ref);

44819

-

44820

- if (TREE_CODE (ref) == MEM_REF)

44821

- {

44822

- ret = unshare_expr (ref);

44823

- idx = TREE_OPERAND (ref, 0);

44824

- idx_p = &TREE_OPERAND (ret, 0);

44825

- }

44826

- else if (TREE_CODE (ref) == COMPONENT_REF)

44827

- {

44828

- /* Check that the offset is loop invariant. */

44829

- if (TREE_OPERAND (ref, 2)

44830

- && !expr_invariant_in_loop_p (loop, TREE_OPERAND (ref, 2)))

44831

- return NULL_TREE;

44832

-

44833

- return build3 (COMPONENT_REF, TREE_TYPE (ref), op0,

44834

- unshare_expr (TREE_OPERAND (ref, 1)),

44835

- unshare_expr (TREE_OPERAND (ref, 2)));

44836

- }

44837

- else if (TREE_CODE (ref) == ARRAY_REF)

44838

- {

44839

- /* Check that the lower bound and the step are loop invariant. */

44840

- if (TREE_OPERAND (ref, 2)

44841

- && !expr_invariant_in_loop_p (loop, TREE_OPERAND (ref, 2)))

44842

- return NULL_TREE;

44843

- if (TREE_OPERAND (ref, 3)

44844

- && !expr_invariant_in_loop_p (loop, TREE_OPERAND (ref, 3)))

44845

- return NULL_TREE;

44846

-

44847

- ret = build4 (ARRAY_REF, TREE_TYPE (ref), op0, NULL_TREE,

44848

- unshare_expr (TREE_OPERAND (ref, 2)),

44849

- unshare_expr (TREE_OPERAND (ref, 3)));

44850

- idx = TREE_OPERAND (ref, 1);

44851

- idx_p = &TREE_OPERAND (ret, 1);

44852

- }

44853

else

44854

- return NULL_TREE;

44855

-

44856

- ok = simple_iv (loop, loop, idx, &iv, true);

44857

- if (!ok)

44858

- return NULL_TREE;

44859

- iv.base = expand_simple_operations (iv.base);

44860

- if (integer_zerop (iv.step))

44861

- *idx_p = unshare_expr (iv.base);

44862

- else

44863

- {

44864

- type = TREE_TYPE (iv.base);

44865

- if (POINTER_TYPE_P (type))

44866

- {

44867

- val = fold_build2 (MULT_EXPR, sizetype, iv.step,

44868

- size_int (iter));

44869

- val = fold_build_pointer_plus (iv.base, val);

44870

- }

44871

- else

44872

- {

44873

- val = fold_build2 (MULT_EXPR, type, iv.step,

44874

- build_int_cst_type (type, iter));

44875

- val = fold_build2 (PLUS_EXPR, type, iv.base, val);

44876

- }

44877

- *idx_p = unshare_expr (val);

44878

- }

44879

-

44880

- return ret;

44881

+ return fold_build2 (MEM_REF, TREE_TYPE (DR_REF (dr)), addr, alias_ptr);

44882

}

44883

44884

/* Get the initialization expression for the INDEX-th temporary variable

44885

@@ -2068,7 +2021,11 @@

44886

44887

stmt = find_common_use_stmt (&name1, &name2);

44888

44889

- if (!stmt)

44890

+ if (!stmt

44891

+ /* A simple post-dominance check - make sure the combination

44892

+ is executed under the same condition as the references. */

44893

+ || (gimple_bb (stmt) != gimple_bb (r1->stmt)

44894

+ && gimple_bb (stmt) != gimple_bb (r2->stmt)))

44895

return false;

44896

44897

acode = gimple_assign_rhs_code (stmt);

44898

@@ -2365,14 +2322,10 @@

44899

if (chain->inits[i] != NULL_TREE)

44900

continue;

44901

44902

- init = ref_at_iteration (loop, DR_REF (dr), (int) i - n);

44903

- if (!init)

44904

- return false;

44905

-

44906

+ init = ref_at_iteration (dr, (int) i - n, &stmts);

44907

if (!chain->all_always_accessed && tree_could_trap_p (init))

44908

return false;

44909

44910

- init = force_gimple_operand (init, &stmts, false, NULL_TREE);

44911

if (stmts)

44912

gsi_insert_seq_on_edge_immediate (entry, stmts);

44913

44914

@@ -2449,6 +2402,7 @@

44915

if (!components)

44916

{

44917

free_data_refs (datarefs);

44918

+ free_affine_expand_cache (&name_expansions);

44919

return false;

44920

}

44921

44922

Index: gcc/loop-iv.c

44923

===================================================================

44924

--- a/src/gcc/loop-iv.c (.../tags/gcc_4_8_2_release)

44925

+++ b/src/gcc/loop-iv.c (.../branches/gcc-4_8-branch)

44926

@@ -425,7 +425,9 @@

44927

&& !iv->first_special)

44928

{

44929

rtx val = get_iv_value (iv, const0_rtx);

44930

- val = lowpart_subreg (mode, val, iv->extend_mode);

44931

+ val = lowpart_subreg (mode, val,

44932

+ iv->extend == IV_UNKNOWN_EXTEND

44933

+ ? iv->mode : iv->extend_mode);

44934

44935

iv->base = val;

44936

iv->extend = IV_UNKNOWN_EXTEND;

44937

@@ -465,8 +467,14 @@

44938

&& !iv->first_special)

44939

{

44940

rtx val = get_iv_value (iv, const0_rtx);

44941

+ if (iv->extend_mode != iv->mode

44942

+ && iv->extend != IV_UNKNOWN_EXTEND

44943

+ && iv->extend != extend)

44944

+ val = lowpart_subreg (iv->mode, val, iv->extend_mode);

44945

val = simplify_gen_unary (iv_extend_to_rtx_code (extend), mode,

44946

- val, iv->extend_mode);

44947

+ val,

44948

+ iv->extend == extend

44949

+ ? iv->extend_mode : iv->mode);

44950

iv->base = val;

44951

iv->extend = IV_UNKNOWN_EXTEND;

44952

iv->mode = iv->extend_mode = mode;

44953

Index: gcc/ipa-prop.c

44954

===================================================================

44955

--- a/src/gcc/ipa-prop.c (.../tags/gcc_4_8_2_release)

44956

+++ b/src/gcc/ipa-prop.c (.../branches/gcc-4_8-branch)

44957

@@ -623,16 +623,22 @@

44958

if (parm_ainfo && parm_ainfo->parm_modified)

44959

return false;

44960

44961

- gcc_checking_assert (gimple_vuse (stmt) != NULL_TREE);

44962

- ao_ref_init (&refd, parm_load);

44963

- /* We can cache visited statements only when parm_ainfo is available and when

44964

- we are looking at a naked load of the whole parameter. */

44965

- if (!parm_ainfo || TREE_CODE (parm_load) != PARM_DECL)

44966

- visited_stmts = NULL;

44967

+ if (optimize)

44968

+ {

44969

+ gcc_checking_assert (gimple_vuse (stmt) != NULL_TREE);

44970

+ ao_ref_init (&refd, parm_load);

44971

+ /* We can cache visited statements only when parm_ainfo is available and

44972

+ when we are looking at a naked load of the whole parameter. */

44973

+ if (!parm_ainfo || TREE_CODE (parm_load) != PARM_DECL)

44974

+ visited_stmts = NULL;

44975

+ else

44976

+ visited_stmts = &parm_ainfo->parm_visited_statements;

44977

+ walk_aliased_vdefs (&refd, gimple_vuse (stmt), mark_modified, &modified,

44978

+ visited_stmts);

44979

+ }

44980

else

44981

- visited_stmts = &parm_ainfo->parm_visited_statements;

44982

- walk_aliased_vdefs (&refd, gimple_vuse (stmt), mark_modified, &modified,

44983

- visited_stmts);

44984

+ modified = true;

44985

+

44986

if (parm_ainfo && modified)

44987

parm_ainfo->parm_modified = true;

44988

return !modified;

44989

@@ -740,7 +746,7 @@

44990

ipa_load_from_parm_agg_1 (vec<ipa_param_descriptor_t> descriptors,

44991

struct param_analysis_info *parms_ainfo, gimple stmt,

44992

tree op, int *index_p, HOST_WIDE_INT *offset_p,

44993

- bool *by_ref_p)

44994

+ HOST_WIDE_INT *size_p, bool *by_ref_p)

44995

{

44996

int index;

44997

HOST_WIDE_INT size, max_size;

44998

@@ -758,6 +764,8 @@

44999

{

45000

*index_p = index;

45001

*by_ref_p = false;

45002

+ if (size_p)

45003

+ *size_p = size;

45004

return true;

45005

}

45006

return false;

45007

@@ -800,6 +808,8 @@

45008

{

45009

*index_p = index;

45010

*by_ref_p = true;

45011

+ if (size_p)

45012

+ *size_p = size;

45013

return true;

45014

}

45015

return false;

45016

@@ -814,7 +824,7 @@

45017

bool *by_ref_p)

45018

{

45019

return ipa_load_from_parm_agg_1 (info->descriptors, NULL, stmt, op, index_p,

45020

- offset_p, by_ref_p);

45021

+ offset_p, NULL, by_ref_p);

45022

}

45023

45024

/* Given that an actual argument is an SSA_NAME (given in NAME) and is a result

45025

@@ -1051,7 +1061,8 @@

45026

return;

45027

parm = TREE_OPERAND (expr, 0);

45028

index = ipa_get_param_decl_index (info, SSA_NAME_VAR (parm));

45029

- gcc_assert (index >= 0);

45030

+ if (index < 0)

45031

+ return;

45032

45033

cond_bb = single_pred (assign_bb);

45034

cond = last_stmt (cond_bb);

45035

@@ -1462,6 +1473,9 @@

45036

{

45037

struct cgraph_edge *cs;

45038

45039

+ if (!optimize)

45040

+ return;

45041

+

45042

for (cs = node->callees; cs; cs = cs->next_callee)

45043

{

45044

struct cgraph_node *callee = cgraph_function_or_thunk_node (cs->callee,

45045

@@ -1646,7 +1660,7 @@

45046

if (gimple_assign_single_p (def)

45047

&& ipa_load_from_parm_agg_1 (info->descriptors, parms_ainfo, def,

45048

gimple_assign_rhs1 (def), &index, &offset,

45049

- &by_ref))

45050

+ NULL, &by_ref))

45051

{

45052

struct cgraph_edge *cs = ipa_note_param_call (node, index, call);

45053

cs->indirect_info->offset = offset;

45054

@@ -1847,8 +1861,7 @@

45055

passed in DATA. */

45056

45057

static bool

45058

-visit_ref_for_mod_analysis (gimple stmt ATTRIBUTE_UNUSED,

45059

- tree op, void *data)

45060

+visit_ref_for_mod_analysis (gimple, tree op, tree, void *data)

45061

{

45062

struct ipa_node_params *info = (struct ipa_node_params *) data;

45063

45064

@@ -2126,7 +2139,6 @@

45065

we may create the first reference to the object in the unit. */

45066

if (!callee || callee->global.inlined_to)

45067

{

45068

- struct cgraph_node *first_clone = callee;

45069

45070

/* We are better to ensure we can refer to it.

45071

In the case of static functions we are out of luck, since we already

45072

@@ -2142,31 +2154,7 @@

45073

xstrdup (cgraph_node_name (ie->callee)), ie->callee->uid);

45074

return NULL;

45075

}

45076

-

45077

- /* Create symbol table node. Even if inline clone exists, we can not take

45078

- it as a target of non-inlined call. */

45079

- callee = cgraph_create_node (target);

45080

-

45081

- /* OK, we previously inlined the function, then removed the offline copy and

45082

- now we want it back for external call. This can happen when devirtualizing

45083

- while inlining function called once that happens after extern inlined and

45084

- virtuals are already removed. In this case introduce the external node

45085

- and make it available for call. */

45086

- if (first_clone)

45087

- {

45088

- first_clone->clone_of = callee;

45089

- callee->clones = first_clone;

45090

- symtab_prevail_in_asm_name_hash ((symtab_node)callee);

45091

- symtab_insert_node_to_hashtable ((symtab_node)callee);

45092

- if (dump_file)

45093

- fprintf (dump_file, "ipa-prop: Introduced new external node "

45094

- "(%s/%i) and turned into root of the clone tree.\n",

45095

- xstrdup (cgraph_node_name (callee)), callee->uid);

45096

- }

45097

- else if (dump_file)

45098

- fprintf (dump_file, "ipa-prop: Introduced new external node "

45099

- "(%s/%i).\n",

45100

- xstrdup (cgraph_node_name (callee)), callee->uid);

45101

+ callee = cgraph_get_create_real_symbol_node (target);

45102

}

45103

ipa_check_create_node_params ();

45104

45105

@@ -3902,7 +3890,7 @@

45106

struct ipa_agg_replacement_value *v;

45107

gimple stmt = gsi_stmt (gsi);

45108

tree rhs, val, t;

45109

- HOST_WIDE_INT offset;

45110

+ HOST_WIDE_INT offset, size;

45111

int index;

45112

bool by_ref, vce;

45113

45114

@@ -3929,13 +3917,15 @@

45115

continue;

45116

45117

if (!ipa_load_from_parm_agg_1 (descriptors, parms_ainfo, stmt,

45118

- rhs, &index, &offset, &by_ref))

45119

+ rhs, &index, &offset, &size, &by_ref))

45120

continue;

45121

for (v = aggval; v; v = v->next)

45122

if (v->index == index

45123

&& v->offset == offset)

45124

break;

45125

- if (!v || v->by_ref != by_ref)

45126

+ if (!v

45127

+ || v->by_ref != by_ref

45128

+ || tree_low_cst (TYPE_SIZE (TREE_TYPE (v->value)), 0) != size)

45129

continue;

45130

45131

gcc_checking_assert (is_gimple_ip_invariant (v->value));

45132

Index: gcc/tree-ssa-dce.c

45133

===================================================================

45134

--- a/src/gcc/tree-ssa-dce.c (.../tags/gcc_4_8_2_release)

45135

+++ b/src/gcc/tree-ssa-dce.c (.../branches/gcc-4_8-branch)

45136

@@ -1307,26 +1307,19 @@

45137

stats.total++;

45138

45139

/* We can mark a call to free as not necessary if the

45140

- defining statement of its argument is an allocation

45141

- function and that is not necessary itself. */

45142

- if (gimple_call_builtin_p (stmt, BUILT_IN_FREE))

45143

+ defining statement of its argument is not necessary

45144

+ (and thus is getting removed). */

45145

+ if (gimple_plf (stmt, STMT_NECESSARY)

45146

+ && gimple_call_builtin_p (stmt, BUILT_IN_FREE))

45147

{

45148

tree ptr = gimple_call_arg (stmt, 0);

45149

- tree callee2;

45150

- gimple def_stmt;

45151

- if (TREE_CODE (ptr) != SSA_NAME)

45152

- continue;

45153

- def_stmt = SSA_NAME_DEF_STMT (ptr);

45154

- if (!is_gimple_call (def_stmt)

45155

- || gimple_plf (def_stmt, STMT_NECESSARY))

45156

- continue;

45157

- callee2 = gimple_call_fndecl (def_stmt);

45158

- if (callee2 == NULL_TREE

45159

- || DECL_BUILT_IN_CLASS (callee2) != BUILT_IN_NORMAL

45160

- || (DECL_FUNCTION_CODE (callee2) != BUILT_IN_MALLOC

45161

- && DECL_FUNCTION_CODE (callee2) != BUILT_IN_CALLOC))

45162

- continue;

45163

- gimple_set_plf (stmt, STMT_NECESSARY, false);

45164

+ if (TREE_CODE (ptr) == SSA_NAME)

45165

+ {

45166

+ gimple def_stmt = SSA_NAME_DEF_STMT (ptr);

45167

+ if (!gimple_nop_p (def_stmt)

45168

+ && !gimple_plf (def_stmt, STMT_NECESSARY))

45169

+ gimple_set_plf (stmt, STMT_NECESSARY, false);

45170

+ }

45171

}

45172

45173

/* If GSI is not necessary then remove it. */

45174

Index: gcc/tree-ssa-ter.c

45175

===================================================================

45176

--- a/src/gcc/tree-ssa-ter.c (.../tags/gcc_4_8_2_release)

45177

+++ b/src/gcc/tree-ssa-ter.c (.../branches/gcc-4_8-branch)

45178

@@ -590,6 +590,30 @@

45179

}

45180

45181

45182

+/* Helper function for find_ssaname_in_stores. Called via walk_tree to

45183

+ find a SSA_NAME DATA somewhere in *TP. */

45184

+

45185

+static tree

45186

+find_ssaname (tree *tp, int *walk_subtrees, void *data)

45187

+{

45188

+ tree var = (tree) data;

45189

+ if (*tp == var)

45190

+ return var;

45191

+ else if (IS_TYPE_OR_DECL_P (*tp))

45192

+ *walk_subtrees = 0;

45193

+ return NULL_TREE;

45194

+}

45195

+

45196

+/* Helper function for find_replaceable_in_bb. Return true if SSA_NAME DATA

45197

+ is used somewhere in T, which is a store in the statement. Called via

45198

+ walk_stmt_load_store_addr_ops. */

45199

+

45200

+static bool

45201

+find_ssaname_in_store (gimple, tree, tree t, void *data)

45202

+{

45203

+ return walk_tree (&t, find_ssaname, data, NULL) != NULL_TREE;

45204

+}

45205

+

45206

/* This function processes basic block BB, and looks for variables which can

45207

be replaced by their expressions. Results are stored in the table TAB. */

45208

45209

@@ -643,8 +667,7 @@

45210

/* If the stmt does a memory store and the replacement

45211

is a load aliasing it avoid creating overlapping

45212

assignments which we cannot expand correctly. */

45213

- if (gimple_vdef (stmt)

45214

- && gimple_assign_single_p (stmt))

45215

+ if (gimple_vdef (stmt))

45216

{

45217

gimple def_stmt = SSA_NAME_DEF_STMT (use);

45218

while (is_gimple_assign (def_stmt)

45219

@@ -653,9 +676,29 @@

45220

= SSA_NAME_DEF_STMT (gimple_assign_rhs1 (def_stmt));

45221

if (gimple_vuse (def_stmt)

45222

&& gimple_assign_single_p (def_stmt)

45223

- && refs_may_alias_p (gimple_assign_lhs (stmt),

45224

- gimple_assign_rhs1 (def_stmt)))

45225

- same_root_var = true;

45226

+ && stmt_may_clobber_ref_p (stmt,

45227

+ gimple_assign_rhs1 (def_stmt)))

45228

+ {

45229

+ /* For calls, it is not a problem if USE is among

45230

+ call's arguments or say OBJ_TYPE_REF argument,

45231

+ all those necessarily need to be evaluated before

45232

+ the call that may clobber the memory. But if

45233

+ LHS of the call refers to USE, expansion might

45234

+ evaluate it after the call, prevent TER in that

45235

+ case.

45236

+ For inline asm, allow TER of loads into input

45237

+ arguments, but disallow TER for USEs that occur

45238

+ somewhere in outputs. */

45239

+ if (is_gimple_call (stmt)

45240

+ || gimple_code (stmt) == GIMPLE_ASM)

45241

+ {

45242

+ if (walk_stmt_load_store_ops (stmt, use, NULL,

45243

+ find_ssaname_in_store))

45244

+ same_root_var = true;

45245

+ }

45246

+ else

45247

+ same_root_var = true;

45248

+ }

45249

}

45250

45251

/* Mark expression as replaceable unless stmt is volatile, or the

45252

Index: gcc/ira.c

45253

===================================================================

45254

--- a/src/gcc/ira.c (.../tags/gcc_4_8_2_release)

45255

+++ b/src/gcc/ira.c (.../branches/gcc-4_8-branch)

45256

@@ -4742,6 +4742,18 @@

45257

if (need_dce && optimize)

45258

run_fast_dce ();

45259

45260

+ /* Diagnose uses of the hard frame pointer when it is used as a global

45261

+ register. Often we can get away with letting the user appropriate

45262

+ the frame pointer, but we should let them know when code generation

45263

+ makes that impossible. */

45264

+ if (global_regs[HARD_FRAME_POINTER_REGNUM] && frame_pointer_needed)

45265

+ {

45266

+ tree decl = global_regs_decl[HARD_FRAME_POINTER_REGNUM];

45267

+ error_at (DECL_SOURCE_LOCATION (current_function_decl),

45268

+ "frame pointer required, but reserved");

45269

+ inform (DECL_SOURCE_LOCATION (decl), "for %qD", decl);

45270

+ }

45271

+

45272

timevar_pop (TV_IRA);

45273

}

45274

45275

Index: gcc/rtl.h

45276

===================================================================

45277

--- a/src/gcc/rtl.h (.../tags/gcc_4_8_2_release)

45278

+++ b/src/gcc/rtl.h (.../branches/gcc-4_8-branch)

45279

@@ -2705,6 +2705,8 @@

45280

const_rtx, rtx);

45281

extern int read_dependence (const_rtx, const_rtx);

45282

extern int anti_dependence (const_rtx, const_rtx);

45283

+extern int canon_anti_dependence (const_rtx, bool,

45284

+ const_rtx, enum machine_mode, rtx);

45285

extern int output_dependence (const_rtx, const_rtx);

45286

extern int may_alias_p (const_rtx, const_rtx);

45287

extern void init_alias_target (void);

45288

@@ -2789,6 +2791,8 @@

45289

#define fatal_insn_not_found(insn) \

45290

_fatal_insn_not_found (insn, __FILE__, __LINE__, __FUNCTION__)

45291

45292

+/* reginfo.c */

45293

+extern tree GTY(()) global_regs_decl[FIRST_PSEUDO_REGISTER];

45294

45295

45296

#endif /* ! GCC_RTL_H */

45297

Index: gcc/tree-vect-stmts.c

45298

===================================================================

45299

--- a/src/gcc/tree-vect-stmts.c (.../tags/gcc_4_8_2_release)

45300

+++ b/src/gcc/tree-vect-stmts.c (.../branches/gcc-4_8-branch)

45301

@@ -4369,6 +4369,20 @@

45302

return false;

45303

}

45304

45305

+ /* Invalidate assumptions made by dependence analysis when vectorization

45306

+ on the unrolled body effectively re-orders stmts. */

45307

+ if (ncopies > 1

45308

+ && STMT_VINFO_MIN_NEG_DIST (stmt_info) != 0

45309

+ && ((unsigned)LOOP_VINFO_VECT_FACTOR (loop_vinfo)

45310

+ > STMT_VINFO_MIN_NEG_DIST (stmt_info)))

45311

+ {

45312

+ if (dump_enabled_p ())

45313

+ dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location,

45314

+ "cannot perform implicit CSE when unrolling "

45315

+ "with negative dependence distance\n");

45316

+ return false;

45317

+ }

45318

+

45319

if (!STMT_VINFO_RELEVANT_P (stmt_info) && !bb_vinfo)

45320

return false;

45321

45322

@@ -4425,6 +4439,20 @@

45323

else if (!vect_grouped_load_supported (vectype, group_size))

45324

return false;

45325

}

45326

+

45327

+ /* Invalidate assumptions made by dependence analysis when vectorization

45328

+ on the unrolled body effectively re-orders stmts. */

45329

+ if (!PURE_SLP_STMT (stmt_info)

45330

+ && STMT_VINFO_MIN_NEG_DIST (stmt_info) != 0

45331

+ && ((unsigned)LOOP_VINFO_VECT_FACTOR (loop_vinfo)

45332

+ > STMT_VINFO_MIN_NEG_DIST (stmt_info)))

45333

+ {

45334

+ if (dump_enabled_p ())

45335

+ dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location,

45336

+ "cannot perform implicit CSE when performing "

45337

+ "group loads with negative dependence distance\n");

45338

+ return false;

45339

+ }

45340

}

45341

45342

45343

@@ -6054,8 +6082,7 @@

45344

corresponding to that mode. The theory is that any use that

45345

would cause problems with this will disable vectorization anyway. */

45346

else if (!SCALAR_FLOAT_TYPE_P (scalar_type)

45347

- && !INTEGRAL_TYPE_P (scalar_type)

45348

- && !POINTER_TYPE_P (scalar_type))

45349

+ && !INTEGRAL_TYPE_P (scalar_type))

45350

scalar_type = lang_hooks.types.type_for_mode (inner_mode, 1);

45351

45352

/* We can't build a vector type of elements with alignment bigger than

45353

Index: gcc/tree-inline.c

45354

===================================================================

45355

--- a/src/gcc/tree-inline.c (.../tags/gcc_4_8_2_release)

45356

+++ b/src/gcc/tree-inline.c (.../branches/gcc-4_8-branch)

45357

@@ -2841,7 +2841,8 @@

45358

{

45359

var = return_slot;

45360

gcc_assert (TREE_CODE (var) != SSA_NAME);

45361

- TREE_ADDRESSABLE (var) |= TREE_ADDRESSABLE (result);

45362

+ if (TREE_ADDRESSABLE (result))

45363

+ mark_addressable (var);

45364

}

45365

if ((TREE_CODE (TREE_TYPE (result)) == COMPLEX_TYPE

45366

|| TREE_CODE (TREE_TYPE (result)) == VECTOR_TYPE)

45367

Index: gcc/tree-ssa-phiprop.c

45368

===================================================================

45369

--- a/src/gcc/tree-ssa-phiprop.c (.../tags/gcc_4_8_2_release)

45370

+++ b/src/gcc/tree-ssa-phiprop.c (.../branches/gcc-4_8-branch)

45371

@@ -307,6 +307,12 @@

45372

gimple def_stmt;

45373

tree vuse;

45374

45375

+ /* Only replace loads in blocks that post-dominate the PHI node. That

45376

+ makes sure we don't end up speculating loads. */

45377

+ if (!dominated_by_p (CDI_POST_DOMINATORS,

45378

+ bb, gimple_bb (use_stmt)))

45379

+ continue;

45380

+

45381

/* Check whether this is a load of *ptr. */

45382

if (!(is_gimple_assign (use_stmt)

45383

&& TREE_CODE (gimple_assign_lhs (use_stmt)) == SSA_NAME

45384

@@ -378,6 +384,7 @@

45385

size_t n;

45386

45387

calculate_dominance_info (CDI_DOMINATORS);

45388

+ calculate_dominance_info (CDI_POST_DOMINATORS);

45389

45390

n = num_ssa_names;

45391

phivn = XCNEWVEC (struct phiprop_d, n);

45392

@@ -395,6 +402,8 @@

45393

bbs.release ();

45394

free (phivn);

45395

45396

+ free_dominance_info (CDI_POST_DOMINATORS);

45397

+

45398

return 0;

45399

}

45400

45401

Index: gcc/tree-object-size.c

45402

===================================================================

45403

--- a/src/gcc/tree-object-size.c (.../tags/gcc_4_8_2_release)

45404

+++ b/src/gcc/tree-object-size.c (.../branches/gcc-4_8-branch)

45405

@@ -64,7 +64,7 @@

45406

the subobject (innermost array or field with address taken).

45407

object_sizes[2] is lower bound for number of bytes till the end of

45408

the object and object_sizes[3] lower bound for subobject. */

45409

-static unsigned HOST_WIDE_INT *object_sizes[4];

45410

+static vec<unsigned HOST_WIDE_INT> object_sizes[4];

45411

45412

/* Bitmaps what object sizes have been computed already. */

45413

static bitmap computed[4];

45414

@@ -493,7 +493,7 @@

45415

45416

if (TREE_CODE (ptr) == SSA_NAME

45417

&& POINTER_TYPE_P (TREE_TYPE (ptr))

45418

- && object_sizes[object_size_type] != NULL)

45419

+ && computed[object_size_type] != NULL)

45420

{

45421

if (!bitmap_bit_p (computed[object_size_type], SSA_NAME_VERSION (ptr)))

45422

{

45423

@@ -501,6 +501,8 @@

45424

bitmap_iterator bi;

45425

unsigned int i;

45426

45427

+ if (num_ssa_names > object_sizes[object_size_type].length ())

45428

+ object_sizes[object_size_type].safe_grow (num_ssa_names);

45429

if (dump_file)

45430

{

45431

fprintf (dump_file, "Computing %s %sobject size for ",

45432

@@ -1162,12 +1164,12 @@

45433

{

45434

int object_size_type;

45435

45436

- if (object_sizes[0])

45437

+ if (computed[0])

45438

return;

45439

45440

for (object_size_type = 0; object_size_type <= 3; object_size_type++)

45441

{

45442

- object_sizes[object_size_type] = XNEWVEC (unsigned HOST_WIDE_INT, num_ssa_names);

45443

+ object_sizes[object_size_type].safe_grow (num_ssa_names);

45444

computed[object_size_type] = BITMAP_ALLOC (NULL);

45445

}

45446

45447

@@ -1184,9 +1186,8 @@

45448

45449

for (object_size_type = 0; object_size_type <= 3; object_size_type++)

45450

{

45451

- free (object_sizes[object_size_type]);

45452

+ object_sizes[object_size_type].release ();

45453

BITMAP_FREE (computed[object_size_type]);

45454

- object_sizes[object_size_type] = NULL;

45455

}

45456

}

45457

45458

@@ -1202,18 +1203,11 @@

45459

gimple_stmt_iterator i;

45460

for (i = gsi_start_bb (bb); !gsi_end_p (i); gsi_next (&i))

45461

{

45462

- tree callee, result;

45463

+ tree result;

45464

gimple call = gsi_stmt (i);

45465

-

45466

- if (gimple_code (call) != GIMPLE_CALL)

45467

+ if (!gimple_call_builtin_p (call, BUILT_IN_OBJECT_SIZE))

45468

continue;

45469

45470

- callee = gimple_call_fndecl (call);

45471

- if (!callee

45472

- || DECL_BUILT_IN_CLASS (callee) != BUILT_IN_NORMAL

45473

- || DECL_FUNCTION_CODE (callee) != BUILT_IN_OBJECT_SIZE)

45474

- continue;

45475

-

45476

init_object_sizes ();

45477

result = fold_call_stmt (call, false);

45478

if (!result)

45479

@@ -1240,20 +1234,32 @@

45480

continue;

45481

}

45482

45483

+ gcc_assert (TREE_CODE (result) == INTEGER_CST);

45484

+

45485

if (dump_file && (dump_flags & TDF_DETAILS))

45486

{

45487

fprintf (dump_file, "Simplified\n ");

45488

print_gimple_stmt (dump_file, call, 0, dump_flags);

45489

+ fprintf (dump_file, " to ");

45490

+ print_generic_expr (dump_file, result, 0);

45491

+ fprintf (dump_file, "\n");

45492

}

45493

45494

- if (!update_call_from_tree (&i, result))

45495

- gcc_unreachable ();

45496

+ tree lhs = gimple_call_lhs (call);

45497

+ if (!lhs)

45498

+ continue;

45499

45500

- if (dump_file && (dump_flags & TDF_DETAILS))

45501

+ /* Propagate into all uses and fold those stmts. */

45502

+ gimple use_stmt;

45503

+ imm_use_iterator iter;

45504

+ FOR_EACH_IMM_USE_STMT (use_stmt, iter, lhs)

45505

{

45506

- fprintf (dump_file, "to\n ");

45507

- print_gimple_stmt (dump_file, gsi_stmt (i), 0, dump_flags);

45508

- fprintf (dump_file, "\n");

45509

+ use_operand_p use_p;

45510

+ FOR_EACH_IMM_USE_ON_STMT (use_p, iter)

45511

+ SET_USE (use_p, result);

45512

+ gimple_stmt_iterator gsi = gsi_for_stmt (use_stmt);

45513

+ fold_stmt (&gsi);

45514

+ update_stmt (gsi_stmt (gsi));

45515

}

45516

}

45517

}

45518

Index: gcc/combine.c

45519

===================================================================

45520

--- a/src/gcc/combine.c (.../tags/gcc_4_8_2_release)

45521

+++ b/src/gcc/combine.c (.../branches/gcc-4_8-branch)

45522

@@ -3884,15 +3884,19 @@

45523

45524

PATTERN (undobuf.other_insn) = other_pat;

45525

45526

- /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they

45527

- are still valid. Then add any non-duplicate notes added by

45528

- recog_for_combine. */

45529

+ /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,

45530

+ ensure that they are still valid. Then add any non-duplicate

45531

+ notes added by recog_for_combine. */

45532

for (note = REG_NOTES (undobuf.other_insn); note; note = next)

45533

{

45534

next = XEXP (note, 1);

45535

45536

- if (REG_NOTE_KIND (note) == REG_UNUSED

45537

- && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))

45538

+ if ((REG_NOTE_KIND (note) == REG_DEAD

45539

+ && !reg_referenced_p (XEXP (note, 0),

45540

+ PATTERN (undobuf.other_insn)))

45541

+ ||(REG_NOTE_KIND (note) == REG_UNUSED

45542

+ && !reg_set_p (XEXP (note, 0),

45543

+ PATTERN (undobuf.other_insn))))

45544

remove_note (undobuf.other_insn, note);

45545

}

45546

45547

@@ -5798,8 +5802,15 @@

45548

return x;

45549

}

45550

45551

- /* If the code changed, return a whole new comparison. */

45552

- if (new_code != code)

45553

+ /* If the code changed, return a whole new comparison.

45554

+ We also need to avoid using SUBST in cases where

45555

+ simplify_comparison has widened a comparison with a CONST_INT,

45556

+ since in that case the wider CONST_INT may fail the sanity

45557

+ checks in do_SUBST. */

45558

+ if (new_code != code

45559

+ || (CONST_INT_P (op1)

45560

+ && GET_MODE (op0) != GET_MODE (XEXP (x, 0))

45561

+ && GET_MODE (op0) != GET_MODE (XEXP (x, 1))))

45562

return gen_rtx_fmt_ee (new_code, mode, op0, op1);

45563

45564

/* Otherwise, keep this operation, but maybe change its operands.

45565

@@ -7991,7 +8002,7 @@

45566

if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)

45567

return x;

45568

45569

- /* We want to perform the operation is its present mode unless we know

45570

+ /* We want to perform the operation in its present mode unless we know

45571

that the operation is valid in MODE, in which case we do the operation

45572

in MODE. */

45573

op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))

45574

@@ -8427,9 +8438,10 @@

45575

GET_MODE (x), GEN_INT (mask),

45576

XEXP (x, 1));

45577

if (temp && CONST_INT_P (temp))

45578

- SUBST (XEXP (x, 0),

45579

- force_to_mode (XEXP (x, 0), GET_MODE (x),

45580

- INTVAL (temp), next_select));

45581

+ x = simplify_gen_binary (code, GET_MODE (x),

45582

+ force_to_mode (XEXP (x, 0), GET_MODE (x),

45583

+ INTVAL (temp), next_select),

45584

+ XEXP (x, 1));

45585

}

45586

break;

45587

45588

@@ -8497,14 +8509,16 @@

45589

/* We have no way of knowing if the IF_THEN_ELSE can itself be

45590

written in a narrower mode. We play it safe and do not do so. */

45591

45592

- SUBST (XEXP (x, 1),

45593

- gen_lowpart_or_truncate (GET_MODE (x),

45594

- force_to_mode (XEXP (x, 1), mode,

45595

- mask, next_select)));

45596

- SUBST (XEXP (x, 2),

45597

- gen_lowpart_or_truncate (GET_MODE (x),

45598

- force_to_mode (XEXP (x, 2), mode,

45599

- mask, next_select)));

45600

+ op0 = gen_lowpart_or_truncate (GET_MODE (x),

45601

+ force_to_mode (XEXP (x, 1), mode,

45602

+ mask, next_select));

45603

+ op1 = gen_lowpart_or_truncate (GET_MODE (x),

45604

+ force_to_mode (XEXP (x, 2), mode,

45605

+ mask, next_select));

45606

+ if (op0 != XEXP (x, 1) || op1 != XEXP (x, 2))

45607

+ x = simplify_gen_ternary (IF_THEN_ELSE, GET_MODE (x),

45608

+ GET_MODE (XEXP (x, 0)), XEXP (x, 0),

45609

+ op0, op1);

45610

break;

45611

45612

default:

45613

Index: gcc/bb-reorder.c

45614

===================================================================

45615

--- a/src/gcc/bb-reorder.c (.../tags/gcc_4_8_2_release)

45616

+++ b/src/gcc/bb-reorder.c (.../branches/gcc-4_8-branch)

45617

@@ -1685,9 +1685,8 @@

45618

edge e;

45619

edge_iterator ei;

45620

45621

- /* Find EDGE_CAN_FALLTHRU edge. */

45622

FOR_EACH_EDGE (e, ei, cur_bb->succs)

45623

- if (e->flags & EDGE_CAN_FALLTHRU)

45624

+ if (e->flags & EDGE_FALLTHRU)

45625

{

45626

fall_thru = e;

45627

break;

45628

Index: gcc/tree-vect-generic.c

45629

===================================================================

45630

--- a/src/gcc/tree-vect-generic.c (.../tags/gcc_4_8_2_release)

45631

+++ b/src/gcc/tree-vect-generic.c (.../branches/gcc-4_8-branch)

45632

@@ -1006,7 +1006,8 @@

45633

45634

if (!optimize

45635

|| !VECTOR_INTEGER_TYPE_P (type)

45636

- || TREE_CODE (rhs2) != VECTOR_CST)

45637

+ || TREE_CODE (rhs2) != VECTOR_CST

45638

+ || !VECTOR_MODE_P (TYPE_MODE (type)))

45639

break;

45640

45641

ret = expand_vector_divmod (gsi, type, rhs1, rhs2, code);

45642

Index: gcc/tree-flow.h

45643

===================================================================

45644

--- a/src/gcc/tree-flow.h (.../tags/gcc_4_8_2_release)

45645

+++ b/src/gcc/tree-flow.h (.../branches/gcc-4_8-branch)

45646

@@ -425,6 +425,7 @@

45647

basic_block, tree);

45648

void remove_edge_and_dominated_blocks (edge);

45649

bool tree_node_can_be_shared (tree);

45650

+extern unsigned int split_critical_edges (void);

45651

45652

/* In tree-cfgcleanup.c */

45653

extern bitmap cfgcleanup_altered_bbs;

45654

Index: gcc/config.gcc

45655

===================================================================

45656

--- a/src/gcc/config.gcc (.../tags/gcc_4_8_2_release)

45657

+++ b/src/gcc/config.gcc (.../branches/gcc-4_8-branch)

45658

@@ -420,7 +420,7 @@

45659

;;

45660

powerpc*-*-*)

45661

cpu_type=rs6000

45662

- extra_headers="ppc-asm.h altivec.h spe.h ppu_intrinsics.h paired.h spu2vmx.h vec_types.h si2vmx.h"

45663

+ extra_headers="ppc-asm.h altivec.h spe.h ppu_intrinsics.h paired.h spu2vmx.h vec_types.h si2vmx.h htmintrin.h htmxlintrin.h"

45664

need_64bit_hwint=yes

45665

case x$with_cpu in

45666

xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[345678]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|Xe6500)

45667

@@ -1761,6 +1761,14 @@

45668

tmake_file="${tmake_file} microblaze/t-microblaze-linux"

45669

;;

45670

microblaze*-*-rtems*)

45671

+ case $target in

45672

+ microblazeel-*)

45673

+ tm_defines="${tm_defines} TARGET_BIG_ENDIAN_DEFAULT=0"

45674

+ ;;

45675

+ microblaze-*)

45676

+ tm_defines="${tm_defines} TARGET_BIG_ENDIAN_DEFAULT=4321"

45677

+ ;;

45678

+ esac

45679

tm_file="${tm_file} dbxelf.h"

45680

tm_file="${tm_file} microblaze/rtems.h rtems.h newlib-stdint.h"

45681

c_target_objs="${c_target_objs} microblaze-c.o"

45682

@@ -2073,7 +2081,7 @@

45683

tmake_file="rs6000/t-fprules rs6000/t-ppcos ${tmake_file} rs6000/t-ppccomm"

45684

case ${target} in

45685

powerpc*le-*-*)

45686

- tm_file="${tm_file} rs6000/sysv4le.h" ;;

45687

+ tm_file="${tm_file} rs6000/sysv4le.h" ;;

45688

esac

45689

maybe_biarch=yes

45690

case ${target} in

45691

@@ -2096,6 +2104,19 @@

45692

fi

45693

tm_file="rs6000/biarch64.h ${tm_file} rs6000/linux64.h glibc-stdint.h"

45694

tmake_file="$tmake_file rs6000/t-linux64"

45695

+ case ${target} in

45696

+ powerpc*le-*-*)

45697

+ tmake_file="$tmake_file rs6000/t-linux64le"

45698

+ case ${enable_targets} in

45699

+ all | *powerpc64-* | *powerpc-*)

45700

+ tmake_file="$tmake_file rs6000/t-linux64lebe" ;;

45701

+ esac ;;

45702

+ *)

45703

+ case ${enable_targets} in

45704

+ all | *powerpc64le-* | *powerpcle-*)

45705

+ tmake_file="$tmake_file rs6000/t-linux64bele" ;;

45706

+ esac ;;

45707

+ esac

45708

extra_options="${extra_options} rs6000/linux64.opt"

45709

;;

45710

*)

45711

@@ -2963,11 +2984,18 @@

45712

with_cpu=8540

45713

fi

45714

;;

45715

- sparc-leon*-*)

45716

- with_cpu=v8;

45717

- ;;

45718

sparc*-*-*)

45719

- with_cpu="`echo ${target} | sed 's/-.*$//'`"

45720

+ case ${target} in

45721

+ *-leon-*)

45722

+ with_cpu=leon

45723

+ ;;

45724

+ *-leon[3-9]*)

45725

+ with_cpu=leon3

45726

+ ;;

45727

+ *)

45728

+ with_cpu="`echo ${target} | sed 's/-.*$//'`"

45729

+ ;;

45730

+ esac

45731

;;

45732

esac

45733

45734

@@ -3494,7 +3522,7 @@

45735

;;

45736

45737

powerpc*-*-* | rs6000-*-*)

45738

- supported_defaults="cpu cpu_32 cpu_64 float tune tune_32 tune_64"

45739

+ supported_defaults="abi cpu cpu_32 cpu_64 float tune tune_32 tune_64"

45740

45741

for which in cpu cpu_32 cpu_64 tune tune_32 tune_64; do

45742

eval "val=\$with_$which"

45743

@@ -3531,6 +3559,16 @@

45744

;;

45745

esac

45746

done

45747

+

45748

+ case "$with_abi" in

45749

+ "" | elfv1 | elfv2 )

45750

+ #OK

45751

+ ;;

45752

+ *)

45753

+ echo "Unknown ABI used in --with-abi=$with_abi"

45754

+ exit 1

45755

+ ;;

45756

+ esac

45757

;;

45758

45759

s390*-*-*)

45760

@@ -3587,7 +3625,7 @@

45761

case ${val} in

45762

"" | sparc | sparcv9 | sparc64 \

45763

| v7 | cypress \

45764

- | v8 | supersparc | hypersparc | leon \

45765

45766

| sparclite | f930 | f934 | sparclite86x \

45767

| sparclet | tsc701 \

45768

45769

@@ -3745,15 +3783,6 @@

45770

cxx_target_objs="${cxx_target_objs} sh-c.o"

45771

;;

45772

45773

- sparc-leon*-*)

45774

- if test x$with_tune = x ; then

45775

- with_tune=leon;

45776

- fi

45777

-

45778

- # The SPARC port checks this value at compile-time.

45779

- target_cpu_default2="TARGET_CPU_$with_cpu"

45780

- ;;

45781

-

45782

sparc*-*-*)

45783

# Some standard aliases.

45784

case x$with_cpu in

45785

@@ -3765,6 +3794,17 @@

45786

;;

45787

esac

45788

45789

+ if test x$with_tune = x ; then

45790

+ case ${target} in

45791

+ *-leon-*)

45792

+ with_tune=leon

45793

+ ;;

45794

+ *-leon[3-9]*)

45795

+ with_tune=leon3

45796

+ ;;

45797

+ esac

45798

+ fi

45799

+

45800

# The SPARC port checks this value at compile-time.

45801

target_cpu_default2="TARGET_CPU_$with_cpu"

45802

;;

45803

Index: gcc/reginfo.c

45804

===================================================================

45805

--- a/src/gcc/reginfo.c (.../tags/gcc_4_8_2_release)

45806

+++ b/src/gcc/reginfo.c (.../branches/gcc-4_8-branch)

45807

@@ -85,7 +85,7 @@

45808

char global_regs[FIRST_PSEUDO_REGISTER];

45809

45810

/* Declaration for the global register. */

45811

-static tree GTY(()) global_regs_decl[FIRST_PSEUDO_REGISTER];

45812

+tree global_regs_decl[FIRST_PSEUDO_REGISTER];

45813

45814

/* Same information as REGS_INVALIDATED_BY_CALL but in regset form to be used

45815

in dataflow more conveniently. */

45816

@@ -620,40 +620,35 @@

45817

mode = GET_MODE_WIDER_MODE (mode))

45818

if ((unsigned) hard_regno_nregs[regno][mode] == nregs

45819

&& HARD_REGNO_MODE_OK (regno, mode)

45820

- && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)))

45821

+ && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))

45822

+ && GET_MODE_SIZE (mode) > GET_MODE_SIZE (found_mode))

45823

found_mode = mode;

45824

45825

- if (found_mode != VOIDmode)

45826

- return found_mode;

45827

-

45828

for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT);

45829

mode != VOIDmode;

45830

mode = GET_MODE_WIDER_MODE (mode))

45831

if ((unsigned) hard_regno_nregs[regno][mode] == nregs

45832

&& HARD_REGNO_MODE_OK (regno, mode)

45833

- && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)))

45834

+ && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))

45835

+ && GET_MODE_SIZE (mode) > GET_MODE_SIZE (found_mode))

45836

found_mode = mode;

45837

45838

- if (found_mode != VOIDmode)

45839

- return found_mode;

45840

-

45841

for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FLOAT);

45842

mode != VOIDmode;

45843

mode = GET_MODE_WIDER_MODE (mode))

45844

if ((unsigned) hard_regno_nregs[regno][mode] == nregs

45845

&& HARD_REGNO_MODE_OK (regno, mode)

45846

- && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)))

45847

+ && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))

45848

+ && GET_MODE_SIZE (mode) > GET_MODE_SIZE (found_mode))

45849

found_mode = mode;

45850

45851

- if (found_mode != VOIDmode)

45852

- return found_mode;

45853

-

45854

for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_INT);

45855

mode != VOIDmode;

45856

mode = GET_MODE_WIDER_MODE (mode))

45857

if ((unsigned) hard_regno_nregs[regno][mode] == nregs

45858

&& HARD_REGNO_MODE_OK (regno, mode)

45859

- && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)))

45860

+ && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))

45861

+ && GET_MODE_SIZE (mode) > GET_MODE_SIZE (found_mode))

45862

found_mode = mode;

45863

45864

if (found_mode != VOIDmode)

45865

Index: gcc/Makefile.in

45866

===================================================================

45867

--- a/src/gcc/Makefile.in (.../tags/gcc_4_8_2_release)

45868

+++ b/src/gcc/Makefile.in (.../branches/gcc-4_8-branch)

45869

@@ -747,7 +747,8 @@

45870

45871

# Native linker and preprocessor flags. For x-fragment overrides.

45872

BUILD_LDFLAGS=@BUILD_LDFLAGS@

45873

-BUILD_CPPFLAGS=$(ALL_CPPFLAGS)

45874

+BUILD_CPPFLAGS= -I. -I$(@D) -I$(srcdir) -I$(srcdir)/$(@D) \

45875

+ -I$(srcdir)/../include @INCINTL@ $(CPPINC) $(CPPFLAGS)

45876

45877

# Actual name to use when installing a native compiler.

45878

GCC_INSTALL_NAME := $(shell echo gcc|sed '$(program_transform_name)')

45879

@@ -1827,7 +1828,7 @@

45880

"$(MULTILIB_EXCLUSIONS)" \

45881

"$(MULTILIB_OSDIRNAMES)" \

45882

"$(MULTILIB_REQUIRED)" \

45883

- "$(MULTIARCH_DIRNAME)" \

45884

+ "$(if $(MULTILIB_OSDIRNAMES),,$(MULTIARCH_DIRNAME))" \

45885

"$(MULTILIB_REUSE)" \

45886

"@enable_multilib@" \

45887

> tmp-mlib.h; \

45888

@@ -2256,7 +2257,7 @@

45889

$(FUNCTION_H) $(TM_H) coretypes.h \

45890

$(TREE_PASS_H) $(BASIC_BLOCK_H) $(BITMAP_H) \

45891

$(FLAGS_H) $(HASHTAB_H) pointer-set.h \

45892

- $(GIMPLE_H) $(TREE_INLINE_H) $(GIMPLE_PRETTY_PRINT_H)

45893

+ $(GIMPLE_H) $(TREE_INLINE_H) $(GIMPLE_PRETTY_PRINT_H) $(PARAMS_H)

45894

tree-ssa.o : tree-ssa.c $(TREE_FLOW_H) $(CONFIG_H) $(SYSTEM_H) \

45895

$(TREE_H) $(TM_P_H) $(EXPR_H) $(DIAGNOSTIC_H) \

45896

toplev.h $(FUNCTION_H) $(TM_H) coretypes.h \

45897

@@ -3037,7 +3038,7 @@

45898

$(TM_H) coretypes.h $(GIMPLE_H) \

45899

$(TREE_PASS_H) $(FLAGS_H) $(EXPR_H) $(BASIC_BLOCK_H) \

45900

$(GGC_H) $(OBSTACK_H) $(PARAMS_H) $(CPPLIB_H) $(PARAMS_H) \

45901

- $(GIMPLE_PRETTY_PRINT_H) langhooks.h

45902

+ $(GIMPLE_PRETTY_PRINT_H) langhooks.h $(OPTABS_H)

45903

tree-complex.o : tree-complex.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TREE_H) \

45904

$(TM_H) $(FLAGS_H) $(TREE_FLOW_H) $(GIMPLE_H) \

45905

tree-iterator.h $(TREE_PASS_H) tree-ssa-propagate.h

45906

@@ -3276,12 +3277,12 @@

45907

$(TM_H) $(RTL_H) $(REGS_H) insn-config.h insn-codes.h $(DF_H) \

45908

$(RECOG_H) output.h addresses.h $(REGS_H) hard-reg-set.h $(FLAGS_H) \

45909

$(FUNCTION_H) $(EXPR_H) $(BASIC_BLOCK_H) $(TM_P_H) $(EXCEPT_H) \

45910

- ira.h rtl-error.h $(LRA_INT_H)

45911

+ ira.h rtl-error.h $(LRA_INT_H) $(OPTABS_H)

45912

lra-eliminations.o : lra-eliminations.c $(CONFIG_H) $(SYSTEM_H) coretypes.h \

45913

$(TM_H) $(RTL_H) $(REGS_H) insn-config.h $(DF_H) \

45914

$(RECOG_H) output.h $(REGS_H) hard-reg-set.h $(FLAGS_H) $(FUNCTION_H) \

45915

$(EXPR_H) $(BASIC_BLOCK_H) $(TM_P_H) $(EXCEPT_H) ira.h \

45916

- rtl-error.h $(LRA_INT_H)

45917

+ rtl-error.h $(LRA_INT_H) $(OPTABS_H)

45918

lra-lives.o : lra-lives.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \

45919

$(RTL_H) $(REGS_H) insn-config.h $(DF_H) \

45920

$(RECOG_H) output.h $(REGS_H) hard-reg-set.h $(FLAGS_H) $(FUNCTION_H) \

45921

Index: gcc/gimple.c

45922

===================================================================

45923

--- a/src/gcc/gimple.c (.../tags/gcc_4_8_2_release)

45924

+++ b/src/gcc/gimple.c (.../branches/gcc-4_8-branch)

45925

@@ -3841,42 +3841,46 @@

45926

45927

/* For the statement STMT call the callbacks VISIT_LOAD, VISIT_STORE and

45928

VISIT_ADDR if non-NULL on loads, store and address-taken operands

45929

- passing the STMT, the base of the operand and DATA to it. The base

45930

- will be either a decl, an indirect reference (including TARGET_MEM_REF)

45931

- or the argument of an address expression.

45932

+ passing the STMT, the base of the operand, the operand itself containing

45933

+ the base and DATA to it. The base will be either a decl, an indirect

45934

+ reference (including TARGET_MEM_REF) or the argument of an address

45935

+ expression.

45936

Returns the results of these callbacks or'ed. */

45937

45938

bool

45939

walk_stmt_load_store_addr_ops (gimple stmt, void *data,

45940

- bool (*visit_load)(gimple, tree, void *),

45941

- bool (*visit_store)(gimple, tree, void *),

45942

- bool (*visit_addr)(gimple, tree, void *))

45943

+ walk_stmt_load_store_addr_fn visit_load,

45944

+ walk_stmt_load_store_addr_fn visit_store,

45945

+ walk_stmt_load_store_addr_fn visit_addr)

45946

{

45947

bool ret = false;

45948

unsigned i;

45949

if (gimple_assign_single_p (stmt))

45950

{

45951

- tree lhs, rhs;

45952

+ tree lhs, rhs, arg;

45953

if (visit_store)

45954

{

45955

- lhs = get_base_loadstore (gimple_assign_lhs (stmt));

45956

+ arg = gimple_assign_lhs (stmt);

45957

+ lhs = get_base_loadstore (arg);

45958

if (lhs)

45959

- ret |= visit_store (stmt, lhs, data);

45960

+ ret |= visit_store (stmt, lhs, arg, data);

45961

}

45962

- rhs = gimple_assign_rhs1 (stmt);

45963

+ arg = gimple_assign_rhs1 (stmt);

45964

+ rhs = arg;

45965

while (handled_component_p (rhs))

45966

rhs = TREE_OPERAND (rhs, 0);

45967

if (visit_addr)

45968

{

45969

if (TREE_CODE (rhs) == ADDR_EXPR)

45970

- ret |= visit_addr (stmt, TREE_OPERAND (rhs, 0), data);

45971

+ ret |= visit_addr (stmt, TREE_OPERAND (rhs, 0), arg, data);

45972

else if (TREE_CODE (rhs) == TARGET_MEM_REF

45973

&& TREE_CODE (TMR_BASE (rhs)) == ADDR_EXPR)

45974

- ret |= visit_addr (stmt, TREE_OPERAND (TMR_BASE (rhs), 0), data);

45975

+ ret |= visit_addr (stmt, TREE_OPERAND (TMR_BASE (rhs), 0), arg,

45976

+ data);

45977

else if (TREE_CODE (rhs) == OBJ_TYPE_REF

45978

&& TREE_CODE (OBJ_TYPE_REF_OBJECT (rhs)) == ADDR_EXPR)

45979

ret |= visit_addr (stmt, TREE_OPERAND (OBJ_TYPE_REF_OBJECT (rhs),

45980

- 0), data);

45981

+ 0), arg, data);

45982

else if (TREE_CODE (rhs) == CONSTRUCTOR)

45983

{

45984

unsigned int ix;

45985

@@ -3884,23 +3888,23 @@

45986

45987

FOR_EACH_CONSTRUCTOR_VALUE (CONSTRUCTOR_ELTS (rhs), ix, val)

45988

if (TREE_CODE (val) == ADDR_EXPR)

45989

- ret |= visit_addr (stmt, TREE_OPERAND (val, 0), data);

45990

+ ret |= visit_addr (stmt, TREE_OPERAND (val, 0), arg, data);

45991

else if (TREE_CODE (val) == OBJ_TYPE_REF

45992

&& TREE_CODE (OBJ_TYPE_REF_OBJECT (val)) == ADDR_EXPR)

45993

ret |= visit_addr (stmt,

45994

TREE_OPERAND (OBJ_TYPE_REF_OBJECT (val),

45995

- 0), data);

45996

+ 0), arg, data);

45997

}

45998

lhs = gimple_assign_lhs (stmt);

45999

if (TREE_CODE (lhs) == TARGET_MEM_REF

46000

&& TREE_CODE (TMR_BASE (lhs)) == ADDR_EXPR)

46001

- ret |= visit_addr (stmt, TREE_OPERAND (TMR_BASE (lhs), 0), data);

46002

+ ret |= visit_addr (stmt, TREE_OPERAND (TMR_BASE (lhs), 0), lhs, data);

46003

}

46004

if (visit_load)

46005

{

46006

rhs = get_base_loadstore (rhs);

46007

if (rhs)

46008

- ret |= visit_load (stmt, rhs, data);

46009

+ ret |= visit_load (stmt, rhs, arg, data);

46010

}

46011

}

46012

else if (visit_addr

46013

@@ -3913,7 +3917,7 @@

46014

if (op == NULL_TREE)

46015

;

46016

else if (TREE_CODE (op) == ADDR_EXPR)

46017

- ret |= visit_addr (stmt, TREE_OPERAND (op, 0), data);

46018

+ ret |= visit_addr (stmt, TREE_OPERAND (op, 0), op, data);

46019

/* COND_EXPR and VCOND_EXPR rhs1 argument is a comparison

46020

tree with two operands. */

46021

else if (i == 1 && COMPARISON_CLASS_P (op))

46022

@@ -3920,10 +3924,10 @@

46023

{

46024

if (TREE_CODE (TREE_OPERAND (op, 0)) == ADDR_EXPR)

46025

ret |= visit_addr (stmt, TREE_OPERAND (TREE_OPERAND (op, 0),

46026

- 0), data);

46027

+ 0), op, data);

46028

if (TREE_CODE (TREE_OPERAND (op, 1)) == ADDR_EXPR)

46029

ret |= visit_addr (stmt, TREE_OPERAND (TREE_OPERAND (op, 1),

46030

- 0), data);

46031

+ 0), op, data);

46032

}

46033

}

46034

}

46035

@@ -3931,26 +3935,26 @@

46036

{

46037

if (visit_store)

46038

{

46039

- tree lhs = gimple_call_lhs (stmt);

46040

- if (lhs)

46041

+ tree arg = gimple_call_lhs (stmt);

46042

+ if (arg)

46043

{

46044

- lhs = get_base_loadstore (lhs);

46045

+ tree lhs = get_base_loadstore (arg);

46046

if (lhs)

46047

- ret |= visit_store (stmt, lhs, data);

46048

+ ret |= visit_store (stmt, lhs, arg, data);

46049

}

46050

}

46051

if (visit_load || visit_addr)

46052

for (i = 0; i < gimple_call_num_args (stmt); ++i)

46053

{

46054

- tree rhs = gimple_call_arg (stmt, i);

46055

+ tree arg = gimple_call_arg (stmt, i);

46056

if (visit_addr

46057

- && TREE_CODE (rhs) == ADDR_EXPR)

46058

- ret |= visit_addr (stmt, TREE_OPERAND (rhs, 0), data);

46059

+ && TREE_CODE (arg) == ADDR_EXPR)

46060

+ ret |= visit_addr (stmt, TREE_OPERAND (arg, 0), arg, data);

46061

else if (visit_load)

46062

{

46063

- rhs = get_base_loadstore (rhs);

46064

+ tree rhs = get_base_loadstore (arg);

46065

if (rhs)

46066

- ret |= visit_load (stmt, rhs, data);

46067

+ ret |= visit_load (stmt, rhs, arg, data);

46068

}

46069

}

46070

if (visit_addr

46071

@@ -3957,12 +3961,13 @@

46072

&& gimple_call_chain (stmt)

46073

&& TREE_CODE (gimple_call_chain (stmt)) == ADDR_EXPR)

46074

ret |= visit_addr (stmt, TREE_OPERAND (gimple_call_chain (stmt), 0),

46075

- data);

46076

+ gimple_call_chain (stmt), data);

46077

if (visit_addr

46078

&& gimple_call_return_slot_opt_p (stmt)

46079

&& gimple_call_lhs (stmt) != NULL_TREE

46080

&& TREE_ADDRESSABLE (TREE_TYPE (gimple_call_lhs (stmt))))

46081

- ret |= visit_addr (stmt, gimple_call_lhs (stmt), data);

46082

+ ret |= visit_addr (stmt, gimple_call_lhs (stmt),

46083

+ gimple_call_lhs (stmt), data);

46084

}

46085

else if (gimple_code (stmt) == GIMPLE_ASM)

46086

{

46087

@@ -3978,7 +3983,7 @@

46088

tree link = gimple_asm_output_op (stmt, i);

46089

tree op = get_base_loadstore (TREE_VALUE (link));

46090

if (op && visit_store)

46091

- ret |= visit_store (stmt, op, data);

46092

+ ret |= visit_store (stmt, op, TREE_VALUE (link), data);

46093

if (visit_addr)

46094

{

46095

constraint = TREE_STRING_POINTER

46096

@@ -3987,7 +3992,7 @@

46097

parse_output_constraint (&constraint, i, 0, 0, &allows_mem,

46098

&allows_reg, &is_inout);

46099

if (op && !allows_reg && allows_mem)

46100

- ret |= visit_addr (stmt, op, data);

46101

+ ret |= visit_addr (stmt, op, TREE_VALUE (link), data);

46102

}

46103

}

46104

if (visit_load || visit_addr)

46105

@@ -3997,7 +4002,7 @@

46106

tree op = TREE_VALUE (link);

46107

if (visit_addr

46108

&& TREE_CODE (op) == ADDR_EXPR)

46109

- ret |= visit_addr (stmt, TREE_OPERAND (op, 0), data);

46110

+ ret |= visit_addr (stmt, TREE_OPERAND (op, 0), op, data);

46111

else if (visit_load || visit_addr)

46112

{

46113

op = get_base_loadstore (op);

46114

@@ -4004,7 +4009,7 @@

46115

if (op)

46116

{

46117

if (visit_load)

46118

- ret |= visit_load (stmt, op, data);

46119

+ ret |= visit_load (stmt, op, TREE_VALUE (link), data);

46120

if (visit_addr)

46121

{

46122

constraint = TREE_STRING_POINTER

46123

@@ -4013,7 +4018,8 @@

46124

0, oconstraints,

46125

&allows_mem, &allows_reg);

46126

if (!allows_reg && allows_mem)

46127

- ret |= visit_addr (stmt, op, data);

46128

+ ret |= visit_addr (stmt, op, TREE_VALUE (link),

46129

+ data);

46130

}

46131

}

46132

}

46133

@@ -4026,12 +4032,12 @@

46134

{

46135

if (visit_addr

46136

&& TREE_CODE (op) == ADDR_EXPR)

46137

- ret |= visit_addr (stmt, TREE_OPERAND (op, 0), data);

46138

+ ret |= visit_addr (stmt, TREE_OPERAND (op, 0), op, data);

46139

else if (visit_load)

46140

{

46141

- op = get_base_loadstore (op);

46142

- if (op)

46143

- ret |= visit_load (stmt, op, data);

46144

+ tree base = get_base_loadstore (op);

46145

+ if (base)

46146

+ ret |= visit_load (stmt, base, op, data);

46147

}

46148

}

46149

}

46150

@@ -4042,7 +4048,7 @@

46151

{

46152

tree op = PHI_ARG_DEF (stmt, i);

46153

if (TREE_CODE (op) == ADDR_EXPR)

46154

- ret |= visit_addr (stmt, TREE_OPERAND (op, 0), data);

46155

+ ret |= visit_addr (stmt, TREE_OPERAND (op, 0), op, data);

46156

}

46157

}

46158

else if (visit_addr

46159

@@ -4050,7 +4056,7 @@

46160

{

46161

tree op = gimple_goto_dest (stmt);

46162

if (TREE_CODE (op) == ADDR_EXPR)

46163

- ret |= visit_addr (stmt, TREE_OPERAND (op, 0), data);

46164

+ ret |= visit_addr (stmt, TREE_OPERAND (op, 0), op, data);

46165

}

46166

46167

return ret;

46168

@@ -4061,8 +4067,8 @@

46169

46170

bool

46171

walk_stmt_load_store_ops (gimple stmt, void *data,

46172

- bool (*visit_load)(gimple, tree, void *),

46173

- bool (*visit_store)(gimple, tree, void *))

46174

+ walk_stmt_load_store_addr_fn visit_load,

46175

+ walk_stmt_load_store_addr_fn visit_store)

46176

{

46177

return walk_stmt_load_store_addr_ops (stmt, data,

46178

visit_load, visit_store, NULL);

46179

@@ -4071,8 +4077,7 @@

46180

/* Helper for gimple_ior_addresses_taken_1. */

46181

46182

static bool

46183

-gimple_ior_addresses_taken_1 (gimple stmt ATTRIBUTE_UNUSED,

46184

- tree addr, void *data)

46185

+gimple_ior_addresses_taken_1 (gimple, tree addr, tree, void *data)

46186

{

46187

bitmap addresses_taken = (bitmap)data;

46188

addr = get_base_address (addr);

46189

Index: gcc/tree-ssa-structalias.c

46190

===================================================================

46191

--- a/src/gcc/tree-ssa-structalias.c (.../tags/gcc_4_8_2_release)

46192

+++ b/src/gcc/tree-ssa-structalias.c (.../branches/gcc-4_8-branch)

46193

@@ -949,24 +949,27 @@

46194

bitmap_set_bit (result, i);

46195

else

46196

{

46197

- unsigned HOST_WIDE_INT fieldoffset = vi->offset + offset;

46198

+ HOST_WIDE_INT fieldoffset = vi->offset + offset;

46199

+ unsigned HOST_WIDE_INT size = vi->size;

46200

46201

/* If the offset makes the pointer point to before the

46202

variable use offset zero for the field lookup. */

46203

- if (offset < 0

46204

- && fieldoffset > vi->offset)

46205

- fieldoffset = 0;

46206

-

46207

- if (offset != 0)

46208

+ if (fieldoffset < 0)

46209

+ vi = lookup_vi_for_tree (vi->decl);

46210

+ else

46211

vi = first_or_preceding_vi_for_offset (vi, fieldoffset);

46212

46213

- bitmap_set_bit (result, vi->id);

46214

- /* If the result is not exactly at fieldoffset include the next

46215

- field as well. See get_constraint_for_ptr_offset for more

46216

- rationale. */

46217

- if (vi->offset != fieldoffset

46218

- && vi->next != NULL)

46219

- bitmap_set_bit (result, vi->next->id);

46220

+ do

46221

+ {

46222

+ bitmap_set_bit (result, vi->id);

46223

+ if (!vi->next)

46224

+ break;

46225

+

46226

+ /* We have to include all fields that overlap the current field

46227

+ shifted by offset. */

46228

+ vi = vi->next;

46229

+ }

46230

+ while (vi->offset < fieldoffset + size);

46231

}

46232

}

46233

46234

@@ -1607,16 +1610,21 @@

46235

{

46236

varinfo_t v = get_varinfo (j);

46237

HOST_WIDE_INT fieldoffset = v->offset + roffset;

46238

+ unsigned HOST_WIDE_INT size = v->size;

46239

unsigned int t;

46240

46241

if (v->is_full_var)

46242

- fieldoffset = v->offset;

46243

+ ;

46244

else if (roffset != 0)

46245

- v = first_vi_for_offset (v, fieldoffset);

46246

- /* If the access is outside of the variable we can ignore it. */

46247

- if (!v)

46248

- continue;

46249

+ {

46250

+ if (fieldoffset < 0)

46251

+ v = lookup_vi_for_tree (v->decl);

46252

+ else

46253

+ v = first_or_preceding_vi_for_offset (v, fieldoffset);

46254

+ }

46255

46256

+ /* We have to include all fields that overlap the current field

46257

+ shifted by roffset. */

46258

do

46259

{

46260

t = find (v->id);

46261

@@ -1633,16 +1641,13 @@

46262

&& add_graph_edge (graph, lhs, t))

46263

flag |= bitmap_ior_into (sol, get_varinfo (t)->solution);

46264

46265

- /* If the variable is not exactly at the requested offset

46266

- we have to include the next one. */

46267

- if (v->offset == (unsigned HOST_WIDE_INT)fieldoffset

46268

+ if (v->is_full_var

46269

|| v->next == NULL)

46270

break;

46271

46272

v = v->next;

46273

- fieldoffset = v->offset;

46274

}

46275

- while (1);

46276

+ while (v->offset < fieldoffset + size);

46277

}

46278

46279

done:

46280

@@ -1705,15 +1710,20 @@

46281

varinfo_t v = get_varinfo (j);

46282

unsigned int t;

46283

HOST_WIDE_INT fieldoffset = v->offset + loff;

46284

+ unsigned HOST_WIDE_INT size = v->size;

46285

46286

if (v->is_full_var)

46287

- fieldoffset = v->offset;

46288

+ ;

46289

else if (loff != 0)

46290

- v = first_vi_for_offset (v, fieldoffset);

46291

- /* If the access is outside of the variable we can ignore it. */

46292

- if (!v)

46293

- continue;

46294

+ {

46295

+ if (fieldoffset < 0)

46296

+ v = lookup_vi_for_tree (v->decl);

46297

+ else

46298

+ v = first_or_preceding_vi_for_offset (v, fieldoffset);

46299

+ }

46300

46301

+ /* We have to include all fields that overlap the current field

46302

+ shifted by loff. */

46303

do

46304

{

46305

if (v->may_have_pointers)

46306

@@ -1739,16 +1749,13 @@

46307

bitmap_set_bit (changed, t);

46308

}

46309

46310

- /* If the variable is not exactly at the requested offset

46311

- we have to include the next one. */

46312

- if (v->offset == (unsigned HOST_WIDE_INT)fieldoffset

46313

+ if (v->is_full_var

46314

|| v->next == NULL)

46315

break;

46316

46317

v = v->next;

46318

- fieldoffset = v->offset;

46319

}

46320

- while (1);

46321

+ while (v->offset < fieldoffset + size);

46322

}

46323

}

46324

46325

@@ -2997,35 +3004,30 @@

46326

varinfo_t temp;

46327

unsigned HOST_WIDE_INT offset = curr->offset + rhsoffset;

46328

46329

- /* Search the sub-field which overlaps with the

46330

- pointed-to offset. If the result is outside of the variable

46331

- we have to provide a conservative result, as the variable is

46332

- still reachable from the resulting pointer (even though it

46333

- technically cannot point to anything). The last and first

46334

- sub-fields are such conservative results.

46335

- ??? If we always had a sub-field for &object + 1 then

46336

- we could represent this in a more precise way. */

46337

+ /* If curr->offset + rhsoffset is less than zero adjust it. */

46338

if (rhsoffset < 0

46339

&& curr->offset < offset)

46340

offset = 0;

46341

+

46342

+ /* We have to include all fields that overlap the current

46343

+ field shifted by rhsoffset. And we include at least

46344

+ the last or the first field of the variable to represent

46345

+ reachability of off-bound addresses, in particular &object + 1,

46346

+ conservatively correct. */

46347

temp = first_or_preceding_vi_for_offset (curr, offset);

46348

-

46349

- /* If the found variable is not exactly at the pointed to

46350

- result, we have to include the next variable in the

46351

- solution as well. Otherwise two increments by offset / 2

46352

- do not result in the same or a conservative superset

46353

- solution. */

46354

- if (temp->offset != offset

46355

- && temp->next != NULL)

46356

+ c.var = temp->id;

46357

+ c.offset = 0;

46358

+ temp = temp->next;

46359

+ while (temp

46360

+ && temp->offset < offset + curr->size)

46361

{

46362

struct constraint_expr c2;

46363

- c2.var = temp->next->id;

46364

+ c2.var = temp->id;

46365

c2.type = ADDRESSOF;

46366

c2.offset = 0;

46367

results->safe_push (c2);

46368

+ temp = temp->next;

46369

}

46370

- c.var = temp->id;

46371

- c.offset = 0;

46372

}

46373

else

46374

c.offset = rhsoffset;

46375

Index: gcc/gimple.h

46376

===================================================================

46377

--- a/src/gcc/gimple.h (.../tags/gcc_4_8_2_release)

46378

+++ b/src/gcc/gimple.h (.../branches/gcc-4_8-branch)

46379

@@ -176,6 +176,9 @@

46380

/* Nonzero if this statement contains volatile operands. */

46381

unsigned has_volatile_ops : 1;

46382

46383

+ /* Padding to get subcode to 16 bit alignment. */

46384

+ unsigned pad : 1;

46385

+

46386

/* The SUBCODE field can be used for tuple-specific flags for tuples

46387

that do not require subcodes. Note that SUBCODE should be at

46388

least as wide as tree codes, as several tuples store tree codes

46389

@@ -888,13 +891,14 @@

46390

extern alias_set_type gimple_get_alias_set (tree);

46391

extern void count_uses_and_derefs (tree, gimple, unsigned *, unsigned *,

46392

unsigned *);

46393

+typedef bool (*walk_stmt_load_store_addr_fn) (gimple, tree, tree, void *);

46394

extern bool walk_stmt_load_store_addr_ops (gimple, void *,

46395

- bool (*)(gimple, tree, void *),

46396

- bool (*)(gimple, tree, void *),

46397

- bool (*)(gimple, tree, void *));

46398

+ walk_stmt_load_store_addr_fn,

46399

+ walk_stmt_load_store_addr_fn,

46400

+ walk_stmt_load_store_addr_fn);

46401

extern bool walk_stmt_load_store_ops (gimple, void *,

46402

- bool (*)(gimple, tree, void *),

46403

- bool (*)(gimple, tree, void *));

46404

+ walk_stmt_load_store_addr_fn,

46405

+ walk_stmt_load_store_addr_fn);

46406

extern bool gimple_ior_addresses_taken (bitmap, gimple);

46407

extern bool gimple_call_builtin_p (gimple, enum built_in_class);

46408

extern bool gimple_call_builtin_p (gimple, enum built_in_function);

46409

Index: gcc/tree-cfg.c

46410

===================================================================

46411

--- a/src/gcc/tree-cfg.c (.../tags/gcc_4_8_2_release)

46412

+++ b/src/gcc/tree-cfg.c (.../branches/gcc-4_8-branch)

46413

@@ -104,7 +104,6 @@

46414

static void assign_discriminator (location_t, basic_block);

46415

static edge gimple_redirect_edge_and_branch (edge, basic_block);

46416

static edge gimple_try_redirect_by_replacing_jump (edge, basic_block);

46417

-static unsigned int split_critical_edges (void);

46418

46419

/* Various helpers. */

46420

static inline bool stmt_starts_bb_p (gimple, gimple);

46421

@@ -1535,6 +1534,11 @@

46422

46423

FOR_EACH_IMM_USE_STMT (stmt, imm_iter, name)

46424

{

46425

+ /* Mark the block if we change the last stmt in it. */

46426

+ if (cfgcleanup_altered_bbs

46427

+ && stmt_ends_bb_p (stmt))

46428

+ bitmap_set_bit (cfgcleanup_altered_bbs, gimple_bb (stmt)->index);

46429

+

46430

FOR_EACH_IMM_USE_ON_STMT (use, imm_iter)

46431

{

46432

replace_exp (use, val);

46433

@@ -1559,11 +1563,6 @@

46434

gimple orig_stmt = stmt;

46435

size_t i;

46436

46437

- /* Mark the block if we changed the last stmt in it. */

46438

- if (cfgcleanup_altered_bbs

46439

- && stmt_ends_bb_p (stmt))

46440

- bitmap_set_bit (cfgcleanup_altered_bbs, gimple_bb (stmt)->index);

46441

-

46442

/* FIXME. It shouldn't be required to keep TREE_CONSTANT

46443

on ADDR_EXPRs up-to-date on GIMPLE. Propagation will

46444

only change sth from non-invariant to invariant, and only

46445

@@ -3513,11 +3512,10 @@

46446

case PLUS_EXPR:

46447

case MINUS_EXPR:

46448

{

46449

- /* We use regular PLUS_EXPR and MINUS_EXPR for vectors.

46450

- ??? This just makes the checker happy and may not be what is

46451

- intended. */

46452

- if (TREE_CODE (lhs_type) == VECTOR_TYPE

46453

- && POINTER_TYPE_P (TREE_TYPE (lhs_type)))

46454

+ tree lhs_etype = lhs_type;

46455

+ tree rhs1_etype = rhs1_type;

46456

+ tree rhs2_etype = rhs2_type;

46457

+ if (TREE_CODE (lhs_type) == VECTOR_TYPE)

46458

{

46459

if (TREE_CODE (rhs1_type) != VECTOR_TYPE

46460

|| TREE_CODE (rhs2_type) != VECTOR_TYPE)

46461

@@ -3525,22 +3523,13 @@

46462

error ("invalid non-vector operands to vector valued plus");

46463

return true;

46464

}

46465

- lhs_type = TREE_TYPE (lhs_type);

46466

- rhs1_type = TREE_TYPE (rhs1_type);

46467

- rhs2_type = TREE_TYPE (rhs2_type);

46468

- /* PLUS_EXPR is commutative, so we might end up canonicalizing

46469

- the pointer to 2nd place. */

46470

- if (POINTER_TYPE_P (rhs2_type))

46471

- {

46472

- tree tem = rhs1_type;

46473

- rhs1_type = rhs2_type;

46474

- rhs2_type = tem;

46475

- }

46476

- goto do_pointer_plus_expr_check;

46477

+ lhs_etype = TREE_TYPE (lhs_type);

46478

+ rhs1_etype = TREE_TYPE (rhs1_type);

46479

+ rhs2_etype = TREE_TYPE (rhs2_type);

46480

}

46481

- if (POINTER_TYPE_P (lhs_type)

46482

- || POINTER_TYPE_P (rhs1_type)

46483

- || POINTER_TYPE_P (rhs2_type))

46484

+ if (POINTER_TYPE_P (lhs_etype)

46485

+ || POINTER_TYPE_P (rhs1_etype)

46486

+ || POINTER_TYPE_P (rhs2_etype))

46487

{

46488

error ("invalid (pointer) operands to plus/minus");

46489

return true;

46490

@@ -3552,7 +3541,6 @@

46491

46492

case POINTER_PLUS_EXPR:

46493

{

46494

-do_pointer_plus_expr_check:

46495

if (!POINTER_TYPE_P (rhs1_type)

46496

|| !useless_type_conversion_p (lhs_type, rhs1_type)

46497

|| !ptrofftype_p (rhs2_type))

46498

@@ -7658,7 +7646,7 @@

46499

46500

/* Split all critical edges. */

46501

46502

-static unsigned int

46503

+unsigned int

46504

split_critical_edges (void)

46505

{

46506

basic_block bb;

46507

Index: gcc/passes.c

46508

===================================================================

46509

--- a/src/gcc/passes.c (.../tags/gcc_4_8_2_release)

46510

+++ b/src/gcc/passes.c (.../branches/gcc-4_8-branch)

46511

@@ -1398,6 +1398,7 @@

46512

/* After CCP we rewrite no longer addressed locals into SSA

46513

form if possible. */

46514

NEXT_PASS (pass_forwprop);

46515

+ NEXT_PASS (pass_object_sizes);

46516

/* pass_build_alias is a dummy pass that ensures that we

46517

execute TODO_rebuild_alias at this point. */

46518

NEXT_PASS (pass_build_alias);

46519

@@ -1435,7 +1436,6 @@

46520

NEXT_PASS (pass_dce);

46521

NEXT_PASS (pass_forwprop);

46522

NEXT_PASS (pass_phiopt);

46523

- NEXT_PASS (pass_object_sizes);

46524

NEXT_PASS (pass_strlen);

46525

NEXT_PASS (pass_ccp);

46526

/* After CCP we rewrite no longer addressed locals into SSA

46527

Index: gcc/tree-ssa-reassoc.c

46528

===================================================================

46529

--- a/src/gcc/tree-ssa-reassoc.c (.../tags/gcc_4_8_2_release)

46530

+++ b/src/gcc/tree-ssa-reassoc.c (.../branches/gcc-4_8-branch)

46531

@@ -785,8 +785,7 @@

46532

if (opcode == BIT_AND_EXPR)

46533

oe->op = build_zero_cst (TREE_TYPE (oe->op));

46534

else if (opcode == BIT_IOR_EXPR)

46535

- oe->op = build_low_bits_mask (TREE_TYPE (oe->op),

46536

- TYPE_PRECISION (TREE_TYPE (oe->op)));

46537

+ oe->op = build_all_ones_cst (TREE_TYPE (oe->op));

46538

46539

reassociate_stats.ops_eliminated += ops->length () - 1;

46540

ops->truncate (0);

46541

@@ -1980,8 +1979,15 @@

46542

46543

tem = fold_convert_loc (loc, optype, tem);

46544

gsi = gsi_for_stmt (stmt);

46545

- tem = force_gimple_operand_gsi (&gsi, tem, true, NULL_TREE, true,

46546

- GSI_SAME_STMT);

46547

+ /* In rare cases range->exp can be equal to lhs of stmt.

46548

+ In that case we have to insert after the stmt rather then before

46549

+ it. */

46550

+ if (op == range->exp)

46551

+ tem = force_gimple_operand_gsi (&gsi, tem, true, NULL_TREE, false,

46552

+ GSI_SAME_STMT);

46553

+ else

46554

+ tem = force_gimple_operand_gsi (&gsi, tem, true, NULL_TREE, true,

46555

+ GSI_SAME_STMT);

46556

46557

/* If doing inter-bb range test optimization, update the

46558

stmts immediately. Start with changing the first range test

46559

Index: gcc/config/s390/s390.c

46560

===================================================================

46561

--- a/src/gcc/config/s390/s390.c (.../tags/gcc_4_8_2_release)

46562

+++ b/src/gcc/config/s390/s390.c (.../branches/gcc-4_8-branch)

46563

@@ -407,6 +407,65 @@

46564

bytes on a z10 (or higher) CPU. */

46565

#define PREDICT_DISTANCE (TARGET_Z10 ? 384 : 2048)

46566

46567

+static const int s390_hotpatch_trampoline_halfwords_default = 12;

46568

+static const int s390_hotpatch_trampoline_halfwords_max = 1000000;

46569

+static int s390_hotpatch_trampoline_halfwords = -1;

46570

+

46571

+/* Return the argument of the given hotpatch attribute or the default value if

46572

+ no argument is present. */

46573

+

46574

+static inline int

46575

+get_hotpatch_attribute (tree hotpatch_attr)

46576

+{

46577

+ const_tree args;

46578

+

46579

+ args = TREE_VALUE (hotpatch_attr);

46580

+

46581

+ return (args) ?

46582

+ TREE_INT_CST_LOW (TREE_VALUE (args)):

46583

+ s390_hotpatch_trampoline_halfwords_default;

46584

+}

46585

+

46586

+/* Check whether the hotpatch attribute is applied to a function and, if it has

46587

+ an argument, the argument is valid. */

46588

+

46589

+static tree

46590

+s390_handle_hotpatch_attribute (tree *node, tree name, tree args,

46591

+ int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)

46592

+{

46593

+ if (TREE_CODE (*node) != FUNCTION_DECL)

46594

+ {

46595

+ warning (OPT_Wattributes, "%qE attribute only applies to functions",

46596

+ name);

46597

+ *no_add_attrs = true;

46598

+ }

46599

+ else if (args)

46600

+ {

46601

+ tree expr = TREE_VALUE (args);

46602

+

46603

+ if (TREE_CODE (expr) != INTEGER_CST

46604

+ || !INTEGRAL_TYPE_P (TREE_TYPE (expr))

46605

+ || TREE_INT_CST_HIGH (expr) != 0

46606

+ || TREE_INT_CST_LOW (expr) > (unsigned int)

46607

+ s390_hotpatch_trampoline_halfwords_max)

46608

+ {

46609

+ error ("requested %qE attribute is not a non-negative integer"

46610

+ " constant or too large (max. %d)", name,

46611

+ s390_hotpatch_trampoline_halfwords_max);

46612

+ *no_add_attrs = true;

46613

+ }

46614

+ }

46615

+

46616

+ return NULL_TREE;

46617

+}

46618

+

46619

+static const struct attribute_spec s390_attribute_table[] = {

46620

+ { "hotpatch", 0, 1, true, false, false, s390_handle_hotpatch_attribute, false

46621

+ },

46622

+ /* End element. */

46623

+ { NULL, 0, 0, false, false, false, NULL, false }

46624

+};

46625

+

46626

/* Return the alignment for LABEL. We default to the -falign-labels

46627

value except for the literal pool base label. */

46628

int

46629

@@ -883,7 +942,8 @@

46630

{

46631

/* For CCRAWmode put the required cc mask into the second

46632

operand. */

46633

- if (GET_MODE (XVECEXP (*op0, 0, 0)) == CCRAWmode)

46634

+ if (GET_MODE (XVECEXP (*op0, 0, 0)) == CCRAWmode

46635

+ && INTVAL (*op1) >= 0 && INTVAL (*op1) <= 3)

46636

*op1 = gen_rtx_CONST_INT (VOIDmode, 1 << (3 - INTVAL (*op1)));

46637

*op0 = XVECEXP (*op0, 0, 0);

46638

*code = new_code;

46639

@@ -1594,6 +1654,46 @@

46640

static void

46641

s390_option_override (void)

46642

{

46643

+ unsigned int i;

46644

+ cl_deferred_option *opt;

46645

+ vec<cl_deferred_option> *v =

46646

+ (vec<cl_deferred_option> *) s390_deferred_options;

46647

+

46648

+ if (v)

46649

+ FOR_EACH_VEC_ELT (*v, i, opt)

46650

+ {

46651

+ switch (opt->opt_index)

46652

+ {

46653

+ case OPT_mhotpatch:

46654

+ s390_hotpatch_trampoline_halfwords = (opt->value) ?

46655

+ s390_hotpatch_trampoline_halfwords_default : -1;

46656

+ break;

46657

+ case OPT_mhotpatch_:

46658

+ {

46659

+ int val;

46660

+

46661

+ val = integral_argument (opt->arg);

46662

+ if (val == -1)

46663

+ {

46664

+ /* argument is not a plain number */

46665

+ error ("argument to %qs should be a non-negative integer",

46666

+ "-mhotpatch=");

46667

+ break;

46668

+ }

46669

+ else if (val > s390_hotpatch_trampoline_halfwords_max)

46670

+ {

46671

+ error ("argument to %qs is too large (max. %d)",

46672

+ "-mhotpatch=", s390_hotpatch_trampoline_halfwords_max);

46673

+ break;

46674

+ }

46675

+ s390_hotpatch_trampoline_halfwords = val;

46676

+ break;

46677

+ }

46678

+ default:

46679

+ gcc_unreachable ();

46680

+ }

46681

+ }

46682

+

46683

/* Set up function hooks. */

46684

init_machine_status = s390_init_machine_status;

46685

46686

@@ -3015,15 +3115,22 @@

46687

prefer ADDR_REGS. If 'class' is not a superset

46688

of ADDR_REGS, e.g. FP_REGS, reject this reload. */

46689

case CONST:

46690

- /* A larl operand with odd addend will get fixed via secondary

46691

- reload. So don't request it to be pushed into literal

46692

- pool. */

46693

+ /* Symrefs cannot be pushed into the literal pool with -fPIC

46694

+ so we *MUST NOT* return NO_REGS for these cases

46695

+ (s390_cannot_force_const_mem will return true).

46696

+

46697

+ On the other hand we MUST return NO_REGS for symrefs with

46698

+ invalid addend which might have been pushed to the literal

46699

+ pool (no -fPIC). Usually we would expect them to be

46700

+ handled via secondary reload but this does not happen if

46701

+ they are used as literal pool slot replacement in reload

46702

+ inheritance (see emit_input_reload_insns). */

46703

if (TARGET_CPU_ZARCH

46704

&& GET_CODE (XEXP (op, 0)) == PLUS

46705

&& GET_CODE (XEXP (XEXP(op, 0), 0)) == SYMBOL_REF

46706

&& GET_CODE (XEXP (XEXP(op, 0), 1)) == CONST_INT)

46707

{

46708

- if (reg_class_subset_p (ADDR_REGS, rclass))

46709

+ if (flag_pic && reg_class_subset_p (ADDR_REGS, rclass))

46710

return ADDR_REGS;

46711

else

46712

return NO_REGS;

46713

@@ -4683,7 +4790,7 @@

46714

int smode_bsize, mode_bsize;

46715

rtx op, clobber;

46716

46717

- if (bitsize + bitpos > GET_MODE_SIZE (mode))

46718

+ if (bitsize + bitpos > GET_MODE_BITSIZE (mode))

46719

return false;

46720

46721

/* Generate INSERT IMMEDIATE (IILL et al). */

46722

@@ -5311,6 +5418,101 @@

46723

gcc_unreachable ();

46724

}

46725

46726

+/* Returns -1 if the function should not be made hotpatchable. Otherwise it

46727

+ returns a number >= 0 that is the desired size of the hotpatch trampoline

46728

+ in halfwords. */

46729

+

46730

+static int s390_function_num_hotpatch_trampoline_halfwords (tree decl,

46731

+ bool do_warn)

46732

+{

46733

+ tree attr;

46734

+

46735

+ if (DECL_DECLARED_INLINE_P (decl)

46736

+ || DECL_ARTIFICIAL (decl)

46737

+ || MAIN_NAME_P (DECL_NAME (decl)))

46738

+ {

46739

+ /* - Explicitly inlined functions cannot be hotpatched.

46740

+ - Artificial functions need not be hotpatched.

46741

+ - Making the main function hotpatchable is useless. */

46742

+ return -1;

46743

+ }

46744

+ attr = lookup_attribute ("hotpatch", DECL_ATTRIBUTES (decl));

46745

+ if (attr || s390_hotpatch_trampoline_halfwords >= 0)

46746

+ {

46747

+ if (lookup_attribute ("always_inline", DECL_ATTRIBUTES (decl)))

46748

+ {

46749

+ if (do_warn)

46750

+ warning (OPT_Wattributes, "function %qE with the %qs attribute"

46751

+ " is not hotpatchable", DECL_NAME (decl), "always_inline");

46752

+ return -1;

46753

+ }

46754

+ else

46755

+ {

46756

+ return (attr) ?

46757

+ get_hotpatch_attribute (attr) : s390_hotpatch_trampoline_halfwords;

46758

+ }

46759

+ }

46760

+

46761

+ return -1;

46762

+}

46763

+

46764

+/* Hook to determine if one function can safely inline another. */

46765

+

46766

+static bool

46767

+s390_can_inline_p (tree caller, tree callee)

46768

+{

46769

+ if (s390_function_num_hotpatch_trampoline_halfwords (callee, false) >= 0)

46770

+ return false;

46771

+

46772

+ return default_target_can_inline_p (caller, callee);

46773

+}

46774

+

46775

+/* Write the extra assembler code needed to declare a function properly. */

46776

+

46777

+void

46778

+s390_asm_output_function_label (FILE *asm_out_file, const char *fname,

46779

+ tree decl)

46780

+{

46781

+ int hotpatch_trampoline_halfwords = -1;

46782

+

46783

+ if (decl)

46784

+ {

46785

+ hotpatch_trampoline_halfwords =

46786

+ s390_function_num_hotpatch_trampoline_halfwords (decl, true);

46787

+ if (hotpatch_trampoline_halfwords >= 0

46788

+ && decl_function_context (decl) != NULL_TREE)

46789

+ {

46790

+ warning_at (DECL_SOURCE_LOCATION (decl), OPT_mhotpatch,

46791

+ "hotpatching is not compatible with nested functions");

46792

+ hotpatch_trampoline_halfwords = -1;

46793

+ }

46794

+ }

46795

+

46796

+ if (hotpatch_trampoline_halfwords > 0)

46797

+ {

46798

+ int i;

46799

+

46800

+ /* Add a trampoline code area before the function label and initialize it

46801

+ with two-byte nop instructions. This area can be overwritten with code

46802

+ that jumps to a patched version of the function. */

46803

+ for (i = 0; i < hotpatch_trampoline_halfwords; i++)

46804

+ asm_fprintf (asm_out_file, "\tnopr\t%%r7\n");

46805

+ /* Note: The function label must be aligned so that (a) the bytes of the

46806

+ following nop do not cross a cacheline boundary, and (b) a jump address

46807

+ (eight bytes for 64 bit targets, 4 bytes for 32 bit targets) can be

46808

+ stored directly before the label without crossing a cacheline

46809

+ boundary. All this is necessary to make sure the trampoline code can

46810

+ be changed atomically. */

46811

+ }

46812

+

46813

+ ASM_OUTPUT_LABEL (asm_out_file, fname);

46814

+

46815

+ /* Output a four-byte nop if hotpatching is enabled. This can be overwritten

46816

+ atomically with a relative backwards jump to the trampoline area. */

46817

+ if (hotpatch_trampoline_halfwords >= 0)

46818

+ asm_fprintf (asm_out_file, "\tnop\t0\n");

46819

+}

46820

+

46821

/* Output machine-dependent UNSPECs occurring in address constant X

46822

in assembler syntax to stdio stream FILE. Returns true if the

46823

constant X could be recognized, false otherwise. */

46824

@@ -7846,6 +8048,9 @@

46825

{

46826

bb = BASIC_BLOCK (bb_index);

46827

46828

+ if (!bb)

46829

+ continue;

46830

+

46831

FOR_BB_INSNS (bb, insn)

46832

{

46833

rtx ite, cc, pat, target;

46834

@@ -7959,7 +8164,10 @@

46835

if (!result)

46836

return;

46837

46838

- PATTERN (tbegin_insn) = XVECEXP (PATTERN (tbegin_insn), 0, 0);

46839

+ PATTERN (tbegin_insn) = gen_rtx_PARALLEL (VOIDmode,

46840

+ gen_rtvec (2,

46841

+ XVECEXP (PATTERN (tbegin_insn), 0, 0),

46842

+ XVECEXP (PATTERN (tbegin_insn), 0, 1)));

46843

INSN_CODE (tbegin_insn) = -1;

46844

df_insn_rescan (tbegin_insn);

46845

46846

@@ -9568,61 +9776,47 @@

46847

void

46848

s390_expand_tbegin (rtx dest, rtx tdb, rtx retry, bool clobber_fprs_p)

46849

{

46850

- const int CC0 = 1 << 3;

46851

- const int CC1 = 1 << 2;

46852

- const int CC3 = 1 << 0;

46853

- rtx abort_label = gen_label_rtx ();

46854

- rtx leave_label = gen_label_rtx ();

46855

+ rtx retry_plus_two = gen_reg_rtx (SImode);

46856

rtx retry_reg = gen_reg_rtx (SImode);

46857

rtx retry_label = NULL_RTX;

46858

- rtx jump;

46859

- rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1);

46860

46861

if (retry != NULL_RTX)

46862

{

46863

emit_move_insn (retry_reg, retry);

46864

+ emit_insn (gen_addsi3 (retry_plus_two, retry_reg, const2_rtx));

46865

+ emit_insn (gen_addsi3 (retry_reg, retry_reg, const1_rtx));

46866

retry_label = gen_label_rtx ();

46867

emit_label (retry_label);

46868

}

46869

46870

if (clobber_fprs_p)

46871

- emit_insn (gen_tbegin_1 (tdb,

46872

- gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK)));

46873

+ emit_insn (gen_tbegin_1 (gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK), tdb));

46874

else

46875

- emit_insn (gen_tbegin_nofloat_1 (tdb,

46876

- gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK)));

46877

+ emit_insn (gen_tbegin_nofloat_1 (gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK),

46878

+ tdb));

46879

46880

- jump = s390_emit_jump (abort_label,

46881

- gen_rtx_NE (VOIDmode,

46882

- gen_rtx_REG (CCRAWmode, CC_REGNUM),

46883

- gen_rtx_CONST_INT (VOIDmode, CC0)));

46884

-

46885

- JUMP_LABEL (jump) = abort_label;

46886

- LABEL_NUSES (abort_label) = 1;

46887

- add_reg_note (jump, REG_BR_PROB, very_unlikely);

46888

-

46889

- /* Initialize CC return value. */

46890

- emit_move_insn (dest, const0_rtx);

46891

-

46892

- s390_emit_jump (leave_label, NULL_RTX);

46893

- LABEL_NUSES (leave_label) = 1;

46894

- emit_barrier ();

46895

-

46896

- /* Abort handler code. */

46897

-

46898

- emit_label (abort_label);

46899

+ emit_move_insn (dest, gen_rtx_UNSPEC (SImode,

46900

+ gen_rtvec (1, gen_rtx_REG (CCRAWmode,

46901

+ CC_REGNUM)),

46902

+ UNSPEC_CC_TO_INT));

46903

if (retry != NULL_RTX)

46904

{

46905

+ const int CC0 = 1 << 3;

46906

+ const int CC1 = 1 << 2;

46907

+ const int CC3 = 1 << 0;

46908

+ rtx jump;

46909

rtx count = gen_reg_rtx (SImode);

46910

+ rtx leave_label = gen_label_rtx ();

46911

+

46912

+ /* Exit for success and permanent failures. */

46913

jump = s390_emit_jump (leave_label,

46914

gen_rtx_EQ (VOIDmode,

46915

gen_rtx_REG (CCRAWmode, CC_REGNUM),

46916

- gen_rtx_CONST_INT (VOIDmode, CC1 | CC3)));

46917

- LABEL_NUSES (leave_label) = 2;

46918

- add_reg_note (jump, REG_BR_PROB, very_unlikely);

46919

+ gen_rtx_CONST_INT (VOIDmode, CC0 | CC1 | CC3)));

46920

+ LABEL_NUSES (leave_label) = 1;

46921

46922

/* CC2 - transient failure. Perform retry with ppa. */

46923

- emit_move_insn (count, retry);

46924

+ emit_move_insn (count, retry_plus_two);

46925

emit_insn (gen_subsi3 (count, count, retry_reg));

46926

emit_insn (gen_tx_assist (count));

46927

jump = emit_jump_insn (gen_doloop_si64 (retry_label,

46928

@@ -9630,13 +9824,8 @@

46929

retry_reg));

46930

JUMP_LABEL (jump) = retry_label;

46931

LABEL_NUSES (retry_label) = 1;

46932

+ emit_label (leave_label);

46933

}

46934

-

46935

- emit_move_insn (dest, gen_rtx_UNSPEC (SImode,

46936

- gen_rtvec (1, gen_rtx_REG (CCRAWmode,

46937

- CC_REGNUM)),

46938

- UNSPEC_CC_TO_INT));

46939

- emit_label (leave_label);

46940

}

46941

46942

/* Builtins. */

46943

@@ -9674,6 +9863,9 @@

46944

s390_init_builtins (void)

46945

{

46946

tree ftype, uint64_type;

46947

+ tree returns_twice_attr = tree_cons (get_identifier ("returns_twice"),

46948

+ NULL, NULL);

46949

+ tree noreturn_attr = tree_cons (get_identifier ("noreturn"), NULL, NULL);

46950

46951

/* void foo (void) */

46952

ftype = build_function_type_list (void_type_node, NULL_TREE);

46953

@@ -9684,7 +9876,7 @@

46954

ftype = build_function_type_list (void_type_node, integer_type_node,

46955

NULL_TREE);

46956

add_builtin_function ("__builtin_tabort", ftype,

46957

- S390_BUILTIN_TABORT, BUILT_IN_MD, NULL, NULL_TREE);

46958

+ S390_BUILTIN_TABORT, BUILT_IN_MD, NULL, noreturn_attr);

46959

add_builtin_function ("__builtin_tx_assist", ftype,

46960

S390_BUILTIN_TX_ASSIST, BUILT_IN_MD, NULL, NULL_TREE);

46961

46962

@@ -9691,10 +9883,10 @@

46963

/* int foo (void *) */

46964

ftype = build_function_type_list (integer_type_node, ptr_type_node, NULL_TREE);

46965

add_builtin_function ("__builtin_tbegin", ftype, S390_BUILTIN_TBEGIN,

46966

- BUILT_IN_MD, NULL, NULL_TREE);

46967

+ BUILT_IN_MD, NULL, returns_twice_attr);

46968

add_builtin_function ("__builtin_tbegin_nofloat", ftype,

46969

S390_BUILTIN_TBEGIN_NOFLOAT,

46970

- BUILT_IN_MD, NULL, NULL_TREE);

46971

+ BUILT_IN_MD, NULL, returns_twice_attr);

46972

46973

/* int foo (void *, int) */

46974

ftype = build_function_type_list (integer_type_node, ptr_type_node,

46975

@@ -9702,11 +9894,11 @@

46976

add_builtin_function ("__builtin_tbegin_retry", ftype,

46977

S390_BUILTIN_TBEGIN_RETRY,

46978

BUILT_IN_MD,

46979

- NULL, NULL_TREE);

46980

+ NULL, returns_twice_attr);

46981

add_builtin_function ("__builtin_tbegin_retry_nofloat", ftype,

46982

S390_BUILTIN_TBEGIN_RETRY_NOFLOAT,

46983

BUILT_IN_MD,

46984

- NULL, NULL_TREE);

46985

+ NULL, returns_twice_attr);

46986

46987

/* int foo (void) */

46988

ftype = build_function_type_list (integer_type_node, NULL_TREE);

46989

@@ -11622,6 +11814,12 @@

46990

#undef TARGET_CANONICALIZE_COMPARISON

46991

#define TARGET_CANONICALIZE_COMPARISON s390_canonicalize_comparison

46992

46993

+#undef TARGET_ATTRIBUTE_TABLE

46994

+#define TARGET_ATTRIBUTE_TABLE s390_attribute_table

46995

+

46996

+#undef TARGET_CAN_INLINE_P

46997

+#define TARGET_CAN_INLINE_P s390_can_inline_p

46998

+

46999

struct gcc_target targetm = TARGET_INITIALIZER;

47000

47001

#include "gt-s390.h"

47002

Index: gcc/config/s390/s390.h

47003

===================================================================

47004

--- a/src/gcc/config/s390/s390.h (.../tags/gcc_4_8_2_release)

47005

+++ b/src/gcc/config/s390/s390.h (.../branches/gcc-4_8-branch)

47006

@@ -217,7 +217,7 @@

47007

#define STACK_BOUNDARY 64

47008

47009

/* Allocation boundary (in *bits*) for the code of a function. */

47010

-#define FUNCTION_BOUNDARY 32

47011

+#define FUNCTION_BOUNDARY 64

47012

47013

/* There is no point aligning anything to a rounder boundary than this. */

47014

#define BIGGEST_ALIGNMENT 64

47015

@@ -878,6 +878,9 @@

47016

fputc ('\n', (FILE)); \

47017

} while (0)

47018

47019

+#undef ASM_OUTPUT_FUNCTION_LABEL

47020

+#define ASM_OUTPUT_FUNCTION_LABEL(FILE, NAME, DECL) \

47021

+ s390_asm_output_function_label (FILE, NAME, DECL)

47022

47023

/* Miscellaneous parameters. */

47024

47025

Index: gcc/config/s390/s390.md

47026

===================================================================

47027

--- a/src/gcc/config/s390/s390.md (.../tags/gcc_4_8_2_release)

47028

+++ b/src/gcc/config/s390/s390.md (.../branches/gcc-4_8-branch)

47029

@@ -147,6 +147,7 @@

47030

47031

; Transactional Execution support

47032

UNSPECV_TBEGIN

47033

+ UNSPECV_TBEGIN_TDB

47034

UNSPECV_TBEGINC

47035

UNSPECV_TEND

47036

UNSPECV_TABORT

47037

@@ -9896,9 +9897,10 @@

47038

47039

(define_insn "tbegin_1"

47040

[(set (reg:CCRAW CC_REGNUM)

47041

- (unspec_volatile:CCRAW [(match_operand:BLK 0 "memory_operand" "=Q")

47042

- (match_operand 1 "const_int_operand" " D")]

47043

+ (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]

47044

UNSPECV_TBEGIN))

47045

+ (set (match_operand:BLK 1 "memory_operand" "=Q")

47046

+ (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))

47047

(clobber (reg:DF 16))

47048

(clobber (reg:DF 17))

47049

(clobber (reg:DF 18))

47050

@@ -9917,18 +9919,19 @@

47051

(clobber (reg:DF 31))]

47052

; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is

47053

; not supposed to be used for immediates (see genpreds.c).

47054

- "TARGET_HTM && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 0xffff"

47055

- "tbegin\t%0,%x1"

47056

+ "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"

47057

+ "tbegin\t%1,%x0"

47058

[(set_attr "op_type" "SIL")])

47059

47060

; Same as above but without the FPR clobbers

47061

(define_insn "tbegin_nofloat_1"

47062

[(set (reg:CCRAW CC_REGNUM)

47063

- (unspec_volatile:CCRAW [(match_operand:BLK 0 "memory_operand" "=Q")

47064

- (match_operand 1 "const_int_operand" " D")]

47065

- UNSPECV_TBEGIN))]

47066

- "TARGET_HTM && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 0xffff"

47067

- "tbegin\t%0,%x1"

47068

+ (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]

47069

+ UNSPECV_TBEGIN))

47070

+ (set (match_operand:BLK 1 "memory_operand" "=Q")

47071

+ (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))]

47072

+ "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"

47073

+ "tbegin\t%1,%x0"

47074

[(set_attr "op_type" "SIL")])

47075

47076

47077

@@ -10012,15 +10015,12 @@

47078

; Transaction perform processor assist

47079

47080

(define_expand "tx_assist"

47081

- [(set (match_dup 1) (const_int 0))

47082

- (unspec_volatile [(match_operand:SI 0 "register_operand" "")

47083

- (match_dup 1)

47084

+ [(unspec_volatile [(match_operand:SI 0 "register_operand" "")

47085

+ (reg:SI GPR0_REGNUM)

47086

(const_int 1)]

47087

UNSPECV_PPA)]

47088

"TARGET_HTM"

47089

-{

47090

- operands[1] = gen_reg_rtx (SImode);

47091

-})

47092

+ "")

47093

47094

(define_insn "*ppa"

47095

[(unspec_volatile [(match_operand:SI 0 "register_operand" "d")

47096

@@ -10028,5 +10028,5 @@

47097

(match_operand 2 "const_int_operand" "I")]

47098

UNSPECV_PPA)]

47099

"TARGET_HTM && INTVAL (operands[2]) < 16"

47100

- "ppa\t%0,%1,1"

47101

+ "ppa\t%0,%1,%2"

47102

[(set_attr "op_type" "RRF")])

47103

Index: gcc/config/s390/s390.opt

47104

===================================================================

47105

--- a/src/gcc/config/s390/s390.opt (.../tags/gcc_4_8_2_release)

47106

+++ b/src/gcc/config/s390/s390.opt (.../branches/gcc-4_8-branch)

47107

@@ -96,6 +96,14 @@

47108

Target Report RejectNegative Negative(msoft-float) InverseMask(SOFT_FLOAT, HARD_FLOAT)

47109

Enable hardware floating point

47110

47111

+mhotpatch

47112

+Target Report Var(s390_deferred_options) Defer

47113

+Prepend the function label with 12 two-byte Nop instructions, and add a four byte Nop instruction after the label for hotpatching.

47114

+

47115

+mhotpatch=

47116

+Target RejectNegative Report Joined Var(s390_deferred_options) Defer

47117

+Prepend the function label with the given number of two-byte Nop instructions, and add a four byte Nop instruction after the label for hotpatching.

47118

+

47119

mlong-double-128

47120

Target Report RejectNegative Negative(mlong-double-64) Mask(LONG_DOUBLE_128)

47121

Use 128-bit long double

47122

Index: gcc/config/s390/htmxlintrin.h

47123

===================================================================

47124

--- a/src/gcc/config/s390/htmxlintrin.h (.../tags/gcc_4_8_2_release)

47125

+++ b/src/gcc/config/s390/htmxlintrin.h (.../branches/gcc-4_8-branch)

47126

@@ -33,13 +33,20 @@

47127

the IBM XL compiler. For documentation please see the "z/OS XL

47128

C/C++ Programming Guide" publically available on the web. */

47129

47130

-extern __inline long __attribute__((__gnu_inline__, __always_inline__, __artificial__))

47131

+/* FIXME: __TM_simple_begin and __TM_begin should be marked

47132

+ __always_inline__ as well but this currently produces an error

47133

+ since the tbegin builtins are "returns_twice" and setjmp_call_p

47134

+ (calls.c) therefore identifies the functions as calling setjmp.

47135

+ The tree inliner currently refuses to inline functions calling

47136

+ setjmp. */

47137

+

47138

+long

47139

__TM_simple_begin ()

47140

{

47141

return __builtin_tbegin_nofloat (0);

47142

}

47143

47144

-extern __inline long __attribute__((__gnu_inline__, __always_inline__, __artificial__))

47145

+long

47146

__TM_begin (void* const tdb)

47147

{

47148

return __builtin_tbegin_nofloat (tdb);

47149

@@ -78,7 +85,7 @@

47150

if (depth != 0)

47151

return depth;

47152

47153

- if (tdb->format == 0)

47154

+ if (tdb->format != 1)

47155

return 0;

47156

return tdb->nesting_depth;

47157

}

47158

@@ -90,7 +97,7 @@

47159

{

47160

struct __htm_tdb *tdb = (struct __htm_tdb*)tdb_ptr;

47161

47162

- if (tdb->format == 0)

47163

+ if (tdb->format != 1)

47164

return 0;

47165

47166

return !!(tdb->abort_code >= _HTM_FIRST_USER_ABORT_CODE);

47167

@@ -101,7 +108,7 @@

47168

{

47169

struct __htm_tdb *tdb = (struct __htm_tdb*)tdb_ptr;

47170

47171

- if (tdb->format == 0)

47172

+ if (tdb->format != 1)

47173

return 0;

47174

47175

if (tdb->abort_code >= _HTM_FIRST_USER_ABORT_CODE)

47176

@@ -117,7 +124,7 @@

47177

{

47178

struct __htm_tdb *tdb = (struct __htm_tdb*)tdb_ptr;

47179

47180

- return (tdb->format == 0

47181

+ return (tdb->format == 1

47182

&& (tdb->abort_code == 4 /* unfiltered program interruption */

47183

|| tdb->abort_code == 11 /* restricted instruction */));

47184

}

47185

@@ -127,7 +134,7 @@

47186

{

47187

struct __htm_tdb *tdb = (struct __htm_tdb*)tdb_ptr;

47188

47189

- return (tdb->format == 0

47190

+ return (tdb->format == 1

47191

&& (tdb->abort_code == 7 /* fetch overflow */

47192

|| tdb->abort_code == 8 /* store overflow */));

47193

}

47194

@@ -137,7 +144,7 @@

47195

{

47196

struct __htm_tdb *tdb = (struct __htm_tdb*)tdb_ptr;

47197

47198

- return tdb->format == 0 && tdb->abort_code == 13; /* depth exceeded */

47199

+ return tdb->format == 1 && tdb->abort_code == 13; /* depth exceeded */

47200

}

47201

47202

extern __inline long __attribute__((__gnu_inline__, __always_inline__, __artificial__))

47203

@@ -145,7 +152,7 @@

47204

{

47205

struct __htm_tdb *tdb = (struct __htm_tdb*)tdb_ptr;

47206

47207

- return (tdb->format == 0

47208

+ return (tdb->format == 1

47209

&& (tdb->abort_code == 9 /* fetch conflict */

47210

|| tdb->abort_code == 10 /* store conflict */));

47211

}

47212

Index: gcc/config/s390/s390-protos.h

47213

===================================================================

47214

--- a/src/gcc/config/s390/s390-protos.h (.../tags/gcc_4_8_2_release)

47215

+++ b/src/gcc/config/s390/s390-protos.h (.../branches/gcc-4_8-branch)

47216

@@ -110,5 +110,6 @@

47217

extern int s390_branch_condition_mask (rtx);

47218

extern int s390_compare_and_branch_condition_mask (rtx);

47219

extern bool s390_extzv_shift_ok (int, int, unsigned HOST_WIDE_INT);

47220

+extern void s390_asm_output_function_label (FILE *, const char *, tree);

47221

47222

#endif /* RTX_CODE */

47223

Index: gcc/config/sparc/t-rtems

47224

===================================================================

47225

--- a/src/gcc/config/sparc/t-rtems (.../tags/gcc_4_8_2_release)

47226

+++ b/src/gcc/config/sparc/t-rtems (.../branches/gcc-4_8-branch)

47227

@@ -17,6 +17,6 @@

47228

# <http://www.gnu.org/licenses/>.

47229

#

47230

47231

-MULTILIB_OPTIONS = msoft-float mcpu=v8

47232

-MULTILIB_DIRNAMES = soft v8

47233

+MULTILIB_OPTIONS = msoft-float mcpu=v8/mcpu=leon3

47234

+MULTILIB_DIRNAMES = soft v8 leon3

47235

MULTILIB_MATCHES = msoft-float=mno-fpu

47236

Index: gcc/config/sparc/sparc.md

47237

===================================================================

47238

--- a/src/gcc/config/sparc/sparc.md (.../tags/gcc_4_8_2_release)

47239

+++ b/src/gcc/config/sparc/sparc.md (.../branches/gcc-4_8-branch)

47240

@@ -206,7 +206,7 @@

47241

;; 'f' for all DF/TFmode values, including those that are specific to the v8.

47242

47243

;; Attribute for cpu type.

47244

-;; These must match the values for enum processor_type in sparc.h.

47245

+;; These must match the values of the enum processor_type in sparc-opts.h.

47246

(define_attr "cpu"

47247

"v7,

47248

cypress,

47249

@@ -214,6 +214,7 @@

47250

supersparc,

47251

hypersparc,

47252

leon,

47253

+ leon3,

47254

sparclite,

47255

f930,

47256

f934,

47257

@@ -284,7 +285,8 @@

47258

(const_string "none"))

47259

47260

(define_attr "pic" "false,true"

47261

- (symbol_ref "(flag_pic != 0 ? PIC_TRUE : PIC_FALSE)"))

47262

+ (symbol_ref "(flag_pic != 0

47263

+ ? PIC_TRUE : PIC_FALSE)"))

47264

47265

(define_attr "calls_alloca" "false,true"

47266

(symbol_ref "(cfun->calls_alloca != 0

47267

@@ -306,6 +308,10 @@

47268

(symbol_ref "(TARGET_FLAT != 0

47269

? FLAT_TRUE : FLAT_FALSE)"))

47270

47271

+(define_attr "fix_ut699" "false,true"

47272

+ (symbol_ref "(sparc_fix_ut699 != 0

47273

+ ? FIX_UT699_TRUE : FIX_UT699_FALSE)"))

47274

+

47275

;; Length (in # of insns).

47276

;; Beware that setting a length greater or equal to 3 for conditional branches

47277

;; has a side-effect (see output_cbranch and output_v9branch).

47278

@@ -420,32 +426,18 @@

47279

[(set_attr "length" "2")

47280

(set_attr "type" "multi")])

47281

47282

-;; Attributes for instruction and branch scheduling

47283

-(define_attr "tls_call_delay" "false,true"

47284

- (symbol_ref "(tls_call_delay (insn)

47285

- ? TLS_CALL_DELAY_TRUE : TLS_CALL_DELAY_FALSE)"))

47286

-

47287

+;; Attributes for branch scheduling

47288

(define_attr "in_call_delay" "false,true"

47289

- (cond [(eq_attr "type" "uncond_branch,branch,cbcond,uncond_cbcond,call,sibcall,call_no_delay_slot,multi")

47290

- (const_string "false")

47291

- (eq_attr "type" "load,fpload,store,fpstore")

47292

- (if_then_else (eq_attr "length" "1")

47293

- (const_string "true")

47294

- (const_string "false"))]

47295

- (if_then_else (and (eq_attr "length" "1")

47296

- (eq_attr "tls_call_delay" "true"))

47297

- (const_string "true")

47298

- (const_string "false"))))

47299

+ (symbol_ref "(eligible_for_call_delay (insn)

47300

+ ? IN_CALL_DELAY_TRUE : IN_CALL_DELAY_FALSE)"))

47301

47302

-(define_attr "eligible_for_sibcall_delay" "false,true"

47303

+(define_attr "in_sibcall_delay" "false,true"

47304

(symbol_ref "(eligible_for_sibcall_delay (insn)

47305

- ? ELIGIBLE_FOR_SIBCALL_DELAY_TRUE

47306

- : ELIGIBLE_FOR_SIBCALL_DELAY_FALSE)"))

47307

+ ? IN_SIBCALL_DELAY_TRUE : IN_SIBCALL_DELAY_FALSE)"))

47308

47309

-(define_attr "eligible_for_return_delay" "false,true"

47310

+(define_attr "in_return_delay" "false,true"

47311

(symbol_ref "(eligible_for_return_delay (insn)

47312

- ? ELIGIBLE_FOR_RETURN_DELAY_TRUE

47313

- : ELIGIBLE_FOR_RETURN_DELAY_FALSE)"))

47314

+ ? IN_RETURN_DELAY_TRUE : IN_RETURN_DELAY_FALSE)"))

47315

47316

;; ??? !v9: Should implement the notion of predelay slots for floating-point

47317

;; branches. This would allow us to remove the nop always inserted before

47318

@@ -460,41 +452,34 @@

47319

;; because it prevents us from moving back the final store of inner loops.

47320

47321

(define_attr "in_branch_delay" "false,true"

47322

- (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbcond,uncond_cbcond,call,sibcall,call_no_delay_slot,multi")

47323

- (eq_attr "length" "1"))

47324

- (const_string "true")

47325

- (const_string "false")))

47326

+ (cond [(eq_attr "type" "uncond_branch,branch,cbcond,uncond_cbcond,call,sibcall,call_no_delay_slot,multi")

47327

+ (const_string "false")

47328

+ (and (eq_attr "fix_ut699" "true") (eq_attr "type" "load,sload"))

47329

+ (const_string "false")

47330

+ (and (eq_attr "fix_ut699" "true")

47331

+ (and (eq_attr "type" "fpload,fp,fpmove,fpmul,fpdivs,fpsqrts")

47332

+ (eq_attr "fptype" "single")))

47333

+ (const_string "false")

47334

+ (eq_attr "length" "1")

47335

+ (const_string "true")

47336

+ ] (const_string "false")))

47337

47338

-(define_attr "in_uncond_branch_delay" "false,true"

47339

- (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbcond,uncond_cbcond,call,sibcall,call_no_delay_slot,multi")

47340

- (eq_attr "length" "1"))

47341

- (const_string "true")

47342

- (const_string "false")))

47343

-

47344

-(define_attr "in_annul_branch_delay" "false,true"

47345

- (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbcond,uncond_cbcond,call,sibcall,call_no_delay_slot,multi")

47346

- (eq_attr "length" "1"))

47347

- (const_string "true")

47348

- (const_string "false")))

47349

-

47350

(define_delay (eq_attr "type" "call")

47351

[(eq_attr "in_call_delay" "true") (nil) (nil)])

47352

47353

(define_delay (eq_attr "type" "sibcall")

47354

- [(eq_attr "eligible_for_sibcall_delay" "true") (nil) (nil)])

47355

+ [(eq_attr "in_sibcall_delay" "true") (nil) (nil)])

47356

47357

+(define_delay (eq_attr "type" "return")

47358

+ [(eq_attr "in_return_delay" "true") (nil) (nil)])

47359

+

47360

(define_delay (eq_attr "type" "branch")

47361

- [(eq_attr "in_branch_delay" "true")

47362

- (nil) (eq_attr "in_annul_branch_delay" "true")])

47363

+ [(eq_attr "in_branch_delay" "true") (nil) (eq_attr "in_branch_delay" "true")])

47364

47365

(define_delay (eq_attr "type" "uncond_branch")

47366

- [(eq_attr "in_uncond_branch_delay" "true")

47367

- (nil) (nil)])

47368

+ [(eq_attr "in_branch_delay" "true") (nil) (nil)])

47369

47370

-(define_delay (eq_attr "type" "return")

47371

- [(eq_attr "eligible_for_return_delay" "true") (nil) (nil)])

47372

47373

-

47374

;; Include SPARC DFA schedulers

47375

47376

(include "cypress.md")

47377

@@ -5548,7 +5533,7 @@

47378

[(set (match_operand:DF 0 "register_operand" "=e")

47379

(mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "f"))

47380

(float_extend:DF (match_operand:SF 2 "register_operand" "f"))))]

47381

- "(TARGET_V8 || TARGET_V9) && TARGET_FPU"

47382

+ "(TARGET_V8 || TARGET_V9) && TARGET_FPU && !sparc_fix_ut699"

47383

"fsmuld\t%1, %2, %0"

47384

[(set_attr "type" "fpmul")

47385

(set_attr "fptype" "double")])

47386

@@ -5575,22 +5560,39 @@

47387

(match_operand:TF 2 "register_operand" "e")))]

47388

"TARGET_FPU && TARGET_HARD_QUAD"

47389

"fdivq\t%1, %2, %0"

47390

- [(set_attr "type" "fpdivd")])

47391

+ [(set_attr "type" "fpdivs")])

47392

47393

-(define_insn "divdf3"

47394

+(define_expand "divdf3"

47395

[(set (match_operand:DF 0 "register_operand" "=e")

47396

(div:DF (match_operand:DF 1 "register_operand" "e")

47397

(match_operand:DF 2 "register_operand" "e")))]

47398

"TARGET_FPU"

47399

+ "")

47400

+

47401

+(define_insn "*divdf3_nofix"

47402

+ [(set (match_operand:DF 0 "register_operand" "=e")

47403

+ (div:DF (match_operand:DF 1 "register_operand" "e")

47404

+ (match_operand:DF 2 "register_operand" "e")))]

47405

+ "TARGET_FPU && !sparc_fix_ut699"

47406

"fdivd\t%1, %2, %0"

47407

[(set_attr "type" "fpdivd")

47408

(set_attr "fptype" "double")])

47409

47410

+(define_insn "*divdf3_fix"

47411

+ [(set (match_operand:DF 0 "register_operand" "=e")

47412

+ (div:DF (match_operand:DF 1 "register_operand" "e")

47413

+ (match_operand:DF 2 "register_operand" "e")))]

47414

+ "TARGET_FPU && sparc_fix_ut699"

47415

+ "fdivd\t%1, %2, %0\n\tstd\t%0, [%%sp-8]"

47416

+ [(set_attr "type" "fpdivd")

47417

+ (set_attr "fptype" "double")

47418

+ (set_attr "length" "2")])

47419

+

47420

(define_insn "divsf3"

47421

[(set (match_operand:SF 0 "register_operand" "=f")

47422

(div:SF (match_operand:SF 1 "register_operand" "f")

47423

(match_operand:SF 2 "register_operand" "f")))]

47424

- "TARGET_FPU"

47425

+ "TARGET_FPU && !sparc_fix_ut699"

47426

"fdivs\t%1, %2, %0"

47427

[(set_attr "type" "fpdivs")])

47428

47429

@@ -5789,20 +5791,35 @@

47430

(sqrt:TF (match_operand:TF 1 "register_operand" "e")))]

47431

"TARGET_FPU && TARGET_HARD_QUAD"

47432

"fsqrtq\t%1, %0"

47433

- [(set_attr "type" "fpsqrtd")])

47434

+ [(set_attr "type" "fpsqrts")])

47435

47436

-(define_insn "sqrtdf2"

47437

+(define_expand "sqrtdf2"

47438

[(set (match_operand:DF 0 "register_operand" "=e")

47439

(sqrt:DF (match_operand:DF 1 "register_operand" "e")))]

47440

"TARGET_FPU"

47441

+ "")

47442

+

47443

+(define_insn "*sqrtdf2_nofix"

47444

+ [(set (match_operand:DF 0 "register_operand" "=e")

47445

+ (sqrt:DF (match_operand:DF 1 "register_operand" "e")))]

47446

+ "TARGET_FPU && !sparc_fix_ut699"

47447

"fsqrtd\t%1, %0"

47448

[(set_attr "type" "fpsqrtd")

47449

(set_attr "fptype" "double")])

47450

47451

+(define_insn "*sqrtdf2_fix"

47452

+ [(set (match_operand:DF 0 "register_operand" "=e")

47453

+ (sqrt:DF (match_operand:DF 1 "register_operand" "e")))]

47454

+ "TARGET_FPU && sparc_fix_ut699"

47455

+ "fsqrtd\t%1, %0\n\tstd\t%0, [%%sp-8]"

47456

+ [(set_attr "type" "fpsqrtd")

47457

+ (set_attr "fptype" "double")

47458

+ (set_attr "length" "2")])

47459

+

47460

(define_insn "sqrtsf2"

47461

[(set (match_operand:SF 0 "register_operand" "=f")

47462

(sqrt:SF (match_operand:SF 1 "register_operand" "f")))]

47463

- "TARGET_FPU"

47464

+ "TARGET_FPU && !sparc_fix_ut699"

47465

"fsqrts\t%1, %0"

47466

[(set_attr "type" "fpsqrts")])

47467

47468

@@ -5821,19 +5838,6 @@

47469

}

47470

[(set_attr "type" "shift")])

47471

47472

-(define_insn "*ashlsi3_extend"

47473

- [(set (match_operand:DI 0 "register_operand" "=r")

47474

- (zero_extend:DI

47475

- (ashift:SI (match_operand:SI 1 "register_operand" "r")

47476

- (match_operand:SI 2 "arith_operand" "rI"))))]

47477

- "TARGET_ARCH64"

47478

-{

47479

- if (GET_CODE (operands[2]) == CONST_INT)

47480

- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);

47481

- return "sll\t%1, %2, %0";

47482

-}

47483

- [(set_attr "type" "shift")])

47484

-

47485

(define_expand "ashldi3"

47486

[(set (match_operand:DI 0 "register_operand" "=r")

47487

(ashift:DI (match_operand:DI 1 "register_operand" "r")

47488

Index: gcc/config/sparc/t-sparc

47489

===================================================================

47490

--- a/src/gcc/config/sparc/t-sparc (.../tags/gcc_4_8_2_release)

47491

+++ b/src/gcc/config/sparc/t-sparc (.../branches/gcc-4_8-branch)

47492

@@ -23,7 +23,7 @@

47493

insn-codes.h conditions.h output.h $(INSN_ATTR_H) $(FLAGS_H) \

47494

$(FUNCTION_H) $(EXCEPT_H) $(EXPR_H) $(OPTABS_H) $(RECOG_H) \

47495

$(DIAGNOSTIC_CORE_H) $(GGC_H) $(TM_P_H) debug.h $(TARGET_H) \

47496

- $(TARGET_DEF_H) $(COMMON_TARGET_H) $(GIMPLE_H) \

47497

+ $(TARGET_DEF_H) $(COMMON_TARGET_H) $(GIMPLE_H) $(TREE_PASS_H) \

47498

langhooks.h reload.h $(PARAMS_H) $(DF_H) $(OPTS_H) \

47499

gt-sparc.h

47500

47501

Index: gcc/config/sparc/sparc.opt

47502

===================================================================

47503

--- a/src/gcc/config/sparc/sparc.opt (.../tags/gcc_4_8_2_release)

47504

+++ b/src/gcc/config/sparc/sparc.opt (.../branches/gcc-4_8-branch)

47505

@@ -113,6 +113,10 @@

47506

Target

47507

Optimize tail call instructions in assembler and linker

47508

47509

+muser-mode

47510

+Target Report Mask(USER_MODE)

47511

+Do not generate code that can only run in supervisor mode

47512

+

47513

mcpu=

47514

Target RejectNegative Joined Var(sparc_cpu_and_features) Enum(sparc_processor_type) Init(PROCESSOR_V7)

47515

Use features of and schedule code for given CPU

47516

@@ -146,6 +150,9 @@

47517

Enum(sparc_processor_type) String(leon) Value(PROCESSOR_LEON)

47518

47519

EnumValue

47520

+Enum(sparc_processor_type) String(leon3) Value(PROCESSOR_LEON3)

47521

+

47522

+EnumValue

47523

Enum(sparc_processor_type) String(sparclite) Value(PROCESSOR_SPARCLITE)

47524

47525

EnumValue

47526

@@ -201,9 +208,19 @@

47527

Enable workaround for single erratum of AT697F processor

47528

(corresponding to erratum #13 of AT697E processor)

47529

47530

+mfix-ut699

47531

+Target Report RejectNegative Var(sparc_fix_ut699)

47532

+Enable workarounds for the errata of the UT699 processor

47533

+

47534

Mask(LONG_DOUBLE_128)

47535

;; Use 128-bit long double

47536

47537

+Mask(LEON)

47538

+;; Generate code for LEON

47539

+

47540

+Mask(LEON3)

47541

+;; Generate code for LEON3

47542

+

47543

Mask(SPARCLITE)

47544

;; Generate code for SPARClite

47545

47546

Index: gcc/config/sparc/sync.md

47547

===================================================================

47548

--- a/src/gcc/config/sparc/sync.md (.../tags/gcc_4_8_2_release)

47549

+++ b/src/gcc/config/sparc/sync.md (.../branches/gcc-4_8-branch)

47550

@@ -161,7 +161,8 @@

47551

(match_operand:SI 5 "const_int_operand" "") ;; is_weak

47552

(match_operand:SI 6 "const_int_operand" "") ;; mod_s

47553

(match_operand:SI 7 "const_int_operand" "")] ;; mod_f

47554

- "TARGET_V9 && (<MODE>mode != DImode || TARGET_ARCH64 || TARGET_V8PLUS)"

47555

+ "(TARGET_V9 || TARGET_LEON3)

47556

+ && (<MODE>mode != DImode || TARGET_ARCH64 || TARGET_V8PLUS)"

47557

{

47558

sparc_expand_compare_and_swap (operands);

47559

DONE;

47560

@@ -176,7 +177,7 @@

47561

[(match_operand:I48MODE 2 "register_operand" "")

47562

(match_operand:I48MODE 3 "register_operand" "")]

47563

UNSPECV_CAS))])]

47564

- "TARGET_V9"

47565

+ "TARGET_V9 || TARGET_LEON3"

47566

"")

47567

47568

(define_insn "*atomic_compare_and_swap<mode>_1"

47569

@@ -187,10 +188,27 @@

47570

[(match_operand:I48MODE 2 "register_operand" "r")

47571

(match_operand:I48MODE 3 "register_operand" "0")]

47572

UNSPECV_CAS))]

47573

- "TARGET_V9 && (<MODE>mode == SImode || TARGET_ARCH64)"

47574

+ "TARGET_V9 && (<MODE>mode != DImode || TARGET_ARCH64)"

47575

"cas<modesuffix>\t%1, %2, %0"

47576

[(set_attr "type" "multi")])

47577

47578

+(define_insn "*atomic_compare_and_swap_leon3_1"

47579

+ [(set (match_operand:SI 0 "register_operand" "=r")

47580

+ (match_operand:SI 1 "mem_noofs_operand" "+w"))

47581

+ (set (match_dup 1)

47582

+ (unspec_volatile:SI

47583

+ [(match_operand:SI 2 "register_operand" "r")

47584

+ (match_operand:SI 3 "register_operand" "0")]

47585

+ UNSPECV_CAS))]

47586

+ "TARGET_LEON3"

47587

+{

47588

+ if (TARGET_USER_MODE)

47589

+ return "casa\t%1 0xa, %2, %0"; /* ASI for user data space. */

47590

+ else

47591

+ return "casa\t%1 0xb, %2, %0"; /* ASI for supervisor data space. */

47592

+}

47593

+ [(set_attr "type" "multi")])

47594

+

47595

(define_insn "*atomic_compare_and_swapdi_v8plus"

47596

[(set (match_operand:DI 0 "register_operand" "=h")

47597

(match_operand:DI 1 "mem_noofs_operand" "+w"))

47598

@@ -220,7 +238,7 @@

47599

(match_operand:SI 1 "memory_operand" "")

47600

(match_operand:SI 2 "register_operand" "")

47601

(match_operand:SI 3 "const_int_operand" "")]

47602

- "TARGET_V8 || TARGET_V9"

47603

+ "(TARGET_V8 || TARGET_V9) && !sparc_fix_ut699"

47604

{

47605

enum memmodel model = (enum memmodel) INTVAL (operands[3]);

47606

47607

@@ -236,7 +254,7 @@

47608

UNSPECV_SWAP))

47609

(set (match_dup 1)

47610

(match_operand:SI 2 "register_operand" "0"))]

47611

- "TARGET_V8 || TARGET_V9"

47612

+ "(TARGET_V8 || TARGET_V9) && !sparc_fix_ut699"

47613

"swap\t%1, %0"

47614

[(set_attr "type" "multi")])

47615

47616

@@ -244,7 +262,7 @@

47617

[(match_operand:QI 0 "register_operand" "")

47618

(match_operand:QI 1 "memory_operand" "")

47619

(match_operand:SI 2 "const_int_operand" "")]

47620

- ""

47621

+ "!sparc_fix_ut699"

47622

{

47623

enum memmodel model = (enum memmodel) INTVAL (operands[2]);

47624

rtx ret;

47625

@@ -268,6 +286,6 @@

47626

(unspec_volatile:QI [(match_operand:QI 1 "memory_operand" "+m")]

47627

UNSPECV_LDSTUB))

47628

(set (match_dup 1) (const_int -1))]

47629

- ""

47630

+ "!sparc_fix_ut699"

47631

"ldstub\t%1, %0"

47632

[(set_attr "type" "multi")])

47633

Index: gcc/config/sparc/sparc-opts.h

47634

===================================================================

47635

--- a/src/gcc/config/sparc/sparc-opts.h (.../tags/gcc_4_8_2_release)

47636

+++ b/src/gcc/config/sparc/sparc-opts.h (.../branches/gcc-4_8-branch)

47637

@@ -30,6 +30,7 @@

47638

PROCESSOR_SUPERSPARC,

47639

PROCESSOR_HYPERSPARC,

47640

PROCESSOR_LEON,

47641

+ PROCESSOR_LEON3,

47642

PROCESSOR_SPARCLITE,

47643

PROCESSOR_F930,

47644

PROCESSOR_F934,

47645

Index: gcc/config/sparc/sparc-protos.h

47646

===================================================================

47647

--- a/src/gcc/config/sparc/sparc-protos.h (.../tags/gcc_4_8_2_release)

47648

+++ b/src/gcc/config/sparc/sparc-protos.h (.../branches/gcc-4_8-branch)

47649

@@ -84,9 +84,9 @@

47650

extern int mems_ok_for_ldd_peep (rtx, rtx, rtx);

47651

extern int empty_delay_slot (rtx);

47652

extern int emit_cbcond_nop (rtx);

47653

+extern int eligible_for_call_delay (rtx);

47654

extern int eligible_for_return_delay (rtx);

47655

extern int eligible_for_sibcall_delay (rtx);

47656

-extern int tls_call_delay (rtx);

47657

extern int emit_move_sequence (rtx, enum machine_mode);

47658

extern int fp_sethi_p (rtx);

47659

extern int fp_mov_p (rtx);

47660

Index: gcc/config/sparc/sparc.c

47661

===================================================================

47662

--- a/src/gcc/config/sparc/sparc.c (.../tags/gcc_4_8_2_release)

47663

+++ b/src/gcc/config/sparc/sparc.c (.../branches/gcc-4_8-branch)

47664

@@ -52,6 +52,7 @@

47665

#include "params.h"

47666

#include "df.h"

47667

#include "opts.h"

47668

+#include "tree-pass.h"

47669

47670

/* Processor costs */

47671

47672

@@ -226,6 +227,30 @@

47673

};

47674

47675

static const

47676

+struct processor_costs leon3_costs = {

47677

+ COSTS_N_INSNS (1), /* int load */

47678

+ COSTS_N_INSNS (1), /* int signed load */

47679

+ COSTS_N_INSNS (1), /* int zeroed load */

47680

+ COSTS_N_INSNS (1), /* float load */

47681

+ COSTS_N_INSNS (1), /* fmov, fneg, fabs */

47682

+ COSTS_N_INSNS (1), /* fadd, fsub */

47683

+ COSTS_N_INSNS (1), /* fcmp */

47684

+ COSTS_N_INSNS (1), /* fmov, fmovr */

47685

+ COSTS_N_INSNS (1), /* fmul */

47686

+ COSTS_N_INSNS (14), /* fdivs */

47687

+ COSTS_N_INSNS (15), /* fdivd */

47688

+ COSTS_N_INSNS (22), /* fsqrts */

47689

+ COSTS_N_INSNS (23), /* fsqrtd */

47690

+ COSTS_N_INSNS (5), /* imul */

47691

+ COSTS_N_INSNS (5), /* imulX */

47692

+ 0, /* imul bit factor */

47693

+ COSTS_N_INSNS (35), /* idiv */

47694

+ COSTS_N_INSNS (35), /* idivX */

47695

+ COSTS_N_INSNS (1), /* movcc/movr */

47696

+ 0, /* shift penalty */

47697

+};

47698

+

47699

+static const

47700

struct processor_costs sparclet_costs = {

47701

COSTS_N_INSNS (3), /* int load */

47702

COSTS_N_INSNS (3), /* int signed load */

47703

@@ -538,7 +563,6 @@

47704

HOST_WIDE_INT, tree);

47705

static bool sparc_can_output_mi_thunk (const_tree, HOST_WIDE_INT,

47706

HOST_WIDE_INT, const_tree);

47707

-static void sparc_reorg (void);

47708

static struct machine_function * sparc_init_machine_status (void);

47709

static bool sparc_cannot_force_const_mem (enum machine_mode, rtx);

47710

static rtx sparc_tls_get_addr (void);

47711

@@ -680,9 +704,6 @@

47712

#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK

47713

#define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk

47714

47715

-#undef TARGET_MACHINE_DEPENDENT_REORG

47716

-#define TARGET_MACHINE_DEPENDENT_REORG sparc_reorg

47717

-

47718

#undef TARGET_RTX_COSTS

47719

#define TARGET_RTX_COSTS sparc_rtx_costs

47720

#undef TARGET_ADDRESS_COST

47721

@@ -804,6 +825,306 @@

47722

47723

struct gcc_target targetm = TARGET_INITIALIZER;

47724

47725

+/* Return the memory reference contained in X if any, zero otherwise. */

47726

+

47727

+static rtx

47728

+mem_ref (rtx x)

47729

+{

47730

+ if (GET_CODE (x) == SIGN_EXTEND || GET_CODE (x) == ZERO_EXTEND)

47731

+ x = XEXP (x, 0);

47732

+

47733

+ if (MEM_P (x))

47734

+ return x;

47735

+

47736

+ return NULL_RTX;

47737

+}

47738

+

47739

+/* We use a machine specific pass to enable workarounds for errata.

47740

+ We need to have the (essentially) final form of the insn stream in order

47741

+ to properly detect the various hazards. Therefore, this machine specific

47742

+ pass runs as late as possible. The pass is inserted in the pass pipeline

47743

+ at the end of sparc_option_override. */

47744

+

47745

+static bool

47746

+sparc_gate_work_around_errata (void)

47747

+{

47748

+ /* The only errata we handle are those of the AT697F and UT699. */

47749

+ return sparc_fix_at697f != 0 || sparc_fix_ut699 != 0;

47750

+}

47751

+

47752

+static unsigned int

47753

+sparc_do_work_around_errata (void)

47754

+{

47755

+ rtx insn, next;

47756

+

47757

+ /* Force all instructions to be split into their final form. */

47758

+ split_all_insns_noflow ();

47759

+

47760

+ /* Now look for specific patterns in the insn stream. */

47761

+ for (insn = get_insns (); insn; insn = next)

47762

+ {

47763

+ bool insert_nop = false;

47764

+ rtx set;

47765

+

47766

+ /* Look into the instruction in a delay slot. */

47767

+ if (NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == SEQUENCE)

47768

+ insn = XVECEXP (PATTERN (insn), 0, 1);

47769

+

47770

+ /* Look for a single-word load into an odd-numbered FP register. */

47771

+ if (sparc_fix_at697f

47772

+ && NONJUMP_INSN_P (insn)

47773

+ && (set = single_set (insn)) != NULL_RTX

47774

+ && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) == 4

47775

+ && MEM_P (SET_SRC (set))

47776

+ && REG_P (SET_DEST (set))

47777

+ && REGNO (SET_DEST (set)) > 31

47778

+ && REGNO (SET_DEST (set)) % 2 != 0)

47779

+ {

47780

+ /* The wrong dependency is on the enclosing double register. */

47781

+ const unsigned int x = REGNO (SET_DEST (set)) - 1;

47782

+ unsigned int src1, src2, dest;

47783

+ int code;

47784

+

47785

+ next = next_active_insn (insn);

47786

+ if (!next)

47787

+ break;

47788

+ /* If the insn is a branch, then it cannot be problematic. */

47789

+ if (!NONJUMP_INSN_P (next) || GET_CODE (PATTERN (next)) == SEQUENCE)

47790

+ continue;

47791

+

47792

+ extract_insn (next);

47793

+ code = INSN_CODE (next);

47794

+

47795

+ switch (code)

47796

+ {

47797

+ case CODE_FOR_adddf3:

47798

+ case CODE_FOR_subdf3:

47799

+ case CODE_FOR_muldf3:

47800

+ case CODE_FOR_divdf3:

47801

+ dest = REGNO (recog_data.operand[0]);

47802

+ src1 = REGNO (recog_data.operand[1]);

47803

+ src2 = REGNO (recog_data.operand[2]);

47804

+ if (src1 != src2)

47805

+ {

47806

+ /* Case [1-4]:

47807

+ ld [address], %fx+1

47808

+ FPOPd %f{x,y}, %f{y,x}, %f{x,y} */

47809

+ if ((src1 == x || src2 == x)

47810

+ && (dest == src1 || dest == src2))

47811

+ insert_nop = true;

47812

+ }

47813

+ else

47814

+ {

47815

+ /* Case 5:

47816

+ ld [address], %fx+1

47817

+ FPOPd %fx, %fx, %fx */

47818

+ if (src1 == x

47819

+ && dest == src1

47820

+ && (code == CODE_FOR_adddf3 || code == CODE_FOR_muldf3))

47821

+ insert_nop = true;

47822

+ }

47823

+ break;

47824

+

47825

+ case CODE_FOR_sqrtdf2:

47826

+ dest = REGNO (recog_data.operand[0]);

47827

+ src1 = REGNO (recog_data.operand[1]);

47828

+ /* Case 6:

47829

+ ld [address], %fx+1

47830

+ fsqrtd %fx, %fx */

47831

+ if (src1 == x && dest == src1)

47832

+ insert_nop = true;

47833

+ break;

47834

+

47835

+ default:

47836

+ break;

47837

+ }

47838

+ }

47839

+

47840

+ /* Look for a single-word load into an integer register. */

47841

+ else if (sparc_fix_ut699

47842

+ && NONJUMP_INSN_P (insn)

47843

+ && (set = single_set (insn)) != NULL_RTX

47844

+ && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) <= 4

47845

+ && mem_ref (SET_SRC (set)) != NULL_RTX

47846

+ && REG_P (SET_DEST (set))

47847

+ && REGNO (SET_DEST (set)) < 32)

47848

+ {

47849

+ /* There is no problem if the second memory access has a data

47850

+ dependency on the first single-cycle load. */

47851

+ rtx x = SET_DEST (set);

47852

+

47853

+ next = next_active_insn (insn);

47854

+ if (!next)

47855

+ break;

47856

+ /* If the insn is a branch, then it cannot be problematic. */

47857

+ if (!NONJUMP_INSN_P (next) || GET_CODE (PATTERN (next)) == SEQUENCE)

47858

+ continue;

47859

+

47860

+ /* Look for a second memory access to/from an integer register. */

47861

+ if ((set = single_set (next)) != NULL_RTX)

47862

+ {

47863

+ rtx src = SET_SRC (set);

47864

+ rtx dest = SET_DEST (set);

47865

+ rtx mem;

47866

+

47867

+ /* LDD is affected. */

47868

+ if ((mem = mem_ref (src)) != NULL_RTX

47869

+ && REG_P (dest)

47870

+ && REGNO (dest) < 32

47871

+ && !reg_mentioned_p (x, XEXP (mem, 0)))

47872

+ insert_nop = true;

47873

+

47874

+ /* STD is *not* affected. */

47875

+ else if (MEM_P (dest)

47876

+ && GET_MODE_SIZE (GET_MODE (dest)) <= 4

47877

+ && (src == CONST0_RTX (GET_MODE (dest))

47878

+ || (REG_P (src)

47879

+ && REGNO (src) < 32

47880

+ && REGNO (src) != REGNO (x)))

47881

+ && !reg_mentioned_p (x, XEXP (dest, 0)))

47882

+ insert_nop = true;

47883

+ }

47884

+ }

47885

+

47886

+ /* Look for a single-word load/operation into an FP register. */

47887

+ else if (sparc_fix_ut699

47888

+ && NONJUMP_INSN_P (insn)

47889

+ && (set = single_set (insn)) != NULL_RTX

47890

+ && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) == 4

47891

+ && REG_P (SET_DEST (set))

47892

+ && REGNO (SET_DEST (set)) > 31)

47893

+ {

47894

+ /* Number of instructions in the problematic window. */

47895

+ const int n_insns = 4;

47896

+ /* The problematic combination is with the sibling FP register. */

47897

+ const unsigned int x = REGNO (SET_DEST (set));

47898

+ const unsigned int y = x ^ 1;

47899

+ rtx after;

47900

+ int i;

47901

+

47902

+ next = next_active_insn (insn);

47903

+ if (!next)

47904

+ break;

47905

+ /* If the insn is a branch, then it cannot be problematic. */

47906

+ if (!NONJUMP_INSN_P (next) || GET_CODE (PATTERN (next)) == SEQUENCE)

47907

+ continue;

47908

+

47909

+ /* Look for a second load/operation into the sibling FP register. */

47910

+ if (!((set = single_set (next)) != NULL_RTX

47911

+ && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) == 4

47912

+ && REG_P (SET_DEST (set))

47913

+ && REGNO (SET_DEST (set)) == y))

47914

+ continue;

47915

+

47916

+ /* Look for a (possible) store from the FP register in the next N

47917

+ instructions, but bail out if it is again modified or if there

47918

+ is a store from the sibling FP register before this store. */

47919

+ for (after = next, i = 0; i < n_insns; i++)

47920

+ {

47921

+ bool branch_p;

47922

+

47923

+ after = next_active_insn (after);

47924

+ if (!after)

47925

+ break;

47926

+

47927

+ /* This is a branch with an empty delay slot. */

47928

+ if (!NONJUMP_INSN_P (after))

47929

+ {

47930

+ if (++i == n_insns)

47931

+ break;

47932

+ branch_p = true;

47933

+ after = NULL_RTX;

47934

+ }

47935

+ /* This is a branch with a filled delay slot. */

47936

+ else if (GET_CODE (PATTERN (after)) == SEQUENCE)

47937

+ {

47938

+ if (++i == n_insns)

47939

+ break;

47940

+ branch_p = true;

47941

+ after = XVECEXP (PATTERN (after), 0, 1);

47942

+ }

47943

+ /* This is a regular instruction. */

47944

+ else

47945

+ branch_p = false;

47946

+

47947

+ if (after && (set = single_set (after)) != NULL_RTX)

47948

+ {

47949

+ const rtx src = SET_SRC (set);

47950

+ const rtx dest = SET_DEST (set);

47951

+ const unsigned int size = GET_MODE_SIZE (GET_MODE (dest));

47952

+

47953

+ /* If the FP register is again modified before the store,

47954

+ then the store isn't affected. */

47955

+ if (REG_P (dest)

47956

+ && (REGNO (dest) == x

47957

+ || (REGNO (dest) == y && size == 8)))

47958

+ break;

47959

+

47960

+ if (MEM_P (dest) && REG_P (src))

47961

+ {

47962

+ /* If there is a store from the sibling FP register

47963

+ before the store, then the store is not affected. */

47964

+ if (REGNO (src) == y || (REGNO (src) == x && size == 8))

47965

+ break;

47966

+

47967

+ /* Otherwise, the store is affected. */

47968

+ if (REGNO (src) == x && size == 4)

47969

+ {

47970

+ insert_nop = true;

47971

+ break;

47972

+ }

47973

+ }

47974

+ }

47975

+

47976

+ /* If we have a branch in the first M instructions, then we

47977

+ cannot see the (M+2)th instruction so we play safe. */

47978

+ if (branch_p && i <= (n_insns - 2))

47979

+ {

47980

+ insert_nop = true;

47981

+ break;

47982

+ }

47983

+ }

47984

+ }

47985

+

47986

+ else

47987

+ next = NEXT_INSN (insn);

47988

+

47989

+ if (insert_nop)

47990

+ emit_insn_before (gen_nop (), next);

47991

+ }

47992

+

47993

+ return 0;

47994

+}

47995

+

47996

+struct rtl_opt_pass pass_work_around_errata =

47997

+{

47998

+ {

47999

+ RTL_PASS,

48000

+ "errata", /* name */

48001

+ OPTGROUP_NONE, /* optinfo_flags */

48002

+ sparc_gate_work_around_errata, /* gate */

48003

+ sparc_do_work_around_errata, /* execute */

48004

+ NULL, /* sub */

48005

+ NULL, /* next */

48006

+ 0, /* static_pass_number */

48007

+ TV_MACH_DEP, /* tv_id */

48008

+ 0, /* properties_required */

48009

+ 0, /* properties_provided */

48010

+ 0, /* properties_destroyed */

48011

+ 0, /* todo_flags_start */

48012

+ TODO_verify_rtl_sharing, /* todo_flags_finish */

48013

+ }

48014

+};

48015

+

48016

+struct register_pass_info insert_pass_work_around_errata =

48017

+{

48018

+ &pass_work_around_errata.pass, /* pass */

48019

+ "dbr", /* reference_pass_name */

48020

+ 1, /* ref_pass_instance_number */

48021

+ PASS_POS_INSERT_AFTER /* po_op */

48022

+};

48023

+

48024

+/* Helpers for TARGET_DEBUG_OPTIONS. */

48025

static void

48026

dump_target_flag_bits (const int flags)

48027

{

48028

@@ -888,6 +1209,7 @@

48029

{ TARGET_CPU_supersparc, PROCESSOR_SUPERSPARC },

48030

{ TARGET_CPU_hypersparc, PROCESSOR_HYPERSPARC },

48031

{ TARGET_CPU_leon, PROCESSOR_LEON },

48032

+ { TARGET_CPU_leon3, PROCESSOR_LEON3 },

48033

{ TARGET_CPU_sparclite, PROCESSOR_F930 },

48034

{ TARGET_CPU_sparclite86x, PROCESSOR_SPARCLITE86X },

48035

{ TARGET_CPU_sparclet, PROCESSOR_TSC701 },

48036

@@ -902,7 +1224,7 @@

48037

};

48038

const struct cpu_default *def;

48039

/* Table of values for -m{cpu,tune}=. This must match the order of

48040

- the PROCESSOR_* enumeration. */

48041

+ the enum processor_type in sparc-opts.h. */

48042

static struct cpu_table {

48043

const char *const name;

48044

const int disable;

48045

@@ -914,8 +1236,8 @@

48046

/* TI TMS390Z55 supersparc */

48047

{ "supersparc", MASK_ISA, MASK_V8 },

48048

{ "hypersparc", MASK_ISA, MASK_V8|MASK_FPU },

48049

- /* LEON */

48050

- { "leon", MASK_ISA, MASK_V8|MASK_FPU },

48051

+ { "leon", MASK_ISA, MASK_V8|MASK_LEON|MASK_FPU },

48052

+ { "leon3", MASK_ISA, MASK_V8|MASK_LEON3|MASK_FPU },

48053

{ "sparclite", MASK_ISA, MASK_SPARCLITE },

48054

/* The Fujitsu MB86930 is the original sparclite chip, with no FPU. */

48055

{ "f930", MASK_ISA|MASK_FPU, MASK_SPARCLITE },

48056

@@ -1075,6 +1397,9 @@

48057

#ifndef HAVE_AS_SPARC4

48058

& ~MASK_CBCOND

48059

#endif

48060

+#ifndef HAVE_AS_LEON

48061

+ & ~(MASK_LEON | MASK_LEON3)

48062

+#endif

48063

);

48064

48065

/* If -mfpu or -mno-fpu was explicitly used, don't override with

48066

@@ -1164,6 +1489,9 @@

48067

case PROCESSOR_LEON:

48068

sparc_costs = &leon_costs;

48069

break;

48070

+ case PROCESSOR_LEON3:

48071

+ sparc_costs = &leon3_costs;

48072

+ break;

48073

case PROCESSOR_SPARCLET:

48074

case PROCESSOR_TSC701:

48075

sparc_costs = &sparclet_costs;

48076

@@ -1200,6 +1528,10 @@

48077

/* Choose the most relaxed model for the processor. */

48078

else if (TARGET_V9)

48079

sparc_memory_model = SMM_RMO;

48080

+ else if (TARGET_LEON3)

48081

+ sparc_memory_model = SMM_TSO;

48082

+ else if (TARGET_LEON)

48083

+ sparc_memory_model = SMM_SC;

48084

else if (TARGET_V8)

48085

sparc_memory_model = SMM_PSO;

48086

else

48087

@@ -1241,6 +1573,13 @@

48088

pessimizes for double floating-point registers. */

48089

if (!global_options_set.x_flag_ira_share_save_slots)

48090

flag_ira_share_save_slots = 0;

48091

+

48092

+ /* We register a machine specific pass to work around errata, if any.

48093

+ The pass mut be scheduled as late as possible so that we have the

48094

+ (essentially) final form of the insn stream to work on.

48095

+ Registering the pass must be done at start up. It's convenient to

48096

+ do it here. */

48097

+ register_pass (&insert_pass_work_around_errata);

48098

}

48099

48100

/* Miscellaneous utilities. */

48101

@@ -3090,10 +3429,13 @@

48102

/* Return nonzero if TRIAL can go into the call delay slot. */

48103

48104

int

48105

-tls_call_delay (rtx trial)

48106

+eligible_for_call_delay (rtx trial)

48107

{

48108

rtx pat;

48109

48110

+ if (get_attr_in_branch_delay (trial) == IN_BRANCH_DELAY_FALSE)

48111

+ return 0;

48112

+

48113

/* Binutils allows

48114

call __tls_get_addr, %tgd_call (foo)

48115

add %l7, %o0, %o0, %tgd_add (foo)

48116

@@ -3175,11 +3517,7 @@

48117

48118

/* If we have the 'return' instruction, anything that does not use

48119

local or output registers and can go into a delay slot wins. */

48120

- else if (return_p

48121

- && TARGET_V9

48122

- && !epilogue_renumber (&pat, 1)

48123

- && get_attr_in_uncond_branch_delay (trial)

48124

- == IN_UNCOND_BRANCH_DELAY_TRUE)

48125

+ else if (return_p && TARGET_V9 && !epilogue_renumber (&pat, 1))

48126

return 1;

48127

48128

/* The 'restore src1,src2,dest' pattern for SImode. */

48129

@@ -3222,22 +3560,21 @@

48130

int regno;

48131

rtx pat;

48132

48133

- if (GET_CODE (trial) != INSN)

48134

- return 0;

48135

-

48136

- if (get_attr_length (trial) != 1)

48137

- return 0;

48138

-

48139

/* If the function uses __builtin_eh_return, the eh_return machinery

48140

occupies the delay slot. */

48141

if (crtl->calls_eh_return)

48142

return 0;

48143

48144

+ if (get_attr_in_branch_delay (trial) == IN_BRANCH_DELAY_FALSE)

48145

+ return 0;

48146

+

48147

/* In the case of a leaf or flat function, anything can go into the slot. */

48148

if (sparc_leaf_function_p || TARGET_FLAT)

48149

- return

48150

- get_attr_in_uncond_branch_delay (trial) == IN_UNCOND_BRANCH_DELAY_TRUE;

48151

+ return 1;

48152

48153

+ if (!NONJUMP_INSN_P (trial))

48154

+ return 0;

48155

+

48156

pat = PATTERN (trial);

48157

if (GET_CODE (pat) == PARALLEL)

48158

{

48159

@@ -3256,9 +3593,7 @@

48160

if (regno >= 8 && regno < 24)

48161

return 0;

48162

}

48163

- return !epilogue_renumber (&pat, 1)

48164

- && (get_attr_in_uncond_branch_delay (trial)

48165

- == IN_UNCOND_BRANCH_DELAY_TRUE);

48166

+ return !epilogue_renumber (&pat, 1);

48167

}

48168

48169

if (GET_CODE (pat) != SET)

48170

@@ -3278,10 +3613,7 @@

48171

instruction, it can probably go in. But restore will not work

48172

with FP_REGS. */

48173

if (! SPARC_INT_REG_P (regno))

48174

- return (TARGET_V9

48175

- && !epilogue_renumber (&pat, 1)

48176

- && get_attr_in_uncond_branch_delay (trial)

48177

- == IN_UNCOND_BRANCH_DELAY_TRUE);

48178

+ return TARGET_V9 && !epilogue_renumber (&pat, 1);

48179

48180

return eligible_for_restore_insn (trial, true);

48181

}

48182

@@ -3293,10 +3625,10 @@

48183

{

48184

rtx pat;

48185

48186

- if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)

48187

+ if (get_attr_in_branch_delay (trial) == IN_BRANCH_DELAY_FALSE)

48188

return 0;

48189

48190

- if (get_attr_length (trial) != 1)

48191

+ if (!NONJUMP_INSN_P (trial))

48192

return 0;

48193

48194

pat = PATTERN (trial);

48195

@@ -3315,6 +3647,9 @@

48196

return 1;

48197

}

48198

48199

+ if (GET_CODE (pat) != SET)

48200

+ return 0;

48201

+

48202

/* Otherwise, only operations which can be done in tandem with

48203

a `restore' insn can go into the delay slot. */

48204

if (GET_CODE (SET_DEST (pat)) != REG

48205

@@ -10355,7 +10690,8 @@

48206

tmp = e0.add_with_sign (tmp, false, &add1_ovf);

48207

if (tmp.is_negative ())

48208

tmp = tmp.neg_with_overflow (&neg2_ovf);

48209

-

48210

+ else

48211

+ neg2_ovf = false;

48212

result = result.add_with_sign (tmp, false, &add2_ovf);

48213

overflow |= neg1_ovf | neg2_ovf | add1_ovf | add2_ovf;

48214

}

48215

@@ -10897,107 +11233,6 @@

48216

return (vcall_offset >= -32768 || ! fixed_regs[5]);

48217

}

48218

48219

-/* We use the machine specific reorg pass to enable workarounds for errata. */

48220

-

48221

-static void

48222

-sparc_reorg (void)

48223

-{

48224

- rtx insn, next;

48225

-

48226

- /* The only erratum we handle for now is that of the AT697F processor. */

48227

- if (!sparc_fix_at697f)

48228

- return;

48229

-

48230

- /* We need to have the (essentially) final form of the insn stream in order

48231

- to properly detect the various hazards. Run delay slot scheduling. */

48232

- if (optimize > 0 && flag_delayed_branch)

48233

- {

48234

- cleanup_barriers ();

48235

- dbr_schedule (get_insns ());

48236

- }

48237

-

48238

- /* Now look for specific patterns in the insn stream. */

48239

- for (insn = get_insns (); insn; insn = next)

48240

- {

48241

- bool insert_nop = false;

48242

- rtx set;

48243

-

48244

- /* Look for a single-word load into an odd-numbered FP register. */

48245

- if (NONJUMP_INSN_P (insn)

48246

- && (set = single_set (insn)) != NULL_RTX

48247

- && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) == 4

48248

- && MEM_P (SET_SRC (set))

48249

- && REG_P (SET_DEST (set))

48250

- && REGNO (SET_DEST (set)) > 31

48251

- && REGNO (SET_DEST (set)) % 2 != 0)

48252

- {

48253

- /* The wrong dependency is on the enclosing double register. */

48254

- unsigned int x = REGNO (SET_DEST (set)) - 1;

48255

- unsigned int src1, src2, dest;

48256

- int code;

48257

-

48258

- /* If the insn has a delay slot, then it cannot be problematic. */

48259

- next = next_active_insn (insn);

48260

- if (NONJUMP_INSN_P (next) && GET_CODE (PATTERN (next)) == SEQUENCE)

48261

- code = -1;

48262

- else

48263

- {

48264

- extract_insn (next);

48265

- code = INSN_CODE (next);

48266

- }

48267

-

48268

- switch (code)

48269

- {

48270

- case CODE_FOR_adddf3:

48271

- case CODE_FOR_subdf3:

48272

- case CODE_FOR_muldf3:

48273

- case CODE_FOR_divdf3:

48274

- dest = REGNO (recog_data.operand[0]);

48275

- src1 = REGNO (recog_data.operand[1]);

48276

- src2 = REGNO (recog_data.operand[2]);

48277

- if (src1 != src2)

48278

- {

48279

- /* Case [1-4]:

48280

- ld [address], %fx+1

48281

- FPOPd %f{x,y}, %f{y,x}, %f{x,y} */

48282

- if ((src1 == x || src2 == x)

48283

- && (dest == src1 || dest == src2))

48284

- insert_nop = true;

48285

- }

48286

- else

48287

- {

48288

- /* Case 5:

48289

- ld [address], %fx+1

48290

- FPOPd %fx, %fx, %fx */

48291

- if (src1 == x

48292

- && dest == src1

48293

- && (code == CODE_FOR_adddf3 || code == CODE_FOR_muldf3))

48294

- insert_nop = true;

48295

- }

48296

- break;

48297

-

48298

- case CODE_FOR_sqrtdf2:

48299

- dest = REGNO (recog_data.operand[0]);

48300

- src1 = REGNO (recog_data.operand[1]);

48301

- /* Case 6:

48302

- ld [address], %fx+1

48303

- fsqrtd %fx, %fx */

48304

- if (src1 == x && dest == src1)

48305

- insert_nop = true;

48306

- break;

48307

-

48308

- default:

48309

- break;

48310

- }

48311

- }

48312

- else

48313

- next = NEXT_INSN (insn);

48314

-

48315

- if (insert_nop)

48316

- emit_insn_after (gen_nop (), insn);

48317

- }

48318

-}

48319

-

48320

/* How to allocate a 'struct machine_function'. */

48321

48322

static struct machine_function *

48323

Index: gcc/config/sparc/leon.md

48324

===================================================================

48325

--- a/src/gcc/config/sparc/leon.md (.../tags/gcc_4_8_2_release)

48326

+++ b/src/gcc/config/sparc/leon.md (.../branches/gcc-4_8-branch)

48327

@@ -17,40 +17,48 @@

48328

;; along with GCC; see the file COPYING3. If not see

48329

;; <http://www.gnu.org/licenses/>.

48330

48331

+;; Leon is a single-issue processor.

48332

48333

(define_automaton "leon")

48334

48335

-(define_cpu_unit "leon_memory, leon_fpalu" "leon")

48336

-(define_cpu_unit "leon_fpmds" "leon")

48337

-(define_cpu_unit "write_buf" "leon")

48338

+(define_cpu_unit "leon_memory" "leon")

48339

48340

(define_insn_reservation "leon_load" 1

48341

- (and (eq_attr "cpu" "leon")

48342

- (eq_attr "type" "load,sload,fpload"))

48343

+ (and (eq_attr "cpu" "leon") (eq_attr "type" "load,sload"))

48344

"leon_memory")

48345

48346

-(define_insn_reservation "leon_store" 1

48347

- (and (eq_attr "cpu" "leon")

48348

- (eq_attr "type" "store,fpstore"))

48349

- "leon_memory+write_buf")

48350

-

48351

-(define_insn_reservation "leon_fp_alu" 1

48352

- (and (eq_attr "cpu" "leon")

48353

- (eq_attr "type" "fp,fpmove"))

48354

- "leon_fpalu, nothing")

48355

+;; Use a double reservation to work around the load pipeline hazard on UT699.

48356

+(define_insn_reservation "leon3_load" 1

48357

+ (and (eq_attr "cpu" "leon3") (eq_attr "type" "load,sload"))

48358

+ "leon_memory*2")

48359

48360

-(define_insn_reservation "leon_fp_mult" 1

48361

- (and (eq_attr "cpu" "leon")

48362

- (eq_attr "type" "fpmul"))

48363

- "leon_fpmds, nothing")

48364

+(define_insn_reservation "leon_store" 2

48365

+ (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "store"))

48366

+ "leon_memory*2")

48367

48368

-(define_insn_reservation "leon_fp_div" 16

48369

- (and (eq_attr "cpu" "leon")

48370

- (eq_attr "type" "fpdivs,fpdivd"))

48371

- "leon_fpmds, nothing*15")

48372

+;; This describes Gaisler Research's FPU

48373

48374

-(define_insn_reservation "leon_fp_sqrt" 23

48375

- (and (eq_attr "cpu" "leon")

48376

- (eq_attr "type" "fpsqrts,fpsqrtd"))

48377

- "leon_fpmds, nothing*21")

48378

+(define_automaton "grfpu")

48379

48380

+(define_cpu_unit "grfpu_alu" "grfpu")

48381

+(define_cpu_unit "grfpu_ds" "grfpu")

48382

+

48383

+(define_insn_reservation "leon_fp_alu" 4

48384

+ (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fp,fpcmp,fpmul"))

48385

+ "grfpu_alu, nothing*3")

48386

+

48387

+(define_insn_reservation "leon_fp_divs" 16

48388

+ (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fpdivs"))

48389

+ "grfpu_ds*14, nothing*2")

48390

+

48391

+(define_insn_reservation "leon_fp_divd" 17

48392

+ (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fpdivd"))

48393

+ "grfpu_ds*15, nothing*2")

48394

+

48395

+(define_insn_reservation "leon_fp_sqrts" 24

48396

+ (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fpsqrts"))

48397

+ "grfpu_ds*22, nothing*2")

48398

+

48399

+(define_insn_reservation "leon_fp_sqrtd" 25

48400

+ (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fpsqrtd"))

48401

+ "grfpu_ds*23, nothing*2")

48402

Index: gcc/config/sparc/sparc.h

48403

===================================================================

48404

--- a/src/gcc/config/sparc/sparc.h (.../tags/gcc_4_8_2_release)

48405

+++ b/src/gcc/config/sparc/sparc.h (.../branches/gcc-4_8-branch)

48406

@@ -136,21 +136,22 @@

48407

#define TARGET_CPU_supersparc 2

48408

#define TARGET_CPU_hypersparc 3

48409

#define TARGET_CPU_leon 4

48410

-#define TARGET_CPU_sparclite 5

48411

-#define TARGET_CPU_f930 5 /* alias */

48412

-#define TARGET_CPU_f934 5 /* alias */

48413

-#define TARGET_CPU_sparclite86x 6

48414

-#define TARGET_CPU_sparclet 7

48415

-#define TARGET_CPU_tsc701 7 /* alias */

48416

-#define TARGET_CPU_v9 8 /* generic v9 implementation */

48417

-#define TARGET_CPU_sparcv9 8 /* alias */

48418

-#define TARGET_CPU_sparc64 8 /* alias */

48419

-#define TARGET_CPU_ultrasparc 9

48420

-#define TARGET_CPU_ultrasparc3 10

48421

-#define TARGET_CPU_niagara 11

48422

-#define TARGET_CPU_niagara2 12

48423

-#define TARGET_CPU_niagara3 13

48424

-#define TARGET_CPU_niagara4 14

48425

+#define TARGET_CPU_leon3 5

48426

+#define TARGET_CPU_sparclite 6

48427

+#define TARGET_CPU_f930 6 /* alias */

48428

+#define TARGET_CPU_f934 6 /* alias */

48429

+#define TARGET_CPU_sparclite86x 7

48430

+#define TARGET_CPU_sparclet 8

48431

+#define TARGET_CPU_tsc701 8 /* alias */

48432

+#define TARGET_CPU_v9 9 /* generic v9 implementation */

48433

+#define TARGET_CPU_sparcv9 9 /* alias */

48434

+#define TARGET_CPU_sparc64 9 /* alias */

48435

+#define TARGET_CPU_ultrasparc 10

48436

+#define TARGET_CPU_ultrasparc3 11

48437

+#define TARGET_CPU_niagara 12

48438

+#define TARGET_CPU_niagara2 13

48439

+#define TARGET_CPU_niagara3 14

48440

+#define TARGET_CPU_niagara4 15

48441

48442

#if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \

48443

|| TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \

48444

@@ -232,9 +233,10 @@

48445

#define ASM_CPU32_DEFAULT_SPEC ""

48446

#endif

48447

48448

-#if TARGET_CPU_DEFAULT == TARGET_CPU_leon

48449

+#if TARGET_CPU_DEFAULT == TARGET_CPU_leon \

48450

+ || TARGET_CPU_DEFAULT == TARGET_CPU_leon3

48451

#define CPP_CPU32_DEFAULT_SPEC "-D__leon__ -D__sparc_v8__"

48452

-#define ASM_CPU32_DEFAULT_SPEC ""

48453

+#define ASM_CPU32_DEFAULT_SPEC AS_LEON_FLAG

48454

#endif

48455

48456

#endif

48457

@@ -282,6 +284,7 @@

48458

%{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \

48459

%{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \

48460

%{mcpu=leon:-D__leon__ -D__sparc_v8__} \

48461

+%{mcpu=leon3:-D__leon__ -D__sparc_v8__} \

48462

%{mcpu=v9:-D__sparc_v9__} \

48463

%{mcpu=ultrasparc:-D__sparc_v9__} \

48464

%{mcpu=ultrasparc3:-D__sparc_v9__} \

48465

@@ -329,7 +332,8 @@

48466

%{mcpu=v8:-Av8} \

48467

%{mcpu=supersparc:-Av8} \

48468

%{mcpu=hypersparc:-Av8} \

48469

-%{mcpu=leon:-Av8} \

48470

+%{mcpu=leon:" AS_LEON_FLAG "} \

48471

+%{mcpu=leon3:" AS_LEON_FLAG "} \

48472

%{mv8plus:-Av8plus} \

48473

%{mcpu=v9:-Av9} \

48474

%{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \

48475

@@ -1754,6 +1758,12 @@

48476

#define AS_NIAGARA4_FLAG "-Av9" AS_NIAGARA3_FLAG

48477

#endif

48478

48479

+#ifdef HAVE_AS_LEON

48480

+#define AS_LEON_FLAG "-Aleon"

48481

+#else

48482

+#define AS_LEON_FLAG "-Av8"

48483

+#endif

48484

+

48485

/* We use gcc _mcount for profiling. */

48486

#define NO_PROFILE_COUNTERS 0

48487

48488

Index: gcc/config/i386/i386.h

48489

===================================================================

48490

--- a/src/gcc/config/i386/i386.h (.../tags/gcc_4_8_2_release)

48491

+++ b/src/gcc/config/i386/i386.h (.../branches/gcc-4_8-branch)

48492

@@ -197,10 +197,10 @@

48493

48494

/* Macros used in the machine description to test the flags. */

48495

48496

-/* configure can arrange to make this 2, to force a 486. */

48497

+/* configure can arrange to change it. */

48498

48499

#ifndef TARGET_CPU_DEFAULT

48500

-#define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_generic

48501

+#define TARGET_CPU_DEFAULT PROCESSOR_GENERIC32

48502

#endif

48503

48504

#ifndef TARGET_FPMATH_DEFAULT

48505

@@ -591,43 +591,6 @@

48506

/* Target Pragmas. */

48507

#define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas ()

48508

48509

-enum target_cpu_default

48510

-{

48511

- TARGET_CPU_DEFAULT_generic = 0,

48512

-

48513

- TARGET_CPU_DEFAULT_i386,

48514

- TARGET_CPU_DEFAULT_i486,

48515

- TARGET_CPU_DEFAULT_pentium,

48516

- TARGET_CPU_DEFAULT_pentium_mmx,

48517

- TARGET_CPU_DEFAULT_pentiumpro,

48518

- TARGET_CPU_DEFAULT_pentium2,

48519

- TARGET_CPU_DEFAULT_pentium3,

48520

- TARGET_CPU_DEFAULT_pentium4,

48521

- TARGET_CPU_DEFAULT_pentium_m,

48522

- TARGET_CPU_DEFAULT_prescott,

48523

- TARGET_CPU_DEFAULT_nocona,

48524

- TARGET_CPU_DEFAULT_core2,

48525

- TARGET_CPU_DEFAULT_corei7,

48526

- TARGET_CPU_DEFAULT_haswell,

48527

- TARGET_CPU_DEFAULT_atom,

48528

-

48529

- TARGET_CPU_DEFAULT_geode,

48530

- TARGET_CPU_DEFAULT_k6,

48531

- TARGET_CPU_DEFAULT_k6_2,

48532

- TARGET_CPU_DEFAULT_k6_3,

48533

- TARGET_CPU_DEFAULT_athlon,

48534

- TARGET_CPU_DEFAULT_athlon_sse,

48535

- TARGET_CPU_DEFAULT_k8,

48536

- TARGET_CPU_DEFAULT_amdfam10,

48537

- TARGET_CPU_DEFAULT_bdver1,

48538

- TARGET_CPU_DEFAULT_bdver2,

48539

- TARGET_CPU_DEFAULT_bdver3,

48540

- TARGET_CPU_DEFAULT_btver1,

48541

- TARGET_CPU_DEFAULT_btver2,

48542

-

48543

- TARGET_CPU_DEFAULT_max

48544

-};

48545

-

48546

#ifndef CC1_SPEC

48547

#define CC1_SPEC "%(cc1_cpu) "

48548

#endif

48549

@@ -2089,25 +2052,27 @@

48550

with x86-64 medium memory model */

48551

#define DEFAULT_LARGE_SECTION_THRESHOLD 65536

48552

48553

-/* Which processor to tune code generation for. */

48554

+/* Which processor to tune code generation for. These must be in sync

48555

+ with processor_target_table in i386.c. */

48556

48557

enum processor_type

48558

{

48559

- PROCESSOR_I386 = 0, /* 80386 */

48560

+ PROCESSOR_GENERIC32 = 0,

48561

+ PROCESSOR_GENERIC64,

48562

+ PROCESSOR_I386, /* 80386 */

48563

PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */

48564

PROCESSOR_PENTIUM,

48565

PROCESSOR_PENTIUMPRO,

48566

- PROCESSOR_GEODE,

48567

- PROCESSOR_K6,

48568

- PROCESSOR_ATHLON,

48569

PROCESSOR_PENTIUM4,

48570

- PROCESSOR_K8,

48571

PROCESSOR_NOCONA,

48572

PROCESSOR_CORE2,

48573

PROCESSOR_COREI7,

48574

PROCESSOR_HASWELL,

48575

- PROCESSOR_GENERIC32,

48576

- PROCESSOR_GENERIC64,

48577

+ PROCESSOR_ATOM,

48578

+ PROCESSOR_GEODE,

48579

+ PROCESSOR_K6,

48580

+ PROCESSOR_ATHLON,

48581

+ PROCESSOR_K8,

48582

PROCESSOR_AMDFAM10,

48583

PROCESSOR_BDVER1,

48584

PROCESSOR_BDVER2,

48585

@@ -2114,7 +2079,6 @@

48586

PROCESSOR_BDVER3,

48587

PROCESSOR_BTVER1,

48588

PROCESSOR_BTVER2,

48589

- PROCESSOR_ATOM,

48590

PROCESSOR_max

48591

};

48592

48593

Index: gcc/config/i386/i386.md

48594

===================================================================

48595

--- a/src/gcc/config/i386/i386.md (.../tags/gcc_4_8_2_release)

48596

+++ b/src/gcc/config/i386/i386.md (.../branches/gcc-4_8-branch)

48597

@@ -363,6 +363,13 @@

48598

(const_string "unknown")]

48599

(const_string "integer")))

48600

48601

+;; The minimum required alignment of vector mode memory operands of the SSE

48602

+;; (non-VEX/EVEX) instruction in bits, if it is different from

48603

+;; GET_MODE_ALIGNMENT of the operand, otherwise 0. If an instruction has

48604

+;; multiple alternatives, this should be conservative maximum of those minimum

48605

+;; required alignments.

48606

+(define_attr "ssememalign" "" (const_int 0))

48607

+

48608

;; The (bounding maximum) length of an instruction immediate.

48609

(define_attr "length_immediate" ""

48610

(cond [(eq_attr "type" "incdec,setcc,icmov,str,lea,other,multi,idiv,leave,

48611

@@ -1570,7 +1577,7 @@

48612

split_double_mode (DImode, &operands[1], 1, &operands[2], &operands[3]);

48613

48614

operands[1] = gen_lowpart (DImode, operands[2]);

48615

- operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,

48616

+ operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (Pmode, stack_pointer_rtx,

48617

GEN_INT (4)));

48618

})

48619

48620

@@ -1587,7 +1594,7 @@

48621

split_double_mode (DImode, &operands[1], 1, &operands[2], &operands[3]);

48622

48623

operands[1] = gen_lowpart (DImode, operands[2]);

48624

- operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,

48625

+ operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (Pmode, stack_pointer_rtx,

48626

GEN_INT (4)));

48627

})

48628

48629

@@ -2715,7 +2722,20 @@

48630

"reload_completed"

48631

[(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (match_dup 2)))

48632

(set (mem:SF (reg:P SP_REG)) (match_dup 1))]

48633

- "operands[2] = GEN_INT (-GET_MODE_SIZE (<P:MODE>mode));")

48634

+{

48635

+ rtx op = XEXP (operands[0], 0);

48636

+ if (GET_CODE (op) == PRE_DEC)

48637

+ {

48638

+ gcc_assert (!TARGET_64BIT);

48639

+ op = GEN_INT (-4);

48640

+ }

48641

+ else

48642

+ {

48643

+ op = XEXP (XEXP (op, 1), 1);

48644

+ gcc_assert (CONST_INT_P (op));

48645

+ }

48646

+ operands[2] = op;

48647

+})

48648

48649

(define_split

48650

[(set (match_operand:SF 0 "push_operand")

48651

@@ -5443,6 +5463,12 @@

48652

mode = SImode;

48653

48654

ix86_split_lea_for_addr (curr_insn, operands, mode);

48655

+

48656

+ /* Zero-extend return register to DImode for zero-extended addresses. */

48657

+ if (mode != <MODE>mode)

48658

+ emit_insn (gen_zero_extendsidi2

48659

+ (operands[0], gen_lowpart (mode, operands[0])));

48660

+

48661

DONE;

48662

}

48663

[(set_attr "type" "lea")

48664

@@ -6589,7 +6615,7 @@

48665

(set_attr "use_carry" "1")

48666

(set_attr "mode" "<MODE>")])

48667

48668

-;; Overflow setting add and subtract instructions

48669

+;; Overflow setting add instructions

48670

48671

(define_insn "*add<mode>3_cconly_overflow"

48672

[(set (reg:CCC FLAGS_REG)

48673

@@ -6604,43 +6630,31 @@

48674

[(set_attr "type" "alu")

48675

(set_attr "mode" "<MODE>")])

48676

48677

-(define_insn "*sub<mode>3_cconly_overflow"

48678

+(define_insn "*add<mode>3_cc_overflow"

48679

[(set (reg:CCC FLAGS_REG)

48680

(compare:CCC

48681

- (minus:SWI

48682

- (match_operand:SWI 0 "nonimmediate_operand" "<r>m,<r>")

48683

- (match_operand:SWI 1 "<general_operand>" "<r><i>,<r>m"))

48684

- (match_dup 0)))]

48685

- ""

48686

- "cmp{<imodesuffix>}\t{%1, %0|%0, %1}"

48687

- [(set_attr "type" "icmp")

48688

- (set_attr "mode" "<MODE>")])

48689

-

48690

-(define_insn "*<plusminus_insn><mode>3_cc_overflow"

48691

- [(set (reg:CCC FLAGS_REG)

48692

- (compare:CCC

48693

- (plusminus:SWI

48694

- (match_operand:SWI 1 "nonimmediate_operand" "<comm>0,0")

48695

+ (plus:SWI

48696

+ (match_operand:SWI 1 "nonimmediate_operand" "%0,0")

48697

(match_operand:SWI 2 "<general_operand>" "<r><i>,<r>m"))

48698

(match_dup 1)))

48699

(set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")

48700

- (plusminus:SWI (match_dup 1) (match_dup 2)))]

48701

- "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"

48702

- "<plusminus_mnemonic>{<imodesuffix>}\t{%2, %0|%0, %2}"

48703

+ (plus:SWI (match_dup 1) (match_dup 2)))]

48704

+ "ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"

48705

+ "add{<imodesuffix>}\t{%2, %0|%0, %2}"

48706

[(set_attr "type" "alu")

48707

(set_attr "mode" "<MODE>")])

48708

48709

-(define_insn "*<plusminus_insn>si3_zext_cc_overflow"

48710

+(define_insn "*addsi3_zext_cc_overflow"

48711

[(set (reg:CCC FLAGS_REG)

48712

(compare:CCC

48713

- (plusminus:SI

48714

- (match_operand:SI 1 "nonimmediate_operand" "<comm>0")

48715

+ (plus:SI

48716

+ (match_operand:SI 1 "nonimmediate_operand" "%0")

48717

(match_operand:SI 2 "x86_64_general_operand" "rme"))

48718

(match_dup 1)))

48719

(set (match_operand:DI 0 "register_operand" "=r")

48720

- (zero_extend:DI (plusminus:SI (match_dup 1) (match_dup 2))))]

48721

- "TARGET_64BIT && ix86_binary_operator_ok (<CODE>, SImode, operands)"

48722

- "<plusminus_mnemonic>{l}\t{%2, %k0|%k0, %2}"

48723

+ (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]

48724

+ "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"

48725

+ "add{l}\t{%2, %k0|%k0, %2}"

48726

[(set_attr "type" "alu")

48727

(set_attr "mode" "SI")])

48728

48729

@@ -8012,7 +8026,18 @@

48730

(const_int 0)))

48731

(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,rm")

48732

(and:DI (match_dup 1) (match_dup 2)))]

48733

- "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)

48734

+ "TARGET_64BIT

48735

+ && ix86_match_ccmode

48736

+ (insn,

48737

+ /* If we are going to emit andl instead of andq, and the operands[2]

48738

+ constant might have the SImode sign bit set, make sure the sign

48739

+ flag isn't tested, because the instruction will set the sign flag

48740

+ based on bit 31 rather than bit 63. If it isn't CONST_INT,

48741

+ conservatively assume it might have bit 31 set. */

48742

+ (satisfies_constraint_Z (operands[2])

48743

+ && (!CONST_INT_P (operands[2])

48744

+ || val_signbit_known_set_p (SImode, INTVAL (operands[2]))))

48745

+ ? CCZmode : CCNOmode)

48746

&& ix86_binary_operator_ok (AND, DImode, operands)"

48747

"@

48748

and{l}\t{%k2, %k0|%k0, %k2}

48749

@@ -17569,7 +17594,13 @@

48750

(define_insn "trap"

48751

[(trap_if (const_int 1) (const_int 6))]

48752

""

48753

- { return ASM_SHORT "0x0b0f"; }

48754

+{

48755

+#ifdef HAVE_AS_IX86_UD2

48756

+ return "ud2";

48757

+#else

48758

+ return ASM_SHORT "0x0b0f";

48759

+#endif

48760

+}

48761

[(set_attr "length" "2")])

48762

48763

(define_expand "prefetch"

48764

Index: gcc/config/i386/f16cintrin.h

48765

===================================================================

48766

--- a/src/gcc/config/i386/f16cintrin.h (.../tags/gcc_4_8_2_release)

48767

+++ b/src/gcc/config/i386/f16cintrin.h (.../branches/gcc-4_8-branch)

48768

@@ -35,7 +35,7 @@

48769

extern __inline float __attribute__((__gnu_inline__, __always_inline__, __artificial__))

48770

_cvtsh_ss (unsigned short __S)

48771

{

48772

- __v8hi __H = __extension__ (__v8hi){ __S, 0, 0, 0, 0, 0, 0, 0 };

48773

+ __v8hi __H = __extension__ (__v8hi){ (short) __S, 0, 0, 0, 0, 0, 0, 0 };

48774

__v4sf __A = __builtin_ia32_vcvtph2ps (__H);

48775

return __builtin_ia32_vec_ext_v4sf (__A, 0);

48776

}

48777

Index: gcc/config/i386/t-rtems

48778

===================================================================

48779

--- a/src/gcc/config/i386/t-rtems (.../tags/gcc_4_8_2_release)

48780

+++ b/src/gcc/config/i386/t-rtems (.../branches/gcc-4_8-branch)

48781

@@ -17,11 +17,10 @@

48782

# <http://www.gnu.org/licenses/>.

48783

#

48784

48785

-MULTILIB_OPTIONS = mtune=i486/mtune=pentium/mtune=pentiumpro \

48786

-msoft-float

48787

+MULTILIB_OPTIONS = mtune=i486/mtune=pentium/mtune=pentiumpro msoft-float

48788

MULTILIB_DIRNAMES= m486 mpentium mpentiumpro soft-float

48789

-MULTILIB_MATCHES = msoft-float=mno-m80387

48790

-MULTILIB_MATCHES += mtune?pentium=mtune?k6 mtune?pentiumpro=mtune?mathlon

48791

+MULTILIB_MATCHES = msoft-float=mno-80387

48792

+MULTILIB_MATCHES += mtune?pentium=mtune?k6 mtune?pentiumpro=mtune?athlon

48793

MULTILIB_EXCEPTIONS = \

48794

mtune=pentium/*msoft-float* \

48795

mtune=pentiumpro/*msoft-float*

48796

Index: gcc/config/i386/winnt.c

48797

===================================================================

48798

--- a/src/gcc/config/i386/winnt.c (.../tags/gcc_4_8_2_release)

48799

+++ b/src/gcc/config/i386/winnt.c (.../branches/gcc-4_8-branch)

48800

@@ -547,8 +547,9 @@

48801

sets 'discard' characteristic, rather than telling linker

48802

to warn of size or content mismatch, so do the same. */

48803

bool discard = (flags & SECTION_CODE)

48804

- || lookup_attribute ("selectany",

48805

- DECL_ATTRIBUTES (decl));

48806

+ || (TREE_CODE (decl) != IDENTIFIER_NODE

48807

+ && lookup_attribute ("selectany",

48808

+ DECL_ATTRIBUTES (decl)));

48809

fprintf (asm_out_file, "\t.linkonce %s\n",

48810

(discard ? "discard" : "same_size"));

48811

}

48812

Index: gcc/config/i386/sse.md

48813

===================================================================

48814

--- a/src/gcc/config/i386/sse.md (.../tags/gcc_4_8_2_release)

48815

+++ b/src/gcc/config/i386/sse.md (.../branches/gcc-4_8-branch)

48816

@@ -605,6 +605,7 @@

48817

}

48818

[(set_attr "type" "ssemov")

48819

(set_attr "movu" "1")

48820

+ (set_attr "ssememalign" "8")

48821

(set_attr "prefix" "maybe_vex")

48822

(set (attr "mode")

48823

(cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")

48824

@@ -634,6 +635,7 @@

48825

}

48826

[(set_attr "type" "ssemov")

48827

(set_attr "movu" "1")

48828

+ (set_attr "ssememalign" "8")

48829

(set_attr "prefix" "maybe_vex")

48830

(set (attr "mode")

48831

(cond [(ior (match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")

48832

@@ -663,6 +665,7 @@

48833

}

48834

[(set_attr "type" "ssemov")

48835

(set_attr "movu" "1")

48836

+ (set_attr "ssememalign" "8")

48837

(set (attr "prefix_data16")

48838

(if_then_else

48839

(match_test "TARGET_AVX")

48840

@@ -696,6 +699,7 @@

48841

}

48842

[(set_attr "type" "ssemov")

48843

(set_attr "movu" "1")

48844

+ (set_attr "ssememalign" "8")

48845

(set (attr "prefix_data16")

48846

(if_then_else

48847

(match_test "TARGET_AVX")

48848

@@ -721,6 +725,7 @@

48849

"%vlddqu\t{%1, %0|%0, %1}"

48850

[(set_attr "type" "ssemov")

48851

(set_attr "movu" "1")

48852

+ (set_attr "ssememalign" "8")

48853

(set (attr "prefix_data16")

48854

(if_then_else

48855

(match_test "TARGET_AVX")

48856

@@ -1001,6 +1006,7 @@

48857

vrcpss\t{%1, %2, %0|%0, %2, %1}"

48858

[(set_attr "isa" "noavx,avx")

48859

(set_attr "type" "sse")

48860

+ (set_attr "ssememalign" "32")

48861

(set_attr "atom_sse_attr" "rcp")

48862

(set_attr "btver2_sse_attr" "rcp")

48863

(set_attr "prefix" "orig,vex")

48864

@@ -1089,6 +1095,7 @@

48865

vrsqrtss\t{%1, %2, %0|%0, %2, %1}"

48866

[(set_attr "isa" "noavx,avx")

48867

(set_attr "type" "sse")

48868

+ (set_attr "ssememalign" "32")

48869

(set_attr "prefix" "orig,vex")

48870

(set_attr "mode" "SF")])

48871

48872

@@ -2844,6 +2851,7 @@

48873

"%vcvtdq2pd\t{%1, %0|%0, %q1}"

48874

[(set_attr "type" "ssecvt")

48875

(set_attr "prefix" "maybe_vex")

48876

+ (set_attr "ssememalign" "64")

48877

(set_attr "mode" "V2DF")])

48878

48879

(define_insn "avx_cvtpd2dq256"

48880

@@ -3572,6 +3580,7 @@

48881

%vmovhps\t{%2, %0|%0, %2}"

48882

[(set_attr "isa" "noavx,avx,noavx,avx,*")

48883

(set_attr "type" "ssemov")

48884

+ (set_attr "ssememalign" "64")

48885

(set_attr "prefix" "orig,vex,orig,vex,maybe_vex")

48886

(set_attr "mode" "V4SF,V4SF,V2SF,V2SF,V2SF")])

48887

48888

@@ -3617,6 +3626,7 @@

48889

%vmovlps\t{%2, %H0|%H0, %2}"

48890

[(set_attr "isa" "noavx,avx,noavx,avx,*")

48891

(set_attr "type" "ssemov")

48892

+ (set_attr "ssememalign" "64")

48893

(set_attr "prefix" "orig,vex,orig,vex,maybe_vex")

48894

(set_attr "mode" "V4SF,V4SF,V2SF,V2SF,V2SF")])

48895

48896

@@ -3941,6 +3951,7 @@

48897

%vmovhlps\t{%1, %d0|%d0, %1}

48898

%vmovlps\t{%H1, %d0|%d0, %H1}"

48899

[(set_attr "type" "ssemov")

48900

+ (set_attr "ssememalign" "64")

48901

(set_attr "prefix" "maybe_vex")

48902

(set_attr "mode" "V2SF,V4SF,V2SF")])

48903

48904

@@ -3980,6 +3991,7 @@

48905

%vmovlps\t{%2, %H0|%H0, %2}"

48906

[(set_attr "isa" "noavx,avx,noavx,avx,*")

48907

(set_attr "type" "ssemov")

48908

+ (set_attr "ssememalign" "64")

48909

(set_attr "prefix" "orig,vex,orig,vex,maybe_vex")

48910

(set_attr "mode" "V2SF,V2SF,V4SF,V4SF,V2SF")])

48911

48912

@@ -4033,6 +4045,7 @@

48913

%vmovlps\t{%2, %0|%0, %2}"

48914

[(set_attr "isa" "noavx,avx,noavx,avx,*")

48915

(set_attr "type" "sseshuf,sseshuf,ssemov,ssemov,ssemov")

48916

+ (set_attr "ssememalign" "64")

48917

(set_attr "length_immediate" "1,1,*,*,*")

48918

(set_attr "prefix" "orig,vex,orig,vex,maybe_vex")

48919

(set_attr "mode" "V4SF,V4SF,V2SF,V2SF,V2SF")])

48920

@@ -4642,7 +4655,8 @@

48921

vmovlpd\t{%H1, %2, %0|%0, %2, %H1}

48922

%vmovhpd\t{%1, %0|%0, %1}"

48923

[(set_attr "isa" "noavx,avx,sse3,noavx,avx,*")

48924

- (set_attr "type" "sselog,sselog,sselog,ssemov,ssemov,ssemov")

48925

+ (set_attr "type" "sselog,sselog,sselog,ssemov,ssemov,ssemov")

48926

+ (set_attr "ssememalign" "64")

48927

(set_attr "prefix_data16" "*,*,*,1,*,1")

48928

(set_attr "prefix" "orig,vex,maybe_vex,orig,vex,maybe_vex")

48929

(set_attr "mode" "V2DF,V2DF,DF,V1DF,V1DF,V1DF")])

48930

@@ -4744,6 +4758,7 @@

48931

%vmovlpd\t{%2, %H0|%H0, %2}"

48932

[(set_attr "isa" "noavx,avx,sse3,noavx,avx,*")

48933

(set_attr "type" "sselog,sselog,sselog,ssemov,ssemov,ssemov")

48934

+ (set_attr "ssememalign" "64")

48935

(set_attr "prefix_data16" "*,*,*,1,*,1")

48936

(set_attr "prefix" "orig,vex,maybe_vex,orig,vex,maybe_vex")

48937

(set_attr "mode" "V2DF,V2DF,DF,V1DF,V1DF,V1DF")])

48938

@@ -4982,6 +4997,7 @@

48939

movhlps\t{%1, %0|%0, %1}

48940

movlps\t{%H1, %0|%0, %H1}"

48941

[(set_attr "type" "ssemov")

48942

+ (set_attr "ssememalign" "64")

48943

(set_attr "mode" "V2SF,V4SF,V2SF")])

48944

48945

;; Avoid combining registers from different units in a single alternative,

48946

@@ -5077,6 +5093,7 @@

48947

#"

48948

[(set_attr "isa" "noavx,avx,noavx,avx,*,*,*")

48949

(set_attr "type" "ssemov,ssemov,sselog,sselog,ssemov,fmov,imov")

48950

+ (set_attr "ssememalign" "64")

48951

(set_attr "prefix_data16" "1,*,*,*,*,*,*")

48952

(set_attr "prefix" "orig,vex,orig,vex,*,*,*")

48953

(set_attr "mode" "V1DF,V1DF,V2DF,V2DF,DF,DF,DF")])

48954

@@ -5145,6 +5162,7 @@

48955

(const_string "imov")

48956

]

48957

(const_string "ssemov")))

48958

+ (set_attr "ssememalign" "64")

48959

(set_attr "prefix_data16" "*,1,*,*,*,*,1,*,*,*,*")

48960

(set_attr "length_immediate" "*,*,*,*,*,1,*,*,*,*,*")

48961

(set_attr "prefix" "maybe_vex,orig,vex,orig,vex,orig,orig,vex,*,*,*")

48962

@@ -5189,6 +5207,7 @@

48963

(const_string "1")

48964

(const_string "*")))

48965

(set_attr "length_immediate" "*,*,*,*,*,1,*,*,*")

48966

+ (set_attr "ssememalign" "64")

48967

(set_attr "prefix" "orig,vex,orig,vex,maybe_vex,orig,orig,vex,maybe_vex")

48968

(set_attr "mode" "DF,DF,V1DF,V1DF,V1DF,V2DF,V1DF,V1DF,V1DF")])

48969

48970

@@ -8736,6 +8755,7 @@

48971

"TARGET_SSE4_1"

48972

"%vpmov<extsuffix>bw\t{%1, %0|%0, %q1}"

48973

[(set_attr "type" "ssemov")

48974

+ (set_attr "ssememalign" "64")

48975

(set_attr "prefix_extra" "1")

48976

(set_attr "prefix" "maybe_vex")

48977

(set_attr "mode" "TI")])

48978

@@ -8766,6 +8786,7 @@

48979

"TARGET_SSE4_1"

48980

"%vpmov<extsuffix>bd\t{%1, %0|%0, %k1}"

48981

[(set_attr "type" "ssemov")

48982

+ (set_attr "ssememalign" "32")

48983

(set_attr "prefix_extra" "1")

48984

(set_attr "prefix" "maybe_vex")

48985

(set_attr "mode" "TI")])

48986

@@ -8791,6 +8812,7 @@

48987

"TARGET_SSE4_1"

48988

"%vpmov<extsuffix>wd\t{%1, %0|%0, %q1}"

48989

[(set_attr "type" "ssemov")

48990

+ (set_attr "ssememalign" "64")

48991

(set_attr "prefix_extra" "1")

48992

(set_attr "prefix" "maybe_vex")

48993

(set_attr "mode" "TI")])

48994

@@ -8818,6 +8840,7 @@

48995

"TARGET_SSE4_1"

48996

"%vpmov<extsuffix>bq\t{%1, %0|%0, %w1}"

48997

[(set_attr "type" "ssemov")

48998

+ (set_attr "ssememalign" "16")

48999

(set_attr "prefix_extra" "1")

49000

(set_attr "prefix" "maybe_vex")

49001

(set_attr "mode" "TI")])

49002

@@ -8845,6 +8868,7 @@

49003

"TARGET_SSE4_1"

49004

"%vpmov<extsuffix>wq\t{%1, %0|%0, %k1}"

49005

[(set_attr "type" "ssemov")

49006

+ (set_attr "ssememalign" "32")

49007

(set_attr "prefix_extra" "1")

49008

(set_attr "prefix" "maybe_vex")

49009

(set_attr "mode" "TI")])

49010

@@ -8868,6 +8892,7 @@

49011

"TARGET_SSE4_1"

49012

"%vpmov<extsuffix>dq\t{%1, %0|%0, %q1}"

49013

[(set_attr "type" "ssemov")

49014

+ (set_attr "ssememalign" "64")

49015

(set_attr "prefix_extra" "1")

49016

(set_attr "prefix" "maybe_vex")

49017

(set_attr "mode" "TI")])

49018

@@ -9151,6 +9176,7 @@

49019

[(set_attr "type" "sselog")

49020

(set_attr "prefix_data16" "1")

49021

(set_attr "prefix_extra" "1")

49022

+ (set_attr "ssememalign" "8")

49023

(set_attr "length_immediate" "1")

49024

(set_attr "memory" "none,load")

49025

(set_attr "mode" "TI")])

49026

@@ -9213,6 +9239,7 @@

49027

[(set_attr "type" "sselog")

49028

(set_attr "prefix_data16" "1")

49029

(set_attr "prefix_extra" "1")

49030

+ (set_attr "ssememalign" "8")

49031

(set_attr "length_immediate" "1")

49032

(set_attr "memory" "load")

49033

(set_attr "mode" "TI")])

49034

@@ -9240,6 +9267,7 @@

49035

(set_attr "prefix_data16" "1")

49036

(set_attr "prefix_extra" "1")

49037

(set_attr "prefix" "maybe_vex")

49038

+ (set_attr "ssememalign" "8")

49039

(set_attr "length_immediate" "1")

49040

(set_attr "btver2_decode" "vector")

49041

(set_attr "memory" "none,load")

49042

@@ -9267,6 +9295,7 @@

49043

[(set_attr "type" "sselog")

49044

(set_attr "prefix_data16" "1")

49045

(set_attr "prefix_extra" "1")

49046

+ (set_attr "ssememalign" "8")

49047

(set_attr "length_immediate" "1")

49048

(set_attr "prefix" "maybe_vex")

49049

(set_attr "btver2_decode" "vector")

49050

@@ -9293,6 +9322,7 @@

49051

[(set_attr "type" "sselog")

49052

(set_attr "prefix_data16" "1")

49053

(set_attr "prefix_extra" "1")

49054

+ (set_attr "ssememalign" "8")

49055

(set_attr "length_immediate" "1")

49056

(set_attr "memory" "none,load,none,load")

49057

(set_attr "btver2_decode" "vector,vector,vector,vector")

49058

@@ -9346,6 +9376,7 @@

49059

[(set_attr "type" "sselog")

49060

(set_attr "prefix_data16" "1")

49061

(set_attr "prefix_extra" "1")

49062

+ (set_attr "ssememalign" "8")

49063

(set_attr "length_immediate" "1")

49064

(set_attr "memory" "none,load")

49065

(set_attr "mode" "TI")])

49066

@@ -9399,6 +9430,7 @@

49067

[(set_attr "type" "sselog")

49068

(set_attr "prefix_data16" "1")

49069

(set_attr "prefix_extra" "1")

49070

+ (set_attr "ssememalign" "8")

49071

(set_attr "length_immediate" "1")

49072

(set_attr "memory" "load")

49073

(set_attr "mode" "TI")])

49074

@@ -9421,6 +9453,7 @@

49075

[(set_attr "type" "sselog")

49076

(set_attr "prefix_data16" "1")

49077

(set_attr "prefix_extra" "1")

49078

+ (set_attr "ssememalign" "8")

49079

(set_attr "length_immediate" "1")

49080

(set_attr "prefix" "maybe_vex")

49081

(set_attr "memory" "none,load")

49082

@@ -9445,6 +9478,7 @@

49083

[(set_attr "type" "sselog")

49084

(set_attr "prefix_data16" "1")

49085

(set_attr "prefix_extra" "1")

49086

+ (set_attr "ssememalign" "8")

49087

(set_attr "length_immediate" "1")

49088

(set_attr "prefix" "maybe_vex")

49089

(set_attr "memory" "none,load")

49090

@@ -9469,6 +9503,7 @@

49091

[(set_attr "type" "sselog")

49092

(set_attr "prefix_data16" "1")

49093

(set_attr "prefix_extra" "1")

49094

+ (set_attr "ssememalign" "8")

49095

(set_attr "length_immediate" "1")

49096

(set_attr "memory" "none,load,none,load")

49097

(set_attr "prefix" "maybe_vex")

49098

@@ -10213,7 +10248,6 @@

49099

[(set_attr "type" "ssecvt1")

49100

(set_attr "mode" "<MODE>")])

49101

49102

-;; scalar insns

49103

(define_expand "xop_vmfrcz<mode>2"

49104

[(set (match_operand:VF_128 0 "register_operand")

49105

(vec_merge:VF_128

49106

@@ -10220,14 +10254,12 @@

49107

(unspec:VF_128

49108

[(match_operand:VF_128 1 "nonimmediate_operand")]

49109

UNSPEC_FRCZ)

49110

- (match_dup 3)

49111

+ (match_dup 2)

49112

(const_int 1)))]

49113

"TARGET_XOP"

49114

-{

49115

- operands[3] = CONST0_RTX (<MODE>mode);

49116

-})

49117

+ "operands[2] = CONST0_RTX (<MODE>mode);")

49118

49119

-(define_insn "*xop_vmfrcz_<mode>"

49120

+(define_insn "*xop_vmfrcz<mode>2"

49121

[(set (match_operand:VF_128 0 "register_operand" "=x")

49122

(vec_merge:VF_128

49123

(unspec:VF_128

49124

Index: gcc/config/i386/xopintrin.h

49125

===================================================================

49126

--- a/src/gcc/config/i386/xopintrin.h (.../tags/gcc_4_8_2_release)

49127

+++ b/src/gcc/config/i386/xopintrin.h (.../branches/gcc-4_8-branch)

49128

@@ -745,13 +745,17 @@

49129

extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))

49130

_mm_frcz_ss (__m128 __A, __m128 __B)

49131

{

49132

- return (__m128) __builtin_ia32_vfrczss ((__v4sf)__A, (__v4sf)__B);

49133

+ return (__m128) __builtin_ia32_movss ((__v4sf)__A,

49134

+ (__v4sf)

49135

+ __builtin_ia32_vfrczss ((__v4sf)__B));

49136

}

49137

49138

extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))

49139

_mm_frcz_sd (__m128d __A, __m128d __B)

49140

{

49141

- return (__m128d) __builtin_ia32_vfrczsd ((__v2df)__A, (__v2df)__B);

49142

+ return (__m128d) __builtin_ia32_movsd ((__v2df)__A,

49143

+ (__v2df)

49144

+ __builtin_ia32_vfrczsd ((__v2df)__B));

49145

}

49146

49147

extern __inline __m256 __attribute__((__gnu_inline__, __always_inline__, __artificial__))

49148

Index: gcc/config/i386/driver-i386.c

49149

===================================================================

49150

--- a/src/gcc/config/i386/driver-i386.c (.../tags/gcc_4_8_2_release)

49151

+++ b/src/gcc/config/i386/driver-i386.c (.../branches/gcc-4_8-branch)

49152

@@ -126,6 +126,18 @@

49153

case 0x0c:

49154

level1->sizekb = 16; level1->assoc = 4; level1->line = 32;

49155

break;

49156

+ case 0x0d:

49157

+ level1->sizekb = 16; level1->assoc = 4; level1->line = 64;

49158

+ break;

49159

+ case 0x0e:

49160

+ level1->sizekb = 24; level1->assoc = 6; level1->line = 64;

49161

+ break;

49162

+ case 0x21:

49163

+ level2->sizekb = 256; level2->assoc = 8; level2->line = 64;

49164

+ break;

49165

+ case 0x24:

49166

+ level2->sizekb = 1024; level2->assoc = 16; level2->line = 64;

49167

+ break;

49168

case 0x2c:

49169

level1->sizekb = 32; level1->assoc = 8; level1->line = 64;

49170

break;

49171

@@ -162,6 +174,9 @@

49172

case 0x45:

49173

level2->sizekb = 2048; level2->assoc = 4; level2->line = 32;

49174

break;

49175

+ case 0x48:

49176

+ level2->sizekb = 3072; level2->assoc = 12; level2->line = 64;

49177

+ break;

49178

case 0x49:

49179

if (xeon_mp)

49180

break;

49181

@@ -203,6 +218,9 @@

49182

case 0x7f:

49183

level2->sizekb = 512; level2->assoc = 2; level2->line = 64;

49184

break;

49185

+ case 0x80:

49186

+ level2->sizekb = 512; level2->assoc = 8; level2->line = 64;

49187

+ break;

49188

case 0x82:

49189

level2->sizekb = 256; level2->assoc = 8; level2->line = 32;

49190

break;

49191

@@ -470,6 +488,28 @@

49192

has_xsaveopt = eax & bit_XSAVEOPT;

49193

}

49194

49195

+ /* Check cpuid level of extended features. */

49196

+ __cpuid (0x80000000, ext_level, ebx, ecx, edx);

49197

+

49198

+ if (ext_level > 0x80000000)

49199

+ {

49200

+ __cpuid (0x80000001, eax, ebx, ecx, edx);

49201

+

49202

+ has_lahf_lm = ecx & bit_LAHF_LM;

49203

+ has_sse4a = ecx & bit_SSE4a;

49204

+ has_abm = ecx & bit_ABM;

49205

+ has_lwp = ecx & bit_LWP;

49206

+ has_fma4 = ecx & bit_FMA4;

49207

+ has_xop = ecx & bit_XOP;

49208

+ has_tbm = ecx & bit_TBM;

49209

+ has_lzcnt = ecx & bit_LZCNT;

49210

+ has_prfchw = ecx & bit_PRFCHW;

49211

+

49212

+ has_longmode = edx & bit_LM;

49213

+ has_3dnowp = edx & bit_3DNOWP;

49214

+ has_3dnow = edx & bit_3DNOW;

49215

+ }

49216

+

49217

/* Get XCR_XFEATURE_ENABLED_MASK register with xgetbv. */

49218

#define XCR_XFEATURE_ENABLED_MASK 0x0

49219

#define XSTATE_FP 0x1

49220

@@ -488,33 +528,12 @@

49221

has_avx2 = 0;

49222

has_fma = 0;

49223

has_fma4 = 0;

49224

+ has_f16c = 0;

49225

has_xop = 0;

49226

has_xsave = 0;

49227

has_xsaveopt = 0;

49228

}

49229

49230

- /* Check cpuid level of extended features. */

49231

- __cpuid (0x80000000, ext_level, ebx, ecx, edx);

49232

-

49233

- if (ext_level > 0x80000000)

49234

- {

49235

- __cpuid (0x80000001, eax, ebx, ecx, edx);

49236

-

49237

- has_lahf_lm = ecx & bit_LAHF_LM;

49238

- has_sse4a = ecx & bit_SSE4a;

49239

- has_abm = ecx & bit_ABM;

49240

- has_lwp = ecx & bit_LWP;

49241

- has_fma4 = ecx & bit_FMA4;

49242

- has_xop = ecx & bit_XOP;

49243

- has_tbm = ecx & bit_TBM;

49244

- has_lzcnt = ecx & bit_LZCNT;

49245

- has_prfchw = ecx & bit_PRFCHW;

49246

-

49247

- has_longmode = edx & bit_LM;

49248

- has_3dnowp = edx & bit_3DNOWP;

49249

- has_3dnow = edx & bit_3DNOW;

49250

- }

49251

-

49252

if (!arch)

49253

{

49254

if (vendor == signature_AMD_ebx

49255

Index: gcc/config/i386/i386.c

49256

===================================================================

49257

--- a/src/gcc/config/i386/i386.c (.../tags/gcc_4_8_2_release)

49258

+++ b/src/gcc/config/i386/i386.c (.../branches/gcc-4_8-branch)

49259

@@ -1378,7 +1378,7 @@

49260

8, /* MMX or SSE register to integer */

49261

8, /* size of l1 cache. */

49262

1024, /* size of l2 cache. */

49263

- 128, /* size of prefetch block */

49264

+ 64, /* size of prefetch block */

49265

8, /* number of parallel prefetches */

49266

1, /* Branch cost */

49267

COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */

49268

@@ -1894,10 +1894,10 @@

49269

49270

49271

/* X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL */

49272

- m_COREI7 | m_AMDFAM10 | m_BDVER | m_BTVER,

49273

+ m_COREI7 | m_HASWELL | m_AMDFAM10 | m_BDVER | m_BTVER,

49274

49275

/* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL */

49276

- m_COREI7 | m_BDVER,

49277

+ m_COREI7 | m_HASWELL| m_BDVER,

49278

49279

/* X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL */

49280

m_BDVER ,

49281

@@ -2409,6 +2409,7 @@

49282

/* Processor target table, indexed by processor number */

49283

struct ptt

49284

{

49285

+ const char *const name; /* processor name */

49286

const struct processor_costs *cost; /* Processor costs */

49287

const int align_loop; /* Default alignments. */

49288

const int align_loop_max_skip;

49289

@@ -2417,67 +2418,32 @@

49290

const int align_func;

49291

};

49292

49293

+/* This table must be in sync with enum processor_type in i386.h. */

49294

static const struct ptt processor_target_table[PROCESSOR_max] =

49295

{

49296

- {&i386_cost, 4, 3, 4, 3, 4},

49297

- {&i486_cost, 16, 15, 16, 15, 16},

49298

- {&pentium_cost, 16, 7, 16, 7, 16},

49299

- {&pentiumpro_cost, 16, 15, 16, 10, 16},

49300

- {&geode_cost, 0, 0, 0, 0, 0},

49301

- {&k6_cost, 32, 7, 32, 7, 32},

49302

- {&athlon_cost, 16, 7, 16, 7, 16},

49303

- {&pentium4_cost, 0, 0, 0, 0, 0},

49304

- {&k8_cost, 16, 7, 16, 7, 16},

49305

- {&nocona_cost, 0, 0, 0, 0, 0},

49306

- /* Core 2 */

49307

- {&core_cost, 16, 10, 16, 10, 16},

49308

- /* Core i7 */

49309

- {&core_cost, 16, 10, 16, 10, 16},

49310

- /* Core avx2 */

49311

- {&core_cost, 16, 10, 16, 10, 16},

49312

- {&generic32_cost, 16, 7, 16, 7, 16},

49313

- {&generic64_cost, 16, 10, 16, 10, 16},

49314

- {&amdfam10_cost, 32, 24, 32, 7, 32},

49315

- {&bdver1_cost, 16, 10, 16, 7, 11},

49316

- {&bdver2_cost, 16, 10, 16, 7, 11},

49317

- {&bdver3_cost, 16, 10, 16, 7, 11},

49318

- {&btver1_cost, 16, 10, 16, 7, 11},

49319

- {&btver2_cost, 16, 10, 16, 7, 11},

49320

- {&atom_cost, 16, 15, 16, 7, 16}

49321

+ {"generic", &generic32_cost, 16, 7, 16, 7, 16},

49322

+ {"generic", &generic64_cost, 16, 10, 16, 10, 16},

49323

+ {"i386", &i386_cost, 4, 3, 4, 3, 4},

49324

+ {"i486", &i486_cost, 16, 15, 16, 15, 16},

49325

+ {"pentium", &pentium_cost, 16, 7, 16, 7, 16},

49326

+ {"pentiumpro", &pentiumpro_cost, 16, 15, 16, 10, 16},

49327

+ {"pentium4", &pentium4_cost, 0, 0, 0, 0, 0},

49328

+ {"nocona", &nocona_cost, 0, 0, 0, 0, 0},

49329

+ {"core2", &core_cost, 16, 10, 16, 10, 16},

49330

+ {"corei7", &core_cost, 16, 10, 16, 10, 16},

49331

+ {"core-avx2", &core_cost, 16, 10, 16, 10, 16},

49332

+ {"atom", &atom_cost, 16, 15, 16, 7, 16},

49333

+ {"geode", &geode_cost, 0, 0, 0, 0, 0},

49334

+ {"k6", &k6_cost, 32, 7, 32, 7, 32},

49335

+ {"athlon", &athlon_cost, 16, 7, 16, 7, 16},

49336

+ {"k8", &k8_cost, 16, 7, 16, 7, 16},

49337

+ {"amdfam10", &amdfam10_cost, 32, 24, 32, 7, 32},

49338

+ {"bdver1", &bdver1_cost, 16, 10, 16, 7, 11},

49339

+ {"bdver2", &bdver2_cost, 16, 10, 16, 7, 11},

49340

+ {"bdver3", &bdver3_cost, 16, 10, 16, 7, 11},

49341

+ {"btver1", &btver1_cost, 16, 10, 16, 7, 11},

49342

+ {"btver2", &btver2_cost, 16, 10, 16, 7, 11}

49343

};

49344

-

49345

-static const char *const cpu_names[TARGET_CPU_DEFAULT_max] =

49346

-{

49347

- "generic",

49348

- "i386",

49349

- "i486",

49350

- "pentium",

49351

- "pentium-mmx",

49352

- "pentiumpro",

49353

- "pentium2",

49354

- "pentium3",

49355

- "pentium4",

49356

- "pentium-m",

49357

- "prescott",

49358

- "nocona",

49359

- "core2",

49360

- "corei7",

49361

- "core-avx2",

49362

- "atom",

49363

- "geode",

49364

- "k6",

49365

- "k6-2",

49366

- "k6-3",

49367

- "athlon",

49368

- "athlon-4",

49369

- "k8",

49370

- "amdfam10",

49371

- "bdver1",

49372

- "bdver2",

49373

- "bdver3",

49374

- "btver1",

49375

- "btver2"

49376

-};

49377

49378

static bool

49379

gate_insert_vzeroupper (void)

49380

@@ -2983,7 +2949,7 @@

49381

{"bdver3", PROCESSOR_BDVER3, CPU_BDVER3,

49382

PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3

49383

49384

- | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX

49385

49386

49387

| PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE

49388

| PTA_XSAVEOPT},

49389

@@ -3125,7 +3091,8 @@

49390

ix86_tune_string = ix86_arch_string;

49391

if (!ix86_tune_string)

49392

{

49393

- ix86_tune_string = cpu_names[TARGET_CPU_DEFAULT];

49394

+ ix86_tune_string

49395

+ = processor_target_table[TARGET_CPU_DEFAULT].name;

49396

ix86_tune_defaulted = 1;

49397

}

49398

49399

@@ -4078,19 +4045,15 @@

49400

= ix86_target_string (ptr->x_ix86_isa_flags, ptr->x_target_flags,

49401

NULL, NULL, ptr->x_ix86_fpmath, false);

49402

49403

+ gcc_assert (ptr->arch < PROCESSOR_max);

49404

fprintf (file, "%*sarch = %d (%s)\n",

49405

indent, "",

49406

- ptr->arch,

49407

- ((ptr->arch < TARGET_CPU_DEFAULT_max)

49408

- ? cpu_names[ptr->arch]

49409

- : "<unknown>"));

49410

+ ptr->arch, processor_target_table[ptr->arch].name);

49411

49412

+ gcc_assert (ptr->tune < PROCESSOR_max);

49413

fprintf (file, "%*stune = %d (%s)\n",

49414

indent, "",

49415

- ptr->tune,

49416

- ((ptr->tune < TARGET_CPU_DEFAULT_max)

49417

- ? cpu_names[ptr->tune]

49418

- : "<unknown>"));

49419

+ ptr->tune, processor_target_table[ptr->tune].name);

49420

49421

fprintf (file, "%*sbranch_cost = %d\n", indent, "", ptr->branch_cost);

49422

49423

@@ -5213,7 +5176,12 @@

49424

/* Use register calling convention for local functions when possible. */

49425

if (decl

49426

&& TREE_CODE (decl) == FUNCTION_DECL

49427

- && optimize

49428

+ /* Caller and callee must agree on the calling convention, so

49429

+ checking here just optimize means that with

49430

+ __attribute__((optimize (...))) caller could use regparm convention

49431

+ and callee not, or vice versa. Instead look at whether the callee

49432

+ is optimized or not. */

49433

+ && opt_for_fn (decl, optimize)

49434

&& !(profile_flag && !flag_fentry))

49435

{

49436

/* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */

49437

@@ -5409,6 +5377,17 @@

49438

bool win;

49439

int j;

49440

49441

+ /* For pre-AVX disallow unaligned loads/stores where the

49442

+ instructions don't support it. */

49443

+ if (!TARGET_AVX

49444

+ && VECTOR_MODE_P (GET_MODE (op))

49445

+ && misaligned_operand (op, GET_MODE (op)))

49446

+ {

49447

+ int min_align = get_attr_ssememalign (insn);

49448

+ if (min_align == 0)

49449

+ return false;

49450

+ }

49451

+

49452

/* A unary operator may be accepted by the predicate, but it

49453

is irrelevant for matching constraints. */

49454

if (UNARY_P (op))

49455

@@ -5747,9 +5726,9 @@

49456

cum->nregs = 0;

49457

cum->sse_nregs = 0;

49458

cum->mmx_nregs = 0;

49459

- cum->warn_avx = 0;

49460

- cum->warn_sse = 0;

49461

- cum->warn_mmx = 0;

49462

+ cum->warn_avx = false;

49463

+ cum->warn_sse = false;

49464

+ cum->warn_mmx = false;

49465

return;

49466

}

49467

49468

@@ -5790,10 +5769,14 @@

49469

49470

The midde-end can't deal with the vector types > 16 bytes. In this

49471

case, we return the original mode and warn ABI change if CUM isn't

49472

- NULL. */

49473

+ NULL.

49474

49475

+ If INT_RETURN is true, warn ABI change if the vector mode isn't

49476

+ available for function return value. */

49477

+

49478

static enum machine_mode

49479

-type_natural_mode (const_tree type, const CUMULATIVE_ARGS *cum)

49480

+type_natural_mode (const_tree type, const CUMULATIVE_ARGS *cum,

49481

+ bool in_return)

49482

{

49483

enum machine_mode mode = TYPE_MODE (type);

49484

49485

@@ -5819,33 +5802,61 @@

49486

if (size == 32 && !TARGET_AVX)

49487

{

49488

static bool warnedavx;

49489

+ static bool warnedavx_ret;

49490

49491

- if (cum

49492

- && !warnedavx

49493

- && cum->warn_avx)

49494

+ if (cum && cum->warn_avx && !warnedavx)

49495

{

49496

- warnedavx = true;

49497

- warning (0, "AVX vector argument without AVX "

49498

- "enabled changes the ABI");

49499

+ if (warning (OPT_Wpsabi, "AVX vector argument "

49500

+ "without AVX enabled changes the ABI"))

49501

+ warnedavx = true;

49502

}

49503

+ else if (in_return && !warnedavx_ret)

49504

+ {

49505

+ if (warning (OPT_Wpsabi, "AVX vector return "

49506

+ "without AVX enabled changes the ABI"))

49507

+ warnedavx_ret = true;

49508

+ }

49509

+

49510

return TYPE_MODE (type);

49511

}

49512

- else if ((size == 8 || size == 16) && !TARGET_SSE)

49513

+ else if (((size == 8 && TARGET_64BIT) || size == 16)

49514

+ && !TARGET_SSE)

49515

{

49516

static bool warnedsse;

49517

+ static bool warnedsse_ret;

49518

49519

- if (cum

49520

- && !warnedsse

49521

- && cum->warn_sse)

49522

+ if (cum && cum->warn_sse && !warnedsse)

49523

{

49524

- warnedsse = true;

49525

- warning (0, "SSE vector argument without SSE "

49526

- "enabled changes the ABI");

49527

+ if (warning (OPT_Wpsabi, "SSE vector argument "

49528

+ "without SSE enabled changes the ABI"))

49529

+ warnedsse = true;

49530

}

49531

- return mode;

49532

+ else if (!TARGET_64BIT && in_return && !warnedsse_ret)

49533

+ {

49534

+ if (warning (OPT_Wpsabi, "SSE vector return "

49535

+ "without SSE enabled changes the ABI"))

49536

+ warnedsse_ret = true;

49537

+ }

49538

}

49539

- else

49540

- return mode;

49541

+ else if ((size == 8 && !TARGET_64BIT) && !TARGET_MMX)

49542

+ {

49543

+ static bool warnedmmx;

49544

+ static bool warnedmmx_ret;

49545

+

49546

+ if (cum && cum->warn_mmx && !warnedmmx)

49547

+ {

49548

+ if (warning (OPT_Wpsabi, "MMX vector argument "

49549

+ "without MMX enabled changes the ABI"))

49550

+ warnedmmx = true;

49551

+ }

49552

+ else if (in_return && !warnedmmx_ret)

49553

+ {

49554

+ if (warning (OPT_Wpsabi, "MMX vector return "

49555

+ "without MMX enabled changes the ABI"))

49556

+ warnedmmx_ret = true;

49557

+ }

49558

+ }

49559

+ return mode;

49560

}

49561

49562

gcc_unreachable ();

49563

@@ -6190,25 +6201,28 @@

49564

case CHImode:

49565

case CQImode:

49566

{

49567

- int size = (bit_offset % 64)+ (int) GET_MODE_BITSIZE (mode);

49568

+ int size = bit_offset + (int) GET_MODE_BITSIZE (mode);

49569

49570

- if (size <= 32)

49571

+ /* Analyze last 128 bits only. */

49572

+ size = (size - 1) & 0x7f;

49573

+

49574

+ if (size < 32)

49575

{

49576

classes[0] = X86_64_INTEGERSI_CLASS;

49577

return 1;

49578

}

49579

- else if (size <= 64)

49580

+ else if (size < 64)

49581

{

49582

classes[0] = X86_64_INTEGER_CLASS;

49583

return 1;

49584

}

49585

- else if (size <= 64+32)

49586

+ else if (size < 64+32)

49587

{

49588

classes[0] = X86_64_INTEGER_CLASS;

49589

classes[1] = X86_64_INTEGERSI_CLASS;

49590

return 2;

49591

}

49592

- else if (size <= 64+64)

49593

+ else if (size < 64+64)

49594

{

49595

classes[0] = classes[1] = X86_64_INTEGER_CLASS;

49596

return 2;

49597

@@ -6475,7 +6489,7 @@

49598

if (n == 2

49599

&& regclass[0] == X86_64_INTEGER_CLASS

49600

&& regclass[1] == X86_64_INTEGER_CLASS

49601

- && (mode == CDImode || mode == TImode || mode == TFmode)

49602

+ && (mode == CDImode || mode == TImode)

49603

&& intreg[0] + 1 == intreg[1])

49604

return gen_rtx_REG (mode, intreg[0]);

49605

49606

@@ -6725,7 +6739,7 @@

49607

words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;

49608

49609

if (type)

49610

- mode = type_natural_mode (type, NULL);

49611

+ mode = type_natural_mode (type, NULL, false);

49612

49613

if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI)

49614

function_arg_advance_ms_64 (cum, bytes, words);

49615

@@ -6753,8 +6767,6 @@

49616

enum machine_mode orig_mode, const_tree type,

49617

HOST_WIDE_INT bytes, HOST_WIDE_INT words)

49618

{

49619

- static bool warnedsse, warnedmmx;

49620

-

49621

/* Avoid the AL settings for the Unix64 ABI. */

49622

if (mode == VOIDmode)

49623

return constm1_rtx;

49624

@@ -6811,12 +6823,6 @@

49625

case V2DFmode:

49626

if (!type || !AGGREGATE_TYPE_P (type))

49627

{

49628

- if (!TARGET_SSE && !warnedsse && cum->warn_sse)

49629

- {

49630

- warnedsse = true;

49631

- warning (0, "SSE vector argument without SSE enabled "

49632

- "changes the ABI");

49633

- }

49634

if (cum->sse_nregs)

49635

return gen_reg_or_parallel (mode, orig_mode,

49636

cum->sse_regno + FIRST_SSE_REG);

49637

@@ -6849,12 +6855,6 @@

49638

case V1DImode:

49639

if (!type || !AGGREGATE_TYPE_P (type))

49640

{

49641

- if (!TARGET_MMX && !warnedmmx && cum->warn_mmx)

49642

- {

49643

- warnedmmx = true;

49644

- warning (0, "MMX vector argument without MMX enabled "

49645

- "changes the ABI");

49646

- }

49647

if (cum->mmx_nregs)

49648

return gen_reg_or_parallel (mode, orig_mode,

49649

cum->mmx_regno + FIRST_MMX_REG);

49650

@@ -6977,7 +6977,7 @@

49651

/* To simplify the code below, represent vector types with a vector mode

49652

even if MMX/SSE are not active. */

49653

if (type && TREE_CODE (type) == VECTOR_TYPE)

49654

- mode = type_natural_mode (type, cum);

49655

+ mode = type_natural_mode (type, cum, false);

49656

49657

if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI)

49658

arg = function_arg_ms_64 (cum, mode, omode, named, bytes);

49659

@@ -7235,9 +7235,15 @@

49660

switch (regno)

49661

{

49662

case AX_REG:

49663

+ case DX_REG:

49664

return true;

49665

+ case DI_REG:

49666

+ case SI_REG:

49667

+ return TARGET_64BIT && ix86_abi != MS_ABI;

49668

49669

- case FIRST_FLOAT_REG:

49670

+ /* Complex values are returned in %st(0)/%st(1) pair. */

49671

+ case ST0_REG:

49672

+ case ST1_REG:

49673

/* TODO: The function should depend on current function ABI but

49674

builtins.c would need updating then. Therefore we use the

49675

default ABI. */

49676

@@ -7245,10 +7251,12 @@

49677

return false;

49678

return TARGET_FLOAT_RETURNS_IN_80387;

49679

49680

- case FIRST_SSE_REG:

49681

+ /* Complex values are returned in %xmm0/%xmm1 pair. */

49682

+ case XMM0_REG:

49683

+ case XMM1_REG:

49684

return TARGET_SSE;

49685

49686

- case FIRST_MMX_REG:

49687

+ case MM0_REG:

49688

if (TARGET_MACHO || TARGET_64BIT)

49689

return false;

49690

return TARGET_MMX;

49691

@@ -7420,7 +7428,7 @@

49692

enum machine_mode mode, orig_mode;

49693

49694

orig_mode = TYPE_MODE (valtype);

49695

- mode = type_natural_mode (valtype, NULL);

49696

+ mode = type_natural_mode (valtype, NULL, true);

49697

return ix86_function_value_1 (valtype, fntype_or_decl, orig_mode, mode);

49698

}

49699

49700

@@ -7535,7 +7543,7 @@

49701

#ifdef SUBTARGET_RETURN_IN_MEMORY

49702

return SUBTARGET_RETURN_IN_MEMORY (type, fntype);

49703

#else

49704

- const enum machine_mode mode = type_natural_mode (type, NULL);

49705

+ const enum machine_mode mode = type_natural_mode (type, NULL, true);

49706

49707

if (TARGET_64BIT)

49708

{

49709

@@ -7549,52 +7557,6 @@

49710

#endif

49711

}

49712

49713

-/* When returning SSE vector types, we have a choice of either

49714

- (1) being abi incompatible with a -march switch, or

49715

- (2) generating an error.

49716

- Given no good solution, I think the safest thing is one warning.

49717

- The user won't be able to use -Werror, but....

49718

-

49719

- Choose the STRUCT_VALUE_RTX hook because that's (at present) only

49720

- called in response to actually generating a caller or callee that

49721

- uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called

49722

- via aggregate_value_p for general type probing from tree-ssa. */

49723

-

49724

-static rtx

49725

-ix86_struct_value_rtx (tree type, int incoming ATTRIBUTE_UNUSED)

49726

-{

49727

- static bool warnedsse, warnedmmx;

49728

-

49729

- if (!TARGET_64BIT && type)

49730

- {

49731

- /* Look at the return type of the function, not the function type. */

49732

- enum machine_mode mode = TYPE_MODE (TREE_TYPE (type));

49733

-

49734

- if (!TARGET_SSE && !warnedsse)

49735

- {

49736

- if (mode == TImode

49737

- || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))

49738

- {

49739

- warnedsse = true;

49740

- warning (0, "SSE vector return without SSE enabled "

49741

- "changes the ABI");

49742

- }

49743

- }

49744

-

49745

- if (!TARGET_MMX && !warnedmmx)

49746

- {

49747

- if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)

49748

- {

49749

- warnedmmx = true;

49750

- warning (0, "MMX vector return without MMX enabled "

49751

- "changes the ABI");

49752

- }

49753

- }

49754

- }

49755

-

49756

- return NULL;

49757

-}

49758

-

49759

49760

/* Create the va_list data type. */

49761

49762

@@ -8019,7 +7981,7 @@

49763

size = int_size_in_bytes (type);

49764

rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;

49765

49766

- nat_mode = type_natural_mode (type, NULL);

49767

+ nat_mode = type_natural_mode (type, NULL, false);

49768

switch (nat_mode)

49769

{

49770

case V8SFmode:

49771

@@ -10560,18 +10522,20 @@

49772

}

49773

m->fs.sp_offset += allocate;

49774

49775

+ /* Use stack_pointer_rtx for relative addressing so that code

49776

+ works for realigned stack, too. */

49777

if (r10_live && eax_live)

49778

{

49779

- t = choose_baseaddr (m->fs.sp_offset - allocate);

49780

+ t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, eax);

49781

emit_move_insn (gen_rtx_REG (word_mode, R10_REG),

49782

gen_frame_mem (word_mode, t));

49783

- t = choose_baseaddr (m->fs.sp_offset - allocate - UNITS_PER_WORD);

49784

+ t = plus_constant (Pmode, t, UNITS_PER_WORD);

49785

emit_move_insn (gen_rtx_REG (word_mode, AX_REG),

49786

gen_frame_mem (word_mode, t));

49787

}

49788

else if (eax_live || r10_live)

49789

{

49790

- t = choose_baseaddr (m->fs.sp_offset - allocate);

49791

+ t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, eax);

49792

emit_move_insn (gen_rtx_REG (word_mode,

49793

(eax_live ? AX_REG : R10_REG)),

49794

gen_frame_mem (word_mode, t));

49795

@@ -11164,8 +11128,9 @@

49796

m->fs.cfa_offset -= UNITS_PER_WORD;

49797

m->fs.sp_offset -= UNITS_PER_WORD;

49798

49799

- add_reg_note (insn, REG_CFA_ADJUST_CFA,

49800

- copy_rtx (XVECEXP (PATTERN (insn), 0, 1)));

49801

+ rtx x = plus_constant (Pmode, stack_pointer_rtx, UNITS_PER_WORD);

49802

+ x = gen_rtx_SET (VOIDmode, stack_pointer_rtx, x);

49803

+ add_reg_note (insn, REG_CFA_ADJUST_CFA, x);

49804

add_reg_note (insn, REG_CFA_REGISTER,

49805

gen_rtx_SET (VOIDmode, ecx, pc_rtx));

49806

RTX_FRAME_RELATED_P (insn) = 1;

49807

@@ -11561,30 +11526,6 @@

49808

}

49809

}

49810

49811

-/* Determine if op is suitable SUBREG RTX for address. */

49812

-

49813

-static bool

49814

-ix86_address_subreg_operand (rtx op)

49815

-{

49816

- enum machine_mode mode;

49817

-

49818

- if (!REG_P (op))

49819

- return false;

49820

-

49821

- mode = GET_MODE (op);

49822

-

49823

- if (GET_MODE_CLASS (mode) != MODE_INT)

49824

- return false;

49825

-

49826

- /* Don't allow SUBREGs that span more than a word. It can lead to spill

49827

- failures when the register is one word out of a two word structure. */

49828

- if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)

49829

- return false;

49830

-

49831

- /* Allow only SUBREGs of non-eliminable hard registers. */

49832

- return register_no_elim_operand (op, mode);

49833

-}

49834

-

49835

/* Extract the parts of an RTL expression that is a valid memory address

49836

for an instruction. Return 0 if the structure of the address is

49837

grossly off. Return -1 if the address contains ASHIFT, so it is not

49838

@@ -11641,7 +11582,7 @@

49839

base = addr;

49840

else if (GET_CODE (addr) == SUBREG)

49841

{

49842

- if (ix86_address_subreg_operand (SUBREG_REG (addr)))

49843

+ if (REG_P (SUBREG_REG (addr)))

49844

base = addr;

49845

else

49846

return 0;

49847

@@ -11705,7 +11646,7 @@

49848

break;

49849

49850

case SUBREG:

49851

- if (!ix86_address_subreg_operand (SUBREG_REG (op)))

49852

+ if (!REG_P (SUBREG_REG (op)))

49853

return 0;

49854

/* FALLTHRU */

49855

49856

@@ -11750,19 +11691,6 @@

49857

scale = 1 << scale;

49858

retval = -1;

49859

}

49860

- else if (CONST_INT_P (addr))

49861

- {

49862

- if (!x86_64_immediate_operand (addr, VOIDmode))

49863

- return 0;

49864

-

49865

- /* Constant addresses are sign extended to 64bit, we have to

49866

- prevent addresses from 0x80000000 to 0xffffffff in x32 mode. */

49867

- if (TARGET_X32

49868

- && val_signbit_known_set_p (SImode, INTVAL (addr)))

49869

- return 0;

49870

-

49871

- disp = addr;

49872

- }

49873

else

49874

disp = addr; /* displacement */

49875

49876

@@ -11771,18 +11699,12 @@

49877

if (REG_P (index))

49878

;

49879

else if (GET_CODE (index) == SUBREG

49880

- && ix86_address_subreg_operand (SUBREG_REG (index)))

49881

+ && REG_P (SUBREG_REG (index)))

49882

;

49883

else

49884

return 0;

49885

}

49886

49887

-/* Address override works only on the (%reg) part of %fs:(%reg). */

49888

- if (seg != SEG_DEFAULT

49889

- && ((base && GET_MODE (base) != word_mode)

49890

- || (index && GET_MODE (index) != word_mode)))

49891

- return 0;

49892

-

49893

/* Extract the integral value of scale. */

49894

if (scale_rtx)

49895

{

49896

@@ -12258,6 +12180,45 @@

49897

return false;

49898

}

49899

49900

+/* Determine if op is suitable RTX for an address register.

49901

+ Return naked register if a register or a register subreg is

49902

+ found, otherwise return NULL_RTX. */

49903

+

49904

+static rtx

49905

+ix86_validate_address_register (rtx op)

49906

+{

49907

+ enum machine_mode mode = GET_MODE (op);

49908

+

49909

+ /* Only SImode or DImode registers can form the address. */

49910

+ if (mode != SImode && mode != DImode)

49911

+ return NULL_RTX;

49912

+

49913

+ if (REG_P (op))

49914

+ return op;

49915

+ else if (GET_CODE (op) == SUBREG)

49916

+ {

49917

+ rtx reg = SUBREG_REG (op);

49918

+

49919

+ if (!REG_P (reg))

49920

+ return NULL_RTX;

49921

+

49922

+ mode = GET_MODE (reg);

49923

+

49924

+ /* Don't allow SUBREGs that span more than a word. It can

49925

+ lead to spill failures when the register is one word out

49926

+ of a two word structure. */

49927

+ if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)

49928

+ return NULL_RTX;

49929

+

49930

+ /* Allow only SUBREGs of non-eliminable hard registers. */

49931

+ if (register_no_elim_operand (reg, mode))

49932

+ return reg;

49933

+ }

49934

+

49935

+ /* Op is not a register. */

49936

+ return NULL_RTX;

49937

+}

49938

+

49939

/* Recognizes RTL expressions that are valid memory addresses for an

49940

instruction. The MODE argument is the machine mode for the MEM

49941

expression that wants to use this address.

49942

@@ -12273,6 +12234,7 @@

49943

struct ix86_address parts;

49944

rtx base, index, disp;

49945

HOST_WIDE_INT scale;

49946

+ enum ix86_address_seg seg;

49947

49948

if (ix86_decompose_address (addr, &parts) <= 0)

49949

/* Decomposition failed. */

49950

@@ -12282,23 +12244,16 @@

49951

index = parts.index;

49952

disp = parts.disp;

49953

scale = parts.scale;

49954

+ seg = parts.seg;

49955

49956

/* Validate base register. */

49957

if (base)

49958

{

49959

- rtx reg;

49960

+ rtx reg = ix86_validate_address_register (base);

49961

49962

- if (REG_P (base))

49963

- reg = base;

49964

- else if (GET_CODE (base) == SUBREG && REG_P (SUBREG_REG (base)))

49965

- reg = SUBREG_REG (base);

49966

- else

49967

- /* Base is not a register. */

49968

+ if (reg == NULL_RTX)

49969

return false;

49970

49971

- if (GET_MODE (base) != SImode && GET_MODE (base) != DImode)

49972

- return false;

49973

-

49974

if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg))

49975

|| (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (reg)))

49976

/* Base is not valid. */

49977

@@ -12308,19 +12263,11 @@

49978

/* Validate index register. */

49979

if (index)

49980

{

49981

- rtx reg;

49982

+ rtx reg = ix86_validate_address_register (index);

49983

49984

- if (REG_P (index))

49985

- reg = index;

49986

- else if (GET_CODE (index) == SUBREG && REG_P (SUBREG_REG (index)))

49987

- reg = SUBREG_REG (index);

49988

- else

49989

- /* Index is not a register. */

49990

+ if (reg == NULL_RTX)

49991

return false;

49992

49993

- if (GET_MODE (index) != SImode && GET_MODE (index) != DImode)

49994

- return false;

49995

-

49996

if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (reg))

49997

|| (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (reg)))

49998

/* Index is not valid. */

49999

@@ -12332,6 +12279,12 @@

50000

&& GET_MODE (base) != GET_MODE (index))

50001

return false;

50002

50003

+ /* Address override works only on the (%reg) part of %fs:(%reg). */

50004

+ if (seg != SEG_DEFAULT

50005

+ && ((base && GET_MODE (base) != word_mode)

50006

+ || (index && GET_MODE (index) != word_mode)))

50007

+ return false;

50008

+

50009

/* Validate scale factor. */

50010

if (scale != 1)

50011

{

50012

@@ -12453,6 +12406,12 @@

50013

&& !x86_64_immediate_operand (disp, VOIDmode))

50014

/* Displacement is out of range. */

50015

return false;

50016

+ /* In x32 mode, constant addresses are sign extended to 64bit, so

50017

+ we have to prevent addresses from 0x80000000 to 0xffffffff. */

50018

+ else if (TARGET_X32 && !(index || base)

50019

+ && CONST_INT_P (disp)

50020

+ && val_signbit_known_set_p (SImode, INTVAL (disp)))

50021

+ return false;

50022

}

50023

50024

/* Everything looks valid. */

50025

@@ -13817,8 +13776,6 @@

50026

Those same assemblers have the same but opposite lossage on cmov. */

50027

if (mode == CCmode)

50028

suffix = fp ? "nbe" : "a";

50029

- else if (mode == CCCmode)

50030

- suffix = "b";

50031

else

50032

gcc_unreachable ();

50033

break;

50034

@@ -13840,8 +13797,12 @@

50035

}

50036

break;

50037

case LTU:

50038

- gcc_assert (mode == CCmode || mode == CCCmode);

50039

- suffix = "b";

50040

+ if (mode == CCmode)

50041

+ suffix = "b";

50042

+ else if (mode == CCCmode)

50043

+ suffix = "c";

50044

+ else

50045

+ gcc_unreachable ();

50046

break;

50047

case GE:

50048

switch (mode)

50049

@@ -13861,9 +13822,12 @@

50050

}

50051

break;

50052

case GEU:

50053

- /* ??? As above. */

50054

- gcc_assert (mode == CCmode || mode == CCCmode);

50055

- suffix = fp ? "nb" : "ae";

50056

+ if (mode == CCmode)

50057

+ suffix = fp ? "nb" : "ae";

50058

+ else if (mode == CCCmode)

50059

+ suffix = "nc";

50060

+ else

50061

+ gcc_unreachable ();

50062

break;

50063

case LE:

50064

gcc_assert (mode == CCmode || mode == CCGCmode || mode == CCNOmode);

50065

@@ -13870,11 +13834,8 @@

50066

suffix = "le";

50067

break;

50068

case LEU:

50069

- /* ??? As above. */

50070

if (mode == CCmode)

50071

suffix = "be";

50072

- else if (mode == CCCmode)

50073

- suffix = fp ? "nb" : "ae";

50074

else

50075

gcc_unreachable ();

50076

break;

50077

@@ -15340,7 +15301,7 @@

50078

rtx arg = XEXP (XEXP (link, 0), 0);

50079

50080

if (ix86_check_avx256_register (&arg, NULL))

50081

- return AVX_U128_ANY;

50082

+ return AVX_U128_DIRTY;

50083

}

50084

}

50085

50086

@@ -15460,8 +15421,8 @@

50087

{

50088

bool avx_reg256_found = false;

50089

note_stores (pat, ix86_check_avx256_stores, &avx_reg256_found);

50090

- if (!avx_reg256_found)

50091

- return AVX_U128_CLEAN;

50092

+

50093

+ return avx_reg256_found ? AVX_U128_DIRTY : AVX_U128_CLEAN;

50094

}

50095

50096

/* Otherwise, return current mode. Remember that if insn

50097

@@ -17350,10 +17311,20 @@

50098

if (!TARGET_OPT_AGU || optimize_function_for_size_p (cfun))

50099

return false;

50100

50101

- /* Check it is correct to split here. */

50102

- if (!ix86_ok_to_clobber_flags(insn))

50103

+ /* The "at least two components" test below might not catch simple

50104

+ move or zero extension insns if parts.base is non-NULL and parts.disp

50105

+ is const0_rtx as the only components in the address, e.g. if the

50106

+ register is %rbp or %r13. As this test is much cheaper and moves or

50107

+ zero extensions are the common case, do this check first. */

50108

+ if (REG_P (operands[1])

50109

+ || (SImode_address_operand (operands[1], VOIDmode)

50110

+ && REG_P (XEXP (operands[1], 0))))

50111

return false;

50112

50113

+ /* Check if it is OK to split here. */

50114

+ if (!ix86_ok_to_clobber_flags (insn))

50115

+ return false;

50116

+

50117

ok = ix86_decompose_address (operands[1], &parts);

50118

gcc_assert (ok);

50119

50120

@@ -18486,12 +18457,7 @@

50121

return CCmode;

50122

case GTU: /* CF=0 & ZF=0 */

50123

case LEU: /* CF=1 | ZF=1 */

50124

- /* Detect overflow checks. They need just the carry flag. */

50125

- if (GET_CODE (op0) == MINUS

50126

- && rtx_equal_p (op1, XEXP (op0, 0)))

50127

- return CCCmode;

50128

- else

50129

- return CCmode;

50130

+ return CCmode;

50131

/* Codes possibly doable only with sign flag when

50132

comparing against zero. */

50133

case GE: /* SF=OF or SF=0 */

50134

@@ -20500,7 +20466,7 @@

50135

return;

50136

50137

case V8SFmode:

50138

- mask = gen_lowpart (V8SFmode, mask);

50139

+ mask = gen_lowpart (V8SImode, mask);

50140

if (one_operand_shuffle)

50141

emit_insn (gen_avx2_permvarv8sf (target, op0, mask));

50142

else

50143

@@ -21740,6 +21706,21 @@

50144

return SImode;

50145

}

50146

50147

+/* Copy the address to a Pmode register. This is used for x32 to

50148

+ truncate DImode TLS address to a SImode register. */

50149

+

50150

+static rtx

50151

+ix86_copy_addr_to_reg (rtx addr)

50152

+{

50153

+ if (GET_MODE (addr) == Pmode || GET_MODE (addr) == VOIDmode)

50154

+ return copy_addr_to_reg (addr);

50155

+ else

50156

+ {

50157

+ gcc_assert (GET_MODE (addr) == DImode && Pmode == SImode);

50158

+ return gen_rtx_SUBREG (SImode, copy_to_mode_reg (DImode, addr), 0);

50159

+ }

50160

+}

50161

+

50162

/* When SRCPTR is non-NULL, output simple loop to move memory

50163

pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,

50164

overall size is COUNT specified in bytes. When SRCPTR is NULL, output the

50165

@@ -22728,8 +22709,8 @@

50166

gcc_assert (alg != no_stringop);

50167

if (!count)

50168

count_exp = copy_to_mode_reg (GET_MODE (count_exp), count_exp);

50169

- destreg = copy_addr_to_reg (XEXP (dst, 0));

50170

- srcreg = copy_addr_to_reg (XEXP (src, 0));

50171

+ destreg = ix86_copy_addr_to_reg (XEXP (dst, 0));

50172

+ srcreg = ix86_copy_addr_to_reg (XEXP (src, 0));

50173

switch (alg)

50174

{

50175

case libcall:

50176

@@ -23119,7 +23100,7 @@

50177

gcc_assert (alg != no_stringop);

50178

if (!count)

50179

count_exp = copy_to_mode_reg (counter_mode (count_exp), count_exp);

50180

- destreg = copy_addr_to_reg (XEXP (dst, 0));

50181

+ destreg = ix86_copy_addr_to_reg (XEXP (dst, 0));

50182

switch (alg)

50183

{

50184

case libcall:

50185

@@ -24988,7 +24969,8 @@

50186

int

50187

ix86_data_alignment (tree type, int align)

50188

{

50189

- int max_align = optimize_size ? BITS_PER_WORD : MIN (256, MAX_OFILE_ALIGNMENT);

50190

+ int max_align

50191

+ = optimize_size ? BITS_PER_WORD : MIN (256, MAX_OFILE_ALIGNMENT);

50192

50193

if (AGGREGATE_TYPE_P (type)

50194

&& TYPE_SIZE (type)

50195

@@ -27984,8 +27966,8 @@

50196

{ OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },

50197

{ OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },

50198

50199

- { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_2_SF },

50200

- { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_2_DF },

50201

+ { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_1_SF },

50202

+ { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_1_DF },

50203

{ OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },

50204

{ OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },

50205

{ OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },

50206

@@ -31245,11 +31227,12 @@

50207

50208

static rtx

50209

ix86_expand_special_args_builtin (const struct builtin_description *d,

50210

- tree exp, rtx target)

50211

+ tree exp, rtx target)

50212

{

50213

tree arg;

50214

rtx pat, op;

50215

unsigned int i, nargs, arg_adjust, memory;

50216

+ bool aligned_mem = false;

50217

struct

50218

{

50219

rtx op;

50220

@@ -31295,6 +31278,15 @@

50221

nargs = 1;

50222

klass = load;

50223

memory = 0;

50224

+ switch (icode)

50225

+ {

50226

+ case CODE_FOR_sse4_1_movntdqa:

50227

+ case CODE_FOR_avx2_movntdqa:

50228

+ aligned_mem = true;

50229

+ break;

50230

+ default:

50231

+ break;

50232

+ }

50233

break;

50234

case VOID_FTYPE_PV2SF_V4SF:

50235

case VOID_FTYPE_PV4DI_V4DI:

50236

@@ -31312,6 +31304,26 @@

50237

klass = store;

50238

/* Reserve memory operand for target. */

50239

memory = ARRAY_SIZE (args);

50240

+ switch (icode)

50241

+ {

50242

+ /* These builtins and instructions require the memory

50243

+ to be properly aligned. */

50244

+ case CODE_FOR_avx_movntv4di:

50245

+ case CODE_FOR_sse2_movntv2di:

50246

+ case CODE_FOR_avx_movntv8sf:

50247

+ case CODE_FOR_sse_movntv4sf:

50248

+ case CODE_FOR_sse4a_vmmovntv4sf:

50249

+ case CODE_FOR_avx_movntv4df:

50250

+ case CODE_FOR_sse2_movntv2df:

50251

+ case CODE_FOR_sse4a_vmmovntv2df:

50252

+ case CODE_FOR_sse2_movntidi:

50253

+ case CODE_FOR_sse_movntq:

50254

+ case CODE_FOR_sse2_movntisi:

50255

+ aligned_mem = true;

50256

+ break;

50257

+ default:

50258

+ break;

50259

+ }

50260

break;

50261

case V4SF_FTYPE_V4SF_PCV2SF:

50262

case V2DF_FTYPE_V2DF_PCDOUBLE:

50263

@@ -31368,6 +31380,17 @@

50264

{

50265

op = force_reg (Pmode, convert_to_mode (Pmode, op, 1));

50266

target = gen_rtx_MEM (tmode, op);

50267

+ /* target at this point has just BITS_PER_UNIT MEM_ALIGN

50268

+ on it. Try to improve it using get_pointer_alignment,

50269

+ and if the special builtin is one that requires strict

50270

+ mode alignment, also from it's GET_MODE_ALIGNMENT.

50271

+ Failure to do so could lead to ix86_legitimate_combined_insn

50272

+ rejecting all changes to such insns. */

50273

+ unsigned int align = get_pointer_alignment (arg);

50274

+ if (aligned_mem && align < GET_MODE_ALIGNMENT (tmode))

50275

+ align = GET_MODE_ALIGNMENT (tmode);

50276

+ if (MEM_ALIGN (target) < align)

50277

+ set_mem_align (target, align);

50278

}

50279

else

50280

target = force_reg (tmode, op);

50281

@@ -31413,8 +31436,17 @@

50282

/* This must be the memory operand. */

50283

op = force_reg (Pmode, convert_to_mode (Pmode, op, 1));

50284

op = gen_rtx_MEM (mode, op);

50285

- gcc_assert (GET_MODE (op) == mode

50286

- || GET_MODE (op) == VOIDmode);

50287

+ /* op at this point has just BITS_PER_UNIT MEM_ALIGN

50288

+ on it. Try to improve it using get_pointer_alignment,

50289

+ and if the special builtin is one that requires strict

50290

+ mode alignment, also from it's GET_MODE_ALIGNMENT.

50291

+ Failure to do so could lead to ix86_legitimate_combined_insn

50292

+ rejecting all changes to such insns. */

50293

+ unsigned int align = get_pointer_alignment (arg);

50294

+ if (aligned_mem && align < GET_MODE_ALIGNMENT (mode))

50295

+ align = GET_MODE_ALIGNMENT (mode);

50296

+ if (MEM_ALIGN (op) < align)

50297

+ set_mem_align (op, align);

50298

}

50299

else

50300

{

50301

@@ -32027,7 +32059,8 @@

50302

else

50303

op2 = gen_rtx_SUBREG (SImode, op0, 0);

50304

50305

- if (target == 0)

50306

+ if (target == 0

50307

+ || !register_operand (target, SImode))

50308

target = gen_reg_rtx (SImode);

50309

50310

pat = gen_rtx_GEU (VOIDmode, gen_rtx_REG (CCCmode, FLAGS_REG),

50311

@@ -32069,7 +32102,8 @@

50312

const0_rtx);

50313

emit_insn (gen_rtx_SET (VOIDmode, op2, pat));

50314

50315

- if (target == 0)

50316

+ if (target == 0

50317

+ || !register_operand (target, SImode))

50318

target = gen_reg_rtx (SImode);

50319

50320

emit_insn (gen_zero_extendqisi2 (target, op2));

50321

@@ -32208,7 +32242,9 @@

50322

mode4 = insn_data[icode].operand[5].mode;

50323

50324

if (target == NULL_RTX

50325

- || GET_MODE (target) != insn_data[icode].operand[0].mode)

50326

+ || GET_MODE (target) != insn_data[icode].operand[0].mode

50327

+ || !insn_data[icode].operand[0].predicate (target,

50328

+ GET_MODE (target)))

50329

subtarget = gen_reg_rtx (insn_data[icode].operand[0].mode);

50330

else

50331

subtarget = target;

50332

@@ -33879,10 +33915,10 @@

50333

{

50334

/* We implement the move patterns for all vector modes into and

50335

out of SSE registers, even when no operation instructions

50336

- are available. OImode move is available only when AVX is

50337

- enabled. */

50338

- return ((TARGET_AVX && mode == OImode)

50339

- || VALID_AVX256_REG_MODE (mode)

50340

+ are available. OImode and AVX modes are available only when

50341

+ AVX is enabled. */

50342

+ return ((TARGET_AVX

50343

+ && VALID_AVX256_REG_OR_OI_MODE (mode))

50344

|| VALID_SSE_REG_MODE (mode)

50345

|| VALID_SSE2_REG_MODE (mode)

50346

|| VALID_MMX_REG_MODE (mode)

50347

@@ -35020,7 +35056,7 @@

50348

{

50349

tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, fnaddr), UNSPEC_GOTPCREL);

50350

tmp = gen_rtx_CONST (Pmode, tmp);

50351

- fnaddr = gen_rtx_MEM (Pmode, tmp);

50352

+ fnaddr = gen_const_mem (Pmode, tmp);

50353

}

50354

}

50355

else

50356

@@ -35040,8 +35076,9 @@

50357

output_set_got (tmp, NULL_RTX);

50358

50359

fnaddr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, fnaddr), UNSPEC_GOT);

50360

- fnaddr = gen_rtx_PLUS (Pmode, fnaddr, tmp);

50361

- fnaddr = gen_rtx_MEM (Pmode, fnaddr);

50362

+ fnaddr = gen_rtx_CONST (Pmode, fnaddr);

50363

+ fnaddr = gen_rtx_PLUS (Pmode, tmp, fnaddr);

50364

+ fnaddr = gen_const_mem (Pmode, fnaddr);

50365

}

50366

}

50367

50368

@@ -35232,7 +35269,10 @@

50369

The smallest offset in the page INSN can start is the case where START

50370

ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).

50371

We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).

50372

- */

50373

+

50374

+ Don't consider asm goto as jump, while it can contain a jump, it doesn't

50375

+ have to, control transfer to label(s) can be performed through other

50376

+ means, and also we estimate minimum length of all asm stmts as 0. */

50377

for (insn = start; insn; insn = NEXT_INSN (insn))

50378

{

50379

int min_size;

50380

@@ -35260,6 +35300,7 @@

50381

{

50382

start = NEXT_INSN (start);

50383

if ((JUMP_P (start)

50384

+ && asm_noperands (PATTERN (start)) < 0

50385

&& GET_CODE (PATTERN (start)) != ADDR_VEC

50386

&& GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)

50387

|| CALL_P (start))

50388

@@ -35278,6 +35319,7 @@

50389

fprintf (dump_file, "Insn %i estimated to %i bytes\n",

50390

INSN_UID (insn), min_size);

50391

if ((JUMP_P (insn)

50392

+ && asm_noperands (PATTERN (insn)) < 0

50393

&& GET_CODE (PATTERN (insn)) != ADDR_VEC

50394

&& GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)

50395

|| CALL_P (insn))

50396

@@ -35289,6 +35331,7 @@

50397

{

50398

start = NEXT_INSN (start);

50399

if ((JUMP_P (start)

50400

+ && asm_noperands (PATTERN (start)) < 0

50401

&& GET_CODE (PATTERN (start)) != ADDR_VEC

50402

&& GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)

50403

|| CALL_P (start))

50404

@@ -39371,7 +39414,9 @@

50405

else

50406

dfinal.perm[i] = e;

50407

}

50408

- dfinal.op0 = gen_reg_rtx (dfinal.vmode);

50409

+

50410

+ if (!d->testing_p)

50411

+ dfinal.op0 = gen_reg_rtx (dfinal.vmode);

50412

dfinal.op1 = dfinal.op0;

50413

dfinal.one_operand_p = true;

50414

dremap.target = dfinal.op0;

50415

@@ -39806,6 +39851,9 @@

50416

return false;

50417

gcc_assert (!d->one_operand_p);

50418

50419

+ if (d->testing_p)

50420

+ return true;

50421

+

50422

nelt = d->nelt;

50423

eltsz = GET_MODE_SIZE (GET_MODE_INNER (d->vmode));

50424

50425

@@ -40005,6 +40053,8 @@

50426

switch (d->vmode)

50427

{

50428

case V4DFmode:

50429

+ if (d->testing_p)

50430

+ break;

50431

t1 = gen_reg_rtx (V4DFmode);

50432

t2 = gen_reg_rtx (V4DFmode);

50433

50434

@@ -40024,6 +40074,8 @@

50435

{

50436

int mask = odd ? 0xdd : 0x88;

50437

50438

+ if (d->testing_p)

50439

+ break;

50440

t1 = gen_reg_rtx (V8SFmode);

50441

t2 = gen_reg_rtx (V8SFmode);

50442

t3 = gen_reg_rtx (V8SFmode);

50443

@@ -40065,6 +40117,8 @@

50444

return expand_vec_perm_pshufb2 (d);

50445

else

50446

{

50447

+ if (d->testing_p)

50448

+ break;

50449

/* We need 2*log2(N)-1 operations to achieve odd/even

50450

with interleave. */

50451

t1 = gen_reg_rtx (V8HImode);

50452

@@ -40086,6 +40140,8 @@

50453

return expand_vec_perm_pshufb2 (d);

50454

else

50455

{

50456

+ if (d->testing_p)

50457

+ break;

50458

t1 = gen_reg_rtx (V16QImode);

50459

t2 = gen_reg_rtx (V16QImode);

50460

t3 = gen_reg_rtx (V16QImode);

50461

@@ -40118,6 +40174,9 @@

50462

return expand_vec_perm_even_odd_1 (&d_copy, odd);

50463

}

50464

50465

+ if (d->testing_p)

50466

+ break;

50467

+

50468

t1 = gen_reg_rtx (V4DImode);

50469

t2 = gen_reg_rtx (V4DImode);

50470

50471

@@ -40144,6 +40203,9 @@

50472

return expand_vec_perm_even_odd_1 (&d_copy, odd);

50473

}

50474

50475

+ if (d->testing_p)

50476

+ break;

50477

+

50478

t1 = gen_reg_rtx (V8SImode);

50479

t2 = gen_reg_rtx (V8SImode);

50480

50481

@@ -40236,6 +40298,8 @@

50482

case V16QImode:

50483

/* These can be implemented via interleave. We save one insn by

50484

stopping once we have promoted to V4SImode and then use pshufd. */

50485

+ if (d->testing_p)

50486

+ return true;

50487

do

50488

{

50489

rtx dest;

50490

@@ -42473,8 +42537,6 @@

50491

50492

#undef TARGET_PROMOTE_PROTOTYPES

50493

#define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true

50494

-#undef TARGET_STRUCT_VALUE_RTX

50495

-#define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx

50496

#undef TARGET_SETUP_INCOMING_VARARGS

50497

#define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs

50498

#undef TARGET_MUST_PASS_IN_STACK

50499

Index: gcc/config/tilegx/tilegx.md

50500

===================================================================

50501

--- a/src/gcc/config/tilegx/tilegx.md (.../tags/gcc_4_8_2_release)

50502

+++ b/src/gcc/config/tilegx/tilegx.md (.../branches/gcc-4_8-branch)

50503

@@ -5076,10 +5076,8 @@

50504

50505

;; Network intrinsics

50506

50507

-;; Note the "pseudo" text is handled specially by the

50508

-;; asm_output_opcode routine. If the output is an empty string, the

50509

-;; instruction would bypass the asm_output_opcode routine, bypassing

50510

-;; the bundle handling code.

50511

+;; Note the this barrier is of type "nothing," which is deleted after

50512

+;; the final scheduling pass so that nothing is emitted for it.

50513

(define_insn "tilegx_network_barrier"

50514

[(unspec_volatile:SI [(const_int 0)] UNSPEC_NETWORK_BARRIER)]

50515

""

50516

Index: gcc/config/tilegx/tilegx-c.c

50517

===================================================================

50518

--- a/src/gcc/config/tilegx/tilegx-c.c (.../tags/gcc_4_8_2_release)

50519

+++ b/src/gcc/config/tilegx/tilegx-c.c (.../branches/gcc-4_8-branch)

50520

@@ -47,6 +47,9 @@

50521

if (TARGET_32BIT)

50522

builtin_define ("__tilegx32__");

50523

50524

+ builtin_define ("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");

50525

+ builtin_define ("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");

50526

+

50527

TILEGX_CPU_CPP_ENDIAN_BUILTINS ();

50528

GNU_USER_TARGET_OS_CPP_BUILTINS ();

50529

}

50530

Index: gcc/config/tilegx/sync.md

50531

===================================================================

50532

--- a/src/gcc/config/tilegx/sync.md (.../tags/gcc_4_8_2_release)

50533

+++ b/src/gcc/config/tilegx/sync.md (.../branches/gcc-4_8-branch)

50534

@@ -150,15 +150,22 @@

50535

(match_operand:SI 3 "const_int_operand" "")] ;; model

50536

""

50537

{

50538

+ rtx addend;

50539

enum memmodel model = (enum memmodel) INTVAL (operands[3]);

50540

50541

if (operands[2] != const0_rtx)

50542

- emit_move_insn (operands[2], gen_rtx_NEG (<MODE>mode, operands[2]));

50543

+ {

50544

+ addend = gen_reg_rtx (<MODE>mode);

50545

+ emit_move_insn (addend,

50546

+ gen_rtx_MINUS (<MODE>mode, const0_rtx, operands[2]));

50547

+ }

50548

+ else

50549

+ addend = operands[2];

50550

50551

tilegx_pre_atomic_barrier (model);

50552

emit_insn (gen_atomic_fetch_add_bare<mode> (operands[0],

50553

operands[1],

50554

- operands[2]));

50555

+ addend));

50556

tilegx_post_atomic_barrier (model);

50557

DONE;

50558

})

50559

Index: gcc/config/tilegx/tilegx.c

50560

===================================================================

50561

--- a/src/gcc/config/tilegx/tilegx.c (.../tags/gcc_4_8_2_release)

50562

+++ b/src/gcc/config/tilegx/tilegx.c (.../branches/gcc-4_8-branch)

50563

@@ -702,6 +702,16 @@

50564

}

50565

50566

50567

+/* Implement TARGET_EXPAND_TO_RTL_HOOK. */

50568

+static void

50569

+tilegx_expand_to_rtl_hook (void)

50570

+{

50571

+ /* Exclude earlier sets of crtl->uses_pic_offset_table, because we

50572

+ only care about uses actually emitted. */

50573

+ crtl->uses_pic_offset_table = 0;

50574

+}

50575

+

50576

+

50577

/* Implement TARGET_SHIFT_TRUNCATION_MASK. DImode shifts use the mode

50578

matching insns and therefore guarantee that the shift count is

50579

modulo 64. SImode shifts sometimes use the 64 bit version so do

50580

@@ -3543,6 +3553,12 @@

50581

}

50582

if (!pat)

50583

return NULL_RTX;

50584

+

50585

+ /* If we are generating a prefetch, tell the scheduler not to move

50586

+ it around. */

50587

+ if (GET_CODE (pat) == PREFETCH)

50588

+ PREFETCH_SCHEDULE_BARRIER_P (pat) = true;

50589

+

50590

emit_insn (pat);

50591

50592

if (nonvoid)

50593

@@ -4368,10 +4384,12 @@

50594

basic_block bb;

50595

FOR_EACH_BB (bb)

50596

{

50597

- rtx insn, next;

50598

+ rtx insn, next, prev;

50599

rtx end = NEXT_INSN (BB_END (bb));

50600

50601

- for (insn = next_insn_to_bundle (BB_HEAD (bb), end); insn; insn = next)

50602

+ prev = NULL_RTX;

50603

+ for (insn = next_insn_to_bundle (BB_HEAD (bb), end); insn;

50604

+ prev = insn, insn = next)

50605

{

50606

next = next_insn_to_bundle (NEXT_INSN (insn), end);

50607

50608

@@ -4396,6 +4414,18 @@

50609

PUT_MODE (insn, SImode);

50610

}

50611

}

50612

+

50613

+ /* Delete barrier insns, because they can mess up the

50614

+ emitting of bundle braces. If it is end-of-bundle, then

50615

+ the previous insn must be marked end-of-bundle. */

50616

+ if (get_attr_type (insn) == TYPE_NOTHING) {

50617

+ if (GET_MODE (insn) == QImode && prev != NULL

50618

+ && GET_MODE (prev) == SImode)

50619

+ {

50620

+ PUT_MODE (prev, QImode);

50621

+ }

50622

+ delete_insn (insn);

50623

+ }

50624

}

50625

}

50626

}

50627

@@ -5498,6 +5528,9 @@

50628

#undef TARGET_RTX_COSTS

50629

#define TARGET_RTX_COSTS tilegx_rtx_costs

50630

50631

+#undef TARGET_EXPAND_TO_RTL_HOOK

50632

+#define TARGET_EXPAND_TO_RTL_HOOK tilegx_expand_to_rtl_hook

50633

+

50634

#undef TARGET_SHIFT_TRUNCATION_MASK

50635

#define TARGET_SHIFT_TRUNCATION_MASK tilegx_shift_truncation_mask

50636

50637

Index: gcc/config/sh/predicates.md

50638

===================================================================

50639

--- a/src/gcc/config/sh/predicates.md (.../tags/gcc_4_8_2_release)

50640

+++ b/src/gcc/config/sh/predicates.md (.../branches/gcc-4_8-branch)

50641

@@ -389,6 +389,12 @@

50642

XEXP (XEXP (op, 0), 1),

50643

TARGET_SH2A, true)")))

50644

50645

+;; Returns true if OP is a displacement address that can fit into a

50646

+;; 16 bit (non-SH2A) memory load / store insn.

50647

+(define_predicate "short_displacement_mem_operand"

50648

+ (match_test "sh_disp_addr_displacement (op)

50649

+ <= sh_max_mov_insn_displacement (GET_MODE (op), false)"))

50650

+

50651

;; Returns 1 if the operand can be used in an SH2A movu.{b|w} insn.

50652

(define_predicate "zero_extend_movu_operand"

50653

(and (match_operand 0 "displacement_mem_operand")

50654

@@ -413,6 +419,11 @@

50655

if (t_reg_operand (op, mode))

50656

return 0;

50657

50658

+ /* Disallow PC relative QImode loads, since these is no insn to do that

50659

+ and an imm8 load should be used instead. */

50660

+ if (IS_PC_RELATIVE_LOAD_ADDR_P (op) && GET_MODE (op) == QImode)

50661

+ return false;

50662

+

50663

if (MEM_P (op))

50664

{

50665

rtx inside = XEXP (op, 0);

50666

Index: gcc/config/sh/sh-protos.h

50667

===================================================================

50668

--- a/src/gcc/config/sh/sh-protos.h (.../tags/gcc_4_8_2_release)

50669

+++ b/src/gcc/config/sh/sh-protos.h (.../branches/gcc-4_8-branch)

50670

@@ -159,6 +159,8 @@

50671

extern bool sh_cfun_trap_exit_p (void);

50672

extern rtx sh_find_equiv_gbr_addr (rtx cur_insn, rtx mem);

50673

extern int sh_eval_treg_value (rtx op);

50674

+extern HOST_WIDE_INT sh_disp_addr_displacement (rtx mem_op);

50675

+extern int sh_max_mov_insn_displacement (machine_mode mode, bool consider_sh2a);

50676

50677

/* Result value of sh_find_set_of_reg. */

50678

struct set_of_reg

50679

Index: gcc/config/sh/sh.c

50680

===================================================================

50681

--- a/src/gcc/config/sh/sh.c (.../tags/gcc_4_8_2_release)

50682

+++ b/src/gcc/config/sh/sh.c (.../branches/gcc-4_8-branch)

50683

@@ -24,6 +24,9 @@

50684

malloc & co, which are poisoned by "system.h". The proper solution is

50685

to include <cstdlib> in "system.h" instead of <stdlib.h>. */

50686

#include <cstdlib>

50687

+#include <sstream>

50688

+#include <vector>

50689

+#include <algorithm>

50690

50691

#include "config.h"

50692

#include "system.h"

50693

@@ -60,10 +63,6 @@

50694

#include "tm-constrs.h"

50695

#include "opts.h"

50696

50697

-#include <sstream>

50698

-#include <vector>

50699

-#include <algorithm>

50700

-

50701

int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch;

50702

50703

#define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)

50704

@@ -310,9 +309,7 @@

50705

static void sh_conditional_register_usage (void);

50706

static bool sh_legitimate_constant_p (enum machine_mode, rtx);

50707

static int mov_insn_size (enum machine_mode, bool);

50708

-static int max_mov_insn_displacement (enum machine_mode, bool);

50709

static int mov_insn_alignment_mask (enum machine_mode, bool);

50710

-static HOST_WIDE_INT disp_addr_displacement (rtx);

50711

static bool sequence_insn_p (rtx);

50712

static void sh_canonicalize_comparison (int *, rtx *, rtx *, bool);

50713

static void sh_canonicalize_comparison (enum rtx_code&, rtx&, rtx&,

50714

@@ -3628,8 +3625,8 @@

50715

50716

/* Determine the maximum possible displacement for a move insn for the

50717

specified mode. */

50718

-static int

50719

-max_mov_insn_displacement (enum machine_mode mode, bool consider_sh2a)

50720

+int

50721

+sh_max_mov_insn_displacement (machine_mode mode, bool consider_sh2a)

50722

{

50723

/* The 4 byte displacement move insns are the same as the 2 byte

50724

versions but take a 12 bit displacement. All we need to do is to

50725

@@ -3665,8 +3662,8 @@

50726

}

50727

50728

/* Return the displacement value of a displacement address. */

50729

-static inline HOST_WIDE_INT

50730

-disp_addr_displacement (rtx x)

50731

+HOST_WIDE_INT

50732

+sh_disp_addr_displacement (rtx x)

50733

{

50734

gcc_assert (satisfies_constraint_Sdd (x));

50735

return INTVAL (XEXP (XEXP (x, 0), 1));

50736

@@ -3703,12 +3700,12 @@

50737

HImode and QImode loads/stores with displacement put pressure on

50738

R0 which will most likely require another reg copy. Thus account

50739

a higher cost for that. */

50740

- if (offset > 0 && offset <= max_mov_insn_displacement (mode, false))

50741

+ if (offset > 0 && offset <= sh_max_mov_insn_displacement (mode, false))

50742

return (mode == HImode || mode == QImode) ? 2 : 1;

50743

50744

/* The displacement would fit into a 4 byte move insn (SH2A). */

50745

if (TARGET_SH2A

50746

- && offset > 0 && offset <= max_mov_insn_displacement (mode, true))

50747

+ && offset > 0 && offset <= sh_max_mov_insn_displacement (mode, true))

50748

return 2;

50749

50750

/* The displacement is probably out of range and will require extra

50751

@@ -10218,7 +10215,7 @@

50752

else

50753

{

50754

const HOST_WIDE_INT offset = INTVAL (op);

50755

- const int max_disp = max_mov_insn_displacement (mode, consider_sh2a);

50756

+ const int max_disp = sh_max_mov_insn_displacement (mode, consider_sh2a);

50757

const int align_mask = mov_insn_alignment_mask (mode, consider_sh2a);

50758

50759

/* If the mode does not support any displacement always return false.

50760

@@ -10404,7 +10401,7 @@

50761

effectively disable the small displacement insns. */

50762

const int mode_sz = GET_MODE_SIZE (mode);

50763

const int mov_insn_sz = mov_insn_size (mode, false);

50764

- const int max_disp = max_mov_insn_displacement (mode, false);

50765

+ const int max_disp = sh_max_mov_insn_displacement (mode, false);

50766

const int max_disp_next = max_disp + mov_insn_sz;

50767

HOST_WIDE_INT align_modifier = offset > 127 ? mov_insn_sz : 0;

50768

HOST_WIDE_INT offset_adjust;

50769

@@ -13165,7 +13162,8 @@

50770

the insns must have the appropriate alternatives. */

50771

if ((mode == QImode || mode == HImode) && rclass != R0_REGS

50772

&& satisfies_constraint_Sdd (x)

50773

- && disp_addr_displacement (x) <= max_mov_insn_displacement (mode, false))

50774

+ && sh_disp_addr_displacement (x)

50775

+ <= sh_max_mov_insn_displacement (mode, false))

50776

return R0_REGS;

50777

50778

/* When reload is trying to address a QImode or HImode subreg on the stack,

50779

Index: gcc/config/sh/constraints.md

50780

===================================================================

50781

--- a/src/gcc/config/sh/constraints.md (.../tags/gcc_4_8_2_release)

50782

+++ b/src/gcc/config/sh/constraints.md (.../branches/gcc-4_8-branch)

50783

@@ -221,6 +221,7 @@

50784

(define_constraint "Q"

50785

"A pc relative load operand."

50786

(and (match_code "mem")

50787

+ (match_test "GET_MODE (op) != QImode")

50788

(match_test "IS_PC_RELATIVE_LOAD_ADDR_P (XEXP (op, 0))")))

50789

50790

(define_constraint "Bsc"

50791

@@ -295,13 +296,15 @@

50792

50793

(define_memory_constraint "Sdd"

50794

"A memory reference that uses displacement addressing."

50795

- (and (match_test "MEM_P (op) && GET_CODE (XEXP (op, 0)) == PLUS")

50796

+ (and (match_code "mem")

50797

+ (match_test "GET_CODE (XEXP (op, 0)) == PLUS")

50798

(match_test "REG_P (XEXP (XEXP (op, 0), 0))")

50799

(match_test "CONST_INT_P (XEXP (XEXP (op, 0), 1))")))

50800

50801

(define_memory_constraint "Snd"

50802

"A memory reference that excludes displacement addressing."

50803

- (match_test "! satisfies_constraint_Sdd (op)"))

50804

+ (and (match_code "mem")

50805

+ (match_test "! satisfies_constraint_Sdd (op)")))

50806

50807

(define_memory_constraint "Sbv"

50808

"A memory reference, as used in SH2A bclr.b, bset.b, etc."

50809

Index: gcc/config/sh/sh.md

50810

===================================================================

50811

--- a/src/gcc/config/sh/sh.md (.../tags/gcc_4_8_2_release)

50812

+++ b/src/gcc/config/sh/sh.md (.../branches/gcc-4_8-branch)

50813

@@ -2152,6 +2152,7 @@

50814

(udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))

50815

(clobber (reg:SI T_REG))

50816

(clobber (reg:SI PR_REG))

50817

+ (clobber (reg:SI R1_REG))

50818

(clobber (reg:SI R4_REG))

50819

(use (match_operand:SI 1 "arith_reg_operand" "r"))]

50820

"TARGET_SH1 && TARGET_DIVIDE_CALL_DIV1"

50821

@@ -6831,34 +6832,9 @@

50822

prepare_move_operands (operands, QImode);

50823

})

50824

50825

-;; If movqi_reg_reg is specified as an alternative of movqi, movqi will be

50826

-;; selected to copy QImode regs. If one of them happens to be allocated

50827

-;; on the stack, reload will stick to movqi insn and generate wrong

50828

-;; displacement addressing because of the generic m alternatives.

50829

-;; With the movqi_reg_reg being specified before movqi it will be initially

50830

-;; picked to load/store regs. If the regs regs are on the stack reload

50831

-;; try other insns and not stick to movqi_reg_reg, unless there were spilled

50832

-;; pseudos in which case 'm' constraints pertain.

50833

-;; The same applies to the movhi variants.

50834

-;;

50835

-;; Notice, that T bit is not allowed as a mov src operand here. This is to

50836

-;; avoid things like (set (reg:QI) (subreg:QI (reg:SI T_REG) 0)), which

50837

-;; introduces zero extensions after T bit stores and redundant reg copies.

50838

-;;

50839

-;; FIXME: We can't use 'arith_reg_operand' (which disallows T_REG) as a

50840

-;; predicate for the mov src operand because reload will have trouble

50841

-;; reloading MAC subregs otherwise. For that probably special patterns

50842

-;; would be required.

50843

-(define_insn "*mov<mode>_reg_reg"

50844

- [(set (match_operand:QIHI 0 "arith_reg_dest" "=r,m,*z")

50845

- (match_operand:QIHI 1 "register_operand" "r,*z,m"))]

50846

- "TARGET_SH1 && !t_reg_operand (operands[1], VOIDmode)"

50847

- "@

50848

- mov %1,%0

50849

- mov.<bw> %1,%0

50850

- mov.<bw> %1,%0"

50851

- [(set_attr "type" "move,store,load")])

50852

-

50853

+;; Specifying the displacement addressing load / store patterns separately

50854

+;; before the generic movqi / movhi pattern allows controlling the order

50855

+;; in which load / store insns are selected in a more fine grained way.

50856

;; FIXME: The non-SH2A and SH2A variants should be combined by adding

50857

;; "enabled" attribute as it is done in other targets.

50858

(define_insn "*mov<mode>_store_mem_disp04"

50859

@@ -6908,38 +6884,44 @@

50860

[(set_attr "type" "load")

50861

(set_attr "length" "2,2,4")])

50862

50863

-;; The m constraints basically allow any kind of addresses to be used with any

50864

-;; source/target register as the other operand. This is not true for

50865

-;; displacement addressing modes on anything but SH2A. That's why the

50866

-;; specialized load/store insns are specified above.

50867

-(define_insn "*movqi"

50868

- [(set (match_operand:QI 0 "general_movdst_operand" "=r,r,m,r,l")

50869

- (match_operand:QI 1 "general_movsrc_operand" "i,m,r,l,r"))]

50870

+;; The order of the constraint alternatives is important here.

50871

+;; Q/r has to come first, otherwise PC relative loads might wrongly get

50872

+;; placed into delay slots. Since there is no QImode PC relative load, the

50873

+;; Q constraint and general_movsrc_operand will reject it for QImode.

50874

+;; The Snd alternatives should come before Sdd in order to avoid a preference

50875

+;; of using r0 als the register operand for addressing modes other than

50876

+;; displacement addressing.

50877

+;; The Sdd alternatives allow only r0 as register operand, even though on

50878

+;; SH2A any register could be allowed by switching to a 32 bit insn.

50879

+;; Generally sticking to the r0 is preferrable, since it generates smaller

50880

+;; code. Obvious r0 reloads can then be eliminated with a peephole on SH2A.

50881

+(define_insn "*mov<mode>"

50882

+ [(set (match_operand:QIHI 0 "general_movdst_operand"

50883

+ "=r,r,r,Snd,r, Sdd,z, r,l")

50884

+ (match_operand:QIHI 1 "general_movsrc_operand"

50885

+ "Q,r,i,r, Snd,z, Sdd,l,r"))]

50886

"TARGET_SH1

50887

- && (arith_reg_operand (operands[0], QImode)

50888

- || arith_reg_operand (operands[1], QImode))"

50889

+ && (arith_reg_operand (operands[0], <MODE>mode)

50890

+ || arith_reg_operand (operands[1], <MODE>mode))"

50891

"@

50892

+ mov.<bw> %1,%0

50893

mov %1,%0

50894

- mov.b %1,%0

50895

- mov.b %1,%0

50896

- sts %1,%0

50897

- lds %1,%0"

50898

- [(set_attr "type" "movi8,load,store,prget,prset")])

50899

-

50900

-(define_insn "*movhi"

50901

- [(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,m,r,l")

50902

- (match_operand:HI 1 "general_movsrc_operand" "Q,i,m,r,l,r"))]

50903

- "TARGET_SH1

50904

- && (arith_reg_operand (operands[0], HImode)

50905

- || arith_reg_operand (operands[1], HImode))"

50906

- "@

50907

- mov.w %1,%0

50908

mov %1,%0

50909

- mov.w %1,%0

50910

- mov.w %1,%0

50911

+ mov.<bw> %1,%0

50912

+ mov.<bw> %1,%0

50913

+ mov.<bw> %1,%0

50914

+ mov.<bw> %1,%0

50915

sts %1,%0

50916

lds %1,%0"

50917

- [(set_attr "type" "pcload,movi8,load,store,prget,prset")])

50918

+ [(set_attr "type" "pcload,move,movi8,store,load,store,load,prget,prset")

50919

+ (set (attr "length")

50920

+ (cond [(and (match_operand 0 "displacement_mem_operand")

50921

+ (not (match_operand 0 "short_displacement_mem_operand")))

50922

+ (const_int 4)

50923

+ (and (match_operand 1 "displacement_mem_operand")

50924

+ (not (match_operand 1 "short_displacement_mem_operand")))

50925

+ (const_int 4)]

50926

+ (const_int 2)))])

50927

50928

(define_insn "*movqi_media"

50929

[(set (match_operand:QI 0 "general_movdst_operand" "=r,r,r,m")

50930

@@ -8427,11 +8409,9 @@

50931

50932

while (true)

50933

{

50934

- /* It's not safe to go beyond the current basic block after reload. */

50935

set_of_reg s1 = sh_find_set_of_reg (tested_reg, s0.insn,

50936

- reload_completed

50937

- ? prev_nonnote_insn_bb

50938

- : prev_nonnote_insn);

50939

+ prev_nonnote_insn);

50940

+

50941

if (s1.set_src == NULL_RTX)

50942

break;

50943

50944

@@ -8449,15 +8429,25 @@

50945

continue;

50946

}

50947

50948

- /* It's only safe to remove the testing insn if the T bit is not

50949

- modified between the testing insn and the insn that stores the

50950

- T bit. Notice that some T bit stores such as negc also modify

50951

- the T bit. */

50952

- if (modified_between_p (get_t_reg_rtx (), s1.insn, testing_insn)

50953

- || modified_in_p (get_t_reg_rtx (), s1.insn))

50954

- operands[2] = NULL_RTX;

50955

+ /* It's only safe to remove the testing insn if the T bit is not

50956

+ modified between the testing insn and the insn that stores the

50957

+ T bit. Notice that some T bit stores such as negc also modify

50958

+ the T bit. */

50959

+ if (modified_between_p (get_t_reg_rtx (), s1.insn, testing_insn)

50960

+ || modified_in_p (get_t_reg_rtx (), s1.insn)

50961

+ || !no_labels_between_p (s1.insn, testing_insn))

50962

+ operands[2] = NULL_RTX;

50963

+ else

50964

+ {

50965

+ /* If the insn that sets the tested reg has a REG_DEAD note on

50966

+ the T bit remove that note since we're extending the usage

50967

+ of the T bit. */

50968

+ rtx n = find_regno_note (s1.insn, REG_DEAD, T_REG);

50969

+ if (n != NULL_RTX)

50970

+ remove_note (s1.insn, n);

50971

+ }

50972

50973

- break;

50974

+ break;

50975

}

50976

50977

if (operands[2] == NULL_RTX)

50978

Index: gcc/config/sh/sh.opt

50979

===================================================================

50980

--- a/src/gcc/config/sh/sh.opt (.../tags/gcc_4_8_2_release)

50981

+++ b/src/gcc/config/sh/sh.opt (.../branches/gcc-4_8-branch)

50982

@@ -21,7 +21,7 @@

50983

;; Used for various architecture options.

50984

Mask(SH_E)

50985

50986

-;; Set if the default precision of th FPU is single.

50987

+;; Set if the default precision of the FPU is single.

50988

Mask(FPU_SINGLE)

50989

50990

;; Set if the a double-precision FPU is present but is restricted to

50991

Index: gcc/config/microblaze/predicates.md

50992

===================================================================

50993

--- a/src/gcc/config/microblaze/predicates.md (.../tags/gcc_4_8_2_release)

50994

+++ b/src/gcc/config/microblaze/predicates.md (.../branches/gcc-4_8-branch)

50995

@@ -85,6 +85,10 @@

50996

(ior (match_operand 0 "const_0_operand")

50997

(match_operand 0 "register_operand")))

50998

50999

+(define_predicate "reg_or_mem_operand"

51000

+ (ior (match_operand 0 "memory_operand")

51001

+ (match_operand 0 "register_operand")))

51002

+

51003

;; Return if the operand is either the PC or a label_ref.

51004

(define_special_predicate "pc_or_label_operand"

51005

(ior (match_code "pc,label_ref")

51006

@@ -119,3 +123,7 @@

51007

;; Test for valid PIC call operand

51008

(define_predicate "call_insn_plt_operand"

51009

(match_test "PLT_ADDR_P (op)"))

51010

+

51011

+;; Return if the code of this rtx pattern is a comparison.

51012

+(define_predicate "cmp_op"

51013

+ (match_code "gt,ge,gtu,geu,lt,le,ltu,leu"))

51014

Index: gcc/config/microblaze/microblaze.md

51015

===================================================================

51016

--- a/src/gcc/config/microblaze/microblaze.md (.../tags/gcc_4_8_2_release)

51017

+++ b/src/gcc/config/microblaze/microblaze.md (.../branches/gcc-4_8-branch)

51018

@@ -74,7 +74,7 @@

51019

;; bshift Shift operations

51020

51021

(define_attr "type"

51022

- "unknown,branch,jump,call,load,store,move,arith,darith,imul,idiv,icmp,multi,nop,no_delay_arith,no_delay_load,no_delay_store,no_delay_imul,no_delay_move,bshift,fadd,frsub,fmul,fdiv,fcmp,fsl,fsqrt,fcvt"

51023

+ "unknown,branch,jump,call,load,store,move,arith,darith,imul,idiv,icmp,multi,nop,no_delay_arith,no_delay_load,no_delay_store,no_delay_imul,no_delay_move,bshift,fadd,frsub,fmul,fdiv,fcmp,fsl,fsqrt,fcvt,trap"

51024

(const_string "unknown"))

51025

51026

;; Main data type used by the insn

51027

@@ -365,7 +365,8 @@

51028

[(set (match_operand:HI 0 "register_operand" "=r")

51029

(bswap:HI (match_operand:HI 1 "register_operand" "r")))]

51030

"TARGET_REORDER"

51031

- "swaph %0, %1"

51032

+ "swapb %0, %1

51033

+ swaph %0, %0"

51034

)

51035

51036

;;----------------------------------------------------------------

51037

@@ -1118,6 +1119,18 @@

51038

}

51039

)

51040

51041

+;;Load and store reverse

51042

+(define_insn "movsi4_rev"

51043

+ [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Q")

51044

+ (bswap:SI (match_operand:SF 1 "reg_or_mem_operand" "Q,r")))]

51045

+ "TARGET_REORDER"

51046

+ "@

51047

+ lwr\t%0,%y1,r0

51048

+ swr\t%1,%y0,r0"

51049

+ [(set_attr "type" "load,store")

51050

+ (set_attr "mode" "SI")

51051

+ (set_attr "length" "4,4")])

51052

+

51053

;; 32-bit floating point moves

51054

51055

(define_expand "movsf"

51056

@@ -1472,7 +1485,7 @@

51057

(set_attr "length" "124")]

51058

)

51059

51060

-(define_insn "*ashlri_reg"

51061

+(define_insn "*ashrsi_reg"

51062

[(set (match_operand:SI 0 "register_operand" "=&d")

51063

(ashiftrt:SI (match_operand:SI 1 "register_operand" "d")

51064

(match_operand:SI 2 "register_operand" "d")))]

51065

@@ -1561,7 +1574,7 @@

51066

(set_attr "length" "124")]

51067

)

51068

51069

-(define_insn "*lshlri_reg"

51070

+(define_insn "*lshrsi_reg"

51071

[(set (match_operand:SI 0 "register_operand" "=&d")

51072

(lshiftrt:SI (match_operand:SI 1 "register_operand" "d")

51073

(match_operand:SI 2 "register_operand" "d")))]

51074

@@ -1622,34 +1635,12 @@

51075

(set_attr "length" "4")]

51076

)

51077

51078

-(define_insn "signed_compare"

51079

- [(set (match_operand:SI 0 "register_operand" "=d")

51080

- (unspec

51081

- [(match_operand:SI 1 "register_operand" "d")

51082

- (match_operand:SI 2 "register_operand" "d")] UNSPEC_CMP))]

51083

- ""

51084

- "cmp\t%0,%1,%2"

51085

- [(set_attr "type" "arith")

51086

- (set_attr "mode" "SI")

51087

- (set_attr "length" "4")])

51088

-

51089

-(define_insn "unsigned_compare"

51090

- [(set (match_operand:SI 0 "register_operand" "=d")

51091

- (unspec

51092

- [(match_operand:SI 1 "register_operand" "d")

51093

- (match_operand:SI 2 "register_operand" "d")] UNSPEC_CMPU))]

51094

- ""

51095

- "cmpu\t%0,%1,%2"

51096

- [(set_attr "type" "arith")

51097

- (set_attr "mode" "SI")

51098

- (set_attr "length" "4")])

51099

-

51100

;;----------------------------------------------------------------

51101

;; Setting a register from an floating point comparison.

51102

;;----------------------------------------------------------------

51103

(define_insn "cstoresf4"

51104

[(set (match_operand:SI 0 "register_operand" "=r")

51105

- (match_operator 1 "comparison_operator"

51106

+ (match_operator:SI 1 "ordered_comparison_operator"

51107

[(match_operand:SF 2 "register_operand" "r")

51108

(match_operand:SF 3 "register_operand" "r")]))]

51109

"TARGET_HARD_FLOAT"

51110

@@ -1678,7 +1669,7 @@

51111

51112

(define_expand "cbranchsf4"

51113

[(set (pc)

51114

- (if_then_else (match_operator 0 "comparison_operator"

51115

+ (if_then_else (match_operator 0 "ordered_comparison_operator"

51116

[(match_operand:SF 1 "register_operand")

51117

(match_operand:SF 2 "register_operand")])

51118

(label_ref (match_operand 3 ""))

51119

@@ -1717,6 +1708,47 @@

51120

(set_attr "length" "4")]

51121

)

51122

51123

+(define_insn "branch_compare"

51124

+ [(set (pc)

51125

+ (if_then_else (match_operator:SI 0 "cmp_op"

51126

+ [(match_operand:SI 1 "register_operand" "d")

51127

+ (match_operand:SI 2 "register_operand" "d")

51128

+ ])

51129

+ (label_ref (match_operand 3))

51130

+ (pc)))

51131

+ (clobber(reg:SI R_TMP))]

51132

+ ""

51133

+ {

51134

+ operands[4] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);

51135

+ enum rtx_code code = GET_CODE (operands[0]);

51136

+

51137

+ if (code == GT || code == LE)

51138

+ {

51139

+ output_asm_insn ("cmp\tr18,%z1,%z2", operands);

51140

+ code = swap_condition (code);

51141

+ }

51142

+ else if (code == GTU || code == LEU)

51143

+ {

51144

+ output_asm_insn ("cmpu\tr18,%z1,%z2", operands);

51145

+ code = swap_condition (code);

51146

+ }

51147

+ else if (code == GE || code == LT)

51148

+ {

51149

+ output_asm_insn ("cmp\tr18,%z2,%z1", operands);

51150

+ }

51151

+ else if (code == GEU || code == LTU)

51152

+ {

51153

+ output_asm_insn ("cmpu\tr18,%z2,%z1", operands);

51154

+ }

51155

+

51156

+ operands[0] = gen_rtx_fmt_ee (signed_condition (code), SImode, operands[4], const0_rtx);

51157

+ return "b%C0i%?\tr18,%3";

51158

+ }

51159

+ [(set_attr "type" "branch")

51160

+ (set_attr "mode" "none")

51161

+ (set_attr "length" "12")]

51162

+)

51163

+

51164

;;----------------------------------------------------------------

51165

;; Unconditional branches

51166

;;----------------------------------------------------------------

51167

@@ -2201,6 +2233,14 @@

51168

(set_attr "mode" "none")

51169

(set_attr "length" "4")])

51170

51171

+;; Trap instruction pattern for __builtin_trap. Same as the glibc ABORT_INSTRUCTION

51172

+(define_insn "trap"

51173

+ [(trap_if (const_int 1) (const_int 0))]

51174

+ ""

51175

+ "brki\tr0,-1"

51176

+ [(set_attr "type" "trap")]

51177

+)

51178

+

51179

;; The insn to set GOT. The hardcoded number "8" accounts for $pc difference

51180

;; between "mfs" and "addik" instructions.

51181

(define_insn "set_got"

51182

Index: gcc/config/microblaze/microblaze.c

51183

===================================================================

51184

--- a/src/gcc/config/microblaze/microblaze.c (.../tags/gcc_4_8_2_release)

51185

+++ b/src/gcc/config/microblaze/microblaze.c (.../branches/gcc-4_8-branch)

51186

@@ -1609,21 +1609,28 @@

51187

microblaze_version_to_int (const char *version)

51188

{

51189

const char *p, *v;

51190

- const char *tmpl = "vX.YY.Z";

51191

+ const char *tmpl = "vXX.YY.Z";

51192

int iver = 0;

51193

51194

p = version;

51195

v = tmpl;

51196

51197

- while (*v)

51198

+ while (*p)

51199

{

51200

if (*v == 'X')

51201

{ /* Looking for major */

51202

- if (!(*p >= '0' && *p <= '9'))

51203

- return -1;

51204

- iver += (int) (*p - '0');

51205

- iver *= 10;

51206

- }

51207

+ if (*p == '.')

51208

+ {

51209

+ *v++;

51210

+ }

51211

+ else

51212

+ {

51213

+ if (!(*p >= '0' && *p <= '9'))

51214

+ return -1;

51215

+ iver += (int) (*p - '0');

51216

+ iver *= 10;

51217

+ }

51218

+ }

51219

else if (*v == 'Y')

51220

{ /* Looking for minor */

51221

if (!(*p >= '0' && *p <= '9'))

51222

@@ -3064,6 +3071,73 @@

51223

return result;

51224

}

51225

51226

+static void

51227

+microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,

51228

+ HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,

51229

+ tree function)

51230

+{

51231

+ rtx this_rtx, insn, funexp;

51232

+

51233

+ reload_completed = 1;

51234

+ epilogue_completed = 1;

51235

+

51236

+ /* Mark the end of the (empty) prologue. */

51237

+ emit_note (NOTE_INSN_PROLOGUE_END);

51238

+

51239

+ /* Find the "this" pointer. If the function returns a structure,

51240

+ the structure return pointer is in MB_ABI_FIRST_ARG_REGNUM. */

51241

+ if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))

51242

+ this_rtx = gen_rtx_REG (Pmode, (MB_ABI_FIRST_ARG_REGNUM + 1));

51243

+ else

51244

+ this_rtx = gen_rtx_REG (Pmode, MB_ABI_FIRST_ARG_REGNUM);

51245

+

51246

+ /* Apply the constant offset, if required. */

51247

+ if (delta)

51248

+ emit_insn (gen_addsi3 (this_rtx, this_rtx, GEN_INT (delta)));

51249

+

51250

+ /* Apply the offset from the vtable, if required. */

51251

+ if (vcall_offset)

51252

+ {

51253

+ rtx vcall_offset_rtx = GEN_INT (vcall_offset);

51254

+ rtx temp1 = gen_rtx_REG (Pmode, MB_ABI_TEMP1_REGNUM);

51255

+

51256

+ emit_move_insn (temp1, gen_rtx_MEM (Pmode, this_rtx));

51257

+

51258

+ rtx loc = gen_rtx_PLUS (Pmode, temp1, vcall_offset_rtx);

51259

+ emit_move_insn (temp1, gen_rtx_MEM (Pmode, loc));

51260

+

51261

+ emit_insn (gen_addsi3 (this_rtx, this_rtx, temp1));

51262

+ }

51263

+

51264

+ /* Generate a tail call to the target function. */

51265

+ if (!TREE_USED (function))

51266

+ {

51267

+ assemble_external (function);

51268

+ TREE_USED (function) = 1;

51269

+ }

51270

+

51271

+ funexp = XEXP (DECL_RTL (function), 0);

51272

+ rtx temp2 = gen_rtx_REG (Pmode, MB_ABI_TEMP2_REGNUM);

51273

+

51274

+ if (flag_pic)

51275

+ emit_move_insn (temp2, expand_pic_symbol_ref (Pmode, funexp));

51276

+ else

51277

+ emit_move_insn (temp2, funexp);

51278

+

51279

+ emit_insn (gen_indirect_jump (temp2));

51280

+

51281

+ /* Run just enough of rest_of_compilation. This sequence was

51282

+ "borrowed" from rs6000.c. */

51283

+ insn = get_insns ();

51284

+ shorten_branches (insn);

51285

+ final_start_function (insn, file, 1);

51286

+ final (insn, file, 1);

51287

+ final_end_function ();

51288

+

51289

+ reload_completed = 0;

51290

+ epilogue_completed = 0;

51291

+}

51292

+

51293

bool

51294

microblaze_expand_move (enum machine_mode mode, rtx operands[])

51295

{

51296

@@ -3234,67 +3308,47 @@

51297

emit_move_insn (mem, fnaddr);

51298

}

51299

51300

-/* Emit instruction to perform compare.

51301

- cmp is (compare_op op0 op1). */

51302

-static rtx

51303

-microblaze_emit_compare (enum machine_mode mode, rtx cmp, enum rtx_code *cmp_code)

51304

+/* Generate conditional branch -- first, generate test condition,

51305

+ second, generate correct branch instruction. */

51306

+

51307

+void

51308

+microblaze_expand_conditional_branch (enum machine_mode mode, rtx operands[])

51309

{

51310

- rtx cmp_op0 = XEXP (cmp, 0);

51311

- rtx cmp_op1 = XEXP (cmp, 1);

51312

+ enum rtx_code code = GET_CODE (operands[0]);

51313

+ rtx cmp_op0 = operands[1];

51314

+ rtx cmp_op1 = operands[2];

51315

+ rtx label1 = operands[3];

51316

rtx comp_reg = gen_reg_rtx (SImode);

51317

- enum rtx_code code = *cmp_code;

51318

-

51319

+ rtx condition;

51320

+

51321

gcc_assert ((GET_CODE (cmp_op0) == REG) || (GET_CODE (cmp_op0) == SUBREG));

51322

51323

/* If comparing against zero, just test source reg. */

51324

- if (cmp_op1 == const0_rtx)

51325

- return cmp_op0;

51326

+ if (cmp_op1 == const0_rtx)

51327

+ {

51328

+ comp_reg = cmp_op0;

51329

+ condition = gen_rtx_fmt_ee (signed_condition (code), SImode, comp_reg, const0_rtx);

51330

+ emit_jump_insn (gen_condjump (condition, label1));

51331

+ }

51332

51333

- if (code == EQ || code == NE)

51334

+ else if (code == EQ || code == NE)

51335

{

51336

/* Use xor for equal/not-equal comparison. */

51337

emit_insn (gen_xorsi3 (comp_reg, cmp_op0, cmp_op1));

51338

+ condition = gen_rtx_fmt_ee (signed_condition (code), SImode, comp_reg, const0_rtx);

51339

+ emit_jump_insn (gen_condjump (condition, label1));

51340

}

51341

- else if (code == GT || code == GTU || code == LE || code == LEU)

51342

+ else

51343

{

51344

- /* MicroBlaze compare is not symmetrical. */

51345

- /* Swap argument order. */

51346

+ /* Generate compare and branch in single instruction. */

51347

cmp_op1 = force_reg (mode, cmp_op1);

51348

- if (code == GT || code == LE)

51349

- emit_insn (gen_signed_compare (comp_reg, cmp_op0, cmp_op1));

51350

- else

51351

- emit_insn (gen_unsigned_compare (comp_reg, cmp_op0, cmp_op1));

51352

- /* Translate test condition. */

51353

- *cmp_code = swap_condition (code);

51354

+ condition = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);

51355

+ emit_jump_insn (gen_branch_compare(condition, cmp_op0, cmp_op1, label1));

51356

}

51357

- else /* if (code == GE || code == GEU || code == LT || code == LTU) */

51358

- {

51359

- cmp_op1 = force_reg (mode, cmp_op1);

51360

- if (code == GE || code == LT)

51361

- emit_insn (gen_signed_compare (comp_reg, cmp_op1, cmp_op0));

51362

- else

51363

- emit_insn (gen_unsigned_compare (comp_reg, cmp_op1, cmp_op0));

51364

- }

51365

-

51366

- return comp_reg;

51367

}

51368

51369

-/* Generate conditional branch -- first, generate test condition,

51370

- second, generate correct branch instruction. */

51371

51372

void

51373

-microblaze_expand_conditional_branch (enum machine_mode mode, rtx operands[])

51374

-{

51375

- enum rtx_code code = GET_CODE (operands[0]);

51376

- rtx comp;

51377

- rtx condition;

51378

-

51379

- comp = microblaze_emit_compare (mode, operands[0], &code);

51380

- condition = gen_rtx_fmt_ee (signed_condition (code), SImode, comp, const0_rtx);

51381

- emit_jump_insn (gen_condjump (condition, operands[3]));

51382

-}

51383

-

51384

-void

51385

microblaze_expand_conditional_branch_sf (rtx operands[])

51386

{

51387

rtx condition;

51388

@@ -3501,6 +3555,12 @@

51389

#undef TARGET_SECONDARY_RELOAD

51390

#define TARGET_SECONDARY_RELOAD microblaze_secondary_reload

51391

51392

+#undef TARGET_ASM_OUTPUT_MI_THUNK

51393

+#define TARGET_ASM_OUTPUT_MI_THUNK microblaze_asm_output_mi_thunk

51394

+

51395

+#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK

51396

+#define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true

51397

+

51398

#undef TARGET_SCHED_ADJUST_COST

51399

#define TARGET_SCHED_ADJUST_COST microblaze_adjust_cost

51400

51401

Index: gcc/config/microblaze/microblaze.h

51402

===================================================================

51403

--- a/src/gcc/config/microblaze/microblaze.h (.../tags/gcc_4_8_2_release)

51404

+++ b/src/gcc/config/microblaze/microblaze.h (.../branches/gcc-4_8-branch)

51405

@@ -213,6 +213,12 @@

51406

#define STRICT_ALIGNMENT 1

51407

#define PCC_BITFIELD_TYPE_MATTERS 1

51408

51409

+#undef SIZE_TYPE

51410

+#define SIZE_TYPE "unsigned int"

51411

+

51412

+#undef PTRDIFF_TYPE

51413

+#define PTRDIFF_TYPE "int"

51414

+

51415

#define CONSTANT_ALIGNMENT(EXP, ALIGN) \

51416

((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \

51417

&& (ALIGN) < BITS_PER_WORD \

51418

@@ -407,9 +413,6 @@

51419

|| GET_MODE (X) == VOIDmode) \

51420

? (GR_REGS) : (CLASS))))

51421

51422

-#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \

51423

- (GET_MODE_CLASS (MODE) == MODE_INT)

51424

-

51425

/* Stack layout; function entry, exit and calling. */

51426

51427

#define STACK_GROWS_DOWNWARD

51428

Index: gcc/config/avr/avr.c

51429

===================================================================

51430

--- a/src/gcc/config/avr/avr.c (.../tags/gcc_4_8_2_release)

51431

+++ b/src/gcc/config/avr/avr.c (.../branches/gcc-4_8-branch)

51432

@@ -587,10 +587,14 @@

51433

const char *name;

51434

51435

name = DECL_ASSEMBLER_NAME_SET_P (decl)

51436

- /* Remove the leading '*' added in set_user_assembler_name. */

51437

- ? 1 + IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))

51438

+ ? IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))

51439

: IDENTIFIER_POINTER (DECL_NAME (decl));

51440

51441

+ /* Skip a leading '*' that might still prefix the assembler name,

51442

+ e.g. in non-LTO runs. */

51443

+

51444

+ name = default_strip_name_encoding (name);

51445

+

51446

/* Silently ignore 'signal' if 'interrupt' is present. AVR-LibC startet

51447

using this when it switched from SIGNAL and INTERRUPT to ISR. */

51448

51449

@@ -6806,8 +6810,8 @@

51450

51451

/* Work out the shortest sequence. */

51452

51453

- avr_out_plus_1 (op, &len_minus, MINUS, &cc_plus, code_sat, sign, out_label);

51454

- avr_out_plus_1 (op, &len_plus, PLUS, &cc_minus, code_sat, sign, out_label);

51455

+ avr_out_plus_1 (op, &len_minus, MINUS, &cc_minus, code_sat, sign, out_label);

51456

+ avr_out_plus_1 (op, &len_plus, PLUS, &cc_plus, code_sat, sign, out_label);

51457

51458

if (plen)

51459

{

51460

Index: gcc/config/cris/cris.md

51461

===================================================================

51462

--- a/src/gcc/config/cris/cris.md (.../tags/gcc_4_8_2_release)

51463

+++ b/src/gcc/config/cris/cris.md (.../branches/gcc-4_8-branch)

51464

@@ -758,7 +758,7 @@

51465

(match_operand:SI 1 "const_int_operand" ""))

51466

(match_operand:SI 2 "register_operand" ""))])

51467

(match_operand 3 "register_operand" ""))

51468

- (set (match_operand:SI 4 "register_operand" "")

51469

+ (set (match_operand:SI 4 "cris_nonsp_register_operand" "")

51470

(plus:SI (mult:SI (match_dup 0)

51471

(match_dup 1))

51472

(match_dup 2)))])]

51473

@@ -859,7 +859,7 @@

51474

(match_operand:SI 0 "cris_bdap_operand" "")

51475

(match_operand:SI 1 "cris_bdap_operand" ""))])

51476

(match_operand 2 "register_operand" ""))

51477

- (set (match_operand:SI 3 "register_operand" "")

51478

+ (set (match_operand:SI 3 "cris_nonsp_register_operand" "")

51479

(plus:SI (match_dup 0) (match_dup 1)))])]

51480

"reload_completed && reg_overlap_mentioned_p (operands[3], operands[2])"

51481

[(set (match_dup 4) (match_dup 2))

51482

@@ -3960,7 +3960,7 @@

51483

;; up.

51484

51485

(define_split

51486

- [(set (match_operand 0 "register_operand" "")

51487

+ [(set (match_operand 0 "cris_nonsp_register_operand" "")

51488

(match_operator

51489

4 "cris_operand_extend_operator"

51490

[(match_operand 1 "register_operand" "")

51491

@@ -3990,7 +3990,7 @@

51492

;; Call this op-extend-split-rx=rz

51493

51494

(define_split

51495

- [(set (match_operand 0 "register_operand" "")

51496

+ [(set (match_operand 0 "cris_nonsp_register_operand" "")

51497

(match_operator

51498

4 "cris_plus_or_bound_operator"

51499

[(match_operand 1 "register_operand" "")

51500

@@ -4018,7 +4018,7 @@

51501

;; Call this op-extend-split-swapped

51502

51503

(define_split

51504

- [(set (match_operand 0 "register_operand" "")

51505

+ [(set (match_operand 0 "cris_nonsp_register_operand" "")

51506

(match_operator

51507

4 "cris_plus_or_bound_operator"

51508

[(match_operator

51509

@@ -4044,7 +4044,7 @@

51510

;; bound. Call this op-extend-split-swapped-rx=rz.

51511

51512

(define_split

51513

- [(set (match_operand 0 "register_operand" "")

51514

+ [(set (match_operand 0 "cris_nonsp_register_operand" "")

51515

(match_operator

51516

4 "cris_plus_or_bound_operator"

51517

[(match_operator

51518

@@ -4075,7 +4075,7 @@

51519

;; Call this op-extend.

51520

51521

(define_split

51522

- [(set (match_operand 0 "register_operand" "")

51523

+ [(set (match_operand 0 "cris_nonsp_register_operand" "")

51524

(match_operator

51525

3 "cris_orthogonal_operator"

51526

[(match_operand 1 "register_operand" "")

51527

@@ -4099,7 +4099,7 @@

51528

;; Call this op-split-rx=rz

51529

51530

(define_split

51531

- [(set (match_operand 0 "register_operand" "")

51532

+ [(set (match_operand 0 "cris_nonsp_register_operand" "")

51533

(match_operator

51534

3 "cris_commutative_orth_op"

51535

[(match_operand 2 "memory_operand" "")

51536

@@ -4123,7 +4123,7 @@

51537

;; Call this op-split-swapped.

51538

51539

(define_split

51540

- [(set (match_operand 0 "register_operand" "")

51541

+ [(set (match_operand 0 "cris_nonsp_register_operand" "")

51542

(match_operator

51543

3 "cris_commutative_orth_op"

51544

[(match_operand 1 "register_operand" "")

51545

@@ -4146,7 +4146,7 @@

51546

;; Call this op-split-swapped-rx=rz.

51547

51548

(define_split

51549

- [(set (match_operand 0 "register_operand" "")

51550

+ [(set (match_operand 0 "cris_nonsp_register_operand" "")

51551

(match_operator

51552

3 "cris_orthogonal_operator"

51553

[(match_operand 2 "memory_operand" "")

51554

@@ -4555,10 +4555,11 @@

51555

;; We're not allowed to generate copies of registers with different mode

51556

;; until after reload; copying pseudos upsets reload. CVS as of

51557

;; 2001-08-24, unwind-dw2-fde.c, _Unwind_Find_FDE ICE in

51558

-;; cselib_invalidate_regno.

51559

+;; cselib_invalidate_regno. Also, don't do this for the stack-pointer,

51560

+;; as we don't want it set temporarily to an invalid value.

51561

51562

(define_split ; indir_to_reg_split

51563

- [(set (match_operand 0 "register_operand" "")

51564

+ [(set (match_operand 0 "cris_nonsp_register_operand" "")

51565

(match_operand 1 "indirect_operand" ""))]

51566

"reload_completed

51567

&& REG_P (operands[0])

51568

@@ -4574,7 +4575,7 @@

51569

;; As the above, but MOVS and MOVU.

51570

51571

(define_split

51572

- [(set (match_operand 0 "register_operand" "")

51573

+ [(set (match_operand 0 "cris_nonsp_register_operand" "")

51574

(match_operator

51575

4 "cris_extend_operator"

51576

[(match_operand 1 "indirect_operand" "")]))]

51577

Index: gcc/config/cris/predicates.md

51578

===================================================================

51579

--- a/src/gcc/config/cris/predicates.md (.../tags/gcc_4_8_2_release)

51580

+++ b/src/gcc/config/cris/predicates.md (.../branches/gcc-4_8-branch)

51581

@@ -76,6 +76,10 @@

51582

(match_test "cris_simple_address_operand (XEXP (op, 0),

51583

Pmode)"))))

51584

51585

+(define_predicate "cris_nonsp_register_operand"

51586

+ (and (match_operand 0 "register_operand")

51587

+ (match_test "op != stack_pointer_rtx")))

51588

+

51589

;; The caller needs to use :SI.

51590

(define_predicate "cris_bdap_sign_extend_operand"

51591

; Disabled until <URL:http://gcc.gnu.org/ml/gcc-patches/2005-10/msg01376.html>

51592

Index: gcc/config/m68k/m68k.c

51593

===================================================================

51594

--- a/src/gcc/config/m68k/m68k.c (.../tags/gcc_4_8_2_release)

51595

+++ b/src/gcc/config/m68k/m68k.c (.../branches/gcc-4_8-branch)

51596

@@ -3325,12 +3325,12 @@

51597

latehalf[1] = adjust_address (operands[1], SImode, 0);

51598

}

51599

51600

- /* If insn is effectively movd N(sp),-(sp) then we will do the

51601

- high word first. We should use the adjusted operand 1 (which is N+4(sp))

51602

- for the low word as well, to compensate for the first decrement of sp. */

51603

+ /* If insn is effectively movd N(REG),-(REG) then we will do the high

51604

+ word first. We should use the adjusted operand 1 (which is N+4(REG))

51605

+ for the low word as well, to compensate for the first decrement of

51606

+ REG. */

51607

if (optype0 == PUSHOP

51608

- && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM

51609

- && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))

51610

+ && reg_overlap_mentioned_p (XEXP (XEXP (operands[0], 0), 0), operands[1]))

51611

operands[1] = middlehalf[1] = latehalf[1];

51612

51613

/* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),

51614

Index: gcc/config/aarch64/aarch64-simd.md

51615

===================================================================

51616

--- a/src/gcc/config/aarch64/aarch64-simd.md (.../tags/gcc_4_8_2_release)

51617

+++ b/src/gcc/config/aarch64/aarch64-simd.md (.../branches/gcc-4_8-branch)

51618

@@ -21,7 +21,7 @@

51619

51620

; Main data types used by the insntructions

51621

51622

-(define_attr "simd_mode" "unknown,none,V8QI,V16QI,V4HI,V8HI,V2SI,V4SI,V2DI,V2SF,V4SF,V2DF,OI,CI,XI,DI,DF,SI,HI,QI"

51623

+(define_attr "simd_mode" "unknown,none,V8QI,V16QI,V4HI,V8HI,V2SI,V4SI,V2DI,V2SF,V4SF,V2DF,OI,CI,XI,DI,DF,SI,SF,HI,QI"

51624

(const_string "unknown"))

51625

51626

51627

@@ -1548,12 +1548,12 @@

51628

51629

case LTU:

51630

case GEU:

51631

- emit_insn (gen_aarch64_cmhs<mode> (mask, operands[4], operands[5]));

51632

+ emit_insn (gen_aarch64_cmgeu<mode> (mask, operands[4], operands[5]));

51633

break;

51634

51635

case LEU:

51636

case GTU:

51637

- emit_insn (gen_aarch64_cmhi<mode> (mask, operands[4], operands[5]));

51638

+ emit_insn (gen_aarch64_cmgtu<mode> (mask, operands[4], operands[5]));

51639

break;

51640

51641

case NE:

51642

@@ -3034,48 +3034,181 @@

51643

)

51644

51645

51646

-;; cm(eq|ge|le|lt|gt)

51647

+;; cm(eq|ge|gt|lt|le)

51648

+;; Note, we have constraints for Dz and Z as different expanders

51649

+;; have different ideas of what should be passed to this pattern.

51650

51651

-(define_insn "aarch64_cm<cmp><mode>"

51652

+(define_insn "aarch64_cm<optab><mode>"

51653

[(set (match_operand:<V_cmp_result> 0 "register_operand" "=w,w")

51654

- (unspec:<V_cmp_result>

51655

- [(match_operand:VSDQ_I_DI 1 "register_operand" "w,w")

51656

- (match_operand:VSDQ_I_DI 2 "aarch64_simd_reg_or_zero" "w,Z")]

51657

- VCMP_S))]

51658

+ (neg:<V_cmp_result>

51659

+ (COMPARISONS:<V_cmp_result>

51660

+ (match_operand:VDQ 1 "register_operand" "w,w")

51661

+ (match_operand:VDQ 2 "aarch64_simd_reg_or_zero" "w,ZDz")

51662

+ )))]

51663

"TARGET_SIMD"

51664

"@

51665

- cm<cmp>\t%<v>0<Vmtype>, %<v>1<Vmtype>, %<v>2<Vmtype>

51666

- cm<cmp>\t%<v>0<Vmtype>, %<v>1<Vmtype>, #0"

51667

+ cm<n_optab>\t%<v>0<Vmtype>, %<v><cmp_1><Vmtype>, %<v><cmp_2><Vmtype>

51668

+ cm<optab>\t%<v>0<Vmtype>, %<v>1<Vmtype>, #0"

51669

[(set_attr "simd_type" "simd_cmp")

51670

(set_attr "simd_mode" "<MODE>")]

51671

)

51672

51673

-;; cm(hs|hi|tst)

51674

+(define_insn_and_split "aarch64_cm<optab>di"

51675

+ [(set (match_operand:DI 0 "register_operand" "=w,w,r")

51676

+ (neg:DI

51677

+ (COMPARISONS:DI

51678

+ (match_operand:DI 1 "register_operand" "w,w,r")

51679

+ (match_operand:DI 2 "aarch64_simd_reg_or_zero" "w,ZDz,r")

51680

+ )))]

51681

+ "TARGET_SIMD"

51682

+ "@

51683

+ cm<n_optab>\t%d0, %d<cmp_1>, %d<cmp_2>

51684

+ cm<optab>\t%d0, %d1, #0

51685

+ #"

51686

+ "reload_completed

51687

+ /* We need to prevent the split from

51688

+ happening in the 'w' constraint cases. */

51689

+ && GP_REGNUM_P (REGNO (operands[0]))

51690

+ && GP_REGNUM_P (REGNO (operands[1]))"

51691

+ [(set (reg:CC CC_REGNUM)

51692

+ (compare:CC

51693

+ (match_dup 1)

51694

+ (match_dup 2)))

51695

+ (set (match_dup 0)

51696

+ (neg:DI

51697

+ (COMPARISONS:DI

51698

+ (match_operand 3 "cc_register" "")

51699

+ (const_int 0))))]

51700

+ {

51701

+ enum machine_mode mode = SELECT_CC_MODE (<CMP>, operands[1], operands[2]);

51702

+ rtx cc_reg = aarch64_gen_compare_reg (<CMP>, operands[1], operands[2]);

51703

+ rtx comparison = gen_rtx_<CMP> (mode, operands[1], operands[2]);

51704

+ emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg));

51705

+ DONE;

51706

+ }

51707

+ [(set_attr "simd_type" "simd_cmp")

51708

+ (set_attr "simd_mode" "DI")]

51709

+)

51710

51711

-(define_insn "aarch64_cm<cmp><mode>"

51712

+;; cm(hs|hi)

51713

+

51714

+(define_insn "aarch64_cm<optab><mode>"

51715

[(set (match_operand:<V_cmp_result> 0 "register_operand" "=w")

51716

- (unspec:<V_cmp_result>

51717

- [(match_operand:VSDQ_I_DI 1 "register_operand" "w")

51718

- (match_operand:VSDQ_I_DI 2 "register_operand" "w")]

51719

- VCMP_U))]

51720

+ (neg:<V_cmp_result>

51721

+ (UCOMPARISONS:<V_cmp_result>

51722

+ (match_operand:VDQ 1 "register_operand" "w")

51723

+ (match_operand:VDQ 2 "register_operand" "w")

51724

+ )))]

51725

"TARGET_SIMD"

51726

- "cm<cmp>\t%<v>0<Vmtype>, %<v>1<Vmtype>, %<v>2<Vmtype>"

51727

+ "cm<n_optab>\t%<v>0<Vmtype>, %<v><cmp_1><Vmtype>, %<v><cmp_2><Vmtype>"

51728

[(set_attr "simd_type" "simd_cmp")

51729

(set_attr "simd_mode" "<MODE>")]

51730

)

51731

51732

-;; fcm(eq|ge|le|lt|gt)

51733

+(define_insn_and_split "aarch64_cm<optab>di"

51734

+ [(set (match_operand:DI 0 "register_operand" "=w,r")

51735

+ (neg:DI

51736

+ (UCOMPARISONS:DI

51737

+ (match_operand:DI 1 "register_operand" "w,r")

51738

+ (match_operand:DI 2 "aarch64_simd_reg_or_zero" "w,r")

51739

+ )))]

51740

+ "TARGET_SIMD"

51741

+ "@

51742

+ cm<n_optab>\t%d0, %d<cmp_1>, %d<cmp_2>

51743

+ #"

51744

+ "reload_completed

51745

+ /* We need to prevent the split from

51746

+ happening in the 'w' constraint cases. */

51747

+ && GP_REGNUM_P (REGNO (operands[0]))

51748

+ && GP_REGNUM_P (REGNO (operands[1]))"

51749

+ [(set (reg:CC CC_REGNUM)

51750

+ (compare:CC

51751

+ (match_dup 1)

51752

+ (match_dup 2)))

51753

+ (set (match_dup 0)

51754

+ (neg:DI

51755

+ (UCOMPARISONS:DI

51756

+ (match_operand 3 "cc_register" "")

51757

+ (const_int 0))))]

51758

+ {

51759

+ enum machine_mode mode = SELECT_CC_MODE (<CMP>, operands[1], operands[2]);

51760

+ rtx cc_reg = aarch64_gen_compare_reg (<CMP>, operands[1], operands[2]);

51761

+ rtx comparison = gen_rtx_<CMP> (mode, operands[1], operands[2]);

51762

+ emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg));

51763

+ DONE;

51764

+ }

51765

+ [(set_attr "simd_type" "simd_cmp")

51766

+ (set_attr "simd_mode" "DI")]

51767

+)

51768

51769

-(define_insn "aarch64_cm<cmp><mode>"

51770

+;; cmtst

51771

+

51772

+(define_insn "aarch64_cmtst<mode>"

51773

+ [(set (match_operand:<V_cmp_result> 0 "register_operand" "=w")

51774

+ (neg:<V_cmp_result>

51775

+ (ne:<V_cmp_result>

51776

+ (and:VDQ

51777

+ (match_operand:VDQ 1 "register_operand" "w")

51778

+ (match_operand:VDQ 2 "register_operand" "w"))

51779

+ (vec_duplicate:<V_cmp_result> (const_int 0)))))]

51780

+ "TARGET_SIMD"

51781

+ "cmtst\t%<v>0<Vmtype>, %<v>1<Vmtype>, %<v>2<Vmtype>"

51782

+ [(set_attr "simd_type" "simd_cmp")

51783

+ (set_attr "simd_mode" "<MODE>")]

51784

+)

51785

+

51786

+(define_insn_and_split "aarch64_cmtstdi"

51787

+ [(set (match_operand:DI 0 "register_operand" "=w,r")

51788

+ (neg:DI

51789

+ (ne:DI

51790

+ (and:DI

51791

+ (match_operand:DI 1 "register_operand" "w,r")

51792

+ (match_operand:DI 2 "register_operand" "w,r"))

51793

+ (const_int 0))))]

51794

+ "TARGET_SIMD"

51795

+ "@

51796

+ cmtst\t%d0, %d1, %d2

51797

+ #"

51798

+ "reload_completed

51799

+ /* We need to prevent the split from

51800

+ happening in the 'w' constraint cases. */

51801

+ && GP_REGNUM_P (REGNO (operands[0]))

51802

+ && GP_REGNUM_P (REGNO (operands[1]))"

51803

+ [(set (reg:CC_NZ CC_REGNUM)

51804

+ (compare:CC_NZ

51805

+ (and:DI (match_dup 1)

51806

+ (match_dup 2))

51807

+ (const_int 0)))

51808

+ (set (match_dup 0)

51809

+ (neg:DI

51810

+ (ne:DI

51811

+ (match_operand 3 "cc_register" "")

51812

+ (const_int 0))))]

51813

+ {

51814

+ rtx and_tree = gen_rtx_AND (DImode, operands[1], operands[2]);

51815

+ enum machine_mode mode = SELECT_CC_MODE (NE, and_tree, const0_rtx);

51816

+ rtx cc_reg = aarch64_gen_compare_reg (NE, and_tree, const0_rtx);

51817

+ rtx comparison = gen_rtx_NE (mode, and_tree, const0_rtx);

51818

+ emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg));

51819

+ DONE;

51820

+ }

51821

+ [(set_attr "simd_type" "simd_cmp")

51822

+ (set_attr "simd_mode" "DI")]

51823

+)

51824

+

51825

+;; fcm(eq|ge|gt|le|lt)

51826

+

51827

+(define_insn "aarch64_cm<optab><mode>"

51828

[(set (match_operand:<V_cmp_result> 0 "register_operand" "=w,w")

51829

- (unspec:<V_cmp_result>

51830

- [(match_operand:VDQF 1 "register_operand" "w,w")

51831

- (match_operand:VDQF 2 "aarch64_simd_reg_or_zero" "w,Dz")]

51832

- VCMP_S))]

51833

+ (neg:<V_cmp_result>

51834

+ (COMPARISONS:<V_cmp_result>

51835

+ (match_operand:VALLF 1 "register_operand" "w,w")

51836

+ (match_operand:VALLF 2 "aarch64_simd_reg_or_zero" "w,YDz")

51837

+ )))]

51838

"TARGET_SIMD"

51839

"@

51840

- fcm<cmp>\t%<v>0<Vmtype>, %<v>1<Vmtype>, %<v>2<Vmtype>

51841

- fcm<cmp>\t%<v>0<Vmtype>, %<v>1<Vmtype>, 0"

51842

+ fcm<n_optab>\t%<v>0<Vmtype>, %<v><cmp_1><Vmtype>, %<v><cmp_2><Vmtype>

51843

+ fcm<optab>\t%<v>0<Vmtype>, %<v>1<Vmtype>, 0"

51844

[(set_attr "simd_type" "simd_fcmp")

51845

(set_attr "simd_mode" "<MODE>")]

51846

)

51847

Index: gcc/config/aarch64/predicates.md

51848

===================================================================

51849

--- a/src/gcc/config/aarch64/predicates.md (.../tags/gcc_4_8_2_release)

51850

+++ b/src/gcc/config/aarch64/predicates.md (.../branches/gcc-4_8-branch)

51851

@@ -31,6 +31,11 @@

51852

(ior (match_operand 0 "register_operand")

51853

(match_test "op == const0_rtx"))))

51854

51855

+(define_predicate "aarch64_reg_or_fp_zero"

51856

+ (and (match_code "reg,subreg,const_double")

51857

+ (ior (match_operand 0 "register_operand")

51858

+ (match_test "aarch64_float_const_zero_rtx_p (op)"))))

51859

+

51860

(define_predicate "aarch64_reg_zero_or_m1_or_1"

51861

(and (match_code "reg,subreg,const_int")

51862

(ior (match_operand 0 "register_operand")

51863

Index: gcc/config/aarch64/arm_neon.h

51864

===================================================================

51865

--- a/src/gcc/config/aarch64/arm_neon.h (.../tags/gcc_4_8_2_release)

51866

+++ b/src/gcc/config/aarch64/arm_neon.h (.../branches/gcc-4_8-branch)

51867

@@ -19551,7 +19551,7 @@

51868

__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))

51869

vcge_u8 (uint8x8_t __a, uint8x8_t __b)

51870

{

51871

- return (uint8x8_t) __builtin_aarch64_cmhsv8qi ((int8x8_t) __a,

51872

+ return (uint8x8_t) __builtin_aarch64_cmgeuv8qi ((int8x8_t) __a,

51873

(int8x8_t) __b);

51874

}

51875

51876

@@ -19558,7 +19558,7 @@

51877

__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))

51878

vcge_u16 (uint16x4_t __a, uint16x4_t __b)

51879

{

51880

- return (uint16x4_t) __builtin_aarch64_cmhsv4hi ((int16x4_t) __a,

51881

+ return (uint16x4_t) __builtin_aarch64_cmgeuv4hi ((int16x4_t) __a,

51882

(int16x4_t) __b);

51883

}

51884

51885

@@ -19565,7 +19565,7 @@

51886

__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))

51887

vcge_u32 (uint32x2_t __a, uint32x2_t __b)

51888

{

51889

- return (uint32x2_t) __builtin_aarch64_cmhsv2si ((int32x2_t) __a,

51890

+ return (uint32x2_t) __builtin_aarch64_cmgeuv2si ((int32x2_t) __a,

51891

(int32x2_t) __b);

51892

}

51893

51894

@@ -19572,7 +19572,7 @@

51895

__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))

51896

vcge_u64 (uint64x1_t __a, uint64x1_t __b)

51897

{

51898

- return (uint64x1_t) __builtin_aarch64_cmhsdi ((int64x1_t) __a,

51899

+ return (uint64x1_t) __builtin_aarch64_cmgeudi ((int64x1_t) __a,

51900

(int64x1_t) __b);

51901

}

51902

51903

@@ -19603,7 +19603,7 @@

51904

__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))

51905

vcgeq_u8 (uint8x16_t __a, uint8x16_t __b)

51906

{

51907

- return (uint8x16_t) __builtin_aarch64_cmhsv16qi ((int8x16_t) __a,

51908

+ return (uint8x16_t) __builtin_aarch64_cmgeuv16qi ((int8x16_t) __a,

51909

(int8x16_t) __b);

51910

}

51911

51912

@@ -19610,7 +19610,7 @@

51913

__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))

51914

vcgeq_u16 (uint16x8_t __a, uint16x8_t __b)

51915

{

51916

- return (uint16x8_t) __builtin_aarch64_cmhsv8hi ((int16x8_t) __a,

51917

+ return (uint16x8_t) __builtin_aarch64_cmgeuv8hi ((int16x8_t) __a,

51918

(int16x8_t) __b);

51919

}

51920

51921

@@ -19617,7 +19617,7 @@

51922

__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))

51923

vcgeq_u32 (uint32x4_t __a, uint32x4_t __b)

51924

{

51925

- return (uint32x4_t) __builtin_aarch64_cmhsv4si ((int32x4_t) __a,

51926

+ return (uint32x4_t) __builtin_aarch64_cmgeuv4si ((int32x4_t) __a,

51927

(int32x4_t) __b);

51928

}

51929

51930

@@ -19624,7 +19624,7 @@

51931

__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))

51932

vcgeq_u64 (uint64x2_t __a, uint64x2_t __b)

51933

{

51934

- return (uint64x2_t) __builtin_aarch64_cmhsv2di ((int64x2_t) __a,

51935

+ return (uint64x2_t) __builtin_aarch64_cmgeuv2di ((int64x2_t) __a,

51936

(int64x2_t) __b);

51937

}

51938

51939

@@ -19637,7 +19637,7 @@

51940

__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))

51941

vcged_u64 (uint64x1_t __a, uint64x1_t __b)

51942

{

51943

- return (uint64x1_t) __builtin_aarch64_cmhsdi ((int64x1_t) __a,

51944

+ return (uint64x1_t) __builtin_aarch64_cmgeudi ((int64x1_t) __a,

51945

(int64x1_t) __b);

51946

}

51947

51948

@@ -19676,7 +19676,7 @@

51949

__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))

51950

vcgt_u8 (uint8x8_t __a, uint8x8_t __b)

51951

{

51952

- return (uint8x8_t) __builtin_aarch64_cmhiv8qi ((int8x8_t) __a,

51953

+ return (uint8x8_t) __builtin_aarch64_cmgtuv8qi ((int8x8_t) __a,

51954

(int8x8_t) __b);

51955

}

51956

51957

@@ -19683,7 +19683,7 @@

51958

__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))

51959

vcgt_u16 (uint16x4_t __a, uint16x4_t __b)

51960

{

51961

- return (uint16x4_t) __builtin_aarch64_cmhiv4hi ((int16x4_t) __a,

51962

+ return (uint16x4_t) __builtin_aarch64_cmgtuv4hi ((int16x4_t) __a,

51963

(int16x4_t) __b);

51964

}

51965

51966

@@ -19690,7 +19690,7 @@

51967

__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))

51968

vcgt_u32 (uint32x2_t __a, uint32x2_t __b)

51969

{

51970

- return (uint32x2_t) __builtin_aarch64_cmhiv2si ((int32x2_t) __a,

51971

+ return (uint32x2_t) __builtin_aarch64_cmgtuv2si ((int32x2_t) __a,

51972

(int32x2_t) __b);

51973

}

51974

51975

@@ -19697,7 +19697,7 @@

51976

__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))

51977

vcgt_u64 (uint64x1_t __a, uint64x1_t __b)

51978

{

51979

- return (uint64x1_t) __builtin_aarch64_cmhidi ((int64x1_t) __a,

51980

+ return (uint64x1_t) __builtin_aarch64_cmgtudi ((int64x1_t) __a,

51981

(int64x1_t) __b);

51982

}

51983

51984

@@ -19728,7 +19728,7 @@

51985

__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))

51986

vcgtq_u8 (uint8x16_t __a, uint8x16_t __b)

51987

{

51988

- return (uint8x16_t) __builtin_aarch64_cmhiv16qi ((int8x16_t) __a,

51989

+ return (uint8x16_t) __builtin_aarch64_cmgtuv16qi ((int8x16_t) __a,

51990

(int8x16_t) __b);

51991

}

51992

51993

@@ -19735,7 +19735,7 @@

51994

__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))

51995

vcgtq_u16 (uint16x8_t __a, uint16x8_t __b)

51996

{

51997

- return (uint16x8_t) __builtin_aarch64_cmhiv8hi ((int16x8_t) __a,

51998

+ return (uint16x8_t) __builtin_aarch64_cmgtuv8hi ((int16x8_t) __a,

51999

(int16x8_t) __b);

52000

}

52001

52002

@@ -19742,7 +19742,7 @@

52003

__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))

52004

vcgtq_u32 (uint32x4_t __a, uint32x4_t __b)

52005

{

52006

- return (uint32x4_t) __builtin_aarch64_cmhiv4si ((int32x4_t) __a,

52007

+ return (uint32x4_t) __builtin_aarch64_cmgtuv4si ((int32x4_t) __a,

52008

(int32x4_t) __b);

52009

}

52010

52011

@@ -19749,7 +19749,7 @@

52012

__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))

52013

vcgtq_u64 (uint64x2_t __a, uint64x2_t __b)

52014

{

52015

- return (uint64x2_t) __builtin_aarch64_cmhiv2di ((int64x2_t) __a,

52016

+ return (uint64x2_t) __builtin_aarch64_cmgtuv2di ((int64x2_t) __a,

52017

(int64x2_t) __b);

52018

}

52019

52020

@@ -19762,7 +19762,7 @@

52021

__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))

52022

vcgtd_u64 (uint64x1_t __a, uint64x1_t __b)

52023

{

52024

- return (uint64x1_t) __builtin_aarch64_cmhidi ((int64x1_t) __a,

52025

+ return (uint64x1_t) __builtin_aarch64_cmgtudi ((int64x1_t) __a,

52026

(int64x1_t) __b);

52027

}

52028

52029

@@ -19801,7 +19801,7 @@

52030

__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))

52031

vcle_u8 (uint8x8_t __a, uint8x8_t __b)

52032

{

52033

- return (uint8x8_t) __builtin_aarch64_cmhsv8qi ((int8x8_t) __b,

52034

+ return (uint8x8_t) __builtin_aarch64_cmgeuv8qi ((int8x8_t) __b,

52035

(int8x8_t) __a);

52036

}

52037

52038

@@ -19808,7 +19808,7 @@

52039

__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))

52040

vcle_u16 (uint16x4_t __a, uint16x4_t __b)

52041

{

52042

- return (uint16x4_t) __builtin_aarch64_cmhsv4hi ((int16x4_t) __b,

52043

+ return (uint16x4_t) __builtin_aarch64_cmgeuv4hi ((int16x4_t) __b,

52044

(int16x4_t) __a);

52045

}

52046

52047

@@ -19815,7 +19815,7 @@

52048

__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))

52049

vcle_u32 (uint32x2_t __a, uint32x2_t __b)

52050

{

52051

- return (uint32x2_t) __builtin_aarch64_cmhsv2si ((int32x2_t) __b,

52052

+ return (uint32x2_t) __builtin_aarch64_cmgeuv2si ((int32x2_t) __b,

52053

(int32x2_t) __a);

52054

}

52055

52056

@@ -19822,7 +19822,7 @@

52057

__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))

52058

vcle_u64 (uint64x1_t __a, uint64x1_t __b)

52059

{

52060

- return (uint64x1_t) __builtin_aarch64_cmhsdi ((int64x1_t) __b,

52061

+ return (uint64x1_t) __builtin_aarch64_cmgeudi ((int64x1_t) __b,

52062

(int64x1_t) __a);

52063

}

52064

52065

@@ -19853,7 +19853,7 @@

52066

__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))

52067

vcleq_u8 (uint8x16_t __a, uint8x16_t __b)

52068

{

52069

- return (uint8x16_t) __builtin_aarch64_cmhsv16qi ((int8x16_t) __b,

52070

+ return (uint8x16_t) __builtin_aarch64_cmgeuv16qi ((int8x16_t) __b,

52071

(int8x16_t) __a);

52072

}

52073

52074

@@ -19860,7 +19860,7 @@

52075

__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))

52076

vcleq_u16 (uint16x8_t __a, uint16x8_t __b)

52077

{

52078

- return (uint16x8_t) __builtin_aarch64_cmhsv8hi ((int16x8_t) __b,

52079

+ return (uint16x8_t) __builtin_aarch64_cmgeuv8hi ((int16x8_t) __b,

52080

(int16x8_t) __a);

52081

}

52082

52083

@@ -19867,7 +19867,7 @@

52084

__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))

52085

vcleq_u32 (uint32x4_t __a, uint32x4_t __b)

52086

{

52087

- return (uint32x4_t) __builtin_aarch64_cmhsv4si ((int32x4_t) __b,

52088

+ return (uint32x4_t) __builtin_aarch64_cmgeuv4si ((int32x4_t) __b,

52089

(int32x4_t) __a);

52090

}

52091

52092

@@ -19874,7 +19874,7 @@

52093

__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))

52094

vcleq_u64 (uint64x2_t __a, uint64x2_t __b)

52095

{

52096

- return (uint64x2_t) __builtin_aarch64_cmhsv2di ((int64x2_t) __b,

52097

+ return (uint64x2_t) __builtin_aarch64_cmgeuv2di ((int64x2_t) __b,

52098

(int64x2_t) __a);

52099

}

52100

52101

@@ -19919,7 +19919,7 @@

52102

__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))

52103

vclt_u8 (uint8x8_t __a, uint8x8_t __b)

52104

{

52105

- return (uint8x8_t) __builtin_aarch64_cmhiv8qi ((int8x8_t) __b,

52106

+ return (uint8x8_t) __builtin_aarch64_cmgtuv8qi ((int8x8_t) __b,

52107

(int8x8_t) __a);

52108

}

52109

52110

@@ -19926,7 +19926,7 @@

52111

__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))

52112

vclt_u16 (uint16x4_t __a, uint16x4_t __b)

52113

{

52114

- return (uint16x4_t) __builtin_aarch64_cmhiv4hi ((int16x4_t) __b,

52115

+ return (uint16x4_t) __builtin_aarch64_cmgtuv4hi ((int16x4_t) __b,

52116

(int16x4_t) __a);

52117

}

52118

52119

@@ -19933,7 +19933,7 @@

52120

__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))

52121

vclt_u32 (uint32x2_t __a, uint32x2_t __b)

52122

{

52123

- return (uint32x2_t) __builtin_aarch64_cmhiv2si ((int32x2_t) __b,

52124

+ return (uint32x2_t) __builtin_aarch64_cmgtuv2si ((int32x2_t) __b,

52125

(int32x2_t) __a);

52126

}

52127

52128

@@ -19940,7 +19940,7 @@

52129

__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))

52130

vclt_u64 (uint64x1_t __a, uint64x1_t __b)

52131

{

52132

- return (uint64x1_t) __builtin_aarch64_cmhidi ((int64x1_t) __b,

52133

+ return (uint64x1_t) __builtin_aarch64_cmgtudi ((int64x1_t) __b,

52134

(int64x1_t) __a);

52135

}

52136

52137

@@ -19971,7 +19971,7 @@

52138

__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))

52139

vcltq_u8 (uint8x16_t __a, uint8x16_t __b)

52140

{

52141

- return (uint8x16_t) __builtin_aarch64_cmhiv16qi ((int8x16_t) __b,

52142

+ return (uint8x16_t) __builtin_aarch64_cmgtuv16qi ((int8x16_t) __b,

52143

(int8x16_t) __a);

52144

}

52145

52146

@@ -19978,7 +19978,7 @@

52147

__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))

52148

vcltq_u16 (uint16x8_t __a, uint16x8_t __b)

52149

{

52150

- return (uint16x8_t) __builtin_aarch64_cmhiv8hi ((int16x8_t) __b,

52151

+ return (uint16x8_t) __builtin_aarch64_cmgtuv8hi ((int16x8_t) __b,

52152

(int16x8_t) __a);

52153

}

52154

52155

@@ -19985,7 +19985,7 @@

52156

__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))

52157

vcltq_u32 (uint32x4_t __a, uint32x4_t __b)

52158

{

52159

- return (uint32x4_t) __builtin_aarch64_cmhiv4si ((int32x4_t) __b,

52160

+ return (uint32x4_t) __builtin_aarch64_cmgtuv4si ((int32x4_t) __b,

52161

(int32x4_t) __a);

52162

}

52163

52164

@@ -19992,7 +19992,7 @@

52165

__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))

52166

vcltq_u64 (uint64x2_t __a, uint64x2_t __b)

52167

{

52168

- return (uint64x2_t) __builtin_aarch64_cmhiv2di ((int64x2_t) __b,

52169

+ return (uint64x2_t) __builtin_aarch64_cmgtuv2di ((int64x2_t) __b,

52170

(int64x2_t) __a);

52171

}

52172

52173

Index: gcc/config/aarch64/aarch64.md

52174

===================================================================

52175

--- a/src/gcc/config/aarch64/aarch64.md (.../tags/gcc_4_8_2_release)

52176

+++ b/src/gcc/config/aarch64/aarch64.md (.../branches/gcc-4_8-branch)

52177

@@ -2211,7 +2211,7 @@

52178

(set_attr "mode" "SI")]

52179

)

52180

52181

-(define_insn "*cstore<mode>_neg"

52182

+(define_insn "cstore<mode>_neg"

52183

[(set (match_operand:ALLI 0 "register_operand" "=r")

52184

(neg:ALLI (match_operator:ALLI 1 "aarch64_comparison_operator"

52185

[(match_operand 2 "cc_register" "") (const_int 0)])))]

52186

Index: gcc/config/aarch64/aarch64-simd-builtins.def

52187

===================================================================

52188

--- a/src/gcc/config/aarch64/aarch64-simd-builtins.def (.../tags/gcc_4_8_2_release)

52189

+++ b/src/gcc/config/aarch64/aarch64-simd-builtins.def (.../branches/gcc-4_8-branch)

52190

@@ -217,8 +217,8 @@

52191

BUILTIN_VSDQ_I_DI (BINOP, cmle)

52192

BUILTIN_VSDQ_I_DI (BINOP, cmlt)

52193

/* Implemented by aarch64_cm<cmp><mode>. */

52194

- BUILTIN_VSDQ_I_DI (BINOP, cmhs)

52195

- BUILTIN_VSDQ_I_DI (BINOP, cmhi)

52196

+ BUILTIN_VSDQ_I_DI (BINOP, cmgeu)

52197

+ BUILTIN_VSDQ_I_DI (BINOP, cmgtu)

52198

BUILTIN_VSDQ_I_DI (BINOP, cmtst)

52199

52200

/* Implemented by aarch64_<fmaxmin><mode>. */

52201

Index: gcc/config/aarch64/aarch64.c

52202

===================================================================

52203

--- a/src/gcc/config/aarch64/aarch64.c (.../tags/gcc_4_8_2_release)

52204

+++ b/src/gcc/config/aarch64/aarch64.c (.../branches/gcc-4_8-branch)

52205

@@ -2274,7 +2274,7 @@

52206

if (ncount < zcount)

52207

{

52208

emit_move_insn (gen_rtx_REG (Pmode, regnum),

52209

- GEN_INT ((~val) & 0xffff));

52210

+ GEN_INT (val | ~(HOST_WIDE_INT) 0xffff));

52211

tval = 0xffff;

52212

}

52213

else

52214

@@ -4568,9 +4568,11 @@

52215

}

52216

52217

static int

52218

-aarch64_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,

52219

- reg_class_t from, reg_class_t to)

52220

+aarch64_register_move_cost (enum machine_mode mode,

52221

+ reg_class_t from_i, reg_class_t to_i)

52222

{

52223

+ enum reg_class from = (enum reg_class) from_i;

52224

+ enum reg_class to = (enum reg_class) to_i;

52225

const struct cpu_regmove_cost *regmove_cost

52226

= aarch64_tune_params->regmove_cost;

52227

52228

@@ -4586,8 +4588,7 @@

52229

secondary reload. A general register is used as a scratch to move

52230

the upper DI value and the lower DI value is moved directly,

52231

hence the cost is the sum of three moves. */

52232

-

52233

- if (! TARGET_SIMD && GET_MODE_SIZE (from) == 128 && GET_MODE_SIZE (to) == 128)

52234

+ if (! TARGET_SIMD && GET_MODE_SIZE (mode) == 128)

52235

return regmove_cost->GP2FP + regmove_cost->FP2GP + regmove_cost->FP2FP;

52236

52237

return regmove_cost->FP2FP;

52238

Index: gcc/config/aarch64/iterators.md

52239

===================================================================

52240

--- a/src/gcc/config/aarch64/iterators.md (.../tags/gcc_4_8_2_release)

52241

+++ b/src/gcc/config/aarch64/iterators.md (.../branches/gcc-4_8-branch)

52242

@@ -83,6 +83,9 @@

52243

;; Vector Float modes.

52244

(define_mode_iterator VDQF [V2SF V4SF V2DF])

52245

52246

+;; All Float modes.

52247

+(define_mode_iterator VALLF [V2SF V4SF V2DF SF DF])

52248

+

52249

;; Vector Float modes with 2 elements.

52250

(define_mode_iterator V2F [V2SF V2DF])

52251

52252

@@ -213,13 +216,6 @@

52253

UNSPEC_URSHL ; Used in aarch64-simd.md.

52254

UNSPEC_SQRSHL ; Used in aarch64-simd.md.

52255

UNSPEC_UQRSHL ; Used in aarch64-simd.md.

52256

- UNSPEC_CMEQ ; Used in aarch64-simd.md.

52257

- UNSPEC_CMLE ; Used in aarch64-simd.md.

52258

- UNSPEC_CMLT ; Used in aarch64-simd.md.

52259

- UNSPEC_CMGE ; Used in aarch64-simd.md.

52260

- UNSPEC_CMGT ; Used in aarch64-simd.md.

52261

- UNSPEC_CMHS ; Used in aarch64-simd.md.

52262

- UNSPEC_CMHI ; Used in aarch64-simd.md.

52263

UNSPEC_SSLI ; Used in aarch64-simd.md.

52264

UNSPEC_USLI ; Used in aarch64-simd.md.

52265

UNSPEC_SSRI ; Used in aarch64-simd.md.

52266

@@ -227,7 +223,6 @@

52267

UNSPEC_SSHLL ; Used in aarch64-simd.md.

52268

UNSPEC_USHLL ; Used in aarch64-simd.md.

52269

UNSPEC_ADDP ; Used in aarch64-simd.md.

52270

- UNSPEC_CMTST ; Used in aarch64-simd.md.

52271

UNSPEC_FMAX ; Used in aarch64-simd.md.

52272

UNSPEC_FMIN ; Used in aarch64-simd.md.

52273

UNSPEC_BSL ; Used in aarch64-simd.md.

52274

@@ -251,6 +246,7 @@

52275

52276

;; For scalar usage of vector/FP registers

52277

(define_mode_attr v [(QI "b") (HI "h") (SI "s") (DI "d")

52278

+ (SF "s") (DF "d")

52279

(V8QI "") (V16QI "")

52280

(V4HI "") (V8HI "")

52281

(V2SI "") (V4SI "")

52282

@@ -305,7 +301,8 @@

52283

(V4SF ".4s") (V2DF ".2d")

52284

(DI "") (SI "")

52285

(HI "") (QI "")

52286

- (TI "")])

52287

+ (TI "") (SF "")

52288

+ (DF "")])

52289

52290

;; Register suffix narrowed modes for VQN.

52291

(define_mode_attr Vmntype [(V8HI ".8b") (V4SI ".4h")

52292

@@ -444,7 +441,8 @@

52293

(V2SI "V2SI") (V4SI "V4SI")

52294

(DI "DI") (V2DI "V2DI")

52295

(V2SF "V2SI") (V4SF "V4SI")

52296

- (V2DF "V2DI")])

52297

+ (V2DF "V2DI") (DF "DI")

52298

+ (SF "SI")])

52299

52300

;; Lower case mode of results of comparison operations.

52301

(define_mode_attr v_cmp_result [(V8QI "v8qi") (V16QI "v16qi")

52302

@@ -452,7 +450,8 @@

52303

(V2SI "v2si") (V4SI "v4si")

52304

(DI "di") (V2DI "v2di")

52305

(V2SF "v2si") (V4SF "v4si")

52306

- (V2DF "v2di")])

52307

+ (V2DF "v2di") (DF "di")

52308

+ (SF "si")])

52309

52310

;; Vm for lane instructions is restricted to FP_LO_REGS.

52311

(define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x")

52312

@@ -543,6 +542,12 @@

52313

;; Code iterator for signed variants of vector saturating binary ops.

52314

(define_code_iterator SBINQOPS [ss_plus ss_minus])

52315

52316

+;; Comparison operators for <F>CM.

52317

+(define_code_iterator COMPARISONS [lt le eq ge gt])

52318

+

52319

+;; Unsigned comparison operators.

52320

+(define_code_iterator UCOMPARISONS [ltu leu geu gtu])

52321

+

52322

;; -------------------------------------------------------------------

52323

;; Code Attributes

52324

;; -------------------------------------------------------------------

52325

@@ -571,8 +576,29 @@

52326

(eq "eq")

52327

(ne "ne")

52328

(lt "lt")

52329

- (ge "ge")])

52330

+ (ge "ge")

52331

+ (le "le")

52332

+ (gt "gt")

52333

+ (ltu "ltu")

52334

+ (leu "leu")

52335

+ (geu "geu")

52336

+ (gtu "gtu")])

52337

52338

+;; For comparison operators we use the FCM* and CM* instructions.

52339

+;; As there are no CMLE or CMLT instructions which act on 3 vector

52340

+;; operands, we must use CMGE or CMGT and swap the order of the

52341

+;; source operands.

52342

+

52343

+(define_code_attr n_optab [(lt "gt") (le "ge") (eq "eq") (ge "ge") (gt "gt")

52344

+ (ltu "hi") (leu "hs") (geu "hs") (gtu "hi")])

52345

+(define_code_attr cmp_1 [(lt "2") (le "2") (eq "1") (ge "1") (gt "1")

52346

+ (ltu "2") (leu "2") (geu "1") (gtu "1")])

52347

+(define_code_attr cmp_2 [(lt "1") (le "1") (eq "2") (ge "2") (gt "2")

52348

+ (ltu "1") (leu "1") (geu "2") (gtu "2")])

52349

+

52350

+(define_code_attr CMP [(lt "LT") (le "LE") (eq "EQ") (ge "GE") (gt "GT")

52351

+ (ltu "LTU") (leu "LEU") (geu "GEU") (gtu "GTU")])

52352

+

52353

;; Optab prefix for sign/zero-extending operations

52354

(define_code_attr su_optab [(sign_extend "") (zero_extend "u")

52355

(div "") (udiv "u")

52356

@@ -680,11 +706,6 @@

52357

UNSPEC_SQSHRN UNSPEC_UQSHRN

52358

UNSPEC_SQRSHRN UNSPEC_UQRSHRN])

52359

52360

-(define_int_iterator VCMP_S [UNSPEC_CMEQ UNSPEC_CMGE UNSPEC_CMGT

52361

- UNSPEC_CMLE UNSPEC_CMLT])

52362

-

52363

-(define_int_iterator VCMP_U [UNSPEC_CMHS UNSPEC_CMHI UNSPEC_CMTST])

52364

-

52365

(define_int_iterator PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2

52366

UNSPEC_TRN1 UNSPEC_TRN2

52367

UNSPEC_UZP1 UNSPEC_UZP2])

52368

@@ -768,12 +789,6 @@

52369

(UNSPEC_RADDHN2 "add")

52370

(UNSPEC_RSUBHN2 "sub")])

52371

52372

-(define_int_attr cmp [(UNSPEC_CMGE "ge") (UNSPEC_CMGT "gt")

52373

- (UNSPEC_CMLE "le") (UNSPEC_CMLT "lt")

52374

- (UNSPEC_CMEQ "eq")

52375

- (UNSPEC_CMHS "hs") (UNSPEC_CMHI "hi")

52376

- (UNSPEC_CMTST "tst")])

52377

-

52378

(define_int_attr offsetlr [(UNSPEC_SSLI "1") (UNSPEC_USLI "1")

52379

(UNSPEC_SSRI "0") (UNSPEC_USRI "0")])

52380

52381

Index: gcc/config/aarch64/aarch64.h

52382

===================================================================

52383

--- a/src/gcc/config/aarch64/aarch64.h (.../tags/gcc_4_8_2_release)

52384

+++ b/src/gcc/config/aarch64/aarch64.h (.../branches/gcc-4_8-branch)

52385

@@ -73,9 +73,9 @@

52386

#define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN)

52387

52388

/* AdvSIMD is supported in the default configuration, unless disabled by

52389

- -mgeneral-regs-only. */

52390

-#define TARGET_SIMD !TARGET_GENERAL_REGS_ONLY

52391

-#define TARGET_FLOAT !TARGET_GENERAL_REGS_ONLY

52392

+ -mgeneral-regs-only or the +nosimd extension. */

52393

+#define TARGET_SIMD (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_SIMD)

52394

+#define TARGET_FLOAT (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_FP)

52395

52396

#define UNITS_PER_WORD 8

52397

52398

Index: gcc/config/rs6000/power8.md

52399

===================================================================

52400

--- a/src/gcc/config/rs6000/power8.md (.../tags/gcc_4_8_2_release)

52401

+++ b/src/gcc/config/rs6000/power8.md (.../branches/gcc-4_8-branch)

52402

@@ -0,0 +1,373 @@

52403

+;; Scheduling description for IBM POWER8 processor.

52404

52405

+;;

52406

+;; Contributed by Pat Haugen (pthaugen@us.ibm.com).

52407

+

52408

+;; This file is part of GCC.

52409

+;;

52410

+;; GCC is free software; you can redistribute it and/or modify it

52411

+;; under the terms of the GNU General Public License as published

52412

+;; by the Free Software Foundation; either version 3, or (at your

52413

+;; option) any later version.

52414

+;;

52415

+;; GCC is distributed in the hope that it will be useful, but WITHOUT

52416

+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY

52417

+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public

52418

+;; License for more details.

52419

+;;

52420

+;; You should have received a copy of the GNU General Public License

52421

+;; along with GCC; see the file COPYING3. If not see

52422

+;; <http://www.gnu.org/licenses/>.

52423

+

52424

+(define_automaton "power8fxu,power8lsu,power8vsu,power8misc")

52425

+

52426

+(define_cpu_unit "fxu0_power8,fxu1_power8" "power8fxu")

52427

+(define_cpu_unit "lu0_power8,lu1_power8" "power8lsu")

52428

+(define_cpu_unit "lsu0_power8,lsu1_power8" "power8lsu")

52429

+(define_cpu_unit "vsu0_power8,vsu1_power8" "power8vsu")

52430

+(define_cpu_unit "bpu_power8,cru_power8" "power8misc")

52431

+(define_cpu_unit "du0_power8,du1_power8,du2_power8,du3_power8,du4_power8,\

52432

+ du5_power8,du6_power8" "power8misc")

52433

+

52434

+

52435

+; Dispatch group reservations

52436

+(define_reservation "DU_any_power8"

52437

52438

+ du5_power8")

52439

+

52440

+; 2-way Cracked instructions go in slots 0-1

52441

+; (can also have a second in slots 3-4 if insns are adjacent)

52442

+(define_reservation "DU_cracked_power8"

52443

+ "du0_power8+du1_power8")

52444

+

52445

+; Insns that are first in group

52446

+(define_reservation "DU_first_power8"

52447

+ "du0_power8")

52448

+

52449

+; Insns that are first and last in group

52450

+(define_reservation "DU_both_power8"

52451

+ "du0_power8+du1_power8+du2_power8+du3_power8+du4_power8+\

52452

+ du5_power8+du6_power8")

52453

+

52454

+; Dispatch slots are allocated in order conforming to program order.

52455

+(absence_set "du0_power8" "du1_power8,du2_power8,du3_power8,du4_power8,\

52456

+ du5_power8,du6_power8")

52457

+(absence_set "du1_power8" "du2_power8,du3_power8,du4_power8,du5_power8,\

52458

+ du6_power8")

52459

+(absence_set "du2_power8" "du3_power8,du4_power8,du5_power8,du6_power8")

52460

+(absence_set "du3_power8" "du4_power8,du5_power8,du6_power8")

52461

+(absence_set "du4_power8" "du5_power8,du6_power8")

52462

+(absence_set "du5_power8" "du6_power8")

52463

+

52464

+

52465

+; Execution unit reservations

52466

+(define_reservation "FXU_power8"

52467

+ "fxu0_power8|fxu1_power8")

52468

+

52469

+(define_reservation "LU_power8"

52470

+ "lu0_power8|lu1_power8")

52471

+

52472

+(define_reservation "LSU_power8"

52473

+ "lsu0_power8|lsu1_power8")

52474

+

52475

+(define_reservation "LU_or_LSU_power8"

52476

+ "lu0_power8|lu1_power8|lsu0_power8|lsu1_power8")

52477

+

52478

+(define_reservation "VSU_power8"

52479

+ "vsu0_power8|vsu1_power8")

52480

+

52481

+

52482

+; LS Unit

52483

+(define_insn_reservation "power8-load" 3

52484

+ (and (eq_attr "type" "load")

52485

+ (eq_attr "cpu" "power8"))

52486

+ "DU_any_power8,LU_or_LSU_power8")

52487

+

52488

+(define_insn_reservation "power8-load-update" 3

52489

+ (and (eq_attr "type" "load_u,load_ux")

52490

+ (eq_attr "cpu" "power8"))

52491

+ "DU_cracked_power8,LU_or_LSU_power8+FXU_power8")

52492

+

52493

+(define_insn_reservation "power8-load-ext" 3

52494

+ (and (eq_attr "type" "load_ext")

52495

+ (eq_attr "cpu" "power8"))

52496

+ "DU_cracked_power8,LU_or_LSU_power8,FXU_power8")

52497

+

52498

+(define_insn_reservation "power8-load-ext-update" 3

52499

+ (and (eq_attr "type" "load_ext_u,load_ext_ux")

52500

+ (eq_attr "cpu" "power8"))

52501

+ "DU_both_power8,LU_or_LSU_power8+FXU_power8,FXU_power8")

52502

+

52503

+(define_insn_reservation "power8-fpload" 5

52504

+ (and (eq_attr "type" "fpload,vecload")

52505

+ (eq_attr "cpu" "power8"))

52506

+ "DU_any_power8,LU_power8")

52507

+

52508

+(define_insn_reservation "power8-fpload-update" 5

52509

+ (and (eq_attr "type" "fpload_u,fpload_ux")

52510

+ (eq_attr "cpu" "power8"))

52511

+ "DU_cracked_power8,LU_power8+FXU_power8")

52512

+

52513

+(define_insn_reservation "power8-store" 5 ; store-forwarding latency

52514

+ (and (eq_attr "type" "store,store_u")

52515

+ (eq_attr "cpu" "power8"))

52516

+ "DU_any_power8,LSU_power8+LU_power8")

52517

+

52518

+(define_insn_reservation "power8-store-update-indexed" 5

52519

+ (and (eq_attr "type" "store_ux")

52520

+ (eq_attr "cpu" "power8"))

52521

+ "DU_cracked_power8,LSU_power8+LU_power8")

52522

+

52523

+(define_insn_reservation "power8-fpstore" 5

52524

+ (and (eq_attr "type" "fpstore")

52525

+ (eq_attr "cpu" "power8"))

52526

+ "DU_any_power8,LSU_power8+VSU_power8")

52527

+

52528

+(define_insn_reservation "power8-fpstore-update" 5

52529

+ (and (eq_attr "type" "fpstore_u,fpstore_ux")

52530

+ (eq_attr "cpu" "power8"))

52531

+ "DU_any_power8,LSU_power8+VSU_power8")

52532

+

52533

+(define_insn_reservation "power8-vecstore" 5

52534

+ (and (eq_attr "type" "vecstore")

52535

+ (eq_attr "cpu" "power8"))

52536

+ "DU_cracked_power8,LSU_power8+VSU_power8")

52537

+

52538

+(define_insn_reservation "power8-larx" 3

52539

+ (and (eq_attr "type" "load_l")

52540

+ (eq_attr "cpu" "power8"))

52541

+ "DU_both_power8,LU_or_LSU_power8")

52542

+

52543

+(define_insn_reservation "power8-stcx" 10

52544

+ (and (eq_attr "type" "store_c")

52545

+ (eq_attr "cpu" "power8"))

52546

+ "DU_both_power8,LSU_power8+LU_power8")

52547

+

52548

+(define_insn_reservation "power8-sync" 1

52549

+ (and (eq_attr "type" "sync,isync")

52550

+ (eq_attr "cpu" "power8"))

52551

+ "DU_both_power8,LSU_power8")

52552

+

52553

+

52554

+; FX Unit

52555

+(define_insn_reservation "power8-1cyc" 1

52556

+ (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\

52557

+ var_shift_rotate,exts,isel")

52558

+ (eq_attr "cpu" "power8"))

52559

+ "DU_any_power8,FXU_power8")

52560

+

52561

+; Extra cycle to LU/LSU

52562

+(define_bypass 2 "power8-1cyc"

52563

+ "power8-load*,power8-fpload*,power8-store*,power8-fpstore*,\

52564

+ power8-vecstore,power8-larx,power8-stcx")

52565

+; "power8-load,power8-load-update,power8-load-ext,\

52566

+; power8-load-ext-update,power8-fpload,power8-fpload-update,\

52567

+; power8-store,power8-store-update,power8-store-update-indexed,\

52568

+; power8-fpstore,power8-fpstore-update,power8-vecstore,\

52569

+; power8-larx,power8-stcx")

52570

+

52571

+(define_insn_reservation "power8-2cyc" 2

52572

+ (and (eq_attr "type" "cntlz,popcnt")

52573

+ (eq_attr "cpu" "power8"))

52574

+ "DU_any_power8,FXU_power8")

52575

+

52576

+(define_insn_reservation "power8-two" 2

52577

+ (and (eq_attr "type" "two")

52578

+ (eq_attr "cpu" "power8"))

52579

+ "DU_any_power8+DU_any_power8,FXU_power8,FXU_power8")

52580

+

52581

+(define_insn_reservation "power8-three" 3

52582

+ (and (eq_attr "type" "three")

52583

+ (eq_attr "cpu" "power8"))

52584

+ "DU_any_power8+DU_any_power8+DU_any_power8,FXU_power8,FXU_power8,FXU_power8")

52585

+

52586

+; cmp - Normal compare insns

52587

+(define_insn_reservation "power8-cmp" 2

52588

+ (and (eq_attr "type" "cmp")

52589

+ (eq_attr "cpu" "power8"))

52590

+ "DU_any_power8,FXU_power8")

52591

+

52592

+; fast_compare : add./and./nor./etc

52593

+(define_insn_reservation "power8-fast-compare" 2

52594

+ (and (eq_attr "type" "fast_compare")

52595

+ (eq_attr "cpu" "power8"))

52596

+ "DU_any_power8,FXU_power8")

52597

+

52598

+; compare : rldicl./exts./etc

52599

+; delayed_compare : rlwinm./slwi./etc

52600

+; var_delayed_compare : rlwnm./slw./etc

52601

+(define_insn_reservation "power8-compare" 2

52602

+ (and (eq_attr "type" "compare,delayed_compare,var_delayed_compare")

52603

+ (eq_attr "cpu" "power8"))

52604

+ "DU_cracked_power8,FXU_power8,FXU_power8")

52605

+

52606

+; Extra cycle to LU/LSU

52607

+(define_bypass 3 "power8-fast-compare,power8-compare"

52608

+ "power8-load*,power8-fpload*,power8-store*,power8-fpstore*,\

52609

+ power8-vecstore,power8-larx,power8-stcx")

52610

+

52611

+; 5 cycle CR latency

52612

+(define_bypass 5 "power8-fast-compare,power8-compare"

52613

+ "power8-crlogical,power8-mfcr,power8-mfcrf,power8-branch")

52614

+

52615

+(define_insn_reservation "power8-mul" 4

52616

+ (and (eq_attr "type" "imul,imul2,imul3,lmul")

52617

+ (eq_attr "cpu" "power8"))

52618

+ "DU_any_power8,FXU_power8")

52619

+

52620

+(define_insn_reservation "power8-mul-compare" 4

52621

+ (and (eq_attr "type" "imul_compare,lmul_compare")

52622

+ (eq_attr "cpu" "power8"))

52623

+ "DU_cracked_power8,FXU_power8")

52624

+

52625

+; Extra cycle to LU/LSU

52626

+(define_bypass 5 "power8-mul,power8-mul-compare"

52627

+ "power8-load*,power8-fpload*,power8-store*,power8-fpstore*,\

52628

+ power8-vecstore,power8-larx,power8-stcx")

52629

+

52630

+; 7 cycle CR latency

52631

+(define_bypass 7 "power8-mul,power8-mul-compare"

52632

+ "power8-crlogical,power8-mfcr,power8-mfcrf,power8-branch")

52633

+

52634

+; FXU divides are not pipelined

52635

+(define_insn_reservation "power8-idiv" 37

52636

+ (and (eq_attr "type" "idiv")

52637

+ (eq_attr "cpu" "power8"))

52638

+ "DU_any_power8,fxu0_power8*37|fxu1_power8*37")

52639

+

52640

+(define_insn_reservation "power8-ldiv" 68

52641

+ (and (eq_attr "type" "ldiv")

52642

+ (eq_attr "cpu" "power8"))

52643

+ "DU_any_power8,fxu0_power8*68|fxu1_power8*68")

52644

+

52645

+(define_insn_reservation "power8-mtjmpr" 5

52646

+ (and (eq_attr "type" "mtjmpr")

52647

+ (eq_attr "cpu" "power8"))

52648

+ "DU_first_power8,FXU_power8")

52649

+

52650

+; Should differentiate between 1 cr field and > 1 since mtocrf is not microcode

52651

+(define_insn_reservation "power8-mtcr" 3

52652

+ (and (eq_attr "type" "mtcr")

52653

+ (eq_attr "cpu" "power8"))

52654

+ "DU_both_power8,FXU_power8")

52655

+

52656

+

52657

+; CR Unit

52658

+(define_insn_reservation "power8-mfjmpr" 5

52659

+ (and (eq_attr "type" "mfjmpr")

52660

+ (eq_attr "cpu" "power8"))

52661

+ "DU_first_power8,cru_power8+FXU_power8")

52662

+

52663

+(define_insn_reservation "power8-crlogical" 3

52664

+ (and (eq_attr "type" "cr_logical,delayed_cr")

52665

+ (eq_attr "cpu" "power8"))

52666

+ "DU_first_power8,cru_power8")

52667

+

52668

+(define_insn_reservation "power8-mfcr" 5

52669

+ (and (eq_attr "type" "mfcr")

52670

+ (eq_attr "cpu" "power8"))

52671

+ "DU_both_power8,cru_power8")

52672

+

52673

+(define_insn_reservation "power8-mfcrf" 3

52674

+ (and (eq_attr "type" "mfcrf")

52675

+ (eq_attr "cpu" "power8"))

52676

+ "DU_first_power8,cru_power8")

52677

+

52678

+

52679

+; BR Unit

52680

+; Branches take dispatch slot 7, but reserve any remaining prior slots to

52681

+; prevent other insns from grabbing them once this is assigned.

52682

+(define_insn_reservation "power8-branch" 3

52683

+ (and (eq_attr "type" "jmpreg,branch")

52684

+ (eq_attr "cpu" "power8"))

52685

+ "(du6_power8\

52686

+ |du5_power8+du6_power8\

52687

+ |du4_power8+du5_power8+du6_power8\

52688

+ |du3_power8+du4_power8+du5_power8+du6_power8\

52689

+ |du2_power8+du3_power8+du4_power8+du5_power8+du6_power8\

52690

+ |du1_power8+du2_power8+du3_power8+du4_power8+du5_power8+du6_power8\

52691

+ |du0_power8+du1_power8+du2_power8+du3_power8+du4_power8+du5_power8+\

52692

+ du6_power8),bpu_power8")

52693

+

52694

+; Branch updating LR/CTR feeding mf[lr|ctr]

52695

+(define_bypass 4 "power8-branch" "power8-mfjmpr")

52696

+

52697

+

52698

+; VS Unit (includes FP/VSX/VMX/DFP/Crypto)

52699

+(define_insn_reservation "power8-fp" 6

52700

+ (and (eq_attr "type" "fp,dmul")

52701

+ (eq_attr "cpu" "power8"))

52702

+ "DU_any_power8,VSU_power8")

52703

+

52704

+; Additional 3 cycles for any CR result

52705

+(define_bypass 9 "power8-fp" "power8-crlogical,power8-mfcr*,power8-branch")

52706

+

52707

+(define_insn_reservation "power8-fpcompare" 8

52708

+ (and (eq_attr "type" "fpcompare")

52709

+ (eq_attr "cpu" "power8"))

52710

+ "DU_any_power8,VSU_power8")

52711

+

52712

+(define_insn_reservation "power8-sdiv" 27

52713

+ (and (eq_attr "type" "sdiv")

52714

+ (eq_attr "cpu" "power8"))

52715

+ "DU_any_power8,VSU_power8")

52716

+

52717

+(define_insn_reservation "power8-ddiv" 33

52718

+ (and (eq_attr "type" "ddiv")

52719

+ (eq_attr "cpu" "power8"))

52720

+ "DU_any_power8,VSU_power8")

52721

+

52722

+(define_insn_reservation "power8-sqrt" 32

52723

+ (and (eq_attr "type" "ssqrt")

52724

+ (eq_attr "cpu" "power8"))

52725

+ "DU_any_power8,VSU_power8")

52726

+

52727

+(define_insn_reservation "power8-dsqrt" 44

52728

+ (and (eq_attr "type" "dsqrt")

52729

+ (eq_attr "cpu" "power8"))

52730

+ "DU_any_power8,VSU_power8")

52731

+

52732

+(define_insn_reservation "power8-vecsimple" 2

52733

+ (and (eq_attr "type" "vecperm,vecsimple,veccmp")

52734

+ (eq_attr "cpu" "power8"))

52735

+ "DU_any_power8,VSU_power8")

52736

+

52737

+(define_insn_reservation "power8-vecnormal" 6

52738

+ (and (eq_attr "type" "vecfloat,vecdouble")

52739

+ (eq_attr "cpu" "power8"))

52740

+ "DU_any_power8,VSU_power8")

52741

+

52742

+(define_bypass 7 "power8-vecnormal"

52743

+ "power8-vecsimple,power8-veccomplex,power8-fpstore*,\

52744

+ power8-vecstore")

52745

+

52746

+(define_insn_reservation "power8-veccomplex" 7

52747

+ (and (eq_attr "type" "veccomplex")

52748

+ (eq_attr "cpu" "power8"))

52749

+ "DU_any_power8,VSU_power8")

52750

+

52751

+(define_insn_reservation "power8-vecfdiv" 25

52752

+ (and (eq_attr "type" "vecfdiv")

52753

+ (eq_attr "cpu" "power8"))

52754

+ "DU_any_power8,VSU_power8")

52755

+

52756

+(define_insn_reservation "power8-vecdiv" 31

52757

+ (and (eq_attr "type" "vecdiv")

52758

+ (eq_attr "cpu" "power8"))

52759

+ "DU_any_power8,VSU_power8")

52760

+

52761

+(define_insn_reservation "power8-mffgpr" 5

52762

+ (and (eq_attr "type" "mffgpr")

52763

+ (eq_attr "cpu" "power8"))

52764

+ "DU_any_power8,VSU_power8")

52765

+

52766

+(define_insn_reservation "power8-mftgpr" 6

52767

+ (and (eq_attr "type" "mftgpr")

52768

+ (eq_attr "cpu" "power8"))

52769

+ "DU_any_power8,VSU_power8")

52770

+

52771

+(define_insn_reservation "power8-crypto" 7

52772

+ (and (eq_attr "type" "crypto")

52773

+ (eq_attr "cpu" "power8"))

52774

+ "DU_any_power8,VSU_power8")

52775

+

52776

Index: gcc/config/rs6000/vector.md

52777

===================================================================

52778

--- a/src/gcc/config/rs6000/vector.md (.../tags/gcc_4_8_2_release)

52779

+++ b/src/gcc/config/rs6000/vector.md (.../branches/gcc-4_8-branch)

52780

@@ -24,28 +24,28 @@

52781

52782

52783

;; Vector int modes

52784

-(define_mode_iterator VEC_I [V16QI V8HI V4SI])

52785

+(define_mode_iterator VEC_I [V16QI V8HI V4SI V2DI])

52786

52787

;; Vector float modes

52788

(define_mode_iterator VEC_F [V4SF V2DF])

52789

52790

;; Vector arithmetic modes

52791

-(define_mode_iterator VEC_A [V16QI V8HI V4SI V4SF V2DF])

52792

+(define_mode_iterator VEC_A [V16QI V8HI V4SI V2DI V4SF V2DF])

52793

52794

;; Vector modes that need alginment via permutes

52795

(define_mode_iterator VEC_K [V16QI V8HI V4SI V4SF])

52796

52797

;; Vector logical modes

52798

-(define_mode_iterator VEC_L [V16QI V8HI V4SI V2DI V4SF V2DF TI])

52799

+(define_mode_iterator VEC_L [V16QI V8HI V4SI V2DI V4SF V2DF V1TI TI])

52800

52801

;; Vector modes for moves. Don't do TImode here.

52802

-(define_mode_iterator VEC_M [V16QI V8HI V4SI V2DI V4SF V2DF])

52803

+(define_mode_iterator VEC_M [V16QI V8HI V4SI V2DI V4SF V2DF V1TI])

52804

52805

;; Vector modes for types that don't need a realignment under VSX

52806

-(define_mode_iterator VEC_N [V4SI V4SF V2DI V2DF])

52807

+(define_mode_iterator VEC_N [V4SI V4SF V2DI V2DF V1TI])

52808

52809

;; Vector comparison modes

52810

-(define_mode_iterator VEC_C [V16QI V8HI V4SI V4SF V2DF])

52811

+(define_mode_iterator VEC_C [V16QI V8HI V4SI V2DI V4SF V2DF])

52812

52813

;; Vector init/extract modes

52814

(define_mode_iterator VEC_E [V16QI V8HI V4SI V2DI V4SF V2DF])

52815

@@ -54,7 +54,8 @@

52816

(define_mode_iterator VEC_64 [V2DI V2DF])

52817

52818

;; Vector reload iterator

52819

-(define_mode_iterator VEC_R [V16QI V8HI V4SI V2DI V4SF V2DF DF TI])

52820

+(define_mode_iterator VEC_R [V16QI V8HI V4SI V2DI V4SF V2DF V1TI

52821

+ SF SD SI DF DD DI TI])

52822

52823

;; Base type from vector mode

52824

(define_mode_attr VEC_base [(V16QI "QI")

52825

@@ -63,6 +64,7 @@

52826

(V2DI "DI")

52827

(V4SF "SF")

52828

(V2DF "DF")

52829

+ (V1TI "TI")

52830

(TI "TI")])

52831

52832

;; Same size integer type for floating point data

52833

@@ -88,7 +90,8 @@

52834

(smax "smax")])

52835

52836

52837

-;; Vector move instructions.

52838

+;; Vector move instructions. Little-endian VSX loads and stores require

52839

+;; special handling to circumvent "element endianness."

52840

(define_expand "mov<mode>"

52841

[(set (match_operand:VEC_M 0 "nonimmediate_operand" "")

52842

(match_operand:VEC_M 1 "any_operand" ""))]

52843

@@ -104,6 +107,15 @@

52844

&& !vlogical_operand (operands[1], <MODE>mode))

52845

operands[1] = force_reg (<MODE>mode, operands[1]);

52846

}

52847

+ if (!BYTES_BIG_ENDIAN

52848

+ && VECTOR_MEM_VSX_P (<MODE>mode)

52849

+ && !gpr_or_gpr_p (operands[0], operands[1])

52850

+ && (memory_operand (operands[0], <MODE>mode)

52851

+ ^ memory_operand (operands[1], <MODE>mode)))

52852

+ {

52853

+ rs6000_emit_le_vsx_move (operands[0], operands[1], <MODE>mode);

52854

+ DONE;

52855

+ }

52856

})

52857

52858

;; Generic vector floating point load/store instructions. These will match

52859

@@ -126,7 +138,9 @@

52860

(match_operand:VEC_L 1 "input_operand" ""))]

52861

"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)

52862

&& reload_completed

52863

- && gpr_or_gpr_p (operands[0], operands[1])"

52864

+ && gpr_or_gpr_p (operands[0], operands[1])

52865

+ && !direct_move_p (operands[0], operands[1])

52866

+ && !quad_load_store_p (operands[0], operands[1])"

52867

[(pc)]

52868

{

52869

rs6000_split_multireg_move (operands[0], operands[1]);

52870

@@ -249,7 +263,7 @@

52871

[(set (match_operand:VEC_F 0 "vfloat_operand" "")

52872

(mult:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")

52873

(match_operand:VEC_F 2 "vfloat_operand" "")))]

52874

- "VECTOR_UNIT_VSX_P (<MODE>mode) || VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"

52875

+ "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"

52876

{

52877

if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))

52878

{

52879

@@ -395,7 +409,7 @@

52880

(match_operand:VEC_I 5 "vint_operand" "")])

52881

(match_operand:VEC_I 1 "vint_operand" "")

52882

(match_operand:VEC_I 2 "vint_operand" "")))]

52883

- "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"

52884

+ "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"

52885

"

52886

{

52887

if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],

52888

@@ -451,7 +465,7 @@

52889

(match_operand:VEC_I 5 "vint_operand" "")])

52890

(match_operand:VEC_I 1 "vint_operand" "")

52891

(match_operand:VEC_I 2 "vint_operand" "")))]

52892

- "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"

52893

+ "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"

52894

"

52895

{

52896

if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],

52897

@@ -505,7 +519,7 @@

52898

[(set (match_operand:VEC_I 0 "vint_operand" "")

52899

(gtu:VEC_I (match_operand:VEC_I 1 "vint_operand" "")

52900

(match_operand:VEC_I 2 "vint_operand" "")))]

52901

- "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"

52902

+ "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"

52903

"")

52904

52905

(define_expand "vector_geu<mode>"

52906

@@ -512,7 +526,7 @@

52907

[(set (match_operand:VEC_I 0 "vint_operand" "")

52908

(geu:VEC_I (match_operand:VEC_I 1 "vint_operand" "")

52909

(match_operand:VEC_I 2 "vint_operand" "")))]

52910

- "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"

52911

+ "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"

52912

"")

52913

52914

(define_insn_and_split "*vector_uneq<mode>"

52915

@@ -595,8 +609,8 @@

52916

(ge:VEC_F (match_dup 2)

52917

(match_dup 1)))

52918

(set (match_dup 0)

52919

- (not:VEC_F (ior:VEC_F (match_dup 3)

52920

- (match_dup 4))))]

52921

+ (and:VEC_F (not:VEC_F (match_dup 3))

52922

+ (not:VEC_F (match_dup 4))))]

52923

"

52924

{

52925

operands[3] = gen_reg_rtx (<MODE>mode);

52926

@@ -708,48 +722,19 @@

52927

"")

52928

52929

52930

-;; Vector logical instructions

52931

-(define_expand "xor<mode>3"

52932

- [(set (match_operand:VEC_L 0 "vlogical_operand" "")

52933

- (xor:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")

52934

- (match_operand:VEC_L 2 "vlogical_operand" "")))]

52935

- "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"

52936

- "")

52937

+;; Vector count leading zeros

52938

+(define_expand "clz<mode>2"

52939

+ [(set (match_operand:VEC_I 0 "register_operand" "")

52940

+ (clz:VEC_I (match_operand:VEC_I 1 "register_operand" "")))]

52941

+ "TARGET_P8_VECTOR")

52942

52943

-(define_expand "ior<mode>3"

52944

- [(set (match_operand:VEC_L 0 "vlogical_operand" "")

52945

- (ior:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")

52946

- (match_operand:VEC_L 2 "vlogical_operand" "")))]

52947

- "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"

52948

- "")

52949

+;; Vector population count

52950

+(define_expand "popcount<mode>2"

52951

+ [(set (match_operand:VEC_I 0 "register_operand" "")

52952

+ (popcount:VEC_I (match_operand:VEC_I 1 "register_operand" "")))]

52953

+ "TARGET_P8_VECTOR")

52954

52955

-(define_expand "and<mode>3"

52956

- [(set (match_operand:VEC_L 0 "vlogical_operand" "")

52957

- (and:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")

52958

- (match_operand:VEC_L 2 "vlogical_operand" "")))]

52959

- "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"

52960

- "")

52961

-

52962

-(define_expand "one_cmpl<mode>2"

52963

- [(set (match_operand:VEC_L 0 "vlogical_operand" "")

52964

- (not:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")))]

52965

- "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"

52966

- "")

52967

-

52968

-(define_expand "nor<mode>3"

52969

- [(set (match_operand:VEC_L 0 "vlogical_operand" "")

52970

- (not:VEC_L (ior:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")

52971

- (match_operand:VEC_L 2 "vlogical_operand" ""))))]

52972

- "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"

52973

- "")

52974

-

52975

-(define_expand "andc<mode>3"

52976

- [(set (match_operand:VEC_L 0 "vlogical_operand" "")

52977

- (and:VEC_L (not:VEC_L (match_operand:VEC_L 2 "vlogical_operand" ""))

52978

- (match_operand:VEC_L 1 "vlogical_operand" "")))]

52979

- "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"

52980

- "")

52981

-

52982

+

52983

;; Same size conversions

52984

(define_expand "float<VEC_int><mode>2"

52985

[(set (match_operand:VEC_F 0 "vfloat_operand" "")

52986

@@ -889,7 +874,7 @@

52987

{

52988

rtx reg = gen_reg_rtx (V4SFmode);

52989

52990

- rs6000_expand_interleave (reg, operands[1], operands[1], true);

52991

+ rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN);

52992

emit_insn (gen_vsx_xvcvspdp (operands[0], reg));

52993

DONE;

52994

})

52995

@@ -901,7 +886,7 @@

52996

{

52997

rtx reg = gen_reg_rtx (V4SFmode);

52998

52999

- rs6000_expand_interleave (reg, operands[1], operands[1], false);

53000

+ rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN);

53001

emit_insn (gen_vsx_xvcvspdp (operands[0], reg));

53002

DONE;

53003

})

53004

@@ -913,7 +898,7 @@

53005

{

53006

rtx reg = gen_reg_rtx (V4SImode);

53007

53008

- rs6000_expand_interleave (reg, operands[1], operands[1], true);

53009

+ rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN);

53010

emit_insn (gen_vsx_xvcvsxwdp (operands[0], reg));

53011

DONE;

53012

})

53013

@@ -925,7 +910,7 @@

53014

{

53015

rtx reg = gen_reg_rtx (V4SImode);

53016

53017

- rs6000_expand_interleave (reg, operands[1], operands[1], false);

53018

+ rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN);

53019

emit_insn (gen_vsx_xvcvsxwdp (operands[0], reg));

53020

DONE;

53021

})

53022

@@ -937,7 +922,7 @@

53023

{

53024

rtx reg = gen_reg_rtx (V4SImode);

53025

53026

- rs6000_expand_interleave (reg, operands[1], operands[1], true);

53027

+ rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN);

53028

emit_insn (gen_vsx_xvcvuxwdp (operands[0], reg));

53029

DONE;

53030

})

53031

@@ -949,7 +934,7 @@

53032

{

53033

rtx reg = gen_reg_rtx (V4SImode);

53034

53035

- rs6000_expand_interleave (reg, operands[1], operands[1], false);

53036

+ rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN);

53037

emit_insn (gen_vsx_xvcvuxwdp (operands[0], reg));

53038

DONE;

53039

})

53040

@@ -963,8 +948,19 @@

53041

(match_operand:V16QI 3 "vlogical_operand" "")]

53042

"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"

53043

{

53044

- emit_insn (gen_altivec_vperm_<mode> (operands[0], operands[1], operands[2],

53045

- operands[3]));

53046

+ if (BYTES_BIG_ENDIAN)

53047

+ emit_insn (gen_altivec_vperm_<mode> (operands[0], operands[1],

53048

+ operands[2], operands[3]));

53049

+ else

53050

+ {

53051

+ /* We have changed lvsr to lvsl, so to complete the transformation

53052

+ of vperm for LE, we must swap the inputs. */

53053

+ rtx unspec = gen_rtx_UNSPEC (<MODE>mode,

53054

+ gen_rtvec (3, operands[2],

53055

+ operands[1], operands[3]),

53056

+ UNSPEC_VPERM);

53057

+ emit_move_insn (operands[0], unspec);

53058

+ }

53059

DONE;

53060

})

53061

53062

@@ -1064,7 +1060,7 @@

53063

[(set (match_operand:VEC_I 0 "vint_operand" "")

53064

(rotate:VEC_I (match_operand:VEC_I 1 "vint_operand" "")

53065

(match_operand:VEC_I 2 "vint_operand" "")))]

53066

- "TARGET_ALTIVEC"

53067

+ "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"

53068

"")

53069

53070

;; Expanders for arithmetic shift left on each vector element

53071

@@ -1072,7 +1068,7 @@

53072

[(set (match_operand:VEC_I 0 "vint_operand" "")

53073

(ashift:VEC_I (match_operand:VEC_I 1 "vint_operand" "")

53074

(match_operand:VEC_I 2 "vint_operand" "")))]

53075

- "TARGET_ALTIVEC"

53076

+ "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"

53077

"")

53078

53079

;; Expanders for logical shift right on each vector element

53080

@@ -1080,7 +1076,7 @@

53081

[(set (match_operand:VEC_I 0 "vint_operand" "")

53082

(lshiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand" "")

53083

(match_operand:VEC_I 2 "vint_operand" "")))]

53084

- "TARGET_ALTIVEC"

53085

+ "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"

53086

"")

53087

53088

;; Expanders for arithmetic shift right on each vector element

53089

@@ -1088,7 +1084,7 @@

53090

[(set (match_operand:VEC_I 0 "vint_operand" "")

53091

(ashiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand" "")

53092

(match_operand:VEC_I 2 "vint_operand" "")))]

53093

- "TARGET_ALTIVEC"

53094

+ "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"

53095

"")

53096

53097

;; Vector reduction expanders for VSX

53098

Index: gcc/config/rs6000/constraints.md

53099

===================================================================

53100

--- a/src/gcc/config/rs6000/constraints.md (.../tags/gcc_4_8_2_release)

53101

+++ b/src/gcc/config/rs6000/constraints.md (.../branches/gcc-4_8-branch)

53102

@@ -52,22 +52,62 @@

53103

"@internal")

53104

53105

;; Use w as a prefix to add VSX modes

53106

-;; vector double (V2DF)

53107

+;; any VSX register

53108

+(define_register_constraint "wa" "rs6000_constraints[RS6000_CONSTRAINT_wa]"

53109

+ "Any VSX register if the -mvsx option was used or NO_REGS.")

53110

+

53111

(define_register_constraint "wd" "rs6000_constraints[RS6000_CONSTRAINT_wd]"

53112

- "@internal")

53113

+ "VSX vector register to hold vector double data or NO_REGS.")

53114

53115

-;; vector float (V4SF)

53116

(define_register_constraint "wf" "rs6000_constraints[RS6000_CONSTRAINT_wf]"

53117

- "@internal")

53118

+ "VSX vector register to hold vector float data or NO_REGS.")

53119

53120

-;; scalar double (DF)

53121

+(define_register_constraint "wg" "rs6000_constraints[RS6000_CONSTRAINT_wg]"

53122

+ "If -mmfpgpr was used, a floating point register or NO_REGS.")

53123

+

53124

+(define_register_constraint "wl" "rs6000_constraints[RS6000_CONSTRAINT_wl]"

53125

+ "Floating point register if the LFIWAX instruction is enabled or NO_REGS.")

53126

+

53127

+(define_register_constraint "wm" "rs6000_constraints[RS6000_CONSTRAINT_wm]"

53128

+ "VSX register if direct move instructions are enabled, or NO_REGS.")

53129

+

53130

+;; NO_REGs register constraint, used to merge mov{sd,sf}, since movsd can use

53131

+;; direct move directly, and movsf can't to move between the register sets.

53132

+;; There is a mode_attr that resolves to wm for SDmode and wn for SFmode

53133

+(define_register_constraint "wn" "NO_REGS" "No register (NO_REGS).")

53134

+

53135

+(define_register_constraint "wr" "rs6000_constraints[RS6000_CONSTRAINT_wr]"

53136

+ "General purpose register if 64-bit instructions are enabled or NO_REGS.")

53137

+

53138

(define_register_constraint "ws" "rs6000_constraints[RS6000_CONSTRAINT_ws]"

53139

- "@internal")

53140

+ "VSX vector register to hold scalar double values or NO_REGS.")

53141

53142

-;; any VSX register

53143

-(define_register_constraint "wa" "rs6000_constraints[RS6000_CONSTRAINT_wa]"

53144

- "@internal")

53145

+(define_register_constraint "wt" "rs6000_constraints[RS6000_CONSTRAINT_wt]"

53146

+ "VSX vector register to hold 128 bit integer or NO_REGS.")

53147

53148

+(define_register_constraint "wu" "rs6000_constraints[RS6000_CONSTRAINT_wu]"

53149

+ "Altivec register to use for float/32-bit int loads/stores or NO_REGS.")

53150

+

53151

+(define_register_constraint "wv" "rs6000_constraints[RS6000_CONSTRAINT_wv]"

53152

+ "Altivec register to use for double loads/stores or NO_REGS.")

53153

+

53154

+(define_register_constraint "ww" "rs6000_constraints[RS6000_CONSTRAINT_ww]"

53155

+ "FP or VSX register to perform float operations under -mvsx or NO_REGS.")

53156

+

53157

+(define_register_constraint "wx" "rs6000_constraints[RS6000_CONSTRAINT_wx]"

53158

+ "Floating point register if the STFIWX instruction is enabled or NO_REGS.")

53159

+

53160

+(define_register_constraint "wy" "rs6000_constraints[RS6000_CONSTRAINT_wy]"

53161

+ "VSX vector register to hold scalar float values or NO_REGS.")

53162

+

53163

+(define_register_constraint "wz" "rs6000_constraints[RS6000_CONSTRAINT_wz]"

53164

+ "Floating point register if the LFIWZX instruction is enabled or NO_REGS.")

53165

+

53166

+;; Lq/stq validates the address for load/store quad

53167

+(define_memory_constraint "wQ"

53168

+ "Memory operand suitable for the load/store quad instructions"

53169

+ (match_operand 0 "quad_memory_operand"))

53170

+

53171

;; Altivec style load/store that ignores the bottom bits of the address

53172

(define_memory_constraint "wZ"

53173

"Indexed or indirect memory operand, ignoring the bottom 4 bits"

53174

Index: gcc/config/rs6000/predicates.md

53175

===================================================================

53176

--- a/src/gcc/config/rs6000/predicates.md (.../tags/gcc_4_8_2_release)

53177

+++ b/src/gcc/config/rs6000/predicates.md (.../branches/gcc-4_8-branch)

53178

@@ -124,6 +124,11 @@

53179

(and (match_code "const_int")

53180

(match_test "INTVAL (op) >= -16 && INTVAL (op) <= 15")))

53181

53182

+;; Return 1 if op is a unsigned 3-bit constant integer.

53183

+(define_predicate "u3bit_cint_operand"

53184

+ (and (match_code "const_int")

53185

+ (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 7")))

53186

+

53187

;; Return 1 if op is a unsigned 5-bit constant integer.

53188

(define_predicate "u5bit_cint_operand"

53189

(and (match_code "const_int")

53190

@@ -135,6 +140,11 @@

53191

(and (match_code "const_int")

53192

(match_test "INTVAL (op) >= -128 && INTVAL (op) <= 127")))

53193

53194

+;; Return 1 if op is a unsigned 10-bit constant integer.

53195

+(define_predicate "u10bit_cint_operand"

53196

+ (and (match_code "const_int")

53197

+ (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 1023")))

53198

+

53199

;; Return 1 if op is a constant integer that can fit in a D field.

53200

(define_predicate "short_cint_operand"

53201

(and (match_code "const_int")

53202

@@ -161,11 +171,21 @@

53203

(and (match_code "const_int")

53204

(match_test "IN_RANGE (INTVAL (op), 0, 1)")))

53205

53206

+;; Match op = 0..3.

53207

+(define_predicate "const_0_to_3_operand"

53208

+ (and (match_code "const_int")

53209

+ (match_test "IN_RANGE (INTVAL (op), 0, 3)")))

53210

+

53211

;; Match op = 2 or op = 3.

53212

(define_predicate "const_2_to_3_operand"

53213

(and (match_code "const_int")

53214

(match_test "IN_RANGE (INTVAL (op), 2, 3)")))

53215

53216

+;; Match op = 0..15

53217

+(define_predicate "const_0_to_15_operand"

53218

+ (and (match_code "const_int")

53219

+ (match_test "IN_RANGE (INTVAL (op), 0, 15)")))

53220

+

53221

;; Return 1 if op is a register that is not special.

53222

(define_predicate "gpc_reg_operand"

53223

(match_operand 0 "register_operand")

53224

@@ -182,9 +202,95 @@

53225

if (REGNO (op) >= ARG_POINTER_REGNUM && !CA_REGNO_P (REGNO (op)))

53226

return 1;

53227

53228

+ if (TARGET_VSX && VSX_REGNO_P (REGNO (op)))

53229

+ return 1;

53230

+

53231

return INT_REGNO_P (REGNO (op)) || FP_REGNO_P (REGNO (op));

53232

})

53233

53234

+;; Return 1 if op is a general purpose register. Unlike gpc_reg_operand, don't

53235

+;; allow floating point or vector registers.

53236

+(define_predicate "int_reg_operand"

53237

+ (match_operand 0 "register_operand")

53238

+{

53239

+ if ((TARGET_E500_DOUBLE || TARGET_SPE) && invalid_e500_subreg (op, mode))

53240

+ return 0;

53241

+

53242

+ if (GET_CODE (op) == SUBREG)

53243

+ op = SUBREG_REG (op);

53244

+

53245

+ if (!REG_P (op))

53246

+ return 0;

53247

+

53248

+ if (REGNO (op) >= FIRST_PSEUDO_REGISTER)

53249

+ return 1;

53250

+

53251

+ return INT_REGNO_P (REGNO (op));

53252

+})

53253

+

53254

+;; Like int_reg_operand, but only return true for base registers

53255

+(define_predicate "base_reg_operand"

53256

+ (match_operand 0 "int_reg_operand")

53257

+{

53258

+ if (GET_CODE (op) == SUBREG)

53259

+ op = SUBREG_REG (op);

53260

+

53261

+ if (!REG_P (op))

53262

+ return 0;

53263

+

53264

+ return (REGNO (op) != FIRST_GPR_REGNO);

53265

+})

53266

+

53267

+;; Return 1 if op is a HTM specific SPR register.

53268

+(define_predicate "htm_spr_reg_operand"

53269

+ (match_operand 0 "register_operand")

53270

+{

53271

+ if (!TARGET_HTM)

53272

+ return 0;

53273

+

53274

+ if (GET_CODE (op) == SUBREG)

53275

+ op = SUBREG_REG (op);

53276

+

53277

+ if (!REG_P (op))

53278

+ return 0;

53279

+

53280

+ switch (REGNO (op))

53281

+ {

53282

+ case TFHAR_REGNO:

53283

+ case TFIAR_REGNO:

53284

+ case TEXASR_REGNO:

53285

+ return 1;

53286

+ default:

53287

+ break;

53288

+ }

53289

+

53290

+ /* Unknown SPR. */

53291

+ return 0;

53292

+})

53293

+

53294

+;; Return 1 if op is a general purpose register that is an even register

53295

+;; which suitable for a load/store quad operation

53296

+(define_predicate "quad_int_reg_operand"

53297

+ (match_operand 0 "register_operand")

53298

+{

53299

+ HOST_WIDE_INT r;

53300

+

53301

+ if (!TARGET_QUAD_MEMORY && !TARGET_QUAD_MEMORY_ATOMIC)

53302

+ return 0;

53303

+

53304

+ if (GET_CODE (op) == SUBREG)

53305

+ op = SUBREG_REG (op);

53306

+

53307

+ if (!REG_P (op))

53308

+ return 0;

53309

+

53310

+ r = REGNO (op);

53311

+ if (r >= FIRST_PSEUDO_REGISTER)

53312

+ return 1;

53313

+

53314

+ return (INT_REGNO_P (r) && ((r & 1) == 0));

53315

+})

53316

+

53317

;; Return 1 if op is a register that is a condition register field.

53318

(define_predicate "cc_reg_operand"

53319

(match_operand 0 "register_operand")

53320

@@ -315,6 +421,11 @@

53321

&& CONST_DOUBLE_HIGH (op) == 0")

53322

(match_operand 0 "gpc_reg_operand"))))

53323

53324

+;; Like reg_or_logical_cint_operand, but allow vsx registers

53325

+(define_predicate "vsx_reg_or_cint_operand"

53326

+ (ior (match_operand 0 "vsx_register_operand")

53327

+ (match_operand 0 "reg_or_logical_cint_operand")))

53328

+

53329

;; Return 1 if operand is a CONST_DOUBLE that can be set in a register

53330

;; with no more than one instruction per word.

53331

(define_predicate "easy_fp_constant"

53332

@@ -333,6 +444,11 @@

53333

&& mode != DImode)

53334

return 1;

53335

53336

+ /* The constant 0.0 is easy under VSX. */

53337

+ if ((mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode)

53338

+ && VECTOR_UNIT_VSX_P (DFmode) && op == CONST0_RTX (mode))

53339

+ return 1;

53340

+

53341

if (DECIMAL_FLOAT_MODE_P (mode))

53342

return 0;

53343

53344

@@ -521,6 +637,55 @@

53345

(and (match_operand 0 "memory_operand")

53346

(match_test "offsettable_nonstrict_memref_p (op)")))

53347

53348

+;; Return 1 if the operand is suitable for load/store quad memory.

53349

+;; This predicate only checks for non-atomic loads/stores (not lqarx/stqcx).

53350

+(define_predicate "quad_memory_operand"

53351

+ (match_code "mem")

53352

+{

53353

+ rtx addr, op0, op1;

53354

+ int ret;

53355

+

53356

+ if (!TARGET_QUAD_MEMORY && !TARGET_SYNC_TI)

53357

+ ret = 0;

53358

+

53359

+ else if (!memory_operand (op, mode))

53360

+ ret = 0;

53361

+

53362

+ else if (GET_MODE_SIZE (GET_MODE (op)) != 16)

53363

+ ret = 0;

53364

+

53365

+ else if (MEM_ALIGN (op) < 128)

53366

+ ret = 0;

53367

+

53368

+ else

53369

+ {

53370

+ addr = XEXP (op, 0);

53371

+ if (int_reg_operand (addr, Pmode))

53372

+ ret = 1;

53373

+

53374

+ else if (GET_CODE (addr) != PLUS)

53375

+ ret = 0;

53376

+

53377

+ else

53378

+ {

53379

+ op0 = XEXP (addr, 0);

53380

+ op1 = XEXP (addr, 1);

53381

+ ret = (int_reg_operand (op0, Pmode)

53382

+ && GET_CODE (op1) == CONST_INT

53383

+ && IN_RANGE (INTVAL (op1), -32768, 32767)

53384

+ && (INTVAL (op1) & 15) == 0);

53385

+ }

53386

+ }

53387

+

53388

+ if (TARGET_DEBUG_ADDR)

53389

+ {

53390

+ fprintf (stderr, "\nquad_memory_operand, ret = %s\n", ret ? "true" : "false");

53391

+ debug_rtx (op);

53392

+ }

53393

+

53394

+ return ret;

53395

+})

53396

+

53397

;; Return 1 if the operand is an indexed or indirect memory operand.

53398

(define_predicate "indexed_or_indirect_operand"

53399

(match_code "mem")

53400

@@ -535,6 +700,19 @@

53401

return indexed_or_indirect_address (op, mode);

53402

})

53403

53404

+;; Like indexed_or_indirect_operand, but also allow a GPR register if direct

53405

+;; moves are supported.

53406

+(define_predicate "reg_or_indexed_operand"

53407

+ (match_code "mem,reg")

53408

+{

53409

+ if (MEM_P (op))

53410

+ return indexed_or_indirect_operand (op, mode);

53411

+ else if (TARGET_DIRECT_MOVE)

53412

+ return register_operand (op, mode);

53413

+ return

53414

+ 0;

53415

+})

53416

+

53417

;; Return 1 if the operand is an indexed or indirect memory operand with an

53418

;; AND -16 in it, used to recognize when we need to switch to Altivec loads

53419

;; to realign loops instead of VSX (altivec silently ignores the bottom bits,

53420

@@ -560,6 +738,28 @@

53421

&& REG_P (XEXP (op, 1)))")

53422

(match_operand 0 "address_operand")))

53423

53424

+;; Return 1 if the operand is an index-form address.

53425

+(define_special_predicate "indexed_address"

53426

+ (match_test "(GET_CODE (op) == PLUS

53427

+ && REG_P (XEXP (op, 0))

53428

+ && REG_P (XEXP (op, 1)))"))

53429

+

53430

+;; Return 1 if the operand is a MEM with an update-form address. This may

53431

+;; also include update-indexed form.

53432

+(define_special_predicate "update_address_mem"

53433

+ (match_test "(MEM_P (op)

53434

+ && (GET_CODE (XEXP (op, 0)) == PRE_INC

53435

+ || GET_CODE (XEXP (op, 0)) == PRE_DEC

53436

+ || GET_CODE (XEXP (op, 0)) == PRE_MODIFY))"))

53437

+

53438

+;; Return 1 if the operand is a MEM with an update-indexed-form address. Note

53439

+;; that PRE_INC/PRE_DEC will always be non-indexed (i.e. non X-form) since the

53440

+;; increment is based on the mode size and will therefor always be a const.

53441

+(define_special_predicate "update_indexed_address_mem"

53442

+ (match_test "(MEM_P (op)

53443

+ && GET_CODE (XEXP (op, 0)) == PRE_MODIFY

53444

+ && indexed_address (XEXP (XEXP (op, 0), 1), mode))"))

53445

+

53446

;; Used for the destination of the fix_truncdfsi2 expander.

53447

;; If stfiwx will be used, the result goes to memory; otherwise,

53448

;; we're going to emit a store and a load of a subreg, so the dest is a

53449

@@ -883,7 +1083,8 @@

53450

(and (match_code "symbol_ref")

53451

(match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))

53452

&& ((SYMBOL_REF_LOCAL_P (op)

53453

- && (DEFAULT_ABI != ABI_AIX

53454

+ && ((DEFAULT_ABI != ABI_AIX

53455

+ && DEFAULT_ABI != ABI_ELFv2)

53456

|| !SYMBOL_REF_EXTERNAL_P (op)))

53457

|| (op == XEXP (DECL_RTL (current_function_decl),

53458

0)))")))

53459

@@ -1364,6 +1565,26 @@

53460

return 1;

53461

})

53462

53463

+;; Return 1 if OP is valid for crsave insn, known to be a PARALLEL.

53464

+(define_predicate "crsave_operation"

53465

+ (match_code "parallel")

53466

+{

53467

+ int count = XVECLEN (op, 0);

53468

+ int i;

53469

+

53470

+ for (i = 1; i < count; i++)

53471

+ {

53472

+ rtx exp = XVECEXP (op, 0, i);

53473

+

53474

+ if (GET_CODE (exp) != USE

53475

+ || GET_CODE (XEXP (exp, 0)) != REG

53476

+ || GET_MODE (XEXP (exp, 0)) != CCmode

53477

+ || ! CR_REGNO_P (REGNO (XEXP (exp, 0))))

53478

+ return 0;

53479

+ }

53480

+ return 1;

53481

+})

53482

+

53483

;; Return 1 if OP is valid for lmw insn, known to be a PARALLEL.

53484

(define_predicate "lmw_operation"

53485

(match_code "parallel")

53486

@@ -1534,3 +1755,99 @@

53487

53488

return GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_TOCREL;

53489

})

53490

+

53491

+;; Match the first insn (addis) in fusing the combination of addis and loads to

53492

+;; GPR registers on power8.

53493

+(define_predicate "fusion_gpr_addis"

53494

+ (match_code "const_int,high,plus")

53495

+{

53496

+ HOST_WIDE_INT value;

53497

+ rtx int_const;

53498

+

53499

+ if (GET_CODE (op) == HIGH)

53500

+ return 1;

53501

+

53502

+ if (CONST_INT_P (op))

53503

+ int_const = op;

53504

+

53505

+ else if (GET_CODE (op) == PLUS

53506

+ && base_reg_operand (XEXP (op, 0), Pmode)

53507

+ && CONST_INT_P (XEXP (op, 1)))

53508

+ int_const = XEXP (op, 1);

53509

+

53510

+ else

53511

+ return 0;

53512

+

53513

+ /* Power8 currently will only do the fusion if the top 11 bits of the addis

53514

+ value are all 1's or 0's. */

53515

+ value = INTVAL (int_const);

53516

+ if ((value & (HOST_WIDE_INT)0xffff) != 0)

53517

+ return 0;

53518

+

53519

+ if ((value & (HOST_WIDE_INT)0xffff0000) == 0)

53520

+ return 0;

53521

+

53522

+ return (IN_RANGE (value >> 16, -32, 31));

53523

+})

53524

+

53525

+;; Match the second insn (lbz, lhz, lwz, ld) in fusing the combination of addis

53526

+;; and loads to GPR registers on power8.

53527

+(define_predicate "fusion_gpr_mem_load"

53528

+ (match_code "mem,sign_extend,zero_extend")

53529

+{

53530

+ rtx addr;

53531

+

53532

+ /* Handle sign/zero extend. */

53533

+ if (GET_CODE (op) == ZERO_EXTEND

53534

+ || (TARGET_P8_FUSION_SIGN && GET_CODE (op) == SIGN_EXTEND))

53535

+ {

53536

+ op = XEXP (op, 0);

53537

+ mode = GET_MODE (op);

53538

+ }

53539

+

53540

+ if (!MEM_P (op))

53541

+ return 0;

53542

+

53543

+ switch (mode)

53544

+ {

53545

+ case QImode:

53546

+ case HImode:

53547

+ case SImode:

53548

+ break;

53549

+

53550

+ case DImode:

53551

+ if (!TARGET_POWERPC64)

53552

+ return 0;

53553

+ break;

53554

+

53555

+ default:

53556

+ return 0;

53557

+ }

53558

+

53559

+ addr = XEXP (op, 0);

53560

+ if (GET_CODE (addr) == PLUS)

53561

+ {

53562

+ rtx base = XEXP (addr, 0);

53563

+ rtx offset = XEXP (addr, 1);

53564

+

53565

+ return (base_reg_operand (base, GET_MODE (base))

53566

+ && satisfies_constraint_I (offset));

53567

+ }

53568

+

53569

+ else if (GET_CODE (addr) == LO_SUM)

53570

+ {

53571

+ rtx base = XEXP (addr, 0);

53572

+ rtx offset = XEXP (addr, 1);

53573

+

53574

+ if (!base_reg_operand (base, GET_MODE (base)))

53575

+ return 0;

53576

+

53577

+ else if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))

53578

+ return small_toc_ref (offset, GET_MODE (offset));

53579

+

53580

+ else if (TARGET_ELF && !TARGET_POWERPC64)

53581

+ return CONSTANT_P (offset);

53582

+ }

53583

+

53584

+ return 0;

53585

+})

53586

Index: gcc/config/rs6000/ppc-asm.h

53587

===================================================================

53588

--- a/src/gcc/config/rs6000/ppc-asm.h (.../tags/gcc_4_8_2_release)

53589

+++ b/src/gcc/config/rs6000/ppc-asm.h (.../branches/gcc-4_8-branch)

53590

@@ -256,7 +256,30 @@

53591

* the real function with one or two leading periods respectively.

53592

*/

53593

53594

-#if defined (__powerpc64__)

53595

+#if defined(__powerpc64__) && _CALL_ELF == 2

53596

+

53597

+/* Defining "toc" above breaks @toc in assembler code. */

53598

+#undef toc

53599

+

53600

+#define FUNC_NAME(name) GLUE(__USER_LABEL_PREFIX__,name)

53601

+#define JUMP_TARGET(name) FUNC_NAME(name)

53602

+#define FUNC_START(name) \

53603

+ .type FUNC_NAME(name),@function; \

53604

+ .globl FUNC_NAME(name); \

53605

+FUNC_NAME(name): \

53606

+0: addis 2,12,(.TOC.-0b)@ha; \

53607

+ addi 2,2,(.TOC.-0b)@l; \

53608

+ .localentry FUNC_NAME(name),.-FUNC_NAME(name)

53609

+

53610

+#define HIDDEN_FUNC(name) \

53611

+ FUNC_START(name) \

53612

+ .hidden FUNC_NAME(name);

53613

+

53614

+#define FUNC_END(name) \

53615

+ .size FUNC_NAME(name),.-FUNC_NAME(name)

53616

+

53617

+#elif defined (__powerpc64__)

53618

+

53619

#define FUNC_NAME(name) GLUE(.,name)

53620

#define JUMP_TARGET(name) FUNC_NAME(name)

53621

#define FUNC_START(name) \

53622

Index: gcc/config/rs6000/htm.md

53623

===================================================================

53624

--- a/src/gcc/config/rs6000/htm.md (.../tags/gcc_4_8_2_release)

53625

+++ b/src/gcc/config/rs6000/htm.md (.../branches/gcc-4_8-branch)

53626

@@ -0,0 +1,366 @@

53627

+;; Hardware Transactional Memory (HTM) patterns.

53628

53629

+;; Contributed by Peter Bergner <bergner@vnet.ibm.com>.

53630

+

53631

+;; This file is part of GCC.

53632

+

53633

+;; GCC is free software; you can redistribute it and/or modify it

53634

+;; under the terms of the GNU General Public License as published

53635

+;; by the Free Software Foundation; either version 3, or (at your

53636

+;; option) any later version.

53637

+

53638

+;; GCC is distributed in the hope that it will be useful, but WITHOUT

53639

+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY

53640

+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public

53641

+;; License for more details.

53642

+

53643

+;; You should have received a copy of the GNU General Public License

53644

+;; along with GCC; see the file COPYING3. If not see

53645

+;; <http://www.gnu.org/licenses/>.

53646

+

53647

+(define_constants

53648

+ [(TFHAR_SPR 128)

53649

+ (TFIAR_SPR 129)

53650

+ (TEXASR_SPR 130)

53651

+ (TEXASRU_SPR 131)

53652

+ (MAX_HTM_OPERANDS 4)

53653

+ ])

53654

+

53655

+;;

53656

+;; UNSPEC_VOLATILE usage

53657

+;;

53658

+

53659

+(define_c_enum "unspecv"

53660

+ [UNSPECV_HTM_TABORT

53661

+ UNSPECV_HTM_TABORTDC

53662

+ UNSPECV_HTM_TABORTDCI

53663

+ UNSPECV_HTM_TABORTWC

53664

+ UNSPECV_HTM_TABORTWCI

53665

+ UNSPECV_HTM_TBEGIN

53666

+ UNSPECV_HTM_TCHECK

53667

+ UNSPECV_HTM_TEND

53668

+ UNSPECV_HTM_TRECHKPT

53669

+ UNSPECV_HTM_TRECLAIM

53670

+ UNSPECV_HTM_TSR

53671

+ UNSPECV_HTM_MFSPR

53672

+ UNSPECV_HTM_MTSPR

53673

+ ])

53674

+

53675

+

53676

+(define_expand "tabort"

53677

+ [(set (match_dup 2)

53678

+ (unspec_volatile:CC [(match_operand:SI 1 "int_reg_operand" "")]

53679

+ UNSPECV_HTM_TABORT))

53680

+ (set (match_dup 3)

53681

+ (eq:SI (match_dup 2)

53682

+ (const_int 0)))

53683

+ (set (match_operand:SI 0 "int_reg_operand" "")

53684

+ (minus:SI (const_int 1) (match_dup 3)))]

53685

+ "TARGET_HTM"

53686

+{

53687

+ operands[2] = gen_rtx_REG (CCmode, CR0_REGNO);

53688

+ operands[3] = gen_reg_rtx (SImode);

53689

+})

53690

+

53691

+(define_insn "*tabort_internal"

53692

+ [(set (match_operand:CC 1 "cc_reg_operand" "=x")

53693

+ (unspec_volatile:CC [(match_operand:SI 0 "int_reg_operand" "r")]

53694

+ UNSPECV_HTM_TABORT))]

53695

+ "TARGET_HTM"

53696

+ "tabort. %0"

53697

+ [(set_attr "type" "htm")

53698

+ (set_attr "length" "4")])

53699

+

53700

+(define_expand "tabortdc"

53701

+ [(set (match_dup 4)

53702

+ (unspec_volatile:CC [(match_operand 1 "u5bit_cint_operand" "n")

53703

+ (match_operand:SI 2 "gpc_reg_operand" "r")

53704

+ (match_operand:SI 3 "gpc_reg_operand" "r")]

53705

+ UNSPECV_HTM_TABORTDC))

53706

+ (set (match_dup 5)

53707

+ (eq:SI (match_dup 4)

53708

+ (const_int 0)))

53709

+ (set (match_operand:SI 0 "int_reg_operand" "")

53710

+ (minus:SI (const_int 1) (match_dup 5)))]

53711

+ "TARGET_HTM"

53712

+{

53713

+ operands[4] = gen_rtx_REG (CCmode, CR0_REGNO);

53714

+ operands[5] = gen_reg_rtx (SImode);

53715

+})

53716

+

53717

+(define_insn "*tabortdc_internal"

53718

+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")

53719

+ (unspec_volatile:CC [(match_operand 0 "u5bit_cint_operand" "n")

53720

+ (match_operand:SI 1 "gpc_reg_operand" "r")

53721

+ (match_operand:SI 2 "gpc_reg_operand" "r")]

53722

+ UNSPECV_HTM_TABORTDC))]

53723

+ "TARGET_HTM"

53724

+ "tabortdc. %0,%1,%2"

53725

+ [(set_attr "type" "htm")

53726

+ (set_attr "length" "4")])

53727

+

53728

+(define_expand "tabortdci"

53729

+ [(set (match_dup 4)

53730

+ (unspec_volatile:CC [(match_operand 1 "u5bit_cint_operand" "n")

53731

+ (match_operand:SI 2 "gpc_reg_operand" "r")

53732

+ (match_operand 3 "s5bit_cint_operand" "n")]

53733

+ UNSPECV_HTM_TABORTDCI))

53734

+ (set (match_dup 5)

53735

+ (eq:SI (match_dup 4)

53736

+ (const_int 0)))

53737

+ (set (match_operand:SI 0 "int_reg_operand" "")

53738

+ (minus:SI (const_int 1) (match_dup 5)))]

53739

+ "TARGET_HTM"

53740

+{

53741

+ operands[4] = gen_rtx_REG (CCmode, CR0_REGNO);

53742

+ operands[5] = gen_reg_rtx (SImode);

53743

+})

53744

+

53745

+(define_insn "*tabortdci_internal"

53746

+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")

53747

+ (unspec_volatile:CC [(match_operand 0 "u5bit_cint_operand" "n")

53748

+ (match_operand:SI 1 "gpc_reg_operand" "r")

53749

+ (match_operand 2 "s5bit_cint_operand" "n")]

53750

+ UNSPECV_HTM_TABORTDCI))]

53751

+ "TARGET_HTM"

53752

+ "tabortdci. %0,%1,%2"

53753

+ [(set_attr "type" "htm")

53754

+ (set_attr "length" "4")])

53755

+

53756

+(define_expand "tabortwc"

53757

+ [(set (match_dup 4)

53758

+ (unspec_volatile:CC [(match_operand 1 "u5bit_cint_operand" "n")

53759

+ (match_operand:SI 2 "gpc_reg_operand" "r")

53760

+ (match_operand:SI 3 "gpc_reg_operand" "r")]

53761

+ UNSPECV_HTM_TABORTWC))

53762

+ (set (match_dup 5)

53763

+ (eq:SI (match_dup 4)

53764

+ (const_int 0)))

53765

+ (set (match_operand:SI 0 "int_reg_operand" "")

53766

+ (minus:SI (const_int 1) (match_dup 5)))]

53767

+ "TARGET_HTM"

53768

+{

53769

+ operands[4] = gen_rtx_REG (CCmode, CR0_REGNO);

53770

+ operands[5] = gen_reg_rtx (SImode);

53771

+})

53772

+

53773

+(define_insn "*tabortwc_internal"

53774

+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")

53775

+ (unspec_volatile:CC [(match_operand 0 "u5bit_cint_operand" "n")

53776

+ (match_operand:SI 1 "gpc_reg_operand" "r")

53777

+ (match_operand:SI 2 "gpc_reg_operand" "r")]

53778

+ UNSPECV_HTM_TABORTWC))]

53779

+ "TARGET_HTM"

53780

+ "tabortwc. %0,%1,%2"

53781

+ [(set_attr "type" "htm")

53782

+ (set_attr "length" "4")])

53783

+

53784

+(define_expand "tabortwci"

53785

+ [(set (match_dup 4)

53786

+ (unspec_volatile:CC [(match_operand 1 "u5bit_cint_operand" "n")

53787

+ (match_operand:SI 2 "gpc_reg_operand" "r")

53788

+ (match_operand 3 "s5bit_cint_operand" "n")]

53789

+ UNSPECV_HTM_TABORTWCI))

53790

+ (set (match_dup 5)

53791

+ (eq:SI (match_dup 4)

53792

+ (const_int 0)))

53793

+ (set (match_operand:SI 0 "int_reg_operand" "")

53794

+ (minus:SI (const_int 1) (match_dup 5)))]

53795

+ "TARGET_HTM"

53796

+{

53797

+ operands[4] = gen_rtx_REG (CCmode, CR0_REGNO);

53798

+ operands[5] = gen_reg_rtx (SImode);

53799

+})

53800

+

53801

+(define_expand "ttest"

53802

+ [(set (match_dup 1)

53803

+ (unspec_volatile:CC [(const_int 0)

53804

+ (reg:SI 0)

53805

+ (const_int 0)]

53806

+ UNSPECV_HTM_TABORTWCI))

53807

+ (set (subreg:CC (match_dup 2) 0) (match_dup 1))

53808

+ (set (match_dup 3) (lshiftrt:SI (match_dup 2) (const_int 24)))

53809

+ (parallel [(set (match_operand:SI 0 "int_reg_operand" "")

53810

+ (and:SI (match_dup 3) (const_int 15)))

53811

+ (clobber (scratch:CC))])]

53812

+ "TARGET_HTM"

53813

+{

53814

+ operands[1] = gen_rtx_REG (CCmode, CR0_REGNO);

53815

+ operands[2] = gen_reg_rtx (SImode);

53816

+ operands[3] = gen_reg_rtx (SImode);

53817

+})

53818

+

53819

+(define_insn "*tabortwci_internal"

53820

+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")

53821

+ (unspec_volatile:CC [(match_operand 0 "u5bit_cint_operand" "n")

53822

+ (match_operand:SI 1 "gpc_reg_operand" "r")

53823

+ (match_operand 2 "s5bit_cint_operand" "n")]

53824

+ UNSPECV_HTM_TABORTWCI))]

53825

+ "TARGET_HTM"

53826

+ "tabortwci. %0,%1,%2"

53827

+ [(set_attr "type" "htm")

53828

+ (set_attr "length" "4")])

53829

+

53830

+(define_expand "tbegin"

53831

+ [(set (match_dup 2)

53832

+ (unspec_volatile:CC [(match_operand 1 "const_0_to_1_operand" "n")]

53833

+ UNSPECV_HTM_TBEGIN))

53834

+ (set (match_dup 3)

53835

+ (eq:SI (match_dup 2)

53836

+ (const_int 0)))

53837

+ (set (match_operand:SI 0 "int_reg_operand" "")

53838

+ (minus:SI (const_int 1) (match_dup 3)))]

53839

+ "TARGET_HTM"

53840

+{

53841

+ operands[2] = gen_rtx_REG (CCmode, CR0_REGNO);

53842

+ operands[3] = gen_reg_rtx (SImode);

53843

+})

53844

+

53845

+(define_insn "*tbegin_internal"

53846

+ [(set (match_operand:CC 1 "cc_reg_operand" "=x")

53847

+ (unspec_volatile:CC [(match_operand 0 "const_0_to_1_operand" "n")]

53848

+ UNSPECV_HTM_TBEGIN))]

53849

+ "TARGET_HTM"

53850

+ "tbegin. %0"

53851

+ [(set_attr "type" "htm")

53852

+ (set_attr "length" "4")])

53853

+

53854

+(define_expand "tcheck"

53855

+ [(set (match_dup 2)

53856

+ (unspec_volatile:CC [(match_operand 1 "u3bit_cint_operand" "n")]

53857

+ UNSPECV_HTM_TCHECK))

53858

+ (set (match_dup 3)

53859

+ (eq:SI (match_dup 2)

53860

+ (const_int 0)))

53861

+ (set (match_operand:SI 0 "int_reg_operand" "")

53862

+ (minus:SI (const_int 1) (match_dup 3)))]

53863

+ "TARGET_HTM"

53864

+{

53865

+ operands[2] = gen_rtx_REG (CCmode, CR0_REGNO);

53866

+ operands[3] = gen_reg_rtx (SImode);

53867

+})

53868

+

53869

+(define_insn "*tcheck_internal"

53870

+ [(set (match_operand:CC 1 "cc_reg_operand" "=x")

53871

+ (unspec_volatile:CC [(match_operand 0 "u3bit_cint_operand" "n")]

53872

+ UNSPECV_HTM_TCHECK))]

53873

+ "TARGET_HTM"

53874

+ "tcheck. %0"

53875

+ [(set_attr "type" "htm")

53876

+ (set_attr "length" "4")])

53877

+

53878

+(define_expand "tend"

53879

+ [(set (match_dup 2)

53880

+ (unspec_volatile:CC [(match_operand 1 "const_0_to_1_operand" "n")]

53881

+ UNSPECV_HTM_TEND))

53882

+ (set (match_dup 3)

53883

+ (eq:SI (match_dup 2)

53884

+ (const_int 0)))

53885

+ (set (match_operand:SI 0 "int_reg_operand" "")

53886

+ (minus:SI (const_int 1) (match_dup 3)))]

53887

+ "TARGET_HTM"

53888

+{

53889

+ operands[2] = gen_rtx_REG (CCmode, CR0_REGNO);

53890

+ operands[3] = gen_reg_rtx (SImode);

53891

+})

53892

+

53893

+(define_insn "*tend_internal"

53894

+ [(set (match_operand:CC 1 "cc_reg_operand" "=x")

53895

+ (unspec_volatile:CC [(match_operand 0 "const_0_to_1_operand" "n")]

53896

+ UNSPECV_HTM_TEND))]

53897

+ "TARGET_HTM"

53898

+ "tend. %0"

53899

+ [(set_attr "type" "htm")

53900

+ (set_attr "length" "4")])

53901

+

53902

+(define_expand "trechkpt"

53903

+ [(set (match_dup 1)

53904

+ (unspec_volatile:CC [(const_int 0)]

53905

+ UNSPECV_HTM_TRECHKPT))

53906

+ (set (match_dup 2)

53907

+ (eq:SI (match_dup 1)

53908

+ (const_int 0)))

53909

+ (set (match_operand:SI 0 "int_reg_operand" "")

53910

+ (minus:SI (const_int 1) (match_dup 2)))]

53911

+ "TARGET_HTM"

53912

+{

53913

+ operands[1] = gen_rtx_REG (CCmode, CR0_REGNO);

53914

+ operands[2] = gen_reg_rtx (SImode);

53915

+})

53916

+

53917

+(define_insn "*trechkpt_internal"

53918

+ [(set (match_operand:CC 0 "cc_reg_operand" "=x")

53919

+ (unspec_volatile:CC [(const_int 0)]

53920

+ UNSPECV_HTM_TRECHKPT))]

53921

+ "TARGET_HTM"

53922

+ "trechkpt."

53923

+ [(set_attr "type" "htm")

53924

+ (set_attr "length" "4")])

53925

+

53926

+(define_expand "treclaim"

53927

+ [(set (match_dup 2)

53928

+ (unspec_volatile:CC [(match_operand:SI 1 "gpc_reg_operand" "r")]

53929

+ UNSPECV_HTM_TRECLAIM))

53930

+ (set (match_dup 3)

53931

+ (eq:SI (match_dup 2)

53932

+ (const_int 0)))

53933

+ (set (match_operand:SI 0 "int_reg_operand" "")

53934

+ (minus:SI (const_int 1) (match_dup 3)))]

53935

+ "TARGET_HTM"

53936

+{

53937

+ operands[2] = gen_rtx_REG (CCmode, CR0_REGNO);

53938

+ operands[3] = gen_reg_rtx (SImode);

53939

+})

53940

+

53941

+(define_insn "*treclaim_internal"

53942

+ [(set (match_operand:CC 1 "cc_reg_operand" "=x")

53943

+ (unspec_volatile:CC [(match_operand:SI 0 "gpc_reg_operand" "r")]

53944

+ UNSPECV_HTM_TRECLAIM))]

53945

+ "TARGET_HTM"

53946

+ "treclaim. %0"

53947

+ [(set_attr "type" "htm")

53948

+ (set_attr "length" "4")])

53949

+

53950

+(define_expand "tsr"

53951

+ [(set (match_dup 2)

53952

+ (unspec_volatile:CC [(match_operand 1 "const_0_to_1_operand" "n")]

53953

+ UNSPECV_HTM_TSR))

53954

+ (set (match_dup 3)

53955

+ (eq:SI (match_dup 2)

53956

+ (const_int 0)))

53957

+ (set (match_operand:SI 0 "int_reg_operand" "")

53958

+ (minus:SI (const_int 1) (match_dup 3)))]

53959

+ "TARGET_HTM"

53960

+{

53961

+ operands[2] = gen_rtx_REG (CCmode, CR0_REGNO);

53962

+ operands[3] = gen_reg_rtx (SImode);

53963

+})

53964

+

53965

+(define_insn "*tsr_internal"

53966

+ [(set (match_operand:CC 1 "cc_reg_operand" "=x")

53967

+ (unspec_volatile:CC [(match_operand 0 "const_0_to_1_operand" "n")]

53968

+ UNSPECV_HTM_TSR))]

53969

+ "TARGET_HTM"

53970

+ "tsr. %0"

53971

+ [(set_attr "type" "htm")

53972

+ (set_attr "length" "4")])

53973

+

53974

+(define_insn "htm_mfspr_<mode>"

53975

+ [(set (match_operand:P 0 "gpc_reg_operand" "=r")

53976

+ (unspec_volatile:P [(match_operand 1 "u10bit_cint_operand" "n")

53977

+ (match_operand:P 2 "htm_spr_reg_operand" "")]

53978

+ UNSPECV_HTM_MFSPR))]

53979

+ "TARGET_HTM"

53980

+ "mfspr %0,%1";

53981

+ [(set_attr "type" "htm")

53982

+ (set_attr "length" "4")])

53983

+

53984

+(define_insn "htm_mtspr_<mode>"

53985

+ [(set (match_operand:P 2 "htm_spr_reg_operand" "")

53986

+ (unspec_volatile:P [(match_operand:P 0 "gpc_reg_operand" "r")

53987

+ (match_operand 1 "u10bit_cint_operand" "n")]

53988

+ UNSPECV_HTM_MTSPR))]

53989

+ "TARGET_HTM"

53990

+ "mtspr %1,%0";

53991

+ [(set_attr "type" "htm")

53992

+ (set_attr "length" "4")])

53993

Index: gcc/config/rs6000/rs6000-modes.def

53994

===================================================================

53995

--- a/src/gcc/config/rs6000/rs6000-modes.def (.../tags/gcc_4_8_2_release)

53996

+++ b/src/gcc/config/rs6000/rs6000-modes.def (.../branches/gcc-4_8-branch)

53997

@@ -38,6 +38,12 @@

53998

VECTOR_MODES (INT, 16); /* V16QI V8HI V4SI V2DI */

53999

VECTOR_MODES (INT, 32); /* V32QI V16HI V8SI V4DI */

54000

VECTOR_MODE (INT, DI, 1);

54001

+VECTOR_MODE (INT, TI, 1);

54002

VECTOR_MODES (FLOAT, 8); /* V4HF V2SF */

54003

VECTOR_MODES (FLOAT, 16); /* V8HF V4SF V2DF */

54004

VECTOR_MODES (FLOAT, 32); /* V16HF V8SF V4DF */

54005

+

54006

+/* Replacement for TImode that only is allowed in GPRs. We also use PTImode

54007

+ for quad memory atomic operations to force getting an even/odd register

54008

+ combination. */

54009

+PARTIAL_INT_MODE (TI);

54010

Index: gcc/config/rs6000/rs6000-cpus.def

54011

===================================================================

54012

--- a/src/gcc/config/rs6000/rs6000-cpus.def (.../tags/gcc_4_8_2_release)

54013

+++ b/src/gcc/config/rs6000/rs6000-cpus.def (.../branches/gcc-4_8-branch)

54014

@@ -28,7 +28,7 @@

54015

ALTIVEC, since in general it isn't a win on power6. In ISA 2.04, fsel,

54016

fre, fsqrt, etc. were no longer documented as optional. Group masks by

54017

server and embedded. */

54018

-#define ISA_2_5_MASKS_EMBEDDED (ISA_2_2_MASKS \

54019

+#define ISA_2_5_MASKS_EMBEDDED (ISA_2_4_MASKS \

54020

| OPTION_MASK_CMPB \

54021

| OPTION_MASK_RECIP_PRECISION \

54022

| OPTION_MASK_PPC_GFXOPT \

54023

@@ -38,6 +38,8 @@

54024

54025

/* For ISA 2.06, don't add ISEL, since in general it isn't a win, but

54026

altivec is a win so enable it. */

54027

+ /* OPTION_MASK_VSX_TIMODE should be set, but disable it for now until

54028

+ PR 58587 is fixed. */

54029

#define ISA_2_6_MASKS_EMBEDDED (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_POPCNTD)

54030

#define ISA_2_6_MASKS_SERVER (ISA_2_5_MASKS_SERVER \

54031

| OPTION_MASK_POPCNTD \

54032

@@ -44,6 +46,16 @@

54033

| OPTION_MASK_ALTIVEC \

54034

| OPTION_MASK_VSX)

54035

54036

+/* For now, don't provide an embedded version of ISA 2.07. */

54037

+#define ISA_2_7_MASKS_SERVER (ISA_2_6_MASKS_SERVER \

54038

+ | OPTION_MASK_P8_FUSION \

54039

+ | OPTION_MASK_P8_VECTOR \

54040

+ | OPTION_MASK_CRYPTO \

54041

+ | OPTION_MASK_DIRECT_MOVE \

54042

+ | OPTION_MASK_HTM \

54043

+ | OPTION_MASK_QUAD_MEMORY \

54044

+ | OPTION_MASK_QUAD_MEMORY_ATOMIC)

54045

+

54046

#define POWERPC_7400_MASK (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC)

54047

54048

/* Deal with ports that do not have -mstrict-align. */

54049

@@ -60,23 +72,30 @@

54050

/* Mask of all options to set the default isa flags based on -mcpu=<xxx>. */

54051

#define POWERPC_MASKS (OPTION_MASK_ALTIVEC \

54052

| OPTION_MASK_CMPB \

54053

+ | OPTION_MASK_CRYPTO \

54054

| OPTION_MASK_DFP \

54055

+ | OPTION_MASK_DIRECT_MOVE \

54056

| OPTION_MASK_DLMZB \

54057

| OPTION_MASK_FPRND \

54058

+ | OPTION_MASK_HTM \

54059

| OPTION_MASK_ISEL \

54060

| OPTION_MASK_MFCRF \

54061

| OPTION_MASK_MFPGPR \

54062

| OPTION_MASK_MULHW \

54063

| OPTION_MASK_NO_UPDATE \

54064

+ | OPTION_MASK_P8_FUSION \

54065

+ | OPTION_MASK_P8_VECTOR \

54066

| OPTION_MASK_POPCNTB \

54067

| OPTION_MASK_POPCNTD \

54068

| OPTION_MASK_POWERPC64 \

54069

| OPTION_MASK_PPC_GFXOPT \

54070

| OPTION_MASK_PPC_GPOPT \

54071

+ | OPTION_MASK_QUAD_MEMORY \

54072

| OPTION_MASK_RECIP_PRECISION \

54073

| OPTION_MASK_SOFT_FLOAT \

54074

| OPTION_MASK_STRICT_ALIGN_OPTIONAL \

54075

- | OPTION_MASK_VSX)

54076

+ | OPTION_MASK_VSX \

54077

+ | OPTION_MASK_VSX_TIMODE)

54078

54079

#endif

54080

54081

@@ -166,10 +185,7 @@

54082

POWERPC_7400_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_MFCRF

54083

54084

| MASK_VSX | MASK_RECIP_PRECISION)

54085

-RS6000_CPU ("power8", PROCESSOR_POWER7, /* Don't add MASK_ISEL by default */

54086

- POWERPC_7400_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_MFCRF

54087

54088

- | MASK_VSX | MASK_RECIP_PRECISION)

54089

+RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER)

54090

RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0)

54091

RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT | MASK_POWERPC64)

54092

RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT | MASK_POWERPC64)

54093

Index: gcc/config/rs6000/t-linux64bele

54094

===================================================================

54095

--- a/src/gcc/config/rs6000/t-linux64bele (.../tags/gcc_4_8_2_release)

54096

+++ b/src/gcc/config/rs6000/t-linux64bele (.../branches/gcc-4_8-branch)

54097

@@ -0,0 +1,7 @@

54098

+#rs6000/t-linux64end

54099

+

54100

+MULTILIB_OPTIONS += mlittle

54101

+MULTILIB_DIRNAMES += le

54102

+MULTILIB_OSDIRNAMES += $(subst =,.mlittle=,$(subst lible32,lib32le,$(subst lible64,lib64le,$(subst lib,lible,$(subst -linux,le-linux,$(MULTILIB_OSDIRNAMES))))))

54103

+MULTILIB_OSDIRNAMES += $(subst $(if $(findstring 64,$(target)),m64,m32).,,$(filter $(if $(findstring 64,$(target)),m64,m32).mlittle%,$(MULTILIB_OSDIRNAMES)))

54104

+MULTILIB_MATCHES := ${MULTILIB_MATCHES_ENDIAN}

54105

Index: gcc/config/rs6000/htmintrin.h

54106

===================================================================

54107

--- a/src/gcc/config/rs6000/htmintrin.h (.../tags/gcc_4_8_2_release)

54108

+++ b/src/gcc/config/rs6000/htmintrin.h (.../branches/gcc-4_8-branch)

54109

@@ -0,0 +1,131 @@

54110

+/* Hardware Transactional Memory (HTM) intrinsics.

54111

54112

+ Contributed by Peter Bergner <bergner@vnet.ibm.com>.

54113

+

54114

+ This file is free software; you can redistribute it and/or modify it under

54115

+ the terms of the GNU General Public License as published by the Free

54116

+ Software Foundation; either version 3 of the License, or (at your option)

54117

+ any later version.

54118

+

54119

+ This file is distributed in the hope that it will be useful, but WITHOUT

54120

+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

54121

+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License

54122

+ for more details.

54123

+

54124

+ Under Section 7 of GPL version 3, you are granted additional

54125

+ permissions described in the GCC Runtime Library Exception, version

54126

+ 3.1, as published by the Free Software Foundation.

54127

+

54128

+ You should have received a copy of the GNU General Public License and

54129

+ a copy of the GCC Runtime Library Exception along with this program;

54130

+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see

54131

+ <http://www.gnu.org/licenses/>. */

54132

+

54133

+#ifndef __HTM__

54134

+# error "HTM instruction set not enabled"

54135

+#endif /* __HTM__ */

54136

+

54137

+#ifndef _HTMINTRIN_H

54138

+#define _HTMINTRIN_H

54139

+

54140

+#include <stdint.h>

54141

+

54142

+typedef uint64_t texasr_t;

54143

+typedef uint32_t texasru_t;

54144

+typedef uint32_t texasrl_t;

54145

+typedef uintptr_t tfiar_t;

54146

+typedef uintptr_t tfhar_t;

54147

+

54148

+#define _HTM_STATE(CR0) ((CR0 >> 1) & 0x3)

54149

+#define _HTM_NONTRANSACTIONAL 0x0

54150

+#define _HTM_SUSPENDED 0x1

54151

+#define _HTM_TRANSACTIONAL 0x2

54152

+

54153

+/* The following macros use the IBM bit numbering for BITNUM

54154

+ as used in the ISA documentation. */

54155

+

54156

+#define _TEXASR_EXTRACT_BITS(TEXASR,BITNUM,SIZE) \

54157

+ (((TEXASR) >> (63-(BITNUM))) & ((1<<(SIZE))-1))

54158

+#define _TEXASRU_EXTRACT_BITS(TEXASR,BITNUM,SIZE) \

54159

+ (((TEXASR) >> (31-(BITNUM))) & ((1<<(SIZE))-1))

54160

+

54161

+#define _TEXASR_FAILURE_CODE(TEXASR) \

54162

+ _TEXASR_EXTRACT_BITS(TEXASR, 7, 8)

54163

+#define _TEXASRU_FAILURE_CODE(TEXASRU) \

54164

+ _TEXASRU_EXTRACT_BITS(TEXASRU, 7, 8)

54165

+

54166

+#define _TEXASR_FAILURE_PERSISTENT(TEXASR) \

54167

+ _TEXASR_EXTRACT_BITS(TEXASR, 7, 1)

54168

+#define _TEXASRU_FAILURE_PERSISTENT(TEXASRU) \

54169

+ _TEXASRU_EXTRACT_BITS(TEXASRU, 7, 1)

54170

+

54171

+#define _TEXASR_DISALLOWED(TEXASR) \

54172

+ _TEXASR_EXTRACT_BITS(TEXASR, 8, 1)

54173

+#define _TEXASRU_DISALLOWED(TEXASRU) \

54174

+ _TEXASRU_EXTRACT_BITS(TEXASRU, 8, 1)

54175

+

54176

+#define _TEXASR_NESTING_OVERFLOW(TEXASR) \

54177

+ _TEXASR_EXTRACT_BITS(TEXASR, 9, 1)

54178

+#define _TEXASRU_NESTING_OVERFLOW(TEXASRU) \

54179

+ _TEXASRU_EXTRACT_BITS(TEXASRU, 9, 1)

54180

+

54181

+#define _TEXASR_FOOTPRINT_OVERFLOW(TEXASR) \

54182

+ _TEXASR_EXTRACT_BITS(TEXASR, 10, 1)

54183

+#define _TEXASRU_FOOTPRINT_OVERFLOW(TEXASRU) \

54184

+ _TEXASRU_EXTRACT_BITS(TEXASRU, 10, 1)

54185

+

54186

+#define _TEXASR_SELF_INDUCED_CONFLICT(TEXASR) \

54187

+ _TEXASR_EXTRACT_BITS(TEXASR, 11, 1)

54188

+#define _TEXASRU_SELF_INDUCED_CONFLICT(TEXASRU) \

54189

+ _TEXASRU_EXTRACT_BITS(TEXASRU, 11, 1)

54190

+

54191

+#define _TEXASR_NON_TRANSACTIONAL_CONFLICT(TEXASR) \

54192

+ _TEXASR_EXTRACT_BITS(TEXASR, 12, 1)

54193

+#define _TEXASRU_NON_TRANSACTIONAL_CONFLICT(TEXASRU) \

54194

+ _TEXASRU_EXTRACT_BITS(TEXASRU, 12, 1)

54195

+

54196

+#define _TEXASR_TRANSACTION_CONFLICT(TEXASR) \

54197

+ _TEXASR_EXTRACT_BITS(TEXASR, 13, 1)

54198

+#define _TEXASRU_TRANSACTION_CONFLICT(TEXASRU) \

54199

+ _TEXASRU_EXTRACT_BITS(TEXASRU, 13, 1)

54200

+

54201

+#define _TEXASR_TRANSLATION_INVALIDATION_CONFLICT(TEXASR) \

54202

+ _TEXASR_EXTRACT_BITS(TEXASR, 14, 1)

54203

+#define _TEXASRU_TRANSLATION_INVALIDATION_CONFLICT(TEXASRU) \

54204

+ _TEXASRU_EXTRACT_BITS(TEXASRU, 14, 1)

54205

+

54206

+#define _TEXASR_IMPLEMENTAION_SPECIFIC(TEXASR) \

54207

+ _TEXASR_EXTRACT_BITS(TEXASR, 15, 1)

54208

+#define _TEXASRU_IMPLEMENTAION_SPECIFIC(TEXASRU) \

54209

+ _TEXASRU_EXTRACT_BITS(TEXASRU, 15, 1)

54210

+

54211

+#define _TEXASR_INSTRUCTION_FETCH_CONFLICT(TEXASR) \

54212

+ _TEXASR_EXTRACT_BITS(TEXASR, 16, 1)

54213

+#define _TEXASRU_INSTRUCTION_FETCH_CONFLICT(TEXASRU) \

54214

+ _TEXASRU_EXTRACT_BITS(TEXASRU, 16, 1)

54215

+

54216

+#define _TEXASR_ABORT(TEXASR) \

54217

+ _TEXASR_EXTRACT_BITS(TEXASR, 31, 1)

54218

+#define _TEXASRU_ABORT(TEXASRU) \

54219

+ _TEXASRU_EXTRACT_BITS(TEXASRU, 31, 1)

54220

+

54221

+

54222

+#define _TEXASR_SUSPENDED(TEXASR) \

54223

+ _TEXASR_EXTRACT_BITS(TEXASR, 32, 1)

54224

+

54225

+#define _TEXASR_PRIVILEGE(TEXASR) \

54226

+ _TEXASR_EXTRACT_BITS(TEXASR, 35, 2)

54227

+

54228

+#define _TEXASR_FAILURE_SUMMARY(TEXASR) \

54229

+ _TEXASR_EXTRACT_BITS(TEXASR, 36, 1)

54230

+

54231

+#define _TEXASR_TFIAR_EXACT(TEXASR) \

54232

+ _TEXASR_EXTRACT_BITS(TEXASR, 37, 1)

54233

+

54234

+#define _TEXASR_ROT(TEXASR) \

54235

+ _TEXASR_EXTRACT_BITS(TEXASR, 38, 1)

54236

+

54237

+#define _TEXASR_TRANSACTION_LEVEL(TEXASR) \

54238

+ _TEXASR_EXTRACT_BITS(TEXASR, 63, 12)

54239

+

54240

+#endif /* _HTMINTRIN_H */

54241

Index: gcc/config/rs6000/rs6000-protos.h

54242

===================================================================

54243

--- a/src/gcc/config/rs6000/rs6000-protos.h (.../tags/gcc_4_8_2_release)

54244

+++ b/src/gcc/config/rs6000/rs6000-protos.h (.../branches/gcc-4_8-branch)

54245

@@ -50,12 +50,19 @@

54246

extern rtx find_addr_reg (rtx);

54247

extern rtx gen_easy_altivec_constant (rtx);

54248

extern const char *output_vec_const_move (rtx *);

54249

+extern const char *rs6000_output_move_128bit (rtx *);

54250

+extern bool rs6000_move_128bit_ok_p (rtx []);

54251

+extern bool rs6000_split_128bit_ok_p (rtx []);

54252

extern void rs6000_expand_vector_init (rtx, rtx);

54253

extern void paired_expand_vector_init (rtx, rtx);

54254

extern void rs6000_expand_vector_set (rtx, rtx, int);

54255

extern void rs6000_expand_vector_extract (rtx, rtx, int);

54256

extern bool altivec_expand_vec_perm_const (rtx op[4]);

54257

+extern void altivec_expand_vec_perm_le (rtx op[4]);

54258

extern bool rs6000_expand_vec_perm_const (rtx op[4]);

54259

+extern void altivec_expand_lvx_be (rtx, rtx, enum machine_mode, unsigned);

54260

+extern void altivec_expand_stvx_be (rtx, rtx, enum machine_mode, unsigned);

54261

+extern void altivec_expand_stvex_be (rtx, rtx, enum machine_mode, unsigned);

54262

extern void rs6000_expand_extract_even (rtx, rtx, rtx);

54263

extern void rs6000_expand_interleave (rtx, rtx, rtx, bool);

54264

extern void build_mask64_2_operands (rtx, rtx *);

54265

@@ -70,6 +77,11 @@

54266

extern int registers_ok_for_quad_peep (rtx, rtx);

54267

extern int mems_ok_for_quad_peep (rtx, rtx);

54268

extern bool gpr_or_gpr_p (rtx, rtx);

54269

+extern bool direct_move_p (rtx, rtx);

54270

+extern bool quad_load_store_p (rtx, rtx);

54271

+extern bool fusion_gpr_load_p (rtx *, bool);

54272

+extern void expand_fusion_gpr_load (rtx *);

54273

+extern const char *emit_fusion_gpr_load (rtx *);

54274

extern enum reg_class (*rs6000_preferred_reload_class_ptr) (rtx,

54275

enum reg_class);

54276

extern enum reg_class (*rs6000_secondary_reload_class_ptr) (enum reg_class,

54277

@@ -116,6 +128,7 @@

54278

extern void rs6000_fatal_bad_address (rtx);

54279

extern rtx create_TOC_reference (rtx, rtx);

54280

extern void rs6000_split_multireg_move (rtx, rtx);

54281

+extern void rs6000_emit_le_vsx_move (rtx, rtx, enum machine_mode);

54282

extern void rs6000_emit_move (rtx, rtx, enum machine_mode);

54283

extern rtx rs6000_secondary_memory_needed_rtx (enum machine_mode);

54284

extern rtx (*rs6000_legitimize_reload_address_ptr) (rtx, enum machine_mode,

54285

@@ -135,9 +148,11 @@

54286

extern rtx rs6000_address_for_altivec (rtx);

54287

extern rtx rs6000_allocate_stack_temp (enum machine_mode, bool, bool);

54288

extern int rs6000_loop_align (rtx);

54289

+extern void rs6000_split_logical (rtx [], enum rtx_code, bool, bool, bool, rtx);

54290

#endif /* RTX_CODE */

54291

54292

#ifdef TREE_CODE

54293

+extern unsigned int rs6000_data_alignment (tree, unsigned int, enum data_align);

54294

extern unsigned int rs6000_special_round_type_align (tree, unsigned int,

54295

unsigned int);

54296

extern unsigned int darwin_rs6000_special_round_type_align (tree, unsigned int,

54297

@@ -146,6 +161,7 @@

54298

extern rtx rs6000_libcall_value (enum machine_mode);

54299

extern rtx rs6000_va_arg (tree, tree);

54300

extern int function_ok_for_sibcall (tree);

54301

+extern int rs6000_reg_parm_stack_space (tree);

54302

extern void rs6000_elf_declare_function_name (FILE *, const char *, tree);

54303

extern bool rs6000_elf_in_small_data_p (const_tree);

54304

#ifdef ARGS_SIZE_RTX

54305

@@ -170,7 +186,8 @@

54306

extern void rs6000_emit_epilogue (int);

54307

extern void rs6000_emit_eh_reg_restore (rtx, rtx);

54308

extern const char * output_isel (rtx *);

54309

-extern void rs6000_call_indirect_aix (rtx, rtx, rtx);

54310

+extern void rs6000_call_aix (rtx, rtx, rtx, rtx);

54311

+extern void rs6000_sibcall_aix (rtx, rtx, rtx, rtx);

54312

extern void rs6000_aix_asm_output_dwarf_table_ref (char *);

54313

extern void get_ppc476_thunk_name (char name[32]);

54314

extern bool rs6000_overloaded_builtin_p (enum rs6000_builtins);

54315

Index: gcc/config/rs6000/t-rs6000

54316

===================================================================

54317

--- a/src/gcc/config/rs6000/t-rs6000 (.../tags/gcc_4_8_2_release)

54318

+++ b/src/gcc/config/rs6000/t-rs6000 (.../branches/gcc-4_8-branch)

54319

@@ -60,6 +60,7 @@

54320

$(srcdir)/config/rs6000/power5.md \

54321

$(srcdir)/config/rs6000/power6.md \

54322

$(srcdir)/config/rs6000/power7.md \

54323

+ $(srcdir)/config/rs6000/power8.md \

54324

$(srcdir)/config/rs6000/cell.md \

54325

$(srcdir)/config/rs6000/xfpu.md \

54326

$(srcdir)/config/rs6000/a2.md \

54327

@@ -70,6 +71,8 @@

54328

$(srcdir)/config/rs6000/vector.md \

54329

$(srcdir)/config/rs6000/vsx.md \

54330

$(srcdir)/config/rs6000/altivec.md \

54331

+ $(srcdir)/config/rs6000/crypto.md \

54332

+ $(srcdir)/config/rs6000/htm.md \

54333

$(srcdir)/config/rs6000/spe.md \

54334

$(srcdir)/config/rs6000/dfp.md \

54335

$(srcdir)/config/rs6000/paired.md

54336

Index: gcc/config/rs6000/htmxlintrin.h

54337

===================================================================

54338

--- a/src/gcc/config/rs6000/htmxlintrin.h (.../tags/gcc_4_8_2_release)

54339

+++ b/src/gcc/config/rs6000/htmxlintrin.h (.../branches/gcc-4_8-branch)

54340

@@ -0,0 +1,208 @@

54341

+/* XL compiler Hardware Transactional Memory (HTM) execution intrinsics.

54342

54343

+ Contributed by Peter Bergner <bergner@vnet.ibm.com>.

54344

+

54345

+ This file is free software; you can redistribute it and/or modify it under

54346

+ the terms of the GNU General Public License as published by the Free

54347

+ Software Foundation; either version 3 of the License, or (at your option)

54348

+ any later version.

54349

+

54350

+ This file is distributed in the hope that it will be useful, but WITHOUT

54351

+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

54352

+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License

54353

+ for more details.

54354

+

54355

+ Under Section 7 of GPL version 3, you are granted additional

54356

+ permissions described in the GCC Runtime Library Exception, version

54357

+ 3.1, as published by the Free Software Foundation.

54358

+

54359

+ You should have received a copy of the GNU General Public License and

54360

+ a copy of the GCC Runtime Library Exception along with this program;

54361

+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see

54362

+ <http://www.gnu.org/licenses/>. */

54363

+

54364

+#ifndef __HTM__

54365

+# error "HTM instruction set not enabled"

54366

+#endif /* __HTM__ */

54367

+

54368

+#ifndef _HTMXLINTRIN_H

54369

+#define _HTMXLINTRIN_H

54370

+

54371

+#include <stdint.h>

54372

+#include <htmintrin.h>

54373

+

54374

+#ifdef __cplusplus

54375

+extern "C" {

54376

+#endif

54377

+

54378

+#define _TEXASR_PTR(TM_BUF) \

54379

+ ((texasr_t *)((TM_BUF)+0))

54380

+#define _TEXASRU_PTR(TM_BUF) \

54381

+ ((texasru_t *)((TM_BUF)+0))

54382

+#define _TEXASRL_PTR(TM_BUF) \

54383

+ ((texasrl_t *)((TM_BUF)+4))

54384

+#define _TFIAR_PTR(TM_BUF) \

54385

+ ((tfiar_t *)((TM_BUF)+8))

54386

+

54387

+typedef char TM_buff_type[16];

54388

+

54389

+extern __inline long

54390

+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))

54391

+__TM_simple_begin (void)

54392

+{

54393

+ if (__builtin_expect (__builtin_tbegin (0), 1))

54394

+ return 1;

54395

+ return 0;

54396

+}

54397

+

54398

+extern __inline long

54399

+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))

54400

+__TM_begin (void* const TM_buff)

54401

+{

54402

+ *_TEXASRL_PTR (TM_buff) = 0;

54403

+ if (__builtin_expect (__builtin_tbegin (0), 1))

54404

+ return 1;

54405

+#ifdef __powerpc64__

54406

+ *_TEXASR_PTR (TM_buff) = __builtin_get_texasr ();

54407

+#else

54408

+ *_TEXASRU_PTR (TM_buff) = __builtin_get_texasru ();

54409

+ *_TEXASRL_PTR (TM_buff) = __builtin_get_texasr ();

54410

+#endif

54411

+ *_TFIAR_PTR (TM_buff) = __builtin_get_tfiar ();

54412

+ return 0;

54413

+}

54414

+

54415

+extern __inline long

54416

+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))

54417

+__TM_end (void)

54418

+{

54419

+ if (__builtin_expect (__builtin_tend (0), 1))

54420

+ return 1;

54421

+ return 0;

54422

+}

54423

+

54424

+extern __inline void

54425

+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))

54426

+__TM_abort (void)

54427

+{

54428

+ __builtin_tabort (0);

54429

+}

54430

+

54431

+extern __inline void

54432

+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))

54433

+__TM_named_abort (unsigned char const code)

54434

+{

54435

+ __builtin_tabort (code);

54436

+}

54437

+

54438

+extern __inline void

54439

+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))

54440

+__TM_resume (void)

54441

+{

54442

+ __builtin_tresume ();

54443

+}

54444

+

54445

+extern __inline void

54446

+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))

54447

+__TM_suspend (void)

54448

+{

54449

+ __builtin_tsuspend ();

54450

+}

54451

+

54452

+extern __inline long

54453

+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))

54454

+__TM_is_user_abort (void* const TM_buff)

54455

+{

54456

+ texasru_t texasru = *_TEXASRU_PTR (TM_buff);

54457

+ return _TEXASRU_ABORT (texasru);

54458

+}

54459

+

54460

+extern __inline long

54461

+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))

54462

+__TM_is_named_user_abort (void* const TM_buff, unsigned char *code)

54463

+{

54464

+ texasru_t texasru = *_TEXASRU_PTR (TM_buff);

54465

+

54466

+ *code = _TEXASRU_FAILURE_CODE (texasru);

54467

+ return _TEXASRU_ABORT (texasru);

54468

+}

54469

+

54470

+extern __inline long

54471

+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))

54472

+__TM_is_illegal (void* const TM_buff)

54473

+{

54474

+ texasru_t texasru = *_TEXASRU_PTR (TM_buff);

54475

+ return _TEXASRU_DISALLOWED (texasru);

54476

+}

54477

+

54478

+extern __inline long

54479

+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))

54480

+__TM_is_footprint_exceeded (void* const TM_buff)

54481

+{

54482

+ texasru_t texasru = *_TEXASRU_PTR (TM_buff);

54483

+ return _TEXASRU_FOOTPRINT_OVERFLOW (texasru);

54484

+}

54485

+

54486

+extern __inline long

54487

+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))

54488

+__TM_nesting_depth (void* const TM_buff)

54489

+{

54490

+ texasrl_t texasrl;

54491

+

54492

+ if (_HTM_STATE (__builtin_ttest ()) == _HTM_NONTRANSACTIONAL)

54493

+ {

54494

+ texasrl = *_TEXASRL_PTR (TM_buff);

54495

+ if (!_TEXASR_FAILURE_SUMMARY (texasrl))

54496

+ texasrl = 0;

54497

+ }

54498

+ else

54499

+ texasrl = (texasrl_t) __builtin_get_texasr ();

54500

+

54501

+ return _TEXASR_TRANSACTION_LEVEL (texasrl);

54502

+}

54503

+

54504

+extern __inline long

54505

+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))

54506

+__TM_is_nested_too_deep(void* const TM_buff)

54507

+{

54508

+ texasru_t texasru = *_TEXASRU_PTR (TM_buff);

54509

+ return _TEXASRU_NESTING_OVERFLOW (texasru);

54510

+}

54511

+

54512

+extern __inline long

54513

+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))

54514

+__TM_is_conflict(void* const TM_buff)

54515

+{

54516

+ texasru_t texasru = *_TEXASRU_PTR (TM_buff);

54517

+ /* Return TEXASR bits 11 (Self-Induced Conflict) through

54518

+ 14 (Translation Invalidation Conflict). */

54519

+ return (_TEXASRU_EXTRACT_BITS (texasru, 14, 4)) ? 1 : 0;

54520

+}

54521

+

54522

+extern __inline long

54523

+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))

54524

+__TM_is_failure_persistent(void* const TM_buff)

54525

+{

54526

+ texasru_t texasru = *_TEXASRU_PTR (TM_buff);

54527

+ return _TEXASRU_FAILURE_PERSISTENT (texasru);

54528

+}

54529

+

54530

+extern __inline long

54531

+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))

54532

+__TM_failure_address(void* const TM_buff)

54533

+{

54534

+ return *_TFIAR_PTR (TM_buff);

54535

+}

54536

+

54537

+extern __inline long long

54538

+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))

54539

+__TM_failure_code(void* const TM_buff)

54540

+{

54541

+ return *_TEXASR_PTR (TM_buff);

54542

+}

54543

+

54544

+#ifdef __cplusplus

54545

+}

54546

+#endif

54547

+

54548

+#endif /* _HTMXLINTRIN_H */

54549

Index: gcc/config/rs6000/rs6000-builtin.def

54550

===================================================================

54551

--- a/src/gcc/config/rs6000/rs6000-builtin.def (.../tags/gcc_4_8_2_release)

54552

+++ b/src/gcc/config/rs6000/rs6000-builtin.def (.../branches/gcc-4_8-branch)

54553

@@ -30,7 +30,8 @@

54554

RS6000_BUILTIN_A -- ABS builtins

54555

RS6000_BUILTIN_D -- DST builtins

54556

RS6000_BUILTIN_E -- SPE EVSEL builtins.

54557

- RS6000_BUILTIN_P -- Altivec and VSX predicate builtins

54558

+ RS6000_BUILTIN_H -- HTM builtins

54559

+ RS6000_BUILTIN_P -- Altivec, VSX, ISA 2.07 vector predicate builtins

54560

RS6000_BUILTIN_Q -- Paired floating point VSX predicate builtins

54561

RS6000_BUILTIN_S -- SPE predicate builtins

54562

RS6000_BUILTIN_X -- special builtins

54563

@@ -66,6 +67,10 @@

54564

#error "RS6000_BUILTIN_E is not defined."

54565

#endif

54566

54567

+#ifndef RS6000_BUILTIN_H

54568

+ #error "RS6000_BUILTIN_H is not defined."

54569

+#endif

54570

+

54571

#ifndef RS6000_BUILTIN_P

54572

#error "RS6000_BUILTIN_P is not defined."

54573

#endif

54574

@@ -301,6 +306,174 @@

54575

| RS6000_BTC_SPECIAL), \

54576

CODE_FOR_nothing) /* ICODE */

54577

54578

+/* ISA 2.07 (power8) vector convenience macros. */

54579

+/* For the instructions that are encoded as altivec instructions use

54580

+ __builtin_altivec_ as the builtin name. */

54581

+#define BU_P8V_AV_1(ENUM, NAME, ATTR, ICODE) \

54582

+ RS6000_BUILTIN_1 (P8V_BUILTIN_ ## ENUM, /* ENUM */ \

54583

+ "__builtin_altivec_" NAME, /* NAME */ \

54584

+ RS6000_BTM_P8_VECTOR, /* MASK */ \

54585

+ (RS6000_BTC_ ## ATTR /* ATTR */ \

54586

+ | RS6000_BTC_UNARY), \

54587

+ CODE_FOR_ ## ICODE) /* ICODE */

54588

+

54589

+#define BU_P8V_AV_2(ENUM, NAME, ATTR, ICODE) \

54590

+ RS6000_BUILTIN_2 (P8V_BUILTIN_ ## ENUM, /* ENUM */ \

54591

+ "__builtin_altivec_" NAME, /* NAME */ \

54592

+ RS6000_BTM_P8_VECTOR, /* MASK */ \

54593

+ (RS6000_BTC_ ## ATTR /* ATTR */ \

54594

+ | RS6000_BTC_BINARY), \

54595

+ CODE_FOR_ ## ICODE) /* ICODE */

54596

+

54597

+#define BU_P8V_AV_3(ENUM, NAME, ATTR, ICODE) \

54598

+ RS6000_BUILTIN_3 (P8V_BUILTIN_ ## ENUM, /* ENUM */ \

54599

+ "__builtin_altivec_" NAME, /* NAME */ \

54600

+ RS6000_BTM_P8_VECTOR, /* MASK */ \

54601

+ (RS6000_BTC_ ## ATTR /* ATTR */ \

54602

+ | RS6000_BTC_TERNARY), \

54603

+ CODE_FOR_ ## ICODE) /* ICODE */

54604

+

54605

+#define BU_P8V_AV_P(ENUM, NAME, ATTR, ICODE) \

54606

+ RS6000_BUILTIN_P (P8V_BUILTIN_ ## ENUM, /* ENUM */ \

54607

+ "__builtin_altivec_" NAME, /* NAME */ \

54608

+ RS6000_BTM_P8_VECTOR, /* MASK */ \

54609

+ (RS6000_BTC_ ## ATTR /* ATTR */ \

54610

+ | RS6000_BTC_PREDICATE), \

54611

+ CODE_FOR_ ## ICODE) /* ICODE */

54612

+

54613

+/* For the instructions encoded as VSX instructions use __builtin_vsx as the

54614

+ builtin name. */

54615

+#define BU_P8V_VSX_1(ENUM, NAME, ATTR, ICODE) \

54616

+ RS6000_BUILTIN_1 (P8V_BUILTIN_ ## ENUM, /* ENUM */ \

54617

+ "__builtin_vsx_" NAME, /* NAME */ \

54618

+ RS6000_BTM_P8_VECTOR, /* MASK */ \

54619

+ (RS6000_BTC_ ## ATTR /* ATTR */ \

54620

+ | RS6000_BTC_UNARY), \

54621

+ CODE_FOR_ ## ICODE) /* ICODE */

54622

+

54623

+#define BU_P8V_OVERLOAD_1(ENUM, NAME) \

54624

+ RS6000_BUILTIN_1 (P8V_BUILTIN_VEC_ ## ENUM, /* ENUM */ \

54625

+ "__builtin_vec_" NAME, /* NAME */ \

54626

+ RS6000_BTM_P8_VECTOR, /* MASK */ \

54627

+ (RS6000_BTC_OVERLOADED /* ATTR */ \

54628

+ | RS6000_BTC_UNARY), \

54629

+ CODE_FOR_nothing) /* ICODE */

54630

+

54631

+#define BU_P8V_OVERLOAD_2(ENUM, NAME) \

54632

+ RS6000_BUILTIN_2 (P8V_BUILTIN_VEC_ ## ENUM, /* ENUM */ \

54633

+ "__builtin_vec_" NAME, /* NAME */ \

54634

+ RS6000_BTM_P8_VECTOR, /* MASK */ \

54635

+ (RS6000_BTC_OVERLOADED /* ATTR */ \

54636

+ | RS6000_BTC_BINARY), \

54637

+ CODE_FOR_nothing) /* ICODE */

54638

+

54639

+#define BU_P8V_OVERLOAD_3(ENUM, NAME) \

54640

+ RS6000_BUILTIN_3 (P8V_BUILTIN_VEC_ ## ENUM, /* ENUM */ \

54641

+ "__builtin_vec_" NAME, /* NAME */ \

54642

+ RS6000_BTM_P8_VECTOR, /* MASK */ \

54643

+ (RS6000_BTC_OVERLOADED /* ATTR */ \

54644

+ | RS6000_BTC_TERNARY), \

54645

+ CODE_FOR_nothing) /* ICODE */

54646

+

54647

+/* Crypto convenience macros. */

54648

+#define BU_CRYPTO_1(ENUM, NAME, ATTR, ICODE) \

54649

+ RS6000_BUILTIN_1 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \

54650

+ "__builtin_crypto_" NAME, /* NAME */ \

54651

+ RS6000_BTM_CRYPTO, /* MASK */ \

54652

+ (RS6000_BTC_ ## ATTR /* ATTR */ \

54653

+ | RS6000_BTC_UNARY), \

54654

+ CODE_FOR_ ## ICODE) /* ICODE */

54655

+

54656

+#define BU_CRYPTO_2(ENUM, NAME, ATTR, ICODE) \

54657

+ RS6000_BUILTIN_2 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \

54658

+ "__builtin_crypto_" NAME, /* NAME */ \

54659

+ RS6000_BTM_CRYPTO, /* MASK */ \

54660

+ (RS6000_BTC_ ## ATTR /* ATTR */ \

54661

+ | RS6000_BTC_BINARY), \

54662

+ CODE_FOR_ ## ICODE) /* ICODE */

54663

+

54664

+#define BU_CRYPTO_3(ENUM, NAME, ATTR, ICODE) \

54665

+ RS6000_BUILTIN_3 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \

54666

+ "__builtin_crypto_" NAME, /* NAME */ \

54667

+ RS6000_BTM_CRYPTO, /* MASK */ \

54668

+ (RS6000_BTC_ ## ATTR /* ATTR */ \

54669

+ | RS6000_BTC_TERNARY), \

54670

+ CODE_FOR_ ## ICODE) /* ICODE */

54671

+

54672

+#define BU_CRYPTO_OVERLOAD_1(ENUM, NAME) \

54673

+ RS6000_BUILTIN_1 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \

54674

+ "__builtin_crypto_" NAME, /* NAME */ \

54675

+ RS6000_BTM_CRYPTO, /* MASK */ \

54676

+ (RS6000_BTC_OVERLOADED /* ATTR */ \

54677

+ | RS6000_BTC_UNARY), \

54678

+ CODE_FOR_nothing) /* ICODE */

54679

+

54680

+#define BU_CRYPTO_OVERLOAD_2(ENUM, NAME) \

54681

+ RS6000_BUILTIN_2 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \

54682

+ "__builtin_crypto_" NAME, /* NAME */ \

54683

+ RS6000_BTM_CRYPTO, /* MASK */ \

54684

+ (RS6000_BTC_OVERLOADED /* ATTR */ \

54685

+ | RS6000_BTC_BINARY), \

54686

+ CODE_FOR_nothing) /* ICODE */

54687

+

54688

+#define BU_CRYPTO_OVERLOAD_3(ENUM, NAME) \

54689

+ RS6000_BUILTIN_3 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \

54690

+ "__builtin_crypto_" NAME, /* NAME */ \

54691

+ RS6000_BTM_CRYPTO, /* MASK */ \

54692

+ (RS6000_BTC_OVERLOADED /* ATTR */ \

54693

+ | RS6000_BTC_TERNARY), \

54694

+ CODE_FOR_nothing) /* ICODE */

54695

+

54696

+/* HTM convenience macros. */

54697

+#define BU_HTM_0(ENUM, NAME, ATTR, ICODE) \

54698

+ RS6000_BUILTIN_H (HTM_BUILTIN_ ## ENUM, /* ENUM */ \

54699

+ "__builtin_" NAME, /* NAME */ \

54700

+ RS6000_BTM_HTM, /* MASK */ \

54701

+ RS6000_BTC_ ## ATTR, /* ATTR */ \

54702

+ CODE_FOR_ ## ICODE) /* ICODE */

54703

+

54704

+#define BU_HTM_1(ENUM, NAME, ATTR, ICODE) \

54705

+ RS6000_BUILTIN_H (HTM_BUILTIN_ ## ENUM, /* ENUM */ \

54706

+ "__builtin_" NAME, /* NAME */ \

54707

+ RS6000_BTM_HTM, /* MASK */ \

54708

+ (RS6000_BTC_ ## ATTR /* ATTR */ \

54709

+ | RS6000_BTC_UNARY), \

54710

+ CODE_FOR_ ## ICODE) /* ICODE */

54711

+

54712

+#define BU_HTM_2(ENUM, NAME, ATTR, ICODE) \

54713

+ RS6000_BUILTIN_H (HTM_BUILTIN_ ## ENUM, /* ENUM */ \

54714

+ "__builtin_" NAME, /* NAME */ \

54715

+ RS6000_BTM_HTM, /* MASK */ \

54716

+ (RS6000_BTC_ ## ATTR /* ATTR */ \

54717

+ | RS6000_BTC_BINARY), \

54718

+ CODE_FOR_ ## ICODE) /* ICODE */

54719

+

54720

+#define BU_HTM_3(ENUM, NAME, ATTR, ICODE) \

54721

+ RS6000_BUILTIN_H (HTM_BUILTIN_ ## ENUM, /* ENUM */ \

54722

+ "__builtin_" NAME, /* NAME */ \

54723

+ RS6000_BTM_HTM, /* MASK */ \

54724

+ (RS6000_BTC_ ## ATTR /* ATTR */ \

54725

+ | RS6000_BTC_TERNARY), \

54726

+ CODE_FOR_ ## ICODE) /* ICODE */

54727

+

54728

+#define BU_HTM_SPR0(ENUM, NAME, ATTR, ICODE) \

54729

+ RS6000_BUILTIN_H (HTM_BUILTIN_ ## ENUM, /* ENUM */ \

54730

+ "__builtin_" NAME, /* NAME */ \

54731

+ RS6000_BTM_HTM, /* MASK */ \

54732

+ (RS6000_BTC_ ## ATTR /* ATTR */ \

54733

+ | RS6000_BTC_SPR), \

54734

+ CODE_FOR_ ## ICODE) /* ICODE */

54735

+

54736

+#define BU_HTM_SPR1(ENUM, NAME, ATTR, ICODE) \

54737

+ RS6000_BUILTIN_H (HTM_BUILTIN_ ## ENUM, /* ENUM */ \

54738

+ "__builtin_" NAME, /* NAME */ \

54739

+ RS6000_BTM_HTM, /* MASK */ \

54740

+ (RS6000_BTC_ ## ATTR /* ATTR */ \

54741

+ | RS6000_BTC_UNARY \

54742

+ | RS6000_BTC_SPR \

54743

+ | RS6000_BTC_VOID), \

54744

+ CODE_FOR_ ## ICODE) /* ICODE */

54745

+

54746

/* SPE convenience macros. */

54747

#define BU_SPE_1(ENUM, NAME, ATTR, ICODE) \

54748

RS6000_BUILTIN_1 (SPE_BUILTIN_ ## ENUM, /* ENUM */ \

54749

@@ -397,6 +570,75 @@

54750

MASK, /* MASK */ \

54751

(ATTR | RS6000_BTC_SPECIAL), /* ATTR */ \

54752

CODE_FOR_nothing) /* ICODE */

54753

+

54754

+

54755

+/* Decimal floating point builtins for instructions. */

54756

+#define BU_DFP_MISC_1(ENUM, NAME, ATTR, ICODE) \

54757

+ RS6000_BUILTIN_1 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \

54758

+ "__builtin_" NAME, /* NAME */ \

54759

+ RS6000_BTM_DFP, /* MASK */ \

54760

+ (RS6000_BTC_ ## ATTR /* ATTR */ \

54761

+ | RS6000_BTC_UNARY), \

54762

+ CODE_FOR_ ## ICODE) /* ICODE */

54763

+

54764

+#define BU_DFP_MISC_2(ENUM, NAME, ATTR, ICODE) \

54765

+ RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \

54766

+ "__builtin_" NAME, /* NAME */ \

54767

+ RS6000_BTM_DFP, /* MASK */ \

54768

+ (RS6000_BTC_ ## ATTR /* ATTR */ \

54769

+ | RS6000_BTC_BINARY), \

54770

+ CODE_FOR_ ## ICODE) /* ICODE */

54771

+

54772

+

54773

+/* Miscellaneous builtins for instructions added in ISA 2.06. These

54774

+ instructions don't require either the DFP or VSX options, just the basic ISA

54775

+ 2.06 (popcntd) enablement since they operate on general purpose

54776

+ registers. */

54777

+#define BU_P7_MISC_1(ENUM, NAME, ATTR, ICODE) \

54778

+ RS6000_BUILTIN_1 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \

54779

+ "__builtin_" NAME, /* NAME */ \

54780

+ RS6000_BTM_POPCNTD, /* MASK */ \

54781

+ (RS6000_BTC_ ## ATTR /* ATTR */ \

54782

+ | RS6000_BTC_UNARY), \

54783

+ CODE_FOR_ ## ICODE) /* ICODE */

54784

+

54785

+#define BU_P7_MISC_2(ENUM, NAME, ATTR, ICODE) \

54786

+ RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \

54787

+ "__builtin_" NAME, /* NAME */ \

54788

+ RS6000_BTM_POPCNTD, /* MASK */ \

54789

+ (RS6000_BTC_ ## ATTR /* ATTR */ \

54790

+ | RS6000_BTC_BINARY), \

54791

+ CODE_FOR_ ## ICODE) /* ICODE */

54792

+

54793

+

54794

+/* Miscellaneous builtins for instructions added in ISA 2.07. These

54795

+ instructions do require the ISA 2.07 vector support, but they aren't vector

54796

+ instructions. */

54797

+#define BU_P8V_MISC_3(ENUM, NAME, ATTR, ICODE) \

54798

+ RS6000_BUILTIN_3 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \

54799

+ "__builtin_" NAME, /* NAME */ \

54800

+ RS6000_BTM_P8_VECTOR, /* MASK */ \

54801

+ (RS6000_BTC_ ## ATTR /* ATTR */ \

54802

+ | RS6000_BTC_TERNARY), \

54803

+ CODE_FOR_ ## ICODE) /* ICODE */

54804

+

54805

+/* Miscellaneous builtins. */

54806

+#define BU_MISC_1(ENUM, NAME, ATTR, ICODE) \

54807

+ RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \

54808

+ "__builtin_" NAME, /* NAME */ \

54809

+ RS6000_BTM_HARD_FLOAT, /* MASK */ \

54810

+ (RS6000_BTC_ ## ATTR /* ATTR */ \

54811

+ | RS6000_BTC_UNARY), \

54812

+ CODE_FOR_ ## ICODE) /* ICODE */

54813

+

54814

+#define BU_MISC_2(ENUM, NAME, ATTR, ICODE) \

54815

+ RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \

54816

+ "__builtin_" NAME, /* NAME */ \

54817

+ RS6000_BTM_HARD_FLOAT, /* MASK */ \

54818

+ (RS6000_BTC_ ## ATTR /* ATTR */ \

54819

+ | RS6000_BTC_BINARY), \

54820

+ CODE_FOR_ ## ICODE) /* ICODE */

54821

+

54822

#endif

54823

54824

/* Insure 0 is not a legitimate index. */

54825

@@ -414,6 +656,7 @@

54826

BU_ALTIVEC_3 (VMSUMUHS, "vmsumuhs", SAT, altivec_vmsumuhs)

54827

BU_ALTIVEC_3 (VMSUMSHS, "vmsumshs", SAT, altivec_vmsumshs)

54828

BU_ALTIVEC_3 (VNMSUBFP, "vnmsubfp", FP, nfmsv4sf4)

54829

+BU_ALTIVEC_3 (VPERM_1TI, "vperm_1ti", CONST, altivec_vperm_v1ti)

54830

BU_ALTIVEC_3 (VPERM_2DF, "vperm_2df", CONST, altivec_vperm_v2df)

54831

BU_ALTIVEC_3 (VPERM_2DI, "vperm_2di", CONST, altivec_vperm_v2di)

54832

BU_ALTIVEC_3 (VPERM_4SF, "vperm_4sf", CONST, altivec_vperm_v4sf)

54833

@@ -420,6 +663,7 @@

54834

BU_ALTIVEC_3 (VPERM_4SI, "vperm_4si", CONST, altivec_vperm_v4si)

54835

BU_ALTIVEC_3 (VPERM_8HI, "vperm_8hi", CONST, altivec_vperm_v8hi)

54836

BU_ALTIVEC_3 (VPERM_16QI, "vperm_16qi", CONST, altivec_vperm_v16qi_uns)

54837

+BU_ALTIVEC_3 (VPERM_1TI_UNS, "vperm_1ti_uns", CONST, altivec_vperm_v1ti_uns)

54838

BU_ALTIVEC_3 (VPERM_2DI_UNS, "vperm_2di_uns", CONST, altivec_vperm_v2di_uns)

54839

BU_ALTIVEC_3 (VPERM_4SI_UNS, "vperm_4si_uns", CONST, altivec_vperm_v4si_uns)

54840

BU_ALTIVEC_3 (VPERM_8HI_UNS, "vperm_8hi_uns", CONST, altivec_vperm_v8hi_uns)

54841

@@ -430,10 +674,12 @@

54842

BU_ALTIVEC_3 (VSEL_16QI, "vsel_16qi", CONST, vector_select_v16qi)

54843

BU_ALTIVEC_3 (VSEL_2DF, "vsel_2df", CONST, vector_select_v2df)

54844

BU_ALTIVEC_3 (VSEL_2DI, "vsel_2di", CONST, vector_select_v2di)

54845

+BU_ALTIVEC_3 (VSEL_1TI, "vsel_1ti", CONST, vector_select_v1ti)

54846

BU_ALTIVEC_3 (VSEL_4SI_UNS, "vsel_4si_uns", CONST, vector_select_v4si_uns)

54847

BU_ALTIVEC_3 (VSEL_8HI_UNS, "vsel_8hi_uns", CONST, vector_select_v8hi_uns)

54848

BU_ALTIVEC_3 (VSEL_16QI_UNS, "vsel_16qi_uns", CONST, vector_select_v16qi_uns)

54849

BU_ALTIVEC_3 (VSEL_2DI_UNS, "vsel_2di_uns", CONST, vector_select_v2di_uns)

54850

+BU_ALTIVEC_3 (VSEL_1TI_UNS, "vsel_1ti_uns", CONST, vector_select_v1ti_uns)

54851

BU_ALTIVEC_3 (VSLDOI_16QI, "vsldoi_16qi", CONST, altivec_vsldoi_v16qi)

54852

BU_ALTIVEC_3 (VSLDOI_8HI, "vsldoi_8hi", CONST, altivec_vsldoi_v8hi)

54853

BU_ALTIVEC_3 (VSLDOI_4SI, "vsldoi_4si", CONST, altivec_vsldoi_v4si)

54854

@@ -626,6 +872,8 @@

54855

BU_ALTIVEC_X (LD_INTERNAL_2df, "ld_internal_2df", MEM)

54856

BU_ALTIVEC_X (ST_INTERNAL_2di, "st_internal_2di", MEM)

54857

BU_ALTIVEC_X (LD_INTERNAL_2di, "ld_internal_2di", MEM)

54858

+BU_ALTIVEC_X (ST_INTERNAL_1ti, "st_internal_1ti", MEM)

54859

+BU_ALTIVEC_X (LD_INTERNAL_1ti, "ld_internal_1ti", MEM)

54860

BU_ALTIVEC_X (MTVSCR, "mtvscr", MISC)

54861

BU_ALTIVEC_X (MFVSCR, "mfvscr", MISC)

54862

BU_ALTIVEC_X (DSSALL, "dssall", MISC)

54863

@@ -636,8 +884,26 @@

54864

BU_ALTIVEC_X (LVEHX, "lvehx", MEM)

54865

BU_ALTIVEC_X (LVEWX, "lvewx", MEM)

54866

BU_ALTIVEC_X (LVXL, "lvxl", MEM)

54867

+BU_ALTIVEC_X (LVXL_V2DF, "lvxl_v2df", MEM)

54868

+BU_ALTIVEC_X (LVXL_V2DI, "lvxl_v2di", MEM)

54869

+BU_ALTIVEC_X (LVXL_V4SF, "lvxl_v4sf", MEM)

54870

+BU_ALTIVEC_X (LVXL_V4SI, "lvxl_v4si", MEM)

54871

+BU_ALTIVEC_X (LVXL_V8HI, "lvxl_v8hi", MEM)

54872

+BU_ALTIVEC_X (LVXL_V16QI, "lvxl_v16qi", MEM)

54873

BU_ALTIVEC_X (LVX, "lvx", MEM)

54874

+BU_ALTIVEC_X (LVX_V2DF, "lvx_v2df", MEM)

54875

+BU_ALTIVEC_X (LVX_V2DI, "lvx_v2di", MEM)

54876

+BU_ALTIVEC_X (LVX_V4SF, "lvx_v4sf", MEM)

54877

+BU_ALTIVEC_X (LVX_V4SI, "lvx_v4si", MEM)

54878

+BU_ALTIVEC_X (LVX_V8HI, "lvx_v8hi", MEM)

54879

+BU_ALTIVEC_X (LVX_V16QI, "lvx_v16qi", MEM)

54880

BU_ALTIVEC_X (STVX, "stvx", MEM)

54881

+BU_ALTIVEC_X (STVX_V2DF, "stvx_v2df", MEM)

54882

+BU_ALTIVEC_X (STVX_V2DI, "stvx_v2di", MEM)

54883

+BU_ALTIVEC_X (STVX_V4SF, "stvx_v4sf", MEM)

54884

+BU_ALTIVEC_X (STVX_V4SI, "stvx_v4si", MEM)

54885

+BU_ALTIVEC_X (STVX_V8HI, "stvx_v8hi", MEM)

54886

+BU_ALTIVEC_X (STVX_V16QI, "stvx_v16qi", MEM)

54887

BU_ALTIVEC_C (LVLX, "lvlx", MEM)

54888

BU_ALTIVEC_C (LVLXL, "lvlxl", MEM)

54889

BU_ALTIVEC_C (LVRX, "lvrx", MEM)

54890

@@ -646,6 +912,12 @@

54891

BU_ALTIVEC_X (STVEHX, "stvehx", MEM)

54892

BU_ALTIVEC_X (STVEWX, "stvewx", MEM)

54893

BU_ALTIVEC_X (STVXL, "stvxl", MEM)

54894

+BU_ALTIVEC_X (STVXL_V2DF, "stvxl_v2df", MEM)

54895

+BU_ALTIVEC_X (STVXL_V2DI, "stvxl_v2di", MEM)

54896

+BU_ALTIVEC_X (STVXL_V4SF, "stvxl_v4sf", MEM)

54897

+BU_ALTIVEC_X (STVXL_V4SI, "stvxl_v4si", MEM)

54898

+BU_ALTIVEC_X (STVXL_V8HI, "stvxl_v8hi", MEM)

54899

+BU_ALTIVEC_X (STVXL_V16QI, "stvxl_v16qi", MEM)

54900

BU_ALTIVEC_C (STVLX, "stvlx", MEM)

54901

BU_ALTIVEC_C (STVLXL, "stvlxl", MEM)

54902

BU_ALTIVEC_C (STVRX, "stvrx", MEM)

54903

@@ -904,6 +1176,7 @@

54904

BU_VSX_3 (XVNMADDDP, "xvnmadddp", CONST, nfmav2df4)

54905

BU_VSX_3 (XVNMSUBDP, "xvnmsubdp", CONST, nfmsv2df4)

54906

54907

+BU_VSX_3 (XXSEL_1TI, "xxsel_1ti", CONST, vector_select_v1ti)

54908

BU_VSX_3 (XXSEL_2DI, "xxsel_2di", CONST, vector_select_v2di)

54909

BU_VSX_3 (XXSEL_2DF, "xxsel_2df", CONST, vector_select_v2df)

54910

BU_VSX_3 (XXSEL_4SF, "xxsel_4sf", CONST, vector_select_v4sf)

54911

@@ -910,11 +1183,13 @@

54912

BU_VSX_3 (XXSEL_4SI, "xxsel_4si", CONST, vector_select_v4si)

54913

BU_VSX_3 (XXSEL_8HI, "xxsel_8hi", CONST, vector_select_v8hi)

54914

BU_VSX_3 (XXSEL_16QI, "xxsel_16qi", CONST, vector_select_v16qi)

54915

+BU_VSX_3 (XXSEL_1TI_UNS, "xxsel_1ti_uns", CONST, vector_select_v1ti_uns)

54916

BU_VSX_3 (XXSEL_2DI_UNS, "xxsel_2di_uns", CONST, vector_select_v2di_uns)

54917

BU_VSX_3 (XXSEL_4SI_UNS, "xxsel_4si_uns", CONST, vector_select_v4si_uns)

54918

BU_VSX_3 (XXSEL_8HI_UNS, "xxsel_8hi_uns", CONST, vector_select_v8hi_uns)

54919

BU_VSX_3 (XXSEL_16QI_UNS, "xxsel_16qi_uns", CONST, vector_select_v16qi_uns)

54920

54921

+BU_VSX_3 (VPERM_1TI, "vperm_1ti", CONST, altivec_vperm_v1ti)

54922

BU_VSX_3 (VPERM_2DI, "vperm_2di", CONST, altivec_vperm_v2di)

54923

BU_VSX_3 (VPERM_2DF, "vperm_2df", CONST, altivec_vperm_v2df)

54924

BU_VSX_3 (VPERM_4SF, "vperm_4sf", CONST, altivec_vperm_v4sf)

54925

@@ -921,11 +1196,13 @@

54926

BU_VSX_3 (VPERM_4SI, "vperm_4si", CONST, altivec_vperm_v4si)

54927

BU_VSX_3 (VPERM_8HI, "vperm_8hi", CONST, altivec_vperm_v8hi)

54928

BU_VSX_3 (VPERM_16QI, "vperm_16qi", CONST, altivec_vperm_v16qi)

54929

+BU_VSX_3 (VPERM_1TI_UNS, "vperm_1ti_uns", CONST, altivec_vperm_v1ti_uns)

54930

BU_VSX_3 (VPERM_2DI_UNS, "vperm_2di_uns", CONST, altivec_vperm_v2di_uns)

54931

BU_VSX_3 (VPERM_4SI_UNS, "vperm_4si_uns", CONST, altivec_vperm_v4si_uns)

54932

BU_VSX_3 (VPERM_8HI_UNS, "vperm_8hi_uns", CONST, altivec_vperm_v8hi_uns)

54933

BU_VSX_3 (VPERM_16QI_UNS, "vperm_16qi_uns", CONST, altivec_vperm_v16qi_uns)

54934

54935

+BU_VSX_3 (XXPERMDI_1TI, "xxpermdi_1ti", CONST, vsx_xxpermdi_v1ti)

54936

BU_VSX_3 (XXPERMDI_2DF, "xxpermdi_2df", CONST, vsx_xxpermdi_v2df)

54937

BU_VSX_3 (XXPERMDI_2DI, "xxpermdi_2di", CONST, vsx_xxpermdi_v2di)

54938

BU_VSX_3 (XXPERMDI_4SF, "xxpermdi_4sf", CONST, vsx_xxpermdi_v4sf)

54939

@@ -932,6 +1209,7 @@

54940

BU_VSX_3 (XXPERMDI_4SI, "xxpermdi_4si", CONST, vsx_xxpermdi_v4si)

54941

BU_VSX_3 (XXPERMDI_8HI, "xxpermdi_8hi", CONST, vsx_xxpermdi_v8hi)

54942

BU_VSX_3 (XXPERMDI_16QI, "xxpermdi_16qi", CONST, vsx_xxpermdi_v16qi)

54943

+BU_VSX_3 (SET_1TI, "set_1ti", CONST, vsx_set_v1ti)

54944

BU_VSX_3 (SET_2DF, "set_2df", CONST, vsx_set_v2df)

54945

BU_VSX_3 (SET_2DI, "set_2di", CONST, vsx_set_v2di)

54946

BU_VSX_3 (XXSLDWI_2DI, "xxsldwi_2di", CONST, vsx_xxsldwi_v2di)

54947

@@ -1012,7 +1290,7 @@

54948

BU_VSX_1 (XVRESP, "xvresp", CONST, vsx_frev4sf2)

54949

54950

BU_VSX_1 (XSCVDPSP, "xscvdpsp", CONST, vsx_xscvdpsp)

54951

-BU_VSX_1 (XSCVSPDP, "xscvspdp", CONST, vsx_xscvdpsp)

54952

+BU_VSX_1 (XSCVSPDP, "xscvspdp", CONST, vsx_xscvspdp)

54953

BU_VSX_1 (XVCVDPSP, "xvcvdpsp", CONST, vsx_xvcvdpsp)

54954

BU_VSX_1 (XVCVSPDP, "xvcvspdp", CONST, vsx_xvcvspdp)

54955

BU_VSX_1 (XSTSQRTDP_FE, "xstsqrtdp_fe", CONST, vsx_tsqrtdf2_fe)

54956

@@ -1052,9 +1330,9 @@

54957

54958

BU_VSX_1 (XSRDPI, "xsrdpi", CONST, vsx_xsrdpi)

54959

BU_VSX_1 (XSRDPIC, "xsrdpic", CONST, vsx_xsrdpic)

54960

-BU_VSX_1 (XSRDPIM, "xsrdpim", CONST, vsx_floordf2)

54961

-BU_VSX_1 (XSRDPIP, "xsrdpip", CONST, vsx_ceildf2)

54962

-BU_VSX_1 (XSRDPIZ, "xsrdpiz", CONST, vsx_btruncdf2)

54963

+BU_VSX_1 (XSRDPIM, "xsrdpim", CONST, floordf2)

54964

+BU_VSX_1 (XSRDPIP, "xsrdpip", CONST, ceildf2)

54965

+BU_VSX_1 (XSRDPIZ, "xsrdpiz", CONST, btruncdf2)

54966

54967

/* VSX predicate functions. */

54968

BU_VSX_P (XVCMPEQSP_P, "xvcmpeqsp_p", CONST, vector_eq_v4sf_p)

54969

@@ -1066,6 +1344,7 @@

54970

54971

/* VSX builtins that are handled as special cases. */

54972

BU_VSX_X (LXSDX, "lxsdx", MEM)

54973

+BU_VSX_X (LXVD2X_V1TI, "lxvd2x_v1ti", MEM)

54974

BU_VSX_X (LXVD2X_V2DF, "lxvd2x_v2df", MEM)

54975

BU_VSX_X (LXVD2X_V2DI, "lxvd2x_v2di", MEM)

54976

BU_VSX_X (LXVDSX, "lxvdsx", MEM)

54977

@@ -1074,6 +1353,7 @@

54978

BU_VSX_X (LXVW4X_V8HI, "lxvw4x_v8hi", MEM)

54979

BU_VSX_X (LXVW4X_V16QI, "lxvw4x_v16qi", MEM)

54980

BU_VSX_X (STXSDX, "stxsdx", MEM)

54981

+BU_VSX_X (STXVD2X_V1TI, "stxsdx_v1ti", MEM)

54982

BU_VSX_X (STXVD2X_V2DF, "stxsdx_v2df", MEM)

54983

BU_VSX_X (STXVD2X_V2DI, "stxsdx_v2di", MEM)

54984

BU_VSX_X (STXVW4X_V4SF, "stxsdx_v4sf", MEM)

54985

@@ -1104,10 +1384,13 @@

54986

BU_VSX_X (XSNMSUBADP, "xsnmsubadp", FP)

54987

BU_VSX_X (XSNMSUBMDP, "xsnmsubmdp", FP)

54988

BU_VSX_X (XSSUBDP, "xssubdp", FP)

54989

+BU_VSX_X (VEC_INIT_V1TI, "vec_init_v1ti", CONST)

54990

BU_VSX_X (VEC_INIT_V2DF, "vec_init_v2df", CONST)

54991

BU_VSX_X (VEC_INIT_V2DI, "vec_init_v2di", CONST)

54992

+BU_VSX_X (VEC_SET_V1TI, "vec_set_v1ti", CONST)

54993

BU_VSX_X (VEC_SET_V2DF, "vec_set_v2df", CONST)

54994

BU_VSX_X (VEC_SET_V2DI, "vec_set_v2di", CONST)

54995

+BU_VSX_X (VEC_EXT_V1TI, "vec_ext_v1ti", CONST)

54996

BU_VSX_X (VEC_EXT_V2DF, "vec_ext_v2df", CONST)

54997

BU_VSX_X (VEC_EXT_V2DI, "vec_ext_v2di", CONST)

54998

54999

@@ -1132,6 +1415,249 @@

55000

BU_VSX_OVERLOAD_X (LD, "ld")

55001

BU_VSX_OVERLOAD_X (ST, "st")

55002

55003

+/* 1 argument VSX instructions added in ISA 2.07. */

55004

+BU_P8V_VSX_1 (XSCVSPDPN, "xscvspdpn", CONST, vsx_xscvspdpn)

55005

+BU_P8V_VSX_1 (XSCVDPSPN, "xscvdpspn", CONST, vsx_xscvdpspn)

55006

+

55007

+/* 1 argument altivec instructions added in ISA 2.07. */

55008

+BU_P8V_AV_1 (ABS_V2DI, "abs_v2di", CONST, absv2di2)

55009

+BU_P8V_AV_1 (VUPKHSW, "vupkhsw", CONST, altivec_vupkhsw)

55010

+BU_P8V_AV_1 (VUPKLSW, "vupklsw", CONST, altivec_vupklsw)

55011

+BU_P8V_AV_1 (VCLZB, "vclzb", CONST, clzv16qi2)

55012

+BU_P8V_AV_1 (VCLZH, "vclzh", CONST, clzv8hi2)

55013

+BU_P8V_AV_1 (VCLZW, "vclzw", CONST, clzv4si2)

55014

+BU_P8V_AV_1 (VCLZD, "vclzd", CONST, clzv2di2)

55015

+BU_P8V_AV_1 (VPOPCNTB, "vpopcntb", CONST, popcountv16qi2)

55016

+BU_P8V_AV_1 (VPOPCNTH, "vpopcnth", CONST, popcountv8hi2)

55017

+BU_P8V_AV_1 (VPOPCNTW, "vpopcntw", CONST, popcountv4si2)

55018

+BU_P8V_AV_1 (VPOPCNTD, "vpopcntd", CONST, popcountv2di2)

55019

+BU_P8V_AV_1 (VGBBD, "vgbbd", CONST, p8v_vgbbd)

55020

+

55021

+/* 2 argument altivec instructions added in ISA 2.07. */

55022

+BU_P8V_AV_2 (VADDCUQ, "vaddcuq", CONST, altivec_vaddcuq)

55023

+BU_P8V_AV_2 (VADDUDM, "vaddudm", CONST, addv2di3)

55024

+BU_P8V_AV_2 (VADDUQM, "vadduqm", CONST, altivec_vadduqm)

55025

+BU_P8V_AV_2 (VMINSD, "vminsd", CONST, sminv2di3)

55026

+BU_P8V_AV_2 (VMAXSD, "vmaxsd", CONST, smaxv2di3)

55027

+BU_P8V_AV_2 (VMINUD, "vminud", CONST, uminv2di3)

55028

+BU_P8V_AV_2 (VMAXUD, "vmaxud", CONST, umaxv2di3)

55029

+BU_P8V_AV_2 (VMRGEW, "vmrgew", CONST, p8_vmrgew)

55030

+BU_P8V_AV_2 (VMRGOW, "vmrgow", CONST, p8_vmrgow)

55031

+BU_P8V_AV_2 (VBPERMQ, "vbpermq", CONST, altivec_vbpermq)

55032

+BU_P8V_AV_2 (VPKUDUM, "vpkudum", CONST, altivec_vpkudum)

55033

+BU_P8V_AV_2 (VPKSDSS, "vpksdss", CONST, altivec_vpksdss)

55034

+BU_P8V_AV_2 (VPKUDUS, "vpkudus", CONST, altivec_vpkudus)

55035

+BU_P8V_AV_2 (VPKSDUS, "vpksdus", CONST, altivec_vpksdus)

55036

+BU_P8V_AV_2 (VRLD, "vrld", CONST, vrotlv2di3)

55037

+BU_P8V_AV_2 (VSLD, "vsld", CONST, vashlv2di3)

55038

+BU_P8V_AV_2 (VSRD, "vsrd", CONST, vlshrv2di3)

55039

+BU_P8V_AV_2 (VSRAD, "vsrad", CONST, vashrv2di3)

55040

+BU_P8V_AV_2 (VSUBCUQ, "vsubcuq", CONST, altivec_vsubcuq)

55041

+BU_P8V_AV_2 (VSUBUDM, "vsubudm", CONST, subv2di3)

55042

+BU_P8V_AV_2 (VSUBUQM, "vsubuqm", CONST, altivec_vsubuqm)

55043

+

55044

+BU_P8V_AV_2 (EQV_V16QI, "eqv_v16qi", CONST, eqvv16qi3)

55045

+BU_P8V_AV_2 (EQV_V8HI, "eqv_v8hi", CONST, eqvv8hi3)

55046

+BU_P8V_AV_2 (EQV_V4SI, "eqv_v4si", CONST, eqvv4si3)

55047

+BU_P8V_AV_2 (EQV_V2DI, "eqv_v2di", CONST, eqvv2di3)

55048

+BU_P8V_AV_2 (EQV_V1TI, "eqv_v1ti", CONST, eqvv1ti3)

55049

+BU_P8V_AV_2 (EQV_V4SF, "eqv_v4sf", CONST, eqvv4sf3)

55050

+BU_P8V_AV_2 (EQV_V2DF, "eqv_v2df", CONST, eqvv2df3)

55051

+

55052

+BU_P8V_AV_2 (NAND_V16QI, "nand_v16qi", CONST, nandv16qi3)

55053

+BU_P8V_AV_2 (NAND_V8HI, "nand_v8hi", CONST, nandv8hi3)

55054

+BU_P8V_AV_2 (NAND_V4SI, "nand_v4si", CONST, nandv4si3)

55055

+BU_P8V_AV_2 (NAND_V2DI, "nand_v2di", CONST, nandv2di3)

55056

+BU_P8V_AV_2 (NAND_V1TI, "nand_v1ti", CONST, nandv1ti3)

55057

+BU_P8V_AV_2 (NAND_V4SF, "nand_v4sf", CONST, nandv4sf3)

55058

+BU_P8V_AV_2 (NAND_V2DF, "nand_v2df", CONST, nandv2df3)

55059

+

55060

+BU_P8V_AV_2 (ORC_V16QI, "orc_v16qi", CONST, orcv16qi3)

55061

+BU_P8V_AV_2 (ORC_V8HI, "orc_v8hi", CONST, orcv8hi3)

55062

+BU_P8V_AV_2 (ORC_V4SI, "orc_v4si", CONST, orcv4si3)

55063

+BU_P8V_AV_2 (ORC_V2DI, "orc_v2di", CONST, orcv2di3)

55064

+BU_P8V_AV_2 (ORC_V1TI, "orc_v1ti", CONST, orcv1ti3)

55065

+BU_P8V_AV_2 (ORC_V4SF, "orc_v4sf", CONST, orcv4sf3)

55066

+BU_P8V_AV_2 (ORC_V2DF, "orc_v2df", CONST, orcv2df3)

55067

+

55068

+/* 3 argument altivec instructions added in ISA 2.07. */

55069

+BU_P8V_AV_3 (VADDEUQM, "vaddeuqm", CONST, altivec_vaddeuqm)

55070

+BU_P8V_AV_3 (VADDECUQ, "vaddecuq", CONST, altivec_vaddecuq)

55071

+BU_P8V_AV_3 (VSUBEUQM, "vsubeuqm", CONST, altivec_vsubeuqm)

55072

+BU_P8V_AV_3 (VSUBECUQ, "vsubecuq", CONST, altivec_vsubecuq)

55073

+

55074

+/* Vector comparison instructions added in ISA 2.07. */

55075

+BU_P8V_AV_2 (VCMPEQUD, "vcmpequd", CONST, vector_eqv2di)

55076

+BU_P8V_AV_2 (VCMPGTSD, "vcmpgtsd", CONST, vector_gtv2di)

55077

+BU_P8V_AV_2 (VCMPGTUD, "vcmpgtud", CONST, vector_gtuv2di)

55078

+

55079

+/* Vector comparison predicate instructions added in ISA 2.07. */

55080

+BU_P8V_AV_P (VCMPEQUD_P, "vcmpequd_p", CONST, vector_eq_v2di_p)

55081

+BU_P8V_AV_P (VCMPGTSD_P, "vcmpgtsd_p", CONST, vector_gt_v2di_p)

55082

+BU_P8V_AV_P (VCMPGTUD_P, "vcmpgtud_p", CONST, vector_gtu_v2di_p)

55083

+

55084

+/* ISA 2.07 vector overloaded 1 argument functions. */

55085

+BU_P8V_OVERLOAD_1 (VUPKHSW, "vupkhsw")

55086

+BU_P8V_OVERLOAD_1 (VUPKLSW, "vupklsw")

55087

+BU_P8V_OVERLOAD_1 (VCLZ, "vclz")

55088

+BU_P8V_OVERLOAD_1 (VCLZB, "vclzb")

55089

+BU_P8V_OVERLOAD_1 (VCLZH, "vclzh")

55090

+BU_P8V_OVERLOAD_1 (VCLZW, "vclzw")

55091

+BU_P8V_OVERLOAD_1 (VCLZD, "vclzd")

55092

+BU_P8V_OVERLOAD_1 (VPOPCNT, "vpopcnt")

55093

+BU_P8V_OVERLOAD_1 (VPOPCNTB, "vpopcntb")

55094

+BU_P8V_OVERLOAD_1 (VPOPCNTH, "vpopcnth")

55095

+BU_P8V_OVERLOAD_1 (VPOPCNTW, "vpopcntw")

55096

+BU_P8V_OVERLOAD_1 (VPOPCNTD, "vpopcntd")

55097

+BU_P8V_OVERLOAD_1 (VGBBD, "vgbbd")

55098

+

55099

+/* ISA 2.07 vector overloaded 2 argument functions. */

55100

+BU_P8V_OVERLOAD_2 (EQV, "eqv")

55101

+BU_P8V_OVERLOAD_2 (NAND, "nand")

55102

+BU_P8V_OVERLOAD_2 (ORC, "orc")

55103

+BU_P8V_OVERLOAD_2 (VADDCUQ, "vaddcuq")

55104

+BU_P8V_OVERLOAD_2 (VADDUDM, "vaddudm")

55105

+BU_P8V_OVERLOAD_2 (VADDUQM, "vadduqm")

55106

+BU_P8V_OVERLOAD_2 (VBPERMQ, "vbpermq")

55107

+BU_P8V_OVERLOAD_2 (VMAXSD, "vmaxsd")

55108

+BU_P8V_OVERLOAD_2 (VMAXUD, "vmaxud")

55109

+BU_P8V_OVERLOAD_2 (VMINSD, "vminsd")

55110

+BU_P8V_OVERLOAD_2 (VMINUD, "vminud")

55111

+BU_P8V_OVERLOAD_2 (VMRGEW, "vmrgew")

55112

+BU_P8V_OVERLOAD_2 (VMRGOW, "vmrgow")

55113

+BU_P8V_OVERLOAD_2 (VPKSDSS, "vpksdss")

55114

+BU_P8V_OVERLOAD_2 (VPKSDUS, "vpksdus")

55115

+BU_P8V_OVERLOAD_2 (VPKUDUM, "vpkudum")

55116

+BU_P8V_OVERLOAD_2 (VPKUDUS, "vpkudus")

55117

+BU_P8V_OVERLOAD_2 (VRLD, "vrld")

55118

+BU_P8V_OVERLOAD_2 (VSLD, "vsld")

55119

+BU_P8V_OVERLOAD_2 (VSRAD, "vsrad")

55120

+BU_P8V_OVERLOAD_2 (VSRD, "vsrd")

55121

+BU_P8V_OVERLOAD_2 (VSUBCUQ, "vsubcuq")

55122

+BU_P8V_OVERLOAD_2 (VSUBUDM, "vsubudm")

55123

+BU_P8V_OVERLOAD_2 (VSUBUQM, "vsubuqm")

55124

+

55125

+/* ISA 2.07 vector overloaded 3 argument functions. */

55126

+BU_P8V_OVERLOAD_3 (VADDECUQ, "vaddecuq")

55127

+BU_P8V_OVERLOAD_3 (VADDEUQM, "vaddeuqm")

55128

+BU_P8V_OVERLOAD_3 (VSUBECUQ, "vsubecuq")

55129

+BU_P8V_OVERLOAD_3 (VSUBEUQM, "vsubeuqm")

55130

+

55131

+

55132

+/* 2 argument extended divide functions added in ISA 2.06. */

55133

+BU_P7_MISC_2 (DIVWE, "divwe", CONST, dive_si)

55134

+BU_P7_MISC_2 (DIVWEO, "divweo", CONST, diveo_si)

55135

+BU_P7_MISC_2 (DIVWEU, "divweu", CONST, diveu_si)

55136

+BU_P7_MISC_2 (DIVWEUO, "divweuo", CONST, diveuo_si)

55137

+BU_P7_MISC_2 (DIVDE, "divde", CONST, dive_di)

55138

+BU_P7_MISC_2 (DIVDEO, "divdeo", CONST, diveo_di)

55139

+BU_P7_MISC_2 (DIVDEU, "divdeu", CONST, diveu_di)

55140

+BU_P7_MISC_2 (DIVDEUO, "divdeuo", CONST, diveuo_di)

55141

+

55142

+/* 1 argument DFP (decimal floating point) functions added in ISA 2.05. */

55143

+BU_DFP_MISC_1 (DXEX, "dxex", CONST, dfp_dxex_dd)

55144

+BU_DFP_MISC_1 (DXEXQ, "dxexq", CONST, dfp_dxex_td)

55145

+

55146

+/* 2 argument DFP (decimal floating point) functions added in ISA 2.05. */

55147

+BU_DFP_MISC_2 (DDEDPD, "ddedpd", CONST, dfp_ddedpd_dd)

55148

+BU_DFP_MISC_2 (DDEDPDQ, "ddedpdq", CONST, dfp_ddedpd_td)

55149

+BU_DFP_MISC_2 (DENBCD, "denbcd", CONST, dfp_denbcd_dd)

55150

+BU_DFP_MISC_2 (DENBCDQ, "denbcdq", CONST, dfp_denbcd_td)

55151

+BU_DFP_MISC_2 (DIEX, "diex", CONST, dfp_diex_dd)

55152

+BU_DFP_MISC_2 (DIEXQ, "diexq", CONST, dfp_diex_td)

55153

+BU_DFP_MISC_2 (DSCLI, "dscli", CONST, dfp_dscli_dd)

55154

+BU_DFP_MISC_2 (DSCLIQ, "dscliq", CONST, dfp_dscli_td)

55155

+BU_DFP_MISC_2 (DSCRI, "dscri", CONST, dfp_dscri_dd)

55156

+BU_DFP_MISC_2 (DSCRIQ, "dscriq", CONST, dfp_dscri_td)

55157

+

55158

+/* 1 argument BCD functions added in ISA 2.06. */

55159

+BU_P7_MISC_1 (CDTBCD, "cdtbcd", CONST, cdtbcd)

55160

+BU_P7_MISC_1 (CBCDTD, "cbcdtd", CONST, cbcdtd)

55161

+

55162

+/* 2 argument BCD functions added in ISA 2.06. */

55163

+BU_P7_MISC_2 (ADDG6S, "addg6s", CONST, addg6s)

55164

+

55165

+/* 3 argument BCD functions added in ISA 2.07. */

55166

+BU_P8V_MISC_3 (BCDADD, "bcdadd", CONST, bcdadd)

55167

+BU_P8V_MISC_3 (BCDADD_LT, "bcdadd_lt", CONST, bcdadd_lt)

55168

+BU_P8V_MISC_3 (BCDADD_EQ, "bcdadd_eq", CONST, bcdadd_eq)

55169

+BU_P8V_MISC_3 (BCDADD_GT, "bcdadd_gt", CONST, bcdadd_gt)

55170

+BU_P8V_MISC_3 (BCDADD_OV, "bcdadd_ov", CONST, bcdadd_unordered)

55171

+BU_P8V_MISC_3 (BCDSUB, "bcdsub", CONST, bcdsub)

55172

+BU_P8V_MISC_3 (BCDSUB_LT, "bcdsub_lt", CONST, bcdsub_lt)

55173

+BU_P8V_MISC_3 (BCDSUB_EQ, "bcdsub_eq", CONST, bcdsub_eq)

55174

+BU_P8V_MISC_3 (BCDSUB_GT, "bcdsub_gt", CONST, bcdsub_gt)

55175

+BU_P8V_MISC_3 (BCDSUB_OV, "bcdsub_ov", CONST, bcdsub_unordered)

55176

+

55177

+/* 2 argument pack/unpack 128-bit floating point types. */

55178

+BU_DFP_MISC_2 (PACK_TD, "pack_dec128", CONST, packtd)

55179

+BU_DFP_MISC_2 (UNPACK_TD, "unpack_dec128", CONST, unpacktd)

55180

+

55181

+BU_MISC_2 (PACK_TF, "pack_longdouble", CONST, packtf)

55182

+BU_MISC_2 (UNPACK_TF, "unpack_longdouble", CONST, unpacktf)

55183

+BU_MISC_1 (UNPACK_TF_0, "longdouble_dw0", CONST, unpacktf_0)

55184

+BU_MISC_1 (UNPACK_TF_1, "longdouble_dw1", CONST, unpacktf_1)

55185

+

55186

+BU_P7_MISC_2 (PACK_V1TI, "pack_vector_int128", CONST, packv1ti)

55187

+BU_P7_MISC_2 (UNPACK_V1TI, "unpack_vector_int128", CONST, unpackv1ti)

55188

+

55189

+

55190

+/* 1 argument crypto functions. */

55191

+BU_CRYPTO_1 (VSBOX, "vsbox", CONST, crypto_vsbox)

55192

+

55193

+/* 2 argument crypto functions. */

55194

+BU_CRYPTO_2 (VCIPHER, "vcipher", CONST, crypto_vcipher)

55195

+BU_CRYPTO_2 (VCIPHERLAST, "vcipherlast", CONST, crypto_vcipherlast)

55196

+BU_CRYPTO_2 (VNCIPHER, "vncipher", CONST, crypto_vncipher)

55197

+BU_CRYPTO_2 (VNCIPHERLAST, "vncipherlast", CONST, crypto_vncipherlast)

55198

+BU_CRYPTO_2 (VPMSUMB, "vpmsumb", CONST, crypto_vpmsumb)

55199

+BU_CRYPTO_2 (VPMSUMH, "vpmsumh", CONST, crypto_vpmsumh)

55200

+BU_CRYPTO_2 (VPMSUMW, "vpmsumw", CONST, crypto_vpmsumw)

55201

+BU_CRYPTO_2 (VPMSUMD, "vpmsumd", CONST, crypto_vpmsumd)

55202

+

55203

+/* 3 argument crypto functions. */

55204

+BU_CRYPTO_3 (VPERMXOR_V2DI, "vpermxor_v2di", CONST, crypto_vpermxor_v2di)

55205

+BU_CRYPTO_3 (VPERMXOR_V4SI, "vpermxor_v4si", CONST, crypto_vpermxor_v4si)

55206

+BU_CRYPTO_3 (VPERMXOR_V8HI, "vpermxor_v8hi", CONST, crypto_vpermxor_v8hi)

55207

+BU_CRYPTO_3 (VPERMXOR_V16QI, "vpermxor_v16qi", CONST, crypto_vpermxor_v16qi)

55208

+BU_CRYPTO_3 (VSHASIGMAW, "vshasigmaw", CONST, crypto_vshasigmaw)

55209

+BU_CRYPTO_3 (VSHASIGMAD, "vshasigmad", CONST, crypto_vshasigmad)

55210

+

55211

+/* 2 argument crypto overloaded functions. */

55212

+BU_CRYPTO_OVERLOAD_2 (VPMSUM, "vpmsum")

55213

+

55214

+/* 3 argument crypto overloaded functions. */

55215

+BU_CRYPTO_OVERLOAD_3 (VPERMXOR, "vpermxor")

55216

+BU_CRYPTO_OVERLOAD_3 (VSHASIGMA, "vshasigma")

55217

+

55218

+

55219

+/* HTM functions. */

55220

+BU_HTM_1 (TABORT, "tabort", MISC, tabort)

55221

+BU_HTM_3 (TABORTDC, "tabortdc", MISC, tabortdc)

55222

+BU_HTM_3 (TABORTDCI, "tabortdci", MISC, tabortdci)

55223

+BU_HTM_3 (TABORTWC, "tabortwc", MISC, tabortwc)

55224

+BU_HTM_3 (TABORTWCI, "tabortwci", MISC, tabortwci)

55225

+BU_HTM_1 (TBEGIN, "tbegin", MISC, tbegin)

55226

+BU_HTM_1 (TCHECK, "tcheck", MISC, tcheck)

55227

+BU_HTM_1 (TEND, "tend", MISC, tend)

55228

+BU_HTM_0 (TENDALL, "tendall", MISC, tend)

55229

+BU_HTM_0 (TRECHKPT, "trechkpt", MISC, trechkpt)

55230

+BU_HTM_1 (TRECLAIM, "treclaim", MISC, treclaim)

55231

+BU_HTM_0 (TRESUME, "tresume", MISC, tsr)

55232

+BU_HTM_0 (TSUSPEND, "tsuspend", MISC, tsr)

55233

+BU_HTM_1 (TSR, "tsr", MISC, tsr)

55234

+BU_HTM_0 (TTEST, "ttest", MISC, ttest)

55235

+

55236

+BU_HTM_SPR0 (GET_TFHAR, "get_tfhar", MISC, nothing)

55237

+BU_HTM_SPR1 (SET_TFHAR, "set_tfhar", MISC, nothing)

55238

+BU_HTM_SPR0 (GET_TFIAR, "get_tfiar", MISC, nothing)

55239

+BU_HTM_SPR1 (SET_TFIAR, "set_tfiar", MISC, nothing)

55240

+BU_HTM_SPR0 (GET_TEXASR, "get_texasr", MISC, nothing)

55241

+BU_HTM_SPR1 (SET_TEXASR, "set_texasr", MISC, nothing)

55242

+BU_HTM_SPR0 (GET_TEXASRU, "get_texasru", MISC, nothing)

55243

+BU_HTM_SPR1 (SET_TEXASRU, "set_texasru", MISC, nothing)

55244

+

55245

+

55246

/* 3 argument paired floating point builtins. */

55247

BU_PAIRED_3 (MSUB, "msub", FP, fmsv2sf4)

55248

BU_PAIRED_3 (MADD, "madd", FP, fmav2sf4)

55249

@@ -1430,10 +1956,10 @@

55250

RS6000_BTC_FP)

55251

55252

BU_SPECIAL_X (RS6000_BUILTIN_GET_TB, "__builtin_ppc_get_timebase",

55253

- RS6000_BTM_ALWAYS, RS6000_BTC_MISC)

55254

+ RS6000_BTM_ALWAYS, RS6000_BTC_MISC)

55255

55256

BU_SPECIAL_X (RS6000_BUILTIN_MFTB, "__builtin_ppc_mftb",

55257

- RS6000_BTM_ALWAYS, RS6000_BTC_MISC)

55258

+ RS6000_BTM_ALWAYS, RS6000_BTC_MISC)

55259

55260

/* Darwin CfString builtin. */

55261

BU_SPECIAL_X (RS6000_BUILTIN_CFSTRING, "__builtin_cfstring", RS6000_BTM_ALWAYS,

55262

Index: gcc/config/rs6000/rs6000-c.c

55263

===================================================================

55264

--- a/src/gcc/config/rs6000/rs6000-c.c (.../tags/gcc_4_8_2_release)

55265

+++ b/src/gcc/config/rs6000/rs6000-c.c (.../branches/gcc-4_8-branch)

55266

@@ -90,6 +90,8 @@

55267

static GTY(()) tree __bool_keyword;

55268

static GTY(()) tree bool_keyword;

55269

static GTY(()) tree _Bool_keyword;

55270

+static GTY(()) tree __int128_type;

55271

+static GTY(()) tree __uint128_type;

55272

55273

/* Preserved across calls. */

55274

static tree expand_bool_pixel;

55275

@@ -122,9 +124,10 @@

55276

static void

55277

init_vector_keywords (void)

55278

{

55279

- /* Keywords without two leading underscores are context-sensitive,

55280

- and hence implemented as conditional macros, controlled by the

55281

- rs6000_macro_to_expand() function below. */

55282

+ /* Keywords without two leading underscores are context-sensitive, and hence

55283

+ implemented as conditional macros, controlled by the

55284

+ rs6000_macro_to_expand() function below. If we have ISA 2.07 64-bit

55285

+ support, record the __int128_t and __uint128_t types. */

55286

55287

__vector_keyword = get_identifier ("__vector");

55288

C_CPP_HASHNODE (__vector_keyword)->flags |= NODE_CONDITIONAL;

55289

@@ -146,6 +149,12 @@

55290

55291

_Bool_keyword = get_identifier ("_Bool");

55292

C_CPP_HASHNODE (_Bool_keyword)->flags |= NODE_CONDITIONAL;

55293

+

55294

+ if (TARGET_VADDUQM)

55295

+ {

55296

+ __int128_type = get_identifier ("__int128_t");

55297

+ __uint128_type = get_identifier ("__uint128_t");

55298

+ }

55299

}

55300

55301

/* Called to decide whether a conditional macro should be expanded.

55302

@@ -221,7 +230,8 @@

55303

|| rid_code == RID_SHORT || rid_code == RID_SIGNED

55304

|| rid_code == RID_INT || rid_code == RID_CHAR

55305

|| rid_code == RID_FLOAT

55306

- || (rid_code == RID_DOUBLE && TARGET_VSX))

55307

+ || (rid_code == RID_DOUBLE && TARGET_VSX)

55308

+ || (rid_code == RID_INT128 && TARGET_VADDUQM))

55309

{

55310

expand_this = C_CPP_HASHNODE (__vector_keyword);

55311

/* If the next keyword is bool or pixel, it

55312

@@ -248,6 +258,13 @@

55313

expand_bool_pixel = __bool_keyword;

55314

}

55315

}

55316

+

55317

+ /* Support vector __int128_t, but we don't need to worry about bool

55318

+ or pixel on this type. */

55319

+ else if (TARGET_VADDUQM

55320

+ && (ident == C_CPP_HASHNODE (__int128_type)

55321

+ || ident == C_CPP_HASHNODE (__uint128_type)))

55322

+ expand_this = C_CPP_HASHNODE (__vector_keyword);

55323

}

55324

}

55325

else if (expand_bool_pixel && ident == C_CPP_HASHNODE (__pixel_keyword))

55326

@@ -315,6 +332,8 @@

55327

rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6X");

55328

if ((flags & OPTION_MASK_POPCNTD) != 0)

55329

rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");

55330

+ if ((flags & OPTION_MASK_DIRECT_MOVE) != 0)

55331

+ rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8");

55332

if ((flags & OPTION_MASK_SOFT_FLOAT) != 0)

55333

rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT");

55334

if ((flags & OPTION_MASK_RECIP_PRECISION) != 0)

55335

@@ -331,6 +350,16 @@

55336

}

55337

if ((flags & OPTION_MASK_VSX) != 0)

55338

rs6000_define_or_undefine_macro (define_p, "__VSX__");

55339

+ if ((flags & OPTION_MASK_HTM) != 0)

55340

+ rs6000_define_or_undefine_macro (define_p, "__HTM__");

55341

+ if ((flags & OPTION_MASK_P8_VECTOR) != 0)

55342

+ rs6000_define_or_undefine_macro (define_p, "__POWER8_VECTOR__");

55343

+ if ((flags & OPTION_MASK_QUAD_MEMORY) != 0)

55344

+ rs6000_define_or_undefine_macro (define_p, "__QUAD_MEMORY__");

55345

+ if ((flags & OPTION_MASK_QUAD_MEMORY_ATOMIC) != 0)

55346

+ rs6000_define_or_undefine_macro (define_p, "__QUAD_MEMORY_ATOMIC__");

55347

+ if ((flags & OPTION_MASK_CRYPTO) != 0)

55348

+ rs6000_define_or_undefine_macro (define_p, "__CRYPTO__");

55349

55350

/* options from the builtin masks. */

55351

if ((bu_mask & RS6000_BTM_SPE) != 0)

55352

@@ -453,7 +482,11 @@

55353

case ABI_AIX:

55354

builtin_define ("_CALL_AIXDESC");

55355

builtin_define ("_CALL_AIX");

55356

+ builtin_define ("_CALL_ELF=1");

55357

break;

55358

+ case ABI_ELFv2:

55359

+ builtin_define ("_CALL_ELF=2");

55360

+ break;

55361

case ABI_DARWIN:

55362

builtin_define ("_CALL_DARWIN");

55363

break;

55364

@@ -465,6 +498,13 @@

55365

if (TARGET_SOFT_FLOAT || !TARGET_FPRS)

55366

builtin_define ("__NO_FPRS__");

55367

55368

+ /* Whether aggregates passed by value are aligned to a 16 byte boundary

55369

+ if their alignment is 16 bytes or larger. */

55370

+ if ((TARGET_MACHO && rs6000_darwin64_abi)

55371

+ || DEFAULT_ABI == ABI_ELFv2

55372

+ || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm))

55373

+ builtin_define ("__STRUCT_PARM_ALIGN__=16");

55374

+

55375

/* Generate defines for Xilinx FPU. */

55376

if (rs6000_xilinx_fpu)

55377

{

55378

@@ -505,6 +545,8 @@

55379

RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },

55380

{ ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SI,

55381

RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },

55382

+ { ALTIVEC_BUILTIN_VEC_ABS, P8V_BUILTIN_ABS_V2DI,

55383

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },

55384

{ ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SF,

55385

RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },

55386

{ ALTIVEC_BUILTIN_VEC_ABS, VSX_BUILTIN_XVABSDP,

55387

@@ -577,6 +619,10 @@

55388

RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },

55389

{ ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSH,

55390

RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },

55391

+ { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW,

55392

+ RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },

55393

+ { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW,

55394

+ RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },

55395

{ ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHPX,

55396

RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },

55397

{ ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH,

55398

@@ -583,6 +629,10 @@

55399

RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },

55400

{ ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH,

55401

RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },

55402

+ { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW,

55403

+ RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },

55404

+ { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW,

55405

+ RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },

55406

{ ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX,

55407

RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 },

55408

{ ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX,

55409

@@ -601,6 +651,10 @@

55410

RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },

55411

{ ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSH,

55412

RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },

55413

+ { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW,

55414

+ RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },

55415

+ { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW,

55416

+ RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },

55417

{ ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX,

55418

RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 },

55419

{ ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX,

55420

@@ -651,10 +705,27 @@

55421

RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },

55422

{ ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,

55423

RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },

55424

+ { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,

55425

+ RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },

55426

+ { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,

55427

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },

55428

+ { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,

55429

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },

55430

+ { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,

55431

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

55432

+ { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,

55433

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },

55434

+ { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,

55435

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

55436

{ ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDFP,

55437

RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },

55438

{ ALTIVEC_BUILTIN_VEC_ADD, VSX_BUILTIN_XVADDDP,

55439

RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },

55440

+ { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUQM,

55441

+ RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },

55442

+ { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUQM,

55443

+ RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,

55444

+ RS6000_BTI_unsigned_V1TI, 0 },

55445

{ ALTIVEC_BUILTIN_VEC_VADDFP, ALTIVEC_BUILTIN_VADDFP,

55446

RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },

55447

{ ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,

55448

@@ -937,6 +1008,10 @@

55449

RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },

55450

{ ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW,

55451

RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },

55452

+ { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD,

55453

+ RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },

55454

+ { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD,

55455

+ RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

55456

{ ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQFP,

55457

RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },

55458

{ ALTIVEC_BUILTIN_VEC_CMPEQ, VSX_BUILTIN_XVCMPEQDP,

55459

@@ -975,6 +1050,10 @@

55460

RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },

55461

{ ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSW,

55462

RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },

55463

+ { ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTUD,

55464

+ RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

55465

+ { ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTSD,

55466

+ RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },

55467

{ ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTFP,

55468

RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },

55469

{ ALTIVEC_BUILTIN_VEC_CMPGT, VSX_BUILTIN_XVCMPGTDP,

55470

@@ -1021,6 +1100,10 @@

55471

RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },

55472

{ ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSW,

55473

RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },

55474

+ { ALTIVEC_BUILTIN_VEC_CMPLT, P8V_BUILTIN_VCMPGTUD,

55475

+ RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

55476

+ { ALTIVEC_BUILTIN_VEC_CMPLT, P8V_BUILTIN_VCMPGTSD,

55477

+ RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },

55478

{ ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTFP,

55479

RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },

55480

{ ALTIVEC_BUILTIN_VEC_CMPLT, VSX_BUILTIN_XVCMPGTDP,

55481

@@ -1045,54 +1128,54 @@

55482

RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },

55483

{ VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVDP,

55484

RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },

55485

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55486

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DF,

55487

RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },

55488

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55489

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,

55490

RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },

55491

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55492

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,

55493

RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,

55494

~RS6000_BTI_unsigned_V2DI, 0 },

55495

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55496

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,

55497

RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },

55498

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55499

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SF,

55500

RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },

55501

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55502

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SF,

55503

RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },

55504

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55505

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,

55506

RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },

55507

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55508

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,

55509

RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },

55510

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55511

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,

55512

RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },

55513

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55514

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,

55515

RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },

55516

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55517

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,

55518

RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },

55519

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55520

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,

55521

RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },

55522

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55523

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,

55524

RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },

55525

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55526

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,

55527

RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },

55528

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55529

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,

55530

RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },

55531

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55532

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,

55533

RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },

55534

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55535

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,

55536

RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },

55537

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55538

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,

55539

RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },

55540

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55541

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,

55542

RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },

55543

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55544

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,

55545

RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },

55546

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55547

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,

55548

RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },

55549

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55550

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,

55551

RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },

55552

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55553

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,

55554

RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },

55555

- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,

55556

+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,

55557

RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },

55558

{ ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEBX,

55559

RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },

55560

@@ -1130,55 +1213,55 @@

55561

RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },

55562

{ ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_LVEBX,

55563

RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },

55564

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

55565

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF,

55566

RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },

55567

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

55568

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF,

55569

RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },

55570

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

55571

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,

55572

RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },

55573

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

55574

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,

55575

RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },

55576

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

55577

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,

55578

RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },

55579

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

55580

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,

55581

RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },

55582

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

55583

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,

55584

RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },

55585

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

55586

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,

55587

RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },

55588

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

55589

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,

55590

RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },

55591

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

55592

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,

55593

RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },

55594

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

55595

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,

55596

RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },

55597

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

55598

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,

55599

RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },

55600

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

55601

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,

55602

RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },

55603

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

55604

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,

55605

RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },

55606

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

55607

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,

55608

RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },

55609

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

55610

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,

55611

RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },

55612

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

55613

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,

55614

RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },

55615

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

55616

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,

55617

RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },

55618

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

55619

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,

55620

RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,

55621

~RS6000_BTI_unsigned_V16QI, 0 },

55622

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

55623

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,

55624

RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },

55625

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

55626

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DF,

55627

RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },

55628

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

55629

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,

55630

RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },

55631

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

55632

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,

55633

RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,

55634

~RS6000_BTI_unsigned_V2DI, 0 },

55635

- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,

55636

+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,

55637

RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },

55638

{ ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,

55639

RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },

55640

@@ -1418,6 +1501,18 @@

55641

RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },

55642

{ ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW,

55643

RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },

55644

+ { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD,

55645

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

55646

+ { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD,

55647

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },

55648

+ { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD,

55649

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

55650

+ { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD,

55651

+ RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },

55652

+ { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD,

55653

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },

55654

+ { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD,

55655

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },

55656

{ ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXFP,

55657

RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },

55658

{ ALTIVEC_BUILTIN_VEC_MAX, VSX_BUILTIN_XVMAXDP,

55659

@@ -1604,6 +1699,18 @@

55660

RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },

55661

{ ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW,

55662

RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },

55663

+ { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD,

55664

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

55665

+ { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD,

55666

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },

55667

+ { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD,

55668

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

55669

+ { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD,

55670

+ RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },

55671

+ { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD,

55672

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },

55673

+ { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD,

55674

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },

55675

{ ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINFP,

55676

RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },

55677

{ ALTIVEC_BUILTIN_VEC_MIN, VSX_BUILTIN_XVMINDP,

55678

@@ -1786,6 +1893,12 @@

55679

RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },

55680

{ ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM,

55681

RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },

55682

+ { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,

55683

+ RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },

55684

+ { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,

55685

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

55686

+ { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,

55687

+ RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },

55688

{ ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM,

55689

RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },

55690

{ ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM,

55691

@@ -1812,6 +1925,10 @@

55692

RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },

55693

{ ALTIVEC_BUILTIN_VEC_VPKUWUS, ALTIVEC_BUILTIN_VPKUWUS,

55694

RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },

55695

+ { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKUDUS,

55696

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

55697

+ { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKSDSS,

55698

+ RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },

55699

{ ALTIVEC_BUILTIN_VEC_VPKSHSS, ALTIVEC_BUILTIN_VPKSHSS,

55700

RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },

55701

{ ALTIVEC_BUILTIN_VEC_VPKUHUS, ALTIVEC_BUILTIN_VPKUHUS,

55702

@@ -1824,6 +1941,8 @@

55703

RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },

55704

{ ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKSWUS,

55705

RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },

55706

+ { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKSDUS,

55707

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },

55708

{ ALTIVEC_BUILTIN_VEC_VPKSWUS, ALTIVEC_BUILTIN_VPKSWUS,

55709

RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },

55710

{ ALTIVEC_BUILTIN_VEC_VPKSHUS, ALTIVEC_BUILTIN_VPKSHUS,

55711

@@ -1844,6 +1963,10 @@

55712

RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },

55713

{ ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLW,

55714

RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },

55715

+ { ALTIVEC_BUILTIN_VEC_RL, P8V_BUILTIN_VRLD,

55716

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

55717

+ { ALTIVEC_BUILTIN_VEC_RL, P8V_BUILTIN_VRLD,

55718

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

55719

{ ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VRLW,

55720

RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },

55721

{ ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VRLW,

55722

@@ -1868,6 +1991,10 @@

55723

RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },

55724

{ ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLW,

55725

RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },

55726

+ { ALTIVEC_BUILTIN_VEC_SL, P8V_BUILTIN_VSLD,

55727

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

55728

+ { ALTIVEC_BUILTIN_VEC_SL, P8V_BUILTIN_VSLD,

55729

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

55730

{ ALTIVEC_BUILTIN_VEC_SQRT, VSX_BUILTIN_XVSQRTDP,

55731

RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },

55732

{ ALTIVEC_BUILTIN_VEC_SQRT, VSX_BUILTIN_XVSQRTSP,

55733

@@ -2032,6 +2159,10 @@

55734

RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },

55735

{ ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRW,

55736

RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },

55737

+ { ALTIVEC_BUILTIN_VEC_SR, P8V_BUILTIN_VSRD,

55738

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

55739

+ { ALTIVEC_BUILTIN_VEC_SR, P8V_BUILTIN_VSRD,

55740

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

55741

{ ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VSRW,

55742

RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },

55743

{ ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VSRW,

55744

@@ -2056,6 +2187,10 @@

55745

RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },

55746

{ ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAW,

55747

RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },

55748

+ { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRAD,

55749

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

55750

+ { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRD,

55751

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

55752

{ ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW,

55753

RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },

55754

{ ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW,

55755

@@ -2196,10 +2331,27 @@

55756

RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },

55757

{ ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,

55758

RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },

55759

+ { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,

55760

+ RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },

55761

+ { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,

55762

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },

55763

+ { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,

55764

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },

55765

+ { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,

55766

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

55767

+ { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,

55768

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },

55769

+ { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,

55770

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

55771

{ ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBFP,

55772

RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },

55773

{ ALTIVEC_BUILTIN_VEC_SUB, VSX_BUILTIN_XVSUBDP,

55774

RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },

55775

+ { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUQM,

55776

+ RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },

55777

+ { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUQM,

55778

+ RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,

55779

+ RS6000_BTI_unsigned_V1TI, 0 },

55780

{ ALTIVEC_BUILTIN_VEC_VSUBFP, ALTIVEC_BUILTIN_VSUBFP,

55781

RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },

55782

{ ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,

55783

@@ -2730,63 +2882,63 @@

55784

RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_NOT_OPAQUE },

55785

{ ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,

55786

RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_NOT_OPAQUE },

55787

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

55788

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DF,

55789

RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },

55790

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

55791

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,

55792

RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },

55793

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

55794

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,

55795

RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,

55796

~RS6000_BTI_unsigned_V2DI },

55797

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

55798

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,

55799

RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,

55800

~RS6000_BTI_bool_V2DI },

55801

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

55802

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SF,

55803

RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },

55804

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

55805

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SF,

55806

RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },

55807

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

55808

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,

55809

RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },

55810

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

55811

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,

55812

RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },

55813

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

55814

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,

55815

RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },

55816

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

55817

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,

55818

RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },

55819

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

55820

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,

55821

RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },

55822

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

55823

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,

55824

RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },

55825

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

55826

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,

55827

RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },

55828

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

55829

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,

55830

RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },

55831

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

55832

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,

55833

RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },

55834

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

55835

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,

55836

RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },

55837

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

55838

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,

55839

RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },

55840

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

55841

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,

55842

RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },

55843

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

55844

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,

55845

RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },

55846

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

55847

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,

55848

RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },

55849

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

55850

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,

55851

RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },

55852

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

55853

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,

55854

RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },

55855

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

55856

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,

55857

RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },

55858

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

55859

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,

55860

RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },

55861

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

55862

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,

55863

RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },

55864

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

55865

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,

55866

RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },

55867

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

55868

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,

55869

RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },

55870

- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,

55871

+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,

55872

RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },

55873

{ ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,

55874

RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },

55875

@@ -2858,64 +3010,64 @@

55876

RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void },

55877

{ ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,

55878

RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void },

55879

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

55880

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SF,

55881

RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },

55882

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

55883

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SF,

55884

RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },

55885

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

55886

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,

55887

RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },

55888

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

55889

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,

55890

RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },

55891

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

55892

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,

55893

RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },

55894

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

55895

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,

55896

RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },

55897

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

55898

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,

55899

RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },

55900

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

55901

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,

55902

RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },

55903

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

55904

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,

55905

RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },

55906

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

55907

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,

55908

RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },

55909

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

55910

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,

55911

RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },

55912

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

55913

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,

55914

RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },

55915

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

55916

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,

55917

RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },

55918

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

55919

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,

55920

RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },

55921

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

55922

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,

55923

RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },

55924

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

55925

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,

55926

RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },

55927

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

55928

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,

55929

RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },

55930

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

55931

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,

55932

RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },

55933

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

55934

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,

55935

RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },

55936

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

55937

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,

55938

RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },

55939

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

55940

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,

55941

RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },

55942

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

55943

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,

55944

RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },

55945

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

55946

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,

55947

RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },

55948

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

55949

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,

55950

RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },

55951

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

55952

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DF,

55953

RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },

55954

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

55955

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DF,

55956

RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },

55957

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

55958

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI,

55959

RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },

55960

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

55961

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI,

55962

RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,

55963

~RS6000_BTI_unsigned_V2DI },

55964

- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,

55965

+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI,

55966

RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,

55967

~RS6000_BTI_bool_V2DI },

55968

{ ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,

55969

@@ -3327,6 +3479,20 @@

55970

RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },

55971

{ ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,

55972

RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI },

55973

+ { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,

55974

+ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI },

55975

+ { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,

55976

+ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },

55977

+ { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,

55978

+ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },

55979

+ { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,

55980

+ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI },

55981

+ { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,

55982

+ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },

55983

+ { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,

55984

+ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },

55985

+ { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,

55986

+ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI },

55987

{ ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQFP_P,

55988

RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },

55989

{ ALTIVEC_BUILTIN_VEC_VCMPEQ_P, VSX_BUILTIN_XVCMPEQDP_P,

55990

@@ -3372,11 +3538,509 @@

55991

RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },

55992

{ ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P,

55993

RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },

55994

+ { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P,

55995

+ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI },

55996

+ { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P,

55997

+ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },

55998

+ { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P,

55999

+ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },

56000

+ { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P,

56001

+ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI },

56002

+ { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P,

56003

+ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },

56004

+ { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P,

56005

+ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },

56006

{ ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGEFP_P,

56007

RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },

56008

{ ALTIVEC_BUILTIN_VEC_VCMPGE_P, VSX_BUILTIN_XVCMPGEDP_P,

56009

RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF },

56010

56011

+ /* Power8 vector overloaded functions. */

56012

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,

56013

+ RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },

56014

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,

56015

+ RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },

56016

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,

56017

+ RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },

56018

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,

56019

+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI,

56020

+ RS6000_BTI_unsigned_V16QI, 0 },

56021

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,

56022

+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,

56023

+ RS6000_BTI_bool_V16QI, 0 },

56024

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,

56025

+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,

56026

+ RS6000_BTI_unsigned_V16QI, 0 },

56027

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,

56028

+ RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },

56029

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,

56030

+ RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },

56031

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,

56032

+ RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },

56033

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,

56034

+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI,

56035

+ RS6000_BTI_unsigned_V8HI, 0 },

56036

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,

56037

+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,

56038

+ RS6000_BTI_bool_V8HI, 0 },

56039

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,

56040

+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,

56041

+ RS6000_BTI_unsigned_V8HI, 0 },

56042

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,

56043

+ RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },

56044

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,

56045

+ RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },

56046

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,

56047

+ RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },

56048

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,

56049

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI,

56050

+ RS6000_BTI_unsigned_V4SI, 0 },

56051

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,

56052

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,

56053

+ RS6000_BTI_bool_V4SI, 0 },

56054

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,

56055

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,

56056

+ RS6000_BTI_unsigned_V4SI, 0 },

56057

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,

56058

+ RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },

56059

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,

56060

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },

56061

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,

56062

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },

56063

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,

56064

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,

56065

+ RS6000_BTI_unsigned_V2DI, 0 },

56066

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,

56067

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,

56068

+ RS6000_BTI_bool_V2DI, 0 },

56069

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,

56070

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,

56071

+ RS6000_BTI_unsigned_V2DI, 0 },

56072

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SF,

56073

+ RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },

56074

+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DF,

56075

+ RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },

56076

+

56077

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,

56078

+ RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },

56079

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,

56080

+ RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },

56081

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,

56082

+ RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },

56083

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,

56084

+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI,

56085

+ RS6000_BTI_unsigned_V16QI, 0 },

56086

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,

56087

+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,

56088

+ RS6000_BTI_bool_V16QI, 0 },

56089

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,

56090

+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,

56091

+ RS6000_BTI_unsigned_V16QI, 0 },

56092

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,

56093

+ RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },

56094

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,

56095

+ RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },

56096

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,

56097

+ RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },

56098

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,

56099

+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI,

56100

+ RS6000_BTI_unsigned_V8HI, 0 },

56101

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,

56102

+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,

56103

+ RS6000_BTI_bool_V8HI, 0 },

56104

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,

56105

+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,

56106

+ RS6000_BTI_unsigned_V8HI, 0 },

56107

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,

56108

+ RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },

56109

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,

56110

+ RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },

56111

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,

56112

+ RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },

56113

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,

56114

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI,

56115

+ RS6000_BTI_unsigned_V4SI, 0 },

56116

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,

56117

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,

56118

+ RS6000_BTI_bool_V4SI, 0 },

56119

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,

56120

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,

56121

+ RS6000_BTI_unsigned_V4SI, 0 },

56122

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,

56123

+ RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },

56124

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,

56125

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },

56126

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,

56127

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },

56128

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,

56129

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,

56130

+ RS6000_BTI_unsigned_V2DI, 0 },

56131

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,

56132

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,

56133

+ RS6000_BTI_bool_V2DI, 0 },

56134

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,

56135

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,

56136

+ RS6000_BTI_unsigned_V2DI, 0 },

56137

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SF,

56138

+ RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },

56139

+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DF,

56140

+ RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },

56141

+

56142

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,

56143

+ RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },

56144

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,

56145

+ RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },

56146

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,

56147

+ RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },

56148

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,

56149

+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI,

56150

+ RS6000_BTI_unsigned_V16QI, 0 },

56151

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,

56152

+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,

56153

+ RS6000_BTI_bool_V16QI, 0 },

56154

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,

56155

+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,

56156

+ RS6000_BTI_unsigned_V16QI, 0 },

56157

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,

56158

+ RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },

56159

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,

56160

+ RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },

56161

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,

56162

+ RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },

56163

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,

56164

+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI,

56165

+ RS6000_BTI_unsigned_V8HI, 0 },

56166

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,

56167

+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,

56168

+ RS6000_BTI_bool_V8HI, 0 },

56169

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,

56170

+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,

56171

+ RS6000_BTI_unsigned_V8HI, 0 },

56172

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,

56173

+ RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },

56174

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,

56175

+ RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },

56176

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,

56177

+ RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },

56178

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,

56179

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI,

56180

+ RS6000_BTI_unsigned_V4SI, 0 },

56181

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,

56182

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,

56183

+ RS6000_BTI_bool_V4SI, 0 },

56184

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,

56185

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,

56186

+ RS6000_BTI_unsigned_V4SI, 0 },

56187

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,

56188

+ RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },

56189

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,

56190

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },

56191

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,

56192

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },

56193

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,

56194

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,

56195

+ RS6000_BTI_unsigned_V2DI, 0 },

56196

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,

56197

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,

56198

+ RS6000_BTI_bool_V2DI, 0 },

56199

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,

56200

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,

56201

+ RS6000_BTI_unsigned_V2DI, 0 },

56202

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SF,

56203

+ RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },

56204

+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DF,

56205

+ RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },

56206

+

56207

+ { P8V_BUILTIN_VEC_VADDCUQ, P8V_BUILTIN_VADDCUQ,

56208

+ RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },

56209

+ { P8V_BUILTIN_VEC_VADDCUQ, P8V_BUILTIN_VADDCUQ,

56210

+ RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,

56211

+ RS6000_BTI_unsigned_V1TI, 0 },

56212

+

56213

+ { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,

56214

+ RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },

56215

+ { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,

56216

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },

56217

+ { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,

56218

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },

56219

+ { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,

56220

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

56221

+ { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,

56222

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },

56223

+ { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,

56224

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

56225

+

56226

+ { P8V_BUILTIN_VEC_VADDUQM, P8V_BUILTIN_VADDUQM,

56227

+ RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },

56228

+ { P8V_BUILTIN_VEC_VADDUQM, P8V_BUILTIN_VADDUQM,

56229

+ RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,

56230

+ RS6000_BTI_unsigned_V1TI, 0 },

56231

+

56232

+ { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,

56233

+ RS6000_BTI_V2DI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },

56234

+ { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,

56235

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI,

56236

+ RS6000_BTI_unsigned_V16QI, 0 },

56237

+

56238

+ { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZB,

56239

+ RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },

56240

+ { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZB,

56241

+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },

56242

+ { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZH,

56243

+ RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },

56244

+ { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZH,

56245

+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },

56246

+ { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZW,

56247

+ RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },

56248

+ { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZW,

56249

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },

56250

+ { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZD,

56251

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },

56252

+ { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZD,

56253

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },

56254

+

56255

+ { P8V_BUILTIN_VEC_VCLZB, P8V_BUILTIN_VCLZB,

56256

+ RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },

56257

+ { P8V_BUILTIN_VEC_VCLZB, P8V_BUILTIN_VCLZB,

56258

+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },

56259

+

56260

+ { P8V_BUILTIN_VEC_VCLZH, P8V_BUILTIN_VCLZH,

56261

+ RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },

56262

+ { P8V_BUILTIN_VEC_VCLZH, P8V_BUILTIN_VCLZH,

56263

+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },

56264

+

56265

+ { P8V_BUILTIN_VEC_VCLZW, P8V_BUILTIN_VCLZW,

56266

+ RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },

56267

+ { P8V_BUILTIN_VEC_VCLZW, P8V_BUILTIN_VCLZW,

56268

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },

56269

+

56270

+ { P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD,

56271

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },

56272

+ { P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD,

56273

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },

56274

+

56275

+ { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,

56276

+ RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },

56277

+ { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,

56278

+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },

56279

+

56280

+ { P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ,

56281

+ RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },

56282

+ { P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ,

56283

+ RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,

56284

+ RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },

56285

+

56286

+ { P8V_BUILTIN_VEC_VADDEUQM, P8V_BUILTIN_VADDEUQM,

56287

+ RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },

56288

+ { P8V_BUILTIN_VEC_VADDEUQM, P8V_BUILTIN_VADDEUQM,

56289

+ RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,

56290

+ RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },

56291

+

56292

+ { P8V_BUILTIN_VEC_VSUBECUQ, P8V_BUILTIN_VSUBECUQ,

56293

+ RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },

56294

+ { P8V_BUILTIN_VEC_VSUBECUQ, P8V_BUILTIN_VSUBECUQ,

56295

+ RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,

56296

+ RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },

56297

+

56298

+ { P8V_BUILTIN_VEC_VSUBEUQM, P8V_BUILTIN_VSUBEUQM,

56299

+ RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },

56300

+ { P8V_BUILTIN_VEC_VSUBEUQM, P8V_BUILTIN_VSUBEUQM,

56301

+ RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,

56302

+ RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },

56303

+

56304

+ { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD,

56305

+ RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },

56306

+ { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD,

56307

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },

56308

+ { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD,

56309

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },

56310

+

56311

+ { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD,

56312

+ RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },

56313

+ { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD,

56314

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },

56315

+ { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD,

56316

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },

56317

+

56318

+ { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD,

56319

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,

56320

+ RS6000_BTI_unsigned_V2DI, 0 },

56321

+ { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD,

56322

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,

56323

+ RS6000_BTI_bool_V2DI, 0 },

56324

+ { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD,

56325

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,

56326

+ RS6000_BTI_unsigned_V2DI, 0 },

56327

+

56328

+ { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD,

56329

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,

56330

+ RS6000_BTI_unsigned_V2DI, 0 },

56331

+ { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD,

56332

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,

56333

+ RS6000_BTI_bool_V2DI, 0 },

56334

+ { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD,

56335

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,

56336

+ RS6000_BTI_unsigned_V2DI, 0 },

56337

+

56338

+ { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW,

56339

+ RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },

56340

+ { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW,

56341

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,

56342

+ RS6000_BTI_unsigned_V4SI, 0 },

56343

+

56344

+ { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW,

56345

+ RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },

56346

+ { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW,

56347

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,

56348

+ RS6000_BTI_unsigned_V4SI, 0 },

56349

+

56350

+ { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTB,

56351

+ RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },

56352

+ { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTB,

56353

+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },

56354

+ { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTH,

56355

+ RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },

56356

+ { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTH,

56357

+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },

56358

+ { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTW,

56359

+ RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },

56360

+ { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTW,

56361

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },

56362

+ { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTD,

56363

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },

56364

+ { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTD,

56365

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },

56366

+

56367

+ { P8V_BUILTIN_VEC_VPOPCNTB, P8V_BUILTIN_VPOPCNTB,

56368

+ RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },

56369

+ { P8V_BUILTIN_VEC_VPOPCNTB, P8V_BUILTIN_VPOPCNTB,

56370

+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },

56371

+

56372

+ { P8V_BUILTIN_VEC_VPOPCNTH, P8V_BUILTIN_VPOPCNTH,

56373

+ RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },

56374

+ { P8V_BUILTIN_VEC_VPOPCNTH, P8V_BUILTIN_VPOPCNTH,

56375

+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },

56376

+

56377

+ { P8V_BUILTIN_VEC_VPOPCNTW, P8V_BUILTIN_VPOPCNTW,

56378

+ RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },

56379

+ { P8V_BUILTIN_VEC_VPOPCNTW, P8V_BUILTIN_VPOPCNTW,

56380

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },

56381

+

56382

+ { P8V_BUILTIN_VEC_VPOPCNTD, P8V_BUILTIN_VPOPCNTD,

56383

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },

56384

+ { P8V_BUILTIN_VEC_VPOPCNTD, P8V_BUILTIN_VPOPCNTD,

56385

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },

56386

+

56387

+ { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM,

56388

+ RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },

56389

+ { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM,

56390

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

56391

+ { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM,

56392

+ RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },

56393

+

56394

+ { P8V_BUILTIN_VEC_VPKSDSS, P8V_BUILTIN_VPKSDSS,

56395

+ RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },

56396

+

56397

+ { P8V_BUILTIN_VEC_VPKUDUS, P8V_BUILTIN_VPKUDUS,

56398

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

56399

+

56400

+ { P8V_BUILTIN_VEC_VPKSDUS, P8V_BUILTIN_VPKSDUS,

56401

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },

56402

+

56403

+ { P8V_BUILTIN_VEC_VRLD, P8V_BUILTIN_VRLD,

56404

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

56405

+ { P8V_BUILTIN_VEC_VRLD, P8V_BUILTIN_VRLD,

56406

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

56407

+

56408

+ { P8V_BUILTIN_VEC_VSLD, P8V_BUILTIN_VSLD,

56409

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

56410

+ { P8V_BUILTIN_VEC_VSLD, P8V_BUILTIN_VSLD,

56411

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

56412

+

56413

+ { P8V_BUILTIN_VEC_VSRD, P8V_BUILTIN_VSRD,

56414

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

56415

+ { P8V_BUILTIN_VEC_VSRD, P8V_BUILTIN_VSRD,

56416

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

56417

+

56418

+ { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRAD,

56419

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

56420

+ { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRD,

56421

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

56422

+

56423

+ { P8V_BUILTIN_VEC_VSUBCUQ, P8V_BUILTIN_VSUBCUQ,

56424

+ RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },

56425

+ { P8V_BUILTIN_VEC_VSUBCUQ, P8V_BUILTIN_VSUBCUQ,

56426

+ RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,

56427

+ RS6000_BTI_unsigned_V1TI, 0 },

56428

+

56429

+ { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,

56430

+ RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },

56431

+ { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,

56432

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },

56433

+ { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,

56434

+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },

56435

+ { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,

56436

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

56437

+ { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,

56438

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },

56439

+ { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,

56440

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },

56441

+

56442

+ { P8V_BUILTIN_VEC_VSUBUQM, P8V_BUILTIN_VSUBUQM,

56443

+ RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },

56444

+ { P8V_BUILTIN_VEC_VSUBUQM, P8V_BUILTIN_VSUBUQM,

56445

+ RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,

56446

+ RS6000_BTI_unsigned_V1TI, 0 },

56447

+

56448

+ { P8V_BUILTIN_VEC_VUPKHSW, P8V_BUILTIN_VUPKHSW,

56449

+ RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },

56450

+ { P8V_BUILTIN_VEC_VUPKHSW, P8V_BUILTIN_VUPKHSW,

56451

+ RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },

56452

+

56453

+ { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW,

56454

+ RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },

56455

+ { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW,

56456

+ RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },

56457

+

56458

+ { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,

56459

+ RS6000_BTI_V16QI, 0, 0, 0 },

56460

+ { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,

56461

+ RS6000_BTI_unsigned_V16QI, 0, 0, 0 },

56462

+

56463

+ /* Crypto builtins. */

56464

+ { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V16QI,

56465

+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,

56466

+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },

56467

+ { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V8HI,

56468

+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,

56469

+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },

56470

+ { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V4SI,

56471

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,

56472

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },

56473

+ { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V2DI,

56474

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,

56475

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },

56476

+

56477

+ { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMB,

56478

+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,

56479

+ RS6000_BTI_unsigned_V16QI, 0 },

56480

+ { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMH,

56481

+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,

56482

+ RS6000_BTI_unsigned_V8HI, 0 },

56483

+ { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMW,

56484

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,

56485

+ RS6000_BTI_unsigned_V4SI, 0 },

56486

+ { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMD,

56487

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,

56488

+ RS6000_BTI_unsigned_V2DI, 0 },

56489

+

56490

+ { CRYPTO_BUILTIN_VSHASIGMA, CRYPTO_BUILTIN_VSHASIGMAW,

56491

+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,

56492

+ RS6000_BTI_INTSI, RS6000_BTI_INTSI },

56493

+ { CRYPTO_BUILTIN_VSHASIGMA, CRYPTO_BUILTIN_VSHASIGMAD,

56494

+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,

56495

+ RS6000_BTI_INTSI, RS6000_BTI_INTSI },

56496

+

56497

{ (enum rs6000_builtins) 0, (enum rs6000_builtins) 0, 0, 0, 0, 0 }

56498

};

56499

56500

@@ -3560,6 +4224,10 @@

56501

unsigned_p = TYPE_UNSIGNED (type);

56502

switch (TYPE_MODE (type))

56503

{

56504

+ case TImode:

56505

+ type = (unsigned_p ? unsigned_V1TI_type_node : V1TI_type_node);

56506

+ size = 1;

56507

+ break;

56508

case DImode:

56509

type = (unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node);

56510

size = 2;

56511

@@ -3591,7 +4259,7 @@

56512

return build_constructor (type, vec);

56513

}

56514

56515

- /* For now use pointer tricks to do the extaction, unless we are on VSX

56516

+ /* For now use pointer tricks to do the extraction, unless we are on VSX

56517

extracting a double from a constant offset. */

56518

if (fcode == ALTIVEC_BUILTIN_VEC_EXTRACT)

56519

{

56520

@@ -3619,6 +4287,17 @@

56521

if (!INTEGRAL_TYPE_P (TREE_TYPE (arg2)))

56522

goto bad;

56523

56524

+ /* If we are targeting little-endian, but -maltivec=be has been

56525

+ specified to override the element order, adjust the element

56526

+ number accordingly. */

56527

+ if (!BYTES_BIG_ENDIAN && rs6000_altivec_element_order == 2)

56528

+ {

56529

+ unsigned int last_elem = TYPE_VECTOR_SUBPARTS (arg1_type) - 1;

56530

+ arg2 = fold_build2_loc (loc, MINUS_EXPR, TREE_TYPE (arg2),

56531

+ build_int_cstu (TREE_TYPE (arg2), last_elem),

56532

+ arg2);

56533

+ }

56534

+

56535

/* If we can use the VSX xxpermdi instruction, use that for extract. */

56536

mode = TYPE_MODE (arg1_type);

56537

if ((mode == V2DFmode || mode == V2DImode) && VECTOR_MEM_VSX_P (mode)

56538

@@ -3636,6 +4315,14 @@

56539

if (call)

56540

return build_call_expr (call, 2, arg1, arg2);

56541

}

56542

+ else if (mode == V1TImode && VECTOR_MEM_VSX_P (mode)

56543

+ && TREE_CODE (arg2) == INTEGER_CST

56544

+ && TREE_INT_CST_HIGH (arg2) == 0

56545

+ && TREE_INT_CST_LOW (arg2) == 0)

56546

+ {

56547

+ tree call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V1TI];

56548

+ return build_call_expr (call, 2, arg1, arg2);

56549

+ }

56550

56551

/* Build *(((arg1_inner_type*)&(vector type){arg1})+arg2). */

56552

arg1_inner_type = TREE_TYPE (arg1_type);

56553

@@ -3666,7 +4353,7 @@

56554

return stmt;

56555

}

56556

56557

- /* For now use pointer tricks to do the insertation, unless we are on VSX

56558

+ /* For now use pointer tricks to do the insertion, unless we are on VSX

56559

inserting a double to a constant offset.. */

56560

if (fcode == ALTIVEC_BUILTIN_VEC_INSERT)

56561

{

56562

@@ -3696,6 +4383,17 @@

56563

if (!INTEGRAL_TYPE_P (TREE_TYPE (arg2)))

56564

goto bad;

56565

56566

+ /* If we are targeting little-endian, but -maltivec=be has been

56567

+ specified to override the element order, adjust the element

56568

+ number accordingly. */

56569

+ if (!BYTES_BIG_ENDIAN && rs6000_altivec_element_order == 2)

56570

+ {

56571

+ unsigned int last_elem = TYPE_VECTOR_SUBPARTS (arg1_type) - 1;

56572

+ arg2 = fold_build2_loc (loc, MINUS_EXPR, TREE_TYPE (arg2),

56573

+ build_int_cstu (TREE_TYPE (arg2), last_elem),

56574

+ arg2);

56575

+ }

56576

+

56577

/* If we can use the VSX xxpermdi instruction, use that for insert. */

56578

mode = TYPE_MODE (arg1_type);

56579

if ((mode == V2DFmode || mode == V2DImode) && VECTOR_UNIT_VSX_P (mode)

56580

@@ -3715,7 +4413,18 @@

56581

if (call)

56582

return build_call_expr (call, 3, arg1, arg0, arg2);

56583

}

56584

+ else if (mode == V1TImode && VECTOR_UNIT_VSX_P (mode)

56585

+ && TREE_CODE (arg2) == INTEGER_CST

56586

+ && TREE_INT_CST_HIGH (arg2) == 0

56587

+ && TREE_INT_CST_LOW (arg2) == 0)

56588

+ {

56589

+ tree call = rs6000_builtin_decls[VSX_BUILTIN_VEC_SET_V1TI];

56590

56591

+ /* Note, __builtin_vec_insert_<xxx> has vector and scalar types

56592

+ reversed. */

56593

+ return build_call_expr (call, 3, arg1, arg0, arg2);

56594

+ }

56595

+

56596

/* Build *(((arg1_inner_type*)&(vector type){arg1})+arg2) = arg0. */

56597

arg1_inner_type = TREE_TYPE (arg1_type);

56598

arg2 = build_binary_op (loc, BIT_AND_EXPR, arg2,

56599

@@ -3824,7 +4533,8 @@

56600

&& (desc->op2 == RS6000_BTI_NOT_OPAQUE

56601

|| rs6000_builtin_type_compatible (types[1], desc->op2))

56602

&& (desc->op3 == RS6000_BTI_NOT_OPAQUE

56603

- || rs6000_builtin_type_compatible (types[2], desc->op3)))

56604

+ || rs6000_builtin_type_compatible (types[2], desc->op3))

56605

+ && rs6000_builtin_decls[desc->overloaded_code] != NULL_TREE)

56606

return altivec_build_resolved_builtin (args, n, desc);

56607

56608

bad:

56609

Index: gcc/config/rs6000/rs6000.opt

56610

===================================================================

56611

--- a/src/gcc/config/rs6000/rs6000.opt (.../tags/gcc_4_8_2_release)

56612

+++ b/src/gcc/config/rs6000/rs6000.opt (.../branches/gcc-4_8-branch)

56613

@@ -1,6 +1,6 @@

56614

; Options for the rs6000 port of the compiler

56615

;

56616

56617

56618

; Contributed by Aldy Hernandez <aldy@quesejoda.com>.

56619

;

56620

; This file is part of GCC.

56621

@@ -137,6 +137,14 @@

56622

Target Report Mask(ALTIVEC) Var(rs6000_isa_flags)

56623

Use AltiVec instructions

56624

56625

+maltivec=le

56626

+Target Report RejectNegative Var(rs6000_altivec_element_order, 1) Save

56627

+Generate Altivec instructions using little-endian element order

56628

+

56629

+maltivec=be

56630

+Target Report RejectNegative Var(rs6000_altivec_element_order, 2)

56631

+Generate Altivec instructions using big-endian element order

56632

+

56633

mhard-dfp

56634

Target Report Mask(DFP) Var(rs6000_isa_flags)

56635

Use decimal floating point instructions

56636

@@ -181,13 +189,16 @@

56637

Target Report Mask(VSX) Var(rs6000_isa_flags)

56638

Use vector/scalar (VSX) instructions

56639

56640

+mvsx-scalar-float

56641

+Target Undocumented Report Var(TARGET_VSX_SCALAR_FLOAT) Init(1)

56642

+; If -mpower8-vector, use VSX arithmetic instructions for SFmode (on by default)

56643

+

56644

mvsx-scalar-double

56645

-Target Undocumented Report Var(TARGET_VSX_SCALAR_DOUBLE) Init(-1)

56646

-; If -mvsx, use VSX arithmetic instructions for scalar double (on by default)

56647

+Target Undocumented Report Var(TARGET_VSX_SCALAR_DOUBLE) Init(1)

56648

+; If -mvsx, use VSX arithmetic instructions for DFmode (on by default)

56649

56650

mvsx-scalar-memory

56651

-Target Undocumented Report Var(TARGET_VSX_SCALAR_MEMORY)

56652

-; If -mvsx, use VSX scalar memory reference instructions for scalar double (off by default)

56653

+Target Undocumented Report Alias(mupper-regs-df)

56654

56655

mvsx-align-128

56656

Target Undocumented Report Var(TARGET_VSX_ALIGN_128)

56657

@@ -363,6 +374,14 @@

56658

Target RejectNegative Var(rs6000_spe_abi, 0)

56659

Do not use the SPE ABI extensions

56660

56661

+mabi=elfv1

56662

+Target RejectNegative Var(rs6000_elf_abi, 1) Save

56663

+Use the ELFv1 ABI

56664

+

56665

+mabi=elfv2

56666

+Target RejectNegative Var(rs6000_elf_abi, 2)

56667

+Use the ELFv2 ABI

56668

+

56669

; These are here for testing during development only, do not document

56670

; in the manual please.

56671

56672

@@ -443,6 +462,10 @@

56673

Target RejectNegative Joined UInteger Var(rs6000_long_double_type_size) Save

56674

-mlong-double-<n> Specify size of long double (64 or 128 bits)

56675

56676

+mlra

56677

+Target Report Var(rs6000_lra_flag) Init(0) Save

56678

+Use LRA instead of reload

56679

+

56680

msched-costly-dep=

56681

Target RejectNegative Joined Var(rs6000_sched_costly_dep_str)

56682

Determine which dependences between insns are considered costly

56683

@@ -514,3 +537,51 @@

56684

msave-toc-indirect

56685

Target Report Var(TARGET_SAVE_TOC_INDIRECT) Save

56686

Control whether we save the TOC in the prologue for indirect calls or generate the save inline

56687

+

56688

+mvsx-timode

56689

+Target Undocumented Mask(VSX_TIMODE) Var(rs6000_isa_flags)

56690

+Allow 128-bit integers in VSX registers

56691

+

56692

+mpower8-fusion

56693

+Target Report Mask(P8_FUSION) Var(rs6000_isa_flags)

56694

+Fuse certain integer operations together for better performance on power8

56695

+

56696

+mpower8-fusion-sign

56697

+Target Undocumented Mask(P8_FUSION_SIGN) Var(rs6000_isa_flags)

56698

+Allow sign extension in fusion operations

56699

+

56700

+mpower8-vector

56701

+Target Report Mask(P8_VECTOR) Var(rs6000_isa_flags)

56702

+Use/do not use vector and scalar instructions added in ISA 2.07.

56703

+

56704

+mcrypto

56705

+Target Report Mask(CRYPTO) Var(rs6000_isa_flags)

56706

+Use ISA 2.07 crypto instructions

56707

+

56708

+mdirect-move

56709

+Target Report Mask(DIRECT_MOVE) Var(rs6000_isa_flags)

56710

+Use ISA 2.07 direct move between GPR & VSX register instructions

56711

+

56712

+mhtm

56713

+Target Report Mask(HTM) Var(rs6000_isa_flags)

56714

+Use ISA 2.07 transactional memory (HTM) instructions

56715

+

56716

+mquad-memory

56717

+Target Report Mask(QUAD_MEMORY) Var(rs6000_isa_flags)

56718

+Generate the quad word memory instructions (lq/stq).

56719

+

56720

+mquad-memory-atomic

56721

+Target Report Mask(QUAD_MEMORY_ATOMIC) Var(rs6000_isa_flags)

56722

+Generate the quad word memory atomic instructions (lqarx/stqcx).

56723

+

56724

+mcompat-align-parm

56725

+Target Report Var(rs6000_compat_align_parm) Init(1) Save

56726

+Generate aggregate parameter passing code with at most 64-bit alignment.

56727

+

56728

+mupper-regs-df

56729

+Target Undocumented Mask(UPPER_REGS_DF) Var(rs6000_isa_flags)

56730

+Allow double variables in upper registers with -mcpu=power7 or -mvsx

56731

+

56732

+mupper-regs-sf

56733

+Target Undocumented Mask(UPPER_REGS_SF) Var(rs6000_isa_flags)

56734

+Allow float variables in upper registers with -mcpu=power8 or -mp8-vector

56735

Index: gcc/config/rs6000/linux64.h

56736

===================================================================

56737

--- a/src/gcc/config/rs6000/linux64.h (.../tags/gcc_4_8_2_release)

56738

+++ b/src/gcc/config/rs6000/linux64.h (.../branches/gcc-4_8-branch)

56739

@@ -25,9 +25,6 @@

56740

56741

#ifndef RS6000_BI_ARCH

56742

56743

-#undef DEFAULT_ABI

56744

-#define DEFAULT_ABI ABI_AIX

56745

-

56746

#undef TARGET_64BIT

56747

#define TARGET_64BIT 1

56748

56749

@@ -74,7 +71,11 @@

56750

#undef PROCESSOR_DEFAULT

56751

#define PROCESSOR_DEFAULT PROCESSOR_POWER7

56752

#undef PROCESSOR_DEFAULT64

56753

+#ifdef LINUX64_DEFAULT_ABI_ELFv2

56754

+#define PROCESSOR_DEFAULT64 PROCESSOR_POWER8

56755

+#else

56756

#define PROCESSOR_DEFAULT64 PROCESSOR_POWER7

56757

+#endif

56758

56759

/* We don't need to generate entries in .fixup, except when

56760

-mrelocatable or -mrelocatable-lib is given. */

56761

@@ -88,6 +89,12 @@

56762

#define INVALID_64BIT "-m%s not supported in this configuration"

56763

#define INVALID_32BIT INVALID_64BIT

56764

56765

+#ifdef LINUX64_DEFAULT_ABI_ELFv2

56766

+#define ELFv2_ABI_CHECK (rs6000_elf_abi != 1)

56767

+#else

56768

+#define ELFv2_ABI_CHECK (rs6000_elf_abi == 2)

56769

+#endif

56770

+

56771

#undef SUBSUBTARGET_OVERRIDE_OPTIONS

56772

#define SUBSUBTARGET_OVERRIDE_OPTIONS \

56773

do \

56774

@@ -102,6 +109,12 @@

56775

error (INVALID_64BIT, "call"); \

56776

} \

56777

dot_symbols = !strcmp (rs6000_abi_name, "aixdesc"); \

56778

+ if (ELFv2_ABI_CHECK) \

56779

+ { \

56780

+ rs6000_current_abi = ABI_ELFv2; \

56781

+ if (dot_symbols) \

56782

+ error ("-mcall-aixdesc incompatible with -mabi=elfv2"); \

56783

+ } \

56784

if (rs6000_isa_flags & OPTION_MASK_RELOCATABLE) \

56785

{ \

56786

rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE; \

56787

@@ -136,8 +149,11 @@

56788

SET_CMODEL (CMODEL_MEDIUM); \

56789

if (rs6000_current_cmodel != CMODEL_SMALL) \

56790

{ \

56791

- TARGET_NO_FP_IN_TOC = 0; \

56792

- TARGET_NO_SUM_IN_TOC = 0; \

56793

+ if (!global_options_set.x_TARGET_NO_FP_IN_TOC) \

56794

+ TARGET_NO_FP_IN_TOC \

56795

+ = rs6000_current_cmodel == CMODEL_MEDIUM; \

56796

+ if (!global_options_set.x_TARGET_NO_SUM_IN_TOC) \

56797

+ TARGET_NO_SUM_IN_TOC = 0; \

56798

} \

56799

} \

56800

} \

56801

@@ -351,7 +367,11 @@

56802

#define LINK_OS_DEFAULT_SPEC "%(link_os_linux)"

56803

56804

#define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1"

56805

-#define GLIBC_DYNAMIC_LINKER64 "/lib64/ld64.so.1"

56806

+#ifdef LINUX64_DEFAULT_ABI_ELFv2

56807

+#define GLIBC_DYNAMIC_LINKER64 "%{mabi=elfv1:/lib64/ld64.so.1;:/lib64/ld64.so.2}"

56808

+#else

56809

+#define GLIBC_DYNAMIC_LINKER64 "%{mabi=elfv2:/lib64/ld64.so.2;:/lib64/ld64.so.1}"

56810

+#endif

56811

#define UCLIBC_DYNAMIC_LINKER32 "/lib/ld-uClibc.so.0"

56812

#define UCLIBC_DYNAMIC_LINKER64 "/lib/ld64-uClibc.so.0"

56813

#if DEFAULT_LIBC == LIBC_UCLIBC

56814

Index: gcc/config/rs6000/darwin.h

56815

===================================================================

56816

--- a/src/gcc/config/rs6000/darwin.h (.../tags/gcc_4_8_2_release)

56817

+++ b/src/gcc/config/rs6000/darwin.h (.../branches/gcc-4_8-branch)

56818

@@ -205,7 +205,8 @@

56819

"v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", \

56820

"vrsave", "vscr", \

56821

"spe_acc", "spefscr", \

56822

- "sfp" \

56823

+ "sfp", \

56824

+ "tfhar", "tfiar", "texasr" \

56825

}

56826

56827

/* This outputs NAME to FILE. */

56828

Index: gcc/config/rs6000/rs6000.c

56829

===================================================================

56830

--- a/src/gcc/config/rs6000/rs6000.c (.../tags/gcc_4_8_2_release)

56831

+++ b/src/gcc/config/rs6000/rs6000.c (.../branches/gcc-4_8-branch)

56832

@@ -1,5 +1,5 @@

56833

/* Subroutines used for code generation on IBM RS/6000.

56834

56835

56836

Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)

56837

56838

This file is part of GCC.

56839

@@ -56,6 +56,7 @@

56840

#include "intl.h"

56841

#include "params.h"

56842

#include "tm-constrs.h"

56843

+#include "ira.h"

56844

#include "opts.h"

56845

#include "tree-vectorizer.h"

56846

#include "dumpfile.h"

56847

@@ -96,6 +97,7 @@

56848

int spe_gp_save_offset; /* offset to save spe 64-bit gprs */

56849

int varargs_save_offset; /* offset to save the varargs registers */

56850

int ehrd_offset; /* offset to EH return data */

56851

+ int ehcr_offset; /* offset to EH CR field data */

56852

int reg_size; /* register size (4 or 8) */

56853

HOST_WIDE_INT vars_size; /* variable save area size */

56854

int parm_size; /* outgoing parameter size */

56855

@@ -139,6 +141,8 @@

56856

64-bits wide and is allocated early enough so that the offset

56857

does not overflow the 16-bit load/store offset field. */

56858

rtx sdmode_stack_slot;

56859

+ /* Flag if r2 setup is needed with ELFv2 ABI. */

56860

+ bool r2_setup_needed;

56861

} machine_function;

56862

56863

/* Support targetm.vectorize.builtin_mask_for_load. */

56864

@@ -189,9 +193,6 @@

56865

/* Map register number to register class. */

56866

enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER];

56867

56868

-/* Reload functions based on the type and the vector unit. */

56869

-static enum insn_code rs6000_vector_reload[NUM_MACHINE_MODES][2];

56870

-

56871

static int dbg_cost_ctrl;

56872

56873

/* Built in types. */

56874

@@ -289,6 +290,105 @@

56875

don't link in rs6000-c.c, so we can't call it directly. */

56876

void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT, HOST_WIDE_INT);

56877

56878

+/* Simplfy register classes into simpler classifications. We assume

56879

+ GPR_REG_TYPE - FPR_REG_TYPE are ordered so that we can use a simple range

56880

+ check for standard register classes (gpr/floating/altivec/vsx) and

56881

+ floating/vector classes (float/altivec/vsx). */

56882

+

56883

+enum rs6000_reg_type {

56884

+ NO_REG_TYPE,

56885

+ PSEUDO_REG_TYPE,

56886

+ GPR_REG_TYPE,

56887

+ VSX_REG_TYPE,

56888

+ ALTIVEC_REG_TYPE,

56889

+ FPR_REG_TYPE,

56890

+ SPR_REG_TYPE,

56891

+ CR_REG_TYPE,

56892

+ SPE_ACC_TYPE,

56893

+ SPEFSCR_REG_TYPE

56894

+};

56895

+

56896

+/* Map register class to register type. */

56897

+static enum rs6000_reg_type reg_class_to_reg_type[N_REG_CLASSES];

56898

+

56899

+/* First/last register type for the 'normal' register types (i.e. general

56900

+ purpose, floating point, altivec, and VSX registers). */

56901

+#define IS_STD_REG_TYPE(RTYPE) IN_RANGE(RTYPE, GPR_REG_TYPE, FPR_REG_TYPE)

56902

+

56903

+#define IS_FP_VECT_REG_TYPE(RTYPE) IN_RANGE(RTYPE, VSX_REG_TYPE, FPR_REG_TYPE)

56904

+

56905

+

56906

+/* Register classes we care about in secondary reload or go if legitimate

56907

+ address. We only need to worry about GPR, FPR, and Altivec registers here,

56908

+ along an ANY field that is the OR of the 3 register classes. */

56909

+

56910

+enum rs6000_reload_reg_type {

56911

+ RELOAD_REG_GPR, /* General purpose registers. */

56912

+ RELOAD_REG_FPR, /* Traditional floating point regs. */

56913

+ RELOAD_REG_VMX, /* Altivec (VMX) registers. */

56914

+ RELOAD_REG_ANY, /* OR of GPR, FPR, Altivec masks. */

56915

+ N_RELOAD_REG

56916

+};

56917

+

56918

+/* For setting up register classes, loop through the 3 register classes mapping

56919

+ into real registers, and skip the ANY class, which is just an OR of the

56920

+ bits. */

56921

+#define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR

56922

+#define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX

56923

+

56924

+/* Map reload register type to a register in the register class. */

56925

+struct reload_reg_map_type {

56926

+ const char *name; /* Register class name. */

56927

+ int reg; /* Register in the register class. */

56928

+};

56929

+

56930

+static const struct reload_reg_map_type reload_reg_map[N_RELOAD_REG] = {

56931

+ { "Gpr", FIRST_GPR_REGNO }, /* RELOAD_REG_GPR. */

56932

+ { "Fpr", FIRST_FPR_REGNO }, /* RELOAD_REG_FPR. */

56933

+ { "VMX", FIRST_ALTIVEC_REGNO }, /* RELOAD_REG_VMX. */

56934

+ { "Any", -1 }, /* RELOAD_REG_ANY. */

56935

+};

56936

+

56937

+/* Mask bits for each register class, indexed per mode. Historically the

56938

+ compiler has been more restrictive which types can do PRE_MODIFY instead of

56939

+ PRE_INC and PRE_DEC, so keep track of sepaate bits for these two. */

56940

+typedef unsigned char addr_mask_type;

56941

+

56942

+#define RELOAD_REG_VALID 0x01 /* Mode valid in register.. */

56943

+#define RELOAD_REG_MULTIPLE 0x02 /* Mode takes multiple registers. */

56944

+#define RELOAD_REG_INDEXED 0x04 /* Reg+reg addressing. */

56945

+#define RELOAD_REG_OFFSET 0x08 /* Reg+offset addressing. */

56946

+#define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */

56947

+#define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */

56948

+

56949

+/* Register type masks based on the type, of valid addressing modes. */

56950

+struct rs6000_reg_addr {

56951

+ enum insn_code reload_load; /* INSN to reload for loading. */

56952

+ enum insn_code reload_store; /* INSN to reload for storing. */

56953

+ enum insn_code reload_fpr_gpr; /* INSN to move from FPR to GPR. */

56954

+ enum insn_code reload_gpr_vsx; /* INSN to move from GPR to VSX. */

56955

+ enum insn_code reload_vsx_gpr; /* INSN to move from VSX to GPR. */

56956

+ addr_mask_type addr_mask[(int)N_RELOAD_REG]; /* Valid address masks. */

56957

+};

56958

+

56959

+static struct rs6000_reg_addr reg_addr[NUM_MACHINE_MODES];

56960

+

56961

+/* Helper function to say whether a mode supports PRE_INC or PRE_DEC. */

56962

+static inline bool

56963

+mode_supports_pre_incdec_p (enum machine_mode mode)

56964

+{

56965

+ return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_INCDEC)

56966

+ != 0);

56967

+}

56968

+

56969

+/* Helper function to say whether a mode supports PRE_MODIFY. */

56970

+static inline bool

56971

+mode_supports_pre_modify_p (enum machine_mode mode)

56972

+{

56973

+ return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY)

56974

+ != 0);

56975

+}

56976

+

56977

56978

/* Target cpu costs. */

56979

56980

@@ -828,6 +928,25 @@

56981

12, /* prefetch streams */

56982

};

56983

56984

+/* Instruction costs on POWER8 processors. */

56985

+static const

56986

+struct processor_costs power8_cost = {

56987

+ COSTS_N_INSNS (3), /* mulsi */

56988

+ COSTS_N_INSNS (3), /* mulsi_const */

56989

+ COSTS_N_INSNS (3), /* mulsi_const9 */

56990

+ COSTS_N_INSNS (3), /* muldi */

56991

+ COSTS_N_INSNS (19), /* divsi */

56992

+ COSTS_N_INSNS (35), /* divdi */

56993

+ COSTS_N_INSNS (3), /* fp */

56994

+ COSTS_N_INSNS (3), /* dmul */

56995

+ COSTS_N_INSNS (14), /* sdiv */

56996

+ COSTS_N_INSNS (17), /* ddiv */

56997

+ 128, /* cache line size */

56998

+ 32, /* l1 cache */

56999

+ 256, /* l2 cache */

57000

+ 12, /* prefetch streams */

57001

+};

57002

+

57003

/* Instruction costs on POWER A2 processors. */

57004

static const

57005

struct processor_costs ppca2_cost = {

57006

@@ -855,6 +974,7 @@

57007

#undef RS6000_BUILTIN_A

57008

#undef RS6000_BUILTIN_D

57009

#undef RS6000_BUILTIN_E

57010

+#undef RS6000_BUILTIN_H

57011

#undef RS6000_BUILTIN_P

57012

#undef RS6000_BUILTIN_Q

57013

#undef RS6000_BUILTIN_S

57014

@@ -878,6 +998,9 @@

57015

#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \

57016

{ NAME, ICODE, MASK, ATTR },

57017

57018

+#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \

57019

+ { NAME, ICODE, MASK, ATTR },

57020

+

57021

#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \

57022

{ NAME, ICODE, MASK, ATTR },

57023

57024

@@ -908,6 +1031,7 @@

57025

#undef RS6000_BUILTIN_A

57026

#undef RS6000_BUILTIN_D

57027

#undef RS6000_BUILTIN_E

57028

+#undef RS6000_BUILTIN_H

57029

#undef RS6000_BUILTIN_P

57030

#undef RS6000_BUILTIN_Q

57031

#undef RS6000_BUILTIN_S

57032

@@ -948,6 +1072,7 @@

57033

static void paired_init_builtins (void);

57034

static rtx paired_expand_predicate_builtin (enum insn_code, tree, rtx);

57035

static void spe_init_builtins (void);

57036

+static void htm_init_builtins (void);

57037

static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);

57038

static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);

57039

static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);

57040

@@ -1020,6 +1145,13 @@

57041

static void rs6000_print_builtin_options (FILE *, int, const char *,

57042

HOST_WIDE_INT);

57043

57044

+static enum rs6000_reg_type register_to_reg_type (rtx, bool *);

57045

+static bool rs6000_secondary_reload_move (enum rs6000_reg_type,

57046

+ enum rs6000_reg_type,

57047

+ enum machine_mode,

57048

+ secondary_reload_info *,

57049

+ bool);

57050

+

57051

/* Hash table stuff for keeping track of TOC entries. */

57052

57053

struct GTY(()) toc_hash_struct

57054

@@ -1068,7 +1200,9 @@

57055

/* SPE registers. */

57056

"spe_acc", "spefscr",

57057

/* Soft frame pointer. */

57058

- "sfp"

57059

+ "sfp",

57060

+ /* HTM SPR registers. */

57061

+ "tfhar", "tfiar", "texasr"

57062

};

57063

57064

#ifdef TARGET_REGNAMES

57065

@@ -1094,7 +1228,9 @@

57066

/* SPE registers. */

57067

"spe_acc", "spefscr",

57068

/* Soft frame pointer. */

57069

- "sfp"

57070

+ "sfp",

57071

+ /* HTM SPR registers. */

57072

+ "tfhar", "tfiar", "texasr"

57073

};

57074

#endif

57075

57076

@@ -1316,6 +1452,9 @@

57077

#undef TARGET_RETURN_IN_MEMORY

57078

#define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory

57079

57080

+#undef TARGET_RETURN_IN_MSB

57081

+#define TARGET_RETURN_IN_MSB rs6000_return_in_msb

57082

+

57083

#undef TARGET_SETUP_INCOMING_VARARGS

57084

#define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs

57085

57086

@@ -1425,6 +1564,9 @@

57087

#undef TARGET_MODE_DEPENDENT_ADDRESS_P

57088

#define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p

57089

57090

+#undef TARGET_LRA_P

57091

+#define TARGET_LRA_P rs6000_lra_p

57092

+

57093

#undef TARGET_CAN_ELIMINATE

57094

#define TARGET_CAN_ELIMINATE rs6000_can_eliminate

57095

57096

@@ -1513,8 +1655,9 @@

57097

{

57098

unsigned HOST_WIDE_INT reg_size;

57099

57100

+ /* TF/TD modes are special in that they always take 2 registers. */

57101

if (FP_REGNO_P (regno))

57102

- reg_size = (VECTOR_MEM_VSX_P (mode)

57103

+ reg_size = ((VECTOR_MEM_VSX_P (mode) && mode != TDmode && mode != TFmode)

57104

? UNITS_PER_VSX_WORD

57105

: UNITS_PER_FP_WORD);

57106

57107

@@ -1546,16 +1689,39 @@

57108

{

57109

int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1;

57110

57111

+ /* PTImode can only go in GPRs. Quad word memory operations require even/odd

57112

+ register combinations, and use PTImode where we need to deal with quad

57113

+ word memory operations. Don't allow quad words in the argument or frame

57114

+ pointer registers, just registers 0..31. */

57115

+ if (mode == PTImode)

57116

+ return (IN_RANGE (regno, FIRST_GPR_REGNO, LAST_GPR_REGNO)

57117

+ && IN_RANGE (last_regno, FIRST_GPR_REGNO, LAST_GPR_REGNO)

57118

+ && ((regno & 1) == 0));

57119

+

57120

/* VSX registers that overlap the FPR registers are larger than for non-VSX

57121

implementations. Don't allow an item to be split between a FP register

57122

- and an Altivec register. */

57123

- if (VECTOR_MEM_VSX_P (mode))

57124

+ and an Altivec register. Allow TImode in all VSX registers if the user

57125

+ asked for it. */

57126

+ if (TARGET_VSX && VSX_REGNO_P (regno)

57127

+ && (VECTOR_MEM_VSX_P (mode)

57128

+ || (TARGET_VSX_SCALAR_FLOAT && mode == SFmode)

57129

+ || (TARGET_VSX_SCALAR_DOUBLE && (mode == DFmode || mode == DImode))

57130

+ || (TARGET_VSX_TIMODE && mode == TImode)

57131

+ || (TARGET_VADDUQM && mode == V1TImode)))

57132

{

57133

if (FP_REGNO_P (regno))

57134

return FP_REGNO_P (last_regno);

57135

57136

if (ALTIVEC_REGNO_P (regno))

57137

- return ALTIVEC_REGNO_P (last_regno);

57138

+ {

57139

+ if (mode == SFmode && !TARGET_UPPER_REGS_SF)

57140

+ return 0;

57141

+

57142

+ if ((mode == DFmode || mode == DImode) && !TARGET_UPPER_REGS_DF)

57143

+ return 0;

57144

+

57145

+ return ALTIVEC_REGNO_P (last_regno);

57146

+ }

57147

}

57148

57149

/* The GPRs can hold any mode, but values bigger than one register

57150

@@ -1564,8 +1730,7 @@

57151

return INT_REGNO_P (last_regno);

57152

57153

/* The float registers (except for VSX vector modes) can only hold floating

57154

- modes and DImode. This excludes the 32-bit decimal float mode for

57155

- now. */

57156

+ modes and DImode. */

57157

if (FP_REGNO_P (regno))

57158

{

57159

if (SCALAR_FLOAT_MODE_P (mode)

57160

@@ -1593,15 +1758,15 @@

57161

57162

/* AltiVec only in AldyVec registers. */

57163

if (ALTIVEC_REGNO_P (regno))

57164

- return VECTOR_MEM_ALTIVEC_OR_VSX_P (mode);

57165

+ return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)

57166

+ || mode == V1TImode);

57167

57168

/* ...but GPRs can hold SIMD data on the SPE in one register. */

57169

if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))

57170

return 1;

57171

57172

- /* We cannot put TImode anywhere except general register and it must be able

57173

- to fit within the register set. In the future, allow TImode in the

57174

- Altivec or VSX registers. */

57175

+ /* We cannot put non-VSX TImode or PTImode anywhere except general register

57176

+ and it must be able to fit within the register set. */

57177

57178

return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;

57179

}

57180

@@ -1674,10 +1839,77 @@

57181

comma = "";

57182

}

57183

57184

+ len += fprintf (stderr, "%sreg-class = %s", comma,

57185

+ reg_class_names[(int)rs6000_regno_regclass[r]]);

57186

+ comma = ", ";

57187

+

57188

+ if (len > 70)

57189

+ {

57190

+ fprintf (stderr, ",\n\t");

57191

+ comma = "";

57192

+ }

57193

+

57194

fprintf (stderr, "%sregno = %d\n", comma, r);

57195

}

57196

}

57197

57198

+static const char *

57199

+rs6000_debug_vector_unit (enum rs6000_vector v)

57200

+{

57201

+ const char *ret;

57202

+

57203

+ switch (v)

57204

+ {

57205

+ case VECTOR_NONE: ret = "none"; break;

57206

+ case VECTOR_ALTIVEC: ret = "altivec"; break;

57207

+ case VECTOR_VSX: ret = "vsx"; break;

57208

+ case VECTOR_P8_VECTOR: ret = "p8_vector"; break;

57209

+ case VECTOR_PAIRED: ret = "paired"; break;

57210

+ case VECTOR_SPE: ret = "spe"; break;

57211

+ case VECTOR_OTHER: ret = "other"; break;

57212

+ default: ret = "unknown"; break;

57213

+ }

57214

+

57215

+ return ret;

57216

+}

57217

+

57218

+/* Print the address masks in a human readble fashion. */

57219

+DEBUG_FUNCTION void

57220

+rs6000_debug_print_mode (ssize_t m)

57221

+{

57222

+ ssize_t rc;

57223

+

57224

+ fprintf (stderr, "Mode: %-5s", GET_MODE_NAME (m));

57225

+ for (rc = 0; rc < N_RELOAD_REG; rc++)

57226

+ {

57227

+ addr_mask_type mask = reg_addr[m].addr_mask[rc];

57228

+ fprintf (stderr,

57229

+ " %s: %c%c%c%c%c%c",

57230

+ reload_reg_map[rc].name,

57231

+ (mask & RELOAD_REG_VALID) != 0 ? 'v' : ' ',

57232

+ (mask & RELOAD_REG_MULTIPLE) != 0 ? 'm' : ' ',

57233

+ (mask & RELOAD_REG_INDEXED) != 0 ? 'i' : ' ',

57234

+ (mask & RELOAD_REG_OFFSET) != 0 ? 'o' : ' ',

57235

+ (mask & RELOAD_REG_PRE_INCDEC) != 0 ? '+' : ' ',

57236

+ (mask & RELOAD_REG_PRE_MODIFY) != 0 ? '+' : ' ');

57237

+ }

57238

+

57239

+ if (rs6000_vector_unit[m] != VECTOR_NONE

57240

+ || rs6000_vector_mem[m] != VECTOR_NONE

57241

+ || (reg_addr[m].reload_store != CODE_FOR_nothing)

57242

+ || (reg_addr[m].reload_load != CODE_FOR_nothing))

57243

+ {

57244

+ fprintf (stderr,

57245

+ " Vector-arith=%-10s Vector-mem=%-10s Reload=%c%c",

57246

+ rs6000_debug_vector_unit (rs6000_vector_unit[m]),

57247

+ rs6000_debug_vector_unit (rs6000_vector_mem[m]),

57248

+ (reg_addr[m].reload_store != CODE_FOR_nothing) ? 's' : '*',

57249

+ (reg_addr[m].reload_load != CODE_FOR_nothing) ? 'l' : '*');

57250

+ }

57251

+

57252

+ fputs ("\n", stderr);

57253

+}

57254

+

57255

#define DEBUG_FMT_ID "%-32s= "

57256

#define DEBUG_FMT_D DEBUG_FMT_ID "%d\n"

57257

#define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: "

57258

@@ -1690,6 +1922,7 @@

57259

static const char *const tf[2] = { "false", "true" };

57260

const char *nl = (const char *)0;

57261

int m;

57262

+ size_t m1, m2, v;

57263

char costly_num[20];

57264

char nop_num[20];

57265

char flags_buffer[40];

57266

@@ -1700,20 +1933,69 @@

57267

const char *cmodel_str;

57268

struct cl_target_option cl_opts;

57269

57270

- /* Map enum rs6000_vector to string. */

57271

- static const char *rs6000_debug_vector_unit[] = {

57272

- "none",

57273

- "altivec",

57274

- "vsx",

57275

- "paired",

57276

- "spe",

57277

- "other"

57278

+ /* Modes we want tieable information on. */

57279

+ static const enum machine_mode print_tieable_modes[] = {

57280

+ QImode,

57281

+ HImode,

57282

+ SImode,

57283

+ DImode,

57284

+ TImode,

57285

+ PTImode,

57286

+ SFmode,

57287

+ DFmode,

57288

+ TFmode,

57289

+ SDmode,

57290

+ DDmode,

57291

+ TDmode,

57292

+ V8QImode,

57293

+ V4HImode,

57294

+ V2SImode,

57295

+ V16QImode,

57296

+ V8HImode,

57297

+ V4SImode,

57298

+ V2DImode,

57299

+ V1TImode,

57300

+ V32QImode,

57301

+ V16HImode,

57302

+ V8SImode,

57303

+ V4DImode,

57304

+ V2TImode,

57305

+ V2SFmode,

57306

+ V4SFmode,

57307

+ V2DFmode,

57308

+ V8SFmode,

57309

+ V4DFmode,

57310

+ CCmode,

57311

+ CCUNSmode,

57312

+ CCEQmode,

57313

};

57314

57315

- fprintf (stderr, "Register information: (last virtual reg = %d)\n",

57316

- LAST_VIRTUAL_REGISTER);

57317

- rs6000_debug_reg_print (0, 31, "gr");

57318

- rs6000_debug_reg_print (32, 63, "fp");

57319

+ /* Virtual regs we are interested in. */

57320

+ const static struct {

57321

+ int regno; /* register number. */

57322

+ const char *name; /* register name. */

57323

+ } virtual_regs[] = {

57324

+ { STACK_POINTER_REGNUM, "stack pointer:" },

57325

+ { TOC_REGNUM, "toc: " },

57326

+ { STATIC_CHAIN_REGNUM, "static chain: " },

57327

+ { RS6000_PIC_OFFSET_TABLE_REGNUM, "pic offset: " },

57328

+ { HARD_FRAME_POINTER_REGNUM, "hard frame: " },

57329

+ { ARG_POINTER_REGNUM, "arg pointer: " },

57330

+ { FRAME_POINTER_REGNUM, "frame pointer:" },

57331

+ { FIRST_PSEUDO_REGISTER, "first pseudo: " },

57332

+ { FIRST_VIRTUAL_REGISTER, "first virtual:" },

57333

+ { VIRTUAL_INCOMING_ARGS_REGNUM, "incoming_args:" },

57334

+ { VIRTUAL_STACK_VARS_REGNUM, "stack_vars: " },

57335

+ { VIRTUAL_STACK_DYNAMIC_REGNUM, "stack_dynamic:" },

57336

+ { VIRTUAL_OUTGOING_ARGS_REGNUM, "outgoing_args:" },

57337

+ { VIRTUAL_CFA_REGNUM, "cfa (frame): " },

57338

+ { VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM, "stack boundry:" },

57339

+ { LAST_VIRTUAL_REGISTER, "last virtual: " },

57340

+ };

57341

+

57342

+ fputs ("\nHard register information:\n", stderr);

57343

+ rs6000_debug_reg_print (FIRST_GPR_REGNO, LAST_GPR_REGNO, "gr");

57344

+ rs6000_debug_reg_print (FIRST_FPR_REGNO, LAST_FPR_REGNO, "fp");

57345

rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO,

57346

LAST_ALTIVEC_REGNO,

57347

"vs");

57348

@@ -1726,6 +2008,10 @@

57349

rs6000_debug_reg_print (SPE_ACC_REGNO, SPE_ACC_REGNO, "spe_a");

57350

rs6000_debug_reg_print (SPEFSCR_REGNO, SPEFSCR_REGNO, "spe_f");

57351

57352

+ fputs ("\nVirtual/stack/frame registers:\n", stderr);

57353

+ for (v = 0; v < ARRAY_SIZE (virtual_regs); v++)

57354

+ fprintf (stderr, "%s regno = %3d\n", virtual_regs[v].name, virtual_regs[v].regno);

57355

+

57356

fprintf (stderr,

57357

"\n"

57358

"d reg_class = %s\n"

57359

@@ -1734,7 +2020,19 @@

57360

"wa reg_class = %s\n"

57361

"wd reg_class = %s\n"

57362

"wf reg_class = %s\n"

57363

- "ws reg_class = %s\n\n",

57364

+ "wg reg_class = %s\n"

57365

+ "wl reg_class = %s\n"

57366

+ "wm reg_class = %s\n"

57367

+ "wr reg_class = %s\n"

57368

+ "ws reg_class = %s\n"

57369

+ "wt reg_class = %s\n"

57370

+ "wu reg_class = %s\n"

57371

+ "wv reg_class = %s\n"

57372

+ "ww reg_class = %s\n"

57373

+ "wx reg_class = %s\n"

57374

+ "wy reg_class = %s\n"

57375

+ "wz reg_class = %s\n"

57376

+ "\n",

57377

reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_d]],

57378

reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_f]],

57379

reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_v]],

57380

@@ -1741,18 +2039,51 @@

57381

reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wa]],

57382

reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wd]],

57383

reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]],

57384

- reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ws]]);

57385

+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wg]],

57386

+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wl]],

57387

+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wm]],

57388

+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]],

57389

+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ws]],

57390

+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wt]],

57391

+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wu]],

57392

+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wv]],

57393

+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ww]],

57394

+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]],

57395

+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wy]],

57396

+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wz]]);

57397

57398

+ nl = "\n";

57399

for (m = 0; m < NUM_MACHINE_MODES; ++m)

57400

- if (rs6000_vector_unit[m] || rs6000_vector_mem[m])

57401

- {

57402

- nl = "\n";

57403

- fprintf (stderr, "Vector mode: %-5s arithmetic: %-8s move: %-8s\n",

57404

- GET_MODE_NAME (m),

57405

- rs6000_debug_vector_unit[ rs6000_vector_unit[m] ],

57406

- rs6000_debug_vector_unit[ rs6000_vector_mem[m] ]);

57407

- }

57408

+ rs6000_debug_print_mode (m);

57409

57410

+ fputs ("\n", stderr);

57411

+

57412

+ for (m1 = 0; m1 < ARRAY_SIZE (print_tieable_modes); m1++)

57413

+ {

57414

+ enum machine_mode mode1 = print_tieable_modes[m1];

57415

+ bool first_time = true;

57416

+

57417

+ nl = (const char *)0;

57418

+ for (m2 = 0; m2 < ARRAY_SIZE (print_tieable_modes); m2++)

57419

+ {

57420

+ enum machine_mode mode2 = print_tieable_modes[m2];

57421

+ if (mode1 != mode2 && MODES_TIEABLE_P (mode1, mode2))

57422

+ {

57423

+ if (first_time)

57424

+ {

57425

+ fprintf (stderr, "Tieable modes %s:", GET_MODE_NAME (mode1));

57426

+ nl = "\n";

57427

+ first_time = false;

57428

+ }

57429

+

57430

+ fprintf (stderr, " %s", GET_MODE_NAME (mode2));

57431

+ }

57432

+ }

57433

+

57434

+ if (!first_time)

57435

+ fputs ("\n", stderr);

57436

+ }

57437

+

57438

if (nl)

57439

fputs (nl, stderr);

57440

57441

@@ -1913,6 +2244,7 @@

57442

{

57443

case ABI_NONE: abi_str = "none"; break;

57444

case ABI_AIX: abi_str = "aix"; break;

57445

+ case ABI_ELFv2: abi_str = "ELFv2"; break;

57446

case ABI_V4: abi_str = "V4"; break;

57447

case ABI_DARWIN: abi_str = "darwin"; break;

57448

default: abi_str = "unknown"; break;

57449

@@ -1932,9 +2264,34 @@

57450

if (rs6000_float_gprs)

57451

fprintf (stderr, DEBUG_FMT_S, "float_gprs", "true");

57452

57453

+ fprintf (stderr, DEBUG_FMT_S, "fprs",

57454

+ (TARGET_FPRS ? "true" : "false"));

57455

+

57456

+ fprintf (stderr, DEBUG_FMT_S, "single_float",

57457

+ (TARGET_SINGLE_FLOAT ? "true" : "false"));

57458

+

57459

+ fprintf (stderr, DEBUG_FMT_S, "double_float",

57460

+ (TARGET_DOUBLE_FLOAT ? "true" : "false"));

57461

+

57462

+ fprintf (stderr, DEBUG_FMT_S, "soft_float",

57463

+ (TARGET_SOFT_FLOAT ? "true" : "false"));

57464

+

57465

+ fprintf (stderr, DEBUG_FMT_S, "e500_single",

57466

+ (TARGET_E500_SINGLE ? "true" : "false"));

57467

+

57468

+ fprintf (stderr, DEBUG_FMT_S, "e500_double",

57469

+ (TARGET_E500_DOUBLE ? "true" : "false"));

57470

+

57471

if (TARGET_LINK_STACK)

57472

fprintf (stderr, DEBUG_FMT_S, "link_stack", "true");

57473

57474

+ if (targetm.lra_p ())

57475

+ fprintf (stderr, DEBUG_FMT_S, "lra", "true");

57476

+

57477

+ if (TARGET_P8_FUSION)

57478

+ fprintf (stderr, DEBUG_FMT_S, "p8 fusion",

57479

+ (TARGET_P8_FUSION_SIGN) ? "zero+sign" : "zero");

57480

+

57481

fprintf (stderr, DEBUG_FMT_S, "plt-format",

57482

TARGET_SECURE_PLT ? "secure" : "bss");

57483

fprintf (stderr, DEBUG_FMT_S, "struct-return",

57484

@@ -1954,11 +2311,106 @@

57485

(int)RS6000_BUILTIN_COUNT);

57486

}

57487

57488

+

57489

+/* Update the addr mask bits in reg_addr to help secondary reload and go if

57490

+ legitimate address support to figure out the appropriate addressing to

57491

+ use. */

57492

+

57493

+static void

57494

+rs6000_setup_reg_addr_masks (void)

57495

+{

57496

+ ssize_t rc, reg, m, nregs;

57497

+ addr_mask_type any_addr_mask, addr_mask;

57498

+

57499

+ for (m = 0; m < NUM_MACHINE_MODES; ++m)

57500

+ {

57501

+ /* SDmode is special in that we want to access it only via REG+REG

57502

+ addressing on power7 and above, since we want to use the LFIWZX and

57503

+ STFIWZX instructions to load it. */

57504

+ bool indexed_only_p = (m == SDmode && TARGET_NO_SDMODE_STACK);

57505

+

57506

+ any_addr_mask = 0;

57507

+ for (rc = FIRST_RELOAD_REG_CLASS; rc <= LAST_RELOAD_REG_CLASS; rc++)

57508

+ {

57509

+ addr_mask = 0;

57510

+ reg = reload_reg_map[rc].reg;

57511

+

57512

+ /* Can mode values go in the GPR/FPR/Altivec registers? */

57513

+ if (reg >= 0 && rs6000_hard_regno_mode_ok_p[m][reg])

57514

+ {

57515

+ nregs = rs6000_hard_regno_nregs[m][reg];

57516

+ addr_mask |= RELOAD_REG_VALID;

57517

+

57518

+ /* Indicate if the mode takes more than 1 physical register. If

57519

+ it takes a single register, indicate it can do REG+REG

57520

+ addressing. */

57521

+ if (nregs > 1 || m == BLKmode)

57522

+ addr_mask |= RELOAD_REG_MULTIPLE;

57523

+ else

57524

+ addr_mask |= RELOAD_REG_INDEXED;

57525

+

57526

+ /* Figure out if we can do PRE_INC, PRE_DEC, or PRE_MODIFY

57527

+ addressing. Restrict addressing on SPE for 64-bit types

57528

+ because of the SUBREG hackery used to address 64-bit floats in

57529

+ '32-bit' GPRs. To simplify secondary reload, don't allow

57530

+ update forms on scalar floating point types that can go in the

57531

+ upper registers. */

57532

+

57533

+ if (TARGET_UPDATE

57534

+ && (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR)

57535

+ && GET_MODE_SIZE (m) <= 8

57536

+ && !VECTOR_MODE_P (m)

57537

+ && !COMPLEX_MODE_P (m)

57538

+ && !indexed_only_p

57539

+ && !(TARGET_E500_DOUBLE && GET_MODE_SIZE (m) == 8)

57540

+ && !(m == DFmode && TARGET_UPPER_REGS_DF)

57541

+ && !(m == SFmode && TARGET_UPPER_REGS_SF))

57542

+ {

57543

+ addr_mask |= RELOAD_REG_PRE_INCDEC;

57544

+

57545

+ /* PRE_MODIFY is more restricted than PRE_INC/PRE_DEC in that

57546

+ we don't allow PRE_MODIFY for some multi-register

57547

+ operations. */

57548

+ switch (m)

57549

+ {

57550

+ default:

57551

+ addr_mask |= RELOAD_REG_PRE_MODIFY;

57552

+ break;

57553

+

57554

+ case DImode:

57555

+ if (TARGET_POWERPC64)

57556

+ addr_mask |= RELOAD_REG_PRE_MODIFY;

57557

+ break;

57558

+

57559

+ case DFmode:

57560

+ case DDmode:

57561

+ if (TARGET_DF_INSN)

57562

+ addr_mask |= RELOAD_REG_PRE_MODIFY;

57563

+ break;

57564

+ }

57565

+ }

57566

+ }

57567

+

57568

+ /* GPR and FPR registers can do REG+OFFSET addressing, except

57569

+ possibly for SDmode. */

57570

+ if ((addr_mask != 0) && !indexed_only_p

57571

+ && (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR))

57572

+ addr_mask |= RELOAD_REG_OFFSET;

57573

+

57574

+ reg_addr[m].addr_mask[rc] = addr_mask;

57575

+ any_addr_mask |= addr_mask;

57576

+ }

57577

+

57578

+ reg_addr[m].addr_mask[RELOAD_REG_ANY] = any_addr_mask;

57579

+ }

57580

+}

57581

+

57582

+

57583

/* Initialize the various global tables that are based on register size. */

57584

static void

57585

rs6000_init_hard_regno_mode_ok (bool global_init_p)

57586

{

57587

- int r, m, c;

57588

+ ssize_t r, m, c;

57589

int align64;

57590

int align32;

57591

57592

@@ -1987,21 +2439,55 @@

57593

rs6000_regno_regclass[VSCR_REGNO] = VRSAVE_REGS;

57594

rs6000_regno_regclass[SPE_ACC_REGNO] = SPE_ACC_REGS;

57595

rs6000_regno_regclass[SPEFSCR_REGNO] = SPEFSCR_REGS;

57596

+ rs6000_regno_regclass[TFHAR_REGNO] = SPR_REGS;

57597

+ rs6000_regno_regclass[TFIAR_REGNO] = SPR_REGS;

57598

+ rs6000_regno_regclass[TEXASR_REGNO] = SPR_REGS;

57599

rs6000_regno_regclass[ARG_POINTER_REGNUM] = BASE_REGS;

57600

rs6000_regno_regclass[FRAME_POINTER_REGNUM] = BASE_REGS;

57601

57602

- /* Precalculate vector information, this must be set up before the

57603

- rs6000_hard_regno_nregs_internal below. */

57604

- for (m = 0; m < NUM_MACHINE_MODES; ++m)

57605

+ /* Precalculate register class to simpler reload register class. We don't

57606

+ need all of the register classes that are combinations of different

57607

+ classes, just the simple ones that have constraint letters. */

57608

+ for (c = 0; c < N_REG_CLASSES; c++)

57609

+ reg_class_to_reg_type[c] = NO_REG_TYPE;

57610

+

57611

+ reg_class_to_reg_type[(int)GENERAL_REGS] = GPR_REG_TYPE;

57612

+ reg_class_to_reg_type[(int)BASE_REGS] = GPR_REG_TYPE;

57613

+ reg_class_to_reg_type[(int)VSX_REGS] = VSX_REG_TYPE;

57614

+ reg_class_to_reg_type[(int)VRSAVE_REGS] = SPR_REG_TYPE;

57615

+ reg_class_to_reg_type[(int)VSCR_REGS] = SPR_REG_TYPE;

57616

+ reg_class_to_reg_type[(int)LINK_REGS] = SPR_REG_TYPE;

57617

+ reg_class_to_reg_type[(int)CTR_REGS] = SPR_REG_TYPE;

57618

+ reg_class_to_reg_type[(int)LINK_OR_CTR_REGS] = SPR_REG_TYPE;

57619

+ reg_class_to_reg_type[(int)CR_REGS] = CR_REG_TYPE;

57620

+ reg_class_to_reg_type[(int)CR0_REGS] = CR_REG_TYPE;

57621

+ reg_class_to_reg_type[(int)SPE_ACC_REGS] = SPE_ACC_TYPE;

57622

+ reg_class_to_reg_type[(int)SPEFSCR_REGS] = SPEFSCR_REG_TYPE;

57623

+

57624

+ if (TARGET_VSX)

57625

{

57626

- rs6000_vector_unit[m] = rs6000_vector_mem[m] = VECTOR_NONE;

57627

- rs6000_vector_reload[m][0] = CODE_FOR_nothing;

57628

- rs6000_vector_reload[m][1] = CODE_FOR_nothing;

57629

+ reg_class_to_reg_type[(int)FLOAT_REGS] = VSX_REG_TYPE;

57630

+ reg_class_to_reg_type[(int)ALTIVEC_REGS] = VSX_REG_TYPE;

57631

}

57632

+ else

57633

+ {

57634

+ reg_class_to_reg_type[(int)FLOAT_REGS] = FPR_REG_TYPE;

57635

+ reg_class_to_reg_type[(int)ALTIVEC_REGS] = ALTIVEC_REG_TYPE;

57636

+ }

57637

57638

- for (c = 0; c < (int)(int)RS6000_CONSTRAINT_MAX; c++)

57639

- rs6000_constraints[c] = NO_REGS;

57640

+ /* Precalculate the valid memory formats as well as the vector information,

57641

+ this must be set up before the rs6000_hard_regno_nregs_internal calls

57642

+ below. */

57643

+ gcc_assert ((int)VECTOR_NONE == 0);

57644

+ memset ((void *) &rs6000_vector_unit[0], '\0', sizeof (rs6000_vector_unit));

57645

+ memset ((void *) &rs6000_vector_mem[0], '\0', sizeof (rs6000_vector_unit));

57646

57647

+ gcc_assert ((int)CODE_FOR_nothing == 0);

57648

+ memset ((void *) &reg_addr[0], '\0', sizeof (reg_addr));

57649

+

57650

+ gcc_assert ((int)NO_REGS == 0);

57651

+ memset ((void *) &rs6000_constraints[0], '\0', sizeof (rs6000_constraints));

57652

+

57653

/* The VSX hardware allows native alignment for vectors, but control whether the compiler

57654

believes it can use native alignment or still uses 128-bit alignment. */

57655

if (TARGET_VSX && !TARGET_VSX_ALIGN_128)

57656

@@ -2062,13 +2548,19 @@

57657

}

57658

}

57659

57660

- /* V2DImode, only allow under VSX, which can do V2DI insert/splat/extract.

57661

- Altivec doesn't have 64-bit support. */

57662

+ /* V2DImode, full mode depends on ISA 2.07 vector mode. Allow under VSX to

57663

+ do insert/splat/extract. Altivec doesn't have 64-bit integer support. */

57664

if (TARGET_VSX)

57665

{

57666

rs6000_vector_mem[V2DImode] = VECTOR_VSX;

57667

- rs6000_vector_unit[V2DImode] = VECTOR_NONE;

57668

+ rs6000_vector_unit[V2DImode]

57669

+ = (TARGET_P8_VECTOR) ? VECTOR_P8_VECTOR : VECTOR_NONE;

57670

rs6000_vector_align[V2DImode] = align64;

57671

+

57672

+ rs6000_vector_mem[V1TImode] = VECTOR_VSX;

57673

+ rs6000_vector_unit[V1TImode]

57674

+ = (TARGET_P8_VECTOR) ? VECTOR_P8_VECTOR : VECTOR_NONE;

57675

+ rs6000_vector_align[V1TImode] = 128;

57676

}

57677

57678

/* DFmode, see if we want to use the VSX unit. */

57679

@@ -2076,14 +2568,48 @@

57680

{

57681

rs6000_vector_unit[DFmode] = VECTOR_VSX;

57682

rs6000_vector_mem[DFmode]

57683

- = (TARGET_VSX_SCALAR_MEMORY ? VECTOR_VSX : VECTOR_NONE);

57684

+ = (TARGET_UPPER_REGS_DF ? VECTOR_VSX : VECTOR_NONE);

57685

rs6000_vector_align[DFmode] = align64;

57686

}

57687

57688

+ /* Allow TImode in VSX register and set the VSX memory macros. */

57689

+ if (TARGET_VSX && TARGET_VSX_TIMODE)

57690

+ {

57691

+ rs6000_vector_mem[TImode] = VECTOR_VSX;

57692

+ rs6000_vector_align[TImode] = align64;

57693

+ }

57694

+

57695

/* TODO add SPE and paired floating point vector support. */

57696

57697

/* Register class constraints for the constraints that depend on compile

57698

- switches. */

57699

+ switches. When the VSX code was added, different constraints were added

57700

+ based on the type (DFmode, V2DFmode, V4SFmode). For the vector types, all

57701

+ of the VSX registers are used. The register classes for scalar floating

57702

+ point types is set, based on whether we allow that type into the upper

57703

+ (Altivec) registers. GCC has register classes to target the Altivec

57704

+ registers for load/store operations, to select using a VSX memory

57705

+ operation instead of the traditional floating point operation. The

57706

+ constraints are:

57707

+

57708

+ d - Register class to use with traditional DFmode instructions.

57709

+ f - Register class to use with traditional SFmode instructions.

57710

+ v - Altivec register.

57711

+ wa - Any VSX register.

57712

+ wd - Preferred register class for V2DFmode.

57713

+ wf - Preferred register class for V4SFmode.

57714

+ wg - Float register for power6x move insns.

57715

+ wl - Float register if we can do 32-bit signed int loads.

57716

+ wm - VSX register for ISA 2.07 direct move operations.

57717

+ wr - GPR if 64-bit mode is permitted.

57718

+ ws - Register class to do ISA 2.06 DF operations.

57719

+ wu - Altivec register for ISA 2.07 VSX SF/SI load/stores.

57720

+ wv - Altivec register for ISA 2.06 VSX DF/DI load/stores.

57721

+ wt - VSX register for TImode in VSX registers.

57722

+ ww - Register class to do SF conversions in with VSX operations.

57723

+ wx - Float register if we can do 32-bit int stores.

57724

+ wy - Register class to do ISA 2.07 SF operations.

57725

+ wz - Float register if we can do 32-bit unsigned int loads. */

57726

+

57727

if (TARGET_HARD_FLOAT && TARGET_FPRS)

57728

rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS;

57729

57730

@@ -2092,64 +2618,164 @@

57731

57732

if (TARGET_VSX)

57733

{

57734

- /* At present, we just use VSX_REGS, but we have different constraints

57735

- based on the use, in case we want to fine tune the default register

57736

- class used. wa = any VSX register, wf = register class to use for

57737

- V4SF, wd = register class to use for V2DF, and ws = register classs to

57738

- use for DF scalars. */

57739

rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS;

57740

+ rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS;

57741

rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS;

57742

- rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS;

57743

- rs6000_constraints[RS6000_CONSTRAINT_ws] = (TARGET_VSX_SCALAR_MEMORY

57744

- ? VSX_REGS

57745

- : FLOAT_REGS);

57746

+

57747

+ if (TARGET_VSX_TIMODE)

57748

+ rs6000_constraints[RS6000_CONSTRAINT_wt] = VSX_REGS;

57749

+

57750

+ if (TARGET_UPPER_REGS_DF)

57751

+ {

57752

+ rs6000_constraints[RS6000_CONSTRAINT_ws] = VSX_REGS;

57753

+ rs6000_constraints[RS6000_CONSTRAINT_wv] = ALTIVEC_REGS;

57754

+ }

57755

+ else

57756

+ rs6000_constraints[RS6000_CONSTRAINT_ws] = FLOAT_REGS;

57757

}

57758

57759

+ /* Add conditional constraints based on various options, to allow us to

57760

+ collapse multiple insn patterns. */

57761

if (TARGET_ALTIVEC)

57762

rs6000_constraints[RS6000_CONSTRAINT_v] = ALTIVEC_REGS;

57763

57764

- /* Set up the reload helper functions. */

57765

+ if (TARGET_MFPGPR)

57766

+ rs6000_constraints[RS6000_CONSTRAINT_wg] = FLOAT_REGS;

57767

+

57768

+ if (TARGET_LFIWAX)

57769

+ rs6000_constraints[RS6000_CONSTRAINT_wl] = FLOAT_REGS;

57770

+

57771

+ if (TARGET_DIRECT_MOVE)

57772

+ rs6000_constraints[RS6000_CONSTRAINT_wm] = VSX_REGS;

57773

+

57774

+ if (TARGET_POWERPC64)

57775

+ rs6000_constraints[RS6000_CONSTRAINT_wr] = GENERAL_REGS;

57776

+

57777

+ if (TARGET_P8_VECTOR && TARGET_UPPER_REGS_SF)

57778

+ {

57779

+ rs6000_constraints[RS6000_CONSTRAINT_wu] = ALTIVEC_REGS;

57780

+ rs6000_constraints[RS6000_CONSTRAINT_wy] = VSX_REGS;

57781

+ rs6000_constraints[RS6000_CONSTRAINT_ww] = VSX_REGS;

57782

+ }

57783

+ else if (TARGET_P8_VECTOR)

57784

+ {

57785

+ rs6000_constraints[RS6000_CONSTRAINT_wy] = FLOAT_REGS;

57786

+ rs6000_constraints[RS6000_CONSTRAINT_ww] = FLOAT_REGS;

57787

+ }

57788

+ else if (TARGET_VSX)

57789

+ rs6000_constraints[RS6000_CONSTRAINT_ww] = FLOAT_REGS;

57790

+

57791

+ if (TARGET_STFIWX)

57792

+ rs6000_constraints[RS6000_CONSTRAINT_wx] = FLOAT_REGS;

57793

+

57794

+ if (TARGET_LFIWZX)

57795

+ rs6000_constraints[RS6000_CONSTRAINT_wz] = FLOAT_REGS;

57796

+

57797

+ /* Set up the reload helper and direct move functions. */

57798

if (TARGET_VSX || TARGET_ALTIVEC)

57799

{

57800

if (TARGET_64BIT)

57801

{

57802

- rs6000_vector_reload[V16QImode][0] = CODE_FOR_reload_v16qi_di_store;

57803

- rs6000_vector_reload[V16QImode][1] = CODE_FOR_reload_v16qi_di_load;

57804

- rs6000_vector_reload[V8HImode][0] = CODE_FOR_reload_v8hi_di_store;

57805

- rs6000_vector_reload[V8HImode][1] = CODE_FOR_reload_v8hi_di_load;

57806

- rs6000_vector_reload[V4SImode][0] = CODE_FOR_reload_v4si_di_store;

57807

- rs6000_vector_reload[V4SImode][1] = CODE_FOR_reload_v4si_di_load;

57808

- rs6000_vector_reload[V2DImode][0] = CODE_FOR_reload_v2di_di_store;

57809

- rs6000_vector_reload[V2DImode][1] = CODE_FOR_reload_v2di_di_load;

57810

- rs6000_vector_reload[V4SFmode][0] = CODE_FOR_reload_v4sf_di_store;

57811

- rs6000_vector_reload[V4SFmode][1] = CODE_FOR_reload_v4sf_di_load;

57812

- rs6000_vector_reload[V2DFmode][0] = CODE_FOR_reload_v2df_di_store;

57813

- rs6000_vector_reload[V2DFmode][1] = CODE_FOR_reload_v2df_di_load;

57814

- if (TARGET_VSX && TARGET_VSX_SCALAR_MEMORY)

57815

+ reg_addr[V16QImode].reload_store = CODE_FOR_reload_v16qi_di_store;

57816

+ reg_addr[V16QImode].reload_load = CODE_FOR_reload_v16qi_di_load;

57817

+ reg_addr[V8HImode].reload_store = CODE_FOR_reload_v8hi_di_store;

57818

+ reg_addr[V8HImode].reload_load = CODE_FOR_reload_v8hi_di_load;

57819

+ reg_addr[V4SImode].reload_store = CODE_FOR_reload_v4si_di_store;

57820

+ reg_addr[V4SImode].reload_load = CODE_FOR_reload_v4si_di_load;

57821

+ reg_addr[V2DImode].reload_store = CODE_FOR_reload_v2di_di_store;

57822

+ reg_addr[V2DImode].reload_load = CODE_FOR_reload_v2di_di_load;

57823

+ reg_addr[V1TImode].reload_store = CODE_FOR_reload_v1ti_di_store;

57824

+ reg_addr[V1TImode].reload_load = CODE_FOR_reload_v1ti_di_load;

57825

+ reg_addr[V4SFmode].reload_store = CODE_FOR_reload_v4sf_di_store;

57826

+ reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_di_load;

57827

+ reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_di_store;

57828

+ reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_di_load;

57829

+ if (TARGET_VSX && TARGET_UPPER_REGS_DF)

57830

{

57831

- rs6000_vector_reload[DFmode][0] = CODE_FOR_reload_df_di_store;

57832

- rs6000_vector_reload[DFmode][1] = CODE_FOR_reload_df_di_load;

57833

+ reg_addr[DFmode].reload_store = CODE_FOR_reload_df_di_store;

57834

+ reg_addr[DFmode].reload_load = CODE_FOR_reload_df_di_load;

57835

+ reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_di_store;

57836

+ reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_di_load;

57837

}

57838

+ if (TARGET_P8_VECTOR)

57839

+ {

57840

+ reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_di_store;

57841

+ reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_di_load;

57842

+ reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_di_store;

57843

+ reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_di_load;

57844

+ }

57845

+ if (TARGET_VSX_TIMODE)

57846

+ {

57847

+ reg_addr[TImode].reload_store = CODE_FOR_reload_ti_di_store;

57848

+ reg_addr[TImode].reload_load = CODE_FOR_reload_ti_di_load;

57849

+ }

57850

+ if (TARGET_DIRECT_MOVE)

57851

+ {

57852

+ if (TARGET_POWERPC64)

57853

+ {

57854

+ reg_addr[TImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxti;

57855

+ reg_addr[V1TImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv1ti;

57856

+ reg_addr[V2DFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv2df;

57857

+ reg_addr[V2DImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv2di;

57858

+ reg_addr[V4SFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv4sf;

57859

+ reg_addr[V4SImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv4si;

57860

+ reg_addr[V8HImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv8hi;

57861

+ reg_addr[V16QImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv16qi;

57862

+ reg_addr[SFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxsf;

57863

+

57864

+ reg_addr[TImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprti;

57865

+ reg_addr[V1TImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv1ti;

57866

+ reg_addr[V2DFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv2df;

57867

+ reg_addr[V2DImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv2di;

57868

+ reg_addr[V4SFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv4sf;

57869

+ reg_addr[V4SImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv4si;

57870

+ reg_addr[V8HImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv8hi;

57871

+ reg_addr[V16QImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv16qi;

57872

+ reg_addr[SFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprsf;

57873

+ }

57874

+ else

57875

+ {

57876

+ reg_addr[DImode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdi;

57877

+ reg_addr[DDmode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdd;

57878

+ reg_addr[DFmode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdf;

57879

+ }

57880

+ }

57881

}

57882

else

57883

{

57884

- rs6000_vector_reload[V16QImode][0] = CODE_FOR_reload_v16qi_si_store;

57885

- rs6000_vector_reload[V16QImode][1] = CODE_FOR_reload_v16qi_si_load;

57886

- rs6000_vector_reload[V8HImode][0] = CODE_FOR_reload_v8hi_si_store;

57887

- rs6000_vector_reload[V8HImode][1] = CODE_FOR_reload_v8hi_si_load;

57888

- rs6000_vector_reload[V4SImode][0] = CODE_FOR_reload_v4si_si_store;

57889

- rs6000_vector_reload[V4SImode][1] = CODE_FOR_reload_v4si_si_load;

57890

- rs6000_vector_reload[V2DImode][0] = CODE_FOR_reload_v2di_si_store;

57891

- rs6000_vector_reload[V2DImode][1] = CODE_FOR_reload_v2di_si_load;

57892

- rs6000_vector_reload[V4SFmode][0] = CODE_FOR_reload_v4sf_si_store;

57893

- rs6000_vector_reload[V4SFmode][1] = CODE_FOR_reload_v4sf_si_load;

57894

- rs6000_vector_reload[V2DFmode][0] = CODE_FOR_reload_v2df_si_store;

57895

- rs6000_vector_reload[V2DFmode][1] = CODE_FOR_reload_v2df_si_load;

57896

- if (TARGET_VSX && TARGET_VSX_SCALAR_MEMORY)

57897

+ reg_addr[V16QImode].reload_store = CODE_FOR_reload_v16qi_si_store;

57898

+ reg_addr[V16QImode].reload_load = CODE_FOR_reload_v16qi_si_load;

57899

+ reg_addr[V8HImode].reload_store = CODE_FOR_reload_v8hi_si_store;

57900

+ reg_addr[V8HImode].reload_load = CODE_FOR_reload_v8hi_si_load;

57901

+ reg_addr[V4SImode].reload_store = CODE_FOR_reload_v4si_si_store;

57902

+ reg_addr[V4SImode].reload_load = CODE_FOR_reload_v4si_si_load;

57903

+ reg_addr[V2DImode].reload_store = CODE_FOR_reload_v2di_si_store;

57904

+ reg_addr[V2DImode].reload_load = CODE_FOR_reload_v2di_si_load;

57905

+ reg_addr[V1TImode].reload_store = CODE_FOR_reload_v1ti_si_store;

57906

+ reg_addr[V1TImode].reload_load = CODE_FOR_reload_v1ti_si_load;

57907

+ reg_addr[V4SFmode].reload_store = CODE_FOR_reload_v4sf_si_store;

57908

+ reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_si_load;

57909

+ reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_si_store;

57910

+ reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_si_load;

57911

+ if (TARGET_VSX && TARGET_UPPER_REGS_DF)

57912

{

57913

- rs6000_vector_reload[DFmode][0] = CODE_FOR_reload_df_si_store;

57914

- rs6000_vector_reload[DFmode][1] = CODE_FOR_reload_df_si_load;

57915

+ reg_addr[DFmode].reload_store = CODE_FOR_reload_df_si_store;

57916

+ reg_addr[DFmode].reload_load = CODE_FOR_reload_df_si_load;

57917

+ reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_si_store;

57918

+ reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_si_load;

57919

}

57920

+ if (TARGET_P8_VECTOR)

57921

+ {

57922

+ reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_si_store;

57923

+ reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_si_load;

57924

+ reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_si_store;

57925

+ reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_si_load;

57926

+ }

57927

+ if (TARGET_VSX_TIMODE)

57928

+ {

57929

+ reg_addr[TImode].reload_store = CODE_FOR_reload_ti_si_store;

57930

+ reg_addr[TImode].reload_load = CODE_FOR_reload_ti_si_load;

57931

+ }

57932

}

57933

}

57934

57935

@@ -2267,6 +2893,11 @@

57936

}

57937

}

57938

57939

+ /* Update the addr mask bits in reg_addr to help secondary reload and go if

57940

+ legitimate address support to figure out the appropriate addressing to

57941

+ use. */

57942

+ rs6000_setup_reg_addr_masks ();

57943

+

57944

if (global_init_p || TARGET_DEBUG_TARGET)

57945

{

57946

if (TARGET_DEBUG_REG)

57947

@@ -2369,16 +3000,21 @@

57948

HOST_WIDE_INT

57949

rs6000_builtin_mask_calculate (void)

57950

{

57951

- return (((TARGET_ALTIVEC) ? RS6000_BTM_ALTIVEC : 0)

57952

- | ((TARGET_VSX) ? RS6000_BTM_VSX : 0)

57953

- | ((TARGET_SPE) ? RS6000_BTM_SPE : 0)

57954

- | ((TARGET_PAIRED_FLOAT) ? RS6000_BTM_PAIRED : 0)

57955

- | ((TARGET_FRE) ? RS6000_BTM_FRE : 0)

57956

- | ((TARGET_FRES) ? RS6000_BTM_FRES : 0)

57957

- | ((TARGET_FRSQRTE) ? RS6000_BTM_FRSQRTE : 0)

57958

- | ((TARGET_FRSQRTES) ? RS6000_BTM_FRSQRTES : 0)

57959

- | ((TARGET_POPCNTD) ? RS6000_BTM_POPCNTD : 0)

57960

- | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0));

57961

+ return (((TARGET_ALTIVEC) ? RS6000_BTM_ALTIVEC : 0)

57962

+ | ((TARGET_VSX) ? RS6000_BTM_VSX : 0)

57963

+ | ((TARGET_SPE) ? RS6000_BTM_SPE : 0)

57964

+ | ((TARGET_PAIRED_FLOAT) ? RS6000_BTM_PAIRED : 0)

57965

+ | ((TARGET_FRE) ? RS6000_BTM_FRE : 0)

57966

+ | ((TARGET_FRES) ? RS6000_BTM_FRES : 0)

57967

+ | ((TARGET_FRSQRTE) ? RS6000_BTM_FRSQRTE : 0)

57968

+ | ((TARGET_FRSQRTES) ? RS6000_BTM_FRSQRTES : 0)

57969

+ | ((TARGET_POPCNTD) ? RS6000_BTM_POPCNTD : 0)

57970

+ | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0)

57971

+ | ((TARGET_P8_VECTOR) ? RS6000_BTM_P8_VECTOR : 0)

57972

+ | ((TARGET_CRYPTO) ? RS6000_BTM_CRYPTO : 0)

57973

+ | ((TARGET_HTM) ? RS6000_BTM_HTM : 0)

57974

+ | ((TARGET_DFP) ? RS6000_BTM_DFP : 0)

57975

+ | ((TARGET_HARD_FLOAT) ? RS6000_BTM_HARD_FLOAT : 0));

57976

}

57977

57978

/* Override command line options. Mostly we process the processor type and

57979

@@ -2415,7 +3051,8 @@

57980

calculation works better for RTL loop invariant motion on targets

57981

with enough (>= 32) registers. It is an expensive optimization.

57982

So it is on only for peak performance. */

57983

- if (optimize >= 3 && global_init_p)

57984

+ if (optimize >= 3 && global_init_p

57985

+ && !global_options_set.x_flag_ira_loop_pressure)

57986

flag_ira_loop_pressure = 1;

57987

57988

/* Set the pointer size. */

57989

@@ -2609,6 +3246,24 @@

57990

}

57991

}

57992

57993

+ /* If little-endian, default to -mstrict-align on older processors.

57994

+ Testing for htm matches power8 and later. */

57995

+ if (!BYTES_BIG_ENDIAN

57996

+ && !(processor_target_table[tune_index].target_enable & OPTION_MASK_HTM))

57997

+ rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_STRICT_ALIGN;

57998

+

57999

+ /* -maltivec={le,be} implies -maltivec. */

58000

+ if (rs6000_altivec_element_order != 0)

58001

+ rs6000_isa_flags |= OPTION_MASK_ALTIVEC;

58002

+

58003

+ /* Disallow -maltivec=le in big endian mode for now. This is not

58004

+ known to be useful for anyone. */

58005

+ if (BYTES_BIG_ENDIAN && rs6000_altivec_element_order == 1)

58006

+ {

58007

+ warning (0, N_("-maltivec=le not allowed for big-endian targets"));

58008

+ rs6000_altivec_element_order = 0;

58009

+ }

58010

+

58011

/* Add some warnings for VSX. */

58012

if (TARGET_VSX)

58013

{

58014

@@ -2619,15 +3274,13 @@

58015

if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)

58016

msg = N_("-mvsx requires hardware floating point");

58017

else

58018

- rs6000_isa_flags &= ~ OPTION_MASK_VSX;

58019

+ {

58020

+ rs6000_isa_flags &= ~ OPTION_MASK_VSX;

58021

+ rs6000_isa_flags_explicit |= OPTION_MASK_VSX;

58022

+ }

58023

}

58024

else if (TARGET_PAIRED_FLOAT)

58025

msg = N_("-mvsx and -mpaired are incompatible");

58026

- /* The hardware will allow VSX and little endian, but until we make sure

58027

- things like vector select, etc. work don't allow VSX on little endian

58028

- systems at this point. */

58029

- else if (!BYTES_BIG_ENDIAN)

58030

- msg = N_("-mvsx used with little endian code");

58031

else if (TARGET_AVOID_XFORM > 0)

58032

msg = N_("-mvsx needs indexed addressing");

58033

else if (!TARGET_ALTIVEC && (rs6000_isa_flags_explicit

58034

@@ -2647,9 +3300,24 @@

58035

}

58036

}

58037

58038

+ /* If hard-float/altivec/vsx were explicitly turned off then don't allow

58039

+ the -mcpu setting to enable options that conflict. */

58040

+ if ((!TARGET_HARD_FLOAT || !TARGET_ALTIVEC || !TARGET_VSX)

58041

+ && (rs6000_isa_flags_explicit & (OPTION_MASK_SOFT_FLOAT

58042

+ | OPTION_MASK_ALTIVEC

58043

+ | OPTION_MASK_VSX)) != 0)

58044

+ rs6000_isa_flags &= ~((OPTION_MASK_P8_VECTOR | OPTION_MASK_CRYPTO

58045

+ | OPTION_MASK_DIRECT_MOVE)

58046

+ & ~rs6000_isa_flags_explicit);

58047

+

58048

+ if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)

58049

+ rs6000_print_isa_options (stderr, 0, "before defaults", rs6000_isa_flags);

58050

+

58051

/* For the newer switches (vsx, dfp, etc.) set some of the older options,

58052

unless the user explicitly used the -mno-<option> to disable the code. */

58053

- if (TARGET_VSX)

58054

+ if (TARGET_P8_VECTOR || TARGET_DIRECT_MOVE || TARGET_CRYPTO)

58055

+ rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~rs6000_isa_flags_explicit);

58056

+ else if (TARGET_VSX)

58057

rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~rs6000_isa_flags_explicit);

58058

else if (TARGET_POPCNTD)

58059

rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~rs6000_isa_flags_explicit);

58060

@@ -2664,6 +3332,99 @@

58061

else if (TARGET_ALTIVEC)

58062

rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~rs6000_isa_flags_explicit);

58063

58064

+ if (TARGET_CRYPTO && !TARGET_ALTIVEC)

58065

+ {

58066

+ if (rs6000_isa_flags_explicit & OPTION_MASK_CRYPTO)

58067

+ error ("-mcrypto requires -maltivec");

58068

+ rs6000_isa_flags &= ~OPTION_MASK_CRYPTO;

58069

+ }

58070

+

58071

+ if (TARGET_DIRECT_MOVE && !TARGET_VSX)

58072

+ {

58073

+ if (rs6000_isa_flags_explicit & OPTION_MASK_DIRECT_MOVE)

58074

+ error ("-mdirect-move requires -mvsx");

58075

+ rs6000_isa_flags &= ~OPTION_MASK_DIRECT_MOVE;

58076

+ }

58077

+

58078

+ if (TARGET_P8_VECTOR && !TARGET_ALTIVEC)

58079

+ {

58080

+ if (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)

58081

+ error ("-mpower8-vector requires -maltivec");

58082

+ rs6000_isa_flags &= ~OPTION_MASK_P8_VECTOR;

58083

+ }

58084

+

58085

+ if (TARGET_P8_VECTOR && !TARGET_VSX)

58086

+ {

58087

+ if (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)

58088

+ error ("-mpower8-vector requires -mvsx");

58089

+ rs6000_isa_flags &= ~OPTION_MASK_P8_VECTOR;

58090

+ }

58091

+

58092

+ if (TARGET_VSX_TIMODE && !TARGET_VSX)

58093

+ {

58094

+ if (rs6000_isa_flags_explicit & OPTION_MASK_VSX_TIMODE)

58095

+ error ("-mvsx-timode requires -mvsx");

58096

+ rs6000_isa_flags &= ~OPTION_MASK_VSX_TIMODE;

58097

+ }

58098

+

58099

+ if (TARGET_DFP && !TARGET_HARD_FLOAT)

58100

+ {

58101

+ if (rs6000_isa_flags_explicit & OPTION_MASK_DFP)

58102

+ error ("-mhard-dfp requires -mhard-float");

58103

+ rs6000_isa_flags &= ~OPTION_MASK_DFP;

58104

+ }

58105

+

58106

+ /* The quad memory instructions only works in 64-bit mode. In 32-bit mode,

58107

+ silently turn off quad memory mode. */

58108

+ if ((TARGET_QUAD_MEMORY || TARGET_QUAD_MEMORY_ATOMIC) && !TARGET_POWERPC64)

58109

+ {

58110

+ if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY) != 0)

58111

+ warning (0, N_("-mquad-memory requires 64-bit mode"));

58112

+

58113

+ if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY_ATOMIC) != 0)

58114

+ warning (0, N_("-mquad-memory-atomic requires 64-bit mode"));

58115

+

58116

+ rs6000_isa_flags &= ~(OPTION_MASK_QUAD_MEMORY

58117

+ | OPTION_MASK_QUAD_MEMORY_ATOMIC);

58118

+ }

58119

+

58120

+ /* Non-atomic quad memory load/store are disabled for little endian, since

58121

+ the words are reversed, but atomic operations can still be done by

58122

+ swapping the words. */

58123

+ if (TARGET_QUAD_MEMORY && !WORDS_BIG_ENDIAN)

58124

+ {

58125

+ if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY) != 0)

58126

+ warning (0, N_("-mquad-memory is not available in little endian mode"));

58127

+

58128

+ rs6000_isa_flags &= ~OPTION_MASK_QUAD_MEMORY;

58129

+ }

58130

+

58131

+ /* Assume if the user asked for normal quad memory instructions, they want

58132

+ the atomic versions as well, unless they explicity told us not to use quad

58133

+ word atomic instructions. */

58134

+ if (TARGET_QUAD_MEMORY

58135

+ && !TARGET_QUAD_MEMORY_ATOMIC

58136

+ && ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY_ATOMIC) == 0))

58137

+ rs6000_isa_flags |= OPTION_MASK_QUAD_MEMORY_ATOMIC;

58138

+

58139

+ /* Enable power8 fusion if we are tuning for power8, even if we aren't

58140

+ generating power8 instructions. */

58141

+ if (!(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION))

58142

+ rs6000_isa_flags |= (processor_target_table[tune_index].target_enable

58143

+ & OPTION_MASK_P8_FUSION);

58144

+

58145

+ /* Power8 does not fuse sign extended loads with the addis. If we are

58146

+ optimizing at high levels for speed, convert a sign extended load into a

58147

+ zero extending load, and an explicit sign extension. */

58148

+ if (TARGET_P8_FUSION

58149

+ && !(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION_SIGN)

58150

+ && optimize_function_for_speed_p (cfun)

58151

+ && optimize >= 3)

58152

+ rs6000_isa_flags |= OPTION_MASK_P8_FUSION_SIGN;

58153

+

58154

+ if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)

58155

+ rs6000_print_isa_options (stderr, 0, "after defaults", rs6000_isa_flags);

58156

+

58157

/* E500mc does "better" if we inline more aggressively. Respect the

58158

user's opinion, though. */

58159

if (rs6000_block_move_inline_limit == 0

58160

@@ -2787,9 +3548,13 @@

58161

58162

/* Place FP constants in the constant pool instead of TOC

58163

if section anchors enabled. */

58164

- if (flag_section_anchors)

58165

+ if (flag_section_anchors

58166

+ && !global_options_set.x_TARGET_NO_FP_IN_TOC)

58167

TARGET_NO_FP_IN_TOC = 1;

58168

58169

+ if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)

58170

+ rs6000_print_isa_options (stderr, 0, "before subtarget", rs6000_isa_flags);

58171

+

58172

#ifdef SUBTARGET_OVERRIDE_OPTIONS

58173

SUBTARGET_OVERRIDE_OPTIONS;

58174

#endif

58175

@@ -2800,6 +3565,9 @@

58176

SUB3TARGET_OVERRIDE_OPTIONS;

58177

#endif

58178

58179

+ if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)

58180

+ rs6000_print_isa_options (stderr, 0, "after subtarget", rs6000_isa_flags);

58181

+

58182

/* For the E500 family of cores, reset the single/double FP flags to let us

58183

check that they remain constant across attributes or pragmas. Also,

58184

clear a possible request for string instructions, not supported and which

58185

@@ -2849,16 +3617,19 @@

58186

&& rs6000_cpu != PROCESSOR_POWER5

58187

&& rs6000_cpu != PROCESSOR_POWER6

58188

&& rs6000_cpu != PROCESSOR_POWER7

58189

+ && rs6000_cpu != PROCESSOR_POWER8

58190

&& rs6000_cpu != PROCESSOR_PPCA2

58191

&& rs6000_cpu != PROCESSOR_CELL

58192

&& rs6000_cpu != PROCESSOR_PPC476);

58193

rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4

58194

|| rs6000_cpu == PROCESSOR_POWER5

58195

- || rs6000_cpu == PROCESSOR_POWER7);

58196

+ || rs6000_cpu == PROCESSOR_POWER7

58197

+ || rs6000_cpu == PROCESSOR_POWER8);

58198

rs6000_align_branch_targets = (rs6000_cpu == PROCESSOR_POWER4

58199

|| rs6000_cpu == PROCESSOR_POWER5

58200

|| rs6000_cpu == PROCESSOR_POWER6

58201

|| rs6000_cpu == PROCESSOR_POWER7

58202

+ || rs6000_cpu == PROCESSOR_POWER8

58203

|| rs6000_cpu == PROCESSOR_PPCE500MC

58204

|| rs6000_cpu == PROCESSOR_PPCE500MC64

58205

|| rs6000_cpu == PROCESSOR_PPCE5500

58206

@@ -2988,7 +3759,7 @@

58207

58208

/* We should always be splitting complex arguments, but we can't break

58209

Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */

58210

- if (DEFAULT_ABI != ABI_AIX)

58211

+ if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN)

58212

targetm.calls.split_complex_arg = NULL;

58213

}

58214

58215

@@ -3102,6 +3873,10 @@

58216

rs6000_cost = &power7_cost;

58217

break;

58218

58219

+ case PROCESSOR_POWER8:

58220

+ rs6000_cost = &power8_cost;

58221

+ break;

58222

+

58223

case PROCESSOR_PPCA2:

58224

rs6000_cost = &ppca2_cost;

58225

break;

58226

@@ -3274,7 +4049,8 @@

58227

&& (rs6000_cpu == PROCESSOR_POWER4

58228

|| rs6000_cpu == PROCESSOR_POWER5

58229

|| rs6000_cpu == PROCESSOR_POWER6

58230

- || rs6000_cpu == PROCESSOR_POWER7))

58231

+ || rs6000_cpu == PROCESSOR_POWER7

58232

+ || rs6000_cpu == PROCESSOR_POWER8))

58233

return 5;

58234

else

58235

return align_loops_log;

58236

@@ -3493,6 +4269,8 @@

58237

{

58238

case SFmode:

58239

return V4SFmode;

58240

+ case TImode:

58241

+ return V1TImode;

58242

case DImode:

58243

return V2DImode;

58244

case SImode:

58245

@@ -3813,6 +4591,22 @@

58246

enum built_in_function fn = DECL_FUNCTION_CODE (fndecl);

58247

switch (fn)

58248

{

58249

+ case BUILT_IN_CLZIMAX:

58250

+ case BUILT_IN_CLZLL:

58251

+ case BUILT_IN_CLZL:

58252

+ case BUILT_IN_CLZ:

58253

+ if (TARGET_P8_VECTOR && in_mode == out_mode && out_n == in_n)

58254

+ {

58255

+ if (out_mode == QImode && out_n == 16)

58256

+ return rs6000_builtin_decls[P8V_BUILTIN_VCLZB];

58257

+ else if (out_mode == HImode && out_n == 8)

58258

+ return rs6000_builtin_decls[P8V_BUILTIN_VCLZH];

58259

+ else if (out_mode == SImode && out_n == 4)

58260

+ return rs6000_builtin_decls[P8V_BUILTIN_VCLZW];

58261

+ else if (out_mode == DImode && out_n == 2)

58262

+ return rs6000_builtin_decls[P8V_BUILTIN_VCLZD];

58263

+ }

58264

+ break;

58265

case BUILT_IN_COPYSIGN:

58266

if (VECTOR_UNIT_VSX_P (V2DFmode)

58267

&& out_mode == DFmode && out_n == 2

58268

@@ -3828,6 +4622,22 @@

58269

if (VECTOR_UNIT_ALTIVEC_P (V4SFmode))

58270

return rs6000_builtin_decls[ALTIVEC_BUILTIN_COPYSIGN_V4SF];

58271

break;

58272

+ case BUILT_IN_POPCOUNTIMAX:

58273

+ case BUILT_IN_POPCOUNTLL:

58274

+ case BUILT_IN_POPCOUNTL:

58275

+ case BUILT_IN_POPCOUNT:

58276

+ if (TARGET_P8_VECTOR && in_mode == out_mode && out_n == in_n)

58277

+ {

58278

+ if (out_mode == QImode && out_n == 16)

58279

+ return rs6000_builtin_decls[P8V_BUILTIN_VPOPCNTB];

58280

+ else if (out_mode == HImode && out_n == 8)

58281

+ return rs6000_builtin_decls[P8V_BUILTIN_VPOPCNTH];

58282

+ else if (out_mode == SImode && out_n == 4)

58283

+ return rs6000_builtin_decls[P8V_BUILTIN_VPOPCNTW];

58284

+ else if (out_mode == DImode && out_n == 2)

58285

+ return rs6000_builtin_decls[P8V_BUILTIN_VPOPCNTD];

58286

+ }

58287

+ break;

58288

case BUILT_IN_SQRT:

58289

if (VECTOR_UNIT_VSX_P (V2DFmode)

58290

&& out_mode == DFmode && out_n == 2

58291

@@ -4043,7 +4853,11 @@

58292

putc ('\n', file);

58293

}

58294

58295

- if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))

58296

+ if (DEFAULT_ABI == ABI_ELFv2)

58297

+ fprintf (file, "\t.abiversion 2\n");

58298

+

58299

+ if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2

58300

+ || (TARGET_ELF && flag_pic == 2))

58301

{

58302

switch_to_section (toc_section);

58303

switch_to_section (text_section);

58304

@@ -4230,7 +5044,7 @@

58305

HOST_WIDE_INT splat_val;

58306

HOST_WIDE_INT msb_val;

58307

58308

- if (mode == V2DImode || mode == V2DFmode)

58309

+ if (mode == V2DImode || mode == V2DFmode || mode == V1TImode)

58310

return false;

58311

58312

nunits = GET_MODE_NUNITS (mode);

58313

@@ -4239,7 +5053,7 @@

58314

58315

val = const_vector_elt_as_int (op, BYTES_BIG_ENDIAN ? nunits - 1 : 0);

58316

splat_val = val;

58317

- msb_val = val > 0 ? 0 : -1;

58318

+ msb_val = val >= 0 ? 0 : -1;

58319

58320

/* Construct the value to be splatted, if possible. If not, return 0. */

58321

for (i = 2; i <= copies; i *= 2)

58322

@@ -4274,15 +5088,16 @@

58323

58324

/* Check if VAL is present in every STEP-th element, and the

58325

other elements are filled with its most significant bit. */

58326

- for (i = 0; i < nunits - 1; ++i)

58327

+ for (i = 1; i < nunits; ++i)

58328

{

58329

HOST_WIDE_INT desired_val;

58330

- if (((BYTES_BIG_ENDIAN ? i + 1 : i) & (step - 1)) == 0)

58331

+ unsigned elt = BYTES_BIG_ENDIAN ? nunits - 1 - i : i;

58332

+ if ((i & (step - 1)) == 0)

58333

desired_val = val;

58334

else

58335

desired_val = msb_val;

58336

58337

- if (desired_val != const_vector_elt_as_int (op, i))

58338

+ if (desired_val != const_vector_elt_as_int (op, elt))

58339

return false;

58340

}

58341

58342

@@ -4308,7 +5123,7 @@

58343

if (mode == V2DFmode)

58344

return zero_constant (op, mode);

58345

58346

- if (mode == V2DImode)

58347

+ else if (mode == V2DImode)

58348

{

58349

/* In case the compiler is built 32-bit, CONST_DOUBLE constants are not

58350

easy. */

58351

@@ -4326,6 +5141,10 @@

58352

return false;

58353

}

58354

58355

+ /* V1TImode is a special container for TImode. Ignore for now. */

58356

+ else if (mode == V1TImode)

58357

+ return false;

58358

+

58359

/* Start with a vspltisw. */

58360

step = GET_MODE_NUNITS (mode) / 4;

58361

copies = 1;

58362

@@ -4407,7 +5226,7 @@

58363

if (zero_constant (vec, mode))

58364

return "xxlxor %x0,%x0,%x0";

58365

58366

- if (mode == V2DImode

58367

+ if ((mode == V2DImode || mode == V1TImode)

58368

&& INTVAL (CONST_VECTOR_ELT (vec, 0)) == -1

58369

&& INTVAL (CONST_VECTOR_ELT (vec, 1)) == -1)

58370

return "vspltisw %0,-1";

58371

@@ -4698,9 +5517,12 @@

58372

{

58373

rtx freg = gen_reg_rtx (V4SFmode);

58374

rtx sreg = force_reg (SFmode, XVECEXP (vals, 0, 0));

58375

+ rtx cvt = ((TARGET_XSCVDPSPN)

58376

+ ? gen_vsx_xscvdpspn_scalar (freg, sreg)

58377

+ : gen_vsx_xscvdpsp_scalar (freg, sreg));

58378

58379

- emit_insn (gen_vsx_xscvdpsp_scalar (freg, sreg));

58380

- emit_insn (gen_vsx_xxspltw_v4sf (target, freg, const0_rtx));

58381

+ emit_insn (cvt);

58382

+ emit_insn (gen_vsx_xxspltw_v4sf_direct (target, freg, const0_rtx));

58383

}

58384

else

58385

{

58386

@@ -4790,6 +5612,13 @@

58387

return;

58388

}

58389

58390

+ /* Simplify setting single element vectors like V1TImode. */

58391

+ if (GET_MODE_SIZE (mode) == GET_MODE_SIZE (inner_mode) && elt == 0)

58392

+ {

58393

+ emit_move_insn (target, gen_lowpart (mode, val));

58394

+ return;

58395

+ }

58396

+

58397

/* Load single variable value. */

58398

mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode));

58399

emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);

58400

@@ -4811,10 +5640,29 @@

58401

XVECEXP (mask, 0, elt*width + i)

58402

= GEN_INT (i + 0x10);

58403

x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));

58404

- x = gen_rtx_UNSPEC (mode,

58405

- gen_rtvec (3, target, reg,

58406

- force_reg (V16QImode, x)),

58407

- UNSPEC_VPERM);

58408

+

58409

+ if (BYTES_BIG_ENDIAN)

58410

+ x = gen_rtx_UNSPEC (mode,

58411

+ gen_rtvec (3, target, reg,

58412

+ force_reg (V16QImode, x)),

58413

+ UNSPEC_VPERM);

58414

+ else

58415

+ {

58416

+ /* Invert selector. We prefer to generate VNAND on P8 so

58417

+ that future fusion opportunities can kick in, but must

58418

+ generate VNOR elsewhere. */

58419

+ rtx notx = gen_rtx_NOT (V16QImode, force_reg (V16QImode, x));

58420

+ rtx iorx = (TARGET_P8_VECTOR

58421

+ ? gen_rtx_IOR (V16QImode, notx, notx)

58422

+ : gen_rtx_AND (V16QImode, notx, notx));

58423

+ rtx tmp = gen_reg_rtx (V16QImode);

58424

+ emit_insn (gen_rtx_SET (VOIDmode, tmp, iorx));

58425

+

58426

+ /* Permute with operands reversed and adjusted selector. */

58427

+ x = gen_rtx_UNSPEC (mode, gen_rtvec (3, reg, target, tmp),

58428

+ UNSPEC_VPERM);

58429

+ }

58430

+

58431

emit_insn (gen_rtx_SET (VOIDmode, target, x));

58432

}

58433

58434

@@ -4833,6 +5681,10 @@

58435

{

58436

default:

58437

break;

58438

+ case V1TImode:

58439

+ gcc_assert (elt == 0 && inner_mode == TImode);

58440

+ emit_move_insn (target, gen_lowpart (TImode, vec));

58441

+ break;

58442

case V2DFmode:

58443

emit_insn (gen_vsx_extract_v2df (target, vec, GEN_INT (elt)));

58444

return;

58445

@@ -4938,7 +5790,7 @@

58446

purpose. */

58447

if (GET_CODE (op) == SUBREG

58448

&& (mode == SImode || mode == DImode || mode == TImode

58449

- || mode == DDmode || mode == TDmode)

58450

+ || mode == DDmode || mode == TDmode || mode == PTImode)

58451

&& REG_P (SUBREG_REG (op))

58452

&& (GET_MODE (SUBREG_REG (op)) == DFmode

58453

|| GET_MODE (SUBREG_REG (op)) == TFmode))

58454

@@ -4951,6 +5803,7 @@

58455

&& REG_P (SUBREG_REG (op))

58456

&& (GET_MODE (SUBREG_REG (op)) == DImode

58457

|| GET_MODE (SUBREG_REG (op)) == TImode

58458

+ || GET_MODE (SUBREG_REG (op)) == PTImode

58459

|| GET_MODE (SUBREG_REG (op)) == DDmode

58460

|| GET_MODE (SUBREG_REG (op)) == TDmode))

58461

return true;

58462

@@ -4966,6 +5819,48 @@

58463

return false;

58464

}

58465

58466

+/* Return alignment of TYPE. Existing alignment is ALIGN. HOW

58467

+ selects whether the alignment is abi mandated, optional, or

58468

+ both abi and optional alignment. */

58469

+

58470

+unsigned int

58471

+rs6000_data_alignment (tree type, unsigned int align, enum data_align how)

58472

+{

58473

+ if (how != align_opt)

58474

+ {

58475

+ if (TREE_CODE (type) == VECTOR_TYPE)

58476

+ {

58477

+ if ((TARGET_SPE && SPE_VECTOR_MODE (TYPE_MODE (type)))

58478

+ || (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (TYPE_MODE (type))))

58479

+ {

58480

+ if (align < 64)

58481

+ align = 64;

58482

+ }

58483

+ else if (align < 128)

58484

+ align = 128;

58485

+ }

58486

+ else if (TARGET_E500_DOUBLE

58487

+ && TREE_CODE (type) == REAL_TYPE

58488

+ && TYPE_MODE (type) == DFmode)

58489

+ {

58490

+ if (align < 64)

58491

+ align = 64;

58492

+ }

58493

+ }

58494

+

58495

+ if (how != align_abi)

58496

+ {

58497

+ if (TREE_CODE (type) == ARRAY_TYPE

58498

+ && TYPE_MODE (TREE_TYPE (type)) == QImode)

58499

+ {

58500

+ if (align < BITS_PER_WORD)

58501

+ align = BITS_PER_WORD;

58502

+ }

58503

+ }

58504

+

58505

+ return align;

58506

+}

58507

+

58508

/* AIX increases natural record alignment to doubleword if the first

58509

field is an FP double while the FP fields remain word aligned. */

58510

58511

@@ -5087,6 +5982,73 @@

58512

|| (REG_P (op1) && INT_REGNO_P (REGNO (op1))));

58513

}

58514

58515

+/* Return true if this is a move direct operation between GPR registers and

58516

+ floating point/VSX registers. */

58517

+

58518

+bool

58519

+direct_move_p (rtx op0, rtx op1)

58520

+{

58521

+ int regno0, regno1;

58522

+

58523

+ if (!REG_P (op0) || !REG_P (op1))

58524

+ return false;

58525

+

58526

+ if (!TARGET_DIRECT_MOVE && !TARGET_MFPGPR)

58527

+ return false;

58528

+

58529

+ regno0 = REGNO (op0);

58530

+ regno1 = REGNO (op1);

58531

+ if (regno0 >= FIRST_PSEUDO_REGISTER || regno1 >= FIRST_PSEUDO_REGISTER)

58532

+ return false;

58533

+

58534

+ if (INT_REGNO_P (regno0))

58535

+ return (TARGET_DIRECT_MOVE) ? VSX_REGNO_P (regno1) : FP_REGNO_P (regno1);

58536

+

58537

+ else if (INT_REGNO_P (regno1))

58538

+ {

58539

+ if (TARGET_MFPGPR && FP_REGNO_P (regno0))

58540

+ return true;

58541

+

58542

+ else if (TARGET_DIRECT_MOVE && VSX_REGNO_P (regno0))

58543

+ return true;

58544

+ }

58545

+

58546

+ return false;

58547

+}

58548

+

58549

+/* Return true if this is a load or store quad operation. This function does

58550

+ not handle the atomic quad memory instructions. */

58551

+

58552

+bool

58553

+quad_load_store_p (rtx op0, rtx op1)

58554

+{

58555

+ bool ret;

58556

+

58557

+ if (!TARGET_QUAD_MEMORY)

58558

+ ret = false;

58559

+

58560

+ else if (REG_P (op0) && MEM_P (op1))

58561

+ ret = (quad_int_reg_operand (op0, GET_MODE (op0))

58562

+ && quad_memory_operand (op1, GET_MODE (op1))

58563

+ && !reg_overlap_mentioned_p (op0, op1));

58564

+

58565

+ else if (MEM_P (op0) && REG_P (op1))

58566

+ ret = (quad_memory_operand (op0, GET_MODE (op0))

58567

+ && quad_int_reg_operand (op1, GET_MODE (op1)));

58568

+

58569

+ else

58570

+ ret = false;

58571

+

58572

+ if (TARGET_DEBUG_ADDR)

58573

+ {

58574

+ fprintf (stderr, "\n========== quad_load_store, return %s\n",

58575

+ ret ? "true" : "false");

58576

+ debug_rtx (gen_rtx_SET (VOIDmode, op0, op1));

58577

+ }

58578

+

58579

+ return ret;

58580

+}

58581

+

58582

/* Given an address, return a constant offset term if one exists. */

58583

58584

static rtx

58585

@@ -5170,7 +6132,12 @@

58586

case V4SImode:

58587

case V2DFmode:

58588

case V2DImode:

58589

- /* AltiVec/VSX vector modes. Only reg+reg addressing is valid. */

58590

+ case V1TImode:

58591

+ case TImode:

58592

+ /* AltiVec/VSX vector modes. Only reg+reg addressing is valid. While

58593

+ TImode is not a vector mode, if we want to use the VSX registers to

58594

+ move it around, we need to restrict ourselves to reg+reg

58595

+ addressing. */

58596

if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))

58597

return false;

58598

break;

58599

@@ -5184,6 +6151,13 @@

58600

return false;

58601

break;

58602

58603

+ case SDmode:

58604

+ /* If we can do direct load/stores of SDmode, restrict it to reg+reg

58605

+ addressing for the LFIWZX and STFIWX instructions. */

58606

+ if (TARGET_NO_SDMODE_STACK)

58607

+ return false;

58608

+ break;

58609

+

58610

default:

58611

break;

58612

}

58613

@@ -5211,8 +6185,8 @@

58614

&& regnum <= LAST_VIRTUAL_POINTER_REGISTER);

58615

}

58616

58617

-/* Return true if memory accesses to OP are known to never straddle

58618

- a 32k boundary. */

58619

+/* Return true if a MODE sized memory accesses to OP plus OFFSET

58620

+ is known to not straddle a 32k boundary. */

58621

58622

static bool

58623

offsettable_ok_by_alignment (rtx op, HOST_WIDE_INT offset,

58624

@@ -5219,15 +6193,16 @@

58625

enum machine_mode mode)

58626

{

58627

tree decl, type;

58628

- unsigned HOST_WIDE_INT dsize, dalign;

58629

+ unsigned HOST_WIDE_INT dsize, dalign, lsb, mask;

58630

58631

if (GET_CODE (op) != SYMBOL_REF)

58632

return false;

58633

58634

+ dsize = GET_MODE_SIZE (mode);

58635

decl = SYMBOL_REF_DECL (op);

58636

if (!decl)

58637

{

58638

- if (GET_MODE_SIZE (mode) == 0)

58639

+ if (dsize == 0)

58640

return false;

58641

58642

/* -fsection-anchors loses the original SYMBOL_REF_DECL when

58643

@@ -5234,68 +6209,78 @@

58644

replacing memory addresses with an anchor plus offset. We

58645

could find the decl by rummaging around in the block->objects

58646

VEC for the given offset but that seems like too much work. */

58647

- dalign = 1;

58648

+ dalign = BITS_PER_UNIT;

58649

if (SYMBOL_REF_HAS_BLOCK_INFO_P (op)

58650

&& SYMBOL_REF_ANCHOR_P (op)

58651

&& SYMBOL_REF_BLOCK (op) != NULL)

58652

{

58653

struct object_block *block = SYMBOL_REF_BLOCK (op);

58654

- HOST_WIDE_INT lsb, mask;

58655

58656

- /* Given the alignment of the block.. */

58657

dalign = block->alignment;

58658

- mask = dalign / BITS_PER_UNIT - 1;

58659

-

58660

- /* ..and the combined offset of the anchor and any offset

58661

- to this block object.. */

58662

offset += SYMBOL_REF_BLOCK_OFFSET (op);

58663

- lsb = offset & -offset;

58664

+ }

58665

+ else if (CONSTANT_POOL_ADDRESS_P (op))

58666

+ {

58667

+ /* It would be nice to have get_pool_align().. */

58668

+ enum machine_mode cmode = get_pool_mode (op);

58669

58670

- /* ..find how many bits of the alignment we know for the

58671

- object. */

58672

- mask &= lsb - 1;

58673

- dalign = mask + 1;

58674

+ dalign = GET_MODE_ALIGNMENT (cmode);

58675

}

58676

- return dalign >= GET_MODE_SIZE (mode);

58677

}

58678

-

58679

- if (DECL_P (decl))

58680

+ else if (DECL_P (decl))

58681

{

58682

- if (TREE_CODE (decl) == FUNCTION_DECL)

58683

- return true;

58684

+ dalign = DECL_ALIGN (decl);

58685

58686

- if (!DECL_SIZE_UNIT (decl))

58687

- return false;

58688

+ if (dsize == 0)

58689

+ {

58690

+ /* Allow BLKmode when the entire object is known to not

58691

+ cross a 32k boundary. */

58692

+ if (!DECL_SIZE_UNIT (decl))

58693

+ return false;

58694

58695

- if (!host_integerp (DECL_SIZE_UNIT (decl), 1))

58696

- return false;

58697

+ if (!host_integerp (DECL_SIZE_UNIT (decl), 1))

58698

+ return false;

58699

58700

- dsize = tree_low_cst (DECL_SIZE_UNIT (decl), 1);

58701

- if (dsize > 32768)

58702

- return false;

58703

+ dsize = tree_low_cst (DECL_SIZE_UNIT (decl), 1);

58704

+ if (dsize > 32768)

58705

+ return false;

58706

58707

- dalign = DECL_ALIGN_UNIT (decl);

58708

- return dalign >= dsize;

58709

+ return dalign / BITS_PER_UNIT >= dsize;

58710

+ }

58711

}

58712

+ else

58713

+ {

58714

+ type = TREE_TYPE (decl);

58715

58716

- type = TREE_TYPE (decl);

58717

+ dalign = TYPE_ALIGN (type);

58718

+ if (CONSTANT_CLASS_P (decl))

58719

+ dalign = CONSTANT_ALIGNMENT (decl, dalign);

58720

+ else

58721

+ dalign = DATA_ALIGNMENT (decl, dalign);

58722

58723

- if (TREE_CODE (decl) == STRING_CST)

58724

- dsize = TREE_STRING_LENGTH (decl);

58725

- else if (TYPE_SIZE_UNIT (type)

58726

- && host_integerp (TYPE_SIZE_UNIT (type), 1))

58727

- dsize = tree_low_cst (TYPE_SIZE_UNIT (type), 1);

58728

- else

58729

- return false;

58730

- if (dsize > 32768)

58731

- return false;

58732

+ if (dsize == 0)

58733

+ {

58734

+ /* BLKmode, check the entire object. */

58735

+ if (TREE_CODE (decl) == STRING_CST)

58736

+ dsize = TREE_STRING_LENGTH (decl);

58737

+ else if (TYPE_SIZE_UNIT (type)

58738

+ && host_integerp (TYPE_SIZE_UNIT (type), 1))

58739

+ dsize = tree_low_cst (TYPE_SIZE_UNIT (type), 1);

58740

+ else

58741

+ return false;

58742

+ if (dsize > 32768)

58743

+ return false;

58744

58745

- dalign = TYPE_ALIGN (type);

58746

- if (CONSTANT_CLASS_P (decl))

58747

- dalign = CONSTANT_ALIGNMENT (decl, dalign);

58748

- else

58749

- dalign = DATA_ALIGNMENT (decl, dalign);

58750

- dalign /= BITS_PER_UNIT;

58751

+ return dalign / BITS_PER_UNIT >= dsize;

58752

+ }

58753

+ }

58754

+

58755

+ /* Find how many bits of the alignment we know for this access. */

58756

+ mask = dalign / BITS_PER_UNIT - 1;

58757

+ lsb = offset & -offset;

58758

+ mask &= lsb - 1;

58759

+ dalign = mask + 1;

58760

+

58761

return dalign >= dsize;

58762

}

58763

58764

@@ -5387,7 +6372,7 @@

58765

return false;

58766

if (!reg_offset_addressing_ok_p (mode))

58767

return virtual_stack_registers_memory_p (x);

58768

- if (legitimate_constant_pool_address_p (x, mode, strict))

58769

+ if (legitimate_constant_pool_address_p (x, mode, strict || lra_in_progress))

58770

return true;

58771

if (GET_CODE (XEXP (x, 1)) != CONST_INT)

58772

return false;

58773

@@ -5416,7 +6401,7 @@

58774

58775

/* If we are using VSX scalar loads, restrict ourselves to reg+reg

58776

addressing. */

58777

- if (mode == DFmode && VECTOR_MEM_VSX_P (DFmode))

58778

+ if (VECTOR_MEM_VSX_P (mode))

58779

return false;

58780

58781

if (!worst_case)

58782

@@ -5428,12 +6413,14 @@

58783

break;

58784

58785

case TFmode:

58786

- case TDmode:

58787

- case TImode:

58788

if (TARGET_E500_DOUBLE)

58789

return (SPE_CONST_OFFSET_OK (offset)

58790

&& SPE_CONST_OFFSET_OK (offset + 8));

58791

+ /* fall through */

58792

58793

+ case TDmode:

58794

+ case TImode:

58795

+ case PTImode:

58796

extra = 8;

58797

if (!worst_case)

58798

break;

58799

@@ -5526,9 +6513,21 @@

58800

58801

if (TARGET_ELF || TARGET_MACHO)

58802

{

58803

- if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)

58804

+ bool large_toc_ok;

58805

+

58806

+ if (DEFAULT_ABI == ABI_V4 && flag_pic)

58807

return false;

58808

- if (TARGET_TOC)

58809

+ /* LRA don't use LEGITIMIZE_RELOAD_ADDRESS as it usually calls

58810

+ push_reload from reload pass code. LEGITIMIZE_RELOAD_ADDRESS

58811

+ recognizes some LO_SUM addresses as valid although this

58812

+ function says opposite. In most cases, LRA through different

58813

+ transformations can generate correct code for address reloads.

58814

+ It can not manage only some LO_SUM cases. So we need to add

58815

+ code analogous to one in rs6000_legitimize_reload_address for

58816

+ LOW_SUM here saying that some addresses are still valid. */

58817

+ large_toc_ok = (lra_in_progress && TARGET_CMODEL != CMODEL_SMALL

58818

+ && small_toc_ref (x, VOIDmode));

58819

+ if (TARGET_TOC && ! large_toc_ok)

58820

return false;

58821

if (GET_MODE_NUNITS (mode) != 1)

58822

return false;

58823

@@ -5538,7 +6537,7 @@

58824

&& (mode == DFmode || mode == DDmode)))

58825

return false;

58826

58827

- return CONSTANT_P (x);

58828

+ return CONSTANT_P (x) || large_toc_ok;

58829

}

58830

58831

return false;

58832

@@ -5582,8 +6581,11 @@

58833

if (GET_CODE (x) == PLUS && XEXP (x, 1) == const0_rtx)

58834

return force_reg (Pmode, XEXP (x, 0));

58835

58836

+ /* For TImode with load/store quad, restrict addresses to just a single

58837

+ pointer, so it works with both GPRs and VSX registers. */

58838

/* Make sure both operands are registers. */

58839

- else if (GET_CODE (x) == PLUS)

58840

+ else if (GET_CODE (x) == PLUS

58841

+ && (mode != TImode || !TARGET_QUAD_MEMORY))

58842

return gen_rtx_PLUS (Pmode,

58843

force_reg (Pmode, XEXP (x, 0)),

58844

force_reg (Pmode, XEXP (x, 1)));

58845

@@ -5603,11 +6605,12 @@

58846

case TFmode:

58847

case TDmode:

58848

case TImode:

58849

+ case PTImode:

58850

/* As in legitimate_offset_address_p we do not assume

58851

worst-case. The mode here is just a hint as to the registers

58852

used. A TImode is usually in gprs, but may actually be in

58853

fprs. Leave worst-case scenario for reload to handle via

58854

- insn constraints. */

58855

+ insn constraints. PTImode is only GPRs. */

58856

extra = 8;

58857

break;

58858

default:

58859

@@ -6099,10 +7102,13 @@

58860

1, const0_rtx, Pmode);

58861

58862

r3 = gen_rtx_REG (Pmode, 3);

58863

- if (DEFAULT_ABI == ABI_AIX && TARGET_64BIT)

58864

- insn = gen_tls_gd_aix64 (r3, got, addr, tga, const0_rtx);

58865

- else if (DEFAULT_ABI == ABI_AIX && !TARGET_64BIT)

58866

- insn = gen_tls_gd_aix32 (r3, got, addr, tga, const0_rtx);

58867

+ if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)

58868

+ {

58869

+ if (TARGET_64BIT)

58870

+ insn = gen_tls_gd_aix64 (r3, got, addr, tga, const0_rtx);

58871

+ else

58872

+ insn = gen_tls_gd_aix32 (r3, got, addr, tga, const0_rtx);

58873

+ }

58874

else if (DEFAULT_ABI == ABI_V4)

58875

insn = gen_tls_gd_sysvsi (r3, got, addr, tga, const0_rtx);

58876

else

58877

@@ -6121,10 +7127,13 @@

58878

1, const0_rtx, Pmode);

58879

58880

r3 = gen_rtx_REG (Pmode, 3);

58881

- if (DEFAULT_ABI == ABI_AIX && TARGET_64BIT)

58882

- insn = gen_tls_ld_aix64 (r3, got, tga, const0_rtx);

58883

- else if (DEFAULT_ABI == ABI_AIX && !TARGET_64BIT)

58884

- insn = gen_tls_ld_aix32 (r3, got, tga, const0_rtx);

58885

+ if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)

58886

+ {

58887

+ if (TARGET_64BIT)

58888

+ insn = gen_tls_ld_aix64 (r3, got, tga, const0_rtx);

58889

+ else

58890

+ insn = gen_tls_ld_aix32 (r3, got, tga, const0_rtx);

58891

+ }

58892

else if (DEFAULT_ABI == ABI_V4)

58893

insn = gen_tls_ld_sysvsi (r3, got, tga, const0_rtx);

58894

else

58895

@@ -6239,7 +7248,6 @@

58896

&& ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (sym),

58897

get_pool_mode (sym)))

58898

|| (TARGET_CMODEL == CMODEL_MEDIUM

58899

- && !CONSTANT_POOL_ADDRESS_P (sym)

58900

&& SYMBOL_REF_LOCAL_P (sym)));

58901

}

58902

58903

@@ -6338,7 +7346,7 @@

58904

&& !(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode

58905

|| mode == DDmode || mode == TDmode

58906

|| mode == DImode))

58907

- && VECTOR_MEM_NONE_P (mode))

58908

+ && (!VECTOR_MODE_P (mode) || VECTOR_MEM_NONE_P (mode)))

58909

{

58910

HOST_WIDE_INT val = INTVAL (XEXP (x, 1));

58911

HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;

58912

@@ -6369,7 +7377,7 @@

58913

58914

if (GET_CODE (x) == SYMBOL_REF

58915

&& reg_offset_p

58916

- && VECTOR_MEM_NONE_P (mode)

58917

+ && (!VECTOR_MODE_P (mode) || VECTOR_MEM_NONE_P (mode))

58918

&& !SPE_VECTOR_MODE (mode)

58919

#if TARGET_MACHO

58920

&& DEFAULT_ABI == ABI_DARWIN

58921

@@ -6395,6 +7403,8 @@

58922

mem is sufficiently aligned. */

58923

&& mode != TFmode

58924

&& mode != TDmode

58925

+ && (mode != TImode || !TARGET_VSX_TIMODE)

58926

+ && mode != PTImode

58927

&& (mode != DImode || TARGET_POWERPC64)

58928

&& ((mode != DFmode && mode != DDmode) || TARGET_POWERPC64

58929

|| (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)))

58930

@@ -6515,15 +7525,9 @@

58931

return 0;

58932

if (legitimate_indirect_address_p (x, reg_ok_strict))

58933

return 1;

58934

- if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)

58935

- && !VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)

58936

- && !SPE_VECTOR_MODE (mode)

58937

- && mode != TFmode

58938

- && mode != TDmode

58939

- /* Restrict addressing for DI because of our SUBREG hackery. */

58940

- && !(TARGET_E500_DOUBLE

58941

- && (mode == DFmode || mode == DDmode || mode == DImode))

58942

- && TARGET_UPDATE

58943

+ if (TARGET_UPDATE

58944

+ && (GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)

58945

+ && mode_supports_pre_incdec_p (mode)

58946

&& legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))

58947

return 1;

58948

if (virtual_stack_registers_memory_p (x))

58949

@@ -6531,8 +7535,16 @@

58950

if (reg_offset_p && legitimate_small_data_p (mode, x))

58951

return 1;

58952

if (reg_offset_p

58953

- && legitimate_constant_pool_address_p (x, mode, reg_ok_strict))

58954

+ && legitimate_constant_pool_address_p (x, mode,

58955

+ reg_ok_strict || lra_in_progress))

58956

return 1;

58957

+ /* For TImode, if we have load/store quad and TImode in VSX registers, only

58958

+ allow register indirect addresses. This will allow the values to go in

58959

+ either GPRs or VSX registers without reloading. The vector types would

58960

+ tend to go into VSX registers, so we allow REG+REG, while TImode seems

58961

+ somewhat split, in that some uses are GPR based, and some VSX based. */

58962

+ if (mode == TImode && TARGET_QUAD_MEMORY && TARGET_VSX_TIMODE)

58963

+ return 0;

58964

/* If not REG_OK_STRICT (before reload) let pass any stack offset. */

58965

if (! reg_ok_strict

58966

&& reg_offset_p

58967

@@ -6544,8 +7556,7 @@

58968

return 1;

58969

if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict, false))

58970

return 1;

58971

- if (mode != TImode

58972

- && mode != TFmode

58973

+ if (mode != TFmode

58974

&& mode != TDmode

58975

&& ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)

58976

|| TARGET_POWERPC64

58977

@@ -6552,23 +7563,13 @@

58978

|| (mode != DFmode && mode != DDmode)

58979

|| (TARGET_E500_DOUBLE && mode != DDmode))

58980

&& (TARGET_POWERPC64 || mode != DImode)

58981

+ && (mode != TImode || VECTOR_MEM_VSX_P (TImode))

58982

+ && mode != PTImode

58983

&& !avoiding_indexed_address_p (mode)

58984

&& legitimate_indexed_address_p (x, reg_ok_strict))

58985

return 1;

58986

- if (GET_CODE (x) == PRE_MODIFY

58987

- && mode != TImode

58988

- && mode != TFmode

58989

- && mode != TDmode

58990

- && ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)

58991

- || TARGET_POWERPC64

58992

- || ((mode != DFmode && mode != DDmode) || TARGET_E500_DOUBLE))

58993

- && (TARGET_POWERPC64 || mode != DImode)

58994

- && !VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)

58995

- && !SPE_VECTOR_MODE (mode)

58996

- /* Restrict addressing for DI because of our SUBREG hackery. */

58997

- && !(TARGET_E500_DOUBLE

58998

- && (mode == DFmode || mode == DDmode || mode == DImode))

58999

- && TARGET_UPDATE

59000

+ if (TARGET_UPDATE && GET_CODE (x) == PRE_MODIFY

59001

+ && mode_supports_pre_modify_p (mode)

59002

&& legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)

59003

&& (rs6000_legitimate_offset_address_p (mode, XEXP (x, 1),

59004

reg_ok_strict, false)

59005

@@ -6589,10 +7590,13 @@

59006

bool ret = rs6000_legitimate_address_p (mode, x, reg_ok_strict);

59007

fprintf (stderr,

59008

"\nrs6000_legitimate_address_p: return = %s, mode = %s, "

59009

- "strict = %d, code = %s\n",

59010

+ "strict = %d, reload = %s, code = %s\n",

59011

ret ? "true" : "false",

59012

GET_MODE_NAME (mode),

59013

reg_ok_strict,

59014

+ (reload_completed

59015

+ ? "after"

59016

+ : (reload_in_progress ? "progress" : "before")),

59017

GET_RTX_NAME (GET_CODE (x)));

59018

debug_rtx (x);

59019

59020

@@ -6758,7 +7762,7 @@

59021

59022

/* The TOC register is not killed across calls in a way that is

59023

visible to the compiler. */

59024

- if (DEFAULT_ABI == ABI_AIX)

59025

+ if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)

59026

call_really_used_regs[2] = 0;

59027

59028

if (DEFAULT_ABI == ABI_V4

59029

@@ -6818,6 +7822,7 @@

59030

fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;

59031

}

59032

}

59033

+

59034

59035

/* Try to output insns to set TARGET equal to the constant C if it can

59036

be done in less than N insns. Do all computations in MODE.

59037

@@ -7006,7 +8011,7 @@

59038

}

59039

59040

/* Helper for the following. Get rid of [r+r] memory refs

59041

- in cases where it won't work (TImode, TFmode, TDmode). */

59042

+ in cases where it won't work (TImode, TFmode, TDmode, PTImode). */

59043

59044

static void

59045

rs6000_eliminate_indexed_memrefs (rtx operands[2])

59046

@@ -7031,6 +8036,131 @@

59047

copy_addr_to_reg (XEXP (operands[1], 0)));

59048

}

59049

59050

+/* Generate a vector of constants to permute MODE for a little-endian

59051

+ storage operation by swapping the two halves of a vector. */

59052

+static rtvec

59053

+rs6000_const_vec (enum machine_mode mode)

59054

+{

59055

+ int i, subparts;

59056

+ rtvec v;

59057

+

59058

+ switch (mode)

59059

+ {

59060

+ case V1TImode:

59061

+ subparts = 1;

59062

+ break;

59063

+ case V2DFmode:

59064

+ case V2DImode:

59065

+ subparts = 2;

59066

+ break;

59067

+ case V4SFmode:

59068

+ case V4SImode:

59069

+ subparts = 4;

59070

+ break;

59071

+ case V8HImode:

59072

+ subparts = 8;

59073

+ break;

59074

+ case V16QImode:

59075

+ subparts = 16;

59076

+ break;

59077

+ default:

59078

+ gcc_unreachable();

59079

+ }

59080

+

59081

+ v = rtvec_alloc (subparts);

59082

+

59083

+ for (i = 0; i < subparts / 2; ++i)

59084

+ RTVEC_ELT (v, i) = gen_rtx_CONST_INT (DImode, i + subparts / 2);

59085

+ for (i = subparts / 2; i < subparts; ++i)

59086

+ RTVEC_ELT (v, i) = gen_rtx_CONST_INT (DImode, i - subparts / 2);

59087

+

59088

+ return v;

59089

+}

59090

+

59091

+/* Generate a permute rtx that represents an lxvd2x, stxvd2x, or xxpermdi

59092

+ for a VSX load or store operation. */

59093

+rtx

59094

+rs6000_gen_le_vsx_permute (rtx source, enum machine_mode mode)

59095

+{

59096

+ rtx par = gen_rtx_PARALLEL (VOIDmode, rs6000_const_vec (mode));

59097

+ return gen_rtx_VEC_SELECT (mode, source, par);

59098

+}

59099

+

59100

+/* Emit a little-endian load from vector memory location SOURCE to VSX

59101

+ register DEST in mode MODE. The load is done with two permuting

59102

+ insn's that represent an lxvd2x and xxpermdi. */

59103

+void

59104

+rs6000_emit_le_vsx_load (rtx dest, rtx source, enum machine_mode mode)

59105

+{

59106

+ rtx tmp, permute_mem, permute_reg;

59107

+

59108

+ /* Use V2DImode to do swaps of types with 128-bit scalare parts (TImode,

59109

+ V1TImode). */

59110

+ if (mode == TImode || mode == V1TImode)

59111

+ {

59112

+ mode = V2DImode;

59113

+ dest = gen_lowpart (V2DImode, dest);

59114

+ source = adjust_address (source, V2DImode, 0);

59115

+ }

59116

+

59117

+ tmp = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (dest) : dest;

59118

+ permute_mem = rs6000_gen_le_vsx_permute (source, mode);

59119

+ permute_reg = rs6000_gen_le_vsx_permute (tmp, mode);

59120

+ emit_insn (gen_rtx_SET (VOIDmode, tmp, permute_mem));

59121

+ emit_insn (gen_rtx_SET (VOIDmode, dest, permute_reg));

59122

+}

59123

+

59124

+/* Emit a little-endian store to vector memory location DEST from VSX

59125

+ register SOURCE in mode MODE. The store is done with two permuting

59126

+ insn's that represent an xxpermdi and an stxvd2x. */

59127

+void

59128

+rs6000_emit_le_vsx_store (rtx dest, rtx source, enum machine_mode mode)

59129

+{

59130

+ rtx tmp, permute_src, permute_tmp;

59131

+

59132

+ /* Use V2DImode to do swaps of types with 128-bit scalare parts (TImode,

59133

+ V1TImode). */

59134

+ if (mode == TImode || mode == V1TImode)

59135

+ {

59136

+ mode = V2DImode;

59137

+ dest = adjust_address (dest, V2DImode, 0);

59138

+ source = gen_lowpart (V2DImode, source);

59139

+ }

59140

+

59141

+ tmp = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (source) : source;

59142

+ permute_src = rs6000_gen_le_vsx_permute (source, mode);

59143

+ permute_tmp = rs6000_gen_le_vsx_permute (tmp, mode);

59144

+ emit_insn (gen_rtx_SET (VOIDmode, tmp, permute_src));

59145

+ emit_insn (gen_rtx_SET (VOIDmode, dest, permute_tmp));

59146

+}

59147

+

59148

+/* Emit a sequence representing a little-endian VSX load or store,

59149

+ moving data from SOURCE to DEST in mode MODE. This is done

59150

+ separately from rs6000_emit_move to ensure it is called only

59151

+ during expand. LE VSX loads and stores introduced later are

59152

+ handled with a split. The expand-time RTL generation allows

59153

+ us to optimize away redundant pairs of register-permutes. */

59154

+void

59155

+rs6000_emit_le_vsx_move (rtx dest, rtx source, enum machine_mode mode)

59156

+{

59157

+ gcc_assert (!BYTES_BIG_ENDIAN

59158

+ && VECTOR_MEM_VSX_P (mode)

59159

+ && !gpr_or_gpr_p (dest, source)

59160

+ && (MEM_P (source) ^ MEM_P (dest)));

59161

+

59162

+ if (MEM_P (source))

59163

+ {

59164

+ gcc_assert (REG_P (dest) || GET_CODE (dest) == SUBREG);

59165

+ rs6000_emit_le_vsx_load (dest, source, mode);

59166

+ }

59167

+ else

59168

+ {

59169

+ if (!REG_P (source))

59170

+ source = force_reg (mode, source);

59171

+ rs6000_emit_le_vsx_store (dest, source, mode);

59172

+ }

59173

+}

59174

+

59175

/* Emit a move from SOURCE to DEST in mode MODE. */

59176

void

59177

rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)

59178

@@ -7149,8 +8279,71 @@

59179

cfun->machine->sdmode_stack_slot =

59180

eliminate_regs (cfun->machine->sdmode_stack_slot, VOIDmode, NULL_RTX);

59181

59182

+

59183

+ if (lra_in_progress

59184

+ && mode == SDmode

59185

+ && REG_P (operands[0]) && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER

59186

+ && reg_preferred_class (REGNO (operands[0])) == NO_REGS

59187

+ && (REG_P (operands[1])

59188

+ || (GET_CODE (operands[1]) == SUBREG

59189

+ && REG_P (SUBREG_REG (operands[1])))))

59190

+ {

59191

+ int regno = REGNO (GET_CODE (operands[1]) == SUBREG

59192

+ ? SUBREG_REG (operands[1]) : operands[1]);

59193

+ enum reg_class cl;

59194

+

59195

+ if (regno >= FIRST_PSEUDO_REGISTER)

59196

+ {

59197

+ cl = reg_preferred_class (regno);

59198

+ gcc_assert (cl != NO_REGS);

59199

+ regno = ira_class_hard_regs[cl][0];

59200

+ }

59201

+ if (FP_REGNO_P (regno))

59202

+ {

59203

+ if (GET_MODE (operands[0]) != DDmode)

59204

+ operands[0] = gen_rtx_SUBREG (DDmode, operands[0], 0);

59205

+ emit_insn (gen_movsd_store (operands[0], operands[1]));

59206

+ }

59207

+ else if (INT_REGNO_P (regno))

59208

+ emit_insn (gen_movsd_hardfloat (operands[0], operands[1]));

59209

+ else

59210

+ gcc_unreachable();

59211

+ return;

59212

+ }

59213

+ if (lra_in_progress

59214

+ && mode == SDmode

59215

+ && (REG_P (operands[0])

59216

+ || (GET_CODE (operands[0]) == SUBREG

59217

+ && REG_P (SUBREG_REG (operands[0]))))

59218

+ && REG_P (operands[1]) && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER

59219

+ && reg_preferred_class (REGNO (operands[1])) == NO_REGS)

59220

+ {

59221

+ int regno = REGNO (GET_CODE (operands[0]) == SUBREG

59222

+ ? SUBREG_REG (operands[0]) : operands[0]);

59223

+ enum reg_class cl;

59224

+

59225

+ if (regno >= FIRST_PSEUDO_REGISTER)

59226

+ {

59227

+ cl = reg_preferred_class (regno);

59228

+ gcc_assert (cl != NO_REGS);

59229

+ regno = ira_class_hard_regs[cl][0];

59230

+ }

59231

+ if (FP_REGNO_P (regno))

59232

+ {

59233

+ if (GET_MODE (operands[1]) != DDmode)

59234

+ operands[1] = gen_rtx_SUBREG (DDmode, operands[1], 0);

59235

+ emit_insn (gen_movsd_load (operands[0], operands[1]));

59236

+ }

59237

+ else if (INT_REGNO_P (regno))

59238

+ emit_insn (gen_movsd_hardfloat (operands[0], operands[1]));

59239

+ else

59240

+ gcc_unreachable();

59241

+ return;

59242

+ }

59243

+

59244

if (reload_in_progress

59245

&& mode == SDmode

59246

+ && cfun->machine->sdmode_stack_slot != NULL_RTX

59247

&& MEM_P (operands[0])

59248

&& rtx_equal_p (operands[0], cfun->machine->sdmode_stack_slot)

59249

&& REG_P (operands[1]))

59250

@@ -7163,7 +8356,9 @@

59251

}

59252

else if (INT_REGNO_P (REGNO (operands[1])))

59253

{

59254

- rtx mem = adjust_address_nv (operands[0], mode, 4);

59255

+ rtx mem = operands[0];

59256

+ if (BYTES_BIG_ENDIAN)

59257

+ mem = adjust_address_nv (mem, mode, 4);

59258

mem = eliminate_regs (mem, VOIDmode, NULL_RTX);

59259

emit_insn (gen_movsd_hardfloat (mem, operands[1]));

59260

}

59261

@@ -7175,6 +8370,7 @@

59262

&& mode == SDmode

59263

&& REG_P (operands[0])

59264

&& MEM_P (operands[1])

59265

+ && cfun->machine->sdmode_stack_slot != NULL_RTX

59266

&& rtx_equal_p (operands[1], cfun->machine->sdmode_stack_slot))

59267

{

59268

if (FP_REGNO_P (REGNO (operands[0])))

59269

@@ -7185,7 +8381,9 @@

59270

}

59271

else if (INT_REGNO_P (REGNO (operands[0])))

59272

{

59273

- rtx mem = adjust_address_nv (operands[1], mode, 4);

59274

+ rtx mem = operands[1];

59275

+ if (BYTES_BIG_ENDIAN)

59276

+ mem = adjust_address_nv (mem, mode, 4);

59277

mem = eliminate_regs (mem, VOIDmode, NULL_RTX);

59278

emit_insn (gen_movsd_hardfloat (operands[0], mem));

59279

}

59280

@@ -7230,6 +8428,7 @@

59281

case V1DImode:

59282

case V2DFmode:

59283

case V2DImode:

59284

+ case V1TImode:

59285

if (CONSTANT_P (operands[1])

59286

&& !easy_vector_constant (operands[1], mode))

59287

operands[1] = force_const_mem (mode, operands[1]);

59288

@@ -7388,6 +8587,11 @@

59289

break;

59290

59291

case TImode:

59292

+ if (!VECTOR_MEM_VSX_P (TImode))

59293

+ rs6000_eliminate_indexed_memrefs (operands);

59294

+ break;

59295

+

59296

+ case PTImode:

59297

rs6000_eliminate_indexed_memrefs (operands);

59298

break;

59299

59300

@@ -7426,18 +8630,231 @@

59301

}

59302

59303

/* Nonzero if we can use a floating-point register to pass this arg. */

59304

-#define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \

59305

+#define USE_FP_FOR_ARG_P(CUM,MODE) \

59306

(SCALAR_FLOAT_MODE_P (MODE) \

59307

&& (CUM)->fregno <= FP_ARG_MAX_REG \

59308

&& TARGET_HARD_FLOAT && TARGET_FPRS)

59309

59310

/* Nonzero if we can use an AltiVec register to pass this arg. */

59311

-#define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \

59312

+#define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,NAMED) \

59313

(ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \

59314

&& (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \

59315

&& TARGET_ALTIVEC_ABI \

59316

&& (NAMED))

59317

59318

+/* Walk down the type tree of TYPE counting consecutive base elements.

59319

+ If *MODEP is VOIDmode, then set it to the first valid floating point

59320

+ or vector type. If a non-floating point or vector type is found, or

59321

+ if a floating point or vector type that doesn't match a non-VOIDmode

59322

+ *MODEP is found, then return -1, otherwise return the count in the

59323

+ sub-tree. */

59324

+

59325

+static int

59326

+rs6000_aggregate_candidate (const_tree type, enum machine_mode *modep)

59327

+{

59328

+ enum machine_mode mode;

59329

+ HOST_WIDE_INT size;

59330

+

59331

+ switch (TREE_CODE (type))

59332

+ {

59333

+ case REAL_TYPE:

59334

+ mode = TYPE_MODE (type);

59335

+ if (!SCALAR_FLOAT_MODE_P (mode))

59336

+ return -1;

59337

+

59338

+ if (*modep == VOIDmode)

59339

+ *modep = mode;

59340

+

59341

+ if (*modep == mode)

59342

+ return 1;

59343

+

59344

+ break;

59345

+

59346

+ case COMPLEX_TYPE:

59347

+ mode = TYPE_MODE (TREE_TYPE (type));

59348

+ if (!SCALAR_FLOAT_MODE_P (mode))

59349

+ return -1;

59350

+

59351

+ if (*modep == VOIDmode)

59352

+ *modep = mode;

59353

+

59354

+ if (*modep == mode)

59355

+ return 2;

59356

+

59357

+ break;

59358

+

59359

+ case VECTOR_TYPE:

59360

+ if (!TARGET_ALTIVEC_ABI || !TARGET_ALTIVEC)

59361

+ return -1;

59362

+

59363

+ /* Use V4SImode as representative of all 128-bit vector types. */

59364

+ size = int_size_in_bytes (type);

59365

+ switch (size)

59366

+ {

59367

+ case 16:

59368

+ mode = V4SImode;

59369

+ break;

59370

+ default:

59371

+ return -1;

59372

+ }

59373

+

59374

+ if (*modep == VOIDmode)

59375

+ *modep = mode;

59376

+

59377

+ /* Vector modes are considered to be opaque: two vectors are

59378

+ equivalent for the purposes of being homogeneous aggregates

59379

+ if they are the same size. */

59380

+ if (*modep == mode)

59381

+ return 1;

59382

+

59383

+ break;

59384

+

59385

+ case ARRAY_TYPE:

59386

+ {

59387

+ int count;

59388

+ tree index = TYPE_DOMAIN (type);

59389

+

59390

+ /* Can't handle incomplete types. */

59391

+ if (!COMPLETE_TYPE_P (type))

59392

+ return -1;

59393

+

59394

+ count = rs6000_aggregate_candidate (TREE_TYPE (type), modep);

59395

+ if (count == -1

59396

+ || !index

59397

+ || !TYPE_MAX_VALUE (index)

59398

+ || !host_integerp (TYPE_MAX_VALUE (index), 1)

59399

+ || !TYPE_MIN_VALUE (index)

59400

+ || !host_integerp (TYPE_MIN_VALUE (index), 1)

59401

+ || count < 0)

59402

+ return -1;

59403

+

59404

+ count *= (1 + tree_low_cst (TYPE_MAX_VALUE (index), 1)

59405

+ - tree_low_cst (TYPE_MIN_VALUE (index), 1));

59406

+

59407

+ /* There must be no padding. */

59408

+ if (!host_integerp (TYPE_SIZE (type), 1)

59409

+ || (tree_low_cst (TYPE_SIZE (type), 1)

59410

+ != count * GET_MODE_BITSIZE (*modep)))

59411

+ return -1;

59412

+

59413

+ return count;

59414

+ }

59415

+

59416

+ case RECORD_TYPE:

59417

+ {

59418

+ int count = 0;

59419

+ int sub_count;

59420

+ tree field;

59421

+

59422

+ /* Can't handle incomplete types. */

59423

+ if (!COMPLETE_TYPE_P (type))

59424

+ return -1;

59425

+

59426

+ for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))

59427

+ {

59428

+ if (TREE_CODE (field) != FIELD_DECL)

59429

+ continue;

59430

+

59431

+ sub_count = rs6000_aggregate_candidate (TREE_TYPE (field), modep);

59432

+ if (sub_count < 0)

59433

+ return -1;

59434

+ count += sub_count;

59435

+ }

59436

+

59437

+ /* There must be no padding. */

59438

+ if (!host_integerp (TYPE_SIZE (type), 1)

59439

+ || (tree_low_cst (TYPE_SIZE (type), 1)

59440

+ != count * GET_MODE_BITSIZE (*modep)))

59441

+ return -1;

59442

+

59443

+ return count;

59444

+ }

59445

+

59446

+ case UNION_TYPE:

59447

+ case QUAL_UNION_TYPE:

59448

+ {

59449

+ /* These aren't very interesting except in a degenerate case. */

59450

+ int count = 0;

59451

+ int sub_count;

59452

+ tree field;

59453

+

59454

+ /* Can't handle incomplete types. */

59455

+ if (!COMPLETE_TYPE_P (type))

59456

+ return -1;

59457

+

59458

+ for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))

59459

+ {

59460

+ if (TREE_CODE (field) != FIELD_DECL)

59461

+ continue;

59462

+

59463

+ sub_count = rs6000_aggregate_candidate (TREE_TYPE (field), modep);

59464

+ if (sub_count < 0)

59465

+ return -1;

59466

+ count = count > sub_count ? count : sub_count;

59467

+ }

59468

+

59469

+ /* There must be no padding. */

59470

+ if (!host_integerp (TYPE_SIZE (type), 1)

59471

+ || (tree_low_cst (TYPE_SIZE (type), 1)

59472

+ != count * GET_MODE_BITSIZE (*modep)))

59473

+ return -1;

59474

+

59475

+ return count;

59476

+ }

59477

+

59478

+ default:

59479

+ break;

59480

+ }

59481

+

59482

+ return -1;

59483

+}

59484

+

59485

+/* If an argument, whose type is described by TYPE and MODE, is a homogeneous

59486

+ float or vector aggregate that shall be passed in FP/vector registers

59487

+ according to the ELFv2 ABI, return the homogeneous element mode in

59488

+ *ELT_MODE and the number of elements in *N_ELTS, and return TRUE.

59489

+

59490

+ Otherwise, set *ELT_MODE to MODE and *N_ELTS to 1, and return FALSE. */

59491

+

59492

+static bool

59493

+rs6000_discover_homogeneous_aggregate (enum machine_mode mode, const_tree type,

59494

+ enum machine_mode *elt_mode,

59495

+ int *n_elts)

59496

+{

59497

+ /* Note that we do not accept complex types at the top level as

59498

+ homogeneous aggregates; these types are handled via the

59499

+ targetm.calls.split_complex_arg mechanism. Complex types

59500

+ can be elements of homogeneous aggregates, however. */

59501

+ if (DEFAULT_ABI == ABI_ELFv2 && type && AGGREGATE_TYPE_P (type))

59502

+ {

59503

+ enum machine_mode field_mode = VOIDmode;

59504

+ int field_count = rs6000_aggregate_candidate (type, &field_mode);

59505

+

59506

+ if (field_count > 0)

59507

+ {

59508

+ int n_regs = (SCALAR_FLOAT_MODE_P (field_mode)?

59509

+ (GET_MODE_SIZE (field_mode) + 7) >> 3 : 1);

59510

+

59511

+ /* The ELFv2 ABI allows homogeneous aggregates to occupy

59512

+ up to AGGR_ARG_NUM_REG registers. */

59513

+ if (field_count * n_regs <= AGGR_ARG_NUM_REG)

59514

+ {

59515

+ if (elt_mode)

59516

+ *elt_mode = field_mode;

59517

+ if (n_elts)

59518

+ *n_elts = field_count;

59519

+ return true;

59520

+ }

59521

+ }

59522

+ }

59523

+

59524

+ if (elt_mode)

59525

+ *elt_mode = mode;

59526

+ if (n_elts)

59527

+ *n_elts = 1;

59528

+ return false;

59529

+}

59530

+

59531

/* Return a nonzero value to say to return the function value in

59532

memory, just as large structures are always returned. TYPE will be

59533

the data type of the value, and FNTYPE will be the type of the

59534

@@ -7490,6 +8907,16 @@

59535

/* Otherwise fall through to more conventional ABI rules. */

59536

}

59537

59538

+ /* The ELFv2 ABI returns homogeneous VFP aggregates in registers */

59539

+ if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (type), type,

59540

+ NULL, NULL))

59541

+ return false;

59542

+

59543

+ /* The ELFv2 ABI returns aggregates up to 16B in registers */

59544

+ if (DEFAULT_ABI == ABI_ELFv2 && AGGREGATE_TYPE_P (type)

59545

+ && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) <= 16)

59546

+ return false;

59547

+

59548

if (AGGREGATE_TYPE_P (type)

59549

&& (aix_struct_return

59550

|| (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))

59551

@@ -7521,6 +8948,19 @@

59552

return false;

59553

}

59554

59555

+/* Specify whether values returned in registers should be at the most

59556

+ significant end of a register. We want aggregates returned by

59557

+ value to match the way aggregates are passed to functions. */

59558

+

59559

+static bool

59560

+rs6000_return_in_msb (const_tree valtype)

59561

+{

59562

+ return (DEFAULT_ABI == ABI_ELFv2

59563

+ && BYTES_BIG_ENDIAN

59564

+ && AGGREGATE_TYPE_P (valtype)

59565

+ && FUNCTION_ARG_PADDING (TYPE_MODE (valtype), valtype) == upward);

59566

+}

59567

+

59568

#ifdef HAVE_AS_GNU_ATTRIBUTE

59569

/* Return TRUE if a call to function FNDECL may be one that

59570

potentially affects the function calling ABI of the object file. */

59571

@@ -7657,7 +9097,7 @@

59572

static bool

59573

rs6000_must_pass_in_stack (enum machine_mode mode, const_tree type)

59574

{

59575

- if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)

59576

+ if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 || TARGET_64BIT)

59577

return must_pass_in_stack_var_size (mode, type);

59578

else

59579

return must_pass_in_stack_var_size_or_pad (mode, type);

59580

@@ -7738,6 +9178,11 @@

59581

static unsigned int

59582

rs6000_function_arg_boundary (enum machine_mode mode, const_tree type)

59583

{

59584

+ enum machine_mode elt_mode;

59585

+ int n_elts;

59586

+

59587

+ rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);

59588

+

59589

if (DEFAULT_ABI == ABI_V4

59590

&& (GET_MODE_SIZE (mode) == 8

59591

|| (TARGET_HARD_FLOAT

59592

@@ -7749,12 +9194,13 @@

59593

&& int_size_in_bytes (type) >= 8

59594

&& int_size_in_bytes (type) < 16))

59595

return 64;

59596

- else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode)

59597

+ else if (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode)

59598

|| (type && TREE_CODE (type) == VECTOR_TYPE

59599

&& int_size_in_bytes (type) >= 16))

59600

return 128;

59601

- else if (TARGET_MACHO

59602

- && rs6000_darwin64_abi

59603

+ else if (((TARGET_MACHO && rs6000_darwin64_abi)

59604

+ || DEFAULT_ABI == ABI_ELFv2

59605

+ || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm))

59606

&& mode == BLKmode

59607

&& type && TYPE_ALIGN (type) > 64)

59608

return 128;

59609

@@ -7762,6 +9208,16 @@

59610

return PARM_BOUNDARY;

59611

}

59612

59613

+/* The offset in words to the start of the parameter save area. */

59614

+

59615

+static unsigned int

59616

+rs6000_parm_offset (void)

59617

+{

59618

+ return (DEFAULT_ABI == ABI_V4 ? 2

59619

+ : DEFAULT_ABI == ABI_ELFv2 ? 4

59620

+ : 6);

59621

+}

59622

+

59623

/* For a function parm of MODE and TYPE, return the starting word in

59624

the parameter area. NWORDS of the parameter area are already used. */

59625

59626

@@ -7770,11 +9226,9 @@

59627

unsigned int nwords)

59628

{

59629

unsigned int align;

59630

- unsigned int parm_offset;

59631

59632

align = rs6000_function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;

59633

- parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;

59634

- return nwords + (-(parm_offset + nwords) & align);

59635

+ return nwords + (-(rs6000_parm_offset () + nwords) & align);

59636

}

59637

59638

/* Compute the size (in words) of a function argument. */

59639

@@ -7881,7 +9335,7 @@

59640

59641

if (TREE_CODE (ftype) == RECORD_TYPE)

59642

rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);

59643

- else if (USE_FP_FOR_ARG_P (cum, mode, ftype))

59644

+ else if (USE_FP_FOR_ARG_P (cum, mode))

59645

{

59646

unsigned n_fpregs = (GET_MODE_SIZE (mode) + 7) >> 3;

59647

rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);

59648

@@ -7922,7 +9376,7 @@

59649

else

59650

cum->words += n_fpregs;

59651

}

59652

- else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))

59653

+ else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, 1))

59654

{

59655

rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);

59656

cum->vregno++;

59657

@@ -7959,6 +9413,11 @@

59658

rs6000_function_arg_advance_1 (CUMULATIVE_ARGS *cum, enum machine_mode mode,

59659

const_tree type, bool named, int depth)

59660

{

59661

+ enum machine_mode elt_mode;

59662

+ int n_elts;

59663

+

59664

+ rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);

59665

+

59666

/* Only tick off an argument if we're not recursing. */

59667

if (depth == 0)

59668

cum->nargs_prototype--;

59669

@@ -7979,15 +9438,16 @@

59670

#endif

59671

59672

if (TARGET_ALTIVEC_ABI

59673

- && (ALTIVEC_OR_VSX_VECTOR_MODE (mode)

59674

+ && (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode)

59675

|| (type && TREE_CODE (type) == VECTOR_TYPE

59676

&& int_size_in_bytes (type) == 16)))

59677

{

59678

bool stack = false;

59679

59680

- if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))

59681

+ if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))

59682

{

59683

- cum->vregno++;

59684

+ cum->vregno += n_elts;

59685

+

59686

if (!TARGET_ALTIVEC)

59687

error ("cannot pass argument in vector register because"

59688

" altivec instructions are disabled, use -maltivec"

59689

@@ -7996,7 +9456,8 @@

59690

/* PowerPC64 Linux and AIX allocate GPRs for a vector argument

59691

even if it is going to be passed in a vector register.

59692

Darwin does the same for variable-argument functions. */

59693

- if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)

59694

+ if (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)

59695

+ && TARGET_64BIT)

59696

|| (cum->stdarg && DEFAULT_ABI != ABI_V4))

59697

stack = true;

59698

}

59699

@@ -8007,15 +9468,13 @@

59700

{

59701

int align;

59702

59703

- /* Vector parameters must be 16-byte aligned. This places

59704

- them at 2 mod 4 in terms of words in 32-bit mode, since

59705

- the parameter save area starts at offset 24 from the

59706

- stack. In 64-bit mode, they just have to start on an

59707

- even word, since the parameter save area is 16-byte

59708

- aligned. Space for GPRs is reserved even if the argument

59709

- will be passed in memory. */

59710

+ /* Vector parameters must be 16-byte aligned. In 32-bit

59711

+ mode this means we need to take into account the offset

59712

+ to the parameter save area. In 64-bit mode, they just

59713

+ have to start on an even word, since the parameter save

59714

+ area is 16-byte aligned. */

59715

if (TARGET_32BIT)

59716

- align = (2 - cum->words) & 3;

59717

+ align = -(rs6000_parm_offset () + cum->words) & 3;

59718

else

59719

align = cum->words & 1;

59720

cum->words += align + rs6000_arg_size (mode, type);

59721

@@ -8140,15 +9599,15 @@

59722

59723

cum->words = align_words + n_words;

59724

59725

- if (SCALAR_FLOAT_MODE_P (mode)

59726

+ if (SCALAR_FLOAT_MODE_P (elt_mode)

59727

&& TARGET_HARD_FLOAT && TARGET_FPRS)

59728

{

59729

/* _Decimal128 must be passed in an even/odd float register pair.

59730

This assumes that the register number is odd when fregno is

59731

odd. */

59732

- if (mode == TDmode && (cum->fregno % 2) == 1)

59733

+ if (elt_mode == TDmode && (cum->fregno % 2) == 1)

59734

cum->fregno++;

59735

- cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;

59736

+ cum->fregno += n_elts * ((GET_MODE_SIZE (elt_mode) + 7) >> 3);

59737

}

59738

59739

if (TARGET_DEBUG_ARG)

59740

@@ -8358,7 +9817,7 @@

59741

59742

if (TREE_CODE (ftype) == RECORD_TYPE)

59743

rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);

59744

- else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))

59745

+ else if (cum->named && USE_FP_FOR_ARG_P (cum, mode))

59746

{

59747

unsigned n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;

59748

#if 0

59749

@@ -8386,7 +9845,7 @@

59750

if (mode == TFmode || mode == TDmode)

59751

cum->fregno++;

59752

}

59753

- else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))

59754

+ else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, 1))

59755

{

59756

rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);

59757

rvec[(*k)++]

59758

@@ -8503,6 +9962,84 @@

59759

return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));

59760

}

59761

59762

+/* We have an argument of MODE and TYPE that goes into FPRs or VRs,

59763

+ but must also be copied into the parameter save area starting at

59764

+ offset ALIGN_WORDS. Fill in RVEC with the elements corresponding

59765

+ to the GPRs and/or memory. Return the number of elements used. */

59766

+

59767

+static int

59768

+rs6000_psave_function_arg (enum machine_mode mode, const_tree type,

59769

+ int align_words, rtx *rvec)

59770

+{

59771

+ int k = 0;

59772

+

59773

+ if (align_words < GP_ARG_NUM_REG)

59774

+ {

59775

+ int n_words = rs6000_arg_size (mode, type);

59776

+

59777

+ if (align_words + n_words > GP_ARG_NUM_REG

59778

+ || mode == BLKmode

59779

+ || (TARGET_32BIT && TARGET_POWERPC64))

59780

+ {

59781

+ /* If this is partially on the stack, then we only

59782

+ include the portion actually in registers here. */

59783

+ enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;

59784

+ int i = 0;

59785

+

59786

+ if (align_words + n_words > GP_ARG_NUM_REG)

59787

+ {

59788

+ /* Not all of the arg fits in gprs. Say that it goes in memory

59789

+ too, using a magic NULL_RTX component. Also see comment in

59790

+ rs6000_mixed_function_arg for why the normal

59791

+ function_arg_partial_nregs scheme doesn't work in this case. */

59792

+ rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);

59793

+ }

59794

+

59795

+ do

59796

+ {

59797

+ rtx r = gen_rtx_REG (rmode, GP_ARG_MIN_REG + align_words);

59798

+ rtx off = GEN_INT (i++ * GET_MODE_SIZE (rmode));

59799

+ rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);

59800

+ }

59801

+ while (++align_words < GP_ARG_NUM_REG && --n_words != 0);

59802

+ }

59803

+ else

59804

+ {

59805

+ /* The whole arg fits in gprs. */

59806

+ rtx r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);

59807

+ rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);

59808

+ }

59809

+ }

59810

+ else

59811

+ {

59812

+ /* It's entirely in memory. */

59813

+ rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);

59814

+ }

59815

+

59816

+ return k;

59817

+}

59818

+

59819

+/* RVEC is a vector of K components of an argument of mode MODE.

59820

+ Construct the final function_arg return value from it. */

59821

+

59822

+static rtx

59823

+rs6000_finish_function_arg (enum machine_mode mode, rtx *rvec, int k)

59824

+{

59825

+ gcc_assert (k >= 1);

59826

+

59827

+ /* Avoid returning a PARALLEL in the trivial cases. */

59828

+ if (k == 1)

59829

+ {

59830

+ if (XEXP (rvec[0], 0) == NULL_RTX)

59831

+ return NULL_RTX;

59832

+

59833

+ if (GET_MODE (XEXP (rvec[0], 0)) == mode)

59834

+ return XEXP (rvec[0], 0);

59835

+ }

59836

+

59837

+ return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));

59838

+}

59839

+

59840

/* Determine where to put an argument to a function.

59841

Value is zero to push the argument on the stack,

59842

or a hard register in which to store the argument.

59843

@@ -8537,6 +10074,8 @@

59844

{

59845

CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);

59846

enum rs6000_abi abi = DEFAULT_ABI;

59847

+ enum machine_mode elt_mode;

59848

+ int n_elts;

59849

59850

/* Return a marker to indicate whether CR1 needs to set or clear the

59851

bit that V.4 uses to say fp args were passed in registers.

59852

@@ -8563,6 +10102,8 @@

59853

return GEN_INT (cum->call_cookie & ~CALL_LIBCALL);

59854

}

59855

59856

+ rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);

59857

+

59858

if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))

59859

{

59860

rtx rslt = rs6000_darwin64_record_arg (cum, type, named, /*retval= */false);

59861

@@ -8571,33 +10112,30 @@

59862

/* Else fall through to usual handling. */

59863

}

59864

59865

- if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))

59866

- if (TARGET_64BIT && ! cum->prototype)

59867

- {

59868

- /* Vector parameters get passed in vector register

59869

- and also in GPRs or memory, in absence of prototype. */

59870

- int align_words;

59871

- rtx slot;

59872

- align_words = (cum->words + 1) & ~1;

59873

+ if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))

59874

+ {

59875

+ rtx rvec[GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + 1];

59876

+ rtx r, off;

59877

+ int i, k = 0;

59878

59879

- if (align_words >= GP_ARG_NUM_REG)

59880

- {

59881

- slot = NULL_RTX;

59882

- }

59883

- else

59884

- {

59885

- slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);

59886

- }

59887

- return gen_rtx_PARALLEL (mode,

59888

- gen_rtvec (2,

59889

- gen_rtx_EXPR_LIST (VOIDmode,

59890

- slot, const0_rtx),

59891

- gen_rtx_EXPR_LIST (VOIDmode,

59892

- gen_rtx_REG (mode, cum->vregno),

59893

- const0_rtx)));

59894

- }

59895

- else

59896

- return gen_rtx_REG (mode, cum->vregno);

59897

+ /* Do we also need to pass this argument in the parameter

59898

+ save area? */

59899

+ if (TARGET_64BIT && ! cum->prototype)

59900

+ {

59901

+ int align_words = (cum->words + 1) & ~1;

59902

+ k = rs6000_psave_function_arg (mode, type, align_words, rvec);

59903

+ }

59904

+

59905

+ /* Describe where this argument goes in the vector registers. */

59906

+ for (i = 0; i < n_elts && cum->vregno + i <= ALTIVEC_ARG_MAX_REG; i++)

59907

+ {

59908

+ r = gen_rtx_REG (elt_mode, cum->vregno + i);

59909

+ off = GEN_INT (i * GET_MODE_SIZE (elt_mode));

59910

+ rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);

59911

+ }

59912

+

59913

+ return rs6000_finish_function_arg (mode, rvec, k);

59914

+ }

59915

else if (TARGET_ALTIVEC_ABI

59916

&& (ALTIVEC_OR_VSX_VECTOR_MODE (mode)

59917

|| (type && TREE_CODE (type) == VECTOR_TYPE

59918

@@ -8612,13 +10150,13 @@

59919

int align, align_words, n_words;

59920

enum machine_mode part_mode;

59921

59922

- /* Vector parameters must be 16-byte aligned. This places them at

59923

- 2 mod 4 in terms of words in 32-bit mode, since the parameter

59924

- save area starts at offset 24 from the stack. In 64-bit mode,

59925

- they just have to start on an even word, since the parameter

59926

- save area is 16-byte aligned. */

59927

+ /* Vector parameters must be 16-byte aligned. In 32-bit

59928

+ mode this means we need to take into account the offset

59929

+ to the parameter save area. In 64-bit mode, they just

59930

+ have to start on an even word, since the parameter save

59931

+ area is 16-byte aligned. */

59932

if (TARGET_32BIT)

59933

- align = (2 - cum->words) & 3;

59934

+ align = -(rs6000_parm_offset () + cum->words) & 3;

59935

else

59936

align = cum->words & 1;

59937

align_words = cum->words + align;

59938

@@ -8696,92 +10234,44 @@

59939

59940

/* _Decimal128 must be passed in an even/odd float register pair.

59941

This assumes that the register number is odd when fregno is odd. */

59942

- if (mode == TDmode && (cum->fregno % 2) == 1)

59943

+ if (elt_mode == TDmode && (cum->fregno % 2) == 1)

59944

cum->fregno++;

59945

59946

- if (USE_FP_FOR_ARG_P (cum, mode, type))

59947

+ if (USE_FP_FOR_ARG_P (cum, elt_mode))

59948

{

59949

- rtx rvec[GP_ARG_NUM_REG + 1];

59950

- rtx r;

59951

- int k;

59952

- bool needs_psave;

59953

- enum machine_mode fmode = mode;

59954

- unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;

59955

+ rtx rvec[GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + 1];

59956

+ rtx r, off;

59957

+ int i, k = 0;

59958

+ unsigned long n_fpreg = (GET_MODE_SIZE (elt_mode) + 7) >> 3;

59959

59960

- if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)

59961

- {

59962

- /* Currently, we only ever need one reg here because complex

59963

- doubles are split. */

59964

- gcc_assert (cum->fregno == FP_ARG_MAX_REG

59965

- && (fmode == TFmode || fmode == TDmode));

59966

+ /* Do we also need to pass this argument in the parameter

59967

+ save area? */

59968

+ if (type && (cum->nargs_prototype <= 0

59969

+ || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)

59970

+ && TARGET_XL_COMPAT

59971

+ && align_words >= GP_ARG_NUM_REG)))

59972

+ k = rs6000_psave_function_arg (mode, type, align_words, rvec);

59973

59974

- /* Long double or _Decimal128 split over regs and memory. */

59975

- fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode;

59976

- }

59977

-

59978

- /* Do we also need to pass this arg in the parameter save

59979

- area? */

59980

- needs_psave = (type

59981

- && (cum->nargs_prototype <= 0

59982

- || (DEFAULT_ABI == ABI_AIX

59983

- && TARGET_XL_COMPAT

59984

- && align_words >= GP_ARG_NUM_REG)));

59985

-

59986

- if (!needs_psave && mode == fmode)

59987

- return gen_rtx_REG (fmode, cum->fregno);

59988

-

59989

- k = 0;

59990

- if (needs_psave)

59991

+ /* Describe where this argument goes in the fprs. */

59992

+ for (i = 0; i < n_elts

59993

+ && cum->fregno + i * n_fpreg <= FP_ARG_MAX_REG; i++)

59994

{

59995

- /* Describe the part that goes in gprs or the stack.

59996

- This piece must come first, before the fprs. */

59997

- if (align_words < GP_ARG_NUM_REG)

59998

+ /* Check if the argument is split over registers and memory.

59999

+ This can only ever happen for long double or _Decimal128;

60000

+ complex types are handled via split_complex_arg. */

60001

+ enum machine_mode fmode = elt_mode;

60002

+ if (cum->fregno + (i + 1) * n_fpreg > FP_ARG_MAX_REG + 1)

60003

{

60004

- unsigned long n_words = rs6000_arg_size (mode, type);

60005

+ gcc_assert (fmode == TFmode || fmode == TDmode);

60006

+ fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode;

60007

+ }

60008

60009

- if (align_words + n_words > GP_ARG_NUM_REG

60010

- || (TARGET_32BIT && TARGET_POWERPC64))

60011

- {

60012

- /* If this is partially on the stack, then we only

60013

- include the portion actually in registers here. */

60014

- enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;

60015

- rtx off;

60016

- int i = 0;

60017

- if (align_words + n_words > GP_ARG_NUM_REG)

60018

- /* Not all of the arg fits in gprs. Say that it

60019

- goes in memory too, using a magic NULL_RTX

60020

- component. Also see comment in

60021

- rs6000_mixed_function_arg for why the normal

60022

- function_arg_partial_nregs scheme doesn't work

60023

- in this case. */

60024

- rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,

60025

- const0_rtx);

60026

- do

60027

- {

60028

- r = gen_rtx_REG (rmode,

60029

- GP_ARG_MIN_REG + align_words);

60030

- off = GEN_INT (i++ * GET_MODE_SIZE (rmode));

60031

- rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);

60032

- }

60033

- while (++align_words < GP_ARG_NUM_REG && --n_words != 0);

60034

- }

60035

- else

60036

- {

60037

- /* The whole arg fits in gprs. */

60038

- r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);

60039

- rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);

60040

- }

60041

- }

60042

- else

60043

- /* It's entirely in memory. */

60044

- rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);

60045

+ r = gen_rtx_REG (fmode, cum->fregno + i * n_fpreg);

60046

+ off = GEN_INT (i * GET_MODE_SIZE (elt_mode));

60047

+ rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);

60048

}

60049

60050

- /* Describe where this piece goes in the fprs. */

60051

- r = gen_rtx_REG (fmode, cum->fregno);

60052

- rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);

60053

-

60054

- return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));

60055

+ return rs6000_finish_function_arg (mode, rvec, k);

60056

}

60057

else if (align_words < GP_ARG_NUM_REG)

60058

{

60059

@@ -8788,9 +10278,6 @@

60060

if (TARGET_32BIT && TARGET_POWERPC64)

60061

return rs6000_mixed_function_arg (mode, type, align_words);

60062

60063

- if (mode == BLKmode)

60064

- mode = Pmode;

60065

-

60066

return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);

60067

}

60068

else

60069

@@ -8809,16 +10296,32 @@

60070

tree type, bool named)

60071

{

60072

CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);

60073

+ bool passed_in_gprs = true;

60074

int ret = 0;

60075

int align_words;

60076

+ enum machine_mode elt_mode;

60077

+ int n_elts;

60078

60079

+ rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);

60080

+

60081

if (DEFAULT_ABI == ABI_V4)

60082

return 0;

60083

60084

- if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)

60085

- && cum->nargs_prototype >= 0)

60086

- return 0;

60087

+ if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))

60088

+ {

60089

+ /* If we are passing this arg in the fixed parameter save area

60090

+ (gprs or memory) as well as VRs, we do not use the partial

60091

+ bytes mechanism; instead, rs6000_function_arg will return a

60092

+ PARALLEL including a memory element as necessary. */

60093

+ if (TARGET_64BIT && ! cum->prototype)

60094

+ return 0;

60095

60096

+ /* Otherwise, we pass in VRs only. Check for partial copies. */

60097

+ passed_in_gprs = false;

60098

+ if (cum->vregno + n_elts > ALTIVEC_ARG_MAX_REG + 1)

60099

+ ret = (ALTIVEC_ARG_MAX_REG + 1 - cum->vregno) * 16;

60100

+ }

60101

+

60102

/* In this complicated case we just disable the partial_nregs code. */

60103

if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))

60104

return 0;

60105

@@ -8825,26 +10328,30 @@

60106

60107

align_words = rs6000_parm_start (mode, type, cum->words);

60108

60109

- if (USE_FP_FOR_ARG_P (cum, mode, type))

60110

+ if (USE_FP_FOR_ARG_P (cum, elt_mode))

60111

{

60112

+ unsigned long n_fpreg = (GET_MODE_SIZE (elt_mode) + 7) >> 3;

60113

+

60114

/* If we are passing this arg in the fixed parameter save area

60115

- (gprs or memory) as well as fprs, then this function should

60116

- return the number of partial bytes passed in the parameter

60117

- save area rather than partial bytes passed in fprs. */

60118

+ (gprs or memory) as well as FPRs, we do not use the partial

60119

+ bytes mechanism; instead, rs6000_function_arg will return a

60120

+ PARALLEL including a memory element as necessary. */

60121

if (type

60122

&& (cum->nargs_prototype <= 0

60123

- || (DEFAULT_ABI == ABI_AIX

60124

+ || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)

60125

&& TARGET_XL_COMPAT

60126

&& align_words >= GP_ARG_NUM_REG)))

60127

return 0;

60128

- else if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3)

60129

- > FP_ARG_MAX_REG + 1)

60130

- ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8;

60131

- else if (cum->nargs_prototype >= 0)

60132

- return 0;

60133

+

60134

+ /* Otherwise, we pass in FPRs only. Check for partial copies. */

60135

+ passed_in_gprs = false;

60136

+ if (cum->fregno + n_elts * n_fpreg > FP_ARG_MAX_REG + 1)

60137

+ ret = ((FP_ARG_MAX_REG + 1 - cum->fregno)

60138

+ * MIN (8, GET_MODE_SIZE (elt_mode)));

60139

}

60140

60141

- if (align_words < GP_ARG_NUM_REG

60142

+ if (passed_in_gprs

60143

+ && align_words < GP_ARG_NUM_REG

60144

&& GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))

60145

ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);

60146

60147

@@ -8925,6 +10432,139 @@

60148

return 0;

60149

}

60150

60151

+/* Process parameter of type TYPE after ARGS_SO_FAR parameters were

60152

+ already processes. Return true if the parameter must be passed

60153

+ (fully or partially) on the stack. */

60154

+

60155

+static bool

60156

+rs6000_parm_needs_stack (cumulative_args_t args_so_far, tree type)

60157

+{

60158

+ enum machine_mode mode;

60159

+ int unsignedp;

60160

+ rtx entry_parm;

60161

+

60162

+ /* Catch errors. */

60163

+ if (type == NULL || type == error_mark_node)

60164

+ return true;

60165

+

60166

+ /* Handle types with no storage requirement. */

60167

+ if (TYPE_MODE (type) == VOIDmode)

60168

+ return false;

60169

+

60170

+ /* Handle complex types. */

60171

+ if (TREE_CODE (type) == COMPLEX_TYPE)

60172

+ return (rs6000_parm_needs_stack (args_so_far, TREE_TYPE (type))

60173

+ || rs6000_parm_needs_stack (args_so_far, TREE_TYPE (type)));

60174

+

60175

+ /* Handle transparent aggregates. */

60176

+ if ((TREE_CODE (type) == UNION_TYPE || TREE_CODE (type) == RECORD_TYPE)

60177

+ && TYPE_TRANSPARENT_AGGR (type))

60178

+ type = TREE_TYPE (first_field (type));

60179

+

60180

+ /* See if this arg was passed by invisible reference. */

60181

+ if (pass_by_reference (get_cumulative_args (args_so_far),

60182

+ TYPE_MODE (type), type, true))

60183

+ type = build_pointer_type (type);

60184

+

60185

+ /* Find mode as it is passed by the ABI. */

60186

+ unsignedp = TYPE_UNSIGNED (type);

60187

+ mode = promote_mode (type, TYPE_MODE (type), &unsignedp);

60188

+

60189

+ /* If we must pass in stack, we need a stack. */

60190

+ if (rs6000_must_pass_in_stack (mode, type))

60191

+ return true;

60192

+

60193

+ /* If there is no incoming register, we need a stack. */

60194

+ entry_parm = rs6000_function_arg (args_so_far, mode, type, true);

60195

+ if (entry_parm == NULL)

60196

+ return true;

60197

+

60198

+ /* Likewise if we need to pass both in registers and on the stack. */

60199

+ if (GET_CODE (entry_parm) == PARALLEL

60200

+ && XEXP (XVECEXP (entry_parm, 0, 0), 0) == NULL_RTX)

60201

+ return true;

60202

+

60203

+ /* Also true if we're partially in registers and partially not. */

60204

+ if (rs6000_arg_partial_bytes (args_so_far, mode, type, true) != 0)

60205

+ return true;

60206

+

60207

+ /* Update info on where next arg arrives in registers. */

60208

+ rs6000_function_arg_advance (args_so_far, mode, type, true);

60209

+ return false;

60210

+}

60211

+

60212

+/* Return true if FUN has no prototype, has a variable argument

60213

+ list, or passes any parameter in memory. */

60214

+

60215

+static bool

60216

+rs6000_function_parms_need_stack (tree fun)

60217

+{

60218

+ function_args_iterator args_iter;

60219

+ tree arg_type;

60220

+ CUMULATIVE_ARGS args_so_far_v;

60221

+ cumulative_args_t args_so_far;

60222

+

60223

+ if (!fun)

60224

+ /* Must be a libcall, all of which only use reg parms. */

60225

+ return false;

60226

+ if (!TYPE_P (fun))

60227

+ fun = TREE_TYPE (fun);

60228

+

60229

+ /* Varargs functions need the parameter save area. */

60230

+ if (!prototype_p (fun) || stdarg_p (fun))

60231

+ return true;

60232

+

60233

+ INIT_CUMULATIVE_INCOMING_ARGS (args_so_far_v, fun, NULL_RTX);

60234

+ args_so_far = pack_cumulative_args (&args_so_far_v);

60235

+

60236

+ if (aggregate_value_p (TREE_TYPE (fun), fun))

60237

+ {

60238

+ tree type = build_pointer_type (TREE_TYPE (fun));

60239

+ rs6000_parm_needs_stack (args_so_far, type);

60240

+ }

60241

+

60242

+ FOREACH_FUNCTION_ARGS (fun, arg_type, args_iter)

60243

+ if (rs6000_parm_needs_stack (args_so_far, arg_type))

60244

+ return true;

60245

+

60246

+ return false;

60247

+}

60248

+

60249

+/* Return the size of the REG_PARM_STACK_SPACE are for FUN. This is

60250

+ usually a constant depending on the ABI. However, in the ELFv2 ABI

60251

+ the register parameter area is optional when calling a function that

60252

+ has a prototype is scope, has no variable argument list, and passes

60253

+ all parameters in registers. */

60254

+

60255

+int

60256

+rs6000_reg_parm_stack_space (tree fun)

60257

+{

60258

+ int reg_parm_stack_space;

60259

+

60260

+ switch (DEFAULT_ABI)

60261

+ {

60262

+ default:

60263

+ reg_parm_stack_space = 0;

60264

+ break;

60265

+

60266

+ case ABI_AIX:

60267

+ case ABI_DARWIN:

60268

+ reg_parm_stack_space = TARGET_64BIT ? 64 : 32;

60269

+ break;

60270

+

60271

+ case ABI_ELFv2:

60272

+ /* ??? Recomputing this every time is a bit expensive. Is there

60273

+ a place to cache this information? */

60274

+ if (rs6000_function_parms_need_stack (fun))

60275

+ reg_parm_stack_space = TARGET_64BIT ? 64 : 32;

60276

+ else

60277

+ reg_parm_stack_space = 0;

60278

+ break;

60279

+ }

60280

+

60281

+ return reg_parm_stack_space;

60282

+}

60283

+

60284

static void

60285

rs6000_move_block_from_reg (int regno, rtx x, int nregs)

60286

{

60287

@@ -9306,8 +10946,10 @@

60288

We don't need to check for pass-by-reference because of the test above.

60289

We can return a simplifed answer, since we know there's no offset to add. */

60290

60291

- if (TARGET_MACHO

60292

- && rs6000_darwin64_abi

60293

+ if (((TARGET_MACHO

60294

+ && rs6000_darwin64_abi)

60295

+ || DEFAULT_ABI == ABI_ELFv2

60296

+ || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm))

60297

&& integer_zerop (TYPE_SIZE (type)))

60298

{

60299

unsigned HOST_WIDE_INT align, boundary;

60300

@@ -9602,6 +11244,7 @@

60301

#undef RS6000_BUILTIN_A

60302

#undef RS6000_BUILTIN_D

60303

#undef RS6000_BUILTIN_E

60304

+#undef RS6000_BUILTIN_H

60305

#undef RS6000_BUILTIN_P

60306

#undef RS6000_BUILTIN_Q

60307

#undef RS6000_BUILTIN_S

60308

@@ -9615,6 +11258,7 @@

60309

#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)

60310

#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)

60311

#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)

60312

+#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)

60313

#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)

60314

#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)

60315

#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)

60316

@@ -9633,6 +11277,7 @@

60317

#undef RS6000_BUILTIN_A

60318

#undef RS6000_BUILTIN_D

60319

#undef RS6000_BUILTIN_E

60320

+#undef RS6000_BUILTIN_H

60321

#undef RS6000_BUILTIN_P

60322

#undef RS6000_BUILTIN_Q

60323

#undef RS6000_BUILTIN_S

60324

@@ -9646,6 +11291,7 @@

60325

{ MASK, ICODE, NAME, ENUM },

60326

60327

#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)

60328

+#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)

60329

#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)

60330

#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)

60331

#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)

60332

@@ -9664,6 +11310,7 @@

60333

#undef RS6000_BUILTIN_A

60334

#undef RS6000_BUILTIN_D

60335

#undef RS6000_BUILTIN_E

60336

+#undef RS6000_BUILTIN_H

60337

#undef RS6000_BUILTIN_P

60338

#undef RS6000_BUILTIN_Q

60339

#undef RS6000_BUILTIN_S

60340

@@ -9677,6 +11324,7 @@

60341

#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)

60342

#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)

60343

#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)

60344

+#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)

60345

#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)

60346

#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)

60347

#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)

60348

@@ -9693,6 +11341,7 @@

60349

#undef RS6000_BUILTIN_A

60350

#undef RS6000_BUILTIN_D

60351

#undef RS6000_BUILTIN_E

60352

+#undef RS6000_BUILTIN_H

60353

#undef RS6000_BUILTIN_P

60354

#undef RS6000_BUILTIN_Q

60355

#undef RS6000_BUILTIN_S

60356

@@ -9704,6 +11353,7 @@

60357

#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)

60358

#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)

60359

#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)

60360

+#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)

60361

#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \

60362

{ MASK, ICODE, NAME, ENUM },

60363

60364

@@ -9725,6 +11375,7 @@

60365

#undef RS6000_BUILTIN_A

60366

#undef RS6000_BUILTIN_D

60367

#undef RS6000_BUILTIN_E

60368

+#undef RS6000_BUILTIN_H

60369

#undef RS6000_BUILTIN_P

60370

#undef RS6000_BUILTIN_Q

60371

#undef RS6000_BUILTIN_S

60372

@@ -9736,6 +11387,7 @@

60373

#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)

60374

#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)

60375

#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)

60376

+#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)

60377

#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)

60378

#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)

60379

#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \

60380

@@ -9755,6 +11407,7 @@

60381

#undef RS6000_BUILTIN_A

60382

#undef RS6000_BUILTIN_D

60383

#undef RS6000_BUILTIN_E

60384

+#undef RS6000_BUILTIN_H

60385

#undef RS6000_BUILTIN_P

60386

#undef RS6000_BUILTIN_Q

60387

#undef RS6000_BUILTIN_S

60388

@@ -9768,6 +11421,7 @@

60389

#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \

60390

{ MASK, ICODE, NAME, ENUM },

60391

60392

+#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)

60393

#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)

60394

#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)

60395

#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)

60396

@@ -9785,6 +11439,7 @@

60397

#undef RS6000_BUILTIN_A

60398

#undef RS6000_BUILTIN_D

60399

#undef RS6000_BUILTIN_E

60400

+#undef RS6000_BUILTIN_H

60401

#undef RS6000_BUILTIN_P

60402

#undef RS6000_BUILTIN_Q

60403

#undef RS6000_BUILTIN_S

60404

@@ -9796,6 +11451,7 @@

60405

#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)

60406

#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)

60407

#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)

60408

+#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)

60409

#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)

60410

#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \

60411

{ MASK, ICODE, NAME, ENUM },

60412

@@ -9816,6 +11472,7 @@

60413

#undef RS6000_BUILTIN_A

60414

#undef RS6000_BUILTIN_D

60415

#undef RS6000_BUILTIN_E

60416

+#undef RS6000_BUILTIN_H

60417

#undef RS6000_BUILTIN_P

60418

#undef RS6000_BUILTIN_Q

60419

#undef RS6000_BUILTIN_S

60420

@@ -9829,6 +11486,7 @@

60421

60422

#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)

60423

#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)

60424

+#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)

60425

#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)

60426

#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)

60427

#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)

60428

@@ -9846,8 +11504,9 @@

60429

#undef RS6000_BUILTIN_2

60430

#undef RS6000_BUILTIN_3

60431

#undef RS6000_BUILTIN_A

60432

+#undef RS6000_BUILTIN_D

60433

#undef RS6000_BUILTIN_E

60434

-#undef RS6000_BUILTIN_D

60435

+#undef RS6000_BUILTIN_H

60436

#undef RS6000_BUILTIN_P

60437

#undef RS6000_BUILTIN_Q

60438

#undef RS6000_BUILTIN_S

60439

@@ -9861,6 +11520,7 @@

60440

#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)

60441

#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)

60442

#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)

60443

+#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)

60444

#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)

60445

#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)

60446

#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)

60447

@@ -9871,6 +11531,7 @@

60448

#include "rs6000-builtin.def"

60449

};

60450

60451

+/* HTM builtins. */

60452

#undef RS6000_BUILTIN_1

60453

#undef RS6000_BUILTIN_2

60454

#undef RS6000_BUILTIN_3

60455

@@ -9877,11 +11538,42 @@

60456

#undef RS6000_BUILTIN_A

60457

#undef RS6000_BUILTIN_D

60458

#undef RS6000_BUILTIN_E

60459

+#undef RS6000_BUILTIN_H

60460

#undef RS6000_BUILTIN_P

60461

#undef RS6000_BUILTIN_Q

60462

#undef RS6000_BUILTIN_S

60463

#undef RS6000_BUILTIN_X

60464

60465

+#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)

60466

+#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)

60467

+#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)

60468

+#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)

60469

+#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)

60470

+#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)

60471

+#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \

60472

+ { MASK, ICODE, NAME, ENUM },

60473

+

60474

+#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)

60475

+#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)

60476

+#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)

60477

+#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)

60478

+

60479

+static const struct builtin_description bdesc_htm[] =

60480

+{

60481

+#include "rs6000-builtin.def"

60482

+};

60483

+

60484

+#undef RS6000_BUILTIN_1

60485

+#undef RS6000_BUILTIN_2

60486

+#undef RS6000_BUILTIN_3

60487

+#undef RS6000_BUILTIN_A

60488

+#undef RS6000_BUILTIN_D

60489

+#undef RS6000_BUILTIN_E

60490

+#undef RS6000_BUILTIN_H

60491

+#undef RS6000_BUILTIN_P

60492

+#undef RS6000_BUILTIN_Q

60493

+#undef RS6000_BUILTIN_S

60494

+

60495

/* Return true if a builtin function is overloaded. */

60496

bool

60497

rs6000_overloaded_builtin_p (enum rs6000_builtins fncode)

60498

@@ -10189,7 +11881,101 @@

60499

return target;

60500

}

60501

60502

+/* Return a constant vector for use as a little-endian permute control vector

60503

+ to reverse the order of elements of the given vector mode. */

60504

static rtx

60505

+swap_selector_for_mode (enum machine_mode mode)

60506

+{

60507

+ /* These are little endian vectors, so their elements are reversed

60508

+ from what you would normally expect for a permute control vector. */

60509

+ unsigned int swap2[16] = {7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8};

60510

+ unsigned int swap4[16] = {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12};

60511

+ unsigned int swap8[16] = {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14};

60512

+ unsigned int swap16[16] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};

60513

+ unsigned int *swaparray, i;

60514

+ rtx perm[16];

60515

+

60516

+ switch (mode)

60517

+ {

60518

+ case V2DFmode:

60519

+ case V2DImode:

60520

+ swaparray = swap2;

60521

+ break;

60522

+ case V4SFmode:

60523

+ case V4SImode:

60524

+ swaparray = swap4;

60525

+ break;

60526

+ case V8HImode:

60527

+ swaparray = swap8;

60528

+ break;

60529

+ case V16QImode:

60530

+ swaparray = swap16;

60531

+ break;

60532

+ default:

60533

+ gcc_unreachable ();

60534

+ }

60535

+

60536

+ for (i = 0; i < 16; ++i)

60537

+ perm[i] = GEN_INT (swaparray[i]);

60538

+

60539

+ return force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, perm)));

60540

+}

60541

+

60542

+/* Generate code for an "lvx", "lvxl", or "lve*x" built-in for a little endian target

60543

+ with -maltivec=be specified. Issue the load followed by an element-reversing

60544

+ permute. */

60545

+void

60546

+altivec_expand_lvx_be (rtx op0, rtx op1, enum machine_mode mode, unsigned unspec)

60547

+{

60548

+ rtx tmp = gen_reg_rtx (mode);

60549

+ rtx load = gen_rtx_SET (VOIDmode, tmp, op1);

60550

+ rtx lvx = gen_rtx_UNSPEC (mode, gen_rtvec (1, const0_rtx), unspec);

60551

+ rtx par = gen_rtx_PARALLEL (mode, gen_rtvec (2, load, lvx));

60552

+ rtx sel = swap_selector_for_mode (mode);

60553

+ rtx vperm = gen_rtx_UNSPEC (mode, gen_rtvec (3, tmp, tmp, sel), UNSPEC_VPERM);

60554

+

60555

+ gcc_assert (REG_P (op0));

60556

+ emit_insn (par);

60557

+ emit_insn (gen_rtx_SET (VOIDmode, op0, vperm));

60558

+}

60559

+

60560

+/* Generate code for a "stvx" or "stvxl" built-in for a little endian target

60561

+ with -maltivec=be specified. Issue the store preceded by an element-reversing

60562

+ permute. */

60563

+void

60564

+altivec_expand_stvx_be (rtx op0, rtx op1, enum machine_mode mode, unsigned unspec)

60565

+{

60566

+ rtx tmp = gen_reg_rtx (mode);

60567

+ rtx store = gen_rtx_SET (VOIDmode, op0, tmp);

60568

+ rtx stvx = gen_rtx_UNSPEC (mode, gen_rtvec (1, const0_rtx), unspec);

60569

+ rtx par = gen_rtx_PARALLEL (mode, gen_rtvec (2, store, stvx));

60570

+ rtx sel = swap_selector_for_mode (mode);

60571

+ rtx vperm;

60572

+

60573

+ gcc_assert (REG_P (op1));

60574

+ vperm = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op1, sel), UNSPEC_VPERM);

60575

+ emit_insn (gen_rtx_SET (VOIDmode, tmp, vperm));

60576

+ emit_insn (par);

60577

+}

60578

+

60579

+/* Generate code for a "stve*x" built-in for a little endian target with -maltivec=be

60580

+ specified. Issue the store preceded by an element-reversing permute. */

60581

+void

60582

+altivec_expand_stvex_be (rtx op0, rtx op1, enum machine_mode mode, unsigned unspec)

60583

+{

60584

+ enum machine_mode inner_mode = GET_MODE_INNER (mode);

60585

+ rtx tmp = gen_reg_rtx (mode);

60586

+ rtx stvx = gen_rtx_UNSPEC (inner_mode, gen_rtvec (1, tmp), unspec);

60587

+ rtx sel = swap_selector_for_mode (mode);

60588

+ rtx vperm;

60589

+

60590

+ gcc_assert (REG_P (op1));

60591

+ vperm = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op1, sel), UNSPEC_VPERM);

60592

+ emit_insn (gen_rtx_SET (VOIDmode, tmp, vperm));

60593

+ emit_insn (gen_rtx_SET (VOIDmode, op0, stvx));

60594

+}

60595

+

60596

+static rtx

60597

altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target, bool blk)

60598

{

60599

rtx pat, addr;

60600

@@ -10351,7 +12137,198 @@

60601

return NULL_RTX;

60602

}

60603

60604

+/* Return the appropriate SPR number associated with the given builtin. */

60605

+static inline HOST_WIDE_INT

60606

+htm_spr_num (enum rs6000_builtins code)

60607

+{

60608

+ if (code == HTM_BUILTIN_GET_TFHAR

60609

+ || code == HTM_BUILTIN_SET_TFHAR)

60610

+ return TFHAR_SPR;

60611

+ else if (code == HTM_BUILTIN_GET_TFIAR

60612

+ || code == HTM_BUILTIN_SET_TFIAR)

60613

+ return TFIAR_SPR;

60614

+ else if (code == HTM_BUILTIN_GET_TEXASR

60615

+ || code == HTM_BUILTIN_SET_TEXASR)

60616

+ return TEXASR_SPR;

60617

+ gcc_assert (code == HTM_BUILTIN_GET_TEXASRU

60618

+ || code == HTM_BUILTIN_SET_TEXASRU);

60619

+ return TEXASRU_SPR;

60620

+}

60621

+

60622

+/* Return the appropriate SPR regno associated with the given builtin. */

60623

+static inline HOST_WIDE_INT

60624

+htm_spr_regno (enum rs6000_builtins code)

60625

+{

60626

+ if (code == HTM_BUILTIN_GET_TFHAR

60627

+ || code == HTM_BUILTIN_SET_TFHAR)

60628

+ return TFHAR_REGNO;

60629

+ else if (code == HTM_BUILTIN_GET_TFIAR

60630

+ || code == HTM_BUILTIN_SET_TFIAR)

60631

+ return TFIAR_REGNO;

60632

+ gcc_assert (code == HTM_BUILTIN_GET_TEXASR

60633

+ || code == HTM_BUILTIN_SET_TEXASR

60634

+ || code == HTM_BUILTIN_GET_TEXASRU

60635

+ || code == HTM_BUILTIN_SET_TEXASRU);

60636

+ return TEXASR_REGNO;

60637

+}

60638

+

60639

+/* Return the correct ICODE value depending on whether we are

60640

+ setting or reading the HTM SPRs. */

60641

+static inline enum insn_code

60642

+rs6000_htm_spr_icode (bool nonvoid)

60643

+{

60644

+ if (nonvoid)

60645

+ return (TARGET_64BIT) ? CODE_FOR_htm_mfspr_di : CODE_FOR_htm_mfspr_si;

60646

+ else

60647

+ return (TARGET_64BIT) ? CODE_FOR_htm_mtspr_di : CODE_FOR_htm_mtspr_si;

60648

+}

60649

+

60650

+/* Expand the HTM builtin in EXP and store the result in TARGET.

60651

+ Store true in *EXPANDEDP if we found a builtin to expand. */

60652

static rtx

60653

+htm_expand_builtin (tree exp, rtx target, bool * expandedp)

60654

+{

60655

+ tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);

60656

+ bool nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;

60657

+ enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);

60658

+ const struct builtin_description *d;

60659

+ size_t i;

60660

+

60661

+ *expandedp = false;

60662

+

60663

+ /* Expand the HTM builtins. */

60664

+ d = bdesc_htm;

60665

+ for (i = 0; i < ARRAY_SIZE (bdesc_htm); i++, d++)

60666

+ if (d->code == fcode)

60667

+ {

60668

+ rtx op[MAX_HTM_OPERANDS], pat;

60669

+ int nopnds = 0;

60670

+ tree arg;

60671

+ call_expr_arg_iterator iter;

60672

+ unsigned attr = rs6000_builtin_info[fcode].attr;

60673

+ enum insn_code icode = d->icode;

60674

+

60675

+ if (attr & RS6000_BTC_SPR)

60676

+ icode = rs6000_htm_spr_icode (nonvoid);

60677

+

60678

+ if (nonvoid)

60679

+ {

60680

+ enum machine_mode tmode = insn_data[icode].operand[0].mode;

60681

+ if (!target

60682

+ || GET_MODE (target) != tmode

60683

+ || !(*insn_data[icode].operand[0].predicate) (target, tmode))

60684

+ target = gen_reg_rtx (tmode);

60685

+ op[nopnds++] = target;

60686

+ }

60687

+

60688

+ FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)

60689

+ {

60690

+ const struct insn_operand_data *insn_op;

60691

+

60692

+ if (arg == error_mark_node || nopnds >= MAX_HTM_OPERANDS)

60693

+ return NULL_RTX;

60694

+

60695

+ insn_op = &insn_data[icode].operand[nopnds];

60696

+

60697

+ op[nopnds] = expand_normal (arg);

60698

+

60699

+ if (!(*insn_op->predicate) (op[nopnds], insn_op->mode))

60700

+ {

60701

+ if (!strcmp (insn_op->constraint, "n"))

60702

+ {

60703

+ int arg_num = (nonvoid) ? nopnds : nopnds + 1;

60704

+ if (!CONST_INT_P (op[nopnds]))

60705

+ error ("argument %d must be an unsigned literal", arg_num);

60706

+ else

60707

+ error ("argument %d is an unsigned literal that is "

60708

+ "out of range", arg_num);

60709

+ return const0_rtx;

60710

+ }

60711

+ op[nopnds] = copy_to_mode_reg (insn_op->mode, op[nopnds]);

60712

+ }

60713

+

60714

+ nopnds++;

60715

+ }

60716

+

60717

+ /* Handle the builtins for extended mnemonics. These accept

60718

+ no arguments, but map to builtins that take arguments. */

60719

+ switch (fcode)

60720

+ {

60721

+ case HTM_BUILTIN_TENDALL: /* Alias for: tend. 1 */

60722

+ case HTM_BUILTIN_TRESUME: /* Alias for: tsr. 1 */

60723

+ op[nopnds++] = GEN_INT (1);

60724

+#ifdef ENABLE_CHECKING

60725

+ attr |= RS6000_BTC_UNARY;

60726

+#endif

60727

+ break;

60728

+ case HTM_BUILTIN_TSUSPEND: /* Alias for: tsr. 0 */

60729

+ op[nopnds++] = GEN_INT (0);

60730

+#ifdef ENABLE_CHECKING

60731

+ attr |= RS6000_BTC_UNARY;

60732

+#endif

60733

+ break;

60734

+ default:

60735

+ break;

60736

+ }

60737

+

60738

+ /* If this builtin accesses SPRs, then pass in the appropriate

60739

+ SPR number and SPR regno as the last two operands. */

60740

+ if (attr & RS6000_BTC_SPR)

60741

+ {

60742

+ op[nopnds++] = gen_rtx_CONST_INT (Pmode, htm_spr_num (fcode));

60743

+ op[nopnds++] = gen_rtx_REG (Pmode, htm_spr_regno (fcode));

60744

+ }

60745

+

60746

+#ifdef ENABLE_CHECKING

60747

+ int expected_nopnds = 0;

60748

+ if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_UNARY)

60749

+ expected_nopnds = 1;

60750

+ else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_BINARY)

60751

+ expected_nopnds = 2;

60752

+ else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_TERNARY)

60753

+ expected_nopnds = 3;

60754

+ if (!(attr & RS6000_BTC_VOID))

60755

+ expected_nopnds += 1;

60756

+ if (attr & RS6000_BTC_SPR)

60757

+ expected_nopnds += 2;

60758

+

60759

+ gcc_assert (nopnds == expected_nopnds && nopnds <= MAX_HTM_OPERANDS);

60760

+#endif

60761

+

60762

+ switch (nopnds)

60763

+ {

60764

+ case 0:

60765

+ pat = GEN_FCN (icode) (NULL_RTX);

60766

+ break;

60767

+ case 1:

60768

+ pat = GEN_FCN (icode) (op[0]);

60769

+ break;

60770

+ case 2:

60771

+ pat = GEN_FCN (icode) (op[0], op[1]);

60772

+ break;

60773

+ case 3:

60774

+ pat = GEN_FCN (icode) (op[0], op[1], op[2]);

60775

+ break;

60776

+ case 4:

60777

+ pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);

60778

+ break;

60779

+ default:

60780

+ gcc_unreachable ();

60781

+ }

60782

+ if (!pat)

60783

+ return NULL_RTX;

60784

+ emit_insn (pat);

60785

+

60786

+ *expandedp = true;

60787

+ if (nonvoid)

60788

+ return target;

60789

+ return const0_rtx;

60790

+ }

60791

+

60792

+ return NULL_RTX;

60793

+}

60794

+

60795

+static rtx

60796

rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target)

60797

{

60798

rtx pat;

60799

@@ -10416,7 +12393,15 @@

60800

}

60801

}

60802

else if (icode == CODE_FOR_vsx_set_v2df

60803

- || icode == CODE_FOR_vsx_set_v2di)

60804

+ || icode == CODE_FOR_vsx_set_v2di

60805

+ || icode == CODE_FOR_bcdadd

60806

+ || icode == CODE_FOR_bcdadd_lt

60807

+ || icode == CODE_FOR_bcdadd_eq

60808

+ || icode == CODE_FOR_bcdadd_gt

60809

+ || icode == CODE_FOR_bcdsub

60810

+ || icode == CODE_FOR_bcdsub_lt

60811

+ || icode == CODE_FOR_bcdsub_eq

60812

+ || icode == CODE_FOR_bcdsub_gt)

60813

{

60814

/* Only allow 1-bit unsigned literals. */

60815

STRIP_NOPS (arg2);

60816

@@ -10427,7 +12412,66 @@

60817

return const0_rtx;

60818

}

60819

}

60820

+ else if (icode == CODE_FOR_dfp_ddedpd_dd

60821

+ || icode == CODE_FOR_dfp_ddedpd_td)

60822

+ {

60823

+ /* Only allow 2-bit unsigned literals where the value is 0 or 2. */

60824

+ STRIP_NOPS (arg0);

60825

+ if (TREE_CODE (arg0) != INTEGER_CST

60826

+ || TREE_INT_CST_LOW (arg2) & ~0x3)

60827

+ {

60828

+ error ("argument 1 must be 0 or 2");

60829

+ return const0_rtx;

60830

+ }

60831

+ }

60832

+ else if (icode == CODE_FOR_dfp_denbcd_dd

60833

+ || icode == CODE_FOR_dfp_denbcd_td)

60834

+ {

60835

+ /* Only allow 1-bit unsigned literals. */

60836

+ STRIP_NOPS (arg0);

60837

+ if (TREE_CODE (arg0) != INTEGER_CST

60838

+ || TREE_INT_CST_LOW (arg0) & ~0x1)

60839

+ {

60840

+ error ("argument 1 must be a 1-bit unsigned literal");

60841

+ return const0_rtx;

60842

+ }

60843

+ }

60844

+ else if (icode == CODE_FOR_dfp_dscli_dd

60845

+ || icode == CODE_FOR_dfp_dscli_td

60846

+ || icode == CODE_FOR_dfp_dscri_dd

60847

+ || icode == CODE_FOR_dfp_dscri_td)

60848

+ {

60849

+ /* Only allow 6-bit unsigned literals. */

60850

+ STRIP_NOPS (arg1);

60851

+ if (TREE_CODE (arg1) != INTEGER_CST

60852

+ || TREE_INT_CST_LOW (arg1) & ~0x3f)

60853

+ {

60854

+ error ("argument 2 must be a 6-bit unsigned literal");

60855

+ return const0_rtx;

60856

+ }

60857

+ }

60858

+ else if (icode == CODE_FOR_crypto_vshasigmaw

60859

+ || icode == CODE_FOR_crypto_vshasigmad)

60860

+ {

60861

+ /* Check whether the 2nd and 3rd arguments are integer constants and in

60862

+ range and prepare arguments. */

60863

+ STRIP_NOPS (arg1);

60864

+ if (TREE_CODE (arg1) != INTEGER_CST

60865

+ || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 1))

60866

+ {

60867

+ error ("argument 2 must be 0 or 1");

60868

+ return const0_rtx;

60869

+ }

60870

60871

+ STRIP_NOPS (arg2);

60872

+ if (TREE_CODE (arg2) != INTEGER_CST

60873

+ || !IN_RANGE (TREE_INT_CST_LOW (arg2), 0, 15))

60874

+ {

60875

+ error ("argument 3 must be in the range 0..15");

60876

+ return const0_rtx;

60877

+ }

60878

+ }

60879

+

60880

if (target == 0

60881

|| GET_MODE (target) != tmode

60882

|| ! (*insn_data[icode].operand[0].predicate) (target, tmode))

60883

@@ -10481,6 +12525,8 @@

60884

break;

60885

case ALTIVEC_BUILTIN_LD_INTERNAL_2di:

60886

icode = CODE_FOR_vector_altivec_load_v2di;

60887

+ case ALTIVEC_BUILTIN_LD_INTERNAL_1ti:

60888

+ icode = CODE_FOR_vector_altivec_load_v1ti;

60889

break;

60890

default:

60891

*expandedp = false;

60892

@@ -10540,6 +12586,8 @@

60893

break;

60894

case ALTIVEC_BUILTIN_ST_INTERNAL_2di:

60895

icode = CODE_FOR_vector_altivec_store_v2di;

60896

+ case ALTIVEC_BUILTIN_ST_INTERNAL_1ti:

60897

+ icode = CODE_FOR_vector_altivec_store_v1ti;

60898

break;

60899

default:

60900

*expandedp = false;

60901

@@ -10632,21 +12680,33 @@

60902

enum machine_mode tmode = TYPE_MODE (type);

60903

enum machine_mode inner_mode = GET_MODE_INNER (tmode);

60904

int i, n_elt = GET_MODE_NUNITS (tmode);

60905

- rtvec v = rtvec_alloc (n_elt);

60906

60907

gcc_assert (VECTOR_MODE_P (tmode));

60908

gcc_assert (n_elt == call_expr_nargs (exp));

60909

60910

- for (i = 0; i < n_elt; ++i)

60911

+ if (!target || !register_operand (target, tmode))

60912

+ target = gen_reg_rtx (tmode);

60913

+

60914

+ /* If we have a vector compromised of a single element, such as V1TImode, do

60915

+ the initialization directly. */

60916

+ if (n_elt == 1 && GET_MODE_SIZE (tmode) == GET_MODE_SIZE (inner_mode))

60917

{

60918

- rtx x = expand_normal (CALL_EXPR_ARG (exp, i));

60919

- RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);

60920

+ rtx x = expand_normal (CALL_EXPR_ARG (exp, 0));

60921

+ emit_move_insn (target, gen_lowpart (tmode, x));

60922

}

60923

+ else

60924

+ {

60925

+ rtvec v = rtvec_alloc (n_elt);

60926

60927

- if (!target || !register_operand (target, tmode))

60928

- target = gen_reg_rtx (tmode);

60929

+ for (i = 0; i < n_elt; ++i)

60930

+ {

60931

+ rtx x = expand_normal (CALL_EXPR_ARG (exp, i));

60932

+ RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);

60933

+ }

60934

60935

- rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));

60936

+ rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));

60937

+ }

60938

+

60939

return target;

60940

}

60941

60942

@@ -10769,8 +12829,19 @@

60943

60944

switch (fcode)

60945

{

60946

+ case ALTIVEC_BUILTIN_STVX_V2DF:

60947

+ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2df, exp);

60948

+ case ALTIVEC_BUILTIN_STVX_V2DI:

60949

+ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2di, exp);

60950

+ case ALTIVEC_BUILTIN_STVX_V4SF:

60951

+ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4sf, exp);

60952

case ALTIVEC_BUILTIN_STVX:

60953

+ case ALTIVEC_BUILTIN_STVX_V4SI:

60954

return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si, exp);

60955

+ case ALTIVEC_BUILTIN_STVX_V8HI:

60956

+ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v8hi, exp);

60957

+ case ALTIVEC_BUILTIN_STVX_V16QI:

60958

+ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v16qi, exp);

60959

case ALTIVEC_BUILTIN_STVEBX:

60960

return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);

60961

case ALTIVEC_BUILTIN_STVEHX:

60962

@@ -10777,8 +12848,19 @@

60963

return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp);

60964

case ALTIVEC_BUILTIN_STVEWX:

60965

return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp);

60966

+ case ALTIVEC_BUILTIN_STVXL_V2DF:

60967

+ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2df, exp);

60968

+ case ALTIVEC_BUILTIN_STVXL_V2DI:

60969

+ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2di, exp);

60970

+ case ALTIVEC_BUILTIN_STVXL_V4SF:

60971

+ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4sf, exp);

60972

case ALTIVEC_BUILTIN_STVXL:

60973

- return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, exp);

60974

+ case ALTIVEC_BUILTIN_STVXL_V4SI:

60975

+ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4si, exp);

60976

+ case ALTIVEC_BUILTIN_STVXL_V8HI:

60977

+ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v8hi, exp);

60978

+ case ALTIVEC_BUILTIN_STVXL_V16QI:

60979

+ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v16qi, exp);

60980

60981

case ALTIVEC_BUILTIN_STVLX:

60982

return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx, exp);

60983

@@ -10789,6 +12871,8 @@

60984

case ALTIVEC_BUILTIN_STVRXL:

60985

return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl, exp);

60986

60987

+ case VSX_BUILTIN_STXVD2X_V1TI:

60988

+ return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v1ti, exp);

60989

case VSX_BUILTIN_STXVD2X_V2DF:

60990

return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df, exp);

60991

case VSX_BUILTIN_STXVD2X_V2DI:

60992

@@ -10869,6 +12953,7 @@

60993

case ALTIVEC_BUILTIN_VEC_INIT_V4SF:

60994

case VSX_BUILTIN_VEC_INIT_V2DF:

60995

case VSX_BUILTIN_VEC_INIT_V2DI:

60996

+ case VSX_BUILTIN_VEC_INIT_V1TI:

60997

return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);

60998

60999

case ALTIVEC_BUILTIN_VEC_SET_V4SI:

61000

@@ -10877,6 +12962,7 @@

61001

case ALTIVEC_BUILTIN_VEC_SET_V4SF:

61002

case VSX_BUILTIN_VEC_SET_V2DF:

61003

case VSX_BUILTIN_VEC_SET_V2DI:

61004

+ case VSX_BUILTIN_VEC_SET_V1TI:

61005

return altivec_expand_vec_set_builtin (exp);

61006

61007

case ALTIVEC_BUILTIN_VEC_EXT_V4SI:

61008

@@ -10885,6 +12971,7 @@

61009

case ALTIVEC_BUILTIN_VEC_EXT_V4SF:

61010

case VSX_BUILTIN_VEC_EXT_V2DF:

61011

case VSX_BUILTIN_VEC_EXT_V2DI:

61012

+ case VSX_BUILTIN_VEC_EXT_V1TI:

61013

return altivec_expand_vec_ext_builtin (exp, target);

61014

61015

default:

61016

@@ -10922,12 +13009,44 @@

61017

case ALTIVEC_BUILTIN_LVEWX:

61018

return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,

61019

exp, target, false);

61020

+ case ALTIVEC_BUILTIN_LVXL_V2DF:

61021

+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2df,

61022

+ exp, target, false);

61023

+ case ALTIVEC_BUILTIN_LVXL_V2DI:

61024

+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2di,

61025

+ exp, target, false);

61026

+ case ALTIVEC_BUILTIN_LVXL_V4SF:

61027

+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4sf,

61028

+ exp, target, false);

61029

case ALTIVEC_BUILTIN_LVXL:

61030

- return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,

61031

+ case ALTIVEC_BUILTIN_LVXL_V4SI:

61032

+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4si,

61033

exp, target, false);

61034

+ case ALTIVEC_BUILTIN_LVXL_V8HI:

61035

+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v8hi,

61036

+ exp, target, false);

61037

+ case ALTIVEC_BUILTIN_LVXL_V16QI:

61038

+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v16qi,

61039

+ exp, target, false);

61040

+ case ALTIVEC_BUILTIN_LVX_V2DF:

61041

+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2df,

61042

+ exp, target, false);

61043

+ case ALTIVEC_BUILTIN_LVX_V2DI:

61044

+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2di,

61045

+ exp, target, false);

61046

+ case ALTIVEC_BUILTIN_LVX_V4SF:

61047

+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4sf,

61048

+ exp, target, false);

61049

case ALTIVEC_BUILTIN_LVX:

61050

+ case ALTIVEC_BUILTIN_LVX_V4SI:

61051

return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si,

61052

exp, target, false);

61053

+ case ALTIVEC_BUILTIN_LVX_V8HI:

61054

+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v8hi,

61055

+ exp, target, false);

61056

+ case ALTIVEC_BUILTIN_LVX_V16QI:

61057

+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v16qi,

61058

+ exp, target, false);

61059

case ALTIVEC_BUILTIN_LVLX:

61060

return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx,

61061

exp, target, true);

61062

@@ -10940,6 +13059,9 @@

61063

case ALTIVEC_BUILTIN_LVRXL:

61064

return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl,

61065

exp, target, true);

61066

+ case VSX_BUILTIN_LXVD2X_V1TI:

61067

+ return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v1ti,

61068

+ exp, target, false);

61069

case VSX_BUILTIN_LXVD2X_V2DF:

61070

return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df,

61071

exp, target, false);

61072

@@ -11411,6 +13533,8 @@

61073

error ("Builtin function %s is only valid for the cell processor", name);

61074

else if ((fnmask & RS6000_BTM_VSX) != 0)

61075

error ("Builtin function %s requires the -mvsx option", name);

61076

+ else if ((fnmask & RS6000_BTM_HTM) != 0)

61077

+ error ("Builtin function %s requires the -mhtm option", name);

61078

else if ((fnmask & RS6000_BTM_ALTIVEC) != 0)

61079

error ("Builtin function %s requires the -maltivec option", name);

61080

else if ((fnmask & RS6000_BTM_PAIRED) != 0)

61081

@@ -11417,6 +13541,16 @@

61082

error ("Builtin function %s requires the -mpaired option", name);

61083

else if ((fnmask & RS6000_BTM_SPE) != 0)

61084

error ("Builtin function %s requires the -mspe option", name);

61085

+ else if ((fnmask & (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))

61086

+ == (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))

61087

+ error ("Builtin function %s requires the -mhard-dfp and"

61088

+ "-mpower8-vector options", name);

61089

+ else if ((fnmask & RS6000_BTM_DFP) != 0)

61090

+ error ("Builtin function %s requires the -mhard-dfp option", name);

61091

+ else if ((fnmask & RS6000_BTM_P8_VECTOR) != 0)

61092

+ error ("Builtin function %s requires the -mpower8-vector option", name);

61093

+ else if ((fnmask & RS6000_BTM_HARD_FLOAT) != 0)

61094

+ error ("Builtin function %s requires the -mhard-float option", name);

61095

else

61096

error ("Builtin function %s is not supported with the current options",

61097

name);

61098

@@ -11515,7 +13649,8 @@

61099

case ALTIVEC_BUILTIN_MASK_FOR_LOAD:

61100

case ALTIVEC_BUILTIN_MASK_FOR_STORE:

61101

{

61102

- int icode = (int) CODE_FOR_altivec_lvsr;

61103

+ int icode = (BYTES_BIG_ENDIAN ? (int) CODE_FOR_altivec_lvsr

61104

+ : (int) CODE_FOR_altivec_lvsl);

61105

enum machine_mode tmode = insn_data[icode].operand[0].mode;

61106

enum machine_mode mode = insn_data[icode].operand[1].mode;

61107

tree arg;

61108

@@ -11590,9 +13725,19 @@

61109

if (success)

61110

return ret;

61111

}

61112

+ if (TARGET_HTM)

61113

+ {

61114

+ ret = htm_expand_builtin (exp, target, &success);

61115

61116

- gcc_assert (TARGET_ALTIVEC || TARGET_VSX || TARGET_SPE || TARGET_PAIRED_FLOAT);

61117

+ if (success)

61118

+ return ret;

61119

+ }

61120

61121

+ unsigned attr = rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK;

61122

+ gcc_assert (attr == RS6000_BTC_UNARY

61123

+ || attr == RS6000_BTC_BINARY

61124

+ || attr == RS6000_BTC_TERNARY);

61125

+

61126

/* Handle simple unary operations. */

61127

d = bdesc_1arg;

61128

for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)

61129

@@ -11648,6 +13793,14 @@

61130

opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);

61131

opaque_V4SI_type_node = build_opaque_vector_type (intSI_type_node, 4);

61132

61133

+ /* We use V1TI mode as a special container to hold __int128_t items that

61134

+ must live in VSX registers. */

61135

+ if (intTI_type_node)

61136

+ {

61137

+ V1TI_type_node = build_vector_type (intTI_type_node, 1);

61138

+ unsigned_V1TI_type_node = build_vector_type (unsigned_intTI_type_node, 1);

61139

+ }

61140

+

61141

/* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'

61142

types, especially in C++ land. Similarly, 'vector pixel' is distinct from

61143

'vector unsigned short'. */

61144

@@ -11670,8 +13823,13 @@

61145

uintSI_type_internal_node = unsigned_intSI_type_node;

61146

intDI_type_internal_node = intDI_type_node;

61147

uintDI_type_internal_node = unsigned_intDI_type_node;

61148

+ intTI_type_internal_node = intTI_type_node;

61149

+ uintTI_type_internal_node = unsigned_intTI_type_node;

61150

float_type_internal_node = float_type_node;

61151

double_type_internal_node = double_type_node;

61152

+ long_double_type_internal_node = long_double_type_node;

61153

+ dfloat64_type_internal_node = dfloat64_type_node;

61154

+ dfloat128_type_internal_node = dfloat128_type_node;

61155

void_type_internal_node = void_type_node;

61156

61157

/* Initialize the modes for builtin_function_type, mapping a machine mode to

61158

@@ -11682,8 +13840,15 @@

61159

builtin_mode_to_type[SImode][1] = unsigned_intSI_type_node;

61160

builtin_mode_to_type[DImode][0] = intDI_type_node;

61161

builtin_mode_to_type[DImode][1] = unsigned_intDI_type_node;

61162

+ builtin_mode_to_type[TImode][0] = intTI_type_node;

61163

+ builtin_mode_to_type[TImode][1] = unsigned_intTI_type_node;

61164

builtin_mode_to_type[SFmode][0] = float_type_node;

61165

builtin_mode_to_type[DFmode][0] = double_type_node;

61166

+ builtin_mode_to_type[TFmode][0] = long_double_type_node;

61167

+ builtin_mode_to_type[DDmode][0] = dfloat64_type_node;

61168

+ builtin_mode_to_type[TDmode][0] = dfloat128_type_node;

61169

+ builtin_mode_to_type[V1TImode][0] = V1TI_type_node;

61170

+ builtin_mode_to_type[V1TImode][1] = unsigned_V1TI_type_node;

61171

builtin_mode_to_type[V2SImode][0] = V2SI_type_node;

61172

builtin_mode_to_type[V2SFmode][0] = V2SF_type_node;

61173

builtin_mode_to_type[V2DImode][0] = V2DI_type_node;

61174

@@ -11752,15 +13917,42 @@

61175

tdecl = add_builtin_type ("__vector double", V2DF_type_node);

61176

TYPE_NAME (V2DF_type_node) = tdecl;

61177

61178

- tdecl = add_builtin_type ("__vector long", V2DI_type_node);

61179

- TYPE_NAME (V2DI_type_node) = tdecl;

61180

+ if (TARGET_POWERPC64)

61181

+ {

61182

+ tdecl = add_builtin_type ("__vector long", V2DI_type_node);

61183

+ TYPE_NAME (V2DI_type_node) = tdecl;

61184

61185

- tdecl = add_builtin_type ("__vector unsigned long", unsigned_V2DI_type_node);

61186

- TYPE_NAME (unsigned_V2DI_type_node) = tdecl;

61187

+ tdecl = add_builtin_type ("__vector unsigned long",

61188

+ unsigned_V2DI_type_node);

61189

+ TYPE_NAME (unsigned_V2DI_type_node) = tdecl;

61190

61191

- tdecl = add_builtin_type ("__vector __bool long", bool_V2DI_type_node);

61192

- TYPE_NAME (bool_V2DI_type_node) = tdecl;

61193

+ tdecl = add_builtin_type ("__vector __bool long", bool_V2DI_type_node);

61194

+ TYPE_NAME (bool_V2DI_type_node) = tdecl;

61195

+ }

61196

+ else

61197

+ {

61198

+ tdecl = add_builtin_type ("__vector long long", V2DI_type_node);

61199

+ TYPE_NAME (V2DI_type_node) = tdecl;

61200

61201

+ tdecl = add_builtin_type ("__vector unsigned long long",

61202

+ unsigned_V2DI_type_node);

61203

+ TYPE_NAME (unsigned_V2DI_type_node) = tdecl;

61204

+

61205

+ tdecl = add_builtin_type ("__vector __bool long long",

61206

+ bool_V2DI_type_node);

61207

+ TYPE_NAME (bool_V2DI_type_node) = tdecl;

61208

+ }

61209

+

61210

+ if (V1TI_type_node)

61211

+ {

61212

+ tdecl = add_builtin_type ("__vector __int128", V1TI_type_node);

61213

+ TYPE_NAME (V1TI_type_node) = tdecl;

61214

+

61215

+ tdecl = add_builtin_type ("__vector unsigned __int128",

61216

+ unsigned_V1TI_type_node);

61217

+ TYPE_NAME (unsigned_V1TI_type_node) = tdecl;

61218

+ }

61219

+

61220

/* Paired and SPE builtins are only available if you build a compiler with

61221

the appropriate options, so only create those builtins with the

61222

appropriate compiler option. Create Altivec and VSX builtins on machines

61223

@@ -11772,6 +13964,9 @@

61224

spe_init_builtins ();

61225

if (TARGET_EXTRA_BUILTINS)

61226

altivec_init_builtins ();

61227

+ if (TARGET_HTM)

61228

+ htm_init_builtins ();

61229

+

61230

if (TARGET_EXTRA_BUILTINS || TARGET_SPE || TARGET_PAIRED_FLOAT)

61231

rs6000_common_init_builtins ();

61232

61233

@@ -12117,6 +14312,10 @@

61234

= build_function_type_list (integer_type_node,

61235

integer_type_node, V4SI_type_node,

61236

V4SI_type_node, NULL_TREE);

61237

+ tree int_ftype_int_v2di_v2di

61238

+ = build_function_type_list (integer_type_node,

61239

+ integer_type_node, V2DI_type_node,

61240

+ V2DI_type_node, NULL_TREE);

61241

tree void_ftype_v4si

61242

= build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);

61243

tree v8hi_ftype_void

61244

@@ -12199,6 +14398,8 @@

61245

= build_function_type_list (integer_type_node,

61246

integer_type_node, V2DF_type_node,

61247

V2DF_type_node, NULL_TREE);

61248

+ tree v2di_ftype_v2di

61249

+ = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);

61250

tree v4si_ftype_v4si

61251

= build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);

61252

tree v8hi_ftype_v8hi

61253

@@ -12224,10 +14425,58 @@

61254

def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);

61255

def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);

61256

def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);

61257

+ def_builtin ("__builtin_altivec_lvxl_v2df", v2df_ftype_long_pcvoid,

61258

+ ALTIVEC_BUILTIN_LVXL_V2DF);

61259

+ def_builtin ("__builtin_altivec_lvxl_v2di", v2di_ftype_long_pcvoid,

61260

+ ALTIVEC_BUILTIN_LVXL_V2DI);

61261

+ def_builtin ("__builtin_altivec_lvxl_v4sf", v4sf_ftype_long_pcvoid,

61262

+ ALTIVEC_BUILTIN_LVXL_V4SF);

61263

+ def_builtin ("__builtin_altivec_lvxl_v4si", v4si_ftype_long_pcvoid,

61264

+ ALTIVEC_BUILTIN_LVXL_V4SI);

61265

+ def_builtin ("__builtin_altivec_lvxl_v8hi", v8hi_ftype_long_pcvoid,

61266

+ ALTIVEC_BUILTIN_LVXL_V8HI);

61267

+ def_builtin ("__builtin_altivec_lvxl_v16qi", v16qi_ftype_long_pcvoid,

61268

+ ALTIVEC_BUILTIN_LVXL_V16QI);

61269

def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);

61270

+ def_builtin ("__builtin_altivec_lvx_v2df", v2df_ftype_long_pcvoid,

61271

+ ALTIVEC_BUILTIN_LVX_V2DF);

61272

+ def_builtin ("__builtin_altivec_lvx_v2di", v2di_ftype_long_pcvoid,

61273

+ ALTIVEC_BUILTIN_LVX_V2DI);

61274

+ def_builtin ("__builtin_altivec_lvx_v4sf", v4sf_ftype_long_pcvoid,

61275

+ ALTIVEC_BUILTIN_LVX_V4SF);

61276

+ def_builtin ("__builtin_altivec_lvx_v4si", v4si_ftype_long_pcvoid,

61277

+ ALTIVEC_BUILTIN_LVX_V4SI);

61278

+ def_builtin ("__builtin_altivec_lvx_v8hi", v8hi_ftype_long_pcvoid,

61279

+ ALTIVEC_BUILTIN_LVX_V8HI);

61280

+ def_builtin ("__builtin_altivec_lvx_v16qi", v16qi_ftype_long_pcvoid,

61281

+ ALTIVEC_BUILTIN_LVX_V16QI);

61282

def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);

61283

+ def_builtin ("__builtin_altivec_stvx_v2df", void_ftype_v2df_long_pvoid,

61284

+ ALTIVEC_BUILTIN_STVX_V2DF);

61285

+ def_builtin ("__builtin_altivec_stvx_v2di", void_ftype_v2di_long_pvoid,

61286

+ ALTIVEC_BUILTIN_STVX_V2DI);

61287

+ def_builtin ("__builtin_altivec_stvx_v4sf", void_ftype_v4sf_long_pvoid,

61288

+ ALTIVEC_BUILTIN_STVX_V4SF);

61289

+ def_builtin ("__builtin_altivec_stvx_v4si", void_ftype_v4si_long_pvoid,

61290

+ ALTIVEC_BUILTIN_STVX_V4SI);

61291

+ def_builtin ("__builtin_altivec_stvx_v8hi", void_ftype_v8hi_long_pvoid,

61292

+ ALTIVEC_BUILTIN_STVX_V8HI);

61293

+ def_builtin ("__builtin_altivec_stvx_v16qi", void_ftype_v16qi_long_pvoid,

61294

+ ALTIVEC_BUILTIN_STVX_V16QI);

61295

def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);

61296

def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);

61297

+ def_builtin ("__builtin_altivec_stvxl_v2df", void_ftype_v2df_long_pvoid,

61298

+ ALTIVEC_BUILTIN_STVXL_V2DF);

61299

+ def_builtin ("__builtin_altivec_stvxl_v2di", void_ftype_v2di_long_pvoid,

61300

+ ALTIVEC_BUILTIN_STVXL_V2DI);

61301

+ def_builtin ("__builtin_altivec_stvxl_v4sf", void_ftype_v4sf_long_pvoid,

61302

+ ALTIVEC_BUILTIN_STVXL_V4SF);

61303

+ def_builtin ("__builtin_altivec_stvxl_v4si", void_ftype_v4si_long_pvoid,

61304

+ ALTIVEC_BUILTIN_STVXL_V4SI);

61305

+ def_builtin ("__builtin_altivec_stvxl_v8hi", void_ftype_v8hi_long_pvoid,

61306

+ ALTIVEC_BUILTIN_STVXL_V8HI);

61307

+ def_builtin ("__builtin_altivec_stvxl_v16qi", void_ftype_v16qi_long_pvoid,

61308

+ ALTIVEC_BUILTIN_STVXL_V16QI);

61309

def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);

61310

def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);

61311

def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);

61312

@@ -12334,6 +14583,9 @@

61313

case VOIDmode:

61314

type = int_ftype_int_opaque_opaque;

61315

break;

61316

+ case V2DImode:

61317

+ type = int_ftype_int_v2di_v2di;

61318

+ break;

61319

case V4SImode:

61320

type = int_ftype_int_v4si_v4si;

61321

break;

61322

@@ -12367,6 +14619,9 @@

61323

61324

switch (mode0)

61325

{

61326

+ case V2DImode:

61327

+ type = v2di_ftype_v2di;

61328

+ break;

61329

case V4SImode:

61330

type = v4si_ftype_v4si;

61331

break;

61332

@@ -12497,8 +14752,109 @@

61333

ftype = build_function_type_list (intDI_type_node, V2DI_type_node,

61334

integer_type_node, NULL_TREE);

61335

def_builtin ("__builtin_vec_ext_v2di", ftype, VSX_BUILTIN_VEC_EXT_V2DI);

61336

+

61337

+

61338

+ if (V1TI_type_node)

61339

+ {

61340

+ tree v1ti_ftype_long_pcvoid

61341

+ = build_function_type_list (V1TI_type_node,

61342

+ long_integer_type_node, pcvoid_type_node,

61343

+ NULL_TREE);

61344

+ tree void_ftype_v1ti_long_pvoid

61345

+ = build_function_type_list (void_type_node,

61346

+ V1TI_type_node, long_integer_type_node,

61347

+ pvoid_type_node, NULL_TREE);

61348

+ def_builtin ("__builtin_vsx_lxvd2x_v1ti", v1ti_ftype_long_pcvoid,

61349

+ VSX_BUILTIN_LXVD2X_V1TI);

61350

+ def_builtin ("__builtin_vsx_stxvd2x_v1ti", void_ftype_v1ti_long_pvoid,

61351

+ VSX_BUILTIN_STXVD2X_V1TI);

61352

+ ftype = build_function_type_list (V1TI_type_node, intTI_type_node,

61353

+ NULL_TREE, NULL_TREE);

61354

+ def_builtin ("__builtin_vec_init_v1ti", ftype, VSX_BUILTIN_VEC_INIT_V1TI);

61355

+ ftype = build_function_type_list (V1TI_type_node, V1TI_type_node,

61356

+ intTI_type_node,

61357

+ integer_type_node, NULL_TREE);

61358

+ def_builtin ("__builtin_vec_set_v1ti", ftype, VSX_BUILTIN_VEC_SET_V1TI);

61359

+ ftype = build_function_type_list (intTI_type_node, V1TI_type_node,

61360

+ integer_type_node, NULL_TREE);

61361

+ def_builtin ("__builtin_vec_ext_v1ti", ftype, VSX_BUILTIN_VEC_EXT_V1TI);

61362

+ }

61363

+

61364

}

61365

61366

+static void

61367

+htm_init_builtins (void)

61368

+{

61369

+ HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;

61370

+ const struct builtin_description *d;

61371

+ size_t i;

61372

+

61373

+ d = bdesc_htm;

61374

+ for (i = 0; i < ARRAY_SIZE (bdesc_htm); i++, d++)

61375

+ {

61376

+ tree op[MAX_HTM_OPERANDS], type;

61377

+ HOST_WIDE_INT mask = d->mask;

61378

+ unsigned attr = rs6000_builtin_info[d->code].attr;

61379

+ bool void_func = (attr & RS6000_BTC_VOID);

61380

+ int attr_args = (attr & RS6000_BTC_TYPE_MASK);

61381

+ int nopnds = 0;

61382

+ tree argtype = (attr & RS6000_BTC_SPR) ? long_unsigned_type_node

61383

+ : unsigned_type_node;

61384

+

61385

+ if ((mask & builtin_mask) != mask)

61386

+ {

61387

+ if (TARGET_DEBUG_BUILTIN)

61388

+ fprintf (stderr, "htm_builtin, skip binary %s\n", d->name);

61389

+ continue;

61390

+ }

61391

+

61392

+ if (d->name == 0)

61393

+ {

61394

+ if (TARGET_DEBUG_BUILTIN)

61395

+ fprintf (stderr, "htm_builtin, bdesc_htm[%ld] no name\n",

61396

+ (long unsigned) i);

61397

+ continue;

61398

+ }

61399

+

61400

+ op[nopnds++] = (void_func) ? void_type_node : argtype;

61401

+

61402

+ if (attr_args == RS6000_BTC_UNARY)

61403

+ op[nopnds++] = argtype;

61404

+ else if (attr_args == RS6000_BTC_BINARY)

61405

+ {

61406

+ op[nopnds++] = argtype;

61407

+ op[nopnds++] = argtype;

61408

+ }

61409

+ else if (attr_args == RS6000_BTC_TERNARY)

61410

+ {

61411

+ op[nopnds++] = argtype;

61412

+ op[nopnds++] = argtype;

61413

+ op[nopnds++] = argtype;

61414

+ }

61415

+

61416

+ switch (nopnds)

61417

+ {

61418

+ case 1:

61419

+ type = build_function_type_list (op[0], NULL_TREE);

61420

+ break;

61421

+ case 2:

61422

+ type = build_function_type_list (op[0], op[1], NULL_TREE);

61423

+ break;

61424

+ case 3:

61425

+ type = build_function_type_list (op[0], op[1], op[2], NULL_TREE);

61426

+ break;

61427

+ case 4:

61428

+ type = build_function_type_list (op[0], op[1], op[2], op[3],

61429

+ NULL_TREE);

61430

+ break;

61431

+ default:

61432

+ gcc_unreachable ();

61433

+ }

61434

+

61435

+ def_builtin (d->name, type, d->code);

61436

+ }

61437

+}

61438

+

61439

/* Hash function for builtin functions with up to 3 arguments and a return

61440

type. */

61441

static unsigned

61442

@@ -12572,11 +14928,34 @@

61443

are type correct. */

61444

switch (builtin)

61445

{

61446

+ /* unsigned 1 argument functions. */

61447

+ case CRYPTO_BUILTIN_VSBOX:

61448

+ case P8V_BUILTIN_VGBBD:

61449

+ case MISC_BUILTIN_CDTBCD:

61450

+ case MISC_BUILTIN_CBCDTD:

61451

+ h.uns_p[0] = 1;

61452

+ h.uns_p[1] = 1;

61453

+ break;

61454

+

61455

/* unsigned 2 argument functions. */

61456

case ALTIVEC_BUILTIN_VMULEUB_UNS:

61457

case ALTIVEC_BUILTIN_VMULEUH_UNS:

61458

case ALTIVEC_BUILTIN_VMULOUB_UNS:

61459

case ALTIVEC_BUILTIN_VMULOUH_UNS:

61460

+ case CRYPTO_BUILTIN_VCIPHER:

61461

+ case CRYPTO_BUILTIN_VCIPHERLAST:

61462

+ case CRYPTO_BUILTIN_VNCIPHER:

61463

+ case CRYPTO_BUILTIN_VNCIPHERLAST:

61464

+ case CRYPTO_BUILTIN_VPMSUMB:

61465

+ case CRYPTO_BUILTIN_VPMSUMH:

61466

+ case CRYPTO_BUILTIN_VPMSUMW:

61467

+ case CRYPTO_BUILTIN_VPMSUMD:

61468

+ case CRYPTO_BUILTIN_VPMSUM:

61469

+ case MISC_BUILTIN_ADDG6S:

61470

+ case MISC_BUILTIN_DIVWEU:

61471

+ case MISC_BUILTIN_DIVWEUO:

61472

+ case MISC_BUILTIN_DIVDEU:

61473

+ case MISC_BUILTIN_DIVDEUO:

61474

h.uns_p[0] = 1;

61475

h.uns_p[1] = 1;

61476

h.uns_p[2] = 1;

61477

@@ -12599,6 +14978,14 @@

61478

case VSX_BUILTIN_XXSEL_8HI_UNS:

61479

case VSX_BUILTIN_XXSEL_4SI_UNS:

61480

case VSX_BUILTIN_XXSEL_2DI_UNS:

61481

+ case CRYPTO_BUILTIN_VPERMXOR:

61482

+ case CRYPTO_BUILTIN_VPERMXOR_V2DI:

61483

+ case CRYPTO_BUILTIN_VPERMXOR_V4SI:

61484

+ case CRYPTO_BUILTIN_VPERMXOR_V8HI:

61485

+ case CRYPTO_BUILTIN_VPERMXOR_V16QI:

61486

+ case CRYPTO_BUILTIN_VSHASIGMAW:

61487

+ case CRYPTO_BUILTIN_VSHASIGMAD:

61488

+ case CRYPTO_BUILTIN_VSHASIGMA:

61489

h.uns_p[0] = 1;

61490

h.uns_p[1] = 1;

61491

h.uns_p[2] = 1;

61492

@@ -12630,9 +15017,18 @@

61493

/* signed args, unsigned return. */

61494

case VSX_BUILTIN_XVCVDPUXDS_UNS:

61495

case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI:

61496

+ case MISC_BUILTIN_UNPACK_TD:

61497

+ case MISC_BUILTIN_UNPACK_V1TI:

61498

h.uns_p[0] = 1;

61499

break;

61500

61501

+ /* unsigned arguments for 128-bit pack instructions. */

61502

+ case MISC_BUILTIN_PACK_TD:

61503

+ case MISC_BUILTIN_PACK_V1TI:

61504

+ h.uns_p[1] = 1;

61505

+ h.uns_p[2] = 1;

61506

+ break;

61507

+

61508

default:

61509

break;

61510

}

61511

@@ -12740,9 +15136,24 @@

61512

else

61513

{

61514

enum insn_code icode = d->icode;

61515

- if (d->name == 0 || icode == CODE_FOR_nothing)

61516

- continue;

61517

+ if (d->name == 0)

61518

+ {

61519

+ if (TARGET_DEBUG_BUILTIN)

61520

+ fprintf (stderr, "rs6000_builtin, bdesc_3arg[%ld] no name\n",

61521

+ (long unsigned)i);

61522

61523

+ continue;

61524

+ }

61525

+

61526

+ if (icode == CODE_FOR_nothing)

61527

+ {

61528

+ if (TARGET_DEBUG_BUILTIN)

61529

+ fprintf (stderr, "rs6000_builtin, skip ternary %s (no code)\n",

61530

+ d->name);

61531

+

61532

+ continue;

61533

+ }

61534

+

61535

type = builtin_function_type (insn_data[icode].operand[0].mode,

61536

insn_data[icode].operand[1].mode,

61537

insn_data[icode].operand[2].mode,

61538

@@ -12780,9 +15191,24 @@

61539

else

61540

{

61541

enum insn_code icode = d->icode;

61542

- if (d->name == 0 || icode == CODE_FOR_nothing)

61543

- continue;

61544

+ if (d->name == 0)

61545

+ {

61546

+ if (TARGET_DEBUG_BUILTIN)

61547

+ fprintf (stderr, "rs6000_builtin, bdesc_2arg[%ld] no name\n",

61548

+ (long unsigned)i);

61549

61550

+ continue;

61551

+ }

61552

+

61553

+ if (icode == CODE_FOR_nothing)

61554

+ {

61555

+ if (TARGET_DEBUG_BUILTIN)

61556

+ fprintf (stderr, "rs6000_builtin, skip binary %s (no code)\n",

61557

+ d->name);

61558

+

61559

+ continue;

61560

+ }

61561

+

61562

mode0 = insn_data[icode].operand[0].mode;

61563

mode1 = insn_data[icode].operand[1].mode;

61564

mode2 = insn_data[icode].operand[2].mode;

61565

@@ -12842,9 +15268,24 @@

61566

else

61567

{

61568

enum insn_code icode = d->icode;

61569

- if (d->name == 0 || icode == CODE_FOR_nothing)

61570

- continue;

61571

+ if (d->name == 0)

61572

+ {

61573

+ if (TARGET_DEBUG_BUILTIN)

61574

+ fprintf (stderr, "rs6000_builtin, bdesc_1arg[%ld] no name\n",

61575

+ (long unsigned)i);

61576

61577

+ continue;

61578

+ }

61579

+

61580

+ if (icode == CODE_FOR_nothing)

61581

+ {

61582

+ if (TARGET_DEBUG_BUILTIN)

61583

+ fprintf (stderr, "rs6000_builtin, skip unary %s (no code)\n",

61584

+ d->name);

61585

+

61586

+ continue;

61587

+ }

61588

+

61589

mode0 = insn_data[icode].operand[0].mode;

61590

mode1 = insn_data[icode].operand[1].mode;

61591

61592

@@ -13631,7 +16072,7 @@

61593

static bool eliminated = false;

61594

rtx ret;

61595

61596

- if (mode != SDmode)

61597

+ if (mode != SDmode || TARGET_NO_SDMODE_STACK)

61598

ret = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);

61599

else

61600

{

61601

@@ -13660,6 +16101,17 @@

61602

return ret;

61603

}

61604

61605

+/* Return the mode to be used for memory when a secondary memory

61606

+ location is needed. For SDmode values we need to use DDmode, in

61607

+ all other cases we can use the same mode. */

61608

+enum machine_mode

61609

+rs6000_secondary_memory_needed_mode (enum machine_mode mode)

61610

+{

61611

+ if (mode == SDmode)

61612

+ return DDmode;

61613

+ return mode;

61614

+}

61615

+

61616

static tree

61617

rs6000_check_sdmode (tree *tp, int *walk_subtrees, void *data ATTRIBUTE_UNUSED)

61618

{

61619

@@ -13690,31 +16142,228 @@

61620

return NULL_TREE;

61621

}

61622

61623

-enum reload_reg_type {

61624

- GPR_REGISTER_TYPE,

61625

- VECTOR_REGISTER_TYPE,

61626

- OTHER_REGISTER_TYPE

61627

-};

61628

+/* Classify a register type. Because the FMRGOW/FMRGEW instructions only work

61629

+ on traditional floating point registers, and the VMRGOW/VMRGEW instructions

61630

+ only work on the traditional altivec registers, note if an altivec register

61631

+ was chosen. */

61632

61633

-static enum reload_reg_type

61634

-rs6000_reload_register_type (enum reg_class rclass)

61635

+static enum rs6000_reg_type

61636

+register_to_reg_type (rtx reg, bool *is_altivec)

61637

{

61638

- switch (rclass)

61639

+ HOST_WIDE_INT regno;

61640

+ enum reg_class rclass;

61641

+

61642

+ if (GET_CODE (reg) == SUBREG)

61643

+ reg = SUBREG_REG (reg);

61644

+

61645

+ if (!REG_P (reg))

61646

+ return NO_REG_TYPE;

61647

+

61648

+ regno = REGNO (reg);

61649

+ if (regno >= FIRST_PSEUDO_REGISTER)

61650

{

61651

- case GENERAL_REGS:

61652

- case BASE_REGS:

61653

- return GPR_REGISTER_TYPE;

61654

+ if (!lra_in_progress && !reload_in_progress && !reload_completed)

61655

+ return PSEUDO_REG_TYPE;

61656

61657

- case FLOAT_REGS:

61658

- case ALTIVEC_REGS:

61659

- case VSX_REGS:

61660

- return VECTOR_REGISTER_TYPE;

61661

+ regno = true_regnum (reg);

61662

+ if (regno < 0 || regno >= FIRST_PSEUDO_REGISTER)

61663

+ return PSEUDO_REG_TYPE;

61664

+ }

61665

61666

- default:

61667

- return OTHER_REGISTER_TYPE;

61668

+ gcc_assert (regno >= 0);

61669

+

61670

+ if (is_altivec && ALTIVEC_REGNO_P (regno))

61671

+ *is_altivec = true;

61672

+

61673

+ rclass = rs6000_regno_regclass[regno];

61674

+ return reg_class_to_reg_type[(int)rclass];

61675

+}

61676

+

61677

+/* Helper function for rs6000_secondary_reload to return true if a move to a

61678

+ different register classe is really a simple move. */

61679

+

61680

+static bool

61681

+rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type,

61682

+ enum rs6000_reg_type from_type,

61683

+ enum machine_mode mode)

61684

+{

61685

+ int size;

61686

+

61687

+ /* Add support for various direct moves available. In this function, we only

61688

+ look at cases where we don't need any extra registers, and one or more

61689

+ simple move insns are issued. At present, 32-bit integers are not allowed

61690

+ in FPR/VSX registers. Single precision binary floating is not a simple

61691

+ move because we need to convert to the single precision memory layout.

61692

+ The 4-byte SDmode can be moved. */

61693

+ size = GET_MODE_SIZE (mode);

61694

+ if (TARGET_DIRECT_MOVE

61695

+ && ((mode == SDmode) || (TARGET_POWERPC64 && size == 8))

61696

+ && ((to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)

61697

+ || (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)))

61698

+ return true;

61699

+

61700

+ else if (TARGET_MFPGPR && TARGET_POWERPC64 && size == 8

61701

+ && ((to_type == GPR_REG_TYPE && from_type == FPR_REG_TYPE)

61702

+ || (to_type == FPR_REG_TYPE && from_type == GPR_REG_TYPE)))

61703

+ return true;

61704

+

61705

+ else if ((size == 4 || (TARGET_POWERPC64 && size == 8))

61706

+ && ((to_type == GPR_REG_TYPE && from_type == SPR_REG_TYPE)

61707

+ || (to_type == SPR_REG_TYPE && from_type == GPR_REG_TYPE)))

61708

+ return true;

61709

+

61710

+ return false;

61711

+}

61712

+

61713

+/* Power8 helper function for rs6000_secondary_reload, handle all of the

61714

+ special direct moves that involve allocating an extra register, return the

61715

+ insn code of the helper function if there is such a function or

61716

+ CODE_FOR_nothing if not. */

61717

+

61718

+static bool

61719

+rs6000_secondary_reload_direct_move (enum rs6000_reg_type to_type,

61720

+ enum rs6000_reg_type from_type,

61721

+ enum machine_mode mode,

61722

+ secondary_reload_info *sri,

61723

+ bool altivec_p)

61724

+{

61725

+ bool ret = false;

61726

+ enum insn_code icode = CODE_FOR_nothing;

61727

+ int cost = 0;

61728

+ int size = GET_MODE_SIZE (mode);

61729

+

61730

+ if (TARGET_POWERPC64)

61731

+ {

61732

+ if (size == 16)

61733

+ {

61734

+ /* Handle moving 128-bit values from GPRs to VSX point registers on

61735

+ power8 when running in 64-bit mode using XXPERMDI to glue the two

61736

+ 64-bit values back together. */

61737

+ if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)

61738

+ {

61739

+ cost = 3; /* 2 mtvsrd's, 1 xxpermdi. */

61740

+ icode = reg_addr[mode].reload_vsx_gpr;

61741

+ }

61742

+

61743

+ /* Handle moving 128-bit values from VSX point registers to GPRs on

61744

+ power8 when running in 64-bit mode using XXPERMDI to get access to the

61745

+ bottom 64-bit value. */

61746

+ else if (to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)

61747

+ {

61748

+ cost = 3; /* 2 mfvsrd's, 1 xxpermdi. */

61749

+ icode = reg_addr[mode].reload_gpr_vsx;

61750

+ }

61751

+ }

61752

+

61753

+ else if (mode == SFmode)

61754

+ {

61755

+ if (to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)

61756

+ {

61757

+ cost = 3; /* xscvdpspn, mfvsrd, and. */

61758

+ icode = reg_addr[mode].reload_gpr_vsx;

61759

+ }

61760

+

61761

+ else if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)

61762

+ {

61763

+ cost = 2; /* mtvsrz, xscvspdpn. */

61764

+ icode = reg_addr[mode].reload_vsx_gpr;

61765

+ }

61766

+ }

61767

}

61768

+

61769

+ if (TARGET_POWERPC64 && size == 16)

61770

+ {

61771

+ /* Handle moving 128-bit values from GPRs to VSX point registers on

61772

+ power8 when running in 64-bit mode using XXPERMDI to glue the two

61773

+ 64-bit values back together. */

61774

+ if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)

61775

+ {

61776

+ cost = 3; /* 2 mtvsrd's, 1 xxpermdi. */

61777

+ icode = reg_addr[mode].reload_vsx_gpr;

61778

+ }

61779

+

61780

+ /* Handle moving 128-bit values from VSX point registers to GPRs on

61781

+ power8 when running in 64-bit mode using XXPERMDI to get access to the

61782

+ bottom 64-bit value. */

61783

+ else if (to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)

61784

+ {

61785

+ cost = 3; /* 2 mfvsrd's, 1 xxpermdi. */

61786

+ icode = reg_addr[mode].reload_gpr_vsx;

61787

+ }

61788

+ }

61789

+

61790

+ else if (!TARGET_POWERPC64 && size == 8)

61791

+ {

61792

+ /* Handle moving 64-bit values from GPRs to floating point registers on

61793

+ power8 when running in 32-bit mode using FMRGOW to glue the two 32-bit

61794

+ values back together. Altivec register classes must be handled

61795

+ specially since a different instruction is used, and the secondary

61796

+ reload support requires a single instruction class in the scratch

61797

+ register constraint. However, right now TFmode is not allowed in

61798

+ Altivec registers, so the pattern will never match. */

61799

+ if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE && !altivec_p)

61800

+ {

61801

+ cost = 3; /* 2 mtvsrwz's, 1 fmrgow. */

61802

+ icode = reg_addr[mode].reload_fpr_gpr;

61803

+ }

61804

+ }

61805

+

61806

+ if (icode != CODE_FOR_nothing)

61807

+ {

61808

+ ret = true;

61809

+ if (sri)

61810

+ {

61811

+ sri->icode = icode;

61812

+ sri->extra_cost = cost;

61813

+ }

61814

+ }

61815

+

61816

+ return ret;

61817

}

61818

61819

+/* Return whether a move between two register classes can be done either

61820

+ directly (simple move) or via a pattern that uses a single extra temporary

61821

+ (using power8's direct move in this case. */

61822

+

61823

+static bool

61824

+rs6000_secondary_reload_move (enum rs6000_reg_type to_type,

61825

+ enum rs6000_reg_type from_type,

61826

+ enum machine_mode mode,

61827

+ secondary_reload_info *sri,

61828

+ bool altivec_p)

61829

+{

61830

+ /* Fall back to load/store reloads if either type is not a register. */

61831

+ if (to_type == NO_REG_TYPE || from_type == NO_REG_TYPE)

61832

+ return false;

61833

+

61834

+ /* If we haven't allocated registers yet, assume the move can be done for the

61835

+ standard register types. */

61836

+ if ((to_type == PSEUDO_REG_TYPE && from_type == PSEUDO_REG_TYPE)

61837

+ || (to_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE (from_type))

61838

+ || (from_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE (to_type)))

61839

+ return true;

61840

+

61841

+ /* Moves to the same set of registers is a simple move for non-specialized

61842

+ registers. */

61843

+ if (to_type == from_type && IS_STD_REG_TYPE (to_type))

61844

+ return true;

61845

+

61846

+ /* Check whether a simple move can be done directly. */

61847

+ if (rs6000_secondary_reload_simple_move (to_type, from_type, mode))

61848

+ {

61849

+ if (sri)

61850

+ {

61851

+ sri->icode = CODE_FOR_nothing;

61852

+ sri->extra_cost = 0;

61853

+ }

61854

+ return true;

61855

+ }

61856

+

61857

+ /* Now check if we can do it in a few steps. */

61858

+ return rs6000_secondary_reload_direct_move (to_type, from_type, mode, sri,

61859

+ altivec_p);

61860

+}

61861

+

61862

/* Inform reload about cases where moving X with a mode MODE to a register in

61863

RCLASS requires an extra scratch or immediate register. Return the class

61864

needed for the immediate register.

61865

@@ -13738,12 +16387,36 @@

61866

bool default_p = false;

61867

61868

sri->icode = CODE_FOR_nothing;

61869

+ icode = ((in_p)

61870

+ ? reg_addr[mode].reload_load

61871

+ : reg_addr[mode].reload_store);

61872

61873

- /* Convert vector loads and stores into gprs to use an additional base

61874

- register. */

61875

- icode = rs6000_vector_reload[mode][in_p != false];

61876

- if (icode != CODE_FOR_nothing)

61877

+ if (REG_P (x) || register_operand (x, mode))

61878

{

61879

+ enum rs6000_reg_type to_type = reg_class_to_reg_type[(int)rclass];

61880

+ bool altivec_p = (rclass == ALTIVEC_REGS);

61881

+ enum rs6000_reg_type from_type = register_to_reg_type (x, &altivec_p);

61882

+

61883

+ if (!in_p)

61884

+ {

61885

+ enum rs6000_reg_type exchange = to_type;

61886

+ to_type = from_type;

61887

+ from_type = exchange;

61888

+ }

61889

+

61890

+ /* Can we do a direct move of some sort? */

61891

+ if (rs6000_secondary_reload_move (to_type, from_type, mode, sri,

61892

+ altivec_p))

61893

+ {

61894

+ icode = (enum insn_code)sri->icode;

61895

+ default_p = false;

61896

+ ret = NO_REGS;

61897

+ }

61898

+ }

61899

+

61900

+ /* Handle vector moves with reload helper functions. */

61901

+ if (ret == ALL_REGS && icode != CODE_FOR_nothing)

61902

+ {

61903

ret = NO_REGS;

61904

sri->icode = CODE_FOR_nothing;

61905

sri->extra_cost = 0;

61906

@@ -13754,14 +16427,23 @@

61907

61908

/* Loads to and stores from gprs can do reg+offset, and wouldn't need

61909

an extra register in that case, but it would need an extra

61910

- register if the addressing is reg+reg or (reg+reg)&(-16). */

61911

+ register if the addressing is reg+reg or (reg+reg)&(-16). Special

61912

+ case load/store quad. */

61913

if (rclass == GENERAL_REGS || rclass == BASE_REGS)

61914

{

61915

- if (!legitimate_indirect_address_p (addr, false)

61916

- && !rs6000_legitimate_offset_address_p (TImode, addr,

61917

- false, true))

61918

+ if (TARGET_POWERPC64 && TARGET_QUAD_MEMORY

61919

+ && GET_MODE_SIZE (mode) == 16

61920

+ && quad_memory_operand (x, mode))

61921

{

61922

sri->icode = icode;

61923

+ sri->extra_cost = 2;

61924

+ }

61925

+

61926

+ else if (!legitimate_indirect_address_p (addr, false)

61927

+ && !rs6000_legitimate_offset_address_p (PTImode, addr,

61928

+ false, true))

61929

+ {

61930

+ sri->icode = icode;

61931

/* account for splitting the loads, and converting the

61932

address from reg+reg to reg. */

61933

sri->extra_cost = (((TARGET_64BIT) ? 3 : 5)

61934

@@ -13768,8 +16450,20 @@

61935

+ ((GET_CODE (addr) == AND) ? 1 : 0));

61936

}

61937

}

61938

- /* Loads to and stores from vector registers can only do reg+reg

61939

- addressing. Altivec registers can also do (reg+reg)&(-16). */

61940

+ /* Allow scalar loads to/from the traditional floating point

61941

+ registers, even if VSX memory is set. */

61942

+ else if ((rclass == FLOAT_REGS || rclass == NO_REGS)

61943

+ && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8)

61944

+ && (legitimate_indirect_address_p (addr, false)

61945

+ || legitimate_indirect_address_p (addr, false)

61946

+ || rs6000_legitimate_offset_address_p (mode, addr,

61947

+ false, true)))

61948

+

61949

+ ;

61950

+ /* Loads to and stores from vector registers can only do reg+reg

61951

+ addressing. Altivec registers can also do (reg+reg)&(-16). Allow

61952

+ scalar modes loading up the traditional floating point registers

61953

+ to use offset addresses. */

61954

else if (rclass == VSX_REGS || rclass == ALTIVEC_REGS

61955

|| rclass == FLOAT_REGS || rclass == NO_REGS)

61956

{

61957

@@ -13813,12 +16507,12 @@

61958

else

61959

{

61960

enum reg_class xclass = REGNO_REG_CLASS (regno);

61961

- enum reload_reg_type rtype1 = rs6000_reload_register_type (rclass);

61962

- enum reload_reg_type rtype2 = rs6000_reload_register_type (xclass);

61963

+ enum rs6000_reg_type rtype1 = reg_class_to_reg_type[(int)rclass];

61964

+ enum rs6000_reg_type rtype2 = reg_class_to_reg_type[(int)xclass];

61965

61966

/* If memory is needed, use default_secondary_reload to create the

61967

stack slot. */

61968

- if (rtype1 != rtype2 || rtype1 == OTHER_REGISTER_TYPE)

61969

+ if (rtype1 != rtype2 || !IS_STD_REG_TYPE (rtype1))

61970

default_p = true;

61971

else

61972

ret = NO_REGS;

61973

@@ -13828,7 +16522,7 @@

61974

default_p = true;

61975

}

61976

else if (TARGET_POWERPC64

61977

- && rs6000_reload_register_type (rclass) == GPR_REGISTER_TYPE

61978

+ && reg_class_to_reg_type[(int)rclass] == GPR_REG_TYPE

61979

&& MEM_P (x)

61980

&& GET_MODE_SIZE (GET_MODE (x)) >= UNITS_PER_WORD)

61981

{

61982

@@ -13867,7 +16561,7 @@

61983

default_p = true;

61984

}

61985

else if (!TARGET_POWERPC64

61986

- && rs6000_reload_register_type (rclass) == GPR_REGISTER_TYPE

61987

+ && reg_class_to_reg_type[(int)rclass] == GPR_REG_TYPE

61988

&& MEM_P (x)

61989

&& GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)

61990

{

61991

@@ -13945,6 +16639,36 @@

61992

return ret;

61993

}

61994

61995

+/* Better tracing for rs6000_secondary_reload_inner. */

61996

+

61997

+static void

61998

+rs6000_secondary_reload_trace (int line, rtx reg, rtx mem, rtx scratch,

61999

+ bool store_p)

62000

+{

62001

+ rtx set, clobber;

62002

+

62003

+ gcc_assert (reg != NULL_RTX && mem != NULL_RTX && scratch != NULL_RTX);

62004

+

62005

+ fprintf (stderr, "rs6000_secondary_reload_inner:%d, type = %s\n", line,

62006

+ store_p ? "store" : "load");

62007

+

62008

+ if (store_p)

62009

+ set = gen_rtx_SET (VOIDmode, mem, reg);

62010

+ else

62011

+ set = gen_rtx_SET (VOIDmode, reg, mem);

62012

+

62013

+ clobber = gen_rtx_CLOBBER (VOIDmode, scratch);

62014

+ debug_rtx (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));

62015

+}

62016

+

62017

+static void

62018

+rs6000_secondary_reload_fail (int line, rtx reg, rtx mem, rtx scratch,

62019

+ bool store_p)

62020

+{

62021

+ rs6000_secondary_reload_trace (line, reg, mem, scratch, store_p);

62022

+ gcc_unreachable ();

62023

+}

62024

+

62025

/* Fixup reload addresses for Altivec or VSX loads/stores to change SP+offset

62026

to SP+reg addressing. */

62027

62028

@@ -13963,21 +16687,16 @@

62029

rtx cc_clobber;

62030

62031

if (TARGET_DEBUG_ADDR)

62032

- {

62033

- fprintf (stderr, "\nrs6000_secondary_reload_inner, type = %s\n",

62034

- store_p ? "store" : "load");

62035

- fprintf (stderr, "reg:\n");

62036

- debug_rtx (reg);

62037

- fprintf (stderr, "mem:\n");

62038

- debug_rtx (mem);

62039

- fprintf (stderr, "scratch:\n");

62040

- debug_rtx (scratch);

62041

- }

62042

+ rs6000_secondary_reload_trace (__LINE__, reg, mem, scratch, store_p);

62043

62044

- gcc_assert (regno >= 0 && regno < FIRST_PSEUDO_REGISTER);

62045

- gcc_assert (GET_CODE (mem) == MEM);

62046

+ if (regno < 0 || regno >= FIRST_PSEUDO_REGISTER)

62047

+ rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);

62048

+

62049

+ if (GET_CODE (mem) != MEM)

62050

+ rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);

62051

+

62052

rclass = REGNO_REG_CLASS (regno);

62053

- addr = XEXP (mem, 0);

62054

+ addr = find_replacement (&XEXP (mem, 0));

62055

62056

switch (rclass)

62057

{

62058

@@ -13988,25 +16707,31 @@

62059

if (GET_CODE (addr) == AND)

62060

{

62061

and_op2 = XEXP (addr, 1);

62062

- addr = XEXP (addr, 0);

62063

+ addr = find_replacement (&XEXP (addr, 0));

62064

}

62065

62066

if (GET_CODE (addr) == PRE_MODIFY)

62067

{

62068

- scratch_or_premodify = XEXP (addr, 0);

62069

- gcc_assert (REG_P (scratch_or_premodify));

62070

- gcc_assert (GET_CODE (XEXP (addr, 1)) == PLUS);

62071

- addr = XEXP (addr, 1);

62072

+ scratch_or_premodify = find_replacement (&XEXP (addr, 0));

62073

+ if (!REG_P (scratch_or_premodify))

62074

+ rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);

62075

+

62076

+ addr = find_replacement (&XEXP (addr, 1));

62077

+ if (GET_CODE (addr) != PLUS)

62078

+ rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);

62079

}

62080

62081

if (GET_CODE (addr) == PLUS

62082

&& (and_op2 != NULL_RTX

62083

- || !rs6000_legitimate_offset_address_p (TImode, addr,

62084

+ || !rs6000_legitimate_offset_address_p (PTImode, addr,

62085

false, true)))

62086

{

62087

+ /* find_replacement already recurses into both operands of

62088

+ PLUS so we don't need to call it here. */

62089

addr_op1 = XEXP (addr, 0);

62090

addr_op2 = XEXP (addr, 1);

62091

- gcc_assert (legitimate_indirect_address_p (addr_op1, false));

62092

+ if (!legitimate_indirect_address_p (addr_op1, false))

62093

+ rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);

62094

62095

if (!REG_P (addr_op2)

62096

&& (GET_CODE (addr_op2) != CONST_INT

62097

@@ -14034,7 +16759,7 @@

62098

scratch_or_premodify = scratch;

62099

}

62100

else if (!legitimate_indirect_address_p (addr, false)

62101

- && !rs6000_legitimate_offset_address_p (TImode, addr,

62102

+ && !rs6000_legitimate_offset_address_p (PTImode, addr,

62103

false, true))

62104

{

62105

if (TARGET_DEBUG_ADDR)

62106

@@ -14050,9 +16775,21 @@

62107

}

62108

break;

62109

62110

- /* Float/Altivec registers can only handle reg+reg addressing. Move

62111

- other addresses into a scratch register. */

62112

+ /* Float registers can do offset+reg addressing for scalar types. */

62113

case FLOAT_REGS:

62114

+ if (legitimate_indirect_address_p (addr, false) /* reg */

62115

+ || legitimate_indexed_address_p (addr, false) /* reg+reg */

62116

+ || ((GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8)

62117

+ && and_op2 == NULL_RTX

62118

+ && scratch_or_premodify == scratch

62119

+ && rs6000_legitimate_offset_address_p (mode, addr, false, false)))

62120

+ break;

62121

+

62122

+ /* If this isn't a legacy floating point load/store, fall through to the

62123

+ VSX defaults. */

62124

+

62125

+ /* VSX/Altivec registers can only handle reg+reg addressing. Move other

62126

+ addresses into a scratch register. */

62127

case VSX_REGS:

62128

case ALTIVEC_REGS:

62129

62130

@@ -14066,35 +16803,35 @@

62131

|| !VECTOR_MEM_ALTIVEC_P (mode)))

62132

{

62133

and_op2 = XEXP (addr, 1);

62134

- addr = XEXP (addr, 0);

62135

+ addr = find_replacement (&XEXP (addr, 0));

62136

}

62137

62138

/* If we aren't using a VSX load, save the PRE_MODIFY register and use it

62139

as the address later. */

62140

if (GET_CODE (addr) == PRE_MODIFY

62141

- && (!VECTOR_MEM_VSX_P (mode)

62142

+ && ((ALTIVEC_OR_VSX_VECTOR_MODE (mode)

62143

+ && (rclass != FLOAT_REGS

62144

+ || (GET_MODE_SIZE (mode) != 4 && GET_MODE_SIZE (mode) != 8)))

62145

|| and_op2 != NULL_RTX

62146

|| !legitimate_indexed_address_p (XEXP (addr, 1), false)))

62147

{

62148

- scratch_or_premodify = XEXP (addr, 0);

62149

- gcc_assert (legitimate_indirect_address_p (scratch_or_premodify,

62150

- false));

62151

- gcc_assert (GET_CODE (XEXP (addr, 1)) == PLUS);

62152

- addr = XEXP (addr, 1);

62153

+ scratch_or_premodify = find_replacement (&XEXP (addr, 0));

62154

+ if (!legitimate_indirect_address_p (scratch_or_premodify, false))

62155

+ rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);

62156

+

62157

+ addr = find_replacement (&XEXP (addr, 1));

62158

+ if (GET_CODE (addr) != PLUS)

62159

+ rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);

62160

}

62161

62162

if (legitimate_indirect_address_p (addr, false) /* reg */

62163

|| legitimate_indexed_address_p (addr, false) /* reg+reg */

62164

- || GET_CODE (addr) == PRE_MODIFY /* VSX pre-modify */

62165

|| (GET_CODE (addr) == AND /* Altivec memory */

62166

+ && rclass == ALTIVEC_REGS

62167

&& GET_CODE (XEXP (addr, 1)) == CONST_INT

62168

&& INTVAL (XEXP (addr, 1)) == -16

62169

- && VECTOR_MEM_ALTIVEC_P (mode))

62170

- || (rclass == FLOAT_REGS /* legacy float mem */

62171

- && GET_MODE_SIZE (mode) == 8

62172

- && and_op2 == NULL_RTX

62173

- && scratch_or_premodify == scratch

62174

- && rs6000_legitimate_offset_address_p (mode, addr, false, false)))

62175

+ && (legitimate_indirect_address_p (XEXP (addr, 0), false)

62176

+ || legitimate_indexed_address_p (XEXP (addr, 0), false))))

62177

;

62178

62179

else if (GET_CODE (addr) == PLUS)

62180

@@ -14101,7 +16838,8 @@

62181

{

62182

addr_op1 = XEXP (addr, 0);

62183

addr_op2 = XEXP (addr, 1);

62184

- gcc_assert (REG_P (addr_op1));

62185

+ if (!REG_P (addr_op1))

62186

+ rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);

62187

62188

if (TARGET_DEBUG_ADDR)

62189

{

62190

@@ -14120,7 +16858,8 @@

62191

}

62192

62193

else if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == CONST

62194

- || GET_CODE (addr) == CONST_INT || REG_P (addr))

62195

+ || GET_CODE (addr) == CONST_INT || GET_CODE (addr) == LO_SUM

62196

+ || REG_P (addr))

62197

{

62198

if (TARGET_DEBUG_ADDR)

62199

{

62200

@@ -14136,12 +16875,12 @@

62201

}

62202

62203

else

62204

- gcc_unreachable ();

62205

+ rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);

62206

62207

break;

62208

62209

default:

62210

- gcc_unreachable ();

62211

+ rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);

62212

}

62213

62214

/* If the original address involved a pre-modify that we couldn't use the VSX

62215

@@ -14188,7 +16927,7 @@

62216

/* Adjust the address if it changed. */

62217

if (addr != XEXP (mem, 0))

62218

{

62219

- mem = change_address (mem, mode, addr);

62220

+ mem = replace_equiv_address_nv (mem, addr);

62221

if (TARGET_DEBUG_ADDR)

62222

fprintf (stderr, "\nrs6000_secondary_reload_inner, mem adjusted.\n");

62223

}

62224

@@ -14253,8 +16992,10 @@

62225

return;

62226

}

62227

62228

-/* Allocate a 64-bit stack slot to be used for copying SDmode

62229

- values through if this function has any SDmode references. */

62230

+/* Allocate a 64-bit stack slot to be used for copying SDmode values through if

62231

+ this function has any SDmode references. If we are on a power7 or later, we

62232

+ don't need the 64-bit stack slot since the LFIWZX and STIFWX instructions

62233

+ can load/store the value. */

62234

62235

static void

62236

rs6000_alloc_sdmode_stack_slot (void)

62237

@@ -14264,7 +17005,14 @@

62238

gimple_stmt_iterator gsi;

62239

62240

gcc_assert (cfun->machine->sdmode_stack_slot == NULL_RTX);

62241

+ /* We use a different approach for dealing with the secondary

62242

+ memory in LRA. */

62243

+ if (ira_use_lra_p)

62244

+ return;

62245

62246

+ if (TARGET_NO_SDMODE_STACK)

62247

+ return;

62248

+

62249

FOR_EACH_BB (bb)

62250

for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi))

62251

{

62252

@@ -14325,8 +17073,7 @@

62253

{

62254

enum machine_mode mode = GET_MODE (x);

62255

62256

- if (VECTOR_UNIT_VSX_P (mode)

62257

- && x == CONST0_RTX (mode) && VSX_REG_CLASS_P (rclass))

62258

+ if (TARGET_VSX && x == CONST0_RTX (mode) && VSX_REG_CLASS_P (rclass))

62259

return rclass;

62260

62261

if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)

62262

@@ -14334,8 +17081,14 @@

62263

&& easy_vector_constant (x, mode))

62264

return ALTIVEC_REGS;

62265

62266

- if (CONSTANT_P (x) && reg_classes_intersect_p (rclass, FLOAT_REGS))

62267

- return NO_REGS;

62268

+ if ((CONSTANT_P (x) || GET_CODE (x) == PLUS))

62269

+ {

62270

+ if (reg_class_subset_p (GENERAL_REGS, rclass))

62271

+ return GENERAL_REGS;

62272

+ if (reg_class_subset_p (BASE_REGS, rclass))

62273

+ return BASE_REGS;

62274

+ return NO_REGS;

62275

+ }

62276

62277

if (GET_MODE_CLASS (mode) == MODE_INT && rclass == NON_SPECIAL_REGS)

62278

return GENERAL_REGS;

62279

@@ -14349,7 +17102,8 @@

62280

if (GET_MODE_SIZE (mode) <= 8)

62281

return FLOAT_REGS;

62282

62283

- if (VECTOR_UNIT_ALTIVEC_P (mode) || VECTOR_MEM_ALTIVEC_P (mode))

62284

+ if (VECTOR_UNIT_ALTIVEC_P (mode) || VECTOR_MEM_ALTIVEC_P (mode)

62285

+ || mode == V1TImode)

62286

return ALTIVEC_REGS;

62287

62288

return rclass;

62289

@@ -14381,60 +17135,45 @@

62290

set and vice versa. */

62291

62292

static bool

62293

-rs6000_secondary_memory_needed (enum reg_class class1,

62294

- enum reg_class class2,

62295

+rs6000_secondary_memory_needed (enum reg_class from_class,

62296

+ enum reg_class to_class,

62297

enum machine_mode mode)

62298

{

62299

- if (class1 == class2)

62300

- return false;

62301

+ enum rs6000_reg_type from_type, to_type;

62302

+ bool altivec_p = ((from_class == ALTIVEC_REGS)

62303

+ || (to_class == ALTIVEC_REGS));

62304

62305

- /* Under VSX, there are 3 register classes that values could be in (VSX_REGS,

62306

- ALTIVEC_REGS, and FLOAT_REGS). We don't need to use memory to copy

62307

- between these classes. But we need memory for other things that can go in

62308

- FLOAT_REGS like SFmode. */

62309

- if (TARGET_VSX

62310

- && (VECTOR_MEM_VSX_P (mode) || VECTOR_UNIT_VSX_P (mode))

62311

- && (class1 == VSX_REGS || class1 == ALTIVEC_REGS

62312

- || class1 == FLOAT_REGS))

62313

- return (class2 != VSX_REGS && class2 != ALTIVEC_REGS

62314

- && class2 != FLOAT_REGS);

62315

+ /* If a simple/direct move is available, we don't need secondary memory */

62316

+ from_type = reg_class_to_reg_type[(int)from_class];

62317

+ to_type = reg_class_to_reg_type[(int)to_class];

62318

62319

- if (class1 == VSX_REGS || class2 == VSX_REGS)

62320

- return true;

62321

+ if (rs6000_secondary_reload_move (to_type, from_type, mode,

62322

+ (secondary_reload_info *)0, altivec_p))

62323

+ return false;

62324

62325

- if (class1 == FLOAT_REGS

62326

- && (!TARGET_MFPGPR || !TARGET_POWERPC64

62327

- || ((mode != DFmode)

62328

- && (mode != DDmode)

62329

- && (mode != DImode))))

62330

+ /* If we have a floating point or vector register class, we need to use

62331

+ memory to transfer the data. */

62332

+ if (IS_FP_VECT_REG_TYPE (from_type) || IS_FP_VECT_REG_TYPE (to_type))

62333

return true;

62334

62335

- if (class2 == FLOAT_REGS

62336

- && (!TARGET_MFPGPR || !TARGET_POWERPC64

62337

- || ((mode != DFmode)

62338

- && (mode != DDmode)

62339

- && (mode != DImode))))

62340

- return true;

62341

-

62342

- if (class1 == ALTIVEC_REGS || class2 == ALTIVEC_REGS)

62343

- return true;

62344

-

62345

return false;

62346

}

62347

62348

/* Debug version of rs6000_secondary_memory_needed. */

62349

static bool

62350

-rs6000_debug_secondary_memory_needed (enum reg_class class1,

62351

- enum reg_class class2,

62352

+rs6000_debug_secondary_memory_needed (enum reg_class from_class,

62353

+ enum reg_class to_class,

62354

enum machine_mode mode)

62355

{

62356

- bool ret = rs6000_secondary_memory_needed (class1, class2, mode);

62357

+ bool ret = rs6000_secondary_memory_needed (from_class, to_class, mode);

62358

62359

fprintf (stderr,

62360

- "rs6000_secondary_memory_needed, return: %s, class1 = %s, "

62361

- "class2 = %s, mode = %s\n",

62362

- ret ? "true" : "false", reg_class_names[class1],

62363

- reg_class_names[class2], GET_MODE_NAME (mode));

62364

+ "rs6000_secondary_memory_needed, return: %s, from_class = %s, "

62365

+ "to_class = %s, mode = %s\n",

62366

+ ret ? "true" : "false",

62367

+ reg_class_names[from_class],

62368

+ reg_class_names[to_class],

62369

+ GET_MODE_NAME (mode));

62370

62371

return ret;

62372

}

62373

@@ -14498,15 +17237,21 @@

62374

/* Constants, memory, and FP registers can go into FP registers. */

62375

if ((regno == -1 || FP_REGNO_P (regno))

62376

&& (rclass == FLOAT_REGS || rclass == NON_SPECIAL_REGS))

62377

- return (mode != SDmode) ? NO_REGS : GENERAL_REGS;

62378

+ return (mode != SDmode || lra_in_progress) ? NO_REGS : GENERAL_REGS;

62379

62380

/* Memory, and FP/altivec registers can go into fp/altivec registers under

62381

- VSX. */

62382

+ VSX. However, for scalar variables, use the traditional floating point

62383

+ registers so that we can use offset+register addressing. */

62384

if (TARGET_VSX

62385

&& (regno == -1 || VSX_REGNO_P (regno))

62386

&& VSX_REG_CLASS_P (rclass))

62387

- return NO_REGS;

62388

+ {

62389

+ if (GET_MODE_SIZE (mode) < 16)

62390

+ return FLOAT_REGS;

62391

62392

+ return NO_REGS;

62393

+ }

62394

+

62395

/* Memory, and AltiVec registers can go into AltiVec registers. */

62396

if ((regno == -1 || ALTIVEC_REGNO_P (regno))

62397

&& rclass == ALTIVEC_REGS)

62398

@@ -14550,8 +17295,42 @@

62399

if (from_size != to_size)

62400

{

62401

enum reg_class xclass = (TARGET_VSX) ? VSX_REGS : FLOAT_REGS;

62402

- return ((from_size < 8 || to_size < 8 || TARGET_IEEEQUAD)

62403

- && reg_classes_intersect_p (xclass, rclass));

62404

+

62405

+ if (reg_classes_intersect_p (xclass, rclass))

62406

+ {

62407

+ unsigned to_nregs = hard_regno_nregs[FIRST_FPR_REGNO][to];

62408

+ unsigned from_nregs = hard_regno_nregs[FIRST_FPR_REGNO][from];

62409

+

62410

+ /* Don't allow 64-bit types to overlap with 128-bit types that take a

62411

+ single register under VSX because the scalar part of the register

62412

+ is in the upper 64-bits, and not the lower 64-bits. Types like

62413

+ TFmode/TDmode that take 2 scalar register can overlap. 128-bit

62414

+ IEEE floating point can't overlap, and neither can small

62415

+ values. */

62416

+

62417

+ if (TARGET_IEEEQUAD && (to == TFmode || from == TFmode))

62418

+ return true;

62419

+

62420

+ /* TDmode in floating-mode registers must always go into a register

62421

+ pair with the most significant word in the even-numbered register

62422

+ to match ISA requirements. In little-endian mode, this does not

62423

+ match subreg numbering, so we cannot allow subregs. */

62424

+ if (!BYTES_BIG_ENDIAN && (to == TDmode || from == TDmode))

62425

+ return true;

62426

+

62427

+ if (from_size < 8 || to_size < 8)

62428

+ return true;

62429

+

62430

+ if (from_size == 8 && (8 * to_nregs) != to_size)

62431

+ return true;

62432

+

62433

+ if (to_size == 8 && (8 * from_nregs) != from_size)

62434

+ return true;

62435

+

62436

+ return false;

62437

+ }

62438

+ else

62439

+ return false;

62440

}

62441

62442

if (TARGET_E500_DOUBLE

62443

@@ -14565,10 +17344,19 @@

62444

/* Since the VSX register set includes traditional floating point registers

62445

and altivec registers, just check for the size being different instead of

62446

trying to check whether the modes are vector modes. Otherwise it won't

62447

- allow say DF and DI to change classes. */

62448

+ allow say DF and DI to change classes. For types like TFmode and TDmode

62449

+ that take 2 64-bit registers, rather than a single 128-bit register, don't

62450

+ allow subregs of those types to other 128 bit types. */

62451

if (TARGET_VSX && VSX_REG_CLASS_P (rclass))

62452

- return (from_size != 8 && from_size != 16);

62453

+ {

62454

+ unsigned num_regs = (from_size + 15) / 16;

62455

+ if (hard_regno_nregs[FIRST_FPR_REGNO][to] > num_regs

62456

+ || hard_regno_nregs[FIRST_FPR_REGNO][from] > num_regs)

62457

+ return true;

62458

62459

+ return (from_size != 8 && from_size != 16);

62460

+ }

62461

+

62462

if (TARGET_ALTIVEC && rclass == ALTIVEC_REGS

62463

&& (ALTIVEC_VECTOR_MODE (from) + ALTIVEC_VECTOR_MODE (to)) == 1)

62464

return true;

62465

@@ -14598,6 +17386,186 @@

62466

return ret;

62467

}

62468

62469

+/* Return a string to do a move operation of 128 bits of data. */

62470

+

62471

+const char *

62472

+rs6000_output_move_128bit (rtx operands[])

62473

+{

62474

+ rtx dest = operands[0];

62475

+ rtx src = operands[1];

62476

+ enum machine_mode mode = GET_MODE (dest);

62477

+ int dest_regno;

62478

+ int src_regno;

62479

+ bool dest_gpr_p, dest_fp_p, dest_vmx_p, dest_vsx_p;

62480

+ bool src_gpr_p, src_fp_p, src_vmx_p, src_vsx_p;

62481

+

62482

+ if (REG_P (dest))

62483

+ {

62484

+ dest_regno = REGNO (dest);

62485

+ dest_gpr_p = INT_REGNO_P (dest_regno);

62486

+ dest_fp_p = FP_REGNO_P (dest_regno);

62487

+ dest_vmx_p = ALTIVEC_REGNO_P (dest_regno);

62488

+ dest_vsx_p = dest_fp_p | dest_vmx_p;

62489

+ }

62490

+ else

62491

+ {

62492

+ dest_regno = -1;

62493

+ dest_gpr_p = dest_fp_p = dest_vmx_p = dest_vsx_p = false;

62494

+ }

62495

+

62496

+ if (REG_P (src))

62497

+ {

62498

+ src_regno = REGNO (src);

62499

+ src_gpr_p = INT_REGNO_P (src_regno);

62500

+ src_fp_p = FP_REGNO_P (src_regno);

62501

+ src_vmx_p = ALTIVEC_REGNO_P (src_regno);

62502

+ src_vsx_p = src_fp_p | src_vmx_p;

62503

+ }

62504

+ else

62505

+ {

62506

+ src_regno = -1;

62507

+ src_gpr_p = src_fp_p = src_vmx_p = src_vsx_p = false;

62508

+ }

62509

+

62510

+ /* Register moves. */

62511

+ if (dest_regno >= 0 && src_regno >= 0)

62512

+ {

62513

+ if (dest_gpr_p)

62514

+ {

62515

+ if (src_gpr_p)

62516

+ return "#";

62517

+

62518

+ else if (TARGET_VSX && TARGET_DIRECT_MOVE && src_vsx_p)

62519

+ return "#";

62520

+ }

62521

+

62522

+ else if (TARGET_VSX && dest_vsx_p)

62523

+ {

62524

+ if (src_vsx_p)

62525

+ return "xxlor %x0,%x1,%x1";

62526

+

62527

+ else if (TARGET_DIRECT_MOVE && src_gpr_p)

62528

+ return "#";

62529

+ }

62530

+

62531

+ else if (TARGET_ALTIVEC && dest_vmx_p && src_vmx_p)

62532

+ return "vor %0,%1,%1";

62533

+

62534

+ else if (dest_fp_p && src_fp_p)

62535

+ return "#";

62536

+ }

62537

+

62538

+ /* Loads. */

62539

+ else if (dest_regno >= 0 && MEM_P (src))

62540

+ {

62541

+ if (dest_gpr_p)

62542

+ {

62543

+ if (TARGET_QUAD_MEMORY && quad_load_store_p (dest, src))

62544

+ return "lq %0,%1";

62545

+ else

62546

+ return "#";

62547

+ }

62548

+

62549

+ else if (TARGET_ALTIVEC && dest_vmx_p

62550

+ && altivec_indexed_or_indirect_operand (src, mode))

62551

+ return "lvx %0,%y1";

62552

+

62553

+ else if (TARGET_VSX && dest_vsx_p)

62554

+ {

62555

+ if (mode == V16QImode || mode == V8HImode || mode == V4SImode)

62556

+ return "lxvw4x %x0,%y1";

62557

+ else

62558

+ return "lxvd2x %x0,%y1";

62559

+ }

62560

+

62561

+ else if (TARGET_ALTIVEC && dest_vmx_p)

62562

+ return "lvx %0,%y1";

62563

+

62564

+ else if (dest_fp_p)

62565

+ return "#";

62566

+ }

62567

+

62568

+ /* Stores. */

62569

+ else if (src_regno >= 0 && MEM_P (dest))

62570

+ {

62571

+ if (src_gpr_p)

62572

+ {

62573

+ if (TARGET_QUAD_MEMORY && quad_load_store_p (dest, src))

62574

+ return "stq %1,%0";

62575

+ else

62576

+ return "#";

62577

+ }

62578

+

62579

+ else if (TARGET_ALTIVEC && src_vmx_p

62580

+ && altivec_indexed_or_indirect_operand (src, mode))

62581

+ return "stvx %1,%y0";

62582

+

62583

+ else if (TARGET_VSX && src_vsx_p)

62584

+ {

62585

+ if (mode == V16QImode || mode == V8HImode || mode == V4SImode)

62586

+ return "stxvw4x %x1,%y0";

62587

+ else

62588

+ return "stxvd2x %x1,%y0";

62589

+ }

62590

+

62591

+ else if (TARGET_ALTIVEC && src_vmx_p)

62592

+ return "stvx %1,%y0";

62593

+

62594

+ else if (src_fp_p)

62595

+ return "#";

62596

+ }

62597

+

62598

+ /* Constants. */

62599

+ else if (dest_regno >= 0

62600

+ && (GET_CODE (src) == CONST_INT

62601

+ || GET_CODE (src) == CONST_DOUBLE

62602

+ || GET_CODE (src) == CONST_VECTOR))

62603

+ {

62604

+ if (dest_gpr_p)

62605

+ return "#";

62606

+

62607

+ else if (TARGET_VSX && dest_vsx_p && zero_constant (src, mode))

62608

+ return "xxlxor %x0,%x0,%x0";

62609

+

62610

+ else if (TARGET_ALTIVEC && dest_vmx_p)

62611

+ return output_vec_const_move (operands);

62612

+ }

62613

+

62614

+ if (TARGET_DEBUG_ADDR)

62615

+ {

62616

+ fprintf (stderr, "\n===== Bad 128 bit move:\n");

62617

+ debug_rtx (gen_rtx_SET (VOIDmode, dest, src));

62618

+ }

62619

+

62620

+ gcc_unreachable ();

62621

+}

62622

+

62623

+/* Validate a 128-bit move. */

62624

+bool

62625

+rs6000_move_128bit_ok_p (rtx operands[])

62626

+{

62627

+ enum machine_mode mode = GET_MODE (operands[0]);

62628

+ return (gpc_reg_operand (operands[0], mode)

62629

+ || gpc_reg_operand (operands[1], mode));

62630

+}

62631

+

62632

+/* Return true if a 128-bit move needs to be split. */

62633

+bool

62634

+rs6000_split_128bit_ok_p (rtx operands[])

62635

+{

62636

+ if (!reload_completed)

62637

+ return false;

62638

+

62639

+ if (!gpr_or_gpr_p (operands[0], operands[1]))

62640

+ return false;

62641

+

62642

+ if (quad_load_store_p (operands[0], operands[1]))

62643

+ return false;

62644

+

62645

+ return true;

62646

+}

62647

+

62648

+

62649

/* Given a comparison operation, return the bit number in CCR to test. We

62650

know this is a valid comparison.

62651

62652

@@ -14823,6 +17791,7 @@

62653

ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");

62654

break;

62655

62656

+ case ABI_ELFv2:

62657

case ABI_V4:

62658

case ABI_DARWIN:

62659

break;

62660

@@ -15302,7 +18271,7 @@

62661

return;

62662

62663

case 'Y':

62664

- /* Like 'L', for third word of TImode */

62665

+ /* Like 'L', for third word of TImode/PTImode */

62666

if (REG_P (x))

62667

fputs (reg_names[REGNO (x) + 2], file);

62668

else if (MEM_P (x))

62669

@@ -15352,7 +18321,7 @@

62670

return;

62671

62672

case 'Z':

62673

- /* Like 'L', for last word of TImode. */

62674

+ /* Like 'L', for last word of TImode/PTImode. */

62675

if (REG_P (x))

62676

fputs (reg_names[REGNO (x) + 3], file);

62677

else if (MEM_P (x))

62678

@@ -15383,7 +18352,8 @@

62679

if ((TARGET_SPE || TARGET_E500_DOUBLE)

62680

&& (GET_MODE_SIZE (GET_MODE (x)) == 8

62681

|| GET_MODE (x) == TFmode

62682

- || GET_MODE (x) == TImode))

62683

+ || GET_MODE (x) == TImode

62684

+ || GET_MODE (x) == PTImode))

62685

{

62686

/* Handle [reg]. */

62687

if (REG_P (tmp))

62688

@@ -16766,7 +19736,8 @@

62689

}

62690

62691

/* A subroutine of the atomic operation splitters. Emit a load-locked

62692

- instruction in MODE. */

62693

+ instruction in MODE. For QI/HImode, possibly use a pattern than includes

62694

+ the zero_extend operation. */

62695

62696

static void

62697

emit_load_locked (enum machine_mode mode, rtx reg, rtx mem)

62698

@@ -16775,12 +19746,26 @@

62699

62700

switch (mode)

62701

{

62702

+ case QImode:

62703

+ fn = gen_load_lockedqi;

62704

+ break;

62705

+ case HImode:

62706

+ fn = gen_load_lockedhi;

62707

+ break;

62708

case SImode:

62709

- fn = gen_load_lockedsi;

62710

+ if (GET_MODE (mem) == QImode)

62711

+ fn = gen_load_lockedqi_si;

62712

+ else if (GET_MODE (mem) == HImode)

62713

+ fn = gen_load_lockedhi_si;

62714

+ else

62715

+ fn = gen_load_lockedsi;

62716

break;

62717

case DImode:

62718

fn = gen_load_lockeddi;

62719

break;

62720

+ case TImode:

62721

+ fn = gen_load_lockedti;

62722

+ break;

62723

default:

62724

gcc_unreachable ();

62725

}

62726

@@ -16797,6 +19782,12 @@

62727

62728

switch (mode)

62729

{

62730

+ case QImode:

62731

+ fn = gen_store_conditionalqi;

62732

+ break;

62733

+ case HImode:

62734

+ fn = gen_store_conditionalhi;

62735

+ break;

62736

case SImode:

62737

fn = gen_store_conditionalsi;

62738

break;

62739

@@ -16803,6 +19794,9 @@

62740

case DImode:

62741

fn = gen_store_conditionaldi;

62742

break;

62743

+ case TImode:

62744

+ fn = gen_store_conditionalti;

62745

+ break;

62746

default:

62747

gcc_unreachable ();

62748

}

62749

@@ -16949,7 +19943,7 @@

62750

{

62751

rtx boolval, retval, mem, oldval, newval, cond;

62752

rtx label1, label2, x, mask, shift;

62753

- enum machine_mode mode;

62754

+ enum machine_mode mode, orig_mode;

62755

enum memmodel mod_s, mod_f;

62756

bool is_weak;

62757

62758

@@ -16961,23 +19955,30 @@

62759

is_weak = (INTVAL (operands[5]) != 0);

62760

mod_s = (enum memmodel) INTVAL (operands[6]);

62761

mod_f = (enum memmodel) INTVAL (operands[7]);

62762

- mode = GET_MODE (mem);

62763

+ orig_mode = mode = GET_MODE (mem);

62764

62765

mask = shift = NULL_RTX;

62766

if (mode == QImode || mode == HImode)

62767

{

62768

- mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);

62769

-

62770

- /* Shift and mask OLDVAL into position with the word. */

62771

+ /* Before power8, we didn't have access to lbarx/lharx, so generate a

62772

+ lwarx and shift/mask operations. With power8, we need to do the

62773

+ comparison in SImode, but the store is still done in QI/HImode. */

62774

oldval = convert_modes (SImode, mode, oldval, 1);

62775

- oldval = expand_simple_binop (SImode, ASHIFT, oldval, shift,

62776

- NULL_RTX, 1, OPTAB_LIB_WIDEN);

62777

62778

- /* Shift and mask NEWVAL into position within the word. */

62779

- newval = convert_modes (SImode, mode, newval, 1);

62780

- newval = expand_simple_binop (SImode, ASHIFT, newval, shift,

62781

- NULL_RTX, 1, OPTAB_LIB_WIDEN);

62782

+ if (!TARGET_SYNC_HI_QI)

62783

+ {

62784

+ mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);

62785

62786

+ /* Shift and mask OLDVAL into position with the word. */

62787

+ oldval = expand_simple_binop (SImode, ASHIFT, oldval, shift,

62788

+ NULL_RTX, 1, OPTAB_LIB_WIDEN);

62789

+

62790

+ /* Shift and mask NEWVAL into position within the word. */

62791

+ newval = convert_modes (SImode, mode, newval, 1);

62792

+ newval = expand_simple_binop (SImode, ASHIFT, newval, shift,

62793

+ NULL_RTX, 1, OPTAB_LIB_WIDEN);

62794

+ }

62795

+

62796

/* Prepare to adjust the return value. */

62797

retval = gen_reg_rtx (SImode);

62798

mode = SImode;

62799

@@ -17005,7 +20006,25 @@

62800

}

62801

62802

cond = gen_reg_rtx (CCmode);

62803

- x = gen_rtx_COMPARE (CCmode, x, oldval);

62804

+ /* If we have TImode, synthesize a comparison. */

62805

+ if (mode != TImode)

62806

+ x = gen_rtx_COMPARE (CCmode, x, oldval);

62807

+ else

62808

+ {

62809

+ rtx xor1_result = gen_reg_rtx (DImode);

62810

+ rtx xor2_result = gen_reg_rtx (DImode);

62811

+ rtx or_result = gen_reg_rtx (DImode);

62812

+ rtx new_word0 = simplify_gen_subreg (DImode, x, TImode, 0);

62813

+ rtx new_word1 = simplify_gen_subreg (DImode, x, TImode, 8);

62814

+ rtx old_word0 = simplify_gen_subreg (DImode, oldval, TImode, 0);

62815

+ rtx old_word1 = simplify_gen_subreg (DImode, oldval, TImode, 8);

62816

+

62817

+ emit_insn (gen_xordi3 (xor1_result, new_word0, old_word0));

62818

+ emit_insn (gen_xordi3 (xor2_result, new_word1, old_word1));

62819

+ emit_insn (gen_iordi3 (or_result, xor1_result, xor2_result));

62820

+ x = gen_rtx_COMPARE (CCmode, or_result, const0_rtx);

62821

+ }

62822

+

62823

emit_insn (gen_rtx_SET (VOIDmode, cond, x));

62824

62825

x = gen_rtx_NE (VOIDmode, cond, const0_rtx);

62826

@@ -17015,7 +20034,7 @@

62827

if (mask)

62828

x = rs6000_mask_atomic_subword (retval, newval, mask);

62829

62830

- emit_store_conditional (mode, cond, mem, x);

62831

+ emit_store_conditional (orig_mode, cond, mem, x);

62832

62833

if (!is_weak)

62834

{

62835

@@ -17033,6 +20052,8 @@

62836

62837

if (shift)

62838

rs6000_finish_atomic_subword (operands[1], retval, shift);

62839

+ else if (mode != GET_MODE (operands[1]))

62840

+ convert_move (operands[1], retval, 1);

62841

62842

/* In all cases, CR0 contains EQ on success, and NE on failure. */

62843

x = gen_rtx_EQ (SImode, cond, const0_rtx);

62844

@@ -17056,7 +20077,7 @@

62845

mode = GET_MODE (mem);

62846

62847

mask = shift = NULL_RTX;

62848

- if (mode == QImode || mode == HImode)

62849

+ if (!TARGET_SYNC_HI_QI && (mode == QImode || mode == HImode))

62850

{

62851

mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);

62852

62853

@@ -17105,53 +20126,70 @@

62854

{

62855

enum memmodel model = (enum memmodel) INTVAL (model_rtx);

62856

enum machine_mode mode = GET_MODE (mem);

62857

+ enum machine_mode store_mode = mode;

62858

rtx label, x, cond, mask, shift;

62859

rtx before = orig_before, after = orig_after;

62860

62861

mask = shift = NULL_RTX;

62862

+ /* On power8, we want to use SImode for the operation. On previous systems,

62863

+ use the operation in a subword and shift/mask to get the proper byte or

62864

+ halfword. */

62865

if (mode == QImode || mode == HImode)

62866

{

62867

- mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);

62868

+ if (TARGET_SYNC_HI_QI)

62869

+ {

62870

+ val = convert_modes (SImode, mode, val, 1);

62871

62872

- /* Shift and mask VAL into position with the word. */

62873

- val = convert_modes (SImode, mode, val, 1);

62874

- val = expand_simple_binop (SImode, ASHIFT, val, shift,

62875

- NULL_RTX, 1, OPTAB_LIB_WIDEN);

62876

-

62877

- switch (code)

62878

+ /* Prepare to adjust the return value. */

62879

+ before = gen_reg_rtx (SImode);

62880

+ if (after)

62881

+ after = gen_reg_rtx (SImode);

62882

+ mode = SImode;

62883

+ }

62884

+ else

62885

{

62886

- case IOR:

62887

- case XOR:

62888

- /* We've already zero-extended VAL. That is sufficient to

62889

- make certain that it does not affect other bits. */

62890

- mask = NULL;

62891

- break;

62892

+ mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);

62893

62894

- case AND:

62895

- /* If we make certain that all of the other bits in VAL are

62896

- set, that will be sufficient to not affect other bits. */

62897

- x = gen_rtx_NOT (SImode, mask);

62898

- x = gen_rtx_IOR (SImode, x, val);

62899

- emit_insn (gen_rtx_SET (VOIDmode, val, x));

62900

- mask = NULL;

62901

- break;

62902

+ /* Shift and mask VAL into position with the word. */

62903

+ val = convert_modes (SImode, mode, val, 1);

62904

+ val = expand_simple_binop (SImode, ASHIFT, val, shift,

62905

+ NULL_RTX, 1, OPTAB_LIB_WIDEN);

62906

62907

- case NOT:

62908

- case PLUS:

62909

- case MINUS:

62910

- /* These will all affect bits outside the field and need

62911

- adjustment via MASK within the loop. */

62912

- break;

62913

+ switch (code)

62914

+ {

62915

+ case IOR:

62916

+ case XOR:

62917

+ /* We've already zero-extended VAL. That is sufficient to

62918

+ make certain that it does not affect other bits. */

62919

+ mask = NULL;

62920

+ break;

62921

62922

- default:

62923

- gcc_unreachable ();

62924

+ case AND:

62925

+ /* If we make certain that all of the other bits in VAL are

62926

+ set, that will be sufficient to not affect other bits. */

62927

+ x = gen_rtx_NOT (SImode, mask);

62928

+ x = gen_rtx_IOR (SImode, x, val);

62929

+ emit_insn (gen_rtx_SET (VOIDmode, val, x));

62930

+ mask = NULL;

62931

+ break;

62932

+

62933

+ case NOT:

62934

+ case PLUS:

62935

+ case MINUS:

62936

+ /* These will all affect bits outside the field and need

62937

+ adjustment via MASK within the loop. */

62938

+ break;

62939

+

62940

+ default:

62941

+ gcc_unreachable ();

62942

+ }

62943

+

62944

+ /* Prepare to adjust the return value. */

62945

+ before = gen_reg_rtx (SImode);

62946

+ if (after)

62947

+ after = gen_reg_rtx (SImode);

62948

+ store_mode = mode = SImode;

62949

}

62950

-

62951

- /* Prepare to adjust the return value. */

62952

- before = gen_reg_rtx (SImode);

62953

- if (after)

62954

- after = gen_reg_rtx (SImode);

62955

- mode = SImode;

62956

}

62957

62958

mem = rs6000_pre_atomic_barrier (mem, model);

62959

@@ -17184,9 +20222,11 @@

62960

NULL_RTX, 1, OPTAB_LIB_WIDEN);

62961

x = rs6000_mask_atomic_subword (before, x, mask);

62962

}

62963

+ else if (store_mode != mode)

62964

+ x = convert_modes (store_mode, mode, x, 1);

62965

62966

cond = gen_reg_rtx (CCmode);

62967

- emit_store_conditional (mode, cond, mem, x);

62968

+ emit_store_conditional (store_mode, cond, mem, x);

62969

62970

x = gen_rtx_NE (VOIDmode, cond, const0_rtx);

62971

emit_unlikely_jump (x, label);

62972

@@ -17195,11 +20235,22 @@

62973

62974

if (shift)

62975

{

62976

+ /* QImode/HImode on machines without lbarx/lharx where we do a lwarx and

62977

+ then do the calcuations in a SImode register. */

62978

if (orig_before)

62979

rs6000_finish_atomic_subword (orig_before, before, shift);

62980

if (orig_after)

62981

rs6000_finish_atomic_subword (orig_after, after, shift);

62982

}

62983

+ else if (store_mode != mode)

62984

+ {

62985

+ /* QImode/HImode on machines with lbarx/lharx where we do the native

62986

+ operation and then do the calcuations in a SImode register. */

62987

+ if (orig_before)

62988

+ convert_move (orig_before, before, 1);

62989

+ if (orig_after)

62990

+ convert_move (orig_after, after, 1);

62991

+ }

62992

else if (orig_after && after != orig_after)

62993

emit_move_insn (orig_after, after);

62994

}

62995

@@ -17239,6 +20290,39 @@

62996

62997

gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));

62998

62999

+ /* TDmode residing in FP registers is special, since the ISA requires that

63000

+ the lower-numbered word of a register pair is always the most significant

63001

+ word, even in little-endian mode. This does not match the usual subreg

63002

+ semantics, so we cannnot use simplify_gen_subreg in those cases. Access

63003

+ the appropriate constituent registers "by hand" in little-endian mode.

63004

+

63005

+ Note we do not need to check for destructive overlap here since TDmode

63006

+ can only reside in even/odd register pairs. */

63007

+ if (FP_REGNO_P (reg) && DECIMAL_FLOAT_MODE_P (mode) && !BYTES_BIG_ENDIAN)

63008

+ {

63009

+ rtx p_src, p_dst;

63010

+ int i;

63011

+

63012

+ for (i = 0; i < nregs; i++)

63013

+ {

63014

+ if (REG_P (src) && FP_REGNO_P (REGNO (src)))

63015

+ p_src = gen_rtx_REG (reg_mode, REGNO (src) + nregs - 1 - i);

63016

+ else

63017

+ p_src = simplify_gen_subreg (reg_mode, src, mode,

63018

+ i * reg_mode_size);

63019

+

63020

+ if (REG_P (dst) && FP_REGNO_P (REGNO (dst)))

63021

+ p_dst = gen_rtx_REG (reg_mode, REGNO (dst) + nregs - 1 - i);

63022

+ else

63023

+ p_dst = simplify_gen_subreg (reg_mode, dst, mode,

63024

+ i * reg_mode_size);

63025

+

63026

+ emit_insn (gen_rtx_SET (VOIDmode, p_dst, p_src));

63027

+ }

63028

+

63029

+ return;

63030

+ }

63031

+

63032

if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))

63033

{

63034

/* Move register range backwards, if we might have destructive

63035

@@ -17693,7 +20777,7 @@

63036

}

63037

else

63038

{

63039

- gcc_checking_assert (DEFAULT_ABI == ABI_AIX);

63040

+ gcc_checking_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);

63041

if (info->first_fp_reg_save > 61)

63042

strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;

63043

strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;

63044

@@ -17704,7 +20788,8 @@

63045

by the static chain. It would require too much fiddling and the

63046

static chain is rarely used anyway. FPRs are saved w.r.t the stack

63047

pointer on Darwin, and AIX uses r1 or r12. */

63048

- if (using_static_chain_p && DEFAULT_ABI != ABI_AIX)

63049

+ if (using_static_chain_p

63050

+ && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN))

63051

strategy |= ((DEFAULT_ABI == ABI_DARWIN ? 0 : SAVE_INLINE_FPRS)

63052

| SAVE_INLINE_GPRS

63053

| SAVE_INLINE_VRS | REST_INLINE_VRS);

63054

@@ -17837,7 +20922,35 @@

63055

The required alignment for AIX configurations is two words (i.e., 8

63056

or 16 bytes).

63057

63058

+ The ELFv2 ABI is a variant of the AIX ABI. Stack frames look like:

63059

63060

+ SP----> +---------------------------------------+

63061

+ | Back chain to caller | 0

63062

+ +---------------------------------------+

63063

+ | Save area for CR | 8

63064

+ +---------------------------------------+

63065

+ | Saved LR | 16

63066

+ +---------------------------------------+

63067

+ | Saved TOC pointer | 24

63068

+ +---------------------------------------+

63069

+ | Parameter save area (P) | 32

63070

+ +---------------------------------------+

63071

+ | Alloca space (A) | 32+P

63072

+ +---------------------------------------+

63073

+ | Local variable space (L) | 32+P+A

63074

+ +---------------------------------------+

63075

+ | Save area for AltiVec registers (W) | 32+P+A+L

63076

+ +---------------------------------------+

63077

+ | AltiVec alignment padding (Y) | 32+P+A+L+W

63078

+ +---------------------------------------+

63079

+ | Save area for GP registers (G) | 32+P+A+L+W+Y

63080

+ +---------------------------------------+

63081

+ | Save area for FP registers (F) | 32+P+A+L+W+Y+G

63082

+ +---------------------------------------+

63083

+ old SP->| back chain to caller's caller | 32+P+A+L+W+Y+G+F

63084

+ +---------------------------------------+

63085

+

63086

+

63087

V.4 stack frames look like:

63088

63089

SP----> +---------------------------------------+

63090

@@ -17897,6 +21010,7 @@

63091

rs6000_stack_t *info_ptr = &stack_info;

63092

int reg_size = TARGET_32BIT ? 4 : 8;

63093

int ehrd_size;

63094

+ int ehcr_size;

63095

int save_align;

63096

int first_gp;

63097

HOST_WIDE_INT non_fixed_size;

63098

@@ -17990,6 +21104,18 @@

63099

else

63100

ehrd_size = 0;

63101

63102

+ /* In the ELFv2 ABI, we also need to allocate space for separate

63103

+ CR field save areas if the function calls __builtin_eh_return. */

63104

+ if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)

63105

+ {

63106

+ /* This hard-codes that we have three call-saved CR fields. */

63107

+ ehcr_size = 3 * reg_size;

63108

+ /* We do *not* use the regular CR save mechanism. */

63109

+ info_ptr->cr_save_p = 0;

63110

+ }

63111

+ else

63112

+ ehcr_size = 0;

63113

+

63114

/* Determine various sizes. */

63115

info_ptr->reg_size = reg_size;

63116

info_ptr->fixed_size = RS6000_SAVE_AREA;

63117

@@ -18029,6 +21155,7 @@

63118

gcc_unreachable ();

63119

63120

case ABI_AIX:

63121

+ case ABI_ELFv2:

63122

case ABI_DARWIN:

63123

info_ptr->fp_save_offset = - info_ptr->fp_size;

63124

info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;

63125

@@ -18058,6 +21185,8 @@

63126

}

63127

else

63128

info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;

63129

+

63130

+ info_ptr->ehcr_offset = info_ptr->ehrd_offset - ehcr_size;

63131

info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */

63132

info_ptr->lr_save_offset = 2*reg_size;

63133

break;

63134

@@ -18120,6 +21249,7 @@

63135

+ info_ptr->spe_gp_size

63136

+ info_ptr->spe_padding_size

63137

+ ehrd_size

63138

+ + ehcr_size

63139

+ info_ptr->cr_size

63140

+ info_ptr->vrsave_size,

63141

save_align);

63142

@@ -18133,7 +21263,7 @@

63143

63144

/* Determine if we need to save the link register. */

63145

if (info_ptr->calls_p

63146

- || (DEFAULT_ABI == ABI_AIX

63147

+ || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)

63148

&& crtl->profile

63149

&& !TARGET_PROFILE_KERNEL)

63150

|| (DEFAULT_ABI == ABI_V4 && cfun->calls_alloca)

63151

@@ -18279,6 +21409,7 @@

63152

default: abi_string = "Unknown"; break;

63153

case ABI_NONE: abi_string = "NONE"; break;

63154

case ABI_AIX: abi_string = "AIX"; break;

63155

+ case ABI_ELFv2: abi_string = "ELFv2"; break;

63156

case ABI_DARWIN: abi_string = "Darwin"; break;

63157

case ABI_V4: abi_string = "V.4"; break;

63158

}

63159

@@ -18400,7 +21531,8 @@

63160

/* Currently we don't optimize very well between prolog and body

63161

code and for PIC code the code can be actually quite bad, so

63162

don't try to be too clever here. */

63163

- if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))

63164

+ if (count != 0

63165

+ || ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN) && flag_pic))

63166

{

63167

cfun->machine->ra_needs_full_frame = 1;

63168

63169

@@ -18459,13 +21591,13 @@

63170

return false;

63171

}

63172

63173

- /* Under the AIX ABI we can't allow calls to non-local functions,

63174

- because the callee may have a different TOC pointer to the

63175

- caller and there's no way to ensure we restore the TOC when we

63176

- return. With the secure-plt SYSV ABI we can't make non-local

63177

+ /* Under the AIX or ELFv2 ABIs we can't allow calls to non-local

63178

+ functions, because the callee may have a different TOC pointer to

63179

+ the caller and there's no way to ensure we restore the TOC when

63180

+ we return. With the secure-plt SYSV ABI we can't make non-local

63181

calls when -fpic/PIC because the plt call stubs use r30. */

63182

if (DEFAULT_ABI == ABI_DARWIN

63183

- || (DEFAULT_ABI == ABI_AIX

63184

+ || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)

63185

&& decl

63186

&& !DECL_EXTERNAL (decl)

63187

&& (*targetm.binds_local_p) (decl))

63188

@@ -18566,7 +21698,7 @@

63189

rtx dest;

63190

dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);

63191

63192

- if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic)

63193

+ if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic)

63194

{

63195

char buf[30];

63196

rtx lab, tmp1, tmp2, got;

63197

@@ -18594,7 +21726,7 @@

63198

emit_insn (gen_load_toc_v4_pic_si ());

63199

emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));

63200

}

63201

- else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)

63202

+ else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2)

63203

{

63204

char buf[30];

63205

rtx temp0 = (fromprolog

63206

@@ -18642,7 +21774,7 @@

63207

}

63208

else

63209

{

63210

- gcc_assert (DEFAULT_ABI == ABI_AIX);

63211

+ gcc_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);

63212

63213

if (TARGET_32BIT)

63214

emit_insn (gen_load_toc_aix_si (dest));

63215

@@ -19047,7 +22179,7 @@

63216

63217

static rtx

63218

rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,

63219

- rtx reg2, rtx rreg)

63220

+ rtx reg2, rtx rreg, rtx split_reg)

63221

{

63222

rtx real, temp;

63223

63224

@@ -19138,6 +22270,11 @@

63225

}

63226

}

63227

63228

+ /* If a store insn has been split into multiple insns, the

63229

+ true source register is given by split_reg. */

63230

+ if (split_reg != NULL_RTX)

63231

+ real = gen_rtx_SET (VOIDmode, SET_DEST (real), split_reg);

63232

+

63233

RTX_FRAME_RELATED_P (insn) = 1;

63234

add_reg_note (insn, REG_FRAME_RELATED_EXPR, real);

63235

63236

@@ -19245,7 +22382,7 @@

63237

reg = gen_rtx_REG (mode, regno);

63238

insn = emit_insn (gen_frame_store (reg, frame_reg, offset));

63239

return rs6000_frame_related (insn, frame_reg, frame_reg_to_sp,

63240

- NULL_RTX, NULL_RTX);

63241

+ NULL_RTX, NULL_RTX, NULL_RTX);

63242

}

63243

63244

/* Emit an offset memory reference suitable for a frame store, while

63245

@@ -19361,7 +22498,7 @@

63246

if ((sel & SAVRES_LR))

63247

suffix = "_x";

63248

}

63249

- else if (DEFAULT_ABI == ABI_AIX)

63250

+ else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)

63251

{

63252

#if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)

63253

/* No out-of-line save/restore routines for GPRs on AIX. */

63254

@@ -19502,7 +22639,7 @@

63255

static inline unsigned

63256

ptr_regno_for_savres (int sel)

63257

{

63258

- if (DEFAULT_ABI == ABI_AIX)

63259

+ if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)

63260

return (sel & SAVRES_REG) == SAVRES_FPR || (sel & SAVRES_LR) ? 1 : 12;

63261

return DEFAULT_ABI == ABI_DARWIN && (sel & SAVRES_REG) == SAVRES_FPR ? 1 : 11;

63262

}

63263

@@ -19587,6 +22724,43 @@

63264

return insn;

63265

}

63266

63267

+/* Emit code to store CR fields that need to be saved into REG. */

63268

+

63269

+static void

63270

+rs6000_emit_move_from_cr (rtx reg)

63271

+{

63272

+ /* Only the ELFv2 ABI allows storing only selected fields. */

63273

+ if (DEFAULT_ABI == ABI_ELFv2 && TARGET_MFCRF)

63274

+ {

63275

+ int i, cr_reg[8], count = 0;

63276

+

63277

+ /* Collect CR fields that must be saved. */

63278

+ for (i = 0; i < 8; i++)

63279

+ if (save_reg_p (CR0_REGNO + i))

63280

+ cr_reg[count++] = i;

63281

+

63282

+ /* If it's just a single one, use mfcrf. */

63283

+ if (count == 1)

63284

+ {

63285

+ rtvec p = rtvec_alloc (1);

63286

+ rtvec r = rtvec_alloc (2);

63287

+ RTVEC_ELT (r, 0) = gen_rtx_REG (CCmode, CR0_REGNO + cr_reg[0]);

63288

+ RTVEC_ELT (r, 1) = GEN_INT (1 << (7 - cr_reg[0]));

63289

+ RTVEC_ELT (p, 0)

63290

+ = gen_rtx_SET (VOIDmode, reg,

63291

+ gen_rtx_UNSPEC (SImode, r, UNSPEC_MOVESI_FROM_CR));

63292

+

63293

+ emit_insn (gen_rtx_PARALLEL (VOIDmode, p));

63294

+ return;

63295

+ }

63296

+

63297

+ /* ??? It might be better to handle count == 2 / 3 cases here

63298

+ as well, using logical operations to combine the values. */

63299

+ }

63300

+

63301

+ emit_insn (gen_movesi_from_cr (reg));

63302

+}

63303

+

63304

/* Determine whether the gp REG is really used. */

63305

63306

static bool

63307

@@ -19652,6 +22826,17 @@

63308

#define NOT_INUSE(R) do {} while (0)

63309

#endif

63310

63311

+ if (DEFAULT_ABI == ABI_ELFv2)

63312

+ {

63313

+ cfun->machine->r2_setup_needed = df_regs_ever_live_p (TOC_REGNUM);

63314

+

63315

+ /* With -mminimal-toc we may generate an extra use of r2 below. */

63316

+ if (!TARGET_SINGLE_PIC_BASE

63317

+ && TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)

63318

+ cfun->machine->r2_setup_needed = true;

63319

+ }

63320

+

63321

+

63322

if (flag_stack_usage_info)

63323

current_function_static_stack_size = info->total_size;

63324

63325

@@ -19766,7 +22951,7 @@

63326

63327

insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));

63328

rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,

63329

- treg, GEN_INT (-info->total_size));

63330

+ treg, GEN_INT (-info->total_size), NULL_RTX);

63331

sp_off = frame_off = info->total_size;

63332

}

63333

63334

@@ -19851,7 +23036,7 @@

63335

63336

insn = emit_move_insn (mem, reg);

63337

rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,

63338

- NULL_RTX, NULL_RTX);

63339

+ NULL_RTX, NULL_RTX, NULL_RTX);

63340

END_USE (0);

63341

}

63342

}

63343

@@ -19858,7 +23043,7 @@

63344

63345

/* If we need to save CR, put it into r12 or r11. Choose r12 except when

63346

r12 will be needed by out-of-line gpr restore. */

63347

- cr_save_regno = (DEFAULT_ABI == ABI_AIX

63348

+ cr_save_regno = ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)

63349

&& !(strategy & (SAVE_INLINE_GPRS

63350

| SAVE_NOINLINE_GPRS_SAVES_LR))

63351

? 11 : 12);

63352

@@ -19867,21 +23052,9 @@

63353

&& REGNO (frame_reg_rtx) != cr_save_regno

63354

&& !(using_static_chain_p && cr_save_regno == 11))

63355

{

63356

- rtx set;

63357

-

63358

cr_save_rtx = gen_rtx_REG (SImode, cr_save_regno);

63359

START_USE (cr_save_regno);

63360

- insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));

63361

- RTX_FRAME_RELATED_P (insn) = 1;

63362

- /* Now, there's no way that dwarf2out_frame_debug_expr is going

63363

- to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.

63364

- But that's OK. All we have to do is specify that _one_ condition

63365

- code register is saved in this stack slot. The thrower's epilogue

63366

- will then restore all the call-saved registers.

63367

- We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */

63368

- set = gen_rtx_SET (VOIDmode, cr_save_rtx,

63369

- gen_rtx_REG (SImode, CR2_REGNO));

63370

- add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);

63371

+ rs6000_emit_move_from_cr (cr_save_rtx);

63372

}

63373

63374

/* Do any required saving of fpr's. If only one or two to save, do

63375

@@ -19919,7 +23092,7 @@

63376

info->lr_save_offset,

63377

DFmode, sel);

63378

rs6000_frame_related (insn, ptr_reg, sp_off,

63379

- NULL_RTX, NULL_RTX);

63380

+ NULL_RTX, NULL_RTX, NULL_RTX);

63381

if (lr)

63382

END_USE (0);

63383

}

63384

@@ -19998,7 +23171,7 @@

63385

SAVRES_SAVE | SAVRES_GPR);

63386

63387

rs6000_frame_related (insn, spe_save_area_ptr, sp_off - save_off,

63388

- NULL_RTX, NULL_RTX);

63389

+ NULL_RTX, NULL_RTX, NULL_RTX);

63390

}

63391

63392

/* Move the static chain pointer back. */

63393

@@ -20048,7 +23221,7 @@

63394

info->lr_save_offset + ptr_off,

63395

reg_mode, sel);

63396

rs6000_frame_related (insn, ptr_reg, sp_off - ptr_off,

63397

- NULL_RTX, NULL_RTX);

63398

+ NULL_RTX, NULL_RTX, NULL_RTX);

63399

if (lr)

63400

END_USE (0);

63401

}

63402

@@ -20064,7 +23237,7 @@

63403

info->gp_save_offset + frame_off + reg_size * i);

63404

insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));

63405

rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,

63406

- NULL_RTX, NULL_RTX);

63407

+ NULL_RTX, NULL_RTX, NULL_RTX);

63408

}

63409

else if (!WORLD_SAVE_P (info))

63410

{

63411

@@ -20133,7 +23306,8 @@

63412

be updated if we arrived at this function via a plt call or

63413

toc adjusting stub. */

63414

emit_move_insn (tmp_reg_si, gen_rtx_MEM (SImode, tmp_reg));

63415

- toc_restore_insn = TARGET_32BIT ? 0x80410014 : 0xE8410028;

63416

+ toc_restore_insn = ((TARGET_32BIT ? 0x80410000 : 0xE8410000)

63417

+ + RS6000_TOC_SAVE_SLOT);

63418

hi = gen_int_mode (toc_restore_insn & ~0xffff, SImode);

63419

emit_insn (gen_xorsi3 (tmp_reg_si, tmp_reg_si, hi));

63420

compare_result = gen_rtx_REG (CCUNSmode, CR0_REGNO);

63421

@@ -20152,7 +23326,7 @@

63422

LABEL_NUSES (toc_save_done) += 1;

63423

63424

save_insn = emit_frame_save (frame_reg_rtx, reg_mode,

63425

- TOC_REGNUM, frame_off + 5 * reg_size,

63426

+ TOC_REGNUM, frame_off + RS6000_TOC_SAVE_SLOT,

63427

sp_off - frame_off);

63428

63429

emit_label (toc_save_done);

63430

@@ -20192,28 +23366,123 @@

63431

rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,

63432

GEN_INT (info->cr_save_offset + frame_off));

63433

rtx mem = gen_frame_mem (SImode, addr);

63434

- /* See the large comment above about why CR2_REGNO is used. */

63435

- rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);

63436

63437

/* If we didn't copy cr before, do so now using r0. */

63438

if (cr_save_rtx == NULL_RTX)

63439

{

63440

- rtx set;

63441

-

63442

START_USE (0);

63443

cr_save_rtx = gen_rtx_REG (SImode, 0);

63444

- insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));

63445

- RTX_FRAME_RELATED_P (insn) = 1;

63446

- set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);

63447

- add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);

63448

+ rs6000_emit_move_from_cr (cr_save_rtx);

63449

}

63450

- insn = emit_move_insn (mem, cr_save_rtx);

63451

+

63452

+ /* Saving CR requires a two-instruction sequence: one instruction

63453

+ to move the CR to a general-purpose register, and a second

63454

+ instruction that stores the GPR to memory.

63455

+

63456

+ We do not emit any DWARF CFI records for the first of these,

63457

+ because we cannot properly represent the fact that CR is saved in

63458

+ a register. One reason is that we cannot express that multiple

63459

+ CR fields are saved; another reason is that on 64-bit, the size

63460

+ of the CR register in DWARF (4 bytes) differs from the size of

63461

+ a general-purpose register.

63462

+

63463

+ This means if any intervening instruction were to clobber one of

63464

+ the call-saved CR fields, we'd have incorrect CFI. To prevent

63465

+ this from happening, we mark the store to memory as a use of

63466

+ those CR fields, which prevents any such instruction from being

63467

+ scheduled in between the two instructions. */

63468

+ rtx crsave_v[9];

63469

+ int n_crsave = 0;

63470

+ int i;

63471

+

63472

+ crsave_v[n_crsave++] = gen_rtx_SET (VOIDmode, mem, cr_save_rtx);

63473

+ for (i = 0; i < 8; i++)

63474

+ if (save_reg_p (CR0_REGNO + i))

63475

+ crsave_v[n_crsave++]

63476

+ = gen_rtx_USE (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO + i));

63477

+

63478

+ insn = emit_insn (gen_rtx_PARALLEL (VOIDmode,

63479

+ gen_rtvec_v (n_crsave, crsave_v)));

63480

END_USE (REGNO (cr_save_rtx));

63481

63482

- rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,

63483

- NULL_RTX, NULL_RTX);

63484

+ /* Now, there's no way that dwarf2out_frame_debug_expr is going to

63485

+ understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)',

63486

+ so we need to construct a frame expression manually. */

63487

+ RTX_FRAME_RELATED_P (insn) = 1;

63488

+

63489

+ /* Update address to be stack-pointer relative, like

63490

+ rs6000_frame_related would do. */

63491

+ addr = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM),

63492

+ GEN_INT (info->cr_save_offset + sp_off));

63493

+ mem = gen_frame_mem (SImode, addr);

63494

+

63495

+ if (DEFAULT_ABI == ABI_ELFv2)

63496

+ {

63497

+ /* In the ELFv2 ABI we generate separate CFI records for each

63498

+ CR field that was actually saved. They all point to the

63499

+ same 32-bit stack slot. */

63500

+ rtx crframe[8];

63501

+ int n_crframe = 0;

63502

+

63503

+ for (i = 0; i < 8; i++)

63504

+ if (save_reg_p (CR0_REGNO + i))

63505

+ {

63506

+ crframe[n_crframe]

63507

+ = gen_rtx_SET (VOIDmode, mem,

63508

+ gen_rtx_REG (SImode, CR0_REGNO + i));

63509

+

63510

+ RTX_FRAME_RELATED_P (crframe[n_crframe]) = 1;

63511

+ n_crframe++;

63512

+ }

63513

+

63514

+ add_reg_note (insn, REG_FRAME_RELATED_EXPR,

63515

+ gen_rtx_PARALLEL (VOIDmode,

63516

+ gen_rtvec_v (n_crframe, crframe)));

63517

+ }

63518

+ else

63519

+ {

63520

+ /* In other ABIs, by convention, we use a single CR regnum to

63521

+ represent the fact that all call-saved CR fields are saved.

63522

+ We use CR2_REGNO to be compatible with gcc-2.95 on Linux. */

63523

+ rtx set = gen_rtx_SET (VOIDmode, mem,

63524

+ gen_rtx_REG (SImode, CR2_REGNO));

63525

+ add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);

63526

+ }

63527

}

63528

63529

+ /* In the ELFv2 ABI we need to save all call-saved CR fields into

63530

+ *separate* slots if the routine calls __builtin_eh_return, so

63531

+ that they can be independently restored by the unwinder. */

63532

+ if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)

63533

+ {

63534

+ int i, cr_off = info->ehcr_offset;

63535

+ rtx crsave;

63536

+

63537

+ /* ??? We might get better performance by using multiple mfocrf

63538

+ instructions. */

63539

+ crsave = gen_rtx_REG (SImode, 0);

63540

+ emit_insn (gen_movesi_from_cr (crsave));

63541

+

63542

+ for (i = 0; i < 8; i++)

63543

+ if (!call_used_regs[CR0_REGNO + i])

63544

+ {

63545

+ rtvec p = rtvec_alloc (2);

63546

+ RTVEC_ELT (p, 0)

63547

+ = gen_frame_store (crsave, frame_reg_rtx, cr_off + frame_off);

63548

+ RTVEC_ELT (p, 1)

63549

+ = gen_rtx_USE (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO + i));

63550

+

63551

+ insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));

63552

+

63553

+ RTX_FRAME_RELATED_P (insn) = 1;

63554

+ add_reg_note (insn, REG_FRAME_RELATED_EXPR,

63555

+ gen_frame_store (gen_rtx_REG (SImode, CR0_REGNO + i),

63556

+ sp_reg_rtx, cr_off + sp_off));

63557

+

63558

+ cr_off += reg_size;

63559

+ }

63560

+ }

63561

+

63562

/* Update stack and set back pointer unless this is V.4,

63563

for which it was done previously. */

63564

if (!WORLD_SAVE_P (info) && info->push_p

63565

@@ -20291,7 +23560,7 @@

63566

info->altivec_save_offset + ptr_off,

63567

0, V4SImode, SAVRES_SAVE | SAVRES_VR);

63568

rs6000_frame_related (insn, scratch_reg, sp_off - ptr_off,

63569

- NULL_RTX, NULL_RTX);

63570

+ NULL_RTX, NULL_RTX, NULL_RTX);

63571

if (REGNO (frame_reg_rtx) == REGNO (scratch_reg))

63572

{

63573

/* The oddity mentioned above clobbered our frame reg. */

63574

@@ -20307,7 +23576,7 @@

63575

for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)

63576

if (info->vrsave_mask & ALTIVEC_REG_BIT (i))

63577

{

63578

- rtx areg, savereg, mem;

63579

+ rtx areg, savereg, mem, split_reg;

63580

int offset;

63581

63582

offset = (info->altivec_save_offset + frame_off

63583

@@ -20325,8 +23594,18 @@

63584

63585

insn = emit_move_insn (mem, savereg);

63586

63587

+ /* When we split a VSX store into two insns, we need to make

63588

+ sure the DWARF info knows which register we are storing.

63589

+ Pass it in to be used on the appropriate note. */

63590

+ if (!BYTES_BIG_ENDIAN

63591

+ && GET_CODE (PATTERN (insn)) == SET

63592

+ && GET_CODE (SET_SRC (PATTERN (insn))) == VEC_SELECT)

63593

+ split_reg = savereg;

63594

+ else

63595

+ split_reg = NULL_RTX;

63596

+

63597

rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,

63598

- areg, GEN_INT (offset));

63599

+ areg, GEN_INT (offset), split_reg);

63600

}

63601

}

63602

63603

@@ -20350,7 +23629,8 @@

63604

be using r12 as frame_reg_rtx and r11 as the static chain

63605

pointer for nested functions. */

63606

save_regno = 12;

63607

- if (DEFAULT_ABI == ABI_AIX && !using_static_chain_p)

63608

+ if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)

63609

+ && !using_static_chain_p)

63610

save_regno = 11;

63611

else if (REGNO (frame_reg_rtx) == 12)

63612

{

63613

@@ -20389,7 +23669,7 @@

63614

can use register 0. This allows us to use a plain 'blr' to return

63615

from the procedure more often. */

63616

int save_LR_around_toc_setup = (TARGET_ELF

63617

- && DEFAULT_ABI != ABI_AIX

63618

+ && DEFAULT_ABI == ABI_V4

63619

&& flag_pic

63620

&& ! info->lr_save_p

63621

&& EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);

63622

@@ -20451,7 +23731,7 @@

63623

if (rs6000_save_toc_in_prologue_p ())

63624

{

63625

rtx reg = gen_rtx_REG (reg_mode, TOC_REGNUM);

63626

- emit_insn (gen_frame_store (reg, sp_reg_rtx, 5 * reg_size));

63627

+ emit_insn (gen_frame_store (reg, sp_reg_rtx, RS6000_TOC_SAVE_SLOT));

63628

}

63629

}

63630

63631

@@ -20492,6 +23772,49 @@

63632

}

63633

}

63634

63635

+ /* ELFv2 ABI r2 setup code and local entry point. This must follow

63636

+ immediately after the global entry point label. */

63637

+ if (DEFAULT_ABI == ABI_ELFv2 && cfun->machine->r2_setup_needed)

63638

+ {

63639

+ const char *name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);

63640

+

63641

+ fprintf (file, "0:\taddis 2,12,.TOC.-0b@ha\n");

63642

+ fprintf (file, "\taddi 2,2,.TOC.-0b@l\n");

63643

+

63644

+ fputs ("\t.localentry\t", file);

63645

+ assemble_name (file, name);

63646

+ fputs (",.-", file);

63647

+ assemble_name (file, name);

63648

+ fputs ("\n", file);

63649

+ }

63650

+

63651

+ /* Output -mprofile-kernel code. This needs to be done here instead of

63652

+ in output_function_profile since it must go after the ELFv2 ABI

63653

+ local entry point. */

63654

+ if (TARGET_PROFILE_KERNEL)

63655

+ {

63656

+ gcc_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);

63657

+ gcc_assert (!TARGET_32BIT);

63658

+

63659

+ asm_fprintf (file, "\tmflr %s\n", reg_names[0]);

63660

+ asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);

63661

+

63662

+ /* In the ELFv2 ABI we have no compiler stack word. It must be

63663

+ the resposibility of _mcount to preserve the static chain

63664

+ register if required. */

63665

+ if (DEFAULT_ABI != ABI_ELFv2

63666

+ && cfun->static_chain_decl != NULL)

63667

+ {

63668

+ asm_fprintf (file, "\tstd %s,24(%s)\n",

63669

+ reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);

63670

+ fprintf (file, "\tbl %s\n", RS6000_MCOUNT);

63671

+ asm_fprintf (file, "\tld %s,24(%s)\n",

63672

+ reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);

63673

+ }

63674

+ else

63675

+ fprintf (file, "\tbl %s\n", RS6000_MCOUNT);

63676

+ }

63677

+

63678

rs6000_pic_labelno++;

63679

}

63680

63681

@@ -20544,6 +23867,7 @@

63682

63683

if (using_mfcr_multiple && count > 1)

63684

{

63685

+ rtx insn;

63686

rtvec p;

63687

int ndx;

63688

63689

@@ -20561,16 +23885,43 @@

63690

gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));

63691

ndx++;

63692

}

63693

- emit_insn (gen_rtx_PARALLEL (VOIDmode, p));

63694

+ insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));

63695

gcc_assert (ndx == count);

63696

+

63697

+ /* For the ELFv2 ABI we generate a CFA_RESTORE for each

63698

+ CR field separately. */

63699

+ if (!exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap)

63700

+ {

63701

+ for (i = 0; i < 8; i++)

63702

+ if (save_reg_p (CR0_REGNO + i))

63703

+ add_reg_note (insn, REG_CFA_RESTORE,

63704

+ gen_rtx_REG (SImode, CR0_REGNO + i));

63705

+

63706

+ RTX_FRAME_RELATED_P (insn) = 1;

63707

+ }

63708

}

63709

else

63710

for (i = 0; i < 8; i++)

63711

if (save_reg_p (CR0_REGNO + i))

63712

- emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode, CR0_REGNO + i),

63713

- reg));

63714

+ {

63715

+ rtx insn = emit_insn (gen_movsi_to_cr_one

63716

+ (gen_rtx_REG (CCmode, CR0_REGNO + i), reg));

63717

63718

- if (!exit_func && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap))

63719

+ /* For the ELFv2 ABI we generate a CFA_RESTORE for each

63720

+ CR field separately, attached to the insn that in fact

63721

+ restores this particular CR field. */

63722

+ if (!exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap)

63723

+ {

63724

+ add_reg_note (insn, REG_CFA_RESTORE,

63725

+ gen_rtx_REG (SImode, CR0_REGNO + i));

63726

+

63727

+ RTX_FRAME_RELATED_P (insn) = 1;

63728

+ }

63729

+ }

63730

+

63731

+ /* For other ABIs, we just generate a single CFA_RESTORE for CR2. */

63732

+ if (!exit_func && DEFAULT_ABI != ABI_ELFv2

63733

+ && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap))

63734

{

63735

rtx insn = get_last_insn ();

63736

rtx cr = gen_rtx_REG (SImode, CR2_REGNO);

63737

@@ -20611,10 +23962,22 @@

63738

static rtx

63739

add_crlr_cfa_restore (const rs6000_stack_t *info, rtx cfa_restores)

63740

{

63741

- if (info->cr_save_p)

63742

+ if (DEFAULT_ABI == ABI_ELFv2)

63743

+ {

63744

+ int i;

63745

+ for (i = 0; i < 8; i++)

63746

+ if (save_reg_p (CR0_REGNO + i))

63747

+ {

63748

+ rtx cr = gen_rtx_REG (SImode, CR0_REGNO + i);

63749

+ cfa_restores = alloc_reg_note (REG_CFA_RESTORE, cr,

63750

+ cfa_restores);

63751

+ }

63752

+ }

63753

+ else if (info->cr_save_p)

63754

cfa_restores = alloc_reg_note (REG_CFA_RESTORE,

63755

gen_rtx_REG (SImode, CR2_REGNO),

63756

cfa_restores);

63757

+

63758

if (info->lr_save_p)

63759

cfa_restores = alloc_reg_note (REG_CFA_RESTORE,

63760

gen_rtx_REG (Pmode, LR_REGNO),

63761

@@ -21112,6 +24475,35 @@

63762

|| (!restoring_GPRs_inline

63763

&& info->first_fp_reg_save == 64));

63764

63765

+ /* In the ELFv2 ABI we need to restore all call-saved CR fields from

63766

+ *separate* slots if the routine calls __builtin_eh_return, so

63767

+ that they can be independently restored by the unwinder. */

63768

+ if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)

63769

+ {

63770

+ int i, cr_off = info->ehcr_offset;

63771

+

63772

+ for (i = 0; i < 8; i++)

63773

+ if (!call_used_regs[CR0_REGNO + i])

63774

+ {

63775

+ rtx reg = gen_rtx_REG (SImode, 0);

63776

+ emit_insn (gen_frame_load (reg, frame_reg_rtx,

63777

+ cr_off + frame_off));

63778

+

63779

+ insn = emit_insn (gen_movsi_to_cr_one

63780

+ (gen_rtx_REG (CCmode, CR0_REGNO + i), reg));

63781

+

63782

+ if (!exit_func && flag_shrink_wrap)

63783

+ {

63784

+ add_reg_note (insn, REG_CFA_RESTORE,

63785

+ gen_rtx_REG (SImode, CR0_REGNO + i));

63786

+

63787

+ RTX_FRAME_RELATED_P (insn) = 1;

63788

+ }

63789

+

63790

+ cr_off += reg_size;

63791

+ }

63792

+ }

63793

+

63794

/* Get the old lr if we saved it. If we are restoring registers

63795

out-of-line, then the out-of-line routines can do this for us. */

63796

if (restore_lr && restoring_GPRs_inline)

63797

@@ -21155,7 +24547,7 @@

63798

{

63799

rtx reg = gen_rtx_REG (reg_mode, 2);

63800

emit_insn (gen_frame_load (reg, frame_reg_rtx,

63801

- frame_off + 5 * reg_size));

63802

+ frame_off + RS6000_TOC_SAVE_SLOT));

63803

}

63804

63805

for (i = 0; ; ++i)

63806

@@ -21441,6 +24833,7 @@

63807

if (! restoring_FPRs_inline)

63808

{

63809

int i;

63810

+ int reg;

63811

rtx sym;

63812

63813

if (flag_shrink_wrap)

63814

@@ -21449,10 +24842,9 @@

63815

sym = rs6000_savres_routine_sym (info,

63816

SAVRES_FPR | (lr ? SAVRES_LR : 0));

63817

RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode, sym);

63818

- RTVEC_ELT (p, 3) = gen_rtx_USE (VOIDmode,

63819

- gen_rtx_REG (Pmode,

63820

- DEFAULT_ABI == ABI_AIX

63821

- ? 1 : 11));

63822

+ reg = (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)? 1 : 11;

63823

+ RTVEC_ELT (p, 3) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, reg));

63824

+

63825

for (i = 0; i < 64 - info->first_fp_reg_save; i++)

63826

{

63827

rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);

63828

@@ -21530,7 +24922,8 @@

63829

63830

System V.4 Powerpc's (and the embedded ABI derived from it) use a

63831

different traceback table. */

63832

- if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive

63833

+ if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)

63834

+ && ! flag_inhibit_size_directive

63835

&& rs6000_traceback != traceback_none && !cfun->is_thunk)

63836

{

63837

const char *fname = NULL;

63838

@@ -21858,6 +25251,12 @@

63839

SIBLING_CALL_P (insn) = 1;

63840

emit_barrier ();

63841

63842

+ /* Ensure we have a global entry point for the thunk. ??? We could

63843

+ avoid that if the target routine doesn't need a global entry point,

63844

+ but we do not know whether this is the case at this point. */

63845

+ if (DEFAULT_ABI == ABI_ELFv2)

63846

+ cfun->machine->r2_setup_needed = true;

63847

+

63848

/* Run just enough of rest_of_compilation to get the insns emitted.

63849

There's not really enough bulk here to make other passes such as

63850

instruction scheduling worth while. Note that use_thunk calls

63851

@@ -22554,7 +25953,7 @@

63852

if (TARGET_PROFILE_KERNEL)

63853

return;

63854

63855

- if (DEFAULT_ABI == ABI_AIX)

63856

+ if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)

63857

{

63858

#ifndef NO_PROFILE_COUNTERS

63859

# define NO_PROFILE_COUNTERS 0

63860

@@ -22698,29 +26097,9 @@

63861

break;

63862

63863

case ABI_AIX:

63864

+ case ABI_ELFv2:

63865

case ABI_DARWIN:

63866

- if (!TARGET_PROFILE_KERNEL)

63867

- {

63868

- /* Don't do anything, done in output_profile_hook (). */

63869

- }

63870

- else

63871

- {

63872

- gcc_assert (!TARGET_32BIT);

63873

-

63874

- asm_fprintf (file, "\tmflr %s\n", reg_names[0]);

63875

- asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);

63876

-

63877

- if (cfun->static_chain_decl != NULL)

63878

- {

63879

- asm_fprintf (file, "\tstd %s,24(%s)\n",

63880

- reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);

63881

- fprintf (file, "\tbl %s\n", RS6000_MCOUNT);

63882

- asm_fprintf (file, "\tld %s,24(%s)\n",

63883

- reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);

63884

- }

63885

- else

63886

- fprintf (file, "\tbl %s\n", RS6000_MCOUNT);

63887

- }

63888

+ /* Don't do anything, done in output_profile_hook (). */

63889

break;

63890

}

63891

}

63892

@@ -22846,6 +26225,7 @@

63893

|| rs6000_cpu_attr == CPU_POWER4

63894

|| rs6000_cpu_attr == CPU_POWER5

63895

|| rs6000_cpu_attr == CPU_POWER7

63896

+ || rs6000_cpu_attr == CPU_POWER8

63897

|| rs6000_cpu_attr == CPU_CELL)

63898

&& recog_memoized (dep_insn)

63899

&& (INSN_CODE (dep_insn) >= 0))

63900

@@ -23128,7 +26508,8 @@

63901

if (rs6000_cpu_attr == CPU_CELL)

63902

return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS;

63903

63904

- if (rs6000_sched_groups)

63905

+ if (rs6000_sched_groups

63906

+ && (rs6000_cpu == PROCESSOR_POWER4 || rs6000_cpu == PROCESSOR_POWER5))

63907

{

63908

enum attr_type type = get_attr_type (insn);

63909

if (type == TYPE_LOAD_EXT_U

63910

@@ -23153,7 +26534,8 @@

63911

|| GET_CODE (PATTERN (insn)) == CLOBBER)

63912

return false;

63913

63914

- if (rs6000_sched_groups)

63915

+ if (rs6000_sched_groups

63916

+ && (rs6000_cpu == PROCESSOR_POWER4 || rs6000_cpu == PROCESSOR_POWER5))

63917

{

63918

enum attr_type type = get_attr_type (insn);

63919

if (type == TYPE_LOAD_U || type == TYPE_STORE_U

63920

@@ -23432,6 +26814,8 @@

63921

case CPU_POWER6:

63922

case CPU_POWER7:

63923

return 5;

63924

+ case CPU_POWER8:

63925

+ return 7;

63926

default:

63927

return 1;

63928

}

63929

@@ -24059,6 +27443,39 @@

63930

break;

63931

}

63932

break;

63933

+ case PROCESSOR_POWER8:

63934

+ type = get_attr_type (insn);

63935

+

63936

+ switch (type)

63937

+ {

63938

+ case TYPE_CR_LOGICAL:

63939

+ case TYPE_DELAYED_CR:

63940

+ case TYPE_MFCR:

63941

+ case TYPE_MFCRF:

63942

+ case TYPE_MTCR:

63943

+ case TYPE_COMPARE:

63944

+ case TYPE_DELAYED_COMPARE:

63945

+ case TYPE_VAR_DELAYED_COMPARE:

63946

+ case TYPE_IMUL_COMPARE:

63947

+ case TYPE_LMUL_COMPARE:

63948

+ case TYPE_SYNC:

63949

+ case TYPE_ISYNC:

63950

+ case TYPE_LOAD_L:

63951

+ case TYPE_STORE_C:

63952

+ case TYPE_LOAD_U:

63953

+ case TYPE_LOAD_UX:

63954

+ case TYPE_LOAD_EXT:

63955

+ case TYPE_LOAD_EXT_U:

63956

+ case TYPE_LOAD_EXT_UX:

63957

+ case TYPE_STORE_UX:

63958

+ case TYPE_VECSTORE:

63959

+ case TYPE_MFJMPR:

63960

+ case TYPE_MTJMPR:

63961

+ return true;

63962

+ default:

63963

+ break;

63964

+ }

63965

+ break;

63966

default:

63967

break;

63968

}

63969

@@ -24137,6 +27554,25 @@

63970

break;

63971

}

63972

break;

63973

+ case PROCESSOR_POWER8:

63974

+ type = get_attr_type (insn);

63975

+

63976

+ switch (type)

63977

+ {

63978

+ case TYPE_MFCR:

63979

+ case TYPE_MTCR:

63980

+ case TYPE_ISYNC:

63981

+ case TYPE_SYNC:

63982

+ case TYPE_LOAD_L:

63983

+ case TYPE_STORE_C:

63984

+ case TYPE_LOAD_EXT_U:

63985

+ case TYPE_LOAD_EXT_UX:

63986

+ case TYPE_STORE_UX:

63987

+ return true;

63988

+ default:

63989

+ break;

63990

+ }

63991

+ break;

63992

default:

63993

break;

63994

}

63995

@@ -24226,8 +27662,9 @@

63996

if (can_issue_more && !is_branch_slot_insn (next_insn))

63997

can_issue_more--;

63998

63999

- /* Power6 and Power7 have special group ending nop. */

64000

- if (rs6000_cpu_attr == CPU_POWER6 || rs6000_cpu_attr == CPU_POWER7)

64001

+ /* Do we have a special group ending nop? */

64002

+ if (rs6000_cpu_attr == CPU_POWER6 || rs6000_cpu_attr == CPU_POWER7

64003

+ || rs6000_cpu_attr == CPU_POWER8)

64004

{

64005

nop = gen_group_ending_nop ();

64006

emit_insn_before (nop, next_insn);

64007

@@ -24598,6 +28035,11 @@

64008

ret = (TARGET_32BIT) ? 12 : 24;

64009

break;

64010

64011

+ case ABI_ELFv2:

64012

+ gcc_assert (!TARGET_32BIT);

64013

+ ret = 32;

64014

+ break;

64015

+

64016

case ABI_DARWIN:

64017

case ABI_V4:

64018

ret = (TARGET_32BIT) ? 40 : 48;

64019

@@ -24653,6 +28095,7 @@

64020

break;

64021

64022

/* Under V.4/eabi/darwin, __trampoline_setup does the real work. */

64023

+ case ABI_ELFv2:

64024

case ABI_DARWIN:

64025

case ABI_V4:

64026

emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"),

64027

@@ -24743,6 +28186,9 @@

64028

unsigned_p = TYPE_UNSIGNED (type);

64029

switch (mode)

64030

{

64031

+ case TImode:

64032

+ result = (unsigned_p ? unsigned_V1TI_type_node : V1TI_type_node);

64033

+ break;

64034

case DImode:

64035

result = (unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node);

64036

break;

64037

@@ -24947,7 +28393,7 @@

64038

static void

64039

rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)

64040

{

64041

- if (DEFAULT_ABI == ABI_AIX

64042

+ if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)

64043

&& TARGET_MINIMAL_TOC

64044

&& !TARGET_RELOCATABLE)

64045

{

64046

@@ -24968,7 +28414,8 @@

64047

else

64048

fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);

64049

}

64050

- else if (DEFAULT_ABI == ABI_AIX && !TARGET_RELOCATABLE)

64051

+ else if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)

64052

+ && !TARGET_RELOCATABLE)

64053

fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);

64054

else

64055

{

64056

@@ -25518,7 +28965,7 @@

64057

{

64058

if (flag_pic)

64059

return 3;

64060

- else if (DEFAULT_ABI == ABI_AIX)

64061

+ else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)

64062

return 2;

64063

else

64064

return 0;

64065

@@ -25594,7 +29041,7 @@

64066

void

64067

rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)

64068

{

64069

- if (TARGET_64BIT)

64070

+ if (TARGET_64BIT && DEFAULT_ABI != ABI_ELFv2)

64071

{

64072

fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);

64073

ASM_OUTPUT_LABEL (file, name);

64074

@@ -25660,8 +29107,7 @@

64075

fprintf (file, "%s:\n", desc_name);

64076

fprintf (file, "\t.long %s\n", orig_name);

64077

fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);

64078

- if (DEFAULT_ABI == ABI_AIX)

64079

- fputs ("\t.long 0\n", file);

64080

+ fputs ("\t.long 0\n", file);

64081

fprintf (file, "\t.previous\n");

64082

}

64083

ASM_OUTPUT_LABEL (file, name);

64084

@@ -25690,7 +29136,7 @@

64085

}

64086

#endif

64087

#if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)

64088

- if (TARGET_32BIT)

64089

+ if (TARGET_32BIT || DEFAULT_ABI == ABI_ELFv2)

64090

file_end_indicate_exec_stack ();

64091

#endif

64092

}

64093

@@ -25829,10 +29275,23 @@

64094

name, suffix[smclass], flags & SECTION_ENTSIZE);

64095

}

64096

64097

+#define IN_NAMED_SECTION(DECL) \

64098

+ ((TREE_CODE (DECL) == FUNCTION_DECL || TREE_CODE (DECL) == VAR_DECL) \

64099

+ && DECL_SECTION_NAME (DECL) != NULL_TREE)

64100

+

64101

static section *

64102

rs6000_xcoff_select_section (tree decl, int reloc,

64103

- unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)

64104

+ unsigned HOST_WIDE_INT align)

64105

{

64106

+ /* Place variables with alignment stricter than BIGGEST_ALIGNMENT into

64107

+ named section. */

64108

+ if (align > BIGGEST_ALIGNMENT)

64109

+ {

64110

+ resolve_unique_section (decl, reloc, true);

64111

+ if (IN_NAMED_SECTION (decl))

64112

+ return get_named_section (decl, NULL, reloc);

64113

+ }

64114

+

64115

if (decl_readonly_section (decl, reloc))

64116

{

64117

if (TREE_PUBLIC (decl))

64118

@@ -25870,10 +29329,12 @@

64119

{

64120

const char *name;

64121

64122

- /* Use select_section for private and uninitialized data. */

64123

+ /* Use select_section for private data and uninitialized data with

64124

+ alignment <= BIGGEST_ALIGNMENT. */

64125

if (!TREE_PUBLIC (decl)

64126

|| DECL_COMMON (decl)

64127

- || DECL_INITIAL (decl) == NULL_TREE

64128

+ || (DECL_INITIAL (decl) == NULL_TREE

64129

+ && DECL_ALIGN (decl) <= BIGGEST_ALIGNMENT)

64130

|| DECL_INITIAL (decl) == error_mark_node

64131

|| (flag_zero_initialized_in_bss

64132

&& initializer_zerop (DECL_INITIAL (decl))))

64133

@@ -26430,7 +29891,8 @@

64134

/* For those processors that have slow LR/CTR moves, make them more

64135

expensive than memory in order to bias spills to memory .*/

64136

else if ((rs6000_cpu == PROCESSOR_POWER6

64137

- || rs6000_cpu == PROCESSOR_POWER7)

64138

+ || rs6000_cpu == PROCESSOR_POWER7

64139

+ || rs6000_cpu == PROCESSOR_POWER8)

64140

&& reg_classes_intersect_p (rclass, LINK_OR_CTR_REGS))

64141

ret = 6 * hard_regno_nregs[0][mode];

64142

64143

@@ -26440,7 +29902,7 @@

64144

}

64145

64146

/* If we have VSX, we can easily move between FPR or Altivec registers. */

64147

- else if (VECTOR_UNIT_VSX_P (mode)

64148

+ else if (VECTOR_MEM_VSX_P (mode)

64149

&& reg_classes_intersect_p (to, VSX_REGS)

64150

&& reg_classes_intersect_p (from, VSX_REGS))

64151

ret = 2 * hard_regno_nregs[32][mode];

64152

@@ -26481,7 +29943,8 @@

64153

64154

if (reg_classes_intersect_p (rclass, GENERAL_REGS))

64155

ret = 4 * hard_regno_nregs[0][mode];

64156

- else if (reg_classes_intersect_p (rclass, FLOAT_REGS))

64157

+ else if ((reg_classes_intersect_p (rclass, FLOAT_REGS)

64158

+ || reg_classes_intersect_p (rclass, VSX_REGS)))

64159

ret = 4 * hard_regno_nregs[32][mode];

64160

else if (reg_classes_intersect_p (rclass, ALTIVEC_REGS))

64161

ret = 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode];

64162

@@ -26643,54 +30106,26 @@

64163

emit_insn (gen_rtx_SET (VOIDmode, dst, r));

64164

}

64165

64166

-/* Newton-Raphson approximation of floating point divide with just 2 passes

64167

- (either single precision floating point, or newer machines with higher

64168

- accuracy estimates). Support both scalar and vector divide. Assumes no

64169

- trapping math and finite arguments. */

64170

+/* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,

64171

+ add a reg_note saying that this was a division. Support both scalar and

64172

+ vector divide. Assumes no trapping math and finite arguments. */

64173

64174

-static void

64175

-rs6000_emit_swdiv_high_precision (rtx dst, rtx n, rtx d)

64176

+void

64177

+rs6000_emit_swdiv (rtx dst, rtx n, rtx d, bool note_p)

64178

{

64179

enum machine_mode mode = GET_MODE (dst);

64180

- rtx x0, e0, e1, y1, u0, v0;

64181

- enum insn_code code = optab_handler (smul_optab, mode);

64182

- insn_gen_fn gen_mul = GEN_FCN (code);

64183

- rtx one = rs6000_load_constant_and_splat (mode, dconst1);

64184

+ rtx one, x0, e0, x1, xprev, eprev, xnext, enext, u, v;

64185

+ int i;

64186

64187

- gcc_assert (code != CODE_FOR_nothing);

64188

+ /* Low precision estimates guarantee 5 bits of accuracy. High

64189

+ precision estimates guarantee 14 bits of accuracy. SFmode

64190

+ requires 23 bits of accuracy. DFmode requires 52 bits of

64191

+ accuracy. Each pass at least doubles the accuracy, leading

64192

+ to the following. */

64193

+ int passes = (TARGET_RECIP_PRECISION) ? 1 : 3;

64194

+ if (mode == DFmode || mode == V2DFmode)

64195

+ passes++;

64196

64197

- /* x0 = 1./d estimate */

64198

- x0 = gen_reg_rtx (mode);

64199

- emit_insn (gen_rtx_SET (VOIDmode, x0,

64200

- gen_rtx_UNSPEC (mode, gen_rtvec (1, d),

64201

- UNSPEC_FRES)));

64202

-

64203

- e0 = gen_reg_rtx (mode);

64204

- rs6000_emit_nmsub (e0, d, x0, one); /* e0 = 1. - (d * x0) */

64205

-

64206

- e1 = gen_reg_rtx (mode);

64207

- rs6000_emit_madd (e1, e0, e0, e0); /* e1 = (e0 * e0) + e0 */

64208

-

64209

- y1 = gen_reg_rtx (mode);

64210

- rs6000_emit_madd (y1, e1, x0, x0); /* y1 = (e1 * x0) + x0 */

64211

-

64212

- u0 = gen_reg_rtx (mode);

64213

- emit_insn (gen_mul (u0, n, y1)); /* u0 = n * y1 */

64214

-

64215

- v0 = gen_reg_rtx (mode);

64216

- rs6000_emit_nmsub (v0, d, u0, n); /* v0 = n - (d * u0) */

64217

-

64218

- rs6000_emit_madd (dst, v0, y1, u0); /* dst = (v0 * y1) + u0 */

64219

-}

64220

-

64221

-/* Newton-Raphson approximation of floating point divide that has a low

64222

- precision estimate. Assumes no trapping math and finite arguments. */

64223

-

64224

-static void

64225

-rs6000_emit_swdiv_low_precision (rtx dst, rtx n, rtx d)

64226

-{

64227

- enum machine_mode mode = GET_MODE (dst);

64228

- rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one;

64229

enum insn_code code = optab_handler (smul_optab, mode);

64230

insn_gen_fn gen_mul = GEN_FCN (code);

64231

64232

@@ -26704,47 +30139,45 @@

64233

gen_rtx_UNSPEC (mode, gen_rtvec (1, d),

64234

UNSPEC_FRES)));

64235

64236

- e0 = gen_reg_rtx (mode);

64237

- rs6000_emit_nmsub (e0, d, x0, one); /* e0 = 1. - d * x0 */

64238

+ /* Each iteration but the last calculates x_(i+1) = x_i * (2 - d * x_i). */

64239

+ if (passes > 1) {

64240

64241

- y1 = gen_reg_rtx (mode);

64242

- rs6000_emit_madd (y1, e0, x0, x0); /* y1 = x0 + e0 * x0 */

64243

+ /* e0 = 1. - d * x0 */

64244

+ e0 = gen_reg_rtx (mode);

64245

+ rs6000_emit_nmsub (e0, d, x0, one);

64246

64247

- e1 = gen_reg_rtx (mode);

64248

- emit_insn (gen_mul (e1, e0, e0)); /* e1 = e0 * e0 */

64249

+ /* x1 = x0 + e0 * x0 */

64250

+ x1 = gen_reg_rtx (mode);

64251

+ rs6000_emit_madd (x1, e0, x0, x0);

64252

64253

- y2 = gen_reg_rtx (mode);

64254

- rs6000_emit_madd (y2, e1, y1, y1); /* y2 = y1 + e1 * y1 */

64255

+ for (i = 0, xprev = x1, eprev = e0; i < passes - 2;

64256

+ ++i, xprev = xnext, eprev = enext) {

64257

+

64258

+ /* enext = eprev * eprev */

64259

+ enext = gen_reg_rtx (mode);

64260

+ emit_insn (gen_mul (enext, eprev, eprev));

64261

64262

- e2 = gen_reg_rtx (mode);

64263

- emit_insn (gen_mul (e2, e1, e1)); /* e2 = e1 * e1 */

64264

+ /* xnext = xprev + enext * xprev */

64265

+ xnext = gen_reg_rtx (mode);

64266

+ rs6000_emit_madd (xnext, enext, xprev, xprev);

64267

+ }

64268

64269

- y3 = gen_reg_rtx (mode);

64270

- rs6000_emit_madd (y3, e2, y2, y2); /* y3 = y2 + e2 * y2 */

64271

+ } else

64272

+ xprev = x0;

64273

64274

- u0 = gen_reg_rtx (mode);

64275

- emit_insn (gen_mul (u0, n, y3)); /* u0 = n * y3 */

64276

+ /* The last iteration calculates x_(i+1) = n * x_i * (2 - d * x_i). */

64277

64278

- v0 = gen_reg_rtx (mode);

64279

- rs6000_emit_nmsub (v0, d, u0, n); /* v0 = n - d * u0 */

64280

+ /* u = n * xprev */

64281

+ u = gen_reg_rtx (mode);

64282

+ emit_insn (gen_mul (u, n, xprev));

64283

64284

- rs6000_emit_madd (dst, v0, y3, u0); /* dst = u0 + v0 * y3 */

64285

-}

64286

+ /* v = n - (d * u) */

64287

+ v = gen_reg_rtx (mode);

64288

+ rs6000_emit_nmsub (v, d, u, n);

64289

64290

-/* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,

64291

- add a reg_note saying that this was a division. Support both scalar and

64292

- vector divide. Assumes no trapping math and finite arguments. */

64293

+ /* dst = (v * xprev) + u */

64294

+ rs6000_emit_madd (dst, v, xprev, u);

64295

64296

-void

64297

-rs6000_emit_swdiv (rtx dst, rtx n, rtx d, bool note_p)

64298

-{

64299

- enum machine_mode mode = GET_MODE (dst);

64300

-

64301

- if (RS6000_RECIP_HIGH_PRECISION_P (mode))

64302

- rs6000_emit_swdiv_high_precision (dst, n, d);

64303

- else

64304

- rs6000_emit_swdiv_low_precision (dst, n, d);

64305

-

64306

if (note_p)

64307

add_reg_note (get_last_insn (), REG_EQUAL, gen_rtx_DIV (mode, n, d));

64308

}

64309

@@ -26758,7 +30191,16 @@

64310

enum machine_mode mode = GET_MODE (src);

64311

rtx x0 = gen_reg_rtx (mode);

64312

rtx y = gen_reg_rtx (mode);

64313

- int passes = (TARGET_RECIP_PRECISION) ? 2 : 3;

64314

+

64315

+ /* Low precision estimates guarantee 5 bits of accuracy. High

64316

+ precision estimates guarantee 14 bits of accuracy. SFmode

64317

+ requires 23 bits of accuracy. DFmode requires 52 bits of

64318

+ accuracy. Each pass at least doubles the accuracy, leading

64319

+ to the following. */

64320

+ int passes = (TARGET_RECIP_PRECISION) ? 1 : 3;

64321

+ if (mode == DFmode || mode == V2DFmode)

64322

+ passes++;

64323

+

64324

REAL_VALUE_TYPE dconst3_2;

64325

int i;

64326

rtx halfthree;

64327

@@ -26920,6 +30362,136 @@

64328

}

64329

}

64330

64331

+/* Expand an Altivec constant permutation for little endian mode.

64332

+ There are two issues: First, the two input operands must be

64333

+ swapped so that together they form a double-wide array in LE

64334

+ order. Second, the vperm instruction has surprising behavior

64335

+ in LE mode: it interprets the elements of the source vectors

64336

+ in BE mode ("left to right") and interprets the elements of

64337

+ the destination vector in LE mode ("right to left"). To

64338

+ correct for this, we must subtract each element of the permute

64339

+ control vector from 31.

64340

+

64341

+ For example, suppose we want to concatenate vr10 = {0, 1, 2, 3}

64342

+ with vr11 = {4, 5, 6, 7} and extract {0, 2, 4, 6} using a vperm.

64343

+ We place {0,1,2,3,8,9,10,11,16,17,18,19,24,25,26,27} in vr12 to

64344

+ serve as the permute control vector. Then, in BE mode,

64345

+

64346

+ vperm 9,10,11,12

64347

+

64348

+ places the desired result in vr9. However, in LE mode the

64349

+ vector contents will be

64350

+

64351

+ vr10 = 00000003 00000002 00000001 00000000

64352

+ vr11 = 00000007 00000006 00000005 00000004

64353

+

64354

+ The result of the vperm using the same permute control vector is

64355

+

64356

+ vr9 = 05000000 07000000 01000000 03000000

64357

+

64358

+ That is, the leftmost 4 bytes of vr10 are interpreted as the

64359

+ source for the rightmost 4 bytes of vr9, and so on.

64360

+

64361

+ If we change the permute control vector to

64362

+

64363

+ vr12 = {31,20,29,28,23,22,21,20,15,14,13,12,7,6,5,4}

64364

+

64365

+ and issue

64366

+

64367

+ vperm 9,11,10,12

64368

+

64369

+ we get the desired

64370

+

64371

+ vr9 = 00000006 00000004 00000002 00000000. */

64372

+

64373

+void

64374

+altivec_expand_vec_perm_const_le (rtx operands[4])

64375

+{

64376

+ unsigned int i;

64377

+ rtx perm[16];

64378

+ rtx constv, unspec;

64379

+ rtx target = operands[0];

64380

+ rtx op0 = operands[1];

64381

+ rtx op1 = operands[2];

64382

+ rtx sel = operands[3];

64383

+

64384

+ /* Unpack and adjust the constant selector. */

64385

+ for (i = 0; i < 16; ++i)

64386

+ {

64387

+ rtx e = XVECEXP (sel, 0, i);

64388

+ unsigned int elt = 31 - (INTVAL (e) & 31);

64389

+ perm[i] = GEN_INT (elt);

64390

+ }

64391

+

64392

+ /* Expand to a permute, swapping the inputs and using the

64393

+ adjusted selector. */

64394

+ if (!REG_P (op0))

64395

+ op0 = force_reg (V16QImode, op0);

64396

+ if (!REG_P (op1))

64397

+ op1 = force_reg (V16QImode, op1);

64398

+

64399

+ constv = gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, perm));

64400

+ constv = force_reg (V16QImode, constv);

64401

+ unspec = gen_rtx_UNSPEC (V16QImode, gen_rtvec (3, op1, op0, constv),

64402

+ UNSPEC_VPERM);

64403

+ if (!REG_P (target))

64404

+ {

64405

+ rtx tmp = gen_reg_rtx (V16QImode);

64406

+ emit_move_insn (tmp, unspec);

64407

+ unspec = tmp;

64408

+ }

64409

+

64410

+ emit_move_insn (target, unspec);

64411

+}

64412

+

64413

+/* Similarly to altivec_expand_vec_perm_const_le, we must adjust the

64414

+ permute control vector. But here it's not a constant, so we must

64415

+ generate a vector NAND or NOR to do the adjustment. */

64416

+

64417

+void

64418

+altivec_expand_vec_perm_le (rtx operands[4])

64419

+{

64420

+ rtx notx, iorx, unspec;

64421

+ rtx target = operands[0];

64422

+ rtx op0 = operands[1];

64423

+ rtx op1 = operands[2];

64424

+ rtx sel = operands[3];

64425

+ rtx tmp = target;

64426

+ rtx norreg = gen_reg_rtx (V16QImode);

64427

+ enum machine_mode mode = GET_MODE (target);

64428

+

64429

+ /* Get everything in regs so the pattern matches. */

64430

+ if (!REG_P (op0))

64431

+ op0 = force_reg (mode, op0);

64432

+ if (!REG_P (op1))

64433

+ op1 = force_reg (mode, op1);

64434

+ if (!REG_P (sel))

64435

+ sel = force_reg (V16QImode, sel);

64436

+ if (!REG_P (target))

64437

+ tmp = gen_reg_rtx (mode);

64438

+

64439

+ /* Invert the selector with a VNAND if available, else a VNOR.

64440

+ The VNAND is preferred for future fusion opportunities. */

64441

+ notx = gen_rtx_NOT (V16QImode, sel);

64442

+ iorx = (TARGET_P8_VECTOR

64443

+ ? gen_rtx_IOR (V16QImode, notx, notx)

64444

+ : gen_rtx_AND (V16QImode, notx, notx));

64445

+ emit_insn (gen_rtx_SET (VOIDmode, norreg, iorx));

64446

+

64447

+ /* Permute with operands reversed and adjusted selector. */

64448

+ unspec = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op0, norreg),

64449

+ UNSPEC_VPERM);

64450

+

64451

+ /* Copy into target, possibly by way of a register. */

64452

+ if (!REG_P (target))

64453

+ {

64454

+ emit_move_insn (tmp, unspec);

64455

+ unspec = tmp;

64456

+ }

64457

+

64458

+ emit_move_insn (target, unspec);

64459

+}

64460

+

64461

/* Expand an Altivec constant permutation. Return true if we match

64462

an efficient implementation; false to fall back to VPERM. */

64463

64464

@@ -26927,26 +30499,43 @@

64465

altivec_expand_vec_perm_const (rtx operands[4])

64466

{

64467

struct altivec_perm_insn {

64468

+ HOST_WIDE_INT mask;

64469

enum insn_code impl;

64470

unsigned char perm[16];

64471

};

64472

static const struct altivec_perm_insn patterns[] = {

64473

- { CODE_FOR_altivec_vpkuhum,

64474

+ { OPTION_MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum_direct,

64475

{ 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },

64476

- { CODE_FOR_altivec_vpkuwum,

64477

+ { OPTION_MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum_direct,

64478

{ 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },

64479

- { CODE_FOR_altivec_vmrghb,

64480

+ { OPTION_MASK_ALTIVEC,

64481

+ (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghb_direct

64482

+ : CODE_FOR_altivec_vmrglb_direct),

64483

{ 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },

64484

- { CODE_FOR_altivec_vmrghh,

64485

+ { OPTION_MASK_ALTIVEC,

64486

+ (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghh_direct

64487

+ : CODE_FOR_altivec_vmrglh_direct),

64488

{ 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },

64489

- { CODE_FOR_altivec_vmrghw,

64490

+ { OPTION_MASK_ALTIVEC,

64491

+ (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghw_direct

64492

+ : CODE_FOR_altivec_vmrglw_direct),

64493

{ 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },

64494

- { CODE_FOR_altivec_vmrglb,

64495

+ { OPTION_MASK_ALTIVEC,

64496

+ (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglb_direct

64497

+ : CODE_FOR_altivec_vmrghb_direct),

64498

{ 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },

64499

- { CODE_FOR_altivec_vmrglh,

64500

+ { OPTION_MASK_ALTIVEC,

64501

+ (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglh_direct

64502

+ : CODE_FOR_altivec_vmrghh_direct),

64503

{ 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },

64504

- { CODE_FOR_altivec_vmrglw,

64505

- { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } }

64506

+ { OPTION_MASK_ALTIVEC,

64507

+ (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglw_direct

64508

+ : CODE_FOR_altivec_vmrghw_direct),

64509

+ { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },

64510

+ { OPTION_MASK_P8_VECTOR, CODE_FOR_p8_vmrgew,

64511

+ { 0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 24, 25, 26, 27 } },

64512

+ { OPTION_MASK_P8_VECTOR, CODE_FOR_p8_vmrgow,

64513

+ { 4, 5, 6, 7, 20, 21, 22, 23, 12, 13, 14, 15, 28, 29, 30, 31 } }

64514

};

64515

64516

unsigned int i, j, elt, which;

64517

@@ -27003,7 +30592,9 @@

64518

break;

64519

if (i == 16)

64520

{

64521

- emit_insn (gen_altivec_vspltb (target, op0, GEN_INT (elt)));

64522

+ if (!BYTES_BIG_ENDIAN)

64523

+ elt = 15 - elt;

64524

+ emit_insn (gen_altivec_vspltb_direct (target, op0, GEN_INT (elt)));

64525

return true;

64526

}

64527

64528

@@ -27014,9 +30605,10 @@

64529

break;

64530

if (i == 16)

64531

{

64532

+ int field = BYTES_BIG_ENDIAN ? elt / 2 : 7 - elt / 2;

64533

x = gen_reg_rtx (V8HImode);

64534

- emit_insn (gen_altivec_vsplth (x, gen_lowpart (V8HImode, op0),

64535

- GEN_INT (elt / 2)));

64536

+ emit_insn (gen_altivec_vsplth_direct (x, gen_lowpart (V8HImode, op0),

64537

+ GEN_INT (field)));

64538

emit_move_insn (target, gen_lowpart (V16QImode, x));

64539

return true;

64540

}

64541

@@ -27032,9 +30624,10 @@

64542

break;

64543

if (i == 16)

64544

{

64545

+ int field = BYTES_BIG_ENDIAN ? elt / 4 : 3 - elt / 4;

64546

x = gen_reg_rtx (V4SImode);

64547

- emit_insn (gen_altivec_vspltw (x, gen_lowpart (V4SImode, op0),

64548

- GEN_INT (elt / 4)));

64549

+ emit_insn (gen_altivec_vspltw_direct (x, gen_lowpart (V4SImode, op0),

64550

+ GEN_INT (field)));

64551

emit_move_insn (target, gen_lowpart (V16QImode, x));

64552

return true;

64553

}

64554

@@ -27046,6 +30639,9 @@

64555

{

64556

bool swapped;

64557

64558

+ if ((patterns[j].mask & rs6000_isa_flags) == 0)

64559

+ continue;

64560

+

64561

elt = patterns[j].perm[0];

64562

if (perm[0] == elt)

64563

swapped = false;

64564

@@ -27069,7 +30665,30 @@

64565

enum machine_mode omode = insn_data[icode].operand[0].mode;

64566

enum machine_mode imode = insn_data[icode].operand[1].mode;

64567

64568

- if (swapped)

64569

+ /* For little-endian, don't use vpkuwum and vpkuhum if the

64570

+ underlying vector type is not V4SI and V8HI, respectively.

64571

+ For example, using vpkuwum with a V8HI picks up the even

64572

+ halfwords (BE numbering) when the even halfwords (LE

64573

+ numbering) are what we need. */

64574

+ if (!BYTES_BIG_ENDIAN

64575

+ && icode == CODE_FOR_altivec_vpkuwum_direct

64576

+ && ((GET_CODE (op0) == REG

64577

+ && GET_MODE (op0) != V4SImode)

64578

+ || (GET_CODE (op0) == SUBREG

64579

+ && GET_MODE (XEXP (op0, 0)) != V4SImode)))

64580

+ continue;

64581

+ if (!BYTES_BIG_ENDIAN

64582

+ && icode == CODE_FOR_altivec_vpkuhum_direct

64583

+ && ((GET_CODE (op0) == REG

64584

+ && GET_MODE (op0) != V8HImode)

64585

+ || (GET_CODE (op0) == SUBREG

64586

+ && GET_MODE (XEXP (op0, 0)) != V8HImode)))

64587

+ continue;

64588

+

64589

+ /* For little-endian, the two input operands must be swapped

64590

+ (or swapped back) to ensure proper right-to-left numbering

64591

+ from 0 to 2N-1. */

64592

+ if (swapped ^ !BYTES_BIG_ENDIAN)

64593

x = op0, op0 = op1, op1 = x;

64594

if (imode != V16QImode)

64595

{

64596

@@ -27087,6 +30706,12 @@

64597

}

64598

}

64599

64600

+ if (!BYTES_BIG_ENDIAN)

64601

+ {

64602

+ altivec_expand_vec_perm_const_le (operands);

64603

+ return true;

64604

+ }

64605

+

64606

return false;

64607

}

64608

64609

@@ -27135,7 +30760,6 @@

64610

vmode = GET_MODE (target);

64611

gcc_assert (GET_MODE_NUNITS (vmode) == 2);

64612

dmode = mode_for_vector (GET_MODE_INNER (vmode), 4);

64613

-

64614

x = gen_rtx_VEC_CONCAT (dmode, op0, op1);

64615

v = gen_rtvec (2, GEN_INT (perm0), GEN_INT (perm1));

64616

x = gen_rtx_VEC_SELECT (vmode, x, gen_rtx_PARALLEL (VOIDmode, v));

64617

@@ -27231,7 +30855,7 @@

64618

unsigned i, high, nelt = GET_MODE_NUNITS (vmode);

64619

rtx perm[16];

64620

64621

- high = (highp == BYTES_BIG_ENDIAN ? 0 : nelt / 2);

64622

+ high = (highp ? 0 : nelt / 2);

64623

for (i = 0; i < nelt / 2; i++)

64624

{

64625

perm[i * 2] = GEN_INT (i + high);

64626

@@ -27286,6 +30910,8 @@

64627

{

64628

enum machine_mode mode;

64629

unsigned int regno;

64630

+ enum machine_mode elt_mode;

64631

+ int n_elts;

64632

64633

/* Special handling for structs in darwin64. */

64634

if (TARGET_MACHO

64635

@@ -27305,6 +30931,36 @@

64636

/* Otherwise fall through to standard ABI rules. */

64637

}

64638

64639

+ /* The ELFv2 ABI returns homogeneous VFP aggregates in registers. */

64640

+ if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (valtype), valtype,

64641

+ &elt_mode, &n_elts))

64642

+ {

64643

+ int first_reg, n_regs, i;

64644

+ rtx par;

64645

+

64646

+ if (SCALAR_FLOAT_MODE_P (elt_mode))

64647

+ {

64648

+ /* _Decimal128 must use even/odd register pairs. */

64649

+ first_reg = (elt_mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;

64650

+ n_regs = (GET_MODE_SIZE (elt_mode) + 7) >> 3;

64651

+ }

64652

+ else

64653

+ {

64654

+ first_reg = ALTIVEC_ARG_RETURN;

64655

+ n_regs = 1;

64656

+ }

64657

+

64658

+ par = gen_rtx_PARALLEL (TYPE_MODE (valtype), rtvec_alloc (n_elts));

64659

+ for (i = 0; i < n_elts; i++)

64660

+ {

64661

+ rtx r = gen_rtx_REG (elt_mode, first_reg + i * n_regs);

64662

+ rtx off = GEN_INT (i * GET_MODE_SIZE (elt_mode));

64663

+ XVECEXP (par, 0, i) = gen_rtx_EXPR_LIST (VOIDmode, r, off);

64664

+ }

64665

+

64666

+ return par;

64667

+ }

64668

+

64669

if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)

64670

{

64671

/* Long long return value need be split in -mpowerpc64, 32bit ABI. */

64672

@@ -27417,6 +31073,13 @@

64673

}

64674

64675

64676

+/* Return true if we use LRA instead of reload pass. */

64677

+static bool

64678

+rs6000_lra_p (void)

64679

+{

64680

+ return rs6000_lra_flag;

64681

+}

64682

+

64683

/* Given FROM and TO register numbers, say whether this elimination is allowed.

64684

Frame pointer elimination is automatically handled.

64685

64686

@@ -27679,22 +31342,33 @@

64687

{

64688

{ "altivec", OPTION_MASK_ALTIVEC, false, true },

64689

{ "cmpb", OPTION_MASK_CMPB, false, true },

64690

+ { "crypto", OPTION_MASK_CRYPTO, false, true },

64691

+ { "direct-move", OPTION_MASK_DIRECT_MOVE, false, true },

64692

{ "dlmzb", OPTION_MASK_DLMZB, false, true },

64693

{ "fprnd", OPTION_MASK_FPRND, false, true },

64694

{ "hard-dfp", OPTION_MASK_DFP, false, true },

64695

+ { "htm", OPTION_MASK_HTM, false, true },

64696

{ "isel", OPTION_MASK_ISEL, false, true },

64697

{ "mfcrf", OPTION_MASK_MFCRF, false, true },

64698

{ "mfpgpr", OPTION_MASK_MFPGPR, false, true },

64699

{ "mulhw", OPTION_MASK_MULHW, false, true },

64700

{ "multiple", OPTION_MASK_MULTIPLE, false, true },

64701

- { "update", OPTION_MASK_NO_UPDATE, true , true },

64702

{ "popcntb", OPTION_MASK_POPCNTB, false, true },

64703

{ "popcntd", OPTION_MASK_POPCNTD, false, true },

64704

+ { "power8-fusion", OPTION_MASK_P8_FUSION, false, true },

64705

+ { "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN, false, true },

64706

+ { "power8-vector", OPTION_MASK_P8_VECTOR, false, true },

64707

{ "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT, false, true },

64708

{ "powerpc-gpopt", OPTION_MASK_PPC_GPOPT, false, true },

64709

+ { "quad-memory", OPTION_MASK_QUAD_MEMORY, false, true },

64710

+ { "quad-memory-atomic", OPTION_MASK_QUAD_MEMORY_ATOMIC, false, true },

64711

{ "recip-precision", OPTION_MASK_RECIP_PRECISION, false, true },

64712

{ "string", OPTION_MASK_STRING, false, true },

64713

+ { "update", OPTION_MASK_NO_UPDATE, true , true },

64714

+ { "upper-regs-df", OPTION_MASK_UPPER_REGS_DF, false, false },

64715

+ { "upper-regs-sf", OPTION_MASK_UPPER_REGS_SF, false, false },

64716

{ "vsx", OPTION_MASK_VSX, false, true },

64717

+ { "vsx-timode", OPTION_MASK_VSX_TIMODE, false, true },

64718

#ifdef OPTION_MASK_64BIT

64719

#if TARGET_AIX_OS

64720

{ "aix64", OPTION_MASK_64BIT, false, false },

64721

@@ -27734,6 +31408,11 @@

64722

{ "frsqrtes", RS6000_BTM_FRSQRTES, false, false },

64723

{ "popcntd", RS6000_BTM_POPCNTD, false, false },

64724

{ "cell", RS6000_BTM_CELL, false, false },

64725

+ { "power8-vector", RS6000_BTM_P8_VECTOR, false, false },

64726

+ { "crypto", RS6000_BTM_CRYPTO, false, false },

64727

+ { "htm", RS6000_BTM_HTM, false, false },

64728

+ { "hard-dfp", RS6000_BTM_DFP, false, false },

64729

+ { "hard-float", RS6000_BTM_HARD_FLOAT, false, false },

64730

};

64731

64732

/* Option variables that we want to support inside attribute((target)) and

64733

@@ -28250,7 +31929,6 @@

64734

size_t cur_column;

64735

size_t max_column = 76;

64736

const char *comma = "";

64737

- const char *nl = "\n";

64738

64739

if (indent)

64740

start_column += fprintf (file, "%*s", indent, "");

64741

@@ -28281,7 +31959,6 @@

64742

fprintf (stderr, ", \\\n%*s", (int)start_column, "");

64743

cur_column = start_column + len;

64744

comma = "";

64745

- nl = "\n\n";

64746

}

64747

64748

fprintf (file, "%s%s%s%s", comma, prefix, no_str,

64749

@@ -28291,7 +31968,7 @@

64750

}

64751

}

64752

64753

- fputs (nl, file);

64754

+ fputs ("\n", file);

64755

}

64756

64757

/* Helper function to print the current isa options on a line. */

64758

@@ -28467,118 +32144,149 @@

64759

}

64760

64761

64762

-/* A function pointer under AIX is a pointer to a data area whose first word

64763

- contains the actual address of the function, whose second word contains a

64764

- pointer to its TOC, and whose third word contains a value to place in the

64765

- static chain register (r11). Note that if we load the static chain, our

64766

- "trampoline" need not have any executable code. */

64767

64768

+/* Expand code to perform a call under the AIX or ELFv2 ABI. */

64769

+

64770

void

64771

-rs6000_call_indirect_aix (rtx value, rtx func_desc, rtx flag)

64772

+rs6000_call_aix (rtx value, rtx func_desc, rtx flag, rtx cookie)

64773

{

64774

+ rtx toc_reg = gen_rtx_REG (Pmode, TOC_REGNUM);

64775

+ rtx toc_load = NULL_RTX;

64776

+ rtx toc_restore = NULL_RTX;

64777

rtx func_addr;

64778

- rtx toc_reg;

64779

- rtx sc_reg;

64780

- rtx stack_ptr;

64781

- rtx stack_toc_offset;

64782

- rtx stack_toc_mem;

64783

- rtx func_toc_offset;

64784

- rtx func_toc_mem;

64785

- rtx func_sc_offset;

64786

- rtx func_sc_mem;

64787

+ rtx abi_reg = NULL_RTX;

64788

+ rtx call[4];

64789

+ int n_call;

64790

rtx insn;

64791

- rtx (*call_func) (rtx, rtx, rtx, rtx);

64792

- rtx (*call_value_func) (rtx, rtx, rtx, rtx, rtx);

64793

64794

- stack_ptr = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);

64795

- toc_reg = gen_rtx_REG (Pmode, TOC_REGNUM);

64796

+ /* Handle longcall attributes. */

64797

+ if (INTVAL (cookie) & CALL_LONG)

64798

+ func_desc = rs6000_longcall_ref (func_desc);

64799

64800

- /* Load up address of the actual function. */

64801

- func_desc = force_reg (Pmode, func_desc);

64802

- func_addr = gen_reg_rtx (Pmode);

64803

- emit_move_insn (func_addr, gen_rtx_MEM (Pmode, func_desc));

64804

-

64805

- if (TARGET_32BIT)

64806

+ /* Handle indirect calls. */

64807

+ if (GET_CODE (func_desc) != SYMBOL_REF

64808

+ || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (func_desc)))

64809

{

64810

+ /* Save the TOC into its reserved slot before the call,

64811

+ and prepare to restore it after the call. */

64812

+ rtx stack_ptr = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);

64813

+ rtx stack_toc_offset = GEN_INT (RS6000_TOC_SAVE_SLOT);

64814

+ rtx stack_toc_mem = gen_frame_mem (Pmode,

64815

+ gen_rtx_PLUS (Pmode, stack_ptr,

64816

+ stack_toc_offset));

64817

+ toc_restore = gen_rtx_SET (VOIDmode, toc_reg, stack_toc_mem);

64818

64819

- stack_toc_offset = GEN_INT (TOC_SAVE_OFFSET_32BIT);

64820

- func_toc_offset = GEN_INT (AIX_FUNC_DESC_TOC_32BIT);

64821

- func_sc_offset = GEN_INT (AIX_FUNC_DESC_SC_32BIT);

64822

- if (TARGET_POINTERS_TO_NESTED_FUNCTIONS)

64823

- {

64824

- call_func = gen_call_indirect_aix32bit;

64825

- call_value_func = gen_call_value_indirect_aix32bit;

64826

- }

64827

+ /* Can we optimize saving the TOC in the prologue or

64828

+ do we need to do it at every call? */

64829

+ if (TARGET_SAVE_TOC_INDIRECT && !cfun->calls_alloca)

64830

+ cfun->machine->save_toc_in_prologue = true;

64831

else

64832

{

64833

- call_func = gen_call_indirect_aix32bit_nor11;

64834

- call_value_func = gen_call_value_indirect_aix32bit_nor11;

64835

+ MEM_VOLATILE_P (stack_toc_mem) = 1;

64836

+ emit_move_insn (stack_toc_mem, toc_reg);

64837

}

64838

- }

64839

- else

64840

- {

64841

- stack_toc_offset = GEN_INT (TOC_SAVE_OFFSET_64BIT);

64842

- func_toc_offset = GEN_INT (AIX_FUNC_DESC_TOC_64BIT);

64843

- func_sc_offset = GEN_INT (AIX_FUNC_DESC_SC_64BIT);

64844

- if (TARGET_POINTERS_TO_NESTED_FUNCTIONS)

64845

+

64846

+ if (DEFAULT_ABI == ABI_ELFv2)

64847

{

64848

- call_func = gen_call_indirect_aix64bit;

64849

- call_value_func = gen_call_value_indirect_aix64bit;

64850

+ /* A function pointer in the ELFv2 ABI is just a plain address, but

64851

+ the ABI requires it to be loaded into r12 before the call. */

64852

+ func_addr = gen_rtx_REG (Pmode, 12);

64853

+ emit_move_insn (func_addr, func_desc);

64854

+ abi_reg = func_addr;

64855

}

64856

else

64857

{

64858

- call_func = gen_call_indirect_aix64bit_nor11;

64859

- call_value_func = gen_call_value_indirect_aix64bit_nor11;

64860

- }

64861

- }

64862

+ /* A function pointer under AIX is a pointer to a data area whose

64863

+ first word contains the actual address of the function, whose

64864

+ second word contains a pointer to its TOC, and whose third word

64865

+ contains a value to place in the static chain register (r11).

64866

+ Note that if we load the static chain, our "trampoline" need

64867

+ not have any executable code. */

64868

64869

- /* Reserved spot to store the TOC. */

64870

- stack_toc_mem = gen_frame_mem (Pmode,

64871

- gen_rtx_PLUS (Pmode,

64872

- stack_ptr,

64873

- stack_toc_offset));

64874

+ /* Load up address of the actual function. */

64875

+ func_desc = force_reg (Pmode, func_desc);

64876

+ func_addr = gen_reg_rtx (Pmode);

64877

+ emit_move_insn (func_addr, gen_rtx_MEM (Pmode, func_desc));

64878

64879

- gcc_assert (cfun);

64880

- gcc_assert (cfun->machine);

64881

+ /* Prepare to load the TOC of the called function. Note that the

64882

+ TOC load must happen immediately before the actual call so

64883

+ that unwinding the TOC registers works correctly. See the

64884

+ comment in frob_update_context. */

64885

+ rtx func_toc_offset = GEN_INT (GET_MODE_SIZE (Pmode));

64886

+ rtx func_toc_mem = gen_rtx_MEM (Pmode,

64887

+ gen_rtx_PLUS (Pmode, func_desc,

64888

+ func_toc_offset));

64889

+ toc_load = gen_rtx_USE (VOIDmode, func_toc_mem);

64890

64891

- /* Can we optimize saving the TOC in the prologue or do we need to do it at

64892

- every call? */

64893

- if (TARGET_SAVE_TOC_INDIRECT && !cfun->calls_alloca)

64894

- cfun->machine->save_toc_in_prologue = true;

64895

-

64896

+ /* If we have a static chain, load it up. */

64897

+ if (TARGET_POINTERS_TO_NESTED_FUNCTIONS)

64898

+ {

64899

+ rtx sc_reg = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM);

64900

+ rtx func_sc_offset = GEN_INT (2 * GET_MODE_SIZE (Pmode));

64901

+ rtx func_sc_mem = gen_rtx_MEM (Pmode,

64902

+ gen_rtx_PLUS (Pmode, func_desc,

64903

+ func_sc_offset));

64904

+ emit_move_insn (sc_reg, func_sc_mem);

64905

+ abi_reg = sc_reg;

64906

+ }

64907

+ }

64908

+ }

64909

else

64910

{

64911

- MEM_VOLATILE_P (stack_toc_mem) = 1;

64912

- emit_move_insn (stack_toc_mem, toc_reg);

64913

+ /* Direct calls use the TOC: for local calls, the callee will

64914

+ assume the TOC register is set; for non-local calls, the

64915

+ PLT stub needs the TOC register. */

64916

+ abi_reg = toc_reg;

64917

+ func_addr = func_desc;

64918

}

64919

64920

- /* Calculate the address to load the TOC of the called function. We don't

64921

- actually load this until the split after reload. */

64922

- func_toc_mem = gen_rtx_MEM (Pmode,

64923

- gen_rtx_PLUS (Pmode,

64924

- func_desc,

64925

- func_toc_offset));

64926

+ /* Create the call. */

64927

+ call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_addr), flag);

64928

+ if (value != NULL_RTX)

64929

+ call[0] = gen_rtx_SET (VOIDmode, value, call[0]);

64930

+ n_call = 1;

64931

64932

- /* If we have a static chain, load it up. */

64933

- if (TARGET_POINTERS_TO_NESTED_FUNCTIONS)

64934

- {

64935

- func_sc_mem = gen_rtx_MEM (Pmode,

64936

- gen_rtx_PLUS (Pmode,

64937

- func_desc,

64938

- func_sc_offset));

64939

+ if (toc_load)

64940

+ call[n_call++] = toc_load;

64941

+ if (toc_restore)

64942

+ call[n_call++] = toc_restore;

64943

64944

- sc_reg = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM);

64945

- emit_move_insn (sc_reg, func_sc_mem);

64946

- }

64947

+ call[n_call++] = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, LR_REGNO));

64948

64949

+ insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (n_call, call));

64950

+ insn = emit_call_insn (insn);

64951

+

64952

+ /* Mention all registers defined by the ABI to hold information

64953

+ as uses in CALL_INSN_FUNCTION_USAGE. */

64954

+ if (abi_reg)

64955

+ use_reg (&CALL_INSN_FUNCTION_USAGE (insn), abi_reg);

64956

+}

64957

+

64958

+/* Expand code to perform a sibling call under the AIX or ELFv2 ABI. */

64959

+

64960

+void

64961

+rs6000_sibcall_aix (rtx value, rtx func_desc, rtx flag, rtx cookie)

64962

+{

64963

+ rtx call[2];

64964

+ rtx insn;

64965

+

64966

+ gcc_assert (INTVAL (cookie) == 0);

64967

+

64968

/* Create the call. */

64969

- if (value)

64970

- insn = call_value_func (value, func_addr, flag, func_toc_mem,

64971

- stack_toc_mem);

64972

- else

64973

- insn = call_func (func_addr, flag, func_toc_mem, stack_toc_mem);

64974

+ call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_desc), flag);

64975

+ if (value != NULL_RTX)

64976

+ call[0] = gen_rtx_SET (VOIDmode, value, call[0]);

64977

64978

- emit_call_insn (insn);

64979

+ call[1] = simple_return_rtx;

64980

+

64981

+ insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (2, call));

64982

+ insn = emit_call_insn (insn);

64983

+

64984

+ /* Note use of the TOC register. */

64985

+ use_reg (&CALL_INSN_FUNCTION_USAGE (insn), gen_rtx_REG (Pmode, TOC_REGNUM));

64986

+ /* We need to also mark a use of the link register since the function we

64987

+ sibling-call to will use it to return to our caller. */

64988

+ use_reg (&CALL_INSN_FUNCTION_USAGE (insn), gen_rtx_REG (Pmode, LR_REGNO));

64989

}

64990

64991

/* Return whether we need to always update the saved TOC pointer when we update

64992

@@ -28679,6 +32387,661 @@

64993

add_to_hard_reg_set (&set->set, Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);

64994

}

64995

64996

+

64997

+/* Helper function for rs6000_split_logical to emit a logical instruction after

64998

+ spliting the operation to single GPR registers.

64999

+

65000

+ DEST is the destination register.

65001

+ OP1 and OP2 are the input source registers.

65002

+ CODE is the base operation (AND, IOR, XOR, NOT).

65003

+ MODE is the machine mode.

65004

+ If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.

65005

+ If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.

65006

+ If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.

65007

+ CLOBBER_REG is either NULL or a scratch register of type CC to allow

65008

+ formation of the AND instructions. */

65009

+

65010

+static void

65011

+rs6000_split_logical_inner (rtx dest,

65012

+ rtx op1,

65013

+ rtx op2,

65014

+ enum rtx_code code,

65015

+ enum machine_mode mode,

65016

+ bool complement_final_p,

65017

+ bool complement_op1_p,

65018

+ bool complement_op2_p,

65019

+ rtx clobber_reg)

65020

+{

65021

+ rtx bool_rtx;

65022

+ rtx set_rtx;

65023

+

65024

+ /* Optimize AND of 0/0xffffffff and IOR/XOR of 0. */

65025

+ if (op2 && GET_CODE (op2) == CONST_INT

65026

+ && (mode == SImode || (mode == DImode && TARGET_POWERPC64))

65027

+ && !complement_final_p && !complement_op1_p && !complement_op2_p)

65028

+ {

65029

+ HOST_WIDE_INT mask = GET_MODE_MASK (mode);

65030

+ HOST_WIDE_INT value = INTVAL (op2) & mask;

65031

+

65032

+ /* Optimize AND of 0 to just set 0. Optimize AND of -1 to be a move. */

65033

+ if (code == AND)

65034

+ {

65035

+ if (value == 0)

65036

+ {

65037

+ emit_insn (gen_rtx_SET (VOIDmode, dest, const0_rtx));

65038

+ return;

65039

+ }

65040

+

65041

+ else if (value == mask)

65042

+ {

65043

+ if (!rtx_equal_p (dest, op1))

65044

+ emit_insn (gen_rtx_SET (VOIDmode, dest, op1));

65045

+ return;

65046

+ }

65047

+ }

65048

+

65049

+ /* Optimize IOR/XOR of 0 to be a simple move. Split large operations

65050

+ into separate ORI/ORIS or XORI/XORIS instrucitons. */

65051

+ else if (code == IOR || code == XOR)

65052

+ {

65053

+ if (value == 0)

65054

+ {

65055

+ if (!rtx_equal_p (dest, op1))

65056

+ emit_insn (gen_rtx_SET (VOIDmode, dest, op1));

65057

+ return;

65058

+ }

65059

+ }

65060

+ }

65061

+

65062

+ if (complement_op1_p)

65063

+ op1 = gen_rtx_NOT (mode, op1);

65064

+

65065

+ if (complement_op2_p)

65066

+ op2 = gen_rtx_NOT (mode, op2);

65067

+

65068

+ bool_rtx = ((code == NOT)

65069

+ ? gen_rtx_NOT (mode, op1)

65070

+ : gen_rtx_fmt_ee (code, mode, op1, op2));

65071

+

65072

+ if (complement_final_p)

65073

+ bool_rtx = gen_rtx_NOT (mode, bool_rtx);

65074

+

65075

+ set_rtx = gen_rtx_SET (VOIDmode, dest, bool_rtx);

65076

+

65077

+ /* Is this AND with an explicit clobber? */

65078

+ if (clobber_reg)

65079

+ {

65080

+ rtx clobber = gen_rtx_CLOBBER (VOIDmode, clobber_reg);

65081

+ set_rtx = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set_rtx, clobber));

65082

+ }

65083

+

65084

+ emit_insn (set_rtx);

65085

+ return;

65086

+}

65087

+

65088

+/* Split a DImode AND/IOR/XOR with a constant on a 32-bit system. These

65089

+ operations are split immediately during RTL generation to allow for more

65090

+ optimizations of the AND/IOR/XOR.

65091

+

65092

+ OPERANDS is an array containing the destination and two input operands.

65093

+ CODE is the base operation (AND, IOR, XOR, NOT).

65094

+ MODE is the machine mode.

65095

+ If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.

65096

+ If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.

65097

+ If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.

65098

+ CLOBBER_REG is either NULL or a scratch register of type CC to allow

65099

+ formation of the AND instructions. */

65100

+

65101

+static void

65102

+rs6000_split_logical_di (rtx operands[3],

65103

+ enum rtx_code code,

65104

+ bool complement_final_p,

65105

+ bool complement_op1_p,

65106

+ bool complement_op2_p,

65107

+ rtx clobber_reg)

65108

+{

65109

+ const HOST_WIDE_INT lower_32bits = HOST_WIDE_INT_C(0xffffffff);

65110

+ const HOST_WIDE_INT upper_32bits = ~ lower_32bits;

65111

+ const HOST_WIDE_INT sign_bit = HOST_WIDE_INT_C(0x80000000);

65112

+ enum hi_lo { hi = 0, lo = 1 };

65113

+ rtx op0_hi_lo[2], op1_hi_lo[2], op2_hi_lo[2];

65114

+ size_t i;

65115

+

65116

+ op0_hi_lo[hi] = gen_highpart (SImode, operands[0]);

65117

+ op1_hi_lo[hi] = gen_highpart (SImode, operands[1]);

65118

+ op0_hi_lo[lo] = gen_lowpart (SImode, operands[0]);

65119

+ op1_hi_lo[lo] = gen_lowpart (SImode, operands[1]);

65120

+

65121

+ if (code == NOT)

65122

+ op2_hi_lo[hi] = op2_hi_lo[lo] = NULL_RTX;

65123

+ else

65124

+ {

65125

+ if (GET_CODE (operands[2]) != CONST_INT)

65126

+ {

65127

+ op2_hi_lo[hi] = gen_highpart_mode (SImode, DImode, operands[2]);

65128

+ op2_hi_lo[lo] = gen_lowpart (SImode, operands[2]);

65129

+ }

65130

+ else

65131

+ {

65132

+ HOST_WIDE_INT value = INTVAL (operands[2]);

65133

+ HOST_WIDE_INT value_hi_lo[2];

65134

+

65135

+ gcc_assert (!complement_final_p);

65136

+ gcc_assert (!complement_op1_p);

65137

+ gcc_assert (!complement_op2_p);

65138

+

65139

+ value_hi_lo[hi] = value >> 32;

65140

+ value_hi_lo[lo] = value & lower_32bits;

65141

+

65142

+ for (i = 0; i < 2; i++)

65143

+ {

65144

+ HOST_WIDE_INT sub_value = value_hi_lo[i];

65145

+

65146

+ if (sub_value & sign_bit)

65147

+ sub_value |= upper_32bits;

65148

+

65149

+ op2_hi_lo[i] = GEN_INT (sub_value);

65150

+

65151

+ /* If this is an AND instruction, check to see if we need to load

65152

+ the value in a register. */

65153

+ if (code == AND && sub_value != -1 && sub_value != 0

65154

+ && !and_operand (op2_hi_lo[i], SImode))

65155

+ op2_hi_lo[i] = force_reg (SImode, op2_hi_lo[i]);

65156

+ }

65157

+ }

65158

+ }

65159

+

65160

+ for (i = 0; i < 2; i++)

65161

+ {

65162

+ /* Split large IOR/XOR operations. */

65163

+ if ((code == IOR || code == XOR)

65164

+ && GET_CODE (op2_hi_lo[i]) == CONST_INT

65165

+ && !complement_final_p

65166

+ && !complement_op1_p

65167

+ && !complement_op2_p

65168

+ && clobber_reg == NULL_RTX

65169

+ && !logical_const_operand (op2_hi_lo[i], SImode))

65170

+ {

65171

+ HOST_WIDE_INT value = INTVAL (op2_hi_lo[i]);

65172

+ HOST_WIDE_INT hi_16bits = value & HOST_WIDE_INT_C(0xffff0000);

65173

+ HOST_WIDE_INT lo_16bits = value & HOST_WIDE_INT_C(0x0000ffff);

65174

+ rtx tmp = gen_reg_rtx (SImode);

65175

+

65176

+ /* Make sure the constant is sign extended. */

65177

+ if ((hi_16bits & sign_bit) != 0)

65178

+ hi_16bits |= upper_32bits;

65179

+

65180

+ rs6000_split_logical_inner (tmp, op1_hi_lo[i], GEN_INT (hi_16bits),

65181

+ code, SImode, false, false, false,

65182

+ NULL_RTX);

65183

+

65184

+ rs6000_split_logical_inner (op0_hi_lo[i], tmp, GEN_INT (lo_16bits),

65185

+ code, SImode, false, false, false,

65186

+ NULL_RTX);

65187

+ }

65188

+ else

65189

+ rs6000_split_logical_inner (op0_hi_lo[i], op1_hi_lo[i], op2_hi_lo[i],

65190

+ code, SImode, complement_final_p,

65191

+ complement_op1_p, complement_op2_p,

65192

+ clobber_reg);

65193

+ }

65194

+

65195

+ return;

65196

+}

65197

+

65198

+/* Split the insns that make up boolean operations operating on multiple GPR

65199

+ registers. The boolean MD patterns ensure that the inputs either are

65200

+ exactly the same as the output registers, or there is no overlap.

65201

+

65202

+ OPERANDS is an array containing the destination and two input operands.

65203

+ CODE is the base operation (AND, IOR, XOR, NOT).

65204

+ MODE is the machine mode.

65205

+ If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.

65206

+ If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.

65207

+ If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.

65208

+ CLOBBER_REG is either NULL or a scratch register of type CC to allow

65209

+ formation of the AND instructions. */

65210

+

65211

+void

65212

+rs6000_split_logical (rtx operands[3],

65213

+ enum rtx_code code,

65214

+ bool complement_final_p,

65215

+ bool complement_op1_p,

65216

+ bool complement_op2_p,

65217

+ rtx clobber_reg)

65218

+{

65219

+ enum machine_mode mode = GET_MODE (operands[0]);

65220

+ enum machine_mode sub_mode;

65221

+ rtx op0, op1, op2;

65222

+ int sub_size, regno0, regno1, nregs, i;

65223

+

65224

+ /* If this is DImode, use the specialized version that can run before

65225

+ register allocation. */

65226

+ if (mode == DImode && !TARGET_POWERPC64)

65227

+ {

65228

+ rs6000_split_logical_di (operands, code, complement_final_p,

65229

+ complement_op1_p, complement_op2_p,

65230

+ clobber_reg);

65231

+ return;

65232

+ }

65233

+

65234

+ op0 = operands[0];

65235

+ op1 = operands[1];

65236

+ op2 = (code == NOT) ? NULL_RTX : operands[2];

65237

+ sub_mode = (TARGET_POWERPC64) ? DImode : SImode;

65238

+ sub_size = GET_MODE_SIZE (sub_mode);

65239

+ regno0 = REGNO (op0);

65240

+ regno1 = REGNO (op1);

65241

+

65242

+ gcc_assert (reload_completed);

65243

+ gcc_assert (IN_RANGE (regno0, FIRST_GPR_REGNO, LAST_GPR_REGNO));

65244

+ gcc_assert (IN_RANGE (regno1, FIRST_GPR_REGNO, LAST_GPR_REGNO));

65245

+

65246

+ nregs = rs6000_hard_regno_nregs[(int)mode][regno0];

65247

+ gcc_assert (nregs > 1);

65248

+

65249

+ if (op2 && REG_P (op2))

65250

+ gcc_assert (IN_RANGE (REGNO (op2), FIRST_GPR_REGNO, LAST_GPR_REGNO));

65251

+

65252

+ for (i = 0; i < nregs; i++)

65253

+ {

65254

+ int offset = i * sub_size;

65255

+ rtx sub_op0 = simplify_subreg (sub_mode, op0, mode, offset);

65256

+ rtx sub_op1 = simplify_subreg (sub_mode, op1, mode, offset);

65257

+ rtx sub_op2 = ((code == NOT)

65258

+ ? NULL_RTX

65259

+ : simplify_subreg (sub_mode, op2, mode, offset));

65260

+

65261

+ rs6000_split_logical_inner (sub_op0, sub_op1, sub_op2, code, sub_mode,

65262

+ complement_final_p, complement_op1_p,

65263

+ complement_op2_p, clobber_reg);

65264

+ }

65265

+

65266

+ return;

65267

+}

65268

+

65269

+

65270

+/* Return true if the peephole2 can combine a load involving a combination of

65271

+ an addis instruction and a load with an offset that can be fused together on

65272

+ a power8.

65273

+

65274

+ The operands are:

65275

+ operands[0] register set with addis

65276

+ operands[1] value set via addis

65277

+ operands[2] target register being loaded

65278

+ operands[3] D-form memory reference using operands[0].

65279

+

65280

+ In addition, we are passed a boolean that is true if this is a peephole2,

65281

+ and we can use see if the addis_reg is dead after the insn and can be

65282

+ replaced by the target register. */

65283

+

65284

+bool

65285

+fusion_gpr_load_p (rtx *operands, bool peep2_p)

65286

+{

65287

+ rtx addis_reg = operands[0];

65288

+ rtx addis_value = operands[1];

65289

+ rtx target = operands[2];

65290

+ rtx mem = operands[3];

65291

+ rtx addr;

65292

+ rtx base_reg;

65293

+

65294

+ /* Validate arguments. */

65295

+ if (!base_reg_operand (addis_reg, GET_MODE (addis_reg)))

65296

+ return false;

65297

+

65298

+ if (!base_reg_operand (target, GET_MODE (target)))

65299

+ return false;

65300

+

65301

+ if (!fusion_gpr_addis (addis_value, GET_MODE (addis_value)))

65302

+ return false;

65303

+

65304

+ if (!fusion_gpr_mem_load (mem, GET_MODE (mem)))

65305

+ return false;

65306

+

65307

+ /* Allow sign/zero extension. */

65308

+ if (GET_CODE (mem) == ZERO_EXTEND

65309

+ || (GET_CODE (mem) == SIGN_EXTEND && TARGET_P8_FUSION_SIGN))

65310

+ mem = XEXP (mem, 0);

65311

+

65312

+ if (!MEM_P (mem))

65313

+ return false;

65314

+

65315

+ addr = XEXP (mem, 0); /* either PLUS or LO_SUM. */

65316

+ if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)

65317

+ return false;

65318

+

65319

+ /* Validate that the register used to load the high value is either the

65320

+ register being loaded, or we can safely replace its use in a peephole2.

65321

+

65322

+ If this is a peephole2, we assume that there are 2 instructions in the

65323

+ peephole (addis and load), so we want to check if the target register was

65324

+ not used in the memory address and the register to hold the addis result

65325

+ is dead after the peephole. */

65326

+ if (REGNO (addis_reg) != REGNO (target))

65327

+ {

65328

+ if (!peep2_p)

65329

+ return false;

65330

+

65331

+ if (reg_mentioned_p (target, mem))

65332

+ return false;

65333

+

65334

+ if (!peep2_reg_dead_p (2, addis_reg))

65335

+ return false;

65336

+

65337

+ /* If the target register being loaded is the stack pointer, we must

65338

+ avoid loading any other value into it, even temporarily. */

65339

+ if (REG_P (target) && REGNO (target) == STACK_POINTER_REGNUM)

65340

+ return false;

65341

+ }

65342

+

65343

+ base_reg = XEXP (addr, 0);

65344

+ return REGNO (addis_reg) == REGNO (base_reg);

65345

+}

65346

+

65347

+/* During the peephole2 pass, adjust and expand the insns for a load fusion

65348

+ sequence. We adjust the addis register to use the target register. If the

65349

+ load sign extends, we adjust the code to do the zero extending load, and an

65350

+ explicit sign extension later since the fusion only covers zero extending

65351

+ loads.

65352

+

65353

+ The operands are:

65354

+ operands[0] register set with addis (to be replaced with target)

65355

+ operands[1] value set via addis

65356

+ operands[2] target register being loaded

65357

+ operands[3] D-form memory reference using operands[0]. */

65358

+

65359

+void

65360

+expand_fusion_gpr_load (rtx *operands)

65361

+{

65362

+ rtx addis_value = operands[1];

65363

+ rtx target = operands[2];

65364

+ rtx orig_mem = operands[3];

65365

+ rtx new_addr, new_mem, orig_addr, offset;

65366

+ enum rtx_code plus_or_lo_sum;

65367

+ enum machine_mode target_mode = GET_MODE (target);

65368

+ enum machine_mode extend_mode = target_mode;

65369

+ enum machine_mode ptr_mode = Pmode;

65370

+ enum rtx_code extend = UNKNOWN;

65371

+ rtx addis_reg = ((ptr_mode == target_mode)

65372

+ ? target

65373

+ : simplify_subreg (ptr_mode, target, target_mode, 0));

65374

+

65375

+ if (GET_CODE (orig_mem) == ZERO_EXTEND

65376

+ || (TARGET_P8_FUSION_SIGN && GET_CODE (orig_mem) == SIGN_EXTEND))

65377

+ {

65378

+ extend = GET_CODE (orig_mem);

65379

+ orig_mem = XEXP (orig_mem, 0);

65380

+ target_mode = GET_MODE (orig_mem);

65381

+ }

65382

+

65383

+ gcc_assert (MEM_P (orig_mem));

65384

+

65385

+ orig_addr = XEXP (orig_mem, 0);

65386

+ plus_or_lo_sum = GET_CODE (orig_addr);

65387

+ gcc_assert (plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM);

65388

+

65389

+ offset = XEXP (orig_addr, 1);

65390

+ new_addr = gen_rtx_fmt_ee (plus_or_lo_sum, ptr_mode, addis_reg, offset);

65391

+ new_mem = change_address (orig_mem, target_mode, new_addr);

65392

+

65393

+ if (extend != UNKNOWN)

65394

+ new_mem = gen_rtx_fmt_e (ZERO_EXTEND, extend_mode, new_mem);

65395

+

65396

+ emit_insn (gen_rtx_SET (VOIDmode, addis_reg, addis_value));

65397

+ emit_insn (gen_rtx_SET (VOIDmode, target, new_mem));

65398

+

65399

+ if (extend == SIGN_EXTEND)

65400

+ {

65401

+ int sub_off = ((BYTES_BIG_ENDIAN)

65402

+ ? GET_MODE_SIZE (extend_mode) - GET_MODE_SIZE (target_mode)

65403

+ : 0);

65404

+ rtx sign_reg

65405

+ = simplify_subreg (target_mode, target, extend_mode, sub_off);

65406

+

65407

+ emit_insn (gen_rtx_SET (VOIDmode, target,

65408

+ gen_rtx_SIGN_EXTEND (extend_mode, sign_reg)));

65409

+ }

65410

+

65411

+ return;

65412

+}

65413

+

65414

+/* Return a string to fuse an addis instruction with a gpr load to the same

65415

+ register that we loaded up the addis instruction. The code is complicated,

65416

+ so we call output_asm_insn directly, and just return "".

65417

+

65418

+ The operands are:

65419

+ operands[0] register set with addis (must be same reg as target).

65420

+ operands[1] value set via addis

65421

+ operands[2] target register being loaded

65422

+ operands[3] D-form memory reference using operands[0]. */

65423

+

65424

+const char *

65425

+emit_fusion_gpr_load (rtx *operands)

65426

+{

65427

+ rtx addis_reg = operands[0];

65428

+ rtx addis_value = operands[1];

65429

+ rtx target = operands[2];

65430

+ rtx mem = operands[3];

65431

+ rtx fuse_ops[10];

65432

+ rtx addr;

65433

+ rtx load_offset;

65434

+ const char *addis_str = NULL;

65435

+ const char *load_str = NULL;

65436

+ const char *extend_insn = NULL;

65437

+ const char *mode_name = NULL;

65438

+ char insn_template[80];

65439

+ enum machine_mode mode;

65440

+ const char *comment_str = ASM_COMMENT_START;

65441

+ bool sign_p = false;

65442

+

65443

+ gcc_assert (REG_P (addis_reg) && REG_P (target));

65444

+ gcc_assert (REGNO (addis_reg) == REGNO (target));

65445

+

65446

+ if (*comment_str == ' ')

65447

+ comment_str++;

65448

+

65449

+ /* Allow sign/zero extension. */

65450

+ if (GET_CODE (mem) == ZERO_EXTEND)

65451

+ mem = XEXP (mem, 0);

65452

+

65453

+ else if (GET_CODE (mem) == SIGN_EXTEND && TARGET_P8_FUSION_SIGN)

65454

+ {

65455

+ sign_p = true;

65456

+ mem = XEXP (mem, 0);

65457

+ }

65458

+

65459

+ gcc_assert (MEM_P (mem));

65460

+ addr = XEXP (mem, 0);

65461

+ if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)

65462

+ gcc_unreachable ();

65463

+

65464

+ load_offset = XEXP (addr, 1);

65465

+

65466

+ /* Now emit the load instruction to the same register. */

65467

+ mode = GET_MODE (mem);

65468

+ switch (mode)

65469

+ {

65470

+ case QImode:

65471

+ mode_name = "char";

65472

+ load_str = "lbz";

65473

+ extend_insn = "extsb %0,%0";

65474

+ break;

65475

+

65476

+ case HImode:

65477

+ mode_name = "short";

65478

+ load_str = "lhz";

65479

+ extend_insn = "extsh %0,%0";

65480

+ break;

65481

+

65482

+ case SImode:

65483

+ mode_name = "int";

65484

+ load_str = "lwz";

65485

+ extend_insn = "extsw %0,%0";

65486

+ break;

65487

+

65488

+ case DImode:

65489

+ if (TARGET_POWERPC64)

65490

+ {

65491

+ mode_name = "long";

65492

+ load_str = "ld";

65493

+ }

65494

+ else

65495

+ gcc_unreachable ();

65496

+ break;

65497

+

65498

+ default:

65499

+ gcc_unreachable ();

65500

+ }

65501

+

65502

+ /* Emit the addis instruction. */

65503

+ fuse_ops[0] = target;

65504

+ if (satisfies_constraint_L (addis_value))

65505

+ {

65506

+ fuse_ops[1] = addis_value;

65507

+ addis_str = "lis %0,%v1";

65508

+ }

65509

+

65510

+ else if (GET_CODE (addis_value) == PLUS)

65511

+ {

65512

+ rtx op0 = XEXP (addis_value, 0);

65513

+ rtx op1 = XEXP (addis_value, 1);

65514

+

65515

+ if (REG_P (op0) && CONST_INT_P (op1)

65516

+ && satisfies_constraint_L (op1))

65517

+ {

65518

+ fuse_ops[1] = op0;

65519

+ fuse_ops[2] = op1;

65520

+ addis_str = "addis %0,%1,%v2";

65521

+ }

65522

+ }

65523

+

65524

+ else if (GET_CODE (addis_value) == HIGH)

65525

+ {

65526

+ rtx value = XEXP (addis_value, 0);

65527

+ if (GET_CODE (value) == UNSPEC && XINT (value, 1) == UNSPEC_TOCREL)

65528

+ {

65529

+ fuse_ops[1] = XVECEXP (value, 0, 0); /* symbol ref. */

65530

+ fuse_ops[2] = XVECEXP (value, 0, 1); /* TOC register. */

65531

+ if (TARGET_ELF)

65532

+ addis_str = "addis %0,%2,%1@toc@ha";

65533

+

65534

+ else if (TARGET_XCOFF)

65535

+ addis_str = "addis %0,%1@u(%2)";

65536

+

65537

+ else

65538

+ gcc_unreachable ();

65539

+ }

65540

+

65541

+ else if (GET_CODE (value) == PLUS)

65542

+ {

65543

+ rtx op0 = XEXP (value, 0);

65544

+ rtx op1 = XEXP (value, 1);

65545

+

65546

+ if (GET_CODE (op0) == UNSPEC

65547

+ && XINT (op0, 1) == UNSPEC_TOCREL

65548

+ && CONST_INT_P (op1))

65549

+ {

65550

+ fuse_ops[1] = XVECEXP (op0, 0, 0); /* symbol ref. */

65551

+ fuse_ops[2] = XVECEXP (op0, 0, 1); /* TOC register. */

65552

+ fuse_ops[3] = op1;

65553

+ if (TARGET_ELF)

65554

+ addis_str = "addis %0,%2,%1+%3@toc@ha";

65555

+

65556

+ else if (TARGET_XCOFF)

65557

+ addis_str = "addis %0,%1+%3@u(%2)";

65558

+

65559

+ else

65560

+ gcc_unreachable ();

65561

+ }

65562

+ }

65563

+

65564

+ else if (satisfies_constraint_L (value))

65565

+ {

65566

+ fuse_ops[1] = value;

65567

+ addis_str = "lis %0,%v1";

65568

+ }

65569

+

65570

+ else if (TARGET_ELF && !TARGET_POWERPC64 && CONSTANT_P (value))

65571

+ {

65572

+ fuse_ops[1] = value;

65573

+ addis_str = "lis %0,%1@ha";

65574

+ }

65575

+ }

65576

+

65577

+ if (!addis_str)

65578

+ fatal_insn ("Could not generate addis value for fusion", addis_value);

65579

+

65580

+ sprintf (insn_template, "%s\t\t%s gpr load fusion, type %s", addis_str,

65581

+ comment_str, mode_name);

65582

+ output_asm_insn (insn_template, fuse_ops);

65583

+

65584

+ /* Emit the D-form load instruction. */

65585

+ if (CONST_INT_P (load_offset) && satisfies_constraint_I (load_offset))

65586

+ {

65587

+ sprintf (insn_template, "%s %%0,%%1(%%0)", load_str);

65588

+ fuse_ops[1] = load_offset;

65589

+ output_asm_insn (insn_template, fuse_ops);

65590

+ }

65591

+

65592

+ else if (GET_CODE (load_offset) == UNSPEC

65593

+ && XINT (load_offset, 1) == UNSPEC_TOCREL)

65594

+ {

65595

+ if (TARGET_ELF)

65596

+ sprintf (insn_template, "%s %%0,%%1@toc@l(%%0)", load_str);

65597

+

65598

+ else if (TARGET_XCOFF)

65599

+ sprintf (insn_template, "%s %%0,%%1@l(%%0)", load_str);

65600

+

65601

+ else

65602

+ gcc_unreachable ();

65603

+

65604

+ fuse_ops[1] = XVECEXP (load_offset, 0, 0);

65605

+ output_asm_insn (insn_template, fuse_ops);

65606

+ }

65607

+

65608

+ else if (GET_CODE (load_offset) == PLUS

65609

+ && GET_CODE (XEXP (load_offset, 0)) == UNSPEC

65610

+ && XINT (XEXP (load_offset, 0), 1) == UNSPEC_TOCREL

65611

+ && CONST_INT_P (XEXP (load_offset, 1)))

65612

+ {

65613

+ rtx tocrel_unspec = XEXP (load_offset, 0);

65614

+ if (TARGET_ELF)

65615

+ sprintf (insn_template, "%s %%0,%%1+%%2@toc@l(%%0)", load_str);

65616

+

65617

+ else if (TARGET_XCOFF)

65618

+ sprintf (insn_template, "%s %%0,%%1+%%2@l(%%0)", load_str);

65619

+

65620

+ else

65621

+ gcc_unreachable ();

65622

+

65623

+ fuse_ops[1] = XVECEXP (tocrel_unspec, 0, 0);

65624

+ fuse_ops[2] = XEXP (load_offset, 1);

65625

+ output_asm_insn (insn_template, fuse_ops);

65626

+ }

65627

+

65628

+ else if (TARGET_ELF && !TARGET_POWERPC64 && CONSTANT_P (load_offset))

65629

+ {

65630

+ sprintf (insn_template, "%s %%0,%%1@l(%%0)", load_str);

65631

+

65632

+ fuse_ops[1] = load_offset;

65633

+ output_asm_insn (insn_template, fuse_ops);

65634

+ }

65635

+

65636

+ else

65637

+ fatal_insn ("Unable to generate load offset for fusion", load_offset);

65638

+

65639

+ /* Handle sign extension. The peephole2 pass generates this as a separate

65640

+ insn, but we handle it just in case it got reattached. */

65641

+ if (sign_p)

65642

+ {

65643

+ gcc_assert (extend_insn != NULL);

65644

+ output_asm_insn (extend_insn, fuse_ops);

65645

+ }

65646

+

65647

+ return "";

65648

+}

65649

+

65650

+

65651

struct gcc_target targetm = TARGET_INITIALIZER;

65652

65653

#include "gt-rs6000.h"

65654

Index: gcc/config/rs6000/vsx.md

65655

===================================================================

65656

--- a/src/gcc/config/rs6000/vsx.md (.../tags/gcc_4_8_2_release)

65657

+++ b/src/gcc/config/rs6000/vsx.md (.../branches/gcc-4_8-branch)

65658

@@ -34,12 +34,21 @@

65659

(define_mode_iterator VSX_F [V4SF V2DF])

65660

65661

;; Iterator for logical types supported by VSX

65662

-(define_mode_iterator VSX_L [V16QI V8HI V4SI V2DI V4SF V2DF TI])

65663

+(define_mode_iterator VSX_L [V16QI V8HI V4SI V2DI V4SF V2DF V1TI TI])

65664

65665

;; Iterator for memory move. Handle TImode specially to allow

65666

;; it to use gprs as well as vsx registers.

65667

-(define_mode_iterator VSX_M [V16QI V8HI V4SI V2DI V4SF V2DF])

65668

+(define_mode_iterator VSX_M [V16QI V8HI V4SI V2DI V4SF V2DF V1TI])

65669

65670

+(define_mode_iterator VSX_M2 [V16QI

65671

+ V8HI

65672

+ V4SI

65673

+ V2DI

65674

+ V4SF

65675

+ V2DF

65676

+ V1TI

65677

+ (TI "TARGET_VSX_TIMODE")])

65678

+

65679

;; Map into the appropriate load/store name based on the type

65680

(define_mode_attr VSm [(V16QI "vw4")

65681

(V8HI "vw4")

65682

@@ -48,7 +57,8 @@

65683

(V2DF "vd2")

65684

(V2DI "vd2")

65685

(DF "d")

65686

- (TI "vw4")])

65687

+ (V1TI "vd2")

65688

+ (TI "vd2")])

65689

65690

;; Map into the appropriate suffix based on the type

65691

(define_mode_attr VSs [(V16QI "sp")

65692

@@ -59,7 +69,8 @@

65693

(V2DI "dp")

65694

(DF "dp")

65695

(SF "sp")

65696

- (TI "sp")])

65697

+ (V1TI "dp")

65698

+ (TI "dp")])

65699

65700

;; Map the register class used

65701

(define_mode_attr VSr [(V16QI "v")

65702

@@ -70,7 +81,8 @@

65703

(V2DF "wd")

65704

(DF "ws")

65705

(SF "d")

65706

- (TI "wd")])

65707

+ (V1TI "v")

65708

+ (TI "wt")])

65709

65710

;; Map the register class used for float<->int conversions

65711

(define_mode_attr VSr2 [(V2DF "wd")

65712

@@ -115,7 +127,7 @@

65713

(V4SF "v")

65714

(V2DI "v")

65715

(V2DF "v")

65716

- (TI "v")

65717

+ (V1TI "v")

65718

(DF "s")])

65719

65720

;; Appropriate type for add ops (and other simple FP ops)

65721

@@ -173,7 +185,8 @@

65722

(V2DF "vecdouble")])

65723

65724

;; Map the scalar mode for a vector type

65725

-(define_mode_attr VS_scalar [(V2DF "DF")

65726

+(define_mode_attr VS_scalar [(V1TI "TI")

65727

+ (V2DF "DF")

65728

(V2DI "DI")

65729

(V4SF "SF")

65730

(V4SI "SI")

65731

@@ -184,7 +197,8 @@

65732

(define_mode_attr VS_double [(V4SI "V8SI")

65733

(V4SF "V8SF")

65734

(V2DI "V4DI")

65735

- (V2DF "V4DF")])

65736

+ (V2DF "V4DF")

65737

+ (V1TI "V2TI")])

65738

65739

;; Constants for creating unspecs

65740

(define_c_enum "unspec"

65741

@@ -192,6 +206,8 @@

65742

UNSPEC_VSX_CVDPSXWS

65743

UNSPEC_VSX_CVDPUXWS

65744

UNSPEC_VSX_CVSPDP

65745

+ UNSPEC_VSX_CVSPDPN

65746

+ UNSPEC_VSX_CVDPSPN

65747

UNSPEC_VSX_CVSXWDP

65748

UNSPEC_VSX_CVUXWDP

65749

UNSPEC_VSX_CVSXDSP

65750

@@ -204,80 +220,397 @@

65751

UNSPEC_VSX_ROUND_I

65752

UNSPEC_VSX_ROUND_IC

65753

UNSPEC_VSX_SLDWI

65754

+ UNSPEC_VSX_XXSPLTW

65755

])

65756

65757

;; VSX moves

65758

-(define_insn "*vsx_mov<mode>"

65759

- [(set (match_operand:VSX_M 0 "nonimmediate_operand" "=Z,<VSr>,<VSr>,?Z,?wa,?wa,*Y,*r,*r,<VSr>,?wa,*r,v,wZ,v")

65760

- (match_operand:VSX_M 1 "input_operand" "<VSr>,Z,<VSr>,wa,Z,wa,r,Y,r,j,j,j,W,v,wZ"))]

65761

- "VECTOR_MEM_VSX_P (<MODE>mode)

65762

- && (register_operand (operands[0], <MODE>mode)

65763

- || register_operand (operands[1], <MODE>mode))"

65764

+

65765

+;; The patterns for LE permuted loads and stores come before the general

65766

+;; VSX moves so they match first.

65767

+(define_insn_and_split "*vsx_le_perm_load_<mode>"

65768

+ [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wa")

65769

+ (match_operand:VSX_D 1 "memory_operand" "Z"))]

65770

+ "!BYTES_BIG_ENDIAN && TARGET_VSX"

65771

+ "#"

65772

+ "!BYTES_BIG_ENDIAN && TARGET_VSX"

65773

+ [(set (match_dup 2)

65774

+ (vec_select:<MODE>

65775

+ (match_dup 1)

65776

+ (parallel [(const_int 1) (const_int 0)])))

65777

+ (set (match_dup 0)

65778

+ (vec_select:<MODE>

65779

+ (match_dup 2)

65780

+ (parallel [(const_int 1) (const_int 0)])))]

65781

+ "

65782

{

65783

- switch (which_alternative)

65784

- {

65785

- case 0:

65786

- case 3:

65787

- gcc_assert (MEM_P (operands[0])

65788

- && GET_CODE (XEXP (operands[0], 0)) != PRE_INC

65789

- && GET_CODE (XEXP (operands[0], 0)) != PRE_DEC

65790

- && GET_CODE (XEXP (operands[0], 0)) != PRE_MODIFY);

65791

- return "stx<VSm>x %x1,%y0";

65792

+ operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[0])

65793

+ : operands[0];

65794

+}

65795

+ "

65796

+ [(set_attr "type" "vecload")

65797

+ (set_attr "length" "8")])

65798

65799

- case 1:

65800

- case 4:

65801

- gcc_assert (MEM_P (operands[1])

65802

- && GET_CODE (XEXP (operands[1], 0)) != PRE_INC

65803

- && GET_CODE (XEXP (operands[1], 0)) != PRE_DEC

65804

- && GET_CODE (XEXP (operands[1], 0)) != PRE_MODIFY);

65805

- return "lx<VSm>x %x0,%y1";

65806

+(define_insn_and_split "*vsx_le_perm_load_<mode>"

65807

+ [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa")

65808

+ (match_operand:VSX_W 1 "memory_operand" "Z"))]

65809

+ "!BYTES_BIG_ENDIAN && TARGET_VSX"

65810

+ "#"

65811

+ "!BYTES_BIG_ENDIAN && TARGET_VSX"

65812

+ [(set (match_dup 2)

65813

+ (vec_select:<MODE>

65814

+ (match_dup 1)

65815

+ (parallel [(const_int 2) (const_int 3)

65816

+ (const_int 0) (const_int 1)])))

65817

+ (set (match_dup 0)

65818

+ (vec_select:<MODE>

65819

+ (match_dup 2)

65820

+ (parallel [(const_int 2) (const_int 3)

65821

+ (const_int 0) (const_int 1)])))]

65822

+ "

65823

+{

65824

+ operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[0])

65825

+ : operands[0];

65826

+}

65827

+ "

65828

+ [(set_attr "type" "vecload")

65829

+ (set_attr "length" "8")])

65830

65831

- case 2:

65832

- case 5:

65833

- return "xxlor %x0,%x1,%x1";

65834

+(define_insn_and_split "*vsx_le_perm_load_v8hi"

65835

+ [(set (match_operand:V8HI 0 "vsx_register_operand" "=wa")

65836

+ (match_operand:V8HI 1 "memory_operand" "Z"))]

65837

+ "!BYTES_BIG_ENDIAN && TARGET_VSX"

65838

+ "#"

65839

+ "!BYTES_BIG_ENDIAN && TARGET_VSX"

65840

+ [(set (match_dup 2)

65841

+ (vec_select:V8HI

65842

+ (match_dup 1)

65843

+ (parallel [(const_int 4) (const_int 5)

65844

+ (const_int 6) (const_int 7)

65845

+ (const_int 0) (const_int 1)

65846

+ (const_int 2) (const_int 3)])))

65847

+ (set (match_dup 0)

65848

+ (vec_select:V8HI

65849

+ (match_dup 2)

65850

+ (parallel [(const_int 4) (const_int 5)

65851

+ (const_int 6) (const_int 7)

65852

+ (const_int 0) (const_int 1)

65853

+ (const_int 2) (const_int 3)])))]

65854

+ "

65855

+{

65856

+ operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[0])

65857

+ : operands[0];

65858

+}

65859

+ "

65860

+ [(set_attr "type" "vecload")

65861

+ (set_attr "length" "8")])

65862

65863

- case 6:

65864

- case 7:

65865

- case 8:

65866

- case 11:

65867

- return "#";

65868

+(define_insn_and_split "*vsx_le_perm_load_v16qi"

65869

+ [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa")

65870

+ (match_operand:V16QI 1 "memory_operand" "Z"))]

65871

+ "!BYTES_BIG_ENDIAN && TARGET_VSX"

65872

+ "#"

65873

+ "!BYTES_BIG_ENDIAN && TARGET_VSX"

65874

+ [(set (match_dup 2)

65875

+ (vec_select:V16QI

65876

+ (match_dup 1)

65877

+ (parallel [(const_int 8) (const_int 9)

65878

+ (const_int 10) (const_int 11)

65879

+ (const_int 12) (const_int 13)

65880

+ (const_int 14) (const_int 15)

65881

+ (const_int 0) (const_int 1)

65882

+ (const_int 2) (const_int 3)

65883

+ (const_int 4) (const_int 5)

65884

+ (const_int 6) (const_int 7)])))

65885

+ (set (match_dup 0)

65886

+ (vec_select:V16QI

65887

+ (match_dup 2)

65888

+ (parallel [(const_int 8) (const_int 9)

65889

+ (const_int 10) (const_int 11)

65890

+ (const_int 12) (const_int 13)

65891

+ (const_int 14) (const_int 15)

65892

+ (const_int 0) (const_int 1)

65893

+ (const_int 2) (const_int 3)

65894

+ (const_int 4) (const_int 5)

65895

+ (const_int 6) (const_int 7)])))]

65896

+ "

65897

+{

65898

+ operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[0])

65899

+ : operands[0];

65900

+}

65901

+ "

65902

+ [(set_attr "type" "vecload")

65903

+ (set_attr "length" "8")])

65904

65905

- case 9:

65906

- case 10:

65907

- return "xxlxor %x0,%x0,%x0";

65908

+(define_insn "*vsx_le_perm_store_<mode>"

65909

+ [(set (match_operand:VSX_D 0 "memory_operand" "=Z")

65910

+ (match_operand:VSX_D 1 "vsx_register_operand" "+wa"))]

65911

+ "!BYTES_BIG_ENDIAN && TARGET_VSX"

65912

+ "#"

65913

+ [(set_attr "type" "vecstore")

65914

+ (set_attr "length" "12")])

65915

65916

- case 12:

65917

- return output_vec_const_move (operands);

65918

+(define_split

65919

+ [(set (match_operand:VSX_D 0 "memory_operand" "")

65920

+ (match_operand:VSX_D 1 "vsx_register_operand" ""))]

65921

+ "!BYTES_BIG_ENDIAN && TARGET_VSX && !reload_completed"

65922

+ [(set (match_dup 2)

65923

+ (vec_select:<MODE>

65924

+ (match_dup 1)

65925

+ (parallel [(const_int 1) (const_int 0)])))

65926

+ (set (match_dup 0)

65927

+ (vec_select:<MODE>

65928

+ (match_dup 2)

65929

+ (parallel [(const_int 1) (const_int 0)])))]

65930

+{

65931

+ operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[1])

65932

+ : operands[1];

65933

+})

65934

65935

- case 13:

65936

- gcc_assert (MEM_P (operands[0])

65937

- && GET_CODE (XEXP (operands[0], 0)) != PRE_INC

65938

- && GET_CODE (XEXP (operands[0], 0)) != PRE_DEC

65939

- && GET_CODE (XEXP (operands[0], 0)) != PRE_MODIFY);

65940

- return "stvx %1,%y0";

65941

+;; The post-reload split requires that we re-permute the source

65942

+;; register in case it is still live.

65943

+(define_split

65944

+ [(set (match_operand:VSX_D 0 "memory_operand" "")

65945

+ (match_operand:VSX_D 1 "vsx_register_operand" ""))]

65946

+ "!BYTES_BIG_ENDIAN && TARGET_VSX && reload_completed"

65947

+ [(set (match_dup 1)

65948

+ (vec_select:<MODE>

65949

+ (match_dup 1)

65950

+ (parallel [(const_int 1) (const_int 0)])))

65951

+ (set (match_dup 0)

65952

+ (vec_select:<MODE>

65953

+ (match_dup 1)

65954

+ (parallel [(const_int 1) (const_int 0)])))

65955

+ (set (match_dup 1)

65956

+ (vec_select:<MODE>

65957

+ (match_dup 1)

65958

+ (parallel [(const_int 1) (const_int 0)])))]

65959

+ "")

65960

65961

- case 14:

65962

- gcc_assert (MEM_P (operands[0])

65963

- && GET_CODE (XEXP (operands[0], 0)) != PRE_INC

65964

- && GET_CODE (XEXP (operands[0], 0)) != PRE_DEC

65965

- && GET_CODE (XEXP (operands[0], 0)) != PRE_MODIFY);

65966

- return "lvx %0,%y1";

65967

+(define_insn "*vsx_le_perm_store_<mode>"

65968

+ [(set (match_operand:VSX_W 0 "memory_operand" "=Z")

65969

+ (match_operand:VSX_W 1 "vsx_register_operand" "+wa"))]

65970

+ "!BYTES_BIG_ENDIAN && TARGET_VSX"

65971

+ "#"

65972

+ [(set_attr "type" "vecstore")

65973

+ (set_attr "length" "12")])

65974

65975

- default:

65976

- gcc_unreachable ();

65977

- }

65978

+(define_split

65979

+ [(set (match_operand:VSX_W 0 "memory_operand" "")

65980

+ (match_operand:VSX_W 1 "vsx_register_operand" ""))]

65981

+ "!BYTES_BIG_ENDIAN && TARGET_VSX && !reload_completed"

65982

+ [(set (match_dup 2)

65983

+ (vec_select:<MODE>

65984

+ (match_dup 1)

65985

+ (parallel [(const_int 2) (const_int 3)

65986

+ (const_int 0) (const_int 1)])))

65987

+ (set (match_dup 0)

65988

+ (vec_select:<MODE>

65989

+ (match_dup 2)

65990

+ (parallel [(const_int 2) (const_int 3)

65991

+ (const_int 0) (const_int 1)])))]

65992

+{

65993

+ operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[1])

65994

+ : operands[1];

65995

+})

65996

+

65997

+;; The post-reload split requires that we re-permute the source

65998

+;; register in case it is still live.

65999

+(define_split

66000

+ [(set (match_operand:VSX_W 0 "memory_operand" "")

66001

+ (match_operand:VSX_W 1 "vsx_register_operand" ""))]

66002

+ "!BYTES_BIG_ENDIAN && TARGET_VSX && reload_completed"

66003

+ [(set (match_dup 1)

66004

+ (vec_select:<MODE>

66005

+ (match_dup 1)

66006

+ (parallel [(const_int 2) (const_int 3)

66007

+ (const_int 0) (const_int 1)])))

66008

+ (set (match_dup 0)

66009

+ (vec_select:<MODE>

66010

+ (match_dup 1)

66011

+ (parallel [(const_int 2) (const_int 3)

66012

+ (const_int 0) (const_int 1)])))

66013

+ (set (match_dup 1)

66014

+ (vec_select:<MODE>

66015

+ (match_dup 1)

66016

+ (parallel [(const_int 2) (const_int 3)

66017

+ (const_int 0) (const_int 1)])))]

66018

+ "")

66019

+

66020

+(define_insn "*vsx_le_perm_store_v8hi"

66021

+ [(set (match_operand:V8HI 0 "memory_operand" "=Z")

66022

+ (match_operand:V8HI 1 "vsx_register_operand" "+wa"))]

66023

+ "!BYTES_BIG_ENDIAN && TARGET_VSX"

66024

+ "#"

66025

+ [(set_attr "type" "vecstore")

66026

+ (set_attr "length" "12")])

66027

+

66028

+(define_split

66029

+ [(set (match_operand:V8HI 0 "memory_operand" "")

66030

+ (match_operand:V8HI 1 "vsx_register_operand" ""))]

66031

+ "!BYTES_BIG_ENDIAN && TARGET_VSX && !reload_completed"

66032

+ [(set (match_dup 2)

66033

+ (vec_select:V8HI

66034

+ (match_dup 1)

66035

+ (parallel [(const_int 4) (const_int 5)

66036

+ (const_int 6) (const_int 7)

66037

+ (const_int 0) (const_int 1)

66038

+ (const_int 2) (const_int 3)])))

66039

+ (set (match_dup 0)

66040

+ (vec_select:V8HI

66041

+ (match_dup 2)

66042

+ (parallel [(const_int 4) (const_int 5)

66043

+ (const_int 6) (const_int 7)

66044

+ (const_int 0) (const_int 1)

66045

+ (const_int 2) (const_int 3)])))]

66046

+{

66047

+ operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[1])

66048

+ : operands[1];

66049

+})

66050

+

66051

+;; The post-reload split requires that we re-permute the source

66052

+;; register in case it is still live.

66053

+(define_split

66054

+ [(set (match_operand:V8HI 0 "memory_operand" "")

66055

+ (match_operand:V8HI 1 "vsx_register_operand" ""))]

66056

+ "!BYTES_BIG_ENDIAN && TARGET_VSX && reload_completed"

66057

+ [(set (match_dup 1)

66058

+ (vec_select:V8HI

66059

+ (match_dup 1)

66060

+ (parallel [(const_int 4) (const_int 5)

66061

+ (const_int 6) (const_int 7)

66062

+ (const_int 0) (const_int 1)

66063

+ (const_int 2) (const_int 3)])))

66064

+ (set (match_dup 0)

66065

+ (vec_select:V8HI

66066

+ (match_dup 1)

66067

+ (parallel [(const_int 4) (const_int 5)

66068

+ (const_int 6) (const_int 7)

66069

+ (const_int 0) (const_int 1)

66070

+ (const_int 2) (const_int 3)])))

66071

+ (set (match_dup 1)

66072

+ (vec_select:V8HI

66073

+ (match_dup 1)

66074

+ (parallel [(const_int 4) (const_int 5)

66075

+ (const_int 6) (const_int 7)

66076

+ (const_int 0) (const_int 1)

66077

+ (const_int 2) (const_int 3)])))]

66078

+ "")

66079

+

66080

+(define_insn "*vsx_le_perm_store_v16qi"

66081

+ [(set (match_operand:V16QI 0 "memory_operand" "=Z")

66082

+ (match_operand:V16QI 1 "vsx_register_operand" "+wa"))]

66083

+ "!BYTES_BIG_ENDIAN && TARGET_VSX"

66084

+ "#"

66085

+ [(set_attr "type" "vecstore")

66086

+ (set_attr "length" "12")])

66087

+

66088

+(define_split

66089

+ [(set (match_operand:V16QI 0 "memory_operand" "")

66090

+ (match_operand:V16QI 1 "vsx_register_operand" ""))]

66091

+ "!BYTES_BIG_ENDIAN && TARGET_VSX && !reload_completed"

66092

+ [(set (match_dup 2)

66093

+ (vec_select:V16QI

66094

+ (match_dup 1)

66095

+ (parallel [(const_int 8) (const_int 9)

66096

+ (const_int 10) (const_int 11)

66097

+ (const_int 12) (const_int 13)

66098

+ (const_int 14) (const_int 15)

66099

+ (const_int 0) (const_int 1)

66100

+ (const_int 2) (const_int 3)

66101

+ (const_int 4) (const_int 5)

66102

+ (const_int 6) (const_int 7)])))

66103

+ (set (match_dup 0)

66104

+ (vec_select:V16QI

66105

+ (match_dup 2)

66106

+ (parallel [(const_int 8) (const_int 9)

66107

+ (const_int 10) (const_int 11)

66108

+ (const_int 12) (const_int 13)

66109

+ (const_int 14) (const_int 15)

66110

+ (const_int 0) (const_int 1)

66111

+ (const_int 2) (const_int 3)

66112

+ (const_int 4) (const_int 5)

66113

+ (const_int 6) (const_int 7)])))]

66114

+{

66115

+ operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[1])

66116

+ : operands[1];

66117

+})

66118

+

66119

+;; The post-reload split requires that we re-permute the source

66120

+;; register in case it is still live.

66121

+(define_split

66122

+ [(set (match_operand:V16QI 0 "memory_operand" "")

66123

+ (match_operand:V16QI 1 "vsx_register_operand" ""))]

66124

+ "!BYTES_BIG_ENDIAN && TARGET_VSX && reload_completed"

66125

+ [(set (match_dup 1)

66126

+ (vec_select:V16QI

66127

+ (match_dup 1)

66128

+ (parallel [(const_int 8) (const_int 9)

66129

+ (const_int 10) (const_int 11)

66130

+ (const_int 12) (const_int 13)

66131

+ (const_int 14) (const_int 15)

66132

+ (const_int 0) (const_int 1)

66133

+ (const_int 2) (const_int 3)

66134

+ (const_int 4) (const_int 5)

66135

+ (const_int 6) (const_int 7)])))

66136

+ (set (match_dup 0)

66137

+ (vec_select:V16QI

66138

+ (match_dup 1)

66139

+ (parallel [(const_int 8) (const_int 9)

66140

+ (const_int 10) (const_int 11)

66141

+ (const_int 12) (const_int 13)

66142

+ (const_int 14) (const_int 15)

66143

+ (const_int 0) (const_int 1)

66144

+ (const_int 2) (const_int 3)

66145

+ (const_int 4) (const_int 5)

66146

+ (const_int 6) (const_int 7)])))

66147

+ (set (match_dup 1)

66148

+ (vec_select:V16QI

66149

+ (match_dup 1)

66150

+ (parallel [(const_int 8) (const_int 9)

66151

+ (const_int 10) (const_int 11)

66152

+ (const_int 12) (const_int 13)

66153

+ (const_int 14) (const_int 15)

66154

+ (const_int 0) (const_int 1)

66155

+ (const_int 2) (const_int 3)

66156

+ (const_int 4) (const_int 5)

66157

+ (const_int 6) (const_int 7)])))]

66158

+ "")

66159

+

66160

+

66161

+(define_insn "*vsx_mov<mode>"

66162

+ [(set (match_operand:VSX_M 0 "nonimmediate_operand" "=Z,<VSr>,<VSr>,?Z,?wa,?wa,wQ,?&r,??Y,??r,??r,<VSr>,?wa,*r,v,wZ, v")

66163

+ (match_operand:VSX_M 1 "input_operand" "<VSr>,Z,<VSr>,wa,Z,wa,r,wQ,r,Y,r,j,j,j,W,v,wZ"))]

66164

+ "VECTOR_MEM_VSX_P (<MODE>mode)

66165

+ && (register_operand (operands[0], <MODE>mode)

66166

+ || register_operand (operands[1], <MODE>mode))"

66167

+{

66168

+ return rs6000_output_move_128bit (operands);

66169

}

66170

- [(set_attr "type" "vecstore,vecload,vecsimple,vecstore,vecload,vecsimple,*,*,*,vecsimple,vecsimple,*,*,vecstore,vecload")])

66171

+ [(set_attr "type" "vecstore,vecload,vecsimple,vecstore,vecload,vecsimple,load,store,store,load, *,vecsimple,vecsimple,*, *,vecstore,vecload")

66172

+ (set_attr "length" "4,4,4,4,4,4,12,12,12,12,16,4,4,*,16,4,4")])

66173

66174

-;; Unlike other VSX moves, allow the GPRs, since a normal use of TImode is for

66175

-;; unions. However for plain data movement, slightly favor the vector loads

66176

-(define_insn "*vsx_movti"

66177

- [(set (match_operand:TI 0 "nonimmediate_operand" "=Z,wa,wa,?Y,?r,?r,wa,v,v,wZ")

66178

- (match_operand:TI 1 "input_operand" "wa,Z,wa,r,Y,r,j,W,wZ,v"))]

66179

- "VECTOR_MEM_VSX_P (TImode)

66180

+;; Unlike other VSX moves, allow the GPRs even for reloading, since a normal

66181

+;; use of TImode is for unions. However for plain data movement, slightly

66182

+;; favor the vector loads

66183

+(define_insn "*vsx_movti_64bit"

66184

+ [(set (match_operand:TI 0 "nonimmediate_operand" "=Z,wa,wa,wa,v,v,wZ,wQ,&r,Y,r,r,?r")

66185

+ (match_operand:TI 1 "input_operand" "wa,Z,wa,O,W,wZ,v,r,wQ,r,Y,r,n"))]

66186

+ "TARGET_POWERPC64 && VECTOR_MEM_VSX_P (TImode)

66187

&& (register_operand (operands[0], TImode)

66188

|| register_operand (operands[1], TImode))"

66189

{

66190

+ return rs6000_output_move_128bit (operands);

66191

+}

66192

+ [(set_attr "type" "vecstore,vecload,vecsimple,vecsimple,vecsimple,vecstore,vecload,store,load,store,load,*,*")

66193

+ (set_attr "length" "4,4,4,4,16,4,4,8,8,8,8,8,8")])

66194

+

66195

+(define_insn "*vsx_movti_32bit"

66196

+ [(set (match_operand:TI 0 "nonimmediate_operand" "=Z,wa,wa,wa,v, v,wZ,Q,Y,????r,????r,????r,r")

66197

+ (match_operand:TI 1 "input_operand" "wa, Z,wa, O,W,wZ, v,r,r, Q, Y, r,n"))]

66198

+ "! TARGET_POWERPC64 && VECTOR_MEM_VSX_P (TImode)

66199

+ && (register_operand (operands[0], TImode)

66200

+ || register_operand (operands[1], TImode))"

66201

+{

66202

switch (which_alternative)

66203

{

66204

case 0:

66205

@@ -290,27 +623,45 @@

66206

return "xxlor %x0,%x1,%x1";

66207

66208

case 3:

66209

+ return "xxlxor %x0,%x0,%x0";

66210

+

66211

case 4:

66212

+ return output_vec_const_move (operands);

66213

+

66214

case 5:

66215

- return "#";

66216

+ return "stvx %1,%y0";

66217

66218

case 6:

66219

- return "xxlxor %x0,%x0,%x0";

66220

+ return "lvx %0,%y1";

66221

66222

case 7:

66223

- return output_vec_const_move (operands);

66224

+ if (TARGET_STRING)

66225

+ return \"stswi %1,%P0,16\";

66226

66227

case 8:

66228

- return "stvx %1,%y0";

66229

+ return \"#\";

66230

66231

case 9:

66232

- return "lvx %0,%y1";

66233

+ /* If the address is not used in the output, we can use lsi. Otherwise,

66234

+ fall through to generating four loads. */

66235

+ if (TARGET_STRING

66236

+ && ! reg_overlap_mentioned_p (operands[0], operands[1]))

66237

+ return \"lswi %0,%P1,16\";

66238

+ /* ... fall through ... */

66239

66240

+ case 10:

66241

+ case 11:

66242

+ case 12:

66243

+ return \"#\";

66244

default:

66245

gcc_unreachable ();

66246

}

66247

}

66248

- [(set_attr "type" "vecstore,vecload,vecsimple,*,*,*,vecsimple,*,vecstore,vecload")])

66249

+ [(set_attr "type" "vecstore,vecload,vecsimple,vecsimple,vecsimple,vecstore,vecload,store_ux,store_ux,load_ux,load_ux, *, *")

66250

+ (set_attr "length" " 4, 4, 4, 4, 8, 4, 4, 16, 16, 16, 16,16,16")

66251

+ (set (attr "cell_micro") (if_then_else (match_test "TARGET_STRING")

66252

+ (const_string "always")

66253

+ (const_string "conditional")))])

66254

66255

;; Explicit load/store expanders for the builtin functions

66256

(define_expand "vsx_load_<mode>"

66257

@@ -320,46 +671,48 @@

66258

"")

66259

66260

(define_expand "vsx_store_<mode>"

66261

- [(set (match_operand:VEC_M 0 "memory_operand" "")

66262

- (match_operand:VEC_M 1 "vsx_register_operand" ""))]

66263

+ [(set (match_operand:VSX_M 0 "memory_operand" "")

66264

+ (match_operand:VSX_M 1 "vsx_register_operand" ""))]

66265

"VECTOR_MEM_VSX_P (<MODE>mode)"

66266

"")

66267

66268

66269

-;; VSX scalar and vector floating point arithmetic instructions

66270

+;; VSX vector floating point arithmetic instructions. The VSX scalar

66271

+;; instructions are now combined with the insn for the traditional floating

66272

+;; point unit.

66273

(define_insn "*vsx_add<mode>3"

66274

- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")

66275

- (plus:VSX_B (match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")

66276

- (match_operand:VSX_B 2 "vsx_register_operand" "<VSr>,wa")))]

66277

+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")

66278

+ (plus:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")

66279

+ (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))]

66280

"VECTOR_UNIT_VSX_P (<MODE>mode)"

66281

- "x<VSv>add<VSs> %x0,%x1,%x2"

66282

+ "xvadd<VSs> %x0,%x1,%x2"

66283

[(set_attr "type" "<VStype_simple>")

66284

(set_attr "fp_type" "<VSfptype_simple>")])

66285

66286

(define_insn "*vsx_sub<mode>3"

66287

- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")

66288

- (minus:VSX_B (match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")

66289

- (match_operand:VSX_B 2 "vsx_register_operand" "<VSr>,wa")))]

66290

+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")

66291

+ (minus:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")

66292

+ (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))]

66293

"VECTOR_UNIT_VSX_P (<MODE>mode)"

66294

- "x<VSv>sub<VSs> %x0,%x1,%x2"

66295

+ "xvsub<VSs> %x0,%x1,%x2"

66296

[(set_attr "type" "<VStype_simple>")

66297

(set_attr "fp_type" "<VSfptype_simple>")])

66298

66299

(define_insn "*vsx_mul<mode>3"

66300

- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")

66301

- (mult:VSX_B (match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")

66302

- (match_operand:VSX_B 2 "vsx_register_operand" "<VSr>,wa")))]

66303

+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")

66304

+ (mult:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")

66305

+ (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))]

66306

"VECTOR_UNIT_VSX_P (<MODE>mode)"

66307

- "x<VSv>mul<VSs> %x0,%x1,%x2"

66308

- [(set_attr "type" "<VStype_mul>")

66309

+ "xvmul<VSs> %x0,%x1,%x2"

66310

+ [(set_attr "type" "<VStype_simple>")

66311

(set_attr "fp_type" "<VSfptype_mul>")])

66312

66313

(define_insn "*vsx_div<mode>3"

66314

- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")

66315

- (div:VSX_B (match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")

66316

- (match_operand:VSX_B 2 "vsx_register_operand" "<VSr>,wa")))]

66317

+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")

66318

+ (div:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")

66319

+ (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))]

66320

"VECTOR_UNIT_VSX_P (<MODE>mode)"

66321

- "x<VSv>div<VSs> %x0,%x1,%x2"

66322

+ "xvdiv<VSs> %x0,%x1,%x2"

66323

[(set_attr "type" "<VStype_div>")

66324

(set_attr "fp_type" "<VSfptype_div>")])

66325

66326

@@ -402,94 +755,72 @@

66327

(set_attr "fp_type" "<VSfptype_simple>")])

66328

66329

(define_insn "vsx_fre<mode>2"

66330

- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")

66331

- (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")]

66332

+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")

66333

+ (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")]

66334

UNSPEC_FRES))]

66335

"VECTOR_UNIT_VSX_P (<MODE>mode)"

66336

- "x<VSv>re<VSs> %x0,%x1"

66337

+ "xvre<VSs> %x0,%x1"

66338

[(set_attr "type" "<VStype_simple>")

66339

(set_attr "fp_type" "<VSfptype_simple>")])

66340

66341

(define_insn "*vsx_neg<mode>2"

66342

- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")

66343

- (neg:VSX_B (match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")))]

66344

+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")

66345

+ (neg:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")))]

66346

"VECTOR_UNIT_VSX_P (<MODE>mode)"

66347

- "x<VSv>neg<VSs> %x0,%x1"

66348

+ "xvneg<VSs> %x0,%x1"

66349

[(set_attr "type" "<VStype_simple>")

66350

(set_attr "fp_type" "<VSfptype_simple>")])

66351

66352

(define_insn "*vsx_abs<mode>2"

66353

- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")

66354

- (abs:VSX_B (match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")))]

66355

+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")

66356

+ (abs:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")))]

66357

"VECTOR_UNIT_VSX_P (<MODE>mode)"

66358

- "x<VSv>abs<VSs> %x0,%x1"

66359

+ "xvabs<VSs> %x0,%x1"

66360

[(set_attr "type" "<VStype_simple>")

66361

(set_attr "fp_type" "<VSfptype_simple>")])

66362

66363

(define_insn "vsx_nabs<mode>2"

66364

- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")

66365

- (neg:VSX_B

66366

- (abs:VSX_B

66367

- (match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa"))))]

66368

+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")

66369

+ (neg:VSX_F

66370

+ (abs:VSX_F

66371

+ (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa"))))]

66372

"VECTOR_UNIT_VSX_P (<MODE>mode)"

66373

- "x<VSv>nabs<VSs> %x0,%x1"

66374

+ "xvnabs<VSs> %x0,%x1"

66375

[(set_attr "type" "<VStype_simple>")

66376

(set_attr "fp_type" "<VSfptype_simple>")])

66377

66378

(define_insn "vsx_smax<mode>3"

66379

- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")

66380

- (smax:VSX_B (match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")

66381

- (match_operand:VSX_B 2 "vsx_register_operand" "<VSr>,wa")))]

66382

+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")

66383

+ (smax:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")

66384

+ (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))]

66385

"VECTOR_UNIT_VSX_P (<MODE>mode)"

66386

- "x<VSv>max<VSs> %x0,%x1,%x2"

66387

+ "xvmax<VSs> %x0,%x1,%x2"

66388

[(set_attr "type" "<VStype_simple>")

66389

(set_attr "fp_type" "<VSfptype_simple>")])

66390

66391

(define_insn "*vsx_smin<mode>3"

66392

- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")

66393

- (smin:VSX_B (match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")

66394

- (match_operand:VSX_B 2 "vsx_register_operand" "<VSr>,wa")))]

66395

+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")

66396

+ (smin:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")

66397

+ (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))]

66398

"VECTOR_UNIT_VSX_P (<MODE>mode)"

66399

- "x<VSv>min<VSs> %x0,%x1,%x2"

66400

+ "xvmin<VSs> %x0,%x1,%x2"

66401

[(set_attr "type" "<VStype_simple>")

66402

(set_attr "fp_type" "<VSfptype_simple>")])

66403

66404

-;; Special VSX version of smin/smax for single precision floating point. Since

66405

-;; both numbers are rounded to single precision, we can just use the DP version

66406

-;; of the instruction.

66407

-

66408

-(define_insn "*vsx_smaxsf3"

66409

- [(set (match_operand:SF 0 "vsx_register_operand" "=f")

66410

- (smax:SF (match_operand:SF 1 "vsx_register_operand" "f")

66411

- (match_operand:SF 2 "vsx_register_operand" "f")))]

66412

- "VECTOR_UNIT_VSX_P (DFmode)"

66413

- "xsmaxdp %x0,%x1,%x2"

66414

- [(set_attr "type" "fp")

66415

- (set_attr "fp_type" "fp_addsub_d")])

66416

-

66417

-(define_insn "*vsx_sminsf3"

66418

- [(set (match_operand:SF 0 "vsx_register_operand" "=f")

66419

- (smin:SF (match_operand:SF 1 "vsx_register_operand" "f")

66420

- (match_operand:SF 2 "vsx_register_operand" "f")))]

66421

- "VECTOR_UNIT_VSX_P (DFmode)"

66422

- "xsmindp %x0,%x1,%x2"

66423

- [(set_attr "type" "fp")

66424

- (set_attr "fp_type" "fp_addsub_d")])

66425

-

66426

(define_insn "*vsx_sqrt<mode>2"

66427

- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")

66428

- (sqrt:VSX_B (match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")))]

66429

+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")

66430

+ (sqrt:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")))]

66431

"VECTOR_UNIT_VSX_P (<MODE>mode)"

66432

- "x<VSv>sqrt<VSs> %x0,%x1"

66433

+ "xvsqrt<VSs> %x0,%x1"

66434

[(set_attr "type" "<VStype_sqrt>")

66435

(set_attr "fp_type" "<VSfptype_sqrt>")])

66436

66437

(define_insn "*vsx_rsqrte<mode>2"

66438

- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")

66439

- (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")]

66440

+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")

66441

+ (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")]

66442

UNSPEC_RSQRT))]

66443

"VECTOR_UNIT_VSX_P (<MODE>mode)"

66444

- "x<VSv>rsqrte<VSs> %x0,%x1"

66445

+ "xvrsqrte<VSs> %x0,%x1"

66446

[(set_attr "type" "<VStype_simple>")

66447

(set_attr "fp_type" "<VSfptype_simple>")])

66448

66449

@@ -528,27 +859,11 @@

66450

[(set_attr "type" "<VStype_simple>")

66451

(set_attr "fp_type" "<VSfptype_simple>")])

66452

66453

-;; Fused vector multiply/add instructions Support the classical DF versions of

66454

-;; fma, which allows the target to be a separate register from the 3 inputs.

66455

-;; Under VSX, the target must be either the addend or the first multiply.

66456

-;; Where we can, also do the same for the Altivec V4SF fmas.

66457

+;; Fused vector multiply/add instructions. Support the classical Altivec

66458

+;; versions of fma, which allows the target to be a separate register from the

66459

+;; 3 inputs. Under VSX, the target must be either the addend or the first

66460

+;; multiply.

66461

66462

-(define_insn "*vsx_fmadf4"

66463

- [(set (match_operand:DF 0 "vsx_register_operand" "=ws,ws,?wa,?wa,d")

66464

- (fma:DF

66465

- (match_operand:DF 1 "vsx_register_operand" "%ws,ws,wa,wa,d")

66466

- (match_operand:DF 2 "vsx_register_operand" "ws,0,wa,0,d")

66467

- (match_operand:DF 3 "vsx_register_operand" "0,ws,0,wa,d")))]

66468

- "VECTOR_UNIT_VSX_P (DFmode)"

66469

- "@

66470

- xsmaddadp %x0,%x1,%x2

66471

- xsmaddmdp %x0,%x1,%x3

66472

- xsmaddadp %x0,%x1,%x2

66473

- xsmaddmdp %x0,%x1,%x3

66474

- fmadd %0,%1,%2,%3"

66475

- [(set_attr "type" "fp")

66476

- (set_attr "fp_type" "fp_maddsub_d")])

66477

-

66478

(define_insn "*vsx_fmav4sf4"

66479

[(set (match_operand:V4SF 0 "vsx_register_operand" "=ws,ws,?wa,?wa,v")

66480

(fma:V4SF

66481

@@ -578,23 +893,6 @@

66482

xvmaddmdp %x0,%x1,%x3"

66483

[(set_attr "type" "vecdouble")])

66484

66485

-(define_insn "*vsx_fmsdf4"

66486

- [(set (match_operand:DF 0 "vsx_register_operand" "=ws,ws,?wa,?wa,d")

66487

- (fma:DF

66488

- (match_operand:DF 1 "vsx_register_operand" "%ws,ws,wa,wa,d")

66489

- (match_operand:DF 2 "vsx_register_operand" "ws,0,wa,0,d")

66490

- (neg:DF

66491

- (match_operand:DF 3 "vsx_register_operand" "0,ws,0,wa,d"))))]

66492

- "VECTOR_UNIT_VSX_P (DFmode)"

66493

- "@

66494

- xsmsubadp %x0,%x1,%x2

66495

- xsmsubmdp %x0,%x1,%x3

66496

- xsmsubadp %x0,%x1,%x2

66497

- xsmsubmdp %x0,%x1,%x3

66498

- fmsub %0,%1,%2,%3"

66499

- [(set_attr "type" "fp")

66500

- (set_attr "fp_type" "fp_maddsub_d")])

66501

-

66502

(define_insn "*vsx_fms<mode>4"

66503

[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,<VSr>,?wa,?wa")

66504

(fma:VSX_F

66505

@@ -604,29 +902,12 @@

66506

(match_operand:VSX_F 3 "vsx_register_operand" "0,<VSr>,0,wa"))))]

66507

"VECTOR_UNIT_VSX_P (<MODE>mode)"

66508

"@

66509

- x<VSv>msuba<VSs> %x0,%x1,%x2

66510

- x<VSv>msubm<VSs> %x0,%x1,%x3

66511

- x<VSv>msuba<VSs> %x0,%x1,%x2

66512

- x<VSv>msubm<VSs> %x0,%x1,%x3"

66513

+ xvmsuba<VSs> %x0,%x1,%x2

66514

+ xvmsubm<VSs> %x0,%x1,%x3

66515

+ xvmsuba<VSs> %x0,%x1,%x2

66516

+ xvmsubm<VSs> %x0,%x1,%x3"

66517

[(set_attr "type" "<VStype_mul>")])

66518

66519

-(define_insn "*vsx_nfmadf4"

66520

- [(set (match_operand:DF 0 "vsx_register_operand" "=ws,ws,?wa,?wa,d")

66521

- (neg:DF

66522

- (fma:DF

66523

- (match_operand:DF 1 "vsx_register_operand" "ws,ws,wa,wa,d")

66524

- (match_operand:DF 2 "vsx_register_operand" "ws,0,wa,0,d")

66525

- (match_operand:DF 3 "vsx_register_operand" "0,ws,0,wa,d"))))]

66526

- "VECTOR_UNIT_VSX_P (DFmode)"

66527

- "@

66528

- xsnmaddadp %x0,%x1,%x2

66529

- xsnmaddmdp %x0,%x1,%x3

66530

- xsnmaddadp %x0,%x1,%x2

66531

- xsnmaddmdp %x0,%x1,%x3

66532

- fnmadd %0,%1,%2,%3"

66533

- [(set_attr "type" "fp")

66534

- (set_attr "fp_type" "fp_maddsub_d")])

66535

-

66536

(define_insn "*vsx_nfma<mode>4"

66537

[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,<VSr>,?wa,?wa")

66538

(neg:VSX_F

66539

@@ -636,31 +917,13 @@

66540

(match_operand:VSX_F 3 "vsx_register_operand" "0,<VSr>,0,wa"))))]

66541

"VECTOR_UNIT_VSX_P (<MODE>mode)"

66542

"@

66543

- x<VSv>nmadda<VSs> %x0,%x1,%x2

66544

- x<VSv>nmaddm<VSs> %x0,%x1,%x3

66545

- x<VSv>nmadda<VSs> %x0,%x1,%x2

66546

- x<VSv>nmaddm<VSs> %x0,%x1,%x3"

66547

+ xvnmadda<VSs> %x0,%x1,%x2

66548

+ xvnmaddm<VSs> %x0,%x1,%x3

66549

+ xvnmadda<VSs> %x0,%x1,%x2

66550

+ xvnmaddm<VSs> %x0,%x1,%x3"

66551

[(set_attr "type" "<VStype_mul>")

66552

(set_attr "fp_type" "<VSfptype_mul>")])

66553

66554

-(define_insn "*vsx_nfmsdf4"

66555

- [(set (match_operand:DF 0 "vsx_register_operand" "=ws,ws,?wa,?wa,d")

66556

- (neg:DF

66557

- (fma:DF

66558

- (match_operand:DF 1 "vsx_register_operand" "%ws,ws,wa,wa,d")

66559

- (match_operand:DF 2 "vsx_register_operand" "ws,0,wa,0,d")

66560

- (neg:DF

66561

- (match_operand:DF 3 "vsx_register_operand" "0,ws,0,wa,d")))))]

66562

- "VECTOR_UNIT_VSX_P (DFmode)"

66563

- "@

66564

- xsnmsubadp %x0,%x1,%x2

66565

- xsnmsubmdp %x0,%x1,%x3

66566

- xsnmsubadp %x0,%x1,%x2

66567

- xsnmsubmdp %x0,%x1,%x3

66568

- fnmsub %0,%1,%2,%3"

66569

- [(set_attr "type" "fp")

66570

- (set_attr "fp_type" "fp_maddsub_d")])

66571

-

66572

(define_insn "*vsx_nfmsv4sf4"

66573

[(set (match_operand:V4SF 0 "vsx_register_operand" "=wf,wf,?wa,?wa,v")

66574

(neg:V4SF

66575

@@ -722,16 +985,6 @@

66576

[(set_attr "type" "<VStype_simple>")

66577

(set_attr "fp_type" "<VSfptype_simple>")])

66578

66579

-;; Floating point scalar compare

66580

-(define_insn "*vsx_cmpdf_internal1"

66581

- [(set (match_operand:CCFP 0 "cc_reg_operand" "=y,?y")

66582

- (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "ws,wa")

66583

- (match_operand:DF 2 "gpc_reg_operand" "ws,wa")))]

66584

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT

66585

- && VECTOR_UNIT_VSX_P (DFmode)"

66586

- "xscmpudp %0,%x1,%x2"

66587

- [(set_attr "type" "fpcompare")])

66588

-

66589

;; Compare vectors producing a vector result and a predicate, setting CR6 to

66590

;; indicate a combined status

66591

(define_insn "*vsx_eq_<mode>_p"

66592

@@ -798,13 +1051,13 @@

66593

66594

;; Copy sign

66595

(define_insn "vsx_copysign<mode>3"

66596

- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")

66597

- (unspec:VSX_B

66598

- [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")

66599

- (match_operand:VSX_B 2 "vsx_register_operand" "<VSr>,wa")]

66600

+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")

66601

+ (unspec:VSX_F

66602

+ [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")

66603

+ (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")]

66604

UNSPEC_COPYSIGN))]

66605

"VECTOR_UNIT_VSX_P (<MODE>mode)"

66606

- "x<VSv>cpsgn<VSs> %x0,%x2,%x1"

66607

+ "xvcpsgn<VSs> %x0,%x2,%x1"

66608

[(set_attr "type" "<VStype_simple>")

66609

(set_attr "fp_type" "<VSfptype_simple>")])

66610

66611

@@ -865,10 +1118,10 @@

66612

(set_attr "fp_type" "<VSfptype_simple>")])

66613

66614

(define_insn "vsx_btrunc<mode>2"

66615

- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")

66616

- (fix:VSX_B (match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")))]

66617

+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")

66618

+ (fix:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")))]

66619

"VECTOR_UNIT_VSX_P (<MODE>mode)"

66620

- "x<VSv>r<VSs>iz %x0,%x1"

66621

+ "xvr<VSs>iz %x0,%x1"

66622

[(set_attr "type" "<VStype_simple>")

66623

(set_attr "fp_type" "<VSfptype_simple>")])

66624

66625

@@ -882,20 +1135,20 @@

66626

(set_attr "fp_type" "<VSfptype_simple>")])

66627

66628

(define_insn "vsx_floor<mode>2"

66629

- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")

66630

- (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")]

66631

+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")

66632

+ (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")]

66633

UNSPEC_FRIM))]

66634

"VECTOR_UNIT_VSX_P (<MODE>mode)"

66635

- "x<VSv>r<VSs>im %x0,%x1"

66636

+ "xvr<VSs>im %x0,%x1"

66637

[(set_attr "type" "<VStype_simple>")

66638

(set_attr "fp_type" "<VSfptype_simple>")])

66639

66640

(define_insn "vsx_ceil<mode>2"

66641

- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")

66642

- (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")]

66643

+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")

66644

+ (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")]

66645

UNSPEC_FRIP))]

66646

"VECTOR_UNIT_VSX_P (<MODE>mode)"

66647

- "x<VSv>r<VSs>ip %x0,%x1"

66648

+ "xvr<VSs>ip %x0,%x1"

66649

[(set_attr "type" "<VStype_simple>")

66650

(set_attr "fp_type" "<VSfptype_simple>")])

66651

66652

@@ -942,6 +1195,40 @@

66653

"xscvspdp %x0,%x1"

66654

[(set_attr "type" "fp")])

66655

66656

+;; ISA 2.07 xscvdpspn/xscvspdpn that does not raise an error on signalling NaNs

66657

+(define_insn "vsx_xscvdpspn"

66658

+ [(set (match_operand:V4SF 0 "vsx_register_operand" "=ws,?wa")

66659

+ (unspec:V4SF [(match_operand:DF 1 "vsx_register_operand" "wd,wa")]

66660

+ UNSPEC_VSX_CVDPSPN))]

66661

+ "TARGET_XSCVDPSPN"

66662

+ "xscvdpspn %x0,%x1"

66663

+ [(set_attr "type" "fp")])

66664

+

66665

+(define_insn "vsx_xscvspdpn"

66666

+ [(set (match_operand:DF 0 "vsx_register_operand" "=ws,?wa")

66667

+ (unspec:DF [(match_operand:V4SF 1 "vsx_register_operand" "wa,wa")]

66668

+ UNSPEC_VSX_CVSPDPN))]

66669

+ "TARGET_XSCVSPDPN"

66670

+ "xscvspdpn %x0,%x1"

66671

+ [(set_attr "type" "fp")])

66672

+

66673

+(define_insn "vsx_xscvdpspn_scalar"

66674

+ [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa")

66675

+ (unspec:V4SF [(match_operand:SF 1 "vsx_register_operand" "f")]

66676

+ UNSPEC_VSX_CVDPSPN))]

66677

+ "TARGET_XSCVDPSPN"

66678

+ "xscvdpspn %x0,%x1"

66679

+ [(set_attr "type" "fp")])

66680

+

66681

+;; Used by direct move to move a SFmode value from GPR to VSX register

66682

+(define_insn "vsx_xscvspdpn_directmove"

66683

+ [(set (match_operand:SF 0 "vsx_register_operand" "=wa")

66684

+ (unspec:SF [(match_operand:SF 1 "vsx_register_operand" "wa")]

66685

+ UNSPEC_VSX_CVSPDPN))]

66686

+ "TARGET_XSCVSPDPN"

66687

+ "xscvspdpn %x0,%x1"

66688

+ [(set_attr "type" "fp")])

66689

+

66690

;; Convert from 64-bit to 32-bit types

66691

;; Note, favor the Altivec registers since the usual use of these instructions

66692

;; is in vector converts and we need to use the Altivec vperm instruction.

66693

@@ -1027,73 +1314,21 @@

66694

(set_attr "fp_type" "<VSfptype_simple>")])

66695

66696

66697

-;; Logical and permute operations

66698

-(define_insn "*vsx_and<mode>3"

66699

- [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?wa")

66700

- (and:VSX_L

66701

- (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,?wa")

66702

- (match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,?wa")))]

66703

- "VECTOR_MEM_VSX_P (<MODE>mode)"

66704

- "xxland %x0,%x1,%x2"

66705

- [(set_attr "type" "vecsimple")])

66706

-

66707

-(define_insn "*vsx_ior<mode>3"

66708

- [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?wa")

66709

- (ior:VSX_L (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,?wa")

66710

- (match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,?wa")))]

66711

- "VECTOR_MEM_VSX_P (<MODE>mode)"

66712

- "xxlor %x0,%x1,%x2"

66713

- [(set_attr "type" "vecsimple")])

66714

-

66715

-(define_insn "*vsx_xor<mode>3"

66716

- [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?wa")

66717

- (xor:VSX_L

66718

- (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,?wa")

66719

- (match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,?wa")))]

66720

- "VECTOR_MEM_VSX_P (<MODE>mode)"

66721

- "xxlxor %x0,%x1,%x2"

66722

- [(set_attr "type" "vecsimple")])

66723

-

66724

-(define_insn "*vsx_one_cmpl<mode>2"

66725

- [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?wa")

66726

- (not:VSX_L

66727

- (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,?wa")))]

66728

- "VECTOR_MEM_VSX_P (<MODE>mode)"

66729

- "xxlnor %x0,%x1,%x1"

66730

- [(set_attr "type" "vecsimple")])

66731

-

66732

-(define_insn "*vsx_nor<mode>3"

66733

- [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?wa")

66734

- (not:VSX_L

66735

- (ior:VSX_L

66736

- (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,?wa")

66737

- (match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,?wa"))))]

66738

- "VECTOR_MEM_VSX_P (<MODE>mode)"

66739

- "xxlnor %x0,%x1,%x2"

66740

- [(set_attr "type" "vecsimple")])

66741

-

66742

-(define_insn "*vsx_andc<mode>3"

66743

- [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?wa")

66744

- (and:VSX_L

66745

- (not:VSX_L

66746

- (match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,?wa"))

66747

- (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,?wa")))]

66748

- "VECTOR_MEM_VSX_P (<MODE>mode)"

66749

- "xxlandc %x0,%x1,%x2"

66750

- [(set_attr "type" "vecsimple")])

66751

-

66752

-

66753

;; Permute operations

66754

66755

;; Build a V2DF/V2DI vector from two scalars

66756

(define_insn "vsx_concat_<mode>"

66757

- [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wd,?wa")

66758

- (unspec:VSX_D

66759

- [(match_operand:<VS_scalar> 1 "vsx_register_operand" "ws,wa")

66760

- (match_operand:<VS_scalar> 2 "vsx_register_operand" "ws,wa")]

66761

- UNSPEC_VSX_CONCAT))]

66762

+ [(set (match_operand:VSX_D 0 "vsx_register_operand" "=<VSr>,?wa")

66763

+ (vec_concat:VSX_D

66764

+ (match_operand:<VS_scalar> 1 "vsx_register_operand" "ws,wa")

66765

+ (match_operand:<VS_scalar> 2 "vsx_register_operand" "ws,wa")))]

66766

"VECTOR_MEM_VSX_P (<MODE>mode)"

66767

- "xxpermdi %x0,%x1,%x2,0"

66768

+{

66769

+ if (BYTES_BIG_ENDIAN)

66770

+ return "xxpermdi %x0,%x1,%x2,0";

66771

+ else

66772

+ return "xxpermdi %x0,%x2,%x1,0";

66773

+}

66774

[(set_attr "type" "vecperm")])

66775

66776

;; Special purpose concat using xxpermdi to glue two single precision values

66777

@@ -1106,9 +1341,176 @@

66778

(match_operand:SF 2 "vsx_register_operand" "f,f")]

66779

UNSPEC_VSX_CONCAT))]

66780

"VECTOR_MEM_VSX_P (V2DFmode)"

66781

- "xxpermdi %x0,%x1,%x2,0"

66782

+{

66783

+ if (BYTES_BIG_ENDIAN)

66784

+ return "xxpermdi %x0,%x1,%x2,0";

66785

+ else

66786

+ return "xxpermdi %x0,%x2,%x1,0";

66787

+}

66788

[(set_attr "type" "vecperm")])

66789

66790

+;; xxpermdi for little endian loads and stores. We need several of

66791

+;; these since the form of the PARALLEL differs by mode.

66792

+(define_insn "*vsx_xxpermdi2_le_<mode>"

66793

+ [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wa")

66794

+ (vec_select:VSX_D

66795

+ (match_operand:VSX_D 1 "vsx_register_operand" "wa")

66796

+ (parallel [(const_int 1) (const_int 0)])))]

66797

+ "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode)"

66798

+ "xxpermdi %x0,%x1,%x1,2"

66799

+ [(set_attr "type" "vecperm")])

66800

+

66801

+(define_insn "*vsx_xxpermdi4_le_<mode>"

66802

+ [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa")

66803

+ (vec_select:VSX_W

66804

+ (match_operand:VSX_W 1 "vsx_register_operand" "wa")

66805

+ (parallel [(const_int 2) (const_int 3)

66806

+ (const_int 0) (const_int 1)])))]

66807

+ "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode)"

66808

+ "xxpermdi %x0,%x1,%x1,2"

66809

+ [(set_attr "type" "vecperm")])

66810

+

66811

+(define_insn "*vsx_xxpermdi8_le_V8HI"

66812

+ [(set (match_operand:V8HI 0 "vsx_register_operand" "=wa")

66813

+ (vec_select:V8HI

66814

+ (match_operand:V8HI 1 "vsx_register_operand" "wa")

66815

+ (parallel [(const_int 4) (const_int 5)

66816

+ (const_int 6) (const_int 7)

66817

+ (const_int 0) (const_int 1)

66818

+ (const_int 2) (const_int 3)])))]

66819

+ "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (V8HImode)"

66820

+ "xxpermdi %x0,%x1,%x1,2"

66821

+ [(set_attr "type" "vecperm")])

66822

+

66823

+(define_insn "*vsx_xxpermdi16_le_V16QI"

66824

+ [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa")

66825

+ (vec_select:V16QI

66826

+ (match_operand:V16QI 1 "vsx_register_operand" "wa")

66827

+ (parallel [(const_int 8) (const_int 9)

66828

+ (const_int 10) (const_int 11)

66829

+ (const_int 12) (const_int 13)

66830

+ (const_int 14) (const_int 15)

66831

+ (const_int 0) (const_int 1)

66832

+ (const_int 2) (const_int 3)

66833

+ (const_int 4) (const_int 5)

66834

+ (const_int 6) (const_int 7)])))]

66835

+ "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (V16QImode)"

66836

+ "xxpermdi %x0,%x1,%x1,2"

66837

+ [(set_attr "type" "vecperm")])

66838

+

66839

+;; lxvd2x for little endian loads. We need several of

66840

+;; these since the form of the PARALLEL differs by mode.

66841

+(define_insn "*vsx_lxvd2x2_le_<mode>"

66842

+ [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wa")

66843

+ (vec_select:VSX_D

66844

+ (match_operand:VSX_D 1 "memory_operand" "Z")

66845

+ (parallel [(const_int 1) (const_int 0)])))]

66846

+ "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode)"

66847

+ "lxvd2x %x0,%y1"

66848

+ [(set_attr "type" "vecload")])

66849

+

66850

+(define_insn "*vsx_lxvd2x4_le_<mode>"

66851

+ [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa")

66852

+ (vec_select:VSX_W

66853

+ (match_operand:VSX_W 1 "memory_operand" "Z")

66854

+ (parallel [(const_int 2) (const_int 3)

66855

+ (const_int 0) (const_int 1)])))]

66856

+ "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode)"

66857

+ "lxvd2x %x0,%y1"

66858

+ [(set_attr "type" "vecload")])

66859

+

66860

+(define_insn "*vsx_lxvd2x8_le_V8HI"

66861

+ [(set (match_operand:V8HI 0 "vsx_register_operand" "=wa")

66862

+ (vec_select:V8HI

66863

+ (match_operand:V8HI 1 "memory_operand" "Z")

66864

+ (parallel [(const_int 4) (const_int 5)

66865

+ (const_int 6) (const_int 7)

66866

+ (const_int 0) (const_int 1)

66867

+ (const_int 2) (const_int 3)])))]

66868

+ "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (V8HImode)"

66869

+ "lxvd2x %x0,%y1"

66870

+ [(set_attr "type" "vecload")])

66871

+

66872

+(define_insn "*vsx_lxvd2x16_le_V16QI"

66873

+ [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa")

66874

+ (vec_select:V16QI

66875

+ (match_operand:V16QI 1 "memory_operand" "Z")

66876

+ (parallel [(const_int 8) (const_int 9)

66877

+ (const_int 10) (const_int 11)

66878

+ (const_int 12) (const_int 13)

66879

+ (const_int 14) (const_int 15)

66880

+ (const_int 0) (const_int 1)

66881

+ (const_int 2) (const_int 3)

66882

+ (const_int 4) (const_int 5)

66883

+ (const_int 6) (const_int 7)])))]

66884

+ "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (V16QImode)"

66885

+ "lxvd2x %x0,%y1"

66886

+ [(set_attr "type" "vecload")])

66887

+

66888

+;; stxvd2x for little endian stores. We need several of

66889

+;; these since the form of the PARALLEL differs by mode.

66890

+(define_insn "*vsx_stxvd2x2_le_<mode>"

66891

+ [(set (match_operand:VSX_D 0 "memory_operand" "=Z")

66892

+ (vec_select:VSX_D

66893

+ (match_operand:VSX_D 1 "vsx_register_operand" "wa")

66894

+ (parallel [(const_int 1) (const_int 0)])))]

66895

+ "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode)"

66896

+ "stxvd2x %x1,%y0"

66897

+ [(set_attr "type" "vecstore")])

66898

+

66899

+(define_insn "*vsx_stxvd2x4_le_<mode>"

66900

+ [(set (match_operand:VSX_W 0 "memory_operand" "=Z")

66901

+ (vec_select:VSX_W

66902

+ (match_operand:VSX_W 1 "vsx_register_operand" "wa")

66903

+ (parallel [(const_int 2) (const_int 3)

66904

+ (const_int 0) (const_int 1)])))]

66905

+ "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode)"

66906

+ "stxvd2x %x1,%y0"

66907

+ [(set_attr "type" "vecstore")])

66908

+

66909

+(define_insn "*vsx_stxvd2x8_le_V8HI"

66910

+ [(set (match_operand:V8HI 0 "memory_operand" "=Z")

66911

+ (vec_select:V8HI

66912

+ (match_operand:V8HI 1 "vsx_register_operand" "wa")

66913

+ (parallel [(const_int 4) (const_int 5)

66914

+ (const_int 6) (const_int 7)

66915

+ (const_int 0) (const_int 1)

66916

+ (const_int 2) (const_int 3)])))]

66917

+ "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (V8HImode)"

66918

+ "stxvd2x %x1,%y0"

66919

+ [(set_attr "type" "vecstore")])

66920

+

66921

+(define_insn "*vsx_stxvd2x16_le_V16QI"

66922

+ [(set (match_operand:V16QI 0 "memory_operand" "=Z")

66923

+ (vec_select:V16QI

66924

+ (match_operand:V16QI 1 "vsx_register_operand" "wa")

66925

+ (parallel [(const_int 8) (const_int 9)

66926

+ (const_int 10) (const_int 11)

66927

+ (const_int 12) (const_int 13)

66928

+ (const_int 14) (const_int 15)

66929

+ (const_int 0) (const_int 1)

66930

+ (const_int 2) (const_int 3)

66931

+ (const_int 4) (const_int 5)

66932

+ (const_int 6) (const_int 7)])))]

66933

+ "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (V16QImode)"

66934

+ "stxvd2x %x1,%y0"

66935

+ [(set_attr "type" "vecstore")])

66936

+

66937

+;; Convert a TImode value into V1TImode

66938

+(define_expand "vsx_set_v1ti"

66939

+ [(match_operand:V1TI 0 "nonimmediate_operand" "")

66940

+ (match_operand:V1TI 1 "nonimmediate_operand" "")

66941

+ (match_operand:TI 2 "input_operand" "")

66942

+ (match_operand:QI 3 "u5bit_cint_operand" "")]

66943

+ "VECTOR_MEM_VSX_P (V1TImode)"

66944

+{

66945

+ if (operands[3] != const0_rtx)

66946

+ gcc_unreachable ();

66947

+

66948

+ emit_move_insn (operands[0], gen_lowpart (V1TImode, operands[1]));

66949

+ DONE;

66950

+})

66951

+

66952

;; Set the element of a V2DI/VD2F mode

66953

(define_insn "vsx_set_<mode>"

66954

[(set (match_operand:VSX_D 0 "vsx_register_operand" "=wd,?wa")

66955

@@ -1118,9 +1520,10 @@

66956

UNSPEC_VSX_SET))]

66957

"VECTOR_MEM_VSX_P (<MODE>mode)"

66958

{

66959

- if (INTVAL (operands[3]) == 0)

66960

+ int idx_first = BYTES_BIG_ENDIAN ? 0 : 1;

66961

+ if (INTVAL (operands[3]) == idx_first)

66962

return \"xxpermdi %x0,%x2,%x1,1\";

66963

- else if (INTVAL (operands[3]) == 1)

66964

+ else if (INTVAL (operands[3]) == 1 - idx_first)

66965

return \"xxpermdi %x0,%x1,%x2,0\";

66966

else

66967

gcc_unreachable ();

66968

@@ -1135,8 +1538,12 @@

66969

[(match_operand:QI 2 "u5bit_cint_operand" "i,i,i")])))]

66970

"VECTOR_MEM_VSX_P (<MODE>mode)"

66971

{

66972

+ int fldDM;

66973

gcc_assert (UINTVAL (operands[2]) <= 1);

66974

- operands[3] = GEN_INT (INTVAL (operands[2]) << 1);

66975

+ fldDM = INTVAL (operands[2]) << 1;

66976

+ if (!BYTES_BIG_ENDIAN)

66977

+ fldDM = 3 - fldDM;

66978

+ operands[3] = GEN_INT (fldDM);

66979

return \"xxpermdi %x0,%x1,%x1,%3\";

66980

}

66981

[(set_attr "type" "vecperm")])

66982

@@ -1149,9 +1556,28 @@

66983

(parallel [(const_int 0)])))]

66984

"VECTOR_MEM_VSX_P (<MODE>mode) && WORDS_BIG_ENDIAN"

66985

"lxsd%U1x %x0,%y1"

66986

- [(set_attr "type" "fpload")

66987

+ [(set (attr "type")

66988

+ (if_then_else

66989

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

66990

+ (const_string "fpload_ux")

66991

+ (const_string "fpload")))

66992

(set_attr "length" "4")])

66993

66994

+;; Optimize extracting element 1 from memory for little endian

66995

+(define_insn "*vsx_extract_<mode>_one_le"

66996

+ [(set (match_operand:<VS_scalar> 0 "vsx_register_operand" "=ws,d,?wa")

66997

+ (vec_select:<VS_scalar>

66998

+ (match_operand:VSX_D 1 "indexed_or_indirect_operand" "Z,Z,Z")

66999

+ (parallel [(const_int 1)])))]

67000

+ "VECTOR_MEM_VSX_P (<MODE>mode) && !WORDS_BIG_ENDIAN"

67001

+ "lxsd%U1x %x0,%y1"

67002

+ [(set (attr "type")

67003

+ (if_then_else

67004

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

67005

+ (const_string "fpload_ux")

67006

+ (const_string "fpload")))

67007

+ (set_attr "length" "4")])

67008

+

67009

;; Extract a SF element from V4SF

67010

(define_insn_and_split "vsx_extract_v4sf"

67011

[(set (match_operand:SF 0 "vsx_register_operand" "=f,f")

67012

@@ -1172,7 +1598,7 @@

67013

rtx op2 = operands[2];

67014

rtx op3 = operands[3];

67015

rtx tmp;

67016

- HOST_WIDE_INT ele = INTVAL (op2);

67017

+ HOST_WIDE_INT ele = BYTES_BIG_ENDIAN ? INTVAL (op2) : 3 - INTVAL (op2);

67018

67019

if (ele == 0)

67020

tmp = op1;

67021

@@ -1213,11 +1639,22 @@

67022

if (<MODE>mode != V2DImode)

67023

{

67024

target = gen_lowpart (V2DImode, target);

67025

- op0 = gen_lowpart (V2DImode, target);

67026

- op1 = gen_lowpart (V2DImode, target);

67027

+ op0 = gen_lowpart (V2DImode, op0);

67028

+ op1 = gen_lowpart (V2DImode, op1);

67029

}

67030

}

67031

- emit_insn (gen (target, op0, op1, perm0, perm1));

67032

+ /* In little endian mode, vsx_xxpermdi2_<mode>_1 will perform a

67033

+ transformation we don't want; it is necessary for

67034

+ rs6000_expand_vec_perm_const_1 but not for this use. So we

67035

+ prepare for that by reversing the transformation here. */

67036

+ if (BYTES_BIG_ENDIAN)

67037

+ emit_insn (gen (target, op0, op1, perm0, perm1));

67038

+ else

67039

+ {

67040

+ rtx p0 = GEN_INT (3 - INTVAL (perm1));

67041

+ rtx p1 = GEN_INT (3 - INTVAL (perm0));

67042

+ emit_insn (gen (target, op1, op0, p0, p1));

67043

+ }

67044

DONE;

67045

})

67046

67047

@@ -1231,9 +1668,32 @@

67048

(match_operand 4 "const_2_to_3_operand" "")])))]

67049

"VECTOR_MEM_VSX_P (<MODE>mode)"

67050

{

67051

- int mask = (INTVAL (operands[3]) << 1) | (INTVAL (operands[4]) - 2);

67052

+ int op3, op4, mask;

67053

+

67054

+ /* For little endian, swap operands and invert/swap selectors

67055

+ to get the correct xxpermdi. The operand swap sets up the

67056

+ inputs as a little endian array. The selectors are swapped

67057

+ because they are defined to use big endian ordering. The

67058

+ selectors are inverted to get the correct doublewords for

67059

+ little endian ordering. */

67060

+ if (BYTES_BIG_ENDIAN)

67061

+ {

67062

+ op3 = INTVAL (operands[3]);

67063

+ op4 = INTVAL (operands[4]);

67064

+ }

67065

+ else

67066

+ {

67067

+ op3 = 3 - INTVAL (operands[4]);

67068

+ op4 = 3 - INTVAL (operands[3]);

67069

+ }

67070

+

67071

+ mask = (op3 << 1) | (op4 - 2);

67072

operands[3] = GEN_INT (mask);

67073

- return "xxpermdi %x0,%x1,%x2,%3";

67074

+

67075

+ if (BYTES_BIG_ENDIAN)

67076

+ return "xxpermdi %x0,%x1,%x2,%3";

67077

+ else

67078

+ return "xxpermdi %x0,%x2,%x1,%3";

67079

}

67080

[(set_attr "type" "vecperm")])

67081

67082

@@ -1252,25 +1712,57 @@

67083

67084

;; Expanders for builtins

67085

(define_expand "vsx_mergel_<mode>"

67086

- [(set (match_operand:VSX_D 0 "vsx_register_operand" "")

67087

- (vec_select:VSX_D

67088

- (vec_concat:<VS_double>

67089

- (match_operand:VSX_D 1 "vsx_register_operand" "")

67090

- (match_operand:VSX_D 2 "vsx_register_operand" ""))

67091

- (parallel [(const_int 1) (const_int 3)])))]

67092

+ [(use (match_operand:VSX_D 0 "vsx_register_operand" ""))

67093

+ (use (match_operand:VSX_D 1 "vsx_register_operand" ""))

67094

+ (use (match_operand:VSX_D 2 "vsx_register_operand" ""))]

67095

"VECTOR_MEM_VSX_P (<MODE>mode)"

67096

- "")

67097

+{

67098

+ rtvec v;

67099

+ rtx x;

67100

67101

+ /* Special handling for LE with -maltivec=be. */

67102

+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)

67103

+ {

67104

+ v = gen_rtvec (2, GEN_INT (0), GEN_INT (2));

67105

+ x = gen_rtx_VEC_CONCAT (<VS_double>mode, operands[2], operands[1]);

67106

+ }

67107

+ else

67108

+ {

67109

+ v = gen_rtvec (2, GEN_INT (1), GEN_INT (3));

67110

+ x = gen_rtx_VEC_CONCAT (<VS_double>mode, operands[1], operands[2]);

67111

+ }

67112

+

67113

+ x = gen_rtx_VEC_SELECT (<MODE>mode, x, gen_rtx_PARALLEL (VOIDmode, v));

67114

+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));

67115

+ DONE;

67116

+})

67117

+

67118

(define_expand "vsx_mergeh_<mode>"

67119

- [(set (match_operand:VSX_D 0 "vsx_register_operand" "")

67120

- (vec_select:VSX_D

67121

- (vec_concat:<VS_double>

67122

- (match_operand:VSX_D 1 "vsx_register_operand" "")

67123

- (match_operand:VSX_D 2 "vsx_register_operand" ""))

67124

- (parallel [(const_int 0) (const_int 2)])))]

67125

+ [(use (match_operand:VSX_D 0 "vsx_register_operand" ""))

67126

+ (use (match_operand:VSX_D 1 "vsx_register_operand" ""))

67127

+ (use (match_operand:VSX_D 2 "vsx_register_operand" ""))]

67128

"VECTOR_MEM_VSX_P (<MODE>mode)"

67129

- "")

67130

+{

67131

+ rtvec v;

67132

+ rtx x;

67133

67134

+ /* Special handling for LE with -maltivec=be. */

67135

+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)

67136

+ {

67137

+ v = gen_rtvec (2, GEN_INT (1), GEN_INT (3));

67138

+ x = gen_rtx_VEC_CONCAT (<VS_double>mode, operands[2], operands[1]);

67139

+ }

67140

+ else

67141

+ {

67142

+ v = gen_rtvec (2, GEN_INT (0), GEN_INT (2));

67143

+ x = gen_rtx_VEC_CONCAT (<VS_double>mode, operands[1], operands[2]);

67144

+ }

67145

+

67146

+ x = gen_rtx_VEC_SELECT (<MODE>mode, x, gen_rtx_PARALLEL (VOIDmode, v));

67147

+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));

67148

+ DONE;

67149

+})

67150

+

67151

;; V2DF/V2DI splat

67152

(define_insn "vsx_splat_<mode>"

67153

[(set (match_operand:VSX_D 0 "vsx_register_operand" "=wd,wd,wd,?wa,?wa,?wa")

67154

@@ -1295,6 +1787,20 @@

67155

(parallel

67156

[(match_operand:QI 2 "u5bit_cint_operand" "i,i")]))))]

67157

"VECTOR_MEM_VSX_P (<MODE>mode)"

67158

+{

67159

+ if (!BYTES_BIG_ENDIAN)

67160

+ operands[2] = GEN_INT (3 - INTVAL (operands[2]));

67161

+

67162

+ return "xxspltw %x0,%x1,%2";

67163

+}

67164

+ [(set_attr "type" "vecperm")])

67165

+

67166

+(define_insn "vsx_xxspltw_<mode>_direct"

67167

+ [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?wa")

67168

+ (unspec:VSX_W [(match_operand:VSX_W 1 "vsx_register_operand" "wf,wa")

67169

+ (match_operand:QI 2 "u5bit_cint_operand" "i,i")]

67170

+ UNSPEC_VSX_XXSPLTW))]

67171

+ "VECTOR_MEM_VSX_P (<MODE>mode)"

67172

"xxspltw %x0,%x1,%2"

67173

[(set_attr "type" "vecperm")])

67174

67175

@@ -1308,7 +1814,12 @@

67176

(parallel [(const_int 0) (const_int 4)

67177

(const_int 1) (const_int 5)])))]

67178

"VECTOR_MEM_VSX_P (<MODE>mode)"

67179

- "xxmrghw %x0,%x1,%x2"

67180

+{

67181

+ if (BYTES_BIG_ENDIAN)

67182

+ return "xxmrghw %x0,%x1,%x2";

67183

+ else

67184

+ return "xxmrglw %x0,%x2,%x1";

67185

+}

67186

[(set_attr "type" "vecperm")])

67187

67188

(define_insn "vsx_xxmrglw_<mode>"

67189

@@ -1320,7 +1831,12 @@

67190

(parallel [(const_int 2) (const_int 6)

67191

(const_int 3) (const_int 7)])))]

67192

"VECTOR_MEM_VSX_P (<MODE>mode)"

67193

- "xxmrglw %x0,%x1,%x2"

67194

+{

67195

+ if (BYTES_BIG_ENDIAN)

67196

+ return "xxmrglw %x0,%x1,%x2";

67197

+ else

67198

+ return "xxmrghw %x0,%x2,%x1";

67199

+}

67200

[(set_attr "type" "vecperm")])

67201

67202

;; Shift left double by word immediate

67203

@@ -1483,3 +1999,27 @@

67204

}"

67205

[(set_attr "length" "20")

67206

(set_attr "type" "veccomplex")])

67207

+

67208

+

67209

+;; Power8 Vector fusion. The fused ops must be physically adjacent.

67210

+(define_peephole

67211

+ [(set (match_operand:P 0 "base_reg_operand" "")

67212

+ (match_operand:P 1 "short_cint_operand" ""))

67213

+ (set (match_operand:VSX_M2 2 "vsx_register_operand" "")

67214

+ (mem:VSX_M2 (plus:P (match_dup 0)

67215

+ (match_operand:P 3 "int_reg_operand" ""))))]

67216

+ "TARGET_VSX && TARGET_P8_FUSION"

67217

+ "li %0,%1\t\t\t# vector load fusion\;lx<VSX_M2:VSm>x %x2,%0,%3"

67218

+ [(set_attr "length" "8")

67219

+ (set_attr "type" "vecload")])

67220

+

67221

+(define_peephole

67222

+ [(set (match_operand:P 0 "base_reg_operand" "")

67223

+ (match_operand:P 1 "short_cint_operand" ""))

67224

+ (set (match_operand:VSX_M2 2 "vsx_register_operand" "")

67225

+ (mem:VSX_M2 (plus:P (match_operand:P 3 "int_reg_operand" "")

67226

+ (match_dup 0))))]

67227

+ "TARGET_VSX && TARGET_P8_FUSION"

67228

+ "li %0,%1\t\t\t# vector load fusion\;lx<VSX_M2:VSm>x %x2,%0,%3"

67229

+ [(set_attr "length" "8")

67230

+ (set_attr "type" "vecload")])

67231

Index: gcc/config/rs6000/rs6000.h

67232

===================================================================

67233

--- a/src/gcc/config/rs6000/rs6000.h (.../tags/gcc_4_8_2_release)

67234

+++ b/src/gcc/config/rs6000/rs6000.h (.../branches/gcc-4_8-branch)

67235

@@ -92,7 +92,7 @@

67236

#ifdef HAVE_AS_POWER8

67237

#define ASM_CPU_POWER8_SPEC "-mpower8"

67238

#else

67239

-#define ASM_CPU_POWER8_SPEC "-mpower4 -maltivec"

67240

+#define ASM_CPU_POWER8_SPEC ASM_CPU_POWER7_SPEC

67241

#endif

67242

67243

#ifdef HAVE_AS_DCI

67244

@@ -164,6 +164,7 @@

67245

%{mcpu=e6500: -me6500} \

67246

%{maltivec: -maltivec} \

67247

%{mvsx: -mvsx %{!maltivec: -maltivec} %{!mcpu*: %(asm_cpu_power7)}} \

67248

+%{mpower8-vector|mcrypto|mdirect-move|mhtm: %{!mcpu*: %(asm_cpu_power8)}} \

67249

-many"

67250

67251

#define CPP_DEFAULT_SPEC ""

67252

@@ -277,6 +278,21 @@

67253

#define TARGET_POPCNTD 0

67254

#endif

67255

67256

+/* Define the ISA 2.07 flags as 0 if the target assembler does not support the

67257

+ waitasecond instruction. Allow -mpower8-fusion, since it does not add new

67258

+ instructions. */

67259

+

67260

+#ifndef HAVE_AS_POWER8

67261

+#undef TARGET_DIRECT_MOVE

67262

+#undef TARGET_CRYPTO

67263

+#undef TARGET_HTM

67264

+#undef TARGET_P8_VECTOR

67265

+#define TARGET_DIRECT_MOVE 0

67266

+#define TARGET_CRYPTO 0

67267

+#define TARGET_HTM 0

67268

+#define TARGET_P8_VECTOR 0

67269

+#endif

67270

+

67271

/* Define TARGET_LWSYNC_INSTRUCTION if the assembler knows about lwsync. If

67272

not, generate the lwsync code as an integer constant. */

67273

#ifdef HAVE_AS_LWSYNC

67274

@@ -386,6 +402,7 @@

67275

#define TARGET_DEBUG_TARGET (rs6000_debug & MASK_DEBUG_TARGET)

67276

#define TARGET_DEBUG_BUILTIN (rs6000_debug & MASK_DEBUG_BUILTIN)

67277

67278

+/* Describe the vector unit used for arithmetic operations. */

67279

extern enum rs6000_vector rs6000_vector_unit[];

67280

67281

#define VECTOR_UNIT_NONE_P(MODE) \

67282

@@ -394,12 +411,25 @@

67283

#define VECTOR_UNIT_VSX_P(MODE) \

67284

(rs6000_vector_unit[(MODE)] == VECTOR_VSX)

67285

67286

+#define VECTOR_UNIT_P8_VECTOR_P(MODE) \

67287

+ (rs6000_vector_unit[(MODE)] == VECTOR_P8_VECTOR)

67288

+

67289

#define VECTOR_UNIT_ALTIVEC_P(MODE) \

67290

(rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC)

67291

67292

+#define VECTOR_UNIT_VSX_OR_P8_VECTOR_P(MODE) \

67293

+ (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \

67294

+ (int)VECTOR_VSX, \

67295

+ (int)VECTOR_P8_VECTOR))

67296

+

67297

+/* VECTOR_UNIT_ALTIVEC_OR_VSX_P is used in places where we are using either

67298

+ altivec (VMX) or VSX vector instructions. P8 vector support is upwards

67299

+ compatible, so allow it as well, rather than changing all of the uses of the

67300

+ macro. */

67301

#define VECTOR_UNIT_ALTIVEC_OR_VSX_P(MODE) \

67302

- (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC \

67303

- || rs6000_vector_unit[(MODE)] == VECTOR_VSX)

67304

+ (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \

67305

+ (int)VECTOR_ALTIVEC, \

67306

+ (int)VECTOR_P8_VECTOR))

67307

67308

/* Describe whether to use VSX loads or Altivec loads. For now, just use the

67309

same unit as the vector unit we are using, but we may want to migrate to

67310

@@ -412,12 +442,21 @@

67311

#define VECTOR_MEM_VSX_P(MODE) \

67312

(rs6000_vector_mem[(MODE)] == VECTOR_VSX)

67313

67314

+#define VECTOR_MEM_P8_VECTOR_P(MODE) \

67315

+ (rs6000_vector_mem[(MODE)] == VECTOR_VSX)

67316

+

67317

#define VECTOR_MEM_ALTIVEC_P(MODE) \

67318

(rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC)

67319

67320

+#define VECTOR_MEM_VSX_OR_P8_VECTOR_P(MODE) \

67321

+ (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \

67322

+ (int)VECTOR_VSX, \

67323

+ (int)VECTOR_P8_VECTOR))

67324

+

67325

#define VECTOR_MEM_ALTIVEC_OR_VSX_P(MODE) \

67326

- (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC \

67327

- || rs6000_vector_mem[(MODE)] == VECTOR_VSX)

67328

+ (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \

67329

+ (int)VECTOR_ALTIVEC, \

67330

+ (int)VECTOR_P8_VECTOR))

67331

67332

/* Return the alignment of a given vector type, which is set based on the

67333

vector unit use. VSX for instance can load 32 or 64 bit aligned words

67334

@@ -429,6 +468,15 @@

67335

? rs6000_vector_align[(MODE)] \

67336

: (int)GET_MODE_BITSIZE ((MODE)))

67337

67338

+/* Determine the element order to use for vector instructions. By

67339

+ default we use big-endian element order when targeting big-endian,

67340

+ and little-endian element order when targeting little-endian. For

67341

+ programs being ported from BE Power to LE Power, it can sometimes

67342

+ be useful to use big-endian element order when targeting little-endian.

67343

+ This is set via -maltivec=be, for example. */

67344

+#define VECTOR_ELT_ORDER_BIG \

67345

+ (BYTES_BIG_ENDIAN || (rs6000_altivec_element_order == 2))

67346

+

67347

/* Alignment options for fields in structures for sub-targets following

67348

AIX-like ABI.

67349

ALIGN_POWER word-aligns FP doubles (default AIX ABI).

67350

@@ -479,16 +527,38 @@

67351

#define TARGET_FCTIDUZ TARGET_POPCNTD

67352

#define TARGET_FCTIWUZ TARGET_POPCNTD

67353

67354

+#define TARGET_XSCVDPSPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR)

67355

+#define TARGET_XSCVSPDPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR)

67356

+#define TARGET_VADDUQM (TARGET_P8_VECTOR && TARGET_POWERPC64)

67357

+

67358

+/* Byte/char syncs were added as phased in for ISA 2.06B, but are not present

67359

+ in power7, so conditionalize them on p8 features. TImode syncs need quad

67360

+ memory support. */

67361

+#define TARGET_SYNC_HI_QI (TARGET_QUAD_MEMORY \

67362

+ || TARGET_QUAD_MEMORY_ATOMIC \

67363

+ || TARGET_DIRECT_MOVE)

67364

+

67365

+#define TARGET_SYNC_TI TARGET_QUAD_MEMORY_ATOMIC

67366

+

67367

+/* Power7 has both 32-bit load and store integer for the FPRs, so we don't need

67368

+ to allocate the SDmode stack slot to get the value into the proper location

67369

+ in the register. */

67370

+#define TARGET_NO_SDMODE_STACK (TARGET_LFIWZX && TARGET_STFIWX && TARGET_DFP)

67371

+

67372

/* In switching from using target_flags to using rs6000_isa_flags, the options

67373

machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. For now map

67374

OPTION_MASK_<xxx> back into MASK_<xxx>. */

67375

#define MASK_ALTIVEC OPTION_MASK_ALTIVEC

67376

#define MASK_CMPB OPTION_MASK_CMPB

67377

+#define MASK_CRYPTO OPTION_MASK_CRYPTO

67378

#define MASK_DFP OPTION_MASK_DFP

67379

+#define MASK_DIRECT_MOVE OPTION_MASK_DIRECT_MOVE

67380

#define MASK_DLMZB OPTION_MASK_DLMZB

67381

#define MASK_EABI OPTION_MASK_EABI

67382

#define MASK_FPRND OPTION_MASK_FPRND

67383

+#define MASK_P8_FUSION OPTION_MASK_P8_FUSION

67384

#define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT

67385

+#define MASK_HTM OPTION_MASK_HTM

67386

#define MASK_ISEL OPTION_MASK_ISEL

67387

#define MASK_MFCRF OPTION_MASK_MFCRF

67388

#define MASK_MFPGPR OPTION_MASK_MFPGPR

67389

@@ -495,6 +565,7 @@

67390

#define MASK_MULHW OPTION_MASK_MULHW

67391

#define MASK_MULTIPLE OPTION_MASK_MULTIPLE

67392

#define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE

67393

+#define MASK_P8_VECTOR OPTION_MASK_P8_VECTOR

67394

#define MASK_POPCNTB OPTION_MASK_POPCNTB

67395

#define MASK_POPCNTD OPTION_MASK_POPCNTD

67396

#define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT

67397

@@ -505,6 +576,7 @@

67398

#define MASK_STRING OPTION_MASK_STRING

67399

#define MASK_UPDATE OPTION_MASK_UPDATE

67400

#define MASK_VSX OPTION_MASK_VSX

67401

+#define MASK_VSX_TIMODE OPTION_MASK_VSX_TIMODE

67402

67403

#ifndef IN_LIBGCC2

67404

#define MASK_POWERPC64 OPTION_MASK_POWERPC64

67405

@@ -551,7 +623,8 @@

67406

|| TARGET_CMPB /* ISA 2.05 */ \

67407

|| TARGET_POPCNTD /* ISA 2.06 */ \

67408

|| TARGET_ALTIVEC \

67409

- || TARGET_VSX)))

67410

+ || TARGET_VSX \

67411

+ || TARGET_HARD_FLOAT)))

67412

67413

/* E500 cores only support plain "sync", not lwsync. */

67414

#define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \

67415

@@ -558,6 +631,25 @@

67416

|| rs6000_cpu == PROCESSOR_PPC8548)

67417

67418

67419

+/* Whether SF/DF operations are supported on the E500. */

67420

+#define TARGET_SF_SPE (TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT \

67421

+ && !TARGET_FPRS)

67422

+

67423

+#define TARGET_DF_SPE (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT \

67424

+ && !TARGET_FPRS && TARGET_E500_DOUBLE)

67425

+

67426

+/* Whether SF/DF operations are supported by by the normal floating point unit

67427

+ (or the vector/scalar unit). */

67428

+#define TARGET_SF_FPR (TARGET_HARD_FLOAT && TARGET_FPRS \

67429

+ && TARGET_SINGLE_FLOAT)

67430

+

67431

+#define TARGET_DF_FPR (TARGET_HARD_FLOAT && TARGET_FPRS \

67432

+ && TARGET_DOUBLE_FLOAT)

67433

+

67434

+/* Whether SF/DF operations are supported by any hardware. */

67435

+#define TARGET_SF_INSN (TARGET_SF_FPR || TARGET_SF_SPE)

67436

+#define TARGET_DF_INSN (TARGET_DF_FPR || TARGET_DF_SPE)

67437

+

67438

/* Which machine supports the various reciprocal estimate instructions. */

67439

#define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \

67440

&& TARGET_FPRS && TARGET_SINGLE_FLOAT)

67441

@@ -595,9 +687,6 @@

67442

#define RS6000_RECIP_AUTO_RSQRTE_P(MODE) \

67443

(rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RSQRTE)

67444

67445

-#define RS6000_RECIP_HIGH_PRECISION_P(MODE) \

67446

- ((MODE) == SFmode || (MODE) == V4SFmode || TARGET_RECIP_PRECISION)

67447

-

67448

/* The default CPU for TARGET_OPTION_OVERRIDE. */

67449

#define OPTION_TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT

67450

67451

@@ -760,12 +849,6 @@

67452

/* No data type wants to be aligned rounder than this. */

67453

#define BIGGEST_ALIGNMENT 128

67454

67455

-/* A C expression to compute the alignment for a variables in the

67456

- local store. TYPE is the data type, and ALIGN is the alignment

67457

- that the object would ordinarily have. */

67458

-#define LOCAL_ALIGNMENT(TYPE, ALIGN) \

67459

- DATA_ALIGNMENT (TYPE, ALIGN)

67460

-

67461

/* Alignment of field after `int : 0' in a structure. */

67462

#define EMPTY_FIELD_BOUNDARY 32

67463

67464

@@ -775,8 +858,15 @@

67465

/* A bit-field declared as `int' forces `int' alignment for the struct. */

67466

#define PCC_BITFIELD_TYPE_MATTERS 1

67467

67468

-/* Make strings word-aligned so strcpy from constants will be faster.

67469

- Make vector constants quadword aligned. */

67470

+enum data_align { align_abi, align_opt, align_both };

67471

+

67472

+/* A C expression to compute the alignment for a variables in the

67473

+ local store. TYPE is the data type, and ALIGN is the alignment

67474

+ that the object would ordinarily have. */

67475

+#define LOCAL_ALIGNMENT(TYPE, ALIGN) \

67476

+ rs6000_data_alignment (TYPE, ALIGN, align_both)

67477

+

67478

+/* Make strings word-aligned so strcpy from constants will be faster. */

67479

#define CONSTANT_ALIGNMENT(EXP, ALIGN) \

67480

(TREE_CODE (EXP) == STRING_CST \

67481

&& (STRICT_ALIGNMENT || !optimize_size) \

67482

@@ -784,21 +874,14 @@

67483

? BITS_PER_WORD \

67484

: (ALIGN))

67485

67486

-/* Make arrays of chars word-aligned for the same reasons.

67487

- Align vectors to 128 bits. Align SPE vectors and E500 v2 doubles to

67488

+/* Make arrays of chars word-aligned for the same reasons. */

67489

+#define DATA_ALIGNMENT(TYPE, ALIGN) \

67490

+ rs6000_data_alignment (TYPE, ALIGN, align_opt)

67491

+

67492

+/* Align vectors to 128 bits. Align SPE vectors and E500 v2 doubles to

67493

64 bits. */

67494

-#define DATA_ALIGNMENT(TYPE, ALIGN) \

67495

- (TREE_CODE (TYPE) == VECTOR_TYPE \

67496

- ? (((TARGET_SPE && SPE_VECTOR_MODE (TYPE_MODE (TYPE))) \

67497

- || (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (TYPE_MODE (TYPE)))) \

67498

- ? 64 : 128) \

67499

- : ((TARGET_E500_DOUBLE \

67500

- && TREE_CODE (TYPE) == REAL_TYPE \

67501

- && TYPE_MODE (TYPE) == DFmode) \

67502

- ? 64 \

67503

- : (TREE_CODE (TYPE) == ARRAY_TYPE \

67504

- && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \

67505

- && (ALIGN) < BITS_PER_WORD) ? BITS_PER_WORD : (ALIGN)))

67506

+#define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \

67507

+ rs6000_data_alignment (TYPE, ALIGN, align_abi)

67508

67509

/* Nonzero if move instructions will actually fail to work

67510

when given unaligned data. */

67511

@@ -842,15 +925,17 @@

67512

in inline functions.

67513

67514

Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame

67515

- pointer, which is eventually eliminated in favor of SP or FP. */

67516

+ pointer, which is eventually eliminated in favor of SP or FP.

67517

67518

-#define FIRST_PSEUDO_REGISTER 114

67519

+ The 3 HTM registers aren't also included in DWARF_FRAME_REGISTERS. */

67520

67521

+#define FIRST_PSEUDO_REGISTER 117

67522

+

67523

/* This must be included for pre gcc 3.0 glibc compatibility. */

67524

#define PRE_GCC3_DWARF_FRAME_REGISTERS 77

67525

67526

/* Add 32 dwarf columns for synthetic SPE registers. */

67527

-#define DWARF_FRAME_REGISTERS ((FIRST_PSEUDO_REGISTER - 1) + 32)

67528

+#define DWARF_FRAME_REGISTERS ((FIRST_PSEUDO_REGISTER - 4) + 32)

67529

67530

/* The SPE has an additional 32 synthetic registers, with DWARF debug

67531

info numbering for these registers starting at 1200. While eh_frame

67532

@@ -866,7 +951,7 @@

67533

We must map them here to avoid huge unwinder tables mostly consisting

67534

of unused space. */

67535

#define DWARF_REG_TO_UNWIND_COLUMN(r) \

67536

- ((r) > 1200 ? ((r) - 1200 + FIRST_PSEUDO_REGISTER - 1) : (r))

67537

+ ((r) > 1200 ? ((r) - 1200 + (DWARF_FRAME_REGISTERS - 32)) : (r))

67538

67539

/* Use standard DWARF numbering for DWARF debugging information. */

67540

#define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO)

67541

@@ -906,7 +991,7 @@

67542

0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \

67543

0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \

67544

1, 1 \

67545

- , 1, 1, 1 \

67546

+ , 1, 1, 1, 1, 1, 1 \

67547

}

67548

67549

/* 1 for registers not available across function calls.

67550

@@ -926,7 +1011,7 @@

67551

0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \

67552

0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \

67553

1, 1 \

67554

- , 1, 1, 1 \

67555

+ , 1, 1, 1, 1, 1, 1 \

67556

}

67557

67558

/* Like `CALL_USED_REGISTERS' except this macro doesn't require that

67559

@@ -945,7 +1030,7 @@

67560

0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \

67561

0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \

67562

0, 0 \

67563

- , 0, 0, 0 \

67564

+ , 0, 0, 0, 0, 0, 0 \

67565

}

67566

67567

#define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)

67568

@@ -984,6 +1069,9 @@

67569

vrsave, vscr (fixed)

67570

spe_acc, spefscr (fixed)

67571

sfp (fixed)

67572

+ tfhar (fixed)

67573

+ tfiar (fixed)

67574

+ texasr (fixed)

67575

*/

67576

67577

#if FIXED_R2 == 1

67578

@@ -1004,7 +1092,9 @@

67579

67580

#define REG_ALLOC_ORDER \

67581

{32, \

67582

- 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \

67583

+ /* move fr13 (ie 45) later, so if we need TFmode, it does */ \

67584

+ /* not use fr14 which is a saved register. */ \

67585

+ 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, 45, \

67586

33, \

67587

63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \

67588

50, 49, 48, 47, 46, \

67589

@@ -1023,7 +1113,7 @@

67590

96, 95, 94, 93, 92, 91, \

67591

108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \

67592

109, 110, \

67593

- 111, 112, 113 \

67594

+ 111, 112, 113, 114, 115, 116 \

67595

}

67596

67597

/* True if register is floating-point. */

67598

@@ -1064,8 +1154,11 @@

67599

#define VINT_REGNO_P(N) ALTIVEC_REGNO_P (N)

67600

67601

/* Alternate name for any vector register supporting logical operations, no

67602

- matter which instruction set(s) are available. */

67603

-#define VLOGICAL_REGNO_P(N) VFLOAT_REGNO_P (N)

67604

+ matter which instruction set(s) are available. Allow GPRs as well as the

67605

+ vector registers. */

67606

+#define VLOGICAL_REGNO_P(N) \

67607

+ (INT_REGNO_P (N) || ALTIVEC_REGNO_P (N) \

67608

+ || (TARGET_VSX && FP_REGNO_P (N))) \

67609

67610

/* Return number of consecutive hard regs needed starting at reg REGNO

67611

to hold something of mode MODE. */

67612

@@ -1106,7 +1199,7 @@

67613

67614

#define ALTIVEC_OR_VSX_VECTOR_MODE(MODE) \

67615

(ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \

67616

- || (MODE) == V2DImode)

67617

+ || (MODE) == V2DImode || (MODE) == V1TImode)

67618

67619

#define SPE_VECTOR_MODE(MODE) \

67620

((MODE) == V4HImode \

67621

@@ -1125,28 +1218,32 @@

67622

/* Value is 1 if it is a good idea to tie two pseudo registers

67623

when one has mode MODE1 and one has mode MODE2.

67624

If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,

67625

- for any hard reg, then this must be 0 for correct output. */

67626

-#define MODES_TIEABLE_P(MODE1, MODE2) \

67627

- (SCALAR_FLOAT_MODE_P (MODE1) \

67628

+ for any hard reg, then this must be 0 for correct output.

67629

+

67630

+ PTImode cannot tie with other modes because PTImode is restricted to even

67631

+ GPR registers, and TImode can go in any GPR as well as VSX registers (PR

67632

+ 57744). */

67633

+#define MODES_TIEABLE_P(MODE1, MODE2) \

67634

+ ((MODE1) == PTImode \

67635

+ ? (MODE2) == PTImode \

67636

+ : (MODE2) == PTImode \

67637

+ ? 0 \

67638

+ : SCALAR_FLOAT_MODE_P (MODE1) \

67639

? SCALAR_FLOAT_MODE_P (MODE2) \

67640

: SCALAR_FLOAT_MODE_P (MODE2) \

67641

- ? SCALAR_FLOAT_MODE_P (MODE1) \

67642

+ ? 0 \

67643

: GET_MODE_CLASS (MODE1) == MODE_CC \

67644

? GET_MODE_CLASS (MODE2) == MODE_CC \

67645

: GET_MODE_CLASS (MODE2) == MODE_CC \

67646

- ? GET_MODE_CLASS (MODE1) == MODE_CC \

67647

+ ? 0 \

67648

: SPE_VECTOR_MODE (MODE1) \

67649

? SPE_VECTOR_MODE (MODE2) \

67650

: SPE_VECTOR_MODE (MODE2) \

67651

- ? SPE_VECTOR_MODE (MODE1) \

67652

- : ALTIVEC_VECTOR_MODE (MODE1) \

67653

- ? ALTIVEC_VECTOR_MODE (MODE2) \

67654

- : ALTIVEC_VECTOR_MODE (MODE2) \

67655

- ? ALTIVEC_VECTOR_MODE (MODE1) \

67656

+ ? 0 \

67657

: ALTIVEC_OR_VSX_VECTOR_MODE (MODE1) \

67658

? ALTIVEC_OR_VSX_VECTOR_MODE (MODE2) \

67659

: ALTIVEC_OR_VSX_VECTOR_MODE (MODE2) \

67660

- ? ALTIVEC_OR_VSX_VECTOR_MODE (MODE1) \

67661

+ ? 0 \

67662

: 1)

67663

67664

/* Post-reload, we can't use any new AltiVec registers, as we already

67665

@@ -1240,6 +1337,7 @@

67666

VSCR_REGS,

67667

SPE_ACC_REGS,

67668

SPEFSCR_REGS,

67669

+ SPR_REGS,

67670

NON_SPECIAL_REGS,

67671

LINK_REGS,

67672

CTR_REGS,

67673

@@ -1270,6 +1368,7 @@

67674

"VSCR_REGS", \

67675

"SPE_ACC_REGS", \

67676

"SPEFSCR_REGS", \

67677

+ "SPR_REGS", \

67678

"NON_SPECIAL_REGS", \

67679

"LINK_REGS", \

67680

"CTR_REGS", \

67681

@@ -1299,6 +1398,7 @@

67682

{ 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \

67683

{ 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \

67684

{ 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \

67685

+ { 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, /* SPR_REGS */ \

67686

{ 0xffffffff, 0xffffffff, 0x00000008, 0x00020000 }, /* NON_SPECIAL_REGS */ \

67687

{ 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \

67688

{ 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \

67689

@@ -1309,7 +1409,7 @@

67690

{ 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \

67691

{ 0xffffffff, 0x00000000, 0x00000ffe, 0x00020000 }, /* NON_FLOAT_REGS */ \

67692

{ 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* CA_REGS */ \

67693

- { 0xffffffff, 0xffffffff, 0xfffffffe, 0x0003ffff } /* ALL_REGS */ \

67694

+ { 0xffffffff, 0xffffffff, 0xfffffffe, 0x0007ffff } /* ALL_REGS */ \

67695

}

67696

67697

/* The same information, inverted:

67698

@@ -1337,7 +1437,18 @@

67699

RS6000_CONSTRAINT_wa, /* Any VSX register */

67700

RS6000_CONSTRAINT_wd, /* VSX register for V2DF */

67701

RS6000_CONSTRAINT_wf, /* VSX register for V4SF */

67702

+ RS6000_CONSTRAINT_wg, /* FPR register for -mmfpgpr */

67703

+ RS6000_CONSTRAINT_wl, /* FPR register for LFIWAX */

67704

+ RS6000_CONSTRAINT_wm, /* VSX register for direct move */

67705

+ RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */

67706

RS6000_CONSTRAINT_ws, /* VSX register for DF */

67707

+ RS6000_CONSTRAINT_wt, /* VSX register for TImode */

67708

+ RS6000_CONSTRAINT_wu, /* Altivec register for float load/stores. */

67709

+ RS6000_CONSTRAINT_wv, /* Altivec register for double load/stores. */

67710

+ RS6000_CONSTRAINT_ww, /* FP or VSX register for vsx float ops. */

67711

+ RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */

67712

+ RS6000_CONSTRAINT_wy, /* VSX register for SF */

67713

+ RS6000_CONSTRAINT_wz, /* FPR register for LFIWZX */

67714

RS6000_CONSTRAINT_MAX

67715

};

67716

67717

@@ -1425,21 +1536,14 @@

67718

arguments. */

67719

#define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0 || flag_asan != 0)

67720

67721

-/* Size of the outgoing register save area */

67722

-#define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \

67723

- || DEFAULT_ABI == ABI_DARWIN) \

67724

- ? (TARGET_64BIT ? 64 : 32) \

67725

- : 0)

67726

-

67727

/* Size of the fixed area on the stack */

67728

#define RS6000_SAVE_AREA \

67729

- (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \

67730

+ ((DEFAULT_ABI == ABI_V4 ? 8 : DEFAULT_ABI == ABI_ELFv2 ? 16 : 24) \

67731

<< (TARGET_64BIT ? 1 : 0))

67732

67733

-/* MEM representing address to save the TOC register */

67734

-#define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \

67735

- plus_constant (Pmode, stack_pointer_rtx, \

67736

- (TARGET_32BIT ? 20 : 40)))

67737

+/* Stack offset for toc save slot. */

67738

+#define RS6000_TOC_SAVE_SLOT \

67739

+ ((DEFAULT_ABI == ABI_ELFv2 ? 12 : 20) << (TARGET_64BIT ? 1 : 0))

67740

67741

/* Align an address */

67742

#define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1))

67743

@@ -1489,7 +1593,7 @@

67744

/* Define this if stack space is still allocated for a parameter passed

67745

in a register. The value is the number of bytes allocated to this

67746

area. */

67747

-#define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE

67748

+#define REG_PARM_STACK_SPACE(FNDECL) rs6000_reg_parm_stack_space((FNDECL))

67749

67750

/* Define this if the above stack space is to be considered part of the

67751

space allocated by the caller. */

67752

@@ -1522,7 +1626,7 @@

67753

NONLOCAL needs twice Pmode to maintain both backchain and SP. */

67754

#define STACK_SAVEAREA_MODE(LEVEL) \

67755

(LEVEL == SAVE_FUNCTION ? VOIDmode \

67756

- : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode)

67757

+ : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : PTImode) : Pmode)

67758

67759

/* Minimum and maximum general purpose registers used to hold arguments. */

67760

#define GP_ARG_MIN_REG 3

67761

@@ -1533,9 +1637,8 @@

67762

#define FP_ARG_MIN_REG 33

67763

#define FP_ARG_AIX_MAX_REG 45

67764

#define FP_ARG_V4_MAX_REG 40

67765

-#define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \

67766

- || DEFAULT_ABI == ABI_DARWIN) \

67767

- ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG)

67768

+#define FP_ARG_MAX_REG (DEFAULT_ABI == ABI_V4 \

67769

+ ? FP_ARG_V4_MAX_REG : FP_ARG_AIX_MAX_REG)

67770

#define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)

67771

67772

/* Minimum and maximum AltiVec registers used to hold arguments. */

67773

@@ -1543,10 +1646,17 @@

67774

#define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)

67775

#define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)

67776

67777

+/* Maximum number of registers per ELFv2 homogeneous aggregate argument. */

67778

+#define AGGR_ARG_NUM_REG 8

67779

+

67780

/* Return registers */

67781

#define GP_ARG_RETURN GP_ARG_MIN_REG

67782

#define FP_ARG_RETURN FP_ARG_MIN_REG

67783

#define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)

67784

+#define FP_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 ? FP_ARG_RETURN \

67785

+ : (FP_ARG_RETURN + AGGR_ARG_NUM_REG - 1))

67786

+#define ALTIVEC_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 ? ALTIVEC_ARG_RETURN \

67787

+ : (ALTIVEC_ARG_RETURN + AGGR_ARG_NUM_REG - 1))

67788

67789

/* Flags for the call/call_value rtl operations set up by function_arg */

67790

#define CALL_NORMAL 0x00000000 /* no special processing */

67791

@@ -1566,8 +1676,10 @@

67792

On RS/6000, this is r3, fp1, and v2 (for AltiVec). */

67793

#define FUNCTION_VALUE_REGNO_P(N) \

67794

((N) == GP_ARG_RETURN \

67795

- || ((N) == FP_ARG_RETURN && TARGET_HARD_FLOAT && TARGET_FPRS) \

67796

- || ((N) == ALTIVEC_ARG_RETURN && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI))

67797

+ || ((N) >= FP_ARG_RETURN && (N) <= FP_ARG_MAX_RETURN \

67798

+ && TARGET_HARD_FLOAT && TARGET_FPRS) \

67799

+ || ((N) >= ALTIVEC_ARG_RETURN && (N) <= ALTIVEC_ARG_MAX_RETURN \

67800

+ && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI))

67801

67802

/* 1 if N is a possible register number for function argument passing.

67803

On RS/6000, these are r3-r10 and fp1-fp13.

67804

@@ -1691,11 +1803,8 @@

67805

/* Number of bytes into the frame return addresses can be found. See

67806

rs6000_stack_info in rs6000.c for more information on how the different

67807

abi's store the return address. */

67808

-#define RETURN_ADDRESS_OFFSET \

67809

- ((DEFAULT_ABI == ABI_AIX \

67810

- || DEFAULT_ABI == ABI_DARWIN) ? (TARGET_32BIT ? 8 : 16) : \

67811

- (DEFAULT_ABI == ABI_V4) ? 4 : \

67812

- (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0))

67813

+#define RETURN_ADDRESS_OFFSET \

67814

+ ((DEFAULT_ABI == ABI_V4 ? 4 : 8) << (TARGET_64BIT ? 1 : 0))

67815

67816

/* The current return address is in link register (65). The return address

67817

of anything farther back is accessed normally at an offset of 8 from the

67818

@@ -2215,6 +2324,9 @@

67819

&rs6000_reg_names[111][0], /* spe_acc */ \

67820

&rs6000_reg_names[112][0], /* spefscr */ \

67821

&rs6000_reg_names[113][0], /* sfp */ \

67822

+ &rs6000_reg_names[114][0], /* tfhar */ \

67823

+ &rs6000_reg_names[115][0], /* tfiar */ \

67824

+ &rs6000_reg_names[116][0], /* texasr */ \

67825

}

67826

67827

/* Table of additional register names to use in user input. */

67828

@@ -2268,7 +2380,9 @@

67829

{"vs48", 93}, {"vs49", 94}, {"vs50", 95}, {"vs51", 96}, \

67830

{"vs52", 97}, {"vs53", 98}, {"vs54", 99}, {"vs55", 100}, \

67831

{"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104}, \

67832

- {"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108} }

67833

+ {"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108}, \

67834

+ /* Transactional Memory Facility (HTM) Registers. */ \

67835

+ {"tfhar", 114}, {"tfiar", 115}, {"texasr", 116} }

67836

67837

/* This is how to output an element of a case-vector that is relative. */

67838

67839

@@ -2357,7 +2471,12 @@

67840

#define RS6000_BTC_ATTR_MASK 0x00000700 /* Mask of the attributes. */

67841

67842

/* Miscellaneous information. */

67843

-#define RS6000_BTC_OVERLOADED 0x4000000 /* function is overloaded. */

67844

+#define RS6000_BTC_SPR 0x01000000 /* function references SPRs. */

67845

+#define RS6000_BTC_VOID 0x02000000 /* function has no return value. */

67846

+#define RS6000_BTC_OVERLOADED 0x04000000 /* function is overloaded. */

67847

+#define RS6000_BTC_32BIT 0x08000000 /* function references SPRs. */

67848

+#define RS6000_BTC_64BIT 0x10000000 /* function references SPRs. */

67849

+#define RS6000_BTC_MISC_MASK 0x1f000000 /* Mask of the misc info. */

67850

67851

/* Convenience macros to document the instruction type. */

67852

#define RS6000_BTC_MEM RS6000_BTC_MISC /* load/store touches mem. */

67853

@@ -2369,6 +2488,9 @@

67854

#define RS6000_BTM_ALWAYS 0 /* Always enabled. */

67855

#define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */

67856

#define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */

67857

+#define RS6000_BTM_P8_VECTOR MASK_P8_VECTOR /* ISA 2.07 vector. */

67858

+#define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */

67859

+#define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */

67860

#define RS6000_BTM_SPE MASK_STRING /* E500 */

67861

#define RS6000_BTM_PAIRED MASK_MULHW /* 750CL paired insns. */

67862

#define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */

67863

@@ -2377,15 +2499,22 @@

67864

#define RS6000_BTM_FRSQRTES MASK_POPCNTB /* FRSQRTES instruction. */

67865

#define RS6000_BTM_POPCNTD MASK_POPCNTD /* Target supports ISA 2.06. */

67866

#define RS6000_BTM_CELL MASK_FPRND /* Target is cell powerpc. */

67867

+#define RS6000_BTM_DFP MASK_DFP /* Decimal floating point. */

67868

+#define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */

67869

67870

#define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \

67871

| RS6000_BTM_VSX \

67872

+ | RS6000_BTM_P8_VECTOR \

67873

+ | RS6000_BTM_CRYPTO \

67874

| RS6000_BTM_FRE \

67875

| RS6000_BTM_FRES \

67876

| RS6000_BTM_FRSQRTE \

67877

| RS6000_BTM_FRSQRTES \

67878

+ | RS6000_BTM_HTM \

67879

| RS6000_BTM_POPCNTD \

67880

- | RS6000_BTM_CELL)

67881

+ | RS6000_BTM_CELL \

67882

+ | RS6000_BTM_DFP \

67883

+ | RS6000_BTM_HARD_FLOAT)

67884

67885

/* Define builtin enum index. */

67886

67887

@@ -2395,6 +2524,7 @@

67888

#undef RS6000_BUILTIN_A

67889

#undef RS6000_BUILTIN_D

67890

#undef RS6000_BUILTIN_E

67891

+#undef RS6000_BUILTIN_H

67892

#undef RS6000_BUILTIN_P

67893

#undef RS6000_BUILTIN_Q

67894

#undef RS6000_BUILTIN_S

67895

@@ -2406,6 +2536,7 @@

67896

#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) ENUM,

67897

#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) ENUM,

67898

#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) ENUM,

67899

+#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) ENUM,

67900

#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) ENUM,

67901

#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) ENUM,

67902

#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) ENUM,

67903

@@ -2424,6 +2555,7 @@

67904

#undef RS6000_BUILTIN_A

67905

#undef RS6000_BUILTIN_D

67906

#undef RS6000_BUILTIN_E

67907

+#undef RS6000_BUILTIN_H

67908

#undef RS6000_BUILTIN_P

67909

#undef RS6000_BUILTIN_Q

67910

#undef RS6000_BUILTIN_S

67911

@@ -2437,6 +2569,7 @@

67912

RS6000_BTI_opaque_p_V2SI,

67913

RS6000_BTI_opaque_V4SI,

67914

RS6000_BTI_V16QI,

67915

+ RS6000_BTI_V1TI,

67916

RS6000_BTI_V2SI,

67917

RS6000_BTI_V2SF,

67918

RS6000_BTI_V2DI,

67919

@@ -2446,6 +2579,7 @@

67920

RS6000_BTI_V4SF,

67921

RS6000_BTI_V8HI,

67922

RS6000_BTI_unsigned_V16QI,

67923

+ RS6000_BTI_unsigned_V1TI,

67924

RS6000_BTI_unsigned_V8HI,

67925

RS6000_BTI_unsigned_V4SI,

67926

RS6000_BTI_unsigned_V2DI,

67927

@@ -2471,8 +2605,13 @@

67928

RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */

67929

RS6000_BTI_INTDI, /* intDI_type_node */

67930

RS6000_BTI_UINTDI, /* unsigned_intDI_type_node */

67931

+ RS6000_BTI_INTTI, /* intTI_type_node */

67932

+ RS6000_BTI_UINTTI, /* unsigned_intTI_type_node */

67933

RS6000_BTI_float, /* float_type_node */

67934

RS6000_BTI_double, /* double_type_node */

67935

+ RS6000_BTI_long_double, /* long_double_type_node */

67936

+ RS6000_BTI_dfloat64, /* dfloat64_type_node */

67937

+ RS6000_BTI_dfloat128, /* dfloat128_type_node */

67938

RS6000_BTI_void, /* void_type_node */

67939

RS6000_BTI_MAX

67940

};

67941

@@ -2483,6 +2622,7 @@

67942

#define opaque_p_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_p_V2SI])

67943

#define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI])

67944

#define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI])

67945

+#define V1TI_type_node (rs6000_builtin_types[RS6000_BTI_V1TI])

67946

#define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI])

67947

#define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF])

67948

#define V2SI_type_node (rs6000_builtin_types[RS6000_BTI_V2SI])

67949

@@ -2492,6 +2632,7 @@

67950

#define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF])

67951

#define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI])

67952

#define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI])

67953

+#define unsigned_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V1TI])

67954

#define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI])

67955

#define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI])

67956

#define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI])

67957

@@ -2518,8 +2659,13 @@

67958

#define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI])

67959

#define intDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTDI])

67960

#define uintDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTDI])

67961

+#define intTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTTI])

67962

+#define uintTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTTI])

67963

#define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float])

67964

#define double_type_internal_node (rs6000_builtin_types[RS6000_BTI_double])

67965

+#define long_double_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_double])

67966

+#define dfloat64_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat64])

67967

+#define dfloat128_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat128])

67968

#define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void])

67969

67970

extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX];

67971

Index: gcc/config/rs6000/altivec.md

67972

===================================================================

67973

--- a/src/gcc/config/rs6000/altivec.md (.../tags/gcc_4_8_2_release)

67974

+++ b/src/gcc/config/rs6000/altivec.md (.../branches/gcc-4_8-branch)

67975

@@ -41,15 +41,12 @@

67976

UNSPEC_VMULOSB

67977

UNSPEC_VMULOUH

67978

UNSPEC_VMULOSH

67979

- UNSPEC_VPKUHUM

67980

- UNSPEC_VPKUWUM

67981

UNSPEC_VPKPX

67982

- UNSPEC_VPKSHSS

67983

- UNSPEC_VPKSWSS

67984

- UNSPEC_VPKUHUS

67985

- UNSPEC_VPKSHUS

67986

- UNSPEC_VPKUWUS

67987

- UNSPEC_VPKSWUS

67988

+ UNSPEC_VPACK_SIGN_SIGN_SAT

67989

+ UNSPEC_VPACK_SIGN_UNS_SAT

67990

+ UNSPEC_VPACK_UNS_UNS_SAT

67991

+ UNSPEC_VPACK_UNS_UNS_MOD

67992

+ UNSPEC_VPACK_UNS_UNS_MOD_DIRECT

67993

UNSPEC_VSLV4SI

67994

UNSPEC_VSLO

67995

UNSPEC_VSR

67996

@@ -71,12 +68,12 @@

67997

UNSPEC_VLOGEFP

67998

UNSPEC_VEXPTEFP

67999

UNSPEC_VLSDOI

68000

- UNSPEC_VUPKHSB

68001

+ UNSPEC_VUNPACK_HI_SIGN

68002

+ UNSPEC_VUNPACK_LO_SIGN

68003

+ UNSPEC_VUNPACK_HI_SIGN_DIRECT

68004

+ UNSPEC_VUNPACK_LO_SIGN_DIRECT

68005

UNSPEC_VUPKHPX

68006

- UNSPEC_VUPKHSH

68007

- UNSPEC_VUPKLSB

68008

UNSPEC_VUPKLPX

68009

- UNSPEC_VUPKLSH

68010

UNSPEC_DST

68011

UNSPEC_DSTT

68012

UNSPEC_DSTST

68013

@@ -134,6 +131,21 @@

68014

UNSPEC_VUPKLS_V4SF

68015

UNSPEC_VUPKHU_V4SF

68016

UNSPEC_VUPKLU_V4SF

68017

+ UNSPEC_VGBBD

68018

+ UNSPEC_VMRGH_DIRECT

68019

+ UNSPEC_VMRGL_DIRECT

68020

+ UNSPEC_VSPLT_DIRECT

68021

+ UNSPEC_VSUMSWS_DIRECT

68022

+ UNSPEC_VADDCUQ

68023

+ UNSPEC_VADDEUQM

68024

+ UNSPEC_VADDECUQ

68025

+ UNSPEC_VSUBCUQ

68026

+ UNSPEC_VSUBEUQM

68027

+ UNSPEC_VSUBECUQ

68028

+ UNSPEC_VBPERMQ

68029

+ UNSPEC_BCDADD

68030

+ UNSPEC_BCDSUB

68031

+ UNSPEC_BCD_OVERFLOW

68032

])

68033

68034

(define_c_enum "unspecv"

68035

@@ -146,6 +158,8 @@

68036

68037

;; Vec int modes

68038

(define_mode_iterator VI [V4SI V8HI V16QI])

68039

+;; Like VI, but add ISA 2.07 integer vector ops

68040

+(define_mode_iterator VI2 [V4SI V8HI V16QI V2DI])

68041

;; Short vec in modes

68042

(define_mode_iterator VIshort [V8HI V16QI])

68043

;; Vec float modes

68044

@@ -154,14 +168,25 @@

68045

(define_mode_iterator V [V4SI V8HI V16QI V4SF])

68046

;; Vec modes for move/logical/permute ops, include vector types for move not

68047

;; otherwise handled by altivec (v2df, v2di, ti)

68048

-(define_mode_iterator VM [V4SI V8HI V16QI V4SF V2DF V2DI TI])

68049

+(define_mode_iterator VM [V4SI V8HI V16QI V4SF V2DF V2DI V1TI TI])

68050

68051

;; Like VM, except don't do TImode

68052

-(define_mode_iterator VM2 [V4SI V8HI V16QI V4SF V2DF V2DI])

68053

+(define_mode_iterator VM2 [V4SI V8HI V16QI V4SF V2DF V2DI V1TI])

68054

68055

-(define_mode_attr VI_char [(V4SI "w") (V8HI "h") (V16QI "b")])

68056

-(define_mode_attr VI_scalar [(V4SI "SI") (V8HI "HI") (V16QI "QI")])

68057

+(define_mode_attr VI_char [(V2DI "d") (V4SI "w") (V8HI "h") (V16QI "b")])

68058

+(define_mode_attr VI_scalar [(V2DI "DI") (V4SI "SI") (V8HI "HI") (V16QI "QI")])

68059

+(define_mode_attr VI_unit [(V16QI "VECTOR_UNIT_ALTIVEC_P (V16QImode)")

68060

+ (V8HI "VECTOR_UNIT_ALTIVEC_P (V8HImode)")

68061

+ (V4SI "VECTOR_UNIT_ALTIVEC_P (V4SImode)")

68062

+ (V2DI "VECTOR_UNIT_P8_VECTOR_P (V2DImode)")

68063

+ (V1TI "VECTOR_UNIT_ALTIVEC_P (V1TImode)")])

68064

68065

+;; Vector pack/unpack

68066

+(define_mode_iterator VP [V2DI V4SI V8HI])

68067

+(define_mode_attr VP_small [(V2DI "V4SI") (V4SI "V8HI") (V8HI "V16QI")])

68068

+(define_mode_attr VP_small_lc [(V2DI "v4si") (V4SI "v8hi") (V8HI "v16qi")])

68069

+(define_mode_attr VU_char [(V2DI "w") (V4SI "h") (V8HI "b")])

68070

+

68071

;; Vector move instructions.

68072

(define_insn "*altivec_mov<mode>"

68073

[(set (match_operand:VM2 0 "nonimmediate_operand" "=Z,v,v,*Y,*r,*r,v,v")

68074

@@ -378,10 +403,10 @@

68075

68076

;; add

68077

(define_insn "add<mode>3"

68078

- [(set (match_operand:VI 0 "register_operand" "=v")

68079

- (plus:VI (match_operand:VI 1 "register_operand" "v")

68080

- (match_operand:VI 2 "register_operand" "v")))]

68081

- "TARGET_ALTIVEC"

68082

+ [(set (match_operand:VI2 0 "register_operand" "=v")

68083

+ (plus:VI2 (match_operand:VI2 1 "register_operand" "v")

68084

+ (match_operand:VI2 2 "register_operand" "v")))]

68085

+ "<VI_unit>"

68086

"vaddu<VI_char>m %0,%1,%2"

68087

[(set_attr "type" "vecsimple")])

68088

68089

@@ -398,7 +423,7 @@

68090

(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")

68091

(match_operand:V4SI 2 "register_operand" "v")]

68092

UNSPEC_VADDCUW))]

68093

- "TARGET_ALTIVEC"

68094

+ "VECTOR_UNIT_ALTIVEC_P (V4SImode)"

68095

"vaddcuw %0,%1,%2"

68096

[(set_attr "type" "vecsimple")])

68097

68098

@@ -405,10 +430,10 @@

68099

(define_insn "altivec_vaddu<VI_char>s"

68100

[(set (match_operand:VI 0 "register_operand" "=v")

68101

(unspec:VI [(match_operand:VI 1 "register_operand" "v")

68102

- (match_operand:VI 2 "register_operand" "v")]

68103

+ (match_operand:VI 2 "register_operand" "v")]

68104

UNSPEC_VADDU))

68105

(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]

68106

- "TARGET_ALTIVEC"

68107

+ "<VI_unit>"

68108

"vaddu<VI_char>s %0,%1,%2"

68109

[(set_attr "type" "vecsimple")])

68110

68111

@@ -418,16 +443,16 @@

68112

(match_operand:VI 2 "register_operand" "v")]

68113

UNSPEC_VADDS))

68114

(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]

68115

- "TARGET_ALTIVEC"

68116

+ "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"

68117

"vadds<VI_char>s %0,%1,%2"

68118

[(set_attr "type" "vecsimple")])

68119

68120

;; sub

68121

(define_insn "sub<mode>3"

68122

- [(set (match_operand:VI 0 "register_operand" "=v")

68123

- (minus:VI (match_operand:VI 1 "register_operand" "v")

68124

- (match_operand:VI 2 "register_operand" "v")))]

68125

- "TARGET_ALTIVEC"

68126

+ [(set (match_operand:VI2 0 "register_operand" "=v")

68127

+ (minus:VI2 (match_operand:VI2 1 "register_operand" "v")

68128

+ (match_operand:VI2 2 "register_operand" "v")))]

68129

+ "<VI_unit>"

68130

"vsubu<VI_char>m %0,%1,%2"

68131

[(set_attr "type" "vecsimple")])

68132

68133

@@ -444,7 +469,7 @@

68134

(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")

68135

(match_operand:V4SI 2 "register_operand" "v")]

68136

UNSPEC_VSUBCUW))]

68137

- "TARGET_ALTIVEC"

68138

+ "VECTOR_UNIT_ALTIVEC_P (V4SImode)"

68139

"vsubcuw %0,%1,%2"

68140

[(set_attr "type" "vecsimple")])

68141

68142

@@ -454,7 +479,7 @@

68143

(match_operand:VI 2 "register_operand" "v")]

68144

UNSPEC_VSUBU))

68145

(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]

68146

- "TARGET_ALTIVEC"

68147

+ "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"

68148

"vsubu<VI_char>s %0,%1,%2"

68149

[(set_attr "type" "vecsimple")])

68150

68151

@@ -464,7 +489,7 @@

68152

(match_operand:VI 2 "register_operand" "v")]

68153

UNSPEC_VSUBS))

68154

(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]

68155

- "TARGET_ALTIVEC"

68156

+ "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"

68157

"vsubs<VI_char>s %0,%1,%2"

68158

[(set_attr "type" "vecsimple")])

68159

68160

@@ -483,7 +508,7 @@

68161

(unspec:VI [(match_operand:VI 1 "register_operand" "v")

68162

(match_operand:VI 2 "register_operand" "v")]

68163

UNSPEC_VAVGS))]

68164

- "TARGET_ALTIVEC"

68165

+ "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"

68166

"vavgs<VI_char> %0,%1,%2"

68167

[(set_attr "type" "vecsimple")])

68168

68169

@@ -492,31 +517,31 @@

68170

(unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")

68171

(match_operand:V4SF 2 "register_operand" "v")]

68172

UNSPEC_VCMPBFP))]

68173

- "TARGET_ALTIVEC"

68174

+ "VECTOR_UNIT_ALTIVEC_P (V4SImode)"

68175

"vcmpbfp %0,%1,%2"

68176

[(set_attr "type" "veccmp")])

68177

68178

(define_insn "*altivec_eq<mode>"

68179

- [(set (match_operand:VI 0 "altivec_register_operand" "=v")

68180

- (eq:VI (match_operand:VI 1 "altivec_register_operand" "v")

68181

- (match_operand:VI 2 "altivec_register_operand" "v")))]

68182

- "TARGET_ALTIVEC"

68183

+ [(set (match_operand:VI2 0 "altivec_register_operand" "=v")

68184

+ (eq:VI2 (match_operand:VI2 1 "altivec_register_operand" "v")

68185

+ (match_operand:VI2 2 "altivec_register_operand" "v")))]

68186

+ "<VI_unit>"

68187

"vcmpequ<VI_char> %0,%1,%2"

68188

[(set_attr "type" "veccmp")])

68189

68190

(define_insn "*altivec_gt<mode>"

68191

- [(set (match_operand:VI 0 "altivec_register_operand" "=v")

68192

- (gt:VI (match_operand:VI 1 "altivec_register_operand" "v")

68193

- (match_operand:VI 2 "altivec_register_operand" "v")))]

68194

- "TARGET_ALTIVEC"

68195

+ [(set (match_operand:VI2 0 "altivec_register_operand" "=v")

68196

+ (gt:VI2 (match_operand:VI2 1 "altivec_register_operand" "v")

68197

+ (match_operand:VI2 2 "altivec_register_operand" "v")))]

68198

+ "<VI_unit>"

68199

"vcmpgts<VI_char> %0,%1,%2"

68200

[(set_attr "type" "veccmp")])

68201

68202

(define_insn "*altivec_gtu<mode>"

68203

- [(set (match_operand:VI 0 "altivec_register_operand" "=v")

68204

- (gtu:VI (match_operand:VI 1 "altivec_register_operand" "v")

68205

- (match_operand:VI 2 "altivec_register_operand" "v")))]

68206

- "TARGET_ALTIVEC"

68207

+ [(set (match_operand:VI2 0 "altivec_register_operand" "=v")

68208

+ (gtu:VI2 (match_operand:VI2 1 "altivec_register_operand" "v")

68209

+ (match_operand:VI2 2 "altivec_register_operand" "v")))]

68210

+ "<VI_unit>"

68211

"vcmpgtu<VI_char> %0,%1,%2"

68212

[(set_attr "type" "veccmp")])

68213

68214

@@ -642,7 +667,7 @@

68215

convert_move (small_swap, swap, 0);

68216

68217

low_product = gen_reg_rtx (V4SImode);

68218

- emit_insn (gen_vec_widen_umult_odd_v8hi (low_product, one, two));

68219

+ emit_insn (gen_altivec_vmulouh (low_product, one, two));

68220

68221

high_product = gen_reg_rtx (V4SImode);

68222

emit_insn (gen_altivec_vmsumuhm (high_product, one, small_swap, zero));

68223

@@ -666,14 +691,23 @@

68224

rtx high = gen_reg_rtx (V4SImode);

68225

rtx low = gen_reg_rtx (V4SImode);

68226

68227

- emit_insn (gen_vec_widen_smult_even_v8hi (even, operands[1], operands[2]));

68228

- emit_insn (gen_vec_widen_smult_odd_v8hi (odd, operands[1], operands[2]));

68229

+ if (BYTES_BIG_ENDIAN)

68230

+ {

68231

+ emit_insn (gen_altivec_vmulesh (even, operands[1], operands[2]));

68232

+ emit_insn (gen_altivec_vmulosh (odd, operands[1], operands[2]));

68233

+ emit_insn (gen_altivec_vmrghw_direct (high, even, odd));

68234

+ emit_insn (gen_altivec_vmrglw_direct (low, even, odd));

68235

+ emit_insn (gen_altivec_vpkuwum_direct (operands[0], high, low));

68236

+ }

68237

+ else

68238

+ {

68239

+ emit_insn (gen_altivec_vmulosh (even, operands[1], operands[2]));

68240

+ emit_insn (gen_altivec_vmulesh (odd, operands[1], operands[2]));

68241

+ emit_insn (gen_altivec_vmrghw_direct (high, odd, even));

68242

+ emit_insn (gen_altivec_vmrglw_direct (low, odd, even));

68243

+ emit_insn (gen_altivec_vpkuwum_direct (operands[0], low, high));

68244

+ }

68245

68246

- emit_insn (gen_altivec_vmrghw (high, even, odd));

68247

- emit_insn (gen_altivec_vmrglw (low, even, odd));

68248

-

68249

- emit_insn (gen_altivec_vpkuwum (operands[0], high, low));

68250

-

68251

DONE;

68252

}")

68253

68254

@@ -744,18 +778,18 @@

68255

;; max

68256

68257

(define_insn "umax<mode>3"

68258

- [(set (match_operand:VI 0 "register_operand" "=v")

68259

- (umax:VI (match_operand:VI 1 "register_operand" "v")

68260

- (match_operand:VI 2 "register_operand" "v")))]

68261

- "TARGET_ALTIVEC"

68262

+ [(set (match_operand:VI2 0 "register_operand" "=v")

68263

+ (umax:VI2 (match_operand:VI2 1 "register_operand" "v")

68264

+ (match_operand:VI2 2 "register_operand" "v")))]

68265

+ "<VI_unit>"

68266

"vmaxu<VI_char> %0,%1,%2"

68267

[(set_attr "type" "vecsimple")])

68268

68269

(define_insn "smax<mode>3"

68270

- [(set (match_operand:VI 0 "register_operand" "=v")

68271

- (smax:VI (match_operand:VI 1 "register_operand" "v")

68272

- (match_operand:VI 2 "register_operand" "v")))]

68273

- "TARGET_ALTIVEC"

68274

+ [(set (match_operand:VI2 0 "register_operand" "=v")

68275

+ (smax:VI2 (match_operand:VI2 1 "register_operand" "v")

68276

+ (match_operand:VI2 2 "register_operand" "v")))]

68277

+ "<VI_unit>"

68278

"vmaxs<VI_char> %0,%1,%2"

68279

[(set_attr "type" "vecsimple")])

68280

68281

@@ -768,18 +802,18 @@

68282

[(set_attr "type" "veccmp")])

68283

68284

(define_insn "umin<mode>3"

68285

- [(set (match_operand:VI 0 "register_operand" "=v")

68286

- (umin:VI (match_operand:VI 1 "register_operand" "v")

68287

- (match_operand:VI 2 "register_operand" "v")))]

68288

- "TARGET_ALTIVEC"

68289

+ [(set (match_operand:VI2 0 "register_operand" "=v")

68290

+ (umin:VI2 (match_operand:VI2 1 "register_operand" "v")

68291

+ (match_operand:VI2 2 "register_operand" "v")))]

68292

+ "<VI_unit>"

68293

"vminu<VI_char> %0,%1,%2"

68294

[(set_attr "type" "vecsimple")])

68295

68296

(define_insn "smin<mode>3"

68297

- [(set (match_operand:VI 0 "register_operand" "=v")

68298

- (smin:VI (match_operand:VI 1 "register_operand" "v")

68299

- (match_operand:VI 2 "register_operand" "v")))]

68300

- "TARGET_ALTIVEC"

68301

+ [(set (match_operand:VI2 0 "register_operand" "=v")

68302

+ (smin:VI2 (match_operand:VI2 1 "register_operand" "v")

68303

+ (match_operand:VI2 2 "register_operand" "v")))]

68304

+ "<VI_unit>"

68305

"vmins<VI_char> %0,%1,%2"

68306

[(set_attr "type" "vecsimple")])

68307

68308

@@ -823,9 +857,41 @@

68309

"vmladduhm %0,%1,%2,%3"

68310

[(set_attr "type" "veccomplex")])

68311

68312

-(define_insn "altivec_vmrghb"

68313

+(define_expand "altivec_vmrghb"

68314

+ [(use (match_operand:V16QI 0 "register_operand" ""))

68315

+ (use (match_operand:V16QI 1 "register_operand" ""))

68316

+ (use (match_operand:V16QI 2 "register_operand" ""))]

68317

+ "TARGET_ALTIVEC"

68318

+{

68319

+ rtvec v;

68320

+ rtx x;

68321

+

68322

+ /* Special handling for LE with -maltivec=be. */

68323

+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)

68324

+ {

68325

+ v = gen_rtvec (16, GEN_INT (8), GEN_INT (24), GEN_INT (9), GEN_INT (25),

68326

+ GEN_INT (10), GEN_INT (26), GEN_INT (11), GEN_INT (27),

68327

+ GEN_INT (12), GEN_INT (28), GEN_INT (13), GEN_INT (29),

68328

+ GEN_INT (14), GEN_INT (30), GEN_INT (15), GEN_INT (31));

68329

+ x = gen_rtx_VEC_CONCAT (V32QImode, operands[2], operands[1]);

68330

+ }

68331

+ else

68332

+ {

68333

+ v = gen_rtvec (16, GEN_INT (0), GEN_INT (16), GEN_INT (1), GEN_INT (17),

68334

+ GEN_INT (2), GEN_INT (18), GEN_INT (3), GEN_INT (19),

68335

+ GEN_INT (4), GEN_INT (20), GEN_INT (5), GEN_INT (21),

68336

+ GEN_INT (6), GEN_INT (22), GEN_INT (7), GEN_INT (23));

68337

+ x = gen_rtx_VEC_CONCAT (V32QImode, operands[1], operands[2]);

68338

+ }

68339

+

68340

+ x = gen_rtx_VEC_SELECT (V16QImode, x, gen_rtx_PARALLEL (VOIDmode, v));

68341

+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));

68342

+ DONE;

68343

+})

68344

+

68345

+(define_insn "*altivec_vmrghb_internal"

68346

[(set (match_operand:V16QI 0 "register_operand" "=v")

68347

- (vec_select:V16QI

68348

+ (vec_select:V16QI

68349

(vec_concat:V32QI

68350

(match_operand:V16QI 1 "register_operand" "v")

68351

(match_operand:V16QI 2 "register_operand" "v"))

68352

@@ -838,12 +904,54 @@

68353

(const_int 6) (const_int 22)

68354

(const_int 7) (const_int 23)])))]

68355

"TARGET_ALTIVEC"

68356

+{

68357

+ if (BYTES_BIG_ENDIAN)

68358

+ return "vmrghb %0,%1,%2";

68359

+ else

68360

+ return "vmrglb %0,%2,%1";

68361

+}

68362

+ [(set_attr "type" "vecperm")])

68363

+

68364

+(define_insn "altivec_vmrghb_direct"

68365

+ [(set (match_operand:V16QI 0 "register_operand" "=v")

68366

+ (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")

68367

+ (match_operand:V16QI 2 "register_operand" "v")]

68368

+ UNSPEC_VMRGH_DIRECT))]

68369

+ "TARGET_ALTIVEC"

68370

"vmrghb %0,%1,%2"

68371

[(set_attr "type" "vecperm")])

68372

68373

-(define_insn "altivec_vmrghh"

68374

+(define_expand "altivec_vmrghh"

68375

+ [(use (match_operand:V8HI 0 "register_operand" ""))

68376

+ (use (match_operand:V8HI 1 "register_operand" ""))

68377

+ (use (match_operand:V8HI 2 "register_operand" ""))]

68378

+ "TARGET_ALTIVEC"

68379

+{

68380

+ rtvec v;

68381

+ rtx x;

68382

+

68383

+ /* Special handling for LE with -maltivec=be. */

68384

+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)

68385

+ {

68386

+ v = gen_rtvec (8, GEN_INT (4), GEN_INT (12), GEN_INT (5), GEN_INT (13),

68387

+ GEN_INT (6), GEN_INT (14), GEN_INT (7), GEN_INT (15));

68388

+ x = gen_rtx_VEC_CONCAT (V16HImode, operands[2], operands[1]);

68389

+ }

68390

+ else

68391

+ {

68392

+ v = gen_rtvec (8, GEN_INT (0), GEN_INT (8), GEN_INT (1), GEN_INT (9),

68393

+ GEN_INT (2), GEN_INT (10), GEN_INT (3), GEN_INT (11));

68394

+ x = gen_rtx_VEC_CONCAT (V16HImode, operands[1], operands[2]);

68395

+ }

68396

+

68397

+ x = gen_rtx_VEC_SELECT (V8HImode, x, gen_rtx_PARALLEL (VOIDmode, v));

68398

+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));

68399

+ DONE;

68400

+})

68401

+

68402

+(define_insn "*altivec_vmrghh_internal"

68403

[(set (match_operand:V8HI 0 "register_operand" "=v")

68404

- (vec_select:V8HI

68405

+ (vec_select:V8HI

68406

(vec_concat:V16HI

68407

(match_operand:V8HI 1 "register_operand" "v")

68408

(match_operand:V8HI 2 "register_operand" "v"))

68409

@@ -852,10 +960,50 @@

68410

(const_int 2) (const_int 10)

68411

(const_int 3) (const_int 11)])))]

68412

"TARGET_ALTIVEC"

68413

+{

68414

+ if (BYTES_BIG_ENDIAN)

68415

+ return "vmrghh %0,%1,%2";

68416

+ else

68417

+ return "vmrglh %0,%2,%1";

68418

+}

68419

+ [(set_attr "type" "vecperm")])

68420

+

68421

+(define_insn "altivec_vmrghh_direct"

68422

+ [(set (match_operand:V8HI 0 "register_operand" "=v")

68423

+ (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")

68424

+ (match_operand:V8HI 2 "register_operand" "v")]

68425

+ UNSPEC_VMRGH_DIRECT))]

68426

+ "TARGET_ALTIVEC"

68427

"vmrghh %0,%1,%2"

68428

[(set_attr "type" "vecperm")])

68429

68430

-(define_insn "altivec_vmrghw"

68431

+(define_expand "altivec_vmrghw"

68432

+ [(use (match_operand:V4SI 0 "register_operand" ""))

68433

+ (use (match_operand:V4SI 1 "register_operand" ""))

68434

+ (use (match_operand:V4SI 2 "register_operand" ""))]

68435

+ "VECTOR_MEM_ALTIVEC_P (V4SImode)"

68436

+{

68437

+ rtvec v;

68438

+ rtx x;

68439

+

68440

+ /* Special handling for LE with -maltivec=be. */

68441

+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)

68442

+ {

68443

+ v = gen_rtvec (4, GEN_INT (2), GEN_INT (6), GEN_INT (3), GEN_INT (7));

68444

+ x = gen_rtx_VEC_CONCAT (V8SImode, operands[2], operands[1]);

68445

+ }

68446

+ else

68447

+ {

68448

+ v = gen_rtvec (4, GEN_INT (0), GEN_INT (4), GEN_INT (1), GEN_INT (5));

68449

+ x = gen_rtx_VEC_CONCAT (V8SImode, operands[1], operands[2]);

68450

+ }

68451

+

68452

+ x = gen_rtx_VEC_SELECT (V4SImode, x, gen_rtx_PARALLEL (VOIDmode, v));

68453

+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));

68454

+ DONE;

68455

+})

68456

+

68457

+(define_insn "*altivec_vmrghw_internal"

68458

[(set (match_operand:V4SI 0 "register_operand" "=v")

68459

(vec_select:V4SI

68460

(vec_concat:V8SI

68461

@@ -864,6 +1012,20 @@

68462

(parallel [(const_int 0) (const_int 4)

68463

(const_int 1) (const_int 5)])))]

68464

"VECTOR_MEM_ALTIVEC_P (V4SImode)"

68465

+{

68466

+ if (BYTES_BIG_ENDIAN)

68467

+ return "vmrghw %0,%1,%2";

68468

+ else

68469

+ return "vmrglw %0,%2,%1";

68470

+}

68471

+ [(set_attr "type" "vecperm")])

68472

+

68473

+(define_insn "altivec_vmrghw_direct"

68474

+ [(set (match_operand:V4SI 0 "register_operand" "=v")

68475

+ (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")

68476

+ (match_operand:V4SI 2 "register_operand" "v")]

68477

+ UNSPEC_VMRGH_DIRECT))]

68478

+ "TARGET_ALTIVEC"

68479

"vmrghw %0,%1,%2"

68480

[(set_attr "type" "vecperm")])

68481

68482

@@ -876,10 +1038,47 @@

68483

(parallel [(const_int 0) (const_int 4)

68484

(const_int 1) (const_int 5)])))]

68485

"VECTOR_MEM_ALTIVEC_P (V4SFmode)"

68486

- "vmrghw %0,%1,%2"

68487

+{

68488

+ if (BYTES_BIG_ENDIAN)

68489

+ return "vmrghw %0,%1,%2";

68490

+ else

68491

+ return "vmrglw %0,%2,%1";

68492

+}

68493

[(set_attr "type" "vecperm")])

68494

68495

-(define_insn "altivec_vmrglb"

68496

+(define_expand "altivec_vmrglb"

68497

+ [(use (match_operand:V16QI 0 "register_operand" ""))

68498

+ (use (match_operand:V16QI 1 "register_operand" ""))

68499

+ (use (match_operand:V16QI 2 "register_operand" ""))]

68500

+ "TARGET_ALTIVEC"

68501

+{

68502

+ rtvec v;

68503

+ rtx x;

68504

+

68505

+ /* Special handling for LE with -maltivec=be. */

68506

+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)

68507

+ {

68508

+ v = gen_rtvec (16, GEN_INT (0), GEN_INT (16), GEN_INT (1), GEN_INT (17),

68509

+ GEN_INT (2), GEN_INT (18), GEN_INT (3), GEN_INT (19),

68510

+ GEN_INT (4), GEN_INT (20), GEN_INT (5), GEN_INT (21),

68511

+ GEN_INT (6), GEN_INT (22), GEN_INT (7), GEN_INT (23));

68512

+ x = gen_rtx_VEC_CONCAT (V32QImode, operands[2], operands[1]);

68513

+ }

68514

+ else

68515

+ {

68516

+ v = gen_rtvec (16, GEN_INT (8), GEN_INT (24), GEN_INT (9), GEN_INT (25),

68517

+ GEN_INT (10), GEN_INT (26), GEN_INT (11), GEN_INT (27),

68518

+ GEN_INT (12), GEN_INT (28), GEN_INT (13), GEN_INT (29),

68519

+ GEN_INT (14), GEN_INT (30), GEN_INT (15), GEN_INT (31));

68520

+ x = gen_rtx_VEC_CONCAT (V32QImode, operands[1], operands[2]);

68521

+ }

68522

+

68523

+ x = gen_rtx_VEC_SELECT (V16QImode, x, gen_rtx_PARALLEL (VOIDmode, v));

68524

+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));

68525

+ DONE;

68526

+})

68527

+

68528

+(define_insn "*altivec_vmrglb_internal"

68529

[(set (match_operand:V16QI 0 "register_operand" "=v")

68530

(vec_select:V16QI

68531

(vec_concat:V32QI

68532

@@ -894,10 +1093,52 @@

68533

(const_int 14) (const_int 30)

68534

(const_int 15) (const_int 31)])))]

68535

"TARGET_ALTIVEC"

68536

+{

68537

+ if (BYTES_BIG_ENDIAN)

68538

+ return "vmrglb %0,%1,%2";

68539

+ else

68540

+ return "vmrghb %0,%2,%1";

68541

+}

68542

+ [(set_attr "type" "vecperm")])

68543

+

68544

+(define_insn "altivec_vmrglb_direct"

68545

+ [(set (match_operand:V16QI 0 "register_operand" "=v")

68546

+ (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")

68547

+ (match_operand:V16QI 2 "register_operand" "v")]

68548

+ UNSPEC_VMRGL_DIRECT))]

68549

+ "TARGET_ALTIVEC"

68550

"vmrglb %0,%1,%2"

68551

[(set_attr "type" "vecperm")])

68552

68553

-(define_insn "altivec_vmrglh"

68554

+(define_expand "altivec_vmrglh"

68555

+ [(use (match_operand:V8HI 0 "register_operand" ""))

68556

+ (use (match_operand:V8HI 1 "register_operand" ""))

68557

+ (use (match_operand:V8HI 2 "register_operand" ""))]

68558

+ "TARGET_ALTIVEC"

68559

+{

68560

+ rtvec v;

68561

+ rtx x;

68562

+

68563

+ /* Special handling for LE with -maltivec=be. */

68564

+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)

68565

+ {

68566

+ v = gen_rtvec (8, GEN_INT (0), GEN_INT (8), GEN_INT (1), GEN_INT (9),

68567

+ GEN_INT (2), GEN_INT (10), GEN_INT (3), GEN_INT (11));

68568

+ x = gen_rtx_VEC_CONCAT (V16HImode, operands[2], operands[1]);

68569

+ }

68570

+ else

68571

+ {

68572

+ v = gen_rtvec (8, GEN_INT (4), GEN_INT (12), GEN_INT (5), GEN_INT (13),

68573

+ GEN_INT (6), GEN_INT (14), GEN_INT (7), GEN_INT (15));

68574

+ x = gen_rtx_VEC_CONCAT (V16HImode, operands[1], operands[2]);

68575

+ }

68576

+

68577

+ x = gen_rtx_VEC_SELECT (V8HImode, x, gen_rtx_PARALLEL (VOIDmode, v));

68578

+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));

68579

+ DONE;

68580

+})

68581

+

68582

+(define_insn "*altivec_vmrglh_internal"

68583

[(set (match_operand:V8HI 0 "register_operand" "=v")

68584

(vec_select:V8HI

68585

(vec_concat:V16HI

68586

@@ -908,10 +1149,50 @@

68587

(const_int 6) (const_int 14)

68588

(const_int 7) (const_int 15)])))]

68589

"TARGET_ALTIVEC"

68590

+{

68591

+ if (BYTES_BIG_ENDIAN)

68592

+ return "vmrglh %0,%1,%2";

68593

+ else

68594

+ return "vmrghh %0,%2,%1";

68595

+}

68596

+ [(set_attr "type" "vecperm")])

68597

+

68598

+(define_insn "altivec_vmrglh_direct"

68599

+ [(set (match_operand:V8HI 0 "register_operand" "=v")

68600

+ (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")

68601

+ (match_operand:V8HI 2 "register_operand" "v")]

68602

+ UNSPEC_VMRGL_DIRECT))]

68603

+ "TARGET_ALTIVEC"

68604

"vmrglh %0,%1,%2"

68605

[(set_attr "type" "vecperm")])

68606

68607

-(define_insn "altivec_vmrglw"

68608

+(define_expand "altivec_vmrglw"

68609

+ [(use (match_operand:V4SI 0 "register_operand" ""))

68610

+ (use (match_operand:V4SI 1 "register_operand" ""))

68611

+ (use (match_operand:V4SI 2 "register_operand" ""))]

68612

+ "VECTOR_MEM_ALTIVEC_P (V4SImode)"

68613

+{

68614

+ rtvec v;

68615

+ rtx x;

68616

+

68617

+ /* Special handling for LE with -maltivec=be. */

68618

+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)

68619

+ {

68620

+ v = gen_rtvec (4, GEN_INT (0), GEN_INT (4), GEN_INT (1), GEN_INT (5));

68621

+ x = gen_rtx_VEC_CONCAT (V8SImode, operands[2], operands[1]);

68622

+ }

68623

+ else

68624

+ {

68625

+ v = gen_rtvec (4, GEN_INT (2), GEN_INT (6), GEN_INT (3), GEN_INT (7));

68626

+ x = gen_rtx_VEC_CONCAT (V8SImode, operands[1], operands[2]);

68627

+ }

68628

+

68629

+ x = gen_rtx_VEC_SELECT (V4SImode, x, gen_rtx_PARALLEL (VOIDmode, v));

68630

+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));

68631

+ DONE;

68632

+})

68633

+

68634

+(define_insn "*altivec_vmrglw_internal"

68635

[(set (match_operand:V4SI 0 "register_operand" "=v")

68636

(vec_select:V4SI

68637

(vec_concat:V8SI

68638

@@ -920,6 +1201,20 @@

68639

(parallel [(const_int 2) (const_int 6)

68640

(const_int 3) (const_int 7)])))]

68641

"VECTOR_MEM_ALTIVEC_P (V4SImode)"

68642

+{

68643

+ if (BYTES_BIG_ENDIAN)

68644

+ return "vmrglw %0,%1,%2";

68645

+ else

68646

+ return "vmrghw %0,%2,%1";

68647

+}

68648

+ [(set_attr "type" "vecperm")])

68649

+

68650

+(define_insn "altivec_vmrglw_direct"

68651

+ [(set (match_operand:V4SI 0 "register_operand" "=v")

68652

+ (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")

68653

+ (match_operand:V4SI 2 "register_operand" "v")]

68654

+ UNSPEC_VMRGL_DIRECT))]

68655

+ "TARGET_ALTIVEC"

68656

"vmrglw %0,%1,%2"

68657

[(set_attr "type" "vecperm")])

68658

68659

@@ -932,10 +1227,154 @@

68660

(parallel [(const_int 2) (const_int 6)

68661

(const_int 3) (const_int 7)])))]

68662

"VECTOR_MEM_ALTIVEC_P (V4SFmode)"

68663

- "vmrglw %0,%1,%2"

68664

+{

68665

+ if (BYTES_BIG_ENDIAN)

68666

+ return "vmrglw %0,%1,%2";

68667

+ else

68668

+ return "vmrghw %0,%2,%1";

68669

+}

68670

[(set_attr "type" "vecperm")])

68671

68672

-(define_insn "vec_widen_umult_even_v16qi"

68673

+;; Power8 vector merge even/odd

68674

+(define_insn "p8_vmrgew"

68675

+ [(set (match_operand:V4SI 0 "register_operand" "=v")

68676

+ (vec_select:V4SI

68677

+ (vec_concat:V8SI

68678

+ (match_operand:V4SI 1 "register_operand" "v")

68679

+ (match_operand:V4SI 2 "register_operand" "v"))

68680

+ (parallel [(const_int 0) (const_int 4)

68681

+ (const_int 2) (const_int 6)])))]

68682

+ "TARGET_P8_VECTOR"

68683

+{

68684

+ if (BYTES_BIG_ENDIAN)

68685

+ return "vmrgew %0,%1,%2";

68686

+ else

68687

+ return "vmrgow %0,%2,%1";

68688

+}

68689

+ [(set_attr "type" "vecperm")])

68690

+

68691

+(define_insn "p8_vmrgow"

68692

+ [(set (match_operand:V4SI 0 "register_operand" "=v")

68693

+ (vec_select:V4SI

68694

+ (vec_concat:V8SI

68695

+ (match_operand:V4SI 1 "register_operand" "v")

68696

+ (match_operand:V4SI 2 "register_operand" "v"))

68697

+ (parallel [(const_int 1) (const_int 5)

68698

+ (const_int 3) (const_int 7)])))]

68699

+ "TARGET_P8_VECTOR"

68700

+{

68701

+ if (BYTES_BIG_ENDIAN)

68702

+ return "vmrgow %0,%1,%2";

68703

+ else

68704

+ return "vmrgew %0,%2,%1";

68705

+}

68706

+ [(set_attr "type" "vecperm")])

68707

+

68708

+(define_expand "vec_widen_umult_even_v16qi"

68709

+ [(use (match_operand:V8HI 0 "register_operand" ""))

68710

+ (use (match_operand:V16QI 1 "register_operand" ""))

68711

+ (use (match_operand:V16QI 2 "register_operand" ""))]

68712

+ "TARGET_ALTIVEC"

68713

+{

68714

+ if (VECTOR_ELT_ORDER_BIG)

68715

+ emit_insn (gen_altivec_vmuleub (operands[0], operands[1], operands[2]));

68716

+ else

68717

+ emit_insn (gen_altivec_vmuloub (operands[0], operands[1], operands[2]));

68718

+ DONE;

68719

+})

68720

+

68721

+(define_expand "vec_widen_smult_even_v16qi"

68722

+ [(use (match_operand:V8HI 0 "register_operand" ""))

68723

+ (use (match_operand:V16QI 1 "register_operand" ""))

68724

+ (use (match_operand:V16QI 2 "register_operand" ""))]

68725

+ "TARGET_ALTIVEC"

68726

+{

68727

+ if (VECTOR_ELT_ORDER_BIG)

68728

+ emit_insn (gen_altivec_vmulesb (operands[0], operands[1], operands[2]));

68729

+ else

68730

+ emit_insn (gen_altivec_vmulosb (operands[0], operands[1], operands[2]));

68731

+ DONE;

68732

+})

68733

+

68734

+(define_expand "vec_widen_umult_even_v8hi"

68735

+ [(use (match_operand:V4SI 0 "register_operand" ""))

68736

+ (use (match_operand:V8HI 1 "register_operand" ""))

68737

+ (use (match_operand:V8HI 2 "register_operand" ""))]

68738

+ "TARGET_ALTIVEC"

68739

+{

68740

+ if (VECTOR_ELT_ORDER_BIG)

68741

+ emit_insn (gen_altivec_vmuleuh (operands[0], operands[1], operands[2]));

68742

+ else

68743

+ emit_insn (gen_altivec_vmulouh (operands[0], operands[1], operands[2]));

68744

+ DONE;

68745

+})

68746

+

68747

+(define_expand "vec_widen_smult_even_v8hi"

68748

+ [(use (match_operand:V4SI 0 "register_operand" ""))

68749

+ (use (match_operand:V8HI 1 "register_operand" ""))

68750

+ (use (match_operand:V8HI 2 "register_operand" ""))]

68751

+ "TARGET_ALTIVEC"

68752

+{

68753

+ if (VECTOR_ELT_ORDER_BIG)

68754

+ emit_insn (gen_altivec_vmulesh (operands[0], operands[1], operands[2]));

68755

+ else

68756

+ emit_insn (gen_altivec_vmulosh (operands[0], operands[1], operands[2]));

68757

+ DONE;

68758

+})

68759

+

68760

+(define_expand "vec_widen_umult_odd_v16qi"

68761

+ [(use (match_operand:V8HI 0 "register_operand" ""))

68762

+ (use (match_operand:V16QI 1 "register_operand" ""))

68763

+ (use (match_operand:V16QI 2 "register_operand" ""))]

68764

+ "TARGET_ALTIVEC"

68765

+{

68766

+ if (VECTOR_ELT_ORDER_BIG)

68767

+ emit_insn (gen_altivec_vmuloub (operands[0], operands[1], operands[2]));

68768

+ else

68769

+ emit_insn (gen_altivec_vmuleub (operands[0], operands[1], operands[2]));

68770

+ DONE;

68771

+})

68772

+

68773

+(define_expand "vec_widen_smult_odd_v16qi"

68774

+ [(use (match_operand:V8HI 0 "register_operand" ""))

68775

+ (use (match_operand:V16QI 1 "register_operand" ""))

68776

+ (use (match_operand:V16QI 2 "register_operand" ""))]

68777

+ "TARGET_ALTIVEC"

68778

+{

68779

+ if (VECTOR_ELT_ORDER_BIG)

68780

+ emit_insn (gen_altivec_vmulosb (operands[0], operands[1], operands[2]));

68781

+ else

68782

+ emit_insn (gen_altivec_vmulesb (operands[0], operands[1], operands[2]));

68783

+ DONE;

68784

+})

68785

+

68786

+(define_expand "vec_widen_umult_odd_v8hi"

68787

+ [(use (match_operand:V4SI 0 "register_operand" ""))

68788

+ (use (match_operand:V8HI 1 "register_operand" ""))

68789

+ (use (match_operand:V8HI 2 "register_operand" ""))]

68790

+ "TARGET_ALTIVEC"

68791

+{

68792

+ if (VECTOR_ELT_ORDER_BIG)

68793

+ emit_insn (gen_altivec_vmulouh (operands[0], operands[1], operands[2]));

68794

+ else

68795

+ emit_insn (gen_altivec_vmuleuh (operands[0], operands[1], operands[2]));

68796

+ DONE;

68797

+})

68798

+

68799

+(define_expand "vec_widen_smult_odd_v8hi"

68800

+ [(use (match_operand:V4SI 0 "register_operand" ""))

68801

+ (use (match_operand:V8HI 1 "register_operand" ""))

68802

+ (use (match_operand:V8HI 2 "register_operand" ""))]

68803

+ "TARGET_ALTIVEC"

68804

+{

68805

+ if (VECTOR_ELT_ORDER_BIG)

68806

+ emit_insn (gen_altivec_vmulosh (operands[0], operands[1], operands[2]));

68807

+ else

68808

+ emit_insn (gen_altivec_vmulesh (operands[0], operands[1], operands[2]));

68809

+ DONE;

68810

+})

68811

+

68812

+(define_insn "altivec_vmuleub"

68813

[(set (match_operand:V8HI 0 "register_operand" "=v")

68814

(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")

68815

(match_operand:V16QI 2 "register_operand" "v")]

68816

@@ -944,43 +1383,25 @@

68817

"vmuleub %0,%1,%2"

68818

[(set_attr "type" "veccomplex")])

68819

68820

-(define_insn "vec_widen_smult_even_v16qi"

68821

+(define_insn "altivec_vmuloub"

68822

[(set (match_operand:V8HI 0 "register_operand" "=v")

68823

(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")

68824

(match_operand:V16QI 2 "register_operand" "v")]

68825

- UNSPEC_VMULESB))]

68826

+ UNSPEC_VMULOUB))]

68827

"TARGET_ALTIVEC"

68828

- "vmulesb %0,%1,%2"

68829

+ "vmuloub %0,%1,%2"

68830

[(set_attr "type" "veccomplex")])

68831

68832

-(define_insn "vec_widen_umult_even_v8hi"

68833

- [(set (match_operand:V4SI 0 "register_operand" "=v")

68834

- (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")

68835

- (match_operand:V8HI 2 "register_operand" "v")]

68836

- UNSPEC_VMULEUH))]

68837

- "TARGET_ALTIVEC"

68838

- "vmuleuh %0,%1,%2"

68839

- [(set_attr "type" "veccomplex")])

68840

-

68841

-(define_insn "vec_widen_smult_even_v8hi"

68842

- [(set (match_operand:V4SI 0 "register_operand" "=v")

68843

- (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")

68844

- (match_operand:V8HI 2 "register_operand" "v")]

68845

- UNSPEC_VMULESH))]

68846

- "TARGET_ALTIVEC"

68847

- "vmulesh %0,%1,%2"

68848

- [(set_attr "type" "veccomplex")])

68849

-

68850

-(define_insn "vec_widen_umult_odd_v16qi"

68851

+(define_insn "altivec_vmulesb"

68852

[(set (match_operand:V8HI 0 "register_operand" "=v")

68853

(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")

68854

(match_operand:V16QI 2 "register_operand" "v")]

68855

- UNSPEC_VMULOUB))]

68856

+ UNSPEC_VMULESB))]

68857

"TARGET_ALTIVEC"

68858

- "vmuloub %0,%1,%2"

68859

+ "vmulesb %0,%1,%2"

68860

[(set_attr "type" "veccomplex")])

68861

68862

-(define_insn "vec_widen_smult_odd_v16qi"

68863

+(define_insn "altivec_vmulosb"

68864

[(set (match_operand:V8HI 0 "register_operand" "=v")

68865

(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")

68866

(match_operand:V16QI 2 "register_operand" "v")]

68867

@@ -989,19 +1410,37 @@

68868

"vmulosb %0,%1,%2"

68869

[(set_attr "type" "veccomplex")])

68870

68871

-(define_insn "vec_widen_umult_odd_v8hi"

68872

+(define_insn "altivec_vmuleuh"

68873

[(set (match_operand:V4SI 0 "register_operand" "=v")

68874

(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")

68875

(match_operand:V8HI 2 "register_operand" "v")]

68876

+ UNSPEC_VMULEUH))]

68877

+ "TARGET_ALTIVEC"

68878

+ "vmuleuh %0,%1,%2"

68879

+ [(set_attr "type" "veccomplex")])

68880

+

68881

+(define_insn "altivec_vmulouh"

68882

+ [(set (match_operand:V4SI 0 "register_operand" "=v")

68883

+ (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")

68884

+ (match_operand:V8HI 2 "register_operand" "v")]

68885

UNSPEC_VMULOUH))]

68886

"TARGET_ALTIVEC"

68887

"vmulouh %0,%1,%2"

68888

[(set_attr "type" "veccomplex")])

68889

68890

-(define_insn "vec_widen_smult_odd_v8hi"

68891

+(define_insn "altivec_vmulesh"

68892

[(set (match_operand:V4SI 0 "register_operand" "=v")

68893

(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")

68894

(match_operand:V8HI 2 "register_operand" "v")]

68895

+ UNSPEC_VMULESH))]

68896

+ "TARGET_ALTIVEC"

68897

+ "vmulesh %0,%1,%2"

68898

+ [(set_attr "type" "veccomplex")])

68899

+

68900

+(define_insn "altivec_vmulosh"

68901

+ [(set (match_operand:V4SI 0 "register_operand" "=v")

68902

+ (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")

68903

+ (match_operand:V8HI 2 "register_operand" "v")]

68904

UNSPEC_VMULOSH))]

68905

"TARGET_ALTIVEC"

68906

"vmulosh %0,%1,%2"

68907

@@ -1008,74 +1447,7 @@

68908

[(set_attr "type" "veccomplex")])

68909

68910

68911

-;; logical ops. Have the logical ops follow the memory ops in

68912

-;; terms of whether to prefer VSX or Altivec

68913

-

68914

-(define_insn "*altivec_and<mode>3"

68915

- [(set (match_operand:VM 0 "register_operand" "=v")

68916

- (and:VM (match_operand:VM 1 "register_operand" "v")

68917

- (match_operand:VM 2 "register_operand" "v")))]

68918

- "VECTOR_MEM_ALTIVEC_P (<MODE>mode)"

68919

- "vand %0,%1,%2"

68920

- [(set_attr "type" "vecsimple")])

68921

-

68922

-(define_insn "*altivec_ior<mode>3"

68923

- [(set (match_operand:VM 0 "register_operand" "=v")

68924

- (ior:VM (match_operand:VM 1 "register_operand" "v")

68925

- (match_operand:VM 2 "register_operand" "v")))]

68926

- "VECTOR_MEM_ALTIVEC_P (<MODE>mode)"

68927

- "vor %0,%1,%2"

68928

- [(set_attr "type" "vecsimple")])

68929

-

68930

-(define_insn "*altivec_xor<mode>3"

68931

- [(set (match_operand:VM 0 "register_operand" "=v")

68932

- (xor:VM (match_operand:VM 1 "register_operand" "v")

68933

- (match_operand:VM 2 "register_operand" "v")))]

68934

- "VECTOR_MEM_ALTIVEC_P (<MODE>mode)"

68935

- "vxor %0,%1,%2"

68936

- [(set_attr "type" "vecsimple")])

68937

-

68938

-(define_insn "*altivec_one_cmpl<mode>2"

68939

- [(set (match_operand:VM 0 "register_operand" "=v")

68940

- (not:VM (match_operand:VM 1 "register_operand" "v")))]

68941

- "VECTOR_MEM_ALTIVEC_P (<MODE>mode)"

68942

- "vnor %0,%1,%1"

68943

- [(set_attr "type" "vecsimple")])

68944

-

68945

-(define_insn "*altivec_nor<mode>3"

68946

- [(set (match_operand:VM 0 "register_operand" "=v")

68947

- (not:VM (ior:VM (match_operand:VM 1 "register_operand" "v")

68948

- (match_operand:VM 2 "register_operand" "v"))))]

68949

- "VECTOR_MEM_ALTIVEC_P (<MODE>mode)"

68950

- "vnor %0,%1,%2"

68951

- [(set_attr "type" "vecsimple")])

68952

-

68953

-(define_insn "*altivec_andc<mode>3"

68954

- [(set (match_operand:VM 0 "register_operand" "=v")

68955

- (and:VM (not:VM (match_operand:VM 2 "register_operand" "v"))

68956

- (match_operand:VM 1 "register_operand" "v")))]

68957

- "VECTOR_MEM_ALTIVEC_P (<MODE>mode)"

68958

- "vandc %0,%1,%2"

68959

- [(set_attr "type" "vecsimple")])

68960

-

68961

-(define_insn "altivec_vpkuhum"

68962

- [(set (match_operand:V16QI 0 "register_operand" "=v")

68963

- (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")

68964

- (match_operand:V8HI 2 "register_operand" "v")]

68965

- UNSPEC_VPKUHUM))]

68966

- "TARGET_ALTIVEC"

68967

- "vpkuhum %0,%1,%2"

68968

- [(set_attr "type" "vecperm")])

68969

-

68970

-(define_insn "altivec_vpkuwum"

68971

- [(set (match_operand:V8HI 0 "register_operand" "=v")

68972

- (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")

68973

- (match_operand:V4SI 2 "register_operand" "v")]

68974

- UNSPEC_VPKUWUM))]

68975

- "TARGET_ALTIVEC"

68976

- "vpkuwum %0,%1,%2"

68977

- [(set_attr "type" "vecperm")])

68978

-

68979

+;; Vector pack/unpack

68980

(define_insn "altivec_vpkpx"

68981

[(set (match_operand:V8HI 0 "register_operand" "=v")

68982

(unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")

68983

@@ -1082,74 +1454,95 @@

68984

(match_operand:V4SI 2 "register_operand" "v")]

68985

UNSPEC_VPKPX))]

68986

"TARGET_ALTIVEC"

68987

- "vpkpx %0,%1,%2"

68988

+ "*

68989

+ {

68990

+ if (VECTOR_ELT_ORDER_BIG)

68991

+ return \"vpkpx %0,%1,%2\";

68992

+ else

68993

+ return \"vpkpx %0,%2,%1\";

68994

+ }"

68995

[(set_attr "type" "vecperm")])

68996

68997

-(define_insn "altivec_vpkshss"

68998

- [(set (match_operand:V16QI 0 "register_operand" "=v")

68999

- (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")

69000

- (match_operand:V8HI 2 "register_operand" "v")]

69001

- UNSPEC_VPKSHSS))

69002

- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]

69003

- "TARGET_ALTIVEC"

69004

- "vpkshss %0,%1,%2"

69005

+(define_insn "altivec_vpks<VI_char>ss"

69006

+ [(set (match_operand:<VP_small> 0 "register_operand" "=v")

69007

+ (unspec:<VP_small> [(match_operand:VP 1 "register_operand" "v")

69008

+ (match_operand:VP 2 "register_operand" "v")]

69009

+ UNSPEC_VPACK_SIGN_SIGN_SAT))]

69010

+ "<VI_unit>"

69011

+ "*

69012

+ {

69013

+ if (VECTOR_ELT_ORDER_BIG)

69014

+ return \"vpks<VI_char>ss %0,%1,%2\";

69015

+ else

69016

+ return \"vpks<VI_char>ss %0,%2,%1\";

69017

+ }"

69018

[(set_attr "type" "vecperm")])

69019

69020

-(define_insn "altivec_vpkswss"

69021

- [(set (match_operand:V8HI 0 "register_operand" "=v")

69022

- (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")

69023

- (match_operand:V4SI 2 "register_operand" "v")]

69024

- UNSPEC_VPKSWSS))

69025

- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]

69026

- "TARGET_ALTIVEC"

69027

- "vpkswss %0,%1,%2"

69028

+(define_insn "altivec_vpks<VI_char>us"

69029

+ [(set (match_operand:<VP_small> 0 "register_operand" "=v")

69030

+ (unspec:<VP_small> [(match_operand:VP 1 "register_operand" "v")

69031

+ (match_operand:VP 2 "register_operand" "v")]

69032

+ UNSPEC_VPACK_SIGN_UNS_SAT))]

69033

+ "<VI_unit>"

69034

+ "*

69035

+ {

69036

+ if (VECTOR_ELT_ORDER_BIG)

69037

+ return \"vpks<VI_char>us %0,%1,%2\";

69038

+ else

69039

+ return \"vpks<VI_char>us %0,%2,%1\";

69040

+ }"

69041

[(set_attr "type" "vecperm")])

69042

69043

-(define_insn "altivec_vpkuhus"

69044

- [(set (match_operand:V16QI 0 "register_operand" "=v")

69045

- (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")

69046

- (match_operand:V8HI 2 "register_operand" "v")]

69047

- UNSPEC_VPKUHUS))

69048

- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]

69049

- "TARGET_ALTIVEC"

69050

- "vpkuhus %0,%1,%2"

69051

+(define_insn "altivec_vpku<VI_char>us"

69052

+ [(set (match_operand:<VP_small> 0 "register_operand" "=v")

69053

+ (unspec:<VP_small> [(match_operand:VP 1 "register_operand" "v")

69054

+ (match_operand:VP 2 "register_operand" "v")]

69055

+ UNSPEC_VPACK_UNS_UNS_SAT))]

69056

+ "<VI_unit>"

69057

+ "*

69058

+ {

69059

+ if (VECTOR_ELT_ORDER_BIG)

69060

+ return \"vpku<VI_char>us %0,%1,%2\";

69061

+ else

69062

+ return \"vpku<VI_char>us %0,%2,%1\";

69063

+ }"

69064

[(set_attr "type" "vecperm")])

69065

69066

-(define_insn "altivec_vpkshus"

69067

- [(set (match_operand:V16QI 0 "register_operand" "=v")

69068

- (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")

69069

- (match_operand:V8HI 2 "register_operand" "v")]

69070

- UNSPEC_VPKSHUS))

69071

- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]

69072

- "TARGET_ALTIVEC"

69073

- "vpkshus %0,%1,%2"

69074

+(define_insn "altivec_vpku<VI_char>um"

69075

+ [(set (match_operand:<VP_small> 0 "register_operand" "=v")

69076

+ (unspec:<VP_small> [(match_operand:VP 1 "register_operand" "v")

69077

+ (match_operand:VP 2 "register_operand" "v")]

69078

+ UNSPEC_VPACK_UNS_UNS_MOD))]

69079

+ "<VI_unit>"

69080

+ "*

69081

+ {

69082

+ if (VECTOR_ELT_ORDER_BIG)

69083

+ return \"vpku<VI_char>um %0,%1,%2\";

69084

+ else

69085

+ return \"vpku<VI_char>um %0,%2,%1\";

69086

+ }"

69087

[(set_attr "type" "vecperm")])

69088

69089

-(define_insn "altivec_vpkuwus"

69090

- [(set (match_operand:V8HI 0 "register_operand" "=v")

69091

- (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")

69092

- (match_operand:V4SI 2 "register_operand" "v")]

69093

- UNSPEC_VPKUWUS))

69094

- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]

69095

- "TARGET_ALTIVEC"

69096

- "vpkuwus %0,%1,%2"

69097

+(define_insn "altivec_vpku<VI_char>um_direct"

69098

+ [(set (match_operand:<VP_small> 0 "register_operand" "=v")

69099

+ (unspec:<VP_small> [(match_operand:VP 1 "register_operand" "v")

69100

+ (match_operand:VP 2 "register_operand" "v")]

69101

+ UNSPEC_VPACK_UNS_UNS_MOD_DIRECT))]

69102

+ "<VI_unit>"

69103

+ "*

69104

+ {

69105

+ if (BYTES_BIG_ENDIAN)

69106

+ return \"vpku<VI_char>um %0,%1,%2\";

69107

+ else

69108

+ return \"vpku<VI_char>um %0,%2,%1\";

69109

+ }"

69110

[(set_attr "type" "vecperm")])

69111

69112

-(define_insn "altivec_vpkswus"

69113

- [(set (match_operand:V8HI 0 "register_operand" "=v")

69114

- (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")

69115

- (match_operand:V4SI 2 "register_operand" "v")]

69116

- UNSPEC_VPKSWUS))

69117

- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]

69118

- "TARGET_ALTIVEC"

69119

- "vpkswus %0,%1,%2"

69120

- [(set_attr "type" "vecperm")])

69121

-

69122

(define_insn "*altivec_vrl<VI_char>"

69123

- [(set (match_operand:VI 0 "register_operand" "=v")

69124

- (rotate:VI (match_operand:VI 1 "register_operand" "v")

69125

- (match_operand:VI 2 "register_operand" "v")))]

69126

- "TARGET_ALTIVEC"

69127

+ [(set (match_operand:VI2 0 "register_operand" "=v")

69128

+ (rotate:VI2 (match_operand:VI2 1 "register_operand" "v")

69129

+ (match_operand:VI2 2 "register_operand" "v")))]

69130

+ "<VI_unit>"

69131

"vrl<VI_char> %0,%1,%2"

69132

[(set_attr "type" "vecsimple")])

69133

69134

@@ -1172,26 +1565,26 @@

69135

[(set_attr "type" "vecperm")])

69136

69137

(define_insn "*altivec_vsl<VI_char>"

69138

- [(set (match_operand:VI 0 "register_operand" "=v")

69139

- (ashift:VI (match_operand:VI 1 "register_operand" "v")

69140

- (match_operand:VI 2 "register_operand" "v")))]

69141

- "TARGET_ALTIVEC"

69142

+ [(set (match_operand:VI2 0 "register_operand" "=v")

69143

+ (ashift:VI2 (match_operand:VI2 1 "register_operand" "v")

69144

+ (match_operand:VI2 2 "register_operand" "v")))]

69145

+ "<VI_unit>"

69146

"vsl<VI_char> %0,%1,%2"

69147

[(set_attr "type" "vecsimple")])

69148

69149

(define_insn "*altivec_vsr<VI_char>"

69150

- [(set (match_operand:VI 0 "register_operand" "=v")

69151

- (lshiftrt:VI (match_operand:VI 1 "register_operand" "v")

69152

- (match_operand:VI 2 "register_operand" "v")))]

69153

- "TARGET_ALTIVEC"

69154

+ [(set (match_operand:VI2 0 "register_operand" "=v")

69155

+ (lshiftrt:VI2 (match_operand:VI2 1 "register_operand" "v")

69156

+ (match_operand:VI2 2 "register_operand" "v")))]

69157

+ "<VI_unit>"

69158

"vsr<VI_char> %0,%1,%2"

69159

[(set_attr "type" "vecsimple")])

69160

69161

(define_insn "*altivec_vsra<VI_char>"

69162

- [(set (match_operand:VI 0 "register_operand" "=v")

69163

- (ashiftrt:VI (match_operand:VI 1 "register_operand" "v")

69164

- (match_operand:VI 2 "register_operand" "v")))]

69165

- "TARGET_ALTIVEC"

69166

+ [(set (match_operand:VI2 0 "register_operand" "=v")

69167

+ (ashiftrt:VI2 (match_operand:VI2 1 "register_operand" "v")

69168

+ (match_operand:VI2 2 "register_operand" "v")))]

69169

+ "<VI_unit>"

69170

"vsra<VI_char> %0,%1,%2"

69171

[(set_attr "type" "vecsimple")])

69172

69173

@@ -1233,15 +1626,29 @@

69174

"vsum4s<VI_char>s %0,%1,%2"

69175

[(set_attr "type" "veccomplex")])

69176

69177

+;; FIXME: For the following two patterns, the scratch should only be

69178

+;; allocated for !VECTOR_ELT_ORDER_BIG, and the instructions should

69179

+;; be emitted separately.

69180

(define_insn "altivec_vsum2sws"

69181

[(set (match_operand:V4SI 0 "register_operand" "=v")

69182

(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")

69183

(match_operand:V4SI 2 "register_operand" "v")]

69184

UNSPEC_VSUM2SWS))

69185

- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]

69186

+ (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))

69187

+ (clobber (match_scratch:V4SI 3 "=v"))]

69188

"TARGET_ALTIVEC"

69189

- "vsum2sws %0,%1,%2"

69190

- [(set_attr "type" "veccomplex")])

69191

+{

69192

+ if (VECTOR_ELT_ORDER_BIG)

69193

+ return "vsum2sws %0,%1,%2";

69194

+ else

69195

+ return "vsldoi %3,%2,%2,12\n\tvsum2sws %3,%1,%3\n\tvsldoi %0,%3,%3,4";

69196

+}

69197

+ [(set_attr "type" "veccomplex")

69198

+ (set (attr "length")

69199

+ (if_then_else

69200

+ (match_test "VECTOR_ELT_ORDER_BIG")

69201

+ (const_string "4")

69202

+ (const_string "12")))])

69203

69204

(define_insn "altivec_vsumsws"

69205

[(set (match_operand:V4SI 0 "register_operand" "=v")

69206

@@ -1248,12 +1655,54 @@

69207

(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")

69208

(match_operand:V4SI 2 "register_operand" "v")]

69209

UNSPEC_VSUMSWS))

69210

+ (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))

69211

+ (clobber (match_scratch:V4SI 3 "=v"))]

69212

+ "TARGET_ALTIVEC"

69213

+{

69214

+ if (VECTOR_ELT_ORDER_BIG)

69215

+ return "vsumsws %0,%1,%2";

69216

+ else

69217

+ return "vspltw %3,%2,0\n\tvsumsws %3,%1,%3\n\tvsldoi %0,%3,%3,12";

69218

+}

69219

+ [(set_attr "type" "veccomplex")

69220

+ (set (attr "length")

69221

+ (if_then_else

69222

+ (match_test "(VECTOR_ELT_ORDER_BIG)")

69223

+ (const_string "4")

69224

+ (const_string "12")))])

69225

+

69226

+(define_insn "altivec_vsumsws_direct"

69227

+ [(set (match_operand:V4SI 0 "register_operand" "=v")

69228

+ (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")

69229

+ (match_operand:V4SI 2 "register_operand" "v")]

69230

+ UNSPEC_VSUMSWS_DIRECT))

69231

(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]

69232

"TARGET_ALTIVEC"

69233

"vsumsws %0,%1,%2"

69234

[(set_attr "type" "veccomplex")])

69235

69236

-(define_insn "altivec_vspltb"

69237

+(define_expand "altivec_vspltb"

69238

+ [(use (match_operand:V16QI 0 "register_operand" ""))

69239

+ (use (match_operand:V16QI 1 "register_operand" ""))

69240

+ (use (match_operand:QI 2 "u5bit_cint_operand" ""))]

69241

+ "TARGET_ALTIVEC"

69242

+{

69243

+ rtvec v;

69244

+ rtx x;

69245

+

69246

+ /* Special handling for LE with -maltivec=be. We have to reflect

69247

+ the actual selected index for the splat in the RTL. */

69248

+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)

69249

+ operands[2] = GEN_INT (15 - INTVAL (operands[2]));

69250

+

69251

+ v = gen_rtvec (1, operands[2]);

69252

+ x = gen_rtx_VEC_SELECT (QImode, operands[1], gen_rtx_PARALLEL (VOIDmode, v));

69253

+ x = gen_rtx_VEC_DUPLICATE (V16QImode, x);

69254

+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));

69255

+ DONE;

69256

+})

69257

+

69258

+(define_insn "*altivec_vspltb_internal"

69259

[(set (match_operand:V16QI 0 "register_operand" "=v")

69260

(vec_duplicate:V16QI

69261

(vec_select:QI (match_operand:V16QI 1 "register_operand" "v")

69262

@@ -1260,10 +1709,48 @@

69263

(parallel

69264

[(match_operand:QI 2 "u5bit_cint_operand" "")]))))]

69265

"TARGET_ALTIVEC"

69266

+{

69267

+ /* For true LE, this adjusts the selected index. For LE with

69268

+ -maltivec=be, this reverses what was done in the define_expand

69269

+ because the instruction already has big-endian bias. */

69270

+ if (!BYTES_BIG_ENDIAN)

69271

+ operands[2] = GEN_INT (15 - INTVAL (operands[2]));

69272

+

69273

+ return "vspltb %0,%1,%2";

69274

+}

69275

+ [(set_attr "type" "vecperm")])

69276

+

69277

+(define_insn "altivec_vspltb_direct"

69278

+ [(set (match_operand:V16QI 0 "register_operand" "=v")

69279

+ (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")

69280

+ (match_operand:QI 2 "u5bit_cint_operand" "i")]

69281

+ UNSPEC_VSPLT_DIRECT))]

69282

+ "TARGET_ALTIVEC"

69283

"vspltb %0,%1,%2"

69284

[(set_attr "type" "vecperm")])

69285

69286

-(define_insn "altivec_vsplth"

69287

+(define_expand "altivec_vsplth"

69288

+ [(use (match_operand:V8HI 0 "register_operand" ""))

69289

+ (use (match_operand:V8HI 1 "register_operand" ""))

69290

+ (use (match_operand:QI 2 "u5bit_cint_operand" ""))]

69291

+ "TARGET_ALTIVEC"

69292

+{

69293

+ rtvec v;

69294

+ rtx x;

69295

+

69296

+ /* Special handling for LE with -maltivec=be. We have to reflect

69297

+ the actual selected index for the splat in the RTL. */

69298

+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)

69299

+ operands[2] = GEN_INT (7 - INTVAL (operands[2]));

69300

+

69301

+ v = gen_rtvec (1, operands[2]);

69302

+ x = gen_rtx_VEC_SELECT (HImode, operands[1], gen_rtx_PARALLEL (VOIDmode, v));

69303

+ x = gen_rtx_VEC_DUPLICATE (V8HImode, x);

69304

+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));

69305

+ DONE;

69306

+})

69307

+

69308

+(define_insn "*altivec_vsplth_internal"

69309

[(set (match_operand:V8HI 0 "register_operand" "=v")

69310

(vec_duplicate:V8HI

69311

(vec_select:HI (match_operand:V8HI 1 "register_operand" "v")

69312

@@ -1270,10 +1757,48 @@

69313

(parallel

69314

[(match_operand:QI 2 "u5bit_cint_operand" "")]))))]

69315

"TARGET_ALTIVEC"

69316

+{

69317

+ /* For true LE, this adjusts the selected index. For LE with

69318

+ -maltivec=be, this reverses what was done in the define_expand

69319

+ because the instruction already has big-endian bias. */

69320

+ if (!BYTES_BIG_ENDIAN)

69321

+ operands[2] = GEN_INT (7 - INTVAL (operands[2]));

69322

+

69323

+ return "vsplth %0,%1,%2";

69324

+}

69325

+ [(set_attr "type" "vecperm")])

69326

+

69327

+(define_insn "altivec_vsplth_direct"

69328

+ [(set (match_operand:V8HI 0 "register_operand" "=v")

69329

+ (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")

69330

+ (match_operand:QI 2 "u5bit_cint_operand" "i")]

69331

+ UNSPEC_VSPLT_DIRECT))]

69332

+ "TARGET_ALTIVEC"

69333

"vsplth %0,%1,%2"

69334

[(set_attr "type" "vecperm")])

69335

69336

-(define_insn "altivec_vspltw"

69337

+(define_expand "altivec_vspltw"

69338

+ [(use (match_operand:V4SI 0 "register_operand" ""))

69339

+ (use (match_operand:V4SI 1 "register_operand" ""))

69340

+ (use (match_operand:QI 2 "u5bit_cint_operand" ""))]

69341

+ "TARGET_ALTIVEC"

69342

+{

69343

+ rtvec v;

69344

+ rtx x;

69345

+

69346

+ /* Special handling for LE with -maltivec=be. We have to reflect

69347

+ the actual selected index for the splat in the RTL. */

69348

+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)

69349

+ operands[2] = GEN_INT (3 - INTVAL (operands[2]));

69350

+

69351

+ v = gen_rtvec (1, operands[2]);

69352

+ x = gen_rtx_VEC_SELECT (SImode, operands[1], gen_rtx_PARALLEL (VOIDmode, v));

69353

+ x = gen_rtx_VEC_DUPLICATE (V4SImode, x);

69354

+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));

69355

+ DONE;

69356

+})

69357

+

69358

+(define_insn "*altivec_vspltw_internal"

69359

[(set (match_operand:V4SI 0 "register_operand" "=v")

69360

(vec_duplicate:V4SI

69361

(vec_select:SI (match_operand:V4SI 1 "register_operand" "v")

69362

@@ -1280,10 +1805,48 @@

69363

(parallel

69364

[(match_operand:QI 2 "u5bit_cint_operand" "i")]))))]

69365

"TARGET_ALTIVEC"

69366

+{

69367

+ /* For true LE, this adjusts the selected index. For LE with

69368

+ -maltivec=be, this reverses what was done in the define_expand

69369

+ because the instruction already has big-endian bias. */

69370

+ if (!BYTES_BIG_ENDIAN)

69371

+ operands[2] = GEN_INT (3 - INTVAL (operands[2]));

69372

+

69373

+ return "vspltw %0,%1,%2";

69374

+}

69375

+ [(set_attr "type" "vecperm")])

69376

+

69377

+(define_insn "altivec_vspltw_direct"

69378

+ [(set (match_operand:V4SI 0 "register_operand" "=v")

69379

+ (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")

69380

+ (match_operand:QI 2 "u5bit_cint_operand" "i")]

69381

+ UNSPEC_VSPLT_DIRECT))]

69382

+ "TARGET_ALTIVEC"

69383

"vspltw %0,%1,%2"

69384

[(set_attr "type" "vecperm")])

69385

69386

-(define_insn "altivec_vspltsf"

69387

+(define_expand "altivec_vspltsf"

69388

+ [(use (match_operand:V4SF 0 "register_operand" ""))

69389

+ (use (match_operand:V4SF 1 "register_operand" ""))

69390

+ (use (match_operand:QI 2 "u5bit_cint_operand" ""))]

69391

+ "TARGET_ALTIVEC"

69392

+{

69393

+ rtvec v;

69394

+ rtx x;

69395

+

69396

+ /* Special handling for LE with -maltivec=be. We have to reflect

69397

+ the actual selected index for the splat in the RTL. */

69398

+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)

69399

+ operands[2] = GEN_INT (3 - INTVAL (operands[2]));

69400

+

69401

+ v = gen_rtvec (1, operands[2]);

69402

+ x = gen_rtx_VEC_SELECT (SFmode, operands[1], gen_rtx_PARALLEL (VOIDmode, v));

69403

+ x = gen_rtx_VEC_DUPLICATE (V4SFmode, x);

69404

+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));

69405

+ DONE;

69406

+})

69407

+

69408

+(define_insn "*altivec_vspltsf_internal"

69409

[(set (match_operand:V4SF 0 "register_operand" "=v")

69410

(vec_duplicate:V4SF

69411

(vec_select:SF (match_operand:V4SF 1 "register_operand" "v")

69412

@@ -1290,7 +1853,15 @@

69413

(parallel

69414

[(match_operand:QI 2 "u5bit_cint_operand" "i")]))))]

69415

"VECTOR_UNIT_ALTIVEC_P (V4SFmode)"

69416

- "vspltw %0,%1,%2"

69417

+{

69418

+ /* For true LE, this adjusts the selected index. For LE with

69419

+ -maltivec=be, this reverses what was done in the define_expand

69420

+ because the instruction already has big-endian bias. */

69421

+ if (!BYTES_BIG_ENDIAN)

69422

+ operands[2] = GEN_INT (3 - INTVAL (operands[2]));

69423

+

69424

+ return "vspltw %0,%1,%2";

69425

+}

69426

[(set_attr "type" "vecperm")])

69427

69428

(define_insn "altivec_vspltis<VI_char>"

69429

@@ -1308,7 +1879,7 @@

69430

"vrfiz %0,%1"

69431

[(set_attr "type" "vecfloat")])

69432

69433

-(define_insn "altivec_vperm_<mode>"

69434

+(define_expand "altivec_vperm_<mode>"

69435

[(set (match_operand:VM 0 "register_operand" "=v")

69436

(unspec:VM [(match_operand:VM 1 "register_operand" "v")

69437

(match_operand:VM 2 "register_operand" "v")

69438

@@ -1315,10 +1886,25 @@

69439

(match_operand:V16QI 3 "register_operand" "v")]

69440

UNSPEC_VPERM))]

69441

"TARGET_ALTIVEC"

69442

+{

69443

+ if (!VECTOR_ELT_ORDER_BIG)

69444

+ {

69445

+ altivec_expand_vec_perm_le (operands);

69446

+ DONE;

69447

+ }

69448

+})

69449

+

69450

+(define_insn "*altivec_vperm_<mode>_internal"

69451

+ [(set (match_operand:VM 0 "register_operand" "=v")

69452

+ (unspec:VM [(match_operand:VM 1 "register_operand" "v")

69453

+ (match_operand:VM 2 "register_operand" "v")

69454

+ (match_operand:V16QI 3 "register_operand" "v")]

69455

+ UNSPEC_VPERM))]

69456

+ "TARGET_ALTIVEC"

69457

"vperm %0,%1,%2,%3"

69458

[(set_attr "type" "vecperm")])

69459

69460

-(define_insn "altivec_vperm_<mode>_uns"

69461

+(define_expand "altivec_vperm_<mode>_uns"

69462

[(set (match_operand:VM 0 "register_operand" "=v")

69463

(unspec:VM [(match_operand:VM 1 "register_operand" "v")

69464

(match_operand:VM 2 "register_operand" "v")

69465

@@ -1325,6 +1911,21 @@

69466

(match_operand:V16QI 3 "register_operand" "v")]

69467

UNSPEC_VPERM_UNS))]

69468

"TARGET_ALTIVEC"

69469

+{

69470

+ if (!VECTOR_ELT_ORDER_BIG)

69471

+ {

69472

+ altivec_expand_vec_perm_le (operands);

69473

+ DONE;

69474

+ }

69475

+})

69476

+

69477

+(define_insn "*altivec_vperm_<mode>_uns_internal"

69478

+ [(set (match_operand:VM 0 "register_operand" "=v")

69479

+ (unspec:VM [(match_operand:VM 1 "register_operand" "v")

69480

+ (match_operand:VM 2 "register_operand" "v")

69481

+ (match_operand:V16QI 3 "register_operand" "v")]

69482

+ UNSPEC_VPERM_UNS))]

69483

+ "TARGET_ALTIVEC"

69484

"vperm %0,%1,%2,%3"

69485

[(set_attr "type" "vecperm")])

69486

69487

@@ -1335,7 +1936,12 @@

69488

(match_operand:V16QI 3 "register_operand" "")]

69489

UNSPEC_VPERM))]

69490

"TARGET_ALTIVEC"

69491

- "")

69492

+{

69493

+ if (!BYTES_BIG_ENDIAN) {

69494

+ altivec_expand_vec_perm_le (operands);

69495

+ DONE;

69496

+ }

69497

+})

69498

69499

(define_expand "vec_perm_constv16qi"

69500

[(match_operand:V16QI 0 "register_operand" "")

69501

@@ -1476,52 +2082,72 @@

69502

"vsldoi %0,%1,%2,%3"

69503

[(set_attr "type" "vecperm")])

69504

69505

-(define_insn "altivec_vupkhsb"

69506

- [(set (match_operand:V8HI 0 "register_operand" "=v")

69507

- (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]

69508

- UNSPEC_VUPKHSB))]

69509

- "TARGET_ALTIVEC"

69510

- "vupkhsb %0,%1"

69511

+(define_insn "altivec_vupkhs<VU_char>"

69512

+ [(set (match_operand:VP 0 "register_operand" "=v")

69513

+ (unspec:VP [(match_operand:<VP_small> 1 "register_operand" "v")]

69514

+ UNSPEC_VUNPACK_HI_SIGN))]

69515

+ "<VI_unit>"

69516

+{

69517

+ if (VECTOR_ELT_ORDER_BIG)

69518

+ return "vupkhs<VU_char> %0,%1";

69519

+ else

69520

+ return "vupkls<VU_char> %0,%1";

69521

+}

69522

[(set_attr "type" "vecperm")])

69523

69524

-(define_insn "altivec_vupkhpx"

69525

- [(set (match_operand:V4SI 0 "register_operand" "=v")

69526

- (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]

69527

- UNSPEC_VUPKHPX))]

69528

- "TARGET_ALTIVEC"

69529

- "vupkhpx %0,%1"

69530

+(define_insn "*altivec_vupkhs<VU_char>_direct"

69531

+ [(set (match_operand:VP 0 "register_operand" "=v")

69532

+ (unspec:VP [(match_operand:<VP_small> 1 "register_operand" "v")]

69533

+ UNSPEC_VUNPACK_HI_SIGN_DIRECT))]

69534

+ "<VI_unit>"

69535

+ "vupkhs<VU_char> %0,%1"

69536

[(set_attr "type" "vecperm")])

69537

69538

-(define_insn "altivec_vupkhsh"

69539

- [(set (match_operand:V4SI 0 "register_operand" "=v")

69540

- (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]

69541

- UNSPEC_VUPKHSH))]

69542

- "TARGET_ALTIVEC"

69543

- "vupkhsh %0,%1"

69544

+(define_insn "altivec_vupkls<VU_char>"

69545

+ [(set (match_operand:VP 0 "register_operand" "=v")

69546

+ (unspec:VP [(match_operand:<VP_small> 1 "register_operand" "v")]

69547

+ UNSPEC_VUNPACK_LO_SIGN))]

69548

+ "<VI_unit>"

69549

+{

69550

+ if (VECTOR_ELT_ORDER_BIG)

69551

+ return "vupkls<VU_char> %0,%1";

69552

+ else

69553

+ return "vupkhs<VU_char> %0,%1";

69554

+}

69555

[(set_attr "type" "vecperm")])

69556

69557

-(define_insn "altivec_vupklsb"

69558

- [(set (match_operand:V8HI 0 "register_operand" "=v")

69559

- (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]

69560

- UNSPEC_VUPKLSB))]

69561

- "TARGET_ALTIVEC"

69562

- "vupklsb %0,%1"

69563

+(define_insn "*altivec_vupkls<VU_char>_direct"

69564

+ [(set (match_operand:VP 0 "register_operand" "=v")

69565

+ (unspec:VP [(match_operand:<VP_small> 1 "register_operand" "v")]

69566

+ UNSPEC_VUNPACK_LO_SIGN_DIRECT))]

69567

+ "<VI_unit>"

69568

+ "vupkls<VU_char> %0,%1"

69569

[(set_attr "type" "vecperm")])

69570

69571

-(define_insn "altivec_vupklpx"

69572

+(define_insn "altivec_vupkhpx"

69573

[(set (match_operand:V4SI 0 "register_operand" "=v")

69574

(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]

69575

- UNSPEC_VUPKLPX))]

69576

+ UNSPEC_VUPKHPX))]

69577

"TARGET_ALTIVEC"

69578

- "vupklpx %0,%1"

69579

+{

69580

+ if (VECTOR_ELT_ORDER_BIG)

69581

+ return "vupkhpx %0,%1";

69582

+ else

69583

+ return "vupklpx %0,%1";

69584

+}

69585

[(set_attr "type" "vecperm")])

69586

69587

-(define_insn "altivec_vupklsh"

69588

+(define_insn "altivec_vupklpx"

69589

[(set (match_operand:V4SI 0 "register_operand" "=v")

69590

(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]

69591

- UNSPEC_VUPKLSH))]

69592

+ UNSPEC_VUPKLPX))]

69593

"TARGET_ALTIVEC"

69594

- "vupklsh %0,%1"

69595

+{

69596

+ if (VECTOR_ELT_ORDER_BIG)

69597

+ return "vupklpx %0,%1";

69598

+ else

69599

+ return "vupkhpx %0,%1";

69600

+}

69601

[(set_attr "type" "vecperm")])

69602

69603

;; Compare vectors producing a vector result and a predicate, setting CR6 to

69604

@@ -1528,37 +2154,37 @@

69605

;; indicate a combined status

69606

(define_insn "*altivec_vcmpequ<VI_char>_p"

69607

[(set (reg:CC 74)

69608

- (unspec:CC [(eq:CC (match_operand:VI 1 "register_operand" "v")

69609

- (match_operand:VI 2 "register_operand" "v"))]

69610

+ (unspec:CC [(eq:CC (match_operand:VI2 1 "register_operand" "v")

69611

+ (match_operand:VI2 2 "register_operand" "v"))]

69612

UNSPEC_PREDICATE))

69613

- (set (match_operand:VI 0 "register_operand" "=v")

69614

- (eq:VI (match_dup 1)

69615

- (match_dup 2)))]

69616

- "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"

69617

+ (set (match_operand:VI2 0 "register_operand" "=v")

69618

+ (eq:VI2 (match_dup 1)

69619

+ (match_dup 2)))]

69620

+ "<VI_unit>"

69621

"vcmpequ<VI_char>. %0,%1,%2"

69622

[(set_attr "type" "veccmp")])

69623

69624

(define_insn "*altivec_vcmpgts<VI_char>_p"

69625

[(set (reg:CC 74)

69626

- (unspec:CC [(gt:CC (match_operand:VI 1 "register_operand" "v")

69627

- (match_operand:VI 2 "register_operand" "v"))]

69628

+ (unspec:CC [(gt:CC (match_operand:VI2 1 "register_operand" "v")

69629

+ (match_operand:VI2 2 "register_operand" "v"))]

69630

UNSPEC_PREDICATE))

69631

- (set (match_operand:VI 0 "register_operand" "=v")

69632

- (gt:VI (match_dup 1)

69633

- (match_dup 2)))]

69634

- "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"

69635

+ (set (match_operand:VI2 0 "register_operand" "=v")

69636

+ (gt:VI2 (match_dup 1)

69637

+ (match_dup 2)))]

69638

+ "<VI_unit>"

69639

"vcmpgts<VI_char>. %0,%1,%2"

69640

[(set_attr "type" "veccmp")])

69641

69642

(define_insn "*altivec_vcmpgtu<VI_char>_p"

69643

[(set (reg:CC 74)

69644

- (unspec:CC [(gtu:CC (match_operand:VI 1 "register_operand" "v")

69645

- (match_operand:VI 2 "register_operand" "v"))]

69646

+ (unspec:CC [(gtu:CC (match_operand:VI2 1 "register_operand" "v")

69647

+ (match_operand:VI2 2 "register_operand" "v"))]

69648

UNSPEC_PREDICATE))

69649

- (set (match_operand:VI 0 "register_operand" "=v")

69650

- (gtu:VI (match_dup 1)

69651

- (match_dup 2)))]

69652

- "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"

69653

+ (set (match_operand:VI2 0 "register_operand" "=v")

69654

+ (gtu:VI2 (match_dup 1)

69655

+ (match_dup 2)))]

69656

+ "<VI_unit>"

69657

"vcmpgtu<VI_char>. %0,%1,%2"

69658

[(set_attr "type" "veccmp")])

69659

69660

@@ -1710,12 +2336,26 @@

69661

;; Parallel some of the LVE* and STV*'s with unspecs because some have

69662

;; identical rtl but different instructions-- and gcc gets confused.

69663

69664

-(define_insn "altivec_lve<VI_char>x"

69665

+(define_expand "altivec_lve<VI_char>x"

69666

[(parallel

69667

[(set (match_operand:VI 0 "register_operand" "=v")

69668

(match_operand:VI 1 "memory_operand" "Z"))

69669

(unspec [(const_int 0)] UNSPEC_LVE)])]

69670

"TARGET_ALTIVEC"

69671

+{

69672

+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)

69673

+ {

69674

+ altivec_expand_lvx_be (operands[0], operands[1], <MODE>mode, UNSPEC_LVE);

69675

+ DONE;

69676

+ }

69677

+})

69678

+

69679

+(define_insn "*altivec_lve<VI_char>x_internal"

69680

+ [(parallel

69681

+ [(set (match_operand:VI 0 "register_operand" "=v")

69682

+ (match_operand:VI 1 "memory_operand" "Z"))

69683

+ (unspec [(const_int 0)] UNSPEC_LVE)])]

69684

+ "TARGET_ALTIVEC"

69685

"lve<VI_char>x %0,%y1"

69686

[(set_attr "type" "vecload")])

69687

69688

@@ -1728,46 +2368,114 @@

69689

"lvewx %0,%y1"

69690

[(set_attr "type" "vecload")])

69691

69692

-(define_insn "altivec_lvxl"

69693

+(define_expand "altivec_lvxl_<mode>"

69694

[(parallel

69695

- [(set (match_operand:V4SI 0 "register_operand" "=v")

69696

- (match_operand:V4SI 1 "memory_operand" "Z"))

69697

+ [(set (match_operand:VM2 0 "register_operand" "=v")

69698

+ (match_operand:VM2 1 "memory_operand" "Z"))

69699

(unspec [(const_int 0)] UNSPEC_SET_VSCR)])]

69700

"TARGET_ALTIVEC"

69701

- "lvxl %0,%y1"

69702

+{

69703

+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)

69704

+ {

69705

+ altivec_expand_lvx_be (operands[0], operands[1], <MODE>mode, UNSPEC_SET_VSCR);

69706

+ DONE;

69707

+ }

69708

+})

69709

+

69710

+(define_insn "*altivec_lvxl_<mode>_internal"

69711

+ [(parallel

69712

+ [(set (match_operand:VM2 0 "register_operand" "=v")

69713

+ (match_operand:VM2 1 "memory_operand" "Z"))

69714

+ (unspec [(const_int 0)] UNSPEC_SET_VSCR)])]

69715

+ "TARGET_ALTIVEC"

69716

+ "lvx %0,%y1"

69717

[(set_attr "type" "vecload")])

69718

69719

-(define_insn "altivec_lvx_<mode>"

69720

+(define_expand "altivec_lvx_<mode>"

69721

[(parallel

69722

[(set (match_operand:VM2 0 "register_operand" "=v")

69723

(match_operand:VM2 1 "memory_operand" "Z"))

69724

(unspec [(const_int 0)] UNSPEC_LVX)])]

69725

"TARGET_ALTIVEC"

69726

+{

69727

+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)

69728

+ {

69729

+ altivec_expand_lvx_be (operands[0], operands[1], <MODE>mode, UNSPEC_LVX);

69730

+ DONE;

69731

+ }

69732

+})

69733

+

69734

+(define_insn "*altivec_lvx_<mode>_internal"

69735

+ [(parallel

69736

+ [(set (match_operand:VM2 0 "register_operand" "=v")

69737

+ (match_operand:VM2 1 "memory_operand" "Z"))

69738

+ (unspec [(const_int 0)] UNSPEC_LVX)])]

69739

+ "TARGET_ALTIVEC"

69740

"lvx %0,%y1"

69741

[(set_attr "type" "vecload")])

69742

69743

-(define_insn "altivec_stvx_<mode>"

69744

+(define_expand "altivec_stvx_<mode>"

69745

[(parallel

69746

[(set (match_operand:VM2 0 "memory_operand" "=Z")

69747

(match_operand:VM2 1 "register_operand" "v"))

69748

(unspec [(const_int 0)] UNSPEC_STVX)])]

69749

"TARGET_ALTIVEC"

69750

+{

69751

+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)

69752

+ {

69753

+ altivec_expand_stvx_be (operands[0], operands[1], <MODE>mode, UNSPEC_STVX);

69754

+ DONE;

69755

+ }

69756

+})

69757

+

69758

+(define_insn "*altivec_stvx_<mode>_internal"

69759

+ [(parallel

69760

+ [(set (match_operand:VM2 0 "memory_operand" "=Z")

69761

+ (match_operand:VM2 1 "register_operand" "v"))

69762

+ (unspec [(const_int 0)] UNSPEC_STVX)])]

69763

+ "TARGET_ALTIVEC"

69764

"stvx %1,%y0"

69765

[(set_attr "type" "vecstore")])

69766

69767

-(define_insn "altivec_stvxl"

69768

+(define_expand "altivec_stvxl_<mode>"

69769

[(parallel

69770

- [(set (match_operand:V4SI 0 "memory_operand" "=Z")

69771

- (match_operand:V4SI 1 "register_operand" "v"))

69772

+ [(set (match_operand:VM2 0 "memory_operand" "=Z")

69773

+ (match_operand:VM2 1 "register_operand" "v"))

69774

(unspec [(const_int 0)] UNSPEC_STVXL)])]

69775

"TARGET_ALTIVEC"

69776

+{

69777

+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)

69778

+ {

69779

+ altivec_expand_stvx_be (operands[0], operands[1], <MODE>mode, UNSPEC_STVXL);

69780

+ DONE;

69781

+ }

69782

+})

69783

+

69784

+(define_insn "*altivec_stvxl_<mode>_internal"

69785

+ [(parallel

69786

+ [(set (match_operand:VM2 0 "memory_operand" "=Z")

69787

+ (match_operand:VM2 1 "register_operand" "v"))

69788

+ (unspec [(const_int 0)] UNSPEC_STVXL)])]

69789

+ "TARGET_ALTIVEC"

69790

"stvxl %1,%y0"

69791

[(set_attr "type" "vecstore")])

69792

69793

-(define_insn "altivec_stve<VI_char>x"

69794

+(define_expand "altivec_stve<VI_char>x"

69795

[(set (match_operand:<VI_scalar> 0 "memory_operand" "=Z")

69796

(unspec:<VI_scalar> [(match_operand:VI 1 "register_operand" "v")] UNSPEC_STVE))]

69797

"TARGET_ALTIVEC"

69798

+{

69799

+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)

69800

+ {

69801

+ altivec_expand_stvex_be (operands[0], operands[1], <MODE>mode, UNSPEC_STVE);

69802

+ DONE;

69803

+ }

69804

+})

69805

+

69806

+(define_insn "*altivec_stve<VI_char>x_internal"

69807

+ [(set (match_operand:<VI_scalar> 0 "memory_operand" "=Z")

69808

+ (unspec:<VI_scalar> [(match_operand:VI 1 "register_operand" "v")] UNSPEC_STVE))]

69809

+ "TARGET_ALTIVEC"

69810

"stve<VI_char>x %1,%y0"

69811

[(set_attr "type" "vecstore")])

69812

69813

@@ -1779,20 +2487,28 @@

69814

[(set_attr "type" "vecstore")])

69815

69816

;; Generate

69817

-;; vspltis? SCRATCH0,0

69818

+;; xxlxor/vxor SCRATCH0,SCRATCH0,SCRATCH0

69819

;; vsubu?m SCRATCH2,SCRATCH1,%1

69820

;; vmaxs? %0,%1,SCRATCH2"

69821

(define_expand "abs<mode>2"

69822

- [(set (match_dup 2) (vec_duplicate:VI (const_int 0)))

69823

- (set (match_dup 3)

69824

- (minus:VI (match_dup 2)

69825

- (match_operand:VI 1 "register_operand" "v")))

69826

- (set (match_operand:VI 0 "register_operand" "=v")

69827

- (smax:VI (match_dup 1) (match_dup 3)))]

69828

- "TARGET_ALTIVEC"

69829

+ [(set (match_dup 2) (match_dup 3))

69830

+ (set (match_dup 4)

69831

+ (minus:VI2 (match_dup 2)

69832

+ (match_operand:VI2 1 "register_operand" "v")))

69833

+ (set (match_operand:VI2 0 "register_operand" "=v")

69834

+ (smax:VI2 (match_dup 1) (match_dup 4)))]

69835

+ "<VI_unit>"

69836

{

69837

- operands[2] = gen_reg_rtx (GET_MODE (operands[0]));

69838

- operands[3] = gen_reg_rtx (GET_MODE (operands[0]));

69839

+ int i, n_elt = GET_MODE_NUNITS (<MODE>mode);

69840

+ rtvec v = rtvec_alloc (n_elt);

69841

+

69842

+ /* Create an all 0 constant. */

69843

+ for (i = 0; i < n_elt; ++i)

69844

+ RTVEC_ELT (v, i) = const0_rtx;

69845

+

69846

+ operands[2] = gen_reg_rtx (<MODE>mode);

69847

+ operands[3] = gen_rtx_CONST_VECTOR (<MODE>mode, v);

69848

+ operands[4] = gen_reg_rtx (<MODE>mode);

69849

})

69850

69851

;; Generate

69852

@@ -1844,7 +2560,7 @@

69853

69854

emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));

69855

emit_insn (gen_altivec_vsum4s<VI_char>s (vtmp1, operands[1], vzero));

69856

- emit_insn (gen_altivec_vsumsws (dest, vtmp1, vzero));

69857

+ emit_insn (gen_altivec_vsumsws_direct (dest, vtmp1, vzero));

69858

DONE;

69859

})

69860

69861

@@ -1860,7 +2576,7 @@

69862

69863

emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));

69864

emit_insn (gen_altivec_vsum4ubs (vtmp1, operands[1], vzero));

69865

- emit_insn (gen_altivec_vsumsws (dest, vtmp1, vzero));

69866

+ emit_insn (gen_altivec_vsumsws_direct (dest, vtmp1, vzero));

69867

DONE;

69868

})

69869

69870

@@ -1950,50 +2666,20 @@

69871

DONE;

69872

}")

69873

69874

-(define_expand "vec_unpacks_hi_v16qi"

69875

- [(set (match_operand:V8HI 0 "register_operand" "=v")

69876

- (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]

69877

- UNSPEC_VUPKHSB))]

69878

- "TARGET_ALTIVEC"

69879

- "

69880

-{

69881

- emit_insn (gen_altivec_vupkhsb (operands[0], operands[1]));

69882

- DONE;

69883

-}")

69884

+(define_expand "vec_unpacks_hi_<VP_small_lc>"

69885

+ [(set (match_operand:VP 0 "register_operand" "=v")

69886

+ (unspec:VP [(match_operand:<VP_small> 1 "register_operand" "v")]

69887

+ UNSPEC_VUNPACK_HI_SIGN_DIRECT))]

69888

+ "<VI_unit>"

69889

+ "")

69890

69891

-(define_expand "vec_unpacks_hi_v8hi"

69892

- [(set (match_operand:V4SI 0 "register_operand" "=v")

69893

- (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]

69894

- UNSPEC_VUPKHSH))]

69895

- "TARGET_ALTIVEC"

69896

- "

69897

-{

69898

- emit_insn (gen_altivec_vupkhsh (operands[0], operands[1]));

69899

- DONE;

69900

-}")

69901

+(define_expand "vec_unpacks_lo_<VP_small_lc>"

69902

+ [(set (match_operand:VP 0 "register_operand" "=v")

69903

+ (unspec:VP [(match_operand:<VP_small> 1 "register_operand" "v")]

69904

+ UNSPEC_VUNPACK_LO_SIGN_DIRECT))]

69905

+ "<VI_unit>"

69906

+ "")

69907

69908

-(define_expand "vec_unpacks_lo_v16qi"

69909

- [(set (match_operand:V8HI 0 "register_operand" "=v")

69910

- (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]

69911

- UNSPEC_VUPKLSB))]

69912

- "TARGET_ALTIVEC"

69913

- "

69914

-{

69915

- emit_insn (gen_altivec_vupklsb (operands[0], operands[1]));

69916

- DONE;

69917

-}")

69918

-

69919

-(define_expand "vec_unpacks_lo_v8hi"

69920

- [(set (match_operand:V4SI 0 "register_operand" "=v")

69921

- (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]

69922

- UNSPEC_VUPKLSH))]

69923

- "TARGET_ALTIVEC"

69924

- "

69925

-{

69926

- emit_insn (gen_altivec_vupklsh (operands[0], operands[1]));

69927

- DONE;

69928

-}")

69929

-

69930

(define_insn "vperm_v8hiv4si"

69931

[(set (match_operand:V4SI 0 "register_operand" "=v")

69932

(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")

69933

@@ -2025,25 +2711,26 @@

69934

rtx vzero = gen_reg_rtx (V8HImode);

69935

rtx mask = gen_reg_rtx (V16QImode);

69936

rtvec v = rtvec_alloc (16);

69937

+ bool be = BYTES_BIG_ENDIAN;

69938

69939

emit_insn (gen_altivec_vspltish (vzero, const0_rtx));

69940

69941

- RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16);

69942

- RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 0);

69943

- RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 16);

69944

- RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 1);

69945

- RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16);

69946

- RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 2);

69947

- RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 16);

69948

- RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 3);

69949

- RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);

69950

- RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 4);

69951

- RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 16);

69952

- RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 5);

69953

- RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16);

69954

- RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 6);

69955

- RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 16);

69956

- RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 7);

69957

+ RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, be ? 16 : 7);

69958

+ RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, be ? 0 : 16);

69959

+ RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, be ? 16 : 6);

69960

+ RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, be ? 1 : 16);

69961

+ RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, be ? 16 : 5);

69962

+ RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, be ? 2 : 16);

69963

+ RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, be ? 16 : 4);

69964

+ RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, be ? 3 : 16);

69965

+ RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, be ? 16 : 3);

69966

+ RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, be ? 4 : 16);

69967

+ RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, be ? 16 : 2);

69968

+ RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, be ? 5 : 16);

69969

+ RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, be ? 16 : 1);

69970

+ RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, be ? 6 : 16);

69971

+ RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, be ? 16 : 0);

69972

+ RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, be ? 7 : 16);

69973

69974

emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));

69975

emit_insn (gen_vperm_v16qiv8hi (operands[0], operands[1], vzero, mask));

69976

@@ -2060,25 +2747,26 @@

69977

rtx vzero = gen_reg_rtx (V4SImode);

69978

rtx mask = gen_reg_rtx (V16QImode);

69979

rtvec v = rtvec_alloc (16);

69980

+ bool be = BYTES_BIG_ENDIAN;

69981

69982

emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));

69983

69984

- RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16);

69985

- RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 17);

69986

- RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 0);

69987

- RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 1);

69988

- RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16);

69989

- RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 17);

69990

- RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 2);

69991

- RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 3);

69992

- RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);

69993

- RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17);

69994

- RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 4);

69995

- RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 5);

69996

- RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16);

69997

- RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 17);

69998

- RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 6);

69999

- RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 7);

70000

+ RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, be ? 16 : 7);

70001

+ RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, be ? 17 : 6);

70002

+ RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, be ? 0 : 17);

70003

+ RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, be ? 1 : 16);

70004

+ RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, be ? 16 : 5);

70005

+ RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, be ? 17 : 4);

70006

+ RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, be ? 2 : 17);

70007

+ RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, be ? 3 : 16);

70008

+ RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, be ? 16 : 3);

70009

+ RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, be ? 17 : 2);

70010

+ RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, be ? 4 : 17);

70011

+ RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, be ? 5 : 16);

70012

+ RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, be ? 16 : 1);

70013

+ RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, be ? 17 : 0);

70014

+ RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, be ? 6 : 17);

70015

+ RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, be ? 7 : 16);

70016

70017

emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));

70018

emit_insn (gen_vperm_v8hiv4si (operands[0], operands[1], vzero, mask));

70019

@@ -2095,25 +2783,26 @@

70020

rtx vzero = gen_reg_rtx (V8HImode);

70021

rtx mask = gen_reg_rtx (V16QImode);

70022

rtvec v = rtvec_alloc (16);

70023

+ bool be = BYTES_BIG_ENDIAN;

70024

70025

emit_insn (gen_altivec_vspltish (vzero, const0_rtx));

70026

70027

- RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16);

70028

- RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 8);

70029

- RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 16);

70030

- RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 9);

70031

- RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16);

70032

- RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 10);

70033

- RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 16);

70034

- RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 11);

70035

- RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);

70036

- RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 12);

70037

- RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 16);

70038

- RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 13);

70039

- RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16);

70040

- RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 14);

70041

- RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 16);

70042

- RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 15);

70043

+ RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, be ? 16 : 15);

70044

+ RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, be ? 8 : 16);

70045

+ RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, be ? 16 : 14);

70046

+ RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, be ? 9 : 16);

70047

+ RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, be ? 16 : 13);

70048

+ RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, be ? 10 : 16);

70049

+ RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, be ? 16 : 12);

70050

+ RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, be ? 11 : 16);

70051

+ RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, be ? 16 : 11);

70052

+ RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, be ? 12 : 16);

70053

+ RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, be ? 16 : 10);

70054

+ RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, be ? 13 : 16);

70055

+ RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, be ? 16 : 9);

70056

+ RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, be ? 14 : 16);

70057

+ RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, be ? 16 : 8);

70058

+ RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, be ? 15 : 16);

70059

70060

emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));

70061

emit_insn (gen_vperm_v16qiv8hi (operands[0], operands[1], vzero, mask));

70062

@@ -2130,25 +2819,26 @@

70063

rtx vzero = gen_reg_rtx (V4SImode);

70064

rtx mask = gen_reg_rtx (V16QImode);

70065

rtvec v = rtvec_alloc (16);

70066

+ bool be = BYTES_BIG_ENDIAN;

70067

70068

emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));

70069

70070

- RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16);

70071

- RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 17);

70072

- RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 8);

70073

- RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 9);

70074

- RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16);

70075

- RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 17);

70076

- RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 10);

70077

- RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 11);

70078

- RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);

70079

- RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17);

70080

- RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 12);

70081

- RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 13);

70082

- RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16);

70083

- RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 17);

70084

- RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 14);

70085

- RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 15);

70086

+ RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, be ? 16 : 15);

70087

+ RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, be ? 17 : 14);

70088

+ RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, be ? 8 : 17);

70089

+ RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, be ? 9 : 16);

70090

+ RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, be ? 16 : 13);

70091

+ RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, be ? 17 : 12);

70092

+ RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, be ? 10 : 17);

70093

+ RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, be ? 11 : 16);

70094

+ RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, be ? 16 : 11);

70095

+ RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, be ? 17 : 10);

70096

+ RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, be ? 12 : 17);

70097

+ RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, be ? 13 : 16);

70098

+ RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, be ? 16 : 9);

70099

+ RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, be ? 17 : 8);

70100

+ RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, be ? 14 : 17);

70101

+ RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, be ? 15 : 16);

70102

70103

emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));

70104

emit_insn (gen_vperm_v8hiv4si (operands[0], operands[1], vzero, mask));

70105

@@ -2166,9 +2856,18 @@

70106

rtx ve = gen_reg_rtx (V8HImode);

70107

rtx vo = gen_reg_rtx (V8HImode);

70108

70109

- emit_insn (gen_vec_widen_umult_even_v16qi (ve, operands[1], operands[2]));

70110

- emit_insn (gen_vec_widen_umult_odd_v16qi (vo, operands[1], operands[2]));

70111

- emit_insn (gen_altivec_vmrghh (operands[0], ve, vo));

70112

+ if (BYTES_BIG_ENDIAN)

70113

+ {

70114

+ emit_insn (gen_altivec_vmuleub (ve, operands[1], operands[2]));

70115

+ emit_insn (gen_altivec_vmuloub (vo, operands[1], operands[2]));

70116

+ emit_insn (gen_altivec_vmrghh_direct (operands[0], ve, vo));

70117

+ }

70118

+ else

70119

+ {

70120

+ emit_insn (gen_altivec_vmuloub (ve, operands[1], operands[2]));

70121

+ emit_insn (gen_altivec_vmuleub (vo, operands[1], operands[2]));

70122

+ emit_insn (gen_altivec_vmrghh_direct (operands[0], vo, ve));

70123

+ }

70124

DONE;

70125

}")

70126

70127

@@ -2183,9 +2882,18 @@

70128

rtx ve = gen_reg_rtx (V8HImode);

70129

rtx vo = gen_reg_rtx (V8HImode);

70130

70131

- emit_insn (gen_vec_widen_umult_even_v16qi (ve, operands[1], operands[2]));

70132

- emit_insn (gen_vec_widen_umult_odd_v16qi (vo, operands[1], operands[2]));

70133

- emit_insn (gen_altivec_vmrglh (operands[0], ve, vo));

70134

+ if (BYTES_BIG_ENDIAN)

70135

+ {

70136

+ emit_insn (gen_altivec_vmuleub (ve, operands[1], operands[2]));

70137

+ emit_insn (gen_altivec_vmuloub (vo, operands[1], operands[2]));

70138

+ emit_insn (gen_altivec_vmrglh_direct (operands[0], ve, vo));

70139

+ }

70140

+ else

70141

+ {

70142

+ emit_insn (gen_altivec_vmuloub (ve, operands[1], operands[2]));

70143

+ emit_insn (gen_altivec_vmuleub (vo, operands[1], operands[2]));

70144

+ emit_insn (gen_altivec_vmrglh_direct (operands[0], vo, ve));

70145

+ }

70146

DONE;

70147

}")

70148

70149

@@ -2200,9 +2908,18 @@

70150

rtx ve = gen_reg_rtx (V8HImode);

70151

rtx vo = gen_reg_rtx (V8HImode);

70152

70153

- emit_insn (gen_vec_widen_smult_even_v16qi (ve, operands[1], operands[2]));

70154

- emit_insn (gen_vec_widen_smult_odd_v16qi (vo, operands[1], operands[2]));

70155

- emit_insn (gen_altivec_vmrghh (operands[0], ve, vo));

70156

+ if (BYTES_BIG_ENDIAN)

70157

+ {

70158

+ emit_insn (gen_altivec_vmulesb (ve, operands[1], operands[2]));

70159

+ emit_insn (gen_altivec_vmulosb (vo, operands[1], operands[2]));

70160

+ emit_insn (gen_altivec_vmrghh_direct (operands[0], ve, vo));

70161

+ }

70162

+ else

70163

+ {

70164

+ emit_insn (gen_altivec_vmulosb (ve, operands[1], operands[2]));

70165

+ emit_insn (gen_altivec_vmulesb (vo, operands[1], operands[2]));

70166

+ emit_insn (gen_altivec_vmrghh_direct (operands[0], vo, ve));

70167

+ }

70168

DONE;

70169

}")

70170

70171

@@ -2217,9 +2934,18 @@

70172

rtx ve = gen_reg_rtx (V8HImode);

70173

rtx vo = gen_reg_rtx (V8HImode);

70174

70175

- emit_insn (gen_vec_widen_smult_even_v16qi (ve, operands[1], operands[2]));

70176

- emit_insn (gen_vec_widen_smult_odd_v16qi (vo, operands[1], operands[2]));

70177

- emit_insn (gen_altivec_vmrglh (operands[0], ve, vo));

70178

+ if (BYTES_BIG_ENDIAN)

70179

+ {

70180

+ emit_insn (gen_altivec_vmulesb (ve, operands[1], operands[2]));

70181

+ emit_insn (gen_altivec_vmulosb (vo, operands[1], operands[2]));

70182

+ emit_insn (gen_altivec_vmrglh_direct (operands[0], ve, vo));

70183

+ }

70184

+ else

70185

+ {

70186

+ emit_insn (gen_altivec_vmulosb (ve, operands[1], operands[2]));

70187

+ emit_insn (gen_altivec_vmulesb (vo, operands[1], operands[2]));

70188

+ emit_insn (gen_altivec_vmrglh_direct (operands[0], vo, ve));

70189

+ }

70190

DONE;

70191

}")

70192

70193

@@ -2234,9 +2960,18 @@

70194

rtx ve = gen_reg_rtx (V4SImode);

70195

rtx vo = gen_reg_rtx (V4SImode);

70196

70197

- emit_insn (gen_vec_widen_umult_even_v8hi (ve, operands[1], operands[2]));

70198

- emit_insn (gen_vec_widen_umult_odd_v8hi (vo, operands[1], operands[2]));

70199

- emit_insn (gen_altivec_vmrghw (operands[0], ve, vo));

70200

+ if (BYTES_BIG_ENDIAN)

70201

+ {

70202

+ emit_insn (gen_altivec_vmuleuh (ve, operands[1], operands[2]));

70203

+ emit_insn (gen_altivec_vmulouh (vo, operands[1], operands[2]));

70204

+ emit_insn (gen_altivec_vmrghw_direct (operands[0], ve, vo));

70205

+ }

70206

+ else

70207

+ {

70208

+ emit_insn (gen_altivec_vmulouh (ve, operands[1], operands[2]));

70209

+ emit_insn (gen_altivec_vmuleuh (vo, operands[1], operands[2]));

70210

+ emit_insn (gen_altivec_vmrghw_direct (operands[0], vo, ve));

70211

+ }

70212

DONE;

70213

}")

70214

70215

@@ -2251,9 +2986,18 @@

70216

rtx ve = gen_reg_rtx (V4SImode);

70217

rtx vo = gen_reg_rtx (V4SImode);

70218

70219

- emit_insn (gen_vec_widen_umult_even_v8hi (ve, operands[1], operands[2]));

70220

- emit_insn (gen_vec_widen_umult_odd_v8hi (vo, operands[1], operands[2]));

70221

- emit_insn (gen_altivec_vmrglw (operands[0], ve, vo));

70222

+ if (BYTES_BIG_ENDIAN)

70223

+ {

70224

+ emit_insn (gen_altivec_vmuleuh (ve, operands[1], operands[2]));

70225

+ emit_insn (gen_altivec_vmulouh (vo, operands[1], operands[2]));

70226

+ emit_insn (gen_altivec_vmrglw_direct (operands[0], ve, vo));

70227

+ }

70228

+ else

70229

+ {

70230

+ emit_insn (gen_altivec_vmulouh (ve, operands[1], operands[2]));

70231

+ emit_insn (gen_altivec_vmuleuh (vo, operands[1], operands[2]));

70232

+ emit_insn (gen_altivec_vmrglw_direct (operands[0], vo, ve));

70233

+ }

70234

DONE;

70235

}")

70236

70237

@@ -2268,9 +3012,18 @@

70238

rtx ve = gen_reg_rtx (V4SImode);

70239

rtx vo = gen_reg_rtx (V4SImode);

70240

70241

- emit_insn (gen_vec_widen_smult_even_v8hi (ve, operands[1], operands[2]));

70242

- emit_insn (gen_vec_widen_smult_odd_v8hi (vo, operands[1], operands[2]));

70243

- emit_insn (gen_altivec_vmrghw (operands[0], ve, vo));

70244

+ if (BYTES_BIG_ENDIAN)

70245

+ {

70246

+ emit_insn (gen_altivec_vmulesh (ve, operands[1], operands[2]));

70247

+ emit_insn (gen_altivec_vmulosh (vo, operands[1], operands[2]));

70248

+ emit_insn (gen_altivec_vmrghw_direct (operands[0], ve, vo));

70249

+ }

70250

+ else

70251

+ {

70252

+ emit_insn (gen_altivec_vmulosh (ve, operands[1], operands[2]));

70253

+ emit_insn (gen_altivec_vmulesh (vo, operands[1], operands[2]));

70254

+ emit_insn (gen_altivec_vmrghw_direct (operands[0], vo, ve));

70255

+ }

70256

DONE;

70257

}")

70258

70259

@@ -2285,35 +3038,28 @@

70260

rtx ve = gen_reg_rtx (V4SImode);

70261

rtx vo = gen_reg_rtx (V4SImode);

70262

70263

- emit_insn (gen_vec_widen_smult_even_v8hi (ve, operands[1], operands[2]));

70264

- emit_insn (gen_vec_widen_smult_odd_v8hi (vo, operands[1], operands[2]));

70265

- emit_insn (gen_altivec_vmrglw (operands[0], ve, vo));

70266

+ if (BYTES_BIG_ENDIAN)

70267

+ {

70268

+ emit_insn (gen_altivec_vmulesh (ve, operands[1], operands[2]));

70269

+ emit_insn (gen_altivec_vmulosh (vo, operands[1], operands[2]));

70270

+ emit_insn (gen_altivec_vmrglw_direct (operands[0], ve, vo));

70271

+ }

70272

+ else

70273

+ {

70274

+ emit_insn (gen_altivec_vmulosh (ve, operands[1], operands[2]));

70275

+ emit_insn (gen_altivec_vmulesh (vo, operands[1], operands[2]));

70276

+ emit_insn (gen_altivec_vmrglw_direct (operands[0], vo, ve));

70277

+ }

70278

DONE;

70279

}")

70280

70281

-(define_expand "vec_pack_trunc_v8hi"

70282

- [(set (match_operand:V16QI 0 "register_operand" "=v")

70283

- (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")

70284

- (match_operand:V8HI 2 "register_operand" "v")]

70285

- UNSPEC_VPKUHUM))]

70286

- "TARGET_ALTIVEC"

70287

- "

70288

-{

70289

- emit_insn (gen_altivec_vpkuhum (operands[0], operands[1], operands[2]));

70290

- DONE;

70291

-}")

70292

-

70293

-(define_expand "vec_pack_trunc_v4si"

70294

- [(set (match_operand:V8HI 0 "register_operand" "=v")

70295

- (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")

70296

- (match_operand:V4SI 2 "register_operand" "v")]

70297

- UNSPEC_VPKUWUM))]

70298

- "TARGET_ALTIVEC"

70299

- "

70300

-{

70301

- emit_insn (gen_altivec_vpkuwum (operands[0], operands[1], operands[2]));

70302

- DONE;

70303

-}")

70304

+(define_expand "vec_pack_trunc_<mode>"

70305

+ [(set (match_operand:<VP_small> 0 "register_operand" "=v")

70306

+ (unspec:<VP_small> [(match_operand:VP 1 "register_operand" "v")

70307

+ (match_operand:VP 2 "register_operand" "v")]

70308

+ UNSPEC_VPACK_UNS_UNS_MOD))]

70309

+ "<VI_unit>"

70310

+ "")

70311

70312

(define_expand "altivec_negv4sf2"

70313

[(use (match_operand:V4SF 0 "register_operand" ""))

70314

@@ -2460,3 +3206,243 @@

70315

emit_insn (gen_altivec_vcfux (operands[0], tmp, const0_rtx));

70316

DONE;

70317

}")

70318

+

70319

+

70320

+;; Power8 vector instructions encoded as Altivec instructions

70321

+

70322

+;; Vector count leading zeros

70323

+(define_insn "*p8v_clz<mode>2"

70324

+ [(set (match_operand:VI2 0 "register_operand" "=v")

70325

+ (clz:VI2 (match_operand:VI2 1 "register_operand" "v")))]

70326

+ "TARGET_P8_VECTOR"

70327

+ "vclz<wd> %0,%1"

70328

+ [(set_attr "length" "4")

70329

+ (set_attr "type" "vecsimple")])

70330

+

70331

+;; Vector population count

70332

+(define_insn "*p8v_popcount<mode>2"

70333

+ [(set (match_operand:VI2 0 "register_operand" "=v")

70334

+ (popcount:VI2 (match_operand:VI2 1 "register_operand" "v")))]

70335

+ "TARGET_P8_VECTOR"

70336

+ "vpopcnt<wd> %0,%1"

70337

+ [(set_attr "length" "4")

70338

+ (set_attr "type" "vecsimple")])

70339

+

70340

+;; Vector Gather Bits by Bytes by Doubleword

70341

+(define_insn "p8v_vgbbd"

70342

+ [(set (match_operand:V16QI 0 "register_operand" "=v")

70343

+ (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")]

70344

+ UNSPEC_VGBBD))]

70345

+ "TARGET_P8_VECTOR"

70346

+ "vgbbd %0,%1"

70347

+ [(set_attr "length" "4")

70348

+ (set_attr "type" "vecsimple")])

70349

+

70350

+

70351

+;; 128-bit binary integer arithmetic

70352

+;; We have a special container type (V1TImode) to allow operations using the

70353

+;; ISA 2.07 128-bit binary support to target the VMX/altivec registers without

70354

+;; having to worry about the register allocator deciding GPRs are better.

70355

+

70356

+(define_insn "altivec_vadduqm"

70357

+ [(set (match_operand:V1TI 0 "register_operand" "=v")

70358

+ (plus:V1TI (match_operand:V1TI 1 "register_operand" "v")

70359

+ (match_operand:V1TI 2 "register_operand" "v")))]

70360

+ "TARGET_VADDUQM"

70361

+ "vadduqm %0,%1,%2"

70362

+ [(set_attr "length" "4")

70363

+ (set_attr "type" "vecsimple")])

70364

+

70365

+(define_insn "altivec_vaddcuq"

70366

+ [(set (match_operand:V1TI 0 "register_operand" "=v")

70367

+ (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "v")

70368

+ (match_operand:V1TI 2 "register_operand" "v")]

70369

+ UNSPEC_VADDCUQ))]

70370

+ "TARGET_VADDUQM"

70371

+ "vaddcuq %0,%1,%2"

70372

+ [(set_attr "length" "4")

70373

+ (set_attr "type" "vecsimple")])

70374

+

70375

+(define_insn "altivec_vsubuqm"

70376

+ [(set (match_operand:V1TI 0 "register_operand" "=v")

70377

+ (minus:V1TI (match_operand:V1TI 1 "register_operand" "v")

70378

+ (match_operand:V1TI 2 "register_operand" "v")))]

70379

+ "TARGET_VADDUQM"

70380

+ "vsubuqm %0,%1,%2"

70381

+ [(set_attr "length" "4")

70382

+ (set_attr "type" "vecsimple")])

70383

+

70384

+(define_insn "altivec_vsubcuq"

70385

+ [(set (match_operand:V1TI 0 "register_operand" "=v")

70386

+ (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "v")

70387

+ (match_operand:V1TI 2 "register_operand" "v")]

70388

+ UNSPEC_VSUBCUQ))]

70389

+ "TARGET_VADDUQM"

70390

+ "vsubcuq %0,%1,%2"

70391

+ [(set_attr "length" "4")

70392

+ (set_attr "type" "vecsimple")])

70393

+

70394

+(define_insn "altivec_vaddeuqm"

70395

+ [(set (match_operand:V1TI 0 "register_operand" "=v")

70396

+ (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "v")

70397

+ (match_operand:V1TI 2 "register_operand" "v")

70398

+ (match_operand:V1TI 3 "register_operand" "v")]

70399

+ UNSPEC_VADDEUQM))]

70400

+ "TARGET_VADDUQM"

70401

+ "vaddeuqm %0,%1,%2,%3"

70402

+ [(set_attr "length" "4")

70403

+ (set_attr "type" "vecsimple")])

70404

+

70405

+(define_insn "altivec_vaddecuq"

70406

+ [(set (match_operand:V1TI 0 "register_operand" "=v")

70407

+ (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "v")

70408

+ (match_operand:V1TI 2 "register_operand" "v")

70409

+ (match_operand:V1TI 3 "register_operand" "v")]

70410

+ UNSPEC_VADDECUQ))]

70411

+ "TARGET_VADDUQM"

70412

+ "vaddecuq %0,%1,%2,%3"

70413

+ [(set_attr "length" "4")

70414

+ (set_attr "type" "vecsimple")])

70415

+

70416

+(define_insn "altivec_vsubeuqm"

70417

+ [(set (match_operand:V1TI 0 "register_operand" "=v")

70418

+ (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "v")

70419

+ (match_operand:V1TI 2 "register_operand" "v")

70420

+ (match_operand:V1TI 3 "register_operand" "v")]

70421

+ UNSPEC_VSUBEUQM))]

70422

+ "TARGET_VADDUQM"

70423

+ "vsubeuqm %0,%1,%2,%3"

70424

+ [(set_attr "length" "4")

70425

+ (set_attr "type" "vecsimple")])

70426

+

70427

+(define_insn "altivec_vsubecuq"

70428

+ [(set (match_operand:V1TI 0 "register_operand" "=v")

70429

+ (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "v")

70430

+ (match_operand:V1TI 2 "register_operand" "v")

70431

+ (match_operand:V1TI 3 "register_operand" "v")]

70432

+ UNSPEC_VSUBECUQ))]

70433

+ "TARGET_VADDUQM"

70434

+ "vsubecuq %0,%1,%2,%3"

70435

+ [(set_attr "length" "4")

70436

+ (set_attr "type" "vecsimple")])

70437

+

70438

+;; We use V2DI as the output type to simplify converting the permute

70439

+;; bits into an integer

70440

+(define_insn "altivec_vbpermq"

70441

+ [(set (match_operand:V2DI 0 "register_operand" "=v")

70442

+ (unspec:V2DI [(match_operand:V16QI 1 "register_operand" "v")

70443

+ (match_operand:V16QI 2 "register_operand" "v")]

70444

+ UNSPEC_VBPERMQ))]

70445

+ "TARGET_P8_VECTOR"

70446

+ "vbpermq %0,%1,%2"

70447

+ [(set_attr "length" "4")

70448

+ (set_attr "type" "vecsimple")])

70449

+

70450

+;; Decimal Integer operations

70451

+(define_int_iterator UNSPEC_BCD_ADD_SUB [UNSPEC_BCDADD UNSPEC_BCDSUB])

70452

+

70453

+(define_int_attr bcd_add_sub [(UNSPEC_BCDADD "add")

70454

+ (UNSPEC_BCDSUB "sub")])

70455

+

70456

+(define_code_iterator BCD_TEST [eq lt gt unordered])

70457

+

70458

+(define_insn "bcd<bcd_add_sub>"

70459

+ [(set (match_operand:V1TI 0 "register_operand" "")

70460

+ (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "")

70461

+ (match_operand:V1TI 2 "register_operand" "")

70462

+ (match_operand:QI 3 "const_0_to_1_operand" "")]

70463

+ UNSPEC_BCD_ADD_SUB))

70464

+ (clobber (reg:CCFP 74))]

70465

+ "TARGET_P8_VECTOR"

70466

+ "bcd<bcd_add_sub>. %0,%1,%2,%3"

70467

+ [(set_attr "length" "4")

70468

+ (set_attr "type" "vecsimple")])

70469

+

70470

+;; Use a floating point type (V2DFmode) for the compare to set CR6 so that we

70471

+;; can use the unordered test for BCD nans and add/subtracts that overflow. An

70472

+;; UNORDERED test on an integer type (like V1TImode) is not defined. The type

70473

+;; probably should be one that can go in the VMX (Altivec) registers, so we

70474

+;; can't use DDmode or DFmode.

70475

+(define_insn "*bcd<bcd_add_sub>_test"

70476

+ [(set (reg:CCFP 74)

70477

+ (compare:CCFP

70478

+ (unspec:V2DF [(match_operand:V1TI 1 "register_operand" "v")

70479

+ (match_operand:V1TI 2 "register_operand" "v")

70480

+ (match_operand:QI 3 "const_0_to_1_operand" "i")]

70481

+ UNSPEC_BCD_ADD_SUB)

70482

+ (match_operand:V2DF 4 "zero_constant" "j")))

70483

+ (clobber (match_scratch:V1TI 0 "=v"))]

70484

+ "TARGET_P8_VECTOR"

70485

+ "bcd<bcd_add_sub>. %0,%1,%2,%3"

70486

+ [(set_attr "length" "4")

70487

+ (set_attr "type" "vecsimple")])

70488

+

70489

+(define_insn "*bcd<bcd_add_sub>_test2"

70490

+ [(set (match_operand:V1TI 0 "register_operand" "=v")

70491

+ (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "v")

70492

+ (match_operand:V1TI 2 "register_operand" "v")

70493

+ (match_operand:QI 3 "const_0_to_1_operand" "i")]

70494

+ UNSPEC_BCD_ADD_SUB))

70495

+ (set (reg:CCFP 74)

70496

+ (compare:CCFP

70497

+ (unspec:V2DF [(match_dup 1)

70498

+ (match_dup 2)

70499

+ (match_dup 3)]

70500

+ UNSPEC_BCD_ADD_SUB)

70501

+ (match_operand:V2DF 4 "zero_constant" "j")))]

70502

+ "TARGET_P8_VECTOR"

70503

+ "bcd<bcd_add_sub>. %0,%1,%2,%3"

70504

+ [(set_attr "length" "4")

70505

+ (set_attr "type" "vecsimple")])

70506

+

70507

+(define_expand "bcd<bcd_add_sub>_<code>"

70508

+ [(parallel [(set (reg:CCFP 74)

70509

+ (compare:CCFP

70510

+ (unspec:V2DF [(match_operand:V1TI 1 "register_operand" "")

70511

+ (match_operand:V1TI 2 "register_operand" "")

70512

+ (match_operand:QI 3 "const_0_to_1_operand" "")]

70513

+ UNSPEC_BCD_ADD_SUB)

70514

+ (match_dup 4)))

70515

+ (clobber (match_scratch:V1TI 5 ""))])

70516

+ (set (match_operand:SI 0 "register_operand" "")

70517

+ (BCD_TEST:SI (reg:CCFP 74)

70518

+ (const_int 0)))]

70519

+ "TARGET_P8_VECTOR"

70520

+{

70521

+ operands[4] = CONST0_RTX (V2DFmode);

70522

+})

70523

+

70524

+;; Peephole2 pattern to combine a bcdadd/bcdsub that calculates the value and

70525

+;; the bcdadd/bcdsub that tests the value. The combiner won't work since

70526

+;; CR6 is a hard coded register. Unfortunately, all of the Altivec predicate

70527

+;; support is hard coded to use the fixed register CR6 instead of creating

70528

+;; a register class for CR6.

70529

+

70530

+(define_peephole2

70531

+ [(parallel [(set (match_operand:V1TI 0 "register_operand" "")

70532

+ (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "")

70533

+ (match_operand:V1TI 2 "register_operand" "")

70534

+ (match_operand:QI 3 "const_0_to_1_operand" "")]

70535

+ UNSPEC_BCD_ADD_SUB))

70536

+ (clobber (reg:CCFP 74))])

70537

+ (parallel [(set (reg:CCFP 74)

70538

+ (compare:CCFP

70539

+ (unspec:V2DF [(match_dup 1)

70540

+ (match_dup 2)

70541

+ (match_dup 3)]

70542

+ UNSPEC_BCD_ADD_SUB)

70543

+ (match_operand:V2DF 4 "zero_constant" "")))

70544

+ (clobber (match_operand:V1TI 5 "register_operand" ""))])]

70545

+ "TARGET_P8_VECTOR"

70546

+ [(parallel [(set (match_dup 0)

70547

+ (unspec:V1TI [(match_dup 1)

70548

+ (match_dup 2)

70549

+ (match_dup 3)]

70550

+ UNSPEC_BCD_ADD_SUB))

70551

+ (set (reg:CCFP 74)

70552

+ (compare:CCFP

70553

+ (unspec:V2DF [(match_dup 1)

70554

+ (match_dup 2)

70555

+ (match_dup 3)]

70556

+ UNSPEC_BCD_ADD_SUB)

70557

+ (match_dup 4)))])])

70558

Index: gcc/config/rs6000/sysv4le.h

70559

===================================================================

70560

--- a/src/gcc/config/rs6000/sysv4le.h (.../tags/gcc_4_8_2_release)

70561

+++ b/src/gcc/config/rs6000/sysv4le.h (.../branches/gcc-4_8-branch)

70562

@@ -22,9 +22,6 @@

70563

#undef TARGET_DEFAULT

70564

#define TARGET_DEFAULT MASK_LITTLE_ENDIAN

70565

70566

-#undef CC1_ENDIAN_DEFAULT_SPEC

70567

-#define CC1_ENDIAN_DEFAULT_SPEC "%(cc1_endian_little)"

70568

-

70569

#undef DEFAULT_ASM_ENDIAN

70570

#define DEFAULT_ASM_ENDIAN " -mlittle"

70571

70572

@@ -34,3 +31,7 @@

70573

70574

#undef MULTILIB_DEFAULTS

70575

#define MULTILIB_DEFAULTS { "mlittle", "mcall-sysv" }

70576

+

70577

+/* Little-endian PowerPC64 Linux uses the ELF v2 ABI by default. */

70578

+#define LINUX64_DEFAULT_ABI_ELFv2

70579

+

70580

Index: gcc/config/rs6000/dfp.md

70581

===================================================================

70582

--- a/src/gcc/config/rs6000/dfp.md (.../tags/gcc_4_8_2_release)

70583

+++ b/src/gcc/config/rs6000/dfp.md (.../branches/gcc-4_8-branch)

70584

@@ -29,77 +29,6 @@

70585

])

70586

70587

70588

-(define_expand "movsd"

70589

- [(set (match_operand:SD 0 "nonimmediate_operand" "")

70590

- (match_operand:SD 1 "any_operand" ""))]

70591

- "TARGET_HARD_FLOAT && TARGET_FPRS"

70592

- "{ rs6000_emit_move (operands[0], operands[1], SDmode); DONE; }")

70593

-

70594

-(define_split

70595

- [(set (match_operand:SD 0 "gpc_reg_operand" "")

70596

- (match_operand:SD 1 "const_double_operand" ""))]

70597

- "reload_completed

70598

- && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)

70599

- || (GET_CODE (operands[0]) == SUBREG

70600

- && GET_CODE (SUBREG_REG (operands[0])) == REG

70601

- && REGNO (SUBREG_REG (operands[0])) <= 31))"

70602

- [(set (match_dup 2) (match_dup 3))]

70603

- "

70604

-{

70605

- long l;

70606

- REAL_VALUE_TYPE rv;

70607

-

70608

- REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);

70609

- REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);

70610

-

70611

- if (! TARGET_POWERPC64)

70612

- operands[2] = operand_subword (operands[0], 0, 0, SDmode);

70613

- else

70614

- operands[2] = gen_lowpart (SImode, operands[0]);

70615

-

70616

- operands[3] = gen_int_mode (l, SImode);

70617

-}")

70618

-

70619

-(define_insn "movsd_hardfloat"

70620

- [(set (match_operand:SD 0 "nonimmediate_operand" "=r,r,m,f,*c*l,!r,*h,!r,!r")

70621

- (match_operand:SD 1 "input_operand" "r,m,r,f,r,h,0,G,Fn"))]

70622

- "(gpc_reg_operand (operands[0], SDmode)

70623

- || gpc_reg_operand (operands[1], SDmode))

70624

- && (TARGET_HARD_FLOAT && TARGET_FPRS)"

70625

- "@

70626

- mr %0,%1

70627

- lwz%U1%X1 %0,%1

70628

- stw%U0%X0 %1,%0

70629

- fmr %0,%1

70630

- mt%0 %1

70631

- mf%1 %0

70632

- nop

70633

- #

70634

- #"

70635

- [(set_attr "type" "*,load,store,fp,mtjmpr,mfjmpr,*,*,*")

70636

- (set_attr "length" "4,4,4,4,4,4,4,4,8")])

70637

-

70638

-(define_insn "movsd_softfloat"

70639

- [(set (match_operand:SD 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,r,*h")

70640

- (match_operand:SD 1 "input_operand" "r,r,h,m,r,I,L,R,G,Fn,0"))]

70641

- "(gpc_reg_operand (operands[0], SDmode)

70642

- || gpc_reg_operand (operands[1], SDmode))

70643

- && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"

70644

- "@

70645

- mr %0,%1

70646

- mt%0 %1

70647

- mf%1 %0

70648

- lwz%U1%X1 %0,%1

70649

- stw%U0%X0 %1,%0

70650

- li %0,%1

70651

- lis %0,%v1

70652

- la %0,%a1

70653

- #

70654

- #

70655

- nop"

70656

- [(set_attr "type" "*,mtjmpr,mfjmpr,load,store,*,*,*,*,*,*")

70657

- (set_attr "length" "4,4,4,4,4,4,4,4,4,8,4")])

70658

-

70659

(define_insn "movsd_store"

70660

[(set (match_operand:DD 0 "nonimmediate_operand" "=m")

70661

(unspec:DD [(match_operand:SD 1 "input_operand" "d")]

70662

@@ -108,7 +37,14 @@

70663

|| gpc_reg_operand (operands[1], SDmode))

70664

&& TARGET_HARD_FLOAT && TARGET_FPRS"

70665

"stfd%U0%X0 %1,%0"

70666

- [(set_attr "type" "fpstore")

70667

+ [(set (attr "type")

70668

+ (if_then_else

70669

+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")

70670

+ (const_string "fpstore_ux")

70671

+ (if_then_else

70672

+ (match_test "update_address_mem (operands[0], VOIDmode)")

70673

+ (const_string "fpstore_u")

70674

+ (const_string "fpstore"))))

70675

(set_attr "length" "4")])

70676

70677

(define_insn "movsd_load"

70678

@@ -119,7 +55,14 @@

70679

|| gpc_reg_operand (operands[1], DDmode))

70680

&& TARGET_HARD_FLOAT && TARGET_FPRS"

70681

"lfd%U1%X1 %0,%1"

70682

- [(set_attr "type" "fpload")

70683

+ [(set (attr "type")

70684

+ (if_then_else

70685

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

70686

+ (const_string "fpload_ux")

70687

+ (if_then_else

70688

+ (match_test "update_address_mem (operands[1], VOIDmode)")

70689

+ (const_string "fpload_u")

70690

+ (const_string "fpload"))))

70691

(set_attr "length" "4")])

70692

70693

;; Hardware support for decimal floating point operations.

70694

@@ -182,211 +125,6 @@

70695

"fnabs %0,%1"

70696

[(set_attr "type" "fp")])

70697

70698

-(define_expand "movdd"

70699

- [(set (match_operand:DD 0 "nonimmediate_operand" "")

70700

- (match_operand:DD 1 "any_operand" ""))]

70701

- ""

70702

- "{ rs6000_emit_move (operands[0], operands[1], DDmode); DONE; }")

70703

-

70704

-(define_split

70705

- [(set (match_operand:DD 0 "gpc_reg_operand" "")

70706

- (match_operand:DD 1 "const_int_operand" ""))]

70707

- "! TARGET_POWERPC64 && reload_completed

70708

- && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)

70709

- || (GET_CODE (operands[0]) == SUBREG

70710

- && GET_CODE (SUBREG_REG (operands[0])) == REG

70711

- && REGNO (SUBREG_REG (operands[0])) <= 31))"

70712

- [(set (match_dup 2) (match_dup 4))

70713

- (set (match_dup 3) (match_dup 1))]

70714

- "

70715

-{

70716

- int endian = (WORDS_BIG_ENDIAN == 0);

70717

- HOST_WIDE_INT value = INTVAL (operands[1]);

70718

-

70719

- operands[2] = operand_subword (operands[0], endian, 0, DDmode);

70720

- operands[3] = operand_subword (operands[0], 1 - endian, 0, DDmode);

70721

-#if HOST_BITS_PER_WIDE_INT == 32

70722

- operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;

70723

-#else

70724

- operands[4] = GEN_INT (value >> 32);

70725

- operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);

70726

-#endif

70727

-}")

70728

-

70729

-(define_split

70730

- [(set (match_operand:DD 0 "gpc_reg_operand" "")

70731

- (match_operand:DD 1 "const_double_operand" ""))]

70732

- "! TARGET_POWERPC64 && reload_completed

70733

- && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)

70734

- || (GET_CODE (operands[0]) == SUBREG

70735

- && GET_CODE (SUBREG_REG (operands[0])) == REG

70736

- && REGNO (SUBREG_REG (operands[0])) <= 31))"

70737

- [(set (match_dup 2) (match_dup 4))

70738

- (set (match_dup 3) (match_dup 5))]

70739

- "

70740

-{

70741

- int endian = (WORDS_BIG_ENDIAN == 0);

70742

- long l[2];

70743

- REAL_VALUE_TYPE rv;

70744

-

70745

- REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);

70746

- REAL_VALUE_TO_TARGET_DECIMAL64 (rv, l);

70747

-

70748

- operands[2] = operand_subword (operands[0], endian, 0, DDmode);

70749

- operands[3] = operand_subword (operands[0], 1 - endian, 0, DDmode);

70750

- operands[4] = gen_int_mode (l[endian], SImode);

70751

- operands[5] = gen_int_mode (l[1 - endian], SImode);

70752

-}")

70753

-

70754

-(define_split

70755

- [(set (match_operand:DD 0 "gpc_reg_operand" "")

70756

- (match_operand:DD 1 "const_double_operand" ""))]

70757

- "TARGET_POWERPC64 && reload_completed

70758

- && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)

70759

- || (GET_CODE (operands[0]) == SUBREG

70760

- && GET_CODE (SUBREG_REG (operands[0])) == REG

70761

- && REGNO (SUBREG_REG (operands[0])) <= 31))"

70762

- [(set (match_dup 2) (match_dup 3))]

70763

- "

70764

-{

70765

- int endian = (WORDS_BIG_ENDIAN == 0);

70766

- long l[2];

70767

- REAL_VALUE_TYPE rv;

70768

-#if HOST_BITS_PER_WIDE_INT >= 64

70769

- HOST_WIDE_INT val;

70770

-#endif

70771

-

70772

- REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);

70773

- REAL_VALUE_TO_TARGET_DECIMAL64 (rv, l);

70774

-

70775

- operands[2] = gen_lowpart (DImode, operands[0]);

70776

- /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */

70777

-#if HOST_BITS_PER_WIDE_INT >= 64

70778

- val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32

70779

- | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));

70780

-

70781

- operands[3] = gen_int_mode (val, DImode);

70782

-#else

70783

- operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);

70784

-#endif

70785

-}")

70786

-

70787

-;; Don't have reload use general registers to load a constant. First,

70788

-;; it might not work if the output operand is the equivalent of

70789

-;; a non-offsettable memref, but also it is less efficient than loading

70790

-;; the constant into an FP register, since it will probably be used there.

70791

-;; The "??" is a kludge until we can figure out a more reasonable way

70792

-;; of handling these non-offsettable values.

70793

-(define_insn "*movdd_hardfloat32"

70794

- [(set (match_operand:DD 0 "nonimmediate_operand" "=!r,??r,m,d,d,m,!r,!r,!r")

70795

- (match_operand:DD 1 "input_operand" "r,m,r,d,m,d,G,H,F"))]

70796

- "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS

70797

- && (gpc_reg_operand (operands[0], DDmode)

70798

- || gpc_reg_operand (operands[1], DDmode))"

70799

- "*

70800

-{

70801

- switch (which_alternative)

70802

- {

70803

- default:

70804

- gcc_unreachable ();

70805

- case 0:

70806

- case 1:

70807

- case 2:

70808

- return \"#\";

70809

- case 3:

70810

- return \"fmr %0,%1\";

70811

- case 4:

70812

- return \"lfd%U1%X1 %0,%1\";

70813

- case 5:

70814

- return \"stfd%U0%X0 %1,%0\";

70815

- case 6:

70816

- case 7:

70817

- case 8:

70818

- return \"#\";

70819

- }

70820

-}"

70821

- [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")

70822

- (set_attr "length" "8,16,16,4,4,4,8,12,16")])

70823

-

70824

-(define_insn "*movdd_softfloat32"

70825

- [(set (match_operand:DD 0 "nonimmediate_operand" "=r,r,m,r,r,r")

70826

- (match_operand:DD 1 "input_operand" "r,m,r,G,H,F"))]

70827

- "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)

70828

- && (gpc_reg_operand (operands[0], DDmode)

70829

- || gpc_reg_operand (operands[1], DDmode))"

70830

- "#"

70831

- [(set_attr "type" "two,load,store,*,*,*")

70832

- (set_attr "length" "8,8,8,8,12,16")])

70833

-

70834

-; ld/std require word-aligned displacements -> 'Y' constraint.

70835

-; List Y->r and r->Y before r->r for reload.

70836

-(define_insn "*movdd_hardfloat64_mfpgpr"

70837

- [(set (match_operand:DD 0 "nonimmediate_operand" "=Y,r,!r,d,d,m,*c*l,!r,*h,!r,!r,!r,r,d")

70838

- (match_operand:DD 1 "input_operand" "r,Y,r,d,m,d,r,h,0,G,H,F,d,r"))]

70839

- "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS

70840

- && (gpc_reg_operand (operands[0], DDmode)

70841

- || gpc_reg_operand (operands[1], DDmode))"

70842

- "@

70843

- std%U0%X0 %1,%0

70844

- ld%U1%X1 %0,%1

70845

- mr %0,%1

70846

- fmr %0,%1

70847

- lfd%U1%X1 %0,%1

70848

- stfd%U0%X0 %1,%0

70849

- mt%0 %1

70850

- mf%1 %0

70851

- nop

70852

- #

70853

- #

70854

- #

70855

- mftgpr %0,%1

70856

- mffgpr %0,%1"

70857

- [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")

70858

- (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16,4,4")])

70859

-

70860

-; ld/std require word-aligned displacements -> 'Y' constraint.

70861

-; List Y->r and r->Y before r->r for reload.

70862

-(define_insn "*movdd_hardfloat64"

70863

- [(set (match_operand:DD 0 "nonimmediate_operand" "=Y,r,!r,d,d,m,*c*l,!r,*h,!r,!r,!r")

70864

- (match_operand:DD 1 "input_operand" "r,Y,r,d,m,d,r,h,0,G,H,F"))]

70865

- "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS

70866

- && (gpc_reg_operand (operands[0], DDmode)

70867

- || gpc_reg_operand (operands[1], DDmode))"

70868

- "@

70869

- std%U0%X0 %1,%0

70870

- ld%U1%X1 %0,%1

70871

- mr %0,%1

70872

- fmr %0,%1

70873

- lfd%U1%X1 %0,%1

70874

- stfd%U0%X0 %1,%0

70875

- mt%0 %1

70876

- mf%1 %0

70877

- nop

70878

- #

70879

- #

70880

- #"

70881

- [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*")

70882

- (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])

70883

-

70884

-(define_insn "*movdd_softfloat64"

70885

- [(set (match_operand:DD 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")

70886

- (match_operand:DD 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]

70887

- "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)

70888

- && (gpc_reg_operand (operands[0], DDmode)

70889

- || gpc_reg_operand (operands[1], DDmode))"

70890

- "@

70891

- ld%U1%X1 %0,%1

70892

- std%U0%X0 %1,%0

70893

- mr %0,%1

70894

- mt%0 %1

70895

- mf%1 %0

70896

- #

70897

- #

70898

- #

70899

- nop"

70900

- [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")

70901

- (set_attr "length" "4,4,4,4,4,8,12,16,4")])

70902

-

70903

(define_expand "negtd2"

70904

[(set (match_operand:TD 0 "gpc_reg_operand" "")

70905

(neg:TD (match_operand:TD 1 "gpc_reg_operand" "")))]

70906

@@ -410,40 +148,25 @@

70907

"")

70908

70909

(define_insn "*abstd2_fpr"

70910

- [(set (match_operand:TD 0 "gpc_reg_operand" "=d")

70911

- (abs:TD (match_operand:TD 1 "gpc_reg_operand" "d")))]

70912

+ [(set (match_operand:TD 0 "gpc_reg_operand" "=d,d")

70913

+ (abs:TD (match_operand:TD 1 "gpc_reg_operand" "0,d")))]

70914

"TARGET_HARD_FLOAT && TARGET_FPRS"

70915

- "fabs %0,%1"

70916

- [(set_attr "type" "fp")])

70917

+ "@

70918

+ fabs %0,%1

70919

+ fabs %0,%1\;fmr %L0,%L1"

70920

+ [(set_attr "type" "fp")

70921

+ (set_attr "length" "4,8")])

70922

70923

(define_insn "*nabstd2_fpr"

70924

- [(set (match_operand:TD 0 "gpc_reg_operand" "=d")

70925

- (neg:TD (abs:TD (match_operand:TD 1 "gpc_reg_operand" "d"))))]

70926

+ [(set (match_operand:TD 0 "gpc_reg_operand" "=d,d")

70927

+ (neg:TD (abs:TD (match_operand:TD 1 "gpc_reg_operand" "0,d"))))]

70928

"TARGET_HARD_FLOAT && TARGET_FPRS"

70929

- "fnabs %0,%1"

70930

- [(set_attr "type" "fp")])

70931

+ "@

70932

+ fnabs %0,%1

70933

+ fnabs %0,%1\;fmr %L0,%L1"

70934

+ [(set_attr "type" "fp")

70935

+ (set_attr "length" "4,8")])

70936

70937

-(define_expand "movtd"

70938

- [(set (match_operand:TD 0 "general_operand" "")

70939

- (match_operand:TD 1 "any_operand" ""))]

70940

- "TARGET_HARD_FLOAT && TARGET_FPRS"

70941

- "{ rs6000_emit_move (operands[0], operands[1], TDmode); DONE; }")

70942

-

70943

-; It's important to list the Y->r and r->Y moves before r->r because

70944

-; otherwise reload, given m->r, will try to pick r->r and reload it,

70945

-; which doesn't make progress.

70946

-(define_insn_and_split "*movtd_internal"

70947

- [(set (match_operand:TD 0 "nonimmediate_operand" "=m,d,d,Y,r,r")

70948

- (match_operand:TD 1 "input_operand" "d,m,d,r,YGHF,r"))]

70949

- "TARGET_HARD_FLOAT && TARGET_FPRS

70950

- && (gpc_reg_operand (operands[0], TDmode)

70951

- || gpc_reg_operand (operands[1], TDmode))"

70952

- "#"

70953

- "&& reload_completed"

70954

- [(pc)]

70955

-{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }

70956

- [(set_attr "length" "8,8,8,20,20,16")])

70957

-

70958

;; Hardware support for decimal floating point operations.

70959

70960

(define_insn "extendddtd2"

70961

@@ -599,3 +322,72 @@

70962

"TARGET_DFP"

70963

"dctfixq %0,%1"

70964

[(set_attr "type" "fp")])

70965

+

70966

+

70967

+;; Decimal builtin support

70968

+

70969

+(define_c_enum "unspec"

70970

+ [UNSPEC_DDEDPD

70971

+ UNSPEC_DENBCD

70972

+ UNSPEC_DXEX

70973

+ UNSPEC_DIEX

70974

+ UNSPEC_DSCLI

70975

+ UNSPEC_DSCRI])

70976

+

70977

+(define_mode_iterator D64_D128 [DD TD])

70978

+

70979

+(define_mode_attr dfp_suffix [(DD "")

70980

+ (TD "q")])

70981

+

70982

+(define_insn "dfp_ddedpd_<mode>"

70983

+ [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")

70984

+ (unspec:D64_D128 [(match_operand:QI 1 "const_0_to_3_operand" "i")

70985

+ (match_operand:D64_D128 2 "gpc_reg_operand" "d")]

70986

+ UNSPEC_DDEDPD))]

70987

+ "TARGET_DFP"

70988

+ "ddedpd<dfp_suffix> %1,%0,%2"

70989

+ [(set_attr "type" "fp")])

70990

+

70991

+(define_insn "dfp_denbcd_<mode>"

70992

+ [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")

70993

+ (unspec:D64_D128 [(match_operand:QI 1 "const_0_to_1_operand" "i")

70994

+ (match_operand:D64_D128 2 "gpc_reg_operand" "d")]

70995

+ UNSPEC_DENBCD))]

70996

+ "TARGET_DFP"

70997

+ "denbcd<dfp_suffix> %1,%0,%2"

70998

+ [(set_attr "type" "fp")])

70999

+

71000

+(define_insn "dfp_dxex_<mode>"

71001

+ [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")

71002

+ (unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d")]

71003

+ UNSPEC_DXEX))]

71004

+ "TARGET_DFP"

71005

+ "dxex<dfp_suffix> %0,%1"

71006

+ [(set_attr "type" "fp")])

71007

+

71008

+(define_insn "dfp_diex_<mode>"

71009

+ [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")

71010

+ (unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d")

71011

+ (match_operand:D64_D128 2 "gpc_reg_operand" "d")]

71012

+ UNSPEC_DXEX))]

71013

+ "TARGET_DFP"

71014

+ "diex<dfp_suffix> %0,%1,%2"

71015

+ [(set_attr "type" "fp")])

71016

+

71017

+(define_insn "dfp_dscli_<mode>"

71018

+ [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")

71019

+ (unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d")

71020

+ (match_operand:QI 2 "immediate_operand" "i")]

71021

+ UNSPEC_DSCLI))]

71022

+ "TARGET_DFP"

71023

+ "dscli<dfp_suffix> %0,%1,%2"

71024

+ [(set_attr "type" "fp")])

71025

+

71026

+(define_insn "dfp_dscri_<mode>"

71027

+ [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")

71028

+ (unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d")

71029

+ (match_operand:QI 2 "immediate_operand" "i")]

71030

+ UNSPEC_DSCRI))]

71031

+ "TARGET_DFP"

71032

+ "dscri<dfp_suffix> %0,%1,%2"

71033

+ [(set_attr "type" "fp")])

71034

Index: gcc/config/rs6000/t-linux64

71035

===================================================================

71036

--- a/src/gcc/config/rs6000/t-linux64 (.../tags/gcc_4_8_2_release)

71037

+++ b/src/gcc/config/rs6000/t-linux64 (.../branches/gcc-4_8-branch)

71038

@@ -25,8 +25,8 @@

71039

# it doesn't tell anything about the 32bit libraries on those systems. Set

71040

# MULTILIB_OSDIRNAMES according to what is found on the target.

71041

71042

-MULTILIB_OPTIONS = m64/m32

71043

-MULTILIB_DIRNAMES = 64 32

71044

-MULTILIB_EXTRA_OPTS = fPIC

71045

-MULTILIB_OSDIRNAMES = ../lib64$(call if_multiarch,:powerpc64-linux-gnu)

71046

-MULTILIB_OSDIRNAMES += $(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib)$(call if_multiarch,:powerpc-linux-gnu)

71047

+MULTILIB_OPTIONS := m64/m32

71048

+MULTILIB_DIRNAMES := 64 32

71049

+MULTILIB_EXTRA_OPTS :=

71050

+MULTILIB_OSDIRNAMES := m64=../lib64$(call if_multiarch,:powerpc64-linux-gnu)

71051

+MULTILIB_OSDIRNAMES += m32=$(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib)$(call if_multiarch,:powerpc-linux-gnu)

71052

Index: gcc/config/rs6000/sync.md

71053

===================================================================

71054

--- a/src/gcc/config/rs6000/sync.md (.../tags/gcc_4_8_2_release)

71055

+++ b/src/gcc/config/rs6000/sync.md (.../branches/gcc-4_8-branch)

71056

@@ -1,5 +1,5 @@

71057

;; Machine description for PowerPC synchronization instructions.

71058

71059

71060

;; Contributed by Geoffrey Keating.

71061

71062

;; This file is part of GCC.

71063

@@ -18,14 +18,23 @@

71064

;; along with GCC; see the file COPYING3. If not see

71065

;; <http://www.gnu.org/licenses/>.

71066

71067

-(define_mode_attr larx [(SI "lwarx") (DI "ldarx")])

71068

-(define_mode_attr stcx [(SI "stwcx.") (DI "stdcx.")])

71069

+(define_mode_attr larx [(QI "lbarx")

71070

+ (HI "lharx")

71071

+ (SI "lwarx")

71072

+ (DI "ldarx")

71073

+ (TI "lqarx")])

71074

71075

+(define_mode_attr stcx [(QI "stbcx.")

71076

+ (HI "sthcx.")

71077

+ (SI "stwcx.")

71078

+ (DI "stdcx.")

71079

+ (TI "stqcx.")])

71080

+

71081

(define_code_iterator FETCHOP [plus minus ior xor and])

71082

(define_code_attr fetchop_name

71083

[(plus "add") (minus "sub") (ior "or") (xor "xor") (and "and")])

71084

(define_code_attr fetchop_pred

71085

- [(plus "add_operand") (minus "gpc_reg_operand")

71086

+ [(plus "add_operand") (minus "int_reg_operand")

71087

(ior "logical_operand") (xor "logical_operand") (and "and_operand")])

71088

71089

(define_expand "mem_thread_fence"

71090

@@ -98,10 +107,17 @@

71091

"isync"

71092

[(set_attr "type" "isync")])

71093

71094

+;; Types that we should provide atomic instructions for.

71095

+(define_mode_iterator AINT [QI

71096

+ HI

71097

+ SI

71098

+ (DI "TARGET_POWERPC64")

71099

+ (TI "TARGET_SYNC_TI")])

71100

+

71101

;; The control dependency used for load dependency described

71102

;; in B.2.3 of the Power ISA 2.06B.

71103

(define_insn "loadsync_<mode>"

71104

- [(unspec_volatile:BLK [(match_operand:INT1 0 "register_operand" "r")]

71105

+ [(unspec_volatile:BLK [(match_operand:AINT 0 "register_operand" "r")]

71106

UNSPECV_ISYNC)

71107

(clobber (match_scratch:CC 1 "=y"))]

71108

""

71109

@@ -109,19 +125,74 @@

71110

[(set_attr "type" "isync")

71111

(set_attr "length" "12")])

71112

71113

+(define_insn "load_quadpti"

71114

+ [(set (match_operand:PTI 0 "quad_int_reg_operand" "=&r")

71115

+ (unspec:PTI

71116

+ [(match_operand:TI 1 "quad_memory_operand" "wQ")] UNSPEC_LSQ))]

71117

+ "TARGET_SYNC_TI

71118

+ && !reg_mentioned_p (operands[0], operands[1])"

71119

+ "lq %0,%1"

71120

+ [(set_attr "type" "load")

71121

+ (set_attr "length" "4")])

71122

+

71123

(define_expand "atomic_load<mode>"

71124

- [(set (match_operand:INT1 0 "register_operand" "") ;; output

71125

- (match_operand:INT1 1 "memory_operand" "")) ;; memory

71126

+ [(set (match_operand:AINT 0 "register_operand" "") ;; output

71127

+ (match_operand:AINT 1 "memory_operand" "")) ;; memory

71128

(use (match_operand:SI 2 "const_int_operand" ""))] ;; model

71129

""

71130

{

71131

+ if (<MODE>mode == TImode && !TARGET_SYNC_TI)

71132

+ FAIL;

71133

+

71134

enum memmodel model = (enum memmodel) INTVAL (operands[2]);

71135

71136

if (model == MEMMODEL_SEQ_CST)

71137

emit_insn (gen_hwsync ());

71138

71139

- emit_move_insn (operands[0], operands[1]);

71140

+ if (<MODE>mode != TImode)

71141

+ emit_move_insn (operands[0], operands[1]);

71142

+ else

71143

+ {

71144

+ rtx op0 = operands[0];

71145

+ rtx op1 = operands[1];

71146

+ rtx pti_reg = gen_reg_rtx (PTImode);

71147

71148

+ // Can't have indexed address for 'lq'

71149

+ if (indexed_address (XEXP (op1, 0), TImode))

71150

+ {

71151

+ rtx old_addr = XEXP (op1, 0);

71152

+ rtx new_addr = force_reg (Pmode, old_addr);

71153

+ operands[1] = op1 = replace_equiv_address (op1, new_addr);

71154

+ }

71155

+

71156

+ emit_insn (gen_load_quadpti (pti_reg, op1));

71157

+

71158

+ /* For 4.8 we need to do explicit dword copies, even in big endian mode,

71159

+ unless we are using the LRA register allocator. The 4.9 register

71160

+ allocator is smart enough to assign an even/odd pair. */

71161

+ if (WORDS_BIG_ENDIAN && rs6000_lra_flag)

71162

+ emit_move_insn (op0, gen_lowpart (TImode, pti_reg));

71163

+ else

71164

+ {

71165

+ rtx op0_lo = gen_lowpart (DImode, op0);

71166

+ rtx op0_hi = gen_highpart (DImode, op0);

71167

+ rtx pti_lo = gen_lowpart (DImode, pti_reg);

71168

+ rtx pti_hi = gen_highpart (DImode, pti_reg);

71169

+

71170

+ emit_insn (gen_rtx_CLOBBER (VOIDmode, op0));

71171

+ if (WORDS_BIG_ENDIAN)

71172

+ {

71173

+ emit_move_insn (op0_hi, pti_hi);

71174

+ emit_move_insn (op0_lo, pti_lo);

71175

+ }

71176

+ else

71177

+ {

71178

+ emit_move_insn (op0_hi, pti_lo);

71179

+ emit_move_insn (op0_lo, pti_hi);

71180

+ }

71181

+ }

71182

+ }

71183

+

71184

switch (model)

71185

{

71186

case MEMMODEL_RELAXED:

71187

@@ -129,16 +200,7 @@

71188

case MEMMODEL_CONSUME:

71189

case MEMMODEL_ACQUIRE:

71190

case MEMMODEL_SEQ_CST:

71191

- if (GET_MODE (operands[0]) == QImode)

71192

- emit_insn (gen_loadsync_qi (operands[0]));

71193

- else if (GET_MODE (operands[0]) == HImode)

71194

- emit_insn (gen_loadsync_hi (operands[0]));

71195

- else if (GET_MODE (operands[0]) == SImode)

71196

- emit_insn (gen_loadsync_si (operands[0]));

71197

- else if (GET_MODE (operands[0]) == DImode)

71198

- emit_insn (gen_loadsync_di (operands[0]));

71199

- else

71200

- gcc_unreachable ();

71201

+ emit_insn (gen_loadsync_<mode> (operands[0]));

71202

break;

71203

default:

71204

gcc_unreachable ();

71205

@@ -146,12 +208,24 @@

71206

DONE;

71207

})

71208

71209

+(define_insn "store_quadpti"

71210

+ [(set (match_operand:PTI 0 "quad_memory_operand" "=wQ")

71211

+ (unspec:PTI

71212

+ [(match_operand:PTI 1 "quad_int_reg_operand" "r")] UNSPEC_LSQ))]

71213

+ "TARGET_SYNC_TI"

71214

+ "stq %1,%0"

71215

+ [(set_attr "type" "store")

71216

+ (set_attr "length" "4")])

71217

+

71218

(define_expand "atomic_store<mode>"

71219

- [(set (match_operand:INT1 0 "memory_operand" "") ;; memory

71220

- (match_operand:INT1 1 "register_operand" "")) ;; input

71221

+ [(set (match_operand:AINT 0 "memory_operand" "") ;; memory

71222

+ (match_operand:AINT 1 "register_operand" "")) ;; input

71223

(use (match_operand:SI 2 "const_int_operand" ""))] ;; model

71224

""

71225

{

71226

+ if (<MODE>mode == TImode && !TARGET_SYNC_TI)

71227

+ FAIL;

71228

+

71229

enum memmodel model = (enum memmodel) INTVAL (operands[2]);

71230

switch (model)

71231

{

71232

@@ -166,18 +240,65 @@

71233

default:

71234

gcc_unreachable ();

71235

}

71236

- emit_move_insn (operands[0], operands[1]);

71237

+ if (<MODE>mode != TImode)

71238

+ emit_move_insn (operands[0], operands[1]);

71239

+ else

71240

+ {

71241

+ rtx op0 = operands[0];

71242

+ rtx op1 = operands[1];

71243

+ rtx pti_reg = gen_reg_rtx (PTImode);

71244

+

71245

+ // Can't have indexed address for 'stq'

71246

+ if (indexed_address (XEXP (op0, 0), TImode))

71247

+ {

71248

+ rtx old_addr = XEXP (op0, 0);

71249

+ rtx new_addr = force_reg (Pmode, old_addr);

71250

+ operands[0] = op0 = replace_equiv_address (op0, new_addr);

71251

+ }

71252

+

71253

+ /* For 4.8 we need to do explicit dword copies, even in big endian mode,

71254

+ unless we are using the LRA register allocator. The 4.9 register

71255

+ allocator is smart enough to assign an even/odd pair. */

71256

+ if (WORDS_BIG_ENDIAN && rs6000_lra_flag)

71257

+ emit_move_insn (pti_reg, gen_lowpart (PTImode, op1));

71258

+ else

71259

+ {

71260

+ rtx op1_lo = gen_lowpart (DImode, op1);

71261

+ rtx op1_hi = gen_highpart (DImode, op1);

71262

+ rtx pti_lo = gen_lowpart (DImode, pti_reg);

71263

+ rtx pti_hi = gen_highpart (DImode, pti_reg);

71264

+

71265

+ emit_insn (gen_rtx_CLOBBER (VOIDmode, pti_reg));

71266

+ if (WORDS_BIG_ENDIAN)

71267

+ {

71268

+ emit_move_insn (pti_hi, op1_hi);

71269

+ emit_move_insn (pti_lo, op1_lo);

71270

+ }

71271

+ else

71272

+ {

71273

+ emit_move_insn (pti_hi, op1_lo);

71274

+ emit_move_insn (pti_lo, op1_hi);

71275

+ }

71276

+ }

71277

+

71278

+ emit_insn (gen_store_quadpti (gen_lowpart (PTImode, op0), pti_reg));

71279

+ }

71280

+

71281

DONE;

71282

})

71283

71284

-;; ??? Power ISA 2.06B says that there *is* a load-{byte,half}-and-reserve

71285

-;; opcode that is "phased-in". Not implemented as of Power7, so not yet used,

71286

-;; but let's prepare the macros anyway.

71287

+;; Any supported integer mode that has atomic l<x>arx/st<x>cx. instrucitons

71288

+;; other than the quad memory operations, which have special restrictions.

71289

+;; Byte/halfword atomic instructions were added in ISA 2.06B, but were phased

71290

+;; in and did not show up until power8. TImode atomic lqarx/stqcx. require

71291

+;; special handling due to even/odd register requirements.

71292

+(define_mode_iterator ATOMIC [(QI "TARGET_SYNC_HI_QI")

71293

+ (HI "TARGET_SYNC_HI_QI")

71294

+ SI

71295

+ (DI "TARGET_POWERPC64")])

71296

71297

-(define_mode_iterator ATOMIC [SI (DI "TARGET_POWERPC64")])

71298

-

71299

(define_insn "load_locked<mode>"

71300

- [(set (match_operand:ATOMIC 0 "gpc_reg_operand" "=r")

71301

+ [(set (match_operand:ATOMIC 0 "int_reg_operand" "=r")

71302

(unspec_volatile:ATOMIC

71303

[(match_operand:ATOMIC 1 "memory_operand" "Z")] UNSPECV_LL))]

71304

""

71305

@@ -184,21 +305,159 @@

71306

"<larx> %0,%y1"

71307

[(set_attr "type" "load_l")])

71308

71309

+(define_insn "load_locked<QHI:mode>_si"

71310

+ [(set (match_operand:SI 0 "int_reg_operand" "=r")

71311

+ (unspec_volatile:SI

71312

+ [(match_operand:QHI 1 "memory_operand" "Z")] UNSPECV_LL))]

71313

+ "TARGET_SYNC_HI_QI"

71314

+ "<QHI:larx> %0,%y1"

71315

+ [(set_attr "type" "load_l")])

71316

+

71317

+;; Use PTImode to get even/odd register pairs.

71318

+

71319

+;; Use a temporary register to force getting an even register for the

71320

+;; lqarx/stqcrx. instructions. Under AT 7.0, we need use an explicit copy,

71321

+;; even in big endian mode, unless we are using the LRA register allocator. In

71322

+;; GCC 4.9, the register allocator is smart enough to assign a even/odd

71323

+;; register pair.

71324

+

71325

+;; On little endian systems where non-atomic quad word load/store instructions

71326

+;; are not used, the address can be register+offset, so make sure the address

71327

+;; is indexed or indirect before register allocation.

71328

+

71329

+(define_expand "load_lockedti"

71330

+ [(use (match_operand:TI 0 "quad_int_reg_operand" ""))

71331

+ (use (match_operand:TI 1 "memory_operand" ""))]

71332

+ "TARGET_SYNC_TI"

71333

+{

71334

+ rtx op0 = operands[0];

71335

+ rtx op1 = operands[1];

71336

+ rtx pti = gen_reg_rtx (PTImode);

71337

+

71338

+ if (!indexed_or_indirect_operand (op1, TImode))

71339

+ {

71340

+ rtx old_addr = XEXP (op1, 0);

71341

+ rtx new_addr = force_reg (Pmode, old_addr);

71342

+ operands[1] = op1 = change_address (op1, TImode, new_addr);

71343

+ }

71344

+

71345

+ emit_insn (gen_load_lockedpti (pti, op1));

71346

+ if (WORDS_BIG_ENDIAN && rs6000_lra_flag)

71347

+ emit_move_insn (op0, gen_lowpart (TImode, pti));

71348

+ else

71349

+ {

71350

+ rtx op0_lo = gen_lowpart (DImode, op0);

71351

+ rtx op0_hi = gen_highpart (DImode, op0);

71352

+ rtx pti_lo = gen_lowpart (DImode, pti);

71353

+ rtx pti_hi = gen_highpart (DImode, pti);

71354

+

71355

+ emit_insn (gen_rtx_CLOBBER (VOIDmode, op0));

71356

+ if (WORDS_BIG_ENDIAN)

71357

+ {

71358

+ emit_move_insn (op0_hi, pti_hi);

71359

+ emit_move_insn (op0_lo, pti_lo);

71360

+ }

71361

+ else

71362

+ {

71363

+ emit_move_insn (op0_hi, pti_lo);

71364

+ emit_move_insn (op0_lo, pti_hi);

71365

+ }

71366

+ }

71367

+ DONE;

71368

+})

71369

+

71370

+(define_insn "load_lockedpti"

71371

+ [(set (match_operand:PTI 0 "quad_int_reg_operand" "=&r")

71372

+ (unspec_volatile:PTI

71373

+ [(match_operand:TI 1 "indexed_or_indirect_operand" "Z")] UNSPECV_LL))]

71374

+ "TARGET_SYNC_TI

71375

+ && !reg_mentioned_p (operands[0], operands[1])

71376

+ && quad_int_reg_operand (operands[0], PTImode)"

71377

+ "lqarx %0,%y1"

71378

+ [(set_attr "type" "load_l")])

71379

+

71380

(define_insn "store_conditional<mode>"

71381

[(set (match_operand:CC 0 "cc_reg_operand" "=x")

71382

(unspec_volatile:CC [(const_int 0)] UNSPECV_SC))

71383

(set (match_operand:ATOMIC 1 "memory_operand" "=Z")

71384

- (match_operand:ATOMIC 2 "gpc_reg_operand" "r"))]

71385

+ (match_operand:ATOMIC 2 "int_reg_operand" "r"))]

71386

""

71387

"<stcx> %2,%y1"

71388

[(set_attr "type" "store_c")])

71389

71390

+;; Use a temporary register to force getting an even register for the

71391

+;; lqarx/stqcrx. instructions. Under AT 7.0, we need use an explicit copy,

71392

+;; even in big endian mode. In GCC 4.9, the register allocator is smart enough

71393

+;; to assign a even/odd register pair.

71394

+

71395

+;; On little endian systems where non-atomic quad word load/store instructions

71396

+;; are not used, the address can be register+offset, so make sure the address

71397

+;; is indexed or indirect before register allocation.

71398

+

71399

+(define_expand "store_conditionalti"

71400

+ [(use (match_operand:CC 0 "cc_reg_operand" ""))

71401

+ (use (match_operand:TI 1 "memory_operand" ""))

71402

+ (use (match_operand:TI 2 "quad_int_reg_operand" ""))]

71403

+ "TARGET_SYNC_TI"

71404

+{

71405

+ rtx op0 = operands[0];

71406

+ rtx op1 = operands[1];

71407

+ rtx op2 = operands[2];

71408

+ rtx addr = XEXP (op1, 0);

71409

+ rtx pti_mem;

71410

+ rtx pti_reg;

71411

+

71412

+ if (!indexed_or_indirect_operand (op1, TImode))

71413

+ {

71414

+ rtx new_addr = force_reg (Pmode, addr);

71415

+ operands[1] = op1 = change_address (op1, TImode, new_addr);

71416

+ addr = new_addr;

71417

+ }

71418

+

71419

+ pti_mem = change_address (op1, PTImode, addr);

71420

+ pti_reg = gen_reg_rtx (PTImode);

71421

+

71422

+ if (WORDS_BIG_ENDIAN && rs6000_lra_flag)

71423

+ emit_move_insn (pti_reg, gen_lowpart (PTImode, op2));

71424

+ else

71425

+ {

71426

+ rtx op2_lo = gen_lowpart (DImode, op2);

71427

+ rtx op2_hi = gen_highpart (DImode, op2);

71428

+ rtx pti_lo = gen_lowpart (DImode, pti_reg);

71429

+ rtx pti_hi = gen_highpart (DImode, pti_reg);

71430

+

71431

+ emit_insn (gen_rtx_CLOBBER (VOIDmode, op0));

71432

+ if (WORDS_BIG_ENDIAN)

71433

+ {

71434

+ emit_move_insn (pti_hi, op2_hi);

71435

+ emit_move_insn (pti_lo, op2_lo);

71436

+ }

71437

+ else

71438

+ {

71439

+ emit_move_insn (pti_hi, op2_lo);

71440

+ emit_move_insn (pti_lo, op2_hi);

71441

+ }

71442

+ }

71443

+

71444

+ emit_insn (gen_store_conditionalpti (op0, pti_mem, pti_reg));

71445

+ DONE;

71446

+})

71447

+

71448

+(define_insn "store_conditionalpti"

71449

+ [(set (match_operand:CC 0 "cc_reg_operand" "=x")

71450

+ (unspec_volatile:CC [(const_int 0)] UNSPECV_SC))

71451

+ (set (match_operand:PTI 1 "indexed_or_indirect_operand" "=Z")

71452

+ (match_operand:PTI 2 "quad_int_reg_operand" "r"))]

71453

+ "TARGET_SYNC_TI && quad_int_reg_operand (operands[2], PTImode)"

71454

+ "stqcx. %2,%y1"

71455

+ [(set_attr "type" "store_c")])

71456

+

71457

(define_expand "atomic_compare_and_swap<mode>"

71458

- [(match_operand:SI 0 "gpc_reg_operand" "") ;; bool out

71459

- (match_operand:INT1 1 "gpc_reg_operand" "") ;; val out

71460

- (match_operand:INT1 2 "memory_operand" "") ;; memory

71461

- (match_operand:INT1 3 "reg_or_short_operand" "") ;; expected

71462

- (match_operand:INT1 4 "gpc_reg_operand" "") ;; desired

71463

+ [(match_operand:SI 0 "int_reg_operand" "") ;; bool out

71464

+ (match_operand:AINT 1 "int_reg_operand" "") ;; val out

71465

+ (match_operand:AINT 2 "memory_operand" "") ;; memory

71466

+ (match_operand:AINT 3 "reg_or_short_operand" "") ;; expected

71467

+ (match_operand:AINT 4 "int_reg_operand" "") ;; desired

71468

(match_operand:SI 5 "const_int_operand" "") ;; is_weak

71469

(match_operand:SI 6 "const_int_operand" "") ;; model succ

71470

(match_operand:SI 7 "const_int_operand" "")] ;; model fail

71471

@@ -209,9 +468,9 @@

71472

})

71473

71474

(define_expand "atomic_exchange<mode>"

71475

- [(match_operand:INT1 0 "gpc_reg_operand" "") ;; output

71476

- (match_operand:INT1 1 "memory_operand" "") ;; memory

71477

- (match_operand:INT1 2 "gpc_reg_operand" "") ;; input

71478

+ [(match_operand:AINT 0 "int_reg_operand" "") ;; output

71479

+ (match_operand:AINT 1 "memory_operand" "") ;; memory

71480

+ (match_operand:AINT 2 "int_reg_operand" "") ;; input

71481

(match_operand:SI 3 "const_int_operand" "")] ;; model

71482

""

71483

{

71484

@@ -220,9 +479,9 @@

71485

})

71486

71487

(define_expand "atomic_<fetchop_name><mode>"

71488

- [(match_operand:INT1 0 "memory_operand" "") ;; memory

71489

- (FETCHOP:INT1 (match_dup 0)

71490

- (match_operand:INT1 1 "<fetchop_pred>" "")) ;; operand

71491

+ [(match_operand:AINT 0 "memory_operand" "") ;; memory

71492

+ (FETCHOP:AINT (match_dup 0)

71493

+ (match_operand:AINT 1 "<fetchop_pred>" "")) ;; operand

71494

(match_operand:SI 2 "const_int_operand" "")] ;; model

71495

""

71496

{

71497

@@ -232,8 +491,8 @@

71498

})

71499

71500

(define_expand "atomic_nand<mode>"

71501

- [(match_operand:INT1 0 "memory_operand" "") ;; memory

71502

- (match_operand:INT1 1 "gpc_reg_operand" "") ;; operand

71503

+ [(match_operand:AINT 0 "memory_operand" "") ;; memory

71504

+ (match_operand:AINT 1 "int_reg_operand" "") ;; operand

71505

(match_operand:SI 2 "const_int_operand" "")] ;; model

71506

""

71507

{

71508

@@ -243,10 +502,10 @@

71509

})

71510

71511

(define_expand "atomic_fetch_<fetchop_name><mode>"

71512

- [(match_operand:INT1 0 "gpc_reg_operand" "") ;; output

71513

- (match_operand:INT1 1 "memory_operand" "") ;; memory

71514

- (FETCHOP:INT1 (match_dup 1)

71515

- (match_operand:INT1 2 "<fetchop_pred>" "")) ;; operand

71516

+ [(match_operand:AINT 0 "int_reg_operand" "") ;; output

71517

+ (match_operand:AINT 1 "memory_operand" "") ;; memory

71518

+ (FETCHOP:AINT (match_dup 1)

71519

+ (match_operand:AINT 2 "<fetchop_pred>" "")) ;; operand

71520

(match_operand:SI 3 "const_int_operand" "")] ;; model

71521

""

71522

{

71523

@@ -256,9 +515,9 @@

71524

})

71525

71526

(define_expand "atomic_fetch_nand<mode>"

71527

- [(match_operand:INT1 0 "gpc_reg_operand" "") ;; output

71528

- (match_operand:INT1 1 "memory_operand" "") ;; memory

71529

- (match_operand:INT1 2 "gpc_reg_operand" "") ;; operand

71530

+ [(match_operand:AINT 0 "int_reg_operand" "") ;; output

71531

+ (match_operand:AINT 1 "memory_operand" "") ;; memory

71532

+ (match_operand:AINT 2 "int_reg_operand" "") ;; operand

71533

(match_operand:SI 3 "const_int_operand" "")] ;; model

71534

""

71535

{

71536

@@ -268,10 +527,10 @@

71537

})

71538

71539

(define_expand "atomic_<fetchop_name>_fetch<mode>"

71540

- [(match_operand:INT1 0 "gpc_reg_operand" "") ;; output

71541

- (match_operand:INT1 1 "memory_operand" "") ;; memory

71542

- (FETCHOP:INT1 (match_dup 1)

71543

- (match_operand:INT1 2 "<fetchop_pred>" "")) ;; operand

71544

+ [(match_operand:AINT 0 "int_reg_operand" "") ;; output

71545

+ (match_operand:AINT 1 "memory_operand" "") ;; memory

71546

+ (FETCHOP:AINT (match_dup 1)

71547

+ (match_operand:AINT 2 "<fetchop_pred>" "")) ;; operand

71548

(match_operand:SI 3 "const_int_operand" "")] ;; model

71549

""

71550

{

71551

@@ -281,9 +540,9 @@

71552

})

71553

71554

(define_expand "atomic_nand_fetch<mode>"

71555

- [(match_operand:INT1 0 "gpc_reg_operand" "") ;; output

71556

- (match_operand:INT1 1 "memory_operand" "") ;; memory

71557

- (match_operand:INT1 2 "gpc_reg_operand" "") ;; operand

71558

+ [(match_operand:AINT 0 "int_reg_operand" "") ;; output

71559

+ (match_operand:AINT 1 "memory_operand" "") ;; memory

71560

+ (match_operand:AINT 2 "int_reg_operand" "") ;; operand

71561

(match_operand:SI 3 "const_int_operand" "")] ;; model

71562

""

71563

{

71564

Index: gcc/config/rs6000/crypto.md

71565

===================================================================

71566

--- a/src/gcc/config/rs6000/crypto.md (.../tags/gcc_4_8_2_release)

71567

+++ b/src/gcc/config/rs6000/crypto.md (.../branches/gcc-4_8-branch)

71568

@@ -0,0 +1,101 @@

71569

+;; Cryptographic instructions added in ISA 2.07

71570

71571

+;; Contributed by Michael Meissner (meissner@linux.vnet.ibm.com)

71572

+

71573

+;; This file is part of GCC.

71574

+

71575

+;; GCC is free software; you can redistribute it and/or modify it

71576

+;; under the terms of the GNU General Public License as published

71577

+;; by the Free Software Foundation; either version 3, or (at your

71578

+;; option) any later version.

71579

+

71580

+;; GCC is distributed in the hope that it will be useful, but WITHOUT

71581

+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY

71582

+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public

71583

+;; License for more details.

71584

+

71585

+;; You should have received a copy of the GNU General Public License

71586

+;; along with GCC; see the file COPYING3. If not see

71587

+;; <http://www.gnu.org/licenses/>.

71588

+

71589

+(define_c_enum "unspec"

71590

+ [UNSPEC_VCIPHER

71591

+ UNSPEC_VNCIPHER

71592

+ UNSPEC_VCIPHERLAST

71593

+ UNSPEC_VNCIPHERLAST

71594

+ UNSPEC_VSBOX

71595

+ UNSPEC_VSHASIGMA

71596

+ UNSPEC_VPERMXOR

71597

+ UNSPEC_VPMSUM])

71598

+

71599

+;; Iterator for VPMSUM/VPERMXOR

71600

+(define_mode_iterator CR_mode [V16QI V8HI V4SI V2DI])

71601

+

71602

+(define_mode_attr CR_char [(V16QI "b")

71603

+ (V8HI "h")

71604

+ (V4SI "w")

71605

+ (V2DI "d")])

71606

+

71607

+;; Iterator for VSHASIGMAD/VSHASIGMAW

71608

+(define_mode_iterator CR_hash [V4SI V2DI])

71609

+

71610

+;; Iterator for the other crypto functions

71611

+(define_int_iterator CR_code [UNSPEC_VCIPHER

71612

+ UNSPEC_VNCIPHER

71613

+ UNSPEC_VCIPHERLAST

71614

+ UNSPEC_VNCIPHERLAST])

71615

+

71616

+(define_int_attr CR_insn [(UNSPEC_VCIPHER "vcipher")

71617

+ (UNSPEC_VNCIPHER "vncipher")

71618

+ (UNSPEC_VCIPHERLAST "vcipherlast")

71619

+ (UNSPEC_VNCIPHERLAST "vncipherlast")])

71620

+

71621

+;; 2 operand crypto instructions

71622

+(define_insn "crypto_<CR_insn>"

71623

+ [(set (match_operand:V2DI 0 "register_operand" "=v")

71624

+ (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "v")

71625

+ (match_operand:V2DI 2 "register_operand" "v")]

71626

+ CR_code))]

71627

+ "TARGET_CRYPTO"

71628

+ "<CR_insn> %0,%1,%2"

71629

+ [(set_attr "type" "crypto")])

71630

+

71631

+(define_insn "crypto_vpmsum<CR_char>"

71632

+ [(set (match_operand:CR_mode 0 "register_operand" "=v")

71633

+ (unspec:CR_mode [(match_operand:CR_mode 1 "register_operand" "v")

71634

+ (match_operand:CR_mode 2 "register_operand" "v")]

71635

+ UNSPEC_VPMSUM))]

71636

+ "TARGET_CRYPTO"

71637

+ "vpmsum<CR_char> %0,%1,%2"

71638

+ [(set_attr "type" "crypto")])

71639

+

71640

+;; 3 operand crypto instructions

71641

+(define_insn "crypto_vpermxor_<mode>"

71642

+ [(set (match_operand:CR_mode 0 "register_operand" "=v")

71643

+ (unspec:CR_mode [(match_operand:CR_mode 1 "register_operand" "v")

71644

+ (match_operand:CR_mode 2 "register_operand" "v")

71645

+ (match_operand:CR_mode 3 "register_operand" "v")]

71646

+ UNSPEC_VPERMXOR))]

71647

+ "TARGET_CRYPTO"

71648

+ "vpermxor %0,%1,%2,%3"

71649

+ [(set_attr "type" "crypto")])

71650

+

71651

+;; 1 operand crypto instruction

71652

+(define_insn "crypto_vsbox"

71653

+ [(set (match_operand:V2DI 0 "register_operand" "=v")

71654

+ (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "v")]

71655

+ UNSPEC_VSBOX))]

71656

+ "TARGET_CRYPTO"

71657

+ "vsbox %0,%1"

71658

+ [(set_attr "type" "crypto")])

71659

+

71660

+;; Hash crypto instructions

71661

+(define_insn "crypto_vshasigma<CR_char>"

71662

+ [(set (match_operand:CR_hash 0 "register_operand" "=v")

71663

+ (unspec:CR_hash [(match_operand:CR_hash 1 "register_operand" "v")

71664

+ (match_operand:SI 2 "const_0_to_1_operand" "n")

71665

+ (match_operand:SI 3 "const_0_to_15_operand" "n")]

71666

+ UNSPEC_VSHASIGMA))]

71667

+ "TARGET_CRYPTO"

71668

+ "vshasigma<CR_char> %0,%1,%2,%3"

71669

+ [(set_attr "type" "crypto")])

71670

Index: gcc/config/rs6000/rs6000.md

71671

===================================================================

71672

--- a/src/gcc/config/rs6000/rs6000.md (.../tags/gcc_4_8_2_release)

71673

+++ b/src/gcc/config/rs6000/rs6000.md (.../branches/gcc-4_8-branch)

71674

@@ -25,10 +25,14 @@

71675

;;

71676

71677

(define_constants

71678

- [(STACK_POINTER_REGNUM 1)

71679

+ [(FIRST_GPR_REGNO 0)

71680

+ (STACK_POINTER_REGNUM 1)

71681

(TOC_REGNUM 2)

71682

(STATIC_CHAIN_REGNUM 11)

71683

(HARD_FRAME_POINTER_REGNUM 31)

71684

+ (LAST_GPR_REGNO 31)

71685

+ (FIRST_FPR_REGNO 32)

71686

+ (LAST_FPR_REGNO 63)

71687

(LR_REGNO 65)

71688

(CTR_REGNO 66)

71689

(ARG_POINTER_REGNUM 67)

71690

@@ -49,18 +53,9 @@

71691

(SPE_ACC_REGNO 111)

71692

(SPEFSCR_REGNO 112)

71693

(FRAME_POINTER_REGNUM 113)

71694

-

71695

- ; ABI defined stack offsets for storing the TOC pointer with AIX calls.

71696

- (TOC_SAVE_OFFSET_32BIT 20)

71697

- (TOC_SAVE_OFFSET_64BIT 40)

71698

-

71699

- ; Function TOC offset in the AIX function descriptor.

71700

- (AIX_FUNC_DESC_TOC_32BIT 4)

71701

- (AIX_FUNC_DESC_TOC_64BIT 8)

71702

-

71703

- ; Static chain offset in the AIX function descriptor.

71704

- (AIX_FUNC_DESC_SC_32BIT 8)

71705

- (AIX_FUNC_DESC_SC_64BIT 16)

71706

+ (TFHAR_REGNO 114)

71707

+ (TFIAR_REGNO 115)

71708

+ (TEXASR_REGNO 116)

71709

])

71710

71711

;;

71712

@@ -123,6 +118,22 @@

71713

UNSPEC_LFIWZX

71714

UNSPEC_FCTIWUZ

71715

UNSPEC_GRP_END_NOP

71716

+ UNSPEC_P8V_FMRGOW

71717

+ UNSPEC_P8V_MTVSRWZ

71718

+ UNSPEC_P8V_RELOAD_FROM_GPR

71719

+ UNSPEC_P8V_MTVSRD

71720

+ UNSPEC_P8V_XXPERMDI

71721

+ UNSPEC_P8V_RELOAD_FROM_VSX

71722

+ UNSPEC_ADDG6S

71723

+ UNSPEC_CDTBCD

71724

+ UNSPEC_CBCDTD

71725

+ UNSPEC_DIVE

71726

+ UNSPEC_DIVEO

71727

+ UNSPEC_DIVEU

71728

+ UNSPEC_DIVEUO

71729

+ UNSPEC_UNPACK_128BIT

71730

+ UNSPEC_PACK_128BIT

71731

+ UNSPEC_LSQ

71732

])

71733

71734

;;

71735

@@ -142,7 +153,7 @@

71736

71737

;; Define an insn type attribute. This is used in function unit delay

71738

;; computations.

71739

-(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,vecdouble,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel,popcnt"

71740

+(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,vecdouble,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel,popcnt,crypto,htm"

71741

(const_string "integer"))

71742

71743

;; Define floating point instruction sub-types for use with Xfpu.md

71744

@@ -164,7 +175,7 @@

71745

;; Processor type -- this attribute must exactly match the processor_type

71746

;; enumeration in rs6000.h.

71747

71748

-(define_attr "cpu" "rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,power4,power5,power6,power7,cell,ppca2,titan"

71749

+(define_attr "cpu" "rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,power4,power5,power6,power7,cell,ppca2,titan,power8"

71750

(const (symbol_ref "rs6000_cpu_attr")))

71751

71752

71753

@@ -197,6 +208,7 @@

71754

(include "power5.md")

71755

(include "power6.md")

71756

(include "power7.md")

71757

+(include "power8.md")

71758

(include "cell.md")

71759

(include "xfpu.md")

71760

(include "a2.md")

71761

@@ -215,7 +227,7 @@

71762

(define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])

71763

71764

; Any supported integer mode.

71765

-(define_mode_iterator INT [QI HI SI DI TI])

71766

+(define_mode_iterator INT [QI HI SI DI TI PTI])

71767

71768

; Any supported integer mode that fits in one register.

71769

(define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])

71770

@@ -223,6 +235,12 @@

71771

; extend modes for DImode

71772

(define_mode_iterator QHSI [QI HI SI])

71773

71774

+; QImode or HImode for small atomic ops

71775

+(define_mode_iterator QHI [QI HI])

71776

+

71777

+; HImode or SImode for sign extended fusion ops

71778

+(define_mode_iterator HSI [HI SI])

71779

+

71780

; SImode or DImode, even if DImode doesn't fit in GPRs.

71781

(define_mode_iterator SDI [SI DI])

71782

71783

@@ -230,6 +248,10 @@

71784

; (one with a '.') will compare; and the size used for arithmetic carries.

71785

(define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])

71786

71787

+; Iterator to add PTImode along with TImode (TImode can go in VSX registers,

71788

+; PTImode is GPR only)

71789

+(define_mode_iterator TI2 [TI PTI])

71790

+

71791

; Any hardware-supported floating-point mode

71792

(define_mode_iterator FP [

71793

(SF "TARGET_HARD_FLOAT

71794

@@ -253,6 +275,50 @@

71795

(V2DF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DFmode)")

71796

])

71797

71798

+; Floating point move iterators to combine binary and decimal moves

71799

+(define_mode_iterator FMOVE32 [SF SD])

71800

+(define_mode_iterator FMOVE64 [DF DD])

71801

+(define_mode_iterator FMOVE64X [DI DF DD])

71802

+(define_mode_iterator FMOVE128 [(TF "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128")

71803

+ (TD "TARGET_HARD_FLOAT && TARGET_FPRS")])

71804

+

71805

+; Iterators for 128 bit types for direct move

71806

+(define_mode_iterator FMOVE128_GPR [(TI "TARGET_VSX_TIMODE")

71807

+ (V16QI "")

71808

+ (V8HI "")

71809

+ (V4SI "")

71810

+ (V4SF "")

71811

+ (V2DI "")

71812

+ (V2DF "")

71813

+ (V1TI "")])

71814

+

71815

+; Whether a floating point move is ok, don't allow SD without hardware FP

71816

+(define_mode_attr fmove_ok [(SF "")

71817

+ (DF "")

71818

+ (SD "TARGET_HARD_FLOAT && TARGET_FPRS")

71819

+ (DD "")])

71820

+

71821

+; Convert REAL_VALUE to the appropriate bits

71822

+(define_mode_attr real_value_to_target [(SF "REAL_VALUE_TO_TARGET_SINGLE")

71823

+ (DF "REAL_VALUE_TO_TARGET_DOUBLE")

71824

+ (SD "REAL_VALUE_TO_TARGET_DECIMAL32")

71825

+ (DD "REAL_VALUE_TO_TARGET_DECIMAL64")])

71826

+

71827

+; Definitions for load to 32-bit fpr register

71828

+(define_mode_attr f32_lr [(SF "f") (SD "wz")])

71829

+(define_mode_attr f32_lm [(SF "m") (SD "Z")])

71830

+(define_mode_attr f32_li [(SF "lfs%U1%X1 %0,%1") (SD "lfiwzx %0,%y1")])

71831

+(define_mode_attr f32_lv [(SF "lxsspx %x0,%y1") (SD "lxsiwzx %x0,%y1")])

71832

+

71833

+; Definitions for store from 32-bit fpr register

71834

+(define_mode_attr f32_sr [(SF "f") (SD "wx")])

71835

+(define_mode_attr f32_sm [(SF "m") (SD "Z")])

71836

+(define_mode_attr f32_si [(SF "stfs%U0%X0 %1,%0") (SD "stfiwx %1,%y0")])

71837

+(define_mode_attr f32_sv [(SF "stxsspx %x1,%y0") (SD "stxsiwzx %x1,%y0")])

71838

+

71839

+; Definitions for 32-bit fpr direct move

71840

+(define_mode_attr f32_dm [(SF "wn") (SD "wm")])

71841

+

71842

; These modes do not fit in integer registers in 32-bit mode.

71843

; but on e500v2, the gpr are 64 bit registers

71844

(define_mode_iterator DIFD [DI (DF "!TARGET_E500_DOUBLE") DD])

71845

@@ -263,6 +329,25 @@

71846

; Iterator for just SF/DF

71847

(define_mode_iterator SFDF [SF DF])

71848

71849

+; SF/DF suffix for traditional floating instructions

71850

+(define_mode_attr Ftrad [(SF "s") (DF "")])

71851

+

71852

+; SF/DF suffix for VSX instructions

71853

+(define_mode_attr Fvsx [(SF "sp") (DF "dp")])

71854

+

71855

+; SF/DF constraint for arithmetic on traditional floating point registers

71856

+(define_mode_attr Ff [(SF "f") (DF "d")])

71857

+

71858

+; SF/DF constraint for arithmetic on VSX registers

71859

+(define_mode_attr Fv [(SF "wy") (DF "ws")])

71860

+

71861

+; s/d suffix for things like fp_addsub_s/fp_addsub_d

71862

+(define_mode_attr Fs [(SF "s") (DF "d")])

71863

+

71864

+; FRE/FRES support

71865

+(define_mode_attr Ffre [(SF "fres") (DF "fre")])

71866

+(define_mode_attr FFRE [(SF "FRES") (DF "FRE")])

71867

+

71868

; Conditional returns.

71869

(define_code_iterator any_return [return simple_return])

71870

(define_code_attr return_pred [(return "direct_return ()")

71871

@@ -271,7 +356,14 @@

71872

71873

; Various instructions that come in SI and DI forms.

71874

; A generic w/d attribute, for things like cmpw/cmpd.

71875

-(define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])

71876

+(define_mode_attr wd [(QI "b")

71877

+ (HI "h")

71878

+ (SI "w")

71879

+ (DI "d")

71880

+ (V16QI "b")

71881

+ (V8HI "h")

71882

+ (V4SI "w")

71883

+ (V2DI "d")])

71884

71885

; DImode bits

71886

(define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])

71887

@@ -297,6 +389,8 @@

71888

71889

(define_mode_attr rreg [(SF "f")

71890

(DF "ws")

71891

+ (TF "f")

71892

+ (TD "f")

71893

(V4SF "wf")

71894

(V2DF "wd")])

71895

71896

@@ -311,6 +405,87 @@

71897

71898

(define_mode_attr TARGET_FLOAT [(SF "TARGET_SINGLE_FLOAT")

71899

(DF "TARGET_DOUBLE_FLOAT")])

71900

+

71901

+;; Mode iterator for logical operations on 128-bit types

71902

+(define_mode_iterator BOOL_128 [TI

71903

+ PTI

71904

+ (V16QI "TARGET_ALTIVEC")

71905

+ (V8HI "TARGET_ALTIVEC")

71906

+ (V4SI "TARGET_ALTIVEC")

71907

+ (V4SF "TARGET_ALTIVEC")

71908

+ (V2DI "TARGET_ALTIVEC")

71909

+ (V2DF "TARGET_ALTIVEC")

71910

+ (V1TI "TARGET_ALTIVEC")])

71911

+

71912

+;; For the GPRs we use 3 constraints for register outputs, two that are the

71913

+;; same as the output register, and a third where the output register is an

71914

+;; early clobber, so we don't have to deal with register overlaps. For the

71915

+;; vector types, we prefer to use the vector registers. For TI mode, allow

71916

+;; either.

71917

+

71918

+;; Mode attribute for boolean operation register constraints for output

71919

+(define_mode_attr BOOL_REGS_OUTPUT [(TI "&r,r,r,wa,v")

71920

+ (PTI "&r,r,r")

71921

+ (V16QI "wa,v,&?r,?r,?r")

71922

+ (V8HI "wa,v,&?r,?r,?r")

71923

+ (V4SI "wa,v,&?r,?r,?r")

71924

+ (V4SF "wa,v,&?r,?r,?r")

71925

+ (V2DI "wa,v,&?r,?r,?r")

71926

+ (V2DF "wa,v,&?r,?r,?r")

71927

+ (V1TI "wa,v,&?r,?r,?r")])

71928

+

71929

+;; Mode attribute for boolean operation register constraints for operand1

71930

+(define_mode_attr BOOL_REGS_OP1 [(TI "r,0,r,wa,v")

71931

+ (PTI "r,0,r")

71932

+ (V16QI "wa,v,r,0,r")

71933

+ (V8HI "wa,v,r,0,r")

71934

+ (V4SI "wa,v,r,0,r")

71935

+ (V4SF "wa,v,r,0,r")

71936

+ (V2DI "wa,v,r,0,r")

71937

+ (V2DF "wa,v,r,0,r")

71938

+ (V1TI "wa,v,r,0,r")])

71939

+

71940

+;; Mode attribute for boolean operation register constraints for operand2

71941

+(define_mode_attr BOOL_REGS_OP2 [(TI "r,r,0,wa,v")

71942

+ (PTI "r,r,0")

71943

+ (V16QI "wa,v,r,r,0")

71944

+ (V8HI "wa,v,r,r,0")

71945

+ (V4SI "wa,v,r,r,0")

71946

+ (V4SF "wa,v,r,r,0")

71947

+ (V2DI "wa,v,r,r,0")

71948

+ (V2DF "wa,v,r,r,0")

71949

+ (V1TI "wa,v,r,r,0")])

71950

+

71951

+;; Mode attribute for boolean operation register constraints for operand1

71952

+;; for one_cmpl. To simplify things, we repeat the constraint where 0

71953

+;; is used for operand1 or operand2

71954

+(define_mode_attr BOOL_REGS_UNARY [(TI "r,0,0,wa,v")

71955

+ (PTI "r,0,0")

71956

+ (V16QI "wa,v,r,0,0")

71957

+ (V8HI "wa,v,r,0,0")

71958

+ (V4SI "wa,v,r,0,0")

71959

+ (V4SF "wa,v,r,0,0")

71960

+ (V2DI "wa,v,r,0,0")

71961

+ (V2DF "wa,v,r,0,0")

71962

+ (V1TI "wa,v,r,0,0")])

71963

+

71964

+;; Mode attribute for the clobber of CC0 for AND expansion.

71965

+;; For the 128-bit types, we never do AND immediate, but we need to

71966

+;; get the correct number of X's for the number of operands.

71967

+(define_mode_attr BOOL_REGS_AND_CR0 [(TI "X,X,X,X,X")

71968

+ (PTI "X,X,X")

71969

+ (V16QI "X,X,X,X,X")

71970

+ (V8HI "X,X,X,X,X")

71971

+ (V4SI "X,X,X,X,X")

71972

+ (V4SF "X,X,X,X,X")

71973

+ (V2DI "X,X,X,X,X")

71974

+ (V2DF "X,X,X,X,X")

71975

+ (V1TI "X,X,X,X,X")])

71976

+

71977

+;; Mode attribute to give the correct type for integer divides

71978

+(define_mode_attr idiv_ldiv [(SI "idiv")

71979

+ (DI "ldiv")])

71980

+

71981

71982

;; Start with fixed-point load and store insns. Here we put only the more

71983

;; complex forms. Basic data transfer is done later.

71984

@@ -324,11 +499,19 @@

71985

(define_insn "*zero_extend<mode>di2_internal1"

71986

[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")

71987

(zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]

71988

- "TARGET_POWERPC64"

71989

+ "TARGET_POWERPC64 && (<MODE>mode != SImode || !TARGET_LFIWZX)"

71990

"@

71991

l<wd>z%U1%X1 %0,%1

71992

rldicl %0,%1,0,<dbits>"

71993

- [(set_attr "type" "load,*")])

71994

+ [(set_attr_alternative "type"

71995

+ [(if_then_else

71996

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

71997

+ (const_string "load_ux")

71998

+ (if_then_else

71999

+ (match_test "update_address_mem (operands[1], VOIDmode)")

72000

+ (const_string "load_u")

72001

+ (const_string "load")))

72002

+ (const_string "*")])])

72003

72004

(define_insn "*zero_extend<mode>di2_internal2"

72005

[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")

72006

@@ -382,6 +565,29 @@

72007

(const_int 0)))]

72008

"")

72009

72010

+(define_insn "*zero_extendsidi2_lfiwzx"

72011

+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wm,!wz,!wu")

72012

+ (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r,r,Z,Z")))]

72013

+ "TARGET_POWERPC64 && TARGET_LFIWZX"

72014

+ "@

72015

+ lwz%U1%X1 %0,%1

72016

+ rldicl %0,%1,0,32

72017

+ mtvsrwz %x0,%1

72018

+ lfiwzx %0,%y1

72019

+ lxsiwzx %x0,%y1"

72020

+ [(set_attr_alternative "type"

72021

+ [(if_then_else

72022

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

72023

+ (const_string "load_ux")

72024

+ (if_then_else

72025

+ (match_test "update_address_mem (operands[1], VOIDmode)")

72026

+ (const_string "load_u")

72027

+ (const_string "load")))

72028

+ (const_string "*")

72029

+ (const_string "mffgpr")

72030

+ (const_string "fpload")

72031

+ (const_string "fpload")])])

72032

+

72033

(define_insn "extendqidi2"

72034

[(set (match_operand:DI 0 "gpc_reg_operand" "=r")

72035

(sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]

72036

@@ -454,7 +660,15 @@

72037

"@

72038

lha%U1%X1 %0,%1

72039

extsh %0,%1"

72040

- [(set_attr "type" "load_ext,exts")])

72041

+ [(set_attr_alternative "type"

72042

+ [(if_then_else

72043

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

72044

+ (const_string "load_ext_ux")

72045

+ (if_then_else

72046

+ (match_test "update_address_mem (operands[1], VOIDmode)")

72047

+ (const_string "load_ext_u")

72048

+ (const_string "load_ext")))

72049

+ (const_string "exts")])])

72050

72051

(define_insn ""

72052

[(set (match_operand:DI 0 "gpc_reg_operand" "=r")

72053

@@ -521,16 +735,47 @@

72054

"TARGET_POWERPC64"

72055

"")

72056

72057

-(define_insn ""

72058

+(define_insn "*extendsidi2_lfiwax"

72059

+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wm,!wl,!wu")

72060

+ (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r,r,Z,Z")))]

72061

+ "TARGET_POWERPC64 && TARGET_LFIWAX"

72062

+ "@

72063

+ lwa%U1%X1 %0,%1

72064

+ extsw %0,%1

72065

+ mtvsrwa %x0,%1

72066

+ lfiwax %0,%y1

72067

+ lxsiwax %x0,%y1"

72068

+ [(set_attr_alternative "type"

72069

+ [(if_then_else

72070

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

72071

+ (const_string "load_ext_ux")

72072

+ (if_then_else

72073

+ (match_test "update_address_mem (operands[1], VOIDmode)")

72074

+ (const_string "load_ext_u")

72075

+ (const_string "load_ext")))

72076

+ (const_string "exts")

72077

+ (const_string "mffgpr")

72078

+ (const_string "fpload")

72079

+ (const_string "fpload")])])

72080

+

72081

+(define_insn "*extendsidi2_nocell"

72082

[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")

72083

(sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]

72084

- "TARGET_POWERPC64 && rs6000_gen_cell_microcode"

72085

+ "TARGET_POWERPC64 && rs6000_gen_cell_microcode && !TARGET_LFIWAX"

72086

"@

72087

lwa%U1%X1 %0,%1

72088

extsw %0,%1"

72089

- [(set_attr "type" "load_ext,exts")])

72090

+ [(set_attr_alternative "type"

72091

+ [(if_then_else

72092

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

72093

+ (const_string "load_ext_ux")

72094

+ (if_then_else

72095

+ (match_test "update_address_mem (operands[1], VOIDmode)")

72096

+ (const_string "load_ext_u")

72097

+ (const_string "load_ext")))

72098

+ (const_string "exts")])])

72099

72100

-(define_insn ""

72101

+(define_insn "*extendsidi2_nocell"

72102

[(set (match_operand:DI 0 "gpc_reg_operand" "=r")

72103

(sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")))]

72104

"TARGET_POWERPC64 && !rs6000_gen_cell_microcode"

72105

@@ -602,7 +847,15 @@

72106

"@

72107

lbz%U1%X1 %0,%1

72108

rlwinm %0,%1,0,0xff"

72109

- [(set_attr "type" "load,*")])

72110

+ [(set_attr_alternative "type"

72111

+ [(if_then_else

72112

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

72113

+ (const_string "load_ux")

72114

+ (if_then_else

72115

+ (match_test "update_address_mem (operands[1], VOIDmode)")

72116

+ (const_string "load_u")

72117

+ (const_string "load")))

72118

+ (const_string "*")])])

72119

72120

(define_insn ""

72121

[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")

72122

@@ -722,7 +975,15 @@

72123

"@

72124

lbz%U1%X1 %0,%1

72125

rlwinm %0,%1,0,0xff"

72126

- [(set_attr "type" "load,*")])

72127

+ [(set_attr_alternative "type"

72128

+ [(if_then_else

72129

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

72130

+ (const_string "load_ux")

72131

+ (if_then_else

72132

+ (match_test "update_address_mem (operands[1], VOIDmode)")

72133

+ (const_string "load_u")

72134

+ (const_string "load")))

72135

+ (const_string "*")])])

72136

72137

(define_insn ""

72138

[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")

72139

@@ -848,7 +1109,15 @@

72140

"@

72141

lhz%U1%X1 %0,%1

72142

rlwinm %0,%1,0,0xffff"

72143

- [(set_attr "type" "load,*")])

72144

+ [(set_attr_alternative "type"

72145

+ [(if_then_else

72146

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

72147

+ (const_string "load_ux")

72148

+ (if_then_else

72149

+ (match_test "update_address_mem (operands[1], VOIDmode)")

72150

+ (const_string "load_u")

72151

+ (const_string "load")))

72152

+ (const_string "*")])])

72153

72154

(define_insn ""

72155

[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")

72156

@@ -915,7 +1184,15 @@

72157

"@

72158

lha%U1%X1 %0,%1

72159

extsh %0,%1"

72160

- [(set_attr "type" "load_ext,exts")])

72161

+ [(set_attr_alternative "type"

72162

+ [(if_then_else

72163

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

72164

+ (const_string "load_ext_ux")

72165

+ (if_then_else

72166

+ (match_test "update_address_mem (operands[1], VOIDmode)")

72167

+ (const_string "load_ext_u")

72168

+ (const_string "load_ext")))

72169

+ (const_string "exts")])])

72170

72171

(define_insn ""

72172

[(set (match_operand:SI 0 "gpc_reg_operand" "=r")

72173

@@ -1658,7 +1935,19 @@

72174

FAIL;

72175

})

72176

72177

-(define_insn "one_cmpl<mode>2"

72178

+(define_expand "one_cmpl<mode>2"

72179

+ [(set (match_operand:SDI 0 "gpc_reg_operand" "")

72180

+ (not:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]

72181

+ ""

72182

+{

72183

+ if (<MODE>mode == DImode && !TARGET_POWERPC64)

72184

+ {

72185

+ rs6000_split_logical (operands, NOT, false, false, false, NULL_RTX);

72186

+ DONE;

72187

+ }

72188

+})

72189

+

72190

+(define_insn "*one_cmpl<mode>2"

72191

[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")

72192

(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]

72193

""

72194

@@ -1935,7 +2224,9 @@

72195

[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")

72196

(unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] UNSPEC_PARITY))]

72197

"TARGET_CMPB && TARGET_POPCNTB"

72198

- "prty<wd> %0,%1")

72199

+ "prty<wd> %0,%1"

72200

+ [(set_attr "length" "4")

72201

+ (set_attr "type" "popcnt")])

72202

72203

(define_expand "parity<mode>2"

72204

[(set (match_operand:GPR 0 "gpc_reg_operand" "")

72205

@@ -2412,7 +2703,7 @@

72206

(match_operand:SI 2 "gpc_reg_operand" "r,r"))

72207

(const_int 0)))

72208

(clobber (match_scratch:SI 3 "=r,r"))]

72209

- ""

72210

+ "TARGET_32BIT"

72211

"@

72212

mullw. %3,%1,%2

72213

#"

72214

@@ -2425,7 +2716,7 @@

72215

(match_operand:SI 2 "gpc_reg_operand" ""))

72216

(const_int 0)))

72217

(clobber (match_scratch:SI 3 ""))]

72218

- "reload_completed"

72219

+ "TARGET_32BIT && reload_completed"

72220

[(set (match_dup 3)

72221

(mult:SI (match_dup 1) (match_dup 2)))

72222

(set (match_dup 0)

72223

@@ -2440,7 +2731,7 @@

72224

(const_int 0)))

72225

(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")

72226

(mult:SI (match_dup 1) (match_dup 2)))]

72227

- ""

72228

+ "TARGET_32BIT"

72229

"@

72230

mullw. %0,%1,%2

72231

#"

72232

@@ -2454,7 +2745,7 @@

72233

(const_int 0)))

72234

(set (match_operand:SI 0 "gpc_reg_operand" "")

72235

(mult:SI (match_dup 1) (match_dup 2)))]

72236

- "reload_completed"

72237

+ "TARGET_32BIT && reload_completed"

72238

[(set (match_dup 0)

72239

(mult:SI (match_dup 1) (match_dup 2)))

72240

(set (match_dup 3)

72241

@@ -2469,10 +2760,7 @@

72242

(match_operand:GPR 2 "gpc_reg_operand" "r")))]

72243

""

72244

"div<wd>u %0,%1,%2"

72245

- [(set (attr "type")

72246

- (cond [(match_operand:SI 0 "" "")

72247

- (const_string "idiv")]

72248

- (const_string "ldiv")))])

72249

+ [(set_attr "type" "<idiv_ldiv>")])

72250

72251

72252

;; For powers of two we can do srai/aze for divide and then adjust for

72253

@@ -2496,10 +2784,7 @@

72254

(match_operand:GPR 2 "gpc_reg_operand" "r")))]

72255

""

72256

"div<wd> %0,%1,%2"

72257

- [(set (attr "type")

72258

- (cond [(match_operand:SI 0 "" "")

72259

- (const_string "idiv")]

72260

- (const_string "ldiv")))])

72261

+ [(set_attr "type" "<idiv_ldiv>")])

72262

72263

(define_expand "mod<mode>3"

72264

[(use (match_operand:GPR 0 "gpc_reg_operand" ""))

72265

@@ -3698,13 +3983,13 @@

72266

(const_int 0)))]

72267

"")

72268

72269

-(define_insn "*rotlsi3_internal7"

72270

+(define_insn "*rotlsi3_internal7le"

72271

[(set (match_operand:SI 0 "gpc_reg_operand" "=r")

72272

(zero_extend:SI

72273

(subreg:QI

72274

(rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")

72275

(match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]

72276

- ""

72277

+ "!BYTES_BIG_ENDIAN"

72278

"rlw%I2nm %0,%1,%h2,0xff"

72279

[(set (attr "cell_micro")

72280

(if_then_else (match_operand:SI 2 "const_int_operand" "")

72281

@@ -3711,7 +3996,20 @@

72282

(const_string "not")

72283

(const_string "always")))])

72284

72285

-(define_insn "*rotlsi3_internal8"

72286

+(define_insn "*rotlsi3_internal7be"

72287

+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")

72288

+ (zero_extend:SI

72289

+ (subreg:QI

72290

+ (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")

72291

+ (match_operand:SI 2 "reg_or_cint_operand" "ri")) 3)))]

72292

+ "BYTES_BIG_ENDIAN"

72293

+ "rlw%I2nm %0,%1,%h2,0xff"

72294

+ [(set (attr "cell_micro")

72295

+ (if_then_else (match_operand:SI 2 "const_int_operand" "")

72296

+ (const_string "not")

72297

+ (const_string "always")))])

72298

+

72299

+(define_insn "*rotlsi3_internal8le"

72300

[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")

72301

(compare:CC (zero_extend:SI

72302

(subreg:QI

72303

@@ -3719,7 +4017,7 @@

72304

(match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))

72305

(const_int 0)))

72306

(clobber (match_scratch:SI 3 "=r,r,r,r"))]

72307

- ""

72308

+ "!BYTES_BIG_ENDIAN"

72309

"@

72310

rlwnm. %3,%1,%2,0xff

72311

rlwinm. %3,%1,%h2,0xff

72312

@@ -3728,6 +4026,23 @@

72313

[(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

72314

(set_attr "length" "4,4,8,8")])

72315

72316

+(define_insn "*rotlsi3_internal8be"

72317

+ [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")

72318

+ (compare:CC (zero_extend:SI

72319

+ (subreg:QI

72320

+ (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")

72321

+ (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 3))

72322

+ (const_int 0)))

72323

+ (clobber (match_scratch:SI 3 "=r,r,r,r"))]

72324

+ "BYTES_BIG_ENDIAN"

72325

+ "@

72326

+ rlwnm. %3,%1,%2,0xff

72327

+ rlwinm. %3,%1,%h2,0xff

72328

+ #

72329

+ #"

72330

+ [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

72331

+ (set_attr "length" "4,4,8,8")])

72332

+

72333

(define_split

72334

[(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")

72335

(compare:CC (zero_extend:SI

72336

@@ -3736,7 +4051,7 @@

72337

(match_operand:SI 2 "reg_or_cint_operand" "")) 0))

72338

(const_int 0)))

72339

(clobber (match_scratch:SI 3 ""))]

72340

- "reload_completed"

72341

+ "!BYTES_BIG_ENDIAN && reload_completed"

72342

[(set (match_dup 3)

72343

(zero_extend:SI (subreg:QI

72344

(rotate:SI (match_dup 1)

72345

@@ -3746,7 +4061,25 @@

72346

(const_int 0)))]

72347

"")

72348

72349

-(define_insn "*rotlsi3_internal9"

72350

+(define_split

72351

+ [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")

72352

+ (compare:CC (zero_extend:SI

72353

+ (subreg:QI

72354

+ (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")

72355

+ (match_operand:SI 2 "reg_or_cint_operand" "")) 3))

72356

+ (const_int 0)))

72357

+ (clobber (match_scratch:SI 3 ""))]

72358

+ "BYTES_BIG_ENDIAN && reload_completed"

72359

+ [(set (match_dup 3)

72360

+ (zero_extend:SI (subreg:QI

72361

+ (rotate:SI (match_dup 1)

72362

+ (match_dup 2)) 3)))

72363

+ (set (match_dup 0)

72364

+ (compare:CC (match_dup 3)

72365

+ (const_int 0)))]

72366

+ "")

72367

+

72368

+(define_insn "*rotlsi3_internal9le"

72369

[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")

72370

(compare:CC (zero_extend:SI

72371

(subreg:QI

72372

@@ -3755,7 +4088,7 @@

72373

(const_int 0)))

72374

(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")

72375

(zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]

72376

- ""

72377

+ "!BYTES_BIG_ENDIAN"

72378

"@

72379

rlwnm. %0,%1,%2,0xff

72380

rlwinm. %0,%1,%h2,0xff

72381

@@ -3764,6 +4097,24 @@

72382

[(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

72383

(set_attr "length" "4,4,8,8")])

72384

72385

+(define_insn "*rotlsi3_internal9be"

72386

+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")

72387

+ (compare:CC (zero_extend:SI

72388

+ (subreg:QI

72389

+ (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")

72390

+ (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 3))

72391

+ (const_int 0)))

72392

+ (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")

72393

+ (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))]

72394

+ "BYTES_BIG_ENDIAN"

72395

+ "@

72396

+ rlwnm. %0,%1,%2,0xff

72397

+ rlwinm. %0,%1,%h2,0xff

72398

+ #

72399

+ #"

72400

+ [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

72401

+ (set_attr "length" "4,4,8,8")])

72402

+

72403

(define_split

72404

[(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")

72405

(compare:CC (zero_extend:SI

72406

@@ -3773,7 +4124,7 @@

72407

(const_int 0)))

72408

(set (match_operand:SI 0 "gpc_reg_operand" "")

72409

(zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]

72410

- "reload_completed"

72411

+ "!BYTES_BIG_ENDIAN && reload_completed"

72412

[(set (match_dup 0)

72413

(zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))

72414

(set (match_dup 3)

72415

@@ -3781,20 +4132,48 @@

72416

(const_int 0)))]

72417

"")

72418

72419

-(define_insn "*rotlsi3_internal10"

72420

+(define_split

72421

+ [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")

72422

+ (compare:CC (zero_extend:SI

72423

+ (subreg:QI

72424

+ (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")

72425

+ (match_operand:SI 2 "reg_or_cint_operand" "")) 3))

72426

+ (const_int 0)))

72427

+ (set (match_operand:SI 0 "gpc_reg_operand" "")

72428

+ (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))]

72429

+ "BYTES_BIG_ENDIAN && reload_completed"

72430

+ [(set (match_dup 0)

72431

+ (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))

72432

+ (set (match_dup 3)

72433

+ (compare:CC (match_dup 0)

72434

+ (const_int 0)))]

72435

+ "")

72436

+

72437

+(define_insn "*rotlsi3_internal10le"

72438

[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")

72439

(zero_extend:SI

72440

(subreg:HI

72441

(rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")

72442

(match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]

72443

- ""

72444

+ "!BYTES_BIG_ENDIAN"

72445

"@

72446

rlwnm %0,%1,%2,0xffff

72447

rlwinm %0,%1,%h2,0xffff"

72448

[(set_attr "type" "var_shift_rotate,integer")])

72449

72450

+(define_insn "*rotlsi3_internal10be"

72451

+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")

72452

+ (zero_extend:SI

72453

+ (subreg:HI

72454

+ (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")

72455

+ (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 2)))]

72456

+ "BYTES_BIG_ENDIAN"

72457

+ "@

72458

+ rlwnm %0,%1,%2,0xffff

72459

+ rlwinm %0,%1,%h2,0xffff"

72460

+ [(set_attr "type" "var_shift_rotate,integer")])

72461

72462

-(define_insn "*rotlsi3_internal11"

72463

+(define_insn "*rotlsi3_internal11le"

72464

[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")

72465

(compare:CC (zero_extend:SI

72466

(subreg:HI

72467

@@ -3802,7 +4181,7 @@

72468

(match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))

72469

(const_int 0)))

72470

(clobber (match_scratch:SI 3 "=r,r,r,r"))]

72471

- ""

72472

+ "!BYTES_BIG_ENDIAN"

72473

"@

72474

rlwnm. %3,%1,%2,0xffff

72475

rlwinm. %3,%1,%h2,0xffff

72476

@@ -3811,6 +4190,23 @@

72477

[(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

72478

(set_attr "length" "4,4,8,8")])

72479

72480

+(define_insn "*rotlsi3_internal11be"

72481

+ [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")

72482

+ (compare:CC (zero_extend:SI

72483

+ (subreg:HI

72484

+ (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")

72485

+ (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 2))

72486

+ (const_int 0)))

72487

+ (clobber (match_scratch:SI 3 "=r,r,r,r"))]

72488

+ "BYTES_BIG_ENDIAN"

72489

+ "@

72490

+ rlwnm. %3,%1,%2,0xffff

72491

+ rlwinm. %3,%1,%h2,0xffff

72492

+ #

72493

+ #"

72494

+ [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

72495

+ (set_attr "length" "4,4,8,8")])

72496

+

72497

(define_split

72498

[(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")

72499

(compare:CC (zero_extend:SI

72500

@@ -3819,7 +4215,7 @@

72501

(match_operand:SI 2 "reg_or_cint_operand" "")) 0))

72502

(const_int 0)))

72503

(clobber (match_scratch:SI 3 ""))]

72504

- "reload_completed"

72505

+ "!BYTES_BIG_ENDIAN && reload_completed"

72506

[(set (match_dup 3)

72507

(zero_extend:SI (subreg:HI

72508

(rotate:SI (match_dup 1)

72509

@@ -3829,7 +4225,25 @@

72510

(const_int 0)))]

72511

"")

72512

72513

-(define_insn "*rotlsi3_internal12"

72514

+(define_split

72515

+ [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")

72516

+ (compare:CC (zero_extend:SI

72517

+ (subreg:HI

72518

+ (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")

72519

+ (match_operand:SI 2 "reg_or_cint_operand" "")) 2))

72520

+ (const_int 0)))

72521

+ (clobber (match_scratch:SI 3 ""))]

72522

+ "BYTES_BIG_ENDIAN && reload_completed"

72523

+ [(set (match_dup 3)

72524

+ (zero_extend:SI (subreg:HI

72525

+ (rotate:SI (match_dup 1)

72526

+ (match_dup 2)) 2)))

72527

+ (set (match_dup 0)

72528

+ (compare:CC (match_dup 3)

72529

+ (const_int 0)))]

72530

+ "")

72531

+

72532

+(define_insn "*rotlsi3_internal12le"

72533

[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")

72534

(compare:CC (zero_extend:SI

72535

(subreg:HI

72536

@@ -3838,7 +4252,7 @@

72537

(const_int 0)))

72538

(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")

72539

(zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]

72540

- ""

72541

+ "!BYTES_BIG_ENDIAN"

72542

"@

72543

rlwnm. %0,%1,%2,0xffff

72544

rlwinm. %0,%1,%h2,0xffff

72545

@@ -3847,6 +4261,24 @@

72546

[(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

72547

(set_attr "length" "4,4,8,8")])

72548

72549

+(define_insn "*rotlsi3_internal12be"

72550

+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")

72551

+ (compare:CC (zero_extend:SI

72552

+ (subreg:HI

72553

+ (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")

72554

+ (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 2))

72555

+ (const_int 0)))

72556

+ (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")

72557

+ (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))]

72558

+ "BYTES_BIG_ENDIAN"

72559

+ "@

72560

+ rlwnm. %0,%1,%2,0xffff

72561

+ rlwinm. %0,%1,%h2,0xffff

72562

+ #

72563

+ #"

72564

+ [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

72565

+ (set_attr "length" "4,4,8,8")])

72566

+

72567

(define_split

72568

[(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")

72569

(compare:CC (zero_extend:SI

72570

@@ -3856,7 +4288,7 @@

72571

(const_int 0)))

72572

(set (match_operand:SI 0 "gpc_reg_operand" "")

72573

(zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]

72574

- "reload_completed"

72575

+ "!BYTES_BIG_ENDIAN && reload_completed"

72576

[(set (match_dup 0)

72577

(zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))

72578

(set (match_dup 3)

72579

@@ -3864,6 +4296,23 @@

72580

(const_int 0)))]

72581

"")

72582

72583

+(define_split

72584

+ [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")

72585

+ (compare:CC (zero_extend:SI

72586

+ (subreg:HI

72587

+ (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")

72588

+ (match_operand:SI 2 "reg_or_cint_operand" "")) 2))

72589

+ (const_int 0)))

72590

+ (set (match_operand:SI 0 "gpc_reg_operand" "")

72591

+ (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))]

72592

+ "BYTES_BIG_ENDIAN && reload_completed"

72593

+ [(set (match_dup 0)

72594

+ (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))

72595

+ (set (match_dup 3)

72596

+ (compare:CC (match_dup 0)

72597

+ (const_int 0)))]

72598

+ "")

72599

+

72600

(define_insn "ashlsi3"

72601

[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")

72602

(ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")

72603

@@ -4054,7 +4503,7 @@

72604

#

72605

#

72606

#"

72607

- [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

72608

+ [(set_attr "type" "fast_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

72609

(set_attr "length" "4,4,4,8,8,8")])

72610

72611

(define_split

72612

@@ -4086,7 +4535,7 @@

72613

#

72614

#

72615

#"

72616

- [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

72617

+ [(set_attr "type" "fast_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

72618

(set_attr "length" "4,4,4,8,8,8")])

72619

72620

(define_split

72621

@@ -4177,16 +4626,25 @@

72622

(const_int 0)))]

72623

"")

72624

72625

-(define_insn ""

72626

+(define_insn "*lshiftrt_internal1le"

72627

[(set (match_operand:SI 0 "gpc_reg_operand" "=r")

72628

(zero_extend:SI

72629

(subreg:QI

72630

(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")

72631

(match_operand:SI 2 "const_int_operand" "i")) 0)))]

72632

- "includes_rshift_p (operands[2], GEN_INT (255))"

72633

+ "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"

72634

"rlwinm %0,%1,%s2,0xff")

72635

72636

-(define_insn ""

72637

+(define_insn "*lshiftrt_internal1be"

72638

+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")

72639

+ (zero_extend:SI

72640

+ (subreg:QI

72641

+ (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")

72642

+ (match_operand:SI 2 "const_int_operand" "i")) 3)))]

72643

+ "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"

72644

+ "rlwinm %0,%1,%s2,0xff")

72645

+

72646

+(define_insn "*lshiftrt_internal2le"

72647

[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")

72648

(compare:CC

72649

(zero_extend:SI

72650

@@ -4195,7 +4653,7 @@

72651

(match_operand:SI 2 "const_int_operand" "i,i")) 0))

72652

(const_int 0)))

72653

(clobber (match_scratch:SI 3 "=r,r"))]

72654

- "includes_rshift_p (operands[2], GEN_INT (255))"

72655

+ "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"

72656

"@

72657

rlwinm. %3,%1,%s2,0xff

72658

#"

72659

@@ -4202,6 +4660,22 @@

72660

[(set_attr "type" "delayed_compare")

72661

(set_attr "length" "4,8")])

72662

72663

+(define_insn "*lshiftrt_internal2be"

72664

+ [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")

72665

+ (compare:CC

72666

+ (zero_extend:SI

72667

+ (subreg:QI

72668

+ (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")

72669

+ (match_operand:SI 2 "const_int_operand" "i,i")) 3))

72670

+ (const_int 0)))

72671

+ (clobber (match_scratch:SI 3 "=r,r"))]

72672

+ "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"

72673

+ "@

72674

+ rlwinm. %3,%1,%s2,0xff

72675

+ #"

72676

+ [(set_attr "type" "delayed_compare")

72677

+ (set_attr "length" "4,8")])

72678

+

72679

(define_split

72680

[(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")

72681

(compare:CC

72682

@@ -4211,7 +4685,7 @@

72683

(match_operand:SI 2 "const_int_operand" "")) 0))

72684

(const_int 0)))

72685

(clobber (match_scratch:SI 3 ""))]

72686

- "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"

72687

+ "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"

72688

[(set (match_dup 3)

72689

(zero_extend:SI (subreg:QI

72690

(lshiftrt:SI (match_dup 1)

72691

@@ -4221,7 +4695,26 @@

72692

(const_int 0)))]

72693

"")

72694

72695

-(define_insn ""

72696

+(define_split

72697

+ [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")

72698

+ (compare:CC

72699

+ (zero_extend:SI

72700

+ (subreg:QI

72701

+ (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")

72702

+ (match_operand:SI 2 "const_int_operand" "")) 3))

72703

+ (const_int 0)))

72704

+ (clobber (match_scratch:SI 3 ""))]

72705

+ "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"

72706

+ [(set (match_dup 3)

72707

+ (zero_extend:SI (subreg:QI

72708

+ (lshiftrt:SI (match_dup 1)

72709

+ (match_dup 2)) 3)))

72710

+ (set (match_dup 0)

72711

+ (compare:CC (match_dup 3)

72712

+ (const_int 0)))]

72713

+ "")

72714

+

72715

+(define_insn "*lshiftrt_internal3le"

72716

[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")

72717

(compare:CC

72718

(zero_extend:SI

72719

@@ -4231,7 +4724,7 @@

72720

(const_int 0)))

72721

(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")

72722

(zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]

72723

- "includes_rshift_p (operands[2], GEN_INT (255))"

72724

+ "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"

72725

"@

72726

rlwinm. %0,%1,%s2,0xff

72727

#"

72728

@@ -4238,6 +4731,23 @@

72729

[(set_attr "type" "delayed_compare")

72730

(set_attr "length" "4,8")])

72731

72732

+(define_insn "*lshiftrt_internal3be"

72733

+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")

72734

+ (compare:CC

72735

+ (zero_extend:SI

72736

+ (subreg:QI

72737

+ (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")

72738

+ (match_operand:SI 2 "const_int_operand" "i,i")) 3))

72739

+ (const_int 0)))

72740

+ (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")

72741

+ (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))]

72742

+ "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"

72743

+ "@

72744

+ rlwinm. %0,%1,%s2,0xff

72745

+ #"

72746

+ [(set_attr "type" "delayed_compare")

72747

+ (set_attr "length" "4,8")])

72748

+

72749

(define_split

72750

[(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")

72751

(compare:CC

72752

@@ -4248,7 +4758,7 @@

72753

(const_int 0)))

72754

(set (match_operand:SI 0 "gpc_reg_operand" "")

72755

(zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]

72756

- "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"

72757

+ "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"

72758

[(set (match_dup 0)

72759

(zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))

72760

(set (match_dup 3)

72761

@@ -4256,16 +4766,43 @@

72762

(const_int 0)))]

72763

"")

72764

72765

-(define_insn ""

72766

+(define_split

72767

+ [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")

72768

+ (compare:CC

72769

+ (zero_extend:SI

72770

+ (subreg:QI

72771

+ (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")

72772

+ (match_operand:SI 2 "const_int_operand" "")) 3))

72773

+ (const_int 0)))

72774

+ (set (match_operand:SI 0 "gpc_reg_operand" "")

72775

+ (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))]

72776

+ "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"

72777

+ [(set (match_dup 0)

72778

+ (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))

72779

+ (set (match_dup 3)

72780

+ (compare:CC (match_dup 0)

72781

+ (const_int 0)))]

72782

+ "")

72783

+

72784

+(define_insn "*lshiftrt_internal4le"

72785

[(set (match_operand:SI 0 "gpc_reg_operand" "=r")

72786

(zero_extend:SI

72787

(subreg:HI

72788

(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")

72789

(match_operand:SI 2 "const_int_operand" "i")) 0)))]

72790

- "includes_rshift_p (operands[2], GEN_INT (65535))"

72791

+ "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"

72792

"rlwinm %0,%1,%s2,0xffff")

72793

72794

-(define_insn ""

72795

+(define_insn "*lshiftrt_internal4be"

72796

+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")

72797

+ (zero_extend:SI

72798

+ (subreg:HI

72799

+ (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")

72800

+ (match_operand:SI 2 "const_int_operand" "i")) 2)))]

72801

+ "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"

72802

+ "rlwinm %0,%1,%s2,0xffff")

72803

+

72804

+(define_insn "*lshiftrt_internal5le"

72805

[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")

72806

(compare:CC

72807

(zero_extend:SI

72808

@@ -4274,7 +4811,7 @@

72809

(match_operand:SI 2 "const_int_operand" "i,i")) 0))

72810

(const_int 0)))

72811

(clobber (match_scratch:SI 3 "=r,r"))]

72812

- "includes_rshift_p (operands[2], GEN_INT (65535))"

72813

+ "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"

72814

"@

72815

rlwinm. %3,%1,%s2,0xffff

72816

#"

72817

@@ -4281,6 +4818,22 @@

72818

[(set_attr "type" "delayed_compare")

72819

(set_attr "length" "4,8")])

72820

72821

+(define_insn "*lshiftrt_internal5be"

72822

+ [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")

72823

+ (compare:CC

72824

+ (zero_extend:SI

72825

+ (subreg:HI

72826

+ (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")

72827

+ (match_operand:SI 2 "const_int_operand" "i,i")) 2))

72828

+ (const_int 0)))

72829

+ (clobber (match_scratch:SI 3 "=r,r"))]

72830

+ "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"

72831

+ "@

72832

+ rlwinm. %3,%1,%s2,0xffff

72833

+ #"

72834

+ [(set_attr "type" "delayed_compare")

72835

+ (set_attr "length" "4,8")])

72836

+

72837

(define_split

72838

[(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")

72839

(compare:CC

72840

@@ -4290,7 +4843,7 @@

72841

(match_operand:SI 2 "const_int_operand" "")) 0))

72842

(const_int 0)))

72843

(clobber (match_scratch:SI 3 ""))]

72844

- "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"

72845

+ "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"

72846

[(set (match_dup 3)

72847

(zero_extend:SI (subreg:HI

72848

(lshiftrt:SI (match_dup 1)

72849

@@ -4300,7 +4853,26 @@

72850

(const_int 0)))]

72851

"")

72852

72853

-(define_insn ""

72854

+(define_split

72855

+ [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")

72856

+ (compare:CC

72857

+ (zero_extend:SI

72858

+ (subreg:HI

72859

+ (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")

72860

+ (match_operand:SI 2 "const_int_operand" "")) 2))

72861

+ (const_int 0)))

72862

+ (clobber (match_scratch:SI 3 ""))]

72863

+ "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"

72864

+ [(set (match_dup 3)

72865

+ (zero_extend:SI (subreg:HI

72866

+ (lshiftrt:SI (match_dup 1)

72867

+ (match_dup 2)) 2)))

72868

+ (set (match_dup 0)

72869

+ (compare:CC (match_dup 3)

72870

+ (const_int 0)))]

72871

+ "")

72872

+

72873

+(define_insn "*lshiftrt_internal5le"

72874

[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")

72875

(compare:CC

72876

(zero_extend:SI

72877

@@ -4310,7 +4882,7 @@

72878

(const_int 0)))

72879

(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")

72880

(zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]

72881

- "includes_rshift_p (operands[2], GEN_INT (65535))"

72882

+ "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"

72883

"@

72884

rlwinm. %0,%1,%s2,0xffff

72885

#"

72886

@@ -4317,6 +4889,23 @@

72887

[(set_attr "type" "delayed_compare")

72888

(set_attr "length" "4,8")])

72889

72890

+(define_insn "*lshiftrt_internal5be"

72891

+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")

72892

+ (compare:CC

72893

+ (zero_extend:SI

72894

+ (subreg:HI

72895

+ (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")

72896

+ (match_operand:SI 2 "const_int_operand" "i,i")) 2))

72897

+ (const_int 0)))

72898

+ (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")

72899

+ (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))]

72900

+ "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"

72901

+ "@

72902

+ rlwinm. %0,%1,%s2,0xffff

72903

+ #"

72904

+ [(set_attr "type" "delayed_compare")

72905

+ (set_attr "length" "4,8")])

72906

+

72907

(define_split

72908

[(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")

72909

(compare:CC

72910

@@ -4327,7 +4916,7 @@

72911

(const_int 0)))

72912

(set (match_operand:SI 0 "gpc_reg_operand" "")

72913

(zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]

72914

- "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"

72915

+ "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"

72916

[(set (match_dup 0)

72917

(zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))

72918

(set (match_dup 3)

72919

@@ -4335,6 +4924,24 @@

72920

(const_int 0)))]

72921

"")

72922

72923

+(define_split

72924

+ [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")

72925

+ (compare:CC

72926

+ (zero_extend:SI

72927

+ (subreg:HI

72928

+ (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")

72929

+ (match_operand:SI 2 "const_int_operand" "")) 2))

72930

+ (const_int 0)))

72931

+ (set (match_operand:SI 0 "gpc_reg_operand" "")

72932

+ (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))]

72933

+ "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"

72934

+ [(set (match_dup 0)

72935

+ (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))

72936

+ (set (match_dup 3)

72937

+ (compare:CC (match_dup 0)

72938

+ (const_int 0)))]

72939

+ "")

72940

+

72941

(define_insn "ashrsi3"

72942

[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")

72943

(ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")

72944

@@ -4455,224 +5062,226 @@

72945

(const_int 0)))]

72946

"")

72947

72948

-;; Floating-point insns, excluding normal data motion.

72949

-;;

72950

-;; PowerPC has a full set of single-precision floating point instructions.

72951

-;;

72952

-;; For the POWER architecture, we pretend that we have both SFmode and

72953

-;; DFmode insns, while, in fact, all fp insns are actually done in double.

72954

-;; The only conversions we will do will be when storing to memory. In that

72955

-;; case, we will use the "frsp" instruction before storing.

72956

-;;

72957

-;; Note that when we store into a single-precision memory location, we need to

72958

-;; use the frsp insn first. If the register being stored isn't dead, we

72959

-;; need a scratch register for the frsp. But this is difficult when the store

72960

-;; is done by reload. It is not incorrect to do the frsp on the register in

72961

-;; this case, we just lose precision that we would have otherwise gotten but

72962

-;; is not guaranteed. Perhaps this should be tightened up at some point.

72963

+

72964

+;; Floating-point insns, excluding normal data motion. We combine the SF/DF

72965

+;; modes here, and also add in conditional vsx/power8-vector support to access

72966

+;; values in the traditional Altivec registers if the appropriate

72967

+;; -mupper-regs-{df,sf} option is enabled.

72968

72969

-(define_expand "extendsfdf2"

72970

- [(set (match_operand:DF 0 "gpc_reg_operand" "")

72971

- (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]

72972

- "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"

72973

+(define_expand "abs<mode>2"

72974

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "")

72975

+ (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))]

72976

+ "TARGET_<MODE>_INSN"

72977

"")

72978

72979

-(define_insn_and_split "*extendsfdf2_fpr"

72980

- [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d")

72981

- (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]

72982

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"

72983

+(define_insn "*abs<mode>2_fpr"

72984

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")

72985

+ (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]

72986

+ "TARGET_<MODE>_FPR"

72987

"@

72988

- #

72989

- fmr %0,%1

72990

- lfs%U1%X1 %0,%1"

72991

- "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"

72992

- [(const_int 0)]

72993

-{

72994

- emit_note (NOTE_INSN_DELETED);

72995

- DONE;

72996

-}

72997

- [(set_attr "type" "fp,fp,fpload")])

72998

+ fabs %0,%1

72999

+ xsabsdp %x0,%x1"

73000

+ [(set_attr "type" "fp")

73001

+ (set_attr "fp_type" "fp_addsub_<Fs>")])

73002

73003

-(define_expand "truncdfsf2"

73004

- [(set (match_operand:SF 0 "gpc_reg_operand" "")

73005

- (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]

73006

- "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"

73007

- "")

73008

+(define_insn "*nabs<mode>2_fpr"

73009

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")

73010

+ (neg:SFDF

73011

+ (abs:SFDF

73012

+ (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))))]

73013

+ "TARGET_<MODE>_FPR"

73014

+ "@

73015

+ fnabs %0,%1

73016

+ xsnabsdp %x0,%x1"

73017

+ [(set_attr "type" "fp")

73018

+ (set_attr "fp_type" "fp_addsub_<Fs>")])

73019

73020

-(define_insn "*truncdfsf2_fpr"

73021

- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")

73022

- (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]

73023

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"

73024

- "frsp %0,%1"

73025

- [(set_attr "type" "fp")])

73026

-

73027

-(define_expand "negsf2"

73028

- [(set (match_operand:SF 0 "gpc_reg_operand" "")

73029

- (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]

73030

- "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"

73031

+(define_expand "neg<mode>2"

73032

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "")

73033

+ (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))]

73034

+ "TARGET_<MODE>_INSN"

73035

"")

73036

73037

-(define_insn "*negsf2"

73038

- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")

73039

- (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]

73040

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"

73041

- "fneg %0,%1"

73042

- [(set_attr "type" "fp")])

73043

+(define_insn "*neg<mode>2_fpr"

73044

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")

73045

+ (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]

73046

+ "TARGET_<MODE>_FPR"

73047

+ "@

73048

+ fneg %0,%1

73049

+ xsnegdp %x0,%x1"

73050

+ [(set_attr "type" "fp")

73051

+ (set_attr "fp_type" "fp_addsub_<Fs>")])

73052

73053

-(define_expand "abssf2"

73054

- [(set (match_operand:SF 0 "gpc_reg_operand" "")

73055

- (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]

73056

- "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"

73057

+(define_expand "add<mode>3"

73058

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "")

73059

+ (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")

73060

+ (match_operand:SFDF 2 "gpc_reg_operand" "")))]

73061

+ "TARGET_<MODE>_INSN"

73062

"")

73063

73064

-(define_insn "*abssf2"

73065

- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")

73066

- (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]

73067

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"

73068

- "fabs %0,%1"

73069

- [(set_attr "type" "fp")])

73070

+(define_insn "*add<mode>3_fpr"

73071

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")

73072

+ (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")

73073

+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]

73074

+ "TARGET_<MODE>_FPR"

73075

+ "@

73076

+ fadd<Ftrad> %0,%1,%2

73077

+ xsadd<Fvsx> %x0,%x1,%x2"

73078

+ [(set_attr "type" "fp")

73079

+ (set_attr "fp_type" "fp_addsub_<Fs>")])

73080

73081

-(define_insn ""

73082

- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")

73083

- (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]

73084

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"

73085

- "fnabs %0,%1"

73086

- [(set_attr "type" "fp")])

73087

-

73088

-(define_expand "addsf3"

73089

- [(set (match_operand:SF 0 "gpc_reg_operand" "")

73090

- (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")

73091

- (match_operand:SF 2 "gpc_reg_operand" "")))]

73092

- "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"

73093

+(define_expand "sub<mode>3"

73094

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "")

73095

+ (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")

73096

+ (match_operand:SFDF 2 "gpc_reg_operand" "")))]

73097

+ "TARGET_<MODE>_INSN"

73098

"")

73099

73100

-(define_insn ""

73101

- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")

73102

- (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")

73103

- (match_operand:SF 2 "gpc_reg_operand" "f")))]

73104

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"

73105

- "fadds %0,%1,%2"

73106

+(define_insn "*sub<mode>3_fpr"

73107

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")

73108

+ (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")

73109

+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]

73110

+ "TARGET_<MODE>_FPR"

73111

+ "@

73112

+ fsub<Ftrad> %0,%1,%2

73113

+ xssub<Fvsx> %x0,%x1,%x2"

73114

[(set_attr "type" "fp")

73115

- (set_attr "fp_type" "fp_addsub_s")])

73116

+ (set_attr "fp_type" "fp_addsub_<Fs>")])

73117

73118

-(define_expand "subsf3"

73119

- [(set (match_operand:SF 0 "gpc_reg_operand" "")

73120

- (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")

73121

- (match_operand:SF 2 "gpc_reg_operand" "")))]

73122

- "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"

73123

+(define_expand "mul<mode>3"

73124

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "")

73125

+ (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")

73126

+ (match_operand:SFDF 2 "gpc_reg_operand" "")))]

73127

+ "TARGET_<MODE>_INSN"

73128

"")

73129

73130

-(define_insn ""

73131

- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")

73132

- (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")

73133

- (match_operand:SF 2 "gpc_reg_operand" "f")))]

73134

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"

73135

- "fsubs %0,%1,%2"

73136

- [(set_attr "type" "fp")

73137

- (set_attr "fp_type" "fp_addsub_s")])

73138

+(define_insn "*mul<mode>3_fpr"

73139

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")

73140

+ (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")

73141

+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]

73142

+ "TARGET_<MODE>_FPR"

73143

+ "@

73144

+ fmul<Ftrad> %0,%1,%2

73145

+ xsmul<Fvsx> %x0,%x1,%x2"

73146

+ [(set_attr "type" "dmul")

73147

+ (set_attr "fp_type" "fp_mul_<Fs>")])

73148

73149

-(define_expand "mulsf3"

73150

- [(set (match_operand:SF 0 "gpc_reg_operand" "")

73151

- (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")

73152

- (match_operand:SF 2 "gpc_reg_operand" "")))]

73153

- "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"

73154

+(define_expand "div<mode>3"

73155

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "")

73156

+ (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")

73157

+ (match_operand:SFDF 2 "gpc_reg_operand" "")))]

73158

+ "TARGET_<MODE>_INSN && !TARGET_SIMPLE_FPU"

73159

"")

73160

73161

-(define_insn ""

73162

- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")

73163

- (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")

73164

- (match_operand:SF 2 "gpc_reg_operand" "f")))]

73165

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"

73166

- "fmuls %0,%1,%2"

73167

- [(set_attr "type" "fp")

73168

- (set_attr "fp_type" "fp_mul_s")])

73169

+(define_insn "*div<mode>3_fpr"

73170

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")

73171

+ (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")

73172

+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]

73173

+ "TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU"

73174

+ "@

73175

+ fdiv<Ftrad> %0,%1,%2

73176

+ xsdiv<Fvsx> %x0,%x1,%x2"

73177

+ [(set_attr "type" "<Fs>div")

73178

+ (set_attr "fp_type" "fp_div_<Fs>")])

73179

73180

-(define_expand "divsf3"

73181

- [(set (match_operand:SF 0 "gpc_reg_operand" "")

73182

- (div:SF (match_operand:SF 1 "gpc_reg_operand" "")

73183

- (match_operand:SF 2 "gpc_reg_operand" "")))]

73184

- "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"

73185

- "")

73186

+(define_insn "sqrt<mode>2"

73187

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")

73188

+ (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]

73189

+ "TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU

73190

+ && (TARGET_PPC_GPOPT || (<MODE>mode == SFmode && TARGET_XILINX_FPU))"

73191

+ "@

73192

+ fsqrt<Ftrad> %0,%1

73193

+ xssqrt<Fvsx> %x0,%x1"

73194

+ [(set_attr "type" "<Fs>sqrt")

73195

+ (set_attr "fp_type" "fp_sqrt_<Fs>")])

73196

73197

-(define_insn ""

73198

- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")

73199

- (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")

73200

- (match_operand:SF 2 "gpc_reg_operand" "f")))]

73201

- "TARGET_HARD_FLOAT && TARGET_FPRS

73202

- && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"

73203

- "fdivs %0,%1,%2"

73204

- [(set_attr "type" "sdiv")])

73205

+;; Floating point reciprocal approximation

73206

+(define_insn "fre<Fs>"

73207

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")

73208

+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]

73209

+ UNSPEC_FRES))]

73210

+ "TARGET_<FFRE>"

73211

+ "@

73212

+ fre<Ftrad> %0,%1

73213

+ xsre<Fvsx> %x0,%x1"

73214

+ [(set_attr "type" "fp")])

73215

73216

-(define_insn "fres"

73217

- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")

73218

- (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]

73219

- "TARGET_FRES"

73220

- "fres %0,%1"

73221

+(define_insn "*rsqrt<mode>2"

73222

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")

73223

+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]

73224

+ UNSPEC_RSQRT))]

73225

+ "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"

73226

+ "@

73227

+ frsqrte<Ftrad> %0,%1

73228

+ xsrsqrte<Fvsx> %x0,%x1"

73229

[(set_attr "type" "fp")])

73230

73231

-; builtin fmaf support

73232

-(define_insn "*fmasf4_fpr"

73233

- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")

73234

- (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")

73235

- (match_operand:SF 2 "gpc_reg_operand" "f")

73236

- (match_operand:SF 3 "gpc_reg_operand" "f")))]

73237

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"

73238

- "fmadds %0,%1,%2,%3"

73239

- [(set_attr "type" "fp")

73240

- (set_attr "fp_type" "fp_maddsub_s")])

73241

+;; Floating point comparisons

73242

+(define_insn "*cmp<mode>_fpr"

73243

+ [(set (match_operand:CCFP 0 "cc_reg_operand" "=y,y")

73244

+ (compare:CCFP (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")

73245

+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]

73246

+ "TARGET_<MODE>_FPR"

73247

+ "@

73248

+ fcmpu %0,%1,%2

73249

+ xscmpudp %0,%x1,%x2"

73250

+ [(set_attr "type" "fpcompare")])

73251

73252

-(define_insn "*fmssf4_fpr"

73253

- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")

73254

- (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")

73255

- (match_operand:SF 2 "gpc_reg_operand" "f")

73256

- (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f"))))]

73257

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"

73258

- "fmsubs %0,%1,%2,%3"

73259

- [(set_attr "type" "fp")

73260

- (set_attr "fp_type" "fp_maddsub_s")])

73261

+;; Floating point conversions

73262

+(define_expand "extendsfdf2"

73263

+ [(set (match_operand:DF 0 "gpc_reg_operand" "")

73264

+ (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]

73265

+ "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"

73266

+ "")

73267

73268

-(define_insn "*nfmasf4_fpr"

73269

- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")

73270

- (neg:SF (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")

73271

- (match_operand:SF 2 "gpc_reg_operand" "f")

73272

- (match_operand:SF 3 "gpc_reg_operand" "f"))))]

73273

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"

73274

- "fnmadds %0,%1,%2,%3"

73275

- [(set_attr "type" "fp")

73276

- (set_attr "fp_type" "fp_maddsub_s")])

73277

+(define_insn_and_split "*extendsfdf2_fpr"

73278

+ [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d,ws,?ws,wv")

73279

+ (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m,0,wy,Z")))]

73280

+ "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"

73281

+ "@

73282

+ #

73283

+ fmr %0,%1

73284

+ lfs%U1%X1 %0,%1

73285

+ #

73286

+ xxlor %x0,%x1,%x1

73287

+ lxsspx %x0,%y1"

73288

+ "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"

73289

+ [(const_int 0)]

73290

+{

73291

+ emit_note (NOTE_INSN_DELETED);

73292

+ DONE;

73293

+}

73294

+ [(set_attr_alternative "type"

73295

+ [(const_string "fp")

73296

+ (const_string "fp")

73297

+ (if_then_else

73298

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

73299

+ (const_string "fpload_ux")

73300

+ (if_then_else

73301

+ (match_test "update_address_mem (operands[1], VOIDmode)")

73302

+ (const_string "fpload_u")

73303

+ (const_string "fpload")))

73304

+ (const_string "fp")

73305

+ (const_string "vecsimple")

73306

+ (if_then_else

73307

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

73308

+ (const_string "fpload_ux")

73309

+ (if_then_else

73310

+ (match_test "update_address_mem (operands[1], VOIDmode)")

73311

+ (const_string "fpload_u")

73312

+ (const_string "fpload")))])])

73313

73314

-(define_insn "*nfmssf4_fpr"

73315

- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")

73316

- (neg:SF (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")

73317

- (match_operand:SF 2 "gpc_reg_operand" "f")

73318

- (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f")))))]

73319

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"

73320

- "fnmsubs %0,%1,%2,%3"

73321

- [(set_attr "type" "fp")

73322

- (set_attr "fp_type" "fp_maddsub_s")])

73323

-

73324

-(define_expand "sqrtsf2"

73325

+(define_expand "truncdfsf2"

73326

[(set (match_operand:SF 0 "gpc_reg_operand" "")

73327

- (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]

73328

- "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU)

73329

- && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT

73330

- && !TARGET_SIMPLE_FPU"

73331

+ (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]

73332

+ "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"

73333

"")

73334

73335

-(define_insn ""

73336

+(define_insn "*truncdfsf2_fpr"

73337

[(set (match_operand:SF 0 "gpc_reg_operand" "=f")

73338

- (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]

73339

- "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT

73340

- && TARGET_FPRS && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"

73341

- "fsqrts %0,%1"

73342

- [(set_attr "type" "ssqrt")])

73343

-

73344

-(define_insn "*rsqrtsf_internal1"

73345

- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")

73346

- (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]

73347

- UNSPEC_RSQRT))]

73348

- "TARGET_FRSQRTES"

73349

- "frsqrtes %0,%1"

73350

+ (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]

73351

+ "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"

73352

+ "frsp %0,%1"

73353

[(set_attr "type" "fp")])

73354

73355

;; This expander is here to avoid FLOAT_WORDS_BIGENDIAN tests in

73356

@@ -4742,12 +5351,14 @@

73357

;; Use an unspec rather providing an if-then-else in RTL, to prevent the

73358

;; compiler from optimizing -0.0

73359

(define_insn "copysign<mode>3_fcpsgn"

73360

- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")

73361

- (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")

73362

- (match_operand:SFDF 2 "gpc_reg_operand" "<rreg2>")]

73363

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")

73364

+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")

73365

+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")]

73366

UNSPEC_COPYSIGN))]

73367

- "TARGET_CMPB && !VECTOR_UNIT_VSX_P (<MODE>mode)"

73368

- "fcpsgn %0,%2,%1"

73369

+ "TARGET_<MODE>_FPR && TARGET_CMPB"

73370

+ "@

73371

+ fcpsgn %0,%2,%1

73372

+ xscpsgn<Fvsx> %x0,%x2,%x1"

73373

[(set_attr "type" "fp")])

73374

73375

;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a

73376

@@ -4754,27 +5365,70 @@

73377

;; fsel instruction and some auxiliary computations. Then we just have a

73378

;; single DEFINE_INSN for fsel and the define_splits to make them if made by

73379

;; combine.

73380

-(define_expand "smaxsf3"

73381

- [(set (match_operand:SF 0 "gpc_reg_operand" "")

73382

- (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")

73383

- (match_operand:SF 2 "gpc_reg_operand" ""))

73384

- (match_dup 1)

73385

- (match_dup 2)))]

73386

- "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS

73387

- && TARGET_SINGLE_FLOAT && !flag_trapping_math"

73388

- "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")

73389

+;; For MIN, MAX on non-VSX machines, and conditional move all of the time, we

73390

+;; use DEFINE_EXPAND's that involve a fsel instruction and some auxiliary

73391

+;; computations. Then we just have a single DEFINE_INSN for fsel and the

73392

+;; define_splits to make them if made by combine. On VSX machines we have the

73393

+;; min/max instructions.

73394

+;;

73395

+;; On VSX, we only check for TARGET_VSX instead of checking for a vsx/p8 vector

73396

+;; to allow either DF/SF to use only traditional registers.

73397

73398

-(define_expand "sminsf3"

73399

- [(set (match_operand:SF 0 "gpc_reg_operand" "")

73400

- (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")

73401

- (match_operand:SF 2 "gpc_reg_operand" ""))

73402

- (match_dup 2)

73403

- (match_dup 1)))]

73404

- "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS

73405

- && TARGET_SINGLE_FLOAT && !flag_trapping_math"

73406

- "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")

73407

+(define_expand "smax<mode>3"

73408

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "")

73409

+ (if_then_else:SFDF (ge (match_operand:SFDF 1 "gpc_reg_operand" "")

73410

+ (match_operand:SFDF 2 "gpc_reg_operand" ""))

73411

+ (match_dup 1)

73412

+ (match_dup 2)))]

73413

+ "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math"

73414

+{

73415

+ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);

73416

+ DONE;

73417

+})

73418

73419

+(define_insn "*smax<mode>3_vsx"

73420

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")

73421

+ (smax:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")

73422

+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]

73423

+ "TARGET_<MODE>_FPR && TARGET_VSX"

73424

+ "xsmaxdp %x0,%x1,%x2"

73425

+ [(set_attr "type" "fp")])

73426

+

73427

+(define_expand "smin<mode>3"

73428

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "")

73429

+ (if_then_else:SFDF (ge (match_operand:SFDF 1 "gpc_reg_operand" "")

73430

+ (match_operand:SFDF 2 "gpc_reg_operand" ""))

73431

+ (match_dup 2)

73432

+ (match_dup 1)))]

73433

+ "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math"

73434

+{

73435

+ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);

73436

+ DONE;

73437

+})

73438

+

73439

+(define_insn "*smin<mode>3_vsx"

73440

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")

73441

+ (smin:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")

73442

+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]

73443

+ "TARGET_<MODE>_FPR && TARGET_VSX"

73444

+ "xsmindp %x0,%x1,%x2"

73445

+ [(set_attr "type" "fp")])

73446

+

73447

(define_split

73448

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "")

73449

+ (match_operator:SFDF 3 "min_max_operator"

73450

+ [(match_operand:SFDF 1 "gpc_reg_operand" "")

73451

+ (match_operand:SFDF 2 "gpc_reg_operand" "")]))]

73452

+ "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math

73453

+ && !TARGET_VSX"

73454

+ [(const_int 0)]

73455

+{

73456

+ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), operands[1],

73457

+ operands[2]);

73458

+ DONE;

73459

+})

73460

+

73461

+(define_split

73462

[(set (match_operand:SF 0 "gpc_reg_operand" "")

73463

(match_operator:SF 3 "min_max_operator"

73464

[(match_operand:SF 1 "gpc_reg_operand" "")

73465

@@ -4904,208 +5558,9 @@

73466

"fsel %0,%1,%2,%3"

73467

[(set_attr "type" "fp")])

73468

73469

-(define_expand "negdf2"

73470

- [(set (match_operand:DF 0 "gpc_reg_operand" "")

73471

- (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]

73472

- "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"

73473

- "")

73474

-

73475

-(define_insn "*negdf2_fpr"

73476

- [(set (match_operand:DF 0 "gpc_reg_operand" "=d")

73477

- (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]

73478

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT

73479

- && !VECTOR_UNIT_VSX_P (DFmode)"

73480

- "fneg %0,%1"

73481

- [(set_attr "type" "fp")])

73482

-

73483

-(define_expand "absdf2"

73484

- [(set (match_operand:DF 0 "gpc_reg_operand" "")

73485

- (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]

73486

- "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"

73487

- "")

73488

-

73489

-(define_insn "*absdf2_fpr"

73490

- [(set (match_operand:DF 0 "gpc_reg_operand" "=d")

73491

- (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]

73492

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT

73493

- && !VECTOR_UNIT_VSX_P (DFmode)"

73494

- "fabs %0,%1"

73495

- [(set_attr "type" "fp")])

73496

-

73497

-(define_insn "*nabsdf2_fpr"

73498

- [(set (match_operand:DF 0 "gpc_reg_operand" "=d")

73499

- (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d"))))]

73500

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT

73501

- && !VECTOR_UNIT_VSX_P (DFmode)"

73502

- "fnabs %0,%1"

73503

- [(set_attr "type" "fp")])

73504

-

73505

-(define_expand "adddf3"

73506

- [(set (match_operand:DF 0 "gpc_reg_operand" "")

73507

- (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")

73508

- (match_operand:DF 2 "gpc_reg_operand" "")))]

73509

- "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"

73510

- "")

73511

-

73512

-(define_insn "*adddf3_fpr"

73513

- [(set (match_operand:DF 0 "gpc_reg_operand" "=d")

73514

- (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%d")

73515

- (match_operand:DF 2 "gpc_reg_operand" "d")))]

73516

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT

73517

- && !VECTOR_UNIT_VSX_P (DFmode)"

73518

- "fadd %0,%1,%2"

73519

- [(set_attr "type" "fp")

73520

- (set_attr "fp_type" "fp_addsub_d")])

73521

-

73522

-(define_expand "subdf3"

73523

- [(set (match_operand:DF 0 "gpc_reg_operand" "")

73524

- (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")

73525

- (match_operand:DF 2 "gpc_reg_operand" "")))]

73526

- "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"

73527

- "")

73528

-

73529

-(define_insn "*subdf3_fpr"

73530

- [(set (match_operand:DF 0 "gpc_reg_operand" "=d")

73531

- (minus:DF (match_operand:DF 1 "gpc_reg_operand" "d")

73532

- (match_operand:DF 2 "gpc_reg_operand" "d")))]

73533

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT

73534

- && !VECTOR_UNIT_VSX_P (DFmode)"

73535

- "fsub %0,%1,%2"

73536

- [(set_attr "type" "fp")

73537

- (set_attr "fp_type" "fp_addsub_d")])

73538

-

73539

-(define_expand "muldf3"

73540

- [(set (match_operand:DF 0 "gpc_reg_operand" "")

73541

- (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")

73542

- (match_operand:DF 2 "gpc_reg_operand" "")))]

73543

- "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"

73544

- "")

73545

-

73546

-(define_insn "*muldf3_fpr"

73547

- [(set (match_operand:DF 0 "gpc_reg_operand" "=d")

73548

- (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")

73549

- (match_operand:DF 2 "gpc_reg_operand" "d")))]

73550

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT

73551

- && !VECTOR_UNIT_VSX_P (DFmode)"

73552

- "fmul %0,%1,%2"

73553

- [(set_attr "type" "dmul")

73554

- (set_attr "fp_type" "fp_mul_d")])

73555

-

73556

-(define_expand "divdf3"

73557

- [(set (match_operand:DF 0 "gpc_reg_operand" "")

73558

- (div:DF (match_operand:DF 1 "gpc_reg_operand" "")

73559

- (match_operand:DF 2 "gpc_reg_operand" "")))]

73560

- "TARGET_HARD_FLOAT

73561

- && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)

73562

- && !TARGET_SIMPLE_FPU"

73563

- "")

73564

-

73565

-(define_insn "*divdf3_fpr"

73566

- [(set (match_operand:DF 0 "gpc_reg_operand" "=d")

73567

- (div:DF (match_operand:DF 1 "gpc_reg_operand" "d")

73568

- (match_operand:DF 2 "gpc_reg_operand" "d")))]

73569

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !TARGET_SIMPLE_FPU

73570

- && !VECTOR_UNIT_VSX_P (DFmode)"

73571

- "fdiv %0,%1,%2"

73572

- [(set_attr "type" "ddiv")])

73573

-

73574

-(define_insn "*fred_fpr"

73575

- [(set (match_operand:DF 0 "gpc_reg_operand" "=f")

73576

- (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]

73577

- "TARGET_FRE && !VECTOR_UNIT_VSX_P (DFmode)"

73578

- "fre %0,%1"

73579

- [(set_attr "type" "fp")])

73580

-

73581

-(define_insn "*rsqrtdf_internal1"

73582

- [(set (match_operand:DF 0 "gpc_reg_operand" "=d")

73583

- (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")]

73584

- UNSPEC_RSQRT))]

73585

- "TARGET_FRSQRTE && !VECTOR_UNIT_VSX_P (DFmode)"

73586

- "frsqrte %0,%1"

73587

- [(set_attr "type" "fp")])

73588

-

73589

-; builtin fma support

73590

-(define_insn "*fmadf4_fpr"

73591

- [(set (match_operand:DF 0 "gpc_reg_operand" "=f")

73592

- (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")

73593

- (match_operand:DF 2 "gpc_reg_operand" "f")

73594

- (match_operand:DF 3 "gpc_reg_operand" "f")))]

73595

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT

73596

- && VECTOR_UNIT_NONE_P (DFmode)"

73597

- "fmadd %0,%1,%2,%3"

73598

- [(set_attr "type" "fp")

73599

- (set_attr "fp_type" "fp_maddsub_d")])

73600

-

73601

-(define_insn "*fmsdf4_fpr"

73602

- [(set (match_operand:DF 0 "gpc_reg_operand" "=f")

73603

- (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")

73604

- (match_operand:DF 2 "gpc_reg_operand" "f")

73605

- (neg:DF (match_operand:DF 3 "gpc_reg_operand" "f"))))]

73606

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT

73607

- && VECTOR_UNIT_NONE_P (DFmode)"

73608

- "fmsub %0,%1,%2,%3"

73609

- [(set_attr "type" "fp")

73610

- (set_attr "fp_type" "fp_maddsub_d")])

73611

-

73612

-(define_insn "*nfmadf4_fpr"

73613

- [(set (match_operand:DF 0 "gpc_reg_operand" "=f")

73614

- (neg:DF (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")

73615

- (match_operand:DF 2 "gpc_reg_operand" "f")

73616

- (match_operand:DF 3 "gpc_reg_operand" "f"))))]

73617

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT

73618

- && VECTOR_UNIT_NONE_P (DFmode)"

73619

- "fnmadd %0,%1,%2,%3"

73620

- [(set_attr "type" "fp")

73621

- (set_attr "fp_type" "fp_maddsub_d")])

73622

-

73623

-(define_insn "*nfmsdf4_fpr"

73624

- [(set (match_operand:DF 0 "gpc_reg_operand" "=f")

73625

- (neg:DF (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")

73626

- (match_operand:DF 2 "gpc_reg_operand" "f")

73627

- (neg:DF (match_operand:DF 3 "gpc_reg_operand" "f")))))]

73628

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT

73629

- && VECTOR_UNIT_NONE_P (DFmode)"

73630

- "fnmsub %0,%1,%2,%3"

73631

- [(set_attr "type" "fp")

73632

- (set_attr "fp_type" "fp_maddsub_d")])

73633

-

73634

-(define_expand "sqrtdf2"

73635

- [(set (match_operand:DF 0 "gpc_reg_operand" "")

73636

- (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "")))]

73637

- "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"

73638

- "")

73639

-

73640

-(define_insn "*sqrtdf2_fpr"

73641

- [(set (match_operand:DF 0 "gpc_reg_operand" "=d")

73642

- (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]

73643

- "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT

73644

- && !VECTOR_UNIT_VSX_P (DFmode)"

73645

- "fsqrt %0,%1"

73646

- [(set_attr "type" "dsqrt")])

73647

-

73648

;; The conditional move instructions allow us to perform max and min

73649

;; operations even when

73650

73651

-(define_expand "smaxdf3"

73652

- [(set (match_operand:DF 0 "gpc_reg_operand" "")

73653

- (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")

73654

- (match_operand:DF 2 "gpc_reg_operand" ""))

73655

- (match_dup 1)

73656

- (match_dup 2)))]

73657

- "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT

73658

- && !flag_trapping_math"

73659

- "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")

73660

-

73661

-(define_expand "smindf3"

73662

- [(set (match_operand:DF 0 "gpc_reg_operand" "")

73663

- (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")

73664

- (match_operand:DF 2 "gpc_reg_operand" ""))

73665

- (match_dup 2)

73666

- (match_dup 1)))]

73667

- "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT

73668

- && !flag_trapping_math"

73669

- "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")

73670

-

73671

(define_split

73672

[(set (match_operand:DF 0 "gpc_reg_operand" "")

73673

(match_operator:DF 3 "min_max_operator"

73674

@@ -5159,12 +5614,15 @@

73675

; We don't define lfiwax/lfiwzx with the normal definition, because we

73676

; don't want to support putting SImode in FPR registers.

73677

(define_insn "lfiwax"

73678

- [(set (match_operand:DI 0 "gpc_reg_operand" "=d")

73679

- (unspec:DI [(match_operand:SI 1 "indexed_or_indirect_operand" "Z")]

73680

+ [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wm,!wm")

73681

+ (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]

73682

UNSPEC_LFIWAX))]

73683

"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX"

73684

- "lfiwax %0,%y1"

73685

- [(set_attr "type" "fpload")])

73686

+ "@

73687

+ lfiwax %0,%y1

73688

+ lxsiwax %x0,%y1

73689

+ mtvsrwa %x0,%1"

73690

+ [(set_attr "type" "fpload,fpload,mffgpr")])

73691

73692

; This split must be run before register allocation because it allocates the

73693

; memory slot that is needed to move values to/from the FPR. We don't allocate

73694

@@ -5186,7 +5644,8 @@

73695

rtx src = operands[1];

73696

rtx tmp;

73697

73698

- if (!MEM_P (src) && TARGET_MFPGPR && TARGET_POWERPC64)

73699

+ if (!MEM_P (src) && TARGET_POWERPC64

73700

+ && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))

73701

tmp = convert_to_mode (DImode, src, false);

73702

else

73703

{

73704

@@ -5235,12 +5694,15 @@

73705

(set_attr "type" "fpload")])

73706

73707

(define_insn "lfiwzx"

73708

- [(set (match_operand:DI 0 "gpc_reg_operand" "=d")

73709

- (unspec:DI [(match_operand:SI 1 "indexed_or_indirect_operand" "Z")]

73710

+ [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wm,!wm")

73711

+ (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]

73712

UNSPEC_LFIWZX))]

73713

"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX"

73714

- "lfiwzx %0,%y1"

73715

- [(set_attr "type" "fpload")])

73716

+ "@

73717

+ lfiwzx %0,%y1

73718

+ lxsiwzx %x0,%y1

73719

+ mtvsrwz %x0,%1"

73720

+ [(set_attr "type" "fpload,fpload,mftgpr")])

73721

73722

(define_insn_and_split "floatunssi<mode>2_lfiwzx"

73723

[(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")

73724

@@ -5257,7 +5719,8 @@

73725

rtx src = operands[1];

73726

rtx tmp;

73727

73728

- if (!MEM_P (src) && TARGET_MFPGPR && TARGET_POWERPC64)

73729

+ if (!MEM_P (src) && TARGET_POWERPC64

73730

+ && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))

73731

tmp = convert_to_mode (DImode, src, true);

73732

else

73733

{

73734

@@ -5548,7 +6011,7 @@

73735

emit_insn (gen_stfiwx (dest, tmp));

73736

DONE;

73737

}

73738

- else if (TARGET_MFPGPR && TARGET_POWERPC64)

73739

+ else if (TARGET_POWERPC64 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))

73740

{

73741

dest = gen_lowpart (DImode, dest);

73742

emit_move_insn (dest, tmp);

73743

@@ -5642,7 +6105,7 @@

73744

emit_insn (gen_stfiwx (dest, tmp));

73745

DONE;

73746

}

73747

- else if (TARGET_MFPGPR && TARGET_POWERPC64)

73748

+ else if (TARGET_POWERPC64 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))

73749

{

73750

dest = gen_lowpart (DImode, dest);

73751

emit_move_insn (dest, tmp);

73752

@@ -5781,66 +6244,52 @@

73753

[(set (match_operand:DI 0 "gpc_reg_operand" "=d")

73754

(unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]

73755

UNSPEC_FCTID))]

73756

- "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"

73757

+ "TARGET_<MODE>_FPR && TARGET_FPRND"

73758

"fctid %0,%1"

73759

[(set_attr "type" "fp")])

73760

73761

-(define_expand "btrunc<mode>2"

73762

- [(set (match_operand:SFDF 0 "gpc_reg_operand" "")

73763

- (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]

73764

+(define_insn "btrunc<mode>2"

73765

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")

73766

+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]

73767

UNSPEC_FRIZ))]

73768

- "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"

73769

- "")

73770

+ "TARGET_<MODE>_FPR && TARGET_FPRND"

73771

+ "@

73772

+ friz %0,%1

73773

+ xsrdpiz %x0,%x1"

73774

+ [(set_attr "type" "fp")

73775

+ (set_attr "fp_type" "fp_addsub_<Fs>")])

73776

73777

-(define_insn "*btrunc<mode>2_fpr"

73778

- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")

73779

- (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]

73780

- UNSPEC_FRIZ))]

73781

- "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>

73782

- && !VECTOR_UNIT_VSX_P (<MODE>mode)"

73783

- "friz %0,%1"

73784

- [(set_attr "type" "fp")])

73785

-

73786

-(define_expand "ceil<mode>2"

73787

- [(set (match_operand:SFDF 0 "gpc_reg_operand" "")

73788

- (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]

73789

+(define_insn "ceil<mode>2"

73790

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")

73791

+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]

73792

UNSPEC_FRIP))]

73793

- "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"

73794

- "")

73795

+ "TARGET_<MODE>_FPR && TARGET_FPRND"

73796

+ "@

73797

+ frip %0,%1

73798

+ xsrdpip %x0,%x1"

73799

+ [(set_attr "type" "fp")

73800

+ (set_attr "fp_type" "fp_addsub_<Fs>")])

73801

73802

-(define_insn "*ceil<mode>2_fpr"

73803

- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")

73804

- (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]

73805

- UNSPEC_FRIP))]

73806

- "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>

73807

- && !VECTOR_UNIT_VSX_P (<MODE>mode)"

73808

- "frip %0,%1"

73809

- [(set_attr "type" "fp")])

73810

-

73811

-(define_expand "floor<mode>2"

73812

- [(set (match_operand:SFDF 0 "gpc_reg_operand" "")

73813

- (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]

73814

+(define_insn "floor<mode>2"

73815

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")

73816

+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]

73817

UNSPEC_FRIM))]

73818

- "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"

73819

- "")

73820

+ "TARGET_<MODE>_FPR && TARGET_FPRND"

73821

+ "@

73822

+ frim %0,%1

73823

+ xsrdpim %x0,%x1"

73824

+ [(set_attr "type" "fp")

73825

+ (set_attr "fp_type" "fp_addsub_<Fs>")])

73826

73827

-(define_insn "*floor<mode>2_fpr"

73828

- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")

73829

- (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]

73830

- UNSPEC_FRIM))]

73831

- "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>

73832

- && !VECTOR_UNIT_VSX_P (<MODE>mode)"

73833

- "frim %0,%1"

73834

- [(set_attr "type" "fp")])

73835

-

73836

;; No VSX equivalent to frin

73837

(define_insn "round<mode>2"

73838

[(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")

73839

(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]

73840

UNSPEC_FRIN))]

73841

- "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"

73842

+ "TARGET_<MODE>_FPR && TARGET_FPRND"

73843

"frin %0,%1"

73844

- [(set_attr "type" "fp")])

73845

+ [(set_attr "type" "fp")

73846

+ (set_attr "fp_type" "fp_addsub_<Fs>")])

73847

73848

; An UNSPEC is used so we don't have to support SImode in FP registers.

73849

(define_insn "stfiwx"

73850

@@ -6084,6 +6533,49 @@

73851

[(set_attr "length" "8")

73852

(set_attr "type" "fpload")])

73853

73854

+;; Define the TImode operations that can be done in a small number

73855

+;; of instructions. The & constraints are to prevent the register

73856

+;; allocator from allocating registers that overlap with the inputs

73857

+;; (for example, having an input in 7,8 and an output in 6,7). We

73858

+;; also allow for the output being the same as one of the inputs.

73859

+

73860

+(define_insn "addti3"

73861

+ [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,&r,r,r")

73862

+ (plus:TI (match_operand:TI 1 "gpc_reg_operand" "%r,r,0,0")

73863

+ (match_operand:TI 2 "reg_or_short_operand" "r,I,r,I")))]

73864

+ "TARGET_64BIT"

73865

+{

73866

+ if (WORDS_BIG_ENDIAN)

73867

+ return (GET_CODE (operands[2])) != CONST_INT

73868

+ ? \"addc %L0,%L1,%L2\;adde %0,%1,%2\"

73869

+ : \"addic %L0,%L1,%2\;add%G2e %0,%1\";

73870

+ else

73871

+ return (GET_CODE (operands[2])) != CONST_INT

73872

+ ? \"addc %0,%1,%2\;adde %L0,%L1,%L2\"

73873

+ : \"addic %0,%1,%2\;add%G2e %L0,%L1\";

73874

+}

73875

+ [(set_attr "type" "two")

73876

+ (set_attr "length" "8")])

73877

+

73878

+(define_insn "subti3"

73879

+ [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,&r,r,r,r")

73880

+ (minus:TI (match_operand:TI 1 "reg_or_short_operand" "r,I,0,r,I")

73881

+ (match_operand:TI 2 "gpc_reg_operand" "r,r,r,0,0")))]

73882

+ "TARGET_64BIT"

73883

+{

73884

+ if (WORDS_BIG_ENDIAN)

73885

+ return (GET_CODE (operands[1]) != CONST_INT)

73886

+ ? \"subfc %L0,%L2,%L1\;subfe %0,%2,%1\"

73887

+ : \"subfic %L0,%L2,%1\;subf%G1e %0,%2\";

73888

+ else

73889

+ return (GET_CODE (operands[1]) != CONST_INT)

73890

+ ? \"subfc %0,%2,%1\;subfe %L0,%L2,%L1\"

73891

+ : \"subfic %0,%2,%1\;subf%G1e %L0,%L2\";

73892

+}

73893

+ [(set_attr "type" "two")

73894

+ (set_attr "length" "8")])

73895

+

73896

+

73897

;; Define the DImode operations that can be done in a small number

73898

;; of instructions. The & constraints are to prevent the register

73899

;; allocator from allocating registers that overlap with the inputs

73900

@@ -6260,11 +6752,11 @@

73901

[(set_attr "type" "two,three")

73902

(set_attr "length" "8,12")])

73903

73904

-(define_insn "*ashrdisi3_noppc64"

73905

+(define_insn "*ashrdisi3_noppc64be"

73906

[(set (match_operand:SI 0 "gpc_reg_operand" "=r")

73907

(subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")

73908

(const_int 32)) 4))]

73909

- "TARGET_32BIT && !TARGET_POWERPC64"

73910

+ "TARGET_32BIT && !TARGET_POWERPC64 && WORDS_BIG_ENDIAN"

73911

"*

73912

{

73913

if (REGNO (operands[0]) == REGNO (operands[1]))

73914

@@ -6551,19 +7043,31 @@

73915

(const_int 0)))]

73916

"")

73917

73918

-(define_insn "*rotldi3_internal7"

73919

+(define_insn "*rotldi3_internal7le"

73920

[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")

73921

(zero_extend:DI

73922

(subreg:QI

73923

(rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")

73924

(match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]

73925

- "TARGET_POWERPC64"

73926

+ "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"

73927

"@

73928

rldcl %0,%1,%2,56

73929

rldicl %0,%1,%H2,56"

73930

[(set_attr "type" "var_shift_rotate,integer")])

73931

73932

-(define_insn "*rotldi3_internal8"

73933

+(define_insn "*rotldi3_internal7be"

73934

+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")

73935

+ (zero_extend:DI

73936

+ (subreg:QI

73937

+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")

73938

+ (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 7)))]

73939

+ "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"

73940

+ "@

73941

+ rldcl %0,%1,%2,56

73942

+ rldicl %0,%1,%H2,56"

73943

+ [(set_attr "type" "var_shift_rotate,integer")])

73944

+

73945

+(define_insn "*rotldi3_internal8le"

73946

[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")

73947

(compare:CC (zero_extend:DI

73948

(subreg:QI

73949

@@ -6571,7 +7075,7 @@

73950

(match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))

73951

(const_int 0)))

73952

(clobber (match_scratch:DI 3 "=r,r,r,r"))]

73953

- "TARGET_64BIT"

73954

+ "TARGET_64BIT && !BYTES_BIG_ENDIAN"

73955

"@

73956

rldcl. %3,%1,%2,56

73957

rldicl. %3,%1,%H2,56

73958

@@ -6580,6 +7084,23 @@

73959

[(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

73960

(set_attr "length" "4,4,8,8")])

73961

73962

+(define_insn "*rotldi3_internal8be"

73963

+ [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")

73964

+ (compare:CC (zero_extend:DI

73965

+ (subreg:QI

73966

+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")

73967

+ (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 7))

73968

+ (const_int 0)))

73969

+ (clobber (match_scratch:DI 3 "=r,r,r,r"))]

73970

+ "TARGET_64BIT && BYTES_BIG_ENDIAN"

73971

+ "@

73972

+ rldcl. %3,%1,%2,56

73973

+ rldicl. %3,%1,%H2,56

73974

+ #

73975

+ #"

73976

+ [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

73977

+ (set_attr "length" "4,4,8,8")])

73978

+

73979

(define_split

73980

[(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")

73981

(compare:CC (zero_extend:DI

73982

@@ -6588,7 +7109,7 @@

73983

(match_operand:DI 2 "reg_or_cint_operand" "")) 0))

73984

(const_int 0)))

73985

(clobber (match_scratch:DI 3 ""))]

73986

- "TARGET_POWERPC64 && reload_completed"

73987

+ "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"

73988

[(set (match_dup 3)

73989

(zero_extend:DI (subreg:QI

73990

(rotate:DI (match_dup 1)

73991

@@ -6598,7 +7119,25 @@

73992

(const_int 0)))]

73993

"")

73994

73995

-(define_insn "*rotldi3_internal9"

73996

+(define_split

73997

+ [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")

73998

+ (compare:CC (zero_extend:DI

73999

+ (subreg:QI

74000

+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")

74001

+ (match_operand:DI 2 "reg_or_cint_operand" "")) 7))

74002

+ (const_int 0)))

74003

+ (clobber (match_scratch:DI 3 ""))]

74004

+ "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"

74005

+ [(set (match_dup 3)

74006

+ (zero_extend:DI (subreg:QI

74007

+ (rotate:DI (match_dup 1)

74008

+ (match_dup 2)) 7)))

74009

+ (set (match_dup 0)

74010

+ (compare:CC (match_dup 3)

74011

+ (const_int 0)))]

74012

+ "")

74013

+

74014

+(define_insn "*rotldi3_internal9le"

74015

[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")

74016

(compare:CC (zero_extend:DI

74017

(subreg:QI

74018

@@ -6607,7 +7146,7 @@

74019

(const_int 0)))

74020

(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")

74021

(zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]

74022

- "TARGET_64BIT"

74023

+ "TARGET_64BIT && !BYTES_BIG_ENDIAN"

74024

"@

74025

rldcl. %0,%1,%2,56

74026

rldicl. %0,%1,%H2,56

74027

@@ -6616,6 +7155,24 @@

74028

[(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

74029

(set_attr "length" "4,4,8,8")])

74030

74031

+(define_insn "*rotldi3_internal9be"

74032

+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")

74033

+ (compare:CC (zero_extend:DI

74034

+ (subreg:QI

74035

+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")

74036

+ (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 7))

74037

+ (const_int 0)))

74038

+ (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")

74039

+ (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]

74040

+ "TARGET_64BIT && BYTES_BIG_ENDIAN"

74041

+ "@

74042

+ rldcl. %0,%1,%2,56

74043

+ rldicl. %0,%1,%H2,56

74044

+ #

74045

+ #"

74046

+ [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

74047

+ (set_attr "length" "4,4,8,8")])

74048

+

74049

(define_split

74050

[(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")

74051

(compare:CC (zero_extend:DI

74052

@@ -6625,7 +7182,7 @@

74053

(const_int 0)))

74054

(set (match_operand:DI 0 "gpc_reg_operand" "")

74055

(zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]

74056

- "TARGET_POWERPC64 && reload_completed"

74057

+ "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"

74058

[(set (match_dup 0)

74059

(zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))

74060

(set (match_dup 3)

74061

@@ -6633,19 +7190,48 @@

74062

(const_int 0)))]

74063

"")

74064

74065

-(define_insn "*rotldi3_internal10"

74066

+(define_split

74067

+ [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")

74068

+ (compare:CC (zero_extend:DI

74069

+ (subreg:QI

74070

+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")

74071

+ (match_operand:DI 2 "reg_or_cint_operand" "")) 7))

74072

+ (const_int 0)))

74073

+ (set (match_operand:DI 0 "gpc_reg_operand" "")

74074

+ (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]

74075

+ "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"

74076

+ [(set (match_dup 0)

74077

+ (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))

74078

+ (set (match_dup 3)

74079

+ (compare:CC (match_dup 0)

74080

+ (const_int 0)))]

74081

+ "")

74082

+

74083

+(define_insn "*rotldi3_internal10le"

74084

[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")

74085

(zero_extend:DI

74086

(subreg:HI

74087

(rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")

74088

(match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]

74089

- "TARGET_POWERPC64"

74090

+ "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"

74091

"@

74092

rldcl %0,%1,%2,48

74093

rldicl %0,%1,%H2,48"

74094

[(set_attr "type" "var_shift_rotate,integer")])

74095

74096

-(define_insn "*rotldi3_internal11"

74097

+(define_insn "*rotldi3_internal10be"

74098

+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")

74099

+ (zero_extend:DI

74100

+ (subreg:HI

74101

+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")

74102

+ (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 6)))]

74103

+ "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"

74104

+ "@

74105

+ rldcl %0,%1,%2,48

74106

+ rldicl %0,%1,%H2,48"

74107

+ [(set_attr "type" "var_shift_rotate,integer")])

74108

+

74109

+(define_insn "*rotldi3_internal11le"

74110

[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")

74111

(compare:CC (zero_extend:DI

74112

(subreg:HI

74113

@@ -6653,7 +7239,7 @@

74114

(match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))

74115

(const_int 0)))

74116

(clobber (match_scratch:DI 3 "=r,r,r,r"))]

74117

- "TARGET_64BIT"

74118

+ "TARGET_64BIT && !BYTES_BIG_ENDIAN"

74119

"@

74120

rldcl. %3,%1,%2,48

74121

rldicl. %3,%1,%H2,48

74122

@@ -6662,6 +7248,23 @@

74123

[(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

74124

(set_attr "length" "4,4,8,8")])

74125

74126

+(define_insn "*rotldi3_internal11be"

74127

+ [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")

74128

+ (compare:CC (zero_extend:DI

74129

+ (subreg:HI

74130

+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")

74131

+ (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 6))

74132

+ (const_int 0)))

74133

+ (clobber (match_scratch:DI 3 "=r,r,r,r"))]

74134

+ "TARGET_64BIT && BYTES_BIG_ENDIAN"

74135

+ "@

74136

+ rldcl. %3,%1,%2,48

74137

+ rldicl. %3,%1,%H2,48

74138

+ #

74139

+ #"

74140

+ [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

74141

+ (set_attr "length" "4,4,8,8")])

74142

+

74143

(define_split

74144

[(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")

74145

(compare:CC (zero_extend:DI

74146

@@ -6670,7 +7273,7 @@

74147

(match_operand:DI 2 "reg_or_cint_operand" "")) 0))

74148

(const_int 0)))

74149

(clobber (match_scratch:DI 3 ""))]

74150

- "TARGET_POWERPC64 && reload_completed"

74151

+ "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"

74152

[(set (match_dup 3)

74153

(zero_extend:DI (subreg:HI

74154

(rotate:DI (match_dup 1)

74155

@@ -6680,7 +7283,25 @@

74156

(const_int 0)))]

74157

"")

74158

74159

-(define_insn "*rotldi3_internal12"

74160

+(define_split

74161

+ [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")

74162

+ (compare:CC (zero_extend:DI

74163

+ (subreg:HI

74164

+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")

74165

+ (match_operand:DI 2 "reg_or_cint_operand" "")) 6))

74166

+ (const_int 0)))

74167

+ (clobber (match_scratch:DI 3 ""))]

74168

+ "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"

74169

+ [(set (match_dup 3)

74170

+ (zero_extend:DI (subreg:HI

74171

+ (rotate:DI (match_dup 1)

74172

+ (match_dup 2)) 6)))

74173

+ (set (match_dup 0)

74174

+ (compare:CC (match_dup 3)

74175

+ (const_int 0)))]

74176

+ "")

74177

+

74178

+(define_insn "*rotldi3_internal12le"

74179

[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")

74180

(compare:CC (zero_extend:DI

74181

(subreg:HI

74182

@@ -6689,7 +7310,7 @@

74183

(const_int 0)))

74184

(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")

74185

(zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]

74186

- "TARGET_64BIT"

74187

+ "TARGET_64BIT && !BYTES_BIG_ENDIAN"

74188

"@

74189

rldcl. %0,%1,%2,48

74190

rldicl. %0,%1,%H2,48

74191

@@ -6698,6 +7319,24 @@

74192

[(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

74193

(set_attr "length" "4,4,8,8")])

74194

74195

+(define_insn "*rotldi3_internal12be"

74196

+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")

74197

+ (compare:CC (zero_extend:DI

74198

+ (subreg:HI

74199

+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")

74200

+ (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 6))

74201

+ (const_int 0)))

74202

+ (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")

74203

+ (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]

74204

+ "TARGET_64BIT && BYTES_BIG_ENDIAN"

74205

+ "@

74206

+ rldcl. %0,%1,%2,48

74207

+ rldicl. %0,%1,%H2,48

74208

+ #

74209

+ #"

74210

+ [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

74211

+ (set_attr "length" "4,4,8,8")])

74212

+

74213

(define_split

74214

[(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")

74215

(compare:CC (zero_extend:DI

74216

@@ -6707,7 +7346,7 @@

74217

(const_int 0)))

74218

(set (match_operand:DI 0 "gpc_reg_operand" "")

74219

(zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]

74220

- "TARGET_POWERPC64 && reload_completed"

74221

+ "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"

74222

[(set (match_dup 0)

74223

(zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))

74224

(set (match_dup 3)

74225

@@ -6715,19 +7354,48 @@

74226

(const_int 0)))]

74227

"")

74228

74229

-(define_insn "*rotldi3_internal13"

74230

+(define_split

74231

+ [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")

74232

+ (compare:CC (zero_extend:DI

74233

+ (subreg:HI

74234

+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")

74235

+ (match_operand:DI 2 "reg_or_cint_operand" "")) 6))

74236

+ (const_int 0)))

74237

+ (set (match_operand:DI 0 "gpc_reg_operand" "")

74238

+ (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]

74239

+ "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"

74240

+ [(set (match_dup 0)

74241

+ (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))

74242

+ (set (match_dup 3)

74243

+ (compare:CC (match_dup 0)

74244

+ (const_int 0)))]

74245

+ "")

74246

+

74247

+(define_insn "*rotldi3_internal13le"

74248

[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")

74249

(zero_extend:DI

74250

(subreg:SI

74251

(rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")

74252

(match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]

74253

- "TARGET_POWERPC64"

74254

+ "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"

74255

"@

74256

rldcl %0,%1,%2,32

74257

rldicl %0,%1,%H2,32"

74258

[(set_attr "type" "var_shift_rotate,integer")])

74259

74260

-(define_insn "*rotldi3_internal14"

74261

+(define_insn "*rotldi3_internal13be"

74262

+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")

74263

+ (zero_extend:DI

74264

+ (subreg:SI

74265

+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")

74266

+ (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 4)))]

74267

+ "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"

74268

+ "@

74269

+ rldcl %0,%1,%2,32

74270

+ rldicl %0,%1,%H2,32"

74271

+ [(set_attr "type" "var_shift_rotate,integer")])

74272

+

74273

+(define_insn "*rotldi3_internal14le"

74274

[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")

74275

(compare:CC (zero_extend:DI

74276

(subreg:SI

74277

@@ -6735,7 +7403,7 @@

74278

(match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))

74279

(const_int 0)))

74280

(clobber (match_scratch:DI 3 "=r,r,r,r"))]

74281

- "TARGET_64BIT"

74282

+ "TARGET_64BIT && !BYTES_BIG_ENDIAN"

74283

"@

74284

rldcl. %3,%1,%2,32

74285

rldicl. %3,%1,%H2,32

74286

@@ -6744,6 +7412,23 @@

74287

[(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

74288

(set_attr "length" "4,4,8,8")])

74289

74290

+(define_insn "*rotldi3_internal14be"

74291

+ [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")

74292

+ (compare:CC (zero_extend:DI

74293

+ (subreg:SI

74294

+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")

74295

+ (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 4))

74296

+ (const_int 0)))

74297

+ (clobber (match_scratch:DI 3 "=r,r,r,r"))]

74298

+ "TARGET_64BIT && BYTES_BIG_ENDIAN"

74299

+ "@

74300

+ rldcl. %3,%1,%2,32

74301

+ rldicl. %3,%1,%H2,32

74302

+ #

74303

+ #"

74304

+ [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

74305

+ (set_attr "length" "4,4,8,8")])

74306

+

74307

(define_split

74308

[(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")

74309

(compare:CC (zero_extend:DI

74310

@@ -6752,7 +7437,7 @@

74311

(match_operand:DI 2 "reg_or_cint_operand" "")) 0))

74312

(const_int 0)))

74313

(clobber (match_scratch:DI 3 ""))]

74314

- "TARGET_POWERPC64 && reload_completed"

74315

+ "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"

74316

[(set (match_dup 3)

74317

(zero_extend:DI (subreg:SI

74318

(rotate:DI (match_dup 1)

74319

@@ -6762,7 +7447,25 @@

74320

(const_int 0)))]

74321

"")

74322

74323

-(define_insn "*rotldi3_internal15"

74324

+(define_split

74325

+ [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")

74326

+ (compare:CC (zero_extend:DI

74327

+ (subreg:SI

74328

+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")

74329

+ (match_operand:DI 2 "reg_or_cint_operand" "")) 4))

74330

+ (const_int 0)))

74331

+ (clobber (match_scratch:DI 3 ""))]

74332

+ "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"

74333

+ [(set (match_dup 3)

74334

+ (zero_extend:DI (subreg:SI

74335

+ (rotate:DI (match_dup 1)

74336

+ (match_dup 2)) 4)))

74337

+ (set (match_dup 0)

74338

+ (compare:CC (match_dup 3)

74339

+ (const_int 0)))]

74340

+ "")

74341

+

74342

+(define_insn "*rotldi3_internal15le"

74343

[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")

74344

(compare:CC (zero_extend:DI

74345

(subreg:SI

74346

@@ -6771,7 +7474,7 @@

74347

(const_int 0)))

74348

(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")

74349

(zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]

74350

- "TARGET_64BIT"

74351

+ "TARGET_64BIT && !BYTES_BIG_ENDIAN"

74352

"@

74353

rldcl. %0,%1,%2,32

74354

rldicl. %0,%1,%H2,32

74355

@@ -6780,6 +7483,24 @@

74356

[(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

74357

(set_attr "length" "4,4,8,8")])

74358

74359

+(define_insn "*rotldi3_internal15be"

74360

+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")

74361

+ (compare:CC (zero_extend:DI

74362

+ (subreg:SI

74363

+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")

74364

+ (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 4))

74365

+ (const_int 0)))

74366

+ (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")

74367

+ (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]

74368

+ "TARGET_64BIT && BYTES_BIG_ENDIAN"

74369

+ "@

74370

+ rldcl. %0,%1,%2,32

74371

+ rldicl. %0,%1,%H2,32

74372

+ #

74373

+ #"

74374

+ [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")

74375

+ (set_attr "length" "4,4,8,8")])

74376

+

74377

(define_split

74378

[(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")

74379

(compare:CC (zero_extend:DI

74380

@@ -6789,7 +7510,7 @@

74381

(const_int 0)))

74382

(set (match_operand:DI 0 "gpc_reg_operand" "")

74383

(zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]

74384

- "TARGET_POWERPC64 && reload_completed"

74385

+ "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"

74386

[(set (match_dup 0)

74387

(zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))

74388

(set (match_dup 3)

74389

@@ -6797,6 +7518,23 @@

74390

(const_int 0)))]

74391

"")

74392

74393

+(define_split

74394

+ [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")

74395

+ (compare:CC (zero_extend:DI

74396

+ (subreg:SI

74397

+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")

74398

+ (match_operand:DI 2 "reg_or_cint_operand" "")) 4))

74399

+ (const_int 0)))

74400

+ (set (match_operand:DI 0 "gpc_reg_operand" "")

74401

+ (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]

74402

+ "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"

74403

+ [(set (match_dup 0)

74404

+ (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))

74405

+ (set (match_dup 3)

74406

+ (compare:CC (match_dup 0)

74407

+ (const_int 0)))]

74408

+ "")

74409

+

74410

(define_expand "ashldi3"

74411

[(set (match_operand:DI 0 "gpc_reg_operand" "")

74412

(ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")

74413

@@ -7195,10 +7933,19 @@

74414

[(parallel

74415

[(set (match_operand:DI 0 "gpc_reg_operand" "")

74416

(and:DI (match_operand:DI 1 "gpc_reg_operand" "")

74417

- (match_operand:DI 2 "and64_2_operand" "")))

74418

+ (match_operand:DI 2 "reg_or_cint_operand" "")))

74419

(clobber (match_scratch:CC 3 ""))])]

74420

- "TARGET_POWERPC64"

74421

- "")

74422

+ ""

74423

+{

74424

+ if (!TARGET_POWERPC64)

74425

+ {

74426

+ rtx cc = gen_rtx_SCRATCH (CCmode);

74427

+ rs6000_split_logical (operands, AND, false, false, false, cc);

74428

+ DONE;

74429

+ }

74430

+ else if (!and64_2_operand (operands[2], DImode))

74431

+ operands[2] = force_reg (DImode, operands[2]);

74432

+})

74433

74434

(define_insn "anddi3_mc"

74435

[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")

74436

@@ -7379,12 +8126,18 @@

74437

(define_expand "iordi3"

74438

[(set (match_operand:DI 0 "gpc_reg_operand" "")

74439

(ior:DI (match_operand:DI 1 "gpc_reg_operand" "")

74440

- (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]

74441

- "TARGET_POWERPC64"

74442

- "

74443

+ (match_operand:DI 2 "reg_or_cint_operand" "")))]

74444

+ ""

74445

{

74446

- if (non_logical_cint_operand (operands[2], DImode))

74447

+ if (!TARGET_POWERPC64)

74448

{

74449

+ rs6000_split_logical (operands, IOR, false, false, false, NULL_RTX);

74450

+ DONE;

74451

+ }

74452

+ else if (!reg_or_logical_cint_operand (operands[2], DImode))

74453

+ operands[2] = force_reg (DImode, operands[2]);

74454

+ else if (non_logical_cint_operand (operands[2], DImode))

74455

+ {

74456

HOST_WIDE_INT value;

74457

rtx tmp = ((!can_create_pseudo_p ()

74458

|| rtx_equal_p (operands[0], operands[1]))

74459

@@ -7408,15 +8161,21 @@

74460

emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));

74461

DONE;

74462

}

74463

-}")

74464

+})

74465

74466

(define_expand "xordi3"

74467

[(set (match_operand:DI 0 "gpc_reg_operand" "")

74468

(xor:DI (match_operand:DI 1 "gpc_reg_operand" "")

74469

- (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]

74470

- "TARGET_POWERPC64"

74471

- "

74472

+ (match_operand:DI 2 "reg_or_cint_operand" "")))]

74473

+ ""

74474

{

74475

+ if (!TARGET_POWERPC64)

74476

+ {

74477

+ rs6000_split_logical (operands, XOR, false, false, false, NULL_RTX);

74478

+ DONE;

74479

+ }

74480

+ else if (!reg_or_logical_cint_operand (operands[2], DImode))

74481

+ operands[2] = force_reg (DImode, operands[2]);

74482

if (non_logical_cint_operand (operands[2], DImode))

74483

{

74484

HOST_WIDE_INT value;

74485

@@ -7442,7 +8201,7 @@

74486

emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));

74487

DONE;

74488

}

74489

-}")

74490

+})

74491

74492

(define_insn "*booldi3_internal1"

74493

[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")

74494

@@ -7678,7 +8437,385 @@

74495

(compare:CC (match_dup 0)

74496

(const_int 0)))]

74497

"")

74498

+

74499

+;; Eqv operation.

74500

+(define_insn "*eqv<mode>3"

74501

+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")

74502

+ (not:GPR

74503

+ (xor:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")

74504

+ (match_operand:GPR 2 "gpc_reg_operand" "r"))))]

74505

+ ""

74506

+ "eqv %0,%1,%2"

74507

+ [(set_attr "type" "integer")

74508

+ (set_attr "length" "4")])

74509

+

74510

74511

+;; 128-bit logical operations expanders

74512

+

74513

+(define_expand "and<mode>3"

74514

+ [(parallel [(set (match_operand:BOOL_128 0 "vlogical_operand" "")

74515

+ (and:BOOL_128

74516

+ (match_operand:BOOL_128 1 "vlogical_operand" "")

74517

+ (match_operand:BOOL_128 2 "vlogical_operand" "")))

74518

+ (clobber (match_scratch:CC 3 ""))])]

74519

+ ""

74520

+ "")

74521

+

74522

+(define_expand "ior<mode>3"

74523

+ [(set (match_operand:BOOL_128 0 "vlogical_operand" "")

74524

+ (ior:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")

74525

+ (match_operand:BOOL_128 2 "vlogical_operand" "")))]

74526

+ ""

74527

+ "")

74528

+

74529

+(define_expand "xor<mode>3"

74530

+ [(set (match_operand:BOOL_128 0 "vlogical_operand" "")

74531

+ (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")

74532

+ (match_operand:BOOL_128 2 "vlogical_operand" "")))]

74533

+ ""

74534

+ "")

74535

+

74536

+(define_expand "one_cmpl<mode>2"

74537

+ [(set (match_operand:BOOL_128 0 "vlogical_operand" "")

74538

+ (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")))]

74539

+ ""

74540

+ "")

74541

+

74542

+(define_expand "nor<mode>3"

74543

+ [(set (match_operand:BOOL_128 0 "vlogical_operand" "")

74544

+ (and:BOOL_128

74545

+ (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" ""))

74546

+ (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]

74547

+ ""

74548

+ "")

74549

+

74550

+(define_expand "andc<mode>3"

74551

+ [(set (match_operand:BOOL_128 0 "vlogical_operand" "")

74552

+ (and:BOOL_128

74553

+ (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))

74554

+ (match_operand:BOOL_128 1 "vlogical_operand" "")))]

74555

+ ""

74556

+ "")

74557

+

74558

+;; Power8 vector logical instructions.

74559

+(define_expand "eqv<mode>3"

74560

+ [(set (match_operand:BOOL_128 0 "vlogical_operand" "")

74561

+ (not:BOOL_128

74562

+ (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")

74563

+ (match_operand:BOOL_128 2 "vlogical_operand" ""))))]

74564

+ "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"

74565

+ "")

74566

+

74567

+;; Rewrite nand into canonical form

74568

+(define_expand "nand<mode>3"

74569

+ [(set (match_operand:BOOL_128 0 "vlogical_operand" "")

74570

+ (ior:BOOL_128

74571

+ (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" ""))

74572

+ (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]

74573

+ "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"

74574

+ "")

74575

+

74576

+;; The canonical form is to have the negated element first, so we need to

74577

+;; reverse arguments.

74578

+(define_expand "orc<mode>3"

74579

+ [(set (match_operand:BOOL_128 0 "vlogical_operand" "")

74580

+ (ior:BOOL_128

74581

+ (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))

74582

+ (match_operand:BOOL_128 1 "vlogical_operand" "")))]

74583

+ "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"

74584

+ "")

74585

+

74586

+;; 128-bit logical operations insns and split operations

74587

+(define_insn_and_split "*and<mode>3_internal"

74588

+ [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")

74589

+ (and:BOOL_128

74590

+ (match_operand:BOOL_128 1 "vlogical_operand" "%<BOOL_REGS_OP1>")

74591

+ (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>")))

74592

+ (clobber (match_scratch:CC 3 "<BOOL_REGS_AND_CR0>"))]

74593

+ ""

74594

+{

74595

+ if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))

74596

+ return "xxland %x0,%x1,%x2";

74597

+

74598

+ if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))

74599

+ return "vand %0,%1,%2";

74600

+

74601

+ return "#";

74602

+}

74603

+ "reload_completed && int_reg_operand (operands[0], <MODE>mode)"

74604

+ [(const_int 0)]

74605

+{

74606

+ rs6000_split_logical (operands, AND, false, false, false, operands[3]);

74607

+ DONE;

74608

+}

74609

+ [(set (attr "type")

74610

+ (if_then_else

74611

+ (match_test "vsx_register_operand (operands[0], <MODE>mode)")

74612

+ (const_string "vecsimple")

74613

+ (const_string "integer")))

74614

+ (set (attr "length")

74615

+ (if_then_else

74616

+ (match_test "vsx_register_operand (operands[0], <MODE>mode)")

74617

+ (const_string "4")

74618

+ (if_then_else

74619

+ (match_test "TARGET_POWERPC64")

74620

+ (const_string "8")

74621

+ (const_string "16"))))])

74622

+

74623

+;; 128-bit IOR/XOR

74624

+(define_insn_and_split "*bool<mode>3_internal"

74625

+ [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")

74626

+ (match_operator:BOOL_128 3 "boolean_or_operator"

74627

+ [(match_operand:BOOL_128 1 "vlogical_operand" "%<BOOL_REGS_OP1>")

74628

+ (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>")]))]

74629

+ ""

74630

+{

74631

+ if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))

74632

+ return "xxl%q3 %x0,%x1,%x2";

74633

+

74634

+ if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))

74635

+ return "v%q3 %0,%1,%2";

74636

+

74637

+ return "#";

74638

+}

74639

+ "reload_completed && int_reg_operand (operands[0], <MODE>mode)"

74640

+ [(const_int 0)]

74641

+{

74642

+ rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, false,

74643

+ NULL_RTX);

74644

+ DONE;

74645

+}

74646

+ [(set (attr "type")

74647

+ (if_then_else

74648

+ (match_test "vsx_register_operand (operands[0], <MODE>mode)")

74649

+ (const_string "vecsimple")

74650

+ (const_string "integer")))

74651

+ (set (attr "length")

74652

+ (if_then_else

74653

+ (match_test "vsx_register_operand (operands[0], <MODE>mode)")

74654

+ (const_string "4")

74655

+ (if_then_else

74656

+ (match_test "TARGET_POWERPC64")

74657

+ (const_string "8")

74658

+ (const_string "16"))))])

74659

+

74660

+;; 128-bit ANDC/ORC

74661

+(define_insn_and_split "*boolc<mode>3_internal1"

74662

+ [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")

74663

+ (match_operator:BOOL_128 3 "boolean_operator"

74664

+ [(not:BOOL_128

74665

+ (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP1>"))

74666

+ (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP2>")]))]

74667

+ "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)"

74668

+{

74669

+ if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))

74670

+ return "xxl%q3 %x0,%x1,%x2";

74671

+

74672

+ if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))

74673

+ return "v%q3 %0,%1,%2";

74674

+

74675

+ return "#";

74676

+}

74677

+ "(TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND))

74678

+ && reload_completed && int_reg_operand (operands[0], <MODE>mode)"

74679

+ [(const_int 0)]

74680

+{

74681

+ rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false,

74682

+ NULL_RTX);

74683

+ DONE;

74684

+}

74685

+ [(set (attr "type")

74686

+ (if_then_else

74687

+ (match_test "vsx_register_operand (operands[0], <MODE>mode)")

74688

+ (const_string "vecsimple")

74689

+ (const_string "integer")))

74690

+ (set (attr "length")

74691

+ (if_then_else

74692

+ (match_test "vsx_register_operand (operands[0], <MODE>mode)")

74693

+ (const_string "4")

74694

+ (if_then_else

74695

+ (match_test "TARGET_POWERPC64")

74696

+ (const_string "8")

74697

+ (const_string "16"))))])

74698

+

74699

+(define_insn_and_split "*boolc<mode>3_internal2"

74700

+ [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")

74701

+ (match_operator:TI2 3 "boolean_operator"

74702

+ [(not:TI2

74703

+ (match_operand:TI2 1 "int_reg_operand" "r,0,r"))

74704

+ (match_operand:TI2 2 "int_reg_operand" "r,r,0")]))]

74705

+ "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"

74706

+ "#"

74707

+ "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"

74708

+ [(const_int 0)]

74709

+{

74710

+ rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false,

74711

+ NULL_RTX);

74712

+ DONE;

74713

+}

74714

+ [(set_attr "type" "integer")

74715

+ (set (attr "length")

74716

+ (if_then_else

74717

+ (match_test "TARGET_POWERPC64")

74718

+ (const_string "8")

74719

+ (const_string "16")))])

74720

+

74721

+;; 128-bit NAND/NOR

74722

+(define_insn_and_split "*boolcc<mode>3_internal1"

74723

+ [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")

74724

+ (match_operator:BOOL_128 3 "boolean_operator"

74725

+ [(not:BOOL_128

74726

+ (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>"))

74727

+ (not:BOOL_128

74728

+ (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))]))]

74729

+ "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)"

74730

+{

74731

+ if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))

74732

+ return "xxl%q3 %x0,%x1,%x2";

74733

+

74734

+ if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))

74735

+ return "v%q3 %0,%1,%2";

74736

+

74737

+ return "#";

74738

+}

74739

+ "(TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND))

74740

+ && reload_completed && int_reg_operand (operands[0], <MODE>mode)"

74741

+ [(const_int 0)]

74742

+{

74743

+ rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true,

74744

+ NULL_RTX);

74745

+ DONE;

74746

+}

74747

+ [(set (attr "type")

74748

+ (if_then_else

74749

+ (match_test "vsx_register_operand (operands[0], <MODE>mode)")

74750

+ (const_string "vecsimple")

74751

+ (const_string "integer")))

74752

+ (set (attr "length")

74753

+ (if_then_else

74754

+ (match_test "vsx_register_operand (operands[0], <MODE>mode)")

74755

+ (const_string "4")

74756

+ (if_then_else

74757

+ (match_test "TARGET_POWERPC64")

74758

+ (const_string "8")

74759

+ (const_string "16"))))])

74760

+

74761

+(define_insn_and_split "*boolcc<mode>3_internal2"

74762

+ [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")

74763

+ (match_operator:TI2 3 "boolean_operator"

74764

+ [(not:TI2

74765

+ (match_operand:TI2 1 "int_reg_operand" "r,0,r"))

74766

+ (not:TI2

74767

+ (match_operand:TI2 2 "int_reg_operand" "r,r,0"))]))]

74768

+ "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"

74769

+ "#"

74770

+ "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"

74771

+ [(const_int 0)]

74772

+{

74773

+ rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true,

74774

+ NULL_RTX);

74775

+ DONE;

74776

+}

74777

+ [(set_attr "type" "integer")

74778

+ (set (attr "length")

74779

+ (if_then_else

74780

+ (match_test "TARGET_POWERPC64")

74781

+ (const_string "8")

74782

+ (const_string "16")))])

74783

+

74784

+

74785

+;; 128-bit EQV

74786

+(define_insn_and_split "*eqv<mode>3_internal1"

74787

+ [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")

74788

+ (not:BOOL_128

74789

+ (xor:BOOL_128

74790

+ (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>")

74791

+ (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))))]

74792

+ "TARGET_P8_VECTOR"

74793

+{

74794

+ if (vsx_register_operand (operands[0], <MODE>mode))

74795

+ return "xxleqv %x0,%x1,%x2";

74796

+

74797

+ return "#";

74798

+}

74799

+ "TARGET_P8_VECTOR && reload_completed

74800

+ && int_reg_operand (operands[0], <MODE>mode)"

74801

+ [(const_int 0)]

74802

+{

74803

+ rs6000_split_logical (operands, XOR, true, false, false, NULL_RTX);

74804

+ DONE;

74805

+}

74806

+ [(set (attr "type")

74807

+ (if_then_else

74808

+ (match_test "vsx_register_operand (operands[0], <MODE>mode)")

74809

+ (const_string "vecsimple")

74810

+ (const_string "integer")))

74811

+ (set (attr "length")

74812

+ (if_then_else

74813

+ (match_test "vsx_register_operand (operands[0], <MODE>mode)")

74814

+ (const_string "4")

74815

+ (if_then_else

74816

+ (match_test "TARGET_POWERPC64")

74817

+ (const_string "8")

74818

+ (const_string "16"))))])

74819

+

74820

+(define_insn_and_split "*eqv<mode>3_internal2"

74821

+ [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")

74822

+ (not:TI2

74823

+ (xor:TI2

74824

+ (match_operand:TI2 1 "int_reg_operand" "r,0,r")

74825

+ (match_operand:TI2 2 "int_reg_operand" "r,r,0"))))]

74826

+ "!TARGET_P8_VECTOR"

74827

+ "#"

74828

+ "reload_completed && !TARGET_P8_VECTOR"

74829

+ [(const_int 0)]

74830

+{

74831

+ rs6000_split_logical (operands, XOR, true, false, false, NULL_RTX);

74832

+ DONE;

74833

+}

74834

+ [(set_attr "type" "integer")

74835

+ (set (attr "length")

74836

+ (if_then_else

74837

+ (match_test "TARGET_POWERPC64")

74838

+ (const_string "8")

74839

+ (const_string "16")))])

74840

+

74841

+;; 128-bit one's complement

74842

+(define_insn_and_split "*one_cmpl<mode>3_internal"

74843

+ [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")

74844

+ (not:BOOL_128

74845

+ (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_UNARY>")))]

74846

+ ""

74847

+{

74848

+ if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))

74849

+ return "xxlnor %x0,%x1,%x1";

74850

+

74851

+ if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))

74852

+ return "vnor %0,%1,%1";

74853

+

74854

+ return "#";

74855

+}

74856

+ "reload_completed && int_reg_operand (operands[0], <MODE>mode)"

74857

+ [(const_int 0)]

74858

+{

74859

+ rs6000_split_logical (operands, NOT, false, false, false, NULL_RTX);

74860

+ DONE;

74861

+}

74862

+ [(set (attr "type")

74863

+ (if_then_else

74864

+ (match_test "vsx_register_operand (operands[0], <MODE>mode)")

74865

+ (const_string "vecsimple")

74866

+ (const_string "integer")))

74867

+ (set (attr "length")

74868

+ (if_then_else

74869

+ (match_test "vsx_register_operand (operands[0], <MODE>mode)")

74870

+ (const_string "4")

74871

+ (if_then_else

74872

+ (match_test "TARGET_POWERPC64")

74873

+ (const_string "8")

74874

+ (const_string "16"))))])

74875

+

74876

+

74877

;; Now define ways of moving data around.

74878

74879

;; Set up a register with a value from the GOT table

74880

@@ -7765,7 +8902,31 @@

74881

mt%0 %1

74882

mt%0 %1

74883

nop"

74884

- [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*")

74885

+ [(set_attr_alternative "type"

74886

+ [(const_string "*")

74887

+ (const_string "*")

74888

+ (if_then_else

74889

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

74890

+ (const_string "load_ux")

74891

+ (if_then_else

74892

+ (match_test "update_address_mem (operands[1], VOIDmode)")

74893

+ (const_string "load_u")

74894

+ (const_string "load")))

74895

+ (if_then_else

74896

+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")

74897

+ (const_string "store_ux")

74898

+ (if_then_else

74899

+ (match_test "update_address_mem (operands[0], VOIDmode)")

74900

+ (const_string "store_u")

74901

+ (const_string "store")))

74902

+ (const_string "*")

74903

+ (const_string "*")

74904

+ (const_string "*")

74905

+ (const_string "mfjmpr")

74906

+ (const_string "mtjmpr")

74907

+ (const_string "*")

74908

+ (const_string "*")])

74909

+

74910

(set_attr "length" "4,4,4,4,4,4,8,4,4,4,4")])

74911

74912

(define_insn "*movsi_internal1_single"

74913

@@ -7787,7 +8948,44 @@

74914

nop

74915

stfs%U0%X0 %1,%0

74916

lfs%U1%X1 %0,%1"

74917

- [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*,*,*")

74918

+ [(set_attr_alternative "type"

74919

+ [(const_string "*")

74920

+ (const_string "*")

74921

+ (if_then_else

74922

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

74923

+ (const_string "load_ux")

74924

+ (if_then_else

74925

+ (match_test "update_address_mem (operands[1], VOIDmode)")

74926

+ (const_string "load_u")

74927

+ (const_string "load")))

74928

+ (if_then_else

74929

+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")

74930

+ (const_string "store_ux")

74931

+ (if_then_else

74932

+ (match_test "update_address_mem (operands[0], VOIDmode)")

74933

+ (const_string "store_u")

74934

+ (const_string "store")))

74935

+ (const_string "*")

74936

+ (const_string "*")

74937

+ (const_string "*")

74938

+ (const_string "mfjmpr")

74939

+ (const_string "mtjmpr")

74940

+ (const_string "*")

74941

+ (const_string "*")

74942

+ (if_then_else

74943

+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")

74944

+ (const_string "fpstore_ux")

74945

+ (if_then_else

74946

+ (match_test "update_address_mem (operands[0], VOIDmode)")

74947

+ (const_string "fpstore_u")

74948

+ (const_string "fpstore")))

74949

+ (if_then_else

74950

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

74951

+ (const_string "fpload_ux")

74952

+ (if_then_else

74953

+ (match_test "update_address_mem (operands[1], VOIDmode)")

74954

+ (const_string "fpload_u")

74955

+ (const_string "fpload")))])

74956

(set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])

74957

74958

;; Split a load of a large constant into the appropriate two-insn

74959

@@ -7822,7 +9020,7 @@

74960

cmp<wd>i %2,%0,0

74961

mr. %0,%1

74962

#"

74963

- [(set_attr "type" "cmp,compare,cmp")

74964

+ [(set_attr "type" "cmp,fast_compare,cmp")

74965

(set_attr "length" "4,4,8")])

74966

74967

(define_split

74968

@@ -7850,7 +9048,26 @@

74969

mf%1 %0

74970

mt%0 %1

74971

nop"

74972

- [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")])

74973

+ [(set_attr_alternative "type"

74974

+ [(const_string "*")

74975

+ (if_then_else

74976

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

74977

+ (const_string "load_ux")

74978

+ (if_then_else

74979

+ (match_test "update_address_mem (operands[1], VOIDmode)")

74980

+ (const_string "load_u")

74981

+ (const_string "load")))

74982

+ (if_then_else

74983

+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")

74984

+ (const_string "store_ux")

74985

+ (if_then_else

74986

+ (match_test "update_address_mem (operands[0], VOIDmode)")

74987

+ (const_string "store_u")

74988

+ (const_string "store")))

74989

+ (const_string "*")

74990

+ (const_string "mfjmpr")

74991

+ (const_string "mtjmpr")

74992

+ (const_string "*")])])

74993

74994

(define_expand "mov<mode>"

74995

[(set (match_operand:INT 0 "general_operand" "")

74996

@@ -7871,7 +9088,26 @@

74997

mf%1 %0

74998

mt%0 %1

74999

nop"

75000

- [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")])

75001

+ [(set_attr_alternative "type"

75002

+ [(const_string "*")

75003

+ (if_then_else

75004

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

75005

+ (const_string "load_ux")

75006

+ (if_then_else

75007

+ (match_test "update_address_mem (operands[1], VOIDmode)")

75008

+ (const_string "load_u")

75009

+ (const_string "load")))

75010

+ (if_then_else

75011

+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")

75012

+ (const_string "store_ux")

75013

+ (if_then_else

75014

+ (match_test "update_address_mem (operands[0], VOIDmode)")

75015

+ (const_string "store_u")

75016

+ (const_string "store")))

75017

+ (const_string "*")

75018

+ (const_string "mfjmpr")

75019

+ (const_string "mtjmpr")

75020

+ (const_string "*")])])

75021

75022

;; Here is how to move condition codes around. When we store CC data in

75023

;; an integer register or memory, we store just the high-order 4 bits.

75024

@@ -7899,7 +9135,7 @@

75025

mf%1 %0

75026

mt%0 %1

75027

lwz%U1%X1 %0,%1

75028

- stw%U0%U1 %1,%0"

75029

+ stw%U0%X0 %1,%0"

75030

[(set (attr "type")

75031

(cond [(eq_attr "alternative" "0,3")

75032

(const_string "cr_logical")

75033

@@ -7912,9 +9148,23 @@

75034

(eq_attr "alternative" "9")

75035

(const_string "mtjmpr")

75036

(eq_attr "alternative" "10")

75037

- (const_string "load")

75038

+ (if_then_else

75039

+ (match_test "update_indexed_address_mem (operands[1],

75040

+ VOIDmode)")

75041

+ (const_string "load_ux")

75042

+ (if_then_else

75043

+ (match_test "update_address_mem (operands[1], VOIDmode)")

75044

+ (const_string "load_u")

75045

+ (const_string "load")))

75046

(eq_attr "alternative" "11")

75047

- (const_string "store")

75048

+ (if_then_else

75049

+ (match_test "update_indexed_address_mem (operands[0],

75050

+ VOIDmode)")

75051

+ (const_string "store_ux")

75052

+ (if_then_else

75053

+ (match_test "update_address_mem (operands[0], VOIDmode)")

75054

+ (const_string "store_u")

75055

+ (const_string "store")))

75056

(match_test "TARGET_MFCRF")

75057

(const_string "mfcrf")

75058

]

75059

@@ -7926,15 +9176,17 @@

75060

;; can produce floating-point values in fixed-point registers. Unless the

75061

;; value is a simple constant or already in memory, we deal with this by

75062

;; allocating memory and copying the value explicitly via that memory location.

75063

-(define_expand "movsf"

75064

- [(set (match_operand:SF 0 "nonimmediate_operand" "")

75065

- (match_operand:SF 1 "any_operand" ""))]

75066

- ""

75067

- "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")

75068

75069

+;; Move 32-bit binary/decimal floating point

75070

+(define_expand "mov<mode>"

75071

+ [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "")

75072

+ (match_operand:FMOVE32 1 "any_operand" ""))]

75073

+ "<fmove_ok>"

75074

+ "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")

75075

+

75076

(define_split

75077

- [(set (match_operand:SF 0 "gpc_reg_operand" "")

75078

- (match_operand:SF 1 "const_double_operand" ""))]

75079

+ [(set (match_operand:FMOVE32 0 "gpc_reg_operand" "")

75080

+ (match_operand:FMOVE32 1 "const_double_operand" ""))]

75081

"reload_completed

75082

&& ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)

75083

|| (GET_CODE (operands[0]) == SUBREG

75084

@@ -7947,10 +9199,10 @@

75085

REAL_VALUE_TYPE rv;

75086

75087

REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);

75088

- REAL_VALUE_TO_TARGET_SINGLE (rv, l);

75089

+ <real_value_to_target> (rv, l);

75090

75091

if (! TARGET_POWERPC64)

75092

- operands[2] = operand_subword (operands[0], 0, 0, SFmode);

75093

+ operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);

75094

else

75095

operands[2] = gen_lowpart (SImode, operands[0]);

75096

75097

@@ -7957,11 +9209,11 @@

75098

operands[3] = gen_int_mode (l, SImode);

75099

}")

75100

75101

-(define_insn "*movsf_hardfloat"

75102

- [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,!r,*h,!r,!r")

75103

- (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,h,0,G,Fn"))]

75104

- "(gpc_reg_operand (operands[0], SFmode)

75105

- || gpc_reg_operand (operands[1], SFmode))

75106

+(define_insn "mov<mode>_hardfloat"

75107

+ [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=!r,!r,m,f,wa,wa,<f32_lr>,<f32_sm>,wu,Z,?<f32_dm>,?r,*c*l,!r,*h,!r,!r")

75108

+ (match_operand:FMOVE32 1 "input_operand" "r,m,r,f,wa,j,<f32_lm>,<f32_sr>,Z,wu,r,<f32_dm>,r,h,0,G,Fn"))]

75109

+ "(gpc_reg_operand (operands[0], <MODE>mode)

75110

+ || gpc_reg_operand (operands[1], <MODE>mode))

75111

&& (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"

75112

"@

75113

mr %0,%1

75114

@@ -7968,21 +9220,68 @@

75115

lwz%U1%X1 %0,%1

75116

stw%U0%X0 %1,%0

75117

fmr %0,%1

75118

- lfs%U1%X1 %0,%1

75119

- stfs%U0%X0 %1,%0

75120

+ xxlor %x0,%x1,%x1

75121

+ xxlxor %x0,%x0,%x0

75122

+ <f32_li>

75123

+ <f32_si>

75124

+ <f32_lv>

75125

+ <f32_sv>

75126

+ mtvsrwz %x0,%1

75127

+ mfvsrwz %0,%x1

75128

mt%0 %1

75129

mf%1 %0

75130

nop

75131

#

75132

#"

75133

- [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*")

75134

- (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8")])

75135

+ [(set_attr_alternative "type"

75136

+ [(const_string "*")

75137

+ (if_then_else

75138

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

75139

+ (const_string "load_ux")

75140

+ (if_then_else

75141

+ (match_test "update_address_mem (operands[1], VOIDmode)")

75142

+ (const_string "load_u")

75143

+ (const_string "load")))

75144

+ (if_then_else

75145

+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")

75146

+ (const_string "store_ux")

75147

+ (if_then_else

75148

+ (match_test "update_address_mem (operands[0], VOIDmode)")

75149

+ (const_string "store_u")

75150

+ (const_string "store")))

75151

+ (const_string "fp")

75152

+ (const_string "vecsimple")

75153

+ (const_string "vecsimple")

75154

+ (if_then_else

75155

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

75156

+ (const_string "fpload_ux")

75157

+ (if_then_else

75158

+ (match_test "update_address_mem (operands[1], VOIDmode)")

75159

+ (const_string "fpload_u")

75160

+ (const_string "fpload")))

75161

+ (if_then_else

75162

+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")

75163

+ (const_string "fpstore_ux")

75164

+ (if_then_else

75165

+ (match_test "update_address_mem (operands[0], VOIDmode)")

75166

+ (const_string "fpstore_u")

75167

+ (const_string "fpstore")))

75168

+ (const_string "fpload")

75169

+ (const_string "fpstore")

75170

+ (const_string "mftgpr")

75171

+ (const_string "mffgpr")

75172

+ (const_string "mtjmpr")

75173

+ (const_string "mfjmpr")

75174

+ (const_string "*")

75175

+ (const_string "*")

75176

+ (const_string "*")])

75177

+ (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8")])

75178

75179

-(define_insn "*movsf_softfloat"

75180

- [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,*h")

75181

- (match_operand:SF 1 "input_operand" "r,r,h,m,r,I,L,G,Fn,0"))]

75182

- "(gpc_reg_operand (operands[0], SFmode)

75183

- || gpc_reg_operand (operands[1], SFmode))

75184

+(define_insn "*mov<mode>_softfloat"

75185

+ [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,*h")

75186

+ (match_operand:FMOVE32 1 "input_operand" "r,r,h,m,r,I,L,G,Fn,0"))]

75187

+ "(gpc_reg_operand (operands[0], <MODE>mode)

75188

+ || gpc_reg_operand (operands[1], <MODE>mode))

75189

&& (TARGET_SOFT_FLOAT || !TARGET_FPRS)"

75190

"@

75191

mr %0,%1

75192

@@ -7995,19 +9294,42 @@

75193

#

75194

#

75195

nop"

75196

- [(set_attr "type" "*,mtjmpr,mfjmpr,load,store,*,*,*,*,*")

75197

+ [(set_attr_alternative "type"

75198

+ [(const_string "*")

75199

+ (const_string "mtjmpr")

75200

+ (const_string "mfjmpr")

75201

+ (if_then_else

75202

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

75203

+ (const_string "load_ux")

75204

+ (if_then_else

75205

+ (match_test "update_address_mem (operands[1], VOIDmode)")

75206

+ (const_string "load_u")

75207

+ (const_string "load")))

75208

+ (if_then_else

75209

+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")

75210

+ (const_string "store_ux")

75211

+ (if_then_else

75212

+ (match_test "update_address_mem (operands[0], VOIDmode)")

75213

+ (const_string "store_u")

75214

+ (const_string "store")))

75215

+ (const_string "*")

75216

+ (const_string "*")

75217

+ (const_string "*")

75218

+ (const_string "*")

75219

+ (const_string "*")])

75220

(set_attr "length" "4,4,4,4,4,4,4,4,8,4")])

75221

75222

75223

-(define_expand "movdf"

75224

- [(set (match_operand:DF 0 "nonimmediate_operand" "")

75225

- (match_operand:DF 1 "any_operand" ""))]

75226

+;; Move 64-bit binary/decimal floating point

75227

+(define_expand "mov<mode>"

75228

+ [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "")

75229

+ (match_operand:FMOVE64 1 "any_operand" ""))]

75230

""

75231

- "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")

75232

+ "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")

75233

75234

(define_split

75235

- [(set (match_operand:DF 0 "gpc_reg_operand" "")

75236

- (match_operand:DF 1 "const_int_operand" ""))]

75237

+ [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")

75238

+ (match_operand:FMOVE64 1 "const_int_operand" ""))]

75239

"! TARGET_POWERPC64 && reload_completed

75240

&& ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)

75241

|| (GET_CODE (operands[0]) == SUBREG

75242

@@ -8020,8 +9342,8 @@

75243

int endian = (WORDS_BIG_ENDIAN == 0);

75244

HOST_WIDE_INT value = INTVAL (operands[1]);

75245

75246

- operands[2] = operand_subword (operands[0], endian, 0, DFmode);

75247

- operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);

75248

+ operands[2] = operand_subword (operands[0], endian, 0, <MODE>mode);

75249

+ operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);

75250

#if HOST_BITS_PER_WIDE_INT == 32

75251

operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;

75252

#else

75253

@@ -8031,8 +9353,8 @@

75254

}")

75255

75256

(define_split

75257

- [(set (match_operand:DF 0 "gpc_reg_operand" "")

75258

- (match_operand:DF 1 "const_double_operand" ""))]

75259

+ [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")

75260

+ (match_operand:FMOVE64 1 "const_double_operand" ""))]

75261

"! TARGET_POWERPC64 && reload_completed

75262

&& ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)

75263

|| (GET_CODE (operands[0]) == SUBREG

75264

@@ -8047,17 +9369,17 @@

75265

REAL_VALUE_TYPE rv;

75266

75267

REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);

75268

- REAL_VALUE_TO_TARGET_DOUBLE (rv, l);

75269

+ <real_value_to_target> (rv, l);

75270

75271

- operands[2] = operand_subword (operands[0], endian, 0, DFmode);

75272

- operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);

75273

+ operands[2] = operand_subword (operands[0], endian, 0, <MODE>mode);

75274

+ operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);

75275

operands[4] = gen_int_mode (l[endian], SImode);

75276

operands[5] = gen_int_mode (l[1 - endian], SImode);

75277

}")

75278

75279

(define_split

75280

- [(set (match_operand:DF 0 "gpc_reg_operand" "")

75281

- (match_operand:DF 1 "const_double_operand" ""))]

75282

+ [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")

75283

+ (match_operand:FMOVE64 1 "const_double_operand" ""))]

75284

"TARGET_POWERPC64 && reload_completed

75285

&& ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)

75286

|| (GET_CODE (operands[0]) == SUBREG

75287

@@ -8074,7 +9396,7 @@

75288

#endif

75289

75290

REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);

75291

- REAL_VALUE_TO_TARGET_DOUBLE (rv, l);

75292

+ <real_value_to_target> (rv, l);

75293

75294

operands[2] = gen_lowpart (DImode, operands[0]);

75295

/* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */

75296

@@ -8099,22 +9421,19 @@

75297

;; since the D-form version of the memory instructions does not need a GPR for

75298

;; reloading.

75299

75300

-(define_insn "*movdf_hardfloat32"

75301

- [(set (match_operand:DF 0 "nonimmediate_operand" "=m,d,d,ws,?wa,Z,?Z,ws,?wa,wa,Y,r,!r,!r,!r,!r")

75302

- (match_operand:DF 1 "input_operand" "d,m,d,Z,Z,ws,wa,ws,wa,j,r,Y,r,G,H,F"))]

75303

+(define_insn "*mov<mode>_hardfloat32"

75304

+ [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,wv,Z,wa,wa,Y,r,!r,!r,!r,!r")

75305

+ (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,wv,wa,j,r,Y,r,G,H,F"))]

75306

"! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT

75307

- && (gpc_reg_operand (operands[0], DFmode)

75308

- || gpc_reg_operand (operands[1], DFmode))"

75309

+ && (gpc_reg_operand (operands[0], <MODE>mode)

75310

+ || gpc_reg_operand (operands[1], <MODE>mode))"

75311

"@

75312

stfd%U0%X0 %1,%0

75313

lfd%U1%X1 %0,%1

75314

fmr %0,%1

75315

lxsd%U1x %x0,%y1

75316

- lxsd%U1x %x0,%y1

75317

stxsd%U0x %x1,%y0

75318

- stxsd%U0x %x1,%y0

75319

xxlor %x0,%x1,%x1

75320

- xxlor %x0,%x1,%x1

75321

xxlxor %x0,%x0,%x0

75322

#

75323

#

75324

@@ -8122,115 +9441,141 @@

75325

#

75326

#

75327

#"

75328

- [(set_attr "type" "fpstore,fpload,fp,fpload,fpload,fpstore,fpstore,vecsimple,vecsimple,vecsimple,store,load,two,fp,fp,*")

75329

- (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,8,8,8,12,16")])

75330

+ [(set_attr_alternative "type"

75331

+ [(if_then_else

75332

+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")

75333

+ (const_string "fpstore_ux")

75334

+ (if_then_else

75335

+ (match_test "update_address_mem (operands[0], VOIDmode)")

75336

+ (const_string "fpstore_u")

75337

+ (const_string "fpstore")))

75338

+ (if_then_else

75339

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

75340

+ (const_string "fpload_ux")

75341

+ (if_then_else

75342

+ (match_test "update_address_mem (operands[1], VOIDmode)")

75343

+ (const_string "fpload_u")

75344

+ (const_string "fpload")))

75345

+ (const_string "fp")

75346

+ (if_then_else

75347

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

75348

+ (const_string "fpload_ux")

75349

+ (const_string "fpload"))

75350

+ (if_then_else

75351

+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")

75352

+ (const_string "fpstore_ux")

75353

+ (const_string "fpstore"))

75354

+ (const_string "vecsimple")

75355

+ (const_string "vecsimple")

75356

+ (const_string "store")

75357

+ (const_string "load")

75358

+ (const_string "two")

75359

+ (const_string "fp")

75360

+ (const_string "fp")

75361

+ (const_string "*")])

75362

+ (set_attr "length" "4,4,4,4,4,4,4,8,8,8,8,12,16")])

75363

75364

-(define_insn "*movdf_softfloat32"

75365

- [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,r,r,r,r")

75366

- (match_operand:DF 1 "input_operand" "r,Y,r,G,H,F"))]

75367

+(define_insn "*mov<mode>_softfloat32"

75368

+ [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,r,r,r")

75369

+ (match_operand:FMOVE64 1 "input_operand" "r,Y,r,G,H,F"))]

75370

"! TARGET_POWERPC64

75371

&& ((TARGET_FPRS && TARGET_SINGLE_FLOAT)

75372

- || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)

75373

- && (gpc_reg_operand (operands[0], DFmode)

75374

- || gpc_reg_operand (operands[1], DFmode))"

75375

+ || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE

75376

+ || (<MODE>mode == DDmode && TARGET_E500_DOUBLE))

75377

+ && (gpc_reg_operand (operands[0], <MODE>mode)

75378

+ || gpc_reg_operand (operands[1], <MODE>mode))"

75379

"#"

75380

[(set_attr "type" "store,load,two,*,*,*")

75381

(set_attr "length" "8,8,8,8,12,16")])

75382

75383

-;; Reload patterns to support gpr load/store with misaligned mem.

75384

-;; and multiple gpr load/store at offset >= 0xfffc

75385

-(define_expand "reload_<mode>_store"

75386

- [(parallel [(match_operand 0 "memory_operand" "=m")

75387

- (match_operand 1 "gpc_reg_operand" "r")

75388

- (match_operand:GPR 2 "register_operand" "=&b")])]

75389

- ""

75390

-{

75391

- rs6000_secondary_reload_gpr (operands[1], operands[0], operands[2], true);

75392

- DONE;

75393

-})

75394

-

75395

-(define_expand "reload_<mode>_load"

75396

- [(parallel [(match_operand 0 "gpc_reg_operand" "=r")

75397

- (match_operand 1 "memory_operand" "m")

75398

- (match_operand:GPR 2 "register_operand" "=b")])]

75399

- ""

75400

-{

75401

- rs6000_secondary_reload_gpr (operands[0], operands[1], operands[2], false);

75402

- DONE;

75403

-})

75404

-

75405

; ld/std require word-aligned displacements -> 'Y' constraint.

75406

; List Y->r and r->Y before r->r for reload.

75407

-(define_insn "*movdf_hardfloat64_mfpgpr"

75408

- [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,m,d,d,wa,*c*l,!r,*h,!r,!r,!r,r,d")

75409

- (match_operand:DF 1 "input_operand" "r,Y,r,ws,?wa,Z,Z,ws,wa,d,m,d,j,r,h,0,G,H,F,d,r"))]

75410

- "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS

75411

- && TARGET_DOUBLE_FLOAT

75412

- && (gpc_reg_operand (operands[0], DFmode)

75413

- || gpc_reg_operand (operands[1], DFmode))"

75414

+(define_insn "*mov<mode>_hardfloat64"

75415

+ [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,wv,Z,wa,wa,Y,r,!r,*c*l,!r,*h,!r,!r,!r,r,wg,r,wm")

75416

+ (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,wv,wa,j,r,Y,r,r,h,0,G,H,F,wg,r,wm,r"))]

75417

+ "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT

75418

+ && (gpc_reg_operand (operands[0], <MODE>mode)

75419

+ || gpc_reg_operand (operands[1], <MODE>mode))"

75420

"@

75421

- std%U0%X0 %1,%0

75422

- ld%U1%X1 %0,%1

75423

- mr %0,%1

75424

- xxlor %x0,%x1,%x1

75425

- xxlor %x0,%x1,%x1

75426

- lxsd%U1x %x0,%y1

75427

- lxsd%U1x %x0,%y1

75428

- stxsd%U0x %x1,%y0

75429

- stxsd%U0x %x1,%y0

75430

stfd%U0%X0 %1,%0

75431

lfd%U1%X1 %0,%1

75432

fmr %0,%1

75433

+ lxsd%U1x %x0,%y1

75434

+ stxsd%U0x %x1,%y0

75435

+ xxlor %x0,%x1,%x1

75436

xxlxor %x0,%x0,%x0

75437

- mt%0 %1

75438

- mf%1 %0

75439

- nop

75440

- #

75441

- #

75442

- #

75443

- mftgpr %0,%1

75444

- mffgpr %0,%1"

75445

- [(set_attr "type" "store,load,*,fp,fp,fpload,fpload,fpstore,fpstore,fpstore,fpload,fp,vecsimple,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")

75446

- (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4")])

75447

-

75448

-; ld/std require word-aligned displacements -> 'Y' constraint.

75449

-; List Y->r and r->Y before r->r for reload.

75450

-(define_insn "*movdf_hardfloat64"

75451

- [(set (match_operand:DF 0 "nonimmediate_operand" "=m,d,d,Y,r,!r,ws,?wa,Z,?Z,ws,?wa,wa,*c*l,!r,*h,!r,!r,!r")

75452

- (match_operand:DF 1 "input_operand" "d,m,d,r,Y,r,Z,Z,ws,wa,ws,wa,j,r,h,0,G,H,F"))]

75453

- "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS

75454

- && TARGET_DOUBLE_FLOAT

75455

- && (gpc_reg_operand (operands[0], DFmode)

75456

- || gpc_reg_operand (operands[1], DFmode))"

75457

- "@

75458

- stfd%U0%X0 %1,%0

75459

- lfd%U1%X1 %0,%1

75460

- fmr %0,%1

75461

std%U0%X0 %1,%0

75462

ld%U1%X1 %0,%1

75463

mr %0,%1

75464

- lxsd%U1x %x0,%y1

75465

- lxsd%U1x %x0,%y1

75466

- stxsd%U0x %x1,%y0

75467

- stxsd%U0x %x1,%y0

75468

- xxlor %x0,%x1,%x1

75469

- xxlor %x0,%x1,%x1

75470

- xxlxor %x0,%x0,%x0

75471

mt%0 %1

75472

mf%1 %0

75473

nop

75474

#

75475

#

75476

- #"

75477

- [(set_attr "type" "fpstore,fpload,fp,store,load,*,fpload,fpload,fpstore,fpstore,vecsimple,vecsimple,vecsimple,mtjmpr,mfjmpr,*,*,*,*")

75478

- (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16")])

75479

+ #

75480

+ mftgpr %0,%1

75481

+ mffgpr %0,%1

75482

+ mfvsrd %0,%x1

75483

+ mtvsrd %x0,%1"

75484

+ [(set_attr_alternative "type"

75485

+ [(if_then_else

75486

+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")

75487

+ (const_string "fpstore_ux")

75488

+ (if_then_else

75489

+ (match_test "update_address_mem (operands[0], VOIDmode)")

75490

+ (const_string "fpstore_u")

75491

+ (const_string "fpstore")))

75492

+ (if_then_else

75493

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

75494

+ (const_string "fpload_ux")

75495

+ (if_then_else

75496

+ (match_test "update_address_mem (operands[1], VOIDmode)")

75497

+ (const_string "fpload_u")

75498

+ (const_string "fpload")))

75499

+ (const_string "fp")

75500

+ (if_then_else

75501

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

75502

+ (const_string "fpload_ux")

75503

+ (const_string "fpload"))

75504

+ (if_then_else

75505

+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")

75506

+ (const_string "fpstore_ux")

75507

+ (const_string "fpstore"))

75508

+ (const_string "vecsimple")

75509

+ (const_string "vecsimple")

75510

+ (if_then_else

75511

+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")

75512

+ (const_string "store_ux")

75513

+ (if_then_else

75514

+ (match_test "update_address_mem (operands[0], VOIDmode)")

75515

+ (const_string "store_u")

75516

+ (const_string "store")))

75517

+ (if_then_else

75518

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

75519

+ (const_string "load_ux")

75520

+ (if_then_else

75521

+ (match_test "update_address_mem (operands[1], VOIDmode)")

75522

+ (const_string "load_u")

75523

+ (const_string "load")))

75524

+ (const_string "*")

75525

+ (const_string "mtjmpr")

75526

+ (const_string "mfjmpr")

75527

+ (const_string "*")

75528

+ (const_string "*")

75529

+ (const_string "*")

75530

+ (const_string "*")

75531

+ (const_string "mftgpr")

75532

+ (const_string "mffgpr")

75533

+ (const_string "mftgpr")

75534

+ (const_string "mffgpr")])

75535

+ (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4,4,4")])

75536

75537

-(define_insn "*movdf_softfloat64"

75538

- [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,r,cl,r,r,r,r,*h")

75539

- (match_operand:DF 1 "input_operand" "r,Y,r,r,h,G,H,F,0"))]

75540

+(define_insn "*mov<mode>_softfloat64"

75541

+ [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,cl,r,r,r,r,*h")

75542

+ (match_operand:FMOVE64 1 "input_operand" "r,Y,r,r,h,G,H,F,0"))]

75543

"TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)

75544

- && (gpc_reg_operand (operands[0], DFmode)

75545

- || gpc_reg_operand (operands[1], DFmode))"

75546

+ && (gpc_reg_operand (operands[0], <MODE>mode)

75547

+ || gpc_reg_operand (operands[1], <MODE>mode))"

75548

"@

75549

std%U0%X0 %1,%0

75550

ld%U1%X1 %0,%1

75551

@@ -8241,38 +9586,87 @@

75552

#

75553

#

75554

nop"

75555

- [(set_attr "type" "store,load,*,mtjmpr,mfjmpr,*,*,*,*")

75556

+ [(set_attr_alternative "type"

75557

+ [(if_then_else

75558

+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")

75559

+ (const_string "store_ux")

75560

+ (if_then_else

75561

+ (match_test "update_address_mem (operands[0], VOIDmode)")

75562

+ (const_string "store_u")

75563

+ (const_string "store")))

75564

+ (if_then_else

75565

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

75566

+ (const_string "load_ux")

75567

+ (if_then_else

75568

+ (match_test "update_address_mem (operands[1], VOIDmode)")

75569

+ (const_string "load_u")

75570

+ (const_string "load")))

75571

+ (const_string "*")

75572

+ (const_string "mtjmpr")

75573

+ (const_string "mfjmpr")

75574

+ (const_string "*")

75575

+ (const_string "*")

75576

+ (const_string "*")

75577

+ (const_string "*")])

75578

(set_attr "length" "4,4,4,4,4,8,12,16,4")])

75579

75580

-(define_expand "movtf"

75581

- [(set (match_operand:TF 0 "general_operand" "")

75582

- (match_operand:TF 1 "any_operand" ""))]

75583

- "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"

75584

- "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")

75585

+(define_expand "mov<mode>"

75586

+ [(set (match_operand:FMOVE128 0 "general_operand" "")

75587

+ (match_operand:FMOVE128 1 "any_operand" ""))]

75588

+ ""

75589

+ "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")

75590

75591

;; It's important to list Y->r and r->Y before r->r because otherwise

75592

;; reload, given m->r, will try to pick r->r and reload it, which

75593

;; doesn't make progress.

75594

-(define_insn_and_split "*movtf_internal"

75595

- [(set (match_operand:TF 0 "nonimmediate_operand" "=m,d,d,Y,r,r")

75596

- (match_operand:TF 1 "input_operand" "d,m,d,r,YGHF,r"))]

75597

- "!TARGET_IEEEQUAD

75598

- && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128

75599

- && (gpc_reg_operand (operands[0], TFmode)

75600

- || gpc_reg_operand (operands[1], TFmode))"

75601

+

75602

+;; We can't split little endian direct moves of TDmode, because the words are

75603

+;; not swapped like they are for TImode or TFmode. Subregs therefore are

75604

+;; problematical. Don't allow direct move for this case.

75605

+

75606

+(define_insn_and_split "*mov<mode>_64bit_dm"

75607

+ [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,Y,r,r,r,wm")

75608

+ (match_operand:FMOVE128 1 "input_operand" "d,m,d,r,YGHF,r,wm,r"))]

75609

+ "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64

75610

+ && (<MODE>mode != TDmode || WORDS_BIG_ENDIAN)

75611

+ && (gpc_reg_operand (operands[0], <MODE>mode)

75612

+ || gpc_reg_operand (operands[1], <MODE>mode))"

75613

"#"

75614

"&& reload_completed"

75615

[(pc)]

75616

{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }

75617

+ [(set_attr "length" "8,8,8,12,12,8,8,8")])

75618

+

75619

+(define_insn_and_split "*movtd_64bit_nodm"

75620

+ [(set (match_operand:TD 0 "nonimmediate_operand" "=m,d,d,Y,r,r")

75621

+ (match_operand:TD 1 "input_operand" "d,m,d,r,YGHF,r"))]

75622

+ "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64 && !WORDS_BIG_ENDIAN

75623

+ && (gpc_reg_operand (operands[0], TDmode)

75624

+ || gpc_reg_operand (operands[1], TDmode))"

75625

+ "#"

75626

+ "&& reload_completed"

75627

+ [(pc)]

75628

+{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }

75629

+ [(set_attr "length" "8,8,8,12,12,8")])

75630

+

75631

+(define_insn_and_split "*mov<mode>_32bit"

75632

+ [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,Y,r,r")

75633

+ (match_operand:FMOVE128 1 "input_operand" "d,m,d,r,YGHF,r"))]

75634

+ "TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_POWERPC64

75635

+ && (gpc_reg_operand (operands[0], <MODE>mode)

75636

+ || gpc_reg_operand (operands[1], <MODE>mode))"

75637

+ "#"

75638

+ "&& reload_completed"

75639

+ [(pc)]

75640

+{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }

75641

[(set_attr "length" "8,8,8,20,20,16")])

75642

75643

-(define_insn_and_split "*movtf_softfloat"

75644

- [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=Y,r,r")

75645

- (match_operand:TF 1 "input_operand" "r,YGHF,r"))]

75646

- "!TARGET_IEEEQUAD

75647

- && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128

75648

- && (gpc_reg_operand (operands[0], TFmode)

75649

- || gpc_reg_operand (operands[1], TFmode))"

75650

+(define_insn_and_split "*mov<mode>_softfloat"

75651

+ [(set (match_operand:FMOVE128 0 "rs6000_nonimmediate_operand" "=Y,r,r")

75652

+ (match_operand:FMOVE128 1 "input_operand" "r,YGHF,r"))]

75653

+ "(TARGET_SOFT_FLOAT || !TARGET_FPRS)

75654

+ && (gpc_reg_operand (operands[0], <MODE>mode)

75655

+ || gpc_reg_operand (operands[1], <MODE>mode))"

75656

"#"

75657

"&& reload_completed"

75658

[(pc)]

75659

@@ -8557,6 +9951,252 @@

75660

operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);

75661

}")

75662

75663

+;; Reload helper functions used by rs6000_secondary_reload. The patterns all

75664

+;; must have 3 arguments, and scratch register constraint must be a single

75665

+;; constraint.

75666

+

75667

+;; Reload patterns to support gpr load/store with misaligned mem.

75668

+;; and multiple gpr load/store at offset >= 0xfffc

75669

+(define_expand "reload_<mode>_store"

75670

+ [(parallel [(match_operand 0 "memory_operand" "=m")

75671

+ (match_operand 1 "gpc_reg_operand" "r")

75672

+ (match_operand:GPR 2 "register_operand" "=&b")])]

75673

+ ""

75674

+{

75675

+ rs6000_secondary_reload_gpr (operands[1], operands[0], operands[2], true);

75676

+ DONE;

75677

+})

75678

+

75679

+(define_expand "reload_<mode>_load"

75680

+ [(parallel [(match_operand 0 "gpc_reg_operand" "=r")

75681

+ (match_operand 1 "memory_operand" "m")

75682

+ (match_operand:GPR 2 "register_operand" "=b")])]

75683

+ ""

75684

+{

75685

+ rs6000_secondary_reload_gpr (operands[0], operands[1], operands[2], false);

75686

+ DONE;

75687

+})

75688

+

75689

+

75690

+;; Power8 merge instructions to allow direct move to/from floating point

75691

+;; registers in 32-bit mode. We use TF mode to get two registers to move the

75692

+;; individual 32-bit parts across. Subreg doesn't work too well on the TF

75693

+;; value, since it is allocated in reload and not all of the flow information

75694

+;; is setup for it. We have two patterns to do the two moves between gprs and

75695

+;; fprs. There isn't a dependancy between the two, but we could potentially

75696

+;; schedule other instructions between the two instructions. TFmode is

75697

+;; currently limited to traditional FPR registers. If/when this is changed, we

75698

+;; will need to revist %L to make sure it works with VSX registers, or add an

75699

+;; %x version of %L.

75700

+

75701

+(define_insn "p8_fmrgow_<mode>"

75702

+ [(set (match_operand:FMOVE64X 0 "register_operand" "=d")

75703

+ (unspec:FMOVE64X [(match_operand:TF 1 "register_operand" "d")]

75704

+ UNSPEC_P8V_FMRGOW))]

75705

+ "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"

75706

+ "fmrgow %0,%1,%L1"

75707

+ [(set_attr "type" "vecperm")])

75708

+

75709

+(define_insn "p8_mtvsrwz_1"

75710

+ [(set (match_operand:TF 0 "register_operand" "=d")

75711

+ (unspec:TF [(match_operand:SI 1 "register_operand" "r")]

75712

+ UNSPEC_P8V_MTVSRWZ))]

75713

+ "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"

75714

+ "mtvsrwz %x0,%1"

75715

+ [(set_attr "type" "mftgpr")])

75716

+

75717

+(define_insn "p8_mtvsrwz_2"

75718

+ [(set (match_operand:TF 0 "register_operand" "+d")

75719

+ (unspec:TF [(match_dup 0)

75720

+ (match_operand:SI 1 "register_operand" "r")]

75721

+ UNSPEC_P8V_MTVSRWZ))]

75722

+ "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"

75723

+ "mtvsrwz %L0,%1"

75724

+ [(set_attr "type" "mftgpr")])

75725

+

75726

+(define_insn_and_split "reload_fpr_from_gpr<mode>"

75727

+ [(set (match_operand:FMOVE64X 0 "register_operand" "=ws")

75728

+ (unspec:FMOVE64X [(match_operand:FMOVE64X 1 "register_operand" "r")]

75729

+ UNSPEC_P8V_RELOAD_FROM_GPR))

75730

+ (clobber (match_operand:TF 2 "register_operand" "=d"))]

75731

+ "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"

75732

+ "#"

75733

+ "&& reload_completed"

75734

+ [(const_int 0)]

75735

+{

75736

+ rtx dest = operands[0];

75737

+ rtx src = operands[1];

75738

+ rtx tmp = operands[2];

75739

+ rtx gpr_hi_reg = gen_highpart (SImode, src);

75740

+ rtx gpr_lo_reg = gen_lowpart (SImode, src);

75741

+

75742

+ emit_insn (gen_p8_mtvsrwz_1 (tmp, gpr_hi_reg));

75743

+ emit_insn (gen_p8_mtvsrwz_2 (tmp, gpr_lo_reg));

75744

+ emit_insn (gen_p8_fmrgow_<mode> (dest, tmp));

75745

+ DONE;

75746

+}

75747

+ [(set_attr "length" "12")

75748

+ (set_attr "type" "three")])

75749

+

75750

+;; Move 128 bit values from GPRs to VSX registers in 64-bit mode

75751

+(define_insn "p8_mtvsrd_1"

75752

+ [(set (match_operand:TF 0 "register_operand" "=ws")

75753

+ (unspec:TF [(match_operand:DI 1 "register_operand" "r")]

75754

+ UNSPEC_P8V_MTVSRD))]

75755

+ "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"

75756

+ "mtvsrd %0,%1"

75757

+ [(set_attr "type" "mftgpr")])

75758

+

75759

+(define_insn "p8_mtvsrd_2"

75760

+ [(set (match_operand:TF 0 "register_operand" "+ws")

75761

+ (unspec:TF [(match_dup 0)

75762

+ (match_operand:DI 1 "register_operand" "r")]

75763

+ UNSPEC_P8V_MTVSRD))]

75764

+ "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"

75765

+ "mtvsrd %L0,%1"

75766

+ [(set_attr "type" "mftgpr")])

75767

+

75768

+(define_insn "p8_xxpermdi_<mode>"

75769

+ [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=wa")

75770

+ (unspec:FMOVE128_GPR [(match_operand:TF 1 "register_operand" "ws")]

75771

+ UNSPEC_P8V_XXPERMDI))]

75772

+ "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"

75773

+ "xxpermdi %x0,%1,%L1,0"

75774

+ [(set_attr "type" "vecperm")])

75775

+

75776

+(define_insn_and_split "reload_vsx_from_gpr<mode>"

75777

+ [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=wa")

75778

+ (unspec:FMOVE128_GPR

75779

+ [(match_operand:FMOVE128_GPR 1 "register_operand" "r")]

75780

+ UNSPEC_P8V_RELOAD_FROM_GPR))

75781

+ (clobber (match_operand:TF 2 "register_operand" "=ws"))]

75782

+ "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"

75783

+ "#"

75784

+ "&& reload_completed"

75785

+ [(const_int 0)]

75786

+{

75787

+ rtx dest = operands[0];

75788

+ rtx src = operands[1];

75789

+ rtx tmp = operands[2];

75790

+ rtx gpr_hi_reg = gen_highpart (DImode, src);

75791

+ rtx gpr_lo_reg = gen_lowpart (DImode, src);

75792

+

75793

+ emit_insn (gen_p8_mtvsrd_1 (tmp, gpr_hi_reg));

75794

+ emit_insn (gen_p8_mtvsrd_2 (tmp, gpr_lo_reg));

75795

+ emit_insn (gen_p8_xxpermdi_<mode> (dest, tmp));

75796

+}

75797

+ [(set_attr "length" "12")

75798

+ (set_attr "type" "three")])

75799

+

75800

+(define_split

75801

+ [(set (match_operand:FMOVE128_GPR 0 "nonimmediate_operand" "")

75802

+ (match_operand:FMOVE128_GPR 1 "input_operand" ""))]

75803

+ "reload_completed

75804

+ && (int_reg_operand (operands[0], <MODE>mode)

75805

+ || int_reg_operand (operands[1], <MODE>mode))"

75806

+ [(pc)]

75807

+{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })

75808

+

75809

+;; Move SFmode to a VSX from a GPR register. Because scalar floating point

75810

+;; type is stored internally as double precision in the VSX registers, we have

75811

+;; to convert it from the vector format.

75812

+

75813

+(define_insn_and_split "reload_vsx_from_gprsf"

75814

+ [(set (match_operand:SF 0 "register_operand" "=wa")

75815

+ (unspec:SF [(match_operand:SF 1 "register_operand" "r")]

75816

+ UNSPEC_P8V_RELOAD_FROM_GPR))

75817

+ (clobber (match_operand:DI 2 "register_operand" "=r"))]

75818

+ "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"

75819

+ "#"

75820

+ "&& reload_completed"

75821

+ [(const_int 0)]

75822

+{

75823

+ rtx op0 = operands[0];

75824

+ rtx op1 = operands[1];

75825

+ rtx op2 = operands[2];

75826

+ rtx op0_di = simplify_gen_subreg (DImode, op0, SFmode, 0);

75827

+ rtx op1_di = simplify_gen_subreg (DImode, op1, SFmode, 0);

75828

+

75829

+ /* Move SF value to upper 32-bits for xscvspdpn. */

75830

+ emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (32)));

75831

+ emit_move_insn (op0_di, op2);

75832

+ emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0));

75833

+ DONE;

75834

+}

75835

+ [(set_attr "length" "8")

75836

+ (set_attr "type" "two")])

75837

+

75838

+;; Move 128 bit values from VSX registers to GPRs in 64-bit mode by doing a

75839

+;; normal 64-bit move, followed by an xxpermdi to get the bottom 64-bit value,

75840

+;; and then doing a move of that.

75841

+(define_insn "p8_mfvsrd_3_<mode>"

75842

+ [(set (match_operand:DF 0 "register_operand" "=r")

75843

+ (unspec:DF [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]

75844

+ UNSPEC_P8V_RELOAD_FROM_VSX))]

75845

+ "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"

75846

+ "mfvsrd %0,%x1"

75847

+ [(set_attr "type" "mftgpr")])

75848

+

75849

+(define_insn_and_split "reload_gpr_from_vsx<mode>"

75850

+ [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=r")

75851

+ (unspec:FMOVE128_GPR

75852

+ [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]

75853

+ UNSPEC_P8V_RELOAD_FROM_VSX))

75854

+ (clobber (match_operand:FMOVE128_GPR 2 "register_operand" "=wa"))]

75855

+ "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"

75856

+ "#"

75857

+ "&& reload_completed"

75858

+ [(const_int 0)]

75859

+{

75860

+ rtx dest = operands[0];

75861

+ rtx src = operands[1];

75862

+ rtx tmp = operands[2];

75863

+ rtx gpr_hi_reg = gen_highpart (DFmode, dest);

75864

+ rtx gpr_lo_reg = gen_lowpart (DFmode, dest);

75865

+

75866

+ emit_insn (gen_p8_mfvsrd_3_<mode> (gpr_hi_reg, src));

75867

+ emit_insn (gen_vsx_xxpermdi_<mode> (tmp, src, src, GEN_INT (3)));

75868

+ emit_insn (gen_p8_mfvsrd_3_<mode> (gpr_lo_reg, tmp));

75869

+}

75870

+ [(set_attr "length" "12")

75871

+ (set_attr "type" "three")])

75872

+

75873

+;; Move SFmode to a GPR from a VSX register. Because scalar floating point

75874

+;; type is stored internally as double precision, we have to convert it to the

75875

+;; vector format.

75876

+

75877

+(define_insn_and_split "reload_gpr_from_vsxsf"

75878

+ [(set (match_operand:SF 0 "register_operand" "=r")

75879

+ (unspec:SF [(match_operand:SF 1 "register_operand" "wa")]

75880

+ UNSPEC_P8V_RELOAD_FROM_VSX))

75881

+ (clobber (match_operand:V4SF 2 "register_operand" "=wa"))]

75882

+ "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"

75883

+ "#"

75884

+ "&& reload_completed"

75885

+ [(const_int 0)]

75886

+{

75887

+ rtx op0 = operands[0];

75888

+ rtx op1 = operands[1];

75889

+ rtx op2 = operands[2];

75890

+ rtx diop0 = simplify_gen_subreg (DImode, op0, SFmode, 0);

75891

+

75892

+ emit_insn (gen_vsx_xscvdpspn_scalar (op2, op1));

75893

+ emit_insn (gen_p8_mfvsrd_4_disf (diop0, op2));

75894

+ emit_insn (gen_lshrdi3 (diop0, diop0, GEN_INT (32)));

75895

+ DONE;

75896

+}

75897

+ [(set_attr "length" "12")

75898

+ (set_attr "type" "three")])

75899

+

75900

+(define_insn "p8_mfvsrd_4_disf"

75901

+ [(set (match_operand:DI 0 "register_operand" "=r")

75902

+ (unspec:DI [(match_operand:V4SF 1 "register_operand" "wa")]

75903

+ UNSPEC_P8V_RELOAD_FROM_VSX))]

75904

+ "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"

75905

+ "mfvsrd %0,%x1"

75906

+ [(set_attr "type" "mftgpr")])

75907

+

75908

+

75909

;; Next come the multi-word integer load and store and the load and store

75910

;; multiple insns.

75911

75912

@@ -8565,8 +10205,8 @@

75913

;; Use of fprs is disparaged slightly otherwise reload prefers to reload

75914

;; a gpr into a fpr instead of reloading an invalid 'Y' address

75915

(define_insn "*movdi_internal32"

75916

- [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=Y,r,r,?m,?*d,?*d,r,?wa")

75917

- (match_operand:DI 1 "input_operand" "r,Y,r,d,m,d,IJKnGHF,O"))]

75918

+ [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=Y,r,r,?m,?*d,?*d,r")

75919

+ (match_operand:DI 1 "input_operand" "r,Y,r,d,m,d,IJKnGHF"))]

75920

"! TARGET_POWERPC64

75921

&& (gpc_reg_operand (operands[0], DImode)

75922

|| gpc_reg_operand (operands[1], DImode))"

75923

@@ -8577,15 +10217,34 @@

75924

stfd%U0%X0 %1,%0

75925

lfd%U1%X1 %0,%1

75926

fmr %0,%1

75927

- #

75928

- xxlxor %x0,%x0,%x0"

75929

- [(set_attr "type" "store,load,*,fpstore,fpload,fp,*,vecsimple")])

75930

+ #"

75931

+ [(set_attr_alternative "type"

75932

+ [(const_string "store")

75933

+ (const_string "load")

75934

+ (const_string "*")

75935

+ (if_then_else

75936

+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")

75937

+ (const_string "fpstore_ux")

75938

+ (if_then_else

75939

+ (match_test "update_address_mem (operands[0], VOIDmode)")

75940

+ (const_string "fpstore_u")

75941

+ (const_string "fpstore")))

75942

+ (if_then_else

75943

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

75944

+ (const_string "fpload_ux")

75945

+ (if_then_else

75946

+ (match_test "update_address_mem (operands[1], VOIDmode)")

75947

+ (const_string "fpload_u")

75948

+ (const_string "fpload")))

75949

+ (const_string "fp")

75950

+ (const_string "*")])])

75951

75952

(define_split

75953

[(set (match_operand:DI 0 "gpc_reg_operand" "")

75954

(match_operand:DI 1 "const_int_operand" ""))]

75955

"! TARGET_POWERPC64 && reload_completed

75956

- && gpr_or_gpr_p (operands[0], operands[1])"

75957

+ && gpr_or_gpr_p (operands[0], operands[1])

75958

+ && !direct_move_p (operands[0], operands[1])"

75959

[(set (match_dup 2) (match_dup 4))

75960

(set (match_dup 3) (match_dup 1))]

75961

"

75962

@@ -8607,14 +10266,15 @@

75963

[(set (match_operand:DIFD 0 "rs6000_nonimmediate_operand" "")

75964

(match_operand:DIFD 1 "input_operand" ""))]

75965

"reload_completed && !TARGET_POWERPC64

75966

- && gpr_or_gpr_p (operands[0], operands[1])"

75967

+ && gpr_or_gpr_p (operands[0], operands[1])

75968

+ && !direct_move_p (operands[0], operands[1])"

75969

[(pc)]

75970

{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })

75971

75972

-(define_insn "*movdi_mfpgpr"

75973

- [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*d")

75974

- (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*d,r"))]

75975

- "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS

75976

+(define_insn "*movdi_internal64"

75977

+ [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*wg,r,?*wm")

75978

+ (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*wg,r,*wm,r"))]

75979

+ "TARGET_POWERPC64

75980

&& (gpc_reg_operand (operands[0], DImode)

75981

|| gpc_reg_operand (operands[1], DImode))"

75982

"@

75983

@@ -8631,33 +10291,52 @@

75984

mt%0 %1

75985

nop

75986

mftgpr %0,%1

75987

- mffgpr %0,%1"

75988

- [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,mftgpr,mffgpr")

75989

- (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4")])

75990

+ mffgpr %0,%1

75991

+ mfvsrd %0,%x1

75992

+ mtvsrd %x0,%1"

75993

+ [(set_attr_alternative "type"

75994

+ [(if_then_else

75995

+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")

75996

+ (const_string "store_ux")

75997

+ (if_then_else

75998

+ (match_test "update_address_mem (operands[0], VOIDmode)")

75999

+ (const_string "store_u")

76000

+ (const_string "store")))

76001

+ (if_then_else

76002

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

76003

+ (const_string "load_ux")

76004

+ (if_then_else

76005

+ (match_test "update_address_mem (operands[1], VOIDmode)")

76006

+ (const_string "load_u")

76007

+ (const_string "load")))

76008

+ (const_string "*")

76009

+ (const_string "*")

76010

+ (const_string "*")

76011

+ (const_string "*")

76012

+ (if_then_else

76013

+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")

76014

+ (const_string "fpstore_ux")

76015

+ (if_then_else

76016

+ (match_test "update_address_mem (operands[0], VOIDmode)")

76017

+ (const_string "fpstore_u")

76018

+ (const_string "fpstore")))

76019

+ (if_then_else

76020

+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")

76021

+ (const_string "fpload_ux")

76022

+ (if_then_else

76023

+ (match_test "update_address_mem (operands[1], VOIDmode)")

76024

+ (const_string "fpload_u")

76025

+ (const_string "fpload")))

76026

+ (const_string "fp")

76027

+ (const_string "mfjmpr")

76028

+ (const_string "mtjmpr")

76029

+ (const_string "*")

76030

+ (const_string "mftgpr")

76031

+ (const_string "mffgpr")

76032

+ (const_string "mftgpr")

76033

+ (const_string "mffgpr")])

76034

+ (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4,4")])

76035

76036

-(define_insn "*movdi_internal64"

76037

- [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,?wa")

76038

- (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,O"))]

76039

- "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)

76040

- && (gpc_reg_operand (operands[0], DImode)

76041

- || gpc_reg_operand (operands[1], DImode))"

76042

- "@

76043

- std%U0%X0 %1,%0

76044

- ld%U1%X1 %0,%1

76045

- mr %0,%1

76046

- li %0,%1

76047

- lis %0,%v1

76048

- #

76049

- stfd%U0%X0 %1,%0

76050

- lfd%U1%X1 %0,%1

76051

- fmr %0,%1

76052

- mf%1 %0

76053

- mt%0 %1

76054

- nop

76055

- xxlxor %x0,%x0,%x0"

76056

- [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,vecsimple")

76057

- (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])

76058

-

76059

;; immediate value valid for a single instruction hiding in a const_double

76060

(define_insn ""

76061

[(set (match_operand:DI 0 "gpc_reg_operand" "=r")

76062

@@ -8719,14 +10398,16 @@

76063

FAIL;

76064

}")

76065

76066

-;; TImode is similar, except that we usually want to compute the address into

76067

-;; a register and use lsi/stsi (the exception is during reload).

76068

+;; TImode/PTImode is similar, except that we usually want to compute the

76069

+;; address into a register and use lsi/stsi (the exception is during reload).

76070

76071

-(define_insn "*movti_string"

76072

- [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,Y,????r,????r,????r,r")

76073

- (match_operand:TI 1 "input_operand" "r,r,Q,Y,r,n"))]

76074

+(define_insn "*mov<mode>_string"

76075

+ [(set (match_operand:TI2 0 "reg_or_mem_operand" "=Q,Y,????r,????r,????r,r")

76076

+ (match_operand:TI2 1 "input_operand" "r,r,Q,Y,r,n"))]

76077

"! TARGET_POWERPC64

76078

- && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"

76079

+ && (<MODE>mode != TImode || VECTOR_MEM_NONE_P (TImode))

76080

+ && (gpc_reg_operand (operands[0], <MODE>mode)

76081

+ || gpc_reg_operand (operands[1], <MODE>mode))"

76082

"*

76083

{

76084

switch (which_alternative)

76085

@@ -8756,27 +10437,32 @@

76086

(const_string "always")

76087

(const_string "conditional")))])

76088

76089

-(define_insn "*movti_ppc64"

76090

- [(set (match_operand:TI 0 "nonimmediate_operand" "=Y,r,r")

76091

- (match_operand:TI 1 "input_operand" "r,Y,r"))]

76092

- "(TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)

76093

- || gpc_reg_operand (operands[1], TImode)))

76094

- && VECTOR_MEM_NONE_P (TImode)"

76095

- "#"

76096

- [(set_attr "type" "store,load,*")])

76097

+(define_insn "*mov<mode>_ppc64"

76098

+ [(set (match_operand:TI2 0 "nonimmediate_operand" "=wQ,Y,r,r,r,r")

76099

+ (match_operand:TI2 1 "input_operand" "r,r,wQ,Y,r,n"))]

76100

+ "(TARGET_POWERPC64 && VECTOR_MEM_NONE_P (<MODE>mode)

76101

+ && (gpc_reg_operand (operands[0], <MODE>mode)

76102

+ || gpc_reg_operand (operands[1], <MODE>mode)))"

76103

+{

76104

+ return rs6000_output_move_128bit (operands);

76105

+}

76106

+ [(set_attr "type" "store,store,load,load,*,*")

76107

+ (set_attr "length" "8")])

76108

76109

(define_split

76110

- [(set (match_operand:TI 0 "gpc_reg_operand" "")

76111

- (match_operand:TI 1 "const_double_operand" ""))]

76112

- "TARGET_POWERPC64 && VECTOR_MEM_NONE_P (TImode)"

76113

+ [(set (match_operand:TI2 0 "int_reg_operand" "")

76114

+ (match_operand:TI2 1 "const_double_operand" ""))]

76115

+ "TARGET_POWERPC64

76116

+ && (VECTOR_MEM_NONE_P (<MODE>mode)

76117

+ || (reload_completed && INT_REGNO_P (REGNO (operands[0]))))"

76118

[(set (match_dup 2) (match_dup 4))

76119

(set (match_dup 3) (match_dup 5))]

76120

"

76121

{

76122

operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,

76123

- TImode);

76124

+ <MODE>mode);

76125

operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,

76126

- TImode);

76127

+ <MODE>mode);

76128

if (GET_CODE (operands[1]) == CONST_DOUBLE)

76129

{

76130

operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));

76131

@@ -8792,10 +10478,12 @@

76132

}")

76133

76134

(define_split

76135

- [(set (match_operand:TI 0 "nonimmediate_operand" "")

76136

- (match_operand:TI 1 "input_operand" ""))]

76137

- "reload_completed && VECTOR_MEM_NONE_P (TImode)

76138

- && gpr_or_gpr_p (operands[0], operands[1])"

76139

+ [(set (match_operand:TI2 0 "nonimmediate_operand" "")

76140

+ (match_operand:TI2 1 "input_operand" ""))]

76141

+ "reload_completed

76142

+ && gpr_or_gpr_p (operands[0], operands[1])

76143

+ && !direct_move_p (operands[0], operands[1])

76144

+ && !quad_load_store_p (operands[0], operands[1])"

76145

[(pc)]

76146

{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })

76147

76148

@@ -9651,7 +11339,7 @@

76149

(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]

76150

UNSPEC_TLSGD)

76151

(clobber (reg:SI LR_REGNO))]

76152

- "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"

76153

+ "HAVE_AS_TLS && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"

76154

{

76155

if (TARGET_CMODEL != CMODEL_SMALL)

76156

return "addis %0,%1,%2@got@tlsgd@ha\;addi %0,%0,%2@got@tlsgd@l\;"

76157

@@ -9723,7 +11411,7 @@

76158

(unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))

76159

(set (match_dup 0)

76160

(lo_sum:TLSmode (match_dup 3)

76161

- (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)))]

76162

+ (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))]

76163

"

76164

{

76165

operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);

76166

@@ -9746,7 +11434,8 @@

76167

(define_insn "*tls_gd_low<TLSmode:tls_abi_suffix>"

76168

[(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")

76169

(lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")

76170

- (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]

76171

+ (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")

76172

+ (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]

76173

UNSPEC_TLSGD)))]

76174

"HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"

76175

"addi %0,%1,%2@got@tlsgd@l"

76176

@@ -9759,7 +11448,8 @@

76177

(unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]

76178

UNSPEC_TLSGD)

76179

(clobber (reg:SI LR_REGNO))]

76180

- "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"

76181

+ "HAVE_AS_TLS && TARGET_TLS_MARKERS

76182

+ && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"

76183

"bl %z1(%3@tlsgd)\;nop"

76184

[(set_attr "type" "branch")

76185

(set_attr "length" "8")])

76186

@@ -9791,7 +11481,7 @@

76187

(unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]

76188

UNSPEC_TLSLD)

76189

(clobber (reg:SI LR_REGNO))]

76190

- "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"

76191

+ "HAVE_AS_TLS && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"

76192

{

76193

if (TARGET_CMODEL != CMODEL_SMALL)

76194

return "addis %0,%1,%&@got@tlsld@ha\;addi %0,%0,%&@got@tlsld@l\;"

76195

@@ -9858,7 +11548,7 @@

76196

(unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))

76197

(set (match_dup 0)

76198

(lo_sum:TLSmode (match_dup 2)

76199

- (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))]

76200

+ (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))]

76201

"

76202

{

76203

operands[2] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);

76204

@@ -9881,7 +11571,9 @@

76205

(define_insn "*tls_ld_low<TLSmode:tls_abi_suffix>"

76206

[(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")

76207

(lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")

76208

- (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))]

76209

+ (unspec:TLSmode [(const_int 0)

76210

+ (match_operand:TLSmode 2 "gpc_reg_operand" "b")]

76211

+ UNSPEC_TLSLD)))]

76212

"HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"

76213

"addi %0,%1,%&@got@tlsld@l"

76214

[(set_attr "length" "4")])

76215

@@ -9892,7 +11584,8 @@

76216

(match_operand 2 "" "g")))

76217

(unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)

76218

(clobber (reg:SI LR_REGNO))]

76219

- "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"

76220

+ "HAVE_AS_TLS && TARGET_TLS_MARKERS

76221

+ && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"

76222

"bl %z1(%&@tlsld)\;nop"

76223

[(set_attr "type" "branch")

76224

(set_attr "length" "8")])

76225

@@ -9953,7 +11646,7 @@

76226

(unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))

76227

(set (match_dup 0)

76228

(lo_sum:TLSmode (match_dup 3)

76229

- (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTDTPREL)))]

76230

+ (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))]

76231

"

76232

{

76233

operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);

76234

@@ -9976,7 +11669,8 @@

76235

(define_insn "*tls_got_dtprel_low<TLSmode:tls_abi_suffix>"

76236

[(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")

76237

(lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")

76238

- (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]

76239

+ (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")

76240

+ (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]

76241

UNSPEC_TLSGOTDTPREL)))]

76242

"HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"

76243

"l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel@l(%1)"

76244

@@ -10022,7 +11716,7 @@

76245

(unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))

76246

(set (match_dup 0)

76247

(lo_sum:TLSmode (match_dup 3)

76248

- (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTTPREL)))]

76249

+ (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))]

76250

"

76251

{

76252

operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);

76253

@@ -10045,7 +11739,8 @@

76254

(define_insn "*tls_got_tprel_low<TLSmode:tls_abi_suffix>"

76255

[(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")

76256

(lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")

76257

- (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]

76258

+ (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")

76259

+ (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]

76260

UNSPEC_TLSGOTTPREL)))]

76261

"HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"

76262

"l<TLSmode:tls_insn_suffix> %0,%2@got@tprel@l(%1)"

76263

@@ -10261,7 +11956,7 @@

76264

[(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")

76265

(unspec:SI [(const_int 0)] UNSPEC_TOC))

76266

(use (reg:SI 2))])]

76267

- "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"

76268

+ "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_32BIT"

76269

"*

76270

{

76271

char buf[30];

76272

@@ -10276,7 +11971,7 @@

76273

[(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")

76274

(unspec:DI [(const_int 0)] UNSPEC_TOC))

76275

(use (reg:DI 2))])]

76276

- "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"

76277

+ "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_64BIT"

76278

"*

76279

{

76280

char buf[30];

76281

@@ -10306,7 +12001,7 @@

76282

[(parallel [(set (reg:SI LR_REGNO)

76283

(match_operand:SI 0 "immediate_operand" "s"))

76284

(use (unspec [(match_dup 0)] UNSPEC_TOC))])]

76285

- "TARGET_ELF && DEFAULT_ABI != ABI_AIX

76286

+ "TARGET_ELF && DEFAULT_ABI == ABI_V4

76287

&& (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"

76288

"")

76289

76290

@@ -10314,7 +12009,7 @@

76291

[(set (reg:SI LR_REGNO)

76292

(match_operand:SI 0 "immediate_operand" "s"))

76293

(use (unspec [(match_dup 0)] UNSPEC_TOC))]

76294

- "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX

76295

+ "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4

76296

&& (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"

76297

"bcl 20,31,%0\\n%0:"

76298

[(set_attr "type" "branch")

76299

@@ -10324,7 +12019,7 @@

76300

[(set (reg:SI LR_REGNO)

76301

(match_operand:SI 0 "immediate_operand" "s"))

76302

(use (unspec [(match_dup 0)] UNSPEC_TOC))]

76303

- "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX

76304

+ "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4

76305

&& (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"

76306

"*

76307

{

76308

@@ -10344,7 +12039,7 @@

76309

(label_ref (match_operand 1 "" ""))]

76310

UNSPEC_TOCPTR))

76311

(match_dup 1)])]

76312

- "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"

76313

+ "TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"

76314

"")

76315

76316

(define_insn "load_toc_v4_PIC_1b_normal"

76317

@@ -10353,7 +12048,7 @@

76318

(label_ref (match_operand 1 "" ""))]

76319

UNSPEC_TOCPTR))

76320

(match_dup 1)]

76321

- "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"

76322

+ "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"

76323

"bcl 20,31,$+8\;.long %0-$"

76324

[(set_attr "type" "branch")

76325

(set_attr "length" "8")])

76326

@@ -10364,7 +12059,7 @@

76327

(label_ref (match_operand 1 "" ""))]

76328

UNSPEC_TOCPTR))

76329

(match_dup 1)]

76330

- "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"

76331

+ "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"

76332

"*

76333

{

76334

char name[32];

76335

@@ -10382,7 +12077,7 @@

76336

(mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")

76337

(minus:SI (match_operand:SI 2 "immediate_operand" "s")

76338

(match_operand:SI 3 "immediate_operand" "s")))))]

76339

- "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"

76340

+ "TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"

76341

"lwz %0,%2-%3(%1)"

76342

[(set_attr "type" "load")])

76343

76344

@@ -10392,7 +12087,7 @@

76345

(high:SI

76346

(minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")

76347

(match_operand:SI 3 "symbol_ref_operand" "s")))))]

76348

- "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"

76349

+ "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic"

76350

"addis %0,%1,%2-%3@ha")

76351

76352

(define_insn "load_toc_v4_PIC_3c"

76353

@@ -10400,7 +12095,7 @@

76354

(lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")

76355

(minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")

76356

(match_operand:SI 3 "symbol_ref_operand" "s"))))]

76357

- "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"

76358

+ "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic"

76359

"addi %0,%1,%2-%3@l")

76360

76361

;; If the TOC is shared over a translation unit, as happens with all

76362

@@ -10542,8 +12237,13 @@

76363

76364

operands[0] = XEXP (operands[0], 0);

76365

76366

+ if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)

76367

+ {

76368

+ rs6000_call_aix (NULL_RTX, operands[0], operands[1], operands[2]);

76369

+ DONE;

76370

+ }

76371

+

76372

if (GET_CODE (operands[0]) != SYMBOL_REF

76373

- || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))

76374

|| (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))

76375

{

76376

if (INTVAL (operands[2]) & CALL_LONG)

76377

@@ -10556,12 +12256,6 @@

76378

operands[0] = force_reg (Pmode, operands[0]);

76379

break;

76380

76381

- case ABI_AIX:

76382

- /* AIX function pointers are really pointers to a three word

76383

- area. */

76384

- rs6000_call_indirect_aix (NULL_RTX, operands[0], operands[1]);

76385

- DONE;

76386

-

76387

default:

76388

gcc_unreachable ();

76389

}

76390

@@ -10587,8 +12281,13 @@

76391

76392

operands[1] = XEXP (operands[1], 0);

76393

76394

+ if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)

76395

+ {

76396

+ rs6000_call_aix (operands[0], operands[1], operands[2], operands[3]);

76397

+ DONE;

76398

+ }

76399

+

76400

if (GET_CODE (operands[1]) != SYMBOL_REF

76401

- || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))

76402

|| (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))

76403

{

76404

if (INTVAL (operands[3]) & CALL_LONG)

76405

@@ -10601,12 +12300,6 @@

76406

operands[1] = force_reg (Pmode, operands[1]);

76407

break;

76408

76409

- case ABI_AIX:

76410

- /* AIX function pointers are really pointers to a three word

76411

- area. */

76412

- rs6000_call_indirect_aix (operands[0], operands[1], operands[2]);

76413

- DONE;

76414

-

76415

default:

76416

gcc_unreachable ();

76417

}

76418

@@ -10698,136 +12391,7 @@

76419

[(set_attr "type" "branch")

76420

(set_attr "length" "4,8")])

76421

76422

-;; Call to indirect functions with the AIX abi using a 3 word descriptor.

76423

-;; Operand0 is the addresss of the function to call

76424

-;; Operand1 is the flag for System V.4 for unprototyped or FP registers

76425

-;; Operand2 is the location in the function descriptor to load r2 from

76426

-;; Operand3 is the stack location to hold the current TOC pointer

76427

76428

-(define_insn "call_indirect_aix<ptrsize>"

76429

- [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))

76430

- (match_operand 1 "" "g,g"))

76431

- (use (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))

76432

- (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))

76433

- (use (reg:P STATIC_CHAIN_REGNUM))

76434

- (clobber (reg:P LR_REGNO))]

76435

- "DEFAULT_ABI == ABI_AIX && TARGET_POINTERS_TO_NESTED_FUNCTIONS"

76436

- "<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3"

76437

- [(set_attr "type" "jmpreg")

76438

- (set_attr "length" "12")])

76439

-

76440

-;; Like call_indirect_aix<ptrsize>, but no use of the static chain

76441

-;; Operand0 is the addresss of the function to call

76442

-;; Operand1 is the flag for System V.4 for unprototyped or FP registers

76443

-;; Operand2 is the location in the function descriptor to load r2 from

76444

-;; Operand3 is the stack location to hold the current TOC pointer

76445

-

76446

-(define_insn "call_indirect_aix<ptrsize>_nor11"

76447

- [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))

76448

- (match_operand 1 "" "g,g"))

76449

- (use (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))

76450

- (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))

76451

- (clobber (reg:P LR_REGNO))]

76452

- "DEFAULT_ABI == ABI_AIX && !TARGET_POINTERS_TO_NESTED_FUNCTIONS"

76453

- "<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3"

76454

- [(set_attr "type" "jmpreg")

76455

- (set_attr "length" "12")])

76456

-

76457

-;; Operand0 is the return result of the function

76458

-;; Operand1 is the addresss of the function to call

76459

-;; Operand2 is the flag for System V.4 for unprototyped or FP registers

76460

-;; Operand3 is the location in the function descriptor to load r2 from

76461

-;; Operand4 is the stack location to hold the current TOC pointer

76462

-

76463

-(define_insn "call_value_indirect_aix<ptrsize>"

76464

- [(set (match_operand 0 "" "")

76465

- (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))

76466

- (match_operand 2 "" "g,g")))

76467

- (use (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))

76468

- (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "<ptrm>,<ptrm>"))

76469

- (use (reg:P STATIC_CHAIN_REGNUM))

76470

- (clobber (reg:P LR_REGNO))]

76471

- "DEFAULT_ABI == ABI_AIX && TARGET_POINTERS_TO_NESTED_FUNCTIONS"

76472

- "<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4"

76473

- [(set_attr "type" "jmpreg")

76474

- (set_attr "length" "12")])

76475

-

76476

-;; Like call_value_indirect_aix<ptrsize>, but no use of the static chain

76477

-;; Operand0 is the return result of the function

76478

-;; Operand1 is the addresss of the function to call

76479

-;; Operand2 is the flag for System V.4 for unprototyped or FP registers

76480

-;; Operand3 is the location in the function descriptor to load r2 from

76481

-;; Operand4 is the stack location to hold the current TOC pointer

76482

-

76483

-(define_insn "call_value_indirect_aix<ptrsize>_nor11"

76484

- [(set (match_operand 0 "" "")

76485

- (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))

76486

- (match_operand 2 "" "g,g")))

76487

- (use (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))

76488

- (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "<ptrm>,<ptrm>"))

76489

- (clobber (reg:P LR_REGNO))]

76490

- "DEFAULT_ABI == ABI_AIX && !TARGET_POINTERS_TO_NESTED_FUNCTIONS"

76491

- "<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4"

76492

- [(set_attr "type" "jmpreg")

76493

- (set_attr "length" "12")])

76494

-

76495

-;; Call to function which may be in another module. Restore the TOC

76496

-;; pointer (r2) after the call unless this is System V.

76497

-;; Operand2 is nonzero if we are using the V.4 calling sequence and

76498

-;; either the function was not prototyped, or it was prototyped as a

76499

-;; variable argument function. It is > 0 if FP registers were passed

76500

-;; and < 0 if they were not.

76501

-

76502

-(define_insn "*call_nonlocal_aix32"

76503

- [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))

76504

- (match_operand 1 "" "g"))

76505

- (use (match_operand:SI 2 "immediate_operand" "O"))

76506

- (clobber (reg:SI LR_REGNO))]

76507

- "TARGET_32BIT

76508

- && DEFAULT_ABI == ABI_AIX

76509

- && (INTVAL (operands[2]) & CALL_LONG) == 0"

76510

- "bl %z0\;nop"

76511

- [(set_attr "type" "branch")

76512

- (set_attr "length" "8")])

76513

-

76514

-(define_insn "*call_nonlocal_aix64"

76515

- [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))

76516

- (match_operand 1 "" "g"))

76517

- (use (match_operand:SI 2 "immediate_operand" "O"))

76518

- (clobber (reg:SI LR_REGNO))]

76519

- "TARGET_64BIT

76520

- && DEFAULT_ABI == ABI_AIX

76521

- && (INTVAL (operands[2]) & CALL_LONG) == 0"

76522

- "bl %z0\;nop"

76523

- [(set_attr "type" "branch")

76524

- (set_attr "length" "8")])

76525

-

76526

-(define_insn "*call_value_nonlocal_aix32"

76527

- [(set (match_operand 0 "" "")

76528

- (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))

76529

- (match_operand 2 "" "g")))

76530

- (use (match_operand:SI 3 "immediate_operand" "O"))

76531

- (clobber (reg:SI LR_REGNO))]

76532

- "TARGET_32BIT

76533

- && DEFAULT_ABI == ABI_AIX

76534

- && (INTVAL (operands[3]) & CALL_LONG) == 0"

76535

- "bl %z1\;nop"

76536

- [(set_attr "type" "branch")

76537

- (set_attr "length" "8")])

76538

-

76539

-(define_insn "*call_value_nonlocal_aix64"

76540

- [(set (match_operand 0 "" "")

76541

- (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))

76542

- (match_operand 2 "" "g")))

76543

- (use (match_operand:SI 3 "immediate_operand" "O"))

76544

- (clobber (reg:SI LR_REGNO))]

76545

- "TARGET_64BIT

76546

- && DEFAULT_ABI == ABI_AIX

76547

- && (INTVAL (operands[3]) & CALL_LONG) == 0"

76548

- "bl %z1\;nop"

76549

- [(set_attr "type" "branch")

76550

- (set_attr "length" "8")])

76551

-

76552

;; A function pointer under System V is just a normal pointer

76553

;; operands[0] is the function pointer

76554

;; operands[1] is the stack size to clean up

76555

@@ -11009,6 +12573,104 @@

76556

[(set_attr "type" "branch,branch")

76557

(set_attr "length" "4,8")])

76558

76559

+

76560

+;; Call to AIX abi function in the same module.

76561

+

76562

+(define_insn "*call_local_aix<mode>"

76563

+ [(call (mem:SI (match_operand:P 0 "current_file_function_operand" "s"))

76564

+ (match_operand 1 "" "g"))

76565

+ (clobber (reg:P LR_REGNO))]

76566

+ "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"

76567

+ "bl %z0"

76568

+ [(set_attr "type" "branch")

76569

+ (set_attr "length" "4")])

76570

+

76571

+(define_insn "*call_value_local_aix<mode>"

76572

+ [(set (match_operand 0 "" "")

76573

+ (call (mem:SI (match_operand:P 1 "current_file_function_operand" "s"))

76574

+ (match_operand 2 "" "g")))

76575

+ (clobber (reg:P LR_REGNO))]

76576

+ "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"

76577

+ "bl %z1"

76578

+ [(set_attr "type" "branch")

76579

+ (set_attr "length" "4")])

76580

+

76581

+;; Call to AIX abi function which may be in another module.

76582

+;; Restore the TOC pointer (r2) after the call.

76583

+

76584

+(define_insn "*call_nonlocal_aix<mode>"

76585

+ [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s"))

76586

+ (match_operand 1 "" "g"))

76587

+ (clobber (reg:P LR_REGNO))]

76588

+ "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"

76589

+ "bl %z0\;nop"

76590

+ [(set_attr "type" "branch")

76591

+ (set_attr "length" "8")])

76592

+

76593

+(define_insn "*call_value_nonlocal_aix<mode>"

76594

+ [(set (match_operand 0 "" "")

76595

+ (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s"))

76596

+ (match_operand 2 "" "g")))

76597

+ (clobber (reg:P LR_REGNO))]

76598

+ "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"

76599

+ "bl %z1\;nop"

76600

+ [(set_attr "type" "branch")

76601

+ (set_attr "length" "8")])

76602

+

76603

+;; Call to indirect functions with the AIX abi using a 3 word descriptor.

76604

+;; Operand0 is the addresss of the function to call

76605

+;; Operand2 is the location in the function descriptor to load r2 from

76606

+;; Operand3 is the stack location to hold the current TOC pointer

76607

+

76608

+(define_insn "*call_indirect_aix<mode>"

76609

+ [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))

76610

+ (match_operand 1 "" "g,g"))

76611

+ (use (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))

76612

+ (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))

76613

+ (clobber (reg:P LR_REGNO))]

76614

+ "DEFAULT_ABI == ABI_AIX"

76615

+ "<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3"

76616

+ [(set_attr "type" "jmpreg")

76617

+ (set_attr "length" "12")])

76618

+

76619

+(define_insn "*call_value_indirect_aix<mode>"

76620

+ [(set (match_operand 0 "" "")

76621

+ (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))

76622

+ (match_operand 2 "" "g,g")))

76623

+ (use (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))

76624

+ (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "<ptrm>,<ptrm>"))

76625

+ (clobber (reg:P LR_REGNO))]

76626

+ "DEFAULT_ABI == ABI_AIX"

76627

+ "<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4"

76628

+ [(set_attr "type" "jmpreg")

76629

+ (set_attr "length" "12")])

76630

+

76631

+;; Call to indirect functions with the ELFv2 ABI.

76632

+;; Operand0 is the addresss of the function to call

76633

+;; Operand2 is the stack location to hold the current TOC pointer

76634

+

76635

+(define_insn "*call_indirect_elfv2<mode>"

76636

+ [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))

76637

+ (match_operand 1 "" "g,g"))

76638

+ (set (reg:P TOC_REGNUM) (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))

76639

+ (clobber (reg:P LR_REGNO))]

76640

+ "DEFAULT_ABI == ABI_ELFv2"

76641

+ "b%T0l\;<ptrload> 2,%2"

76642

+ [(set_attr "type" "jmpreg")

76643

+ (set_attr "length" "8")])

76644

+

76645

+(define_insn "*call_value_indirect_elfv2<mode>"

76646

+ [(set (match_operand 0 "" "")

76647

+ (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))

76648

+ (match_operand 2 "" "g,g")))

76649

+ (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))

76650

+ (clobber (reg:P LR_REGNO))]

76651

+ "DEFAULT_ABI == ABI_ELFv2"

76652

+ "b%T1l\;<ptrload> 2,%3"

76653

+ [(set_attr "type" "jmpreg")

76654

+ (set_attr "length" "8")])

76655

+

76656

+

76657

;; Call subroutine returning any type.

76658

(define_expand "untyped_call"

76659

[(parallel [(call (match_operand 0 "" "")

76660

@@ -11056,8 +12718,41 @@

76661

gcc_assert (GET_CODE (operands[1]) == CONST_INT);

76662

76663

operands[0] = XEXP (operands[0], 0);

76664

+

76665

+ if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)

76666

+ {

76667

+ rs6000_sibcall_aix (NULL_RTX, operands[0], operands[1], operands[2]);

76668

+ DONE;

76669

+ }

76670

}")

76671

76672

+(define_expand "sibcall_value"

76673

+ [(parallel [(set (match_operand 0 "register_operand" "")

76674

+ (call (mem:SI (match_operand 1 "address_operand" ""))

76675

+ (match_operand 2 "" "")))

76676

+ (use (match_operand 3 "" ""))

76677

+ (use (reg:SI LR_REGNO))

76678

+ (simple_return)])]

76679

+ ""

76680

+ "

76681

+{

76682

+#if TARGET_MACHO

76683

+ if (MACHOPIC_INDIRECT)

76684

+ operands[1] = machopic_indirect_call_target (operands[1]);

76685

+#endif

76686

+

76687

+ gcc_assert (GET_CODE (operands[1]) == MEM);

76688

+ gcc_assert (GET_CODE (operands[2]) == CONST_INT);

76689

+

76690

+ operands[1] = XEXP (operands[1], 0);

76691

+

76692

+ if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)

76693

+ {

76694

+ rs6000_sibcall_aix (operands[0], operands[1], operands[2], operands[3]);

76695

+ DONE;

76696

+ }

76697

+}")

76698

+

76699

;; this and similar patterns must be marked as using LR, otherwise

76700

;; dataflow will try to delete the store into it. This is true

76701

;; even when the actual reg to jump to is in CTR, when LR was

76702

@@ -11123,7 +12818,6 @@

76703

[(set_attr "type" "branch")

76704

(set_attr "length" "4,8")])

76705

76706

-

76707

(define_insn "*sibcall_value_local64"

76708

[(set (match_operand 0 "" "")

76709

(call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))

76710

@@ -11145,35 +12839,6 @@

76711

[(set_attr "type" "branch")

76712

(set_attr "length" "4,8")])

76713

76714

-(define_insn "*sibcall_nonlocal_aix<mode>"

76715

- [(call (mem:SI (match_operand:P 0 "call_operand" "s,c"))

76716

- (match_operand 1 "" "g,g"))

76717

- (use (match_operand:SI 2 "immediate_operand" "O,O"))

76718

- (use (reg:SI LR_REGNO))

76719

- (simple_return)]

76720

- "DEFAULT_ABI == ABI_AIX

76721

- && (INTVAL (operands[2]) & CALL_LONG) == 0"

76722

- "@

76723

- b %z0

76724

- b%T0"

76725

- [(set_attr "type" "branch")

76726

- (set_attr "length" "4")])

76727

-

76728

-(define_insn "*sibcall_value_nonlocal_aix<mode>"

76729

- [(set (match_operand 0 "" "")

76730

- (call (mem:SI (match_operand:P 1 "call_operand" "s,c"))

76731

- (match_operand 2 "" "g,g")))

76732

- (use (match_operand:SI 3 "immediate_operand" "O,O"))

76733

- (use (reg:SI LR_REGNO))

76734

- (simple_return)]

76735

- "DEFAULT_ABI == ABI_AIX

76736

- && (INTVAL (operands[3]) & CALL_LONG) == 0"

76737

- "@

76738

- b %z1

76739

- b%T1"

76740

- [(set_attr "type" "branch")

76741

- (set_attr "length" "4")])

76742

-

76743

(define_insn "*sibcall_nonlocal_sysv<mode>"

76744

[(call (mem:SI (match_operand:P 0 "call_operand" "s,s,c,c"))

76745

(match_operand 1 "" ""))

76746

@@ -11204,27 +12869,6 @@

76747

[(set_attr "type" "branch")

76748

(set_attr "length" "4,8,4,8")])

76749

76750

-(define_expand "sibcall_value"

76751

- [(parallel [(set (match_operand 0 "register_operand" "")

76752

- (call (mem:SI (match_operand 1 "address_operand" ""))

76753

- (match_operand 2 "" "")))

76754

- (use (match_operand 3 "" ""))

76755

- (use (reg:SI LR_REGNO))

76756

- (simple_return)])]

76757

- ""

76758

- "

76759

-{

76760

-#if TARGET_MACHO

76761

- if (MACHOPIC_INDIRECT)

76762

- operands[1] = machopic_indirect_call_target (operands[1]);

76763

-#endif

76764

-

76765

- gcc_assert (GET_CODE (operands[1]) == MEM);

76766

- gcc_assert (GET_CODE (operands[2]) == CONST_INT);

76767

-

76768

- operands[1] = XEXP (operands[1], 0);

76769

-}")

76770

-

76771

(define_insn "*sibcall_value_nonlocal_sysv<mode>"

76772

[(set (match_operand 0 "" "")

76773

(call (mem:SI (match_operand:P 1 "call_operand" "s,s,c,c"))

76774

@@ -11256,6 +12900,31 @@

76775

[(set_attr "type" "branch")

76776

(set_attr "length" "4,8,4,8")])

76777

76778

+;; AIX ABI sibling call patterns.

76779

+

76780

+(define_insn "*sibcall_aix<mode>"

76781

+ [(call (mem:SI (match_operand:P 0 "call_operand" "s,c"))

76782

+ (match_operand 1 "" "g,g"))

76783

+ (simple_return)]

76784

+ "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"

76785

+ "@

76786

+ b %z0

76787

+ b%T0"

76788

+ [(set_attr "type" "branch")

76789

+ (set_attr "length" "4")])

76790

+

76791

+(define_insn "*sibcall_value_aix<mode>"

76792

+ [(set (match_operand 0 "" "")

76793

+ (call (mem:SI (match_operand:P 1 "call_operand" "s,c"))

76794

+ (match_operand 2 "" "g,g")))

76795

+ (simple_return)]

76796

+ "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"

76797

+ "@

76798

+ b %z1

76799

+ b%T1"

76800

+ [(set_attr "type" "branch")

76801

+ (set_attr "length" "4")])

76802

+

76803

(define_expand "sibcall_epilogue"

76804

[(use (const_int 0))]

76805

""

76806

@@ -11294,7 +12963,14 @@

76807

operands[1] = gen_rtx_REG (Pmode, 0);

76808

return "st<wd>%U0%X0 %1,%0";

76809

}

76810

- [(set_attr "type" "store")

76811

+ [(set (attr "type")

76812

+ (if_then_else

76813

+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")

76814

+ (const_string "store_ux")

76815

+ (if_then_else

76816

+ (match_test "update_address_mem (operands[0], VOIDmode)")

76817

+ (const_string "store_u")

76818

+ (const_string "store"))))

76819

(set_attr "length" "4")])

76820

76821

(define_insn "probe_stack_range<P:mode>"

76822

@@ -11589,23 +13265,6 @@

76823

[(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))

76824

(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])

76825

76826

-(define_insn "*cmpsf_internal1"

76827

- [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")

76828

- (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")

76829

- (match_operand:SF 2 "gpc_reg_operand" "f")))]

76830

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"

76831

- "fcmpu %0,%1,%2"

76832

- [(set_attr "type" "fpcompare")])

76833

-

76834

-(define_insn "*cmpdf_internal1"

76835

- [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")

76836

- (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "d")

76837

- (match_operand:DF 2 "gpc_reg_operand" "d")))]

76838

- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT

76839

- && !VECTOR_UNIT_VSX_P (DFmode)"

76840

- "fcmpu %0,%1,%2"

76841

- [(set_attr "type" "fpcompare")])

76842

-

76843

;; Only need to compare second words if first words equal

76844

(define_insn "*cmptf_internal1"

76845

[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")

76846

@@ -13501,6 +15160,14 @@

76847

"mfcr %0"

76848

[(set_attr "type" "mfcr")])

76849

76850

+(define_insn "*crsave"

76851

+ [(match_parallel 0 "crsave_operation"

76852

+ [(set (match_operand:SI 1 "memory_operand" "=m")

76853

+ (match_operand:SI 2 "gpc_reg_operand" "r"))])]

76854

+ ""

76855

+ "stw %2,%1"

76856

+ [(set_attr "type" "store")])

76857

+

76858

(define_insn "*stmw"

76859

[(match_parallel 0 "stmw_operation"

76860

[(set (match_operand:SI 1 "memory_operand" "=m")

76861

@@ -13885,7 +15552,7 @@

76862

(match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]

76863

"TARGET_POPCNTD"

76864

"bpermd %0,%1,%2"

76865

- [(set_attr "type" "integer")])

76866

+ [(set_attr "type" "popcnt")])

76867

76868

76869

;; Builtin fma support. Handle

76870

@@ -13900,6 +15567,20 @@

76871

""

76872

"")

76873

76874

+(define_insn "*fma<mode>4_fpr"

76875

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")

76876

+ (fma:SFDF

76877

+ (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>,<Fv>")

76878

+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")

76879

+ (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>")))]

76880

+ "TARGET_<MODE>_FPR"

76881

+ "@

76882

+ fmadd<Ftrad> %0,%1,%2,%3

76883

+ xsmadda<Fvsx> %x0,%x1,%x2

76884

+ xsmaddm<Fvsx> %x0,%x1,%x3"

76885

+ [(set_attr "type" "fp")

76886

+ (set_attr "fp_type" "fp_maddsub_<Fs>")])

76887

+

76888

; Altivec only has fma and nfms.

76889

(define_expand "fms<mode>4"

76890

[(set (match_operand:FMA_F 0 "register_operand" "")

76891

@@ -13910,6 +15591,20 @@

76892

"!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"

76893

"")

76894

76895

+(define_insn "*fms<mode>4_fpr"

76896

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")

76897

+ (fma:SFDF

76898

+ (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")

76899

+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")

76900

+ (neg:SFDF (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>"))))]

76901

+ "TARGET_<MODE>_FPR"

76902

+ "@

76903

+ fmsub<Ftrad> %0,%1,%2,%3

76904

+ xsmsuba<Fvsx> %x0,%x1,%x2

76905

+ xsmsubm<Fvsx> %x0,%x1,%x3"

76906

+ [(set_attr "type" "fp")

76907

+ (set_attr "fp_type" "fp_maddsub_<Fs>")])

76908

+

76909

;; If signed zeros are ignored, -(a * b - c) = -a * b + c.

76910

(define_expand "fnma<mode>4"

76911

[(set (match_operand:FMA_F 0 "register_operand" "")

76912

@@ -13943,6 +15638,21 @@

76913

"!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"

76914

"")

76915

76916

+(define_insn "*nfma<mode>4_fpr"

76917

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")

76918

+ (neg:SFDF

76919

+ (fma:SFDF

76920

+ (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")

76921

+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")

76922

+ (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>"))))]

76923

+ "TARGET_<MODE>_FPR"

76924

+ "@

76925

+ fnmadd<Ftrad> %0,%1,%2,%3

76926

+ xsnmadda<Fvsx> %x0,%x1,%x2

76927

+ xsnmaddm<Fvsx> %x0,%x1,%x3"

76928

+ [(set_attr "type" "fp")

76929

+ (set_attr "fp_type" "fp_maddsub_<Fs>")])

76930

+

76931

; Not an official optab name, but used from builtins.

76932

(define_expand "nfms<mode>4"

76933

[(set (match_operand:FMA_F 0 "register_operand" "")

76934

@@ -13954,6 +15664,23 @@

76935

""

76936

"")

76937

76938

+(define_insn "*nfmssf4_fpr"

76939

+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")

76940

+ (neg:SFDF

76941

+ (fma:SFDF

76942

+ (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")

76943

+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")

76944

+ (neg:SFDF

76945

+ (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>")))))]

76946

+ "TARGET_<MODE>_FPR"

76947

+ "@

76948

+ fnmsub<Ftrad> %0,%1,%2,%3

76949

+ xsnmsuba<Fvsx> %x0,%x1,%x2

76950

+ xsnmsubm<Fvsx> %x0,%x1,%x3"

76951

+ [(set_attr "type" "fp")

76952

+ (set_attr "fp_type" "fp_maddsub_<Fs>")])

76953

+

76954

+

76955

(define_expand "rs6000_get_timebase"

76956

[(use (match_operand:DI 0 "gpc_reg_operand" ""))]

76957

""

76958

@@ -14020,7 +15747,229 @@

76959

})

76960

76961

76962

+;; Power8 fusion support for fusing an addis instruction with a D-form load of

76963

+;; a GPR. The addis instruction must be adjacent to the load, and use the same

76964

+;; register that is being loaded. The fused ops must be physically adjacent.

76965

76966

+;; We use define_peephole for the actual addis/load, and the register used to

76967

+;; hold the addis value must be the same as the register being loaded. We use

76968

+;; define_peephole2 to change the register used for addis to be the register

76969

+;; being loaded, since we can look at whether it is dead after the load insn.

76970

+

76971

+(define_peephole

76972

+ [(set (match_operand:P 0 "base_reg_operand" "")

76973

+ (match_operand:P 1 "fusion_gpr_addis" ""))

76974

+ (set (match_operand:INT1 2 "base_reg_operand" "")

76975

+ (match_operand:INT1 3 "fusion_gpr_mem_load" ""))]

76976

+ "TARGET_P8_FUSION && fusion_gpr_load_p (operands, false)"

76977

+{

76978

+ return emit_fusion_gpr_load (operands);

76979

+}

76980

+ [(set_attr "type" "load")

76981

+ (set_attr "length" "8")])

76982

+

76983

+(define_peephole2

76984

+ [(set (match_operand:P 0 "base_reg_operand" "")

76985

+ (match_operand:P 1 "fusion_gpr_addis" ""))

76986

+ (set (match_operand:INT1 2 "base_reg_operand" "")

76987

+ (match_operand:INT1 3 "fusion_gpr_mem_load" ""))]

76988

+ "TARGET_P8_FUSION

76989

+ && (REGNO (operands[0]) != REGNO (operands[2])

76990

+ || GET_CODE (operands[3]) == SIGN_EXTEND)

76991

+ && fusion_gpr_load_p (operands, true)"

76992

+ [(const_int 0)]

76993

+{

76994

+ expand_fusion_gpr_load (operands);

76995

+ DONE;

76996

+})

76997

+

76998

+

76999

+;; Miscellaneous ISA 2.06 (power7) instructions

77000

+(define_insn "addg6s"

77001

+ [(set (match_operand:SI 0 "register_operand" "=r")

77002

+ (unspec:SI [(match_operand:SI 1 "register_operand" "r")

77003

+ (match_operand:SI 2 "register_operand" "r")]

77004

+ UNSPEC_ADDG6S))]

77005

+ "TARGET_POPCNTD"

77006

+ "addg6s %0,%1,%2"

77007

+ [(set_attr "type" "integer")

77008

+ (set_attr "length" "4")])

77009

+

77010

+(define_insn "cdtbcd"

77011

+ [(set (match_operand:SI 0 "register_operand" "=r")

77012

+ (unspec:SI [(match_operand:SI 1 "register_operand" "r")]

77013

+ UNSPEC_CDTBCD))]

77014

+ "TARGET_POPCNTD"

77015

+ "cdtbcd %0,%1"

77016

+ [(set_attr "type" "integer")

77017

+ (set_attr "length" "4")])

77018

+

77019

+(define_insn "cbcdtd"

77020

+ [(set (match_operand:SI 0 "register_operand" "=r")

77021

+ (unspec:SI [(match_operand:SI 1 "register_operand" "r")]

77022

+ UNSPEC_CBCDTD))]

77023

+ "TARGET_POPCNTD"

77024

+ "cbcdtd %0,%1"

77025

+ [(set_attr "type" "integer")

77026

+ (set_attr "length" "4")])

77027

+

77028

+(define_int_iterator UNSPEC_DIV_EXTEND [UNSPEC_DIVE

77029

+ UNSPEC_DIVEO

77030

+ UNSPEC_DIVEU

77031

+ UNSPEC_DIVEUO])

77032

+

77033

+(define_int_attr div_extend [(UNSPEC_DIVE "e")

77034

+ (UNSPEC_DIVEO "eo")

77035

+ (UNSPEC_DIVEU "eu")

77036

+ (UNSPEC_DIVEUO "euo")])

77037

+

77038

+(define_insn "div<div_extend>_<mode>"

77039

+ [(set (match_operand:GPR 0 "register_operand" "=r")

77040

+ (unspec:GPR [(match_operand:GPR 1 "register_operand" "r")

77041

+ (match_operand:GPR 2 "register_operand" "r")]

77042

+ UNSPEC_DIV_EXTEND))]

77043

+ "TARGET_POPCNTD"

77044

+ "div<wd><div_extend> %0,%1,%2"

77045

+ [(set_attr "type" "<idiv_ldiv>")])

77046

+

77047

+

77048

+;; Pack/unpack 128-bit floating point types that take 2 scalar registers

77049

+

77050

+; Type of the 64-bit part when packing/unpacking 128-bit floating point types

77051

+(define_mode_attr FP128_64 [(TF "DF") (TD "DI")])

77052

+

77053

+(define_expand "unpack<mode>"

77054

+ [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "")

77055

+ (unspec:<FP128_64>

77056

+ [(match_operand:FMOVE128 1 "register_operand" "")

77057

+ (match_operand:QI 2 "const_0_to_1_operand" "")]

77058

+ UNSPEC_UNPACK_128BIT))]

77059

+ ""

77060

+ "")

77061

+

77062

+;; The Advance Toolchain 7.0-3 added private builtins: __builtin_longdouble_dw0

77063

+;; and __builtin_longdouble_dw1 to optimize glibc. Add support for these

77064

+;; builtins here.

77065

+

77066

+(define_expand "unpacktf_0"

77067

+ [(set (match_operand:DF 0 "nonimmediate_operand" "")

77068

+ (unspec:DF [(match_operand:TF 1 "register_operand" "")

77069

+ (const_int 0)]

77070

+ UNSPEC_UNPACK_128BIT))]

77071

+ ""

77072

+ "")

77073

+

77074

+(define_expand "unpacktf_1"

77075

+ [(set (match_operand:DF 0 "nonimmediate_operand" "")

77076

+ (unspec:DF [(match_operand:TF 1 "register_operand" "")

77077

+ (const_int 1)]

77078

+ UNSPEC_UNPACK_128BIT))]

77079

+ ""

77080

+ "")

77081

+

77082

+(define_insn_and_split "unpack<mode>_dm"

77083

+ [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m,d,r,m")

77084

+ (unspec:<FP128_64>

77085

+ [(match_operand:FMOVE128 1 "register_operand" "d,d,r,d,r")

77086

+ (match_operand:QI 2 "const_0_to_1_operand" "i,i,i,i,i")]

77087

+ UNSPEC_UNPACK_128BIT))]

77088

+ "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"

77089

+ "#"

77090

+ "&& reload_completed"

77091

+ [(set (match_dup 0) (match_dup 3))]

77092

+{

77093

+ unsigned fp_regno = REGNO (operands[1]) + UINTVAL (operands[2]);

77094

+

77095

+ if (REG_P (operands[0]) && REGNO (operands[0]) == fp_regno)

77096

+ {

77097

+ emit_note (NOTE_INSN_DELETED);

77098

+ DONE;

77099

+ }

77100

+

77101

+ operands[3] = gen_rtx_REG (<FP128_64>mode, fp_regno);

77102

+}

77103

+ [(set_attr "type" "fp,fpstore,mffgpr,mftgpr,store")

77104

+ (set_attr "length" "4")])

77105

+

77106

+(define_insn_and_split "unpack<mode>_nodm"

77107

+ [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m")

77108

+ (unspec:<FP128_64>

77109

+ [(match_operand:FMOVE128 1 "register_operand" "d,d")

77110

+ (match_operand:QI 2 "const_0_to_1_operand" "i,i")]

77111

+ UNSPEC_UNPACK_128BIT))]

77112

+ "!TARGET_POWERPC64 || !TARGET_DIRECT_MOVE"

77113

+ "#"

77114

+ "&& reload_completed"

77115

+ [(set (match_dup 0) (match_dup 3))]

77116

+{

77117

+ unsigned fp_regno = REGNO (operands[1]) + UINTVAL (operands[2]);

77118

+

77119

+ if (REG_P (operands[0]) && REGNO (operands[0]) == fp_regno)

77120

+ {

77121

+ emit_note (NOTE_INSN_DELETED);

77122

+ DONE;

77123

+ }

77124

+

77125

+ operands[3] = gen_rtx_REG (<FP128_64>mode, fp_regno);

77126

+}

77127

+ [(set_attr "type" "fp,fpstore")

77128

+ (set_attr "length" "4")])

77129

+

77130

+(define_insn_and_split "pack<mode>"

77131

+ [(set (match_operand:FMOVE128 0 "register_operand" "=d,&d")

77132

+ (unspec:FMOVE128

77133

+ [(match_operand:<FP128_64> 1 "register_operand" "0,d")

77134

+ (match_operand:<FP128_64> 2 "register_operand" "d,d")]

77135

+ UNSPEC_PACK_128BIT))]

77136

+ ""

77137

+ "@

77138

+ fmr %L0,%2

77139

+ #"

77140

+ "&& reload_completed && REGNO (operands[0]) != REGNO (operands[1])"

77141

+ [(set (match_dup 3) (match_dup 1))

77142

+ (set (match_dup 4) (match_dup 2))]

77143

+{

77144

+ unsigned dest_hi = REGNO (operands[0]);

77145

+ unsigned dest_lo = dest_hi + 1;

77146

+

77147

+ gcc_assert (!IN_RANGE (REGNO (operands[1]), dest_hi, dest_lo));

77148

+ gcc_assert (!IN_RANGE (REGNO (operands[2]), dest_hi, dest_lo));

77149

+

77150

+ operands[3] = gen_rtx_REG (<FP128_64>mode, dest_hi);

77151

+ operands[4] = gen_rtx_REG (<FP128_64>mode, dest_lo);

77152

+}

77153

+ [(set_attr "type" "fp,fp")

77154

+ (set_attr "length" "4,8")])

77155

+

77156

+(define_insn "unpackv1ti"

77157

+ [(set (match_operand:DI 0 "register_operand" "=d,d")

77158

+ (unspec:DI [(match_operand:V1TI 1 "register_operand" "0,wa")

77159

+ (match_operand:QI 2 "const_0_to_1_operand" "O,i")]

77160

+ UNSPEC_UNPACK_128BIT))]

77161

+ "TARGET_VSX"

77162

+{

77163

+ if (REGNO (operands[0]) == REGNO (operands[1]) && INTVAL (operands[2]) == 0)

77164

+ return ASM_COMMENT_START " xxpermdi to same register";

77165

+

77166

+ operands[3] = GEN_INT (INTVAL (operands[2]) == 0 ? 0 : 3);

77167

+ return "xxpermdi %x0,%x1,%x1,%3";

77168

+}

77169

+ [(set_attr "type" "vecperm")

77170

+ (set_attr "length" "4")])

77171

+

77172

+(define_insn "packv1ti"

77173

+ [(set (match_operand:V1TI 0 "register_operand" "=wa")

77174

+ (unspec:V1TI

77175

+ [(match_operand:DI 1 "register_operand" "d")

77176

+ (match_operand:DI 2 "register_operand" "d")]

77177

+ UNSPEC_PACK_128BIT))]

77178

+ "TARGET_VSX"

77179

+ "xxpermdi %x0,%x1,%x2,0"

77180

+ [(set_attr "type" "vecperm")

77181

+ (set_attr "length" "4")])

77182

+

77183

+

77184

+

77185

(include "sync.md")

77186

(include "vector.md")

77187

(include "vsx.md")

77188

@@ -14028,3 +15977,5 @@

77189

(include "spe.md")

77190

(include "dfp.md")

77191

(include "paired.md")

77192

+(include "crypto.md")

77193

+(include "htm.md")

77194

Index: gcc/config/rs6000/t-linux64le

77195

===================================================================

77196

--- a/src/gcc/config/rs6000/t-linux64le (.../tags/gcc_4_8_2_release)

77197

+++ b/src/gcc/config/rs6000/t-linux64le (.../branches/gcc-4_8-branch)

77198

@@ -0,0 +1,3 @@

77199

+#rs6000/t-linux64le

77200

+

77201

+MULTILIB_OSDIRNAMES := $(subst -linux,le-linux,$(MULTILIB_OSDIRNAMES))

77202

Index: gcc/config/rs6000/t-linux64lebe

77203

===================================================================

77204

--- a/src/gcc/config/rs6000/t-linux64lebe (.../tags/gcc_4_8_2_release)

77205

+++ b/src/gcc/config/rs6000/t-linux64lebe (.../branches/gcc-4_8-branch)

77206

@@ -0,0 +1,7 @@

77207

+#rs6000/t-linux64leend

77208

+

77209

+MULTILIB_OPTIONS += mbig

77210

+MULTILIB_DIRNAMES += be

77211

+MULTILIB_OSDIRNAMES += $(subst =,.mbig=,$(subst libbe32,lib32be,$(subst libbe64,lib64be,$(subst lib,libbe,$(subst le-linux,-linux,$(MULTILIB_OSDIRNAMES))))))

77212

+MULTILIB_OSDIRNAMES += $(subst $(if $(findstring 64,$(target)),m64,m32).,,$(filter $(if $(findstring 64,$(target)),m64,m32).mbig%,$(MULTILIB_OSDIRNAMES)))

77213

+MULTILIB_MATCHES := ${MULTILIB_MATCHES_ENDIAN}

77214

Index: gcc/config/rs6000/rs6000-opts.h

77215

===================================================================

77216

--- a/src/gcc/config/rs6000/rs6000-opts.h (.../tags/gcc_4_8_2_release)

77217

+++ b/src/gcc/config/rs6000/rs6000-opts.h (.../branches/gcc-4_8-branch)

77218

@@ -59,7 +59,8 @@

77219

PROCESSOR_POWER7,

77220

PROCESSOR_CELL,

77221

PROCESSOR_PPCA2,

77222

- PROCESSOR_TITAN

77223

+ PROCESSOR_TITAN,

77224

+ PROCESSOR_POWER8

77225

};

77226

77227

/* FP processor type. */

77228

@@ -100,7 +101,8 @@

77229

/* Enumeration to give which calling sequence to use. */

77230

enum rs6000_abi {

77231

ABI_NONE,

77232

- ABI_AIX, /* IBM's AIX */

77233

+ ABI_AIX, /* IBM's AIX, or Linux ELFv1 */

77234

+ ABI_ELFv2, /* Linux ELFv2 ABI */

77235

ABI_V4, /* System V.4/eabi */

77236

ABI_DARWIN /* Apple's Darwin (OS X kernel) */

77237

};

77238

@@ -131,11 +133,14 @@

77239

CMODEL_LARGE

77240

};

77241

77242

-/* Describe which vector unit to use for a given machine mode. */

77243

+/* Describe which vector unit to use for a given machine mode. The

77244

+ VECTOR_MEM_* and VECTOR_UNIT_* macros assume that Altivec, VSX, and

77245

+ P8_VECTOR are contiguous. */

77246

enum rs6000_vector {

77247

VECTOR_NONE, /* Type is not a vector or not supported */

77248

VECTOR_ALTIVEC, /* Use altivec for vector processing */

77249

VECTOR_VSX, /* Use VSX for vector processing */

77250

+ VECTOR_P8_VECTOR, /* Use ISA 2.07 VSX for vector processing */

77251

VECTOR_PAIRED, /* Use paired floating point for vectors */

77252

VECTOR_SPE, /* Use SPE for vector processing */

77253

VECTOR_OTHER /* Some other vector unit */

77254

Index: gcc/config/rs6000/option-defaults.h

77255

===================================================================

77256

--- a/src/gcc/config/rs6000/option-defaults.h (.../tags/gcc_4_8_2_release)

77257

+++ b/src/gcc/config/rs6000/option-defaults.h (.../branches/gcc-4_8-branch)

77258

@@ -54,6 +54,7 @@

77259

--with-float is ignored if -mhard-float or -msoft-float are

77260

specified. */

77261

#define OPTION_DEFAULT_SPECS \

77262

+ {"abi", "%{!mabi=elfv*:-mabi=%(VALUE)}" }, \

77263

{"tune", "%{!mtune=*:%{!mcpu=*:-mtune=%(VALUE)}}" }, \

77264

{"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:-mtune=%(VALUE)}}}" }, \

77265

{"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:-mtune=%(VALUE)}}}" }, \

77266

Index: gcc/config/rs6000/altivec.h

77267

===================================================================

77268

--- a/src/gcc/config/rs6000/altivec.h (.../tags/gcc_4_8_2_release)

77269

+++ b/src/gcc/config/rs6000/altivec.h (.../branches/gcc-4_8-branch)

77270

@@ -319,8 +319,58 @@

77271

#define vec_sqrt __builtin_vec_sqrt

77272

#define vec_vsx_ld __builtin_vec_vsx_ld

77273

#define vec_vsx_st __builtin_vec_vsx_st

77274

+

77275

+/* Note, xxsldi and xxpermdi were added as __builtin_vsx_<xxx> functions

77276

+ instead of __builtin_vec_<xxx> */

77277

+#define vec_xxsldwi __builtin_vsx_xxsldwi

77278

+#define vec_xxpermdi __builtin_vsx_xxpermdi

77279

#endif

77280

77281

+#ifdef _ARCH_PWR8

77282

+/* Vector additions added in ISA 2.07. */

77283

+#define vec_eqv __builtin_vec_eqv

77284

+#define vec_nand __builtin_vec_nand

77285

+#define vec_orc __builtin_vec_orc

77286

+#define vec_vaddcuq __builtin_vec_vaddcuq

77287

+#define vec_vaddudm __builtin_vec_vaddudm

77288

+#define vec_vadduqm __builtin_vec_vadduqm

77289

+#define vec_vbpermq __builtin_vec_vbpermq

77290

+#define vec_vclz __builtin_vec_vclz

77291

+#define vec_vclzb __builtin_vec_vclzb

77292

+#define vec_vclzd __builtin_vec_vclzd

77293

+#define vec_vclzh __builtin_vec_vclzh

77294

+#define vec_vclzw __builtin_vec_vclzw

77295

+#define vec_vaddecuq __builtin_vec_vaddecuq

77296

+#define vec_vaddeuqm __builtin_vec_vaddeuqm

77297

+#define vec_vsubecuq __builtin_vec_vsubecuq

77298

+#define vec_vsubeuqm __builtin_vec_vsubeuqm

77299

+#define vec_vgbbd __builtin_vec_vgbbd

77300

+#define vec_vmaxsd __builtin_vec_vmaxsd

77301

+#define vec_vmaxud __builtin_vec_vmaxud

77302

+#define vec_vminsd __builtin_vec_vminsd

77303

+#define vec_vminud __builtin_vec_vminud

77304

+#define vec_vmrgew __builtin_vec_vmrgew

77305

+#define vec_vmrgow __builtin_vec_vmrgow

77306

+#define vec_vpksdss __builtin_vec_vpksdss

77307

+#define vec_vpksdus __builtin_vec_vpksdus

77308

+#define vec_vpkudum __builtin_vec_vpkudum

77309

+#define vec_vpkudus __builtin_vec_vpkudus

77310

+#define vec_vpopcnt __builtin_vec_vpopcnt

77311

+#define vec_vpopcntb __builtin_vec_vpopcntb

77312

+#define vec_vpopcntd __builtin_vec_vpopcntd

77313

+#define vec_vpopcnth __builtin_vec_vpopcnth

77314

+#define vec_vpopcntw __builtin_vec_vpopcntw

77315

+#define vec_vrld __builtin_vec_vrld

77316

+#define vec_vsld __builtin_vec_vsld

77317

+#define vec_vsrad __builtin_vec_vsrad

77318

+#define vec_vsrd __builtin_vec_vsrd

77319

+#define vec_vsubcuq __builtin_vec_vsubcuq

77320

+#define vec_vsubudm __builtin_vec_vsubudm

77321

+#define vec_vsubuqm __builtin_vec_vsubuqm

77322

+#define vec_vupkhsw __builtin_vec_vupkhsw

77323

+#define vec_vupklsw __builtin_vec_vupklsw

77324

+#endif

77325

+

77326

/* Predicates.

77327

For C++, we use templates in order to allow non-parenthesized arguments.

77328

For C, instead, we use macros since non-parenthesized arguments were

77329

Index: gcc/config/rs6000/sysv4.h

77330

===================================================================

77331

--- a/src/gcc/config/rs6000/sysv4.h (.../tags/gcc_4_8_2_release)

77332

+++ b/src/gcc/config/rs6000/sysv4.h (.../branches/gcc-4_8-branch)

77333

@@ -45,7 +45,7 @@

77334

& (OPTION_MASK_RELOCATABLE \

77335

| OPTION_MASK_MINIMAL_TOC)) \

77336

&& flag_pic > 1) \

77337

- || DEFAULT_ABI == ABI_AIX)

77338

+ || DEFAULT_ABI != ABI_V4)

77339

77340

#define TARGET_BITFIELD_TYPE (! TARGET_NO_BITFIELD_TYPE)

77341

#define TARGET_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN)

77342

@@ -147,7 +147,7 @@

77343

rs6000_sdata_name); \

77344

} \

77345

\

77346

- else if (flag_pic && DEFAULT_ABI != ABI_AIX \

77347

+ else if (flag_pic && DEFAULT_ABI == ABI_V4 \

77348

&& (rs6000_sdata == SDATA_EABI \

77349

|| rs6000_sdata == SDATA_SYSV)) \

77350

{ \

77351

@@ -173,7 +173,7 @@

77352

error ("-mrelocatable and -mno-minimal-toc are incompatible"); \

77353

} \

77354

\

77355

- if (TARGET_RELOCATABLE && rs6000_current_abi == ABI_AIX) \

77356

+ if (TARGET_RELOCATABLE && rs6000_current_abi != ABI_V4) \

77357

{ \

77358

rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE; \

77359

error ("-mrelocatable and -mcall-%s are incompatible", \

77360

@@ -180,7 +180,7 @@

77361

rs6000_abi_name); \

77362

} \

77363

\

77364

- if (!TARGET_64BIT && flag_pic > 1 && rs6000_current_abi == ABI_AIX) \

77365

+ if (!TARGET_64BIT && flag_pic > 1 && rs6000_current_abi != ABI_V4) \

77366

{ \

77367

flag_pic = 0; \

77368

error ("-fPIC and -mcall-%s are incompatible", \

77369

@@ -193,7 +193,7 @@

77370

} \

77371

\

77372

/* Treat -fPIC the same as -mrelocatable. */ \

77373

- if (flag_pic > 1 && DEFAULT_ABI != ABI_AIX) \

77374

+ if (flag_pic > 1 && DEFAULT_ABI == ABI_V4) \

77375

{ \

77376

rs6000_isa_flags |= OPTION_MASK_RELOCATABLE | OPTION_MASK_MINIMAL_TOC; \

77377

TARGET_NO_FP_IN_TOC = 1; \

77378

@@ -317,7 +317,7 @@

77379

77380

/* Put PC relative got entries in .got2. */

77381

#define MINIMAL_TOC_SECTION_ASM_OP \

77382

- (TARGET_RELOCATABLE || (flag_pic && DEFAULT_ABI != ABI_AIX) \

77383

+ (TARGET_RELOCATABLE || (flag_pic && DEFAULT_ABI == ABI_V4) \

77384

? "\t.section\t\".got2\",\"aw\"" : "\t.section\t\".got1\",\"aw\"")

77385

77386

#define SDATA_SECTION_ASM_OP "\t.section\t\".sdata\",\"aw\""

77387

@@ -522,8 +522,6 @@

77388

#define ENDIAN_SELECT(BIG_OPT, LITTLE_OPT, DEFAULT_OPT) \

77389

"%{mlittle|mlittle-endian:" LITTLE_OPT ";" \

77390

"mbig|mbig-endian:" BIG_OPT ";" \

77391

- "mcall-aixdesc|mcall-freebsd|mcall-netbsd|" \

77392

- "mcall-openbsd|mcall-linux:" BIG_OPT ";" \

77393

"mcall-i960-old:" LITTLE_OPT ";" \

77394

":" DEFAULT_OPT "}"

77395

77396

@@ -536,25 +534,12 @@

77397

%{memb|msdata=eabi: -memb}" \

77398

ENDIAN_SELECT(" -mbig", " -mlittle", DEFAULT_ASM_ENDIAN)

77399

77400

-#define CC1_ENDIAN_BIG_SPEC ""

77401

-

77402

-#define CC1_ENDIAN_LITTLE_SPEC "\

77403

-%{!mstrict-align: %{!mno-strict-align: \

77404

- %{!mcall-i960-old: \

77405

- -mstrict-align \

77406

- } \

77407

-}}"

77408

-

77409

-#define CC1_ENDIAN_DEFAULT_SPEC "%(cc1_endian_big)"

77410

-

77411

#ifndef CC1_SECURE_PLT_DEFAULT_SPEC

77412

#define CC1_SECURE_PLT_DEFAULT_SPEC ""

77413

#endif

77414

77415

-/* Pass -G xxx to the compiler and set correct endian mode. */

77416

+/* Pass -G xxx to the compiler. */

77417

#define CC1_SPEC "%{G*} %(cc1_cpu)" \

77418

- ENDIAN_SELECT(" %(cc1_endian_big)", " %(cc1_endian_little)", \

77419

- " %(cc1_endian_default)") \

77420

"%{meabi: %{!mcall-*: -mcall-sysv }} \

77421

%{!meabi: %{!mno-eabi: \

77422

%{mrelocatable: -meabi } \

77423

@@ -908,9 +893,6 @@

77424

{ "link_os_netbsd", LINK_OS_NETBSD_SPEC }, \

77425

{ "link_os_openbsd", LINK_OS_OPENBSD_SPEC }, \

77426

{ "link_os_default", LINK_OS_DEFAULT_SPEC }, \

77427

- { "cc1_endian_big", CC1_ENDIAN_BIG_SPEC }, \

77428

- { "cc1_endian_little", CC1_ENDIAN_LITTLE_SPEC }, \

77429

- { "cc1_endian_default", CC1_ENDIAN_DEFAULT_SPEC }, \

77430

{ "cc1_secure_plt_default", CC1_SECURE_PLT_DEFAULT_SPEC }, \

77431

{ "cpp_os_ads", CPP_OS_ADS_SPEC }, \

77432

{ "cpp_os_yellowknife", CPP_OS_YELLOWKNIFE_SPEC }, \

77433

Index: gcc/config/darwin.c

77434

===================================================================

77435

--- a/src/gcc/config/darwin.c (.../tags/gcc_4_8_2_release)

77436

+++ b/src/gcc/config/darwin.c (.../branches/gcc-4_8-branch)

77437

@@ -1329,6 +1329,9 @@

77438

return NULL_TREE;

77439

}

77440

77441

+static int classes_seen;

77442

+static int objc_metadata_seen;

77443

+

77444

/* Return the section required for Objective C ABI 2 metadata. */

77445

static section *

77446

darwin_objc2_section (tree decl ATTRIBUTE_UNUSED, tree meta, section * base)

77447

@@ -1338,12 +1341,9 @@

77448

gcc_assert (TREE_CODE (ident) == IDENTIFIER_NODE);

77449

p = IDENTIFIER_POINTER (ident);

77450

77451

- /* If we are in LTO, then we don't know the state of flag_next_runtime

77452

- or flag_objc_abi when the code was generated. We set these from the

77453

- meta-data - which is needed to deal with const string constructors. */

77454

+ gcc_checking_assert (flag_next_runtime == 1 && flag_objc_abi == 2);

77455

77456

- flag_next_runtime = 1;

77457

- flag_objc_abi = 2;

77458

+ objc_metadata_seen = 1;

77459

77460

if (base == data_section)

77461

base = darwin_sections[objc2_metadata_section];

77462

@@ -1366,7 +1366,10 @@

77463

else if (!strncmp (p, "V2_NLCL", 7))

77464

return darwin_sections[objc2_nonlazy_class_section];

77465

else if (!strncmp (p, "V2_CLAB", 7))

77466

- return darwin_sections[objc2_classlist_section];

77467

+ {

77468

+ classes_seen = 1;

77469

+ return darwin_sections[objc2_classlist_section];

77470

+ }

77471

else if (!strncmp (p, "V2_SRFS", 7))

77472

return darwin_sections[objc2_selector_refs_section];

77473

else if (!strncmp (p, "V2_NLCA", 7))

77474

@@ -1401,13 +1404,10 @@

77475

gcc_assert (TREE_CODE (ident) == IDENTIFIER_NODE);

77476

p = IDENTIFIER_POINTER (ident);

77477

77478

- /* If we are in LTO, then we don't know the state of flag_next_runtime

77479

- or flag_objc_abi when the code was generated. We set these from the

77480

- meta-data - which is needed to deal with const string constructors. */

77481

- flag_next_runtime = 1;

77482

- if (!global_options_set.x_flag_objc_abi)

77483

- flag_objc_abi = 1;

77484

+ gcc_checking_assert (flag_next_runtime == 1 && flag_objc_abi < 2);

77485

77486

+ objc_metadata_seen = 1;

77487

+

77488

/* String sections first, cos there are lots of strings. */

77489

if (!strncmp (p, "V1_STRG", 7))

77490

return darwin_sections[cstring_section];

77491

@@ -1419,7 +1419,10 @@

77492

return darwin_sections[objc_meth_var_types_section];

77493

77494

else if (!strncmp (p, "V1_CLAS", 7))

77495

- return darwin_sections[objc_class_section];

77496

+ {

77497

+ classes_seen = 1;

77498

+ return darwin_sections[objc_class_section];

77499

+ }

77500

else if (!strncmp (p, "V1_META", 7))

77501

return darwin_sections[objc_meta_class_section];

77502

else if (!strncmp (p, "V1_CATG", 7))

77503

@@ -1603,8 +1606,6 @@

77504

if (TREE_CODE (name) == TYPE_DECL)

77505

name = DECL_NAME (name);

77506

77507

- /* FIXME: This is unsatisfactory for LTO, since it relies on other

77508

- metadata determining the source FE. */

77509

if (!strcmp (IDENTIFIER_POINTER (name), "__builtin_ObjCString"))

77510

{

77511

if (flag_next_runtime)

77512

@@ -2845,6 +2846,33 @@

77513

finalize_ctors ();

77514

if (!vec_safe_is_empty (dtors))

77515

finalize_dtors ();

77516

+

77517

+ /* If we are expecting to output NeXT ObjC meta-data, (and we actually see

77518

+ some) then we output the fix-and-continue marker (Image Info).

77519

+ This applies to Objective C, Objective C++ and LTO with either language

77520

+ as part of the input. */

77521

+ if (flag_next_runtime && objc_metadata_seen)

77522

+ {

77523

+ unsigned int flags = 0;

77524

+ if (flag_objc_abi >= 2)

77525

+ {

77526

+ flags = 16;

77527

+ output_section_asm_op

77528

+ (darwin_sections[objc2_image_info_section]->unnamed.data);

77529

+ }

77530

+ else

77531

+ output_section_asm_op

77532

+ (darwin_sections[objc_image_info_section]->unnamed.data);

77533

+

77534

+ ASM_OUTPUT_ALIGN (asm_out_file, 2);

77535

+ fputs ("L_OBJC_ImageInfo:\n", asm_out_file);

77536

+

77537

+ flags |= (flag_replace_objc_classes && classes_seen) ? 1 : 0;

77538

+ flags |= flag_objc_gc ? 2 : 0;

77539

+

77540

+ fprintf (asm_out_file, "\t.long\t0\n\t.long\t%u\n", flags);

77541

+ }

77542

+

77543

machopic_finish (asm_out_file);

77544

if (strcmp (lang_hooks.name, "GNU C++") == 0)

77545

{

77546

Index: gcc/config/tilepro/tilepro-c.c

77547

===================================================================

77548

--- a/src/gcc/config/tilepro/tilepro-c.c (.../tags/gcc_4_8_2_release)

77549

+++ b/src/gcc/config/tilepro/tilepro-c.c (.../branches/gcc-4_8-branch)

77550

@@ -44,6 +44,11 @@

77551

builtin_define ("__tile_chip__=1");

77552

builtin_define ("__tile_chip_rev__=0");

77553

77554

+ builtin_define ("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");

77555

+ builtin_define ("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");

77556

+ builtin_define ("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");

77557

+ builtin_define ("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");

77558

+

77559

TILEPRO_CPU_CPP_ENDIAN_BUILTINS ();

77560

GNU_USER_TARGET_OS_CPP_BUILTINS ();

77561

}

77562

Index: gcc/config/tilepro/tilepro.c

77563

===================================================================

77564

--- a/src/gcc/config/tilepro/tilepro.c (.../tags/gcc_4_8_2_release)

77565

+++ b/src/gcc/config/tilepro/tilepro.c (.../branches/gcc-4_8-branch)

77566

@@ -3167,6 +3167,12 @@

77567

}

77568

if (!pat)

77569

return NULL_RTX;

77570

+

77571

+ /* If we are generating a prefetch, tell the scheduler not to move

77572

+ it around. */

77573

+ if (GET_CODE (pat) == PREFETCH)

77574

+ PREFETCH_SCHEDULE_BARRIER_P (pat) = true;

77575

+

77576

emit_insn (pat);

77577

77578

if (nonvoid)

77579

Index: gcc/config/tilepro/tilepro.md

77580

===================================================================

77581

--- a/src/gcc/config/tilepro/tilepro.md (.../tags/gcc_4_8_2_release)

77582

+++ b/src/gcc/config/tilepro/tilepro.md (.../branches/gcc-4_8-branch)

77583

@@ -795,7 +795,7 @@

77584

77585

(define_expand "ctzdi2"

77586

[(set (match_operand:DI 0 "register_operand" "")

77587

- (ctz:DI (match_operand:DI 1 "reg_or_0_operand" "")))]

77588

+ (ctz:DI (match_operand:DI 1 "register_operand" "")))]

77589

""

77590

{

77591

rtx lo, hi, ctz_lo, ctz_hi, ctz_hi_plus_32, result;

77592

@@ -823,7 +823,7 @@

77593

77594

(define_expand "clzdi2"

77595

[(set (match_operand:DI 0 "register_operand" "")

77596

- (clz:DI (match_operand:DI 1 "reg_or_0_operand" "")))]

77597

+ (clz:DI (match_operand:DI 1 "register_operand" "")))]

77598

""

77599

{

77600

rtx lo, hi, clz_lo, clz_hi, clz_lo_plus_32, result;

77601

@@ -851,7 +851,7 @@

77602

77603

(define_expand "ffsdi2"

77604

[(set (match_operand:DI 0 "register_operand" "")

77605

- (ffs:DI (match_operand:DI 1 "reg_or_0_operand" "")))]

77606

+ (ffs:DI (match_operand:DI 1 "register_operand" "")))]

77607

""

77608

{

77609

rtx lo, hi, ctz_lo, ctz_hi, ctz_hi_plus_32, ctz, ctz_plus_1,ctz_cond;

77610

Index: gcc/config/arm/arm.c

77611

===================================================================

77612

--- a/src/gcc/config/arm/arm.c (.../tags/gcc_4_8_2_release)

77613

+++ b/src/gcc/config/arm/arm.c (.../branches/gcc-4_8-branch)

77614

@@ -230,7 +230,6 @@

77615

static void arm_option_override (void);

77616

static unsigned HOST_WIDE_INT arm_shift_truncation_mask (enum machine_mode);

77617

static bool arm_cannot_copy_insn_p (rtx);

77618

-static bool arm_tls_symbol_p (rtx x);

77619

static int arm_issue_rate (void);

77620

static void arm_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;

77621

static bool arm_output_addr_const_extra (FILE *, rtx);

77622

@@ -5425,7 +5424,8 @@

77623

if (!crtl->uses_pic_offset_table)

77624

{

77625

gcc_assert (can_create_pseudo_p ());

77626

- if (arm_pic_register != INVALID_REGNUM)

77627

+ if (arm_pic_register != INVALID_REGNUM

77628

+ && !(TARGET_THUMB1 && arm_pic_register > LAST_LO_REGNUM))

77629

{

77630

if (!cfun->machine->pic_reg)

77631

cfun->machine->pic_reg = gen_rtx_REG (Pmode, arm_pic_register);

77632

@@ -5451,7 +5451,12 @@

77633

crtl->uses_pic_offset_table = 1;

77634

start_sequence ();

77635

77636

- arm_load_pic_register (0UL);

77637

+ if (TARGET_THUMB1 && arm_pic_register != INVALID_REGNUM

77638

+ && arm_pic_register > LAST_LO_REGNUM)

77639

+ emit_move_insn (cfun->machine->pic_reg,

77640

+ gen_rtx_REG (Pmode, arm_pic_register));

77641

+ else

77642

+ arm_load_pic_register (0UL);

77643

77644

seq = get_insns ();

77645

end_sequence ();

77646

@@ -5709,6 +5714,14 @@

77647

emit_insn (gen_movsi (pic_offset_table_rtx, pic_tmp));

77648

emit_insn (gen_pic_add_dot_plus_four (pic_reg, pic_reg, labelno));

77649

}

77650

+ else if (arm_pic_register != INVALID_REGNUM

77651

+ && arm_pic_register > LAST_LO_REGNUM

77652

+ && REGNO (pic_reg) <= LAST_LO_REGNUM)

77653

+ {

77654

+ emit_insn (gen_pic_load_addr_unified (pic_reg, pic_rtx, labelno));

77655

+ emit_move_insn (gen_rtx_REG (Pmode, arm_pic_register), pic_reg);

77656

+ emit_use (gen_rtx_REG (Pmode, arm_pic_register));

77657

+ }

77658

else

77659

emit_insn (gen_pic_load_addr_unified (pic_reg, pic_rtx, labelno));

77660

}

77661

@@ -6573,6 +6586,32 @@

77662

rtx

77663

arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)

77664

{

77665

+ if (arm_tls_referenced_p (x))

77666

+ {

77667

+ rtx addend = NULL;

77668

+

77669

+ if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS)

77670

+ {

77671

+ addend = XEXP (XEXP (x, 0), 1);

77672

+ x = XEXP (XEXP (x, 0), 0);

77673

+ }

77674

+

77675

+ if (GET_CODE (x) != SYMBOL_REF)

77676

+ return x;

77677

+

77678

+ gcc_assert (SYMBOL_REF_TLS_MODEL (x) != 0);

77679

+

77680

+ x = legitimize_tls_address (x, NULL_RTX);

77681

+

77682

+ if (addend)

77683

+ {

77684

+ x = gen_rtx_PLUS (SImode, x, addend);

77685

+ orig_x = x;

77686

+ }

77687

+ else

77688

+ return x;

77689

+ }

77690

+

77691

if (!TARGET_ARM)

77692

{

77693

/* TODO: legitimize_address for Thumb2. */

77694

@@ -6581,9 +6620,6 @@

77695

return thumb_legitimize_address (x, orig_x, mode);

77696

}

77697

77698

- if (arm_tls_symbol_p (x))

77699

- return legitimize_tls_address (x, NULL_RTX);

77700

-

77701

if (GET_CODE (x) == PLUS)

77702

{

77703

rtx xop0 = XEXP (x, 0);

77704

@@ -6695,9 +6731,6 @@

77705

rtx

77706

thumb_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)

77707

{

77708

- if (arm_tls_symbol_p (x))

77709

- return legitimize_tls_address (x, NULL_RTX);

77710

-

77711

if (GET_CODE (x) == PLUS

77712

&& CONST_INT_P (XEXP (x, 1))

77713

&& (INTVAL (XEXP (x, 1)) >= 32 * GET_MODE_SIZE (mode)

77714

@@ -6988,20 +7021,6 @@

77715

77716

/* Test for various thread-local symbols. */

77717

77718

-/* Return TRUE if X is a thread-local symbol. */

77719

-

77720

-static bool

77721

-arm_tls_symbol_p (rtx x)

77722

-{

77723

- if (! TARGET_HAVE_TLS)

77724

- return false;

77725

-

77726

- if (GET_CODE (x) != SYMBOL_REF)

77727

- return false;

77728

-

77729

- return SYMBOL_REF_TLS_MODEL (x) != 0;

77730

-}

77731

-

77732

/* Helper for arm_tls_referenced_p. */

77733

77734

static int

77735

@@ -21279,7 +21298,11 @@

77736

type_mode);

77737

}

77738

77739

- op[argc] = expand_normal (arg[argc]);

77740

+ /* Use EXPAND_MEMORY for NEON_ARG_MEMORY to ensure a MEM_P

77741

+ be returned. */

77742

+ op[argc] = expand_expr (arg[argc], NULL_RTX, VOIDmode,

77743

+ (thisarg == NEON_ARG_MEMORY

77744

+ ? EXPAND_MEMORY : EXPAND_NORMAL));

77745

77746

switch (thisarg)

77747

{

77748

@@ -21298,6 +21321,9 @@

77749

break;

77750

77751

case NEON_ARG_MEMORY:

77752

+ /* Check if expand failed. */

77753

+ if (op[argc] == const0_rtx)

77754

+ return 0;

77755

gcc_assert (MEM_P (op[argc]));

77756

PUT_MODE (op[argc], mode[argc]);

77757

/* ??? arm_neon.h uses the same built-in functions for signed

77758

@@ -23555,6 +23581,7 @@

77759

num_regs = bit_count (saved_regs_mask);

77760

if ((offsets->outgoing_args != (1 + num_regs)) || cfun->calls_alloca)

77761

{

77762

+ emit_insn (gen_blockage ());

77763

/* Unwind the stack to just below the saved registers. */

77764

emit_insn (gen_addsi3 (stack_pointer_rtx,

77765

hard_frame_pointer_rtx,

77766

@@ -23583,8 +23610,8 @@

77767

77768

if (crtl->calls_eh_return)

77769

emit_insn (gen_addsi3 (stack_pointer_rtx,

77770

- stack_pointer_rtx,

77771

- GEN_INT (ARM_EH_STACKADJ_REGNUM)));

77772

+ stack_pointer_rtx,

77773

+ gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)));

77774

77775

if (IS_STACKALIGN (func_type))

77776

/* Restore the original stack pointer. Before prologue, the stack was

77777

Index: gcc/config/arm/arm.h

77778

===================================================================

77779

--- a/src/gcc/config/arm/arm.h (.../tags/gcc_4_8_2_release)

77780

+++ b/src/gcc/config/arm/arm.h (.../branches/gcc-4_8-branch)

77781

@@ -1213,11 +1213,15 @@

77782

VFPv2.

77783

In big-endian mode, modes greater than word size (i.e. DFmode) are stored in

77784

VFP registers in little-endian order. We can't describe that accurately to

77785

- GCC, so avoid taking subregs of such values. */

77786

-#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \

77787

- (TARGET_VFP && TARGET_BIG_END \

77788

- && (GET_MODE_SIZE (FROM) > UNITS_PER_WORD \

77789

- || GET_MODE_SIZE (TO) > UNITS_PER_WORD) \

77790

+ GCC, so avoid taking subregs of such values.

77791

+ The only exception is going from a 128-bit to a 64-bit type. In that case

77792

+ the data layout happens to be consistent for big-endian, so we explicitly allow

77793

+ that case. */

77794

+#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \

77795

+ (TARGET_VFP && TARGET_BIG_END \

77796

+ && !(GET_MODE_SIZE (FROM) == 16 && GET_MODE_SIZE (TO) == 8) \

77797

+ && (GET_MODE_SIZE (FROM) > UNITS_PER_WORD \

77798

+ || GET_MODE_SIZE (TO) > UNITS_PER_WORD) \

77799

&& reg_classes_intersect_p (VFP_REGS, (CLASS)))

77800

77801

/* The class value for index registers, and the one for base regs. */

77802

Index: gcc/config/arm/vfp.md

77803

===================================================================

77804

--- a/src/gcc/config/arm/vfp.md (.../tags/gcc_4_8_2_release)

77805

+++ b/src/gcc/config/arm/vfp.md (.../branches/gcc-4_8-branch)

77806

@@ -1264,6 +1264,7 @@

77807

"TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>"

77808

"vrint<vrint_variant>%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1"

77809

[(set_attr "predicable" "<vrint_predicable>")

77810

+ (set_attr "conds" "<vrint_conds>")

77811

(set_attr "type" "f_rint<vfp_type>")]

77812

)

77813

77814

@@ -1280,7 +1281,8 @@

77815

(match_operand:SDF 2 "register_operand" "<F_constraint>")))]

77816

"TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>"

77817

"vmaxnm.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"

77818

- [(set_attr "type" "f_minmax<vfp_type>")]

77819

+ [(set_attr "type" "f_minmax<vfp_type>")

77820

+ (set_attr "conds" "unconditional")]

77821

)

77822

77823

(define_insn "smin<mode>3"

77824

@@ -1289,7 +1291,8 @@

77825

(match_operand:SDF 2 "register_operand" "<F_constraint>")))]

77826

"TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>"

77827

"vminnm.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"

77828

- [(set_attr "type" "f_minmax<vfp_type>")]

77829

+ [(set_attr "type" "f_minmax<vfp_type>")

77830

+ (set_attr "conds" "unconditional")]

77831

)

77832

77833

;; Unimplemented insns:

77834

Index: gcc/config/arm/ldmstm.md

77835

===================================================================

77836

--- a/src/gcc/config/arm/ldmstm.md (.../tags/gcc_4_8_2_release)

77837

+++ b/src/gcc/config/arm/ldmstm.md (.../branches/gcc-4_8-branch)

77838

@@ -23,15 +23,15 @@

77839

77840

(define_insn "*ldm4_ia"

77841

[(match_parallel 0 "load_multiple_operation"

77842

- [(set (match_operand:SI 1 "arm_hard_register_operand" "")

77843

+ [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")

77844

(mem:SI (match_operand:SI 5 "s_register_operand" "rk")))

77845

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

77846

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

77847

(mem:SI (plus:SI (match_dup 5)

77848

(const_int 4))))

77849

- (set (match_operand:SI 3 "arm_hard_register_operand" "")

77850

+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")

77851

(mem:SI (plus:SI (match_dup 5)

77852

(const_int 8))))

77853

- (set (match_operand:SI 4 "arm_hard_register_operand" "")

77854

+ (set (match_operand:SI 4 "arm_hard_general_register_operand" "")

77855

(mem:SI (plus:SI (match_dup 5)

77856

(const_int 12))))])]

77857

"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"

77858

@@ -41,15 +41,15 @@

77859

77860

(define_insn "*thumb_ldm4_ia"

77861

[(match_parallel 0 "load_multiple_operation"

77862

- [(set (match_operand:SI 1 "arm_hard_register_operand" "")

77863

+ [(set (match_operand:SI 1 "low_register_operand" "")

77864

(mem:SI (match_operand:SI 5 "s_register_operand" "l")))

77865

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

77866

+ (set (match_operand:SI 2 "low_register_operand" "")

77867

(mem:SI (plus:SI (match_dup 5)

77868

(const_int 4))))

77869

- (set (match_operand:SI 3 "arm_hard_register_operand" "")

77870

+ (set (match_operand:SI 3 "low_register_operand" "")

77871

(mem:SI (plus:SI (match_dup 5)

77872

(const_int 8))))

77873

- (set (match_operand:SI 4 "arm_hard_register_operand" "")

77874

+ (set (match_operand:SI 4 "low_register_operand" "")

77875

(mem:SI (plus:SI (match_dup 5)

77876

(const_int 12))))])]

77877

"TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4"

77878

@@ -60,15 +60,15 @@

77879

[(match_parallel 0 "load_multiple_operation"

77880

[(set (match_operand:SI 5 "s_register_operand" "+&rk")

77881

(plus:SI (match_dup 5) (const_int 16)))

77882

- (set (match_operand:SI 1 "arm_hard_register_operand" "")

77883

+ (set (match_operand:SI 1 "arm_hard_general_register_operand" "")

77884

(mem:SI (match_dup 5)))

77885

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

77886

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

77887

(mem:SI (plus:SI (match_dup 5)

77888

(const_int 4))))

77889

- (set (match_operand:SI 3 "arm_hard_register_operand" "")

77890

+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")

77891

(mem:SI (plus:SI (match_dup 5)

77892

(const_int 8))))

77893

- (set (match_operand:SI 4 "arm_hard_register_operand" "")

77894

+ (set (match_operand:SI 4 "arm_hard_general_register_operand" "")

77895

(mem:SI (plus:SI (match_dup 5)

77896

(const_int 12))))])]

77897

"TARGET_32BIT && XVECLEN (operands[0], 0) == 5"

77898

@@ -80,15 +80,15 @@

77899

[(match_parallel 0 "load_multiple_operation"

77900

[(set (match_operand:SI 5 "s_register_operand" "+&l")

77901

(plus:SI (match_dup 5) (const_int 16)))

77902

- (set (match_operand:SI 1 "arm_hard_register_operand" "")

77903

+ (set (match_operand:SI 1 "low_register_operand" "")

77904

(mem:SI (match_dup 5)))

77905

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

77906

+ (set (match_operand:SI 2 "low_register_operand" "")

77907

(mem:SI (plus:SI (match_dup 5)

77908

(const_int 4))))

77909

- (set (match_operand:SI 3 "arm_hard_register_operand" "")

77910

+ (set (match_operand:SI 3 "low_register_operand" "")

77911

(mem:SI (plus:SI (match_dup 5)

77912

(const_int 8))))

77913

- (set (match_operand:SI 4 "arm_hard_register_operand" "")

77914

+ (set (match_operand:SI 4 "low_register_operand" "")

77915

(mem:SI (plus:SI (match_dup 5)

77916

(const_int 12))))])]

77917

"TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5"

77918

@@ -98,13 +98,13 @@

77919

(define_insn "*stm4_ia"

77920

[(match_parallel 0 "store_multiple_operation"

77921

[(set (mem:SI (match_operand:SI 5 "s_register_operand" "rk"))

77922

- (match_operand:SI 1 "arm_hard_register_operand" ""))

77923

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

77924

(set (mem:SI (plus:SI (match_dup 5) (const_int 4)))

77925

- (match_operand:SI 2 "arm_hard_register_operand" ""))

77926

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))

77927

(set (mem:SI (plus:SI (match_dup 5) (const_int 8)))

77928

- (match_operand:SI 3 "arm_hard_register_operand" ""))

77929

+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))

77930

(set (mem:SI (plus:SI (match_dup 5) (const_int 12)))

77931

- (match_operand:SI 4 "arm_hard_register_operand" ""))])]

77932

+ (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]

77933

"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"

77934

"stm%(ia%)\t%5, {%1, %2, %3, %4}"

77935

[(set_attr "type" "store4")

77936

@@ -115,13 +115,13 @@

77937

[(set (match_operand:SI 5 "s_register_operand" "+&rk")

77938

(plus:SI (match_dup 5) (const_int 16)))

77939

(set (mem:SI (match_dup 5))

77940

- (match_operand:SI 1 "arm_hard_register_operand" ""))

77941

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

77942

(set (mem:SI (plus:SI (match_dup 5) (const_int 4)))

77943

- (match_operand:SI 2 "arm_hard_register_operand" ""))

77944

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))

77945

(set (mem:SI (plus:SI (match_dup 5) (const_int 8)))

77946

- (match_operand:SI 3 "arm_hard_register_operand" ""))

77947

+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))

77948

(set (mem:SI (plus:SI (match_dup 5) (const_int 12)))

77949

- (match_operand:SI 4 "arm_hard_register_operand" ""))])]

77950

+ (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]

77951

"TARGET_32BIT && XVECLEN (operands[0], 0) == 5"

77952

"stm%(ia%)\t%5!, {%1, %2, %3, %4}"

77953

[(set_attr "type" "store4")

77954

@@ -132,13 +132,13 @@

77955

[(set (match_operand:SI 5 "s_register_operand" "+&l")

77956

(plus:SI (match_dup 5) (const_int 16)))

77957

(set (mem:SI (match_dup 5))

77958

- (match_operand:SI 1 "arm_hard_register_operand" ""))

77959

+ (match_operand:SI 1 "low_register_operand" ""))

77960

(set (mem:SI (plus:SI (match_dup 5) (const_int 4)))

77961

- (match_operand:SI 2 "arm_hard_register_operand" ""))

77962

+ (match_operand:SI 2 "low_register_operand" ""))

77963

(set (mem:SI (plus:SI (match_dup 5) (const_int 8)))

77964

- (match_operand:SI 3 "arm_hard_register_operand" ""))

77965

+ (match_operand:SI 3 "low_register_operand" ""))

77966

(set (mem:SI (plus:SI (match_dup 5) (const_int 12)))

77967

- (match_operand:SI 4 "arm_hard_register_operand" ""))])]

77968

+ (match_operand:SI 4 "low_register_operand" ""))])]

77969

"TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5"

77970

"stm%(ia%)\t%5!, {%1, %2, %3, %4}"

77971

[(set_attr "type" "store4")])

77972

@@ -145,16 +145,16 @@

77973

77974

(define_insn "*ldm4_ib"

77975

[(match_parallel 0 "load_multiple_operation"

77976

- [(set (match_operand:SI 1 "arm_hard_register_operand" "")

77977

+ [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")

77978

(mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk")

77979

(const_int 4))))

77980

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

77981

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

77982

(mem:SI (plus:SI (match_dup 5)

77983

(const_int 8))))

77984

- (set (match_operand:SI 3 "arm_hard_register_operand" "")

77985

+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")

77986

(mem:SI (plus:SI (match_dup 5)

77987

(const_int 12))))

77988

- (set (match_operand:SI 4 "arm_hard_register_operand" "")

77989

+ (set (match_operand:SI 4 "arm_hard_general_register_operand" "")

77990

(mem:SI (plus:SI (match_dup 5)

77991

(const_int 16))))])]

77992

"TARGET_ARM && XVECLEN (operands[0], 0) == 4"

77993

@@ -166,16 +166,16 @@

77994

[(match_parallel 0 "load_multiple_operation"

77995

[(set (match_operand:SI 5 "s_register_operand" "+&rk")

77996

(plus:SI (match_dup 5) (const_int 16)))

77997

- (set (match_operand:SI 1 "arm_hard_register_operand" "")

77998

+ (set (match_operand:SI 1 "arm_hard_general_register_operand" "")

77999

(mem:SI (plus:SI (match_dup 5)

78000

(const_int 4))))

78001

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78002

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

78003

(mem:SI (plus:SI (match_dup 5)

78004

(const_int 8))))

78005

- (set (match_operand:SI 3 "arm_hard_register_operand" "")

78006

+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")

78007

(mem:SI (plus:SI (match_dup 5)

78008

(const_int 12))))

78009

- (set (match_operand:SI 4 "arm_hard_register_operand" "")

78010

+ (set (match_operand:SI 4 "arm_hard_general_register_operand" "")

78011

(mem:SI (plus:SI (match_dup 5)

78012

(const_int 16))))])]

78013

"TARGET_ARM && XVECLEN (operands[0], 0) == 5"

78014

@@ -186,13 +186,13 @@

78015

(define_insn "*stm4_ib"

78016

[(match_parallel 0 "store_multiple_operation"

78017

[(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int 4)))

78018

- (match_operand:SI 1 "arm_hard_register_operand" ""))

78019

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

78020

(set (mem:SI (plus:SI (match_dup 5) (const_int 8)))

78021

- (match_operand:SI 2 "arm_hard_register_operand" ""))

78022

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))

78023

(set (mem:SI (plus:SI (match_dup 5) (const_int 12)))

78024

- (match_operand:SI 3 "arm_hard_register_operand" ""))

78025

+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))

78026

(set (mem:SI (plus:SI (match_dup 5) (const_int 16)))

78027

- (match_operand:SI 4 "arm_hard_register_operand" ""))])]

78028

+ (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]

78029

"TARGET_ARM && XVECLEN (operands[0], 0) == 4"

78030

"stm%(ib%)\t%5, {%1, %2, %3, %4}"

78031

[(set_attr "type" "store4")

78032

@@ -203,13 +203,13 @@

78033

[(set (match_operand:SI 5 "s_register_operand" "+&rk")

78034

(plus:SI (match_dup 5) (const_int 16)))

78035

(set (mem:SI (plus:SI (match_dup 5) (const_int 4)))

78036

- (match_operand:SI 1 "arm_hard_register_operand" ""))

78037

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

78038

(set (mem:SI (plus:SI (match_dup 5) (const_int 8)))

78039

- (match_operand:SI 2 "arm_hard_register_operand" ""))

78040

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))

78041

(set (mem:SI (plus:SI (match_dup 5) (const_int 12)))

78042

- (match_operand:SI 3 "arm_hard_register_operand" ""))

78043

+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))

78044

(set (mem:SI (plus:SI (match_dup 5) (const_int 16)))

78045

- (match_operand:SI 4 "arm_hard_register_operand" ""))])]

78046

+ (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]

78047

"TARGET_ARM && XVECLEN (operands[0], 0) == 5"

78048

"stm%(ib%)\t%5!, {%1, %2, %3, %4}"

78049

[(set_attr "type" "store4")

78050

@@ -217,16 +217,16 @@

78051

78052

(define_insn "*ldm4_da"

78053

[(match_parallel 0 "load_multiple_operation"

78054

- [(set (match_operand:SI 1 "arm_hard_register_operand" "")

78055

+ [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")

78056

(mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk")

78057

(const_int -12))))

78058

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78059

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

78060

(mem:SI (plus:SI (match_dup 5)

78061

(const_int -8))))

78062

- (set (match_operand:SI 3 "arm_hard_register_operand" "")

78063

+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")

78064

(mem:SI (plus:SI (match_dup 5)

78065

(const_int -4))))

78066

- (set (match_operand:SI 4 "arm_hard_register_operand" "")

78067

+ (set (match_operand:SI 4 "arm_hard_general_register_operand" "")

78068

(mem:SI (match_dup 5)))])]

78069

"TARGET_ARM && XVECLEN (operands[0], 0) == 4"

78070

"ldm%(da%)\t%5, {%1, %2, %3, %4}"

78071

@@ -237,16 +237,16 @@

78072

[(match_parallel 0 "load_multiple_operation"

78073

[(set (match_operand:SI 5 "s_register_operand" "+&rk")

78074

(plus:SI (match_dup 5) (const_int -16)))

78075

- (set (match_operand:SI 1 "arm_hard_register_operand" "")

78076

+ (set (match_operand:SI 1 "arm_hard_general_register_operand" "")

78077

(mem:SI (plus:SI (match_dup 5)

78078

(const_int -12))))

78079

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78080

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

78081

(mem:SI (plus:SI (match_dup 5)

78082

(const_int -8))))

78083

- (set (match_operand:SI 3 "arm_hard_register_operand" "")

78084

+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")

78085

(mem:SI (plus:SI (match_dup 5)

78086

(const_int -4))))

78087

- (set (match_operand:SI 4 "arm_hard_register_operand" "")

78088

+ (set (match_operand:SI 4 "arm_hard_general_register_operand" "")

78089

(mem:SI (match_dup 5)))])]

78090

"TARGET_ARM && XVECLEN (operands[0], 0) == 5"

78091

"ldm%(da%)\t%5!, {%1, %2, %3, %4}"

78092

@@ -256,13 +256,13 @@

78093

(define_insn "*stm4_da"

78094

[(match_parallel 0 "store_multiple_operation"

78095

[(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int -12)))

78096

- (match_operand:SI 1 "arm_hard_register_operand" ""))

78097

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

78098

(set (mem:SI (plus:SI (match_dup 5) (const_int -8)))

78099

- (match_operand:SI 2 "arm_hard_register_operand" ""))

78100

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))

78101

(set (mem:SI (plus:SI (match_dup 5) (const_int -4)))

78102

- (match_operand:SI 3 "arm_hard_register_operand" ""))

78103

+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))

78104

(set (mem:SI (match_dup 5))

78105

- (match_operand:SI 4 "arm_hard_register_operand" ""))])]

78106

+ (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]

78107

"TARGET_ARM && XVECLEN (operands[0], 0) == 4"

78108

"stm%(da%)\t%5, {%1, %2, %3, %4}"

78109

[(set_attr "type" "store4")

78110

@@ -273,13 +273,13 @@

78111

[(set (match_operand:SI 5 "s_register_operand" "+&rk")

78112

(plus:SI (match_dup 5) (const_int -16)))

78113

(set (mem:SI (plus:SI (match_dup 5) (const_int -12)))

78114

- (match_operand:SI 1 "arm_hard_register_operand" ""))

78115

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

78116

(set (mem:SI (plus:SI (match_dup 5) (const_int -8)))

78117

- (match_operand:SI 2 "arm_hard_register_operand" ""))

78118

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))

78119

(set (mem:SI (plus:SI (match_dup 5) (const_int -4)))

78120

- (match_operand:SI 3 "arm_hard_register_operand" ""))

78121

+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))

78122

(set (mem:SI (match_dup 5))

78123

- (match_operand:SI 4 "arm_hard_register_operand" ""))])]

78124

+ (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]

78125

"TARGET_ARM && XVECLEN (operands[0], 0) == 5"

78126

"stm%(da%)\t%5!, {%1, %2, %3, %4}"

78127

[(set_attr "type" "store4")

78128

@@ -287,16 +287,16 @@

78129

78130

(define_insn "*ldm4_db"

78131

[(match_parallel 0 "load_multiple_operation"

78132

- [(set (match_operand:SI 1 "arm_hard_register_operand" "")

78133

+ [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")

78134

(mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk")

78135

(const_int -16))))

78136

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78137

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

78138

(mem:SI (plus:SI (match_dup 5)

78139

(const_int -12))))

78140

- (set (match_operand:SI 3 "arm_hard_register_operand" "")

78141

+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")

78142

(mem:SI (plus:SI (match_dup 5)

78143

(const_int -8))))

78144

- (set (match_operand:SI 4 "arm_hard_register_operand" "")

78145

+ (set (match_operand:SI 4 "arm_hard_general_register_operand" "")

78146

(mem:SI (plus:SI (match_dup 5)

78147

(const_int -4))))])]

78148

"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"

78149

@@ -308,16 +308,16 @@

78150

[(match_parallel 0 "load_multiple_operation"

78151

[(set (match_operand:SI 5 "s_register_operand" "+&rk")

78152

(plus:SI (match_dup 5) (const_int -16)))

78153

- (set (match_operand:SI 1 "arm_hard_register_operand" "")

78154

+ (set (match_operand:SI 1 "arm_hard_general_register_operand" "")

78155

(mem:SI (plus:SI (match_dup 5)

78156

(const_int -16))))

78157

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78158

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

78159

(mem:SI (plus:SI (match_dup 5)

78160

(const_int -12))))

78161

- (set (match_operand:SI 3 "arm_hard_register_operand" "")

78162

+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")

78163

(mem:SI (plus:SI (match_dup 5)

78164

(const_int -8))))

78165

- (set (match_operand:SI 4 "arm_hard_register_operand" "")

78166

+ (set (match_operand:SI 4 "arm_hard_general_register_operand" "")

78167

(mem:SI (plus:SI (match_dup 5)

78168

(const_int -4))))])]

78169

"TARGET_32BIT && XVECLEN (operands[0], 0) == 5"

78170

@@ -328,13 +328,13 @@

78171

(define_insn "*stm4_db"

78172

[(match_parallel 0 "store_multiple_operation"

78173

[(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int -16)))

78174

- (match_operand:SI 1 "arm_hard_register_operand" ""))

78175

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

78176

(set (mem:SI (plus:SI (match_dup 5) (const_int -12)))

78177

- (match_operand:SI 2 "arm_hard_register_operand" ""))

78178

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))

78179

(set (mem:SI (plus:SI (match_dup 5) (const_int -8)))

78180

- (match_operand:SI 3 "arm_hard_register_operand" ""))

78181

+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))

78182

(set (mem:SI (plus:SI (match_dup 5) (const_int -4)))

78183

- (match_operand:SI 4 "arm_hard_register_operand" ""))])]

78184

+ (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]

78185

"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"

78186

"stm%(db%)\t%5, {%1, %2, %3, %4}"

78187

[(set_attr "type" "store4")

78188

@@ -345,13 +345,13 @@

78189

[(set (match_operand:SI 5 "s_register_operand" "+&rk")

78190

(plus:SI (match_dup 5) (const_int -16)))

78191

(set (mem:SI (plus:SI (match_dup 5) (const_int -16)))

78192

- (match_operand:SI 1 "arm_hard_register_operand" ""))

78193

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

78194

(set (mem:SI (plus:SI (match_dup 5) (const_int -12)))

78195

- (match_operand:SI 2 "arm_hard_register_operand" ""))

78196

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))

78197

(set (mem:SI (plus:SI (match_dup 5) (const_int -8)))

78198

- (match_operand:SI 3 "arm_hard_register_operand" ""))

78199

+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))

78200

(set (mem:SI (plus:SI (match_dup 5) (const_int -4)))

78201

- (match_operand:SI 4 "arm_hard_register_operand" ""))])]

78202

+ (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]

78203

"TARGET_32BIT && XVECLEN (operands[0], 0) == 5"

78204

"stm%(db%)\t%5!, {%1, %2, %3, %4}"

78205

[(set_attr "type" "store4")

78206

@@ -466,12 +466,12 @@

78207

78208

(define_insn "*ldm3_ia"

78209

[(match_parallel 0 "load_multiple_operation"

78210

- [(set (match_operand:SI 1 "arm_hard_register_operand" "")

78211

+ [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")

78212

(mem:SI (match_operand:SI 4 "s_register_operand" "rk")))

78213

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78214

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

78215

(mem:SI (plus:SI (match_dup 4)

78216

(const_int 4))))

78217

- (set (match_operand:SI 3 "arm_hard_register_operand" "")

78218

+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")

78219

(mem:SI (plus:SI (match_dup 4)

78220

(const_int 8))))])]

78221

"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"

78222

@@ -481,12 +481,12 @@

78223

78224

(define_insn "*thumb_ldm3_ia"

78225

[(match_parallel 0 "load_multiple_operation"

78226

- [(set (match_operand:SI 1 "arm_hard_register_operand" "")

78227

+ [(set (match_operand:SI 1 "low_register_operand" "")

78228

(mem:SI (match_operand:SI 4 "s_register_operand" "l")))

78229

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78230

+ (set (match_operand:SI 2 "low_register_operand" "")

78231

(mem:SI (plus:SI (match_dup 4)

78232

(const_int 4))))

78233

- (set (match_operand:SI 3 "arm_hard_register_operand" "")

78234

+ (set (match_operand:SI 3 "low_register_operand" "")

78235

(mem:SI (plus:SI (match_dup 4)

78236

(const_int 8))))])]

78237

"TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3"

78238

@@ -497,12 +497,12 @@

78239

[(match_parallel 0 "load_multiple_operation"

78240

[(set (match_operand:SI 4 "s_register_operand" "+&rk")

78241

(plus:SI (match_dup 4) (const_int 12)))

78242

- (set (match_operand:SI 1 "arm_hard_register_operand" "")

78243

+ (set (match_operand:SI 1 "arm_hard_general_register_operand" "")

78244

(mem:SI (match_dup 4)))

78245

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78246

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

78247

(mem:SI (plus:SI (match_dup 4)

78248

(const_int 4))))

78249

- (set (match_operand:SI 3 "arm_hard_register_operand" "")

78250

+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")

78251

(mem:SI (plus:SI (match_dup 4)

78252

(const_int 8))))])]

78253

"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"

78254

@@ -514,12 +514,12 @@

78255

[(match_parallel 0 "load_multiple_operation"

78256

[(set (match_operand:SI 4 "s_register_operand" "+&l")

78257

(plus:SI (match_dup 4) (const_int 12)))

78258

- (set (match_operand:SI 1 "arm_hard_register_operand" "")

78259

+ (set (match_operand:SI 1 "low_register_operand" "")

78260

(mem:SI (match_dup 4)))

78261

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78262

+ (set (match_operand:SI 2 "low_register_operand" "")

78263

(mem:SI (plus:SI (match_dup 4)

78264

(const_int 4))))

78265

- (set (match_operand:SI 3 "arm_hard_register_operand" "")

78266

+ (set (match_operand:SI 3 "low_register_operand" "")

78267

(mem:SI (plus:SI (match_dup 4)

78268

(const_int 8))))])]

78269

"TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4"

78270

@@ -529,11 +529,11 @@

78271

(define_insn "*stm3_ia"

78272

[(match_parallel 0 "store_multiple_operation"

78273

[(set (mem:SI (match_operand:SI 4 "s_register_operand" "rk"))

78274

- (match_operand:SI 1 "arm_hard_register_operand" ""))

78275

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

78276

(set (mem:SI (plus:SI (match_dup 4) (const_int 4)))

78277

- (match_operand:SI 2 "arm_hard_register_operand" ""))

78278

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))

78279

(set (mem:SI (plus:SI (match_dup 4) (const_int 8)))

78280

- (match_operand:SI 3 "arm_hard_register_operand" ""))])]

78281

+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]

78282

"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"

78283

"stm%(ia%)\t%4, {%1, %2, %3}"

78284

[(set_attr "type" "store3")

78285

@@ -544,11 +544,11 @@

78286

[(set (match_operand:SI 4 "s_register_operand" "+&rk")

78287

(plus:SI (match_dup 4) (const_int 12)))

78288

(set (mem:SI (match_dup 4))

78289

- (match_operand:SI 1 "arm_hard_register_operand" ""))

78290

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

78291

(set (mem:SI (plus:SI (match_dup 4) (const_int 4)))

78292

- (match_operand:SI 2 "arm_hard_register_operand" ""))

78293

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))

78294

(set (mem:SI (plus:SI (match_dup 4) (const_int 8)))

78295

- (match_operand:SI 3 "arm_hard_register_operand" ""))])]

78296

+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]

78297

"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"

78298

"stm%(ia%)\t%4!, {%1, %2, %3}"

78299

[(set_attr "type" "store3")

78300

@@ -559,11 +559,11 @@

78301

[(set (match_operand:SI 4 "s_register_operand" "+&l")

78302

(plus:SI (match_dup 4) (const_int 12)))

78303

(set (mem:SI (match_dup 4))

78304

- (match_operand:SI 1 "arm_hard_register_operand" ""))

78305

+ (match_operand:SI 1 "low_register_operand" ""))

78306

(set (mem:SI (plus:SI (match_dup 4) (const_int 4)))

78307

- (match_operand:SI 2 "arm_hard_register_operand" ""))

78308

+ (match_operand:SI 2 "low_register_operand" ""))

78309

(set (mem:SI (plus:SI (match_dup 4) (const_int 8)))

78310

- (match_operand:SI 3 "arm_hard_register_operand" ""))])]

78311

+ (match_operand:SI 3 "low_register_operand" ""))])]

78312

"TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4"

78313

"stm%(ia%)\t%4!, {%1, %2, %3}"

78314

[(set_attr "type" "store3")])

78315

@@ -570,13 +570,13 @@

78316

78317

(define_insn "*ldm3_ib"

78318

[(match_parallel 0 "load_multiple_operation"

78319

- [(set (match_operand:SI 1 "arm_hard_register_operand" "")

78320

+ [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")

78321

(mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk")

78322

(const_int 4))))

78323

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78324

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

78325

(mem:SI (plus:SI (match_dup 4)

78326

(const_int 8))))

78327

- (set (match_operand:SI 3 "arm_hard_register_operand" "")

78328

+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")

78329

(mem:SI (plus:SI (match_dup 4)

78330

(const_int 12))))])]

78331

"TARGET_ARM && XVECLEN (operands[0], 0) == 3"

78332

@@ -588,13 +588,13 @@

78333

[(match_parallel 0 "load_multiple_operation"

78334

[(set (match_operand:SI 4 "s_register_operand" "+&rk")

78335

(plus:SI (match_dup 4) (const_int 12)))

78336

- (set (match_operand:SI 1 "arm_hard_register_operand" "")

78337

+ (set (match_operand:SI 1 "arm_hard_general_register_operand" "")

78338

(mem:SI (plus:SI (match_dup 4)

78339

(const_int 4))))

78340

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78341

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

78342

(mem:SI (plus:SI (match_dup 4)

78343

(const_int 8))))

78344

- (set (match_operand:SI 3 "arm_hard_register_operand" "")

78345

+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")

78346

(mem:SI (plus:SI (match_dup 4)

78347

(const_int 12))))])]

78348

"TARGET_ARM && XVECLEN (operands[0], 0) == 4"

78349

@@ -605,11 +605,11 @@

78350

(define_insn "*stm3_ib"

78351

[(match_parallel 0 "store_multiple_operation"

78352

[(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int 4)))

78353

- (match_operand:SI 1 "arm_hard_register_operand" ""))

78354

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

78355

(set (mem:SI (plus:SI (match_dup 4) (const_int 8)))

78356

- (match_operand:SI 2 "arm_hard_register_operand" ""))

78357

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))

78358

(set (mem:SI (plus:SI (match_dup 4) (const_int 12)))

78359

- (match_operand:SI 3 "arm_hard_register_operand" ""))])]

78360

+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]

78361

"TARGET_ARM && XVECLEN (operands[0], 0) == 3"

78362

"stm%(ib%)\t%4, {%1, %2, %3}"

78363

[(set_attr "type" "store3")

78364

@@ -620,11 +620,11 @@

78365

[(set (match_operand:SI 4 "s_register_operand" "+&rk")

78366

(plus:SI (match_dup 4) (const_int 12)))

78367

(set (mem:SI (plus:SI (match_dup 4) (const_int 4)))

78368

- (match_operand:SI 1 "arm_hard_register_operand" ""))

78369

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

78370

(set (mem:SI (plus:SI (match_dup 4) (const_int 8)))

78371

- (match_operand:SI 2 "arm_hard_register_operand" ""))

78372

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))

78373

(set (mem:SI (plus:SI (match_dup 4) (const_int 12)))

78374

- (match_operand:SI 3 "arm_hard_register_operand" ""))])]

78375

+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]

78376

"TARGET_ARM && XVECLEN (operands[0], 0) == 4"

78377

"stm%(ib%)\t%4!, {%1, %2, %3}"

78378

[(set_attr "type" "store3")

78379

@@ -632,13 +632,13 @@

78380

78381

(define_insn "*ldm3_da"

78382

[(match_parallel 0 "load_multiple_operation"

78383

- [(set (match_operand:SI 1 "arm_hard_register_operand" "")

78384

+ [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")

78385

(mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk")

78386

(const_int -8))))

78387

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78388

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

78389

(mem:SI (plus:SI (match_dup 4)

78390

(const_int -4))))

78391

- (set (match_operand:SI 3 "arm_hard_register_operand" "")

78392

+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")

78393

(mem:SI (match_dup 4)))])]

78394

"TARGET_ARM && XVECLEN (operands[0], 0) == 3"

78395

"ldm%(da%)\t%4, {%1, %2, %3}"

78396

@@ -649,13 +649,13 @@

78397

[(match_parallel 0 "load_multiple_operation"

78398

[(set (match_operand:SI 4 "s_register_operand" "+&rk")

78399

(plus:SI (match_dup 4) (const_int -12)))

78400

- (set (match_operand:SI 1 "arm_hard_register_operand" "")

78401

+ (set (match_operand:SI 1 "arm_hard_general_register_operand" "")

78402

(mem:SI (plus:SI (match_dup 4)

78403

(const_int -8))))

78404

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78405

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

78406

(mem:SI (plus:SI (match_dup 4)

78407

(const_int -4))))

78408

- (set (match_operand:SI 3 "arm_hard_register_operand" "")

78409

+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")

78410

(mem:SI (match_dup 4)))])]

78411

"TARGET_ARM && XVECLEN (operands[0], 0) == 4"

78412

"ldm%(da%)\t%4!, {%1, %2, %3}"

78413

@@ -665,11 +665,11 @@

78414

(define_insn "*stm3_da"

78415

[(match_parallel 0 "store_multiple_operation"

78416

[(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int -8)))

78417

- (match_operand:SI 1 "arm_hard_register_operand" ""))

78418

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

78419

(set (mem:SI (plus:SI (match_dup 4) (const_int -4)))

78420

- (match_operand:SI 2 "arm_hard_register_operand" ""))

78421

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))

78422

(set (mem:SI (match_dup 4))

78423

- (match_operand:SI 3 "arm_hard_register_operand" ""))])]

78424

+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]

78425

"TARGET_ARM && XVECLEN (operands[0], 0) == 3"

78426

"stm%(da%)\t%4, {%1, %2, %3}"

78427

[(set_attr "type" "store3")

78428

@@ -680,11 +680,11 @@

78429

[(set (match_operand:SI 4 "s_register_operand" "+&rk")

78430

(plus:SI (match_dup 4) (const_int -12)))

78431

(set (mem:SI (plus:SI (match_dup 4) (const_int -8)))

78432

- (match_operand:SI 1 "arm_hard_register_operand" ""))

78433

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

78434

(set (mem:SI (plus:SI (match_dup 4) (const_int -4)))

78435

- (match_operand:SI 2 "arm_hard_register_operand" ""))

78436

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))

78437

(set (mem:SI (match_dup 4))

78438

- (match_operand:SI 3 "arm_hard_register_operand" ""))])]

78439

+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]

78440

"TARGET_ARM && XVECLEN (operands[0], 0) == 4"

78441

"stm%(da%)\t%4!, {%1, %2, %3}"

78442

[(set_attr "type" "store3")

78443

@@ -692,13 +692,13 @@

78444

78445

(define_insn "*ldm3_db"

78446

[(match_parallel 0 "load_multiple_operation"

78447

- [(set (match_operand:SI 1 "arm_hard_register_operand" "")

78448

+ [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")

78449

(mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk")

78450

(const_int -12))))

78451

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78452

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

78453

(mem:SI (plus:SI (match_dup 4)

78454

(const_int -8))))

78455

- (set (match_operand:SI 3 "arm_hard_register_operand" "")

78456

+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")

78457

(mem:SI (plus:SI (match_dup 4)

78458

(const_int -4))))])]

78459

"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"

78460

@@ -710,13 +710,13 @@

78461

[(match_parallel 0 "load_multiple_operation"

78462

[(set (match_operand:SI 4 "s_register_operand" "+&rk")

78463

(plus:SI (match_dup 4) (const_int -12)))

78464

- (set (match_operand:SI 1 "arm_hard_register_operand" "")

78465

+ (set (match_operand:SI 1 "arm_hard_general_register_operand" "")

78466

(mem:SI (plus:SI (match_dup 4)

78467

(const_int -12))))

78468

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78469

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

78470

(mem:SI (plus:SI (match_dup 4)

78471

(const_int -8))))

78472

- (set (match_operand:SI 3 "arm_hard_register_operand" "")

78473

+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")

78474

(mem:SI (plus:SI (match_dup 4)

78475

(const_int -4))))])]

78476

"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"

78477

@@ -727,11 +727,11 @@

78478

(define_insn "*stm3_db"

78479

[(match_parallel 0 "store_multiple_operation"

78480

[(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int -12)))

78481

- (match_operand:SI 1 "arm_hard_register_operand" ""))

78482

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

78483

(set (mem:SI (plus:SI (match_dup 4) (const_int -8)))

78484

- (match_operand:SI 2 "arm_hard_register_operand" ""))

78485

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))

78486

(set (mem:SI (plus:SI (match_dup 4) (const_int -4)))

78487

- (match_operand:SI 3 "arm_hard_register_operand" ""))])]

78488

+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]

78489

"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"

78490

"stm%(db%)\t%4, {%1, %2, %3}"

78491

[(set_attr "type" "store3")

78492

@@ -742,11 +742,11 @@

78493

[(set (match_operand:SI 4 "s_register_operand" "+&rk")

78494

(plus:SI (match_dup 4) (const_int -12)))

78495

(set (mem:SI (plus:SI (match_dup 4) (const_int -12)))

78496

- (match_operand:SI 1 "arm_hard_register_operand" ""))

78497

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

78498

(set (mem:SI (plus:SI (match_dup 4) (const_int -8)))

78499

- (match_operand:SI 2 "arm_hard_register_operand" ""))

78500

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))

78501

(set (mem:SI (plus:SI (match_dup 4) (const_int -4)))

78502

- (match_operand:SI 3 "arm_hard_register_operand" ""))])]

78503

+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]

78504

"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"

78505

"stm%(db%)\t%4!, {%1, %2, %3}"

78506

[(set_attr "type" "store3")

78507

@@ -847,9 +847,9 @@

78508

78509

(define_insn "*ldm2_ia"

78510

[(match_parallel 0 "load_multiple_operation"

78511

- [(set (match_operand:SI 1 "arm_hard_register_operand" "")

78512

+ [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")

78513

(mem:SI (match_operand:SI 3 "s_register_operand" "rk")))

78514

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78515

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

78516

(mem:SI (plus:SI (match_dup 3)

78517

(const_int 4))))])]

78518

"TARGET_32BIT && XVECLEN (operands[0], 0) == 2"

78519

@@ -859,9 +859,9 @@

78520

78521

(define_insn "*thumb_ldm2_ia"

78522

[(match_parallel 0 "load_multiple_operation"

78523

- [(set (match_operand:SI 1 "arm_hard_register_operand" "")

78524

+ [(set (match_operand:SI 1 "low_register_operand" "")

78525

(mem:SI (match_operand:SI 3 "s_register_operand" "l")))

78526

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78527

+ (set (match_operand:SI 2 "low_register_operand" "")

78528

(mem:SI (plus:SI (match_dup 3)

78529

(const_int 4))))])]

78530

"TARGET_THUMB1 && XVECLEN (operands[0], 0) == 2"

78531

@@ -872,9 +872,9 @@

78532

[(match_parallel 0 "load_multiple_operation"

78533

[(set (match_operand:SI 3 "s_register_operand" "+&rk")

78534

(plus:SI (match_dup 3) (const_int 8)))

78535

- (set (match_operand:SI 1 "arm_hard_register_operand" "")

78536

+ (set (match_operand:SI 1 "arm_hard_general_register_operand" "")

78537

(mem:SI (match_dup 3)))

78538

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78539

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

78540

(mem:SI (plus:SI (match_dup 3)

78541

(const_int 4))))])]

78542

"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"

78543

@@ -886,9 +886,9 @@

78544

[(match_parallel 0 "load_multiple_operation"

78545

[(set (match_operand:SI 3 "s_register_operand" "+&l")

78546

(plus:SI (match_dup 3) (const_int 8)))

78547

- (set (match_operand:SI 1 "arm_hard_register_operand" "")

78548

+ (set (match_operand:SI 1 "low_register_operand" "")

78549

(mem:SI (match_dup 3)))

78550

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78551

+ (set (match_operand:SI 2 "low_register_operand" "")

78552

(mem:SI (plus:SI (match_dup 3)

78553

(const_int 4))))])]

78554

"TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3"

78555

@@ -898,9 +898,9 @@

78556

(define_insn "*stm2_ia"

78557

[(match_parallel 0 "store_multiple_operation"

78558

[(set (mem:SI (match_operand:SI 3 "s_register_operand" "rk"))

78559

- (match_operand:SI 1 "arm_hard_register_operand" ""))

78560

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

78561

(set (mem:SI (plus:SI (match_dup 3) (const_int 4)))

78562

- (match_operand:SI 2 "arm_hard_register_operand" ""))])]

78563

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]

78564

"TARGET_32BIT && XVECLEN (operands[0], 0) == 2"

78565

"stm%(ia%)\t%3, {%1, %2}"

78566

[(set_attr "type" "store2")

78567

@@ -911,9 +911,9 @@

78568

[(set (match_operand:SI 3 "s_register_operand" "+&rk")

78569

(plus:SI (match_dup 3) (const_int 8)))

78570

(set (mem:SI (match_dup 3))

78571

- (match_operand:SI 1 "arm_hard_register_operand" ""))

78572

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

78573

(set (mem:SI (plus:SI (match_dup 3) (const_int 4)))

78574

- (match_operand:SI 2 "arm_hard_register_operand" ""))])]

78575

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]

78576

"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"

78577

"stm%(ia%)\t%3!, {%1, %2}"

78578

[(set_attr "type" "store2")

78579

@@ -924,9 +924,9 @@

78580

[(set (match_operand:SI 3 "s_register_operand" "+&l")

78581

(plus:SI (match_dup 3) (const_int 8)))

78582

(set (mem:SI (match_dup 3))

78583

- (match_operand:SI 1 "arm_hard_register_operand" ""))

78584

+ (match_operand:SI 1 "low_register_operand" ""))

78585

(set (mem:SI (plus:SI (match_dup 3) (const_int 4)))

78586

- (match_operand:SI 2 "arm_hard_register_operand" ""))])]

78587

+ (match_operand:SI 2 "low_register_operand" ""))])]

78588

"TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3"

78589

"stm%(ia%)\t%3!, {%1, %2}"

78590

[(set_attr "type" "store2")])

78591

@@ -933,10 +933,10 @@

78592

78593

(define_insn "*ldm2_ib"

78594

[(match_parallel 0 "load_multiple_operation"

78595

- [(set (match_operand:SI 1 "arm_hard_register_operand" "")

78596

+ [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")

78597

(mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk")

78598

(const_int 4))))

78599

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78600

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

78601

(mem:SI (plus:SI (match_dup 3)

78602

(const_int 8))))])]

78603

"TARGET_ARM && XVECLEN (operands[0], 0) == 2"

78604

@@ -948,10 +948,10 @@

78605

[(match_parallel 0 "load_multiple_operation"

78606

[(set (match_operand:SI 3 "s_register_operand" "+&rk")

78607

(plus:SI (match_dup 3) (const_int 8)))

78608

- (set (match_operand:SI 1 "arm_hard_register_operand" "")

78609

+ (set (match_operand:SI 1 "arm_hard_general_register_operand" "")

78610

(mem:SI (plus:SI (match_dup 3)

78611

(const_int 4))))

78612

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78613

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

78614

(mem:SI (plus:SI (match_dup 3)

78615

(const_int 8))))])]

78616

"TARGET_ARM && XVECLEN (operands[0], 0) == 3"

78617

@@ -962,9 +962,9 @@

78618

(define_insn "*stm2_ib"

78619

[(match_parallel 0 "store_multiple_operation"

78620

[(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int 4)))

78621

- (match_operand:SI 1 "arm_hard_register_operand" ""))

78622

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

78623

(set (mem:SI (plus:SI (match_dup 3) (const_int 8)))

78624

- (match_operand:SI 2 "arm_hard_register_operand" ""))])]

78625

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]

78626

"TARGET_ARM && XVECLEN (operands[0], 0) == 2"

78627

"stm%(ib%)\t%3, {%1, %2}"

78628

[(set_attr "type" "store2")

78629

@@ -975,9 +975,9 @@

78630

[(set (match_operand:SI 3 "s_register_operand" "+&rk")

78631

(plus:SI (match_dup 3) (const_int 8)))

78632

(set (mem:SI (plus:SI (match_dup 3) (const_int 4)))

78633

- (match_operand:SI 1 "arm_hard_register_operand" ""))

78634

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

78635

(set (mem:SI (plus:SI (match_dup 3) (const_int 8)))

78636

- (match_operand:SI 2 "arm_hard_register_operand" ""))])]

78637

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]

78638

"TARGET_ARM && XVECLEN (operands[0], 0) == 3"

78639

"stm%(ib%)\t%3!, {%1, %2}"

78640

[(set_attr "type" "store2")

78641

@@ -985,10 +985,10 @@

78642

78643

(define_insn "*ldm2_da"

78644

[(match_parallel 0 "load_multiple_operation"

78645

- [(set (match_operand:SI 1 "arm_hard_register_operand" "")

78646

+ [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")

78647

(mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk")

78648

(const_int -4))))

78649

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78650

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

78651

(mem:SI (match_dup 3)))])]

78652

"TARGET_ARM && XVECLEN (operands[0], 0) == 2"

78653

"ldm%(da%)\t%3, {%1, %2}"

78654

@@ -999,10 +999,10 @@

78655

[(match_parallel 0 "load_multiple_operation"

78656

[(set (match_operand:SI 3 "s_register_operand" "+&rk")

78657

(plus:SI (match_dup 3) (const_int -8)))

78658

- (set (match_operand:SI 1 "arm_hard_register_operand" "")

78659

+ (set (match_operand:SI 1 "arm_hard_general_register_operand" "")

78660

(mem:SI (plus:SI (match_dup 3)

78661

(const_int -4))))

78662

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78663

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

78664

(mem:SI (match_dup 3)))])]

78665

"TARGET_ARM && XVECLEN (operands[0], 0) == 3"

78666

"ldm%(da%)\t%3!, {%1, %2}"

78667

@@ -1012,9 +1012,9 @@

78668

(define_insn "*stm2_da"

78669

[(match_parallel 0 "store_multiple_operation"

78670

[(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int -4)))

78671

- (match_operand:SI 1 "arm_hard_register_operand" ""))

78672

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

78673

(set (mem:SI (match_dup 3))

78674

- (match_operand:SI 2 "arm_hard_register_operand" ""))])]

78675

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]

78676

"TARGET_ARM && XVECLEN (operands[0], 0) == 2"

78677

"stm%(da%)\t%3, {%1, %2}"

78678

[(set_attr "type" "store2")

78679

@@ -1025,9 +1025,9 @@

78680

[(set (match_operand:SI 3 "s_register_operand" "+&rk")

78681

(plus:SI (match_dup 3) (const_int -8)))

78682

(set (mem:SI (plus:SI (match_dup 3) (const_int -4)))

78683

- (match_operand:SI 1 "arm_hard_register_operand" ""))

78684

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

78685

(set (mem:SI (match_dup 3))

78686

- (match_operand:SI 2 "arm_hard_register_operand" ""))])]

78687

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]

78688

"TARGET_ARM && XVECLEN (operands[0], 0) == 3"

78689

"stm%(da%)\t%3!, {%1, %2}"

78690

[(set_attr "type" "store2")

78691

@@ -1035,10 +1035,10 @@

78692

78693

(define_insn "*ldm2_db"

78694

[(match_parallel 0 "load_multiple_operation"

78695

- [(set (match_operand:SI 1 "arm_hard_register_operand" "")

78696

+ [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")

78697

(mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk")

78698

(const_int -8))))

78699

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78700

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

78701

(mem:SI (plus:SI (match_dup 3)

78702

(const_int -4))))])]

78703

"TARGET_32BIT && XVECLEN (operands[0], 0) == 2"

78704

@@ -1050,10 +1050,10 @@

78705

[(match_parallel 0 "load_multiple_operation"

78706

[(set (match_operand:SI 3 "s_register_operand" "+&rk")

78707

(plus:SI (match_dup 3) (const_int -8)))

78708

- (set (match_operand:SI 1 "arm_hard_register_operand" "")

78709

+ (set (match_operand:SI 1 "arm_hard_general_register_operand" "")

78710

(mem:SI (plus:SI (match_dup 3)

78711

(const_int -8))))

78712

- (set (match_operand:SI 2 "arm_hard_register_operand" "")

78713

+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")

78714

(mem:SI (plus:SI (match_dup 3)

78715

(const_int -4))))])]

78716

"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"

78717

@@ -1064,9 +1064,9 @@

78718

(define_insn "*stm2_db"

78719

[(match_parallel 0 "store_multiple_operation"

78720

[(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int -8)))

78721

- (match_operand:SI 1 "arm_hard_register_operand" ""))

78722

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

78723

(set (mem:SI (plus:SI (match_dup 3) (const_int -4)))

78724

- (match_operand:SI 2 "arm_hard_register_operand" ""))])]

78725

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]

78726

"TARGET_32BIT && XVECLEN (operands[0], 0) == 2"

78727

"stm%(db%)\t%3, {%1, %2}"

78728

[(set_attr "type" "store2")

78729

@@ -1077,9 +1077,9 @@

78730

[(set (match_operand:SI 3 "s_register_operand" "+&rk")

78731

(plus:SI (match_dup 3) (const_int -8)))

78732

(set (mem:SI (plus:SI (match_dup 3) (const_int -8)))

78733

- (match_operand:SI 1 "arm_hard_register_operand" ""))

78734

+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))

78735

(set (mem:SI (plus:SI (match_dup 3) (const_int -4)))

78736

- (match_operand:SI 2 "arm_hard_register_operand" ""))])]

78737

+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]

78738

"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"

78739

"stm%(db%)\t%3!, {%1, %2}"

78740

[(set_attr "type" "store2")

78741

Index: gcc/config/arm/predicates.md

78742

===================================================================

78743

--- a/src/gcc/config/arm/predicates.md (.../tags/gcc_4_8_2_release)

78744

+++ b/src/gcc/config/arm/predicates.md (.../branches/gcc-4_8-branch)

78745

@@ -31,11 +31,11 @@

78746

|| REGNO_REG_CLASS (REGNO (op)) != NO_REGS));

78747

})

78748

78749

-;; Any hard register.

78750

-(define_predicate "arm_hard_register_operand"

78751

+;; Any general register.

78752

+(define_predicate "arm_hard_general_register_operand"

78753

(match_code "reg")

78754

{

78755

- return REGNO (op) < FIRST_PSEUDO_REGISTER;

78756

+ return REGNO (op) <= LAST_ARM_REGNUM;

78757

})

78758

78759

;; A low register.

78760

@@ -76,6 +76,12 @@

78761

&& REGNO_REG_CLASS (REGNO (op)) == VFP_REGS)));

78762

})

78763

78764

+(define_predicate "vfp_hard_register_operand"

78765

+ (match_code "reg")

78766

+{

78767

+ return (IS_VFP_REGNUM (REGNO (op)));

78768

+})

78769

+

78770

(define_predicate "zero_operand"

78771

(and (match_code "const_int,const_double,const_vector")

78772

(match_test "op == CONST0_RTX (mode)")))

78773

Index: gcc/config/arm/arm-ldmstm.ml

78774

===================================================================

78775

--- a/src/gcc/config/arm/arm-ldmstm.ml (.../tags/gcc_4_8_2_release)

78776

+++ b/src/gcc/config/arm/arm-ldmstm.ml (.../branches/gcc-4_8-branch)

78777

@@ -67,10 +67,13 @@

78778

Printf.sprintf ("(match_operand:SI %d \"s_register_operand\" \"%s%s\")")

78779

(nregs + 1) (inout_constr op_type) (constr thumb)

78780

78781

+let reg_predicate thumb =

78782

+ if thumb then "low_register_operand" else "arm_hard_general_register_operand"

78783

+

78784

let write_ldm_set thumb nregs offset opnr first =

78785

let indent = " " in

78786

Printf.printf "%s" (if first then " [" else indent);

78787

- Printf.printf "(set (match_operand:SI %d \"arm_hard_register_operand\" \"\")\n" opnr;

78788

+ Printf.printf "(set (match_operand:SI %d \"%s\" \"\")\n" opnr (reg_predicate thumb);

78789

Printf.printf "%s (mem:SI " indent;

78790

begin if offset != 0 then Printf.printf "(plus:SI " end;

78791

Printf.printf "%s" (destreg nregs first IN thumb);

78792

@@ -84,7 +87,7 @@

78793

begin if offset != 0 then Printf.printf "(plus:SI " end;

78794

Printf.printf "%s" (destreg nregs first IN thumb);

78795

begin if offset != 0 then Printf.printf " (const_int %d))" offset end;

78796

- Printf.printf ")\n%s (match_operand:SI %d \"arm_hard_register_operand\" \"\"))" indent opnr

78797

+ Printf.printf ")\n%s (match_operand:SI %d \"%s\" \"\"))" indent opnr (reg_predicate thumb)

78798

78799

let write_ldm_peep_set extra_indent nregs opnr first =

78800

let indent = " " ^ extra_indent in

78801

Index: gcc/config/arm/iterators.md

78802

===================================================================

78803

--- a/src/gcc/config/arm/iterators.md (.../tags/gcc_4_8_2_release)

78804

+++ b/src/gcc/config/arm/iterators.md (.../branches/gcc-4_8-branch)

78805

@@ -493,6 +493,10 @@

78806

(UNSPEC_VRINTA "no") (UNSPEC_VRINTM "no")

78807

(UNSPEC_VRINTR "yes") (UNSPEC_VRINTX "yes")])

78808

78809

+(define_int_attr vrint_conds [(UNSPEC_VRINTZ "nocond") (UNSPEC_VRINTP "unconditional")

78810

+ (UNSPEC_VRINTA "unconditional") (UNSPEC_VRINTM "unconditional")

78811

+ (UNSPEC_VRINTR "nocond") (UNSPEC_VRINTX "nocond")])

78812

+

78813

(define_int_attr nvrint_variant [(UNSPEC_NVRINTZ "z") (UNSPEC_NVRINTP "p")

78814

(UNSPEC_NVRINTA "a") (UNSPEC_NVRINTM "m")

78815

(UNSPEC_NVRINTX "x") (UNSPEC_NVRINTN "n")])

78816

Index: gcc/config/arm/arm.md

78817

===================================================================

78818

--- a/src/gcc/config/arm/arm.md (.../tags/gcc_4_8_2_release)

78819

+++ b/src/gcc/config/arm/arm.md (.../branches/gcc-4_8-branch)

78820

@@ -11036,7 +11036,7 @@

78821

[(set (match_operand:SI 1 "s_register_operand" "+rk")

78822

(plus:SI (match_dup 1)

78823

(match_operand:SI 2 "const_int_operand" "I")))

78824

- (set (match_operand:DF 3 "arm_hard_register_operand" "")

78825

+ (set (match_operand:DF 3 "vfp_hard_register_operand" "")

78826

(mem:DF (match_dup 1)))])]

78827

"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"

78828

"*

78829

@@ -11270,7 +11270,9 @@

78830

(match_operand:SI 1 "" "")

78831

(match_operand:SI 2 "" ""))]

78832

"TARGET_32BIT && arm_arch5e"

78833

- "pld\\t%a0")

78834

+ "pld\\t%a0"

78835

+ [(set_attr "type" "load1")]

78836

+)

78837

78838

;; General predication pattern

78839

78840

Index: gcc/config/pa/pa.c

78841

===================================================================

78842

--- a/src/gcc/config/pa/pa.c (.../tags/gcc_4_8_2_release)

78843

+++ b/src/gcc/config/pa/pa.c (.../branches/gcc-4_8-branch)

78844

@@ -912,9 +912,12 @@

78845

legitimize_tls_address (rtx addr)

78846

{

78847

rtx ret, insn, tmp, t1, t2, tp;

78848

- enum tls_model model = SYMBOL_REF_TLS_MODEL (addr);

78849

78850

- switch (model)

78851

+ /* Currently, we can't handle anything but a SYMBOL_REF. */

78852

+ if (GET_CODE (addr) != SYMBOL_REF)

78853

+ return addr;

78854

+

78855

+ switch (SYMBOL_REF_TLS_MODEL (addr))

78856

{

78857

case TLS_MODEL_GLOBAL_DYNAMIC:

78858

tmp = gen_reg_rtx (Pmode);

78859

@@ -1035,7 +1038,7 @@

78860

&& !REG_POINTER (XEXP (x, 1)))

78861

return gen_rtx_PLUS (Pmode, XEXP (x, 1), XEXP (x, 0));

78862

78863

- if (PA_SYMBOL_REF_TLS_P (x))

78864

+ if (pa_tls_referenced_p (x))

78865

return legitimize_tls_address (x);

78866

else if (flag_pic)

78867

return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));

78868

@@ -1916,9 +1919,10 @@

78869

not consider them legitimate constants. Loop optimizations can

78870

call the emit_move_xxx with one as a source. */

78871

if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))

78872

+ || (GET_CODE (operand1) == HIGH

78873

+ && symbolic_operand (XEXP (operand1, 0), mode))

78874

|| function_label_operand (operand1, VOIDmode)

78875

- || (GET_CODE (operand1) == HIGH

78876

- && symbolic_operand (XEXP (operand1, 0), mode)))

78877

+ || pa_tls_referenced_p (operand1))

78878

{

78879

int ishighonly = 0;

78880

78881

@@ -2625,7 +2629,7 @@

78882

if (optype0 == REGOP)

78883

latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);

78884

else if (optype0 == OFFSOP)

78885

- latehalf[0] = adjust_address (operands[0], SImode, 4);

78886

+ latehalf[0] = adjust_address_nv (operands[0], SImode, 4);

78887

else

78888

latehalf[0] = operands[0];

78889

78890

@@ -2632,7 +2636,7 @@

78891

if (optype1 == REGOP)

78892

latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);

78893

else if (optype1 == OFFSOP)

78894

- latehalf[1] = adjust_address (operands[1], SImode, 4);

78895

+ latehalf[1] = adjust_address_nv (operands[1], SImode, 4);

78896

else if (optype1 == CNSTOP)

78897

split_double (operands[1], &operands[1], &latehalf[1]);

78898

else

78899

@@ -7539,7 +7543,7 @@

78900

if (!TARGET_LONG_CALLS && distance < MAX_PCREL17F_OFFSET)

78901

return 8;

78902

78903

- if (TARGET_LONG_ABS_CALL && !flag_pic)

78904

+ if (!flag_pic)

78905

return 12;

78906

78907

return 24;

78908

@@ -8104,7 +8108,8 @@

78909

return 12;

78910

78911

if (TARGET_FAST_INDIRECT_CALLS

78912

- || (!TARGET_PORTABLE_RUNTIME

78913

+ || (!TARGET_LONG_CALLS

78914

+ && !TARGET_PORTABLE_RUNTIME

78915

&& ((TARGET_PA_20 && !TARGET_SOM && distance < 7600000)

78916

|| distance < MAX_PCREL17F_OFFSET)))

78917

return 8;

78918

@@ -10397,7 +10402,7 @@

78919

/* TLS_MODEL_GLOBAL_DYNAMIC and TLS_MODEL_LOCAL_DYNAMIC are not

78920

legitimate constants. The other variants can't be handled by

78921

the move patterns after reload starts. */

78922

- if (PA_SYMBOL_REF_TLS_P (x))

78923

+ if (pa_tls_referenced_p (x))

78924

return false;

78925

78926

if (TARGET_64BIT && GET_CODE (x) == CONST_DOUBLE)

78927

@@ -10522,13 +10527,13 @@

78928

78929

/* When INT14_OK_STRICT is false, a secondary reload is needed

78930

to adjust the displacement of SImode and DImode floating point

78931

- instructions. So, we return false when STRICT is true. We

78932

+ instructions but this may fail when the register also needs

78933

+ reloading. So, we return false when STRICT is true. We

78934

also reject long displacements for float mode addresses since

78935

the majority of accesses will use floating point instructions

78936

that don't support 14-bit offsets. */

78937

if (!INT14_OK_STRICT

78938

- && reload_in_progress

78939

- && strict

78940

+ && (strict || !(reload_in_progress || reload_completed))

78941

&& mode != QImode

78942

&& mode != HImode)

78943

return false;

78944

@@ -10588,8 +10593,7 @@

78945

return true;

78946

78947

if (!INT14_OK_STRICT

78948

- && reload_in_progress

78949

- && strict

78950

+ && (strict || !(reload_in_progress || reload_completed))

78951

&& mode != QImode

78952

&& mode != HImode)

78953

return false;

78954

Index: gcc/config/pa/pa.h

78955

===================================================================

78956

--- a/src/gcc/config/pa/pa.h (.../tags/gcc_4_8_2_release)

78957

+++ b/src/gcc/config/pa/pa.h (.../branches/gcc-4_8-branch)

78958

@@ -784,9 +784,9 @@

78959

78960

#define MAX_REGS_PER_ADDRESS 2

78961

78962

-/* Non-TLS symbolic references. */

78963

-#define PA_SYMBOL_REF_TLS_P(RTX) \

78964

- (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)

78965

+/* TLS symbolic reference. */

78966

+#define PA_SYMBOL_REF_TLS_P(X) \

78967

+ (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (X) != 0)

78968

78969

/* Recognize any constant value that is a valid address except

78970

for symbolic addresses. We get better CSE by rejecting them

78971

@@ -796,7 +796,8 @@

78972

#define CONSTANT_ADDRESS_P(X) \

78973

((GET_CODE (X) == LABEL_REF \

78974

|| (GET_CODE (X) == SYMBOL_REF && !SYMBOL_REF_TLS_MODEL (X)) \

78975

- || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \

78976

+ || GET_CODE (X) == CONST_INT \

78977

+ || (GET_CODE (X) == CONST && !pa_tls_referenced_p (X)) \

78978

|| GET_CODE (X) == HIGH) \

78979

&& (reload_in_progress || reload_completed \

78980

|| ! pa_symbolic_expression_p (X)))

78981

Index: gcc/config/mips/driver-native.c

78982

===================================================================

78983

--- a/src/gcc/config/mips/driver-native.c (.../tags/gcc_4_8_2_release)

78984

+++ b/src/gcc/config/mips/driver-native.c (.../branches/gcc-4_8-branch)

78985

@@ -58,11 +58,17 @@

78986

if (strncmp (buf, "cpu model", sizeof ("cpu model") - 1) == 0)

78987

{

78988

if (strstr (buf, "Godson2 V0.2") != NULL

78989

- || strstr (buf, "Loongson-2 V0.2") != NULL)

78990

+ || strstr (buf, "Loongson-2 V0.2") != NULL

78991

+ || strstr (buf, "Loongson-2E") != NULL)

78992

cpu = "loongson2e";

78993

else if (strstr (buf, "Godson2 V0.3") != NULL

78994

- || strstr (buf, "Loongson-2 V0.3") != NULL)

78995

+ || strstr (buf, "Loongson-2 V0.3") != NULL

78996

+ || strstr (buf, "Loongson-2F") != NULL)

78997

cpu = "loongson2f";

78998

+ else if (strstr (buf, "Godson3 V0.5") != NULL

78999

+ || strstr (buf, "Loongson-3 V0.5") != NULL

79000

+ || strstr (buf, "Loongson-3A") != NULL)

79001

+ cpu = "loongson3a";

79002

else if (strstr (buf, "SiByte SB1") != NULL)

79003

cpu = "sb1";

79004

else if (strstr (buf, "R5000") != NULL)

79005

Index: gcc/config/mips/mips.md

79006

===================================================================

79007

--- a/src/gcc/config/mips/mips.md (.../tags/gcc_4_8_2_release)

79008

+++ b/src/gcc/config/mips/mips.md (.../branches/gcc-4_8-branch)

79009

@@ -73,6 +73,11 @@

79010

UNSPEC_STORE_LEFT

79011

UNSPEC_STORE_RIGHT

79012

79013

+ ;; Integer operations that are too cumbersome to describe directly.

79014

+ UNSPEC_WSBH

79015

+ UNSPEC_DSBH

79016

+ UNSPEC_DSHD

79017

+

79018

;; Floating-point moves.

79019

UNSPEC_LOAD_LOW

79020

UNSPEC_LOAD_HIGH

79021

@@ -1294,20 +1299,32 @@

79022

79023

;; Combiner patterns for unsigned byte-add.

79024

79025

-(define_insn "*baddu_si"

79026

+(define_insn "*baddu_si_eb"

79027

[(set (match_operand:SI 0 "register_operand" "=d")

79028

(zero_extend:SI

79029

- (plus:QI (match_operand:QI 1 "register_operand" "d")

79030

- (match_operand:QI 2 "register_operand" "d"))))]

79031

- "ISA_HAS_BADDU"

79032

+ (subreg:QI

79033

+ (plus:SI (match_operand:SI 1 "register_operand" "d")

79034

+ (match_operand:SI 2 "register_operand" "d")) 3)))]

79035

+ "ISA_HAS_BADDU && BYTES_BIG_ENDIAN"

79036

"baddu\\t%0,%1,%2"

79037

[(set_attr "alu_type" "add")])

79038

79039

+(define_insn "*baddu_si_el"

79040

+ [(set (match_operand:SI 0 "register_operand" "=d")

79041

+ (zero_extend:SI

79042

+ (subreg:QI

79043

+ (plus:SI (match_operand:SI 1 "register_operand" "d")

79044

+ (match_operand:SI 2 "register_operand" "d")) 0)))]

79045

+ "ISA_HAS_BADDU && !BYTES_BIG_ENDIAN"

79046

+ "baddu\\t%0,%1,%2"

79047

+ [(set_attr "alu_type" "add")])

79048

+

79049

(define_insn "*baddu_di<mode>"

79050

[(set (match_operand:GPR 0 "register_operand" "=d")

79051

(zero_extend:GPR

79052

- (plus:QI (truncate:QI (match_operand:DI 1 "register_operand" "d"))

79053

- (truncate:QI (match_operand:DI 2 "register_operand" "d")))))]

79054

+ (truncate:QI

79055

+ (plus:DI (match_operand:DI 1 "register_operand" "d")

79056

+ (match_operand:DI 2 "register_operand" "d")))))]

79057

"ISA_HAS_BADDU && TARGET_64BIT"

79058

"baddu\\t%0,%1,%2"

79059

[(set_attr "alu_type" "add")])

79060

@@ -5367,6 +5384,56 @@

79061

}

79062

[(set_attr "type" "shift")

79063

(set_attr "mode" "<MODE>")])

79064

+

79065

+(define_insn "bswaphi2"

79066

+ [(set (match_operand:HI 0 "register_operand" "=d")

79067

+ (bswap:HI (match_operand:HI 1 "register_operand" "d")))]

79068

+ "ISA_HAS_WSBH"

79069

+ "wsbh\t%0,%1"

79070

+ [(set_attr "type" "shift")])

79071

+

79072

+(define_insn_and_split "bswapsi2"

79073

+ [(set (match_operand:SI 0 "register_operand" "=d")

79074

+ (bswap:SI (match_operand:SI 1 "register_operand" "d")))]

79075

+ "ISA_HAS_WSBH && ISA_HAS_ROR"

79076

+ "#"

79077

+ ""

79078

+ [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_WSBH))

79079

+ (set (match_dup 0) (rotatert:SI (match_dup 0) (const_int 16)))]

79080

+ ""

79081

+ [(set_attr "length" "8")])

79082

+

79083

+(define_insn_and_split "bswapdi2"

79084

+ [(set (match_operand:DI 0 "register_operand" "=d")

79085

+ (bswap:DI (match_operand:DI 1 "register_operand" "d")))]

79086

+ "TARGET_64BIT && ISA_HAS_WSBH"

79087

+ "#"

79088

+ ""

79089

+ [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_DSBH))

79090

+ (set (match_dup 0) (unspec:DI [(match_dup 0)] UNSPEC_DSHD))]

79091

+ ""

79092

+ [(set_attr "length" "8")])

79093

+

79094

+(define_insn "wsbh"

79095

+ [(set (match_operand:SI 0 "register_operand" "=d")

79096

+ (unspec:SI [(match_operand:SI 1 "register_operand" "d")] UNSPEC_WSBH))]

79097

+ "ISA_HAS_WSBH"

79098

+ "wsbh\t%0,%1"

79099

+ [(set_attr "type" "shift")])

79100

+

79101

+(define_insn "dsbh"

79102

+ [(set (match_operand:DI 0 "register_operand" "=d")

79103

+ (unspec:DI [(match_operand:DI 1 "register_operand" "d")] UNSPEC_DSBH))]

79104

+ "TARGET_64BIT && ISA_HAS_WSBH"

79105

+ "dsbh\t%0,%1"

79106

+ [(set_attr "type" "shift")])

79107

+

79108

+(define_insn "dshd"

79109

+ [(set (match_operand:DI 0 "register_operand" "=d")

79110

+ (unspec:DI [(match_operand:DI 1 "register_operand" "d")] UNSPEC_DSHD))]

79111

+ "TARGET_64BIT && ISA_HAS_WSBH"

79112

+ "dshd\t%0,%1"

79113

+ [(set_attr "type" "shift")])

79114

79115

;;

79116

;; ....................

79117

Index: gcc/config/mips/mips.c

79118

===================================================================

79119

--- a/src/gcc/config/mips/mips.c (.../tags/gcc_4_8_2_release)

79120

+++ b/src/gcc/config/mips/mips.c (.../branches/gcc-4_8-branch)

79121

@@ -3560,17 +3560,6 @@

79122

}

79123

}

79124

79125

-/* Return the cost of an operand X that can be trucated for free.

79126

- SPEED says whether we're optimizing for size or speed. */

79127

-

79128

-static int

79129

-mips_truncated_op_cost (rtx x, bool speed)

79130

-{

79131

- if (GET_CODE (x) == TRUNCATE)

79132

- x = XEXP (x, 0);

79133

- return set_src_cost (x, speed);

79134

-}

79135

-

79136

/* Implement TARGET_RTX_COSTS. */

79137

79138

static bool

79139

@@ -3951,13 +3940,12 @@

79140

case ZERO_EXTEND:

79141

if (outer_code == SET

79142

&& ISA_HAS_BADDU

79143

+ && (GET_CODE (XEXP (x, 0)) == TRUNCATE

79144

+ || GET_CODE (XEXP (x, 0)) == SUBREG)

79145

&& GET_MODE (XEXP (x, 0)) == QImode

79146

- && GET_CODE (XEXP (x, 0)) == PLUS)

79147

+ && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)

79148

{

79149

- rtx plus = XEXP (x, 0);

79150

- *total = (COSTS_N_INSNS (1)

79151

- + mips_truncated_op_cost (XEXP (plus, 0), speed)

79152

- + mips_truncated_op_cost (XEXP (plus, 1), speed));

79153

+ *total = set_src_cost (XEXP (XEXP (x, 0), 0), speed);

79154

return true;

79155

}

79156

*total = mips_zero_extend_cost (mode, XEXP (x, 0));

79157

@@ -8057,7 +8045,7 @@

79158

case 't':

79159

{

79160

int truth = (code == NE) == (letter == 'T');

79161

- fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);

79162

+ fputc ("zfnt"[truth * 2 + ST_REG_P (REGNO (XEXP (op, 0)))], file);

79163

}

79164

break;

79165

79166

Index: gcc/config/mips/mips.h

79167

===================================================================

79168

--- a/src/gcc/config/mips/mips.h (.../tags/gcc_4_8_2_release)

79169

+++ b/src/gcc/config/mips/mips.h (.../branches/gcc-4_8-branch)

79170

@@ -949,6 +949,11 @@

79171

|| TARGET_SMARTMIPS) \

79172

&& !TARGET_MIPS16)

79173

79174

+/* ISA has the WSBH (word swap bytes within halfwords) instruction.

79175

+ 64-bit targets also provide DSBH and DSHD. */

79176

+#define ISA_HAS_WSBH ((ISA_MIPS32R2 || ISA_MIPS64R2) \

79177

+ && !TARGET_MIPS16)

79178

+

79179

/* ISA has data prefetch instructions. This controls use of 'pref'. */

79180

#define ISA_HAS_PREFETCH ((ISA_MIPS4 \

79181

|| TARGET_LOONGSON_2EF \

79182

Index: gcc/params.def

79183

===================================================================

79184

--- a/src/gcc/params.def (.../tags/gcc_4_8_2_release)

79185

+++ b/src/gcc/params.def (.../branches/gcc-4_8-branch)

79186

@@ -1014,6 +1014,12 @@

79187

"strength reduction",

79188

50, 1, 999999)

79189

79190

+DEFPARAM (PARAM_UNINIT_CONTROL_DEP_ATTEMPTS,

79191

+ "uninit-control-dep-attempts",

79192

+ "Maximum number of nested calls to search for control dependencies "

79193

+ "during uninitialized variable analysis",

79194

+ 1000, 1, 0)

79195

+

79196

/*

79197

Local variables:

79198

mode:c

79199

Index: gcc/tree-ssanames.c

79200

===================================================================

79201

--- a/src/gcc/tree-ssanames.c (.../tags/gcc_4_8_2_release)

79202

+++ b/src/gcc/tree-ssanames.c (.../branches/gcc-4_8-branch)

79203

@@ -128,7 +128,7 @@

79204

79205

/* The node was cleared out when we put it on the free list, so

79206

there is no need to do so again here. */

79207

- gcc_assert (ssa_name (SSA_NAME_VERSION (t)) == NULL);

79208

+ gcc_assert ((*SSANAMES (fn))[SSA_NAME_VERSION (t)] == NULL);

79209

(*SSANAMES (fn))[SSA_NAME_VERSION (t)] = t;

79210

}

79211

else

79212

Index: gcc/regcprop.c

79213

===================================================================

79214

--- a/src/gcc/regcprop.c (.../tags/gcc_4_8_2_release)

79215

+++ b/src/gcc/regcprop.c (.../branches/gcc-4_8-branch)

79216

@@ -747,6 +747,7 @@

79217

int n_ops, i, alt, predicated;

79218

bool is_asm, any_replacements;

79219

rtx set;

79220

+ rtx link;

79221

bool replaced[MAX_RECOG_OPERANDS];

79222

bool changed = false;

79223

struct kill_set_value_data ksvd;

79224

@@ -815,6 +816,23 @@

79225

if (recog_op_alt[i][alt].earlyclobber)

79226

kill_value (recog_data.operand[i], vd);

79227

79228

+ /* If we have dead sets in the insn, then we need to note these as we

79229

+ would clobbers. */

79230

+ for (link = REG_NOTES (insn); link; link = XEXP (link, 1))

79231

+ {

79232

+ if (REG_NOTE_KIND (link) == REG_UNUSED)

79233

+ {

79234

+ kill_value (XEXP (link, 0), vd);

79235

+ /* Furthermore, if the insn looked like a single-set,

79236

+ but the dead store kills the source value of that

79237

+ set, then we can no-longer use the plain move

79238

+ special case below. */

79239

+ if (set

79240

+ && reg_overlap_mentioned_p (XEXP (link, 0), SET_SRC (set)))

79241

+ set = NULL;

79242

+ }

79243

+ }

79244

+

79245

/* Special-case plain move instructions, since we may well

79246

be able to do the move from a different register class. */

79247

if (set && REG_P (SET_SRC (set)))

79248

Index: gcc/tree-ssa-operands.c

79249

===================================================================

79250

--- a/src/gcc/tree-ssa-operands.c (.../tags/gcc_4_8_2_release)

79251

+++ b/src/gcc/tree-ssa-operands.c (.../branches/gcc-4_8-branch)

79252

@@ -626,10 +626,8 @@

79253

call-clobbered. */

79254

if (!(call_flags & ECF_NOVOPS))

79255

{

79256

- /* A 'pure' or a 'const' function never call-clobbers anything.

79257

- A 'noreturn' function might, but since we don't return anyway

79258

- there is no point in recording that. */

79259

- if (!(call_flags & (ECF_PURE | ECF_CONST | ECF_NORETURN)))

79260

+ /* A 'pure' or a 'const' function never call-clobbers anything. */

79261

+ if (!(call_flags & (ECF_PURE | ECF_CONST)))

79262

add_virtual_operand (stmt, opf_def);

79263

else if (!(call_flags & ECF_CONST))

79264

add_virtual_operand (stmt, opf_use);

79265

Index: libgo/configure

79266

===================================================================

79267

--- a/src/libgo/configure (.../tags/gcc_4_8_2_release)

79268

+++ b/src/libgo/configure (.../branches/gcc-4_8-branch)

79269

@@ -6501,7 +6501,7 @@

79270

rm -rf conftest*

79271

;;

79272

79273

-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \

79274

+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \

79275

s390*-*linux*|s390*-*tpf*|sparc*-*linux*)

79276

# Find out which ABI we are using.

79277

echo 'int i;' > conftest.$ac_ext

79278

@@ -6519,7 +6519,10 @@

79279

x86_64-*linux*)

79280

LD="${LD-ld} -m elf_i386"

79281

;;

79282

- ppc64-*linux*|powerpc64-*linux*)

79283

+ powerpc64le-*linux*)

79284

+ LD="${LD-ld} -m elf32lppclinux"

79285

+ ;;

79286

+ powerpc64-*linux*)

79287

LD="${LD-ld} -m elf32ppclinux"

79288

;;

79289

s390x-*linux*)

79290

@@ -6538,7 +6541,10 @@

79291

x86_64-*linux*)

79292

LD="${LD-ld} -m elf_x86_64"

79293

;;

79294

- ppc*-*linux*|powerpc*-*linux*)

79295

+ powerpcle-*linux*)

79296

+ LD="${LD-ld} -m elf64lppc"

79297

+ ;;

79298

+ powerpc-*linux*)

79299

LD="${LD-ld} -m elf64ppc"

79300

;;

79301

s390*-*linux*|s390*-*tpf*)

79302

@@ -11105,7 +11111,7 @@

79303

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

79304

lt_status=$lt_dlunknown

79305

cat > conftest.$ac_ext <<_LT_EOF

79306

-#line 11108 "configure"

79307

+#line 11114 "configure"

79308

#include "confdefs.h"

79309

79310

#if HAVE_DLFCN_H

79311

@@ -11211,7 +11217,7 @@

79312

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

79313

lt_status=$lt_dlunknown

79314

cat > conftest.$ac_ext <<_LT_EOF

79315

-#line 11214 "configure"

79316

+#line 11220 "configure"

79317

#include "confdefs.h"

79318

79319

#if HAVE_DLFCN_H

79320

@@ -14700,7 +14706,7 @@

79321

fi

79322

79323

79324

-for ac_func in accept4 epoll_create1 faccessat fallocate fchmodat fchownat futimesat inotify_add_watch inotify_init inotify_init1 inotify_rm_watch mkdirat mknodat openat pipe2 renameat sync_file_range splice tee unlinkat unshare utimensat

79325

+for ac_func in accept4 dup3 epoll_create1 faccessat fallocate fchmodat fchownat futimesat getxattr inotify_add_watch inotify_init inotify_init1 inotify_rm_watch listxattr mkdirat mknodat openat pipe2 removexattr renameat setxattr sync_file_range splice tee unlinkat unshare utimensat

79326

do :

79327

as_ac_var=`$as_echo "ac_cv_func_$ac_func" | $as_tr_sh`

79328

ac_fn_c_check_func "$LINENO" "$ac_func" "$as_ac_var"

79329

Index: libgo/Makefile.in

79330

===================================================================

79331

--- a/src/libgo/Makefile.in (.../tags/gcc_4_8_2_release)

79332

+++ b/src/libgo/Makefile.in (.../branches/gcc-4_8-branch)

79333

@@ -195,7 +195,7 @@

79334

@LIBGO_IS_LINUX_TRUE@am__objects_5 = getncpu-linux.lo

79335

am__objects_6 = go-append.lo go-assert.lo go-assert-interface.lo \

79336

go-byte-array-to-string.lo go-breakpoint.lo go-caller.lo \

79337

- go-callers.lo go-can-convert-interface.lo go-cgo.lo \

79338

+ go-callers.lo go-can-convert-interface.lo go-cdiv.lo go-cgo.lo \

79339

go-check-interface.lo go-construct-map.lo \

79340

go-convert-interface.lo go-copy.lo go-defer.lo \

79341

go-deferred-recover.lo go-eface-compare.lo \

79342

@@ -757,6 +757,7 @@

79343

runtime/go-caller.c \

79344

runtime/go-callers.c \

79345

runtime/go-can-convert-interface.c \

79346

+ runtime/go-cdiv.c \

79347

runtime/go-cgo.c \

79348

runtime/go-check-interface.c \

79349

runtime/go-construct-map.c \

79350

@@ -1446,7 +1447,7 @@

79351

go/go/build/build.go \

79352

go/go/build/doc.go \

79353

go/go/build/read.go \

79354

- syslist.go

79355

+ go/go/build/syslist.go

79356

79357

go_go_doc_files = \

79358

go/go/doc/comment.go \

79359

@@ -2368,6 +2369,7 @@

79360

@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/go-caller.Plo@am__quote@

79361

@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/go-callers.Plo@am__quote@

79362

@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/go-can-convert-interface.Plo@am__quote@

79363

+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/go-cdiv.Plo@am__quote@

79364

@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/go-cgo.Plo@am__quote@

79365

@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/go-check-interface.Plo@am__quote@

79366

@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/go-construct-map.Plo@am__quote@

79367

@@ -2554,6 +2556,13 @@

79368

@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@

79369

@am__fastdepCC_FALSE@ $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o go-can-convert-interface.lo `test -f 'runtime/go-can-convert-interface.c' || echo '$(srcdir)/'`runtime/go-can-convert-interface.c

79370

79371

+go-cdiv.lo: runtime/go-cdiv.c

79372

+@am__fastdepCC_TRUE@ $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT go-cdiv.lo -MD -MP -MF $(DEPDIR)/go-cdiv.Tpo -c -o go-cdiv.lo `test -f 'runtime/go-cdiv.c' || echo '$(srcdir)/'`runtime/go-cdiv.c

79373

+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/go-cdiv.Tpo $(DEPDIR)/go-cdiv.Plo

79374

+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='runtime/go-cdiv.c' object='go-cdiv.lo' libtool=yes @AMDEPBACKSLASH@

79375

+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@

79376

+@am__fastdepCC_FALSE@ $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o go-cdiv.lo `test -f 'runtime/go-cdiv.c' || echo '$(srcdir)/'`runtime/go-cdiv.c

79377

+

79378

go-cgo.lo: runtime/go-cgo.c

79379

@am__fastdepCC_TRUE@ $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT go-cgo.lo -MD -MP -MF $(DEPDIR)/go-cgo.Tpo -c -o go-cgo.lo `test -f 'runtime/go-cgo.c' || echo '$(srcdir)/'`runtime/go-cgo.c

79380

@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/go-cgo.Tpo $(DEPDIR)/go-cgo.Plo

79381

@@ -5062,15 +5071,6 @@

79382

@$(CHECK)

79383

.PHONY: go/build/check

79384

79385

-syslist.go: s-syslist; @true

79386

-s-syslist: Makefile

79387

- echo '// Generated automatically by make.' >syslist.go.tmp

79388

- echo 'package build' >>syslist.go.tmp

79389

- echo 'const goosList = "$(GOOS)"' >>syslist.go.tmp

79390

- echo 'const goarchList = "$(GOARCH)"' >>syslist.go.tmp

79391

- $(SHELL) $(srcdir)/../move-if-change syslist.go.tmp syslist.go

79392

- $(STAMP) $@

79393

-

79394

@go_include@ go/doc.lo.dep

79395

go/doc.lo.dep: $(go_go_doc_files)

79396

$(BUILDDEPS)

79397

Index: libgo/runtime/go-defer.c

79398

===================================================================

79399

--- a/src/libgo/runtime/go-defer.c (.../tags/gcc_4_8_2_release)

79400

+++ b/src/libgo/runtime/go-defer.c (.../branches/gcc-4_8-branch)

79401

@@ -27,6 +27,7 @@

79402

n->__pfn = pfn;

79403

n->__arg = arg;

79404

n->__retaddr = NULL;

79405

+ n->__makefunc_can_recover = 0;

79406

g->defer = n;

79407

}

79408

79409

Index: libgo/runtime/go-defer.h

79410

===================================================================

79411

--- a/src/libgo/runtime/go-defer.h (.../tags/gcc_4_8_2_release)

79412

+++ b/src/libgo/runtime/go-defer.h (.../branches/gcc-4_8-branch)

79413

@@ -34,4 +34,10 @@

79414

set by __go_set_defer_retaddr which is called by the thunks

79415

created by defer statements. */

79416

const void *__retaddr;

79417

+

79418

+ /* Set to true if a function created by reflect.MakeFunc is

79419

+ permitted to recover. The return address of such a function

79420

+ function will be somewhere in libffi, so __retaddr is not

79421

+ useful. */

79422

+ _Bool __makefunc_can_recover;

79423

};

79424

Index: libgo/runtime/go-int-array-to-string.c

79425

===================================================================

79426

--- a/src/libgo/runtime/go-int-array-to-string.c (.../tags/gcc_4_8_2_release)

79427

+++ b/src/libgo/runtime/go-int-array-to-string.c (.../branches/gcc-4_8-branch)

79428

@@ -30,6 +30,8 @@

79429

79430

if (v < 0 || v > 0x10ffff)

79431

v = 0xfffd;

79432

+ else if (0xd800 <= v && v <= 0xdfff)

79433

+ v = 0xfffd;

79434

79435

if (v <= 0x7f)

79436

slen += 1;

79437

@@ -56,6 +58,8 @@

79438

character. */

79439

if (v < 0 || v > 0x10ffff)

79440

v = 0xfffd;

79441

+ else if (0xd800 <= v && v <= 0xdfff)

79442

+ v = 0xfffd;

79443

79444

if (v <= 0x7f)

79445

*s++ = v;

79446

Index: libgo/runtime/go-nosys.c

79447

===================================================================

79448

--- a/src/libgo/runtime/go-nosys.c (.../tags/gcc_4_8_2_release)

79449

+++ b/src/libgo/runtime/go-nosys.c (.../branches/gcc-4_8-branch)

79450

@@ -43,6 +43,17 @@

79451

}

79452

#endif

79453

79454

+#ifndef HAVE_DUP3

79455

+int

79456

+dup3 (int oldfd __attribute__ ((unused)),

79457

+ int newfd __attribute__ ((unused)),

79458

+ int flags __attribute__ ((unused)))

79459

+{

79460

+ errno = ENOSYS;

79461

+ return -1;

79462

+}

79463

+#endif

79464

+

79465

#ifndef HAVE_EPOLL_CREATE1

79466

int

79467

epoll_create1 (int flags __attribute__ ((unused)))

79468

@@ -112,6 +123,18 @@

79469

}

79470

#endif

79471

79472

+#ifndef HAVE_GETXATTR

79473

+ssize_t

79474

+getxattr (const char *path __attribute__ ((unused)),

79475

+ const char *name __attribute__ ((unused)),

79476

+ void *value __attribute__ ((unused)),

79477

+ size_t size __attribute__ ((unused)))

79478

+{

79479

+ errno = ENOSYS;

79480

+ return -1;

79481

+}

79482

+#endif

79483

+

79484

#ifndef HAVE_INOTIFY_ADD_WATCH

79485

int

79486

inotify_add_watch (int fd __attribute__ ((unused)),

79487

@@ -151,6 +174,17 @@

79488

}

79489

#endif

79490

79491

+#ifndef HAVE_LISTXATTR

79492

+ssize_t

79493

+listxattr (const char *path __attribute__ ((unused)),

79494

+ char *list __attribute__ ((unused)),

79495

+ size_t size __attribute__ ((unused)))

79496

+{

79497

+ errno = ENOSYS;

79498

+ return -1;

79499

+}

79500

+#endif

79501

+

79502

#ifndef HAVE_MKDIRAT

79503

int

79504

mkdirat (int dirfd __attribute__ ((unused)),

79505

@@ -196,6 +230,16 @@

79506

}

79507

#endif

79508

79509

+#ifndef HAVE_REMOVEXATTR

79510

+int

79511

+removexattr (const char *path __attribute__ ((unused)),

79512

+ const char *name __attribute__ ((unused)))

79513

+{

79514

+ errno = ENOSYS;

79515

+ return -1;

79516

+}

79517

+#endif

79518

+

79519

#ifndef HAVE_RENAMEAT

79520

int

79521

renameat (int olddirfd __attribute__ ((unused)),

79522

@@ -208,6 +252,19 @@

79523

}

79524

#endif

79525

79526

+#ifndef HAVE_SETXATTR

79527

+int

79528

+setxattr (const char *path __attribute__ ((unused)),

79529

+ const char *name __attribute__ ((unused)),

79530

+ const void *value __attribute__ ((unused)),

79531

+ size_t size __attribute__ ((unused)),

79532

+ int flags __attribute__ ((unused)))

79533

+{

79534

+ errno = ENOSYS;

79535

+ return -1;

79536

+}

79537

+#endif

79538

+

79539

#ifndef HAVE_SPLICE

79540

int

79541

splice (int fd __attribute__ ((unused)),

79542

Index: libgo/runtime/runtime.h

79543

===================================================================

79544

--- a/src/libgo/runtime/runtime.h (.../tags/gcc_4_8_2_release)

79545

+++ b/src/libgo/runtime/runtime.h (.../branches/gcc-4_8-branch)

79546

@@ -440,7 +440,7 @@

79547

};

79548

void runtime_hashinit(void);

79549

79550

-void runtime_traceback();

79551

+void runtime_traceback(void);

79552

void runtime_tracebackothers(G*);

79553

79554

/*

79555

@@ -756,6 +756,7 @@

79556

extern _Bool __go_file_line(uintptr, String*, String*, intgo *);

79557

extern byte* runtime_progname();

79558

extern void runtime_main(void*);

79559

+extern uint32 runtime_in_callers;

79560

79561

int32 getproccount(void);

79562

79563

Index: libgo/runtime/proc.c

79564

===================================================================

79565

--- a/src/libgo/runtime/proc.c (.../tags/gcc_4_8_2_release)

79566

+++ b/src/libgo/runtime/proc.c (.../branches/gcc-4_8-branch)

79567

@@ -1716,10 +1716,30 @@

79568

// entersyscall is going to return immediately after.

79569

79570

void runtime_entersyscall(void) __attribute__ ((no_split_stack));

79571

+static void doentersyscall(void) __attribute__ ((no_split_stack, noinline));

79572

79573

void

79574

runtime_entersyscall()

79575

{

79576

+ // Save the registers in the g structure so that any pointers

79577

+ // held in registers will be seen by the garbage collector.

79578

+ getcontext(&g->gcregs);

79579

+

79580

+ // Do the work in a separate function, so that this function

79581

+ // doesn't save any registers on its own stack. If this

79582

+ // function does save any registers, we might store the wrong

79583

+ // value in the call to getcontext.

79584

+ //

79585

+ // FIXME: This assumes that we do not need to save any

79586

+ // callee-saved registers to access the TLS variable g. We

79587

+ // don't want to put the ucontext_t on the stack because it is

79588

+ // large and we can not split the stack here.

79589

+ doentersyscall();

79590

+}

79591

+

79592

+static void

79593

+doentersyscall()

79594

+{

79595

if(m->profilehz > 0)

79596

runtime_setprof(false);

79597

79598

@@ -1736,10 +1756,6 @@

79599

}

79600

#endif

79601

79602

- // Save the registers in the g structure so that any pointers

79603

- // held in registers will be seen by the garbage collector.

79604

- getcontext(&g->gcregs);

79605

-

79606

g->status = Gsyscall;

79607

79608

if(runtime_atomicload(&runtime_sched.sysmonwait)) { // TODO: fast atomic

79609

@@ -2239,6 +2255,14 @@

79610

if(prof.fn == nil || prof.hz == 0)

79611

return;

79612

79613

+ if(runtime_atomicload(&runtime_in_callers) > 0) {

79614

+ // If SIGPROF arrived while already fetching runtime

79615

+ // callers we can have trouble on older systems

79616

+ // because the unwind library calls dl_iterate_phdr

79617

+ // which was not recursive in the past.

79618

+ return;

79619

+ }

79620

+

79621

runtime_lock(&prof);

79622

if(prof.fn == nil) {

79623

runtime_unlock(&prof);

79624

Index: libgo/runtime/mgc0.c

79625

===================================================================

79626

--- a/src/libgo/runtime/mgc0.c (.../tags/gcc_4_8_2_release)

79627

+++ b/src/libgo/runtime/mgc0.c (.../branches/gcc-4_8-branch)

79628

@@ -174,7 +174,7 @@

79629

Obj *roots;

79630

uint32 nroot;

79631

uint32 rootcap;

79632

-} work;

79633

+} work __attribute__((aligned(8)));

79634

79635

enum {

79636

GC_DEFAULT_PTR = GC_NUM_INSTR,

79637

@@ -239,8 +239,7 @@

79638

// (Manually inlined copy of MHeap_LookupMaybe.)

79639

k = (uintptr)obj>>PageShift;

79640

x = k;

79641

- if(sizeof(void*) == 8)

79642

- x -= (uintptr)runtime_mheap->arena_start>>PageShift;

79643

+ x -= (uintptr)runtime_mheap->arena_start>>PageShift;

79644

s = runtime_mheap->map[x];

79645

if(s == nil || k < s->start || k - s->start >= s->npages || s->state != MSpanInUse)

79646

return false;

79647

@@ -418,8 +417,7 @@

79648

// (Manually inlined copy of MHeap_LookupMaybe.)

79649

k = (uintptr)obj>>PageShift;

79650

x = k;

79651

- if(sizeof(void*) == 8)

79652

- x -= (uintptr)arena_start>>PageShift;

79653

+ x -= (uintptr)arena_start>>PageShift;

79654

s = runtime_mheap->map[x];

79655

if(s == nil || k < s->start || k - s->start >= s->npages || s->state != MSpanInUse)

79656

continue;

79657

@@ -466,8 +464,7 @@

79658

// Ask span about size class.

79659

// (Manually inlined copy of MHeap_Lookup.)

79660

x = (uintptr)obj >> PageShift;

79661

- if(sizeof(void*) == 8)

79662

- x -= (uintptr)arena_start>>PageShift;

79663

+ x -= (uintptr)arena_start>>PageShift;

79664

s = runtime_mheap->map[x];

79665

79666

PREFETCH(obj);

79667

@@ -585,8 +582,7 @@

79668

if(t == nil)

79669

return;

79670

x = (uintptr)obj >> PageShift;

79671

- if(sizeof(void*) == 8)

79672

- x -= (uintptr)(runtime_mheap->arena_start)>>PageShift;

79673

+ x -= (uintptr)(runtime_mheap->arena_start)>>PageShift;

79674

s = runtime_mheap->map[x];

79675

objstart = (byte*)((uintptr)s->start<<PageShift);

79676

if(s->sizeclass != 0) {

79677

Index: libgo/runtime/go-signal.c

79678

===================================================================

79679

--- a/src/libgo/runtime/go-signal.c (.../tags/gcc_4_8_2_release)

79680

+++ b/src/libgo/runtime/go-signal.c (.../branches/gcc-4_8-branch)

79681

@@ -234,7 +234,7 @@

79682

G *g;

79683

79684

g = runtime_g ();

79685

- runtime_traceback (g);

79686

+ runtime_traceback ();

79687

runtime_tracebackothers (g);

79688

79689

/* The gc library calls runtime_dumpregs here, and provides

79690

@@ -399,6 +399,9 @@

79691

{

79692

G *gp;

79693

M *mp;

79694

+#ifdef USING_SPLIT_STACK

79695

+ void *stack_context[10];

79696

+#endif

79697

79698

/* We are now running on the stack registered via sigaltstack.

79699

(Actually there is a small span of time between runtime_siginit

79700

@@ -409,7 +412,7 @@

79701

if (gp != NULL)

79702

{

79703

#ifdef USING_SPLIT_STACK

79704

- __splitstack_getcontext (&gp->stack_context[0]);

79705

+ __splitstack_getcontext (&stack_context[0]);

79706

#endif

79707

}

79708

79709

@@ -432,7 +435,7 @@

79710

if (gp != NULL)

79711

{

79712

#ifdef USING_SPLIT_STACK

79713

- __splitstack_setcontext (&gp->stack_context[0]);

79714

+ __splitstack_setcontext (&stack_context[0]);

79715

#endif

79716

}

79717

}

79718

Index: libgo/runtime/go-callers.c

79719

===================================================================

79720

--- a/src/libgo/runtime/go-callers.c (.../tags/gcc_4_8_2_release)

79721

+++ b/src/libgo/runtime/go-callers.c (.../branches/gcc-4_8-branch)

79722

@@ -11,6 +11,13 @@

79723

#include "runtime.h"

79724

#include "array.h"

79725

79726

+/* This is set to non-zero when calling backtrace_full. This is used

79727

+ to avoid getting hanging on a recursive lock in dl_iterate_phdr on

79728

+ older versions of glibc when a SIGPROF signal arrives while

79729

+ collecting a backtrace. */

79730

+

79731

+uint32 runtime_in_callers;

79732

+

79733

/* Argument passed to callback function. */

79734

79735

struct callers_data

79736

@@ -111,8 +118,10 @@

79737

data.skip = skip + 1;

79738

data.index = 0;

79739

data.max = m;

79740

+ runtime_xadd (&runtime_in_callers, 1);

79741

backtrace_full (__go_get_backtrace_state (), 0, callback, error_callback,

79742

&data);

79743

+ runtime_xadd (&runtime_in_callers, -1);

79744

return data.index;

79745

}

79746

79747

Index: libgo/runtime/go-cdiv.c

79748

===================================================================

79749

--- a/src/libgo/runtime/go-cdiv.c (.../tags/gcc_4_8_2_release)

79750

+++ b/src/libgo/runtime/go-cdiv.c (.../branches/gcc-4_8-branch)

79751

@@ -0,0 +1,46 @@

79752

+/* go-cdiv.c -- complex division routines

79753

+

79754

79755

+ Use of this source code is governed by a BSD-style

79756

+ license that can be found in the LICENSE file. */

79757

+

79758

+/* Calls to these functions are generated by the Go frontend for

79759

+ division of complex64 or complex128. We use these because Go's

79760

+ complex division expects slightly different results from the GCC

79761

+ default. When dividing NaN+1.0i / 0+0i, Go expects NaN+NaNi but

79762

+ GCC generates NaN+Infi. NaN+Infi seems wrong seems the rules of

79763

+ C99 Annex G specify that if either side of a complex number is Inf,

79764

+ the the whole number is Inf, but an operation involving NaN ought

79765

+ to result in NaN, not Inf. */

79766

+

79767

+__complex float

79768

+__go_complex64_div (__complex float a, __complex float b)

79769

+{

79770

+ if (__builtin_expect (b == 0+0i, 0))

79771

+ {

79772

+ if (!__builtin_isinff (__real__ a)

79773

+ && !__builtin_isinff (__imag__ a)

79774

+ && (__builtin_isnanf (__real__ a) || __builtin_isnanf (__imag__ a)))

79775

+ {

79776

+ /* Pass "1" to nanf to match math/bits.go. */

79777

+ return __builtin_nanf("1") + __builtin_nanf("1")*1i;

79778

+ }

79779

+ }

79780

+ return a / b;

79781

+}

79782

+

79783

+__complex double

79784

+__go_complex128_div (__complex double a, __complex double b)

79785

+{

79786

+ if (__builtin_expect (b == 0+0i, 0))

79787

+ {

79788

+ if (!__builtin_isinf (__real__ a)

79789

+ && !__builtin_isinf (__imag__ a)

79790

+ && (__builtin_isnan (__real__ a) || __builtin_isnan (__imag__ a)))

79791

+ {

79792

+ /* Pass "1" to nan to match math/bits.go. */

79793

+ return __builtin_nan("1") + __builtin_nan("1")*1i;

79794

+ }

79795

+ }

79796

+ return a / b;

79797

+}

79798

Index: libgo/runtime/go-reflect-call.c

79799

===================================================================

79800

--- a/src/libgo/runtime/go-reflect-call.c (.../tags/gcc_4_8_2_release)

79801

+++ b/src/libgo/runtime/go-reflect-call.c (.../branches/gcc-4_8-branch)

79802

@@ -98,9 +98,12 @@

79803

const struct __go_struct_field *fields;

79804

int i;

79805

79806

+ field_count = descriptor->__fields.__count;

79807

+ if (field_count == 0) {

79808

+ return &ffi_type_void;

79809

+ }

79810

ret = (ffi_type *) __go_alloc (sizeof (ffi_type));

79811

ret->type = FFI_TYPE_STRUCT;

79812

- field_count = descriptor->__fields.__count;

79813

fields = (const struct __go_struct_field *) descriptor->__fields.__values;

79814

ret->elements = (ffi_type **) __go_alloc ((field_count + 1)

79815

* sizeof (ffi_type *));

79816

Index: libgo/runtime/go-recover.c

79817

===================================================================

79818

--- a/src/libgo/runtime/go-recover.c (.../tags/gcc_4_8_2_release)

79819

+++ b/src/libgo/runtime/go-recover.c (.../branches/gcc-4_8-branch)

79820

@@ -16,12 +16,14 @@

79821

__go_can_recover--this is, the thunk. */

79822

79823

_Bool

79824

-__go_can_recover (const void* retaddr)

79825

+__go_can_recover (const void *retaddr)

79826

{

79827

G *g;

79828

struct __go_defer_stack *d;

79829

const char* ret;

79830

const char* dret;

79831

+ Location loc;

79832

+ const byte *name;

79833

79834

g = runtime_g ();

79835

79836

@@ -52,9 +54,80 @@

79837

#endif

79838

79839

dret = (const char *) d->__retaddr;

79840

- return ret <= dret && ret + 16 >= dret;

79841

+ if (ret <= dret && ret + 16 >= dret)

79842

+ return 1;

79843

+

79844

+ /* If the function calling recover was created by reflect.MakeFunc,

79845

+ then RETADDR will be somewhere in libffi. Our caller is

79846

+ permitted to recover if it was called from libffi. */

79847

+ if (!d->__makefunc_can_recover)

79848

+ return 0;

79849

+

79850

+ if (runtime_callers (2, &loc, 1) < 1)

79851

+ return 0;

79852

+

79853

+ /* If we have no function name, then we weren't called by Go code.

79854

+ Guess that we were called by libffi. */

79855

+ if (loc.function.len == 0)

79856

+ return 1;

79857

+

79858

+ if (loc.function.len < 4)

79859

+ return 0;

79860

+ name = loc.function.str;

79861

+ if (*name == '_')

79862

+ {

79863

+ if (loc.function.len < 5)

79864

+ return 0;

79865

+ ++name;

79866

+ }

79867

+

79868

+ if (name[0] == 'f' && name[1] == 'f' && name[2] == 'i' && name[3] == '_')

79869

+ return 1;

79870

+

79871

+ /* We may also be called by reflect.makeFuncImpl.call, for a

79872

+ function created by reflect.MakeFunc. */

79873

+ if (__builtin_strstr ((const char *) name, "makeFuncImpl") != NULL)

79874

+ return 1;

79875

+

79876

+ return 0;

79877

}

79878

79879

+/* This function is called when code is about to enter a function

79880

+ created by reflect.MakeFunc. It is called by the function stub

79881

+ used by MakeFunc. If the stub is permitted to call recover, then a

79882

+ real MakeFunc function is permitted to call recover. */

79883

+

79884

+void

79885

+__go_makefunc_can_recover (const void *retaddr)

79886

+{

79887

+ struct __go_defer_stack *d;

79888

+

79889

+ d = runtime_g ()->defer;

79890

+ if (d != NULL

79891

+ && !d->__makefunc_can_recover

79892

+ && __go_can_recover (retaddr))

79893

+ d->__makefunc_can_recover = 1;

79894

+}

79895

+

79896

+/* This function is called when code is about to exit a function

79897

+ created by reflect.MakeFunc. It is called by the function stub

79898

+ used by MakeFunc. It clears the __makefunc_can_recover field.

79899

+ It's OK to always clear this field, because __go_can_recover will

79900

+ only be called by a stub created for a function that calls recover.

79901

+ That stub will not call a function created by reflect.MakeFunc, so

79902

+ by the time we get here any caller higher up on the call stack no

79903

+ longer needs the information. */

79904

+

79905

+void

79906

+__go_makefunc_returning (void)

79907

+{

79908

+ struct __go_defer_stack *d;

79909

+

79910

+ d = runtime_g ()->defer;

79911

+ if (d != NULL)

79912

+ d->__makefunc_can_recover = 0;

79913

+}

79914

+

79915

/* This is only called when it is valid for the caller to recover the

79916

value on top of the panic stack, if there is one. */

79917

79918

Index: libgo/runtime/malloc.goc

79919

===================================================================

79920

--- a/src/libgo/runtime/malloc.goc (.../tags/gcc_4_8_2_release)

79921

+++ b/src/libgo/runtime/malloc.goc (.../branches/gcc-4_8-branch)

79922

@@ -541,8 +541,7 @@

79923

79924

// (Manually inlined copy of runtime_MHeap_Lookup)

79925

p = (uintptr)v>>PageShift;

79926

- if(sizeof(void*) == 8)

79927

- p -= (uintptr)runtime_mheap->arena_start >> PageShift;

79928

+ p -= (uintptr)runtime_mheap->arena_start >> PageShift;

79929

s = runtime_mheap->map[p];

79930

79931

if(s->sizeclass == 0) {

79932

Index: libgo/runtime/go-make-slice.c

79933

===================================================================

79934

--- a/src/libgo/runtime/go-make-slice.c (.../tags/gcc_4_8_2_release)

79935

+++ b/src/libgo/runtime/go-make-slice.c (.../branches/gcc-4_8-branch)

79936

@@ -34,7 +34,10 @@

79937

std = (const struct __go_slice_type *) td;

79938

79939

ilen = (intgo) len;

79940

- if (ilen < 0 || (uintptr_t) ilen != len)

79941

+ if (ilen < 0

79942

+ || (uintptr_t) ilen != len

79943

+ || (std->__element_type->__size > 0

79944

+ && len > MaxMem / std->__element_type->__size))

79945

runtime_panicstring ("makeslice: len out of range");

79946

79947

icap = (intgo) cap;

79948

Index: libgo/runtime/mheap.c

79949

===================================================================

79950

--- a/src/libgo/runtime/mheap.c (.../tags/gcc_4_8_2_release)

79951

+++ b/src/libgo/runtime/mheap.c (.../branches/gcc-4_8-branch)

79952

@@ -150,8 +150,7 @@

79953

runtime_MSpan_Init(t, s->start + npage, s->npages - npage);

79954

s->npages = npage;

79955

p = t->start;

79956

- if(sizeof(void*) == 8)

79957

- p -= ((uintptr)h->arena_start>>PageShift);

79958

+ p -= ((uintptr)h->arena_start>>PageShift);

79959

if(p > 0)

79960

h->map[p-1] = s;

79961

h->map[p] = t;

79962

@@ -169,8 +168,7 @@

79963

s->elemsize = (sizeclass==0 ? s->npages<<PageShift : (uintptr)runtime_class_to_size[sizeclass]);

79964

s->types.compression = MTypes_Empty;

79965

p = s->start;

79966

- if(sizeof(void*) == 8)

79967

- p -= ((uintptr)h->arena_start>>PageShift);

79968

+ p -= ((uintptr)h->arena_start>>PageShift);

79969

for(n=0; n<npage; n++)

79970

h->map[p+n] = s;

79971

return s;

79972

@@ -241,8 +239,7 @@

79973

mstats.mspan_sys = h->spanalloc.sys;

79974

runtime_MSpan_Init(s, (uintptr)v>>PageShift, ask>>PageShift);

79975

p = s->start;

79976

- if(sizeof(void*) == 8)

79977

- p -= ((uintptr)h->arena_start>>PageShift);

79978

+ p -= ((uintptr)h->arena_start>>PageShift);

79979

h->map[p] = s;

79980

h->map[p + s->npages - 1] = s;

79981

s->state = MSpanInUse;

79982

@@ -259,8 +256,7 @@

79983

uintptr p;

79984

79985

p = (uintptr)v;

79986

- if(sizeof(void*) == 8)

79987

- p -= (uintptr)h->arena_start;

79988

+ p -= (uintptr)h->arena_start;

79989

return h->map[p >> PageShift];

79990

}

79991

79992

@@ -281,8 +277,7 @@

79993

return nil;

79994

p = (uintptr)v>>PageShift;

79995

q = p;

79996

- if(sizeof(void*) == 8)

79997

- q -= (uintptr)h->arena_start >> PageShift;

79998

+ q -= (uintptr)h->arena_start >> PageShift;

79999

s = h->map[q];

80000

if(s == nil || p < s->start || p - s->start >= s->npages)

80001

return nil;

80002

@@ -332,8 +327,7 @@

80003

80004

// Coalesce with earlier, later spans.

80005

p = s->start;

80006

- if(sizeof(void*) == 8)

80007

- p -= (uintptr)h->arena_start >> PageShift;

80008

+ p -= (uintptr)h->arena_start >> PageShift;

80009

if(p > 0 && (t = h->map[p-1]) != nil && t->state != MSpanInUse) {

80010

tp = (uintptr*)(t->start<<PageShift);

80011

*tp |= *sp; // propagate "needs zeroing" mark

80012

Index: libgo/testsuite/gotest

80013

===================================================================

80014

--- a/src/libgo/testsuite/gotest (.../tags/gcc_4_8_2_release)

80015

+++ b/src/libgo/testsuite/gotest (.../branches/gcc-4_8-branch)

80016

@@ -369,7 +369,7 @@

80017

{

80018

text="T"

80019

case "$GOARCH" in

80020

- ppc64) text="D" ;;

80021

+ ppc64) text="[TD]" ;;

80022

esac

80023

80024

symtogo='sed -e s/_test/XXXtest/ -e s/.*_$[^_]*\.$/\1/ -e s/XXXtest/_test/'

80025

Index: libgo/mksysinfo.sh

80026

===================================================================

80027

--- a/src/libgo/mksysinfo.sh (.../tags/gcc_4_8_2_release)

80028

+++ b/src/libgo/mksysinfo.sh (.../branches/gcc-4_8-branch)

80029

@@ -1035,6 +1035,10 @@

80030

grep '^const _LOCK_' gen-sysinfo.go |

80031

sed -e 's/^$const $_$LOCK_[^= ]*$$.*$$/\1\2 = _\2/' >> ${OUT}

80032

80033

+# The PRIO constants.

80034

+grep '^const _PRIO_' gen-sysinfo.go | \

80035

+ sed -e 's/^$const $_$PRIO_[^= ]*$$.*$$/\1\2 = _\2/' >> ${OUT}

80036

+

80037

# The GNU/Linux LINUX_REBOOT flags.

80038

grep '^const _LINUX_REBOOT_' gen-sysinfo.go |

80039

sed -e 's/^$const $_$LINUX_REBOOT_[^= ]*$$.*$$/\1\2 = _\2/' >> ${OUT}

80040

Index: libgo/config.h.in

80041

===================================================================

80042

--- a/src/libgo/config.h.in (.../tags/gcc_4_8_2_release)

80043

+++ b/src/libgo/config.h.in (.../branches/gcc-4_8-branch)

80044

@@ -39,6 +39,9 @@

80045

/* Define to 1 if you have the `dl_iterate_phdr' function. */

80046

#undef HAVE_DL_ITERATE_PHDR

80047

80048

+/* Define to 1 if you have the `dup3' function. */

80049

+#undef HAVE_DUP3

80050

+

80051

/* Define to 1 if you have the `epoll_create1' function. */

80052

#undef HAVE_EPOLL_CREATE1

80053

80054

@@ -66,6 +69,9 @@

80055

/* Define if _Unwind_GetIPInfo is available. */

80056

#undef HAVE_GETIPINFO

80057

80058

+/* Define to 1 if you have the `getxattr' function. */

80059

+#undef HAVE_GETXATTR

80060

+

80061

/* Define to 1 if you have the `inotify_add_watch' function. */

80062

#undef HAVE_INOTIFY_ADD_WATCH

80063

80064

@@ -111,6 +117,9 @@

80065

/* Define to 1 if you have the <linux/rtnetlink.h> header file. */

80066

#undef HAVE_LINUX_RTNETLINK_H

80067

80068

+/* Define to 1 if you have the `listxattr' function. */

80069

+#undef HAVE_LISTXATTR

80070

+

80071

/* Define to 1 if the system has the type `loff_t'. */

80072

#undef HAVE_LOFF_T

80073

80074

@@ -171,6 +180,9 @@

80075

/* Define to 1 if you have the `pipe2' function. */

80076

#undef HAVE_PIPE2

80077

80078

+/* Define to 1 if you have the `removexattr' function. */

80079

+#undef HAVE_REMOVEXATTR

80080

+

80081

/* Define to 1 if you have the `renameat' function. */

80082

#undef HAVE_RENAMEAT

80083

80084

@@ -180,6 +192,9 @@

80085

/* Define to 1 if you have the `setenv' function. */

80086

#undef HAVE_SETENV

80087

80088

+/* Define to 1 if you have the `setxattr' function. */

80089

+#undef HAVE_SETXATTR

80090

+

80091

/* Define to 1 if you have the `sinl' function. */

80092

#undef HAVE_SINL

80093

80094

Index: libgo/configure.ac

80095

===================================================================

80096

--- a/src/libgo/configure.ac (.../tags/gcc_4_8_2_release)

80097

+++ b/src/libgo/configure.ac (.../branches/gcc-4_8-branch)

80098

@@ -503,7 +503,7 @@

80099

AM_CONDITIONAL(HAVE_STRERROR_R, test "$ac_cv_func_strerror_r" = yes)

80100

AM_CONDITIONAL(HAVE_WAIT4, test "$ac_cv_func_wait4" = yes)

80101

80102

-AC_CHECK_FUNCS(accept4 epoll_create1 faccessat fallocate fchmodat fchownat futimesat inotify_add_watch inotify_init inotify_init1 inotify_rm_watch mkdirat mknodat openat pipe2 renameat sync_file_range splice tee unlinkat unshare utimensat)

80103

+AC_CHECK_FUNCS(accept4 dup3 epoll_create1 faccessat fallocate fchmodat fchownat futimesat getxattr inotify_add_watch inotify_init inotify_init1 inotify_rm_watch listxattr mkdirat mknodat openat pipe2 removexattr renameat setxattr sync_file_range splice tee unlinkat unshare utimensat)

80104

AC_TYPE_OFF_T

80105

AC_CHECK_TYPES([loff_t])

80106

80107

Index: libgo/config/libtool.m4

80108

===================================================================

80109

--- a/src/libgo/config/libtool.m4 (.../tags/gcc_4_8_2_release)

80110

+++ b/src/libgo/config/libtool.m4 (.../branches/gcc-4_8-branch)

80111

@@ -1225,7 +1225,7 @@

80112

rm -rf conftest*

80113

;;

80114

80115

-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \

80116

+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \

80117

s390*-*linux*|s390*-*tpf*|sparc*-*linux*)

80118

# Find out which ABI we are using.

80119

echo 'int i;' > conftest.$ac_ext

80120

@@ -1239,7 +1239,10 @@

80121

x86_64-*linux*)

80122

LD="${LD-ld} -m elf_i386"

80123

;;

80124

- ppc64-*linux*|powerpc64-*linux*)

80125

+ powerpc64le-*linux*)

80126

+ LD="${LD-ld} -m elf32lppclinux"

80127

+ ;;

80128

+ powerpc64-*linux*)

80129

LD="${LD-ld} -m elf32ppclinux"

80130

;;

80131

s390x-*linux*)

80132

@@ -1258,7 +1261,10 @@

80133

x86_64-*linux*)

80134

LD="${LD-ld} -m elf_x86_64"

80135

;;

80136

- ppc*-*linux*|powerpc*-*linux*)

80137

+ powerpcle-*linux*)

80138

+ LD="${LD-ld} -m elf64lppc"

80139

+ ;;

80140

+ powerpc-*linux*)

80141

LD="${LD-ld} -m elf64ppc"

80142

;;

80143

s390*-*linux*|s390*-*tpf*)

80144

Index: libgo/go/reflect/value.go

80145

===================================================================

80146

--- a/src/libgo/go/reflect/value.go (.../tags/gcc_4_8_2_release)

80147

+++ b/src/libgo/go/reflect/value.go (.../branches/gcc-4_8-branch)

80148

@@ -98,6 +98,7 @@

80149

flagIndir

80150

flagAddr

80151

flagMethod

80152

+ flagMethodFn // gccgo: first fn parameter is always pointer

80153

flagKindShift = iota

80154

flagKindWidth = 5 // there are 27 kinds

80155

flagKindMask flag = 1<<flagKindWidth - 1

80156

@@ -433,7 +434,7 @@

80157

if v.flag&flagMethod != 0 {

80158

nin++

80159

}

80160

- firstPointer := len(in) > 0 && t.In(0).Kind() != Ptr && v.flag&flagMethod == 0 && isMethod(v.typ)

80161

+ firstPointer := len(in) > 0 && t.In(0).Kind() != Ptr && v.flag&flagMethodFn != 0

80162

params := make([]unsafe.Pointer, nin)

80163

off := 0

80164

if v.flag&flagMethod != 0 {

80165

@@ -484,33 +485,6 @@

80166

return ret

80167

}

80168

80169

-// gccgo specific test to see if typ is a method. We can tell by

80170

-// looking at the string to see if there is a receiver. We need this

80171

-// because for gccgo all methods take pointer receivers.

80172

-func isMethod(t *rtype) bool {

80173

- if Kind(t.kind) != Func {

80174

- return false

80175

- }

80176

- s := *t.string

80177

- parens := 0

80178

- params := 0

80179

- sawRet := false

80180

- for i, c := range s {

80181

- if c == '(' {

80182

- if parens == 0 {

80183

- params++

80184

- }

80185

- parens++

80186

- } else if c == ')' {

80187

- parens--

80188

- } else if parens == 0 && c == ' ' && s[i+1] != '(' && !sawRet {

80189

- params++

80190

- sawRet = true

80191

- }

80192

- }

80193

- return params > 2

80194

-}

80195

-

80196

// methodReceiver returns information about the receiver

80197

// described by v. The Value v may or may not have the

80198

// flagMethod bit set, so the kind cached in v.flag should

80199

@@ -917,6 +891,16 @@

80200

v = makeMethodValue("Interface", v)

80201

}

80202

80203

+ if v.flag&flagMethodFn != 0 {

80204

+ if v.typ.Kind() != Func {

80205

+ panic("reflect: MethodFn of non-Func")

80206

+ }

80207

+ ft := (*funcType)(unsafe.Pointer(v.typ))

80208

+ if ft.in[0].Kind() != Ptr {

80209

+ v = makeValueMethod(v)

80210

+ }

80211

+ }

80212

+

80213

k := v.kind()

80214

if k == Interface {

80215

// Special case: return the element inside the interface.

80216

@@ -1230,8 +1214,7 @@

80217

// created via reflect have the same underlying code pointer,

80218

// so their Pointers are equal. The function used here must

80219

// match the one used in makeMethodValue.

80220

- // This is not properly implemented for gccgo.

80221

- f := Zero

80222

+ f := makeFuncStub

80223

return **(**uintptr)(unsafe.Pointer(&f))

80224

}

80225

p := v.val

80226

Index: libgo/go/reflect/makefuncgo_386.go

80227

===================================================================

80228

--- a/src/libgo/go/reflect/makefuncgo_386.go (.../tags/gcc_4_8_2_release)

80229

+++ b/src/libgo/go/reflect/makefuncgo_386.go (.../branches/gcc-4_8-branch)

80230

@@ -14,8 +14,10 @@

80231

// registers that might hold result values.

80232

type i386Regs struct {

80233

esp uint32

80234

- eax uint32 // Value to return in %eax.

80235

- st0 uint64 // Value to return in %st(0).

80236

+ eax uint32 // Value to return in %eax.

80237

+ st0 float64 // Value to return in %st(0).

80238

+ sr bool // Set to true if hidden struct pointer.

80239

+ sf bool // Set to true if returning float

80240

}

80241

80242

// MakeFuncStubGo implements the 386 calling convention for MakeFunc.

80243

@@ -56,10 +58,13 @@

80244

in := make([]Value, 0, len(ftyp.in))

80245

ap := uintptr(regs.esp)

80246

80247

+ regs.sr = false

80248

+ regs.sf = false

80249

var retPtr unsafe.Pointer

80250

if retStruct {

80251

retPtr = *(*unsafe.Pointer)(unsafe.Pointer(ap))

80252

ap += ptrSize

80253

+ regs.sr = true

80254

}

80255

80256

for _, rt := range ftyp.in {

80257

@@ -77,7 +82,7 @@

80258

80259

// Call the real function.

80260

80261

- out := c.fn(in)

80262

+ out := c.call(in)

80263

80264

if len(out) != len(ftyp.out) {

80265

panic("reflect: wrong return count from function created by MakeFunc")

80266

@@ -123,13 +128,16 @@

80267

80268

v := out[0]

80269

w := v.iword()

80270

- if v.Kind() != Ptr && v.Kind() != UnsafePointer {

80271

- w = loadIword(unsafe.Pointer(w), v.typ.size)

80272

- }

80273

switch v.Kind() {

80274

- case Float32, Float64:

80275

- regs.st0 = uint64(uintptr(w))

80276

+ case Ptr, UnsafePointer:

80277

+ regs.eax = uint32(uintptr(w))

80278

+ case Float32:

80279

+ regs.st0 = float64(*(*float32)(unsafe.Pointer(w)))

80280

+ regs.sf = true

80281

+ case Float64:

80282

+ regs.st0 = *(*float64)(unsafe.Pointer(w))

80283

+ regs.sf = true

80284

default:

80285

- regs.eax = uint32(uintptr(w))

80286

+ regs.eax = uint32(uintptr(loadIword(unsafe.Pointer(w), v.typ.size)))

80287

}

80288

}

80289

Index: libgo/go/reflect/makefunc_amd64.S

80290

===================================================================

80291

--- a/src/libgo/go/reflect/makefunc_amd64.S (.../tags/gcc_4_8_2_release)

80292

+++ b/src/libgo/go/reflect/makefunc_amd64.S (.../branches/gcc-4_8-branch)

80293

@@ -61,6 +61,14 @@

80294

movdqa %xmm6, 0xa0(%rsp)

80295

movdqa %xmm7, 0xb0(%rsp)

80296

80297

+ /* For MakeFunc functions that call recover. */

80298

+ movq 8(%rbp), %rdi

80299

+#ifdef __PIC__

80300

+ call __go_makefunc_can_recover@PLT

80301

+#else

80302

+ call __go_makefunc_can_recover

80303

+#endif

80304

+

80305

# Get function type.

80306

#ifdef __PIC__

80307

call __go_get_closure@PLT

80308

@@ -77,6 +85,13 @@

80309

call reflect.MakeFuncStubGo

80310

#endif

80311

80312

+ /* MakeFunc functions can no longer call recover. */

80313

+#ifdef __PIC__

80314

+ call __go_makefunc_returning@PLT

80315

+#else

80316

+ call __go_makefunc_returning

80317

+#endif

80318

+

80319

# The structure will be updated with any return values. Load

80320

# all possible return registers before returning to the caller.

80321

80322

Index: libgo/go/reflect/type.go

80323

===================================================================

80324

--- a/src/libgo/go/reflect/type.go (.../tags/gcc_4_8_2_release)

80325

+++ b/src/libgo/go/reflect/type.go (.../branches/gcc-4_8-branch)

80326

@@ -508,7 +508,7 @@

80327

m.Type = toType(mt)

80328

x := new(unsafe.Pointer)

80329

*x = unsafe.Pointer(&p.tfn)

80330

- m.Func = Value{mt, unsafe.Pointer(x), fl | flagIndir}

80331

+ m.Func = Value{mt, unsafe.Pointer(x), fl | flagIndir | flagMethodFn}

80332

m.Index = i

80333

return

80334

}

80335

Index: libgo/go/reflect/makefunc_386.S

80336

===================================================================

80337

--- a/src/libgo/go/reflect/makefunc_386.S (.../tags/gcc_4_8_2_release)

80338

+++ b/src/libgo/go/reflect/makefunc_386.S (.../branches/gcc-4_8-branch)

80339

@@ -25,9 +25,13 @@

80340

struct {

80341

esp uint32 // 0x0

80342

eax uint32 // 0x4

80343

- st0 uint64 // 0x8

80344

+ st0 float64 // 0x8

80345

+ sr bool // 0x10

80346

+ sf bool // 0x11

80347

}

80348

- */

80349

+ The sr field is set by the function to a non-zero value if

80350

+ the function takes a struct hidden pointer that must be

80351

+ popped off the stack. */

80352

80353

pushl %ebp

80354

.LCFI0:

80355

@@ -45,7 +49,16 @@

80356

leal 8(%ebp), %eax /* Set esp field in struct. */

80357

movl %eax, -24(%ebp)

80358

80359

+ /* For MakeFunc functions that call recover. */

80360

+ movl 4(%ebp), %eax

80361

+ movl %eax, (%esp)

80362

#ifdef __PIC__

80363

+ call __go_makefunc_can_recover@PLT

80364

+#else

80365

+ call __go_makefunc_can_recover

80366

+#endif

80367

+

80368

+#ifdef __PIC__

80369

call __go_get_closure@PLT

80370

#else

80371

call __go_get_closure

80372

@@ -62,9 +75,20 @@

80373

call reflect.MakeFuncStubGo

80374

#endif

80375

80376

+ /* MakeFunc functions can no longer call recover. */

80377

+#ifdef __PIC__

80378

+ call __go_makefunc_returning@PLT

80379

+#else

80380

+ call __go_makefunc_returning

80381

+#endif

80382

+

80383

/* Set return registers. */

80384

80385

movl -20(%ebp), %eax

80386

+

80387

+ cmpb $0, -7(%ebp)

80388

+ je 2f

80389

+

80390

fldl -16(%ebp)

80391

80392

#ifdef __SSE2__

80393

@@ -73,12 +97,20 @@

80394

movsd -16(%ebp), %xmm0

80395

#endif

80396

80397

+2:

80398

+ movb -8(%ebp), %dl

80399

+

80400

addl $36, %esp

80401

popl %ebx

80402

.LCFI3:

80403

popl %ebp

80404

.LCFI4:

80405

+

80406

+ testb %dl,%dl

80407

+ jne 1f

80408

ret

80409

+1:

80410

+ ret $4

80411

.LFE1:

80412

#ifdef __ELF__

80413

.size reflect.makeFuncStub, . - reflect.makeFuncStub

80414

Index: libgo/go/reflect/all_test.go

80415

===================================================================

80416

--- a/src/libgo/go/reflect/all_test.go (.../tags/gcc_4_8_2_release)

80417

+++ b/src/libgo/go/reflect/all_test.go (.../branches/gcc-4_8-branch)

80418

@@ -1430,6 +1430,46 @@

80419

}

80420

}

80421

80422

+type emptyStruct struct{}

80423

+

80424

+type nonEmptyStruct struct {

80425

+ member int

80426

+}

80427

+

80428

+func returnEmpty() emptyStruct {

80429

+ return emptyStruct{}

80430

+}

80431

+

80432

+func takesEmpty(e emptyStruct) {

80433

+}

80434

+

80435

+func returnNonEmpty(i int) nonEmptyStruct {

80436

+ return nonEmptyStruct{member: i}

80437

+}

80438

+

80439

+func takesNonEmpty(n nonEmptyStruct) int {

80440

+ return n.member

80441

+}

80442

+

80443

+func TestCallWithStruct(t *testing.T) {

80444

+ r := ValueOf(returnEmpty).Call([]Value{})

80445

+ if len(r) != 1 || r[0].Type() != TypeOf(emptyStruct{}) {

80446

+ t.Errorf("returning empty struct returned %s instead", r)

80447

+ }

80448

+ r = ValueOf(takesEmpty).Call([]Value{ValueOf(emptyStruct{})})

80449

+ if len(r) != 0 {

80450

+ t.Errorf("takesEmpty returned values: %s", r)

80451

+ }

80452

+ r = ValueOf(returnNonEmpty).Call([]Value{ValueOf(42)})

80453

+ if len(r) != 1 || r[0].Type() != TypeOf(nonEmptyStruct{}) || r[0].Field(0).Int() != 42 {

80454

+ t.Errorf("returnNonEmpty returned %s", r)

80455

+ }

80456

+ r = ValueOf(takesNonEmpty).Call([]Value{ValueOf(nonEmptyStruct{member: 42})})

80457

+ if len(r) != 1 || r[0].Type() != TypeOf(1) || r[0].Int() != 42 {

80458

+ t.Errorf("takesNonEmpty returned %s", r)

80459

+ }

80460

+}

80461

+

80462

func TestMakeFunc(t *testing.T) {

80463

switch runtime.GOARCH {

80464

case "amd64", "386":

80465

@@ -1587,9 +1627,13 @@

80466

}

80467

}

80468

80469

-/* Not yet implemented for gccgo

80470

+func TestMethodValue(t *testing.T) {

80471

+ switch runtime.GOARCH {

80472

+ case "amd64", "386":

80473

+ default:

80474

+ t.Skip("reflect method values not implemented for " + runtime.GOARCH)

80475

+ }

80476

80477

-func TestMethodValue(t *testing.T) {

80478

p := Point{3, 4}

80479

var i int64

80480

80481

@@ -1658,8 +1702,6 @@

80482

}

80483

}

80484

80485

-*/

80486

-

80487

// Reflect version of $GOROOT/test/method5.go

80488

80489

// Concrete types implementing M method.

80490

@@ -1744,7 +1786,12 @@

80491

func (t4 Tm4) M(x int, b byte) (byte, int) { return b, x + 40 }

80492

80493

func TestMethod5(t *testing.T) {

80494

- /* Not yet used for gccgo

80495

+ switch runtime.GOARCH {

80496

+ case "amd64", "386":

80497

+ default:

80498

+ t.Skip("reflect method values not implemented for " + runtime.GOARCH)

80499

+ }

80500

+

80501

CheckF := func(name string, f func(int, byte) (byte, int), inc int) {

80502

b, x := f(1000, 99)

80503

if b != 99 || x != 1000+inc {

80504

@@ -1751,7 +1798,6 @@

80505

t.Errorf("%s(1000, 99) = %v, %v, want 99, %v", name, b, x, 1000+inc)

80506

}

80507

}

80508

- */

80509

80510

CheckV := func(name string, i Value, inc int) {

80511

bx := i.Method(0).Call([]Value{ValueOf(1000), ValueOf(byte(99))})

80512

@@ -1761,9 +1807,7 @@

80513

t.Errorf("direct %s.M(1000, 99) = %v, %v, want 99, %v", name, b, x, 1000+inc)

80514

}

80515

80516

- /* Not yet implemented for gccgo

80517

CheckF(name+".M", i.Method(0).Interface().(func(int, byte) (byte, int)), inc)

80518

- */

80519

}

80520

80521

var TinterType = TypeOf(new(Tinter)).Elem()

80522

Index: libgo/go/reflect/makefunc.go

80523

===================================================================

80524

--- a/src/libgo/go/reflect/makefunc.go (.../tags/gcc_4_8_2_release)

80525

+++ b/src/libgo/go/reflect/makefunc.go (.../branches/gcc-4_8-branch)

80526

@@ -17,6 +17,11 @@

80527

code uintptr

80528

typ *funcType

80529

fn func([]Value) []Value

80530

+

80531

+ // For gccgo we use the same entry point for functions and for

80532

+ // method values.

80533

+ method int

80534

+ rcvr Value

80535

}

80536

80537

// MakeFunc returns a new function of the given Type

80538

@@ -61,7 +66,7 @@

80539

dummy := makeFuncStub

80540

code := **(**uintptr)(unsafe.Pointer(&dummy))

80541

80542

- impl := &makeFuncImpl{code: code, typ: ftyp, fn: fn}

80543

+ impl := &makeFuncImpl{code: code, typ: ftyp, fn: fn, method: -1}

80544

80545

return Value{t, unsafe.Pointer(&impl), flag(Func<<flagKindShift) | flagIndir}

80546

}

80547

@@ -85,15 +90,94 @@

80548

panic("reflect: internal error: invalid use of makePartialFunc")

80549

}

80550

80551

+ switch runtime.GOARCH {

80552

+ case "amd64", "386":

80553

+ default:

80554

+ panic("reflect.makeMethodValue not implemented for " + runtime.GOARCH)

80555

+ }

80556

+

80557

// Ignoring the flagMethod bit, v describes the receiver, not the method type.

80558

fl := v.flag & (flagRO | flagAddr | flagIndir)

80559

fl |= flag(v.typ.Kind()) << flagKindShift

80560

rcvr := Value{v.typ, v.val, fl}

80561

80562

+ // v.Type returns the actual type of the method value.

80563

+ ft := v.Type().(*rtype)

80564

+

80565

+ // Indirect Go func value (dummy) to obtain

80566

+ // actual code address. (A Go func value is a pointer

80567

+ // to a C function pointer. http://golang.org/s/go11func.)

80568

+ dummy := makeFuncStub

80569

+ code := **(**uintptr)(unsafe.Pointer(&dummy))

80570

+

80571

// Cause panic if method is not appropriate.

80572

// The panic would still happen during the call if we omit this,

80573

// but we want Interface() and other operations to fail early.

80574

- methodReceiver(op, rcvr, int(v.flag)>>flagMethodShift)

80575

+ t, _, _ := methodReceiver(op, rcvr, int(v.flag)>>flagMethodShift)

80576

80577

- panic("reflect makeMethodValue not implemented")

80578

+ fv := &makeFuncImpl{

80579

+ code: code,

80580

+ typ: (*funcType)(unsafe.Pointer(t)),

80581

+ method: int(v.flag) >> flagMethodShift,

80582

+ rcvr: rcvr,

80583

+ }

80584

+

80585

+ return Value{ft, unsafe.Pointer(&fv), v.flag&flagRO | flag(Func)<<flagKindShift | flagIndir}

80586

}

80587

+

80588

+// makeValueMethod takes a method function and returns a function that

80589

+// takes a value receiver and calls the real method with a pointer to

80590

+// it.

80591

+func makeValueMethod(v Value) Value {

80592

+ typ := v.typ

80593

+ if typ.Kind() != Func {

80594

+ panic("reflect: call of makeValueMethod with non-Func type")

80595

+ }

80596

+ if v.flag&flagMethodFn == 0 {

80597

+ panic("reflect: call of makeValueMethod with non-MethodFn")

80598

+ }

80599

+

80600

+ switch runtime.GOARCH {

80601

+ case "amd64", "386":

80602

+ default:

80603

+ panic("reflect.makeValueMethod not implemented for " + runtime.GOARCH)

80604

+ }

80605

+

80606

+ t := typ.common()

80607

+ ftyp := (*funcType)(unsafe.Pointer(t))

80608

+

80609

+ // Indirect Go func value (dummy) to obtain

80610

+ // actual code address. (A Go func value is a pointer

80611

+ // to a C function pointer. http://golang.org/s/go11func.)

80612

+ dummy := makeFuncStub

80613

+ code := **(**uintptr)(unsafe.Pointer(&dummy))

80614

+

80615

+ impl := &makeFuncImpl{

80616

+ code: code,

80617

+ typ: ftyp,

80618

+ method: -2,

80619

+ rcvr: v,

80620

+ }

80621

+

80622

+ return Value{t, unsafe.Pointer(&impl), flag(Func<<flagKindShift) | flagIndir}

80623

+}

80624

+

80625

+// Call the function represented by a makeFuncImpl.

80626

+func (c *makeFuncImpl) call(in []Value) []Value {

80627

+ if c.method == -1 {

80628

+ return c.fn(in)

80629

+ } else if c.method == -2 {

80630

+ if c.typ.IsVariadic() {

80631

+ return c.rcvr.CallSlice(in)

80632

+ } else {

80633

+ return c.rcvr.Call(in)

80634

+ }

80635

+ } else {

80636

+ m := c.rcvr.Method(c.method)

80637

+ if c.typ.IsVariadic() {

80638

+ return m.CallSlice(in)

80639

+ } else {

80640

+ return m.Call(in)

80641

+ }

80642

+ }

80643

+}

80644

Index: libgo/go/reflect/makefuncgo_amd64.go

80645

===================================================================

80646

--- a/src/libgo/go/reflect/makefuncgo_amd64.go (.../tags/gcc_4_8_2_release)

80647

+++ b/src/libgo/go/reflect/makefuncgo_amd64.go (.../branches/gcc-4_8-branch)

80648

@@ -319,7 +319,7 @@

80649

// All the real arguments have been found and turned into

80650

// Value's. Call the real function.

80651

80652

- out := c.fn(in)

80653

+ out := c.call(in)

80654

80655

if len(out) != len(ftyp.out) {

80656

panic("reflect: wrong return count from function created by MakeFunc")

80657

Index: libgo/go/net/fd_unix.go

80658

===================================================================

80659

--- a/src/libgo/go/net/fd_unix.go (.../tags/gcc_4_8_2_release)

80660

+++ b/src/libgo/go/net/fd_unix.go (.../branches/gcc-4_8-branch)

80661

@@ -9,6 +9,7 @@

80662

import (

80663

"io"

80664

"os"

80665

+ "runtime"

80666

"sync"

80667

"syscall"

80668

"time"

80669

@@ -90,6 +91,16 @@

80670

if err == nil || err == syscall.EISCONN {

80671

break

80672

}

80673

+

80674

+ // On Solaris we can see EINVAL if the socket has

80675

+ // already been accepted and closed by the server.

80676

+ // Treat this as a successful connection--writes to

80677

+ // the socket will see EOF. For details and a test

80678

+ // case in C see http://golang.org/issue/6828.

80679

+ if runtime.GOOS == "solaris" && err == syscall.EINVAL {

80680

+ break

80681

+ }

80682

+

80683

if err != syscall.EINPROGRESS && err != syscall.EALREADY && err != syscall.EINTR {

80684

return err

80685

}

80686

Index: libgo/go/go/build/build.go

80687

===================================================================

80688

--- a/src/libgo/go/go/build/build.go (.../tags/gcc_4_8_2_release)

80689

+++ b/src/libgo/go/go/build/build.go (.../branches/gcc-4_8-branch)

80690

@@ -429,7 +429,7 @@

80691

switch ctxt.Compiler {

80692

case "gccgo":

80693

dir, elem := pathpkg.Split(p.ImportPath)

80694

- pkga = "pkg/gccgo/" + dir + "lib" + elem + ".a"

80695

+ pkga = "pkg/gccgo_" + ctxt.GOOS + "_" + ctxt.GOARCH + "/" + dir + "lib" + elem + ".a"

80696

case "gc":

80697

suffix := ""

80698

if ctxt.InstallSuffix != "" {

80699

Index: libgo/go/go/build/syslist.go

80700

===================================================================

80701

--- a/src/libgo/go/go/build/syslist.go (.../tags/gcc_4_8_2_release)

80702

+++ b/src/libgo/go/go/build/syslist.go (.../branches/gcc-4_8-branch)

80703

@@ -0,0 +1,8 @@

80704

80705

+// Use of this source code is governed by a BSD-style

80706

+// license that can be found in the LICENSE file.

80707

+

80708

+package build

80709

+

80710

+const goosList = "darwin dragonfly freebsd linux netbsd openbsd plan9 windows solaris "

80711

+const goarchList = "386 amd64 arm alpha m68k mipso32 mipsn32 mipsn64 mipso64 ppc ppc64 sparc sparc64 "

80712

Index: libgo/go/syscall/libcall_linux.go

80713

===================================================================

80714

--- a/src/libgo/go/syscall/libcall_linux.go (.../tags/gcc_4_8_2_release)

80715

+++ b/src/libgo/go/syscall/libcall_linux.go (.../branches/gcc-4_8-branch)

80716

@@ -190,6 +190,9 @@

80717

//sys Adjtimex(buf *Timex) (state int, err error)

80718

//adjtimex(buf *Timex) _C_int

80719

80720

+//sysnb Dup3(oldfd int, newfd int, flags int) (err error)

80721

+//dup3(oldfd _C_int, newfd _C_int, flags _C_int) _C_int

80722

+

80723

//sys Faccessat(dirfd int, path string, mode uint32, flags int) (err error)

80724

//faccessat(dirfd _C_int, pathname *byte, mode _C_int, flags _C_int) _C_int

80725

80726

@@ -268,6 +271,9 @@

80727

return origlen - len(buf), count, names

80728

}

80729

80730

+//sys Getxattr(path string, attr string, dest []byte) (sz int, err error)

80731

+//getxattr(path *byte, attr *byte, buf *byte, count Size_t) Ssize_t

80732

+

80733

//sys InotifyAddWatch(fd int, pathname string, mask uint32) (watchdesc int, err error)

80734

//inotify_add_watch(fd _C_int, pathname *byte, mask uint32) _C_int

80735

80736

@@ -283,6 +289,9 @@

80737

//sys Klogctl(typ int, buf []byte) (n int, err error)

80738

//klogctl(typ _C_int, bufp *byte, len _C_int) _C_int

80739

80740

+//sys Listxattr(path string, dest []byte) (sz int, err error)

80741

+//listxattr(path *byte, list *byte, size Size_t) Ssize_t

80742

+

80743

//sys Mkdirat(dirfd int, path string, mode uint32) (err error)

80744

//mkdirat(dirfd _C_int, path *byte, mode Mode_t) _C_int

80745

80746

@@ -305,6 +314,9 @@

80747

//sys PivotRoot(newroot string, putold string) (err error)

80748

//pivot_root(newroot *byte, putold *byte) _C_int

80749

80750

+//sys Removexattr(path string, attr string) (err error)

80751

+//removexattr(path *byte, name *byte) _C_int

80752

+

80753

//sys Renameat(olddirfd int, oldpath string, newdirfd int, newpath string) (err error)

80754

//renameat(olddirfd _C_int, oldpath *byte, newdirfd _C_int, newpath *byte) _C_int

80755

80756

@@ -338,6 +350,9 @@

80757

//sysnb Setresuid(ruid int, eguid int, suid int) (err error)

80758

//setresuid(ruid Uid_t, euid Uid_t, suid Uid_t) _C_int

80759

80760

+//sys Setxattr(path string, attr string, data []byte, flags int) (err error)

80761

+//setxattr(path *byte, name *byte, value *byte, size Size_t, flags _C_int) _C_int

80762

+

80763

//sys splice(rfd int, roff *_loff_t, wfd int, woff *_loff_t, len int, flags int) (n int64, err error)

80764

//splice(rfd _C_int, roff *_loff_t, wfd _C_int, woff *_loff_t, len Size_t, flags _C_uint) Ssize_t

80765

func Splice(rfd int, roff *int64, wfd int, woff *int64, len int, flags int) (n int64, err error) {

80766

Index: libgo/go/syscall/socket.go

80767

===================================================================

80768

--- a/src/libgo/go/syscall/socket.go (.../tags/gcc_4_8_2_release)

80769

+++ b/src/libgo/go/syscall/socket.go (.../branches/gcc-4_8-branch)

80770

@@ -25,7 +25,7 @@

80771

Pad [96]int8

80772

}

80773

80774

-const SizeofSockaddrAny = 0x1c

80775

+const SizeofSockaddrAny = 0x6c

80776

80777

type SockaddrInet4 struct {

80778

Port int

80779

Index: libgo/go/syscall/libcall_posix.go

80780

===================================================================

80781

--- a/src/libgo/go/syscall/libcall_posix.go (.../tags/gcc_4_8_2_release)

80782

+++ b/src/libgo/go/syscall/libcall_posix.go (.../branches/gcc-4_8-branch)

80783

@@ -238,6 +238,9 @@

80784

//sysnb Getppid() (ppid int)

80785

//getppid() Pid_t

80786

80787

+//sys Getpriority(which int, who int) (prio int, err error)

80788

+//getpriority(which _C_int, who _C_int) _C_int

80789

+

80790

//sysnb Getrlimit(resource int, rlim *Rlimit) (err error)

80791

//getrlimit(resource _C_int, rlim *Rlimit) _C_int

80792

80793

@@ -307,6 +310,9 @@

80794

//sysnb Setpgid(pid int, pgid int) (err error)

80795

//setpgid(pid Pid_t, pgid Pid_t) _C_int

80796

80797

+//sys Setpriority(which int, who int, prio int) (err error)

80798

+//setpriority(which _C_int, who _C_int, prio _C_int) _C_int

80799

+

80800

//sysnb Setreuid(ruid int, euid int) (err error)

80801

//setreuid(ruid Uid_t, euid Uid_t) _C_int

80802

80803

Index: libgo/Makefile.am

80804

===================================================================

80805

--- a/src/libgo/Makefile.am (.../tags/gcc_4_8_2_release)

80806

+++ b/src/libgo/Makefile.am (.../branches/gcc-4_8-branch)

80807

@@ -424,6 +424,7 @@

80808

runtime/go-caller.c \

80809

runtime/go-callers.c \

80810

runtime/go-can-convert-interface.c \

80811

+ runtime/go-cdiv.c \

80812

runtime/go-cgo.c \

80813

runtime/go-check-interface.c \

80814

runtime/go-construct-map.c \

80815

@@ -1254,7 +1255,7 @@

80816

go/go/build/build.go \

80817

go/go/build/doc.go \

80818

go/go/build/read.go \

80819

- syslist.go

80820

+ go/go/build/syslist.go

80821

go_go_doc_files = \

80822

go/go/doc/comment.go \

80823

go/go/doc/doc.go \

80824

@@ -2712,15 +2713,6 @@

80825

@$(CHECK)

80826

.PHONY: go/build/check

80827

80828

-syslist.go: s-syslist; @true

80829

-s-syslist: Makefile

80830

- echo '// Generated automatically by make.' >syslist.go.tmp

80831

- echo 'package build' >>syslist.go.tmp

80832

- echo 'const goosList = "$(GOOS)"' >>syslist.go.tmp

80833

- echo 'const goarchList = "$(GOARCH)"' >>syslist.go.tmp

80834

- $(SHELL) $(srcdir)/../move-if-change syslist.go.tmp syslist.go

80835

- $(STAMP) $@

80836

-

80837

@go_include@ go/doc.lo.dep

80838

go/doc.lo.dep: $(go_go_doc_files)

80839

$(BUILDDEPS)

80840

Index: config.sub

80841

===================================================================

80842

--- a/src/config.sub (.../tags/gcc_4_8_2_release)

80843

+++ b/src/config.sub (.../branches/gcc-4_8-branch)

80844

@@ -1,10 +1,8 @@

80845

#! /bin/sh

80846

# Configuration validation subroutine script.

80847

80848

-# 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,

80849

-# 2011, 2012, 2013 Free Software Foundation, Inc.

80850

80851

80852

-timestamp='2013-01-11'

80853

+timestamp='2013-10-01'

80854

80855

# This file is free software; you can redistribute it and/or modify it

80856

# under the terms of the GNU General Public License as published by

80857

@@ -70,9 +68,7 @@

80858

version="\

80859

GNU config.sub ($timestamp)

80860

80861

80862

-2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011,

80863

-2012, 2013 Free Software Foundation, Inc.

80864

80865

80866

This is free software; see the source for copying conditions. There is NO

80867

warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE."

80868

@@ -256,12 +252,12 @@

80869

80870

80871

| am33_2.0 \

80872

- | arc \

80873

+ | arc | arceb \

80874

80875

| avr | avr32 \

80876

| be32 | be64 \

80877

| bfin \

80878

- | c4x | clipper \

80879

+ | c4x | c8051 | clipper \

80880

| d10v | d30v | dlx | dsp16xx \

80881

| epiphany \

80882

| fido | fr30 | frv \

80883

@@ -269,6 +265,7 @@

80884

| hexagon \

80885

| i370 | i860 | i960 | ia64 \

80886

| ip2k | iq2000 \

80887

+ | k1om \

80888

| le32 | le64 \

80889

| lm32 \

80890

| m32c | m32r | m32rle | m68000 | m68k | m88k \

80891

@@ -297,10 +294,10 @@

80892

| mt \

80893

| msp430 \

80894

| nds32 | nds32le | nds32be \

80895

- | nios | nios2 \

80896

+ | nios | nios2 | nios2eb | nios2el \

80897

| ns16k | ns32k \

80898

| open8 \

80899

- | or32 \

80900

+ | or1k | or32 \

80901

| pdp10 | pdp11 | pj | pjl \

80902

| powerpc | powerpc64 | powerpc64le | powerpcle \

80903

| pyramid \

80904

@@ -328,7 +325,7 @@

80905

c6x)

80906

basic_machine=tic6x-unknown

80907

;;

80908

- m6811 | m68hc11 | m6812 | m68hc12 | m68hcs12x | picochip)

80909

+ m6811 | m68hc11 | m6812 | m68hc12 | m68hcs12x | nvptx | picochip)

80910

basic_machine=$basic_machine-unknown

80911

os=-none

80912

;;

80913

@@ -370,13 +367,13 @@

80914

| aarch64-* | aarch64_be-* \

80915

| alpha-* | alphaev[4-8]-* | alphaev56-* | alphaev6[78]-* \

80916

| alpha64-* | alpha64ev[4-8]-* | alpha64ev56-* | alpha64ev6[78]-* \

80917

- | alphapca5[67]-* | alpha64pca5[67]-* | arc-* \

80918

+ | alphapca5[67]-* | alpha64pca5[67]-* | arc-* | arceb-* \

80919

80920

| avr-* | avr32-* \

80921

| be32-* | be64-* \

80922

| bfin-* | bs2000-* \

80923

| c[123]* | c30-* | [cjt]90-* | c4x-* \

80924

- | clipper-* | craynv-* | cydra-* \

80925

+ | c8051-* | clipper-* | craynv-* | cydra-* \

80926

| d10v-* | d30v-* | dlx-* \

80927

| elxsi-* \

80928

| f30[01]-* | f700-* | fido-* | fr30-* | frv-* | fx80-* \

80929

@@ -385,6 +382,7 @@

80930

| hexagon-* \

80931

| i*86-* | i860-* | i960-* | ia64-* \

80932

| ip2k-* | iq2000-* \

80933

+ | k1om-* \

80934

| le32-* | le64-* \

80935

| lm32-* \

80936

| m32c-* | m32r-* | m32rle-* \

80937

@@ -414,7 +412,7 @@

80938

| mt-* \

80939

| msp430-* \

80940

| nds32-* | nds32le-* | nds32be-* \

80941

- | nios-* | nios2-* \

80942

+ | nios-* | nios2-* | nios2eb-* | nios2el-* \

80943

| none-* | np1-* | ns16k-* | ns32k-* \

80944

| open8-* \

80945

| orion-* \

80946

@@ -798,7 +796,7 @@

80947

os=-mingw64

80948

;;

80949

mingw32)

80950

- basic_machine=i386-pc

80951

+ basic_machine=i686-pc

80952

os=-mingw32

80953

;;

80954

mingw32ce)

80955

@@ -834,7 +832,7 @@

80956

basic_machine=`echo $basic_machine | sed -e 's/ms1-/mt-/'`

80957

;;

80958

msys)

80959

- basic_machine=i386-pc

80960

+ basic_machine=i686-pc

80961

os=-msys

80962

;;

80963

mvs)

80964

@@ -1550,6 +1548,9 @@

80965

c4x-* | tic4x-*)

80966

os=-coff

80967

;;

80968

+ c8051-*)

80969

+ os=-elf

80970

+ ;;

80971

hexagon-*)

80972

os=-elf

80973

;;

80974

@@ -1593,6 +1594,9 @@

80975

mips*-*)

80976

os=-elf

80977

;;

80978

+ or1k-*)

80979

+ os=-elf

80980

+ ;;

80981

or32-*)

80982

os=-coff

80983

;;

80984

Index: libobjc/configure

80985

===================================================================

80986

--- a/src/libobjc/configure (.../tags/gcc_4_8_2_release)

80987

+++ b/src/libobjc/configure (.../branches/gcc-4_8-branch)

80988

@@ -6056,7 +6056,7 @@

80989

rm -rf conftest*

80990

;;

80991

80992

-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \

80993

+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \

80994

s390*-*linux*|s390*-*tpf*|sparc*-*linux*)

80995

# Find out which ABI we are using.

80996

echo 'int i;' > conftest.$ac_ext

80997

@@ -6081,7 +6081,10 @@

80998

;;

80999

esac

81000

;;

81001

- ppc64-*linux*|powerpc64-*linux*)

81002

+ powerpc64le-*linux*)

81003

+ LD="${LD-ld} -m elf32lppclinux"

81004

+ ;;

81005

+ powerpc64-*linux*)

81006

LD="${LD-ld} -m elf32ppclinux"

81007

;;

81008

s390x-*linux*)

81009

@@ -6100,7 +6103,10 @@

81010

x86_64-*linux*)

81011

LD="${LD-ld} -m elf_x86_64"

81012

;;

81013

- ppc*-*linux*|powerpc*-*linux*)

81014

+ powerpcle-*linux*)

81015

+ LD="${LD-ld} -m elf64lppc"

81016

+ ;;

81017

+ powerpc-*linux*)

81018

LD="${LD-ld} -m elf64ppc"

81019

;;

81020

s390*-*linux*|s390*-*tpf*)

81021

@@ -10595,7 +10601,7 @@

81022

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

81023

lt_status=$lt_dlunknown

81024

cat > conftest.$ac_ext <<_LT_EOF

81025

-#line 10598 "configure"

81026

+#line 10604 "configure"

81027

#include "confdefs.h"

81028

81029

#if HAVE_DLFCN_H

81030

@@ -10701,7 +10707,7 @@

81031

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

81032

lt_status=$lt_dlunknown

81033

cat > conftest.$ac_ext <<_LT_EOF

81034

-#line 10704 "configure"

81035

+#line 10710 "configure"

81036

#include "confdefs.h"

81037

81038

#if HAVE_DLFCN_H

81039

@@ -11472,7 +11478,7 @@

81040

enableval=$enable_sjlj_exceptions; :

81041

else

81042

cat > conftest.$ac_ext << EOF

81043

-#line 11475 "configure"

81044

+#line 11481 "configure"

81045

@interface Frob

81046

@end

81047

@implementation Frob

81048

Index: libobjc/ChangeLog

81049

===================================================================

81050

--- a/src/libobjc/ChangeLog (.../tags/gcc_4_8_2_release)

81051

+++ b/src/libobjc/ChangeLog (.../branches/gcc-4_8-branch)

81052

@@ -1,3 +1,10 @@

81053

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

81054

+

81055

+ Backport from mainline

81056

+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

81057

+

81058

+ * configure: Regenerate.

81059

+

81060

2013-10-16 Release Manager

81061

81062

* GCC 4.8.2 released.

81063

Index: libgfortran/configure

81064

===================================================================

81065

--- a/src/libgfortran/configure (.../tags/gcc_4_8_2_release)

81066

+++ b/src/libgfortran/configure (.../branches/gcc-4_8-branch)

81067

@@ -8062,7 +8062,7 @@

81068

rm -rf conftest*

81069

;;

81070

81071

-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \

81072

+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \

81073

s390*-*linux*|s390*-*tpf*|sparc*-*linux*)

81074

# Find out which ABI we are using.

81075

echo 'int i;' > conftest.$ac_ext

81076

@@ -8087,7 +8087,10 @@

81077

;;

81078

esac

81079

;;

81080

- ppc64-*linux*|powerpc64-*linux*)

81081

+ powerpc64le-*linux*)

81082

+ LD="${LD-ld} -m elf32lppclinux"

81083

+ ;;

81084

+ powerpc64-*linux*)

81085

LD="${LD-ld} -m elf32ppclinux"

81086

;;

81087

s390x-*linux*)

81088

@@ -8106,7 +8109,10 @@

81089

x86_64-*linux*)

81090

LD="${LD-ld} -m elf_x86_64"

81091

;;

81092

- ppc*-*linux*|powerpc*-*linux*)

81093

+ powerpcle-*linux*)

81094

+ LD="${LD-ld} -m elf64lppc"

81095

+ ;;

81096

+ powerpc-*linux*)

81097

LD="${LD-ld} -m elf64ppc"

81098

;;

81099

s390*-*linux*|s390*-*tpf*)

81100

@@ -12333,7 +12339,7 @@

81101

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

81102

lt_status=$lt_dlunknown

81103

cat > conftest.$ac_ext <<_LT_EOF

81104

-#line 12336 "configure"

81105

+#line 12342 "configure"

81106

#include "confdefs.h"

81107

81108

#if HAVE_DLFCN_H

81109

@@ -12439,7 +12445,7 @@

81110

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

81111

lt_status=$lt_dlunknown

81112

cat > conftest.$ac_ext <<_LT_EOF

81113

-#line 12442 "configure"

81114

+#line 12448 "configure"

81115

#include "confdefs.h"

81116

81117

#if HAVE_DLFCN_H

81118

Index: libgfortran/intrinsics/system_clock.c

81119

===================================================================

81120

--- a/src/libgfortran/intrinsics/system_clock.c (.../tags/gcc_4_8_2_release)

81121

+++ b/src/libgfortran/intrinsics/system_clock.c (.../branches/gcc-4_8-branch)

81122

@@ -32,7 +32,8 @@

81123

/* POSIX states that CLOCK_REALTIME must be present if clock_gettime

81124

is available, others are optional. */

81125

#if defined(HAVE_CLOCK_GETTIME) || defined(HAVE_CLOCK_GETTIME_LIBRT)

81126

-#ifdef CLOCK_MONOTONIC

81127

+#if defined(CLOCK_MONOTONIC) && defined(_POSIX_MONOTONIC_CLOCK) \

81128

+ && _POSIX_MONOTONIC_CLOCK >= 0

81129

#define GF_CLOCK_MONOTONIC CLOCK_MONOTONIC

81130

#else

81131

#define GF_CLOCK_MONOTONIC CLOCK_REALTIME

81132

Index: libgfortran/ChangeLog

81133

===================================================================

81134

--- a/src/libgfortran/ChangeLog (.../tags/gcc_4_8_2_release)

81135

+++ b/src/libgfortran/ChangeLog (.../branches/gcc-4_8-branch)

81136

@@ -1,3 +1,75 @@

81137

+2014-05-03 Janne Blomqvist <jb@gcc.gnu.org>

81138

+

81139

+ Backport from 4.9

81140

+ PR libfortran/56919

81141

+ * intrinsics/system_clock.c (GF_CLOCK_MONOTONIC): Check

81142

+ _POSIX_MONOTONIC_CLOCK as well.

81143

+

81144

+2014-04-12 Jerry DeLisle <jvdelisle@gcc.gnu>

81145

+

81146

+ Backport from mainline

81147

+ PR libfortran/60810

81148

+ * io/unit.c (is_trim_ok): If internal unit is array, do not trim.

81149

+

81150

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

81151

+

81152

+ Backport from mainline

81153

+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

81154

+ * configure: Regenerate.

81155

+

81156

+2014-03-15 Dominique d'Humieres <dominiq@lps.ens.fr>

81157

+

81158

+ Backport from mainline

81159

+ PR libgfortran/60128

81160

+ * io/write_float.def (output_float): Remove unused variable

81161

+ nzero_real. Replace a double space with a single one.

81162

+ (determine_en_precision): Fix wrong handling of the EN format.

81163

+

81164

+2014-03-15 Jerry DeLisle <jvdelisle@gcc.gnu>

81165

+

81166

+ Backport from mainline

81167

+ PR libfortran/58324

81168

+ PR libfortran/38199

81169

+ * io/list_read.c (finish_list_read): Read one character to check

81170

+ for the end of the file. If it is the end, then issue the file

81171

+ end error message. If not, use eat_line to reach the end

81172

+ without giving error. The next attempt to read will then

81173

+ issue the error as described above.

81174

+ * io/read.c (read_decimal): Quickly skip spaces to avoid calls

81175

+ to next_char.

81176

+ * io/unit.c (is_trim_ok): New helper function to check various

81177

+ conditions to see if its OK to trim the internal unit string.

81178

+ (get_internal_unit): Use LEN_TRIM to shorten selected internal

81179

+ unit strings for optimizing READ. Enable this optimization for

81180

+ formatted READ.

81181

+

81182

+2014-02-21 Jerry DeLisle <jvdelisle@gcc.gnu>

81183

+ Dominique d'Humieres <dominiq@lps.ens.fr>

81184

+ Steven G. Kargl <kargl@gcc.gnu.org>

81185

+

81186

+ Backport from mainline

81187

+ PR libfortran/59700

81188

+ PR libfortran/59764

81189

+ * io/io.h (struct st_parameter_dt): Assign expanded_read flag to

81190

+ unused bit. Define new variable line_buffer_pos.

81191

+ * io/list_read.c (free_saved, next_char, l_push_char,

81192

+ read_logical, read_real): Replace use of item_count with

81193

+ line_buffer_pos for line_buffer look ahead.

81194

+ (read_logical, read_integer, parse_real, read_real, check_type):

81195

+ Adjust location of free_line to after generating error messages

81196

+ to retain the correct item count for the message.

81197

+

81198

+2014-02-15 Jerry DeLisle <jvdelisle@gcc.gnu>

81199

+ Dominique d'Humieres <dominiq@lps.ens.fr>

81200

+

81201

+ Backport from mainline

81202

+ PR libfortran/59771

81203

+ PR libfortran/59774

81204

+ PR libfortran/59836

81205

+ * io/write_float.def (output_float): Fix wrong handling of the

81206

+ Fw.0 format.

81207

+ (output_float_FMT_G_): Fixes rounding issues with -m32.

81208

+

81209

2013-10-16 Release Manager

81210

81211

* GCC 4.8.2 released.

81212

Index: libgfortran/io/list_read.c

81213

===================================================================

81214

--- a/src/libgfortran/io/list_read.c (.../tags/gcc_4_8_2_release)

81215

+++ b/src/libgfortran/io/list_read.c (.../branches/gcc-4_8-branch)

81216

@@ -118,7 +118,7 @@

81217

static void

81218

free_line (st_parameter_dt *dtp)

81219

{

81220

- dtp->u.p.item_count = 0;

81221

+ dtp->u.p.line_buffer_pos = 0;

81222

dtp->u.p.line_buffer_enabled = 0;

81223

81224

if (dtp->u.p.line_buffer == NULL)

81225

@@ -150,15 +150,15 @@

81226

{

81227

dtp->u.p.at_eol = 0;

81228

81229

- c = dtp->u.p.line_buffer[dtp->u.p.item_count];

81230

- if (c != '\0' && dtp->u.p.item_count < 64)

81231

+ c = dtp->u.p.line_buffer[dtp->u.p.line_buffer_pos];

81232

+ if (c != '\0' && dtp->u.p.line_buffer_pos < 64)

81233

{

81234

- dtp->u.p.line_buffer[dtp->u.p.item_count] = '\0';

81235

- dtp->u.p.item_count++;

81236

+ dtp->u.p.line_buffer[dtp->u.p.line_buffer_pos] = '\0';

81237

+ dtp->u.p.line_buffer_pos++;

81238

goto done;

81239

}

81240

81241

- dtp->u.p.item_count = 0;

81242

+ dtp->u.p.line_buffer_pos = 0;

81243

dtp->u.p.line_buffer_enabled = 0;

81244

}

81245

81246

@@ -640,7 +640,7 @@

81247

if (dtp->u.p.line_buffer == NULL)

81248

dtp->u.p.line_buffer = xcalloc (SCRATCH_SIZE, 1);

81249

81250

- dtp->u.p.line_buffer[dtp->u.p.item_count++] = c;

81251

+ dtp->u.p.line_buffer[dtp->u.p.line_buffer_pos++] = c;

81252

}

81253

81254

81255

@@ -750,7 +750,7 @@

81256

{

81257

dtp->u.p.nml_read_error = 1;

81258

dtp->u.p.line_buffer_enabled = 1;

81259

- dtp->u.p.item_count = 0;

81260

+ dtp->u.p.line_buffer_pos = 0;

81261

return;

81262

}

81263

81264

@@ -758,14 +758,17 @@

81265

81266

bad_logical:

81267

81268

- free_line (dtp);

81269

-

81270

if (nml_bad_return (dtp, c))

81271

- return;

81272

+ {

81273

+ free_line (dtp);

81274

+ return;

81275

+ }

81276

81277

+

81278

free_saved (dtp);

81279

if (c == EOF)

81280

{

81281

+ free_line (dtp);

81282

hit_eof (dtp);

81283

return;

81284

}

81285

@@ -773,6 +776,7 @@

81286

eat_line (dtp);

81287

snprintf (message, MSGLEN, "Bad logical value while reading item %d",

81288

dtp->u.p.item_count);

81289

+ free_line (dtp);

81290

generate_error (&dtp->common, LIBERROR_READ_VALUE, message);

81291

return;

81292

81293

@@ -913,9 +917,9 @@

81294

else if (c != '\n')

81295

eat_line (dtp);

81296

81297

- free_line (dtp);

81298

snprintf (message, MSGLEN, "Bad integer for item %d in list input",

81299

dtp->u.p.item_count);

81300

+ free_line (dtp);

81301

generate_error (&dtp->common, LIBERROR_READ_VALUE, message);

81302

81303

return;

81304

@@ -1298,9 +1302,9 @@

81305

else if (c != '\n')

81306

eat_line (dtp);

81307

81308

- free_line (dtp);

81309

snprintf (message, MSGLEN, "Bad floating point number for item %d",

81310

dtp->u.p.item_count);

81311

+ free_line (dtp);

81312

generate_error (&dtp->common, LIBERROR_READ_VALUE, message);

81313

81314

return 1;

81315

@@ -1406,9 +1410,9 @@

81316

else if (c != '\n')

81317

eat_line (dtp);

81318

81319

- free_line (dtp);

81320

snprintf (message, MSGLEN, "Bad complex value in item %d of list input",

81321

dtp->u.p.item_count);

81322

+ free_line (dtp);

81323

generate_error (&dtp->common, LIBERROR_READ_VALUE, message);

81324

}

81325

81326

@@ -1770,7 +1774,7 @@

81327

{

81328

dtp->u.p.nml_read_error = 1;

81329

dtp->u.p.line_buffer_enabled = 1;

81330

- dtp->u.p.item_count = 0;

81331

+ dtp->u.p.line_buffer_pos = 0;

81332

return;

81333

}

81334

81335

@@ -1789,9 +1793,9 @@

81336

else if (c != '\n')

81337

eat_line (dtp);

81338

81339

- free_line (dtp);

81340

snprintf (message, MSGLEN, "Bad real number in item %d of list input",

81341

dtp->u.p.item_count);

81342

+ free_line (dtp);

81343

generate_error (&dtp->common, LIBERROR_READ_VALUE, message);

81344

}

81345

81346

@@ -1806,11 +1810,10 @@

81347

81348

if (dtp->u.p.saved_type != BT_UNKNOWN && dtp->u.p.saved_type != type)

81349

{

81350

- free_line (dtp);

81351

snprintf (message, MSGLEN, "Read type %s where %s was expected for item %d",

81352

type_name (dtp->u.p.saved_type), type_name (type),

81353

dtp->u.p.item_count);

81354

-

81355

+ free_line (dtp);

81356

generate_error (&dtp->common, LIBERROR_READ_VALUE, message);

81357

return 1;

81358

}

81359

@@ -1820,12 +1823,12 @@

81360

81361

if (dtp->u.p.saved_length != len)

81362

{

81363

- free_line (dtp);

81364

snprintf (message, MSGLEN,

81365

"Read kind %d %s where kind %d is required for item %d",

81366

dtp->u.p.saved_length, type_name (dtp->u.p.saved_type), len,

81367

dtp->u.p.item_count);

81368

generate_error (&dtp->common, LIBERROR_READ_VALUE, message);

81369

+ free_line (dtp);

81370

return 1;

81371

}

81372

81373

@@ -2031,8 +2034,6 @@

81374

void

81375

finish_list_read (st_parameter_dt *dtp)

81376

{

81377

- int err;

81378

-

81379

free_saved (dtp);

81380

81381

fbuf_flush (dtp->u.p.current_unit, dtp->u.p.mode);

81382

@@ -2043,12 +2044,22 @@

81383

return;

81384

}

81385

81386

- err = eat_line (dtp);

81387

- if (err == LIBERROR_END)

81388

+ if (!is_internal_unit (dtp))

81389

{

81390

- free_line (dtp);

81391

- hit_eof (dtp);

81392

+ int c;

81393

+ c = next_char (dtp);

81394

+ if (c == EOF)

81395

+ {

81396

+ free_line (dtp);

81397

+ hit_eof (dtp);

81398

+ return;

81399

+ }

81400

+ if (c != '\n')

81401

+ eat_line (dtp);

81402

}

81403

+

81404

+ free_line (dtp);

81405

+

81406

}

81407

81408

/* NAMELIST INPUT

81409

Index: libgfortran/io/read.c

81410

===================================================================

81411

--- a/src/libgfortran/io/read.c (.../tags/gcc_4_8_2_release)

81412

+++ b/src/libgfortran/io/read.c (.../branches/gcc-4_8-branch)

81413

@@ -655,7 +655,13 @@

81414

81415

if (c == ' ')

81416

{

81417

- if (dtp->u.p.blank_status == BLANK_NULL) continue;

81418

+ if (dtp->u.p.blank_status == BLANK_NULL)

81419

+ {

81420

+ /* Skip spaces. */

81421

+ for ( ; w > 0; p++, w--)

81422

+ if (*p != ' ') break;

81423

+ continue;

81424

+ }

81425

if (dtp->u.p.blank_status == BLANK_ZERO) c = '0';

81426

}

81427

81428

Index: libgfortran/io/io.h

81429

===================================================================

81430

--- a/src/libgfortran/io/io.h (.../tags/gcc_4_8_2_release)

81431

+++ b/src/libgfortran/io/io.h (.../branches/gcc-4_8-branch)

81432

@@ -424,7 +424,10 @@

81433

unsigned g0_no_blanks : 1;

81434

/* Used to signal use of free_format_data. */

81435

unsigned format_not_saved : 1;

81436

- /* 14 unused bits. */

81437

+ /* A flag used to identify when a non-standard expanded namelist read

81438

+ has occurred. */

81439

+ unsigned expanded_read : 1;

81440

+ /* 13 unused bits. */

81441

81442

/* Used for ungetc() style functionality. Possible values

81443

are an unsigned char, EOF, or EOF - 1 used to mark the

81444

@@ -441,9 +444,8 @@

81445

char *line_buffer;

81446

struct format_data *fmt;

81447

namelist_info *ionml;

81448

- /* A flag used to identify when a non-standard expanded namelist read

81449

- has occurred. */

81450

- int expanded_read;

81451

+ /* Current position within the look-ahead line buffer. */

81452

+ int line_buffer_pos;

81453

/* Storage area for values except for strings. Must be

81454

large enough to hold a complex value (two reals) of the

81455

largest kind. */

81456

Index: libgfortran/io/unit.c

81457

===================================================================

81458

--- a/src/libgfortran/io/unit.c (.../tags/gcc_4_8_2_release)

81459

+++ b/src/libgfortran/io/unit.c (.../branches/gcc-4_8-branch)

81460

@@ -29,6 +29,7 @@

81461

#include "unix.h"

81462

#include <stdlib.h>

81463

#include <string.h>

81464

+#include <stdbool.h>

81465

81466

81467

/* IO locking rules:

81468

@@ -375,6 +376,36 @@

81469

}

81470

81471

81472

+/* Helper function to check rank, stride, format string, and namelist.

81473

+ This is used for optimization. You can't trim out blanks or shorten

81474

+ the string if trailing spaces are significant. */

81475

+static bool

81476

+is_trim_ok (st_parameter_dt *dtp)

81477

+{

81478

+ /* Check rank and stride. */

81479

+ if (dtp->internal_unit_desc)

81480

+ return false;

81481

+ /* Format strings can not have 'BZ' or '/'. */

81482

+ if (dtp->common.flags & IOPARM_DT_HAS_FORMAT)

81483

+ {

81484

+ char *p = dtp->format;

81485

+ off_t i;

81486

+ if (dtp->common.flags & IOPARM_DT_HAS_BLANK)

81487

+ return false;

81488

+ for (i = 0; i < dtp->format_len; i++)

81489

+ {

81490

+ if (p[i] == '/') return false;

81491

+ if (p[i] == 'b' || p[i] == 'B')

81492

+ if (p[i+1] == 'z' || p[i+1] == 'Z')

81493

+ return false;

81494

+ }

81495

+ }

81496

+ if (dtp->u.p.ionml) /* A namelist. */

81497

+ return false;

81498

+ return true;

81499

+}

81500

+

81501

+

81502

gfc_unit *

81503

get_internal_unit (st_parameter_dt *dtp)

81504

{

81505

@@ -402,6 +433,22 @@

81506

some other file I/O unit. */

81507

iunit->unit_number = -1;

81508

81509

+ /* As an optimization, adjust the unit record length to not

81510

+ include trailing blanks. This will not work under certain conditions

81511

+ where trailing blanks have significance. */

81512

+ if (dtp->u.p.mode == READING && is_trim_ok (dtp))

81513

+ {

81514

+ int len;

81515

+ if (dtp->common.unit == 0)

81516

+ len = string_len_trim (dtp->internal_unit_len,

81517

+ dtp->internal_unit);

81518

+ else

81519

+ len = string_len_trim_char4 (dtp->internal_unit_len,

81520

+ (const gfc_char4_t*) dtp->internal_unit);

81521

+ dtp->internal_unit_len = len;

81522

+ iunit->recl = dtp->internal_unit_len;

81523

+ }

81524

+

81525

/* Set up the looping specification from the array descriptor, if any. */

81526

81527

if (is_array_io (dtp))

81528

@@ -414,27 +461,6 @@

81529

81530

start_record *= iunit->recl;

81531

}

81532

- else

81533

- {

81534

- /* If we are not processing an array, adjust the unit record length not

81535

- to include trailing blanks for list-formatted reads. */

81536

- if (dtp->u.p.mode == READING && !(dtp->common.flags & IOPARM_DT_HAS_FORMAT))

81537

- {

81538

- if (dtp->common.unit == 0)

81539

- {

81540

- dtp->internal_unit_len =

81541

- string_len_trim (dtp->internal_unit_len, dtp->internal_unit);

81542

- iunit->recl = dtp->internal_unit_len;

81543

- }

81544

- else

81545

- {

81546

- dtp->internal_unit_len =

81547

- string_len_trim_char4 (dtp->internal_unit_len,

81548

- (const gfc_char4_t*) dtp->internal_unit);

81549

- iunit->recl = dtp->internal_unit_len;

81550

- }

81551

- }

81552

- }

81553

81554

/* Set initial values for unit parameters. */

81555

if (dtp->common.unit)

81556

Index: libgfortran/io/write_float.def

81557

===================================================================

81558

--- a/src/libgfortran/io/write_float.def (.../tags/gcc_4_8_2_release)

81559

+++ b/src/libgfortran/io/write_float.def (.../branches/gcc-4_8-branch)

81560

@@ -125,8 +125,6 @@

81561

int nzero;

81562

/* Number of digits after the decimal point. */

81563

int nafter;

81564

- /* Number of zeros after the decimal point, whatever the precision. */

81565

- int nzero_real;

81566

int leadzero;

81567

int nblanks;

81568

int ndigits, edigits;

81569

@@ -138,7 +136,6 @@

81570

p = dtp->u.p.scale_factor;

81571

81572

rchar = '5';

81573

- nzero_real = -1;

81574

81575

/* We should always know the field width and precision. */

81576

if (d < 0)

81577

@@ -191,7 +188,7 @@

81578

if (nafter < 0)

81579

nafter = 0;

81580

nafter = d;

81581

- nzero = nzero_real = 0;

81582

+ nzero = 0;

81583

}

81584

else /* p < 0 */

81585

{

81586

@@ -211,7 +208,6 @@

81587

nafter = d + nbefore;

81588

nbefore = 0;

81589

}

81590

- nzero_real = nzero;

81591

if (nzero > d)

81592

nzero = d;

81593

}

81594

@@ -218,7 +214,7 @@

81595

}

81596

else

81597

{

81598

- nzero = nzero_real = 0;

81599

+ nzero = 0;

81600

nafter = d;

81601

}

81602

81603

@@ -373,7 +369,7 @@

81604

updown:

81605

81606

rchar = '0';

81607

- if (w > 0 && d == 0 && p == 0)

81608

+ if (ft != FMT_F && w > 0 && d == 0 && p == 0)

81609

nbefore = 1;

81610

/* Scan for trailing zeros to see if we really need to round it. */

81611

for(i = nbefore + nafter; i < ndigits; i++)

81612

@@ -386,13 +382,14 @@

81613

do_rnd:

81614

81615

if (nbefore + nafter == 0)

81616

+ /* Handle the case Fw.0 and value < 1.0 */

81617

{

81618

ndigits = 0;

81619

- if (nzero_real == d && digits[0] >= rchar)

81620

+ if (digits[0] >= rchar)

81621

{

81622

/* We rounded to zero but shouldn't have */

81623

- nzero--;

81624

- nafter = 1;

81625

+ nbefore = 1;

81626

+ digits--;

81627

digits[0] = '1';

81628

ndigits = 1;

81629

}

81630

@@ -990,7 +987,7 @@

81631

int d = f->u.real.d;\

81632

int w = f->u.real.w;\

81633

fnode newf;\

81634

- GFC_REAL_ ## x rexp_d, r = 0.5;\

81635

+ GFC_REAL_ ## x exp_d, r = 0.5, r_sc;\

81636

int low, high, mid;\

81637

int ubound, lbound;\

81638

char *p, pad = ' ';\

81639

@@ -997,6 +994,7 @@

81640

int save_scale_factor, nb = 0;\

81641

try result;\

81642

int nprinted, precision;\

81643

+ volatile GFC_REAL_ ## x temp;\

81644

\

81645

save_scale_factor = dtp->u.p.scale_factor;\

81646

\

81647

@@ -1015,10 +1013,13 @@

81648

break;\

81649

}\

81650

\

81651

- rexp_d = calculate_exp_ ## x (-d);\

81652

- if ((m > 0.0 && ((m < 0.1 - 0.1 * r * rexp_d) || (rexp_d * (m + r) >= 1.0)))\

81653

+ exp_d = calculate_exp_ ## x (d);\

81654

+ r_sc = (1 - r / exp_d);\

81655

+ temp = 0.1 * r_sc;\

81656

+ if ((m > 0.0 && ((m < temp) || (r >= (exp_d - m))))\

81657

|| ((m == 0.0) && !(compile_options.allow_std\

81658

- & (GFC_STD_F2003 | GFC_STD_F2008))))\

81659

+ & (GFC_STD_F2003 | GFC_STD_F2008)))\

81660

+ || d == 0)\

81661

{ \

81662

newf.format = FMT_E;\

81663

newf.u.real.w = w;\

81664

@@ -1038,10 +1039,9 @@

81665

\

81666

while (low <= high)\

81667

{ \

81668

- volatile GFC_REAL_ ## x temp;\

81669

mid = (low + high) / 2;\

81670

\

81671

- temp = (calculate_exp_ ## x (mid - 1) * (1 - r * rexp_d));\

81672

+ temp = (calculate_exp_ ## x (mid - 1) * r_sc);\

81673

\

81674

if (m < temp)\

81675

{ \

81676

@@ -1121,14 +1121,36 @@

81677

/* EN format is tricky since the number of significant digits depends

81678

on the magnitude. Solve it by first printing a temporary value and

81679

figure out the number of significant digits from the printed

81680

- exponent. */

81681

+ exponent. Values y, 0.95*10.0**e <= y <10.0**e, are rounded to

81682

+ 10.0**e even when the final result will not be rounded to 10.0**e.

81683

+ For these values the exponent returned by atoi has to be decremented

81684

+ by one. The values y in the ranges

81685

+ (1000.0-0.5*10.0**(-d))*10.0**(3*n) <= y < 10.0*(3*(n+1))

81686

+ (100.0-0.5*10.0**(-d))*10.0**(3*n) <= y < 10.0*(3*n+2)

81687

+ (10.0-0.5*10.0**(-d))*10.0**(3*n) <= y < 10.0*(3*n+1)

81688

+ are correctly rounded respectively to 1.0...0*10.0*(3*(n+1)),

81689

+ 100.0...0*10.0*(3*n), and 10.0...0*10.0*(3*n), where 0...0

81690

+ represents d zeroes, by the lines 279 to 297. */

81691

81692

#define EN_PREC(x,y)\

81693

{\

81694

- GFC_REAL_ ## x tmp; \

81695

- tmp = * (GFC_REAL_ ## x *)source; \

81696

+ volatile GFC_REAL_ ## x tmp, one = 1.0;\

81697

+ tmp = * (GFC_REAL_ ## x *)source;\

81698

if (isfinite (tmp)) \

81699

- nprinted = DTOA(y,0,tmp); \

81700

+ {\

81701

+ nprinted = DTOA(y,0,tmp);\

81702

+ int e = atoi (&buffer[4]);\

81703

+ if (buffer[1] == '1')\

81704

+ {\

81705

+ tmp = (calculate_exp_ ## x (-e)) * tmp;\

81706

+ tmp = one - (tmp < 0 ? -tmp : tmp); \

81707

+ if (tmp > 0)\

81708

+ e = e - 1;\

81709

+ }\

81710

+ nbefore = e%3;\

81711

+ if (nbefore < 0)\

81712

+ nbefore = 3 + nbefore;\

81713

+ }\

81714

else\

81715

nprinted = -1;\

81716

}\

81717

@@ -1140,6 +1162,7 @@

81718

int nprinted;

81719

char buffer[10];

81720

const size_t size = 10;

81721

+ int nbefore; /* digits before decimal point - 1. */

81722

81723

switch (len)

81724

{

81725

@@ -1172,16 +1195,6 @@

81726

if (nprinted == -1)

81727

return -1;

81728

81729

- int e = atoi (&buffer[5]);

81730

- int nbefore; /* digits before decimal point - 1. */

81731

- if (e >= 0)

81732

- nbefore = e % 3;

81733

- else

81734

- {

81735

- nbefore = (-e) % 3;

81736

- if (nbefore != 0)

81737

- nbefore = 3 - nbefore;

81738

- }

81739

int prec = f->u.real.d + nbefore;

81740

if (dtp->u.p.current_unit->round_status != ROUND_UNSPECIFIED

81741

&& dtp->u.p.current_unit->round_status != ROUND_PROCDEFINED)

81742

Index: libffi/configure

81743

===================================================================

81744

--- a/src/libffi/configure (.../tags/gcc_4_8_2_release)

81745

+++ b/src/libffi/configure (.../branches/gcc-4_8-branch)

81746

@@ -613,6 +613,7 @@

81747

FFI_EXEC_TRAMPOLINE_TABLE

81748

FFI_EXEC_TRAMPOLINE_TABLE_FALSE

81749

FFI_EXEC_TRAMPOLINE_TABLE_TRUE

81750

+HAVE_LONG_DOUBLE_VARIANT

81751

HAVE_LONG_DOUBLE

81752

ALLOCA

81753

TILE_FALSE

81754

@@ -6392,7 +6393,7 @@

81755

rm -rf conftest*

81756

;;

81757

81758

-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \

81759

+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \

81760

s390*-*linux*|s390*-*tpf*|sparc*-*linux*)

81761

# Find out which ABI we are using.

81762

echo 'int i;' > conftest.$ac_ext

81763

@@ -6417,7 +6418,10 @@

81764

;;

81765

esac

81766

;;

81767

- ppc64-*linux*|powerpc64-*linux*)

81768

+ powerpc64le-*linux*)

81769

+ LD="${LD-ld} -m elf32lppclinux"

81770

+ ;;

81771

+ powerpc64-*linux*)

81772

LD="${LD-ld} -m elf32ppclinux"

81773

;;

81774

s390x-*linux*)

81775

@@ -6436,7 +6440,10 @@

81776

x86_64-*linux*)

81777

LD="${LD-ld} -m elf_x86_64"

81778

;;

81779

- ppc*-*linux*|powerpc*-*linux*)

81780

+ powerpcle-*linux*)

81781

+ LD="${LD-ld} -m elf64lppc"

81782

+ ;;

81783

+ powerpc-*linux*)

81784

LD="${LD-ld} -m elf64ppc"

81785

;;

81786

s390*-*linux*|s390*-*tpf*)

81787

@@ -10900,7 +10907,7 @@

81788

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

81789

lt_status=$lt_dlunknown

81790

cat > conftest.$ac_ext <<_LT_EOF

81791

-#line 10903 "configure"

81792

+#line 10910 "configure"

81793

#include "confdefs.h"

81794

81795

#if HAVE_DLFCN_H

81796

@@ -11006,7 +11013,7 @@

81797

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

81798

lt_status=$lt_dlunknown

81799

cat > conftest.$ac_ext <<_LT_EOF

81800

-#line 11009 "configure"

81801

+#line 11016 "configure"

81802

#include "confdefs.h"

81803

81804

#if HAVE_DLFCN_H

81805

@@ -11443,6 +11450,7 @@

81806

81807

81808

TARGETDIR="unknown"

81809

+HAVE_LONG_DOUBLE_VARIANT=0

81810

case "$host" in

81811

aarch64*-*-*)

81812

TARGET=AARCH64; TARGETDIR=aarch64

81813

@@ -11540,6 +11548,7 @@

81814

81815

powerpc*-*-linux* | powerpc-*-sysv*)

81816

TARGET=POWERPC; TARGETDIR=powerpc

81817

+ HAVE_LONG_DOUBLE_VARIANT=1

81818

;;

81819

powerpc-*-amigaos*)

81820

TARGET=POWERPC; TARGETDIR=powerpc

81821

@@ -11555,6 +11564,7 @@

81822

;;

81823

powerpc-*-freebsd* | powerpc-*-openbsd*)

81824

TARGET=POWERPC_FREEBSD; TARGETDIR=powerpc

81825

+ HAVE_LONG_DOUBLE_VARIANT=1

81826

;;

81827

powerpc64-*-freebsd*)

81828

TARGET=POWERPC; TARGETDIR=powerpc

81829

@@ -12230,17 +12240,25 @@

81830

# Also AC_SUBST this variable for ffi.h.

81831

if test -z "$HAVE_LONG_DOUBLE"; then

81832

HAVE_LONG_DOUBLE=0

81833

- if test $ac_cv_sizeof_double != $ac_cv_sizeof_long_double; then

81834

- if test $ac_cv_sizeof_long_double != 0; then

81835

+ if test $ac_cv_sizeof_long_double != 0; then

81836

+ if test $HAVE_LONG_DOUBLE_VARIANT != 0; then

81837

+

81838

+$as_echo "#define HAVE_LONG_DOUBLE_VARIANT 1" >>confdefs.h

81839

+

81840

HAVE_LONG_DOUBLE=1

81841

+ else

81842

+ if test $ac_cv_sizeof_double != $ac_cv_sizeof_long_double; then

81843

+ HAVE_LONG_DOUBLE=1

81844

81845

$as_echo "#define HAVE_LONG_DOUBLE 1" >>confdefs.h

81846

81847

+ fi

81848

fi

81849

fi

81850

fi

81851

81852

81853

+

81854

{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether byte ordering is bigendian" >&5

81855

$as_echo_n "checking whether byte ordering is bigendian... " >&6; }

81856

if test "${ac_cv_c_bigendian+set}" = set; then :

81857

Index: libffi/Makefile.in

81858

===================================================================

81859

--- a/src/libffi/Makefile.in (.../tags/gcc_4_8_2_release)

81860

+++ b/src/libffi/Makefile.in (.../branches/gcc-4_8-branch)

81861

@@ -48,10 +48,10 @@

81862

@IA64_TRUE@am__append_11 = src/ia64/ffi.c src/ia64/unix.S

81863

@M32R_TRUE@am__append_12 = src/m32r/sysv.S src/m32r/ffi.c

81864

@M68K_TRUE@am__append_13 = src/m68k/ffi.c src/m68k/sysv.S

81865

-@POWERPC_TRUE@am__append_14 = src/powerpc/ffi.c src/powerpc/sysv.S src/powerpc/ppc_closure.S src/powerpc/linux64.S src/powerpc/linux64_closure.S

81866

+@POWERPC_TRUE@am__append_14 = src/powerpc/ffi.c src/powerpc/ffi_sysv.c src/powerpc/ffi_linux64.c src/powerpc/sysv.S src/powerpc/ppc_closure.S src/powerpc/linux64.S src/powerpc/linux64_closure.S

81867

@POWERPC_AIX_TRUE@am__append_15 = src/powerpc/ffi_darwin.c src/powerpc/aix.S src/powerpc/aix_closure.S

81868

@POWERPC_DARWIN_TRUE@am__append_16 = src/powerpc/ffi_darwin.c src/powerpc/darwin.S src/powerpc/darwin_closure.S

81869

-@POWERPC_FREEBSD_TRUE@am__append_17 = src/powerpc/ffi.c src/powerpc/sysv.S src/powerpc/ppc_closure.S

81870

+@POWERPC_FREEBSD_TRUE@am__append_17 = src/powerpc/ffi.c src/powerpc/ffi_sysv.c src/powerpc/sysv.S src/powerpc/ppc_closure.S

81871

@AARCH64_TRUE@am__append_18 = src/aarch64/sysv.S src/aarch64/ffi.c

81872

@ARM_TRUE@am__append_19 = src/arm/sysv.S src/arm/ffi.c

81873

@ARM_TRUE@@FFI_EXEC_TRAMPOLINE_TABLE_TRUE@am__append_20 = src/arm/trampoline.S

81874

@@ -133,7 +133,9 @@

81875

@IA64_TRUE@am__objects_11 = src/ia64/ffi.lo src/ia64/unix.lo

81876

@M32R_TRUE@am__objects_12 = src/m32r/sysv.lo src/m32r/ffi.lo

81877

@M68K_TRUE@am__objects_13 = src/m68k/ffi.lo src/m68k/sysv.lo

81878

-@POWERPC_TRUE@am__objects_14 = src/powerpc/ffi.lo src/powerpc/sysv.lo \

81879

+@POWERPC_TRUE@am__objects_14 = src/powerpc/ffi.lo \

81880

+@POWERPC_TRUE@ src/powerpc/ffi_sysv.lo \

81881

+@POWERPC_TRUE@ src/powerpc/ffi_linux64.lo src/powerpc/sysv.lo \

81882

@POWERPC_TRUE@ src/powerpc/ppc_closure.lo \

81883

@POWERPC_TRUE@ src/powerpc/linux64.lo \

81884

@POWERPC_TRUE@ src/powerpc/linux64_closure.lo

81885

@@ -144,6 +146,7 @@

81886

@POWERPC_DARWIN_TRUE@ src/powerpc/darwin.lo \

81887

@POWERPC_DARWIN_TRUE@ src/powerpc/darwin_closure.lo

81888

@POWERPC_FREEBSD_TRUE@am__objects_17 = src/powerpc/ffi.lo \

81889

+@POWERPC_FREEBSD_TRUE@ src/powerpc/ffi_sysv.lo \

81890

@POWERPC_FREEBSD_TRUE@ src/powerpc/sysv.lo \

81891

@POWERPC_FREEBSD_TRUE@ src/powerpc/ppc_closure.lo

81892

@AARCH64_TRUE@am__objects_18 = src/aarch64/sysv.lo src/aarch64/ffi.lo

81893

@@ -278,6 +281,7 @@

81894

FGREP = @FGREP@

81895

GREP = @GREP@

81896

HAVE_LONG_DOUBLE = @HAVE_LONG_DOUBLE@

81897

+HAVE_LONG_DOUBLE_VARIANT = @HAVE_LONG_DOUBLE_VARIANT@

81898

INSTALL = @INSTALL@

81899

INSTALL_DATA = @INSTALL_DATA@

81900

INSTALL_PROGRAM = @INSTALL_PROGRAM@

81901

@@ -387,10 +391,12 @@

81902

src/ia64/unix.S src/mips/ffi.c src/mips/n32.S src/mips/o32.S \

81903

src/mips/ffitarget.h src/m32r/ffi.c src/m32r/sysv.S \

81904

src/m32r/ffitarget.h src/m68k/ffi.c src/m68k/sysv.S \

81905

- src/m68k/ffitarget.h src/powerpc/ffi.c src/powerpc/sysv.S \

81906

- src/powerpc/linux64.S src/powerpc/linux64_closure.S \

81907

- src/powerpc/ppc_closure.S src/powerpc/asm.h \

81908

- src/powerpc/aix.S src/powerpc/darwin.S \

81909

+ src/m68k/ffitarget.h \

81910

+ src/powerpc/ffi.c src/powerpc/ffi_powerpc.h \

81911

+ src/powerpc/ffi_sysv.c src/powerpc/ffi_linux64.c \

81912

+ src/powerpc/sysv.S src/powerpc/linux64.S \

81913

+ src/powerpc/linux64_closure.S src/powerpc/ppc_closure.S \

81914

+ src/powerpc/asm.h src/powerpc/aix.S src/powerpc/darwin.S \

81915

src/powerpc/aix_closure.S src/powerpc/darwin_closure.S \

81916

src/powerpc/ffi_darwin.c src/powerpc/ffitarget.h \

81917

src/s390/ffi.c src/s390/sysv.S src/s390/ffitarget.h \

81918

@@ -711,6 +717,10 @@

81919

@: > src/powerpc/$(DEPDIR)/$(am__dirstamp)

81920

src/powerpc/ffi.lo: src/powerpc/$(am__dirstamp) \

81921

src/powerpc/$(DEPDIR)/$(am__dirstamp)

81922

+src/powerpc/ffi_sysv.lo: src/powerpc/$(am__dirstamp) \

81923

+ src/powerpc/$(DEPDIR)/$(am__dirstamp)

81924

+src/powerpc/ffi_linux64.lo: src/powerpc/$(am__dirstamp) \

81925

+ src/powerpc/$(DEPDIR)/$(am__dirstamp)

81926

src/powerpc/sysv.lo: src/powerpc/$(am__dirstamp) \

81927

src/powerpc/$(DEPDIR)/$(am__dirstamp)

81928

src/powerpc/ppc_closure.lo: src/powerpc/$(am__dirstamp) \

81929

@@ -912,6 +922,10 @@

81930

-rm -f src/powerpc/ffi.lo

81931

-rm -f src/powerpc/ffi_darwin.$(OBJEXT)

81932

-rm -f src/powerpc/ffi_darwin.lo

81933

+ -rm -f src/powerpc/ffi_linux64.$(OBJEXT)

81934

+ -rm -f src/powerpc/ffi_linux64.lo

81935

+ -rm -f src/powerpc/ffi_sysv.$(OBJEXT)

81936

+ -rm -f src/powerpc/ffi_sysv.lo

81937

-rm -f src/powerpc/linux64.$(OBJEXT)

81938

-rm -f src/powerpc/linux64.lo

81939

-rm -f src/powerpc/linux64_closure.$(OBJEXT)

81940

@@ -1009,6 +1023,8 @@

81941

@AMDEP_TRUE@@am__include@ @am__quote@src/powerpc/$(DEPDIR)/darwin_closure.Plo@am__quote@

81942

@AMDEP_TRUE@@am__include@ @am__quote@src/powerpc/$(DEPDIR)/ffi.Plo@am__quote@

81943

@AMDEP_TRUE@@am__include@ @am__quote@src/powerpc/$(DEPDIR)/ffi_darwin.Plo@am__quote@

81944

+@AMDEP_TRUE@@am__include@ @am__quote@src/powerpc/$(DEPDIR)/ffi_linux64.Plo@am__quote@

81945

+@AMDEP_TRUE@@am__include@ @am__quote@src/powerpc/$(DEPDIR)/ffi_sysv.Plo@am__quote@

81946

@AMDEP_TRUE@@am__include@ @am__quote@src/powerpc/$(DEPDIR)/linux64.Plo@am__quote@

81947

@AMDEP_TRUE@@am__include@ @am__quote@src/powerpc/$(DEPDIR)/linux64_closure.Plo@am__quote@

81948

@AMDEP_TRUE@@am__include@ @am__quote@src/powerpc/$(DEPDIR)/ppc_closure.Plo@am__quote@

81949

Index: libffi/include/ffi.h.in

81950

===================================================================

81951

--- a/src/libffi/include/ffi.h.in (.../tags/gcc_4_8_2_release)

81952

+++ b/src/libffi/include/ffi.h.in (.../branches/gcc-4_8-branch)

81953

@@ -207,6 +207,11 @@

81954

#endif

81955

} ffi_cif;

81956

81957

+#if HAVE_LONG_DOUBLE_VARIANT

81958

+/* Used to adjust size/alignment of ffi types. */

81959

+void ffi_prep_types (ffi_abi abi);

81960

+# endif

81961

+

81962

/* Used internally, but overridden by some architectures */

81963

ffi_status ffi_prep_cif_core(ffi_cif *cif,

81964

ffi_abi abi,

81965

Index: libffi/include/Makefile.in

81966

===================================================================

81967

--- a/src/libffi/include/Makefile.in (.../tags/gcc_4_8_2_release)

81968

+++ b/src/libffi/include/Makefile.in (.../branches/gcc-4_8-branch)

81969

@@ -113,6 +113,7 @@

81970

FGREP = @FGREP@

81971

GREP = @GREP@

81972

HAVE_LONG_DOUBLE = @HAVE_LONG_DOUBLE@

81973

+HAVE_LONG_DOUBLE_VARIANT = @HAVE_LONG_DOUBLE_VARIANT@

81974

INSTALL = @INSTALL@

81975

INSTALL_DATA = @INSTALL_DATA@

81976

INSTALL_PROGRAM = @INSTALL_PROGRAM@

81977

Index: libffi/fficonfig.h.in

81978

===================================================================

81979

--- a/src/libffi/fficonfig.h.in (.../tags/gcc_4_8_2_release)

81980

+++ b/src/libffi/fficonfig.h.in (.../branches/gcc-4_8-branch)

81981

@@ -73,6 +73,9 @@

81982

/* Define if you have the long double type and it is bigger than a double */

81983

#undef HAVE_LONG_DOUBLE

81984

81985

+/* Define if you support more than one size of the long double type */

81986

+#undef HAVE_LONG_DOUBLE_VARIANT

81987

+

81988

/* Define to 1 if you have the `memcpy' function. */

81989

#undef HAVE_MEMCPY

81990

81991

Index: libffi/src/powerpc/ppc_closure.S

81992

===================================================================

81993

--- a/src/libffi/src/powerpc/ppc_closure.S (.../tags/gcc_4_8_2_release)

81994

+++ b/src/libffi/src/powerpc/ppc_closure.S (.../branches/gcc-4_8-branch)

81995

@@ -31,7 +31,7 @@

81996

81997

.file "ppc_closure.S"

81998

81999

-#ifndef __powerpc64__

82000

+#ifndef POWERPC64

82001

82002

ENTRY(ffi_closure_SYSV)

82003

.LFB1:

82004

@@ -238,7 +238,7 @@

82005

lwz %r3,112+0(%r1)

82006

lwz %r4,112+4(%r1)

82007

lwz %r5,112+8(%r1)

82008

- bl .Luint128

82009

+ b .Luint128

82010

82011

# The return types below are only used when the ABI type is FFI_SYSV.

82012

# case FFI_SYSV_TYPE_SMALL_STRUCT + 1. One byte struct.

82013

@@ -378,8 +378,7 @@

82014

.align 2

82015

.LEFDE1:

82016

82017

-#endif

82018

-

82019

#if defined __ELF__ && defined __linux__

82020

.section .note.GNU-stack,"",@progbits

82021

#endif

82022

+#endif

82023

Index: libffi/src/powerpc/ffitarget.h

82024

===================================================================

82025

--- a/src/libffi/src/powerpc/ffitarget.h (.../tags/gcc_4_8_2_release)

82026

+++ b/src/libffi/src/powerpc/ffitarget.h (.../branches/gcc-4_8-branch)

82027

@@ -60,45 +60,76 @@

82028

typedef enum ffi_abi {

82029

FFI_FIRST_ABI = 0,

82030

82031

-#ifdef POWERPC

82032

- FFI_SYSV,

82033

- FFI_GCC_SYSV,

82034

- FFI_LINUX64,

82035

- FFI_LINUX,

82036

- FFI_LINUX_SOFT_FLOAT,

82037

-# if defined(POWERPC64)

82038

- FFI_DEFAULT_ABI = FFI_LINUX64,

82039

-# elif defined(__NO_FPRS__)

82040

- FFI_DEFAULT_ABI = FFI_LINUX_SOFT_FLOAT,

82041

-# elif (__LDBL_MANT_DIG__ == 106)

82042

- FFI_DEFAULT_ABI = FFI_LINUX,

82043

-# else

82044

- FFI_DEFAULT_ABI = FFI_GCC_SYSV,

82045

-# endif

82046

-#endif

82047

-

82048

-#ifdef POWERPC_AIX

82049

+#if defined (POWERPC_AIX)

82050

FFI_AIX,

82051

FFI_DARWIN,

82052

FFI_DEFAULT_ABI = FFI_AIX,

82053

-#endif

82054

+ FFI_LAST_ABI

82055

82056

-#ifdef POWERPC_DARWIN

82057

+#elif defined (POWERPC_DARWIN)

82058

FFI_AIX,

82059

FFI_DARWIN,

82060

FFI_DEFAULT_ABI = FFI_DARWIN,

82061

-#endif

82062

+ FFI_LAST_ABI

82063

82064

-#ifdef POWERPC_FREEBSD

82065

- FFI_SYSV,

82066

- FFI_GCC_SYSV,

82067

- FFI_LINUX64,

82068

- FFI_LINUX,

82069

- FFI_LINUX_SOFT_FLOAT,

82070

- FFI_DEFAULT_ABI = FFI_SYSV,

82071

+#else

82072

+ /* The FFI_COMPAT values are used by old code. Since libffi may be

82073

+ a shared library we have to support old values for backwards

82074

+ compatibility. */

82075

+ FFI_COMPAT_SYSV,

82076

+ FFI_COMPAT_GCC_SYSV,

82077

+ FFI_COMPAT_LINUX64,

82078

+ FFI_COMPAT_LINUX,

82079

+ FFI_COMPAT_LINUX_SOFT_FLOAT,

82080

+

82081

+# if defined (POWERPC64)

82082

+ /* This bit, always set in new code, must not be set in any of the

82083

+ old FFI_COMPAT values that might be used for 64-bit linux. We

82084

+ only need worry about FFI_COMPAT_LINUX64, but to be safe avoid

82085

+ all old values. */

82086

+ FFI_LINUX = 8,

82087

+ /* This and following bits can reuse FFI_COMPAT values. */

82088

+ FFI_LINUX_STRUCT_ALIGN = 1,

82089

+ FFI_LINUX_LONG_DOUBLE_128 = 2,

82090

+ FFI_DEFAULT_ABI = (FFI_LINUX

82091

+# ifdef __STRUCT_PARM_ALIGN__

82092

+ | FFI_LINUX_STRUCT_ALIGN

82093

+# endif

82094

+# ifdef __LONG_DOUBLE_128__

82095

+ | FFI_LINUX_LONG_DOUBLE_128

82096

+# endif

82097

+ ),

82098

+ FFI_LAST_ABI = 12

82099

+

82100

+# else

82101

+ /* This bit, always set in new code, must not be set in any of the

82102

+ old FFI_COMPAT values that might be used for 32-bit linux/sysv/bsd. */

82103

+ FFI_SYSV = 8,

82104

+ /* This and following bits can reuse FFI_COMPAT values. */

82105

+ FFI_SYSV_SOFT_FLOAT = 1,

82106

+ FFI_SYSV_STRUCT_RET = 2,

82107

+ FFI_SYSV_IBM_LONG_DOUBLE = 4,

82108

+ FFI_SYSV_LONG_DOUBLE_128 = 16,

82109

+

82110

+ FFI_DEFAULT_ABI = (FFI_SYSV

82111

+# ifdef __NO_FPRS__

82112

+ | FFI_SYSV_SOFT_FLOAT

82113

+# endif

82114

+# if (defined (__SVR4_STRUCT_RETURN) \

82115

+ || defined (POWERPC_FREEBSD) && !defined (__AIX_STRUCT_RETURN))

82116

+ | FFI_SYSV_STRUCT_RET

82117

+# endif

82118

+# if __LDBL_MANT_DIG__ == 106

82119

+ | FFI_SYSV_IBM_LONG_DOUBLE

82120

+# endif

82121

+# ifdef __LONG_DOUBLE_128__

82122

+ | FFI_SYSV_LONG_DOUBLE_128

82123

+# endif

82124

+ ),

82125

+ FFI_LAST_ABI = 32

82126

+# endif

82127

#endif

82128

82129

- FFI_LAST_ABI

82130

} ffi_abi;

82131

#endif

82132

82133

@@ -106,6 +137,10 @@

82134

82135

#define FFI_CLOSURES 1

82136

#define FFI_NATIVE_RAW_API 0

82137

+#if defined (POWERPC) || defined (POWERPC_FREEBSD)

82138

+# define FFI_TARGET_SPECIFIC_VARIADIC 1

82139

+# define FFI_EXTRA_CIF_FIELDS unsigned nfixedargs

82140

+#endif

82141

82142

/* For additional types like the below, take care about the order in

82143

ppc_closures.S. They must follow after the FFI_TYPE_LAST. */

82144

@@ -113,19 +148,26 @@

82145

/* Needed for soft-float long-double-128 support. */

82146

#define FFI_TYPE_UINT128 (FFI_TYPE_LAST + 1)

82147

82148

-/* Needed for FFI_SYSV small structure returns.

82149

- We use two flag bits, (FLAG_SYSV_SMST_R3, FLAG_SYSV_SMST_R4) which are

82150

- defined in ffi.c, to determine the exact return type and its size. */

82151

+/* Needed for FFI_SYSV small structure returns. */

82152

#define FFI_SYSV_TYPE_SMALL_STRUCT (FFI_TYPE_LAST + 2)

82153

82154

-#if defined(POWERPC64) || defined(POWERPC_AIX)

82155

+/* Used by ELFv2 for homogenous structure returns. */

82156

+#define FFI_V2_TYPE_FLOAT_HOMOG (FFI_TYPE_LAST + 1)

82157

+#define FFI_V2_TYPE_DOUBLE_HOMOG (FFI_TYPE_LAST + 2)

82158

+#define FFI_V2_TYPE_SMALL_STRUCT (FFI_TYPE_LAST + 3)

82159

+

82160

+#if _CALL_ELF == 2

82161

+# define FFI_TRAMPOLINE_SIZE 32

82162

+#else

82163

+# if defined(POWERPC64) || defined(POWERPC_AIX)

82164

# if defined(POWERPC_DARWIN64)

82165

# define FFI_TRAMPOLINE_SIZE 48

82166

# else

82167

# define FFI_TRAMPOLINE_SIZE 24

82168

# endif

82169

-#else /* POWERPC || POWERPC_AIX */

82170

+# else /* POWERPC || POWERPC_AIX */

82171

# define FFI_TRAMPOLINE_SIZE 40

82172

+# endif

82173

#endif

82174

82175

#ifndef LIBFFI_ASM

82176

Index: libffi/src/powerpc/ffi.c

82177

===================================================================

82178

--- a/src/libffi/src/powerpc/ffi.c (.../tags/gcc_4_8_2_release)

82179

+++ b/src/libffi/src/powerpc/ffi.c (.../branches/gcc-4_8-branch)

82180

@@ -1,5 +1,6 @@

82181

/* -----------------------------------------------------------------------

82182

82183

82184

82185

82186

82187

82188

@@ -27,966 +28,104 @@

82189

OTHER DEALINGS IN THE SOFTWARE.

82190

----------------------------------------------------------------------- */

82191

82192

-#include <ffi.h>

82193

-#include <ffi_common.h>

82194

+#include "ffi.h"

82195

+#include "ffi_common.h"

82196

+#include "ffi_powerpc.h"

82197

82198

-#include <stdlib.h>

82199

-#include <stdio.h>

82200

-

82201

-

82202

-extern void ffi_closure_SYSV (void);

82203

-extern void FFI_HIDDEN ffi_closure_LINUX64 (void);

82204

-

82205

-enum {

82206

- /* The assembly depends on these exact flags. */

82207

- FLAG_RETURNS_SMST = 1 << (31-31), /* Used for FFI_SYSV small structs. */

82208

- FLAG_RETURNS_NOTHING = 1 << (31-30), /* These go in cr7 */

82209

-#ifndef __NO_FPRS__

82210

- FLAG_RETURNS_FP = 1 << (31-29),

82211

-#endif

82212

- FLAG_RETURNS_64BITS = 1 << (31-28),

82213

-

82214

- FLAG_RETURNS_128BITS = 1 << (31-27), /* cr6 */

82215

-

82216

- FLAG_ARG_NEEDS_COPY = 1 << (31- 7),

82217

-#ifndef __NO_FPRS__

82218

- FLAG_FP_ARGUMENTS = 1 << (31- 6), /* cr1.eq; specified by ABI */

82219

-#endif

82220

- FLAG_4_GPR_ARGUMENTS = 1 << (31- 5),

82221

- FLAG_RETVAL_REFERENCE = 1 << (31- 4)

82222

-};

82223

-

82224

-/* About the SYSV ABI. */

82225

-#define ASM_NEEDS_REGISTERS 4

82226

-#define NUM_GPR_ARG_REGISTERS 8

82227

-#ifndef __NO_FPRS__

82228

-# define NUM_FPR_ARG_REGISTERS 8

82229

-#endif

82230

-

82231

-/* ffi_prep_args_SYSV is called by the assembly routine once stack space

82232

- has been allocated for the function's arguments.

82233

-

82234

- The stack layout we want looks like this:

82235

-

82236

- | Return address from ffi_call_SYSV 4bytes | higher addresses

82237

- |--------------------------------------------|

82238

- | Previous backchain pointer 4 | stack pointer here

82239

- |--------------------------------------------|<+ <<< on entry to

82240

- | Saved r28-r31 4*4 | | ffi_call_SYSV

82241

- |--------------------------------------------| |

82242

- | GPR registers r3-r10 8*4 | | ffi_call_SYSV

82243

- |--------------------------------------------| |

82244

- | FPR registers f1-f8 (optional) 8*8 | |

82245

- |--------------------------------------------| | stack |

82246

- | Space for copied structures | | grows |

82247

- |--------------------------------------------| | down V

82248

- | Parameters that didn't fit in registers | |

82249

- |--------------------------------------------| | lower addresses

82250

- | Space for callee's LR 4 | |

82251

- |--------------------------------------------| | stack pointer here

82252

- | Current backchain pointer 4 |-/ during

82253

- |--------------------------------------------| <<< ffi_call_SYSV

82254

-

82255

-*/

82256

-

82257

-void

82258

-ffi_prep_args_SYSV (extended_cif *ecif, unsigned *const stack)

82259

+#if HAVE_LONG_DOUBLE_VARIANT

82260

+/* Adjust ffi_type_longdouble. */

82261

+void FFI_HIDDEN

82262

+ffi_prep_types (ffi_abi abi)

82263

{

82264

- const unsigned bytes = ecif->cif->bytes;

82265

- const unsigned flags = ecif->cif->flags;

82266

-

82267

- typedef union {

82268

- char *c;

82269

- unsigned *u;

82270

- long long *ll;

82271

- float *f;

82272

- double *d;

82273

- } valp;

82274

-

82275

- /* 'stacktop' points at the previous backchain pointer. */

82276

- valp stacktop;

82277

-

82278

- /* 'gpr_base' points at the space for gpr3, and grows upwards as

82279

- we use GPR registers. */

82280

- valp gpr_base;

82281

- int intarg_count;

82282

-

82283

-#ifndef __NO_FPRS__

82284

- /* 'fpr_base' points at the space for fpr1, and grows upwards as

82285

- we use FPR registers. */

82286

- valp fpr_base;

82287

- int fparg_count;

82288

-#endif

82289

-

82290

- /* 'copy_space' grows down as we put structures in it. It should

82291

- stay 16-byte aligned. */

82292

- valp copy_space;

82293

-

82294

- /* 'next_arg' grows up as we put parameters in it. */

82295

- valp next_arg;

82296

-

82297

- int i;

82298

- ffi_type **ptr;

82299

-#ifndef __NO_FPRS__

82300

- double double_tmp;

82301

-#endif

82302

- union {

82303

- void **v;

82304

- char **c;

82305

- signed char **sc;

82306

- unsigned char **uc;

82307

- signed short **ss;

82308

- unsigned short **us;

82309

- unsigned int **ui;

82310

- long long **ll;

82311

- float **f;

82312

- double **d;

82313

- } p_argv;

82314

- size_t struct_copy_size;

82315

- unsigned gprvalue;

82316

-

82317

- stacktop.c = (char *) stack + bytes;

82318

- gpr_base.u = stacktop.u - ASM_NEEDS_REGISTERS - NUM_GPR_ARG_REGISTERS;

82319

- intarg_count = 0;

82320

-#ifndef __NO_FPRS__

82321

- fpr_base.d = gpr_base.d - NUM_FPR_ARG_REGISTERS;

82322

- fparg_count = 0;

82323

- copy_space.c = ((flags & FLAG_FP_ARGUMENTS) ? fpr_base.c : gpr_base.c);

82324

-#else

82325

- copy_space.c = gpr_base.c;

82326

-#endif

82327

- next_arg.u = stack + 2;

82328

-

82329

- /* Check that everything starts aligned properly. */

82330

- FFI_ASSERT (((unsigned long) (char *) stack & 0xF) == 0);

82331

- FFI_ASSERT (((unsigned long) copy_space.c & 0xF) == 0);

82332

- FFI_ASSERT (((unsigned long) stacktop.c & 0xF) == 0);

82333

- FFI_ASSERT ((bytes & 0xF) == 0);

82334

- FFI_ASSERT (copy_space.c >= next_arg.c);

82335

-

82336

- /* Deal with return values that are actually pass-by-reference. */

82337

- if (flags & FLAG_RETVAL_REFERENCE)

82338

- {

82339

- *gpr_base.u++ = (unsigned long) (char *) ecif->rvalue;

82340

- intarg_count++;

82341

- }

82342

-

82343

- /* Now for the arguments. */

82344

- p_argv.v = ecif->avalue;

82345

- for (ptr = ecif->cif->arg_types, i = ecif->cif->nargs;

82346

- i > 0;

82347

- i--, ptr++, p_argv.v++)

82348

- {

82349

- unsigned short typenum = (*ptr)->type;

82350

-

82351

- /* We may need to handle some values depending on ABI */

82352

- if (ecif->cif->abi == FFI_LINUX_SOFT_FLOAT) {

82353

- if (typenum == FFI_TYPE_FLOAT)

82354

- typenum = FFI_TYPE_UINT32;

82355

- if (typenum == FFI_TYPE_DOUBLE)

82356

- typenum = FFI_TYPE_UINT64;

82357

- if (typenum == FFI_TYPE_LONGDOUBLE)

82358

- typenum = FFI_TYPE_UINT128;

82359

- } else if (ecif->cif->abi != FFI_LINUX) {

82360

-#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

82361

- if (typenum == FFI_TYPE_LONGDOUBLE)

82362

- typenum = FFI_TYPE_STRUCT;

82363

-#endif

82364

- }

82365

-

82366

- /* Now test the translated value */

82367

- switch (typenum) {

82368

-#ifndef __NO_FPRS__

82369

- case FFI_TYPE_FLOAT:

82370

- /* With FFI_LINUX_SOFT_FLOAT floats are handled like UINT32. */

82371

- double_tmp = **p_argv.f;

82372

- if (fparg_count >= NUM_FPR_ARG_REGISTERS)

82373

- {

82374

- *next_arg.f = (float) double_tmp;

82375

- next_arg.u += 1;

82376

- intarg_count++;

82377

- }

82378

- else

82379

- *fpr_base.d++ = double_tmp;

82380

- fparg_count++;

82381

- FFI_ASSERT (flags & FLAG_FP_ARGUMENTS);

82382

- break;

82383

-

82384

- case FFI_TYPE_DOUBLE:

82385

- /* With FFI_LINUX_SOFT_FLOAT doubles are handled like UINT64. */

82386

- double_tmp = **p_argv.d;

82387

-

82388

- if (fparg_count >= NUM_FPR_ARG_REGISTERS)

82389

- {

82390

- if (intarg_count >= NUM_GPR_ARG_REGISTERS

82391

- && intarg_count % 2 != 0)

82392

- {

82393

- intarg_count++;

82394

- next_arg.u++;

82395

- }

82396

- *next_arg.d = double_tmp;

82397

- next_arg.u += 2;

82398

- }

82399

- else

82400

- *fpr_base.d++ = double_tmp;

82401

- fparg_count++;

82402

- FFI_ASSERT (flags & FLAG_FP_ARGUMENTS);

82403

- break;

82404

-

82405

-#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

82406

- case FFI_TYPE_LONGDOUBLE:

82407

- double_tmp = (*p_argv.d)[0];

82408

-

82409

- if (fparg_count >= NUM_FPR_ARG_REGISTERS - 1)

82410

- {

82411

- if (intarg_count >= NUM_GPR_ARG_REGISTERS

82412

- && intarg_count % 2 != 0)

82413

- {

82414

- intarg_count++;

82415

- next_arg.u++;

82416

- }

82417

- *next_arg.d = double_tmp;

82418

- next_arg.u += 2;

82419

- double_tmp = (*p_argv.d)[1];

82420

- *next_arg.d = double_tmp;

82421

- next_arg.u += 2;

82422

- }

82423

- else

82424

- {

82425

- *fpr_base.d++ = double_tmp;

82426

- double_tmp = (*p_argv.d)[1];

82427

- *fpr_base.d++ = double_tmp;

82428

- }

82429

-

82430

- fparg_count += 2;

82431

- FFI_ASSERT (flags & FLAG_FP_ARGUMENTS);

82432

- break;

82433

-#endif

82434

-#endif /* have FPRs */

82435

-

82436

- /*

82437

- * The soft float ABI for long doubles works like this, a long double

82438

- * is passed in four consecutive GPRs if available. A maximum of 2

82439

- * long doubles can be passed in gprs. If we do not have 4 GPRs

82440

- * left, the long double is passed on the stack, 4-byte aligned.

82441

- */

82442

- case FFI_TYPE_UINT128: {

82443

- unsigned int int_tmp = (*p_argv.ui)[0];

82444

- unsigned int ii;

82445

- if (intarg_count >= NUM_GPR_ARG_REGISTERS - 3) {

82446

- if (intarg_count < NUM_GPR_ARG_REGISTERS)

82447

- intarg_count += NUM_GPR_ARG_REGISTERS - intarg_count;

82448

- *(next_arg.u++) = int_tmp;

82449

- for (ii = 1; ii < 4; ii++) {

82450

- int_tmp = (*p_argv.ui)[ii];

82451

- *(next_arg.u++) = int_tmp;

82452

- }

82453

- } else {

82454

- *(gpr_base.u++) = int_tmp;

82455

- for (ii = 1; ii < 4; ii++) {

82456

- int_tmp = (*p_argv.ui)[ii];

82457

- *(gpr_base.u++) = int_tmp;

82458

- }

82459

- }

82460

- intarg_count += 4;

82461

- break;

82462

- }

82463

-

82464

- case FFI_TYPE_UINT64:

82465

- case FFI_TYPE_SINT64:

82466

- if (intarg_count == NUM_GPR_ARG_REGISTERS-1)

82467

- intarg_count++;

82468

- if (intarg_count >= NUM_GPR_ARG_REGISTERS)

82469

- {

82470

- if (intarg_count % 2 != 0)

82471

- {

82472

- intarg_count++;

82473

- next_arg.u++;

82474

- }

82475

- *next_arg.ll = **p_argv.ll;

82476

- next_arg.u += 2;

82477

- }

82478

- else

82479

- {

82480

- /* whoops: abi states only certain register pairs

82481

- * can be used for passing long long int

82482

- * specifically (r3,r4), (r5,r6), (r7,r8),

82483

- * (r9,r10) and if next arg is long long but

82484

- * not correct starting register of pair then skip

82485

- * until the proper starting register

82486

- */

82487

- if (intarg_count % 2 != 0)

82488

- {

82489

- intarg_count ++;

82490

- gpr_base.u++;

82491

- }

82492

- *gpr_base.ll++ = **p_argv.ll;

82493

- }

82494

- intarg_count += 2;

82495

- break;

82496

-

82497

- case FFI_TYPE_STRUCT:

82498

- struct_copy_size = ((*ptr)->size + 15) & ~0xF;

82499

- copy_space.c -= struct_copy_size;

82500

- memcpy (copy_space.c, *p_argv.c, (*ptr)->size);

82501

-

82502

- gprvalue = (unsigned long) copy_space.c;

82503

-

82504

- FFI_ASSERT (copy_space.c > next_arg.c);

82505

- FFI_ASSERT (flags & FLAG_ARG_NEEDS_COPY);

82506

- goto putgpr;

82507

-

82508

- case FFI_TYPE_UINT8:

82509

- gprvalue = **p_argv.uc;

82510

- goto putgpr;

82511

- case FFI_TYPE_SINT8:

82512

- gprvalue = **p_argv.sc;

82513

- goto putgpr;

82514

- case FFI_TYPE_UINT16:

82515

- gprvalue = **p_argv.us;

82516

- goto putgpr;

82517

- case FFI_TYPE_SINT16:

82518

- gprvalue = **p_argv.ss;

82519

- goto putgpr;

82520

-

82521

- case FFI_TYPE_INT:

82522

- case FFI_TYPE_UINT32:

82523

- case FFI_TYPE_SINT32:

82524

- case FFI_TYPE_POINTER:

82525

-

82526

- gprvalue = **p_argv.ui;

82527

-

82528

- putgpr:

82529

- if (intarg_count >= NUM_GPR_ARG_REGISTERS)

82530

- *next_arg.u++ = gprvalue;

82531

- else

82532

- *gpr_base.u++ = gprvalue;

82533

- intarg_count++;

82534

- break;

82535

- }

82536

- }

82537

-

82538

- /* Check that we didn't overrun the stack... */

82539

- FFI_ASSERT (copy_space.c >= next_arg.c);

82540

- FFI_ASSERT (gpr_base.u <= stacktop.u - ASM_NEEDS_REGISTERS);

82541

-#ifndef __NO_FPRS__

82542

- FFI_ASSERT (fpr_base.u

82543

- <= stacktop.u - ASM_NEEDS_REGISTERS - NUM_GPR_ARG_REGISTERS);

82544

-#endif

82545

- FFI_ASSERT (flags & FLAG_4_GPR_ARGUMENTS || intarg_count <= 4);

82546

+# if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

82547

+# ifdef POWERPC64

82548

+ ffi_prep_types_linux64 (abi);

82549

+# else

82550

+ ffi_prep_types_sysv (abi);

82551

+# endif

82552

+# endif

82553

}

82554

-

82555

-/* About the LINUX64 ABI. */

82556

-enum {

82557

- NUM_GPR_ARG_REGISTERS64 = 8,

82558

- NUM_FPR_ARG_REGISTERS64 = 13

82559

-};

82560

-enum { ASM_NEEDS_REGISTERS64 = 4 };

82561

-

82562

-/* ffi_prep_args64 is called by the assembly routine once stack space

82563

- has been allocated for the function's arguments.

82564

-

82565

- The stack layout we want looks like this:

82566

-

82567

- | Ret addr from ffi_call_LINUX64 8bytes | higher addresses

82568

- |--------------------------------------------|

82569

- | CR save area 8bytes |

82570

- |--------------------------------------------|

82571

- | Previous backchain pointer 8 | stack pointer here

82572

- |--------------------------------------------|<+ <<< on entry to

82573

- | Saved r28-r31 4*8 | | ffi_call_LINUX64

82574

- |--------------------------------------------| |

82575

- | GPR registers r3-r10 8*8 | |

82576

- |--------------------------------------------| |

82577

- | FPR registers f1-f13 (optional) 13*8 | |

82578

- |--------------------------------------------| |

82579

- | Parameter save area | |

82580

- |--------------------------------------------| |

82581

- | TOC save area 8 | |

82582

- |--------------------------------------------| | stack |

82583

- | Linker doubleword 8 | | grows |

82584

- |--------------------------------------------| | down V

82585

- | Compiler doubleword 8 | |

82586

- |--------------------------------------------| | lower addresses

82587

- | Space for callee's LR 8 | |

82588

- |--------------------------------------------| |

82589

- | CR save area 8 | |

82590

- |--------------------------------------------| | stack pointer here

82591

- | Current backchain pointer 8 |-/ during

82592

- |--------------------------------------------| <<< ffi_call_LINUX64

82593

-

82594

-*/

82595

-

82596

-void FFI_HIDDEN

82597

-ffi_prep_args64 (extended_cif *ecif, unsigned long *const stack)

82598

-{

82599

- const unsigned long bytes = ecif->cif->bytes;

82600

- const unsigned long flags = ecif->cif->flags;

82601

-

82602

- typedef union {

82603

- char *c;

82604

- unsigned long *ul;

82605

- float *f;

82606

- double *d;

82607

- } valp;

82608

-

82609

- /* 'stacktop' points at the previous backchain pointer. */

82610

- valp stacktop;

82611

-

82612

- /* 'next_arg' points at the space for gpr3, and grows upwards as

82613

- we use GPR registers, then continues at rest. */

82614

- valp gpr_base;

82615

- valp gpr_end;

82616

- valp rest;

82617

- valp next_arg;

82618

-

82619

- /* 'fpr_base' points at the space for fpr3, and grows upwards as

82620

- we use FPR registers. */

82621

- valp fpr_base;

82622

- int fparg_count;

82623

-

82624

- int i, words;

82625

- ffi_type **ptr;

82626

- double double_tmp;

82627

- union {

82628

- void **v;

82629

- char **c;

82630

- signed char **sc;

82631

- unsigned char **uc;

82632

- signed short **ss;

82633

- unsigned short **us;

82634

- signed int **si;

82635

- unsigned int **ui;

82636

- unsigned long **ul;

82637

- float **f;

82638

- double **d;

82639

- } p_argv;

82640

- unsigned long gprvalue;

82641

-

82642

- stacktop.c = (char *) stack + bytes;

82643

- gpr_base.ul = stacktop.ul - ASM_NEEDS_REGISTERS64 - NUM_GPR_ARG_REGISTERS64;

82644

- gpr_end.ul = gpr_base.ul + NUM_GPR_ARG_REGISTERS64;

82645

- rest.ul = stack + 6 + NUM_GPR_ARG_REGISTERS64;

82646

- fpr_base.d = gpr_base.d - NUM_FPR_ARG_REGISTERS64;

82647

- fparg_count = 0;

82648

- next_arg.ul = gpr_base.ul;

82649

-

82650

- /* Check that everything starts aligned properly. */

82651

- FFI_ASSERT (((unsigned long) (char *) stack & 0xF) == 0);

82652

- FFI_ASSERT (((unsigned long) stacktop.c & 0xF) == 0);

82653

- FFI_ASSERT ((bytes & 0xF) == 0);

82654

-

82655

- /* Deal with return values that are actually pass-by-reference. */

82656

- if (flags & FLAG_RETVAL_REFERENCE)

82657

- *next_arg.ul++ = (unsigned long) (char *) ecif->rvalue;

82658

-

82659

- /* Now for the arguments. */

82660

- p_argv.v = ecif->avalue;

82661

- for (ptr = ecif->cif->arg_types, i = ecif->cif->nargs;

82662

- i > 0;

82663

- i--, ptr++, p_argv.v++)

82664

- {

82665

- switch ((*ptr)->type)

82666

- {

82667

- case FFI_TYPE_FLOAT:

82668

- double_tmp = **p_argv.f;

82669

- *next_arg.f = (float) double_tmp;

82670

- if (++next_arg.ul == gpr_end.ul)

82671

- next_arg.ul = rest.ul;

82672

- if (fparg_count < NUM_FPR_ARG_REGISTERS64)

82673

- *fpr_base.d++ = double_tmp;

82674

- fparg_count++;

82675

- FFI_ASSERT (flags & FLAG_FP_ARGUMENTS);

82676

- break;

82677

-

82678

- case FFI_TYPE_DOUBLE:

82679

- double_tmp = **p_argv.d;

82680

- *next_arg.d = double_tmp;

82681

- if (++next_arg.ul == gpr_end.ul)

82682

- next_arg.ul = rest.ul;

82683

- if (fparg_count < NUM_FPR_ARG_REGISTERS64)

82684

- *fpr_base.d++ = double_tmp;

82685

- fparg_count++;

82686

- FFI_ASSERT (flags & FLAG_FP_ARGUMENTS);

82687

- break;

82688

-

82689

-#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

82690

- case FFI_TYPE_LONGDOUBLE:

82691

- double_tmp = (*p_argv.d)[0];

82692

- *next_arg.d = double_tmp;

82693

- if (++next_arg.ul == gpr_end.ul)

82694

- next_arg.ul = rest.ul;

82695

- if (fparg_count < NUM_FPR_ARG_REGISTERS64)

82696

- *fpr_base.d++ = double_tmp;

82697

- fparg_count++;

82698

- double_tmp = (*p_argv.d)[1];

82699

- *next_arg.d = double_tmp;

82700

- if (++next_arg.ul == gpr_end.ul)

82701

- next_arg.ul = rest.ul;

82702

- if (fparg_count < NUM_FPR_ARG_REGISTERS64)

82703

- *fpr_base.d++ = double_tmp;

82704

- fparg_count++;

82705

- FFI_ASSERT (__LDBL_MANT_DIG__ == 106);

82706

- FFI_ASSERT (flags & FLAG_FP_ARGUMENTS);

82707

- break;

82708

#endif

82709

82710

- case FFI_TYPE_STRUCT:

82711

- words = ((*ptr)->size + 7) / 8;

82712

- if (next_arg.ul >= gpr_base.ul && next_arg.ul + words > gpr_end.ul)

82713

- {

82714

- size_t first = gpr_end.c - next_arg.c;

82715

- memcpy (next_arg.c, *p_argv.c, first);

82716

- memcpy (rest.c, *p_argv.c + first, (*ptr)->size - first);

82717

- next_arg.c = rest.c + words * 8 - first;

82718

- }

82719

- else

82720

- {

82721

- char *where = next_arg.c;

82722

-

82723

-#ifndef __LITTLE_ENDIAN__

82724

- /* Structures with size less than eight bytes are passed

82725

- left-padded. */

82726

- if ((*ptr)->size < 8)

82727

- where += 8 - (*ptr)->size;

82728

-#endif

82729

- memcpy (where, *p_argv.c, (*ptr)->size);

82730

- next_arg.ul += words;

82731

- if (next_arg.ul == gpr_end.ul)

82732

- next_arg.ul = rest.ul;

82733

- }

82734

- break;

82735

-

82736

- case FFI_TYPE_UINT8:

82737

- gprvalue = **p_argv.uc;

82738

- goto putgpr;

82739

- case FFI_TYPE_SINT8:

82740

- gprvalue = **p_argv.sc;

82741

- goto putgpr;

82742

- case FFI_TYPE_UINT16:

82743

- gprvalue = **p_argv.us;

82744

- goto putgpr;

82745

- case FFI_TYPE_SINT16:

82746

- gprvalue = **p_argv.ss;

82747

- goto putgpr;

82748

- case FFI_TYPE_UINT32:

82749

- gprvalue = **p_argv.ui;

82750

- goto putgpr;

82751

- case FFI_TYPE_INT:

82752

- case FFI_TYPE_SINT32:

82753

- gprvalue = **p_argv.si;

82754

- goto putgpr;

82755

-

82756

- case FFI_TYPE_UINT64:

82757

- case FFI_TYPE_SINT64:

82758

- case FFI_TYPE_POINTER:

82759

- gprvalue = **p_argv.ul;

82760

- putgpr:

82761

- *next_arg.ul++ = gprvalue;

82762

- if (next_arg.ul == gpr_end.ul)

82763

- next_arg.ul = rest.ul;

82764

- break;

82765

- }

82766

- }

82767

-

82768

- FFI_ASSERT (flags & FLAG_4_GPR_ARGUMENTS

82769

- || (next_arg.ul >= gpr_base.ul

82770

- && next_arg.ul <= gpr_base.ul + 4));

82771

-}

82772

-

82773

-

82774

-

82775

/* Perform machine dependent cif processing */

82776

-ffi_status

82777

+ffi_status FFI_HIDDEN

82778

ffi_prep_cif_machdep (ffi_cif *cif)

82779

{

82780

- /* All this is for the SYSV and LINUX64 ABI. */

82781

- int i;

82782

- ffi_type **ptr;

82783

- unsigned bytes;

82784

- int fparg_count = 0, intarg_count = 0;

82785

- unsigned flags = 0;

82786

- unsigned struct_copy_size = 0;

82787

- unsigned type = cif->rtype->type;

82788

- unsigned size = cif->rtype->size;

82789

-

82790

- if (cif->abi != FFI_LINUX64)

82791

- {

82792

- /* All the machine-independent calculation of cif->bytes will be wrong.

82793

- Redo the calculation for SYSV. */

82794

-

82795

- /* Space for the frame pointer, callee's LR, and the asm's temp regs. */

82796

- bytes = (2 + ASM_NEEDS_REGISTERS) * sizeof (int);

82797

-

82798

- /* Space for the GPR registers. */

82799

- bytes += NUM_GPR_ARG_REGISTERS * sizeof (int);

82800

- }

82801

- else

82802

- {

82803

- /* 64-bit ABI. */

82804

-

82805

- /* Space for backchain, CR, LR, cc/ld doubleword, TOC and the asm's temp

82806

- regs. */

82807

- bytes = (6 + ASM_NEEDS_REGISTERS64) * sizeof (long);

82808

-

82809

- /* Space for the mandatory parm save area and general registers. */

82810

- bytes += 2 * NUM_GPR_ARG_REGISTERS64 * sizeof (long);

82811

- }

82812

-

82813

- /* Return value handling. The rules for SYSV are as follows:

82814

- - 32-bit (or less) integer values are returned in gpr3;

82815

- - Structures of size <= 4 bytes also returned in gpr3;

82816

- - 64-bit integer values and structures between 5 and 8 bytes are returned

82817

- in gpr3 and gpr4;

82818

- - Single/double FP values are returned in fpr1;

82819

- - Larger structures are allocated space and a pointer is passed as

82820

- the first argument.

82821

- - long doubles (if not equivalent to double) are returned in

82822

- fpr1,fpr2 for Linux and as for large structs for SysV.

82823

- For LINUX64:

82824

- - integer values in gpr3;

82825

- - Structures/Unions by reference;

82826

- - Single/double FP values in fpr1, long double in fpr1,fpr2.

82827

- - soft-float float/doubles are treated as UINT32/UINT64 respectivley.

82828

- - soft-float long doubles are returned in gpr3-gpr6. */

82829

- /* First translate for softfloat/nonlinux */

82830

- if (cif->abi == FFI_LINUX_SOFT_FLOAT) {

82831

- if (type == FFI_TYPE_FLOAT)

82832

- type = FFI_TYPE_UINT32;

82833

- if (type == FFI_TYPE_DOUBLE)

82834

- type = FFI_TYPE_UINT64;

82835

- if (type == FFI_TYPE_LONGDOUBLE)

82836

- type = FFI_TYPE_UINT128;

82837

- } else if (cif->abi != FFI_LINUX && cif->abi != FFI_LINUX64) {

82838

-#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

82839

- if (type == FFI_TYPE_LONGDOUBLE)

82840

- type = FFI_TYPE_STRUCT;

82841

+#ifdef POWERPC64

82842

+ return ffi_prep_cif_linux64 (cif);

82843

+#else

82844

+ return ffi_prep_cif_sysv (cif);

82845

#endif

82846

- }

82847

+}

82848

82849

- switch (type)

82850

- {

82851

-#ifndef __NO_FPRS__

82852

-#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

82853

- case FFI_TYPE_LONGDOUBLE:

82854

- flags |= FLAG_RETURNS_128BITS;

82855

- /* Fall through. */

82856

+ffi_status FFI_HIDDEN

82857

+ffi_prep_cif_machdep_var (ffi_cif *cif,

82858

+ unsigned int nfixedargs MAYBE_UNUSED,

82859

+ unsigned int ntotalargs MAYBE_UNUSED)

82860

+{

82861

+#ifdef POWERPC64

82862

+ return ffi_prep_cif_linux64_var (cif, nfixedargs, ntotalargs);

82863

+#else

82864

+ return ffi_prep_cif_sysv (cif);

82865

#endif

82866

- case FFI_TYPE_DOUBLE:

82867

- flags |= FLAG_RETURNS_64BITS;

82868

- /* Fall through. */

82869

- case FFI_TYPE_FLOAT:

82870

- flags |= FLAG_RETURNS_FP;

82871

- break;

82872

-#endif

82873

-

82874

- case FFI_TYPE_UINT128:

82875

- flags |= FLAG_RETURNS_128BITS;

82876

- /* Fall through. */

82877

- case FFI_TYPE_UINT64:

82878

- case FFI_TYPE_SINT64:

82879

- flags |= FLAG_RETURNS_64BITS;

82880

- break;

82881

-

82882

- case FFI_TYPE_STRUCT:

82883

- /*

82884

- * The final SYSV ABI says that structures smaller or equal 8 bytes

82885

- * are returned in r3/r4. The FFI_GCC_SYSV ABI instead returns them

82886

- * in memory.

82887

- *

82888

- * NOTE: The assembly code can safely assume that it just needs to

82889

- * store both r3 and r4 into a 8-byte word-aligned buffer, as

82890

- * we allocate a temporary buffer in ffi_call() if this flag is

82891

- * set.

82892

- */

82893

- if (cif->abi == FFI_SYSV && size <= 8)

82894

- flags |= FLAG_RETURNS_SMST;

82895

- intarg_count++;

82896

- flags |= FLAG_RETVAL_REFERENCE;

82897

- /* Fall through. */

82898

- case FFI_TYPE_VOID:

82899

- flags |= FLAG_RETURNS_NOTHING;

82900

- break;

82901

-

82902

- default:

82903

- /* Returns 32-bit integer, or similar. Nothing to do here. */

82904

- break;

82905

- }

82906

-

82907

- if (cif->abi != FFI_LINUX64)

82908

- /* The first NUM_GPR_ARG_REGISTERS words of integer arguments, and the

82909

- first NUM_FPR_ARG_REGISTERS fp arguments, go in registers; the rest

82910

- goes on the stack. Structures and long doubles (if not equivalent

82911

- to double) are passed as a pointer to a copy of the structure.

82912

- Stuff on the stack needs to keep proper alignment. */

82913

- for (ptr = cif->arg_types, i = cif->nargs; i > 0; i--, ptr++)

82914

- {

82915

- unsigned short typenum = (*ptr)->type;

82916

-

82917

- /* We may need to handle some values depending on ABI */

82918

- if (cif->abi == FFI_LINUX_SOFT_FLOAT) {

82919

- if (typenum == FFI_TYPE_FLOAT)

82920

- typenum = FFI_TYPE_UINT32;

82921

- if (typenum == FFI_TYPE_DOUBLE)

82922

- typenum = FFI_TYPE_UINT64;

82923

- if (typenum == FFI_TYPE_LONGDOUBLE)

82924

- typenum = FFI_TYPE_UINT128;

82925

- } else if (cif->abi != FFI_LINUX && cif->abi != FFI_LINUX64) {

82926

-#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

82927

- if (typenum == FFI_TYPE_LONGDOUBLE)

82928

- typenum = FFI_TYPE_STRUCT;

82929

-#endif

82930

- }

82931

-

82932

- switch (typenum) {

82933

-#ifndef __NO_FPRS__

82934

- case FFI_TYPE_FLOAT:

82935

- fparg_count++;

82936

- /* floating singles are not 8-aligned on stack */

82937

- break;

82938

-

82939

-#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

82940

- case FFI_TYPE_LONGDOUBLE:

82941

- fparg_count++;

82942

- /* Fall thru */

82943

-#endif

82944

- case FFI_TYPE_DOUBLE:

82945

- fparg_count++;

82946

- /* If this FP arg is going on the stack, it must be

82947

- 8-byte-aligned. */

82948

- if (fparg_count > NUM_FPR_ARG_REGISTERS

82949

- && intarg_count >= NUM_GPR_ARG_REGISTERS

82950

- && intarg_count % 2 != 0)

82951

- intarg_count++;

82952

- break;

82953

-#endif

82954

- case FFI_TYPE_UINT128:

82955

- /*

82956

- * A long double in FFI_LINUX_SOFT_FLOAT can use only a set

82957

- * of four consecutive gprs. If we do not have enough, we

82958

- * have to adjust the intarg_count value.

82959

- */

82960

- if (intarg_count >= NUM_GPR_ARG_REGISTERS - 3

82961

- && intarg_count < NUM_GPR_ARG_REGISTERS)

82962

- intarg_count = NUM_GPR_ARG_REGISTERS;

82963

- intarg_count += 4;

82964

- break;

82965

-

82966

- case FFI_TYPE_UINT64:

82967

- case FFI_TYPE_SINT64:

82968

- /* 'long long' arguments are passed as two words, but

82969

- either both words must fit in registers or both go

82970

- on the stack. If they go on the stack, they must

82971

- be 8-byte-aligned.

82972

-

82973

- Also, only certain register pairs can be used for

82974

- passing long long int -- specifically (r3,r4), (r5,r6),

82975

- (r7,r8), (r9,r10).

82976

- */

82977

- if (intarg_count == NUM_GPR_ARG_REGISTERS-1

82978

- || intarg_count % 2 != 0)

82979

- intarg_count++;

82980

- intarg_count += 2;

82981

- break;

82982

-

82983

- case FFI_TYPE_STRUCT:

82984

- /* We must allocate space for a copy of these to enforce

82985

- pass-by-value. Pad the space up to a multiple of 16

82986

- bytes (the maximum alignment required for anything under

82987

- the SYSV ABI). */

82988

- struct_copy_size += ((*ptr)->size + 15) & ~0xF;

82989

- /* Fall through (allocate space for the pointer). */

82990

-

82991

- case FFI_TYPE_POINTER:

82992

- case FFI_TYPE_INT:

82993

- case FFI_TYPE_UINT32:

82994

- case FFI_TYPE_SINT32:

82995

- case FFI_TYPE_UINT16:

82996

- case FFI_TYPE_SINT16:

82997

- case FFI_TYPE_UINT8:

82998

- case FFI_TYPE_SINT8:

82999

- /* Everything else is passed as a 4-byte word in a GPR, either

83000

- the object itself or a pointer to it. */

83001

- intarg_count++;

83002

- break;

83003

- default:

83004

- FFI_ASSERT (0);

83005

- }

83006

- }

83007

- else

83008

- for (ptr = cif->arg_types, i = cif->nargs; i > 0; i--, ptr++)

83009

- {

83010

- switch ((*ptr)->type)

83011

- {

83012

-#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

83013

- case FFI_TYPE_LONGDOUBLE:

83014

- if (cif->abi == FFI_LINUX_SOFT_FLOAT)

83015

- intarg_count += 4;

83016

- else

83017

- {

83018

- fparg_count += 2;

83019

- intarg_count += 2;

83020

- }

83021

- break;

83022

-#endif

83023

- case FFI_TYPE_FLOAT:

83024

- case FFI_TYPE_DOUBLE:

83025

- fparg_count++;

83026

- intarg_count++;

83027

- break;

83028

-

83029

- case FFI_TYPE_STRUCT:

83030

- intarg_count += ((*ptr)->size + 7) / 8;

83031

- break;

83032

-

83033

- case FFI_TYPE_POINTER:

83034

- case FFI_TYPE_UINT64:

83035

- case FFI_TYPE_SINT64:

83036

- case FFI_TYPE_INT:

83037

- case FFI_TYPE_UINT32:

83038

- case FFI_TYPE_SINT32:

83039

- case FFI_TYPE_UINT16:

83040

- case FFI_TYPE_SINT16:

83041

- case FFI_TYPE_UINT8:

83042

- case FFI_TYPE_SINT8:

83043

- /* Everything else is passed as a 8-byte word in a GPR, either

83044

- the object itself or a pointer to it. */

83045

- intarg_count++;

83046

- break;

83047

- default:

83048

- FFI_ASSERT (0);

83049

- }

83050

- }

83051

-

83052

-#ifndef __NO_FPRS__

83053

- if (fparg_count != 0)

83054

- flags |= FLAG_FP_ARGUMENTS;

83055

-#endif

83056

- if (intarg_count > 4)

83057

- flags |= FLAG_4_GPR_ARGUMENTS;

83058

- if (struct_copy_size != 0)

83059

- flags |= FLAG_ARG_NEEDS_COPY;

83060

-

83061

- if (cif->abi != FFI_LINUX64)

83062

- {

83063

-#ifndef __NO_FPRS__

83064

- /* Space for the FPR registers, if needed. */

83065

- if (fparg_count != 0)

83066

- bytes += NUM_FPR_ARG_REGISTERS * sizeof (double);

83067

-#endif

83068

-

83069

- /* Stack space. */

83070

- if (intarg_count > NUM_GPR_ARG_REGISTERS)

83071

- bytes += (intarg_count - NUM_GPR_ARG_REGISTERS) * sizeof (int);

83072

-#ifndef __NO_FPRS__

83073

- if (fparg_count > NUM_FPR_ARG_REGISTERS)

83074

- bytes += (fparg_count - NUM_FPR_ARG_REGISTERS) * sizeof (double);

83075

-#endif

83076

- }

83077

- else

83078

- {

83079

-#ifndef __NO_FPRS__

83080

- /* Space for the FPR registers, if needed. */

83081

- if (fparg_count != 0)

83082

- bytes += NUM_FPR_ARG_REGISTERS64 * sizeof (double);

83083

-#endif

83084

-

83085

- /* Stack space. */

83086

- if (intarg_count > NUM_GPR_ARG_REGISTERS64)

83087

- bytes += (intarg_count - NUM_GPR_ARG_REGISTERS64) * sizeof (long);

83088

- }

83089

-

83090

- /* The stack space allocated needs to be a multiple of 16 bytes. */

83091

- bytes = (bytes + 15) & ~0xF;

83092

-

83093

- /* Add in the space for the copied structures. */

83094

- bytes += struct_copy_size;

83095

-

83096

- cif->flags = flags;

83097

- cif->bytes = bytes;

83098

-

83099

- return FFI_OK;

83100

}

83101

83102

-extern void ffi_call_SYSV(extended_cif *, unsigned, unsigned, unsigned *,

83103

- void (*fn)(void));

83104

-extern void FFI_HIDDEN ffi_call_LINUX64(extended_cif *, unsigned long,

83105

- unsigned long, unsigned long *,

83106

- void (*fn)(void));

83107

-

83108

void

83109

ffi_call(ffi_cif *cif, void (*fn)(void), void *rvalue, void **avalue)

83110

{

83111

- /*

83112

- * The final SYSV ABI says that structures smaller or equal 8 bytes

83113

- * are returned in r3/r4. The FFI_GCC_SYSV ABI instead returns them

83114

- * in memory.

83115

- *

83116

- * Just to keep things simple for the assembly code, we will always

83117

- * bounce-buffer struct return values less than or equal to 8 bytes.

83118

- * This allows the ASM to handle SYSV small structures by directly

83119

- * writing r3 and r4 to memory without worrying about struct size.

83120

- */

83121

- unsigned int smst_buffer[2];

83122

+ /* The final SYSV ABI says that structures smaller or equal 8 bytes

83123

+ are returned in r3/r4. A draft ABI used by linux instead returns

83124

+ them in memory.

83125

+

83126

+ We bounce-buffer SYSV small struct return values so that sysv.S

83127

+ can write r3 and r4 to memory without worrying about struct size.

83128

+

83129

+ For ELFv2 ABI, use a bounce buffer for homogeneous structs too,

83130

+ for similar reasons. */

83131

+ unsigned long smst_buffer[8];

83132

extended_cif ecif;

83133

- unsigned int rsize = 0;

83134

83135

ecif.cif = cif;

83136

ecif.avalue = avalue;

83137

83138

- /* Ensure that we have a valid struct return value */

83139

ecif.rvalue = rvalue;

83140

- if (cif->rtype->type == FFI_TYPE_STRUCT) {

83141

- rsize = cif->rtype->size;

83142

- if (rsize <= 8)

83143

- ecif.rvalue = smst_buffer;

83144

- else if (!rvalue)

83145

- ecif.rvalue = alloca(rsize);

83146

- }

83147

+ if ((cif->flags & FLAG_RETURNS_SMST) != 0)

83148

+ ecif.rvalue = smst_buffer;

83149

+ /* Ensure that we have a valid struct return value.

83150

+ FIXME: Isn't this just papering over a user problem? */

83151

+ else if (!rvalue && cif->rtype->type == FFI_TYPE_STRUCT)

83152

+ ecif.rvalue = alloca (cif->rtype->size);

83153

83154

- switch (cif->abi)

83155

- {

83156

-#ifndef POWERPC64

83157

-# ifndef __NO_FPRS__

83158

- case FFI_SYSV:

83159

- case FFI_GCC_SYSV:

83160

- case FFI_LINUX:

83161

-# endif

83162

- case FFI_LINUX_SOFT_FLOAT:

83163

- ffi_call_SYSV (&ecif, -cif->bytes, cif->flags, ecif.rvalue, fn);

83164

- break;

83165

+#ifdef POWERPC64

83166

+ ffi_call_LINUX64 (&ecif, -(long) cif->bytes, cif->flags, ecif.rvalue, fn);

83167

#else

83168

- case FFI_LINUX64:

83169

- ffi_call_LINUX64 (&ecif, -(long) cif->bytes, cif->flags, ecif.rvalue, fn);

83170

- break;

83171

+ ffi_call_SYSV (&ecif, -cif->bytes, cif->flags, ecif.rvalue, fn);

83172

#endif

83173

- default:

83174

- FFI_ASSERT (0);

83175

- break;

83176

- }

83177

83178

/* Check for a bounce-buffered return value */

83179

if (rvalue && ecif.rvalue == smst_buffer)

83180

- memcpy(rvalue, smst_buffer, rsize);

83181

+ {

83182

+ unsigned int rsize = cif->rtype->size;

83183

+#ifndef __LITTLE_ENDIAN__

83184

+ /* The SYSV ABI returns a structure of up to 4 bytes in size

83185

+ left-padded in r3. */

83186

+# ifndef POWERPC64

83187

+ if (rsize <= 4)

83188

+ memcpy (rvalue, (char *) smst_buffer + 4 - rsize, rsize);

83189

+ else

83190

+# endif

83191

+ /* The SYSV ABI returns a structure of up to 8 bytes in size

83192

+ left-padded in r3/r4, and the ELFv2 ABI similarly returns a

83193

+ structure of up to 8 bytes in size left-padded in r3. */

83194

+ if (rsize <= 8)

83195

+ memcpy (rvalue, (char *) smst_buffer + 8 - rsize, rsize);

83196

+ else

83197

+#endif

83198

+ memcpy (rvalue, smst_buffer, rsize);

83199

+ }

83200

}

83201

83202

83203

-#ifndef POWERPC64

83204

-#define MIN_CACHE_LINE_SIZE 8

83205

-

83206

-static void

83207

-flush_icache (char *wraddr, char *xaddr, int size)

83208

-{

83209

- int i;

83210

- for (i = 0; i < size; i += MIN_CACHE_LINE_SIZE)

83211

- __asm__ volatile ("icbi 0,%0;" "dcbf 0,%1;"

83212

- : : "r" (xaddr + i), "r" (wraddr + i) : "memory");

83213

- __asm__ volatile ("icbi 0,%0;" "dcbf 0,%1;" "sync;" "isync;"

83214

- : : "r"(xaddr + size - 1), "r"(wraddr + size - 1)

83215

- : "memory");

83216

-}

83217

-#endif

83218

-

83219

ffi_status

83220

ffi_prep_closure_loc (ffi_closure *closure,

83221

ffi_cif *cif,

83222

@@ -995,487 +134,8 @@

83223

void *codeloc)

83224

{

83225

#ifdef POWERPC64

83226

- void **tramp = (void **) &closure->tramp[0];

83227

-

83228

- if (cif->abi != FFI_LINUX64)

83229

- return FFI_BAD_ABI;

83230

- /* Copy function address and TOC from ffi_closure_LINUX64. */

83231

- memcpy (tramp, (char *) ffi_closure_LINUX64, 16);

83232

- tramp[2] = codeloc;

83233

+ return ffi_prep_closure_loc_linux64 (closure, cif, fun, user_data, codeloc);

83234

#else

83235

- unsigned int *tramp;

83236

-

83237

- if (! (cif->abi == FFI_GCC_SYSV

83238

- || cif->abi == FFI_SYSV

83239

- || cif->abi == FFI_LINUX

83240

- || cif->abi == FFI_LINUX_SOFT_FLOAT))

83241

- return FFI_BAD_ABI;

83242

-

83243

- tramp = (unsigned int *) &closure->tramp[0];

83244

- tramp[0] = 0x7c0802a6; /* mflr r0 */

83245

- tramp[1] = 0x4800000d; /* bl 10 <trampoline_initial+0x10> */

83246

- tramp[4] = 0x7d6802a6; /* mflr r11 */

83247

- tramp[5] = 0x7c0803a6; /* mtlr r0 */

83248

- tramp[6] = 0x800b0000; /* lwz r0,0(r11) */

83249

- tramp[7] = 0x816b0004; /* lwz r11,4(r11) */

83250

- tramp[8] = 0x7c0903a6; /* mtctr r0 */

83251

- tramp[9] = 0x4e800420; /* bctr */

83252

- *(void **) &tramp[2] = (void *) ffi_closure_SYSV; /* function */

83253

- *(void **) &tramp[3] = codeloc; /* context */

83254

-

83255

- /* Flush the icache. */

83256

- flush_icache ((char *)tramp, (char *)codeloc, FFI_TRAMPOLINE_SIZE);

83257

+ return ffi_prep_closure_loc_sysv (closure, cif, fun, user_data, codeloc);

83258

#endif

83259

-

83260

- closure->cif = cif;

83261

- closure->fun = fun;

83262

- closure->user_data = user_data;

83263

-

83264

- return FFI_OK;

83265

}

83266

-

83267

-typedef union

83268

-{

83269

- float f;

83270

- double d;

83271

-} ffi_dblfl;

83272

-

83273

-int ffi_closure_helper_SYSV (ffi_closure *, void *, unsigned long *,

83274

- ffi_dblfl *, unsigned long *);

83275

-

83276

-/* Basically the trampoline invokes ffi_closure_SYSV, and on

83277

- * entry, r11 holds the address of the closure.

83278

- * After storing the registers that could possibly contain

83279

- * parameters to be passed into the stack frame and setting

83280

- * up space for a return value, ffi_closure_SYSV invokes the

83281

- * following helper function to do most of the work

83282

- */

83283

-

83284

-int

83285

-ffi_closure_helper_SYSV (ffi_closure *closure, void *rvalue,

83286

- unsigned long *pgr, ffi_dblfl *pfr,

83287

- unsigned long *pst)

83288

-{

83289

- /* rvalue is the pointer to space for return value in closure assembly */

83290

- /* pgr is the pointer to where r3-r10 are stored in ffi_closure_SYSV */

83291

- /* pfr is the pointer to where f1-f8 are stored in ffi_closure_SYSV */

83292

- /* pst is the pointer to outgoing parameter stack in original caller */

83293

-

83294

- void ** avalue;

83295

- ffi_type ** arg_types;

83296

- long i, avn;

83297

-#ifndef __NO_FPRS__

83298

- long nf = 0; /* number of floating registers already used */

83299

-#endif

83300

- long ng = 0; /* number of general registers already used */

83301

-

83302

- ffi_cif *cif = closure->cif;

83303

- unsigned size = cif->rtype->size;

83304

- unsigned short rtypenum = cif->rtype->type;

83305

-

83306

- avalue = alloca (cif->nargs * sizeof (void *));

83307

-

83308

- /* First translate for softfloat/nonlinux */

83309

- if (cif->abi == FFI_LINUX_SOFT_FLOAT) {

83310

- if (rtypenum == FFI_TYPE_FLOAT)

83311

- rtypenum = FFI_TYPE_UINT32;

83312

- if (rtypenum == FFI_TYPE_DOUBLE)

83313

- rtypenum = FFI_TYPE_UINT64;

83314

- if (rtypenum == FFI_TYPE_LONGDOUBLE)

83315

- rtypenum = FFI_TYPE_UINT128;

83316

- } else if (cif->abi != FFI_LINUX && cif->abi != FFI_LINUX64) {

83317

-#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

83318

- if (rtypenum == FFI_TYPE_LONGDOUBLE)

83319

- rtypenum = FFI_TYPE_STRUCT;

83320

-#endif

83321

- }

83322

-

83323

-

83324

- /* Copy the caller's structure return value address so that the closure

83325

- returns the data directly to the caller.

83326

- For FFI_SYSV the result is passed in r3/r4 if the struct size is less

83327

- or equal 8 bytes. */

83328

- if (rtypenum == FFI_TYPE_STRUCT && ((cif->abi != FFI_SYSV) || (size > 8))) {

83329

- rvalue = (void *) *pgr;

83330

- ng++;

83331

- pgr++;

83332

- }

83333

-

83334

- i = 0;

83335

- avn = cif->nargs;

83336

- arg_types = cif->arg_types;

83337

-

83338

- /* Grab the addresses of the arguments from the stack frame. */

83339

- while (i < avn) {

83340

- unsigned short typenum = arg_types[i]->type;

83341

-

83342

- /* We may need to handle some values depending on ABI */

83343

- if (cif->abi == FFI_LINUX_SOFT_FLOAT) {

83344

- if (typenum == FFI_TYPE_FLOAT)

83345

- typenum = FFI_TYPE_UINT32;

83346

- if (typenum == FFI_TYPE_DOUBLE)

83347

- typenum = FFI_TYPE_UINT64;

83348

- if (typenum == FFI_TYPE_LONGDOUBLE)

83349

- typenum = FFI_TYPE_UINT128;

83350

- } else if (cif->abi != FFI_LINUX && cif->abi != FFI_LINUX64) {

83351

-#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

83352

- if (typenum == FFI_TYPE_LONGDOUBLE)

83353

- typenum = FFI_TYPE_STRUCT;

83354

-#endif

83355

- }

83356

-

83357

- switch (typenum) {

83358

-#ifndef __NO_FPRS__

83359

- case FFI_TYPE_FLOAT:

83360

- /* unfortunately float values are stored as doubles

83361

- * in the ffi_closure_SYSV code (since we don't check

83362

- * the type in that routine).

83363

- */

83364

-

83365

- /* there are 8 64bit floating point registers */

83366

-

83367

- if (nf < 8)

83368

- {

83369

- double temp = pfr->d;

83370

- pfr->f = (float) temp;

83371

- avalue[i] = pfr;

83372

- nf++;

83373

- pfr++;

83374

- }

83375

- else

83376

- {

83377

- /* FIXME? here we are really changing the values

83378

- * stored in the original calling routines outgoing

83379

- * parameter stack. This is probably a really

83380

- * naughty thing to do but...

83381

- */

83382

- avalue[i] = pst;

83383

- pst += 1;

83384

- }

83385

- break;

83386

-

83387

- case FFI_TYPE_DOUBLE:

83388

- /* On the outgoing stack all values are aligned to 8 */

83389

- /* there are 8 64bit floating point registers */

83390

-

83391

- if (nf < 8)

83392

- {

83393

- avalue[i] = pfr;

83394

- nf++;

83395

- pfr++;

83396

- }

83397

- else

83398

- {

83399

- if (((long) pst) & 4)

83400

- pst++;

83401

- avalue[i] = pst;

83402

- pst += 2;

83403

- }

83404

- break;

83405

-

83406

-#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

83407

- case FFI_TYPE_LONGDOUBLE:

83408

- if (nf < 7)

83409

- {

83410

- avalue[i] = pfr;

83411

- pfr += 2;

83412

- nf += 2;

83413

- }

83414

- else

83415

- {

83416

- if (((long) pst) & 4)

83417

- pst++;

83418

- avalue[i] = pst;

83419

- pst += 4;

83420

- nf = 8;

83421

- }

83422

- break;

83423

-#endif

83424

-#endif /* have FPRS */

83425

-

83426

- case FFI_TYPE_UINT128:

83427

- /*

83428

- * Test if for the whole long double, 4 gprs are available.

83429

- * otherwise the stuff ends up on the stack.

83430

- */

83431

- if (ng < 5) {

83432

- avalue[i] = pgr;

83433

- pgr += 4;

83434

- ng += 4;

83435

- } else {

83436

- avalue[i] = pst;

83437

- pst += 4;

83438

- ng = 8+4;

83439

- }

83440

- break;

83441

-

83442

- case FFI_TYPE_SINT8:

83443

- case FFI_TYPE_UINT8:

83444

-#ifndef __LITTLE_ENDIAN__

83445

- /* there are 8 gpr registers used to pass values */

83446

- if (ng < 8)

83447

- {

83448

- avalue[i] = (char *) pgr + 3;

83449

- ng++;

83450

- pgr++;

83451

- }

83452

- else

83453

- {

83454

- avalue[i] = (char *) pst + 3;

83455

- pst++;

83456

- }

83457

- break;

83458

-#endif

83459

- case FFI_TYPE_SINT16:

83460

- case FFI_TYPE_UINT16:

83461

-#ifndef __LITTLE_ENDIAN__

83462

- /* there are 8 gpr registers used to pass values */

83463

- if (ng < 8)

83464

- {

83465

- avalue[i] = (char *) pgr + 2;

83466

- ng++;

83467

- pgr++;

83468

- }

83469

- else

83470

- {

83471

- avalue[i] = (char *) pst + 2;

83472

- pst++;

83473

- }

83474

- break;

83475

-#endif

83476

- case FFI_TYPE_SINT32:

83477

- case FFI_TYPE_UINT32:

83478

- case FFI_TYPE_POINTER:

83479

- /* there are 8 gpr registers used to pass values */

83480

- if (ng < 8)

83481

- {

83482

- avalue[i] = pgr;

83483

- ng++;

83484

- pgr++;

83485

- }

83486

- else

83487

- {

83488

- avalue[i] = pst;

83489

- pst++;

83490

- }

83491

- break;

83492

-

83493

- case FFI_TYPE_STRUCT:

83494

- /* Structs are passed by reference. The address will appear in a

83495

- gpr if it is one of the first 8 arguments. */

83496

- if (ng < 8)

83497

- {

83498

- avalue[i] = (void *) *pgr;

83499

- ng++;

83500

- pgr++;

83501

- }

83502

- else

83503

- {

83504

- avalue[i] = (void *) *pst;

83505

- pst++;

83506

- }

83507

- break;

83508

-

83509

- case FFI_TYPE_SINT64:

83510

- case FFI_TYPE_UINT64:

83511

- /* passing long long ints are complex, they must

83512

- * be passed in suitable register pairs such as

83513

- * (r3,r4) or (r5,r6) or (r6,r7), or (r7,r8) or (r9,r10)

83514

- * and if the entire pair aren't available then the outgoing

83515

- * parameter stack is used for both but an alignment of 8

83516

- * must will be kept. So we must either look in pgr

83517

- * or pst to find the correct address for this type

83518

- * of parameter.

83519

- */

83520

- if (ng < 7)

83521

- {

83522

- if (ng & 0x01)

83523

- {

83524

- /* skip r4, r6, r8 as starting points */

83525

- ng++;

83526

- pgr++;

83527

- }

83528

- avalue[i] = pgr;

83529

- ng += 2;

83530

- pgr += 2;

83531

- }

83532

- else

83533

- {

83534

- if (((long) pst) & 4)

83535

- pst++;

83536

- avalue[i] = pst;

83537

- pst += 2;

83538

- ng = 8;

83539

- }

83540

- break;

83541

-

83542

- default:

83543

- FFI_ASSERT (0);

83544

- }

83545

-

83546

- i++;

83547

- }

83548

-

83549

-

83550

- (closure->fun) (cif, rvalue, avalue, closure->user_data);

83551

-

83552

- /* Tell ffi_closure_SYSV how to perform return type promotions.

83553

- Because the FFI_SYSV ABI returns the structures <= 8 bytes in r3/r4

83554

- we have to tell ffi_closure_SYSV how to treat them. We combine the base

83555

- type FFI_SYSV_TYPE_SMALL_STRUCT - 1 with the size of the struct.

83556

- So a one byte struct gets the return type 16. Return type 1 to 15 are

83557

- already used and we never have a struct with size zero. That is the reason

83558

- for the subtraction of 1. See the comment in ffitarget.h about ordering.

83559

- */

83560

- if (cif->abi == FFI_SYSV && rtypenum == FFI_TYPE_STRUCT && size <= 8)

83561

- return (FFI_SYSV_TYPE_SMALL_STRUCT - 1) + size;

83562

- return rtypenum;

83563

-}

83564

-

83565

-int FFI_HIDDEN ffi_closure_helper_LINUX64 (ffi_closure *, void *,

83566

- unsigned long *, ffi_dblfl *);

83567

-

83568

-int FFI_HIDDEN

83569

-ffi_closure_helper_LINUX64 (ffi_closure *closure, void *rvalue,

83570

- unsigned long *pst, ffi_dblfl *pfr)

83571

-{

83572

- /* rvalue is the pointer to space for return value in closure assembly */

83573

- /* pst is the pointer to parameter save area

83574

- (r3-r10 are stored into its first 8 slots by ffi_closure_LINUX64) */

83575

- /* pfr is the pointer to where f1-f13 are stored in ffi_closure_LINUX64 */

83576

-

83577

- void **avalue;

83578

- ffi_type **arg_types;

83579

- long i, avn;

83580

- ffi_cif *cif;

83581

- ffi_dblfl *end_pfr = pfr + NUM_FPR_ARG_REGISTERS64;

83582

-

83583

- cif = closure->cif;

83584

- avalue = alloca (cif->nargs * sizeof (void *));

83585

-

83586

- /* Copy the caller's structure return value address so that the closure

83587

- returns the data directly to the caller. */

83588

- if (cif->rtype->type == FFI_TYPE_STRUCT)

83589

- {

83590

- rvalue = (void *) *pst;

83591

- pst++;

83592

- }

83593

-

83594

- i = 0;

83595

- avn = cif->nargs;

83596

- arg_types = cif->arg_types;

83597

-

83598

- /* Grab the addresses of the arguments from the stack frame. */

83599

- while (i < avn)

83600

- {

83601

- switch (arg_types[i]->type)

83602

- {

83603

- case FFI_TYPE_SINT8:

83604

- case FFI_TYPE_UINT8:

83605

-#ifndef __LITTLE_ENDIAN__

83606

- avalue[i] = (char *) pst + 7;

83607

- pst++;

83608

- break;

83609

-#endif

83610

- case FFI_TYPE_SINT16:

83611

- case FFI_TYPE_UINT16:

83612

-#ifndef __LITTLE_ENDIAN__

83613

- avalue[i] = (char *) pst + 6;

83614

- pst++;

83615

- break;

83616

-#endif

83617

- case FFI_TYPE_SINT32:

83618

- case FFI_TYPE_UINT32:

83619

-#ifndef __LITTLE_ENDIAN__

83620

- avalue[i] = (char *) pst + 4;

83621

- pst++;

83622

- break;

83623

-#endif

83624

- case FFI_TYPE_SINT64:

83625

- case FFI_TYPE_UINT64:

83626

- case FFI_TYPE_POINTER:

83627

- avalue[i] = pst;

83628

- pst++;

83629

- break;

83630

-

83631

- case FFI_TYPE_STRUCT:

83632

-#ifndef __LITTLE_ENDIAN__

83633

- /* Structures with size less than eight bytes are passed

83634

- left-padded. */

83635

- if (arg_types[i]->size < 8)

83636

- avalue[i] = (char *) pst + 8 - arg_types[i]->size;

83637

- else

83638

-#endif

83639

- avalue[i] = pst;

83640

- pst += (arg_types[i]->size + 7) / 8;

83641

- break;

83642

-

83643

- case FFI_TYPE_FLOAT:

83644

- /* unfortunately float values are stored as doubles

83645

- * in the ffi_closure_LINUX64 code (since we don't check

83646

- * the type in that routine).

83647

- */

83648

-

83649

- /* there are 13 64bit floating point registers */

83650

-

83651

- if (pfr < end_pfr)

83652

- {

83653

- double temp = pfr->d;

83654

- pfr->f = (float) temp;

83655

- avalue[i] = pfr;

83656

- pfr++;

83657

- }

83658

- else

83659

- avalue[i] = pst;

83660

- pst++;

83661

- break;

83662

-

83663

- case FFI_TYPE_DOUBLE:

83664

- /* On the outgoing stack all values are aligned to 8 */

83665

- /* there are 13 64bit floating point registers */

83666

-

83667

- if (pfr < end_pfr)

83668

- {

83669

- avalue[i] = pfr;

83670

- pfr++;

83671

- }

83672

- else

83673

- avalue[i] = pst;

83674

- pst++;

83675

- break;

83676

-

83677

-#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

83678

- case FFI_TYPE_LONGDOUBLE:

83679

- if (pfr + 1 < end_pfr)

83680

- {

83681

- avalue[i] = pfr;

83682

- pfr += 2;

83683

- }

83684

- else

83685

- {

83686

- if (pfr < end_pfr)

83687

- {

83688

- /* Passed partly in f13 and partly on the stack.

83689

- Move it all to the stack. */

83690

- *pst = *(unsigned long *) pfr;

83691

- pfr++;

83692

- }

83693

- avalue[i] = pst;

83694

- }

83695

- pst += 2;

83696

- break;

83697

-#endif

83698

-

83699

- default:

83700

- FFI_ASSERT (0);

83701

- }

83702

-

83703

- i++;

83704

- }

83705

-

83706

-

83707

- (closure->fun) (cif, rvalue, avalue, closure->user_data);

83708

-

83709

- /* Tell ffi_closure_LINUX64 how to perform return type promotions. */

83710

- return cif->rtype->type;

83711

-}

83712

Index: libffi/src/powerpc/sysv.S

83713

===================================================================

83714

--- a/src/libffi/src/powerpc/sysv.S (.../tags/gcc_4_8_2_release)

83715

+++ b/src/libffi/src/powerpc/sysv.S (.../branches/gcc-4_8-branch)

83716

@@ -30,7 +30,7 @@

83717

#include <ffi.h>

83718

#include <powerpc/asm.h>

83719

83720

-#ifndef __powerpc64__

83721

+#ifndef POWERPC64

83722

.globl ffi_prep_args_SYSV

83723

ENTRY(ffi_call_SYSV)

83724

.LFB1:

83725

@@ -213,8 +213,8 @@

83726

.uleb128 0x1c

83727

.align 2

83728

.LEFDE1:

83729

-#endif

83730

83731

#if defined __ELF__ && defined __linux__

83732

.section .note.GNU-stack,"",@progbits

83733

#endif

83734

+#endif

83735

Index: libffi/src/powerpc/linux64_closure.S

83736

===================================================================

83737

--- a/src/libffi/src/powerpc/linux64_closure.S (.../tags/gcc_4_8_2_release)

83738

+++ b/src/libffi/src/powerpc/linux64_closure.S (.../branches/gcc-4_8-branch)

83739

@@ -30,18 +30,25 @@

83740

83741

.file "linux64_closure.S"

83742

83743

-#ifdef __powerpc64__

83744

+#ifdef POWERPC64

83745

FFI_HIDDEN (ffi_closure_LINUX64)

83746

.globl ffi_closure_LINUX64

83747

+# if _CALL_ELF == 2

83748

+ .text

83749

+ffi_closure_LINUX64:

83750

+ addis %r2, %r12, .TOC.-ffi_closure_LINUX64@ha

83751

+ addi %r2, %r2, .TOC.-ffi_closure_LINUX64@l

83752

+ .localentry ffi_closure_LINUX64, . - ffi_closure_LINUX64

83753

+# else

83754

.section ".opd","aw"

83755

.align 3

83756

ffi_closure_LINUX64:

83757

-#ifdef _CALL_LINUX

83758

+# ifdef _CALL_LINUX

83759

.quad .L.ffi_closure_LINUX64,.TOC.@tocbase,0

83760

.type ffi_closure_LINUX64,@function

83761

.text

83762

.L.ffi_closure_LINUX64:

83763

-#else

83764

+# else

83765

FFI_HIDDEN (.ffi_closure_LINUX64)

83766

.globl .ffi_closure_LINUX64

83767

.quad .ffi_closure_LINUX64,.TOC.@tocbase,0

83768

@@ -49,61 +56,101 @@

83769

.type .ffi_closure_LINUX64,@function

83770

.text

83771

.ffi_closure_LINUX64:

83772

-#endif

83773

+# endif

83774

+# endif

83775

+

83776

+# if _CALL_ELF == 2

83777

+# 32 byte special reg save area + 64 byte parm save area

83778

+# + 64 byte retval area + 13*8 fpr save area + round to 16

83779

+# define STACKFRAME 272

83780

+# define PARMSAVE 32

83781

+# define RETVAL PARMSAVE+64

83782

+# else

83783

+# 48 bytes special reg save area + 64 bytes parm save area

83784

+# + 16 bytes retval area + 13*8 bytes fpr save area + round to 16

83785

+# define STACKFRAME 240

83786

+# define PARMSAVE 48

83787

+# define RETVAL PARMSAVE+64

83788

+# endif

83789

+

83790

.LFB1:

83791

- # save general regs into parm save area

83792

- std %r3, 48(%r1)

83793

- std %r4, 56(%r1)

83794

- std %r5, 64(%r1)

83795

- std %r6, 72(%r1)

83796

+# if _CALL_ELF == 2

83797

+ ld %r12, FFI_TRAMPOLINE_SIZE(%r11) # closure->cif

83798

mflr %r0

83799

+ lwz %r12, 28(%r12) # cif->flags

83800

+ mtcrf 0x40, %r12

83801

+ addi %r12, %r1, PARMSAVE

83802

+ bt 7, .Lparmsave

83803

+ # Our caller has not allocated a parameter save area.

83804

+ # We need to allocate one here and use it to pass gprs to

83805

+ # ffi_closure_helper_LINUX64.

83806

+ addi %r12, %r1, -STACKFRAME+PARMSAVE

83807

+.Lparmsave:

83808

+ std %r0, 16(%r1)

83809

+ # Save general regs into parm save area

83810

+ std %r3, 0(%r12)

83811

+ std %r4, 8(%r12)

83812

+ std %r5, 16(%r12)

83813

+ std %r6, 24(%r12)

83814

+ std %r7, 32(%r12)

83815

+ std %r8, 40(%r12)

83816

+ std %r9, 48(%r12)

83817

+ std %r10, 56(%r12)

83818

83819

- std %r7, 80(%r1)

83820

- std %r8, 88(%r1)

83821

- std %r9, 96(%r1)

83822

- std %r10, 104(%r1)

83823

+ # load up the pointer to the parm save area

83824

+ mr %r5, %r12

83825

+# else

83826

+ mflr %r0

83827

+ # Save general regs into parm save area

83828

+ # This is the parameter save area set up by our caller.

83829

+ std %r3, PARMSAVE+0(%r1)

83830

+ std %r4, PARMSAVE+8(%r1)

83831

+ std %r5, PARMSAVE+16(%r1)

83832

+ std %r6, PARMSAVE+24(%r1)

83833

+ std %r7, PARMSAVE+32(%r1)

83834

+ std %r8, PARMSAVE+40(%r1)

83835

+ std %r9, PARMSAVE+48(%r1)

83836

+ std %r10, PARMSAVE+56(%r1)

83837

+

83838

std %r0, 16(%r1)

83839

83840

- # mandatory 48 bytes special reg save area + 64 bytes parm save area

83841

- # + 16 bytes retval area + 13*8 bytes fpr save area + round to 16

83842

- stdu %r1, -240(%r1)

83843

-.LCFI0:

83844

+ # load up the pointer to the parm save area

83845

+ addi %r5, %r1, PARMSAVE

83846

+# endif

83847

83848

# next save fpr 1 to fpr 13

83849

- stfd %f1, 128+(0*8)(%r1)

83850

- stfd %f2, 128+(1*8)(%r1)

83851

- stfd %f3, 128+(2*8)(%r1)

83852

- stfd %f4, 128+(3*8)(%r1)

83853

- stfd %f5, 128+(4*8)(%r1)

83854

- stfd %f6, 128+(5*8)(%r1)

83855

- stfd %f7, 128+(6*8)(%r1)

83856

- stfd %f8, 128+(7*8)(%r1)

83857

- stfd %f9, 128+(8*8)(%r1)

83858

- stfd %f10, 128+(9*8)(%r1)

83859

- stfd %f11, 128+(10*8)(%r1)

83860

- stfd %f12, 128+(11*8)(%r1)

83861

- stfd %f13, 128+(12*8)(%r1)

83862

+ stfd %f1, -104+(0*8)(%r1)

83863

+ stfd %f2, -104+(1*8)(%r1)

83864

+ stfd %f3, -104+(2*8)(%r1)

83865

+ stfd %f4, -104+(3*8)(%r1)

83866

+ stfd %f5, -104+(4*8)(%r1)

83867

+ stfd %f6, -104+(5*8)(%r1)

83868

+ stfd %f7, -104+(6*8)(%r1)

83869

+ stfd %f8, -104+(7*8)(%r1)

83870

+ stfd %f9, -104+(8*8)(%r1)

83871

+ stfd %f10, -104+(9*8)(%r1)

83872

+ stfd %f11, -104+(10*8)(%r1)

83873

+ stfd %f12, -104+(11*8)(%r1)

83874

+ stfd %f13, -104+(12*8)(%r1)

83875

83876

- # set up registers for the routine that actually does the work

83877

- # get the context pointer from the trampoline

83878

- mr %r3, %r11

83879

+ # load up the pointer to the saved fpr registers */

83880

+ addi %r6, %r1, -104

83881

83882

- # now load up the pointer to the result storage

83883

- addi %r4, %r1, 112

83884

+ # load up the pointer to the result storage

83885

+ addi %r4, %r1, -STACKFRAME+RETVAL

83886

83887

- # now load up the pointer to the parameter save area

83888

- # in the previous frame

83889

- addi %r5, %r1, 240 + 48

83890

+ stdu %r1, -STACKFRAME(%r1)

83891

+.LCFI0:

83892

83893

- # now load up the pointer to the saved fpr registers */

83894

- addi %r6, %r1, 128

83895

+ # get the context pointer from the trampoline

83896

+ mr %r3, %r11

83897

83898

# make the call

83899

-#ifdef _CALL_LINUX

83900

+# if defined _CALL_LINUX || _CALL_ELF == 2

83901

bl ffi_closure_helper_LINUX64

83902

-#else

83903

+# else

83904

bl .ffi_closure_helper_LINUX64

83905

-#endif

83906

+# endif

83907

.Lret:

83908

83909

# now r3 contains the return type

83910

@@ -112,10 +159,12 @@

83911

83912

# look up the proper starting point in table

83913

# by using return type as offset

83914

+ ld %r0, STACKFRAME+16(%r1)

83915

+ cmpldi %r3, FFI_V2_TYPE_SMALL_STRUCT

83916

+ bge .Lsmall

83917

mflr %r4 # move address of .Lret to r4

83918

sldi %r3, %r3, 4 # now multiply return type by 16

83919

addi %r4, %r4, .Lret_type0 - .Lret

83920

- ld %r0, 240+16(%r1)

83921

add %r3, %r3, %r4 # add contents of table to table address

83922

mtctr %r3

83923

bctr # jump to it

83924

@@ -128,117 +177,175 @@

83925

.Lret_type0:

83926

# case FFI_TYPE_VOID

83927

mtlr %r0

83928

- addi %r1, %r1, 240

83929

+ addi %r1, %r1, STACKFRAME

83930

blr

83931

nop

83932

# case FFI_TYPE_INT

83933

-#ifdef __LITTLE_ENDIAN__

83934

- lwa %r3, 112+0(%r1)

83935

-#else

83936

- lwa %r3, 112+4(%r1)

83937

-#endif

83938

+# ifdef __LITTLE_ENDIAN__

83939

+ lwa %r3, RETVAL+0(%r1)

83940

+# else

83941

+ lwa %r3, RETVAL+4(%r1)

83942

+# endif

83943

mtlr %r0

83944

- addi %r1, %r1, 240

83945

+ addi %r1, %r1, STACKFRAME

83946

blr

83947

# case FFI_TYPE_FLOAT

83948

- lfs %f1, 112+0(%r1)

83949

+ lfs %f1, RETVAL+0(%r1)

83950

mtlr %r0

83951

- addi %r1, %r1, 240

83952

+ addi %r1, %r1, STACKFRAME

83953

blr

83954

# case FFI_TYPE_DOUBLE

83955

- lfd %f1, 112+0(%r1)

83956

+ lfd %f1, RETVAL+0(%r1)

83957

mtlr %r0

83958

- addi %r1, %r1, 240

83959

+ addi %r1, %r1, STACKFRAME

83960

blr

83961

# case FFI_TYPE_LONGDOUBLE

83962

- lfd %f1, 112+0(%r1)

83963

+ lfd %f1, RETVAL+0(%r1)

83964

mtlr %r0

83965

- lfd %f2, 112+8(%r1)

83966

+ lfd %f2, RETVAL+8(%r1)

83967

b .Lfinish

83968

# case FFI_TYPE_UINT8

83969

-#ifdef __LITTLE_ENDIAN__

83970

- lbz %r3, 112+0(%r1)

83971

-#else

83972

- lbz %r3, 112+7(%r1)

83973

-#endif

83974

+# ifdef __LITTLE_ENDIAN__

83975

+ lbz %r3, RETVAL+0(%r1)

83976

+# else

83977

+ lbz %r3, RETVAL+7(%r1)

83978

+# endif

83979

mtlr %r0

83980

- addi %r1, %r1, 240

83981

+ addi %r1, %r1, STACKFRAME

83982

blr

83983

# case FFI_TYPE_SINT8

83984

-#ifdef __LITTLE_ENDIAN__

83985

- lbz %r3, 112+0(%r1)

83986

-#else

83987

- lbz %r3, 112+7(%r1)

83988

-#endif

83989

+# ifdef __LITTLE_ENDIAN__

83990

+ lbz %r3, RETVAL+0(%r1)

83991

+# else

83992

+ lbz %r3, RETVAL+7(%r1)

83993

+# endif

83994

extsb %r3,%r3

83995

mtlr %r0

83996

b .Lfinish

83997

# case FFI_TYPE_UINT16

83998

-#ifdef __LITTLE_ENDIAN__

83999

- lhz %r3, 112+0(%r1)

84000

-#else

84001

- lhz %r3, 112+6(%r1)

84002

-#endif

84003

+# ifdef __LITTLE_ENDIAN__

84004

+ lhz %r3, RETVAL+0(%r1)

84005

+# else

84006

+ lhz %r3, RETVAL+6(%r1)

84007

+# endif

84008

mtlr %r0

84009

.Lfinish:

84010

- addi %r1, %r1, 240

84011

+ addi %r1, %r1, STACKFRAME

84012

blr

84013

# case FFI_TYPE_SINT16

84014

-#ifdef __LITTLE_ENDIAN__

84015

- lha %r3, 112+0(%r1)

84016

-#else

84017

- lha %r3, 112+6(%r1)

84018

-#endif

84019

+# ifdef __LITTLE_ENDIAN__

84020

+ lha %r3, RETVAL+0(%r1)

84021

+# else

84022

+ lha %r3, RETVAL+6(%r1)

84023

+# endif

84024

mtlr %r0

84025

- addi %r1, %r1, 240

84026

+ addi %r1, %r1, STACKFRAME

84027

blr

84028

# case FFI_TYPE_UINT32

84029

-#ifdef __LITTLE_ENDIAN__

84030

- lwz %r3, 112+0(%r1)

84031

-#else

84032

- lwz %r3, 112+4(%r1)

84033

-#endif

84034

+# ifdef __LITTLE_ENDIAN__

84035

+ lwz %r3, RETVAL+0(%r1)

84036

+# else

84037

+ lwz %r3, RETVAL+4(%r1)

84038

+# endif

84039

mtlr %r0

84040

- addi %r1, %r1, 240

84041

+ addi %r1, %r1, STACKFRAME

84042

blr

84043

# case FFI_TYPE_SINT32

84044

-#ifdef __LITTLE_ENDIAN__

84045

- lwa %r3, 112+0(%r1)

84046

-#else

84047

- lwa %r3, 112+4(%r1)

84048

-#endif

84049

+# ifdef __LITTLE_ENDIAN__

84050

+ lwa %r3, RETVAL+0(%r1)

84051

+# else

84052

+ lwa %r3, RETVAL+4(%r1)

84053

+# endif

84054

mtlr %r0

84055

- addi %r1, %r1, 240

84056

+ addi %r1, %r1, STACKFRAME

84057

blr

84058

# case FFI_TYPE_UINT64

84059

- ld %r3, 112+0(%r1)

84060

+ ld %r3, RETVAL+0(%r1)

84061

mtlr %r0

84062

- addi %r1, %r1, 240

84063

+ addi %r1, %r1, STACKFRAME

84064

blr

84065

# case FFI_TYPE_SINT64

84066

- ld %r3, 112+0(%r1)

84067

+ ld %r3, RETVAL+0(%r1)

84068

mtlr %r0

84069

- addi %r1, %r1, 240

84070

+ addi %r1, %r1, STACKFRAME

84071

blr

84072

# case FFI_TYPE_STRUCT

84073

mtlr %r0

84074

- addi %r1, %r1, 240

84075

+ addi %r1, %r1, STACKFRAME

84076

blr

84077

nop

84078

# case FFI_TYPE_POINTER

84079

- ld %r3, 112+0(%r1)

84080

+ ld %r3, RETVAL+0(%r1)

84081

mtlr %r0

84082

- addi %r1, %r1, 240

84083

+ addi %r1, %r1, STACKFRAME

84084

blr

84085

-# esac

84086

+# case FFI_V2_TYPE_FLOAT_HOMOG

84087

+ lfs %f1, RETVAL+0(%r1)

84088

+ lfs %f2, RETVAL+4(%r1)

84089

+ lfs %f3, RETVAL+8(%r1)

84090

+ b .Lmorefloat

84091

+# case FFI_V2_TYPE_DOUBLE_HOMOG

84092

+ lfd %f1, RETVAL+0(%r1)

84093

+ lfd %f2, RETVAL+8(%r1)

84094

+ lfd %f3, RETVAL+16(%r1)

84095

+ lfd %f4, RETVAL+24(%r1)

84096

+ mtlr %r0

84097

+ lfd %f5, RETVAL+32(%r1)

84098

+ lfd %f6, RETVAL+40(%r1)

84099

+ lfd %f7, RETVAL+48(%r1)

84100

+ lfd %f8, RETVAL+56(%r1)

84101

+ addi %r1, %r1, STACKFRAME

84102

+ blr

84103

+.Lmorefloat:

84104

+ lfs %f4, RETVAL+12(%r1)

84105

+ mtlr %r0

84106

+ lfs %f5, RETVAL+16(%r1)

84107

+ lfs %f6, RETVAL+20(%r1)

84108

+ lfs %f7, RETVAL+24(%r1)

84109

+ lfs %f8, RETVAL+28(%r1)

84110

+ addi %r1, %r1, STACKFRAME

84111

+ blr

84112

+.Lsmall:

84113

+# ifdef __LITTLE_ENDIAN__

84114

+ ld %r3,RETVAL+0(%r1)

84115

+ mtlr %r0

84116

+ ld %r4,RETVAL+8(%r1)

84117

+ addi %r1, %r1, STACKFRAME

84118

+ blr

84119

+# else

84120

+ # A struct smaller than a dword is returned in the low bits of r3

84121

+ # ie. right justified. Larger structs are passed left justified

84122

+ # in r3 and r4. The return value area on the stack will have

84123

+ # the structs as they are usually stored in memory.

84124

+ cmpldi %r3, FFI_V2_TYPE_SMALL_STRUCT + 7 # size 8 bytes?

84125

+ neg %r5, %r3

84126

+ ld %r3,RETVAL+0(%r1)

84127

+ blt .Lsmalldown

84128

+ mtlr %r0

84129

+ ld %r4,RETVAL+8(%r1)

84130

+ addi %r1, %r1, STACKFRAME

84131

+ blr

84132

+.Lsmalldown:

84133

+ addi %r5, %r5, FFI_V2_TYPE_SMALL_STRUCT + 7

84134

+ mtlr %r0

84135

+ sldi %r5, %r5, 3

84136

+ addi %r1, %r1, STACKFRAME

84137

+ srd %r3, %r3, %r5

84138

+ blr

84139

+# endif

84140

+

84141

.LFE1:

84142

.long 0

84143

.byte 0,12,0,1,128,0,0,0

84144

-#ifdef _CALL_LINUX

84145

+# if _CALL_ELF == 2

84146

+ .size ffi_closure_LINUX64,.-ffi_closure_LINUX64

84147

+# else

84148

+# ifdef _CALL_LINUX

84149

.size ffi_closure_LINUX64,.-.L.ffi_closure_LINUX64

84150

-#else

84151

+# else

84152

.size .ffi_closure_LINUX64,.-.ffi_closure_LINUX64

84153

-#endif

84154

+# endif

84155

+# endif

84156

84157

.section .eh_frame,EH_FRAME_FLAGS,@progbits

84158

.Lframe1:

84159

@@ -267,14 +374,14 @@

84160

.byte 0x2 # DW_CFA_advance_loc1

84161

.byte .LCFI0-.LFB1

84162

.byte 0xe # DW_CFA_def_cfa_offset

84163

- .uleb128 240

84164

+ .uleb128 STACKFRAME

84165

.byte 0x11 # DW_CFA_offset_extended_sf

84166

.uleb128 0x41

84167

.sleb128 -2

84168

.align 3

84169

.LEFDE1:

84170

-#endif

84171

84172

-#if defined __ELF__ && defined __linux__

84173

+# if defined __ELF__ && defined __linux__

84174

.section .note.GNU-stack,"",@progbits

84175

+# endif

84176

#endif

84177

Index: libffi/src/powerpc/ffi_powerpc.h

84178

===================================================================

84179

--- a/src/libffi/src/powerpc/ffi_powerpc.h (.../tags/gcc_4_8_2_release)

84180

+++ b/src/libffi/src/powerpc/ffi_powerpc.h (.../branches/gcc-4_8-branch)

84181

@@ -0,0 +1,77 @@

84182

+/* -----------------------------------------------------------------------

84183

84184

84185

84186

84187

84188

84189

+

84190

+ PowerPC Foreign Function Interface

84191

+

84192

+ Permission is hereby granted, free of charge, to any person obtaining

84193

+ a copy of this software and associated documentation files (the

84194

+ ``Software''), to deal in the Software without restriction, including

84195

+ without limitation the rights to use, copy, modify, merge, publish,

84196

+ distribute, sublicense, and/or sell copies of the Software, and to

84197

+ permit persons to whom the Software is furnished to do so, subject to

84198

+ the following conditions:

84199

+

84200

+ The above copyright notice and this permission notice shall be included

84201

+ in all copies or substantial portions of the Software.

84202

+

84203

+ THE SOFTWARE IS PROVIDED ``AS IS'', WITHOUT WARRANTY OF ANY KIND, EXPRESS

84204

+ OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

84205

+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.

84206

+ IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR

84207

+ OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

84208

+ ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

84209

+ OTHER DEALINGS IN THE SOFTWARE.

84210

+ ----------------------------------------------------------------------- */

84211

+

84212

+enum {

84213

+ /* The assembly depends on these exact flags. */

84214

+ /* These go in cr7 */

84215

+ FLAG_RETURNS_SMST = 1 << (31-31), /* Used for FFI_SYSV small structs. */

84216

+ FLAG_RETURNS_NOTHING = 1 << (31-30),

84217

+ FLAG_RETURNS_FP = 1 << (31-29),

84218

+ FLAG_RETURNS_64BITS = 1 << (31-28),

84219

+

84220

+ /* This goes in cr6 */

84221

+ FLAG_RETURNS_128BITS = 1 << (31-27),

84222

+

84223

+ FLAG_COMPAT = 1 << (31- 8), /* Not used by assembly */

84224

+

84225

+ /* These go in cr1 */

84226

+ FLAG_ARG_NEEDS_COPY = 1 << (31- 7), /* Used by sysv code */

84227

+ FLAG_ARG_NEEDS_PSAVE = FLAG_ARG_NEEDS_COPY, /* Used by linux64 code */

84228

+ FLAG_FP_ARGUMENTS = 1 << (31- 6), /* cr1.eq; specified by ABI */

84229

+ FLAG_4_GPR_ARGUMENTS = 1 << (31- 5),

84230

+ FLAG_RETVAL_REFERENCE = 1 << (31- 4)

84231

+};

84232

+

84233

+typedef union

84234

+{

84235

+ float f;

84236

+ double d;

84237

+} ffi_dblfl;

84238

+

84239

+void FFI_HIDDEN ffi_closure_SYSV (void);

84240

+void FFI_HIDDEN ffi_call_SYSV(extended_cif *, unsigned, unsigned, unsigned *,

84241

+ void (*)(void));

84242

+

84243

+void FFI_HIDDEN ffi_prep_types_sysv (ffi_abi);

84244

+ffi_status FFI_HIDDEN ffi_prep_cif_sysv (ffi_cif *);

84245

+int FFI_HIDDEN ffi_closure_helper_SYSV (ffi_closure *, void *, unsigned long *,

84246

+ ffi_dblfl *, unsigned long *);

84247

+

84248

+void FFI_HIDDEN ffi_call_LINUX64(extended_cif *, unsigned long, unsigned long,

84249

+ unsigned long *, void (*)(void));

84250

+void FFI_HIDDEN ffi_closure_LINUX64 (void);

84251

+

84252

+void FFI_HIDDEN ffi_prep_types_linux64 (ffi_abi);

84253

+ffi_status FFI_HIDDEN ffi_prep_cif_linux64 (ffi_cif *);

84254

+ffi_status FFI_HIDDEN ffi_prep_cif_linux64_var (ffi_cif *, unsigned int,

84255

+ unsigned int);

84256

+void FFI_HIDDEN ffi_prep_args64 (extended_cif *, unsigned long *const);

84257

+int FFI_HIDDEN ffi_closure_helper_LINUX64 (ffi_closure *, void *,

84258

+ unsigned long *, ffi_dblfl *);

84259

Index: libffi/src/powerpc/ffi_sysv.c

84260

===================================================================

84261

--- a/src/libffi/src/powerpc/ffi_sysv.c (.../tags/gcc_4_8_2_release)

84262

+++ b/src/libffi/src/powerpc/ffi_sysv.c (.../branches/gcc-4_8-branch)

84263

@@ -0,0 +1,931 @@

84264

+/* -----------------------------------------------------------------------

84265

84266

84267

84268

84269

84270

84271

+

84272

+ PowerPC Foreign Function Interface

84273

+

84274

+ Permission is hereby granted, free of charge, to any person obtaining

84275

+ a copy of this software and associated documentation files (the

84276

+ ``Software''), to deal in the Software without restriction, including

84277

+ without limitation the rights to use, copy, modify, merge, publish,

84278

+ distribute, sublicense, and/or sell copies of the Software, and to

84279

+ permit persons to whom the Software is furnished to do so, subject to

84280

+ the following conditions:

84281

+

84282

+ The above copyright notice and this permission notice shall be included

84283

+ in all copies or substantial portions of the Software.

84284

+

84285

+ THE SOFTWARE IS PROVIDED ``AS IS'', WITHOUT WARRANTY OF ANY KIND, EXPRESS

84286

+ OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

84287

+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.

84288

+ IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR

84289

+ OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

84290

+ ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

84291

+ OTHER DEALINGS IN THE SOFTWARE.

84292

+ ----------------------------------------------------------------------- */

84293

+

84294

+#include "ffi.h"

84295

+

84296

+#ifndef POWERPC64

84297

+#include "ffi_common.h"

84298

+#include "ffi_powerpc.h"

84299

+

84300

+

84301

+/* About the SYSV ABI. */

84302

+#define ASM_NEEDS_REGISTERS 4

84303

+#define NUM_GPR_ARG_REGISTERS 8

84304

+#define NUM_FPR_ARG_REGISTERS 8

84305

+

84306

+

84307

+#if HAVE_LONG_DOUBLE_VARIANT && FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

84308

+/* Adjust size of ffi_type_longdouble. */

84309

+void FFI_HIDDEN

84310

+ffi_prep_types_sysv (ffi_abi abi)

84311

+{

84312

+ if ((abi & (FFI_SYSV | FFI_SYSV_LONG_DOUBLE_128)) == FFI_SYSV)

84313

+ {

84314

+ ffi_type_longdouble.size = 8;

84315

+ ffi_type_longdouble.alignment = 8;

84316

+ }

84317

+ else

84318

+ {

84319

+ ffi_type_longdouble.size = 16;

84320

+ ffi_type_longdouble.alignment = 16;

84321

+ }

84322

+}

84323

+#endif

84324

+

84325

+/* Transform long double, double and float to other types as per abi. */

84326

+static int

84327

+translate_float (int abi, int type)

84328

+{

84329

+#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

84330

+ if (type == FFI_TYPE_LONGDOUBLE

84331

+ && (abi & FFI_SYSV_LONG_DOUBLE_128) == 0)

84332

+ type = FFI_TYPE_DOUBLE;

84333

+#endif

84334

+ if ((abi & FFI_SYSV_SOFT_FLOAT) != 0)

84335

+ {

84336

+ if (type == FFI_TYPE_FLOAT)

84337

+ type = FFI_TYPE_UINT32;

84338

+ else if (type == FFI_TYPE_DOUBLE)

84339

+ type = FFI_TYPE_UINT64;

84340

+#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

84341

+ else if (type == FFI_TYPE_LONGDOUBLE)

84342

+ type = FFI_TYPE_UINT128;

84343

+ }

84344

+ else if ((abi & FFI_SYSV_IBM_LONG_DOUBLE) == 0)

84345

+ {

84346

+ if (type == FFI_TYPE_LONGDOUBLE)

84347

+ type = FFI_TYPE_STRUCT;

84348

+#endif

84349

+ }

84350

+ return type;

84351

+}

84352

+

84353

+/* Perform machine dependent cif processing */

84354

+static ffi_status

84355

+ffi_prep_cif_sysv_core (ffi_cif *cif)

84356

+{

84357

+ ffi_type **ptr;

84358

+ unsigned bytes;

84359

+ unsigned i, fparg_count = 0, intarg_count = 0;

84360

+ unsigned flags = cif->flags;

84361

+ unsigned struct_copy_size = 0;

84362

+ unsigned type = cif->rtype->type;

84363

+ unsigned size = cif->rtype->size;

84364

+

84365

+ /* The machine-independent calculation of cif->bytes doesn't work

84366

+ for us. Redo the calculation. */

84367

+

84368

+ /* Space for the frame pointer, callee's LR, and the asm's temp regs. */

84369

+ bytes = (2 + ASM_NEEDS_REGISTERS) * sizeof (int);

84370

+

84371

+ /* Space for the GPR registers. */

84372

+ bytes += NUM_GPR_ARG_REGISTERS * sizeof (int);

84373

+

84374

+ /* Return value handling. The rules for SYSV are as follows:

84375

+ - 32-bit (or less) integer values are returned in gpr3;

84376

+ - Structures of size <= 4 bytes also returned in gpr3;

84377

+ - 64-bit integer values and structures between 5 and 8 bytes are returned

84378

+ in gpr3 and gpr4;

84379

+ - Larger structures are allocated space and a pointer is passed as

84380

+ the first argument.

84381

+ - Single/double FP values are returned in fpr1;

84382

+ - long doubles (if not equivalent to double) are returned in

84383

+ fpr1,fpr2 for Linux and as for large structs for SysV. */

84384

+

84385

+ type = translate_float (cif->abi, type);

84386

+

84387

+ switch (type)

84388

+ {

84389

+#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

84390

+ case FFI_TYPE_LONGDOUBLE:

84391

+ flags |= FLAG_RETURNS_128BITS;

84392

+ /* Fall through. */

84393

+#endif

84394

+ case FFI_TYPE_DOUBLE:

84395

+ flags |= FLAG_RETURNS_64BITS;

84396

+ /* Fall through. */

84397

+ case FFI_TYPE_FLOAT:

84398

+ flags |= FLAG_RETURNS_FP;

84399

+#ifdef __NO_FPRS__

84400

+ return FFI_BAD_ABI;

84401

+#endif

84402

+ break;

84403

+

84404

+ case FFI_TYPE_UINT128:

84405

+ flags |= FLAG_RETURNS_128BITS;

84406

+ /* Fall through. */

84407

+ case FFI_TYPE_UINT64:

84408

+ case FFI_TYPE_SINT64:

84409

+ flags |= FLAG_RETURNS_64BITS;

84410

+ break;

84411

+

84412

+ case FFI_TYPE_STRUCT:

84413

+ /* The final SYSV ABI says that structures smaller or equal 8 bytes

84414

+ are returned in r3/r4. A draft ABI used by linux instead

84415

+ returns them in memory. */

84416

+ if ((cif->abi & FFI_SYSV_STRUCT_RET) != 0 && size <= 8)

84417

+ {

84418

+ flags |= FLAG_RETURNS_SMST;

84419

+ break;

84420

+ }

84421

+ intarg_count++;

84422

+ flags |= FLAG_RETVAL_REFERENCE;

84423

+ /* Fall through. */

84424

+ case FFI_TYPE_VOID:

84425

+ flags |= FLAG_RETURNS_NOTHING;

84426

+ break;

84427

+

84428

+ default:

84429

+ /* Returns 32-bit integer, or similar. Nothing to do here. */

84430

+ break;

84431

+ }

84432

+

84433

+ /* The first NUM_GPR_ARG_REGISTERS words of integer arguments, and the

84434

+ first NUM_FPR_ARG_REGISTERS fp arguments, go in registers; the rest

84435

+ goes on the stack. Structures and long doubles (if not equivalent

84436

+ to double) are passed as a pointer to a copy of the structure.

84437

+ Stuff on the stack needs to keep proper alignment. */

84438

+ for (ptr = cif->arg_types, i = cif->nargs; i > 0; i--, ptr++)

84439

+ {

84440

+ unsigned short typenum = (*ptr)->type;

84441

+

84442

+ typenum = translate_float (cif->abi, typenum);

84443

+

84444

+ switch (typenum)

84445

+ {

84446

+#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

84447

+ case FFI_TYPE_LONGDOUBLE:

84448

+ fparg_count++;

84449

+ /* Fall thru */

84450

+#endif

84451

+ case FFI_TYPE_DOUBLE:

84452

+ fparg_count++;

84453

+ /* If this FP arg is going on the stack, it must be

84454

+ 8-byte-aligned. */

84455

+ if (fparg_count > NUM_FPR_ARG_REGISTERS

84456

+ && intarg_count >= NUM_GPR_ARG_REGISTERS

84457

+ && intarg_count % 2 != 0)

84458

+ intarg_count++;

84459

+#ifdef __NO_FPRS__

84460

+ return FFI_BAD_ABI;

84461

+#endif

84462

+ break;

84463

+

84464

+ case FFI_TYPE_FLOAT:

84465

+ fparg_count++;

84466

+#ifdef __NO_FPRS__

84467

+ return FFI_BAD_ABI;

84468

+#endif

84469

+ break;

84470

+

84471

+ case FFI_TYPE_UINT128:

84472

+ /* A long double in FFI_LINUX_SOFT_FLOAT can use only a set

84473

+ of four consecutive gprs. If we do not have enough, we

84474

+ have to adjust the intarg_count value. */

84475

+ if (intarg_count >= NUM_GPR_ARG_REGISTERS - 3

84476

+ && intarg_count < NUM_GPR_ARG_REGISTERS)

84477

+ intarg_count = NUM_GPR_ARG_REGISTERS;

84478

+ intarg_count += 4;

84479

+ break;

84480

+

84481

+ case FFI_TYPE_UINT64:

84482

+ case FFI_TYPE_SINT64:

84483

+ /* 'long long' arguments are passed as two words, but

84484

+ either both words must fit in registers or both go

84485

+ on the stack. If they go on the stack, they must

84486

+ be 8-byte-aligned.

84487

+

84488

+ Also, only certain register pairs can be used for

84489

+ passing long long int -- specifically (r3,r4), (r5,r6),

84490

+ (r7,r8), (r9,r10). */

84491

+ if (intarg_count == NUM_GPR_ARG_REGISTERS-1

84492

+ || intarg_count % 2 != 0)

84493

+ intarg_count++;

84494

+ intarg_count += 2;

84495

+ break;

84496

+

84497

+ case FFI_TYPE_STRUCT:

84498

+ /* We must allocate space for a copy of these to enforce

84499

+ pass-by-value. Pad the space up to a multiple of 16

84500

+ bytes (the maximum alignment required for anything under

84501

+ the SYSV ABI). */

84502

+ struct_copy_size += ((*ptr)->size + 15) & ~0xF;

84503

+ /* Fall through (allocate space for the pointer). */

84504

+

84505

+ case FFI_TYPE_POINTER:

84506

+ case FFI_TYPE_INT:

84507

+ case FFI_TYPE_UINT32:

84508

+ case FFI_TYPE_SINT32:

84509

+ case FFI_TYPE_UINT16:

84510

+ case FFI_TYPE_SINT16:

84511

+ case FFI_TYPE_UINT8:

84512

+ case FFI_TYPE_SINT8:

84513

+ /* Everything else is passed as a 4-byte word in a GPR, either

84514

+ the object itself or a pointer to it. */

84515

+ intarg_count++;

84516

+ break;

84517

+

84518

+ default:

84519

+ FFI_ASSERT (0);

84520

+ }

84521

+ }

84522

+

84523

+ if (fparg_count != 0)

84524

+ flags |= FLAG_FP_ARGUMENTS;

84525

+ if (intarg_count > 4)

84526

+ flags |= FLAG_4_GPR_ARGUMENTS;

84527

+ if (struct_copy_size != 0)

84528

+ flags |= FLAG_ARG_NEEDS_COPY;

84529

+

84530

+ /* Space for the FPR registers, if needed. */

84531

+ if (fparg_count != 0)

84532

+ bytes += NUM_FPR_ARG_REGISTERS * sizeof (double);

84533

+

84534

+ /* Stack space. */

84535

+ if (intarg_count > NUM_GPR_ARG_REGISTERS)

84536

+ bytes += (intarg_count - NUM_GPR_ARG_REGISTERS) * sizeof (int);

84537

+ if (fparg_count > NUM_FPR_ARG_REGISTERS)

84538

+ bytes += (fparg_count - NUM_FPR_ARG_REGISTERS) * sizeof (double);

84539

+

84540

+ /* The stack space allocated needs to be a multiple of 16 bytes. */

84541

+ bytes = (bytes + 15) & ~0xF;

84542

+

84543

+ /* Add in the space for the copied structures. */

84544

+ bytes += struct_copy_size;

84545

+

84546

+ cif->flags = flags;

84547

+ cif->bytes = bytes;

84548

+

84549

+ return FFI_OK;

84550

+}

84551

+

84552

+ffi_status FFI_HIDDEN

84553

+ffi_prep_cif_sysv (ffi_cif *cif)

84554

+{

84555

+ if ((cif->abi & FFI_SYSV) == 0)

84556

+ {

84557

+ /* This call is from old code. Translate to new ABI values. */

84558

+ cif->flags |= FLAG_COMPAT;

84559

+ switch (cif->abi)

84560

+ {

84561

+ default:

84562

+ return FFI_BAD_ABI;

84563

+

84564

+ case FFI_COMPAT_SYSV:

84565

+ cif->abi = FFI_SYSV | FFI_SYSV_STRUCT_RET | FFI_SYSV_LONG_DOUBLE_128;

84566

+ break;

84567

+

84568

+ case FFI_COMPAT_GCC_SYSV:

84569

+ cif->abi = FFI_SYSV | FFI_SYSV_LONG_DOUBLE_128;

84570

+ break;

84571

+

84572

+ case FFI_COMPAT_LINUX:

84573

+ cif->abi = (FFI_SYSV | FFI_SYSV_IBM_LONG_DOUBLE

84574

+ | FFI_SYSV_LONG_DOUBLE_128);

84575

+ break;

84576

+

84577

+ case FFI_COMPAT_LINUX_SOFT_FLOAT:

84578

+ cif->abi = (FFI_SYSV | FFI_SYSV_SOFT_FLOAT | FFI_SYSV_IBM_LONG_DOUBLE

84579

+ | FFI_SYSV_LONG_DOUBLE_128);

84580

+ break;

84581

+ }

84582

+ }

84583

+ return ffi_prep_cif_sysv_core (cif);

84584

+}

84585

+

84586

+/* ffi_prep_args_SYSV is called by the assembly routine once stack space

84587

+ has been allocated for the function's arguments.

84588

+

84589

+ The stack layout we want looks like this:

84590

+

84591

+ | Return address from ffi_call_SYSV 4bytes | higher addresses

84592

+ |--------------------------------------------|

84593

+ | Previous backchain pointer 4 | stack pointer here

84594

+ |--------------------------------------------|<+ <<< on entry to

84595

+ | Saved r28-r31 4*4 | | ffi_call_SYSV

84596

+ |--------------------------------------------| |

84597

+ | GPR registers r3-r10 8*4 | | ffi_call_SYSV

84598

+ |--------------------------------------------| |

84599

+ | FPR registers f1-f8 (optional) 8*8 | |

84600

+ |--------------------------------------------| | stack |

84601

+ | Space for copied structures | | grows |

84602

+ |--------------------------------------------| | down V

84603

+ | Parameters that didn't fit in registers | |

84604

+ |--------------------------------------------| | lower addresses

84605

+ | Space for callee's LR 4 | |

84606

+ |--------------------------------------------| | stack pointer here

84607

+ | Current backchain pointer 4 |-/ during

84608

+ |--------------------------------------------| <<< ffi_call_SYSV

84609

+

84610

+*/

84611

+

84612

+void FFI_HIDDEN

84613

+ffi_prep_args_SYSV (extended_cif *ecif, unsigned *const stack)

84614

+{

84615

+ const unsigned bytes = ecif->cif->bytes;

84616

+ const unsigned flags = ecif->cif->flags;

84617

+

84618

+ typedef union

84619

+ {

84620

+ char *c;

84621

+ unsigned *u;

84622

+ long long *ll;

84623

+ float *f;

84624

+ double *d;

84625

+ } valp;

84626

+

84627

+ /* 'stacktop' points at the previous backchain pointer. */

84628

+ valp stacktop;

84629

+

84630

+ /* 'gpr_base' points at the space for gpr3, and grows upwards as

84631

+ we use GPR registers. */

84632

+ valp gpr_base;

84633

+ int intarg_count;

84634

+

84635

+#ifndef __NO_FPRS__

84636

+ /* 'fpr_base' points at the space for fpr1, and grows upwards as

84637

+ we use FPR registers. */

84638

+ valp fpr_base;

84639

+ int fparg_count;

84640

+#endif

84641

+

84642

+ /* 'copy_space' grows down as we put structures in it. It should

84643

+ stay 16-byte aligned. */

84644

+ valp copy_space;

84645

+

84646

+ /* 'next_arg' grows up as we put parameters in it. */

84647

+ valp next_arg;

84648

+

84649

+ int i;

84650

+ ffi_type **ptr;

84651

+#ifndef __NO_FPRS__

84652

+ double double_tmp;

84653

+#endif

84654

+ union

84655

+ {

84656

+ void **v;

84657

+ char **c;

84658

+ signed char **sc;

84659

+ unsigned char **uc;

84660

+ signed short **ss;

84661

+ unsigned short **us;

84662

+ unsigned int **ui;

84663

+ long long **ll;

84664

+ float **f;

84665

+ double **d;

84666

+ } p_argv;

84667

+ size_t struct_copy_size;

84668

+ unsigned gprvalue;

84669

+

84670

+ stacktop.c = (char *) stack + bytes;

84671

+ gpr_base.u = stacktop.u - ASM_NEEDS_REGISTERS - NUM_GPR_ARG_REGISTERS;

84672

+ intarg_count = 0;

84673

+#ifndef __NO_FPRS__

84674

+ fpr_base.d = gpr_base.d - NUM_FPR_ARG_REGISTERS;

84675

+ fparg_count = 0;

84676

+ copy_space.c = ((flags & FLAG_FP_ARGUMENTS) ? fpr_base.c : gpr_base.c);

84677

+#else

84678

+ copy_space.c = gpr_base.c;

84679

+#endif

84680

+ next_arg.u = stack + 2;

84681

+

84682

+ /* Check that everything starts aligned properly. */

84683

+ FFI_ASSERT (((unsigned long) (char *) stack & 0xF) == 0);

84684

+ FFI_ASSERT (((unsigned long) copy_space.c & 0xF) == 0);

84685

+ FFI_ASSERT (((unsigned long) stacktop.c & 0xF) == 0);

84686

+ FFI_ASSERT ((bytes & 0xF) == 0);

84687

+ FFI_ASSERT (copy_space.c >= next_arg.c);

84688

+

84689

+ /* Deal with return values that are actually pass-by-reference. */

84690

+ if (flags & FLAG_RETVAL_REFERENCE)

84691

+ {

84692

+ *gpr_base.u++ = (unsigned long) (char *) ecif->rvalue;

84693

+ intarg_count++;

84694

+ }

84695

+

84696

+ /* Now for the arguments. */

84697

+ p_argv.v = ecif->avalue;

84698

+ for (ptr = ecif->cif->arg_types, i = ecif->cif->nargs;

84699

+ i > 0;

84700

+ i--, ptr++, p_argv.v++)

84701

+ {

84702

+ unsigned int typenum = (*ptr)->type;

84703

+

84704

+ typenum = translate_float (ecif->cif->abi, typenum);

84705

+

84706

+ /* Now test the translated value */

84707

+ switch (typenum)

84708

+ {

84709

+#ifndef __NO_FPRS__

84710

+# if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

84711

+ case FFI_TYPE_LONGDOUBLE:

84712

+ double_tmp = (*p_argv.d)[0];

84713

+

84714

+ if (fparg_count >= NUM_FPR_ARG_REGISTERS - 1)

84715

+ {

84716

+ if (intarg_count >= NUM_GPR_ARG_REGISTERS

84717

+ && intarg_count % 2 != 0)

84718

+ {

84719

+ intarg_count++;

84720

+ next_arg.u++;

84721

+ }

84722

+ *next_arg.d = double_tmp;

84723

+ next_arg.u += 2;

84724

+ double_tmp = (*p_argv.d)[1];

84725

+ *next_arg.d = double_tmp;

84726

+ next_arg.u += 2;

84727

+ }

84728

+ else

84729

+ {

84730

+ *fpr_base.d++ = double_tmp;

84731

+ double_tmp = (*p_argv.d)[1];

84732

+ *fpr_base.d++ = double_tmp;

84733

+ }

84734

+

84735

+ fparg_count += 2;

84736

+ FFI_ASSERT (flags & FLAG_FP_ARGUMENTS);

84737

+ break;

84738

+# endif

84739

+ case FFI_TYPE_DOUBLE:

84740

+ double_tmp = **p_argv.d;

84741

+

84742

+ if (fparg_count >= NUM_FPR_ARG_REGISTERS)

84743

+ {

84744

+ if (intarg_count >= NUM_GPR_ARG_REGISTERS

84745

+ && intarg_count % 2 != 0)

84746

+ {

84747

+ intarg_count++;

84748

+ next_arg.u++;

84749

+ }

84750

+ *next_arg.d = double_tmp;

84751

+ next_arg.u += 2;

84752

+ }

84753

+ else

84754

+ *fpr_base.d++ = double_tmp;

84755

+ fparg_count++;

84756

+ FFI_ASSERT (flags & FLAG_FP_ARGUMENTS);

84757

+ break;

84758

+

84759

+ case FFI_TYPE_FLOAT:

84760

+ double_tmp = **p_argv.f;

84761

+ if (fparg_count >= NUM_FPR_ARG_REGISTERS)

84762

+ {

84763

+ *next_arg.f = (float) double_tmp;

84764

+ next_arg.u += 1;

84765

+ intarg_count++;

84766

+ }

84767

+ else

84768

+ *fpr_base.d++ = double_tmp;

84769

+ fparg_count++;

84770

+ FFI_ASSERT (flags & FLAG_FP_ARGUMENTS);

84771

+ break;

84772

+#endif /* have FPRs */

84773

+

84774

+ case FFI_TYPE_UINT128:

84775

+ /* The soft float ABI for long doubles works like this, a long double

84776

+ is passed in four consecutive GPRs if available. A maximum of 2

84777

+ long doubles can be passed in gprs. If we do not have 4 GPRs

84778

+ left, the long double is passed on the stack, 4-byte aligned. */

84779

+ {

84780

+ unsigned int int_tmp;

84781

+ unsigned int ii;

84782

+ if (intarg_count >= NUM_GPR_ARG_REGISTERS - 3)

84783

+ {

84784

+ if (intarg_count < NUM_GPR_ARG_REGISTERS)

84785

+ intarg_count = NUM_GPR_ARG_REGISTERS;

84786

+ for (ii = 0; ii < 4; ii++)

84787

+ {

84788

+ int_tmp = (*p_argv.ui)[ii];

84789

+ *next_arg.u++ = int_tmp;

84790

+ }

84791

+ }

84792

+ else

84793

+ {

84794

+ for (ii = 0; ii < 4; ii++)

84795

+ {

84796

+ int_tmp = (*p_argv.ui)[ii];

84797

+ *gpr_base.u++ = int_tmp;

84798

+ }

84799

+ }

84800

+ intarg_count += 4;

84801

+ break;

84802

+ }

84803

+

84804

+ case FFI_TYPE_UINT64:

84805

+ case FFI_TYPE_SINT64:

84806

+ if (intarg_count == NUM_GPR_ARG_REGISTERS-1)

84807

+ intarg_count++;

84808

+ if (intarg_count >= NUM_GPR_ARG_REGISTERS)

84809

+ {

84810

+ if (intarg_count % 2 != 0)

84811

+ {

84812

+ intarg_count++;

84813

+ next_arg.u++;

84814

+ }

84815

+ *next_arg.ll = **p_argv.ll;

84816

+ next_arg.u += 2;

84817

+ }

84818

+ else

84819

+ {

84820

+ /* The abi states only certain register pairs can be

84821

+ used for passing long long int specifically (r3,r4),

84822

+ (r5,r6), (r7,r8), (r9,r10). If next arg is long long

84823

+ but not correct starting register of pair then skip

84824

+ until the proper starting register. */

84825

+ if (intarg_count % 2 != 0)

84826

+ {

84827

+ intarg_count ++;

84828

+ gpr_base.u++;

84829

+ }

84830

+ *gpr_base.ll++ = **p_argv.ll;

84831

+ }

84832

+ intarg_count += 2;

84833

+ break;

84834

+

84835

+ case FFI_TYPE_STRUCT:

84836

+ struct_copy_size = ((*ptr)->size + 15) & ~0xF;

84837

+ copy_space.c -= struct_copy_size;

84838

+ memcpy (copy_space.c, *p_argv.c, (*ptr)->size);

84839

+

84840

+ gprvalue = (unsigned long) copy_space.c;

84841

+

84842

+ FFI_ASSERT (copy_space.c > next_arg.c);

84843

+ FFI_ASSERT (flags & FLAG_ARG_NEEDS_COPY);

84844

+ goto putgpr;

84845

+

84846

+ case FFI_TYPE_UINT8:

84847

+ gprvalue = **p_argv.uc;

84848

+ goto putgpr;

84849

+ case FFI_TYPE_SINT8:

84850

+ gprvalue = **p_argv.sc;

84851

+ goto putgpr;

84852

+ case FFI_TYPE_UINT16:

84853

+ gprvalue = **p_argv.us;

84854

+ goto putgpr;

84855

+ case FFI_TYPE_SINT16:

84856

+ gprvalue = **p_argv.ss;

84857

+ goto putgpr;

84858

+

84859

+ case FFI_TYPE_INT:

84860

+ case FFI_TYPE_UINT32:

84861

+ case FFI_TYPE_SINT32:

84862

+ case FFI_TYPE_POINTER:

84863

+

84864

+ gprvalue = **p_argv.ui;

84865

+

84866

+ putgpr:

84867

+ if (intarg_count >= NUM_GPR_ARG_REGISTERS)

84868

+ *next_arg.u++ = gprvalue;

84869

+ else

84870

+ *gpr_base.u++ = gprvalue;

84871

+ intarg_count++;

84872

+ break;

84873

+ }

84874

+ }

84875

+

84876

+ /* Check that we didn't overrun the stack... */

84877

+ FFI_ASSERT (copy_space.c >= next_arg.c);

84878

+ FFI_ASSERT (gpr_base.u <= stacktop.u - ASM_NEEDS_REGISTERS);

84879

+ /* The assert below is testing that the number of integer arguments agrees

84880

+ with the number found in ffi_prep_cif_machdep(). However, intarg_count

84881

+ is incremented whenever we place an FP arg on the stack, so account for

84882

+ that before our assert test. */

84883

+#ifndef __NO_FPRS__

84884

+ if (fparg_count > NUM_FPR_ARG_REGISTERS)

84885

+ intarg_count -= fparg_count - NUM_FPR_ARG_REGISTERS;

84886

+ FFI_ASSERT (fpr_base.u

84887

+ <= stacktop.u - ASM_NEEDS_REGISTERS - NUM_GPR_ARG_REGISTERS);

84888

+#endif

84889

+ FFI_ASSERT (flags & FLAG_4_GPR_ARGUMENTS || intarg_count <= 4);

84890

+}

84891

+

84892

+#define MIN_CACHE_LINE_SIZE 8

84893

+

84894

+static void

84895

+flush_icache (char *wraddr, char *xaddr, int size)

84896

+{

84897

+ int i;

84898

+ for (i = 0; i < size; i += MIN_CACHE_LINE_SIZE)

84899

+ __asm__ volatile ("icbi 0,%0;" "dcbf 0,%1;"

84900

+ : : "r" (xaddr + i), "r" (wraddr + i) : "memory");

84901

+ __asm__ volatile ("icbi 0,%0;" "dcbf 0,%1;" "sync;" "isync;"

84902

+ : : "r"(xaddr + size - 1), "r"(wraddr + size - 1)

84903

+ : "memory");

84904

+}

84905

+

84906

+ffi_status FFI_HIDDEN

84907

+ffi_prep_closure_loc_sysv (ffi_closure *closure,

84908

+ ffi_cif *cif,

84909

+ void (*fun) (ffi_cif *, void *, void **, void *),

84910

+ void *user_data,

84911

+ void *codeloc)

84912

+{

84913

+ unsigned int *tramp;

84914

+

84915

+ if (cif->abi < FFI_SYSV || cif->abi >= FFI_LAST_ABI)

84916

+ return FFI_BAD_ABI;

84917

+

84918

+ tramp = (unsigned int *) &closure->tramp[0];

84919

+ tramp[0] = 0x7c0802a6; /* mflr r0 */

84920

+ tramp[1] = 0x4800000d; /* bl 10 <trampoline_initial+0x10> */

84921

+ tramp[4] = 0x7d6802a6; /* mflr r11 */

84922

+ tramp[5] = 0x7c0803a6; /* mtlr r0 */

84923

+ tramp[6] = 0x800b0000; /* lwz r0,0(r11) */

84924

+ tramp[7] = 0x816b0004; /* lwz r11,4(r11) */

84925

+ tramp[8] = 0x7c0903a6; /* mtctr r0 */

84926

+ tramp[9] = 0x4e800420; /* bctr */

84927

+ *(void **) &tramp[2] = (void *) ffi_closure_SYSV; /* function */

84928

+ *(void **) &tramp[3] = codeloc; /* context */

84929

+

84930

+ /* Flush the icache. */

84931

+ flush_icache ((char *)tramp, (char *)codeloc, FFI_TRAMPOLINE_SIZE);

84932

+

84933

+ closure->cif = cif;

84934

+ closure->fun = fun;

84935

+ closure->user_data = user_data;

84936

+

84937

+ return FFI_OK;

84938

+}

84939

+

84940

+/* Basically the trampoline invokes ffi_closure_SYSV, and on

84941

+ entry, r11 holds the address of the closure.

84942

+ After storing the registers that could possibly contain

84943

+ parameters to be passed into the stack frame and setting

84944

+ up space for a return value, ffi_closure_SYSV invokes the

84945

+ following helper function to do most of the work. */

84946

+

84947

+int

84948

+ffi_closure_helper_SYSV (ffi_closure *closure, void *rvalue,

84949

+ unsigned long *pgr, ffi_dblfl *pfr,

84950

+ unsigned long *pst)

84951

+{

84952

+ /* rvalue is the pointer to space for return value in closure assembly */

84953

+ /* pgr is the pointer to where r3-r10 are stored in ffi_closure_SYSV */

84954

+ /* pfr is the pointer to where f1-f8 are stored in ffi_closure_SYSV */

84955

+ /* pst is the pointer to outgoing parameter stack in original caller */

84956

+

84957

+ void ** avalue;

84958

+ ffi_type ** arg_types;

84959

+ long i, avn;

84960

+#ifndef __NO_FPRS__

84961

+ long nf = 0; /* number of floating registers already used */

84962

+#endif

84963

+ long ng = 0; /* number of general registers already used */

84964

+

84965

+ ffi_cif *cif = closure->cif;

84966

+ unsigned size = cif->rtype->size;

84967

+ unsigned short rtypenum = cif->rtype->type;

84968

+

84969

+ avalue = alloca (cif->nargs * sizeof (void *));

84970

+

84971

+ /* First translate for softfloat/nonlinux */

84972

+ rtypenum = translate_float (cif->abi, rtypenum);

84973

+

84974

+ /* Copy the caller's structure return value address so that the closure

84975

+ returns the data directly to the caller.

84976

+ For FFI_SYSV the result is passed in r3/r4 if the struct size is less

84977

+ or equal 8 bytes. */

84978

+ if (rtypenum == FFI_TYPE_STRUCT

84979

+ && !((cif->abi & FFI_SYSV_STRUCT_RET) != 0 && size <= 8))

84980

+ {

84981

+ rvalue = (void *) *pgr;

84982

+ ng++;

84983

+ pgr++;

84984

+ }

84985

+

84986

+ i = 0;

84987

+ avn = cif->nargs;

84988

+ arg_types = cif->arg_types;

84989

+

84990

+ /* Grab the addresses of the arguments from the stack frame. */

84991

+ while (i < avn) {

84992

+ unsigned short typenum = arg_types[i]->type;

84993

+

84994

+ /* We may need to handle some values depending on ABI. */

84995

+ typenum = translate_float (cif->abi, typenum);

84996

+

84997

+ switch (typenum)

84998

+ {

84999

+#ifndef __NO_FPRS__

85000

+ case FFI_TYPE_FLOAT:

85001

+ /* Unfortunately float values are stored as doubles

85002

+ in the ffi_closure_SYSV code (since we don't check

85003

+ the type in that routine). */

85004

+ if (nf < NUM_FPR_ARG_REGISTERS)

85005

+ {

85006

+ /* FIXME? here we are really changing the values

85007

+ stored in the original calling routines outgoing

85008

+ parameter stack. This is probably a really

85009

+ naughty thing to do but... */

85010

+ double temp = pfr->d;

85011

+ pfr->f = (float) temp;

85012

+ avalue[i] = pfr;

85013

+ nf++;

85014

+ pfr++;

85015

+ }

85016

+ else

85017

+ {

85018

+ avalue[i] = pst;

85019

+ pst += 1;

85020

+ }

85021

+ break;

85022

+

85023

+ case FFI_TYPE_DOUBLE:

85024

+ if (nf < NUM_FPR_ARG_REGISTERS)

85025

+ {

85026

+ avalue[i] = pfr;

85027

+ nf++;

85028

+ pfr++;

85029

+ }

85030

+ else

85031

+ {

85032

+ if (((long) pst) & 4)

85033

+ pst++;

85034

+ avalue[i] = pst;

85035

+ pst += 2;

85036

+ }

85037

+ break;

85038

+

85039

+# if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

85040

+ case FFI_TYPE_LONGDOUBLE:

85041

+ if (nf < NUM_FPR_ARG_REGISTERS - 1)

85042

+ {

85043

+ avalue[i] = pfr;

85044

+ pfr += 2;

85045

+ nf += 2;

85046

+ }

85047

+ else

85048

+ {

85049

+ if (((long) pst) & 4)

85050

+ pst++;

85051

+ avalue[i] = pst;

85052

+ pst += 4;

85053

+ nf = 8;

85054

+ }

85055

+ break;

85056

+# endif

85057

+#endif

85058

+

85059

+ case FFI_TYPE_UINT128:

85060

+ /* Test if for the whole long double, 4 gprs are available.

85061

+ otherwise the stuff ends up on the stack. */

85062

+ if (ng < NUM_GPR_ARG_REGISTERS - 3)

85063

+ {

85064

+ avalue[i] = pgr;

85065

+ pgr += 4;

85066

+ ng += 4;

85067

+ }

85068

+ else

85069

+ {

85070

+ avalue[i] = pst;

85071

+ pst += 4;

85072

+ ng = 8+4;

85073

+ }

85074

+ break;

85075

+

85076

+ case FFI_TYPE_SINT8:

85077

+ case FFI_TYPE_UINT8:

85078

+#ifndef __LITTLE_ENDIAN__

85079

+ if (ng < NUM_GPR_ARG_REGISTERS)

85080

+ {

85081

+ avalue[i] = (char *) pgr + 3;

85082

+ ng++;

85083

+ pgr++;

85084

+ }

85085

+ else

85086

+ {

85087

+ avalue[i] = (char *) pst + 3;

85088

+ pst++;

85089

+ }

85090

+ break;

85091

+#endif

85092

+

85093

+ case FFI_TYPE_SINT16:

85094

+ case FFI_TYPE_UINT16:

85095

+#ifndef __LITTLE_ENDIAN__

85096

+ if (ng < NUM_GPR_ARG_REGISTERS)

85097

+ {

85098

+ avalue[i] = (char *) pgr + 2;

85099

+ ng++;

85100

+ pgr++;

85101

+ }

85102

+ else

85103

+ {

85104

+ avalue[i] = (char *) pst + 2;

85105

+ pst++;

85106

+ }

85107

+ break;

85108

+#endif

85109

+

85110

+ case FFI_TYPE_SINT32:

85111

+ case FFI_TYPE_UINT32:

85112

+ case FFI_TYPE_POINTER:

85113

+ if (ng < NUM_GPR_ARG_REGISTERS)

85114

+ {

85115

+ avalue[i] = pgr;

85116

+ ng++;

85117

+ pgr++;

85118

+ }

85119

+ else

85120

+ {

85121

+ avalue[i] = pst;

85122

+ pst++;

85123

+ }

85124

+ break;

85125

+

85126

+ case FFI_TYPE_STRUCT:

85127

+ /* Structs are passed by reference. The address will appear in a

85128

+ gpr if it is one of the first 8 arguments. */

85129

+ if (ng < NUM_GPR_ARG_REGISTERS)

85130

+ {

85131

+ avalue[i] = (void *) *pgr;

85132

+ ng++;

85133

+ pgr++;

85134

+ }

85135

+ else

85136

+ {

85137

+ avalue[i] = (void *) *pst;

85138

+ pst++;

85139

+ }

85140

+ break;

85141

+

85142

+ case FFI_TYPE_SINT64:

85143

+ case FFI_TYPE_UINT64:

85144

+ /* Passing long long ints are complex, they must

85145

+ be passed in suitable register pairs such as

85146

+ (r3,r4) or (r5,r6) or (r6,r7), or (r7,r8) or (r9,r10)

85147

+ and if the entire pair aren't available then the outgoing

85148

+ parameter stack is used for both but an alignment of 8

85149

+ must will be kept. So we must either look in pgr

85150

+ or pst to find the correct address for this type

85151

+ of parameter. */

85152

+ if (ng < NUM_GPR_ARG_REGISTERS - 1)

85153

+ {

85154

+ if (ng & 1)

85155

+ {

85156

+ /* skip r4, r6, r8 as starting points */

85157

+ ng++;

85158

+ pgr++;

85159

+ }

85160

+ avalue[i] = pgr;

85161

+ ng += 2;

85162

+ pgr += 2;

85163

+ }

85164

+ else

85165

+ {

85166

+ if (((long) pst) & 4)

85167

+ pst++;

85168

+ avalue[i] = pst;

85169

+ pst += 2;

85170

+ ng = NUM_GPR_ARG_REGISTERS;

85171

+ }

85172

+ break;

85173

+

85174

+ default:

85175

+ FFI_ASSERT (0);

85176

+ }

85177

+

85178

+ i++;

85179

+ }

85180

+

85181

+ (closure->fun) (cif, rvalue, avalue, closure->user_data);

85182

+

85183

+ /* Tell ffi_closure_SYSV how to perform return type promotions.

85184

+ Because the FFI_SYSV ABI returns the structures <= 8 bytes in

85185

+ r3/r4 we have to tell ffi_closure_SYSV how to treat them. We

85186

+ combine the base type FFI_SYSV_TYPE_SMALL_STRUCT with the size of

85187

+ the struct less one. We never have a struct with size zero.

85188

+ See the comment in ffitarget.h about ordering. */

85189

+ if (rtypenum == FFI_TYPE_STRUCT

85190

+ && (cif->abi & FFI_SYSV_STRUCT_RET) != 0 && size <= 8)

85191

+ return FFI_SYSV_TYPE_SMALL_STRUCT - 1 + size;

85192

+ return rtypenum;

85193

+}

85194

+#endif

85195

Index: libffi/src/powerpc/linux64.S

85196

===================================================================

85197

--- a/src/libffi/src/powerpc/linux64.S (.../tags/gcc_4_8_2_release)

85198

+++ b/src/libffi/src/powerpc/linux64.S (.../branches/gcc-4_8-branch)

85199

@@ -29,18 +29,25 @@

85200

#include <fficonfig.h>

85201

#include <ffi.h>

85202

85203

-#ifdef __powerpc64__

85204

+#ifdef POWERPC64

85205

.hidden ffi_call_LINUX64

85206

.globl ffi_call_LINUX64

85207

+# if _CALL_ELF == 2

85208

+ .text

85209

+ffi_call_LINUX64:

85210

+ addis %r2, %r12, .TOC.-ffi_call_LINUX64@ha

85211

+ addi %r2, %r2, .TOC.-ffi_call_LINUX64@l

85212

+ .localentry ffi_call_LINUX64, . - ffi_call_LINUX64

85213

+# else

85214

.section ".opd","aw"

85215

.align 3

85216

ffi_call_LINUX64:

85217

-#ifdef _CALL_LINUX

85218

+# ifdef _CALL_LINUX

85219

.quad .L.ffi_call_LINUX64,.TOC.@tocbase,0

85220

.type ffi_call_LINUX64,@function

85221

.text

85222

.L.ffi_call_LINUX64:

85223

-#else

85224

+# else

85225

.hidden .ffi_call_LINUX64

85226

.globl .ffi_call_LINUX64

85227

.quad .ffi_call_LINUX64,.TOC.@tocbase,0

85228

@@ -48,7 +55,8 @@

85229

.type .ffi_call_LINUX64,@function

85230

.text

85231

.ffi_call_LINUX64:

85232

-#endif

85233

+# endif

85234

+# endif

85235

.LFB1:

85236

mflr %r0

85237

std %r28, -32(%r1)

85238

@@ -63,26 +71,35 @@

85239

mr %r31, %r5 /* flags, */

85240

mr %r30, %r6 /* rvalue, */

85241

mr %r29, %r7 /* function address. */

85242

+/* Save toc pointer, not for the ffi_prep_args64 call, but for the later

85243

+ bctrl function call. */

85244

+# if _CALL_ELF == 2

85245

+ std %r2, 24(%r1)

85246

+# else

85247

std %r2, 40(%r1)

85248

+# endif

85249

85250

/* Call ffi_prep_args64. */

85251

mr %r4, %r1

85252

-#ifdef _CALL_LINUX

85253

+# if defined _CALL_LINUX || _CALL_ELF == 2

85254

bl ffi_prep_args64

85255

-#else

85256

+# else

85257

bl .ffi_prep_args64

85258

-#endif

85259

+# endif

85260

85261

- ld %r0, 0(%r29)

85262

+# if _CALL_ELF == 2

85263

+ mr %r12, %r29

85264

+# else

85265

+ ld %r12, 0(%r29)

85266

ld %r2, 8(%r29)

85267

ld %r11, 16(%r29)

85268

-

85269

+# endif

85270

/* Now do the call. */

85271

/* Set up cr1 with bits 4-7 of the flags. */

85272

mtcrf 0x40, %r31

85273

85274

/* Get the address to call into CTR. */

85275

- mtctr %r0

85276

+ mtctr %r12

85277

/* Load all those argument registers. */

85278

ld %r3, -32-(8*8)(%r28)

85279

ld %r4, -32-(7*8)(%r28)

85280

@@ -117,12 +134,17 @@

85281

85282

/* This must follow the call immediately, the unwinder

85283

uses this to find out if r2 has been saved or not. */

85284

+# if _CALL_ELF == 2

85285

+ ld %r2, 24(%r1)

85286

+# else

85287

ld %r2, 40(%r1)

85288

+# endif

85289

85290

/* Now, deal with the return value. */

85291

mtcrf 0x01, %r31

85292

- bt- 30, .Ldone_return_value

85293

- bt- 29, .Lfp_return_value

85294

+ bt 31, .Lstruct_return_value

85295

+ bt 30, .Ldone_return_value

85296

+ bt 29, .Lfp_return_value

85297

std %r3, 0(%r30)

85298

/* Fall through... */

85299

85300

@@ -130,7 +152,7 @@

85301

/* Restore the registers we used and return. */

85302

mr %r1, %r28

85303

ld %r0, 16(%r28)

85304

- ld %r28, -32(%r1)

85305

+ ld %r28, -32(%r28)

85306

mtlr %r0

85307

ld %r29, -24(%r1)

85308

ld %r30, -16(%r1)

85309

@@ -147,14 +169,48 @@

85310

.Lfloat_return_value:

85311

stfs %f1, 0(%r30)

85312

b .Ldone_return_value

85313

+

85314

+.Lstruct_return_value:

85315

+ bf 29, .Lsmall_struct

85316

+ bf 28, .Lfloat_homog_return_value

85317

+ stfd %f1, 0(%r30)

85318

+ stfd %f2, 8(%r30)

85319

+ stfd %f3, 16(%r30)

85320

+ stfd %f4, 24(%r30)

85321

+ stfd %f5, 32(%r30)

85322

+ stfd %f6, 40(%r30)

85323

+ stfd %f7, 48(%r30)

85324

+ stfd %f8, 56(%r30)

85325

+ b .Ldone_return_value

85326

+

85327

+.Lfloat_homog_return_value:

85328

+ stfs %f1, 0(%r30)

85329

+ stfs %f2, 4(%r30)

85330

+ stfs %f3, 8(%r30)

85331

+ stfs %f4, 12(%r30)

85332

+ stfs %f5, 16(%r30)

85333

+ stfs %f6, 20(%r30)

85334

+ stfs %f7, 24(%r30)

85335

+ stfs %f8, 28(%r30)

85336

+ b .Ldone_return_value

85337

+

85338

+.Lsmall_struct:

85339

+ std %r3, 0(%r30)

85340

+ std %r4, 8(%r30)

85341

+ b .Ldone_return_value

85342

+

85343

.LFE1:

85344

.long 0

85345

.byte 0,12,0,1,128,4,0,0

85346

-#ifdef _CALL_LINUX

85347

+# if _CALL_ELF == 2

85348

+ .size ffi_call_LINUX64,.-ffi_call_LINUX64

85349

+# else

85350

+# ifdef _CALL_LINUX

85351

.size ffi_call_LINUX64,.-.L.ffi_call_LINUX64

85352

-#else

85353

+# else

85354

.size .ffi_call_LINUX64,.-.ffi_call_LINUX64

85355

-#endif

85356

+# endif

85357

+# endif

85358

85359

.section .eh_frame,EH_FRAME_FLAGS,@progbits

85360

.Lframe1:

85361

@@ -197,8 +253,8 @@

85362

.uleb128 0x4

85363

.align 3

85364

.LEFDE1:

85365

-#endif

85366

85367

-#if defined __ELF__ && defined __linux__

85368

+# if (defined __ELF__ && defined __linux__) || _CALL_ELF == 2

85369

.section .note.GNU-stack,"",@progbits

85370

+# endif

85371

#endif

85372

Index: libffi/src/powerpc/ffi_linux64.c

85373

===================================================================

85374

--- a/src/libffi/src/powerpc/ffi_linux64.c (.../tags/gcc_4_8_2_release)

85375

+++ b/src/libffi/src/powerpc/ffi_linux64.c (.../branches/gcc-4_8-branch)

85376

@@ -0,0 +1,942 @@

85377

+/* -----------------------------------------------------------------------

85378

85379

85380

85381

85382

85383

85384

+

85385

+ PowerPC Foreign Function Interface

85386

+

85387

+ Permission is hereby granted, free of charge, to any person obtaining

85388

+ a copy of this software and associated documentation files (the

85389

+ ``Software''), to deal in the Software without restriction, including

85390

+ without limitation the rights to use, copy, modify, merge, publish,

85391

+ distribute, sublicense, and/or sell copies of the Software, and to

85392

+ permit persons to whom the Software is furnished to do so, subject to

85393

+ the following conditions:

85394

+

85395

+ The above copyright notice and this permission notice shall be included

85396

+ in all copies or substantial portions of the Software.

85397

+

85398

+ THE SOFTWARE IS PROVIDED ``AS IS'', WITHOUT WARRANTY OF ANY KIND, EXPRESS

85399

+ OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

85400

+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.

85401

+ IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR

85402

+ OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

85403

+ ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

85404

+ OTHER DEALINGS IN THE SOFTWARE.

85405

+ ----------------------------------------------------------------------- */

85406

+

85407

+#include "ffi.h"

85408

+

85409

+#ifdef POWERPC64

85410

+#include "ffi_common.h"

85411

+#include "ffi_powerpc.h"

85412

+

85413

+

85414

+/* About the LINUX64 ABI. */

85415

+enum {

85416

+ NUM_GPR_ARG_REGISTERS64 = 8,

85417

+ NUM_FPR_ARG_REGISTERS64 = 13

85418

+};

85419

+enum { ASM_NEEDS_REGISTERS64 = 4 };

85420

+

85421

+

85422

+#if HAVE_LONG_DOUBLE_VARIANT && FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

85423

+/* Adjust size of ffi_type_longdouble. */

85424

+void FFI_HIDDEN

85425

+ffi_prep_types_linux64 (ffi_abi abi)

85426

+{

85427

+ if ((abi & (FFI_LINUX | FFI_LINUX_LONG_DOUBLE_128)) == FFI_LINUX)

85428

+ {

85429

+ ffi_type_longdouble.size = 8;

85430

+ ffi_type_longdouble.alignment = 8;

85431

+ }

85432

+ else

85433

+ {

85434

+ ffi_type_longdouble.size = 16;

85435

+ ffi_type_longdouble.alignment = 16;

85436

+ }

85437

+}

85438

+#endif

85439

+

85440

+

85441

+#if _CALL_ELF == 2

85442

+static unsigned int

85443

+discover_homogeneous_aggregate (const ffi_type *t, unsigned int *elnum)

85444

+{

85445

+ switch (t->type)

85446

+ {

85447

+ case FFI_TYPE_FLOAT:

85448

+ case FFI_TYPE_DOUBLE:

85449

+ *elnum = 1;

85450

+ return (int) t->type;

85451

+

85452

+ case FFI_TYPE_STRUCT:;

85453

+ {

85454

+ unsigned int base_elt = 0, total_elnum = 0;

85455

+ ffi_type **el = t->elements;

85456

+ while (*el)

85457

+ {

85458

+ unsigned int el_elt, el_elnum = 0;

85459

+ el_elt = discover_homogeneous_aggregate (*el, &el_elnum);

85460

+ if (el_elt == 0

85461

+ || (base_elt && base_elt != el_elt))

85462

+ return 0;

85463

+ base_elt = el_elt;

85464

+ total_elnum += el_elnum;

85465

+ if (total_elnum > 8)

85466

+ return 0;

85467

+ el++;

85468

+ }

85469

+ *elnum = total_elnum;

85470

+ return base_elt;

85471

+ }

85472

+

85473

+ default:

85474

+ return 0;

85475

+ }

85476

+}

85477

+#endif

85478

+

85479

+

85480

+/* Perform machine dependent cif processing */

85481

+static ffi_status

85482

+ffi_prep_cif_linux64_core (ffi_cif *cif)

85483

+{

85484

+ ffi_type **ptr;

85485

+ unsigned bytes;

85486

+ unsigned i, fparg_count = 0, intarg_count = 0;

85487

+ unsigned flags = cif->flags;

85488

+#if _CALL_ELF == 2

85489

+ unsigned int elt, elnum;

85490

+#endif

85491

+

85492

+#if FFI_TYPE_LONGDOUBLE == FFI_TYPE_DOUBLE

85493

+ /* If compiled without long double support.. */

85494

+ if ((cif->abi & FFI_LINUX_LONG_DOUBLE_128) != 0)

85495

+ return FFI_BAD_ABI;

85496

+#endif

85497

+

85498

+ /* The machine-independent calculation of cif->bytes doesn't work

85499

+ for us. Redo the calculation. */

85500

+#if _CALL_ELF == 2

85501

+ /* Space for backchain, CR, LR, TOC and the asm's temp regs. */

85502

+ bytes = (4 + ASM_NEEDS_REGISTERS64) * sizeof (long);

85503

+

85504

+ /* Space for the general registers. */

85505

+ bytes += NUM_GPR_ARG_REGISTERS64 * sizeof (long);

85506

+#else

85507

+ /* Space for backchain, CR, LR, cc/ld doubleword, TOC and the asm's temp

85508

+ regs. */

85509

+ bytes = (6 + ASM_NEEDS_REGISTERS64) * sizeof (long);

85510

+

85511

+ /* Space for the mandatory parm save area and general registers. */

85512

+ bytes += 2 * NUM_GPR_ARG_REGISTERS64 * sizeof (long);

85513

+#endif

85514

+

85515

+ /* Return value handling. */

85516

+ switch (cif->rtype->type)

85517

+ {

85518

+#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

85519

+ case FFI_TYPE_LONGDOUBLE:

85520

+ if ((cif->abi & FFI_LINUX_LONG_DOUBLE_128) != 0)

85521

+ flags |= FLAG_RETURNS_128BITS;

85522

+ /* Fall through. */

85523

+#endif

85524

+ case FFI_TYPE_DOUBLE:

85525

+ flags |= FLAG_RETURNS_64BITS;

85526

+ /* Fall through. */

85527

+ case FFI_TYPE_FLOAT:

85528

+ flags |= FLAG_RETURNS_FP;

85529

+ break;

85530

+

85531

+ case FFI_TYPE_UINT128:

85532

+ flags |= FLAG_RETURNS_128BITS;

85533

+ /* Fall through. */

85534

+ case FFI_TYPE_UINT64:

85535

+ case FFI_TYPE_SINT64:

85536

+ flags |= FLAG_RETURNS_64BITS;

85537

+ break;

85538

+

85539

+ case FFI_TYPE_STRUCT:

85540

+#if _CALL_ELF == 2

85541

+ elt = discover_homogeneous_aggregate (cif->rtype, &elnum);

85542

+ if (elt)

85543

+ {

85544

+ if (elt == FFI_TYPE_DOUBLE)

85545

+ flags |= FLAG_RETURNS_64BITS;

85546

+ flags |= FLAG_RETURNS_FP | FLAG_RETURNS_SMST;

85547

+ break;

85548

+ }

85549

+ if (cif->rtype->size <= 16)

85550

+ {

85551

+ flags |= FLAG_RETURNS_SMST;

85552

+ break;

85553

+ }

85554

+#endif

85555

+ intarg_count++;

85556

+ flags |= FLAG_RETVAL_REFERENCE;

85557

+ /* Fall through. */

85558

+ case FFI_TYPE_VOID:

85559

+ flags |= FLAG_RETURNS_NOTHING;

85560

+ break;

85561

+

85562

+ default:

85563

+ /* Returns 32-bit integer, or similar. Nothing to do here. */

85564

+ break;

85565

+ }

85566

+

85567

+ for (ptr = cif->arg_types, i = cif->nargs; i > 0; i--, ptr++)

85568

+ {

85569

+ unsigned int align;

85570

+

85571

+ switch ((*ptr)->type)

85572

+ {

85573

+#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

85574

+ case FFI_TYPE_LONGDOUBLE:

85575

+ if ((cif->abi & FFI_LINUX_LONG_DOUBLE_128) != 0)

85576

+ {

85577

+ fparg_count++;

85578

+ intarg_count++;

85579

+ }

85580

+ /* Fall through. */

85581

+#endif

85582

+ case FFI_TYPE_DOUBLE:

85583

+ case FFI_TYPE_FLOAT:

85584

+ fparg_count++;

85585

+ intarg_count++;

85586

+ if (fparg_count > NUM_FPR_ARG_REGISTERS64)

85587

+ flags |= FLAG_ARG_NEEDS_PSAVE;

85588

+ break;

85589

+

85590

+ case FFI_TYPE_STRUCT:

85591

+ if ((cif->abi & FFI_LINUX_STRUCT_ALIGN) != 0)

85592

+ {

85593

+ align = (*ptr)->alignment;

85594

+ if (align > 16)

85595

+ align = 16;

85596

+ align = align / 8;

85597

+ if (align > 1)

85598

+ intarg_count = ALIGN (intarg_count, align);

85599

+ }

85600

+ intarg_count += ((*ptr)->size + 7) / 8;

85601

+#if _CALL_ELF == 2

85602

+ elt = discover_homogeneous_aggregate (*ptr, &elnum);

85603

+ if (elt)

85604

+ {

85605

+ fparg_count += elnum;

85606

+ if (fparg_count > NUM_FPR_ARG_REGISTERS64)

85607

+ flags |= FLAG_ARG_NEEDS_PSAVE;

85608

+ }

85609

+ else

85610

+#endif

85611

+ {

85612

+ if (intarg_count > NUM_GPR_ARG_REGISTERS64)

85613

+ flags |= FLAG_ARG_NEEDS_PSAVE;

85614

+ }

85615

+ break;

85616

+

85617

+ case FFI_TYPE_POINTER:

85618

+ case FFI_TYPE_UINT64:

85619

+ case FFI_TYPE_SINT64:

85620

+ case FFI_TYPE_INT:

85621

+ case FFI_TYPE_UINT32:

85622

+ case FFI_TYPE_SINT32:

85623

+ case FFI_TYPE_UINT16:

85624

+ case FFI_TYPE_SINT16:

85625

+ case FFI_TYPE_UINT8:

85626

+ case FFI_TYPE_SINT8:

85627

+ /* Everything else is passed as a 8-byte word in a GPR, either

85628

+ the object itself or a pointer to it. */

85629

+ intarg_count++;

85630

+ if (intarg_count > NUM_GPR_ARG_REGISTERS64)

85631

+ flags |= FLAG_ARG_NEEDS_PSAVE;

85632

+ break;

85633

+ default:

85634

+ FFI_ASSERT (0);

85635

+ }

85636

+ }

85637

+

85638

+ if (fparg_count != 0)

85639

+ flags |= FLAG_FP_ARGUMENTS;

85640

+ if (intarg_count > 4)

85641

+ flags |= FLAG_4_GPR_ARGUMENTS;

85642

+

85643

+ /* Space for the FPR registers, if needed. */

85644

+ if (fparg_count != 0)

85645

+ bytes += NUM_FPR_ARG_REGISTERS64 * sizeof (double);

85646

+

85647

+ /* Stack space. */

85648

+#if _CALL_ELF == 2

85649

+ if ((flags & FLAG_ARG_NEEDS_PSAVE) != 0)

85650

+ bytes += intarg_count * sizeof (long);

85651

+#else

85652

+ if (intarg_count > NUM_GPR_ARG_REGISTERS64)

85653

+ bytes += (intarg_count - NUM_GPR_ARG_REGISTERS64) * sizeof (long);

85654

+#endif

85655

+

85656

+ /* The stack space allocated needs to be a multiple of 16 bytes. */

85657

+ bytes = (bytes + 15) & ~0xF;

85658

+

85659

+ cif->flags = flags;

85660

+ cif->bytes = bytes;

85661

+

85662

+ return FFI_OK;

85663

+}

85664

+

85665

+ffi_status FFI_HIDDEN

85666

+ffi_prep_cif_linux64 (ffi_cif *cif)

85667

+{

85668

+ if ((cif->abi & FFI_LINUX) != 0)

85669

+ cif->nfixedargs = cif->nargs;

85670

+#if _CALL_ELF != 2

85671

+ else if (cif->abi == FFI_COMPAT_LINUX64)

85672

+ {

85673

+ /* This call is from old code. Don't touch cif->nfixedargs

85674

+ since old code will be using a smaller cif. */

85675

+ cif->flags |= FLAG_COMPAT;

85676

+ /* Translate to new abi value. */

85677

+ cif->abi = FFI_LINUX | FFI_LINUX_LONG_DOUBLE_128;

85678

+ }

85679

+#endif

85680

+ else

85681

+ return FFI_BAD_ABI;

85682

+ return ffi_prep_cif_linux64_core (cif);

85683

+}

85684

+

85685

+ffi_status FFI_HIDDEN

85686

+ffi_prep_cif_linux64_var (ffi_cif *cif,

85687

+ unsigned int nfixedargs,

85688

+ unsigned int ntotalargs MAYBE_UNUSED)

85689

+{

85690

+ if ((cif->abi & FFI_LINUX) != 0)

85691

+ cif->nfixedargs = nfixedargs;

85692

+#if _CALL_ELF != 2

85693

+ else if (cif->abi == FFI_COMPAT_LINUX64)

85694

+ {

85695

+ /* This call is from old code. Don't touch cif->nfixedargs

85696

+ since old code will be using a smaller cif. */

85697

+ cif->flags |= FLAG_COMPAT;

85698

+ /* Translate to new abi value. */

85699

+ cif->abi = FFI_LINUX | FFI_LINUX_LONG_DOUBLE_128;

85700

+ }

85701

+#endif

85702

+ else

85703

+ return FFI_BAD_ABI;

85704

+#if _CALL_ELF == 2

85705

+ cif->flags |= FLAG_ARG_NEEDS_PSAVE;

85706

+#endif

85707

+ return ffi_prep_cif_linux64_core (cif);

85708

+}

85709

+

85710

+

85711

+/* ffi_prep_args64 is called by the assembly routine once stack space

85712

+ has been allocated for the function's arguments.

85713

+

85714

+ The stack layout we want looks like this:

85715

+

85716

+ | Ret addr from ffi_call_LINUX64 8bytes | higher addresses

85717

+ |--------------------------------------------|

85718

+ | CR save area 8bytes |

85719

+ |--------------------------------------------|

85720

+ | Previous backchain pointer 8 | stack pointer here

85721

+ |--------------------------------------------|<+ <<< on entry to

85722

+ | Saved r28-r31 4*8 | | ffi_call_LINUX64

85723

+ |--------------------------------------------| |

85724

+ | GPR registers r3-r10 8*8 | |

85725

+ |--------------------------------------------| |

85726

+ | FPR registers f1-f13 (optional) 13*8 | |

85727

+ |--------------------------------------------| |

85728

+ | Parameter save area | |

85729

+ |--------------------------------------------| |

85730

+ | TOC save area 8 | |

85731

+ |--------------------------------------------| | stack |

85732

+ | Linker doubleword 8 | | grows |

85733

+ |--------------------------------------------| | down V

85734

+ | Compiler doubleword 8 | |

85735

+ |--------------------------------------------| | lower addresses

85736

+ | Space for callee's LR 8 | |

85737

+ |--------------------------------------------| |

85738

+ | CR save area 8 | |

85739

+ |--------------------------------------------| | stack pointer here

85740

+ | Current backchain pointer 8 |-/ during

85741

+ |--------------------------------------------| <<< ffi_call_LINUX64

85742

+

85743

+*/

85744

+

85745

+void FFI_HIDDEN

85746

+ffi_prep_args64 (extended_cif *ecif, unsigned long *const stack)

85747

+{

85748

+ const unsigned long bytes = ecif->cif->bytes;

85749

+ const unsigned long flags = ecif->cif->flags;

85750

+

85751

+ typedef union

85752

+ {

85753

+ char *c;

85754

+ unsigned long *ul;

85755

+ float *f;

85756

+ double *d;

85757

+ size_t p;

85758

+ } valp;

85759

+

85760

+ /* 'stacktop' points at the previous backchain pointer. */

85761

+ valp stacktop;

85762

+

85763

+ /* 'next_arg' points at the space for gpr3, and grows upwards as

85764

+ we use GPR registers, then continues at rest. */

85765

+ valp gpr_base;

85766

+ valp gpr_end;

85767

+ valp rest;

85768

+ valp next_arg;

85769

+

85770

+ /* 'fpr_base' points at the space for fpr3, and grows upwards as

85771

+ we use FPR registers. */

85772

+ valp fpr_base;

85773

+ unsigned int fparg_count;

85774

+

85775

+ unsigned int i, words, nargs, nfixedargs;

85776

+ ffi_type **ptr;

85777

+ double double_tmp;

85778

+ union

85779

+ {

85780

+ void **v;

85781

+ char **c;

85782

+ signed char **sc;

85783

+ unsigned char **uc;

85784

+ signed short **ss;

85785

+ unsigned short **us;

85786

+ signed int **si;

85787

+ unsigned int **ui;

85788

+ unsigned long **ul;

85789

+ float **f;

85790

+ double **d;

85791

+ } p_argv;

85792

+ unsigned long gprvalue;

85793

+ unsigned long align;

85794

+

85795

+ stacktop.c = (char *) stack + bytes;

85796

+ gpr_base.ul = stacktop.ul - ASM_NEEDS_REGISTERS64 - NUM_GPR_ARG_REGISTERS64;

85797

+ gpr_end.ul = gpr_base.ul + NUM_GPR_ARG_REGISTERS64;

85798

+#if _CALL_ELF == 2

85799

+ rest.ul = stack + 4 + NUM_GPR_ARG_REGISTERS64;

85800

+#else

85801

+ rest.ul = stack + 6 + NUM_GPR_ARG_REGISTERS64;

85802

+#endif

85803

+ fpr_base.d = gpr_base.d - NUM_FPR_ARG_REGISTERS64;

85804

+ fparg_count = 0;

85805

+ next_arg.ul = gpr_base.ul;

85806

+

85807

+ /* Check that everything starts aligned properly. */

85808

+ FFI_ASSERT (((unsigned long) (char *) stack & 0xF) == 0);

85809

+ FFI_ASSERT (((unsigned long) stacktop.c & 0xF) == 0);

85810

+ FFI_ASSERT ((bytes & 0xF) == 0);

85811

+

85812

+ /* Deal with return values that are actually pass-by-reference. */

85813

+ if (flags & FLAG_RETVAL_REFERENCE)

85814

+ *next_arg.ul++ = (unsigned long) (char *) ecif->rvalue;

85815

+

85816

+ /* Now for the arguments. */

85817

+ p_argv.v = ecif->avalue;

85818

+ nargs = ecif->cif->nargs;

85819

+#if _CALL_ELF != 2

85820

+ nfixedargs = (unsigned) -1;

85821

+ if ((flags & FLAG_COMPAT) == 0)

85822

+#endif

85823

+ nfixedargs = ecif->cif->nfixedargs;

85824

+ for (ptr = ecif->cif->arg_types, i = 0;

85825

+ i < nargs;

85826

+ i++, ptr++, p_argv.v++)

85827

+ {

85828

+#if _CALL_ELF == 2

85829

+ unsigned int elt, elnum;

85830

+#endif

85831

+

85832

+ switch ((*ptr)->type)

85833

+ {

85834

+#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

85835

+ case FFI_TYPE_LONGDOUBLE:

85836

+ if ((ecif->cif->abi & FFI_LINUX_LONG_DOUBLE_128) != 0)

85837

+ {

85838

+ double_tmp = (*p_argv.d)[0];

85839

+ if (fparg_count < NUM_FPR_ARG_REGISTERS64 && i < nfixedargs)

85840

+ {

85841

+ *fpr_base.d++ = double_tmp;

85842

+# if _CALL_ELF != 2

85843

+ if ((flags & FLAG_COMPAT) != 0)

85844

+ *next_arg.d = double_tmp;

85845

+# endif

85846

+ }

85847

+ else

85848

+ *next_arg.d = double_tmp;

85849

+ if (++next_arg.ul == gpr_end.ul)

85850

+ next_arg.ul = rest.ul;

85851

+ fparg_count++;

85852

+ double_tmp = (*p_argv.d)[1];

85853

+ if (fparg_count < NUM_FPR_ARG_REGISTERS64 && i < nfixedargs)

85854

+ {

85855

+ *fpr_base.d++ = double_tmp;

85856

+# if _CALL_ELF != 2

85857

+ if ((flags & FLAG_COMPAT) != 0)

85858

+ *next_arg.d = double_tmp;

85859

+# endif

85860

+ }

85861

+ else

85862

+ *next_arg.d = double_tmp;

85863

+ if (++next_arg.ul == gpr_end.ul)

85864

+ next_arg.ul = rest.ul;

85865

+ fparg_count++;

85866

+ FFI_ASSERT (__LDBL_MANT_DIG__ == 106);

85867

+ FFI_ASSERT (flags & FLAG_FP_ARGUMENTS);

85868

+ break;

85869

+ }

85870

+ /* Fall through. */

85871

+#endif

85872

+ case FFI_TYPE_DOUBLE:

85873

+ double_tmp = **p_argv.d;

85874

+ if (fparg_count < NUM_FPR_ARG_REGISTERS64 && i < nfixedargs)

85875

+ {

85876

+ *fpr_base.d++ = double_tmp;

85877

+#if _CALL_ELF != 2

85878

+ if ((flags & FLAG_COMPAT) != 0)

85879

+ *next_arg.d = double_tmp;

85880

+#endif

85881

+ }

85882

+ else

85883

+ *next_arg.d = double_tmp;

85884

+ if (++next_arg.ul == gpr_end.ul)

85885

+ next_arg.ul = rest.ul;

85886

+ fparg_count++;

85887

+ FFI_ASSERT (flags & FLAG_FP_ARGUMENTS);

85888

+ break;

85889

+

85890

+ case FFI_TYPE_FLOAT:

85891

+ double_tmp = **p_argv.f;

85892

+ if (fparg_count < NUM_FPR_ARG_REGISTERS64 && i < nfixedargs)

85893

+ {

85894

+ *fpr_base.d++ = double_tmp;

85895

+#if _CALL_ELF != 2

85896

+ if ((flags & FLAG_COMPAT) != 0)

85897

+ *next_arg.f = (float) double_tmp;

85898

+#endif

85899

+ }

85900

+ else

85901

+ *next_arg.f = (float) double_tmp;

85902

+ if (++next_arg.ul == gpr_end.ul)

85903

+ next_arg.ul = rest.ul;

85904

+ fparg_count++;

85905

+ FFI_ASSERT (flags & FLAG_FP_ARGUMENTS);

85906

+ break;

85907

+

85908

+ case FFI_TYPE_STRUCT:

85909

+ if ((ecif->cif->abi & FFI_LINUX_STRUCT_ALIGN) != 0)

85910

+ {

85911

+ align = (*ptr)->alignment;

85912

+ if (align > 16)

85913

+ align = 16;

85914

+ if (align > 1)

85915

+ next_arg.p = ALIGN (next_arg.p, align);

85916

+ }

85917

+#if _CALL_ELF == 2

85918

+ elt = discover_homogeneous_aggregate (*ptr, &elnum);

85919

+ if (elt)

85920

+ {

85921

+ union {

85922

+ void *v;

85923

+ float *f;

85924

+ double *d;

85925

+ } arg;

85926

+

85927

+ arg.v = *p_argv.v;

85928

+ if (elt == FFI_TYPE_FLOAT)

85929

+ {

85930

+ do

85931

+ {

85932

+ double_tmp = *arg.f++;

85933

+ if (fparg_count < NUM_FPR_ARG_REGISTERS64

85934

+ && i < nfixedargs)

85935

+ *fpr_base.d++ = double_tmp;

85936

+ else

85937

+ *next_arg.f = (float) double_tmp;

85938

+ if (++next_arg.f == gpr_end.f)

85939

+ next_arg.f = rest.f;

85940

+ fparg_count++;

85941

+ }

85942

+ while (--elnum != 0);

85943

+ if ((next_arg.p & 3) != 0)

85944

+ {

85945

+ if (++next_arg.f == gpr_end.f)

85946

+ next_arg.f = rest.f;

85947

+ }

85948

+ }

85949

+ else

85950

+ do

85951

+ {

85952

+ double_tmp = *arg.d++;

85953

+ if (fparg_count < NUM_FPR_ARG_REGISTERS64 && i < nfixedargs)

85954

+ *fpr_base.d++ = double_tmp;

85955

+ else

85956

+ *next_arg.d = double_tmp;

85957

+ if (++next_arg.d == gpr_end.d)

85958

+ next_arg.d = rest.d;

85959

+ fparg_count++;

85960

+ }

85961

+ while (--elnum != 0);

85962

+ }

85963

+ else

85964

+#endif

85965

+ {

85966

+ words = ((*ptr)->size + 7) / 8;

85967

+ if (next_arg.ul >= gpr_base.ul && next_arg.ul + words > gpr_end.ul)

85968

+ {

85969

+ size_t first = gpr_end.c - next_arg.c;

85970

+ memcpy (next_arg.c, *p_argv.c, first);

85971

+ memcpy (rest.c, *p_argv.c + first, (*ptr)->size - first);

85972

+ next_arg.c = rest.c + words * 8 - first;

85973

+ }

85974

+ else

85975

+ {

85976

+ char *where = next_arg.c;

85977

+

85978

+#ifndef __LITTLE_ENDIAN__

85979

+ /* Structures with size less than eight bytes are passed

85980

+ left-padded. */

85981

+ if ((*ptr)->size < 8)

85982

+ where += 8 - (*ptr)->size;

85983

+#endif

85984

+ memcpy (where, *p_argv.c, (*ptr)->size);

85985

+ next_arg.ul += words;

85986

+ if (next_arg.ul == gpr_end.ul)

85987

+ next_arg.ul = rest.ul;

85988

+ }

85989

+ }

85990

+ break;

85991

+

85992

+ case FFI_TYPE_UINT8:

85993

+ gprvalue = **p_argv.uc;

85994

+ goto putgpr;

85995

+ case FFI_TYPE_SINT8:

85996

+ gprvalue = **p_argv.sc;

85997

+ goto putgpr;

85998

+ case FFI_TYPE_UINT16:

85999

+ gprvalue = **p_argv.us;

86000

+ goto putgpr;

86001

+ case FFI_TYPE_SINT16:

86002

+ gprvalue = **p_argv.ss;

86003

+ goto putgpr;

86004

+ case FFI_TYPE_UINT32:

86005

+ gprvalue = **p_argv.ui;

86006

+ goto putgpr;

86007

+ case FFI_TYPE_INT:

86008

+ case FFI_TYPE_SINT32:

86009

+ gprvalue = **p_argv.si;

86010

+ goto putgpr;

86011

+

86012

+ case FFI_TYPE_UINT64:

86013

+ case FFI_TYPE_SINT64:

86014

+ case FFI_TYPE_POINTER:

86015

+ gprvalue = **p_argv.ul;

86016

+ putgpr:

86017

+ *next_arg.ul++ = gprvalue;

86018

+ if (next_arg.ul == gpr_end.ul)

86019

+ next_arg.ul = rest.ul;

86020

+ break;

86021

+ }

86022

+ }

86023

+

86024

+ FFI_ASSERT (flags & FLAG_4_GPR_ARGUMENTS

86025

+ || (next_arg.ul >= gpr_base.ul

86026

+ && next_arg.ul <= gpr_base.ul + 4));

86027

+}

86028

+

86029

+

86030

+#if _CALL_ELF == 2

86031

+#define MIN_CACHE_LINE_SIZE 8

86032

+

86033

+static void

86034

+flush_icache (char *wraddr, char *xaddr, int size)

86035

+{

86036

+ int i;

86037

+ for (i = 0; i < size; i += MIN_CACHE_LINE_SIZE)

86038

+ __asm__ volatile ("icbi 0,%0;" "dcbf 0,%1;"

86039

+ : : "r" (xaddr + i), "r" (wraddr + i) : "memory");

86040

+ __asm__ volatile ("icbi 0,%0;" "dcbf 0,%1;" "sync;" "isync;"

86041

+ : : "r"(xaddr + size - 1), "r"(wraddr + size - 1)

86042

+ : "memory");

86043

+}

86044

+#endif

86045

+

86046

+ffi_status

86047

+ffi_prep_closure_loc_linux64 (ffi_closure *closure,

86048

+ ffi_cif *cif,

86049

+ void (*fun) (ffi_cif *, void *, void **, void *),

86050

+ void *user_data,

86051

+ void *codeloc)

86052

+{

86053

+#if _CALL_ELF == 2

86054

+ unsigned int *tramp = (unsigned int *) &closure->tramp[0];

86055

+

86056

+ if (cif->abi < FFI_LINUX || cif->abi >= FFI_LAST_ABI)

86057

+ return FFI_BAD_ABI;

86058

+

86059

+ tramp[0] = 0xe96c0018; /* 0: ld 11,2f-0b(12) */

86060

+ tramp[1] = 0xe98c0010; /* ld 12,1f-0b(12) */

86061

+ tramp[2] = 0x7d8903a6; /* mtctr 12 */

86062

+ tramp[3] = 0x4e800420; /* bctr */

86063

+ /* 1: .quad function_addr */

86064

+ /* 2: .quad context */

86065

+ *(void **) &tramp[4] = (void *) ffi_closure_LINUX64;

86066

+ *(void **) &tramp[6] = codeloc;

86067

+ flush_icache ((char *)tramp, (char *)codeloc, FFI_TRAMPOLINE_SIZE);

86068

+#else

86069

+ void **tramp = (void **) &closure->tramp[0];

86070

+

86071

+ if (cif->abi < FFI_LINUX || cif->abi >= FFI_LAST_ABI)

86072

+ return FFI_BAD_ABI;

86073

+

86074

+ /* Copy function address and TOC from ffi_closure_LINUX64. */

86075

+ memcpy (tramp, (char *) ffi_closure_LINUX64, 16);

86076

+ tramp[2] = codeloc;

86077

+#endif

86078

+

86079

+ closure->cif = cif;

86080

+ closure->fun = fun;

86081

+ closure->user_data = user_data;

86082

+

86083

+ return FFI_OK;

86084

+}

86085

+

86086

+

86087

+int FFI_HIDDEN

86088

+ffi_closure_helper_LINUX64 (ffi_closure *closure, void *rvalue,

86089

+ unsigned long *pst, ffi_dblfl *pfr)

86090

+{

86091

+ /* rvalue is the pointer to space for return value in closure assembly */

86092

+ /* pst is the pointer to parameter save area

86093

+ (r3-r10 are stored into its first 8 slots by ffi_closure_LINUX64) */

86094

+ /* pfr is the pointer to where f1-f13 are stored in ffi_closure_LINUX64 */

86095

+

86096

+ void **avalue;

86097

+ ffi_type **arg_types;

86098

+ unsigned long i, avn, nfixedargs;

86099

+ ffi_cif *cif;

86100

+ ffi_dblfl *end_pfr = pfr + NUM_FPR_ARG_REGISTERS64;

86101

+ unsigned long align;

86102

+

86103

+ cif = closure->cif;

86104

+ avalue = alloca (cif->nargs * sizeof (void *));

86105

+

86106

+ /* Copy the caller's structure return value address so that the

86107

+ closure returns the data directly to the caller. */

86108

+ if (cif->rtype->type == FFI_TYPE_STRUCT

86109

+ && (cif->flags & FLAG_RETURNS_SMST) == 0)

86110

+ {

86111

+ rvalue = (void *) *pst;

86112

+ pst++;

86113

+ }

86114

+

86115

+ i = 0;

86116

+ avn = cif->nargs;

86117

+#if _CALL_ELF != 2

86118

+ nfixedargs = (unsigned) -1;

86119

+ if ((cif->flags & FLAG_COMPAT) == 0)

86120

+#endif

86121

+ nfixedargs = cif->nfixedargs;

86122

+ arg_types = cif->arg_types;

86123

+

86124

+ /* Grab the addresses of the arguments from the stack frame. */

86125

+ while (i < avn)

86126

+ {

86127

+ unsigned int elt, elnum;

86128

+

86129

+ switch (arg_types[i]->type)

86130

+ {

86131

+ case FFI_TYPE_SINT8:

86132

+ case FFI_TYPE_UINT8:

86133

+#ifndef __LITTLE_ENDIAN__

86134

+ avalue[i] = (char *) pst + 7;

86135

+ pst++;

86136

+ break;

86137

+#endif

86138

+

86139

+ case FFI_TYPE_SINT16:

86140

+ case FFI_TYPE_UINT16:

86141

+#ifndef __LITTLE_ENDIAN__

86142

+ avalue[i] = (char *) pst + 6;

86143

+ pst++;

86144

+ break;

86145

+#endif

86146

+

86147

+ case FFI_TYPE_SINT32:

86148

+ case FFI_TYPE_UINT32:

86149

+#ifndef __LITTLE_ENDIAN__

86150

+ avalue[i] = (char *) pst + 4;

86151

+ pst++;

86152

+ break;

86153

+#endif

86154

+

86155

+ case FFI_TYPE_SINT64:

86156

+ case FFI_TYPE_UINT64:

86157

+ case FFI_TYPE_POINTER:

86158

+ avalue[i] = pst;

86159

+ pst++;

86160

+ break;

86161

+

86162

+ case FFI_TYPE_STRUCT:

86163

+ if ((cif->abi & FFI_LINUX_STRUCT_ALIGN) != 0)

86164

+ {

86165

+ align = arg_types[i]->alignment;

86166

+ if (align > 16)

86167

+ align = 16;

86168

+ if (align > 1)

86169

+ pst = (unsigned long *) ALIGN ((size_t) pst, align);

86170

+ }

86171

+ elt = 0;

86172

+#if _CALL_ELF == 2

86173

+ elt = discover_homogeneous_aggregate (arg_types[i], &elnum);

86174

+#endif

86175

+ if (elt)

86176

+ {

86177

+ union {

86178

+ void *v;

86179

+ unsigned long *ul;

86180

+ float *f;

86181

+ double *d;

86182

+ size_t p;

86183

+ } to, from;

86184

+

86185

+ /* Repackage the aggregate from its parts. The

86186

+ aggregate size is not greater than the space taken by

86187

+ the registers so store back to the register/parameter

86188

+ save arrays. */

86189

+ if (pfr + elnum <= end_pfr)

86190

+ to.v = pfr;

86191

+ else

86192

+ to.v = pst;

86193

+

86194

+ avalue[i] = to.v;

86195

+ from.ul = pst;

86196

+ if (elt == FFI_TYPE_FLOAT)

86197

+ {

86198

+ do

86199

+ {

86200

+ if (pfr < end_pfr && i < nfixedargs)

86201

+ {

86202

+ *to.f = (float) pfr->d;

86203

+ pfr++;

86204

+ }

86205

+ else

86206

+ *to.f = *from.f;

86207

+ to.f++;

86208

+ from.f++;

86209

+ }

86210

+ while (--elnum != 0);

86211

+ }

86212

+ else

86213

+ {

86214

+ do

86215

+ {

86216

+ if (pfr < end_pfr && i < nfixedargs)

86217

+ {

86218

+ *to.d = pfr->d;

86219

+ pfr++;

86220

+ }

86221

+ else

86222

+ *to.d = *from.d;

86223

+ to.d++;

86224

+ from.d++;

86225

+ }

86226

+ while (--elnum != 0);

86227

+ }

86228

+ }

86229

+ else

86230

+ {

86231

+#ifndef __LITTLE_ENDIAN__

86232

+ /* Structures with size less than eight bytes are passed

86233

+ left-padded. */

86234

+ if (arg_types[i]->size < 8)

86235

+ avalue[i] = (char *) pst + 8 - arg_types[i]->size;

86236

+ else

86237

+#endif

86238

+ avalue[i] = pst;

86239

+ }

86240

+ pst += (arg_types[i]->size + 7) / 8;

86241

+ break;

86242

+

86243

+#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

86244

+ case FFI_TYPE_LONGDOUBLE:

86245

+ if ((cif->abi & FFI_LINUX_LONG_DOUBLE_128) != 0)

86246

+ {

86247

+ if (pfr + 1 < end_pfr && i + 1 < nfixedargs)

86248

+ {

86249

+ avalue[i] = pfr;

86250

+ pfr += 2;

86251

+ }

86252

+ else

86253

+ {

86254

+ if (pfr < end_pfr && i < nfixedargs)

86255

+ {

86256

+ /* Passed partly in f13 and partly on the stack.

86257

+ Move it all to the stack. */

86258

+ *pst = *(unsigned long *) pfr;

86259

+ pfr++;

86260

+ }

86261

+ avalue[i] = pst;

86262

+ }

86263

+ pst += 2;

86264

+ break;

86265

+ }

86266

+ /* Fall through. */

86267

+#endif

86268

+ case FFI_TYPE_DOUBLE:

86269

+ /* On the outgoing stack all values are aligned to 8 */

86270

+ /* there are 13 64bit floating point registers */

86271

+

86272

+ if (pfr < end_pfr && i < nfixedargs)

86273

+ {

86274

+ avalue[i] = pfr;

86275

+ pfr++;

86276

+ }

86277

+ else

86278

+ avalue[i] = pst;

86279

+ pst++;

86280

+ break;

86281

+

86282

+ case FFI_TYPE_FLOAT:

86283

+ if (pfr < end_pfr && i < nfixedargs)

86284

+ {

86285

+ /* Float values are stored as doubles in the

86286

+ ffi_closure_LINUX64 code. Fix them here. */

86287

+ pfr->f = (float) pfr->d;

86288

+ avalue[i] = pfr;

86289

+ pfr++;

86290

+ }

86291

+ else

86292

+ avalue[i] = pst;

86293

+ pst++;

86294

+ break;

86295

+

86296

+ default:

86297

+ FFI_ASSERT (0);

86298

+ }

86299

+

86300

+ i++;

86301

+ }

86302

+

86303

+

86304

+ (closure->fun) (cif, rvalue, avalue, closure->user_data);

86305

+

86306

+ /* Tell ffi_closure_LINUX64 how to perform return type promotions. */

86307

+ if ((cif->flags & FLAG_RETURNS_SMST) != 0)

86308

+ {

86309

+ if ((cif->flags & FLAG_RETURNS_FP) == 0)

86310

+ return FFI_V2_TYPE_SMALL_STRUCT + cif->rtype->size - 1;

86311

+ else if ((cif->flags & FLAG_RETURNS_64BITS) != 0)

86312

+ return FFI_V2_TYPE_DOUBLE_HOMOG;

86313

+ else

86314

+ return FFI_V2_TYPE_FLOAT_HOMOG;

86315

+ }

86316

+ return cif->rtype->type;

86317

+}

86318

+#endif

86319

Index: libffi/src/types.c

86320

===================================================================

86321

--- a/src/libffi/src/types.c (.../tags/gcc_4_8_2_release)

86322

+++ b/src/libffi/src/types.c (.../branches/gcc-4_8-branch)

86323

@@ -44,6 +44,17 @@

86324

id, NULL \

86325

}

86326

86327

+#define FFI_NONCONST_TYPEDEF(name, type, id) \

86328

+struct struct_align_##name { \

86329

+ char c; \

86330

+ type x; \

86331

+}; \

86332

+ffi_type ffi_type_##name = { \

86333

+ sizeof(type), \

86334

+ offsetof(struct struct_align_##name, x), \

86335

+ id, NULL \

86336

+}

86337

+

86338

/* Size and alignment are fake here. They must not be 0. */

86339

const ffi_type ffi_type_void = {

86340

1, 1, FFI_TYPE_VOID, NULL

86341

@@ -73,5 +84,9 @@

86342

# endif

86343

const ffi_type ffi_type_longdouble = { 16, 16, 4, NULL };

86344

#elif FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE

86345

+# if HAVE_LONG_DOUBLE_VARIANT

86346

+FFI_NONCONST_TYPEDEF(longdouble, long double, FFI_TYPE_LONGDOUBLE);

86347

+# else

86348

FFI_TYPEDEF(longdouble, long double, FFI_TYPE_LONGDOUBLE);

86349

+# endif

86350

#endif

86351

Index: libffi/src/prep_cif.c

86352

===================================================================

86353

--- a/src/libffi/src/prep_cif.c (.../tags/gcc_4_8_2_release)

86354

+++ b/src/libffi/src/prep_cif.c (.../branches/gcc-4_8-branch)

86355

@@ -126,6 +126,10 @@

86356

86357

cif->flags = 0;

86358

86359

+#if HAVE_LONG_DOUBLE_VARIANT

86360

+ ffi_prep_types (abi);

86361

+#endif

86362

+

86363

/* Initialize the return type if necessary */

86364

if ((cif->rtype->size == 0) && (initialize_aggregate(cif->rtype) != FFI_OK))

86365

return FFI_BAD_TYPEDEF;

86366

Index: libffi/ChangeLog

86367

===================================================================

86368

--- a/src/libffi/ChangeLog (.../tags/gcc_4_8_2_release)

86369

+++ b/src/libffi/ChangeLog (.../branches/gcc-4_8-branch)

86370

@@ -1,3 +1,39 @@

86371

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

86372

+

86373

+ Backport mainline r205844.

86374

+ 2013-11-18 Alan Modra <amodra@gmail.com>

86375

+ * src/powerpc/ffitarget.h: Import from upstream.

86376

+ * src/powerpc/ffi_powerpc.h: Likewise.

86377

+ * src/powerpc/ffi.c: Likewise.

86378

+ * src/powerpc/ffi_sysv.c: Likewise.

86379

+ * src/powerpc/ffi_linux64.c: Likewise.

86380

+ * src/powerpc/sysv.S: Likewise.

86381

+ * src/powerpc/ppc_closure.S: Likewise.

86382

+ * src/powerpc/linux64.S: Likewise.

86383

+ * src/powerpc/linux64_closure.S: Likewise.

86384

+ * src/types.c: Likewise.

86385

+ * Makefile.am (EXTRA_DIST): Add new src/powerpc files.

86386

+ (nodist_libffi_la_SOURCES <POWERPC, POWERPC_FREEBSD>): Likewise.

86387

+ * configure.ac (HAVE_LONG_DOUBLE_VARIANT): Define for powerpc.

86388

+ * include/ffi.h.in (ffi_prep_types): Declare.

86389

+ * src/prep_cif.c (ffi_prep_cif_core): Call ffi_prep_types.

86390

+ * configure: Regenerate.

86391

+ * fficonfig.h.in: Regenerate.

86392

+ * Makefile.in: Regenerate.

86393

+ * man/Makefile.in: Regenerate.

86394

+ * include/Makefile.in: Regenerate.

86395

+ * testsuite/Makefile.in: Regenerate.

86396

+

86397

+ * src/powerpc/ppc_closure.S: Don't bl .Luint128.

86398

+

86399

+ * src/powerpc/ffitarget.h: Import from upstream.

86400

+ * src/powerpc/ffi.c: Likewise.

86401

+ * src/powerpc/linux64.S: Likewise.

86402

+ * src/powerpc/linux64_closure.S: Likewise.

86403

+ * doc/libffi.texi: Likewise.

86404

+ * testsuite/libffi.call/cls_double_va.c: Likewise.

86405

+ * testsuite/libffi.call/cls_longdouble_va.c: Likewise.

86406

+

86407

2013-10-16 Release Manager

86408

86409

* GCC 4.8.2 released.

86410

Index: libffi/testsuite/Makefile.in

86411

===================================================================

86412

--- a/src/libffi/testsuite/Makefile.in (.../tags/gcc_4_8_2_release)

86413

+++ b/src/libffi/testsuite/Makefile.in (.../branches/gcc-4_8-branch)

86414

@@ -88,6 +88,7 @@

86415

FGREP = @FGREP@

86416

GREP = @GREP@

86417

HAVE_LONG_DOUBLE = @HAVE_LONG_DOUBLE@

86418

+HAVE_LONG_DOUBLE_VARIANT = @HAVE_LONG_DOUBLE_VARIANT@

86419

INSTALL = @INSTALL@

86420

INSTALL_DATA = @INSTALL_DATA@

86421

INSTALL_PROGRAM = @INSTALL_PROGRAM@

86422

Index: libffi/testsuite/libffi.call/cls_double_va.c

86423

===================================================================

86424

--- a/src/libffi/testsuite/libffi.call/cls_double_va.c (.../tags/gcc_4_8_2_release)

86425

+++ b/src/libffi/testsuite/libffi.call/cls_double_va.c (.../branches/gcc-4_8-branch)

86426

@@ -38,7 +38,7 @@

86427

86428

/* This printf call is variadic */

86429

CHECK(ffi_prep_cif_var(&cif, FFI_DEFAULT_ABI, 1, 2, &ffi_type_sint,

86430

- arg_types) == FFI_OK);

86431

+ arg_types) == FFI_OK);

86432

86433

args[0] = &format;

86434

args[1] = &doubleArg;

86435

@@ -45,19 +45,17 @@

86436

args[2] = NULL;

86437

86438

ffi_call(&cif, FFI_FN(printf), &res, args);

86439

- // { dg-output "7.0" }

86440

+ /* { dg-output "7.0" } */

86441

printf("res: %d\n", (int) res);

86442

- // { dg-output "\nres: 4" }

86443

+ /* { dg-output "\nres: 4" } */

86444

86445

- /* The call to cls_double_va_fn is static, so have to use a normal prep_cif */

86446

- CHECK(ffi_prep_cif(&cif, FFI_DEFAULT_ABI, 2, &ffi_type_sint, arg_types) == FFI_OK);

86447

+ CHECK(ffi_prep_closure_loc(pcl, &cif, cls_double_va_fn, NULL,

86448

+ code) == FFI_OK);

86449

86450

- CHECK(ffi_prep_closure_loc(pcl, &cif, cls_double_va_fn, NULL, code) == FFI_OK);

86451

-

86452

- res = ((int(*)(char*, double))(code))(format, doubleArg);

86453

- // { dg-output "\n7.0" }

86454

+ res = ((int(*)(char*, ...))(code))(format, doubleArg);

86455

+ /* { dg-output "\n7.0" } */

86456

printf("res: %d\n", (int) res);

86457

- // { dg-output "\nres: 4" }

86458

+ /* { dg-output "\nres: 4" } */

86459

86460

exit(0);

86461

}

86462

Index: libffi/testsuite/libffi.call/cls_longdouble_va.c

86463

===================================================================

86464

--- a/src/libffi/testsuite/libffi.call/cls_longdouble_va.c (.../tags/gcc_4_8_2_release)

86465

+++ b/src/libffi/testsuite/libffi.call/cls_longdouble_va.c (.../branches/gcc-4_8-branch)

86466

@@ -38,7 +38,7 @@

86467

86468

/* This printf call is variadic */

86469

CHECK(ffi_prep_cif_var(&cif, FFI_DEFAULT_ABI, 1, 2, &ffi_type_sint,

86470

- arg_types) == FFI_OK);

86471

+ arg_types) == FFI_OK);

86472

86473

args[0] = &format;

86474

args[1] = &ldArg;

86475

@@ -45,20 +45,17 @@

86476

args[2] = NULL;

86477

86478

ffi_call(&cif, FFI_FN(printf), &res, args);

86479

- // { dg-output "7.0" }

86480

+ /* { dg-output "7.0" } */

86481

printf("res: %d\n", (int) res);

86482

- // { dg-output "\nres: 4" }

86483

+ /* { dg-output "\nres: 4" } */

86484

86485

- /* The call to cls_longdouble_va_fn is static, so have to use a normal prep_cif */

86486

- CHECK(ffi_prep_cif(&cif, FFI_DEFAULT_ABI, 2, &ffi_type_sint,

86487

- arg_types) == FFI_OK);

86488

+ CHECK(ffi_prep_closure_loc(pcl, &cif, cls_longdouble_va_fn, NULL,

86489

+ code) == FFI_OK);

86490

86491

- CHECK(ffi_prep_closure_loc(pcl, &cif, cls_longdouble_va_fn, NULL, code) == FFI_OK);

86492

-

86493

- res = ((int(*)(char*, long double))(code))(format, ldArg);

86494

- // { dg-output "\n7.0" }

86495

+ res = ((int(*)(char*, ...))(code))(format, ldArg);

86496

+ /* { dg-output "\n7.0" } */

86497

printf("res: %d\n", (int) res);

86498

- // { dg-output "\nres: 4" }

86499

+ /* { dg-output "\nres: 4" } */

86500

86501

exit(0);

86502

}

86503

Index: libffi/configure.ac

86504

===================================================================

86505

--- a/src/libffi/configure.ac (.../tags/gcc_4_8_2_release)

86506

+++ b/src/libffi/configure.ac (.../branches/gcc-4_8-branch)

86507

@@ -65,6 +65,7 @@

86508

AM_CONDITIONAL(TESTSUBDIR, test -d $srcdir/testsuite)

86509

86510

TARGETDIR="unknown"

86511

+HAVE_LONG_DOUBLE_VARIANT=0

86512

case "$host" in

86513

aarch64*-*-*)

86514

TARGET=AARCH64; TARGETDIR=aarch64

86515

@@ -162,6 +163,7 @@

86516

86517

powerpc*-*-linux* | powerpc-*-sysv*)

86518

TARGET=POWERPC; TARGETDIR=powerpc

86519

+ HAVE_LONG_DOUBLE_VARIANT=1

86520

;;

86521

powerpc-*-amigaos*)

86522

TARGET=POWERPC; TARGETDIR=powerpc

86523

@@ -177,6 +179,7 @@

86524

;;

86525

powerpc-*-freebsd* | powerpc-*-openbsd*)

86526

TARGET=POWERPC_FREEBSD; TARGETDIR=powerpc

86527

+ HAVE_LONG_DOUBLE_VARIANT=1

86528

;;

86529

powerpc64-*-freebsd*)

86530

TARGET=POWERPC; TARGETDIR=powerpc

86531

@@ -273,14 +276,20 @@

86532

# Also AC_SUBST this variable for ffi.h.

86533

if test -z "$HAVE_LONG_DOUBLE"; then

86534

HAVE_LONG_DOUBLE=0

86535

- if test $ac_cv_sizeof_double != $ac_cv_sizeof_long_double; then

86536

- if test $ac_cv_sizeof_long_double != 0; then

86537

+ if test $ac_cv_sizeof_long_double != 0; then

86538

+ if test $HAVE_LONG_DOUBLE_VARIANT != 0; then

86539

+ AC_DEFINE(HAVE_LONG_DOUBLE_VARIANT, 1, [Define if you support more than one size of the long double type])

86540

HAVE_LONG_DOUBLE=1

86541

- AC_DEFINE(HAVE_LONG_DOUBLE, 1, [Define if you have the long double type and it is bigger than a double])

86542

+ else

86543

+ if test $ac_cv_sizeof_double != $ac_cv_sizeof_long_double; then

86544

+ HAVE_LONG_DOUBLE=1

86545

+ AC_DEFINE(HAVE_LONG_DOUBLE, 1, [Define if you have the long double type and it is bigger than a double])

86546

+ fi

86547

fi

86548

fi

86549

fi

86550

AC_SUBST(HAVE_LONG_DOUBLE)

86551

+AC_SUBST(HAVE_LONG_DOUBLE_VARIANT)

86552

86553

AC_C_BIGENDIAN

86554

86555

Index: libffi/Makefile.am

86556

===================================================================

86557

--- a/src/libffi/Makefile.am (.../tags/gcc_4_8_2_release)

86558

+++ b/src/libffi/Makefile.am (.../branches/gcc-4_8-branch)

86559

@@ -15,10 +15,12 @@

86560

src/ia64/unix.S src/mips/ffi.c src/mips/n32.S src/mips/o32.S \

86561

src/mips/ffitarget.h src/m32r/ffi.c src/m32r/sysv.S \

86562

src/m32r/ffitarget.h src/m68k/ffi.c src/m68k/sysv.S \

86563

- src/m68k/ffitarget.h src/powerpc/ffi.c src/powerpc/sysv.S \

86564

- src/powerpc/linux64.S src/powerpc/linux64_closure.S \

86565

- src/powerpc/ppc_closure.S src/powerpc/asm.h \

86566

- src/powerpc/aix.S src/powerpc/darwin.S \

86567

+ src/m68k/ffitarget.h \

86568

+ src/powerpc/ffi.c src/powerpc/ffi_powerpc.h \

86569

+ src/powerpc/ffi_sysv.c src/powerpc/ffi_linux64.c \

86570

+ src/powerpc/sysv.S src/powerpc/linux64.S \

86571

+ src/powerpc/linux64_closure.S src/powerpc/ppc_closure.S \

86572

+ src/powerpc/asm.h src/powerpc/aix.S src/powerpc/darwin.S \

86573

src/powerpc/aix_closure.S src/powerpc/darwin_closure.S \

86574

src/powerpc/ffi_darwin.c src/powerpc/ffitarget.h \

86575

src/s390/ffi.c src/s390/sysv.S src/s390/ffitarget.h \

86576

@@ -179,7 +181,7 @@

86577

nodist_libffi_la_SOURCES += src/m68k/ffi.c src/m68k/sysv.S

86578

endif

86579

if POWERPC

86580

-nodist_libffi_la_SOURCES += src/powerpc/ffi.c src/powerpc/sysv.S src/powerpc/ppc_closure.S src/powerpc/linux64.S src/powerpc/linux64_closure.S

86581

+nodist_libffi_la_SOURCES += src/powerpc/ffi.c src/powerpc/ffi_sysv.c src/powerpc/ffi_linux64.c src/powerpc/sysv.S src/powerpc/ppc_closure.S src/powerpc/linux64.S src/powerpc/linux64_closure.S

86582

endif

86583

if POWERPC_AIX

86584

nodist_libffi_la_SOURCES += src/powerpc/ffi_darwin.c src/powerpc/aix.S src/powerpc/aix_closure.S

86585

@@ -188,7 +190,7 @@

86586

nodist_libffi_la_SOURCES += src/powerpc/ffi_darwin.c src/powerpc/darwin.S src/powerpc/darwin_closure.S

86587

endif

86588

if POWERPC_FREEBSD

86589

-nodist_libffi_la_SOURCES += src/powerpc/ffi.c src/powerpc/sysv.S src/powerpc/ppc_closure.S

86590

+nodist_libffi_la_SOURCES += src/powerpc/ffi.c src/powerpc/ffi_sysv.c src/powerpc/sysv.S src/powerpc/ppc_closure.S

86591

endif

86592

if AARCH64

86593

nodist_libffi_la_SOURCES += src/aarch64/sysv.S src/aarch64/ffi.c

86594

Index: libffi/man/Makefile.in

86595

===================================================================

86596

--- a/src/libffi/man/Makefile.in (.../tags/gcc_4_8_2_release)

86597

+++ b/src/libffi/man/Makefile.in (.../branches/gcc-4_8-branch)

86598

@@ -111,6 +111,7 @@

86599

FGREP = @FGREP@

86600

GREP = @GREP@

86601

HAVE_LONG_DOUBLE = @HAVE_LONG_DOUBLE@

86602

+HAVE_LONG_DOUBLE_VARIANT = @HAVE_LONG_DOUBLE_VARIANT@

86603

INSTALL = @INSTALL@

86604

INSTALL_DATA = @INSTALL_DATA@

86605

INSTALL_PROGRAM = @INSTALL_PROGRAM@

86606

Index: libssp/configure

86607

===================================================================

86608

--- a/src/libssp/configure (.../tags/gcc_4_8_2_release)

86609

+++ b/src/libssp/configure (.../branches/gcc-4_8-branch)

86610

@@ -6385,7 +6385,7 @@

86611

rm -rf conftest*

86612

;;

86613

86614

-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \

86615

+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \

86616

s390*-*linux*|s390*-*tpf*|sparc*-*linux*)

86617

# Find out which ABI we are using.

86618

echo 'int i;' > conftest.$ac_ext

86619

@@ -6410,7 +6410,10 @@

86620

;;

86621

esac

86622

;;

86623

- ppc64-*linux*|powerpc64-*linux*)

86624

+ powerpc64le-*linux*)

86625

+ LD="${LD-ld} -m elf32lppclinux"

86626

+ ;;

86627

+ powerpc64-*linux*)

86628

LD="${LD-ld} -m elf32ppclinux"

86629

;;

86630

s390x-*linux*)

86631

@@ -6429,7 +6432,10 @@

86632

x86_64-*linux*)

86633

LD="${LD-ld} -m elf_x86_64"

86634

;;

86635

- ppc*-*linux*|powerpc*-*linux*)

86636

+ powerpcle-*linux*)

86637

+ LD="${LD-ld} -m elf64lppc"

86638

+ ;;

86639

+ powerpc-*linux*)

86640

LD="${LD-ld} -m elf64ppc"

86641

;;

86642

s390*-*linux*|s390*-*tpf*)

86643

@@ -10658,7 +10664,7 @@

86644

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

86645

lt_status=$lt_dlunknown

86646

cat > conftest.$ac_ext <<_LT_EOF

86647

-#line 10661 "configure"

86648

+#line 10667 "configure"

86649

#include "confdefs.h"

86650

86651

#if HAVE_DLFCN_H

86652

@@ -10764,7 +10770,7 @@

86653

lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2

86654

lt_status=$lt_dlunknown

86655

cat > conftest.$ac_ext <<_LT_EOF

86656

-#line 10767 "configure"

86657

+#line 10773 "configure"

86658

#include "confdefs.h"

86659

86660

#if HAVE_DLFCN_H

86661

Index: libssp/ChangeLog

86662

===================================================================

86663

--- a/src/libssp/ChangeLog (.../tags/gcc_4_8_2_release)

86664

+++ b/src/libssp/ChangeLog (.../branches/gcc-4_8-branch)

86665

@@ -1,3 +1,10 @@

86666

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

86667

+

86668

+ Backport from mainline

86669

+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

86670

+

86671

+ * configure: Regenerate.

86672

+

86673

2013-10-16 Release Manager

86674

86675

* GCC 4.8.2 released.

86676

Index: libcpp/macro.c

86677

===================================================================

86678

--- a/src/libcpp/macro.c (.../tags/gcc_4_8_2_release)

86679

+++ b/src/libcpp/macro.c (.../branches/gcc-4_8-branch)

86680

@@ -1108,21 +1108,22 @@

86681

86682

if (macro->paramc == 0)

86683

{

86684

+ unsigned tokens_count = macro_real_token_count (macro);

86685

if (CPP_OPTION (pfile, track_macro_expansion))

86686

{

86687

- unsigned int i, count = macro->count;

86688

+ unsigned int i;

86689

const cpp_token *src = macro->exp.tokens;

86690

const struct line_map *map;

86691

source_location *virt_locs = NULL;

86692

- _cpp_buff *macro_tokens =

86693

- tokens_buff_new (pfile, count, &virt_locs);

86694

+ _cpp_buff *macro_tokens

86695

+ = tokens_buff_new (pfile, tokens_count, &virt_locs);

86696

86697

/* Create a macro map to record the locations of the

86698

tokens that are involved in the expansion. LOCATION

86699

is the location of the macro expansion point. */

86700

- map = linemap_enter_macro (pfile->line_table,

86701

- node, location, count);

86702

- for (i = 0; i < count; ++i)

86703

+ map = linemap_enter_macro (pfile->line_table,

86704

+ node, location, tokens_count);

86705

+ for (i = 0; i < tokens_count; ++i)

86706

{

86707

tokens_buff_add_token (macro_tokens, virt_locs,

86708

src, src->src_loc,

86709

@@ -1134,16 +1135,12 @@

86710

virt_locs,

86711

(const cpp_token **)

86712

macro_tokens->base,

86713

- count);

86714

- num_macro_tokens_counter += count;

86715

+ tokens_count);

86716

}

86717

else

86718

- {

86719

- unsigned tokens_count = macro_real_token_count (macro);

86720

- _cpp_push_token_context (pfile, node, macro->exp.tokens,

86721

- tokens_count);

86722

- num_macro_tokens_counter += tokens_count;

86723

- }

86724

+ _cpp_push_token_context (pfile, node, macro->exp.tokens,

86725

+ tokens_count);

86726

+ num_macro_tokens_counter += tokens_count;

86727

}

86728

86729

if (pragma_buff)

86730

Index: libcpp/line-map.c

86731

===================================================================

86732

--- a/src/libcpp/line-map.c (.../tags/gcc_4_8_2_release)

86733

+++ b/src/libcpp/line-map.c (.../branches/gcc-4_8-branch)

86734

@@ -1024,6 +1024,11 @@

86735

bool pre_virtual_p, post_virtual_p;

86736

source_location l0 = pre, l1 = post;

86737

86738

+ if (IS_ADHOC_LOC (l0))

86739

+ l0 = set->location_adhoc_data_map.data[l0 & MAX_SOURCE_LOCATION].locus;

86740

+ if (IS_ADHOC_LOC (l1))

86741

+ l1 = set->location_adhoc_data_map.data[l1 & MAX_SOURCE_LOCATION].locus;

86742

+

86743

if (l0 == l1)

86744

return 0;

86745

86746

Index: libcpp/files.c

86747

===================================================================

86748

--- a/src/libcpp/files.c (.../tags/gcc_4_8_2_release)

86749

+++ b/src/libcpp/files.c (.../branches/gcc-4_8-branch)

86750

@@ -983,6 +983,7 @@

86751

{

86752

struct cpp_dir *dir;

86753

_cpp_file *file;

86754

+ bool stacked;

86755

86756

dir = search_path_head (pfile, fname, angle_brackets, type);

86757

if (!dir)

86758

@@ -993,19 +994,26 @@

86759

if (type == IT_DEFAULT && file == NULL)

86760

return false;

86761

86762

- /* Compensate for the increment in linemap_add that occurs in

86763

- _cpp_stack_file. In the case of a normal #include, we're

86764

- currently at the start of the line *following* the #include. A

86765

- separate source_location for this location makes no sense (until

86766

- we do the LC_LEAVE), and complicates LAST_SOURCE_LINE_LOCATION.

86767

- This does not apply if we found a PCH file (in which case

86768

- linemap_add is not called) or we were included from the

86769

- command-line. */

86770

+ /* Compensate for the increment in linemap_add that occurs if

86771

+ _cpp_stack_file actually stacks the file. In the case of a

86772

+ normal #include, we're currently at the start of the line

86773

+ *following* the #include. A separate source_location for this

86774

+ location makes no sense (until we do the LC_LEAVE), and

86775

+ complicates LAST_SOURCE_LINE_LOCATION. This does not apply if we

86776

+ found a PCH file (in which case linemap_add is not called) or we

86777

+ were included from the command-line. */

86778

if (file->pchname == NULL && file->err_no == 0

86779

&& type != IT_CMDLINE && type != IT_DEFAULT)

86780

pfile->line_table->highest_location--;

86781

86782

- return _cpp_stack_file (pfile, file, type == IT_IMPORT);

86783

+ stacked = _cpp_stack_file (pfile, file, type == IT_IMPORT);

86784

+

86785

+ if (!stacked)

86786

+ /* _cpp_stack_file didn't stack the file, so let's rollback the

86787

+ compensation dance we performed above. */

86788

+ pfile->line_table->highest_location++;

86789

+

86790

+ return stacked;

86791

}

86792

86793

/* Could not open FILE. The complication is dependency output. */

86794

Index: libcpp/ChangeLog

86795

===================================================================

86796

--- a/src/libcpp/ChangeLog (.../tags/gcc_4_8_2_release)

86797

+++ b/src/libcpp/ChangeLog (.../branches/gcc-4_8-branch)

86798

@@ -1,3 +1,36 @@

86799

+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

86800

+

86801

+ Backport from mainline

86802

+ 2013-11-18 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

86803

+

86804

+ * lex.c (search_line_fast): Correct for little endian.

86805

+

86806

+2014-03-06 Jakub Jelinek <jakub@redhat.com>

86807

+

86808

+ Backport from mainline

86809

+ 2014-02-19 Jakub Jelinek <jakub@redhat.com>

86810

+

86811

+ PR preprocessor/58844

86812

+ * macro.c (enter_macro_context): Only push

86813

+ macro_real_token_count (macro) tokens rather than

86814

+ macro->count tokens, regardless of

86815

+ CPP_OPTION (pfile, track-macro-expansion).

86816

+

86817

+ 2014-02-07 Jakub Jelinek <jakub@redhat.com>

86818

+

86819

+ PR preprocessor/56824

86820

+ * line-map.c (linemap_compare_locations): Look through adhoc locations

86821

+ for both l0 and l1.

86822

+

86823

+2014-03-06 Jakub Jelinek <jakub@redhat.com>

86824

+

86825

+ PR preprocessor/60400

86826

+ Backport from mainline

86827

+ 2013-06-24 Dehao Chen <dehao@google.com>

86828

+

86829

+ * files.c (_cpp_stack_include): Fix the highest_location when header

86830

+ file is guarded by #ifndef and is included twice.

86831

+

86832

2013-10-16 Release Manager

86833

86834

* GCC 4.8.2 released.

86835

Index: libcpp/lex.c

86836

===================================================================

86837

--- a/src/libcpp/lex.c (.../tags/gcc_4_8_2_release)

86838

+++ b/src/libcpp/lex.c (.../branches/gcc-4_8-branch)

86839

@@ -559,8 +559,13 @@

86840

beginning with all ones and shifting in zeros according to the

86841

mis-alignment. The LVSR instruction pulls the exact shift we

86842

want from the address. */

86843

+#ifdef __BIG_ENDIAN__

86844

mask = __builtin_vec_lvsr(0, s);

86845

mask = __builtin_vec_perm(zero, ones, mask);

86846

+#else

86847

+ mask = __builtin_vec_lvsl(0, s);

86848

+ mask = __builtin_vec_perm(ones, zero, mask);

86849

+#endif

86850

data &= mask;

86851

86852

/* While altivec loads mask addresses, we still need to align S so

86853

@@ -624,7 +629,11 @@

86854

/* L now contains 0xff in bytes for which we matched one of the

86855

relevant characters. We can find the byte index by finding

86856

its bit index and dividing by 8. */

86857

+#ifdef __BIG_ENDIAN__

86858

l = __builtin_clzl(l) >> 3;

86859

+#else

86860

+ l = __builtin_ctzl(l) >> 3;

86861

+#endif

86862

return s + l;

86863

86864

#undef N

86865

Index: libcpp/po/pt_BR.po

86866

===================================================================

86867

--- a/src/libcpp/po/pt_BR.po (.../tags/gcc_4_8_2_release)

86868

+++ b/src/libcpp/po/pt_BR.po (.../branches/gcc-4_8-branch)

86869

@@ -0,0 +1,908 @@

86870

+# Brazilian Portuguese translation for cpplib

86871

86872

+# This file is distributed under the same license as the gcc package.

86873

+# Rafael Ferreira <rafael.f.f1@gmail.com>, 2013.

86874

+#

86875

+msgid ""

86876

+msgstr ""

86877

+"Project-Id-Version: cpplib 4.8.0\n"

86878

+"Report-Msgid-Bugs-To: http://gcc.gnu.org/bugs.html\n"

86879

+"POT-Creation-Date: 2013-03-15 17:42+0000\n"

86880

+"PO-Revision-Date: 2013-12-18 03:12-0300\n"

86881

+"Last-Translator: Rafael Ferreira <rafael.f.f1@gmail.com>\n"

86882

+"Language-Team: Brazilian Portuguese <ldpbr-translation@lists.sourceforge.net>\n"

86883

+"Language: pt_BR\n"

86884

+"MIME-Version: 1.0\n"

86885

+"Content-Type: text/plain; charset=UTF-8\n"

86886

+"Content-Transfer-Encoding: 8bit\n"

86887

+"X-Generator: Poedit 1.5.7\n"

86888

+"Plural-Forms: nplurals=2; plural=(n > 1);\n"

86889

+

86890

+#: charset.c:673

86891

+#, c-format

86892

+msgid "conversion from %s to %s not supported by iconv"

86893

+msgstr "sem suporte a conversão de %s para %s por iconv"

86894

+

86895

+#: charset.c:676

86896

+msgid "iconv_open"

86897

+msgstr "iconv_open"

86898

+

86899

+#: charset.c:684

86900

+#, c-format

86901

+msgid "no iconv implementation, cannot convert from %s to %s"

86902

+msgstr "nenhuma implementação iconv, não foi possível converter de %s para %s"

86903

+

86904

+#: charset.c:780

86905

+#, c-format

86906

+msgid "character 0x%lx is not in the basic source character set\n"

86907

+msgstr "caractere 0x%lx não está no conjunto de caracteres fonte básico\n"

86908

+

86909

+#: charset.c:797 charset.c:1443

86910

+msgid "converting to execution character set"

86911

+msgstr "convertendo para conjunto de caracteres da execução"

86912

+

86913

+#: charset.c:803

86914

+#, c-format

86915

+msgid "character 0x%lx is not unibyte in execution character set"

86916

+msgstr "caractere 0x%lx não é unibyte no conjunto de caracteres de execução"

86917

+

86918

+#: charset.c:927

86919

+#, c-format

86920

+msgid "Character %x might not be NFKC"

86921

+msgstr "Caractere %x pode não ser NFKC"

86922

+

86923

+#: charset.c:993

86924

+msgid "universal character names are only valid in C++ and C99"

86925

+msgstr "nomes de caractere universais são válidos apenas em C++ e C99"

86926

+

86927

+#: charset.c:996

86928

+#, c-format

86929

+msgid "the meaning of '\\%c' is different in traditional C"

86930

+msgstr "o significado de \"\\%c\" é diferente em C tradicional"

86931

+

86932

+#: charset.c:1005

86933

+msgid "In _cpp_valid_ucn but not a UCN"

86934

+msgstr "Em _cpp_valid_ucn, mas não é um UCN"

86935

+

86936

+#: charset.c:1030

86937

+#, c-format

86938

+msgid "incomplete universal character name %.*s"

86939

+msgstr "nome de caractere universal incompleto %.*s"

86940

+

86941

+#: charset.c:1045

86942

+#, c-format

86943

+msgid "%.*s is not a valid universal character"

86944

+msgstr "%.*s não é um caractere universal válido"

86945

+

86946

+#: charset.c:1055 lex.c:1117

86947

+msgid "'$' in identifier or number"

86948

+msgstr "\"$\" em identificador ou número"

86949

+

86950

+#: charset.c:1065

86951

+#, c-format

86952

+msgid "universal character %.*s is not valid in an identifier"

86953

+msgstr "caractere universal %.*s não é válido em um identificador"

86954

+

86955

+#: charset.c:1069

86956

+#, c-format

86957

+msgid "universal character %.*s is not valid at the start of an identifier"

86958

+msgstr "caractere universal %.*s não é válido no começo de um identificador"

86959

+

86960

+#: charset.c:1101 charset.c:1673

86961

+msgid "converting UCN to source character set"

86962

+msgstr "convertendo UCN para conjunto de caracteres fonte"

86963

+

86964

+#: charset.c:1105

86965

+msgid "converting UCN to execution character set"

86966

+msgstr "convertendo UCN para conjunto de caracteres de execução"

86967

+

86968

+#: charset.c:1177

86969

+msgid "the meaning of '\\x' is different in traditional C"

86970

+msgstr "o significado de \"\\x\" é diferente em C tradicional"

86971

+

86972

+#: charset.c:1194

86973

+msgid "\\x used with no following hex digits"

86974

+msgstr "\\x usado com nenhum dígito hexa"

86975

+

86976

+#: charset.c:1201

86977

+msgid "hex escape sequence out of range"

86978

+msgstr "sequência de escape hexa fora de alcance"

86979

+

86980

+#: charset.c:1239

86981

+msgid "octal escape sequence out of range"

86982

+msgstr "sequência de escape octal fora de alcance"

86983

+

86984

+#: charset.c:1305

86985

+msgid "the meaning of '\\a' is different in traditional C"

86986

+msgstr "o significado de \"\\a\" é diferente em C tradicional"

86987

+

86988

+#: charset.c:1312

86989

+#, c-format

86990

+msgid "non-ISO-standard escape sequence, '\\%c'"

86991

+msgstr "sequência de escape não padrão ISO, \"\\%c\""

86992

+

86993

+#: charset.c:1320

86994

+#, c-format

86995

+msgid "unknown escape sequence: '\\%c'"

86996

+msgstr "sequência de escape desconhecida: \"\\%c\""

86997

+

86998

+#: charset.c:1328

86999

+#, c-format

87000

+msgid "unknown escape sequence: '\\%s'"

87001

+msgstr "sequência de escape desconhecida: \"\\%s\""

87002

+

87003

+#: charset.c:1335

87004

+msgid "converting escape sequence to execution character set"

87005

+msgstr "convertendo sequência de escape para conjunto de caracteres de execução"

87006

+

87007

+#: charset.c:1508 charset.c:1572

87008

+msgid "character constant too long for its type"

87009

+msgstr "constante caractere muito longa para seu tipo"

87010

+

87011

+#: charset.c:1511

87012

+msgid "multi-character character constant"

87013

+msgstr "constante de caractere multi-caractere"

87014

+

87015

+#: charset.c:1611

87016

+msgid "empty character constant"

87017

+msgstr "constante caractere vazia"

87018

+

87019

+#: charset.c:1720

87020

+#, c-format

87021

+msgid "failure to convert %s to %s"

87022

+msgstr "falha ao converter %s para %s"

87023

+

87024

+#: directives.c:224 directives.c:250

87025

+#, c-format

87026

+msgid "extra tokens at end of #%s directive"

87027

+msgstr "tokens extras ao final da diretiva %#s"

87028

+

87029

+#: directives.c:357

87030

+#, c-format

87031

+msgid "#%s is a GCC extension"

87032

+msgstr "#%s é uma extensão GCC"

87033

+

87034

+#: directives.c:362

87035

+#, c-format

87036

+msgid "#%s is a deprecated GCC extension"

87037

+msgstr "#%s é uma extensão GCC obsoleta"

87038

+

87039

+#: directives.c:375

87040

+msgid "suggest not using #elif in traditional C"

87041

+msgstr "sugere-se não usar #elif em C tradicional"

87042

+

87043

+#: directives.c:378

87044

+#, c-format

87045

+msgid "traditional C ignores #%s with the # indented"

87046

+msgstr "C tradicional ignora #%s com o # com recuo"

87047

+

87048

+#: directives.c:382

87049

+#, c-format

87050

+msgid "suggest hiding #%s from traditional C with an indented #"

87051

+msgstr "sugere-se ocultar #%s do C tradicional com um # com recuo"

87052

+

87053

+#: directives.c:408

87054

+msgid "embedding a directive within macro arguments is not portable"

87055

+msgstr "embutir uma diretiva dentro de argumentos macro não é portátil"

87056

+

87057

+#: directives.c:428

87058

+msgid "style of line directive is a GCC extension"

87059

+msgstr "estilo de diretiva de linha é uma extensão GCC"

87060

+

87061

+#: directives.c:483

87062

+#, c-format

87063

+msgid "invalid preprocessing directive #%s"

87064

+msgstr "diretiva de preprocessamento inválida #%s"

87065

+

87066

+#: directives.c:551

87067

+msgid "\"defined\" cannot be used as a macro name"

87068

+msgstr "\"defined\" não pode ser usado como um nome de macro"

87069

+

87070

+#: directives.c:557

87071

+#, c-format

87072

+msgid "\"%s\" cannot be used as a macro name as it is an operator in C++"

87073

+msgstr "\"%s\" não pode ser usado como um nome de macro, pois é um operador em C++"

87074

+

87075

+#: directives.c:560

87076

+#, c-format

87077

+msgid "no macro name given in #%s directive"

87078

+msgstr "nenhum nome de macro fornecido na diretiva #%s"

87079

+

87080

+#: directives.c:563

87081

+msgid "macro names must be identifiers"

87082

+msgstr "nomes de macro devem ser identificadores"

87083

+

87084

+#: directives.c:612

87085

+#, c-format

87086

+msgid "undefining \"%s\""

87087

+msgstr "removendo definição de \"%s\""

87088

+

87089

+#: directives.c:667

87090

+msgid "missing terminating > character"

87091

+msgstr "faltando caractere terminador >"

87092

+

87093

+#: directives.c:726

87094

+#, c-format

87095

+msgid "#%s expects \"FILENAME\" or <FILENAME>"

87096

+msgstr "#%s espera \"NOME DE ARQUIVO\" OU <NOME DE ARQUIVO>"

87097

+

87098

+#: directives.c:772

87099

+#, c-format

87100

+msgid "empty filename in #%s"

87101

+msgstr "nome de arquivo vazio em #%s"

87102

+

87103

+#: directives.c:782

87104

+msgid "#include nested too deeply"

87105

+msgstr "#include aninhado profundo demais"

87106

+

87107

+#: directives.c:823

87108

+msgid "#include_next in primary source file"

87109

+msgstr "#include_next no arquivo fonte primário"

87110

+

87111

+#: directives.c:849

87112

+#, c-format

87113

+msgid "invalid flag \"%s\" in line directive"

87114

+msgstr "opção inválida \"%s\" na diretiva line"

87115

+

87116

+#: directives.c:909

87117

+msgid "unexpected end of file after #line"

87118

+msgstr "fim de arquivo inesperado após #line"

87119

+

87120

+#: directives.c:912

87121

+#, c-format

87122

+msgid "\"%s\" after #line is not a positive integer"

87123

+msgstr "\"%s\" após #line não é um inteiro positivo"

87124

+

87125

+#: directives.c:918 directives.c:920

87126

+msgid "line number out of range"

87127

+msgstr "número da linha fora de alcance"

87128

+

87129

+#: directives.c:933 directives.c:1013

87130

+#, c-format

87131

+msgid "\"%s\" is not a valid filename"

87132

+msgstr "\"%s\" não é um nome de arquivo válido"

87133

+

87134

+#: directives.c:973

87135

+#, c-format

87136

+msgid "\"%s\" after # is not a positive integer"

87137

+msgstr "\"%s\" após # não é um inteiro positivo"

87138

+

87139

+#: directives.c:1068 directives.c:1070 directives.c:1072 directives.c:1658

87140

+#, c-format

87141

+msgid "%s"

87142

+msgstr "%s"

87143

+

87144

+#: directives.c:1096

87145

+#, c-format

87146

+msgid "invalid #%s directive"

87147

+msgstr "diretiva inválida #%s"

87148

+

87149

+#: directives.c:1159

87150

+#, c-format

87151

+msgid "registering pragmas in namespace \"%s\" with mismatched name expansion"

87152

+msgstr "registrando pragmas em espaço de nomes \"%s\" com expansão de nome incompatível"

87153

+

87154

+#: directives.c:1168

87155

+#, c-format

87156

+msgid "registering pragma \"%s\" with name expansion and no namespace"

87157

+msgstr "registrando pragma \"%s\" com expansão de nome e nenhum espaço de nomes"

87158

+

87159

+#: directives.c:1186

87160

+#, c-format

87161

+msgid "registering \"%s\" as both a pragma and a pragma namespace"

87162

+msgstr "registrando \"%s\" como tanto um pragma e um espaço de nomes de pragma"

87163

+

87164

+#: directives.c:1189

87165

+#, c-format

87166

+msgid "#pragma %s %s is already registered"

87167

+msgstr "#pragma %s %s já está registrado"

87168

+

87169

+#: directives.c:1192

87170

+#, c-format

87171

+msgid "#pragma %s is already registered"

87172

+msgstr "#pragma %s já está registrado"

87173

+

87174

+#: directives.c:1222

87175

+msgid "registering pragma with NULL handler"

87176

+msgstr "registrando pragma com manipulador NULO"

87177

+

87178

+#: directives.c:1439

87179

+msgid "#pragma once in main file"

87180

+msgstr "#pragma ocorre uma vez no arquivo principal"

87181

+

87182

+#: directives.c:1462

87183

+msgid "invalid #pragma push_macro directive"

87184

+msgstr "diretiva inválida #pragma push_macro"

87185

+

87186

+#: directives.c:1517

87187

+msgid "invalid #pragma pop_macro directive"

87188

+msgstr "diretiva inválida #pragma pop_macro"

87189

+

87190

+#: directives.c:1572

87191

+msgid "invalid #pragma GCC poison directive"

87192

+msgstr "diretiva inválida #pragma GCC poison"

87193

+

87194

+#: directives.c:1581

87195

+#, c-format

87196

+msgid "poisoning existing macro \"%s\""

87197

+msgstr "envenenando macro existente \"%s\""

87198

+

87199

+#: directives.c:1600

87200

+msgid "#pragma system_header ignored outside include file"

87201

+msgstr "#pragma system_header ignorado fora do arquivo include"

87202

+

87203

+#: directives.c:1625

87204

+#, c-format

87205

+msgid "cannot find source file %s"

87206

+msgstr "não foi possível localizar o arquivo fonte %s"

87207

+

87208

+#: directives.c:1629

87209

+#, c-format

87210

+msgid "current file is older than %s"

87211

+msgstr "arquivo atual é mais velho do que %s"

87212

+

87213

+#: directives.c:1653

87214

+#, c-format

87215

+msgid "invalid \"#pragma GCC %s\" directive"

87216

+msgstr "diretiva inválida \"#pragma GCC %s\""

87217

+

87218

+#: directives.c:1847

87219

+msgid "_Pragma takes a parenthesized string literal"

87220

+msgstr "_Pragma leva uma literal de string entre parenteses"

87221

+

87222

+#: directives.c:1968

87223

+msgid "#else without #if"

87224

+msgstr "#else sem #if"

87225

+

87226

+#: directives.c:1973

87227

+msgid "#else after #else"

87228

+msgstr "#else após #else"

87229

+

87230

+#: directives.c:1975 directives.c:2008

87231

+msgid "the conditional began here"

87232

+msgstr "a condicional começou aqui"

87233

+

87234

+#: directives.c:2001

87235

+msgid "#elif without #if"

87236

+msgstr "#elif sem #if"

87237

+

87238

+#: directives.c:2006

87239

+msgid "#elif after #else"

87240

+msgstr "#elif após #else"

87241

+

87242

+#: directives.c:2044

87243

+msgid "#endif without #if"

87244

+msgstr "#endif sem #if"

87245

+

87246

+#: directives.c:2124

87247

+msgid "missing '(' after predicate"

87248

+msgstr "faltando \"(\" após predicado"

87249

+

87250

+#: directives.c:2139

87251

+msgid "missing ')' to complete answer"

87252

+msgstr "faltando \")\" para uma resposta completa"

87253

+

87254

+#: directives.c:2159

87255

+msgid "predicate's answer is empty"

87256

+msgstr "resposta do predicado está vazia"

87257

+

87258

+#: directives.c:2186

87259

+msgid "assertion without predicate"

87260

+msgstr "asserção sem predicado"

87261

+

87262

+#: directives.c:2189

87263

+msgid "predicate must be an identifier"

87264

+msgstr "predicado deve ser um identificador"

87265

+

87266

+#: directives.c:2275

87267

+#, c-format

87268

+msgid "\"%s\" re-asserted"

87269

+msgstr "\"%s\" re-assertado"

87270

+

87271

+#: directives.c:2567

87272

+#, c-format

87273

+msgid "unterminated #%s"

87274

+msgstr "#%s não terminado"

87275

+

87276

+#: directives-only.c:221 lex.c:2234 traditional.c:162

87277

+msgid "unterminated comment"

87278

+msgstr "comentário não terminado"

87279

+

87280

+#: errors.c:234

87281

+msgid "stdout"

87282

+msgstr "saída padrão"

87283

+

87284

+#: errors.c:236

87285

+#, c-format

87286

+msgid "%s: %s"

87287

+msgstr "%s: %s"

87288

+

87289

+#: expr.c:479 expr.c:577

87290

+msgid "fixed-point constants are a GCC extension"

87291

+msgstr "constantes de ponto fixo (fixed-point constants) é uma extensão GCC"

87292

+

87293

+#: expr.c:504

87294

+msgid "invalid prefix \"0b\" for floating constant"

87295

+msgstr "prefixo inválido \"0b\" para constante flutuante"

87296

+

87297

+#: expr.c:514

87298

+msgid "use of C99 hexadecimal floating constant"

87299

+msgstr "uso de constante flutuante hexadecimal de C99"

87300

+

87301

+#: expr.c:545

87302

+#, c-format

87303

+msgid "invalid suffix \"%.*s\" on floating constant"

87304

+msgstr "sufixo inválido \"%.*s\" na constante flutuante"

87305

+

87306

+#: expr.c:556 expr.c:616

87307

+#, c-format

87308

+msgid "traditional C rejects the \"%.*s\" suffix"

87309

+msgstr "C tradicional rejeita o sufixo \"%.*s\""

87310

+

87311

+#: expr.c:564

87312

+msgid "suffix for double constant is a GCC extension"

87313

+msgstr "sufixo para constante dupla (suffix for double constant) é uma extensão GCC"

87314

+

87315

+#: expr.c:570

87316

+#, c-format

87317

+msgid "invalid suffix \"%.*s\" with hexadecimal floating constant"

87318

+msgstr "sufixo inválido \"%.*s\" com constante flutuante hexadecimal"

87319

+

87320

+#: expr.c:581

87321

+msgid "decimal float constants are a GCC extension"

87322

+msgstr "constantes flutuante decimais (decimal float constants) é uma extensão GCC"

87323

+

87324

+#: expr.c:599

87325

+#, c-format

87326

+msgid "invalid suffix \"%.*s\" on integer constant"

87327

+msgstr "sufixo inválido \"%.*s\" em constante inteiro"

87328

+

87329

+#: expr.c:624

87330

+msgid "use of C++0x long long integer constant"

87331

+msgstr "uso de constante longo longo inteiro de C++0x"

87332

+

87333

+#: expr.c:625

87334

+msgid "use of C99 long long integer constant"

87335

+msgstr "uso de constante longo longo inteiro de C99"

87336

+

87337

+#: expr.c:641

87338

+msgid "imaginary constants are a GCC extension"

87339

+msgstr "constantes imaginárias (imaginary constants) é uma extensão GCC"

87340

+

87341

+#: expr.c:644

87342

+msgid "binary constants are a GCC extension"

87343

+msgstr "constantes binárias (binary constants) é uma extensão GCC"

87344

+

87345

+#: expr.c:737

87346

+msgid "integer constant is too large for its type"

87347

+msgstr "constante inteira é muito grande para seu tipo"

87348

+

87349

+#: expr.c:768

87350

+msgid "integer constant is so large that it is unsigned"

87351

+msgstr "constante inteira é tão grande que não está assinada"

87352

+

87353

+#: expr.c:863

87354

+msgid "missing ')' after \"defined\""

87355

+msgstr "faltando \")\" após \"defined\""

87356

+

87357

+#: expr.c:870

87358

+msgid "operator \"defined\" requires an identifier"

87359

+msgstr "operador \"defined\" requer um identificador"

87360

+

87361

+#: expr.c:878

87362

+#, c-format

87363

+msgid "(\"%s\" is an alternative token for \"%s\" in C++)"

87364

+msgstr "(\"%s\" é um token alternativo para \"%s\" em C++)"

87365

+

87366

+#: expr.c:888

87367

+msgid "this use of \"defined\" may not be portable"

87368

+msgstr "esse uso de \"defined\" pode não ser portátil"

87369

+

87370

+#: expr.c:948

87371

+msgid "user-defined literal in preprocessor expression"

87372

+msgstr "literal definida pelo usuário em expressão do preprocessador"

87373

+

87374

+#: expr.c:953

87375

+msgid "floating constant in preprocessor expression"

87376

+msgstr "constante flutuante em expressão do preprocessador"

87377

+

87378

+#: expr.c:959

87379

+msgid "imaginary number in preprocessor expression"

87380

+msgstr "número imaginário em expressão do preprocessador"

87381

+

87382

+#: expr.c:1007

87383

+#, c-format

87384

+msgid "\"%s\" is not defined"

87385

+msgstr "\"%s\" não está definido"

87386

+

87387

+#: expr.c:1020

87388

+msgid "assertions are a GCC extension"

87389

+msgstr "asserções (assertions) é uma extensão GCC"

87390

+

87391

+#: expr.c:1023

87392

+msgid "assertions are a deprecated extension"

87393

+msgstr "asserções (assertions) é uma extensão obsoleta"

87394

+

87395

+#: expr.c:1268

87396

+#, c-format

87397

+msgid "unbalanced stack in %s"

87398

+msgstr "pilha não balanceada em %s"

87399

+

87400

+#: expr.c:1288

87401

+#, c-format

87402

+msgid "impossible operator '%u'"

87403

+msgstr "operador impossível \"%u\""

87404

+

87405

+#: expr.c:1389

87406

+msgid "missing ')' in expression"

87407

+msgstr "faltando \")\" na expressão"

87408

+

87409

+#: expr.c:1418

87410

+msgid "'?' without following ':'"

87411

+msgstr "\"?\" sem estar seguido por \":\""

87412

+

87413

+#: expr.c:1428

87414

+msgid "integer overflow in preprocessor expression"

87415

+msgstr "estouro de inteiro em expressão do preprocessador"

87416

+

87417

+#: expr.c:1433

87418

+msgid "missing '(' in expression"

87419

+msgstr "faltando \"(\" na expressão"

87420

+

87421

+#: expr.c:1465

87422

+#, c-format

87423

+msgid "the left operand of \"%s\" changes sign when promoted"

87424

+msgstr "o operador à esquerda de \"%s\" altera o sinal quando promovido"

87425

+

87426

+#: expr.c:1470

87427

+#, c-format

87428

+msgid "the right operand of \"%s\" changes sign when promoted"

87429

+msgstr "o operador à direita de \"%s\" altera o sinal quando promovido"

87430

+

87431

+#: expr.c:1729

87432

+msgid "traditional C rejects the unary plus operator"

87433

+msgstr "C tradicional rejeita o operador unário mais"

87434

+

87435

+#: expr.c:1812

87436

+msgid "comma operator in operand of #if"

87437

+msgstr "operador vírgula em operando de #if"

87438

+

87439

+#: expr.c:1948

87440

+msgid "division by zero in #if"

87441

+msgstr "divisão por zero em #if"

87442

+

87443

+#: files.c:505

87444

+msgid "NULL directory in find_file"

87445

+msgstr "diretório NULO em find_file"

87446

+

87447

+#: files.c:553

87448

+msgid "one or more PCH files were found, but they were invalid"

87449

+msgstr "um ou mais arquivos PCH foram encontrados, mas são inválidos"

87450

+

87451

+#: files.c:556

87452

+msgid "use -Winvalid-pch for more information"

87453

+msgstr "use -Winvalid-pch para mais informações"

87454

+

87455

+#: files.c:660

87456

+#, c-format

87457

+msgid "%s is a block device"

87458

+msgstr "%s é um dispositivo de bloco"

87459

+

87460

+#: files.c:677

87461

+#, c-format

87462

+msgid "%s is too large"

87463

+msgstr "%s é muito grande"

87464

+

87465

+#: files.c:717

87466

+#, c-format

87467

+msgid "%s is shorter than expected"

87468

+msgstr "%s é muito menor do que esperado"

87469

+

87470

+#: files.c:953

87471

+#, c-format

87472

+msgid "no include path in which to search for %s"

87473

+msgstr "não foi incluído nenhum caminho no qual se possa procurar por %s"

87474

+

87475

+#: files.c:1381

87476

+msgid "Multiple include guards may be useful for:\n"

87477

+msgstr "Múltiplos include guards podem ser úteis para:\n"

87478

+

87479

+#: init.c:524

87480

+msgid "cppchar_t must be an unsigned type"

87481

+msgstr "cppchar_t deve ser um tipo não assinado"

87482

+

87483

+#: init.c:528

87484

+#, c-format

87485

+msgid "preprocessor arithmetic has maximum precision of %lu bits; target requires %lu bits"

87486

+msgstr "aritmética do preprocessador possui uma precisão máxima de %lu bits; o alvo requer %lu bits"

87487

+

87488

+#: init.c:535

87489

+msgid "CPP arithmetic must be at least as precise as a target int"

87490

+msgstr "aritmética do CPP deve ser pelo menos tão precisa quanto um int alvo"

87491

+

87492

+#: init.c:538

87493

+msgid "target char is less than 8 bits wide"

87494

+msgstr "char alvo é menor do que 8 bits"

87495

+

87496

+#: init.c:542

87497

+msgid "target wchar_t is narrower than target char"

87498

+msgstr "wchar_t alvo é mais estreito do que o char alvo"

87499

+

87500

+#: init.c:546

87501

+msgid "target int is narrower than target char"

87502

+msgstr "int alvo é mais estreito do que o char alvo"

87503

+

87504

+#: init.c:551

87505

+msgid "CPP half-integer narrower than CPP character"

87506

+msgstr "meio-inteiro do CPP é mais estreito do que o caractere do CPP"

87507

+

87508

+#: init.c:555

87509

+#, c-format

87510

+msgid "CPP on this host cannot handle wide character constants over %lu bits, but the target requires %lu bits"

87511

+msgstr "CPP nesta máquina não consegue manipular constantes de wide character acima de %lu bits, mas o alvo requer %lu bits"

87512

+

87513

+#: lex.c:910

87514

+msgid "backslash and newline separated by space"

87515

+msgstr "barra invertida e nova linha separadas por espaço"

87516

+

87517

+#: lex.c:915

87518

+msgid "backslash-newline at end of file"

87519

+msgstr "barra invertida e nova linha no final do arquivo"

87520

+

87521

+#: lex.c:931

87522

+#, c-format

87523

+msgid "trigraph ??%c converted to %c"

87524

+msgstr "trígrafo ??%c convertido para %c"

87525

+

87526

+#: lex.c:939

87527

+#, c-format

87528

+msgid "trigraph ??%c ignored, use -trigraphs to enable"

87529

+msgstr "trígrafo ??%c ignorado, use -trigraphs para habilitá-lo"

87530

+

87531

+#: lex.c:988

87532

+msgid "\"/*\" within comment"

87533

+msgstr "\"/*\" dentro de comentário"

87534

+

87535

+#: lex.c:1046

87536

+#, c-format

87537

+msgid "%s in preprocessing directive"

87538

+msgstr "%s em diretiva de preprocessamento"

87539

+

87540

+#: lex.c:1055

87541

+msgid "null character(s) ignored"

87542

+msgstr "um ou mais caracteres nulos ignorados"

87543

+

87544

+#: lex.c:1092

87545

+#, c-format

87546

+msgid "`%.*s' is not in NFKC"

87547

+msgstr "\"%.*s\" não está em NFKC"

87548

+

87549

+#: lex.c:1095

87550

+#, c-format

87551

+msgid "`%.*s' is not in NFC"

87552

+msgstr "\"%.*s\" não está em NFC"

87553

+

87554

+#: lex.c:1164 lex.c:1241

87555

+#, c-format

87556

+msgid "attempt to use poisoned \"%s\""

87557

+msgstr "tentativa de usar \"%s\" envenenado"

87558

+

87559

+#: lex.c:1172 lex.c:1249

87560

+msgid "__VA_ARGS__ can only appear in the expansion of a C99 variadic macro"

87561

+msgstr "__VA_ARGS__ pode aparecer apenas na expansão de uma macro variádica C99"

87562

+

87563

+#: lex.c:1178 lex.c:1255

87564

+#, c-format

87565

+msgid "identifier \"%s\" is a special operator name in C++"

87566

+msgstr "identificador \"%s\" é o nome de um operador especial em C++"

87567

+

87568

+#: lex.c:1399

87569

+msgid "raw string delimiter longer than 16 characters"

87570

+msgstr "delimitador de string não tratada (raw) maior do que 16 caracteres"

87571

+

87572

+#: lex.c:1402

87573

+#, c-format

87574

+msgid "invalid character '%c' in raw string delimiter"

87575

+msgstr "caractere inválido \"%c\" em delimitador de string não tratada (raw)"

87576

+

87577

+#: lex.c:1525 lex.c:1547

87578

+msgid "unterminated raw string"

87579

+msgstr "string não tratada (raw) não terminada"

87580

+

87581

+#: lex.c:1573 lex.c:1706

87582

+msgid "invalid suffix on literal; C++11 requires a space between literal and identifier"

87583

+msgstr "sufixo inválido em literal; C++11 requer um espaço entre literal e identificador"

87584

+

87585

+#: lex.c:1684

87586

+msgid "null character(s) preserved in literal"

87587

+msgstr "um ou mais caracteres nulos preservados em literal"

87588

+

87589

+#: lex.c:1687

87590

+#, c-format

87591

+msgid "missing terminating %c character"

87592

+msgstr "faltando o caractere de terminação %c"

87593

+

87594

+#: lex.c:2245

87595

+msgid "C++ style comments are not allowed in ISO C90"

87596

+msgstr "comentários no estilo C++ não são permitidos em ISO C90"

87597

+

87598

+#: lex.c:2247

87599

+msgid "(this will be reported only once per input file)"

87600

+msgstr "(isso será relatado apenas uma vez por arquivo de entrada)"

87601

+

87602

+#: lex.c:2252

87603

+msgid "multi-line comment"

87604

+msgstr "comentário multilinha"

87605

+

87606

+#: lex.c:2583

87607

+#, c-format

87608

+msgid "unspellable token %s"

87609

+msgstr "token %s impronunciável"

87610

+

87611

+#: macro.c:191

87612

+#, c-format

87613

+msgid "macro \"%s\" is not used"

87614

+msgstr "macro \"%s\" não é usada"

87615

+

87616

+#: macro.c:229 macro.c:426

87617

+#, c-format

87618

+msgid "invalid built-in macro \"%s\""

87619

+msgstr "macro interna inválida \"%s\""

87620

+

87621

+#: macro.c:263

87622

+msgid "could not determine file timestamp"

87623

+msgstr "não foi possível determinar o arquivo de marca de tempo"

87624

+

87625

+#: macro.c:361

87626

+msgid "could not determine date and time"

87627

+msgstr "não foi possível determinar a data e a hora"

87628

+

87629

+#: macro.c:377

87630

+msgid "__COUNTER__ expanded inside directive with -fdirectives-only"

87631

+msgstr "__COUNTER__ expandido dentro diretiva com -fdirectives-only"

87632

+

87633

+#: macro.c:535

87634

+msgid "invalid string literal, ignoring final '\\'"

87635

+msgstr "literal de string inválida, ignorando final \"\\\""

87636

+

87637

+#: macro.c:597

87638

+#, c-format

87639

+msgid "pasting \"%s\" and \"%s\" does not give a valid preprocessing token"

87640

+msgstr "colar \"%s\" em \"%s\" não resulta em nenhum token de preprocessamento válido"

87641

+

87642

+#: macro.c:719

87643

+msgid "ISO C99 requires rest arguments to be used"

87644

+msgstr "ISO C99 requer que argumentos restantes sejam usados"

87645

+

87646

+#: macro.c:724

87647

+#, c-format

87648

+msgid "macro \"%s\" requires %u arguments, but only %u given"

87649

+msgstr "macro \"%s\" requer %u argumentos, mas apenas %u foram fornecidos"

87650

+

87651

+#: macro.c:729

87652

+#, c-format

87653

+msgid "macro \"%s\" passed %u arguments, but takes just %u"

87654

+msgstr "macro \"%s\" passou %u argumentos, mas usa apenas %u"

87655

+

87656

+#: macro.c:923 traditional.c:680

87657

+#, c-format

87658

+msgid "unterminated argument list invoking macro \"%s\""

87659

+msgstr "lista de argumentos interminável chamando macro \"%s\""

87660

+

87661

+#: macro.c:1074

87662

+#, c-format

87663

+msgid "function-like macro \"%s\" must be used with arguments in traditional C"

87664

+msgstr "macro \"%s\" do tipo função deve ser usada com argumento em C tradicional"

87665

+

87666

+# http://gcc.gnu.org/bugzilla/show_bug.cgi?id=33305

87667

+#: macro.c:1746

87668

+#, c-format

87669

+msgid "invoking macro %s argument %d: empty macro arguments are undefined in ISO C90 and ISO C++98"

87670

+msgstr "chamando macro %s argumento %d: argumentos de macro vazios estão indefinidos em ISO C90 e ISO C++98"

87671

+

87672

+#: macro.c:2708

87673

+#, c-format

87674

+msgid "duplicate macro parameter \"%s\""

87675

+msgstr "parâmetro de macro \"%s\" duplicado"

87676

+

87677

+#: macro.c:2754

87678

+#, c-format

87679

+msgid "\"%s\" may not appear in macro parameter list"

87680

+msgstr "\"%s\" não pode aparecer na lista de parâmetros de macro"

87681

+

87682

+#: macro.c:2762

87683

+msgid "macro parameters must be comma-separated"

87684

+msgstr "parâmetros de macro devem ser separados por vírgula"

87685

+

87686

+#: macro.c:2779

87687

+msgid "parameter name missing"

87688

+msgstr "faltando nome de parâmetro"

87689

+

87690

+#: macro.c:2797

87691

+msgid "anonymous variadic macros were introduced in C99"

87692

+msgstr "macros variádicas anônimas foram introduzidas em C99"

87693

+

87694

+#: macro.c:2802

87695

+msgid "ISO C does not permit named variadic macros"

87696

+msgstr "ISO C não permite macros variádicas nomeadas"

87697

+

87698

+#: macro.c:2811

87699

+msgid "missing ')' in macro parameter list"

87700

+msgstr "faltando \")\" na lista de parâmetros de macro"

87701

+

87702

+#: macro.c:2860

87703

+msgid "'##' cannot appear at either end of a macro expansion"

87704

+msgstr "\"##\" não pode aparecer no final da expansão de macro"

87705

+

87706

+#: macro.c:2895

87707

+msgid "ISO C99 requires whitespace after the macro name"

87708

+msgstr "ISO C99 requer espaço em branco após o nome de macro"

87709

+

87710

+#: macro.c:2919

87711

+msgid "missing whitespace after the macro name"

87712

+msgstr "faltando espaço em branco após o nome de macro"

87713

+

87714

+#: macro.c:2953

87715

+msgid "'#' is not followed by a macro parameter"

87716

+msgstr "\"#\" não está seguido por um parâmetro de macro"

87717

+

87718

+#: macro.c:3111

87719

+#, c-format

87720

+msgid "\"%s\" redefined"

87721

+msgstr "\"%s\" re-definido"

87722

+

87723

+#: macro.c:3117

87724

+msgid "this is the location of the previous definition"

87725

+msgstr "essa é a localização da definição anterior"

87726

+

87727

+#: macro.c:3178

87728

+#, c-format

87729

+msgid "macro argument \"%s\" would be stringified in traditional C"

87730

+msgstr "argumento de macro \"%s\" estaria em uma string no C tradicional"

87731

+

87732

+#: macro.c:3205

87733

+#, c-format

87734

+msgid "invalid hash type %d in cpp_macro_definition"

87735

+msgstr "tipo de hash inválido %d em cpp_macro_definition"

87736

+

87737

+#: pch.c:87 pch.c:345 pch.c:359 pch.c:377 pch.c:383 pch.c:392 pch.c:399

87738

+msgid "while writing precompiled header"

87739

+msgstr "enquanto realizava escrita de header pré-compilado"

87740

+

87741

+#: pch.c:619

87742

+#, c-format

87743

+msgid "%s: not used because `%.*s' is poisoned"

87744

+msgstr "%s: não usado porque \"%.*s\" está envenenado"

87745

+

87746

+#: pch.c:641

87747

+#, c-format

87748

+msgid "%s: not used because `%.*s' not defined"

87749

+msgstr "%s: não usado porque \"%.*s\" não está definido"

87750

+

87751

+#: pch.c:653

87752

+#, c-format

87753

+msgid "%s: not used because `%.*s' defined as `%s' not `%.*s'"

87754

+msgstr "%s: não usado porque \"%.*s\" está definido como \"%s\", e não \"%.*s\""

87755

+

87756

+#: pch.c:694

87757

+#, c-format

87758

+msgid "%s: not used because `%s' is defined"

87759

+msgstr "%s: não usado porque \"%s\" está definido"

87760

+

87761

+#: pch.c:714

87762

+#, c-format

87763

+msgid "%s: not used because `__COUNTER__' is invalid"

87764

+msgstr "%s: não usado porque \"__COUNTER__\" é inválido"

87765

+

87766

+#: pch.c:723 pch.c:898

87767

+msgid "while reading precompiled header"

87768

+msgstr "enquanto realizava leitura de header pré-compilado"

87769

+

87770

+#: traditional.c:750

87771

+#, c-format

87772

+msgid "detected recursion whilst expanding macro \"%s\""

87773

+msgstr "detectada recursão enquanto expandia macro \"%s\""

87774

+

87775

+#: traditional.c:968

87776

+msgid "syntax error in macro parameter list"

87777

+msgstr "erro de sintaxe na lista de parâmetros de macro"

87778

Index: libcpp/po/ChangeLog

87779

===================================================================

87780

--- a/src/libcpp/po/ChangeLog (.../tags/gcc_4_8_2_release)

87781

+++ b/src/libcpp/po/ChangeLog (.../branches/gcc-4_8-branch)

87782

@@ -1,3 +1,11 @@

87783

+2013-12-18 Joseph Myers <joseph@codesourcery.com>

87784

+

87785

+ * pt_BR.po: New.

87786

+

87787

+2013-11-01 Joseph Myers <joseph@codesourcery.com>

87788

+

87789

+ * tr.po: Update.

87790

+

87791

2013-10-16 Release Manager

87792

87793

* GCC 4.8.2 released.

87794

Index: libcpp/po/tr.po

87795

===================================================================

87796

--- a/src/libcpp/po/tr.po (.../tags/gcc_4_8_2_release)

87797

+++ b/src/libcpp/po/tr.po (.../branches/gcc-4_8-branch)

87798

@@ -1,20 +1,22 @@

87799

# Turkish translations for cpplib messages.

87800

87801

+# This file is distributed under the same license as the gcc package.

87802

#

87803

# Nilgün Belma Bugüner <nilgun@buguner.name.tr>, 2001, ..., 2007.

87804

+# Volkan Gezer <vlkngzr@gmail.com>, 2013.

87805

msgid ""

87806

msgstr ""

87807

-"Project-Id-Version: cpplib 4.2.0\n"

87808

+"Project-Id-Version: cpplib 4.8.0\n"

87809

"Report-Msgid-Bugs-To: http://gcc.gnu.org/bugs.html\n"

87810

-"POT-Creation-Date: 2013-02-24 01:05+0000\n"

87811

-"PO-Revision-Date: 2007-05-23 01:17+0300\n"

87812

-"Last-Translator: Nilgün Belma Bugüner <nilgun@buguner.name.tr>\n"

87813

+"POT-Creation-Date: 2013-03-15 17:42+0000\n"

87814

+"PO-Revision-Date: 2013-11-01 22:29+0100\n"

87815

+"Last-Translator: Volkan Gezer <vlkngzr@gmail.com>\n"

87816

"Language-Team: Turkish <gnu-tr-u12a@lists.sourceforge.net>\n"

87817

"Language: tr\n"

87818

"MIME-Version: 1.0\n"

87819

"Content-Type: text/plain; charset=UTF-8\n"

87820

"Content-Transfer-Encoding: 8bit\n"

87821

-"X-Generator: KBabel 1.11.4\n"

87822

+"X-Generator: Lokalize 1.5\n"

87823

"Plural-Forms: nplurals=2; plural=(n != 1);\n"

87824

87825

#: charset.c:673

87826

@@ -121,10 +123,9 @@

87827

msgstr "ISO standardı olmayan önceleme dizgesi, '\\%c'"

87828

87829

#: charset.c:1320

87830

-#, fuzzy, c-format

87831

-#| msgid "unknown escape sequence '\\%c'"

87832

+#, c-format

87833

msgid "unknown escape sequence: '\\%c'"

87834

-msgstr "bilinmeyen önceleme dizgesi '\\%c'"

87835

+msgstr "bilinmeyen kaçış dizgesi: '\\%c'"

87836

87837

#: charset.c:1328

87838

#, c-format

87839

@@ -163,10 +164,9 @@

87840

msgstr "#%s bir GCC uzantısıdır"

87841

87842

#: directives.c:362

87843

-#, fuzzy, c-format

87844

-#| msgid "#%s is a GCC extension"

87845

+#, c-format

87846

msgid "#%s is a deprecated GCC extension"

87847

-msgstr "#%s bir GCC uzantısıdır"

87848

+msgstr "#%s eskimiş bir GCC uzantısıdır"

87849

87850

#: directives.c:375

87851

msgid "suggest not using #elif in traditional C"

87852

@@ -247,7 +247,7 @@

87853

87854

#: directives.c:909

87855

msgid "unexpected end of file after #line"

87856

-msgstr ""

87857

+msgstr "#line satırından sonra beklenmeyen dosya sonu"

87858

87859

#: directives.c:912

87860

#, c-format

87861

@@ -271,7 +271,7 @@

87862

#: directives.c:1068 directives.c:1070 directives.c:1072 directives.c:1658

87863

#, c-format

87864

msgid "%s"

87865

-msgstr ""

87866

+msgstr "%s"

87867

87868

#: directives.c:1096

87869

#, c-format

87870

@@ -312,16 +312,12 @@

87871

msgstr "main dosyasında '#pragma once'"

87872

87873

#: directives.c:1462

87874

-#, fuzzy

87875

-#| msgid "invalid #pragma GCC poison directive"

87876

msgid "invalid #pragma push_macro directive"

87877

-msgstr "geçersiz #pragma GCC poison yönergesi"

87878

+msgstr "geçersiz #pragma güdümlü_makro yönergesi"

87879

87880

#: directives.c:1517

87881

-#, fuzzy

87882

-#| msgid "invalid #pragma GCC poison directive"

87883

msgid "invalid #pragma pop_macro directive"

87884

-msgstr "geçersiz #pragma GCC poison yönergesi"

87885

+msgstr "geçersiz #pragma güdümlü_makro yönergesi"

87886

87887

#: directives.c:1572

87888

msgid "invalid #pragma GCC poison directive"

87889

@@ -347,10 +343,9 @@

87890

msgstr "mevcut dosya %s den daha eski"

87891

87892

#: directives.c:1653

87893

-#, fuzzy, c-format

87894

-#| msgid "invalid #pragma GCC poison directive"

87895

+#, c-format

87896

msgid "invalid \"#pragma GCC %s\" directive"

87897

-msgstr "geçersiz #pragma GCC poison yönergesi"

87898

+msgstr "geçersiz \"#pragma GCC %s\" yönergesi"

87899

87900

#: directives.c:1847

87901

msgid "_Pragma takes a parenthesized string literal"

87902

@@ -405,7 +400,7 @@

87903

msgid "\"%s\" re-asserted"

87904

msgstr "\"%s\" tekrar olumlanmış"

87905

87906

-#: directives.c:2566

87907

+#: directives.c:2567

87908

#, c-format

87909

msgid "unterminated #%s"

87910

msgstr "sonlandırılmamış #%s"

87911

@@ -424,16 +419,12 @@

87912

msgstr "%s: %s"

87913

87914

#: expr.c:479 expr.c:577

87915

-#, fuzzy

87916

-#| msgid "imaginary constants are a GCC extension"

87917

msgid "fixed-point constants are a GCC extension"

87918

-msgstr "sanal sabitler bir GCC genişletmesidir"

87919

+msgstr "sabit noktalı sabitler bir GCC uzantısıdır"

87920

87921

#: expr.c:504

87922

-#, fuzzy

87923

-#| msgid "invalid suffix \"%.*s\" on floating constant"

87924

msgid "invalid prefix \"0b\" for floating constant"

87925

-msgstr "gerçel sabitin \"%.*s\" soneki geçersiz"

87926

+msgstr "kayan nokta için geçerisz \"0b\" öntakısı"

87927

87928

#: expr.c:514

87929

msgid "use of C99 hexadecimal floating constant"

87930

@@ -450,10 +441,8 @@

87931

msgstr "geleneksel C \"%.*s\" sonekini kullanmaz"

87932

87933

#: expr.c:564

87934

-#, fuzzy

87935

-#| msgid "imaginary constants are a GCC extension"

87936

msgid "suffix for double constant is a GCC extension"

87937

-msgstr "sanal sabitler bir GCC genişletmesidir"

87938

+msgstr "çift sabit için öntakı bir GCC uzantısıdır"

87939

87940

#: expr.c:570

87941

#, c-format

87942

@@ -461,10 +450,8 @@

87943

msgstr "onaltılık kayan sabitli \"%.*s\" soneki geçersiz"

87944

87945

#: expr.c:581

87946

-#, fuzzy

87947

-#| msgid "imaginary constants are a GCC extension"

87948

msgid "decimal float constants are a GCC extension"

87949

-msgstr "sanal sabitler bir GCC genişletmesidir"

87950

+msgstr "onluk kayan sabitler bir GCC uzantısıdır"

87951

87952

#: expr.c:599

87953

#, c-format

87954

@@ -472,10 +459,8 @@

87955

msgstr "tamsayı sabitte sonek \"%.*s\" soneki geçersiz"

87956

87957

#: expr.c:624

87958

-#, fuzzy

87959

-#| msgid "use of C99 long long integer constant"

87960

msgid "use of C++0x long long integer constant"

87961

-msgstr "ISO C99 long long tamsayı sabitleri yasaklar"

87962

+msgstr "ISO C++0x long long tamsayı sabitlerinin kullanımı"

87963

87964

#: expr.c:625

87965

msgid "use of C99 long long integer constant"

87966

@@ -486,10 +471,8 @@

87967

msgstr "sanal sabitler bir GCC genişletmesidir"

87968

87969

#: expr.c:644

87970

-#, fuzzy

87971

-#| msgid "imaginary constants are a GCC extension"

87972

msgid "binary constants are a GCC extension"

87973

-msgstr "sanal sabitler bir GCC genişletmesidir"

87974

+msgstr "ikili sabitler bir GCC uzantısıdır"

87975

87976

#: expr.c:737

87977

msgid "integer constant is too large for its type"

87978

@@ -517,10 +500,8 @@

87979

msgstr "\"defined\" bu kullanımıyla uyarlanabilir olmayabilir"

87980

87981

#: expr.c:948

87982

-#, fuzzy

87983

-#| msgid "integer overflow in preprocessor expression"

87984

msgid "user-defined literal in preprocessor expression"

87985

-msgstr "önişlemci ifadesinde tamsayı taşması"

87986

+msgstr "önişleyici ifadesinde kullanıcı tanımlı bağımlı"

87987

87988

#: expr.c:953

87989

msgid "floating constant in preprocessor expression"

87990

@@ -536,20 +517,17 @@

87991

msgstr "\"%s\" tanımlı değil"

87992

87993

#: expr.c:1020

87994

-#, fuzzy

87995

-#| msgid "#%s is a GCC extension"

87996

msgid "assertions are a GCC extension"

87997

-msgstr "#%s bir GCC uzantısıdır"

87998

+msgstr "belirteçler bir GCC uzantısıdır"

87999

88000

#: expr.c:1023

88001

msgid "assertions are a deprecated extension"

88002

-msgstr ""

88003

+msgstr "belirteçler artık kullanılmayan bir ifadedir"

88004

88005

#: expr.c:1268

88006

-#, fuzzy, c-format

88007

-#| msgid "unbalanced stack in #if"

88008

+#, c-format

88009

msgid "unbalanced stack in %s"

88010

-msgstr "#if ifadesinde karşılıksız yığın"

88011

+msgstr "%s içinde dengelenmemiş yığın"

88012

88013

#: expr.c:1288

88014

#, c-format

88015

@@ -594,39 +572,39 @@

88016

msgid "division by zero in #if"

88017

msgstr "#if içinde sıfırla bölme"

88018

88019

-#: files.c:504

88020

+#: files.c:505

88021

msgid "NULL directory in find_file"

88022

msgstr "find_file içinde boş dizin"

88023

88024

-#: files.c:542

88025

+#: files.c:553

88026

msgid "one or more PCH files were found, but they were invalid"

88027

msgstr "bir veya daha fazla PCH dosyası bulundu ama bunlar geçersiz"

88028

88029

-#: files.c:545

88030

+#: files.c:556

88031

msgid "use -Winvalid-pch for more information"

88032

msgstr "daha fazla bilgi almak için -Winvalid-pch kullanın"

88033

88034

-#: files.c:643

88035

+#: files.c:660

88036

#, c-format

88037

msgid "%s is a block device"

88038

msgstr "%s bir blok aygıtıdır"

88039

88040

-#: files.c:660

88041

+#: files.c:677

88042

#, c-format

88043

msgid "%s is too large"

88044

msgstr "%s çok büyük"

88045

88046

-#: files.c:700

88047

+#: files.c:717

88048

#, c-format

88049

msgid "%s is shorter than expected"

88050

msgstr "%s beklenenden daha kısa"

88051

88052

-#: files.c:935

88053

+#: files.c:953

88054

#, c-format

88055

msgid "no include path in which to search for %s"

88056

msgstr "%s için aranacaklar içinde başlık dosyaları yolu yok"

88057

88058

-#: files.c:1363

88059

+#: files.c:1381

88060

msgid "Multiple include guards may be useful for:\n"

88061

msgstr "Çoklu include önlemleri aşağıdakiler için kullanışlı olabilir:\n"

88062

88063

@@ -717,27 +695,24 @@

88064

#: lex.c:1178 lex.c:1255

88065

#, c-format

88066

msgid "identifier \"%s\" is a special operator name in C++"

88067

-msgstr ""

88068

+msgstr "\"%s\" belirteci, C++'da özel bir işleç adıdır"

88069

88070

#: lex.c:1399

88071

msgid "raw string delimiter longer than 16 characters"

88072

-msgstr ""

88073

+msgstr "ham dizge ayracı 16 karakterden uzun"

88074

88075

#: lex.c:1402

88076

-#, fuzzy, c-format

88077

-#| msgid "universal character %.*s is not valid in an identifier"

88078

+#, c-format

88079

msgid "invalid character '%c' in raw string delimiter"

88080

-msgstr "evrensel karakter %.*s bir belirteç içinde geçerli değil"

88081

+msgstr "ham dizge ayracında geçersiz karakter '%c'"

88082

88083

#: lex.c:1525 lex.c:1547

88084

-#, fuzzy

88085

-#| msgid "unterminated #%s"

88086

msgid "unterminated raw string"

88087

-msgstr "sonlandırılmamış #%s"

88088

+msgstr "bitirilmemiş ham dizge"

88089

88090

#: lex.c:1573 lex.c:1706

88091

msgid "invalid suffix on literal; C++11 requires a space between literal and identifier"

88092

-msgstr ""

88093

+msgstr "geçersiz ifade soneki; C++11 ifade ve tanımlayıcı arasında bir boşluk gerektirir"

88094

88095

#: lex.c:1684

88096

msgid "null character(s) preserved in literal"

88097

@@ -785,7 +760,7 @@

88098

88099

#: macro.c:377

88100

msgid "__COUNTER__ expanded inside directive with -fdirectives-only"

88101

-msgstr ""

88102

+msgstr "__COUNTER__ -fdirectives-only ile talimat içerisinde genişletildi"

88103

88104

#: macro.c:535

88105

msgid "invalid string literal, ignoring final '\\'"

88106

@@ -823,7 +798,7 @@

88107

#: macro.c:1746

88108

#, c-format

88109

msgid "invoking macro %s argument %d: empty macro arguments are undefined in ISO C90 and ISO C++98"

88110

-msgstr ""

88111

+msgstr "%s makrosu %d argümanı uygulanıyor: ISO C90 ve ISO C++98 içerisinde boş makro argümanları tanımsızdır"

88112

88113

#: macro.c:2708

88114

#, c-format

88115

@@ -890,38 +865,36 @@

88116

msgid "invalid hash type %d in cpp_macro_definition"

88117

msgstr "cpp_macro_definition içindeki isimli yapı türü %d geçersiz"

88118

88119

-#: pch.c:87 pch.c:335 pch.c:347 pch.c:365 pch.c:371 pch.c:380 pch.c:387

88120

+#: pch.c:87 pch.c:345 pch.c:359 pch.c:377 pch.c:383 pch.c:392 pch.c:399

88121

msgid "while writing precompiled header"

88122

msgstr "önderlemeli başlık yazılırken"

88123

88124

-#: pch.c:607

88125

-#, fuzzy, c-format

88126

-#| msgid "%s: not used because `%s' is defined"

88127

+#: pch.c:619

88128

+#, c-format

88129

msgid "%s: not used because `%.*s' is poisoned"

88130

-msgstr "%s: `%s' tanımlı olduğundan kullanılmadı"

88131

+msgstr "%s: `%.*s' zehirli olduğu için kullanılmadı"

88132

88133

-#: pch.c:629

88134

+#: pch.c:641

88135

#, c-format

88136

msgid "%s: not used because `%.*s' not defined"

88137

msgstr "%s: `%.*s' tanımlı olmadığından kullanılmadı"

88138

88139

-#: pch.c:641

88140

+#: pch.c:653

88141

#, c-format

88142

msgid "%s: not used because `%.*s' defined as `%s' not `%.*s'"

88143

msgstr "%s: `%.*s' kullanılmadı çünkü `%s' olarak tanımlı, `%.*s' değil"

88144

88145

-#: pch.c:682

88146

+#: pch.c:694

88147

#, c-format

88148

msgid "%s: not used because `%s' is defined"

88149

msgstr "%s: `%s' tanımlı olduğundan kullanılmadı"

88150

88151

-#: pch.c:702

88152

-#, fuzzy, c-format

88153

-#| msgid "%s: not used because `%s' is defined"

88154

+#: pch.c:714

88155

+#, c-format

88156

msgid "%s: not used because `__COUNTER__' is invalid"

88157

-msgstr "%s: `%s' tanımlı olduğundan kullanılmadı"

88158

+msgstr "%s: `__COUNTER__' geçersiz olduğundan kullanılmadı"

88159

88160

-#: pch.c:711 pch.c:886

88161

+#: pch.c:723 pch.c:898

88162

msgid "while reading precompiled header"

88163

msgstr "önderlemeli başlık okunurken"

88164

88165

Index: .

88166

===================================================================

88167

--- a/src/. (.../tags/gcc_4_8_2_release)

88168

+++ b/src/. (.../branches/gcc-4_8-branch)

88169

88170

Property changes on: .

88171

___________________________________________________________________

88172

Modified: svn:mergeinfo

88173

Merged /trunk:r202766,204547,206123-206126,206395,206628,207387