686
/***************************************************************************
687
CAU BRANCH INSTRUCTION IMPLEMENTATION
688
***************************************************************************/
706
//**************************************************************************
707
// CAU BRANCH INSTRUCTION IMPLEMENTATION
708
//**************************************************************************
690
static void nop(dsp32_state *cpustate, UINT32 op)
710
void dsp32c_device::nop(UINT32 op)
694
execute_one(cpustate);
695
cpustate->PC = TRUNCATE24(REG24(cpustate, (op >> 16) & 0x1f) + (INT16)op);
715
PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
699
static void goto_t(dsp32_state *cpustate, UINT32 op)
719
void dsp32c_device::goto_t(UINT32 op)
701
execute_one(cpustate);
702
cpustate->PC = TRUNCATE24(REG24(cpustate, (op >> 16) & 0x1f) + (INT16)op);
722
PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
706
static void goto_pl(dsp32_state *cpustate, UINT32 op)
726
void dsp32c_device::goto_pl(UINT32 op)
710
execute_one(cpustate);
711
cpustate->PC = TRUNCATE24(REG24(cpustate, (op >> 16) & 0x1f) + (INT16)op);
731
PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
716
static void goto_mi(dsp32_state *cpustate, UINT32 op)
736
void dsp32c_device::goto_mi(UINT32 op)
720
execute_one(cpustate);
721
cpustate->PC = TRUNCATE24(REG24(cpustate, (op >> 16) & 0x1f) + (INT16)op);
741
PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
726
static void goto_ne(dsp32_state *cpustate, UINT32 op)
746
void dsp32c_device::goto_ne(UINT32 op)
730
execute_one(cpustate);
731
cpustate->PC = TRUNCATE24(REG24(cpustate, (op >> 16) & 0x1f) + (INT16)op);
751
PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
736
static void goto_eq(dsp32_state *cpustate, UINT32 op)
756
void dsp32c_device::goto_eq(UINT32 op)
740
execute_one(cpustate);
741
cpustate->PC = TRUNCATE24(REG24(cpustate, (op >> 16) & 0x1f) + (INT16)op);
761
PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
746
static void goto_vc(dsp32_state *cpustate, UINT32 op)
766
void dsp32c_device::goto_vc(UINT32 op)
750
execute_one(cpustate);
751
cpustate->PC = TRUNCATE24(REG24(cpustate, (op >> 16) & 0x1f) + (INT16)op);
771
PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
756
static void goto_vs(dsp32_state *cpustate, UINT32 op)
776
void dsp32c_device::goto_vs(UINT32 op)
760
execute_one(cpustate);
761
cpustate->PC = TRUNCATE24(REG24(cpustate, (op >> 16) & 0x1f) + (INT16)op);
781
PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
766
static void goto_cc(dsp32_state *cpustate, UINT32 op)
786
void dsp32c_device::goto_cc(UINT32 op)
770
execute_one(cpustate);
771
cpustate->PC = TRUNCATE24(REG24(cpustate, (op >> 16) & 0x1f) + (INT16)op);
791
PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
776
static void goto_cs(dsp32_state *cpustate, UINT32 op)
796
void dsp32c_device::goto_cs(UINT32 op)
780
execute_one(cpustate);
781
cpustate->PC = TRUNCATE24(REG24(cpustate, (op >> 16) & 0x1f) + (INT16)op);
801
PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
786
static void goto_ge(dsp32_state *cpustate, UINT32 op)
806
void dsp32c_device::goto_ge(UINT32 op)
788
808
if (!(nFLAG ^ vFLAG))
790
execute_one(cpustate);
791
cpustate->PC = TRUNCATE24(REG24(cpustate, (op >> 16) & 0x1f) + (INT16)op);
811
PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
796
static void goto_lt(dsp32_state *cpustate, UINT32 op)
816
void dsp32c_device::goto_lt(UINT32 op)
798
818
if (nFLAG ^ vFLAG)
800
execute_one(cpustate);
801
cpustate->PC = TRUNCATE24(REG24(cpustate, (op >> 16) & 0x1f) + (INT16)op);
821
PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
806
static void goto_gt(dsp32_state *cpustate, UINT32 op)
826
void dsp32c_device::goto_gt(UINT32 op)
808
828
if (!(zFLAG | (nFLAG ^ vFLAG)))
810
execute_one(cpustate);
811
cpustate->PC = TRUNCATE24(REG24(cpustate, (op >> 16) & 0x1f) + (INT16)op);
831
PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
816
static void goto_le(dsp32_state *cpustate, UINT32 op)
836
void dsp32c_device::goto_le(UINT32 op)
818
838
if (zFLAG | (nFLAG ^ vFLAG))
820
execute_one(cpustate);
821
cpustate->PC = TRUNCATE24(REG24(cpustate, (op >> 16) & 0x1f) + (INT16)op);
841
PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
826
static void goto_hi(dsp32_state *cpustate, UINT32 op)
846
void dsp32c_device::goto_hi(UINT32 op)
828
848
if (!cFLAG && !zFLAG)
830
execute_one(cpustate);
831
cpustate->PC = TRUNCATE24(REG24(cpustate, (op >> 16) & 0x1f) + (INT16)op);
851
PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
836
static void goto_ls(dsp32_state *cpustate, UINT32 op)
856
void dsp32c_device::goto_ls(UINT32 op)
838
858
if (cFLAG || zFLAG)
840
execute_one(cpustate);
841
cpustate->PC = TRUNCATE24(REG24(cpustate, (op >> 16) & 0x1f) + (INT16)op);
846
static void goto_auc(dsp32_state *cpustate, UINT32 op)
848
if (!(DEFERRED_VUFLAGS(cpustate) & UFLAGBIT))
850
execute_one(cpustate);
851
cpustate->PC = TRUNCATE24(REG24(cpustate, (op >> 16) & 0x1f) + (INT16)op);
856
static void goto_aus(dsp32_state *cpustate, UINT32 op)
858
if (DEFERRED_VUFLAGS(cpustate) & UFLAGBIT)
860
execute_one(cpustate);
861
cpustate->PC = TRUNCATE24(REG24(cpustate, (op >> 16) & 0x1f) + (INT16)op);
866
static void goto_age(dsp32_state *cpustate, UINT32 op)
868
if (DEFERRED_NZFLAGS(cpustate) >= 0)
870
execute_one(cpustate);
871
cpustate->PC = TRUNCATE24(REG24(cpustate, (op >> 16) & 0x1f) + (INT16)op);
876
static void goto_alt(dsp32_state *cpustate, UINT32 op)
878
if (DEFERRED_NZFLAGS(cpustate) < 0)
880
execute_one(cpustate);
881
cpustate->PC = TRUNCATE24(REG24(cpustate, (op >> 16) & 0x1f) + (INT16)op);
886
static void goto_ane(dsp32_state *cpustate, UINT32 op)
888
if (DEFERRED_NZFLAGS(cpustate) != 0)
890
execute_one(cpustate);
891
cpustate->PC = TRUNCATE24(REG24(cpustate, (op >> 16) & 0x1f) + (INT16)op);
896
static void goto_aeq(dsp32_state *cpustate, UINT32 op)
898
if (DEFERRED_NZFLAGS(cpustate) == 0)
900
execute_one(cpustate);
901
cpustate->PC = TRUNCATE24(REG24(cpustate, (op >> 16) & 0x1f) + (INT16)op);
906
static void goto_avc(dsp32_state *cpustate, UINT32 op)
908
if (!(DEFERRED_VUFLAGS(cpustate) & VFLAGBIT))
910
execute_one(cpustate);
911
cpustate->PC = TRUNCATE24(REG24(cpustate, (op >> 16) & 0x1f) + (INT16)op);
916
static void goto_avs(dsp32_state *cpustate, UINT32 op)
918
if (DEFERRED_VUFLAGS(cpustate) & VFLAGBIT)
920
execute_one(cpustate);
921
cpustate->PC = TRUNCATE24(REG24(cpustate, (op >> 16) & 0x1f) + (INT16)op);
926
static void goto_agt(dsp32_state *cpustate, UINT32 op)
928
if (DEFERRED_NZFLAGS(cpustate) > 0)
930
execute_one(cpustate);
931
cpustate->PC = TRUNCATE24(REG24(cpustate, (op >> 16) & 0x1f) + (INT16)op);
936
static void goto_ale(dsp32_state *cpustate, UINT32 op)
938
if (DEFERRED_NZFLAGS(cpustate) <= 0)
940
execute_one(cpustate);
941
cpustate->PC = TRUNCATE24(REG24(cpustate, (op >> 16) & 0x1f) + (INT16)op);
946
static void goto_ibe(dsp32_state *cpustate, UINT32 op)
948
unimplemented(cpustate, op);
952
static void goto_ibf(dsp32_state *cpustate, UINT32 op)
954
unimplemented(cpustate, op);
958
static void goto_obf(dsp32_state *cpustate, UINT32 op)
960
unimplemented(cpustate, op);
964
static void goto_obe(dsp32_state *cpustate, UINT32 op)
966
unimplemented(cpustate, op);
970
static void goto_pde(dsp32_state *cpustate, UINT32 op)
972
unimplemented(cpustate, op);
976
static void goto_pdf(dsp32_state *cpustate, UINT32 op)
978
unimplemented(cpustate, op);
982
static void goto_pie(dsp32_state *cpustate, UINT32 op)
984
unimplemented(cpustate, op);
988
static void goto_pif(dsp32_state *cpustate, UINT32 op)
990
unimplemented(cpustate, op);
994
static void goto_syc(dsp32_state *cpustate, UINT32 op)
996
unimplemented(cpustate, op);
1000
static void goto_sys(dsp32_state *cpustate, UINT32 op)
1002
unimplemented(cpustate, op);
1006
static void goto_fbc(dsp32_state *cpustate, UINT32 op)
1008
unimplemented(cpustate, op);
1012
static void goto_fbs(dsp32_state *cpustate, UINT32 op)
1014
unimplemented(cpustate, op);
1018
static void goto_irq1lo(dsp32_state *cpustate, UINT32 op)
1020
unimplemented(cpustate, op);
1024
static void goto_irq1hi(dsp32_state *cpustate, UINT32 op)
1026
unimplemented(cpustate, op);
1030
static void goto_irq2lo(dsp32_state *cpustate, UINT32 op)
1032
unimplemented(cpustate, op);
1036
static void goto_irq2hi(dsp32_state *cpustate, UINT32 op)
1038
unimplemented(cpustate, op);
1042
static void dec_goto(dsp32_state *cpustate, UINT32 op)
861
PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
866
void dsp32c_device::goto_auc(UINT32 op)
868
if (!(DEFERRED_VUFLAGS() & UFLAGBIT))
871
PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
876
void dsp32c_device::goto_aus(UINT32 op)
878
if (DEFERRED_VUFLAGS() & UFLAGBIT)
881
PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
886
void dsp32c_device::goto_age(UINT32 op)
888
if (DEFERRED_NZFLAGS() >= 0)
891
PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
896
void dsp32c_device::goto_alt(UINT32 op)
898
if (DEFERRED_NZFLAGS() < 0)
901
PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
906
void dsp32c_device::goto_ane(UINT32 op)
908
if (DEFERRED_NZFLAGS() != 0)
911
PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
916
void dsp32c_device::goto_aeq(UINT32 op)
918
if (DEFERRED_NZFLAGS() == 0)
921
PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
926
void dsp32c_device::goto_avc(UINT32 op)
928
if (!(DEFERRED_VUFLAGS() & VFLAGBIT))
931
PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
936
void dsp32c_device::goto_avs(UINT32 op)
938
if (DEFERRED_VUFLAGS() & VFLAGBIT)
941
PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
946
void dsp32c_device::goto_agt(UINT32 op)
948
if (DEFERRED_NZFLAGS() > 0)
951
PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
956
void dsp32c_device::goto_ale(UINT32 op)
958
if (DEFERRED_NZFLAGS() <= 0)
961
PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
966
void dsp32c_device::goto_ibe(UINT32 op)
972
void dsp32c_device::goto_ibf(UINT32 op)
978
void dsp32c_device::goto_obf(UINT32 op)
984
void dsp32c_device::goto_obe(UINT32 op)
990
void dsp32c_device::goto_pde(UINT32 op)
996
void dsp32c_device::goto_pdf(UINT32 op)
1002
void dsp32c_device::goto_pie(UINT32 op)
1008
void dsp32c_device::goto_pif(UINT32 op)
1014
void dsp32c_device::goto_syc(UINT32 op)
1020
void dsp32c_device::goto_sys(UINT32 op)
1026
void dsp32c_device::goto_fbc(UINT32 op)
1032
void dsp32c_device::goto_fbs(UINT32 op)
1038
void dsp32c_device::goto_irq1lo(UINT32 op)
1044
void dsp32c_device::goto_irq1hi(UINT32 op)
1050
void dsp32c_device::goto_irq2lo(UINT32 op)
1056
void dsp32c_device::goto_irq2hi(UINT32 op)
1062
void dsp32c_device::dec_goto(UINT32 op)
1044
1064
int hr = (op >> 21) & 0x1f;
1045
int old = (INT16)cpustate->r[hr];
1046
cpustate->r[hr] = EXTEND16_TO_24(cpustate->r[hr] - 1);
1065
int old = (INT16)m_r[hr];
1066
m_r[hr] = EXTEND16_TO_24(m_r[hr] - 1);
1049
execute_one(cpustate);
1050
cpustate->PC = TRUNCATE24(REG24(cpustate, (op >> 16) & 0x1f) + (INT16)op);
1070
PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
1055
static void call(dsp32_state *cpustate, UINT32 op)
1075
void dsp32c_device::call(UINT32 op)
1057
1077
int mr = (op >> 21) & 0x1f;
1058
1078
if (IS_WRITEABLE(mr))
1059
cpustate->r[mr] = cpustate->PC + 4;
1060
execute_one(cpustate);
1061
cpustate->PC = TRUNCATE24(REG24(cpustate, (op >> 16) & 0x1f) + (INT16)op);
1081
PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
1065
static void goto24(dsp32_state *cpustate, UINT32 op)
1085
void dsp32c_device::goto24(UINT32 op)
1067
execute_one(cpustate);
1068
cpustate->PC = TRUNCATE24(REG24(cpustate, (op >> 16) & 0x1f) + (op & 0xffff) + ((op >> 5) & 0xff0000));
1088
PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (op & 0xffff) + ((op >> 5) & 0xff0000));
1072
static void call24(dsp32_state *cpustate, UINT32 op)
1092
void dsp32c_device::call24(UINT32 op)
1074
1094
int mr = (op >> 16) & 0x1f;
1075
1095
if (IS_WRITEABLE(mr))
1076
cpustate->r[mr] = cpustate->PC + 4;
1077
execute_one(cpustate);
1078
cpustate->PC = (op & 0xffff) + ((op >> 5) & 0xff0000);
1082
static void do_i(dsp32_state *cpustate, UINT32 op)
1084
unimplemented(cpustate, op);
1088
static void do_r(dsp32_state *cpustate, UINT32 op)
1090
unimplemented(cpustate, op);
1095
/***************************************************************************
1096
CAU 16-BIT ARITHMETIC IMPLEMENTATION
1097
***************************************************************************/
1099
static void add_si(dsp32_state *cpustate, UINT32 op)
1098
PC = (op & 0xffff) + ((op >> 5) & 0xff0000);
1102
void dsp32c_device::do_i(UINT32 op)
1108
void dsp32c_device::do_r(UINT32 op)
1115
//**************************************************************************
1116
// CAU 16-BIT ARITHMETIC IMPLEMENTATION
1117
//**************************************************************************
1119
void dsp32c_device::add_si(UINT32 op)
1101
1121
int dr = (op >> 21) & 0x1f;
1102
int hrval = REG16(cpustate, (op >> 16) & 0x1f);
1122
int hrval = REG16((op >> 16) & 0x1f);
1103
1123
int res = hrval + (UINT16)op;
1104
1124
if (IS_WRITEABLE(dr))
1105
cpustate->r[dr] = EXTEND16_TO_24(res);
1106
SET_NZCV_16(cpustate, hrval, op, res);
1125
m_r[dr] = EXTEND16_TO_24(res);
1126
SET_NZCV_16(hrval, op, res);
1110
static void add_ss(dsp32_state *cpustate, UINT32 op)
1130
void dsp32c_device::add_ss(UINT32 op)
1112
if (CONDITION_IS_TRUE(cpustate))
1132
if (CONDITION_IS_TRUE())
1114
1134
int dr = (op >> 16) & 0x1f;
1115
int s1rval = REG16(cpustate, (op >> 5) & 0x1f);
1116
int s2rval = (op & 0x800) ? REG16(cpustate, (op >> 0) & 0x1f) : REG16(cpustate, dr);
1135
int s1rval = REG16((op >> 5) & 0x1f);
1136
int s2rval = (op & 0x800) ? REG16((op >> 0) & 0x1f) : REG16(dr);
1117
1137
int res = s2rval + s1rval;
1118
1138
if (IS_WRITEABLE(dr))
1119
cpustate->r[dr] = EXTEND16_TO_24(res);
1120
SET_NZCV_16(cpustate, s1rval, s2rval, res);
1139
m_r[dr] = EXTEND16_TO_24(res);
1140
SET_NZCV_16(s1rval, s2rval, res);
1125
static void mul2_s(dsp32_state *cpustate, UINT32 op)
1145
void dsp32c_device::mul2_s(UINT32 op)
1127
if (CONDITION_IS_TRUE(cpustate))
1147
if (CONDITION_IS_TRUE())
1129
1149
int dr = (op >> 16) & 0x1f;
1130
int s1rval = REG16(cpustate, (op >> 5) & 0x1f);
1150
int s1rval = REG16((op >> 5) & 0x1f);
1131
1151
int res = s1rval * 2;
1132
1152
if (IS_WRITEABLE(dr))
1133
cpustate->r[dr] = EXTEND16_TO_24(res);
1134
SET_NZCV_16(cpustate, s1rval, 0, res);
1153
m_r[dr] = EXTEND16_TO_24(res);
1154
SET_NZCV_16(s1rval, 0, res);
1139
static void subr_ss(dsp32_state *cpustate, UINT32 op)
1159
void dsp32c_device::subr_ss(UINT32 op)
1141
if (CONDITION_IS_TRUE(cpustate))
1161
if (CONDITION_IS_TRUE())
1143
1163
int dr = (op >> 16) & 0x1f;
1144
int s1rval = REG16(cpustate, (op >> 5) & 0x1f);
1145
int s2rval = (op & 0x800) ? REG16(cpustate, (op >> 0) & 0x1f) : REG16(cpustate, dr);
1164
int s1rval = REG16((op >> 5) & 0x1f);
1165
int s2rval = (op & 0x800) ? REG16((op >> 0) & 0x1f) : REG16(dr);
1146
1166
int res = s1rval - s2rval;
1147
1167
if (IS_WRITEABLE(dr))
1148
cpustate->r[dr] = EXTEND16_TO_24(res);
1149
SET_NZCV_16(cpustate, s1rval, s2rval, res);
1168
m_r[dr] = EXTEND16_TO_24(res);
1169
SET_NZCV_16(s1rval, s2rval, res);
1154
static void addr_ss(dsp32_state *cpustate, UINT32 op)
1174
void dsp32c_device::addr_ss(UINT32 op)
1156
unimplemented(cpustate, op);
1160
static void sub_ss(dsp32_state *cpustate, UINT32 op)
1180
void dsp32c_device::sub_ss(UINT32 op)
1162
if (CONDITION_IS_TRUE(cpustate))
1182
if (CONDITION_IS_TRUE())
1164
1184
int dr = (op >> 16) & 0x1f;
1165
int s1rval = REG16(cpustate, (op >> 5) & 0x1f);
1166
int s2rval = (op & 0x800) ? REG16(cpustate, (op >> 0) & 0x1f) : REG16(cpustate, dr);
1185
int s1rval = REG16((op >> 5) & 0x1f);
1186
int s2rval = (op & 0x800) ? REG16((op >> 0) & 0x1f) : REG16(dr);
1167
1187
int res = s2rval - s1rval;
1168
1188
if (IS_WRITEABLE(dr))
1169
cpustate->r[dr] = EXTEND16_TO_24(res);
1170
SET_NZCV_16(cpustate, s1rval, s2rval, res);
1189
m_r[dr] = EXTEND16_TO_24(res);
1190
SET_NZCV_16(s1rval, s2rval, res);
1175
static void neg_s(dsp32_state *cpustate, UINT32 op)
1195
void dsp32c_device::neg_s(UINT32 op)
1177
if (CONDITION_IS_TRUE(cpustate))
1197
if (CONDITION_IS_TRUE())
1179
1199
int dr = (op >> 16) & 0x1f;
1180
int s1rval = REG16(cpustate, (op >> 5) & 0x1f);
1200
int s1rval = REG16((op >> 5) & 0x1f);
1181
1201
int res = -s1rval;
1182
1202
if (IS_WRITEABLE(dr))
1183
cpustate->r[dr] = EXTEND16_TO_24(res);
1184
SET_NZCV_16(cpustate, s1rval, 0, res);
1203
m_r[dr] = EXTEND16_TO_24(res);
1204
SET_NZCV_16(s1rval, 0, res);
1189
static void andc_ss(dsp32_state *cpustate, UINT32 op)
1209
void dsp32c_device::andc_ss(UINT32 op)
1191
if (CONDITION_IS_TRUE(cpustate))
1211
if (CONDITION_IS_TRUE())
1193
1213
int dr = (op >> 16) & 0x1f;
1194
int s1rval = REG16(cpustate, (op >> 5) & 0x1f);
1195
int s2rval = (op & 0x800) ? REG16(cpustate, (op >> 0) & 0x1f) : REG16(cpustate, dr);
1214
int s1rval = REG16((op >> 5) & 0x1f);
1215
int s2rval = (op & 0x800) ? REG16((op >> 0) & 0x1f) : REG16(dr);
1196
1216
int res = s2rval & ~s1rval;
1197
1217
if (IS_WRITEABLE(dr))
1198
cpustate->r[dr] = EXTEND16_TO_24(res);
1199
SET_NZ00_16(cpustate, res);
1218
m_r[dr] = EXTEND16_TO_24(res);
1204
static void cmp_ss(dsp32_state *cpustate, UINT32 op)
1224
void dsp32c_device::cmp_ss(UINT32 op)
1206
if (CONDITION_IS_TRUE(cpustate))
1226
if (CONDITION_IS_TRUE())
1208
int drval = REG16(cpustate, (op >> 16) & 0x1f);
1209
int s1rval = REG16(cpustate, (op >> 5) & 0x1f);
1228
int drval = REG16((op >> 16) & 0x1f);
1229
int s1rval = REG16((op >> 5) & 0x1f);
1210
1230
int res = drval - s1rval;
1211
SET_NZCV_16(cpustate, drval, s1rval, res);
1231
SET_NZCV_16(drval, s1rval, res);
1216
static void xor_ss(dsp32_state *cpustate, UINT32 op)
1236
void dsp32c_device::xor_ss(UINT32 op)
1218
if (CONDITION_IS_TRUE(cpustate))
1238
if (CONDITION_IS_TRUE())
1220
1240
int dr = (op >> 16) & 0x1f;
1221
int s1rval = REG16(cpustate, (op >> 5) & 0x1f);
1222
int s2rval = (op & 0x800) ? REG16(cpustate, (op >> 0) & 0x1f) : REG16(cpustate, dr);
1241
int s1rval = REG16((op >> 5) & 0x1f);
1242
int s2rval = (op & 0x800) ? REG16((op >> 0) & 0x1f) : REG16(dr);
1223
1243
int res = s2rval ^ s1rval;
1224
1244
if (IS_WRITEABLE(dr))
1225
cpustate->r[dr] = EXTEND16_TO_24(res);
1226
SET_NZ00_16(cpustate, res);
1245
m_r[dr] = EXTEND16_TO_24(res);
1231
static void rcr_s(dsp32_state *cpustate, UINT32 op)
1251
void dsp32c_device::rcr_s(UINT32 op)
1233
if (CONDITION_IS_TRUE(cpustate))
1253
if (CONDITION_IS_TRUE())
1235
1255
int dr = (op >> 16) & 0x1f;
1236
int s1rval = REG16(cpustate, (op >> 5) & 0x1f);
1237
int res = ((cpustate->nzcflags >> 9) & 0x8000) | (s1rval >> 1);
1256
int s1rval = REG16((op >> 5) & 0x1f);
1257
int res = ((m_nzcflags >> 9) & 0x8000) | (s1rval >> 1);
1238
1258
if (IS_WRITEABLE(dr))
1239
cpustate->r[dr] = EXTEND16_TO_24(res);
1240
cpustate->nzcflags = ((res & 0xffff) << 8) | ((s1rval & 1) << 24);
1241
cpustate->vflags = 0;
1259
m_r[dr] = EXTEND16_TO_24(res);
1260
m_nzcflags = ((res & 0xffff) << 8) | ((s1rval & 1) << 24);
1246
static void or_ss(dsp32_state *cpustate, UINT32 op)
1266
void dsp32c_device::or_ss(UINT32 op)
1248
if (CONDITION_IS_TRUE(cpustate))
1268
if (CONDITION_IS_TRUE())
1250
1270
int dr = (op >> 16) & 0x1f;
1251
int s1rval = REG16(cpustate, (op >> 5) & 0x1f);
1252
int s2rval = (op & 0x800) ? REG16(cpustate, (op >> 0) & 0x1f) : REG16(cpustate, dr);
1271
int s1rval = REG16((op >> 5) & 0x1f);
1272
int s2rval = (op & 0x800) ? REG16((op >> 0) & 0x1f) : REG16(dr);
1253
1273
int res = s2rval | s1rval;
1254
1274
if (IS_WRITEABLE(dr))
1255
cpustate->r[dr] = EXTEND16_TO_24(res);
1256
SET_NZ00_16(cpustate, res);
1275
m_r[dr] = EXTEND16_TO_24(res);
1261
static void rcl_s(dsp32_state *cpustate, UINT32 op)
1281
void dsp32c_device::rcl_s(UINT32 op)
1263
if (CONDITION_IS_TRUE(cpustate))
1283
if (CONDITION_IS_TRUE())
1265
1285
int dr = (op >> 16) & 0x1f;
1266
int s1rval = REG16(cpustate, (op >> 5) & 0x1f);
1267
int res = ((cpustate->nzcflags >> 24) & 0x0001) | (s1rval << 1);
1286
int s1rval = REG16((op >> 5) & 0x1f);
1287
int res = ((m_nzcflags >> 24) & 0x0001) | (s1rval << 1);
1268
1288
if (IS_WRITEABLE(dr))
1269
cpustate->r[dr] = EXTEND16_TO_24(res);
1270
cpustate->nzcflags = ((res & 0xffff) << 8) | ((s1rval & 0x8000) << 9);
1271
cpustate->vflags = 0;
1289
m_r[dr] = EXTEND16_TO_24(res);
1290
m_nzcflags = ((res & 0xffff) << 8) | ((s1rval & 0x8000) << 9);
1276
static void shr_s(dsp32_state *cpustate, UINT32 op)
1296
void dsp32c_device::shr_s(UINT32 op)
1278
if (CONDITION_IS_TRUE(cpustate))
1298
if (CONDITION_IS_TRUE())
1280
1300
int dr = (op >> 16) & 0x1f;
1281
int s1rval = REG16(cpustate, (op >> 5) & 0x1f);
1301
int s1rval = REG16((op >> 5) & 0x1f);
1282
1302
int res = s1rval >> 1;
1283
1303
if (IS_WRITEABLE(dr))
1284
cpustate->r[dr] = EXTEND16_TO_24(res);
1285
cpustate->nzcflags = ((res & 0xffff) << 8) | ((s1rval & 1) << 24);
1286
cpustate->vflags = 0;
1304
m_r[dr] = EXTEND16_TO_24(res);
1305
m_nzcflags = ((res & 0xffff) << 8) | ((s1rval & 1) << 24);
1291
static void div2_s(dsp32_state *cpustate, UINT32 op)
1311
void dsp32c_device::div2_s(UINT32 op)
1293
if (CONDITION_IS_TRUE(cpustate))
1313
if (CONDITION_IS_TRUE())
1295
1315
int dr = (op >> 16) & 0x1f;
1296
int s1rval = REG16(cpustate, (op >> 5) & 0x1f);
1316
int s1rval = REG16((op >> 5) & 0x1f);
1297
1317
int res = (s1rval & 0x8000) | (s1rval >> 1);
1298
1318
if (IS_WRITEABLE(dr))
1299
cpustate->r[dr] = EXTEND16_TO_24(res);
1300
cpustate->nzcflags = ((res & 0xffff) << 8) | ((s1rval & 1) << 24);
1301
cpustate->vflags = 0;
1319
m_r[dr] = EXTEND16_TO_24(res);
1320
m_nzcflags = ((res & 0xffff) << 8) | ((s1rval & 1) << 24);
1306
static void and_ss(dsp32_state *cpustate, UINT32 op)
1326
void dsp32c_device::and_ss(UINT32 op)
1308
if (CONDITION_IS_TRUE(cpustate))
1328
if (CONDITION_IS_TRUE())
1310
1330
int dr = (op >> 16) & 0x1f;
1311
int s1rval = REG16(cpustate, (op >> 5) & 0x1f);
1312
int s2rval = (op & 0x800) ? REG16(cpustate, (op >> 0) & 0x1f) : REG16(cpustate, dr);
1331
int s1rval = REG16((op >> 5) & 0x1f);
1332
int s2rval = (op & 0x800) ? REG16((op >> 0) & 0x1f) : REG16(dr);
1313
1333
int res = s2rval & s1rval;
1314
1334
if (IS_WRITEABLE(dr))
1315
cpustate->r[dr] = EXTEND16_TO_24(res);
1316
SET_NZ00_16(cpustate, res);
1335
m_r[dr] = EXTEND16_TO_24(res);
1321
static void test_ss(dsp32_state *cpustate, UINT32 op)
1341
void dsp32c_device::test_ss(UINT32 op)
1323
if (CONDITION_IS_TRUE(cpustate))
1343
if (CONDITION_IS_TRUE())
1325
int drval = REG16(cpustate, (op >> 16) & 0x1f);
1326
int s1rval = REG16(cpustate, (op >> 5) & 0x1f);
1345
int drval = REG16((op >> 16) & 0x1f);
1346
int s1rval = REG16((op >> 5) & 0x1f);
1327
1347
int res = drval & s1rval;
1328
SET_NZ00_16(cpustate, res);
1333
static void add_di(dsp32_state *cpustate, UINT32 op)
1353
void dsp32c_device::add_di(UINT32 op)
1335
1355
int dr = (op >> 16) & 0x1f;
1336
int drval = REG16(cpustate, dr);
1356
int drval = REG16(dr);
1337
1357
int res = drval + (UINT16)op;
1338
1358
if (IS_WRITEABLE(dr))
1339
cpustate->r[dr] = EXTEND16_TO_24(res);
1340
SET_NZCV_16(cpustate, drval, op, res);
1359
m_r[dr] = EXTEND16_TO_24(res);
1360
SET_NZCV_16(drval, op, res);
1344
static void subr_di(dsp32_state *cpustate, UINT32 op)
1364
void dsp32c_device::subr_di(UINT32 op)
1346
1366
int dr = (op >> 16) & 0x1f;
1347
int drval = REG16(cpustate, dr);
1367
int drval = REG16(dr);
1348
1368
int res = (UINT16)op - drval;
1349
1369
if (IS_WRITEABLE(dr))
1350
cpustate->r[dr] = EXTEND16_TO_24(res);
1351
SET_NZCV_16(cpustate, drval, op, res);
1370
m_r[dr] = EXTEND16_TO_24(res);
1371
SET_NZCV_16(drval, op, res);
1355
static void addr_di(dsp32_state *cpustate, UINT32 op)
1375
void dsp32c_device::addr_di(UINT32 op)
1357
unimplemented(cpustate, op);
1361
static void sub_di(dsp32_state *cpustate, UINT32 op)
1381
void dsp32c_device::sub_di(UINT32 op)
1363
1383
int dr = (op >> 16) & 0x1f;
1364
int drval = REG16(cpustate, dr);
1384
int drval = REG16(dr);
1365
1385
int res = drval - (UINT16)op;
1366
1386
if (IS_WRITEABLE(dr))
1367
cpustate->r[dr] = EXTEND16_TO_24(res);
1368
SET_NZCV_16(cpustate, drval, op, res);
1387
m_r[dr] = EXTEND16_TO_24(res);
1388
SET_NZCV_16(drval, op, res);
1372
static void andc_di(dsp32_state *cpustate, UINT32 op)
1392
void dsp32c_device::andc_di(UINT32 op)
1374
1394
int dr = (op >> 16) & 0x1f;
1375
int drval = REG16(cpustate, dr);
1395
int drval = REG16(dr);
1376
1396
int res = drval & ~(UINT16)op;
1377
1397
if (IS_WRITEABLE(dr))
1378
cpustate->r[dr] = EXTEND16_TO_24(res);
1379
SET_NZ00_16(cpustate, res);
1398
m_r[dr] = EXTEND16_TO_24(res);
1383
static void cmp_di(dsp32_state *cpustate, UINT32 op)
1403
void dsp32c_device::cmp_di(UINT32 op)
1385
int drval = REG16(cpustate, (op >> 16) & 0x1f);
1405
int drval = REG16((op >> 16) & 0x1f);
1386
1406
int res = drval - (UINT16)op;
1387
SET_NZCV_16(cpustate, drval, op, res);
1407
SET_NZCV_16(drval, op, res);
1391
static void xor_di(dsp32_state *cpustate, UINT32 op)
1411
void dsp32c_device::xor_di(UINT32 op)
1393
1413
int dr = (op >> 16) & 0x1f;
1394
int drval = REG16(cpustate, dr);
1414
int drval = REG16(dr);
1395
1415
int res = drval ^ (UINT16)op;
1396
1416
if (IS_WRITEABLE(dr))
1397
cpustate->r[dr] = EXTEND16_TO_24(res);
1398
SET_NZ00_16(cpustate, res);
1417
m_r[dr] = EXTEND16_TO_24(res);
1402
static void or_di(dsp32_state *cpustate, UINT32 op)
1422
void dsp32c_device::or_di(UINT32 op)
1404
1424
int dr = (op >> 16) & 0x1f;
1405
int drval = REG16(cpustate, dr);
1425
int drval = REG16(dr);
1406
1426
int res = drval | (UINT16)op;
1407
1427
if (IS_WRITEABLE(dr))
1408
cpustate->r[dr] = EXTEND16_TO_24(res);
1409
SET_NZ00_16(cpustate, res);
1428
m_r[dr] = EXTEND16_TO_24(res);
1413
static void and_di(dsp32_state *cpustate, UINT32 op)
1433
void dsp32c_device::and_di(UINT32 op)
1415
1435
int dr = (op >> 16) & 0x1f;
1416
int drval = REG16(cpustate, dr);
1436
int drval = REG16(dr);
1417
1437
int res = drval & (UINT16)op;
1418
1438
if (IS_WRITEABLE(dr))
1419
cpustate->r[dr] = EXTEND16_TO_24(res);
1420
SET_NZ00_16(cpustate, res);
1439
m_r[dr] = EXTEND16_TO_24(res);
1424
static void test_di(dsp32_state *cpustate, UINT32 op)
1444
void dsp32c_device::test_di(UINT32 op)
1426
int drval = REG16(cpustate, (op >> 16) & 0x1f);
1446
int drval = REG16((op >> 16) & 0x1f);
1427
1447
int res = drval & (UINT16)op;
1428
SET_NZ00_16(cpustate, res);
1433
/***************************************************************************
1434
CAU 24-BIT ARITHMETIC IMPLEMENTATION
1435
***************************************************************************/
1453
//**************************************************************************
1454
// CAU 24-BIT ARITHMETIC IMPLEMENTATION
1455
//**************************************************************************
1437
static void adde_si(dsp32_state *cpustate, UINT32 op)
1457
void dsp32c_device::adde_si(UINT32 op)
1439
1459
int dr = (op >> 21) & 0x1f;
1440
int hrval = REG24(cpustate, (op >> 16) & 0x1f);
1460
int hrval = REG24((op >> 16) & 0x1f);
1441
1461
int res = hrval + EXTEND16_TO_24(op);
1442
1462
if (IS_WRITEABLE(dr))
1443
cpustate->r[dr] = TRUNCATE24(res);
1444
SET_NZCV_24(cpustate, hrval, op << 8, res);
1463
m_r[dr] = TRUNCATE24(res);
1464
SET_NZCV_24(hrval, op << 8, res);
1448
static void adde_ss(dsp32_state *cpustate, UINT32 op)
1468
void dsp32c_device::adde_ss(UINT32 op)
1450
if (CONDITION_IS_TRUE(cpustate))
1470
if (CONDITION_IS_TRUE())
1452
1472
int dr = (op >> 16) & 0x1f;
1453
int s1rval = REG24(cpustate, (op >> 5) & 0x1f);
1454
int s2rval = (op & 0x800) ? REG24(cpustate, (op >> 0) & 0x1f) : REG24(cpustate, dr);
1473
int s1rval = REG24((op >> 5) & 0x1f);
1474
int s2rval = (op & 0x800) ? REG24((op >> 0) & 0x1f) : REG24(dr);
1455
1475
int res = s2rval + s1rval;
1456
1476
if (IS_WRITEABLE(dr))
1457
cpustate->r[dr] = TRUNCATE24(res);
1458
SET_NZCV_24(cpustate, s1rval, s2rval, res);
1477
m_r[dr] = TRUNCATE24(res);
1478
SET_NZCV_24(s1rval, s2rval, res);
1463
static void mul2e_s(dsp32_state *cpustate, UINT32 op)
1483
void dsp32c_device::mul2e_s(UINT32 op)
1465
if (CONDITION_IS_TRUE(cpustate))
1485
if (CONDITION_IS_TRUE())
1467
1487
int dr = (op >> 16) & 0x1f;
1468
int s1rval = REG24(cpustate, (op >> 5) & 0x1f);
1488
int s1rval = REG24((op >> 5) & 0x1f);
1469
1489
int res = s1rval * 2;
1470
1490
if (IS_WRITEABLE(dr))
1471
cpustate->r[dr] = TRUNCATE24(res);
1472
SET_NZCV_24(cpustate, s1rval, 0, res);
1491
m_r[dr] = TRUNCATE24(res);
1492
SET_NZCV_24(s1rval, 0, res);
1477
static void subre_ss(dsp32_state *cpustate, UINT32 op)
1497
void dsp32c_device::subre_ss(UINT32 op)
1479
if (CONDITION_IS_TRUE(cpustate))
1499
if (CONDITION_IS_TRUE())
1481
1501
int dr = (op >> 16) & 0x1f;
1482
int s1rval = REG24(cpustate, (op >> 5) & 0x1f);
1483
int s2rval = (op & 0x800) ? REG24(cpustate, (op >> 0) & 0x1f) : REG24(cpustate, dr);
1502
int s1rval = REG24((op >> 5) & 0x1f);
1503
int s2rval = (op & 0x800) ? REG24((op >> 0) & 0x1f) : REG24(dr);
1484
1504
int res = s1rval - s2rval;
1485
1505
if (IS_WRITEABLE(dr))
1486
cpustate->r[dr] = TRUNCATE24(res);
1487
SET_NZCV_24(cpustate, s1rval, s2rval, res);
1506
m_r[dr] = TRUNCATE24(res);
1507
SET_NZCV_24(s1rval, s2rval, res);
1492
static void addre_ss(dsp32_state *cpustate, UINT32 op)
1512
void dsp32c_device::addre_ss(UINT32 op)
1494
unimplemented(cpustate, op);
1498
static void sube_ss(dsp32_state *cpustate, UINT32 op)
1518
void dsp32c_device::sube_ss(UINT32 op)
1500
if (CONDITION_IS_TRUE(cpustate))
1520
if (CONDITION_IS_TRUE())
1502
1522
int dr = (op >> 16) & 0x1f;
1503
int s1rval = REG24(cpustate, (op >> 5) & 0x1f);
1504
int s2rval = (op & 0x800) ? REG24(cpustate, (op >> 0) & 0x1f) : REG24(cpustate, dr);
1523
int s1rval = REG24((op >> 5) & 0x1f);
1524
int s2rval = (op & 0x800) ? REG24((op >> 0) & 0x1f) : REG24(dr);
1505
1525
int res = s2rval - s1rval;
1506
1526
if (IS_WRITEABLE(dr))
1507
cpustate->r[dr] = TRUNCATE24(res);
1508
SET_NZCV_24(cpustate, s1rval, s2rval, res);
1527
m_r[dr] = TRUNCATE24(res);
1528
SET_NZCV_24(s1rval, s2rval, res);
1513
static void nege_s(dsp32_state *cpustate, UINT32 op)
1533
void dsp32c_device::nege_s(UINT32 op)
1515
if (CONDITION_IS_TRUE(cpustate))
1535
if (CONDITION_IS_TRUE())
1517
1537
int dr = (op >> 16) & 0x1f;
1518
int s1rval = REG24(cpustate, (op >> 5) & 0x1f);
1538
int s1rval = REG24((op >> 5) & 0x1f);
1519
1539
int res = -s1rval;
1520
1540
if (IS_WRITEABLE(dr))
1521
cpustate->r[dr] = TRUNCATE24(res);
1522
SET_NZCV_24(cpustate, s1rval, 0, res);
1541
m_r[dr] = TRUNCATE24(res);
1542
SET_NZCV_24(s1rval, 0, res);
1527
static void andce_ss(dsp32_state *cpustate, UINT32 op)
1547
void dsp32c_device::andce_ss(UINT32 op)
1529
if (CONDITION_IS_TRUE(cpustate))
1549
if (CONDITION_IS_TRUE())
1531
1551
int dr = (op >> 16) & 0x1f;
1532
int s1rval = REG24(cpustate, (op >> 5) & 0x1f);
1533
int s2rval = (op & 0x800) ? REG24(cpustate, (op >> 0) & 0x1f) : REG24(cpustate, dr);
1552
int s1rval = REG24((op >> 5) & 0x1f);
1553
int s2rval = (op & 0x800) ? REG24((op >> 0) & 0x1f) : REG24(dr);
1534
1554
int res = s2rval & ~s1rval;
1535
1555
if (IS_WRITEABLE(dr))
1536
cpustate->r[dr] = res;
1537
SET_NZ00_24(cpustate, res);
1542
static void cmpe_ss(dsp32_state *cpustate, UINT32 op)
1562
void dsp32c_device::cmpe_ss(UINT32 op)
1544
if (CONDITION_IS_TRUE(cpustate))
1564
if (CONDITION_IS_TRUE())
1546
int drval = REG24(cpustate, (op >> 16) & 0x1f);
1547
int s1rval = REG24(cpustate, (op >> 5) & 0x1f);
1566
int drval = REG24((op >> 16) & 0x1f);
1567
int s1rval = REG24((op >> 5) & 0x1f);
1548
1568
int res = drval - s1rval;
1549
SET_NZCV_24(cpustate, drval, s1rval, res);
1569
SET_NZCV_24(drval, s1rval, res);
1554
static void xore_ss(dsp32_state *cpustate, UINT32 op)
1574
void dsp32c_device::xore_ss(UINT32 op)
1556
if (CONDITION_IS_TRUE(cpustate))
1576
if (CONDITION_IS_TRUE())
1558
1578
int dr = (op >> 16) & 0x1f;
1559
int s1rval = REG24(cpustate, (op >> 5) & 0x1f);
1560
int s2rval = (op & 0x800) ? REG24(cpustate, (op >> 0) & 0x1f) : REG24(cpustate, dr);
1579
int s1rval = REG24((op >> 5) & 0x1f);
1580
int s2rval = (op & 0x800) ? REG24((op >> 0) & 0x1f) : REG24(dr);
1561
1581
int res = s2rval ^ s1rval;
1562
1582
if (IS_WRITEABLE(dr))
1563
cpustate->r[dr] = res;
1564
SET_NZ00_24(cpustate, res);
1569
static void rcre_s(dsp32_state *cpustate, UINT32 op)
1589
void dsp32c_device::rcre_s(UINT32 op)
1571
if (CONDITION_IS_TRUE(cpustate))
1591
if (CONDITION_IS_TRUE())
1573
1593
int dr = (op >> 16) & 0x1f;
1574
int s1rval = REG24(cpustate, (op >> 5) & 0x1f);
1575
int res = ((cpustate->nzcflags >> 1) & 0x800000) | (s1rval >> 1);
1594
int s1rval = REG24((op >> 5) & 0x1f);
1595
int res = ((m_nzcflags >> 1) & 0x800000) | (s1rval >> 1);
1576
1596
if (IS_WRITEABLE(dr))
1577
cpustate->r[dr] = TRUNCATE24(res);
1578
cpustate->nzcflags = res | ((s1rval & 1) << 24);
1579
cpustate->vflags = 0;
1597
m_r[dr] = TRUNCATE24(res);
1598
m_nzcflags = res | ((s1rval & 1) << 24);
1584
static void ore_ss(dsp32_state *cpustate, UINT32 op)
1604
void dsp32c_device::ore_ss(UINT32 op)
1586
if (CONDITION_IS_TRUE(cpustate))
1606
if (CONDITION_IS_TRUE())
1588
1608
int dr = (op >> 16) & 0x1f;
1589
int s1rval = REG24(cpustate, (op >> 5) & 0x1f);
1590
int s2rval = (op & 0x800) ? REG24(cpustate, (op >> 0) & 0x1f) : REG24(cpustate, dr);
1609
int s1rval = REG24((op >> 5) & 0x1f);
1610
int s2rval = (op & 0x800) ? REG24((op >> 0) & 0x1f) : REG24(dr);
1591
1611
int res = s2rval | s1rval;
1592
1612
if (IS_WRITEABLE(dr))
1593
cpustate->r[dr] = res;
1594
SET_NZ00_24(cpustate, res);
1599
static void rcle_s(dsp32_state *cpustate, UINT32 op)
1619
void dsp32c_device::rcle_s(UINT32 op)
1601
if (CONDITION_IS_TRUE(cpustate))
1621
if (CONDITION_IS_TRUE())
1603
1623
int dr = (op >> 16) & 0x1f;
1604
int s1rval = REG24(cpustate, (op >> 5) & 0x1f);
1605
int res = ((cpustate->nzcflags >> 24) & 0x000001) | (s1rval << 1);
1624
int s1rval = REG24((op >> 5) & 0x1f);
1625
int res = ((m_nzcflags >> 24) & 0x000001) | (s1rval << 1);
1606
1626
if (IS_WRITEABLE(dr))
1607
cpustate->r[dr] = TRUNCATE24(res);
1608
cpustate->nzcflags = res | ((s1rval & 0x800000) << 1);
1609
cpustate->vflags = 0;
1627
m_r[dr] = TRUNCATE24(res);
1628
m_nzcflags = res | ((s1rval & 0x800000) << 1);
1614
static void shre_s(dsp32_state *cpustate, UINT32 op)
1634
void dsp32c_device::shre_s(UINT32 op)
1616
if (CONDITION_IS_TRUE(cpustate))
1636
if (CONDITION_IS_TRUE())
1618
1638
int dr = (op >> 16) & 0x1f;
1619
int s1rval = REG24(cpustate, (op >> 5) & 0x1f);
1639
int s1rval = REG24((op >> 5) & 0x1f);
1620
1640
int res = s1rval >> 1;
1621
1641
if (IS_WRITEABLE(dr))
1622
cpustate->r[dr] = res;
1623
cpustate->nzcflags = res | ((s1rval & 1) << 24);
1624
cpustate->vflags = 0;
1643
m_nzcflags = res | ((s1rval & 1) << 24);
1629
static void div2e_s(dsp32_state *cpustate, UINT32 op)
1649
void dsp32c_device::div2e_s(UINT32 op)
1631
if (CONDITION_IS_TRUE(cpustate))
1651
if (CONDITION_IS_TRUE())
1633
1653
int dr = (op >> 16) & 0x1f;
1634
int s1rval = REG24(cpustate, (op >> 5) & 0x1f);
1654
int s1rval = REG24((op >> 5) & 0x1f);
1635
1655
int res = (s1rval & 0x800000) | (s1rval >> 1);
1636
1656
if (IS_WRITEABLE(dr))
1637
cpustate->r[dr] = TRUNCATE24(res);
1638
cpustate->nzcflags = res | ((s1rval & 1) << 24);
1639
cpustate->vflags = 0;
1657
m_r[dr] = TRUNCATE24(res);
1658
m_nzcflags = res | ((s1rval & 1) << 24);
1644
static void ande_ss(dsp32_state *cpustate, UINT32 op)
1664
void dsp32c_device::ande_ss(UINT32 op)
1646
if (CONDITION_IS_TRUE(cpustate))
1666
if (CONDITION_IS_TRUE())
1648
1668
int dr = (op >> 16) & 0x1f;
1649
int s1rval = REG24(cpustate, (op >> 5) & 0x1f);
1650
int s2rval = (op & 0x800) ? REG24(cpustate, (op >> 0) & 0x1f) : REG24(cpustate, dr);
1669
int s1rval = REG24((op >> 5) & 0x1f);
1670
int s2rval = (op & 0x800) ? REG24((op >> 0) & 0x1f) : REG24(dr);
1651
1671
int res = s2rval & s1rval;
1652
1672
if (IS_WRITEABLE(dr))
1653
cpustate->r[dr] = res;
1654
SET_NZ00_24(cpustate, res);
1659
static void teste_ss(dsp32_state *cpustate, UINT32 op)
1679
void dsp32c_device::teste_ss(UINT32 op)
1661
if (CONDITION_IS_TRUE(cpustate))
1681
if (CONDITION_IS_TRUE())
1663
int drval = REG24(cpustate, (op >> 16) & 0x1f);
1664
int s1rval = REG24(cpustate, (op >> 5) & 0x1f);
1683
int drval = REG24((op >> 16) & 0x1f);
1684
int s1rval = REG24((op >> 5) & 0x1f);
1665
1685
int res = drval & s1rval;
1666
SET_NZ00_24(cpustate, res);
1671
static void adde_di(dsp32_state *cpustate, UINT32 op)
1691
void dsp32c_device::adde_di(UINT32 op)
1673
1693
int dr = (op >> 16) & 0x1f;
1674
int drval = REG24(cpustate, dr);
1694
int drval = REG24(dr);
1675
1695
int res = drval + EXTEND16_TO_24(op);
1676
1696
if (IS_WRITEABLE(dr))
1677
cpustate->r[dr] = TRUNCATE24(res);
1678
SET_NZCV_24(cpustate, drval, op << 8, res);
1697
m_r[dr] = TRUNCATE24(res);
1698
SET_NZCV_24(drval, op << 8, res);
1682
static void subre_di(dsp32_state *cpustate, UINT32 op)
1702
void dsp32c_device::subre_di(UINT32 op)
1684
1704
int dr = (op >> 16) & 0x1f;
1685
int drval = REG24(cpustate, dr);
1705
int drval = REG24(dr);
1686
1706
int res = EXTEND16_TO_24(op) - drval;
1687
1707
if (IS_WRITEABLE(dr))
1688
cpustate->r[dr] = TRUNCATE24(res);
1689
SET_NZCV_24(cpustate, drval, op << 8, res);
1708
m_r[dr] = TRUNCATE24(res);
1709
SET_NZCV_24(drval, op << 8, res);
1693
static void addre_di(dsp32_state *cpustate, UINT32 op)
1713
void dsp32c_device::addre_di(UINT32 op)
1695
unimplemented(cpustate, op);
1699
static void sube_di(dsp32_state *cpustate, UINT32 op)
1719
void dsp32c_device::sube_di(UINT32 op)
1701
1721
int dr = (op >> 16) & 0x1f;
1702
int drval = REG24(cpustate, dr);
1722
int drval = REG24(dr);
1703
1723
int res = drval - EXTEND16_TO_24(op);
1704
1724
if (IS_WRITEABLE(dr))
1705
cpustate->r[dr] = TRUNCATE24(res);
1706
SET_NZCV_24(cpustate, drval, op << 8, res);
1725
m_r[dr] = TRUNCATE24(res);
1726
SET_NZCV_24(drval, op << 8, res);
1710
static void andce_di(dsp32_state *cpustate, UINT32 op)
1730
void dsp32c_device::andce_di(UINT32 op)
1712
1732
int dr = (op >> 16) & 0x1f;
1713
int drval = REG24(cpustate, dr);
1733
int drval = REG24(dr);
1714
1734
int res = drval & ~EXTEND16_TO_24(op);
1715
1735
if (IS_WRITEABLE(dr))
1716
cpustate->r[dr] = res;
1717
SET_NZ00_24(cpustate, res);
1721
static void cmpe_di(dsp32_state *cpustate, UINT32 op)
1741
void dsp32c_device::cmpe_di(UINT32 op)
1723
int drval = REG24(cpustate, (op >> 16) & 0x1f);
1743
int drval = REG24((op >> 16) & 0x1f);
1724
1744
int res = drval - EXTEND16_TO_24(op);
1725
SET_NZCV_24(cpustate, drval, op << 8, res);
1745
SET_NZCV_24(drval, op << 8, res);
1729
static void xore_di(dsp32_state *cpustate, UINT32 op)
1749
void dsp32c_device::xore_di(UINT32 op)
1731
1751
int dr = (op >> 16) & 0x1f;
1732
int drval = REG24(cpustate, dr);
1752
int drval = REG24(dr);
1733
1753
int res = drval ^ EXTEND16_TO_24(op);
1734
1754
if (IS_WRITEABLE(dr))
1735
cpustate->r[dr] = res;
1736
SET_NZ00_24(cpustate, res);
1740
static void ore_di(dsp32_state *cpustate, UINT32 op)
1760
void dsp32c_device::ore_di(UINT32 op)
1742
1762
int dr = (op >> 16) & 0x1f;
1743
int drval = REG24(cpustate, dr);
1763
int drval = REG24(dr);
1744
1764
int res = drval | EXTEND16_TO_24(op);
1745
1765
if (IS_WRITEABLE(dr))
1746
cpustate->r[dr] = res;
1747
SET_NZ00_24(cpustate, res);
1751
static void ande_di(dsp32_state *cpustate, UINT32 op)
1753
int dr = (op >> 16) & 0x1f;
1754
int drval = REG24(cpustate, dr);
1755
int res = drval & EXTEND16_TO_24(op);
1756
if (IS_WRITEABLE(dr))
1757
cpustate->r[dr] = res;
1758
SET_NZ00_24(cpustate, res);
1762
static void teste_di(dsp32_state *cpustate, UINT32 op)
1764
int drval = REG24(cpustate, (op >> 16) & 0x1f);
1765
int res = drval & EXTEND16_TO_24(op);
1766
SET_NZ00_24(cpustate, res);
1771
/***************************************************************************
1772
CAU LOAD/STORE IMPLEMENTATION
1773
***************************************************************************/
1775
static void load_hi(dsp32_state *cpustate, UINT32 op)
1777
int dr = (op >> 16) & 0x1f;
1778
UINT32 res = RBYTE(cpustate, EXTEND16_TO_24(op));
1779
if (IS_WRITEABLE(dr))
1780
cpustate->r[dr] = EXTEND16_TO_24(res);
1781
cpustate->nzcflags = res << 8;
1782
cpustate->vflags = 0;
1786
static void load_li(dsp32_state *cpustate, UINT32 op)
1788
int dr = (op >> 16) & 0x1f;
1789
UINT32 res = RBYTE(cpustate, EXTEND16_TO_24(op));
1790
if (IS_WRITEABLE(dr))
1791
cpustate->r[dr] = res;
1792
cpustate->nzcflags = res << 8;
1793
cpustate->vflags = 0;
1797
static void load_i(dsp32_state *cpustate, UINT32 op)
1799
UINT32 res = RWORD(cpustate, EXTEND16_TO_24(op));
1800
int dr = (op >> 16) & 0x1f;
1801
if (IS_WRITEABLE(dr))
1802
cpustate->r[dr] = EXTEND16_TO_24(res);
1803
cpustate->nzcflags = res << 8;
1804
cpustate->vflags = 0;
1808
static void load_ei(dsp32_state *cpustate, UINT32 op)
1810
UINT32 res = TRUNCATE24(RLONG(cpustate, EXTEND16_TO_24(op)));
1811
int dr = (op >> 16) & 0x1f;
1812
if (IS_WRITEABLE(dr))
1813
cpustate->r[dr] = res;
1814
cpustate->nzcflags = res;
1815
cpustate->vflags = 0;
1819
static void store_hi(dsp32_state *cpustate, UINT32 op)
1821
WBYTE(cpustate, EXTEND16_TO_24(op), cpustate->r[(op >> 16) & 0x1f] >> 8);
1825
static void store_li(dsp32_state *cpustate, UINT32 op)
1827
WBYTE(cpustate, EXTEND16_TO_24(op), cpustate->r[(op >> 16) & 0x1f]);
1831
static void store_i(dsp32_state *cpustate, UINT32 op)
1833
WWORD(cpustate, EXTEND16_TO_24(op), REG16(cpustate, (op >> 16) & 0x1f));
1837
static void store_ei(dsp32_state *cpustate, UINT32 op)
1839
WLONG(cpustate, EXTEND16_TO_24(op), (INT32)(REG24(cpustate, (op >> 16) & 0x1f) << 8) >> 8);
1843
static void load_hr(dsp32_state *cpustate, UINT32 op)
1847
int dr = (op >> 16) & 0x1f;
1848
UINT32 res = cau_read_pi_1byte(cpustate, op) << 8;
1849
if (IS_WRITEABLE(dr))
1850
cpustate->r[dr] = EXTEND16_TO_24(res);
1851
cpustate->nzcflags = res << 8;
1852
cpustate->vflags = 0;
1855
unimplemented(cpustate, op);
1859
static void load_lr(dsp32_state *cpustate, UINT32 op)
1863
int dr = (op >> 16) & 0x1f;
1864
UINT32 res = cau_read_pi_1byte(cpustate, op);
1865
if (IS_WRITEABLE(dr))
1866
cpustate->r[dr] = res;
1867
cpustate->nzcflags = res << 8;
1868
cpustate->vflags = 0;
1871
unimplemented(cpustate, op);
1875
static void load_r(dsp32_state *cpustate, UINT32 op)
1879
UINT32 res = cau_read_pi_2byte(cpustate, op);
1880
int dr = (op >> 16) & 0x1f;
1881
if (IS_WRITEABLE(dr))
1882
cpustate->r[dr] = EXTEND16_TO_24(res);
1883
cpustate->nzcflags = res << 8;
1884
cpustate->vflags = 0;
1887
unimplemented(cpustate, op);
1891
static void load_er(dsp32_state *cpustate, UINT32 op)
1895
UINT32 res = TRUNCATE24(cau_read_pi_4byte(cpustate, op));
1896
int dr = (op >> 16) & 0x1f;
1897
if (IS_WRITEABLE(dr))
1898
cpustate->r[dr] = res;
1899
cpustate->nzcflags = res;
1900
cpustate->vflags = 0;
1903
unimplemented(cpustate, op);
1907
static void store_hr(dsp32_state *cpustate, UINT32 op)
1910
cau_write_pi_1byte(cpustate, op, cpustate->r[(op >> 16) & 0x1f] >> 8);
1912
unimplemented(cpustate, op);
1916
static void store_lr(dsp32_state *cpustate, UINT32 op)
1919
cau_write_pi_1byte(cpustate, op, cpustate->r[(op >> 16) & 0x1f]);
1921
unimplemented(cpustate, op);
1925
static void store_r(dsp32_state *cpustate, UINT32 op)
1928
cau_write_pi_2byte(cpustate, op, REG16(cpustate, (op >> 16) & 0x1f));
1930
unimplemented(cpustate, op);
1934
static void store_er(dsp32_state *cpustate, UINT32 op)
1937
cau_write_pi_4byte(cpustate, op, REG24(cpustate, (op >> 16) & 0x1f));
1939
unimplemented(cpustate, op);
1943
static void load24(dsp32_state *cpustate, UINT32 op)
1771
void dsp32c_device::ande_di(UINT32 op)
1773
int dr = (op >> 16) & 0x1f;
1774
int drval = REG24(dr);
1775
int res = drval & EXTEND16_TO_24(op);
1776
if (IS_WRITEABLE(dr))
1782
void dsp32c_device::teste_di(UINT32 op)
1784
int drval = REG24((op >> 16) & 0x1f);
1785
int res = drval & EXTEND16_TO_24(op);
1791
//**************************************************************************
1792
// CAU LOAD/STORE IMPLEMENTATION
1793
//**************************************************************************
1795
void dsp32c_device::load_hi(UINT32 op)
1797
int dr = (op >> 16) & 0x1f;
1798
UINT32 res = RBYTE(EXTEND16_TO_24(op));
1799
if (IS_WRITEABLE(dr))
1800
m_r[dr] = EXTEND16_TO_24(res);
1801
m_nzcflags = res << 8;
1806
void dsp32c_device::load_li(UINT32 op)
1808
int dr = (op >> 16) & 0x1f;
1809
UINT32 res = RBYTE(EXTEND16_TO_24(op));
1810
if (IS_WRITEABLE(dr))
1812
m_nzcflags = res << 8;
1817
void dsp32c_device::load_i(UINT32 op)
1819
UINT32 res = RWORD(EXTEND16_TO_24(op));
1820
int dr = (op >> 16) & 0x1f;
1821
if (IS_WRITEABLE(dr))
1822
m_r[dr] = EXTEND16_TO_24(res);
1823
m_nzcflags = res << 8;
1828
void dsp32c_device::load_ei(UINT32 op)
1830
UINT32 res = TRUNCATE24(RLONG(EXTEND16_TO_24(op)));
1831
int dr = (op >> 16) & 0x1f;
1832
if (IS_WRITEABLE(dr))
1839
void dsp32c_device::store_hi(UINT32 op)
1841
WBYTE(EXTEND16_TO_24(op), m_r[(op >> 16) & 0x1f] >> 8);
1845
void dsp32c_device::store_li(UINT32 op)
1847
WBYTE(EXTEND16_TO_24(op), m_r[(op >> 16) & 0x1f]);
1851
void dsp32c_device::store_i(UINT32 op)
1853
WWORD(EXTEND16_TO_24(op), REG16((op >> 16) & 0x1f));
1857
void dsp32c_device::store_ei(UINT32 op)
1859
WLONG(EXTEND16_TO_24(op), (INT32)(REG24((op >> 16) & 0x1f) << 8) >> 8);
1863
void dsp32c_device::load_hr(UINT32 op)
1867
int dr = (op >> 16) & 0x1f;
1868
UINT32 res = cau_read_pi_1byte(op) << 8;
1869
if (IS_WRITEABLE(dr))
1870
m_r[dr] = EXTEND16_TO_24(res);
1871
m_nzcflags = res << 8;
1879
void dsp32c_device::load_lr(UINT32 op)
1883
int dr = (op >> 16) & 0x1f;
1884
UINT32 res = cau_read_pi_1byte(op);
1885
if (IS_WRITEABLE(dr))
1887
m_nzcflags = res << 8;
1895
void dsp32c_device::load_r(UINT32 op)
1899
UINT32 res = cau_read_pi_2byte(op);
1900
int dr = (op >> 16) & 0x1f;
1901
if (IS_WRITEABLE(dr))
1902
m_r[dr] = EXTEND16_TO_24(res);
1903
m_nzcflags = res << 8;
1911
void dsp32c_device::load_er(UINT32 op)
1915
UINT32 res = TRUNCATE24(cau_read_pi_4byte(op));
1916
int dr = (op >> 16) & 0x1f;
1917
if (IS_WRITEABLE(dr))
1927
void dsp32c_device::store_hr(UINT32 op)
1930
cau_write_pi_1byte(op, m_r[(op >> 16) & 0x1f] >> 8);
1936
void dsp32c_device::store_lr(UINT32 op)
1939
cau_write_pi_1byte(op, m_r[(op >> 16) & 0x1f]);
1945
void dsp32c_device::store_r(UINT32 op)
1948
cau_write_pi_2byte(op, REG16((op >> 16) & 0x1f));
1954
void dsp32c_device::store_er(UINT32 op)
1957
cau_write_pi_4byte(op, REG24((op >> 16) & 0x1f));
1963
void dsp32c_device::load24(UINT32 op)
1945
1965
int dr = (op >> 16) & 0x1f;
1946
1966
UINT32 res = (op & 0xffff) + ((op >> 5) & 0xff0000);
1947
1967
if (IS_WRITEABLE(dr))
1948
cpustate->r[dr] = res;
1953
/***************************************************************************
1954
DAU FORM 1 IMPLEMENTATION
1955
***************************************************************************/
1957
static void d1_aMpp(dsp32_state *cpustate, UINT32 op)
1959
double xval = dau_read_pi_double_1st(cpustate, op >> 14, 1);
1960
double yval = dau_read_pi_double_2nd(cpustate, op >> 7, 0, xval);
1961
double res = yval + DEFERRED_MULTIPLIER(cpustate, (op >> 26) & 7) * xval;
1962
int zpi = (op >> 0) & 0x7f;
1964
dau_write_pi_double(cpustate, zpi, res);
1965
dau_set_val_flags(cpustate, (op >> 21) & 3, res);
1969
static void d1_aMpm(dsp32_state *cpustate, UINT32 op)
1971
double xval = dau_read_pi_double_1st(cpustate, op >> 14, 1);
1972
double yval = dau_read_pi_double_2nd(cpustate, op >> 7, 0, xval);
1973
double res = yval - DEFERRED_MULTIPLIER(cpustate, (op >> 26) & 7) * xval;
1974
int zpi = (op >> 0) & 0x7f;
1976
dau_write_pi_double(cpustate, zpi, res);
1977
dau_set_val_flags(cpustate, (op >> 21) & 3, res);
1981
static void d1_aMmp(dsp32_state *cpustate, UINT32 op)
1983
double xval = dau_read_pi_double_1st(cpustate, op >> 14, 1);
1984
double yval = dau_read_pi_double_2nd(cpustate, op >> 7, 0, xval);
1985
double res = -yval + DEFERRED_MULTIPLIER(cpustate, (op >> 26) & 7) * xval;
1986
int zpi = (op >> 0) & 0x7f;
1988
dau_write_pi_double(cpustate, zpi, res);
1989
dau_set_val_flags(cpustate, (op >> 21) & 3, res);
1993
static void d1_aMmm(dsp32_state *cpustate, UINT32 op)
1995
double xval = dau_read_pi_double_1st(cpustate, op >> 14, 1);
1996
double yval = dau_read_pi_double_2nd(cpustate, op >> 7, 0, xval);
1997
double res = -yval - DEFERRED_MULTIPLIER(cpustate, (op >> 26) & 7) * xval;
1998
int zpi = (op >> 0) & 0x7f;
2000
dau_write_pi_double(cpustate, zpi, res);
2001
dau_set_val_flags(cpustate, (op >> 21) & 3, res);
2005
static void d1_0px(dsp32_state *cpustate, UINT32 op)
2007
double xval = dau_read_pi_double_1st(cpustate, op >> 14, 1);
2008
double yval = dau_read_pi_double_2nd(cpustate, op >> 7, 0, xval);
1973
//**************************************************************************
1974
// DAU FORM 1 IMPLEMENTATION
1975
//**************************************************************************
1977
void dsp32c_device::d1_aMpp(UINT32 op)
1979
double xval = dau_read_pi_double_1st(op >> 14, 1);
1980
double yval = dau_read_pi_double_2nd(op >> 7, 0, xval);
1981
double res = yval + DEFERRED_MULTIPLIER((op >> 26) & 7) * xval;
1982
int zpi = (op >> 0) & 0x7f;
1984
dau_write_pi_double(zpi, res);
1985
dau_set_val_flags((op >> 21) & 3, res);
1989
void dsp32c_device::d1_aMpm(UINT32 op)
1991
double xval = dau_read_pi_double_1st(op >> 14, 1);
1992
double yval = dau_read_pi_double_2nd(op >> 7, 0, xval);
1993
double res = yval - DEFERRED_MULTIPLIER((op >> 26) & 7) * xval;
1994
int zpi = (op >> 0) & 0x7f;
1996
dau_write_pi_double(zpi, res);
1997
dau_set_val_flags((op >> 21) & 3, res);
2001
void dsp32c_device::d1_aMmp(UINT32 op)
2003
double xval = dau_read_pi_double_1st(op >> 14, 1);
2004
double yval = dau_read_pi_double_2nd(op >> 7, 0, xval);
2005
double res = -yval + DEFERRED_MULTIPLIER((op >> 26) & 7) * xval;
2006
int zpi = (op >> 0) & 0x7f;
2008
dau_write_pi_double(zpi, res);
2009
dau_set_val_flags((op >> 21) & 3, res);
2013
void dsp32c_device::d1_aMmm(UINT32 op)
2015
double xval = dau_read_pi_double_1st(op >> 14, 1);
2016
double yval = dau_read_pi_double_2nd(op >> 7, 0, xval);
2017
double res = -yval - DEFERRED_MULTIPLIER((op >> 26) & 7) * xval;
2018
int zpi = (op >> 0) & 0x7f;
2020
dau_write_pi_double(zpi, res);
2021
dau_set_val_flags((op >> 21) & 3, res);
2025
void dsp32c_device::d1_0px(UINT32 op)
2027
double xval = dau_read_pi_double_1st(op >> 14, 1);
2028
double yval = dau_read_pi_double_2nd(op >> 7, 0, xval);
2009
2029
double res = yval;
2010
2030
int zpi = (op >> 0) & 0x7f;
2012
dau_write_pi_double(cpustate, zpi, res);
2013
dau_set_val_flags(cpustate, (op >> 21) & 3, res);
2032
dau_write_pi_double(zpi, res);
2033
dau_set_val_flags((op >> 21) & 3, res);
2018
static void d1_0mx(dsp32_state *cpustate, UINT32 op)
2038
void dsp32c_device::d1_0mx(UINT32 op)
2020
double xval = dau_read_pi_double_1st(cpustate, op >> 14, 1);
2021
double yval = dau_read_pi_double_2nd(cpustate, op >> 7, 0, xval);
2040
double xval = dau_read_pi_double_1st(op >> 14, 1);
2041
double yval = dau_read_pi_double_2nd(op >> 7, 0, xval);
2022
2042
double res = -yval;
2023
2043
int zpi = (op >> 0) & 0x7f;
2025
dau_write_pi_double(cpustate, zpi, res);
2026
dau_set_val_flags(cpustate, (op >> 21) & 3, res);
2045
dau_write_pi_double(zpi, res);
2046
dau_set_val_flags((op >> 21) & 3, res);
2031
static void d1_1pp(dsp32_state *cpustate, UINT32 op)
2033
double xval = dau_read_pi_double_1st(cpustate, op >> 14, 1);
2034
double yval = dau_read_pi_double_2nd(cpustate, op >> 7, 0, xval);
2035
double res = yval + xval;
2036
int zpi = (op >> 0) & 0x7f;
2038
dau_write_pi_double(cpustate, zpi, res);
2039
dau_set_val_flags(cpustate, (op >> 21) & 3, res);
2043
static void d1_1pm(dsp32_state *cpustate, UINT32 op)
2045
double xval = dau_read_pi_double_1st(cpustate, op >> 14, 1);
2046
double yval = dau_read_pi_double_2nd(cpustate, op >> 7, 0, xval);
2047
double res = yval - xval;
2048
int zpi = (op >> 0) & 0x7f;
2050
dau_write_pi_double(cpustate, zpi, res);
2051
dau_set_val_flags(cpustate, (op >> 21) & 3, res);
2055
static void d1_1mp(dsp32_state *cpustate, UINT32 op)
2057
double xval = dau_read_pi_double_1st(cpustate, op >> 14, 1);
2058
double yval = dau_read_pi_double_2nd(cpustate, op >> 7, 0, xval);
2059
double res = -yval + xval;
2060
int zpi = (op >> 0) & 0x7f;
2062
dau_write_pi_double(cpustate, zpi, res);
2063
dau_set_val_flags(cpustate, (op >> 21) & 3, res);
2067
static void d1_1mm(dsp32_state *cpustate, UINT32 op)
2069
double xval = dau_read_pi_double_1st(cpustate, op >> 14, 1);
2070
double yval = dau_read_pi_double_2nd(cpustate, op >> 7, 0, xval);
2071
double res = -yval - xval;
2072
int zpi = (op >> 0) & 0x7f;
2074
dau_write_pi_double(cpustate, zpi, res);
2075
dau_set_val_flags(cpustate, (op >> 21) & 3, res);
2079
static void d1_aMppr(dsp32_state *cpustate, UINT32 op)
2081
unimplemented(cpustate, op);
2085
static void d1_aMpmr(dsp32_state *cpustate, UINT32 op)
2087
unimplemented(cpustate, op);
2091
static void d1_aMmpr(dsp32_state *cpustate, UINT32 op)
2093
unimplemented(cpustate, op);
2097
static void d1_aMmmr(dsp32_state *cpustate, UINT32 op)
2099
unimplemented(cpustate, op);
2104
/***************************************************************************
2105
DAU FORM 2 IMPLEMENTATION
2106
***************************************************************************/
2108
static void d2_aMpp(dsp32_state *cpustate, UINT32 op)
2110
double xval = dau_read_pi_double_1st(cpustate, op >> 14, 1);
2111
double yval = dau_read_pi_double_2nd(cpustate, op >> 7, 1, xval);
2112
double res = cpustate->a[(op >> 26) & 7] + yval * xval;
2113
int zpi = (op >> 0) & 0x7f;
2115
dau_write_pi_double(cpustate, zpi, yval);
2116
dau_set_val_flags(cpustate, (op >> 21) & 3, res);
2120
static void d2_aMpm(dsp32_state *cpustate, UINT32 op)
2122
double xval = dau_read_pi_double_1st(cpustate, op >> 14, 1);
2123
double yval = dau_read_pi_double_2nd(cpustate, op >> 7, 1, xval);
2124
double res = cpustate->a[(op >> 26) & 7] - yval * xval;
2125
int zpi = (op >> 0) & 0x7f;
2127
dau_write_pi_double(cpustate, zpi, yval);
2128
dau_set_val_flags(cpustate, (op >> 21) & 3, res);
2132
static void d2_aMmp(dsp32_state *cpustate, UINT32 op)
2134
double xval = dau_read_pi_double_1st(cpustate, op >> 14, 1);
2135
double yval = dau_read_pi_double_2nd(cpustate, op >> 7, 1, xval);
2136
double res = -cpustate->a[(op >> 26) & 7] + yval * xval;
2137
int zpi = (op >> 0) & 0x7f;
2139
dau_write_pi_double(cpustate, zpi, yval);
2140
dau_set_val_flags(cpustate, (op >> 21) & 3, res);
2144
static void d2_aMmm(dsp32_state *cpustate, UINT32 op)
2146
double xval = dau_read_pi_double_1st(cpustate, op >> 14, 1);
2147
double yval = dau_read_pi_double_2nd(cpustate, op >> 7, 1, xval);
2148
double res = -cpustate->a[(op >> 26) & 7] - yval * xval;
2149
int zpi = (op >> 0) & 0x7f;
2151
dau_write_pi_double(cpustate, zpi, yval);
2152
dau_set_val_flags(cpustate, (op >> 21) & 3, res);
2156
static void d2_aMppr(dsp32_state *cpustate, UINT32 op)
2158
unimplemented(cpustate, op);
2162
static void d2_aMpmr(dsp32_state *cpustate, UINT32 op)
2164
unimplemented(cpustate, op);
2168
static void d2_aMmpr(dsp32_state *cpustate, UINT32 op)
2170
unimplemented(cpustate, op);
2174
static void d2_aMmmr(dsp32_state *cpustate, UINT32 op)
2176
unimplemented(cpustate, op);
2181
/***************************************************************************
2182
DAU FORM 3 IMPLEMENTATION
2183
***************************************************************************/
2185
static void d3_aMpp(dsp32_state *cpustate, UINT32 op)
2187
double xval = dau_read_pi_double_1st(cpustate, op >> 14, 1);
2188
double yval = dau_read_pi_double_2nd(cpustate, op >> 7, 1, xval);
2189
double res = cpustate->a[(op >> 26) & 7] + yval * xval;
2190
int zpi = (op >> 0) & 0x7f;
2192
dau_write_pi_double(cpustate, zpi, res);
2193
dau_set_val_flags(cpustate, (op >> 21) & 3, res);
2197
static void d3_aMpm(dsp32_state *cpustate, UINT32 op)
2199
double xval = dau_read_pi_double_1st(cpustate, op >> 14, 1);
2200
double yval = dau_read_pi_double_2nd(cpustate, op >> 7, 1, xval);
2201
double res = cpustate->a[(op >> 26) & 7] - yval * xval;
2202
int zpi = (op >> 0) & 0x7f;
2204
dau_write_pi_double(cpustate, zpi, res);
2205
dau_set_val_flags(cpustate, (op >> 21) & 3, res);
2209
static void d3_aMmp(dsp32_state *cpustate, UINT32 op)
2211
double xval = dau_read_pi_double_1st(cpustate, op >> 14, 1);
2212
double yval = dau_read_pi_double_2nd(cpustate, op >> 7, 1, xval);
2213
double res = -cpustate->a[(op >> 26) & 7] + yval * xval;
2214
int zpi = (op >> 0) & 0x7f;
2216
dau_write_pi_double(cpustate, zpi, res);
2217
dau_set_val_flags(cpustate, (op >> 21) & 3, res);
2221
static void d3_aMmm(dsp32_state *cpustate, UINT32 op)
2223
double xval = dau_read_pi_double_1st(cpustate, op >> 14, 1);
2224
double yval = dau_read_pi_double_2nd(cpustate, op >> 7, 1, xval);
2225
double res = -cpustate->a[(op >> 26) & 7] - yval * xval;
2226
int zpi = (op >> 0) & 0x7f;
2228
dau_write_pi_double(cpustate, zpi, res);
2229
dau_set_val_flags(cpustate, (op >> 21) & 3, res);
2233
static void d3_aMppr(dsp32_state *cpustate, UINT32 op)
2235
unimplemented(cpustate, op);
2239
static void d3_aMpmr(dsp32_state *cpustate, UINT32 op)
2241
unimplemented(cpustate, op);
2245
static void d3_aMmpr(dsp32_state *cpustate, UINT32 op)
2247
unimplemented(cpustate, op);
2251
static void d3_aMmmr(dsp32_state *cpustate, UINT32 op)
2253
unimplemented(cpustate, op);
2258
/***************************************************************************
2259
DAU FORM 4 IMPLEMENTATION
2260
***************************************************************************/
2262
static void d4_pp(dsp32_state *cpustate, UINT32 op)
2264
double xval = dau_read_pi_double_1st(cpustate, op >> 14, 1);
2265
double yval = dau_read_pi_double_2nd(cpustate, op >> 7, 0, xval);
2266
double res = yval + xval;
2267
int zpi = (op >> 0) & 0x7f;
2269
dau_write_pi_double(cpustate, zpi, yval);
2270
dau_set_val_flags(cpustate, (op >> 21) & 3, res);
2274
static void d4_pm(dsp32_state *cpustate, UINT32 op)
2276
double xval = dau_read_pi_double_1st(cpustate, op >> 14, 1);
2277
double yval = dau_read_pi_double_2nd(cpustate, op >> 7, 0, xval);
2278
double res = yval - xval;
2279
int zpi = (op >> 0) & 0x7f;
2281
dau_write_pi_double(cpustate, zpi, yval);
2282
dau_set_val_flags(cpustate, (op >> 21) & 3, res);
2286
static void d4_mp(dsp32_state *cpustate, UINT32 op)
2288
double xval = dau_read_pi_double_1st(cpustate, op >> 14, 1);
2289
double yval = dau_read_pi_double_2nd(cpustate, op >> 7, 0, xval);
2290
double res = -yval + xval;
2291
int zpi = (op >> 0) & 0x7f;
2293
dau_write_pi_double(cpustate, zpi, yval);
2294
dau_set_val_flags(cpustate, (op >> 21) & 3, res);
2298
static void d4_mm(dsp32_state *cpustate, UINT32 op)
2300
double xval = dau_read_pi_double_1st(cpustate, op >> 14, 1);
2301
double yval = dau_read_pi_double_2nd(cpustate, op >> 7, 0, xval);
2302
double res = -yval - xval;
2303
int zpi = (op >> 0) & 0x7f;
2305
dau_write_pi_double(cpustate, zpi, yval);
2306
dau_set_val_flags(cpustate, (op >> 21) & 3, res);
2310
static void d4_ppr(dsp32_state *cpustate, UINT32 op)
2312
unimplemented(cpustate, op);
2316
static void d4_pmr(dsp32_state *cpustate, UINT32 op)
2318
unimplemented(cpustate, op);
2322
static void d4_mpr(dsp32_state *cpustate, UINT32 op)
2324
unimplemented(cpustate, op);
2328
static void d4_mmr(dsp32_state *cpustate, UINT32 op)
2330
unimplemented(cpustate, op);
2335
/***************************************************************************
2336
DAU FORM 5 IMPLEMENTATION
2337
***************************************************************************/
2339
static void d5_ic(dsp32_state *cpustate, UINT32 op)
2341
unimplemented(cpustate, op);
2345
static void d5_oc(dsp32_state *cpustate, UINT32 op)
2347
unimplemented(cpustate, op);
2351
static void d5_float(dsp32_state *cpustate, UINT32 op)
2353
double res = (double)(INT16)dau_read_pi_2bytes(cpustate, op >> 7);
2354
int zpi = (op >> 0) & 0x7f;
2356
dau_write_pi_double(cpustate, zpi, res);
2357
dau_set_val_flags(cpustate, (op >> 21) & 3, res);
2361
static void d5_int(dsp32_state *cpustate, UINT32 op)
2363
double val = dau_read_pi_double_1st(cpustate, op >> 7, 0);
2051
void dsp32c_device::d1_1pp(UINT32 op)
2053
double xval = dau_read_pi_double_1st(op >> 14, 1);
2054
double yval = dau_read_pi_double_2nd(op >> 7, 0, xval);
2055
double res = yval + xval;
2056
int zpi = (op >> 0) & 0x7f;
2058
dau_write_pi_double(zpi, res);
2059
dau_set_val_flags((op >> 21) & 3, res);
2063
void dsp32c_device::d1_1pm(UINT32 op)
2065
double xval = dau_read_pi_double_1st(op >> 14, 1);
2066
double yval = dau_read_pi_double_2nd(op >> 7, 0, xval);
2067
double res = yval - xval;
2068
int zpi = (op >> 0) & 0x7f;
2070
dau_write_pi_double(zpi, res);
2071
dau_set_val_flags((op >> 21) & 3, res);
2075
void dsp32c_device::d1_1mp(UINT32 op)
2077
double xval = dau_read_pi_double_1st(op >> 14, 1);
2078
double yval = dau_read_pi_double_2nd(op >> 7, 0, xval);
2079
double res = -yval + xval;
2080
int zpi = (op >> 0) & 0x7f;
2082
dau_write_pi_double(zpi, res);
2083
dau_set_val_flags((op >> 21) & 3, res);
2087
void dsp32c_device::d1_1mm(UINT32 op)
2089
double xval = dau_read_pi_double_1st(op >> 14, 1);
2090
double yval = dau_read_pi_double_2nd(op >> 7, 0, xval);
2091
double res = -yval - xval;
2092
int zpi = (op >> 0) & 0x7f;
2094
dau_write_pi_double(zpi, res);
2095
dau_set_val_flags((op >> 21) & 3, res);
2099
void dsp32c_device::d1_aMppr(UINT32 op)
2105
void dsp32c_device::d1_aMpmr(UINT32 op)
2111
void dsp32c_device::d1_aMmpr(UINT32 op)
2117
void dsp32c_device::d1_aMmmr(UINT32 op)
2124
//**************************************************************************
2125
// DAU FORM 2 IMPLEMENTATION
2126
//**************************************************************************
2128
void dsp32c_device::d2_aMpp(UINT32 op)
2130
double xval = dau_read_pi_double_1st(op >> 14, 1);
2131
double yval = dau_read_pi_double_2nd(op >> 7, 1, xval);
2132
double res = m_a[(op >> 26) & 7] + yval * xval;
2133
int zpi = (op >> 0) & 0x7f;
2135
dau_write_pi_double(zpi, yval);
2136
dau_set_val_flags((op >> 21) & 3, res);
2140
void dsp32c_device::d2_aMpm(UINT32 op)
2142
double xval = dau_read_pi_double_1st(op >> 14, 1);
2143
double yval = dau_read_pi_double_2nd(op >> 7, 1, xval);
2144
double res = m_a[(op >> 26) & 7] - yval * xval;
2145
int zpi = (op >> 0) & 0x7f;
2147
dau_write_pi_double(zpi, yval);
2148
dau_set_val_flags((op >> 21) & 3, res);
2152
void dsp32c_device::d2_aMmp(UINT32 op)
2154
double xval = dau_read_pi_double_1st(op >> 14, 1);
2155
double yval = dau_read_pi_double_2nd(op >> 7, 1, xval);
2156
double res = -m_a[(op >> 26) & 7] + yval * xval;
2157
int zpi = (op >> 0) & 0x7f;
2159
dau_write_pi_double(zpi, yval);
2160
dau_set_val_flags((op >> 21) & 3, res);
2164
void dsp32c_device::d2_aMmm(UINT32 op)
2166
double xval = dau_read_pi_double_1st(op >> 14, 1);
2167
double yval = dau_read_pi_double_2nd(op >> 7, 1, xval);
2168
double res = -m_a[(op >> 26) & 7] - yval * xval;
2169
int zpi = (op >> 0) & 0x7f;
2171
dau_write_pi_double(zpi, yval);
2172
dau_set_val_flags((op >> 21) & 3, res);
2176
void dsp32c_device::d2_aMppr(UINT32 op)
2182
void dsp32c_device::d2_aMpmr(UINT32 op)
2188
void dsp32c_device::d2_aMmpr(UINT32 op)
2194
void dsp32c_device::d2_aMmmr(UINT32 op)
2201
//**************************************************************************
2202
// DAU FORM 3 IMPLEMENTATION
2203
//**************************************************************************
2205
void dsp32c_device::d3_aMpp(UINT32 op)
2207
double xval = dau_read_pi_double_1st(op >> 14, 1);
2208
double yval = dau_read_pi_double_2nd(op >> 7, 1, xval);
2209
double res = m_a[(op >> 26) & 7] + yval * xval;
2210
int zpi = (op >> 0) & 0x7f;
2212
dau_write_pi_double(zpi, res);
2213
dau_set_val_flags((op >> 21) & 3, res);
2217
void dsp32c_device::d3_aMpm(UINT32 op)
2219
double xval = dau_read_pi_double_1st(op >> 14, 1);
2220
double yval = dau_read_pi_double_2nd(op >> 7, 1, xval);
2221
double res = m_a[(op >> 26) & 7] - yval * xval;
2222
int zpi = (op >> 0) & 0x7f;
2224
dau_write_pi_double(zpi, res);
2225
dau_set_val_flags((op >> 21) & 3, res);
2229
void dsp32c_device::d3_aMmp(UINT32 op)
2231
double xval = dau_read_pi_double_1st(op >> 14, 1);
2232
double yval = dau_read_pi_double_2nd(op >> 7, 1, xval);
2233
double res = -m_a[(op >> 26) & 7] + yval * xval;
2234
int zpi = (op >> 0) & 0x7f;
2236
dau_write_pi_double(zpi, res);
2237
dau_set_val_flags((op >> 21) & 3, res);
2241
void dsp32c_device::d3_aMmm(UINT32 op)
2243
double xval = dau_read_pi_double_1st(op >> 14, 1);
2244
double yval = dau_read_pi_double_2nd(op >> 7, 1, xval);
2245
double res = -m_a[(op >> 26) & 7] - yval * xval;
2246
int zpi = (op >> 0) & 0x7f;
2248
dau_write_pi_double(zpi, res);
2249
dau_set_val_flags((op >> 21) & 3, res);
2253
void dsp32c_device::d3_aMppr(UINT32 op)
2259
void dsp32c_device::d3_aMpmr(UINT32 op)
2265
void dsp32c_device::d3_aMmpr(UINT32 op)
2271
void dsp32c_device::d3_aMmmr(UINT32 op)
2278
//**************************************************************************
2279
// DAU FORM 4 IMPLEMENTATION
2280
//**************************************************************************
2282
void dsp32c_device::d4_pp(UINT32 op)
2284
double xval = dau_read_pi_double_1st(op >> 14, 1);
2285
double yval = dau_read_pi_double_2nd(op >> 7, 0, xval);
2286
double res = yval + xval;
2287
int zpi = (op >> 0) & 0x7f;
2289
dau_write_pi_double(zpi, yval);
2290
dau_set_val_flags((op >> 21) & 3, res);
2294
void dsp32c_device::d4_pm(UINT32 op)
2296
double xval = dau_read_pi_double_1st(op >> 14, 1);
2297
double yval = dau_read_pi_double_2nd(op >> 7, 0, xval);
2298
double res = yval - xval;
2299
int zpi = (op >> 0) & 0x7f;
2301
dau_write_pi_double(zpi, yval);
2302
dau_set_val_flags((op >> 21) & 3, res);
2306
void dsp32c_device::d4_mp(UINT32 op)
2308
double xval = dau_read_pi_double_1st(op >> 14, 1);
2309
double yval = dau_read_pi_double_2nd(op >> 7, 0, xval);
2310
double res = -yval + xval;
2311
int zpi = (op >> 0) & 0x7f;
2313
dau_write_pi_double(zpi, yval);
2314
dau_set_val_flags((op >> 21) & 3, res);
2318
void dsp32c_device::d4_mm(UINT32 op)
2320
double xval = dau_read_pi_double_1st(op >> 14, 1);
2321
double yval = dau_read_pi_double_2nd(op >> 7, 0, xval);
2322
double res = -yval - xval;
2323
int zpi = (op >> 0) & 0x7f;
2325
dau_write_pi_double(zpi, yval);
2326
dau_set_val_flags((op >> 21) & 3, res);
2330
void dsp32c_device::d4_ppr(UINT32 op)
2336
void dsp32c_device::d4_pmr(UINT32 op)
2342
void dsp32c_device::d4_mpr(UINT32 op)
2348
void dsp32c_device::d4_mmr(UINT32 op)
2355
//**************************************************************************
2356
// DAU FORM 5 IMPLEMENTATION
2357
//**************************************************************************
2359
void dsp32c_device::d5_ic(UINT32 op)
2365
void dsp32c_device::d5_oc(UINT32 op)
2371
void dsp32c_device::d5_float(UINT32 op)
2373
double res = (double)(INT16)dau_read_pi_2bytes(op >> 7);
2374
int zpi = (op >> 0) & 0x7f;
2376
dau_write_pi_double(zpi, res);
2377
dau_set_val_flags((op >> 21) & 3, res);
2381
void dsp32c_device::d5_int(UINT32 op)
2383
double val = dau_read_pi_double_1st(op >> 7, 0);
2364
2384
int zpi = (op >> 0) & 0x7f;
2366
if (!(cpustate->DAUC & 0x10)) val = floor(val + 0.5);
2386
if (!(DAUC & 0x10)) val = floor(val + 0.5);
2367
2387
else val = ceil(val - 0.5);
2368
2388
res = (INT16)val;
2370
dau_write_pi_2bytes(cpustate, zpi, res);
2371
dau_set_val_noflags(cpustate, (op >> 21) & 3, dsp_to_double(res << 16));
2390
dau_write_pi_2bytes(zpi, res);
2391
dau_set_val_noflags((op >> 21) & 3, dsp_to_double(res << 16));
2375
static void d5_round(dsp32_state *cpustate, UINT32 op)
2395
void dsp32c_device::d5_round(UINT32 op)
2377
double res = (double)(float)dau_read_pi_double_1st(cpustate, op >> 7, 0);
2397
double res = (double)(float)dau_read_pi_double_1st(op >> 7, 0);
2378
2398
int zpi = (op >> 0) & 0x7f;
2380
dau_write_pi_double(cpustate, zpi, res);
2381
dau_set_val_flags(cpustate, (op >> 21) & 3, res);
2400
dau_write_pi_double(zpi, res);
2401
dau_set_val_flags((op >> 21) & 3, res);
2385
static void d5_ifalt(dsp32_state *cpustate, UINT32 op)
2405
void dsp32c_device::d5_ifalt(UINT32 op)
2387
2407
int ar = (op >> 21) & 3;
2388
double res = cpustate->a[ar];
2408
double res = m_a[ar];
2389
2409
int zpi = (op >> 0) & 0x7f;
2391
res = dau_read_pi_double_1st(cpustate, op >> 7, 0);
2411
res = dau_read_pi_double_1st(op >> 7, 0);
2393
dau_write_pi_double(cpustate, zpi, res);
2394
dau_set_val_noflags(cpustate, ar, res);
2413
dau_write_pi_double(zpi, res);
2414
dau_set_val_noflags(ar, res);
2398
static void d5_ifaeq(dsp32_state *cpustate, UINT32 op)
2418
void dsp32c_device::d5_ifaeq(UINT32 op)
2400
2420
int ar = (op >> 21) & 3;
2401
double res = cpustate->a[ar];
2421
double res = m_a[ar];
2402
2422
int zpi = (op >> 0) & 0x7f;
2404
res = dau_read_pi_double_1st(cpustate, op >> 7, 0);
2424
res = dau_read_pi_double_1st(op >> 7, 0);
2406
dau_write_pi_double(cpustate, zpi, res);
2407
dau_set_val_noflags(cpustate, ar, res);
2426
dau_write_pi_double(zpi, res);
2427
dau_set_val_noflags(ar, res);
2411
static void d5_ifagt(dsp32_state *cpustate, UINT32 op)
2431
void dsp32c_device::d5_ifagt(UINT32 op)
2413
2433
int ar = (op >> 21) & 3;
2414
double res = cpustate->a[ar];
2434
double res = m_a[ar];
2415
2435
int zpi = (op >> 0) & 0x7f;
2416
2436
if (!NFLAG && !ZFLAG)
2417
res = dau_read_pi_double_1st(cpustate, op >> 7, 0);
2437
res = dau_read_pi_double_1st(op >> 7, 0);
2419
dau_write_pi_double(cpustate, zpi, res);
2420
dau_set_val_noflags(cpustate, ar, res);
2439
dau_write_pi_double(zpi, res);
2440
dau_set_val_noflags(ar, res);
2424
static void d5_float24(dsp32_state *cpustate, UINT32 op)
2444
void dsp32c_device::d5_float24(UINT32 op)
2426
double res = (double)((INT32)(dau_read_pi_4bytes(cpustate, op >> 7) << 8) >> 8);
2446
double res = (double)((INT32)(dau_read_pi_4bytes(op >> 7) << 8) >> 8);
2427
2447
int zpi = (op >> 0) & 0x7f;
2429
dau_write_pi_double(cpustate, zpi, res);
2430
dau_set_val_flags(cpustate, (op >> 21) & 3, res);
2449
dau_write_pi_double(zpi, res);
2450
dau_set_val_flags((op >> 21) & 3, res);
2434
static void d5_int24(dsp32_state *cpustate, UINT32 op)
2454
void dsp32c_device::d5_int24(UINT32 op)
2436
double val = dau_read_pi_double_1st(cpustate, op >> 7, 0);
2456
double val = dau_read_pi_double_1st(op >> 7, 0);
2437
2457
int zpi = (op >> 0) & 0x7f;
2439
if (!(cpustate->DAUC & 0x10)) val = floor(val + 0.5);
2459
if (!(DAUC & 0x10)) val = floor(val + 0.5);
2440
2460
else val = ceil(val - 0.5);
2441
2461
res = (INT32)val;
2442
2462
if (res > 0x7fffff) res = 0x7fffff;
2443
2463
else if (res < -0x800000) res = -0x800000;
2445
dau_write_pi_4bytes(cpustate, zpi, (INT32)(res << 8) >> 8);
2446
dau_set_val_noflags(cpustate, (op >> 21) & 3, dsp_to_double(res << 8));
2450
static void d5_ieee(dsp32_state *cpustate, UINT32 op)
2452
unimplemented(cpustate, op);
2456
static void d5_dsp(dsp32_state *cpustate, UINT32 op)
2458
unimplemented(cpustate, op);
2462
static void d5_seed(dsp32_state *cpustate, UINT32 op)
2464
UINT32 val = dau_read_pi_4bytes(cpustate, op >> 7);
2465
dau_write_pi_4bytes(zpi, (INT32)(res << 8) >> 8);
2466
dau_set_val_noflags((op >> 21) & 3, dsp_to_double(res << 8));
2470
void dsp32c_device::d5_ieee(UINT32 op)
2476
void dsp32c_device::d5_dsp(UINT32 op)
2482
void dsp32c_device::d5_seed(UINT32 op)
2484
UINT32 val = dau_read_pi_4bytes(op >> 7);
2465
2485
INT32 res = val ^ 0x7fffffff;
2466
2486
int zpi = (op >> 0) & 0x7f;
2468
dau_write_pi_4bytes(cpustate, zpi, res);
2469
dau_set_val_flags(cpustate, (op >> 21) & 3, dsp_to_double((INT32)res));
2488
dau_write_pi_4bytes(zpi, res);
2489
dau_set_val_flags((op >> 21) & 3, dsp_to_double((INT32)res));
2474
/***************************************************************************
2476
***************************************************************************/
2494
//**************************************************************************
2496
//**************************************************************************
2478
void (*const dsp32ops[])(dsp32_state *cpustate, UINT32 op) =
2498
void (dsp32c_device::*const dsp32c_device::s_dsp32ops[])(UINT32 op) =
2480
nop, goto_t, goto_pl, goto_mi, goto_ne, goto_eq, goto_vc, goto_vs, /* 00 */
2481
goto_cc, goto_cs, goto_ge, goto_lt, goto_gt, goto_le, goto_hi, goto_ls,
2482
goto_auc, goto_aus, goto_age, goto_alt, goto_ane, goto_aeq, goto_avc, goto_avs, /* 01 */
2483
goto_agt, goto_ale, illegal, illegal, illegal, illegal, illegal, illegal,
2484
goto_ibe, goto_ibf, goto_obf, goto_obe, goto_pde, goto_pdf, goto_pie, goto_pif, /* 02 */
2485
goto_syc, goto_sys, goto_fbc, goto_fbs, goto_irq1lo,goto_irq1hi,goto_irq2lo,goto_irq2hi,
2486
illegal, illegal, illegal, illegal, illegal, illegal, illegal, illegal, /* 03 */
2487
illegal, illegal, illegal, illegal, illegal, illegal, illegal, illegal,
2489
illegal, illegal, illegal, illegal, illegal, illegal, illegal, illegal, /* 04 */
2490
illegal, illegal, illegal, illegal, illegal, illegal, illegal, illegal,
2491
illegal, illegal, illegal, illegal, illegal, illegal, illegal, illegal, /* 05 */
2492
illegal, illegal, illegal, illegal, illegal, illegal, illegal, illegal,
2493
dec_goto, dec_goto, dec_goto, dec_goto, dec_goto, dec_goto, dec_goto, dec_goto, /* 06 */
2494
dec_goto, dec_goto, dec_goto, dec_goto, dec_goto, dec_goto, dec_goto, dec_goto,
2495
dec_goto, dec_goto, dec_goto, dec_goto, dec_goto, dec_goto, dec_goto, dec_goto, /* 07 */
2496
dec_goto, dec_goto, dec_goto, dec_goto, dec_goto, dec_goto, dec_goto, dec_goto,
2498
call, call, call, call, call, call, call, call, /* 08 */
2499
call, call, call, call, call, call, call, call,
2500
call, call, call, call, call, call, call, call, /* 09 */
2501
call, call, call, call, call, call, call, call,
2502
add_si, add_si, add_si, add_si, add_si, add_si, add_si, add_si, /* 0a */
2503
add_si, add_si, add_si, add_si, add_si, add_si, add_si, add_si,
2504
add_si, add_si, add_si, add_si, add_si, add_si, add_si, add_si, /* 0b */
2505
add_si, add_si, add_si, add_si, add_si, add_si, add_si, add_si,
2507
add_ss, mul2_s, subr_ss, addr_ss, sub_ss, neg_s, andc_ss, cmp_ss, /* 0c */
2508
xor_ss, rcr_s, or_ss, rcl_s, shr_s, div2_s, and_ss, test_ss,
2509
add_di, illegal, subr_di, addr_di, sub_di, illegal, andc_di, cmp_di, /* 0d */
2510
xor_di, illegal, or_di, illegal, illegal, illegal, and_di, test_di,
2511
load_hi, load_hi, load_li, load_li, load_i, load_i, load_ei, load_ei, /* 0e */
2512
store_hi, store_hi, store_li, store_li, store_i, store_i, store_ei, store_ei,
2513
load_hr, load_hr, load_lr, load_lr, load_r, load_r, load_er, load_er, /* 0f */
2514
store_hr, store_hr, store_lr, store_lr, store_r, store_r, store_er, store_er,
2516
d1_aMpp, d1_aMpp, d1_aMpp, d1_aMpp, d1_aMpm, d1_aMpm, d1_aMpm, d1_aMpm, /* 10 */
2517
d1_aMmp, d1_aMmp, d1_aMmp, d1_aMmp, d1_aMmm, d1_aMmm, d1_aMmm, d1_aMmm,
2518
d1_aMppr, d1_aMppr, d1_aMppr, d1_aMppr, d1_aMpmr, d1_aMpmr, d1_aMpmr, d1_aMpmr, /* 11 */
2519
d1_aMmpr, d1_aMmpr, d1_aMmpr, d1_aMmpr, d1_aMmmr, d1_aMmmr, d1_aMmmr, d1_aMmmr,
2520
d1_aMpp, d1_aMpp, d1_aMpp, d1_aMpp, d1_aMpm, d1_aMpm, d1_aMpm, d1_aMpm, /* 12 */
2521
d1_aMmp, d1_aMmp, d1_aMmp, d1_aMmp, d1_aMmm, d1_aMmm, d1_aMmm, d1_aMmm,
2522
d1_aMppr, d1_aMppr, d1_aMppr, d1_aMppr, d1_aMpmr, d1_aMpmr, d1_aMpmr, d1_aMpmr, /* 13 */
2523
d1_aMmpr, d1_aMmpr, d1_aMmpr, d1_aMmpr, d1_aMmmr, d1_aMmmr, d1_aMmmr, d1_aMmmr,
2525
d1_aMpp, d1_aMpp, d1_aMpp, d1_aMpp, d1_aMpm, d1_aMpm, d1_aMpm, d1_aMpm, /* 14 */
2526
d1_aMmp, d1_aMmp, d1_aMmp, d1_aMmp, d1_aMmm, d1_aMmm, d1_aMmm, d1_aMmm,
2527
d1_aMppr, d1_aMppr, d1_aMppr, d1_aMppr, d1_aMpmr, d1_aMpmr, d1_aMpmr, d1_aMpmr, /* 15 */
2528
d1_aMmpr, d1_aMmpr, d1_aMmpr, d1_aMmpr, d1_aMmmr, d1_aMmmr, d1_aMmmr, d1_aMmmr,
2529
d1_aMpp, d1_aMpp, d1_aMpp, d1_aMpp, d1_aMpm, d1_aMpm, d1_aMpm, d1_aMpm, /* 16 */
2530
d1_aMmp, d1_aMmp, d1_aMmp, d1_aMmp, d1_aMmm, d1_aMmm, d1_aMmm, d1_aMmm,
2531
d1_aMppr, d1_aMppr, d1_aMppr, d1_aMppr, d1_aMpmr, d1_aMpmr, d1_aMpmr, d1_aMpmr, /* 17 */
2532
d1_aMmpr, d1_aMmpr, d1_aMmpr, d1_aMmpr, d1_aMmmr, d1_aMmmr, d1_aMmmr, d1_aMmmr,
2534
d1_0px, d1_0px, d1_0px, d1_0px, d1_0px, d1_0px, d1_0px, d1_0px, /* 18 */
2535
d1_0mx, d1_0mx, d1_0mx, d1_0mx, d1_0mx, d1_0mx, d1_0mx, d1_0mx,
2536
d1_aMppr, d1_aMppr, d1_aMppr, d1_aMppr, d1_aMpmr, d1_aMpmr, d1_aMpmr, d1_aMpmr, /* 19 */
2537
d1_aMmpr, d1_aMmpr, d1_aMmpr, d1_aMmpr, d1_aMmmr, d1_aMmmr, d1_aMmmr, d1_aMmmr,
2538
d1_1pp, d1_1pp, d1_1pp, d1_1pp, d1_1pm, d1_1pm, d1_1pm, d1_1pm, /* 1a */
2539
d1_1mp, d1_1mp, d1_1mp, d1_1mp, d1_1mm, d1_1mm, d1_1mm, d1_1mm,
2540
d1_aMppr, d1_aMppr, d1_aMppr, d1_aMppr, d1_aMpmr, d1_aMpmr, d1_aMpmr, d1_aMpmr, /* 1b */
2541
d1_aMmpr, d1_aMmpr, d1_aMmpr, d1_aMmpr, d1_aMmmr, d1_aMmmr, d1_aMmmr, d1_aMmmr,
2543
d4_pp, d4_pp, d4_pp, d4_pp, d4_pm, d4_pm, d4_pm, d4_pm, /* 1c */
2544
d4_mp, d4_mp, d4_mp, d4_mp, d4_mm, d4_mm, d4_mm, d4_mm,
2545
d4_ppr, d4_ppr, d4_ppr, d4_ppr, d4_pmr, d4_pmr, d4_pmr, d4_pmr, /* 1d */
2546
d4_mpr, d4_mpr, d4_mpr, d4_mpr, d4_mmr, d4_mmr, d4_mmr, d4_mmr,
2547
illegal, illegal, illegal, illegal, illegal, illegal, illegal, illegal, /* 1e */
2548
illegal, illegal, illegal, illegal, illegal, illegal, illegal, illegal,
2549
illegal, illegal, illegal, illegal, illegal, illegal, illegal, illegal, /* 1f */
2550
illegal, illegal, illegal, illegal, illegal, illegal, illegal, illegal,
2552
d2_aMpp, d2_aMpp, d2_aMpp, d2_aMpp, d2_aMpm, d2_aMpm, d2_aMpm, d2_aMpm, /* 20 */
2553
d2_aMmp, d2_aMmp, d2_aMmp, d2_aMmp, d2_aMmm, d2_aMmm, d2_aMmm, d2_aMmm,
2554
d2_aMppr, d2_aMppr, d2_aMppr, d2_aMppr, d2_aMpmr, d2_aMpmr, d2_aMpmr, d2_aMpmr, /* 21 */
2555
d2_aMmpr, d2_aMmpr, d2_aMmpr, d2_aMmpr, d2_aMmmr, d2_aMmmr, d2_aMmmr, d2_aMmmr,
2556
d2_aMpp, d2_aMpp, d2_aMpp, d2_aMpp, d2_aMpm, d2_aMpm, d2_aMpm, d2_aMpm, /* 22 */
2557
d2_aMmp, d2_aMmp, d2_aMmp, d2_aMmp, d2_aMmm, d2_aMmm, d2_aMmm, d2_aMmm,
2558
d2_aMppr, d2_aMppr, d2_aMppr, d2_aMppr, d2_aMpmr, d2_aMpmr, d2_aMpmr, d2_aMpmr, /* 23 */
2559
d2_aMmpr, d2_aMmpr, d2_aMmpr, d2_aMmpr, d2_aMmmr, d2_aMmmr, d2_aMmmr, d2_aMmmr,
2561
d2_aMpp, d2_aMpp, d2_aMpp, d2_aMpp, d2_aMpm, d2_aMpm, d2_aMpm, d2_aMpm, /* 24 */
2562
d2_aMmp, d2_aMmp, d2_aMmp, d2_aMmp, d2_aMmm, d2_aMmm, d2_aMmm, d2_aMmm,
2563
d2_aMppr, d2_aMppr, d2_aMppr, d2_aMppr, d2_aMpmr, d2_aMpmr, d2_aMpmr, d2_aMpmr, /* 25 */
2564
d2_aMmpr, d2_aMmpr, d2_aMmpr, d2_aMmpr, d2_aMmmr, d2_aMmmr, d2_aMmmr, d2_aMmmr,
2565
d2_aMpp, d2_aMpp, d2_aMpp, d2_aMpp, d2_aMpm, d2_aMpm, d2_aMpm, d2_aMpm, /* 26 */
2566
d2_aMmp, d2_aMmp, d2_aMmp, d2_aMmp, d2_aMmm, d2_aMmm, d2_aMmm, d2_aMmm,
2567
d2_aMppr, d2_aMppr, d2_aMppr, d2_aMppr, d2_aMpmr, d2_aMpmr, d2_aMpmr, d2_aMpmr, /* 27 */
2568
d2_aMmpr, d2_aMmpr, d2_aMmpr, d2_aMmpr, d2_aMmmr, d2_aMmmr, d2_aMmmr, d2_aMmmr,
2570
d2_aMpp, d2_aMpp, d2_aMpp, d2_aMpp, d2_aMpm, d2_aMpm, d2_aMpm, d2_aMpm, /* 28 */
2571
d2_aMmp, d2_aMmp, d2_aMmp, d2_aMmp, d2_aMmm, d2_aMmm, d2_aMmm, d2_aMmm,
2572
d2_aMppr, d2_aMppr, d2_aMppr, d2_aMppr, d2_aMpmr, d2_aMpmr, d2_aMpmr, d2_aMpmr, /* 29 */
2573
d2_aMmpr, d2_aMmpr, d2_aMmpr, d2_aMmpr, d2_aMmmr, d2_aMmmr, d2_aMmmr, d2_aMmmr,
2574
d2_aMpp, d2_aMpp, d2_aMpp, d2_aMpp, d2_aMpm, d2_aMpm, d2_aMpm, d2_aMpm, /* 2a */
2575
d2_aMmp, d2_aMmp, d2_aMmp, d2_aMmp, d2_aMmm, d2_aMmm, d2_aMmm, d2_aMmm,
2576
d2_aMppr, d2_aMppr, d2_aMppr, d2_aMppr, d2_aMpmr, d2_aMpmr, d2_aMpmr, d2_aMpmr, /* 2b */
2577
d2_aMmpr, d2_aMmpr, d2_aMmpr, d2_aMmpr, d2_aMmmr, d2_aMmmr, d2_aMmmr, d2_aMmmr,
2579
illegal, illegal, illegal, illegal, illegal, illegal, illegal, illegal, /* 2c */
2580
illegal, illegal, illegal, illegal, illegal, illegal, illegal, illegal,
2581
illegal, illegal, illegal, illegal, illegal, illegal, illegal, illegal, /* 2d */
2582
illegal, illegal, illegal, illegal, illegal, illegal, illegal, illegal,
2583
illegal, illegal, illegal, illegal, illegal, illegal, illegal, illegal, /* 2e */
2584
illegal, illegal, illegal, illegal, illegal, illegal, illegal, illegal,
2585
illegal, illegal, illegal, illegal, illegal, illegal, illegal, illegal, /* 2f */
2586
illegal, illegal, illegal, illegal, illegal, illegal, illegal, illegal,
2588
d3_aMpp, d3_aMpp, d3_aMpp, d3_aMpp, d3_aMpm, d3_aMpm, d3_aMpm, d3_aMpm, /* 30 */
2589
d3_aMmp, d3_aMmp, d3_aMmp, d3_aMmp, d3_aMmm, d3_aMmm, d3_aMmm, d3_aMmm,
2590
d3_aMppr, d3_aMppr, d3_aMppr, d3_aMppr, d3_aMpmr, d3_aMpmr, d3_aMpmr, d3_aMpmr, /* 31 */
2591
d3_aMmpr, d3_aMmpr, d3_aMmpr, d3_aMmpr, d3_aMmmr, d3_aMmmr, d3_aMmmr, d3_aMmmr,
2592
d3_aMpp, d3_aMpp, d3_aMpp, d3_aMpp, d3_aMpm, d3_aMpm, d3_aMpm, d3_aMpm, /* 32 */
2593
d3_aMmp, d3_aMmp, d3_aMmp, d3_aMmp, d3_aMmm, d3_aMmm, d3_aMmm, d3_aMmm,
2594
d3_aMppr, d3_aMppr, d3_aMppr, d3_aMppr, d3_aMpmr, d3_aMpmr, d3_aMpmr, d3_aMpmr, /* 33 */
2595
d3_aMmpr, d3_aMmpr, d3_aMmpr, d3_aMmpr, d3_aMmmr, d3_aMmmr, d3_aMmmr, d3_aMmmr,
2597
d3_aMpp, d3_aMpp, d3_aMpp, d3_aMpp, d3_aMpm, d3_aMpm, d3_aMpm, d3_aMpm, /* 34 */
2598
d3_aMmp, d3_aMmp, d3_aMmp, d3_aMmp, d3_aMmm, d3_aMmm, d3_aMmm, d3_aMmm,
2599
d3_aMppr, d3_aMppr, d3_aMppr, d3_aMppr, d3_aMpmr, d3_aMpmr, d3_aMpmr, d3_aMpmr, /* 35 */
2600
d3_aMmpr, d3_aMmpr, d3_aMmpr, d3_aMmpr, d3_aMmmr, d3_aMmmr, d3_aMmmr, d3_aMmmr,
2601
d3_aMpp, d3_aMpp, d3_aMpp, d3_aMpp, d3_aMpm, d3_aMpm, d3_aMpm, d3_aMpm, /* 36 */
2602
d3_aMmp, d3_aMmp, d3_aMmp, d3_aMmp, d3_aMmm, d3_aMmm, d3_aMmm, d3_aMmm,
2603
d3_aMppr, d3_aMppr, d3_aMppr, d3_aMppr, d3_aMpmr, d3_aMpmr, d3_aMpmr, d3_aMpmr, /* 37 */
2604
d3_aMmpr, d3_aMmpr, d3_aMmpr, d3_aMmpr, d3_aMmmr, d3_aMmmr, d3_aMmmr, d3_aMmmr,
2606
d3_aMpp, d3_aMpp, d3_aMpp, d3_aMpp, d3_aMpm, d3_aMpm, d3_aMpm, d3_aMpm, /* 38 */
2607
d3_aMmp, d3_aMmp, d3_aMmp, d3_aMmp, d3_aMmm, d3_aMmm, d3_aMmm, d3_aMmm,
2608
d3_aMppr, d3_aMppr, d3_aMppr, d3_aMppr, d3_aMpmr, d3_aMpmr, d3_aMpmr, d3_aMpmr, /* 39 */
2609
d3_aMmpr, d3_aMmpr, d3_aMmpr, d3_aMmpr, d3_aMmmr, d3_aMmmr, d3_aMmmr, d3_aMmmr,
2610
d3_aMpp, d3_aMpp, d3_aMpp, d3_aMpp, d3_aMpm, d3_aMpm, d3_aMpm, d3_aMpm, /* 3a */
2611
d3_aMmp, d3_aMmp, d3_aMmp, d3_aMmp, d3_aMmm, d3_aMmm, d3_aMmm, d3_aMmm,
2612
d3_aMppr, d3_aMppr, d3_aMppr, d3_aMppr, d3_aMpmr, d3_aMpmr, d3_aMpmr, d3_aMpmr, /* 3b */
2613
d3_aMmpr, d3_aMmpr, d3_aMmpr, d3_aMmpr, d3_aMmmr, d3_aMmmr, d3_aMmmr, d3_aMmmr,
2615
d5_ic, d5_ic, d5_ic, d5_ic, d5_oc, d5_oc, d5_oc, d5_oc, /* 3c */
2616
d5_float, d5_float, d5_float, d5_float, d5_int, d5_int, d5_int, d5_int,
2617
d5_round, d5_round, d5_round, d5_round, d5_ifalt, d5_ifalt, d5_ifalt, d5_ifalt, /* 3d */
2618
d5_ifaeq, d5_ifaeq, d5_ifaeq, d5_ifaeq, d5_ifagt, d5_ifagt, d5_ifagt, d5_ifagt,
2619
illegal, illegal, illegal, illegal, illegal, illegal, illegal, illegal, /* 3e */
2620
d5_float24, d5_float24, d5_float24, d5_float24, d5_int24, d5_int24, d5_int24, d5_int24,
2621
d5_ieee, d5_ieee, d5_ieee, d5_ieee, d5_dsp, d5_dsp, d5_dsp, d5_dsp, /* 3f */
2622
d5_seed, d5_seed, d5_seed, d5_seed, illegal, illegal, illegal, illegal,
2624
illegal, illegal, illegal, illegal, illegal, illegal, illegal, illegal, /* 40 */
2625
illegal, illegal, illegal, illegal, illegal, illegal, illegal, illegal,
2626
illegal, illegal, illegal, illegal, illegal, illegal, illegal, illegal, /* 41 */
2627
illegal, illegal, illegal, illegal, illegal, illegal, illegal, illegal,
2628
illegal, illegal, illegal, illegal, illegal, illegal, illegal, illegal, /* 42 */
2629
illegal, illegal, illegal, illegal, illegal, illegal, illegal, illegal,
2630
illegal, illegal, illegal, illegal, illegal, illegal, illegal, illegal, /* 43 */
2631
illegal, illegal, illegal, illegal, illegal, illegal, illegal, illegal,
2633
illegal, illegal, illegal, illegal, illegal, illegal, illegal, illegal, /* 44 */
2634
illegal, illegal, illegal, illegal, illegal, illegal, illegal, illegal,
2635
illegal, illegal, illegal, illegal, illegal, illegal, illegal, illegal, /* 45 */
2636
illegal, illegal, illegal, illegal, illegal, illegal, illegal, illegal,
2637
do_i, do_r, illegal, illegal, illegal, illegal, illegal, illegal, /* 46 */
2638
illegal, illegal, illegal, illegal, illegal, illegal, illegal, illegal,
2639
illegal, illegal, illegal, illegal, illegal, illegal, illegal, illegal, /* 47 */
2640
illegal, illegal, illegal, illegal, illegal, illegal, illegal, illegal,
2642
illegal, illegal, illegal, illegal, illegal, illegal, illegal, illegal, /* 48 */
2643
illegal, illegal, illegal, illegal, illegal, illegal, illegal, illegal,
2644
illegal, illegal, illegal, illegal, illegal, illegal, illegal, illegal, /* 49 */
2645
illegal, illegal, illegal, illegal, illegal, illegal, illegal, illegal,
2646
adde_si, adde_si, adde_si, adde_si, adde_si, adde_si, adde_si, adde_si, /* 4a */
2647
adde_si, adde_si, adde_si, adde_si, adde_si, adde_si, adde_si, adde_si,
2648
adde_si, adde_si, adde_si, adde_si, adde_si, adde_si, adde_si, adde_si, /* 4b */
2649
adde_si, adde_si, adde_si, adde_si, adde_si, adde_si, adde_si, adde_si,
2651
adde_ss, mul2e_s, subre_ss, addre_ss, sube_ss, nege_s, andce_ss, cmpe_ss, /* 4c */
2652
xore_ss, rcre_s, ore_ss, rcle_s, shre_s, div2e_s, ande_ss, teste_ss,
2653
adde_di, illegal, subre_di, addre_di, sube_di, illegal, andce_di, cmpe_di, /* 4d */
2654
xore_di, illegal, ore_di, illegal, illegal, illegal, ande_di, teste_di,
2655
illegal, illegal, illegal, illegal, illegal, illegal, illegal, illegal, /* 4e */
2656
illegal, illegal, illegal, illegal, illegal, illegal, illegal, illegal,
2657
illegal, illegal, illegal, illegal, illegal, illegal, illegal, illegal, /* 4f */
2658
illegal, illegal, illegal, illegal, illegal, illegal, illegal, illegal,
2660
goto24, goto24, goto24, goto24, goto24, goto24, goto24, goto24, /* 50 */
2661
goto24, goto24, goto24, goto24, goto24, goto24, goto24, goto24,
2662
goto24, goto24, goto24, goto24, goto24, goto24, goto24, goto24, /* 51 */
2663
goto24, goto24, goto24, goto24, goto24, goto24, goto24, goto24,
2664
goto24, goto24, goto24, goto24, goto24, goto24, goto24, goto24, /* 52 */
2665
goto24, goto24, goto24, goto24, goto24, goto24, goto24, goto24,
2666
goto24, goto24, goto24, goto24, goto24, goto24, goto24, goto24, /* 53 */
2667
goto24, goto24, goto24, goto24, goto24, goto24, goto24, goto24,
2669
goto24, goto24, goto24, goto24, goto24, goto24, goto24, goto24, /* 54 */
2670
goto24, goto24, goto24, goto24, goto24, goto24, goto24, goto24,
2671
goto24, goto24, goto24, goto24, goto24, goto24, goto24, goto24, /* 55 */
2672
goto24, goto24, goto24, goto24, goto24, goto24, goto24, goto24,
2673
goto24, goto24, goto24, goto24, goto24, goto24, goto24, goto24, /* 56 */
2674
goto24, goto24, goto24, goto24, goto24, goto24, goto24, goto24,
2675
goto24, goto24, goto24, goto24, goto24, goto24, goto24, goto24, /* 57 */
2676
goto24, goto24, goto24, goto24, goto24, goto24, goto24, goto24,
2678
goto24, goto24, goto24, goto24, goto24, goto24, goto24, goto24, /* 58 */
2679
goto24, goto24, goto24, goto24, goto24, goto24, goto24, goto24,
2680
goto24, goto24, goto24, goto24, goto24, goto24, goto24, goto24, /* 59 */
2681
goto24, goto24, goto24, goto24, goto24, goto24, goto24, goto24,
2682
goto24, goto24, goto24, goto24, goto24, goto24, goto24, goto24, /* 5a */
2683
goto24, goto24, goto24, goto24, goto24, goto24, goto24, goto24,
2684
goto24, goto24, goto24, goto24, goto24, goto24, goto24, goto24, /* 5b */
2685
goto24, goto24, goto24, goto24, goto24, goto24, goto24, goto24,
2687
goto24, goto24, goto24, goto24, goto24, goto24, goto24, goto24, /* 5c */
2688
goto24, goto24, goto24, goto24, goto24, goto24, goto24, goto24,
2689
goto24, goto24, goto24, goto24, goto24, goto24, goto24, goto24, /* 5d */
2690
goto24, goto24, goto24, goto24, goto24, goto24, goto24, goto24,
2691
goto24, goto24, goto24, goto24, goto24, goto24, goto24, goto24, /* 5e */
2692
goto24, goto24, goto24, goto24, goto24, goto24, goto24, goto24,
2693
goto24, goto24, goto24, goto24, goto24, goto24, goto24, goto24, /* 5f */
2694
goto24, goto24, goto24, goto24, goto24, goto24, goto24, goto24,
2696
load24, load24, load24, load24, load24, load24, load24, load24, /* 60 */
2697
load24, load24, load24, load24, load24, load24, load24, load24,
2698
load24, load24, load24, load24, load24, load24, load24, load24, /* 61 */
2699
load24, load24, load24, load24, load24, load24, load24, load24,
2700
load24, load24, load24, load24, load24, load24, load24, load24, /* 62 */
2701
load24, load24, load24, load24, load24, load24, load24, load24,
2702
load24, load24, load24, load24, load24, load24, load24, load24, /* 63 */
2703
load24, load24, load24, load24, load24, load24, load24, load24,
2705
load24, load24, load24, load24, load24, load24, load24, load24, /* 64 */
2706
load24, load24, load24, load24, load24, load24, load24, load24,
2707
load24, load24, load24, load24, load24, load24, load24, load24, /* 65 */
2708
load24, load24, load24, load24, load24, load24, load24, load24,
2709
load24, load24, load24, load24, load24, load24, load24, load24, /* 66 */
2710
load24, load24, load24, load24, load24, load24, load24, load24,
2711
load24, load24, load24, load24, load24, load24, load24, load24, /* 67 */
2712
load24, load24, load24, load24, load24, load24, load24, load24,
2714
load24, load24, load24, load24, load24, load24, load24, load24, /* 68 */
2715
load24, load24, load24, load24, load24, load24, load24, load24,
2716
load24, load24, load24, load24, load24, load24, load24, load24, /* 69 */
2717
load24, load24, load24, load24, load24, load24, load24, load24,
2718
load24, load24, load24, load24, load24, load24, load24, load24, /* 6a */
2719
load24, load24, load24, load24, load24, load24, load24, load24,
2720
load24, load24, load24, load24, load24, load24, load24, load24, /* 6b */
2721
load24, load24, load24, load24, load24, load24, load24, load24,
2723
load24, load24, load24, load24, load24, load24, load24, load24, /* 6c */
2724
load24, load24, load24, load24, load24, load24, load24, load24,
2725
load24, load24, load24, load24, load24, load24, load24, load24, /* 6d */
2726
load24, load24, load24, load24, load24, load24, load24, load24,
2727
load24, load24, load24, load24, load24, load24, load24, load24, /* 6e */
2728
load24, load24, load24, load24, load24, load24, load24, load24,
2729
load24, load24, load24, load24, load24, load24, load24, load24, /* 6f */
2730
load24, load24, load24, load24, load24, load24, load24, load24,
2732
call24, call24, call24, call24, call24, call24, call24, call24, /* 70 */
2733
call24, call24, call24, call24, call24, call24, call24, call24,
2734
call24, call24, call24, call24, call24, call24, call24, call24, /* 71 */
2735
call24, call24, call24, call24, call24, call24, call24, call24,
2736
call24, call24, call24, call24, call24, call24, call24, call24, /* 72 */
2737
call24, call24, call24, call24, call24, call24, call24, call24,
2738
call24, call24, call24, call24, call24, call24, call24, call24, /* 73 */
2739
call24, call24, call24, call24, call24, call24, call24, call24,
2741
call24, call24, call24, call24, call24, call24, call24, call24, /* 74 */
2742
call24, call24, call24, call24, call24, call24, call24, call24,
2743
call24, call24, call24, call24, call24, call24, call24, call24, /* 75 */
2744
call24, call24, call24, call24, call24, call24, call24, call24,
2745
call24, call24, call24, call24, call24, call24, call24, call24, /* 76 */
2746
call24, call24, call24, call24, call24, call24, call24, call24,
2747
call24, call24, call24, call24, call24, call24, call24, call24, /* 77 */
2748
call24, call24, call24, call24, call24, call24, call24, call24,
2750
call24, call24, call24, call24, call24, call24, call24, call24, /* 78 */
2751
call24, call24, call24, call24, call24, call24, call24, call24,
2752
call24, call24, call24, call24, call24, call24, call24, call24, /* 79 */
2753
call24, call24, call24, call24, call24, call24, call24, call24,
2754
call24, call24, call24, call24, call24, call24, call24, call24, /* 7a */
2755
call24, call24, call24, call24, call24, call24, call24, call24,
2756
call24, call24, call24, call24, call24, call24, call24, call24, /* 7b */
2757
call24, call24, call24, call24, call24, call24, call24, call24,
2759
call24, call24, call24, call24, call24, call24, call24, call24, /* 7c */
2760
call24, call24, call24, call24, call24, call24, call24, call24,
2761
call24, call24, call24, call24, call24, call24, call24, call24, /* 7d */
2762
call24, call24, call24, call24, call24, call24, call24, call24,
2763
call24, call24, call24, call24, call24, call24, call24, call24, /* 7e */
2764
call24, call24, call24, call24, call24, call24, call24, call24,
2765
call24, call24, call24, call24, call24, call24, call24, call24, /* 7f */
2766
call24, call24, call24, call24, call24, call24, call24, call24
2500
&dsp32c_device::nop, &dsp32c_device::goto_t, &dsp32c_device::goto_pl, &dsp32c_device::goto_mi, &dsp32c_device::goto_ne, &dsp32c_device::goto_eq, &dsp32c_device::goto_vc, &dsp32c_device::goto_vs, // 00
2501
&dsp32c_device::goto_cc, &dsp32c_device::goto_cs, &dsp32c_device::goto_ge, &dsp32c_device::goto_lt, &dsp32c_device::goto_gt, &dsp32c_device::goto_le, &dsp32c_device::goto_hi, &dsp32c_device::goto_ls,
2502
&dsp32c_device::goto_auc, &dsp32c_device::goto_aus, &dsp32c_device::goto_age, &dsp32c_device::goto_alt, &dsp32c_device::goto_ane, &dsp32c_device::goto_aeq, &dsp32c_device::goto_avc, &dsp32c_device::goto_avs, // 01
2503
&dsp32c_device::goto_agt, &dsp32c_device::goto_ale, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal,
2504
&dsp32c_device::goto_ibe, &dsp32c_device::goto_ibf, &dsp32c_device::goto_obf, &dsp32c_device::goto_obe, &dsp32c_device::goto_pde, &dsp32c_device::goto_pdf, &dsp32c_device::goto_pie, &dsp32c_device::goto_pif, // 02
2505
&dsp32c_device::goto_syc, &dsp32c_device::goto_sys, &dsp32c_device::goto_fbc, &dsp32c_device::goto_fbs, &dsp32c_device::goto_irq1lo,&dsp32c_device::goto_irq1hi,&dsp32c_device::goto_irq2lo,&dsp32c_device::goto_irq2hi,
2506
&dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, // 03
2507
&dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal,
2509
&dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, // 04
2510
&dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal,
2511
&dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, // 05
2512
&dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal,
2513
&dsp32c_device::dec_goto, &dsp32c_device::dec_goto, &dsp32c_device::dec_goto, &dsp32c_device::dec_goto, &dsp32c_device::dec_goto, &dsp32c_device::dec_goto, &dsp32c_device::dec_goto, &dsp32c_device::dec_goto, // 06
2514
&dsp32c_device::dec_goto, &dsp32c_device::dec_goto, &dsp32c_device::dec_goto, &dsp32c_device::dec_goto, &dsp32c_device::dec_goto, &dsp32c_device::dec_goto, &dsp32c_device::dec_goto, &dsp32c_device::dec_goto,
2515
&dsp32c_device::dec_goto, &dsp32c_device::dec_goto, &dsp32c_device::dec_goto, &dsp32c_device::dec_goto, &dsp32c_device::dec_goto, &dsp32c_device::dec_goto, &dsp32c_device::dec_goto, &dsp32c_device::dec_goto, // 07
2516
&dsp32c_device::dec_goto, &dsp32c_device::dec_goto, &dsp32c_device::dec_goto, &dsp32c_device::dec_goto, &dsp32c_device::dec_goto, &dsp32c_device::dec_goto, &dsp32c_device::dec_goto, &dsp32c_device::dec_goto,
2518
&dsp32c_device::call, &dsp32c_device::call, &dsp32c_device::call, &dsp32c_device::call, &dsp32c_device::call, &dsp32c_device::call, &dsp32c_device::call, &dsp32c_device::call, // 08
2519
&dsp32c_device::call, &dsp32c_device::call, &dsp32c_device::call, &dsp32c_device::call, &dsp32c_device::call, &dsp32c_device::call, &dsp32c_device::call, &dsp32c_device::call,
2520
&dsp32c_device::call, &dsp32c_device::call, &dsp32c_device::call, &dsp32c_device::call, &dsp32c_device::call, &dsp32c_device::call, &dsp32c_device::call, &dsp32c_device::call, // 09
2521
&dsp32c_device::call, &dsp32c_device::call, &dsp32c_device::call, &dsp32c_device::call, &dsp32c_device::call, &dsp32c_device::call, &dsp32c_device::call, &dsp32c_device::call,
2522
&dsp32c_device::add_si, &dsp32c_device::add_si, &dsp32c_device::add_si, &dsp32c_device::add_si, &dsp32c_device::add_si, &dsp32c_device::add_si, &dsp32c_device::add_si, &dsp32c_device::add_si, // 0a
2523
&dsp32c_device::add_si, &dsp32c_device::add_si, &dsp32c_device::add_si, &dsp32c_device::add_si, &dsp32c_device::add_si, &dsp32c_device::add_si, &dsp32c_device::add_si, &dsp32c_device::add_si,
2524
&dsp32c_device::add_si, &dsp32c_device::add_si, &dsp32c_device::add_si, &dsp32c_device::add_si, &dsp32c_device::add_si, &dsp32c_device::add_si, &dsp32c_device::add_si, &dsp32c_device::add_si, // 0b
2525
&dsp32c_device::add_si, &dsp32c_device::add_si, &dsp32c_device::add_si, &dsp32c_device::add_si, &dsp32c_device::add_si, &dsp32c_device::add_si, &dsp32c_device::add_si, &dsp32c_device::add_si,
2527
&dsp32c_device::add_ss, &dsp32c_device::mul2_s, &dsp32c_device::subr_ss, &dsp32c_device::addr_ss, &dsp32c_device::sub_ss, &dsp32c_device::neg_s, &dsp32c_device::andc_ss, &dsp32c_device::cmp_ss, // 0c
2528
&dsp32c_device::xor_ss, &dsp32c_device::rcr_s, &dsp32c_device::or_ss, &dsp32c_device::rcl_s, &dsp32c_device::shr_s, &dsp32c_device::div2_s, &dsp32c_device::and_ss, &dsp32c_device::test_ss,
2529
&dsp32c_device::add_di, &dsp32c_device::illegal, &dsp32c_device::subr_di, &dsp32c_device::addr_di, &dsp32c_device::sub_di, &dsp32c_device::illegal, &dsp32c_device::andc_di, &dsp32c_device::cmp_di, // 0d
2530
&dsp32c_device::xor_di, &dsp32c_device::illegal, &dsp32c_device::or_di, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::and_di, &dsp32c_device::test_di,
2531
&dsp32c_device::load_hi, &dsp32c_device::load_hi, &dsp32c_device::load_li, &dsp32c_device::load_li, &dsp32c_device::load_i, &dsp32c_device::load_i, &dsp32c_device::load_ei, &dsp32c_device::load_ei, // 0e
2532
&dsp32c_device::store_hi, &dsp32c_device::store_hi, &dsp32c_device::store_li, &dsp32c_device::store_li, &dsp32c_device::store_i, &dsp32c_device::store_i, &dsp32c_device::store_ei, &dsp32c_device::store_ei,
2533
&dsp32c_device::load_hr, &dsp32c_device::load_hr, &dsp32c_device::load_lr, &dsp32c_device::load_lr, &dsp32c_device::load_r, &dsp32c_device::load_r, &dsp32c_device::load_er, &dsp32c_device::load_er, // 0f
2534
&dsp32c_device::store_hr, &dsp32c_device::store_hr, &dsp32c_device::store_lr, &dsp32c_device::store_lr, &dsp32c_device::store_r, &dsp32c_device::store_r, &dsp32c_device::store_er, &dsp32c_device::store_er,
2536
&dsp32c_device::d1_aMpp, &dsp32c_device::d1_aMpp, &dsp32c_device::d1_aMpp, &dsp32c_device::d1_aMpp, &dsp32c_device::d1_aMpm, &dsp32c_device::d1_aMpm, &dsp32c_device::d1_aMpm, &dsp32c_device::d1_aMpm, // 10
2537
&dsp32c_device::d1_aMmp, &dsp32c_device::d1_aMmp, &dsp32c_device::d1_aMmp, &dsp32c_device::d1_aMmp, &dsp32c_device::d1_aMmm, &dsp32c_device::d1_aMmm, &dsp32c_device::d1_aMmm, &dsp32c_device::d1_aMmm,
2538
&dsp32c_device::d1_aMppr, &dsp32c_device::d1_aMppr, &dsp32c_device::d1_aMppr, &dsp32c_device::d1_aMppr, &dsp32c_device::d1_aMpmr, &dsp32c_device::d1_aMpmr, &dsp32c_device::d1_aMpmr, &dsp32c_device::d1_aMpmr, // 11
2539
&dsp32c_device::d1_aMmpr, &dsp32c_device::d1_aMmpr, &dsp32c_device::d1_aMmpr, &dsp32c_device::d1_aMmpr, &dsp32c_device::d1_aMmmr, &dsp32c_device::d1_aMmmr, &dsp32c_device::d1_aMmmr, &dsp32c_device::d1_aMmmr,
2540
&dsp32c_device::d1_aMpp, &dsp32c_device::d1_aMpp, &dsp32c_device::d1_aMpp, &dsp32c_device::d1_aMpp, &dsp32c_device::d1_aMpm, &dsp32c_device::d1_aMpm, &dsp32c_device::d1_aMpm, &dsp32c_device::d1_aMpm, // 12
2541
&dsp32c_device::d1_aMmp, &dsp32c_device::d1_aMmp, &dsp32c_device::d1_aMmp, &dsp32c_device::d1_aMmp, &dsp32c_device::d1_aMmm, &dsp32c_device::d1_aMmm, &dsp32c_device::d1_aMmm, &dsp32c_device::d1_aMmm,
2542
&dsp32c_device::d1_aMppr, &dsp32c_device::d1_aMppr, &dsp32c_device::d1_aMppr, &dsp32c_device::d1_aMppr, &dsp32c_device::d1_aMpmr, &dsp32c_device::d1_aMpmr, &dsp32c_device::d1_aMpmr, &dsp32c_device::d1_aMpmr, // 13
2543
&dsp32c_device::d1_aMmpr, &dsp32c_device::d1_aMmpr, &dsp32c_device::d1_aMmpr, &dsp32c_device::d1_aMmpr, &dsp32c_device::d1_aMmmr, &dsp32c_device::d1_aMmmr, &dsp32c_device::d1_aMmmr, &dsp32c_device::d1_aMmmr,
2545
&dsp32c_device::d1_aMpp, &dsp32c_device::d1_aMpp, &dsp32c_device::d1_aMpp, &dsp32c_device::d1_aMpp, &dsp32c_device::d1_aMpm, &dsp32c_device::d1_aMpm, &dsp32c_device::d1_aMpm, &dsp32c_device::d1_aMpm, // 14
2546
&dsp32c_device::d1_aMmp, &dsp32c_device::d1_aMmp, &dsp32c_device::d1_aMmp, &dsp32c_device::d1_aMmp, &dsp32c_device::d1_aMmm, &dsp32c_device::d1_aMmm, &dsp32c_device::d1_aMmm, &dsp32c_device::d1_aMmm,
2547
&dsp32c_device::d1_aMppr, &dsp32c_device::d1_aMppr, &dsp32c_device::d1_aMppr, &dsp32c_device::d1_aMppr, &dsp32c_device::d1_aMpmr, &dsp32c_device::d1_aMpmr, &dsp32c_device::d1_aMpmr, &dsp32c_device::d1_aMpmr, // 15
2548
&dsp32c_device::d1_aMmpr, &dsp32c_device::d1_aMmpr, &dsp32c_device::d1_aMmpr, &dsp32c_device::d1_aMmpr, &dsp32c_device::d1_aMmmr, &dsp32c_device::d1_aMmmr, &dsp32c_device::d1_aMmmr, &dsp32c_device::d1_aMmmr,
2549
&dsp32c_device::d1_aMpp, &dsp32c_device::d1_aMpp, &dsp32c_device::d1_aMpp, &dsp32c_device::d1_aMpp, &dsp32c_device::d1_aMpm, &dsp32c_device::d1_aMpm, &dsp32c_device::d1_aMpm, &dsp32c_device::d1_aMpm, // 16
2550
&dsp32c_device::d1_aMmp, &dsp32c_device::d1_aMmp, &dsp32c_device::d1_aMmp, &dsp32c_device::d1_aMmp, &dsp32c_device::d1_aMmm, &dsp32c_device::d1_aMmm, &dsp32c_device::d1_aMmm, &dsp32c_device::d1_aMmm,
2551
&dsp32c_device::d1_aMppr, &dsp32c_device::d1_aMppr, &dsp32c_device::d1_aMppr, &dsp32c_device::d1_aMppr, &dsp32c_device::d1_aMpmr, &dsp32c_device::d1_aMpmr, &dsp32c_device::d1_aMpmr, &dsp32c_device::d1_aMpmr, // 17
2552
&dsp32c_device::d1_aMmpr, &dsp32c_device::d1_aMmpr, &dsp32c_device::d1_aMmpr, &dsp32c_device::d1_aMmpr, &dsp32c_device::d1_aMmmr, &dsp32c_device::d1_aMmmr, &dsp32c_device::d1_aMmmr, &dsp32c_device::d1_aMmmr,
2554
&dsp32c_device::d1_0px, &dsp32c_device::d1_0px, &dsp32c_device::d1_0px, &dsp32c_device::d1_0px, &dsp32c_device::d1_0px, &dsp32c_device::d1_0px, &dsp32c_device::d1_0px, &dsp32c_device::d1_0px, // 18
2555
&dsp32c_device::d1_0mx, &dsp32c_device::d1_0mx, &dsp32c_device::d1_0mx, &dsp32c_device::d1_0mx, &dsp32c_device::d1_0mx, &dsp32c_device::d1_0mx, &dsp32c_device::d1_0mx, &dsp32c_device::d1_0mx,
2556
&dsp32c_device::d1_aMppr, &dsp32c_device::d1_aMppr, &dsp32c_device::d1_aMppr, &dsp32c_device::d1_aMppr, &dsp32c_device::d1_aMpmr, &dsp32c_device::d1_aMpmr, &dsp32c_device::d1_aMpmr, &dsp32c_device::d1_aMpmr, // 19
2557
&dsp32c_device::d1_aMmpr, &dsp32c_device::d1_aMmpr, &dsp32c_device::d1_aMmpr, &dsp32c_device::d1_aMmpr, &dsp32c_device::d1_aMmmr, &dsp32c_device::d1_aMmmr, &dsp32c_device::d1_aMmmr, &dsp32c_device::d1_aMmmr,
2558
&dsp32c_device::d1_1pp, &dsp32c_device::d1_1pp, &dsp32c_device::d1_1pp, &dsp32c_device::d1_1pp, &dsp32c_device::d1_1pm, &dsp32c_device::d1_1pm, &dsp32c_device::d1_1pm, &dsp32c_device::d1_1pm, // 1a
2559
&dsp32c_device::d1_1mp, &dsp32c_device::d1_1mp, &dsp32c_device::d1_1mp, &dsp32c_device::d1_1mp, &dsp32c_device::d1_1mm, &dsp32c_device::d1_1mm, &dsp32c_device::d1_1mm, &dsp32c_device::d1_1mm,
2560
&dsp32c_device::d1_aMppr, &dsp32c_device::d1_aMppr, &dsp32c_device::d1_aMppr, &dsp32c_device::d1_aMppr, &dsp32c_device::d1_aMpmr, &dsp32c_device::d1_aMpmr, &dsp32c_device::d1_aMpmr, &dsp32c_device::d1_aMpmr, // 1b
2561
&dsp32c_device::d1_aMmpr, &dsp32c_device::d1_aMmpr, &dsp32c_device::d1_aMmpr, &dsp32c_device::d1_aMmpr, &dsp32c_device::d1_aMmmr, &dsp32c_device::d1_aMmmr, &dsp32c_device::d1_aMmmr, &dsp32c_device::d1_aMmmr,
2563
&dsp32c_device::d4_pp, &dsp32c_device::d4_pp, &dsp32c_device::d4_pp, &dsp32c_device::d4_pp, &dsp32c_device::d4_pm, &dsp32c_device::d4_pm, &dsp32c_device::d4_pm, &dsp32c_device::d4_pm, // 1c
2564
&dsp32c_device::d4_mp, &dsp32c_device::d4_mp, &dsp32c_device::d4_mp, &dsp32c_device::d4_mp, &dsp32c_device::d4_mm, &dsp32c_device::d4_mm, &dsp32c_device::d4_mm, &dsp32c_device::d4_mm,
2565
&dsp32c_device::d4_ppr, &dsp32c_device::d4_ppr, &dsp32c_device::d4_ppr, &dsp32c_device::d4_ppr, &dsp32c_device::d4_pmr, &dsp32c_device::d4_pmr, &dsp32c_device::d4_pmr, &dsp32c_device::d4_pmr, // 1d
2566
&dsp32c_device::d4_mpr, &dsp32c_device::d4_mpr, &dsp32c_device::d4_mpr, &dsp32c_device::d4_mpr, &dsp32c_device::d4_mmr, &dsp32c_device::d4_mmr, &dsp32c_device::d4_mmr, &dsp32c_device::d4_mmr,
2567
&dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, // 1e
2568
&dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal,
2569
&dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, // 1f
2570
&dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal,
2572
&dsp32c_device::d2_aMpp, &dsp32c_device::d2_aMpp, &dsp32c_device::d2_aMpp, &dsp32c_device::d2_aMpp, &dsp32c_device::d2_aMpm, &dsp32c_device::d2_aMpm, &dsp32c_device::d2_aMpm, &dsp32c_device::d2_aMpm, // 20
2573
&dsp32c_device::d2_aMmp, &dsp32c_device::d2_aMmp, &dsp32c_device::d2_aMmp, &dsp32c_device::d2_aMmp, &dsp32c_device::d2_aMmm, &dsp32c_device::d2_aMmm, &dsp32c_device::d2_aMmm, &dsp32c_device::d2_aMmm,
2574
&dsp32c_device::d2_aMppr, &dsp32c_device::d2_aMppr, &dsp32c_device::d2_aMppr, &dsp32c_device::d2_aMppr, &dsp32c_device::d2_aMpmr, &dsp32c_device::d2_aMpmr, &dsp32c_device::d2_aMpmr, &dsp32c_device::d2_aMpmr, // 21
2575
&dsp32c_device::d2_aMmpr, &dsp32c_device::d2_aMmpr, &dsp32c_device::d2_aMmpr, &dsp32c_device::d2_aMmpr, &dsp32c_device::d2_aMmmr, &dsp32c_device::d2_aMmmr, &dsp32c_device::d2_aMmmr, &dsp32c_device::d2_aMmmr,
2576
&dsp32c_device::d2_aMpp, &dsp32c_device::d2_aMpp, &dsp32c_device::d2_aMpp, &dsp32c_device::d2_aMpp, &dsp32c_device::d2_aMpm, &dsp32c_device::d2_aMpm, &dsp32c_device::d2_aMpm, &dsp32c_device::d2_aMpm, // 22
2577
&dsp32c_device::d2_aMmp, &dsp32c_device::d2_aMmp, &dsp32c_device::d2_aMmp, &dsp32c_device::d2_aMmp, &dsp32c_device::d2_aMmm, &dsp32c_device::d2_aMmm, &dsp32c_device::d2_aMmm, &dsp32c_device::d2_aMmm,
2578
&dsp32c_device::d2_aMppr, &dsp32c_device::d2_aMppr, &dsp32c_device::d2_aMppr, &dsp32c_device::d2_aMppr, &dsp32c_device::d2_aMpmr, &dsp32c_device::d2_aMpmr, &dsp32c_device::d2_aMpmr, &dsp32c_device::d2_aMpmr, // 23
2579
&dsp32c_device::d2_aMmpr, &dsp32c_device::d2_aMmpr, &dsp32c_device::d2_aMmpr, &dsp32c_device::d2_aMmpr, &dsp32c_device::d2_aMmmr, &dsp32c_device::d2_aMmmr, &dsp32c_device::d2_aMmmr, &dsp32c_device::d2_aMmmr,
2581
&dsp32c_device::d2_aMpp, &dsp32c_device::d2_aMpp, &dsp32c_device::d2_aMpp, &dsp32c_device::d2_aMpp, &dsp32c_device::d2_aMpm, &dsp32c_device::d2_aMpm, &dsp32c_device::d2_aMpm, &dsp32c_device::d2_aMpm, // 24
2582
&dsp32c_device::d2_aMmp, &dsp32c_device::d2_aMmp, &dsp32c_device::d2_aMmp, &dsp32c_device::d2_aMmp, &dsp32c_device::d2_aMmm, &dsp32c_device::d2_aMmm, &dsp32c_device::d2_aMmm, &dsp32c_device::d2_aMmm,
2583
&dsp32c_device::d2_aMppr, &dsp32c_device::d2_aMppr, &dsp32c_device::d2_aMppr, &dsp32c_device::d2_aMppr, &dsp32c_device::d2_aMpmr, &dsp32c_device::d2_aMpmr, &dsp32c_device::d2_aMpmr, &dsp32c_device::d2_aMpmr, // 25
2584
&dsp32c_device::d2_aMmpr, &dsp32c_device::d2_aMmpr, &dsp32c_device::d2_aMmpr, &dsp32c_device::d2_aMmpr, &dsp32c_device::d2_aMmmr, &dsp32c_device::d2_aMmmr, &dsp32c_device::d2_aMmmr, &dsp32c_device::d2_aMmmr,
2585
&dsp32c_device::d2_aMpp, &dsp32c_device::d2_aMpp, &dsp32c_device::d2_aMpp, &dsp32c_device::d2_aMpp, &dsp32c_device::d2_aMpm, &dsp32c_device::d2_aMpm, &dsp32c_device::d2_aMpm, &dsp32c_device::d2_aMpm, // 26
2586
&dsp32c_device::d2_aMmp, &dsp32c_device::d2_aMmp, &dsp32c_device::d2_aMmp, &dsp32c_device::d2_aMmp, &dsp32c_device::d2_aMmm, &dsp32c_device::d2_aMmm, &dsp32c_device::d2_aMmm, &dsp32c_device::d2_aMmm,
2587
&dsp32c_device::d2_aMppr, &dsp32c_device::d2_aMppr, &dsp32c_device::d2_aMppr, &dsp32c_device::d2_aMppr, &dsp32c_device::d2_aMpmr, &dsp32c_device::d2_aMpmr, &dsp32c_device::d2_aMpmr, &dsp32c_device::d2_aMpmr, // 27
2588
&dsp32c_device::d2_aMmpr, &dsp32c_device::d2_aMmpr, &dsp32c_device::d2_aMmpr, &dsp32c_device::d2_aMmpr, &dsp32c_device::d2_aMmmr, &dsp32c_device::d2_aMmmr, &dsp32c_device::d2_aMmmr, &dsp32c_device::d2_aMmmr,
2590
&dsp32c_device::d2_aMpp, &dsp32c_device::d2_aMpp, &dsp32c_device::d2_aMpp, &dsp32c_device::d2_aMpp, &dsp32c_device::d2_aMpm, &dsp32c_device::d2_aMpm, &dsp32c_device::d2_aMpm, &dsp32c_device::d2_aMpm, // 28
2591
&dsp32c_device::d2_aMmp, &dsp32c_device::d2_aMmp, &dsp32c_device::d2_aMmp, &dsp32c_device::d2_aMmp, &dsp32c_device::d2_aMmm, &dsp32c_device::d2_aMmm, &dsp32c_device::d2_aMmm, &dsp32c_device::d2_aMmm,
2592
&dsp32c_device::d2_aMppr, &dsp32c_device::d2_aMppr, &dsp32c_device::d2_aMppr, &dsp32c_device::d2_aMppr, &dsp32c_device::d2_aMpmr, &dsp32c_device::d2_aMpmr, &dsp32c_device::d2_aMpmr, &dsp32c_device::d2_aMpmr, // 29
2593
&dsp32c_device::d2_aMmpr, &dsp32c_device::d2_aMmpr, &dsp32c_device::d2_aMmpr, &dsp32c_device::d2_aMmpr, &dsp32c_device::d2_aMmmr, &dsp32c_device::d2_aMmmr, &dsp32c_device::d2_aMmmr, &dsp32c_device::d2_aMmmr,
2594
&dsp32c_device::d2_aMpp, &dsp32c_device::d2_aMpp, &dsp32c_device::d2_aMpp, &dsp32c_device::d2_aMpp, &dsp32c_device::d2_aMpm, &dsp32c_device::d2_aMpm, &dsp32c_device::d2_aMpm, &dsp32c_device::d2_aMpm, // 2a
2595
&dsp32c_device::d2_aMmp, &dsp32c_device::d2_aMmp, &dsp32c_device::d2_aMmp, &dsp32c_device::d2_aMmp, &dsp32c_device::d2_aMmm, &dsp32c_device::d2_aMmm, &dsp32c_device::d2_aMmm, &dsp32c_device::d2_aMmm,
2596
&dsp32c_device::d2_aMppr, &dsp32c_device::d2_aMppr, &dsp32c_device::d2_aMppr, &dsp32c_device::d2_aMppr, &dsp32c_device::d2_aMpmr, &dsp32c_device::d2_aMpmr, &dsp32c_device::d2_aMpmr, &dsp32c_device::d2_aMpmr, // 2b
2597
&dsp32c_device::d2_aMmpr, &dsp32c_device::d2_aMmpr, &dsp32c_device::d2_aMmpr, &dsp32c_device::d2_aMmpr, &dsp32c_device::d2_aMmmr, &dsp32c_device::d2_aMmmr, &dsp32c_device::d2_aMmmr, &dsp32c_device::d2_aMmmr,
2599
&dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, // 2c
2600
&dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal,
2601
&dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, // 2d
2602
&dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal,
2603
&dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, // 2e
2604
&dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal,
2605
&dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, // 2f
2606
&dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal,
2608
&dsp32c_device::d3_aMpp, &dsp32c_device::d3_aMpp, &dsp32c_device::d3_aMpp, &dsp32c_device::d3_aMpp, &dsp32c_device::d3_aMpm, &dsp32c_device::d3_aMpm, &dsp32c_device::d3_aMpm, &dsp32c_device::d3_aMpm, // 30
2609
&dsp32c_device::d3_aMmp, &dsp32c_device::d3_aMmp, &dsp32c_device::d3_aMmp, &dsp32c_device::d3_aMmp, &dsp32c_device::d3_aMmm, &dsp32c_device::d3_aMmm, &dsp32c_device::d3_aMmm, &dsp32c_device::d3_aMmm,
2610
&dsp32c_device::d3_aMppr, &dsp32c_device::d3_aMppr, &dsp32c_device::d3_aMppr, &dsp32c_device::d3_aMppr, &dsp32c_device::d3_aMpmr, &dsp32c_device::d3_aMpmr, &dsp32c_device::d3_aMpmr, &dsp32c_device::d3_aMpmr, // 31
2611
&dsp32c_device::d3_aMmpr, &dsp32c_device::d3_aMmpr, &dsp32c_device::d3_aMmpr, &dsp32c_device::d3_aMmpr, &dsp32c_device::d3_aMmmr, &dsp32c_device::d3_aMmmr, &dsp32c_device::d3_aMmmr, &dsp32c_device::d3_aMmmr,
2612
&dsp32c_device::d3_aMpp, &dsp32c_device::d3_aMpp, &dsp32c_device::d3_aMpp, &dsp32c_device::d3_aMpp, &dsp32c_device::d3_aMpm, &dsp32c_device::d3_aMpm, &dsp32c_device::d3_aMpm, &dsp32c_device::d3_aMpm, // 32
2613
&dsp32c_device::d3_aMmp, &dsp32c_device::d3_aMmp, &dsp32c_device::d3_aMmp, &dsp32c_device::d3_aMmp, &dsp32c_device::d3_aMmm, &dsp32c_device::d3_aMmm, &dsp32c_device::d3_aMmm, &dsp32c_device::d3_aMmm,
2614
&dsp32c_device::d3_aMppr, &dsp32c_device::d3_aMppr, &dsp32c_device::d3_aMppr, &dsp32c_device::d3_aMppr, &dsp32c_device::d3_aMpmr, &dsp32c_device::d3_aMpmr, &dsp32c_device::d3_aMpmr, &dsp32c_device::d3_aMpmr, // 33
2615
&dsp32c_device::d3_aMmpr, &dsp32c_device::d3_aMmpr, &dsp32c_device::d3_aMmpr, &dsp32c_device::d3_aMmpr, &dsp32c_device::d3_aMmmr, &dsp32c_device::d3_aMmmr, &dsp32c_device::d3_aMmmr, &dsp32c_device::d3_aMmmr,
2617
&dsp32c_device::d3_aMpp, &dsp32c_device::d3_aMpp, &dsp32c_device::d3_aMpp, &dsp32c_device::d3_aMpp, &dsp32c_device::d3_aMpm, &dsp32c_device::d3_aMpm, &dsp32c_device::d3_aMpm, &dsp32c_device::d3_aMpm, // 34
2618
&dsp32c_device::d3_aMmp, &dsp32c_device::d3_aMmp, &dsp32c_device::d3_aMmp, &dsp32c_device::d3_aMmp, &dsp32c_device::d3_aMmm, &dsp32c_device::d3_aMmm, &dsp32c_device::d3_aMmm, &dsp32c_device::d3_aMmm,
2619
&dsp32c_device::d3_aMppr, &dsp32c_device::d3_aMppr, &dsp32c_device::d3_aMppr, &dsp32c_device::d3_aMppr, &dsp32c_device::d3_aMpmr, &dsp32c_device::d3_aMpmr, &dsp32c_device::d3_aMpmr, &dsp32c_device::d3_aMpmr, // 35
2620
&dsp32c_device::d3_aMmpr, &dsp32c_device::d3_aMmpr, &dsp32c_device::d3_aMmpr, &dsp32c_device::d3_aMmpr, &dsp32c_device::d3_aMmmr, &dsp32c_device::d3_aMmmr, &dsp32c_device::d3_aMmmr, &dsp32c_device::d3_aMmmr,
2621
&dsp32c_device::d3_aMpp, &dsp32c_device::d3_aMpp, &dsp32c_device::d3_aMpp, &dsp32c_device::d3_aMpp, &dsp32c_device::d3_aMpm, &dsp32c_device::d3_aMpm, &dsp32c_device::d3_aMpm, &dsp32c_device::d3_aMpm, // 36
2622
&dsp32c_device::d3_aMmp, &dsp32c_device::d3_aMmp, &dsp32c_device::d3_aMmp, &dsp32c_device::d3_aMmp, &dsp32c_device::d3_aMmm, &dsp32c_device::d3_aMmm, &dsp32c_device::d3_aMmm, &dsp32c_device::d3_aMmm,
2623
&dsp32c_device::d3_aMppr, &dsp32c_device::d3_aMppr, &dsp32c_device::d3_aMppr, &dsp32c_device::d3_aMppr, &dsp32c_device::d3_aMpmr, &dsp32c_device::d3_aMpmr, &dsp32c_device::d3_aMpmr, &dsp32c_device::d3_aMpmr, // 37
2624
&dsp32c_device::d3_aMmpr, &dsp32c_device::d3_aMmpr, &dsp32c_device::d3_aMmpr, &dsp32c_device::d3_aMmpr, &dsp32c_device::d3_aMmmr, &dsp32c_device::d3_aMmmr, &dsp32c_device::d3_aMmmr, &dsp32c_device::d3_aMmmr,
2626
&dsp32c_device::d3_aMpp, &dsp32c_device::d3_aMpp, &dsp32c_device::d3_aMpp, &dsp32c_device::d3_aMpp, &dsp32c_device::d3_aMpm, &dsp32c_device::d3_aMpm, &dsp32c_device::d3_aMpm, &dsp32c_device::d3_aMpm, // 38
2627
&dsp32c_device::d3_aMmp, &dsp32c_device::d3_aMmp, &dsp32c_device::d3_aMmp, &dsp32c_device::d3_aMmp, &dsp32c_device::d3_aMmm, &dsp32c_device::d3_aMmm, &dsp32c_device::d3_aMmm, &dsp32c_device::d3_aMmm,
2628
&dsp32c_device::d3_aMppr, &dsp32c_device::d3_aMppr, &dsp32c_device::d3_aMppr, &dsp32c_device::d3_aMppr, &dsp32c_device::d3_aMpmr, &dsp32c_device::d3_aMpmr, &dsp32c_device::d3_aMpmr, &dsp32c_device::d3_aMpmr, // 39
2629
&dsp32c_device::d3_aMmpr, &dsp32c_device::d3_aMmpr, &dsp32c_device::d3_aMmpr, &dsp32c_device::d3_aMmpr, &dsp32c_device::d3_aMmmr, &dsp32c_device::d3_aMmmr, &dsp32c_device::d3_aMmmr, &dsp32c_device::d3_aMmmr,
2630
&dsp32c_device::d3_aMpp, &dsp32c_device::d3_aMpp, &dsp32c_device::d3_aMpp, &dsp32c_device::d3_aMpp, &dsp32c_device::d3_aMpm, &dsp32c_device::d3_aMpm, &dsp32c_device::d3_aMpm, &dsp32c_device::d3_aMpm, // 3a
2631
&dsp32c_device::d3_aMmp, &dsp32c_device::d3_aMmp, &dsp32c_device::d3_aMmp, &dsp32c_device::d3_aMmp, &dsp32c_device::d3_aMmm, &dsp32c_device::d3_aMmm, &dsp32c_device::d3_aMmm, &dsp32c_device::d3_aMmm,
2632
&dsp32c_device::d3_aMppr, &dsp32c_device::d3_aMppr, &dsp32c_device::d3_aMppr, &dsp32c_device::d3_aMppr, &dsp32c_device::d3_aMpmr, &dsp32c_device::d3_aMpmr, &dsp32c_device::d3_aMpmr, &dsp32c_device::d3_aMpmr, // 3b
2633
&dsp32c_device::d3_aMmpr, &dsp32c_device::d3_aMmpr, &dsp32c_device::d3_aMmpr, &dsp32c_device::d3_aMmpr, &dsp32c_device::d3_aMmmr, &dsp32c_device::d3_aMmmr, &dsp32c_device::d3_aMmmr, &dsp32c_device::d3_aMmmr,
2635
&dsp32c_device::d5_ic, &dsp32c_device::d5_ic, &dsp32c_device::d5_ic, &dsp32c_device::d5_ic, &dsp32c_device::d5_oc, &dsp32c_device::d5_oc, &dsp32c_device::d5_oc, &dsp32c_device::d5_oc, // 3c
2636
&dsp32c_device::d5_float, &dsp32c_device::d5_float, &dsp32c_device::d5_float, &dsp32c_device::d5_float, &dsp32c_device::d5_int, &dsp32c_device::d5_int, &dsp32c_device::d5_int, &dsp32c_device::d5_int,
2637
&dsp32c_device::d5_round, &dsp32c_device::d5_round, &dsp32c_device::d5_round, &dsp32c_device::d5_round, &dsp32c_device::d5_ifalt, &dsp32c_device::d5_ifalt, &dsp32c_device::d5_ifalt, &dsp32c_device::d5_ifalt, // 3d
2638
&dsp32c_device::d5_ifaeq, &dsp32c_device::d5_ifaeq, &dsp32c_device::d5_ifaeq, &dsp32c_device::d5_ifaeq, &dsp32c_device::d5_ifagt, &dsp32c_device::d5_ifagt, &dsp32c_device::d5_ifagt, &dsp32c_device::d5_ifagt,
2639
&dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, // 3e
2640
&dsp32c_device::d5_float24, &dsp32c_device::d5_float24, &dsp32c_device::d5_float24, &dsp32c_device::d5_float24, &dsp32c_device::d5_int24, &dsp32c_device::d5_int24, &dsp32c_device::d5_int24, &dsp32c_device::d5_int24,
2641
&dsp32c_device::d5_ieee, &dsp32c_device::d5_ieee, &dsp32c_device::d5_ieee, &dsp32c_device::d5_ieee, &dsp32c_device::d5_dsp, &dsp32c_device::d5_dsp, &dsp32c_device::d5_dsp, &dsp32c_device::d5_dsp, // 3f
2642
&dsp32c_device::d5_seed, &dsp32c_device::d5_seed, &dsp32c_device::d5_seed, &dsp32c_device::d5_seed, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal,
2644
&dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, // 40
2645
&dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal,
2646
&dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, // 41
2647
&dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal,
2648
&dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, // 42
2649
&dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal,
2650
&dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, // 43
2651
&dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal,
2653
&dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, // 44
2654
&dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal,
2655
&dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, // 45
2656
&dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal,
2657
&dsp32c_device::do_i, &dsp32c_device::do_r, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, // 46
2658
&dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal,
2659
&dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, // 47
2660
&dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal,
2662
&dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, // 48
2663
&dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal,
2664
&dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, // 49
2665
&dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal,
2666
&dsp32c_device::adde_si, &dsp32c_device::adde_si, &dsp32c_device::adde_si, &dsp32c_device::adde_si, &dsp32c_device::adde_si, &dsp32c_device::adde_si, &dsp32c_device::adde_si, &dsp32c_device::adde_si, // 4a
2667
&dsp32c_device::adde_si, &dsp32c_device::adde_si, &dsp32c_device::adde_si, &dsp32c_device::adde_si, &dsp32c_device::adde_si, &dsp32c_device::adde_si, &dsp32c_device::adde_si, &dsp32c_device::adde_si,
2668
&dsp32c_device::adde_si, &dsp32c_device::adde_si, &dsp32c_device::adde_si, &dsp32c_device::adde_si, &dsp32c_device::adde_si, &dsp32c_device::adde_si, &dsp32c_device::adde_si, &dsp32c_device::adde_si, // 4b
2669
&dsp32c_device::adde_si, &dsp32c_device::adde_si, &dsp32c_device::adde_si, &dsp32c_device::adde_si, &dsp32c_device::adde_si, &dsp32c_device::adde_si, &dsp32c_device::adde_si, &dsp32c_device::adde_si,
2671
&dsp32c_device::adde_ss, &dsp32c_device::mul2e_s, &dsp32c_device::subre_ss, &dsp32c_device::addre_ss, &dsp32c_device::sube_ss, &dsp32c_device::nege_s, &dsp32c_device::andce_ss, &dsp32c_device::cmpe_ss, // 4c
2672
&dsp32c_device::xore_ss, &dsp32c_device::rcre_s, &dsp32c_device::ore_ss, &dsp32c_device::rcle_s, &dsp32c_device::shre_s, &dsp32c_device::div2e_s, &dsp32c_device::ande_ss, &dsp32c_device::teste_ss,
2673
&dsp32c_device::adde_di, &dsp32c_device::illegal, &dsp32c_device::subre_di, &dsp32c_device::addre_di, &dsp32c_device::sube_di, &dsp32c_device::illegal, &dsp32c_device::andce_di, &dsp32c_device::cmpe_di, // 4d
2674
&dsp32c_device::xore_di, &dsp32c_device::illegal, &dsp32c_device::ore_di, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::ande_di, &dsp32c_device::teste_di,
2675
&dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, // 4e
2676
&dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal,
2677
&dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, // 4f
2678
&dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal, &dsp32c_device::illegal,
2680
&dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, // 50
2681
&dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24,
2682
&dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, // 51
2683
&dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24,
2684
&dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, // 52
2685
&dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24,
2686
&dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, // 53
2687
&dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24,
2689
&dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, // 54
2690
&dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24,
2691
&dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, // 55
2692
&dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24,
2693
&dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, // 56
2694
&dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24,
2695
&dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, // 57
2696
&dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24,
2698
&dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, // 58
2699
&dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24,
2700
&dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, // 59
2701
&dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24,
2702
&dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, // 5a
2703
&dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24,
2704
&dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, // 5b
2705
&dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24,
2707
&dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, // 5c
2708
&dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24,
2709
&dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, // 5d
2710
&dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24,
2711
&dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, // 5e
2712
&dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24,
2713
&dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, // 5f
2714
&dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24, &dsp32c_device::goto24,
2716
&dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, // 60
2717
&dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24,
2718
&dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, // 61
2719
&dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24,
2720
&dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, // 62
2721
&dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24,
2722
&dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, // 63
2723
&dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24,
2725
&dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, // 64
2726
&dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24,
2727
&dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, // 65
2728
&dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24,
2729
&dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, // 66
2730
&dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24,
2731
&dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, // 67
2732
&dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24,
2734
&dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, // 68
2735
&dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24,
2736
&dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, // 69
2737
&dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24,
2738
&dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, // 6a
2739
&dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24,
2740
&dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, // 6b
2741
&dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24,
2743
&dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, // 6c
2744
&dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24,
2745
&dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, // 6d
2746
&dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24,
2747
&dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, // 6e
2748
&dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24,
2749
&dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, // 6f
2750
&dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24, &dsp32c_device::load24,
2752
&dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, // 70
2753
&dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24,
2754
&dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, // 71
2755
&dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24,
2756
&dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, // 72
2757
&dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24,
2758
&dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, // 73
2759
&dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24,
2761
&dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, // 74
2762
&dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24,
2763
&dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, // 75
2764
&dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24,
2765
&dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, // 76
2766
&dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24,
2767
&dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, // 77
2768
&dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24,
2770
&dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, // 78
2771
&dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24,
2772
&dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, // 79
2773
&dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24,
2774
&dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, // 7a
2775
&dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24,
2776
&dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, // 7b
2777
&dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24,
2779
&dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, // 7c
2780
&dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24,
2781
&dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, // 7d
2782
&dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24,
2783
&dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, // 7e
2784
&dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24,
2785
&dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, // 7f
2786
&dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24, &dsp32c_device::call24