176
176
***************************************************************************/
178
/* ROM is mapped to ADDRESS_SPACE_PROGRAM */
178
/* ROM is mapped to AS_PROGRAM */
179
179
#define program_r(a) cpustate->program->read_byte(a)
181
/* RAM is mapped to ADDRESS_SPACE_DATA */
181
/* RAM is mapped to AS_DATA */
182
182
#define ram_r(a) cpustate->data->read_byte(a)
183
183
#define ram_w(a,V) cpustate->data->write_byte(a, V)
185
/* ports are mapped to ADDRESS_SPACE_IO */
185
/* ports are mapped to AS_IO */
186
186
#define ext_r(a) cpustate->io->read_byte(a)
187
187
#define ext_w(a,V) cpustate->io->write_byte(a, V)
188
188
#define port_r(a) cpustate->io->read_byte(MCS48_PORT_P0 + a)
897
897
/* ensure that regptr is valid before get_info gets called */
898
898
update_regptr(cpustate);
900
state_save_register_device_item(device, 0, cpustate->prevpc);
901
state_save_register_device_item(device, 0, cpustate->pc);
903
state_save_register_device_item(device, 0, cpustate->a);
904
state_save_register_device_item(device, 0, cpustate->psw);
905
state_save_register_device_item(device, 0, cpustate->p1);
906
state_save_register_device_item(device, 0, cpustate->p2);
907
state_save_register_device_item(device, 0, cpustate->ea);
908
state_save_register_device_item(device, 0, cpustate->timer);
909
state_save_register_device_item(device, 0, cpustate->prescaler);
910
state_save_register_device_item(device, 0, cpustate->t1_history);
911
state_save_register_device_item(device, 0, cpustate->sts);
912
state_save_register_device_item(device, 0, cpustate->dbbi);
913
state_save_register_device_item(device, 0, cpustate->dbbo);
915
state_save_register_device_item(device, 0, cpustate->irq_state);
916
state_save_register_device_item(device, 0, cpustate->irq_in_progress);
917
state_save_register_device_item(device, 0, cpustate->timer_overflow);
918
state_save_register_device_item(device, 0, cpustate->timer_flag);
919
state_save_register_device_item(device, 0, cpustate->tirq_enabled);
920
state_save_register_device_item(device, 0, cpustate->xirq_enabled);
921
state_save_register_device_item(device, 0, cpustate->timecount_enabled);
922
state_save_register_device_item(device, 0, cpustate->flags_enabled);
923
state_save_register_device_item(device, 0, cpustate->dma_enabled);
925
state_save_register_device_item(device, 0, cpustate->a11);
900
device->save_item(NAME(cpustate->prevpc));
901
device->save_item(NAME(cpustate->pc));
903
device->save_item(NAME(cpustate->a));
904
device->save_item(NAME(cpustate->psw));
905
device->save_item(NAME(cpustate->p1));
906
device->save_item(NAME(cpustate->p2));
907
device->save_item(NAME(cpustate->ea));
908
device->save_item(NAME(cpustate->timer));
909
device->save_item(NAME(cpustate->prescaler));
910
device->save_item(NAME(cpustate->t1_history));
911
device->save_item(NAME(cpustate->sts));
912
device->save_item(NAME(cpustate->dbbi));
913
device->save_item(NAME(cpustate->dbbo));
915
device->save_item(NAME(cpustate->irq_state));
916
device->save_item(NAME(cpustate->irq_in_progress));
917
device->save_item(NAME(cpustate->timer_overflow));
918
device->save_item(NAME(cpustate->timer_flag));
919
device->save_item(NAME(cpustate->tirq_enabled));
920
device->save_item(NAME(cpustate->xirq_enabled));
921
device->save_item(NAME(cpustate->timecount_enabled));
922
device->save_item(NAME(cpustate->flags_enabled));
923
device->save_item(NAME(cpustate->dma_enabled));
925
device->save_item(NAME(cpustate->a11));
1225
1225
***************************************************************************/
1227
1227
/* FIXME: the memory maps should probably support rom banking for EA */
1228
static ADDRESS_MAP_START(program_10bit, ADDRESS_SPACE_PROGRAM, 8)
1228
static ADDRESS_MAP_START(program_10bit, AS_PROGRAM, 8)
1229
1229
AM_RANGE(0x000, 0x3ff) AM_ROM
1230
1230
ADDRESS_MAP_END
1232
static ADDRESS_MAP_START(program_11bit, ADDRESS_SPACE_PROGRAM, 8)
1232
static ADDRESS_MAP_START(program_11bit, AS_PROGRAM, 8)
1233
1233
AM_RANGE(0x000, 0x7ff) AM_ROM
1234
1234
ADDRESS_MAP_END
1236
static ADDRESS_MAP_START(program_12bit, ADDRESS_SPACE_PROGRAM, 8)
1236
static ADDRESS_MAP_START(program_12bit, AS_PROGRAM, 8)
1237
1237
AM_RANGE(0x000, 0xfff) AM_ROM
1238
1238
ADDRESS_MAP_END
1240
static ADDRESS_MAP_START(data_6bit, ADDRESS_SPACE_DATA, 8)
1240
static ADDRESS_MAP_START(data_6bit, AS_DATA, 8)
1241
1241
AM_RANGE(0x00, 0x3f) AM_RAM
1242
1242
ADDRESS_MAP_END
1244
static ADDRESS_MAP_START(data_7bit, ADDRESS_SPACE_DATA, 8)
1244
static ADDRESS_MAP_START(data_7bit, AS_DATA, 8)
1245
1245
AM_RANGE(0x00, 0x7f) AM_RAM
1246
1246
ADDRESS_MAP_END
1248
static ADDRESS_MAP_START(data_8bit, ADDRESS_SPACE_DATA, 8)
1248
static ADDRESS_MAP_START(data_8bit, AS_DATA, 8)
1249
1249
AM_RANGE(0x00, 0xff) AM_RAM
1250
1250
ADDRESS_MAP_END
1375
1375
case CPUINFO_INT_MIN_CYCLES: info->i = 1; break;
1376
1376
case CPUINFO_INT_MAX_CYCLES: info->i = 3; break;
1378
case DEVINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 8; break;
1379
case DEVINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 12; break;
1380
case DEVINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_PROGRAM: info->i = 0; break;
1381
case DEVINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_DATA: info->i = 8; break;
1382
case DEVINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_DATA: /*info->i = 6 or 7 or 8;*/ break;
1383
case DEVINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_DATA: info->i = 0; break;
1384
case DEVINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_IO: info->i = 8; break;
1385
case DEVINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_IO: info->i = 9; break;
1386
case DEVINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_IO: info->i = 0; break;
1378
case DEVINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 8; break;
1379
case DEVINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 12; break;
1380
case DEVINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break;
1381
case DEVINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 8; break;
1382
case DEVINFO_INT_ADDRBUS_WIDTH + AS_DATA: /*info->i = 6 or 7 or 8;*/ break;
1383
case DEVINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break;
1384
case DEVINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 8; break;
1385
case DEVINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 9; break;
1386
case DEVINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break;
1388
1388
case CPUINFO_INT_INPUT_STATE + MCS48_INPUT_IRQ: info->i = cpustate->irq_state ? ASSERT_LINE : CLEAR_LINE; break;
1389
1389
case CPUINFO_INT_INPUT_STATE + MCS48_INPUT_EA: info->i = cpustate->ea; break;