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Viewing changes to src/emu/cpu/sh4/sh4comn.c

  • Committer: Bazaar Package Importer
  • Author(s): Jordi Mallach, Emmanuel Kasper, Félix Arreola Rodríguez, Jordi Mallach
  • Date: 2011-05-11 21:06:50 UTC
  • mfrom: (1.1.1 upstream)
  • Revision ID: james.westby@ubuntu.com-20110511210650-jizvh8a6x117y9hr
Tags: 0.142-1
[ Emmanuel Kasper ]
* New upstream release
* Set NOWERROR=1 to allow compiling with gcc-4.6
* Remove fix_powerpc_build.patch, as upstream has taken it in this release
* Add gnome-video-arcade front end as a suggested package

[ Félix Arreola Rodríguez ]
* Add kfreebsd-build.patch to quilt series, to fix build on kfreebsd

[ Jordi Mallach ]
* Remove unneeded and bogus addition of --with-quilt to the dh invocation.
* Add Cesare Falco (long time Ubuntu maintainer) to Uploaders, and wrap
  them into multiple lines.

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Lines of Context:
src/emu/cpu/sh4/sh4comn.c
30
30
static const UINT16 tcor[] = { TCOR0, TCOR1, TCOR2 };
31
31
static const UINT16 tcr[] = { TCR0, TCR1, TCR2 };
32
32
 
33
 
INLINE sh4_state *get_safe_token(device_t *device)
34
 
{
35
 
        assert(device != NULL);
36
 
        assert(device->type() == SH4);
37
 
        return (sh4_state *)downcast<legacy_cpu_device *>(device)->token();
38
 
}
39
 
 
40
33
void sh4_change_register_bank(sh4_state *sh4, int to)
41
34
{
42
35
int s;
200
193
        sh4->sgr = sh4->r[15];
201
194
 
202
195
        sh4->sr |= MD;
203
 
        if ((sh4->device->machine->debug_flags & DEBUG_FLAG_ENABLED) != 0)
 
196
        if ((sh4->device->machine().debug_flags & DEBUG_FLAG_ENABLED) != 0)
204
197
                sh4_syncronize_register_bank(sh4, (sh4->sr & sRB) >> 29);
205
198
        if (!(sh4->sr & sRB))
206
199
                sh4_change_register_bank(sh4, 1);
219
212
        // elapsed:total = x : ticks
220
213
        // x=elapsed*tics/total -> x=elapsed*(double)100000000/rtcnt_div[(sh4->m[RTCSR] >> 3) & 7]
221
214
        // ticks/total=ticks / ((rtcnt_div[(sh4->m[RTCSR] >> 3) & 7] * ticks) / 100000000)=1/((rtcnt_div[(sh4->m[RTCSR] >> 3) & 7] / 100000000)=100000000/rtcnt_div[(sh4->m[RTCSR] >> 3) & 7]
222
 
        return base + (UINT32)((attotime_to_double(timer_timeelapsed(timer)) * (double)hertz) / (double)divisor);
 
215
        return base + (UINT32)((timer->elapsed().as_double() * (double)hertz) / (double)divisor);
223
216
}
224
217
 
225
218
static void sh4_refresh_timer_recompute(sh4_state *sh4)
231
224
        ticks = sh4->m[RTCOR]-sh4->m[RTCNT];
232
225
        if (ticks <= 0)
233
226
                ticks = 256 + ticks;
234
 
        timer_adjust_oneshot(sh4->refresh_timer, attotime_mul(attotime_mul(ATTOTIME_IN_HZ(sh4->bus_clock), rtcnt_div[(sh4->m[RTCSR] >> 3) & 7]), ticks), 0);
 
227
        sh4->refresh_timer->adjust(attotime::from_hz(sh4->bus_clock) * rtcnt_div[(sh4->m[RTCSR] >> 3) & 7] * ticks);
235
228
        sh4->refresh_timer_base = sh4->m[RTCNT];
236
229
}
237
230
 
242
235
 
243
236
INLINE attotime sh4_scale_up_mame_time(attotime _time1, UINT32 factor1)
244
237
{
245
 
        return attotime_add(attotime_mul(_time1, factor1), _time1);
 
238
        return _time1 * factor1 + _time1;
246
239
}
247
240
 
248
241
static UINT32 compute_ticks_timer(emu_timer *timer, int hertz, int divisor)
249
242
{
250
243
        double ret;
251
244
 
252
 
        ret=((attotime_to_double(timer_timeleft(timer)) * (double)hertz) / (double)divisor) - 1;
 
245
        ret=((timer->remaining().as_double() * (double)hertz) / (double)divisor) - 1;
253
246
        return (UINT32)ret;
254
247
}
255
248
 
258
251
        double ticks;
259
252
 
260
253
        ticks = sh4->m[tcnt[which]];
261
 
        timer_adjust_oneshot(sh4->timer[which], sh4_scale_up_mame_time(attotime_mul(ATTOTIME_IN_HZ(sh4->pm_clock), tcnt_div[sh4->m[tcr[which]] & 7]), ticks), which);
 
254
        sh4->timer[which]->adjust(sh4_scale_up_mame_time(attotime::from_hz(sh4->pm_clock) * tcnt_div[sh4->m[tcr[which]] & 7], ticks), which);
262
255
}
263
256
 
264
257
static TIMER_CALLBACK( sh4_refresh_timer_callback )
376
369
{
377
370
        sh4_state *sh4 = (sh4_state *)ptr;
378
371
 
379
 
        timer_adjust_oneshot(sh4->rtc_timer, ATTOTIME_IN_HZ(128), 0);
 
372
        sh4->rtc_timer->adjust(attotime::from_hz(128));
380
373
        sh4->m[R64CNT] = (sh4->m[R64CNT]+1) & 0x7f;
381
374
        if (sh4->m[R64CNT] == 64)
382
375
        {
460
453
        if (timermode == 1)
461
454
        {
462
455
                sh4->dma_timer_active[channel] = 1;
463
 
                timer_adjust_oneshot(sh4->dma_timer[channel], sh4->device->cycles_to_attotime(2*count+1), channel);
 
456
                sh4->dma_timer[channel]->adjust(sh4->device->cycles_to_attotime(2*count+1), channel);
464
457
        }
465
458
        else if (timermode == 2)
466
459
        {
467
460
                sh4->dma_timer_active[channel] = 1;
468
 
                timer_adjust_oneshot(sh4->dma_timer[channel], attotime_zero, channel);
 
461
                sh4->dma_timer[channel]->adjust(attotime::zero, channel);
469
462
        }
470
463
 
471
464
        src &= AM;
608
601
                if (sh4->dma_timer_active[channel])
609
602
                {
610
603
                        logerror("SH4: DMA %d cancelled in-flight but all data transferred", channel);
611
 
                        timer_adjust_oneshot(sh4->dma_timer[channel], attotime_never, channel);
 
604
                        sh4->dma_timer[channel]->adjust(attotime::never, channel);
612
605
                        sh4->dma_timer_active[channel] = 0;
613
606
                }
614
607
        }
624
617
                if (sh4->dma_timer_active[s])
625
618
                {
626
619
                        logerror("SH4: DMA %d cancelled due to NMI but all data transferred", s);
627
 
                        timer_adjust_oneshot(sh4->dma_timer[s], attotime_never, s);
 
620
                        sh4->dma_timer[s]->adjust(attotime::never, s);
628
621
                        sh4->dma_timer_active[s] = 0;
629
622
                }
630
623
        }
632
625
 
633
626
WRITE32_HANDLER( sh4_internal_w )
634
627
{
635
 
        sh4_state *sh4 = get_safe_token(space->cpu);
 
628
        sh4_state *sh4 = get_safe_token(&space->device());
636
629
        int a;
637
630
        UINT32 old = sh4->m[offset];
638
631
        COMBINE_DATA(sh4->m+offset);
678
671
                }
679
672
                else
680
673
                {
681
 
                        timer_adjust_oneshot(sh4->refresh_timer, attotime_never, 0);
 
674
                        sh4->refresh_timer->adjust(attotime::never);
682
675
                }
683
676
                break;
684
677
 
724
717
                }
725
718
                if ((sh4->m[RCR2] & 8) && (~old & 8))
726
719
                { // 0 -> 1
727
 
                        timer_adjust_oneshot(sh4->rtc_timer, ATTOTIME_IN_HZ(128), 0);
 
720
                        sh4->rtc_timer->adjust(attotime::from_hz(128));
728
721
                }
729
722
                else if (~(sh4->m[RCR2]) & 8)
730
723
                { // 0
731
 
                        timer_adjust_oneshot(sh4->rtc_timer, attotime_never, 0);
 
724
                        sh4->rtc_timer->adjust(attotime::never);
732
725
                }
733
726
                break;
734
727
 
737
730
                if (old & 1)
738
731
                        sh4->m[TCNT0] = compute_ticks_timer(sh4->timer[0], sh4->pm_clock, tcnt_div[sh4->m[TCR0] & 7]);
739
732
                if ((sh4->m[TSTR] & 1) == 0) {
740
 
                        timer_adjust_oneshot(sh4->timer[0], attotime_never, 0);
 
733
                        sh4->timer[0]->adjust(attotime::never);
741
734
                } else
742
735
                        sh4_timer_recompute(sh4, 0);
743
736
 
744
737
                if (old & 2)
745
738
                        sh4->m[TCNT1] = compute_ticks_timer(sh4->timer[1], sh4->pm_clock, tcnt_div[sh4->m[TCR1] & 7]);
746
739
                if ((sh4->m[TSTR] & 2) == 0) {
747
 
                        timer_adjust_oneshot(sh4->timer[1], attotime_never, 0);
 
740
                        sh4->timer[1]->adjust(attotime::never);
748
741
                } else
749
742
                        sh4_timer_recompute(sh4, 1);
750
743
 
751
744
                if (old & 4)
752
745
                        sh4->m[TCNT2] = compute_ticks_timer(sh4->timer[2], sh4->pm_clock, tcnt_div[sh4->m[TCR2] & 7]);
753
746
                if ((sh4->m[TSTR] & 4) == 0) {
754
 
                        timer_adjust_oneshot(sh4->timer[2], attotime_never, 0);
 
747
                        sh4->timer[2]->adjust(attotime::never);
755
748
                } else
756
749
                        sh4_timer_recompute(sh4, 2);
757
750
                break;
944
937
 
945
938
READ32_HANDLER( sh4_internal_r )
946
939
{
947
 
        sh4_state *sh4 = get_safe_token(space->cpu);
 
940
        sh4_state *sh4 = get_safe_token(&space->device());
948
941
        //  logerror("sh4_internal_r:  Read %08x (%x) @ %08x\n", 0xfe000000+((offset & 0x3fc0) << 11)+((offset & 0x3f) << 2), offset, mem_mask);
949
942
        switch( offset )
950
943
        {
952
945
                if ((sh4->m[RTCSR] >> 3) & 7)
953
946
                { // activated
954
947
                        //((double)rtcnt_div[(sh4->m[RTCSR] >> 3) & 7] / (double)100000000)
955
 
                        //return (refresh_timer_base + (timer_timeelapsed(sh4->refresh_timer) * (double)100000000) / (double)rtcnt_div[(sh4->m[RTCSR] >> 3) & 7]) & 0xff;
 
948
                        //return (refresh_timer_base + (sh4->refresh_timer->elapsed() * (double)100000000) / (double)rtcnt_div[(sh4->m[RTCSR] >> 3) & 7]) & 0xff;
956
949
                        return compute_ticks_refresh_timer(sh4->refresh_timer, sh4->bus_clock, sh4->refresh_timer_base, rtcnt_div[(sh4->m[RTCSR] >> 3) & 7]) & 0xff;
957
950
                }
958
951
                else
1038
1031
        if (sh4->irln == value)
1039
1032
                return;
1040
1033
        sh4->irln = value;
1041
 
        cpu_set_input_line(device, SH4_IRLn, ASSERT_LINE);
1042
 
        cpu_set_input_line(device, SH4_IRLn, CLEAR_LINE);
 
1034
        device_set_input_line(device, SH4_IRLn, ASSERT_LINE);
 
1035
        device_set_input_line(device, SH4_IRLn, CLEAR_LINE);
1043
1036
}
1044
1037
 
1045
1038
void sh4_set_irq_line(sh4_state *sh4, int irqline, int state) // set state of external interrupt line
1167
1160
 
1168
1161
        for (i=0; i<3; i++)
1169
1162
        {
1170
 
                sh4->timer[i] = timer_alloc(device->machine, sh4_timer_callback, sh4);
1171
 
                timer_adjust_oneshot(sh4->timer[i], attotime_never, i);
 
1163
                sh4->timer[i] = device->machine().scheduler().timer_alloc(FUNC(sh4_timer_callback), sh4);
 
1164
                sh4->timer[i]->adjust(attotime::never, i);
1172
1165
        }
1173
1166
 
1174
1167
        for (i=0; i<4; i++)
1175
1168
        {
1176
 
                sh4->dma_timer[i] = timer_alloc(device->machine, sh4_dmac_callback, sh4);
1177
 
                timer_adjust_oneshot(sh4->dma_timer[i], attotime_never, i);
 
1169
                sh4->dma_timer[i] = device->machine().scheduler().timer_alloc(FUNC(sh4_dmac_callback), sh4);
 
1170
                sh4->dma_timer[i]->adjust(attotime::never, i);
1178
1171
        }
1179
1172
 
1180
 
        sh4->refresh_timer = timer_alloc(device->machine, sh4_refresh_timer_callback, sh4);
1181
 
        timer_adjust_oneshot(sh4->refresh_timer, attotime_never, 0);
 
1173
        sh4->refresh_timer = device->machine().scheduler().timer_alloc(FUNC(sh4_refresh_timer_callback), sh4);
 
1174
        sh4->refresh_timer->adjust(attotime::never);
1182
1175
        sh4->refresh_timer_base = 0;
1183
1176
 
1184
 
        sh4->rtc_timer = timer_alloc(device->machine, sh4_rtc_timer_callback, sh4);
1185
 
        timer_adjust_oneshot(sh4->rtc_timer, attotime_never, 0);
 
1177
        sh4->rtc_timer = device->machine().scheduler().timer_alloc(FUNC(sh4_rtc_timer_callback), sh4);
 
1178
        sh4->rtc_timer->adjust(attotime::never);
1186
1179
 
1187
 
        sh4->m = auto_alloc_array(device->machine, UINT32, 16384);
 
1180
        sh4->m = auto_alloc_array(device->machine(), UINT32, 16384);
1188
1181
}
1189
1182
 
1190
1183
void sh4_dma_ddt(device_t *device, struct sh4_ddt_dma *s)
1314
1307
        }
1315
1308
}
1316
1309
 
 
1310
UINT32 sh4_getsqremap(sh4_state *sh4, UINT32 address)
 
1311
{
 
1312
        if (!sh4->sh4_mmu_enabled)
 
1313
                return address;
 
1314
        else
 
1315
        {
 
1316
                int i;
 
1317
                UINT32 topaddr = address&0xfff00000;
 
1318
 
 
1319
                for (i=0;i<64;i++)
 
1320
                {
 
1321
                        UINT32 topcmp = sh4->sh4_tlb_address[i]&0xfff00000;
 
1322
                        if (topcmp==topaddr)
 
1323
                                return (address&0x000fffff) | ((sh4->sh4_tlb_data[i])&0xfff00000);
 
1324
                }
 
1325
 
 
1326
        }
 
1327
 
 
1328
        return address;
 
1329
}
 
1330
 
 
1331
READ64_HANDLER( sh4_tlb_r )
 
1332
{
 
1333
        sh4_state *sh4 = get_safe_token(&space->device());
 
1334
 
 
1335
        int offs = offset*8;
 
1336
 
 
1337
        if (offs >= 0x01000000)
 
1338
        {
 
1339
                UINT8 i = (offs>>8)&63;
 
1340
                return sh4->sh4_tlb_data[i];
 
1341
        }
 
1342
        else
 
1343
        {
 
1344
                UINT8 i = (offs>>8)&63;
 
1345
                return sh4->sh4_tlb_address[i];
 
1346
        }
 
1347
}
 
1348
 
 
1349
WRITE64_HANDLER( sh4_tlb_w )
 
1350
{
 
1351
        sh4_state *sh4 = get_safe_token(&space->device());
 
1352
 
 
1353
        int offs = offset*8;
 
1354
 
 
1355
        if (offs >= 0x01000000)
 
1356
        {
 
1357
                UINT8 i = (offs>>8)&63;
 
1358
                sh4->sh4_tlb_data[i]  = data&0xffffffff;
 
1359
        }
 
1360
        else
 
1361
        {
 
1362
                UINT8 i = (offs>>8)&63;
 
1363
                sh4->sh4_tlb_address[i] = data&0xffffffff;
 
1364
        }
 
1365
}
 
1366