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* CPUM - CPU Monitor(/ Manager).
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* Copyright (C) 2006-2010 Oracle Corporation
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* This file is part of VirtualBox Open Source Edition (OSE), as
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* available from http://www.virtualbox.org. This file is free software;
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* you can redistribute it and/or modify it under the terms of the GNU
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* General Public License (GPL) as published by the Free Software
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* Foundation, in version 2 as it comes in the "COPYING" file of the
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* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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* The contents of this file may alternatively be used under the terms
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* of the Common Development and Distribution License Version 1.0
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* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
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* VirtualBox OSE distribution, in which case the provisions of the
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* CDDL are applicable instead of those of the GPL.
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* You may elect to license modified versions of this file under the
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* terms and conditions of either the GPL or the CDDL or both.
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#ifndef ___VBox_vmm_cpum_h
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#define ___VBox_vmm_cpum_h
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#include <iprt/types.h>
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#include <VBox/vmm/cpumctx.h>
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/** @defgroup grp_cpum The CPU Monitor / Manager API
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* CPUID feature to set or clear.
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typedef enum CPUMCPUIDFEATURE
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CPUMCPUIDFEATURE_INVALID = 0,
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/** The APIC feature bit. (Std+Ext) */
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CPUMCPUIDFEATURE_APIC,
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/** The sysenter/sysexit feature bit. (Std) */
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/** The SYSCALL/SYSEXIT feature bit (64 bits mode only for Intel CPUs). (Ext) */
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CPUMCPUIDFEATURE_SYSCALL,
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/** The PAE feature bit. (Std+Ext) */
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/** The NXE feature bit. (Ext) */
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/** The LAHF/SAHF feature bit (64 bits mode only). (Ext) */
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CPUMCPUIDFEATURE_LAHF,
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/** The LONG MODE feature bit. (Ext) */
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CPUMCPUIDFEATURE_LONG_MODE,
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/** The PAT feature bit. (Std+Ext) */
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/** The x2APIC feature bit. (Std) */
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CPUMCPUIDFEATURE_X2APIC,
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/** The RDTSCP feature bit. (Ext) */
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CPUMCPUIDFEATURE_RDTSCP,
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/** 32bit hackishness. */
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CPUMCPUIDFEATURE_32BIT_HACK = 0x7fffffff
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typedef enum CPUMCPUVENDOR
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CPUMCPUVENDOR_INVALID = 0,
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CPUMCPUVENDOR_UNKNOWN,
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CPUMCPUVENDOR_SYNTHETIC,
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/** 32bit hackishness. */
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CPUMCPUVENDOR_32BIT_HACK = 0x7fffffff
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/** @name Guest Register Getters.
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VMMDECL(void) CPUMGetGuestGDTR(PVMCPU pVCpu, PVBOXGDTR pGDTR);
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VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PVMCPU pVCpu, uint16_t *pcbLimit);
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VMMDECL(RTSEL) CPUMGetGuestTR(PVMCPU pVCpu, PCPUMSELREGHID pHidden);
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VMMDECL(RTSEL) CPUMGetGuestLDTR(PVMCPU pVCpu);
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VMMDECL(uint64_t) CPUMGetGuestCR0(PVMCPU pVCpu);
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VMMDECL(uint64_t) CPUMGetGuestCR2(PVMCPU pVCpu);
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VMMDECL(uint64_t) CPUMGetGuestCR3(PVMCPU pVCpu);
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VMMDECL(uint64_t) CPUMGetGuestCR4(PVMCPU pVCpu);
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VMMDECL(uint64_t) CPUMGetGuestCR8(PVMCPU pVCpu);
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VMMDECL(int) CPUMGetGuestCRx(PVMCPU pVCpu, unsigned iReg, uint64_t *pValue);
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VMMDECL(uint32_t) CPUMGetGuestEFlags(PVMCPU pVCpu);
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VMMDECL(uint32_t) CPUMGetGuestEIP(PVMCPU pVCpu);
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VMMDECL(uint64_t) CPUMGetGuestRIP(PVMCPU pVCpu);
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VMMDECL(uint32_t) CPUMGetGuestEAX(PVMCPU pVCpu);
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VMMDECL(uint32_t) CPUMGetGuestEBX(PVMCPU pVCpu);
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VMMDECL(uint32_t) CPUMGetGuestECX(PVMCPU pVCpu);
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VMMDECL(uint32_t) CPUMGetGuestEDX(PVMCPU pVCpu);
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VMMDECL(uint32_t) CPUMGetGuestESI(PVMCPU pVCpu);
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VMMDECL(uint32_t) CPUMGetGuestEDI(PVMCPU pVCpu);
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VMMDECL(uint32_t) CPUMGetGuestESP(PVMCPU pVCpu);
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VMMDECL(uint32_t) CPUMGetGuestEBP(PVMCPU pVCpu);
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VMMDECL(RTSEL) CPUMGetGuestCS(PVMCPU pVCpu);
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VMMDECL(RTSEL) CPUMGetGuestDS(PVMCPU pVCpu);
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VMMDECL(RTSEL) CPUMGetGuestES(PVMCPU pVCpu);
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VMMDECL(RTSEL) CPUMGetGuestFS(PVMCPU pVCpu);
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VMMDECL(RTSEL) CPUMGetGuestGS(PVMCPU pVCpu);
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VMMDECL(RTSEL) CPUMGetGuestSS(PVMCPU pVCpu);
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VMMDECL(uint64_t) CPUMGetGuestDR0(PVMCPU pVCpu);
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VMMDECL(uint64_t) CPUMGetGuestDR1(PVMCPU pVCpu);
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VMMDECL(uint64_t) CPUMGetGuestDR2(PVMCPU pVCpu);
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VMMDECL(uint64_t) CPUMGetGuestDR3(PVMCPU pVCpu);
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VMMDECL(uint64_t) CPUMGetGuestDR6(PVMCPU pVCpu);
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VMMDECL(uint64_t) CPUMGetGuestDR7(PVMCPU pVCpu);
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VMMDECL(int) CPUMGetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t *pValue);
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VMMDECL(void) CPUMGetGuestCpuId(PVMCPU pVCpu, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx);
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VMMDECL(uint32_t) CPUMGetGuestCpuIdStdMax(PVM pVM);
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VMMDECL(uint32_t) CPUMGetGuestCpuIdExtMax(PVM pVM);
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VMMDECL(uint32_t) CPUMGetGuestCpuIdCentaurMax(PVM pVM);
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VMMDECL(uint64_t) CPUMGetGuestEFER(PVMCPU pVCpu);
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VMMDECL(int) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue);
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VMMDECL(int) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue);
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VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM);
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VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM);
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/** @name Guest Register Setters.
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VMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit);
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VMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit);
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VMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr);
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VMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr);
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VMMDECL(int) CPUMSetGuestCR0(PVMCPU pVCpu, uint64_t cr0);
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VMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2);
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VMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3);
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VMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4);
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VMMDECL(int) CPUMSetGuestDR0(PVMCPU pVCpu, uint64_t uDr0);
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VMMDECL(int) CPUMSetGuestDR1(PVMCPU pVCpu, uint64_t uDr1);
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VMMDECL(int) CPUMSetGuestDR2(PVMCPU pVCpu, uint64_t uDr2);
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VMMDECL(int) CPUMSetGuestDR3(PVMCPU pVCpu, uint64_t uDr3);
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VMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6);
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VMMDECL(int) CPUMSetGuestDR7(PVMCPU pVCpu, uint64_t uDr7);
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VMMDECL(int) CPUMSetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t Value);
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VMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags);
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VMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip);
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VMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax);
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VMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx);
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VMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx);
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VMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx);
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VMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi);
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VMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi);
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VMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp);
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VMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp);
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VMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs);
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VMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds);
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VMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es);
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VMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs);
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VMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs);
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VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss);
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VMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val);
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VMMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
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VMMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
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VMMDECL(bool) CPUMGetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
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VMMDECL(void) CPUMSetGuestCtx(PVMCPU pVCpu, const PCPUMCTX pCtx);
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/** @name Misc Guest Predicate Functions.
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VMMDECL(bool) CPUMIsGuestIn16BitCode(PVMCPU pVCpu);
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VMMDECL(bool) CPUMIsGuestIn32BitCode(PVMCPU pVCpu);
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VMMDECL(bool) CPUMIsGuestNXEnabled(PVMCPU pVCpu);
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VMMDECL(bool) CPUMIsGuestPageSizeExtEnabled(PVMCPU pVCpu);
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VMMDECL(bool) CPUMIsGuestPagingEnabled(PVMCPU pVCpu);
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VMMDECL(bool) CPUMIsGuestR0WriteProtEnabled(PVMCPU pVCpu);
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VMMDECL(bool) CPUMIsGuestInRealMode(PVMCPU pVCpu);
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VMMDECL(bool) CPUMIsGuestInProtectedMode(PVMCPU pVCpu);
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VMMDECL(bool) CPUMIsGuestInPagedProtectedMode(PVMCPU pVCpu);
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VMMDECL(bool) CPUMIsGuestInLongMode(PVMCPU pVCpu);
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VMMDECL(bool) CPUMIsGuestInPAEMode(PVMCPU pVCpu);
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#ifndef VBOX_WITHOUT_UNNAMED_UNIONS
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* Tests if the guest is running in real mode or not.
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* @returns true if in real mode, otherwise false.
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* @param pCtx Current CPU context
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DECLINLINE(bool) CPUMIsGuestInRealModeEx(PCPUMCTX pCtx)
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return !(pCtx->cr0 & X86_CR0_PE);
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* Tests if the guest is running in paged protected or not.
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* @returns true if in paged protected mode, otherwise false.
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* @param pVM The VM handle.
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DECLINLINE(bool) CPUMIsGuestInPagedProtectedModeEx(PCPUMCTX pCtx)
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return (pCtx->cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
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* Tests if the guest is running in long mode or not.
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* @returns true if in long mode, otherwise false.
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* @param pCtx Current CPU context
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DECLINLINE(bool) CPUMIsGuestInLongModeEx(PCPUMCTX pCtx)
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return (pCtx->msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
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* Tests if the guest is running in 64 bits mode or not.
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* @returns true if in 64 bits protected mode, otherwise false.
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* @param pVM The VM handle.
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* @param pCtx Current CPU context
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DECLINLINE(bool) CPUMIsGuestIn64BitCode(PVMCPU pVCpu, PCCPUMCTXCORE pCtx)
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if (!CPUMIsGuestInLongMode(pVCpu))
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return pCtx->csHid.Attr.n.u1Long;
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* Tests if the guest is running in 64 bits mode or not.
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* @returns true if in 64 bits protected mode, otherwise false.
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* @param pVM The VM handle.
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* @param pCtx Current CPU context
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DECLINLINE(bool) CPUMIsGuestIn64BitCodeEx(PCCPUMCTX pCtx)
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if (!(pCtx->msrEFER & MSR_K6_EFER_LMA))
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return pCtx->csHid.Attr.n.u1Long;
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* Tests if the guest is running in PAE mode or not.
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* @returns true if in PAE mode, otherwise false.
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* @param pCtx Current CPU context
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DECLINLINE(bool) CPUMIsGuestInPAEModeEx(PCPUMCTX pCtx)
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return ( (pCtx->cr4 & X86_CR4_PAE)
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&& CPUMIsGuestInPagedProtectedModeEx(pCtx)
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&& !CPUMIsGuestInLongModeEx(pCtx));
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#endif /* VBOX_WITHOUT_UNNAMED_UNIONS */
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/** @name Hypervisor Register Getters.
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VMMDECL(RTSEL) CPUMGetHyperCS(PVMCPU pVCpu);
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VMMDECL(RTSEL) CPUMGetHyperDS(PVMCPU pVCpu);
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VMMDECL(RTSEL) CPUMGetHyperES(PVMCPU pVCpu);
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VMMDECL(RTSEL) CPUMGetHyperFS(PVMCPU pVCpu);
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VMMDECL(RTSEL) CPUMGetHyperGS(PVMCPU pVCpu);
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VMMDECL(RTSEL) CPUMGetHyperSS(PVMCPU pVCpu);
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#if 0 /* these are not correct. */
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VMMDECL(uint32_t) CPUMGetHyperCR0(PVMCPU pVCpu);
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VMMDECL(uint32_t) CPUMGetHyperCR2(PVMCPU pVCpu);
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VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu);
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VMMDECL(uint32_t) CPUMGetHyperCR4(PVMCPU pVCpu);
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/** This register is only saved on fatal traps. */
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VMMDECL(uint32_t) CPUMGetHyperEAX(PVMCPU pVCpu);
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VMMDECL(uint32_t) CPUMGetHyperEBX(PVMCPU pVCpu);
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/** This register is only saved on fatal traps. */
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VMMDECL(uint32_t) CPUMGetHyperECX(PVMCPU pVCpu);
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/** This register is only saved on fatal traps. */
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VMMDECL(uint32_t) CPUMGetHyperEDX(PVMCPU pVCpu);
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VMMDECL(uint32_t) CPUMGetHyperESI(PVMCPU pVCpu);
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VMMDECL(uint32_t) CPUMGetHyperEDI(PVMCPU pVCpu);
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VMMDECL(uint32_t) CPUMGetHyperEBP(PVMCPU pVCpu);
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VMMDECL(uint32_t) CPUMGetHyperESP(PVMCPU pVCpu);
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VMMDECL(uint32_t) CPUMGetHyperEFlags(PVMCPU pVCpu);
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VMMDECL(uint32_t) CPUMGetHyperEIP(PVMCPU pVCpu);
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VMMDECL(uint64_t) CPUMGetHyperRIP(PVMCPU pVCpu);
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VMMDECL(uint32_t) CPUMGetHyperIDTR(PVMCPU pVCpu, uint16_t *pcbLimit);
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VMMDECL(uint32_t) CPUMGetHyperGDTR(PVMCPU pVCpu, uint16_t *pcbLimit);
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VMMDECL(RTSEL) CPUMGetHyperLDTR(PVMCPU pVCpu);
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VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVMCPU pVCpu);
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VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVMCPU pVCpu);
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VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVMCPU pVCpu);
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VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVMCPU pVCpu);
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VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVMCPU pVCpu);
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VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVMCPU pVCpu);
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VMMDECL(void) CPUMGetHyperCtx(PVMCPU pVCpu, PCPUMCTX pCtx);
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VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu);
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/** @name Hypervisor Register Setters.
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VMMDECL(void) CPUMSetHyperGDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit);
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VMMDECL(void) CPUMSetHyperLDTR(PVMCPU pVCpu, RTSEL SelLDTR);
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VMMDECL(void) CPUMSetHyperIDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit);
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VMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3);
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VMMDECL(void) CPUMSetHyperTR(PVMCPU pVCpu, RTSEL SelTR);
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VMMDECL(void) CPUMSetHyperCS(PVMCPU pVCpu, RTSEL SelCS);
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VMMDECL(void) CPUMSetHyperDS(PVMCPU pVCpu, RTSEL SelDS);
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VMMDECL(void) CPUMSetHyperES(PVMCPU pVCpu, RTSEL SelDS);
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VMMDECL(void) CPUMSetHyperFS(PVMCPU pVCpu, RTSEL SelDS);
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VMMDECL(void) CPUMSetHyperGS(PVMCPU pVCpu, RTSEL SelDS);
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VMMDECL(void) CPUMSetHyperSS(PVMCPU pVCpu, RTSEL SelSS);
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VMMDECL(void) CPUMSetHyperESP(PVMCPU pVCpu, uint32_t u32ESP);
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VMMDECL(int) CPUMSetHyperEFlags(PVMCPU pVCpu, uint32_t Efl);
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VMMDECL(void) CPUMSetHyperEIP(PVMCPU pVCpu, uint32_t u32EIP);
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VMMDECL(void) CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0);
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VMMDECL(void) CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1);
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VMMDECL(void) CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2);
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VMMDECL(void) CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3);
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VMMDECL(void) CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6);
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VMMDECL(void) CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7);
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VMMDECL(void) CPUMSetHyperCtx(PVMCPU pVCpu, const PCPUMCTX pCtx);
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VMMDECL(int) CPUMRecalcHyperDRx(PVMCPU pVCpu);
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VMMDECL(void) CPUMPushHyper(PVMCPU pVCpu, uint32_t u32);
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VMMDECL(void) CPUMHyperSetCtxCore(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore);
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VMMDECL(int) CPUMQueryHyperCtxPtr(PVMCPU pVCpu, PCPUMCTX *ppCtx);
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VMMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVMCPU pVCpu);
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VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu);
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VMMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVMCPU pVCpu);
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VMMDECL(void) CPUMSetGuestCtxCore(PVMCPU pVCpu, PCCPUMCTXCORE pCtxCore);
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VMMR3DECL(int) CPUMR3RawEnter(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore);
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VMMR3DECL(int) CPUMR3RawLeave(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, int rc);
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VMMDECL(uint32_t) CPUMRawGetEFlags(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore);
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VMMDECL(void) CPUMRawSetEFlags(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, uint32_t eflags);
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VMMDECL(int) CPUMHandleLazyFPU(PVMCPU pVCpu);
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/** @name Changed flags
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* These flags are used to keep track of which important register that
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* have been changed since last they were reset. The only one allowed
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* to clear them is REM!
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#define CPUM_CHANGED_FPU_REM RT_BIT(0)
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#define CPUM_CHANGED_CR0 RT_BIT(1)
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#define CPUM_CHANGED_CR4 RT_BIT(2)
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#define CPUM_CHANGED_GLOBAL_TLB_FLUSH RT_BIT(3)
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#define CPUM_CHANGED_CR3 RT_BIT(4)
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#define CPUM_CHANGED_GDTR RT_BIT(5)
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#define CPUM_CHANGED_IDTR RT_BIT(6)
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#define CPUM_CHANGED_LDTR RT_BIT(7)
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#define CPUM_CHANGED_TR RT_BIT(8)
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#define CPUM_CHANGED_SYSENTER_MSR RT_BIT(9)
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#define CPUM_CHANGED_HIDDEN_SEL_REGS RT_BIT(10)
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#define CPUM_CHANGED_CPUID RT_BIT(11)
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#define CPUM_CHANGED_ALL \
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( CPUM_CHANGED_FPU_REM | CPUM_CHANGED_CR0 | CPUM_CHANGED_CR3 | CPUM_CHANGED_CR4 | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR \
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| CPUM_CHANGED_LDTR | CPUM_CHANGED_TR | CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_HIDDEN_SEL_REGS | CPUM_CHANGED_CPUID )
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/** This one is used by raw-mode to indicate that the hidden register
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* information is not longer reliable and have to be re-determined.
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* @remarks This must not be part of CPUM_CHANGED_ALL! */
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#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
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VMMDECL(void) CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedFlags);
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VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl);
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VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels);
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VMMDECL(bool) CPUMSupportsFXSR(PVM pVM);
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VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM);
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VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM);
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VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCPU);
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VMMDECL(void) CPUMDeactivateGuestFPUState(PVMCPU pVCpu);
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VMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu);
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VMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu);
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VMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu);
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VMMDECL(void) CPUMDeactivateHyperDebugState(PVMCPU pVCpu);
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VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore);
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VMMDECL(bool) CPUMAreHiddenSelRegsValid(PVMCPU pVCpu);
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VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu);
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/** @defgroup grp_cpum_r3 The CPU Monitor(/Manager) API
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VMMR3DECL(int) CPUMR3Init(PVM pVM);
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VMMR3DECL(void) CPUMR3Relocate(PVM pVM);
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VMMR3DECL(int) CPUMR3Term(PVM pVM);
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VMMR3DECL(void) CPUMR3Reset(PVM pVM);
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VMMR3DECL(void) CPUMR3ResetCpu(PVMCPU pVCpu);
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VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM);
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VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled);
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VMMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM);
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VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd);
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VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM);
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VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM);
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VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM);
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VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM);
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#endif /* IN_RING3 */
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/** @defgroup grp_cpum_gc The CPU Monitor(/Manager) API
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* Calls a guest trap/interrupt handler directly
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* Assumes a trap stack frame has already been setup on the guest's stack!
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* This function does not return!
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* @param pRegFrame Original trap/interrupt context
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* @param selCS Code selector of handler
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* @param pHandler GC virtual address of handler
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* @param eflags Callee's EFLAGS
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* @param selSS Stack selector for handler
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* @param pEsp Stack address for handler
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DECLASM(void) CPUMGCCallGuestTrapHandler(PCPUMCTXCORE pRegFrame, uint32_t selCS, RTRCPTR pHandler,
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uint32_t eflags, uint32_t selSS, RTRCPTR pEsp);
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* Call guest V86 code directly.
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* This function does not return!
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* @param pRegFrame Original trap/interrupt context
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DECLASM(void) CPUMGCCallV86Code(PCPUMCTXCORE pRegFrame);
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/** @defgroup grp_cpum_r0 The CPU Monitor(/Manager) API
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VMMR0DECL(int) CPUMR0ModuleInit(void);
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VMMR0DECL(int) CPUMR0ModuleTerm(void);
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VMMR0DECL(int) CPUMR0Init(PVM pVM);
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VMMR0DECL(int) CPUMR0LoadGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
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VMMR0DECL(int) CPUMR0SaveGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
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VMMR0DECL(int) CPUMR0SaveGuestDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6);
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VMMR0DECL(int) CPUMR0LoadGuestDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6);
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VMMR0DECL(int) CPUMR0LoadHostDebugState(PVM pVM, PVMCPU pVCpu);
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VMMR0DECL(int) CPUMR0SaveHostDebugState(PVM pVM, PVMCPU pVCpu);
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VMMR0DECL(int) CPUMR0LoadHyperDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6);
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#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
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VMMR0DECL(void) CPUMR0SetLApic(PVM pVM, RTCPUID idHostCpu);
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#endif /* IN_RING0 */