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* HWACCM - VMX Structures and Definitions. (VMM)
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* Copyright (C) 2006-2010 Oracle Corporation
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* This file is part of VirtualBox Open Source Edition (OSE), as
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* available from http://www.virtualbox.org. This file is free software;
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* you can redistribute it and/or modify it under the terms of the GNU
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* General Public License (GPL) as published by the Free Software
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* Foundation, in version 2 as it comes in the "COPYING" file of the
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* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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* The contents of this file may alternatively be used under the terms
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* of the Common Development and Distribution License Version 1.0
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* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
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* VirtualBox OSE distribution, in which case the provisions of the
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* CDDL are applicable instead of those of the GPL.
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* You may elect to license modified versions of this file under the
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* terms and conditions of either the GPL or the CDDL or both.
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#ifndef ___VBox_vmm_vmx_h
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#define ___VBox_vmm_vmx_h
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#include <VBox/types.h>
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#include <iprt/assert.h>
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/** @defgroup grp_vmx vmx Types and Definitions
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/** @name VMX EPT paging structures
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* Number of page table entries in the EPT. (PDPTE/PDE/PTE)
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#define EPT_PG_ENTRIES X86_PG_PAE_ENTRIES
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* EPT Page Directory Pointer Entry. Bit view.
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* @todo uint64_t isn't safe for bitfields (gcc pedantic warnings, and IIRC,
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* this did cause trouble with one compiler/version).
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typedef struct EPTPML4EBITS
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uint64_t u1Present : 1;
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/** Executable bit. */
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uint64_t u1Execute : 1;
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/** Reserved (must be 0). */
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uint64_t u5Reserved : 5;
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/** Available for software. */
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uint64_t u4Available : 4;
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/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
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uint64_t u40PhysAddr : 40;
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/** Availabe for software. */
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uint64_t u12Available : 12;
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AssertCompileSize(EPTPML4EBITS, 8);
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/** Bits 12-51 - - EPT - Physical Page number of the next level. */
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#define EPT_PML4E_PG_MASK X86_PML4E_PG_MASK
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/** The page shift to get the PML4 index. */
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#define EPT_PML4_SHIFT X86_PML4_SHIFT
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/** The PML4 index mask (apply to a shifted page address). */
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#define EPT_PML4_MASK X86_PML4_MASK
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typedef union EPTPML4E
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/** Unsigned integer view. */
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/** 64 bit unsigned integer view. */
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/** 32 bit unsigned integer view. */
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/** Pointer to a PML4 table entry. */
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typedef EPTPML4E *PEPTPML4E;
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/** Pointer to a const PML4 table entry. */
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typedef const EPTPML4E *PCEPTPML4E;
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AssertCompileSize(EPTPML4E, 8);
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typedef struct EPTPML4
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EPTPML4E a[EPT_PG_ENTRIES];
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/** Pointer to an EPT PML4 Table. */
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typedef EPTPML4 *PEPTPML4;
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/** Pointer to a const EPT PML4 Table. */
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typedef const EPTPML4 *PCEPTPML4;
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* EPT Page Directory Pointer Entry. Bit view.
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typedef struct EPTPDPTEBITS
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uint64_t u1Present : 1;
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uint64_t u1Write : 1;
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/** Executable bit. */
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uint64_t u1Execute : 1;
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/** Reserved (must be 0). */
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uint64_t u5Reserved : 5;
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/** Available for software. */
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uint64_t u4Available : 4;
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/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
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uint64_t u40PhysAddr : 40;
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/** Availabe for software. */
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uint64_t u12Available : 12;
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AssertCompileSize(EPTPDPTEBITS, 8);
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/** Bits 12-51 - - EPT - Physical Page number of the next level. */
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#define EPT_PDPTE_PG_MASK X86_PDPE_PG_MASK
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/** The page shift to get the PDPT index. */
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#define EPT_PDPT_SHIFT X86_PDPT_SHIFT
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/** The PDPT index mask (apply to a shifted page address). */
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#define EPT_PDPT_MASK X86_PDPT_MASK_AMD64
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* EPT Page Directory Pointer.
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typedef union EPTPDPTE
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/** Unsigned integer view. */
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/** 64 bit unsigned integer view. */
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/** 32 bit unsigned integer view. */
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/** Pointer to an EPT Page Directory Pointer Entry. */
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typedef EPTPDPTE *PEPTPDPTE;
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/** Pointer to a const EPT Page Directory Pointer Entry. */
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typedef const EPTPDPTE *PCEPTPDPTE;
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AssertCompileSize(EPTPDPTE, 8);
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* EPT Page Directory Pointer Table.
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typedef struct EPTPDPT
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EPTPDPTE a[EPT_PG_ENTRIES];
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/** Pointer to an EPT Page Directory Pointer Table. */
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typedef EPTPDPT *PEPTPDPT;
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/** Pointer to a const EPT Page Directory Pointer Table. */
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typedef const EPTPDPT *PCEPTPDPT;
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* EPT Page Directory Table Entry. Bit view.
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typedef struct EPTPDEBITS
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uint64_t u1Present : 1;
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uint64_t u1Write : 1;
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/** Executable bit. */
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uint64_t u1Execute : 1;
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/** Reserved (must be 0). */
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uint64_t u4Reserved : 4;
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/** Big page (must be 0 here). */
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/** Available for software. */
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uint64_t u4Available : 4;
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/** Physical address of page table. Restricted by maximum physical address width of the cpu. */
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uint64_t u40PhysAddr : 40;
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/** Availabe for software. */
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uint64_t u12Available : 12;
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AssertCompileSize(EPTPDEBITS, 8);
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/** Bits 12-51 - - EPT - Physical Page number of the next level. */
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#define EPT_PDE_PG_MASK X86_PDE_PAE_PG_MASK
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/** The page shift to get the PD index. */
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#define EPT_PD_SHIFT X86_PD_PAE_SHIFT
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/** The PD index mask (apply to a shifted page address). */
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#define EPT_PD_MASK X86_PD_PAE_MASK
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* EPT 2MB Page Directory Table Entry. Bit view.
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typedef struct EPTPDE2MBITS
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uint64_t u1Present : 1;
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uint64_t u1Write : 1;
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/** Executable bit. */
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uint64_t u1Execute : 1;
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/** EPT Table Memory Type. MBZ for non-leaf nodes. */
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/** Ignore PAT memory type */
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uint64_t u1IgnorePAT : 1;
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/** Big page (must be 1 here). */
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/** Available for software. */
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uint64_t u4Available : 4;
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/** Reserved (must be 0). */
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uint64_t u9Reserved : 9;
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/** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
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uint64_t u31PhysAddr : 31;
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/** Availabe for software. */
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uint64_t u12Available : 12;
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AssertCompileSize(EPTPDE2MBITS, 8);
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/** Bits 21-51 - - EPT - Physical Page number of the next level. */
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#define EPT_PDE2M_PG_MASK X86_PDE2M_PAE_PG_MASK
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* EPT Page Directory Table Entry.
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/** 2MB view (big). */
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/** Unsigned integer view. */
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/** 64 bit unsigned integer view. */
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/** 32 bit unsigned integer view. */
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/** Pointer to an EPT Page Directory Table Entry. */
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typedef EPTPDE *PEPTPDE;
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/** Pointer to a const EPT Page Directory Table Entry. */
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typedef const EPTPDE *PCEPTPDE;
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AssertCompileSize(EPTPDE, 8);
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* EPT Page Directory Table.
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EPTPDE a[EPT_PG_ENTRIES];
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/** Pointer to an EPT Page Directory Table. */
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typedef EPTPD *PEPTPD;
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/** Pointer to a const EPT Page Directory Table. */
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typedef const EPTPD *PCEPTPD;
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* EPT Page Table Entry. Bit view.
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typedef struct EPTPTEBITS
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* @remark This is a convenience "misnomer". The bit actually indicates
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* read access and the CPU will consider an entry with any of the
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* first three bits set as present. Since all our valid entries
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* will have this bit set, it can be used as a present indicator
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* and allow some code sharing. */
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uint64_t u1Present : 1;
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/** 1 - Writable bit. */
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uint64_t u1Write : 1;
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/** 2 - Executable bit. */
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uint64_t u1Execute : 1;
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/** 5:3 - EPT Memory Type. MBZ for non-leaf nodes. */
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/** 6 - Ignore PAT memory type */
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uint64_t u1IgnorePAT : 1;
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/** 11:7 - Available for software. */
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uint64_t u5Available : 5;
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/** 51:12 - Physical address of page. Restricted by maximum physical
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* address width of the cpu. */
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uint64_t u40PhysAddr : 40;
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/** 63:52 - Available for software. */
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uint64_t u12Available : 12;
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AssertCompileSize(EPTPTEBITS, 8);
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/** Bits 12-51 - - EPT - Physical Page number of the next level. */
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#define EPT_PTE_PG_MASK X86_PTE_PAE_PG_MASK
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/** The page shift to get the EPT PTE index. */
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#define EPT_PT_SHIFT X86_PT_PAE_SHIFT
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/** The EPT PT index mask (apply to a shifted page address). */
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#define EPT_PT_MASK X86_PT_PAE_MASK
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* EPT Page Table Entry.
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/** Unsigned integer view. */
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/** 64 bit unsigned integer view. */
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/** 32 bit unsigned integer view. */
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/** Pointer to an EPT Page Directory Table Entry. */
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typedef EPTPTE *PEPTPTE;
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/** Pointer to a const EPT Page Directory Table Entry. */
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typedef const EPTPTE *PCEPTPTE;
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AssertCompileSize(EPTPTE, 8);
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EPTPTE a[EPT_PG_ENTRIES];
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/** Pointer to an extended page table. */
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typedef EPTPT *PEPTPT;
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/** Pointer to a const extended table. */
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typedef const EPTPT *PCEPTPT;
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* VPID and EPT flush types
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/* Invalidate a specific page. */
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/* Invalidate one context (VPID or EPT) */
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VMX_FLUSH_SINGLE_CONTEXT = 1,
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/* Invalidate all contexts (VPIDs or EPTs) */
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VMX_FLUSH_ALL_CONTEXTS = 2,
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/* Invalidate a single VPID context retaining global mappings. */
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VMX_FLUSH_SINGLE_CONTEXT_WITHOUT_GLOBAL = 3,
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/** 32bit hackishness. */
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VMX_FLUSH_32BIT_HACK = 0x7fffffff
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/** @name MSR load/store elements
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uint32_t u32IndexMSR;
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uint32_t u32Reserved;
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/** Pointer to an MSR load/store element. */
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typedef VMXMSR *PVMXMSR;
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/** Pointer to a const MSR load/store element. */
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typedef const VMXMSR *PCVMXMSR;
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/** @name VT-x capability qword
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uint32_t disallowed0;
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/** @name VMX Basic Exit Reasons.
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/** And-mask for setting reserved bits to zero */
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#define VMX_EFLAGS_RESERVED_0 (~0xffc08028)
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/** Or-mask for setting reserved bits to 1 */
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#define VMX_EFLAGS_RESERVED_1 0x00000002
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/** @name VMX Basic Exit Reasons.
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/** -1 Invalid exit code */
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#define VMX_EXIT_INVALID -1
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/** 0 Exception or non-maskable interrupt (NMI). */
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#define VMX_EXIT_EXCEPTION 0
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/** 1 External interrupt. */
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#define VMX_EXIT_EXTERNAL_IRQ 1
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/** 2 Triple fault. */
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#define VMX_EXIT_TRIPLE_FAULT 2
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/** 3 INIT signal. */
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#define VMX_EXIT_INIT_SIGNAL 3
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/** 4 Start-up IPI (SIPI). */
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#define VMX_EXIT_SIPI 4
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/** 5 I/O system-management interrupt (SMI). */
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#define VMX_EXIT_IO_SMI_IRQ 5
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#define VMX_EXIT_SMI_IRQ 6
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/** 7 Interrupt window. */
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#define VMX_EXIT_IRQ_WINDOW 7
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/** 9 Task switch. */
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#define VMX_EXIT_TASK_SWITCH 9
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/** 10 Guest software attempted to execute CPUID. */
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#define VMX_EXIT_CPUID 10
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/** 12 Guest software attempted to execute HLT. */
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#define VMX_EXIT_HLT 12
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/** 13 Guest software attempted to execute INVD. */
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#define VMX_EXIT_INVD 13
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/** 14 Guest software attempted to execute INVPG. */
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#define VMX_EXIT_INVPG 14
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/** 15 Guest software attempted to execute RDPMC. */
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#define VMX_EXIT_RDPMC 15
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/** 16 Guest software attempted to execute RDTSC. */
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#define VMX_EXIT_RDTSC 16
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/** 17 Guest software attempted to execute RSM in SMM. */
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#define VMX_EXIT_RSM 17
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/** 18 Guest software executed VMCALL. */
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#define VMX_EXIT_VMCALL 18
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/** 19 Guest software executed VMCLEAR. */
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#define VMX_EXIT_VMCLEAR 19
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/** 20 Guest software executed VMLAUNCH. */
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#define VMX_EXIT_VMLAUNCH 20
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/** 21 Guest software executed VMPTRLD. */
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#define VMX_EXIT_VMPTRLD 21
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/** 22 Guest software executed VMPTRST. */
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#define VMX_EXIT_VMPTRST 22
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/** 23 Guest software executed VMREAD. */
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#define VMX_EXIT_VMREAD 23
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/** 24 Guest software executed VMRESUME. */
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#define VMX_EXIT_VMRESUME 24
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/** 25 Guest software executed VMWRITE. */
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#define VMX_EXIT_VMWRITE 25
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/** 26 Guest software executed VMXOFF. */
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#define VMX_EXIT_VMXOFF 26
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/** 27 Guest software executed VMXON. */
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#define VMX_EXIT_VMXON 27
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/** 28 Control-register accesses. */
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#define VMX_EXIT_CRX_MOVE 28
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/** 29 Debug-register accesses. */
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#define VMX_EXIT_DRX_MOVE 29
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/** 30 I/O instruction. */
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#define VMX_EXIT_PORT_IO 30
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/** 31 RDMSR. Guest software attempted to execute RDMSR. */
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#define VMX_EXIT_RDMSR 31
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/** 32 WRMSR. Guest software attempted to execute WRMSR. */
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#define VMX_EXIT_WRMSR 32
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/** 33 VM-entry failure due to invalid guest state. */
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#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
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/** 34 VM-entry failure due to MSR loading. */
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#define VMX_EXIT_ERR_MSR_LOAD 34
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/** 36 Guest software executed MWAIT. */
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#define VMX_EXIT_MWAIT 36
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/** 39 Guest software attempted to execute MONITOR. */
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#define VMX_EXIT_MONITOR 39
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/** 40 Guest software attempted to execute PAUSE. */
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#define VMX_EXIT_PAUSE 40
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/** 41 VM-entry failure due to machine-check. */
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#define VMX_EXIT_ERR_MACHINE_CHECK 41
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/** 43 TPR below threshold. Guest software executed MOV to CR8. */
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#define VMX_EXIT_TPR 43
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/** 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
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#define VMX_EXIT_APIC_ACCESS 44
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/** 46 Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT. */
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#define VMX_EXIT_XDTR_ACCESS 46
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/** 47 Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR. */
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#define VMX_EXIT_TR_ACCESS 47
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/** 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
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#define VMX_EXIT_EPT_VIOLATION 48
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/** 49 EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry. */
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#define VMX_EXIT_EPT_MISCONFIG 49
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/** 50 INVEPT. Guest software attempted to execute INVEPT. */
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#define VMX_EXIT_INVEPT 50
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/** 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
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#define VMX_EXIT_PREEMPTION_TIMER 52
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/** 53 INVVPID. Guest software attempted to execute INVVPID. */
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#define VMX_EXIT_INVVPID 53
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/** 54 WBINVD. Guest software attempted to execute WBINVD. */
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#define VMX_EXIT_WBINVD 54
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/** 55 XSETBV. Guest software attempted to execute XSETBV. */
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#define VMX_EXIT_XSETBV 55
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/** @name VM Instruction Errors
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/** 1 VMCALL executed in VMX root operation. */
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#define VMX_ERROR_VMCALL 1
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/** 2 VMCLEAR with invalid physical address. */
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#define VMX_ERROR_VMCLEAR_INVALID_PHYS_ADDR 2
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/** 3 VMCLEAR with VMXON pointer. */
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#define VMX_ERROR_VMCLEAR_INVALID_VMXON_PTR 3
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/** 4 VMLAUNCH with non-clear VMCS. */
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#define VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS 4
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/** 5 VMRESUME with non-launched VMCS. */
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#define VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS 5
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/** 6 VMRESUME with a corrupted VMCS (indicates corruption of the current VMCS). */
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#define VMX_ERROR_VMRESUME_CORRUPTED_VMCS 6
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/** 7 VM entry with invalid control field(s). */
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#define VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS 7
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/** 8 VM entry with invalid host-state field(s). */
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#define VMX_ERROR_VMENTRY_INVALID_HOST_STATE 8
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/** 9 VMPTRLD with invalid physical address. */
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#define VMX_ERROR_VMPTRLD_INVALID_PHYS_ADDR 9
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/** 10 VMPTRLD with VMXON pointer. */
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#define VMX_ERROR_VMPTRLD_VMXON_PTR 10
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/** 11 VMPTRLD with incorrect VMCS revision identifier. */
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#define VMX_ERROR_VMPTRLD_WRONG_VMCS_REVISION 11
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/** 12 VMREAD/VMWRITE from/to unsupported VMCS component. */
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#define VMX_ERROR_VMREAD_INVALID_COMPONENT 12
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#define VMX_ERROR_VMWRITE_INVALID_COMPONENT VMX_ERROR_VMREAD_INVALID_COMPONENT
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/** 13 VMWRITE to read-only VMCS component. */
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#define VMX_ERROR_VMWRITE_READONLY_COMPONENT 13
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/** 15 VMXON executed in VMX root operation. */
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#define VMX_ERROR_VMXON_IN_VMX_ROOT_OP 15
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/** 16 VM entry with invalid executive-VMCS pointer. */
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#define VMX_ERROR_VMENTRY_INVALID_VMCS_EXEC_PTR 16
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/** 17 VM entry with non-launched executive VMCS. */
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#define VMX_ERROR_VMENTRY_NON_LAUNCHED_EXEC_VMCS 17
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/** 18 VM entry with executive-VMCS pointer not VMXON pointer. */
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#define VMX_ERROR_VMENTRY_EXEC_VMCS_PTR 18
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/** 19 VMCALL with non-clear VMCS. */
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#define VMX_ERROR_VMCALL_NON_CLEAR_VMCS 19
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/** 20 VMCALL with invalid VM-exit control fields. */
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#define VMX_ERROR_VMCALL_INVALID_VMEXIT_FIELDS 20
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/** 22 VMCALL with incorrect MSEG revision identifier. */
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#define VMX_ERROR_VMCALL_INVALID_MSEG_REVISION 22
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/** 23 VMXOFF under dual-monitor treatment of SMIs and SMM. */
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#define VMX_ERROR_VMXOFF_DUAL_MONITOR 23
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/** 24 VMCALL with invalid SMM-monitor features. */
578
#define VMX_ERROR_VMCALL_INVALID_SMM_MONITOR 24
579
/** 25 VM entry with invalid VM-execution control fields in executive VMCS. */
580
#define VMX_ERROR_VMENTRY_INVALID_VM_EXEC_CTRL 25
581
/** 26 VM entry with events blocked by MOV SS. */
582
#define VMX_ERROR_VMENTRY_MOV_SS 26
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/** 26 Invalid operand to INVEPT/INVVPID. */
584
#define VMX_ERROR_INVEPTVPID_INVALID_OPERAND 28
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/** @name VMX MSRs - Basic VMX information.
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/** VMCS revision identifier used by the processor. */
593
#define MSR_IA32_VMX_BASIC_INFO_VMCS_ID(a) (a & 0x7FFFFFFF)
594
/** Size of the VMCS. */
595
#define MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(a) (((a) >> 32) & 0xFFF)
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/** Width of physical address used for the VMCS.
597
* 0 -> limited to the available amount of physical ram
598
* 1 -> within the first 4 GB
600
#define MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(a) (((a) >> 48) & 1)
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/** Whether the processor supports the dual-monitor treatment of system-management interrupts and system-management code. (always 1) */
602
#define MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(a) (((a) >> 49) & 1)
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/** Memory type that must be used for the VMCS. */
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#define MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(a) (((a) >> 50) & 0xF)
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/** @name VMX MSRs - Misc VMX info.
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/** Relationship between the preemption timer and tsc; count down every time bit x of the tsc changes. */
612
#define MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(a) ((a) & 0x1f)
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/** Activity states supported by the implementation. */
614
#define MSR_IA32_VMX_MISC_ACTIVITY_STATES(a) (((a) >> 6) & 0x7)
615
/** Number of CR3 target values supported by the processor. (0-256) */
616
#define MSR_IA32_VMX_MISC_CR3_TARGET(a) (((a) >> 16) & 0x1FF)
617
/** Maximum nr of MSRs in the VMCS. (N+1)*512. */
618
#define MSR_IA32_VMX_MISC_MAX_MSR(a) (((((a) >> 25) & 0x7) + 1) * 512)
619
/** MSEG revision identifier used by the processor. */
620
#define MSR_IA32_VMX_MISC_MSEG_ID(a) ((a) >> 32)
624
/** @name VMX MSRs - VMCS enumeration field info
627
/** Highest field index. */
628
#define MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(a) (((a) >> 1) & 0x1FF)
633
/** @name MSR_IA32_VMX_EPT_CAPS; EPT capabilities MSR
636
#define MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY RT_BIT_64(0)
637
#define MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY RT_BIT_64(1)
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#define MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY RT_BIT_64(2)
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#define MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS RT_BIT_64(3)
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#define MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS RT_BIT_64(4)
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#define MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS RT_BIT_64(5)
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#define MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS RT_BIT_64(6)
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#define MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS RT_BIT_64(7)
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#define MSR_IA32_VMX_EPT_CAPS_EMT_UC RT_BIT_64(8)
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#define MSR_IA32_VMX_EPT_CAPS_EMT_WC RT_BIT_64(9)
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#define MSR_IA32_VMX_EPT_CAPS_EMT_WT RT_BIT_64(12)
647
#define MSR_IA32_VMX_EPT_CAPS_EMT_WP RT_BIT_64(13)
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#define MSR_IA32_VMX_EPT_CAPS_EMT_WB RT_BIT_64(14)
649
#define MSR_IA32_VMX_EPT_CAPS_SP_21_BITS RT_BIT_64(16)
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#define MSR_IA32_VMX_EPT_CAPS_SP_30_BITS RT_BIT_64(17)
651
#define MSR_IA32_VMX_EPT_CAPS_SP_39_BITS RT_BIT_64(18)
652
#define MSR_IA32_VMX_EPT_CAPS_SP_48_BITS RT_BIT_64(19)
653
#define MSR_IA32_VMX_EPT_CAPS_INVEPT RT_BIT_64(20)
654
#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV RT_BIT_64(24)
655
#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT RT_BIT_64(25)
656
#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL RT_BIT_64(26)
657
#define MSR_IA32_VMX_EPT_CAPS_INVVPID RT_BIT_64(32)
658
#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV RT_BIT_64(40)
659
#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT RT_BIT_64(41)
660
#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL RT_BIT_64(42)
661
#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL RT_BIT_64(43)
665
/** @name Extended Page Table Pointer (EPTP)
668
/** Uncachable EPT paging structure memory type. */
669
#define VMX_EPT_MEMTYPE_UC 0
670
/** Write-back EPT paging structure memory type. */
671
#define VMX_EPT_MEMTYPE_WB 6
672
/** Shift value to get the EPT page walk length (bits 5-3) */
673
#define VMX_EPT_PAGE_WALK_LENGTH_SHIFT 3
674
/** Mask value to get the EPT page walk length (bits 5-3) */
675
#define VMX_EPT_PAGE_WALK_LENGTH_MASK 7
676
/** Default EPT page walk length */
677
#define VMX_EPT_PAGE_WALK_LENGTH_DEFAULT 3
681
/** @name VMCS field encoding - 16 bits guest fields
684
#define VMX_VMCS16_GUEST_FIELD_VPID 0x0
685
#define VMX_VMCS16_GUEST_FIELD_ES 0x800
686
#define VMX_VMCS16_GUEST_FIELD_CS 0x802
687
#define VMX_VMCS16_GUEST_FIELD_SS 0x804
688
#define VMX_VMCS16_GUEST_FIELD_DS 0x806
689
#define VMX_VMCS16_GUEST_FIELD_FS 0x808
690
#define VMX_VMCS16_GUEST_FIELD_GS 0x80A
691
#define VMX_VMCS16_GUEST_FIELD_LDTR 0x80C
692
#define VMX_VMCS16_GUEST_FIELD_TR 0x80E
695
/** @name VMCS field encoding - 16 bits host fields
698
#define VMX_VMCS16_HOST_FIELD_ES 0xC00
699
#define VMX_VMCS16_HOST_FIELD_CS 0xC02
700
#define VMX_VMCS16_HOST_FIELD_SS 0xC04
701
#define VMX_VMCS16_HOST_FIELD_DS 0xC06
702
#define VMX_VMCS16_HOST_FIELD_FS 0xC08
703
#define VMX_VMCS16_HOST_FIELD_GS 0xC0A
704
#define VMX_VMCS16_HOST_FIELD_TR 0xC0C
707
/** @name VMCS field encoding - 64 bits host fields
710
#define VMX_VMCS_HOST_FIELD_PAT_FULL 0x2C00
711
#define VMX_VMCS_HOST_FIELD_PAT_HIGH 0x2C01
712
#define VMX_VMCS_HOST_FIELD_EFER_FULL 0x2C02
713
#define VMX_VMCS_HOST_FIELD_EFER_HIGH 0x2C03
714
#define VMX_VMCS_HOST_PERF_GLOBAL_CTRL_FULL 0x2C04 /**< MSR IA32_PERF_GLOBAL_CTRL */
715
#define VMX_VMCS_HOST_PERF_GLOBAL_CTRL_HIGH 0x2C05 /**< MSR IA32_PERF_GLOBAL_CTRL */
719
/** @name VMCS field encoding - 64 Bits control fields
722
#define VMX_VMCS_CTRL_IO_BITMAP_A_FULL 0x2000
723
#define VMX_VMCS_CTRL_IO_BITMAP_A_HIGH 0x2001
724
#define VMX_VMCS_CTRL_IO_BITMAP_B_FULL 0x2002
725
#define VMX_VMCS_CTRL_IO_BITMAP_B_HIGH 0x2003
728
#define VMX_VMCS_CTRL_MSR_BITMAP_FULL 0x2004
729
#define VMX_VMCS_CTRL_MSR_BITMAP_HIGH 0x2005
731
#define VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL 0x2006
732
#define VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH 0x2007
733
#define VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL 0x2008
734
#define VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH 0x2009
736
#define VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL 0x200A
737
#define VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_HIGH 0x200B
739
#define VMX_VMCS_CTRL_EXEC_VMCS_PTR_FULL 0x200C
740
#define VMX_VMCS_CTRL_EXEC_VMCS_PTR_HIGH 0x200D
742
#define VMX_VMCS_CTRL_TSC_OFFSET_FULL 0x2010
743
#define VMX_VMCS_CTRL_TSC_OFFSET_HIGH 0x2011
745
/** Optional (VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW) */
746
#define VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL 0x2012
747
#define VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH 0x2013
749
/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) */
750
#define VMX_VMCS_CTRL_APIC_ACCESSADDR_FULL 0x2014
751
#define VMX_VMCS_CTRL_APIC_ACCESSADDR_HIGH 0x2015
753
/** Extended page table pointer. */
754
#define VMX_VMCS_CTRL_EPTP_FULL 0x201a
755
#define VMX_VMCS_CTRL_EPTP_HIGH 0x201b
757
/** VM-exit phyiscal address. */
758
#define VMX_VMCS_EXIT_PHYS_ADDR_FULL 0x2400
759
#define VMX_VMCS_EXIT_PHYS_ADDR_HIGH 0x2401
763
/** @name VMCS field encoding - 64 Bits guest fields
766
#define VMX_VMCS_GUEST_LINK_PTR_FULL 0x2800
767
#define VMX_VMCS_GUEST_LINK_PTR_HIGH 0x2801
768
#define VMX_VMCS_GUEST_DEBUGCTL_FULL 0x2802 /**< MSR IA32_DEBUGCTL */
769
#define VMX_VMCS_GUEST_DEBUGCTL_HIGH 0x2803 /**< MSR IA32_DEBUGCTL */
770
#define VMX_VMCS_GUEST_PAT_FULL 0x2804
771
#define VMX_VMCS_GUEST_PAT_HIGH 0x2805
772
#define VMX_VMCS_GUEST_EFER_FULL 0x2806
773
#define VMX_VMCS_GUEST_EFER_HIGH 0x2807
774
#define VMX_VMCS_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808 /**< MSR IA32_PERF_GLOBAL_CTRL */
775
#define VMX_VMCS_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809 /**< MSR IA32_PERF_GLOBAL_CTRL */
776
#define VMX_VMCS_GUEST_PDPTR0_FULL 0x280A
777
#define VMX_VMCS_GUEST_PDPTR0_HIGH 0x280B
778
#define VMX_VMCS_GUEST_PDPTR1_FULL 0x280C
779
#define VMX_VMCS_GUEST_PDPTR1_HIGH 0x280D
780
#define VMX_VMCS_GUEST_PDPTR2_FULL 0x280E
781
#define VMX_VMCS_GUEST_PDPTR2_HIGH 0x280F
782
#define VMX_VMCS_GUEST_PDPTR3_FULL 0x2810
783
#define VMX_VMCS_GUEST_PDPTR3_HIGH 0x2811
787
/** @name VMCS field encoding - 32 Bits control fields
790
#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS 0x4000
791
#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS 0x4002
792
#define VMX_VMCS_CTRL_EXCEPTION_BITMAP 0x4004
793
#define VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK 0x4006
794
#define VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
795
#define VMX_VMCS_CTRL_CR3_TARGET_COUNT 0x400A
796
#define VMX_VMCS_CTRL_EXIT_CONTROLS 0x400C
797
#define VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT 0x400E
798
#define VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
799
#define VMX_VMCS_CTRL_ENTRY_CONTROLS 0x4012
800
#define VMX_VMCS_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
801
#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO 0x4016
802
#define VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
803
#define VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH 0x401A
804
/** This field exists only on processors that support the 1-setting of the �use TPR shadow� VM-execution control. */
805
#define VMX_VMCS_CTRL_TPR_THRESHOLD 0x401C
806
/** This field exists only on processors that support the 1-setting of the �activate secondary controls� VM-execution control. */
807
#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2 0x401E
811
/** @name VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
814
/** External interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
815
#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT RT_BIT(0)
816
/** Non-maskable interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
817
#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT RT_BIT(3)
819
#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI RT_BIT(5)
820
/** Activate VMX preemption timer. */
821
#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER RT_BIT(6)
822
/* All other bits are reserved and must be set according to MSR IA32_VMX_PROCBASED_CTLS. */
825
/** @name VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
828
/** VM Exit as soon as RFLAGS.IF=1 and no blocking is active. */
829
#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT RT_BIT(2)
830
/** Use timestamp counter offset. */
831
#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET RT_BIT(3)
832
/** VM Exit when executing the HLT instruction. */
833
#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT RT_BIT(7)
834
/** VM Exit when executing the INVLPG instruction. */
835
#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT RT_BIT(9)
836
/** VM Exit when executing the MWAIT instruction. */
837
#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT RT_BIT(10)
838
/** VM Exit when executing the RDPMC instruction. */
839
#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT RT_BIT(11)
840
/** VM Exit when executing the RDTSC instruction. */
841
#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT RT_BIT(12)
842
/** VM Exit when executing the MOV to CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
843
#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT RT_BIT(15)
844
/** VM Exit when executing the MOV from CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
845
#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT RT_BIT(16)
846
/** VM Exit on CR8 loads. */
847
#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT RT_BIT(19)
848
/** VM Exit on CR8 stores. */
849
#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT RT_BIT(20)
850
/** Use TPR shadow. */
851
#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW RT_BIT(21)
852
/** VM Exit when virtual nmi blocking is disabled. */
853
#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT RT_BIT(22)
854
/** VM Exit when executing a MOV DRx instruction. */
855
#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT RT_BIT(23)
856
/** VM Exit when executing IO instructions. */
857
#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT RT_BIT(24)
858
/** Use IO bitmaps. */
859
#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS RT_BIT(25)
860
/** Monitor trap flag. */
861
#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG RT_BIT(27)
862
/** Use MSR bitmaps. */
863
#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS RT_BIT(28)
864
/** VM Exit when executing the MONITOR instruction. */
865
#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT RT_BIT(29)
866
/** VM Exit when executing the PAUSE instruction. */
867
#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT RT_BIT(30)
868
/** Determines whether the secondary processor based VM-execution controls are used. */
869
#define VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL RT_BIT(31)
872
/** @name VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
875
/** Virtualize APIC access. */
876
#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC RT_BIT(0)
877
/** EPT supported/enabled. */
878
#define VMX_VMCS_CTRL_PROC_EXEC2_EPT RT_BIT(1)
879
/** Descriptor table instructions cause VM-exits. */
880
#define VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT RT_BIT(2)
881
/** RDTSCP causes a VM-exit. */
882
#define VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT RT_BIT(3)
883
/** Virtualize x2APIC mode. */
884
#define VMX_VMCS_CTRL_PROC_EXEC2_X2APIC RT_BIT(4)
885
/** VPID supported/enabled. */
886
#define VMX_VMCS_CTRL_PROC_EXEC2_VPID RT_BIT(5)
887
/** VM Exit when executing the WBINVD instruction. */
888
#define VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT RT_BIT(6)
889
/** Unrestricted guest execution. */
890
#define VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE RT_BIT(7)
891
/** A specified nr of pause loops cause a VM-exit. */
892
#define VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT RT_BIT(10)
896
/** @name VMX_VMCS_CTRL_ENTRY_CONTROLS
899
/** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
900
#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG RT_BIT(2)
901
/** 64 bits guest mode. Must be 0 for CPUs that don't support AMD64. */
902
#define VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE RT_BIT(9)
903
/** In SMM mode after VM-entry. */
904
#define VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM RT_BIT(10)
905
/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
906
#define VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON RT_BIT(11)
907
/** This control determines whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM entry. */
908
#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR RT_BIT(13)
909
/** This control determines whether the guest IA32_PAT MSR is loaded on VM entry. */
910
#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR RT_BIT(14)
911
/** This control determines whether the guest IA32_EFER MSR is loaded on VM entry. */
912
#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR RT_BIT(15)
916
/** @name VMX_VMCS_CTRL_EXIT_CONTROLS
919
/** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
920
#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG RT_BIT(2)
921
/** Return to long mode after a VM-exit. */
922
#define VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 RT_BIT(9)
923
/** This control determines whether the IA32_PERF_GLOBAL_CTRL MSR is loaded on VM exit. */
924
#define VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_PERF_MSR RT_BIT(12)
925
/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
926
#define VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ RT_BIT(15)
927
/** This control determines whether the guest IA32_PAT MSR is saved on VM exit. */
928
#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR RT_BIT(18)
929
/** This control determines whether the host IA32_PAT MSR is loaded on VM exit. */
930
#define VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR RT_BIT(19)
931
/** This control determines whether the guest IA32_EFER MSR is saved on VM exit. */
932
#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR RT_BIT(20)
933
/** This control determines whether the host IA32_EFER MSR is loaded on VM exit. */
934
#define VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR RT_BIT(21)
935
/** This control determines whether the value of the VMX preemption timer is saved on VM exit. */
936
#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER RT_BIT(22)
939
/** @name VMCS field encoding - 32 Bits read-only fields
942
#define VMX_VMCS32_RO_VM_INSTR_ERROR 0x4400
943
#define VMX_VMCS32_RO_EXIT_REASON 0x4402
944
#define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO 0x4404
945
#define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE 0x4406
946
#define VMX_VMCS32_RO_IDT_INFO 0x4408
947
#define VMX_VMCS32_RO_IDT_ERRCODE 0x440A
948
#define VMX_VMCS32_RO_EXIT_INSTR_LENGTH 0x440C
949
#define VMX_VMCS32_RO_EXIT_INSTR_INFO 0x440E
952
/** @name VMX_VMCS_RO_EXIT_INTERRUPTION_INFO
955
#define VMX_EXIT_INTERRUPTION_INFO_VECTOR(a) (a & 0xff)
956
#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT 8
957
#define VMX_EXIT_INTERRUPTION_INFO_TYPE(a) ((a >> VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
958
#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID RT_BIT(11)
959
#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(a) (a & VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID)
960
#define VMX_EXIT_INTERRUPTION_INFO_NMI_UNBLOCK(a) (a & RT_BIT(12))
961
#define VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT 31
962
#define VMX_EXIT_INTERRUPTION_INFO_VALID(a) (a & RT_BIT(31))
963
/** Construct an irq event injection value from the exit interruption info value (same except that bit 12 is reserved). */
964
#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(a) (a & ~RT_BIT(12))
967
/** @name VMX_VMCS_RO_EXIT_INTERRUPTION_INFO_TYPE
970
#define VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT 0
971
#define VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI 2
972
#define VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT 3
973
#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW 4 /**< int xx */
974
#define VMX_EXIT_INTERRUPTION_INFO_TYPE_DBEXCPT 5 /**< Why are we getting this one?? */
975
#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT 6
979
/** @name VMCS field encoding - 32 Bits guest state fields
982
#define VMX_VMCS32_GUEST_ES_LIMIT 0x4800
983
#define VMX_VMCS32_GUEST_CS_LIMIT 0x4802
984
#define VMX_VMCS32_GUEST_SS_LIMIT 0x4804
985
#define VMX_VMCS32_GUEST_DS_LIMIT 0x4806
986
#define VMX_VMCS32_GUEST_FS_LIMIT 0x4808
987
#define VMX_VMCS32_GUEST_GS_LIMIT 0x480A
988
#define VMX_VMCS32_GUEST_LDTR_LIMIT 0x480C
989
#define VMX_VMCS32_GUEST_TR_LIMIT 0x480E
990
#define VMX_VMCS32_GUEST_GDTR_LIMIT 0x4810
991
#define VMX_VMCS32_GUEST_IDTR_LIMIT 0x4812
992
#define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS 0x4814
993
#define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS 0x4816
994
#define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS 0x4818
995
#define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS 0x481A
996
#define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS 0x481C
997
#define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS 0x481E
998
#define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS 0x4820
999
#define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS 0x4822
1000
#define VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE 0x4824
1001
#define VMX_VMCS32_GUEST_ACTIVITY_STATE 0x4826
1002
#define VMX_VMCS32_GUEST_SYSENTER_CS 0x482A /**< MSR IA32_SYSENTER_CS */
1003
#define VMX_VMCS32_GUEST_PREEMPTION_TIMER_VALUE 0x482E
1007
/** @name VMX_VMCS_GUEST_ACTIVITY_STATE
1010
/** The logical processor is active. */
1011
#define VMX_CMS_GUEST_ACTIVITY_ACTIVE 0x0
1012
/** The logical processor is inactive, because executed a HLT instruction. */
1013
#define VMX_CMS_GUEST_ACTIVITY_HLT 0x1
1014
/** The logical processor is inactive, because of a triple fault or other serious error. */
1015
#define VMX_CMS_GUEST_ACTIVITY_SHUTDOWN 0x2
1016
/** The logical processor is inactive, because it's waiting for a startup-IPI */
1017
#define VMX_CMS_GUEST_ACTIVITY_SIPI_WAIT 0x3
1021
/** @name VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE
1024
#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI RT_BIT(0)
1025
#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS RT_BIT(1)
1026
#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI RT_BIT(2)
1027
#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI RT_BIT(3)
1031
/** @name VMCS field encoding - 32 Bits host state fields
1034
#define VMX_VMCS32_HOST_SYSENTER_CS 0x4C00
1037
/** @name Natural width control fields
1040
#define VMX_VMCS_CTRL_CR0_MASK 0x6000
1041
#define VMX_VMCS_CTRL_CR4_MASK 0x6002
1042
#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
1043
#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
1044
#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
1045
#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600A
1046
#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600C
1047
#define VMX_VMCS_CTRL_CR3_TARGET_VAL31 0x600E
1051
/** @name Natural width read-only data fields
1054
#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
1055
#define VMX_VMCS_RO_IO_RCX 0x6402
1056
#define VMX_VMCS_RO_IO_RSX 0x6404
1057
#define VMX_VMCS_RO_IO_RDI 0x6406
1058
#define VMX_VMCS_RO_IO_RIP 0x6408
1059
#define VMX_VMCS_EXIT_GUEST_LINEAR_ADDR 0x640A
1063
/** @name VMX_VMCS_RO_EXIT_QUALIFICATION
1066
/** 0-2: Debug register number */
1067
#define VMX_EXIT_QUALIFICATION_DRX_REGISTER(a) (a & 7)
1068
/** 3: Reserved; cleared to 0. */
1069
#define VMX_EXIT_QUALIFICATION_DRX_RES1(a) ((a >> 3) & 1)
1070
/** 4: Direction of move (0 = write, 1 = read) */
1071
#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION(a) ((a >> 4) & 1)
1072
/** 5-7: Reserved; cleared to 0. */
1073
#define VMX_EXIT_QUALIFICATION_DRX_RES2(a) ((a >> 5) & 7)
1074
/** 8-11: General purpose register number. */
1075
#define VMX_EXIT_QUALIFICATION_DRX_GENREG(a) ((a >> 8) & 0xF)
1076
/** Rest: reserved. */
1079
/** @name VMX_EXIT_QUALIFICATION_DRX_DIRECTION values
1082
#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE 0
1083
#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_READ 1
1088
/** @name CRx accesses
1091
/** 0-3: Control register number (0 for CLTS & LMSW) */
1092
#define VMX_EXIT_QUALIFICATION_CRX_REGISTER(a) (a & 0xF)
1093
/** 4-5: Access type. */
1094
#define VMX_EXIT_QUALIFICATION_CRX_ACCESS(a) ((a >> 4) & 3)
1095
/** 6: LMSW operand type */
1096
#define VMX_EXIT_QUALIFICATION_CRX_LMSW_OP(a) ((a >> 6) & 1)
1097
/** 7: Reserved; cleared to 0. */
1098
#define VMX_EXIT_QUALIFICATION_CRX_RES1(a) ((a >> 7) & 1)
1099
/** 8-11: General purpose register number (0 for CLTS & LMSW). */
1100
#define VMX_EXIT_QUALIFICATION_CRX_GENREG(a) ((a >> 8) & 0xF)
1101
/** 12-15: Reserved; cleared to 0. */
1102
#define VMX_EXIT_QUALIFICATION_CRX_RES2(a) ((a >> 12) & 0xF)
1103
/** 16-31: LMSW source data (else 0). */
1104
#define VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(a) ((a >> 16) & 0xFFFF)
1105
/** Rest: reserved. */
1108
/** @name VMX_EXIT_QUALIFICATION_CRX_ACCESS
1111
#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE 0
1112
#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ 1
1113
#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS 2
1114
#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW 3
1117
/** @name VMX_EXIT_QUALIFICATION_TASK_SWITCH
1120
#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_SELECTOR(a) (a & 0xffff)
1121
#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE(a) ((a >> 30)& 0x3)
1122
/** Task switch caused by a call instruction. */
1123
#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_CALL 0
1124
/** Task switch caused by an iret instruction. */
1125
#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IRET 1
1126
/** Task switch caused by a jmp instruction. */
1127
#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_JMP 2
1128
/** Task switch caused by an interrupt gate. */
1129
#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IDT 3
1134
/** @name VMX_EXIT_EPT_VIOLATION
1137
/** Set if the violation was caused by a data read. */
1138
#define VMX_EXIT_QUALIFICATION_EPT_DATA_READ RT_BIT(0)
1139
/** Set if the violation was caused by a data write. */
1140
#define VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE RT_BIT(1)
1141
/** Set if the violation was caused by an insruction fetch. */
1142
#define VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH RT_BIT(2)
1143
/** AND of the present bit of all EPT structures. */
1144
#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT RT_BIT(3)
1145
/** AND of the write bit of all EPT structures. */
1146
#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_WRITE RT_BIT(4)
1147
/** AND of the execute bit of all EPT structures. */
1148
#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_EXECUTE RT_BIT(5)
1149
/** Set if the guest linear address field contains the faulting address. */
1150
#define VMX_EXIT_QUALIFICATION_EPT_GUEST_ADDR_VALID RT_BIT(7)
1151
/** If bit 7 is one: (reserved otherwise)
1152
* 1 - violation due to physical address access.
1153
* 0 - violation caused by page walk or access/dirty bit updates
1155
#define VMX_EXIT_QUALIFICATION_EPT_TRANSLATED_ACCESS RT_BIT(8)
1159
/** @name VMX_EXIT_PORT_IO
1162
/** 0-2: IO operation width. */
1163
#define VMX_EXIT_QUALIFICATION_IO_WIDTH(a) (a & 7)
1164
/** 3: IO operation direction. */
1165
#define VMX_EXIT_QUALIFICATION_IO_DIRECTION(a) ((a >> 3) & 1)
1166
/** 4: String IO operation. */
1167
#define VMX_EXIT_QUALIFICATION_IO_STRING(a) ((a >> 4) & 1)
1168
/** 5: Repeated IO operation. */
1169
#define VMX_EXIT_QUALIFICATION_IO_REP(a) ((a >> 5) & 1)
1170
/** 6: Operand encoding. */
1171
#define VMX_EXIT_QUALIFICATION_IO_ENCODING(a) ((a >> 6) & 1)
1172
/** 16-31: IO Port (0-0xffff). */
1173
#define VMX_EXIT_QUALIFICATION_IO_PORT(a) ((a >> 16) & 0xffff)
1174
/* Rest reserved. */
1177
/** @name VMX_EXIT_QUALIFICATION_IO_DIRECTION
1180
#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT 0
1181
#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_IN 1
1185
/** @name VMX_EXIT_QUALIFICATION_IO_ENCODING
1188
#define VMX_EXIT_QUALIFICATION_IO_ENCODING_DX 0
1189
#define VMX_EXIT_QUALIFICATION_IO_ENCODING_IMM 1
1192
/** @name VMX_EXIT_APIC_ACCESS
1195
/** 0-11: If the APIC-access VM exit is due to a linear access, the offset of access within the APIC page. */
1196
#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(a) (a & 0xfff)
1197
/** 12-15: Access type. */
1198
#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE(a) ((a >> 12) & 0xf)
1199
/* Rest reserved. */
1203
/** @name VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE; access types
1206
/** Linear read access. */
1207
#define VMX_APIC_ACCESS_TYPE_LINEAR_READ 0
1208
/** Linear write access. */
1209
#define VMX_APIC_ACCESS_TYPE_LINEAR_WRITE 1
1210
/** Linear instruction fetch access. */
1211
#define VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH 2
1212
/** Linear read/write access during event delivery. */
1213
#define VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY 3
1214
/** Physical read/write access during event delivery. */
1215
#define VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY 10
1216
/** Physical access for an instruction fetch or during instruction execution. */
1217
#define VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR 15
1222
/** @name VMCS field encoding - Natural width guest state fields
1225
#define VMX_VMCS64_GUEST_CR0 0x6800
1226
#define VMX_VMCS64_GUEST_CR3 0x6802
1227
#define VMX_VMCS64_GUEST_CR4 0x6804
1228
#define VMX_VMCS64_GUEST_ES_BASE 0x6806
1229
#define VMX_VMCS64_GUEST_CS_BASE 0x6808
1230
#define VMX_VMCS64_GUEST_SS_BASE 0x680A
1231
#define VMX_VMCS64_GUEST_DS_BASE 0x680C
1232
#define VMX_VMCS64_GUEST_FS_BASE 0x680E
1233
#define VMX_VMCS64_GUEST_GS_BASE 0x6810
1234
#define VMX_VMCS64_GUEST_LDTR_BASE 0x6812
1235
#define VMX_VMCS64_GUEST_TR_BASE 0x6814
1236
#define VMX_VMCS64_GUEST_GDTR_BASE 0x6816
1237
#define VMX_VMCS64_GUEST_IDTR_BASE 0x6818
1238
#define VMX_VMCS64_GUEST_DR7 0x681A
1239
#define VMX_VMCS64_GUEST_RSP 0x681C
1240
#define VMX_VMCS64_GUEST_RIP 0x681E
1241
#define VMX_VMCS_GUEST_RFLAGS 0x6820
1242
#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS 0x6822
1243
#define VMX_VMCS64_GUEST_SYSENTER_ESP 0x6824 /**< MSR IA32_SYSENTER_ESP */
1244
#define VMX_VMCS64_GUEST_SYSENTER_EIP 0x6826 /**< MSR IA32_SYSENTER_EIP */
1248
/** @name VMX_VMCS_GUEST_DEBUG_EXCEPTIONS
1251
/** Hardware breakpoint 0 was met. */
1252
#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B0 RT_BIT(0)
1253
/** Hardware breakpoint 1 was met. */
1254
#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B1 RT_BIT(1)
1255
/** Hardware breakpoint 2 was met. */
1256
#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B2 RT_BIT(2)
1257
/** Hardware breakpoint 3 was met. */
1258
#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B3 RT_BIT(3)
1259
/** At least one data or IO breakpoint was hit. */
1260
#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BREAKPOINT_ENABLED RT_BIT(12)
1261
/** A debug exception would have been triggered by single-step execution mode. */
1262
#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BS RT_BIT(14)
1263
/** Bits 4-11, 13 and 15-63 are reserved. */
1267
/** @name VMCS field encoding - Natural width host state fields
1270
#define VMX_VMCS_HOST_CR0 0x6C00
1271
#define VMX_VMCS_HOST_CR3 0x6C02
1272
#define VMX_VMCS_HOST_CR4 0x6C04
1273
#define VMX_VMCS_HOST_FS_BASE 0x6C06
1274
#define VMX_VMCS_HOST_GS_BASE 0x6C08
1275
#define VMX_VMCS_HOST_TR_BASE 0x6C0A
1276
#define VMX_VMCS_HOST_GDTR_BASE 0x6C0C
1277
#define VMX_VMCS_HOST_IDTR_BASE 0x6C0E
1278
#define VMX_VMCS_HOST_SYSENTER_ESP 0x6C10
1279
#define VMX_VMCS_HOST_SYSENTER_EIP 0x6C12
1280
#define VMX_VMCS_HOST_RSP 0x6C14
1281
#define VMX_VMCS_HOST_RIP 0x6C16
1287
#if RT_INLINE_ASM_GNU_STYLE
1288
# define __STR(x) #x
1289
# define STR(x) __STR(x)
1293
/** @defgroup grp_vmx_asm vmx assembly helpers
1301
* @returns VBox status code
1302
* @param pVMXOn Physical address of VMXON structure
1304
#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64 || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1305
DECLASM(int) VMXEnable(RTHCPHYS pVMXOn);
1307
DECLINLINE(int) VMXEnable(RTHCPHYS pVMXOn)
1309
int rc = VINF_SUCCESS;
1310
# if RT_INLINE_ASM_GNU_STYLE
1311
__asm__ __volatile__ (
1314
".byte 0xF3, 0x0F, 0xC7, 0x34, 0x24 # VMXON [esp] \n\t"
1317
"movl $"STR(VERR_VMX_INVALID_VMXON_PTR)", %0 \n\t"
1320
"movl $"STR(VERR_VMX_GENERIC)", %0 \n\t"
1322
"add $8, %%esp \n\t"
1325
"ir"((uint32_t)pVMXOn), /* don't allow direct memory reference here, */
1326
"ir"((uint32_t)(pVMXOn >> 32)) /* this would not work with -fomit-frame-pointer */
1332
push dword ptr [pVMXOn+4]
1333
push dword ptr [pVMXOn]
1338
_emit 0x24 /* VMXON [esp] */
1340
mov dword ptr [rc], VERR_VMX_INVALID_VMXON_PTR
1345
mov dword ptr [rc], VERR_VMX_GENERIC
1358
#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64 || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1359
DECLASM(void) VMXDisable(void);
1361
DECLINLINE(void) VMXDisable(void)
1363
# if RT_INLINE_ASM_GNU_STYLE
1364
__asm__ __volatile__ (
1365
".byte 0x0F, 0x01, 0xC4 # VMXOFF \n\t"
1372
_emit 0xC4 /* VMXOFF */
1382
* @returns VBox status code
1383
* @param pVMCS Physical address of VM control structure
1385
#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64 || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1386
DECLASM(int) VMXClearVMCS(RTHCPHYS pVMCS);
1388
DECLINLINE(int) VMXClearVMCS(RTHCPHYS pVMCS)
1390
int rc = VINF_SUCCESS;
1391
# if RT_INLINE_ASM_GNU_STYLE
1392
__asm__ __volatile__ (
1395
".byte 0x66, 0x0F, 0xC7, 0x34, 0x24 # VMCLEAR [esp] \n\t"
1397
"movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1399
"add $8, %%esp \n\t"
1402
"ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
1403
"ir"((uint32_t)(pVMCS >> 32)) /* this would not work with -fomit-frame-pointer */
1409
push dword ptr [pVMCS+4]
1410
push dword ptr [pVMCS]
1415
_emit 0x24 /* VMCLEAR [esp] */
1417
mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1430
* @returns VBox status code
1431
* @param pVMCS Physical address of VMCS structure
1433
#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64 || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1434
DECLASM(int) VMXActivateVMCS(RTHCPHYS pVMCS);
1436
DECLINLINE(int) VMXActivateVMCS(RTHCPHYS pVMCS)
1438
int rc = VINF_SUCCESS;
1439
# if RT_INLINE_ASM_GNU_STYLE
1440
__asm__ __volatile__ (
1443
".byte 0x0F, 0xC7, 0x34, 0x24 # VMPTRLD [esp] \n\t"
1445
"movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1447
"add $8, %%esp \n\t"
1450
"ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
1451
"ir"((uint32_t)(pVMCS >> 32)) /* this will not work with -fomit-frame-pointer */
1456
push dword ptr [pVMCS+4]
1457
push dword ptr [pVMCS]
1461
_emit 0x24 /* VMPTRLD [esp] */
1463
mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1476
* @returns VBox status code
1477
* @param pVMCS Address that will receive the current pointer
1479
DECLASM(int) VMXGetActivateVMCS(RTHCPHYS *pVMCS);
1484
* @returns VBox status code
1485
* @param idxField VMCS index
1486
* @param u32Val 32 bits value
1488
#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64 || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1489
DECLASM(int) VMXWriteVMCS32(uint32_t idxField, uint32_t u32Val);
1491
DECLINLINE(int) VMXWriteVMCS32(uint32_t idxField, uint32_t u32Val)
1493
int rc = VINF_SUCCESS;
1494
# if RT_INLINE_ASM_GNU_STYLE
1495
__asm__ __volatile__ (
1496
".byte 0x0F, 0x79, 0xC2 # VMWRITE eax, edx \n\t"
1499
"movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1502
"movl $"STR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
1512
push dword ptr [u32Val]
1517
_emit 0x24 /* VMWRITE eax, [esp] */
1519
mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1524
mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
1536
* @returns VBox status code
1537
* @param idxField VMCS index
1538
* @param u64Val 16, 32 or 64 bits value
1540
#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1541
DECLASM(int) VMXWriteVMCS64(uint32_t idxField, uint64_t u64Val);
1543
VMMR0DECL(int) VMXWriteVMCS64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val);
1545
#define VMXWriteVMCS64(idxField, u64Val) VMXWriteVMCS64Ex(pVCpu, idxField, u64Val)
1548
#if HC_ARCH_BITS == 64
1549
#define VMXWriteVMCS VMXWriteVMCS64
1551
#define VMXWriteVMCS VMXWriteVMCS32
1552
#endif /* HC_ARCH_BITS == 64 */
1556
* Invalidate a page using invept
1557
* @returns VBox status code
1558
* @param enmFlush Type of flush
1559
* @param pDescriptor Descriptor
1561
DECLASM(int) VMXR0InvEPT(VMX_FLUSH enmFlush, uint64_t *pDescriptor);
1564
* Invalidate a page using invvpid
1565
* @returns VBox status code
1566
* @param enmFlush Type of flush
1567
* @param pDescriptor Descriptor
1569
DECLASM(int) VMXR0InvVPID(VMX_FLUSH enmFlush, uint64_t *pDescriptor);
1574
* @returns VBox status code
1575
* @param idxField VMCS index
1576
* @param pData Ptr to store VM field value
1578
#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64 || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1579
DECLASM(int) VMXReadVMCS32(uint32_t idxField, uint32_t *pData);
1581
DECLINLINE(int) VMXReadVMCS32(uint32_t idxField, uint32_t *pData)
1583
int rc = VINF_SUCCESS;
1584
# if RT_INLINE_ASM_GNU_STYLE
1585
__asm__ __volatile__ (
1586
"movl $"STR(VINF_SUCCESS)", %0 \n\t"
1587
".byte 0x0F, 0x78, 0xc2 # VMREAD eax, edx \n\t"
1590
"movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1593
"movl $"STR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
1604
mov dword ptr [esp], 0
1609
_emit 0x24 /* VMREAD eax, [esp] */
1613
mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1618
mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
1629
* @returns VBox status code
1630
* @param idxField VMCS index
1631
* @param pData Ptr to store VM field value
1633
#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1634
DECLASM(int) VMXReadVMCS64(uint32_t idxField, uint64_t *pData);
1636
DECLINLINE(int) VMXReadVMCS64(uint32_t idxField, uint64_t *pData)
1640
uint32_t val_hi, val;
1641
rc = VMXReadVMCS32(idxField, &val);
1642
rc |= VMXReadVMCS32(idxField + 1, &val_hi);
1644
*pData = RT_MAKE_U64(val, val_hi);
1649
#if HC_ARCH_BITS == 64
1650
# define VMXReadVMCS VMXReadVMCS64
1652
# define VMXReadVMCS VMXReadVMCS32
1653
#endif /* HC_ARCH_BITS == 64 */
1656
* Gets the last instruction error value from the current VMCS
1658
* @returns error value
1660
DECLINLINE(uint32_t) VMXGetLastError(void)
1662
#if HC_ARCH_BITS == 64
1663
uint64_t uLastError = 0;
1664
int rc = VMXReadVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
1666
return (uint32_t)uLastError;
1668
#else /* 32-bit host: */
1669
uint32_t uLastError = 0;
1670
int rc = VMXReadVMCS32(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
1677
VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt);
1678
VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys);
1679
#endif /* IN_RING0 */
added
removed
include/VBox/vmm/hwacc_vmx.h
