2
* DO NOT EDIT THIS FILE
3
* This file is under version control at
4
* svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
5
* and can be replaced with that version at any time
6
* DO NOT EDIT THIS FILE
8
* Copyright 2004-2011 Analog Devices Inc.
9
* Licensed under the Clear BSD license.
12
/* This file should be up to date with:
15
#if __SILICON_REVISION__ < 0
16
# error will not work on BF506 silicon version
19
#ifndef _MACH_ANOMALY_H_
20
#define _MACH_ANOMALY_H_
22
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
23
#define ANOMALY_05000074 (1)
24
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
25
#define ANOMALY_05000119 (1)
26
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
27
#define ANOMALY_05000122 (1)
28
/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
29
#define ANOMALY_05000245 (1)
30
/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
31
#define ANOMALY_05000254 (1)
32
/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
33
#define ANOMALY_05000265 (1)
34
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
35
#define ANOMALY_05000310 (1)
36
/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
37
#define ANOMALY_05000366 (1)
38
/* Speculative Fetches Can Cause Undesired External FIFO Operations */
39
#define ANOMALY_05000416 (1)
40
/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
41
#define ANOMALY_05000426 (1)
42
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
43
#define ANOMALY_05000443 (1)
44
/* UART IrDA Receiver Fails on Extended Bit Pulses */
45
#define ANOMALY_05000447 (1)
46
/* False Hardware Error when RETI Points to Invalid Memory */
47
#define ANOMALY_05000461 (1)
48
/* PLL Latches Incorrect Settings During Reset */
49
#define ANOMALY_05000469 (1)
50
/* Incorrect Default MSEL Value in PLL_CTL */
51
#define ANOMALY_05000472 (1)
52
/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
53
#define ANOMALY_05000473 (1)
54
/* TESTSET Instruction Cannot Be Interrupted */
55
#define ANOMALY_05000477 (1)
56
/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
57
#define ANOMALY_05000481 (1)
58
/* IFLUSH sucks at life */
59
#define ANOMALY_05000491 (1)
60
/* Tempopary anomaly ID for data loss in MMR read operation if interrupted */
61
#define ANOMALY_05001001 (__SILICON_REVISION__ < 1)
63
/* Anomalies that don't exist on this proc */
64
#define ANOMALY_05000099 (0)
65
#define ANOMALY_05000120 (0)
66
#define ANOMALY_05000125 (0)
67
#define ANOMALY_05000149 (0)
68
#define ANOMALY_05000158 (0)
69
#define ANOMALY_05000171 (0)
70
#define ANOMALY_05000179 (0)
71
#define ANOMALY_05000182 (0)
72
#define ANOMALY_05000183 (0)
73
#define ANOMALY_05000189 (0)
74
#define ANOMALY_05000198 (0)
75
#define ANOMALY_05000202 (0)
76
#define ANOMALY_05000215 (0)
77
#define ANOMALY_05000219 (0)
78
#define ANOMALY_05000220 (0)
79
#define ANOMALY_05000227 (0)
80
#define ANOMALY_05000230 (0)
81
#define ANOMALY_05000231 (0)
82
#define ANOMALY_05000233 (0)
83
#define ANOMALY_05000234 (0)
84
#define ANOMALY_05000242 (0)
85
#define ANOMALY_05000244 (0)
86
#define ANOMALY_05000248 (0)
87
#define ANOMALY_05000250 (0)
88
#define ANOMALY_05000257 (0)
89
#define ANOMALY_05000261 (0)
90
#define ANOMALY_05000263 (0)
91
#define ANOMALY_05000266 (0)
92
#define ANOMALY_05000273 (0)
93
#define ANOMALY_05000274 (0)
94
#define ANOMALY_05000278 (0)
95
#define ANOMALY_05000281 (0)
96
#define ANOMALY_05000283 (0)
97
#define ANOMALY_05000285 (0)
98
#define ANOMALY_05000287 (0)
99
#define ANOMALY_05000301 (0)
100
#define ANOMALY_05000305 (0)
101
#define ANOMALY_05000307 (0)
102
#define ANOMALY_05000311 (0)
103
#define ANOMALY_05000312 (0)
104
#define ANOMALY_05000315 (0)
105
#define ANOMALY_05000323 (0)
106
#define ANOMALY_05000353 (1)
107
#define ANOMALY_05000357 (0)
108
#define ANOMALY_05000362 (1)
109
#define ANOMALY_05000363 (0)
110
#define ANOMALY_05000364 (0)
111
#define ANOMALY_05000371 (0)
112
#define ANOMALY_05000380 (0)
113
#define ANOMALY_05000386 (0)
114
#define ANOMALY_05000389 (0)
115
#define ANOMALY_05000400 (0)
116
#define ANOMALY_05000402 (0)
117
#define ANOMALY_05000412 (0)
118
#define ANOMALY_05000432 (0)
119
#define ANOMALY_05000440 (0)
120
#define ANOMALY_05000448 (0)
121
#define ANOMALY_05000456 (0)
122
#define ANOMALY_05000450 (0)
123
#define ANOMALY_05000465 (0)
124
#define ANOMALY_05000467 (0)
125
#define ANOMALY_05000474 (0)
126
#define ANOMALY_05000475 (0)
127
#define ANOMALY_05000480 (0)
128
#define ANOMALY_05000485 (0)