176
177
static int lnw_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
178
179
struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
179
return lnw->irq_base + offset;
180
return irq_create_mapping(lnw->domain, offset);
182
183
static int lnw_irq_type(struct irq_data *d, unsigned type)
184
185
struct lnw_gpio *lnw = irq_data_get_irq_chip_data(d);
185
u32 gpio = d->irq - lnw->irq_base;
186
u32 gpio = irqd_to_hwirq(d);
186
187
unsigned long flags;
188
189
void __iomem *grer = gpio_reg(&lnw->chip, gpio, GRER);
249
250
/* check GPIO controller to check which pin triggered the interrupt */
250
251
for (base = 0; base < lnw->chip.ngpio; base += 32) {
251
252
gedr = gpio_reg(&lnw->chip, base, GEDR);
252
pending = readl(gedr);
253
while ((pending = readl(gedr))) {
254
254
gpio = __ffs(pending);
255
255
mask = BIT(gpio);
257
256
/* Clear before handling so we can't lose an edge */
258
257
writel(mask, gedr);
259
generic_handle_irq(lnw->irq_base + base + gpio);
258
generic_handle_irq(irq_find_mapping(lnw->domain,
263
263
chip->irq_eoi(data);
266
static void lnw_irq_init_hw(struct lnw_gpio *lnw)
271
for (base = 0; base < lnw->chip.ngpio; base += 32) {
272
/* Clear the rising-edge detect register */
273
reg = gpio_reg(&lnw->chip, base, GRER);
275
/* Clear the falling-edge detect register */
276
reg = gpio_reg(&lnw->chip, base, GFER);
278
/* Clear the edge detect status register */
279
reg = gpio_reg(&lnw->chip, base, GEDR);
284
static int lnw_gpio_irq_map(struct irq_domain *d, unsigned int virq,
287
struct lnw_gpio *lnw = d->host_data;
289
irq_set_chip_and_handler_name(virq, &lnw_irqchip, handle_simple_irq,
291
irq_set_chip_data(virq, lnw);
292
irq_set_irq_type(virq, IRQ_TYPE_NONE);
297
static const struct irq_domain_ops lnw_gpio_irq_ops = {
298
.map = lnw_gpio_irq_map,
299
.xlate = irq_domain_xlate_twocell,
267
303
static int lnw_gpio_runtime_resume(struct device *dev)
300
336
const struct pci_device_id *id)
304
339
resource_size_t start, len;
305
340
struct lnw_gpio *lnw;
343
int ngpio = id->driver_data;
310
345
retval = pci_enable_device(pdev);
314
349
retval = pci_request_regions(pdev, "langwell_gpio");
316
351
dev_err(&pdev->dev, "error requesting resources\n");
319
/* get the irq_base from bar1 */
354
/* get the gpio_base from bar1 */
320
355
start = pci_resource_start(pdev, 1);
321
356
len = pci_resource_len(pdev, 1);
322
357
base = ioremap_nocache(start, len);
324
359
dev_err(&pdev->dev, "error mapping bar1\n");
327
irq_base = *(u32 *)base;
328
362
gpio_base = *((u32 *)base + 1);
329
363
/* release the IO mapping, since we already get the info from bar1 */
331
365
/* get the register base from bar0 */
332
366
start = pci_resource_start(pdev, 0);
333
367
len = pci_resource_len(pdev, 0);
334
base = ioremap_nocache(start, len);
368
base = devm_ioremap_nocache(&pdev->dev, start, len);
336
370
dev_err(&pdev->dev, "error mapping bar0\n");
337
371
retval = -EFAULT;
341
lnw = kzalloc(sizeof(struct lnw_gpio), GFP_KERNEL);
375
lnw = devm_kzalloc(&pdev->dev, sizeof(struct lnw_gpio), GFP_KERNEL);
343
377
dev_err(&pdev->dev, "can't allocate langwell_gpio chip data\n");
344
378
retval = -ENOMEM;
382
lnw->domain = irq_domain_add_linear(pdev->dev.of_node, ngpio,
383
&lnw_gpio_irq_ops, lnw);
347
387
lnw->reg_base = base;
348
lnw->irq_base = irq_base;
349
388
lnw->chip.label = dev_name(&pdev->dev);
350
389
lnw->chip.request = lnw_gpio_request;
351
390
lnw->chip.direction_input = lnw_gpio_direction_input;
354
393
lnw->chip.set = lnw_gpio_set;
355
394
lnw->chip.to_irq = lnw_gpio_to_irq;
356
395
lnw->chip.base = gpio_base;
357
lnw->chip.ngpio = id->driver_data;
396
lnw->chip.ngpio = ngpio;
358
397
lnw->chip.can_sleep = 0;
359
398
lnw->pdev = pdev;
360
399
pci_set_drvdata(pdev, lnw);
361
400
retval = gpiochip_add(&lnw->chip);
363
402
dev_err(&pdev->dev, "langwell gpiochip_add error %d\n", retval);
406
lnw_irq_init_hw(lnw);
366
408
irq_set_handler_data(pdev->irq, lnw);
367
409
irq_set_chained_handler(pdev->irq, lnw_irq_handler);
368
for (i = 0; i < lnw->chip.ngpio; i++) {
369
irq_set_chip_and_handler_name(i + lnw->irq_base, &lnw_irqchip,
370
handle_simple_irq, "demux");
371
irq_set_chip_data(i + lnw->irq_base, lnw);
374
411
spin_lock_init(&lnw->lock);
376
413
pm_runtime_put_noidle(&pdev->dev);
377
414
pm_runtime_allow(&pdev->dev);
385
419
pci_release_regions(pdev);
387
421
pci_disable_device(pdev);