335
* enum edac_mc_layer - memory controller hierarchy layer
337
* @EDAC_MC_LAYER_BRANCH: memory layer is named "branch"
338
* @EDAC_MC_LAYER_CHANNEL: memory layer is named "channel"
339
* @EDAC_MC_LAYER_SLOT: memory layer is named "slot"
340
* @EDAC_MC_LAYER_CHIP_SELECT: memory layer is named "chip select"
342
* This enum is used by the drivers to tell edac_mc_sysfs what name should
343
* be used when describing a memory stick location.
345
enum edac_mc_layer_type {
346
EDAC_MC_LAYER_BRANCH,
347
EDAC_MC_LAYER_CHANNEL,
349
EDAC_MC_LAYER_CHIP_SELECT,
353
* struct edac_mc_layer - describes the memory controller hierarchy
355
* @size: number of components per layer. For example,
356
* if the channel layer has two channels, size = 2
357
* @is_virt_csrow: This layer is part of the "csrow" when old API
358
* compatibility mode is enabled. Otherwise, it is
361
struct edac_mc_layer {
362
enum edac_mc_layer_type type;
368
* Maximum number of layers used by the memory controller to uniquely
369
* identify a single memory stick.
370
* NOTE: Changing this constant requires not only to change the constant
371
* below, but also to change the existing code at the core, as there are
372
* some code there that are optimized for 3 layers.
374
#define EDAC_MAX_LAYERS 3
377
* EDAC_DIMM_PTR - Macro responsible to find a pointer inside a pointer array
378
* for the element given by [layer0,layer1,layer2] position
380
* @layers: a struct edac_mc_layer array, describing how many elements
381
* were allocated for each layer
382
* @var: name of the var where we want to get the pointer
384
* @n_layers: Number of layers at the @layers array
385
* @layer0: layer0 position
386
* @layer1: layer1 position. Unused if n_layers < 2
387
* @layer2: layer2 position. Unused if n_layers < 3
389
* For 1 layer, this macro returns &var[layer0]
390
* For 2 layers, this macro is similar to allocate a bi-dimensional array
391
* and to return "&var[layer0][layer1]"
392
* For 3 layers, this macro is similar to allocate a tri-dimensional array
393
* and to return "&var[layer0][layer1][layer2]"
395
* A loop could be used here to make it more generic, but, as we only have
396
* 3 layers, this is a little faster.
397
* By design, layers can never be 0 or more than 3. If that ever happens,
398
* a NULL is returned, causing an OOPS during the memory allocation routine,
399
* with would point to the developer that he's doing something wrong.
401
#define EDAC_DIMM_PTR(layers, var, nlayers, layer0, layer1, layer2) ({ \
403
if ((nlayers) == 1) \
404
__p = &var[layer0]; \
405
else if ((nlayers) == 2) \
406
__p = &var[(layer1) + ((layers[1]).size * (layer0))]; \
407
else if ((nlayers) == 3) \
408
__p = &var[(layer2) + ((layers[2]).size * ((layer1) + \
409
((layers[1]).size * (layer0))))]; \
416
/* FIXME: add the proper per-location error counts */
418
char label[EDAC_MC_LABEL_LEN + 1]; /* DIMM label on motherboard */
420
/* Memory location data */
421
unsigned location[EDAC_MAX_LAYERS];
423
struct mem_ctl_info *mci; /* the parent */
425
u32 grain; /* granularity of reported error in bytes */
426
enum dev_type dtype; /* memory device type */
427
enum mem_type mtype; /* memory dimm type */
428
enum edac_type edac_mode; /* EDAC mode for this dimm */
430
u32 nr_pages; /* number of pages on this dimm */
432
unsigned csrow, cschannel; /* Points to the old API data */
316
436
* struct rank_info - contains the information for one DIMM rank
318
438
* @chan_idx: channel number where the rank is (typically, 0 or 1)
319
439
* @ce_count: number of correctable errors for this rank
320
* @label: DIMM label. Different ranks for the same DIMM should be
321
* filled, on userspace, with the same label.
322
* FIXME: The core currently won't enforce it.
323
440
* @csrow: A pointer to the chip select row structure (the parent
324
441
* structure). The location of the rank is given by
325
442
* the (csrow->csrow_idx, chan_idx) vector.
443
* @dimm: A pointer to the DIMM structure, where the DIMM label
444
* information is stored.
446
* FIXME: Currently, the EDAC core model will assume one DIMM per rank.
447
* This is a bad assumption, but it makes this patch easier. Later
448
* patches in this series will fix this issue.
327
450
struct rank_info {
330
char label[EDAC_MC_LABEL_LEN + 1];
331
struct csrow_info *csrow; /* the parent */
452
struct csrow_info *csrow;
453
struct dimm_info *dimm;
455
u32 ce_count; /* Correctable Errors for this csrow */
334
458
struct csrow_info {
335
unsigned long first_page; /* first page number in dimm */
336
unsigned long last_page; /* last page number in dimm */
459
/* Used only by edac_mc_find_csrow_by_page() */
460
unsigned long first_page; /* first page number in csrow */
461
unsigned long last_page; /* last page number in csrow */
337
462
unsigned long page_mask; /* used for interleaving -
340
u32 nr_pages; /* number of pages in csrow */
341
u32 grain; /* granularity of reported error in bytes */
342
int csrow_idx; /* the chip-select row */
343
enum dev_type dtype; /* memory device type */
463
* 0UL for non intlv */
465
int csrow_idx; /* the chip-select row */
344
467
u32 ue_count; /* Uncorrectable Errors for this csrow */
345
468
u32 ce_count; /* Correctable Errors for this csrow */
346
enum mem_type mtype; /* memory csrow type */
347
enum edac_type edac_mode; /* EDAC mode for this csrow */
348
470
struct mem_ctl_info *mci; /* the parent */
350
472
struct kobject kobj; /* sysfs kobject for this csrow */