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Viewing changes to arch/mips/ath79/clock.c

  • Committer: Package Import Robot
  • Author(s): Paolo Pisati, Paolo Pisati, Stefan Bader, Upstream Kernel Changes
  • Date: 2012-08-15 17:17:43 UTC
  • Revision ID: package-import@ubuntu.com-20120815171743-h5wnuf51xe7pvdid
Tags: 3.5.0-207.13
[ Paolo Pisati ]

* Start new release

[ Stefan Bader ]

* (config) Enable getabis to use local package copies

[ Upstream Kernel Changes ]

* fixup: gargabe collect iva_seq[0|1] init
* [Config] enable all SND_OMAP_SOC_*s
* fixup: cm2xxx_3xxx.o is needed for omap2_cm_read|write_reg
* fixup: add some snd_soc_dai* helper functions
* fixup: s/snd_soc_dpcm_params/snd_soc_dpcm/g
* fixup: typo, no_host_mode and useless SDP4430 init
* fixup: enable again aess hwmod

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arch/mips/ath79/clock.c
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/*
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 *  Atheros AR71XX/AR724X/AR913X common routines
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 *
 
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 *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
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 *  Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
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 *
 
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 *  Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
 
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 *
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 *  This program is free software; you can redistribute it and/or modify it
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 *  under the terms of the GNU General Public License version 2 as published
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 *  by the Free Software Foundation.
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        ath79_uart_clk.rate = ath79_ref_clk.rate;
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}
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static void __init ar934x_clocks_init(void)
 
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{
 
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        u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
 
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        u32 cpu_pll, ddr_pll;
 
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        u32 bootstrap;
 
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        bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
 
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        if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40)
 
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                ath79_ref_clk.rate = 40 * 1000 * 1000;
 
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        else
 
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                ath79_ref_clk.rate = 25 * 1000 * 1000;
 
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        pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG);
 
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        out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
 
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                  AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
 
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        ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
 
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                  AR934X_PLL_CPU_CONFIG_REFDIV_MASK;
 
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        nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
 
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               AR934X_PLL_CPU_CONFIG_NINT_MASK;
 
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        frac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
 
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               AR934X_PLL_CPU_CONFIG_NFRAC_MASK;
 
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        cpu_pll = nint * ath79_ref_clk.rate / ref_div;
 
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        cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 6));
 
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        cpu_pll /= (1 << out_div);
 
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        pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG);
 
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        out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
 
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                  AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
 
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        ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
 
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                  AR934X_PLL_DDR_CONFIG_REFDIV_MASK;
 
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        nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
 
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               AR934X_PLL_DDR_CONFIG_NINT_MASK;
 
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        frac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
 
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               AR934X_PLL_DDR_CONFIG_NFRAC_MASK;
 
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        ddr_pll = nint * ath79_ref_clk.rate / ref_div;
 
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        ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 10));
 
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        ddr_pll /= (1 << out_div);
 
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        clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
 
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        postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
 
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                  AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
 
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        if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS)
 
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                ath79_cpu_clk.rate = ath79_ref_clk.rate;
 
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        else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL)
 
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                ath79_cpu_clk.rate = cpu_pll / (postdiv + 1);
 
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        else
 
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                ath79_cpu_clk.rate = ddr_pll / (postdiv + 1);
 
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        postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) &
 
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                  AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK;
 
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        if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS)
 
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                ath79_ddr_clk.rate = ath79_ref_clk.rate;
 
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        else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL)
 
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                ath79_ddr_clk.rate = ddr_pll / (postdiv + 1);
 
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        else
 
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                ath79_ddr_clk.rate = cpu_pll / (postdiv + 1);
 
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        postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) &
 
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                  AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK;
 
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        if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS)
 
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                ath79_ahb_clk.rate = ath79_ref_clk.rate;
 
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        else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL)
 
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                ath79_ahb_clk.rate = ddr_pll / (postdiv + 1);
 
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        else
 
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                ath79_ahb_clk.rate = cpu_pll / (postdiv + 1);
 
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        ath79_wdt_clk.rate = ath79_ref_clk.rate;
 
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        ath79_uart_clk.rate = ath79_ref_clk.rate;
 
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}
 
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void __init ath79_clocks_init(void)
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{
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        if (soc_is_ar71xx())
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                ar913x_clocks_init();
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        else if (soc_is_ar933x())
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                ar933x_clocks_init();
 
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        else if (soc_is_ar934x())
 
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                ar934x_clocks_init();
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        else
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                BUG();
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