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* internal execution defines for qemu
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* Copyright (c) 2003 Fabrice Bellard
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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#include "qemu-common.h"
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/* allow to see translation results - the slowdown should be negligible, so we leave it */
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/* Page tracking code uses ram addresses in system mode, and virtual
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addresses in userspace mode. Define tb_page_addr_t to be an appropriate
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#if defined(CONFIG_USER_ONLY)
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typedef abi_ulong tb_page_addr_t;
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typedef ram_addr_t tb_page_addr_t;
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/* is_jmp field values */
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#define DISAS_NEXT 0 /* next instruction can be analyzed */
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#define DISAS_JUMP 1 /* only pc was modified dynamically */
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#define DISAS_UPDATE 2 /* cpu state was modified dynamically */
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#define DISAS_TB_JUMP 3 /* only pc was modified statically */
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struct TranslationBlock;
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typedef struct TranslationBlock TranslationBlock;
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/* XXX: make safe guess about sizes */
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#define MAX_OP_PER_INSTR 208
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#if HOST_LONG_BITS == 32
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#define MAX_OPC_PARAM_PER_ARG 2
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#define MAX_OPC_PARAM_PER_ARG 1
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#define MAX_OPC_PARAM_IARGS 4
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#define MAX_OPC_PARAM_OARGS 1
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#define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
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/* A Call op needs up to 4 + 2N parameters on 32-bit archs,
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* and up to 4 + N parameters on 64-bit archs
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* (N = number of input arguments + output arguments). */
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#define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
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#define OPC_BUF_SIZE 640
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#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
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/* Maximum size a TCG op can expand to. This is complicated because a
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single op may require several host instructions and register reloads.
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For now take a wild guess at 192 bytes, which should allow at least
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a couple of fixup instructions per argument. */
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#define TCG_MAX_OP_SIZE 192
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#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
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extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
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extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
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extern uint16_t gen_opc_icount[OPC_BUF_SIZE];
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void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
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void gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
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void restore_state_to_opc(CPUState *env, struct TranslationBlock *tb,
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void cpu_gen_init(void);
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int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
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int *gen_code_size_ptr);
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int cpu_restore_state(struct TranslationBlock *tb,
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CPUState *env, unsigned long searched_pc);
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void cpu_resume_from_signal(CPUState *env1, void *puc);
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void cpu_io_recompile(CPUState *env, void *retaddr);
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TranslationBlock *tb_gen_code(CPUState *env,
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target_ulong pc, target_ulong cs_base, int flags,
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void cpu_exec_init(CPUState *env);
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void QEMU_NORETURN cpu_loop_exit(CPUState *env1);
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int page_unprotect(target_ulong address, unsigned long pc, void *puc);
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void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
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int is_cpu_write_access);
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void tlb_flush_page(CPUState *env, target_ulong addr);
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void tlb_flush(CPUState *env, int flush_global);
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#if !defined(CONFIG_USER_ONLY)
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void tlb_set_page(CPUState *env, target_ulong vaddr,
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target_phys_addr_t paddr, int prot,
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int mmu_idx, target_ulong size);
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#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
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#define CODE_GEN_PHYS_HASH_BITS 15
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#define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS)
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#define MIN_CODE_GEN_BUFFER_SIZE (1024 * 1024)
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/* estimated block size for TB allocation */
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/* XXX: use a per code average code fragment size and modulate it
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according to the host CPU */
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#if defined(CONFIG_SOFTMMU)
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#define CODE_GEN_AVG_BLOCK_SIZE 128
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#define CODE_GEN_AVG_BLOCK_SIZE 64
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#if defined(_ARCH_PPC) || defined(__x86_64__) || defined(__arm__) || defined(__i386__)
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#define USE_DIRECT_JUMP
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#elif defined(CONFIG_TCG_INTERPRETER)
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#define USE_DIRECT_JUMP
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struct TranslationBlock {
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target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
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target_ulong cs_base; /* CS base for this block */
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uint64_t flags; /* flags defining in which context the code was generated */
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uint16_t size; /* size of target code for this block (1 <=
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size <= TARGET_PAGE_SIZE) */
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uint16_t cflags; /* compile flags */
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#define CF_COUNT_MASK 0x7fff
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#define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */
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uint8_t *tc_ptr; /* pointer to the translated code */
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/* next matching tb for physical address. */
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struct TranslationBlock *phys_hash_next;
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/* first and second physical page containing code. The lower bit
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of the pointer tells the index in page_next[] */
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struct TranslationBlock *page_next[2];
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tb_page_addr_t page_addr[2];
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/* the following data are used to directly call another TB from
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the code of this one. */
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uint16_t tb_next_offset[2]; /* offset of original jump target */
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#ifdef USE_DIRECT_JUMP
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uint16_t tb_jmp_offset[2]; /* offset of jump instruction */
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unsigned long tb_next[2]; /* address of jump generated code */
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/* list of TBs jumping to this one. This is a circular list using
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the two least significant bits of the pointers to tell what is
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the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
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struct TranslationBlock *jmp_next[2];
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struct TranslationBlock *jmp_first;
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static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
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tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
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return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
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static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
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tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
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return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
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| (tmp & TB_JMP_ADDR_MASK));
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static inline unsigned int tb_phys_hash_func(tb_page_addr_t pc)
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return (pc >> 2) & (CODE_GEN_PHYS_HASH_SIZE - 1);
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void tb_free(TranslationBlock *tb);
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void tb_flush(CPUState *env);
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void tb_link_page(TranslationBlock *tb,
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tb_page_addr_t phys_pc, tb_page_addr_t phys_page2);
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void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
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extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
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#if defined(USE_DIRECT_JUMP)
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#if defined(CONFIG_TCG_INTERPRETER)
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static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
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/* patch the branch destination */
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*(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
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/* no need to flush icache explicitly */
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#elif defined(_ARCH_PPC)
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void ppc_tb_set_jmp_target(unsigned long jmp_addr, unsigned long addr);
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#define tb_set_jmp_target1 ppc_tb_set_jmp_target
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#elif defined(__i386__) || defined(__x86_64__)
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static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
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/* patch the branch destination */
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*(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
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/* no need to flush icache explicitly */
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#elif defined(__arm__)
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static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
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#if !QEMU_GNUC_PREREQ(4, 1)
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register unsigned long _beg __asm ("a1");
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register unsigned long _end __asm ("a2");
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register unsigned long _flg __asm ("a3");
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/* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
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*(uint32_t *)jmp_addr =
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(*(uint32_t *)jmp_addr & ~0xffffff)
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| (((addr - (jmp_addr + 8)) >> 2) & 0xffffff);
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#if QEMU_GNUC_PREREQ(4, 1)
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__builtin___clear_cache((char *) jmp_addr, (char *) jmp_addr + 4);
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__asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
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#error tb_set_jmp_target1 is missing
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static inline void tb_set_jmp_target(TranslationBlock *tb,
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int n, unsigned long addr)
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unsigned long offset;
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offset = tb->tb_jmp_offset[n];
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tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
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/* set the jump target */
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static inline void tb_set_jmp_target(TranslationBlock *tb,
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int n, unsigned long addr)
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tb->tb_next[n] = addr;
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static inline void tb_add_jump(TranslationBlock *tb, int n,
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TranslationBlock *tb_next)
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/* NOTE: this test is only needed for thread safety */
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if (!tb->jmp_next[n]) {
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/* patch the native jump address */
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tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
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/* add in TB jmp circular list */
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tb->jmp_next[n] = tb_next->jmp_first;
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tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
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TranslationBlock *tb_find_pc(unsigned long pc_ptr);
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#include "qemu-lock.h"
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extern spinlock_t tb_lock;
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extern int tb_invalidated_flag;
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/* The return address may point to the start of the next instruction.
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Subtracting one gets us the call instruction itself. */
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#if defined(CONFIG_TCG_INTERPRETER)
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/* Alpha and SH4 user mode emulations and Softmmu call GETPC().
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For all others, GETPC remains undefined (which makes TCI a little faster. */
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# if defined(CONFIG_SOFTMMU) || defined(TARGET_ALPHA) || defined(TARGET_SH4)
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extern void *tci_tb_ptr;
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# define GETPC() tci_tb_ptr
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#elif defined(__s390__) && !defined(__s390x__)
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# define GETPC() ((void*)(((unsigned long)__builtin_return_address(0) & 0x7fffffffUL) - 1))
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#elif defined(__arm__)
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/* Thumb return addresses have the low bit set, so we need to subtract two.
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This is still safe in ARM mode because instructions are 4 bytes. */
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# define GETPC() ((void *)((unsigned long)__builtin_return_address(0) - 2))
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# define GETPC() ((void *)((unsigned long)__builtin_return_address(0) - 1))
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#if !defined(CONFIG_USER_ONLY)
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extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
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extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
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extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
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void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx,
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#include "softmmu_defs.h"
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#define ACCESS_TYPE (NB_MMU_MODES + 1)
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#define MEMSUFFIX _code
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#define env cpu_single_env
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#include "softmmu_header.h"
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#include "softmmu_header.h"
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#include "softmmu_header.h"
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#include "softmmu_header.h"
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#if defined(CONFIG_USER_ONLY)
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static inline tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr)
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/* NOTE: this function can trigger an exception */
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/* NOTE2: the returned address is not exactly the physical address: it
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is the offset relative to phys_ram_base */
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static inline tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr)
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int mmu_idx, page_index, pd;
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page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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mmu_idx = cpu_mmu_index(env1);
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if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
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(addr & TARGET_PAGE_MASK))) {
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pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK;
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if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
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#if defined(TARGET_ALPHA) || defined(TARGET_MIPS) || defined(TARGET_SPARC)
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cpu_unassigned_access(env1, addr, 0, 1, 0, 4);
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cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
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p = (void *)((uintptr_t)addr + env1->tlb_table[mmu_idx][page_index].addend);
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return qemu_ram_addr_from_host_nofail(p);
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typedef void (CPUDebugExcpHandler)(CPUState *env);
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CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler);
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extern int singlestep;
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extern volatile sig_atomic_t exit_request;
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/* Deterministic execution requires that IO only be performed on the last
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instruction of a TB so that interrupts take effect immediately. */
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static inline int can_do_io(CPUState *env)
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/* If not executing code then assume we are ok. */
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if (!env->current_tb) {
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return env->can_do_io != 0;
added
removed
exec-all.h
