2
* QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
4
* Copyright (c) 2003-2005, 2007 Jocelyn Mayer
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26
#include "qemu-timer.h"
33
#if defined(DEBUG_NVRAM)
34
#define NVRAM_PRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0)
36
#define NVRAM_PRINTF(fmt, ...) do { } while (0)
40
* The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has
41
* alarm and a watchdog timer and related control registers. In the
42
* PPC platform there is also a nvram lock function.
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* http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf
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* http://www.st.com/stonline/products/literature/ds/2411/m48t08.pdf
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* http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf
53
/* Hardware parameters */
60
/* Alarm & watchdog */
62
struct QEMUTimer *alrm_timer;
63
struct QEMUTimer *wd_timer;
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/* Model parameters */
67
uint32_t type; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */
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typedef struct M48t59ISAState {
79
typedef struct M48t59SysBusState {
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/* Fake timer functions */
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/* Alarm management */
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static void alarm_cb (void *opaque)
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M48t59State *NVRAM = opaque;
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qemu_set_irq(NVRAM->IRQ, 1);
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if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 &&
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(NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
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(NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
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(NVRAM->buffer[0x1FF2] & 0x80) == 0) {
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/* Repeat once a month */
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qemu_get_timedate(&tm, NVRAM->time_offset);
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if (tm.tm_mon == 13) {
105
next_time = qemu_timedate_diff(&tm) - NVRAM->time_offset;
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} else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
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(NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
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(NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
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(NVRAM->buffer[0x1FF2] & 0x80) == 0) {
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/* Repeat once a day */
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next_time = 24 * 60 * 60;
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} else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
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(NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
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(NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
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(NVRAM->buffer[0x1FF2] & 0x80) == 0) {
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/* Repeat once an hour */
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} else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
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(NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
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(NVRAM->buffer[0x1FF3] & 0x80) != 0 &&
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(NVRAM->buffer[0x1FF2] & 0x80) == 0) {
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/* Repeat once a minute */
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/* Repeat once a second */
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qemu_mod_timer(NVRAM->alrm_timer, qemu_get_clock_ns(vm_clock) +
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qemu_set_irq(NVRAM->IRQ, 0);
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static void set_alarm(M48t59State *NVRAM)
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if (NVRAM->alrm_timer != NULL) {
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qemu_del_timer(NVRAM->alrm_timer);
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diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset;
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qemu_mod_timer(NVRAM->alrm_timer, diff * 1000);
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/* RTC management helpers */
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static inline void get_time(M48t59State *NVRAM, struct tm *tm)
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qemu_get_timedate(tm, NVRAM->time_offset);
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static void set_time(M48t59State *NVRAM, struct tm *tm)
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NVRAM->time_offset = qemu_timedate_diff(tm);
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/* Watchdog management */
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static void watchdog_cb (void *opaque)
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M48t59State *NVRAM = opaque;
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NVRAM->buffer[0x1FF0] |= 0x80;
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if (NVRAM->buffer[0x1FF7] & 0x80) {
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NVRAM->buffer[0x1FF7] = 0x00;
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NVRAM->buffer[0x1FFC] &= ~0x40;
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/* May it be a hw CPU Reset instead ? */
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qemu_system_reset_request();
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qemu_set_irq(NVRAM->IRQ, 1);
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qemu_set_irq(NVRAM->IRQ, 0);
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static void set_up_watchdog(M48t59State *NVRAM, uint8_t value)
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uint64_t interval; /* in 1/16 seconds */
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NVRAM->buffer[0x1FF0] &= ~0x80;
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if (NVRAM->wd_timer != NULL) {
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qemu_del_timer(NVRAM->wd_timer);
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interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F);
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qemu_mod_timer(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) +
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((interval * 1000) >> 4));
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/* Direct access to NVRAM */
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void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
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M48t59State *NVRAM = opaque;
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if (addr > 0x1FF8 && addr < 0x2000)
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NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
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/* check for NVRAM access */
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if ((NVRAM->type == 2 && addr < 0x7f8) ||
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(NVRAM->type == 8 && addr < 0x1ff8) ||
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(NVRAM->type == 59 && addr < 0x1ff0))
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/* flags register : read-only */
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tmp = from_bcd(val & 0x7F);
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if (tmp >= 0 && tmp <= 59) {
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NVRAM->alarm.tm_sec = tmp;
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NVRAM->buffer[0x1FF2] = val;
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tmp = from_bcd(val & 0x7F);
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if (tmp >= 0 && tmp <= 59) {
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NVRAM->alarm.tm_min = tmp;
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NVRAM->buffer[0x1FF3] = val;
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tmp = from_bcd(val & 0x3F);
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if (tmp >= 0 && tmp <= 23) {
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NVRAM->alarm.tm_hour = tmp;
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NVRAM->buffer[0x1FF4] = val;
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tmp = from_bcd(val & 0x1F);
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NVRAM->alarm.tm_mday = tmp;
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NVRAM->buffer[0x1FF5] = val;
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NVRAM->buffer[0x1FF6] = val;
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NVRAM->buffer[0x1FF7] = val;
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set_up_watchdog(NVRAM, val);
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NVRAM->buffer[addr] = (val & ~0xA0) | 0x90;
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tmp = from_bcd(val & 0x7F);
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if (tmp >= 0 && tmp <= 59) {
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get_time(NVRAM, &tm);
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set_time(NVRAM, &tm);
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if ((val & 0x80) ^ (NVRAM->buffer[addr] & 0x80)) {
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NVRAM->stop_time = time(NULL);
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NVRAM->time_offset += NVRAM->stop_time - time(NULL);
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NVRAM->stop_time = 0;
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NVRAM->buffer[addr] = val & 0x80;
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tmp = from_bcd(val & 0x7F);
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if (tmp >= 0 && tmp <= 59) {
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get_time(NVRAM, &tm);
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set_time(NVRAM, &tm);
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tmp = from_bcd(val & 0x3F);
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if (tmp >= 0 && tmp <= 23) {
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get_time(NVRAM, &tm);
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set_time(NVRAM, &tm);
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/* day of the week / century */
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tmp = from_bcd(val & 0x07);
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get_time(NVRAM, &tm);
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set_time(NVRAM, &tm);
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NVRAM->buffer[addr] = val & 0x40;
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tmp = from_bcd(val & 0x1F);
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get_time(NVRAM, &tm);
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set_time(NVRAM, &tm);
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tmp = from_bcd(val & 0x1F);
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if (tmp >= 1 && tmp <= 12) {
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get_time(NVRAM, &tm);
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set_time(NVRAM, &tm);
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if (tmp >= 0 && tmp <= 99) {
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get_time(NVRAM, &tm);
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if (NVRAM->type == 8)
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tm.tm_year = from_bcd(val) + 68; // Base year is 1968
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tm.tm_year = from_bcd(val);
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set_time(NVRAM, &tm);
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/* Check lock registers state */
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if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
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if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
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if (addr < NVRAM->size) {
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NVRAM->buffer[addr] = val & 0xFF;
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uint32_t m48t59_read (void *opaque, uint32_t addr)
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M48t59State *NVRAM = opaque;
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uint32_t retval = 0xFF;
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/* check for NVRAM access */
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if ((NVRAM->type == 2 && addr < 0x078f) ||
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(NVRAM->type == 8 && addr < 0x1ff8) ||
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(NVRAM->type == 59 && addr < 0x1ff0))
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/* A read resets the watchdog */
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set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
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get_time(NVRAM, &tm);
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retval = (NVRAM->buffer[addr] & 0x80) | to_bcd(tm.tm_sec);
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get_time(NVRAM, &tm);
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retval = to_bcd(tm.tm_min);
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get_time(NVRAM, &tm);
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retval = to_bcd(tm.tm_hour);
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/* day of the week / century */
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get_time(NVRAM, &tm);
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retval = NVRAM->buffer[addr] | tm.tm_wday;
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get_time(NVRAM, &tm);
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retval = to_bcd(tm.tm_mday);
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get_time(NVRAM, &tm);
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retval = to_bcd(tm.tm_mon + 1);
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get_time(NVRAM, &tm);
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if (NVRAM->type == 8)
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retval = to_bcd(tm.tm_year - 68); // Base year is 1968
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retval = to_bcd(tm.tm_year);
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/* Check lock registers state */
448
if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
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if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
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if (addr < NVRAM->size) {
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retval = NVRAM->buffer[addr];
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if (addr > 0x1FF9 && addr < 0x2000)
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NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
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void m48t59_set_addr (void *opaque, uint32_t addr)
466
M48t59State *NVRAM = opaque;
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void m48t59_toggle_lock (void *opaque, int lock)
473
M48t59State *NVRAM = opaque;
475
NVRAM->lock ^= 1 << lock;
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/* IO access to NVRAM */
479
static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val)
481
M48t59State *NVRAM = opaque;
483
NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
486
NVRAM->addr &= ~0x00FF;
490
NVRAM->addr &= ~0xFF00;
491
NVRAM->addr |= val << 8;
494
m48t59_write(NVRAM, NVRAM->addr, val);
495
NVRAM->addr = 0x0000;
502
static uint32_t NVRAM_readb (void *opaque, uint32_t addr)
504
M48t59State *NVRAM = opaque;
509
retval = m48t59_read(NVRAM, NVRAM->addr);
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NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
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static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
522
M48t59State *NVRAM = opaque;
524
m48t59_write(NVRAM, addr, value & 0xff);
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static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
529
M48t59State *NVRAM = opaque;
531
m48t59_write(NVRAM, addr, (value >> 8) & 0xff);
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m48t59_write(NVRAM, addr + 1, value & 0xff);
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static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
537
M48t59State *NVRAM = opaque;
539
m48t59_write(NVRAM, addr, (value >> 24) & 0xff);
540
m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff);
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m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff);
542
m48t59_write(NVRAM, addr + 3, value & 0xff);
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static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
547
M48t59State *NVRAM = opaque;
550
retval = m48t59_read(NVRAM, addr);
554
static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
556
M48t59State *NVRAM = opaque;
559
retval = m48t59_read(NVRAM, addr) << 8;
560
retval |= m48t59_read(NVRAM, addr + 1);
564
static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
566
M48t59State *NVRAM = opaque;
569
retval = m48t59_read(NVRAM, addr) << 24;
570
retval |= m48t59_read(NVRAM, addr + 1) << 16;
571
retval |= m48t59_read(NVRAM, addr + 2) << 8;
572
retval |= m48t59_read(NVRAM, addr + 3);
576
static CPUWriteMemoryFunc * const nvram_write[] = {
582
static CPUReadMemoryFunc * const nvram_read[] = {
588
static const VMStateDescription vmstate_m48t59 = {
591
.minimum_version_id = 1,
592
.minimum_version_id_old = 1,
593
.fields = (VMStateField[]) {
594
VMSTATE_UINT8(lock, M48t59State),
595
VMSTATE_UINT16(addr, M48t59State),
596
VMSTATE_VBUFFER_UINT32(buffer, M48t59State, 0, NULL, 0, size),
597
VMSTATE_END_OF_LIST()
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static void m48t59_reset_common(M48t59State *NVRAM)
605
if (NVRAM->alrm_timer != NULL)
606
qemu_del_timer(NVRAM->alrm_timer);
608
if (NVRAM->wd_timer != NULL)
609
qemu_del_timer(NVRAM->wd_timer);
612
static void m48t59_reset_isa(DeviceState *d)
614
M48t59ISAState *isa = container_of(d, M48t59ISAState, busdev.qdev);
615
M48t59State *NVRAM = &isa->state;
617
m48t59_reset_common(NVRAM);
620
static void m48t59_reset_sysbus(DeviceState *d)
622
M48t59SysBusState *sys = container_of(d, M48t59SysBusState, busdev.qdev);
623
M48t59State *NVRAM = &sys->state;
625
m48t59_reset_common(NVRAM);
628
static const MemoryRegionPortio m48t59_portio[] = {
629
{0, 4, 1, .read = NVRAM_readb, .write = NVRAM_writeb },
630
PORTIO_END_OF_LIST(),
633
static const MemoryRegionOps m48t59_io_ops = {
634
.old_portio = m48t59_portio,
637
/* Initialisation routine */
638
M48t59State *m48t59_init(qemu_irq IRQ, target_phys_addr_t mem_base,
639
uint32_t io_base, uint16_t size, int type)
643
M48t59SysBusState *d;
646
dev = qdev_create(NULL, "m48t59");
647
qdev_prop_set_uint32(dev, "type", type);
648
qdev_prop_set_uint32(dev, "size", size);
649
qdev_prop_set_uint32(dev, "io_base", io_base);
650
qdev_init_nofail(dev);
651
s = sysbus_from_qdev(dev);
652
d = FROM_SYSBUS(M48t59SysBusState, s);
654
sysbus_connect_irq(s, 0, IRQ);
656
register_ioport_read(io_base, 0x04, 1, NVRAM_readb, state);
657
register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, state);
660
sysbus_mmio_map(s, 0, mem_base);
666
M48t59State *m48t59_init_isa(uint32_t io_base, uint16_t size, int type)
672
dev = isa_create("m48t59_isa");
673
qdev_prop_set_uint32(&dev->qdev, "type", type);
674
qdev_prop_set_uint32(&dev->qdev, "size", size);
675
qdev_prop_set_uint32(&dev->qdev, "io_base", io_base);
676
qdev_init_nofail(&dev->qdev);
677
d = DO_UPCAST(M48t59ISAState, busdev, dev);
680
memory_region_init_io(&d->io, &m48t59_io_ops, s, "m48t59", 4);
682
isa_register_ioport(dev, &d->io, io_base);
688
static void m48t59_init_common(M48t59State *s)
690
s->buffer = g_malloc0(s->size);
692
s->alrm_timer = qemu_new_timer_ns(vm_clock, &alarm_cb, s);
693
s->wd_timer = qemu_new_timer_ns(vm_clock, &watchdog_cb, s);
695
qemu_get_timedate(&s->alarm, 0);
697
vmstate_register(NULL, -1, &vmstate_m48t59, s);
700
static int m48t59_init_isa1(ISADevice *dev)
702
M48t59ISAState *d = DO_UPCAST(M48t59ISAState, busdev, dev);
703
M48t59State *s = &d->state;
705
isa_init_irq(dev, &s->IRQ, 8);
706
m48t59_init_common(s);
711
static int m48t59_init1(SysBusDevice *dev)
713
M48t59SysBusState *d = FROM_SYSBUS(M48t59SysBusState, dev);
714
M48t59State *s = &d->state;
717
sysbus_init_irq(dev, &s->IRQ);
719
mem_index = cpu_register_io_memory(nvram_read, nvram_write, s,
720
DEVICE_NATIVE_ENDIAN);
721
sysbus_init_mmio(dev, s->size, mem_index);
722
m48t59_init_common(s);
727
static ISADeviceInfo m48t59_isa_info = {
728
.init = m48t59_init_isa1,
729
.qdev.name = "m48t59_isa",
730
.qdev.size = sizeof(M48t59ISAState),
731
.qdev.reset = m48t59_reset_isa,
733
.qdev.props = (Property[]) {
734
DEFINE_PROP_UINT32("size", M48t59ISAState, state.size, -1),
735
DEFINE_PROP_UINT32("type", M48t59ISAState, state.type, -1),
736
DEFINE_PROP_HEX32( "io_base", M48t59ISAState, state.io_base, 0),
737
DEFINE_PROP_END_OF_LIST(),
741
static SysBusDeviceInfo m48t59_info = {
742
.init = m48t59_init1,
743
.qdev.name = "m48t59",
744
.qdev.size = sizeof(M48t59SysBusState),
745
.qdev.reset = m48t59_reset_sysbus,
746
.qdev.props = (Property[]) {
747
DEFINE_PROP_UINT32("size", M48t59SysBusState, state.size, -1),
748
DEFINE_PROP_UINT32("type", M48t59SysBusState, state.type, -1),
749
DEFINE_PROP_HEX32( "io_base", M48t59SysBusState, state.io_base, 0),
750
DEFINE_PROP_END_OF_LIST(),
754
static void m48t59_register_devices(void)
756
sysbus_register_withprop(&m48t59_info);
757
isa_qdev_register(&m48t59_isa_info);
760
device_init(m48t59_register_devices)