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  • Committer: Al Stone
  • Date: 2012-02-09 01:17:20 UTC
  • Revision ID: albert.stone@canonical.com-20120209011720-tztl7ik3qayz80p4
first commit to bzr for qemu

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hw/heathrow_pic.c
 
1
/*
 
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 * Heathrow PIC support (OldWorld PowerMac)
 
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 *
 
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 * Copyright (c) 2005-2007 Fabrice Bellard
 
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 * Copyright (c) 2007 Jocelyn Mayer
 
6
 *
 
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
 
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 * of this software and associated documentation files (the "Software"), to deal
 
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 * in the Software without restriction, including without limitation the rights
 
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 
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 * copies of the Software, and to permit persons to whom the Software is
 
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 * furnished to do so, subject to the following conditions:
 
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 *
 
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 * The above copyright notice and this permission notice shall be included in
 
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 * all copies or substantial portions of the Software.
 
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 *
 
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 
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 * THE SOFTWARE.
 
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 */
 
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#include "hw.h"
 
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#include "ppc_mac.h"
 
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/* debug PIC */
 
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//#define DEBUG_PIC
 
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#ifdef DEBUG_PIC
 
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#define PIC_DPRINTF(fmt, ...)                                   \
 
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    do { printf("PIC: " fmt , ## __VA_ARGS__); } while (0)
 
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#else
 
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#define PIC_DPRINTF(fmt, ...)
 
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#endif
 
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typedef struct HeathrowPIC {
 
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    uint32_t events;
 
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    uint32_t mask;
 
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    uint32_t levels;
 
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    uint32_t level_triggered;
 
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} HeathrowPIC;
 
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typedef struct HeathrowPICS {
 
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    MemoryRegion mem;
 
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    HeathrowPIC pics[2];
 
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    qemu_irq *irqs;
 
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} HeathrowPICS;
 
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static inline int check_irq(HeathrowPIC *pic)
 
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{
 
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    return (pic->events | (pic->levels & pic->level_triggered)) & pic->mask;
 
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}
 
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/* update the CPU irq state */
 
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static void heathrow_pic_update(HeathrowPICS *s)
 
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{
 
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    if (check_irq(&s->pics[0]) || check_irq(&s->pics[1])) {
 
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        qemu_irq_raise(s->irqs[0]);
 
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    } else {
 
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        qemu_irq_lower(s->irqs[0]);
 
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    }
 
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}
 
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static void pic_write(void *opaque, target_phys_addr_t addr,
 
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                      uint64_t value, unsigned size)
 
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{
 
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    HeathrowPICS *s = opaque;
 
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    HeathrowPIC *pic;
 
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    unsigned int n;
 
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    n = ((addr & 0xfff) - 0x10) >> 4;
 
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    PIC_DPRINTF("writel: " TARGET_FMT_plx " %u: %08x\n", addr, n, value);
 
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    if (n >= 2)
 
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        return;
 
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    pic = &s->pics[n];
 
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    switch(addr & 0xf) {
 
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    case 0x04:
 
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        pic->mask = value;
 
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        heathrow_pic_update(s);
 
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        break;
 
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    case 0x08:
 
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        /* do not reset level triggered IRQs */
 
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        value &= ~pic->level_triggered;
 
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        pic->events &= ~value;
 
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        heathrow_pic_update(s);
 
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        break;
 
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    default:
 
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        break;
 
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    }
 
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}
 
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static uint64_t pic_read(void *opaque, target_phys_addr_t addr,
 
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                         unsigned size)
 
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{
 
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    HeathrowPICS *s = opaque;
 
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    HeathrowPIC *pic;
 
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    unsigned int n;
 
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    uint32_t value;
 
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    n = ((addr & 0xfff) - 0x10) >> 4;
 
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    if (n >= 2) {
 
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        value = 0;
 
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    } else {
 
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        pic = &s->pics[n];
 
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        switch(addr & 0xf) {
 
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        case 0x0:
 
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            value = pic->events;
 
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            break;
 
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        case 0x4:
 
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            value = pic->mask;
 
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            break;
 
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        case 0xc:
 
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            value = pic->levels;
 
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            break;
 
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        default:
 
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            value = 0;
 
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            break;
 
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        }
 
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    }
 
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    PIC_DPRINTF("readl: " TARGET_FMT_plx " %u: %08x\n", addr, n, value);
 
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    return value;
 
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}
 
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static const MemoryRegionOps heathrow_pic_ops = {
 
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    .read = pic_read,
 
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    .write = pic_write,
 
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    .endianness = DEVICE_LITTLE_ENDIAN,
 
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};
 
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static void heathrow_pic_set_irq(void *opaque, int num, int level)
 
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{
 
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    HeathrowPICS *s = opaque;
 
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    HeathrowPIC *pic;
 
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    unsigned int irq_bit;
 
137
 
 
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#if defined(DEBUG)
 
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    {
 
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        static int last_level[64];
 
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        if (last_level[num] != level) {
 
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            PIC_DPRINTF("set_irq: num=0x%02x level=%d\n", num, level);
 
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            last_level[num] = level;
 
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        }
 
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    }
 
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#endif
 
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    pic = &s->pics[1 - (num >> 5)];
 
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    irq_bit = 1 << (num & 0x1f);
 
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    if (level) {
 
150
        pic->events |= irq_bit & ~pic->level_triggered;
 
151
        pic->levels |= irq_bit;
 
152
    } else {
 
153
        pic->levels &= ~irq_bit;
 
154
    }
 
155
    heathrow_pic_update(s);
 
156
}
 
157
 
 
158
static const VMStateDescription vmstate_heathrow_pic_one = {
 
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    .name = "heathrow_pic_one",
 
160
    .version_id = 0,
 
161
    .minimum_version_id = 0,
 
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    .minimum_version_id_old = 0,
 
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    .fields      = (VMStateField[]) {
 
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        VMSTATE_UINT32(events, HeathrowPIC),
 
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        VMSTATE_UINT32(mask, HeathrowPIC),
 
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        VMSTATE_UINT32(levels, HeathrowPIC),
 
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        VMSTATE_UINT32(level_triggered, HeathrowPIC),
 
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        VMSTATE_END_OF_LIST()
 
169
    }
 
170
};
 
171
 
 
172
static const VMStateDescription vmstate_heathrow_pic = {
 
173
    .name = "heathrow_pic",
 
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    .version_id = 1,
 
175
    .minimum_version_id = 1,
 
176
    .minimum_version_id_old = 1,
 
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    .fields      = (VMStateField[]) {
 
178
        VMSTATE_STRUCT_ARRAY(pics, HeathrowPICS, 2, 1,
 
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                             vmstate_heathrow_pic_one, HeathrowPIC),
 
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        VMSTATE_END_OF_LIST()
 
181
    }
 
182
};
 
183
 
 
184
static void heathrow_pic_reset_one(HeathrowPIC *s)
 
185
{
 
186
    memset(s, '\0', sizeof(HeathrowPIC));
 
187
}
 
188
 
 
189
static void heathrow_pic_reset(void *opaque)
 
190
{
 
191
    HeathrowPICS *s = opaque;
 
192
 
 
193
    heathrow_pic_reset_one(&s->pics[0]);
 
194
    heathrow_pic_reset_one(&s->pics[1]);
 
195
 
 
196
    s->pics[0].level_triggered = 0;
 
197
    s->pics[1].level_triggered = 0x1ff00000;
 
198
}
 
199
 
 
200
qemu_irq *heathrow_pic_init(MemoryRegion **pmem,
 
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                            int nb_cpus, qemu_irq **irqs)
 
202
{
 
203
    HeathrowPICS *s;
 
204
 
 
205
    s = g_malloc0(sizeof(HeathrowPICS));
 
206
    /* only 1 CPU */
 
207
    s->irqs = irqs[0];
 
208
    memory_region_init_io(&s->mem, &heathrow_pic_ops, s,
 
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                          "heathrow-pic", 0x1000);
 
210
    *pmem = &s->mem;
 
211
 
 
212
    vmstate_register(NULL, -1, &vmstate_heathrow_pic, s);
 
213
    qemu_register_reset(heathrow_pic_reset, s);
 
214
    return qemu_allocate_irqs(heathrow_pic_set_irq, s, 64);
 
215
}