~ahs3/+junk/cq-qemu

CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/

333

CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/

334

CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/

335

};

336

337

enum Cfg9346Bits {

338

Cfg9346_Lock = 0x00,

339

Cfg9346_Unlock = 0xC0,

340

};

341

342

typedef enum {

343

CH_8139 = 0,

344

CH_8139_K,

345

CH_8139A,

346

CH_8139A_G,

347

CH_8139B,

348

CH_8130,

349

CH_8139C,

350

CH_8100,

351

CH_8100B_8139D,

352

CH_8101,

353

} chip_t;

354

355

enum chip_flags {

356

HasHltClk = (1 << 0),

357

HasLWake = (1 << 1),

358

};

359

360

#define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \

361

(b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)

362

#define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)

363

364

#define RTL8139_PCI_REVID_8139 0x10

365

#define RTL8139_PCI_REVID_8139CPLUS 0x20

366

367

#define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS

368

369

/* Size is 64 * 16bit words */

370

#define EEPROM_9346_ADDR_BITS 6

371

#define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS)

372

#define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1)

373

374

enum Chip9346Operation

375

{

376

Chip9346_op_mask = 0xc0, /* 10 zzzzzz */

377

Chip9346_op_read = 0x80, /* 10 AAAAAA */

378

Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */

379

Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */

380

Chip9346_op_write_enable = 0x30, /* 00 11zzzz */

381

Chip9346_op_write_all = 0x10, /* 00 01zzzz */

382

Chip9346_op_write_disable = 0x00, /* 00 00zzzz */

383

};

384

385

enum Chip9346Mode

386

{

387

Chip9346_none = 0,

388

Chip9346_enter_command_mode,

389

Chip9346_read_command,

390

Chip9346_data_read, /* from output register */

391

Chip9346_data_write, /* to input register, then to contents at specified address */

392

Chip9346_data_write_all, /* to input register, then filling contents */

393

};

394

395

typedef struct EEprom9346

396

{

397

uint16_t contents[EEPROM_9346_SIZE];

398

int mode;

399

uint32_t tick;

400

uint8_t address;

401

uint16_t input;

402

uint16_t output;

403

404

uint8_t eecs;

405

uint8_t eesk;

406

uint8_t eedi;

407

uint8_t eedo;

408

} EEprom9346;

409

410

typedef struct RTL8139TallyCounters

411

{

412

/* Tally counters */

413

uint64_t TxOk;

414

uint64_t RxOk;

415

uint64_t TxERR;

416

uint32_t RxERR;

417

uint16_t MissPkt;

418

uint16_t FAE;

419

uint32_t Tx1Col;

420

uint32_t TxMCol;

421

uint64_t RxOkPhy;

422

uint64_t RxOkBrd;

423

uint32_t RxOkMul;

424

uint16_t TxAbt;

425

uint16_t TxUndrn;

426

} RTL8139TallyCounters;

427

428

/* Clears all tally counters */

429

static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters);

430

431

typedef struct RTL8139State {

432

PCIDevice dev;

433

uint8_t phys[8]; /* mac address */

434

uint8_t mult[8]; /* multicast mask array */

435

436

uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */

437

uint32_t TxAddr[4]; /* TxAddr0 */

438

uint32_t RxBuf; /* Receive buffer */

439

uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */

440

uint32_t RxBufPtr;

441

uint32_t RxBufAddr;

442

443

uint16_t IntrStatus;

444

uint16_t IntrMask;

445

446

uint32_t TxConfig;

447

uint32_t RxConfig;

448

uint32_t RxMissed;

449

450

uint16_t CSCR;

451

452

uint8_t Cfg9346;

453

uint8_t Config0;

454

uint8_t Config1;

455

uint8_t Config3;

456

uint8_t Config4;

457

uint8_t Config5;

458

459

uint8_t clock_enabled;

460

uint8_t bChipCmdState;

461

462

uint16_t MultiIntr;

463

464

uint16_t BasicModeCtrl;

465

uint16_t BasicModeStatus;

466

uint16_t NWayAdvert;

467

uint16_t NWayLPAR;

468

uint16_t NWayExpansion;

469

470

uint16_t CpCmd;

471

uint8_t TxThresh;

472

473

NICState *nic;

474

NICConf conf;

475

476

/* C ring mode */

477

uint32_t currTxDesc;

478

479

/* C+ mode */

480

uint32_t cplus_enabled;

481

482

uint32_t currCPlusRxDesc;

483

uint32_t currCPlusTxDesc;

484

485

uint32_t RxRingAddrLO;

486

uint32_t RxRingAddrHI;

487

488

EEprom9346 eeprom;

489

490

uint32_t TCTR;

491

uint32_t TimerInt;

492

int64_t TCTR_base;

493

494

/* Tally counters */

495

RTL8139TallyCounters tally_counters;

496

497

/* Non-persistent data */

498

uint8_t *cplus_txbuffer;

499

int cplus_txbuffer_len;

500

int cplus_txbuffer_offset;

501

502

/* PCI interrupt timer */

503

QEMUTimer *timer;

504

int64_t TimerExpire;

505

506

MemoryRegion bar_io;

507

MemoryRegion bar_mem;

508

509

/* Support migration to/from old versions */

510

int rtl8139_mmio_io_addr_dummy;

511

} RTL8139State;

512

513

/* Writes tally counters to memory via DMA */

514

static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr);

515

516

static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time);

517

518

static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)

519

{

520

DPRINTF("eeprom command 0x%02x\n", command);

521

522

switch (command & Chip9346_op_mask)

523

{

524

case Chip9346_op_read:

525

{

526

eeprom->address = command & EEPROM_9346_ADDR_MASK;

527

eeprom->output = eeprom->contents[eeprom->address];

528

eeprom->eedo = 0;

529

eeprom->tick = 0;

530

eeprom->mode = Chip9346_data_read;

531

DPRINTF("eeprom read from address 0x%02x data=0x%04x\n",

532

eeprom->address, eeprom->output);

533

}

534

break;

535

536

case Chip9346_op_write:

537

{

538

eeprom->address = command & EEPROM_9346_ADDR_MASK;

539

eeprom->input = 0;

540

eeprom->tick = 0;

541

eeprom->mode = Chip9346_none; /* Chip9346_data_write */

542

DPRINTF("eeprom begin write to address 0x%02x\n",

543

eeprom->address);

544

}

545

break;

546

default:

547

eeprom->mode = Chip9346_none;

548

switch (command & Chip9346_op_ext_mask)

549

{

550

case Chip9346_op_write_enable:

551

DPRINTF("eeprom write enabled\n");

552

break;

553

case Chip9346_op_write_all:

554

DPRINTF("eeprom begin write all\n");

555

break;

556

case Chip9346_op_write_disable:

557

DPRINTF("eeprom write disabled\n");

558

break;

559

}

560

break;

561

}

562

}

563

564

static void prom9346_shift_clock(EEprom9346 *eeprom)

565

{

566

int bit = eeprom->eedi?1:0;

567

568

++ eeprom->tick;

569

570

DPRINTF("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi,

571

eeprom->eedo);

572

573

switch (eeprom->mode)

574

{

575

case Chip9346_enter_command_mode:

576

if (bit)

577

{

578

eeprom->mode = Chip9346_read_command;

579

eeprom->tick = 0;

580

eeprom->input = 0;

581

DPRINTF("eeprom: +++ synchronized, begin command read\n");

582

}

583

break;

584

585

case Chip9346_read_command:

586

eeprom->input = (eeprom->input << 1) | (bit & 1);

587

if (eeprom->tick == 8)

588

{

589

prom9346_decode_command(eeprom, eeprom->input & 0xff);

590

}

591

break;

592

593

case Chip9346_data_read:

594

eeprom->eedo = (eeprom->output & 0x8000)?1:0;

595

eeprom->output <<= 1;

596

if (eeprom->tick == 16)

597

{

598

#if 1

599

// the FreeBSD drivers (rl and re) don't explicitly toggle

600

// CS between reads (or does setting Cfg9346 to 0 count too?),

601

// so we need to enter wait-for-command state here

602

eeprom->mode = Chip9346_enter_command_mode;

603

eeprom->input = 0;

604

eeprom->tick = 0;

605

606

DPRINTF("eeprom: +++ end of read, awaiting next command\n");

607

#else

608

// original behaviour

609

++eeprom->address;

610

eeprom->address &= EEPROM_9346_ADDR_MASK;

611

eeprom->output = eeprom->contents[eeprom->address];

612

eeprom->tick = 0;

613

614

DPRINTF("eeprom: +++ read next address 0x%02x data=0x%04x\n",

615

eeprom->address, eeprom->output);

616

#endif

617

}

618

break;

619

620

case Chip9346_data_write:

621

eeprom->input = (eeprom->input << 1) | (bit & 1);

622

if (eeprom->tick == 16)

623

{

624

DPRINTF("eeprom write to address 0x%02x data=0x%04x\n",

625

eeprom->address, eeprom->input);

626

627

eeprom->contents[eeprom->address] = eeprom->input;

628

eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */

629

eeprom->tick = 0;

630

eeprom->input = 0;

631

}

632

break;

633

634

case Chip9346_data_write_all:

635

eeprom->input = (eeprom->input << 1) | (bit & 1);

636

if (eeprom->tick == 16)

637

{

638

int i;

639

for (i = 0; i < EEPROM_9346_SIZE; i++)

640

{

641

eeprom->contents[i] = eeprom->input;

642

}

643

DPRINTF("eeprom filled with data=0x%04x\n", eeprom->input);

644

645

eeprom->mode = Chip9346_enter_command_mode;

646

eeprom->tick = 0;

647

eeprom->input = 0;

648

}

649

break;

650

651

default:

652

break;

653

}

654

}

655

656

static int prom9346_get_wire(RTL8139State *s)

657

{

658

EEprom9346 *eeprom = &s->eeprom;

659

if (!eeprom->eecs)

660

return 0;

661

662

return eeprom->eedo;

663

}

664

665

/* FIXME: This should be merged into/replaced by eeprom93xx.c. */

666

static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi)

667

{

668

EEprom9346 *eeprom = &s->eeprom;

669

uint8_t old_eecs = eeprom->eecs;

670

uint8_t old_eesk = eeprom->eesk;

671

672

eeprom->eecs = eecs;

673

eeprom->eesk = eesk;

674

eeprom->eedi = eedi;

675

676

DPRINTF("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n", eeprom->eecs,

677

eeprom->eesk, eeprom->eedi, eeprom->eedo);

678

679

if (!old_eecs && eecs)

680

{

681

/* Synchronize start */

682

eeprom->tick = 0;

683

eeprom->input = 0;

684

eeprom->output = 0;

685

eeprom->mode = Chip9346_enter_command_mode;

686

687

DPRINTF("=== eeprom: begin access, enter command mode\n");

688

}

689

690

if (!eecs)

691

{

692

DPRINTF("=== eeprom: end access\n");

693

return;

694

}

695

696

if (!old_eesk && eesk)

697

{

698

/* SK front rules */

699

prom9346_shift_clock(eeprom);

700

}

701

}

702

703

static void rtl8139_update_irq(RTL8139State *s)

704

{

705

int isr;

706

isr = (s->IntrStatus & s->IntrMask) & 0xffff;

707

708

DPRINTF("Set IRQ to %d (%04x %04x)\n", isr ? 1 : 0, s->IntrStatus,

709

s->IntrMask);

710

711

qemu_set_irq(s->dev.irq[0], (isr != 0));

712

}

713

714

#define POLYNOMIAL 0x04c11db6

715

716

/* From FreeBSD */

717

/* XXX: optimize */

718

static int compute_mcast_idx(const uint8_t *ep)

719

{

720

uint32_t crc;

721

int carry, i, j;

722

uint8_t b;

723

724

crc = 0xffffffff;

725

for (i = 0; i < 6; i++) {

726

b = *ep++;

727

for (j = 0; j < 8; j++) {

728

carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);

729

crc <<= 1;

730

b >>= 1;

731

if (carry)

732

crc = ((crc ^ POLYNOMIAL) | carry);

733

}

734

}

735

return (crc >> 26);

736

}

737

738

static int rtl8139_RxWrap(RTL8139State *s)

739

{

740

/* wrapping enabled; assume 1.5k more buffer space if size < 65536 */

741

return (s->RxConfig & (1 << 7));

742

}

743

744

static int rtl8139_receiver_enabled(RTL8139State *s)

745

{

746

return s->bChipCmdState & CmdRxEnb;

747

}

748

749

static int rtl8139_transmitter_enabled(RTL8139State *s)

750

{

751

return s->bChipCmdState & CmdTxEnb;

752

}

753

754

static int rtl8139_cp_receiver_enabled(RTL8139State *s)

755

{

756

return s->CpCmd & CPlusRxEnb;

757

}

758

759

static int rtl8139_cp_transmitter_enabled(RTL8139State *s)

760

{

761

return s->CpCmd & CPlusTxEnb;

762

}

763

764

static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size)

765

{

766

if (s->RxBufAddr + size > s->RxBufferSize)

767

{

768

int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize);

769

770

/* write packet data */

771

if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s)))

772

{

773

DPRINTF(">>> rx packet wrapped in buffer at %d\n", size - wrapped);

774

775

if (size > wrapped)

776

{

777

pci_dma_write(&s->dev, s->RxBuf + s->RxBufAddr,

778

buf, size-wrapped);

779

}

780

781

/* reset buffer pointer */

782

s->RxBufAddr = 0;

783

784

pci_dma_write(&s->dev, s->RxBuf + s->RxBufAddr,

785

buf + (size-wrapped), wrapped);

786

787

s->RxBufAddr = wrapped;

788

789

return;

790

}

791

}

792

793

/* non-wrapping path or overwrapping enabled */

794

pci_dma_write(&s->dev, s->RxBuf + s->RxBufAddr, buf, size);

795

796

s->RxBufAddr += size;

797

}

798

799

#define MIN_BUF_SIZE 60

800

static inline dma_addr_t rtl8139_addr64(uint32_t low, uint32_t high)

801

{

802

#if TARGET_PHYS_ADDR_BITS > 32

803

return low | ((target_phys_addr_t)high << 32);

804

#else

805

return low;

806

#endif

807

}

808

809

static int rtl8139_can_receive(VLANClientState *nc)

810

{

811

RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;

812

int avail;

813

814

/* Receive (drop) packets if card is disabled. */

815

if (!s->clock_enabled)

816

return 1;

817

if (!rtl8139_receiver_enabled(s))

818

return 1;

819

820

if (rtl8139_cp_receiver_enabled(s)) {

821

/* ??? Flow control not implemented in c+ mode.

822

This is a hack to work around slirp deficiencies anyway. */

823

return 1;

824

} else {

825

avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr,

826

s->RxBufferSize);

827

return (avail == 0 || avail >= 1514);

828

}

829

}

830

831

static ssize_t rtl8139_do_receive(VLANClientState *nc, const uint8_t *buf, size_t size_, int do_interrupt)

832

{

833

RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;

834

/* size is the length of the buffer passed to the driver */

835

int size = size_;

836

const uint8_t *dot1q_buf = NULL;

837

838

uint32_t packet_header = 0;

839

840

uint8_t buf1[MIN_BUF_SIZE + VLAN_HLEN];

841

static const uint8_t broadcast_macaddr[6] =

842

{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };

843

844

DPRINTF(">>> received len=%d\n", size);

845

846

/* test if board clock is stopped */

847

if (!s->clock_enabled)

848

{

849

DPRINTF("stopped ==========================\n");

850

return -1;

851

}

852

853

/* first check if receiver is enabled */

854

855

if (!rtl8139_receiver_enabled(s))

856

{

857

DPRINTF("receiver disabled ================\n");

858

return -1;

859

}

860

861

/* XXX: check this */

862

if (s->RxConfig & AcceptAllPhys) {

863

/* promiscuous: receive all */

864

DPRINTF(">>> packet received in promiscuous mode\n");

865

866

} else {

867

if (!memcmp(buf, broadcast_macaddr, 6)) {

868

/* broadcast address */

869

if (!(s->RxConfig & AcceptBroadcast))

870

{

871

DPRINTF(">>> broadcast packet rejected\n");

872

873

/* update tally counter */

874

++s->tally_counters.RxERR;

875

876

return size;

877

}

878

879

packet_header |= RxBroadcast;

880

881

DPRINTF(">>> broadcast packet received\n");

882

883

/* update tally counter */

884

++s->tally_counters.RxOkBrd;

885

886

} else if (buf[0] & 0x01) {

887

/* multicast */

888

if (!(s->RxConfig & AcceptMulticast))

889

{

890

DPRINTF(">>> multicast packet rejected\n");

891

892

/* update tally counter */

893

++s->tally_counters.RxERR;

894

895

return size;

896

}

897

898

int mcast_idx = compute_mcast_idx(buf);

899

900

if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))

901

{

902

DPRINTF(">>> multicast address mismatch\n");

903

904

/* update tally counter */

905

++s->tally_counters.RxERR;

906

907

return size;

908

}

909

910

packet_header |= RxMulticast;

911

912

DPRINTF(">>> multicast packet received\n");

913

914

/* update tally counter */

915

++s->tally_counters.RxOkMul;

916

917

} else if (s->phys[0] == buf[0] &&

918

s->phys[1] == buf[1] &&

919

s->phys[2] == buf[2] &&

920

s->phys[3] == buf[3] &&

921

s->phys[4] == buf[4] &&

922

s->phys[5] == buf[5]) {

923

/* match */

924

if (!(s->RxConfig & AcceptMyPhys))

925

{

926

DPRINTF(">>> rejecting physical address matching packet\n");

927

928

/* update tally counter */

929

++s->tally_counters.RxERR;

930

931

return size;

932

}

933

934

packet_header |= RxPhysical;

935

936

DPRINTF(">>> physical address matching packet received\n");

937

938

/* update tally counter */

939

++s->tally_counters.RxOkPhy;

940

941

} else {

942

943

DPRINTF(">>> unknown packet\n");

944

945

/* update tally counter */

946

++s->tally_counters.RxERR;

947

948

return size;

949

}

950

}

951

952

/* if too small buffer, then expand it

953

* Include some tailroom in case a vlan tag is later removed. */

954

if (size < MIN_BUF_SIZE + VLAN_HLEN) {

955

memcpy(buf1, buf, size);

956

memset(buf1 + size, 0, MIN_BUF_SIZE + VLAN_HLEN - size);

957

buf = buf1;

958

if (size < MIN_BUF_SIZE) {

959

size = MIN_BUF_SIZE;

960

}

961

}

962

963

if (rtl8139_cp_receiver_enabled(s))

964

{

965

DPRINTF("in C+ Rx mode ================\n");

966

967

/* begin C+ receiver mode */

968

969

/* w0 ownership flag */

970

#define CP_RX_OWN (1<<31)

971

/* w0 end of ring flag */

972

#define CP_RX_EOR (1<<30)

973

/* w0 bits 0...12 : buffer size */

974

#define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1)

975

/* w1 tag available flag */

976

#define CP_RX_TAVA (1<<16)

977

/* w1 bits 0...15 : VLAN tag */

978

#define CP_RX_VLAN_TAG_MASK ((1<<16) - 1)

979

/* w2 low 32bit of Rx buffer ptr */

980

/* w3 high 32bit of Rx buffer ptr */

981

982

int descriptor = s->currCPlusRxDesc;

983

dma_addr_t cplus_rx_ring_desc;

984

985

cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI);

986

cplus_rx_ring_desc += 16 * descriptor;

987

988

DPRINTF("+++ C+ mode reading RX descriptor %d from host memory at "

989

"%08x %08x = "DMA_ADDR_FMT"\n", descriptor, s->RxRingAddrHI,

990

s->RxRingAddrLO, cplus_rx_ring_desc);

991

992

uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI;

993

994

pci_dma_read(&s->dev, cplus_rx_ring_desc, (uint8_t *)&val, 4);

995

rxdw0 = le32_to_cpu(val);

996

pci_dma_read(&s->dev, cplus_rx_ring_desc+4, (uint8_t *)&val, 4);

997

rxdw1 = le32_to_cpu(val);

998

pci_dma_read(&s->dev, cplus_rx_ring_desc+8, (uint8_t *)&val, 4);

999

rxbufLO = le32_to_cpu(val);

1000

pci_dma_read(&s->dev, cplus_rx_ring_desc+12, (uint8_t *)&val, 4);

1001

rxbufHI = le32_to_cpu(val);

1002

1003

DPRINTF("+++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",

1004

descriptor, rxdw0, rxdw1, rxbufLO, rxbufHI);

1005

1006

if (!(rxdw0 & CP_RX_OWN))

1007

{

1008

DPRINTF("C+ Rx mode : descriptor %d is owned by host\n",

1009

descriptor);

1010

1011

s->IntrStatus |= RxOverflow;

1012

++s->RxMissed;

1013

1014

/* update tally counter */

1015

++s->tally_counters.RxERR;

1016

++s->tally_counters.MissPkt;

1017

1018

rtl8139_update_irq(s);

1019

return size_;

1020

}

1021

1022

uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK;

1023

1024

/* write VLAN info to descriptor variables. */

1025

if (s->CpCmd & CPlusRxVLAN && be16_to_cpup((uint16_t *)

1026

&buf[ETHER_ADDR_LEN * 2]) == ETH_P_8021Q) {

1027

dot1q_buf = &buf[ETHER_ADDR_LEN * 2];

1028

size -= VLAN_HLEN;

1029

/* if too small buffer, use the tailroom added duing expansion */

1030

if (size < MIN_BUF_SIZE) {

1031

size = MIN_BUF_SIZE;

1032

}

1033

1034

rxdw1 &= ~CP_RX_VLAN_TAG_MASK;

1035

/* BE + ~le_to_cpu()~ + cpu_to_le() = BE */

1036

rxdw1 |= CP_RX_TAVA | le16_to_cpup((uint16_t *)

1037

&dot1q_buf[ETHER_TYPE_LEN]);

1038

1039

DPRINTF("C+ Rx mode : extracted vlan tag with tci: ""%u\n",

1040

be16_to_cpup((uint16_t *)&dot1q_buf[ETHER_TYPE_LEN]));

1041

} else {

1042

/* reset VLAN tag flag */

1043

rxdw1 &= ~CP_RX_TAVA;

1044

}

1045

1046

/* TODO: scatter the packet over available receive ring descriptors space */

1047

1048

if (size+4 > rx_space)

1049

{

1050

DPRINTF("C+ Rx mode : descriptor %d size %d received %d + 4\n",

1051

descriptor, rx_space, size);

1052

1053

s->IntrStatus |= RxOverflow;

1054

++s->RxMissed;

1055

1056

/* update tally counter */

1057

++s->tally_counters.RxERR;

1058

++s->tally_counters.MissPkt;

1059

1060

rtl8139_update_irq(s);

1061

return size_;

1062

}

1063

1064

dma_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI);

1065

1066

/* receive/copy to target memory */

1067

if (dot1q_buf) {

1068

pci_dma_write(&s->dev, rx_addr, buf, 2 * ETHER_ADDR_LEN);

1069

pci_dma_write(&s->dev, rx_addr + 2 * ETHER_ADDR_LEN,

1070

buf + 2 * ETHER_ADDR_LEN + VLAN_HLEN,

1071

size - 2 * ETHER_ADDR_LEN);

1072

} else {

1073

pci_dma_write(&s->dev, rx_addr, buf, size);

1074

}

1075

1076

if (s->CpCmd & CPlusRxChkSum)

1077

{

1078

/* do some packet checksumming */

1079

}

1080

1081

/* write checksum */

1082

val = cpu_to_le32(crc32(0, buf, size_));

1083

pci_dma_write(&s->dev, rx_addr+size, (uint8_t *)&val, 4);

1084

1085

/* first segment of received packet flag */

1086

#define CP_RX_STATUS_FS (1<<29)

1087

/* last segment of received packet flag */

1088

#define CP_RX_STATUS_LS (1<<28)

1089

/* multicast packet flag */

1090

#define CP_RX_STATUS_MAR (1<<26)

1091

/* physical-matching packet flag */

1092

#define CP_RX_STATUS_PAM (1<<25)

1093

/* broadcast packet flag */

1094

#define CP_RX_STATUS_BAR (1<<24)

1095

/* runt packet flag */

1096

#define CP_RX_STATUS_RUNT (1<<19)

1097

/* crc error flag */

1098

#define CP_RX_STATUS_CRC (1<<18)

1099

/* IP checksum error flag */

1100

#define CP_RX_STATUS_IPF (1<<15)

1101

/* UDP checksum error flag */

1102

#define CP_RX_STATUS_UDPF (1<<14)

1103

/* TCP checksum error flag */

1104

#define CP_RX_STATUS_TCPF (1<<13)

1105

1106

/* transfer ownership to target */

1107

rxdw0 &= ~CP_RX_OWN;

1108

1109

/* set first segment bit */

1110

rxdw0 |= CP_RX_STATUS_FS;

1111

1112

/* set last segment bit */

1113

rxdw0 |= CP_RX_STATUS_LS;

1114

1115

/* set received packet type flags */

1116

if (packet_header & RxBroadcast)

1117

rxdw0 |= CP_RX_STATUS_BAR;

1118

if (packet_header & RxMulticast)

1119

rxdw0 |= CP_RX_STATUS_MAR;

1120

if (packet_header & RxPhysical)

1121

rxdw0 |= CP_RX_STATUS_PAM;

1122

1123

/* set received size */

1124

rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK;

1125

rxdw0 |= (size+4);

1126

1127

/* update ring data */

1128

val = cpu_to_le32(rxdw0);

1129

pci_dma_write(&s->dev, cplus_rx_ring_desc, (uint8_t *)&val, 4);

1130

val = cpu_to_le32(rxdw1);

1131

pci_dma_write(&s->dev, cplus_rx_ring_desc+4, (uint8_t *)&val, 4);

1132

1133

/* update tally counter */

1134

++s->tally_counters.RxOk;

1135

1136

/* seek to next Rx descriptor */

1137

if (rxdw0 & CP_RX_EOR)

1138

{

1139

s->currCPlusRxDesc = 0;

1140

}

1141

else

1142

{

1143

++s->currCPlusRxDesc;

1144

}

1145

1146

DPRINTF("done C+ Rx mode ----------------\n");

1147

1148

}

1149

else

1150

{

1151

DPRINTF("in ring Rx mode ================\n");

1152

1153

/* begin ring receiver mode */

1154

int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize);

1155

1156

/* if receiver buffer is empty then avail == 0 */

1157

1158

if (avail != 0 && size + 8 >= avail)

1159

{

1160

DPRINTF("rx overflow: rx buffer length %d head 0x%04x "

1161

"read 0x%04x === available 0x%04x need 0x%04x\n",

1162

s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8);

1163

1164

s->IntrStatus |= RxOverflow;

1165

++s->RxMissed;

1166

rtl8139_update_irq(s);

1167

return size_;

1168

}

1169

1170

packet_header |= RxStatusOK;

1171

1172

packet_header |= (((size+4) << 16) & 0xffff0000);

1173

1174

/* write header */

1175

uint32_t val = cpu_to_le32(packet_header);

1176

1177

rtl8139_write_buffer(s, (uint8_t *)&val, 4);

1178

1179

rtl8139_write_buffer(s, buf, size);

1180

1181

/* write checksum */

1182

val = cpu_to_le32(crc32(0, buf, size));

1183

rtl8139_write_buffer(s, (uint8_t *)&val, 4);

1184

1185

/* correct buffer write pointer */

1186

s->RxBufAddr = MOD2((s->RxBufAddr + 3) & ~0x3, s->RxBufferSize);

1187

1188

/* now we can signal we have received something */

1189

1190

DPRINTF("received: rx buffer length %d head 0x%04x read 0x%04x\n",

1191

s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);

1192

}

1193

1194

s->IntrStatus |= RxOK;

1195

1196

if (do_interrupt)

1197

{

1198

rtl8139_update_irq(s);

1199

}

1200

1201

return size_;

1202

}

1203

1204

static ssize_t rtl8139_receive(VLANClientState *nc, const uint8_t *buf, size_t size)

1205

{

1206

return rtl8139_do_receive(nc, buf, size, 1);

1207

}

1208

1209

static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize)

1210

{

1211

s->RxBufferSize = bufferSize;

1212

s->RxBufPtr = 0;

1213

s->RxBufAddr = 0;

1214

}

1215

1216

static void rtl8139_reset(DeviceState *d)

1217

{

1218

RTL8139State *s = container_of(d, RTL8139State, dev.qdev);

1219

int i;

1220

1221

/* restore MAC address */

1222

memcpy(s->phys, s->conf.macaddr.a, 6);

1223

1224

/* reset interrupt mask */

1225

s->IntrStatus = 0;

1226

s->IntrMask = 0;

1227

1228

rtl8139_update_irq(s);

1229

1230

/* mark all status registers as owned by host */

1231

for (i = 0; i < 4; ++i)

1232

{

1233

s->TxStatus[i] = TxHostOwns;

1234

}

1235

1236

s->currTxDesc = 0;

1237

s->currCPlusRxDesc = 0;

1238

s->currCPlusTxDesc = 0;

1239

1240

s->RxRingAddrLO = 0;

1241

s->RxRingAddrHI = 0;

1242

1243

s->RxBuf = 0;

1244

1245

rtl8139_reset_rxring(s, 8192);

1246

1247

/* ACK the reset */

1248

s->TxConfig = 0;

1249

1250

#if 0

1251

// s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk

1252

s->clock_enabled = 0;

1253

#else

1254

s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake

1255

s->clock_enabled = 1;

1256

#endif

1257

1258

s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */;

1259

1260

/* set initial state data */

1261

s->Config0 = 0x0; /* No boot ROM */

1262

s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */

1263

s->Config3 = 0x1; /* fast back-to-back compatible */

1264

s->Config5 = 0x0;

1265

1266

s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD;

1267

1268

s->CpCmd = 0x0; /* reset C+ mode */

1269

s->cplus_enabled = 0;

1270

1271

1272

// s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation

1273

// s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex

1274

s->BasicModeCtrl = 0x1000; // autonegotiation

1275

1276

s->BasicModeStatus = 0x7809;

1277

//s->BasicModeStatus |= 0x0040; /* UTP medium */

1278

s->BasicModeStatus |= 0x0020; /* autonegotiation completed */

1279

s->BasicModeStatus |= 0x0004; /* link is up */

1280

1281

s->NWayAdvert = 0x05e1; /* all modes, full duplex */

1282

s->NWayLPAR = 0x05e1; /* all modes, full duplex */

1283

s->NWayExpansion = 0x0001; /* autonegotiation supported */

1284

1285

/* also reset timer and disable timer interrupt */

1286

s->TCTR = 0;

1287

s->TimerInt = 0;

1288

s->TCTR_base = 0;

1289

1290

/* reset tally counters */

1291

RTL8139TallyCounters_clear(&s->tally_counters);

1292

}

1293

1294

static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters)

1295

{

1296

counters->TxOk = 0;

1297

counters->RxOk = 0;

1298

counters->TxERR = 0;

1299

counters->RxERR = 0;

1300

counters->MissPkt = 0;

1301

counters->FAE = 0;

1302

counters->Tx1Col = 0;

1303

counters->TxMCol = 0;

1304

counters->RxOkPhy = 0;

1305

counters->RxOkBrd = 0;

1306

counters->RxOkMul = 0;

1307

counters->TxAbt = 0;

1308

counters->TxUndrn = 0;

1309

}

1310

1311

static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr)

1312

{

1313

RTL8139TallyCounters *tally_counters = &s->tally_counters;

1314

uint16_t val16;

1315

uint32_t val32;

1316

uint64_t val64;

1317

1318

val64 = cpu_to_le64(tally_counters->TxOk);

1319

pci_dma_write(&s->dev, tc_addr + 0, (uint8_t *)&val64, 8);

1320

1321

val64 = cpu_to_le64(tally_counters->RxOk);

1322

pci_dma_write(&s->dev, tc_addr + 8, (uint8_t *)&val64, 8);

1323

1324

val64 = cpu_to_le64(tally_counters->TxERR);

1325

pci_dma_write(&s->dev, tc_addr + 16, (uint8_t *)&val64, 8);

1326

1327

val32 = cpu_to_le32(tally_counters->RxERR);

1328

pci_dma_write(&s->dev, tc_addr + 24, (uint8_t *)&val32, 4);

1329

1330

val16 = cpu_to_le16(tally_counters->MissPkt);

1331

pci_dma_write(&s->dev, tc_addr + 28, (uint8_t *)&val16, 2);

1332

1333

val16 = cpu_to_le16(tally_counters->FAE);

1334

pci_dma_write(&s->dev, tc_addr + 30, (uint8_t *)&val16, 2);

1335

1336

val32 = cpu_to_le32(tally_counters->Tx1Col);

1337

pci_dma_write(&s->dev, tc_addr + 32, (uint8_t *)&val32, 4);

1338

1339

val32 = cpu_to_le32(tally_counters->TxMCol);

1340

pci_dma_write(&s->dev, tc_addr + 36, (uint8_t *)&val32, 4);

1341

1342

val64 = cpu_to_le64(tally_counters->RxOkPhy);

1343

pci_dma_write(&s->dev, tc_addr + 40, (uint8_t *)&val64, 8);

1344

1345

val64 = cpu_to_le64(tally_counters->RxOkBrd);

1346

pci_dma_write(&s->dev, tc_addr + 48, (uint8_t *)&val64, 8);

1347

1348

val32 = cpu_to_le32(tally_counters->RxOkMul);

1349

pci_dma_write(&s->dev, tc_addr + 56, (uint8_t *)&val32, 4);

1350

1351

val16 = cpu_to_le16(tally_counters->TxAbt);

1352

pci_dma_write(&s->dev, tc_addr + 60, (uint8_t *)&val16, 2);

1353

1354

val16 = cpu_to_le16(tally_counters->TxUndrn);

1355

pci_dma_write(&s->dev, tc_addr + 62, (uint8_t *)&val16, 2);

1356

}

1357

1358

/* Loads values of tally counters from VM state file */

1359

1360

static const VMStateDescription vmstate_tally_counters = {

1361

.name = "tally_counters",

1362

.version_id = 1,

1363

.minimum_version_id = 1,

1364

.minimum_version_id_old = 1,

1365

.fields = (VMStateField []) {

1366

VMSTATE_UINT64(TxOk, RTL8139TallyCounters),

1367

VMSTATE_UINT64(RxOk, RTL8139TallyCounters),

1368

VMSTATE_UINT64(TxERR, RTL8139TallyCounters),

1369

VMSTATE_UINT32(RxERR, RTL8139TallyCounters),

1370

VMSTATE_UINT16(MissPkt, RTL8139TallyCounters),

1371

VMSTATE_UINT16(FAE, RTL8139TallyCounters),

1372

VMSTATE_UINT32(Tx1Col, RTL8139TallyCounters),

1373

VMSTATE_UINT32(TxMCol, RTL8139TallyCounters),

1374

VMSTATE_UINT64(RxOkPhy, RTL8139TallyCounters),

1375

VMSTATE_UINT64(RxOkBrd, RTL8139TallyCounters),

1376

VMSTATE_UINT16(TxAbt, RTL8139TallyCounters),

1377

VMSTATE_UINT16(TxUndrn, RTL8139TallyCounters),

1378

VMSTATE_END_OF_LIST()

1379

}

1380

};

1381

1382

static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val)

1383

{

1384

val &= 0xff;

1385

1386

DPRINTF("ChipCmd write val=0x%08x\n", val);

1387

1388

if (val & CmdReset)

1389

{

1390

DPRINTF("ChipCmd reset\n");

1391

rtl8139_reset(&s->dev.qdev);

1392

}

1393

if (val & CmdRxEnb)

1394

{

1395

DPRINTF("ChipCmd enable receiver\n");

1396

1397

s->currCPlusRxDesc = 0;

1398

}

1399

if (val & CmdTxEnb)

1400

{

1401

DPRINTF("ChipCmd enable transmitter\n");

1402

1403

s->currCPlusTxDesc = 0;

1404

}

1405

1406

/* mask unwritable bits */

1407

val = SET_MASKED(val, 0xe3, s->bChipCmdState);

1408

1409

/* Deassert reset pin before next read */

1410

val &= ~CmdReset;

1411

1412

s->bChipCmdState = val;

1413

}

1414

1415

static int rtl8139_RxBufferEmpty(RTL8139State *s)

1416

{

1417

int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize);

1418

1419

if (unread != 0)

1420

{

1421

DPRINTF("receiver buffer data available 0x%04x\n", unread);

1422

return 0;

1423

}

1424

1425

DPRINTF("receiver buffer is empty\n");

1426

1427

return 1;

1428

}

1429

1430

static uint32_t rtl8139_ChipCmd_read(RTL8139State *s)

1431

{

1432

uint32_t ret = s->bChipCmdState;

1433

1434

if (rtl8139_RxBufferEmpty(s))

1435

ret |= RxBufEmpty;

1436

1437

DPRINTF("ChipCmd read val=0x%04x\n", ret);

1438

1439

return ret;

1440

}

1441

1442

static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val)

1443

{

1444

val &= 0xffff;

1445

1446

DPRINTF("C+ command register write(w) val=0x%04x\n", val);

1447

1448

s->cplus_enabled = 1;

1449

1450

/* mask unwritable bits */

1451

val = SET_MASKED(val, 0xff84, s->CpCmd);

1452

1453

s->CpCmd = val;

1454

}

1455

1456

static uint32_t rtl8139_CpCmd_read(RTL8139State *s)

1457

{

1458

uint32_t ret = s->CpCmd;

1459

1460

DPRINTF("C+ command register read(w) val=0x%04x\n", ret);

1461

1462

return ret;

1463

}

1464

1465

static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val)

1466

{

1467

DPRINTF("C+ IntrMitigate register write(w) val=0x%04x\n", val);

1468

}

1469

1470

static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s)

1471

{

1472

uint32_t ret = 0;

1473

1474

DPRINTF("C+ IntrMitigate register read(w) val=0x%04x\n", ret);

1475

1476

return ret;

1477

}

1478

1479

static int rtl8139_config_writable(RTL8139State *s)

1480

{

1481

if (s->Cfg9346 & Cfg9346_Unlock)

1482

{

1483

return 1;

1484

}

1485

1486

DPRINTF("Configuration registers are write-protected\n");

1487

1488

return 0;

1489

}

1490

1491

static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val)

1492

{

1493

val &= 0xffff;

1494

1495

DPRINTF("BasicModeCtrl register write(w) val=0x%04x\n", val);

1496

1497

/* mask unwritable bits */

1498

uint32_t mask = 0x4cff;

1499

1500

if (1 || !rtl8139_config_writable(s))

1501

{

1502

/* Speed setting and autonegotiation enable bits are read-only */

1503

mask |= 0x3000;

1504

/* Duplex mode setting is read-only */

1505

mask |= 0x0100;

1506

}

1507

1508

val = SET_MASKED(val, mask, s->BasicModeCtrl);

1509

1510

s->BasicModeCtrl = val;

1511

}

1512

1513

static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s)

1514

{

1515

uint32_t ret = s->BasicModeCtrl;

1516

1517

DPRINTF("BasicModeCtrl register read(w) val=0x%04x\n", ret);

1518

1519

return ret;

1520

}

1521

1522

static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val)

1523

{

1524

val &= 0xffff;

1525

1526

DPRINTF("BasicModeStatus register write(w) val=0x%04x\n", val);

1527

1528

/* mask unwritable bits */

1529

val = SET_MASKED(val, 0xff3f, s->BasicModeStatus);

1530

1531

s->BasicModeStatus = val;

1532

}

1533

1534

static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s)

1535

{

1536

uint32_t ret = s->BasicModeStatus;

1537

1538

DPRINTF("BasicModeStatus register read(w) val=0x%04x\n", ret);

1539

1540

return ret;

1541

}

1542

1543

static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val)

1544

{

1545

val &= 0xff;

1546

1547

DPRINTF("Cfg9346 write val=0x%02x\n", val);

1548

1549

/* mask unwritable bits */

1550

val = SET_MASKED(val, 0x31, s->Cfg9346);

1551

1552

uint32_t opmode = val & 0xc0;

1553

uint32_t eeprom_val = val & 0xf;

1554

1555

if (opmode == 0x80) {

1556

/* eeprom access */

1557

int eecs = (eeprom_val & 0x08)?1:0;

1558

int eesk = (eeprom_val & 0x04)?1:0;

1559

int eedi = (eeprom_val & 0x02)?1:0;

1560

prom9346_set_wire(s, eecs, eesk, eedi);

1561

} else if (opmode == 0x40) {

1562

/* Reset. */

1563

val = 0;

1564

rtl8139_reset(&s->dev.qdev);

1565

}

1566

1567

s->Cfg9346 = val;

1568

}

1569

1570

static uint32_t rtl8139_Cfg9346_read(RTL8139State *s)

1571

{

1572

uint32_t ret = s->Cfg9346;

1573

1574

uint32_t opmode = ret & 0xc0;

1575

1576

if (opmode == 0x80)

1577

{

1578

/* eeprom access */

1579

int eedo = prom9346_get_wire(s);

1580

if (eedo)

1581

{

1582

ret |= 0x01;

1583

}

1584

else

1585

{

1586

ret &= ~0x01;

1587

}

1588

}

1589

1590

DPRINTF("Cfg9346 read val=0x%02x\n", ret);

1591

1592

return ret;

1593

}

1594

1595

static void rtl8139_Config0_write(RTL8139State *s, uint32_t val)

1596

{

1597

val &= 0xff;

1598

1599

DPRINTF("Config0 write val=0x%02x\n", val);

1600

1601

if (!rtl8139_config_writable(s)) {

1602

return;

1603

}

1604

1605

/* mask unwritable bits */

1606

val = SET_MASKED(val, 0xf8, s->Config0);

1607

1608

s->Config0 = val;

1609

}

1610

1611

static uint32_t rtl8139_Config0_read(RTL8139State *s)

1612

{

1613

uint32_t ret = s->Config0;

1614

1615

DPRINTF("Config0 read val=0x%02x\n", ret);

1616

1617

return ret;

1618

}

1619

1620

static void rtl8139_Config1_write(RTL8139State *s, uint32_t val)

1621

{

1622

val &= 0xff;

1623

1624

DPRINTF("Config1 write val=0x%02x\n", val);

1625

1626

if (!rtl8139_config_writable(s)) {

1627

return;

1628

}

1629

1630

/* mask unwritable bits */

1631

val = SET_MASKED(val, 0xC, s->Config1);

1632

1633

s->Config1 = val;

1634

}

1635

1636

static uint32_t rtl8139_Config1_read(RTL8139State *s)

1637

{

1638

uint32_t ret = s->Config1;

1639

1640

DPRINTF("Config1 read val=0x%02x\n", ret);

1641

1642

return ret;

1643

}

1644

1645

static void rtl8139_Config3_write(RTL8139State *s, uint32_t val)

1646

{

1647

val &= 0xff;

1648

1649

DPRINTF("Config3 write val=0x%02x\n", val);

1650

1651

if (!rtl8139_config_writable(s)) {

1652

return;

1653

}

1654

1655

/* mask unwritable bits */

1656

val = SET_MASKED(val, 0x8F, s->Config3);

1657

1658

s->Config3 = val;

1659

}

1660

1661

static uint32_t rtl8139_Config3_read(RTL8139State *s)

1662

{

1663

uint32_t ret = s->Config3;

1664

1665

DPRINTF("Config3 read val=0x%02x\n", ret);

1666

1667

return ret;

1668

}

1669

1670

static void rtl8139_Config4_write(RTL8139State *s, uint32_t val)

1671

{

1672

val &= 0xff;

1673

1674

DPRINTF("Config4 write val=0x%02x\n", val);

1675

1676

if (!rtl8139_config_writable(s)) {

1677

return;

1678

}

1679

1680

/* mask unwritable bits */

1681

val = SET_MASKED(val, 0x0a, s->Config4);

1682

1683

s->Config4 = val;

1684

}

1685

1686

static uint32_t rtl8139_Config4_read(RTL8139State *s)

1687

{

1688

uint32_t ret = s->Config4;

1689

1690

DPRINTF("Config4 read val=0x%02x\n", ret);

1691

1692

return ret;

1693

}

1694

1695

static void rtl8139_Config5_write(RTL8139State *s, uint32_t val)

1696

{

1697

val &= 0xff;

1698

1699

DPRINTF("Config5 write val=0x%02x\n", val);

1700

1701

/* mask unwritable bits */

1702

val = SET_MASKED(val, 0x80, s->Config5);

1703

1704

s->Config5 = val;

1705

}

1706

1707

static uint32_t rtl8139_Config5_read(RTL8139State *s)

1708

{

1709

uint32_t ret = s->Config5;

1710

1711

DPRINTF("Config5 read val=0x%02x\n", ret);

1712

1713

return ret;

1714

}

1715

1716

static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val)

1717

{

1718

if (!rtl8139_transmitter_enabled(s))

1719

{

1720

DPRINTF("transmitter disabled; no TxConfig write val=0x%08x\n", val);

1721

return;

1722

}

1723

1724

DPRINTF("TxConfig write val=0x%08x\n", val);

1725

1726

val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig);

1727

1728

s->TxConfig = val;

1729

}

1730

1731

static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val)

1732

{

1733

DPRINTF("RTL8139C TxConfig via write(b) val=0x%02x\n", val);

1734

1735

uint32_t tc = s->TxConfig;

1736

tc &= 0xFFFFFF00;

1737

tc |= (val & 0x000000FF);

1738

rtl8139_TxConfig_write(s, tc);

1739

}

1740

1741

static uint32_t rtl8139_TxConfig_read(RTL8139State *s)

1742

{

1743

uint32_t ret = s->TxConfig;

1744

1745

DPRINTF("TxConfig read val=0x%04x\n", ret);

1746

1747

return ret;

1748

}

1749

1750

static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val)

1751

{

1752

DPRINTF("RxConfig write val=0x%08x\n", val);

1753

1754

/* mask unwritable bits */

1755

val = SET_MASKED(val, 0xf0fc0040, s->RxConfig);

1756

1757

s->RxConfig = val;

1758

1759

/* reset buffer size and read/write pointers */

1760

rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3));

1761

1762

DPRINTF("RxConfig write reset buffer size to %d\n", s->RxBufferSize);

1763

}

1764

1765

static uint32_t rtl8139_RxConfig_read(RTL8139State *s)

1766

{

1767

uint32_t ret = s->RxConfig;

1768

1769

DPRINTF("RxConfig read val=0x%08x\n", ret);

1770

1771

return ret;

1772

}

1773

1774

static void rtl8139_transfer_frame(RTL8139State *s, uint8_t *buf, int size,

1775

int do_interrupt, const uint8_t *dot1q_buf)

1776

{

1777

struct iovec *iov = NULL;

1778

1779

if (!size)

1780

{

1781

DPRINTF("+++ empty ethernet frame\n");

1782

return;

1783

}

1784

1785

if (dot1q_buf && size >= ETHER_ADDR_LEN * 2) {

1786

iov = (struct iovec[3]) {

1787

{ .iov_base = buf, .iov_len = ETHER_ADDR_LEN * 2 },

1788

{ .iov_base = (void *) dot1q_buf, .iov_len = VLAN_HLEN },

1789

{ .iov_base = buf + ETHER_ADDR_LEN * 2,

1790

.iov_len = size - ETHER_ADDR_LEN * 2 },

1791

};

1792

}

1793

1794

if (TxLoopBack == (s->TxConfig & TxLoopBack))

1795

{

1796

size_t buf2_size;

1797

uint8_t *buf2;

1798

1799

if (iov) {

1800

buf2_size = iov_size(iov, 3);

1801

buf2 = g_malloc(buf2_size);

1802

iov_to_buf(iov, 3, buf2, 0, buf2_size);

1803

buf = buf2;

1804

}

1805

1806

DPRINTF("+++ transmit loopback mode\n");

1807

rtl8139_do_receive(&s->nic->nc, buf, size, do_interrupt);

1808

1809

if (iov) {

1810

g_free(buf2);

1811

}

1812

}

1813

else

1814

{

1815

if (iov) {

1816

qemu_sendv_packet(&s->nic->nc, iov, 3);

1817

} else {

1818

qemu_send_packet(&s->nic->nc, buf, size);

1819

}

1820

}

1821

}

1822

1823

static int rtl8139_transmit_one(RTL8139State *s, int descriptor)

1824

{

1825

if (!rtl8139_transmitter_enabled(s))

1826

{

1827

DPRINTF("+++ cannot transmit from descriptor %d: transmitter "

1828

"disabled\n", descriptor);

1829

return 0;

1830

}

1831

1832

if (s->TxStatus[descriptor] & TxHostOwns)

1833

{

1834

DPRINTF("+++ cannot transmit from descriptor %d: owned by host "

1835

"(%08x)\n", descriptor, s->TxStatus[descriptor]);

1836

return 0;

1837

}

1838

1839

DPRINTF("+++ transmitting from descriptor %d\n", descriptor);

1840

1841

int txsize = s->TxStatus[descriptor] & 0x1fff;

1842

uint8_t txbuffer[0x2000];

1843

1844

DPRINTF("+++ transmit reading %d bytes from host memory at 0x%08x\n",

1845

txsize, s->TxAddr[descriptor]);

1846

1847

pci_dma_read(&s->dev, s->TxAddr[descriptor], txbuffer, txsize);

1848

1849

/* Mark descriptor as transferred */

1850

s->TxStatus[descriptor] |= TxHostOwns;

1851

s->TxStatus[descriptor] |= TxStatOK;

1852

1853

rtl8139_transfer_frame(s, txbuffer, txsize, 0, NULL);

1854

1855

DPRINTF("+++ transmitted %d bytes from descriptor %d\n", txsize,

1856

descriptor);

1857

1858

/* update interrupt */

1859

s->IntrStatus |= TxOK;

1860

rtl8139_update_irq(s);

1861

1862

return 1;

1863

}

1864

1865

/* structures and macros for task offloading */

1866

typedef struct ip_header

1867

{

1868

uint8_t ip_ver_len; /* version and header length */

1869

uint8_t ip_tos; /* type of service */

1870

uint16_t ip_len; /* total length */

1871

uint16_t ip_id; /* identification */

1872

uint16_t ip_off; /* fragment offset field */

1873

uint8_t ip_ttl; /* time to live */

1874

uint8_t ip_p; /* protocol */

1875

uint16_t ip_sum; /* checksum */

1876

uint32_t ip_src,ip_dst; /* source and dest address */

1877

} ip_header;

1878

1879

#define IP_HEADER_VERSION_4 4

1880

#define IP_HEADER_VERSION(ip) ((ip->ip_ver_len >> 4)&0xf)

1881

#define IP_HEADER_LENGTH(ip) (((ip->ip_ver_len)&0xf) << 2)

1882

1883

typedef struct tcp_header

1884

{

1885

uint16_t th_sport; /* source port */

1886

uint16_t th_dport; /* destination port */

1887

uint32_t th_seq; /* sequence number */

1888

uint32_t th_ack; /* acknowledgement number */

1889

uint16_t th_offset_flags; /* data offset, reserved 6 bits, TCP protocol flags */

1890

uint16_t th_win; /* window */

1891

uint16_t th_sum; /* checksum */

1892

uint16_t th_urp; /* urgent pointer */

1893

} tcp_header;

1894

1895

typedef struct udp_header

1896

{

1897

uint16_t uh_sport; /* source port */

1898

uint16_t uh_dport; /* destination port */

1899

uint16_t uh_ulen; /* udp length */

1900

uint16_t uh_sum; /* udp checksum */

1901

} udp_header;

1902

1903

typedef struct ip_pseudo_header

1904

{

1905

uint32_t ip_src;

1906

uint32_t ip_dst;

1907

uint8_t zeros;

1908

uint8_t ip_proto;

1909

uint16_t ip_payload;

1910

} ip_pseudo_header;

1911

1912

#define IP_PROTO_TCP 6

1913

#define IP_PROTO_UDP 17

1914

1915

#define TCP_HEADER_DATA_OFFSET(tcp) (((be16_to_cpu(tcp->th_offset_flags) >> 12)&0xf) << 2)

1916

#define TCP_FLAGS_ONLY(flags) ((flags)&0x3f)

1917

#define TCP_HEADER_FLAGS(tcp) TCP_FLAGS_ONLY(be16_to_cpu(tcp->th_offset_flags))

1918

1919

#define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off)))

1920

1921

#define TCP_FLAG_FIN 0x01

1922

#define TCP_FLAG_PUSH 0x08

1923

1924

/* produces ones' complement sum of data */

1925

static uint16_t ones_complement_sum(uint8_t *data, size_t len)

1926

{

1927

uint32_t result = 0;

1928

1929

for (; len > 1; data+=2, len-=2)

1930

{

1931

result += *(uint16_t*)data;

1932

}

1933

1934

/* add the remainder byte */

1935

if (len)

1936

{

1937

uint8_t odd[2] = {*data, 0};

1938

result += *(uint16_t*)odd;

1939

}

1940

1941

while (result>>16)

1942

result = (result & 0xffff) + (result >> 16);

1943

1944

return result;

1945

}

1946

1947

static uint16_t ip_checksum(void *data, size_t len)

1948

{

1949

return ~ones_complement_sum((uint8_t*)data, len);

1950

}

1951

1952

static int rtl8139_cplus_transmit_one(RTL8139State *s)

1953

{

1954

if (!rtl8139_transmitter_enabled(s))

1955

{

1956

DPRINTF("+++ C+ mode: transmitter disabled\n");

1957

return 0;

1958

}

1959

1960

if (!rtl8139_cp_transmitter_enabled(s))

1961

{

1962

DPRINTF("+++ C+ mode: C+ transmitter disabled\n");

1963

return 0 ;

1964

}

1965

1966

int descriptor = s->currCPlusTxDesc;

1967

1968

dma_addr_t cplus_tx_ring_desc = rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]);

1969

1970

/* Normal priority ring */

1971

cplus_tx_ring_desc += 16 * descriptor;

1972

1973

DPRINTF("+++ C+ mode reading TX descriptor %d from host memory at "

1974

"%08x %08x = 0x"DMA_ADDR_FMT"\n", descriptor, s->TxAddr[1],

1975

s->TxAddr[0], cplus_tx_ring_desc);

1976

1977

uint32_t val, txdw0,txdw1,txbufLO,txbufHI;

1978

1979

pci_dma_read(&s->dev, cplus_tx_ring_desc, (uint8_t *)&val, 4);

1980

txdw0 = le32_to_cpu(val);

1981

pci_dma_read(&s->dev, cplus_tx_ring_desc+4, (uint8_t *)&val, 4);

1982

txdw1 = le32_to_cpu(val);

1983

pci_dma_read(&s->dev, cplus_tx_ring_desc+8, (uint8_t *)&val, 4);

1984

txbufLO = le32_to_cpu(val);

1985

pci_dma_read(&s->dev, cplus_tx_ring_desc+12, (uint8_t *)&val, 4);

1986

txbufHI = le32_to_cpu(val);

1987

1988

DPRINTF("+++ C+ mode TX descriptor %d %08x %08x %08x %08x\n", descriptor,

1989

txdw0, txdw1, txbufLO, txbufHI);

1990

1991

/* w0 ownership flag */

1992

#define CP_TX_OWN (1<<31)

1993

/* w0 end of ring flag */

1994

#define CP_TX_EOR (1<<30)

1995

/* first segment of received packet flag */

1996

#define CP_TX_FS (1<<29)

1997

/* last segment of received packet flag */

1998

#define CP_TX_LS (1<<28)

1999

/* large send packet flag */

2000

#define CP_TX_LGSEN (1<<27)

2001

/* large send MSS mask, bits 16...25 */

2002

#define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1)

2003

2004

/* IP checksum offload flag */

2005

#define CP_TX_IPCS (1<<18)

2006

/* UDP checksum offload flag */

2007

#define CP_TX_UDPCS (1<<17)

2008

/* TCP checksum offload flag */

2009

#define CP_TX_TCPCS (1<<16)

2010

2011

/* w0 bits 0...15 : buffer size */

2012

#define CP_TX_BUFFER_SIZE (1<<16)

2013

#define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1)

2014

/* w1 add tag flag */

2015

#define CP_TX_TAGC (1<<17)

2016

/* w1 bits 0...15 : VLAN tag (big endian) */

2017

#define CP_TX_VLAN_TAG_MASK ((1<<16) - 1)

2018

/* w2 low 32bit of Rx buffer ptr */

2019

/* w3 high 32bit of Rx buffer ptr */

2020

2021

/* set after transmission */

2022

/* FIFO underrun flag */

2023

#define CP_TX_STATUS_UNF (1<<25)

2024

/* transmit error summary flag, valid if set any of three below */

2025

#define CP_TX_STATUS_TES (1<<23)

2026

/* out-of-window collision flag */

2027

#define CP_TX_STATUS_OWC (1<<22)

2028

/* link failure flag */

2029

#define CP_TX_STATUS_LNKF (1<<21)

2030

/* excessive collisions flag */

2031

#define CP_TX_STATUS_EXC (1<<20)

2032

2033

if (!(txdw0 & CP_TX_OWN))

2034

{

2035

DPRINTF("C+ Tx mode : descriptor %d is owned by host\n", descriptor);

2036

return 0 ;

2037

}

2038

2039

DPRINTF("+++ C+ Tx mode : transmitting from descriptor %d\n", descriptor);

2040

2041

if (txdw0 & CP_TX_FS)

2042

{

2043

DPRINTF("+++ C+ Tx mode : descriptor %d is first segment "

2044

"descriptor\n", descriptor);

2045

2046

/* reset internal buffer offset */

2047

s->cplus_txbuffer_offset = 0;

2048

}

2049

2050

int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK;

2051

dma_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI);

2052

2053

/* make sure we have enough space to assemble the packet */

2054

if (!s->cplus_txbuffer)

2055

{

2056

s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE;

2057

s->cplus_txbuffer = g_malloc(s->cplus_txbuffer_len);

2058

s->cplus_txbuffer_offset = 0;

2059

2060

DPRINTF("+++ C+ mode transmission buffer allocated space %d\n",

2061

s->cplus_txbuffer_len);

2062

}

2063

2064

while (s->cplus_txbuffer && s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len)

2065

{

2066

s->cplus_txbuffer_len += CP_TX_BUFFER_SIZE;

2067

s->cplus_txbuffer = g_realloc(s->cplus_txbuffer, s->cplus_txbuffer_len);

2068

2069

DPRINTF("+++ C+ mode transmission buffer space changed to %d\n",

2070

s->cplus_txbuffer_len);

2071

}

2072

2073

if (!s->cplus_txbuffer)

2074

{

2075

/* out of memory */

2076

2077

DPRINTF("+++ C+ mode transmiter failed to reallocate %d bytes\n",

2078

s->cplus_txbuffer_len);

2079

2080

/* update tally counter */

2081

++s->tally_counters.TxERR;

2082

++s->tally_counters.TxAbt;

2083

2084

return 0;

2085

}

2086

2087

/* append more data to the packet */

2088

2089

DPRINTF("+++ C+ mode transmit reading %d bytes from host memory at "

2090

DMA_ADDR_FMT" to offset %d\n", txsize, tx_addr,

2091

s->cplus_txbuffer_offset);

2092

2093

pci_dma_read(&s->dev, tx_addr,

2094

s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize);

2095

s->cplus_txbuffer_offset += txsize;

2096

2097

/* seek to next Rx descriptor */

2098

if (txdw0 & CP_TX_EOR)

2099

{

2100

s->currCPlusTxDesc = 0;

2101

}

2102

else

2103

{

2104

++s->currCPlusTxDesc;

2105

if (s->currCPlusTxDesc >= 64)

2106

s->currCPlusTxDesc = 0;

2107

}

2108

2109

/* transfer ownership to target */

2110

txdw0 &= ~CP_RX_OWN;

2111

2112

/* reset error indicator bits */

2113

txdw0 &= ~CP_TX_STATUS_UNF;

2114

txdw0 &= ~CP_TX_STATUS_TES;

2115

txdw0 &= ~CP_TX_STATUS_OWC;

2116

txdw0 &= ~CP_TX_STATUS_LNKF;

2117

txdw0 &= ~CP_TX_STATUS_EXC;

2118

2119

/* update ring data */

2120

val = cpu_to_le32(txdw0);

2121

pci_dma_write(&s->dev, cplus_tx_ring_desc, (uint8_t *)&val, 4);

2122

2123

/* Now decide if descriptor being processed is holding the last segment of packet */

2124

if (txdw0 & CP_TX_LS)

2125

{

2126

uint8_t dot1q_buffer_space[VLAN_HLEN];

2127

uint16_t *dot1q_buffer;

2128

2129

DPRINTF("+++ C+ Tx mode : descriptor %d is last segment descriptor\n",

2130

descriptor);

2131

2132

/* can transfer fully assembled packet */

2133

2134

uint8_t *saved_buffer = s->cplus_txbuffer;

2135

int saved_size = s->cplus_txbuffer_offset;

2136

int saved_buffer_len = s->cplus_txbuffer_len;

2137

2138

/* create vlan tag */

2139

if (txdw1 & CP_TX_TAGC) {

2140

/* the vlan tag is in BE byte order in the descriptor

2141

* BE + le_to_cpu() + ~swap()~ = cpu */

2142

DPRINTF("+++ C+ Tx mode : inserting vlan tag with ""tci: %u\n",

2143

bswap16(txdw1 & CP_TX_VLAN_TAG_MASK));

2144

2145

dot1q_buffer = (uint16_t *) dot1q_buffer_space;

2146

dot1q_buffer[0] = cpu_to_be16(ETH_P_8021Q);

2147

/* BE + le_to_cpu() + ~cpu_to_le()~ = BE */

2148

dot1q_buffer[1] = cpu_to_le16(txdw1 & CP_TX_VLAN_TAG_MASK);

2149

} else {

2150

dot1q_buffer = NULL;

2151

}

2152

2153

/* reset the card space to protect from recursive call */

2154

s->cplus_txbuffer = NULL;

2155

s->cplus_txbuffer_offset = 0;

2156

s->cplus_txbuffer_len = 0;

2157

2158

if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN))

2159

{

2160

DPRINTF("+++ C+ mode offloaded task checksum\n");

2161

2162

/* ip packet header */

2163

ip_header *ip = NULL;

2164

int hlen = 0;

2165

uint8_t ip_protocol = 0;

2166

uint16_t ip_data_len = 0;

2167

2168

uint8_t *eth_payload_data = NULL;

2169

size_t eth_payload_len = 0;

2170

2171

int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12));

2172

if (proto == ETH_P_IP)

2173

{

2174

DPRINTF("+++ C+ mode has IP packet\n");

2175

2176

/* not aligned */

2177

eth_payload_data = saved_buffer + ETH_HLEN;

2178

eth_payload_len = saved_size - ETH_HLEN;

2179

2180

ip = (ip_header*)eth_payload_data;

2181

2182

if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) {

2183

DPRINTF("+++ C+ mode packet has bad IP version %d "

2184

"expected %d\n", IP_HEADER_VERSION(ip),

2185

IP_HEADER_VERSION_4);

2186

ip = NULL;

2187

} else {

2188

hlen = IP_HEADER_LENGTH(ip);

2189

ip_protocol = ip->ip_p;

2190

ip_data_len = be16_to_cpu(ip->ip_len) - hlen;

2191

}

2192

}

2193

2194

if (ip)

2195

{

2196

if (txdw0 & CP_TX_IPCS)

2197

{

2198

DPRINTF("+++ C+ mode need IP checksum\n");

2199

2200

if (hlen<sizeof(ip_header) || hlen>eth_payload_len) {/* min header length */

2201

/* bad packet header len */

2202

/* or packet too short */

2203

}

2204

else

2205

{

2206

ip->ip_sum = 0;

2207

ip->ip_sum = ip_checksum(ip, hlen);

2208

DPRINTF("+++ C+ mode IP header len=%d checksum=%04x\n",

2209

hlen, ip->ip_sum);

2210

}

2211

}

2212

2213

if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP)

2214

{

2215

int large_send_mss = (txdw0 >> 16) & CP_TC_LGSEN_MSS_MASK;

2216

2217

DPRINTF("+++ C+ mode offloaded task TSO MTU=%d IP data %d "

2218

"frame data %d specified MSS=%d\n", ETH_MTU,

2219

ip_data_len, saved_size - ETH_HLEN, large_send_mss);

2220

2221

int tcp_send_offset = 0;

2222

int send_count = 0;

2223

2224

/* maximum IP header length is 60 bytes */

2225

uint8_t saved_ip_header[60];

2226

2227

/* save IP header template; data area is used in tcp checksum calculation */

2228

memcpy(saved_ip_header, eth_payload_data, hlen);

2229

2230

/* a placeholder for checksum calculation routine in tcp case */

2231

uint8_t *data_to_checksum = eth_payload_data + hlen - 12;

2232

// size_t data_to_checksum_len = eth_payload_len - hlen + 12;

2233

2234

/* pointer to TCP header */

2235

tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen);

2236

2237

int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr);

2238

2239

/* ETH_MTU = ip header len + tcp header len + payload */

2240

int tcp_data_len = ip_data_len - tcp_hlen;

2241

int tcp_chunk_size = ETH_MTU - hlen - tcp_hlen;

2242

2243

DPRINTF("+++ C+ mode TSO IP data len %d TCP hlen %d TCP "

2244

"data len %d TCP chunk size %d\n", ip_data_len,

2245

tcp_hlen, tcp_data_len, tcp_chunk_size);

2246

2247

/* note the cycle below overwrites IP header data,

2248

but restores it from saved_ip_header before sending packet */

2249

2250

int is_last_frame = 0;

2251

2252

for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += tcp_chunk_size)

2253

{

2254

uint16_t chunk_size = tcp_chunk_size;

2255

2256

/* check if this is the last frame */

2257

if (tcp_send_offset + tcp_chunk_size >= tcp_data_len)

2258

{

2259

is_last_frame = 1;

2260

chunk_size = tcp_data_len - tcp_send_offset;

2261

}

2262

2263

DPRINTF("+++ C+ mode TSO TCP seqno %08x\n",

2264

be32_to_cpu(p_tcp_hdr->th_seq));

2265

2266

/* add 4 TCP pseudoheader fields */

2267

/* copy IP source and destination fields */

2268

memcpy(data_to_checksum, saved_ip_header + 12, 8);

2269

2270

DPRINTF("+++ C+ mode TSO calculating TCP checksum for "

2271

"packet with %d bytes data\n", tcp_hlen +

2272

chunk_size);

2273

2274

if (tcp_send_offset)

2275

{

2276

memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size);

2277

}

2278

2279

/* keep PUSH and FIN flags only for the last frame */

2280

if (!is_last_frame)

2281

{

2282

TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TCP_FLAG_PUSH|TCP_FLAG_FIN);

2283

}

2284

2285

/* recalculate TCP checksum */

2286

ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;

2287

p_tcpip_hdr->zeros = 0;

2288

p_tcpip_hdr->ip_proto = IP_PROTO_TCP;

2289

p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size);

2290

2291

p_tcp_hdr->th_sum = 0;

2292

2293

int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12);

2294

DPRINTF("+++ C+ mode TSO TCP checksum %04x\n",

2295

tcp_checksum);

2296

2297

p_tcp_hdr->th_sum = tcp_checksum;

2298

2299

/* restore IP header */

2300

memcpy(eth_payload_data, saved_ip_header, hlen);

2301

2302

/* set IP data length and recalculate IP checksum */

2303

ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size);

2304

2305

/* increment IP id for subsequent frames */

2306

ip->ip_id = cpu_to_be16(tcp_send_offset/tcp_chunk_size + be16_to_cpu(ip->ip_id));

2307

2308

ip->ip_sum = 0;

2309

ip->ip_sum = ip_checksum(eth_payload_data, hlen);

2310

DPRINTF("+++ C+ mode TSO IP header len=%d "

2311

"checksum=%04x\n", hlen, ip->ip_sum);

2312

2313

int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size;

2314

DPRINTF("+++ C+ mode TSO transferring packet size "

2315

"%d\n", tso_send_size);

2316

rtl8139_transfer_frame(s, saved_buffer, tso_send_size,

2317

0, (uint8_t *) dot1q_buffer);

2318

2319

/* add transferred count to TCP sequence number */

2320

p_tcp_hdr->th_seq = cpu_to_be32(chunk_size + be32_to_cpu(p_tcp_hdr->th_seq));

2321

++send_count;

2322

}

2323

2324

/* Stop sending this frame */

2325

saved_size = 0;

2326

}

2327

else if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS))

2328

{

2329

DPRINTF("+++ C+ mode need TCP or UDP checksum\n");

2330

2331

/* maximum IP header length is 60 bytes */

2332

uint8_t saved_ip_header[60];

2333

memcpy(saved_ip_header, eth_payload_data, hlen);

2334

2335

uint8_t *data_to_checksum = eth_payload_data + hlen - 12;

2336

// size_t data_to_checksum_len = eth_payload_len - hlen + 12;

2337

2338

/* add 4 TCP pseudoheader fields */

2339

/* copy IP source and destination fields */

2340

memcpy(data_to_checksum, saved_ip_header + 12, 8);

2341

2342

if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP)

2343

{

2344

DPRINTF("+++ C+ mode calculating TCP checksum for "

2345

"packet with %d bytes data\n", ip_data_len);

2346

2347

ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;

2348

p_tcpip_hdr->zeros = 0;

2349

p_tcpip_hdr->ip_proto = IP_PROTO_TCP;

2350

p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len);

2351

2352

tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12);

2353

2354

p_tcp_hdr->th_sum = 0;

2355

2356

int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);

2357

DPRINTF("+++ C+ mode TCP checksum %04x\n",

2358

tcp_checksum);

2359

2360

p_tcp_hdr->th_sum = tcp_checksum;

2361

}

2362

else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP)

2363

{

2364

DPRINTF("+++ C+ mode calculating UDP checksum for "

2365

"packet with %d bytes data\n", ip_data_len);

2366

2367

ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum;

2368

p_udpip_hdr->zeros = 0;

2369

p_udpip_hdr->ip_proto = IP_PROTO_UDP;

2370

p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len);

2371

2372

udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12);

2373

2374

p_udp_hdr->uh_sum = 0;

2375

2376

int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);

2377

DPRINTF("+++ C+ mode UDP checksum %04x\n",

2378

udp_checksum);

2379

2380

p_udp_hdr->uh_sum = udp_checksum;

2381

}

2382

2383

/* restore IP header */

2384

memcpy(eth_payload_data, saved_ip_header, hlen);

2385

}

2386

}

2387

}

2388

2389

/* update tally counter */

2390

++s->tally_counters.TxOk;

2391

2392

DPRINTF("+++ C+ mode transmitting %d bytes packet\n", saved_size);

2393

2394

rtl8139_transfer_frame(s, saved_buffer, saved_size, 1,

2395

(uint8_t *) dot1q_buffer);

2396

2397

/* restore card space if there was no recursion and reset offset */

2398

if (!s->cplus_txbuffer)

2399

{

2400

s->cplus_txbuffer = saved_buffer;

2401

s->cplus_txbuffer_len = saved_buffer_len;

2402

s->cplus_txbuffer_offset = 0;

2403

}

2404

else

2405

{

2406

g_free(saved_buffer);

2407

}

2408

}

2409

else

2410

{

2411

DPRINTF("+++ C+ mode transmission continue to next descriptor\n");

2412

}

2413

2414

return 1;

2415

}

2416

2417

static void rtl8139_cplus_transmit(RTL8139State *s)

2418

{

2419

int txcount = 0;

2420

2421

while (rtl8139_cplus_transmit_one(s))

2422

{

2423

++txcount;

2424

}

2425

2426

/* Mark transfer completed */

2427

if (!txcount)

2428

{

2429

DPRINTF("C+ mode : transmitter queue stalled, current TxDesc = %d\n",

2430

s->currCPlusTxDesc);

2431

}

2432

else

2433

{

2434

/* update interrupt status */

2435

s->IntrStatus |= TxOK;

2436

rtl8139_update_irq(s);

2437

}

2438

}

2439

2440

static void rtl8139_transmit(RTL8139State *s)

2441

{

2442

int descriptor = s->currTxDesc, txcount = 0;

2443

2444

/*while*/

2445

if (rtl8139_transmit_one(s, descriptor))

2446

{

2447

++s->currTxDesc;

2448

s->currTxDesc %= 4;

2449

++txcount;

2450

}

2451

2452

/* Mark transfer completed */

2453

if (!txcount)

2454

{

2455

DPRINTF("transmitter queue stalled, current TxDesc = %d\n",

2456

s->currTxDesc);

2457

}

2458

}

2459

2460

static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val)

2461

{

2462

2463

int descriptor = txRegOffset/4;

2464

2465

/* handle C+ transmit mode register configuration */

2466

2467

if (s->cplus_enabled)

2468

{

2469

DPRINTF("RTL8139C+ DTCCR write offset=0x%x val=0x%08x "

2470

"descriptor=%d\n", txRegOffset, val, descriptor);

2471

2472

/* handle Dump Tally Counters command */

2473

s->TxStatus[descriptor] = val;

2474

2475

if (descriptor == 0 && (val & 0x8))

2476

{

2477

target_phys_addr_t tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]);

2478

2479

/* dump tally counters to specified memory location */

2480

RTL8139TallyCounters_dma_write(s, tc_addr);

2481

2482

/* mark dump completed */

2483

s->TxStatus[0] &= ~0x8;

2484

}

2485

2486

return;

2487

}

2488

2489

DPRINTF("TxStatus write offset=0x%x val=0x%08x descriptor=%d\n",

2490

txRegOffset, val, descriptor);

2491

2492

/* mask only reserved bits */

2493

val &= ~0xff00c000; /* these bits are reset on write */

2494

val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]);

2495

2496

s->TxStatus[descriptor] = val;

2497

2498

/* attempt to start transmission */

2499

rtl8139_transmit(s);

2500

}

2501

2502

static uint32_t rtl8139_TxStatus_read(RTL8139State *s, uint32_t txRegOffset)

2503

{

2504

uint32_t ret = s->TxStatus[txRegOffset/4];

2505

2506

DPRINTF("TxStatus read offset=0x%x val=0x%08x\n", txRegOffset, ret);

2507

2508

return ret;

2509

}

2510

2511

static uint16_t rtl8139_TSAD_read(RTL8139State *s)

2512

{

2513

uint16_t ret = 0;

2514

2515

/* Simulate TSAD, it is read only anyway */

2516

2517

ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0)

2518

|((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0)

2519

|((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0)

2520

|((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0)

2521

2522

|((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0)

2523

|((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0)

2524

|((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0)

2525

|((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0)

2526

2527

|((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0)

2528

|((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0)

2529

|((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0)

2530

|((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0)

2531

2532

|((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0)

2533

|((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0)

2534

|((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0)

2535

|((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ;

2536

2537

2538

DPRINTF("TSAD read val=0x%04x\n", ret);

2539

2540

return ret;

2541

}

2542

2543

static uint16_t rtl8139_CSCR_read(RTL8139State *s)

2544

{

2545

uint16_t ret = s->CSCR;

2546

2547

DPRINTF("CSCR read val=0x%04x\n", ret);

2548

2549

return ret;

2550

}

2551

2552

static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val)

2553

{

2554

DPRINTF("TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val);

2555

2556

s->TxAddr[txAddrOffset/4] = val;

2557

}

2558

2559

static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset)

2560

{

2561

uint32_t ret = s->TxAddr[txAddrOffset/4];

2562

2563

DPRINTF("TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret);

2564

2565

return ret;

2566

}

2567

2568

static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val)

2569

{

2570

DPRINTF("RxBufPtr write val=0x%04x\n", val);

2571

2572

/* this value is off by 16 */

2573

s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize);

2574

2575

DPRINTF(" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",

2576

s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);

2577

}

2578

2579

static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s)

2580

{

2581

/* this value is off by 16 */

2582

uint32_t ret = s->RxBufPtr - 0x10;

2583

2584

DPRINTF("RxBufPtr read val=0x%04x\n", ret);

2585

2586

return ret;

2587

}

2588

2589

static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s)

2590

{

2591

/* this value is NOT off by 16 */

2592

uint32_t ret = s->RxBufAddr;

2593

2594

DPRINTF("RxBufAddr read val=0x%04x\n", ret);

2595

2596

return ret;

2597

}

2598

2599

static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val)

2600

{

2601

DPRINTF("RxBuf write val=0x%08x\n", val);

2602

2603

s->RxBuf = val;

2604

2605

/* may need to reset rxring here */

2606

}

2607

2608

static uint32_t rtl8139_RxBuf_read(RTL8139State *s)

2609

{

2610

uint32_t ret = s->RxBuf;

2611

2612

DPRINTF("RxBuf read val=0x%08x\n", ret);

2613

2614

return ret;

2615

}

2616

2617

static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val)

2618

{

2619

DPRINTF("IntrMask write(w) val=0x%04x\n", val);

2620

2621

/* mask unwritable bits */

2622

val = SET_MASKED(val, 0x1e00, s->IntrMask);

2623

2624

s->IntrMask = val;

2625

2626

rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));

2627

rtl8139_update_irq(s);

2628

2629

}

2630

2631

static uint32_t rtl8139_IntrMask_read(RTL8139State *s)

2632

{

2633

uint32_t ret = s->IntrMask;

2634

2635

DPRINTF("IntrMask read(w) val=0x%04x\n", ret);

2636

2637

return ret;

2638

}

2639

2640

static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val)

2641

{

2642

DPRINTF("IntrStatus write(w) val=0x%04x\n", val);

2643

2644

#if 0

2645

2646

/* writing to ISR has no effect */

2647

2648

return;

2649

2650

#else

2651

uint16_t newStatus = s->IntrStatus & ~val;

2652

2653

/* mask unwritable bits */

2654

newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus);

2655

2656

/* writing 1 to interrupt status register bit clears it */

2657

s->IntrStatus = 0;

2658

rtl8139_update_irq(s);

2659

2660

s->IntrStatus = newStatus;

2661

2662

* Computing if we miss an interrupt here is not that correct but

2663

* considered that we should have had already an interrupt

2664

* and probably emulated is slower is better to assume this resetting was

2665

* done before testing on previous rtl8139_update_irq lead to IRQ loosing

2666

2667

rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));

2668

rtl8139_update_irq(s);

2669

2670

#endif

2671

}

2672

2673

static uint32_t rtl8139_IntrStatus_read(RTL8139State *s)

2674

{

2675

rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));

2676

2677

uint32_t ret = s->IntrStatus;

2678

2679

DPRINTF("IntrStatus read(w) val=0x%04x\n", ret);

2680

2681

#if 0

2682

2683

/* reading ISR clears all interrupts */

2684

s->IntrStatus = 0;

2685

2686

rtl8139_update_irq(s);

2687

2688

#endif

2689

2690

return ret;

2691

}

2692

2693

static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val)

2694

{

2695

DPRINTF("MultiIntr write(w) val=0x%04x\n", val);

2696

2697

/* mask unwritable bits */

2698

val = SET_MASKED(val, 0xf000, s->MultiIntr);

2699

2700

s->MultiIntr = val;

2701

}

2702

2703

static uint32_t rtl8139_MultiIntr_read(RTL8139State *s)

2704

{

2705

uint32_t ret = s->MultiIntr;

2706

2707

DPRINTF("MultiIntr read(w) val=0x%04x\n", ret);

2708

2709

return ret;

2710

}

2711

2712

static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val)

2713

{

2714

RTL8139State *s = opaque;

2715

2716

switch (addr)

2717

{

2718

case MAC0 ... MAC0+5:

2719

s->phys[addr - MAC0] = val;

2720

break;

2721

case MAC0+6 ... MAC0+7:

2722

/* reserved */

2723

break;

2724

case MAR0 ... MAR0+7:

2725

s->mult[addr - MAR0] = val;

2726

break;

2727

case ChipCmd:

2728

rtl8139_ChipCmd_write(s, val);

2729

break;

2730

case Cfg9346:

2731

rtl8139_Cfg9346_write(s, val);

2732

break;

2733

case TxConfig: /* windows driver sometimes writes using byte-lenth call */

2734

rtl8139_TxConfig_writeb(s, val);

2735

break;

2736

case Config0:

2737

rtl8139_Config0_write(s, val);

2738

break;

2739

case Config1:

2740

rtl8139_Config1_write(s, val);

2741

break;

2742

case Config3:

2743

rtl8139_Config3_write(s, val);

2744

break;

2745

case Config4:

2746

rtl8139_Config4_write(s, val);

2747

break;

2748

case Config5:

2749

rtl8139_Config5_write(s, val);

2750

break;

2751

case MediaStatus:

2752

/* ignore */

2753

DPRINTF("not implemented write(b) to MediaStatus val=0x%02x\n",

2754

val);

2755

break;

2756

2757

case HltClk:

2758

DPRINTF("HltClk write val=0x%08x\n", val);

2759

if (val == 'R')

2760

{

2761

s->clock_enabled = 1;

2762

}

2763

else if (val == 'H')

2764

{

2765

s->clock_enabled = 0;

2766

}

2767

break;

2768

2769

case TxThresh:

2770

DPRINTF("C+ TxThresh write(b) val=0x%02x\n", val);

2771

s->TxThresh = val;

2772

break;

2773

2774

case TxPoll:

2775

DPRINTF("C+ TxPoll write(b) val=0x%02x\n", val);

2776

if (val & (1 << 7))

2777

{

2778

DPRINTF("C+ TxPoll high priority transmission (not "

2779

"implemented)\n");

2780

//rtl8139_cplus_transmit(s);

2781

}

2782

if (val & (1 << 6))

2783

{

2784

DPRINTF("C+ TxPoll normal priority transmission\n");

2785

rtl8139_cplus_transmit(s);

2786

}

2787

2788

break;

2789

2790

default:

2791

DPRINTF("not implemented write(b) addr=0x%x val=0x%02x\n", addr,

2792

val);

2793

break;

2794

}

2795

}

2796

2797

static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val)

2798

{

2799

RTL8139State *s = opaque;

2800

2801

switch (addr)

2802

{

2803

case IntrMask:

2804

rtl8139_IntrMask_write(s, val);

2805

break;

2806

2807

case IntrStatus:

2808

rtl8139_IntrStatus_write(s, val);

2809

break;

2810

2811

case MultiIntr:

2812

rtl8139_MultiIntr_write(s, val);

2813

break;

2814

2815

case RxBufPtr:

2816

rtl8139_RxBufPtr_write(s, val);

2817

break;

2818

2819

case BasicModeCtrl:

2820

rtl8139_BasicModeCtrl_write(s, val);

2821

break;

2822

case BasicModeStatus:

2823

rtl8139_BasicModeStatus_write(s, val);

2824

break;

2825

case NWayAdvert:

2826

DPRINTF("NWayAdvert write(w) val=0x%04x\n", val);

2827

s->NWayAdvert = val;

2828

break;

2829

case NWayLPAR:

2830

DPRINTF("forbidden NWayLPAR write(w) val=0x%04x\n", val);

2831

break;

2832

case NWayExpansion:

2833

DPRINTF("NWayExpansion write(w) val=0x%04x\n", val);

2834

s->NWayExpansion = val;

2835

break;

2836

2837

case CpCmd:

2838

rtl8139_CpCmd_write(s, val);

2839

break;

2840

2841

case IntrMitigate:

2842

rtl8139_IntrMitigate_write(s, val);

2843

break;

2844

2845

default:

2846

DPRINTF("ioport write(w) addr=0x%x val=0x%04x via write(b)\n",

2847

addr, val);

2848

2849

rtl8139_io_writeb(opaque, addr, val & 0xff);

2850

rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);

2851

break;

2852

}

2853

}

2854

2855

static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time)

2856

{

2857

int64_t pci_time, next_time;

2858

uint32_t low_pci;

2859

2860

DPRINTF("entered rtl8139_set_next_tctr_time\n");

2861

2862

if (s->TimerExpire && current_time >= s->TimerExpire) {

2863

s->IntrStatus |= PCSTimeout;

2864

rtl8139_update_irq(s);

2865

}

2866

2867

/* Set QEMU timer only if needed that is

2868

* - TimerInt <> 0 (we have a timer)

2869

* - mask = 1 (we want an interrupt timer)

2870

* - irq = 0 (irq is not already active)

2871

* If any of above change we need to compute timer again

2872

* Also we must check if timer is passed without QEMU timer

2873

2874

s->TimerExpire = 0;

2875

if (!s->TimerInt) {

2876

return;

2877

}

2878

2879

pci_time = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY,

2880

get_ticks_per_sec());

2881

low_pci = pci_time & 0xffffffff;

2882

pci_time = pci_time - low_pci + s->TimerInt;

2883

if (low_pci >= s->TimerInt) {

2884

pci_time += 0x100000000LL;

2885

}

2886

next_time = s->TCTR_base + muldiv64(pci_time, get_ticks_per_sec(),

2887

PCI_FREQUENCY);

2888

s->TimerExpire = next_time;

2889

2890

if ((s->IntrMask & PCSTimeout) != 0 && (s->IntrStatus & PCSTimeout) == 0) {

2891

qemu_mod_timer(s->timer, next_time);

2892

}

2893

}

2894

2895

static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val)

2896

{

2897

RTL8139State *s = opaque;

2898

2899

switch (addr)

2900

{

2901

case RxMissed:

2902

DPRINTF("RxMissed clearing on write\n");

2903

s->RxMissed = 0;

2904

break;

2905

2906

case TxConfig:

2907

rtl8139_TxConfig_write(s, val);

2908

break;

2909

2910

case RxConfig:

2911

rtl8139_RxConfig_write(s, val);

2912

break;

2913

2914

case TxStatus0 ... TxStatus0+4*4-1:

2915

rtl8139_TxStatus_write(s, addr-TxStatus0, val);

2916

break;

2917

2918

case TxAddr0 ... TxAddr0+4*4-1:

2919

rtl8139_TxAddr_write(s, addr-TxAddr0, val);

2920

break;

2921

2922

case RxBuf:

2923

rtl8139_RxBuf_write(s, val);

2924

break;

2925

2926

case RxRingAddrLO:

2927

DPRINTF("C+ RxRing low bits write val=0x%08x\n", val);

2928

s->RxRingAddrLO = val;

2929

break;

2930

2931

case RxRingAddrHI:

2932

DPRINTF("C+ RxRing high bits write val=0x%08x\n", val);

2933

s->RxRingAddrHI = val;

2934

break;

2935

2936

case Timer:

2937

DPRINTF("TCTR Timer reset on write\n");

2938

s->TCTR_base = qemu_get_clock_ns(vm_clock);

2939

rtl8139_set_next_tctr_time(s, s->TCTR_base);

2940

break;

2941

2942

case FlashReg:

2943

DPRINTF("FlashReg TimerInt write val=0x%08x\n", val);

2944

if (s->TimerInt != val) {

2945

s->TimerInt = val;

2946

rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));

2947

}

2948

break;

2949

2950

default:

2951

DPRINTF("ioport write(l) addr=0x%x val=0x%08x via write(b)\n",

2952

addr, val);

2953

rtl8139_io_writeb(opaque, addr, val & 0xff);

2954

rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);

2955

rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff);

2956

rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff);

2957

break;

2958

}

2959

}

2960

2961

static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr)

2962

{

2963

RTL8139State *s = opaque;

2964

int ret;

2965

2966

switch (addr)

2967

{

2968

case MAC0 ... MAC0+5:

2969

ret = s->phys[addr - MAC0];

2970

break;

2971

case MAC0+6 ... MAC0+7:

2972

ret = 0;

2973

break;

2974

case MAR0 ... MAR0+7:

2975

ret = s->mult[addr - MAR0];

2976

break;

2977

case ChipCmd:

2978

ret = rtl8139_ChipCmd_read(s);

2979

break;

2980

case Cfg9346:

2981

ret = rtl8139_Cfg9346_read(s);

2982

break;

2983

case Config0:

2984

ret = rtl8139_Config0_read(s);

2985

break;

2986

case Config1:

2987

ret = rtl8139_Config1_read(s);

2988

break;

2989

case Config3:

2990

ret = rtl8139_Config3_read(s);

2991

break;

2992

case Config4:

2993

ret = rtl8139_Config4_read(s);

2994

break;

2995

case Config5:

2996

ret = rtl8139_Config5_read(s);

2997

break;

2998

2999

case MediaStatus:

3000

ret = 0xd0;

3001

DPRINTF("MediaStatus read 0x%x\n", ret);

3002

break;

3003

3004

case HltClk:

3005

ret = s->clock_enabled;

3006

DPRINTF("HltClk read 0x%x\n", ret);

3007

break;

3008

3009

case PCIRevisionID:

3010

ret = RTL8139_PCI_REVID;

3011

DPRINTF("PCI Revision ID read 0x%x\n", ret);

3012

break;

3013

3014

case TxThresh:

3015

ret = s->TxThresh;

3016

DPRINTF("C+ TxThresh read(b) val=0x%02x\n", ret);

3017

break;

3018

3019

case 0x43: /* Part of TxConfig register. Windows driver tries to read it */

3020

ret = s->TxConfig >> 24;

3021

DPRINTF("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret);

3022

break;

3023

3024

default:

3025

DPRINTF("not implemented read(b) addr=0x%x\n", addr);

3026

ret = 0;

3027

break;

3028

}

3029

3030

return ret;

3031

}

3032

3033

static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr)

3034

{

3035

RTL8139State *s = opaque;

3036

uint32_t ret;

3037

3038

switch (addr)

3039

{

3040

case IntrMask:

3041

ret = rtl8139_IntrMask_read(s);

3042

break;

3043

3044

case IntrStatus:

3045

ret = rtl8139_IntrStatus_read(s);

3046

break;

3047

3048

case MultiIntr:

3049

ret = rtl8139_MultiIntr_read(s);

3050

break;

3051

3052

case RxBufPtr:

3053

ret = rtl8139_RxBufPtr_read(s);

3054

break;

3055

3056

case RxBufAddr:

3057

ret = rtl8139_RxBufAddr_read(s);

3058

break;

3059

3060

case BasicModeCtrl:

3061

ret = rtl8139_BasicModeCtrl_read(s);

3062

break;

3063

case BasicModeStatus:

3064

ret = rtl8139_BasicModeStatus_read(s);

3065

break;

3066

case NWayAdvert:

3067

ret = s->NWayAdvert;

3068

DPRINTF("NWayAdvert read(w) val=0x%04x\n", ret);

3069

break;

3070

case NWayLPAR:

3071

ret = s->NWayLPAR;

3072

DPRINTF("NWayLPAR read(w) val=0x%04x\n", ret);

3073

break;

3074

case NWayExpansion:

3075

ret = s->NWayExpansion;

3076

DPRINTF("NWayExpansion read(w) val=0x%04x\n", ret);

3077

break;

3078

3079

case CpCmd:

3080

ret = rtl8139_CpCmd_read(s);

3081

break;

3082

3083

case IntrMitigate:

3084

ret = rtl8139_IntrMitigate_read(s);

3085

break;

3086

3087

case TxSummary:

3088

ret = rtl8139_TSAD_read(s);

3089

break;

3090

3091

case CSCR:

3092

ret = rtl8139_CSCR_read(s);

3093

break;

3094

3095

default:

3096

DPRINTF("ioport read(w) addr=0x%x via read(b)\n", addr);

3097

3098

ret = rtl8139_io_readb(opaque, addr);

3099

ret |= rtl8139_io_readb(opaque, addr + 1) << 8;

3100

3101

DPRINTF("ioport read(w) addr=0x%x val=0x%04x\n", addr, ret);

3102

break;

3103

}

3104

3105

return ret;

3106

}

3107

3108

static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr)

3109

{

3110

RTL8139State *s = opaque;

3111

uint32_t ret;

3112

3113

switch (addr)

3114

{

3115

case RxMissed:

3116

ret = s->RxMissed;

3117

3118

DPRINTF("RxMissed read val=0x%08x\n", ret);

3119

break;

3120

3121

case TxConfig:

3122

ret = rtl8139_TxConfig_read(s);

3123

break;

3124

3125

case RxConfig:

3126

ret = rtl8139_RxConfig_read(s);

3127

break;

3128

3129

case TxStatus0 ... TxStatus0+4*4-1:

3130

ret = rtl8139_TxStatus_read(s, addr-TxStatus0);

3131

break;

3132

3133

case TxAddr0 ... TxAddr0+4*4-1:

3134

ret = rtl8139_TxAddr_read(s, addr-TxAddr0);

3135

break;

3136

3137

case RxBuf:

3138

ret = rtl8139_RxBuf_read(s);

3139

break;

3140

3141

case RxRingAddrLO:

3142

ret = s->RxRingAddrLO;

3143

DPRINTF("C+ RxRing low bits read val=0x%08x\n", ret);

3144

break;

3145

3146

case RxRingAddrHI:

3147

ret = s->RxRingAddrHI;

3148

DPRINTF("C+ RxRing high bits read val=0x%08x\n", ret);

3149

break;

3150

3151

case Timer:

3152

ret = muldiv64(qemu_get_clock_ns(vm_clock) - s->TCTR_base,

3153

PCI_FREQUENCY, get_ticks_per_sec());

3154

DPRINTF("TCTR Timer read val=0x%08x\n", ret);

3155

break;

3156

3157

case FlashReg:

3158

ret = s->TimerInt;

3159

DPRINTF("FlashReg TimerInt read val=0x%08x\n", ret);

3160

break;

3161

3162

default:

3163

DPRINTF("ioport read(l) addr=0x%x via read(b)\n", addr);

3164

3165

ret = rtl8139_io_readb(opaque, addr);

3166

ret |= rtl8139_io_readb(opaque, addr + 1) << 8;

3167

ret |= rtl8139_io_readb(opaque, addr + 2) << 16;

3168

ret |= rtl8139_io_readb(opaque, addr + 3) << 24;

3169

3170

DPRINTF("read(l) addr=0x%x val=%08x\n", addr, ret);

3171

break;

3172

}

3173

3174

return ret;

3175

}

3176

3177

/* */

3178

3179

static void rtl8139_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)

3180

{

3181

rtl8139_io_writeb(opaque, addr & 0xFF, val);

3182

}

3183

3184

static void rtl8139_ioport_writew(void *opaque, uint32_t addr, uint32_t val)

3185

{

3186

rtl8139_io_writew(opaque, addr & 0xFF, val);

3187

}

3188

3189

static void rtl8139_ioport_writel(void *opaque, uint32_t addr, uint32_t val)

3190

{

3191

rtl8139_io_writel(opaque, addr & 0xFF, val);

3192

}

3193

3194

static uint32_t rtl8139_ioport_readb(void *opaque, uint32_t addr)

3195

{

3196

return rtl8139_io_readb(opaque, addr & 0xFF);

3197

}

3198

3199

static uint32_t rtl8139_ioport_readw(void *opaque, uint32_t addr)

3200

{

3201

return rtl8139_io_readw(opaque, addr & 0xFF);

3202

}

3203

3204

static uint32_t rtl8139_ioport_readl(void *opaque, uint32_t addr)

3205

{

3206

return rtl8139_io_readl(opaque, addr & 0xFF);

3207

}

3208

3209

/* */

3210

3211

static void rtl8139_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)

3212

{

3213

rtl8139_io_writeb(opaque, addr & 0xFF, val);

3214

}

3215

3216

static void rtl8139_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)

3217

{

3218

rtl8139_io_writew(opaque, addr & 0xFF, val);

3219

}

3220

3221

static void rtl8139_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)

3222

{

3223

rtl8139_io_writel(opaque, addr & 0xFF, val);

3224

}

3225

3226

static uint32_t rtl8139_mmio_readb(void *opaque, target_phys_addr_t addr)

3227

{

3228

return rtl8139_io_readb(opaque, addr & 0xFF);

3229

}

3230

3231

static uint32_t rtl8139_mmio_readw(void *opaque, target_phys_addr_t addr)

3232

{

3233

uint32_t val = rtl8139_io_readw(opaque, addr & 0xFF);

3234

return val;

3235

}

3236

3237

static uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr)

3238

{

3239

uint32_t val = rtl8139_io_readl(opaque, addr & 0xFF);

3240

return val;

3241

}

3242

3243

static int rtl8139_post_load(void *opaque, int version_id)

3244

{

3245

RTL8139State* s = opaque;

3246

rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));

3247

if (version_id < 4) {

3248

s->cplus_enabled = s->CpCmd != 0;

3249

}

3250

3251

return 0;

3252

}

3253

3254

static bool rtl8139_hotplug_ready_needed(void *opaque)

3255

{

3256

return qdev_machine_modified();

3257

}

3258

3259

static const VMStateDescription vmstate_rtl8139_hotplug_ready ={

3260

.name = "rtl8139/hotplug_ready",

3261

.version_id = 1,

3262

.minimum_version_id = 1,

3263

.minimum_version_id_old = 1,

3264

.fields = (VMStateField []) {

3265

VMSTATE_END_OF_LIST()

3266

}

3267

};

3268

3269

static void rtl8139_pre_save(void *opaque)

3270

{

3271

RTL8139State* s = opaque;

3272

int64_t current_time = qemu_get_clock_ns(vm_clock);

3273

3274

/* set IntrStatus correctly */

3275

rtl8139_set_next_tctr_time(s, current_time);

3276

s->TCTR = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY,

3277

get_ticks_per_sec());

3278

s->rtl8139_mmio_io_addr_dummy = 0;

3279

}

3280

3281

static const VMStateDescription vmstate_rtl8139 = {

3282

.name = "rtl8139",

3283

.version_id = 4,

3284

.minimum_version_id = 3,

3285

.minimum_version_id_old = 3,

3286

.post_load = rtl8139_post_load,

3287

.pre_save = rtl8139_pre_save,

3288

.fields = (VMStateField []) {

3289

VMSTATE_PCI_DEVICE(dev, RTL8139State),

3290

VMSTATE_PARTIAL_BUFFER(phys, RTL8139State, 6),

3291

VMSTATE_BUFFER(mult, RTL8139State),

3292

VMSTATE_UINT32_ARRAY(TxStatus, RTL8139State, 4),

3293

VMSTATE_UINT32_ARRAY(TxAddr, RTL8139State, 4),

3294

3295

VMSTATE_UINT32(RxBuf, RTL8139State),

3296

VMSTATE_UINT32(RxBufferSize, RTL8139State),

3297

VMSTATE_UINT32(RxBufPtr, RTL8139State),

3298

VMSTATE_UINT32(RxBufAddr, RTL8139State),

3299

3300

VMSTATE_UINT16(IntrStatus, RTL8139State),

3301

VMSTATE_UINT16(IntrMask, RTL8139State),

3302

3303

VMSTATE_UINT32(TxConfig, RTL8139State),

3304

VMSTATE_UINT32(RxConfig, RTL8139State),

3305

VMSTATE_UINT32(RxMissed, RTL8139State),

3306

VMSTATE_UINT16(CSCR, RTL8139State),

3307

3308

VMSTATE_UINT8(Cfg9346, RTL8139State),

3309

VMSTATE_UINT8(Config0, RTL8139State),

3310

VMSTATE_UINT8(Config1, RTL8139State),

3311

VMSTATE_UINT8(Config3, RTL8139State),

3312

VMSTATE_UINT8(Config4, RTL8139State),

3313

VMSTATE_UINT8(Config5, RTL8139State),

3314

3315

VMSTATE_UINT8(clock_enabled, RTL8139State),

3316

VMSTATE_UINT8(bChipCmdState, RTL8139State),

3317

3318

VMSTATE_UINT16(MultiIntr, RTL8139State),

3319

3320

VMSTATE_UINT16(BasicModeCtrl, RTL8139State),

3321

VMSTATE_UINT16(BasicModeStatus, RTL8139State),

3322

VMSTATE_UINT16(NWayAdvert, RTL8139State),

3323

VMSTATE_UINT16(NWayLPAR, RTL8139State),

3324

VMSTATE_UINT16(NWayExpansion, RTL8139State),

3325

3326

VMSTATE_UINT16(CpCmd, RTL8139State),

3327

VMSTATE_UINT8(TxThresh, RTL8139State),

3328

3329

VMSTATE_UNUSED(4),

3330

VMSTATE_MACADDR(conf.macaddr, RTL8139State),

3331

VMSTATE_INT32(rtl8139_mmio_io_addr_dummy, RTL8139State),

3332

3333

VMSTATE_UINT32(currTxDesc, RTL8139State),

3334

VMSTATE_UINT32(currCPlusRxDesc, RTL8139State),

3335

VMSTATE_UINT32(currCPlusTxDesc, RTL8139State),

3336

VMSTATE_UINT32(RxRingAddrLO, RTL8139State),

3337

VMSTATE_UINT32(RxRingAddrHI, RTL8139State),

3338

3339

VMSTATE_UINT16_ARRAY(eeprom.contents, RTL8139State, EEPROM_9346_SIZE),

3340

VMSTATE_INT32(eeprom.mode, RTL8139State),

3341

VMSTATE_UINT32(eeprom.tick, RTL8139State),

3342

VMSTATE_UINT8(eeprom.address, RTL8139State),

3343

VMSTATE_UINT16(eeprom.input, RTL8139State),

3344

VMSTATE_UINT16(eeprom.output, RTL8139State),

3345

3346

VMSTATE_UINT8(eeprom.eecs, RTL8139State),

3347

VMSTATE_UINT8(eeprom.eesk, RTL8139State),

3348

VMSTATE_UINT8(eeprom.eedi, RTL8139State),

3349

VMSTATE_UINT8(eeprom.eedo, RTL8139State),

3350

3351

VMSTATE_UINT32(TCTR, RTL8139State),

3352

VMSTATE_UINT32(TimerInt, RTL8139State),

3353

VMSTATE_INT64(TCTR_base, RTL8139State),

3354

3355

VMSTATE_STRUCT(tally_counters, RTL8139State, 0,

3356

vmstate_tally_counters, RTL8139TallyCounters),

3357

3358

VMSTATE_UINT32_V(cplus_enabled, RTL8139State, 4),

3359

VMSTATE_END_OF_LIST()

3360

3361

.subsections = (VMStateSubsection []) {

3362

{

3363

.vmsd = &vmstate_rtl8139_hotplug_ready,

3364

.needed = rtl8139_hotplug_ready_needed,

3365

}, {

3366

/* empty */

3367

}

3368

}

3369

};

3370

3371

/***********************************************************/

3372

/* PCI RTL8139 definitions */

3373

3374

static const MemoryRegionPortio rtl8139_portio[] = {

3375

{ 0, 0x100, 1, .read = rtl8139_ioport_readb, },

3376

{ 0, 0x100, 1, .write = rtl8139_ioport_writeb, },

3377

{ 0, 0x100, 2, .read = rtl8139_ioport_readw, },

3378

{ 0, 0x100, 2, .write = rtl8139_ioport_writew, },

3379

{ 0, 0x100, 4, .read = rtl8139_ioport_readl, },

3380

{ 0, 0x100, 4, .write = rtl8139_ioport_writel, },

3381

PORTIO_END_OF_LIST()

3382

};

3383

3384

static const MemoryRegionOps rtl8139_io_ops = {

3385

.old_portio = rtl8139_portio,

3386

.endianness = DEVICE_LITTLE_ENDIAN,

3387

};

3388

3389

static const MemoryRegionOps rtl8139_mmio_ops = {

3390

.old_mmio = {

3391

.read = {

3392

rtl8139_mmio_readb,

3393

rtl8139_mmio_readw,

3394

rtl8139_mmio_readl,

3395

3396

.write = {

3397

rtl8139_mmio_writeb,

3398

rtl8139_mmio_writew,

3399

rtl8139_mmio_writel,

3400

3401

3402

.endianness = DEVICE_LITTLE_ENDIAN,

3403

};

3404

3405

static void rtl8139_timer(void *opaque)

3406

{

3407

RTL8139State *s = opaque;

3408

3409

if (!s->clock_enabled)

3410

{

3411

DPRINTF(">>> timer: clock is not running\n");

3412

return;

3413

}

3414

3415

s->IntrStatus |= PCSTimeout;

3416

rtl8139_update_irq(s);

3417

rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));

3418

}

3419

3420

static void rtl8139_cleanup(VLANClientState *nc)

3421

{

3422

RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;

3423

3424

s->nic = NULL;

3425

}

3426

3427

static int pci_rtl8139_uninit(PCIDevice *dev)

3428

{

3429

RTL8139State *s = DO_UPCAST(RTL8139State, dev, dev);

3430

3431

memory_region_destroy(&s->bar_io);

3432

memory_region_destroy(&s->bar_mem);

3433

if (s->cplus_txbuffer) {

3434

g_free(s->cplus_txbuffer);

3435

s->cplus_txbuffer = NULL;

3436

}

3437

qemu_del_timer(s->timer);

3438

qemu_free_timer(s->timer);

3439

qemu_del_vlan_client(&s->nic->nc);

3440

return 0;

3441

}

3442

3443

static NetClientInfo net_rtl8139_info = {

3444

.type = NET_CLIENT_TYPE_NIC,

3445

.size = sizeof(NICState),

3446

.can_receive = rtl8139_can_receive,

3447

.receive = rtl8139_receive,

3448

.cleanup = rtl8139_cleanup,

3449

};

3450

3451

static int pci_rtl8139_init(PCIDevice *dev)

3452

{

3453

RTL8139State * s = DO_UPCAST(RTL8139State, dev, dev);

3454

uint8_t *pci_conf;

3455

3456

pci_conf = s->dev.config;

3457

pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */

3458

/* TODO: start of capability list, but no capability

3459

* list bit in status register, and offset 0xdc seems unused. */

3460

pci_conf[PCI_CAPABILITY_LIST] = 0xdc;

3461

3462

memory_region_init_io(&s->bar_io, &rtl8139_io_ops, s, "rtl8139", 0x100);

3463

memory_region_init_io(&s->bar_mem, &rtl8139_mmio_ops, s, "rtl8139", 0x100);

3464

pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->bar_io);

3465

pci_register_bar(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar_mem);

3466

3467

qemu_macaddr_default_if_unset(&s->conf.macaddr);

3468

3469

/* prepare eeprom */

3470

s->eeprom.contents[0] = 0x8129;

3471

#if 1

3472

/* PCI vendor and device ID should be mirrored here */

3473

s->eeprom.contents[1] = PCI_VENDOR_ID_REALTEK;

3474

s->eeprom.contents[2] = PCI_DEVICE_ID_REALTEK_8139;

3475

#endif

3476

s->eeprom.contents[7] = s->conf.macaddr.a[0] | s->conf.macaddr.a[1] << 8;

3477

s->eeprom.contents[8] = s->conf.macaddr.a[2] | s->conf.macaddr.a[3] << 8;

3478

s->eeprom.contents[9] = s->conf.macaddr.a[4] | s->conf.macaddr.a[5] << 8;

3479

3480

s->nic = qemu_new_nic(&net_rtl8139_info, &s->conf,

3481

dev->qdev.info->name, dev->qdev.id, s);

3482

qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);

3483

3484

s->cplus_txbuffer = NULL;

3485

s->cplus_txbuffer_len = 0;

3486

s->cplus_txbuffer_offset = 0;

3487

3488

s->TimerExpire = 0;

3489

s->timer = qemu_new_timer_ns(vm_clock, rtl8139_timer, s);

3490

rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));

3491

3492

add_boot_device_path(s->conf.bootindex, &dev->qdev, "/ethernet-phy@0");

3493

3494

return 0;

3495

}

3496

3497

static PCIDeviceInfo rtl8139_info = {

3498

.qdev.name = "rtl8139",

3499

.qdev.size = sizeof(RTL8139State),

3500

.qdev.reset = rtl8139_reset,

3501

.qdev.vmsd = &vmstate_rtl8139,

3502

.init = pci_rtl8139_init,

3503

.exit = pci_rtl8139_uninit,

3504

.romfile = "pxe-rtl8139.rom",

3505

.vendor_id = PCI_VENDOR_ID_REALTEK,

3506

.device_id = PCI_DEVICE_ID_REALTEK_8139,

3507

.revision = RTL8139_PCI_REVID, /* >=0x20 is for 8139C+ */

3508

.class_id = PCI_CLASS_NETWORK_ETHERNET,

3509

.qdev.props = (Property[]) {

3510

DEFINE_NIC_PROPERTIES(RTL8139State, conf),

3511

DEFINE_PROP_END_OF_LIST(),

3512

}

3513

};

3514

3515

static void rtl8139_register_devices(void)

3516

{

3517

pci_qdev_register(&rtl8139_info);

3518

}

3519

3520

device_init(rtl8139_register_devices)

Older »