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* QEMU MC146818 RTC emulation
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* Copyright (c) 2003-2004 Fabrice Bellard
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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#include "qemu-timer.h"
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#include "mc146818rtc.h"
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//#define DEBUG_COALESCED
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# define CMOS_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
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# define CMOS_DPRINTF(format, ...) do { } while (0)
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#ifdef DEBUG_COALESCED
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# define DPRINTF_C(format, ...) printf(format, ## __VA_ARGS__)
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# define DPRINTF_C(format, ...) do { } while (0)
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#define RTC_REINJECT_ON_ACK_COUNT 20
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#define RTC_SECONDS_ALARM 1
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#define RTC_MINUTES_ALARM 3
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#define RTC_HOURS_ALARM 5
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#define RTC_ALARM_DONT_CARE 0xC0
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#define RTC_DAY_OF_WEEK 6
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#define RTC_DAY_OF_MONTH 7
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#define REG_A_UIP 0x80
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#define REG_B_SET 0x80
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#define REG_B_PIE 0x40
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#define REG_B_AIE 0x20
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#define REG_B_UIE 0x10
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#define REG_B_SQWE 0x08
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#define REG_B_24H 0x02
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#define REG_C_IRQF 0x80
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typedef struct RTCState {
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uint8_t cmos_data[128];
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QEMUTimer *periodic_timer;
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int64_t next_periodic_time;
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int64_t next_second_time;
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uint16_t irq_reinject_on_ack_count;
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uint32_t irq_coalesced;
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QEMUTimer *coalesced_timer;
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QEMUTimer *second_timer;
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QEMUTimer *second_timer2;
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Notifier clock_reset_notifier;
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static void rtc_set_time(RTCState *s);
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static void rtc_copy_date(RTCState *s);
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static void rtc_coalesced_timer_update(RTCState *s)
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if (s->irq_coalesced == 0) {
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qemu_del_timer(s->coalesced_timer);
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/* divide each RTC interval to 2 - 8 smaller intervals */
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int c = MIN(s->irq_coalesced, 7) + 1;
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int64_t next_clock = qemu_get_clock_ns(rtc_clock) +
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muldiv64(s->period / c, get_ticks_per_sec(), 32768);
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qemu_mod_timer(s->coalesced_timer, next_clock);
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static void rtc_coalesced_timer(void *opaque)
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RTCState *s = opaque;
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if (s->irq_coalesced != 0) {
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apic_reset_irq_delivered();
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s->cmos_data[RTC_REG_C] |= 0xc0;
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DPRINTF_C("cmos: injecting from timer\n");
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qemu_irq_raise(s->irq);
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if (apic_get_irq_delivered()) {
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DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
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rtc_coalesced_timer_update(s);
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static void rtc_timer_update(RTCState *s, int64_t current_time)
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int period_code, period;
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int64_t cur_clock, next_irq_clock;
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period_code = s->cmos_data[RTC_REG_A] & 0x0f;
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&& ((s->cmos_data[RTC_REG_B] & REG_B_PIE)
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|| ((s->cmos_data[RTC_REG_B] & REG_B_SQWE) && s->sqw_irq))) {
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if (period_code <= 2)
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/* period in 32 Khz cycles */
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period = 1 << (period_code - 1);
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if (period != s->period) {
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s->irq_coalesced = (s->irq_coalesced * s->period) / period;
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DPRINTF_C("cmos: coalesced irqs scaled to %d\n", s->irq_coalesced);
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/* compute 32 khz clock */
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cur_clock = muldiv64(current_time, 32768, get_ticks_per_sec());
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next_irq_clock = (cur_clock & ~(period - 1)) + period;
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s->next_periodic_time =
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muldiv64(next_irq_clock, get_ticks_per_sec(), 32768) + 1;
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qemu_mod_timer(s->periodic_timer, s->next_periodic_time);
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s->irq_coalesced = 0;
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qemu_del_timer(s->periodic_timer);
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static void rtc_periodic_timer(void *opaque)
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RTCState *s = opaque;
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rtc_timer_update(s, s->next_periodic_time);
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if (s->cmos_data[RTC_REG_B] & REG_B_PIE) {
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s->cmos_data[RTC_REG_C] |= 0xc0;
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if (s->irq_reinject_on_ack_count >= RTC_REINJECT_ON_ACK_COUNT)
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s->irq_reinject_on_ack_count = 0;
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apic_reset_irq_delivered();
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qemu_irq_raise(s->irq);
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if (!apic_get_irq_delivered()) {
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rtc_coalesced_timer_update(s);
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DPRINTF_C("cmos: coalesced irqs increased to %d\n",
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qemu_irq_raise(s->irq);
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if (s->cmos_data[RTC_REG_B] & REG_B_SQWE) {
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/* Not square wave at all but we don't want 2048Hz interrupts!
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Must be seen as a pulse. */
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qemu_irq_raise(s->sqw_irq);
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static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data)
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RTCState *s = opaque;
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if ((addr & 1) == 0) {
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s->cmos_index = data & 0x7f;
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CMOS_DPRINTF("cmos: write index=0x%02x val=0x%02x\n",
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s->cmos_index, data);
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switch(s->cmos_index) {
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case RTC_SECONDS_ALARM:
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case RTC_MINUTES_ALARM:
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case RTC_HOURS_ALARM:
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s->cmos_data[s->cmos_index] = data;
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case RTC_DAY_OF_WEEK:
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case RTC_DAY_OF_MONTH:
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s->cmos_data[s->cmos_index] = data;
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/* if in set mode, do not update the time */
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if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
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/* UIP bit is read only */
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s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) |
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(s->cmos_data[RTC_REG_A] & REG_A_UIP);
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rtc_timer_update(s, qemu_get_clock_ns(rtc_clock));
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if (data & REG_B_SET) {
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/* set mode: reset UIP mode */
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s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
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/* if disabling set mode, update the time */
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if (s->cmos_data[RTC_REG_B] & REG_B_SET) {
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if (((s->cmos_data[RTC_REG_B] ^ data) & (REG_B_DM | REG_B_24H)) &&
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!(data & REG_B_SET)) {
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/* If the time format has changed and not in set mode,
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update the registers immediately. */
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s->cmos_data[RTC_REG_B] = data;
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s->cmos_data[RTC_REG_B] = data;
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rtc_timer_update(s, qemu_get_clock_ns(rtc_clock));
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/* cannot write to them */
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s->cmos_data[s->cmos_index] = data;
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static inline int rtc_to_bcd(RTCState *s, int a)
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if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
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return ((a / 10) << 4) | (a % 10);
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static inline int rtc_from_bcd(RTCState *s, int a)
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if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
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return ((a >> 4) * 10) + (a & 0x0f);
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static void rtc_set_time(RTCState *s)
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struct tm *tm = &s->current_tm;
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tm->tm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]);
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tm->tm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]);
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tm->tm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
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if (!(s->cmos_data[RTC_REG_B] & REG_B_24H) &&
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(s->cmos_data[RTC_HOURS] & 0x80)) {
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tm->tm_wday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1;
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tm->tm_mday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]);
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tm->tm_mon = rtc_from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
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tm->tm_year = rtc_from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year - 1900;
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rtc_change_mon_event(tm);
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static void rtc_copy_date(RTCState *s)
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const struct tm *tm = &s->current_tm;
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s->cmos_data[RTC_SECONDS] = rtc_to_bcd(s, tm->tm_sec);
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s->cmos_data[RTC_MINUTES] = rtc_to_bcd(s, tm->tm_min);
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if (s->cmos_data[RTC_REG_B] & REG_B_24H) {
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s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour);
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s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour % 12);
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if (tm->tm_hour >= 12)
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s->cmos_data[RTC_HOURS] |= 0x80;
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s->cmos_data[RTC_DAY_OF_WEEK] = rtc_to_bcd(s, tm->tm_wday + 1);
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s->cmos_data[RTC_DAY_OF_MONTH] = rtc_to_bcd(s, tm->tm_mday);
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s->cmos_data[RTC_MONTH] = rtc_to_bcd(s, tm->tm_mon + 1);
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year = (tm->tm_year - s->base_year) % 100;
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s->cmos_data[RTC_YEAR] = rtc_to_bcd(s, year);
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/* month is between 0 and 11. */
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static int get_days_in_month(int month, int year)
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static const int days_tab[12] = {
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31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
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if ((unsigned )month >= 12)
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if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0))
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/* update 'tm' to the next second */
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static void rtc_next_second(struct tm *tm)
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if ((unsigned)tm->tm_sec >= 60) {
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if ((unsigned)tm->tm_min >= 60) {
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if ((unsigned)tm->tm_hour >= 24) {
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if ((unsigned)tm->tm_wday >= 7)
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days_in_month = get_days_in_month(tm->tm_mon,
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if (tm->tm_mday < 1) {
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} else if (tm->tm_mday > days_in_month) {
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if (tm->tm_mon >= 12) {
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static void rtc_update_second(void *opaque)
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RTCState *s = opaque;
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/* if the oscillator is not in normal operation, we do not update */
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if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) {
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s->next_second_time += get_ticks_per_sec();
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qemu_mod_timer(s->second_timer, s->next_second_time);
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rtc_next_second(&s->current_tm);
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if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
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/* update in progress bit */
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s->cmos_data[RTC_REG_A] |= REG_A_UIP;
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/* should be 244 us = 8 / 32768 seconds, but currently the
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timers do not have the necessary resolution. */
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delay = (get_ticks_per_sec() * 1) / 100;
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qemu_mod_timer(s->second_timer2,
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s->next_second_time + delay);
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static void rtc_update_second2(void *opaque)
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RTCState *s = opaque;
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if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
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if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
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if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 ||
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rtc_from_bcd(s, s->cmos_data[RTC_SECONDS_ALARM]) == s->current_tm.tm_sec) &&
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((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 ||
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rtc_from_bcd(s, s->cmos_data[RTC_MINUTES_ALARM]) == s->current_tm.tm_min) &&
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((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 ||
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rtc_from_bcd(s, s->cmos_data[RTC_HOURS_ALARM]) == s->current_tm.tm_hour)) {
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s->cmos_data[RTC_REG_C] |= 0xa0;
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qemu_irq_raise(s->irq);
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/* update ended interrupt */
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s->cmos_data[RTC_REG_C] |= REG_C_UF;
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if (s->cmos_data[RTC_REG_B] & REG_B_UIE) {
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s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
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qemu_irq_raise(s->irq);
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/* clear update in progress bit */
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s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
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s->next_second_time += get_ticks_per_sec();
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qemu_mod_timer(s->second_timer, s->next_second_time);
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static uint32_t cmos_ioport_read(void *opaque, uint32_t addr)
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RTCState *s = opaque;
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if ((addr & 1) == 0) {
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switch(s->cmos_index) {
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case RTC_DAY_OF_WEEK:
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case RTC_DAY_OF_MONTH:
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ret = s->cmos_data[s->cmos_index];
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ret = s->cmos_data[s->cmos_index];
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ret = s->cmos_data[s->cmos_index];
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qemu_irq_lower(s->irq);
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if(s->irq_coalesced &&
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s->irq_reinject_on_ack_count < RTC_REINJECT_ON_ACK_COUNT) {
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s->irq_reinject_on_ack_count++;
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apic_reset_irq_delivered();
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DPRINTF_C("cmos: injecting on ack\n");
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qemu_irq_raise(s->irq);
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if (apic_get_irq_delivered()) {
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DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
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s->cmos_data[RTC_REG_C] = 0x00;
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ret = s->cmos_data[s->cmos_index];
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CMOS_DPRINTF("cmos: read index=0x%02x val=0x%02x\n",
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void rtc_set_memory(ISADevice *dev, int addr, int val)
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RTCState *s = DO_UPCAST(RTCState, dev, dev);
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if (addr >= 0 && addr <= 127)
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s->cmos_data[addr] = val;
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void rtc_set_date(ISADevice *dev, const struct tm *tm)
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RTCState *s = DO_UPCAST(RTCState, dev, dev);
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/* PC cmos mappings */
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#define REG_IBM_CENTURY_BYTE 0x32
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#define REG_IBM_PS2_CENTURY_BYTE 0x37
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static void rtc_set_date_from_host(ISADevice *dev)
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RTCState *s = DO_UPCAST(RTCState, dev, dev);
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/* set the CMOS date */
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qemu_get_timedate(&tm, 0);
529
rtc_set_date(dev, &tm);
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val = rtc_to_bcd(s, (tm.tm_year / 100) + 19);
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rtc_set_memory(dev, REG_IBM_CENTURY_BYTE, val);
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rtc_set_memory(dev, REG_IBM_PS2_CENTURY_BYTE, val);
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static int rtc_post_load(void *opaque, int version_id)
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RTCState *s = opaque;
541
if (version_id >= 2) {
543
rtc_coalesced_timer_update(s);
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static const VMStateDescription vmstate_rtc = {
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.name = "mc146818rtc",
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.post_load = rtc_post_load,
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.fields = (VMStateField []) {
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VMSTATE_BUFFER(cmos_data, RTCState),
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VMSTATE_UINT8(cmos_index, RTCState),
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VMSTATE_INT32(current_tm.tm_sec, RTCState),
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VMSTATE_INT32(current_tm.tm_min, RTCState),
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VMSTATE_INT32(current_tm.tm_hour, RTCState),
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VMSTATE_INT32(current_tm.tm_wday, RTCState),
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VMSTATE_INT32(current_tm.tm_mday, RTCState),
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VMSTATE_INT32(current_tm.tm_mon, RTCState),
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VMSTATE_INT32(current_tm.tm_year, RTCState),
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VMSTATE_TIMER(periodic_timer, RTCState),
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VMSTATE_INT64(next_periodic_time, RTCState),
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VMSTATE_INT64(next_second_time, RTCState),
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VMSTATE_TIMER(second_timer, RTCState),
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VMSTATE_TIMER(second_timer2, RTCState),
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VMSTATE_UINT32_V(irq_coalesced, RTCState, 2),
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VMSTATE_UINT32_V(period, RTCState, 2),
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VMSTATE_END_OF_LIST()
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static void rtc_notify_clock_reset(Notifier *notifier, void *data)
579
RTCState *s = container_of(notifier, RTCState, clock_reset_notifier);
580
int64_t now = *(int64_t *)data;
582
rtc_set_date_from_host(&s->dev);
583
s->next_second_time = now + (get_ticks_per_sec() * 99) / 100;
584
qemu_mod_timer(s->second_timer2, s->next_second_time);
585
rtc_timer_update(s, now);
588
rtc_coalesced_timer_update(s);
593
static void rtc_reset(void *opaque)
595
RTCState *s = opaque;
597
s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE);
598
s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF);
600
qemu_irq_lower(s->irq);
604
s->irq_coalesced = 0;
608
static const MemoryRegionPortio cmos_portio[] = {
609
{0, 2, 1, .read = cmos_ioport_read, .write = cmos_ioport_write },
610
PORTIO_END_OF_LIST(),
613
static const MemoryRegionOps cmos_ops = {
614
.old_portio = cmos_portio
617
static int rtc_initfn(ISADevice *dev)
619
RTCState *s = DO_UPCAST(RTCState, dev, dev);
622
s->cmos_data[RTC_REG_A] = 0x26;
623
s->cmos_data[RTC_REG_B] = 0x02;
624
s->cmos_data[RTC_REG_C] = 0x00;
625
s->cmos_data[RTC_REG_D] = 0x80;
627
rtc_set_date_from_host(dev);
629
s->periodic_timer = qemu_new_timer_ns(rtc_clock, rtc_periodic_timer, s);
633
qemu_new_timer_ns(rtc_clock, rtc_coalesced_timer, s);
635
s->second_timer = qemu_new_timer_ns(rtc_clock, rtc_update_second, s);
636
s->second_timer2 = qemu_new_timer_ns(rtc_clock, rtc_update_second2, s);
638
s->clock_reset_notifier.notify = rtc_notify_clock_reset;
639
qemu_register_clock_reset_notifier(rtc_clock, &s->clock_reset_notifier);
641
s->next_second_time =
642
qemu_get_clock_ns(rtc_clock) + (get_ticks_per_sec() * 99) / 100;
643
qemu_mod_timer(s->second_timer2, s->next_second_time);
645
memory_region_init_io(&s->io, &cmos_ops, s, "rtc", 2);
646
isa_register_ioport(dev, &s->io, base);
648
qdev_set_legacy_instance_id(&dev->qdev, base, 2);
649
qemu_register_reset(rtc_reset, s);
653
ISADevice *rtc_init(int base_year, qemu_irq intercept_irq)
658
dev = isa_create("mc146818rtc");
659
s = DO_UPCAST(RTCState, dev, dev);
660
qdev_prop_set_int32(&dev->qdev, "base_year", base_year);
661
qdev_init_nofail(&dev->qdev);
663
s->irq = intercept_irq;
665
isa_init_irq(dev, &s->irq, RTC_ISA_IRQ);
670
static ISADeviceInfo mc146818rtc_info = {
671
.qdev.name = "mc146818rtc",
672
.qdev.size = sizeof(RTCState),
674
.qdev.vmsd = &vmstate_rtc,
676
.qdev.props = (Property[]) {
677
DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980),
678
DEFINE_PROP_END_OF_LIST(),
682
static void mc146818rtc_register(void)
684
isa_qdev_register(&mc146818rtc_info);
686
device_init(mc146818rtc_register)