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  • Committer: Al Stone
  • Date: 2012-02-09 01:17:20 UTC
  • Revision ID: albert.stone@canonical.com-20120209011720-tztl7ik3qayz80p4
first commit to bzr for qemu

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tcg/ia64/tcg-target.h
 
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/*
 
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 * Tiny Code Generator for QEMU
 
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 *
 
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 * Copyright (c) 2009-2010 Aurelien Jarno <aurelien@aurel32.net>
 
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 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
 
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 *
 
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
 
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 * of this software and associated documentation files (the "Software"), to deal
 
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 * in the Software without restriction, including without limitation the rights
 
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 
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 * copies of the Software, and to permit persons to whom the Software is
 
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 * furnished to do so, subject to the following conditions:
 
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 *
 
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 * The above copyright notice and this permission notice shall be included in
 
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 * all copies or substantial portions of the Software.
 
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 *
 
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 
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 * THE SOFTWARE.
 
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 */
 
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#define TCG_TARGET_IA64 1
 
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/* We only map the first 64 registers */
 
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#define TCG_TARGET_NB_REGS 64
 
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typedef enum {
 
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    TCG_REG_R0 = 0,
 
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    TCG_REG_R1,
 
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    TCG_REG_R2,
 
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    TCG_REG_R3,
 
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    TCG_REG_R4,
 
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    TCG_REG_R5,
 
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    TCG_REG_R6,
 
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    TCG_REG_R7,
 
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    TCG_REG_R8,
 
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    TCG_REG_R9,
 
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    TCG_REG_R10,
 
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    TCG_REG_R11,
 
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    TCG_REG_R12,
 
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    TCG_REG_R13,
 
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    TCG_REG_R14,
 
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    TCG_REG_R15,
 
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    TCG_REG_R16,
 
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    TCG_REG_R17,
 
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    TCG_REG_R18,
 
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    TCG_REG_R19,
 
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    TCG_REG_R20,
 
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    TCG_REG_R21,
 
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    TCG_REG_R22,
 
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    TCG_REG_R23,
 
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    TCG_REG_R24,
 
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    TCG_REG_R25,
 
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    TCG_REG_R26,
 
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    TCG_REG_R27,
 
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    TCG_REG_R28,
 
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    TCG_REG_R29,
 
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    TCG_REG_R30,
 
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    TCG_REG_R31,
 
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    TCG_REG_R32,
 
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    TCG_REG_R33,
 
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    TCG_REG_R34,
 
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    TCG_REG_R35,
 
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    TCG_REG_R36,
 
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    TCG_REG_R37,
 
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    TCG_REG_R38,
 
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    TCG_REG_R39,
 
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    TCG_REG_R40,
 
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    TCG_REG_R41,
 
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    TCG_REG_R42,
 
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    TCG_REG_R43,
 
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    TCG_REG_R44,
 
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    TCG_REG_R45,
 
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    TCG_REG_R46,
 
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    TCG_REG_R47,
 
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    TCG_REG_R48,
 
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    TCG_REG_R49,
 
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    TCG_REG_R50,
 
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    TCG_REG_R51,
 
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    TCG_REG_R52,
 
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    TCG_REG_R53,
 
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    TCG_REG_R54,
 
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    TCG_REG_R55,
 
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    TCG_REG_R56,
 
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    TCG_REG_R57,
 
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    TCG_REG_R58,
 
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    TCG_REG_R59,
 
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    TCG_REG_R60,
 
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    TCG_REG_R61,
 
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    TCG_REG_R62,
 
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    TCG_REG_R63,
 
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} TCGReg;
 
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#define TCG_CT_CONST_ZERO 0x100
 
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#define TCG_CT_CONST_S22 0x200
 
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/* used for function call generation */
 
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#define TCG_REG_CALL_STACK TCG_REG_R12
 
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#define TCG_TARGET_STACK_ALIGN 16
 
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#define TCG_TARGET_CALL_STACK_OFFSET 16
 
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/* optional instructions */
 
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#define TCG_TARGET_HAS_div_i32          0
 
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#define TCG_TARGET_HAS_div_i64          0
 
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#define TCG_TARGET_HAS_andc_i32         1
 
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#define TCG_TARGET_HAS_andc_i64         1
 
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#define TCG_TARGET_HAS_bswap16_i32      1
 
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#define TCG_TARGET_HAS_bswap16_i64      1
 
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#define TCG_TARGET_HAS_bswap32_i32      1
 
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#define TCG_TARGET_HAS_bswap32_i64      1
 
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#define TCG_TARGET_HAS_bswap64_i64      1
 
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#define TCG_TARGET_HAS_eqv_i32          1
 
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#define TCG_TARGET_HAS_eqv_i64          1
 
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#define TCG_TARGET_HAS_ext8s_i32        1
 
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#define TCG_TARGET_HAS_ext16s_i32       1
 
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#define TCG_TARGET_HAS_ext8s_i64        1
 
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#define TCG_TARGET_HAS_ext16s_i64       1
 
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#define TCG_TARGET_HAS_ext32s_i64       1
 
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#define TCG_TARGET_HAS_ext8u_i32        1
 
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#define TCG_TARGET_HAS_ext16u_i32       1
 
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#define TCG_TARGET_HAS_ext8u_i64        1
 
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#define TCG_TARGET_HAS_ext16u_i64       1
 
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#define TCG_TARGET_HAS_ext32u_i64       1
 
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#define TCG_TARGET_HAS_nand_i32         1
 
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#define TCG_TARGET_HAS_nand_i64         1
 
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#define TCG_TARGET_HAS_nor_i32          1
 
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#define TCG_TARGET_HAS_nor_i64          1
 
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#define TCG_TARGET_HAS_orc_i32          1
 
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#define TCG_TARGET_HAS_orc_i64          1
 
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#define TCG_TARGET_HAS_rot_i32          1
 
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#define TCG_TARGET_HAS_rot_i64          1
 
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#define TCG_TARGET_HAS_deposit_i32      0
 
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#define TCG_TARGET_HAS_deposit_i64      0
 
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/* optional instructions automatically implemented */
 
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#define TCG_TARGET_HAS_neg_i32          0 /* sub r1, r0, r3 */
 
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#define TCG_TARGET_HAS_neg_i64          0 /* sub r1, r0, r3 */
 
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#define TCG_TARGET_HAS_not_i32          0 /* xor r1, -1, r3 */
 
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#define TCG_TARGET_HAS_not_i64          0 /* xor r1, -1, r3 */
 
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/* Note: must be synced with dyngen-exec.h */
 
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#define TCG_AREG0 TCG_REG_R7
 
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/* Guest base is supported */
 
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#define TCG_TARGET_HAS_GUEST_BASE
 
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static inline void flush_icache_range(unsigned long start, unsigned long stop)
 
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{
 
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    start = start & ~(32UL - 1UL);
 
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    stop = (stop + (32UL - 1UL)) & ~(32UL - 1UL);
 
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    for (; start < stop; start += 32UL) {
 
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        asm volatile ("fc.i %0" :: "r" (start));
 
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    }
 
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    asm volatile (";;sync.i;;srlz.i;;");
 
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}