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Viewing changes to Source/Core/Core/Src/PowerPC/PPCCache.cpp

  • Committer: Sérgio Benjamim
  • Date: 2015-02-13 05:54:40 UTC
  • Revision ID: sergio_br2@yahoo.com.br-20150213055440-ey2rt3sjpy27km78
Dolphin Triforce branch from code.google, commit b957980 (4.0-315).

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Source/Core/Core/Src/PowerPC/PPCCache.cpp
 
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// Copyright 2013 Dolphin Emulator Project
 
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// Licensed under GPLv2
 
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// Refer to the license.txt file included.
 
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#include "PPCCache.h"
 
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#include "../HW/Memmap.h"
 
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#include "PowerPC.h"
 
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#include "JitCommon/JitBase.h"
 
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#include "JitCommon/JitCache.h"
 
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#include "JitInterface.h"
 
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namespace PowerPC
 
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{
 
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        const u32 plru_mask[8] = {11,11,19,19,37,37,69,69};
 
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        const u32 plru_value[8] = {11,3,17,1,36,4,64,0};
 
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        InstructionCache::InstructionCache()
 
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        {
 
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                for (u32 m = 0; m < 0xff; m++)
 
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                {
 
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                        u32 w = 0;
 
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                        while (m & (1<<w)) w++;
 
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                        way_from_valid[m] = w;
 
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                }
 
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                for (u32 m = 0; m < 128; m++)
 
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                {
 
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                        u32 b[7];
 
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                        for (int i = 0; i < 7; i++) b[i] = m & (1<<i);
 
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                        u32 w;
 
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                        if (b[0])
 
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                                if (b[2])
 
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                                        if (b[6])
 
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                                                w = 7;
 
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                                        else
 
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                                                w = 6;
 
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                                else
 
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                                        if (b[5])
 
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                                                w = 5;
 
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                                        else
 
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                                                w = 4;
 
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                        else
 
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                                if (b[1])
 
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                                        if (b[4])
 
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                                                w = 3;
 
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                                        else
 
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                                                w = 2;
 
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                                else
 
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                                        if (b[3])
 
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                                                w = 1;
 
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                                        else
 
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                                                w = 0;
 
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                        way_from_plru[m] = w;
 
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                }
 
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        }
 
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        void InstructionCache::Reset()
 
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        {
 
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                memset(valid, 0, sizeof(valid));
 
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                memset(plru, 0, sizeof(plru));
 
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#ifdef FAST_ICACHE
 
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                memset(lookup_table, 0xff, sizeof(lookup_table));
 
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                memset(lookup_table_ex, 0xff, sizeof(lookup_table_ex));
 
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                memset(lookup_table_vmem, 0xff, sizeof(lookup_table_vmem));
 
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#endif
 
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                JitInterface::ClearSafe();
 
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        }
 
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        void InstructionCache::Init()
 
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        {
 
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                memset(data, 0, sizeof(data));
 
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                memset(tags, 0, sizeof(tags));
 
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                memset(way_from_valid, 0, sizeof(way_from_valid));
 
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                memset(way_from_plru, 0, sizeof(way_from_plru));
 
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                Reset();
 
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        }
 
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        void InstructionCache::Invalidate(u32 addr)
 
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        {
 
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                if (!HID0.ICE)
 
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                        return;
 
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                // invalidates the whole set
 
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                u32 set = (addr >> 5) & 0x7f;
 
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#ifdef FAST_ICACHE
 
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                for (int i = 0; i < 8; i++)
 
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                        if (valid[set] & (1<<i))
 
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                        {
 
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                                if (tags[set][i] & (ICACHE_VMEM_BIT >> 12))
 
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                                        lookup_table_vmem[((tags[set][i] << 7) | set) & 0xfffff] = 0xff;
 
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                                else if (tags[set][i] & (ICACHE_EXRAM_BIT >> 12))
 
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                                        lookup_table_ex[((tags[set][i] << 7) | set) & 0x1fffff] = 0xff;
 
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                                else
 
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                                        lookup_table[((tags[set][i] << 7) | set) & 0xfffff] = 0xff;
 
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                        }
 
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#endif
 
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                valid[set] = 0;
 
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                JitInterface::InvalidateICache(addr & ~0x1f, 32);
 
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        }
 
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        u32 InstructionCache::ReadInstruction(u32 addr)
 
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        {               
 
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                if (!HID0.ICE) // instruction cache is disabled
 
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                        return Memory::ReadUnchecked_U32(addr);
 
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                u32 set = (addr >> 5) & 0x7f;
 
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                u32 tag = addr >> 12;
 
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#ifdef FAST_ICACHE
 
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                u32 t;
 
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                if (addr & ICACHE_VMEM_BIT)
 
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                {
 
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                        t = lookup_table_vmem[(addr>>5) & 0xfffff];
 
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                }
 
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                else if (addr & ICACHE_EXRAM_BIT)
 
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                {
 
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                        t = lookup_table_ex[(addr>>5) & 0x1fffff];
 
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                }
 
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                else
 
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                {
 
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                        t = lookup_table[(addr>>5) & 0xfffff];
 
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                }
 
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#else
 
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                u32 t = 0xff;
 
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                for (u32 i = 0; i < 8; i++)
 
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                        if (tags[set][i] == tag && (valid[set] & (1<<i)))
 
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                        {
 
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                                t = i;
 
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                                break;
 
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                        }
 
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#endif
 
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                if (t == 0xff) // load to the cache
 
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                {
 
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                        if (HID0.ILOCK) // instruction cache is locked
 
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                                return Memory::ReadUnchecked_U32(addr);
 
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                        // select a way
 
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                        if (valid[set] != 0xff)
 
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                                t = way_from_valid[valid[set]];
 
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                        else
 
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                                t = way_from_plru[plru[set]];
 
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                        // load
 
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                        u8 *p = Memory::GetPointer(addr & ~0x1f);
 
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                        memcpy(data[set][t], p, 32);
 
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#ifdef FAST_ICACHE
 
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                        if (valid[set] & (1<<t))
 
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                        {
 
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                                if (tags[set][t] & (ICACHE_VMEM_BIT >> 12))
 
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                                        lookup_table_vmem[((tags[set][t] << 7) | set) & 0xfffff] = 0xff;
 
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                                else if (tags[set][t] & (ICACHE_EXRAM_BIT >> 12))
 
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                                        lookup_table_ex[((tags[set][t] << 7) | set) & 0x1fffff] = 0xff;
 
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                                else
 
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                                        lookup_table[((tags[set][t] << 7) | set) & 0xfffff] = 0xff;
 
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                        }
 
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                        if (addr & ICACHE_VMEM_BIT)
 
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                                lookup_table_vmem[(addr>>5) & 0xfffff] = t;
 
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                        else if (addr & ICACHE_EXRAM_BIT)
 
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                                lookup_table_ex[(addr>>5) & 0x1fffff] = t;
 
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                        else
 
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                                lookup_table[(addr>>5) & 0xfffff] = t;
 
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#endif
 
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                        tags[set][t] = tag;
 
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                        valid[set] |= 1<<t;
 
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                }
 
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                // update plru
 
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                plru[set] = (plru[set] & ~plru_mask[t]) | plru_value[t];
 
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                u32 res = Common::swap32(data[set][t][(addr>>2)&7]);
 
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                return res;
 
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        }
 
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}