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//=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===//
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// The LLVM Compiler Infrastructure
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//===----------------------------------------------------------------------===//
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// This file describes an abstract interface used to get information about a
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// target machines register file. This information is used for a variety of
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// purposed, especially register allocation.
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_TARGETREGISTERINFO_H
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#define LLVM_TARGET_TARGETREGISTERINFO_H
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/ADT/DenseSet.h"
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class MachineFunction;
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template<class T> class SmallVectorImpl;
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/// TargetRegisterDesc - This record contains all of the information known about
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/// a particular register. The AliasSet field (if not null) contains a pointer
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/// to a Zero terminated array of registers that this register aliases. This is
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/// needed for architectures like X86 which have AL alias AX alias EAX.
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/// Registers that this does not apply to simply should set this to null.
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/// The SubRegs field is a zero terminated array of registers that are
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/// sub-registers of the specific register, e.g. AL, AH are sub-registers of AX.
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/// The SuperRegs field is a zero terminated array of registers that are
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/// super-registers of the specific register, e.g. RAX, EAX, are super-registers
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struct TargetRegisterDesc {
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const char *Name; // Printable name for the reg (for debugging)
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const unsigned *AliasSet; // Register Alias Set, described above
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const unsigned *SubRegs; // Sub-register set, described above
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const unsigned *SuperRegs; // Super-register set, described above
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class TargetRegisterClass {
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typedef const unsigned* iterator;
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typedef const unsigned* const_iterator;
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typedef const EVT* vt_iterator;
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typedef const TargetRegisterClass* const * sc_iterator;
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const vt_iterator VTs;
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const sc_iterator SubClasses;
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const sc_iterator SuperClasses;
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const sc_iterator SubRegClasses;
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const sc_iterator SuperRegClasses;
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const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
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const iterator RegsBegin, RegsEnd;
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DenseSet<unsigned> RegSet;
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TargetRegisterClass(unsigned id,
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const TargetRegisterClass * const *subcs,
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const TargetRegisterClass * const *supcs,
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const TargetRegisterClass * const *subregcs,
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const TargetRegisterClass * const *superregcs,
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unsigned RS, unsigned Al, int CC,
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iterator RB, iterator RE)
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: ID(id), Name(name), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
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SubRegClasses(subregcs), SuperRegClasses(superregcs),
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RegSize(RS), Alignment(Al), CopyCost(CC), RegsBegin(RB), RegsEnd(RE) {
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for (iterator I = RegsBegin, E = RegsEnd; I != E; ++I)
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virtual ~TargetRegisterClass() {} // Allow subclasses
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/// getID() - Return the register class ID number.
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unsigned getID() const { return ID; }
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/// getName() - Return the register class name for debugging.
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const char *getName() const { return Name; }
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/// begin/end - Return all of the registers in this class.
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iterator begin() const { return RegsBegin; }
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iterator end() const { return RegsEnd; }
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/// getNumRegs - Return the number of registers in this class.
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unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); }
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/// getRegister - Return the specified register in the class.
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unsigned getRegister(unsigned i) const {
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assert(i < getNumRegs() && "Register number out of range!");
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/// contains - Return true if the specified register is included in this
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/// register class. This does not include virtual registers.
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bool contains(unsigned Reg) const {
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return RegSet.count(Reg);
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/// contains - Return true if both registers are in this class.
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bool contains(unsigned Reg1, unsigned Reg2) const {
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return contains(Reg1) && contains(Reg2);
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/// hasType - return true if this TargetRegisterClass has the ValueType vt.
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bool hasType(EVT vt) const {
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for(int i = 0; VTs[i].getSimpleVT().SimpleTy != MVT::Other; ++i)
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/// vt_begin / vt_end - Loop over all of the value types that can be
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/// represented by values in this register class.
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vt_iterator vt_begin() const {
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vt_iterator vt_end() const {
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while (I->getSimpleVT().SimpleTy != MVT::Other) ++I;
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/// subregclasses_begin / subregclasses_end - Loop over all of
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/// the subreg register classes of this register class.
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sc_iterator subregclasses_begin() const {
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return SubRegClasses;
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sc_iterator subregclasses_end() const {
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sc_iterator I = SubRegClasses;
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while (*I != NULL) ++I;
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/// getSubRegisterRegClass - Return the register class of subregisters with
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/// index SubIdx, or NULL if no such class exists.
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const TargetRegisterClass* getSubRegisterRegClass(unsigned SubIdx) const {
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assert(SubIdx>0 && "Invalid subregister index");
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return SubRegClasses[SubIdx-1];
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/// superregclasses_begin / superregclasses_end - Loop over all of
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/// the superreg register classes of this register class.
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sc_iterator superregclasses_begin() const {
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return SuperRegClasses;
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sc_iterator superregclasses_end() const {
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sc_iterator I = SuperRegClasses;
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while (*I != NULL) ++I;
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/// hasSubClass - return true if the specified TargetRegisterClass
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/// is a proper subset of this TargetRegisterClass.
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bool hasSubClass(const TargetRegisterClass *cs) const {
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for (int i = 0; SubClasses[i] != NULL; ++i)
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if (SubClasses[i] == cs)
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/// subclasses_begin / subclasses_end - Loop over all of the classes
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/// that are proper subsets of this register class.
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sc_iterator subclasses_begin() const {
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sc_iterator subclasses_end() const {
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sc_iterator I = SubClasses;
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while (*I != NULL) ++I;
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/// hasSuperClass - return true if the specified TargetRegisterClass is a
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/// proper superset of this TargetRegisterClass.
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bool hasSuperClass(const TargetRegisterClass *cs) const {
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for (int i = 0; SuperClasses[i] != NULL; ++i)
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if (SuperClasses[i] == cs)
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/// superclasses_begin / superclasses_end - Loop over all of the classes
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/// that are proper supersets of this register class.
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sc_iterator superclasses_begin() const {
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sc_iterator superclasses_end() const {
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sc_iterator I = SuperClasses;
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while (*I != NULL) ++I;
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/// isASubClass - return true if this TargetRegisterClass is a subset
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/// class of at least one other TargetRegisterClass.
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bool isASubClass() const {
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return SuperClasses[0] != 0;
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/// allocation_order_begin/end - These methods define a range of registers
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/// which specify the registers in this class that are valid to register
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/// allocate, and the preferred order to allocate them in. For example,
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/// callee saved registers should be at the end of the list, because it is
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/// cheaper to allocate caller saved registers.
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/// These methods take a MachineFunction argument, which can be used to tune
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/// the allocatable registers based on the characteristics of the function.
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/// One simple example is that the frame pointer register can be used if
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/// frame-pointer-elimination is performed.
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/// By default, these methods return all registers in the class.
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virtual iterator allocation_order_begin(const MachineFunction &MF) const {
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virtual iterator allocation_order_end(const MachineFunction &MF) const {
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/// getSize - Return the size of the register in bytes, which is also the size
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/// of a stack slot allocated to hold a spilled copy of this register.
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unsigned getSize() const { return RegSize; }
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/// getAlignment - Return the minimum required alignment for a register of
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unsigned getAlignment() const { return Alignment; }
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/// getCopyCost - Return the cost of copying a value between two registers in
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/// this class. A negative number means the register class is very expensive
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/// to copy e.g. status flag register classes.
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int getCopyCost() const { return CopyCost; }
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/// TargetRegisterInfo base class - We assume that the target defines a static
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/// array of TargetRegisterDesc objects that represent all of the machine
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/// registers that the target has. As such, we simply have to track a pointer
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/// to this array so that we can turn register number into a register
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class TargetRegisterInfo {
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const unsigned* SubregHash;
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const unsigned SubregHashSize;
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const unsigned* AliasesHash;
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const unsigned AliasesHashSize;
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typedef const TargetRegisterClass * const * regclass_iterator;
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const TargetRegisterDesc *Desc; // Pointer to the descriptor array
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const char *const *SubRegIndexNames; // Names of subreg indexes.
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unsigned NumRegs; // Number of entries in the array
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regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
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int CallFrameSetupOpcode, CallFrameDestroyOpcode;
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TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
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regclass_iterator RegClassBegin,
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regclass_iterator RegClassEnd,
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const char *const *subregindexnames,
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int CallFrameSetupOpcode = -1,
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int CallFrameDestroyOpcode = -1,
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const unsigned* subregs = 0,
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const unsigned subregsize = 0,
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const unsigned* aliases = 0,
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const unsigned aliasessize = 0);
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virtual ~TargetRegisterInfo();
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enum { // Define some target independent constants
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/// NoRegister - This physical register is not a real target register. It
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/// is useful as a sentinal.
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/// FirstVirtualRegister - This is the first register number that is
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/// considered to be a 'virtual' register, which is part of the SSA
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/// namespace. This must be the same for all targets, which means that each
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/// target is limited to this fixed number of registers.
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FirstVirtualRegister = 16384
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/// isPhysicalRegister - Return true if the specified register number is in
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/// the physical register namespace.
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static bool isPhysicalRegister(unsigned Reg) {
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assert(Reg && "this is not a register!");
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return Reg < FirstVirtualRegister;
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/// isVirtualRegister - Return true if the specified register number is in
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/// the virtual register namespace.
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static bool isVirtualRegister(unsigned Reg) {
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assert(Reg && "this is not a register!");
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return Reg >= FirstVirtualRegister;
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/// getMinimalPhysRegClass - Returns the Register Class of a physical
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/// register of the given type, picking the most sub register class of
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/// the right type that contains this physreg.
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const TargetRegisterClass *
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getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const;
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/// getAllocatableSet - Returns a bitset indexed by register number
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/// indicating if a register is allocatable or not. If a register class is
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/// specified, returns the subset for the class.
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BitVector getAllocatableSet(const MachineFunction &MF,
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const TargetRegisterClass *RC = NULL) const;
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const TargetRegisterDesc &operator[](unsigned RegNo) const {
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assert(RegNo < NumRegs &&
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"Attempting to access record for invalid register number!");
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/// Provide a get method, equivalent to [], but more useful if we have a
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/// pointer to this object.
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const TargetRegisterDesc &get(unsigned RegNo) const {
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return operator[](RegNo);
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/// getAliasSet - Return the set of registers aliased by the specified
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/// register, or a null list of there are none. The list returned is zero
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const unsigned *getAliasSet(unsigned RegNo) const {
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return get(RegNo).AliasSet;
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/// getSubRegisters - Return the list of registers that are sub-registers of
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/// the specified register, or a null list of there are none. The list
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/// returned is zero terminated and sorted according to super-sub register
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/// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH.
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const unsigned *getSubRegisters(unsigned RegNo) const {
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return get(RegNo).SubRegs;
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/// getSuperRegisters - Return the list of registers that are super-registers
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/// of the specified register, or a null list of there are none. The list
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/// returned is zero terminated and sorted according to super-sub register
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/// relations. e.g. X86::AL's super-register list is RAX, EAX, AX.
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const unsigned *getSuperRegisters(unsigned RegNo) const {
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return get(RegNo).SuperRegs;
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/// getName - Return the human-readable symbolic target-specific name for the
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/// specified physical register.
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const char *getName(unsigned RegNo) const {
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return get(RegNo).Name;
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/// getNumRegs - Return the number of registers this target has (useful for
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/// sizing arrays holding per register information)
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unsigned getNumRegs() const {
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/// getSubRegIndexName - Return the human-readable symbolic target-specific
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/// name for the specified SubRegIndex.
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const char *getSubRegIndexName(unsigned SubIdx) const {
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assert(SubIdx && "This is not a subregister index");
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return SubRegIndexNames[SubIdx-1];
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/// regsOverlap - Returns true if the two registers are equal or alias each
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/// other. The registers may be virtual register.
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bool regsOverlap(unsigned regA, unsigned regB) const {
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if (isVirtualRegister(regA) || isVirtualRegister(regB))
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// regA and regB are distinct physical registers. Do they alias?
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size_t index = (regA + regB * 37) & (AliasesHashSize-1);
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unsigned ProbeAmt = 0;
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while (AliasesHash[index*2] != 0 &&
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AliasesHash[index*2+1] != 0) {
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if (AliasesHash[index*2] == regA && AliasesHash[index*2+1] == regB)
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index = (index + ProbeAmt) & (AliasesHashSize-1);
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/// isSubRegister - Returns true if regB is a sub-register of regA.
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bool isSubRegister(unsigned regA, unsigned regB) const {
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// SubregHash is a simple quadratically probed hash table.
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size_t index = (regA + regB * 37) & (SubregHashSize-1);
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unsigned ProbeAmt = 2;
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while (SubregHash[index*2] != 0 &&
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SubregHash[index*2+1] != 0) {
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if (SubregHash[index*2] == regA && SubregHash[index*2+1] == regB)
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index = (index + ProbeAmt) & (SubregHashSize-1);
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/// isSuperRegister - Returns true if regB is a super-register of regA.
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bool isSuperRegister(unsigned regA, unsigned regB) const {
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return isSubRegister(regB, regA);
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/// getCalleeSavedRegs - Return a null-terminated list of all of the
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/// callee saved registers on this target. The register should be in the
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/// order of desired callee-save stack frame offset. The first register is
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/// closed to the incoming stack pointer if stack grows down, and vice versa.
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virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0)
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/// getReservedRegs - Returns a bitset indexed by physical register number
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/// indicating if a register is a special register that has particular uses
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/// and should be considered unavailable at all times, e.g. SP, RA. This is
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/// used by register scavenger to determine what registers are free.
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virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
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/// getSubReg - Returns the physical register number of sub-register "Index"
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/// for physical register RegNo. Return zero if the sub-register does not
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virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
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/// getSubRegIndex - For a given register pair, return the sub-register index
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/// if the second register is a sub-register of the first. Return zero
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virtual unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const = 0;
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/// getMatchingSuperReg - Return a super-register of the specified register
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/// Reg so its sub-register of index SubIdx is Reg.
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unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
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const TargetRegisterClass *RC) const {
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for (const unsigned *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs)
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if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR))
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/// canCombineSubRegIndices - Given a register class and a list of
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/// subregister indices, return true if it's possible to combine the
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/// subregister indices into one that corresponds to a larger
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/// subregister. Return the new subregister index by reference. Note the
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/// new index may be zero if the given subregisters can be combined to
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/// form the whole register.
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virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC,
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SmallVectorImpl<unsigned> &SubIndices,
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unsigned &NewSubIdx) const {
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/// getMatchingSuperRegClass - Return a subclass of the specified register
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/// class A so that each register in it has a sub-register of the
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/// specified sub-register index which is in the specified register class B.
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virtual const TargetRegisterClass *
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getMatchingSuperRegClass(const TargetRegisterClass *A,
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const TargetRegisterClass *B, unsigned Idx) const {
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/// composeSubRegIndices - Return the subregister index you get from composing
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/// two subregister indices.
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/// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b)
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/// returns c. Note that composeSubRegIndices does not tell you about illegal
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/// compositions. If R does not have a subreg a, or R:a does not have a subreg
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/// b, composeSubRegIndices doesn't tell you.
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/// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has
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/// ssub_0:S0 - ssub_3:S3 subregs.
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/// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
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virtual unsigned composeSubRegIndices(unsigned a, unsigned b) const {
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// This default implementation is correct for most targets.
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//===--------------------------------------------------------------------===//
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// Register Class Information
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/// Register class iterators
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regclass_iterator regclass_begin() const { return RegClassBegin; }
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regclass_iterator regclass_end() const { return RegClassEnd; }
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unsigned getNumRegClasses() const {
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return (unsigned)(regclass_end()-regclass_begin());
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/// getRegClass - Returns the register class associated with the enumeration
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/// value. See class TargetOperandInfo.
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const TargetRegisterClass *getRegClass(unsigned i) const {
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assert(i < getNumRegClasses() && "Register Class ID out of range");
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return RegClassBegin[i];
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/// getPointerRegClass - Returns a TargetRegisterClass used for pointer
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/// values. If a target supports multiple different pointer register classes,
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/// kind specifies which one is indicated.
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virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) const {
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assert(0 && "Target didn't implement getPointerRegClass!");
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return 0; // Must return a value in order to compile with VS 2005
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/// getCrossCopyRegClass - Returns a legal register class to copy a register
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/// in the specified class to or from. Returns NULL if it is possible to copy
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/// between a two registers of the specified class.
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virtual const TargetRegisterClass *
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getCrossCopyRegClass(const TargetRegisterClass *RC) const {
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/// getAllocationOrder - Returns the register allocation order for a specified
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/// register class in the form of a pair of TargetRegisterClass iterators.
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virtual std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
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getAllocationOrder(const TargetRegisterClass *RC,
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unsigned HintType, unsigned HintReg,
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const MachineFunction &MF) const {
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return std::make_pair(RC->allocation_order_begin(MF),
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RC->allocation_order_end(MF));
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/// ResolveRegAllocHint - Resolves the specified register allocation hint
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/// to a physical register. Returns the physical register if it is successful.
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virtual unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
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const MachineFunction &MF) const {
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if (Type == 0 && Reg && isPhysicalRegister(Reg))
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/// UpdateRegAllocHint - A callback to allow target a chance to update
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/// register allocation hints when a register is "changed" (e.g. coalesced)
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/// to another register. e.g. On ARM, some virtual registers should target
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/// register pairs, if one of pair is coalesced to another register, the
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/// allocation hint of the other half of the pair should be changed to point
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/// to the new register.
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virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
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MachineFunction &MF) const {
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/// targetHandlesStackFrameRounding - Returns true if the target is
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/// responsible for rounding up the stack frame (probably at emitPrologue
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virtual bool targetHandlesStackFrameRounding() const {
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/// requiresRegisterScavenging - returns true if the target requires (and can
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/// make use of) the register scavenger.
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virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
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/// requiresFrameIndexScavenging - returns true if the target requires post
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/// PEI scavenging of registers for materializing frame index constants.
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virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
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/// requiresVirtualBaseRegisters - Returns true if the target wants the
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/// LocalStackAllocation pass to be run and virtual base registers
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/// used for more efficient stack access.
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virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const {
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/// hasFP - Return true if the specified function should have a dedicated
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/// frame pointer register. For most targets this is true only if the function
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/// has variable sized allocas or if frame pointer elimination is disabled.
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virtual bool hasFP(const MachineFunction &MF) const = 0;
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/// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
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/// not required, we reserve argument space for call sites in the function
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/// immediately on entry to the current function. This eliminates the need for
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/// add/sub sp brackets around call sites. Returns true if the call frame is
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/// included as part of the stack frame.
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virtual bool hasReservedCallFrame(const MachineFunction &MF) const {
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/// canSimplifyCallFramePseudos - When possible, it's best to simplify the
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/// call frame pseudo ops before doing frame index elimination. This is
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/// possible only when frame index references between the pseudos won't
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/// need adjusting for the call frame adjustments. Normally, that's true
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/// if the function has a reserved call frame or a frame pointer. Some
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/// targets (Thumb2, for example) may have more complicated criteria,
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/// however, and can override this behavior.
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virtual bool canSimplifyCallFramePseudos(const MachineFunction &MF) const {
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return hasReservedCallFrame(MF) || hasFP(MF);
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/// hasReservedSpillSlot - Return true if target has reserved a spill slot in
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/// the stack frame of the given function for the specified register. e.g. On
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/// x86, if the frame register is required, the first fixed stack object is
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/// reserved as its spill slot. This tells PEI not to create a new stack frame
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/// object for the given register. It should be called only after
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/// processFunctionBeforeCalleeSavedScan().
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virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
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int &FrameIdx) const {
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/// needsStackRealignment - true if storage within the function requires the
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/// stack pointer to be aligned more than the normal calling convention calls
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virtual bool needsStackRealignment(const MachineFunction &MF) const {
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/// getFrameIndexInstrOffset - Get the offset from the referenced frame
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/// index in the instruction, if the is one.
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virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
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/// needsFrameBaseReg - Returns true if the instruction's frame index
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/// reference would be better served by a base register other than FP
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/// or SP. Used by LocalStackFrameAllocation to determine which frame index
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/// references it should create new base registers for.
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virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
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/// materializeFrameBaseRegister - Insert defining instruction(s) for
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/// BaseReg to be a pointer to FrameIdx before insertion point I.
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virtual void materializeFrameBaseRegister(MachineBasicBlock::iterator I,
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unsigned BaseReg, int FrameIdx,
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int64_t Offset) const {
666
assert(0 && "materializeFrameBaseRegister does not exist on this target");
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/// resolveFrameIndex - Resolve a frame index operand of an instruction
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/// to reference the indicated base register plus offset instead.
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virtual void resolveFrameIndex(MachineBasicBlock::iterator I,
672
unsigned BaseReg, int64_t Offset) const {
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assert(0 && "resolveFrameIndex does not exist on this target");
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/// isFrameOffsetLegal - Determine whether a given offset immediate is
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/// encodable to resolve a frame index.
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virtual bool isFrameOffsetLegal(const MachineInstr *MI,
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int64_t Offset) const {
680
assert(0 && "isFrameOffsetLegal does not exist on this target");
681
return false; // Must return a value in order to compile with VS 2005
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/// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
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/// frame setup/destroy instructions if they exist (-1 otherwise). Some
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/// targets use pseudo instructions in order to abstract away the difference
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/// between operating with a frame pointer and operating without, through the
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/// use of these two instructions.
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int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
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int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
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/// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
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/// code insertion to eliminate call frame setup and destroy pseudo
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/// instructions (but only if the Target is using them). It is responsible
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/// for eliminating these instructions, replacing them with concrete
697
/// instructions. This method need only be implemented if using call frame
698
/// setup/destroy pseudo instructions.
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eliminateCallFramePseudoInstr(MachineFunction &MF,
702
MachineBasicBlock &MBB,
703
MachineBasicBlock::iterator MI) const {
704
assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
705
"eliminateCallFramePseudoInstr must be implemented if using"
706
" call frame setup/destroy pseudo instructions!");
707
assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
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/// processFunctionBeforeCalleeSavedScan - This method is called immediately
711
/// before PrologEpilogInserter scans the physical registers used to determine
712
/// what callee saved registers should be spilled. This method is optional.
713
virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
714
RegScavenger *RS = NULL) const {
718
/// processFunctionBeforeFrameFinalized - This method is called immediately
719
/// before the specified function's frame layout (MF.getFrameInfo()) is
720
/// finalized. Once the frame is finalized, MO_FrameIndex operands are
721
/// replaced with direct constants. This method is optional.
723
virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
726
/// saveScavengerRegister - Spill the register so it can be used by the
727
/// register scavenger. Return true if the register was spilled, false
728
/// otherwise. If this function does not spill the register, the scavenger
729
/// will instead spill it to the emergency spill slot.
731
virtual bool saveScavengerRegister(MachineBasicBlock &MBB,
732
MachineBasicBlock::iterator I,
733
MachineBasicBlock::iterator &UseMI,
734
const TargetRegisterClass *RC,
735
unsigned Reg) const {
739
/// eliminateFrameIndex - This method must be overriden to eliminate abstract
740
/// frame indices from instructions which may use them. The instruction
741
/// referenced by the iterator contains an MO_FrameIndex operand which must be
742
/// eliminated by this method. This method may modify or replace the
743
/// specified instruction, as long as it keeps the iterator pointing at the
744
/// finished product. SPAdj is the SP adjustment due to call frame setup
746
virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
747
int SPAdj, RegScavenger *RS=NULL) const = 0;
749
/// emitProlog/emitEpilog - These methods insert prolog and epilog code into
751
virtual void emitPrologue(MachineFunction &MF) const = 0;
752
virtual void emitEpilogue(MachineFunction &MF,
753
MachineBasicBlock &MBB) const = 0;
755
//===--------------------------------------------------------------------===//
756
/// Debug information queries.
758
/// getDwarfRegNum - Map a target register to an equivalent dwarf register
759
/// number. Returns -1 if there is no equivalent value. The second
760
/// parameter allows targets to use different numberings for EH info and
762
virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;
764
/// getFrameRegister - This method should return the register used as a base
765
/// for values allocated in the current stack frame.
766
virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0;
768
/// getFrameIndexOffset - Returns the displacement from the frame register to
769
/// the stack frame of the specified index.
770
virtual int getFrameIndexOffset(const MachineFunction &MF, int FI) const;
772
/// getFrameIndexReference - This method should return the base register
773
/// and offset used to reference a frame index location. The offset is
774
/// returned directly, and the base register is returned via FrameReg.
775
virtual int getFrameIndexReference(const MachineFunction &MF, int FI,
776
unsigned &FrameReg) const {
777
// By default, assume all frame indices are referenced via whatever
778
// getFrameRegister() says. The target can override this if it's doing
779
// something different.
780
FrameReg = getFrameRegister(MF);
781
return getFrameIndexOffset(MF, FI);
784
/// getRARegister - This method should return the register where the return
785
/// address can be found.
786
virtual unsigned getRARegister() const = 0;
788
/// getInitialFrameState - Returns a list of machine moves that are assumed
789
/// on entry to all functions. Note that LabelID is ignored (assumed to be
790
/// the beginning of the function.)
791
virtual void getInitialFrameState(std::vector<MachineMove> &Moves) const;
795
// This is useful when building IndexedMaps keyed on virtual registers
796
struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> {
797
unsigned operator()(unsigned Reg) const {
798
return Reg - TargetRegisterInfo::FirstVirtualRegister;
802
/// getCommonSubClass - find the largest common subclass of A and B. Return NULL
803
/// if there is no common subclass.
804
const TargetRegisterClass *getCommonSubClass(const TargetRegisterClass *A,
805
const TargetRegisterClass *B);
807
} // End llvm namespace
added
removed
libclamav/c++/llvm/include/llvm/Target/TargetRegisterInfo.h
