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//===----- AggressiveAntiDepBreaker.cpp - Anti-dep breaker ----------------===//
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// The LLVM Compiler Infrastructure
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//===----------------------------------------------------------------------===//
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// This file implements the AggressiveAntiDepBreaker class, which
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// implements register anti-dependence breaking during post-RA
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// scheduling. It attempts to break all anti-dependencies within a
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "post-RA-sched"
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#include "AggressiveAntiDepBreaker.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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// If DebugDiv > 0 then only break antidep with (ID % DebugDiv) == DebugMod
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DebugDiv("agg-antidep-debugdiv",
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cl::desc("Debug control for aggressive anti-dep breaker"),
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cl::init(0), cl::Hidden);
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DebugMod("agg-antidep-debugmod",
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cl::desc("Debug control for aggressive anti-dep breaker"),
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cl::init(0), cl::Hidden);
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AggressiveAntiDepState::AggressiveAntiDepState(const unsigned TargetRegs,
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MachineBasicBlock *BB) :
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NumTargetRegs(TargetRegs), GroupNodes(TargetRegs, 0),
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GroupNodeIndices(TargetRegs, 0),
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KillIndices(TargetRegs, 0),
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DefIndices(TargetRegs, 0)
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const unsigned BBSize = BB->size();
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for (unsigned i = 0; i < NumTargetRegs; ++i) {
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// Initialize all registers to be in their own group. Initially we
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// assign the register to the same-indexed GroupNode.
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GroupNodeIndices[i] = i;
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// Initialize the indices to indicate that no registers are live.
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DefIndices[i] = BBSize;
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unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) {
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unsigned Node = GroupNodeIndices[Reg];
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while (GroupNodes[Node] != Node)
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Node = GroupNodes[Node];
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void AggressiveAntiDepState::GetGroupRegs(
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std::vector<unsigned> &Regs,
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std::multimap<unsigned, AggressiveAntiDepState::RegisterReference> *RegRefs)
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for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) {
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if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0))
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unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2)
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assert(GroupNodes[0] == 0 && "GroupNode 0 not parent!");
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assert(GroupNodeIndices[0] == 0 && "Reg 0 not in Group 0!");
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// find group for each register
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unsigned Group1 = GetGroup(Reg1);
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unsigned Group2 = GetGroup(Reg2);
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// if either group is 0, then that must become the parent
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unsigned Parent = (Group1 == 0) ? Group1 : Group2;
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unsigned Other = (Parent == Group1) ? Group2 : Group1;
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GroupNodes.at(Other) = Parent;
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unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg)
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// Create a new GroupNode for Reg. Reg's existing GroupNode must
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// stay as is because there could be other GroupNodes referring to
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unsigned idx = GroupNodes.size();
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GroupNodes.push_back(idx);
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GroupNodeIndices[Reg] = idx;
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bool AggressiveAntiDepState::IsLive(unsigned Reg)
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// KillIndex must be defined and DefIndex not defined for a register
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return((KillIndices[Reg] != ~0u) && (DefIndices[Reg] == ~0u));
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AggressiveAntiDepBreaker::
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AggressiveAntiDepBreaker(MachineFunction& MFi,
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TargetSubtarget::RegClassVector& CriticalPathRCs) :
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AntiDepBreaker(), MF(MFi),
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MRI(MF.getRegInfo()),
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TII(MF.getTarget().getInstrInfo()),
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TRI(MF.getTarget().getRegisterInfo()),
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AllocatableSet(TRI->getAllocatableSet(MF)),
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/* Collect a bitset of all registers that are only broken if they
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are on the critical path. */
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for (unsigned i = 0, e = CriticalPathRCs.size(); i < e; ++i) {
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BitVector CPSet = TRI->getAllocatableSet(MF, CriticalPathRCs[i]);
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if (CriticalPathSet.none())
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CriticalPathSet = CPSet;
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CriticalPathSet |= CPSet;
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DEBUG(dbgs() << "AntiDep Critical-Path Registers:");
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DEBUG(for (int r = CriticalPathSet.find_first(); r != -1;
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r = CriticalPathSet.find_next(r))
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dbgs() << " " << TRI->getName(r));
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DEBUG(dbgs() << '\n');
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AggressiveAntiDepBreaker::~AggressiveAntiDepBreaker() {
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void AggressiveAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
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assert(State == NULL);
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State = new AggressiveAntiDepState(TRI->getNumRegs(), BB);
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bool IsReturnBlock = (!BB->empty() && BB->back().getDesc().isReturn());
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std::vector<unsigned> &KillIndices = State->GetKillIndices();
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std::vector<unsigned> &DefIndices = State->GetDefIndices();
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// Determine the live-out physregs for this block.
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// In a return block, examine the function live-out regs.
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for (MachineRegisterInfo::liveout_iterator I = MRI.liveout_begin(),
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E = MRI.liveout_end(); I != E; ++I) {
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State->UnionGroups(Reg, 0);
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KillIndices[Reg] = BB->size();
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DefIndices[Reg] = ~0u;
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// Repeat, for all aliases.
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for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
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unsigned AliasReg = *Alias;
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State->UnionGroups(AliasReg, 0);
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KillIndices[AliasReg] = BB->size();
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DefIndices[AliasReg] = ~0u;
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// In a non-return block, examine the live-in regs of all successors.
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// Note a return block can have successors if the return instruction is
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for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
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SE = BB->succ_end(); SI != SE; ++SI)
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for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
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E = (*SI)->livein_end(); I != E; ++I) {
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State->UnionGroups(Reg, 0);
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KillIndices[Reg] = BB->size();
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DefIndices[Reg] = ~0u;
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// Repeat, for all aliases.
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for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
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unsigned AliasReg = *Alias;
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State->UnionGroups(AliasReg, 0);
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KillIndices[AliasReg] = BB->size();
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DefIndices[AliasReg] = ~0u;
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// Mark live-out callee-saved registers. In a return block this is
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// all callee-saved registers. In non-return this is any
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// callee-saved register that is not saved in the prolog.
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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BitVector Pristine = MFI->getPristineRegs(BB);
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for (const unsigned *I = TRI->getCalleeSavedRegs(); *I; ++I) {
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if (!IsReturnBlock && !Pristine.test(Reg)) continue;
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State->UnionGroups(Reg, 0);
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KillIndices[Reg] = BB->size();
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DefIndices[Reg] = ~0u;
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// Repeat, for all aliases.
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for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
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unsigned AliasReg = *Alias;
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State->UnionGroups(AliasReg, 0);
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KillIndices[AliasReg] = BB->size();
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DefIndices[AliasReg] = ~0u;
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void AggressiveAntiDepBreaker::FinishBlock() {
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void AggressiveAntiDepBreaker::Observe(MachineInstr *MI, unsigned Count,
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unsigned InsertPosIndex) {
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assert(Count < InsertPosIndex && "Instruction index out of expected range!");
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std::set<unsigned> PassthruRegs;
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GetPassthruRegs(MI, PassthruRegs);
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PrescanInstruction(MI, Count, PassthruRegs);
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ScanInstruction(MI, Count);
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DEBUG(dbgs() << "Observe: ");
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DEBUG(dbgs() << "\tRegs:");
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std::vector<unsigned> &DefIndices = State->GetDefIndices();
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for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {
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// If Reg is current live, then mark that it can't be renamed as
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// we don't know the extent of its live-range anymore (now that it
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// has been scheduled). If it is not live but was defined in the
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// previous schedule region, then set its def index to the most
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// conservative location (i.e. the beginning of the previous
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if (State->IsLive(Reg)) {
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DEBUG(if (State->GetGroup(Reg) != 0)
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dbgs() << " " << TRI->getName(Reg) << "=g" <<
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State->GetGroup(Reg) << "->g0(region live-out)");
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State->UnionGroups(Reg, 0);
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} else if ((DefIndices[Reg] < InsertPosIndex)
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&& (DefIndices[Reg] >= Count)) {
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DefIndices[Reg] = Count;
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DEBUG(dbgs() << '\n');
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bool AggressiveAntiDepBreaker::IsImplicitDefUse(MachineInstr *MI,
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if (!MO.isReg() || !MO.isImplicit())
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unsigned Reg = MO.getReg();
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MachineOperand *Op = NULL;
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Op = MI->findRegisterUseOperand(Reg, true);
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Op = MI->findRegisterDefOperand(Reg);
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return((Op != NULL) && Op->isImplicit());
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void AggressiveAntiDepBreaker::GetPassthruRegs(MachineInstr *MI,
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std::set<unsigned>& PassthruRegs) {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg()) continue;
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if ((MO.isDef() && MI->isRegTiedToUseOperand(i)) ||
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IsImplicitDefUse(MI, MO)) {
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const unsigned Reg = MO.getReg();
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PassthruRegs.insert(Reg);
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for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
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PassthruRegs.insert(*Subreg);
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/// AntiDepEdges - Return in Edges the anti- and output- dependencies
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/// in SU that we want to consider for breaking.
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static void AntiDepEdges(const SUnit *SU, std::vector<const SDep*>& Edges) {
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SmallSet<unsigned, 4> RegSet;
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for (SUnit::const_pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
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if ((P->getKind() == SDep::Anti) || (P->getKind() == SDep::Output)) {
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unsigned Reg = P->getReg();
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if (RegSet.count(Reg) == 0) {
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Edges.push_back(&*P);
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/// CriticalPathStep - Return the next SUnit after SU on the bottom-up
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static const SUnit *CriticalPathStep(const SUnit *SU) {
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const SDep *Next = 0;
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unsigned NextDepth = 0;
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// Find the predecessor edge with the greatest depth.
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for (SUnit::const_pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
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const SUnit *PredSU = P->getSUnit();
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unsigned PredLatency = P->getLatency();
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unsigned PredTotalLatency = PredSU->getDepth() + PredLatency;
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// In the case of a latency tie, prefer an anti-dependency edge over
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// other types of edges.
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if (NextDepth < PredTotalLatency ||
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(NextDepth == PredTotalLatency && P->getKind() == SDep::Anti)) {
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NextDepth = PredTotalLatency;
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return (Next) ? Next->getSUnit() : 0;
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void AggressiveAntiDepBreaker::HandleLastUse(unsigned Reg, unsigned KillIdx,
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const char *footer) {
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std::vector<unsigned> &KillIndices = State->GetKillIndices();
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std::vector<unsigned> &DefIndices = State->GetDefIndices();
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std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
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RegRefs = State->GetRegRefs();
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if (!State->IsLive(Reg)) {
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KillIndices[Reg] = KillIdx;
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DefIndices[Reg] = ~0u;
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State->LeaveGroup(Reg);
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DEBUG(if (header != NULL) {
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dbgs() << header << TRI->getName(Reg); header = NULL; });
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DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << tag);
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// Repeat for subregisters.
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for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
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unsigned SubregReg = *Subreg;
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if (!State->IsLive(SubregReg)) {
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KillIndices[SubregReg] = KillIdx;
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DefIndices[SubregReg] = ~0u;
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RegRefs.erase(SubregReg);
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State->LeaveGroup(SubregReg);
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DEBUG(if (header != NULL) {
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dbgs() << header << TRI->getName(Reg); header = NULL; });
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DEBUG(dbgs() << " " << TRI->getName(SubregReg) << "->g" <<
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State->GetGroup(SubregReg) << tag);
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DEBUG(if ((header == NULL) && (footer != NULL)) dbgs() << footer);
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void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI,
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std::set<unsigned>& PassthruRegs) {
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std::vector<unsigned> &DefIndices = State->GetDefIndices();
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std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
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RegRefs = State->GetRegRefs();
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// Handle dead defs by simulating a last-use of the register just
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// after the def. A dead def can occur because the def is truely
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// dead, or because only a subregister is live at the def. If we
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// don't do this the dead def will be incorrectly merged into the
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || !MO.isDef()) continue;
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unsigned Reg = MO.getReg();
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if (Reg == 0) continue;
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HandleLastUse(Reg, Count + 1, "", "\tDead Def: ", "\n");
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DEBUG(dbgs() << "\tDef Groups:");
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || !MO.isDef()) continue;
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unsigned Reg = MO.getReg();
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if (Reg == 0) continue;
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DEBUG(dbgs() << " " << TRI->getName(Reg) << "=g" << State->GetGroup(Reg));
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// If MI's defs have a special allocation requirement, don't allow
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// any def registers to be changed. Also assume all registers
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// defined in a call must not be changed (ABI).
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if (MI->getDesc().isCall() || MI->getDesc().hasExtraDefRegAllocReq() ||
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TII->isPredicated(MI)) {
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DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
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State->UnionGroups(Reg, 0);
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// Any aliased that are live at this point are completely or
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// partially defined here, so group those aliases with Reg.
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for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
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unsigned AliasReg = *Alias;
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if (State->IsLive(AliasReg)) {
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State->UnionGroups(Reg, AliasReg);
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DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << "(via " <<
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TRI->getName(AliasReg) << ")");
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// Note register reference...
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const TargetRegisterClass *RC = NULL;
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if (i < MI->getDesc().getNumOperands())
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RC = MI->getDesc().OpInfo[i].getRegClass(TRI);
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AggressiveAntiDepState::RegisterReference RR = { &MO, RC };
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RegRefs.insert(std::make_pair(Reg, RR));
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DEBUG(dbgs() << '\n');
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// Scan the register defs for this instruction and update
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || !MO.isDef()) continue;
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unsigned Reg = MO.getReg();
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if (Reg == 0) continue;
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// Ignore KILLs and passthru registers for liveness...
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if (MI->isKill() || (PassthruRegs.count(Reg) != 0))
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// Update def for Reg and aliases.
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DefIndices[Reg] = Count;
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for (const unsigned *Alias = TRI->getAliasSet(Reg);
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unsigned AliasReg = *Alias;
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DefIndices[AliasReg] = Count;
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void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr *MI,
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DEBUG(dbgs() << "\tUse Groups:");
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std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
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RegRefs = State->GetRegRefs();
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// If MI's uses have special allocation requirement, don't allow
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// any use registers to be changed. Also assume all registers
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// used in a call must not be changed (ABI).
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// FIXME: The issue with predicated instruction is more complex. We are being
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// conservatively here because the kill markers cannot be trusted after
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// %R6<def> = LDR %SP, %reg0, 92, pred:14, pred:%reg0; mem:LD4[FixedStack14]
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// STR %R0, %R6<kill>, %reg0, 0, pred:0, pred:%CPSR; mem:ST4[%395]
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// %R6<def> = LDR %SP, %reg0, 100, pred:0, pred:%CPSR; mem:LD4[FixedStack12]
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// STR %R0, %R6<kill>, %reg0, 0, pred:14, pred:%reg0; mem:ST4[%396](align=8)
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// The first R6 kill is not really a kill since it's killed by a predicated
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// instruction which may not be executed. The second R6 def may or may not
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// re-define R6 so it's not safe to change it since the last R6 use cannot be
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bool Special = MI->getDesc().isCall() ||
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MI->getDesc().hasExtraSrcRegAllocReq() ||
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TII->isPredicated(MI);
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// Scan the register uses for this instruction and update
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// live-ranges, groups and RegRefs.
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || !MO.isUse()) continue;
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unsigned Reg = MO.getReg();
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if (Reg == 0) continue;
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DEBUG(dbgs() << " " << TRI->getName(Reg) << "=g" <<
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State->GetGroup(Reg));
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// It wasn't previously live but now it is, this is a kill. Forget
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// the previous live-range information and start a new live-range
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HandleLastUse(Reg, Count, "(last-use)");
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DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
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State->UnionGroups(Reg, 0);
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// Note register reference...
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const TargetRegisterClass *RC = NULL;
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if (i < MI->getDesc().getNumOperands())
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RC = MI->getDesc().OpInfo[i].getRegClass(TRI);
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AggressiveAntiDepState::RegisterReference RR = { &MO, RC };
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RegRefs.insert(std::make_pair(Reg, RR));
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DEBUG(dbgs() << '\n');
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// Form a group of all defs and uses of a KILL instruction to ensure
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// that all registers are renamed as a group.
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DEBUG(dbgs() << "\tKill Group:");
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unsigned FirstReg = 0;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg()) continue;
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unsigned Reg = MO.getReg();
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if (Reg == 0) continue;
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DEBUG(dbgs() << "=" << TRI->getName(Reg));
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State->UnionGroups(FirstReg, Reg);
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DEBUG(dbgs() << " " << TRI->getName(Reg));
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DEBUG(dbgs() << "->g" << State->GetGroup(FirstReg) << '\n');
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BitVector AggressiveAntiDepBreaker::GetRenameRegisters(unsigned Reg) {
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BitVector BV(TRI->getNumRegs(), false);
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// Check all references that need rewriting for Reg. For each, use
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// the corresponding register class to narrow the set of registers
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// that are appropriate for renaming.
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std::pair<std::multimap<unsigned,
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AggressiveAntiDepState::RegisterReference>::iterator,
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std::multimap<unsigned,
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AggressiveAntiDepState::RegisterReference>::iterator>
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Range = State->GetRegRefs().equal_range(Reg);
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for (std::multimap<unsigned,
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AggressiveAntiDepState::RegisterReference>::iterator Q = Range.first,
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QE = Range.second; Q != QE; ++Q) {
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const TargetRegisterClass *RC = Q->second.RC;
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if (RC == NULL) continue;
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BitVector RCBV = TRI->getAllocatableSet(MF, RC);
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DEBUG(dbgs() << " " << RC->getName());
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bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
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unsigned AntiDepGroupIndex,
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RenameOrderType& RenameOrder,
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std::map<unsigned, unsigned> &RenameMap) {
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std::vector<unsigned> &KillIndices = State->GetKillIndices();
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std::vector<unsigned> &DefIndices = State->GetDefIndices();
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std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
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RegRefs = State->GetRegRefs();
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// Collect all referenced registers in the same group as
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// AntiDepReg. These all need to be renamed together if we are to
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// break the anti-dependence.
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std::vector<unsigned> Regs;
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State->GetGroupRegs(AntiDepGroupIndex, Regs, &RegRefs);
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assert(Regs.size() > 0 && "Empty register group!");
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if (Regs.size() == 0)
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// Find the "superest" register in the group. At the same time,
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// collect the BitVector of registers that can be used to rename
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DEBUG(dbgs() << "\tRename Candidates for Group g" << AntiDepGroupIndex
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std::map<unsigned, BitVector> RenameRegisterMap;
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unsigned SuperReg = 0;
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for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
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unsigned Reg = Regs[i];
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if ((SuperReg == 0) || TRI->isSuperRegister(SuperReg, Reg))
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// If Reg has any references, then collect possible rename regs
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if (RegRefs.count(Reg) > 0) {
593
DEBUG(dbgs() << "\t\t" << TRI->getName(Reg) << ":");
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BitVector BV = GetRenameRegisters(Reg);
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RenameRegisterMap.insert(std::pair<unsigned, BitVector>(Reg, BV));
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DEBUG(dbgs() << " ::");
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DEBUG(for (int r = BV.find_first(); r != -1; r = BV.find_next(r))
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dbgs() << " " << TRI->getName(r));
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DEBUG(dbgs() << "\n");
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// All group registers should be a subreg of SuperReg.
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for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
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unsigned Reg = Regs[i];
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if (Reg == SuperReg) continue;
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bool IsSub = TRI->isSubRegister(SuperReg, Reg);
610
assert(IsSub && "Expecting group subregister");
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// If DebugDiv > 0 then only rename (renamecnt % DebugDiv) == DebugMod
618
static int renamecnt = 0;
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if (renamecnt++ % DebugDiv != DebugMod)
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dbgs() << "*** Performing rename " << TRI->getName(SuperReg) <<
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// Check each possible rename register for SuperReg in round-robin
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// order. If that register is available, and the corresponding
629
// registers are available for the other group subregisters, then we
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// can use those registers to rename.
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// FIXME: Using getMinimalPhysRegClass is very conservative. We should
633
// check every use of the register and find the largest register class
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// that can be used in all of them.
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const TargetRegisterClass *SuperRC =
636
TRI->getMinimalPhysRegClass(SuperReg, MVT::Other);
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const TargetRegisterClass::iterator RB = SuperRC->allocation_order_begin(MF);
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const TargetRegisterClass::iterator RE = SuperRC->allocation_order_end(MF);
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DEBUG(dbgs() << "\tEmpty Super Regclass!!\n");
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DEBUG(dbgs() << "\tFind Registers:");
647
if (RenameOrder.count(SuperRC) == 0)
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RenameOrder.insert(RenameOrderType::value_type(SuperRC, RE));
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const TargetRegisterClass::iterator OrigR = RenameOrder[SuperRC];
651
const TargetRegisterClass::iterator EndR = ((OrigR == RE) ? RB : OrigR);
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TargetRegisterClass::iterator R = OrigR;
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const unsigned NewSuperReg = *R;
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// Don't consider non-allocatable registers
658
if (!AllocatableSet.test(NewSuperReg)) continue;
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// Don't replace a register with itself.
660
if (NewSuperReg == SuperReg) continue;
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DEBUG(dbgs() << " [" << TRI->getName(NewSuperReg) << ':');
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// For each referenced group register (which must be a SuperReg or
666
// a subregister of SuperReg), find the corresponding subregister
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// of NewSuperReg and make sure it is free to be renamed.
668
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
669
unsigned Reg = Regs[i];
671
if (Reg == SuperReg) {
672
NewReg = NewSuperReg;
674
unsigned NewSubRegIdx = TRI->getSubRegIndex(SuperReg, Reg);
675
if (NewSubRegIdx != 0)
676
NewReg = TRI->getSubReg(NewSuperReg, NewSubRegIdx);
679
DEBUG(dbgs() << " " << TRI->getName(NewReg));
681
// Check if Reg can be renamed to NewReg.
682
BitVector BV = RenameRegisterMap[Reg];
683
if (!BV.test(NewReg)) {
684
DEBUG(dbgs() << "(no rename)");
688
// If NewReg is dead and NewReg's most recent def is not before
689
// Regs's kill, it's safe to replace Reg with NewReg. We
690
// must also check all aliases of NewReg, because we can't define a
691
// register when any sub or super is already live.
692
if (State->IsLive(NewReg) || (KillIndices[Reg] > DefIndices[NewReg])) {
693
DEBUG(dbgs() << "(live)");
697
for (const unsigned *Alias = TRI->getAliasSet(NewReg);
699
unsigned AliasReg = *Alias;
700
if (State->IsLive(AliasReg) ||
701
(KillIndices[Reg] > DefIndices[AliasReg])) {
702
DEBUG(dbgs() << "(alias " << TRI->getName(AliasReg) << " live)");
711
// Record that 'Reg' can be renamed to 'NewReg'.
712
RenameMap.insert(std::pair<unsigned, unsigned>(Reg, NewReg));
715
// If we fall-out here, then every register in the group can be
716
// renamed, as recorded in RenameMap.
717
RenameOrder.erase(SuperRC);
718
RenameOrder.insert(RenameOrderType::value_type(SuperRC, R));
719
DEBUG(dbgs() << "]\n");
723
DEBUG(dbgs() << ']');
726
DEBUG(dbgs() << '\n');
728
// No registers are free and available!
732
/// BreakAntiDependencies - Identifiy anti-dependencies within the
733
/// ScheduleDAG and break them by renaming registers.
735
unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
736
const std::vector<SUnit>& SUnits,
737
MachineBasicBlock::iterator Begin,
738
MachineBasicBlock::iterator End,
739
unsigned InsertPosIndex) {
740
std::vector<unsigned> &KillIndices = State->GetKillIndices();
741
std::vector<unsigned> &DefIndices = State->GetDefIndices();
742
std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
743
RegRefs = State->GetRegRefs();
745
// The code below assumes that there is at least one instruction,
746
// so just duck out immediately if the block is empty.
747
if (SUnits.empty()) return 0;
749
// For each regclass the next register to use for renaming.
750
RenameOrderType RenameOrder;
752
// ...need a map from MI to SUnit.
753
std::map<MachineInstr *, const SUnit *> MISUnitMap;
754
for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
755
const SUnit *SU = &SUnits[i];
756
MISUnitMap.insert(std::pair<MachineInstr *, const SUnit *>(SU->getInstr(),
760
// Track progress along the critical path through the SUnit graph as
761
// we walk the instructions. This is needed for regclasses that only
762
// break critical-path anti-dependencies.
763
const SUnit *CriticalPathSU = 0;
764
MachineInstr *CriticalPathMI = 0;
765
if (CriticalPathSet.any()) {
766
for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
767
const SUnit *SU = &SUnits[i];
768
if (!CriticalPathSU ||
769
((SU->getDepth() + SU->Latency) >
770
(CriticalPathSU->getDepth() + CriticalPathSU->Latency))) {
775
CriticalPathMI = CriticalPathSU->getInstr();
779
DEBUG(dbgs() << "\n===== Aggressive anti-dependency breaking\n");
780
DEBUG(dbgs() << "Available regs:");
781
for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
782
if (!State->IsLive(Reg))
783
DEBUG(dbgs() << " " << TRI->getName(Reg));
785
DEBUG(dbgs() << '\n');
788
// Attempt to break anti-dependence edges. Walk the instructions
789
// from the bottom up, tracking information about liveness as we go
790
// to help determine which registers are available.
792
unsigned Count = InsertPosIndex - 1;
793
for (MachineBasicBlock::iterator I = End, E = Begin;
795
MachineInstr *MI = --I;
797
DEBUG(dbgs() << "Anti: ");
800
std::set<unsigned> PassthruRegs;
801
GetPassthruRegs(MI, PassthruRegs);
803
// Process the defs in MI...
804
PrescanInstruction(MI, Count, PassthruRegs);
806
// The dependence edges that represent anti- and output-
807
// dependencies that are candidates for breaking.
808
std::vector<const SDep *> Edges;
809
const SUnit *PathSU = MISUnitMap[MI];
810
AntiDepEdges(PathSU, Edges);
812
// If MI is not on the critical path, then we don't rename
813
// registers in the CriticalPathSet.
814
BitVector *ExcludeRegs = NULL;
815
if (MI == CriticalPathMI) {
816
CriticalPathSU = CriticalPathStep(CriticalPathSU);
817
CriticalPathMI = (CriticalPathSU) ? CriticalPathSU->getInstr() : 0;
819
ExcludeRegs = &CriticalPathSet;
822
// Ignore KILL instructions (they form a group in ScanInstruction
823
// but don't cause any anti-dependence breaking themselves)
825
// Attempt to break each anti-dependency...
826
for (unsigned i = 0, e = Edges.size(); i != e; ++i) {
827
const SDep *Edge = Edges[i];
828
SUnit *NextSU = Edge->getSUnit();
830
if ((Edge->getKind() != SDep::Anti) &&
831
(Edge->getKind() != SDep::Output)) continue;
833
unsigned AntiDepReg = Edge->getReg();
834
DEBUG(dbgs() << "\tAntidep reg: " << TRI->getName(AntiDepReg));
835
assert(AntiDepReg != 0 && "Anti-dependence on reg0?");
837
if (!AllocatableSet.test(AntiDepReg)) {
838
// Don't break anti-dependencies on non-allocatable registers.
839
DEBUG(dbgs() << " (non-allocatable)\n");
841
} else if ((ExcludeRegs != NULL) && ExcludeRegs->test(AntiDepReg)) {
842
// Don't break anti-dependencies for critical path registers
843
// if not on the critical path
844
DEBUG(dbgs() << " (not critical-path)\n");
846
} else if (PassthruRegs.count(AntiDepReg) != 0) {
847
// If the anti-dep register liveness "passes-thru", then
848
// don't try to change it. It will be changed along with
849
// the use if required to break an earlier antidep.
850
DEBUG(dbgs() << " (passthru)\n");
853
// No anti-dep breaking for implicit deps
854
MachineOperand *AntiDepOp = MI->findRegisterDefOperand(AntiDepReg);
855
assert(AntiDepOp != NULL &&
856
"Can't find index for defined register operand");
857
if ((AntiDepOp == NULL) || AntiDepOp->isImplicit()) {
858
DEBUG(dbgs() << " (implicit)\n");
862
// If the SUnit has other dependencies on the SUnit that
863
// it anti-depends on, don't bother breaking the
864
// anti-dependency since those edges would prevent such
865
// units from being scheduled past each other
868
// Also, if there are dependencies on other SUnits with the
869
// same register as the anti-dependency, don't attempt to
871
for (SUnit::const_pred_iterator P = PathSU->Preds.begin(),
872
PE = PathSU->Preds.end(); P != PE; ++P) {
873
if (P->getSUnit() == NextSU ?
874
(P->getKind() != SDep::Anti || P->getReg() != AntiDepReg) :
875
(P->getKind() == SDep::Data && P->getReg() == AntiDepReg)) {
880
for (SUnit::const_pred_iterator P = PathSU->Preds.begin(),
881
PE = PathSU->Preds.end(); P != PE; ++P) {
882
if ((P->getSUnit() == NextSU) && (P->getKind() != SDep::Anti) &&
883
(P->getKind() != SDep::Output)) {
884
DEBUG(dbgs() << " (real dependency)\n");
887
} else if ((P->getSUnit() != NextSU) &&
888
(P->getKind() == SDep::Data) &&
889
(P->getReg() == AntiDepReg)) {
890
DEBUG(dbgs() << " (other dependency)\n");
896
if (AntiDepReg == 0) continue;
899
assert(AntiDepReg != 0);
900
if (AntiDepReg == 0) continue;
902
// Determine AntiDepReg's register group.
903
const unsigned GroupIndex = State->GetGroup(AntiDepReg);
904
if (GroupIndex == 0) {
905
DEBUG(dbgs() << " (zero group)\n");
909
DEBUG(dbgs() << '\n');
911
// Look for a suitable register to use to break the anti-dependence.
912
std::map<unsigned, unsigned> RenameMap;
913
if (FindSuitableFreeRegisters(GroupIndex, RenameOrder, RenameMap)) {
914
DEBUG(dbgs() << "\tBreaking anti-dependence edge on "
915
<< TRI->getName(AntiDepReg) << ":");
917
// Handle each group register...
918
for (std::map<unsigned, unsigned>::iterator
919
S = RenameMap.begin(), E = RenameMap.end(); S != E; ++S) {
920
unsigned CurrReg = S->first;
921
unsigned NewReg = S->second;
923
DEBUG(dbgs() << " " << TRI->getName(CurrReg) << "->" <<
924
TRI->getName(NewReg) << "(" <<
925
RegRefs.count(CurrReg) << " refs)");
927
// Update the references to the old register CurrReg to
928
// refer to the new register NewReg.
929
std::pair<std::multimap<unsigned,
930
AggressiveAntiDepState::RegisterReference>::iterator,
931
std::multimap<unsigned,
932
AggressiveAntiDepState::RegisterReference>::iterator>
933
Range = RegRefs.equal_range(CurrReg);
934
for (std::multimap<unsigned,
935
AggressiveAntiDepState::RegisterReference>::iterator
936
Q = Range.first, QE = Range.second; Q != QE; ++Q) {
937
Q->second.Operand->setReg(NewReg);
938
// If the SU for the instruction being updated has debug
939
// information related to the anti-dependency register, make
940
// sure to update that as well.
941
const SUnit *SU = MISUnitMap[Q->second.Operand->getParent()];
943
for (unsigned i = 0, e = SU->DbgInstrList.size() ; i < e ; ++i) {
944
MachineInstr *DI = SU->DbgInstrList[i];
945
assert (DI->getNumOperands()==3 && DI->getOperand(0).isReg() &&
946
DI->getOperand(0).getReg()
947
&& "Non register dbg_value attached to SUnit!");
948
if (DI->getOperand(0).getReg() == AntiDepReg)
949
DI->getOperand(0).setReg(NewReg);
953
// We just went back in time and modified history; the
954
// liveness information for CurrReg is now inconsistent. Set
955
// the state as if it were dead.
956
State->UnionGroups(NewReg, 0);
957
RegRefs.erase(NewReg);
958
DefIndices[NewReg] = DefIndices[CurrReg];
959
KillIndices[NewReg] = KillIndices[CurrReg];
961
State->UnionGroups(CurrReg, 0);
962
RegRefs.erase(CurrReg);
963
DefIndices[CurrReg] = KillIndices[CurrReg];
964
KillIndices[CurrReg] = ~0u;
965
assert(((KillIndices[CurrReg] == ~0u) !=
966
(DefIndices[CurrReg] == ~0u)) &&
967
"Kill and Def maps aren't consistent for AntiDepReg!");
971
DEBUG(dbgs() << '\n');
976
ScanInstruction(MI, Count);
added
removed
libclamav/c++/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
