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//===------------------------ CalcSpillWeights.cpp ------------------------===//
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// The LLVM Compiler Infrastructure
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "calcspillweights"
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#include "llvm/Function.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/CodeGen/CalcSpillWeights.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SlotIndexes.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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char CalculateSpillWeights::ID = 0;
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INITIALIZE_PASS(CalculateSpillWeights, "calcspillweights",
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"Calculate spill weights", false, false);
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void CalculateSpillWeights::getAnalysisUsage(AnalysisUsage &au) const {
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au.addRequired<LiveIntervals>();
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au.addRequired<MachineLoopInfo>();
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MachineFunctionPass::getAnalysisUsage(au);
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bool CalculateSpillWeights::runOnMachineFunction(MachineFunction &fn) {
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DEBUG(dbgs() << "********** Compute Spill Weights **********\n"
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<< "********** Function: "
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<< fn.getFunction()->getName() << '\n');
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LiveIntervals &lis = getAnalysis<LiveIntervals>();
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VirtRegAuxInfo vrai(fn, lis, getAnalysis<MachineLoopInfo>());
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for (LiveIntervals::iterator I = lis.begin(), E = lis.end(); I != E; ++I) {
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LiveInterval &li = *I->second;
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if (TargetRegisterInfo::isVirtualRegister(li.reg))
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vrai.CalculateWeightAndHint(li);
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// Return the preferred allocation register for reg, given a COPY instruction.
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static unsigned copyHint(const MachineInstr *mi, unsigned reg,
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const TargetRegisterInfo &tri,
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const MachineRegisterInfo &mri) {
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unsigned sub, hreg, hsub;
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if (mi->getOperand(0).getReg() == reg) {
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sub = mi->getOperand(0).getSubReg();
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hreg = mi->getOperand(1).getReg();
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hsub = mi->getOperand(1).getSubReg();
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sub = mi->getOperand(1).getSubReg();
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hreg = mi->getOperand(0).getReg();
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hsub = mi->getOperand(0).getSubReg();
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if (TargetRegisterInfo::isVirtualRegister(hreg))
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return sub == hsub ? hreg : 0;
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const TargetRegisterClass *rc = mri.getRegClass(reg);
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// Only allow physreg hints in rc.
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return rc->contains(hreg) ? hreg : 0;
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// reg:sub should match the physreg hreg.
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return tri.getMatchingSuperReg(hreg, sub, rc);
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void VirtRegAuxInfo::CalculateWeightAndHint(LiveInterval &li) {
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MachineRegisterInfo &mri = mf_.getRegInfo();
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const TargetRegisterInfo &tri = *mf_.getTarget().getRegisterInfo();
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MachineBasicBlock *mbb = 0;
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MachineLoop *loop = 0;
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unsigned loopDepth = 0;
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bool isExiting = false;
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float totalWeight = 0;
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SmallPtrSet<MachineInstr*, 8> visited;
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// Find the best physreg hist and the best virtreg hint.
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float bestPhys = 0, bestVirt = 0;
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unsigned hintPhys = 0, hintVirt = 0;
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// Don't recompute a target specific hint.
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bool noHint = mri.getRegAllocationHint(li.reg).first != 0;
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for (MachineRegisterInfo::reg_iterator I = mri.reg_begin(li.reg);
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MachineInstr *mi = I.skipInstruction();) {
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if (mi->isIdentityCopy() || mi->isImplicitDef() || mi->isDebugValue())
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if (!visited.insert(mi))
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// Get loop info for mi.
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if (mi->getParent() != mbb) {
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mbb = mi->getParent();
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loop = loops_.getLoopFor(mbb);
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loopDepth = loop ? loop->getLoopDepth() : 0;
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isExiting = loop ? loop->isLoopExiting(mbb) : false;
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// Calculate instr weight.
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tie(reads, writes) = mi->readsWritesVirtualRegister(li.reg);
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float weight = LiveIntervals::getSpillWeight(writes, reads, loopDepth);
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// Give extra weight to what looks like a loop induction variable update.
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if (writes && isExiting && lis_.isLiveOutOfMBB(li, mbb))
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totalWeight += weight;
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// Get allocation hints from copies.
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if (noHint || !mi->isCopy())
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unsigned hint = copyHint(mi, li.reg, tri, mri);
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float hweight = hint_[hint] += weight;
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if (TargetRegisterInfo::isPhysicalRegister(hint)) {
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if (hweight > bestPhys && lis_.isAllocatable(hint))
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bestPhys = hweight, hintPhys = hint;
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if (hweight > bestVirt)
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bestVirt = hweight, hintVirt = hint;
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// Always prefer the physreg hint.
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if (unsigned hint = hintPhys ? hintPhys : hintVirt) {
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mri.setRegAllocationHint(li.reg, 0, hint);
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// Weakly boost the spill weifght of hinted registers.
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totalWeight *= 1.01F;
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// Mark li as unspillable if all live ranges are tiny.
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if (li.isZeroLength()) {
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li.markNotSpillable();
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// If all of the definitions of the interval are re-materializable,
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// it is a preferred candidate for spilling. If none of the defs are
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// loads, then it's potentially very cheap to re-materialize.
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// FIXME: this gets much more complicated once we support non-trivial
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// re-materialization.
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SmallVector<LiveInterval*, 4> spillIs;
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if (lis_.isReMaterializable(li, spillIs, isLoad)) {
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li.weight = totalWeight;
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lis_.normalizeSpillWeight(li);
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void VirtRegAuxInfo::CalculateRegClass(unsigned reg) {
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MachineRegisterInfo &mri = mf_.getRegInfo();
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const TargetRegisterInfo *tri = mf_.getTarget().getRegisterInfo();
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const TargetRegisterClass *orc = mri.getRegClass(reg);
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SmallPtrSet<const TargetRegisterClass*,8> rcs;
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for (MachineRegisterInfo::reg_nodbg_iterator I = mri.reg_nodbg_begin(reg),
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E = mri.reg_nodbg_end(); I != E; ++I) {
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// The targets don't have accurate enough regclass descriptions that we can
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// handle subregs. We need something similar to
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// TRI::getMatchingSuperRegClass, but returning a super class instead of a
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if (I.getOperand().getSubReg()) {
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DEBUG(dbgs() << "Cannot handle subregs: " << I.getOperand() << '\n');
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if (const TargetRegisterClass *rc =
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I->getDesc().getRegClass(I.getOperandNo(), tri))
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// If we found no regclass constraints, just leave reg as is.
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// In theory, we could inflate to the largest superclass of reg's existing
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// class, but that might not be legal for the current cpu setting.
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// This could happen if reg is only used by COPY instructions, so we may need
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// to improve on this.
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// Compute the intersection of all classes in rcs.
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// This ought to be independent of iteration order, but if the target register
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// classes don't form a proper algebra, it is possible to get different
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// results. The solution is to make sure the intersection of any two register
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// classes is also a register class or the null set.
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const TargetRegisterClass *rc = 0;
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for (SmallPtrSet<const TargetRegisterClass*,8>::iterator I = rcs.begin(),
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E = rcs.end(); I != E; ++I) {
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rc = rc ? getCommonSubClass(rc, *I) : *I;
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assert(rc && "Incompatible regclass constraints found");
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DEBUG(dbgs() << "Inflating " << orc->getName() << ":%reg" << reg << " to "
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<< rc->getName() <<".\n");
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mri.setRegClass(reg, rc);