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//===- DAGISelMatcherGen.cpp - Matcher generator --------------------------===//
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// The LLVM Compiler Infrastructure
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//===----------------------------------------------------------------------===//
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#include "DAGISelMatcher.h"
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#include "CodeGenDAGPatterns.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringMap.h"
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/// getRegisterValueType - Look up and return the ValueType of the specified
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/// register. If the register is a member of multiple register classes which
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/// have different associated types, return MVT::Other.
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static MVT::SimpleValueType getRegisterValueType(Record *R,
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const CodeGenTarget &T) {
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MVT::SimpleValueType VT = MVT::Other;
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const std::vector<CodeGenRegisterClass> &RCs = T.getRegisterClasses();
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std::vector<Record*>::const_iterator Element;
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for (unsigned rc = 0, e = RCs.size(); rc != e; ++rc) {
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const CodeGenRegisterClass &RC = RCs[rc];
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if (!std::count(RC.Elements.begin(), RC.Elements.end(), R))
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VT = RC.getValueTypeNum(0);
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// If this occurs in multiple register classes, they all have to agree.
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assert(VT == RC.getValueTypeNum(0));
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const PatternToMatch &Pattern;
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const CodeGenDAGPatterns &CGP;
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/// PatWithNoTypes - This is a clone of Pattern.getSrcPattern() that starts
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/// out with all of the types removed. This allows us to insert type checks
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/// as we scan the tree.
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TreePatternNode *PatWithNoTypes;
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/// VariableMap - A map from variable names ('$dst') to the recorded operand
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/// number that they were captured as. These are biased by 1 to make
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StringMap<unsigned> VariableMap;
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/// NextRecordedOperandNo - As we emit opcodes to record matched values in
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/// the RecordedNodes array, this keeps track of which slot will be next to
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unsigned NextRecordedOperandNo;
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/// MatchedChainNodes - This maintains the position in the recorded nodes
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/// array of all of the recorded input nodes that have chains.
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SmallVector<unsigned, 2> MatchedChainNodes;
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/// MatchedFlagResultNodes - This maintains the position in the recorded
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/// nodes array of all of the recorded input nodes that have flag results.
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SmallVector<unsigned, 2> MatchedFlagResultNodes;
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/// MatchedComplexPatterns - This maintains a list of all of the
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/// ComplexPatterns that we need to check. The patterns are known to have
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/// names which were recorded. The second element of each pair is the first
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/// slot number that the OPC_CheckComplexPat opcode drops the matched
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SmallVector<std::pair<const TreePatternNode*,
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unsigned>, 2> MatchedComplexPatterns;
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/// PhysRegInputs - List list has an entry for each explicitly specified
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/// physreg input to the pattern. The first elt is the Register node, the
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/// second is the recorded slot number the input pattern match saved it in.
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SmallVector<std::pair<Record*, unsigned>, 2> PhysRegInputs;
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/// Matcher - This is the top level of the generated matcher, the result.
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/// CurPredicate - As we emit matcher nodes, this points to the latest check
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/// which should have future checks stuck into its Next position.
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Matcher *CurPredicate;
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MatcherGen(const PatternToMatch &pattern, const CodeGenDAGPatterns &cgp);
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delete PatWithNoTypes;
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bool EmitMatcherCode(unsigned Variant);
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void EmitResultCode();
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Matcher *GetMatcher() const { return TheMatcher; }
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Matcher *GetCurPredicate() const { return CurPredicate; }
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void AddMatcher(Matcher *NewNode);
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void InferPossibleTypes();
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// Matcher Generation.
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void EmitMatchCode(const TreePatternNode *N, TreePatternNode *NodeNoTypes);
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void EmitLeafMatchCode(const TreePatternNode *N);
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void EmitOperatorMatchCode(const TreePatternNode *N,
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TreePatternNode *NodeNoTypes);
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// Result Code Generation.
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unsigned getNamedArgumentSlot(StringRef Name) {
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unsigned VarMapEntry = VariableMap[Name];
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assert(VarMapEntry != 0 &&
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"Variable referenced but not defined and not caught earlier!");
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return VarMapEntry-1;
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/// GetInstPatternNode - Get the pattern for an instruction.
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const TreePatternNode *GetInstPatternNode(const DAGInstruction &Ins,
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const TreePatternNode *N);
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void EmitResultOperand(const TreePatternNode *N,
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SmallVectorImpl<unsigned> &ResultOps);
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void EmitResultOfNamedOperand(const TreePatternNode *N,
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SmallVectorImpl<unsigned> &ResultOps);
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void EmitResultLeafAsOperand(const TreePatternNode *N,
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SmallVectorImpl<unsigned> &ResultOps);
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void EmitResultInstructionAsOperand(const TreePatternNode *N,
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SmallVectorImpl<unsigned> &ResultOps);
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void EmitResultSDNodeXFormAsOperand(const TreePatternNode *N,
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SmallVectorImpl<unsigned> &ResultOps);
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} // end anon namespace.
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MatcherGen::MatcherGen(const PatternToMatch &pattern,
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const CodeGenDAGPatterns &cgp)
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: Pattern(pattern), CGP(cgp), NextRecordedOperandNo(0),
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TheMatcher(0), CurPredicate(0) {
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// We need to produce the matcher tree for the patterns source pattern. To do
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// this we need to match the structure as well as the types. To do the type
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// matching, we want to figure out the fewest number of type checks we need to
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// emit. For example, if there is only one integer type supported by a
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// target, there should be no type comparisons at all for integer patterns!
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// To figure out the fewest number of type checks needed, clone the pattern,
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// remove the types, then perform type inference on the pattern as a whole.
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// If there are unresolved types, emit an explicit check for those types,
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// apply the type to the tree, then rerun type inference. Iterate until all
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// types are resolved.
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PatWithNoTypes = Pattern.getSrcPattern()->clone();
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PatWithNoTypes->RemoveAllTypes();
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// If there are types that are manifestly known, infer them.
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InferPossibleTypes();
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/// InferPossibleTypes - As we emit the pattern, we end up generating type
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/// checks and applying them to the 'PatWithNoTypes' tree. As we do this, we
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/// want to propagate implied types as far throughout the tree as possible so
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/// that we avoid doing redundant type checks. This does the type propagation.
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void MatcherGen::InferPossibleTypes() {
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// TP - Get *SOME* tree pattern, we don't care which. It is only used for
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// diagnostics, which we know are impossible at this point.
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TreePattern &TP = *CGP.pf_begin()->second;
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bool MadeChange = true;
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MadeChange = PatWithNoTypes->ApplyTypeConstraints(TP,
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true/*Ignore reg constraints*/);
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errs() << "Type constraint application shouldn't fail!";
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/// AddMatcher - Add a matcher node to the current graph we're building.
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void MatcherGen::AddMatcher(Matcher *NewNode) {
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if (CurPredicate != 0)
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CurPredicate->setNext(NewNode);
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TheMatcher = NewNode;
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CurPredicate = NewNode;
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//===----------------------------------------------------------------------===//
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// Pattern Match Generation
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//===----------------------------------------------------------------------===//
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/// EmitLeafMatchCode - Generate matching code for leaf nodes.
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void MatcherGen::EmitLeafMatchCode(const TreePatternNode *N) {
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assert(N->isLeaf() && "Not a leaf?");
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// Direct match against an integer constant.
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if (IntInit *II = dynamic_cast<IntInit*>(N->getLeafValue())) {
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// If this is the root of the dag we're matching, we emit a redundant opcode
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// check to ensure that this gets folded into the normal top-level
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if (N == Pattern.getSrcPattern()) {
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const SDNodeInfo &NI = CGP.getSDNodeInfo(CGP.getSDNodeNamed("imm"));
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AddMatcher(new CheckOpcodeMatcher(NI));
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return AddMatcher(new CheckIntegerMatcher(II->getValue()));
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DefInit *DI = dynamic_cast<DefInit*>(N->getLeafValue());
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errs() << "Unknown leaf kind: " << *DI << "\n";
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Record *LeafRec = DI->getDef();
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if (// Handle register references. Nothing to do here, they always match.
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LeafRec->isSubClassOf("RegisterClass") ||
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LeafRec->isSubClassOf("PointerLikeRegClass") ||
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LeafRec->isSubClassOf("SubRegIndex") ||
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// Place holder for SRCVALUE nodes. Nothing to do here.
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LeafRec->getName() == "srcvalue")
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// If we have a physreg reference like (mul gpr:$src, EAX) then we need to
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// record the register
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if (LeafRec->isSubClassOf("Register")) {
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AddMatcher(new RecordMatcher("physreg input "+LeafRec->getName(),
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NextRecordedOperandNo));
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PhysRegInputs.push_back(std::make_pair(LeafRec, NextRecordedOperandNo++));
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if (LeafRec->isSubClassOf("ValueType"))
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return AddMatcher(new CheckValueTypeMatcher(LeafRec->getName()));
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if (LeafRec->isSubClassOf("CondCode"))
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return AddMatcher(new CheckCondCodeMatcher(LeafRec->getName()));
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if (LeafRec->isSubClassOf("ComplexPattern")) {
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// We can't model ComplexPattern uses that don't have their name taken yet.
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// The OPC_CheckComplexPattern operation implicitly records the results.
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if (N->getName().empty()) {
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errs() << "We expect complex pattern uses to have names: " << *N << "\n";
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// Remember this ComplexPattern so that we can emit it after all the other
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// structural matches are done.
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MatchedComplexPatterns.push_back(std::make_pair(N, 0));
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errs() << "Unknown leaf kind: " << *N << "\n";
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void MatcherGen::EmitOperatorMatchCode(const TreePatternNode *N,
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TreePatternNode *NodeNoTypes) {
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assert(!N->isLeaf() && "Not an operator?");
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const SDNodeInfo &CInfo = CGP.getSDNodeInfo(N->getOperator());
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// If this is an 'and R, 1234' where the operation is AND/OR and the RHS is
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// a constant without a predicate fn that has more that one bit set, handle
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// this as a special case. This is usually for targets that have special
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// handling of certain large constants (e.g. alpha with it's 8/16/32-bit
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// handling stuff). Using these instructions is often far more efficient
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// than materializing the constant. Unfortunately, both the instcombiner
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// and the dag combiner can often infer that bits are dead, and thus drop
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// them from the mask in the dag. For example, it might turn 'AND X, 255'
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// into 'AND X, 254' if it knows the low bit is set. Emit code that checks
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if ((N->getOperator()->getName() == "and" ||
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N->getOperator()->getName() == "or") &&
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N->getChild(1)->isLeaf() && N->getChild(1)->getPredicateFns().empty() &&
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N->getPredicateFns().empty()) {
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if (IntInit *II = dynamic_cast<IntInit*>(N->getChild(1)->getLeafValue())) {
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if (!isPowerOf2_32(II->getValue())) { // Don't bother with single bits.
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// If this is at the root of the pattern, we emit a redundant
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// CheckOpcode so that the following checks get factored properly under
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// a single opcode check.
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if (N == Pattern.getSrcPattern())
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AddMatcher(new CheckOpcodeMatcher(CInfo));
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// Emit the CheckAndImm/CheckOrImm node.
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if (N->getOperator()->getName() == "and")
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AddMatcher(new CheckAndImmMatcher(II->getValue()));
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AddMatcher(new CheckOrImmMatcher(II->getValue()));
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// Match the LHS of the AND as appropriate.
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AddMatcher(new MoveChildMatcher(0));
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EmitMatchCode(N->getChild(0), NodeNoTypes->getChild(0));
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AddMatcher(new MoveParentMatcher());
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// Check that the current opcode lines up.
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AddMatcher(new CheckOpcodeMatcher(CInfo));
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// If this node has memory references (i.e. is a load or store), tell the
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// interpreter to capture them in the memref array.
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if (N->NodeHasProperty(SDNPMemOperand, CGP))
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AddMatcher(new RecordMemRefMatcher());
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// If this node has a chain, then the chain is operand #0 is the SDNode, and
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// the child numbers of the node are all offset by one.
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if (N->NodeHasProperty(SDNPHasChain, CGP)) {
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// Record the node and remember it in our chained nodes list.
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AddMatcher(new RecordMatcher("'" + N->getOperator()->getName() +
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NextRecordedOperandNo));
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// Remember all of the input chains our pattern will match.
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MatchedChainNodes.push_back(NextRecordedOperandNo++);
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// Don't look at the input chain when matching the tree pattern to the
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// If this node is not the root and the subtree underneath it produces a
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// chain, then the result of matching the node is also produce a chain.
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// Beyond that, this means that we're also folding (at least) the root node
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// into the node that produce the chain (for example, matching
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// "(add reg, (load ptr))" as a add_with_memory on X86). This is
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// problematic, if the 'reg' node also uses the load (say, its chain).
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// | \ DAG's like cheese.
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// It would be invalid to fold XX and LD. In this case, folding the two
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// nodes together would induce a cycle in the DAG, making it a 'cyclic DAG'
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// To prevent this, we emit a dynamic check for legality before allowing
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// this to be folded.
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const TreePatternNode *Root = Pattern.getSrcPattern();
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if (N != Root) { // Not the root of the pattern.
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// If there is a node between the root and this node, then we definitely
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// need to emit the check.
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bool NeedCheck = !Root->hasChild(N);
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// If it *is* an immediate child of the root, we can still need a check if
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// the root SDNode has multiple inputs. For us, this means that it is an
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// intrinsic, has multiple operands, or has other inputs like chain or
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const SDNodeInfo &PInfo = CGP.getSDNodeInfo(Root->getOperator());
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Root->getOperator() == CGP.get_intrinsic_void_sdnode() ||
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Root->getOperator() == CGP.get_intrinsic_w_chain_sdnode() ||
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Root->getOperator() == CGP.get_intrinsic_wo_chain_sdnode() ||
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PInfo.getNumOperands() > 1 ||
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PInfo.hasProperty(SDNPHasChain) ||
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PInfo.hasProperty(SDNPInFlag) ||
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PInfo.hasProperty(SDNPOptInFlag);
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AddMatcher(new CheckFoldableChainNodeMatcher());
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// If this node has an output flag and isn't the root, remember it.
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if (N->NodeHasProperty(SDNPOutFlag, CGP) &&
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N != Pattern.getSrcPattern()) {
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// TODO: This redundantly records nodes with both flags and chains.
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// Record the node and remember it in our chained nodes list.
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AddMatcher(new RecordMatcher("'" + N->getOperator()->getName() +
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"' flag output node",
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NextRecordedOperandNo));
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// Remember all of the nodes with output flags our pattern will match.
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MatchedFlagResultNodes.push_back(NextRecordedOperandNo++);
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// If this node is known to have an input flag or if it *might* have an input
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// flag, capture it as the flag input of the pattern.
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if (N->NodeHasProperty(SDNPOptInFlag, CGP) ||
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N->NodeHasProperty(SDNPInFlag, CGP))
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AddMatcher(new CaptureFlagInputMatcher());
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for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i, ++OpNo) {
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// Get the code suitable for matching this child. Move to the child, check
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// it then move back to the parent.
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AddMatcher(new MoveChildMatcher(OpNo));
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EmitMatchCode(N->getChild(i), NodeNoTypes->getChild(i));
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AddMatcher(new MoveParentMatcher());
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void MatcherGen::EmitMatchCode(const TreePatternNode *N,
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TreePatternNode *NodeNoTypes) {
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// If N and NodeNoTypes don't agree on a type, then this is a case where we
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// need to do a type check. Emit the check, apply the tyep to NodeNoTypes and
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// reinfer any correlated types.
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SmallVector<unsigned, 2> ResultsToTypeCheck;
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for (unsigned i = 0, e = NodeNoTypes->getNumTypes(); i != e; ++i) {
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if (NodeNoTypes->getExtType(i) == N->getExtType(i)) continue;
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NodeNoTypes->setType(i, N->getExtType(i));
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InferPossibleTypes();
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ResultsToTypeCheck.push_back(i);
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// If this node has a name associated with it, capture it in VariableMap. If
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// we already saw this in the pattern, emit code to verify dagness.
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if (!N->getName().empty()) {
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unsigned &VarMapEntry = VariableMap[N->getName()];
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if (VarMapEntry == 0) {
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// If it is a named node, we must emit a 'Record' opcode.
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AddMatcher(new RecordMatcher("$" + N->getName(), NextRecordedOperandNo));
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VarMapEntry = ++NextRecordedOperandNo;
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// If we get here, this is a second reference to a specific name. Since
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// we already have checked that the first reference is valid, we don't
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// have to recursively match it, just check that it's the same as the
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// previously named thing.
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AddMatcher(new CheckSameMatcher(VarMapEntry-1));
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EmitLeafMatchCode(N);
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EmitOperatorMatchCode(N, NodeNoTypes);
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// If there are node predicates for this node, generate their checks.
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for (unsigned i = 0, e = N->getPredicateFns().size(); i != e; ++i)
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AddMatcher(new CheckPredicateMatcher(N->getPredicateFns()[i]));
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for (unsigned i = 0, e = ResultsToTypeCheck.size(); i != e; ++i)
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AddMatcher(new CheckTypeMatcher(N->getType(ResultsToTypeCheck[i]),
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ResultsToTypeCheck[i]));
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/// EmitMatcherCode - Generate the code that matches the predicate of this
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/// pattern for the specified Variant. If the variant is invalid this returns
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/// true and does not generate code, if it is valid, it returns false.
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bool MatcherGen::EmitMatcherCode(unsigned Variant) {
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// If the root of the pattern is a ComplexPattern and if it is specified to
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// match some number of root opcodes, these are considered to be our variants.
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// Depending on which variant we're generating code for, emit the root opcode
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if (const ComplexPattern *CP =
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Pattern.getSrcPattern()->getComplexPatternInfo(CGP)) {
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const std::vector<Record*> &OpNodes = CP->getRootNodes();
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assert(!OpNodes.empty() &&"Complex Pattern must specify what it can match");
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if (Variant >= OpNodes.size()) return true;
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AddMatcher(new CheckOpcodeMatcher(CGP.getSDNodeInfo(OpNodes[Variant])));
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if (Variant != 0) return true;
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// Emit the matcher for the pattern structure and types.
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EmitMatchCode(Pattern.getSrcPattern(), PatWithNoTypes);
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// If the pattern has a predicate on it (e.g. only enabled when a subtarget
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// feature is around, do the check).
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if (!Pattern.getPredicateCheck().empty())
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AddMatcher(new CheckPatternPredicateMatcher(Pattern.getPredicateCheck()));
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// Now that we've completed the structural type match, emit any ComplexPattern
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// checks (e.g. addrmode matches). We emit this after the structural match
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// because they are generally more expensive to evaluate and more difficult to
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for (unsigned i = 0, e = MatchedComplexPatterns.size(); i != e; ++i) {
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const TreePatternNode *N = MatchedComplexPatterns[i].first;
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// Remember where the results of this match get stuck.
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MatchedComplexPatterns[i].second = NextRecordedOperandNo;
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// Get the slot we recorded the value in from the name on the node.
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unsigned RecNodeEntry = VariableMap[N->getName()];
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assert(!N->getName().empty() && RecNodeEntry &&
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"Complex pattern should have a name and slot");
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--RecNodeEntry; // Entries in VariableMap are biased.
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const ComplexPattern &CP =
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CGP.getComplexPattern(((DefInit*)N->getLeafValue())->getDef());
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// Emit a CheckComplexPat operation, which does the match (aborting if it
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// fails) and pushes the matched operands onto the recorded nodes list.
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AddMatcher(new CheckComplexPatMatcher(CP, RecNodeEntry,
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N->getName(), NextRecordedOperandNo));
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// Record the right number of operands.
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NextRecordedOperandNo += CP.getNumOperands();
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if (CP.hasProperty(SDNPHasChain)) {
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// If the complex pattern has a chain, then we need to keep track of the
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// fact that we just recorded a chain input. The chain input will be
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// matched as the last operand of the predicate if it was successful.
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++NextRecordedOperandNo; // Chained node operand.
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// It is the last operand recorded.
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assert(NextRecordedOperandNo > 1 &&
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"Should have recorded input/result chains at least!");
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MatchedChainNodes.push_back(NextRecordedOperandNo-1);
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// TODO: Complex patterns can't have output flags, if they did, we'd want
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//===----------------------------------------------------------------------===//
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// Node Result Generation
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//===----------------------------------------------------------------------===//
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void MatcherGen::EmitResultOfNamedOperand(const TreePatternNode *N,
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SmallVectorImpl<unsigned> &ResultOps){
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assert(!N->getName().empty() && "Operand not named!");
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// A reference to a complex pattern gets all of the results of the complex
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if (const ComplexPattern *CP = N->getComplexPatternInfo(CGP)) {
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for (unsigned i = 0, e = MatchedComplexPatterns.size(); i != e; ++i)
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if (MatchedComplexPatterns[i].first->getName() == N->getName()) {
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SlotNo = MatchedComplexPatterns[i].second;
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assert(SlotNo != 0 && "Didn't get a slot number assigned?");
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// The first slot entry is the node itself, the subsequent entries are the
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for (unsigned i = 0, e = CP->getNumOperands(); i != e; ++i)
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ResultOps.push_back(SlotNo+i);
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unsigned SlotNo = getNamedArgumentSlot(N->getName());
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// If this is an 'imm' or 'fpimm' node, make sure to convert it to the target
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// version of the immediate so that it doesn't get selected due to some other
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StringRef OperatorName = N->getOperator()->getName();
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if (OperatorName == "imm" || OperatorName == "fpimm") {
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AddMatcher(new EmitConvertToTargetMatcher(SlotNo));
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ResultOps.push_back(NextRecordedOperandNo++);
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ResultOps.push_back(SlotNo);
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void MatcherGen::EmitResultLeafAsOperand(const TreePatternNode *N,
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SmallVectorImpl<unsigned> &ResultOps) {
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assert(N->isLeaf() && "Must be a leaf");
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if (IntInit *II = dynamic_cast<IntInit*>(N->getLeafValue())) {
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AddMatcher(new EmitIntegerMatcher(II->getValue(), N->getType(0)));
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ResultOps.push_back(NextRecordedOperandNo++);
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// If this is an explicit register reference, handle it.
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if (DefInit *DI = dynamic_cast<DefInit*>(N->getLeafValue())) {
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if (DI->getDef()->isSubClassOf("Register")) {
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AddMatcher(new EmitRegisterMatcher(DI->getDef(), N->getType(0)));
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ResultOps.push_back(NextRecordedOperandNo++);
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if (DI->getDef()->getName() == "zero_reg") {
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AddMatcher(new EmitRegisterMatcher(0, N->getType(0)));
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ResultOps.push_back(NextRecordedOperandNo++);
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// Handle a reference to a register class. This is used
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// in COPY_TO_SUBREG instructions.
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if (DI->getDef()->isSubClassOf("RegisterClass")) {
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std::string Value = getQualifiedName(DI->getDef()) + "RegClassID";
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AddMatcher(new EmitStringIntegerMatcher(Value, MVT::i32));
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ResultOps.push_back(NextRecordedOperandNo++);
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// Handle a subregister index. This is used for INSERT_SUBREG etc.
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if (DI->getDef()->isSubClassOf("SubRegIndex")) {
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std::string Value = getQualifiedName(DI->getDef());
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AddMatcher(new EmitStringIntegerMatcher(Value, MVT::i32));
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ResultOps.push_back(NextRecordedOperandNo++);
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errs() << "unhandled leaf node: \n";
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/// GetInstPatternNode - Get the pattern for an instruction.
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const TreePatternNode *MatcherGen::
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GetInstPatternNode(const DAGInstruction &Inst, const TreePatternNode *N) {
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const TreePattern *InstPat = Inst.getPattern();
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// FIXME2?: Assume actual pattern comes before "implicit".
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TreePatternNode *InstPatNode;
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InstPatNode = InstPat->getTree(0);
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else if (/*isRoot*/ N == Pattern.getDstPattern())
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InstPatNode = Pattern.getSrcPattern();
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if (InstPatNode && !InstPatNode->isLeaf() &&
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InstPatNode->getOperator()->getName() == "set")
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InstPatNode = InstPatNode->getChild(InstPatNode->getNumChildren()-1);
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EmitResultInstructionAsOperand(const TreePatternNode *N,
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SmallVectorImpl<unsigned> &OutputOps) {
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Record *Op = N->getOperator();
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const CodeGenTarget &CGT = CGP.getTargetInfo();
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CodeGenInstruction &II = CGT.getInstruction(Op);
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const DAGInstruction &Inst = CGP.getInstruction(Op);
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// If we can, get the pattern for the instruction we're generating. We derive
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// a variety of information from this pattern, such as whether it has a chain.
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// FIXME2: This is extremely dubious for several reasons, not the least of
649
// which it gives special status to instructions with patterns that Pat<>
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// nodes can't duplicate.
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const TreePatternNode *InstPatNode = GetInstPatternNode(Inst, N);
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// NodeHasChain - Whether the instruction node we're creating takes chains.
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bool NodeHasChain = InstPatNode &&
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InstPatNode->TreeHasProperty(SDNPHasChain, CGP);
657
bool isRoot = N == Pattern.getDstPattern();
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// TreeHasOutFlag - True if this tree has a flag.
660
bool TreeHasInFlag = false, TreeHasOutFlag = false;
662
const TreePatternNode *SrcPat = Pattern.getSrcPattern();
663
TreeHasInFlag = SrcPat->TreeHasProperty(SDNPOptInFlag, CGP) ||
664
SrcPat->TreeHasProperty(SDNPInFlag, CGP);
666
// FIXME2: this is checking the entire pattern, not just the node in
667
// question, doing this just for the root seems like a total hack.
668
TreeHasOutFlag = SrcPat->TreeHasProperty(SDNPOutFlag, CGP);
671
// NumResults - This is the number of results produced by the instruction in
673
unsigned NumResults = Inst.getNumResults();
675
// Loop over all of the operands of the instruction pattern, emitting code
676
// to fill them all in. The node 'N' usually has number children equal to
677
// the number of input operands of the instruction. However, in cases
678
// where there are predicate operands for an instruction, we need to fill
679
// in the 'execute always' values. Match up the node operands to the
680
// instruction operands to do this.
681
SmallVector<unsigned, 8> InstOps;
682
for (unsigned ChildNo = 0, InstOpNo = NumResults, e = II.OperandList.size();
683
InstOpNo != e; ++InstOpNo) {
685
// Determine what to emit for this operand.
686
Record *OperandNode = II.OperandList[InstOpNo].Rec;
687
if ((OperandNode->isSubClassOf("PredicateOperand") ||
688
OperandNode->isSubClassOf("OptionalDefOperand")) &&
689
!CGP.getDefaultOperand(OperandNode).DefaultOps.empty()) {
690
// This is a predicate or optional def operand; emit the
691
// 'default ops' operands.
692
const DAGDefaultOperand &DefaultOp
693
= CGP.getDefaultOperand(OperandNode);
694
for (unsigned i = 0, e = DefaultOp.DefaultOps.size(); i != e; ++i)
695
EmitResultOperand(DefaultOp.DefaultOps[i], InstOps);
699
const TreePatternNode *Child = N->getChild(ChildNo);
701
// Otherwise this is a normal operand or a predicate operand without
702
// 'execute always'; emit it.
703
unsigned BeforeAddingNumOps = InstOps.size();
704
EmitResultOperand(Child, InstOps);
705
assert(InstOps.size() > BeforeAddingNumOps && "Didn't add any operands");
707
// If the operand is an instruction and it produced multiple results, just
708
// take the first one.
709
if (!Child->isLeaf() && Child->getOperator()->isSubClassOf("Instruction"))
710
InstOps.resize(BeforeAddingNumOps+1);
715
// If this node has an input flag or explicitly specified input physregs, we
716
// need to add chained and flagged copyfromreg nodes and materialize the flag
718
if (isRoot && !PhysRegInputs.empty()) {
719
// Emit all of the CopyToReg nodes for the input physical registers. These
720
// occur in patterns like (mul:i8 AL:i8, GR8:i8:$src).
721
for (unsigned i = 0, e = PhysRegInputs.size(); i != e; ++i)
722
AddMatcher(new EmitCopyToRegMatcher(PhysRegInputs[i].second,
723
PhysRegInputs[i].first));
724
// Even if the node has no other flag inputs, the resultant node must be
725
// flagged to the CopyFromReg nodes we just generated.
726
TreeHasInFlag = true;
729
// Result order: node results, chain, flags
731
// Determine the result types.
732
SmallVector<MVT::SimpleValueType, 4> ResultVTs;
733
for (unsigned i = 0, e = N->getNumTypes(); i != e; ++i)
734
ResultVTs.push_back(N->getType(i));
736
// If this is the root instruction of a pattern that has physical registers in
737
// its result pattern, add output VTs for them. For example, X86 has:
738
// (set AL, (mul ...))
739
// This also handles implicit results like:
741
if (isRoot && !Pattern.getDstRegs().empty()) {
742
// If the root came from an implicit def in the instruction handling stuff,
744
Record *HandledReg = 0;
745
if (II.HasOneImplicitDefWithKnownVT(CGT) != MVT::Other)
746
HandledReg = II.ImplicitDefs[0];
748
for (unsigned i = 0; i != Pattern.getDstRegs().size(); ++i) {
749
Record *Reg = Pattern.getDstRegs()[i];
750
if (!Reg->isSubClassOf("Register") || Reg == HandledReg) continue;
751
ResultVTs.push_back(getRegisterValueType(Reg, CGT));
755
// If this is the root of the pattern and the pattern we're matching includes
756
// a node that is variadic, mark the generated node as variadic so that it
757
// gets the excess operands from the input DAG.
758
int NumFixedArityOperands = -1;
760
(Pattern.getSrcPattern()->NodeHasProperty(SDNPVariadic, CGP)))
761
NumFixedArityOperands = Pattern.getSrcPattern()->getNumChildren();
763
// If this is the root node and any of the nodes matched nodes in the input
764
// pattern have MemRefs in them, have the interpreter collect them and plop
765
// them onto this node.
767
// FIXME3: This is actively incorrect for result patterns where the root of
768
// the pattern is not the memory reference and is also incorrect when the
769
// result pattern has multiple memory-referencing instructions. For example,
770
// in the X86 backend, this pattern causes the memrefs to get attached to the
771
// CVTSS2SDrr instead of the MOVSSrm:
773
// def : Pat<(extloadf32 addr:$src),
774
// (CVTSS2SDrr (MOVSSrm addr:$src))>;
776
bool NodeHasMemRefs =
777
isRoot && Pattern.getSrcPattern()->TreeHasProperty(SDNPMemOperand, CGP);
779
assert((!ResultVTs.empty() || TreeHasOutFlag || NodeHasChain) &&
780
"Node has no result");
782
AddMatcher(new EmitNodeMatcher(II.Namespace+"::"+II.TheDef->getName(),
783
ResultVTs.data(), ResultVTs.size(),
784
InstOps.data(), InstOps.size(),
785
NodeHasChain, TreeHasInFlag, TreeHasOutFlag,
786
NodeHasMemRefs, NumFixedArityOperands,
787
NextRecordedOperandNo));
789
// The non-chain and non-flag results of the newly emitted node get recorded.
790
for (unsigned i = 0, e = ResultVTs.size(); i != e; ++i) {
791
if (ResultVTs[i] == MVT::Other || ResultVTs[i] == MVT::Flag) break;
792
OutputOps.push_back(NextRecordedOperandNo++);
797
EmitResultSDNodeXFormAsOperand(const TreePatternNode *N,
798
SmallVectorImpl<unsigned> &ResultOps) {
799
assert(N->getOperator()->isSubClassOf("SDNodeXForm") && "Not SDNodeXForm?");
802
SmallVector<unsigned, 8> InputOps;
804
// FIXME2: Could easily generalize this to support multiple inputs and outputs
805
// to the SDNodeXForm. For now we just support one input and one output like
806
// the old instruction selector.
807
assert(N->getNumChildren() == 1);
808
EmitResultOperand(N->getChild(0), InputOps);
810
// The input currently must have produced exactly one result.
811
assert(InputOps.size() == 1 && "Unexpected input to SDNodeXForm");
813
AddMatcher(new EmitNodeXFormMatcher(InputOps[0], N->getOperator()));
814
ResultOps.push_back(NextRecordedOperandNo++);
817
void MatcherGen::EmitResultOperand(const TreePatternNode *N,
818
SmallVectorImpl<unsigned> &ResultOps) {
819
// This is something selected from the pattern we matched.
820
if (!N->getName().empty())
821
return EmitResultOfNamedOperand(N, ResultOps);
824
return EmitResultLeafAsOperand(N, ResultOps);
826
Record *OpRec = N->getOperator();
827
if (OpRec->isSubClassOf("Instruction"))
828
return EmitResultInstructionAsOperand(N, ResultOps);
829
if (OpRec->isSubClassOf("SDNodeXForm"))
830
return EmitResultSDNodeXFormAsOperand(N, ResultOps);
831
errs() << "Unknown result node to emit code for: " << *N << '\n';
832
throw std::string("Unknown node in result pattern!");
835
void MatcherGen::EmitResultCode() {
836
// Patterns that match nodes with (potentially multiple) chain inputs have to
837
// merge them together into a token factor. This informs the generated code
838
// what all the chained nodes are.
839
if (!MatchedChainNodes.empty())
840
AddMatcher(new EmitMergeInputChainsMatcher
841
(MatchedChainNodes.data(), MatchedChainNodes.size()));
843
// Codegen the root of the result pattern, capturing the resulting values.
844
SmallVector<unsigned, 8> Ops;
845
EmitResultOperand(Pattern.getDstPattern(), Ops);
847
// At this point, we have however many values the result pattern produces.
848
// However, the input pattern might not need all of these. If there are
849
// excess values at the end (such as implicit defs of condition codes etc)
850
// just lop them off. This doesn't need to worry about flags or chains, just
853
unsigned NumSrcResults = Pattern.getSrcPattern()->getNumTypes();
855
// If the pattern also has (implicit) results, count them as well.
856
if (!Pattern.getDstRegs().empty()) {
857
// If the root came from an implicit def in the instruction handling stuff,
859
Record *HandledReg = 0;
860
const TreePatternNode *DstPat = Pattern.getDstPattern();
861
if (!DstPat->isLeaf() &&DstPat->getOperator()->isSubClassOf("Instruction")){
862
const CodeGenTarget &CGT = CGP.getTargetInfo();
863
CodeGenInstruction &II = CGT.getInstruction(DstPat->getOperator());
865
if (II.HasOneImplicitDefWithKnownVT(CGT) != MVT::Other)
866
HandledReg = II.ImplicitDefs[0];
869
for (unsigned i = 0; i != Pattern.getDstRegs().size(); ++i) {
870
Record *Reg = Pattern.getDstRegs()[i];
871
if (!Reg->isSubClassOf("Register") || Reg == HandledReg) continue;
876
assert(Ops.size() >= NumSrcResults && "Didn't provide enough results");
877
Ops.resize(NumSrcResults);
879
// If the matched pattern covers nodes which define a flag result, emit a node
880
// that tells the matcher about them so that it can update their results.
881
if (!MatchedFlagResultNodes.empty())
882
AddMatcher(new MarkFlagResultsMatcher(MatchedFlagResultNodes.data(),
883
MatchedFlagResultNodes.size()));
885
AddMatcher(new CompleteMatchMatcher(Ops.data(), Ops.size(), Pattern));
889
/// ConvertPatternToMatcher - Create the matcher for the specified pattern with
890
/// the specified variant. If the variant number is invalid, this returns null.
891
Matcher *llvm::ConvertPatternToMatcher(const PatternToMatch &Pattern,
893
const CodeGenDAGPatterns &CGP) {
894
MatcherGen Gen(Pattern, CGP);
896
// Generate the code for the matcher.
897
if (Gen.EmitMatcherCode(Variant))
900
// FIXME2: Kill extra MoveParent commands at the end of the matcher sequence.
901
// FIXME2: Split result code out to another table, and make the matcher end
902
// with an "Emit <index>" command. This allows result generation stuff to be
903
// shared and factored?
905
// If the match succeeds, then we generate Pattern.
906
Gen.EmitResultCode();
908
// Unconditional match.
909
return Gen.GetMatcher();
added
removed
libclamav/c++/llvm/utils/TableGen/DAGISelMatcherGen.cpp
