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* Copyright (c) 2005 Jakub Jermar
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* - Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* - Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* - The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#ifndef KERN_amd64_ASM_H_
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#define KERN_amd64_ASM_H_
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#include <arch/types.h>
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extern void asm_delay_loop(uint32_t t);
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extern void asm_fake_loop(uint32_t t);
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/** Return base address of current stack.
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* Return the base address of the current stack.
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* The stack is assumed to be STACK_SIZE bytes long.
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* The stack must start on page boundary.
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static inline uintptr_t get_stack_base(void)
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: "0" (~((uint64_t) STACK_SIZE-1))
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static inline void cpu_sleep(void)
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asm volatile ("hlt\n");
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static inline void cpu_halt(void)
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* @param port Port to read from
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static inline uint8_t pio_read_8(ioport8_t *port)
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"inb %w[port], %b[val]\n"
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* @param port Port to read from
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static inline uint16_t pio_read_16(ioport16_t *port)
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"inw %w[port], %w[val]\n"
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/** Double word from port
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* Get double word from port
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* @param port Port to read from
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static inline uint32_t pio_read_32(ioport32_t *port)
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"inl %w[port], %[val]\n"
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* Output byte to port
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* @param port Port to write to
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* @param val Value to write
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static inline void pio_write_8(ioport8_t *port, uint8_t val)
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"outb %b[val], %w[port]\n"
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:: [val] "a" (val), [port] "d" (port)
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* Output word to port
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* @param port Port to write to
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* @param val Value to write
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static inline void pio_write_16(ioport16_t *port, uint16_t val)
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"outw %w[val], %w[port]\n"
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:: [val] "a" (val), [port] "d" (port)
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/** Double word to port
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* Output double word to port
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* @param port Port to write to
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* @param val Value to write
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static inline void pio_write_32(ioport32_t *port, uint32_t val)
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"outl %[val], %w[port]\n"
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:: [val] "a" (val), [port] "d" (port)
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/** Swap Hidden part of GS register with visible one */
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static inline void swapgs(void)
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asm volatile("swapgs");
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/** Enable interrupts.
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* Enable interrupts and return previous
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* @return Old interrupt priority level.
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static inline ipl_t interrupts_enable(void) {
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/** Disable interrupts.
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* Disable interrupts and return previous
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* @return Old interrupt priority level.
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static inline ipl_t interrupts_disable(void) {
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/** Restore interrupt priority level.
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* @param ipl Saved interrupt priority level.
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static inline void interrupts_restore(ipl_t ipl) {
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/** Return interrupt priority level.
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* @return Current interrupt priority level.
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static inline ipl_t interrupts_read(void) {
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static inline void write_msr(uint32_t msr, uint64_t value)
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"a" ((uint32_t) (value)),
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"d" ((uint32_t) (value >> 32))
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static inline unative_t read_msr(uint32_t msr)
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: "=a" (ax), "=d" (dx)
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return ((uint64_t) dx << 32) | ax;
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/** Enable local APIC
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* Enable local APIC in MSR.
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static inline void enable_l_apic_in_msr()
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"movl $0x1b, %%ecx\n"
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"orl $(1 << 11),%%eax\n"
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"orl $(0xfee00000),%%eax\n"
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::: "%eax","%ecx","%edx"
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static inline uintptr_t * get_ip()
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/** Invalidate TLB Entry.
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* @param addr Address on a page whose TLB entry is to be invalidated.
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static inline void invlpg(uintptr_t addr)
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:: [addr] "m" (*((unative_t *) addr))
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/** Load GDTR register from memory.
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* @param gdtr_reg Address of memory from where to load GDTR.
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static inline void gdtr_load(ptr_16_64_t *gdtr_reg)
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"lgdtq %[gdtr_reg]\n"
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:: [gdtr_reg] "m" (*gdtr_reg)
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/** Store GDTR register to memory.
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* @param gdtr_reg Address of memory to where to load GDTR.
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static inline void gdtr_store(ptr_16_64_t *gdtr_reg)
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"sgdtq %[gdtr_reg]\n"
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:: [gdtr_reg] "m" (*gdtr_reg)
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/** Load IDTR register from memory.
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* @param idtr_reg Address of memory from where to load IDTR.
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static inline void idtr_load(ptr_16_64_t *idtr_reg)
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"lidtq %[idtr_reg]\n"
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:: [idtr_reg] "m" (*idtr_reg));
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/** Load TR from descriptor table.
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* @param sel Selector specifying descriptor of TSS segment.
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static inline void tr_load(uint16_t sel)
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#define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \
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"movq %%" #reg ", %[res]" \
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#define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \
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"movq %[regn], %%" #reg \
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:: [regn] "r" (regn) \
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extern size_t interrupt_handler_size;
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extern void interrupt_handlers(void);