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* Copyright (c) 2001-2004 Jakub Jermar
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* - Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* - Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* - The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#include <arch/types.h>
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#include <arch/smp/apic.h>
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#include <arch/smp/ap.h>
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#include <arch/smp/mps.h>
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#include <arch/boot/boot.h>
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#include <time/delay.h>
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#include <interrupt.h>
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#include <arch/interrupt.h>
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#include <ddi/device.h>
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* Advanced Programmable Interrupt Controller for SMP systems.
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* Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs
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* Simics 2.0.28 - Simics 2.2.19 2-15 CPUs
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* VMware Workstation 5.5 with 2 CPUs
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* QEMU 0.8.0 with 2-15 CPUs
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* ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
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* ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs
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* MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs
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* These variables either stay configured as initilalized, or are changed by
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* the MP configuration code.
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* Pay special attention to the volatile keyword. Without it, gcc -O2 would
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* optimize the code too much and accesses to l_apic and io_apic, that must
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* always be 32-bit, would use byte oriented instructions.
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volatile uint32_t *l_apic = (uint32_t *) 0xfee00000;
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volatile uint32_t *io_apic = (uint32_t *) 0xfec00000;
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uint32_t apic_id_mask = 0;
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static irq_t l_apic_timer_irq;
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static int apic_poll_errors(void);
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static char *delmod_str[] = {
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static char *destmod_str[] = {
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static char *trigmod_str[] = {
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static char *mask_str[] = {
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static char *delivs_str[] = {
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static char *tm_mode_str[] = {
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static char *intpol_str[] = {
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#endif /* LAPIC_VERBOSE */
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/** APIC spurious interrupt handler.
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* @param n Interrupt vector.
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* @param istate Interrupted state.
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static void apic_spurious(int n __attribute__((unused)), istate_t *istate __attribute__((unused)))
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printf("cpu%u: APIC spurious interrupt\n", CPU->id);
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static irq_ownership_t l_apic_timer_claim(irq_t *irq)
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static void l_apic_timer_irq_handler(irq_t *irq)
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* Holding a spinlock could prevent clock() from preempting
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* the current thread. In this case, we don't need to hold the
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* irq->lock so we just unlock it and then lock it again.
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spinlock_unlock(&irq->lock);
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spinlock_lock(&irq->lock);
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/** Initialize APIC on BSP. */
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exc_register(VECTOR_APIC_SPUR, "apic_spurious", (iroutine) apic_spurious);
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enable_irqs_function = io_apic_enable_irqs;
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disable_irqs_function = io_apic_disable_irqs;
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eoi_function = l_apic_eoi;
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* Configure interrupt routing.
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* IRQ 0 remains masked as the time signal is generated by l_apic's themselves.
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* Other interrupts will be forwarded to the lowest priority CPU.
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io_apic_disable_irqs(0xffff);
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irq_initialize(&l_apic_timer_irq);
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l_apic_timer_irq.preack = true;
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l_apic_timer_irq.devno = device_assign_devno();
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l_apic_timer_irq.inr = IRQ_CLK;
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l_apic_timer_irq.claim = l_apic_timer_claim;
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l_apic_timer_irq.handler = l_apic_timer_irq_handler;
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irq_register(&l_apic_timer_irq);
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for (i = 0; i < IRQ_COUNT; i++) {
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if ((pin = smp_irq_to_pin(i)) != -1)
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io_apic_change_ioredtbl((uint8_t) pin, DEST_ALL, (uint8_t) (IVT_IRQBASE + i), LOPRI);
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* Ensure that io_apic has unique ID.
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idreg.value = io_apic_read(IOAPICID);
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if ((1 << idreg.apic_id) & apic_id_mask) { /* see if IO APIC ID is used already */
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for (i = 0; i < APIC_ID_COUNT; i++) {
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if (!((1 << i) & apic_id_mask)) {
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io_apic_write(IOAPICID, idreg.value);
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* Configure the BSP's lapic.
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/** Poll for APIC errors.
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* Examine Error Status Register and report all errors found.
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* @return 0 on error, 1 on success.
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int apic_poll_errors(void)
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esr.value = l_apic[ESR];
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if (esr.send_checksum_error)
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printf("Send Checksum Error\n");
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if (esr.receive_checksum_error)
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printf("Receive Checksum Error\n");
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if (esr.send_accept_error)
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printf("Send Accept Error\n");
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if (esr.receive_accept_error)
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printf("Receive Accept Error\n");
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if (esr.send_illegal_vector)
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printf("Send Illegal Vector\n");
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if (esr.received_illegal_vector)
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printf("Received Illegal Vector\n");
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if (esr.illegal_register_address)
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printf("Illegal Register Address\n");
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return !esr.err_bitmap;
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/** Send all CPUs excluding CPU IPI vector.
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* @param vector Interrupt vector to be sent.
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* @return 0 on failure, 1 on success.
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int l_apic_broadcast_custom_ipi(uint8_t vector)
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icr.lo = l_apic[ICRlo];
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icr.delmod = DELMOD_FIXED;
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icr.destmod = DESTMOD_LOGIC;
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icr.level = LEVEL_ASSERT;
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icr.shorthand = SHORTHAND_ALL_EXCL;
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icr.trigger_mode = TRIGMOD_LEVEL;
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l_apic[ICRlo] = icr.lo;
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icr.lo = l_apic[ICRlo];
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if (icr.delivs == DELIVS_PENDING) {
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printf("IPI is pending.\n");
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return apic_poll_errors();
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/** Universal Start-up Algorithm for bringing up the AP processors.
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* @param apicid APIC ID of the processor to be brought up.
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* @return 0 on failure, 1 on success.
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int l_apic_send_init_ipi(uint8_t apicid)
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* Read the ICR register in and zero all non-reserved fields.
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icr.lo = l_apic[ICRlo];
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icr.hi = l_apic[ICRhi];
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icr.delmod = DELMOD_INIT;
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icr.destmod = DESTMOD_PHYS;
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icr.level = LEVEL_ASSERT;
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icr.trigger_mode = TRIGMOD_LEVEL;
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icr.shorthand = SHORTHAND_NONE;
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l_apic[ICRhi] = icr.hi;
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l_apic[ICRlo] = icr.lo;
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* According to MP Specification, 20us should be enough to
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if (!apic_poll_errors())
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icr.lo = l_apic[ICRlo];
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if (icr.delivs == DELIVS_PENDING) {
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printf("IPI is pending.\n");
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icr.delmod = DELMOD_INIT;
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icr.destmod = DESTMOD_PHYS;
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icr.level = LEVEL_DEASSERT;
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icr.shorthand = SHORTHAND_NONE;
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icr.trigger_mode = TRIGMOD_LEVEL;
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l_apic[ICRlo] = icr.lo;
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* Wait 10ms as MP Specification specifies.
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if (!is_82489DX_apic(l_apic[LAVR])) {
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* If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
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for (i = 0; i<2; i++) {
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icr.lo = l_apic[ICRlo];
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icr.vector = (uint8_t) (((uintptr_t) ap_boot) >> 12); /* calculate the reset vector */
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icr.delmod = DELMOD_STARTUP;
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icr.destmod = DESTMOD_PHYS;
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icr.level = LEVEL_ASSERT;
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icr.shorthand = SHORTHAND_NONE;
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icr.trigger_mode = TRIGMOD_LEVEL;
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l_apic[ICRlo] = icr.lo;
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return apic_poll_errors();
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/** Initialize Local APIC. */
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void l_apic_init(void)
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/* Initialize LVT Error register. */
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error.value = l_apic[LVT_Err];
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l_apic[LVT_Err] = error.value;
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/* Initialize LVT LINT0 register. */
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lint.value = l_apic[LVT_LINT0];
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l_apic[LVT_LINT0] = lint.value;
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/* Initialize LVT LINT1 register. */
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lint.value = l_apic[LVT_LINT1];
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l_apic[LVT_LINT1] = lint.value;
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/* Task Priority Register initialization. */
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tpr.value = l_apic[TPR];
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l_apic[TPR] = tpr.value;
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/* Spurious-Interrupt Vector Register initialization. */
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svr.value = l_apic[SVR];
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svr.vector = VECTOR_APIC_SPUR;
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svr.lapic_enabled = true;
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svr.focus_checking = true;
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l_apic[SVR] = svr.value;
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if (CPU->arch.family >= 6)
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enable_l_apic_in_msr();
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/* Interrupt Command Register initialization. */
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icr.lo = l_apic[ICRlo];
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icr.delmod = DELMOD_INIT;
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icr.destmod = DESTMOD_PHYS;
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icr.level = LEVEL_DEASSERT;
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icr.shorthand = SHORTHAND_ALL_INCL;
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icr.trigger_mode = TRIGMOD_LEVEL;
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l_apic[ICRlo] = icr.lo;
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/* Timer Divide Configuration Register initialization. */
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tdcr.value = l_apic[TDCR];
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tdcr.div_value = DIVIDE_1;
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l_apic[TDCR] = tdcr.value;
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/* Program local timer. */
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tm.value = l_apic[LVT_Tm];
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tm.vector = VECTOR_CLK;
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tm.mode = TIMER_PERIODIC;
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l_apic[LVT_Tm] = tm.value;
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* Measure and configure the timer to generate timer
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* interrupt with period 1s/HZ seconds.
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l_apic[ICRT] = 0xffffffff;
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while (l_apic[CCRT] == t1)
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l_apic[ICRT] = t1-t2;
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/* Program Logical Destination Register. */
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ldr.value = l_apic[LDR];
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ldr.id = (uint8_t) (1 << CPU->id);
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l_apic[LDR] = ldr.value;
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/* Program Destination Format Register for Flat mode. */
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dfr.value = l_apic[DFR];
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dfr.model = MODEL_FLAT;
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l_apic[DFR] = dfr.value;
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/** Local APIC End of Interrupt. */
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void l_apic_eoi(void)
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/** Dump content of Local APIC registers. */
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void l_apic_debug(void)
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printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());
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tm.value = l_apic[LVT_Tm];
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printf("LVT Tm: vector=%hhd, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]);
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lint.value = l_apic[LVT_LINT0];
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printf("LVT LINT0: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);
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lint.value = l_apic[LVT_LINT1];
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printf("LVT LINT1: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);
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error.value = l_apic[LVT_Err];
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printf("LVT Err: vector=%hhd, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]);
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/** Get Local APIC ID.
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* @return Local APIC ID.
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uint8_t l_apic_id(void)
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idreg.value = l_apic[L_APIC_ID];
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return idreg.apic_id;
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/** Read from IO APIC register.
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* @param address IO APIC register address.
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* @return Content of the addressed IO APIC register.
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uint32_t io_apic_read(uint8_t address)
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regsel.value = io_apic[IOREGSEL];
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regsel.reg_addr = address;
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io_apic[IOREGSEL] = regsel.value;
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return io_apic[IOWIN];
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/** Write to IO APIC register.
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* @param address IO APIC register address.
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* @param x Content to be written to the addressed IO APIC register.
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void io_apic_write(uint8_t address, uint32_t x)
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regsel.value = io_apic[IOREGSEL];
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regsel.reg_addr = address;
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io_apic[IOREGSEL] = regsel.value;
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/** Change some attributes of one item in I/O Redirection Table.
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* @param pin IO APIC pin number.
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* @param dest Interrupt destination address.
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* @param v Interrupt vector to trigger.
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* @param flags Flags.
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void io_apic_change_ioredtbl(uint8_t pin, uint8_t dest, uint8_t v, int flags)
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io_redirection_reg_t reg;
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int dlvr = DELMOD_FIXED;
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dlvr = DELMOD_LOWPRI;
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reg.lo = io_apic_read((uint8_t) (IOREDTBL + pin * 2));
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reg.hi = io_apic_read((uint8_t) (IOREDTBL + pin * 2 + 1));
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reg.destmod = DESTMOD_LOGIC;
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reg.trigger_mode = TRIGMOD_EDGE;
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reg.intpol = POLARITY_HIGH;
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io_apic_write((uint8_t) (IOREDTBL + pin * 2), reg.lo);
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io_apic_write((uint8_t) (IOREDTBL + pin * 2 + 1), reg.hi);
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/** Mask IRQs in IO APIC.
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* @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask).
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void io_apic_disable_irqs(uint16_t irqmask)
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io_redirection_reg_t reg;
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for (i = 0; i < 16; i++) {
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if (irqmask & (1 << i)) {
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* Mask the signal input in IO APIC if there is a
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* mapping for the respective IRQ number.
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pin = smp_irq_to_pin(i);
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reg.lo = io_apic_read((uint8_t) (IOREDTBL + pin * 2));
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io_apic_write((uint8_t) (IOREDTBL + pin * 2), reg.lo);
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/** Unmask IRQs in IO APIC.
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* @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask).
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void io_apic_enable_irqs(uint16_t irqmask)
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io_redirection_reg_t reg;
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for (i = 0; i < 16; i++) {
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if (irqmask & (1 << i)) {
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* Unmask the signal input in IO APIC if there is a
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* mapping for the respective IRQ number.
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pin = smp_irq_to_pin(i);
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reg.lo = io_apic_read((uint8_t) (IOREDTBL + pin * 2));
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io_apic_write((uint8_t) (IOREDTBL + pin * 2), reg.lo);
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#endif /* CONFIG_SMP */