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* Copyright (c) 2005 Jakub Jermar
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* - Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* - Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* - The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#ifndef KERN_ia64_ASM_H_
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#define KERN_ia64_ASM_H_
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#include <arch/types.h>
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#include <arch/register.h>
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#define IA64_IOSPACE_ADDRESS 0xE001000000000000ULL
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static inline void pio_write_8(ioport8_t *port, uint8_t v)
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uintptr_t prt = (uintptr_t) port;
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*((ioport8_t *)(IA64_IOSPACE_ADDRESS +
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((prt & 0xfff) | ((prt >> 2) << 12)))) = v;
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asm volatile ("mf\n" ::: "memory");
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static inline void pio_write_16(ioport16_t *port, uint16_t v)
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uintptr_t prt = (uintptr_t) port;
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*((ioport16_t *)(IA64_IOSPACE_ADDRESS +
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((prt & 0xfff) | ((prt >> 2) << 12)))) = v;
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asm volatile ("mf\n" ::: "memory");
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static inline void pio_write_32(ioport32_t *port, uint32_t v)
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uintptr_t prt = (uintptr_t) port;
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*((ioport32_t *)(IA64_IOSPACE_ADDRESS +
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((prt & 0xfff) | ((prt >> 2) << 12)))) = v;
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asm volatile ("mf\n" ::: "memory");
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static inline uint8_t pio_read_8(ioport8_t *port)
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uintptr_t prt = (uintptr_t) port;
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asm volatile ("mf\n" ::: "memory");
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return *((ioport8_t *)(IA64_IOSPACE_ADDRESS +
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((prt & 0xfff) | ((prt >> 2) << 12))));
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static inline uint16_t pio_read_16(ioport16_t *port)
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uintptr_t prt = (uintptr_t) port;
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asm volatile ("mf\n" ::: "memory");
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return *((ioport16_t *)(IA64_IOSPACE_ADDRESS +
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((prt & 0xfff) | ((prt >> 2) << 12))));
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static inline uint32_t pio_read_32(ioport32_t *port)
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uintptr_t prt = (uintptr_t) port;
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asm volatile ("mf\n" ::: "memory");
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return *((ioport32_t *)(IA64_IOSPACE_ADDRESS +
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((prt & 0xfff) | ((prt >> 2) << 12))));
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/** Return base address of current stack
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* Return the base address of the current stack.
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* The stack is assumed to be STACK_SIZE long.
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* The stack must start on page boundary.
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static inline uintptr_t get_stack_base(void)
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//I'm not sure why but this code bad inlines in scheduler,
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//so THE shifts about 16B and causes kernel panic
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//asm volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1)));
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//this code have the same meaning but inlines well
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asm volatile ("mov %0 = r12" : "=r" (v) );
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return v & (~(STACK_SIZE-1));
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/** Return Processor State Register.
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static inline uint64_t psr_read(void)
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asm volatile ("mov %0 = psr\n" : "=r" (v));
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/** Read IVA (Interruption Vector Address).
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* @return Return location of interruption vector table.
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static inline uint64_t iva_read(void)
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asm volatile ("mov %0 = cr.iva\n" : "=r" (v));
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/** Write IVA (Interruption Vector Address) register.
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* @param v New location of interruption vector table.
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static inline void iva_write(uint64_t v)
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asm volatile ("mov cr.iva = %0\n" : : "r" (v));
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/** Read IVR (External Interrupt Vector Register).
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* @return Highest priority, pending, unmasked external interrupt vector.
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static inline uint64_t ivr_read(void)
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asm volatile ("mov %0 = cr.ivr\n" : "=r" (v));
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static inline uint64_t cr64_read(void)
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asm volatile ("mov %0 = cr64\n" : "=r" (v));
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/** Write ITC (Interval Timer Counter) register.
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* @param v New counter value.
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static inline void itc_write(uint64_t v)
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asm volatile ("mov ar.itc = %0\n" : : "r" (v));
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/** Read ITC (Interval Timer Counter) register.
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* @return Current counter value.
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static inline uint64_t itc_read(void)
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asm volatile ("mov %0 = ar.itc\n" : "=r" (v));
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/** Write ITM (Interval Timer Match) register.
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* @param v New match value.
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static inline void itm_write(uint64_t v)
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asm volatile ("mov cr.itm = %0\n" : : "r" (v));
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/** Read ITM (Interval Timer Match) register.
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* @return Match value.
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static inline uint64_t itm_read(void)
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asm volatile ("mov %0 = cr.itm\n" : "=r" (v));
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/** Read ITV (Interval Timer Vector) register.
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* @return Current vector and mask bit.
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static inline uint64_t itv_read(void)
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asm volatile ("mov %0 = cr.itv\n" : "=r" (v));
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/** Write ITV (Interval Timer Vector) register.
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* @param v New vector and mask bit.
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static inline void itv_write(uint64_t v)
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asm volatile ("mov cr.itv = %0\n" : : "r" (v));
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/** Write EOI (End Of Interrupt) register.
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* @param v This value is ignored.
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static inline void eoi_write(uint64_t v)
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asm volatile ("mov cr.eoi = %0\n" : : "r" (v));
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/** Read TPR (Task Priority Register).
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* @return Current value of TPR.
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static inline uint64_t tpr_read(void)
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asm volatile ("mov %0 = cr.tpr\n" : "=r" (v));
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/** Write TPR (Task Priority Register).
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* @param v New value of TPR.
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static inline void tpr_write(uint64_t v)
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asm volatile ("mov cr.tpr = %0\n" : : "r" (v));
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/** Disable interrupts.
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* Disable interrupts and return previous
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* @return Old interrupt priority level.
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static ipl_t interrupts_disable(void)
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/** Enable interrupts.
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* Enable interrupts and return previous
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* @return Old interrupt priority level.
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static ipl_t interrupts_enable(void)
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/** Restore interrupt priority level.
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* @param ipl Saved interrupt priority level.
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static inline void interrupts_restore(ipl_t ipl)
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if (ipl & PSR_I_MASK)
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(void) interrupts_enable();
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(void) interrupts_disable();
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/** Return interrupt priority level.
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static inline ipl_t interrupts_read(void)
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return (ipl_t) psr_read();
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/** Disable protection key checking. */
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static inline void pk_disable(void)
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asm volatile ("rsm %0\n" : : "i" (PSR_PK_MASK));
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extern void cpu_halt(void);
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extern void cpu_sleep(void);
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extern void asm_delay_loop(uint32_t t);
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extern void switch_to_userspace(uintptr_t, uintptr_t, uintptr_t, uintptr_t,