2
#include "MipsOpcodes.h"
4
/* Placeholders for encoding
7
B cop2 branch condition
11
d destination register
22
u Shifted 16 bit immediate (upper)
23
n negative 16 bit immediate (for subi/u aliases)
24
j 5 bit secondary immediate
27
b cop2 branch condition
28
vs PSP vfpu source reg
30
vt PSP vfpu target reg
31
vc PSP vfpu control reg
32
Vs PS2 vector source reg
33
Vd PS2 vector dest reg
34
Vt PS2 vector target reg
35
C PSP vector condition
36
W weird vfpu parameters
44
const tMipsOpcode MipsOpcodes[] = {
45
// 31---------26---------------------------------------------------0
47
// ------6----------------------------------------------------------
48
// |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
49
// 000 | *1 | *2 | J | JAL | BEQ | BNE | BLEZ | BGTZ | 00..07
50
// 001 | ADDI | ADDIU | SLTI | SLTIU | ANDI | ORI | XORI | LUI | 08..0F
51
// 010 | *3 | *4 | --- | --- | BEQL | BNEL | BLEZL | BGTZL | 10..17
52
// 011 | DADDI | DADDIU| LDL | LDR | --- | --- | LQ | SQ | 18..1F
53
// 100 | LB | LH | LWL | LW | LBU | LHU | LWR | LWU | 20..27
54
// 101 | SB | SH | SWL | SW | SDL | SDR | SWR | CACHE | 28..2F
55
// 110 | LL | LWC1 | LV.S | --- | LLD | ULV.Q | LV.Q | LD | 30..37
56
// 111 | SC | SWC1 | SV.S | --- | SCD | USV.Q | SV.Q | SD | 38..3F
57
// hi |-------|-------|-------|-------|-------|-------|-------|-------|
58
// *1 = SPECIAL *2 = REGIMM *3 = COP0 *4 = COP1
59
{ "j", "i26", MIPS_OP(0x02), MA_MIPS1, MO_IPCA|MO_DELAY|MO_NODELAYSLOT },
60
{ "jal", "i26", MIPS_OP(0x03), MA_MIPS1, MO_IPCA|MO_DELAY|MO_NODELAYSLOT },
61
{ "beq", "s,t,i16", MIPS_OP(0x04), MA_MIPS1, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
62
{ "beqz", "s,i16", MIPS_OP(0x04), MA_MIPS1, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
63
{ "b", "i16", MIPS_OP(0x04), MA_MIPS1, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
64
{ "bne", "s,t,i16", MIPS_OP(0x05), MA_MIPS1, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
65
{ "bnez", "s,i16", MIPS_OP(0x05), MA_MIPS1, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
66
{ "blez", "s,i16", MIPS_OP(0x06), MA_MIPS1, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
67
{ "bgtz", "s,i16", MIPS_OP(0x07), MA_MIPS1, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
68
{ "addi", "t,s,i16", MIPS_OP(0x08), MA_MIPS1, MO_IGNORERTD },
69
{ "addi", "s,i16", MIPS_OP(0x08), MA_MIPS1, MO_RST },
70
{ "addiu", "t,s,i16", MIPS_OP(0x09), MA_MIPS1, MO_IGNORERTD },
71
{ "addiu", "s,i16", MIPS_OP(0x09), MA_MIPS1, MO_RST },
72
{ "slti", "t,s,i16", MIPS_OP(0x0A), MA_MIPS1, MO_IGNORERTD },
73
{ "slti", "s,i16", MIPS_OP(0x0A), MA_MIPS1, MO_RST },
74
{ "sltiu", "t,s,i16", MIPS_OP(0x0B), MA_MIPS1, MO_IGNORERTD },
75
{ "sltiu", "s,i16", MIPS_OP(0x0B), MA_MIPS1, MO_RST },
76
{ "andi", "t,s,i16", MIPS_OP(0x0C), MA_MIPS1, MO_IGNORERTD },
77
{ "andi", "s,i16", MIPS_OP(0x0C), MA_MIPS1, MO_RST },
78
{ "ori", "t,s,i16", MIPS_OP(0x0D), MA_MIPS1, MO_IGNORERTD },
79
{ "ori", "s,i16", MIPS_OP(0x0D), MA_MIPS1, MO_RST },
80
{ "xori", "t,s,i16", MIPS_OP(0x0E), MA_MIPS1, MO_IGNORERTD },
81
{ "xori", "s,i16", MIPS_OP(0x0E), MA_MIPS1, MO_RST },
82
{ "lui", "t,i16", MIPS_OP(0x0F), MA_MIPS1, MO_IGNORERTD },
83
{ "beql", "s,t,i16", MIPS_OP(0x14), MA_MIPS2, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
84
{ "beqzl", "s,i16", MIPS_OP(0x14), MA_MIPS2, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
85
{ "bnel", "s,t,i16", MIPS_OP(0x15), MA_MIPS2, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
86
{ "bnezl", "s,i16", MIPS_OP(0x15), MA_MIPS2, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
87
{ "blezl", "s,i16", MIPS_OP(0x16), MA_MIPS2, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
88
{ "bgtzl", "s,i16", MIPS_OP(0x17), MA_MIPS2, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
89
{ "daddi", "t,s,i16", MIPS_OP(0x18), MA_MIPS3, MO_64BIT },
90
{ "daddi", "s,i16", MIPS_OP(0x18), MA_MIPS3, MO_64BIT|MO_RST },
91
{ "daddiu", "t,s,i16", MIPS_OP(0x19), MA_MIPS3, MO_64BIT },
92
{ "daddiu", "s,i16", MIPS_OP(0x19), MA_MIPS3, MO_64BIT|MO_RST },
93
{ "ldl", "t,i16(s)", MIPS_OP(0x1A), MA_MIPS3, MO_64BIT|MO_DELAYRT|MO_IGNORERTD },
94
{ "ldl", "t,(s)", MIPS_OP(0x1A), MA_MIPS3, MO_64BIT|MO_DELAYRT|MO_IGNORERTD },
95
{ "ldr", "t,i16(s)", MIPS_OP(0x1B), MA_MIPS3, MO_64BIT|MO_DELAYRT|MO_IGNORERTD },
96
{ "ldr", "t,(s)", MIPS_OP(0x1B), MA_MIPS3, MO_64BIT|MO_DELAYRT|MO_IGNORERTD },
97
{ "lq", "t,i16(s)", MIPS_OP(0x1E), MA_MIPS1, MO_DELAYRT|MO_IGNORERTD },
98
{ "sq", "t,i16(s)", MIPS_OP(0x1F), MA_MIPS1, MO_DELAYRT|MO_IGNORERTD },
99
{ "lb", "t,i16(s)", MIPS_OP(0x20), MA_MIPS1, MO_DELAYRT|MO_IGNORERTD },
100
{ "lb", "t,(s)", MIPS_OP(0x20), MA_MIPS1, MO_DELAYRT|MO_IGNORERTD },
101
{ "lh", "t,i16(s)", MIPS_OP(0x21), MA_MIPS1, MO_DELAYRT|MO_IGNORERTD },
102
{ "lh", "t,(s)", MIPS_OP(0x21), MA_MIPS1, MO_DELAYRT|MO_IGNORERTD },
103
{ "lwl", "t,i16(s)", MIPS_OP(0x22), MA_MIPS1, MO_DELAYRT|MO_IGNORERTD },
104
{ "lwl", "t,(s)", MIPS_OP(0x22), MA_MIPS1, MO_DELAYRT|MO_IGNORERTD },
105
{ "lw", "t,i16(s)", MIPS_OP(0x23), MA_MIPS1, MO_DELAYRT|MO_IGNORERTD },
106
{ "lw", "t,(s)", MIPS_OP(0x23), MA_MIPS1, MO_DELAYRT|MO_IGNORERTD },
107
{ "lbu", "t,i16(s)", MIPS_OP(0x24), MA_MIPS1, MO_DELAYRT|MO_IGNORERTD },
108
{ "lbu", "t,(s)", MIPS_OP(0x24), MA_MIPS1, MO_DELAYRT|MO_IGNORERTD },
109
{ "lhu", "t,i16(s)", MIPS_OP(0x25), MA_MIPS1, MO_DELAYRT|MO_IGNORERTD },
110
{ "lhu", "t,(s)", MIPS_OP(0x25), MA_MIPS1, MO_DELAYRT|MO_IGNORERTD },
111
{ "lwr", "t,i16(s)", MIPS_OP(0x26), MA_MIPS1, MO_DELAYRT|MO_IGNORERTD },
112
{ "lwr", "t,(s)", MIPS_OP(0x26), MA_MIPS1, MO_DELAYRT|MO_IGNORERTD },
113
{ "lwu", "t,i16(s)", MIPS_OP(0x27), MA_MIPS3, MO_64BIT|MO_DELAYRT },
114
{ "lwu", "t,(s)", MIPS_OP(0x27), MA_MIPS3, MO_64BIT|MO_DELAYRT },
115
{ "sb", "t,i16(s)", MIPS_OP(0x28), MA_MIPS1, 0 },
116
{ "sb", "t,(s)", MIPS_OP(0x28), MA_MIPS1, 0 },
117
{ "sh", "t,i16(s)", MIPS_OP(0x29), MA_MIPS1, 0 },
118
{ "sh", "t,(s)", MIPS_OP(0x29), MA_MIPS1, 0 },
119
{ "swl", "t,i16(s)", MIPS_OP(0x2A), MA_MIPS1, 0 },
120
{ "swl", "t,(s)", MIPS_OP(0x2A), MA_MIPS1, 0 },
121
{ "sw", "t,i16(s)", MIPS_OP(0x2B), MA_MIPS1, 0 },
122
{ "sw", "t,(s)", MIPS_OP(0x2B), MA_MIPS1, 0 },
123
{ "sdl", "t,i16(s)", MIPS_OP(0x2C), MA_MIPS3, MO_64BIT },
124
{ "sdl", "t,(s)", MIPS_OP(0x2C), MA_MIPS3, MO_64BIT },
125
{ "sdr", "t,i16(s)", MIPS_OP(0x2D), MA_MIPS3, MO_64BIT|MO_IGNORERTD },
126
{ "sdr", "t,(s)", MIPS_OP(0x2D), MA_MIPS3, MO_64BIT|MO_IGNORERTD },
127
{ "swr", "t,i16(s)", MIPS_OP(0x2E), MA_MIPS1, 0 },
128
{ "swr", "t,(s)", MIPS_OP(0x2E), MA_MIPS1, 0 },
129
{ "cache", "t,i16(s)", MIPS_OP(0x2F), MA_PS2, 0 },
130
{ "ll", "t,i16(s)", MIPS_OP(0x30), MA_MIPS2, MO_DELAYRT|MO_IGNORERTD },
131
{ "ll", "t,(s)", MIPS_OP(0x30), MA_MIPS2, MO_DELAYRT|MO_IGNORERTD },
132
{ "lwc1", "T,i16(s)", MIPS_OP(0x31), MA_MIPS1, 0 },
133
{ "lwc1", "T,(s)", MIPS_OP(0x31), MA_MIPS1, 0 },
134
{ "lv.s", "vt,i16(s)", MIPS_OP(0x32), MA_PSP, MO_VFPU_SINGLE|MO_VFPU_MIXED|MO_IMMALIGNED },
135
{ "lv.s", "vt,(s)", MIPS_OP(0x32), MA_PSP, MO_VFPU_SINGLE|MO_VFPU_MIXED },
136
{ "lld", "t,i16(s)", MIPS_OP(0x34), MA_MIPS3, MO_64BIT|MO_DELAYRT },
137
{ "lld", "t,(s)", MIPS_OP(0x34), MA_MIPS3, MO_64BIT|MO_DELAYRT },
138
{ "ulv.q", "vt,i16(s)", MIPS_OP(0x35), MA_PSP, MO_VFPU_QUAD|MO_VFPU_MIXED|MO_IMMALIGNED },
139
{ "ulv.q", "vt,(s)", MIPS_OP(0x35), MA_PSP, MO_VFPU_QUAD|MO_VFPU_MIXED },
140
{ "lvl.q", "vt,i16(s)", MIPS_OP(0x35), MA_PSP, MO_VFPU_QUAD|MO_VFPU_MIXED|MO_VFPU_6BIT|MO_IMMALIGNED },
141
{ "lvl.q", "vt,(s)", MIPS_OP(0x35), MA_PSP, MO_VFPU_QUAD|MO_VFPU_MIXED|MO_VFPU_6BIT },
142
{ "lvr.q", "vt,i16(s)", MIPS_OP(0x35)|0x02, MA_PSP, MO_VFPU_QUAD|MO_VFPU_MIXED|MO_VFPU_6BIT|MO_IMMALIGNED },
143
{ "lvr.q", "vt,(s)", MIPS_OP(0x35)|0x02, MA_PSP, MO_VFPU_QUAD|MO_VFPU_MIXED|MO_VFPU_6BIT },
144
{ "lv.q", "vt,i16(s)", MIPS_OP(0x36), MA_PSP, MO_VFPU_QUAD|MO_VFPU_MIXED|MO_VFPU_6BIT|MO_IMMALIGNED },
145
{ "lv.q", "vt,(s)", MIPS_OP(0x36), MA_PSP, MO_VFPU_QUAD|MO_VFPU_MIXED|MO_VFPU_6BIT },
146
{ "lqc2", "Vt,i16(s)", MIPS_OP(0x36), MA_PS2, MO_DELAYRT },
147
{ "ld", "t,i16(s)", MIPS_OP(0x37), MA_MIPS3, MO_64BIT|MO_DELAYRT },
148
{ "ld", "t,(s)", MIPS_OP(0x37), MA_MIPS3, MO_64BIT|MO_DELAYRT },
149
{ "sc", "t,i16(s)", MIPS_OP(0x38), MA_MIPS2, 0 },
150
{ "sc", "t,(s)", MIPS_OP(0x38), MA_MIPS2, 0 },
151
{ "swc1", "T,i16(s)", MIPS_OP(0x39), MA_MIPS1, 0 },
152
{ "swc1", "T,(s)", MIPS_OP(0x39), MA_MIPS1, 0 },
153
{ "sv.s", "vt,i16(s)", MIPS_OP(0x3A), MA_PSP, MO_VFPU_SINGLE|MO_VFPU_MIXED|MO_IMMALIGNED },
154
{ "sv.s", "vt,(s)", MIPS_OP(0x3A), MA_PSP, MO_VFPU_SINGLE|MO_VFPU_MIXED },
155
{ "scd", "t,i16(s)", MIPS_OP(0x3C), MA_MIPS3, MO_64BIT|MO_DELAYRT },
156
{ "scd", "t,(s)", MIPS_OP(0x3C), MA_MIPS3, MO_64BIT|MO_DELAYRT },
157
{ "usv.q", "vt,i16(s)", MIPS_OP(0x3D), MA_PSP, MO_VFPU_QUAD|MO_VFPU_MIXED|MO_IMMALIGNED },
158
{ "usv.q", "vt,(s)", MIPS_OP(0x3D), MA_PSP, MO_VFPU_QUAD|MO_VFPU_MIXED },
159
{ "svl.q", "vt,i16(s)", MIPS_OP(0x3D), MA_PSP, MO_VFPU_QUAD|MO_VFPU_MIXED|MO_VFPU_6BIT|MO_IMMALIGNED },
160
{ "svl.q", "vt,(s)", MIPS_OP(0x3D), MA_PSP, MO_VFPU_QUAD|MO_VFPU_MIXED|MO_VFPU_6BIT },
161
{ "svr.q", "vt,i16(s)", MIPS_OP(0x3D)|0x02, MA_PSP, MO_VFPU_QUAD|MO_VFPU_MIXED|MO_VFPU_6BIT|MO_IMMALIGNED },
162
{ "svr.q", "vt,(s)", MIPS_OP(0x3D)|0x02, MA_PSP, MO_VFPU_QUAD|MO_VFPU_MIXED|MO_VFPU_6BIT },
163
{ "sv.q", "vt,i16(s),w", MIPS_OP(0x3E)|0x02, MA_PSP, MO_VFPU_QUAD|MO_VFPU_MIXED|MO_VFPU_6BIT|MO_IMMALIGNED },
164
{ "sv.q", "vt,(s),w", MIPS_OP(0x3E)|0x02, MA_PSP, MO_VFPU_QUAD|MO_VFPU_MIXED|MO_VFPU_6BIT },
165
{ "sv.q", "vt,i16(s)", MIPS_OP(0x3E), MA_PSP, MO_VFPU_QUAD|MO_VFPU_MIXED|MO_VFPU_6BIT|MO_IMMALIGNED },
166
{ "sv.q", "vt,(s)", MIPS_OP(0x3E), MA_PSP, MO_VFPU_QUAD|MO_VFPU_MIXED|MO_VFPU_6BIT },
167
{ "sqc2", "Vt,i16(s)", MIPS_OP(0x3E), MA_PS2, MO_DELAYRT },
168
{ "sd", "t,i16(s)", MIPS_OP(0x3F), MA_MIPS3, MO_64BIT|MO_DELAYRT },
169
{ "sd", "t,(s)", MIPS_OP(0x3F), MA_MIPS3, MO_64BIT|MO_DELAYRT },
171
// 31---------26------------------------------------------5--------0
172
// |= SPECIAL| | function|
173
// ------6----------------------------------------------------6-----
174
// |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
175
// 000 | SLL | --- | SRL*1 | SRA | SLLV | --- | SRLV*2| SRAV | 00..07
176
// 001 | JR | JALR | MOVZ | MOVN |SYSCALL| BREAK | --- | SYNC | 08..0F
177
// 010 | MFHI | MTHI | MFLO | MTLO | DSLLV | --- | *3 | *4 | 10..17
178
// 011 | MULT | MULTU | DIV | DIVU | MADD | MADDU | ---- | ----- | 18..1F
179
// 100 | ADD | ADDU | SUB | SUBU | AND | OR | XOR | NOR | 20..27
180
// 101 | mfsa | mtsa | SLT | SLTU | *5 | *6 | *7 | *8 | 28..2F
181
// 110 | TGE | TGEU | TLT | TLTU | TEQ | --- | TNE | --- | 30..37
182
// 111 | dsll | --- | dsrl | dsra |dsll32 | --- |dsrl32 |dsra32 | 38..3F
183
// hi |-------|-------|-------|-------|-------|-------|-------|-------|
184
// *1: rotr when rs = 1 (PSP only) *2: rotrv when sa = 1 (PSP only)
185
// *3: dsrlv on PS2, clz on PSP *4: dsrav on PS2, clo on PSP
186
// *5: dadd on PS2, max on PSP *6: daddu on PS2, min on PSP
187
// *7: dsub on PS2, msub on PSP *8: dsubu on PS2, msubu on PSP
188
{ "sll", "d,t,i5", MIPS_SPECIAL(0x00), MA_MIPS1, 0 },
189
{ "sll", "d,i5", MIPS_SPECIAL(0x00), MA_MIPS1, MO_RDT },
190
{ "nop", "", MIPS_SPECIAL(0x00), MA_MIPS1, 0 },
191
{ "srl", "d,t,i5", MIPS_SPECIAL(0x02), MA_MIPS1, 0 },
192
{ "srl", "d,i5", MIPS_SPECIAL(0x02), MA_MIPS1, MO_RDT },
193
{ "rotr", "d,t,i5", MIPS_SPECIAL(0x02)|MIPS_RS(1), MA_PSP, 0 },
194
{ "rotr", "d,i5", MIPS_SPECIAL(0x02)|MIPS_RS(1), MA_PSP, MO_RDT },
195
{ "sra", "d,t,i5", MIPS_SPECIAL(0x03), MA_MIPS1, 0 },
196
{ "sra", "d,i5", MIPS_SPECIAL(0x03), MA_MIPS1, MO_RDT },
197
{ "sllv", "d,t,s", MIPS_SPECIAL(0x04), MA_MIPS1, 0 },
198
{ "sllv", "d,s", MIPS_SPECIAL(0x04), MA_MIPS1, MO_RDT },
199
{ "srlv", "d,t,s", MIPS_SPECIAL(0x06), MA_MIPS1, 0 },
200
{ "srlv", "d,s", MIPS_SPECIAL(0x06), MA_MIPS1, MO_RDT },
201
{ "rotrv", "d,t,s", MIPS_SPECIAL(0x06)|MIPS_SA(1), MA_PSP, 0 },
202
{ "rotrv", "d,s", MIPS_SPECIAL(0x06)|MIPS_SA(1), MA_PSP, MO_RDT },
203
{ "srav", "d,t,s", MIPS_SPECIAL(0x07), MA_MIPS1, 0 },
204
{ "srav", "d,s", MIPS_SPECIAL(0x07), MA_MIPS1, MO_RDT },
205
{ "jr", "s", MIPS_SPECIAL(0x08), MA_MIPS1, MO_DELAY|MO_NODELAYSLOT },
206
{ "jalr", "s,d", MIPS_SPECIAL(0x09), MA_MIPS1, MO_DELAY|MO_NODELAYSLOT },
207
{ "jalr", "s", MIPS_SPECIAL(0x09)|MIPS_RD(31), MA_MIPS1, MO_DELAY|MO_NODELAYSLOT },
208
{ "movz", "d,s,t", MIPS_SPECIAL(0x0A), MA_MIPS4|MA_PS2|MA_PSP, 0 },
209
{ "movn", "d,s,t", MIPS_SPECIAL(0x0B), MA_MIPS4|MA_PS2|MA_PSP, 0 },
210
{ "syscall","i20", MIPS_SPECIAL(0x0C), MA_MIPS1, MO_NODELAYSLOT },
211
{ "break", "i20", MIPS_SPECIAL(0x0D), MA_MIPS1, MO_NODELAYSLOT },
212
{ "sync", "", MIPS_SPECIAL(0x0F), MA_MIPS2, 0 },
213
{ "mfhi", "d", MIPS_SPECIAL(0x10), MA_MIPS1, 0 },
214
{ "mthi", "s", MIPS_SPECIAL(0x11), MA_MIPS1, 0 },
215
{ "mflo", "d", MIPS_SPECIAL(0x12), MA_MIPS1, 0 },
216
{ "mtlo", "s", MIPS_SPECIAL(0x13), MA_MIPS1, 0 },
217
{ "dsllv", "d,t,s", MIPS_SPECIAL(0x14), MA_MIPS3, MO_64BIT },
218
{ "dsllv", "d,s", MIPS_SPECIAL(0x14), MA_MIPS3, MO_64BIT },
219
{ "dsrlv", "d,t,s", MIPS_SPECIAL(0x16), MA_MIPS3, MO_64BIT },
220
{ "dsrlv", "d,s", MIPS_SPECIAL(0x16), MA_MIPS3, MO_64BIT|MO_RDT },
221
{ "clz", "d,s", MIPS_SPECIAL(0x16), MA_PSP, 0 },
222
{ "dsrav", "d,t,s", MIPS_SPECIAL(0x17), MA_MIPS3, MO_64BIT },
223
{ "dsrav", "d,s", MIPS_SPECIAL(0x17), MA_MIPS3, MO_64BIT|MO_RDT },
224
{ "clo", "d,s", MIPS_SPECIAL(0x17), MA_PSP, 0 },
225
{ "mult", "d,s,t", MIPS_SPECIAL(0x18), MA_PS2, 0 },
226
{ "multu", "d,s,t", MIPS_SPECIAL(0x19), MA_PS2, 0 },
227
{ "mult", "s,t", MIPS_SPECIAL(0x18), MA_MIPS1, 0 },
228
{ "mult", "r\x0,s,t", MIPS_SPECIAL(0x18), MA_MIPS1, 0 },
229
{ "multu", "s,t", MIPS_SPECIAL(0x19), MA_MIPS1, 0 },
230
{ "multu", "r\x0,s,t", MIPS_SPECIAL(0x19), MA_MIPS1, 0 },
231
{ "div", "s,t", MIPS_SPECIAL(0x1A), MA_MIPS1, 0 },
232
{ "div", "r\x0,s,t", MIPS_SPECIAL(0x1A), MA_MIPS1, 0 },
233
{ "divu", "s,t", MIPS_SPECIAL(0x1B), MA_MIPS1, 0 },
234
{ "divu", "r\x0,s,t", MIPS_SPECIAL(0x1B), MA_MIPS1, 0 },
235
{ "dmult", "s,t", MIPS_SPECIAL(0x1C), MA_MIPS3|MA_EXPS2, MO_64BIT },
236
{ "dmult", "r\x0,s,t", MIPS_SPECIAL(0x1C), MA_MIPS3|MA_EXPS2, MO_64BIT },
237
{ "madd", "s,t", MIPS_SPECIAL(0x1C), MA_PSP, 0 },
238
{ "dmultu", "s,t", MIPS_SPECIAL(0x1D), MA_MIPS3|MA_EXPS2, MO_64BIT },
239
{ "dmultu", "r\x0,s,t", MIPS_SPECIAL(0x1D), MA_MIPS3|MA_EXPS2, MO_64BIT },
240
{ "maddu", "s,t", MIPS_SPECIAL(0x1D), MA_PSP, 0 },
241
{ "ddiv", "s,t", MIPS_SPECIAL(0x1E), MA_MIPS3|MA_EXPS2, MO_64BIT },
242
{ "ddiv", "r\x0,s,t", MIPS_SPECIAL(0x1E), MA_MIPS3|MA_EXPS2, MO_64BIT },
243
{ "ddivu", "s,t", MIPS_SPECIAL(0x1F), MA_MIPS3|MA_EXPS2, MO_64BIT },
244
{ "ddivu", "r\x0,s,t", MIPS_SPECIAL(0x1F), MA_MIPS3|MA_EXPS2, MO_64BIT },
245
{ "add", "d,s,t", MIPS_SPECIAL(0x20), MA_MIPS1, 0 },
246
{ "add", "s,t", MIPS_SPECIAL(0x20), MA_MIPS1, MO_RSD },
247
{ "addu", "d,s,t", MIPS_SPECIAL(0x21), MA_MIPS1, 0 },
248
{ "addu", "s,t", MIPS_SPECIAL(0x21), MA_MIPS1, MO_RSD },
249
{ "move", "d,s", MIPS_SPECIAL(0x21), MA_MIPS1, 0 },
250
{ "sub", "d,s,t", MIPS_SPECIAL(0x22), MA_MIPS1, 0 },
251
{ "sub", "s,t", MIPS_SPECIAL(0x22), MA_MIPS1, MO_RSD },
252
{ "neg", "d,t", MIPS_SPECIAL(0x22), MA_MIPS1, 0 },
253
{ "subu", "d,s,t", MIPS_SPECIAL(0x23), MA_MIPS1, 0 },
254
{ "subu", "s,t", MIPS_SPECIAL(0x23), MA_MIPS1, MO_RSD },
255
{ "negu", "d,t", MIPS_SPECIAL(0x23), MA_MIPS1, 0 },
256
{ "and", "d,s,t", MIPS_SPECIAL(0x24), MA_MIPS1, 0 },
257
{ "and", "s,t", MIPS_SPECIAL(0x24), MA_MIPS1, MO_RSD },
258
{ "or", "d,s,t", MIPS_SPECIAL(0x25), MA_MIPS1, 0 },
259
{ "or", "s,t", MIPS_SPECIAL(0x25), MA_MIPS1, MO_RSD },
260
{ "xor", "d,s,t", MIPS_SPECIAL(0x26), MA_MIPS1, 0 },
261
{ "eor", "d,s,t", MIPS_SPECIAL(0x26), MA_MIPS1, 0 },
262
{ "xor", "s,t", MIPS_SPECIAL(0x26), MA_MIPS1, MO_RSD },
263
{ "eor", "s,t", MIPS_SPECIAL(0x26), MA_MIPS1, MO_RSD },
264
{ "nor", "d,s,t", MIPS_SPECIAL(0x27), MA_MIPS1, 0 },
265
{ "nor", "s,t", MIPS_SPECIAL(0x27), MA_MIPS1, MO_RSD },
266
{ "mfsa", "d", MIPS_SPECIAL(0x28), MA_PS2, 0 },
267
{ "mtsa", "s", MIPS_SPECIAL(0x29), MA_PS2, 0 },
268
{ "slt", "d,s,t", MIPS_SPECIAL(0x2A), MA_MIPS1, 0 },
269
{ "slt", "s,t", MIPS_SPECIAL(0x2A), MA_MIPS1, MO_RSD},
270
{ "sltu", "d,s,t", MIPS_SPECIAL(0x2B), MA_MIPS1, 0 },
271
{ "sltu", "s,t", MIPS_SPECIAL(0x2B), MA_MIPS1, MO_RSD },
272
{ "dadd", "d,s,t", MIPS_SPECIAL(0x2C), MA_MIPS3, MO_64BIT },
273
{ "max", "d,s,t", MIPS_SPECIAL(0x2C), MA_PSP, 0 },
274
{ "daddu", "d,s,t", MIPS_SPECIAL(0x2D), MA_MIPS3, MO_64BIT },
275
{ "dmove", "d,s", MIPS_SPECIAL(0x2D), MA_MIPS3, MO_64BIT },
276
{ "min", "d,s,t", MIPS_SPECIAL(0x2D), MA_PSP, 0 },
277
{ "dsub", "d,s,t", MIPS_SPECIAL(0x2E), MA_MIPS3, MO_64BIT },
278
{ "msub", "s,t", MIPS_SPECIAL(0x2E), MA_PSP, 0 },
279
{ "dsubu", "d,s,t", MIPS_SPECIAL(0x2F), MA_MIPS3, MO_64BIT },
280
{ "msubu", "s,t", MIPS_SPECIAL(0x2F), MA_PSP, 0 },
281
{ "tge", "s,t", MIPS_SPECIAL(0x30), MA_MIPS2, MO_RSD },
282
{ "tgeu", "s,t", MIPS_SPECIAL(0x31), MA_MIPS2, MO_RSD },
283
{ "tlt", "s,t", MIPS_SPECIAL(0x32), MA_MIPS2, MO_RSD },
284
{ "tltu", "s,t", MIPS_SPECIAL(0x33), MA_MIPS2, MO_RSD },
285
{ "teq", "s,t", MIPS_SPECIAL(0x34), MA_MIPS2, MO_RSD },
286
{ "tne", "s,t", MIPS_SPECIAL(0x36), MA_MIPS2, MO_RSD },
287
{ "dsll", "d,t,i5", MIPS_SPECIAL(0x38), MA_MIPS3, MO_64BIT },
288
{ "dsll", "d,i5", MIPS_SPECIAL(0x38), MA_MIPS3, MO_64BIT|MO_RDT },
289
{ "dsrl", "d,t,i5", MIPS_SPECIAL(0x3A), MA_MIPS3, MO_64BIT },
290
{ "dsrl", "d,i5", MIPS_SPECIAL(0x3A), MA_MIPS3, MO_64BIT|MO_RDT },
291
{ "dsra", "d,t,i5", MIPS_SPECIAL(0x3B), MA_MIPS3, MO_64BIT },
292
{ "dsra", "d,i5", MIPS_SPECIAL(0x3B), MA_MIPS3, MO_64BIT|MO_RDT },
293
{ "dsll32", "d,t,i5", MIPS_SPECIAL(0x3C), MA_MIPS3, MO_64BIT },
294
{ "dsll32", "d,i5", MIPS_SPECIAL(0x3C), MA_MIPS3, MO_64BIT|MO_RDT },
295
{ "dsrl32", "d,t,i5", MIPS_SPECIAL(0x3E), MA_MIPS3, MO_64BIT },
296
{ "dsrl32", "d,i5", MIPS_SPECIAL(0x3E), MA_MIPS3, MO_64BIT|MO_RDT },
297
{ "dsra32", "d,t,i5", MIPS_SPECIAL(0x3F), MA_MIPS3, MO_64BIT },
298
{ "dsra32", "d,i5", MIPS_SPECIAL(0x3F), MA_MIPS3, MO_64BIT|MO_RDT },
300
// REGIMM: encoded by the rt field when opcode field = REGIMM.
301
// 31---------26----------20-------16------------------------------0
302
// |= REGIMM| | rt | |
303
// ------6---------------------5------------------------------------
304
// |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
305
// 00 | BLTZ | BGEZ | BLTZL | BGEZL | --- | --- | --- | --- | 00-07
306
// 01 | tgei | tgeiu | tlti | tltiu | teqi | --- | tnei | --- | 08-0F
307
// 10 | BLTZAL| BGEZAL|BLTZALL|BGEZALL| --- | --- | --- | --- | 10-17
308
// 11 | mtsab | mtsah | --- | --- | --- | --- | --- | --- | 18-1F
309
// hi |-------|-------|-------|-------|-------|-------|-------|-------|
310
{ "bltz", "s,i16", MIPS_REGIMM(0x00), MA_MIPS1, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
311
{ "bgez", "s,i16", MIPS_REGIMM(0x01), MA_MIPS1, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
312
{ "bltzl", "s,i16", MIPS_REGIMM(0x02), MA_MIPS2, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
313
{ "bgezl", "s,i16", MIPS_REGIMM(0x03), MA_MIPS2, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
314
{ "tgei", "s,i16", MIPS_REGIMM(0x08), MA_MIPS2, 0 },
315
{ "tgeiu", "s,i16", MIPS_REGIMM(0x09), MA_MIPS2, 0 },
316
{ "tlti", "s,i16", MIPS_REGIMM(0x0A), MA_MIPS2, 0 },
317
{ "tltiu", "s,i16", MIPS_REGIMM(0x0B), MA_MIPS2, 0 },
318
{ "teqi", "s,i16", MIPS_REGIMM(0x0C), MA_MIPS2, 0 },
319
{ "tnei", "s,i16", MIPS_REGIMM(0x0E), MA_MIPS2, 0 },
320
{ "bltzal", "s,i16", MIPS_REGIMM(0x10), MA_MIPS1, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
321
{ "bgezal", "s,i16", MIPS_REGIMM(0x11), MA_MIPS1, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
322
{ "bltzall","s,i16", MIPS_REGIMM(0x12), MA_MIPS2, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
323
{ "bgezall","s,i16", MIPS_REGIMM(0x13), MA_MIPS2, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
324
{ "mtsab", "s,i16", MIPS_REGIMM(0x18), MA_PS2, 0 },
325
{ "mtsah", "s,i16", MIPS_REGIMM(0x19), MA_PS2, 0 },
327
// 31-------26------21---------------------------------------------0
329
// -----6-------5---------------------------------------------------
330
// |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
331
// 00 | MFC1 | --- | CFC1 | --- | MTC1 | --- | CTC1 | --- | 00..07
332
// 01 | BC* | --- | --- | --- | --- | --- | --- | --- | 08..0F
333
// 10 | S* | --- | --- | --- | W* | --- | --- | --- | 10..17
334
// 11 | --- | --- | --- | --- | --- | --- | --- | --- | 18..1F
335
// hi |-------|-------|-------|-------|-------|-------|-------|-------|
336
{ "mfc1", "t,S", MIPS_COP1(0x00), MA_MIPS2, 0 },
337
{ "cfc1", "t,S", MIPS_COP1(0x02), MA_MIPS2, 0 },
338
{ "mtc1", "t,S", MIPS_COP1(0x04), MA_MIPS2, 0 },
339
{ "ctc1", "t,S", MIPS_COP1(0x06), MA_MIPS2, 0 },
341
// 31---------21-------16------------------------------------------0
343
// ------11---------5-----------------------------------------------
344
// |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
345
// 00 | BC1F | BC1T | BC1FL | BC1TL | --- | --- | --- | --- | 00..07
346
// 01 | --- | --- | --- | --- | --- | --- | --- | --- | 08..0F
347
// 10 | --- | --- | --- | --- | --- | --- | --- | --- | 10..17
348
// 11 | --- | --- | --- | --- | --- | --- | --- | --- | 18..1F
349
// hi |-------|-------|-------|-------|-------|-------|-------|-------|
350
{ "bc1f", "i26", MIPS_COP1BC(0x00), MA_MIPS2, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
351
{ "bc1t", "i26", MIPS_COP1BC(0x01), MA_MIPS2, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
352
{ "bc1fl", "i26", MIPS_COP1BC(0x02), MA_MIPS2, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
353
{ "bc1tl", "i26", MIPS_COP1BC(0x03), MA_MIPS2, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
355
// 31---------21------------------------------------------5--------0
356
// |= COP1S | | function|
357
// -----11----------------------------------------------------6-----
358
// |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
359
// 000 | add | sub | mul | div | sqrt | abs | mov | neg | 00..07
360
// 001 | --- | --- | --- | --- |round.w|trunc.w|ceil.w |floor.w| 08..0F
361
// 010 | --- | --- | --- | --- | --- | --- | rsqrt | --- | 10..17
362
// 011 | adda | suba | mula | --- | madd | msub | madda | msuba | 18..1F
363
// 100 | --- | --- | --- | --- | cvt.w | --- | --- | --- | 20..27
364
// 101 | max | min | --- | --- | --- | --- | --- | --- | 28..2F
365
// 110 | c.f | c.un | c.eq | c.ueq |c.(o)lt| c.ult |c.(o)le| c.ule | 30..37
366
// 110 | c.sf | c.ngle| c.seq | c.ngl | c.lt | c.nge | c.le | c.ngt | 38..3F
367
// hi |-------|-------|-------|-------|-------|-------|-------|-------|
368
{ "add.s", "D,S,T", MIPS_COP1S(0x00), MA_MIPS2, 0 },
369
{ "add.s", "S,T", MIPS_COP1S(0x00), MA_MIPS2, MO_FRSD },
370
{ "sub.s", "D,S,T", MIPS_COP1S(0x01), MA_MIPS2, 0 },
371
{ "sub.s", "S,T", MIPS_COP1S(0x01), MA_MIPS2, MO_FRSD },
372
{ "mul.s", "D,S,T", MIPS_COP1S(0x02), MA_MIPS2, 0 },
373
{ "mul.s", "S,T", MIPS_COP1S(0x02), MA_MIPS2, MO_FRSD },
374
{ "div.s", "D,S,T", MIPS_COP1S(0x03), MA_MIPS2, 0 },
375
{ "div.s", "S,T", MIPS_COP1S(0x03), MA_MIPS2, MO_FRSD },
376
{ "sqrt.s", "D,S", MIPS_COP1S(0x04), MA_MIPS2, 0 },
377
{ "abs.s", "D,S", MIPS_COP1S(0x05), MA_MIPS2, 0 },
378
{ "mov.s", "D,S", MIPS_COP1S(0x06), MA_MIPS2, 0 },
379
{ "neg.s", "D,S", MIPS_COP1S(0x07), MA_MIPS2, 0 },
380
{ "round.w.s", "D,S", MIPS_COP1S(0x0C), MA_PSP, 0 },
381
{ "trunc.w.s", "D,S", MIPS_COP1S(0x0D), MA_PSP, 0 },
382
{ "ceil.w.s", "D,S", MIPS_COP1S(0x0E), MA_PSP, 0 },
383
{ "floor.w.s", "D,S", MIPS_COP1S(0x0F), MA_PSP, 0 },
384
{ "rsqrt.w.s", "D,S", MIPS_COP1S(0x16), MA_PS2, 0 },
385
{ "adda.s", "S,T", MIPS_COP1S(0x18), MA_PS2, 0 },
386
{ "suba.s", "S,T", MIPS_COP1S(0x19), MA_PS2, 0 },
387
{ "mula.s", "S,T", MIPS_COP1S(0x1A), MA_PS2, 0 },
388
{ "madd.s", "D,S,T", MIPS_COP1S(0x1C), MA_PS2, 0 },
389
{ "madd.s", "S,T", MIPS_COP1S(0x1C), MA_PS2, MO_FRSD },
390
{ "msub.s", "D,S,T", MIPS_COP1S(0x1D), MA_PS2, 0 },
391
{ "msub.s", "S,T", MIPS_COP1S(0x1D), MA_PS2, MO_FRSD },
392
{ "madda.s", "S,T", MIPS_COP1S(0x1E), MA_PS2, 0 },
393
{ "msuba.s", "S,T", MIPS_COP1S(0x1F), MA_PS2, 0 },
394
{ "cvt.w.s", "D,S", MIPS_COP1S(0x24), MA_MIPS2, 0 },
395
{ "max.s", "D,S,T", MIPS_COP1S(0x28), MA_PS2, 0 },
396
{ "min.s", "D,S,T", MIPS_COP1S(0x29), MA_PS2, 0 },
397
{ "c.f.s", "S,T", MIPS_COP1S(0x30), MA_MIPS2, 0 },
398
{ "c.un.s", "S,T", MIPS_COP1S(0x31), MA_PSP, 0 },
399
{ "c.eq.s", "S,T", MIPS_COP1S(0x32), MA_MIPS2, 0 },
400
{ "c.ueq.s", "S,T", MIPS_COP1S(0x33), MA_PSP, 0 },
401
{ "c.olt.s", "S,T", MIPS_COP1S(0x34), MA_PSP, 0 },
402
{ "c.lt.s", "S,T", MIPS_COP1S(0x34), MA_PS2, 0 },
403
{ "c.ult.s", "S,T", MIPS_COP1S(0x35), MA_PSP, 0 },
404
{ "c.ole.s", "S,T", MIPS_COP1S(0x36), MA_PSP, 0 },
405
{ "c.le.s", "S,T", MIPS_COP1S(0x36), MA_PS2, 0 },
406
{ "c.ule.s", "S,T", MIPS_COP1S(0x37), MA_PSP, 0 },
407
{ "c.sf.s", "S,T", MIPS_COP1S(0x38), MA_PSP, 0 },
408
{ "c.ngle.s", "S,T", MIPS_COP1S(0x39), MA_PSP, 0 },
409
{ "c.seq.s", "S,T", MIPS_COP1S(0x3A), MA_PSP, 0 },
410
{ "c.ngl.s", "S,T", MIPS_COP1S(0x3B), MA_PSP, 0 },
411
{ "c.lt.s", "S,T", MIPS_COP1S(0x3C), MA_PSP, 0 },
412
{ "c.nge.s", "S,T", MIPS_COP1S(0x3D), MA_PSP, 0 },
413
{ "c.le.s", "S,T", MIPS_COP1S(0x3E), MA_PSP, 0 },
414
{ "c.ngt.s", "S,T", MIPS_COP1S(0x3F), MA_PSP, 0 },
416
// COP1W: encoded by function field
417
// 31---------21------------------------------------------5--------0
418
// |= COP1W | | function|
419
// -----11----------------------------------------------------6-----
420
// |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
421
// 000 | --- | --- | --- | --- | --- | --- | --- | --- | 00..07
422
// 001 | --- | --- | --- | --- | --- | --- | --- | --- | 08..0F
423
// 010 | --- | --- | --- | --- | --- | --- | --- | --- | 10..17
424
// 011 | --- | --- | --- | --- | --- | --- | --- | --- | 18..1F
425
// 100 |cvt.s.w| --- | --- | --- | --- | --- | --- | --- | 20..27
426
// 101 | --- | --- | --- | --- | --- | --- | --- | --- | 28..2F
427
// 110 | --- | --- | --- | --- | --- | --- | --- | --- | 30..37
428
// 110 | --- | --- | --- | --- | --- | --- | --- | --- | 38..3F
429
// hi |-------|-------|-------|-------|-------|-------|-------|-------|
430
{ "cvt.s.w", "D,S", MIPS_COP1W(0x20), MA_MIPS2, 0 },
432
// 31-------26------21---------------------------------------------0
434
// -----6-------5---------------------------------------------------
435
// |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
436
// 00 | --- | --- | --- | MFV | --- | --- | --- | MTV |
437
// 01 | BC* | --- | --- | --- | --- | --- | --- | --- |
438
// 10 | --- | --- | --- | --- | --- | --- | --- | --- |
439
// 11 | --- | --- | --- | --- | --- | --- | --- | --- |
440
// hi |-------|-------|-------|-------|-------|-------|-------|-------|
441
// VVVVVV VVVVV ttttt -------- C DDDDDDD
442
{ "mfv", "t,vd", MIPS_COP2(3), MA_PSP, MO_VFPU|MO_VFPU_SINGLE },
443
{ "mfvc", "t,vc", MIPS_COP2(3) | 0x80, MA_PSP, MO_VFPU },
444
{ "mtv", "t,vd", MIPS_COP2(7), MA_PSP, MO_VFPU|MO_VFPU_SINGLE },
445
{ "mtvc", "t,vc", MIPS_COP2(7) | 0x80, MA_PSP, MO_VFPU },
447
// COP2BC: ? indicates any, * indicates all
448
// 31---------21-------16------------------------------------------0
450
// ------11---------5-----------------------------------------------
451
// |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
452
// 00 | BVFx | BVTx | BVFLx | BVTLx | BVFy | BVTy | BVFLy | BVTLy |
453
// 01 | BVFz | BVTz | BVFLz | BVTLz | BVFw | BVTw | BVFLw | BVTLw |
454
// 10 | BVF? | BVT? | BVFL? | BVTL? | BVF* | BVT* | BVFL* | BVTL* |
455
// 11 | --- | --- | --- | --- | --- | --- | --- | --- |
456
// hi |-------|-------|-------|-------|-------|-------|-------|-------|
457
{ "bvf", "jb,i16", MIPS_COP2BC(0x00), MA_PSP, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
458
{ "bvf.B", "i16", MIPS_COP2BC(0x00), MA_PSP, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
459
{ "bvt", "jb,i16", MIPS_COP2BC(0x01), MA_PSP, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
460
{ "bvt.B", "i16", MIPS_COP2BC(0x01), MA_PSP, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
461
{ "bvfl", "jb,i16", MIPS_COP2BC(0x02), MA_PSP, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
462
{ "bvfl.B", "i16", MIPS_COP2BC(0x02), MA_PSP, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
463
{ "bvtl", "jb,i16", MIPS_COP2BC(0x03), MA_PSP, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
464
{ "bvtl.B", "i16", MIPS_COP2BC(0x03), MA_PSP, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
466
// 31---------26-----23--------------------------------------------0
468
// ------6--------3-------------------------------------------------
469
// |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--|
470
// 000 | VADD | VSUB | VSBN | --- | --- | --- | --- | VDIV | 00..07
471
// hi |-------|-------|-------|-------|-------|-------|-------|-------|
472
{ "vadd.S", "vd,vs,vt", MIPS_VFPU0(0x00), MA_PSP, MO_VFPU },
473
{ "vsub.S", "vd,vs,vt", MIPS_VFPU0(0x01), MA_PSP, MO_VFPU },
474
{ "vsbn.S", "vd,vs,vt", MIPS_VFPU0(0x02), MA_PSP, MO_VFPU },
475
{ "vdiv.S", "vd,vs,vt", MIPS_VFPU0(0x07), MA_PSP, MO_VFPU },
477
// 31-------26-----23----------------------------------------------0
479
// -----6-------3---------------------------------------------------
480
// |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--|
481
// | VMUL | VDOT | VSCL | --- | VHDP | VDET | VCRS | --- |
482
// |-------|-------|-------|-------|-------|-------|-------|-------|
483
{ "vmul.S", "vd,vs,vt", MIPS_VFPU1(0), MA_PSP, MO_VFPU },
484
{ "vdot.S", "vd,vs,vt", MIPS_VFPU1(1), MA_PSP, MO_VFPU },
485
{ "vscl.S", "vd,vs,vt", MIPS_VFPU1(2), MA_PSP, MO_VFPU },
486
{ "vhdp.S", "vd,vs,vt", MIPS_VFPU1(4), MA_PSP, MO_VFPU },
487
{ "vdet.S", "vd,vs,vt", MIPS_VFPU1(5), MA_PSP, MO_VFPU },
488
{ "vcrs.S", "vd,vs,vt", MIPS_VFPU1(6), MA_PSP, MO_VFPU },
490
// 31-------26-----23----------------------------------------------0
492
// -----6-------3---------------------------------------------------
493
// |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--|
494
// | VCMP | --- | VMIN | VMAX | --- | VSCMP | VSGE | VSLT |
495
// |-------|-------|-------|-------|-------|-------|-------|-------|
496
// VVVVVV VVV TTTTTTT z SSSSSSS z --- CCCC
497
{ "vcmp.S", "C,vs,vt", MIPS_VFPU3(0), MA_PSP, MO_VFPU },
498
{ "vmin.S", "vd,vs,vt", MIPS_VFPU3(2), MA_PSP, MO_VFPU },
499
{ "vmax.S", "vd,vs,vt", MIPS_VFPU3(3), MA_PSP, MO_VFPU },
500
{ "vscmp.S", "vd,vs,vt", MIPS_VFPU3(5), MA_PSP, MO_VFPU },
501
{ "vsge.S", "vd,vs,vt", MIPS_VFPU3(6), MA_PSP, MO_VFPU },
502
{ "vslt.S", "vd,vs,vt", MIPS_VFPU3(7), MA_PSP, MO_VFPU },
504
// 31-------26--------------------------------------------5--------0
505
// |=SPECIAL3| | function|
506
// -----11----------------------------------------------------6-----
507
// -----6-------5---------------------------------------------------
508
// |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
509
// 000 | EXT | --- | --- | --- | INS | --- | --- | --- |
510
// 001 | --- | --- | --- | --- | --- | --- | --- | --- |
511
// 010 | --- | --- | --- | --- | --- | --- | --- | --- |
512
// 011 | --- | --- | --- | --- | --- | --- | --- | --- |
513
// 100 |ALLEGRE| --- | --- | --- | --- | --- | --- | --- |
514
// 101 | --- | --- | --- | --- | --- | --- | --- | --- |
515
// 110 | --- | --- | --- | --- | --- | --- | --- | --- |
516
// 110 | --- | --- | --- | --- | --- | --- | --- | --- |
517
// hi |-------|-------|-------|-------|-------|-------|-------|-------|
518
{ "ext", "t,s,i5,je", MIPS_SPECIAL3(0), MA_PSP },
519
{ "ins", "t,s,i5,ji", MIPS_SPECIAL3(4), MA_PSP },
521
// 31-------26----------------------------------10--------5--------0
522
// |=SPECIAL3| | secfunc |ALLEGREX0|
523
// ------11---------5-------------------------------5---------6-----
524
// |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
525
// 00 | --- | --- | WSBH | WSBW | --- | --- | --- | --- |
526
// 01 | --- | --- | --- | --- | --- | --- | --- | --- |
527
// 10 | SEB | --- | --- | --- |BITREV | --- | --- | --- |
528
// 11 | SEH | --- | --- | --- | --- | --- | --- | --- |
529
// hi |-------|-------|-------|-------|-------|-------|-------|-------|
530
// VVVVVV ----- ttttt ddddd VVVVV VVVVVV
531
{ "wsbh", "d,t", MIPS_ALLEGREX0(0x02), MA_PSP },
532
{ "wsbh", "d", MIPS_ALLEGREX0(0x02), MA_PSP },
533
{ "wsbw", "d,t", MIPS_ALLEGREX0(0x03), MA_PSP },
534
{ "wsbw", "d", MIPS_ALLEGREX0(0x03), MA_PSP },
535
{ "seb", "d,t", MIPS_ALLEGREX0(0x10), MA_PSP },
536
{ "seb", "d", MIPS_ALLEGREX0(0x10), MA_PSP },
537
{ "bitrev", "d,t", MIPS_ALLEGREX0(0x14), MA_PSP },
538
{ "bitrev", "d", MIPS_ALLEGREX0(0x14), MA_PSP },
539
{ "seh", "d,t", MIPS_ALLEGREX0(0x18), MA_PSP },
540
{ "seh", "d", MIPS_ALLEGREX0(0x18), MA_PSP },
543
// VFPU4: This one is a bit messy.
544
// 31-------26------21---------------------------------------------0
546
// -----6-------5---------------------------------------------------
547
// hi |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
548
// 00 |VF4-1.1|VF4-1.2|VF4-1.3| VCST | --- | --- | --- | --- |
549
// 01 | --- | --- | --- | --- | --- | --- | --- | --- |
550
// 10 | VF2IN | VF2IZ | VF2IU | VF2ID | VI2F | VCMOV | --- | --- |
551
// 11 | VWBN | VWBN | VWBN | VWBN | VWBN | VWBN | VWBN | VWBN |
552
// |-------|-------|-------|-------|-------|-------|-------|-------|
553
// VVVVVV VVVVV iiiii z ------- z DDDDDDD
554
// Technically these also have names (as the second arg.)
555
{ "vcst.S", "vd,Wc", MIPS_VFPU4(0x03), MA_PSP, MO_VFPU },
556
{ "vf2in.S", "vd,vs,i5", MIPS_VFPU4(0x10), MA_PSP, MO_VFPU },
557
{ "vf2iz.S", "vd,vs,i5", MIPS_VFPU4(0x11), MA_PSP, MO_VFPU },
558
{ "vf2iu.S", "vd,vs,i5", MIPS_VFPU4(0x12), MA_PSP, MO_VFPU },
559
{ "vf2id.S", "vd,vs,i5", MIPS_VFPU4(0x13), MA_PSP, MO_VFPU },
560
{ "vi2f.S", "vd,vs,i5", MIPS_VFPU4(0x14), MA_PSP, MO_VFPU },
561
{ "vcmovt.S", "vd,vs,i5", MIPS_VFPU4(0x15) | 0x00000000, MA_PSP, MO_VFPU },
562
{ "vcmovf.S", "vd,vs,i5", MIPS_VFPU4(0x15) | 0x00080000, MA_PSP, MO_VFPU },
563
{ "vwbn.S", "vd,vs,i5", MIPS_VFPU4(0x18), MA_PSP, MO_VFPU },
565
// 31-------------21-------16--------------------------------------0
566
// |= VF4-1.1 | rt | |
567
// --------11----------5--------------------------------------------
568
// hi |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
569
// 00 | VMOV | VABS | VNEG | VIDT | vsAT0 | vsAT1 | VZERO | VONE |
570
// 01 | --- | --- | --- | --- | --- | --- | --- | --- |
571
// 10 | VRCP | VRSQ | vsIN | VCOS | VEXP2 | VLOG2 | vsQRT | VASIN |
572
// 11 | VNRCP | --- | VNSIN | --- |VREXP2 | --- | --- | --- |
573
// |-------|-------|-------|-------|-------|-------|-------|-------|
574
{ "vmov.S", "vd,vs", MIPS_VFPU4_11(0x00), MA_PSP, MO_VFPU },
575
{ "vabs.S", "vd,vs", MIPS_VFPU4_11(0x01), MA_PSP, MO_VFPU },
576
{ "vneg.S", "vd,vs", MIPS_VFPU4_11(0x02), MA_PSP, MO_VFPU },
577
{ "vidt.S", "vd", MIPS_VFPU4_11(0x03), MA_PSP, MO_VFPU },
578
{ "vsat0.S", "vd,vs", MIPS_VFPU4_11(0x04), MA_PSP, MO_VFPU },
579
{ "vsat1.S", "vd,vs", MIPS_VFPU4_11(0x05), MA_PSP, MO_VFPU },
580
{ "vzero.S", "vd", MIPS_VFPU4_11(0x06), MA_PSP, MO_VFPU },
581
{ "vone.S", "vd", MIPS_VFPU4_11(0x07), MA_PSP, MO_VFPU },
582
{ "vrcp.S", "vd,vs", MIPS_VFPU4_11(0x10), MA_PSP, MO_VFPU },
583
{ "vrsq.S", "vd,vs", MIPS_VFPU4_11(0x11), MA_PSP, MO_VFPU },
584
{ "vsin.S", "vd,vs", MIPS_VFPU4_11(0x12), MA_PSP, MO_VFPU },
585
{ "vcos.S", "vd,vs", MIPS_VFPU4_11(0x13), MA_PSP, MO_VFPU },
586
{ "vexp2.S", "vd,vs", MIPS_VFPU4_11(0x14), MA_PSP, MO_VFPU },
587
{ "vlog2.S", "vd,vs", MIPS_VFPU4_11(0x15), MA_PSP, MO_VFPU },
588
{ "vsqrt.S", "vd,vs", MIPS_VFPU4_11(0x16), MA_PSP, MO_VFPU },
589
{ "vasin.S", "vd,vs", MIPS_VFPU4_11(0x17), MA_PSP, MO_VFPU },
590
{ "vnrcp.S", "vd,vs", MIPS_VFPU4_11(0x18), MA_PSP, MO_VFPU },
591
{ "vnsin.S", "vd,vs", MIPS_VFPU4_11(0x1a), MA_PSP, MO_VFPU },
592
{ "vrexp2.S", "vd,vs", MIPS_VFPU4_11(0x1c), MA_PSP, MO_VFPU },
594
// VFPU4 1.2: TODO: Unsure where vsBZ goes, no one uses it.
595
// 31-------------21-------16--------------------------------------0
596
// |= VF4-1.2 | rt | |
597
// --------11----------5--------------------------------------------
598
// hi |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
599
// 00 | VRNDS | VRNDI |VRNDF1 |VRNDF2 | --- | --- | --- | --- |
600
// 01 | --- | --- | --- | --- | vsBZ? | --- | --- | --- |
601
// 10 | --- | --- | VF2H | VH2F | --- | --- | vsBZ? | VLGB |
602
// 11 | VUC2I | VC2I | VUS2I | vs2I | VI2UC | VI2C | VI2US | VI2S |
603
// |-------|-------|-------|-------|-------|-------|-------|-------|
604
{ "vrnds.S", "vd", MIPS_VFPU4_12(0x00), MA_PSP, MO_VFPU },
605
{ "vrndi.S", "vd", MIPS_VFPU4_12(0x01), MA_PSP, MO_VFPU },
606
{ "vrndf1.S", "vd", MIPS_VFPU4_12(0x02), MA_PSP, MO_VFPU },
607
{ "vrndf2.S", "vd", MIPS_VFPU4_12(0x03), MA_PSP, MO_VFPU },
609
{ "vf2h.S", "vd,vs", MIPS_VFPU4_12(0x12), MA_PSP, MO_VFPU },
610
{ "vh2f.S", "vd,vs", MIPS_VFPU4_12(0x13), MA_PSP, MO_VFPU },
612
{ "vlgb.S", "vd,vs", MIPS_VFPU4_12(0x17), MA_PSP, MO_VFPU },
613
{ "vuc2i.S", "vd,vs", MIPS_VFPU4_12(0x18), MA_PSP, MO_VFPU },
614
{ "vc2i.S", "vd,vs", MIPS_VFPU4_12(0x19), MA_PSP, MO_VFPU },
615
{ "vus2i.S", "vd,vs", MIPS_VFPU4_12(0x1a), MA_PSP, MO_VFPU },
616
{ "vs2i.S", "vd,vs", MIPS_VFPU4_12(0x1b), MA_PSP, MO_VFPU },
617
{ "vi2uc.S", "vd,vs", MIPS_VFPU4_12(0x1c), MA_PSP, MO_VFPU },
618
{ "vi2c.S", "vd,vs", MIPS_VFPU4_12(0x1d), MA_PSP, MO_VFPU },
619
{ "vi2us.S", "vd,vs", MIPS_VFPU4_12(0x1e), MA_PSP, MO_VFPU },
620
{ "vi2s.S", "vd,vs", MIPS_VFPU4_12(0x1f), MA_PSP, MO_VFPU },
622
// 31--------------21------16--------------------------------------0
623
// |= VF4-1.3 | rt | |
624
// --------11----------5--------------------------------------------
625
// hi |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
626
// 00 | vsRT1 | vsRT2 | VBFY1 | VBFY2 | VOCP | vsOCP | VFAD | VAVG |
627
// 01 | vsRT3 | vsRT4 | vsGN | --- | --- | --- | --- | --- |
628
// 10 | VMFVC | VMTVC | --- | --- | --- | --- | --- | --- |
629
// 11 | --- |VT4444 |VT5551 |VT5650 | --- | --- | --- | --- |
630
// |-------|-------|-------|-------|-------|-------|-------|-------|
631
{ "vsrt1.S", "vd,vs", MIPS_VFPU4_13(0x00), MA_PSP, MO_VFPU },
632
{ "vsrt2.S", "vd,vs", MIPS_VFPU4_13(0x01), MA_PSP, MO_VFPU },
633
{ "vbfy1.S", "vd,vs", MIPS_VFPU4_13(0x02), MA_PSP, MO_VFPU },
634
{ "vbfy2.S", "vd,vs", MIPS_VFPU4_13(0x03), MA_PSP, MO_VFPU },
635
{ "vocp.S", "vd,vs", MIPS_VFPU4_13(0x04), MA_PSP, MO_VFPU },
636
{ "vsocp.S", "vd,vs", MIPS_VFPU4_13(0x05), MA_PSP, MO_VFPU },
637
{ "vfad.S", "vd,vs", MIPS_VFPU4_13(0x06), MA_PSP, MO_VFPU },
638
{ "vavg.S", "vd,vs", MIPS_VFPU4_13(0x07), MA_PSP, MO_VFPU },
639
{ "vsrt3.S", "vd,vs", MIPS_VFPU4_13(0x08), MA_PSP, MO_VFPU },
640
{ "vsrt4.S", "vd,vs", MIPS_VFPU4_13(0x09), MA_PSP, MO_VFPU },
641
{ "vsgn.S", "vd,vs", MIPS_VFPU4_13(0x0a), MA_PSP, MO_VFPU },
642
{ "vmfv.S", "vs,i7", MIPS_VFPU4_13(0x10) | 0x00, MA_PSP, MO_VFPU },
643
{ "vmtv.S", "vs,i7", MIPS_VFPU4_13(0x11) | 0x00, MA_PSP, MO_VFPU },
644
{ "vmfvc.S", "vs,i7", MIPS_VFPU4_13(0x10) | 0x80, MA_PSP, MO_VFPU },
645
{ "vmtvc.S", "vs,i7", MIPS_VFPU4_13(0x11) | 0x80, MA_PSP, MO_VFPU },
646
{ "vt4444.S", "vd,vs", MIPS_VFPU4_13(0x19), MA_PSP, MO_VFPU },
647
{ "vt5551.S", "vd,vs", MIPS_VFPU4_13(0x1a), MA_PSP, MO_VFPU },
648
{ "vt5650.S", "vd,vs", MIPS_VFPU4_13(0x1b), MA_PSP, MO_VFPU },
650
// 31-------26-----23----------------------------------------------0
652
// -----6-------3---------------------------------------------------
653
// |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
654
// | VPFXS | VPFXS | VPFXT | VPFXT | VPFXD | VPFXD | VIIM | VFIM |
655
// |-------|-------|-------|-------|-------|-------|-------|-------|
656
{ "vpfxs", "Ws", MIPS_VFPU5(0), MA_PSP },
657
{ "vpfxt", "Ws", MIPS_VFPU5(2), MA_PSP },
658
{ "vpfxd", "Wd", MIPS_VFPU5(4), MA_PSP },
659
{ "viim.s", "vt,i16", MIPS_VFPU5(6), MA_PSP, MO_VFPU_SINGLE },
660
{ "vfim.s", "vt,ih", MIPS_VFPU5(7), MA_PSP, MO_VFPU_SINGLE },
662
// 31-------26-----23----------------------------------------------0
664
// -----6-------3---------------------------------------------------
665
// |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
666
// | VMMUL | V(H)TFM2/3/4 | VMSCL | *1 | --- |VF6-1.1|
667
// |-------|-------|-------|-------|-------|-------|-------|-------|
668
// *1: vcrsp.t/vqmul.q
669
{ "vmmul.S", "md,ms,mt", MIPS_VFPU6(0), MA_PSP, MO_VFPU|MO_TRANSPOSE_VS },
670
{ "vtfm2.p", "vd,ms,vt", MIPS_VFPU6(1)|MIPS_VFPUSIZE(1), MA_PSP, MO_VFPU|MO_VFPU_PAIR },
671
{ "vhtfm2.p", "vd,ms,vt", MIPS_VFPU6(2)|MIPS_VFPUSIZE(1), MA_PSP, MO_VFPU|MO_VFPU_PAIR },
672
{ "vtfm3.t", "vd,ms,vt", MIPS_VFPU6(2)|MIPS_VFPUSIZE(2), MA_PSP, MO_VFPU|MO_VFPU_TRIPLE },
673
{ "vhtfm3.t", "vd,ms,vt", MIPS_VFPU6(3)|MIPS_VFPUSIZE(2), MA_PSP, MO_VFPU|MO_VFPU_TRIPLE },
674
{ "vtfm4.q", "vd,ms,vt", MIPS_VFPU6(3)|MIPS_VFPUSIZE(3), MA_PSP, MO_VFPU|MO_VFPU_QUAD },
675
{ "vmscl.S", "md,ms,vSt", MIPS_VFPU6(4), MA_PSP, MO_VFPU },
676
{ "vcrsp.t", "vd,vs,vt", MIPS_VFPU6(5)|MIPS_VFPUSIZE(2), MA_PSP, MO_VFPU|MO_VFPU_TRIPLE },
677
{ "vqmul.q", "vd,vs,vt", MIPS_VFPU6(5)|MIPS_VFPUSIZE(3), MA_PSP, MO_VFPU|MO_VFPU_QUAD },
679
// 31--------23----20----------------------------------------------0
680
// |= VF6-1.1 | f | |
681
// -----9-------3---------------------------------------------------
682
// |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
683
// |VF6-1.2| --- | VROT | --- | --- | --- | --- |
684
// |-------|-------|-------|-------|-------|-------|-------|-------|
685
// VVVVVVVVVVV iiiii z SSSSSSS z DDDDDDD
686
{ "vrot.S", "vd,vSs,Wr", MIPS_VFPU6_1VROT(), MA_PSP, MO_VFPU },
688
// 31--------20----16----------------------------------------------0
689
// |= VF6-1.2 | f | |
690
// -----6-------4---------------------------------------------------
691
// hi |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
692
// 0 | VMMOV | --- | --- | VMIDT | --- | --- |VMZERO | VMONE |
693
// 1 | --- | --- | --- | --- | --- | --- | --- | --- |
694
// |-------|-------|-------|-------|-------|-------|-------|-------|
695
// VVVVVVVVVVVVVVVV z SSSSSSS z DDDDDDD
696
{ "vmmov.S", "md,ms", MIPS_VFPU6_2(0), MA_PSP, MO_VFPU },
697
// VVVVVVVVVVVVVVVV z ------- z DDDDDDD
698
{ "vmidt.S", "md", MIPS_VFPU6_2(3), MA_PSP, MO_VFPU },
699
{ "vmzero.S", "md", MIPS_VFPU6_2(6), MA_PSP, MO_VFPU },
700
{ "vmone.S", "md", MIPS_VFPU6_2(7), MA_PSP, MO_VFPU },
706
const MipsArchDefinition mipsArchs[] = {
708
{ "PSX", MA_MIPS1, MA_EXPSX, 0 },
710
{ "N64", MA_MIPS1|MA_MIPS2|MA_MIPS3, MA_EXN64, MO_FPU },
712
{ "PS2", MA_MIPS1|MA_MIPS2|MA_MIPS3|MA_PS2, MA_EXPS2, MO_64BIT|MO_FPU },
714
{ "PSP", MA_MIPS1|MA_MIPS2|MA_MIPS3|MA_PSP, MA_EXPSP, MO_FPU },
716
{ "Invalid", 0, 0, 0 },
b'\\ No newline at end of file'
added
removed
ext/armips/Archs/MIPS/MipsOpcodes.cpp
