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Viewing changes to arch/powerpc/boot/dts/p2020rdb.dts

  • Committer: Package Import Robot
  • Author(s): John Rigby, John Rigby
  • Date: 2011-09-26 10:44:23 UTC
  • Revision ID: package-import@ubuntu.com-20110926104423-57i0gl3v99b3lkfg
Tags: 3.0.0-1007.9
https://launchpad.net/bugs/826021
[ John Rigby ]

Enable crypto modules and remove crypto-modules from
exclude-module files
LP: #826021

Show diffs side-by-side

added added

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Lines of Context:
arch/powerpc/boot/dts/p2020rdb.dts
9
9
 * option) any later version.
10
10
 */
11
11
 
12
 
/dts-v1/;
 
12
/include/ "p2020si.dtsi"
 
13
 
13
14
/ {
14
 
        model = "fsl,P2020";
 
15
        model = "fsl,P2020RDB";
15
16
        compatible = "fsl,P2020RDB";
16
 
        #address-cells = <2>;
17
 
        #size-cells = <2>;
18
17
 
19
18
        aliases {
20
19
                ethernet0 = &enet0;
26
25
                pci1 = &pci1;
27
26
        };
28
27
 
29
 
        cpus {
30
 
                #address-cells = <1>;
31
 
                #size-cells = <0>;
32
 
 
33
 
                PowerPC,P2020@0 {
34
 
                        device_type = "cpu";
35
 
                        reg = <0x0>;
36
 
                        next-level-cache = <&L2>;
37
 
                };
38
 
 
39
 
                PowerPC,P2020@1 {
40
 
                        device_type = "cpu";
41
 
                        reg = <0x1>;
42
 
                        next-level-cache = <&L2>;
43
 
                };
44
 
        };
45
 
 
46
28
        memory {
47
29
                device_type = "memory";
48
30
        };
49
31
 
50
32
        localbus@ffe05000 {
51
 
                #address-cells = <2>;
52
 
                #size-cells = <1>;
53
 
                compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus";
54
 
                reg = <0 0xffe05000 0 0x1000>;
55
 
                interrupts = <19 2>;
56
 
                interrupt-parent = <&mpic>;
57
33
 
58
34
                /* NOR and NAND Flashes */
59
35
                ranges = <0x0 0x0 0x0 0xef000000 0x01000000
165
141
        };
166
142
 
167
143
        soc@ffe00000 {
168
 
                #address-cells = <1>;
169
 
                #size-cells = <1>;
170
 
                device_type = "soc";
171
 
                compatible = "fsl,p2020-immr", "simple-bus";
172
 
                ranges = <0x0  0x0 0xffe00000 0x100000>;
173
 
                bus-frequency = <0>;            // Filled out by uboot.
174
 
 
175
 
                ecm-law@0 {
176
 
                        compatible = "fsl,ecm-law";
177
 
                        reg = <0x0 0x1000>;
178
 
                        fsl,num-laws = <12>;
179
 
                };
180
 
 
181
 
                ecm@1000 {
182
 
                        compatible = "fsl,p2020-ecm", "fsl,ecm";
183
 
                        reg = <0x1000 0x1000>;
184
 
                        interrupts = <17 2>;
185
 
                        interrupt-parent = <&mpic>;
186
 
                };
187
 
 
188
 
                memory-controller@2000 {
189
 
                        compatible = "fsl,p2020-memory-controller";
190
 
                        reg = <0x2000 0x1000>;
191
 
                        interrupt-parent = <&mpic>;
192
 
                        interrupts = <18 2>;
193
 
                };
194
 
 
195
144
                i2c@3000 {
196
 
                        #address-cells = <1>;
197
 
                        #size-cells = <0>;
198
 
                        cell-index = <0>;
199
 
                        compatible = "fsl-i2c";
200
 
                        reg = <0x3000 0x100>;
201
 
                        interrupts = <43 2>;
202
 
                        interrupt-parent = <&mpic>;
203
 
                        dfsrr;
204
145
                        rtc@68 {
205
146
                                compatible = "dallas,ds1339";
206
147
                                reg = <0x68>;
207
148
                        };
208
149
                };
209
150
 
210
 
                i2c@3100 {
211
 
                        #address-cells = <1>;
212
 
                        #size-cells = <0>;
213
 
                        cell-index = <1>;
214
 
                        compatible = "fsl-i2c";
215
 
                        reg = <0x3100 0x100>;
216
 
                        interrupts = <43 2>;
217
 
                        interrupt-parent = <&mpic>;
218
 
                        dfsrr;
219
 
                };
220
 
 
221
 
                serial0: serial@4500 {
222
 
                        cell-index = <0>;
223
 
                        device_type = "serial";
224
 
                        compatible = "ns16550";
225
 
                        reg = <0x4500 0x100>;
226
 
                        clock-frequency = <0>;
227
 
                        interrupts = <42 2>;
228
 
                        interrupt-parent = <&mpic>;
229
 
                };
230
 
 
231
 
                serial1: serial@4600 {
232
 
                        cell-index = <1>;
233
 
                        device_type = "serial";
234
 
                        compatible = "ns16550";
235
 
                        reg = <0x4600 0x100>;
236
 
                        clock-frequency = <0>;
237
 
                        interrupts = <42 2>;
238
 
                        interrupt-parent = <&mpic>;
239
 
                };
240
 
 
241
 
                spi@7000 {
242
 
                        cell-index = <0>;
243
 
                        #address-cells = <1>;
244
 
                        #size-cells = <0>;
245
 
                        compatible = "fsl,espi";
246
 
                        reg = <0x7000 0x1000>;
247
 
                        interrupts = <59 0x2>;
248
 
                        interrupt-parent = <&mpic>;
249
 
                        mode = "cpu";
250
 
 
251
 
                        fsl_m25p80@0 {
 
151
        spi@7000 {
 
152
 
 
153
                fsl_m25p80@0 {
252
154
                                #address-cells = <1>;
253
155
                                #size-cells = <1>;
254
156
                                compatible = "fsl,espi-flash";
294
196
                        };
295
197
                };
296
198
 
297
 
                dma@c300 {
298
 
                        #address-cells = <1>;
299
 
                        #size-cells = <1>;
300
 
                        compatible = "fsl,eloplus-dma";
301
 
                        reg = <0xc300 0x4>;
302
 
                        ranges = <0x0 0xc100 0x200>;
303
 
                        cell-index = <1>;
304
 
                        dma-channel@0 {
305
 
                                compatible = "fsl,eloplus-dma-channel";
306
 
                                reg = <0x0 0x80>;
307
 
                                cell-index = <0>;
308
 
                                interrupt-parent = <&mpic>;
309
 
                                interrupts = <76 2>;
310
 
                        };
311
 
                        dma-channel@80 {
312
 
                                compatible = "fsl,eloplus-dma-channel";
313
 
                                reg = <0x80 0x80>;
314
 
                                cell-index = <1>;
315
 
                                interrupt-parent = <&mpic>;
316
 
                                interrupts = <77 2>;
317
 
                        };
318
 
                        dma-channel@100 {
319
 
                                compatible = "fsl,eloplus-dma-channel";
320
 
                                reg = <0x100 0x80>;
321
 
                                cell-index = <2>;
322
 
                                interrupt-parent = <&mpic>;
323
 
                                interrupts = <78 2>;
324
 
                        };
325
 
                        dma-channel@180 {
326
 
                                compatible = "fsl,eloplus-dma-channel";
327
 
                                reg = <0x180 0x80>;
328
 
                                cell-index = <3>;
329
 
                                interrupt-parent = <&mpic>;
330
 
                                interrupts = <79 2>;
331
 
                        };
332
 
                };
333
 
 
334
 
                gpio: gpio-controller@f000 {
335
 
                        #gpio-cells = <2>;
336
 
                        compatible = "fsl,mpc8572-gpio";
337
 
                        reg = <0xf000 0x100>;
338
 
                        interrupts = <47 0x2>;
339
 
                        interrupt-parent = <&mpic>;
340
 
                        gpio-controller;
341
 
                };
342
 
 
343
 
                L2: l2-cache-controller@20000 {
344
 
                        compatible = "fsl,p2020-l2-cache-controller";
345
 
                        reg = <0x20000 0x1000>;
346
 
                        cache-line-size = <32>; // 32 bytes
347
 
                        cache-size = <0x80000>; // L2,512K
348
 
                        interrupt-parent = <&mpic>;
349
 
                        interrupts = <16 2>;
350
 
                };
351
 
 
352
 
                dma@21300 {
353
 
                        #address-cells = <1>;
354
 
                        #size-cells = <1>;
355
 
                        compatible = "fsl,eloplus-dma";
356
 
                        reg = <0x21300 0x4>;
357
 
                        ranges = <0x0 0x21100 0x200>;
358
 
                        cell-index = <0>;
359
 
                        dma-channel@0 {
360
 
                                compatible = "fsl,eloplus-dma-channel";
361
 
                                reg = <0x0 0x80>;
362
 
                                cell-index = <0>;
363
 
                                interrupt-parent = <&mpic>;
364
 
                                interrupts = <20 2>;
365
 
                        };
366
 
                        dma-channel@80 {
367
 
                                compatible = "fsl,eloplus-dma-channel";
368
 
                                reg = <0x80 0x80>;
369
 
                                cell-index = <1>;
370
 
                                interrupt-parent = <&mpic>;
371
 
                                interrupts = <21 2>;
372
 
                        };
373
 
                        dma-channel@100 {
374
 
                                compatible = "fsl,eloplus-dma-channel";
375
 
                                reg = <0x100 0x80>;
376
 
                                cell-index = <2>;
377
 
                                interrupt-parent = <&mpic>;
378
 
                                interrupts = <22 2>;
379
 
                        };
380
 
                        dma-channel@180 {
381
 
                                compatible = "fsl,eloplus-dma-channel";
382
 
                                reg = <0x180 0x80>;
383
 
                                cell-index = <3>;
384
 
                                interrupt-parent = <&mpic>;
385
 
                                interrupts = <23 2>;
386
 
                        };
387
 
                };
388
 
 
389
199
                usb@22000 {
390
 
                        #address-cells = <1>;
391
 
                        #size-cells = <0>;
392
 
                        compatible = "fsl-usb2-dr";
393
 
                        reg = <0x22000 0x1000>;
394
 
                        interrupt-parent = <&mpic>;
395
 
                        interrupts = <28 0x2>;
396
200
                        phy_type = "ulpi";
397
201
                };
398
202
 
 
203
                mdio@24520 {
 
204
                        phy0: ethernet-phy@0 {
 
205
                                interrupt-parent = <&mpic>;
 
206
                                interrupts = <3 1>;
 
207
                                reg = <0x0>;
 
208
                                };
 
209
                        phy1: ethernet-phy@1 {
 
210
                                interrupt-parent = <&mpic>;
 
211
                                interrupts = <3 1>;
 
212
                                reg = <0x1>;
 
213
                                };
 
214
                };
 
215
 
 
216
                mdio@25520 {
 
217
                        tbi0: tbi-phy@11 {
 
218
                                reg = <0x11>;
 
219
                                device_type = "tbi-phy";
 
220
                        };
 
221
                };
 
222
 
 
223
                mdio@26520 {
 
224
                        status = "disabled";
 
225
                };
 
226
 
 
227
                ptp_clock@24E00 {
 
228
                        compatible = "fsl,etsec-ptp";
 
229
                        reg = <0x24E00 0xB0>;
 
230
                        interrupts = <68 2 69 2 70 2>;
 
231
                        interrupt-parent = < &mpic >;
 
232
                        fsl,tclk-period = <5>;
 
233
                        fsl,tmr-prsc = <200>;
 
234
                        fsl,tmr-add = <0xCCCCCCCD>;
 
235
                        fsl,tmr-fiper1 = <0x3B9AC9FB>;
 
236
                        fsl,tmr-fiper2 = <0x0001869B>;
 
237
                        fsl,max-adj = <249999999>;
 
238
                };
 
239
 
399
240
                enet0: ethernet@24000 {
400
 
                        #address-cells = <1>;
401
 
                        #size-cells = <1>;
402
 
                        cell-index = <0>;
403
 
                        device_type = "network";
404
 
                        model = "eTSEC";
405
 
                        compatible = "gianfar";
406
 
                        reg = <0x24000 0x1000>;
407
 
                        ranges = <0x0 0x24000 0x1000>;
408
 
                        local-mac-address = [ 00 00 00 00 00 00 ];
409
 
                        interrupts = <29 2 30 2 34 2>;
410
 
                        interrupt-parent = <&mpic>;
411
241
                        fixed-link = <1 1 1000 0 0>;
412
242
                        phy-connection-type = "rgmii-id";
413
 
 
414
 
                        mdio@520 {
415
 
                                #address-cells = <1>;
416
 
                                #size-cells = <0>;
417
 
                                compatible = "fsl,gianfar-mdio";
418
 
                                reg = <0x520 0x20>;
419
 
 
420
 
                                phy0: ethernet-phy@0 {
421
 
                                        interrupt-parent = <&mpic>;
422
 
                                        interrupts = <3 1>;
423
 
                                        reg = <0x0>;
424
 
                                };
425
 
                                phy1: ethernet-phy@1 {
426
 
                                        interrupt-parent = <&mpic>;
427
 
                                        interrupts = <3 1>;
428
 
                                        reg = <0x1>;
429
 
                                };
430
 
                        };
431
243
                };
432
244
 
433
245
                enet1: ethernet@25000 {
434
 
                        #address-cells = <1>;
435
 
                        #size-cells = <1>;
436
 
                        cell-index = <1>;
437
 
                        device_type = "network";
438
 
                        model = "eTSEC";
439
 
                        compatible = "gianfar";
440
 
                        reg = <0x25000 0x1000>;
441
 
                        ranges = <0x0 0x25000 0x1000>;
442
 
                        local-mac-address = [ 00 00 00 00 00 00 ];
443
 
                        interrupts = <35 2 36 2 40 2>;
444
 
                        interrupt-parent = <&mpic>;
445
246
                        tbi-handle = <&tbi0>;
446
247
                        phy-handle = <&phy0>;
447
248
                        phy-connection-type = "sgmii";
448
 
 
449
 
                        mdio@520 {
450
 
                                #address-cells = <1>;
451
 
                                #size-cells = <0>;
452
 
                                compatible = "fsl,gianfar-tbi";
453
 
                                reg = <0x520 0x20>;
454
 
 
455
 
                                tbi0: tbi-phy@11 {
456
 
                                        reg = <0x11>;
457
 
                                        device_type = "tbi-phy";
458
 
                                };
459
 
                        };
460
249
                };
461
250
 
462
251
                enet2: ethernet@26000 {
463
 
                        #address-cells = <1>;
464
 
                        #size-cells = <1>;
465
 
                        cell-index = <2>;
466
 
                        device_type = "network";
467
 
                        model = "eTSEC";
468
 
                        compatible = "gianfar";
469
 
                        reg = <0x26000 0x1000>;
470
 
                        ranges = <0x0 0x26000 0x1000>;
471
 
                        local-mac-address = [ 00 00 00 00 00 00 ];
472
 
                        interrupts = <31 2 32 2 33 2>;
473
 
                        interrupt-parent = <&mpic>;
474
252
                        phy-handle = <&phy1>;
475
253
                        phy-connection-type = "rgmii-id";
476
254
                };
477
255
 
478
 
                sdhci@2e000 {
479
 
                        compatible = "fsl,p2020-esdhc", "fsl,esdhc";
480
 
                        reg = <0x2e000 0x1000>;
481
 
                        interrupts = <72 0x2>;
482
 
                        interrupt-parent = <&mpic>;
483
 
                        /* Filled in by U-Boot */
484
 
                        clock-frequency = <0>;
485
 
                };
486
 
 
487
 
                crypto@30000 {
488
 
                        compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
489
 
                                     "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
490
 
                        reg = <0x30000 0x10000>;
491
 
                        interrupts = <45 2 58 2>;
492
 
                        interrupt-parent = <&mpic>;
493
 
                        fsl,num-channels = <4>;
494
 
                        fsl,channel-fifo-len = <24>;
495
 
                        fsl,exec-units-mask = <0xbfe>;
496
 
                        fsl,descriptor-types-mask = <0x3ab0ebf>;
497
 
                };
498
 
 
499
 
                mpic: pic@40000 {
500
 
                        interrupt-controller;
501
 
                        #address-cells = <0>;
502
 
                        #interrupt-cells = <2>;
503
 
                        reg = <0x40000 0x40000>;
504
 
                        compatible = "chrp,open-pic";
505
 
                        device_type = "open-pic";
506
 
                };
507
 
 
508
 
                msi@41600 {
509
 
                        compatible = "fsl,p2020-msi", "fsl,mpic-msi";
510
 
                        reg = <0x41600 0x80>;
511
 
                        msi-available-ranges = <0 0x100>;
512
 
                        interrupts = <
513
 
                                0xe0 0
514
 
                                0xe1 0
515
 
                                0xe2 0
516
 
                                0xe3 0
517
 
                                0xe4 0
518
 
                                0xe5 0
519
 
                                0xe6 0
520
 
                                0xe7 0>;
521
 
                        interrupt-parent = <&mpic>;
522
 
                };
523
 
 
524
 
                global-utilities@e0000 {        //global utilities block
525
 
                        compatible = "fsl,p2020-guts";
526
 
                        reg = <0xe0000 0x1000>;
527
 
                        fsl,has-rstcr;
528
 
                };
529
 
        };
530
 
 
531
 
        pci0: pcie@ffe09000 {
532
 
                compatible = "fsl,mpc8548-pcie";
533
 
                device_type = "pci";
534
 
                #interrupt-cells = <1>;
535
 
                #size-cells = <2>;
536
 
                #address-cells = <3>;
537
 
                reg = <0 0xffe09000 0 0x1000>;
538
 
                bus-range = <0 255>;
 
256
        };
 
257
 
 
258
        pci0: pcie@ffe08000 {
 
259
                status = "disabled";
 
260
        };
 
261
 
 
262
        pci1: pcie@ffe09000 {
539
263
                ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
540
264
                          0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
541
 
                clock-frequency = <33333333>;
542
 
                interrupt-parent = <&mpic>;
543
 
                interrupts = <25 2>;
544
 
                pcie@0 {
 
265
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 
266
                interrupt-map = <
 
267
                        /* IDSEL 0x0 */
 
268
                        0000 0x0 0x0 0x1 &mpic 0x4 0x1
 
269
                        0000 0x0 0x0 0x2 &mpic 0x5 0x1
 
270
                        0000 0x0 0x0 0x3 &mpic 0x6 0x1
 
271
                        0000 0x0 0x0 0x4 &mpic 0x7 0x1
 
272
                        >;
 
273
                        pcie@0 {
545
274
                        reg = <0x0 0x0 0x0 0x0 0x0>;
546
275
                        #size-cells = <2>;
547
276
                        #address-cells = <3>;
556
285
                };
557
286
        };
558
287
 
559
 
        pci1: pcie@ffe0a000 {
560
 
                compatible = "fsl,mpc8548-pcie";
561
 
                device_type = "pci";
562
 
                #interrupt-cells = <1>;
563
 
                #size-cells = <2>;
564
 
                #address-cells = <3>;
565
 
                reg = <0 0xffe0a000 0 0x1000>;
566
 
                bus-range = <0 255>;
 
288
        pci2: pcie@ffe0a000 {
567
289
                ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
568
290
                          0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
569
 
                clock-frequency = <33333333>;
570
 
                interrupt-parent = <&mpic>;
571
 
                interrupts = <26 2>;
 
291
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 
292
                interrupt-map = <
 
293
                        /* IDSEL 0x0 */
 
294
                        0000 0x0 0x0 0x1 &mpic 0x0 0x1
 
295
                        0000 0x0 0x0 0x2 &mpic 0x1 0x1
 
296
                        0000 0x0 0x0 0x3 &mpic 0x2 0x1
 
297
                        0000 0x0 0x0 0x4 &mpic 0x3 0x1
 
298
                        >;
572
299
                pcie@0 {
573
300
                        reg = <0x0 0x0 0x0 0x0 0x0>;
574
301
                        #size-cells = <2>;