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Viewing changes to drivers/net/wireless/rtlwifi/rtl8192se/hw.c

  • Committer: Package Import Robot
  • Author(s): John Rigby, John Rigby
  • Date: 2011-09-26 10:44:23 UTC
  • Revision ID: package-import@ubuntu.com-20110926104423-57i0gl3v99b3lkfg
Tags: 3.0.0-1007.9
https://launchpad.net/bugs/826021
[ John Rigby ]

Enable crypto modules and remove crypto-modules from
exclude-module files
LP: #826021

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added added

removed removed

Lines of Context:
drivers/net/wireless/rtlwifi/rtl8192se/hw.c
 
1
/******************************************************************************
 
2
 *
 
3
 * Copyright(c) 2009-2010  Realtek Corporation.
 
4
 *
 
5
 * This program is free software; you can redistribute it and/or modify it
 
6
 * under the terms of version 2 of the GNU General Public License as
 
7
 * published by the Free Software Foundation.
 
8
 *
 
9
 * This program is distributed in the hope that it will be useful, but WITHOUT
 
10
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 
11
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 
12
 * more details.
 
13
 *
 
14
 * You should have received a copy of the GNU General Public License along with
 
15
 * this program; if not, write to the Free Software Foundation, Inc.,
 
16
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
 
17
 *
 
18
 * The full GNU General Public License is included in this distribution in the
 
19
 * file called LICENSE.
 
20
 *
 
21
 * Contact Information:
 
22
 * wlanfae <wlanfae@realtek.com>
 
23
 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
 
24
 * Hsinchu 300, Taiwan.
 
25
 *
 
26
 * Larry Finger <Larry.Finger@lwfinger.net>
 
27
 *
 
28
 *****************************************************************************/
 
29
 
 
30
#include "../wifi.h"
 
31
#include "../efuse.h"
 
32
#include "../base.h"
 
33
#include "../regd.h"
 
34
#include "../cam.h"
 
35
#include "../ps.h"
 
36
#include "../pci.h"
 
37
#include "reg.h"
 
38
#include "def.h"
 
39
#include "phy.h"
 
40
#include "dm.h"
 
41
#include "fw.h"
 
42
#include "led.h"
 
43
#include "hw.h"
 
44
 
 
45
void rtl92se_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 
46
{
 
47
        struct rtl_priv *rtlpriv = rtl_priv(hw);
 
48
        struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 
49
        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 
50
 
 
51
        switch (variable) {
 
52
        case HW_VAR_RCR: {
 
53
                        *((u32 *) (val)) = rtlpci->receive_config;
 
54
                        break;
 
55
                }
 
56
        case HW_VAR_RF_STATE: {
 
57
                        *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
 
58
                        break;
 
59
                }
 
60
        case HW_VAR_FW_PSMODE_STATUS: {
 
61
                        *((bool *) (val)) = ppsc->fw_current_inpsmode;
 
62
                        break;
 
63
                }
 
64
        case HW_VAR_CORRECT_TSF: {
 
65
                        u64 tsf;
 
66
                        u32 *ptsf_low = (u32 *)&tsf;
 
67
                        u32 *ptsf_high = ((u32 *)&tsf) + 1;
 
68
 
 
69
                        *ptsf_high = rtl_read_dword(rtlpriv, (TSFR + 4));
 
70
                        *ptsf_low = rtl_read_dword(rtlpriv, TSFR);
 
71
 
 
72
                        *((u64 *) (val)) = tsf;
 
73
 
 
74
                        break;
 
75
                }
 
76
        case HW_VAR_MRC: {
 
77
                        *((bool *)(val)) = rtlpriv->dm.current_mrc_switch;
 
78
                        break;
 
79
                }
 
80
        default: {
 
81
                        RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 
82
                                 ("switch case not process\n"));
 
83
                        break;
 
84
                }
 
85
        }
 
86
}
 
87
 
 
88
void rtl92se_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 
89
{
 
90
        struct rtl_priv *rtlpriv = rtl_priv(hw);
 
91
        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 
92
        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 
93
        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 
94
        struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 
95
        struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 
96
 
 
97
        switch (variable) {
 
98
        case HW_VAR_ETHER_ADDR:{
 
99
                        rtl_write_dword(rtlpriv, IDR0, ((u32 *)(val))[0]);
 
100
                        rtl_write_word(rtlpriv, IDR4, ((u16 *)(val + 4))[0]);
 
101
                        break;
 
102
                }
 
103
        case HW_VAR_BASIC_RATE:{
 
104
                        u16 rate_cfg = ((u16 *) val)[0];
 
105
                        u8 rate_index = 0;
 
106
 
 
107
                        if (rtlhal->version == VERSION_8192S_ACUT)
 
108
                                rate_cfg = rate_cfg & 0x150;
 
109
                        else
 
110
                                rate_cfg = rate_cfg & 0x15f;
 
111
 
 
112
                        rate_cfg |= 0x01;
 
113
 
 
114
                        rtl_write_byte(rtlpriv, RRSR, rate_cfg & 0xff);
 
115
                        rtl_write_byte(rtlpriv, RRSR + 1,
 
116
                                       (rate_cfg >> 8) & 0xff);
 
117
 
 
118
                        while (rate_cfg > 0x1) {
 
119
                                rate_cfg = (rate_cfg >> 1);
 
120
                                rate_index++;
 
121
                        }
 
122
                        rtl_write_byte(rtlpriv, INIRTSMCS_SEL, rate_index);
 
123
 
 
124
                        break;
 
125
                }
 
126
        case HW_VAR_BSSID:{
 
127
                        rtl_write_dword(rtlpriv, BSSIDR, ((u32 *)(val))[0]);
 
128
                        rtl_write_word(rtlpriv, BSSIDR + 4,
 
129
                                       ((u16 *)(val + 4))[0]);
 
130
                        break;
 
131
                }
 
132
        case HW_VAR_SIFS:{
 
133
                        rtl_write_byte(rtlpriv, SIFS_OFDM, val[0]);
 
134
                        rtl_write_byte(rtlpriv, SIFS_OFDM + 1, val[1]);
 
135
                        break;
 
136
                }
 
137
        case HW_VAR_SLOT_TIME:{
 
138
                        u8 e_aci;
 
139
 
 
140
                        RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 
141
                                 ("HW_VAR_SLOT_TIME %x\n", val[0]));
 
142
 
 
143
                        rtl_write_byte(rtlpriv, SLOT_TIME, val[0]);
 
144
 
 
145
                        for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
 
146
                                rtlpriv->cfg->ops->set_hw_reg(hw,
 
147
                                                HW_VAR_AC_PARAM,
 
148
                                                (u8 *)(&e_aci));
 
149
                        }
 
150
                        break;
 
151
                }
 
152
        case HW_VAR_ACK_PREAMBLE:{
 
153
                        u8 reg_tmp;
 
154
                        u8 short_preamble = (bool) (*(u8 *) val);
 
155
                        reg_tmp = (mac->cur_40_prime_sc) << 5;
 
156
                        if (short_preamble)
 
157
                                reg_tmp |= 0x80;
 
158
 
 
159
                        rtl_write_byte(rtlpriv, RRSR + 2, reg_tmp);
 
160
                        break;
 
161
                }
 
162
        case HW_VAR_AMPDU_MIN_SPACE:{
 
163
                        u8 min_spacing_to_set;
 
164
                        u8 sec_min_space;
 
165
 
 
166
                        min_spacing_to_set = *((u8 *)val);
 
167
                        if (min_spacing_to_set <= 7) {
 
168
                                if (rtlpriv->sec.pairwise_enc_algorithm ==
 
169
                                    NO_ENCRYPTION)
 
170
                                        sec_min_space = 0;
 
171
                                else
 
172
                                        sec_min_space = 1;
 
173
 
 
174
                                if (min_spacing_to_set < sec_min_space)
 
175
                                        min_spacing_to_set = sec_min_space;
 
176
                                if (min_spacing_to_set > 5)
 
177
                                        min_spacing_to_set = 5;
 
178
 
 
179
                                mac->min_space_cfg =
 
180
                                                ((mac->min_space_cfg & 0xf8) |
 
181
                                                min_spacing_to_set);
 
182
 
 
183
                                *val = min_spacing_to_set;
 
184
 
 
185
                                RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 
186
                                         ("Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
 
187
                                          mac->min_space_cfg));
 
188
 
 
189
                                rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE,
 
190
                                               mac->min_space_cfg);
 
191
                        }
 
192
                        break;
 
193
                }
 
194
        case HW_VAR_SHORTGI_DENSITY:{
 
195
                        u8 density_to_set;
 
196
 
 
197
                        density_to_set = *((u8 *) val);
 
198
                        mac->min_space_cfg = rtlpriv->rtlhal.minspace_cfg;
 
199
                        mac->min_space_cfg |= (density_to_set << 3);
 
200
 
 
201
                        RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 
202
                                 ("Set HW_VAR_SHORTGI_DENSITY: %#x\n",
 
203
                                  mac->min_space_cfg));
 
204
 
 
205
                        rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE,
 
206
                                       mac->min_space_cfg);
 
207
 
 
208
                        break;
 
209
                }
 
210
        case HW_VAR_AMPDU_FACTOR:{
 
211
                        u8 factor_toset;
 
212
                        u8 regtoset;
 
213
                        u8 factorlevel[18] = {
 
214
                                2, 4, 4, 7, 7, 13, 13,
 
215
                                13, 2, 7, 7, 13, 13,
 
216
                                15, 15, 15, 15, 0};
 
217
                        u8 index = 0;
 
218
 
 
219
                        factor_toset = *((u8 *) val);
 
220
                        if (factor_toset <= 3) {
 
221
                                factor_toset = (1 << (factor_toset + 2));
 
222
                                if (factor_toset > 0xf)
 
223
                                        factor_toset = 0xf;
 
224
 
 
225
                                for (index = 0; index < 17; index++) {
 
226
                                        if (factorlevel[index] > factor_toset)
 
227
                                                factorlevel[index] =
 
228
                                                                 factor_toset;
 
229
                                }
 
230
 
 
231
                                for (index = 0; index < 8; index++) {
 
232
                                        regtoset = ((factorlevel[index * 2]) |
 
233
                                                    (factorlevel[index *
 
234
                                                    2 + 1] << 4));
 
235
                                        rtl_write_byte(rtlpriv,
 
236
                                                       AGGLEN_LMT_L + index,
 
237
                                                       regtoset);
 
238
                                }
 
239
 
 
240
                                regtoset = ((factorlevel[16]) |
 
241
                                            (factorlevel[17] << 4));
 
242
                                rtl_write_byte(rtlpriv, AGGLEN_LMT_H, regtoset);
 
243
 
 
244
                                RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 
245
                                         ("Set HW_VAR_AMPDU_FACTOR: %#x\n",
 
246
                                          factor_toset));
 
247
                        }
 
248
                        break;
 
249
                }
 
250
        case HW_VAR_AC_PARAM:{
 
251
                        u8 e_aci = *((u8 *) val);
 
252
                        rtl92s_dm_init_edca_turbo(hw);
 
253
 
 
254
                        if (rtlpci->acm_method != eAcmWay2_SW)
 
255
                                rtlpriv->cfg->ops->set_hw_reg(hw,
 
256
                                                 HW_VAR_ACM_CTRL,
 
257
                                                 (u8 *)(&e_aci));
 
258
                        break;
 
259
                }
 
260
        case HW_VAR_ACM_CTRL:{
 
261
                        u8 e_aci = *((u8 *) val);
 
262
                        union aci_aifsn *p_aci_aifsn = (union aci_aifsn *)(&(
 
263
                                                        mac->ac[0].aifs));
 
264
                        u8 acm = p_aci_aifsn->f.acm;
 
265
                        u8 acm_ctrl = rtl_read_byte(rtlpriv, AcmHwCtrl);
 
266
 
 
267
                        acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ?
 
268
                                   0x0 : 0x1);
 
269
 
 
270
                        if (acm) {
 
271
                                switch (e_aci) {
 
272
                                case AC0_BE:
 
273
                                        acm_ctrl |= AcmHw_BeqEn;
 
274
                                        break;
 
275
                                case AC2_VI:
 
276
                                        acm_ctrl |= AcmHw_ViqEn;
 
277
                                        break;
 
278
                                case AC3_VO:
 
279
                                        acm_ctrl |= AcmHw_VoqEn;
 
280
                                        break;
 
281
                                default:
 
282
                                        RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 
283
                                                 ("HW_VAR_ACM_CTRL acm set "
 
284
                                                  "failed: eACI is %d\n", acm));
 
285
                                        break;
 
286
                                }
 
287
                        } else {
 
288
                                switch (e_aci) {
 
289
                                case AC0_BE:
 
290
                                        acm_ctrl &= (~AcmHw_BeqEn);
 
291
                                        break;
 
292
                                case AC2_VI:
 
293
                                        acm_ctrl &= (~AcmHw_ViqEn);
 
294
                                        break;
 
295
                                case AC3_VO:
 
296
                                        acm_ctrl &= (~AcmHw_BeqEn);
 
297
                                        break;
 
298
                                default:
 
299
                                        RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 
300
                                                 ("switch case not process\n"));
 
301
                                        break;
 
302
                                }
 
303
                        }
 
304
 
 
305
                        RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
 
306
                                 ("HW_VAR_ACM_CTRL Write 0x%X\n", acm_ctrl));
 
307
                        rtl_write_byte(rtlpriv, AcmHwCtrl, acm_ctrl);
 
308
                        break;
 
309
                }
 
310
        case HW_VAR_RCR:{
 
311
                        rtl_write_dword(rtlpriv, RCR, ((u32 *) (val))[0]);
 
312
                        rtlpci->receive_config = ((u32 *) (val))[0];
 
313
                        break;
 
314
                }
 
315
        case HW_VAR_RETRY_LIMIT:{
 
316
                        u8 retry_limit = ((u8 *) (val))[0];
 
317
 
 
318
                        rtl_write_word(rtlpriv, RETRY_LIMIT,
 
319
                                       retry_limit << RETRY_LIMIT_SHORT_SHIFT |
 
320
                                       retry_limit << RETRY_LIMIT_LONG_SHIFT);
 
321
                        break;
 
322
                }
 
323
        case HW_VAR_DUAL_TSF_RST: {
 
324
                        break;
 
325
                }
 
326
        case HW_VAR_EFUSE_BYTES: {
 
327
                        rtlefuse->efuse_usedbytes = *((u16 *) val);
 
328
                        break;
 
329
                }
 
330
        case HW_VAR_EFUSE_USAGE: {
 
331
                        rtlefuse->efuse_usedpercentage = *((u8 *) val);
 
332
                        break;
 
333
                }
 
334
        case HW_VAR_IO_CMD: {
 
335
                        break;
 
336
                }
 
337
        case HW_VAR_WPA_CONFIG: {
 
338
                        rtl_write_byte(rtlpriv, REG_SECR, *((u8 *) val));
 
339
                        break;
 
340
                }
 
341
        case HW_VAR_SET_RPWM:{
 
342
                        break;
 
343
                }
 
344
        case HW_VAR_H2C_FW_PWRMODE:{
 
345
                        break;
 
346
                }
 
347
        case HW_VAR_FW_PSMODE_STATUS: {
 
348
                        ppsc->fw_current_inpsmode = *((bool *) val);
 
349
                        break;
 
350
                }
 
351
        case HW_VAR_H2C_FW_JOINBSSRPT:{
 
352
                        break;
 
353
                }
 
354
        case HW_VAR_AID:{
 
355
                        break;
 
356
                }
 
357
        case HW_VAR_CORRECT_TSF:{
 
358
                        break;
 
359
                }
 
360
        case HW_VAR_MRC: {
 
361
                        bool bmrc_toset = *((bool *)val);
 
362
                        u8 u1bdata = 0;
 
363
 
 
364
                        if (bmrc_toset) {
 
365
                                rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
 
366
                                              MASKBYTE0, 0x33);
 
367
                                u1bdata = (u8)rtl_get_bbreg(hw,
 
368
                                                ROFDM1_TRXPATHENABLE,
 
369
                                                MASKBYTE0);
 
370
                                rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE,
 
371
                                              MASKBYTE0,
 
372
                                              ((u1bdata & 0xf0) | 0x03));
 
373
                                u1bdata = (u8)rtl_get_bbreg(hw,
 
374
                                                ROFDM0_TRXPATHENABLE,
 
375
                                                MASKBYTE1);
 
376
                                rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
 
377
                                              MASKBYTE1,
 
378
                                              (u1bdata | 0x04));
 
379
 
 
380
                                /* Update current settings. */
 
381
                                rtlpriv->dm.current_mrc_switch = bmrc_toset;
 
382
                        } else {
 
383
                                rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
 
384
                                              MASKBYTE0, 0x13);
 
385
                                u1bdata = (u8)rtl_get_bbreg(hw,
 
386
                                                 ROFDM1_TRXPATHENABLE,
 
387
                                                 MASKBYTE0);
 
388
                                rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE,
 
389
                                              MASKBYTE0,
 
390
                                              ((u1bdata & 0xf0) | 0x01));
 
391
                                u1bdata = (u8)rtl_get_bbreg(hw,
 
392
                                                ROFDM0_TRXPATHENABLE,
 
393
                                                MASKBYTE1);
 
394
                                rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
 
395
                                              MASKBYTE1, (u1bdata & 0xfb));
 
396
 
 
397
                                /* Update current settings. */
 
398
                                rtlpriv->dm.current_mrc_switch = bmrc_toset;
 
399
                        }
 
400
 
 
401
                        break;
 
402
                }
 
403
        default:
 
404
                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 
405
                         ("switch case not process\n"));
 
406
                break;
 
407
        }
 
408
 
 
409
}
 
410
 
 
411
void rtl92se_enable_hw_security_config(struct ieee80211_hw *hw)
 
412
{
 
413
        struct rtl_priv *rtlpriv = rtl_priv(hw);
 
414
        u8 sec_reg_value = 0x0;
 
415
 
 
416
        RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("PairwiseEncAlgorithm = %d "
 
417
                 "GroupEncAlgorithm = %d\n",
 
418
                 rtlpriv->sec.pairwise_enc_algorithm,
 
419
                 rtlpriv->sec.group_enc_algorithm));
 
420
 
 
421
        if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
 
422
                RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
 
423
                         ("not open hw encryption\n"));
 
424
                return;
 
425
        }
 
426
 
 
427
        sec_reg_value = SCR_TXENCENABLE | SCR_RXENCENABLE;
 
428
 
 
429
        if (rtlpriv->sec.use_defaultkey) {
 
430
                sec_reg_value |= SCR_TXUSEDK;
 
431
                sec_reg_value |= SCR_RXUSEDK;
 
432
        }
 
433
 
 
434
        RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, ("The SECR-value %x\n",
 
435
                        sec_reg_value));
 
436
 
 
437
        rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
 
438
 
 
439
}
 
440
 
 
441
static u8 _rtl92ce_halset_sysclk(struct ieee80211_hw *hw, u8 data)
 
442
{
 
443
        struct rtl_priv *rtlpriv = rtl_priv(hw);
 
444
        u8 waitcount = 100;
 
445
        bool bresult = false;
 
446
        u8 tmpvalue;
 
447
 
 
448
        rtl_write_byte(rtlpriv, SYS_CLKR + 1, data);
 
449
 
 
450
        /* Wait the MAC synchronized. */
 
451
        udelay(400);
 
452
 
 
453
        /* Check if it is set ready. */
 
454
        tmpvalue = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
 
455
        bresult = ((tmpvalue & BIT(7)) == (data & BIT(7)));
 
456
 
 
457
        if ((data & (BIT(6) | BIT(7))) == false) {
 
458
                waitcount = 100;
 
459
                tmpvalue = 0;
 
460
 
 
461
                while (1) {
 
462
                        waitcount--;
 
463
 
 
464
                        tmpvalue = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
 
465
                        if ((tmpvalue & BIT(6)))
 
466
                                break;
 
467
 
 
468
                        printk(KERN_ERR "wait for BIT(6) return value %x\n",
 
469
                               tmpvalue);
 
470
                        if (waitcount == 0)
 
471
                                break;
 
472
 
 
473
                        udelay(10);
 
474
                }
 
475
 
 
476
                if (waitcount == 0)
 
477
                        bresult = false;
 
478
                else
 
479
                        bresult = true;
 
480
        }
 
481
 
 
482
        return bresult;
 
483
}
 
484
 
 
485
void rtl8192se_gpiobit3_cfg_inputmode(struct ieee80211_hw *hw)
 
486
{
 
487
        struct rtl_priv *rtlpriv = rtl_priv(hw);
 
488
        u8 u1tmp;
 
489
 
 
490
        /* The following config GPIO function */
 
491
        rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO));
 
492
        u1tmp = rtl_read_byte(rtlpriv, GPIO_IO_SEL);
 
493
 
 
494
        /* config GPIO3 to input */
 
495
        u1tmp &= HAL_8192S_HW_GPIO_OFF_MASK;
 
496
        rtl_write_byte(rtlpriv, GPIO_IO_SEL, u1tmp);
 
497
 
 
498
}
 
499
 
 
500
static u8 _rtl92se_rf_onoff_detect(struct ieee80211_hw *hw)
 
501
{
 
502
        struct rtl_priv *rtlpriv = rtl_priv(hw);
 
503
        u8 u1tmp;
 
504
        u8 retval = ERFON;
 
505
 
 
506
        /* The following config GPIO function */
 
507
        rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO));
 
508
        u1tmp = rtl_read_byte(rtlpriv, GPIO_IO_SEL);
 
509
 
 
510
        /* config GPIO3 to input */
 
511
        u1tmp &= HAL_8192S_HW_GPIO_OFF_MASK;
 
512
        rtl_write_byte(rtlpriv, GPIO_IO_SEL, u1tmp);
 
513
 
 
514
        /* On some of the platform, driver cannot read correct
 
515
         * value without delay between Write_GPIO_SEL and Read_GPIO_IN */
 
516
        mdelay(10);
 
517
 
 
518
        /* check GPIO3 */
 
519
        u1tmp = rtl_read_byte(rtlpriv, GPIO_IN);
 
520
        retval = (u1tmp & HAL_8192S_HW_GPIO_OFF_BIT) ? ERFON : ERFOFF;
 
521
 
 
522
        return retval;
 
523
}
 
524
 
 
525
static void _rtl92se_macconfig_before_fwdownload(struct ieee80211_hw *hw)
 
526
{
 
527
        struct rtl_priv *rtlpriv = rtl_priv(hw);
 
528
        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 
529
        struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 
530
 
 
531
        u8 i;
 
532
        u8 tmpu1b;
 
533
        u16 tmpu2b;
 
534
        u8 pollingcnt = 20;
 
535
 
 
536
        if (rtlpci->first_init) {
 
537
                /* Reset PCIE Digital */
 
538
                tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
 
539
                tmpu1b &= 0xFE;
 
540
                rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
 
541
                udelay(1);
 
542
                rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b | BIT(0));
 
543
        }
 
544
 
 
545
        /* Switch to SW IO control */
 
546
        tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
 
547
        if (tmpu1b & BIT(7)) {
 
548
                tmpu1b &= ~(BIT(6) | BIT(7));
 
549
 
 
550
                /* Set failed, return to prevent hang. */
 
551
                if (!_rtl92ce_halset_sysclk(hw, tmpu1b))
 
552
                        return;
 
553
        }
 
554
 
 
555
        rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x0);
 
556
        udelay(50);
 
557
        rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
 
558
        udelay(50);
 
559
 
 
560
        /* Clear FW RPWM for FW control LPS.*/
 
561
        rtl_write_byte(rtlpriv, RPWM, 0x0);
 
562
 
 
563
        /* Reset MAC-IO and CPU and Core Digital BIT(10)/11/15 */
 
564
        tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
 
565
        tmpu1b &= 0x73;
 
566
        rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
 
567
        /* wait for BIT 10/11/15 to pull high automatically!! */
 
568
        mdelay(1);
 
569
 
 
570
        rtl_write_byte(rtlpriv, CMDR, 0);
 
571
        rtl_write_byte(rtlpriv, TCR, 0);
 
572
 
 
573
        /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */
 
574
        tmpu1b = rtl_read_byte(rtlpriv, 0x562);
 
575
        tmpu1b |= 0x08;
 
576
        rtl_write_byte(rtlpriv, 0x562, tmpu1b);
 
577
        tmpu1b &= ~(BIT(3));
 
578
        rtl_write_byte(rtlpriv, 0x562, tmpu1b);
 
579
 
 
580
        /* Enable AFE clock source */
 
581
        tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL);
 
582
        rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, (tmpu1b | 0x01));
 
583
        /* Delay 1.5ms */
 
584
        mdelay(2);
 
585
        tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL + 1);
 
586
        rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, (tmpu1b & 0xfb));
 
587
 
 
588
        /* Enable AFE Macro Block's Bandgap */
 
589
        tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
 
590
        rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0)));
 
591
        mdelay(1);
 
592
 
 
593
        /* Enable AFE Mbias */
 
594
        tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
 
595
        rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | 0x02));
 
596
        mdelay(1);
 
597
 
 
598
        /* Enable LDOA15 block  */
 
599
        tmpu1b = rtl_read_byte(rtlpriv, LDOA15_CTRL);
 
600
        rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0)));
 
601
 
 
602
        /* Set Digital Vdd to Retention isolation Path. */
 
603
        tmpu2b = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
 
604
        rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, (tmpu2b | BIT(11)));
 
605
 
 
606
        /* For warm reboot NIC disappera bug. */
 
607
        tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
 
608
        rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(13)));
 
609
 
 
610
        rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x68);
 
611
 
 
612
        /* Enable AFE PLL Macro Block */
 
613
        /* We need to delay 100u before enabling PLL. */
 
614
        udelay(200);
 
615
        tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL);
 
616
        rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
 
617
 
 
618
        /* for divider reset  */
 
619
        udelay(100);
 
620
        rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) |
 
621
                       BIT(4) | BIT(6)));
 
622
        udelay(10);
 
623
        rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
 
624
        udelay(10);
 
625
 
 
626
        /* Enable MAC 80MHZ clock  */
 
627
        tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL + 1);
 
628
        rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0)));
 
629
        mdelay(1);
 
630
 
 
631
        /* Release isolation AFE PLL & MD */
 
632
        rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xA6);
 
633
 
 
634
        /* Enable MAC clock */
 
635
        tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
 
636
        rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11)));
 
637
 
 
638
        /* Enable Core digital and enable IOREG R/W */
 
639
        tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
 
640
        rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11)));
 
641
 
 
642
        tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
 
643
        rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b & ~(BIT(7)));
 
644
 
 
645
        /* enable REG_EN */
 
646
        rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15)));
 
647
 
 
648
        /* Switch the control path. */
 
649
        tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
 
650
        rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b & (~BIT(2))));
 
651
 
 
652
        tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
 
653
        tmpu1b = ((tmpu1b | BIT(7)) & (~BIT(6)));
 
654
        if (!_rtl92ce_halset_sysclk(hw, tmpu1b))
 
655
                return; /* Set failed, return to prevent hang. */
 
656
 
 
657
        rtl_write_word(rtlpriv, CMDR, 0x07FC);
 
658
 
 
659
        /* MH We must enable the section of code to prevent load IMEM fail. */
 
660
        /* Load MAC register from WMAc temporarily We simulate macreg. */
 
661
        /* txt HW will provide MAC txt later  */
 
662
        rtl_write_byte(rtlpriv, 0x6, 0x30);
 
663
        rtl_write_byte(rtlpriv, 0x49, 0xf0);
 
664
 
 
665
        rtl_write_byte(rtlpriv, 0x4b, 0x81);
 
666
 
 
667
        rtl_write_byte(rtlpriv, 0xb5, 0x21);
 
668
 
 
669
        rtl_write_byte(rtlpriv, 0xdc, 0xff);
 
670
        rtl_write_byte(rtlpriv, 0xdd, 0xff);
 
671
        rtl_write_byte(rtlpriv, 0xde, 0xff);
 
672
        rtl_write_byte(rtlpriv, 0xdf, 0xff);
 
673
 
 
674
        rtl_write_byte(rtlpriv, 0x11a, 0x00);
 
675
        rtl_write_byte(rtlpriv, 0x11b, 0x00);
 
676
 
 
677
        for (i = 0; i < 32; i++)
 
678
                rtl_write_byte(rtlpriv, INIMCS_SEL + i, 0x1b);
 
679
 
 
680
        rtl_write_byte(rtlpriv, 0x236, 0xff);
 
681
 
 
682
        rtl_write_byte(rtlpriv, 0x503, 0x22);
 
683
 
 
684
        if (ppsc->support_aspm && !ppsc->support_backdoor)
 
685
                rtl_write_byte(rtlpriv, 0x560, 0x40);
 
686
        else
 
687
                rtl_write_byte(rtlpriv, 0x560, 0x00);
 
688
 
 
689
        rtl_write_byte(rtlpriv, DBG_PORT, 0x91);
 
690
 
 
691
        /* Set RX Desc Address */
 
692
        rtl_write_dword(rtlpriv, RDQDA, rtlpci->rx_ring[RX_MPDU_QUEUE].dma);
 
693
        rtl_write_dword(rtlpriv, RCDA, rtlpci->rx_ring[RX_CMD_QUEUE].dma);
 
694
 
 
695
        /* Set TX Desc Address */
 
696
        rtl_write_dword(rtlpriv, TBKDA, rtlpci->tx_ring[BK_QUEUE].dma);
 
697
        rtl_write_dword(rtlpriv, TBEDA, rtlpci->tx_ring[BE_QUEUE].dma);
 
698
        rtl_write_dword(rtlpriv, TVIDA, rtlpci->tx_ring[VI_QUEUE].dma);
 
699
        rtl_write_dword(rtlpriv, TVODA, rtlpci->tx_ring[VO_QUEUE].dma);
 
700
        rtl_write_dword(rtlpriv, TBDA, rtlpci->tx_ring[BEACON_QUEUE].dma);
 
701
        rtl_write_dword(rtlpriv, TCDA, rtlpci->tx_ring[TXCMD_QUEUE].dma);
 
702
        rtl_write_dword(rtlpriv, TMDA, rtlpci->tx_ring[MGNT_QUEUE].dma);
 
703
        rtl_write_dword(rtlpriv, THPDA, rtlpci->tx_ring[HIGH_QUEUE].dma);
 
704
        rtl_write_dword(rtlpriv, HDA, rtlpci->tx_ring[HCCA_QUEUE].dma);
 
705
 
 
706
        rtl_write_word(rtlpriv, CMDR, 0x37FC);
 
707
 
 
708
        /* To make sure that TxDMA can ready to download FW. */
 
709
        /* We should reset TxDMA if IMEM RPT was not ready. */
 
710
        do {
 
711
                tmpu1b = rtl_read_byte(rtlpriv, TCR);
 
712
                if ((tmpu1b & TXDMA_INIT_VALUE) == TXDMA_INIT_VALUE)
 
713
                        break;
 
714
 
 
715
                udelay(5);
 
716
        } while (pollingcnt--);
 
717
 
 
718
        if (pollingcnt <= 0) {
 
719
                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 
720
                         ("Polling TXDMA_INIT_VALUE "
 
721
                         "timeout!! Current TCR(%#x)\n", tmpu1b));
 
722
                tmpu1b = rtl_read_byte(rtlpriv, CMDR);
 
723
                rtl_write_byte(rtlpriv, CMDR, tmpu1b & (~TXDMA_EN));
 
724
                udelay(2);
 
725
                /* Reset TxDMA */
 
726
                rtl_write_byte(rtlpriv, CMDR, tmpu1b | TXDMA_EN);
 
727
        }
 
728
 
 
729
        /* After MACIO reset,we must refresh LED state. */
 
730
        if ((ppsc->rfoff_reason == RF_CHANGE_BY_IPS) ||
 
731
           (ppsc->rfoff_reason == 0)) {
 
732
                struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 
733
                struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
 
734
                enum rf_pwrstate rfpwr_state_toset;
 
735
                rfpwr_state_toset = _rtl92se_rf_onoff_detect(hw);
 
736
 
 
737
                if (rfpwr_state_toset == ERFON)
 
738
                        rtl92se_sw_led_on(hw, pLed0);
 
739
        }
 
740
}
 
741
 
 
742
static void _rtl92se_macconfig_after_fwdownload(struct ieee80211_hw *hw)
 
743
{
 
744
        struct rtl_priv *rtlpriv = rtl_priv(hw);
 
745
        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 
746
        struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 
747
        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 
748
        u8 i;
 
749
        u16 tmpu2b;
 
750
 
 
751
        /* 1. System Configure Register (Offset: 0x0000 - 0x003F) */
 
752
 
 
753
        /* 2. Command Control Register (Offset: 0x0040 - 0x004F) */
 
754
        /* Turn on 0x40 Command register */
 
755
        rtl_write_word(rtlpriv, CMDR, (BBRSTN | BB_GLB_RSTN |
 
756
                        SCHEDULE_EN | MACRXEN | MACTXEN | DDMA_EN | FW2HW_EN |
 
757
                        RXDMA_EN | TXDMA_EN | HCI_RXDMA_EN | HCI_TXDMA_EN));
 
758
 
 
759
        /* Set TCR TX DMA pre 2 FULL enable bit */
 
760
        rtl_write_dword(rtlpriv, TCR, rtl_read_dword(rtlpriv, TCR) |
 
761
                        TXDMAPRE2FULL);
 
762
 
 
763
        /* Set RCR      */
 
764
        rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config);
 
765
 
 
766
        /* 3. MACID Setting Register (Offset: 0x0050 - 0x007F) */
 
767
 
 
768
        /* 4. Timing Control Register  (Offset: 0x0080 - 0x009F) */
 
769
        /* Set CCK/OFDM SIFS */
 
770
        /* CCK SIFS shall always be 10us. */
 
771
        rtl_write_word(rtlpriv, SIFS_CCK, 0x0a0a);
 
772
        rtl_write_word(rtlpriv, SIFS_OFDM, 0x1010);
 
773
 
 
774
        /* Set AckTimeout */
 
775
        rtl_write_byte(rtlpriv, ACK_TIMEOUT, 0x40);
 
776
 
 
777
        /* Beacon related */
 
778
        rtl_write_word(rtlpriv, BCN_INTERVAL, 100);
 
779
        rtl_write_word(rtlpriv, ATIMWND, 2);
 
780
 
 
781
        /* 5. FIFO Control Register (Offset: 0x00A0 - 0x015F) */
 
782
        /* 5.1 Initialize Number of Reserved Pages in Firmware Queue */
 
783
        /* Firmware allocate now, associate with FW internal setting.!!! */
 
784
 
 
785
        /* 5.2 Setting TX/RX page size 0/1/2/3/4=64/128/256/512/1024 */
 
786
        /* 5.3 Set driver info, we only accept PHY status now. */
 
787
        /* 5.4 Set RXDMA arbitration to control RXDMA/MAC/FW R/W for RXFIFO  */
 
788
        rtl_write_byte(rtlpriv, RXDMA, rtl_read_byte(rtlpriv, RXDMA) | BIT(6));
 
789
 
 
790
        /* 6. Adaptive Control Register  (Offset: 0x0160 - 0x01CF) */
 
791
        /* Set RRSR to all legacy rate and HT rate
 
792
         * CCK rate is supported by default.
 
793
         * CCK rate will be filtered out only when associated
 
794
         * AP does not support it.
 
795
         * Only enable ACK rate to OFDM 24M
 
796
         * Disable RRSR for CCK rate in A-Cut   */
 
797
 
 
798
        if (rtlhal->version == VERSION_8192S_ACUT)
 
799
                rtl_write_byte(rtlpriv, RRSR, 0xf0);
 
800
        else if (rtlhal->version == VERSION_8192S_BCUT)
 
801
                rtl_write_byte(rtlpriv, RRSR, 0xff);
 
802
        rtl_write_byte(rtlpriv, RRSR + 1, 0x01);
 
803
        rtl_write_byte(rtlpriv, RRSR + 2, 0x00);
 
804
 
 
805
        /* A-Cut IC do not support CCK rate. We forbid ARFR to */
 
806
        /* fallback to CCK rate */
 
807
        for (i = 0; i < 8; i++) {
 
808
                /*Disable RRSR for CCK rate in A-Cut */
 
809
                if (rtlhal->version == VERSION_8192S_ACUT)
 
810
                        rtl_write_dword(rtlpriv, ARFR0 + i * 4, 0x1f0ff0f0);
 
811
        }
 
812
 
 
813
        /* Different rate use different AMPDU size */
 
814
        /* MCS32/ MCS15_SG use max AMPDU size 15*2=30K */
 
815
        rtl_write_byte(rtlpriv, AGGLEN_LMT_H, 0x0f);
 
816
        /* MCS0/1/2/3 use max AMPDU size 4*2=8K */
 
817
        rtl_write_word(rtlpriv, AGGLEN_LMT_L, 0x7442);
 
818
        /* MCS4/5 use max AMPDU size 8*2=16K 6/7 use 10*2=20K */
 
819
        rtl_write_word(rtlpriv, AGGLEN_LMT_L + 2, 0xddd7);
 
820
        /* MCS8/9 use max AMPDU size 8*2=16K 10/11 use 10*2=20K */
 
821
        rtl_write_word(rtlpriv, AGGLEN_LMT_L + 4, 0xd772);
 
822
        /* MCS12/13/14/15 use max AMPDU size 15*2=30K */
 
823
        rtl_write_word(rtlpriv, AGGLEN_LMT_L + 6, 0xfffd);
 
824
 
 
825
        /* Set Data / Response auto rate fallack retry count */
 
826
        rtl_write_dword(rtlpriv, DARFRC, 0x04010000);
 
827
        rtl_write_dword(rtlpriv, DARFRC + 4, 0x09070605);
 
828
        rtl_write_dword(rtlpriv, RARFRC, 0x04010000);
 
829
        rtl_write_dword(rtlpriv, RARFRC + 4, 0x09070605);
 
830
 
 
831
        /* 7. EDCA Setting Register (Offset: 0x01D0 - 0x01FF) */
 
832
        /* Set all rate to support SG */
 
833
        rtl_write_word(rtlpriv, SG_RATE, 0xFFFF);
 
834
 
 
835
        /* 8. WMAC, BA, and CCX related Register (Offset: 0x0200 - 0x023F) */
 
836
        /* Set NAV protection length */
 
837
        rtl_write_word(rtlpriv, NAV_PROT_LEN, 0x0080);
 
838
        /* CF-END Threshold */
 
839
        rtl_write_byte(rtlpriv, CFEND_TH, 0xFF);
 
840
        /* Set AMPDU minimum space */
 
841
        rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, 0x07);
 
842
        /* Set TXOP stall control for several queue/HI/BCN/MGT/ */
 
843
        rtl_write_byte(rtlpriv, TXOP_STALL_CTRL, 0x00);
 
844
 
 
845
        /* 9. Security Control Register (Offset: 0x0240 - 0x025F) */
 
846
        /* 10. Power Save Control Register (Offset: 0x0260 - 0x02DF) */
 
847
        /* 11. General Purpose Register (Offset: 0x02E0 - 0x02FF) */
 
848
        /* 12. Host Interrupt Status Register (Offset: 0x0300 - 0x030F) */
 
849
        /* 13. Test Mode and Debug Control Register (Offset: 0x0310 - 0x034F) */
 
850
 
 
851
        /* 14. Set driver info, we only accept PHY status now. */
 
852
        rtl_write_byte(rtlpriv, RXDRVINFO_SZ, 4);
 
853
 
 
854
        /* 15. For EEPROM R/W Workaround */
 
855
        /* 16. For EFUSE to share REG_SYS_FUNC_EN with EEPROM!!! */
 
856
        tmpu2b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
 
857
        rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, tmpu2b | BIT(13));
 
858
        tmpu2b = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL);
 
859
        rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, tmpu2b & (~BIT(8)));
 
860
 
 
861
        /* 17. For EFUSE */
 
862
        /* We may R/W EFUSE in EEPROM mode */
 
863
        if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
 
864
                u8      tempval;
 
865
 
 
866
                tempval = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL + 1);
 
867
                tempval &= 0xFE;
 
868
                rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, tempval);
 
869
 
 
870
                /* Change Program timing */
 
871
                rtl_write_byte(rtlpriv, REG_EFUSE_CTRL + 3, 0x72);
 
872
                RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("EFUSE CONFIG OK\n"));
 
873
        }
 
874
 
 
875
        RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("OK\n"));
 
876
 
 
877
}
 
878
 
 
879
static void _rtl92se_hw_configure(struct ieee80211_hw *hw)
 
880
{
 
881
        struct rtl_priv *rtlpriv = rtl_priv(hw);
 
882
        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 
883
        struct rtl_phy *rtlphy = &(rtlpriv->phy);
 
884
        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 
885
 
 
886
        u8 reg_bw_opmode = 0;
 
887
        u32 reg_ratr = 0, reg_rrsr = 0;
 
888
        u8 regtmp = 0;
 
889
 
 
890
        reg_bw_opmode = BW_OPMODE_20MHZ;
 
891
        reg_ratr = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS |
 
892
                                RATE_ALL_OFDM_2SS;
 
893
        reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 
894
 
 
895
        regtmp = rtl_read_byte(rtlpriv, INIRTSMCS_SEL);
 
896
        reg_rrsr = ((reg_rrsr & 0x000fffff) << 8) | regtmp;
 
897
        rtl_write_dword(rtlpriv, INIRTSMCS_SEL, reg_rrsr);
 
898
        rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode);
 
899
 
 
900
        /* Set Retry Limit here */
 
901
        rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT,
 
902
                        (u8 *)(&rtlpci->shortretry_limit));
 
903
 
 
904
        rtl_write_byte(rtlpriv, MLT, 0x8f);
 
905
 
 
906
        /* For Min Spacing configuration. */
 
907
        switch (rtlphy->rf_type) {
 
908
        case RF_1T2R:
 
909
        case RF_1T1R:
 
910
                rtlhal->minspace_cfg = (MAX_MSS_DENSITY_1T << 3);
 
911
                break;
 
912
        case RF_2T2R:
 
913
        case RF_2T2R_GREEN:
 
914
                rtlhal->minspace_cfg = (MAX_MSS_DENSITY_2T << 3);
 
915
                break;
 
916
        }
 
917
        rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, rtlhal->minspace_cfg);
 
918
}
 
919
 
 
920
int rtl92se_hw_init(struct ieee80211_hw *hw)
 
921
{
 
922
        struct rtl_priv *rtlpriv = rtl_priv(hw);
 
923
        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 
924
        struct rtl_phy *rtlphy = &(rtlpriv->phy);
 
925
        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 
926
        struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 
927
        u8 tmp_byte = 0;
 
928
 
 
929
        bool rtstatus = true;
 
930
        u8 tmp_u1b;
 
931
        int err = false;
 
932
        u8 i;
 
933
        int wdcapra_add[] = {
 
934
                EDCAPARA_BE, EDCAPARA_BK,
 
935
                EDCAPARA_VI, EDCAPARA_VO};
 
936
        u8 secr_value = 0x0;
 
937
 
 
938
        rtlpci->being_init_adapter = true;
 
939
 
 
940
        rtlpriv->intf_ops->disable_aspm(hw);
 
941
 
 
942
        /* 1. MAC Initialize */
 
943
        /* Before FW download, we have to set some MAC register */
 
944
        _rtl92se_macconfig_before_fwdownload(hw);
 
945
 
 
946
        rtlhal->version = (enum version_8192s)((rtl_read_dword(rtlpriv,
 
947
                        PMC_FSM) >> 16) & 0xF);
 
948
 
 
949
        rtl8192se_gpiobit3_cfg_inputmode(hw);
 
950
 
 
951
        /* 2. download firmware */
 
952
        rtstatus = rtl92s_download_fw(hw);
 
953
        if (!rtstatus) {
 
954
                RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 
955
                         ("Failed to download FW. "
 
956
                         "Init HW without FW now.., Please copy FW into"
 
957
                         "/lib/firmware/rtlwifi\n"));
 
958
                rtlhal->fw_ready = false;
 
959
        } else {
 
960
                rtlhal->fw_ready = true;
 
961
        }
 
962
 
 
963
        /* After FW download, we have to reset MAC register */
 
964
        _rtl92se_macconfig_after_fwdownload(hw);
 
965
 
 
966
        /*Retrieve default FW Cmd IO map. */
 
967
        rtlhal->fwcmd_iomap =   rtl_read_word(rtlpriv, LBUS_MON_ADDR);
 
968
        rtlhal->fwcmd_ioparam = rtl_read_dword(rtlpriv, LBUS_ADDR_MASK);
 
969
 
 
970
        /* 3. Initialize MAC/PHY Config by MACPHY_reg.txt */
 
971
        if (rtl92s_phy_mac_config(hw) != true) {
 
972
                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("MAC Config failed\n"));
 
973
                return rtstatus;
 
974
        }
 
975
 
 
976
        /* Make sure BB/RF write OK. We should prevent enter IPS. radio off. */
 
977
        /* We must set flag avoid BB/RF config period later!! */
 
978
        rtl_write_dword(rtlpriv, CMDR, 0x37FC);
 
979
 
 
980
        /* 4. Initialize BB After MAC Config PHY_reg.txt, AGC_Tab.txt */
 
981
        if (rtl92s_phy_bb_config(hw) != true) {
 
982
                RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, ("BB Config failed\n"));
 
983
                return rtstatus;
 
984
        }
 
985
 
 
986
        /* 5. Initiailze RF RAIO_A.txt RF RAIO_B.txt */
 
987
        /* Before initalizing RF. We can not use FW to do RF-R/W. */
 
988
 
 
989
        rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
 
990
 
 
991
        /* RF Power Save */
 
992
#if 0
 
993
        /* H/W or S/W RF OFF before sleep. */
 
994
        if (rtlpriv->psc.rfoff_reason > RF_CHANGE_BY_PS) {
 
995
                u32 rfoffreason = rtlpriv->psc.rfoff_reason;
 
996
 
 
997
                rtlpriv->psc.rfoff_reason = RF_CHANGE_BY_INIT;
 
998
                rtlpriv->psc.rfpwr_state = ERFON;
 
999
                rtl_ps_set_rf_state(hw, ERFOFF, rfoffreason, true);
 
1000
        } else {
 
1001
                /* gpio radio on/off is out of adapter start */
 
1002
                if (rtlpriv->psc.hwradiooff == false) {
 
1003
                        rtlpriv->psc.rfpwr_state = ERFON;
 
1004
                        rtlpriv->psc.rfoff_reason = 0;
 
1005
                }
 
1006
        }
 
1007
#endif
 
1008
 
 
1009
        /* Before RF-R/W we must execute the IO from Scott's suggestion. */
 
1010
        rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, 0xDB);
 
1011
        if (rtlhal->version == VERSION_8192S_ACUT)
 
1012
                rtl_write_byte(rtlpriv, SPS1_CTRL + 3, 0x07);
 
1013
        else
 
1014
                rtl_write_byte(rtlpriv, RF_CTRL, 0x07);
 
1015
 
 
1016
        if (rtl92s_phy_rf_config(hw) != true) {
 
1017
                RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("RF Config failed\n"));
 
1018
                return rtstatus;
 
1019
        }
 
1020
 
 
1021
        /* After read predefined TXT, we must set BB/MAC/RF
 
1022
         * register as our requirement */
 
1023
 
 
1024
        rtlphy->rfreg_chnlval[0] = rtl92s_phy_query_rf_reg(hw,
 
1025
                                                           (enum radio_path)0,
 
1026
                                                           RF_CHNLBW,
 
1027
                                                           RFREG_OFFSET_MASK);
 
1028
        rtlphy->rfreg_chnlval[1] = rtl92s_phy_query_rf_reg(hw,
 
1029
                                                           (enum radio_path)1,
 
1030
                                                           RF_CHNLBW,
 
1031
                                                           RFREG_OFFSET_MASK);
 
1032
 
 
1033
        /*---- Set CCK and OFDM Block "ON"----*/
 
1034
        rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
 
1035
        rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
 
1036
 
 
1037
        /*3 Set Hardware(Do nothing now) */
 
1038
        _rtl92se_hw_configure(hw);
 
1039
 
 
1040
        /* Read EEPROM TX power index and PHY_REG_PG.txt to capture correct */
 
1041
        /* TX power index for different rate set. */
 
1042
        /* Get original hw reg values */
 
1043
        rtl92s_phy_get_hw_reg_originalvalue(hw);
 
1044
        /* Write correct tx power index */
 
1045
        rtl92s_phy_set_txpower(hw, rtlphy->current_channel);
 
1046
 
 
1047
        /* We must set MAC address after firmware download. */
 
1048
        for (i = 0; i < 6; i++)
 
1049
                rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]);
 
1050
 
 
1051
        /* EEPROM R/W workaround */
 
1052
        tmp_u1b = rtl_read_byte(rtlpriv, MAC_PINMUX_CFG);
 
1053
        rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, tmp_u1b & (~BIT(3)));
 
1054
 
 
1055
        rtl_write_byte(rtlpriv, 0x4d, 0x0);
 
1056
 
 
1057
        if (hal_get_firmwareversion(rtlpriv) >= 0x49) {
 
1058
                tmp_byte = rtl_read_byte(rtlpriv, FW_RSVD_PG_CRTL) & (~BIT(4));
 
1059
                tmp_byte = tmp_byte | BIT(5);
 
1060
                rtl_write_byte(rtlpriv, FW_RSVD_PG_CRTL, tmp_byte);
 
1061
                rtl_write_dword(rtlpriv, TXDESC_MSK, 0xFFFFCFFF);
 
1062
        }
 
1063
 
 
1064
        /* We enable high power and RA related mechanism after NIC
 
1065
         * initialized. */
 
1066
        rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_INIT);
 
1067
 
 
1068
        /* Add to prevent ASPM bug. */
 
1069
        /* Always enable hst and NIC clock request. */
 
1070
        rtl92s_phy_switch_ephy_parameter(hw);
 
1071
 
 
1072
        /* Security related
 
1073
         * 1. Clear all H/W keys.
 
1074
         * 2. Enable H/W encryption/decryption. */
 
1075
        rtl_cam_reset_all_entry(hw);
 
1076
        secr_value |= SCR_TXENCENABLE;
 
1077
        secr_value |= SCR_RXENCENABLE;
 
1078
        secr_value |= SCR_NOSKMC;
 
1079
        rtl_write_byte(rtlpriv, REG_SECR, secr_value);
 
1080
 
 
1081
        for (i = 0; i < 4; i++)
 
1082
                rtl_write_dword(rtlpriv, wdcapra_add[i], 0x5e4322);
 
1083
 
 
1084
        if (rtlphy->rf_type == RF_1T2R) {
 
1085
                bool mrc2set = true;
 
1086
                /* Turn on B-Path */
 
1087
                rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_MRC, (u8 *)&mrc2set);
 
1088
        }
 
1089
 
 
1090
        rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_ON);
 
1091
        rtl92s_dm_init(hw);
 
1092
        rtlpci->being_init_adapter = false;
 
1093
 
 
1094
        return err;
 
1095
}
 
1096
 
 
1097
void rtl92se_set_mac_addr(struct rtl_io *io, const u8 * addr)
 
1098
{
 
1099
}
 
1100
 
 
1101
void rtl92se_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
 
1102
{
 
1103
        struct rtl_priv *rtlpriv = rtl_priv(hw);
 
1104
        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 
1105
        u32 reg_rcr = rtlpci->receive_config;
 
1106
 
 
1107
        if (rtlpriv->psc.rfpwr_state != ERFON)
 
1108
                return;
 
1109
 
 
1110
        if (check_bssid == true) {
 
1111
                reg_rcr |= (RCR_CBSSID);
 
1112
                rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
 
1113
        } else if (check_bssid == false) {
 
1114
                reg_rcr &= (~RCR_CBSSID);
 
1115
                rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
 
1116
        }
 
1117
 
 
1118
}
 
1119
 
 
1120
static int _rtl92se_set_media_status(struct ieee80211_hw *hw,
 
1121
                                     enum nl80211_iftype type)
 
1122
{
 
1123
        struct rtl_priv *rtlpriv = rtl_priv(hw);
 
1124
        u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
 
1125
        enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
 
1126
        u32 temp;
 
1127
        bt_msr &= ~MSR_LINK_MASK;
 
1128
 
 
1129
        switch (type) {
 
1130
        case NL80211_IFTYPE_UNSPECIFIED:
 
1131
                bt_msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
 
1132
                ledaction = LED_CTL_LINK;
 
1133
                RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 
1134
                         ("Set Network type to NO LINK!\n"));
 
1135
                break;
 
1136
        case NL80211_IFTYPE_ADHOC:
 
1137
                bt_msr |= (MSR_LINK_ADHOC << MSR_LINK_SHIFT);
 
1138
                RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 
1139
                         ("Set Network type to Ad Hoc!\n"));
 
1140
                break;
 
1141
        case NL80211_IFTYPE_STATION:
 
1142
                bt_msr |= (MSR_LINK_MANAGED << MSR_LINK_SHIFT);
 
1143
                ledaction = LED_CTL_LINK;
 
1144
                RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 
1145
                         ("Set Network type to STA!\n"));
 
1146
                break;
 
1147
        case NL80211_IFTYPE_AP:
 
1148
                bt_msr |= (MSR_LINK_MASTER << MSR_LINK_SHIFT);
 
1149
                RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 
1150
                         ("Set Network type to AP!\n"));
 
1151
                break;
 
1152
        default:
 
1153
                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 
1154
                         ("Network type %d not support!\n", type));
 
1155
                return 1;
 
1156
                break;
 
1157
 
 
1158
        }
 
1159
 
 
1160
        rtl_write_byte(rtlpriv, (MSR), bt_msr);
 
1161
 
 
1162
        temp = rtl_read_dword(rtlpriv, TCR);
 
1163
        rtl_write_dword(rtlpriv, TCR, temp & (~BIT(8)));
 
1164
        rtl_write_dword(rtlpriv, TCR, temp | BIT(8));
 
1165
 
 
1166
 
 
1167
        return 0;
 
1168
}
 
1169
 
 
1170
/* HW_VAR_MEDIA_STATUS & HW_VAR_CECHK_BSSID */
 
1171
int rtl92se_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
 
1172
{
 
1173
        struct rtl_priv *rtlpriv = rtl_priv(hw);
 
1174
 
 
1175
        if (_rtl92se_set_media_status(hw, type))
 
1176
                return -EOPNOTSUPP;
 
1177
 
 
1178
        if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
 
1179
                if (type != NL80211_IFTYPE_AP)
 
1180
                        rtl92se_set_check_bssid(hw, true);
 
1181
        } else {
 
1182
                rtl92se_set_check_bssid(hw, false);
 
1183
        }
 
1184
 
 
1185
        return 0;
 
1186
}
 
1187
 
 
1188
/* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
 
1189
void rtl92se_set_qos(struct ieee80211_hw *hw, int aci)
 
1190
{
 
1191
        struct rtl_priv *rtlpriv = rtl_priv(hw);
 
1192
        rtl92s_dm_init_edca_turbo(hw);
 
1193
 
 
1194
        switch (aci) {
 
1195
        case AC1_BK:
 
1196
                rtl_write_dword(rtlpriv, EDCAPARA_BK, 0xa44f);
 
1197
                break;
 
1198
        case AC0_BE:
 
1199
                /* rtl_write_dword(rtlpriv, EDCAPARA_BE, u4b_ac_param); */
 
1200
                break;
 
1201
        case AC2_VI:
 
1202
                rtl_write_dword(rtlpriv, EDCAPARA_VI, 0x5e4322);
 
1203
                break;
 
1204
        case AC3_VO:
 
1205
                rtl_write_dword(rtlpriv, EDCAPARA_VO, 0x2f3222);
 
1206
                break;
 
1207
        default:
 
1208
                RT_ASSERT(false, ("invalid aci: %d !\n", aci));
 
1209
                break;
 
1210
        }
 
1211
}
 
1212
 
 
1213
void rtl92se_enable_interrupt(struct ieee80211_hw *hw)
 
1214
{
 
1215
        struct rtl_priv *rtlpriv = rtl_priv(hw);
 
1216
        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 
1217
 
 
1218
        rtl_write_dword(rtlpriv, INTA_MASK, rtlpci->irq_mask[0]);
 
1219
        /* Support Bit 32-37(Assign as Bit 0-5) interrupt setting now */
 
1220
        rtl_write_dword(rtlpriv, INTA_MASK + 4, rtlpci->irq_mask[1] & 0x3F);
 
1221
 
 
1222
        rtlpci->irq_enabled = true;
 
1223
}
 
1224
 
 
1225
void rtl92se_disable_interrupt(struct ieee80211_hw *hw)
 
1226
{
 
1227
        struct rtl_priv *rtlpriv = rtl_priv(hw);
 
1228
        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 
1229
 
 
1230
        rtl_write_dword(rtlpriv, INTA_MASK, 0);
 
1231
        rtl_write_dword(rtlpriv, INTA_MASK + 4, 0);
 
1232
 
 
1233
        rtlpci->irq_enabled = false;
 
1234
}
 
1235
 
 
1236
 
 
1237
static u8 _rtl92s_set_sysclk(struct ieee80211_hw *hw, u8 data)
 
1238
{
 
1239
        struct rtl_priv *rtlpriv = rtl_priv(hw);
 
1240
        u8 waitcnt = 100;
 
1241
        bool result = false;
 
1242
        u8 tmp;
 
1243
 
 
1244
        rtl_write_byte(rtlpriv, SYS_CLKR + 1, data);
 
1245
 
 
1246
        /* Wait the MAC synchronized. */
 
1247
        udelay(400);
 
1248
 
 
1249
        /* Check if it is set ready. */
 
1250
        tmp = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
 
1251
        result = ((tmp & BIT(7)) == (data & BIT(7)));
 
1252
 
 
1253
        if ((data & (BIT(6) | BIT(7))) == false) {
 
1254
                waitcnt = 100;
 
1255
                tmp = 0;
 
1256
 
 
1257
                while (1) {
 
1258
                        waitcnt--;
 
1259
                        tmp = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
 
1260
 
 
1261
                        if ((tmp & BIT(6)))
 
1262
                                break;
 
1263
 
 
1264
                        printk(KERN_ERR "wait for BIT(6) return value %x\n",
 
1265
                               tmp);
 
1266
 
 
1267
                        if (waitcnt == 0)
 
1268
                                break;
 
1269
                        udelay(10);
 
1270
                }
 
1271
 
 
1272
                if (waitcnt == 0)
 
1273
                        result = false;
 
1274
                else
 
1275
                        result = true;
 
1276
        }
 
1277
 
 
1278
        return result;
 
1279
}
 
1280
 
 
1281
static void _rtl92s_phy_set_rfhalt(struct ieee80211_hw *hw)
 
1282
{
 
1283
        struct rtl_priv *rtlpriv = rtl_priv(hw);
 
1284
        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 
1285
        struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 
1286
        u8 u1btmp;
 
1287
 
 
1288
        if (rtlhal->driver_going2unload)
 
1289
                rtl_write_byte(rtlpriv, 0x560, 0x0);
 
1290
 
 
1291
        /* Power save for BB/RF */
 
1292
        u1btmp = rtl_read_byte(rtlpriv, LDOV12D_CTRL);
 
1293
        u1btmp |= BIT(0);
 
1294
        rtl_write_byte(rtlpriv, LDOV12D_CTRL, u1btmp);
 
1295
        rtl_write_byte(rtlpriv, SPS1_CTRL, 0x0);
 
1296
        rtl_write_byte(rtlpriv, TXPAUSE, 0xFF);
 
1297
        rtl_write_word(rtlpriv, CMDR, 0x57FC);
 
1298
        udelay(100);
 
1299
        rtl_write_word(rtlpriv, CMDR, 0x77FC);
 
1300
        rtl_write_byte(rtlpriv, PHY_CCA, 0x0);
 
1301
        udelay(10);
 
1302
        rtl_write_word(rtlpriv, CMDR, 0x37FC);
 
1303
        udelay(10);
 
1304
        rtl_write_word(rtlpriv, CMDR, 0x77FC);
 
1305
        udelay(10);
 
1306
        rtl_write_word(rtlpriv, CMDR, 0x57FC);
 
1307
        rtl_write_word(rtlpriv, CMDR, 0x0000);
 
1308
 
 
1309
        if (rtlhal->driver_going2unload) {
 
1310
                u1btmp = rtl_read_byte(rtlpriv, (REG_SYS_FUNC_EN + 1));
 
1311
                u1btmp &= ~(BIT(0));
 
1312
                rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, u1btmp);
 
1313
        }
 
1314
 
 
1315
        u1btmp = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
 
1316
 
 
1317
        /* Add description. After switch control path. register
 
1318
         * after page1 will be invisible. We can not do any IO
 
1319
         * for register>0x40. After resume&MACIO reset, we need
 
1320
         * to remember previous reg content. */
 
1321
        if (u1btmp & BIT(7)) {
 
1322
                u1btmp &= ~(BIT(6) | BIT(7));
 
1323
                if (!_rtl92s_set_sysclk(hw, u1btmp)) {
 
1324
                        printk(KERN_ERR "Switch ctrl path fail\n");
 
1325
                        return;
 
1326
                }
 
1327
        }
 
1328
 
 
1329
        /* Power save for MAC */
 
1330
        if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS  &&
 
1331
                !rtlhal->driver_going2unload) {
 
1332
                /* enable LED function */
 
1333
                rtl_write_byte(rtlpriv, 0x03, 0xF9);
 
1334
        /* SW/HW radio off or halt adapter!! For example S3/S4 */
 
1335
        } else {
 
1336
                /* LED function disable. Power range is about 8mA now. */
 
1337
                /* if write 0xF1 disconnet_pci power
 
1338
                 *       ifconfig wlan0 down power are both high 35:70 */
 
1339
                /* if write oxF9 disconnet_pci power
 
1340
                 * ifconfig wlan0 down power are both low  12:45*/
 
1341
                rtl_write_byte(rtlpriv, 0x03, 0xF9);
 
1342
        }
 
1343
 
 
1344
        rtl_write_byte(rtlpriv, SYS_CLKR + 1, 0x70);
 
1345
        rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, 0x68);
 
1346
        rtl_write_byte(rtlpriv,  AFE_PLL_CTRL, 0x00);
 
1347
        rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
 
1348
        rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, 0x0E);
 
1349
        RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
 
1350
 
 
1351
}
 
1352
 
 
1353
static void _rtl92se_gen_refreshledstate(struct ieee80211_hw *hw)
 
1354
{
 
1355
        struct rtl_priv *rtlpriv = rtl_priv(hw);
 
1356
        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 
1357
        struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 
1358
        struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
 
1359
 
 
1360
        if (rtlpci->up_first_time == 1)
 
1361
                return;
 
1362
 
 
1363
        if (rtlpriv->psc.rfoff_reason == RF_CHANGE_BY_IPS)
 
1364
                rtl92se_sw_led_on(hw, pLed0);
 
1365
        else
 
1366
                rtl92se_sw_led_off(hw, pLed0);
 
1367
}
 
1368
 
 
1369
 
 
1370
static void _rtl92se_power_domain_init(struct ieee80211_hw *hw)
 
1371
{
 
1372
        struct rtl_priv *rtlpriv = rtl_priv(hw);
 
1373
        u16 tmpu2b;
 
1374
        u8 tmpu1b;
 
1375
 
 
1376
        rtlpriv->psc.pwrdomain_protect = true;
 
1377
 
 
1378
        tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
 
1379
        if (tmpu1b & BIT(7)) {
 
1380
                tmpu1b &= ~(BIT(6) | BIT(7));
 
1381
                if (!_rtl92s_set_sysclk(hw, tmpu1b)) {
 
1382
                        rtlpriv->psc.pwrdomain_protect = false;
 
1383
                        return;
 
1384
                }
 
1385
        }
 
1386
 
 
1387
        rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x0);
 
1388
        rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
 
1389
 
 
1390
        /* Reset MAC-IO and CPU and Core Digital BIT10/11/15 */
 
1391
        tmpu1b = rtl_read_byte(rtlpriv, SYS_FUNC_EN + 1);
 
1392
 
 
1393
        /* If IPS we need to turn LED on. So we not
 
1394
         * not disable BIT 3/7 of reg3. */
 
1395
        if (rtlpriv->psc.rfoff_reason & (RF_CHANGE_BY_IPS | RF_CHANGE_BY_HW))
 
1396
                tmpu1b &= 0xFB;
 
1397
        else
 
1398
                tmpu1b &= 0x73;
 
1399
 
 
1400
        rtl_write_byte(rtlpriv, SYS_FUNC_EN + 1, tmpu1b);
 
1401
        /* wait for BIT 10/11/15 to pull high automatically!! */
 
1402
        mdelay(1);
 
1403
 
 
1404
        rtl_write_byte(rtlpriv, CMDR, 0);
 
1405
        rtl_write_byte(rtlpriv, TCR, 0);
 
1406
 
 
1407
        /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */
 
1408
        tmpu1b = rtl_read_byte(rtlpriv, 0x562);
 
1409
        tmpu1b |= 0x08;
 
1410
        rtl_write_byte(rtlpriv, 0x562, tmpu1b);
 
1411
        tmpu1b &= ~(BIT(3));
 
1412
        rtl_write_byte(rtlpriv, 0x562, tmpu1b);
 
1413
 
 
1414
        /* Enable AFE clock source */
 
1415
        tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL);
 
1416
        rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, (tmpu1b | 0x01));
 
1417
        /* Delay 1.5ms */
 
1418
        udelay(1500);
 
1419
        tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL + 1);
 
1420
        rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, (tmpu1b & 0xfb));
 
1421
 
 
1422
        /* Enable AFE Macro Block's Bandgap */
 
1423
        tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
 
1424
        rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0)));
 
1425
        mdelay(1);
 
1426
 
 
1427
        /* Enable AFE Mbias */
 
1428
        tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
 
1429
        rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | 0x02));
 
1430
        mdelay(1);
 
1431
 
 
1432
        /* Enable LDOA15 block */
 
1433
        tmpu1b = rtl_read_byte(rtlpriv, LDOA15_CTRL);
 
1434
        rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0)));
 
1435
 
 
1436
        /* Set Digital Vdd to Retention isolation Path. */
 
1437
        tmpu2b = rtl_read_word(rtlpriv, SYS_ISO_CTRL);
 
1438
        rtl_write_word(rtlpriv, SYS_ISO_CTRL, (tmpu2b | BIT(11)));
 
1439
 
 
1440
 
 
1441
        /* For warm reboot NIC disappera bug. */
 
1442
        tmpu2b = rtl_read_word(rtlpriv, SYS_FUNC_EN);
 
1443
        rtl_write_word(rtlpriv, SYS_FUNC_EN, (tmpu2b | BIT(13)));
 
1444
 
 
1445
        rtl_write_byte(rtlpriv, SYS_ISO_CTRL + 1, 0x68);
 
1446
 
 
1447
        /* Enable AFE PLL Macro Block */
 
1448
        tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL);
 
1449
        rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
 
1450
        /* Enable MAC 80MHZ clock */
 
1451
        tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL + 1);
 
1452
        rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0)));
 
1453
        mdelay(1);
 
1454
 
 
1455
        /* Release isolation AFE PLL & MD */
 
1456
        rtl_write_byte(rtlpriv, SYS_ISO_CTRL, 0xA6);
 
1457
 
 
1458
        /* Enable MAC clock */
 
1459
        tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
 
1460
        rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11)));
 
1461
 
 
1462
        /* Enable Core digital and enable IOREG R/W */
 
1463
        tmpu2b = rtl_read_word(rtlpriv, SYS_FUNC_EN);
 
1464
        rtl_write_word(rtlpriv, SYS_FUNC_EN, (tmpu2b | BIT(11)));
 
1465
        /* enable REG_EN */
 
1466
        rtl_write_word(rtlpriv, SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15)));
 
1467
 
 
1468
        /* Switch the control path. */
 
1469
        tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
 
1470
        rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b & (~BIT(2))));
 
1471
 
 
1472
        tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
 
1473
        tmpu1b = ((tmpu1b | BIT(7)) & (~BIT(6)));
 
1474
        if (!_rtl92s_set_sysclk(hw, tmpu1b)) {
 
1475
                rtlpriv->psc.pwrdomain_protect = false;
 
1476
                return;
 
1477
        }
 
1478
 
 
1479
        rtl_write_word(rtlpriv, CMDR, 0x37FC);
 
1480
 
 
1481
        /* After MACIO reset,we must refresh LED state. */
 
1482
        _rtl92se_gen_refreshledstate(hw);
 
1483
 
 
1484
        rtlpriv->psc.pwrdomain_protect = false;
 
1485
}
 
1486
 
 
1487
void rtl92se_card_disable(struct ieee80211_hw *hw)
 
1488
{
 
1489
        struct rtl_priv *rtlpriv = rtl_priv(hw);
 
1490
        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 
1491
        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 
1492
        struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 
1493
        enum nl80211_iftype opmode;
 
1494
        u8 wait = 30;
 
1495
 
 
1496
        rtlpriv->intf_ops->enable_aspm(hw);
 
1497
 
 
1498
        if (rtlpci->driver_is_goingto_unload ||
 
1499
                ppsc->rfoff_reason > RF_CHANGE_BY_PS)
 
1500
                rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
 
1501
 
 
1502
        /* we should chnge GPIO to input mode
 
1503
         * this will drop away current about 25mA*/
 
1504
        rtl8192se_gpiobit3_cfg_inputmode(hw);
 
1505
 
 
1506
        /* this is very important for ips power save */
 
1507
        while (wait-- >= 10 && rtlpriv->psc.pwrdomain_protect) {
 
1508
                if (rtlpriv->psc.pwrdomain_protect)
 
1509
                        mdelay(20);
 
1510
                else
 
1511
                        break;
 
1512
        }
 
1513
 
 
1514
        mac->link_state = MAC80211_NOLINK;
 
1515
        opmode = NL80211_IFTYPE_UNSPECIFIED;
 
1516
        _rtl92se_set_media_status(hw, opmode);
 
1517
 
 
1518
        _rtl92s_phy_set_rfhalt(hw);
 
1519
        udelay(100);
 
1520
}
 
1521
 
 
1522
void rtl92se_interrupt_recognized(struct ieee80211_hw *hw, u32 *p_inta,
 
1523
                             u32 *p_intb)
 
1524
{
 
1525
        struct rtl_priv *rtlpriv = rtl_priv(hw);
 
1526
        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 
1527
 
 
1528
        *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
 
1529
        rtl_write_dword(rtlpriv, ISR, *p_inta);
 
1530
 
 
1531
        *p_intb = rtl_read_dword(rtlpriv, ISR + 4) & rtlpci->irq_mask[1];
 
1532
        rtl_write_dword(rtlpriv, ISR + 4, *p_intb);
 
1533
}
 
1534
 
 
1535
void rtl92se_set_beacon_related_registers(struct ieee80211_hw *hw)
 
1536
{
 
1537
        struct rtl_priv *rtlpriv = rtl_priv(hw);
 
1538
        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 
1539
        u16 bcntime_cfg = 0;
 
1540
        u16 bcn_cw = 6, bcn_ifs = 0xf;
 
1541
        u16 atim_window = 2;
 
1542
 
 
1543
        /* ATIM Window (in unit of TU). */
 
1544
        rtl_write_word(rtlpriv, ATIMWND, atim_window);
 
1545
 
 
1546
        /* Beacon interval (in unit of TU). */
 
1547
        rtl_write_word(rtlpriv, BCN_INTERVAL, mac->beacon_interval);
 
1548
 
 
1549
        /* DrvErlyInt (in unit of TU). (Time to send
 
1550
         * interrupt to notify driver to change
 
1551
         * beacon content) */
 
1552
        rtl_write_word(rtlpriv, BCN_DRV_EARLY_INT, 10 << 4);
 
1553
 
 
1554
        /* BcnDMATIM(in unit of us). Indicates the
 
1555
         * time before TBTT to perform beacon queue DMA  */
 
1556
        rtl_write_word(rtlpriv, BCN_DMATIME, 256);
 
1557
 
 
1558
        /* Force beacon frame transmission even
 
1559
         * after receiving beacon frame from
 
1560
         * other ad hoc STA */
 
1561
        rtl_write_byte(rtlpriv, BCN_ERR_THRESH, 100);
 
1562
 
 
1563
        /* Beacon Time Configuration */
 
1564
        if (mac->opmode == NL80211_IFTYPE_ADHOC)
 
1565
                bcntime_cfg |= (bcn_cw << BCN_TCFG_CW_SHIFT);
 
1566
 
 
1567
        /* TODO: bcn_ifs may required to be changed on ASIC */
 
1568
        bcntime_cfg |= bcn_ifs << BCN_TCFG_IFS;
 
1569
 
 
1570
        /*for beacon changed */
 
1571
        rtl92s_phy_set_beacon_hwreg(hw, mac->beacon_interval);
 
1572
}
 
1573
 
 
1574
void rtl92se_set_beacon_interval(struct ieee80211_hw *hw)
 
1575
{
 
1576
        struct rtl_priv *rtlpriv = rtl_priv(hw);
 
1577
        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 
1578
        u16 bcn_interval = mac->beacon_interval;
 
1579
 
 
1580
        /* Beacon interval (in unit of TU). */
 
1581
        rtl_write_word(rtlpriv, BCN_INTERVAL, bcn_interval);
 
1582
        /* 2008.10.24 added by tynli for beacon changed. */
 
1583
        rtl92s_phy_set_beacon_hwreg(hw, bcn_interval);
 
1584
}
 
1585
 
 
1586
void rtl92se_update_interrupt_mask(struct ieee80211_hw *hw,
 
1587
                u32 add_msr, u32 rm_msr)
 
1588
{
 
1589
        struct rtl_priv *rtlpriv = rtl_priv(hw);
 
1590
        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 
1591
 
 
1592
        RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
 
1593
                 ("add_msr:%x, rm_msr:%x\n", add_msr, rm_msr));
 
1594
 
 
1595
        if (add_msr)
 
1596
                rtlpci->irq_mask[0] |= add_msr;
 
1597
 
 
1598
        if (rm_msr)
 
1599
                rtlpci->irq_mask[0] &= (~rm_msr);
 
1600
 
 
1601
        rtl92se_disable_interrupt(hw);
 
1602
        rtl92se_enable_interrupt(hw);
 
1603
}
 
1604
 
 
1605
static void _rtl8192se_get_IC_Inferiority(struct ieee80211_hw *hw)
 
1606
{
 
1607
        struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 
1608
        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 
1609
        u8 efuse_id;
 
1610
 
 
1611
        rtlhal->ic_class = IC_INFERIORITY_A;
 
1612
 
 
1613
        /* Only retrieving while using EFUSE. */
 
1614
        if ((rtlefuse->epromtype == EEPROM_BOOT_EFUSE) &&
 
1615
                !rtlefuse->autoload_failflag) {
 
1616
                efuse_id = efuse_read_1byte(hw, EFUSE_IC_ID_OFFSET);
 
1617
 
 
1618
                if (efuse_id == 0xfe)
 
1619
                        rtlhal->ic_class = IC_INFERIORITY_B;
 
1620
        }
 
1621
}
 
1622
 
 
1623
static void _rtl92se_read_adapter_info(struct ieee80211_hw *hw)
 
1624
{
 
1625
        struct rtl_priv *rtlpriv = rtl_priv(hw);
 
1626
        struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 
1627
        struct rtl_phy *rtlphy = &(rtlpriv->phy);
 
1628
        u16 i, usvalue;
 
1629
        u16     eeprom_id;
 
1630
        u8 tempval;
 
1631
        u8 hwinfo[HWSET_MAX_SIZE_92S];
 
1632
        u8 rf_path, index;
 
1633
 
 
1634
        if (rtlefuse->epromtype == EEPROM_93C46) {
 
1635
                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 
1636
                         ("RTL819X Not boot from eeprom, check it !!"));
 
1637
        } else if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
 
1638
                rtl_efuse_shadow_map_update(hw);
 
1639
 
 
1640
                memcpy((void *)hwinfo, (void *)
 
1641
                        &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
 
1642
                        HWSET_MAX_SIZE_92S);
 
1643
        }
 
1644
 
 
1645
        RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, ("MAP\n"),
 
1646
                      hwinfo, HWSET_MAX_SIZE_92S);
 
1647
 
 
1648
        eeprom_id = *((u16 *)&hwinfo[0]);
 
1649
        if (eeprom_id != RTL8190_EEPROM_ID) {
 
1650
                RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 
1651
                         ("EEPROM ID(%#x) is invalid!!\n", eeprom_id));
 
1652
                rtlefuse->autoload_failflag = true;
 
1653
        } else {
 
1654
                RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
 
1655
                rtlefuse->autoload_failflag = false;
 
1656
        }
 
1657
 
 
1658
        if (rtlefuse->autoload_failflag == true)
 
1659
                return;
 
1660
 
 
1661
        _rtl8192se_get_IC_Inferiority(hw);
 
1662
 
 
1663
        /* Read IC Version && Channel Plan */
 
1664
        /* VID, DID      SE     0xA-D */
 
1665
        rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
 
1666
        rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
 
1667
        rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
 
1668
        rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
 
1669
        rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
 
1670
 
 
1671
        RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 
1672
                        ("EEPROMId = 0x%4x\n", eeprom_id));
 
1673
        RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 
1674
                        ("EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid));
 
1675
        RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 
1676
                        ("EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did));
 
1677
        RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 
1678
                        ("EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid));
 
1679
        RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 
1680
                        ("EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid));
 
1681
 
 
1682
        for (i = 0; i < 6; i += 2) {
 
1683
                usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
 
1684
                *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
 
1685
        }
 
1686
 
 
1687
        for (i = 0; i < 6; i++)
 
1688
                rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]);
 
1689
 
 
1690
        RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
 
1691
                 (MAC_FMT "\n", MAC_ARG(rtlefuse->dev_addr)));
 
1692
 
 
1693
        /* Get Tx Power Level by Channel */
 
1694
        /* Read Tx power of Channel 1 ~ 14 from EEPROM. */
 
1695
        /* 92S suupport RF A & B */
 
1696
        for (rf_path = 0; rf_path < 2; rf_path++) {
 
1697
                for (i = 0; i < 3; i++) {
 
1698
                        /* Read CCK RF A & B Tx power  */
 
1699
                        rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][i] =
 
1700
                        hwinfo[EEPROM_TXPOWERBASE + rf_path * 3 + i];
 
1701
 
 
1702
                        /* Read OFDM RF A & B Tx power for 1T */
 
1703
                        rtlefuse->eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
 
1704
                        hwinfo[EEPROM_TXPOWERBASE + 6 + rf_path * 3 + i];
 
1705
 
 
1706
                        /* Read OFDM RF A & B Tx power for 2T */
 
1707
                        rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path][i]
 
1708
                                 = hwinfo[EEPROM_TXPOWERBASE + 12 +
 
1709
                                   rf_path * 3 + i];
 
1710
                }
 
1711
        }
 
1712
 
 
1713
        for (rf_path = 0; rf_path < 2; rf_path++)
 
1714
                for (i = 0; i < 3; i++)
 
1715
                        RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
 
1716
                                ("RF(%d) EEPROM CCK Area(%d) = 0x%x\n", rf_path,
 
1717
                                i, rtlefuse->eeprom_chnlarea_txpwr_cck
 
1718
                                        [rf_path][i]));
 
1719
        for (rf_path = 0; rf_path < 2; rf_path++)
 
1720
                for (i = 0; i < 3; i++)
 
1721
                        RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
 
1722
                                ("RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
 
1723
                                 rf_path, i,
 
1724
                                 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
 
1725
                                                [rf_path][i]));
 
1726
        for (rf_path = 0; rf_path < 2; rf_path++)
 
1727
                for (i = 0; i < 3; i++)
 
1728
                        RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
 
1729
                                ("RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
 
1730
                                 rf_path, i,
 
1731
                                 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif
 
1732
                                        [rf_path][i]));
 
1733
 
 
1734
        for (rf_path = 0; rf_path < 2; rf_path++) {
 
1735
 
 
1736
                /* Assign dedicated channel tx power */
 
1737
                for (i = 0; i < 14; i++)        {
 
1738
                        /* channel 1~3 use the same Tx Power Level. */
 
1739
                        if (i < 3)
 
1740
                                index = 0;
 
1741
                        /* Channel 4-8 */
 
1742
                        else if (i < 8)
 
1743
                                index = 1;
 
1744
                        /* Channel 9-14 */
 
1745
                        else
 
1746
                                index = 2;
 
1747
 
 
1748
                        /* Record A & B CCK /OFDM - 1T/2T Channel area
 
1749
                         * tx power */
 
1750
                        rtlefuse->txpwrlevel_cck[rf_path][i]  =
 
1751
                                rtlefuse->eeprom_chnlarea_txpwr_cck
 
1752
                                                        [rf_path][index];
 
1753
                        rtlefuse->txpwrlevel_ht40_1s[rf_path][i]  =
 
1754
                                rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
 
1755
                                                        [rf_path][index];
 
1756
                        rtlefuse->txpwrlevel_ht40_2s[rf_path][i]  =
 
1757
                                rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif
 
1758
                                                        [rf_path][index];
 
1759
                }
 
1760
 
 
1761
                for (i = 0; i < 14; i++) {
 
1762
                        RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 
1763
                                ("RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = "
 
1764
                                 "[0x%x / 0x%x / 0x%x]\n", rf_path, i,
 
1765
                                 rtlefuse->txpwrlevel_cck[rf_path][i],
 
1766
                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
 
1767
                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]));
 
1768
                }
 
1769
        }
 
1770
 
 
1771
        for (rf_path = 0; rf_path < 2; rf_path++) {
 
1772
                for (i = 0; i < 3; i++) {
 
1773
                        /* Read Power diff limit. */
 
1774
                        rtlefuse->eeprom_pwrgroup[rf_path][i] =
 
1775
                                hwinfo[EEPROM_TXPWRGROUP + rf_path * 3 + i];
 
1776
                }
 
1777
        }
 
1778
 
 
1779
        for (rf_path = 0; rf_path < 2; rf_path++) {
 
1780
                /* Fill Pwr group */
 
1781
                for (i = 0; i < 14; i++) {
 
1782
                        /* Chanel 1-3 */
 
1783
                        if (i < 3)
 
1784
                                index = 0;
 
1785
                        /* Channel 4-8 */
 
1786
                        else if (i < 8)
 
1787
                                index = 1;
 
1788
                        /* Channel 9-13 */
 
1789
                        else
 
1790
                                index = 2;
 
1791
 
 
1792
                        rtlefuse->pwrgroup_ht20[rf_path][i] =
 
1793
                                (rtlefuse->eeprom_pwrgroup[rf_path][index] &
 
1794
                                0xf);
 
1795
                        rtlefuse->pwrgroup_ht40[rf_path][i] =
 
1796
                                ((rtlefuse->eeprom_pwrgroup[rf_path][index] &
 
1797
                                0xf0) >> 4);
 
1798
 
 
1799
                        RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 
1800
                                ("RF-%d pwrgroup_ht20[%d] = 0x%x\n",
 
1801
                                 rf_path, i,
 
1802
                                 rtlefuse->pwrgroup_ht20[rf_path][i]));
 
1803
                        RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 
1804
                                ("RF-%d pwrgroup_ht40[%d] = 0x%x\n",
 
1805
                                 rf_path, i,
 
1806
                                 rtlefuse->pwrgroup_ht40[rf_path][i]));
 
1807
                        }
 
1808
        }
 
1809
 
 
1810
        for (i = 0; i < 14; i++) {
 
1811
                /* Read tx power difference between HT OFDM 20/40 MHZ */
 
1812
                /* channel 1-3 */
 
1813
                if (i < 3)
 
1814
                        index = 0;
 
1815
                /* Channel 4-8 */
 
1816
                else if (i < 8)
 
1817
                        index = 1;
 
1818
                /* Channel 9-14 */
 
1819
                else
 
1820
                        index = 2;
 
1821
 
 
1822
                tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_HT20_DIFF +
 
1823
                           index]) & 0xff;
 
1824
                rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
 
1825
                rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
 
1826
                                                 ((tempval >> 4) & 0xF);
 
1827
 
 
1828
                /* Read OFDM<->HT tx power diff */
 
1829
                /* Channel 1-3 */
 
1830
                if (i < 3)
 
1831
                        index = 0;
 
1832
                /* Channel 4-8 */
 
1833
                else if (i < 8)
 
1834
                        index = 0x11;
 
1835
                /* Channel 9-14 */
 
1836
                else
 
1837
                        index = 1;
 
1838
 
 
1839
                tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_OFDM_DIFF + index])
 
1840
                                  & 0xff;
 
1841
                rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] =
 
1842
                                 (tempval & 0xF);
 
1843
                rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
 
1844
                                 ((tempval >> 4) & 0xF);
 
1845
 
 
1846
                tempval = (*(u8 *)&hwinfo[TX_PWR_SAFETY_CHK]);
 
1847
                rtlefuse->txpwr_safetyflag = (tempval & 0x01);
 
1848
        }
 
1849
 
 
1850
        rtlefuse->eeprom_regulatory = 0;
 
1851
        if (rtlefuse->eeprom_version >= 2) {
 
1852
                /* BIT(0)~2 */
 
1853
                if (rtlefuse->eeprom_version >= 4)
 
1854
                        rtlefuse->eeprom_regulatory =
 
1855
                                 (hwinfo[EEPROM_REGULATORY] & 0x7);
 
1856
                else /* BIT(0) */
 
1857
                        rtlefuse->eeprom_regulatory =
 
1858
                                 (hwinfo[EEPROM_REGULATORY] & 0x1);
 
1859
        }
 
1860
        RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 
1861
                ("eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory));
 
1862
 
 
1863
        for (i = 0; i < 14; i++)
 
1864
                RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 
1865
                        ("RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i,
 
1866
                         rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]));
 
1867
        for (i = 0; i < 14; i++)
 
1868
                RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 
1869
                        ("RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i,
 
1870
                         rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]));
 
1871
        for (i = 0; i < 14; i++)
 
1872
                RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 
1873
                        ("RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i,
 
1874
                         rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]));
 
1875
        for (i = 0; i < 14; i++)
 
1876
                RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 
1877
                        ("RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i,
 
1878
                         rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]));
 
1879
 
 
1880
        RTPRINT(rtlpriv, FINIT, INIT_TxPower, ("TxPwrSafetyFlag = %d\n",
 
1881
                rtlefuse->txpwr_safetyflag));
 
1882
 
 
1883
        /* Read RF-indication and Tx Power gain
 
1884
         * index diff of legacy to HT OFDM rate. */
 
1885
        tempval = (*(u8 *)&hwinfo[EEPROM_RFIND_POWERDIFF]) & 0xff;
 
1886
        rtlefuse->eeprom_txpowerdiff = tempval;
 
1887
        rtlefuse->legacy_httxpowerdiff =
 
1888
                rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][0];
 
1889
 
 
1890
        RTPRINT(rtlpriv, FINIT, INIT_TxPower, ("TxPowerDiff = %#x\n",
 
1891
                rtlefuse->eeprom_txpowerdiff));
 
1892
 
 
1893
        /* Get TSSI value for each path. */
 
1894
        usvalue = *(u16 *)&hwinfo[EEPROM_TSSI_A];
 
1895
        rtlefuse->eeprom_tssi[RF90_PATH_A] = (u8)((usvalue & 0xff00) >> 8);
 
1896
        usvalue = *(u8 *)&hwinfo[EEPROM_TSSI_B];
 
1897
        rtlefuse->eeprom_tssi[RF90_PATH_B] = (u8)(usvalue & 0xff);
 
1898
 
 
1899
        RTPRINT(rtlpriv, FINIT, INIT_TxPower, ("TSSI_A = 0x%x, TSSI_B = 0x%x\n",
 
1900
                 rtlefuse->eeprom_tssi[RF90_PATH_A],
 
1901
                 rtlefuse->eeprom_tssi[RF90_PATH_B]));
 
1902
 
 
1903
        /* Read antenna tx power offset of B/C/D to A  from EEPROM */
 
1904
        /* and read ThermalMeter from EEPROM */
 
1905
        tempval = *(u8 *)&hwinfo[EEPROM_THERMALMETER];
 
1906
        rtlefuse->eeprom_thermalmeter = tempval;
 
1907
        RTPRINT(rtlpriv, FINIT, INIT_TxPower, ("thermalmeter = 0x%x\n",
 
1908
                rtlefuse->eeprom_thermalmeter));
 
1909
 
 
1910
        /* ThermalMeter, BIT(0)~3 for RFIC1, BIT(4)~7 for RFIC2 */
 
1911
        rtlefuse->thermalmeter[0] = (rtlefuse->eeprom_thermalmeter & 0x1f);
 
1912
        rtlefuse->tssi_13dbm = rtlefuse->eeprom_thermalmeter * 100;
 
1913
 
 
1914
        /* Read CrystalCap from EEPROM */
 
1915
        tempval = (*(u8 *)&hwinfo[EEPROM_CRYSTALCAP]) >> 4;
 
1916
        rtlefuse->eeprom_crystalcap = tempval;
 
1917
        /* CrystalCap, BIT(12)~15 */
 
1918
        rtlefuse->crystalcap = rtlefuse->eeprom_crystalcap;
 
1919
 
 
1920
        /* Read IC Version && Channel Plan */
 
1921
        /* Version ID, Channel plan */
 
1922
        rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
 
1923
        rtlefuse->txpwr_fromeprom = true;
 
1924
        RTPRINT(rtlpriv, FINIT, INIT_TxPower, ("EEPROM ChannelPlan = 0x%4x\n",
 
1925
                rtlefuse->eeprom_channelplan));
 
1926
 
 
1927
        /* Read Customer ID or Board Type!!! */
 
1928
        tempval = *(u8 *)&hwinfo[EEPROM_BOARDTYPE];
 
1929
        /* Change RF type definition */
 
1930
        if (tempval == 0)
 
1931
                rtlphy->rf_type = RF_2T2R;
 
1932
        else if (tempval == 1)
 
1933
                rtlphy->rf_type = RF_1T2R;
 
1934
        else if (tempval == 2)
 
1935
                rtlphy->rf_type = RF_1T2R;
 
1936
        else if (tempval == 3)
 
1937
                rtlphy->rf_type = RF_1T1R;
 
1938
 
 
1939
        /* 1T2R but 1SS (1x1 receive combining) */
 
1940
        rtlefuse->b1x1_recvcombine = false;
 
1941
        if (rtlphy->rf_type == RF_1T2R) {
 
1942
                tempval = rtl_read_byte(rtlpriv, 0x07);
 
1943
                if (!(tempval & BIT(0))) {
 
1944
                        rtlefuse->b1x1_recvcombine = true;
 
1945
                        RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 
1946
                                ("RF_TYPE=1T2R but only 1SS\n"));
 
1947
                }
 
1948
        }
 
1949
        rtlefuse->b1ss_support = rtlefuse->b1x1_recvcombine;
 
1950
        rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMID];
 
1951
 
 
1952
        RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("EEPROM Customer ID: 0x%2x",
 
1953
                        rtlefuse->eeprom_oemid));
 
1954
 
 
1955
        /* set channel paln to world wide 13 */
 
1956
        rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13;
 
1957
}
 
1958
 
 
1959
void rtl92se_read_eeprom_info(struct ieee80211_hw *hw)
 
1960
{
 
1961
        struct rtl_priv *rtlpriv = rtl_priv(hw);
 
1962
        struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 
1963
        u8 tmp_u1b = 0;
 
1964
 
 
1965
        tmp_u1b = rtl_read_byte(rtlpriv, EPROM_CMD);
 
1966
 
 
1967
        if (tmp_u1b & BIT(4)) {
 
1968
                RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("Boot from EEPROM\n"));
 
1969
                rtlefuse->epromtype = EEPROM_93C46;
 
1970
        } else {
 
1971
                RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("Boot from EFUSE\n"));
 
1972
                rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
 
1973
        }
 
1974
 
 
1975
        if (tmp_u1b & BIT(5)) {
 
1976
                RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
 
1977
                rtlefuse->autoload_failflag = false;
 
1978
                _rtl92se_read_adapter_info(hw);
 
1979
        } else {
 
1980
                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Autoload ERR!!\n"));
 
1981
                rtlefuse->autoload_failflag = true;
 
1982
        }
 
1983
}
 
1984
 
 
1985
static void rtl92se_update_hal_rate_table(struct ieee80211_hw *hw,
 
1986
                                          struct ieee80211_sta *sta)
 
1987
{
 
1988
        struct rtl_priv *rtlpriv = rtl_priv(hw);
 
1989
        struct rtl_phy *rtlphy = &(rtlpriv->phy);
 
1990
        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 
1991
        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 
1992
        u32 ratr_value;
 
1993
        u8 ratr_index = 0;
 
1994
        u8 nmode = mac->ht_enable;
 
1995
        u8 mimo_ps = IEEE80211_SMPS_OFF;
 
1996
        u16 shortgi_rate = 0;
 
1997
        u32 tmp_ratr_value = 0;
 
1998
        u8 curtxbw_40mhz = mac->bw_40;
 
1999
        u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
 
2000
                                1 : 0;
 
2001
        u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
 
2002
                                1 : 0;
 
2003
        enum wireless_mode wirelessmode = mac->mode;
 
2004
 
 
2005
        if (rtlhal->current_bandtype == BAND_ON_5G)
 
2006
                ratr_value = sta->supp_rates[1] << 4;
 
2007
        else
 
2008
                ratr_value = sta->supp_rates[0];
 
2009
        ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
 
2010
                        sta->ht_cap.mcs.rx_mask[0] << 12);
 
2011
        switch (wirelessmode) {
 
2012
        case WIRELESS_MODE_B:
 
2013
                ratr_value &= 0x0000000D;
 
2014
                break;
 
2015
        case WIRELESS_MODE_G:
 
2016
                ratr_value &= 0x00000FF5;
 
2017
                break;
 
2018
        case WIRELESS_MODE_N_24G:
 
2019
        case WIRELESS_MODE_N_5G:
 
2020
                nmode = 1;
 
2021
                if (mimo_ps == IEEE80211_SMPS_STATIC) {
 
2022
                        ratr_value &= 0x0007F005;
 
2023
                } else {
 
2024
                        u32 ratr_mask;
 
2025
 
 
2026
                        if (get_rf_type(rtlphy) == RF_1T2R ||
 
2027
                            get_rf_type(rtlphy) == RF_1T1R) {
 
2028
                                if (curtxbw_40mhz)
 
2029
                                        ratr_mask = 0x000ff015;
 
2030
                                else
 
2031
                                        ratr_mask = 0x000ff005;
 
2032
                        } else {
 
2033
                                if (curtxbw_40mhz)
 
2034
                                        ratr_mask = 0x0f0ff015;
 
2035
                                else
 
2036
                                        ratr_mask = 0x0f0ff005;
 
2037
                        }
 
2038
 
 
2039
                        ratr_value &= ratr_mask;
 
2040
                }
 
2041
                break;
 
2042
        default:
 
2043
                if (rtlphy->rf_type == RF_1T2R)
 
2044
                        ratr_value &= 0x000ff0ff;
 
2045
                else
 
2046
                        ratr_value &= 0x0f0ff0ff;
 
2047
 
 
2048
                break;
 
2049
        }
 
2050
 
 
2051
        if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT)
 
2052
                ratr_value &= 0x0FFFFFFF;
 
2053
        else if (rtlpriv->rtlhal.version == VERSION_8192S_ACUT)
 
2054
                ratr_value &= 0x0FFFFFF0;
 
2055
 
 
2056
        if (nmode && ((curtxbw_40mhz &&
 
2057
                         curshortgi_40mhz) || (!curtxbw_40mhz &&
 
2058
                                                 curshortgi_20mhz))) {
 
2059
 
 
2060
                ratr_value |= 0x10000000;
 
2061
                tmp_ratr_value = (ratr_value >> 12);
 
2062
 
 
2063
                for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
 
2064
                        if ((1 << shortgi_rate) & tmp_ratr_value)
 
2065
                                break;
 
2066
                }
 
2067
 
 
2068
                shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
 
2069
                    (shortgi_rate << 4) | (shortgi_rate);
 
2070
 
 
2071
                rtl_write_byte(rtlpriv, SG_RATE, shortgi_rate);
 
2072
        }
 
2073
 
 
2074
        rtl_write_dword(rtlpriv, ARFR0 + ratr_index * 4, ratr_value);
 
2075
        if (ratr_value & 0xfffff000)
 
2076
                rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_REFRESH_N);
 
2077
        else
 
2078
                rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_REFRESH_BG);
 
2079
 
 
2080
        RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
 
2081
                 ("%x\n", rtl_read_dword(rtlpriv, ARFR0)));
 
2082
}
 
2083
 
 
2084
static void rtl92se_update_hal_rate_mask(struct ieee80211_hw *hw,
 
2085
                                         struct ieee80211_sta *sta,
 
2086
                                         u8 rssi_level)
 
2087
{
 
2088
        struct rtl_priv *rtlpriv = rtl_priv(hw);
 
2089
        struct rtl_phy *rtlphy = &(rtlpriv->phy);
 
2090
        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 
2091
        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 
2092
        struct rtl_sta_info *sta_entry = NULL;
 
2093
        u32 ratr_bitmap;
 
2094
        u8 ratr_index = 0;
 
2095
        u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
 
2096
                                ? 1 : 0;
 
2097
        u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
 
2098
                                1 : 0;
 
2099
        u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
 
2100
                                1 : 0;
 
2101
        enum wireless_mode wirelessmode = 0;
 
2102
        bool shortgi = false;
 
2103
        u32 ratr_value = 0;
 
2104
        u8 shortgi_rate = 0;
 
2105
        u32 mask = 0;
 
2106
        u32 band = 0;
 
2107
        bool bmulticast = false;
 
2108
        u8 macid = 0;
 
2109
        u8 mimo_ps = IEEE80211_SMPS_OFF;
 
2110
 
 
2111
        sta_entry = (struct rtl_sta_info *) sta->drv_priv;
 
2112
        wirelessmode = sta_entry->wireless_mode;
 
2113
        if (mac->opmode == NL80211_IFTYPE_STATION)
 
2114
                curtxbw_40mhz = mac->bw_40;
 
2115
        else if (mac->opmode == NL80211_IFTYPE_AP ||
 
2116
                mac->opmode == NL80211_IFTYPE_ADHOC)
 
2117
                macid = sta->aid + 1;
 
2118
 
 
2119
        if (rtlhal->current_bandtype == BAND_ON_5G)
 
2120
                ratr_bitmap = sta->supp_rates[1] << 4;
 
2121
        else
 
2122
                ratr_bitmap = sta->supp_rates[0];
 
2123
        ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
 
2124
                        sta->ht_cap.mcs.rx_mask[0] << 12);
 
2125
        switch (wirelessmode) {
 
2126
        case WIRELESS_MODE_B:
 
2127
                band |= WIRELESS_11B;
 
2128
                ratr_index = RATR_INX_WIRELESS_B;
 
2129
                if (ratr_bitmap & 0x0000000c)
 
2130
                        ratr_bitmap &= 0x0000000d;
 
2131
                else
 
2132
                        ratr_bitmap &= 0x0000000f;
 
2133
                break;
 
2134
        case WIRELESS_MODE_G:
 
2135
                band |= (WIRELESS_11G | WIRELESS_11B);
 
2136
                ratr_index = RATR_INX_WIRELESS_GB;
 
2137
 
 
2138
                if (rssi_level == 1)
 
2139
                        ratr_bitmap &= 0x00000f00;
 
2140
                else if (rssi_level == 2)
 
2141
                        ratr_bitmap &= 0x00000ff0;
 
2142
                else
 
2143
                        ratr_bitmap &= 0x00000ff5;
 
2144
                break;
 
2145
        case WIRELESS_MODE_A:
 
2146
                band |= WIRELESS_11A;
 
2147
                ratr_index = RATR_INX_WIRELESS_A;
 
2148
                ratr_bitmap &= 0x00000ff0;
 
2149
                break;
 
2150
        case WIRELESS_MODE_N_24G:
 
2151
        case WIRELESS_MODE_N_5G:
 
2152
                band |= (WIRELESS_11N | WIRELESS_11G | WIRELESS_11B);
 
2153
                ratr_index = RATR_INX_WIRELESS_NGB;
 
2154
 
 
2155
                if (mimo_ps == IEEE80211_SMPS_STATIC) {
 
2156
                        if (rssi_level == 1)
 
2157
                                ratr_bitmap &= 0x00070000;
 
2158
                        else if (rssi_level == 2)
 
2159
                                ratr_bitmap &= 0x0007f000;
 
2160
                        else
 
2161
                                ratr_bitmap &= 0x0007f005;
 
2162
                } else {
 
2163
                        if (rtlphy->rf_type == RF_1T2R ||
 
2164
                                rtlphy->rf_type == RF_1T1R) {
 
2165
                                if (rssi_level == 1) {
 
2166
                                                ratr_bitmap &= 0x000f0000;
 
2167
                                } else if (rssi_level == 3) {
 
2168
                                        ratr_bitmap &= 0x000fc000;
 
2169
                                } else if (rssi_level == 5) {
 
2170
                                                ratr_bitmap &= 0x000ff000;
 
2171
                                } else {
 
2172
                                        if (curtxbw_40mhz)
 
2173
                                                ratr_bitmap &= 0x000ff015;
 
2174
                                        else
 
2175
                                                ratr_bitmap &= 0x000ff005;
 
2176
                                }
 
2177
                        } else {
 
2178
                                if (rssi_level == 1) {
 
2179
                                        ratr_bitmap &= 0x0f8f0000;
 
2180
                                } else if (rssi_level == 3) {
 
2181
                                        ratr_bitmap &= 0x0f8fc000;
 
2182
                                } else if (rssi_level == 5) {
 
2183
                                        ratr_bitmap &= 0x0f8ff000;
 
2184
                                } else {
 
2185
                                        if (curtxbw_40mhz)
 
2186
                                                ratr_bitmap &= 0x0f8ff015;
 
2187
                                        else
 
2188
                                                ratr_bitmap &= 0x0f8ff005;
 
2189
                                }
 
2190
                        }
 
2191
                }
 
2192
 
 
2193
                if ((curtxbw_40mhz && curshortgi_40mhz) ||
 
2194
                    (!curtxbw_40mhz && curshortgi_20mhz)) {
 
2195
                        if (macid == 0)
 
2196
                                shortgi = true;
 
2197
                        else if (macid == 1)
 
2198
                                shortgi = false;
 
2199
                }
 
2200
                break;
 
2201
        default:
 
2202
                band |= (WIRELESS_11N | WIRELESS_11G | WIRELESS_11B);
 
2203
                ratr_index = RATR_INX_WIRELESS_NGB;
 
2204
 
 
2205
                if (rtlphy->rf_type == RF_1T2R)
 
2206
                        ratr_bitmap &= 0x000ff0ff;
 
2207
                else
 
2208
                        ratr_bitmap &= 0x0f8ff0ff;
 
2209
                break;
 
2210
        }
 
2211
 
 
2212
        if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT)
 
2213
                ratr_bitmap &= 0x0FFFFFFF;
 
2214
        else if (rtlpriv->rtlhal.version == VERSION_8192S_ACUT)
 
2215
                ratr_bitmap &= 0x0FFFFFF0;
 
2216
 
 
2217
        if (shortgi) {
 
2218
                ratr_bitmap |= 0x10000000;
 
2219
                /* Get MAX MCS available. */
 
2220
                ratr_value = (ratr_bitmap >> 12);
 
2221
                for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
 
2222
                        if ((1 << shortgi_rate) & ratr_value)
 
2223
                                break;
 
2224
                }
 
2225
 
 
2226
                shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
 
2227
                        (shortgi_rate << 4) | (shortgi_rate);
 
2228
                rtl_write_byte(rtlpriv, SG_RATE, shortgi_rate);
 
2229
        }
 
2230
 
 
2231
        mask |= (bmulticast ? 1 : 0) << 9 | (macid & 0x1f) << 4 | (band & 0xf);
 
2232
 
 
2233
        RT_TRACE(rtlpriv, COMP_RATR, DBG_TRACE, ("mask = %x, bitmap = %x\n",
 
2234
                        mask, ratr_bitmap));
 
2235
        rtl_write_dword(rtlpriv, 0x2c4, ratr_bitmap);
 
2236
        rtl_write_dword(rtlpriv, WFM5, (FW_RA_UPDATE_MASK | (mask << 8)));
 
2237
 
 
2238
        if (macid != 0)
 
2239
                sta_entry->ratr_index = ratr_index;
 
2240
}
 
2241
 
 
2242
void rtl92se_update_hal_rate_tbl(struct ieee80211_hw *hw,
 
2243
                struct ieee80211_sta *sta, u8 rssi_level)
 
2244
{
 
2245
        struct rtl_priv *rtlpriv = rtl_priv(hw);
 
2246
 
 
2247
        if (rtlpriv->dm.useramask)
 
2248
                rtl92se_update_hal_rate_mask(hw, sta, rssi_level);
 
2249
        else
 
2250
                rtl92se_update_hal_rate_table(hw, sta);
 
2251
}
 
2252
 
 
2253
void rtl92se_update_channel_access_setting(struct ieee80211_hw *hw)
 
2254
{
 
2255
        struct rtl_priv *rtlpriv = rtl_priv(hw);
 
2256
        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 
2257
        u16 sifs_timer;
 
2258
 
 
2259
        rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
 
2260
                                      (u8 *)&mac->slot_time);
 
2261
        sifs_timer = 0x0e0e;
 
2262
        rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
 
2263
 
 
2264
}
 
2265
 
 
2266
/* this ifunction is for RFKILL, it's different with windows,
 
2267
 * because UI will disable wireless when GPIO Radio Off.
 
2268
 * And here we not check or Disable/Enable ASPM like windows*/
 
2269
bool rtl92se_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
 
2270
{
 
2271
        struct rtl_priv *rtlpriv = rtl_priv(hw);
 
2272
        struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 
2273
        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 
2274
        enum rf_pwrstate rfpwr_toset, cur_rfstate;
 
2275
        unsigned long flag = 0;
 
2276
        bool actuallyset = false;
 
2277
        bool turnonbypowerdomain = false;
 
2278
 
 
2279
        /* just 8191se can check gpio before firstup, 92c/92d have fixed it */
 
2280
        if ((rtlpci->up_first_time == 1) || (rtlpci->being_init_adapter))
 
2281
                return false;
 
2282
 
 
2283
        if (ppsc->swrf_processing)
 
2284
                return false;
 
2285
 
 
2286
        spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
 
2287
        if (ppsc->rfchange_inprogress) {
 
2288
                spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
 
2289
                return false;
 
2290
        } else {
 
2291
                ppsc->rfchange_inprogress = true;
 
2292
                spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
 
2293
        }
 
2294
 
 
2295
        cur_rfstate = ppsc->rfpwr_state;
 
2296
 
 
2297
        /* because after _rtl92s_phy_set_rfhalt, all power
 
2298
         * closed, so we must open some power for GPIO check,
 
2299
         * or we will always check GPIO RFOFF here,
 
2300
         * And we should close power after GPIO check */
 
2301
        if (RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
 
2302
                _rtl92se_power_domain_init(hw);
 
2303
                turnonbypowerdomain = true;
 
2304
        }
 
2305
 
 
2306
        rfpwr_toset = _rtl92se_rf_onoff_detect(hw);
 
2307
 
 
2308
        if ((ppsc->hwradiooff == true) && (rfpwr_toset == ERFON)) {
 
2309
                RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
 
2310
                         ("RFKILL-HW Radio ON, RF ON\n"));
 
2311
 
 
2312
                rfpwr_toset = ERFON;
 
2313
                ppsc->hwradiooff = false;
 
2314
                actuallyset = true;
 
2315
        } else if ((ppsc->hwradiooff == false) && (rfpwr_toset == ERFOFF)) {
 
2316
                RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
 
2317
                         ("RFKILL-HW Radio OFF, RF OFF\n"));
 
2318
 
 
2319
                rfpwr_toset = ERFOFF;
 
2320
                ppsc->hwradiooff = true;
 
2321
                actuallyset = true;
 
2322
        }
 
2323
 
 
2324
        if (actuallyset) {
 
2325
                spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
 
2326
                ppsc->rfchange_inprogress = false;
 
2327
                spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
 
2328
 
 
2329
        /* this not include ifconfig wlan0 down case */
 
2330
        /* } else if (rfpwr_toset == ERFOFF || cur_rfstate == ERFOFF) { */
 
2331
        } else {
 
2332
                /* because power_domain_init may be happen when
 
2333
                 * _rtl92s_phy_set_rfhalt, this will open some powers
 
2334
                 * and cause current increasing about 40 mA for ips,
 
2335
                 * rfoff and ifconfig down, so we set
 
2336
                 * _rtl92s_phy_set_rfhalt again here */
 
2337
                if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC &&
 
2338
                        turnonbypowerdomain) {
 
2339
                        _rtl92s_phy_set_rfhalt(hw);
 
2340
                        RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
 
2341
                }
 
2342
 
 
2343
                spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
 
2344
                ppsc->rfchange_inprogress = false;
 
2345
                spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
 
2346
        }
 
2347
 
 
2348
        *valid = 1;
 
2349
        return !ppsc->hwradiooff;
 
2350
 
 
2351
}
 
2352
 
 
2353
/* Is_wepkey just used for WEP used as group & pairwise key
 
2354
 * if pairwise is AES ang group is WEP Is_wepkey == false.*/
 
2355
void rtl92se_set_key(struct ieee80211_hw *hw, u32 key_index, u8 *p_macaddr,
 
2356
        bool is_group, u8 enc_algo, bool is_wepkey, bool clear_all)
 
2357
{
 
2358
        struct rtl_priv *rtlpriv = rtl_priv(hw);
 
2359
        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 
2360
        struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 
2361
        u8 *macaddr = p_macaddr;
 
2362
 
 
2363
        u32 entry_id = 0;
 
2364
        bool is_pairwise = false;
 
2365
 
 
2366
        static u8 cam_const_addr[4][6] = {
 
2367
                {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 
2368
                {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
 
2369
                {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
 
2370
                {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
 
2371
        };
 
2372
        static u8 cam_const_broad[] = {
 
2373
                0xff, 0xff, 0xff, 0xff, 0xff, 0xff
 
2374
        };
 
2375
 
 
2376
        if (clear_all) {
 
2377
                u8 idx = 0;
 
2378
                u8 cam_offset = 0;
 
2379
                u8 clear_number = 5;
 
2380
 
 
2381
                RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, ("clear_all\n"));
 
2382
 
 
2383
                for (idx = 0; idx < clear_number; idx++) {
 
2384
                        rtl_cam_mark_invalid(hw, cam_offset + idx);
 
2385
                        rtl_cam_empty_entry(hw, cam_offset + idx);
 
2386
 
 
2387
                        if (idx < 5) {
 
2388
                                memset(rtlpriv->sec.key_buf[idx], 0,
 
2389
                                       MAX_KEY_LEN);
 
2390
                                rtlpriv->sec.key_len[idx] = 0;
 
2391
                        }
 
2392
                }
 
2393
 
 
2394
        } else {
 
2395
                switch (enc_algo) {
 
2396
                case WEP40_ENCRYPTION:
 
2397
                        enc_algo = CAM_WEP40;
 
2398
                        break;
 
2399
                case WEP104_ENCRYPTION:
 
2400
                        enc_algo = CAM_WEP104;
 
2401
                        break;
 
2402
                case TKIP_ENCRYPTION:
 
2403
                        enc_algo = CAM_TKIP;
 
2404
                        break;
 
2405
                case AESCCMP_ENCRYPTION:
 
2406
                        enc_algo = CAM_AES;
 
2407
                        break;
 
2408
                default:
 
2409
                        RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 
2410
                                        ("switch case not process\n"));
 
2411
                        enc_algo = CAM_TKIP;
 
2412
                        break;
 
2413
                }
 
2414
 
 
2415
                if (is_wepkey || rtlpriv->sec.use_defaultkey) {
 
2416
                        macaddr = cam_const_addr[key_index];
 
2417
                        entry_id = key_index;
 
2418
                } else {
 
2419
                        if (is_group) {
 
2420
                                macaddr = cam_const_broad;
 
2421
                                entry_id = key_index;
 
2422
                        } else {
 
2423
                                if (mac->opmode == NL80211_IFTYPE_AP) {
 
2424
                                        entry_id = rtl_cam_get_free_entry(hw,
 
2425
                                                                 p_macaddr);
 
2426
                                        if (entry_id >=  TOTAL_CAM_ENTRY) {
 
2427
                                                RT_TRACE(rtlpriv,
 
2428
                                                   COMP_SEC, DBG_EMERG,
 
2429
                                                   ("Can not find free hw"
 
2430
                                                   " security cam entry\n"));
 
2431
                                                return;
 
2432
                                        }
 
2433
                                } else {
 
2434
                                        entry_id = CAM_PAIRWISE_KEY_POSITION;
 
2435
                                }
 
2436
 
 
2437
                                key_index = PAIRWISE_KEYIDX;
 
2438
                                is_pairwise = true;
 
2439
                        }
 
2440
                }
 
2441
 
 
2442
                if (rtlpriv->sec.key_len[key_index] == 0) {
 
2443
                        RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
 
2444
                                 ("delete one entry, entry_id is %d\n",
 
2445
                                 entry_id));
 
2446
                        if (mac->opmode == NL80211_IFTYPE_AP)
 
2447
                                rtl_cam_del_entry(hw, p_macaddr);
 
2448
                        rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
 
2449
                } else {
 
2450
                        RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
 
2451
                                 ("The insert KEY length is %d\n",
 
2452
                                  rtlpriv->sec.key_len[PAIRWISE_KEYIDX]));
 
2453
                        RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
 
2454
                                 ("The insert KEY  is %x %x\n",
 
2455
                                  rtlpriv->sec.key_buf[0][0],
 
2456
                                  rtlpriv->sec.key_buf[0][1]));
 
2457
 
 
2458
                        RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
 
2459
                                 ("add one entry\n"));
 
2460
                        if (is_pairwise) {
 
2461
                                RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
 
2462
                                      "Pairwiase Key content :",
 
2463
                                       rtlpriv->sec.pairwise_key,
 
2464
                                       rtlpriv->sec.key_len[PAIRWISE_KEYIDX]);
 
2465
 
 
2466
                                RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
 
2467
                                         ("set Pairwiase key\n"));
 
2468
 
 
2469
                                rtl_cam_add_one_entry(hw, macaddr, key_index,
 
2470
                                        entry_id, enc_algo,
 
2471
                                        CAM_CONFIG_NO_USEDK,
 
2472
                                        rtlpriv->sec.key_buf[key_index]);
 
2473
                        } else {
 
2474
                                RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
 
2475
                                         ("set group key\n"));
 
2476
 
 
2477
                                if (mac->opmode == NL80211_IFTYPE_ADHOC) {
 
2478
                                        rtl_cam_add_one_entry(hw,
 
2479
                                                rtlefuse->dev_addr,
 
2480
                                                PAIRWISE_KEYIDX,
 
2481
                                                CAM_PAIRWISE_KEY_POSITION,
 
2482
                                                enc_algo, CAM_CONFIG_NO_USEDK,
 
2483
                                                rtlpriv->sec.key_buf[entry_id]);
 
2484
                                }
 
2485
 
 
2486
                                rtl_cam_add_one_entry(hw, macaddr, key_index,
 
2487
                                              entry_id, enc_algo,
 
2488
                                              CAM_CONFIG_NO_USEDK,
 
2489
                                              rtlpriv->sec.key_buf[entry_id]);
 
2490
                        }
 
2491
 
 
2492
                }
 
2493
        }
 
2494
}
 
2495
 
 
2496
void rtl92se_suspend(struct ieee80211_hw *hw)
 
2497
{
 
2498
        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 
2499
 
 
2500
        rtlpci->up_first_time = true;
 
2501
}
 
2502
 
 
2503
void rtl92se_resume(struct ieee80211_hw *hw)
 
2504
{
 
2505
        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 
2506
        u32 val;
 
2507
 
 
2508
        pci_read_config_dword(rtlpci->pdev, 0x40, &val);
 
2509
        if ((val & 0x0000ff00) != 0)
 
2510
                pci_write_config_dword(rtlpci->pdev, 0x40,
 
2511
                        val & 0xffff00ff);
 
2512
}